2006.237.08:08:55.10;Log Opened: Mark IV Field System Version 9.7.7 2006.237.08:08:55.10;location,TSUKUB32,-140.09,36.10,61.0 2006.237.08:08:55.10;horizon1,0.,5.,360. 2006.237.08:08:55.10;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.237.08:08:55.10;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.237.08:08:55.10;drivev11,330,270,no 2006.237.08:08:55.10;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.237.08:08:55.10;drivev13,15.000,268,10.000,10.000,10.000 2006.237.08:08:55.10;drivev21,330,270,no 2006.237.08:08:55.10;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.237.08:08:55.10;drivev23,15.000,268,10.000,10.000,10.000 2006.237.08:08:55.10;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.237.08:08:55.10;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.237.08:08:55.10;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.237.08:08:55.10;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.237.08:08:55.10;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.237.08:08:55.10;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.237.08:08:55.10;time,-0.364,101.533,rate 2006.237.08:08:55.10;flagr,200 2006.237.08:08:55.10:" K06238 2006 TSUKUB32 T Ts 2006.237.08:08:55.10:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.237.08:08:55.10:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.237.08:08:55.10:" 108 TSUKUB32 14 17400 2006.237.08:08:55.10:" drudg version 050216 compiled under FS 9.7.07 2006.237.08:08:55.10:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.237.08:08:55.10:exper_initi 2006.237.08:08:55.10&exper_initi/proc_library 2006.237.08:08:55.10&exper_initi/sched_initi 2006.237.08:08:55.11:!2006.238.06:29:50 2006.237.08:08:55.11&proc_library/" k06238 tsukub32 ts 2006.237.08:08:55.11&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.237.08:08:55.11&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.237.08:08:55.11&sched_initi/startcheck 2006.237.08:08:55.11&startcheck/sy=check_fsrun.pl & 2006.237.08:08:55.11&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.237.08:09:06.12;cable 2006.237.08:09:06.30/cable/+6.3859E-03 2006.237.08:10:02.44;cablelong 2006.237.08:10:02.50/cablelong/+6.9161E-03 2006.237.08:10:04.84;cablediff 2006.237.08:10:04.84/cablediff/530.2e-6,+ 2006.237.08:11:21.40;cable 2006.237.08:11:21.62/cable/+6.3836E-03 2006.237.08:11:25.49;wx 2006.237.08:11:25.49/wx/27.91,1010.8,68 2006.237.08:11:31.51;"Sky is fine. 2006.237.08:11:34.44;xfe 2006.237.08:11:34.53/xfe/off,on,14.0 2006.237.08:11:42.16;clockoff 2006.237.08:11:42.16&clockoff/"gps-fmout=1p 2006.237.08:11:42.16&clockoff/fmout-gps=1p 2006.237.08:11:43.08/fmout-gps/S +4.41E-07 2006.238.00:22:15.94?ERROR st -97 Trouble decoding pressure data 2006.238.00:22:15.94#wxget#13 0.8 1.8 23.65 971013.9 2006.238.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.238.06:29:50.02:!2006.238.07:19:50 2006.238.07:19:50.00:unstow 2006.238.07:19:50.00&unstow/antenna=e 2006.238.07:19:50.00&unstow/!+10s 2006.238.07:19:50.00&unstow/antenna=m2 2006.238.07:20:02.02:scan_name=238-0730,k06238,60 2006.238.07:20:02.02:source=3c418,203837.03,511912.7,2000.0,ccw 2006.238.07:20:02.02#antcn#PM 1 00019 2005 228 00 22 31 00 2006.238.07:20:02.02#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.238.07:20:02.02#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.238.07:20:02.02#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.238.07:20:02.02#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.238.07:20:02.02#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.238.07:20:03.15:ready_k5 2006.238.07:20:03.15&ready_k5/obsinfo=st 2006.238.07:20:03.15&ready_k5/autoobs=1 2006.238.07:20:03.15&ready_k5/autoobs=2 2006.238.07:20:03.15&ready_k5/autoobs=3 2006.238.07:20:03.15&ready_k5/autoobs=4 2006.238.07:20:03.15&ready_k5/obsinfo 2006.238.07:20:03.15/obsinfo=st/error_log.tmp was not found (or not removed). 2006.238.07:20:03.15#flagr#flagr/antenna,new-source 2006.238.07:20:06.35/autoobs//k5ts1/ autoobs started! 2006.238.07:20:09.49/autoobs//k5ts2/ autoobs started! 2006.238.07:20:12.62/autoobs//k5ts3/ autoobs started! 2006.238.07:20:15.74/autoobs//k5ts4/ autoobs started! 2006.238.07:20:15.77/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:20:15.77:4f8m12a=1 2006.238.07:20:15.77&4f8m12a/xlog=on 2006.238.07:20:15.77&4f8m12a/echo=on 2006.238.07:20:15.77&4f8m12a/pcalon 2006.238.07:20:15.77&4f8m12a/"tpicd=stop 2006.238.07:20:15.77&4f8m12a/vc4f8 2006.238.07:20:15.77&4f8m12a/ifd4f 2006.238.07:20:15.77&4f8m12a/"form=m,16.000,1:2 2006.238.07:20:15.77&4f8m12a/"tpicd 2006.238.07:20:15.77&4f8m12a/echo=off 2006.238.07:20:15.77&4f8m12a/xlog=off 2006.238.07:20:15.77$4f8m12a/echo=on 2006.238.07:20:15.77$4f8m12a/pcalon 2006.238.07:20:15.77&pcalon/"no phase cal control is implemented here 2006.238.07:20:15.77$pcalon/"no phase cal control is implemented here 2006.238.07:20:15.77$4f8m12a/"tpicd=stop 2006.238.07:20:15.77$4f8m12a/vc4f8 2006.238.07:20:15.77&vc4f8/valo=1,532.99 2006.238.07:20:15.77&vc4f8/va=1,8 2006.238.07:20:15.77&vc4f8/valo=2,572.99 2006.238.07:20:15.77&vc4f8/va=2,7 2006.238.07:20:15.77&vc4f8/valo=3,672.99 2006.238.07:20:15.77&vc4f8/va=3,7 2006.238.07:20:15.77&vc4f8/valo=4,832.99 2006.238.07:20:15.77&vc4f8/va=4,7 2006.238.07:20:15.77&vc4f8/valo=5,652.99 2006.238.07:20:15.77&vc4f8/va=5,8 2006.238.07:20:15.77&vc4f8/valo=6,772.99 2006.238.07:20:15.77&vc4f8/va=6,7 2006.238.07:20:15.77&vc4f8/valo=7,832.99 2006.238.07:20:15.77&vc4f8/va=7,7 2006.238.07:20:15.77&vc4f8/valo=8,852.99 2006.238.07:20:15.77&vc4f8/va=8,7 2006.238.07:20:15.77&vc4f8/vblo=1,632.99 2006.238.07:20:15.77&vc4f8/vb=1,4 2006.238.07:20:15.77&vc4f8/vblo=2,640.99 2006.238.07:20:15.77&vc4f8/vb=2,4 2006.238.07:20:15.77&vc4f8/vblo=3,656.99 2006.238.07:20:15.77&vc4f8/vb=3,4 2006.238.07:20:15.77&vc4f8/vblo=4,712.99 2006.238.07:20:15.77&vc4f8/vb=4,4 2006.238.07:20:15.77&vc4f8/vblo=5,744.99 2006.238.07:20:15.77&vc4f8/vb=5,4 2006.238.07:20:15.77&vc4f8/vblo=6,752.99 2006.238.07:20:15.77&vc4f8/vb=6,4 2006.238.07:20:15.77&vc4f8/vabw=wide 2006.238.07:20:15.77&vc4f8/vbbw=wide 2006.238.07:20:15.77$vc4f8/valo=1,532.99 2006.238.07:20:15.78#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.07:20:15.78#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.07:20:15.78#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:15.78#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:20:15.78#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:20:15.78#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:20:15.78#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:20:15.78#ibcon#first serial, iclass 15, count 0 2006.238.07:20:15.78#ibcon#enter sib2, iclass 15, count 0 2006.238.07:20:15.78#ibcon#flushed, iclass 15, count 0 2006.238.07:20:15.78#ibcon#about to write, iclass 15, count 0 2006.238.07:20:15.78#ibcon#wrote, iclass 15, count 0 2006.238.07:20:15.78#ibcon#about to read 3, iclass 15, count 0 2006.238.07:20:15.81#ibcon#read 3, iclass 15, count 0 2006.238.07:20:15.81#ibcon#about to read 4, iclass 15, count 0 2006.238.07:20:15.81#ibcon#read 4, iclass 15, count 0 2006.238.07:20:15.81#ibcon#about to read 5, iclass 15, count 0 2006.238.07:20:15.81#ibcon#read 5, iclass 15, count 0 2006.238.07:20:15.81#ibcon#about to read 6, iclass 15, count 0 2006.238.07:20:15.81#ibcon#read 6, iclass 15, count 0 2006.238.07:20:15.81#ibcon#end of sib2, iclass 15, count 0 2006.238.07:20:15.81#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:20:15.81#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:20:15.81#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:20:15.81#ibcon#*before write, iclass 15, count 0 2006.238.07:20:15.81#ibcon#enter sib2, iclass 15, count 0 2006.238.07:20:15.81#ibcon#flushed, iclass 15, count 0 2006.238.07:20:15.81#ibcon#about to write, iclass 15, count 0 2006.238.07:20:15.81#ibcon#wrote, iclass 15, count 0 2006.238.07:20:15.81#ibcon#about to read 3, iclass 15, count 0 2006.238.07:20:15.87#ibcon#read 3, iclass 15, count 0 2006.238.07:20:15.87#ibcon#about to read 4, iclass 15, count 0 2006.238.07:20:15.87#ibcon#read 4, iclass 15, count 0 2006.238.07:20:15.87#ibcon#about to read 5, iclass 15, count 0 2006.238.07:20:15.87#ibcon#read 5, iclass 15, count 0 2006.238.07:20:15.87#ibcon#about to read 6, iclass 15, count 0 2006.238.07:20:15.87#ibcon#read 6, iclass 15, count 0 2006.238.07:20:15.87#ibcon#end of sib2, iclass 15, count 0 2006.238.07:20:15.87#ibcon#*after write, iclass 15, count 0 2006.238.07:20:15.87#ibcon#*before return 0, iclass 15, count 0 2006.238.07:20:15.87#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:20:15.87#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:20:15.87#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:20:15.87#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:20:15.87$vc4f8/va=1,8 2006.238.07:20:15.87#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.07:20:15.88#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.07:20:15.88#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:15.88#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:20:15.88#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:20:15.88#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:20:15.88#ibcon#enter wrdev, iclass 17, count 2 2006.238.07:20:15.88#ibcon#first serial, iclass 17, count 2 2006.238.07:20:15.88#ibcon#enter sib2, iclass 17, count 2 2006.238.07:20:15.88#ibcon#flushed, iclass 17, count 2 2006.238.07:20:15.88#ibcon#about to write, iclass 17, count 2 2006.238.07:20:15.88#ibcon#wrote, iclass 17, count 2 2006.238.07:20:15.88#ibcon#about to read 3, iclass 17, count 2 2006.238.07:20:15.89#ibcon#read 3, iclass 17, count 2 2006.238.07:20:15.89#ibcon#about to read 4, iclass 17, count 2 2006.238.07:20:15.89#ibcon#read 4, iclass 17, count 2 2006.238.07:20:15.89#ibcon#about to read 5, iclass 17, count 2 2006.238.07:20:15.89#ibcon#read 5, iclass 17, count 2 2006.238.07:20:15.89#ibcon#about to read 6, iclass 17, count 2 2006.238.07:20:15.89#ibcon#read 6, iclass 17, count 2 2006.238.07:20:15.89#ibcon#end of sib2, iclass 17, count 2 2006.238.07:20:15.89#ibcon#*mode == 0, iclass 17, count 2 2006.238.07:20:15.89#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.07:20:15.89#ibcon#[25=AT01-08\r\n] 2006.238.07:20:15.89#ibcon#*before write, iclass 17, count 2 2006.238.07:20:15.89#ibcon#enter sib2, iclass 17, count 2 2006.238.07:20:15.89#ibcon#flushed, iclass 17, count 2 2006.238.07:20:15.89#ibcon#about to write, iclass 17, count 2 2006.238.07:20:15.89#ibcon#wrote, iclass 17, count 2 2006.238.07:20:15.89#ibcon#about to read 3, iclass 17, count 2 2006.238.07:20:15.92#ibcon#read 3, iclass 17, count 2 2006.238.07:20:15.92#ibcon#about to read 4, iclass 17, count 2 2006.238.07:20:15.92#ibcon#read 4, iclass 17, count 2 2006.238.07:20:15.92#ibcon#about to read 5, iclass 17, count 2 2006.238.07:20:15.92#ibcon#read 5, iclass 17, count 2 2006.238.07:20:15.92#ibcon#about to read 6, iclass 17, count 2 2006.238.07:20:15.92#ibcon#read 6, iclass 17, count 2 2006.238.07:20:15.92#ibcon#end of sib2, iclass 17, count 2 2006.238.07:20:15.92#ibcon#*after write, iclass 17, count 2 2006.238.07:20:15.92#ibcon#*before return 0, iclass 17, count 2 2006.238.07:20:15.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:20:15.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:20:15.92#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.07:20:15.92#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:15.92#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:20:16.04#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:20:16.04#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:20:16.04#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:20:16.04#ibcon#first serial, iclass 17, count 0 2006.238.07:20:16.04#ibcon#enter sib2, iclass 17, count 0 2006.238.07:20:16.04#ibcon#flushed, iclass 17, count 0 2006.238.07:20:16.04#ibcon#about to write, iclass 17, count 0 2006.238.07:20:16.04#ibcon#wrote, iclass 17, count 0 2006.238.07:20:16.04#ibcon#about to read 3, iclass 17, count 0 2006.238.07:20:16.06#ibcon#read 3, iclass 17, count 0 2006.238.07:20:16.06#ibcon#about to read 4, iclass 17, count 0 2006.238.07:20:16.06#ibcon#read 4, iclass 17, count 0 2006.238.07:20:16.06#ibcon#about to read 5, iclass 17, count 0 2006.238.07:20:16.06#ibcon#read 5, iclass 17, count 0 2006.238.07:20:16.06#ibcon#about to read 6, iclass 17, count 0 2006.238.07:20:16.06#ibcon#read 6, iclass 17, count 0 2006.238.07:20:16.06#ibcon#end of sib2, iclass 17, count 0 2006.238.07:20:16.06#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:20:16.06#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:20:16.06#ibcon#[25=USB\r\n] 2006.238.07:20:16.06#ibcon#*before write, iclass 17, count 0 2006.238.07:20:16.06#ibcon#enter sib2, iclass 17, count 0 2006.238.07:20:16.06#ibcon#flushed, iclass 17, count 0 2006.238.07:20:16.06#ibcon#about to write, iclass 17, count 0 2006.238.07:20:16.06#ibcon#wrote, iclass 17, count 0 2006.238.07:20:16.06#ibcon#about to read 3, iclass 17, count 0 2006.238.07:20:16.09#ibcon#read 3, iclass 17, count 0 2006.238.07:20:16.09#ibcon#about to read 4, iclass 17, count 0 2006.238.07:20:16.09#ibcon#read 4, iclass 17, count 0 2006.238.07:20:16.09#ibcon#about to read 5, iclass 17, count 0 2006.238.07:20:16.09#ibcon#read 5, iclass 17, count 0 2006.238.07:20:16.09#ibcon#about to read 6, iclass 17, count 0 2006.238.07:20:16.09#ibcon#read 6, iclass 17, count 0 2006.238.07:20:16.09#ibcon#end of sib2, iclass 17, count 0 2006.238.07:20:16.09#ibcon#*after write, iclass 17, count 0 2006.238.07:20:16.09#ibcon#*before return 0, iclass 17, count 0 2006.238.07:20:16.09#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:20:16.09#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:20:16.09#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:20:16.09#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:20:16.09$vc4f8/valo=2,572.99 2006.238.07:20:16.10#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.07:20:16.10#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.07:20:16.10#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:16.10#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:20:16.10#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:20:16.10#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:20:16.10#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:20:16.10#ibcon#first serial, iclass 19, count 0 2006.238.07:20:16.10#ibcon#enter sib2, iclass 19, count 0 2006.238.07:20:16.10#ibcon#flushed, iclass 19, count 0 2006.238.07:20:16.10#ibcon#about to write, iclass 19, count 0 2006.238.07:20:16.10#ibcon#wrote, iclass 19, count 0 2006.238.07:20:16.10#ibcon#about to read 3, iclass 19, count 0 2006.238.07:20:16.11#ibcon#read 3, iclass 19, count 0 2006.238.07:20:16.11#ibcon#about to read 4, iclass 19, count 0 2006.238.07:20:16.11#ibcon#read 4, iclass 19, count 0 2006.238.07:20:16.11#ibcon#about to read 5, iclass 19, count 0 2006.238.07:20:16.11#ibcon#read 5, iclass 19, count 0 2006.238.07:20:16.11#ibcon#about to read 6, iclass 19, count 0 2006.238.07:20:16.11#ibcon#read 6, iclass 19, count 0 2006.238.07:20:16.11#ibcon#end of sib2, iclass 19, count 0 2006.238.07:20:16.11#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:20:16.11#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:20:16.11#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:20:16.11#ibcon#*before write, iclass 19, count 0 2006.238.07:20:16.11#ibcon#enter sib2, iclass 19, count 0 2006.238.07:20:16.11#ibcon#flushed, iclass 19, count 0 2006.238.07:20:16.11#ibcon#about to write, iclass 19, count 0 2006.238.07:20:16.11#ibcon#wrote, iclass 19, count 0 2006.238.07:20:16.11#ibcon#about to read 3, iclass 19, count 0 2006.238.07:20:16.15#ibcon#read 3, iclass 19, count 0 2006.238.07:20:16.15#ibcon#about to read 4, iclass 19, count 0 2006.238.07:20:16.15#ibcon#read 4, iclass 19, count 0 2006.238.07:20:16.15#ibcon#about to read 5, iclass 19, count 0 2006.238.07:20:16.15#ibcon#read 5, iclass 19, count 0 2006.238.07:20:16.15#ibcon#about to read 6, iclass 19, count 0 2006.238.07:20:16.15#ibcon#read 6, iclass 19, count 0 2006.238.07:20:16.15#ibcon#end of sib2, iclass 19, count 0 2006.238.07:20:16.15#ibcon#*after write, iclass 19, count 0 2006.238.07:20:16.15#ibcon#*before return 0, iclass 19, count 0 2006.238.07:20:16.15#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:20:16.15#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:20:16.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:20:16.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:20:16.15$vc4f8/va=2,7 2006.238.07:20:16.16#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.07:20:16.16#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.07:20:16.16#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:16.16#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:20:16.21#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:20:16.21#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:20:16.21#ibcon#enter wrdev, iclass 21, count 2 2006.238.07:20:16.21#ibcon#first serial, iclass 21, count 2 2006.238.07:20:16.21#ibcon#enter sib2, iclass 21, count 2 2006.238.07:20:16.21#ibcon#flushed, iclass 21, count 2 2006.238.07:20:16.21#ibcon#about to write, iclass 21, count 2 2006.238.07:20:16.21#ibcon#wrote, iclass 21, count 2 2006.238.07:20:16.21#ibcon#about to read 3, iclass 21, count 2 2006.238.07:20:16.22#ibcon#read 3, iclass 21, count 2 2006.238.07:20:16.22#ibcon#about to read 4, iclass 21, count 2 2006.238.07:20:16.22#ibcon#read 4, iclass 21, count 2 2006.238.07:20:16.22#ibcon#about to read 5, iclass 21, count 2 2006.238.07:20:16.22#ibcon#read 5, iclass 21, count 2 2006.238.07:20:16.22#ibcon#about to read 6, iclass 21, count 2 2006.238.07:20:16.22#ibcon#read 6, iclass 21, count 2 2006.238.07:20:16.22#ibcon#end of sib2, iclass 21, count 2 2006.238.07:20:16.22#ibcon#*mode == 0, iclass 21, count 2 2006.238.07:20:16.22#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.07:20:16.22#ibcon#[25=AT02-07\r\n] 2006.238.07:20:16.22#ibcon#*before write, iclass 21, count 2 2006.238.07:20:16.22#ibcon#enter sib2, iclass 21, count 2 2006.238.07:20:16.23#ibcon#flushed, iclass 21, count 2 2006.238.07:20:16.23#ibcon#about to write, iclass 21, count 2 2006.238.07:20:16.23#ibcon#wrote, iclass 21, count 2 2006.238.07:20:16.23#ibcon#about to read 3, iclass 21, count 2 2006.238.07:20:16.25#ibcon#read 3, iclass 21, count 2 2006.238.07:20:16.25#ibcon#about to read 4, iclass 21, count 2 2006.238.07:20:16.25#ibcon#read 4, iclass 21, count 2 2006.238.07:20:16.25#ibcon#about to read 5, iclass 21, count 2 2006.238.07:20:16.25#ibcon#read 5, iclass 21, count 2 2006.238.07:20:16.25#ibcon#about to read 6, iclass 21, count 2 2006.238.07:20:16.25#ibcon#read 6, iclass 21, count 2 2006.238.07:20:16.25#ibcon#end of sib2, iclass 21, count 2 2006.238.07:20:16.25#ibcon#*after write, iclass 21, count 2 2006.238.07:20:16.25#ibcon#*before return 0, iclass 21, count 2 2006.238.07:20:16.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:20:16.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:20:16.25#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.07:20:16.25#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:16.25#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:20:16.37#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:20:16.37#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:20:16.37#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:20:16.37#ibcon#first serial, iclass 21, count 0 2006.238.07:20:16.37#ibcon#enter sib2, iclass 21, count 0 2006.238.07:20:16.37#ibcon#flushed, iclass 21, count 0 2006.238.07:20:16.37#ibcon#about to write, iclass 21, count 0 2006.238.07:20:16.37#ibcon#wrote, iclass 21, count 0 2006.238.07:20:16.37#ibcon#about to read 3, iclass 21, count 0 2006.238.07:20:16.39#ibcon#read 3, iclass 21, count 0 2006.238.07:20:16.39#ibcon#about to read 4, iclass 21, count 0 2006.238.07:20:16.39#ibcon#read 4, iclass 21, count 0 2006.238.07:20:16.39#ibcon#about to read 5, iclass 21, count 0 2006.238.07:20:16.39#ibcon#read 5, iclass 21, count 0 2006.238.07:20:16.39#ibcon#about to read 6, iclass 21, count 0 2006.238.07:20:16.39#ibcon#read 6, iclass 21, count 0 2006.238.07:20:16.39#ibcon#end of sib2, iclass 21, count 0 2006.238.07:20:16.39#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:20:16.39#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:20:16.39#ibcon#[25=USB\r\n] 2006.238.07:20:16.39#ibcon#*before write, iclass 21, count 0 2006.238.07:20:16.39#ibcon#enter sib2, iclass 21, count 0 2006.238.07:20:16.39#ibcon#flushed, iclass 21, count 0 2006.238.07:20:16.39#ibcon#about to write, iclass 21, count 0 2006.238.07:20:16.39#ibcon#wrote, iclass 21, count 0 2006.238.07:20:16.39#ibcon#about to read 3, iclass 21, count 0 2006.238.07:20:16.42#ibcon#read 3, iclass 21, count 0 2006.238.07:20:16.42#ibcon#about to read 4, iclass 21, count 0 2006.238.07:20:16.42#ibcon#read 4, iclass 21, count 0 2006.238.07:20:16.42#ibcon#about to read 5, iclass 21, count 0 2006.238.07:20:16.42#ibcon#read 5, iclass 21, count 0 2006.238.07:20:16.42#ibcon#about to read 6, iclass 21, count 0 2006.238.07:20:16.42#ibcon#read 6, iclass 21, count 0 2006.238.07:20:16.42#ibcon#end of sib2, iclass 21, count 0 2006.238.07:20:16.42#ibcon#*after write, iclass 21, count 0 2006.238.07:20:16.42#ibcon#*before return 0, iclass 21, count 0 2006.238.07:20:16.42#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:20:16.42#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:20:16.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:20:16.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:20:16.42$vc4f8/valo=3,672.99 2006.238.07:20:16.43#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:20:16.43#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:20:16.43#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:16.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:20:16.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:20:16.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:20:16.43#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:20:16.43#ibcon#first serial, iclass 23, count 0 2006.238.07:20:16.43#ibcon#enter sib2, iclass 23, count 0 2006.238.07:20:16.43#ibcon#flushed, iclass 23, count 0 2006.238.07:20:16.43#ibcon#about to write, iclass 23, count 0 2006.238.07:20:16.43#ibcon#wrote, iclass 23, count 0 2006.238.07:20:16.43#ibcon#about to read 3, iclass 23, count 0 2006.238.07:20:16.44#ibcon#read 3, iclass 23, count 0 2006.238.07:20:16.44#ibcon#about to read 4, iclass 23, count 0 2006.238.07:20:16.44#ibcon#read 4, iclass 23, count 0 2006.238.07:20:16.44#ibcon#about to read 5, iclass 23, count 0 2006.238.07:20:16.44#ibcon#read 5, iclass 23, count 0 2006.238.07:20:16.44#ibcon#about to read 6, iclass 23, count 0 2006.238.07:20:16.44#ibcon#read 6, iclass 23, count 0 2006.238.07:20:16.44#ibcon#end of sib2, iclass 23, count 0 2006.238.07:20:16.44#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:20:16.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:20:16.44#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:20:16.44#ibcon#*before write, iclass 23, count 0 2006.238.07:20:16.44#ibcon#enter sib2, iclass 23, count 0 2006.238.07:20:16.44#ibcon#flushed, iclass 23, count 0 2006.238.07:20:16.44#ibcon#about to write, iclass 23, count 0 2006.238.07:20:16.44#ibcon#wrote, iclass 23, count 0 2006.238.07:20:16.44#ibcon#about to read 3, iclass 23, count 0 2006.238.07:20:16.48#ibcon#read 3, iclass 23, count 0 2006.238.07:20:16.48#ibcon#about to read 4, iclass 23, count 0 2006.238.07:20:16.48#ibcon#read 4, iclass 23, count 0 2006.238.07:20:16.48#ibcon#about to read 5, iclass 23, count 0 2006.238.07:20:16.48#ibcon#read 5, iclass 23, count 0 2006.238.07:20:16.48#ibcon#about to read 6, iclass 23, count 0 2006.238.07:20:16.48#ibcon#read 6, iclass 23, count 0 2006.238.07:20:16.48#ibcon#end of sib2, iclass 23, count 0 2006.238.07:20:16.48#ibcon#*after write, iclass 23, count 0 2006.238.07:20:16.48#ibcon#*before return 0, iclass 23, count 0 2006.238.07:20:16.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:20:16.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:20:16.48#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:20:16.48#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:20:16.48$vc4f8/va=3,7 2006.238.07:20:16.49#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.07:20:16.49#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.07:20:16.49#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:16.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:20:16.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:20:16.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:20:16.54#ibcon#enter wrdev, iclass 25, count 2 2006.238.07:20:16.54#ibcon#first serial, iclass 25, count 2 2006.238.07:20:16.54#ibcon#enter sib2, iclass 25, count 2 2006.238.07:20:16.54#ibcon#flushed, iclass 25, count 2 2006.238.07:20:16.54#ibcon#about to write, iclass 25, count 2 2006.238.07:20:16.54#ibcon#wrote, iclass 25, count 2 2006.238.07:20:16.54#ibcon#about to read 3, iclass 25, count 2 2006.238.07:20:16.55#ibcon#read 3, iclass 25, count 2 2006.238.07:20:16.55#ibcon#about to read 4, iclass 25, count 2 2006.238.07:20:16.55#ibcon#read 4, iclass 25, count 2 2006.238.07:20:16.55#ibcon#about to read 5, iclass 25, count 2 2006.238.07:20:16.55#ibcon#read 5, iclass 25, count 2 2006.238.07:20:16.55#ibcon#about to read 6, iclass 25, count 2 2006.238.07:20:16.55#ibcon#read 6, iclass 25, count 2 2006.238.07:20:16.55#ibcon#end of sib2, iclass 25, count 2 2006.238.07:20:16.55#ibcon#*mode == 0, iclass 25, count 2 2006.238.07:20:16.55#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.07:20:16.55#ibcon#[25=AT03-07\r\n] 2006.238.07:20:16.55#ibcon#*before write, iclass 25, count 2 2006.238.07:20:16.55#ibcon#enter sib2, iclass 25, count 2 2006.238.07:20:16.55#ibcon#flushed, iclass 25, count 2 2006.238.07:20:16.55#ibcon#about to write, iclass 25, count 2 2006.238.07:20:16.55#ibcon#wrote, iclass 25, count 2 2006.238.07:20:16.55#ibcon#about to read 3, iclass 25, count 2 2006.238.07:20:16.58#ibcon#read 3, iclass 25, count 2 2006.238.07:20:16.58#ibcon#about to read 4, iclass 25, count 2 2006.238.07:20:16.58#ibcon#read 4, iclass 25, count 2 2006.238.07:20:16.58#ibcon#about to read 5, iclass 25, count 2 2006.238.07:20:16.58#ibcon#read 5, iclass 25, count 2 2006.238.07:20:16.58#ibcon#about to read 6, iclass 25, count 2 2006.238.07:20:16.58#ibcon#read 6, iclass 25, count 2 2006.238.07:20:16.58#ibcon#end of sib2, iclass 25, count 2 2006.238.07:20:16.58#ibcon#*after write, iclass 25, count 2 2006.238.07:20:16.58#ibcon#*before return 0, iclass 25, count 2 2006.238.07:20:16.58#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:20:16.58#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:20:16.58#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.07:20:16.58#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:16.58#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:20:16.70#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:20:16.70#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:20:16.70#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:20:16.70#ibcon#first serial, iclass 25, count 0 2006.238.07:20:16.70#ibcon#enter sib2, iclass 25, count 0 2006.238.07:20:16.70#ibcon#flushed, iclass 25, count 0 2006.238.07:20:16.70#ibcon#about to write, iclass 25, count 0 2006.238.07:20:16.70#ibcon#wrote, iclass 25, count 0 2006.238.07:20:16.70#ibcon#about to read 3, iclass 25, count 0 2006.238.07:20:16.72#ibcon#read 3, iclass 25, count 0 2006.238.07:20:16.72#ibcon#about to read 4, iclass 25, count 0 2006.238.07:20:16.72#ibcon#read 4, iclass 25, count 0 2006.238.07:20:16.72#ibcon#about to read 5, iclass 25, count 0 2006.238.07:20:16.72#ibcon#read 5, iclass 25, count 0 2006.238.07:20:16.72#ibcon#about to read 6, iclass 25, count 0 2006.238.07:20:16.72#ibcon#read 6, iclass 25, count 0 2006.238.07:20:16.72#ibcon#end of sib2, iclass 25, count 0 2006.238.07:20:16.72#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:20:16.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:20:16.72#ibcon#[25=USB\r\n] 2006.238.07:20:16.72#ibcon#*before write, iclass 25, count 0 2006.238.07:20:16.72#ibcon#enter sib2, iclass 25, count 0 2006.238.07:20:16.72#ibcon#flushed, iclass 25, count 0 2006.238.07:20:16.72#ibcon#about to write, iclass 25, count 0 2006.238.07:20:16.72#ibcon#wrote, iclass 25, count 0 2006.238.07:20:16.72#ibcon#about to read 3, iclass 25, count 0 2006.238.07:20:16.75#ibcon#read 3, iclass 25, count 0 2006.238.07:20:16.75#ibcon#about to read 4, iclass 25, count 0 2006.238.07:20:16.75#ibcon#read 4, iclass 25, count 0 2006.238.07:20:16.75#ibcon#about to read 5, iclass 25, count 0 2006.238.07:20:16.75#ibcon#read 5, iclass 25, count 0 2006.238.07:20:16.75#ibcon#about to read 6, iclass 25, count 0 2006.238.07:20:16.75#ibcon#read 6, iclass 25, count 0 2006.238.07:20:16.75#ibcon#end of sib2, iclass 25, count 0 2006.238.07:20:16.75#ibcon#*after write, iclass 25, count 0 2006.238.07:20:16.75#ibcon#*before return 0, iclass 25, count 0 2006.238.07:20:16.75#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:20:16.75#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:20:16.75#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:20:16.75#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:20:16.75$vc4f8/valo=4,832.99 2006.238.07:20:16.76#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:20:16.76#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:20:16.76#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:16.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:20:16.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:20:16.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:20:16.76#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:20:16.76#ibcon#first serial, iclass 27, count 0 2006.238.07:20:16.76#ibcon#enter sib2, iclass 27, count 0 2006.238.07:20:16.76#ibcon#flushed, iclass 27, count 0 2006.238.07:20:16.76#ibcon#about to write, iclass 27, count 0 2006.238.07:20:16.76#ibcon#wrote, iclass 27, count 0 2006.238.07:20:16.76#ibcon#about to read 3, iclass 27, count 0 2006.238.07:20:16.77#ibcon#read 3, iclass 27, count 0 2006.238.07:20:16.77#ibcon#about to read 4, iclass 27, count 0 2006.238.07:20:16.77#ibcon#read 4, iclass 27, count 0 2006.238.07:20:16.77#ibcon#about to read 5, iclass 27, count 0 2006.238.07:20:16.77#ibcon#read 5, iclass 27, count 0 2006.238.07:20:16.77#ibcon#about to read 6, iclass 27, count 0 2006.238.07:20:16.77#ibcon#read 6, iclass 27, count 0 2006.238.07:20:16.77#ibcon#end of sib2, iclass 27, count 0 2006.238.07:20:16.77#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:20:16.77#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:20:16.77#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:20:16.77#ibcon#*before write, iclass 27, count 0 2006.238.07:20:16.77#ibcon#enter sib2, iclass 27, count 0 2006.238.07:20:16.77#ibcon#flushed, iclass 27, count 0 2006.238.07:20:16.77#ibcon#about to write, iclass 27, count 0 2006.238.07:20:16.77#ibcon#wrote, iclass 27, count 0 2006.238.07:20:16.77#ibcon#about to read 3, iclass 27, count 0 2006.238.07:20:16.81#ibcon#read 3, iclass 27, count 0 2006.238.07:20:16.81#ibcon#about to read 4, iclass 27, count 0 2006.238.07:20:16.81#ibcon#read 4, iclass 27, count 0 2006.238.07:20:16.81#ibcon#about to read 5, iclass 27, count 0 2006.238.07:20:16.81#ibcon#read 5, iclass 27, count 0 2006.238.07:20:16.81#ibcon#about to read 6, iclass 27, count 0 2006.238.07:20:16.81#ibcon#read 6, iclass 27, count 0 2006.238.07:20:16.81#ibcon#end of sib2, iclass 27, count 0 2006.238.07:20:16.81#ibcon#*after write, iclass 27, count 0 2006.238.07:20:16.81#ibcon#*before return 0, iclass 27, count 0 2006.238.07:20:16.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:20:16.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:20:16.81#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:20:16.81#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:20:16.81$vc4f8/va=4,7 2006.238.07:20:16.82#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.07:20:16.82#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.07:20:16.82#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:16.82#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:20:16.87#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:20:16.87#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:20:16.87#ibcon#enter wrdev, iclass 29, count 2 2006.238.07:20:16.87#ibcon#first serial, iclass 29, count 2 2006.238.07:20:16.87#ibcon#enter sib2, iclass 29, count 2 2006.238.07:20:16.87#ibcon#flushed, iclass 29, count 2 2006.238.07:20:16.87#ibcon#about to write, iclass 29, count 2 2006.238.07:20:16.87#ibcon#wrote, iclass 29, count 2 2006.238.07:20:16.87#ibcon#about to read 3, iclass 29, count 2 2006.238.07:20:16.88#ibcon#read 3, iclass 29, count 2 2006.238.07:20:16.88#ibcon#about to read 4, iclass 29, count 2 2006.238.07:20:16.88#ibcon#read 4, iclass 29, count 2 2006.238.07:20:16.88#ibcon#about to read 5, iclass 29, count 2 2006.238.07:20:16.88#ibcon#read 5, iclass 29, count 2 2006.238.07:20:16.88#ibcon#about to read 6, iclass 29, count 2 2006.238.07:20:16.88#ibcon#read 6, iclass 29, count 2 2006.238.07:20:16.88#ibcon#end of sib2, iclass 29, count 2 2006.238.07:20:16.88#ibcon#*mode == 0, iclass 29, count 2 2006.238.07:20:16.88#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.07:20:16.88#ibcon#[25=AT04-07\r\n] 2006.238.07:20:16.88#ibcon#*before write, iclass 29, count 2 2006.238.07:20:16.88#ibcon#enter sib2, iclass 29, count 2 2006.238.07:20:16.88#ibcon#flushed, iclass 29, count 2 2006.238.07:20:16.88#ibcon#about to write, iclass 29, count 2 2006.238.07:20:16.88#ibcon#wrote, iclass 29, count 2 2006.238.07:20:16.88#ibcon#about to read 3, iclass 29, count 2 2006.238.07:20:16.91#ibcon#read 3, iclass 29, count 2 2006.238.07:20:16.91#ibcon#about to read 4, iclass 29, count 2 2006.238.07:20:16.91#ibcon#read 4, iclass 29, count 2 2006.238.07:20:16.91#ibcon#about to read 5, iclass 29, count 2 2006.238.07:20:16.91#ibcon#read 5, iclass 29, count 2 2006.238.07:20:16.91#ibcon#about to read 6, iclass 29, count 2 2006.238.07:20:16.91#ibcon#read 6, iclass 29, count 2 2006.238.07:20:16.91#ibcon#end of sib2, iclass 29, count 2 2006.238.07:20:16.91#ibcon#*after write, iclass 29, count 2 2006.238.07:20:16.91#ibcon#*before return 0, iclass 29, count 2 2006.238.07:20:16.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:20:16.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:20:16.91#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.07:20:16.91#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:16.91#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:20:17.03#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:20:17.03#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:20:17.03#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:20:17.03#ibcon#first serial, iclass 29, count 0 2006.238.07:20:17.03#ibcon#enter sib2, iclass 29, count 0 2006.238.07:20:17.03#ibcon#flushed, iclass 29, count 0 2006.238.07:20:17.03#ibcon#about to write, iclass 29, count 0 2006.238.07:20:17.03#ibcon#wrote, iclass 29, count 0 2006.238.07:20:17.03#ibcon#about to read 3, iclass 29, count 0 2006.238.07:20:17.07#ibcon#read 3, iclass 29, count 0 2006.238.07:20:17.07#ibcon#about to read 4, iclass 29, count 0 2006.238.07:20:17.07#ibcon#read 4, iclass 29, count 0 2006.238.07:20:17.07#ibcon#about to read 5, iclass 29, count 0 2006.238.07:20:17.07#ibcon#read 5, iclass 29, count 0 2006.238.07:20:17.07#ibcon#about to read 6, iclass 29, count 0 2006.238.07:20:17.07#ibcon#read 6, iclass 29, count 0 2006.238.07:20:17.07#ibcon#end of sib2, iclass 29, count 0 2006.238.07:20:17.07#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:20:17.07#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:20:17.07#ibcon#[25=USB\r\n] 2006.238.07:20:17.07#ibcon#*before write, iclass 29, count 0 2006.238.07:20:17.07#ibcon#enter sib2, iclass 29, count 0 2006.238.07:20:17.07#ibcon#flushed, iclass 29, count 0 2006.238.07:20:17.07#ibcon#about to write, iclass 29, count 0 2006.238.07:20:17.07#ibcon#wrote, iclass 29, count 0 2006.238.07:20:17.07#ibcon#about to read 3, iclass 29, count 0 2006.238.07:20:17.10#ibcon#read 3, iclass 29, count 0 2006.238.07:20:17.10#ibcon#about to read 4, iclass 29, count 0 2006.238.07:20:17.10#ibcon#read 4, iclass 29, count 0 2006.238.07:20:17.10#ibcon#about to read 5, iclass 29, count 0 2006.238.07:20:17.10#ibcon#read 5, iclass 29, count 0 2006.238.07:20:17.10#ibcon#about to read 6, iclass 29, count 0 2006.238.07:20:17.10#ibcon#read 6, iclass 29, count 0 2006.238.07:20:17.10#ibcon#end of sib2, iclass 29, count 0 2006.238.07:20:17.10#ibcon#*after write, iclass 29, count 0 2006.238.07:20:17.10#ibcon#*before return 0, iclass 29, count 0 2006.238.07:20:17.10#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:20:17.10#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:20:17.10#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:20:17.10#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:20:17.11$vc4f8/valo=5,652.99 2006.238.07:20:17.11#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.07:20:17.11#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.07:20:17.11#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:17.11#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:20:17.11#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:20:17.11#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:20:17.11#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:20:17.11#ibcon#first serial, iclass 31, count 0 2006.238.07:20:17.11#ibcon#enter sib2, iclass 31, count 0 2006.238.07:20:17.11#ibcon#flushed, iclass 31, count 0 2006.238.07:20:17.11#ibcon#about to write, iclass 31, count 0 2006.238.07:20:17.11#ibcon#wrote, iclass 31, count 0 2006.238.07:20:17.11#ibcon#about to read 3, iclass 31, count 0 2006.238.07:20:17.12#ibcon#read 3, iclass 31, count 0 2006.238.07:20:17.12#ibcon#about to read 4, iclass 31, count 0 2006.238.07:20:17.12#ibcon#read 4, iclass 31, count 0 2006.238.07:20:17.12#ibcon#about to read 5, iclass 31, count 0 2006.238.07:20:17.12#ibcon#read 5, iclass 31, count 0 2006.238.07:20:17.12#ibcon#about to read 6, iclass 31, count 0 2006.238.07:20:17.12#ibcon#read 6, iclass 31, count 0 2006.238.07:20:17.12#ibcon#end of sib2, iclass 31, count 0 2006.238.07:20:17.12#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:20:17.12#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:20:17.12#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:20:17.12#ibcon#*before write, iclass 31, count 0 2006.238.07:20:17.12#ibcon#enter sib2, iclass 31, count 0 2006.238.07:20:17.12#ibcon#flushed, iclass 31, count 0 2006.238.07:20:17.12#ibcon#about to write, iclass 31, count 0 2006.238.07:20:17.12#ibcon#wrote, iclass 31, count 0 2006.238.07:20:17.12#ibcon#about to read 3, iclass 31, count 0 2006.238.07:20:17.17#ibcon#read 3, iclass 31, count 0 2006.238.07:20:17.17#ibcon#about to read 4, iclass 31, count 0 2006.238.07:20:17.17#ibcon#read 4, iclass 31, count 0 2006.238.07:20:17.17#ibcon#about to read 5, iclass 31, count 0 2006.238.07:20:17.17#ibcon#read 5, iclass 31, count 0 2006.238.07:20:17.17#ibcon#about to read 6, iclass 31, count 0 2006.238.07:20:17.17#ibcon#read 6, iclass 31, count 0 2006.238.07:20:17.17#ibcon#end of sib2, iclass 31, count 0 2006.238.07:20:17.17#ibcon#*after write, iclass 31, count 0 2006.238.07:20:17.17#ibcon#*before return 0, iclass 31, count 0 2006.238.07:20:17.17#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:20:17.17#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:20:17.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:20:17.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:20:17.17$vc4f8/va=5,8 2006.238.07:20:17.17#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:20:17.17#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:20:17.17#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:17.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:20:17.21#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:20:17.21#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:20:17.21#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:20:17.21#ibcon#first serial, iclass 33, count 2 2006.238.07:20:17.21#ibcon#enter sib2, iclass 33, count 2 2006.238.07:20:17.21#ibcon#flushed, iclass 33, count 2 2006.238.07:20:17.21#ibcon#about to write, iclass 33, count 2 2006.238.07:20:17.21#ibcon#wrote, iclass 33, count 2 2006.238.07:20:17.21#ibcon#about to read 3, iclass 33, count 2 2006.238.07:20:17.23#ibcon#read 3, iclass 33, count 2 2006.238.07:20:17.23#ibcon#about to read 4, iclass 33, count 2 2006.238.07:20:17.23#ibcon#read 4, iclass 33, count 2 2006.238.07:20:17.23#ibcon#about to read 5, iclass 33, count 2 2006.238.07:20:17.23#ibcon#read 5, iclass 33, count 2 2006.238.07:20:17.23#ibcon#about to read 6, iclass 33, count 2 2006.238.07:20:17.23#ibcon#read 6, iclass 33, count 2 2006.238.07:20:17.23#ibcon#end of sib2, iclass 33, count 2 2006.238.07:20:17.23#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:20:17.23#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:20:17.23#ibcon#[25=AT05-08\r\n] 2006.238.07:20:17.23#ibcon#*before write, iclass 33, count 2 2006.238.07:20:17.23#ibcon#enter sib2, iclass 33, count 2 2006.238.07:20:17.23#ibcon#flushed, iclass 33, count 2 2006.238.07:20:17.23#ibcon#about to write, iclass 33, count 2 2006.238.07:20:17.23#ibcon#wrote, iclass 33, count 2 2006.238.07:20:17.23#ibcon#about to read 3, iclass 33, count 2 2006.238.07:20:17.26#ibcon#read 3, iclass 33, count 2 2006.238.07:20:17.26#ibcon#about to read 4, iclass 33, count 2 2006.238.07:20:17.26#ibcon#read 4, iclass 33, count 2 2006.238.07:20:17.26#ibcon#about to read 5, iclass 33, count 2 2006.238.07:20:17.26#ibcon#read 5, iclass 33, count 2 2006.238.07:20:17.26#ibcon#about to read 6, iclass 33, count 2 2006.238.07:20:17.26#ibcon#read 6, iclass 33, count 2 2006.238.07:20:17.26#ibcon#end of sib2, iclass 33, count 2 2006.238.07:20:17.26#ibcon#*after write, iclass 33, count 2 2006.238.07:20:17.26#ibcon#*before return 0, iclass 33, count 2 2006.238.07:20:17.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:20:17.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:20:17.26#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:20:17.26#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:17.26#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:20:17.38#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:20:17.38#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:20:17.38#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:20:17.38#ibcon#first serial, iclass 33, count 0 2006.238.07:20:17.38#ibcon#enter sib2, iclass 33, count 0 2006.238.07:20:17.38#ibcon#flushed, iclass 33, count 0 2006.238.07:20:17.38#ibcon#about to write, iclass 33, count 0 2006.238.07:20:17.38#ibcon#wrote, iclass 33, count 0 2006.238.07:20:17.38#ibcon#about to read 3, iclass 33, count 0 2006.238.07:20:17.40#ibcon#read 3, iclass 33, count 0 2006.238.07:20:17.40#ibcon#about to read 4, iclass 33, count 0 2006.238.07:20:17.40#ibcon#read 4, iclass 33, count 0 2006.238.07:20:17.40#ibcon#about to read 5, iclass 33, count 0 2006.238.07:20:17.40#ibcon#read 5, iclass 33, count 0 2006.238.07:20:17.40#ibcon#about to read 6, iclass 33, count 0 2006.238.07:20:17.40#ibcon#read 6, iclass 33, count 0 2006.238.07:20:17.40#ibcon#end of sib2, iclass 33, count 0 2006.238.07:20:17.40#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:20:17.40#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:20:17.40#ibcon#[25=USB\r\n] 2006.238.07:20:17.40#ibcon#*before write, iclass 33, count 0 2006.238.07:20:17.40#ibcon#enter sib2, iclass 33, count 0 2006.238.07:20:17.40#ibcon#flushed, iclass 33, count 0 2006.238.07:20:17.40#ibcon#about to write, iclass 33, count 0 2006.238.07:20:17.40#ibcon#wrote, iclass 33, count 0 2006.238.07:20:17.40#ibcon#about to read 3, iclass 33, count 0 2006.238.07:20:17.43#ibcon#read 3, iclass 33, count 0 2006.238.07:20:17.43#ibcon#about to read 4, iclass 33, count 0 2006.238.07:20:17.43#ibcon#read 4, iclass 33, count 0 2006.238.07:20:17.43#ibcon#about to read 5, iclass 33, count 0 2006.238.07:20:17.43#ibcon#read 5, iclass 33, count 0 2006.238.07:20:17.43#ibcon#about to read 6, iclass 33, count 0 2006.238.07:20:17.43#ibcon#read 6, iclass 33, count 0 2006.238.07:20:17.43#ibcon#end of sib2, iclass 33, count 0 2006.238.07:20:17.43#ibcon#*after write, iclass 33, count 0 2006.238.07:20:17.43#ibcon#*before return 0, iclass 33, count 0 2006.238.07:20:17.43#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:20:17.43#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:20:17.43#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:20:17.43#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:20:17.43$vc4f8/valo=6,772.99 2006.238.07:20:17.44#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:20:17.44#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:20:17.44#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:17.44#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:20:17.44#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:20:17.44#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:20:17.44#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:20:17.44#ibcon#first serial, iclass 35, count 0 2006.238.07:20:17.44#ibcon#enter sib2, iclass 35, count 0 2006.238.07:20:17.44#ibcon#flushed, iclass 35, count 0 2006.238.07:20:17.44#ibcon#about to write, iclass 35, count 0 2006.238.07:20:17.44#ibcon#wrote, iclass 35, count 0 2006.238.07:20:17.44#ibcon#about to read 3, iclass 35, count 0 2006.238.07:20:17.45#ibcon#read 3, iclass 35, count 0 2006.238.07:20:17.45#ibcon#about to read 4, iclass 35, count 0 2006.238.07:20:17.45#ibcon#read 4, iclass 35, count 0 2006.238.07:20:17.45#ibcon#about to read 5, iclass 35, count 0 2006.238.07:20:17.45#ibcon#read 5, iclass 35, count 0 2006.238.07:20:17.45#ibcon#about to read 6, iclass 35, count 0 2006.238.07:20:17.45#ibcon#read 6, iclass 35, count 0 2006.238.07:20:17.45#ibcon#end of sib2, iclass 35, count 0 2006.238.07:20:17.45#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:20:17.45#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:20:17.45#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:20:17.45#ibcon#*before write, iclass 35, count 0 2006.238.07:20:17.45#ibcon#enter sib2, iclass 35, count 0 2006.238.07:20:17.45#ibcon#flushed, iclass 35, count 0 2006.238.07:20:17.45#ibcon#about to write, iclass 35, count 0 2006.238.07:20:17.45#ibcon#wrote, iclass 35, count 0 2006.238.07:20:17.45#ibcon#about to read 3, iclass 35, count 0 2006.238.07:20:17.50#ibcon#read 3, iclass 35, count 0 2006.238.07:20:17.50#ibcon#about to read 4, iclass 35, count 0 2006.238.07:20:17.50#ibcon#read 4, iclass 35, count 0 2006.238.07:20:17.50#ibcon#about to read 5, iclass 35, count 0 2006.238.07:20:17.50#ibcon#read 5, iclass 35, count 0 2006.238.07:20:17.50#ibcon#about to read 6, iclass 35, count 0 2006.238.07:20:17.50#ibcon#read 6, iclass 35, count 0 2006.238.07:20:17.50#ibcon#end of sib2, iclass 35, count 0 2006.238.07:20:17.50#ibcon#*after write, iclass 35, count 0 2006.238.07:20:17.50#ibcon#*before return 0, iclass 35, count 0 2006.238.07:20:17.50#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:20:17.50#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:20:17.50#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:20:17.50#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:20:17.50$vc4f8/va=6,7 2006.238.07:20:17.50#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.07:20:17.50#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.07:20:17.50#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:17.50#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:20:17.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:20:17.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:20:17.54#ibcon#enter wrdev, iclass 37, count 2 2006.238.07:20:17.54#ibcon#first serial, iclass 37, count 2 2006.238.07:20:17.54#ibcon#enter sib2, iclass 37, count 2 2006.238.07:20:17.54#ibcon#flushed, iclass 37, count 2 2006.238.07:20:17.54#ibcon#about to write, iclass 37, count 2 2006.238.07:20:17.54#ibcon#wrote, iclass 37, count 2 2006.238.07:20:17.54#ibcon#about to read 3, iclass 37, count 2 2006.238.07:20:17.57#ibcon#read 3, iclass 37, count 2 2006.238.07:20:17.57#ibcon#about to read 4, iclass 37, count 2 2006.238.07:20:17.57#ibcon#read 4, iclass 37, count 2 2006.238.07:20:17.57#ibcon#about to read 5, iclass 37, count 2 2006.238.07:20:17.57#ibcon#read 5, iclass 37, count 2 2006.238.07:20:17.57#ibcon#about to read 6, iclass 37, count 2 2006.238.07:20:17.57#ibcon#read 6, iclass 37, count 2 2006.238.07:20:17.57#ibcon#end of sib2, iclass 37, count 2 2006.238.07:20:17.57#ibcon#*mode == 0, iclass 37, count 2 2006.238.07:20:17.57#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.07:20:17.57#ibcon#[25=AT06-07\r\n] 2006.238.07:20:17.57#ibcon#*before write, iclass 37, count 2 2006.238.07:20:17.57#ibcon#enter sib2, iclass 37, count 2 2006.238.07:20:17.57#ibcon#flushed, iclass 37, count 2 2006.238.07:20:17.57#ibcon#about to write, iclass 37, count 2 2006.238.07:20:17.57#ibcon#wrote, iclass 37, count 2 2006.238.07:20:17.57#ibcon#about to read 3, iclass 37, count 2 2006.238.07:20:17.60#ibcon#read 3, iclass 37, count 2 2006.238.07:20:17.60#ibcon#about to read 4, iclass 37, count 2 2006.238.07:20:17.60#ibcon#read 4, iclass 37, count 2 2006.238.07:20:17.60#ibcon#about to read 5, iclass 37, count 2 2006.238.07:20:17.60#ibcon#read 5, iclass 37, count 2 2006.238.07:20:17.60#ibcon#about to read 6, iclass 37, count 2 2006.238.07:20:17.60#ibcon#read 6, iclass 37, count 2 2006.238.07:20:17.60#ibcon#end of sib2, iclass 37, count 2 2006.238.07:20:17.60#ibcon#*after write, iclass 37, count 2 2006.238.07:20:17.60#ibcon#*before return 0, iclass 37, count 2 2006.238.07:20:17.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:20:17.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:20:17.60#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.07:20:17.60#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:17.60#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:20:17.72#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:20:17.72#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:20:17.72#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:20:17.72#ibcon#first serial, iclass 37, count 0 2006.238.07:20:17.72#ibcon#enter sib2, iclass 37, count 0 2006.238.07:20:17.72#ibcon#flushed, iclass 37, count 0 2006.238.07:20:17.72#ibcon#about to write, iclass 37, count 0 2006.238.07:20:17.72#ibcon#wrote, iclass 37, count 0 2006.238.07:20:17.72#ibcon#about to read 3, iclass 37, count 0 2006.238.07:20:17.74#ibcon#read 3, iclass 37, count 0 2006.238.07:20:17.74#ibcon#about to read 4, iclass 37, count 0 2006.238.07:20:17.74#ibcon#read 4, iclass 37, count 0 2006.238.07:20:17.74#ibcon#about to read 5, iclass 37, count 0 2006.238.07:20:17.74#ibcon#read 5, iclass 37, count 0 2006.238.07:20:17.74#ibcon#about to read 6, iclass 37, count 0 2006.238.07:20:17.74#ibcon#read 6, iclass 37, count 0 2006.238.07:20:17.74#ibcon#end of sib2, iclass 37, count 0 2006.238.07:20:17.74#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:20:17.74#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:20:17.74#ibcon#[25=USB\r\n] 2006.238.07:20:17.74#ibcon#*before write, iclass 37, count 0 2006.238.07:20:17.74#ibcon#enter sib2, iclass 37, count 0 2006.238.07:20:17.74#ibcon#flushed, iclass 37, count 0 2006.238.07:20:17.74#ibcon#about to write, iclass 37, count 0 2006.238.07:20:17.74#ibcon#wrote, iclass 37, count 0 2006.238.07:20:17.74#ibcon#about to read 3, iclass 37, count 0 2006.238.07:20:17.77#ibcon#read 3, iclass 37, count 0 2006.238.07:20:17.77#ibcon#about to read 4, iclass 37, count 0 2006.238.07:20:17.77#ibcon#read 4, iclass 37, count 0 2006.238.07:20:17.77#ibcon#about to read 5, iclass 37, count 0 2006.238.07:20:17.77#ibcon#read 5, iclass 37, count 0 2006.238.07:20:17.77#ibcon#about to read 6, iclass 37, count 0 2006.238.07:20:17.77#ibcon#read 6, iclass 37, count 0 2006.238.07:20:17.77#ibcon#end of sib2, iclass 37, count 0 2006.238.07:20:17.77#ibcon#*after write, iclass 37, count 0 2006.238.07:20:17.77#ibcon#*before return 0, iclass 37, count 0 2006.238.07:20:17.77#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:20:17.77#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:20:17.77#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:20:17.77#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:20:17.77$vc4f8/valo=7,832.99 2006.238.07:20:17.78#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.07:20:17.78#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.07:20:17.78#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:17.78#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:20:17.78#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:20:17.78#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:20:17.78#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:20:17.78#ibcon#first serial, iclass 39, count 0 2006.238.07:20:17.78#ibcon#enter sib2, iclass 39, count 0 2006.238.07:20:17.78#ibcon#flushed, iclass 39, count 0 2006.238.07:20:17.78#ibcon#about to write, iclass 39, count 0 2006.238.07:20:17.78#ibcon#wrote, iclass 39, count 0 2006.238.07:20:17.78#ibcon#about to read 3, iclass 39, count 0 2006.238.07:20:17.79#ibcon#read 3, iclass 39, count 0 2006.238.07:20:17.79#ibcon#about to read 4, iclass 39, count 0 2006.238.07:20:17.79#ibcon#read 4, iclass 39, count 0 2006.238.07:20:17.79#ibcon#about to read 5, iclass 39, count 0 2006.238.07:20:17.79#ibcon#read 5, iclass 39, count 0 2006.238.07:20:17.79#ibcon#about to read 6, iclass 39, count 0 2006.238.07:20:17.79#ibcon#read 6, iclass 39, count 0 2006.238.07:20:17.79#ibcon#end of sib2, iclass 39, count 0 2006.238.07:20:17.79#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:20:17.79#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:20:17.79#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:20:17.79#ibcon#*before write, iclass 39, count 0 2006.238.07:20:17.79#ibcon#enter sib2, iclass 39, count 0 2006.238.07:20:17.79#ibcon#flushed, iclass 39, count 0 2006.238.07:20:17.79#ibcon#about to write, iclass 39, count 0 2006.238.07:20:17.79#ibcon#wrote, iclass 39, count 0 2006.238.07:20:17.79#ibcon#about to read 3, iclass 39, count 0 2006.238.07:20:17.83#ibcon#read 3, iclass 39, count 0 2006.238.07:20:17.83#ibcon#about to read 4, iclass 39, count 0 2006.238.07:20:17.83#ibcon#read 4, iclass 39, count 0 2006.238.07:20:17.83#ibcon#about to read 5, iclass 39, count 0 2006.238.07:20:17.83#ibcon#read 5, iclass 39, count 0 2006.238.07:20:17.83#ibcon#about to read 6, iclass 39, count 0 2006.238.07:20:17.83#ibcon#read 6, iclass 39, count 0 2006.238.07:20:17.83#ibcon#end of sib2, iclass 39, count 0 2006.238.07:20:17.83#ibcon#*after write, iclass 39, count 0 2006.238.07:20:17.83#ibcon#*before return 0, iclass 39, count 0 2006.238.07:20:17.83#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:20:17.83#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:20:17.83#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:20:17.83#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:20:17.83$vc4f8/va=7,7 2006.238.07:20:17.84#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.07:20:17.84#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.07:20:17.84#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:17.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:20:17.89#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:20:17.89#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:20:17.89#ibcon#enter wrdev, iclass 3, count 2 2006.238.07:20:17.89#ibcon#first serial, iclass 3, count 2 2006.238.07:20:17.89#ibcon#enter sib2, iclass 3, count 2 2006.238.07:20:17.89#ibcon#flushed, iclass 3, count 2 2006.238.07:20:17.89#ibcon#about to write, iclass 3, count 2 2006.238.07:20:17.89#ibcon#wrote, iclass 3, count 2 2006.238.07:20:17.89#ibcon#about to read 3, iclass 3, count 2 2006.238.07:20:17.90#ibcon#read 3, iclass 3, count 2 2006.238.07:20:17.90#ibcon#about to read 4, iclass 3, count 2 2006.238.07:20:17.90#ibcon#read 4, iclass 3, count 2 2006.238.07:20:17.90#ibcon#about to read 5, iclass 3, count 2 2006.238.07:20:17.90#ibcon#read 5, iclass 3, count 2 2006.238.07:20:17.90#ibcon#about to read 6, iclass 3, count 2 2006.238.07:20:17.90#ibcon#read 6, iclass 3, count 2 2006.238.07:20:17.90#ibcon#end of sib2, iclass 3, count 2 2006.238.07:20:17.90#ibcon#*mode == 0, iclass 3, count 2 2006.238.07:20:17.90#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.07:20:17.90#ibcon#[25=AT07-07\r\n] 2006.238.07:20:17.90#ibcon#*before write, iclass 3, count 2 2006.238.07:20:17.90#ibcon#enter sib2, iclass 3, count 2 2006.238.07:20:17.90#ibcon#flushed, iclass 3, count 2 2006.238.07:20:17.90#ibcon#about to write, iclass 3, count 2 2006.238.07:20:17.90#ibcon#wrote, iclass 3, count 2 2006.238.07:20:17.90#ibcon#about to read 3, iclass 3, count 2 2006.238.07:20:17.93#ibcon#read 3, iclass 3, count 2 2006.238.07:20:17.93#ibcon#about to read 4, iclass 3, count 2 2006.238.07:20:17.93#ibcon#read 4, iclass 3, count 2 2006.238.07:20:17.93#ibcon#about to read 5, iclass 3, count 2 2006.238.07:20:17.93#ibcon#read 5, iclass 3, count 2 2006.238.07:20:17.93#ibcon#about to read 6, iclass 3, count 2 2006.238.07:20:17.93#ibcon#read 6, iclass 3, count 2 2006.238.07:20:17.93#ibcon#end of sib2, iclass 3, count 2 2006.238.07:20:17.93#ibcon#*after write, iclass 3, count 2 2006.238.07:20:17.93#ibcon#*before return 0, iclass 3, count 2 2006.238.07:20:17.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:20:17.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:20:17.93#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.07:20:17.93#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:17.93#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:20:18.05#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:20:18.05#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:20:18.05#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:20:18.05#ibcon#first serial, iclass 3, count 0 2006.238.07:20:18.05#ibcon#enter sib2, iclass 3, count 0 2006.238.07:20:18.05#ibcon#flushed, iclass 3, count 0 2006.238.07:20:18.05#ibcon#about to write, iclass 3, count 0 2006.238.07:20:18.05#ibcon#wrote, iclass 3, count 0 2006.238.07:20:18.05#ibcon#about to read 3, iclass 3, count 0 2006.238.07:20:18.10#ibcon#read 3, iclass 3, count 0 2006.238.07:20:18.10#ibcon#about to read 4, iclass 3, count 0 2006.238.07:20:18.10#ibcon#read 4, iclass 3, count 0 2006.238.07:20:18.10#ibcon#about to read 5, iclass 3, count 0 2006.238.07:20:18.10#ibcon#read 5, iclass 3, count 0 2006.238.07:20:18.10#ibcon#about to read 6, iclass 3, count 0 2006.238.07:20:18.10#ibcon#read 6, iclass 3, count 0 2006.238.07:20:18.10#ibcon#end of sib2, iclass 3, count 0 2006.238.07:20:18.10#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:20:18.10#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:20:18.10#ibcon#[25=USB\r\n] 2006.238.07:20:18.10#ibcon#*before write, iclass 3, count 0 2006.238.07:20:18.10#ibcon#enter sib2, iclass 3, count 0 2006.238.07:20:18.10#ibcon#flushed, iclass 3, count 0 2006.238.07:20:18.10#ibcon#about to write, iclass 3, count 0 2006.238.07:20:18.10#ibcon#wrote, iclass 3, count 0 2006.238.07:20:18.10#ibcon#about to read 3, iclass 3, count 0 2006.238.07:20:18.12#ibcon#read 3, iclass 3, count 0 2006.238.07:20:18.12#ibcon#about to read 4, iclass 3, count 0 2006.238.07:20:18.12#ibcon#read 4, iclass 3, count 0 2006.238.07:20:18.12#ibcon#about to read 5, iclass 3, count 0 2006.238.07:20:18.12#ibcon#read 5, iclass 3, count 0 2006.238.07:20:18.12#ibcon#about to read 6, iclass 3, count 0 2006.238.07:20:18.12#ibcon#read 6, iclass 3, count 0 2006.238.07:20:18.12#ibcon#end of sib2, iclass 3, count 0 2006.238.07:20:18.12#ibcon#*after write, iclass 3, count 0 2006.238.07:20:18.12#ibcon#*before return 0, iclass 3, count 0 2006.238.07:20:18.12#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:20:18.12#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:20:18.12#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:20:18.12#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:20:18.12$vc4f8/valo=8,852.99 2006.238.07:20:18.12#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.07:20:18.13#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.07:20:18.13#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:18.13#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:20:18.13#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:20:18.13#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:20:18.13#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:20:18.13#ibcon#first serial, iclass 5, count 0 2006.238.07:20:18.13#ibcon#enter sib2, iclass 5, count 0 2006.238.07:20:18.13#ibcon#flushed, iclass 5, count 0 2006.238.07:20:18.13#ibcon#about to write, iclass 5, count 0 2006.238.07:20:18.13#ibcon#wrote, iclass 5, count 0 2006.238.07:20:18.13#ibcon#about to read 3, iclass 5, count 0 2006.238.07:20:18.14#ibcon#read 3, iclass 5, count 0 2006.238.07:20:18.14#ibcon#about to read 4, iclass 5, count 0 2006.238.07:20:18.14#ibcon#read 4, iclass 5, count 0 2006.238.07:20:18.14#ibcon#about to read 5, iclass 5, count 0 2006.238.07:20:18.14#ibcon#read 5, iclass 5, count 0 2006.238.07:20:18.14#ibcon#about to read 6, iclass 5, count 0 2006.238.07:20:18.14#ibcon#read 6, iclass 5, count 0 2006.238.07:20:18.14#ibcon#end of sib2, iclass 5, count 0 2006.238.07:20:18.14#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:20:18.14#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:20:18.14#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:20:18.14#ibcon#*before write, iclass 5, count 0 2006.238.07:20:18.14#ibcon#enter sib2, iclass 5, count 0 2006.238.07:20:18.14#ibcon#flushed, iclass 5, count 0 2006.238.07:20:18.14#ibcon#about to write, iclass 5, count 0 2006.238.07:20:18.14#ibcon#wrote, iclass 5, count 0 2006.238.07:20:18.14#ibcon#about to read 3, iclass 5, count 0 2006.238.07:20:18.19#ibcon#read 3, iclass 5, count 0 2006.238.07:20:18.19#ibcon#about to read 4, iclass 5, count 0 2006.238.07:20:18.19#ibcon#read 4, iclass 5, count 0 2006.238.07:20:18.19#ibcon#about to read 5, iclass 5, count 0 2006.238.07:20:18.19#ibcon#read 5, iclass 5, count 0 2006.238.07:20:18.19#ibcon#about to read 6, iclass 5, count 0 2006.238.07:20:18.19#ibcon#read 6, iclass 5, count 0 2006.238.07:20:18.19#ibcon#end of sib2, iclass 5, count 0 2006.238.07:20:18.19#ibcon#*after write, iclass 5, count 0 2006.238.07:20:18.19#ibcon#*before return 0, iclass 5, count 0 2006.238.07:20:18.19#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:20:18.19#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:20:18.19#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:20:18.19#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:20:18.19$vc4f8/va=8,7 2006.238.07:20:18.19#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.07:20:18.19#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.07:20:18.19#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:18.19#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:20:18.23#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:20:18.23#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:20:18.23#ibcon#enter wrdev, iclass 7, count 2 2006.238.07:20:18.23#ibcon#first serial, iclass 7, count 2 2006.238.07:20:18.23#ibcon#enter sib2, iclass 7, count 2 2006.238.07:20:18.23#ibcon#flushed, iclass 7, count 2 2006.238.07:20:18.23#ibcon#about to write, iclass 7, count 2 2006.238.07:20:18.23#ibcon#wrote, iclass 7, count 2 2006.238.07:20:18.23#ibcon#about to read 3, iclass 7, count 2 2006.238.07:20:18.25#ibcon#read 3, iclass 7, count 2 2006.238.07:20:18.25#ibcon#about to read 4, iclass 7, count 2 2006.238.07:20:18.25#ibcon#read 4, iclass 7, count 2 2006.238.07:20:18.25#ibcon#about to read 5, iclass 7, count 2 2006.238.07:20:18.25#ibcon#read 5, iclass 7, count 2 2006.238.07:20:18.25#ibcon#about to read 6, iclass 7, count 2 2006.238.07:20:18.25#ibcon#read 6, iclass 7, count 2 2006.238.07:20:18.25#ibcon#end of sib2, iclass 7, count 2 2006.238.07:20:18.25#ibcon#*mode == 0, iclass 7, count 2 2006.238.07:20:18.25#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.07:20:18.25#ibcon#[25=AT08-07\r\n] 2006.238.07:20:18.25#ibcon#*before write, iclass 7, count 2 2006.238.07:20:18.25#ibcon#enter sib2, iclass 7, count 2 2006.238.07:20:18.25#ibcon#flushed, iclass 7, count 2 2006.238.07:20:18.25#ibcon#about to write, iclass 7, count 2 2006.238.07:20:18.25#ibcon#wrote, iclass 7, count 2 2006.238.07:20:18.25#ibcon#about to read 3, iclass 7, count 2 2006.238.07:20:18.28#ibcon#read 3, iclass 7, count 2 2006.238.07:20:18.28#ibcon#about to read 4, iclass 7, count 2 2006.238.07:20:18.28#ibcon#read 4, iclass 7, count 2 2006.238.07:20:18.28#ibcon#about to read 5, iclass 7, count 2 2006.238.07:20:18.28#ibcon#read 5, iclass 7, count 2 2006.238.07:20:18.28#ibcon#about to read 6, iclass 7, count 2 2006.238.07:20:18.28#ibcon#read 6, iclass 7, count 2 2006.238.07:20:18.28#ibcon#end of sib2, iclass 7, count 2 2006.238.07:20:18.28#ibcon#*after write, iclass 7, count 2 2006.238.07:20:18.28#ibcon#*before return 0, iclass 7, count 2 2006.238.07:20:18.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:20:18.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:20:18.28#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.07:20:18.28#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:18.28#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:20:18.40#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:20:18.40#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:20:18.40#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:20:18.40#ibcon#first serial, iclass 7, count 0 2006.238.07:20:18.40#ibcon#enter sib2, iclass 7, count 0 2006.238.07:20:18.40#ibcon#flushed, iclass 7, count 0 2006.238.07:20:18.40#ibcon#about to write, iclass 7, count 0 2006.238.07:20:18.40#ibcon#wrote, iclass 7, count 0 2006.238.07:20:18.40#ibcon#about to read 3, iclass 7, count 0 2006.238.07:20:18.42#ibcon#read 3, iclass 7, count 0 2006.238.07:20:18.42#ibcon#about to read 4, iclass 7, count 0 2006.238.07:20:18.42#ibcon#read 4, iclass 7, count 0 2006.238.07:20:18.42#ibcon#about to read 5, iclass 7, count 0 2006.238.07:20:18.42#ibcon#read 5, iclass 7, count 0 2006.238.07:20:18.42#ibcon#about to read 6, iclass 7, count 0 2006.238.07:20:18.42#ibcon#read 6, iclass 7, count 0 2006.238.07:20:18.42#ibcon#end of sib2, iclass 7, count 0 2006.238.07:20:18.42#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:20:18.42#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:20:18.42#ibcon#[25=USB\r\n] 2006.238.07:20:18.42#ibcon#*before write, iclass 7, count 0 2006.238.07:20:18.42#ibcon#enter sib2, iclass 7, count 0 2006.238.07:20:18.42#ibcon#flushed, iclass 7, count 0 2006.238.07:20:18.42#ibcon#about to write, iclass 7, count 0 2006.238.07:20:18.42#ibcon#wrote, iclass 7, count 0 2006.238.07:20:18.42#ibcon#about to read 3, iclass 7, count 0 2006.238.07:20:18.45#ibcon#read 3, iclass 7, count 0 2006.238.07:20:18.45#ibcon#about to read 4, iclass 7, count 0 2006.238.07:20:18.45#ibcon#read 4, iclass 7, count 0 2006.238.07:20:18.45#ibcon#about to read 5, iclass 7, count 0 2006.238.07:20:18.45#ibcon#read 5, iclass 7, count 0 2006.238.07:20:18.45#ibcon#about to read 6, iclass 7, count 0 2006.238.07:20:18.45#ibcon#read 6, iclass 7, count 0 2006.238.07:20:18.45#ibcon#end of sib2, iclass 7, count 0 2006.238.07:20:18.45#ibcon#*after write, iclass 7, count 0 2006.238.07:20:18.45#ibcon#*before return 0, iclass 7, count 0 2006.238.07:20:18.45#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:20:18.45#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:20:18.45#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:20:18.45#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:20:18.45$vc4f8/vblo=1,632.99 2006.238.07:20:18.45#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.07:20:18.46#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.07:20:18.46#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:18.46#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:20:18.46#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:20:18.46#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:20:18.46#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:20:18.46#ibcon#first serial, iclass 11, count 0 2006.238.07:20:18.46#ibcon#enter sib2, iclass 11, count 0 2006.238.07:20:18.46#ibcon#flushed, iclass 11, count 0 2006.238.07:20:18.46#ibcon#about to write, iclass 11, count 0 2006.238.07:20:18.46#ibcon#wrote, iclass 11, count 0 2006.238.07:20:18.46#ibcon#about to read 3, iclass 11, count 0 2006.238.07:20:18.47#ibcon#read 3, iclass 11, count 0 2006.238.07:20:18.47#ibcon#about to read 4, iclass 11, count 0 2006.238.07:20:18.47#ibcon#read 4, iclass 11, count 0 2006.238.07:20:18.47#ibcon#about to read 5, iclass 11, count 0 2006.238.07:20:18.47#ibcon#read 5, iclass 11, count 0 2006.238.07:20:18.47#ibcon#about to read 6, iclass 11, count 0 2006.238.07:20:18.47#ibcon#read 6, iclass 11, count 0 2006.238.07:20:18.47#ibcon#end of sib2, iclass 11, count 0 2006.238.07:20:18.47#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:20:18.47#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:20:18.47#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:20:18.47#ibcon#*before write, iclass 11, count 0 2006.238.07:20:18.47#ibcon#enter sib2, iclass 11, count 0 2006.238.07:20:18.47#ibcon#flushed, iclass 11, count 0 2006.238.07:20:18.47#ibcon#about to write, iclass 11, count 0 2006.238.07:20:18.47#ibcon#wrote, iclass 11, count 0 2006.238.07:20:18.47#ibcon#about to read 3, iclass 11, count 0 2006.238.07:20:18.53#ibcon#read 3, iclass 11, count 0 2006.238.07:20:18.53#ibcon#about to read 4, iclass 11, count 0 2006.238.07:20:18.53#ibcon#read 4, iclass 11, count 0 2006.238.07:20:18.53#ibcon#about to read 5, iclass 11, count 0 2006.238.07:20:18.53#ibcon#read 5, iclass 11, count 0 2006.238.07:20:18.53#ibcon#about to read 6, iclass 11, count 0 2006.238.07:20:18.53#ibcon#read 6, iclass 11, count 0 2006.238.07:20:18.53#ibcon#end of sib2, iclass 11, count 0 2006.238.07:20:18.53#ibcon#*after write, iclass 11, count 0 2006.238.07:20:18.53#ibcon#*before return 0, iclass 11, count 0 2006.238.07:20:18.53#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:20:18.53#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:20:18.53#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:20:18.53#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:20:18.53$vc4f8/vb=1,4 2006.238.07:20:18.54#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.07:20:18.54#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.07:20:18.54#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:18.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:20:18.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:20:18.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:20:18.54#ibcon#enter wrdev, iclass 13, count 2 2006.238.07:20:18.54#ibcon#first serial, iclass 13, count 2 2006.238.07:20:18.54#ibcon#enter sib2, iclass 13, count 2 2006.238.07:20:18.54#ibcon#flushed, iclass 13, count 2 2006.238.07:20:18.54#ibcon#about to write, iclass 13, count 2 2006.238.07:20:18.54#ibcon#wrote, iclass 13, count 2 2006.238.07:20:18.54#ibcon#about to read 3, iclass 13, count 2 2006.238.07:20:18.55#ibcon#read 3, iclass 13, count 2 2006.238.07:20:18.55#ibcon#about to read 4, iclass 13, count 2 2006.238.07:20:18.55#ibcon#read 4, iclass 13, count 2 2006.238.07:20:18.55#ibcon#about to read 5, iclass 13, count 2 2006.238.07:20:18.55#ibcon#read 5, iclass 13, count 2 2006.238.07:20:18.55#ibcon#about to read 6, iclass 13, count 2 2006.238.07:20:18.55#ibcon#read 6, iclass 13, count 2 2006.238.07:20:18.55#ibcon#end of sib2, iclass 13, count 2 2006.238.07:20:18.55#ibcon#*mode == 0, iclass 13, count 2 2006.238.07:20:18.55#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.07:20:18.55#ibcon#[27=AT01-04\r\n] 2006.238.07:20:18.55#ibcon#*before write, iclass 13, count 2 2006.238.07:20:18.55#ibcon#enter sib2, iclass 13, count 2 2006.238.07:20:18.55#ibcon#flushed, iclass 13, count 2 2006.238.07:20:18.55#ibcon#about to write, iclass 13, count 2 2006.238.07:20:18.55#ibcon#wrote, iclass 13, count 2 2006.238.07:20:18.55#ibcon#about to read 3, iclass 13, count 2 2006.238.07:20:18.58#ibcon#read 3, iclass 13, count 2 2006.238.07:20:18.58#ibcon#about to read 4, iclass 13, count 2 2006.238.07:20:18.58#ibcon#read 4, iclass 13, count 2 2006.238.07:20:18.58#ibcon#about to read 5, iclass 13, count 2 2006.238.07:20:18.58#ibcon#read 5, iclass 13, count 2 2006.238.07:20:18.58#ibcon#about to read 6, iclass 13, count 2 2006.238.07:20:18.58#ibcon#read 6, iclass 13, count 2 2006.238.07:20:18.58#ibcon#end of sib2, iclass 13, count 2 2006.238.07:20:18.58#ibcon#*after write, iclass 13, count 2 2006.238.07:20:18.58#ibcon#*before return 0, iclass 13, count 2 2006.238.07:20:18.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:20:18.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:20:18.58#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.07:20:18.58#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:18.58#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:20:18.70#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:20:18.70#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:20:18.70#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:20:18.70#ibcon#first serial, iclass 13, count 0 2006.238.07:20:18.70#ibcon#enter sib2, iclass 13, count 0 2006.238.07:20:18.70#ibcon#flushed, iclass 13, count 0 2006.238.07:20:18.70#ibcon#about to write, iclass 13, count 0 2006.238.07:20:18.70#ibcon#wrote, iclass 13, count 0 2006.238.07:20:18.70#ibcon#about to read 3, iclass 13, count 0 2006.238.07:20:18.72#ibcon#read 3, iclass 13, count 0 2006.238.07:20:18.72#ibcon#about to read 4, iclass 13, count 0 2006.238.07:20:18.72#ibcon#read 4, iclass 13, count 0 2006.238.07:20:18.72#ibcon#about to read 5, iclass 13, count 0 2006.238.07:20:18.72#ibcon#read 5, iclass 13, count 0 2006.238.07:20:18.72#ibcon#about to read 6, iclass 13, count 0 2006.238.07:20:18.72#ibcon#read 6, iclass 13, count 0 2006.238.07:20:18.72#ibcon#end of sib2, iclass 13, count 0 2006.238.07:20:18.72#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:20:18.72#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:20:18.73#ibcon#[27=USB\r\n] 2006.238.07:20:18.73#ibcon#*before write, iclass 13, count 0 2006.238.07:20:18.73#ibcon#enter sib2, iclass 13, count 0 2006.238.07:20:18.73#ibcon#flushed, iclass 13, count 0 2006.238.07:20:18.73#ibcon#about to write, iclass 13, count 0 2006.238.07:20:18.73#ibcon#wrote, iclass 13, count 0 2006.238.07:20:18.73#ibcon#about to read 3, iclass 13, count 0 2006.238.07:20:18.75#ibcon#read 3, iclass 13, count 0 2006.238.07:20:18.75#ibcon#about to read 4, iclass 13, count 0 2006.238.07:20:18.75#ibcon#read 4, iclass 13, count 0 2006.238.07:20:18.75#ibcon#about to read 5, iclass 13, count 0 2006.238.07:20:18.75#ibcon#read 5, iclass 13, count 0 2006.238.07:20:18.75#ibcon#about to read 6, iclass 13, count 0 2006.238.07:20:18.75#ibcon#read 6, iclass 13, count 0 2006.238.07:20:18.75#ibcon#end of sib2, iclass 13, count 0 2006.238.07:20:18.75#ibcon#*after write, iclass 13, count 0 2006.238.07:20:18.75#ibcon#*before return 0, iclass 13, count 0 2006.238.07:20:18.75#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:20:18.75#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:20:18.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:20:18.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:20:18.75$vc4f8/vblo=2,640.99 2006.238.07:20:18.75#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.07:20:18.76#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.07:20:18.76#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:18.76#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:20:18.76#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:20:18.76#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:20:18.76#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:20:18.76#ibcon#first serial, iclass 15, count 0 2006.238.07:20:18.76#ibcon#enter sib2, iclass 15, count 0 2006.238.07:20:18.76#ibcon#flushed, iclass 15, count 0 2006.238.07:20:18.76#ibcon#about to write, iclass 15, count 0 2006.238.07:20:18.76#ibcon#wrote, iclass 15, count 0 2006.238.07:20:18.76#ibcon#about to read 3, iclass 15, count 0 2006.238.07:20:18.78#ibcon#read 3, iclass 15, count 0 2006.238.07:20:18.78#ibcon#about to read 4, iclass 15, count 0 2006.238.07:20:18.78#ibcon#read 4, iclass 15, count 0 2006.238.07:20:18.78#ibcon#about to read 5, iclass 15, count 0 2006.238.07:20:18.78#ibcon#read 5, iclass 15, count 0 2006.238.07:20:18.78#ibcon#about to read 6, iclass 15, count 0 2006.238.07:20:18.78#ibcon#read 6, iclass 15, count 0 2006.238.07:20:18.78#ibcon#end of sib2, iclass 15, count 0 2006.238.07:20:18.78#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:20:18.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:20:18.78#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:20:18.78#ibcon#*before write, iclass 15, count 0 2006.238.07:20:18.78#ibcon#enter sib2, iclass 15, count 0 2006.238.07:20:18.78#ibcon#flushed, iclass 15, count 0 2006.238.07:20:18.78#ibcon#about to write, iclass 15, count 0 2006.238.07:20:18.78#ibcon#wrote, iclass 15, count 0 2006.238.07:20:18.78#ibcon#about to read 3, iclass 15, count 0 2006.238.07:20:18.81#ibcon#read 3, iclass 15, count 0 2006.238.07:20:18.81#ibcon#about to read 4, iclass 15, count 0 2006.238.07:20:18.81#ibcon#read 4, iclass 15, count 0 2006.238.07:20:18.81#ibcon#about to read 5, iclass 15, count 0 2006.238.07:20:18.81#ibcon#read 5, iclass 15, count 0 2006.238.07:20:18.81#ibcon#about to read 6, iclass 15, count 0 2006.238.07:20:18.81#ibcon#read 6, iclass 15, count 0 2006.238.07:20:18.81#ibcon#end of sib2, iclass 15, count 0 2006.238.07:20:18.81#ibcon#*after write, iclass 15, count 0 2006.238.07:20:18.81#ibcon#*before return 0, iclass 15, count 0 2006.238.07:20:18.81#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:20:18.81#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:20:18.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:20:18.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:20:18.81$vc4f8/vb=2,4 2006.238.07:20:18.82#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.07:20:18.82#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.07:20:18.82#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:18.82#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:20:18.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:20:18.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:20:18.86#ibcon#enter wrdev, iclass 17, count 2 2006.238.07:20:18.86#ibcon#first serial, iclass 17, count 2 2006.238.07:20:18.86#ibcon#enter sib2, iclass 17, count 2 2006.238.07:20:18.86#ibcon#flushed, iclass 17, count 2 2006.238.07:20:18.86#ibcon#about to write, iclass 17, count 2 2006.238.07:20:18.86#ibcon#wrote, iclass 17, count 2 2006.238.07:20:18.86#ibcon#about to read 3, iclass 17, count 2 2006.238.07:20:18.89#ibcon#read 3, iclass 17, count 2 2006.238.07:20:18.89#ibcon#about to read 4, iclass 17, count 2 2006.238.07:20:18.89#ibcon#read 4, iclass 17, count 2 2006.238.07:20:18.89#ibcon#about to read 5, iclass 17, count 2 2006.238.07:20:18.89#ibcon#read 5, iclass 17, count 2 2006.238.07:20:18.89#ibcon#about to read 6, iclass 17, count 2 2006.238.07:20:18.89#ibcon#read 6, iclass 17, count 2 2006.238.07:20:18.89#ibcon#end of sib2, iclass 17, count 2 2006.238.07:20:18.89#ibcon#*mode == 0, iclass 17, count 2 2006.238.07:20:18.89#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.07:20:18.89#ibcon#[27=AT02-04\r\n] 2006.238.07:20:18.89#ibcon#*before write, iclass 17, count 2 2006.238.07:20:18.89#ibcon#enter sib2, iclass 17, count 2 2006.238.07:20:18.89#ibcon#flushed, iclass 17, count 2 2006.238.07:20:18.89#ibcon#about to write, iclass 17, count 2 2006.238.07:20:18.89#ibcon#wrote, iclass 17, count 2 2006.238.07:20:18.89#ibcon#about to read 3, iclass 17, count 2 2006.238.07:20:18.92#ibcon#read 3, iclass 17, count 2 2006.238.07:20:18.92#ibcon#about to read 4, iclass 17, count 2 2006.238.07:20:18.92#ibcon#read 4, iclass 17, count 2 2006.238.07:20:18.92#ibcon#about to read 5, iclass 17, count 2 2006.238.07:20:18.92#ibcon#read 5, iclass 17, count 2 2006.238.07:20:18.92#ibcon#about to read 6, iclass 17, count 2 2006.238.07:20:18.92#ibcon#read 6, iclass 17, count 2 2006.238.07:20:18.92#ibcon#end of sib2, iclass 17, count 2 2006.238.07:20:18.92#ibcon#*after write, iclass 17, count 2 2006.238.07:20:18.92#ibcon#*before return 0, iclass 17, count 2 2006.238.07:20:18.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:20:18.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:20:18.92#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.07:20:18.92#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:18.92#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:20:19.03#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:20:19.03#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:20:19.03#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:20:19.03#ibcon#first serial, iclass 17, count 0 2006.238.07:20:19.03#ibcon#enter sib2, iclass 17, count 0 2006.238.07:20:19.03#ibcon#flushed, iclass 17, count 0 2006.238.07:20:19.03#ibcon#about to write, iclass 17, count 0 2006.238.07:20:19.03#ibcon#wrote, iclass 17, count 0 2006.238.07:20:19.03#ibcon#about to read 3, iclass 17, count 0 2006.238.07:20:19.05#ibcon#read 3, iclass 17, count 0 2006.238.07:20:19.05#ibcon#about to read 4, iclass 17, count 0 2006.238.07:20:19.05#ibcon#read 4, iclass 17, count 0 2006.238.07:20:19.05#ibcon#about to read 5, iclass 17, count 0 2006.238.07:20:19.05#ibcon#read 5, iclass 17, count 0 2006.238.07:20:19.05#ibcon#about to read 6, iclass 17, count 0 2006.238.07:20:19.05#ibcon#read 6, iclass 17, count 0 2006.238.07:20:19.05#ibcon#end of sib2, iclass 17, count 0 2006.238.07:20:19.05#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:20:19.05#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:20:19.05#ibcon#[27=USB\r\n] 2006.238.07:20:19.05#ibcon#*before write, iclass 17, count 0 2006.238.07:20:19.05#ibcon#enter sib2, iclass 17, count 0 2006.238.07:20:19.05#ibcon#flushed, iclass 17, count 0 2006.238.07:20:19.05#ibcon#about to write, iclass 17, count 0 2006.238.07:20:19.05#ibcon#wrote, iclass 17, count 0 2006.238.07:20:19.05#ibcon#about to read 3, iclass 17, count 0 2006.238.07:20:19.08#ibcon#read 3, iclass 17, count 0 2006.238.07:20:19.08#ibcon#about to read 4, iclass 17, count 0 2006.238.07:20:19.08#ibcon#read 4, iclass 17, count 0 2006.238.07:20:19.08#ibcon#about to read 5, iclass 17, count 0 2006.238.07:20:19.08#ibcon#read 5, iclass 17, count 0 2006.238.07:20:19.08#ibcon#about to read 6, iclass 17, count 0 2006.238.07:20:19.08#ibcon#read 6, iclass 17, count 0 2006.238.07:20:19.08#ibcon#end of sib2, iclass 17, count 0 2006.238.07:20:19.08#ibcon#*after write, iclass 17, count 0 2006.238.07:20:19.08#ibcon#*before return 0, iclass 17, count 0 2006.238.07:20:19.08#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:20:19.08#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:20:19.08#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:20:19.08#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:20:19.08$vc4f8/vblo=3,656.99 2006.238.07:20:19.09#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.07:20:19.09#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.07:20:19.09#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:19.09#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:20:19.09#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:20:19.09#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:20:19.09#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:20:19.09#ibcon#first serial, iclass 19, count 0 2006.238.07:20:19.09#ibcon#enter sib2, iclass 19, count 0 2006.238.07:20:19.09#ibcon#flushed, iclass 19, count 0 2006.238.07:20:19.09#ibcon#about to write, iclass 19, count 0 2006.238.07:20:19.09#ibcon#wrote, iclass 19, count 0 2006.238.07:20:19.09#ibcon#about to read 3, iclass 19, count 0 2006.238.07:20:19.10#ibcon#read 3, iclass 19, count 0 2006.238.07:20:19.10#ibcon#about to read 4, iclass 19, count 0 2006.238.07:20:19.10#ibcon#read 4, iclass 19, count 0 2006.238.07:20:19.10#ibcon#about to read 5, iclass 19, count 0 2006.238.07:20:19.10#ibcon#read 5, iclass 19, count 0 2006.238.07:20:19.10#ibcon#about to read 6, iclass 19, count 0 2006.238.07:20:19.10#ibcon#read 6, iclass 19, count 0 2006.238.07:20:19.10#ibcon#end of sib2, iclass 19, count 0 2006.238.07:20:19.10#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:20:19.10#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:20:19.10#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:20:19.10#ibcon#*before write, iclass 19, count 0 2006.238.07:20:19.10#ibcon#enter sib2, iclass 19, count 0 2006.238.07:20:19.10#ibcon#flushed, iclass 19, count 0 2006.238.07:20:19.10#ibcon#about to write, iclass 19, count 0 2006.238.07:20:19.10#ibcon#wrote, iclass 19, count 0 2006.238.07:20:19.10#ibcon#about to read 3, iclass 19, count 0 2006.238.07:20:19.14#ibcon#read 3, iclass 19, count 0 2006.238.07:20:19.14#ibcon#about to read 4, iclass 19, count 0 2006.238.07:20:19.14#ibcon#read 4, iclass 19, count 0 2006.238.07:20:19.14#ibcon#about to read 5, iclass 19, count 0 2006.238.07:20:19.14#ibcon#read 5, iclass 19, count 0 2006.238.07:20:19.14#ibcon#about to read 6, iclass 19, count 0 2006.238.07:20:19.14#ibcon#read 6, iclass 19, count 0 2006.238.07:20:19.14#ibcon#end of sib2, iclass 19, count 0 2006.238.07:20:19.14#ibcon#*after write, iclass 19, count 0 2006.238.07:20:19.14#ibcon#*before return 0, iclass 19, count 0 2006.238.07:20:19.14#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:20:19.14#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:20:19.14#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:20:19.14#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:20:19.14$vc4f8/vb=3,4 2006.238.07:20:19.14#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.07:20:19.14#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.07:20:19.14#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:19.14#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:20:19.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:20:19.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:20:19.20#ibcon#enter wrdev, iclass 21, count 2 2006.238.07:20:19.20#ibcon#first serial, iclass 21, count 2 2006.238.07:20:19.20#ibcon#enter sib2, iclass 21, count 2 2006.238.07:20:19.20#ibcon#flushed, iclass 21, count 2 2006.238.07:20:19.20#ibcon#about to write, iclass 21, count 2 2006.238.07:20:19.20#ibcon#wrote, iclass 21, count 2 2006.238.07:20:19.20#ibcon#about to read 3, iclass 21, count 2 2006.238.07:20:19.22#ibcon#read 3, iclass 21, count 2 2006.238.07:20:19.22#ibcon#about to read 4, iclass 21, count 2 2006.238.07:20:19.22#ibcon#read 4, iclass 21, count 2 2006.238.07:20:19.22#ibcon#about to read 5, iclass 21, count 2 2006.238.07:20:19.22#ibcon#read 5, iclass 21, count 2 2006.238.07:20:19.22#ibcon#about to read 6, iclass 21, count 2 2006.238.07:20:19.22#ibcon#read 6, iclass 21, count 2 2006.238.07:20:19.22#ibcon#end of sib2, iclass 21, count 2 2006.238.07:20:19.22#ibcon#*mode == 0, iclass 21, count 2 2006.238.07:20:19.22#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.07:20:19.22#ibcon#[27=AT03-04\r\n] 2006.238.07:20:19.22#ibcon#*before write, iclass 21, count 2 2006.238.07:20:19.22#ibcon#enter sib2, iclass 21, count 2 2006.238.07:20:19.22#ibcon#flushed, iclass 21, count 2 2006.238.07:20:19.22#ibcon#about to write, iclass 21, count 2 2006.238.07:20:19.22#ibcon#wrote, iclass 21, count 2 2006.238.07:20:19.22#ibcon#about to read 3, iclass 21, count 2 2006.238.07:20:19.25#ibcon#read 3, iclass 21, count 2 2006.238.07:20:19.25#ibcon#about to read 4, iclass 21, count 2 2006.238.07:20:19.25#ibcon#read 4, iclass 21, count 2 2006.238.07:20:19.25#ibcon#about to read 5, iclass 21, count 2 2006.238.07:20:19.25#ibcon#read 5, iclass 21, count 2 2006.238.07:20:19.25#ibcon#about to read 6, iclass 21, count 2 2006.238.07:20:19.25#ibcon#read 6, iclass 21, count 2 2006.238.07:20:19.25#ibcon#end of sib2, iclass 21, count 2 2006.238.07:20:19.25#ibcon#*after write, iclass 21, count 2 2006.238.07:20:19.25#ibcon#*before return 0, iclass 21, count 2 2006.238.07:20:19.25#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:20:19.25#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:20:19.25#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.07:20:19.25#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:19.25#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:20:19.37#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:20:19.37#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:20:19.37#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:20:19.37#ibcon#first serial, iclass 21, count 0 2006.238.07:20:19.37#ibcon#enter sib2, iclass 21, count 0 2006.238.07:20:19.37#ibcon#flushed, iclass 21, count 0 2006.238.07:20:19.37#ibcon#about to write, iclass 21, count 0 2006.238.07:20:19.37#ibcon#wrote, iclass 21, count 0 2006.238.07:20:19.37#ibcon#about to read 3, iclass 21, count 0 2006.238.07:20:19.39#ibcon#read 3, iclass 21, count 0 2006.238.07:20:19.39#ibcon#about to read 4, iclass 21, count 0 2006.238.07:20:19.39#ibcon#read 4, iclass 21, count 0 2006.238.07:20:19.39#ibcon#about to read 5, iclass 21, count 0 2006.238.07:20:19.39#ibcon#read 5, iclass 21, count 0 2006.238.07:20:19.39#ibcon#about to read 6, iclass 21, count 0 2006.238.07:20:19.39#ibcon#read 6, iclass 21, count 0 2006.238.07:20:19.39#ibcon#end of sib2, iclass 21, count 0 2006.238.07:20:19.39#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:20:19.39#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:20:19.39#ibcon#[27=USB\r\n] 2006.238.07:20:19.39#ibcon#*before write, iclass 21, count 0 2006.238.07:20:19.39#ibcon#enter sib2, iclass 21, count 0 2006.238.07:20:19.39#ibcon#flushed, iclass 21, count 0 2006.238.07:20:19.39#ibcon#about to write, iclass 21, count 0 2006.238.07:20:19.39#ibcon#wrote, iclass 21, count 0 2006.238.07:20:19.39#ibcon#about to read 3, iclass 21, count 0 2006.238.07:20:19.42#ibcon#read 3, iclass 21, count 0 2006.238.07:20:19.42#ibcon#about to read 4, iclass 21, count 0 2006.238.07:20:19.42#ibcon#read 4, iclass 21, count 0 2006.238.07:20:19.42#ibcon#about to read 5, iclass 21, count 0 2006.238.07:20:19.42#ibcon#read 5, iclass 21, count 0 2006.238.07:20:19.42#ibcon#about to read 6, iclass 21, count 0 2006.238.07:20:19.42#ibcon#read 6, iclass 21, count 0 2006.238.07:20:19.42#ibcon#end of sib2, iclass 21, count 0 2006.238.07:20:19.42#ibcon#*after write, iclass 21, count 0 2006.238.07:20:19.42#ibcon#*before return 0, iclass 21, count 0 2006.238.07:20:19.42#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:20:19.42#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:20:19.42#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:20:19.42#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:20:19.42$vc4f8/vblo=4,712.99 2006.238.07:20:19.43#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:20:19.43#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:20:19.43#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:19.43#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:20:19.43#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:20:19.43#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:20:19.43#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:20:19.43#ibcon#first serial, iclass 23, count 0 2006.238.07:20:19.43#ibcon#enter sib2, iclass 23, count 0 2006.238.07:20:19.43#ibcon#flushed, iclass 23, count 0 2006.238.07:20:19.43#ibcon#about to write, iclass 23, count 0 2006.238.07:20:19.43#ibcon#wrote, iclass 23, count 0 2006.238.07:20:19.43#ibcon#about to read 3, iclass 23, count 0 2006.238.07:20:19.44#ibcon#read 3, iclass 23, count 0 2006.238.07:20:19.44#ibcon#about to read 4, iclass 23, count 0 2006.238.07:20:19.44#ibcon#read 4, iclass 23, count 0 2006.238.07:20:19.44#ibcon#about to read 5, iclass 23, count 0 2006.238.07:20:19.44#ibcon#read 5, iclass 23, count 0 2006.238.07:20:19.44#ibcon#about to read 6, iclass 23, count 0 2006.238.07:20:19.44#ibcon#read 6, iclass 23, count 0 2006.238.07:20:19.44#ibcon#end of sib2, iclass 23, count 0 2006.238.07:20:19.44#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:20:19.44#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:20:19.44#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:20:19.44#ibcon#*before write, iclass 23, count 0 2006.238.07:20:19.44#ibcon#enter sib2, iclass 23, count 0 2006.238.07:20:19.44#ibcon#flushed, iclass 23, count 0 2006.238.07:20:19.44#ibcon#about to write, iclass 23, count 0 2006.238.07:20:19.44#ibcon#wrote, iclass 23, count 0 2006.238.07:20:19.44#ibcon#about to read 3, iclass 23, count 0 2006.238.07:20:19.48#ibcon#read 3, iclass 23, count 0 2006.238.07:20:19.48#ibcon#about to read 4, iclass 23, count 0 2006.238.07:20:19.48#ibcon#read 4, iclass 23, count 0 2006.238.07:20:19.48#ibcon#about to read 5, iclass 23, count 0 2006.238.07:20:19.48#ibcon#read 5, iclass 23, count 0 2006.238.07:20:19.48#ibcon#about to read 6, iclass 23, count 0 2006.238.07:20:19.48#ibcon#read 6, iclass 23, count 0 2006.238.07:20:19.48#ibcon#end of sib2, iclass 23, count 0 2006.238.07:20:19.48#ibcon#*after write, iclass 23, count 0 2006.238.07:20:19.48#ibcon#*before return 0, iclass 23, count 0 2006.238.07:20:19.48#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:20:19.48#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:20:19.48#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:20:19.48#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:20:19.48$vc4f8/vb=4,4 2006.238.07:20:19.49#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.07:20:19.49#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.07:20:19.49#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:19.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:20:19.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:20:19.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:20:19.54#ibcon#enter wrdev, iclass 25, count 2 2006.238.07:20:19.54#ibcon#first serial, iclass 25, count 2 2006.238.07:20:19.54#ibcon#enter sib2, iclass 25, count 2 2006.238.07:20:19.54#ibcon#flushed, iclass 25, count 2 2006.238.07:20:19.54#ibcon#about to write, iclass 25, count 2 2006.238.07:20:19.54#ibcon#wrote, iclass 25, count 2 2006.238.07:20:19.54#ibcon#about to read 3, iclass 25, count 2 2006.238.07:20:19.55#ibcon#read 3, iclass 25, count 2 2006.238.07:20:19.55#ibcon#about to read 4, iclass 25, count 2 2006.238.07:20:19.55#ibcon#read 4, iclass 25, count 2 2006.238.07:20:19.55#ibcon#about to read 5, iclass 25, count 2 2006.238.07:20:19.55#ibcon#read 5, iclass 25, count 2 2006.238.07:20:19.55#ibcon#about to read 6, iclass 25, count 2 2006.238.07:20:19.55#ibcon#read 6, iclass 25, count 2 2006.238.07:20:19.55#ibcon#end of sib2, iclass 25, count 2 2006.238.07:20:19.55#ibcon#*mode == 0, iclass 25, count 2 2006.238.07:20:19.55#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.07:20:19.55#ibcon#[27=AT04-04\r\n] 2006.238.07:20:19.55#ibcon#*before write, iclass 25, count 2 2006.238.07:20:19.55#ibcon#enter sib2, iclass 25, count 2 2006.238.07:20:19.55#ibcon#flushed, iclass 25, count 2 2006.238.07:20:19.55#ibcon#about to write, iclass 25, count 2 2006.238.07:20:19.55#ibcon#wrote, iclass 25, count 2 2006.238.07:20:19.55#ibcon#about to read 3, iclass 25, count 2 2006.238.07:20:19.58#ibcon#read 3, iclass 25, count 2 2006.238.07:20:19.58#ibcon#about to read 4, iclass 25, count 2 2006.238.07:20:19.58#ibcon#read 4, iclass 25, count 2 2006.238.07:20:19.58#ibcon#about to read 5, iclass 25, count 2 2006.238.07:20:19.58#ibcon#read 5, iclass 25, count 2 2006.238.07:20:19.58#ibcon#about to read 6, iclass 25, count 2 2006.238.07:20:19.58#ibcon#read 6, iclass 25, count 2 2006.238.07:20:19.58#ibcon#end of sib2, iclass 25, count 2 2006.238.07:20:19.58#ibcon#*after write, iclass 25, count 2 2006.238.07:20:19.58#ibcon#*before return 0, iclass 25, count 2 2006.238.07:20:19.58#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:20:19.58#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:20:19.58#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.07:20:19.58#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:19.58#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:20:19.70#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:20:19.70#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:20:19.70#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:20:19.70#ibcon#first serial, iclass 25, count 0 2006.238.07:20:19.70#ibcon#enter sib2, iclass 25, count 0 2006.238.07:20:19.70#ibcon#flushed, iclass 25, count 0 2006.238.07:20:19.70#ibcon#about to write, iclass 25, count 0 2006.238.07:20:19.70#ibcon#wrote, iclass 25, count 0 2006.238.07:20:19.70#ibcon#about to read 3, iclass 25, count 0 2006.238.07:20:19.72#ibcon#read 3, iclass 25, count 0 2006.238.07:20:19.72#ibcon#about to read 4, iclass 25, count 0 2006.238.07:20:19.72#ibcon#read 4, iclass 25, count 0 2006.238.07:20:19.72#ibcon#about to read 5, iclass 25, count 0 2006.238.07:20:19.72#ibcon#read 5, iclass 25, count 0 2006.238.07:20:19.72#ibcon#about to read 6, iclass 25, count 0 2006.238.07:20:19.72#ibcon#read 6, iclass 25, count 0 2006.238.07:20:19.72#ibcon#end of sib2, iclass 25, count 0 2006.238.07:20:19.72#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:20:19.72#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:20:19.72#ibcon#[27=USB\r\n] 2006.238.07:20:19.72#ibcon#*before write, iclass 25, count 0 2006.238.07:20:19.72#ibcon#enter sib2, iclass 25, count 0 2006.238.07:20:19.72#ibcon#flushed, iclass 25, count 0 2006.238.07:20:19.72#ibcon#about to write, iclass 25, count 0 2006.238.07:20:19.72#ibcon#wrote, iclass 25, count 0 2006.238.07:20:19.72#ibcon#about to read 3, iclass 25, count 0 2006.238.07:20:19.75#ibcon#read 3, iclass 25, count 0 2006.238.07:20:19.75#ibcon#about to read 4, iclass 25, count 0 2006.238.07:20:19.75#ibcon#read 4, iclass 25, count 0 2006.238.07:20:19.75#ibcon#about to read 5, iclass 25, count 0 2006.238.07:20:19.75#ibcon#read 5, iclass 25, count 0 2006.238.07:20:19.75#ibcon#about to read 6, iclass 25, count 0 2006.238.07:20:19.75#ibcon#read 6, iclass 25, count 0 2006.238.07:20:19.75#ibcon#end of sib2, iclass 25, count 0 2006.238.07:20:19.75#ibcon#*after write, iclass 25, count 0 2006.238.07:20:19.75#ibcon#*before return 0, iclass 25, count 0 2006.238.07:20:19.75#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:20:19.75#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:20:19.75#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:20:19.75#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:20:19.75$vc4f8/vblo=5,744.99 2006.238.07:20:19.76#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:20:19.76#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:20:19.76#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:19.76#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:20:19.76#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:20:19.76#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:20:19.76#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:20:19.76#ibcon#first serial, iclass 27, count 0 2006.238.07:20:19.76#ibcon#enter sib2, iclass 27, count 0 2006.238.07:20:19.76#ibcon#flushed, iclass 27, count 0 2006.238.07:20:19.76#ibcon#about to write, iclass 27, count 0 2006.238.07:20:19.76#ibcon#wrote, iclass 27, count 0 2006.238.07:20:19.76#ibcon#about to read 3, iclass 27, count 0 2006.238.07:20:19.77#ibcon#read 3, iclass 27, count 0 2006.238.07:20:19.77#ibcon#about to read 4, iclass 27, count 0 2006.238.07:20:19.77#ibcon#read 4, iclass 27, count 0 2006.238.07:20:19.77#ibcon#about to read 5, iclass 27, count 0 2006.238.07:20:19.77#ibcon#read 5, iclass 27, count 0 2006.238.07:20:19.77#ibcon#about to read 6, iclass 27, count 0 2006.238.07:20:19.77#ibcon#read 6, iclass 27, count 0 2006.238.07:20:19.77#ibcon#end of sib2, iclass 27, count 0 2006.238.07:20:19.77#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:20:19.77#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:20:19.77#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:20:19.77#ibcon#*before write, iclass 27, count 0 2006.238.07:20:19.77#ibcon#enter sib2, iclass 27, count 0 2006.238.07:20:19.77#ibcon#flushed, iclass 27, count 0 2006.238.07:20:19.77#ibcon#about to write, iclass 27, count 0 2006.238.07:20:19.77#ibcon#wrote, iclass 27, count 0 2006.238.07:20:19.77#ibcon#about to read 3, iclass 27, count 0 2006.238.07:20:19.81#ibcon#read 3, iclass 27, count 0 2006.238.07:20:19.81#ibcon#about to read 4, iclass 27, count 0 2006.238.07:20:19.81#ibcon#read 4, iclass 27, count 0 2006.238.07:20:19.81#ibcon#about to read 5, iclass 27, count 0 2006.238.07:20:19.81#ibcon#read 5, iclass 27, count 0 2006.238.07:20:19.81#ibcon#about to read 6, iclass 27, count 0 2006.238.07:20:19.81#ibcon#read 6, iclass 27, count 0 2006.238.07:20:19.81#ibcon#end of sib2, iclass 27, count 0 2006.238.07:20:19.81#ibcon#*after write, iclass 27, count 0 2006.238.07:20:19.81#ibcon#*before return 0, iclass 27, count 0 2006.238.07:20:19.81#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:20:19.81#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:20:19.81#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:20:19.81#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:20:19.81$vc4f8/vb=5,4 2006.238.07:20:19.82#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.07:20:19.82#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.07:20:19.82#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:19.82#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:20:19.86#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:20:19.86#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:20:19.86#ibcon#enter wrdev, iclass 29, count 2 2006.238.07:20:19.86#ibcon#first serial, iclass 29, count 2 2006.238.07:20:19.86#ibcon#enter sib2, iclass 29, count 2 2006.238.07:20:19.86#ibcon#flushed, iclass 29, count 2 2006.238.07:20:19.86#ibcon#about to write, iclass 29, count 2 2006.238.07:20:19.86#ibcon#wrote, iclass 29, count 2 2006.238.07:20:19.86#ibcon#about to read 3, iclass 29, count 2 2006.238.07:20:19.88#ibcon#read 3, iclass 29, count 2 2006.238.07:20:19.88#ibcon#about to read 4, iclass 29, count 2 2006.238.07:20:19.88#ibcon#read 4, iclass 29, count 2 2006.238.07:20:19.88#ibcon#about to read 5, iclass 29, count 2 2006.238.07:20:19.88#ibcon#read 5, iclass 29, count 2 2006.238.07:20:19.88#ibcon#about to read 6, iclass 29, count 2 2006.238.07:20:19.88#ibcon#read 6, iclass 29, count 2 2006.238.07:20:19.88#ibcon#end of sib2, iclass 29, count 2 2006.238.07:20:19.88#ibcon#*mode == 0, iclass 29, count 2 2006.238.07:20:19.88#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.07:20:19.88#ibcon#[27=AT05-04\r\n] 2006.238.07:20:19.88#ibcon#*before write, iclass 29, count 2 2006.238.07:20:19.88#ibcon#enter sib2, iclass 29, count 2 2006.238.07:20:19.88#ibcon#flushed, iclass 29, count 2 2006.238.07:20:19.88#ibcon#about to write, iclass 29, count 2 2006.238.07:20:19.88#ibcon#wrote, iclass 29, count 2 2006.238.07:20:19.88#ibcon#about to read 3, iclass 29, count 2 2006.238.07:20:19.91#ibcon#read 3, iclass 29, count 2 2006.238.07:20:19.91#ibcon#about to read 4, iclass 29, count 2 2006.238.07:20:19.91#ibcon#read 4, iclass 29, count 2 2006.238.07:20:19.91#ibcon#about to read 5, iclass 29, count 2 2006.238.07:20:19.91#ibcon#read 5, iclass 29, count 2 2006.238.07:20:19.91#ibcon#about to read 6, iclass 29, count 2 2006.238.07:20:19.91#ibcon#read 6, iclass 29, count 2 2006.238.07:20:19.91#ibcon#end of sib2, iclass 29, count 2 2006.238.07:20:19.91#ibcon#*after write, iclass 29, count 2 2006.238.07:20:19.91#ibcon#*before return 0, iclass 29, count 2 2006.238.07:20:19.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:20:19.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:20:19.91#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.07:20:19.91#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:19.91#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:20:20.03#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:20:20.03#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:20:20.03#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:20:20.03#ibcon#first serial, iclass 29, count 0 2006.238.07:20:20.03#ibcon#enter sib2, iclass 29, count 0 2006.238.07:20:20.03#ibcon#flushed, iclass 29, count 0 2006.238.07:20:20.03#ibcon#about to write, iclass 29, count 0 2006.238.07:20:20.03#ibcon#wrote, iclass 29, count 0 2006.238.07:20:20.03#ibcon#about to read 3, iclass 29, count 0 2006.238.07:20:20.05#ibcon#read 3, iclass 29, count 0 2006.238.07:20:20.05#ibcon#about to read 4, iclass 29, count 0 2006.238.07:20:20.05#ibcon#read 4, iclass 29, count 0 2006.238.07:20:20.05#ibcon#about to read 5, iclass 29, count 0 2006.238.07:20:20.05#ibcon#read 5, iclass 29, count 0 2006.238.07:20:20.05#ibcon#about to read 6, iclass 29, count 0 2006.238.07:20:20.05#ibcon#read 6, iclass 29, count 0 2006.238.07:20:20.05#ibcon#end of sib2, iclass 29, count 0 2006.238.07:20:20.05#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:20:20.05#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:20:20.05#ibcon#[27=USB\r\n] 2006.238.07:20:20.05#ibcon#*before write, iclass 29, count 0 2006.238.07:20:20.05#ibcon#enter sib2, iclass 29, count 0 2006.238.07:20:20.05#ibcon#flushed, iclass 29, count 0 2006.238.07:20:20.05#ibcon#about to write, iclass 29, count 0 2006.238.07:20:20.05#ibcon#wrote, iclass 29, count 0 2006.238.07:20:20.05#ibcon#about to read 3, iclass 29, count 0 2006.238.07:20:20.08#ibcon#read 3, iclass 29, count 0 2006.238.07:20:20.08#ibcon#about to read 4, iclass 29, count 0 2006.238.07:20:20.08#ibcon#read 4, iclass 29, count 0 2006.238.07:20:20.08#ibcon#about to read 5, iclass 29, count 0 2006.238.07:20:20.08#ibcon#read 5, iclass 29, count 0 2006.238.07:20:20.08#ibcon#about to read 6, iclass 29, count 0 2006.238.07:20:20.08#ibcon#read 6, iclass 29, count 0 2006.238.07:20:20.08#ibcon#end of sib2, iclass 29, count 0 2006.238.07:20:20.08#ibcon#*after write, iclass 29, count 0 2006.238.07:20:20.08#ibcon#*before return 0, iclass 29, count 0 2006.238.07:20:20.08#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:20:20.08#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:20:20.08#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:20:20.08#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:20:20.08$vc4f8/vblo=6,752.99 2006.238.07:20:20.08#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.07:20:20.08#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.07:20:20.08#ibcon#ireg 17 cls_cnt 0 2006.238.07:20:20.08#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:20:20.08#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:20:20.09#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:20:20.09#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:20:20.09#ibcon#first serial, iclass 31, count 0 2006.238.07:20:20.09#ibcon#enter sib2, iclass 31, count 0 2006.238.07:20:20.09#ibcon#flushed, iclass 31, count 0 2006.238.07:20:20.09#ibcon#about to write, iclass 31, count 0 2006.238.07:20:20.09#ibcon#wrote, iclass 31, count 0 2006.238.07:20:20.09#ibcon#about to read 3, iclass 31, count 0 2006.238.07:20:20.10#ibcon#read 3, iclass 31, count 0 2006.238.07:20:20.10#ibcon#about to read 4, iclass 31, count 0 2006.238.07:20:20.10#ibcon#read 4, iclass 31, count 0 2006.238.07:20:20.10#ibcon#about to read 5, iclass 31, count 0 2006.238.07:20:20.10#ibcon#read 5, iclass 31, count 0 2006.238.07:20:20.10#ibcon#about to read 6, iclass 31, count 0 2006.238.07:20:20.10#ibcon#read 6, iclass 31, count 0 2006.238.07:20:20.10#ibcon#end of sib2, iclass 31, count 0 2006.238.07:20:20.10#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:20:20.10#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:20:20.10#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:20:20.10#ibcon#*before write, iclass 31, count 0 2006.238.07:20:20.10#ibcon#enter sib2, iclass 31, count 0 2006.238.07:20:20.10#ibcon#flushed, iclass 31, count 0 2006.238.07:20:20.10#ibcon#about to write, iclass 31, count 0 2006.238.07:20:20.10#ibcon#wrote, iclass 31, count 0 2006.238.07:20:20.10#ibcon#about to read 3, iclass 31, count 0 2006.238.07:20:20.14#ibcon#read 3, iclass 31, count 0 2006.238.07:20:20.14#ibcon#about to read 4, iclass 31, count 0 2006.238.07:20:20.14#ibcon#read 4, iclass 31, count 0 2006.238.07:20:20.14#ibcon#about to read 5, iclass 31, count 0 2006.238.07:20:20.14#ibcon#read 5, iclass 31, count 0 2006.238.07:20:20.14#ibcon#about to read 6, iclass 31, count 0 2006.238.07:20:20.14#ibcon#read 6, iclass 31, count 0 2006.238.07:20:20.14#ibcon#end of sib2, iclass 31, count 0 2006.238.07:20:20.14#ibcon#*after write, iclass 31, count 0 2006.238.07:20:20.14#ibcon#*before return 0, iclass 31, count 0 2006.238.07:20:20.14#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:20:20.14#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:20:20.14#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:20:20.14#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:20:20.14$vc4f8/vb=6,4 2006.238.07:20:20.14#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:20:20.14#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:20:20.15#ibcon#ireg 11 cls_cnt 2 2006.238.07:20:20.15#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:20:20.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:20:20.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:20:20.19#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:20:20.19#ibcon#first serial, iclass 33, count 2 2006.238.07:20:20.19#ibcon#enter sib2, iclass 33, count 2 2006.238.07:20:20.19#ibcon#flushed, iclass 33, count 2 2006.238.07:20:20.19#ibcon#about to write, iclass 33, count 2 2006.238.07:20:20.19#ibcon#wrote, iclass 33, count 2 2006.238.07:20:20.19#ibcon#about to read 3, iclass 33, count 2 2006.238.07:20:20.21#ibcon#read 3, iclass 33, count 2 2006.238.07:20:20.21#ibcon#about to read 4, iclass 33, count 2 2006.238.07:20:20.21#ibcon#read 4, iclass 33, count 2 2006.238.07:20:20.21#ibcon#about to read 5, iclass 33, count 2 2006.238.07:20:20.21#ibcon#read 5, iclass 33, count 2 2006.238.07:20:20.21#ibcon#about to read 6, iclass 33, count 2 2006.238.07:20:20.21#ibcon#read 6, iclass 33, count 2 2006.238.07:20:20.21#ibcon#end of sib2, iclass 33, count 2 2006.238.07:20:20.21#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:20:20.21#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:20:20.21#ibcon#[27=AT06-04\r\n] 2006.238.07:20:20.21#ibcon#*before write, iclass 33, count 2 2006.238.07:20:20.21#ibcon#enter sib2, iclass 33, count 2 2006.238.07:20:20.21#ibcon#flushed, iclass 33, count 2 2006.238.07:20:20.21#ibcon#about to write, iclass 33, count 2 2006.238.07:20:20.21#ibcon#wrote, iclass 33, count 2 2006.238.07:20:20.21#ibcon#about to read 3, iclass 33, count 2 2006.238.07:20:20.24#ibcon#read 3, iclass 33, count 2 2006.238.07:20:20.24#ibcon#about to read 4, iclass 33, count 2 2006.238.07:20:20.24#ibcon#read 4, iclass 33, count 2 2006.238.07:20:20.24#ibcon#about to read 5, iclass 33, count 2 2006.238.07:20:20.24#ibcon#read 5, iclass 33, count 2 2006.238.07:20:20.24#ibcon#about to read 6, iclass 33, count 2 2006.238.07:20:20.24#ibcon#read 6, iclass 33, count 2 2006.238.07:20:20.24#ibcon#end of sib2, iclass 33, count 2 2006.238.07:20:20.24#ibcon#*after write, iclass 33, count 2 2006.238.07:20:20.24#ibcon#*before return 0, iclass 33, count 2 2006.238.07:20:20.24#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:20:20.24#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:20:20.24#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:20:20.24#ibcon#ireg 7 cls_cnt 0 2006.238.07:20:20.24#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:20:20.38#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:20:20.38#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:20:20.38#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:20:20.38#ibcon#first serial, iclass 33, count 0 2006.238.07:20:20.38#ibcon#enter sib2, iclass 33, count 0 2006.238.07:20:20.38#ibcon#flushed, iclass 33, count 0 2006.238.07:20:20.38#ibcon#about to write, iclass 33, count 0 2006.238.07:20:20.38#ibcon#wrote, iclass 33, count 0 2006.238.07:20:20.38#ibcon#about to read 3, iclass 33, count 0 2006.238.07:20:20.39#ibcon#read 3, iclass 33, count 0 2006.238.07:20:20.39#ibcon#about to read 4, iclass 33, count 0 2006.238.07:20:20.39#ibcon#read 4, iclass 33, count 0 2006.238.07:20:20.39#ibcon#about to read 5, iclass 33, count 0 2006.238.07:20:20.39#ibcon#read 5, iclass 33, count 0 2006.238.07:20:20.39#ibcon#about to read 6, iclass 33, count 0 2006.238.07:20:20.39#ibcon#read 6, iclass 33, count 0 2006.238.07:20:20.39#ibcon#end of sib2, iclass 33, count 0 2006.238.07:20:20.39#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:20:20.39#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:20:20.39#ibcon#[27=USB\r\n] 2006.238.07:20:20.39#ibcon#*before write, iclass 33, count 0 2006.238.07:20:20.39#ibcon#enter sib2, iclass 33, count 0 2006.238.07:20:20.39#ibcon#flushed, iclass 33, count 0 2006.238.07:20:20.39#ibcon#about to write, iclass 33, count 0 2006.238.07:20:20.39#ibcon#wrote, iclass 33, count 0 2006.238.07:20:20.39#ibcon#about to read 3, iclass 33, count 0 2006.238.07:20:20.42#ibcon#read 3, iclass 33, count 0 2006.238.07:20:20.42#ibcon#about to read 4, iclass 33, count 0 2006.238.07:20:20.42#ibcon#read 4, iclass 33, count 0 2006.238.07:20:20.42#ibcon#about to read 5, iclass 33, count 0 2006.238.07:20:20.42#ibcon#read 5, iclass 33, count 0 2006.238.07:20:20.42#ibcon#about to read 6, iclass 33, count 0 2006.238.07:20:20.42#ibcon#read 6, iclass 33, count 0 2006.238.07:20:20.42#ibcon#end of sib2, iclass 33, count 0 2006.238.07:20:20.42#ibcon#*after write, iclass 33, count 0 2006.238.07:20:20.42#ibcon#*before return 0, iclass 33, count 0 2006.238.07:20:20.42#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:20:20.42#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:20:20.42#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:20:20.42#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:20:20.42$vc4f8/vabw=wide 2006.238.07:20:20.42#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:20:20.42#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:20:20.42#ibcon#ireg 8 cls_cnt 0 2006.238.07:20:20.43#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:20:20.43#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:20:20.43#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:20:20.43#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:20:20.43#ibcon#first serial, iclass 35, count 0 2006.238.07:20:20.43#ibcon#enter sib2, iclass 35, count 0 2006.238.07:20:20.43#ibcon#flushed, iclass 35, count 0 2006.238.07:20:20.43#ibcon#about to write, iclass 35, count 0 2006.238.07:20:20.43#ibcon#wrote, iclass 35, count 0 2006.238.07:20:20.43#ibcon#about to read 3, iclass 35, count 0 2006.238.07:20:20.44#ibcon#read 3, iclass 35, count 0 2006.238.07:20:20.44#ibcon#about to read 4, iclass 35, count 0 2006.238.07:20:20.44#ibcon#read 4, iclass 35, count 0 2006.238.07:20:20.44#ibcon#about to read 5, iclass 35, count 0 2006.238.07:20:20.44#ibcon#read 5, iclass 35, count 0 2006.238.07:20:20.44#ibcon#about to read 6, iclass 35, count 0 2006.238.07:20:20.44#ibcon#read 6, iclass 35, count 0 2006.238.07:20:20.44#ibcon#end of sib2, iclass 35, count 0 2006.238.07:20:20.44#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:20:20.44#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:20:20.44#ibcon#[25=BW32\r\n] 2006.238.07:20:20.44#ibcon#*before write, iclass 35, count 0 2006.238.07:20:20.44#ibcon#enter sib2, iclass 35, count 0 2006.238.07:20:20.44#ibcon#flushed, iclass 35, count 0 2006.238.07:20:20.44#ibcon#about to write, iclass 35, count 0 2006.238.07:20:20.44#ibcon#wrote, iclass 35, count 0 2006.238.07:20:20.44#ibcon#about to read 3, iclass 35, count 0 2006.238.07:20:20.47#ibcon#read 3, iclass 35, count 0 2006.238.07:20:20.47#ibcon#about to read 4, iclass 35, count 0 2006.238.07:20:20.47#ibcon#read 4, iclass 35, count 0 2006.238.07:20:20.47#ibcon#about to read 5, iclass 35, count 0 2006.238.07:20:20.47#ibcon#read 5, iclass 35, count 0 2006.238.07:20:20.47#ibcon#about to read 6, iclass 35, count 0 2006.238.07:20:20.47#ibcon#read 6, iclass 35, count 0 2006.238.07:20:20.47#ibcon#end of sib2, iclass 35, count 0 2006.238.07:20:20.47#ibcon#*after write, iclass 35, count 0 2006.238.07:20:20.47#ibcon#*before return 0, iclass 35, count 0 2006.238.07:20:20.47#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:20:20.47#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:20:20.47#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:20:20.47#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:20:20.47$vc4f8/vbbw=wide 2006.238.07:20:20.48#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.07:20:20.48#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.07:20:20.48#ibcon#ireg 8 cls_cnt 0 2006.238.07:20:20.48#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:20:20.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:20:20.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:20:20.53#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:20:20.53#ibcon#first serial, iclass 37, count 0 2006.238.07:20:20.53#ibcon#enter sib2, iclass 37, count 0 2006.238.07:20:20.53#ibcon#flushed, iclass 37, count 0 2006.238.07:20:20.53#ibcon#about to write, iclass 37, count 0 2006.238.07:20:20.53#ibcon#wrote, iclass 37, count 0 2006.238.07:20:20.53#ibcon#about to read 3, iclass 37, count 0 2006.238.07:20:20.55#ibcon#read 3, iclass 37, count 0 2006.238.07:20:20.55#ibcon#about to read 4, iclass 37, count 0 2006.238.07:20:20.55#ibcon#read 4, iclass 37, count 0 2006.238.07:20:20.55#ibcon#about to read 5, iclass 37, count 0 2006.238.07:20:20.55#ibcon#read 5, iclass 37, count 0 2006.238.07:20:20.55#ibcon#about to read 6, iclass 37, count 0 2006.238.07:20:20.55#ibcon#read 6, iclass 37, count 0 2006.238.07:20:20.55#ibcon#end of sib2, iclass 37, count 0 2006.238.07:20:20.55#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:20:20.55#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:20:20.55#ibcon#[27=BW32\r\n] 2006.238.07:20:20.55#ibcon#*before write, iclass 37, count 0 2006.238.07:20:20.55#ibcon#enter sib2, iclass 37, count 0 2006.238.07:20:20.55#ibcon#flushed, iclass 37, count 0 2006.238.07:20:20.55#ibcon#about to write, iclass 37, count 0 2006.238.07:20:20.55#ibcon#wrote, iclass 37, count 0 2006.238.07:20:20.55#ibcon#about to read 3, iclass 37, count 0 2006.238.07:20:20.58#ibcon#read 3, iclass 37, count 0 2006.238.07:20:20.58#ibcon#about to read 4, iclass 37, count 0 2006.238.07:20:20.58#ibcon#read 4, iclass 37, count 0 2006.238.07:20:20.58#ibcon#about to read 5, iclass 37, count 0 2006.238.07:20:20.58#ibcon#read 5, iclass 37, count 0 2006.238.07:20:20.58#ibcon#about to read 6, iclass 37, count 0 2006.238.07:20:20.58#ibcon#read 6, iclass 37, count 0 2006.238.07:20:20.58#ibcon#end of sib2, iclass 37, count 0 2006.238.07:20:20.58#ibcon#*after write, iclass 37, count 0 2006.238.07:20:20.58#ibcon#*before return 0, iclass 37, count 0 2006.238.07:20:20.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:20:20.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:20:20.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:20:20.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:20:20.58$4f8m12a/ifd4f 2006.238.07:20:20.58&ifd4f/lo= 2006.238.07:20:20.58&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:20:20.58&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:20:20.58&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:20:20.58&ifd4f/patch= 2006.238.07:20:20.59&ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:20:20.59&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:20:20.59&ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:20:20.59$ifd4f/lo= 2006.238.07:20:20.59$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:20:20.59$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:20:20.59$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:20:20.59$ifd4f/patch= 2006.238.07:20:20.59$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:20:20.59$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:20:20.59$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:20:20.59$4f8m12a/"form=m,16.000,1:2 2006.238.07:20:20.59$4f8m12a/"tpicd 2006.238.07:20:20.59$4f8m12a/echo=off 2006.238.07:20:20.59$4f8m12a/xlog=off 2006.238.07:20:20.59:!2006.238.07:29:50 2006.238.07:20:36.14#trakl#Source acquired 2006.238.07:20:38.14#flagr#flagr/antenna,acquired 2006.238.07:29:50.00:preob 2006.238.07:29:50.00&preob/onsource 2006.238.07:29:51.14/onsource/TRACKING 2006.238.07:29:51.14:!2006.238.07:30:00 2006.238.07:30:00.00:data_valid=on 2006.238.07:30:00.00:midob 2006.238.07:30:00.00&midob/onsource 2006.238.07:30:00.00&midob/wx 2006.238.07:30:00.00&midob/cable 2006.238.07:30:00.00&midob/va 2006.238.07:30:00.00&midob/valo 2006.238.07:30:00.00&midob/vb 2006.238.07:30:00.00&midob/vblo 2006.238.07:30:00.00&midob/vabw 2006.238.07:30:00.00&midob/vbbw 2006.238.07:30:00.00&midob/"form 2006.238.07:30:00.00&midob/xfe 2006.238.07:30:00.00&midob/ifatt 2006.238.07:30:00.00&midob/clockoff 2006.238.07:30:00.00&midob/sy=logmail 2006.238.07:30:00.00&midob/"sy=run setcl adapt & 2006.238.07:30:00.14/onsource/TRACKING 2006.238.07:30:00.14/wx/25.36,1012.2,91 2006.238.07:30:00.29/cable/+6.4179E-03 2006.238.07:30:01.38/va/01,08,usb,yes,32,34 2006.238.07:30:01.38/va/02,07,usb,yes,32,34 2006.238.07:30:01.38/va/03,07,usb,yes,30,30 2006.238.07:30:01.38/va/04,07,usb,yes,33,36 2006.238.07:30:01.38/va/05,08,usb,yes,31,33 2006.238.07:30:01.38/va/06,07,usb,yes,34,34 2006.238.07:30:01.38/va/07,07,usb,yes,34,34 2006.238.07:30:01.38/va/08,07,usb,yes,36,36 2006.238.07:30:01.61/valo/01,532.99,yes,locked 2006.238.07:30:01.61/valo/02,572.99,yes,locked 2006.238.07:30:01.61/valo/03,672.99,yes,locked 2006.238.07:30:01.61/valo/04,832.99,yes,locked 2006.238.07:30:01.61/valo/05,652.99,yes,locked 2006.238.07:30:01.61/valo/06,772.99,yes,locked 2006.238.07:30:01.61/valo/07,832.99,yes,locked 2006.238.07:30:01.61/valo/08,852.99,yes,locked 2006.238.07:30:02.70/vb/01,04,usb,yes,31,30 2006.238.07:30:02.70/vb/02,04,usb,yes,33,34 2006.238.07:30:02.70/vb/03,04,usb,yes,29,33 2006.238.07:30:02.70/vb/04,04,usb,yes,30,30 2006.238.07:30:02.70/vb/05,04,usb,yes,29,33 2006.238.07:30:02.70/vb/06,04,usb,yes,30,32 2006.238.07:30:02.70/vb/07,04,usb,yes,32,32 2006.238.07:30:02.70/vb/08,04,usb,yes,29,33 2006.238.07:30:02.94/vblo/01,632.99,yes,locked 2006.238.07:30:02.94/vblo/02,640.99,yes,locked 2006.238.07:30:02.94/vblo/03,656.99,yes,locked 2006.238.07:30:02.94/vblo/04,712.99,yes,locked 2006.238.07:30:02.94/vblo/05,744.99,yes,locked 2006.238.07:30:02.94/vblo/06,752.99,yes,locked 2006.238.07:30:02.94/vblo/07,734.99,yes,locked 2006.238.07:30:02.94/vblo/08,744.99,yes,locked 2006.238.07:30:03.09/vabw/8 2006.238.07:30:03.24/vbbw/8 2006.238.07:30:03.33/xfe/off,on,13.2 2006.238.07:30:03.71/ifatt/23,28,28,28 2006.238.07:30:04.07/fmout-gps/S +4.36E-07 2006.238.07:30:04.16:!2006.238.07:31:00 2006.238.07:31:00.00:data_valid=off 2006.238.07:31:00.01:postob 2006.238.07:31:00.01&postob/cable 2006.238.07:31:00.01&postob/wx 2006.238.07:31:00.02&postob/clockoff 2006.238.07:31:00.09/cable/+6.4170E-03 2006.238.07:31:00.10/wx/25.36,1012.2,91 2006.238.07:31:00.18/fmout-gps/S +4.36E-07 2006.238.07:31:00.18:scan_name=238-0733,k06238,60 2006.238.07:31:00.19:source=oj287,085448.87,200630.6,2000.0,ccw 2006.238.07:31:01.14#flagr#flagr/antenna,new-source 2006.238.07:31:01.15:checkk5 2006.238.07:31:01.15&checkk5/chk_autoobs=1 2006.238.07:31:01.15&checkk5/chk_autoobs=2 2006.238.07:31:01.16&checkk5/chk_autoobs=3 2006.238.07:31:01.16&checkk5/chk_autoobs=4 2006.238.07:31:01.17&checkk5/chk_obsdata=1 2006.238.07:31:01.17&checkk5/chk_obsdata=2 2006.238.07:31:01.17&checkk5/chk_obsdata=3 2006.238.07:31:01.18&checkk5/chk_obsdata=4 2006.238.07:31:01.18&checkk5/k5log=1 2006.238.07:31:01.21&checkk5/k5log=2 2006.238.07:31:01.21&checkk5/k5log=3 2006.238.07:31:01.21&checkk5/k5log=4 2006.238.07:31:01.21&checkk5/obsinfo 2006.238.07:31:01.58/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:31:01.97/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:31:02.37/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:31:02.77/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:31:03.14/chk_obsdata//k5ts1/T2380730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:31:03.51/chk_obsdata//k5ts2/T2380730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:31:03.88/chk_obsdata//k5ts3/T2380730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:31:04.25/chk_obsdata//k5ts4/T2380730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:31:04.96/k5log//k5ts1_log_newline 2006.238.07:31:05.65/k5log//k5ts2_log_newline 2006.238.07:31:06.34/k5log//k5ts3_log_newline 2006.238.07:31:07.03/k5log//k5ts4_log_newline 2006.238.07:31:07.09/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:31:07.09:4f8m12a=1 2006.238.07:31:07.09$4f8m12a/echo=on 2006.238.07:31:07.09$4f8m12a/pcalon 2006.238.07:31:07.09$pcalon/"no phase cal control is implemented here 2006.238.07:31:07.09$4f8m12a/"tpicd=stop 2006.238.07:31:07.09$4f8m12a/vc4f8 2006.238.07:31:07.09$vc4f8/valo=1,532.99 2006.238.07:31:07.09#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.07:31:07.09#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.07:31:07.09#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:07.09#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:31:07.09#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:31:07.09#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:31:07.09#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:31:07.09#ibcon#first serial, iclass 39, count 0 2006.238.07:31:07.09#ibcon#enter sib2, iclass 39, count 0 2006.238.07:31:07.09#ibcon#flushed, iclass 39, count 0 2006.238.07:31:07.09#ibcon#about to write, iclass 39, count 0 2006.238.07:31:07.09#ibcon#wrote, iclass 39, count 0 2006.238.07:31:07.09#ibcon#about to read 3, iclass 39, count 0 2006.238.07:31:07.11#ibcon#read 3, iclass 39, count 0 2006.238.07:31:07.11#ibcon#about to read 4, iclass 39, count 0 2006.238.07:31:07.11#ibcon#read 4, iclass 39, count 0 2006.238.07:31:07.11#ibcon#about to read 5, iclass 39, count 0 2006.238.07:31:07.11#ibcon#read 5, iclass 39, count 0 2006.238.07:31:07.11#ibcon#about to read 6, iclass 39, count 0 2006.238.07:31:07.11#ibcon#read 6, iclass 39, count 0 2006.238.07:31:07.11#ibcon#end of sib2, iclass 39, count 0 2006.238.07:31:07.11#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:31:07.11#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:31:07.11#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:31:07.11#ibcon#*before write, iclass 39, count 0 2006.238.07:31:07.11#ibcon#enter sib2, iclass 39, count 0 2006.238.07:31:07.11#ibcon#flushed, iclass 39, count 0 2006.238.07:31:07.11#ibcon#about to write, iclass 39, count 0 2006.238.07:31:07.11#ibcon#wrote, iclass 39, count 0 2006.238.07:31:07.11#ibcon#about to read 3, iclass 39, count 0 2006.238.07:31:07.17#ibcon#read 3, iclass 39, count 0 2006.238.07:31:07.17#ibcon#about to read 4, iclass 39, count 0 2006.238.07:31:07.17#ibcon#read 4, iclass 39, count 0 2006.238.07:31:07.17#ibcon#about to read 5, iclass 39, count 0 2006.238.07:31:07.17#ibcon#read 5, iclass 39, count 0 2006.238.07:31:07.17#ibcon#about to read 6, iclass 39, count 0 2006.238.07:31:07.17#ibcon#read 6, iclass 39, count 0 2006.238.07:31:07.17#ibcon#end of sib2, iclass 39, count 0 2006.238.07:31:07.17#ibcon#*after write, iclass 39, count 0 2006.238.07:31:07.17#ibcon#*before return 0, iclass 39, count 0 2006.238.07:31:07.17#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:31:07.17#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:31:07.17#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:31:07.17#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:31:07.17$vc4f8/va=1,8 2006.238.07:31:07.17#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.07:31:07.17#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.07:31:07.17#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:07.17#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:31:07.17#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:31:07.17#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:31:07.17#ibcon#enter wrdev, iclass 3, count 2 2006.238.07:31:07.17#ibcon#first serial, iclass 3, count 2 2006.238.07:31:07.17#ibcon#enter sib2, iclass 3, count 2 2006.238.07:31:07.17#ibcon#flushed, iclass 3, count 2 2006.238.07:31:07.17#ibcon#about to write, iclass 3, count 2 2006.238.07:31:07.17#ibcon#wrote, iclass 3, count 2 2006.238.07:31:07.17#ibcon#about to read 3, iclass 3, count 2 2006.238.07:31:07.19#ibcon#read 3, iclass 3, count 2 2006.238.07:31:07.19#ibcon#about to read 4, iclass 3, count 2 2006.238.07:31:07.19#ibcon#read 4, iclass 3, count 2 2006.238.07:31:07.19#ibcon#about to read 5, iclass 3, count 2 2006.238.07:31:07.19#ibcon#read 5, iclass 3, count 2 2006.238.07:31:07.19#ibcon#about to read 6, iclass 3, count 2 2006.238.07:31:07.19#ibcon#read 6, iclass 3, count 2 2006.238.07:31:07.19#ibcon#end of sib2, iclass 3, count 2 2006.238.07:31:07.19#ibcon#*mode == 0, iclass 3, count 2 2006.238.07:31:07.19#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.07:31:07.19#ibcon#[25=AT01-08\r\n] 2006.238.07:31:07.19#ibcon#*before write, iclass 3, count 2 2006.238.07:31:07.19#ibcon#enter sib2, iclass 3, count 2 2006.238.07:31:07.19#ibcon#flushed, iclass 3, count 2 2006.238.07:31:07.19#ibcon#about to write, iclass 3, count 2 2006.238.07:31:07.19#ibcon#wrote, iclass 3, count 2 2006.238.07:31:07.19#ibcon#about to read 3, iclass 3, count 2 2006.238.07:31:07.22#ibcon#read 3, iclass 3, count 2 2006.238.07:31:07.22#ibcon#about to read 4, iclass 3, count 2 2006.238.07:31:07.22#ibcon#read 4, iclass 3, count 2 2006.238.07:31:07.22#ibcon#about to read 5, iclass 3, count 2 2006.238.07:31:07.22#ibcon#read 5, iclass 3, count 2 2006.238.07:31:07.22#ibcon#about to read 6, iclass 3, count 2 2006.238.07:31:07.22#ibcon#read 6, iclass 3, count 2 2006.238.07:31:07.22#ibcon#end of sib2, iclass 3, count 2 2006.238.07:31:07.22#ibcon#*after write, iclass 3, count 2 2006.238.07:31:07.22#ibcon#*before return 0, iclass 3, count 2 2006.238.07:31:07.22#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:31:07.22#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:31:07.22#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.07:31:07.22#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:07.22#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:31:07.34#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:31:07.34#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:31:07.34#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:31:07.34#ibcon#first serial, iclass 3, count 0 2006.238.07:31:07.34#ibcon#enter sib2, iclass 3, count 0 2006.238.07:31:07.34#ibcon#flushed, iclass 3, count 0 2006.238.07:31:07.34#ibcon#about to write, iclass 3, count 0 2006.238.07:31:07.34#ibcon#wrote, iclass 3, count 0 2006.238.07:31:07.34#ibcon#about to read 3, iclass 3, count 0 2006.238.07:31:07.36#ibcon#read 3, iclass 3, count 0 2006.238.07:31:07.36#ibcon#about to read 4, iclass 3, count 0 2006.238.07:31:07.36#ibcon#read 4, iclass 3, count 0 2006.238.07:31:07.36#ibcon#about to read 5, iclass 3, count 0 2006.238.07:31:07.36#ibcon#read 5, iclass 3, count 0 2006.238.07:31:07.36#ibcon#about to read 6, iclass 3, count 0 2006.238.07:31:07.36#ibcon#read 6, iclass 3, count 0 2006.238.07:31:07.36#ibcon#end of sib2, iclass 3, count 0 2006.238.07:31:07.36#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:31:07.36#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:31:07.36#ibcon#[25=USB\r\n] 2006.238.07:31:07.36#ibcon#*before write, iclass 3, count 0 2006.238.07:31:07.36#ibcon#enter sib2, iclass 3, count 0 2006.238.07:31:07.36#ibcon#flushed, iclass 3, count 0 2006.238.07:31:07.36#ibcon#about to write, iclass 3, count 0 2006.238.07:31:07.36#ibcon#wrote, iclass 3, count 0 2006.238.07:31:07.36#ibcon#about to read 3, iclass 3, count 0 2006.238.07:31:07.39#ibcon#read 3, iclass 3, count 0 2006.238.07:31:07.39#ibcon#about to read 4, iclass 3, count 0 2006.238.07:31:07.39#ibcon#read 4, iclass 3, count 0 2006.238.07:31:07.39#ibcon#about to read 5, iclass 3, count 0 2006.238.07:31:07.39#ibcon#read 5, iclass 3, count 0 2006.238.07:31:07.39#ibcon#about to read 6, iclass 3, count 0 2006.238.07:31:07.39#ibcon#read 6, iclass 3, count 0 2006.238.07:31:07.39#ibcon#end of sib2, iclass 3, count 0 2006.238.07:31:07.39#ibcon#*after write, iclass 3, count 0 2006.238.07:31:07.39#ibcon#*before return 0, iclass 3, count 0 2006.238.07:31:07.39#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:31:07.39#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:31:07.39#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:31:07.39#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:31:07.39$vc4f8/valo=2,572.99 2006.238.07:31:07.39#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.07:31:07.39#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.07:31:07.39#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:07.39#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:31:07.39#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:31:07.39#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:31:07.39#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:31:07.39#ibcon#first serial, iclass 5, count 0 2006.238.07:31:07.39#ibcon#enter sib2, iclass 5, count 0 2006.238.07:31:07.39#ibcon#flushed, iclass 5, count 0 2006.238.07:31:07.39#ibcon#about to write, iclass 5, count 0 2006.238.07:31:07.39#ibcon#wrote, iclass 5, count 0 2006.238.07:31:07.39#ibcon#about to read 3, iclass 5, count 0 2006.238.07:31:07.41#ibcon#read 3, iclass 5, count 0 2006.238.07:31:07.41#ibcon#about to read 4, iclass 5, count 0 2006.238.07:31:07.41#ibcon#read 4, iclass 5, count 0 2006.238.07:31:07.41#ibcon#about to read 5, iclass 5, count 0 2006.238.07:31:07.41#ibcon#read 5, iclass 5, count 0 2006.238.07:31:07.41#ibcon#about to read 6, iclass 5, count 0 2006.238.07:31:07.41#ibcon#read 6, iclass 5, count 0 2006.238.07:31:07.41#ibcon#end of sib2, iclass 5, count 0 2006.238.07:31:07.41#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:31:07.41#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:31:07.41#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:31:07.41#ibcon#*before write, iclass 5, count 0 2006.238.07:31:07.41#ibcon#enter sib2, iclass 5, count 0 2006.238.07:31:07.41#ibcon#flushed, iclass 5, count 0 2006.238.07:31:07.41#ibcon#about to write, iclass 5, count 0 2006.238.07:31:07.41#ibcon#wrote, iclass 5, count 0 2006.238.07:31:07.41#ibcon#about to read 3, iclass 5, count 0 2006.238.07:31:07.45#ibcon#read 3, iclass 5, count 0 2006.238.07:31:07.45#ibcon#about to read 4, iclass 5, count 0 2006.238.07:31:07.45#ibcon#read 4, iclass 5, count 0 2006.238.07:31:07.45#ibcon#about to read 5, iclass 5, count 0 2006.238.07:31:07.45#ibcon#read 5, iclass 5, count 0 2006.238.07:31:07.45#ibcon#about to read 6, iclass 5, count 0 2006.238.07:31:07.45#ibcon#read 6, iclass 5, count 0 2006.238.07:31:07.45#ibcon#end of sib2, iclass 5, count 0 2006.238.07:31:07.45#ibcon#*after write, iclass 5, count 0 2006.238.07:31:07.45#ibcon#*before return 0, iclass 5, count 0 2006.238.07:31:07.45#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:31:07.45#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:31:07.45#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:31:07.45#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:31:07.45$vc4f8/va=2,7 2006.238.07:31:07.45#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.07:31:07.45#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.07:31:07.45#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:07.45#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:31:07.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:31:07.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:31:07.52#ibcon#enter wrdev, iclass 7, count 2 2006.238.07:31:07.52#ibcon#first serial, iclass 7, count 2 2006.238.07:31:07.52#ibcon#enter sib2, iclass 7, count 2 2006.238.07:31:07.52#ibcon#flushed, iclass 7, count 2 2006.238.07:31:07.52#ibcon#about to write, iclass 7, count 2 2006.238.07:31:07.52#ibcon#wrote, iclass 7, count 2 2006.238.07:31:07.52#ibcon#about to read 3, iclass 7, count 2 2006.238.07:31:07.53#ibcon#read 3, iclass 7, count 2 2006.238.07:31:07.53#ibcon#about to read 4, iclass 7, count 2 2006.238.07:31:07.53#ibcon#read 4, iclass 7, count 2 2006.238.07:31:07.53#ibcon#about to read 5, iclass 7, count 2 2006.238.07:31:07.53#ibcon#read 5, iclass 7, count 2 2006.238.07:31:07.53#ibcon#about to read 6, iclass 7, count 2 2006.238.07:31:07.53#ibcon#read 6, iclass 7, count 2 2006.238.07:31:07.53#ibcon#end of sib2, iclass 7, count 2 2006.238.07:31:07.53#ibcon#*mode == 0, iclass 7, count 2 2006.238.07:31:07.53#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.07:31:07.53#ibcon#[25=AT02-07\r\n] 2006.238.07:31:07.53#ibcon#*before write, iclass 7, count 2 2006.238.07:31:07.53#ibcon#enter sib2, iclass 7, count 2 2006.238.07:31:07.53#ibcon#flushed, iclass 7, count 2 2006.238.07:31:07.53#ibcon#about to write, iclass 7, count 2 2006.238.07:31:07.53#ibcon#wrote, iclass 7, count 2 2006.238.07:31:07.53#ibcon#about to read 3, iclass 7, count 2 2006.238.07:31:07.56#ibcon#read 3, iclass 7, count 2 2006.238.07:31:07.56#ibcon#about to read 4, iclass 7, count 2 2006.238.07:31:07.56#ibcon#read 4, iclass 7, count 2 2006.238.07:31:07.56#ibcon#about to read 5, iclass 7, count 2 2006.238.07:31:07.56#ibcon#read 5, iclass 7, count 2 2006.238.07:31:07.56#ibcon#about to read 6, iclass 7, count 2 2006.238.07:31:07.56#ibcon#read 6, iclass 7, count 2 2006.238.07:31:07.56#ibcon#end of sib2, iclass 7, count 2 2006.238.07:31:07.56#ibcon#*after write, iclass 7, count 2 2006.238.07:31:07.56#ibcon#*before return 0, iclass 7, count 2 2006.238.07:31:07.56#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:31:07.56#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:31:07.56#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.07:31:07.56#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:07.56#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:31:07.68#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:31:07.68#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:31:07.68#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:31:07.68#ibcon#first serial, iclass 7, count 0 2006.238.07:31:07.68#ibcon#enter sib2, iclass 7, count 0 2006.238.07:31:07.68#ibcon#flushed, iclass 7, count 0 2006.238.07:31:07.68#ibcon#about to write, iclass 7, count 0 2006.238.07:31:07.68#ibcon#wrote, iclass 7, count 0 2006.238.07:31:07.68#ibcon#about to read 3, iclass 7, count 0 2006.238.07:31:07.70#ibcon#read 3, iclass 7, count 0 2006.238.07:31:07.70#ibcon#about to read 4, iclass 7, count 0 2006.238.07:31:07.70#ibcon#read 4, iclass 7, count 0 2006.238.07:31:07.70#ibcon#about to read 5, iclass 7, count 0 2006.238.07:31:07.70#ibcon#read 5, iclass 7, count 0 2006.238.07:31:07.70#ibcon#about to read 6, iclass 7, count 0 2006.238.07:31:07.70#ibcon#read 6, iclass 7, count 0 2006.238.07:31:07.70#ibcon#end of sib2, iclass 7, count 0 2006.238.07:31:07.70#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:31:07.70#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:31:07.70#ibcon#[25=USB\r\n] 2006.238.07:31:07.70#ibcon#*before write, iclass 7, count 0 2006.238.07:31:07.70#ibcon#enter sib2, iclass 7, count 0 2006.238.07:31:07.70#ibcon#flushed, iclass 7, count 0 2006.238.07:31:07.70#ibcon#about to write, iclass 7, count 0 2006.238.07:31:07.70#ibcon#wrote, iclass 7, count 0 2006.238.07:31:07.70#ibcon#about to read 3, iclass 7, count 0 2006.238.07:31:07.73#ibcon#read 3, iclass 7, count 0 2006.238.07:31:07.73#ibcon#about to read 4, iclass 7, count 0 2006.238.07:31:07.73#ibcon#read 4, iclass 7, count 0 2006.238.07:31:07.73#ibcon#about to read 5, iclass 7, count 0 2006.238.07:31:07.73#ibcon#read 5, iclass 7, count 0 2006.238.07:31:07.73#ibcon#about to read 6, iclass 7, count 0 2006.238.07:31:07.73#ibcon#read 6, iclass 7, count 0 2006.238.07:31:07.73#ibcon#end of sib2, iclass 7, count 0 2006.238.07:31:07.73#ibcon#*after write, iclass 7, count 0 2006.238.07:31:07.73#ibcon#*before return 0, iclass 7, count 0 2006.238.07:31:07.73#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:31:07.73#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:31:07.73#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:31:07.73#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:31:07.73$vc4f8/valo=3,672.99 2006.238.07:31:07.73#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.07:31:07.73#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.07:31:07.73#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:07.73#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:31:07.73#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:31:07.73#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:31:07.73#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:31:07.73#ibcon#first serial, iclass 11, count 0 2006.238.07:31:07.73#ibcon#enter sib2, iclass 11, count 0 2006.238.07:31:07.73#ibcon#flushed, iclass 11, count 0 2006.238.07:31:07.73#ibcon#about to write, iclass 11, count 0 2006.238.07:31:07.73#ibcon#wrote, iclass 11, count 0 2006.238.07:31:07.73#ibcon#about to read 3, iclass 11, count 0 2006.238.07:31:07.75#ibcon#read 3, iclass 11, count 0 2006.238.07:31:07.75#ibcon#about to read 4, iclass 11, count 0 2006.238.07:31:07.75#ibcon#read 4, iclass 11, count 0 2006.238.07:31:07.75#ibcon#about to read 5, iclass 11, count 0 2006.238.07:31:07.75#ibcon#read 5, iclass 11, count 0 2006.238.07:31:07.75#ibcon#about to read 6, iclass 11, count 0 2006.238.07:31:07.75#ibcon#read 6, iclass 11, count 0 2006.238.07:31:07.75#ibcon#end of sib2, iclass 11, count 0 2006.238.07:31:07.75#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:31:07.75#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:31:07.75#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:31:07.75#ibcon#*before write, iclass 11, count 0 2006.238.07:31:07.75#ibcon#enter sib2, iclass 11, count 0 2006.238.07:31:07.75#ibcon#flushed, iclass 11, count 0 2006.238.07:31:07.75#ibcon#about to write, iclass 11, count 0 2006.238.07:31:07.75#ibcon#wrote, iclass 11, count 0 2006.238.07:31:07.75#ibcon#about to read 3, iclass 11, count 0 2006.238.07:31:07.79#ibcon#read 3, iclass 11, count 0 2006.238.07:31:07.79#ibcon#about to read 4, iclass 11, count 0 2006.238.07:31:07.79#ibcon#read 4, iclass 11, count 0 2006.238.07:31:07.79#ibcon#about to read 5, iclass 11, count 0 2006.238.07:31:07.79#ibcon#read 5, iclass 11, count 0 2006.238.07:31:07.79#ibcon#about to read 6, iclass 11, count 0 2006.238.07:31:07.79#ibcon#read 6, iclass 11, count 0 2006.238.07:31:07.79#ibcon#end of sib2, iclass 11, count 0 2006.238.07:31:07.79#ibcon#*after write, iclass 11, count 0 2006.238.07:31:07.79#ibcon#*before return 0, iclass 11, count 0 2006.238.07:31:07.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:31:07.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:31:07.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:31:07.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:31:07.79$vc4f8/va=3,7 2006.238.07:31:07.79#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.07:31:07.79#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.07:31:07.79#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:07.79#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:31:07.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:31:07.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:31:07.86#ibcon#enter wrdev, iclass 13, count 2 2006.238.07:31:07.86#ibcon#first serial, iclass 13, count 2 2006.238.07:31:07.86#ibcon#enter sib2, iclass 13, count 2 2006.238.07:31:07.86#ibcon#flushed, iclass 13, count 2 2006.238.07:31:07.86#ibcon#about to write, iclass 13, count 2 2006.238.07:31:07.86#ibcon#wrote, iclass 13, count 2 2006.238.07:31:07.86#ibcon#about to read 3, iclass 13, count 2 2006.238.07:31:07.87#ibcon#read 3, iclass 13, count 2 2006.238.07:31:07.87#ibcon#about to read 4, iclass 13, count 2 2006.238.07:31:07.87#ibcon#read 4, iclass 13, count 2 2006.238.07:31:07.87#ibcon#about to read 5, iclass 13, count 2 2006.238.07:31:07.87#ibcon#read 5, iclass 13, count 2 2006.238.07:31:07.87#ibcon#about to read 6, iclass 13, count 2 2006.238.07:31:07.87#ibcon#read 6, iclass 13, count 2 2006.238.07:31:07.87#ibcon#end of sib2, iclass 13, count 2 2006.238.07:31:07.87#ibcon#*mode == 0, iclass 13, count 2 2006.238.07:31:07.87#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.07:31:07.87#ibcon#[25=AT03-07\r\n] 2006.238.07:31:07.87#ibcon#*before write, iclass 13, count 2 2006.238.07:31:07.87#ibcon#enter sib2, iclass 13, count 2 2006.238.07:31:07.87#ibcon#flushed, iclass 13, count 2 2006.238.07:31:07.87#ibcon#about to write, iclass 13, count 2 2006.238.07:31:07.87#ibcon#wrote, iclass 13, count 2 2006.238.07:31:07.87#ibcon#about to read 3, iclass 13, count 2 2006.238.07:31:07.90#ibcon#read 3, iclass 13, count 2 2006.238.07:31:07.90#ibcon#about to read 4, iclass 13, count 2 2006.238.07:31:07.90#ibcon#read 4, iclass 13, count 2 2006.238.07:31:07.90#ibcon#about to read 5, iclass 13, count 2 2006.238.07:31:07.90#ibcon#read 5, iclass 13, count 2 2006.238.07:31:07.90#ibcon#about to read 6, iclass 13, count 2 2006.238.07:31:07.90#ibcon#read 6, iclass 13, count 2 2006.238.07:31:07.90#ibcon#end of sib2, iclass 13, count 2 2006.238.07:31:07.90#ibcon#*after write, iclass 13, count 2 2006.238.07:31:07.90#ibcon#*before return 0, iclass 13, count 2 2006.238.07:31:07.90#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:31:07.90#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:31:07.90#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.07:31:07.90#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:07.90#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:31:08.02#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:31:08.02#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:31:08.02#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:31:08.02#ibcon#first serial, iclass 13, count 0 2006.238.07:31:08.02#ibcon#enter sib2, iclass 13, count 0 2006.238.07:31:08.02#ibcon#flushed, iclass 13, count 0 2006.238.07:31:08.02#ibcon#about to write, iclass 13, count 0 2006.238.07:31:08.02#ibcon#wrote, iclass 13, count 0 2006.238.07:31:08.02#ibcon#about to read 3, iclass 13, count 0 2006.238.07:31:08.04#ibcon#read 3, iclass 13, count 0 2006.238.07:31:08.04#ibcon#about to read 4, iclass 13, count 0 2006.238.07:31:08.04#ibcon#read 4, iclass 13, count 0 2006.238.07:31:08.04#ibcon#about to read 5, iclass 13, count 0 2006.238.07:31:08.04#ibcon#read 5, iclass 13, count 0 2006.238.07:31:08.04#ibcon#about to read 6, iclass 13, count 0 2006.238.07:31:08.04#ibcon#read 6, iclass 13, count 0 2006.238.07:31:08.04#ibcon#end of sib2, iclass 13, count 0 2006.238.07:31:08.04#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:31:08.04#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:31:08.04#ibcon#[25=USB\r\n] 2006.238.07:31:08.04#ibcon#*before write, iclass 13, count 0 2006.238.07:31:08.04#ibcon#enter sib2, iclass 13, count 0 2006.238.07:31:08.04#ibcon#flushed, iclass 13, count 0 2006.238.07:31:08.04#ibcon#about to write, iclass 13, count 0 2006.238.07:31:08.04#ibcon#wrote, iclass 13, count 0 2006.238.07:31:08.04#ibcon#about to read 3, iclass 13, count 0 2006.238.07:31:08.07#ibcon#read 3, iclass 13, count 0 2006.238.07:31:08.07#ibcon#about to read 4, iclass 13, count 0 2006.238.07:31:08.07#ibcon#read 4, iclass 13, count 0 2006.238.07:31:08.07#ibcon#about to read 5, iclass 13, count 0 2006.238.07:31:08.07#ibcon#read 5, iclass 13, count 0 2006.238.07:31:08.07#ibcon#about to read 6, iclass 13, count 0 2006.238.07:31:08.07#ibcon#read 6, iclass 13, count 0 2006.238.07:31:08.07#ibcon#end of sib2, iclass 13, count 0 2006.238.07:31:08.07#ibcon#*after write, iclass 13, count 0 2006.238.07:31:08.07#ibcon#*before return 0, iclass 13, count 0 2006.238.07:31:08.07#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:31:08.07#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:31:08.07#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:31:08.07#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:31:08.07$vc4f8/valo=4,832.99 2006.238.07:31:08.07#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.07:31:08.07#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.07:31:08.07#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:08.07#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:31:08.07#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:31:08.07#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:31:08.07#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:31:08.07#ibcon#first serial, iclass 15, count 0 2006.238.07:31:08.07#ibcon#enter sib2, iclass 15, count 0 2006.238.07:31:08.07#ibcon#flushed, iclass 15, count 0 2006.238.07:31:08.07#ibcon#about to write, iclass 15, count 0 2006.238.07:31:08.07#ibcon#wrote, iclass 15, count 0 2006.238.07:31:08.07#ibcon#about to read 3, iclass 15, count 0 2006.238.07:31:08.09#ibcon#read 3, iclass 15, count 0 2006.238.07:31:08.09#ibcon#about to read 4, iclass 15, count 0 2006.238.07:31:08.09#ibcon#read 4, iclass 15, count 0 2006.238.07:31:08.09#ibcon#about to read 5, iclass 15, count 0 2006.238.07:31:08.09#ibcon#read 5, iclass 15, count 0 2006.238.07:31:08.09#ibcon#about to read 6, iclass 15, count 0 2006.238.07:31:08.09#ibcon#read 6, iclass 15, count 0 2006.238.07:31:08.09#ibcon#end of sib2, iclass 15, count 0 2006.238.07:31:08.09#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:31:08.09#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:31:08.09#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:31:08.09#ibcon#*before write, iclass 15, count 0 2006.238.07:31:08.09#ibcon#enter sib2, iclass 15, count 0 2006.238.07:31:08.09#ibcon#flushed, iclass 15, count 0 2006.238.07:31:08.09#ibcon#about to write, iclass 15, count 0 2006.238.07:31:08.09#ibcon#wrote, iclass 15, count 0 2006.238.07:31:08.09#ibcon#about to read 3, iclass 15, count 0 2006.238.07:31:08.13#ibcon#read 3, iclass 15, count 0 2006.238.07:31:08.13#ibcon#about to read 4, iclass 15, count 0 2006.238.07:31:08.13#ibcon#read 4, iclass 15, count 0 2006.238.07:31:08.13#ibcon#about to read 5, iclass 15, count 0 2006.238.07:31:08.13#ibcon#read 5, iclass 15, count 0 2006.238.07:31:08.13#ibcon#about to read 6, iclass 15, count 0 2006.238.07:31:08.13#ibcon#read 6, iclass 15, count 0 2006.238.07:31:08.13#ibcon#end of sib2, iclass 15, count 0 2006.238.07:31:08.13#ibcon#*after write, iclass 15, count 0 2006.238.07:31:08.13#ibcon#*before return 0, iclass 15, count 0 2006.238.07:31:08.13#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:31:08.13#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:31:08.13#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:31:08.13#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:31:08.13$vc4f8/va=4,7 2006.238.07:31:08.13#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.07:31:08.13#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.07:31:08.13#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:08.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:31:08.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:31:08.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:31:08.19#ibcon#enter wrdev, iclass 17, count 2 2006.238.07:31:08.19#ibcon#first serial, iclass 17, count 2 2006.238.07:31:08.19#ibcon#enter sib2, iclass 17, count 2 2006.238.07:31:08.19#ibcon#flushed, iclass 17, count 2 2006.238.07:31:08.19#ibcon#about to write, iclass 17, count 2 2006.238.07:31:08.19#ibcon#wrote, iclass 17, count 2 2006.238.07:31:08.19#ibcon#about to read 3, iclass 17, count 2 2006.238.07:31:08.21#ibcon#read 3, iclass 17, count 2 2006.238.07:31:08.21#ibcon#about to read 4, iclass 17, count 2 2006.238.07:31:08.21#ibcon#read 4, iclass 17, count 2 2006.238.07:31:08.21#ibcon#about to read 5, iclass 17, count 2 2006.238.07:31:08.21#ibcon#read 5, iclass 17, count 2 2006.238.07:31:08.21#ibcon#about to read 6, iclass 17, count 2 2006.238.07:31:08.21#ibcon#read 6, iclass 17, count 2 2006.238.07:31:08.21#ibcon#end of sib2, iclass 17, count 2 2006.238.07:31:08.21#ibcon#*mode == 0, iclass 17, count 2 2006.238.07:31:08.21#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.07:31:08.21#ibcon#[25=AT04-07\r\n] 2006.238.07:31:08.21#ibcon#*before write, iclass 17, count 2 2006.238.07:31:08.21#ibcon#enter sib2, iclass 17, count 2 2006.238.07:31:08.21#ibcon#flushed, iclass 17, count 2 2006.238.07:31:08.21#ibcon#about to write, iclass 17, count 2 2006.238.07:31:08.21#ibcon#wrote, iclass 17, count 2 2006.238.07:31:08.21#ibcon#about to read 3, iclass 17, count 2 2006.238.07:31:08.24#ibcon#read 3, iclass 17, count 2 2006.238.07:31:08.24#ibcon#about to read 4, iclass 17, count 2 2006.238.07:31:08.24#ibcon#read 4, iclass 17, count 2 2006.238.07:31:08.24#ibcon#about to read 5, iclass 17, count 2 2006.238.07:31:08.24#ibcon#read 5, iclass 17, count 2 2006.238.07:31:08.24#ibcon#about to read 6, iclass 17, count 2 2006.238.07:31:08.24#ibcon#read 6, iclass 17, count 2 2006.238.07:31:08.24#ibcon#end of sib2, iclass 17, count 2 2006.238.07:31:08.24#ibcon#*after write, iclass 17, count 2 2006.238.07:31:08.24#ibcon#*before return 0, iclass 17, count 2 2006.238.07:31:08.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:31:08.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:31:08.24#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.07:31:08.24#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:08.24#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:31:08.36#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:31:08.36#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:31:08.36#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:31:08.36#ibcon#first serial, iclass 17, count 0 2006.238.07:31:08.36#ibcon#enter sib2, iclass 17, count 0 2006.238.07:31:08.36#ibcon#flushed, iclass 17, count 0 2006.238.07:31:08.36#ibcon#about to write, iclass 17, count 0 2006.238.07:31:08.36#ibcon#wrote, iclass 17, count 0 2006.238.07:31:08.36#ibcon#about to read 3, iclass 17, count 0 2006.238.07:31:08.38#ibcon#read 3, iclass 17, count 0 2006.238.07:31:08.38#ibcon#about to read 4, iclass 17, count 0 2006.238.07:31:08.38#ibcon#read 4, iclass 17, count 0 2006.238.07:31:08.38#ibcon#about to read 5, iclass 17, count 0 2006.238.07:31:08.38#ibcon#read 5, iclass 17, count 0 2006.238.07:31:08.38#ibcon#about to read 6, iclass 17, count 0 2006.238.07:31:08.38#ibcon#read 6, iclass 17, count 0 2006.238.07:31:08.38#ibcon#end of sib2, iclass 17, count 0 2006.238.07:31:08.38#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:31:08.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:31:08.38#ibcon#[25=USB\r\n] 2006.238.07:31:08.38#ibcon#*before write, iclass 17, count 0 2006.238.07:31:08.38#ibcon#enter sib2, iclass 17, count 0 2006.238.07:31:08.38#ibcon#flushed, iclass 17, count 0 2006.238.07:31:08.38#ibcon#about to write, iclass 17, count 0 2006.238.07:31:08.38#ibcon#wrote, iclass 17, count 0 2006.238.07:31:08.38#ibcon#about to read 3, iclass 17, count 0 2006.238.07:31:08.41#ibcon#read 3, iclass 17, count 0 2006.238.07:31:08.41#ibcon#about to read 4, iclass 17, count 0 2006.238.07:31:08.41#ibcon#read 4, iclass 17, count 0 2006.238.07:31:08.41#ibcon#about to read 5, iclass 17, count 0 2006.238.07:31:08.41#ibcon#read 5, iclass 17, count 0 2006.238.07:31:08.41#ibcon#about to read 6, iclass 17, count 0 2006.238.07:31:08.41#ibcon#read 6, iclass 17, count 0 2006.238.07:31:08.41#ibcon#end of sib2, iclass 17, count 0 2006.238.07:31:08.41#ibcon#*after write, iclass 17, count 0 2006.238.07:31:08.41#ibcon#*before return 0, iclass 17, count 0 2006.238.07:31:08.41#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:31:08.41#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:31:08.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:31:08.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:31:08.41$vc4f8/valo=5,652.99 2006.238.07:31:08.41#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.07:31:08.41#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.07:31:08.41#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:08.41#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:31:08.41#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:31:08.41#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:31:08.41#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:31:08.41#ibcon#first serial, iclass 19, count 0 2006.238.07:31:08.41#ibcon#enter sib2, iclass 19, count 0 2006.238.07:31:08.41#ibcon#flushed, iclass 19, count 0 2006.238.07:31:08.41#ibcon#about to write, iclass 19, count 0 2006.238.07:31:08.41#ibcon#wrote, iclass 19, count 0 2006.238.07:31:08.41#ibcon#about to read 3, iclass 19, count 0 2006.238.07:31:08.43#ibcon#read 3, iclass 19, count 0 2006.238.07:31:08.43#ibcon#about to read 4, iclass 19, count 0 2006.238.07:31:08.43#ibcon#read 4, iclass 19, count 0 2006.238.07:31:08.43#ibcon#about to read 5, iclass 19, count 0 2006.238.07:31:08.43#ibcon#read 5, iclass 19, count 0 2006.238.07:31:08.43#ibcon#about to read 6, iclass 19, count 0 2006.238.07:31:08.43#ibcon#read 6, iclass 19, count 0 2006.238.07:31:08.43#ibcon#end of sib2, iclass 19, count 0 2006.238.07:31:08.43#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:31:08.43#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:31:08.43#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:31:08.43#ibcon#*before write, iclass 19, count 0 2006.238.07:31:08.43#ibcon#enter sib2, iclass 19, count 0 2006.238.07:31:08.43#ibcon#flushed, iclass 19, count 0 2006.238.07:31:08.43#ibcon#about to write, iclass 19, count 0 2006.238.07:31:08.43#ibcon#wrote, iclass 19, count 0 2006.238.07:31:08.43#ibcon#about to read 3, iclass 19, count 0 2006.238.07:31:08.47#ibcon#read 3, iclass 19, count 0 2006.238.07:31:08.47#ibcon#about to read 4, iclass 19, count 0 2006.238.07:31:08.47#ibcon#read 4, iclass 19, count 0 2006.238.07:31:08.47#ibcon#about to read 5, iclass 19, count 0 2006.238.07:31:08.47#ibcon#read 5, iclass 19, count 0 2006.238.07:31:08.47#ibcon#about to read 6, iclass 19, count 0 2006.238.07:31:08.47#ibcon#read 6, iclass 19, count 0 2006.238.07:31:08.47#ibcon#end of sib2, iclass 19, count 0 2006.238.07:31:08.47#ibcon#*after write, iclass 19, count 0 2006.238.07:31:08.47#ibcon#*before return 0, iclass 19, count 0 2006.238.07:31:08.47#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:31:08.47#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:31:08.47#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:31:08.47#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:31:08.47$vc4f8/va=5,8 2006.238.07:31:08.47#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.07:31:08.47#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.07:31:08.47#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:08.47#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:31:08.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:31:08.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:31:08.54#ibcon#enter wrdev, iclass 21, count 2 2006.238.07:31:08.54#ibcon#first serial, iclass 21, count 2 2006.238.07:31:08.54#ibcon#enter sib2, iclass 21, count 2 2006.238.07:31:08.54#ibcon#flushed, iclass 21, count 2 2006.238.07:31:08.54#ibcon#about to write, iclass 21, count 2 2006.238.07:31:08.54#ibcon#wrote, iclass 21, count 2 2006.238.07:31:08.54#ibcon#about to read 3, iclass 21, count 2 2006.238.07:31:08.55#ibcon#read 3, iclass 21, count 2 2006.238.07:31:08.55#ibcon#about to read 4, iclass 21, count 2 2006.238.07:31:08.55#ibcon#read 4, iclass 21, count 2 2006.238.07:31:08.55#ibcon#about to read 5, iclass 21, count 2 2006.238.07:31:08.55#ibcon#read 5, iclass 21, count 2 2006.238.07:31:08.55#ibcon#about to read 6, iclass 21, count 2 2006.238.07:31:08.55#ibcon#read 6, iclass 21, count 2 2006.238.07:31:08.55#ibcon#end of sib2, iclass 21, count 2 2006.238.07:31:08.55#ibcon#*mode == 0, iclass 21, count 2 2006.238.07:31:08.55#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.07:31:08.55#ibcon#[25=AT05-08\r\n] 2006.238.07:31:08.55#ibcon#*before write, iclass 21, count 2 2006.238.07:31:08.55#ibcon#enter sib2, iclass 21, count 2 2006.238.07:31:08.55#ibcon#flushed, iclass 21, count 2 2006.238.07:31:08.55#ibcon#about to write, iclass 21, count 2 2006.238.07:31:08.55#ibcon#wrote, iclass 21, count 2 2006.238.07:31:08.55#ibcon#about to read 3, iclass 21, count 2 2006.238.07:31:08.58#ibcon#read 3, iclass 21, count 2 2006.238.07:31:08.58#ibcon#about to read 4, iclass 21, count 2 2006.238.07:31:08.58#ibcon#read 4, iclass 21, count 2 2006.238.07:31:08.58#ibcon#about to read 5, iclass 21, count 2 2006.238.07:31:08.58#ibcon#read 5, iclass 21, count 2 2006.238.07:31:08.58#ibcon#about to read 6, iclass 21, count 2 2006.238.07:31:08.58#ibcon#read 6, iclass 21, count 2 2006.238.07:31:08.58#ibcon#end of sib2, iclass 21, count 2 2006.238.07:31:08.58#ibcon#*after write, iclass 21, count 2 2006.238.07:31:08.58#ibcon#*before return 0, iclass 21, count 2 2006.238.07:31:08.58#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:31:08.58#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:31:08.58#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.07:31:08.58#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:08.58#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:31:08.70#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:31:08.70#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:31:08.70#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:31:08.70#ibcon#first serial, iclass 21, count 0 2006.238.07:31:08.70#ibcon#enter sib2, iclass 21, count 0 2006.238.07:31:08.70#ibcon#flushed, iclass 21, count 0 2006.238.07:31:08.70#ibcon#about to write, iclass 21, count 0 2006.238.07:31:08.70#ibcon#wrote, iclass 21, count 0 2006.238.07:31:08.70#ibcon#about to read 3, iclass 21, count 0 2006.238.07:31:08.72#ibcon#read 3, iclass 21, count 0 2006.238.07:31:08.72#ibcon#about to read 4, iclass 21, count 0 2006.238.07:31:08.72#ibcon#read 4, iclass 21, count 0 2006.238.07:31:08.72#ibcon#about to read 5, iclass 21, count 0 2006.238.07:31:08.72#ibcon#read 5, iclass 21, count 0 2006.238.07:31:08.72#ibcon#about to read 6, iclass 21, count 0 2006.238.07:31:08.72#ibcon#read 6, iclass 21, count 0 2006.238.07:31:08.72#ibcon#end of sib2, iclass 21, count 0 2006.238.07:31:08.72#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:31:08.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:31:08.72#ibcon#[25=USB\r\n] 2006.238.07:31:08.72#ibcon#*before write, iclass 21, count 0 2006.238.07:31:08.72#ibcon#enter sib2, iclass 21, count 0 2006.238.07:31:08.72#ibcon#flushed, iclass 21, count 0 2006.238.07:31:08.72#ibcon#about to write, iclass 21, count 0 2006.238.07:31:08.72#ibcon#wrote, iclass 21, count 0 2006.238.07:31:08.72#ibcon#about to read 3, iclass 21, count 0 2006.238.07:31:08.75#ibcon#read 3, iclass 21, count 0 2006.238.07:31:08.75#ibcon#about to read 4, iclass 21, count 0 2006.238.07:31:08.75#ibcon#read 4, iclass 21, count 0 2006.238.07:31:08.75#ibcon#about to read 5, iclass 21, count 0 2006.238.07:31:08.75#ibcon#read 5, iclass 21, count 0 2006.238.07:31:08.75#ibcon#about to read 6, iclass 21, count 0 2006.238.07:31:08.75#ibcon#read 6, iclass 21, count 0 2006.238.07:31:08.75#ibcon#end of sib2, iclass 21, count 0 2006.238.07:31:08.75#ibcon#*after write, iclass 21, count 0 2006.238.07:31:08.75#ibcon#*before return 0, iclass 21, count 0 2006.238.07:31:08.75#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:31:08.75#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:31:08.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:31:08.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:31:08.75$vc4f8/valo=6,772.99 2006.238.07:31:08.75#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:31:08.75#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:31:08.75#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:08.75#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:31:08.75#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:31:08.75#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:31:08.75#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:31:08.75#ibcon#first serial, iclass 23, count 0 2006.238.07:31:08.75#ibcon#enter sib2, iclass 23, count 0 2006.238.07:31:08.75#ibcon#flushed, iclass 23, count 0 2006.238.07:31:08.75#ibcon#about to write, iclass 23, count 0 2006.238.07:31:08.75#ibcon#wrote, iclass 23, count 0 2006.238.07:31:08.75#ibcon#about to read 3, iclass 23, count 0 2006.238.07:31:08.77#ibcon#read 3, iclass 23, count 0 2006.238.07:31:08.77#ibcon#about to read 4, iclass 23, count 0 2006.238.07:31:08.77#ibcon#read 4, iclass 23, count 0 2006.238.07:31:08.77#ibcon#about to read 5, iclass 23, count 0 2006.238.07:31:08.77#ibcon#read 5, iclass 23, count 0 2006.238.07:31:08.77#ibcon#about to read 6, iclass 23, count 0 2006.238.07:31:08.77#ibcon#read 6, iclass 23, count 0 2006.238.07:31:08.77#ibcon#end of sib2, iclass 23, count 0 2006.238.07:31:08.77#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:31:08.77#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:31:08.77#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:31:08.77#ibcon#*before write, iclass 23, count 0 2006.238.07:31:08.77#ibcon#enter sib2, iclass 23, count 0 2006.238.07:31:08.77#ibcon#flushed, iclass 23, count 0 2006.238.07:31:08.77#ibcon#about to write, iclass 23, count 0 2006.238.07:31:08.77#ibcon#wrote, iclass 23, count 0 2006.238.07:31:08.77#ibcon#about to read 3, iclass 23, count 0 2006.238.07:31:08.81#ibcon#read 3, iclass 23, count 0 2006.238.07:31:08.81#ibcon#about to read 4, iclass 23, count 0 2006.238.07:31:08.81#ibcon#read 4, iclass 23, count 0 2006.238.07:31:08.81#ibcon#about to read 5, iclass 23, count 0 2006.238.07:31:08.81#ibcon#read 5, iclass 23, count 0 2006.238.07:31:08.81#ibcon#about to read 6, iclass 23, count 0 2006.238.07:31:08.81#ibcon#read 6, iclass 23, count 0 2006.238.07:31:08.81#ibcon#end of sib2, iclass 23, count 0 2006.238.07:31:08.81#ibcon#*after write, iclass 23, count 0 2006.238.07:31:08.81#ibcon#*before return 0, iclass 23, count 0 2006.238.07:31:08.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:31:08.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:31:08.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:31:08.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:31:08.81$vc4f8/va=6,7 2006.238.07:31:08.81#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.07:31:08.81#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.07:31:08.81#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:08.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:31:08.87#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:31:08.87#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:31:08.87#ibcon#enter wrdev, iclass 25, count 2 2006.238.07:31:08.87#ibcon#first serial, iclass 25, count 2 2006.238.07:31:08.87#ibcon#enter sib2, iclass 25, count 2 2006.238.07:31:08.87#ibcon#flushed, iclass 25, count 2 2006.238.07:31:08.87#ibcon#about to write, iclass 25, count 2 2006.238.07:31:08.87#ibcon#wrote, iclass 25, count 2 2006.238.07:31:08.87#ibcon#about to read 3, iclass 25, count 2 2006.238.07:31:08.89#ibcon#read 3, iclass 25, count 2 2006.238.07:31:08.89#ibcon#about to read 4, iclass 25, count 2 2006.238.07:31:08.89#ibcon#read 4, iclass 25, count 2 2006.238.07:31:08.89#ibcon#about to read 5, iclass 25, count 2 2006.238.07:31:08.89#ibcon#read 5, iclass 25, count 2 2006.238.07:31:08.89#ibcon#about to read 6, iclass 25, count 2 2006.238.07:31:08.89#ibcon#read 6, iclass 25, count 2 2006.238.07:31:08.89#ibcon#end of sib2, iclass 25, count 2 2006.238.07:31:08.89#ibcon#*mode == 0, iclass 25, count 2 2006.238.07:31:08.89#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.07:31:08.89#ibcon#[25=AT06-07\r\n] 2006.238.07:31:08.89#ibcon#*before write, iclass 25, count 2 2006.238.07:31:08.89#ibcon#enter sib2, iclass 25, count 2 2006.238.07:31:08.89#ibcon#flushed, iclass 25, count 2 2006.238.07:31:08.89#ibcon#about to write, iclass 25, count 2 2006.238.07:31:08.89#ibcon#wrote, iclass 25, count 2 2006.238.07:31:08.89#ibcon#about to read 3, iclass 25, count 2 2006.238.07:31:08.92#ibcon#read 3, iclass 25, count 2 2006.238.07:31:08.92#ibcon#about to read 4, iclass 25, count 2 2006.238.07:31:08.92#ibcon#read 4, iclass 25, count 2 2006.238.07:31:08.92#ibcon#about to read 5, iclass 25, count 2 2006.238.07:31:08.92#ibcon#read 5, iclass 25, count 2 2006.238.07:31:08.92#ibcon#about to read 6, iclass 25, count 2 2006.238.07:31:08.92#ibcon#read 6, iclass 25, count 2 2006.238.07:31:08.92#ibcon#end of sib2, iclass 25, count 2 2006.238.07:31:08.92#ibcon#*after write, iclass 25, count 2 2006.238.07:31:08.92#ibcon#*before return 0, iclass 25, count 2 2006.238.07:31:08.92#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:31:08.92#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:31:08.92#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.07:31:08.92#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:08.92#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:31:09.04#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:31:09.04#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:31:09.04#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:31:09.04#ibcon#first serial, iclass 25, count 0 2006.238.07:31:09.04#ibcon#enter sib2, iclass 25, count 0 2006.238.07:31:09.04#ibcon#flushed, iclass 25, count 0 2006.238.07:31:09.04#ibcon#about to write, iclass 25, count 0 2006.238.07:31:09.04#ibcon#wrote, iclass 25, count 0 2006.238.07:31:09.04#ibcon#about to read 3, iclass 25, count 0 2006.238.07:31:09.08#ibcon#read 3, iclass 25, count 0 2006.238.07:31:09.08#ibcon#about to read 4, iclass 25, count 0 2006.238.07:31:09.08#ibcon#read 4, iclass 25, count 0 2006.238.07:31:09.08#ibcon#about to read 5, iclass 25, count 0 2006.238.07:31:09.08#ibcon#read 5, iclass 25, count 0 2006.238.07:31:09.08#ibcon#about to read 6, iclass 25, count 0 2006.238.07:31:09.08#ibcon#read 6, iclass 25, count 0 2006.238.07:31:09.08#ibcon#end of sib2, iclass 25, count 0 2006.238.07:31:09.08#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:31:09.08#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:31:09.08#ibcon#[25=USB\r\n] 2006.238.07:31:09.08#ibcon#*before write, iclass 25, count 0 2006.238.07:31:09.08#ibcon#enter sib2, iclass 25, count 0 2006.238.07:31:09.08#ibcon#flushed, iclass 25, count 0 2006.238.07:31:09.08#ibcon#about to write, iclass 25, count 0 2006.238.07:31:09.08#ibcon#wrote, iclass 25, count 0 2006.238.07:31:09.08#ibcon#about to read 3, iclass 25, count 0 2006.238.07:31:09.11#ibcon#read 3, iclass 25, count 0 2006.238.07:31:09.11#ibcon#about to read 4, iclass 25, count 0 2006.238.07:31:09.11#ibcon#read 4, iclass 25, count 0 2006.238.07:31:09.11#ibcon#about to read 5, iclass 25, count 0 2006.238.07:31:09.11#ibcon#read 5, iclass 25, count 0 2006.238.07:31:09.11#ibcon#about to read 6, iclass 25, count 0 2006.238.07:31:09.11#ibcon#read 6, iclass 25, count 0 2006.238.07:31:09.11#ibcon#end of sib2, iclass 25, count 0 2006.238.07:31:09.11#ibcon#*after write, iclass 25, count 0 2006.238.07:31:09.11#ibcon#*before return 0, iclass 25, count 0 2006.238.07:31:09.11#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:31:09.11#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:31:09.11#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:31:09.11#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:31:09.11$vc4f8/valo=7,832.99 2006.238.07:31:09.11#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:31:09.11#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:31:09.11#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:09.11#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:31:09.11#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:31:09.11#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:31:09.11#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:31:09.11#ibcon#first serial, iclass 27, count 0 2006.238.07:31:09.11#ibcon#enter sib2, iclass 27, count 0 2006.238.07:31:09.11#ibcon#flushed, iclass 27, count 0 2006.238.07:31:09.11#ibcon#about to write, iclass 27, count 0 2006.238.07:31:09.11#ibcon#wrote, iclass 27, count 0 2006.238.07:31:09.11#ibcon#about to read 3, iclass 27, count 0 2006.238.07:31:09.13#ibcon#read 3, iclass 27, count 0 2006.238.07:31:09.13#ibcon#about to read 4, iclass 27, count 0 2006.238.07:31:09.13#ibcon#read 4, iclass 27, count 0 2006.238.07:31:09.13#ibcon#about to read 5, iclass 27, count 0 2006.238.07:31:09.13#ibcon#read 5, iclass 27, count 0 2006.238.07:31:09.13#ibcon#about to read 6, iclass 27, count 0 2006.238.07:31:09.13#ibcon#read 6, iclass 27, count 0 2006.238.07:31:09.13#ibcon#end of sib2, iclass 27, count 0 2006.238.07:31:09.13#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:31:09.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:31:09.13#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:31:09.13#ibcon#*before write, iclass 27, count 0 2006.238.07:31:09.13#ibcon#enter sib2, iclass 27, count 0 2006.238.07:31:09.13#ibcon#flushed, iclass 27, count 0 2006.238.07:31:09.13#ibcon#about to write, iclass 27, count 0 2006.238.07:31:09.13#ibcon#wrote, iclass 27, count 0 2006.238.07:31:09.13#ibcon#about to read 3, iclass 27, count 0 2006.238.07:31:09.18#ibcon#read 3, iclass 27, count 0 2006.238.07:31:09.18#ibcon#about to read 4, iclass 27, count 0 2006.238.07:31:09.18#ibcon#read 4, iclass 27, count 0 2006.238.07:31:09.18#ibcon#about to read 5, iclass 27, count 0 2006.238.07:31:09.18#ibcon#read 5, iclass 27, count 0 2006.238.07:31:09.18#ibcon#about to read 6, iclass 27, count 0 2006.238.07:31:09.18#ibcon#read 6, iclass 27, count 0 2006.238.07:31:09.18#ibcon#end of sib2, iclass 27, count 0 2006.238.07:31:09.18#ibcon#*after write, iclass 27, count 0 2006.238.07:31:09.18#ibcon#*before return 0, iclass 27, count 0 2006.238.07:31:09.18#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:31:09.18#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:31:09.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:31:09.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:31:09.18$vc4f8/va=7,7 2006.238.07:31:09.18#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.07:31:09.18#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.07:31:09.18#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:09.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:31:09.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:31:09.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:31:09.22#ibcon#enter wrdev, iclass 29, count 2 2006.238.07:31:09.22#ibcon#first serial, iclass 29, count 2 2006.238.07:31:09.22#ibcon#enter sib2, iclass 29, count 2 2006.238.07:31:09.22#ibcon#flushed, iclass 29, count 2 2006.238.07:31:09.22#ibcon#about to write, iclass 29, count 2 2006.238.07:31:09.22#ibcon#wrote, iclass 29, count 2 2006.238.07:31:09.22#ibcon#about to read 3, iclass 29, count 2 2006.238.07:31:09.24#ibcon#read 3, iclass 29, count 2 2006.238.07:31:09.24#ibcon#about to read 4, iclass 29, count 2 2006.238.07:31:09.24#ibcon#read 4, iclass 29, count 2 2006.238.07:31:09.24#ibcon#about to read 5, iclass 29, count 2 2006.238.07:31:09.24#ibcon#read 5, iclass 29, count 2 2006.238.07:31:09.24#ibcon#about to read 6, iclass 29, count 2 2006.238.07:31:09.24#ibcon#read 6, iclass 29, count 2 2006.238.07:31:09.24#ibcon#end of sib2, iclass 29, count 2 2006.238.07:31:09.24#ibcon#*mode == 0, iclass 29, count 2 2006.238.07:31:09.24#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.07:31:09.24#ibcon#[25=AT07-07\r\n] 2006.238.07:31:09.24#ibcon#*before write, iclass 29, count 2 2006.238.07:31:09.24#ibcon#enter sib2, iclass 29, count 2 2006.238.07:31:09.24#ibcon#flushed, iclass 29, count 2 2006.238.07:31:09.24#ibcon#about to write, iclass 29, count 2 2006.238.07:31:09.24#ibcon#wrote, iclass 29, count 2 2006.238.07:31:09.24#ibcon#about to read 3, iclass 29, count 2 2006.238.07:31:09.27#ibcon#read 3, iclass 29, count 2 2006.238.07:31:09.27#ibcon#about to read 4, iclass 29, count 2 2006.238.07:31:09.27#ibcon#read 4, iclass 29, count 2 2006.238.07:31:09.27#ibcon#about to read 5, iclass 29, count 2 2006.238.07:31:09.27#ibcon#read 5, iclass 29, count 2 2006.238.07:31:09.27#ibcon#about to read 6, iclass 29, count 2 2006.238.07:31:09.27#ibcon#read 6, iclass 29, count 2 2006.238.07:31:09.27#ibcon#end of sib2, iclass 29, count 2 2006.238.07:31:09.27#ibcon#*after write, iclass 29, count 2 2006.238.07:31:09.27#ibcon#*before return 0, iclass 29, count 2 2006.238.07:31:09.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:31:09.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:31:09.27#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.07:31:09.27#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:09.27#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:31:09.39#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:31:09.39#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:31:09.39#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:31:09.39#ibcon#first serial, iclass 29, count 0 2006.238.07:31:09.39#ibcon#enter sib2, iclass 29, count 0 2006.238.07:31:09.39#ibcon#flushed, iclass 29, count 0 2006.238.07:31:09.39#ibcon#about to write, iclass 29, count 0 2006.238.07:31:09.39#ibcon#wrote, iclass 29, count 0 2006.238.07:31:09.39#ibcon#about to read 3, iclass 29, count 0 2006.238.07:31:09.41#ibcon#read 3, iclass 29, count 0 2006.238.07:31:09.41#ibcon#about to read 4, iclass 29, count 0 2006.238.07:31:09.41#ibcon#read 4, iclass 29, count 0 2006.238.07:31:09.41#ibcon#about to read 5, iclass 29, count 0 2006.238.07:31:09.41#ibcon#read 5, iclass 29, count 0 2006.238.07:31:09.41#ibcon#about to read 6, iclass 29, count 0 2006.238.07:31:09.41#ibcon#read 6, iclass 29, count 0 2006.238.07:31:09.41#ibcon#end of sib2, iclass 29, count 0 2006.238.07:31:09.41#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:31:09.41#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:31:09.41#ibcon#[25=USB\r\n] 2006.238.07:31:09.41#ibcon#*before write, iclass 29, count 0 2006.238.07:31:09.41#ibcon#enter sib2, iclass 29, count 0 2006.238.07:31:09.41#ibcon#flushed, iclass 29, count 0 2006.238.07:31:09.41#ibcon#about to write, iclass 29, count 0 2006.238.07:31:09.41#ibcon#wrote, iclass 29, count 0 2006.238.07:31:09.41#ibcon#about to read 3, iclass 29, count 0 2006.238.07:31:09.44#ibcon#read 3, iclass 29, count 0 2006.238.07:31:09.44#ibcon#about to read 4, iclass 29, count 0 2006.238.07:31:09.44#ibcon#read 4, iclass 29, count 0 2006.238.07:31:09.44#ibcon#about to read 5, iclass 29, count 0 2006.238.07:31:09.44#ibcon#read 5, iclass 29, count 0 2006.238.07:31:09.44#ibcon#about to read 6, iclass 29, count 0 2006.238.07:31:09.44#ibcon#read 6, iclass 29, count 0 2006.238.07:31:09.44#ibcon#end of sib2, iclass 29, count 0 2006.238.07:31:09.44#ibcon#*after write, iclass 29, count 0 2006.238.07:31:09.44#ibcon#*before return 0, iclass 29, count 0 2006.238.07:31:09.44#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:31:09.44#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:31:09.44#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:31:09.44#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:31:09.44$vc4f8/valo=8,852.99 2006.238.07:31:09.44#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.07:31:09.44#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.07:31:09.44#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:09.44#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:31:09.44#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:31:09.44#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:31:09.44#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:31:09.44#ibcon#first serial, iclass 31, count 0 2006.238.07:31:09.44#ibcon#enter sib2, iclass 31, count 0 2006.238.07:31:09.44#ibcon#flushed, iclass 31, count 0 2006.238.07:31:09.44#ibcon#about to write, iclass 31, count 0 2006.238.07:31:09.44#ibcon#wrote, iclass 31, count 0 2006.238.07:31:09.44#ibcon#about to read 3, iclass 31, count 0 2006.238.07:31:09.46#ibcon#read 3, iclass 31, count 0 2006.238.07:31:09.46#ibcon#about to read 4, iclass 31, count 0 2006.238.07:31:09.46#ibcon#read 4, iclass 31, count 0 2006.238.07:31:09.46#ibcon#about to read 5, iclass 31, count 0 2006.238.07:31:09.46#ibcon#read 5, iclass 31, count 0 2006.238.07:31:09.46#ibcon#about to read 6, iclass 31, count 0 2006.238.07:31:09.46#ibcon#read 6, iclass 31, count 0 2006.238.07:31:09.46#ibcon#end of sib2, iclass 31, count 0 2006.238.07:31:09.46#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:31:09.46#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:31:09.46#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:31:09.46#ibcon#*before write, iclass 31, count 0 2006.238.07:31:09.46#ibcon#enter sib2, iclass 31, count 0 2006.238.07:31:09.46#ibcon#flushed, iclass 31, count 0 2006.238.07:31:09.46#ibcon#about to write, iclass 31, count 0 2006.238.07:31:09.46#ibcon#wrote, iclass 31, count 0 2006.238.07:31:09.46#ibcon#about to read 3, iclass 31, count 0 2006.238.07:31:09.50#ibcon#read 3, iclass 31, count 0 2006.238.07:31:09.50#ibcon#about to read 4, iclass 31, count 0 2006.238.07:31:09.50#ibcon#read 4, iclass 31, count 0 2006.238.07:31:09.50#ibcon#about to read 5, iclass 31, count 0 2006.238.07:31:09.50#ibcon#read 5, iclass 31, count 0 2006.238.07:31:09.50#ibcon#about to read 6, iclass 31, count 0 2006.238.07:31:09.50#ibcon#read 6, iclass 31, count 0 2006.238.07:31:09.50#ibcon#end of sib2, iclass 31, count 0 2006.238.07:31:09.50#ibcon#*after write, iclass 31, count 0 2006.238.07:31:09.50#ibcon#*before return 0, iclass 31, count 0 2006.238.07:31:09.50#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:31:09.50#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:31:09.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:31:09.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:31:09.50$vc4f8/va=8,7 2006.238.07:31:09.50#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:31:09.50#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:31:09.50#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:09.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:31:09.56#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:31:09.56#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:31:09.56#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:31:09.56#ibcon#first serial, iclass 33, count 2 2006.238.07:31:09.56#ibcon#enter sib2, iclass 33, count 2 2006.238.07:31:09.56#ibcon#flushed, iclass 33, count 2 2006.238.07:31:09.56#ibcon#about to write, iclass 33, count 2 2006.238.07:31:09.56#ibcon#wrote, iclass 33, count 2 2006.238.07:31:09.56#ibcon#about to read 3, iclass 33, count 2 2006.238.07:31:09.58#ibcon#read 3, iclass 33, count 2 2006.238.07:31:09.58#ibcon#about to read 4, iclass 33, count 2 2006.238.07:31:09.58#ibcon#read 4, iclass 33, count 2 2006.238.07:31:09.58#ibcon#about to read 5, iclass 33, count 2 2006.238.07:31:09.58#ibcon#read 5, iclass 33, count 2 2006.238.07:31:09.58#ibcon#about to read 6, iclass 33, count 2 2006.238.07:31:09.58#ibcon#read 6, iclass 33, count 2 2006.238.07:31:09.58#ibcon#end of sib2, iclass 33, count 2 2006.238.07:31:09.58#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:31:09.58#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:31:09.58#ibcon#[25=AT08-07\r\n] 2006.238.07:31:09.58#ibcon#*before write, iclass 33, count 2 2006.238.07:31:09.58#ibcon#enter sib2, iclass 33, count 2 2006.238.07:31:09.58#ibcon#flushed, iclass 33, count 2 2006.238.07:31:09.58#ibcon#about to write, iclass 33, count 2 2006.238.07:31:09.58#ibcon#wrote, iclass 33, count 2 2006.238.07:31:09.58#ibcon#about to read 3, iclass 33, count 2 2006.238.07:31:09.61#ibcon#read 3, iclass 33, count 2 2006.238.07:31:09.61#ibcon#about to read 4, iclass 33, count 2 2006.238.07:31:09.61#ibcon#read 4, iclass 33, count 2 2006.238.07:31:09.61#ibcon#about to read 5, iclass 33, count 2 2006.238.07:31:09.61#ibcon#read 5, iclass 33, count 2 2006.238.07:31:09.61#ibcon#about to read 6, iclass 33, count 2 2006.238.07:31:09.61#ibcon#read 6, iclass 33, count 2 2006.238.07:31:09.61#ibcon#end of sib2, iclass 33, count 2 2006.238.07:31:09.61#ibcon#*after write, iclass 33, count 2 2006.238.07:31:09.61#ibcon#*before return 0, iclass 33, count 2 2006.238.07:31:09.61#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:31:09.61#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:31:09.61#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:31:09.61#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:09.61#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:31:09.73#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:31:09.73#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:31:09.73#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:31:09.73#ibcon#first serial, iclass 33, count 0 2006.238.07:31:09.73#ibcon#enter sib2, iclass 33, count 0 2006.238.07:31:09.73#ibcon#flushed, iclass 33, count 0 2006.238.07:31:09.73#ibcon#about to write, iclass 33, count 0 2006.238.07:31:09.73#ibcon#wrote, iclass 33, count 0 2006.238.07:31:09.73#ibcon#about to read 3, iclass 33, count 0 2006.238.07:31:09.75#ibcon#read 3, iclass 33, count 0 2006.238.07:31:09.75#ibcon#about to read 4, iclass 33, count 0 2006.238.07:31:09.75#ibcon#read 4, iclass 33, count 0 2006.238.07:31:09.75#ibcon#about to read 5, iclass 33, count 0 2006.238.07:31:09.75#ibcon#read 5, iclass 33, count 0 2006.238.07:31:09.75#ibcon#about to read 6, iclass 33, count 0 2006.238.07:31:09.75#ibcon#read 6, iclass 33, count 0 2006.238.07:31:09.75#ibcon#end of sib2, iclass 33, count 0 2006.238.07:31:09.75#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:31:09.75#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:31:09.75#ibcon#[25=USB\r\n] 2006.238.07:31:09.75#ibcon#*before write, iclass 33, count 0 2006.238.07:31:09.75#ibcon#enter sib2, iclass 33, count 0 2006.238.07:31:09.75#ibcon#flushed, iclass 33, count 0 2006.238.07:31:09.75#ibcon#about to write, iclass 33, count 0 2006.238.07:31:09.75#ibcon#wrote, iclass 33, count 0 2006.238.07:31:09.75#ibcon#about to read 3, iclass 33, count 0 2006.238.07:31:09.78#ibcon#read 3, iclass 33, count 0 2006.238.07:31:09.78#ibcon#about to read 4, iclass 33, count 0 2006.238.07:31:09.78#ibcon#read 4, iclass 33, count 0 2006.238.07:31:09.78#ibcon#about to read 5, iclass 33, count 0 2006.238.07:31:09.78#ibcon#read 5, iclass 33, count 0 2006.238.07:31:09.78#ibcon#about to read 6, iclass 33, count 0 2006.238.07:31:09.78#ibcon#read 6, iclass 33, count 0 2006.238.07:31:09.78#ibcon#end of sib2, iclass 33, count 0 2006.238.07:31:09.78#ibcon#*after write, iclass 33, count 0 2006.238.07:31:09.78#ibcon#*before return 0, iclass 33, count 0 2006.238.07:31:09.78#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:31:09.78#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:31:09.78#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:31:09.78#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:31:09.78$vc4f8/vblo=1,632.99 2006.238.07:31:09.78#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:31:09.78#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:31:09.78#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:09.78#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:31:09.78#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:31:09.78#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:31:09.78#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:31:09.78#ibcon#first serial, iclass 35, count 0 2006.238.07:31:09.78#ibcon#enter sib2, iclass 35, count 0 2006.238.07:31:09.78#ibcon#flushed, iclass 35, count 0 2006.238.07:31:09.78#ibcon#about to write, iclass 35, count 0 2006.238.07:31:09.78#ibcon#wrote, iclass 35, count 0 2006.238.07:31:09.78#ibcon#about to read 3, iclass 35, count 0 2006.238.07:31:09.80#ibcon#read 3, iclass 35, count 0 2006.238.07:31:09.80#ibcon#about to read 4, iclass 35, count 0 2006.238.07:31:09.80#ibcon#read 4, iclass 35, count 0 2006.238.07:31:09.80#ibcon#about to read 5, iclass 35, count 0 2006.238.07:31:09.80#ibcon#read 5, iclass 35, count 0 2006.238.07:31:09.80#ibcon#about to read 6, iclass 35, count 0 2006.238.07:31:09.80#ibcon#read 6, iclass 35, count 0 2006.238.07:31:09.80#ibcon#end of sib2, iclass 35, count 0 2006.238.07:31:09.80#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:31:09.80#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:31:09.80#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:31:09.80#ibcon#*before write, iclass 35, count 0 2006.238.07:31:09.80#ibcon#enter sib2, iclass 35, count 0 2006.238.07:31:09.80#ibcon#flushed, iclass 35, count 0 2006.238.07:31:09.80#ibcon#about to write, iclass 35, count 0 2006.238.07:31:09.80#ibcon#wrote, iclass 35, count 0 2006.238.07:31:09.80#ibcon#about to read 3, iclass 35, count 0 2006.238.07:31:09.84#ibcon#read 3, iclass 35, count 0 2006.238.07:31:09.84#ibcon#about to read 4, iclass 35, count 0 2006.238.07:31:09.84#ibcon#read 4, iclass 35, count 0 2006.238.07:31:09.84#ibcon#about to read 5, iclass 35, count 0 2006.238.07:31:09.84#ibcon#read 5, iclass 35, count 0 2006.238.07:31:09.84#ibcon#about to read 6, iclass 35, count 0 2006.238.07:31:09.84#ibcon#read 6, iclass 35, count 0 2006.238.07:31:09.84#ibcon#end of sib2, iclass 35, count 0 2006.238.07:31:09.84#ibcon#*after write, iclass 35, count 0 2006.238.07:31:09.84#ibcon#*before return 0, iclass 35, count 0 2006.238.07:31:09.84#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:31:09.84#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:31:09.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:31:09.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:31:09.84$vc4f8/vb=1,4 2006.238.07:31:09.84#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.07:31:09.84#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.07:31:09.84#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:09.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:31:09.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:31:09.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:31:09.84#ibcon#enter wrdev, iclass 37, count 2 2006.238.07:31:09.84#ibcon#first serial, iclass 37, count 2 2006.238.07:31:09.84#ibcon#enter sib2, iclass 37, count 2 2006.238.07:31:09.84#ibcon#flushed, iclass 37, count 2 2006.238.07:31:09.84#ibcon#about to write, iclass 37, count 2 2006.238.07:31:09.84#ibcon#wrote, iclass 37, count 2 2006.238.07:31:09.84#ibcon#about to read 3, iclass 37, count 2 2006.238.07:31:09.86#ibcon#read 3, iclass 37, count 2 2006.238.07:31:09.86#ibcon#about to read 4, iclass 37, count 2 2006.238.07:31:09.86#ibcon#read 4, iclass 37, count 2 2006.238.07:31:09.86#ibcon#about to read 5, iclass 37, count 2 2006.238.07:31:09.86#ibcon#read 5, iclass 37, count 2 2006.238.07:31:09.86#ibcon#about to read 6, iclass 37, count 2 2006.238.07:31:09.86#ibcon#read 6, iclass 37, count 2 2006.238.07:31:09.86#ibcon#end of sib2, iclass 37, count 2 2006.238.07:31:09.86#ibcon#*mode == 0, iclass 37, count 2 2006.238.07:31:09.86#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.07:31:09.86#ibcon#[27=AT01-04\r\n] 2006.238.07:31:09.86#ibcon#*before write, iclass 37, count 2 2006.238.07:31:09.86#ibcon#enter sib2, iclass 37, count 2 2006.238.07:31:09.86#ibcon#flushed, iclass 37, count 2 2006.238.07:31:09.86#ibcon#about to write, iclass 37, count 2 2006.238.07:31:09.86#ibcon#wrote, iclass 37, count 2 2006.238.07:31:09.86#ibcon#about to read 3, iclass 37, count 2 2006.238.07:31:09.89#ibcon#read 3, iclass 37, count 2 2006.238.07:31:09.89#ibcon#about to read 4, iclass 37, count 2 2006.238.07:31:09.89#ibcon#read 4, iclass 37, count 2 2006.238.07:31:09.89#ibcon#about to read 5, iclass 37, count 2 2006.238.07:31:09.89#ibcon#read 5, iclass 37, count 2 2006.238.07:31:09.89#ibcon#about to read 6, iclass 37, count 2 2006.238.07:31:09.89#ibcon#read 6, iclass 37, count 2 2006.238.07:31:09.89#ibcon#end of sib2, iclass 37, count 2 2006.238.07:31:09.89#ibcon#*after write, iclass 37, count 2 2006.238.07:31:09.89#ibcon#*before return 0, iclass 37, count 2 2006.238.07:31:09.89#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:31:09.89#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:31:09.89#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.07:31:09.89#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:09.89#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:31:10.02#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:31:10.02#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:31:10.02#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:31:10.02#ibcon#first serial, iclass 37, count 0 2006.238.07:31:10.02#ibcon#enter sib2, iclass 37, count 0 2006.238.07:31:10.02#ibcon#flushed, iclass 37, count 0 2006.238.07:31:10.02#ibcon#about to write, iclass 37, count 0 2006.238.07:31:10.02#ibcon#wrote, iclass 37, count 0 2006.238.07:31:10.02#ibcon#about to read 3, iclass 37, count 0 2006.238.07:31:10.03#ibcon#read 3, iclass 37, count 0 2006.238.07:31:10.03#ibcon#about to read 4, iclass 37, count 0 2006.238.07:31:10.03#ibcon#read 4, iclass 37, count 0 2006.238.07:31:10.03#ibcon#about to read 5, iclass 37, count 0 2006.238.07:31:10.03#ibcon#read 5, iclass 37, count 0 2006.238.07:31:10.03#ibcon#about to read 6, iclass 37, count 0 2006.238.07:31:10.03#ibcon#read 6, iclass 37, count 0 2006.238.07:31:10.03#ibcon#end of sib2, iclass 37, count 0 2006.238.07:31:10.03#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:31:10.03#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:31:10.03#ibcon#[27=USB\r\n] 2006.238.07:31:10.03#ibcon#*before write, iclass 37, count 0 2006.238.07:31:10.03#ibcon#enter sib2, iclass 37, count 0 2006.238.07:31:10.03#ibcon#flushed, iclass 37, count 0 2006.238.07:31:10.03#ibcon#about to write, iclass 37, count 0 2006.238.07:31:10.03#ibcon#wrote, iclass 37, count 0 2006.238.07:31:10.03#ibcon#about to read 3, iclass 37, count 0 2006.238.07:31:10.06#ibcon#read 3, iclass 37, count 0 2006.238.07:31:10.06#ibcon#about to read 4, iclass 37, count 0 2006.238.07:31:10.06#ibcon#read 4, iclass 37, count 0 2006.238.07:31:10.06#ibcon#about to read 5, iclass 37, count 0 2006.238.07:31:10.06#ibcon#read 5, iclass 37, count 0 2006.238.07:31:10.06#ibcon#about to read 6, iclass 37, count 0 2006.238.07:31:10.06#ibcon#read 6, iclass 37, count 0 2006.238.07:31:10.06#ibcon#end of sib2, iclass 37, count 0 2006.238.07:31:10.06#ibcon#*after write, iclass 37, count 0 2006.238.07:31:10.06#ibcon#*before return 0, iclass 37, count 0 2006.238.07:31:10.06#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:31:10.06#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:31:10.06#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:31:10.06#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:31:10.06$vc4f8/vblo=2,640.99 2006.238.07:31:10.06#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.07:31:10.06#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.07:31:10.06#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:10.06#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:31:10.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:31:10.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:31:10.06#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:31:10.06#ibcon#first serial, iclass 39, count 0 2006.238.07:31:10.06#ibcon#enter sib2, iclass 39, count 0 2006.238.07:31:10.06#ibcon#flushed, iclass 39, count 0 2006.238.07:31:10.06#ibcon#about to write, iclass 39, count 0 2006.238.07:31:10.06#ibcon#wrote, iclass 39, count 0 2006.238.07:31:10.06#ibcon#about to read 3, iclass 39, count 0 2006.238.07:31:10.08#ibcon#read 3, iclass 39, count 0 2006.238.07:31:10.08#ibcon#about to read 4, iclass 39, count 0 2006.238.07:31:10.08#ibcon#read 4, iclass 39, count 0 2006.238.07:31:10.08#ibcon#about to read 5, iclass 39, count 0 2006.238.07:31:10.08#ibcon#read 5, iclass 39, count 0 2006.238.07:31:10.08#ibcon#about to read 6, iclass 39, count 0 2006.238.07:31:10.08#ibcon#read 6, iclass 39, count 0 2006.238.07:31:10.08#ibcon#end of sib2, iclass 39, count 0 2006.238.07:31:10.08#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:31:10.08#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:31:10.08#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:31:10.08#ibcon#*before write, iclass 39, count 0 2006.238.07:31:10.08#ibcon#enter sib2, iclass 39, count 0 2006.238.07:31:10.08#ibcon#flushed, iclass 39, count 0 2006.238.07:31:10.08#ibcon#about to write, iclass 39, count 0 2006.238.07:31:10.08#ibcon#wrote, iclass 39, count 0 2006.238.07:31:10.08#ibcon#about to read 3, iclass 39, count 0 2006.238.07:31:10.12#ibcon#read 3, iclass 39, count 0 2006.238.07:31:10.12#ibcon#about to read 4, iclass 39, count 0 2006.238.07:31:10.12#ibcon#read 4, iclass 39, count 0 2006.238.07:31:10.12#ibcon#about to read 5, iclass 39, count 0 2006.238.07:31:10.12#ibcon#read 5, iclass 39, count 0 2006.238.07:31:10.12#ibcon#about to read 6, iclass 39, count 0 2006.238.07:31:10.12#ibcon#read 6, iclass 39, count 0 2006.238.07:31:10.12#ibcon#end of sib2, iclass 39, count 0 2006.238.07:31:10.12#ibcon#*after write, iclass 39, count 0 2006.238.07:31:10.12#ibcon#*before return 0, iclass 39, count 0 2006.238.07:31:10.12#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:31:10.12#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:31:10.12#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:31:10.12#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:31:10.12$vc4f8/vb=2,4 2006.238.07:31:10.12#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.07:31:10.12#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.07:31:10.12#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:10.12#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:31:10.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:31:10.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:31:10.18#ibcon#enter wrdev, iclass 3, count 2 2006.238.07:31:10.18#ibcon#first serial, iclass 3, count 2 2006.238.07:31:10.18#ibcon#enter sib2, iclass 3, count 2 2006.238.07:31:10.18#ibcon#flushed, iclass 3, count 2 2006.238.07:31:10.18#ibcon#about to write, iclass 3, count 2 2006.238.07:31:10.18#ibcon#wrote, iclass 3, count 2 2006.238.07:31:10.18#ibcon#about to read 3, iclass 3, count 2 2006.238.07:31:10.20#ibcon#read 3, iclass 3, count 2 2006.238.07:31:10.20#ibcon#about to read 4, iclass 3, count 2 2006.238.07:31:10.20#ibcon#read 4, iclass 3, count 2 2006.238.07:31:10.20#ibcon#about to read 5, iclass 3, count 2 2006.238.07:31:10.20#ibcon#read 5, iclass 3, count 2 2006.238.07:31:10.20#ibcon#about to read 6, iclass 3, count 2 2006.238.07:31:10.20#ibcon#read 6, iclass 3, count 2 2006.238.07:31:10.20#ibcon#end of sib2, iclass 3, count 2 2006.238.07:31:10.20#ibcon#*mode == 0, iclass 3, count 2 2006.238.07:31:10.20#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.07:31:10.20#ibcon#[27=AT02-04\r\n] 2006.238.07:31:10.20#ibcon#*before write, iclass 3, count 2 2006.238.07:31:10.20#ibcon#enter sib2, iclass 3, count 2 2006.238.07:31:10.20#ibcon#flushed, iclass 3, count 2 2006.238.07:31:10.20#ibcon#about to write, iclass 3, count 2 2006.238.07:31:10.20#ibcon#wrote, iclass 3, count 2 2006.238.07:31:10.20#ibcon#about to read 3, iclass 3, count 2 2006.238.07:31:10.23#ibcon#read 3, iclass 3, count 2 2006.238.07:31:10.23#ibcon#about to read 4, iclass 3, count 2 2006.238.07:31:10.23#ibcon#read 4, iclass 3, count 2 2006.238.07:31:10.23#ibcon#about to read 5, iclass 3, count 2 2006.238.07:31:10.23#ibcon#read 5, iclass 3, count 2 2006.238.07:31:10.23#ibcon#about to read 6, iclass 3, count 2 2006.238.07:31:10.23#ibcon#read 6, iclass 3, count 2 2006.238.07:31:10.23#ibcon#end of sib2, iclass 3, count 2 2006.238.07:31:10.23#ibcon#*after write, iclass 3, count 2 2006.238.07:31:10.23#ibcon#*before return 0, iclass 3, count 2 2006.238.07:31:10.23#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:31:10.23#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:31:10.23#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.07:31:10.23#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:10.23#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:31:10.35#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:31:10.35#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:31:10.35#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:31:10.35#ibcon#first serial, iclass 3, count 0 2006.238.07:31:10.35#ibcon#enter sib2, iclass 3, count 0 2006.238.07:31:10.35#ibcon#flushed, iclass 3, count 0 2006.238.07:31:10.35#ibcon#about to write, iclass 3, count 0 2006.238.07:31:10.35#ibcon#wrote, iclass 3, count 0 2006.238.07:31:10.35#ibcon#about to read 3, iclass 3, count 0 2006.238.07:31:10.37#ibcon#read 3, iclass 3, count 0 2006.238.07:31:10.37#ibcon#about to read 4, iclass 3, count 0 2006.238.07:31:10.37#ibcon#read 4, iclass 3, count 0 2006.238.07:31:10.37#ibcon#about to read 5, iclass 3, count 0 2006.238.07:31:10.37#ibcon#read 5, iclass 3, count 0 2006.238.07:31:10.37#ibcon#about to read 6, iclass 3, count 0 2006.238.07:31:10.37#ibcon#read 6, iclass 3, count 0 2006.238.07:31:10.37#ibcon#end of sib2, iclass 3, count 0 2006.238.07:31:10.37#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:31:10.37#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:31:10.37#ibcon#[27=USB\r\n] 2006.238.07:31:10.37#ibcon#*before write, iclass 3, count 0 2006.238.07:31:10.37#ibcon#enter sib2, iclass 3, count 0 2006.238.07:31:10.37#ibcon#flushed, iclass 3, count 0 2006.238.07:31:10.37#ibcon#about to write, iclass 3, count 0 2006.238.07:31:10.37#ibcon#wrote, iclass 3, count 0 2006.238.07:31:10.37#ibcon#about to read 3, iclass 3, count 0 2006.238.07:31:10.40#ibcon#read 3, iclass 3, count 0 2006.238.07:31:10.40#ibcon#about to read 4, iclass 3, count 0 2006.238.07:31:10.40#ibcon#read 4, iclass 3, count 0 2006.238.07:31:10.40#ibcon#about to read 5, iclass 3, count 0 2006.238.07:31:10.40#ibcon#read 5, iclass 3, count 0 2006.238.07:31:10.40#ibcon#about to read 6, iclass 3, count 0 2006.238.07:31:10.40#ibcon#read 6, iclass 3, count 0 2006.238.07:31:10.40#ibcon#end of sib2, iclass 3, count 0 2006.238.07:31:10.40#ibcon#*after write, iclass 3, count 0 2006.238.07:31:10.40#ibcon#*before return 0, iclass 3, count 0 2006.238.07:31:10.40#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:31:10.40#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:31:10.40#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:31:10.40#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:31:10.40$vc4f8/vblo=3,656.99 2006.238.07:31:10.40#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.07:31:10.40#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.07:31:10.40#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:10.40#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:31:10.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:31:10.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:31:10.40#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:31:10.40#ibcon#first serial, iclass 5, count 0 2006.238.07:31:10.40#ibcon#enter sib2, iclass 5, count 0 2006.238.07:31:10.40#ibcon#flushed, iclass 5, count 0 2006.238.07:31:10.40#ibcon#about to write, iclass 5, count 0 2006.238.07:31:10.40#ibcon#wrote, iclass 5, count 0 2006.238.07:31:10.40#ibcon#about to read 3, iclass 5, count 0 2006.238.07:31:10.42#ibcon#read 3, iclass 5, count 0 2006.238.07:31:10.42#ibcon#about to read 4, iclass 5, count 0 2006.238.07:31:10.42#ibcon#read 4, iclass 5, count 0 2006.238.07:31:10.42#ibcon#about to read 5, iclass 5, count 0 2006.238.07:31:10.42#ibcon#read 5, iclass 5, count 0 2006.238.07:31:10.42#ibcon#about to read 6, iclass 5, count 0 2006.238.07:31:10.42#ibcon#read 6, iclass 5, count 0 2006.238.07:31:10.42#ibcon#end of sib2, iclass 5, count 0 2006.238.07:31:10.42#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:31:10.42#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:31:10.42#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:31:10.42#ibcon#*before write, iclass 5, count 0 2006.238.07:31:10.42#ibcon#enter sib2, iclass 5, count 0 2006.238.07:31:10.42#ibcon#flushed, iclass 5, count 0 2006.238.07:31:10.42#ibcon#about to write, iclass 5, count 0 2006.238.07:31:10.42#ibcon#wrote, iclass 5, count 0 2006.238.07:31:10.42#ibcon#about to read 3, iclass 5, count 0 2006.238.07:31:10.46#ibcon#read 3, iclass 5, count 0 2006.238.07:31:10.46#ibcon#about to read 4, iclass 5, count 0 2006.238.07:31:10.46#ibcon#read 4, iclass 5, count 0 2006.238.07:31:10.46#ibcon#about to read 5, iclass 5, count 0 2006.238.07:31:10.46#ibcon#read 5, iclass 5, count 0 2006.238.07:31:10.46#ibcon#about to read 6, iclass 5, count 0 2006.238.07:31:10.46#ibcon#read 6, iclass 5, count 0 2006.238.07:31:10.46#ibcon#end of sib2, iclass 5, count 0 2006.238.07:31:10.46#ibcon#*after write, iclass 5, count 0 2006.238.07:31:10.46#ibcon#*before return 0, iclass 5, count 0 2006.238.07:31:10.46#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:31:10.46#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:31:10.46#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:31:10.46#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:31:10.46$vc4f8/vb=3,4 2006.238.07:31:10.46#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.07:31:10.46#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.07:31:10.46#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:10.46#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:31:10.53#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:31:10.53#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:31:10.53#ibcon#enter wrdev, iclass 7, count 2 2006.238.07:31:10.53#ibcon#first serial, iclass 7, count 2 2006.238.07:31:10.53#ibcon#enter sib2, iclass 7, count 2 2006.238.07:31:10.53#ibcon#flushed, iclass 7, count 2 2006.238.07:31:10.53#ibcon#about to write, iclass 7, count 2 2006.238.07:31:10.53#ibcon#wrote, iclass 7, count 2 2006.238.07:31:10.53#ibcon#about to read 3, iclass 7, count 2 2006.238.07:31:10.54#ibcon#read 3, iclass 7, count 2 2006.238.07:31:10.54#ibcon#about to read 4, iclass 7, count 2 2006.238.07:31:10.54#ibcon#read 4, iclass 7, count 2 2006.238.07:31:10.54#ibcon#about to read 5, iclass 7, count 2 2006.238.07:31:10.54#ibcon#read 5, iclass 7, count 2 2006.238.07:31:10.54#ibcon#about to read 6, iclass 7, count 2 2006.238.07:31:10.54#ibcon#read 6, iclass 7, count 2 2006.238.07:31:10.54#ibcon#end of sib2, iclass 7, count 2 2006.238.07:31:10.54#ibcon#*mode == 0, iclass 7, count 2 2006.238.07:31:10.54#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.07:31:10.54#ibcon#[27=AT03-04\r\n] 2006.238.07:31:10.54#ibcon#*before write, iclass 7, count 2 2006.238.07:31:10.54#ibcon#enter sib2, iclass 7, count 2 2006.238.07:31:10.54#ibcon#flushed, iclass 7, count 2 2006.238.07:31:10.54#ibcon#about to write, iclass 7, count 2 2006.238.07:31:10.54#ibcon#wrote, iclass 7, count 2 2006.238.07:31:10.54#ibcon#about to read 3, iclass 7, count 2 2006.238.07:31:10.57#ibcon#read 3, iclass 7, count 2 2006.238.07:31:10.57#ibcon#about to read 4, iclass 7, count 2 2006.238.07:31:10.57#ibcon#read 4, iclass 7, count 2 2006.238.07:31:10.57#ibcon#about to read 5, iclass 7, count 2 2006.238.07:31:10.57#ibcon#read 5, iclass 7, count 2 2006.238.07:31:10.57#ibcon#about to read 6, iclass 7, count 2 2006.238.07:31:10.57#ibcon#read 6, iclass 7, count 2 2006.238.07:31:10.57#ibcon#end of sib2, iclass 7, count 2 2006.238.07:31:10.57#ibcon#*after write, iclass 7, count 2 2006.238.07:31:10.57#ibcon#*before return 0, iclass 7, count 2 2006.238.07:31:10.57#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:31:10.57#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:31:10.57#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.07:31:10.57#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:10.57#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:31:10.69#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:31:10.69#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:31:10.69#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:31:10.69#ibcon#first serial, iclass 7, count 0 2006.238.07:31:10.69#ibcon#enter sib2, iclass 7, count 0 2006.238.07:31:10.69#ibcon#flushed, iclass 7, count 0 2006.238.07:31:10.69#ibcon#about to write, iclass 7, count 0 2006.238.07:31:10.69#ibcon#wrote, iclass 7, count 0 2006.238.07:31:10.69#ibcon#about to read 3, iclass 7, count 0 2006.238.07:31:10.71#ibcon#read 3, iclass 7, count 0 2006.238.07:31:10.71#ibcon#about to read 4, iclass 7, count 0 2006.238.07:31:10.71#ibcon#read 4, iclass 7, count 0 2006.238.07:31:10.71#ibcon#about to read 5, iclass 7, count 0 2006.238.07:31:10.71#ibcon#read 5, iclass 7, count 0 2006.238.07:31:10.71#ibcon#about to read 6, iclass 7, count 0 2006.238.07:31:10.71#ibcon#read 6, iclass 7, count 0 2006.238.07:31:10.71#ibcon#end of sib2, iclass 7, count 0 2006.238.07:31:10.71#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:31:10.71#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:31:10.71#ibcon#[27=USB\r\n] 2006.238.07:31:10.71#ibcon#*before write, iclass 7, count 0 2006.238.07:31:10.71#ibcon#enter sib2, iclass 7, count 0 2006.238.07:31:10.71#ibcon#flushed, iclass 7, count 0 2006.238.07:31:10.71#ibcon#about to write, iclass 7, count 0 2006.238.07:31:10.71#ibcon#wrote, iclass 7, count 0 2006.238.07:31:10.71#ibcon#about to read 3, iclass 7, count 0 2006.238.07:31:10.74#ibcon#read 3, iclass 7, count 0 2006.238.07:31:10.74#ibcon#about to read 4, iclass 7, count 0 2006.238.07:31:10.74#ibcon#read 4, iclass 7, count 0 2006.238.07:31:10.74#ibcon#about to read 5, iclass 7, count 0 2006.238.07:31:10.74#ibcon#read 5, iclass 7, count 0 2006.238.07:31:10.74#ibcon#about to read 6, iclass 7, count 0 2006.238.07:31:10.74#ibcon#read 6, iclass 7, count 0 2006.238.07:31:10.74#ibcon#end of sib2, iclass 7, count 0 2006.238.07:31:10.74#ibcon#*after write, iclass 7, count 0 2006.238.07:31:10.74#ibcon#*before return 0, iclass 7, count 0 2006.238.07:31:10.74#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:31:10.74#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:31:10.74#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:31:10.74#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:31:10.74$vc4f8/vblo=4,712.99 2006.238.07:31:10.74#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.07:31:10.74#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.07:31:10.74#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:10.74#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:31:10.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:31:10.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:31:10.74#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:31:10.74#ibcon#first serial, iclass 11, count 0 2006.238.07:31:10.74#ibcon#enter sib2, iclass 11, count 0 2006.238.07:31:10.74#ibcon#flushed, iclass 11, count 0 2006.238.07:31:10.74#ibcon#about to write, iclass 11, count 0 2006.238.07:31:10.74#ibcon#wrote, iclass 11, count 0 2006.238.07:31:10.74#ibcon#about to read 3, iclass 11, count 0 2006.238.07:31:10.76#ibcon#read 3, iclass 11, count 0 2006.238.07:31:10.76#ibcon#about to read 4, iclass 11, count 0 2006.238.07:31:10.76#ibcon#read 4, iclass 11, count 0 2006.238.07:31:10.76#ibcon#about to read 5, iclass 11, count 0 2006.238.07:31:10.76#ibcon#read 5, iclass 11, count 0 2006.238.07:31:10.76#ibcon#about to read 6, iclass 11, count 0 2006.238.07:31:10.76#ibcon#read 6, iclass 11, count 0 2006.238.07:31:10.76#ibcon#end of sib2, iclass 11, count 0 2006.238.07:31:10.76#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:31:10.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:31:10.76#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:31:10.76#ibcon#*before write, iclass 11, count 0 2006.238.07:31:10.76#ibcon#enter sib2, iclass 11, count 0 2006.238.07:31:10.76#ibcon#flushed, iclass 11, count 0 2006.238.07:31:10.76#ibcon#about to write, iclass 11, count 0 2006.238.07:31:10.76#ibcon#wrote, iclass 11, count 0 2006.238.07:31:10.76#ibcon#about to read 3, iclass 11, count 0 2006.238.07:31:10.80#ibcon#read 3, iclass 11, count 0 2006.238.07:31:10.80#ibcon#about to read 4, iclass 11, count 0 2006.238.07:31:10.80#ibcon#read 4, iclass 11, count 0 2006.238.07:31:10.80#ibcon#about to read 5, iclass 11, count 0 2006.238.07:31:10.80#ibcon#read 5, iclass 11, count 0 2006.238.07:31:10.80#ibcon#about to read 6, iclass 11, count 0 2006.238.07:31:10.80#ibcon#read 6, iclass 11, count 0 2006.238.07:31:10.80#ibcon#end of sib2, iclass 11, count 0 2006.238.07:31:10.80#ibcon#*after write, iclass 11, count 0 2006.238.07:31:10.80#ibcon#*before return 0, iclass 11, count 0 2006.238.07:31:10.80#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:31:10.80#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:31:10.80#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:31:10.80#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:31:10.80$vc4f8/vb=4,4 2006.238.07:31:10.80#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.07:31:10.80#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.07:31:10.80#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:10.80#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:31:10.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:31:10.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:31:10.86#ibcon#enter wrdev, iclass 13, count 2 2006.238.07:31:10.86#ibcon#first serial, iclass 13, count 2 2006.238.07:31:10.86#ibcon#enter sib2, iclass 13, count 2 2006.238.07:31:10.86#ibcon#flushed, iclass 13, count 2 2006.238.07:31:10.86#ibcon#about to write, iclass 13, count 2 2006.238.07:31:10.86#ibcon#wrote, iclass 13, count 2 2006.238.07:31:10.86#ibcon#about to read 3, iclass 13, count 2 2006.238.07:31:10.88#ibcon#read 3, iclass 13, count 2 2006.238.07:31:10.88#ibcon#about to read 4, iclass 13, count 2 2006.238.07:31:10.88#ibcon#read 4, iclass 13, count 2 2006.238.07:31:10.88#ibcon#about to read 5, iclass 13, count 2 2006.238.07:31:10.88#ibcon#read 5, iclass 13, count 2 2006.238.07:31:10.88#ibcon#about to read 6, iclass 13, count 2 2006.238.07:31:10.88#ibcon#read 6, iclass 13, count 2 2006.238.07:31:10.88#ibcon#end of sib2, iclass 13, count 2 2006.238.07:31:10.88#ibcon#*mode == 0, iclass 13, count 2 2006.238.07:31:10.88#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.07:31:10.88#ibcon#[27=AT04-04\r\n] 2006.238.07:31:10.88#ibcon#*before write, iclass 13, count 2 2006.238.07:31:10.88#ibcon#enter sib2, iclass 13, count 2 2006.238.07:31:10.88#ibcon#flushed, iclass 13, count 2 2006.238.07:31:10.88#ibcon#about to write, iclass 13, count 2 2006.238.07:31:10.88#ibcon#wrote, iclass 13, count 2 2006.238.07:31:10.88#ibcon#about to read 3, iclass 13, count 2 2006.238.07:31:10.91#ibcon#read 3, iclass 13, count 2 2006.238.07:31:10.91#ibcon#about to read 4, iclass 13, count 2 2006.238.07:31:10.91#ibcon#read 4, iclass 13, count 2 2006.238.07:31:10.91#ibcon#about to read 5, iclass 13, count 2 2006.238.07:31:10.91#ibcon#read 5, iclass 13, count 2 2006.238.07:31:10.91#ibcon#about to read 6, iclass 13, count 2 2006.238.07:31:10.91#ibcon#read 6, iclass 13, count 2 2006.238.07:31:10.91#ibcon#end of sib2, iclass 13, count 2 2006.238.07:31:10.91#ibcon#*after write, iclass 13, count 2 2006.238.07:31:10.91#ibcon#*before return 0, iclass 13, count 2 2006.238.07:31:10.91#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:31:10.91#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:31:10.91#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.07:31:10.91#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:10.91#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:31:11.03#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:31:11.03#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:31:11.03#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:31:11.03#ibcon#first serial, iclass 13, count 0 2006.238.07:31:11.03#ibcon#enter sib2, iclass 13, count 0 2006.238.07:31:11.03#ibcon#flushed, iclass 13, count 0 2006.238.07:31:11.03#ibcon#about to write, iclass 13, count 0 2006.238.07:31:11.03#ibcon#wrote, iclass 13, count 0 2006.238.07:31:11.03#ibcon#about to read 3, iclass 13, count 0 2006.238.07:31:11.05#ibcon#read 3, iclass 13, count 0 2006.238.07:31:11.05#ibcon#about to read 4, iclass 13, count 0 2006.238.07:31:11.05#ibcon#read 4, iclass 13, count 0 2006.238.07:31:11.05#ibcon#about to read 5, iclass 13, count 0 2006.238.07:31:11.05#ibcon#read 5, iclass 13, count 0 2006.238.07:31:11.05#ibcon#about to read 6, iclass 13, count 0 2006.238.07:31:11.05#ibcon#read 6, iclass 13, count 0 2006.238.07:31:11.05#ibcon#end of sib2, iclass 13, count 0 2006.238.07:31:11.05#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:31:11.05#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:31:11.05#ibcon#[27=USB\r\n] 2006.238.07:31:11.05#ibcon#*before write, iclass 13, count 0 2006.238.07:31:11.05#ibcon#enter sib2, iclass 13, count 0 2006.238.07:31:11.05#ibcon#flushed, iclass 13, count 0 2006.238.07:31:11.05#ibcon#about to write, iclass 13, count 0 2006.238.07:31:11.05#ibcon#wrote, iclass 13, count 0 2006.238.07:31:11.05#ibcon#about to read 3, iclass 13, count 0 2006.238.07:31:11.08#ibcon#read 3, iclass 13, count 0 2006.238.07:31:11.08#ibcon#about to read 4, iclass 13, count 0 2006.238.07:31:11.08#ibcon#read 4, iclass 13, count 0 2006.238.07:31:11.08#ibcon#about to read 5, iclass 13, count 0 2006.238.07:31:11.08#ibcon#read 5, iclass 13, count 0 2006.238.07:31:11.08#ibcon#about to read 6, iclass 13, count 0 2006.238.07:31:11.08#ibcon#read 6, iclass 13, count 0 2006.238.07:31:11.08#ibcon#end of sib2, iclass 13, count 0 2006.238.07:31:11.08#ibcon#*after write, iclass 13, count 0 2006.238.07:31:11.08#ibcon#*before return 0, iclass 13, count 0 2006.238.07:31:11.08#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:31:11.08#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:31:11.08#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:31:11.08#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:31:11.08$vc4f8/vblo=5,744.99 2006.238.07:31:11.08#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.07:31:11.08#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.07:31:11.08#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:11.08#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:31:11.08#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:31:11.08#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:31:11.08#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:31:11.08#ibcon#first serial, iclass 15, count 0 2006.238.07:31:11.08#ibcon#enter sib2, iclass 15, count 0 2006.238.07:31:11.08#ibcon#flushed, iclass 15, count 0 2006.238.07:31:11.08#ibcon#about to write, iclass 15, count 0 2006.238.07:31:11.08#ibcon#wrote, iclass 15, count 0 2006.238.07:31:11.08#ibcon#about to read 3, iclass 15, count 0 2006.238.07:31:11.10#ibcon#read 3, iclass 15, count 0 2006.238.07:31:11.10#ibcon#about to read 4, iclass 15, count 0 2006.238.07:31:11.10#ibcon#read 4, iclass 15, count 0 2006.238.07:31:11.10#ibcon#about to read 5, iclass 15, count 0 2006.238.07:31:11.10#ibcon#read 5, iclass 15, count 0 2006.238.07:31:11.10#ibcon#about to read 6, iclass 15, count 0 2006.238.07:31:11.10#ibcon#read 6, iclass 15, count 0 2006.238.07:31:11.10#ibcon#end of sib2, iclass 15, count 0 2006.238.07:31:11.10#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:31:11.10#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:31:11.10#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:31:11.10#ibcon#*before write, iclass 15, count 0 2006.238.07:31:11.10#ibcon#enter sib2, iclass 15, count 0 2006.238.07:31:11.10#ibcon#flushed, iclass 15, count 0 2006.238.07:31:11.10#ibcon#about to write, iclass 15, count 0 2006.238.07:31:11.10#ibcon#wrote, iclass 15, count 0 2006.238.07:31:11.10#ibcon#about to read 3, iclass 15, count 0 2006.238.07:31:11.14#ibcon#read 3, iclass 15, count 0 2006.238.07:31:11.14#ibcon#about to read 4, iclass 15, count 0 2006.238.07:31:11.14#ibcon#read 4, iclass 15, count 0 2006.238.07:31:11.14#ibcon#about to read 5, iclass 15, count 0 2006.238.07:31:11.14#ibcon#read 5, iclass 15, count 0 2006.238.07:31:11.14#ibcon#about to read 6, iclass 15, count 0 2006.238.07:31:11.14#ibcon#read 6, iclass 15, count 0 2006.238.07:31:11.14#ibcon#end of sib2, iclass 15, count 0 2006.238.07:31:11.14#ibcon#*after write, iclass 15, count 0 2006.238.07:31:11.14#ibcon#*before return 0, iclass 15, count 0 2006.238.07:31:11.14#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:31:11.14#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:31:11.14#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:31:11.14#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:31:11.14$vc4f8/vb=5,4 2006.238.07:31:11.14#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.07:31:11.14#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.07:31:11.14#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:11.14#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:31:11.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:31:11.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:31:11.20#ibcon#enter wrdev, iclass 17, count 2 2006.238.07:31:11.20#ibcon#first serial, iclass 17, count 2 2006.238.07:31:11.20#ibcon#enter sib2, iclass 17, count 2 2006.238.07:31:11.20#ibcon#flushed, iclass 17, count 2 2006.238.07:31:11.20#ibcon#about to write, iclass 17, count 2 2006.238.07:31:11.20#ibcon#wrote, iclass 17, count 2 2006.238.07:31:11.20#ibcon#about to read 3, iclass 17, count 2 2006.238.07:31:11.22#ibcon#read 3, iclass 17, count 2 2006.238.07:31:11.22#ibcon#about to read 4, iclass 17, count 2 2006.238.07:31:11.22#ibcon#read 4, iclass 17, count 2 2006.238.07:31:11.22#ibcon#about to read 5, iclass 17, count 2 2006.238.07:31:11.22#ibcon#read 5, iclass 17, count 2 2006.238.07:31:11.22#ibcon#about to read 6, iclass 17, count 2 2006.238.07:31:11.22#ibcon#read 6, iclass 17, count 2 2006.238.07:31:11.22#ibcon#end of sib2, iclass 17, count 2 2006.238.07:31:11.22#ibcon#*mode == 0, iclass 17, count 2 2006.238.07:31:11.22#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.07:31:11.22#ibcon#[27=AT05-04\r\n] 2006.238.07:31:11.22#ibcon#*before write, iclass 17, count 2 2006.238.07:31:11.22#ibcon#enter sib2, iclass 17, count 2 2006.238.07:31:11.22#ibcon#flushed, iclass 17, count 2 2006.238.07:31:11.22#ibcon#about to write, iclass 17, count 2 2006.238.07:31:11.22#ibcon#wrote, iclass 17, count 2 2006.238.07:31:11.22#ibcon#about to read 3, iclass 17, count 2 2006.238.07:31:11.26#ibcon#read 3, iclass 17, count 2 2006.238.07:31:11.26#ibcon#about to read 4, iclass 17, count 2 2006.238.07:31:11.26#ibcon#read 4, iclass 17, count 2 2006.238.07:31:11.26#ibcon#about to read 5, iclass 17, count 2 2006.238.07:31:11.26#ibcon#read 5, iclass 17, count 2 2006.238.07:31:11.26#ibcon#about to read 6, iclass 17, count 2 2006.238.07:31:11.26#ibcon#read 6, iclass 17, count 2 2006.238.07:31:11.26#ibcon#end of sib2, iclass 17, count 2 2006.238.07:31:11.26#ibcon#*after write, iclass 17, count 2 2006.238.07:31:11.26#ibcon#*before return 0, iclass 17, count 2 2006.238.07:31:11.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:31:11.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:31:11.26#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.07:31:11.26#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:11.26#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:31:11.38#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:31:11.38#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:31:11.38#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:31:11.38#ibcon#first serial, iclass 17, count 0 2006.238.07:31:11.38#ibcon#enter sib2, iclass 17, count 0 2006.238.07:31:11.38#ibcon#flushed, iclass 17, count 0 2006.238.07:31:11.38#ibcon#about to write, iclass 17, count 0 2006.238.07:31:11.38#ibcon#wrote, iclass 17, count 0 2006.238.07:31:11.38#ibcon#about to read 3, iclass 17, count 0 2006.238.07:31:11.39#ibcon#read 3, iclass 17, count 0 2006.238.07:31:11.39#ibcon#about to read 4, iclass 17, count 0 2006.238.07:31:11.39#ibcon#read 4, iclass 17, count 0 2006.238.07:31:11.39#ibcon#about to read 5, iclass 17, count 0 2006.238.07:31:11.39#ibcon#read 5, iclass 17, count 0 2006.238.07:31:11.39#ibcon#about to read 6, iclass 17, count 0 2006.238.07:31:11.39#ibcon#read 6, iclass 17, count 0 2006.238.07:31:11.39#ibcon#end of sib2, iclass 17, count 0 2006.238.07:31:11.39#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:31:11.39#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:31:11.39#ibcon#[27=USB\r\n] 2006.238.07:31:11.39#ibcon#*before write, iclass 17, count 0 2006.238.07:31:11.39#ibcon#enter sib2, iclass 17, count 0 2006.238.07:31:11.39#ibcon#flushed, iclass 17, count 0 2006.238.07:31:11.39#ibcon#about to write, iclass 17, count 0 2006.238.07:31:11.39#ibcon#wrote, iclass 17, count 0 2006.238.07:31:11.39#ibcon#about to read 3, iclass 17, count 0 2006.238.07:31:11.42#ibcon#read 3, iclass 17, count 0 2006.238.07:31:11.42#ibcon#about to read 4, iclass 17, count 0 2006.238.07:31:11.42#ibcon#read 4, iclass 17, count 0 2006.238.07:31:11.42#ibcon#about to read 5, iclass 17, count 0 2006.238.07:31:11.42#ibcon#read 5, iclass 17, count 0 2006.238.07:31:11.42#ibcon#about to read 6, iclass 17, count 0 2006.238.07:31:11.42#ibcon#read 6, iclass 17, count 0 2006.238.07:31:11.42#ibcon#end of sib2, iclass 17, count 0 2006.238.07:31:11.42#ibcon#*after write, iclass 17, count 0 2006.238.07:31:11.42#ibcon#*before return 0, iclass 17, count 0 2006.238.07:31:11.42#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:31:11.42#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:31:11.42#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:31:11.42#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:31:11.42$vc4f8/vblo=6,752.99 2006.238.07:31:11.42#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.07:31:11.42#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.07:31:11.42#ibcon#ireg 17 cls_cnt 0 2006.238.07:31:11.42#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:31:11.42#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:31:11.42#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:31:11.42#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:31:11.42#ibcon#first serial, iclass 19, count 0 2006.238.07:31:11.42#ibcon#enter sib2, iclass 19, count 0 2006.238.07:31:11.42#ibcon#flushed, iclass 19, count 0 2006.238.07:31:11.42#ibcon#about to write, iclass 19, count 0 2006.238.07:31:11.42#ibcon#wrote, iclass 19, count 0 2006.238.07:31:11.42#ibcon#about to read 3, iclass 19, count 0 2006.238.07:31:11.44#ibcon#read 3, iclass 19, count 0 2006.238.07:31:11.44#ibcon#about to read 4, iclass 19, count 0 2006.238.07:31:11.44#ibcon#read 4, iclass 19, count 0 2006.238.07:31:11.44#ibcon#about to read 5, iclass 19, count 0 2006.238.07:31:11.44#ibcon#read 5, iclass 19, count 0 2006.238.07:31:11.44#ibcon#about to read 6, iclass 19, count 0 2006.238.07:31:11.44#ibcon#read 6, iclass 19, count 0 2006.238.07:31:11.44#ibcon#end of sib2, iclass 19, count 0 2006.238.07:31:11.44#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:31:11.44#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:31:11.44#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:31:11.44#ibcon#*before write, iclass 19, count 0 2006.238.07:31:11.44#ibcon#enter sib2, iclass 19, count 0 2006.238.07:31:11.44#ibcon#flushed, iclass 19, count 0 2006.238.07:31:11.44#ibcon#about to write, iclass 19, count 0 2006.238.07:31:11.44#ibcon#wrote, iclass 19, count 0 2006.238.07:31:11.44#ibcon#about to read 3, iclass 19, count 0 2006.238.07:31:11.48#ibcon#read 3, iclass 19, count 0 2006.238.07:31:11.48#ibcon#about to read 4, iclass 19, count 0 2006.238.07:31:11.48#ibcon#read 4, iclass 19, count 0 2006.238.07:31:11.48#ibcon#about to read 5, iclass 19, count 0 2006.238.07:31:11.48#ibcon#read 5, iclass 19, count 0 2006.238.07:31:11.48#ibcon#about to read 6, iclass 19, count 0 2006.238.07:31:11.48#ibcon#read 6, iclass 19, count 0 2006.238.07:31:11.48#ibcon#end of sib2, iclass 19, count 0 2006.238.07:31:11.48#ibcon#*after write, iclass 19, count 0 2006.238.07:31:11.48#ibcon#*before return 0, iclass 19, count 0 2006.238.07:31:11.48#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:31:11.48#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:31:11.48#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:31:11.48#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:31:11.48$vc4f8/vb=6,4 2006.238.07:31:11.48#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.07:31:11.48#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.07:31:11.48#ibcon#ireg 11 cls_cnt 2 2006.238.07:31:11.48#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:31:11.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:31:11.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:31:11.54#ibcon#enter wrdev, iclass 21, count 2 2006.238.07:31:11.54#ibcon#first serial, iclass 21, count 2 2006.238.07:31:11.54#ibcon#enter sib2, iclass 21, count 2 2006.238.07:31:11.54#ibcon#flushed, iclass 21, count 2 2006.238.07:31:11.54#ibcon#about to write, iclass 21, count 2 2006.238.07:31:11.54#ibcon#wrote, iclass 21, count 2 2006.238.07:31:11.54#ibcon#about to read 3, iclass 21, count 2 2006.238.07:31:11.56#ibcon#read 3, iclass 21, count 2 2006.238.07:31:11.56#ibcon#about to read 4, iclass 21, count 2 2006.238.07:31:11.56#ibcon#read 4, iclass 21, count 2 2006.238.07:31:11.56#ibcon#about to read 5, iclass 21, count 2 2006.238.07:31:11.56#ibcon#read 5, iclass 21, count 2 2006.238.07:31:11.56#ibcon#about to read 6, iclass 21, count 2 2006.238.07:31:11.56#ibcon#read 6, iclass 21, count 2 2006.238.07:31:11.56#ibcon#end of sib2, iclass 21, count 2 2006.238.07:31:11.56#ibcon#*mode == 0, iclass 21, count 2 2006.238.07:31:11.56#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.07:31:11.56#ibcon#[27=AT06-04\r\n] 2006.238.07:31:11.56#ibcon#*before write, iclass 21, count 2 2006.238.07:31:11.56#ibcon#enter sib2, iclass 21, count 2 2006.238.07:31:11.56#ibcon#flushed, iclass 21, count 2 2006.238.07:31:11.56#ibcon#about to write, iclass 21, count 2 2006.238.07:31:11.56#ibcon#wrote, iclass 21, count 2 2006.238.07:31:11.56#ibcon#about to read 3, iclass 21, count 2 2006.238.07:31:11.59#ibcon#read 3, iclass 21, count 2 2006.238.07:31:11.59#ibcon#about to read 4, iclass 21, count 2 2006.238.07:31:11.59#ibcon#read 4, iclass 21, count 2 2006.238.07:31:11.59#ibcon#about to read 5, iclass 21, count 2 2006.238.07:31:11.59#ibcon#read 5, iclass 21, count 2 2006.238.07:31:11.59#ibcon#about to read 6, iclass 21, count 2 2006.238.07:31:11.59#ibcon#read 6, iclass 21, count 2 2006.238.07:31:11.59#ibcon#end of sib2, iclass 21, count 2 2006.238.07:31:11.59#ibcon#*after write, iclass 21, count 2 2006.238.07:31:11.59#ibcon#*before return 0, iclass 21, count 2 2006.238.07:31:11.59#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:31:11.59#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:31:11.59#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.07:31:11.59#ibcon#ireg 7 cls_cnt 0 2006.238.07:31:11.59#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:31:11.71#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:31:11.71#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:31:11.71#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:31:11.71#ibcon#first serial, iclass 21, count 0 2006.238.07:31:11.71#ibcon#enter sib2, iclass 21, count 0 2006.238.07:31:11.71#ibcon#flushed, iclass 21, count 0 2006.238.07:31:11.71#ibcon#about to write, iclass 21, count 0 2006.238.07:31:11.71#ibcon#wrote, iclass 21, count 0 2006.238.07:31:11.71#ibcon#about to read 3, iclass 21, count 0 2006.238.07:31:11.73#ibcon#read 3, iclass 21, count 0 2006.238.07:31:11.73#ibcon#about to read 4, iclass 21, count 0 2006.238.07:31:11.73#ibcon#read 4, iclass 21, count 0 2006.238.07:31:11.73#ibcon#about to read 5, iclass 21, count 0 2006.238.07:31:11.73#ibcon#read 5, iclass 21, count 0 2006.238.07:31:11.73#ibcon#about to read 6, iclass 21, count 0 2006.238.07:31:11.73#ibcon#read 6, iclass 21, count 0 2006.238.07:31:11.73#ibcon#end of sib2, iclass 21, count 0 2006.238.07:31:11.73#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:31:11.73#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:31:11.73#ibcon#[27=USB\r\n] 2006.238.07:31:11.73#ibcon#*before write, iclass 21, count 0 2006.238.07:31:11.73#ibcon#enter sib2, iclass 21, count 0 2006.238.07:31:11.73#ibcon#flushed, iclass 21, count 0 2006.238.07:31:11.73#ibcon#about to write, iclass 21, count 0 2006.238.07:31:11.73#ibcon#wrote, iclass 21, count 0 2006.238.07:31:11.73#ibcon#about to read 3, iclass 21, count 0 2006.238.07:31:11.76#ibcon#read 3, iclass 21, count 0 2006.238.07:31:11.76#ibcon#about to read 4, iclass 21, count 0 2006.238.07:31:11.76#ibcon#read 4, iclass 21, count 0 2006.238.07:31:11.76#ibcon#about to read 5, iclass 21, count 0 2006.238.07:31:11.76#ibcon#read 5, iclass 21, count 0 2006.238.07:31:11.76#ibcon#about to read 6, iclass 21, count 0 2006.238.07:31:11.76#ibcon#read 6, iclass 21, count 0 2006.238.07:31:11.76#ibcon#end of sib2, iclass 21, count 0 2006.238.07:31:11.76#ibcon#*after write, iclass 21, count 0 2006.238.07:31:11.76#ibcon#*before return 0, iclass 21, count 0 2006.238.07:31:11.76#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:31:11.76#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:31:11.76#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:31:11.76#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:31:11.76$vc4f8/vabw=wide 2006.238.07:31:11.76#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:31:11.76#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:31:11.76#ibcon#ireg 8 cls_cnt 0 2006.238.07:31:11.76#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:31:11.76#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:31:11.76#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:31:11.76#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:31:11.76#ibcon#first serial, iclass 23, count 0 2006.238.07:31:11.76#ibcon#enter sib2, iclass 23, count 0 2006.238.07:31:11.76#ibcon#flushed, iclass 23, count 0 2006.238.07:31:11.76#ibcon#about to write, iclass 23, count 0 2006.238.07:31:11.76#ibcon#wrote, iclass 23, count 0 2006.238.07:31:11.76#ibcon#about to read 3, iclass 23, count 0 2006.238.07:31:11.78#ibcon#read 3, iclass 23, count 0 2006.238.07:31:11.78#ibcon#about to read 4, iclass 23, count 0 2006.238.07:31:11.78#ibcon#read 4, iclass 23, count 0 2006.238.07:31:11.78#ibcon#about to read 5, iclass 23, count 0 2006.238.07:31:11.78#ibcon#read 5, iclass 23, count 0 2006.238.07:31:11.78#ibcon#about to read 6, iclass 23, count 0 2006.238.07:31:11.78#ibcon#read 6, iclass 23, count 0 2006.238.07:31:11.78#ibcon#end of sib2, iclass 23, count 0 2006.238.07:31:11.78#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:31:11.78#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:31:11.78#ibcon#[25=BW32\r\n] 2006.238.07:31:11.78#ibcon#*before write, iclass 23, count 0 2006.238.07:31:11.78#ibcon#enter sib2, iclass 23, count 0 2006.238.07:31:11.78#ibcon#flushed, iclass 23, count 0 2006.238.07:31:11.78#ibcon#about to write, iclass 23, count 0 2006.238.07:31:11.78#ibcon#wrote, iclass 23, count 0 2006.238.07:31:11.78#ibcon#about to read 3, iclass 23, count 0 2006.238.07:31:11.81#ibcon#read 3, iclass 23, count 0 2006.238.07:31:11.81#ibcon#about to read 4, iclass 23, count 0 2006.238.07:31:11.81#ibcon#read 4, iclass 23, count 0 2006.238.07:31:11.81#ibcon#about to read 5, iclass 23, count 0 2006.238.07:31:11.81#ibcon#read 5, iclass 23, count 0 2006.238.07:31:11.81#ibcon#about to read 6, iclass 23, count 0 2006.238.07:31:11.81#ibcon#read 6, iclass 23, count 0 2006.238.07:31:11.81#ibcon#end of sib2, iclass 23, count 0 2006.238.07:31:11.81#ibcon#*after write, iclass 23, count 0 2006.238.07:31:11.81#ibcon#*before return 0, iclass 23, count 0 2006.238.07:31:11.81#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:31:11.81#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:31:11.81#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:31:11.81#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:31:11.81$vc4f8/vbbw=wide 2006.238.07:31:11.81#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.07:31:11.81#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.07:31:11.81#ibcon#ireg 8 cls_cnt 0 2006.238.07:31:11.81#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:31:11.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:31:11.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:31:11.88#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:31:11.88#ibcon#first serial, iclass 25, count 0 2006.238.07:31:11.88#ibcon#enter sib2, iclass 25, count 0 2006.238.07:31:11.88#ibcon#flushed, iclass 25, count 0 2006.238.07:31:11.88#ibcon#about to write, iclass 25, count 0 2006.238.07:31:11.88#ibcon#wrote, iclass 25, count 0 2006.238.07:31:11.88#ibcon#about to read 3, iclass 25, count 0 2006.238.07:31:11.90#ibcon#read 3, iclass 25, count 0 2006.238.07:31:11.90#ibcon#about to read 4, iclass 25, count 0 2006.238.07:31:11.90#ibcon#read 4, iclass 25, count 0 2006.238.07:31:11.90#ibcon#about to read 5, iclass 25, count 0 2006.238.07:31:11.90#ibcon#read 5, iclass 25, count 0 2006.238.07:31:11.90#ibcon#about to read 6, iclass 25, count 0 2006.238.07:31:11.90#ibcon#read 6, iclass 25, count 0 2006.238.07:31:11.90#ibcon#end of sib2, iclass 25, count 0 2006.238.07:31:11.90#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:31:11.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:31:11.90#ibcon#[27=BW32\r\n] 2006.238.07:31:11.90#ibcon#*before write, iclass 25, count 0 2006.238.07:31:11.90#ibcon#enter sib2, iclass 25, count 0 2006.238.07:31:11.90#ibcon#flushed, iclass 25, count 0 2006.238.07:31:11.90#ibcon#about to write, iclass 25, count 0 2006.238.07:31:11.90#ibcon#wrote, iclass 25, count 0 2006.238.07:31:11.90#ibcon#about to read 3, iclass 25, count 0 2006.238.07:31:11.93#ibcon#read 3, iclass 25, count 0 2006.238.07:31:11.93#ibcon#about to read 4, iclass 25, count 0 2006.238.07:31:11.93#ibcon#read 4, iclass 25, count 0 2006.238.07:31:11.93#ibcon#about to read 5, iclass 25, count 0 2006.238.07:31:11.93#ibcon#read 5, iclass 25, count 0 2006.238.07:31:11.93#ibcon#about to read 6, iclass 25, count 0 2006.238.07:31:11.93#ibcon#read 6, iclass 25, count 0 2006.238.07:31:11.93#ibcon#end of sib2, iclass 25, count 0 2006.238.07:31:11.93#ibcon#*after write, iclass 25, count 0 2006.238.07:31:11.93#ibcon#*before return 0, iclass 25, count 0 2006.238.07:31:11.93#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:31:11.93#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:31:11.93#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:31:11.93#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:31:11.93$4f8m12a/ifd4f 2006.238.07:31:11.93$ifd4f/lo= 2006.238.07:31:11.93$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:31:11.93$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:31:11.93$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:31:11.93$ifd4f/patch= 2006.238.07:31:11.93$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:31:11.93$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:31:11.93$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:31:11.93$4f8m12a/"form=m,16.000,1:2 2006.238.07:31:11.93$4f8m12a/"tpicd 2006.238.07:31:11.93$4f8m12a/echo=off 2006.238.07:31:11.93$4f8m12a/xlog=off 2006.238.07:31:11.93:!2006.238.07:33:20 2006.238.07:31:47.14#trakl#Source acquired 2006.238.07:31:48.14#flagr#flagr/antenna,acquired 2006.238.07:33:20.00:preob 2006.238.07:33:20.14/onsource/TRACKING 2006.238.07:33:20.14:!2006.238.07:33:30 2006.238.07:33:30.00:data_valid=on 2006.238.07:33:30.00:midob 2006.238.07:33:30.13/onsource/TRACKING 2006.238.07:33:30.13/wx/25.37,1012.2,90 2006.238.07:33:30.27/cable/+6.4186E-03 2006.238.07:33:31.36/va/01,08,usb,yes,38,40 2006.238.07:33:31.36/va/02,07,usb,yes,38,40 2006.238.07:33:31.36/va/03,07,usb,yes,36,36 2006.238.07:33:31.36/va/04,07,usb,yes,39,43 2006.238.07:33:31.36/va/05,08,usb,yes,37,39 2006.238.07:33:31.36/va/06,07,usb,yes,40,40 2006.238.07:33:31.36/va/07,07,usb,yes,40,39 2006.238.07:33:31.36/va/08,07,usb,yes,43,42 2006.238.07:33:31.59/valo/01,532.99,yes,locked 2006.238.07:33:31.59/valo/02,572.99,yes,locked 2006.238.07:33:31.59/valo/03,672.99,yes,locked 2006.238.07:33:31.59/valo/04,832.99,yes,locked 2006.238.07:33:31.59/valo/05,652.99,yes,locked 2006.238.07:33:31.59/valo/06,772.99,yes,locked 2006.238.07:33:31.59/valo/07,832.99,yes,locked 2006.238.07:33:31.59/valo/08,852.99,yes,locked 2006.238.07:33:32.68/vb/01,04,usb,yes,34,32 2006.238.07:33:32.68/vb/02,04,usb,yes,36,37 2006.238.07:33:32.68/vb/03,04,usb,yes,32,36 2006.238.07:33:32.68/vb/04,04,usb,yes,33,33 2006.238.07:33:32.68/vb/05,04,usb,yes,31,35 2006.238.07:33:32.68/vb/06,04,usb,yes,32,35 2006.238.07:33:32.68/vb/07,04,usb,yes,35,34 2006.238.07:33:32.68/vb/08,04,usb,yes,32,35 2006.238.07:33:32.92/vblo/01,632.99,yes,locked 2006.238.07:33:32.92/vblo/02,640.99,yes,locked 2006.238.07:33:32.92/vblo/03,656.99,yes,locked 2006.238.07:33:32.92/vblo/04,712.99,yes,locked 2006.238.07:33:32.92/vblo/05,744.99,yes,locked 2006.238.07:33:32.92/vblo/06,752.99,yes,locked 2006.238.07:33:32.92/vblo/07,734.99,yes,locked 2006.238.07:33:32.92/vblo/08,744.99,yes,locked 2006.238.07:33:33.07/vabw/8 2006.238.07:33:33.22/vbbw/8 2006.238.07:33:33.43/xfe/off,on,13.0 2006.238.07:33:33.81/ifatt/23,28,28,28 2006.238.07:33:34.08/fmout-gps/S +4.36E-07 2006.238.07:33:34.12:!2006.238.07:34:30 2006.238.07:34:30.00:data_valid=off 2006.238.07:34:30.00:postob 2006.238.07:34:30.10/cable/+6.4200E-03 2006.238.07:34:30.10/wx/25.36,1012.2,89 2006.238.07:34:31.07/fmout-gps/S +4.35E-07 2006.238.07:34:31.07:scan_name=238-0735,k06238,60 2006.238.07:34:31.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.238.07:34:31.13#flagr#flagr/antenna,new-source 2006.238.07:34:32.13:checkk5 2006.238.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:34:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:34:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:34:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:34:34.02/chk_obsdata//k5ts1/T2380733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:34:34.39/chk_obsdata//k5ts2/T2380733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:34:34.76/chk_obsdata//k5ts3/T2380733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:34:35.14/chk_obsdata//k5ts4/T2380733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:34:35.82/k5log//k5ts1_log_newline 2006.238.07:34:36.51/k5log//k5ts2_log_newline 2006.238.07:34:37.20/k5log//k5ts3_log_newline 2006.238.07:34:37.90/k5log//k5ts4_log_newline 2006.238.07:34:37.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:34:37.92:4f8m12a=1 2006.238.07:34:37.92$4f8m12a/echo=on 2006.238.07:34:37.92$4f8m12a/pcalon 2006.238.07:34:37.92$pcalon/"no phase cal control is implemented here 2006.238.07:34:37.92$4f8m12a/"tpicd=stop 2006.238.07:34:37.92$4f8m12a/vc4f8 2006.238.07:34:37.92$vc4f8/valo=1,532.99 2006.238.07:34:37.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.07:34:37.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.07:34:37.92#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:37.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:34:37.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:34:37.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:34:37.92#ibcon#enter wrdev, iclass 36, count 0 2006.238.07:34:37.92#ibcon#first serial, iclass 36, count 0 2006.238.07:34:37.92#ibcon#enter sib2, iclass 36, count 0 2006.238.07:34:37.92#ibcon#flushed, iclass 36, count 0 2006.238.07:34:37.92#ibcon#about to write, iclass 36, count 0 2006.238.07:34:37.92#ibcon#wrote, iclass 36, count 0 2006.238.07:34:37.92#ibcon#about to read 3, iclass 36, count 0 2006.238.07:34:37.94#ibcon#read 3, iclass 36, count 0 2006.238.07:34:37.94#ibcon#about to read 4, iclass 36, count 0 2006.238.07:34:37.94#ibcon#read 4, iclass 36, count 0 2006.238.07:34:37.94#ibcon#about to read 5, iclass 36, count 0 2006.238.07:34:37.94#ibcon#read 5, iclass 36, count 0 2006.238.07:34:37.94#ibcon#about to read 6, iclass 36, count 0 2006.238.07:34:37.94#ibcon#read 6, iclass 36, count 0 2006.238.07:34:37.94#ibcon#end of sib2, iclass 36, count 0 2006.238.07:34:37.94#ibcon#*mode == 0, iclass 36, count 0 2006.238.07:34:37.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.07:34:37.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:34:37.94#ibcon#*before write, iclass 36, count 0 2006.238.07:34:37.94#ibcon#enter sib2, iclass 36, count 0 2006.238.07:34:37.94#ibcon#flushed, iclass 36, count 0 2006.238.07:34:37.94#ibcon#about to write, iclass 36, count 0 2006.238.07:34:37.94#ibcon#wrote, iclass 36, count 0 2006.238.07:34:37.94#ibcon#about to read 3, iclass 36, count 0 2006.238.07:34:37.99#ibcon#read 3, iclass 36, count 0 2006.238.07:34:37.99#ibcon#about to read 4, iclass 36, count 0 2006.238.07:34:37.99#ibcon#read 4, iclass 36, count 0 2006.238.07:34:37.99#ibcon#about to read 5, iclass 36, count 0 2006.238.07:34:37.99#ibcon#read 5, iclass 36, count 0 2006.238.07:34:37.99#ibcon#about to read 6, iclass 36, count 0 2006.238.07:34:37.99#ibcon#read 6, iclass 36, count 0 2006.238.07:34:37.99#ibcon#end of sib2, iclass 36, count 0 2006.238.07:34:37.99#ibcon#*after write, iclass 36, count 0 2006.238.07:34:37.99#ibcon#*before return 0, iclass 36, count 0 2006.238.07:34:37.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:34:37.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:34:37.99#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.07:34:37.99#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.07:34:37.99$vc4f8/va=1,8 2006.238.07:34:37.99#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.238.07:34:37.99#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.238.07:34:37.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:37.99#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:34:37.99#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:34:37.99#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:34:37.99#ibcon#enter wrdev, iclass 38, count 2 2006.238.07:34:37.99#ibcon#first serial, iclass 38, count 2 2006.238.07:34:37.99#ibcon#enter sib2, iclass 38, count 2 2006.238.07:34:37.99#ibcon#flushed, iclass 38, count 2 2006.238.07:34:37.99#ibcon#about to write, iclass 38, count 2 2006.238.07:34:37.99#ibcon#wrote, iclass 38, count 2 2006.238.07:34:37.99#ibcon#about to read 3, iclass 38, count 2 2006.238.07:34:38.01#ibcon#read 3, iclass 38, count 2 2006.238.07:34:38.01#ibcon#about to read 4, iclass 38, count 2 2006.238.07:34:38.01#ibcon#read 4, iclass 38, count 2 2006.238.07:34:38.01#ibcon#about to read 5, iclass 38, count 2 2006.238.07:34:38.01#ibcon#read 5, iclass 38, count 2 2006.238.07:34:38.01#ibcon#about to read 6, iclass 38, count 2 2006.238.07:34:38.01#ibcon#read 6, iclass 38, count 2 2006.238.07:34:38.01#ibcon#end of sib2, iclass 38, count 2 2006.238.07:34:38.01#ibcon#*mode == 0, iclass 38, count 2 2006.238.07:34:38.01#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.238.07:34:38.01#ibcon#[25=AT01-08\r\n] 2006.238.07:34:38.01#ibcon#*before write, iclass 38, count 2 2006.238.07:34:38.01#ibcon#enter sib2, iclass 38, count 2 2006.238.07:34:38.01#ibcon#flushed, iclass 38, count 2 2006.238.07:34:38.01#ibcon#about to write, iclass 38, count 2 2006.238.07:34:38.01#ibcon#wrote, iclass 38, count 2 2006.238.07:34:38.01#ibcon#about to read 3, iclass 38, count 2 2006.238.07:34:38.04#ibcon#read 3, iclass 38, count 2 2006.238.07:34:38.04#ibcon#about to read 4, iclass 38, count 2 2006.238.07:34:38.04#ibcon#read 4, iclass 38, count 2 2006.238.07:34:38.04#ibcon#about to read 5, iclass 38, count 2 2006.238.07:34:38.04#ibcon#read 5, iclass 38, count 2 2006.238.07:34:38.04#ibcon#about to read 6, iclass 38, count 2 2006.238.07:34:38.04#ibcon#read 6, iclass 38, count 2 2006.238.07:34:38.04#ibcon#end of sib2, iclass 38, count 2 2006.238.07:34:38.04#ibcon#*after write, iclass 38, count 2 2006.238.07:34:38.04#ibcon#*before return 0, iclass 38, count 2 2006.238.07:34:38.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:34:38.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:34:38.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.238.07:34:38.04#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:38.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:34:38.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:34:38.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:34:38.16#ibcon#enter wrdev, iclass 38, count 0 2006.238.07:34:38.16#ibcon#first serial, iclass 38, count 0 2006.238.07:34:38.16#ibcon#enter sib2, iclass 38, count 0 2006.238.07:34:38.16#ibcon#flushed, iclass 38, count 0 2006.238.07:34:38.16#ibcon#about to write, iclass 38, count 0 2006.238.07:34:38.16#ibcon#wrote, iclass 38, count 0 2006.238.07:34:38.16#ibcon#about to read 3, iclass 38, count 0 2006.238.07:34:38.18#ibcon#read 3, iclass 38, count 0 2006.238.07:34:38.18#ibcon#about to read 4, iclass 38, count 0 2006.238.07:34:38.18#ibcon#read 4, iclass 38, count 0 2006.238.07:34:38.18#ibcon#about to read 5, iclass 38, count 0 2006.238.07:34:38.18#ibcon#read 5, iclass 38, count 0 2006.238.07:34:38.18#ibcon#about to read 6, iclass 38, count 0 2006.238.07:34:38.18#ibcon#read 6, iclass 38, count 0 2006.238.07:34:38.18#ibcon#end of sib2, iclass 38, count 0 2006.238.07:34:38.18#ibcon#*mode == 0, iclass 38, count 0 2006.238.07:34:38.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.07:34:38.18#ibcon#[25=USB\r\n] 2006.238.07:34:38.18#ibcon#*before write, iclass 38, count 0 2006.238.07:34:38.18#ibcon#enter sib2, iclass 38, count 0 2006.238.07:34:38.18#ibcon#flushed, iclass 38, count 0 2006.238.07:34:38.18#ibcon#about to write, iclass 38, count 0 2006.238.07:34:38.18#ibcon#wrote, iclass 38, count 0 2006.238.07:34:38.18#ibcon#about to read 3, iclass 38, count 0 2006.238.07:34:38.21#ibcon#read 3, iclass 38, count 0 2006.238.07:34:38.21#ibcon#about to read 4, iclass 38, count 0 2006.238.07:34:38.21#ibcon#read 4, iclass 38, count 0 2006.238.07:34:38.21#ibcon#about to read 5, iclass 38, count 0 2006.238.07:34:38.21#ibcon#read 5, iclass 38, count 0 2006.238.07:34:38.21#ibcon#about to read 6, iclass 38, count 0 2006.238.07:34:38.21#ibcon#read 6, iclass 38, count 0 2006.238.07:34:38.21#ibcon#end of sib2, iclass 38, count 0 2006.238.07:34:38.21#ibcon#*after write, iclass 38, count 0 2006.238.07:34:38.21#ibcon#*before return 0, iclass 38, count 0 2006.238.07:34:38.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:34:38.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:34:38.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.07:34:38.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.07:34:38.21$vc4f8/valo=2,572.99 2006.238.07:34:38.21#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.07:34:38.21#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.07:34:38.21#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:38.21#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:34:38.21#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:34:38.21#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:34:38.21#ibcon#enter wrdev, iclass 40, count 0 2006.238.07:34:38.21#ibcon#first serial, iclass 40, count 0 2006.238.07:34:38.21#ibcon#enter sib2, iclass 40, count 0 2006.238.07:34:38.21#ibcon#flushed, iclass 40, count 0 2006.238.07:34:38.21#ibcon#about to write, iclass 40, count 0 2006.238.07:34:38.21#ibcon#wrote, iclass 40, count 0 2006.238.07:34:38.21#ibcon#about to read 3, iclass 40, count 0 2006.238.07:34:38.23#ibcon#read 3, iclass 40, count 0 2006.238.07:34:38.23#ibcon#about to read 4, iclass 40, count 0 2006.238.07:34:38.23#ibcon#read 4, iclass 40, count 0 2006.238.07:34:38.23#ibcon#about to read 5, iclass 40, count 0 2006.238.07:34:38.23#ibcon#read 5, iclass 40, count 0 2006.238.07:34:38.23#ibcon#about to read 6, iclass 40, count 0 2006.238.07:34:38.23#ibcon#read 6, iclass 40, count 0 2006.238.07:34:38.23#ibcon#end of sib2, iclass 40, count 0 2006.238.07:34:38.23#ibcon#*mode == 0, iclass 40, count 0 2006.238.07:34:38.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.07:34:38.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:34:38.23#ibcon#*before write, iclass 40, count 0 2006.238.07:34:38.23#ibcon#enter sib2, iclass 40, count 0 2006.238.07:34:38.23#ibcon#flushed, iclass 40, count 0 2006.238.07:34:38.23#ibcon#about to write, iclass 40, count 0 2006.238.07:34:38.23#ibcon#wrote, iclass 40, count 0 2006.238.07:34:38.23#ibcon#about to read 3, iclass 40, count 0 2006.238.07:34:38.27#ibcon#read 3, iclass 40, count 0 2006.238.07:34:38.27#ibcon#about to read 4, iclass 40, count 0 2006.238.07:34:38.27#ibcon#read 4, iclass 40, count 0 2006.238.07:34:38.27#ibcon#about to read 5, iclass 40, count 0 2006.238.07:34:38.27#ibcon#read 5, iclass 40, count 0 2006.238.07:34:38.27#ibcon#about to read 6, iclass 40, count 0 2006.238.07:34:38.27#ibcon#read 6, iclass 40, count 0 2006.238.07:34:38.27#ibcon#end of sib2, iclass 40, count 0 2006.238.07:34:38.27#ibcon#*after write, iclass 40, count 0 2006.238.07:34:38.27#ibcon#*before return 0, iclass 40, count 0 2006.238.07:34:38.27#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:34:38.27#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:34:38.27#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.07:34:38.27#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.07:34:38.27$vc4f8/va=2,7 2006.238.07:34:38.27#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.238.07:34:38.27#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.238.07:34:38.27#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:38.27#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:34:38.33#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:34:38.33#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:34:38.33#ibcon#enter wrdev, iclass 4, count 2 2006.238.07:34:38.33#ibcon#first serial, iclass 4, count 2 2006.238.07:34:38.33#ibcon#enter sib2, iclass 4, count 2 2006.238.07:34:38.33#ibcon#flushed, iclass 4, count 2 2006.238.07:34:38.33#ibcon#about to write, iclass 4, count 2 2006.238.07:34:38.33#ibcon#wrote, iclass 4, count 2 2006.238.07:34:38.33#ibcon#about to read 3, iclass 4, count 2 2006.238.07:34:38.35#ibcon#read 3, iclass 4, count 2 2006.238.07:34:38.35#ibcon#about to read 4, iclass 4, count 2 2006.238.07:34:38.35#ibcon#read 4, iclass 4, count 2 2006.238.07:34:38.35#ibcon#about to read 5, iclass 4, count 2 2006.238.07:34:38.35#ibcon#read 5, iclass 4, count 2 2006.238.07:34:38.35#ibcon#about to read 6, iclass 4, count 2 2006.238.07:34:38.35#ibcon#read 6, iclass 4, count 2 2006.238.07:34:38.35#ibcon#end of sib2, iclass 4, count 2 2006.238.07:34:38.35#ibcon#*mode == 0, iclass 4, count 2 2006.238.07:34:38.35#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.238.07:34:38.35#ibcon#[25=AT02-07\r\n] 2006.238.07:34:38.35#ibcon#*before write, iclass 4, count 2 2006.238.07:34:38.35#ibcon#enter sib2, iclass 4, count 2 2006.238.07:34:38.35#ibcon#flushed, iclass 4, count 2 2006.238.07:34:38.35#ibcon#about to write, iclass 4, count 2 2006.238.07:34:38.35#ibcon#wrote, iclass 4, count 2 2006.238.07:34:38.35#ibcon#about to read 3, iclass 4, count 2 2006.238.07:34:38.38#ibcon#read 3, iclass 4, count 2 2006.238.07:34:38.38#ibcon#about to read 4, iclass 4, count 2 2006.238.07:34:38.38#ibcon#read 4, iclass 4, count 2 2006.238.07:34:38.38#ibcon#about to read 5, iclass 4, count 2 2006.238.07:34:38.38#ibcon#read 5, iclass 4, count 2 2006.238.07:34:38.38#ibcon#about to read 6, iclass 4, count 2 2006.238.07:34:38.38#ibcon#read 6, iclass 4, count 2 2006.238.07:34:38.38#ibcon#end of sib2, iclass 4, count 2 2006.238.07:34:38.38#ibcon#*after write, iclass 4, count 2 2006.238.07:34:38.38#ibcon#*before return 0, iclass 4, count 2 2006.238.07:34:38.38#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:34:38.38#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:34:38.38#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.238.07:34:38.38#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:38.38#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:34:38.47#abcon#<5=/04 1.6 2.7 25.36 891012.2\r\n> 2006.238.07:34:38.49#abcon#{5=INTERFACE CLEAR} 2006.238.07:34:38.50#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:34:38.50#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:34:38.50#ibcon#enter wrdev, iclass 4, count 0 2006.238.07:34:38.50#ibcon#first serial, iclass 4, count 0 2006.238.07:34:38.50#ibcon#enter sib2, iclass 4, count 0 2006.238.07:34:38.50#ibcon#flushed, iclass 4, count 0 2006.238.07:34:38.50#ibcon#about to write, iclass 4, count 0 2006.238.07:34:38.50#ibcon#wrote, iclass 4, count 0 2006.238.07:34:38.50#ibcon#about to read 3, iclass 4, count 0 2006.238.07:34:38.52#ibcon#read 3, iclass 4, count 0 2006.238.07:34:38.52#ibcon#about to read 4, iclass 4, count 0 2006.238.07:34:38.52#ibcon#read 4, iclass 4, count 0 2006.238.07:34:38.52#ibcon#about to read 5, iclass 4, count 0 2006.238.07:34:38.52#ibcon#read 5, iclass 4, count 0 2006.238.07:34:38.52#ibcon#about to read 6, iclass 4, count 0 2006.238.07:34:38.52#ibcon#read 6, iclass 4, count 0 2006.238.07:34:38.52#ibcon#end of sib2, iclass 4, count 0 2006.238.07:34:38.52#ibcon#*mode == 0, iclass 4, count 0 2006.238.07:34:38.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.07:34:38.52#ibcon#[25=USB\r\n] 2006.238.07:34:38.52#ibcon#*before write, iclass 4, count 0 2006.238.07:34:38.52#ibcon#enter sib2, iclass 4, count 0 2006.238.07:34:38.52#ibcon#flushed, iclass 4, count 0 2006.238.07:34:38.52#ibcon#about to write, iclass 4, count 0 2006.238.07:34:38.52#ibcon#wrote, iclass 4, count 0 2006.238.07:34:38.52#ibcon#about to read 3, iclass 4, count 0 2006.238.07:34:38.55#ibcon#read 3, iclass 4, count 0 2006.238.07:34:38.55#ibcon#about to read 4, iclass 4, count 0 2006.238.07:34:38.55#ibcon#read 4, iclass 4, count 0 2006.238.07:34:38.55#ibcon#about to read 5, iclass 4, count 0 2006.238.07:34:38.55#ibcon#read 5, iclass 4, count 0 2006.238.07:34:38.55#ibcon#about to read 6, iclass 4, count 0 2006.238.07:34:38.55#ibcon#read 6, iclass 4, count 0 2006.238.07:34:38.55#ibcon#end of sib2, iclass 4, count 0 2006.238.07:34:38.55#ibcon#*after write, iclass 4, count 0 2006.238.07:34:38.55#ibcon#*before return 0, iclass 4, count 0 2006.238.07:34:38.55#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:34:38.55#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:34:38.55#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.07:34:38.55#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.07:34:38.55$vc4f8/valo=3,672.99 2006.238.07:34:38.55#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.238.07:34:38.55#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.238.07:34:38.55#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:38.55#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:34:38.55#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:34:38.55#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:34:38.55#ibcon#enter wrdev, iclass 12, count 0 2006.238.07:34:38.55#ibcon#first serial, iclass 12, count 0 2006.238.07:34:38.55#ibcon#enter sib2, iclass 12, count 0 2006.238.07:34:38.55#ibcon#flushed, iclass 12, count 0 2006.238.07:34:38.55#ibcon#about to write, iclass 12, count 0 2006.238.07:34:38.55#ibcon#wrote, iclass 12, count 0 2006.238.07:34:38.55#ibcon#about to read 3, iclass 12, count 0 2006.238.07:34:38.57#abcon#[5=S1D000X0/0*\r\n] 2006.238.07:34:38.57#ibcon#read 3, iclass 12, count 0 2006.238.07:34:38.57#ibcon#about to read 4, iclass 12, count 0 2006.238.07:34:38.57#ibcon#read 4, iclass 12, count 0 2006.238.07:34:38.57#ibcon#about to read 5, iclass 12, count 0 2006.238.07:34:38.57#ibcon#read 5, iclass 12, count 0 2006.238.07:34:38.57#ibcon#about to read 6, iclass 12, count 0 2006.238.07:34:38.57#ibcon#read 6, iclass 12, count 0 2006.238.07:34:38.57#ibcon#end of sib2, iclass 12, count 0 2006.238.07:34:38.57#ibcon#*mode == 0, iclass 12, count 0 2006.238.07:34:38.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.07:34:38.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:34:38.57#ibcon#*before write, iclass 12, count 0 2006.238.07:34:38.57#ibcon#enter sib2, iclass 12, count 0 2006.238.07:34:38.57#ibcon#flushed, iclass 12, count 0 2006.238.07:34:38.57#ibcon#about to write, iclass 12, count 0 2006.238.07:34:38.57#ibcon#wrote, iclass 12, count 0 2006.238.07:34:38.57#ibcon#about to read 3, iclass 12, count 0 2006.238.07:34:38.61#ibcon#read 3, iclass 12, count 0 2006.238.07:34:38.61#ibcon#about to read 4, iclass 12, count 0 2006.238.07:34:38.61#ibcon#read 4, iclass 12, count 0 2006.238.07:34:38.61#ibcon#about to read 5, iclass 12, count 0 2006.238.07:34:38.61#ibcon#read 5, iclass 12, count 0 2006.238.07:34:38.61#ibcon#about to read 6, iclass 12, count 0 2006.238.07:34:38.61#ibcon#read 6, iclass 12, count 0 2006.238.07:34:38.61#ibcon#end of sib2, iclass 12, count 0 2006.238.07:34:38.61#ibcon#*after write, iclass 12, count 0 2006.238.07:34:38.61#ibcon#*before return 0, iclass 12, count 0 2006.238.07:34:38.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:34:38.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:34:38.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.07:34:38.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.07:34:38.61$vc4f8/va=3,7 2006.238.07:34:38.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.238.07:34:38.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.238.07:34:38.61#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:38.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:34:38.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:34:38.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:34:38.67#ibcon#enter wrdev, iclass 14, count 2 2006.238.07:34:38.67#ibcon#first serial, iclass 14, count 2 2006.238.07:34:38.67#ibcon#enter sib2, iclass 14, count 2 2006.238.07:34:38.67#ibcon#flushed, iclass 14, count 2 2006.238.07:34:38.67#ibcon#about to write, iclass 14, count 2 2006.238.07:34:38.67#ibcon#wrote, iclass 14, count 2 2006.238.07:34:38.67#ibcon#about to read 3, iclass 14, count 2 2006.238.07:34:38.69#ibcon#read 3, iclass 14, count 2 2006.238.07:34:38.69#ibcon#about to read 4, iclass 14, count 2 2006.238.07:34:38.69#ibcon#read 4, iclass 14, count 2 2006.238.07:34:38.69#ibcon#about to read 5, iclass 14, count 2 2006.238.07:34:38.69#ibcon#read 5, iclass 14, count 2 2006.238.07:34:38.69#ibcon#about to read 6, iclass 14, count 2 2006.238.07:34:38.69#ibcon#read 6, iclass 14, count 2 2006.238.07:34:38.69#ibcon#end of sib2, iclass 14, count 2 2006.238.07:34:38.69#ibcon#*mode == 0, iclass 14, count 2 2006.238.07:34:38.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.238.07:34:38.69#ibcon#[25=AT03-07\r\n] 2006.238.07:34:38.69#ibcon#*before write, iclass 14, count 2 2006.238.07:34:38.69#ibcon#enter sib2, iclass 14, count 2 2006.238.07:34:38.69#ibcon#flushed, iclass 14, count 2 2006.238.07:34:38.69#ibcon#about to write, iclass 14, count 2 2006.238.07:34:38.69#ibcon#wrote, iclass 14, count 2 2006.238.07:34:38.69#ibcon#about to read 3, iclass 14, count 2 2006.238.07:34:38.72#ibcon#read 3, iclass 14, count 2 2006.238.07:34:38.72#ibcon#about to read 4, iclass 14, count 2 2006.238.07:34:38.72#ibcon#read 4, iclass 14, count 2 2006.238.07:34:38.72#ibcon#about to read 5, iclass 14, count 2 2006.238.07:34:38.72#ibcon#read 5, iclass 14, count 2 2006.238.07:34:38.72#ibcon#about to read 6, iclass 14, count 2 2006.238.07:34:38.72#ibcon#read 6, iclass 14, count 2 2006.238.07:34:38.72#ibcon#end of sib2, iclass 14, count 2 2006.238.07:34:38.72#ibcon#*after write, iclass 14, count 2 2006.238.07:34:38.72#ibcon#*before return 0, iclass 14, count 2 2006.238.07:34:38.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:34:38.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:34:38.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.238.07:34:38.72#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:38.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:34:38.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:34:38.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:34:38.84#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:34:38.84#ibcon#first serial, iclass 14, count 0 2006.238.07:34:38.84#ibcon#enter sib2, iclass 14, count 0 2006.238.07:34:38.84#ibcon#flushed, iclass 14, count 0 2006.238.07:34:38.84#ibcon#about to write, iclass 14, count 0 2006.238.07:34:38.84#ibcon#wrote, iclass 14, count 0 2006.238.07:34:38.84#ibcon#about to read 3, iclass 14, count 0 2006.238.07:34:38.86#ibcon#read 3, iclass 14, count 0 2006.238.07:34:38.86#ibcon#about to read 4, iclass 14, count 0 2006.238.07:34:38.86#ibcon#read 4, iclass 14, count 0 2006.238.07:34:38.86#ibcon#about to read 5, iclass 14, count 0 2006.238.07:34:38.86#ibcon#read 5, iclass 14, count 0 2006.238.07:34:38.86#ibcon#about to read 6, iclass 14, count 0 2006.238.07:34:38.86#ibcon#read 6, iclass 14, count 0 2006.238.07:34:38.86#ibcon#end of sib2, iclass 14, count 0 2006.238.07:34:38.86#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:34:38.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:34:38.86#ibcon#[25=USB\r\n] 2006.238.07:34:38.86#ibcon#*before write, iclass 14, count 0 2006.238.07:34:38.86#ibcon#enter sib2, iclass 14, count 0 2006.238.07:34:38.86#ibcon#flushed, iclass 14, count 0 2006.238.07:34:38.86#ibcon#about to write, iclass 14, count 0 2006.238.07:34:38.86#ibcon#wrote, iclass 14, count 0 2006.238.07:34:38.86#ibcon#about to read 3, iclass 14, count 0 2006.238.07:34:38.89#ibcon#read 3, iclass 14, count 0 2006.238.07:34:38.89#ibcon#about to read 4, iclass 14, count 0 2006.238.07:34:38.89#ibcon#read 4, iclass 14, count 0 2006.238.07:34:38.89#ibcon#about to read 5, iclass 14, count 0 2006.238.07:34:38.89#ibcon#read 5, iclass 14, count 0 2006.238.07:34:38.89#ibcon#about to read 6, iclass 14, count 0 2006.238.07:34:38.89#ibcon#read 6, iclass 14, count 0 2006.238.07:34:38.89#ibcon#end of sib2, iclass 14, count 0 2006.238.07:34:38.89#ibcon#*after write, iclass 14, count 0 2006.238.07:34:38.89#ibcon#*before return 0, iclass 14, count 0 2006.238.07:34:38.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:34:38.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:34:38.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:34:38.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:34:38.89$vc4f8/valo=4,832.99 2006.238.07:34:38.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.07:34:38.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.07:34:38.89#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:38.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:34:38.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:34:38.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:34:38.89#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:34:38.89#ibcon#first serial, iclass 16, count 0 2006.238.07:34:38.89#ibcon#enter sib2, iclass 16, count 0 2006.238.07:34:38.89#ibcon#flushed, iclass 16, count 0 2006.238.07:34:38.89#ibcon#about to write, iclass 16, count 0 2006.238.07:34:38.89#ibcon#wrote, iclass 16, count 0 2006.238.07:34:38.89#ibcon#about to read 3, iclass 16, count 0 2006.238.07:34:38.91#ibcon#read 3, iclass 16, count 0 2006.238.07:34:38.91#ibcon#about to read 4, iclass 16, count 0 2006.238.07:34:38.91#ibcon#read 4, iclass 16, count 0 2006.238.07:34:38.91#ibcon#about to read 5, iclass 16, count 0 2006.238.07:34:38.91#ibcon#read 5, iclass 16, count 0 2006.238.07:34:38.91#ibcon#about to read 6, iclass 16, count 0 2006.238.07:34:38.91#ibcon#read 6, iclass 16, count 0 2006.238.07:34:38.91#ibcon#end of sib2, iclass 16, count 0 2006.238.07:34:38.91#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:34:38.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:34:38.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:34:38.91#ibcon#*before write, iclass 16, count 0 2006.238.07:34:38.91#ibcon#enter sib2, iclass 16, count 0 2006.238.07:34:38.91#ibcon#flushed, iclass 16, count 0 2006.238.07:34:38.91#ibcon#about to write, iclass 16, count 0 2006.238.07:34:38.91#ibcon#wrote, iclass 16, count 0 2006.238.07:34:38.91#ibcon#about to read 3, iclass 16, count 0 2006.238.07:34:38.95#ibcon#read 3, iclass 16, count 0 2006.238.07:34:38.95#ibcon#about to read 4, iclass 16, count 0 2006.238.07:34:38.95#ibcon#read 4, iclass 16, count 0 2006.238.07:34:38.95#ibcon#about to read 5, iclass 16, count 0 2006.238.07:34:38.95#ibcon#read 5, iclass 16, count 0 2006.238.07:34:38.95#ibcon#about to read 6, iclass 16, count 0 2006.238.07:34:38.95#ibcon#read 6, iclass 16, count 0 2006.238.07:34:38.95#ibcon#end of sib2, iclass 16, count 0 2006.238.07:34:38.95#ibcon#*after write, iclass 16, count 0 2006.238.07:34:38.95#ibcon#*before return 0, iclass 16, count 0 2006.238.07:34:38.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:34:38.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:34:38.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:34:38.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:34:38.95$vc4f8/va=4,7 2006.238.07:34:38.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.238.07:34:38.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.238.07:34:38.95#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:38.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:34:39.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:34:39.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:34:39.01#ibcon#enter wrdev, iclass 18, count 2 2006.238.07:34:39.01#ibcon#first serial, iclass 18, count 2 2006.238.07:34:39.01#ibcon#enter sib2, iclass 18, count 2 2006.238.07:34:39.01#ibcon#flushed, iclass 18, count 2 2006.238.07:34:39.01#ibcon#about to write, iclass 18, count 2 2006.238.07:34:39.01#ibcon#wrote, iclass 18, count 2 2006.238.07:34:39.01#ibcon#about to read 3, iclass 18, count 2 2006.238.07:34:39.03#ibcon#read 3, iclass 18, count 2 2006.238.07:34:39.03#ibcon#about to read 4, iclass 18, count 2 2006.238.07:34:39.03#ibcon#read 4, iclass 18, count 2 2006.238.07:34:39.03#ibcon#about to read 5, iclass 18, count 2 2006.238.07:34:39.03#ibcon#read 5, iclass 18, count 2 2006.238.07:34:39.03#ibcon#about to read 6, iclass 18, count 2 2006.238.07:34:39.03#ibcon#read 6, iclass 18, count 2 2006.238.07:34:39.03#ibcon#end of sib2, iclass 18, count 2 2006.238.07:34:39.03#ibcon#*mode == 0, iclass 18, count 2 2006.238.07:34:39.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.238.07:34:39.03#ibcon#[25=AT04-07\r\n] 2006.238.07:34:39.03#ibcon#*before write, iclass 18, count 2 2006.238.07:34:39.03#ibcon#enter sib2, iclass 18, count 2 2006.238.07:34:39.03#ibcon#flushed, iclass 18, count 2 2006.238.07:34:39.03#ibcon#about to write, iclass 18, count 2 2006.238.07:34:39.03#ibcon#wrote, iclass 18, count 2 2006.238.07:34:39.03#ibcon#about to read 3, iclass 18, count 2 2006.238.07:34:39.06#ibcon#read 3, iclass 18, count 2 2006.238.07:34:39.06#ibcon#about to read 4, iclass 18, count 2 2006.238.07:34:39.06#ibcon#read 4, iclass 18, count 2 2006.238.07:34:39.06#ibcon#about to read 5, iclass 18, count 2 2006.238.07:34:39.06#ibcon#read 5, iclass 18, count 2 2006.238.07:34:39.06#ibcon#about to read 6, iclass 18, count 2 2006.238.07:34:39.06#ibcon#read 6, iclass 18, count 2 2006.238.07:34:39.06#ibcon#end of sib2, iclass 18, count 2 2006.238.07:34:39.06#ibcon#*after write, iclass 18, count 2 2006.238.07:34:39.06#ibcon#*before return 0, iclass 18, count 2 2006.238.07:34:39.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:34:39.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:34:39.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.238.07:34:39.06#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:39.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:34:39.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:34:39.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:34:39.18#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:34:39.18#ibcon#first serial, iclass 18, count 0 2006.238.07:34:39.18#ibcon#enter sib2, iclass 18, count 0 2006.238.07:34:39.18#ibcon#flushed, iclass 18, count 0 2006.238.07:34:39.18#ibcon#about to write, iclass 18, count 0 2006.238.07:34:39.18#ibcon#wrote, iclass 18, count 0 2006.238.07:34:39.18#ibcon#about to read 3, iclass 18, count 0 2006.238.07:34:39.20#ibcon#read 3, iclass 18, count 0 2006.238.07:34:39.20#ibcon#about to read 4, iclass 18, count 0 2006.238.07:34:39.20#ibcon#read 4, iclass 18, count 0 2006.238.07:34:39.20#ibcon#about to read 5, iclass 18, count 0 2006.238.07:34:39.20#ibcon#read 5, iclass 18, count 0 2006.238.07:34:39.20#ibcon#about to read 6, iclass 18, count 0 2006.238.07:34:39.20#ibcon#read 6, iclass 18, count 0 2006.238.07:34:39.20#ibcon#end of sib2, iclass 18, count 0 2006.238.07:34:39.20#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:34:39.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:34:39.20#ibcon#[25=USB\r\n] 2006.238.07:34:39.20#ibcon#*before write, iclass 18, count 0 2006.238.07:34:39.20#ibcon#enter sib2, iclass 18, count 0 2006.238.07:34:39.20#ibcon#flushed, iclass 18, count 0 2006.238.07:34:39.20#ibcon#about to write, iclass 18, count 0 2006.238.07:34:39.20#ibcon#wrote, iclass 18, count 0 2006.238.07:34:39.20#ibcon#about to read 3, iclass 18, count 0 2006.238.07:34:39.23#ibcon#read 3, iclass 18, count 0 2006.238.07:34:39.23#ibcon#about to read 4, iclass 18, count 0 2006.238.07:34:39.23#ibcon#read 4, iclass 18, count 0 2006.238.07:34:39.23#ibcon#about to read 5, iclass 18, count 0 2006.238.07:34:39.23#ibcon#read 5, iclass 18, count 0 2006.238.07:34:39.23#ibcon#about to read 6, iclass 18, count 0 2006.238.07:34:39.23#ibcon#read 6, iclass 18, count 0 2006.238.07:34:39.23#ibcon#end of sib2, iclass 18, count 0 2006.238.07:34:39.23#ibcon#*after write, iclass 18, count 0 2006.238.07:34:39.23#ibcon#*before return 0, iclass 18, count 0 2006.238.07:34:39.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:34:39.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:34:39.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:34:39.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:34:39.23$vc4f8/valo=5,652.99 2006.238.07:34:39.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.07:34:39.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.07:34:39.23#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:39.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:34:39.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:34:39.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:34:39.23#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:34:39.23#ibcon#first serial, iclass 20, count 0 2006.238.07:34:39.23#ibcon#enter sib2, iclass 20, count 0 2006.238.07:34:39.23#ibcon#flushed, iclass 20, count 0 2006.238.07:34:39.23#ibcon#about to write, iclass 20, count 0 2006.238.07:34:39.23#ibcon#wrote, iclass 20, count 0 2006.238.07:34:39.23#ibcon#about to read 3, iclass 20, count 0 2006.238.07:34:39.25#ibcon#read 3, iclass 20, count 0 2006.238.07:34:39.25#ibcon#about to read 4, iclass 20, count 0 2006.238.07:34:39.25#ibcon#read 4, iclass 20, count 0 2006.238.07:34:39.25#ibcon#about to read 5, iclass 20, count 0 2006.238.07:34:39.25#ibcon#read 5, iclass 20, count 0 2006.238.07:34:39.25#ibcon#about to read 6, iclass 20, count 0 2006.238.07:34:39.25#ibcon#read 6, iclass 20, count 0 2006.238.07:34:39.25#ibcon#end of sib2, iclass 20, count 0 2006.238.07:34:39.25#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:34:39.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:34:39.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:34:39.25#ibcon#*before write, iclass 20, count 0 2006.238.07:34:39.25#ibcon#enter sib2, iclass 20, count 0 2006.238.07:34:39.25#ibcon#flushed, iclass 20, count 0 2006.238.07:34:39.25#ibcon#about to write, iclass 20, count 0 2006.238.07:34:39.25#ibcon#wrote, iclass 20, count 0 2006.238.07:34:39.25#ibcon#about to read 3, iclass 20, count 0 2006.238.07:34:39.29#ibcon#read 3, iclass 20, count 0 2006.238.07:34:39.29#ibcon#about to read 4, iclass 20, count 0 2006.238.07:34:39.29#ibcon#read 4, iclass 20, count 0 2006.238.07:34:39.29#ibcon#about to read 5, iclass 20, count 0 2006.238.07:34:39.29#ibcon#read 5, iclass 20, count 0 2006.238.07:34:39.29#ibcon#about to read 6, iclass 20, count 0 2006.238.07:34:39.29#ibcon#read 6, iclass 20, count 0 2006.238.07:34:39.29#ibcon#end of sib2, iclass 20, count 0 2006.238.07:34:39.29#ibcon#*after write, iclass 20, count 0 2006.238.07:34:39.29#ibcon#*before return 0, iclass 20, count 0 2006.238.07:34:39.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:34:39.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:34:39.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:34:39.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:34:39.29$vc4f8/va=5,8 2006.238.07:34:39.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.238.07:34:39.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.238.07:34:39.29#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:39.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:34:39.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:34:39.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:34:39.35#ibcon#enter wrdev, iclass 22, count 2 2006.238.07:34:39.35#ibcon#first serial, iclass 22, count 2 2006.238.07:34:39.35#ibcon#enter sib2, iclass 22, count 2 2006.238.07:34:39.35#ibcon#flushed, iclass 22, count 2 2006.238.07:34:39.35#ibcon#about to write, iclass 22, count 2 2006.238.07:34:39.35#ibcon#wrote, iclass 22, count 2 2006.238.07:34:39.35#ibcon#about to read 3, iclass 22, count 2 2006.238.07:34:39.37#ibcon#read 3, iclass 22, count 2 2006.238.07:34:39.37#ibcon#about to read 4, iclass 22, count 2 2006.238.07:34:39.37#ibcon#read 4, iclass 22, count 2 2006.238.07:34:39.37#ibcon#about to read 5, iclass 22, count 2 2006.238.07:34:39.37#ibcon#read 5, iclass 22, count 2 2006.238.07:34:39.37#ibcon#about to read 6, iclass 22, count 2 2006.238.07:34:39.37#ibcon#read 6, iclass 22, count 2 2006.238.07:34:39.37#ibcon#end of sib2, iclass 22, count 2 2006.238.07:34:39.37#ibcon#*mode == 0, iclass 22, count 2 2006.238.07:34:39.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.238.07:34:39.37#ibcon#[25=AT05-08\r\n] 2006.238.07:34:39.37#ibcon#*before write, iclass 22, count 2 2006.238.07:34:39.37#ibcon#enter sib2, iclass 22, count 2 2006.238.07:34:39.37#ibcon#flushed, iclass 22, count 2 2006.238.07:34:39.37#ibcon#about to write, iclass 22, count 2 2006.238.07:34:39.37#ibcon#wrote, iclass 22, count 2 2006.238.07:34:39.37#ibcon#about to read 3, iclass 22, count 2 2006.238.07:34:39.40#ibcon#read 3, iclass 22, count 2 2006.238.07:34:39.40#ibcon#about to read 4, iclass 22, count 2 2006.238.07:34:39.40#ibcon#read 4, iclass 22, count 2 2006.238.07:34:39.40#ibcon#about to read 5, iclass 22, count 2 2006.238.07:34:39.40#ibcon#read 5, iclass 22, count 2 2006.238.07:34:39.40#ibcon#about to read 6, iclass 22, count 2 2006.238.07:34:39.40#ibcon#read 6, iclass 22, count 2 2006.238.07:34:39.40#ibcon#end of sib2, iclass 22, count 2 2006.238.07:34:39.40#ibcon#*after write, iclass 22, count 2 2006.238.07:34:39.40#ibcon#*before return 0, iclass 22, count 2 2006.238.07:34:39.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:34:39.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:34:39.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.238.07:34:39.40#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:39.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:34:39.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:34:39.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:34:39.52#ibcon#enter wrdev, iclass 22, count 0 2006.238.07:34:39.52#ibcon#first serial, iclass 22, count 0 2006.238.07:34:39.52#ibcon#enter sib2, iclass 22, count 0 2006.238.07:34:39.52#ibcon#flushed, iclass 22, count 0 2006.238.07:34:39.52#ibcon#about to write, iclass 22, count 0 2006.238.07:34:39.52#ibcon#wrote, iclass 22, count 0 2006.238.07:34:39.52#ibcon#about to read 3, iclass 22, count 0 2006.238.07:34:39.54#ibcon#read 3, iclass 22, count 0 2006.238.07:34:39.54#ibcon#about to read 4, iclass 22, count 0 2006.238.07:34:39.54#ibcon#read 4, iclass 22, count 0 2006.238.07:34:39.54#ibcon#about to read 5, iclass 22, count 0 2006.238.07:34:39.54#ibcon#read 5, iclass 22, count 0 2006.238.07:34:39.54#ibcon#about to read 6, iclass 22, count 0 2006.238.07:34:39.54#ibcon#read 6, iclass 22, count 0 2006.238.07:34:39.54#ibcon#end of sib2, iclass 22, count 0 2006.238.07:34:39.54#ibcon#*mode == 0, iclass 22, count 0 2006.238.07:34:39.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.07:34:39.54#ibcon#[25=USB\r\n] 2006.238.07:34:39.54#ibcon#*before write, iclass 22, count 0 2006.238.07:34:39.54#ibcon#enter sib2, iclass 22, count 0 2006.238.07:34:39.54#ibcon#flushed, iclass 22, count 0 2006.238.07:34:39.54#ibcon#about to write, iclass 22, count 0 2006.238.07:34:39.54#ibcon#wrote, iclass 22, count 0 2006.238.07:34:39.54#ibcon#about to read 3, iclass 22, count 0 2006.238.07:34:39.57#ibcon#read 3, iclass 22, count 0 2006.238.07:34:39.57#ibcon#about to read 4, iclass 22, count 0 2006.238.07:34:39.57#ibcon#read 4, iclass 22, count 0 2006.238.07:34:39.57#ibcon#about to read 5, iclass 22, count 0 2006.238.07:34:39.57#ibcon#read 5, iclass 22, count 0 2006.238.07:34:39.57#ibcon#about to read 6, iclass 22, count 0 2006.238.07:34:39.57#ibcon#read 6, iclass 22, count 0 2006.238.07:34:39.57#ibcon#end of sib2, iclass 22, count 0 2006.238.07:34:39.57#ibcon#*after write, iclass 22, count 0 2006.238.07:34:39.57#ibcon#*before return 0, iclass 22, count 0 2006.238.07:34:39.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:34:39.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:34:39.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.07:34:39.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.07:34:39.57$vc4f8/valo=6,772.99 2006.238.07:34:39.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.07:34:39.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.07:34:39.57#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:39.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:34:39.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:34:39.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:34:39.57#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:34:39.57#ibcon#first serial, iclass 24, count 0 2006.238.07:34:39.57#ibcon#enter sib2, iclass 24, count 0 2006.238.07:34:39.57#ibcon#flushed, iclass 24, count 0 2006.238.07:34:39.57#ibcon#about to write, iclass 24, count 0 2006.238.07:34:39.57#ibcon#wrote, iclass 24, count 0 2006.238.07:34:39.57#ibcon#about to read 3, iclass 24, count 0 2006.238.07:34:39.59#ibcon#read 3, iclass 24, count 0 2006.238.07:34:39.59#ibcon#about to read 4, iclass 24, count 0 2006.238.07:34:39.59#ibcon#read 4, iclass 24, count 0 2006.238.07:34:39.59#ibcon#about to read 5, iclass 24, count 0 2006.238.07:34:39.59#ibcon#read 5, iclass 24, count 0 2006.238.07:34:39.59#ibcon#about to read 6, iclass 24, count 0 2006.238.07:34:39.59#ibcon#read 6, iclass 24, count 0 2006.238.07:34:39.59#ibcon#end of sib2, iclass 24, count 0 2006.238.07:34:39.59#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:34:39.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:34:39.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:34:39.59#ibcon#*before write, iclass 24, count 0 2006.238.07:34:39.59#ibcon#enter sib2, iclass 24, count 0 2006.238.07:34:39.59#ibcon#flushed, iclass 24, count 0 2006.238.07:34:39.59#ibcon#about to write, iclass 24, count 0 2006.238.07:34:39.59#ibcon#wrote, iclass 24, count 0 2006.238.07:34:39.59#ibcon#about to read 3, iclass 24, count 0 2006.238.07:34:39.63#ibcon#read 3, iclass 24, count 0 2006.238.07:34:39.63#ibcon#about to read 4, iclass 24, count 0 2006.238.07:34:39.63#ibcon#read 4, iclass 24, count 0 2006.238.07:34:39.63#ibcon#about to read 5, iclass 24, count 0 2006.238.07:34:39.63#ibcon#read 5, iclass 24, count 0 2006.238.07:34:39.63#ibcon#about to read 6, iclass 24, count 0 2006.238.07:34:39.63#ibcon#read 6, iclass 24, count 0 2006.238.07:34:39.63#ibcon#end of sib2, iclass 24, count 0 2006.238.07:34:39.63#ibcon#*after write, iclass 24, count 0 2006.238.07:34:39.63#ibcon#*before return 0, iclass 24, count 0 2006.238.07:34:39.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:34:39.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:34:39.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:34:39.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:34:39.63$vc4f8/va=6,7 2006.238.07:34:39.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.238.07:34:39.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.238.07:34:39.63#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:39.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:34:39.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:34:39.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:34:39.69#ibcon#enter wrdev, iclass 26, count 2 2006.238.07:34:39.69#ibcon#first serial, iclass 26, count 2 2006.238.07:34:39.69#ibcon#enter sib2, iclass 26, count 2 2006.238.07:34:39.69#ibcon#flushed, iclass 26, count 2 2006.238.07:34:39.69#ibcon#about to write, iclass 26, count 2 2006.238.07:34:39.69#ibcon#wrote, iclass 26, count 2 2006.238.07:34:39.69#ibcon#about to read 3, iclass 26, count 2 2006.238.07:34:39.71#ibcon#read 3, iclass 26, count 2 2006.238.07:34:39.71#ibcon#about to read 4, iclass 26, count 2 2006.238.07:34:39.71#ibcon#read 4, iclass 26, count 2 2006.238.07:34:39.71#ibcon#about to read 5, iclass 26, count 2 2006.238.07:34:39.71#ibcon#read 5, iclass 26, count 2 2006.238.07:34:39.71#ibcon#about to read 6, iclass 26, count 2 2006.238.07:34:39.71#ibcon#read 6, iclass 26, count 2 2006.238.07:34:39.71#ibcon#end of sib2, iclass 26, count 2 2006.238.07:34:39.71#ibcon#*mode == 0, iclass 26, count 2 2006.238.07:34:39.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.238.07:34:39.71#ibcon#[25=AT06-07\r\n] 2006.238.07:34:39.71#ibcon#*before write, iclass 26, count 2 2006.238.07:34:39.71#ibcon#enter sib2, iclass 26, count 2 2006.238.07:34:39.71#ibcon#flushed, iclass 26, count 2 2006.238.07:34:39.71#ibcon#about to write, iclass 26, count 2 2006.238.07:34:39.71#ibcon#wrote, iclass 26, count 2 2006.238.07:34:39.71#ibcon#about to read 3, iclass 26, count 2 2006.238.07:34:39.74#ibcon#read 3, iclass 26, count 2 2006.238.07:34:39.74#ibcon#about to read 4, iclass 26, count 2 2006.238.07:34:39.74#ibcon#read 4, iclass 26, count 2 2006.238.07:34:39.74#ibcon#about to read 5, iclass 26, count 2 2006.238.07:34:39.74#ibcon#read 5, iclass 26, count 2 2006.238.07:34:39.74#ibcon#about to read 6, iclass 26, count 2 2006.238.07:34:39.74#ibcon#read 6, iclass 26, count 2 2006.238.07:34:39.74#ibcon#end of sib2, iclass 26, count 2 2006.238.07:34:39.74#ibcon#*after write, iclass 26, count 2 2006.238.07:34:39.74#ibcon#*before return 0, iclass 26, count 2 2006.238.07:34:39.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:34:39.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:34:39.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.238.07:34:39.74#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:39.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:34:39.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:34:39.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:34:39.86#ibcon#enter wrdev, iclass 26, count 0 2006.238.07:34:39.86#ibcon#first serial, iclass 26, count 0 2006.238.07:34:39.86#ibcon#enter sib2, iclass 26, count 0 2006.238.07:34:39.86#ibcon#flushed, iclass 26, count 0 2006.238.07:34:39.86#ibcon#about to write, iclass 26, count 0 2006.238.07:34:39.86#ibcon#wrote, iclass 26, count 0 2006.238.07:34:39.86#ibcon#about to read 3, iclass 26, count 0 2006.238.07:34:39.88#ibcon#read 3, iclass 26, count 0 2006.238.07:34:39.88#ibcon#about to read 4, iclass 26, count 0 2006.238.07:34:39.88#ibcon#read 4, iclass 26, count 0 2006.238.07:34:39.88#ibcon#about to read 5, iclass 26, count 0 2006.238.07:34:39.88#ibcon#read 5, iclass 26, count 0 2006.238.07:34:39.88#ibcon#about to read 6, iclass 26, count 0 2006.238.07:34:39.88#ibcon#read 6, iclass 26, count 0 2006.238.07:34:39.88#ibcon#end of sib2, iclass 26, count 0 2006.238.07:34:39.88#ibcon#*mode == 0, iclass 26, count 0 2006.238.07:34:39.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.07:34:39.88#ibcon#[25=USB\r\n] 2006.238.07:34:39.88#ibcon#*before write, iclass 26, count 0 2006.238.07:34:39.88#ibcon#enter sib2, iclass 26, count 0 2006.238.07:34:39.88#ibcon#flushed, iclass 26, count 0 2006.238.07:34:39.88#ibcon#about to write, iclass 26, count 0 2006.238.07:34:39.88#ibcon#wrote, iclass 26, count 0 2006.238.07:34:39.88#ibcon#about to read 3, iclass 26, count 0 2006.238.07:34:39.91#ibcon#read 3, iclass 26, count 0 2006.238.07:34:39.91#ibcon#about to read 4, iclass 26, count 0 2006.238.07:34:39.91#ibcon#read 4, iclass 26, count 0 2006.238.07:34:39.91#ibcon#about to read 5, iclass 26, count 0 2006.238.07:34:39.91#ibcon#read 5, iclass 26, count 0 2006.238.07:34:39.91#ibcon#about to read 6, iclass 26, count 0 2006.238.07:34:39.91#ibcon#read 6, iclass 26, count 0 2006.238.07:34:39.91#ibcon#end of sib2, iclass 26, count 0 2006.238.07:34:39.91#ibcon#*after write, iclass 26, count 0 2006.238.07:34:39.91#ibcon#*before return 0, iclass 26, count 0 2006.238.07:34:39.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:34:39.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:34:39.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.07:34:39.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.07:34:39.91$vc4f8/valo=7,832.99 2006.238.07:34:39.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.238.07:34:39.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.238.07:34:39.91#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:39.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:34:39.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:34:39.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:34:39.91#ibcon#enter wrdev, iclass 28, count 0 2006.238.07:34:39.91#ibcon#first serial, iclass 28, count 0 2006.238.07:34:39.91#ibcon#enter sib2, iclass 28, count 0 2006.238.07:34:39.91#ibcon#flushed, iclass 28, count 0 2006.238.07:34:39.91#ibcon#about to write, iclass 28, count 0 2006.238.07:34:39.91#ibcon#wrote, iclass 28, count 0 2006.238.07:34:39.91#ibcon#about to read 3, iclass 28, count 0 2006.238.07:34:39.93#ibcon#read 3, iclass 28, count 0 2006.238.07:34:39.93#ibcon#about to read 4, iclass 28, count 0 2006.238.07:34:39.93#ibcon#read 4, iclass 28, count 0 2006.238.07:34:39.93#ibcon#about to read 5, iclass 28, count 0 2006.238.07:34:39.93#ibcon#read 5, iclass 28, count 0 2006.238.07:34:39.93#ibcon#about to read 6, iclass 28, count 0 2006.238.07:34:39.93#ibcon#read 6, iclass 28, count 0 2006.238.07:34:39.93#ibcon#end of sib2, iclass 28, count 0 2006.238.07:34:39.93#ibcon#*mode == 0, iclass 28, count 0 2006.238.07:34:39.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.07:34:39.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:34:39.93#ibcon#*before write, iclass 28, count 0 2006.238.07:34:39.93#ibcon#enter sib2, iclass 28, count 0 2006.238.07:34:39.93#ibcon#flushed, iclass 28, count 0 2006.238.07:34:39.93#ibcon#about to write, iclass 28, count 0 2006.238.07:34:39.93#ibcon#wrote, iclass 28, count 0 2006.238.07:34:39.93#ibcon#about to read 3, iclass 28, count 0 2006.238.07:34:39.97#ibcon#read 3, iclass 28, count 0 2006.238.07:34:39.97#ibcon#about to read 4, iclass 28, count 0 2006.238.07:34:39.97#ibcon#read 4, iclass 28, count 0 2006.238.07:34:39.97#ibcon#about to read 5, iclass 28, count 0 2006.238.07:34:39.97#ibcon#read 5, iclass 28, count 0 2006.238.07:34:39.97#ibcon#about to read 6, iclass 28, count 0 2006.238.07:34:39.97#ibcon#read 6, iclass 28, count 0 2006.238.07:34:39.97#ibcon#end of sib2, iclass 28, count 0 2006.238.07:34:39.97#ibcon#*after write, iclass 28, count 0 2006.238.07:34:39.97#ibcon#*before return 0, iclass 28, count 0 2006.238.07:34:39.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:34:39.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:34:39.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.07:34:39.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.07:34:39.97$vc4f8/va=7,7 2006.238.07:34:39.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.238.07:34:39.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.238.07:34:39.97#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:39.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:34:40.04#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:34:40.04#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:34:40.04#ibcon#enter wrdev, iclass 30, count 2 2006.238.07:34:40.04#ibcon#first serial, iclass 30, count 2 2006.238.07:34:40.04#ibcon#enter sib2, iclass 30, count 2 2006.238.07:34:40.04#ibcon#flushed, iclass 30, count 2 2006.238.07:34:40.04#ibcon#about to write, iclass 30, count 2 2006.238.07:34:40.04#ibcon#wrote, iclass 30, count 2 2006.238.07:34:40.04#ibcon#about to read 3, iclass 30, count 2 2006.238.07:34:40.05#ibcon#read 3, iclass 30, count 2 2006.238.07:34:40.05#ibcon#about to read 4, iclass 30, count 2 2006.238.07:34:40.05#ibcon#read 4, iclass 30, count 2 2006.238.07:34:40.05#ibcon#about to read 5, iclass 30, count 2 2006.238.07:34:40.05#ibcon#read 5, iclass 30, count 2 2006.238.07:34:40.05#ibcon#about to read 6, iclass 30, count 2 2006.238.07:34:40.05#ibcon#read 6, iclass 30, count 2 2006.238.07:34:40.05#ibcon#end of sib2, iclass 30, count 2 2006.238.07:34:40.05#ibcon#*mode == 0, iclass 30, count 2 2006.238.07:34:40.05#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.238.07:34:40.05#ibcon#[25=AT07-07\r\n] 2006.238.07:34:40.05#ibcon#*before write, iclass 30, count 2 2006.238.07:34:40.05#ibcon#enter sib2, iclass 30, count 2 2006.238.07:34:40.05#ibcon#flushed, iclass 30, count 2 2006.238.07:34:40.05#ibcon#about to write, iclass 30, count 2 2006.238.07:34:40.05#ibcon#wrote, iclass 30, count 2 2006.238.07:34:40.05#ibcon#about to read 3, iclass 30, count 2 2006.238.07:34:40.08#ibcon#read 3, iclass 30, count 2 2006.238.07:34:40.08#ibcon#about to read 4, iclass 30, count 2 2006.238.07:34:40.08#ibcon#read 4, iclass 30, count 2 2006.238.07:34:40.08#ibcon#about to read 5, iclass 30, count 2 2006.238.07:34:40.08#ibcon#read 5, iclass 30, count 2 2006.238.07:34:40.08#ibcon#about to read 6, iclass 30, count 2 2006.238.07:34:40.08#ibcon#read 6, iclass 30, count 2 2006.238.07:34:40.08#ibcon#end of sib2, iclass 30, count 2 2006.238.07:34:40.08#ibcon#*after write, iclass 30, count 2 2006.238.07:34:40.08#ibcon#*before return 0, iclass 30, count 2 2006.238.07:34:40.08#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:34:40.08#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:34:40.08#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.238.07:34:40.08#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:40.08#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:34:40.20#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:34:40.20#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:34:40.20#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:34:40.20#ibcon#first serial, iclass 30, count 0 2006.238.07:34:40.20#ibcon#enter sib2, iclass 30, count 0 2006.238.07:34:40.20#ibcon#flushed, iclass 30, count 0 2006.238.07:34:40.20#ibcon#about to write, iclass 30, count 0 2006.238.07:34:40.20#ibcon#wrote, iclass 30, count 0 2006.238.07:34:40.20#ibcon#about to read 3, iclass 30, count 0 2006.238.07:34:40.22#ibcon#read 3, iclass 30, count 0 2006.238.07:34:40.22#ibcon#about to read 4, iclass 30, count 0 2006.238.07:34:40.22#ibcon#read 4, iclass 30, count 0 2006.238.07:34:40.22#ibcon#about to read 5, iclass 30, count 0 2006.238.07:34:40.22#ibcon#read 5, iclass 30, count 0 2006.238.07:34:40.22#ibcon#about to read 6, iclass 30, count 0 2006.238.07:34:40.22#ibcon#read 6, iclass 30, count 0 2006.238.07:34:40.22#ibcon#end of sib2, iclass 30, count 0 2006.238.07:34:40.22#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:34:40.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:34:40.22#ibcon#[25=USB\r\n] 2006.238.07:34:40.22#ibcon#*before write, iclass 30, count 0 2006.238.07:34:40.22#ibcon#enter sib2, iclass 30, count 0 2006.238.07:34:40.22#ibcon#flushed, iclass 30, count 0 2006.238.07:34:40.22#ibcon#about to write, iclass 30, count 0 2006.238.07:34:40.22#ibcon#wrote, iclass 30, count 0 2006.238.07:34:40.22#ibcon#about to read 3, iclass 30, count 0 2006.238.07:34:40.25#ibcon#read 3, iclass 30, count 0 2006.238.07:34:40.25#ibcon#about to read 4, iclass 30, count 0 2006.238.07:34:40.25#ibcon#read 4, iclass 30, count 0 2006.238.07:34:40.25#ibcon#about to read 5, iclass 30, count 0 2006.238.07:34:40.25#ibcon#read 5, iclass 30, count 0 2006.238.07:34:40.25#ibcon#about to read 6, iclass 30, count 0 2006.238.07:34:40.25#ibcon#read 6, iclass 30, count 0 2006.238.07:34:40.25#ibcon#end of sib2, iclass 30, count 0 2006.238.07:34:40.25#ibcon#*after write, iclass 30, count 0 2006.238.07:34:40.25#ibcon#*before return 0, iclass 30, count 0 2006.238.07:34:40.25#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:34:40.25#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:34:40.25#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:34:40.25#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:34:40.25$vc4f8/valo=8,852.99 2006.238.07:34:40.25#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.07:34:40.25#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.07:34:40.25#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:40.25#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:34:40.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:34:40.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:34:40.25#ibcon#enter wrdev, iclass 32, count 0 2006.238.07:34:40.25#ibcon#first serial, iclass 32, count 0 2006.238.07:34:40.25#ibcon#enter sib2, iclass 32, count 0 2006.238.07:34:40.25#ibcon#flushed, iclass 32, count 0 2006.238.07:34:40.25#ibcon#about to write, iclass 32, count 0 2006.238.07:34:40.25#ibcon#wrote, iclass 32, count 0 2006.238.07:34:40.25#ibcon#about to read 3, iclass 32, count 0 2006.238.07:34:40.27#ibcon#read 3, iclass 32, count 0 2006.238.07:34:40.27#ibcon#about to read 4, iclass 32, count 0 2006.238.07:34:40.27#ibcon#read 4, iclass 32, count 0 2006.238.07:34:40.27#ibcon#about to read 5, iclass 32, count 0 2006.238.07:34:40.27#ibcon#read 5, iclass 32, count 0 2006.238.07:34:40.27#ibcon#about to read 6, iclass 32, count 0 2006.238.07:34:40.27#ibcon#read 6, iclass 32, count 0 2006.238.07:34:40.27#ibcon#end of sib2, iclass 32, count 0 2006.238.07:34:40.27#ibcon#*mode == 0, iclass 32, count 0 2006.238.07:34:40.27#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.07:34:40.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:34:40.27#ibcon#*before write, iclass 32, count 0 2006.238.07:34:40.27#ibcon#enter sib2, iclass 32, count 0 2006.238.07:34:40.27#ibcon#flushed, iclass 32, count 0 2006.238.07:34:40.27#ibcon#about to write, iclass 32, count 0 2006.238.07:34:40.27#ibcon#wrote, iclass 32, count 0 2006.238.07:34:40.27#ibcon#about to read 3, iclass 32, count 0 2006.238.07:34:40.31#ibcon#read 3, iclass 32, count 0 2006.238.07:34:40.31#ibcon#about to read 4, iclass 32, count 0 2006.238.07:34:40.31#ibcon#read 4, iclass 32, count 0 2006.238.07:34:40.31#ibcon#about to read 5, iclass 32, count 0 2006.238.07:34:40.31#ibcon#read 5, iclass 32, count 0 2006.238.07:34:40.31#ibcon#about to read 6, iclass 32, count 0 2006.238.07:34:40.31#ibcon#read 6, iclass 32, count 0 2006.238.07:34:40.31#ibcon#end of sib2, iclass 32, count 0 2006.238.07:34:40.31#ibcon#*after write, iclass 32, count 0 2006.238.07:34:40.31#ibcon#*before return 0, iclass 32, count 0 2006.238.07:34:40.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:34:40.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:34:40.31#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.07:34:40.31#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.07:34:40.31$vc4f8/va=8,7 2006.238.07:34:40.31#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.238.07:34:40.31#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.238.07:34:40.31#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:40.31#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:34:40.37#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:34:40.37#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:34:40.37#ibcon#enter wrdev, iclass 34, count 2 2006.238.07:34:40.37#ibcon#first serial, iclass 34, count 2 2006.238.07:34:40.37#ibcon#enter sib2, iclass 34, count 2 2006.238.07:34:40.37#ibcon#flushed, iclass 34, count 2 2006.238.07:34:40.37#ibcon#about to write, iclass 34, count 2 2006.238.07:34:40.37#ibcon#wrote, iclass 34, count 2 2006.238.07:34:40.37#ibcon#about to read 3, iclass 34, count 2 2006.238.07:34:40.39#ibcon#read 3, iclass 34, count 2 2006.238.07:34:40.39#ibcon#about to read 4, iclass 34, count 2 2006.238.07:34:40.39#ibcon#read 4, iclass 34, count 2 2006.238.07:34:40.39#ibcon#about to read 5, iclass 34, count 2 2006.238.07:34:40.39#ibcon#read 5, iclass 34, count 2 2006.238.07:34:40.39#ibcon#about to read 6, iclass 34, count 2 2006.238.07:34:40.39#ibcon#read 6, iclass 34, count 2 2006.238.07:34:40.39#ibcon#end of sib2, iclass 34, count 2 2006.238.07:34:40.39#ibcon#*mode == 0, iclass 34, count 2 2006.238.07:34:40.39#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.238.07:34:40.39#ibcon#[25=AT08-07\r\n] 2006.238.07:34:40.39#ibcon#*before write, iclass 34, count 2 2006.238.07:34:40.39#ibcon#enter sib2, iclass 34, count 2 2006.238.07:34:40.39#ibcon#flushed, iclass 34, count 2 2006.238.07:34:40.39#ibcon#about to write, iclass 34, count 2 2006.238.07:34:40.39#ibcon#wrote, iclass 34, count 2 2006.238.07:34:40.39#ibcon#about to read 3, iclass 34, count 2 2006.238.07:34:40.42#ibcon#read 3, iclass 34, count 2 2006.238.07:34:40.42#ibcon#about to read 4, iclass 34, count 2 2006.238.07:34:40.42#ibcon#read 4, iclass 34, count 2 2006.238.07:34:40.42#ibcon#about to read 5, iclass 34, count 2 2006.238.07:34:40.42#ibcon#read 5, iclass 34, count 2 2006.238.07:34:40.42#ibcon#about to read 6, iclass 34, count 2 2006.238.07:34:40.42#ibcon#read 6, iclass 34, count 2 2006.238.07:34:40.42#ibcon#end of sib2, iclass 34, count 2 2006.238.07:34:40.42#ibcon#*after write, iclass 34, count 2 2006.238.07:34:40.42#ibcon#*before return 0, iclass 34, count 2 2006.238.07:34:40.42#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:34:40.42#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:34:40.42#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.238.07:34:40.42#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:40.42#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:34:40.54#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:34:40.54#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:34:40.54#ibcon#enter wrdev, iclass 34, count 0 2006.238.07:34:40.54#ibcon#first serial, iclass 34, count 0 2006.238.07:34:40.54#ibcon#enter sib2, iclass 34, count 0 2006.238.07:34:40.54#ibcon#flushed, iclass 34, count 0 2006.238.07:34:40.54#ibcon#about to write, iclass 34, count 0 2006.238.07:34:40.54#ibcon#wrote, iclass 34, count 0 2006.238.07:34:40.54#ibcon#about to read 3, iclass 34, count 0 2006.238.07:34:40.56#ibcon#read 3, iclass 34, count 0 2006.238.07:34:40.56#ibcon#about to read 4, iclass 34, count 0 2006.238.07:34:40.56#ibcon#read 4, iclass 34, count 0 2006.238.07:34:40.56#ibcon#about to read 5, iclass 34, count 0 2006.238.07:34:40.56#ibcon#read 5, iclass 34, count 0 2006.238.07:34:40.56#ibcon#about to read 6, iclass 34, count 0 2006.238.07:34:40.56#ibcon#read 6, iclass 34, count 0 2006.238.07:34:40.56#ibcon#end of sib2, iclass 34, count 0 2006.238.07:34:40.56#ibcon#*mode == 0, iclass 34, count 0 2006.238.07:34:40.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.07:34:40.56#ibcon#[25=USB\r\n] 2006.238.07:34:40.56#ibcon#*before write, iclass 34, count 0 2006.238.07:34:40.56#ibcon#enter sib2, iclass 34, count 0 2006.238.07:34:40.56#ibcon#flushed, iclass 34, count 0 2006.238.07:34:40.56#ibcon#about to write, iclass 34, count 0 2006.238.07:34:40.56#ibcon#wrote, iclass 34, count 0 2006.238.07:34:40.56#ibcon#about to read 3, iclass 34, count 0 2006.238.07:34:40.59#ibcon#read 3, iclass 34, count 0 2006.238.07:34:40.59#ibcon#about to read 4, iclass 34, count 0 2006.238.07:34:40.59#ibcon#read 4, iclass 34, count 0 2006.238.07:34:40.59#ibcon#about to read 5, iclass 34, count 0 2006.238.07:34:40.59#ibcon#read 5, iclass 34, count 0 2006.238.07:34:40.59#ibcon#about to read 6, iclass 34, count 0 2006.238.07:34:40.59#ibcon#read 6, iclass 34, count 0 2006.238.07:34:40.59#ibcon#end of sib2, iclass 34, count 0 2006.238.07:34:40.59#ibcon#*after write, iclass 34, count 0 2006.238.07:34:40.59#ibcon#*before return 0, iclass 34, count 0 2006.238.07:34:40.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:34:40.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:34:40.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.07:34:40.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.07:34:40.59$vc4f8/vblo=1,632.99 2006.238.07:34:40.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.07:34:40.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.07:34:40.59#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:40.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:34:40.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:34:40.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:34:40.59#ibcon#enter wrdev, iclass 36, count 0 2006.238.07:34:40.59#ibcon#first serial, iclass 36, count 0 2006.238.07:34:40.59#ibcon#enter sib2, iclass 36, count 0 2006.238.07:34:40.59#ibcon#flushed, iclass 36, count 0 2006.238.07:34:40.59#ibcon#about to write, iclass 36, count 0 2006.238.07:34:40.59#ibcon#wrote, iclass 36, count 0 2006.238.07:34:40.59#ibcon#about to read 3, iclass 36, count 0 2006.238.07:34:40.61#ibcon#read 3, iclass 36, count 0 2006.238.07:34:40.61#ibcon#about to read 4, iclass 36, count 0 2006.238.07:34:40.61#ibcon#read 4, iclass 36, count 0 2006.238.07:34:40.61#ibcon#about to read 5, iclass 36, count 0 2006.238.07:34:40.61#ibcon#read 5, iclass 36, count 0 2006.238.07:34:40.61#ibcon#about to read 6, iclass 36, count 0 2006.238.07:34:40.61#ibcon#read 6, iclass 36, count 0 2006.238.07:34:40.61#ibcon#end of sib2, iclass 36, count 0 2006.238.07:34:40.61#ibcon#*mode == 0, iclass 36, count 0 2006.238.07:34:40.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.07:34:40.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:34:40.61#ibcon#*before write, iclass 36, count 0 2006.238.07:34:40.61#ibcon#enter sib2, iclass 36, count 0 2006.238.07:34:40.61#ibcon#flushed, iclass 36, count 0 2006.238.07:34:40.61#ibcon#about to write, iclass 36, count 0 2006.238.07:34:40.61#ibcon#wrote, iclass 36, count 0 2006.238.07:34:40.61#ibcon#about to read 3, iclass 36, count 0 2006.238.07:34:40.65#ibcon#read 3, iclass 36, count 0 2006.238.07:34:40.65#ibcon#about to read 4, iclass 36, count 0 2006.238.07:34:40.65#ibcon#read 4, iclass 36, count 0 2006.238.07:34:40.65#ibcon#about to read 5, iclass 36, count 0 2006.238.07:34:40.65#ibcon#read 5, iclass 36, count 0 2006.238.07:34:40.65#ibcon#about to read 6, iclass 36, count 0 2006.238.07:34:40.65#ibcon#read 6, iclass 36, count 0 2006.238.07:34:40.65#ibcon#end of sib2, iclass 36, count 0 2006.238.07:34:40.65#ibcon#*after write, iclass 36, count 0 2006.238.07:34:40.65#ibcon#*before return 0, iclass 36, count 0 2006.238.07:34:40.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:34:40.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:34:40.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.07:34:40.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.07:34:40.65$vc4f8/vb=1,4 2006.238.07:34:40.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.238.07:34:40.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.238.07:34:40.65#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:40.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:34:40.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:34:40.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:34:40.65#ibcon#enter wrdev, iclass 38, count 2 2006.238.07:34:40.65#ibcon#first serial, iclass 38, count 2 2006.238.07:34:40.65#ibcon#enter sib2, iclass 38, count 2 2006.238.07:34:40.65#ibcon#flushed, iclass 38, count 2 2006.238.07:34:40.65#ibcon#about to write, iclass 38, count 2 2006.238.07:34:40.65#ibcon#wrote, iclass 38, count 2 2006.238.07:34:40.65#ibcon#about to read 3, iclass 38, count 2 2006.238.07:34:40.67#ibcon#read 3, iclass 38, count 2 2006.238.07:34:40.67#ibcon#about to read 4, iclass 38, count 2 2006.238.07:34:40.67#ibcon#read 4, iclass 38, count 2 2006.238.07:34:40.67#ibcon#about to read 5, iclass 38, count 2 2006.238.07:34:40.67#ibcon#read 5, iclass 38, count 2 2006.238.07:34:40.67#ibcon#about to read 6, iclass 38, count 2 2006.238.07:34:40.67#ibcon#read 6, iclass 38, count 2 2006.238.07:34:40.67#ibcon#end of sib2, iclass 38, count 2 2006.238.07:34:40.67#ibcon#*mode == 0, iclass 38, count 2 2006.238.07:34:40.67#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.238.07:34:40.67#ibcon#[27=AT01-04\r\n] 2006.238.07:34:40.67#ibcon#*before write, iclass 38, count 2 2006.238.07:34:40.67#ibcon#enter sib2, iclass 38, count 2 2006.238.07:34:40.67#ibcon#flushed, iclass 38, count 2 2006.238.07:34:40.67#ibcon#about to write, iclass 38, count 2 2006.238.07:34:40.67#ibcon#wrote, iclass 38, count 2 2006.238.07:34:40.67#ibcon#about to read 3, iclass 38, count 2 2006.238.07:34:40.70#ibcon#read 3, iclass 38, count 2 2006.238.07:34:40.70#ibcon#about to read 4, iclass 38, count 2 2006.238.07:34:40.70#ibcon#read 4, iclass 38, count 2 2006.238.07:34:40.70#ibcon#about to read 5, iclass 38, count 2 2006.238.07:34:40.70#ibcon#read 5, iclass 38, count 2 2006.238.07:34:40.70#ibcon#about to read 6, iclass 38, count 2 2006.238.07:34:40.70#ibcon#read 6, iclass 38, count 2 2006.238.07:34:40.70#ibcon#end of sib2, iclass 38, count 2 2006.238.07:34:40.70#ibcon#*after write, iclass 38, count 2 2006.238.07:34:40.70#ibcon#*before return 0, iclass 38, count 2 2006.238.07:34:40.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:34:40.70#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:34:40.70#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.238.07:34:40.70#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:40.70#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:34:40.83#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:34:40.83#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:34:40.83#ibcon#enter wrdev, iclass 38, count 0 2006.238.07:34:40.83#ibcon#first serial, iclass 38, count 0 2006.238.07:34:40.83#ibcon#enter sib2, iclass 38, count 0 2006.238.07:34:40.83#ibcon#flushed, iclass 38, count 0 2006.238.07:34:40.83#ibcon#about to write, iclass 38, count 0 2006.238.07:34:40.83#ibcon#wrote, iclass 38, count 0 2006.238.07:34:40.83#ibcon#about to read 3, iclass 38, count 0 2006.238.07:34:40.85#ibcon#read 3, iclass 38, count 0 2006.238.07:34:40.85#ibcon#about to read 4, iclass 38, count 0 2006.238.07:34:40.85#ibcon#read 4, iclass 38, count 0 2006.238.07:34:40.85#ibcon#about to read 5, iclass 38, count 0 2006.238.07:34:40.85#ibcon#read 5, iclass 38, count 0 2006.238.07:34:40.85#ibcon#about to read 6, iclass 38, count 0 2006.238.07:34:40.85#ibcon#read 6, iclass 38, count 0 2006.238.07:34:40.85#ibcon#end of sib2, iclass 38, count 0 2006.238.07:34:40.85#ibcon#*mode == 0, iclass 38, count 0 2006.238.07:34:40.85#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.07:34:40.85#ibcon#[27=USB\r\n] 2006.238.07:34:40.85#ibcon#*before write, iclass 38, count 0 2006.238.07:34:40.85#ibcon#enter sib2, iclass 38, count 0 2006.238.07:34:40.85#ibcon#flushed, iclass 38, count 0 2006.238.07:34:40.85#ibcon#about to write, iclass 38, count 0 2006.238.07:34:40.85#ibcon#wrote, iclass 38, count 0 2006.238.07:34:40.85#ibcon#about to read 3, iclass 38, count 0 2006.238.07:34:40.88#ibcon#read 3, iclass 38, count 0 2006.238.07:34:40.88#ibcon#about to read 4, iclass 38, count 0 2006.238.07:34:40.88#ibcon#read 4, iclass 38, count 0 2006.238.07:34:40.88#ibcon#about to read 5, iclass 38, count 0 2006.238.07:34:40.88#ibcon#read 5, iclass 38, count 0 2006.238.07:34:40.88#ibcon#about to read 6, iclass 38, count 0 2006.238.07:34:40.88#ibcon#read 6, iclass 38, count 0 2006.238.07:34:40.88#ibcon#end of sib2, iclass 38, count 0 2006.238.07:34:40.88#ibcon#*after write, iclass 38, count 0 2006.238.07:34:40.88#ibcon#*before return 0, iclass 38, count 0 2006.238.07:34:40.88#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:34:40.88#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:34:40.88#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.07:34:40.88#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.07:34:40.88$vc4f8/vblo=2,640.99 2006.238.07:34:40.88#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.07:34:40.88#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.07:34:40.88#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:40.88#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:34:40.88#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:34:40.88#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:34:40.88#ibcon#enter wrdev, iclass 40, count 0 2006.238.07:34:40.88#ibcon#first serial, iclass 40, count 0 2006.238.07:34:40.88#ibcon#enter sib2, iclass 40, count 0 2006.238.07:34:40.88#ibcon#flushed, iclass 40, count 0 2006.238.07:34:40.88#ibcon#about to write, iclass 40, count 0 2006.238.07:34:40.88#ibcon#wrote, iclass 40, count 0 2006.238.07:34:40.88#ibcon#about to read 3, iclass 40, count 0 2006.238.07:34:40.90#ibcon#read 3, iclass 40, count 0 2006.238.07:34:40.90#ibcon#about to read 4, iclass 40, count 0 2006.238.07:34:40.90#ibcon#read 4, iclass 40, count 0 2006.238.07:34:40.90#ibcon#about to read 5, iclass 40, count 0 2006.238.07:34:40.90#ibcon#read 5, iclass 40, count 0 2006.238.07:34:40.90#ibcon#about to read 6, iclass 40, count 0 2006.238.07:34:40.90#ibcon#read 6, iclass 40, count 0 2006.238.07:34:40.90#ibcon#end of sib2, iclass 40, count 0 2006.238.07:34:40.90#ibcon#*mode == 0, iclass 40, count 0 2006.238.07:34:40.90#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.07:34:40.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:34:40.90#ibcon#*before write, iclass 40, count 0 2006.238.07:34:40.90#ibcon#enter sib2, iclass 40, count 0 2006.238.07:34:40.90#ibcon#flushed, iclass 40, count 0 2006.238.07:34:40.90#ibcon#about to write, iclass 40, count 0 2006.238.07:34:40.90#ibcon#wrote, iclass 40, count 0 2006.238.07:34:40.90#ibcon#about to read 3, iclass 40, count 0 2006.238.07:34:40.94#ibcon#read 3, iclass 40, count 0 2006.238.07:34:40.94#ibcon#about to read 4, iclass 40, count 0 2006.238.07:34:40.94#ibcon#read 4, iclass 40, count 0 2006.238.07:34:40.94#ibcon#about to read 5, iclass 40, count 0 2006.238.07:34:40.94#ibcon#read 5, iclass 40, count 0 2006.238.07:34:40.94#ibcon#about to read 6, iclass 40, count 0 2006.238.07:34:40.94#ibcon#read 6, iclass 40, count 0 2006.238.07:34:40.94#ibcon#end of sib2, iclass 40, count 0 2006.238.07:34:40.94#ibcon#*after write, iclass 40, count 0 2006.238.07:34:40.94#ibcon#*before return 0, iclass 40, count 0 2006.238.07:34:40.94#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:34:40.94#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:34:40.94#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.07:34:40.94#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.07:34:40.94$vc4f8/vb=2,4 2006.238.07:34:40.94#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.238.07:34:40.94#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.238.07:34:40.94#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:40.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:34:41.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:34:41.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:34:41.00#ibcon#enter wrdev, iclass 4, count 2 2006.238.07:34:41.00#ibcon#first serial, iclass 4, count 2 2006.238.07:34:41.00#ibcon#enter sib2, iclass 4, count 2 2006.238.07:34:41.00#ibcon#flushed, iclass 4, count 2 2006.238.07:34:41.00#ibcon#about to write, iclass 4, count 2 2006.238.07:34:41.00#ibcon#wrote, iclass 4, count 2 2006.238.07:34:41.00#ibcon#about to read 3, iclass 4, count 2 2006.238.07:34:41.02#ibcon#read 3, iclass 4, count 2 2006.238.07:34:41.02#ibcon#about to read 4, iclass 4, count 2 2006.238.07:34:41.02#ibcon#read 4, iclass 4, count 2 2006.238.07:34:41.02#ibcon#about to read 5, iclass 4, count 2 2006.238.07:34:41.02#ibcon#read 5, iclass 4, count 2 2006.238.07:34:41.02#ibcon#about to read 6, iclass 4, count 2 2006.238.07:34:41.02#ibcon#read 6, iclass 4, count 2 2006.238.07:34:41.02#ibcon#end of sib2, iclass 4, count 2 2006.238.07:34:41.02#ibcon#*mode == 0, iclass 4, count 2 2006.238.07:34:41.02#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.238.07:34:41.02#ibcon#[27=AT02-04\r\n] 2006.238.07:34:41.02#ibcon#*before write, iclass 4, count 2 2006.238.07:34:41.02#ibcon#enter sib2, iclass 4, count 2 2006.238.07:34:41.02#ibcon#flushed, iclass 4, count 2 2006.238.07:34:41.02#ibcon#about to write, iclass 4, count 2 2006.238.07:34:41.02#ibcon#wrote, iclass 4, count 2 2006.238.07:34:41.02#ibcon#about to read 3, iclass 4, count 2 2006.238.07:34:41.05#ibcon#read 3, iclass 4, count 2 2006.238.07:34:41.05#ibcon#about to read 4, iclass 4, count 2 2006.238.07:34:41.05#ibcon#read 4, iclass 4, count 2 2006.238.07:34:41.05#ibcon#about to read 5, iclass 4, count 2 2006.238.07:34:41.05#ibcon#read 5, iclass 4, count 2 2006.238.07:34:41.05#ibcon#about to read 6, iclass 4, count 2 2006.238.07:34:41.05#ibcon#read 6, iclass 4, count 2 2006.238.07:34:41.05#ibcon#end of sib2, iclass 4, count 2 2006.238.07:34:41.05#ibcon#*after write, iclass 4, count 2 2006.238.07:34:41.05#ibcon#*before return 0, iclass 4, count 2 2006.238.07:34:41.05#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:34:41.05#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:34:41.05#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.238.07:34:41.05#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:41.05#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:34:41.17#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:34:41.17#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:34:41.17#ibcon#enter wrdev, iclass 4, count 0 2006.238.07:34:41.17#ibcon#first serial, iclass 4, count 0 2006.238.07:34:41.17#ibcon#enter sib2, iclass 4, count 0 2006.238.07:34:41.17#ibcon#flushed, iclass 4, count 0 2006.238.07:34:41.17#ibcon#about to write, iclass 4, count 0 2006.238.07:34:41.17#ibcon#wrote, iclass 4, count 0 2006.238.07:34:41.17#ibcon#about to read 3, iclass 4, count 0 2006.238.07:34:41.19#ibcon#read 3, iclass 4, count 0 2006.238.07:34:41.19#ibcon#about to read 4, iclass 4, count 0 2006.238.07:34:41.19#ibcon#read 4, iclass 4, count 0 2006.238.07:34:41.19#ibcon#about to read 5, iclass 4, count 0 2006.238.07:34:41.19#ibcon#read 5, iclass 4, count 0 2006.238.07:34:41.19#ibcon#about to read 6, iclass 4, count 0 2006.238.07:34:41.19#ibcon#read 6, iclass 4, count 0 2006.238.07:34:41.19#ibcon#end of sib2, iclass 4, count 0 2006.238.07:34:41.19#ibcon#*mode == 0, iclass 4, count 0 2006.238.07:34:41.19#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.07:34:41.19#ibcon#[27=USB\r\n] 2006.238.07:34:41.19#ibcon#*before write, iclass 4, count 0 2006.238.07:34:41.19#ibcon#enter sib2, iclass 4, count 0 2006.238.07:34:41.19#ibcon#flushed, iclass 4, count 0 2006.238.07:34:41.19#ibcon#about to write, iclass 4, count 0 2006.238.07:34:41.19#ibcon#wrote, iclass 4, count 0 2006.238.07:34:41.19#ibcon#about to read 3, iclass 4, count 0 2006.238.07:34:41.22#ibcon#read 3, iclass 4, count 0 2006.238.07:34:41.22#ibcon#about to read 4, iclass 4, count 0 2006.238.07:34:41.22#ibcon#read 4, iclass 4, count 0 2006.238.07:34:41.22#ibcon#about to read 5, iclass 4, count 0 2006.238.07:34:41.22#ibcon#read 5, iclass 4, count 0 2006.238.07:34:41.22#ibcon#about to read 6, iclass 4, count 0 2006.238.07:34:41.22#ibcon#read 6, iclass 4, count 0 2006.238.07:34:41.22#ibcon#end of sib2, iclass 4, count 0 2006.238.07:34:41.22#ibcon#*after write, iclass 4, count 0 2006.238.07:34:41.22#ibcon#*before return 0, iclass 4, count 0 2006.238.07:34:41.22#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:34:41.22#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:34:41.22#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.07:34:41.22#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.07:34:41.22$vc4f8/vblo=3,656.99 2006.238.07:34:41.22#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.238.07:34:41.22#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.238.07:34:41.22#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:41.22#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:34:41.22#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:34:41.22#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:34:41.22#ibcon#enter wrdev, iclass 6, count 0 2006.238.07:34:41.22#ibcon#first serial, iclass 6, count 0 2006.238.07:34:41.22#ibcon#enter sib2, iclass 6, count 0 2006.238.07:34:41.22#ibcon#flushed, iclass 6, count 0 2006.238.07:34:41.22#ibcon#about to write, iclass 6, count 0 2006.238.07:34:41.22#ibcon#wrote, iclass 6, count 0 2006.238.07:34:41.22#ibcon#about to read 3, iclass 6, count 0 2006.238.07:34:41.24#ibcon#read 3, iclass 6, count 0 2006.238.07:34:41.24#ibcon#about to read 4, iclass 6, count 0 2006.238.07:34:41.24#ibcon#read 4, iclass 6, count 0 2006.238.07:34:41.24#ibcon#about to read 5, iclass 6, count 0 2006.238.07:34:41.24#ibcon#read 5, iclass 6, count 0 2006.238.07:34:41.24#ibcon#about to read 6, iclass 6, count 0 2006.238.07:34:41.24#ibcon#read 6, iclass 6, count 0 2006.238.07:34:41.24#ibcon#end of sib2, iclass 6, count 0 2006.238.07:34:41.24#ibcon#*mode == 0, iclass 6, count 0 2006.238.07:34:41.24#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.07:34:41.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:34:41.24#ibcon#*before write, iclass 6, count 0 2006.238.07:34:41.24#ibcon#enter sib2, iclass 6, count 0 2006.238.07:34:41.24#ibcon#flushed, iclass 6, count 0 2006.238.07:34:41.24#ibcon#about to write, iclass 6, count 0 2006.238.07:34:41.24#ibcon#wrote, iclass 6, count 0 2006.238.07:34:41.24#ibcon#about to read 3, iclass 6, count 0 2006.238.07:34:41.28#ibcon#read 3, iclass 6, count 0 2006.238.07:34:41.28#ibcon#about to read 4, iclass 6, count 0 2006.238.07:34:41.28#ibcon#read 4, iclass 6, count 0 2006.238.07:34:41.28#ibcon#about to read 5, iclass 6, count 0 2006.238.07:34:41.28#ibcon#read 5, iclass 6, count 0 2006.238.07:34:41.28#ibcon#about to read 6, iclass 6, count 0 2006.238.07:34:41.28#ibcon#read 6, iclass 6, count 0 2006.238.07:34:41.28#ibcon#end of sib2, iclass 6, count 0 2006.238.07:34:41.28#ibcon#*after write, iclass 6, count 0 2006.238.07:34:41.28#ibcon#*before return 0, iclass 6, count 0 2006.238.07:34:41.28#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:34:41.28#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:34:41.28#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.07:34:41.28#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.07:34:41.28$vc4f8/vb=3,4 2006.238.07:34:41.28#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.238.07:34:41.28#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.238.07:34:41.28#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:41.28#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:34:41.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:34:41.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:34:41.34#ibcon#enter wrdev, iclass 10, count 2 2006.238.07:34:41.34#ibcon#first serial, iclass 10, count 2 2006.238.07:34:41.34#ibcon#enter sib2, iclass 10, count 2 2006.238.07:34:41.34#ibcon#flushed, iclass 10, count 2 2006.238.07:34:41.34#ibcon#about to write, iclass 10, count 2 2006.238.07:34:41.34#ibcon#wrote, iclass 10, count 2 2006.238.07:34:41.34#ibcon#about to read 3, iclass 10, count 2 2006.238.07:34:41.36#ibcon#read 3, iclass 10, count 2 2006.238.07:34:41.36#ibcon#about to read 4, iclass 10, count 2 2006.238.07:34:41.36#ibcon#read 4, iclass 10, count 2 2006.238.07:34:41.36#ibcon#about to read 5, iclass 10, count 2 2006.238.07:34:41.36#ibcon#read 5, iclass 10, count 2 2006.238.07:34:41.36#ibcon#about to read 6, iclass 10, count 2 2006.238.07:34:41.36#ibcon#read 6, iclass 10, count 2 2006.238.07:34:41.36#ibcon#end of sib2, iclass 10, count 2 2006.238.07:34:41.36#ibcon#*mode == 0, iclass 10, count 2 2006.238.07:34:41.36#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.238.07:34:41.36#ibcon#[27=AT03-04\r\n] 2006.238.07:34:41.36#ibcon#*before write, iclass 10, count 2 2006.238.07:34:41.36#ibcon#enter sib2, iclass 10, count 2 2006.238.07:34:41.36#ibcon#flushed, iclass 10, count 2 2006.238.07:34:41.36#ibcon#about to write, iclass 10, count 2 2006.238.07:34:41.36#ibcon#wrote, iclass 10, count 2 2006.238.07:34:41.36#ibcon#about to read 3, iclass 10, count 2 2006.238.07:34:41.39#ibcon#read 3, iclass 10, count 2 2006.238.07:34:41.39#ibcon#about to read 4, iclass 10, count 2 2006.238.07:34:41.39#ibcon#read 4, iclass 10, count 2 2006.238.07:34:41.39#ibcon#about to read 5, iclass 10, count 2 2006.238.07:34:41.39#ibcon#read 5, iclass 10, count 2 2006.238.07:34:41.39#ibcon#about to read 6, iclass 10, count 2 2006.238.07:34:41.39#ibcon#read 6, iclass 10, count 2 2006.238.07:34:41.39#ibcon#end of sib2, iclass 10, count 2 2006.238.07:34:41.39#ibcon#*after write, iclass 10, count 2 2006.238.07:34:41.39#ibcon#*before return 0, iclass 10, count 2 2006.238.07:34:41.39#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:34:41.39#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:34:41.39#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.238.07:34:41.39#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:41.39#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:34:41.51#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:34:41.51#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:34:41.51#ibcon#enter wrdev, iclass 10, count 0 2006.238.07:34:41.51#ibcon#first serial, iclass 10, count 0 2006.238.07:34:41.51#ibcon#enter sib2, iclass 10, count 0 2006.238.07:34:41.51#ibcon#flushed, iclass 10, count 0 2006.238.07:34:41.51#ibcon#about to write, iclass 10, count 0 2006.238.07:34:41.51#ibcon#wrote, iclass 10, count 0 2006.238.07:34:41.51#ibcon#about to read 3, iclass 10, count 0 2006.238.07:34:41.53#ibcon#read 3, iclass 10, count 0 2006.238.07:34:41.53#ibcon#about to read 4, iclass 10, count 0 2006.238.07:34:41.53#ibcon#read 4, iclass 10, count 0 2006.238.07:34:41.53#ibcon#about to read 5, iclass 10, count 0 2006.238.07:34:41.53#ibcon#read 5, iclass 10, count 0 2006.238.07:34:41.53#ibcon#about to read 6, iclass 10, count 0 2006.238.07:34:41.53#ibcon#read 6, iclass 10, count 0 2006.238.07:34:41.53#ibcon#end of sib2, iclass 10, count 0 2006.238.07:34:41.53#ibcon#*mode == 0, iclass 10, count 0 2006.238.07:34:41.53#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.07:34:41.53#ibcon#[27=USB\r\n] 2006.238.07:34:41.53#ibcon#*before write, iclass 10, count 0 2006.238.07:34:41.53#ibcon#enter sib2, iclass 10, count 0 2006.238.07:34:41.53#ibcon#flushed, iclass 10, count 0 2006.238.07:34:41.53#ibcon#about to write, iclass 10, count 0 2006.238.07:34:41.53#ibcon#wrote, iclass 10, count 0 2006.238.07:34:41.53#ibcon#about to read 3, iclass 10, count 0 2006.238.07:34:41.56#ibcon#read 3, iclass 10, count 0 2006.238.07:34:41.56#ibcon#about to read 4, iclass 10, count 0 2006.238.07:34:41.56#ibcon#read 4, iclass 10, count 0 2006.238.07:34:41.56#ibcon#about to read 5, iclass 10, count 0 2006.238.07:34:41.56#ibcon#read 5, iclass 10, count 0 2006.238.07:34:41.56#ibcon#about to read 6, iclass 10, count 0 2006.238.07:34:41.56#ibcon#read 6, iclass 10, count 0 2006.238.07:34:41.56#ibcon#end of sib2, iclass 10, count 0 2006.238.07:34:41.56#ibcon#*after write, iclass 10, count 0 2006.238.07:34:41.56#ibcon#*before return 0, iclass 10, count 0 2006.238.07:34:41.56#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:34:41.56#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:34:41.56#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.07:34:41.56#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.07:34:41.56$vc4f8/vblo=4,712.99 2006.238.07:34:41.56#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.238.07:34:41.56#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.238.07:34:41.56#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:41.56#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:34:41.56#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:34:41.56#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:34:41.56#ibcon#enter wrdev, iclass 12, count 0 2006.238.07:34:41.56#ibcon#first serial, iclass 12, count 0 2006.238.07:34:41.56#ibcon#enter sib2, iclass 12, count 0 2006.238.07:34:41.56#ibcon#flushed, iclass 12, count 0 2006.238.07:34:41.56#ibcon#about to write, iclass 12, count 0 2006.238.07:34:41.56#ibcon#wrote, iclass 12, count 0 2006.238.07:34:41.56#ibcon#about to read 3, iclass 12, count 0 2006.238.07:34:41.58#ibcon#read 3, iclass 12, count 0 2006.238.07:34:41.58#ibcon#about to read 4, iclass 12, count 0 2006.238.07:34:41.58#ibcon#read 4, iclass 12, count 0 2006.238.07:34:41.58#ibcon#about to read 5, iclass 12, count 0 2006.238.07:34:41.58#ibcon#read 5, iclass 12, count 0 2006.238.07:34:41.58#ibcon#about to read 6, iclass 12, count 0 2006.238.07:34:41.58#ibcon#read 6, iclass 12, count 0 2006.238.07:34:41.58#ibcon#end of sib2, iclass 12, count 0 2006.238.07:34:41.58#ibcon#*mode == 0, iclass 12, count 0 2006.238.07:34:41.58#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.07:34:41.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:34:41.58#ibcon#*before write, iclass 12, count 0 2006.238.07:34:41.58#ibcon#enter sib2, iclass 12, count 0 2006.238.07:34:41.58#ibcon#flushed, iclass 12, count 0 2006.238.07:34:41.58#ibcon#about to write, iclass 12, count 0 2006.238.07:34:41.58#ibcon#wrote, iclass 12, count 0 2006.238.07:34:41.58#ibcon#about to read 3, iclass 12, count 0 2006.238.07:34:41.62#ibcon#read 3, iclass 12, count 0 2006.238.07:34:41.62#ibcon#about to read 4, iclass 12, count 0 2006.238.07:34:41.62#ibcon#read 4, iclass 12, count 0 2006.238.07:34:41.62#ibcon#about to read 5, iclass 12, count 0 2006.238.07:34:41.62#ibcon#read 5, iclass 12, count 0 2006.238.07:34:41.62#ibcon#about to read 6, iclass 12, count 0 2006.238.07:34:41.62#ibcon#read 6, iclass 12, count 0 2006.238.07:34:41.62#ibcon#end of sib2, iclass 12, count 0 2006.238.07:34:41.62#ibcon#*after write, iclass 12, count 0 2006.238.07:34:41.62#ibcon#*before return 0, iclass 12, count 0 2006.238.07:34:41.62#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:34:41.62#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:34:41.62#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.07:34:41.62#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.07:34:41.62$vc4f8/vb=4,4 2006.238.07:34:41.62#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.238.07:34:41.62#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.238.07:34:41.62#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:41.62#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:34:41.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:34:41.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:34:41.68#ibcon#enter wrdev, iclass 14, count 2 2006.238.07:34:41.68#ibcon#first serial, iclass 14, count 2 2006.238.07:34:41.68#ibcon#enter sib2, iclass 14, count 2 2006.238.07:34:41.68#ibcon#flushed, iclass 14, count 2 2006.238.07:34:41.68#ibcon#about to write, iclass 14, count 2 2006.238.07:34:41.68#ibcon#wrote, iclass 14, count 2 2006.238.07:34:41.68#ibcon#about to read 3, iclass 14, count 2 2006.238.07:34:41.70#ibcon#read 3, iclass 14, count 2 2006.238.07:34:41.70#ibcon#about to read 4, iclass 14, count 2 2006.238.07:34:41.70#ibcon#read 4, iclass 14, count 2 2006.238.07:34:41.70#ibcon#about to read 5, iclass 14, count 2 2006.238.07:34:41.70#ibcon#read 5, iclass 14, count 2 2006.238.07:34:41.70#ibcon#about to read 6, iclass 14, count 2 2006.238.07:34:41.70#ibcon#read 6, iclass 14, count 2 2006.238.07:34:41.70#ibcon#end of sib2, iclass 14, count 2 2006.238.07:34:41.70#ibcon#*mode == 0, iclass 14, count 2 2006.238.07:34:41.70#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.238.07:34:41.70#ibcon#[27=AT04-04\r\n] 2006.238.07:34:41.70#ibcon#*before write, iclass 14, count 2 2006.238.07:34:41.70#ibcon#enter sib2, iclass 14, count 2 2006.238.07:34:41.70#ibcon#flushed, iclass 14, count 2 2006.238.07:34:41.70#ibcon#about to write, iclass 14, count 2 2006.238.07:34:41.70#ibcon#wrote, iclass 14, count 2 2006.238.07:34:41.70#ibcon#about to read 3, iclass 14, count 2 2006.238.07:34:41.73#ibcon#read 3, iclass 14, count 2 2006.238.07:34:41.73#ibcon#about to read 4, iclass 14, count 2 2006.238.07:34:41.73#ibcon#read 4, iclass 14, count 2 2006.238.07:34:41.73#ibcon#about to read 5, iclass 14, count 2 2006.238.07:34:41.73#ibcon#read 5, iclass 14, count 2 2006.238.07:34:41.73#ibcon#about to read 6, iclass 14, count 2 2006.238.07:34:41.73#ibcon#read 6, iclass 14, count 2 2006.238.07:34:41.73#ibcon#end of sib2, iclass 14, count 2 2006.238.07:34:41.73#ibcon#*after write, iclass 14, count 2 2006.238.07:34:41.73#ibcon#*before return 0, iclass 14, count 2 2006.238.07:34:41.73#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:34:41.73#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:34:41.73#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.238.07:34:41.73#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:41.73#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:34:41.85#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:34:41.85#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:34:41.85#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:34:41.85#ibcon#first serial, iclass 14, count 0 2006.238.07:34:41.85#ibcon#enter sib2, iclass 14, count 0 2006.238.07:34:41.85#ibcon#flushed, iclass 14, count 0 2006.238.07:34:41.85#ibcon#about to write, iclass 14, count 0 2006.238.07:34:41.85#ibcon#wrote, iclass 14, count 0 2006.238.07:34:41.85#ibcon#about to read 3, iclass 14, count 0 2006.238.07:34:41.87#ibcon#read 3, iclass 14, count 0 2006.238.07:34:41.87#ibcon#about to read 4, iclass 14, count 0 2006.238.07:34:41.87#ibcon#read 4, iclass 14, count 0 2006.238.07:34:41.87#ibcon#about to read 5, iclass 14, count 0 2006.238.07:34:41.87#ibcon#read 5, iclass 14, count 0 2006.238.07:34:41.87#ibcon#about to read 6, iclass 14, count 0 2006.238.07:34:41.87#ibcon#read 6, iclass 14, count 0 2006.238.07:34:41.87#ibcon#end of sib2, iclass 14, count 0 2006.238.07:34:41.87#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:34:41.87#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:34:41.87#ibcon#[27=USB\r\n] 2006.238.07:34:41.87#ibcon#*before write, iclass 14, count 0 2006.238.07:34:41.87#ibcon#enter sib2, iclass 14, count 0 2006.238.07:34:41.87#ibcon#flushed, iclass 14, count 0 2006.238.07:34:41.87#ibcon#about to write, iclass 14, count 0 2006.238.07:34:41.87#ibcon#wrote, iclass 14, count 0 2006.238.07:34:41.87#ibcon#about to read 3, iclass 14, count 0 2006.238.07:34:41.90#ibcon#read 3, iclass 14, count 0 2006.238.07:34:41.90#ibcon#about to read 4, iclass 14, count 0 2006.238.07:34:41.90#ibcon#read 4, iclass 14, count 0 2006.238.07:34:41.90#ibcon#about to read 5, iclass 14, count 0 2006.238.07:34:41.90#ibcon#read 5, iclass 14, count 0 2006.238.07:34:41.90#ibcon#about to read 6, iclass 14, count 0 2006.238.07:34:41.90#ibcon#read 6, iclass 14, count 0 2006.238.07:34:41.90#ibcon#end of sib2, iclass 14, count 0 2006.238.07:34:41.90#ibcon#*after write, iclass 14, count 0 2006.238.07:34:41.90#ibcon#*before return 0, iclass 14, count 0 2006.238.07:34:41.90#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:34:41.90#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:34:41.90#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:34:41.90#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:34:41.90$vc4f8/vblo=5,744.99 2006.238.07:34:41.90#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.07:34:41.90#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.07:34:41.90#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:41.90#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:34:41.90#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:34:41.90#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:34:41.90#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:34:41.90#ibcon#first serial, iclass 16, count 0 2006.238.07:34:41.90#ibcon#enter sib2, iclass 16, count 0 2006.238.07:34:41.90#ibcon#flushed, iclass 16, count 0 2006.238.07:34:41.90#ibcon#about to write, iclass 16, count 0 2006.238.07:34:41.90#ibcon#wrote, iclass 16, count 0 2006.238.07:34:41.90#ibcon#about to read 3, iclass 16, count 0 2006.238.07:34:41.92#ibcon#read 3, iclass 16, count 0 2006.238.07:34:41.92#ibcon#about to read 4, iclass 16, count 0 2006.238.07:34:41.92#ibcon#read 4, iclass 16, count 0 2006.238.07:34:41.92#ibcon#about to read 5, iclass 16, count 0 2006.238.07:34:41.92#ibcon#read 5, iclass 16, count 0 2006.238.07:34:41.92#ibcon#about to read 6, iclass 16, count 0 2006.238.07:34:41.92#ibcon#read 6, iclass 16, count 0 2006.238.07:34:41.92#ibcon#end of sib2, iclass 16, count 0 2006.238.07:34:41.92#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:34:41.92#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:34:41.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:34:41.92#ibcon#*before write, iclass 16, count 0 2006.238.07:34:41.92#ibcon#enter sib2, iclass 16, count 0 2006.238.07:34:41.92#ibcon#flushed, iclass 16, count 0 2006.238.07:34:41.92#ibcon#about to write, iclass 16, count 0 2006.238.07:34:41.92#ibcon#wrote, iclass 16, count 0 2006.238.07:34:41.92#ibcon#about to read 3, iclass 16, count 0 2006.238.07:34:41.96#ibcon#read 3, iclass 16, count 0 2006.238.07:34:41.96#ibcon#about to read 4, iclass 16, count 0 2006.238.07:34:41.96#ibcon#read 4, iclass 16, count 0 2006.238.07:34:41.96#ibcon#about to read 5, iclass 16, count 0 2006.238.07:34:41.96#ibcon#read 5, iclass 16, count 0 2006.238.07:34:41.96#ibcon#about to read 6, iclass 16, count 0 2006.238.07:34:41.96#ibcon#read 6, iclass 16, count 0 2006.238.07:34:41.96#ibcon#end of sib2, iclass 16, count 0 2006.238.07:34:41.96#ibcon#*after write, iclass 16, count 0 2006.238.07:34:41.96#ibcon#*before return 0, iclass 16, count 0 2006.238.07:34:41.96#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:34:41.96#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:34:41.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:34:41.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:34:41.96$vc4f8/vb=5,4 2006.238.07:34:41.96#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.238.07:34:41.96#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.238.07:34:41.96#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:41.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:34:42.03#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:34:42.03#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:34:42.03#ibcon#enter wrdev, iclass 18, count 2 2006.238.07:34:42.03#ibcon#first serial, iclass 18, count 2 2006.238.07:34:42.03#ibcon#enter sib2, iclass 18, count 2 2006.238.07:34:42.03#ibcon#flushed, iclass 18, count 2 2006.238.07:34:42.03#ibcon#about to write, iclass 18, count 2 2006.238.07:34:42.03#ibcon#wrote, iclass 18, count 2 2006.238.07:34:42.03#ibcon#about to read 3, iclass 18, count 2 2006.238.07:34:42.04#ibcon#read 3, iclass 18, count 2 2006.238.07:34:42.04#ibcon#about to read 4, iclass 18, count 2 2006.238.07:34:42.04#ibcon#read 4, iclass 18, count 2 2006.238.07:34:42.04#ibcon#about to read 5, iclass 18, count 2 2006.238.07:34:42.04#ibcon#read 5, iclass 18, count 2 2006.238.07:34:42.04#ibcon#about to read 6, iclass 18, count 2 2006.238.07:34:42.04#ibcon#read 6, iclass 18, count 2 2006.238.07:34:42.04#ibcon#end of sib2, iclass 18, count 2 2006.238.07:34:42.04#ibcon#*mode == 0, iclass 18, count 2 2006.238.07:34:42.04#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.238.07:34:42.04#ibcon#[27=AT05-04\r\n] 2006.238.07:34:42.04#ibcon#*before write, iclass 18, count 2 2006.238.07:34:42.04#ibcon#enter sib2, iclass 18, count 2 2006.238.07:34:42.04#ibcon#flushed, iclass 18, count 2 2006.238.07:34:42.04#ibcon#about to write, iclass 18, count 2 2006.238.07:34:42.04#ibcon#wrote, iclass 18, count 2 2006.238.07:34:42.04#ibcon#about to read 3, iclass 18, count 2 2006.238.07:34:42.08#ibcon#read 3, iclass 18, count 2 2006.238.07:34:42.08#ibcon#about to read 4, iclass 18, count 2 2006.238.07:34:42.08#ibcon#read 4, iclass 18, count 2 2006.238.07:34:42.08#ibcon#about to read 5, iclass 18, count 2 2006.238.07:34:42.08#ibcon#read 5, iclass 18, count 2 2006.238.07:34:42.08#ibcon#about to read 6, iclass 18, count 2 2006.238.07:34:42.08#ibcon#read 6, iclass 18, count 2 2006.238.07:34:42.08#ibcon#end of sib2, iclass 18, count 2 2006.238.07:34:42.08#ibcon#*after write, iclass 18, count 2 2006.238.07:34:42.08#ibcon#*before return 0, iclass 18, count 2 2006.238.07:34:42.08#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:34:42.08#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:34:42.08#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.238.07:34:42.08#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:42.08#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:34:42.20#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:34:42.20#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:34:42.20#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:34:42.20#ibcon#first serial, iclass 18, count 0 2006.238.07:34:42.20#ibcon#enter sib2, iclass 18, count 0 2006.238.07:34:42.20#ibcon#flushed, iclass 18, count 0 2006.238.07:34:42.20#ibcon#about to write, iclass 18, count 0 2006.238.07:34:42.20#ibcon#wrote, iclass 18, count 0 2006.238.07:34:42.20#ibcon#about to read 3, iclass 18, count 0 2006.238.07:34:42.24#ibcon#read 3, iclass 18, count 0 2006.238.07:34:42.24#ibcon#about to read 4, iclass 18, count 0 2006.238.07:34:42.24#ibcon#read 4, iclass 18, count 0 2006.238.07:34:42.24#ibcon#about to read 5, iclass 18, count 0 2006.238.07:34:42.24#ibcon#read 5, iclass 18, count 0 2006.238.07:34:42.24#ibcon#about to read 6, iclass 18, count 0 2006.238.07:34:42.24#ibcon#read 6, iclass 18, count 0 2006.238.07:34:42.24#ibcon#end of sib2, iclass 18, count 0 2006.238.07:34:42.24#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:34:42.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:34:42.24#ibcon#[27=USB\r\n] 2006.238.07:34:42.24#ibcon#*before write, iclass 18, count 0 2006.238.07:34:42.24#ibcon#enter sib2, iclass 18, count 0 2006.238.07:34:42.24#ibcon#flushed, iclass 18, count 0 2006.238.07:34:42.24#ibcon#about to write, iclass 18, count 0 2006.238.07:34:42.24#ibcon#wrote, iclass 18, count 0 2006.238.07:34:42.24#ibcon#about to read 3, iclass 18, count 0 2006.238.07:34:42.27#ibcon#read 3, iclass 18, count 0 2006.238.07:34:42.27#ibcon#about to read 4, iclass 18, count 0 2006.238.07:34:42.27#ibcon#read 4, iclass 18, count 0 2006.238.07:34:42.27#ibcon#about to read 5, iclass 18, count 0 2006.238.07:34:42.27#ibcon#read 5, iclass 18, count 0 2006.238.07:34:42.27#ibcon#about to read 6, iclass 18, count 0 2006.238.07:34:42.27#ibcon#read 6, iclass 18, count 0 2006.238.07:34:42.27#ibcon#end of sib2, iclass 18, count 0 2006.238.07:34:42.27#ibcon#*after write, iclass 18, count 0 2006.238.07:34:42.27#ibcon#*before return 0, iclass 18, count 0 2006.238.07:34:42.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:34:42.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:34:42.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:34:42.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:34:42.27$vc4f8/vblo=6,752.99 2006.238.07:34:42.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.07:34:42.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.07:34:42.27#ibcon#ireg 17 cls_cnt 0 2006.238.07:34:42.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:34:42.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:34:42.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:34:42.27#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:34:42.27#ibcon#first serial, iclass 20, count 0 2006.238.07:34:42.27#ibcon#enter sib2, iclass 20, count 0 2006.238.07:34:42.27#ibcon#flushed, iclass 20, count 0 2006.238.07:34:42.27#ibcon#about to write, iclass 20, count 0 2006.238.07:34:42.27#ibcon#wrote, iclass 20, count 0 2006.238.07:34:42.27#ibcon#about to read 3, iclass 20, count 0 2006.238.07:34:42.29#ibcon#read 3, iclass 20, count 0 2006.238.07:34:42.29#ibcon#about to read 4, iclass 20, count 0 2006.238.07:34:42.29#ibcon#read 4, iclass 20, count 0 2006.238.07:34:42.29#ibcon#about to read 5, iclass 20, count 0 2006.238.07:34:42.29#ibcon#read 5, iclass 20, count 0 2006.238.07:34:42.29#ibcon#about to read 6, iclass 20, count 0 2006.238.07:34:42.29#ibcon#read 6, iclass 20, count 0 2006.238.07:34:42.29#ibcon#end of sib2, iclass 20, count 0 2006.238.07:34:42.29#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:34:42.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:34:42.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:34:42.29#ibcon#*before write, iclass 20, count 0 2006.238.07:34:42.29#ibcon#enter sib2, iclass 20, count 0 2006.238.07:34:42.29#ibcon#flushed, iclass 20, count 0 2006.238.07:34:42.29#ibcon#about to write, iclass 20, count 0 2006.238.07:34:42.29#ibcon#wrote, iclass 20, count 0 2006.238.07:34:42.29#ibcon#about to read 3, iclass 20, count 0 2006.238.07:34:42.33#ibcon#read 3, iclass 20, count 0 2006.238.07:34:42.33#ibcon#about to read 4, iclass 20, count 0 2006.238.07:34:42.33#ibcon#read 4, iclass 20, count 0 2006.238.07:34:42.33#ibcon#about to read 5, iclass 20, count 0 2006.238.07:34:42.33#ibcon#read 5, iclass 20, count 0 2006.238.07:34:42.33#ibcon#about to read 6, iclass 20, count 0 2006.238.07:34:42.33#ibcon#read 6, iclass 20, count 0 2006.238.07:34:42.33#ibcon#end of sib2, iclass 20, count 0 2006.238.07:34:42.33#ibcon#*after write, iclass 20, count 0 2006.238.07:34:42.33#ibcon#*before return 0, iclass 20, count 0 2006.238.07:34:42.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:34:42.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:34:42.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:34:42.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:34:42.33$vc4f8/vb=6,4 2006.238.07:34:42.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.238.07:34:42.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.238.07:34:42.33#ibcon#ireg 11 cls_cnt 2 2006.238.07:34:42.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:34:42.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:34:42.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:34:42.39#ibcon#enter wrdev, iclass 22, count 2 2006.238.07:34:42.39#ibcon#first serial, iclass 22, count 2 2006.238.07:34:42.39#ibcon#enter sib2, iclass 22, count 2 2006.238.07:34:42.39#ibcon#flushed, iclass 22, count 2 2006.238.07:34:42.39#ibcon#about to write, iclass 22, count 2 2006.238.07:34:42.39#ibcon#wrote, iclass 22, count 2 2006.238.07:34:42.39#ibcon#about to read 3, iclass 22, count 2 2006.238.07:34:42.41#ibcon#read 3, iclass 22, count 2 2006.238.07:34:42.41#ibcon#about to read 4, iclass 22, count 2 2006.238.07:34:42.41#ibcon#read 4, iclass 22, count 2 2006.238.07:34:42.41#ibcon#about to read 5, iclass 22, count 2 2006.238.07:34:42.41#ibcon#read 5, iclass 22, count 2 2006.238.07:34:42.41#ibcon#about to read 6, iclass 22, count 2 2006.238.07:34:42.41#ibcon#read 6, iclass 22, count 2 2006.238.07:34:42.41#ibcon#end of sib2, iclass 22, count 2 2006.238.07:34:42.41#ibcon#*mode == 0, iclass 22, count 2 2006.238.07:34:42.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.238.07:34:42.41#ibcon#[27=AT06-04\r\n] 2006.238.07:34:42.41#ibcon#*before write, iclass 22, count 2 2006.238.07:34:42.41#ibcon#enter sib2, iclass 22, count 2 2006.238.07:34:42.41#ibcon#flushed, iclass 22, count 2 2006.238.07:34:42.41#ibcon#about to write, iclass 22, count 2 2006.238.07:34:42.41#ibcon#wrote, iclass 22, count 2 2006.238.07:34:42.41#ibcon#about to read 3, iclass 22, count 2 2006.238.07:34:42.44#ibcon#read 3, iclass 22, count 2 2006.238.07:34:42.44#ibcon#about to read 4, iclass 22, count 2 2006.238.07:34:42.44#ibcon#read 4, iclass 22, count 2 2006.238.07:34:42.44#ibcon#about to read 5, iclass 22, count 2 2006.238.07:34:42.44#ibcon#read 5, iclass 22, count 2 2006.238.07:34:42.44#ibcon#about to read 6, iclass 22, count 2 2006.238.07:34:42.44#ibcon#read 6, iclass 22, count 2 2006.238.07:34:42.44#ibcon#end of sib2, iclass 22, count 2 2006.238.07:34:42.44#ibcon#*after write, iclass 22, count 2 2006.238.07:34:42.44#ibcon#*before return 0, iclass 22, count 2 2006.238.07:34:42.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:34:42.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:34:42.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.238.07:34:42.44#ibcon#ireg 7 cls_cnt 0 2006.238.07:34:42.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:34:42.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:34:42.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:34:42.56#ibcon#enter wrdev, iclass 22, count 0 2006.238.07:34:42.56#ibcon#first serial, iclass 22, count 0 2006.238.07:34:42.56#ibcon#enter sib2, iclass 22, count 0 2006.238.07:34:42.56#ibcon#flushed, iclass 22, count 0 2006.238.07:34:42.56#ibcon#about to write, iclass 22, count 0 2006.238.07:34:42.56#ibcon#wrote, iclass 22, count 0 2006.238.07:34:42.56#ibcon#about to read 3, iclass 22, count 0 2006.238.07:34:42.58#ibcon#read 3, iclass 22, count 0 2006.238.07:34:42.58#ibcon#about to read 4, iclass 22, count 0 2006.238.07:34:42.58#ibcon#read 4, iclass 22, count 0 2006.238.07:34:42.58#ibcon#about to read 5, iclass 22, count 0 2006.238.07:34:42.58#ibcon#read 5, iclass 22, count 0 2006.238.07:34:42.58#ibcon#about to read 6, iclass 22, count 0 2006.238.07:34:42.58#ibcon#read 6, iclass 22, count 0 2006.238.07:34:42.58#ibcon#end of sib2, iclass 22, count 0 2006.238.07:34:42.58#ibcon#*mode == 0, iclass 22, count 0 2006.238.07:34:42.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.07:34:42.58#ibcon#[27=USB\r\n] 2006.238.07:34:42.58#ibcon#*before write, iclass 22, count 0 2006.238.07:34:42.58#ibcon#enter sib2, iclass 22, count 0 2006.238.07:34:42.58#ibcon#flushed, iclass 22, count 0 2006.238.07:34:42.58#ibcon#about to write, iclass 22, count 0 2006.238.07:34:42.58#ibcon#wrote, iclass 22, count 0 2006.238.07:34:42.58#ibcon#about to read 3, iclass 22, count 0 2006.238.07:34:42.61#ibcon#read 3, iclass 22, count 0 2006.238.07:34:42.61#ibcon#about to read 4, iclass 22, count 0 2006.238.07:34:42.61#ibcon#read 4, iclass 22, count 0 2006.238.07:34:42.61#ibcon#about to read 5, iclass 22, count 0 2006.238.07:34:42.61#ibcon#read 5, iclass 22, count 0 2006.238.07:34:42.61#ibcon#about to read 6, iclass 22, count 0 2006.238.07:34:42.61#ibcon#read 6, iclass 22, count 0 2006.238.07:34:42.61#ibcon#end of sib2, iclass 22, count 0 2006.238.07:34:42.61#ibcon#*after write, iclass 22, count 0 2006.238.07:34:42.61#ibcon#*before return 0, iclass 22, count 0 2006.238.07:34:42.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:34:42.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:34:42.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.07:34:42.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.07:34:42.61$vc4f8/vabw=wide 2006.238.07:34:42.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.07:34:42.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.07:34:42.61#ibcon#ireg 8 cls_cnt 0 2006.238.07:34:42.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:34:42.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:34:42.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:34:42.61#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:34:42.61#ibcon#first serial, iclass 24, count 0 2006.238.07:34:42.61#ibcon#enter sib2, iclass 24, count 0 2006.238.07:34:42.61#ibcon#flushed, iclass 24, count 0 2006.238.07:34:42.61#ibcon#about to write, iclass 24, count 0 2006.238.07:34:42.61#ibcon#wrote, iclass 24, count 0 2006.238.07:34:42.61#ibcon#about to read 3, iclass 24, count 0 2006.238.07:34:42.63#ibcon#read 3, iclass 24, count 0 2006.238.07:34:42.63#ibcon#about to read 4, iclass 24, count 0 2006.238.07:34:42.63#ibcon#read 4, iclass 24, count 0 2006.238.07:34:42.63#ibcon#about to read 5, iclass 24, count 0 2006.238.07:34:42.63#ibcon#read 5, iclass 24, count 0 2006.238.07:34:42.63#ibcon#about to read 6, iclass 24, count 0 2006.238.07:34:42.63#ibcon#read 6, iclass 24, count 0 2006.238.07:34:42.63#ibcon#end of sib2, iclass 24, count 0 2006.238.07:34:42.63#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:34:42.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:34:42.63#ibcon#[25=BW32\r\n] 2006.238.07:34:42.63#ibcon#*before write, iclass 24, count 0 2006.238.07:34:42.63#ibcon#enter sib2, iclass 24, count 0 2006.238.07:34:42.63#ibcon#flushed, iclass 24, count 0 2006.238.07:34:42.63#ibcon#about to write, iclass 24, count 0 2006.238.07:34:42.63#ibcon#wrote, iclass 24, count 0 2006.238.07:34:42.63#ibcon#about to read 3, iclass 24, count 0 2006.238.07:34:42.66#ibcon#read 3, iclass 24, count 0 2006.238.07:34:42.66#ibcon#about to read 4, iclass 24, count 0 2006.238.07:34:42.66#ibcon#read 4, iclass 24, count 0 2006.238.07:34:42.66#ibcon#about to read 5, iclass 24, count 0 2006.238.07:34:42.66#ibcon#read 5, iclass 24, count 0 2006.238.07:34:42.66#ibcon#about to read 6, iclass 24, count 0 2006.238.07:34:42.66#ibcon#read 6, iclass 24, count 0 2006.238.07:34:42.66#ibcon#end of sib2, iclass 24, count 0 2006.238.07:34:42.66#ibcon#*after write, iclass 24, count 0 2006.238.07:34:42.66#ibcon#*before return 0, iclass 24, count 0 2006.238.07:34:42.66#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:34:42.66#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:34:42.66#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:34:42.66#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:34:42.66$vc4f8/vbbw=wide 2006.238.07:34:42.66#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.07:34:42.66#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.07:34:42.66#ibcon#ireg 8 cls_cnt 0 2006.238.07:34:42.66#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:34:42.73#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:34:42.73#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:34:42.73#ibcon#enter wrdev, iclass 26, count 0 2006.238.07:34:42.73#ibcon#first serial, iclass 26, count 0 2006.238.07:34:42.73#ibcon#enter sib2, iclass 26, count 0 2006.238.07:34:42.73#ibcon#flushed, iclass 26, count 0 2006.238.07:34:42.73#ibcon#about to write, iclass 26, count 0 2006.238.07:34:42.73#ibcon#wrote, iclass 26, count 0 2006.238.07:34:42.73#ibcon#about to read 3, iclass 26, count 0 2006.238.07:34:42.75#ibcon#read 3, iclass 26, count 0 2006.238.07:34:42.75#ibcon#about to read 4, iclass 26, count 0 2006.238.07:34:42.75#ibcon#read 4, iclass 26, count 0 2006.238.07:34:42.75#ibcon#about to read 5, iclass 26, count 0 2006.238.07:34:42.75#ibcon#read 5, iclass 26, count 0 2006.238.07:34:42.75#ibcon#about to read 6, iclass 26, count 0 2006.238.07:34:42.75#ibcon#read 6, iclass 26, count 0 2006.238.07:34:42.75#ibcon#end of sib2, iclass 26, count 0 2006.238.07:34:42.75#ibcon#*mode == 0, iclass 26, count 0 2006.238.07:34:42.75#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.07:34:42.75#ibcon#[27=BW32\r\n] 2006.238.07:34:42.75#ibcon#*before write, iclass 26, count 0 2006.238.07:34:42.75#ibcon#enter sib2, iclass 26, count 0 2006.238.07:34:42.75#ibcon#flushed, iclass 26, count 0 2006.238.07:34:42.75#ibcon#about to write, iclass 26, count 0 2006.238.07:34:42.75#ibcon#wrote, iclass 26, count 0 2006.238.07:34:42.75#ibcon#about to read 3, iclass 26, count 0 2006.238.07:34:42.78#ibcon#read 3, iclass 26, count 0 2006.238.07:34:42.78#ibcon#about to read 4, iclass 26, count 0 2006.238.07:34:42.78#ibcon#read 4, iclass 26, count 0 2006.238.07:34:42.78#ibcon#about to read 5, iclass 26, count 0 2006.238.07:34:42.78#ibcon#read 5, iclass 26, count 0 2006.238.07:34:42.78#ibcon#about to read 6, iclass 26, count 0 2006.238.07:34:42.78#ibcon#read 6, iclass 26, count 0 2006.238.07:34:42.78#ibcon#end of sib2, iclass 26, count 0 2006.238.07:34:42.78#ibcon#*after write, iclass 26, count 0 2006.238.07:34:42.78#ibcon#*before return 0, iclass 26, count 0 2006.238.07:34:42.78#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:34:42.78#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:34:42.78#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.07:34:42.78#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.07:34:42.78$4f8m12a/ifd4f 2006.238.07:34:42.78$ifd4f/lo= 2006.238.07:34:42.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:34:42.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:34:42.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:34:42.78$ifd4f/patch= 2006.238.07:34:42.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:34:42.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:34:42.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:34:42.78$4f8m12a/"form=m,16.000,1:2 2006.238.07:34:42.78$4f8m12a/"tpicd 2006.238.07:34:42.78$4f8m12a/echo=off 2006.238.07:34:42.78$4f8m12a/xlog=off 2006.238.07:34:42.78:!2006.238.07:35:10 2006.238.07:34:55.13#trakl#Source acquired 2006.238.07:34:55.13#flagr#flagr/antenna,acquired 2006.238.07:35:10.00:preob 2006.238.07:35:11.13/onsource/TRACKING 2006.238.07:35:11.13:!2006.238.07:35:20 2006.238.07:35:20.00:data_valid=on 2006.238.07:35:20.00:midob 2006.238.07:35:20.13/onsource/TRACKING 2006.238.07:35:20.13/wx/25.36,1012.2,89 2006.238.07:35:20.21/cable/+6.4195E-03 2006.238.07:35:21.30/va/01,08,usb,yes,32,33 2006.238.07:35:21.30/va/02,07,usb,yes,31,33 2006.238.07:35:21.30/va/03,07,usb,yes,30,30 2006.238.07:35:21.30/va/04,07,usb,yes,33,35 2006.238.07:35:21.30/va/05,08,usb,yes,30,32 2006.238.07:35:21.30/va/06,07,usb,yes,33,33 2006.238.07:35:21.30/va/07,07,usb,yes,33,33 2006.238.07:35:21.30/va/08,07,usb,yes,35,35 2006.238.07:35:21.53/valo/01,532.99,yes,locked 2006.238.07:35:21.53/valo/02,572.99,yes,locked 2006.238.07:35:21.53/valo/03,672.99,yes,locked 2006.238.07:35:21.53/valo/04,832.99,yes,locked 2006.238.07:35:21.53/valo/05,652.99,yes,locked 2006.238.07:35:21.53/valo/06,772.99,yes,locked 2006.238.07:35:21.53/valo/07,832.99,yes,locked 2006.238.07:35:21.53/valo/08,852.99,yes,locked 2006.238.07:35:22.62/vb/01,04,usb,yes,30,29 2006.238.07:35:22.62/vb/02,04,usb,yes,32,34 2006.238.07:35:22.62/vb/03,04,usb,yes,29,32 2006.238.07:35:22.62/vb/04,04,usb,yes,29,30 2006.238.07:35:22.62/vb/05,04,usb,yes,28,32 2006.238.07:35:22.62/vb/06,04,usb,yes,29,32 2006.238.07:35:22.62/vb/07,04,usb,yes,31,31 2006.238.07:35:22.62/vb/08,04,usb,yes,28,32 2006.238.07:35:22.85/vblo/01,632.99,yes,locked 2006.238.07:35:22.85/vblo/02,640.99,yes,locked 2006.238.07:35:22.85/vblo/03,656.99,yes,locked 2006.238.07:35:22.85/vblo/04,712.99,yes,locked 2006.238.07:35:22.85/vblo/05,744.99,yes,locked 2006.238.07:35:22.85/vblo/06,752.99,yes,locked 2006.238.07:35:22.85/vblo/07,734.99,yes,locked 2006.238.07:35:22.85/vblo/08,744.99,yes,locked 2006.238.07:35:23.00/vabw/8 2006.238.07:35:23.15/vbbw/8 2006.238.07:35:23.24/xfe/off,on,13.0 2006.238.07:35:23.61/ifatt/23,28,28,28 2006.238.07:35:24.07/fmout-gps/S +4.36E-07 2006.238.07:35:24.11:!2006.238.07:36:20 2006.238.07:36:20.00:data_valid=off 2006.238.07:36:20.00:postob 2006.238.07:36:20.22/cable/+6.4195E-03 2006.238.07:36:20.22/wx/25.35,1012.2,89 2006.238.07:36:21.08/fmout-gps/S +4.37E-07 2006.238.07:36:21.08:scan_name=238-0737,k06238,60 2006.238.07:36:21.09:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.238.07:36:21.14#flagr#flagr/antenna,new-source 2006.238.07:36:22.14:checkk5 2006.238.07:36:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:36:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:36:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:36:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:36:24.02/chk_obsdata//k5ts1/T2380735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:36:24.40/chk_obsdata//k5ts2/T2380735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:36:24.76/chk_obsdata//k5ts3/T2380735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:36:25.14/chk_obsdata//k5ts4/T2380735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:36:25.83/k5log//k5ts1_log_newline 2006.238.07:36:26.52/k5log//k5ts2_log_newline 2006.238.07:36:27.22/k5log//k5ts3_log_newline 2006.238.07:36:27.91/k5log//k5ts4_log_newline 2006.238.07:36:27.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:36:27.93:4f8m12a=1 2006.238.07:36:27.93$4f8m12a/echo=on 2006.238.07:36:27.93$4f8m12a/pcalon 2006.238.07:36:27.93$pcalon/"no phase cal control is implemented here 2006.238.07:36:27.93$4f8m12a/"tpicd=stop 2006.238.07:36:27.93$4f8m12a/vc4f8 2006.238.07:36:27.93$vc4f8/valo=1,532.99 2006.238.07:36:27.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.07:36:27.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.07:36:27.94#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:27.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:36:27.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:36:27.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:36:27.94#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:36:27.94#ibcon#first serial, iclass 33, count 0 2006.238.07:36:27.94#ibcon#enter sib2, iclass 33, count 0 2006.238.07:36:27.94#ibcon#flushed, iclass 33, count 0 2006.238.07:36:27.94#ibcon#about to write, iclass 33, count 0 2006.238.07:36:27.94#ibcon#wrote, iclass 33, count 0 2006.238.07:36:27.94#ibcon#about to read 3, iclass 33, count 0 2006.238.07:36:27.95#ibcon#read 3, iclass 33, count 0 2006.238.07:36:27.95#ibcon#about to read 4, iclass 33, count 0 2006.238.07:36:27.95#ibcon#read 4, iclass 33, count 0 2006.238.07:36:27.95#ibcon#about to read 5, iclass 33, count 0 2006.238.07:36:27.95#ibcon#read 5, iclass 33, count 0 2006.238.07:36:27.95#ibcon#about to read 6, iclass 33, count 0 2006.238.07:36:27.95#ibcon#read 6, iclass 33, count 0 2006.238.07:36:27.95#ibcon#end of sib2, iclass 33, count 0 2006.238.07:36:27.95#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:36:27.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:36:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:36:27.95#ibcon#*before write, iclass 33, count 0 2006.238.07:36:27.95#ibcon#enter sib2, iclass 33, count 0 2006.238.07:36:27.95#ibcon#flushed, iclass 33, count 0 2006.238.07:36:27.95#ibcon#about to write, iclass 33, count 0 2006.238.07:36:27.95#ibcon#wrote, iclass 33, count 0 2006.238.07:36:27.95#ibcon#about to read 3, iclass 33, count 0 2006.238.07:36:28.00#ibcon#read 3, iclass 33, count 0 2006.238.07:36:28.00#ibcon#about to read 4, iclass 33, count 0 2006.238.07:36:28.00#ibcon#read 4, iclass 33, count 0 2006.238.07:36:28.00#ibcon#about to read 5, iclass 33, count 0 2006.238.07:36:28.00#ibcon#read 5, iclass 33, count 0 2006.238.07:36:28.00#ibcon#about to read 6, iclass 33, count 0 2006.238.07:36:28.00#ibcon#read 6, iclass 33, count 0 2006.238.07:36:28.00#ibcon#end of sib2, iclass 33, count 0 2006.238.07:36:28.00#ibcon#*after write, iclass 33, count 0 2006.238.07:36:28.00#ibcon#*before return 0, iclass 33, count 0 2006.238.07:36:28.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:36:28.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:36:28.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:36:28.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:36:28.00$vc4f8/va=1,8 2006.238.07:36:28.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.238.07:36:28.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.238.07:36:28.00#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:28.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:36:28.00#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:36:28.00#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:36:28.00#ibcon#enter wrdev, iclass 35, count 2 2006.238.07:36:28.00#ibcon#first serial, iclass 35, count 2 2006.238.07:36:28.00#ibcon#enter sib2, iclass 35, count 2 2006.238.07:36:28.00#ibcon#flushed, iclass 35, count 2 2006.238.07:36:28.00#ibcon#about to write, iclass 35, count 2 2006.238.07:36:28.00#ibcon#wrote, iclass 35, count 2 2006.238.07:36:28.00#ibcon#about to read 3, iclass 35, count 2 2006.238.07:36:28.02#ibcon#read 3, iclass 35, count 2 2006.238.07:36:28.02#ibcon#about to read 4, iclass 35, count 2 2006.238.07:36:28.02#ibcon#read 4, iclass 35, count 2 2006.238.07:36:28.02#ibcon#about to read 5, iclass 35, count 2 2006.238.07:36:28.02#ibcon#read 5, iclass 35, count 2 2006.238.07:36:28.02#ibcon#about to read 6, iclass 35, count 2 2006.238.07:36:28.02#ibcon#read 6, iclass 35, count 2 2006.238.07:36:28.02#ibcon#end of sib2, iclass 35, count 2 2006.238.07:36:28.02#ibcon#*mode == 0, iclass 35, count 2 2006.238.07:36:28.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.238.07:36:28.02#ibcon#[25=AT01-08\r\n] 2006.238.07:36:28.02#ibcon#*before write, iclass 35, count 2 2006.238.07:36:28.02#ibcon#enter sib2, iclass 35, count 2 2006.238.07:36:28.02#ibcon#flushed, iclass 35, count 2 2006.238.07:36:28.02#ibcon#about to write, iclass 35, count 2 2006.238.07:36:28.02#ibcon#wrote, iclass 35, count 2 2006.238.07:36:28.02#ibcon#about to read 3, iclass 35, count 2 2006.238.07:36:28.05#ibcon#read 3, iclass 35, count 2 2006.238.07:36:28.05#ibcon#about to read 4, iclass 35, count 2 2006.238.07:36:28.05#ibcon#read 4, iclass 35, count 2 2006.238.07:36:28.05#ibcon#about to read 5, iclass 35, count 2 2006.238.07:36:28.05#ibcon#read 5, iclass 35, count 2 2006.238.07:36:28.05#ibcon#about to read 6, iclass 35, count 2 2006.238.07:36:28.05#ibcon#read 6, iclass 35, count 2 2006.238.07:36:28.05#ibcon#end of sib2, iclass 35, count 2 2006.238.07:36:28.05#ibcon#*after write, iclass 35, count 2 2006.238.07:36:28.05#ibcon#*before return 0, iclass 35, count 2 2006.238.07:36:28.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:36:28.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:36:28.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.238.07:36:28.05#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:28.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:36:28.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:36:28.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:36:28.17#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:36:28.17#ibcon#first serial, iclass 35, count 0 2006.238.07:36:28.17#ibcon#enter sib2, iclass 35, count 0 2006.238.07:36:28.17#ibcon#flushed, iclass 35, count 0 2006.238.07:36:28.17#ibcon#about to write, iclass 35, count 0 2006.238.07:36:28.17#ibcon#wrote, iclass 35, count 0 2006.238.07:36:28.17#ibcon#about to read 3, iclass 35, count 0 2006.238.07:36:28.19#ibcon#read 3, iclass 35, count 0 2006.238.07:36:28.19#ibcon#about to read 4, iclass 35, count 0 2006.238.07:36:28.19#ibcon#read 4, iclass 35, count 0 2006.238.07:36:28.19#ibcon#about to read 5, iclass 35, count 0 2006.238.07:36:28.19#ibcon#read 5, iclass 35, count 0 2006.238.07:36:28.19#ibcon#about to read 6, iclass 35, count 0 2006.238.07:36:28.19#ibcon#read 6, iclass 35, count 0 2006.238.07:36:28.19#ibcon#end of sib2, iclass 35, count 0 2006.238.07:36:28.19#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:36:28.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:36:28.19#ibcon#[25=USB\r\n] 2006.238.07:36:28.19#ibcon#*before write, iclass 35, count 0 2006.238.07:36:28.19#ibcon#enter sib2, iclass 35, count 0 2006.238.07:36:28.19#ibcon#flushed, iclass 35, count 0 2006.238.07:36:28.19#ibcon#about to write, iclass 35, count 0 2006.238.07:36:28.19#ibcon#wrote, iclass 35, count 0 2006.238.07:36:28.19#ibcon#about to read 3, iclass 35, count 0 2006.238.07:36:28.22#ibcon#read 3, iclass 35, count 0 2006.238.07:36:28.22#ibcon#about to read 4, iclass 35, count 0 2006.238.07:36:28.22#ibcon#read 4, iclass 35, count 0 2006.238.07:36:28.22#ibcon#about to read 5, iclass 35, count 0 2006.238.07:36:28.22#ibcon#read 5, iclass 35, count 0 2006.238.07:36:28.22#ibcon#about to read 6, iclass 35, count 0 2006.238.07:36:28.22#ibcon#read 6, iclass 35, count 0 2006.238.07:36:28.22#ibcon#end of sib2, iclass 35, count 0 2006.238.07:36:28.22#ibcon#*after write, iclass 35, count 0 2006.238.07:36:28.22#ibcon#*before return 0, iclass 35, count 0 2006.238.07:36:28.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:36:28.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:36:28.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:36:28.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:36:28.22$vc4f8/valo=2,572.99 2006.238.07:36:28.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.07:36:28.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.07:36:28.22#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:28.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:36:28.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:36:28.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:36:28.22#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:36:28.22#ibcon#first serial, iclass 37, count 0 2006.238.07:36:28.22#ibcon#enter sib2, iclass 37, count 0 2006.238.07:36:28.22#ibcon#flushed, iclass 37, count 0 2006.238.07:36:28.22#ibcon#about to write, iclass 37, count 0 2006.238.07:36:28.22#ibcon#wrote, iclass 37, count 0 2006.238.07:36:28.22#ibcon#about to read 3, iclass 37, count 0 2006.238.07:36:28.24#ibcon#read 3, iclass 37, count 0 2006.238.07:36:28.24#ibcon#about to read 4, iclass 37, count 0 2006.238.07:36:28.24#ibcon#read 4, iclass 37, count 0 2006.238.07:36:28.24#ibcon#about to read 5, iclass 37, count 0 2006.238.07:36:28.24#ibcon#read 5, iclass 37, count 0 2006.238.07:36:28.24#ibcon#about to read 6, iclass 37, count 0 2006.238.07:36:28.24#ibcon#read 6, iclass 37, count 0 2006.238.07:36:28.24#ibcon#end of sib2, iclass 37, count 0 2006.238.07:36:28.24#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:36:28.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:36:28.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:36:28.24#ibcon#*before write, iclass 37, count 0 2006.238.07:36:28.24#ibcon#enter sib2, iclass 37, count 0 2006.238.07:36:28.24#ibcon#flushed, iclass 37, count 0 2006.238.07:36:28.24#ibcon#about to write, iclass 37, count 0 2006.238.07:36:28.24#ibcon#wrote, iclass 37, count 0 2006.238.07:36:28.24#ibcon#about to read 3, iclass 37, count 0 2006.238.07:36:28.28#ibcon#read 3, iclass 37, count 0 2006.238.07:36:28.28#ibcon#about to read 4, iclass 37, count 0 2006.238.07:36:28.28#ibcon#read 4, iclass 37, count 0 2006.238.07:36:28.28#ibcon#about to read 5, iclass 37, count 0 2006.238.07:36:28.28#ibcon#read 5, iclass 37, count 0 2006.238.07:36:28.28#ibcon#about to read 6, iclass 37, count 0 2006.238.07:36:28.28#ibcon#read 6, iclass 37, count 0 2006.238.07:36:28.28#ibcon#end of sib2, iclass 37, count 0 2006.238.07:36:28.28#ibcon#*after write, iclass 37, count 0 2006.238.07:36:28.28#ibcon#*before return 0, iclass 37, count 0 2006.238.07:36:28.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:36:28.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:36:28.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:36:28.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:36:28.28$vc4f8/va=2,7 2006.238.07:36:28.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.238.07:36:28.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.238.07:36:28.28#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:28.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:36:28.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:36:28.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:36:28.34#ibcon#enter wrdev, iclass 39, count 2 2006.238.07:36:28.34#ibcon#first serial, iclass 39, count 2 2006.238.07:36:28.34#ibcon#enter sib2, iclass 39, count 2 2006.238.07:36:28.34#ibcon#flushed, iclass 39, count 2 2006.238.07:36:28.34#ibcon#about to write, iclass 39, count 2 2006.238.07:36:28.34#ibcon#wrote, iclass 39, count 2 2006.238.07:36:28.34#ibcon#about to read 3, iclass 39, count 2 2006.238.07:36:28.37#ibcon#read 3, iclass 39, count 2 2006.238.07:36:28.37#ibcon#about to read 4, iclass 39, count 2 2006.238.07:36:28.37#ibcon#read 4, iclass 39, count 2 2006.238.07:36:28.37#ibcon#about to read 5, iclass 39, count 2 2006.238.07:36:28.37#ibcon#read 5, iclass 39, count 2 2006.238.07:36:28.37#ibcon#about to read 6, iclass 39, count 2 2006.238.07:36:28.37#ibcon#read 6, iclass 39, count 2 2006.238.07:36:28.37#ibcon#end of sib2, iclass 39, count 2 2006.238.07:36:28.37#ibcon#*mode == 0, iclass 39, count 2 2006.238.07:36:28.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.238.07:36:28.37#ibcon#[25=AT02-07\r\n] 2006.238.07:36:28.37#ibcon#*before write, iclass 39, count 2 2006.238.07:36:28.37#ibcon#enter sib2, iclass 39, count 2 2006.238.07:36:28.37#ibcon#flushed, iclass 39, count 2 2006.238.07:36:28.37#ibcon#about to write, iclass 39, count 2 2006.238.07:36:28.37#ibcon#wrote, iclass 39, count 2 2006.238.07:36:28.37#ibcon#about to read 3, iclass 39, count 2 2006.238.07:36:28.40#ibcon#read 3, iclass 39, count 2 2006.238.07:36:28.40#ibcon#about to read 4, iclass 39, count 2 2006.238.07:36:28.40#ibcon#read 4, iclass 39, count 2 2006.238.07:36:28.40#ibcon#about to read 5, iclass 39, count 2 2006.238.07:36:28.40#ibcon#read 5, iclass 39, count 2 2006.238.07:36:28.40#ibcon#about to read 6, iclass 39, count 2 2006.238.07:36:28.40#ibcon#read 6, iclass 39, count 2 2006.238.07:36:28.40#ibcon#end of sib2, iclass 39, count 2 2006.238.07:36:28.40#ibcon#*after write, iclass 39, count 2 2006.238.07:36:28.40#ibcon#*before return 0, iclass 39, count 2 2006.238.07:36:28.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:36:28.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:36:28.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.238.07:36:28.40#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:28.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:36:28.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:36:28.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:36:28.52#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:36:28.52#ibcon#first serial, iclass 39, count 0 2006.238.07:36:28.52#ibcon#enter sib2, iclass 39, count 0 2006.238.07:36:28.52#ibcon#flushed, iclass 39, count 0 2006.238.07:36:28.52#ibcon#about to write, iclass 39, count 0 2006.238.07:36:28.52#ibcon#wrote, iclass 39, count 0 2006.238.07:36:28.52#ibcon#about to read 3, iclass 39, count 0 2006.238.07:36:28.54#ibcon#read 3, iclass 39, count 0 2006.238.07:36:28.54#ibcon#about to read 4, iclass 39, count 0 2006.238.07:36:28.54#ibcon#read 4, iclass 39, count 0 2006.238.07:36:28.54#ibcon#about to read 5, iclass 39, count 0 2006.238.07:36:28.54#ibcon#read 5, iclass 39, count 0 2006.238.07:36:28.54#ibcon#about to read 6, iclass 39, count 0 2006.238.07:36:28.54#ibcon#read 6, iclass 39, count 0 2006.238.07:36:28.54#ibcon#end of sib2, iclass 39, count 0 2006.238.07:36:28.54#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:36:28.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:36:28.54#ibcon#[25=USB\r\n] 2006.238.07:36:28.54#ibcon#*before write, iclass 39, count 0 2006.238.07:36:28.54#ibcon#enter sib2, iclass 39, count 0 2006.238.07:36:28.54#ibcon#flushed, iclass 39, count 0 2006.238.07:36:28.54#ibcon#about to write, iclass 39, count 0 2006.238.07:36:28.54#ibcon#wrote, iclass 39, count 0 2006.238.07:36:28.54#ibcon#about to read 3, iclass 39, count 0 2006.238.07:36:28.57#ibcon#read 3, iclass 39, count 0 2006.238.07:36:28.57#ibcon#about to read 4, iclass 39, count 0 2006.238.07:36:28.57#ibcon#read 4, iclass 39, count 0 2006.238.07:36:28.57#ibcon#about to read 5, iclass 39, count 0 2006.238.07:36:28.57#ibcon#read 5, iclass 39, count 0 2006.238.07:36:28.57#ibcon#about to read 6, iclass 39, count 0 2006.238.07:36:28.57#ibcon#read 6, iclass 39, count 0 2006.238.07:36:28.57#ibcon#end of sib2, iclass 39, count 0 2006.238.07:36:28.57#ibcon#*after write, iclass 39, count 0 2006.238.07:36:28.57#ibcon#*before return 0, iclass 39, count 0 2006.238.07:36:28.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:36:28.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:36:28.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:36:28.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:36:28.57$vc4f8/valo=3,672.99 2006.238.07:36:28.57#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.07:36:28.57#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.07:36:28.57#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:28.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:36:28.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:36:28.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:36:28.57#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:36:28.57#ibcon#first serial, iclass 3, count 0 2006.238.07:36:28.57#ibcon#enter sib2, iclass 3, count 0 2006.238.07:36:28.57#ibcon#flushed, iclass 3, count 0 2006.238.07:36:28.57#ibcon#about to write, iclass 3, count 0 2006.238.07:36:28.57#ibcon#wrote, iclass 3, count 0 2006.238.07:36:28.57#ibcon#about to read 3, iclass 3, count 0 2006.238.07:36:28.59#ibcon#read 3, iclass 3, count 0 2006.238.07:36:28.59#ibcon#about to read 4, iclass 3, count 0 2006.238.07:36:28.59#ibcon#read 4, iclass 3, count 0 2006.238.07:36:28.59#ibcon#about to read 5, iclass 3, count 0 2006.238.07:36:28.59#ibcon#read 5, iclass 3, count 0 2006.238.07:36:28.59#ibcon#about to read 6, iclass 3, count 0 2006.238.07:36:28.59#ibcon#read 6, iclass 3, count 0 2006.238.07:36:28.59#ibcon#end of sib2, iclass 3, count 0 2006.238.07:36:28.59#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:36:28.59#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:36:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:36:28.59#ibcon#*before write, iclass 3, count 0 2006.238.07:36:28.59#ibcon#enter sib2, iclass 3, count 0 2006.238.07:36:28.59#ibcon#flushed, iclass 3, count 0 2006.238.07:36:28.59#ibcon#about to write, iclass 3, count 0 2006.238.07:36:28.59#ibcon#wrote, iclass 3, count 0 2006.238.07:36:28.59#ibcon#about to read 3, iclass 3, count 0 2006.238.07:36:28.63#ibcon#read 3, iclass 3, count 0 2006.238.07:36:28.63#ibcon#about to read 4, iclass 3, count 0 2006.238.07:36:28.63#ibcon#read 4, iclass 3, count 0 2006.238.07:36:28.63#ibcon#about to read 5, iclass 3, count 0 2006.238.07:36:28.63#ibcon#read 5, iclass 3, count 0 2006.238.07:36:28.63#ibcon#about to read 6, iclass 3, count 0 2006.238.07:36:28.63#ibcon#read 6, iclass 3, count 0 2006.238.07:36:28.63#ibcon#end of sib2, iclass 3, count 0 2006.238.07:36:28.63#ibcon#*after write, iclass 3, count 0 2006.238.07:36:28.63#ibcon#*before return 0, iclass 3, count 0 2006.238.07:36:28.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:36:28.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:36:28.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:36:28.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:36:28.63$vc4f8/va=3,7 2006.238.07:36:28.63#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.238.07:36:28.63#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.238.07:36:28.63#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:28.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:36:28.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:36:28.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:36:28.69#ibcon#enter wrdev, iclass 5, count 2 2006.238.07:36:28.69#ibcon#first serial, iclass 5, count 2 2006.238.07:36:28.69#ibcon#enter sib2, iclass 5, count 2 2006.238.07:36:28.69#ibcon#flushed, iclass 5, count 2 2006.238.07:36:28.69#ibcon#about to write, iclass 5, count 2 2006.238.07:36:28.69#ibcon#wrote, iclass 5, count 2 2006.238.07:36:28.69#ibcon#about to read 3, iclass 5, count 2 2006.238.07:36:28.71#ibcon#read 3, iclass 5, count 2 2006.238.07:36:28.71#ibcon#about to read 4, iclass 5, count 2 2006.238.07:36:28.71#ibcon#read 4, iclass 5, count 2 2006.238.07:36:28.71#ibcon#about to read 5, iclass 5, count 2 2006.238.07:36:28.71#ibcon#read 5, iclass 5, count 2 2006.238.07:36:28.71#ibcon#about to read 6, iclass 5, count 2 2006.238.07:36:28.71#ibcon#read 6, iclass 5, count 2 2006.238.07:36:28.71#ibcon#end of sib2, iclass 5, count 2 2006.238.07:36:28.71#ibcon#*mode == 0, iclass 5, count 2 2006.238.07:36:28.71#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.238.07:36:28.71#ibcon#[25=AT03-07\r\n] 2006.238.07:36:28.71#ibcon#*before write, iclass 5, count 2 2006.238.07:36:28.71#ibcon#enter sib2, iclass 5, count 2 2006.238.07:36:28.71#ibcon#flushed, iclass 5, count 2 2006.238.07:36:28.71#ibcon#about to write, iclass 5, count 2 2006.238.07:36:28.71#ibcon#wrote, iclass 5, count 2 2006.238.07:36:28.71#ibcon#about to read 3, iclass 5, count 2 2006.238.07:36:28.74#ibcon#read 3, iclass 5, count 2 2006.238.07:36:28.74#ibcon#about to read 4, iclass 5, count 2 2006.238.07:36:28.74#ibcon#read 4, iclass 5, count 2 2006.238.07:36:28.74#ibcon#about to read 5, iclass 5, count 2 2006.238.07:36:28.74#ibcon#read 5, iclass 5, count 2 2006.238.07:36:28.74#ibcon#about to read 6, iclass 5, count 2 2006.238.07:36:28.74#ibcon#read 6, iclass 5, count 2 2006.238.07:36:28.74#ibcon#end of sib2, iclass 5, count 2 2006.238.07:36:28.74#ibcon#*after write, iclass 5, count 2 2006.238.07:36:28.74#ibcon#*before return 0, iclass 5, count 2 2006.238.07:36:28.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:36:28.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:36:28.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.238.07:36:28.74#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:28.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:36:28.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:36:28.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:36:28.86#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:36:28.86#ibcon#first serial, iclass 5, count 0 2006.238.07:36:28.86#ibcon#enter sib2, iclass 5, count 0 2006.238.07:36:28.86#ibcon#flushed, iclass 5, count 0 2006.238.07:36:28.86#ibcon#about to write, iclass 5, count 0 2006.238.07:36:28.86#ibcon#wrote, iclass 5, count 0 2006.238.07:36:28.86#ibcon#about to read 3, iclass 5, count 0 2006.238.07:36:28.88#ibcon#read 3, iclass 5, count 0 2006.238.07:36:28.88#ibcon#about to read 4, iclass 5, count 0 2006.238.07:36:28.88#ibcon#read 4, iclass 5, count 0 2006.238.07:36:28.88#ibcon#about to read 5, iclass 5, count 0 2006.238.07:36:28.88#ibcon#read 5, iclass 5, count 0 2006.238.07:36:28.88#ibcon#about to read 6, iclass 5, count 0 2006.238.07:36:28.88#ibcon#read 6, iclass 5, count 0 2006.238.07:36:28.88#ibcon#end of sib2, iclass 5, count 0 2006.238.07:36:28.88#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:36:28.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:36:28.88#ibcon#[25=USB\r\n] 2006.238.07:36:28.88#ibcon#*before write, iclass 5, count 0 2006.238.07:36:28.88#ibcon#enter sib2, iclass 5, count 0 2006.238.07:36:28.88#ibcon#flushed, iclass 5, count 0 2006.238.07:36:28.88#ibcon#about to write, iclass 5, count 0 2006.238.07:36:28.88#ibcon#wrote, iclass 5, count 0 2006.238.07:36:28.88#ibcon#about to read 3, iclass 5, count 0 2006.238.07:36:28.91#ibcon#read 3, iclass 5, count 0 2006.238.07:36:28.91#ibcon#about to read 4, iclass 5, count 0 2006.238.07:36:28.91#ibcon#read 4, iclass 5, count 0 2006.238.07:36:28.91#ibcon#about to read 5, iclass 5, count 0 2006.238.07:36:28.91#ibcon#read 5, iclass 5, count 0 2006.238.07:36:28.91#ibcon#about to read 6, iclass 5, count 0 2006.238.07:36:28.91#ibcon#read 6, iclass 5, count 0 2006.238.07:36:28.91#ibcon#end of sib2, iclass 5, count 0 2006.238.07:36:28.91#ibcon#*after write, iclass 5, count 0 2006.238.07:36:28.91#ibcon#*before return 0, iclass 5, count 0 2006.238.07:36:28.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:36:28.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:36:28.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:36:28.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:36:28.91$vc4f8/valo=4,832.99 2006.238.07:36:28.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.238.07:36:28.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.238.07:36:28.91#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:28.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:36:28.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:36:28.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:36:28.91#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:36:28.91#ibcon#first serial, iclass 7, count 0 2006.238.07:36:28.91#ibcon#enter sib2, iclass 7, count 0 2006.238.07:36:28.91#ibcon#flushed, iclass 7, count 0 2006.238.07:36:28.91#ibcon#about to write, iclass 7, count 0 2006.238.07:36:28.91#ibcon#wrote, iclass 7, count 0 2006.238.07:36:28.91#ibcon#about to read 3, iclass 7, count 0 2006.238.07:36:28.93#ibcon#read 3, iclass 7, count 0 2006.238.07:36:28.93#ibcon#about to read 4, iclass 7, count 0 2006.238.07:36:28.93#ibcon#read 4, iclass 7, count 0 2006.238.07:36:28.93#ibcon#about to read 5, iclass 7, count 0 2006.238.07:36:28.93#ibcon#read 5, iclass 7, count 0 2006.238.07:36:28.93#ibcon#about to read 6, iclass 7, count 0 2006.238.07:36:28.93#ibcon#read 6, iclass 7, count 0 2006.238.07:36:28.93#ibcon#end of sib2, iclass 7, count 0 2006.238.07:36:28.93#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:36:28.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:36:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:36:28.93#ibcon#*before write, iclass 7, count 0 2006.238.07:36:28.93#ibcon#enter sib2, iclass 7, count 0 2006.238.07:36:28.93#ibcon#flushed, iclass 7, count 0 2006.238.07:36:28.93#ibcon#about to write, iclass 7, count 0 2006.238.07:36:28.93#ibcon#wrote, iclass 7, count 0 2006.238.07:36:28.93#ibcon#about to read 3, iclass 7, count 0 2006.238.07:36:28.97#ibcon#read 3, iclass 7, count 0 2006.238.07:36:28.97#ibcon#about to read 4, iclass 7, count 0 2006.238.07:36:28.97#ibcon#read 4, iclass 7, count 0 2006.238.07:36:28.97#ibcon#about to read 5, iclass 7, count 0 2006.238.07:36:28.97#ibcon#read 5, iclass 7, count 0 2006.238.07:36:28.97#ibcon#about to read 6, iclass 7, count 0 2006.238.07:36:28.97#ibcon#read 6, iclass 7, count 0 2006.238.07:36:28.97#ibcon#end of sib2, iclass 7, count 0 2006.238.07:36:28.97#ibcon#*after write, iclass 7, count 0 2006.238.07:36:28.97#ibcon#*before return 0, iclass 7, count 0 2006.238.07:36:28.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:36:28.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:36:28.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:36:28.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:36:28.97$vc4f8/va=4,7 2006.238.07:36:28.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.238.07:36:28.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.238.07:36:28.97#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:28.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:36:29.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:36:29.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:36:29.03#ibcon#enter wrdev, iclass 11, count 2 2006.238.07:36:29.03#ibcon#first serial, iclass 11, count 2 2006.238.07:36:29.03#ibcon#enter sib2, iclass 11, count 2 2006.238.07:36:29.03#ibcon#flushed, iclass 11, count 2 2006.238.07:36:29.03#ibcon#about to write, iclass 11, count 2 2006.238.07:36:29.03#ibcon#wrote, iclass 11, count 2 2006.238.07:36:29.03#ibcon#about to read 3, iclass 11, count 2 2006.238.07:36:29.05#ibcon#read 3, iclass 11, count 2 2006.238.07:36:29.05#ibcon#about to read 4, iclass 11, count 2 2006.238.07:36:29.05#ibcon#read 4, iclass 11, count 2 2006.238.07:36:29.05#ibcon#about to read 5, iclass 11, count 2 2006.238.07:36:29.05#ibcon#read 5, iclass 11, count 2 2006.238.07:36:29.05#ibcon#about to read 6, iclass 11, count 2 2006.238.07:36:29.05#ibcon#read 6, iclass 11, count 2 2006.238.07:36:29.05#ibcon#end of sib2, iclass 11, count 2 2006.238.07:36:29.05#ibcon#*mode == 0, iclass 11, count 2 2006.238.07:36:29.05#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.238.07:36:29.05#ibcon#[25=AT04-07\r\n] 2006.238.07:36:29.05#ibcon#*before write, iclass 11, count 2 2006.238.07:36:29.05#ibcon#enter sib2, iclass 11, count 2 2006.238.07:36:29.05#ibcon#flushed, iclass 11, count 2 2006.238.07:36:29.05#ibcon#about to write, iclass 11, count 2 2006.238.07:36:29.05#ibcon#wrote, iclass 11, count 2 2006.238.07:36:29.05#ibcon#about to read 3, iclass 11, count 2 2006.238.07:36:29.08#ibcon#read 3, iclass 11, count 2 2006.238.07:36:29.08#ibcon#about to read 4, iclass 11, count 2 2006.238.07:36:29.08#ibcon#read 4, iclass 11, count 2 2006.238.07:36:29.08#ibcon#about to read 5, iclass 11, count 2 2006.238.07:36:29.08#ibcon#read 5, iclass 11, count 2 2006.238.07:36:29.08#ibcon#about to read 6, iclass 11, count 2 2006.238.07:36:29.08#ibcon#read 6, iclass 11, count 2 2006.238.07:36:29.08#ibcon#end of sib2, iclass 11, count 2 2006.238.07:36:29.08#ibcon#*after write, iclass 11, count 2 2006.238.07:36:29.08#ibcon#*before return 0, iclass 11, count 2 2006.238.07:36:29.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:36:29.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:36:29.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.238.07:36:29.08#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:29.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:36:29.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:36:29.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:36:29.20#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:36:29.20#ibcon#first serial, iclass 11, count 0 2006.238.07:36:29.20#ibcon#enter sib2, iclass 11, count 0 2006.238.07:36:29.20#ibcon#flushed, iclass 11, count 0 2006.238.07:36:29.20#ibcon#about to write, iclass 11, count 0 2006.238.07:36:29.20#ibcon#wrote, iclass 11, count 0 2006.238.07:36:29.20#ibcon#about to read 3, iclass 11, count 0 2006.238.07:36:29.22#ibcon#read 3, iclass 11, count 0 2006.238.07:36:29.22#ibcon#about to read 4, iclass 11, count 0 2006.238.07:36:29.22#ibcon#read 4, iclass 11, count 0 2006.238.07:36:29.22#ibcon#about to read 5, iclass 11, count 0 2006.238.07:36:29.22#ibcon#read 5, iclass 11, count 0 2006.238.07:36:29.22#ibcon#about to read 6, iclass 11, count 0 2006.238.07:36:29.22#ibcon#read 6, iclass 11, count 0 2006.238.07:36:29.22#ibcon#end of sib2, iclass 11, count 0 2006.238.07:36:29.22#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:36:29.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:36:29.22#ibcon#[25=USB\r\n] 2006.238.07:36:29.22#ibcon#*before write, iclass 11, count 0 2006.238.07:36:29.22#ibcon#enter sib2, iclass 11, count 0 2006.238.07:36:29.22#ibcon#flushed, iclass 11, count 0 2006.238.07:36:29.22#ibcon#about to write, iclass 11, count 0 2006.238.07:36:29.22#ibcon#wrote, iclass 11, count 0 2006.238.07:36:29.22#ibcon#about to read 3, iclass 11, count 0 2006.238.07:36:29.25#ibcon#read 3, iclass 11, count 0 2006.238.07:36:29.25#ibcon#about to read 4, iclass 11, count 0 2006.238.07:36:29.25#ibcon#read 4, iclass 11, count 0 2006.238.07:36:29.25#ibcon#about to read 5, iclass 11, count 0 2006.238.07:36:29.25#ibcon#read 5, iclass 11, count 0 2006.238.07:36:29.25#ibcon#about to read 6, iclass 11, count 0 2006.238.07:36:29.25#ibcon#read 6, iclass 11, count 0 2006.238.07:36:29.25#ibcon#end of sib2, iclass 11, count 0 2006.238.07:36:29.25#ibcon#*after write, iclass 11, count 0 2006.238.07:36:29.25#ibcon#*before return 0, iclass 11, count 0 2006.238.07:36:29.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:36:29.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:36:29.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:36:29.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:36:29.25$vc4f8/valo=5,652.99 2006.238.07:36:29.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.07:36:29.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.07:36:29.25#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:29.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:36:29.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:36:29.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:36:29.25#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:36:29.25#ibcon#first serial, iclass 13, count 0 2006.238.07:36:29.25#ibcon#enter sib2, iclass 13, count 0 2006.238.07:36:29.25#ibcon#flushed, iclass 13, count 0 2006.238.07:36:29.25#ibcon#about to write, iclass 13, count 0 2006.238.07:36:29.25#ibcon#wrote, iclass 13, count 0 2006.238.07:36:29.25#ibcon#about to read 3, iclass 13, count 0 2006.238.07:36:29.27#ibcon#read 3, iclass 13, count 0 2006.238.07:36:29.27#ibcon#about to read 4, iclass 13, count 0 2006.238.07:36:29.27#ibcon#read 4, iclass 13, count 0 2006.238.07:36:29.27#ibcon#about to read 5, iclass 13, count 0 2006.238.07:36:29.27#ibcon#read 5, iclass 13, count 0 2006.238.07:36:29.27#ibcon#about to read 6, iclass 13, count 0 2006.238.07:36:29.27#ibcon#read 6, iclass 13, count 0 2006.238.07:36:29.27#ibcon#end of sib2, iclass 13, count 0 2006.238.07:36:29.27#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:36:29.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:36:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:36:29.27#ibcon#*before write, iclass 13, count 0 2006.238.07:36:29.27#ibcon#enter sib2, iclass 13, count 0 2006.238.07:36:29.27#ibcon#flushed, iclass 13, count 0 2006.238.07:36:29.27#ibcon#about to write, iclass 13, count 0 2006.238.07:36:29.27#ibcon#wrote, iclass 13, count 0 2006.238.07:36:29.27#ibcon#about to read 3, iclass 13, count 0 2006.238.07:36:29.31#ibcon#read 3, iclass 13, count 0 2006.238.07:36:29.31#ibcon#about to read 4, iclass 13, count 0 2006.238.07:36:29.31#ibcon#read 4, iclass 13, count 0 2006.238.07:36:29.31#ibcon#about to read 5, iclass 13, count 0 2006.238.07:36:29.31#ibcon#read 5, iclass 13, count 0 2006.238.07:36:29.31#ibcon#about to read 6, iclass 13, count 0 2006.238.07:36:29.31#ibcon#read 6, iclass 13, count 0 2006.238.07:36:29.31#ibcon#end of sib2, iclass 13, count 0 2006.238.07:36:29.31#ibcon#*after write, iclass 13, count 0 2006.238.07:36:29.31#ibcon#*before return 0, iclass 13, count 0 2006.238.07:36:29.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:36:29.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:36:29.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:36:29.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:36:29.31$vc4f8/va=5,8 2006.238.07:36:29.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.238.07:36:29.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.238.07:36:29.31#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:29.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:36:29.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:36:29.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:36:29.37#ibcon#enter wrdev, iclass 15, count 2 2006.238.07:36:29.37#ibcon#first serial, iclass 15, count 2 2006.238.07:36:29.37#ibcon#enter sib2, iclass 15, count 2 2006.238.07:36:29.37#ibcon#flushed, iclass 15, count 2 2006.238.07:36:29.37#ibcon#about to write, iclass 15, count 2 2006.238.07:36:29.37#ibcon#wrote, iclass 15, count 2 2006.238.07:36:29.37#ibcon#about to read 3, iclass 15, count 2 2006.238.07:36:29.39#ibcon#read 3, iclass 15, count 2 2006.238.07:36:29.39#ibcon#about to read 4, iclass 15, count 2 2006.238.07:36:29.39#ibcon#read 4, iclass 15, count 2 2006.238.07:36:29.39#ibcon#about to read 5, iclass 15, count 2 2006.238.07:36:29.39#ibcon#read 5, iclass 15, count 2 2006.238.07:36:29.39#ibcon#about to read 6, iclass 15, count 2 2006.238.07:36:29.39#ibcon#read 6, iclass 15, count 2 2006.238.07:36:29.39#ibcon#end of sib2, iclass 15, count 2 2006.238.07:36:29.39#ibcon#*mode == 0, iclass 15, count 2 2006.238.07:36:29.39#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.238.07:36:29.39#ibcon#[25=AT05-08\r\n] 2006.238.07:36:29.39#ibcon#*before write, iclass 15, count 2 2006.238.07:36:29.39#ibcon#enter sib2, iclass 15, count 2 2006.238.07:36:29.39#ibcon#flushed, iclass 15, count 2 2006.238.07:36:29.39#ibcon#about to write, iclass 15, count 2 2006.238.07:36:29.39#ibcon#wrote, iclass 15, count 2 2006.238.07:36:29.39#ibcon#about to read 3, iclass 15, count 2 2006.238.07:36:29.42#ibcon#read 3, iclass 15, count 2 2006.238.07:36:29.42#ibcon#about to read 4, iclass 15, count 2 2006.238.07:36:29.42#ibcon#read 4, iclass 15, count 2 2006.238.07:36:29.42#ibcon#about to read 5, iclass 15, count 2 2006.238.07:36:29.42#ibcon#read 5, iclass 15, count 2 2006.238.07:36:29.42#ibcon#about to read 6, iclass 15, count 2 2006.238.07:36:29.42#ibcon#read 6, iclass 15, count 2 2006.238.07:36:29.42#ibcon#end of sib2, iclass 15, count 2 2006.238.07:36:29.42#ibcon#*after write, iclass 15, count 2 2006.238.07:36:29.42#ibcon#*before return 0, iclass 15, count 2 2006.238.07:36:29.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:36:29.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:36:29.42#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.238.07:36:29.42#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:29.42#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:36:29.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:36:29.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:36:29.55#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:36:29.55#ibcon#first serial, iclass 15, count 0 2006.238.07:36:29.55#ibcon#enter sib2, iclass 15, count 0 2006.238.07:36:29.55#ibcon#flushed, iclass 15, count 0 2006.238.07:36:29.55#ibcon#about to write, iclass 15, count 0 2006.238.07:36:29.55#ibcon#wrote, iclass 15, count 0 2006.238.07:36:29.55#ibcon#about to read 3, iclass 15, count 0 2006.238.07:36:29.57#ibcon#read 3, iclass 15, count 0 2006.238.07:36:29.57#ibcon#about to read 4, iclass 15, count 0 2006.238.07:36:29.57#ibcon#read 4, iclass 15, count 0 2006.238.07:36:29.57#ibcon#about to read 5, iclass 15, count 0 2006.238.07:36:29.57#ibcon#read 5, iclass 15, count 0 2006.238.07:36:29.57#ibcon#about to read 6, iclass 15, count 0 2006.238.07:36:29.57#ibcon#read 6, iclass 15, count 0 2006.238.07:36:29.57#ibcon#end of sib2, iclass 15, count 0 2006.238.07:36:29.57#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:36:29.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:36:29.57#ibcon#[25=USB\r\n] 2006.238.07:36:29.57#ibcon#*before write, iclass 15, count 0 2006.238.07:36:29.57#ibcon#enter sib2, iclass 15, count 0 2006.238.07:36:29.57#ibcon#flushed, iclass 15, count 0 2006.238.07:36:29.57#ibcon#about to write, iclass 15, count 0 2006.238.07:36:29.57#ibcon#wrote, iclass 15, count 0 2006.238.07:36:29.57#ibcon#about to read 3, iclass 15, count 0 2006.238.07:36:29.60#ibcon#read 3, iclass 15, count 0 2006.238.07:36:29.60#ibcon#about to read 4, iclass 15, count 0 2006.238.07:36:29.60#ibcon#read 4, iclass 15, count 0 2006.238.07:36:29.60#ibcon#about to read 5, iclass 15, count 0 2006.238.07:36:29.60#ibcon#read 5, iclass 15, count 0 2006.238.07:36:29.60#ibcon#about to read 6, iclass 15, count 0 2006.238.07:36:29.60#ibcon#read 6, iclass 15, count 0 2006.238.07:36:29.60#ibcon#end of sib2, iclass 15, count 0 2006.238.07:36:29.60#ibcon#*after write, iclass 15, count 0 2006.238.07:36:29.60#ibcon#*before return 0, iclass 15, count 0 2006.238.07:36:29.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:36:29.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:36:29.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:36:29.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:36:29.60$vc4f8/valo=6,772.99 2006.238.07:36:29.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.07:36:29.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.07:36:29.60#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:29.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:36:29.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:36:29.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:36:29.60#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:36:29.60#ibcon#first serial, iclass 17, count 0 2006.238.07:36:29.60#ibcon#enter sib2, iclass 17, count 0 2006.238.07:36:29.60#ibcon#flushed, iclass 17, count 0 2006.238.07:36:29.60#ibcon#about to write, iclass 17, count 0 2006.238.07:36:29.60#ibcon#wrote, iclass 17, count 0 2006.238.07:36:29.60#ibcon#about to read 3, iclass 17, count 0 2006.238.07:36:29.62#ibcon#read 3, iclass 17, count 0 2006.238.07:36:29.62#ibcon#about to read 4, iclass 17, count 0 2006.238.07:36:29.62#ibcon#read 4, iclass 17, count 0 2006.238.07:36:29.62#ibcon#about to read 5, iclass 17, count 0 2006.238.07:36:29.62#ibcon#read 5, iclass 17, count 0 2006.238.07:36:29.62#ibcon#about to read 6, iclass 17, count 0 2006.238.07:36:29.62#ibcon#read 6, iclass 17, count 0 2006.238.07:36:29.62#ibcon#end of sib2, iclass 17, count 0 2006.238.07:36:29.62#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:36:29.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:36:29.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:36:29.62#ibcon#*before write, iclass 17, count 0 2006.238.07:36:29.62#ibcon#enter sib2, iclass 17, count 0 2006.238.07:36:29.62#ibcon#flushed, iclass 17, count 0 2006.238.07:36:29.62#ibcon#about to write, iclass 17, count 0 2006.238.07:36:29.62#ibcon#wrote, iclass 17, count 0 2006.238.07:36:29.62#ibcon#about to read 3, iclass 17, count 0 2006.238.07:36:29.66#ibcon#read 3, iclass 17, count 0 2006.238.07:36:29.66#ibcon#about to read 4, iclass 17, count 0 2006.238.07:36:29.66#ibcon#read 4, iclass 17, count 0 2006.238.07:36:29.66#ibcon#about to read 5, iclass 17, count 0 2006.238.07:36:29.66#ibcon#read 5, iclass 17, count 0 2006.238.07:36:29.66#ibcon#about to read 6, iclass 17, count 0 2006.238.07:36:29.66#ibcon#read 6, iclass 17, count 0 2006.238.07:36:29.66#ibcon#end of sib2, iclass 17, count 0 2006.238.07:36:29.66#ibcon#*after write, iclass 17, count 0 2006.238.07:36:29.66#ibcon#*before return 0, iclass 17, count 0 2006.238.07:36:29.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:36:29.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:36:29.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:36:29.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:36:29.66$vc4f8/va=6,7 2006.238.07:36:29.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.238.07:36:29.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.238.07:36:29.66#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:29.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:36:29.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:36:29.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:36:29.72#ibcon#enter wrdev, iclass 19, count 2 2006.238.07:36:29.72#ibcon#first serial, iclass 19, count 2 2006.238.07:36:29.72#ibcon#enter sib2, iclass 19, count 2 2006.238.07:36:29.72#ibcon#flushed, iclass 19, count 2 2006.238.07:36:29.72#ibcon#about to write, iclass 19, count 2 2006.238.07:36:29.72#ibcon#wrote, iclass 19, count 2 2006.238.07:36:29.72#ibcon#about to read 3, iclass 19, count 2 2006.238.07:36:29.74#ibcon#read 3, iclass 19, count 2 2006.238.07:36:29.74#ibcon#about to read 4, iclass 19, count 2 2006.238.07:36:29.74#ibcon#read 4, iclass 19, count 2 2006.238.07:36:29.74#ibcon#about to read 5, iclass 19, count 2 2006.238.07:36:29.74#ibcon#read 5, iclass 19, count 2 2006.238.07:36:29.74#ibcon#about to read 6, iclass 19, count 2 2006.238.07:36:29.74#ibcon#read 6, iclass 19, count 2 2006.238.07:36:29.74#ibcon#end of sib2, iclass 19, count 2 2006.238.07:36:29.74#ibcon#*mode == 0, iclass 19, count 2 2006.238.07:36:29.74#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.238.07:36:29.74#ibcon#[25=AT06-07\r\n] 2006.238.07:36:29.74#ibcon#*before write, iclass 19, count 2 2006.238.07:36:29.74#ibcon#enter sib2, iclass 19, count 2 2006.238.07:36:29.74#ibcon#flushed, iclass 19, count 2 2006.238.07:36:29.74#ibcon#about to write, iclass 19, count 2 2006.238.07:36:29.74#ibcon#wrote, iclass 19, count 2 2006.238.07:36:29.74#ibcon#about to read 3, iclass 19, count 2 2006.238.07:36:29.77#ibcon#read 3, iclass 19, count 2 2006.238.07:36:29.77#ibcon#about to read 4, iclass 19, count 2 2006.238.07:36:29.77#ibcon#read 4, iclass 19, count 2 2006.238.07:36:29.77#ibcon#about to read 5, iclass 19, count 2 2006.238.07:36:29.77#ibcon#read 5, iclass 19, count 2 2006.238.07:36:29.77#ibcon#about to read 6, iclass 19, count 2 2006.238.07:36:29.77#ibcon#read 6, iclass 19, count 2 2006.238.07:36:29.77#ibcon#end of sib2, iclass 19, count 2 2006.238.07:36:29.77#ibcon#*after write, iclass 19, count 2 2006.238.07:36:29.77#ibcon#*before return 0, iclass 19, count 2 2006.238.07:36:29.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:36:29.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:36:29.77#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.238.07:36:29.77#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:29.77#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:36:29.89#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:36:29.89#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:36:29.89#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:36:29.89#ibcon#first serial, iclass 19, count 0 2006.238.07:36:29.89#ibcon#enter sib2, iclass 19, count 0 2006.238.07:36:29.89#ibcon#flushed, iclass 19, count 0 2006.238.07:36:29.89#ibcon#about to write, iclass 19, count 0 2006.238.07:36:29.89#ibcon#wrote, iclass 19, count 0 2006.238.07:36:29.89#ibcon#about to read 3, iclass 19, count 0 2006.238.07:36:29.91#ibcon#read 3, iclass 19, count 0 2006.238.07:36:29.91#ibcon#about to read 4, iclass 19, count 0 2006.238.07:36:29.91#ibcon#read 4, iclass 19, count 0 2006.238.07:36:29.91#ibcon#about to read 5, iclass 19, count 0 2006.238.07:36:29.91#ibcon#read 5, iclass 19, count 0 2006.238.07:36:29.91#ibcon#about to read 6, iclass 19, count 0 2006.238.07:36:29.91#ibcon#read 6, iclass 19, count 0 2006.238.07:36:29.91#ibcon#end of sib2, iclass 19, count 0 2006.238.07:36:29.91#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:36:29.91#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:36:29.91#ibcon#[25=USB\r\n] 2006.238.07:36:29.91#ibcon#*before write, iclass 19, count 0 2006.238.07:36:29.91#ibcon#enter sib2, iclass 19, count 0 2006.238.07:36:29.91#ibcon#flushed, iclass 19, count 0 2006.238.07:36:29.91#ibcon#about to write, iclass 19, count 0 2006.238.07:36:29.91#ibcon#wrote, iclass 19, count 0 2006.238.07:36:29.91#ibcon#about to read 3, iclass 19, count 0 2006.238.07:36:29.94#ibcon#read 3, iclass 19, count 0 2006.238.07:36:29.94#ibcon#about to read 4, iclass 19, count 0 2006.238.07:36:29.94#ibcon#read 4, iclass 19, count 0 2006.238.07:36:29.94#ibcon#about to read 5, iclass 19, count 0 2006.238.07:36:29.94#ibcon#read 5, iclass 19, count 0 2006.238.07:36:29.94#ibcon#about to read 6, iclass 19, count 0 2006.238.07:36:29.94#ibcon#read 6, iclass 19, count 0 2006.238.07:36:29.94#ibcon#end of sib2, iclass 19, count 0 2006.238.07:36:29.94#ibcon#*after write, iclass 19, count 0 2006.238.07:36:29.94#ibcon#*before return 0, iclass 19, count 0 2006.238.07:36:29.94#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:36:29.94#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:36:29.94#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:36:29.94#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:36:29.94$vc4f8/valo=7,832.99 2006.238.07:36:29.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.07:36:29.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.07:36:29.94#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:29.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:36:29.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:36:29.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:36:29.94#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:36:29.94#ibcon#first serial, iclass 21, count 0 2006.238.07:36:29.94#ibcon#enter sib2, iclass 21, count 0 2006.238.07:36:29.94#ibcon#flushed, iclass 21, count 0 2006.238.07:36:29.94#ibcon#about to write, iclass 21, count 0 2006.238.07:36:29.94#ibcon#wrote, iclass 21, count 0 2006.238.07:36:29.94#ibcon#about to read 3, iclass 21, count 0 2006.238.07:36:29.96#ibcon#read 3, iclass 21, count 0 2006.238.07:36:29.96#ibcon#about to read 4, iclass 21, count 0 2006.238.07:36:29.96#ibcon#read 4, iclass 21, count 0 2006.238.07:36:29.96#ibcon#about to read 5, iclass 21, count 0 2006.238.07:36:29.96#ibcon#read 5, iclass 21, count 0 2006.238.07:36:29.96#ibcon#about to read 6, iclass 21, count 0 2006.238.07:36:29.96#ibcon#read 6, iclass 21, count 0 2006.238.07:36:29.96#ibcon#end of sib2, iclass 21, count 0 2006.238.07:36:29.96#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:36:29.96#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:36:29.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:36:29.96#ibcon#*before write, iclass 21, count 0 2006.238.07:36:29.96#ibcon#enter sib2, iclass 21, count 0 2006.238.07:36:29.96#ibcon#flushed, iclass 21, count 0 2006.238.07:36:29.96#ibcon#about to write, iclass 21, count 0 2006.238.07:36:29.96#ibcon#wrote, iclass 21, count 0 2006.238.07:36:29.96#ibcon#about to read 3, iclass 21, count 0 2006.238.07:36:30.00#ibcon#read 3, iclass 21, count 0 2006.238.07:36:30.00#ibcon#about to read 4, iclass 21, count 0 2006.238.07:36:30.00#ibcon#read 4, iclass 21, count 0 2006.238.07:36:30.00#ibcon#about to read 5, iclass 21, count 0 2006.238.07:36:30.00#ibcon#read 5, iclass 21, count 0 2006.238.07:36:30.00#ibcon#about to read 6, iclass 21, count 0 2006.238.07:36:30.00#ibcon#read 6, iclass 21, count 0 2006.238.07:36:30.00#ibcon#end of sib2, iclass 21, count 0 2006.238.07:36:30.00#ibcon#*after write, iclass 21, count 0 2006.238.07:36:30.00#ibcon#*before return 0, iclass 21, count 0 2006.238.07:36:30.00#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:36:30.00#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:36:30.00#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:36:30.00#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:36:30.00$vc4f8/va=7,7 2006.238.07:36:30.00#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.238.07:36:30.00#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.238.07:36:30.00#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:30.00#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:36:30.06#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:36:30.06#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:36:30.06#ibcon#enter wrdev, iclass 23, count 2 2006.238.07:36:30.06#ibcon#first serial, iclass 23, count 2 2006.238.07:36:30.06#ibcon#enter sib2, iclass 23, count 2 2006.238.07:36:30.06#ibcon#flushed, iclass 23, count 2 2006.238.07:36:30.06#ibcon#about to write, iclass 23, count 2 2006.238.07:36:30.06#ibcon#wrote, iclass 23, count 2 2006.238.07:36:30.06#ibcon#about to read 3, iclass 23, count 2 2006.238.07:36:30.08#ibcon#read 3, iclass 23, count 2 2006.238.07:36:30.08#ibcon#about to read 4, iclass 23, count 2 2006.238.07:36:30.08#ibcon#read 4, iclass 23, count 2 2006.238.07:36:30.08#ibcon#about to read 5, iclass 23, count 2 2006.238.07:36:30.08#ibcon#read 5, iclass 23, count 2 2006.238.07:36:30.08#ibcon#about to read 6, iclass 23, count 2 2006.238.07:36:30.08#ibcon#read 6, iclass 23, count 2 2006.238.07:36:30.08#ibcon#end of sib2, iclass 23, count 2 2006.238.07:36:30.08#ibcon#*mode == 0, iclass 23, count 2 2006.238.07:36:30.08#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.238.07:36:30.08#ibcon#[25=AT07-07\r\n] 2006.238.07:36:30.08#ibcon#*before write, iclass 23, count 2 2006.238.07:36:30.08#ibcon#enter sib2, iclass 23, count 2 2006.238.07:36:30.08#ibcon#flushed, iclass 23, count 2 2006.238.07:36:30.08#ibcon#about to write, iclass 23, count 2 2006.238.07:36:30.08#ibcon#wrote, iclass 23, count 2 2006.238.07:36:30.08#ibcon#about to read 3, iclass 23, count 2 2006.238.07:36:30.11#ibcon#read 3, iclass 23, count 2 2006.238.07:36:30.11#ibcon#about to read 4, iclass 23, count 2 2006.238.07:36:30.11#ibcon#read 4, iclass 23, count 2 2006.238.07:36:30.11#ibcon#about to read 5, iclass 23, count 2 2006.238.07:36:30.11#ibcon#read 5, iclass 23, count 2 2006.238.07:36:30.11#ibcon#about to read 6, iclass 23, count 2 2006.238.07:36:30.11#ibcon#read 6, iclass 23, count 2 2006.238.07:36:30.11#ibcon#end of sib2, iclass 23, count 2 2006.238.07:36:30.11#ibcon#*after write, iclass 23, count 2 2006.238.07:36:30.11#ibcon#*before return 0, iclass 23, count 2 2006.238.07:36:30.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:36:30.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:36:30.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.238.07:36:30.11#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:30.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:36:30.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:36:30.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:36:30.23#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:36:30.23#ibcon#first serial, iclass 23, count 0 2006.238.07:36:30.23#ibcon#enter sib2, iclass 23, count 0 2006.238.07:36:30.23#ibcon#flushed, iclass 23, count 0 2006.238.07:36:30.23#ibcon#about to write, iclass 23, count 0 2006.238.07:36:30.23#ibcon#wrote, iclass 23, count 0 2006.238.07:36:30.23#ibcon#about to read 3, iclass 23, count 0 2006.238.07:36:30.25#ibcon#read 3, iclass 23, count 0 2006.238.07:36:30.25#ibcon#about to read 4, iclass 23, count 0 2006.238.07:36:30.25#ibcon#read 4, iclass 23, count 0 2006.238.07:36:30.25#ibcon#about to read 5, iclass 23, count 0 2006.238.07:36:30.25#ibcon#read 5, iclass 23, count 0 2006.238.07:36:30.25#ibcon#about to read 6, iclass 23, count 0 2006.238.07:36:30.25#ibcon#read 6, iclass 23, count 0 2006.238.07:36:30.25#ibcon#end of sib2, iclass 23, count 0 2006.238.07:36:30.25#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:36:30.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:36:30.25#ibcon#[25=USB\r\n] 2006.238.07:36:30.25#ibcon#*before write, iclass 23, count 0 2006.238.07:36:30.25#ibcon#enter sib2, iclass 23, count 0 2006.238.07:36:30.25#ibcon#flushed, iclass 23, count 0 2006.238.07:36:30.25#ibcon#about to write, iclass 23, count 0 2006.238.07:36:30.25#ibcon#wrote, iclass 23, count 0 2006.238.07:36:30.25#ibcon#about to read 3, iclass 23, count 0 2006.238.07:36:30.28#ibcon#read 3, iclass 23, count 0 2006.238.07:36:30.28#ibcon#about to read 4, iclass 23, count 0 2006.238.07:36:30.28#ibcon#read 4, iclass 23, count 0 2006.238.07:36:30.28#ibcon#about to read 5, iclass 23, count 0 2006.238.07:36:30.28#ibcon#read 5, iclass 23, count 0 2006.238.07:36:30.28#ibcon#about to read 6, iclass 23, count 0 2006.238.07:36:30.28#ibcon#read 6, iclass 23, count 0 2006.238.07:36:30.28#ibcon#end of sib2, iclass 23, count 0 2006.238.07:36:30.28#ibcon#*after write, iclass 23, count 0 2006.238.07:36:30.28#ibcon#*before return 0, iclass 23, count 0 2006.238.07:36:30.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:36:30.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:36:30.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:36:30.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:36:30.28$vc4f8/valo=8,852.99 2006.238.07:36:30.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.07:36:30.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.07:36:30.28#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:30.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:36:30.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:36:30.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:36:30.28#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:36:30.28#ibcon#first serial, iclass 25, count 0 2006.238.07:36:30.28#ibcon#enter sib2, iclass 25, count 0 2006.238.07:36:30.28#ibcon#flushed, iclass 25, count 0 2006.238.07:36:30.28#ibcon#about to write, iclass 25, count 0 2006.238.07:36:30.28#ibcon#wrote, iclass 25, count 0 2006.238.07:36:30.28#ibcon#about to read 3, iclass 25, count 0 2006.238.07:36:30.30#ibcon#read 3, iclass 25, count 0 2006.238.07:36:30.30#ibcon#about to read 4, iclass 25, count 0 2006.238.07:36:30.30#ibcon#read 4, iclass 25, count 0 2006.238.07:36:30.30#ibcon#about to read 5, iclass 25, count 0 2006.238.07:36:30.30#ibcon#read 5, iclass 25, count 0 2006.238.07:36:30.30#ibcon#about to read 6, iclass 25, count 0 2006.238.07:36:30.30#ibcon#read 6, iclass 25, count 0 2006.238.07:36:30.30#ibcon#end of sib2, iclass 25, count 0 2006.238.07:36:30.30#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:36:30.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:36:30.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:36:30.30#ibcon#*before write, iclass 25, count 0 2006.238.07:36:30.30#ibcon#enter sib2, iclass 25, count 0 2006.238.07:36:30.30#ibcon#flushed, iclass 25, count 0 2006.238.07:36:30.30#ibcon#about to write, iclass 25, count 0 2006.238.07:36:30.30#ibcon#wrote, iclass 25, count 0 2006.238.07:36:30.30#ibcon#about to read 3, iclass 25, count 0 2006.238.07:36:30.34#ibcon#read 3, iclass 25, count 0 2006.238.07:36:30.34#ibcon#about to read 4, iclass 25, count 0 2006.238.07:36:30.34#ibcon#read 4, iclass 25, count 0 2006.238.07:36:30.34#ibcon#about to read 5, iclass 25, count 0 2006.238.07:36:30.34#ibcon#read 5, iclass 25, count 0 2006.238.07:36:30.34#ibcon#about to read 6, iclass 25, count 0 2006.238.07:36:30.34#ibcon#read 6, iclass 25, count 0 2006.238.07:36:30.34#ibcon#end of sib2, iclass 25, count 0 2006.238.07:36:30.34#ibcon#*after write, iclass 25, count 0 2006.238.07:36:30.34#ibcon#*before return 0, iclass 25, count 0 2006.238.07:36:30.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:36:30.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:36:30.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:36:30.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:36:30.34$vc4f8/va=8,7 2006.238.07:36:30.34#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.07:36:30.34#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.07:36:30.34#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:30.34#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:36:30.36#abcon#<5=/04 1.6 3.1 25.34 881012.2\r\n> 2006.238.07:36:30.38#abcon#{5=INTERFACE CLEAR} 2006.238.07:36:30.40#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:36:30.40#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:36:30.40#ibcon#enter wrdev, iclass 28, count 2 2006.238.07:36:30.40#ibcon#first serial, iclass 28, count 2 2006.238.07:36:30.40#ibcon#enter sib2, iclass 28, count 2 2006.238.07:36:30.40#ibcon#flushed, iclass 28, count 2 2006.238.07:36:30.40#ibcon#about to write, iclass 28, count 2 2006.238.07:36:30.40#ibcon#wrote, iclass 28, count 2 2006.238.07:36:30.40#ibcon#about to read 3, iclass 28, count 2 2006.238.07:36:30.42#ibcon#read 3, iclass 28, count 2 2006.238.07:36:30.42#ibcon#about to read 4, iclass 28, count 2 2006.238.07:36:30.42#ibcon#read 4, iclass 28, count 2 2006.238.07:36:30.42#ibcon#about to read 5, iclass 28, count 2 2006.238.07:36:30.42#ibcon#read 5, iclass 28, count 2 2006.238.07:36:30.42#ibcon#about to read 6, iclass 28, count 2 2006.238.07:36:30.42#ibcon#read 6, iclass 28, count 2 2006.238.07:36:30.42#ibcon#end of sib2, iclass 28, count 2 2006.238.07:36:30.42#ibcon#*mode == 0, iclass 28, count 2 2006.238.07:36:30.42#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.07:36:30.42#ibcon#[25=AT08-07\r\n] 2006.238.07:36:30.42#ibcon#*before write, iclass 28, count 2 2006.238.07:36:30.42#ibcon#enter sib2, iclass 28, count 2 2006.238.07:36:30.42#ibcon#flushed, iclass 28, count 2 2006.238.07:36:30.42#ibcon#about to write, iclass 28, count 2 2006.238.07:36:30.42#ibcon#wrote, iclass 28, count 2 2006.238.07:36:30.42#ibcon#about to read 3, iclass 28, count 2 2006.238.07:36:30.44#abcon#[5=S1D000X0/0*\r\n] 2006.238.07:36:30.45#ibcon#read 3, iclass 28, count 2 2006.238.07:36:30.45#ibcon#about to read 4, iclass 28, count 2 2006.238.07:36:30.45#ibcon#read 4, iclass 28, count 2 2006.238.07:36:30.45#ibcon#about to read 5, iclass 28, count 2 2006.238.07:36:30.45#ibcon#read 5, iclass 28, count 2 2006.238.07:36:30.45#ibcon#about to read 6, iclass 28, count 2 2006.238.07:36:30.45#ibcon#read 6, iclass 28, count 2 2006.238.07:36:30.45#ibcon#end of sib2, iclass 28, count 2 2006.238.07:36:30.45#ibcon#*after write, iclass 28, count 2 2006.238.07:36:30.45#ibcon#*before return 0, iclass 28, count 2 2006.238.07:36:30.45#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:36:30.45#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:36:30.45#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.07:36:30.45#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:30.45#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:36:30.57#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:36:30.57#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:36:30.57#ibcon#enter wrdev, iclass 28, count 0 2006.238.07:36:30.57#ibcon#first serial, iclass 28, count 0 2006.238.07:36:30.57#ibcon#enter sib2, iclass 28, count 0 2006.238.07:36:30.57#ibcon#flushed, iclass 28, count 0 2006.238.07:36:30.57#ibcon#about to write, iclass 28, count 0 2006.238.07:36:30.57#ibcon#wrote, iclass 28, count 0 2006.238.07:36:30.57#ibcon#about to read 3, iclass 28, count 0 2006.238.07:36:30.59#ibcon#read 3, iclass 28, count 0 2006.238.07:36:30.59#ibcon#about to read 4, iclass 28, count 0 2006.238.07:36:30.59#ibcon#read 4, iclass 28, count 0 2006.238.07:36:30.59#ibcon#about to read 5, iclass 28, count 0 2006.238.07:36:30.59#ibcon#read 5, iclass 28, count 0 2006.238.07:36:30.59#ibcon#about to read 6, iclass 28, count 0 2006.238.07:36:30.59#ibcon#read 6, iclass 28, count 0 2006.238.07:36:30.59#ibcon#end of sib2, iclass 28, count 0 2006.238.07:36:30.59#ibcon#*mode == 0, iclass 28, count 0 2006.238.07:36:30.59#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.07:36:30.59#ibcon#[25=USB\r\n] 2006.238.07:36:30.59#ibcon#*before write, iclass 28, count 0 2006.238.07:36:30.59#ibcon#enter sib2, iclass 28, count 0 2006.238.07:36:30.59#ibcon#flushed, iclass 28, count 0 2006.238.07:36:30.59#ibcon#about to write, iclass 28, count 0 2006.238.07:36:30.59#ibcon#wrote, iclass 28, count 0 2006.238.07:36:30.59#ibcon#about to read 3, iclass 28, count 0 2006.238.07:36:30.62#ibcon#read 3, iclass 28, count 0 2006.238.07:36:30.62#ibcon#about to read 4, iclass 28, count 0 2006.238.07:36:30.62#ibcon#read 4, iclass 28, count 0 2006.238.07:36:30.62#ibcon#about to read 5, iclass 28, count 0 2006.238.07:36:30.62#ibcon#read 5, iclass 28, count 0 2006.238.07:36:30.62#ibcon#about to read 6, iclass 28, count 0 2006.238.07:36:30.62#ibcon#read 6, iclass 28, count 0 2006.238.07:36:30.62#ibcon#end of sib2, iclass 28, count 0 2006.238.07:36:30.62#ibcon#*after write, iclass 28, count 0 2006.238.07:36:30.62#ibcon#*before return 0, iclass 28, count 0 2006.238.07:36:30.62#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:36:30.62#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:36:30.62#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.07:36:30.62#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.07:36:30.62$vc4f8/vblo=1,632.99 2006.238.07:36:30.62#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.07:36:30.62#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.07:36:30.62#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:30.62#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:36:30.62#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:36:30.62#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:36:30.62#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:36:30.62#ibcon#first serial, iclass 33, count 0 2006.238.07:36:30.62#ibcon#enter sib2, iclass 33, count 0 2006.238.07:36:30.62#ibcon#flushed, iclass 33, count 0 2006.238.07:36:30.62#ibcon#about to write, iclass 33, count 0 2006.238.07:36:30.62#ibcon#wrote, iclass 33, count 0 2006.238.07:36:30.62#ibcon#about to read 3, iclass 33, count 0 2006.238.07:36:30.64#ibcon#read 3, iclass 33, count 0 2006.238.07:36:30.64#ibcon#about to read 4, iclass 33, count 0 2006.238.07:36:30.64#ibcon#read 4, iclass 33, count 0 2006.238.07:36:30.64#ibcon#about to read 5, iclass 33, count 0 2006.238.07:36:30.64#ibcon#read 5, iclass 33, count 0 2006.238.07:36:30.64#ibcon#about to read 6, iclass 33, count 0 2006.238.07:36:30.64#ibcon#read 6, iclass 33, count 0 2006.238.07:36:30.64#ibcon#end of sib2, iclass 33, count 0 2006.238.07:36:30.64#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:36:30.64#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:36:30.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:36:30.64#ibcon#*before write, iclass 33, count 0 2006.238.07:36:30.64#ibcon#enter sib2, iclass 33, count 0 2006.238.07:36:30.64#ibcon#flushed, iclass 33, count 0 2006.238.07:36:30.64#ibcon#about to write, iclass 33, count 0 2006.238.07:36:30.64#ibcon#wrote, iclass 33, count 0 2006.238.07:36:30.64#ibcon#about to read 3, iclass 33, count 0 2006.238.07:36:30.68#ibcon#read 3, iclass 33, count 0 2006.238.07:36:30.68#ibcon#about to read 4, iclass 33, count 0 2006.238.07:36:30.68#ibcon#read 4, iclass 33, count 0 2006.238.07:36:30.68#ibcon#about to read 5, iclass 33, count 0 2006.238.07:36:30.68#ibcon#read 5, iclass 33, count 0 2006.238.07:36:30.68#ibcon#about to read 6, iclass 33, count 0 2006.238.07:36:30.68#ibcon#read 6, iclass 33, count 0 2006.238.07:36:30.68#ibcon#end of sib2, iclass 33, count 0 2006.238.07:36:30.68#ibcon#*after write, iclass 33, count 0 2006.238.07:36:30.68#ibcon#*before return 0, iclass 33, count 0 2006.238.07:36:30.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:36:30.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:36:30.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:36:30.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:36:30.68$vc4f8/vb=1,4 2006.238.07:36:30.68#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.238.07:36:30.68#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.238.07:36:30.68#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:30.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:36:30.68#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:36:30.68#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:36:30.68#ibcon#enter wrdev, iclass 35, count 2 2006.238.07:36:30.68#ibcon#first serial, iclass 35, count 2 2006.238.07:36:30.68#ibcon#enter sib2, iclass 35, count 2 2006.238.07:36:30.68#ibcon#flushed, iclass 35, count 2 2006.238.07:36:30.68#ibcon#about to write, iclass 35, count 2 2006.238.07:36:30.68#ibcon#wrote, iclass 35, count 2 2006.238.07:36:30.68#ibcon#about to read 3, iclass 35, count 2 2006.238.07:36:30.70#ibcon#read 3, iclass 35, count 2 2006.238.07:36:30.70#ibcon#about to read 4, iclass 35, count 2 2006.238.07:36:30.70#ibcon#read 4, iclass 35, count 2 2006.238.07:36:30.70#ibcon#about to read 5, iclass 35, count 2 2006.238.07:36:30.70#ibcon#read 5, iclass 35, count 2 2006.238.07:36:30.70#ibcon#about to read 6, iclass 35, count 2 2006.238.07:36:30.70#ibcon#read 6, iclass 35, count 2 2006.238.07:36:30.70#ibcon#end of sib2, iclass 35, count 2 2006.238.07:36:30.70#ibcon#*mode == 0, iclass 35, count 2 2006.238.07:36:30.70#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.238.07:36:30.70#ibcon#[27=AT01-04\r\n] 2006.238.07:36:30.70#ibcon#*before write, iclass 35, count 2 2006.238.07:36:30.70#ibcon#enter sib2, iclass 35, count 2 2006.238.07:36:30.70#ibcon#flushed, iclass 35, count 2 2006.238.07:36:30.70#ibcon#about to write, iclass 35, count 2 2006.238.07:36:30.70#ibcon#wrote, iclass 35, count 2 2006.238.07:36:30.70#ibcon#about to read 3, iclass 35, count 2 2006.238.07:36:30.73#ibcon#read 3, iclass 35, count 2 2006.238.07:36:30.73#ibcon#about to read 4, iclass 35, count 2 2006.238.07:36:30.73#ibcon#read 4, iclass 35, count 2 2006.238.07:36:30.73#ibcon#about to read 5, iclass 35, count 2 2006.238.07:36:30.73#ibcon#read 5, iclass 35, count 2 2006.238.07:36:30.73#ibcon#about to read 6, iclass 35, count 2 2006.238.07:36:30.73#ibcon#read 6, iclass 35, count 2 2006.238.07:36:30.73#ibcon#end of sib2, iclass 35, count 2 2006.238.07:36:30.73#ibcon#*after write, iclass 35, count 2 2006.238.07:36:30.73#ibcon#*before return 0, iclass 35, count 2 2006.238.07:36:30.73#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:36:30.73#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:36:30.73#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.238.07:36:30.73#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:30.73#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:36:30.85#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:36:30.85#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:36:30.85#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:36:30.85#ibcon#first serial, iclass 35, count 0 2006.238.07:36:30.85#ibcon#enter sib2, iclass 35, count 0 2006.238.07:36:30.85#ibcon#flushed, iclass 35, count 0 2006.238.07:36:30.85#ibcon#about to write, iclass 35, count 0 2006.238.07:36:30.85#ibcon#wrote, iclass 35, count 0 2006.238.07:36:30.85#ibcon#about to read 3, iclass 35, count 0 2006.238.07:36:30.87#ibcon#read 3, iclass 35, count 0 2006.238.07:36:30.87#ibcon#about to read 4, iclass 35, count 0 2006.238.07:36:30.87#ibcon#read 4, iclass 35, count 0 2006.238.07:36:30.87#ibcon#about to read 5, iclass 35, count 0 2006.238.07:36:30.87#ibcon#read 5, iclass 35, count 0 2006.238.07:36:30.87#ibcon#about to read 6, iclass 35, count 0 2006.238.07:36:30.87#ibcon#read 6, iclass 35, count 0 2006.238.07:36:30.87#ibcon#end of sib2, iclass 35, count 0 2006.238.07:36:30.87#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:36:30.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:36:30.87#ibcon#[27=USB\r\n] 2006.238.07:36:30.87#ibcon#*before write, iclass 35, count 0 2006.238.07:36:30.87#ibcon#enter sib2, iclass 35, count 0 2006.238.07:36:30.87#ibcon#flushed, iclass 35, count 0 2006.238.07:36:30.87#ibcon#about to write, iclass 35, count 0 2006.238.07:36:30.87#ibcon#wrote, iclass 35, count 0 2006.238.07:36:30.87#ibcon#about to read 3, iclass 35, count 0 2006.238.07:36:30.90#ibcon#read 3, iclass 35, count 0 2006.238.07:36:30.90#ibcon#about to read 4, iclass 35, count 0 2006.238.07:36:30.90#ibcon#read 4, iclass 35, count 0 2006.238.07:36:30.90#ibcon#about to read 5, iclass 35, count 0 2006.238.07:36:30.90#ibcon#read 5, iclass 35, count 0 2006.238.07:36:30.90#ibcon#about to read 6, iclass 35, count 0 2006.238.07:36:30.90#ibcon#read 6, iclass 35, count 0 2006.238.07:36:30.90#ibcon#end of sib2, iclass 35, count 0 2006.238.07:36:30.90#ibcon#*after write, iclass 35, count 0 2006.238.07:36:30.90#ibcon#*before return 0, iclass 35, count 0 2006.238.07:36:30.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:36:30.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:36:30.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:36:30.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:36:30.90$vc4f8/vblo=2,640.99 2006.238.07:36:30.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.07:36:30.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.07:36:30.90#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:30.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:36:30.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:36:30.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:36:30.90#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:36:30.90#ibcon#first serial, iclass 37, count 0 2006.238.07:36:30.90#ibcon#enter sib2, iclass 37, count 0 2006.238.07:36:30.90#ibcon#flushed, iclass 37, count 0 2006.238.07:36:30.90#ibcon#about to write, iclass 37, count 0 2006.238.07:36:30.90#ibcon#wrote, iclass 37, count 0 2006.238.07:36:30.90#ibcon#about to read 3, iclass 37, count 0 2006.238.07:36:30.92#ibcon#read 3, iclass 37, count 0 2006.238.07:36:30.92#ibcon#about to read 4, iclass 37, count 0 2006.238.07:36:30.92#ibcon#read 4, iclass 37, count 0 2006.238.07:36:30.92#ibcon#about to read 5, iclass 37, count 0 2006.238.07:36:30.92#ibcon#read 5, iclass 37, count 0 2006.238.07:36:30.92#ibcon#about to read 6, iclass 37, count 0 2006.238.07:36:30.92#ibcon#read 6, iclass 37, count 0 2006.238.07:36:30.92#ibcon#end of sib2, iclass 37, count 0 2006.238.07:36:30.92#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:36:30.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:36:30.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:36:30.92#ibcon#*before write, iclass 37, count 0 2006.238.07:36:30.92#ibcon#enter sib2, iclass 37, count 0 2006.238.07:36:30.92#ibcon#flushed, iclass 37, count 0 2006.238.07:36:30.92#ibcon#about to write, iclass 37, count 0 2006.238.07:36:30.92#ibcon#wrote, iclass 37, count 0 2006.238.07:36:30.92#ibcon#about to read 3, iclass 37, count 0 2006.238.07:36:30.96#ibcon#read 3, iclass 37, count 0 2006.238.07:36:30.96#ibcon#about to read 4, iclass 37, count 0 2006.238.07:36:30.96#ibcon#read 4, iclass 37, count 0 2006.238.07:36:30.96#ibcon#about to read 5, iclass 37, count 0 2006.238.07:36:30.96#ibcon#read 5, iclass 37, count 0 2006.238.07:36:30.96#ibcon#about to read 6, iclass 37, count 0 2006.238.07:36:30.96#ibcon#read 6, iclass 37, count 0 2006.238.07:36:30.96#ibcon#end of sib2, iclass 37, count 0 2006.238.07:36:30.96#ibcon#*after write, iclass 37, count 0 2006.238.07:36:30.96#ibcon#*before return 0, iclass 37, count 0 2006.238.07:36:30.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:36:30.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:36:30.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:36:30.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:36:30.96$vc4f8/vb=2,4 2006.238.07:36:30.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.238.07:36:30.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.238.07:36:30.96#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:30.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:36:31.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:36:31.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:36:31.02#ibcon#enter wrdev, iclass 39, count 2 2006.238.07:36:31.02#ibcon#first serial, iclass 39, count 2 2006.238.07:36:31.02#ibcon#enter sib2, iclass 39, count 2 2006.238.07:36:31.02#ibcon#flushed, iclass 39, count 2 2006.238.07:36:31.02#ibcon#about to write, iclass 39, count 2 2006.238.07:36:31.02#ibcon#wrote, iclass 39, count 2 2006.238.07:36:31.02#ibcon#about to read 3, iclass 39, count 2 2006.238.07:36:31.04#ibcon#read 3, iclass 39, count 2 2006.238.07:36:31.04#ibcon#about to read 4, iclass 39, count 2 2006.238.07:36:31.04#ibcon#read 4, iclass 39, count 2 2006.238.07:36:31.04#ibcon#about to read 5, iclass 39, count 2 2006.238.07:36:31.04#ibcon#read 5, iclass 39, count 2 2006.238.07:36:31.04#ibcon#about to read 6, iclass 39, count 2 2006.238.07:36:31.04#ibcon#read 6, iclass 39, count 2 2006.238.07:36:31.04#ibcon#end of sib2, iclass 39, count 2 2006.238.07:36:31.04#ibcon#*mode == 0, iclass 39, count 2 2006.238.07:36:31.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.238.07:36:31.04#ibcon#[27=AT02-04\r\n] 2006.238.07:36:31.04#ibcon#*before write, iclass 39, count 2 2006.238.07:36:31.04#ibcon#enter sib2, iclass 39, count 2 2006.238.07:36:31.04#ibcon#flushed, iclass 39, count 2 2006.238.07:36:31.04#ibcon#about to write, iclass 39, count 2 2006.238.07:36:31.04#ibcon#wrote, iclass 39, count 2 2006.238.07:36:31.04#ibcon#about to read 3, iclass 39, count 2 2006.238.07:36:31.07#ibcon#read 3, iclass 39, count 2 2006.238.07:36:31.07#ibcon#about to read 4, iclass 39, count 2 2006.238.07:36:31.07#ibcon#read 4, iclass 39, count 2 2006.238.07:36:31.07#ibcon#about to read 5, iclass 39, count 2 2006.238.07:36:31.07#ibcon#read 5, iclass 39, count 2 2006.238.07:36:31.07#ibcon#about to read 6, iclass 39, count 2 2006.238.07:36:31.07#ibcon#read 6, iclass 39, count 2 2006.238.07:36:31.07#ibcon#end of sib2, iclass 39, count 2 2006.238.07:36:31.07#ibcon#*after write, iclass 39, count 2 2006.238.07:36:31.07#ibcon#*before return 0, iclass 39, count 2 2006.238.07:36:31.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:36:31.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:36:31.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.238.07:36:31.07#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:31.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:36:31.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:36:31.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:36:31.19#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:36:31.19#ibcon#first serial, iclass 39, count 0 2006.238.07:36:31.19#ibcon#enter sib2, iclass 39, count 0 2006.238.07:36:31.19#ibcon#flushed, iclass 39, count 0 2006.238.07:36:31.19#ibcon#about to write, iclass 39, count 0 2006.238.07:36:31.19#ibcon#wrote, iclass 39, count 0 2006.238.07:36:31.19#ibcon#about to read 3, iclass 39, count 0 2006.238.07:36:31.21#ibcon#read 3, iclass 39, count 0 2006.238.07:36:31.21#ibcon#about to read 4, iclass 39, count 0 2006.238.07:36:31.21#ibcon#read 4, iclass 39, count 0 2006.238.07:36:31.21#ibcon#about to read 5, iclass 39, count 0 2006.238.07:36:31.21#ibcon#read 5, iclass 39, count 0 2006.238.07:36:31.21#ibcon#about to read 6, iclass 39, count 0 2006.238.07:36:31.21#ibcon#read 6, iclass 39, count 0 2006.238.07:36:31.21#ibcon#end of sib2, iclass 39, count 0 2006.238.07:36:31.21#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:36:31.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:36:31.21#ibcon#[27=USB\r\n] 2006.238.07:36:31.21#ibcon#*before write, iclass 39, count 0 2006.238.07:36:31.21#ibcon#enter sib2, iclass 39, count 0 2006.238.07:36:31.21#ibcon#flushed, iclass 39, count 0 2006.238.07:36:31.21#ibcon#about to write, iclass 39, count 0 2006.238.07:36:31.21#ibcon#wrote, iclass 39, count 0 2006.238.07:36:31.21#ibcon#about to read 3, iclass 39, count 0 2006.238.07:36:31.24#ibcon#read 3, iclass 39, count 0 2006.238.07:36:31.24#ibcon#about to read 4, iclass 39, count 0 2006.238.07:36:31.24#ibcon#read 4, iclass 39, count 0 2006.238.07:36:31.24#ibcon#about to read 5, iclass 39, count 0 2006.238.07:36:31.24#ibcon#read 5, iclass 39, count 0 2006.238.07:36:31.24#ibcon#about to read 6, iclass 39, count 0 2006.238.07:36:31.24#ibcon#read 6, iclass 39, count 0 2006.238.07:36:31.24#ibcon#end of sib2, iclass 39, count 0 2006.238.07:36:31.24#ibcon#*after write, iclass 39, count 0 2006.238.07:36:31.24#ibcon#*before return 0, iclass 39, count 0 2006.238.07:36:31.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:36:31.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:36:31.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:36:31.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:36:31.24$vc4f8/vblo=3,656.99 2006.238.07:36:31.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.07:36:31.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.07:36:31.24#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:31.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:36:31.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:36:31.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:36:31.24#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:36:31.24#ibcon#first serial, iclass 3, count 0 2006.238.07:36:31.24#ibcon#enter sib2, iclass 3, count 0 2006.238.07:36:31.24#ibcon#flushed, iclass 3, count 0 2006.238.07:36:31.24#ibcon#about to write, iclass 3, count 0 2006.238.07:36:31.24#ibcon#wrote, iclass 3, count 0 2006.238.07:36:31.24#ibcon#about to read 3, iclass 3, count 0 2006.238.07:36:31.26#ibcon#read 3, iclass 3, count 0 2006.238.07:36:31.26#ibcon#about to read 4, iclass 3, count 0 2006.238.07:36:31.26#ibcon#read 4, iclass 3, count 0 2006.238.07:36:31.26#ibcon#about to read 5, iclass 3, count 0 2006.238.07:36:31.26#ibcon#read 5, iclass 3, count 0 2006.238.07:36:31.26#ibcon#about to read 6, iclass 3, count 0 2006.238.07:36:31.26#ibcon#read 6, iclass 3, count 0 2006.238.07:36:31.26#ibcon#end of sib2, iclass 3, count 0 2006.238.07:36:31.26#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:36:31.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:36:31.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:36:31.26#ibcon#*before write, iclass 3, count 0 2006.238.07:36:31.26#ibcon#enter sib2, iclass 3, count 0 2006.238.07:36:31.26#ibcon#flushed, iclass 3, count 0 2006.238.07:36:31.26#ibcon#about to write, iclass 3, count 0 2006.238.07:36:31.26#ibcon#wrote, iclass 3, count 0 2006.238.07:36:31.26#ibcon#about to read 3, iclass 3, count 0 2006.238.07:36:31.30#ibcon#read 3, iclass 3, count 0 2006.238.07:36:31.30#ibcon#about to read 4, iclass 3, count 0 2006.238.07:36:31.30#ibcon#read 4, iclass 3, count 0 2006.238.07:36:31.30#ibcon#about to read 5, iclass 3, count 0 2006.238.07:36:31.30#ibcon#read 5, iclass 3, count 0 2006.238.07:36:31.30#ibcon#about to read 6, iclass 3, count 0 2006.238.07:36:31.30#ibcon#read 6, iclass 3, count 0 2006.238.07:36:31.30#ibcon#end of sib2, iclass 3, count 0 2006.238.07:36:31.30#ibcon#*after write, iclass 3, count 0 2006.238.07:36:31.30#ibcon#*before return 0, iclass 3, count 0 2006.238.07:36:31.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:36:31.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:36:31.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:36:31.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:36:31.30$vc4f8/vb=3,4 2006.238.07:36:31.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.238.07:36:31.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.238.07:36:31.30#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:31.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:36:31.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:36:31.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:36:31.36#ibcon#enter wrdev, iclass 5, count 2 2006.238.07:36:31.36#ibcon#first serial, iclass 5, count 2 2006.238.07:36:31.36#ibcon#enter sib2, iclass 5, count 2 2006.238.07:36:31.36#ibcon#flushed, iclass 5, count 2 2006.238.07:36:31.36#ibcon#about to write, iclass 5, count 2 2006.238.07:36:31.36#ibcon#wrote, iclass 5, count 2 2006.238.07:36:31.36#ibcon#about to read 3, iclass 5, count 2 2006.238.07:36:31.38#ibcon#read 3, iclass 5, count 2 2006.238.07:36:31.38#ibcon#about to read 4, iclass 5, count 2 2006.238.07:36:31.38#ibcon#read 4, iclass 5, count 2 2006.238.07:36:31.38#ibcon#about to read 5, iclass 5, count 2 2006.238.07:36:31.38#ibcon#read 5, iclass 5, count 2 2006.238.07:36:31.38#ibcon#about to read 6, iclass 5, count 2 2006.238.07:36:31.38#ibcon#read 6, iclass 5, count 2 2006.238.07:36:31.38#ibcon#end of sib2, iclass 5, count 2 2006.238.07:36:31.38#ibcon#*mode == 0, iclass 5, count 2 2006.238.07:36:31.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.238.07:36:31.38#ibcon#[27=AT03-04\r\n] 2006.238.07:36:31.38#ibcon#*before write, iclass 5, count 2 2006.238.07:36:31.38#ibcon#enter sib2, iclass 5, count 2 2006.238.07:36:31.38#ibcon#flushed, iclass 5, count 2 2006.238.07:36:31.38#ibcon#about to write, iclass 5, count 2 2006.238.07:36:31.38#ibcon#wrote, iclass 5, count 2 2006.238.07:36:31.38#ibcon#about to read 3, iclass 5, count 2 2006.238.07:36:31.41#ibcon#read 3, iclass 5, count 2 2006.238.07:36:31.41#ibcon#about to read 4, iclass 5, count 2 2006.238.07:36:31.41#ibcon#read 4, iclass 5, count 2 2006.238.07:36:31.41#ibcon#about to read 5, iclass 5, count 2 2006.238.07:36:31.41#ibcon#read 5, iclass 5, count 2 2006.238.07:36:31.41#ibcon#about to read 6, iclass 5, count 2 2006.238.07:36:31.41#ibcon#read 6, iclass 5, count 2 2006.238.07:36:31.41#ibcon#end of sib2, iclass 5, count 2 2006.238.07:36:31.41#ibcon#*after write, iclass 5, count 2 2006.238.07:36:31.41#ibcon#*before return 0, iclass 5, count 2 2006.238.07:36:31.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:36:31.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:36:31.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.238.07:36:31.41#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:31.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:36:31.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:36:31.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:36:31.53#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:36:31.53#ibcon#first serial, iclass 5, count 0 2006.238.07:36:31.53#ibcon#enter sib2, iclass 5, count 0 2006.238.07:36:31.53#ibcon#flushed, iclass 5, count 0 2006.238.07:36:31.53#ibcon#about to write, iclass 5, count 0 2006.238.07:36:31.53#ibcon#wrote, iclass 5, count 0 2006.238.07:36:31.53#ibcon#about to read 3, iclass 5, count 0 2006.238.07:36:31.55#ibcon#read 3, iclass 5, count 0 2006.238.07:36:31.55#ibcon#about to read 4, iclass 5, count 0 2006.238.07:36:31.55#ibcon#read 4, iclass 5, count 0 2006.238.07:36:31.55#ibcon#about to read 5, iclass 5, count 0 2006.238.07:36:31.55#ibcon#read 5, iclass 5, count 0 2006.238.07:36:31.55#ibcon#about to read 6, iclass 5, count 0 2006.238.07:36:31.55#ibcon#read 6, iclass 5, count 0 2006.238.07:36:31.55#ibcon#end of sib2, iclass 5, count 0 2006.238.07:36:31.55#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:36:31.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:36:31.55#ibcon#[27=USB\r\n] 2006.238.07:36:31.55#ibcon#*before write, iclass 5, count 0 2006.238.07:36:31.55#ibcon#enter sib2, iclass 5, count 0 2006.238.07:36:31.55#ibcon#flushed, iclass 5, count 0 2006.238.07:36:31.55#ibcon#about to write, iclass 5, count 0 2006.238.07:36:31.55#ibcon#wrote, iclass 5, count 0 2006.238.07:36:31.55#ibcon#about to read 3, iclass 5, count 0 2006.238.07:36:31.58#ibcon#read 3, iclass 5, count 0 2006.238.07:36:31.58#ibcon#about to read 4, iclass 5, count 0 2006.238.07:36:31.58#ibcon#read 4, iclass 5, count 0 2006.238.07:36:31.58#ibcon#about to read 5, iclass 5, count 0 2006.238.07:36:31.58#ibcon#read 5, iclass 5, count 0 2006.238.07:36:31.58#ibcon#about to read 6, iclass 5, count 0 2006.238.07:36:31.58#ibcon#read 6, iclass 5, count 0 2006.238.07:36:31.58#ibcon#end of sib2, iclass 5, count 0 2006.238.07:36:31.58#ibcon#*after write, iclass 5, count 0 2006.238.07:36:31.58#ibcon#*before return 0, iclass 5, count 0 2006.238.07:36:31.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:36:31.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:36:31.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:36:31.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:36:31.58$vc4f8/vblo=4,712.99 2006.238.07:36:31.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.238.07:36:31.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.238.07:36:31.58#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:31.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:36:31.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:36:31.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:36:31.58#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:36:31.58#ibcon#first serial, iclass 7, count 0 2006.238.07:36:31.58#ibcon#enter sib2, iclass 7, count 0 2006.238.07:36:31.58#ibcon#flushed, iclass 7, count 0 2006.238.07:36:31.58#ibcon#about to write, iclass 7, count 0 2006.238.07:36:31.58#ibcon#wrote, iclass 7, count 0 2006.238.07:36:31.58#ibcon#about to read 3, iclass 7, count 0 2006.238.07:36:31.60#ibcon#read 3, iclass 7, count 0 2006.238.07:36:31.60#ibcon#about to read 4, iclass 7, count 0 2006.238.07:36:31.60#ibcon#read 4, iclass 7, count 0 2006.238.07:36:31.60#ibcon#about to read 5, iclass 7, count 0 2006.238.07:36:31.60#ibcon#read 5, iclass 7, count 0 2006.238.07:36:31.60#ibcon#about to read 6, iclass 7, count 0 2006.238.07:36:31.60#ibcon#read 6, iclass 7, count 0 2006.238.07:36:31.60#ibcon#end of sib2, iclass 7, count 0 2006.238.07:36:31.60#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:36:31.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:36:31.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:36:31.60#ibcon#*before write, iclass 7, count 0 2006.238.07:36:31.60#ibcon#enter sib2, iclass 7, count 0 2006.238.07:36:31.60#ibcon#flushed, iclass 7, count 0 2006.238.07:36:31.60#ibcon#about to write, iclass 7, count 0 2006.238.07:36:31.60#ibcon#wrote, iclass 7, count 0 2006.238.07:36:31.60#ibcon#about to read 3, iclass 7, count 0 2006.238.07:36:31.64#ibcon#read 3, iclass 7, count 0 2006.238.07:36:31.64#ibcon#about to read 4, iclass 7, count 0 2006.238.07:36:31.64#ibcon#read 4, iclass 7, count 0 2006.238.07:36:31.64#ibcon#about to read 5, iclass 7, count 0 2006.238.07:36:31.64#ibcon#read 5, iclass 7, count 0 2006.238.07:36:31.64#ibcon#about to read 6, iclass 7, count 0 2006.238.07:36:31.64#ibcon#read 6, iclass 7, count 0 2006.238.07:36:31.64#ibcon#end of sib2, iclass 7, count 0 2006.238.07:36:31.64#ibcon#*after write, iclass 7, count 0 2006.238.07:36:31.64#ibcon#*before return 0, iclass 7, count 0 2006.238.07:36:31.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:36:31.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:36:31.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:36:31.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:36:31.64$vc4f8/vb=4,4 2006.238.07:36:31.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.238.07:36:31.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.238.07:36:31.64#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:31.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:36:31.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:36:31.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:36:31.70#ibcon#enter wrdev, iclass 11, count 2 2006.238.07:36:31.70#ibcon#first serial, iclass 11, count 2 2006.238.07:36:31.70#ibcon#enter sib2, iclass 11, count 2 2006.238.07:36:31.70#ibcon#flushed, iclass 11, count 2 2006.238.07:36:31.70#ibcon#about to write, iclass 11, count 2 2006.238.07:36:31.70#ibcon#wrote, iclass 11, count 2 2006.238.07:36:31.70#ibcon#about to read 3, iclass 11, count 2 2006.238.07:36:31.72#ibcon#read 3, iclass 11, count 2 2006.238.07:36:31.72#ibcon#about to read 4, iclass 11, count 2 2006.238.07:36:31.72#ibcon#read 4, iclass 11, count 2 2006.238.07:36:31.72#ibcon#about to read 5, iclass 11, count 2 2006.238.07:36:31.72#ibcon#read 5, iclass 11, count 2 2006.238.07:36:31.72#ibcon#about to read 6, iclass 11, count 2 2006.238.07:36:31.72#ibcon#read 6, iclass 11, count 2 2006.238.07:36:31.72#ibcon#end of sib2, iclass 11, count 2 2006.238.07:36:31.72#ibcon#*mode == 0, iclass 11, count 2 2006.238.07:36:31.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.238.07:36:31.72#ibcon#[27=AT04-04\r\n] 2006.238.07:36:31.72#ibcon#*before write, iclass 11, count 2 2006.238.07:36:31.72#ibcon#enter sib2, iclass 11, count 2 2006.238.07:36:31.72#ibcon#flushed, iclass 11, count 2 2006.238.07:36:31.72#ibcon#about to write, iclass 11, count 2 2006.238.07:36:31.72#ibcon#wrote, iclass 11, count 2 2006.238.07:36:31.72#ibcon#about to read 3, iclass 11, count 2 2006.238.07:36:31.75#ibcon#read 3, iclass 11, count 2 2006.238.07:36:31.75#ibcon#about to read 4, iclass 11, count 2 2006.238.07:36:31.75#ibcon#read 4, iclass 11, count 2 2006.238.07:36:31.75#ibcon#about to read 5, iclass 11, count 2 2006.238.07:36:31.75#ibcon#read 5, iclass 11, count 2 2006.238.07:36:31.75#ibcon#about to read 6, iclass 11, count 2 2006.238.07:36:31.75#ibcon#read 6, iclass 11, count 2 2006.238.07:36:31.75#ibcon#end of sib2, iclass 11, count 2 2006.238.07:36:31.75#ibcon#*after write, iclass 11, count 2 2006.238.07:36:31.75#ibcon#*before return 0, iclass 11, count 2 2006.238.07:36:31.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:36:31.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:36:31.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.238.07:36:31.75#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:31.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:36:31.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:36:31.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:36:31.87#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:36:31.87#ibcon#first serial, iclass 11, count 0 2006.238.07:36:31.87#ibcon#enter sib2, iclass 11, count 0 2006.238.07:36:31.87#ibcon#flushed, iclass 11, count 0 2006.238.07:36:31.87#ibcon#about to write, iclass 11, count 0 2006.238.07:36:31.87#ibcon#wrote, iclass 11, count 0 2006.238.07:36:31.87#ibcon#about to read 3, iclass 11, count 0 2006.238.07:36:31.89#ibcon#read 3, iclass 11, count 0 2006.238.07:36:31.89#ibcon#about to read 4, iclass 11, count 0 2006.238.07:36:31.89#ibcon#read 4, iclass 11, count 0 2006.238.07:36:31.89#ibcon#about to read 5, iclass 11, count 0 2006.238.07:36:31.89#ibcon#read 5, iclass 11, count 0 2006.238.07:36:31.89#ibcon#about to read 6, iclass 11, count 0 2006.238.07:36:31.89#ibcon#read 6, iclass 11, count 0 2006.238.07:36:31.89#ibcon#end of sib2, iclass 11, count 0 2006.238.07:36:31.89#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:36:31.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:36:31.89#ibcon#[27=USB\r\n] 2006.238.07:36:31.89#ibcon#*before write, iclass 11, count 0 2006.238.07:36:31.89#ibcon#enter sib2, iclass 11, count 0 2006.238.07:36:31.89#ibcon#flushed, iclass 11, count 0 2006.238.07:36:31.89#ibcon#about to write, iclass 11, count 0 2006.238.07:36:31.89#ibcon#wrote, iclass 11, count 0 2006.238.07:36:31.89#ibcon#about to read 3, iclass 11, count 0 2006.238.07:36:31.92#ibcon#read 3, iclass 11, count 0 2006.238.07:36:31.92#ibcon#about to read 4, iclass 11, count 0 2006.238.07:36:31.92#ibcon#read 4, iclass 11, count 0 2006.238.07:36:31.92#ibcon#about to read 5, iclass 11, count 0 2006.238.07:36:31.92#ibcon#read 5, iclass 11, count 0 2006.238.07:36:31.92#ibcon#about to read 6, iclass 11, count 0 2006.238.07:36:31.92#ibcon#read 6, iclass 11, count 0 2006.238.07:36:31.92#ibcon#end of sib2, iclass 11, count 0 2006.238.07:36:31.92#ibcon#*after write, iclass 11, count 0 2006.238.07:36:31.92#ibcon#*before return 0, iclass 11, count 0 2006.238.07:36:31.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:36:31.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:36:31.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:36:31.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:36:31.92$vc4f8/vblo=5,744.99 2006.238.07:36:31.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.07:36:31.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.07:36:31.92#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:31.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:36:31.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:36:31.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:36:31.92#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:36:31.92#ibcon#first serial, iclass 13, count 0 2006.238.07:36:31.92#ibcon#enter sib2, iclass 13, count 0 2006.238.07:36:31.92#ibcon#flushed, iclass 13, count 0 2006.238.07:36:31.92#ibcon#about to write, iclass 13, count 0 2006.238.07:36:31.92#ibcon#wrote, iclass 13, count 0 2006.238.07:36:31.92#ibcon#about to read 3, iclass 13, count 0 2006.238.07:36:31.94#ibcon#read 3, iclass 13, count 0 2006.238.07:36:31.94#ibcon#about to read 4, iclass 13, count 0 2006.238.07:36:31.94#ibcon#read 4, iclass 13, count 0 2006.238.07:36:31.94#ibcon#about to read 5, iclass 13, count 0 2006.238.07:36:31.94#ibcon#read 5, iclass 13, count 0 2006.238.07:36:31.94#ibcon#about to read 6, iclass 13, count 0 2006.238.07:36:31.94#ibcon#read 6, iclass 13, count 0 2006.238.07:36:31.94#ibcon#end of sib2, iclass 13, count 0 2006.238.07:36:31.94#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:36:31.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:36:31.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:36:31.94#ibcon#*before write, iclass 13, count 0 2006.238.07:36:31.94#ibcon#enter sib2, iclass 13, count 0 2006.238.07:36:31.94#ibcon#flushed, iclass 13, count 0 2006.238.07:36:31.94#ibcon#about to write, iclass 13, count 0 2006.238.07:36:31.94#ibcon#wrote, iclass 13, count 0 2006.238.07:36:31.94#ibcon#about to read 3, iclass 13, count 0 2006.238.07:36:31.98#ibcon#read 3, iclass 13, count 0 2006.238.07:36:31.98#ibcon#about to read 4, iclass 13, count 0 2006.238.07:36:31.98#ibcon#read 4, iclass 13, count 0 2006.238.07:36:31.98#ibcon#about to read 5, iclass 13, count 0 2006.238.07:36:31.98#ibcon#read 5, iclass 13, count 0 2006.238.07:36:31.98#ibcon#about to read 6, iclass 13, count 0 2006.238.07:36:31.98#ibcon#read 6, iclass 13, count 0 2006.238.07:36:31.98#ibcon#end of sib2, iclass 13, count 0 2006.238.07:36:31.98#ibcon#*after write, iclass 13, count 0 2006.238.07:36:31.98#ibcon#*before return 0, iclass 13, count 0 2006.238.07:36:31.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:36:31.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:36:31.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:36:31.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:36:31.98$vc4f8/vb=5,4 2006.238.07:36:31.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.238.07:36:31.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.238.07:36:31.98#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:31.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:36:32.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:36:32.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:36:32.04#ibcon#enter wrdev, iclass 15, count 2 2006.238.07:36:32.04#ibcon#first serial, iclass 15, count 2 2006.238.07:36:32.04#ibcon#enter sib2, iclass 15, count 2 2006.238.07:36:32.04#ibcon#flushed, iclass 15, count 2 2006.238.07:36:32.04#ibcon#about to write, iclass 15, count 2 2006.238.07:36:32.04#ibcon#wrote, iclass 15, count 2 2006.238.07:36:32.04#ibcon#about to read 3, iclass 15, count 2 2006.238.07:36:32.06#ibcon#read 3, iclass 15, count 2 2006.238.07:36:32.06#ibcon#about to read 4, iclass 15, count 2 2006.238.07:36:32.06#ibcon#read 4, iclass 15, count 2 2006.238.07:36:32.06#ibcon#about to read 5, iclass 15, count 2 2006.238.07:36:32.06#ibcon#read 5, iclass 15, count 2 2006.238.07:36:32.06#ibcon#about to read 6, iclass 15, count 2 2006.238.07:36:32.06#ibcon#read 6, iclass 15, count 2 2006.238.07:36:32.06#ibcon#end of sib2, iclass 15, count 2 2006.238.07:36:32.06#ibcon#*mode == 0, iclass 15, count 2 2006.238.07:36:32.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.238.07:36:32.06#ibcon#[27=AT05-04\r\n] 2006.238.07:36:32.06#ibcon#*before write, iclass 15, count 2 2006.238.07:36:32.06#ibcon#enter sib2, iclass 15, count 2 2006.238.07:36:32.06#ibcon#flushed, iclass 15, count 2 2006.238.07:36:32.06#ibcon#about to write, iclass 15, count 2 2006.238.07:36:32.06#ibcon#wrote, iclass 15, count 2 2006.238.07:36:32.06#ibcon#about to read 3, iclass 15, count 2 2006.238.07:36:32.09#ibcon#read 3, iclass 15, count 2 2006.238.07:36:32.09#ibcon#about to read 4, iclass 15, count 2 2006.238.07:36:32.09#ibcon#read 4, iclass 15, count 2 2006.238.07:36:32.09#ibcon#about to read 5, iclass 15, count 2 2006.238.07:36:32.09#ibcon#read 5, iclass 15, count 2 2006.238.07:36:32.09#ibcon#about to read 6, iclass 15, count 2 2006.238.07:36:32.09#ibcon#read 6, iclass 15, count 2 2006.238.07:36:32.09#ibcon#end of sib2, iclass 15, count 2 2006.238.07:36:32.09#ibcon#*after write, iclass 15, count 2 2006.238.07:36:32.09#ibcon#*before return 0, iclass 15, count 2 2006.238.07:36:32.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:36:32.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:36:32.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.238.07:36:32.09#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:32.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:36:32.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:36:32.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:36:32.21#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:36:32.21#ibcon#first serial, iclass 15, count 0 2006.238.07:36:32.21#ibcon#enter sib2, iclass 15, count 0 2006.238.07:36:32.21#ibcon#flushed, iclass 15, count 0 2006.238.07:36:32.21#ibcon#about to write, iclass 15, count 0 2006.238.07:36:32.21#ibcon#wrote, iclass 15, count 0 2006.238.07:36:32.21#ibcon#about to read 3, iclass 15, count 0 2006.238.07:36:32.23#ibcon#read 3, iclass 15, count 0 2006.238.07:36:32.23#ibcon#about to read 4, iclass 15, count 0 2006.238.07:36:32.23#ibcon#read 4, iclass 15, count 0 2006.238.07:36:32.23#ibcon#about to read 5, iclass 15, count 0 2006.238.07:36:32.23#ibcon#read 5, iclass 15, count 0 2006.238.07:36:32.23#ibcon#about to read 6, iclass 15, count 0 2006.238.07:36:32.23#ibcon#read 6, iclass 15, count 0 2006.238.07:36:32.23#ibcon#end of sib2, iclass 15, count 0 2006.238.07:36:32.23#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:36:32.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:36:32.23#ibcon#[27=USB\r\n] 2006.238.07:36:32.23#ibcon#*before write, iclass 15, count 0 2006.238.07:36:32.23#ibcon#enter sib2, iclass 15, count 0 2006.238.07:36:32.23#ibcon#flushed, iclass 15, count 0 2006.238.07:36:32.23#ibcon#about to write, iclass 15, count 0 2006.238.07:36:32.23#ibcon#wrote, iclass 15, count 0 2006.238.07:36:32.23#ibcon#about to read 3, iclass 15, count 0 2006.238.07:36:32.26#ibcon#read 3, iclass 15, count 0 2006.238.07:36:32.26#ibcon#about to read 4, iclass 15, count 0 2006.238.07:36:32.26#ibcon#read 4, iclass 15, count 0 2006.238.07:36:32.26#ibcon#about to read 5, iclass 15, count 0 2006.238.07:36:32.26#ibcon#read 5, iclass 15, count 0 2006.238.07:36:32.26#ibcon#about to read 6, iclass 15, count 0 2006.238.07:36:32.26#ibcon#read 6, iclass 15, count 0 2006.238.07:36:32.26#ibcon#end of sib2, iclass 15, count 0 2006.238.07:36:32.26#ibcon#*after write, iclass 15, count 0 2006.238.07:36:32.26#ibcon#*before return 0, iclass 15, count 0 2006.238.07:36:32.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:36:32.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:36:32.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:36:32.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:36:32.26$vc4f8/vblo=6,752.99 2006.238.07:36:32.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.07:36:32.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.07:36:32.26#ibcon#ireg 17 cls_cnt 0 2006.238.07:36:32.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:36:32.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:36:32.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:36:32.26#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:36:32.26#ibcon#first serial, iclass 17, count 0 2006.238.07:36:32.26#ibcon#enter sib2, iclass 17, count 0 2006.238.07:36:32.26#ibcon#flushed, iclass 17, count 0 2006.238.07:36:32.26#ibcon#about to write, iclass 17, count 0 2006.238.07:36:32.26#ibcon#wrote, iclass 17, count 0 2006.238.07:36:32.26#ibcon#about to read 3, iclass 17, count 0 2006.238.07:36:32.28#ibcon#read 3, iclass 17, count 0 2006.238.07:36:32.28#ibcon#about to read 4, iclass 17, count 0 2006.238.07:36:32.28#ibcon#read 4, iclass 17, count 0 2006.238.07:36:32.28#ibcon#about to read 5, iclass 17, count 0 2006.238.07:36:32.28#ibcon#read 5, iclass 17, count 0 2006.238.07:36:32.28#ibcon#about to read 6, iclass 17, count 0 2006.238.07:36:32.28#ibcon#read 6, iclass 17, count 0 2006.238.07:36:32.28#ibcon#end of sib2, iclass 17, count 0 2006.238.07:36:32.28#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:36:32.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:36:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:36:32.28#ibcon#*before write, iclass 17, count 0 2006.238.07:36:32.28#ibcon#enter sib2, iclass 17, count 0 2006.238.07:36:32.28#ibcon#flushed, iclass 17, count 0 2006.238.07:36:32.28#ibcon#about to write, iclass 17, count 0 2006.238.07:36:32.28#ibcon#wrote, iclass 17, count 0 2006.238.07:36:32.28#ibcon#about to read 3, iclass 17, count 0 2006.238.07:36:32.32#ibcon#read 3, iclass 17, count 0 2006.238.07:36:32.32#ibcon#about to read 4, iclass 17, count 0 2006.238.07:36:32.32#ibcon#read 4, iclass 17, count 0 2006.238.07:36:32.32#ibcon#about to read 5, iclass 17, count 0 2006.238.07:36:32.32#ibcon#read 5, iclass 17, count 0 2006.238.07:36:32.32#ibcon#about to read 6, iclass 17, count 0 2006.238.07:36:32.32#ibcon#read 6, iclass 17, count 0 2006.238.07:36:32.32#ibcon#end of sib2, iclass 17, count 0 2006.238.07:36:32.32#ibcon#*after write, iclass 17, count 0 2006.238.07:36:32.32#ibcon#*before return 0, iclass 17, count 0 2006.238.07:36:32.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:36:32.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:36:32.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:36:32.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:36:32.32$vc4f8/vb=6,4 2006.238.07:36:32.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.238.07:36:32.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.238.07:36:32.32#ibcon#ireg 11 cls_cnt 2 2006.238.07:36:32.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:36:32.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:36:32.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:36:32.38#ibcon#enter wrdev, iclass 19, count 2 2006.238.07:36:32.38#ibcon#first serial, iclass 19, count 2 2006.238.07:36:32.38#ibcon#enter sib2, iclass 19, count 2 2006.238.07:36:32.38#ibcon#flushed, iclass 19, count 2 2006.238.07:36:32.38#ibcon#about to write, iclass 19, count 2 2006.238.07:36:32.38#ibcon#wrote, iclass 19, count 2 2006.238.07:36:32.38#ibcon#about to read 3, iclass 19, count 2 2006.238.07:36:32.40#ibcon#read 3, iclass 19, count 2 2006.238.07:36:32.40#ibcon#about to read 4, iclass 19, count 2 2006.238.07:36:32.40#ibcon#read 4, iclass 19, count 2 2006.238.07:36:32.40#ibcon#about to read 5, iclass 19, count 2 2006.238.07:36:32.40#ibcon#read 5, iclass 19, count 2 2006.238.07:36:32.40#ibcon#about to read 6, iclass 19, count 2 2006.238.07:36:32.40#ibcon#read 6, iclass 19, count 2 2006.238.07:36:32.40#ibcon#end of sib2, iclass 19, count 2 2006.238.07:36:32.40#ibcon#*mode == 0, iclass 19, count 2 2006.238.07:36:32.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.238.07:36:32.40#ibcon#[27=AT06-04\r\n] 2006.238.07:36:32.40#ibcon#*before write, iclass 19, count 2 2006.238.07:36:32.40#ibcon#enter sib2, iclass 19, count 2 2006.238.07:36:32.40#ibcon#flushed, iclass 19, count 2 2006.238.07:36:32.40#ibcon#about to write, iclass 19, count 2 2006.238.07:36:32.40#ibcon#wrote, iclass 19, count 2 2006.238.07:36:32.40#ibcon#about to read 3, iclass 19, count 2 2006.238.07:36:32.43#ibcon#read 3, iclass 19, count 2 2006.238.07:36:32.43#ibcon#about to read 4, iclass 19, count 2 2006.238.07:36:32.43#ibcon#read 4, iclass 19, count 2 2006.238.07:36:32.43#ibcon#about to read 5, iclass 19, count 2 2006.238.07:36:32.43#ibcon#read 5, iclass 19, count 2 2006.238.07:36:32.43#ibcon#about to read 6, iclass 19, count 2 2006.238.07:36:32.43#ibcon#read 6, iclass 19, count 2 2006.238.07:36:32.43#ibcon#end of sib2, iclass 19, count 2 2006.238.07:36:32.43#ibcon#*after write, iclass 19, count 2 2006.238.07:36:32.43#ibcon#*before return 0, iclass 19, count 2 2006.238.07:36:32.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:36:32.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:36:32.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.238.07:36:32.43#ibcon#ireg 7 cls_cnt 0 2006.238.07:36:32.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:36:32.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:36:32.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:36:32.55#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:36:32.55#ibcon#first serial, iclass 19, count 0 2006.238.07:36:32.55#ibcon#enter sib2, iclass 19, count 0 2006.238.07:36:32.55#ibcon#flushed, iclass 19, count 0 2006.238.07:36:32.55#ibcon#about to write, iclass 19, count 0 2006.238.07:36:32.55#ibcon#wrote, iclass 19, count 0 2006.238.07:36:32.55#ibcon#about to read 3, iclass 19, count 0 2006.238.07:36:32.57#ibcon#read 3, iclass 19, count 0 2006.238.07:36:32.57#ibcon#about to read 4, iclass 19, count 0 2006.238.07:36:32.57#ibcon#read 4, iclass 19, count 0 2006.238.07:36:32.57#ibcon#about to read 5, iclass 19, count 0 2006.238.07:36:32.57#ibcon#read 5, iclass 19, count 0 2006.238.07:36:32.57#ibcon#about to read 6, iclass 19, count 0 2006.238.07:36:32.57#ibcon#read 6, iclass 19, count 0 2006.238.07:36:32.57#ibcon#end of sib2, iclass 19, count 0 2006.238.07:36:32.57#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:36:32.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:36:32.57#ibcon#[27=USB\r\n] 2006.238.07:36:32.57#ibcon#*before write, iclass 19, count 0 2006.238.07:36:32.57#ibcon#enter sib2, iclass 19, count 0 2006.238.07:36:32.57#ibcon#flushed, iclass 19, count 0 2006.238.07:36:32.57#ibcon#about to write, iclass 19, count 0 2006.238.07:36:32.57#ibcon#wrote, iclass 19, count 0 2006.238.07:36:32.57#ibcon#about to read 3, iclass 19, count 0 2006.238.07:36:32.60#ibcon#read 3, iclass 19, count 0 2006.238.07:36:32.60#ibcon#about to read 4, iclass 19, count 0 2006.238.07:36:32.60#ibcon#read 4, iclass 19, count 0 2006.238.07:36:32.60#ibcon#about to read 5, iclass 19, count 0 2006.238.07:36:32.60#ibcon#read 5, iclass 19, count 0 2006.238.07:36:32.60#ibcon#about to read 6, iclass 19, count 0 2006.238.07:36:32.60#ibcon#read 6, iclass 19, count 0 2006.238.07:36:32.60#ibcon#end of sib2, iclass 19, count 0 2006.238.07:36:32.60#ibcon#*after write, iclass 19, count 0 2006.238.07:36:32.60#ibcon#*before return 0, iclass 19, count 0 2006.238.07:36:32.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:36:32.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:36:32.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:36:32.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:36:32.60$vc4f8/vabw=wide 2006.238.07:36:32.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.07:36:32.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.07:36:32.60#ibcon#ireg 8 cls_cnt 0 2006.238.07:36:32.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:36:32.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:36:32.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:36:32.60#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:36:32.60#ibcon#first serial, iclass 21, count 0 2006.238.07:36:32.60#ibcon#enter sib2, iclass 21, count 0 2006.238.07:36:32.60#ibcon#flushed, iclass 21, count 0 2006.238.07:36:32.60#ibcon#about to write, iclass 21, count 0 2006.238.07:36:32.60#ibcon#wrote, iclass 21, count 0 2006.238.07:36:32.60#ibcon#about to read 3, iclass 21, count 0 2006.238.07:36:32.62#ibcon#read 3, iclass 21, count 0 2006.238.07:36:32.62#ibcon#about to read 4, iclass 21, count 0 2006.238.07:36:32.62#ibcon#read 4, iclass 21, count 0 2006.238.07:36:32.62#ibcon#about to read 5, iclass 21, count 0 2006.238.07:36:32.62#ibcon#read 5, iclass 21, count 0 2006.238.07:36:32.62#ibcon#about to read 6, iclass 21, count 0 2006.238.07:36:32.62#ibcon#read 6, iclass 21, count 0 2006.238.07:36:32.62#ibcon#end of sib2, iclass 21, count 0 2006.238.07:36:32.62#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:36:32.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:36:32.62#ibcon#[25=BW32\r\n] 2006.238.07:36:32.62#ibcon#*before write, iclass 21, count 0 2006.238.07:36:32.62#ibcon#enter sib2, iclass 21, count 0 2006.238.07:36:32.62#ibcon#flushed, iclass 21, count 0 2006.238.07:36:32.62#ibcon#about to write, iclass 21, count 0 2006.238.07:36:32.62#ibcon#wrote, iclass 21, count 0 2006.238.07:36:32.62#ibcon#about to read 3, iclass 21, count 0 2006.238.07:36:32.65#ibcon#read 3, iclass 21, count 0 2006.238.07:36:32.65#ibcon#about to read 4, iclass 21, count 0 2006.238.07:36:32.65#ibcon#read 4, iclass 21, count 0 2006.238.07:36:32.65#ibcon#about to read 5, iclass 21, count 0 2006.238.07:36:32.65#ibcon#read 5, iclass 21, count 0 2006.238.07:36:32.65#ibcon#about to read 6, iclass 21, count 0 2006.238.07:36:32.65#ibcon#read 6, iclass 21, count 0 2006.238.07:36:32.65#ibcon#end of sib2, iclass 21, count 0 2006.238.07:36:32.65#ibcon#*after write, iclass 21, count 0 2006.238.07:36:32.65#ibcon#*before return 0, iclass 21, count 0 2006.238.07:36:32.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:36:32.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:36:32.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:36:32.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:36:32.65$vc4f8/vbbw=wide 2006.238.07:36:32.65#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:36:32.65#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:36:32.65#ibcon#ireg 8 cls_cnt 0 2006.238.07:36:32.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:36:32.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:36:32.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:36:32.72#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:36:32.72#ibcon#first serial, iclass 23, count 0 2006.238.07:36:32.72#ibcon#enter sib2, iclass 23, count 0 2006.238.07:36:32.72#ibcon#flushed, iclass 23, count 0 2006.238.07:36:32.72#ibcon#about to write, iclass 23, count 0 2006.238.07:36:32.72#ibcon#wrote, iclass 23, count 0 2006.238.07:36:32.72#ibcon#about to read 3, iclass 23, count 0 2006.238.07:36:32.74#ibcon#read 3, iclass 23, count 0 2006.238.07:36:32.74#ibcon#about to read 4, iclass 23, count 0 2006.238.07:36:32.74#ibcon#read 4, iclass 23, count 0 2006.238.07:36:32.74#ibcon#about to read 5, iclass 23, count 0 2006.238.07:36:32.74#ibcon#read 5, iclass 23, count 0 2006.238.07:36:32.74#ibcon#about to read 6, iclass 23, count 0 2006.238.07:36:32.74#ibcon#read 6, iclass 23, count 0 2006.238.07:36:32.74#ibcon#end of sib2, iclass 23, count 0 2006.238.07:36:32.74#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:36:32.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:36:32.74#ibcon#[27=BW32\r\n] 2006.238.07:36:32.74#ibcon#*before write, iclass 23, count 0 2006.238.07:36:32.74#ibcon#enter sib2, iclass 23, count 0 2006.238.07:36:32.74#ibcon#flushed, iclass 23, count 0 2006.238.07:36:32.74#ibcon#about to write, iclass 23, count 0 2006.238.07:36:32.74#ibcon#wrote, iclass 23, count 0 2006.238.07:36:32.74#ibcon#about to read 3, iclass 23, count 0 2006.238.07:36:32.77#ibcon#read 3, iclass 23, count 0 2006.238.07:36:32.77#ibcon#about to read 4, iclass 23, count 0 2006.238.07:36:32.77#ibcon#read 4, iclass 23, count 0 2006.238.07:36:32.77#ibcon#about to read 5, iclass 23, count 0 2006.238.07:36:32.77#ibcon#read 5, iclass 23, count 0 2006.238.07:36:32.77#ibcon#about to read 6, iclass 23, count 0 2006.238.07:36:32.77#ibcon#read 6, iclass 23, count 0 2006.238.07:36:32.77#ibcon#end of sib2, iclass 23, count 0 2006.238.07:36:32.77#ibcon#*after write, iclass 23, count 0 2006.238.07:36:32.77#ibcon#*before return 0, iclass 23, count 0 2006.238.07:36:32.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:36:32.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:36:32.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:36:32.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:36:32.77$4f8m12a/ifd4f 2006.238.07:36:32.77$ifd4f/lo= 2006.238.07:36:32.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:36:32.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:36:32.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:36:32.77$ifd4f/patch= 2006.238.07:36:32.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:36:32.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:36:32.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:36:32.77$4f8m12a/"form=m,16.000,1:2 2006.238.07:36:32.77$4f8m12a/"tpicd 2006.238.07:36:32.77$4f8m12a/echo=off 2006.238.07:36:32.77$4f8m12a/xlog=off 2006.238.07:36:32.77:!2006.238.07:37:00 2006.238.07:36:45.14#trakl#Source acquired 2006.238.07:36:45.14#flagr#flagr/antenna,acquired 2006.238.07:37:00.00:preob 2006.238.07:37:01.14/onsource/TRACKING 2006.238.07:37:01.14:!2006.238.07:37:10 2006.238.07:37:10.00:data_valid=on 2006.238.07:37:10.00:midob 2006.238.07:37:10.14/onsource/TRACKING 2006.238.07:37:10.14/wx/25.34,1012.2,88 2006.238.07:37:10.30/cable/+6.4191E-03 2006.238.07:37:11.39/va/01,08,usb,yes,31,32 2006.238.07:37:11.39/va/02,07,usb,yes,31,32 2006.238.07:37:11.39/va/03,07,usb,yes,29,29 2006.238.07:37:11.39/va/04,07,usb,yes,32,35 2006.238.07:37:11.39/va/05,08,usb,yes,30,31 2006.238.07:37:11.39/va/06,07,usb,yes,32,32 2006.238.07:37:11.39/va/07,07,usb,yes,32,32 2006.238.07:37:11.39/va/08,07,usb,yes,35,34 2006.238.07:37:11.62/valo/01,532.99,yes,locked 2006.238.07:37:11.62/valo/02,572.99,yes,locked 2006.238.07:37:11.62/valo/03,672.99,yes,locked 2006.238.07:37:11.62/valo/04,832.99,yes,locked 2006.238.07:37:11.62/valo/05,652.99,yes,locked 2006.238.07:37:11.62/valo/06,772.99,yes,locked 2006.238.07:37:11.62/valo/07,832.99,yes,locked 2006.238.07:37:11.62/valo/08,852.99,yes,locked 2006.238.07:37:12.71/vb/01,04,usb,yes,30,29 2006.238.07:37:12.71/vb/02,04,usb,yes,32,33 2006.238.07:37:12.71/vb/03,04,usb,yes,28,32 2006.238.07:37:12.71/vb/04,04,usb,yes,29,29 2006.238.07:37:12.71/vb/05,04,usb,yes,28,32 2006.238.07:37:12.71/vb/06,04,usb,yes,28,31 2006.238.07:37:12.71/vb/07,04,usb,yes,31,31 2006.238.07:37:12.71/vb/08,04,usb,yes,28,32 2006.238.07:37:12.95/vblo/01,632.99,yes,locked 2006.238.07:37:12.95/vblo/02,640.99,yes,locked 2006.238.07:37:12.95/vblo/03,656.99,yes,locked 2006.238.07:37:12.95/vblo/04,712.99,yes,locked 2006.238.07:37:12.95/vblo/05,744.99,yes,locked 2006.238.07:37:12.95/vblo/06,752.99,yes,locked 2006.238.07:37:12.95/vblo/07,734.99,yes,locked 2006.238.07:37:12.95/vblo/08,744.99,yes,locked 2006.238.07:37:13.10/vabw/8 2006.238.07:37:13.25/vbbw/8 2006.238.07:37:13.36/xfe/off,on,13.2 2006.238.07:37:13.74/ifatt/23,28,28,28 2006.238.07:37:14.08/fmout-gps/S +4.37E-07 2006.238.07:37:14.12:!2006.238.07:38:10 2006.238.07:38:10.00:data_valid=off 2006.238.07:38:10.00:postob 2006.238.07:38:10.14/cable/+6.4185E-03 2006.238.07:38:10.14/wx/25.33,1012.2,87 2006.238.07:38:11.08/fmout-gps/S +4.38E-07 2006.238.07:38:11.08:scan_name=238-0739,k06238,60 2006.238.07:38:11.09:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.238.07:38:11.15#flagr#flagr/antenna,new-source 2006.238.07:38:12.14:checkk5 2006.238.07:38:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:38:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:38:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:38:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:38:14.02/chk_obsdata//k5ts1/T2380737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:38:14.39/chk_obsdata//k5ts2/T2380737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:38:14.77/chk_obsdata//k5ts3/T2380737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:38:15.14/chk_obsdata//k5ts4/T2380737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:38:15.83/k5log//k5ts1_log_newline 2006.238.07:38:16.54/k5log//k5ts2_log_newline 2006.238.07:38:17.24/k5log//k5ts3_log_newline 2006.238.07:38:17.93/k5log//k5ts4_log_newline 2006.238.07:38:17.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:38:17.95:4f8m12a=1 2006.238.07:38:17.95$4f8m12a/echo=on 2006.238.07:38:17.95$4f8m12a/pcalon 2006.238.07:38:17.95$pcalon/"no phase cal control is implemented here 2006.238.07:38:17.95$4f8m12a/"tpicd=stop 2006.238.07:38:17.95$4f8m12a/vc4f8 2006.238.07:38:17.95$vc4f8/valo=1,532.99 2006.238.07:38:17.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.07:38:17.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.07:38:17.95#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:17.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:38:17.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:38:17.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:38:17.95#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:38:17.95#ibcon#first serial, iclass 30, count 0 2006.238.07:38:17.95#ibcon#enter sib2, iclass 30, count 0 2006.238.07:38:17.95#ibcon#flushed, iclass 30, count 0 2006.238.07:38:17.95#ibcon#about to write, iclass 30, count 0 2006.238.07:38:17.95#ibcon#wrote, iclass 30, count 0 2006.238.07:38:17.95#ibcon#about to read 3, iclass 30, count 0 2006.238.07:38:18.00#ibcon#read 3, iclass 30, count 0 2006.238.07:38:18.00#ibcon#about to read 4, iclass 30, count 0 2006.238.07:38:18.00#ibcon#read 4, iclass 30, count 0 2006.238.07:38:18.00#ibcon#about to read 5, iclass 30, count 0 2006.238.07:38:18.00#ibcon#read 5, iclass 30, count 0 2006.238.07:38:18.00#ibcon#about to read 6, iclass 30, count 0 2006.238.07:38:18.00#ibcon#read 6, iclass 30, count 0 2006.238.07:38:18.00#ibcon#end of sib2, iclass 30, count 0 2006.238.07:38:18.00#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:38:18.00#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:38:18.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:38:18.00#ibcon#*before write, iclass 30, count 0 2006.238.07:38:18.00#ibcon#enter sib2, iclass 30, count 0 2006.238.07:38:18.00#ibcon#flushed, iclass 30, count 0 2006.238.07:38:18.00#ibcon#about to write, iclass 30, count 0 2006.238.07:38:18.00#ibcon#wrote, iclass 30, count 0 2006.238.07:38:18.00#ibcon#about to read 3, iclass 30, count 0 2006.238.07:38:18.05#ibcon#read 3, iclass 30, count 0 2006.238.07:38:18.05#ibcon#about to read 4, iclass 30, count 0 2006.238.07:38:18.05#ibcon#read 4, iclass 30, count 0 2006.238.07:38:18.05#ibcon#about to read 5, iclass 30, count 0 2006.238.07:38:18.05#ibcon#read 5, iclass 30, count 0 2006.238.07:38:18.05#ibcon#about to read 6, iclass 30, count 0 2006.238.07:38:18.05#ibcon#read 6, iclass 30, count 0 2006.238.07:38:18.05#ibcon#end of sib2, iclass 30, count 0 2006.238.07:38:18.05#ibcon#*after write, iclass 30, count 0 2006.238.07:38:18.05#ibcon#*before return 0, iclass 30, count 0 2006.238.07:38:18.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:38:18.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:38:18.05#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:38:18.05#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:38:18.05$vc4f8/va=1,8 2006.238.07:38:18.05#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.238.07:38:18.05#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.238.07:38:18.05#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:18.05#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:38:18.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:38:18.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:38:18.05#ibcon#enter wrdev, iclass 32, count 2 2006.238.07:38:18.05#ibcon#first serial, iclass 32, count 2 2006.238.07:38:18.05#ibcon#enter sib2, iclass 32, count 2 2006.238.07:38:18.05#ibcon#flushed, iclass 32, count 2 2006.238.07:38:18.05#ibcon#about to write, iclass 32, count 2 2006.238.07:38:18.05#ibcon#wrote, iclass 32, count 2 2006.238.07:38:18.05#ibcon#about to read 3, iclass 32, count 2 2006.238.07:38:18.07#ibcon#read 3, iclass 32, count 2 2006.238.07:38:18.07#ibcon#about to read 4, iclass 32, count 2 2006.238.07:38:18.07#ibcon#read 4, iclass 32, count 2 2006.238.07:38:18.07#ibcon#about to read 5, iclass 32, count 2 2006.238.07:38:18.07#ibcon#read 5, iclass 32, count 2 2006.238.07:38:18.07#ibcon#about to read 6, iclass 32, count 2 2006.238.07:38:18.07#ibcon#read 6, iclass 32, count 2 2006.238.07:38:18.07#ibcon#end of sib2, iclass 32, count 2 2006.238.07:38:18.07#ibcon#*mode == 0, iclass 32, count 2 2006.238.07:38:18.07#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.238.07:38:18.07#ibcon#[25=AT01-08\r\n] 2006.238.07:38:18.07#ibcon#*before write, iclass 32, count 2 2006.238.07:38:18.07#ibcon#enter sib2, iclass 32, count 2 2006.238.07:38:18.07#ibcon#flushed, iclass 32, count 2 2006.238.07:38:18.07#ibcon#about to write, iclass 32, count 2 2006.238.07:38:18.07#ibcon#wrote, iclass 32, count 2 2006.238.07:38:18.07#ibcon#about to read 3, iclass 32, count 2 2006.238.07:38:18.10#ibcon#read 3, iclass 32, count 2 2006.238.07:38:18.10#ibcon#about to read 4, iclass 32, count 2 2006.238.07:38:18.10#ibcon#read 4, iclass 32, count 2 2006.238.07:38:18.10#ibcon#about to read 5, iclass 32, count 2 2006.238.07:38:18.10#ibcon#read 5, iclass 32, count 2 2006.238.07:38:18.10#ibcon#about to read 6, iclass 32, count 2 2006.238.07:38:18.10#ibcon#read 6, iclass 32, count 2 2006.238.07:38:18.10#ibcon#end of sib2, iclass 32, count 2 2006.238.07:38:18.10#ibcon#*after write, iclass 32, count 2 2006.238.07:38:18.10#ibcon#*before return 0, iclass 32, count 2 2006.238.07:38:18.10#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:38:18.10#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:38:18.10#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.238.07:38:18.10#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:18.10#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:38:18.22#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:38:18.22#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:38:18.22#ibcon#enter wrdev, iclass 32, count 0 2006.238.07:38:18.22#ibcon#first serial, iclass 32, count 0 2006.238.07:38:18.22#ibcon#enter sib2, iclass 32, count 0 2006.238.07:38:18.22#ibcon#flushed, iclass 32, count 0 2006.238.07:38:18.22#ibcon#about to write, iclass 32, count 0 2006.238.07:38:18.22#ibcon#wrote, iclass 32, count 0 2006.238.07:38:18.22#ibcon#about to read 3, iclass 32, count 0 2006.238.07:38:18.24#ibcon#read 3, iclass 32, count 0 2006.238.07:38:18.24#ibcon#about to read 4, iclass 32, count 0 2006.238.07:38:18.24#ibcon#read 4, iclass 32, count 0 2006.238.07:38:18.24#ibcon#about to read 5, iclass 32, count 0 2006.238.07:38:18.24#ibcon#read 5, iclass 32, count 0 2006.238.07:38:18.24#ibcon#about to read 6, iclass 32, count 0 2006.238.07:38:18.24#ibcon#read 6, iclass 32, count 0 2006.238.07:38:18.24#ibcon#end of sib2, iclass 32, count 0 2006.238.07:38:18.24#ibcon#*mode == 0, iclass 32, count 0 2006.238.07:38:18.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.07:38:18.24#ibcon#[25=USB\r\n] 2006.238.07:38:18.24#ibcon#*before write, iclass 32, count 0 2006.238.07:38:18.24#ibcon#enter sib2, iclass 32, count 0 2006.238.07:38:18.24#ibcon#flushed, iclass 32, count 0 2006.238.07:38:18.24#ibcon#about to write, iclass 32, count 0 2006.238.07:38:18.24#ibcon#wrote, iclass 32, count 0 2006.238.07:38:18.24#ibcon#about to read 3, iclass 32, count 0 2006.238.07:38:18.27#ibcon#read 3, iclass 32, count 0 2006.238.07:38:18.27#ibcon#about to read 4, iclass 32, count 0 2006.238.07:38:18.27#ibcon#read 4, iclass 32, count 0 2006.238.07:38:18.27#ibcon#about to read 5, iclass 32, count 0 2006.238.07:38:18.27#ibcon#read 5, iclass 32, count 0 2006.238.07:38:18.27#ibcon#about to read 6, iclass 32, count 0 2006.238.07:38:18.27#ibcon#read 6, iclass 32, count 0 2006.238.07:38:18.27#ibcon#end of sib2, iclass 32, count 0 2006.238.07:38:18.27#ibcon#*after write, iclass 32, count 0 2006.238.07:38:18.27#ibcon#*before return 0, iclass 32, count 0 2006.238.07:38:18.27#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:38:18.27#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:38:18.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.07:38:18.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.07:38:18.27$vc4f8/valo=2,572.99 2006.238.07:38:18.27#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.238.07:38:18.27#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.238.07:38:18.27#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:18.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:38:18.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:38:18.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:38:18.27#ibcon#enter wrdev, iclass 34, count 0 2006.238.07:38:18.27#ibcon#first serial, iclass 34, count 0 2006.238.07:38:18.27#ibcon#enter sib2, iclass 34, count 0 2006.238.07:38:18.27#ibcon#flushed, iclass 34, count 0 2006.238.07:38:18.27#ibcon#about to write, iclass 34, count 0 2006.238.07:38:18.27#ibcon#wrote, iclass 34, count 0 2006.238.07:38:18.27#ibcon#about to read 3, iclass 34, count 0 2006.238.07:38:18.29#ibcon#read 3, iclass 34, count 0 2006.238.07:38:18.29#ibcon#about to read 4, iclass 34, count 0 2006.238.07:38:18.29#ibcon#read 4, iclass 34, count 0 2006.238.07:38:18.29#ibcon#about to read 5, iclass 34, count 0 2006.238.07:38:18.29#ibcon#read 5, iclass 34, count 0 2006.238.07:38:18.29#ibcon#about to read 6, iclass 34, count 0 2006.238.07:38:18.29#ibcon#read 6, iclass 34, count 0 2006.238.07:38:18.29#ibcon#end of sib2, iclass 34, count 0 2006.238.07:38:18.29#ibcon#*mode == 0, iclass 34, count 0 2006.238.07:38:18.29#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.07:38:18.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:38:18.29#ibcon#*before write, iclass 34, count 0 2006.238.07:38:18.29#ibcon#enter sib2, iclass 34, count 0 2006.238.07:38:18.29#ibcon#flushed, iclass 34, count 0 2006.238.07:38:18.29#ibcon#about to write, iclass 34, count 0 2006.238.07:38:18.29#ibcon#wrote, iclass 34, count 0 2006.238.07:38:18.29#ibcon#about to read 3, iclass 34, count 0 2006.238.07:38:18.33#ibcon#read 3, iclass 34, count 0 2006.238.07:38:18.33#ibcon#about to read 4, iclass 34, count 0 2006.238.07:38:18.33#ibcon#read 4, iclass 34, count 0 2006.238.07:38:18.33#ibcon#about to read 5, iclass 34, count 0 2006.238.07:38:18.33#ibcon#read 5, iclass 34, count 0 2006.238.07:38:18.33#ibcon#about to read 6, iclass 34, count 0 2006.238.07:38:18.33#ibcon#read 6, iclass 34, count 0 2006.238.07:38:18.33#ibcon#end of sib2, iclass 34, count 0 2006.238.07:38:18.33#ibcon#*after write, iclass 34, count 0 2006.238.07:38:18.33#ibcon#*before return 0, iclass 34, count 0 2006.238.07:38:18.33#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:38:18.33#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:38:18.33#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.07:38:18.33#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.07:38:18.33$vc4f8/va=2,7 2006.238.07:38:18.33#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.238.07:38:18.33#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.238.07:38:18.33#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:18.33#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:38:18.39#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:38:18.39#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:38:18.39#ibcon#enter wrdev, iclass 36, count 2 2006.238.07:38:18.39#ibcon#first serial, iclass 36, count 2 2006.238.07:38:18.39#ibcon#enter sib2, iclass 36, count 2 2006.238.07:38:18.39#ibcon#flushed, iclass 36, count 2 2006.238.07:38:18.39#ibcon#about to write, iclass 36, count 2 2006.238.07:38:18.39#ibcon#wrote, iclass 36, count 2 2006.238.07:38:18.39#ibcon#about to read 3, iclass 36, count 2 2006.238.07:38:18.41#ibcon#read 3, iclass 36, count 2 2006.238.07:38:18.41#ibcon#about to read 4, iclass 36, count 2 2006.238.07:38:18.41#ibcon#read 4, iclass 36, count 2 2006.238.07:38:18.41#ibcon#about to read 5, iclass 36, count 2 2006.238.07:38:18.41#ibcon#read 5, iclass 36, count 2 2006.238.07:38:18.41#ibcon#about to read 6, iclass 36, count 2 2006.238.07:38:18.41#ibcon#read 6, iclass 36, count 2 2006.238.07:38:18.41#ibcon#end of sib2, iclass 36, count 2 2006.238.07:38:18.41#ibcon#*mode == 0, iclass 36, count 2 2006.238.07:38:18.41#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.238.07:38:18.41#ibcon#[25=AT02-07\r\n] 2006.238.07:38:18.41#ibcon#*before write, iclass 36, count 2 2006.238.07:38:18.41#ibcon#enter sib2, iclass 36, count 2 2006.238.07:38:18.41#ibcon#flushed, iclass 36, count 2 2006.238.07:38:18.41#ibcon#about to write, iclass 36, count 2 2006.238.07:38:18.41#ibcon#wrote, iclass 36, count 2 2006.238.07:38:18.41#ibcon#about to read 3, iclass 36, count 2 2006.238.07:38:18.44#ibcon#read 3, iclass 36, count 2 2006.238.07:38:18.44#ibcon#about to read 4, iclass 36, count 2 2006.238.07:38:18.44#ibcon#read 4, iclass 36, count 2 2006.238.07:38:18.44#ibcon#about to read 5, iclass 36, count 2 2006.238.07:38:18.44#ibcon#read 5, iclass 36, count 2 2006.238.07:38:18.44#ibcon#about to read 6, iclass 36, count 2 2006.238.07:38:18.44#ibcon#read 6, iclass 36, count 2 2006.238.07:38:18.44#ibcon#end of sib2, iclass 36, count 2 2006.238.07:38:18.44#ibcon#*after write, iclass 36, count 2 2006.238.07:38:18.44#ibcon#*before return 0, iclass 36, count 2 2006.238.07:38:18.44#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:38:18.44#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:38:18.44#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.238.07:38:18.44#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:18.44#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:38:18.56#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:38:18.56#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:38:18.56#ibcon#enter wrdev, iclass 36, count 0 2006.238.07:38:18.56#ibcon#first serial, iclass 36, count 0 2006.238.07:38:18.56#ibcon#enter sib2, iclass 36, count 0 2006.238.07:38:18.56#ibcon#flushed, iclass 36, count 0 2006.238.07:38:18.56#ibcon#about to write, iclass 36, count 0 2006.238.07:38:18.56#ibcon#wrote, iclass 36, count 0 2006.238.07:38:18.56#ibcon#about to read 3, iclass 36, count 0 2006.238.07:38:18.58#ibcon#read 3, iclass 36, count 0 2006.238.07:38:18.58#ibcon#about to read 4, iclass 36, count 0 2006.238.07:38:18.58#ibcon#read 4, iclass 36, count 0 2006.238.07:38:18.58#ibcon#about to read 5, iclass 36, count 0 2006.238.07:38:18.58#ibcon#read 5, iclass 36, count 0 2006.238.07:38:18.58#ibcon#about to read 6, iclass 36, count 0 2006.238.07:38:18.58#ibcon#read 6, iclass 36, count 0 2006.238.07:38:18.58#ibcon#end of sib2, iclass 36, count 0 2006.238.07:38:18.58#ibcon#*mode == 0, iclass 36, count 0 2006.238.07:38:18.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.07:38:18.58#ibcon#[25=USB\r\n] 2006.238.07:38:18.58#ibcon#*before write, iclass 36, count 0 2006.238.07:38:18.58#ibcon#enter sib2, iclass 36, count 0 2006.238.07:38:18.58#ibcon#flushed, iclass 36, count 0 2006.238.07:38:18.58#ibcon#about to write, iclass 36, count 0 2006.238.07:38:18.58#ibcon#wrote, iclass 36, count 0 2006.238.07:38:18.58#ibcon#about to read 3, iclass 36, count 0 2006.238.07:38:18.61#ibcon#read 3, iclass 36, count 0 2006.238.07:38:18.61#ibcon#about to read 4, iclass 36, count 0 2006.238.07:38:18.61#ibcon#read 4, iclass 36, count 0 2006.238.07:38:18.61#ibcon#about to read 5, iclass 36, count 0 2006.238.07:38:18.61#ibcon#read 5, iclass 36, count 0 2006.238.07:38:18.61#ibcon#about to read 6, iclass 36, count 0 2006.238.07:38:18.61#ibcon#read 6, iclass 36, count 0 2006.238.07:38:18.61#ibcon#end of sib2, iclass 36, count 0 2006.238.07:38:18.61#ibcon#*after write, iclass 36, count 0 2006.238.07:38:18.61#ibcon#*before return 0, iclass 36, count 0 2006.238.07:38:18.61#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:38:18.61#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:38:18.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.07:38:18.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.07:38:18.61$vc4f8/valo=3,672.99 2006.238.07:38:18.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.238.07:38:18.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.238.07:38:18.61#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:18.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:38:18.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:38:18.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:38:18.61#ibcon#enter wrdev, iclass 38, count 0 2006.238.07:38:18.61#ibcon#first serial, iclass 38, count 0 2006.238.07:38:18.61#ibcon#enter sib2, iclass 38, count 0 2006.238.07:38:18.61#ibcon#flushed, iclass 38, count 0 2006.238.07:38:18.61#ibcon#about to write, iclass 38, count 0 2006.238.07:38:18.61#ibcon#wrote, iclass 38, count 0 2006.238.07:38:18.61#ibcon#about to read 3, iclass 38, count 0 2006.238.07:38:18.63#ibcon#read 3, iclass 38, count 0 2006.238.07:38:18.63#ibcon#about to read 4, iclass 38, count 0 2006.238.07:38:18.63#ibcon#read 4, iclass 38, count 0 2006.238.07:38:18.63#ibcon#about to read 5, iclass 38, count 0 2006.238.07:38:18.63#ibcon#read 5, iclass 38, count 0 2006.238.07:38:18.63#ibcon#about to read 6, iclass 38, count 0 2006.238.07:38:18.63#ibcon#read 6, iclass 38, count 0 2006.238.07:38:18.63#ibcon#end of sib2, iclass 38, count 0 2006.238.07:38:18.63#ibcon#*mode == 0, iclass 38, count 0 2006.238.07:38:18.63#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.07:38:18.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:38:18.63#ibcon#*before write, iclass 38, count 0 2006.238.07:38:18.63#ibcon#enter sib2, iclass 38, count 0 2006.238.07:38:18.63#ibcon#flushed, iclass 38, count 0 2006.238.07:38:18.63#ibcon#about to write, iclass 38, count 0 2006.238.07:38:18.63#ibcon#wrote, iclass 38, count 0 2006.238.07:38:18.63#ibcon#about to read 3, iclass 38, count 0 2006.238.07:38:18.67#ibcon#read 3, iclass 38, count 0 2006.238.07:38:18.67#ibcon#about to read 4, iclass 38, count 0 2006.238.07:38:18.67#ibcon#read 4, iclass 38, count 0 2006.238.07:38:18.67#ibcon#about to read 5, iclass 38, count 0 2006.238.07:38:18.67#ibcon#read 5, iclass 38, count 0 2006.238.07:38:18.67#ibcon#about to read 6, iclass 38, count 0 2006.238.07:38:18.67#ibcon#read 6, iclass 38, count 0 2006.238.07:38:18.67#ibcon#end of sib2, iclass 38, count 0 2006.238.07:38:18.67#ibcon#*after write, iclass 38, count 0 2006.238.07:38:18.67#ibcon#*before return 0, iclass 38, count 0 2006.238.07:38:18.67#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:38:18.67#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:38:18.67#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.07:38:18.67#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.07:38:18.67$vc4f8/va=3,7 2006.238.07:38:18.67#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.238.07:38:18.67#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.238.07:38:18.67#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:18.67#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:38:18.73#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:38:18.73#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:38:18.73#ibcon#enter wrdev, iclass 40, count 2 2006.238.07:38:18.73#ibcon#first serial, iclass 40, count 2 2006.238.07:38:18.73#ibcon#enter sib2, iclass 40, count 2 2006.238.07:38:18.73#ibcon#flushed, iclass 40, count 2 2006.238.07:38:18.73#ibcon#about to write, iclass 40, count 2 2006.238.07:38:18.73#ibcon#wrote, iclass 40, count 2 2006.238.07:38:18.73#ibcon#about to read 3, iclass 40, count 2 2006.238.07:38:18.75#ibcon#read 3, iclass 40, count 2 2006.238.07:38:18.75#ibcon#about to read 4, iclass 40, count 2 2006.238.07:38:18.75#ibcon#read 4, iclass 40, count 2 2006.238.07:38:18.75#ibcon#about to read 5, iclass 40, count 2 2006.238.07:38:18.75#ibcon#read 5, iclass 40, count 2 2006.238.07:38:18.75#ibcon#about to read 6, iclass 40, count 2 2006.238.07:38:18.75#ibcon#read 6, iclass 40, count 2 2006.238.07:38:18.75#ibcon#end of sib2, iclass 40, count 2 2006.238.07:38:18.75#ibcon#*mode == 0, iclass 40, count 2 2006.238.07:38:18.75#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.238.07:38:18.75#ibcon#[25=AT03-07\r\n] 2006.238.07:38:18.75#ibcon#*before write, iclass 40, count 2 2006.238.07:38:18.75#ibcon#enter sib2, iclass 40, count 2 2006.238.07:38:18.75#ibcon#flushed, iclass 40, count 2 2006.238.07:38:18.75#ibcon#about to write, iclass 40, count 2 2006.238.07:38:18.75#ibcon#wrote, iclass 40, count 2 2006.238.07:38:18.75#ibcon#about to read 3, iclass 40, count 2 2006.238.07:38:18.78#ibcon#read 3, iclass 40, count 2 2006.238.07:38:18.78#ibcon#about to read 4, iclass 40, count 2 2006.238.07:38:18.78#ibcon#read 4, iclass 40, count 2 2006.238.07:38:18.78#ibcon#about to read 5, iclass 40, count 2 2006.238.07:38:18.78#ibcon#read 5, iclass 40, count 2 2006.238.07:38:18.78#ibcon#about to read 6, iclass 40, count 2 2006.238.07:38:18.78#ibcon#read 6, iclass 40, count 2 2006.238.07:38:18.78#ibcon#end of sib2, iclass 40, count 2 2006.238.07:38:18.78#ibcon#*after write, iclass 40, count 2 2006.238.07:38:18.78#ibcon#*before return 0, iclass 40, count 2 2006.238.07:38:18.78#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:38:18.78#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:38:18.78#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.238.07:38:18.78#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:18.78#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:38:18.90#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:38:18.90#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:38:18.90#ibcon#enter wrdev, iclass 40, count 0 2006.238.07:38:18.90#ibcon#first serial, iclass 40, count 0 2006.238.07:38:18.90#ibcon#enter sib2, iclass 40, count 0 2006.238.07:38:18.90#ibcon#flushed, iclass 40, count 0 2006.238.07:38:18.90#ibcon#about to write, iclass 40, count 0 2006.238.07:38:18.90#ibcon#wrote, iclass 40, count 0 2006.238.07:38:18.90#ibcon#about to read 3, iclass 40, count 0 2006.238.07:38:18.92#ibcon#read 3, iclass 40, count 0 2006.238.07:38:18.92#ibcon#about to read 4, iclass 40, count 0 2006.238.07:38:18.92#ibcon#read 4, iclass 40, count 0 2006.238.07:38:18.92#ibcon#about to read 5, iclass 40, count 0 2006.238.07:38:18.92#ibcon#read 5, iclass 40, count 0 2006.238.07:38:18.92#ibcon#about to read 6, iclass 40, count 0 2006.238.07:38:18.92#ibcon#read 6, iclass 40, count 0 2006.238.07:38:18.92#ibcon#end of sib2, iclass 40, count 0 2006.238.07:38:18.92#ibcon#*mode == 0, iclass 40, count 0 2006.238.07:38:18.92#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.07:38:18.92#ibcon#[25=USB\r\n] 2006.238.07:38:18.92#ibcon#*before write, iclass 40, count 0 2006.238.07:38:18.92#ibcon#enter sib2, iclass 40, count 0 2006.238.07:38:18.92#ibcon#flushed, iclass 40, count 0 2006.238.07:38:18.92#ibcon#about to write, iclass 40, count 0 2006.238.07:38:18.92#ibcon#wrote, iclass 40, count 0 2006.238.07:38:18.92#ibcon#about to read 3, iclass 40, count 0 2006.238.07:38:18.95#ibcon#read 3, iclass 40, count 0 2006.238.07:38:18.95#ibcon#about to read 4, iclass 40, count 0 2006.238.07:38:18.95#ibcon#read 4, iclass 40, count 0 2006.238.07:38:18.95#ibcon#about to read 5, iclass 40, count 0 2006.238.07:38:18.95#ibcon#read 5, iclass 40, count 0 2006.238.07:38:18.95#ibcon#about to read 6, iclass 40, count 0 2006.238.07:38:18.95#ibcon#read 6, iclass 40, count 0 2006.238.07:38:18.95#ibcon#end of sib2, iclass 40, count 0 2006.238.07:38:18.95#ibcon#*after write, iclass 40, count 0 2006.238.07:38:18.95#ibcon#*before return 0, iclass 40, count 0 2006.238.07:38:18.95#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:38:18.95#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:38:18.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.07:38:18.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.07:38:18.95$vc4f8/valo=4,832.99 2006.238.07:38:18.95#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.07:38:18.95#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.07:38:18.95#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:18.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:38:18.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:38:18.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:38:18.95#ibcon#enter wrdev, iclass 4, count 0 2006.238.07:38:18.95#ibcon#first serial, iclass 4, count 0 2006.238.07:38:18.95#ibcon#enter sib2, iclass 4, count 0 2006.238.07:38:18.95#ibcon#flushed, iclass 4, count 0 2006.238.07:38:18.95#ibcon#about to write, iclass 4, count 0 2006.238.07:38:18.95#ibcon#wrote, iclass 4, count 0 2006.238.07:38:18.95#ibcon#about to read 3, iclass 4, count 0 2006.238.07:38:18.97#ibcon#read 3, iclass 4, count 0 2006.238.07:38:18.97#ibcon#about to read 4, iclass 4, count 0 2006.238.07:38:18.97#ibcon#read 4, iclass 4, count 0 2006.238.07:38:18.97#ibcon#about to read 5, iclass 4, count 0 2006.238.07:38:18.97#ibcon#read 5, iclass 4, count 0 2006.238.07:38:18.97#ibcon#about to read 6, iclass 4, count 0 2006.238.07:38:18.97#ibcon#read 6, iclass 4, count 0 2006.238.07:38:18.97#ibcon#end of sib2, iclass 4, count 0 2006.238.07:38:18.97#ibcon#*mode == 0, iclass 4, count 0 2006.238.07:38:18.97#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.07:38:18.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:38:18.97#ibcon#*before write, iclass 4, count 0 2006.238.07:38:18.97#ibcon#enter sib2, iclass 4, count 0 2006.238.07:38:18.97#ibcon#flushed, iclass 4, count 0 2006.238.07:38:18.97#ibcon#about to write, iclass 4, count 0 2006.238.07:38:18.97#ibcon#wrote, iclass 4, count 0 2006.238.07:38:18.97#ibcon#about to read 3, iclass 4, count 0 2006.238.07:38:19.01#ibcon#read 3, iclass 4, count 0 2006.238.07:38:19.01#ibcon#about to read 4, iclass 4, count 0 2006.238.07:38:19.01#ibcon#read 4, iclass 4, count 0 2006.238.07:38:19.01#ibcon#about to read 5, iclass 4, count 0 2006.238.07:38:19.01#ibcon#read 5, iclass 4, count 0 2006.238.07:38:19.01#ibcon#about to read 6, iclass 4, count 0 2006.238.07:38:19.01#ibcon#read 6, iclass 4, count 0 2006.238.07:38:19.01#ibcon#end of sib2, iclass 4, count 0 2006.238.07:38:19.01#ibcon#*after write, iclass 4, count 0 2006.238.07:38:19.01#ibcon#*before return 0, iclass 4, count 0 2006.238.07:38:19.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:38:19.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:38:19.01#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.07:38:19.01#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.07:38:19.01$vc4f8/va=4,7 2006.238.07:38:19.01#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.07:38:19.01#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.07:38:19.01#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:19.01#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:38:19.07#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:38:19.07#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:38:19.07#ibcon#enter wrdev, iclass 6, count 2 2006.238.07:38:19.07#ibcon#first serial, iclass 6, count 2 2006.238.07:38:19.07#ibcon#enter sib2, iclass 6, count 2 2006.238.07:38:19.07#ibcon#flushed, iclass 6, count 2 2006.238.07:38:19.07#ibcon#about to write, iclass 6, count 2 2006.238.07:38:19.07#ibcon#wrote, iclass 6, count 2 2006.238.07:38:19.07#ibcon#about to read 3, iclass 6, count 2 2006.238.07:38:19.09#ibcon#read 3, iclass 6, count 2 2006.238.07:38:19.09#ibcon#about to read 4, iclass 6, count 2 2006.238.07:38:19.09#ibcon#read 4, iclass 6, count 2 2006.238.07:38:19.09#ibcon#about to read 5, iclass 6, count 2 2006.238.07:38:19.09#ibcon#read 5, iclass 6, count 2 2006.238.07:38:19.09#ibcon#about to read 6, iclass 6, count 2 2006.238.07:38:19.09#ibcon#read 6, iclass 6, count 2 2006.238.07:38:19.09#ibcon#end of sib2, iclass 6, count 2 2006.238.07:38:19.09#ibcon#*mode == 0, iclass 6, count 2 2006.238.07:38:19.09#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.07:38:19.09#ibcon#[25=AT04-07\r\n] 2006.238.07:38:19.09#ibcon#*before write, iclass 6, count 2 2006.238.07:38:19.09#ibcon#enter sib2, iclass 6, count 2 2006.238.07:38:19.09#ibcon#flushed, iclass 6, count 2 2006.238.07:38:19.09#ibcon#about to write, iclass 6, count 2 2006.238.07:38:19.09#ibcon#wrote, iclass 6, count 2 2006.238.07:38:19.09#ibcon#about to read 3, iclass 6, count 2 2006.238.07:38:19.12#ibcon#read 3, iclass 6, count 2 2006.238.07:38:19.12#ibcon#about to read 4, iclass 6, count 2 2006.238.07:38:19.12#ibcon#read 4, iclass 6, count 2 2006.238.07:38:19.12#ibcon#about to read 5, iclass 6, count 2 2006.238.07:38:19.12#ibcon#read 5, iclass 6, count 2 2006.238.07:38:19.12#ibcon#about to read 6, iclass 6, count 2 2006.238.07:38:19.12#ibcon#read 6, iclass 6, count 2 2006.238.07:38:19.12#ibcon#end of sib2, iclass 6, count 2 2006.238.07:38:19.12#ibcon#*after write, iclass 6, count 2 2006.238.07:38:19.12#ibcon#*before return 0, iclass 6, count 2 2006.238.07:38:19.12#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:38:19.12#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:38:19.12#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.07:38:19.12#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:19.12#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:38:19.24#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:38:19.24#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:38:19.24#ibcon#enter wrdev, iclass 6, count 0 2006.238.07:38:19.24#ibcon#first serial, iclass 6, count 0 2006.238.07:38:19.24#ibcon#enter sib2, iclass 6, count 0 2006.238.07:38:19.24#ibcon#flushed, iclass 6, count 0 2006.238.07:38:19.24#ibcon#about to write, iclass 6, count 0 2006.238.07:38:19.24#ibcon#wrote, iclass 6, count 0 2006.238.07:38:19.24#ibcon#about to read 3, iclass 6, count 0 2006.238.07:38:19.26#ibcon#read 3, iclass 6, count 0 2006.238.07:38:19.26#ibcon#about to read 4, iclass 6, count 0 2006.238.07:38:19.26#ibcon#read 4, iclass 6, count 0 2006.238.07:38:19.26#ibcon#about to read 5, iclass 6, count 0 2006.238.07:38:19.26#ibcon#read 5, iclass 6, count 0 2006.238.07:38:19.26#ibcon#about to read 6, iclass 6, count 0 2006.238.07:38:19.26#ibcon#read 6, iclass 6, count 0 2006.238.07:38:19.26#ibcon#end of sib2, iclass 6, count 0 2006.238.07:38:19.26#ibcon#*mode == 0, iclass 6, count 0 2006.238.07:38:19.26#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.07:38:19.26#ibcon#[25=USB\r\n] 2006.238.07:38:19.26#ibcon#*before write, iclass 6, count 0 2006.238.07:38:19.26#ibcon#enter sib2, iclass 6, count 0 2006.238.07:38:19.26#ibcon#flushed, iclass 6, count 0 2006.238.07:38:19.26#ibcon#about to write, iclass 6, count 0 2006.238.07:38:19.26#ibcon#wrote, iclass 6, count 0 2006.238.07:38:19.26#ibcon#about to read 3, iclass 6, count 0 2006.238.07:38:19.29#ibcon#read 3, iclass 6, count 0 2006.238.07:38:19.29#ibcon#about to read 4, iclass 6, count 0 2006.238.07:38:19.29#ibcon#read 4, iclass 6, count 0 2006.238.07:38:19.29#ibcon#about to read 5, iclass 6, count 0 2006.238.07:38:19.29#ibcon#read 5, iclass 6, count 0 2006.238.07:38:19.29#ibcon#about to read 6, iclass 6, count 0 2006.238.07:38:19.29#ibcon#read 6, iclass 6, count 0 2006.238.07:38:19.29#ibcon#end of sib2, iclass 6, count 0 2006.238.07:38:19.29#ibcon#*after write, iclass 6, count 0 2006.238.07:38:19.29#ibcon#*before return 0, iclass 6, count 0 2006.238.07:38:19.29#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:38:19.29#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:38:19.29#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.07:38:19.29#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.07:38:19.29$vc4f8/valo=5,652.99 2006.238.07:38:19.29#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.07:38:19.29#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.07:38:19.29#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:19.29#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:38:19.29#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:38:19.29#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:38:19.29#ibcon#enter wrdev, iclass 10, count 0 2006.238.07:38:19.29#ibcon#first serial, iclass 10, count 0 2006.238.07:38:19.29#ibcon#enter sib2, iclass 10, count 0 2006.238.07:38:19.29#ibcon#flushed, iclass 10, count 0 2006.238.07:38:19.29#ibcon#about to write, iclass 10, count 0 2006.238.07:38:19.29#ibcon#wrote, iclass 10, count 0 2006.238.07:38:19.29#ibcon#about to read 3, iclass 10, count 0 2006.238.07:38:19.31#ibcon#read 3, iclass 10, count 0 2006.238.07:38:19.31#ibcon#about to read 4, iclass 10, count 0 2006.238.07:38:19.31#ibcon#read 4, iclass 10, count 0 2006.238.07:38:19.31#ibcon#about to read 5, iclass 10, count 0 2006.238.07:38:19.31#ibcon#read 5, iclass 10, count 0 2006.238.07:38:19.31#ibcon#about to read 6, iclass 10, count 0 2006.238.07:38:19.31#ibcon#read 6, iclass 10, count 0 2006.238.07:38:19.31#ibcon#end of sib2, iclass 10, count 0 2006.238.07:38:19.31#ibcon#*mode == 0, iclass 10, count 0 2006.238.07:38:19.31#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.07:38:19.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:38:19.31#ibcon#*before write, iclass 10, count 0 2006.238.07:38:19.31#ibcon#enter sib2, iclass 10, count 0 2006.238.07:38:19.31#ibcon#flushed, iclass 10, count 0 2006.238.07:38:19.31#ibcon#about to write, iclass 10, count 0 2006.238.07:38:19.31#ibcon#wrote, iclass 10, count 0 2006.238.07:38:19.31#ibcon#about to read 3, iclass 10, count 0 2006.238.07:38:19.35#ibcon#read 3, iclass 10, count 0 2006.238.07:38:19.35#ibcon#about to read 4, iclass 10, count 0 2006.238.07:38:19.35#ibcon#read 4, iclass 10, count 0 2006.238.07:38:19.35#ibcon#about to read 5, iclass 10, count 0 2006.238.07:38:19.35#ibcon#read 5, iclass 10, count 0 2006.238.07:38:19.35#ibcon#about to read 6, iclass 10, count 0 2006.238.07:38:19.35#ibcon#read 6, iclass 10, count 0 2006.238.07:38:19.35#ibcon#end of sib2, iclass 10, count 0 2006.238.07:38:19.35#ibcon#*after write, iclass 10, count 0 2006.238.07:38:19.35#ibcon#*before return 0, iclass 10, count 0 2006.238.07:38:19.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:38:19.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:38:19.35#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.07:38:19.35#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.07:38:19.35$vc4f8/va=5,8 2006.238.07:38:19.35#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.238.07:38:19.35#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.238.07:38:19.35#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:19.35#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:38:19.41#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:38:19.41#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:38:19.41#ibcon#enter wrdev, iclass 12, count 2 2006.238.07:38:19.41#ibcon#first serial, iclass 12, count 2 2006.238.07:38:19.41#ibcon#enter sib2, iclass 12, count 2 2006.238.07:38:19.41#ibcon#flushed, iclass 12, count 2 2006.238.07:38:19.41#ibcon#about to write, iclass 12, count 2 2006.238.07:38:19.41#ibcon#wrote, iclass 12, count 2 2006.238.07:38:19.41#ibcon#about to read 3, iclass 12, count 2 2006.238.07:38:19.43#ibcon#read 3, iclass 12, count 2 2006.238.07:38:19.43#ibcon#about to read 4, iclass 12, count 2 2006.238.07:38:19.43#ibcon#read 4, iclass 12, count 2 2006.238.07:38:19.43#ibcon#about to read 5, iclass 12, count 2 2006.238.07:38:19.43#ibcon#read 5, iclass 12, count 2 2006.238.07:38:19.43#ibcon#about to read 6, iclass 12, count 2 2006.238.07:38:19.43#ibcon#read 6, iclass 12, count 2 2006.238.07:38:19.43#ibcon#end of sib2, iclass 12, count 2 2006.238.07:38:19.43#ibcon#*mode == 0, iclass 12, count 2 2006.238.07:38:19.43#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.238.07:38:19.43#ibcon#[25=AT05-08\r\n] 2006.238.07:38:19.43#ibcon#*before write, iclass 12, count 2 2006.238.07:38:19.43#ibcon#enter sib2, iclass 12, count 2 2006.238.07:38:19.43#ibcon#flushed, iclass 12, count 2 2006.238.07:38:19.43#ibcon#about to write, iclass 12, count 2 2006.238.07:38:19.43#ibcon#wrote, iclass 12, count 2 2006.238.07:38:19.43#ibcon#about to read 3, iclass 12, count 2 2006.238.07:38:19.46#ibcon#read 3, iclass 12, count 2 2006.238.07:38:19.46#ibcon#about to read 4, iclass 12, count 2 2006.238.07:38:19.46#ibcon#read 4, iclass 12, count 2 2006.238.07:38:19.46#ibcon#about to read 5, iclass 12, count 2 2006.238.07:38:19.46#ibcon#read 5, iclass 12, count 2 2006.238.07:38:19.46#ibcon#about to read 6, iclass 12, count 2 2006.238.07:38:19.46#ibcon#read 6, iclass 12, count 2 2006.238.07:38:19.46#ibcon#end of sib2, iclass 12, count 2 2006.238.07:38:19.46#ibcon#*after write, iclass 12, count 2 2006.238.07:38:19.46#ibcon#*before return 0, iclass 12, count 2 2006.238.07:38:19.46#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:38:19.46#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:38:19.46#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.238.07:38:19.46#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:19.46#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:38:19.58#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:38:19.58#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:38:19.58#ibcon#enter wrdev, iclass 12, count 0 2006.238.07:38:19.58#ibcon#first serial, iclass 12, count 0 2006.238.07:38:19.58#ibcon#enter sib2, iclass 12, count 0 2006.238.07:38:19.58#ibcon#flushed, iclass 12, count 0 2006.238.07:38:19.58#ibcon#about to write, iclass 12, count 0 2006.238.07:38:19.58#ibcon#wrote, iclass 12, count 0 2006.238.07:38:19.58#ibcon#about to read 3, iclass 12, count 0 2006.238.07:38:19.60#ibcon#read 3, iclass 12, count 0 2006.238.07:38:19.60#ibcon#about to read 4, iclass 12, count 0 2006.238.07:38:19.60#ibcon#read 4, iclass 12, count 0 2006.238.07:38:19.60#ibcon#about to read 5, iclass 12, count 0 2006.238.07:38:19.60#ibcon#read 5, iclass 12, count 0 2006.238.07:38:19.60#ibcon#about to read 6, iclass 12, count 0 2006.238.07:38:19.60#ibcon#read 6, iclass 12, count 0 2006.238.07:38:19.60#ibcon#end of sib2, iclass 12, count 0 2006.238.07:38:19.60#ibcon#*mode == 0, iclass 12, count 0 2006.238.07:38:19.60#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.07:38:19.60#ibcon#[25=USB\r\n] 2006.238.07:38:19.60#ibcon#*before write, iclass 12, count 0 2006.238.07:38:19.60#ibcon#enter sib2, iclass 12, count 0 2006.238.07:38:19.60#ibcon#flushed, iclass 12, count 0 2006.238.07:38:19.60#ibcon#about to write, iclass 12, count 0 2006.238.07:38:19.60#ibcon#wrote, iclass 12, count 0 2006.238.07:38:19.60#ibcon#about to read 3, iclass 12, count 0 2006.238.07:38:19.63#ibcon#read 3, iclass 12, count 0 2006.238.07:38:19.63#ibcon#about to read 4, iclass 12, count 0 2006.238.07:38:19.63#ibcon#read 4, iclass 12, count 0 2006.238.07:38:19.63#ibcon#about to read 5, iclass 12, count 0 2006.238.07:38:19.63#ibcon#read 5, iclass 12, count 0 2006.238.07:38:19.63#ibcon#about to read 6, iclass 12, count 0 2006.238.07:38:19.63#ibcon#read 6, iclass 12, count 0 2006.238.07:38:19.63#ibcon#end of sib2, iclass 12, count 0 2006.238.07:38:19.63#ibcon#*after write, iclass 12, count 0 2006.238.07:38:19.63#ibcon#*before return 0, iclass 12, count 0 2006.238.07:38:19.63#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:38:19.63#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:38:19.63#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.07:38:19.63#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.07:38:19.63$vc4f8/valo=6,772.99 2006.238.07:38:19.63#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.07:38:19.63#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.07:38:19.63#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:19.63#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:38:19.63#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:38:19.63#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:38:19.63#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:38:19.63#ibcon#first serial, iclass 14, count 0 2006.238.07:38:19.63#ibcon#enter sib2, iclass 14, count 0 2006.238.07:38:19.63#ibcon#flushed, iclass 14, count 0 2006.238.07:38:19.63#ibcon#about to write, iclass 14, count 0 2006.238.07:38:19.63#ibcon#wrote, iclass 14, count 0 2006.238.07:38:19.63#ibcon#about to read 3, iclass 14, count 0 2006.238.07:38:19.65#ibcon#read 3, iclass 14, count 0 2006.238.07:38:19.65#ibcon#about to read 4, iclass 14, count 0 2006.238.07:38:19.65#ibcon#read 4, iclass 14, count 0 2006.238.07:38:19.65#ibcon#about to read 5, iclass 14, count 0 2006.238.07:38:19.65#ibcon#read 5, iclass 14, count 0 2006.238.07:38:19.65#ibcon#about to read 6, iclass 14, count 0 2006.238.07:38:19.65#ibcon#read 6, iclass 14, count 0 2006.238.07:38:19.65#ibcon#end of sib2, iclass 14, count 0 2006.238.07:38:19.65#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:38:19.65#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:38:19.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:38:19.65#ibcon#*before write, iclass 14, count 0 2006.238.07:38:19.65#ibcon#enter sib2, iclass 14, count 0 2006.238.07:38:19.65#ibcon#flushed, iclass 14, count 0 2006.238.07:38:19.65#ibcon#about to write, iclass 14, count 0 2006.238.07:38:19.65#ibcon#wrote, iclass 14, count 0 2006.238.07:38:19.65#ibcon#about to read 3, iclass 14, count 0 2006.238.07:38:19.69#ibcon#read 3, iclass 14, count 0 2006.238.07:38:19.69#ibcon#about to read 4, iclass 14, count 0 2006.238.07:38:19.69#ibcon#read 4, iclass 14, count 0 2006.238.07:38:19.69#ibcon#about to read 5, iclass 14, count 0 2006.238.07:38:19.69#ibcon#read 5, iclass 14, count 0 2006.238.07:38:19.69#ibcon#about to read 6, iclass 14, count 0 2006.238.07:38:19.69#ibcon#read 6, iclass 14, count 0 2006.238.07:38:19.69#ibcon#end of sib2, iclass 14, count 0 2006.238.07:38:19.69#ibcon#*after write, iclass 14, count 0 2006.238.07:38:19.69#ibcon#*before return 0, iclass 14, count 0 2006.238.07:38:19.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:38:19.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:38:19.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:38:19.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:38:19.69$vc4f8/va=6,7 2006.238.07:38:19.69#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.238.07:38:19.69#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.238.07:38:19.69#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:19.69#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:38:19.76#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:38:19.76#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:38:19.76#ibcon#enter wrdev, iclass 16, count 2 2006.238.07:38:19.76#ibcon#first serial, iclass 16, count 2 2006.238.07:38:19.76#ibcon#enter sib2, iclass 16, count 2 2006.238.07:38:19.76#ibcon#flushed, iclass 16, count 2 2006.238.07:38:19.76#ibcon#about to write, iclass 16, count 2 2006.238.07:38:19.76#ibcon#wrote, iclass 16, count 2 2006.238.07:38:19.76#ibcon#about to read 3, iclass 16, count 2 2006.238.07:38:19.77#ibcon#read 3, iclass 16, count 2 2006.238.07:38:19.77#ibcon#about to read 4, iclass 16, count 2 2006.238.07:38:19.77#ibcon#read 4, iclass 16, count 2 2006.238.07:38:19.77#ibcon#about to read 5, iclass 16, count 2 2006.238.07:38:19.77#ibcon#read 5, iclass 16, count 2 2006.238.07:38:19.77#ibcon#about to read 6, iclass 16, count 2 2006.238.07:38:19.77#ibcon#read 6, iclass 16, count 2 2006.238.07:38:19.77#ibcon#end of sib2, iclass 16, count 2 2006.238.07:38:19.77#ibcon#*mode == 0, iclass 16, count 2 2006.238.07:38:19.77#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.238.07:38:19.77#ibcon#[25=AT06-07\r\n] 2006.238.07:38:19.77#ibcon#*before write, iclass 16, count 2 2006.238.07:38:19.77#ibcon#enter sib2, iclass 16, count 2 2006.238.07:38:19.77#ibcon#flushed, iclass 16, count 2 2006.238.07:38:19.77#ibcon#about to write, iclass 16, count 2 2006.238.07:38:19.77#ibcon#wrote, iclass 16, count 2 2006.238.07:38:19.77#ibcon#about to read 3, iclass 16, count 2 2006.238.07:38:19.80#ibcon#read 3, iclass 16, count 2 2006.238.07:38:19.80#ibcon#about to read 4, iclass 16, count 2 2006.238.07:38:19.80#ibcon#read 4, iclass 16, count 2 2006.238.07:38:19.80#ibcon#about to read 5, iclass 16, count 2 2006.238.07:38:19.80#ibcon#read 5, iclass 16, count 2 2006.238.07:38:19.80#ibcon#about to read 6, iclass 16, count 2 2006.238.07:38:19.80#ibcon#read 6, iclass 16, count 2 2006.238.07:38:19.80#ibcon#end of sib2, iclass 16, count 2 2006.238.07:38:19.80#ibcon#*after write, iclass 16, count 2 2006.238.07:38:19.80#ibcon#*before return 0, iclass 16, count 2 2006.238.07:38:19.80#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:38:19.80#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:38:19.80#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.238.07:38:19.80#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:19.80#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:38:19.92#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:38:19.92#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:38:19.92#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:38:19.92#ibcon#first serial, iclass 16, count 0 2006.238.07:38:19.92#ibcon#enter sib2, iclass 16, count 0 2006.238.07:38:19.92#ibcon#flushed, iclass 16, count 0 2006.238.07:38:19.92#ibcon#about to write, iclass 16, count 0 2006.238.07:38:19.92#ibcon#wrote, iclass 16, count 0 2006.238.07:38:19.92#ibcon#about to read 3, iclass 16, count 0 2006.238.07:38:19.94#ibcon#read 3, iclass 16, count 0 2006.238.07:38:19.94#ibcon#about to read 4, iclass 16, count 0 2006.238.07:38:19.94#ibcon#read 4, iclass 16, count 0 2006.238.07:38:19.94#ibcon#about to read 5, iclass 16, count 0 2006.238.07:38:19.94#ibcon#read 5, iclass 16, count 0 2006.238.07:38:19.94#ibcon#about to read 6, iclass 16, count 0 2006.238.07:38:19.94#ibcon#read 6, iclass 16, count 0 2006.238.07:38:19.94#ibcon#end of sib2, iclass 16, count 0 2006.238.07:38:19.94#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:38:19.94#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:38:19.94#ibcon#[25=USB\r\n] 2006.238.07:38:19.94#ibcon#*before write, iclass 16, count 0 2006.238.07:38:19.94#ibcon#enter sib2, iclass 16, count 0 2006.238.07:38:19.94#ibcon#flushed, iclass 16, count 0 2006.238.07:38:19.94#ibcon#about to write, iclass 16, count 0 2006.238.07:38:19.94#ibcon#wrote, iclass 16, count 0 2006.238.07:38:19.94#ibcon#about to read 3, iclass 16, count 0 2006.238.07:38:19.97#ibcon#read 3, iclass 16, count 0 2006.238.07:38:19.97#ibcon#about to read 4, iclass 16, count 0 2006.238.07:38:19.97#ibcon#read 4, iclass 16, count 0 2006.238.07:38:19.97#ibcon#about to read 5, iclass 16, count 0 2006.238.07:38:19.97#ibcon#read 5, iclass 16, count 0 2006.238.07:38:19.97#ibcon#about to read 6, iclass 16, count 0 2006.238.07:38:19.97#ibcon#read 6, iclass 16, count 0 2006.238.07:38:19.97#ibcon#end of sib2, iclass 16, count 0 2006.238.07:38:19.97#ibcon#*after write, iclass 16, count 0 2006.238.07:38:19.97#ibcon#*before return 0, iclass 16, count 0 2006.238.07:38:19.97#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:38:19.97#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:38:19.97#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:38:19.97#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:38:19.97$vc4f8/valo=7,832.99 2006.238.07:38:19.97#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.07:38:19.97#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.07:38:19.97#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:19.97#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:38:19.97#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:38:19.97#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:38:19.97#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:38:19.97#ibcon#first serial, iclass 18, count 0 2006.238.07:38:19.97#ibcon#enter sib2, iclass 18, count 0 2006.238.07:38:19.97#ibcon#flushed, iclass 18, count 0 2006.238.07:38:19.97#ibcon#about to write, iclass 18, count 0 2006.238.07:38:19.97#ibcon#wrote, iclass 18, count 0 2006.238.07:38:19.97#ibcon#about to read 3, iclass 18, count 0 2006.238.07:38:19.99#ibcon#read 3, iclass 18, count 0 2006.238.07:38:19.99#ibcon#about to read 4, iclass 18, count 0 2006.238.07:38:19.99#ibcon#read 4, iclass 18, count 0 2006.238.07:38:19.99#ibcon#about to read 5, iclass 18, count 0 2006.238.07:38:19.99#ibcon#read 5, iclass 18, count 0 2006.238.07:38:19.99#ibcon#about to read 6, iclass 18, count 0 2006.238.07:38:19.99#ibcon#read 6, iclass 18, count 0 2006.238.07:38:19.99#ibcon#end of sib2, iclass 18, count 0 2006.238.07:38:19.99#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:38:19.99#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:38:19.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:38:19.99#ibcon#*before write, iclass 18, count 0 2006.238.07:38:19.99#ibcon#enter sib2, iclass 18, count 0 2006.238.07:38:19.99#ibcon#flushed, iclass 18, count 0 2006.238.07:38:19.99#ibcon#about to write, iclass 18, count 0 2006.238.07:38:19.99#ibcon#wrote, iclass 18, count 0 2006.238.07:38:19.99#ibcon#about to read 3, iclass 18, count 0 2006.238.07:38:20.03#ibcon#read 3, iclass 18, count 0 2006.238.07:38:20.03#ibcon#about to read 4, iclass 18, count 0 2006.238.07:38:20.03#ibcon#read 4, iclass 18, count 0 2006.238.07:38:20.03#ibcon#about to read 5, iclass 18, count 0 2006.238.07:38:20.03#ibcon#read 5, iclass 18, count 0 2006.238.07:38:20.03#ibcon#about to read 6, iclass 18, count 0 2006.238.07:38:20.03#ibcon#read 6, iclass 18, count 0 2006.238.07:38:20.03#ibcon#end of sib2, iclass 18, count 0 2006.238.07:38:20.03#ibcon#*after write, iclass 18, count 0 2006.238.07:38:20.03#ibcon#*before return 0, iclass 18, count 0 2006.238.07:38:20.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:38:20.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:38:20.03#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:38:20.03#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:38:20.03$vc4f8/va=7,7 2006.238.07:38:20.03#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.238.07:38:20.03#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.238.07:38:20.03#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:20.03#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:38:20.09#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:38:20.09#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:38:20.09#ibcon#enter wrdev, iclass 20, count 2 2006.238.07:38:20.09#ibcon#first serial, iclass 20, count 2 2006.238.07:38:20.09#ibcon#enter sib2, iclass 20, count 2 2006.238.07:38:20.09#ibcon#flushed, iclass 20, count 2 2006.238.07:38:20.09#ibcon#about to write, iclass 20, count 2 2006.238.07:38:20.09#ibcon#wrote, iclass 20, count 2 2006.238.07:38:20.09#ibcon#about to read 3, iclass 20, count 2 2006.238.07:38:20.11#ibcon#read 3, iclass 20, count 2 2006.238.07:38:20.11#ibcon#about to read 4, iclass 20, count 2 2006.238.07:38:20.11#ibcon#read 4, iclass 20, count 2 2006.238.07:38:20.11#ibcon#about to read 5, iclass 20, count 2 2006.238.07:38:20.11#ibcon#read 5, iclass 20, count 2 2006.238.07:38:20.11#ibcon#about to read 6, iclass 20, count 2 2006.238.07:38:20.11#ibcon#read 6, iclass 20, count 2 2006.238.07:38:20.11#ibcon#end of sib2, iclass 20, count 2 2006.238.07:38:20.11#ibcon#*mode == 0, iclass 20, count 2 2006.238.07:38:20.11#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.238.07:38:20.11#ibcon#[25=AT07-07\r\n] 2006.238.07:38:20.11#ibcon#*before write, iclass 20, count 2 2006.238.07:38:20.11#ibcon#enter sib2, iclass 20, count 2 2006.238.07:38:20.11#ibcon#flushed, iclass 20, count 2 2006.238.07:38:20.11#ibcon#about to write, iclass 20, count 2 2006.238.07:38:20.11#ibcon#wrote, iclass 20, count 2 2006.238.07:38:20.11#ibcon#about to read 3, iclass 20, count 2 2006.238.07:38:20.14#ibcon#read 3, iclass 20, count 2 2006.238.07:38:20.14#ibcon#about to read 4, iclass 20, count 2 2006.238.07:38:20.14#ibcon#read 4, iclass 20, count 2 2006.238.07:38:20.14#ibcon#about to read 5, iclass 20, count 2 2006.238.07:38:20.14#ibcon#read 5, iclass 20, count 2 2006.238.07:38:20.14#ibcon#about to read 6, iclass 20, count 2 2006.238.07:38:20.14#ibcon#read 6, iclass 20, count 2 2006.238.07:38:20.14#ibcon#end of sib2, iclass 20, count 2 2006.238.07:38:20.14#ibcon#*after write, iclass 20, count 2 2006.238.07:38:20.14#ibcon#*before return 0, iclass 20, count 2 2006.238.07:38:20.14#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:38:20.14#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:38:20.14#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.238.07:38:20.14#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:20.14#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:38:20.26#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:38:20.26#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:38:20.26#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:38:20.26#ibcon#first serial, iclass 20, count 0 2006.238.07:38:20.26#ibcon#enter sib2, iclass 20, count 0 2006.238.07:38:20.26#ibcon#flushed, iclass 20, count 0 2006.238.07:38:20.26#ibcon#about to write, iclass 20, count 0 2006.238.07:38:20.26#ibcon#wrote, iclass 20, count 0 2006.238.07:38:20.26#ibcon#about to read 3, iclass 20, count 0 2006.238.07:38:20.28#ibcon#read 3, iclass 20, count 0 2006.238.07:38:20.28#ibcon#about to read 4, iclass 20, count 0 2006.238.07:38:20.28#ibcon#read 4, iclass 20, count 0 2006.238.07:38:20.28#ibcon#about to read 5, iclass 20, count 0 2006.238.07:38:20.28#ibcon#read 5, iclass 20, count 0 2006.238.07:38:20.28#ibcon#about to read 6, iclass 20, count 0 2006.238.07:38:20.28#ibcon#read 6, iclass 20, count 0 2006.238.07:38:20.28#ibcon#end of sib2, iclass 20, count 0 2006.238.07:38:20.28#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:38:20.28#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:38:20.28#ibcon#[25=USB\r\n] 2006.238.07:38:20.28#ibcon#*before write, iclass 20, count 0 2006.238.07:38:20.28#ibcon#enter sib2, iclass 20, count 0 2006.238.07:38:20.28#ibcon#flushed, iclass 20, count 0 2006.238.07:38:20.28#ibcon#about to write, iclass 20, count 0 2006.238.07:38:20.28#ibcon#wrote, iclass 20, count 0 2006.238.07:38:20.28#ibcon#about to read 3, iclass 20, count 0 2006.238.07:38:20.31#ibcon#read 3, iclass 20, count 0 2006.238.07:38:20.31#ibcon#about to read 4, iclass 20, count 0 2006.238.07:38:20.31#ibcon#read 4, iclass 20, count 0 2006.238.07:38:20.31#ibcon#about to read 5, iclass 20, count 0 2006.238.07:38:20.31#ibcon#read 5, iclass 20, count 0 2006.238.07:38:20.31#ibcon#about to read 6, iclass 20, count 0 2006.238.07:38:20.31#ibcon#read 6, iclass 20, count 0 2006.238.07:38:20.31#ibcon#end of sib2, iclass 20, count 0 2006.238.07:38:20.31#ibcon#*after write, iclass 20, count 0 2006.238.07:38:20.31#ibcon#*before return 0, iclass 20, count 0 2006.238.07:38:20.31#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:38:20.31#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:38:20.31#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:38:20.31#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:38:20.31$vc4f8/valo=8,852.99 2006.238.07:38:20.31#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.07:38:20.31#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.07:38:20.31#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:20.31#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:38:20.31#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:38:20.31#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:38:20.31#ibcon#enter wrdev, iclass 22, count 0 2006.238.07:38:20.31#ibcon#first serial, iclass 22, count 0 2006.238.07:38:20.31#ibcon#enter sib2, iclass 22, count 0 2006.238.07:38:20.31#ibcon#flushed, iclass 22, count 0 2006.238.07:38:20.31#ibcon#about to write, iclass 22, count 0 2006.238.07:38:20.31#ibcon#wrote, iclass 22, count 0 2006.238.07:38:20.31#ibcon#about to read 3, iclass 22, count 0 2006.238.07:38:20.33#ibcon#read 3, iclass 22, count 0 2006.238.07:38:20.33#ibcon#about to read 4, iclass 22, count 0 2006.238.07:38:20.33#ibcon#read 4, iclass 22, count 0 2006.238.07:38:20.33#ibcon#about to read 5, iclass 22, count 0 2006.238.07:38:20.33#ibcon#read 5, iclass 22, count 0 2006.238.07:38:20.33#ibcon#about to read 6, iclass 22, count 0 2006.238.07:38:20.33#ibcon#read 6, iclass 22, count 0 2006.238.07:38:20.33#ibcon#end of sib2, iclass 22, count 0 2006.238.07:38:20.33#ibcon#*mode == 0, iclass 22, count 0 2006.238.07:38:20.33#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.07:38:20.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:38:20.33#ibcon#*before write, iclass 22, count 0 2006.238.07:38:20.33#ibcon#enter sib2, iclass 22, count 0 2006.238.07:38:20.33#ibcon#flushed, iclass 22, count 0 2006.238.07:38:20.33#ibcon#about to write, iclass 22, count 0 2006.238.07:38:20.33#ibcon#wrote, iclass 22, count 0 2006.238.07:38:20.33#ibcon#about to read 3, iclass 22, count 0 2006.238.07:38:20.37#ibcon#read 3, iclass 22, count 0 2006.238.07:38:20.37#ibcon#about to read 4, iclass 22, count 0 2006.238.07:38:20.37#ibcon#read 4, iclass 22, count 0 2006.238.07:38:20.37#ibcon#about to read 5, iclass 22, count 0 2006.238.07:38:20.37#ibcon#read 5, iclass 22, count 0 2006.238.07:38:20.37#ibcon#about to read 6, iclass 22, count 0 2006.238.07:38:20.37#ibcon#read 6, iclass 22, count 0 2006.238.07:38:20.37#ibcon#end of sib2, iclass 22, count 0 2006.238.07:38:20.37#ibcon#*after write, iclass 22, count 0 2006.238.07:38:20.37#ibcon#*before return 0, iclass 22, count 0 2006.238.07:38:20.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:38:20.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:38:20.37#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.07:38:20.37#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.07:38:20.37$vc4f8/va=8,7 2006.238.07:38:20.37#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.238.07:38:20.37#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.238.07:38:20.37#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:20.37#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:38:20.44#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:38:20.44#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:38:20.44#ibcon#enter wrdev, iclass 24, count 2 2006.238.07:38:20.44#ibcon#first serial, iclass 24, count 2 2006.238.07:38:20.44#ibcon#enter sib2, iclass 24, count 2 2006.238.07:38:20.44#ibcon#flushed, iclass 24, count 2 2006.238.07:38:20.44#ibcon#about to write, iclass 24, count 2 2006.238.07:38:20.44#ibcon#wrote, iclass 24, count 2 2006.238.07:38:20.44#ibcon#about to read 3, iclass 24, count 2 2006.238.07:38:20.45#ibcon#read 3, iclass 24, count 2 2006.238.07:38:20.45#ibcon#about to read 4, iclass 24, count 2 2006.238.07:38:20.45#ibcon#read 4, iclass 24, count 2 2006.238.07:38:20.45#ibcon#about to read 5, iclass 24, count 2 2006.238.07:38:20.45#ibcon#read 5, iclass 24, count 2 2006.238.07:38:20.45#ibcon#about to read 6, iclass 24, count 2 2006.238.07:38:20.45#ibcon#read 6, iclass 24, count 2 2006.238.07:38:20.45#ibcon#end of sib2, iclass 24, count 2 2006.238.07:38:20.45#ibcon#*mode == 0, iclass 24, count 2 2006.238.07:38:20.45#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.238.07:38:20.45#ibcon#[25=AT08-07\r\n] 2006.238.07:38:20.45#ibcon#*before write, iclass 24, count 2 2006.238.07:38:20.45#ibcon#enter sib2, iclass 24, count 2 2006.238.07:38:20.45#ibcon#flushed, iclass 24, count 2 2006.238.07:38:20.45#ibcon#about to write, iclass 24, count 2 2006.238.07:38:20.45#ibcon#wrote, iclass 24, count 2 2006.238.07:38:20.45#ibcon#about to read 3, iclass 24, count 2 2006.238.07:38:20.48#ibcon#read 3, iclass 24, count 2 2006.238.07:38:20.48#ibcon#about to read 4, iclass 24, count 2 2006.238.07:38:20.48#ibcon#read 4, iclass 24, count 2 2006.238.07:38:20.48#ibcon#about to read 5, iclass 24, count 2 2006.238.07:38:20.48#ibcon#read 5, iclass 24, count 2 2006.238.07:38:20.48#ibcon#about to read 6, iclass 24, count 2 2006.238.07:38:20.48#ibcon#read 6, iclass 24, count 2 2006.238.07:38:20.48#ibcon#end of sib2, iclass 24, count 2 2006.238.07:38:20.48#ibcon#*after write, iclass 24, count 2 2006.238.07:38:20.48#ibcon#*before return 0, iclass 24, count 2 2006.238.07:38:20.48#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:38:20.48#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:38:20.48#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.238.07:38:20.48#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:20.48#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:38:20.60#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:38:20.60#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:38:20.60#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:38:20.60#ibcon#first serial, iclass 24, count 0 2006.238.07:38:20.60#ibcon#enter sib2, iclass 24, count 0 2006.238.07:38:20.60#ibcon#flushed, iclass 24, count 0 2006.238.07:38:20.60#ibcon#about to write, iclass 24, count 0 2006.238.07:38:20.60#ibcon#wrote, iclass 24, count 0 2006.238.07:38:20.60#ibcon#about to read 3, iclass 24, count 0 2006.238.07:38:20.62#ibcon#read 3, iclass 24, count 0 2006.238.07:38:20.62#ibcon#about to read 4, iclass 24, count 0 2006.238.07:38:20.62#ibcon#read 4, iclass 24, count 0 2006.238.07:38:20.62#ibcon#about to read 5, iclass 24, count 0 2006.238.07:38:20.62#ibcon#read 5, iclass 24, count 0 2006.238.07:38:20.62#ibcon#about to read 6, iclass 24, count 0 2006.238.07:38:20.62#ibcon#read 6, iclass 24, count 0 2006.238.07:38:20.62#ibcon#end of sib2, iclass 24, count 0 2006.238.07:38:20.62#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:38:20.62#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:38:20.62#ibcon#[25=USB\r\n] 2006.238.07:38:20.62#ibcon#*before write, iclass 24, count 0 2006.238.07:38:20.62#ibcon#enter sib2, iclass 24, count 0 2006.238.07:38:20.62#ibcon#flushed, iclass 24, count 0 2006.238.07:38:20.62#ibcon#about to write, iclass 24, count 0 2006.238.07:38:20.62#ibcon#wrote, iclass 24, count 0 2006.238.07:38:20.62#ibcon#about to read 3, iclass 24, count 0 2006.238.07:38:20.65#ibcon#read 3, iclass 24, count 0 2006.238.07:38:20.65#ibcon#about to read 4, iclass 24, count 0 2006.238.07:38:20.65#ibcon#read 4, iclass 24, count 0 2006.238.07:38:20.65#ibcon#about to read 5, iclass 24, count 0 2006.238.07:38:20.65#ibcon#read 5, iclass 24, count 0 2006.238.07:38:20.65#ibcon#about to read 6, iclass 24, count 0 2006.238.07:38:20.65#ibcon#read 6, iclass 24, count 0 2006.238.07:38:20.65#ibcon#end of sib2, iclass 24, count 0 2006.238.07:38:20.65#ibcon#*after write, iclass 24, count 0 2006.238.07:38:20.65#ibcon#*before return 0, iclass 24, count 0 2006.238.07:38:20.65#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:38:20.65#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:38:20.65#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:38:20.65#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:38:20.65$vc4f8/vblo=1,632.99 2006.238.07:38:20.65#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.07:38:20.65#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.07:38:20.65#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:20.65#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:38:20.65#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:38:20.65#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:38:20.65#ibcon#enter wrdev, iclass 26, count 0 2006.238.07:38:20.65#ibcon#first serial, iclass 26, count 0 2006.238.07:38:20.65#ibcon#enter sib2, iclass 26, count 0 2006.238.07:38:20.65#ibcon#flushed, iclass 26, count 0 2006.238.07:38:20.65#ibcon#about to write, iclass 26, count 0 2006.238.07:38:20.65#ibcon#wrote, iclass 26, count 0 2006.238.07:38:20.65#ibcon#about to read 3, iclass 26, count 0 2006.238.07:38:20.67#ibcon#read 3, iclass 26, count 0 2006.238.07:38:20.67#ibcon#about to read 4, iclass 26, count 0 2006.238.07:38:20.67#ibcon#read 4, iclass 26, count 0 2006.238.07:38:20.67#ibcon#about to read 5, iclass 26, count 0 2006.238.07:38:20.67#ibcon#read 5, iclass 26, count 0 2006.238.07:38:20.67#ibcon#about to read 6, iclass 26, count 0 2006.238.07:38:20.67#ibcon#read 6, iclass 26, count 0 2006.238.07:38:20.67#ibcon#end of sib2, iclass 26, count 0 2006.238.07:38:20.67#ibcon#*mode == 0, iclass 26, count 0 2006.238.07:38:20.67#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.07:38:20.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:38:20.67#ibcon#*before write, iclass 26, count 0 2006.238.07:38:20.67#ibcon#enter sib2, iclass 26, count 0 2006.238.07:38:20.67#ibcon#flushed, iclass 26, count 0 2006.238.07:38:20.67#ibcon#about to write, iclass 26, count 0 2006.238.07:38:20.67#ibcon#wrote, iclass 26, count 0 2006.238.07:38:20.67#ibcon#about to read 3, iclass 26, count 0 2006.238.07:38:20.71#ibcon#read 3, iclass 26, count 0 2006.238.07:38:20.71#ibcon#about to read 4, iclass 26, count 0 2006.238.07:38:20.71#ibcon#read 4, iclass 26, count 0 2006.238.07:38:20.71#ibcon#about to read 5, iclass 26, count 0 2006.238.07:38:20.71#ibcon#read 5, iclass 26, count 0 2006.238.07:38:20.71#ibcon#about to read 6, iclass 26, count 0 2006.238.07:38:20.71#ibcon#read 6, iclass 26, count 0 2006.238.07:38:20.71#ibcon#end of sib2, iclass 26, count 0 2006.238.07:38:20.71#ibcon#*after write, iclass 26, count 0 2006.238.07:38:20.71#ibcon#*before return 0, iclass 26, count 0 2006.238.07:38:20.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:38:20.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:38:20.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.07:38:20.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.07:38:20.71$vc4f8/vb=1,4 2006.238.07:38:20.71#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.07:38:20.71#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.07:38:20.71#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:20.71#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:38:20.71#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:38:20.71#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:38:20.71#ibcon#enter wrdev, iclass 28, count 2 2006.238.07:38:20.71#ibcon#first serial, iclass 28, count 2 2006.238.07:38:20.71#ibcon#enter sib2, iclass 28, count 2 2006.238.07:38:20.71#ibcon#flushed, iclass 28, count 2 2006.238.07:38:20.71#ibcon#about to write, iclass 28, count 2 2006.238.07:38:20.71#ibcon#wrote, iclass 28, count 2 2006.238.07:38:20.71#ibcon#about to read 3, iclass 28, count 2 2006.238.07:38:20.73#ibcon#read 3, iclass 28, count 2 2006.238.07:38:20.73#ibcon#about to read 4, iclass 28, count 2 2006.238.07:38:20.73#ibcon#read 4, iclass 28, count 2 2006.238.07:38:20.73#ibcon#about to read 5, iclass 28, count 2 2006.238.07:38:20.73#ibcon#read 5, iclass 28, count 2 2006.238.07:38:20.73#ibcon#about to read 6, iclass 28, count 2 2006.238.07:38:20.73#ibcon#read 6, iclass 28, count 2 2006.238.07:38:20.73#ibcon#end of sib2, iclass 28, count 2 2006.238.07:38:20.73#ibcon#*mode == 0, iclass 28, count 2 2006.238.07:38:20.73#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.07:38:20.73#ibcon#[27=AT01-04\r\n] 2006.238.07:38:20.73#ibcon#*before write, iclass 28, count 2 2006.238.07:38:20.73#ibcon#enter sib2, iclass 28, count 2 2006.238.07:38:20.73#ibcon#flushed, iclass 28, count 2 2006.238.07:38:20.73#ibcon#about to write, iclass 28, count 2 2006.238.07:38:20.73#ibcon#wrote, iclass 28, count 2 2006.238.07:38:20.73#ibcon#about to read 3, iclass 28, count 2 2006.238.07:38:20.76#ibcon#read 3, iclass 28, count 2 2006.238.07:38:20.76#ibcon#about to read 4, iclass 28, count 2 2006.238.07:38:20.76#ibcon#read 4, iclass 28, count 2 2006.238.07:38:20.76#ibcon#about to read 5, iclass 28, count 2 2006.238.07:38:20.76#ibcon#read 5, iclass 28, count 2 2006.238.07:38:20.76#ibcon#about to read 6, iclass 28, count 2 2006.238.07:38:20.76#ibcon#read 6, iclass 28, count 2 2006.238.07:38:20.76#ibcon#end of sib2, iclass 28, count 2 2006.238.07:38:20.76#ibcon#*after write, iclass 28, count 2 2006.238.07:38:20.76#ibcon#*before return 0, iclass 28, count 2 2006.238.07:38:20.76#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:38:20.76#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:38:20.76#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.07:38:20.76#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:20.76#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:38:20.88#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:38:20.88#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:38:20.88#ibcon#enter wrdev, iclass 28, count 0 2006.238.07:38:20.88#ibcon#first serial, iclass 28, count 0 2006.238.07:38:20.88#ibcon#enter sib2, iclass 28, count 0 2006.238.07:38:20.88#ibcon#flushed, iclass 28, count 0 2006.238.07:38:20.88#ibcon#about to write, iclass 28, count 0 2006.238.07:38:20.88#ibcon#wrote, iclass 28, count 0 2006.238.07:38:20.88#ibcon#about to read 3, iclass 28, count 0 2006.238.07:38:20.90#ibcon#read 3, iclass 28, count 0 2006.238.07:38:20.90#ibcon#about to read 4, iclass 28, count 0 2006.238.07:38:20.90#ibcon#read 4, iclass 28, count 0 2006.238.07:38:20.90#ibcon#about to read 5, iclass 28, count 0 2006.238.07:38:20.90#ibcon#read 5, iclass 28, count 0 2006.238.07:38:20.90#ibcon#about to read 6, iclass 28, count 0 2006.238.07:38:20.90#ibcon#read 6, iclass 28, count 0 2006.238.07:38:20.90#ibcon#end of sib2, iclass 28, count 0 2006.238.07:38:20.90#ibcon#*mode == 0, iclass 28, count 0 2006.238.07:38:20.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.07:38:20.90#ibcon#[27=USB\r\n] 2006.238.07:38:20.90#ibcon#*before write, iclass 28, count 0 2006.238.07:38:20.90#ibcon#enter sib2, iclass 28, count 0 2006.238.07:38:20.90#ibcon#flushed, iclass 28, count 0 2006.238.07:38:20.90#ibcon#about to write, iclass 28, count 0 2006.238.07:38:20.90#ibcon#wrote, iclass 28, count 0 2006.238.07:38:20.90#ibcon#about to read 3, iclass 28, count 0 2006.238.07:38:20.93#ibcon#read 3, iclass 28, count 0 2006.238.07:38:20.93#ibcon#about to read 4, iclass 28, count 0 2006.238.07:38:20.93#ibcon#read 4, iclass 28, count 0 2006.238.07:38:20.93#ibcon#about to read 5, iclass 28, count 0 2006.238.07:38:20.93#ibcon#read 5, iclass 28, count 0 2006.238.07:38:20.93#ibcon#about to read 6, iclass 28, count 0 2006.238.07:38:20.93#ibcon#read 6, iclass 28, count 0 2006.238.07:38:20.93#ibcon#end of sib2, iclass 28, count 0 2006.238.07:38:20.93#ibcon#*after write, iclass 28, count 0 2006.238.07:38:20.93#ibcon#*before return 0, iclass 28, count 0 2006.238.07:38:20.93#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:38:20.93#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:38:20.93#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.07:38:20.93#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.07:38:20.93$vc4f8/vblo=2,640.99 2006.238.07:38:20.93#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.07:38:20.93#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.07:38:20.93#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:20.93#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:38:20.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:38:20.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:38:20.93#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:38:20.93#ibcon#first serial, iclass 30, count 0 2006.238.07:38:20.93#ibcon#enter sib2, iclass 30, count 0 2006.238.07:38:20.93#ibcon#flushed, iclass 30, count 0 2006.238.07:38:20.93#ibcon#about to write, iclass 30, count 0 2006.238.07:38:20.93#ibcon#wrote, iclass 30, count 0 2006.238.07:38:20.93#ibcon#about to read 3, iclass 30, count 0 2006.238.07:38:20.95#ibcon#read 3, iclass 30, count 0 2006.238.07:38:20.95#ibcon#about to read 4, iclass 30, count 0 2006.238.07:38:20.95#ibcon#read 4, iclass 30, count 0 2006.238.07:38:20.95#ibcon#about to read 5, iclass 30, count 0 2006.238.07:38:20.95#ibcon#read 5, iclass 30, count 0 2006.238.07:38:20.95#ibcon#about to read 6, iclass 30, count 0 2006.238.07:38:20.95#ibcon#read 6, iclass 30, count 0 2006.238.07:38:20.95#ibcon#end of sib2, iclass 30, count 0 2006.238.07:38:20.95#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:38:20.95#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:38:20.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:38:20.95#ibcon#*before write, iclass 30, count 0 2006.238.07:38:20.95#ibcon#enter sib2, iclass 30, count 0 2006.238.07:38:20.95#ibcon#flushed, iclass 30, count 0 2006.238.07:38:20.95#ibcon#about to write, iclass 30, count 0 2006.238.07:38:20.95#ibcon#wrote, iclass 30, count 0 2006.238.07:38:20.95#ibcon#about to read 3, iclass 30, count 0 2006.238.07:38:20.99#ibcon#read 3, iclass 30, count 0 2006.238.07:38:20.99#ibcon#about to read 4, iclass 30, count 0 2006.238.07:38:20.99#ibcon#read 4, iclass 30, count 0 2006.238.07:38:20.99#ibcon#about to read 5, iclass 30, count 0 2006.238.07:38:20.99#ibcon#read 5, iclass 30, count 0 2006.238.07:38:20.99#ibcon#about to read 6, iclass 30, count 0 2006.238.07:38:20.99#ibcon#read 6, iclass 30, count 0 2006.238.07:38:20.99#ibcon#end of sib2, iclass 30, count 0 2006.238.07:38:20.99#ibcon#*after write, iclass 30, count 0 2006.238.07:38:20.99#ibcon#*before return 0, iclass 30, count 0 2006.238.07:38:20.99#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:38:20.99#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:38:20.99#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:38:20.99#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:38:20.99$vc4f8/vb=2,4 2006.238.07:38:20.99#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.238.07:38:20.99#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.238.07:38:20.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:20.99#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:38:21.05#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:38:21.05#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:38:21.05#ibcon#enter wrdev, iclass 32, count 2 2006.238.07:38:21.05#ibcon#first serial, iclass 32, count 2 2006.238.07:38:21.05#ibcon#enter sib2, iclass 32, count 2 2006.238.07:38:21.05#ibcon#flushed, iclass 32, count 2 2006.238.07:38:21.05#ibcon#about to write, iclass 32, count 2 2006.238.07:38:21.05#ibcon#wrote, iclass 32, count 2 2006.238.07:38:21.05#ibcon#about to read 3, iclass 32, count 2 2006.238.07:38:21.08#ibcon#read 3, iclass 32, count 2 2006.238.07:38:21.08#ibcon#about to read 4, iclass 32, count 2 2006.238.07:38:21.08#ibcon#read 4, iclass 32, count 2 2006.238.07:38:21.08#ibcon#about to read 5, iclass 32, count 2 2006.238.07:38:21.08#ibcon#read 5, iclass 32, count 2 2006.238.07:38:21.08#ibcon#about to read 6, iclass 32, count 2 2006.238.07:38:21.08#ibcon#read 6, iclass 32, count 2 2006.238.07:38:21.08#ibcon#end of sib2, iclass 32, count 2 2006.238.07:38:21.08#ibcon#*mode == 0, iclass 32, count 2 2006.238.07:38:21.08#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.238.07:38:21.08#ibcon#[27=AT02-04\r\n] 2006.238.07:38:21.08#ibcon#*before write, iclass 32, count 2 2006.238.07:38:21.08#ibcon#enter sib2, iclass 32, count 2 2006.238.07:38:21.08#ibcon#flushed, iclass 32, count 2 2006.238.07:38:21.08#ibcon#about to write, iclass 32, count 2 2006.238.07:38:21.08#ibcon#wrote, iclass 32, count 2 2006.238.07:38:21.08#ibcon#about to read 3, iclass 32, count 2 2006.238.07:38:21.11#ibcon#read 3, iclass 32, count 2 2006.238.07:38:21.11#ibcon#about to read 4, iclass 32, count 2 2006.238.07:38:21.11#ibcon#read 4, iclass 32, count 2 2006.238.07:38:21.11#ibcon#about to read 5, iclass 32, count 2 2006.238.07:38:21.11#ibcon#read 5, iclass 32, count 2 2006.238.07:38:21.11#ibcon#about to read 6, iclass 32, count 2 2006.238.07:38:21.11#ibcon#read 6, iclass 32, count 2 2006.238.07:38:21.11#ibcon#end of sib2, iclass 32, count 2 2006.238.07:38:21.11#ibcon#*after write, iclass 32, count 2 2006.238.07:38:21.11#ibcon#*before return 0, iclass 32, count 2 2006.238.07:38:21.11#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:38:21.11#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:38:21.11#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.238.07:38:21.11#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:21.11#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:38:21.23#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:38:21.23#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:38:21.23#ibcon#enter wrdev, iclass 32, count 0 2006.238.07:38:21.23#ibcon#first serial, iclass 32, count 0 2006.238.07:38:21.23#ibcon#enter sib2, iclass 32, count 0 2006.238.07:38:21.23#ibcon#flushed, iclass 32, count 0 2006.238.07:38:21.23#ibcon#about to write, iclass 32, count 0 2006.238.07:38:21.23#ibcon#wrote, iclass 32, count 0 2006.238.07:38:21.23#ibcon#about to read 3, iclass 32, count 0 2006.238.07:38:21.25#ibcon#read 3, iclass 32, count 0 2006.238.07:38:21.25#ibcon#about to read 4, iclass 32, count 0 2006.238.07:38:21.25#ibcon#read 4, iclass 32, count 0 2006.238.07:38:21.25#ibcon#about to read 5, iclass 32, count 0 2006.238.07:38:21.25#ibcon#read 5, iclass 32, count 0 2006.238.07:38:21.25#ibcon#about to read 6, iclass 32, count 0 2006.238.07:38:21.25#ibcon#read 6, iclass 32, count 0 2006.238.07:38:21.25#ibcon#end of sib2, iclass 32, count 0 2006.238.07:38:21.25#ibcon#*mode == 0, iclass 32, count 0 2006.238.07:38:21.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.07:38:21.25#ibcon#[27=USB\r\n] 2006.238.07:38:21.25#ibcon#*before write, iclass 32, count 0 2006.238.07:38:21.25#ibcon#enter sib2, iclass 32, count 0 2006.238.07:38:21.25#ibcon#flushed, iclass 32, count 0 2006.238.07:38:21.25#ibcon#about to write, iclass 32, count 0 2006.238.07:38:21.25#ibcon#wrote, iclass 32, count 0 2006.238.07:38:21.25#ibcon#about to read 3, iclass 32, count 0 2006.238.07:38:21.28#ibcon#read 3, iclass 32, count 0 2006.238.07:38:21.28#ibcon#about to read 4, iclass 32, count 0 2006.238.07:38:21.28#ibcon#read 4, iclass 32, count 0 2006.238.07:38:21.28#ibcon#about to read 5, iclass 32, count 0 2006.238.07:38:21.28#ibcon#read 5, iclass 32, count 0 2006.238.07:38:21.28#ibcon#about to read 6, iclass 32, count 0 2006.238.07:38:21.28#ibcon#read 6, iclass 32, count 0 2006.238.07:38:21.28#ibcon#end of sib2, iclass 32, count 0 2006.238.07:38:21.28#ibcon#*after write, iclass 32, count 0 2006.238.07:38:21.28#ibcon#*before return 0, iclass 32, count 0 2006.238.07:38:21.28#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:38:21.28#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:38:21.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.07:38:21.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.07:38:21.28$vc4f8/vblo=3,656.99 2006.238.07:38:21.28#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.238.07:38:21.28#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.238.07:38:21.28#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:21.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:38:21.28#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:38:21.28#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:38:21.28#ibcon#enter wrdev, iclass 34, count 0 2006.238.07:38:21.28#ibcon#first serial, iclass 34, count 0 2006.238.07:38:21.28#ibcon#enter sib2, iclass 34, count 0 2006.238.07:38:21.28#ibcon#flushed, iclass 34, count 0 2006.238.07:38:21.28#ibcon#about to write, iclass 34, count 0 2006.238.07:38:21.28#ibcon#wrote, iclass 34, count 0 2006.238.07:38:21.28#ibcon#about to read 3, iclass 34, count 0 2006.238.07:38:21.30#ibcon#read 3, iclass 34, count 0 2006.238.07:38:21.30#ibcon#about to read 4, iclass 34, count 0 2006.238.07:38:21.30#ibcon#read 4, iclass 34, count 0 2006.238.07:38:21.30#ibcon#about to read 5, iclass 34, count 0 2006.238.07:38:21.30#ibcon#read 5, iclass 34, count 0 2006.238.07:38:21.30#ibcon#about to read 6, iclass 34, count 0 2006.238.07:38:21.30#ibcon#read 6, iclass 34, count 0 2006.238.07:38:21.30#ibcon#end of sib2, iclass 34, count 0 2006.238.07:38:21.30#ibcon#*mode == 0, iclass 34, count 0 2006.238.07:38:21.30#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.07:38:21.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:38:21.30#ibcon#*before write, iclass 34, count 0 2006.238.07:38:21.30#ibcon#enter sib2, iclass 34, count 0 2006.238.07:38:21.30#ibcon#flushed, iclass 34, count 0 2006.238.07:38:21.30#ibcon#about to write, iclass 34, count 0 2006.238.07:38:21.30#ibcon#wrote, iclass 34, count 0 2006.238.07:38:21.30#ibcon#about to read 3, iclass 34, count 0 2006.238.07:38:21.34#ibcon#read 3, iclass 34, count 0 2006.238.07:38:21.34#ibcon#about to read 4, iclass 34, count 0 2006.238.07:38:21.34#ibcon#read 4, iclass 34, count 0 2006.238.07:38:21.34#ibcon#about to read 5, iclass 34, count 0 2006.238.07:38:21.34#ibcon#read 5, iclass 34, count 0 2006.238.07:38:21.34#ibcon#about to read 6, iclass 34, count 0 2006.238.07:38:21.34#ibcon#read 6, iclass 34, count 0 2006.238.07:38:21.34#ibcon#end of sib2, iclass 34, count 0 2006.238.07:38:21.34#ibcon#*after write, iclass 34, count 0 2006.238.07:38:21.34#ibcon#*before return 0, iclass 34, count 0 2006.238.07:38:21.34#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:38:21.34#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:38:21.34#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.07:38:21.34#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.07:38:21.34$vc4f8/vb=3,4 2006.238.07:38:21.34#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.238.07:38:21.34#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.238.07:38:21.34#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:21.34#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:38:21.40#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:38:21.40#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:38:21.40#ibcon#enter wrdev, iclass 36, count 2 2006.238.07:38:21.40#ibcon#first serial, iclass 36, count 2 2006.238.07:38:21.40#ibcon#enter sib2, iclass 36, count 2 2006.238.07:38:21.40#ibcon#flushed, iclass 36, count 2 2006.238.07:38:21.40#ibcon#about to write, iclass 36, count 2 2006.238.07:38:21.40#ibcon#wrote, iclass 36, count 2 2006.238.07:38:21.40#ibcon#about to read 3, iclass 36, count 2 2006.238.07:38:21.42#ibcon#read 3, iclass 36, count 2 2006.238.07:38:21.42#ibcon#about to read 4, iclass 36, count 2 2006.238.07:38:21.42#ibcon#read 4, iclass 36, count 2 2006.238.07:38:21.42#ibcon#about to read 5, iclass 36, count 2 2006.238.07:38:21.42#ibcon#read 5, iclass 36, count 2 2006.238.07:38:21.42#ibcon#about to read 6, iclass 36, count 2 2006.238.07:38:21.42#ibcon#read 6, iclass 36, count 2 2006.238.07:38:21.42#ibcon#end of sib2, iclass 36, count 2 2006.238.07:38:21.42#ibcon#*mode == 0, iclass 36, count 2 2006.238.07:38:21.42#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.238.07:38:21.42#ibcon#[27=AT03-04\r\n] 2006.238.07:38:21.42#ibcon#*before write, iclass 36, count 2 2006.238.07:38:21.42#ibcon#enter sib2, iclass 36, count 2 2006.238.07:38:21.42#ibcon#flushed, iclass 36, count 2 2006.238.07:38:21.42#ibcon#about to write, iclass 36, count 2 2006.238.07:38:21.42#ibcon#wrote, iclass 36, count 2 2006.238.07:38:21.42#ibcon#about to read 3, iclass 36, count 2 2006.238.07:38:21.45#ibcon#read 3, iclass 36, count 2 2006.238.07:38:21.45#ibcon#about to read 4, iclass 36, count 2 2006.238.07:38:21.45#ibcon#read 4, iclass 36, count 2 2006.238.07:38:21.45#ibcon#about to read 5, iclass 36, count 2 2006.238.07:38:21.45#ibcon#read 5, iclass 36, count 2 2006.238.07:38:21.45#ibcon#about to read 6, iclass 36, count 2 2006.238.07:38:21.45#ibcon#read 6, iclass 36, count 2 2006.238.07:38:21.45#ibcon#end of sib2, iclass 36, count 2 2006.238.07:38:21.45#ibcon#*after write, iclass 36, count 2 2006.238.07:38:21.45#ibcon#*before return 0, iclass 36, count 2 2006.238.07:38:21.45#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:38:21.45#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:38:21.45#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.238.07:38:21.45#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:21.45#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:38:21.57#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:38:21.57#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:38:21.57#ibcon#enter wrdev, iclass 36, count 0 2006.238.07:38:21.57#ibcon#first serial, iclass 36, count 0 2006.238.07:38:21.57#ibcon#enter sib2, iclass 36, count 0 2006.238.07:38:21.57#ibcon#flushed, iclass 36, count 0 2006.238.07:38:21.57#ibcon#about to write, iclass 36, count 0 2006.238.07:38:21.57#ibcon#wrote, iclass 36, count 0 2006.238.07:38:21.57#ibcon#about to read 3, iclass 36, count 0 2006.238.07:38:21.59#ibcon#read 3, iclass 36, count 0 2006.238.07:38:21.59#ibcon#about to read 4, iclass 36, count 0 2006.238.07:38:21.59#ibcon#read 4, iclass 36, count 0 2006.238.07:38:21.59#ibcon#about to read 5, iclass 36, count 0 2006.238.07:38:21.59#ibcon#read 5, iclass 36, count 0 2006.238.07:38:21.59#ibcon#about to read 6, iclass 36, count 0 2006.238.07:38:21.59#ibcon#read 6, iclass 36, count 0 2006.238.07:38:21.59#ibcon#end of sib2, iclass 36, count 0 2006.238.07:38:21.59#ibcon#*mode == 0, iclass 36, count 0 2006.238.07:38:21.59#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.07:38:21.59#ibcon#[27=USB\r\n] 2006.238.07:38:21.59#ibcon#*before write, iclass 36, count 0 2006.238.07:38:21.59#ibcon#enter sib2, iclass 36, count 0 2006.238.07:38:21.59#ibcon#flushed, iclass 36, count 0 2006.238.07:38:21.59#ibcon#about to write, iclass 36, count 0 2006.238.07:38:21.59#ibcon#wrote, iclass 36, count 0 2006.238.07:38:21.59#ibcon#about to read 3, iclass 36, count 0 2006.238.07:38:21.62#ibcon#read 3, iclass 36, count 0 2006.238.07:38:21.62#ibcon#about to read 4, iclass 36, count 0 2006.238.07:38:21.62#ibcon#read 4, iclass 36, count 0 2006.238.07:38:21.62#ibcon#about to read 5, iclass 36, count 0 2006.238.07:38:21.62#ibcon#read 5, iclass 36, count 0 2006.238.07:38:21.62#ibcon#about to read 6, iclass 36, count 0 2006.238.07:38:21.62#ibcon#read 6, iclass 36, count 0 2006.238.07:38:21.62#ibcon#end of sib2, iclass 36, count 0 2006.238.07:38:21.62#ibcon#*after write, iclass 36, count 0 2006.238.07:38:21.62#ibcon#*before return 0, iclass 36, count 0 2006.238.07:38:21.62#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:38:21.62#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:38:21.62#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.07:38:21.62#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.07:38:21.62$vc4f8/vblo=4,712.99 2006.238.07:38:21.62#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.238.07:38:21.62#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.238.07:38:21.62#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:21.62#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:38:21.62#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:38:21.62#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:38:21.62#ibcon#enter wrdev, iclass 38, count 0 2006.238.07:38:21.62#ibcon#first serial, iclass 38, count 0 2006.238.07:38:21.62#ibcon#enter sib2, iclass 38, count 0 2006.238.07:38:21.62#ibcon#flushed, iclass 38, count 0 2006.238.07:38:21.62#ibcon#about to write, iclass 38, count 0 2006.238.07:38:21.62#ibcon#wrote, iclass 38, count 0 2006.238.07:38:21.62#ibcon#about to read 3, iclass 38, count 0 2006.238.07:38:21.64#ibcon#read 3, iclass 38, count 0 2006.238.07:38:21.64#ibcon#about to read 4, iclass 38, count 0 2006.238.07:38:21.64#ibcon#read 4, iclass 38, count 0 2006.238.07:38:21.64#ibcon#about to read 5, iclass 38, count 0 2006.238.07:38:21.64#ibcon#read 5, iclass 38, count 0 2006.238.07:38:21.64#ibcon#about to read 6, iclass 38, count 0 2006.238.07:38:21.64#ibcon#read 6, iclass 38, count 0 2006.238.07:38:21.64#ibcon#end of sib2, iclass 38, count 0 2006.238.07:38:21.64#ibcon#*mode == 0, iclass 38, count 0 2006.238.07:38:21.64#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.07:38:21.64#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:38:21.64#ibcon#*before write, iclass 38, count 0 2006.238.07:38:21.64#ibcon#enter sib2, iclass 38, count 0 2006.238.07:38:21.64#ibcon#flushed, iclass 38, count 0 2006.238.07:38:21.64#ibcon#about to write, iclass 38, count 0 2006.238.07:38:21.64#ibcon#wrote, iclass 38, count 0 2006.238.07:38:21.64#ibcon#about to read 3, iclass 38, count 0 2006.238.07:38:21.68#ibcon#read 3, iclass 38, count 0 2006.238.07:38:21.68#ibcon#about to read 4, iclass 38, count 0 2006.238.07:38:21.68#ibcon#read 4, iclass 38, count 0 2006.238.07:38:21.68#ibcon#about to read 5, iclass 38, count 0 2006.238.07:38:21.68#ibcon#read 5, iclass 38, count 0 2006.238.07:38:21.68#ibcon#about to read 6, iclass 38, count 0 2006.238.07:38:21.68#ibcon#read 6, iclass 38, count 0 2006.238.07:38:21.68#ibcon#end of sib2, iclass 38, count 0 2006.238.07:38:21.68#ibcon#*after write, iclass 38, count 0 2006.238.07:38:21.68#ibcon#*before return 0, iclass 38, count 0 2006.238.07:38:21.68#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:38:21.68#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:38:21.68#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.07:38:21.68#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.07:38:21.68$vc4f8/vb=4,4 2006.238.07:38:21.68#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.238.07:38:21.68#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.238.07:38:21.68#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:21.68#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:38:21.75#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:38:21.75#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:38:21.75#ibcon#enter wrdev, iclass 40, count 2 2006.238.07:38:21.75#ibcon#first serial, iclass 40, count 2 2006.238.07:38:21.75#ibcon#enter sib2, iclass 40, count 2 2006.238.07:38:21.75#ibcon#flushed, iclass 40, count 2 2006.238.07:38:21.75#ibcon#about to write, iclass 40, count 2 2006.238.07:38:21.75#ibcon#wrote, iclass 40, count 2 2006.238.07:38:21.75#ibcon#about to read 3, iclass 40, count 2 2006.238.07:38:21.76#ibcon#read 3, iclass 40, count 2 2006.238.07:38:21.76#ibcon#about to read 4, iclass 40, count 2 2006.238.07:38:21.76#ibcon#read 4, iclass 40, count 2 2006.238.07:38:21.76#ibcon#about to read 5, iclass 40, count 2 2006.238.07:38:21.76#ibcon#read 5, iclass 40, count 2 2006.238.07:38:21.76#ibcon#about to read 6, iclass 40, count 2 2006.238.07:38:21.76#ibcon#read 6, iclass 40, count 2 2006.238.07:38:21.76#ibcon#end of sib2, iclass 40, count 2 2006.238.07:38:21.76#ibcon#*mode == 0, iclass 40, count 2 2006.238.07:38:21.76#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.238.07:38:21.76#ibcon#[27=AT04-04\r\n] 2006.238.07:38:21.76#ibcon#*before write, iclass 40, count 2 2006.238.07:38:21.76#ibcon#enter sib2, iclass 40, count 2 2006.238.07:38:21.76#ibcon#flushed, iclass 40, count 2 2006.238.07:38:21.76#ibcon#about to write, iclass 40, count 2 2006.238.07:38:21.76#ibcon#wrote, iclass 40, count 2 2006.238.07:38:21.76#ibcon#about to read 3, iclass 40, count 2 2006.238.07:38:21.79#ibcon#read 3, iclass 40, count 2 2006.238.07:38:21.79#ibcon#about to read 4, iclass 40, count 2 2006.238.07:38:21.79#ibcon#read 4, iclass 40, count 2 2006.238.07:38:21.79#ibcon#about to read 5, iclass 40, count 2 2006.238.07:38:21.79#ibcon#read 5, iclass 40, count 2 2006.238.07:38:21.79#ibcon#about to read 6, iclass 40, count 2 2006.238.07:38:21.79#ibcon#read 6, iclass 40, count 2 2006.238.07:38:21.79#ibcon#end of sib2, iclass 40, count 2 2006.238.07:38:21.79#ibcon#*after write, iclass 40, count 2 2006.238.07:38:21.79#ibcon#*before return 0, iclass 40, count 2 2006.238.07:38:21.79#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:38:21.79#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:38:21.79#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.238.07:38:21.79#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:21.79#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:38:21.91#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:38:21.91#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:38:21.91#ibcon#enter wrdev, iclass 40, count 0 2006.238.07:38:21.91#ibcon#first serial, iclass 40, count 0 2006.238.07:38:21.91#ibcon#enter sib2, iclass 40, count 0 2006.238.07:38:21.91#ibcon#flushed, iclass 40, count 0 2006.238.07:38:21.91#ibcon#about to write, iclass 40, count 0 2006.238.07:38:21.91#ibcon#wrote, iclass 40, count 0 2006.238.07:38:21.91#ibcon#about to read 3, iclass 40, count 0 2006.238.07:38:21.93#ibcon#read 3, iclass 40, count 0 2006.238.07:38:21.93#ibcon#about to read 4, iclass 40, count 0 2006.238.07:38:21.93#ibcon#read 4, iclass 40, count 0 2006.238.07:38:21.93#ibcon#about to read 5, iclass 40, count 0 2006.238.07:38:21.93#ibcon#read 5, iclass 40, count 0 2006.238.07:38:21.93#ibcon#about to read 6, iclass 40, count 0 2006.238.07:38:21.93#ibcon#read 6, iclass 40, count 0 2006.238.07:38:21.93#ibcon#end of sib2, iclass 40, count 0 2006.238.07:38:21.93#ibcon#*mode == 0, iclass 40, count 0 2006.238.07:38:21.93#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.07:38:21.93#ibcon#[27=USB\r\n] 2006.238.07:38:21.93#ibcon#*before write, iclass 40, count 0 2006.238.07:38:21.93#ibcon#enter sib2, iclass 40, count 0 2006.238.07:38:21.93#ibcon#flushed, iclass 40, count 0 2006.238.07:38:21.93#ibcon#about to write, iclass 40, count 0 2006.238.07:38:21.93#ibcon#wrote, iclass 40, count 0 2006.238.07:38:21.93#ibcon#about to read 3, iclass 40, count 0 2006.238.07:38:21.96#ibcon#read 3, iclass 40, count 0 2006.238.07:38:21.96#ibcon#about to read 4, iclass 40, count 0 2006.238.07:38:21.96#ibcon#read 4, iclass 40, count 0 2006.238.07:38:21.96#ibcon#about to read 5, iclass 40, count 0 2006.238.07:38:21.96#ibcon#read 5, iclass 40, count 0 2006.238.07:38:21.96#ibcon#about to read 6, iclass 40, count 0 2006.238.07:38:21.96#ibcon#read 6, iclass 40, count 0 2006.238.07:38:21.96#ibcon#end of sib2, iclass 40, count 0 2006.238.07:38:21.96#ibcon#*after write, iclass 40, count 0 2006.238.07:38:21.96#ibcon#*before return 0, iclass 40, count 0 2006.238.07:38:21.96#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:38:21.96#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:38:21.96#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.07:38:21.96#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.07:38:21.96$vc4f8/vblo=5,744.99 2006.238.07:38:21.96#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.07:38:21.96#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.07:38:21.96#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:21.96#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:38:21.96#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:38:21.96#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:38:21.96#ibcon#enter wrdev, iclass 4, count 0 2006.238.07:38:21.96#ibcon#first serial, iclass 4, count 0 2006.238.07:38:21.96#ibcon#enter sib2, iclass 4, count 0 2006.238.07:38:21.96#ibcon#flushed, iclass 4, count 0 2006.238.07:38:21.96#ibcon#about to write, iclass 4, count 0 2006.238.07:38:21.96#ibcon#wrote, iclass 4, count 0 2006.238.07:38:21.96#ibcon#about to read 3, iclass 4, count 0 2006.238.07:38:21.98#ibcon#read 3, iclass 4, count 0 2006.238.07:38:21.98#ibcon#about to read 4, iclass 4, count 0 2006.238.07:38:21.98#ibcon#read 4, iclass 4, count 0 2006.238.07:38:21.98#ibcon#about to read 5, iclass 4, count 0 2006.238.07:38:21.98#ibcon#read 5, iclass 4, count 0 2006.238.07:38:21.98#ibcon#about to read 6, iclass 4, count 0 2006.238.07:38:21.98#ibcon#read 6, iclass 4, count 0 2006.238.07:38:21.98#ibcon#end of sib2, iclass 4, count 0 2006.238.07:38:21.98#ibcon#*mode == 0, iclass 4, count 0 2006.238.07:38:21.98#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.07:38:21.98#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:38:21.98#ibcon#*before write, iclass 4, count 0 2006.238.07:38:21.98#ibcon#enter sib2, iclass 4, count 0 2006.238.07:38:21.98#ibcon#flushed, iclass 4, count 0 2006.238.07:38:21.98#ibcon#about to write, iclass 4, count 0 2006.238.07:38:21.98#ibcon#wrote, iclass 4, count 0 2006.238.07:38:21.98#ibcon#about to read 3, iclass 4, count 0 2006.238.07:38:22.02#ibcon#read 3, iclass 4, count 0 2006.238.07:38:22.02#ibcon#about to read 4, iclass 4, count 0 2006.238.07:38:22.02#ibcon#read 4, iclass 4, count 0 2006.238.07:38:22.02#ibcon#about to read 5, iclass 4, count 0 2006.238.07:38:22.02#ibcon#read 5, iclass 4, count 0 2006.238.07:38:22.02#ibcon#about to read 6, iclass 4, count 0 2006.238.07:38:22.02#ibcon#read 6, iclass 4, count 0 2006.238.07:38:22.02#ibcon#end of sib2, iclass 4, count 0 2006.238.07:38:22.02#ibcon#*after write, iclass 4, count 0 2006.238.07:38:22.02#ibcon#*before return 0, iclass 4, count 0 2006.238.07:38:22.02#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:38:22.02#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:38:22.02#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.07:38:22.02#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.07:38:22.02$vc4f8/vb=5,4 2006.238.07:38:22.02#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.07:38:22.02#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.07:38:22.02#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:22.02#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:38:22.08#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:38:22.08#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:38:22.08#ibcon#enter wrdev, iclass 6, count 2 2006.238.07:38:22.08#ibcon#first serial, iclass 6, count 2 2006.238.07:38:22.08#ibcon#enter sib2, iclass 6, count 2 2006.238.07:38:22.08#ibcon#flushed, iclass 6, count 2 2006.238.07:38:22.08#ibcon#about to write, iclass 6, count 2 2006.238.07:38:22.08#ibcon#wrote, iclass 6, count 2 2006.238.07:38:22.08#ibcon#about to read 3, iclass 6, count 2 2006.238.07:38:22.10#ibcon#read 3, iclass 6, count 2 2006.238.07:38:22.10#ibcon#about to read 4, iclass 6, count 2 2006.238.07:38:22.10#ibcon#read 4, iclass 6, count 2 2006.238.07:38:22.10#ibcon#about to read 5, iclass 6, count 2 2006.238.07:38:22.10#ibcon#read 5, iclass 6, count 2 2006.238.07:38:22.10#ibcon#about to read 6, iclass 6, count 2 2006.238.07:38:22.10#ibcon#read 6, iclass 6, count 2 2006.238.07:38:22.10#ibcon#end of sib2, iclass 6, count 2 2006.238.07:38:22.10#ibcon#*mode == 0, iclass 6, count 2 2006.238.07:38:22.10#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.07:38:22.10#ibcon#[27=AT05-04\r\n] 2006.238.07:38:22.10#ibcon#*before write, iclass 6, count 2 2006.238.07:38:22.10#ibcon#enter sib2, iclass 6, count 2 2006.238.07:38:22.10#ibcon#flushed, iclass 6, count 2 2006.238.07:38:22.10#ibcon#about to write, iclass 6, count 2 2006.238.07:38:22.10#ibcon#wrote, iclass 6, count 2 2006.238.07:38:22.10#ibcon#about to read 3, iclass 6, count 2 2006.238.07:38:22.13#ibcon#read 3, iclass 6, count 2 2006.238.07:38:22.13#ibcon#about to read 4, iclass 6, count 2 2006.238.07:38:22.13#ibcon#read 4, iclass 6, count 2 2006.238.07:38:22.13#ibcon#about to read 5, iclass 6, count 2 2006.238.07:38:22.13#ibcon#read 5, iclass 6, count 2 2006.238.07:38:22.13#ibcon#about to read 6, iclass 6, count 2 2006.238.07:38:22.13#ibcon#read 6, iclass 6, count 2 2006.238.07:38:22.13#ibcon#end of sib2, iclass 6, count 2 2006.238.07:38:22.13#ibcon#*after write, iclass 6, count 2 2006.238.07:38:22.13#ibcon#*before return 0, iclass 6, count 2 2006.238.07:38:22.13#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:38:22.13#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:38:22.13#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.07:38:22.13#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:22.13#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:38:22.23#abcon#<5=/04 1.8 3.4 25.33 871012.2\r\n> 2006.238.07:38:22.25#abcon#{5=INTERFACE CLEAR} 2006.238.07:38:22.25#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:38:22.25#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:38:22.25#ibcon#enter wrdev, iclass 6, count 0 2006.238.07:38:22.25#ibcon#first serial, iclass 6, count 0 2006.238.07:38:22.25#ibcon#enter sib2, iclass 6, count 0 2006.238.07:38:22.25#ibcon#flushed, iclass 6, count 0 2006.238.07:38:22.25#ibcon#about to write, iclass 6, count 0 2006.238.07:38:22.25#ibcon#wrote, iclass 6, count 0 2006.238.07:38:22.25#ibcon#about to read 3, iclass 6, count 0 2006.238.07:38:22.27#ibcon#read 3, iclass 6, count 0 2006.238.07:38:22.27#ibcon#about to read 4, iclass 6, count 0 2006.238.07:38:22.27#ibcon#read 4, iclass 6, count 0 2006.238.07:38:22.27#ibcon#about to read 5, iclass 6, count 0 2006.238.07:38:22.27#ibcon#read 5, iclass 6, count 0 2006.238.07:38:22.27#ibcon#about to read 6, iclass 6, count 0 2006.238.07:38:22.27#ibcon#read 6, iclass 6, count 0 2006.238.07:38:22.27#ibcon#end of sib2, iclass 6, count 0 2006.238.07:38:22.27#ibcon#*mode == 0, iclass 6, count 0 2006.238.07:38:22.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.07:38:22.27#ibcon#[27=USB\r\n] 2006.238.07:38:22.27#ibcon#*before write, iclass 6, count 0 2006.238.07:38:22.27#ibcon#enter sib2, iclass 6, count 0 2006.238.07:38:22.27#ibcon#flushed, iclass 6, count 0 2006.238.07:38:22.27#ibcon#about to write, iclass 6, count 0 2006.238.07:38:22.27#ibcon#wrote, iclass 6, count 0 2006.238.07:38:22.27#ibcon#about to read 3, iclass 6, count 0 2006.238.07:38:22.30#ibcon#read 3, iclass 6, count 0 2006.238.07:38:22.30#ibcon#about to read 4, iclass 6, count 0 2006.238.07:38:22.30#ibcon#read 4, iclass 6, count 0 2006.238.07:38:22.30#ibcon#about to read 5, iclass 6, count 0 2006.238.07:38:22.30#ibcon#read 5, iclass 6, count 0 2006.238.07:38:22.30#ibcon#about to read 6, iclass 6, count 0 2006.238.07:38:22.30#ibcon#read 6, iclass 6, count 0 2006.238.07:38:22.30#ibcon#end of sib2, iclass 6, count 0 2006.238.07:38:22.30#ibcon#*after write, iclass 6, count 0 2006.238.07:38:22.30#ibcon#*before return 0, iclass 6, count 0 2006.238.07:38:22.30#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:38:22.30#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:38:22.30#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.07:38:22.30#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.07:38:22.30$vc4f8/vblo=6,752.99 2006.238.07:38:22.30#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.07:38:22.30#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.07:38:22.30#ibcon#ireg 17 cls_cnt 0 2006.238.07:38:22.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:38:22.30#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:38:22.30#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:38:22.30#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:38:22.30#ibcon#first serial, iclass 14, count 0 2006.238.07:38:22.30#ibcon#enter sib2, iclass 14, count 0 2006.238.07:38:22.30#ibcon#flushed, iclass 14, count 0 2006.238.07:38:22.30#ibcon#about to write, iclass 14, count 0 2006.238.07:38:22.30#ibcon#wrote, iclass 14, count 0 2006.238.07:38:22.30#ibcon#about to read 3, iclass 14, count 0 2006.238.07:38:22.31#abcon#[5=S1D000X0/0*\r\n] 2006.238.07:38:22.32#ibcon#read 3, iclass 14, count 0 2006.238.07:38:22.32#ibcon#about to read 4, iclass 14, count 0 2006.238.07:38:22.32#ibcon#read 4, iclass 14, count 0 2006.238.07:38:22.32#ibcon#about to read 5, iclass 14, count 0 2006.238.07:38:22.32#ibcon#read 5, iclass 14, count 0 2006.238.07:38:22.32#ibcon#about to read 6, iclass 14, count 0 2006.238.07:38:22.32#ibcon#read 6, iclass 14, count 0 2006.238.07:38:22.32#ibcon#end of sib2, iclass 14, count 0 2006.238.07:38:22.32#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:38:22.32#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:38:22.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:38:22.32#ibcon#*before write, iclass 14, count 0 2006.238.07:38:22.32#ibcon#enter sib2, iclass 14, count 0 2006.238.07:38:22.32#ibcon#flushed, iclass 14, count 0 2006.238.07:38:22.32#ibcon#about to write, iclass 14, count 0 2006.238.07:38:22.32#ibcon#wrote, iclass 14, count 0 2006.238.07:38:22.32#ibcon#about to read 3, iclass 14, count 0 2006.238.07:38:22.36#ibcon#read 3, iclass 14, count 0 2006.238.07:38:22.36#ibcon#about to read 4, iclass 14, count 0 2006.238.07:38:22.36#ibcon#read 4, iclass 14, count 0 2006.238.07:38:22.36#ibcon#about to read 5, iclass 14, count 0 2006.238.07:38:22.36#ibcon#read 5, iclass 14, count 0 2006.238.07:38:22.36#ibcon#about to read 6, iclass 14, count 0 2006.238.07:38:22.36#ibcon#read 6, iclass 14, count 0 2006.238.07:38:22.36#ibcon#end of sib2, iclass 14, count 0 2006.238.07:38:22.36#ibcon#*after write, iclass 14, count 0 2006.238.07:38:22.36#ibcon#*before return 0, iclass 14, count 0 2006.238.07:38:22.36#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:38:22.36#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:38:22.36#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:38:22.36#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:38:22.36$vc4f8/vb=6,4 2006.238.07:38:22.36#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.238.07:38:22.36#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.238.07:38:22.36#ibcon#ireg 11 cls_cnt 2 2006.238.07:38:22.36#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:38:22.42#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:38:22.42#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:38:22.42#ibcon#enter wrdev, iclass 16, count 2 2006.238.07:38:22.42#ibcon#first serial, iclass 16, count 2 2006.238.07:38:22.42#ibcon#enter sib2, iclass 16, count 2 2006.238.07:38:22.42#ibcon#flushed, iclass 16, count 2 2006.238.07:38:22.42#ibcon#about to write, iclass 16, count 2 2006.238.07:38:22.42#ibcon#wrote, iclass 16, count 2 2006.238.07:38:22.42#ibcon#about to read 3, iclass 16, count 2 2006.238.07:38:22.44#ibcon#read 3, iclass 16, count 2 2006.238.07:38:22.44#ibcon#about to read 4, iclass 16, count 2 2006.238.07:38:22.44#ibcon#read 4, iclass 16, count 2 2006.238.07:38:22.44#ibcon#about to read 5, iclass 16, count 2 2006.238.07:38:22.44#ibcon#read 5, iclass 16, count 2 2006.238.07:38:22.44#ibcon#about to read 6, iclass 16, count 2 2006.238.07:38:22.44#ibcon#read 6, iclass 16, count 2 2006.238.07:38:22.44#ibcon#end of sib2, iclass 16, count 2 2006.238.07:38:22.44#ibcon#*mode == 0, iclass 16, count 2 2006.238.07:38:22.44#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.238.07:38:22.44#ibcon#[27=AT06-04\r\n] 2006.238.07:38:22.44#ibcon#*before write, iclass 16, count 2 2006.238.07:38:22.44#ibcon#enter sib2, iclass 16, count 2 2006.238.07:38:22.44#ibcon#flushed, iclass 16, count 2 2006.238.07:38:22.44#ibcon#about to write, iclass 16, count 2 2006.238.07:38:22.44#ibcon#wrote, iclass 16, count 2 2006.238.07:38:22.44#ibcon#about to read 3, iclass 16, count 2 2006.238.07:38:22.47#ibcon#read 3, iclass 16, count 2 2006.238.07:38:22.47#ibcon#about to read 4, iclass 16, count 2 2006.238.07:38:22.47#ibcon#read 4, iclass 16, count 2 2006.238.07:38:22.47#ibcon#about to read 5, iclass 16, count 2 2006.238.07:38:22.47#ibcon#read 5, iclass 16, count 2 2006.238.07:38:22.47#ibcon#about to read 6, iclass 16, count 2 2006.238.07:38:22.47#ibcon#read 6, iclass 16, count 2 2006.238.07:38:22.47#ibcon#end of sib2, iclass 16, count 2 2006.238.07:38:22.47#ibcon#*after write, iclass 16, count 2 2006.238.07:38:22.47#ibcon#*before return 0, iclass 16, count 2 2006.238.07:38:22.47#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:38:22.47#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:38:22.47#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.238.07:38:22.47#ibcon#ireg 7 cls_cnt 0 2006.238.07:38:22.47#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:38:22.59#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:38:22.59#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:38:22.59#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:38:22.59#ibcon#first serial, iclass 16, count 0 2006.238.07:38:22.59#ibcon#enter sib2, iclass 16, count 0 2006.238.07:38:22.59#ibcon#flushed, iclass 16, count 0 2006.238.07:38:22.59#ibcon#about to write, iclass 16, count 0 2006.238.07:38:22.59#ibcon#wrote, iclass 16, count 0 2006.238.07:38:22.59#ibcon#about to read 3, iclass 16, count 0 2006.238.07:38:22.61#ibcon#read 3, iclass 16, count 0 2006.238.07:38:22.61#ibcon#about to read 4, iclass 16, count 0 2006.238.07:38:22.61#ibcon#read 4, iclass 16, count 0 2006.238.07:38:22.61#ibcon#about to read 5, iclass 16, count 0 2006.238.07:38:22.61#ibcon#read 5, iclass 16, count 0 2006.238.07:38:22.61#ibcon#about to read 6, iclass 16, count 0 2006.238.07:38:22.61#ibcon#read 6, iclass 16, count 0 2006.238.07:38:22.61#ibcon#end of sib2, iclass 16, count 0 2006.238.07:38:22.61#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:38:22.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:38:22.61#ibcon#[27=USB\r\n] 2006.238.07:38:22.61#ibcon#*before write, iclass 16, count 0 2006.238.07:38:22.61#ibcon#enter sib2, iclass 16, count 0 2006.238.07:38:22.61#ibcon#flushed, iclass 16, count 0 2006.238.07:38:22.61#ibcon#about to write, iclass 16, count 0 2006.238.07:38:22.61#ibcon#wrote, iclass 16, count 0 2006.238.07:38:22.61#ibcon#about to read 3, iclass 16, count 0 2006.238.07:38:22.64#ibcon#read 3, iclass 16, count 0 2006.238.07:38:22.64#ibcon#about to read 4, iclass 16, count 0 2006.238.07:38:22.64#ibcon#read 4, iclass 16, count 0 2006.238.07:38:22.64#ibcon#about to read 5, iclass 16, count 0 2006.238.07:38:22.64#ibcon#read 5, iclass 16, count 0 2006.238.07:38:22.64#ibcon#about to read 6, iclass 16, count 0 2006.238.07:38:22.64#ibcon#read 6, iclass 16, count 0 2006.238.07:38:22.64#ibcon#end of sib2, iclass 16, count 0 2006.238.07:38:22.64#ibcon#*after write, iclass 16, count 0 2006.238.07:38:22.64#ibcon#*before return 0, iclass 16, count 0 2006.238.07:38:22.64#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:38:22.64#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:38:22.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:38:22.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:38:22.64$vc4f8/vabw=wide 2006.238.07:38:22.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.07:38:22.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.07:38:22.64#ibcon#ireg 8 cls_cnt 0 2006.238.07:38:22.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:38:22.64#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:38:22.64#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:38:22.64#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:38:22.64#ibcon#first serial, iclass 18, count 0 2006.238.07:38:22.64#ibcon#enter sib2, iclass 18, count 0 2006.238.07:38:22.64#ibcon#flushed, iclass 18, count 0 2006.238.07:38:22.64#ibcon#about to write, iclass 18, count 0 2006.238.07:38:22.64#ibcon#wrote, iclass 18, count 0 2006.238.07:38:22.64#ibcon#about to read 3, iclass 18, count 0 2006.238.07:38:22.66#ibcon#read 3, iclass 18, count 0 2006.238.07:38:22.66#ibcon#about to read 4, iclass 18, count 0 2006.238.07:38:22.66#ibcon#read 4, iclass 18, count 0 2006.238.07:38:22.66#ibcon#about to read 5, iclass 18, count 0 2006.238.07:38:22.66#ibcon#read 5, iclass 18, count 0 2006.238.07:38:22.66#ibcon#about to read 6, iclass 18, count 0 2006.238.07:38:22.66#ibcon#read 6, iclass 18, count 0 2006.238.07:38:22.66#ibcon#end of sib2, iclass 18, count 0 2006.238.07:38:22.66#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:38:22.66#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:38:22.66#ibcon#[25=BW32\r\n] 2006.238.07:38:22.66#ibcon#*before write, iclass 18, count 0 2006.238.07:38:22.66#ibcon#enter sib2, iclass 18, count 0 2006.238.07:38:22.66#ibcon#flushed, iclass 18, count 0 2006.238.07:38:22.66#ibcon#about to write, iclass 18, count 0 2006.238.07:38:22.66#ibcon#wrote, iclass 18, count 0 2006.238.07:38:22.66#ibcon#about to read 3, iclass 18, count 0 2006.238.07:38:22.69#ibcon#read 3, iclass 18, count 0 2006.238.07:38:22.69#ibcon#about to read 4, iclass 18, count 0 2006.238.07:38:22.69#ibcon#read 4, iclass 18, count 0 2006.238.07:38:22.69#ibcon#about to read 5, iclass 18, count 0 2006.238.07:38:22.69#ibcon#read 5, iclass 18, count 0 2006.238.07:38:22.69#ibcon#about to read 6, iclass 18, count 0 2006.238.07:38:22.69#ibcon#read 6, iclass 18, count 0 2006.238.07:38:22.69#ibcon#end of sib2, iclass 18, count 0 2006.238.07:38:22.69#ibcon#*after write, iclass 18, count 0 2006.238.07:38:22.69#ibcon#*before return 0, iclass 18, count 0 2006.238.07:38:22.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:38:22.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:38:22.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:38:22.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:38:22.69$vc4f8/vbbw=wide 2006.238.07:38:22.69#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.07:38:22.69#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.07:38:22.69#ibcon#ireg 8 cls_cnt 0 2006.238.07:38:22.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:38:22.76#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:38:22.76#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:38:22.76#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:38:22.76#ibcon#first serial, iclass 20, count 0 2006.238.07:38:22.76#ibcon#enter sib2, iclass 20, count 0 2006.238.07:38:22.76#ibcon#flushed, iclass 20, count 0 2006.238.07:38:22.76#ibcon#about to write, iclass 20, count 0 2006.238.07:38:22.76#ibcon#wrote, iclass 20, count 0 2006.238.07:38:22.76#ibcon#about to read 3, iclass 20, count 0 2006.238.07:38:22.78#ibcon#read 3, iclass 20, count 0 2006.238.07:38:22.78#ibcon#about to read 4, iclass 20, count 0 2006.238.07:38:22.78#ibcon#read 4, iclass 20, count 0 2006.238.07:38:22.78#ibcon#about to read 5, iclass 20, count 0 2006.238.07:38:22.78#ibcon#read 5, iclass 20, count 0 2006.238.07:38:22.78#ibcon#about to read 6, iclass 20, count 0 2006.238.07:38:22.78#ibcon#read 6, iclass 20, count 0 2006.238.07:38:22.78#ibcon#end of sib2, iclass 20, count 0 2006.238.07:38:22.78#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:38:22.78#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:38:22.78#ibcon#[27=BW32\r\n] 2006.238.07:38:22.78#ibcon#*before write, iclass 20, count 0 2006.238.07:38:22.78#ibcon#enter sib2, iclass 20, count 0 2006.238.07:38:22.78#ibcon#flushed, iclass 20, count 0 2006.238.07:38:22.78#ibcon#about to write, iclass 20, count 0 2006.238.07:38:22.78#ibcon#wrote, iclass 20, count 0 2006.238.07:38:22.78#ibcon#about to read 3, iclass 20, count 0 2006.238.07:38:22.81#ibcon#read 3, iclass 20, count 0 2006.238.07:38:22.81#ibcon#about to read 4, iclass 20, count 0 2006.238.07:38:22.81#ibcon#read 4, iclass 20, count 0 2006.238.07:38:22.81#ibcon#about to read 5, iclass 20, count 0 2006.238.07:38:22.81#ibcon#read 5, iclass 20, count 0 2006.238.07:38:22.81#ibcon#about to read 6, iclass 20, count 0 2006.238.07:38:22.81#ibcon#read 6, iclass 20, count 0 2006.238.07:38:22.81#ibcon#end of sib2, iclass 20, count 0 2006.238.07:38:22.81#ibcon#*after write, iclass 20, count 0 2006.238.07:38:22.81#ibcon#*before return 0, iclass 20, count 0 2006.238.07:38:22.81#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:38:22.81#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:38:22.81#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:38:22.81#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:38:22.81$4f8m12a/ifd4f 2006.238.07:38:22.81$ifd4f/lo= 2006.238.07:38:22.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:38:22.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:38:22.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:38:22.81$ifd4f/patch= 2006.238.07:38:22.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:38:22.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:38:22.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:38:22.81$4f8m12a/"form=m,16.000,1:2 2006.238.07:38:22.81$4f8m12a/"tpicd 2006.238.07:38:22.81$4f8m12a/echo=off 2006.238.07:38:22.81$4f8m12a/xlog=off 2006.238.07:38:22.81:!2006.238.07:38:50 2006.238.07:38:34.14#trakl#Source acquired 2006.238.07:38:35.14#flagr#flagr/antenna,acquired 2006.238.07:38:50.00:preob 2006.238.07:38:51.14/onsource/TRACKING 2006.238.07:38:51.14:!2006.238.07:39:00 2006.238.07:39:00.00:data_valid=on 2006.238.07:39:00.00:midob 2006.238.07:39:00.14/onsource/TRACKING 2006.238.07:39:00.14/wx/25.32,1012.2,88 2006.238.07:39:00.21/cable/+6.4189E-03 2006.238.07:39:01.30/va/01,08,usb,yes,31,33 2006.238.07:39:01.30/va/02,07,usb,yes,31,33 2006.238.07:39:01.30/va/03,07,usb,yes,29,29 2006.238.07:39:01.30/va/04,07,usb,yes,32,35 2006.238.07:39:01.30/va/05,08,usb,yes,30,31 2006.238.07:39:01.30/va/06,07,usb,yes,32,32 2006.238.07:39:01.30/va/07,07,usb,yes,32,32 2006.238.07:39:01.30/va/08,07,usb,yes,35,34 2006.238.07:39:01.53/valo/01,532.99,yes,locked 2006.238.07:39:01.53/valo/02,572.99,yes,locked 2006.238.07:39:01.53/valo/03,672.99,yes,locked 2006.238.07:39:01.53/valo/04,832.99,yes,locked 2006.238.07:39:01.53/valo/05,652.99,yes,locked 2006.238.07:39:01.53/valo/06,772.99,yes,locked 2006.238.07:39:01.53/valo/07,832.99,yes,locked 2006.238.07:39:01.53/valo/08,852.99,yes,locked 2006.238.07:39:02.62/vb/01,04,usb,yes,30,29 2006.238.07:39:02.62/vb/02,04,usb,yes,32,33 2006.238.07:39:02.62/vb/03,04,usb,yes,28,32 2006.238.07:39:02.62/vb/04,04,usb,yes,29,29 2006.238.07:39:02.62/vb/05,04,usb,yes,27,31 2006.238.07:39:02.62/vb/06,04,usb,yes,28,31 2006.238.07:39:02.62/vb/07,04,usb,yes,31,31 2006.238.07:39:02.62/vb/08,04,usb,yes,28,31 2006.238.07:39:02.86/vblo/01,632.99,yes,locked 2006.238.07:39:02.86/vblo/02,640.99,yes,locked 2006.238.07:39:02.86/vblo/03,656.99,yes,locked 2006.238.07:39:02.86/vblo/04,712.99,yes,locked 2006.238.07:39:02.86/vblo/05,744.99,yes,locked 2006.238.07:39:02.86/vblo/06,752.99,yes,locked 2006.238.07:39:02.86/vblo/07,734.99,yes,locked 2006.238.07:39:02.86/vblo/08,744.99,yes,locked 2006.238.07:39:03.01/vabw/8 2006.238.07:39:03.16/vbbw/8 2006.238.07:39:03.25/xfe/off,on,13.2 2006.238.07:39:03.64/ifatt/23,28,28,28 2006.238.07:39:04.08/fmout-gps/S +4.37E-07 2006.238.07:39:04.12:!2006.238.07:40:00 2006.238.07:40:00.00:data_valid=off 2006.238.07:40:00.00:postob 2006.238.07:40:00.18/cable/+6.4175E-03 2006.238.07:40:00.18/wx/25.31,1012.2,87 2006.238.07:40:01.08/fmout-gps/S +4.37E-07 2006.238.07:40:01.08:scan_name=238-0740,k06238,60 2006.238.07:40:01.09:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.238.07:40:01.14#flagr#flagr/antenna,new-source 2006.238.07:40:02.14:checkk5 2006.238.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:40:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:40:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:40:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:40:04.01/chk_obsdata//k5ts1/T2380739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:40:04.38/chk_obsdata//k5ts2/T2380739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:40:04.76/chk_obsdata//k5ts3/T2380739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:40:05.13/chk_obsdata//k5ts4/T2380739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:40:05.82/k5log//k5ts1_log_newline 2006.238.07:40:06.51/k5log//k5ts2_log_newline 2006.238.07:40:07.21/k5log//k5ts3_log_newline 2006.238.07:40:07.90/k5log//k5ts4_log_newline 2006.238.07:40:07.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:40:07.92:4f8m12a=1 2006.238.07:40:07.92$4f8m12a/echo=on 2006.238.07:40:07.92$4f8m12a/pcalon 2006.238.07:40:07.92$pcalon/"no phase cal control is implemented here 2006.238.07:40:07.92$4f8m12a/"tpicd=stop 2006.238.07:40:07.92$4f8m12a/vc4f8 2006.238.07:40:07.92$vc4f8/valo=1,532.99 2006.238.07:40:07.92#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:40:07.92#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:40:07.92#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:07.92#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:40:07.92#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:40:07.92#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:40:07.92#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:40:07.92#ibcon#first serial, iclass 27, count 0 2006.238.07:40:07.92#ibcon#enter sib2, iclass 27, count 0 2006.238.07:40:07.92#ibcon#flushed, iclass 27, count 0 2006.238.07:40:07.92#ibcon#about to write, iclass 27, count 0 2006.238.07:40:07.92#ibcon#wrote, iclass 27, count 0 2006.238.07:40:07.92#ibcon#about to read 3, iclass 27, count 0 2006.238.07:40:07.94#ibcon#read 3, iclass 27, count 0 2006.238.07:40:07.94#ibcon#about to read 4, iclass 27, count 0 2006.238.07:40:07.94#ibcon#read 4, iclass 27, count 0 2006.238.07:40:07.94#ibcon#about to read 5, iclass 27, count 0 2006.238.07:40:07.94#ibcon#read 5, iclass 27, count 0 2006.238.07:40:07.94#ibcon#about to read 6, iclass 27, count 0 2006.238.07:40:07.94#ibcon#read 6, iclass 27, count 0 2006.238.07:40:07.94#ibcon#end of sib2, iclass 27, count 0 2006.238.07:40:07.94#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:40:07.94#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:40:07.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:40:07.94#ibcon#*before write, iclass 27, count 0 2006.238.07:40:07.94#ibcon#enter sib2, iclass 27, count 0 2006.238.07:40:07.94#ibcon#flushed, iclass 27, count 0 2006.238.07:40:07.94#ibcon#about to write, iclass 27, count 0 2006.238.07:40:07.94#ibcon#wrote, iclass 27, count 0 2006.238.07:40:07.94#ibcon#about to read 3, iclass 27, count 0 2006.238.07:40:07.99#ibcon#read 3, iclass 27, count 0 2006.238.07:40:07.99#ibcon#about to read 4, iclass 27, count 0 2006.238.07:40:07.99#ibcon#read 4, iclass 27, count 0 2006.238.07:40:07.99#ibcon#about to read 5, iclass 27, count 0 2006.238.07:40:07.99#ibcon#read 5, iclass 27, count 0 2006.238.07:40:07.99#ibcon#about to read 6, iclass 27, count 0 2006.238.07:40:07.99#ibcon#read 6, iclass 27, count 0 2006.238.07:40:07.99#ibcon#end of sib2, iclass 27, count 0 2006.238.07:40:07.99#ibcon#*after write, iclass 27, count 0 2006.238.07:40:07.99#ibcon#*before return 0, iclass 27, count 0 2006.238.07:40:07.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:40:07.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:40:07.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:40:07.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:40:07.99$vc4f8/va=1,8 2006.238.07:40:07.99#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.07:40:07.99#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.07:40:07.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:07.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:40:07.99#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:40:07.99#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:40:07.99#ibcon#enter wrdev, iclass 29, count 2 2006.238.07:40:07.99#ibcon#first serial, iclass 29, count 2 2006.238.07:40:07.99#ibcon#enter sib2, iclass 29, count 2 2006.238.07:40:07.99#ibcon#flushed, iclass 29, count 2 2006.238.07:40:07.99#ibcon#about to write, iclass 29, count 2 2006.238.07:40:07.99#ibcon#wrote, iclass 29, count 2 2006.238.07:40:07.99#ibcon#about to read 3, iclass 29, count 2 2006.238.07:40:08.01#ibcon#read 3, iclass 29, count 2 2006.238.07:40:08.01#ibcon#about to read 4, iclass 29, count 2 2006.238.07:40:08.01#ibcon#read 4, iclass 29, count 2 2006.238.07:40:08.01#ibcon#about to read 5, iclass 29, count 2 2006.238.07:40:08.01#ibcon#read 5, iclass 29, count 2 2006.238.07:40:08.01#ibcon#about to read 6, iclass 29, count 2 2006.238.07:40:08.01#ibcon#read 6, iclass 29, count 2 2006.238.07:40:08.01#ibcon#end of sib2, iclass 29, count 2 2006.238.07:40:08.01#ibcon#*mode == 0, iclass 29, count 2 2006.238.07:40:08.01#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.07:40:08.01#ibcon#[25=AT01-08\r\n] 2006.238.07:40:08.01#ibcon#*before write, iclass 29, count 2 2006.238.07:40:08.01#ibcon#enter sib2, iclass 29, count 2 2006.238.07:40:08.01#ibcon#flushed, iclass 29, count 2 2006.238.07:40:08.01#ibcon#about to write, iclass 29, count 2 2006.238.07:40:08.01#ibcon#wrote, iclass 29, count 2 2006.238.07:40:08.01#ibcon#about to read 3, iclass 29, count 2 2006.238.07:40:08.04#ibcon#read 3, iclass 29, count 2 2006.238.07:40:08.04#ibcon#about to read 4, iclass 29, count 2 2006.238.07:40:08.04#ibcon#read 4, iclass 29, count 2 2006.238.07:40:08.04#ibcon#about to read 5, iclass 29, count 2 2006.238.07:40:08.04#ibcon#read 5, iclass 29, count 2 2006.238.07:40:08.04#ibcon#about to read 6, iclass 29, count 2 2006.238.07:40:08.04#ibcon#read 6, iclass 29, count 2 2006.238.07:40:08.04#ibcon#end of sib2, iclass 29, count 2 2006.238.07:40:08.04#ibcon#*after write, iclass 29, count 2 2006.238.07:40:08.04#ibcon#*before return 0, iclass 29, count 2 2006.238.07:40:08.04#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:40:08.04#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:40:08.04#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.07:40:08.04#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:08.04#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:40:08.16#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:40:08.16#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:40:08.16#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:40:08.16#ibcon#first serial, iclass 29, count 0 2006.238.07:40:08.16#ibcon#enter sib2, iclass 29, count 0 2006.238.07:40:08.16#ibcon#flushed, iclass 29, count 0 2006.238.07:40:08.16#ibcon#about to write, iclass 29, count 0 2006.238.07:40:08.16#ibcon#wrote, iclass 29, count 0 2006.238.07:40:08.16#ibcon#about to read 3, iclass 29, count 0 2006.238.07:40:08.18#ibcon#read 3, iclass 29, count 0 2006.238.07:40:08.18#ibcon#about to read 4, iclass 29, count 0 2006.238.07:40:08.18#ibcon#read 4, iclass 29, count 0 2006.238.07:40:08.18#ibcon#about to read 5, iclass 29, count 0 2006.238.07:40:08.18#ibcon#read 5, iclass 29, count 0 2006.238.07:40:08.18#ibcon#about to read 6, iclass 29, count 0 2006.238.07:40:08.18#ibcon#read 6, iclass 29, count 0 2006.238.07:40:08.18#ibcon#end of sib2, iclass 29, count 0 2006.238.07:40:08.18#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:40:08.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:40:08.18#ibcon#[25=USB\r\n] 2006.238.07:40:08.18#ibcon#*before write, iclass 29, count 0 2006.238.07:40:08.18#ibcon#enter sib2, iclass 29, count 0 2006.238.07:40:08.18#ibcon#flushed, iclass 29, count 0 2006.238.07:40:08.18#ibcon#about to write, iclass 29, count 0 2006.238.07:40:08.18#ibcon#wrote, iclass 29, count 0 2006.238.07:40:08.18#ibcon#about to read 3, iclass 29, count 0 2006.238.07:40:08.21#ibcon#read 3, iclass 29, count 0 2006.238.07:40:08.21#ibcon#about to read 4, iclass 29, count 0 2006.238.07:40:08.21#ibcon#read 4, iclass 29, count 0 2006.238.07:40:08.21#ibcon#about to read 5, iclass 29, count 0 2006.238.07:40:08.21#ibcon#read 5, iclass 29, count 0 2006.238.07:40:08.21#ibcon#about to read 6, iclass 29, count 0 2006.238.07:40:08.21#ibcon#read 6, iclass 29, count 0 2006.238.07:40:08.21#ibcon#end of sib2, iclass 29, count 0 2006.238.07:40:08.21#ibcon#*after write, iclass 29, count 0 2006.238.07:40:08.21#ibcon#*before return 0, iclass 29, count 0 2006.238.07:40:08.21#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:40:08.21#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:40:08.21#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:40:08.21#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:40:08.21$vc4f8/valo=2,572.99 2006.238.07:40:08.21#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.07:40:08.21#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.07:40:08.21#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:08.21#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:40:08.21#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:40:08.21#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:40:08.21#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:40:08.21#ibcon#first serial, iclass 31, count 0 2006.238.07:40:08.21#ibcon#enter sib2, iclass 31, count 0 2006.238.07:40:08.21#ibcon#flushed, iclass 31, count 0 2006.238.07:40:08.21#ibcon#about to write, iclass 31, count 0 2006.238.07:40:08.21#ibcon#wrote, iclass 31, count 0 2006.238.07:40:08.21#ibcon#about to read 3, iclass 31, count 0 2006.238.07:40:08.23#ibcon#read 3, iclass 31, count 0 2006.238.07:40:08.23#ibcon#about to read 4, iclass 31, count 0 2006.238.07:40:08.23#ibcon#read 4, iclass 31, count 0 2006.238.07:40:08.23#ibcon#about to read 5, iclass 31, count 0 2006.238.07:40:08.23#ibcon#read 5, iclass 31, count 0 2006.238.07:40:08.23#ibcon#about to read 6, iclass 31, count 0 2006.238.07:40:08.23#ibcon#read 6, iclass 31, count 0 2006.238.07:40:08.23#ibcon#end of sib2, iclass 31, count 0 2006.238.07:40:08.23#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:40:08.23#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:40:08.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:40:08.23#ibcon#*before write, iclass 31, count 0 2006.238.07:40:08.23#ibcon#enter sib2, iclass 31, count 0 2006.238.07:40:08.23#ibcon#flushed, iclass 31, count 0 2006.238.07:40:08.23#ibcon#about to write, iclass 31, count 0 2006.238.07:40:08.23#ibcon#wrote, iclass 31, count 0 2006.238.07:40:08.23#ibcon#about to read 3, iclass 31, count 0 2006.238.07:40:08.27#ibcon#read 3, iclass 31, count 0 2006.238.07:40:08.27#ibcon#about to read 4, iclass 31, count 0 2006.238.07:40:08.27#ibcon#read 4, iclass 31, count 0 2006.238.07:40:08.27#ibcon#about to read 5, iclass 31, count 0 2006.238.07:40:08.27#ibcon#read 5, iclass 31, count 0 2006.238.07:40:08.27#ibcon#about to read 6, iclass 31, count 0 2006.238.07:40:08.27#ibcon#read 6, iclass 31, count 0 2006.238.07:40:08.27#ibcon#end of sib2, iclass 31, count 0 2006.238.07:40:08.27#ibcon#*after write, iclass 31, count 0 2006.238.07:40:08.27#ibcon#*before return 0, iclass 31, count 0 2006.238.07:40:08.27#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:40:08.27#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:40:08.27#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:40:08.27#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:40:08.27$vc4f8/va=2,7 2006.238.07:40:08.27#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:40:08.27#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:40:08.27#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:08.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:40:08.33#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:40:08.33#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:40:08.33#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:40:08.33#ibcon#first serial, iclass 33, count 2 2006.238.07:40:08.33#ibcon#enter sib2, iclass 33, count 2 2006.238.07:40:08.33#ibcon#flushed, iclass 33, count 2 2006.238.07:40:08.33#ibcon#about to write, iclass 33, count 2 2006.238.07:40:08.33#ibcon#wrote, iclass 33, count 2 2006.238.07:40:08.33#ibcon#about to read 3, iclass 33, count 2 2006.238.07:40:08.36#ibcon#read 3, iclass 33, count 2 2006.238.07:40:08.36#ibcon#about to read 4, iclass 33, count 2 2006.238.07:40:08.36#ibcon#read 4, iclass 33, count 2 2006.238.07:40:08.36#ibcon#about to read 5, iclass 33, count 2 2006.238.07:40:08.36#ibcon#read 5, iclass 33, count 2 2006.238.07:40:08.36#ibcon#about to read 6, iclass 33, count 2 2006.238.07:40:08.36#ibcon#read 6, iclass 33, count 2 2006.238.07:40:08.36#ibcon#end of sib2, iclass 33, count 2 2006.238.07:40:08.36#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:40:08.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:40:08.36#ibcon#[25=AT02-07\r\n] 2006.238.07:40:08.36#ibcon#*before write, iclass 33, count 2 2006.238.07:40:08.36#ibcon#enter sib2, iclass 33, count 2 2006.238.07:40:08.36#ibcon#flushed, iclass 33, count 2 2006.238.07:40:08.36#ibcon#about to write, iclass 33, count 2 2006.238.07:40:08.36#ibcon#wrote, iclass 33, count 2 2006.238.07:40:08.36#ibcon#about to read 3, iclass 33, count 2 2006.238.07:40:08.39#ibcon#read 3, iclass 33, count 2 2006.238.07:40:08.39#ibcon#about to read 4, iclass 33, count 2 2006.238.07:40:08.39#ibcon#read 4, iclass 33, count 2 2006.238.07:40:08.39#ibcon#about to read 5, iclass 33, count 2 2006.238.07:40:08.39#ibcon#read 5, iclass 33, count 2 2006.238.07:40:08.39#ibcon#about to read 6, iclass 33, count 2 2006.238.07:40:08.39#ibcon#read 6, iclass 33, count 2 2006.238.07:40:08.39#ibcon#end of sib2, iclass 33, count 2 2006.238.07:40:08.39#ibcon#*after write, iclass 33, count 2 2006.238.07:40:08.39#ibcon#*before return 0, iclass 33, count 2 2006.238.07:40:08.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:40:08.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:40:08.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:40:08.39#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:08.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:40:08.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:40:08.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:40:08.51#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:40:08.51#ibcon#first serial, iclass 33, count 0 2006.238.07:40:08.51#ibcon#enter sib2, iclass 33, count 0 2006.238.07:40:08.51#ibcon#flushed, iclass 33, count 0 2006.238.07:40:08.51#ibcon#about to write, iclass 33, count 0 2006.238.07:40:08.51#ibcon#wrote, iclass 33, count 0 2006.238.07:40:08.51#ibcon#about to read 3, iclass 33, count 0 2006.238.07:40:08.53#ibcon#read 3, iclass 33, count 0 2006.238.07:40:08.53#ibcon#about to read 4, iclass 33, count 0 2006.238.07:40:08.53#ibcon#read 4, iclass 33, count 0 2006.238.07:40:08.53#ibcon#about to read 5, iclass 33, count 0 2006.238.07:40:08.53#ibcon#read 5, iclass 33, count 0 2006.238.07:40:08.53#ibcon#about to read 6, iclass 33, count 0 2006.238.07:40:08.53#ibcon#read 6, iclass 33, count 0 2006.238.07:40:08.53#ibcon#end of sib2, iclass 33, count 0 2006.238.07:40:08.53#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:40:08.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:40:08.53#ibcon#[25=USB\r\n] 2006.238.07:40:08.53#ibcon#*before write, iclass 33, count 0 2006.238.07:40:08.53#ibcon#enter sib2, iclass 33, count 0 2006.238.07:40:08.53#ibcon#flushed, iclass 33, count 0 2006.238.07:40:08.53#ibcon#about to write, iclass 33, count 0 2006.238.07:40:08.53#ibcon#wrote, iclass 33, count 0 2006.238.07:40:08.53#ibcon#about to read 3, iclass 33, count 0 2006.238.07:40:08.56#ibcon#read 3, iclass 33, count 0 2006.238.07:40:08.56#ibcon#about to read 4, iclass 33, count 0 2006.238.07:40:08.56#ibcon#read 4, iclass 33, count 0 2006.238.07:40:08.56#ibcon#about to read 5, iclass 33, count 0 2006.238.07:40:08.56#ibcon#read 5, iclass 33, count 0 2006.238.07:40:08.56#ibcon#about to read 6, iclass 33, count 0 2006.238.07:40:08.56#ibcon#read 6, iclass 33, count 0 2006.238.07:40:08.56#ibcon#end of sib2, iclass 33, count 0 2006.238.07:40:08.56#ibcon#*after write, iclass 33, count 0 2006.238.07:40:08.56#ibcon#*before return 0, iclass 33, count 0 2006.238.07:40:08.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:40:08.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:40:08.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:40:08.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:40:08.56$vc4f8/valo=3,672.99 2006.238.07:40:08.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:40:08.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:40:08.56#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:08.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:40:08.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:40:08.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:40:08.56#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:40:08.56#ibcon#first serial, iclass 35, count 0 2006.238.07:40:08.56#ibcon#enter sib2, iclass 35, count 0 2006.238.07:40:08.56#ibcon#flushed, iclass 35, count 0 2006.238.07:40:08.56#ibcon#about to write, iclass 35, count 0 2006.238.07:40:08.56#ibcon#wrote, iclass 35, count 0 2006.238.07:40:08.56#ibcon#about to read 3, iclass 35, count 0 2006.238.07:40:08.58#ibcon#read 3, iclass 35, count 0 2006.238.07:40:08.58#ibcon#about to read 4, iclass 35, count 0 2006.238.07:40:08.58#ibcon#read 4, iclass 35, count 0 2006.238.07:40:08.58#ibcon#about to read 5, iclass 35, count 0 2006.238.07:40:08.58#ibcon#read 5, iclass 35, count 0 2006.238.07:40:08.58#ibcon#about to read 6, iclass 35, count 0 2006.238.07:40:08.58#ibcon#read 6, iclass 35, count 0 2006.238.07:40:08.58#ibcon#end of sib2, iclass 35, count 0 2006.238.07:40:08.58#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:40:08.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:40:08.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:40:08.58#ibcon#*before write, iclass 35, count 0 2006.238.07:40:08.58#ibcon#enter sib2, iclass 35, count 0 2006.238.07:40:08.58#ibcon#flushed, iclass 35, count 0 2006.238.07:40:08.58#ibcon#about to write, iclass 35, count 0 2006.238.07:40:08.58#ibcon#wrote, iclass 35, count 0 2006.238.07:40:08.58#ibcon#about to read 3, iclass 35, count 0 2006.238.07:40:08.62#ibcon#read 3, iclass 35, count 0 2006.238.07:40:08.62#ibcon#about to read 4, iclass 35, count 0 2006.238.07:40:08.62#ibcon#read 4, iclass 35, count 0 2006.238.07:40:08.62#ibcon#about to read 5, iclass 35, count 0 2006.238.07:40:08.62#ibcon#read 5, iclass 35, count 0 2006.238.07:40:08.62#ibcon#about to read 6, iclass 35, count 0 2006.238.07:40:08.62#ibcon#read 6, iclass 35, count 0 2006.238.07:40:08.62#ibcon#end of sib2, iclass 35, count 0 2006.238.07:40:08.62#ibcon#*after write, iclass 35, count 0 2006.238.07:40:08.62#ibcon#*before return 0, iclass 35, count 0 2006.238.07:40:08.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:40:08.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:40:08.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:40:08.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:40:08.62$vc4f8/va=3,7 2006.238.07:40:08.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.07:40:08.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.07:40:08.62#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:08.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:40:08.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:40:08.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:40:08.68#ibcon#enter wrdev, iclass 37, count 2 2006.238.07:40:08.68#ibcon#first serial, iclass 37, count 2 2006.238.07:40:08.68#ibcon#enter sib2, iclass 37, count 2 2006.238.07:40:08.68#ibcon#flushed, iclass 37, count 2 2006.238.07:40:08.68#ibcon#about to write, iclass 37, count 2 2006.238.07:40:08.68#ibcon#wrote, iclass 37, count 2 2006.238.07:40:08.68#ibcon#about to read 3, iclass 37, count 2 2006.238.07:40:08.70#ibcon#read 3, iclass 37, count 2 2006.238.07:40:08.70#ibcon#about to read 4, iclass 37, count 2 2006.238.07:40:08.70#ibcon#read 4, iclass 37, count 2 2006.238.07:40:08.70#ibcon#about to read 5, iclass 37, count 2 2006.238.07:40:08.70#ibcon#read 5, iclass 37, count 2 2006.238.07:40:08.70#ibcon#about to read 6, iclass 37, count 2 2006.238.07:40:08.70#ibcon#read 6, iclass 37, count 2 2006.238.07:40:08.70#ibcon#end of sib2, iclass 37, count 2 2006.238.07:40:08.70#ibcon#*mode == 0, iclass 37, count 2 2006.238.07:40:08.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.07:40:08.70#ibcon#[25=AT03-07\r\n] 2006.238.07:40:08.70#ibcon#*before write, iclass 37, count 2 2006.238.07:40:08.70#ibcon#enter sib2, iclass 37, count 2 2006.238.07:40:08.70#ibcon#flushed, iclass 37, count 2 2006.238.07:40:08.70#ibcon#about to write, iclass 37, count 2 2006.238.07:40:08.70#ibcon#wrote, iclass 37, count 2 2006.238.07:40:08.70#ibcon#about to read 3, iclass 37, count 2 2006.238.07:40:08.73#ibcon#read 3, iclass 37, count 2 2006.238.07:40:08.73#ibcon#about to read 4, iclass 37, count 2 2006.238.07:40:08.73#ibcon#read 4, iclass 37, count 2 2006.238.07:40:08.73#ibcon#about to read 5, iclass 37, count 2 2006.238.07:40:08.73#ibcon#read 5, iclass 37, count 2 2006.238.07:40:08.73#ibcon#about to read 6, iclass 37, count 2 2006.238.07:40:08.73#ibcon#read 6, iclass 37, count 2 2006.238.07:40:08.73#ibcon#end of sib2, iclass 37, count 2 2006.238.07:40:08.73#ibcon#*after write, iclass 37, count 2 2006.238.07:40:08.73#ibcon#*before return 0, iclass 37, count 2 2006.238.07:40:08.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:40:08.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:40:08.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.07:40:08.73#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:08.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:40:08.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:40:08.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:40:08.85#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:40:08.85#ibcon#first serial, iclass 37, count 0 2006.238.07:40:08.85#ibcon#enter sib2, iclass 37, count 0 2006.238.07:40:08.85#ibcon#flushed, iclass 37, count 0 2006.238.07:40:08.85#ibcon#about to write, iclass 37, count 0 2006.238.07:40:08.85#ibcon#wrote, iclass 37, count 0 2006.238.07:40:08.85#ibcon#about to read 3, iclass 37, count 0 2006.238.07:40:08.87#ibcon#read 3, iclass 37, count 0 2006.238.07:40:08.87#ibcon#about to read 4, iclass 37, count 0 2006.238.07:40:08.87#ibcon#read 4, iclass 37, count 0 2006.238.07:40:08.87#ibcon#about to read 5, iclass 37, count 0 2006.238.07:40:08.87#ibcon#read 5, iclass 37, count 0 2006.238.07:40:08.87#ibcon#about to read 6, iclass 37, count 0 2006.238.07:40:08.87#ibcon#read 6, iclass 37, count 0 2006.238.07:40:08.87#ibcon#end of sib2, iclass 37, count 0 2006.238.07:40:08.87#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:40:08.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:40:08.87#ibcon#[25=USB\r\n] 2006.238.07:40:08.87#ibcon#*before write, iclass 37, count 0 2006.238.07:40:08.87#ibcon#enter sib2, iclass 37, count 0 2006.238.07:40:08.87#ibcon#flushed, iclass 37, count 0 2006.238.07:40:08.87#ibcon#about to write, iclass 37, count 0 2006.238.07:40:08.87#ibcon#wrote, iclass 37, count 0 2006.238.07:40:08.87#ibcon#about to read 3, iclass 37, count 0 2006.238.07:40:08.90#ibcon#read 3, iclass 37, count 0 2006.238.07:40:08.90#ibcon#about to read 4, iclass 37, count 0 2006.238.07:40:08.90#ibcon#read 4, iclass 37, count 0 2006.238.07:40:08.90#ibcon#about to read 5, iclass 37, count 0 2006.238.07:40:08.90#ibcon#read 5, iclass 37, count 0 2006.238.07:40:08.90#ibcon#about to read 6, iclass 37, count 0 2006.238.07:40:08.90#ibcon#read 6, iclass 37, count 0 2006.238.07:40:08.90#ibcon#end of sib2, iclass 37, count 0 2006.238.07:40:08.90#ibcon#*after write, iclass 37, count 0 2006.238.07:40:08.90#ibcon#*before return 0, iclass 37, count 0 2006.238.07:40:08.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:40:08.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:40:08.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:40:08.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:40:08.90$vc4f8/valo=4,832.99 2006.238.07:40:08.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.07:40:08.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.07:40:08.90#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:08.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:40:08.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:40:08.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:40:08.90#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:40:08.90#ibcon#first serial, iclass 39, count 0 2006.238.07:40:08.90#ibcon#enter sib2, iclass 39, count 0 2006.238.07:40:08.90#ibcon#flushed, iclass 39, count 0 2006.238.07:40:08.90#ibcon#about to write, iclass 39, count 0 2006.238.07:40:08.90#ibcon#wrote, iclass 39, count 0 2006.238.07:40:08.90#ibcon#about to read 3, iclass 39, count 0 2006.238.07:40:08.92#ibcon#read 3, iclass 39, count 0 2006.238.07:40:08.92#ibcon#about to read 4, iclass 39, count 0 2006.238.07:40:08.92#ibcon#read 4, iclass 39, count 0 2006.238.07:40:08.92#ibcon#about to read 5, iclass 39, count 0 2006.238.07:40:08.92#ibcon#read 5, iclass 39, count 0 2006.238.07:40:08.92#ibcon#about to read 6, iclass 39, count 0 2006.238.07:40:08.92#ibcon#read 6, iclass 39, count 0 2006.238.07:40:08.92#ibcon#end of sib2, iclass 39, count 0 2006.238.07:40:08.92#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:40:08.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:40:08.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:40:08.92#ibcon#*before write, iclass 39, count 0 2006.238.07:40:08.92#ibcon#enter sib2, iclass 39, count 0 2006.238.07:40:08.92#ibcon#flushed, iclass 39, count 0 2006.238.07:40:08.92#ibcon#about to write, iclass 39, count 0 2006.238.07:40:08.92#ibcon#wrote, iclass 39, count 0 2006.238.07:40:08.92#ibcon#about to read 3, iclass 39, count 0 2006.238.07:40:08.96#ibcon#read 3, iclass 39, count 0 2006.238.07:40:08.96#ibcon#about to read 4, iclass 39, count 0 2006.238.07:40:08.96#ibcon#read 4, iclass 39, count 0 2006.238.07:40:08.96#ibcon#about to read 5, iclass 39, count 0 2006.238.07:40:08.96#ibcon#read 5, iclass 39, count 0 2006.238.07:40:08.96#ibcon#about to read 6, iclass 39, count 0 2006.238.07:40:08.96#ibcon#read 6, iclass 39, count 0 2006.238.07:40:08.96#ibcon#end of sib2, iclass 39, count 0 2006.238.07:40:08.96#ibcon#*after write, iclass 39, count 0 2006.238.07:40:08.96#ibcon#*before return 0, iclass 39, count 0 2006.238.07:40:08.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:40:08.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:40:08.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:40:08.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:40:08.96$vc4f8/va=4,7 2006.238.07:40:08.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.07:40:08.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.07:40:08.96#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:08.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:40:09.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:40:09.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:40:09.02#ibcon#enter wrdev, iclass 3, count 2 2006.238.07:40:09.02#ibcon#first serial, iclass 3, count 2 2006.238.07:40:09.02#ibcon#enter sib2, iclass 3, count 2 2006.238.07:40:09.02#ibcon#flushed, iclass 3, count 2 2006.238.07:40:09.02#ibcon#about to write, iclass 3, count 2 2006.238.07:40:09.02#ibcon#wrote, iclass 3, count 2 2006.238.07:40:09.02#ibcon#about to read 3, iclass 3, count 2 2006.238.07:40:09.04#ibcon#read 3, iclass 3, count 2 2006.238.07:40:09.04#ibcon#about to read 4, iclass 3, count 2 2006.238.07:40:09.04#ibcon#read 4, iclass 3, count 2 2006.238.07:40:09.04#ibcon#about to read 5, iclass 3, count 2 2006.238.07:40:09.04#ibcon#read 5, iclass 3, count 2 2006.238.07:40:09.04#ibcon#about to read 6, iclass 3, count 2 2006.238.07:40:09.04#ibcon#read 6, iclass 3, count 2 2006.238.07:40:09.04#ibcon#end of sib2, iclass 3, count 2 2006.238.07:40:09.04#ibcon#*mode == 0, iclass 3, count 2 2006.238.07:40:09.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.07:40:09.04#ibcon#[25=AT04-07\r\n] 2006.238.07:40:09.04#ibcon#*before write, iclass 3, count 2 2006.238.07:40:09.04#ibcon#enter sib2, iclass 3, count 2 2006.238.07:40:09.04#ibcon#flushed, iclass 3, count 2 2006.238.07:40:09.04#ibcon#about to write, iclass 3, count 2 2006.238.07:40:09.04#ibcon#wrote, iclass 3, count 2 2006.238.07:40:09.04#ibcon#about to read 3, iclass 3, count 2 2006.238.07:40:09.07#ibcon#read 3, iclass 3, count 2 2006.238.07:40:09.07#ibcon#about to read 4, iclass 3, count 2 2006.238.07:40:09.07#ibcon#read 4, iclass 3, count 2 2006.238.07:40:09.07#ibcon#about to read 5, iclass 3, count 2 2006.238.07:40:09.07#ibcon#read 5, iclass 3, count 2 2006.238.07:40:09.07#ibcon#about to read 6, iclass 3, count 2 2006.238.07:40:09.07#ibcon#read 6, iclass 3, count 2 2006.238.07:40:09.07#ibcon#end of sib2, iclass 3, count 2 2006.238.07:40:09.07#ibcon#*after write, iclass 3, count 2 2006.238.07:40:09.07#ibcon#*before return 0, iclass 3, count 2 2006.238.07:40:09.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:40:09.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:40:09.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.07:40:09.07#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:09.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:40:09.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:40:09.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:40:09.19#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:40:09.19#ibcon#first serial, iclass 3, count 0 2006.238.07:40:09.19#ibcon#enter sib2, iclass 3, count 0 2006.238.07:40:09.19#ibcon#flushed, iclass 3, count 0 2006.238.07:40:09.19#ibcon#about to write, iclass 3, count 0 2006.238.07:40:09.19#ibcon#wrote, iclass 3, count 0 2006.238.07:40:09.19#ibcon#about to read 3, iclass 3, count 0 2006.238.07:40:09.21#ibcon#read 3, iclass 3, count 0 2006.238.07:40:09.21#ibcon#about to read 4, iclass 3, count 0 2006.238.07:40:09.21#ibcon#read 4, iclass 3, count 0 2006.238.07:40:09.21#ibcon#about to read 5, iclass 3, count 0 2006.238.07:40:09.21#ibcon#read 5, iclass 3, count 0 2006.238.07:40:09.21#ibcon#about to read 6, iclass 3, count 0 2006.238.07:40:09.21#ibcon#read 6, iclass 3, count 0 2006.238.07:40:09.21#ibcon#end of sib2, iclass 3, count 0 2006.238.07:40:09.21#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:40:09.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:40:09.21#ibcon#[25=USB\r\n] 2006.238.07:40:09.21#ibcon#*before write, iclass 3, count 0 2006.238.07:40:09.21#ibcon#enter sib2, iclass 3, count 0 2006.238.07:40:09.21#ibcon#flushed, iclass 3, count 0 2006.238.07:40:09.21#ibcon#about to write, iclass 3, count 0 2006.238.07:40:09.21#ibcon#wrote, iclass 3, count 0 2006.238.07:40:09.21#ibcon#about to read 3, iclass 3, count 0 2006.238.07:40:09.24#ibcon#read 3, iclass 3, count 0 2006.238.07:40:09.24#ibcon#about to read 4, iclass 3, count 0 2006.238.07:40:09.24#ibcon#read 4, iclass 3, count 0 2006.238.07:40:09.24#ibcon#about to read 5, iclass 3, count 0 2006.238.07:40:09.24#ibcon#read 5, iclass 3, count 0 2006.238.07:40:09.24#ibcon#about to read 6, iclass 3, count 0 2006.238.07:40:09.24#ibcon#read 6, iclass 3, count 0 2006.238.07:40:09.24#ibcon#end of sib2, iclass 3, count 0 2006.238.07:40:09.24#ibcon#*after write, iclass 3, count 0 2006.238.07:40:09.24#ibcon#*before return 0, iclass 3, count 0 2006.238.07:40:09.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:40:09.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:40:09.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:40:09.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:40:09.24$vc4f8/valo=5,652.99 2006.238.07:40:09.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.07:40:09.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.07:40:09.24#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:09.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:40:09.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:40:09.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:40:09.24#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:40:09.24#ibcon#first serial, iclass 5, count 0 2006.238.07:40:09.24#ibcon#enter sib2, iclass 5, count 0 2006.238.07:40:09.24#ibcon#flushed, iclass 5, count 0 2006.238.07:40:09.24#ibcon#about to write, iclass 5, count 0 2006.238.07:40:09.24#ibcon#wrote, iclass 5, count 0 2006.238.07:40:09.24#ibcon#about to read 3, iclass 5, count 0 2006.238.07:40:09.26#ibcon#read 3, iclass 5, count 0 2006.238.07:40:09.26#ibcon#about to read 4, iclass 5, count 0 2006.238.07:40:09.26#ibcon#read 4, iclass 5, count 0 2006.238.07:40:09.26#ibcon#about to read 5, iclass 5, count 0 2006.238.07:40:09.26#ibcon#read 5, iclass 5, count 0 2006.238.07:40:09.26#ibcon#about to read 6, iclass 5, count 0 2006.238.07:40:09.26#ibcon#read 6, iclass 5, count 0 2006.238.07:40:09.26#ibcon#end of sib2, iclass 5, count 0 2006.238.07:40:09.26#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:40:09.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:40:09.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:40:09.26#ibcon#*before write, iclass 5, count 0 2006.238.07:40:09.26#ibcon#enter sib2, iclass 5, count 0 2006.238.07:40:09.26#ibcon#flushed, iclass 5, count 0 2006.238.07:40:09.26#ibcon#about to write, iclass 5, count 0 2006.238.07:40:09.26#ibcon#wrote, iclass 5, count 0 2006.238.07:40:09.26#ibcon#about to read 3, iclass 5, count 0 2006.238.07:40:09.30#ibcon#read 3, iclass 5, count 0 2006.238.07:40:09.30#ibcon#about to read 4, iclass 5, count 0 2006.238.07:40:09.30#ibcon#read 4, iclass 5, count 0 2006.238.07:40:09.30#ibcon#about to read 5, iclass 5, count 0 2006.238.07:40:09.30#ibcon#read 5, iclass 5, count 0 2006.238.07:40:09.30#ibcon#about to read 6, iclass 5, count 0 2006.238.07:40:09.30#ibcon#read 6, iclass 5, count 0 2006.238.07:40:09.30#ibcon#end of sib2, iclass 5, count 0 2006.238.07:40:09.30#ibcon#*after write, iclass 5, count 0 2006.238.07:40:09.30#ibcon#*before return 0, iclass 5, count 0 2006.238.07:40:09.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:40:09.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:40:09.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:40:09.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:40:09.30$vc4f8/va=5,8 2006.238.07:40:09.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.07:40:09.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.07:40:09.30#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:09.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:40:09.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:40:09.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:40:09.36#ibcon#enter wrdev, iclass 7, count 2 2006.238.07:40:09.36#ibcon#first serial, iclass 7, count 2 2006.238.07:40:09.36#ibcon#enter sib2, iclass 7, count 2 2006.238.07:40:09.36#ibcon#flushed, iclass 7, count 2 2006.238.07:40:09.36#ibcon#about to write, iclass 7, count 2 2006.238.07:40:09.36#ibcon#wrote, iclass 7, count 2 2006.238.07:40:09.36#ibcon#about to read 3, iclass 7, count 2 2006.238.07:40:09.38#ibcon#read 3, iclass 7, count 2 2006.238.07:40:09.38#ibcon#about to read 4, iclass 7, count 2 2006.238.07:40:09.38#ibcon#read 4, iclass 7, count 2 2006.238.07:40:09.38#ibcon#about to read 5, iclass 7, count 2 2006.238.07:40:09.38#ibcon#read 5, iclass 7, count 2 2006.238.07:40:09.38#ibcon#about to read 6, iclass 7, count 2 2006.238.07:40:09.38#ibcon#read 6, iclass 7, count 2 2006.238.07:40:09.38#ibcon#end of sib2, iclass 7, count 2 2006.238.07:40:09.38#ibcon#*mode == 0, iclass 7, count 2 2006.238.07:40:09.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.07:40:09.38#ibcon#[25=AT05-08\r\n] 2006.238.07:40:09.38#ibcon#*before write, iclass 7, count 2 2006.238.07:40:09.38#ibcon#enter sib2, iclass 7, count 2 2006.238.07:40:09.38#ibcon#flushed, iclass 7, count 2 2006.238.07:40:09.38#ibcon#about to write, iclass 7, count 2 2006.238.07:40:09.38#ibcon#wrote, iclass 7, count 2 2006.238.07:40:09.38#ibcon#about to read 3, iclass 7, count 2 2006.238.07:40:09.41#ibcon#read 3, iclass 7, count 2 2006.238.07:40:09.41#ibcon#about to read 4, iclass 7, count 2 2006.238.07:40:09.41#ibcon#read 4, iclass 7, count 2 2006.238.07:40:09.41#ibcon#about to read 5, iclass 7, count 2 2006.238.07:40:09.41#ibcon#read 5, iclass 7, count 2 2006.238.07:40:09.41#ibcon#about to read 6, iclass 7, count 2 2006.238.07:40:09.41#ibcon#read 6, iclass 7, count 2 2006.238.07:40:09.41#ibcon#end of sib2, iclass 7, count 2 2006.238.07:40:09.41#ibcon#*after write, iclass 7, count 2 2006.238.07:40:09.41#ibcon#*before return 0, iclass 7, count 2 2006.238.07:40:09.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:40:09.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:40:09.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.07:40:09.41#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:09.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:40:09.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:40:09.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:40:09.53#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:40:09.53#ibcon#first serial, iclass 7, count 0 2006.238.07:40:09.53#ibcon#enter sib2, iclass 7, count 0 2006.238.07:40:09.53#ibcon#flushed, iclass 7, count 0 2006.238.07:40:09.53#ibcon#about to write, iclass 7, count 0 2006.238.07:40:09.53#ibcon#wrote, iclass 7, count 0 2006.238.07:40:09.53#ibcon#about to read 3, iclass 7, count 0 2006.238.07:40:09.55#ibcon#read 3, iclass 7, count 0 2006.238.07:40:09.55#ibcon#about to read 4, iclass 7, count 0 2006.238.07:40:09.55#ibcon#read 4, iclass 7, count 0 2006.238.07:40:09.55#ibcon#about to read 5, iclass 7, count 0 2006.238.07:40:09.55#ibcon#read 5, iclass 7, count 0 2006.238.07:40:09.55#ibcon#about to read 6, iclass 7, count 0 2006.238.07:40:09.55#ibcon#read 6, iclass 7, count 0 2006.238.07:40:09.55#ibcon#end of sib2, iclass 7, count 0 2006.238.07:40:09.55#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:40:09.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:40:09.55#ibcon#[25=USB\r\n] 2006.238.07:40:09.55#ibcon#*before write, iclass 7, count 0 2006.238.07:40:09.55#ibcon#enter sib2, iclass 7, count 0 2006.238.07:40:09.55#ibcon#flushed, iclass 7, count 0 2006.238.07:40:09.55#ibcon#about to write, iclass 7, count 0 2006.238.07:40:09.55#ibcon#wrote, iclass 7, count 0 2006.238.07:40:09.55#ibcon#about to read 3, iclass 7, count 0 2006.238.07:40:09.58#ibcon#read 3, iclass 7, count 0 2006.238.07:40:09.58#ibcon#about to read 4, iclass 7, count 0 2006.238.07:40:09.58#ibcon#read 4, iclass 7, count 0 2006.238.07:40:09.58#ibcon#about to read 5, iclass 7, count 0 2006.238.07:40:09.58#ibcon#read 5, iclass 7, count 0 2006.238.07:40:09.58#ibcon#about to read 6, iclass 7, count 0 2006.238.07:40:09.58#ibcon#read 6, iclass 7, count 0 2006.238.07:40:09.58#ibcon#end of sib2, iclass 7, count 0 2006.238.07:40:09.58#ibcon#*after write, iclass 7, count 0 2006.238.07:40:09.58#ibcon#*before return 0, iclass 7, count 0 2006.238.07:40:09.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:40:09.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:40:09.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:40:09.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:40:09.58$vc4f8/valo=6,772.99 2006.238.07:40:09.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.07:40:09.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.07:40:09.58#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:09.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:40:09.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:40:09.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:40:09.58#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:40:09.58#ibcon#first serial, iclass 11, count 0 2006.238.07:40:09.58#ibcon#enter sib2, iclass 11, count 0 2006.238.07:40:09.58#ibcon#flushed, iclass 11, count 0 2006.238.07:40:09.58#ibcon#about to write, iclass 11, count 0 2006.238.07:40:09.58#ibcon#wrote, iclass 11, count 0 2006.238.07:40:09.58#ibcon#about to read 3, iclass 11, count 0 2006.238.07:40:09.60#ibcon#read 3, iclass 11, count 0 2006.238.07:40:09.60#ibcon#about to read 4, iclass 11, count 0 2006.238.07:40:09.60#ibcon#read 4, iclass 11, count 0 2006.238.07:40:09.60#ibcon#about to read 5, iclass 11, count 0 2006.238.07:40:09.60#ibcon#read 5, iclass 11, count 0 2006.238.07:40:09.60#ibcon#about to read 6, iclass 11, count 0 2006.238.07:40:09.60#ibcon#read 6, iclass 11, count 0 2006.238.07:40:09.60#ibcon#end of sib2, iclass 11, count 0 2006.238.07:40:09.60#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:40:09.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:40:09.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:40:09.60#ibcon#*before write, iclass 11, count 0 2006.238.07:40:09.60#ibcon#enter sib2, iclass 11, count 0 2006.238.07:40:09.60#ibcon#flushed, iclass 11, count 0 2006.238.07:40:09.60#ibcon#about to write, iclass 11, count 0 2006.238.07:40:09.60#ibcon#wrote, iclass 11, count 0 2006.238.07:40:09.60#ibcon#about to read 3, iclass 11, count 0 2006.238.07:40:09.64#ibcon#read 3, iclass 11, count 0 2006.238.07:40:09.64#ibcon#about to read 4, iclass 11, count 0 2006.238.07:40:09.64#ibcon#read 4, iclass 11, count 0 2006.238.07:40:09.64#ibcon#about to read 5, iclass 11, count 0 2006.238.07:40:09.64#ibcon#read 5, iclass 11, count 0 2006.238.07:40:09.64#ibcon#about to read 6, iclass 11, count 0 2006.238.07:40:09.64#ibcon#read 6, iclass 11, count 0 2006.238.07:40:09.64#ibcon#end of sib2, iclass 11, count 0 2006.238.07:40:09.64#ibcon#*after write, iclass 11, count 0 2006.238.07:40:09.64#ibcon#*before return 0, iclass 11, count 0 2006.238.07:40:09.64#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:40:09.64#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:40:09.64#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:40:09.64#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:40:09.64$vc4f8/va=6,7 2006.238.07:40:09.64#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.07:40:09.64#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.07:40:09.64#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:09.64#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:40:09.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:40:09.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:40:09.70#ibcon#enter wrdev, iclass 13, count 2 2006.238.07:40:09.70#ibcon#first serial, iclass 13, count 2 2006.238.07:40:09.70#ibcon#enter sib2, iclass 13, count 2 2006.238.07:40:09.70#ibcon#flushed, iclass 13, count 2 2006.238.07:40:09.70#ibcon#about to write, iclass 13, count 2 2006.238.07:40:09.70#ibcon#wrote, iclass 13, count 2 2006.238.07:40:09.70#ibcon#about to read 3, iclass 13, count 2 2006.238.07:40:09.72#ibcon#read 3, iclass 13, count 2 2006.238.07:40:09.72#ibcon#about to read 4, iclass 13, count 2 2006.238.07:40:09.72#ibcon#read 4, iclass 13, count 2 2006.238.07:40:09.72#ibcon#about to read 5, iclass 13, count 2 2006.238.07:40:09.72#ibcon#read 5, iclass 13, count 2 2006.238.07:40:09.72#ibcon#about to read 6, iclass 13, count 2 2006.238.07:40:09.72#ibcon#read 6, iclass 13, count 2 2006.238.07:40:09.72#ibcon#end of sib2, iclass 13, count 2 2006.238.07:40:09.72#ibcon#*mode == 0, iclass 13, count 2 2006.238.07:40:09.72#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.07:40:09.72#ibcon#[25=AT06-07\r\n] 2006.238.07:40:09.72#ibcon#*before write, iclass 13, count 2 2006.238.07:40:09.72#ibcon#enter sib2, iclass 13, count 2 2006.238.07:40:09.72#ibcon#flushed, iclass 13, count 2 2006.238.07:40:09.72#ibcon#about to write, iclass 13, count 2 2006.238.07:40:09.72#ibcon#wrote, iclass 13, count 2 2006.238.07:40:09.72#ibcon#about to read 3, iclass 13, count 2 2006.238.07:40:09.75#ibcon#read 3, iclass 13, count 2 2006.238.07:40:09.75#ibcon#about to read 4, iclass 13, count 2 2006.238.07:40:09.75#ibcon#read 4, iclass 13, count 2 2006.238.07:40:09.75#ibcon#about to read 5, iclass 13, count 2 2006.238.07:40:09.75#ibcon#read 5, iclass 13, count 2 2006.238.07:40:09.75#ibcon#about to read 6, iclass 13, count 2 2006.238.07:40:09.75#ibcon#read 6, iclass 13, count 2 2006.238.07:40:09.75#ibcon#end of sib2, iclass 13, count 2 2006.238.07:40:09.75#ibcon#*after write, iclass 13, count 2 2006.238.07:40:09.75#ibcon#*before return 0, iclass 13, count 2 2006.238.07:40:09.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:40:09.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:40:09.75#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.07:40:09.75#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:09.75#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:40:09.87#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:40:09.87#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:40:09.87#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:40:09.87#ibcon#first serial, iclass 13, count 0 2006.238.07:40:09.87#ibcon#enter sib2, iclass 13, count 0 2006.238.07:40:09.87#ibcon#flushed, iclass 13, count 0 2006.238.07:40:09.87#ibcon#about to write, iclass 13, count 0 2006.238.07:40:09.87#ibcon#wrote, iclass 13, count 0 2006.238.07:40:09.87#ibcon#about to read 3, iclass 13, count 0 2006.238.07:40:09.89#ibcon#read 3, iclass 13, count 0 2006.238.07:40:09.89#ibcon#about to read 4, iclass 13, count 0 2006.238.07:40:09.89#ibcon#read 4, iclass 13, count 0 2006.238.07:40:09.89#ibcon#about to read 5, iclass 13, count 0 2006.238.07:40:09.89#ibcon#read 5, iclass 13, count 0 2006.238.07:40:09.89#ibcon#about to read 6, iclass 13, count 0 2006.238.07:40:09.89#ibcon#read 6, iclass 13, count 0 2006.238.07:40:09.89#ibcon#end of sib2, iclass 13, count 0 2006.238.07:40:09.89#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:40:09.89#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:40:09.89#ibcon#[25=USB\r\n] 2006.238.07:40:09.89#ibcon#*before write, iclass 13, count 0 2006.238.07:40:09.89#ibcon#enter sib2, iclass 13, count 0 2006.238.07:40:09.89#ibcon#flushed, iclass 13, count 0 2006.238.07:40:09.89#ibcon#about to write, iclass 13, count 0 2006.238.07:40:09.89#ibcon#wrote, iclass 13, count 0 2006.238.07:40:09.89#ibcon#about to read 3, iclass 13, count 0 2006.238.07:40:09.92#ibcon#read 3, iclass 13, count 0 2006.238.07:40:09.92#ibcon#about to read 4, iclass 13, count 0 2006.238.07:40:09.92#ibcon#read 4, iclass 13, count 0 2006.238.07:40:09.92#ibcon#about to read 5, iclass 13, count 0 2006.238.07:40:09.92#ibcon#read 5, iclass 13, count 0 2006.238.07:40:09.92#ibcon#about to read 6, iclass 13, count 0 2006.238.07:40:09.92#ibcon#read 6, iclass 13, count 0 2006.238.07:40:09.92#ibcon#end of sib2, iclass 13, count 0 2006.238.07:40:09.92#ibcon#*after write, iclass 13, count 0 2006.238.07:40:09.92#ibcon#*before return 0, iclass 13, count 0 2006.238.07:40:09.92#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:40:09.92#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:40:09.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:40:09.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:40:09.92$vc4f8/valo=7,832.99 2006.238.07:40:09.92#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.07:40:09.92#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.07:40:09.92#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:09.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:40:09.92#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:40:09.92#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:40:09.92#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:40:09.92#ibcon#first serial, iclass 15, count 0 2006.238.07:40:09.92#ibcon#enter sib2, iclass 15, count 0 2006.238.07:40:09.92#ibcon#flushed, iclass 15, count 0 2006.238.07:40:09.92#ibcon#about to write, iclass 15, count 0 2006.238.07:40:09.92#ibcon#wrote, iclass 15, count 0 2006.238.07:40:09.92#ibcon#about to read 3, iclass 15, count 0 2006.238.07:40:09.94#ibcon#read 3, iclass 15, count 0 2006.238.07:40:09.94#ibcon#about to read 4, iclass 15, count 0 2006.238.07:40:09.94#ibcon#read 4, iclass 15, count 0 2006.238.07:40:09.94#ibcon#about to read 5, iclass 15, count 0 2006.238.07:40:09.94#ibcon#read 5, iclass 15, count 0 2006.238.07:40:09.94#ibcon#about to read 6, iclass 15, count 0 2006.238.07:40:09.94#ibcon#read 6, iclass 15, count 0 2006.238.07:40:09.94#ibcon#end of sib2, iclass 15, count 0 2006.238.07:40:09.94#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:40:09.94#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:40:09.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:40:09.94#ibcon#*before write, iclass 15, count 0 2006.238.07:40:09.94#ibcon#enter sib2, iclass 15, count 0 2006.238.07:40:09.94#ibcon#flushed, iclass 15, count 0 2006.238.07:40:09.94#ibcon#about to write, iclass 15, count 0 2006.238.07:40:09.94#ibcon#wrote, iclass 15, count 0 2006.238.07:40:09.94#ibcon#about to read 3, iclass 15, count 0 2006.238.07:40:09.98#ibcon#read 3, iclass 15, count 0 2006.238.07:40:09.98#ibcon#about to read 4, iclass 15, count 0 2006.238.07:40:09.98#ibcon#read 4, iclass 15, count 0 2006.238.07:40:09.98#ibcon#about to read 5, iclass 15, count 0 2006.238.07:40:09.98#ibcon#read 5, iclass 15, count 0 2006.238.07:40:09.98#ibcon#about to read 6, iclass 15, count 0 2006.238.07:40:09.98#ibcon#read 6, iclass 15, count 0 2006.238.07:40:09.98#ibcon#end of sib2, iclass 15, count 0 2006.238.07:40:09.98#ibcon#*after write, iclass 15, count 0 2006.238.07:40:09.98#ibcon#*before return 0, iclass 15, count 0 2006.238.07:40:09.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:40:09.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:40:09.98#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:40:09.98#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:40:09.98$vc4f8/va=7,7 2006.238.07:40:09.98#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.07:40:09.98#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.07:40:09.98#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:09.98#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:40:10.04#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:40:10.04#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:40:10.04#ibcon#enter wrdev, iclass 17, count 2 2006.238.07:40:10.04#ibcon#first serial, iclass 17, count 2 2006.238.07:40:10.04#ibcon#enter sib2, iclass 17, count 2 2006.238.07:40:10.04#ibcon#flushed, iclass 17, count 2 2006.238.07:40:10.04#ibcon#about to write, iclass 17, count 2 2006.238.07:40:10.04#ibcon#wrote, iclass 17, count 2 2006.238.07:40:10.04#ibcon#about to read 3, iclass 17, count 2 2006.238.07:40:10.06#ibcon#read 3, iclass 17, count 2 2006.238.07:40:10.06#ibcon#about to read 4, iclass 17, count 2 2006.238.07:40:10.06#ibcon#read 4, iclass 17, count 2 2006.238.07:40:10.06#ibcon#about to read 5, iclass 17, count 2 2006.238.07:40:10.06#ibcon#read 5, iclass 17, count 2 2006.238.07:40:10.06#ibcon#about to read 6, iclass 17, count 2 2006.238.07:40:10.06#ibcon#read 6, iclass 17, count 2 2006.238.07:40:10.06#ibcon#end of sib2, iclass 17, count 2 2006.238.07:40:10.06#ibcon#*mode == 0, iclass 17, count 2 2006.238.07:40:10.06#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.07:40:10.06#ibcon#[25=AT07-07\r\n] 2006.238.07:40:10.06#ibcon#*before write, iclass 17, count 2 2006.238.07:40:10.06#ibcon#enter sib2, iclass 17, count 2 2006.238.07:40:10.06#ibcon#flushed, iclass 17, count 2 2006.238.07:40:10.06#ibcon#about to write, iclass 17, count 2 2006.238.07:40:10.06#ibcon#wrote, iclass 17, count 2 2006.238.07:40:10.06#ibcon#about to read 3, iclass 17, count 2 2006.238.07:40:10.09#ibcon#read 3, iclass 17, count 2 2006.238.07:40:10.09#ibcon#about to read 4, iclass 17, count 2 2006.238.07:40:10.09#ibcon#read 4, iclass 17, count 2 2006.238.07:40:10.09#ibcon#about to read 5, iclass 17, count 2 2006.238.07:40:10.09#ibcon#read 5, iclass 17, count 2 2006.238.07:40:10.09#ibcon#about to read 6, iclass 17, count 2 2006.238.07:40:10.09#ibcon#read 6, iclass 17, count 2 2006.238.07:40:10.09#ibcon#end of sib2, iclass 17, count 2 2006.238.07:40:10.09#ibcon#*after write, iclass 17, count 2 2006.238.07:40:10.09#ibcon#*before return 0, iclass 17, count 2 2006.238.07:40:10.09#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:40:10.09#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:40:10.09#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.07:40:10.09#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:10.09#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:40:10.21#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:40:10.21#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:40:10.21#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:40:10.21#ibcon#first serial, iclass 17, count 0 2006.238.07:40:10.21#ibcon#enter sib2, iclass 17, count 0 2006.238.07:40:10.21#ibcon#flushed, iclass 17, count 0 2006.238.07:40:10.21#ibcon#about to write, iclass 17, count 0 2006.238.07:40:10.21#ibcon#wrote, iclass 17, count 0 2006.238.07:40:10.21#ibcon#about to read 3, iclass 17, count 0 2006.238.07:40:10.23#ibcon#read 3, iclass 17, count 0 2006.238.07:40:10.23#ibcon#about to read 4, iclass 17, count 0 2006.238.07:40:10.23#ibcon#read 4, iclass 17, count 0 2006.238.07:40:10.23#ibcon#about to read 5, iclass 17, count 0 2006.238.07:40:10.23#ibcon#read 5, iclass 17, count 0 2006.238.07:40:10.23#ibcon#about to read 6, iclass 17, count 0 2006.238.07:40:10.23#ibcon#read 6, iclass 17, count 0 2006.238.07:40:10.23#ibcon#end of sib2, iclass 17, count 0 2006.238.07:40:10.23#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:40:10.23#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:40:10.23#ibcon#[25=USB\r\n] 2006.238.07:40:10.23#ibcon#*before write, iclass 17, count 0 2006.238.07:40:10.23#ibcon#enter sib2, iclass 17, count 0 2006.238.07:40:10.23#ibcon#flushed, iclass 17, count 0 2006.238.07:40:10.23#ibcon#about to write, iclass 17, count 0 2006.238.07:40:10.23#ibcon#wrote, iclass 17, count 0 2006.238.07:40:10.23#ibcon#about to read 3, iclass 17, count 0 2006.238.07:40:10.26#ibcon#read 3, iclass 17, count 0 2006.238.07:40:10.26#ibcon#about to read 4, iclass 17, count 0 2006.238.07:40:10.26#ibcon#read 4, iclass 17, count 0 2006.238.07:40:10.26#ibcon#about to read 5, iclass 17, count 0 2006.238.07:40:10.26#ibcon#read 5, iclass 17, count 0 2006.238.07:40:10.26#ibcon#about to read 6, iclass 17, count 0 2006.238.07:40:10.26#ibcon#read 6, iclass 17, count 0 2006.238.07:40:10.26#ibcon#end of sib2, iclass 17, count 0 2006.238.07:40:10.26#ibcon#*after write, iclass 17, count 0 2006.238.07:40:10.26#ibcon#*before return 0, iclass 17, count 0 2006.238.07:40:10.26#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:40:10.26#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:40:10.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:40:10.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:40:10.26$vc4f8/valo=8,852.99 2006.238.07:40:10.26#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.07:40:10.26#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.07:40:10.26#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:10.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:40:10.26#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:40:10.26#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:40:10.26#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:40:10.26#ibcon#first serial, iclass 19, count 0 2006.238.07:40:10.26#ibcon#enter sib2, iclass 19, count 0 2006.238.07:40:10.26#ibcon#flushed, iclass 19, count 0 2006.238.07:40:10.26#ibcon#about to write, iclass 19, count 0 2006.238.07:40:10.26#ibcon#wrote, iclass 19, count 0 2006.238.07:40:10.26#ibcon#about to read 3, iclass 19, count 0 2006.238.07:40:10.28#ibcon#read 3, iclass 19, count 0 2006.238.07:40:10.28#ibcon#about to read 4, iclass 19, count 0 2006.238.07:40:10.28#ibcon#read 4, iclass 19, count 0 2006.238.07:40:10.28#ibcon#about to read 5, iclass 19, count 0 2006.238.07:40:10.28#ibcon#read 5, iclass 19, count 0 2006.238.07:40:10.28#ibcon#about to read 6, iclass 19, count 0 2006.238.07:40:10.28#ibcon#read 6, iclass 19, count 0 2006.238.07:40:10.28#ibcon#end of sib2, iclass 19, count 0 2006.238.07:40:10.28#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:40:10.28#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:40:10.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:40:10.28#ibcon#*before write, iclass 19, count 0 2006.238.07:40:10.28#ibcon#enter sib2, iclass 19, count 0 2006.238.07:40:10.28#ibcon#flushed, iclass 19, count 0 2006.238.07:40:10.28#ibcon#about to write, iclass 19, count 0 2006.238.07:40:10.28#ibcon#wrote, iclass 19, count 0 2006.238.07:40:10.28#ibcon#about to read 3, iclass 19, count 0 2006.238.07:40:10.32#ibcon#read 3, iclass 19, count 0 2006.238.07:40:10.32#ibcon#about to read 4, iclass 19, count 0 2006.238.07:40:10.32#ibcon#read 4, iclass 19, count 0 2006.238.07:40:10.32#ibcon#about to read 5, iclass 19, count 0 2006.238.07:40:10.32#ibcon#read 5, iclass 19, count 0 2006.238.07:40:10.32#ibcon#about to read 6, iclass 19, count 0 2006.238.07:40:10.32#ibcon#read 6, iclass 19, count 0 2006.238.07:40:10.32#ibcon#end of sib2, iclass 19, count 0 2006.238.07:40:10.32#ibcon#*after write, iclass 19, count 0 2006.238.07:40:10.32#ibcon#*before return 0, iclass 19, count 0 2006.238.07:40:10.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:40:10.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:40:10.32#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:40:10.32#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:40:10.32$vc4f8/va=8,7 2006.238.07:40:10.32#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.07:40:10.32#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.07:40:10.32#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:10.32#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:40:10.38#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:40:10.38#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:40:10.38#ibcon#enter wrdev, iclass 21, count 2 2006.238.07:40:10.38#ibcon#first serial, iclass 21, count 2 2006.238.07:40:10.38#ibcon#enter sib2, iclass 21, count 2 2006.238.07:40:10.38#ibcon#flushed, iclass 21, count 2 2006.238.07:40:10.38#ibcon#about to write, iclass 21, count 2 2006.238.07:40:10.38#ibcon#wrote, iclass 21, count 2 2006.238.07:40:10.38#ibcon#about to read 3, iclass 21, count 2 2006.238.07:40:10.40#ibcon#read 3, iclass 21, count 2 2006.238.07:40:10.40#ibcon#about to read 4, iclass 21, count 2 2006.238.07:40:10.40#ibcon#read 4, iclass 21, count 2 2006.238.07:40:10.40#ibcon#about to read 5, iclass 21, count 2 2006.238.07:40:10.40#ibcon#read 5, iclass 21, count 2 2006.238.07:40:10.40#ibcon#about to read 6, iclass 21, count 2 2006.238.07:40:10.40#ibcon#read 6, iclass 21, count 2 2006.238.07:40:10.40#ibcon#end of sib2, iclass 21, count 2 2006.238.07:40:10.40#ibcon#*mode == 0, iclass 21, count 2 2006.238.07:40:10.40#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.07:40:10.40#ibcon#[25=AT08-07\r\n] 2006.238.07:40:10.40#ibcon#*before write, iclass 21, count 2 2006.238.07:40:10.40#ibcon#enter sib2, iclass 21, count 2 2006.238.07:40:10.40#ibcon#flushed, iclass 21, count 2 2006.238.07:40:10.40#ibcon#about to write, iclass 21, count 2 2006.238.07:40:10.40#ibcon#wrote, iclass 21, count 2 2006.238.07:40:10.40#ibcon#about to read 3, iclass 21, count 2 2006.238.07:40:10.43#ibcon#read 3, iclass 21, count 2 2006.238.07:40:10.43#ibcon#about to read 4, iclass 21, count 2 2006.238.07:40:10.43#ibcon#read 4, iclass 21, count 2 2006.238.07:40:10.43#ibcon#about to read 5, iclass 21, count 2 2006.238.07:40:10.43#ibcon#read 5, iclass 21, count 2 2006.238.07:40:10.43#ibcon#about to read 6, iclass 21, count 2 2006.238.07:40:10.43#ibcon#read 6, iclass 21, count 2 2006.238.07:40:10.43#ibcon#end of sib2, iclass 21, count 2 2006.238.07:40:10.43#ibcon#*after write, iclass 21, count 2 2006.238.07:40:10.43#ibcon#*before return 0, iclass 21, count 2 2006.238.07:40:10.43#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:40:10.43#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:40:10.43#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.07:40:10.43#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:10.43#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:40:10.55#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:40:10.55#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:40:10.55#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:40:10.55#ibcon#first serial, iclass 21, count 0 2006.238.07:40:10.55#ibcon#enter sib2, iclass 21, count 0 2006.238.07:40:10.55#ibcon#flushed, iclass 21, count 0 2006.238.07:40:10.55#ibcon#about to write, iclass 21, count 0 2006.238.07:40:10.55#ibcon#wrote, iclass 21, count 0 2006.238.07:40:10.55#ibcon#about to read 3, iclass 21, count 0 2006.238.07:40:10.57#ibcon#read 3, iclass 21, count 0 2006.238.07:40:10.57#ibcon#about to read 4, iclass 21, count 0 2006.238.07:40:10.57#ibcon#read 4, iclass 21, count 0 2006.238.07:40:10.57#ibcon#about to read 5, iclass 21, count 0 2006.238.07:40:10.57#ibcon#read 5, iclass 21, count 0 2006.238.07:40:10.57#ibcon#about to read 6, iclass 21, count 0 2006.238.07:40:10.57#ibcon#read 6, iclass 21, count 0 2006.238.07:40:10.57#ibcon#end of sib2, iclass 21, count 0 2006.238.07:40:10.57#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:40:10.57#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:40:10.57#ibcon#[25=USB\r\n] 2006.238.07:40:10.57#ibcon#*before write, iclass 21, count 0 2006.238.07:40:10.57#ibcon#enter sib2, iclass 21, count 0 2006.238.07:40:10.57#ibcon#flushed, iclass 21, count 0 2006.238.07:40:10.57#ibcon#about to write, iclass 21, count 0 2006.238.07:40:10.57#ibcon#wrote, iclass 21, count 0 2006.238.07:40:10.57#ibcon#about to read 3, iclass 21, count 0 2006.238.07:40:10.60#ibcon#read 3, iclass 21, count 0 2006.238.07:40:10.60#ibcon#about to read 4, iclass 21, count 0 2006.238.07:40:10.60#ibcon#read 4, iclass 21, count 0 2006.238.07:40:10.60#ibcon#about to read 5, iclass 21, count 0 2006.238.07:40:10.60#ibcon#read 5, iclass 21, count 0 2006.238.07:40:10.60#ibcon#about to read 6, iclass 21, count 0 2006.238.07:40:10.60#ibcon#read 6, iclass 21, count 0 2006.238.07:40:10.60#ibcon#end of sib2, iclass 21, count 0 2006.238.07:40:10.60#ibcon#*after write, iclass 21, count 0 2006.238.07:40:10.60#ibcon#*before return 0, iclass 21, count 0 2006.238.07:40:10.60#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:40:10.60#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:40:10.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:40:10.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:40:10.60$vc4f8/vblo=1,632.99 2006.238.07:40:10.60#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:40:10.60#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:40:10.60#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:10.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:40:10.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:40:10.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:40:10.60#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:40:10.60#ibcon#first serial, iclass 23, count 0 2006.238.07:40:10.60#ibcon#enter sib2, iclass 23, count 0 2006.238.07:40:10.60#ibcon#flushed, iclass 23, count 0 2006.238.07:40:10.60#ibcon#about to write, iclass 23, count 0 2006.238.07:40:10.60#ibcon#wrote, iclass 23, count 0 2006.238.07:40:10.60#ibcon#about to read 3, iclass 23, count 0 2006.238.07:40:10.62#ibcon#read 3, iclass 23, count 0 2006.238.07:40:10.62#ibcon#about to read 4, iclass 23, count 0 2006.238.07:40:10.62#ibcon#read 4, iclass 23, count 0 2006.238.07:40:10.62#ibcon#about to read 5, iclass 23, count 0 2006.238.07:40:10.62#ibcon#read 5, iclass 23, count 0 2006.238.07:40:10.62#ibcon#about to read 6, iclass 23, count 0 2006.238.07:40:10.62#ibcon#read 6, iclass 23, count 0 2006.238.07:40:10.62#ibcon#end of sib2, iclass 23, count 0 2006.238.07:40:10.62#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:40:10.62#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:40:10.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:40:10.62#ibcon#*before write, iclass 23, count 0 2006.238.07:40:10.62#ibcon#enter sib2, iclass 23, count 0 2006.238.07:40:10.62#ibcon#flushed, iclass 23, count 0 2006.238.07:40:10.62#ibcon#about to write, iclass 23, count 0 2006.238.07:40:10.62#ibcon#wrote, iclass 23, count 0 2006.238.07:40:10.62#ibcon#about to read 3, iclass 23, count 0 2006.238.07:40:10.66#ibcon#read 3, iclass 23, count 0 2006.238.07:40:10.66#ibcon#about to read 4, iclass 23, count 0 2006.238.07:40:10.66#ibcon#read 4, iclass 23, count 0 2006.238.07:40:10.66#ibcon#about to read 5, iclass 23, count 0 2006.238.07:40:10.66#ibcon#read 5, iclass 23, count 0 2006.238.07:40:10.66#ibcon#about to read 6, iclass 23, count 0 2006.238.07:40:10.66#ibcon#read 6, iclass 23, count 0 2006.238.07:40:10.66#ibcon#end of sib2, iclass 23, count 0 2006.238.07:40:10.66#ibcon#*after write, iclass 23, count 0 2006.238.07:40:10.66#ibcon#*before return 0, iclass 23, count 0 2006.238.07:40:10.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:40:10.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:40:10.66#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:40:10.66#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:40:10.66$vc4f8/vb=1,4 2006.238.07:40:10.66#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.07:40:10.66#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.07:40:10.66#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:10.66#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:40:10.66#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:40:10.66#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:40:10.66#ibcon#enter wrdev, iclass 25, count 2 2006.238.07:40:10.66#ibcon#first serial, iclass 25, count 2 2006.238.07:40:10.66#ibcon#enter sib2, iclass 25, count 2 2006.238.07:40:10.66#ibcon#flushed, iclass 25, count 2 2006.238.07:40:10.66#ibcon#about to write, iclass 25, count 2 2006.238.07:40:10.66#ibcon#wrote, iclass 25, count 2 2006.238.07:40:10.66#ibcon#about to read 3, iclass 25, count 2 2006.238.07:40:10.68#ibcon#read 3, iclass 25, count 2 2006.238.07:40:10.68#ibcon#about to read 4, iclass 25, count 2 2006.238.07:40:10.68#ibcon#read 4, iclass 25, count 2 2006.238.07:40:10.68#ibcon#about to read 5, iclass 25, count 2 2006.238.07:40:10.68#ibcon#read 5, iclass 25, count 2 2006.238.07:40:10.68#ibcon#about to read 6, iclass 25, count 2 2006.238.07:40:10.68#ibcon#read 6, iclass 25, count 2 2006.238.07:40:10.68#ibcon#end of sib2, iclass 25, count 2 2006.238.07:40:10.68#ibcon#*mode == 0, iclass 25, count 2 2006.238.07:40:10.68#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.07:40:10.68#ibcon#[27=AT01-04\r\n] 2006.238.07:40:10.68#ibcon#*before write, iclass 25, count 2 2006.238.07:40:10.68#ibcon#enter sib2, iclass 25, count 2 2006.238.07:40:10.68#ibcon#flushed, iclass 25, count 2 2006.238.07:40:10.68#ibcon#about to write, iclass 25, count 2 2006.238.07:40:10.68#ibcon#wrote, iclass 25, count 2 2006.238.07:40:10.68#ibcon#about to read 3, iclass 25, count 2 2006.238.07:40:10.71#ibcon#read 3, iclass 25, count 2 2006.238.07:40:10.71#ibcon#about to read 4, iclass 25, count 2 2006.238.07:40:10.71#ibcon#read 4, iclass 25, count 2 2006.238.07:40:10.71#ibcon#about to read 5, iclass 25, count 2 2006.238.07:40:10.71#ibcon#read 5, iclass 25, count 2 2006.238.07:40:10.71#ibcon#about to read 6, iclass 25, count 2 2006.238.07:40:10.71#ibcon#read 6, iclass 25, count 2 2006.238.07:40:10.71#ibcon#end of sib2, iclass 25, count 2 2006.238.07:40:10.71#ibcon#*after write, iclass 25, count 2 2006.238.07:40:10.71#ibcon#*before return 0, iclass 25, count 2 2006.238.07:40:10.71#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:40:10.71#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:40:10.71#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.07:40:10.71#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:10.71#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:40:10.83#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:40:10.83#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:40:10.83#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:40:10.83#ibcon#first serial, iclass 25, count 0 2006.238.07:40:10.83#ibcon#enter sib2, iclass 25, count 0 2006.238.07:40:10.83#ibcon#flushed, iclass 25, count 0 2006.238.07:40:10.83#ibcon#about to write, iclass 25, count 0 2006.238.07:40:10.83#ibcon#wrote, iclass 25, count 0 2006.238.07:40:10.83#ibcon#about to read 3, iclass 25, count 0 2006.238.07:40:10.85#ibcon#read 3, iclass 25, count 0 2006.238.07:40:10.85#ibcon#about to read 4, iclass 25, count 0 2006.238.07:40:10.85#ibcon#read 4, iclass 25, count 0 2006.238.07:40:10.85#ibcon#about to read 5, iclass 25, count 0 2006.238.07:40:10.85#ibcon#read 5, iclass 25, count 0 2006.238.07:40:10.85#ibcon#about to read 6, iclass 25, count 0 2006.238.07:40:10.85#ibcon#read 6, iclass 25, count 0 2006.238.07:40:10.85#ibcon#end of sib2, iclass 25, count 0 2006.238.07:40:10.85#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:40:10.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:40:10.85#ibcon#[27=USB\r\n] 2006.238.07:40:10.85#ibcon#*before write, iclass 25, count 0 2006.238.07:40:10.85#ibcon#enter sib2, iclass 25, count 0 2006.238.07:40:10.85#ibcon#flushed, iclass 25, count 0 2006.238.07:40:10.85#ibcon#about to write, iclass 25, count 0 2006.238.07:40:10.85#ibcon#wrote, iclass 25, count 0 2006.238.07:40:10.85#ibcon#about to read 3, iclass 25, count 0 2006.238.07:40:10.88#ibcon#read 3, iclass 25, count 0 2006.238.07:40:10.88#ibcon#about to read 4, iclass 25, count 0 2006.238.07:40:10.88#ibcon#read 4, iclass 25, count 0 2006.238.07:40:10.88#ibcon#about to read 5, iclass 25, count 0 2006.238.07:40:10.88#ibcon#read 5, iclass 25, count 0 2006.238.07:40:10.88#ibcon#about to read 6, iclass 25, count 0 2006.238.07:40:10.88#ibcon#read 6, iclass 25, count 0 2006.238.07:40:10.88#ibcon#end of sib2, iclass 25, count 0 2006.238.07:40:10.88#ibcon#*after write, iclass 25, count 0 2006.238.07:40:10.88#ibcon#*before return 0, iclass 25, count 0 2006.238.07:40:10.88#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:40:10.88#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:40:10.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:40:10.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:40:10.88$vc4f8/vblo=2,640.99 2006.238.07:40:10.88#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:40:10.88#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:40:10.88#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:10.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:40:10.88#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:40:10.88#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:40:10.88#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:40:10.88#ibcon#first serial, iclass 27, count 0 2006.238.07:40:10.88#ibcon#enter sib2, iclass 27, count 0 2006.238.07:40:10.88#ibcon#flushed, iclass 27, count 0 2006.238.07:40:10.88#ibcon#about to write, iclass 27, count 0 2006.238.07:40:10.88#ibcon#wrote, iclass 27, count 0 2006.238.07:40:10.88#ibcon#about to read 3, iclass 27, count 0 2006.238.07:40:10.90#ibcon#read 3, iclass 27, count 0 2006.238.07:40:10.90#ibcon#about to read 4, iclass 27, count 0 2006.238.07:40:10.90#ibcon#read 4, iclass 27, count 0 2006.238.07:40:10.90#ibcon#about to read 5, iclass 27, count 0 2006.238.07:40:10.90#ibcon#read 5, iclass 27, count 0 2006.238.07:40:10.90#ibcon#about to read 6, iclass 27, count 0 2006.238.07:40:10.90#ibcon#read 6, iclass 27, count 0 2006.238.07:40:10.90#ibcon#end of sib2, iclass 27, count 0 2006.238.07:40:10.90#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:40:10.90#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:40:10.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:40:10.90#ibcon#*before write, iclass 27, count 0 2006.238.07:40:10.90#ibcon#enter sib2, iclass 27, count 0 2006.238.07:40:10.90#ibcon#flushed, iclass 27, count 0 2006.238.07:40:10.90#ibcon#about to write, iclass 27, count 0 2006.238.07:40:10.90#ibcon#wrote, iclass 27, count 0 2006.238.07:40:10.90#ibcon#about to read 3, iclass 27, count 0 2006.238.07:40:10.94#ibcon#read 3, iclass 27, count 0 2006.238.07:40:10.94#ibcon#about to read 4, iclass 27, count 0 2006.238.07:40:10.94#ibcon#read 4, iclass 27, count 0 2006.238.07:40:10.94#ibcon#about to read 5, iclass 27, count 0 2006.238.07:40:10.94#ibcon#read 5, iclass 27, count 0 2006.238.07:40:10.94#ibcon#about to read 6, iclass 27, count 0 2006.238.07:40:10.94#ibcon#read 6, iclass 27, count 0 2006.238.07:40:10.94#ibcon#end of sib2, iclass 27, count 0 2006.238.07:40:10.94#ibcon#*after write, iclass 27, count 0 2006.238.07:40:10.94#ibcon#*before return 0, iclass 27, count 0 2006.238.07:40:10.94#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:40:10.94#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:40:10.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:40:10.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:40:10.94$vc4f8/vb=2,4 2006.238.07:40:10.94#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.07:40:10.94#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.07:40:10.94#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:10.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:40:11.00#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:40:11.00#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:40:11.00#ibcon#enter wrdev, iclass 29, count 2 2006.238.07:40:11.00#ibcon#first serial, iclass 29, count 2 2006.238.07:40:11.00#ibcon#enter sib2, iclass 29, count 2 2006.238.07:40:11.00#ibcon#flushed, iclass 29, count 2 2006.238.07:40:11.00#ibcon#about to write, iclass 29, count 2 2006.238.07:40:11.00#ibcon#wrote, iclass 29, count 2 2006.238.07:40:11.00#ibcon#about to read 3, iclass 29, count 2 2006.238.07:40:11.02#ibcon#read 3, iclass 29, count 2 2006.238.07:40:11.02#ibcon#about to read 4, iclass 29, count 2 2006.238.07:40:11.02#ibcon#read 4, iclass 29, count 2 2006.238.07:40:11.02#ibcon#about to read 5, iclass 29, count 2 2006.238.07:40:11.02#ibcon#read 5, iclass 29, count 2 2006.238.07:40:11.02#ibcon#about to read 6, iclass 29, count 2 2006.238.07:40:11.02#ibcon#read 6, iclass 29, count 2 2006.238.07:40:11.02#ibcon#end of sib2, iclass 29, count 2 2006.238.07:40:11.02#ibcon#*mode == 0, iclass 29, count 2 2006.238.07:40:11.02#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.07:40:11.02#ibcon#[27=AT02-04\r\n] 2006.238.07:40:11.02#ibcon#*before write, iclass 29, count 2 2006.238.07:40:11.02#ibcon#enter sib2, iclass 29, count 2 2006.238.07:40:11.02#ibcon#flushed, iclass 29, count 2 2006.238.07:40:11.02#ibcon#about to write, iclass 29, count 2 2006.238.07:40:11.02#ibcon#wrote, iclass 29, count 2 2006.238.07:40:11.02#ibcon#about to read 3, iclass 29, count 2 2006.238.07:40:11.05#ibcon#read 3, iclass 29, count 2 2006.238.07:40:11.05#ibcon#about to read 4, iclass 29, count 2 2006.238.07:40:11.05#ibcon#read 4, iclass 29, count 2 2006.238.07:40:11.05#ibcon#about to read 5, iclass 29, count 2 2006.238.07:40:11.05#ibcon#read 5, iclass 29, count 2 2006.238.07:40:11.05#ibcon#about to read 6, iclass 29, count 2 2006.238.07:40:11.05#ibcon#read 6, iclass 29, count 2 2006.238.07:40:11.05#ibcon#end of sib2, iclass 29, count 2 2006.238.07:40:11.05#ibcon#*after write, iclass 29, count 2 2006.238.07:40:11.05#ibcon#*before return 0, iclass 29, count 2 2006.238.07:40:11.05#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:40:11.05#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:40:11.05#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.07:40:11.05#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:11.05#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:40:11.17#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:40:11.17#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:40:11.17#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:40:11.17#ibcon#first serial, iclass 29, count 0 2006.238.07:40:11.17#ibcon#enter sib2, iclass 29, count 0 2006.238.07:40:11.17#ibcon#flushed, iclass 29, count 0 2006.238.07:40:11.17#ibcon#about to write, iclass 29, count 0 2006.238.07:40:11.17#ibcon#wrote, iclass 29, count 0 2006.238.07:40:11.17#ibcon#about to read 3, iclass 29, count 0 2006.238.07:40:11.19#ibcon#read 3, iclass 29, count 0 2006.238.07:40:11.19#ibcon#about to read 4, iclass 29, count 0 2006.238.07:40:11.19#ibcon#read 4, iclass 29, count 0 2006.238.07:40:11.19#ibcon#about to read 5, iclass 29, count 0 2006.238.07:40:11.19#ibcon#read 5, iclass 29, count 0 2006.238.07:40:11.19#ibcon#about to read 6, iclass 29, count 0 2006.238.07:40:11.19#ibcon#read 6, iclass 29, count 0 2006.238.07:40:11.19#ibcon#end of sib2, iclass 29, count 0 2006.238.07:40:11.19#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:40:11.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:40:11.19#ibcon#[27=USB\r\n] 2006.238.07:40:11.19#ibcon#*before write, iclass 29, count 0 2006.238.07:40:11.19#ibcon#enter sib2, iclass 29, count 0 2006.238.07:40:11.19#ibcon#flushed, iclass 29, count 0 2006.238.07:40:11.19#ibcon#about to write, iclass 29, count 0 2006.238.07:40:11.19#ibcon#wrote, iclass 29, count 0 2006.238.07:40:11.19#ibcon#about to read 3, iclass 29, count 0 2006.238.07:40:11.22#ibcon#read 3, iclass 29, count 0 2006.238.07:40:11.22#ibcon#about to read 4, iclass 29, count 0 2006.238.07:40:11.22#ibcon#read 4, iclass 29, count 0 2006.238.07:40:11.22#ibcon#about to read 5, iclass 29, count 0 2006.238.07:40:11.22#ibcon#read 5, iclass 29, count 0 2006.238.07:40:11.22#ibcon#about to read 6, iclass 29, count 0 2006.238.07:40:11.22#ibcon#read 6, iclass 29, count 0 2006.238.07:40:11.22#ibcon#end of sib2, iclass 29, count 0 2006.238.07:40:11.22#ibcon#*after write, iclass 29, count 0 2006.238.07:40:11.22#ibcon#*before return 0, iclass 29, count 0 2006.238.07:40:11.22#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:40:11.22#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:40:11.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:40:11.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:40:11.22$vc4f8/vblo=3,656.99 2006.238.07:40:11.22#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.07:40:11.22#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.07:40:11.22#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:11.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:40:11.22#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:40:11.22#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:40:11.22#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:40:11.22#ibcon#first serial, iclass 31, count 0 2006.238.07:40:11.22#ibcon#enter sib2, iclass 31, count 0 2006.238.07:40:11.22#ibcon#flushed, iclass 31, count 0 2006.238.07:40:11.22#ibcon#about to write, iclass 31, count 0 2006.238.07:40:11.22#ibcon#wrote, iclass 31, count 0 2006.238.07:40:11.22#ibcon#about to read 3, iclass 31, count 0 2006.238.07:40:11.24#ibcon#read 3, iclass 31, count 0 2006.238.07:40:11.24#ibcon#about to read 4, iclass 31, count 0 2006.238.07:40:11.24#ibcon#read 4, iclass 31, count 0 2006.238.07:40:11.24#ibcon#about to read 5, iclass 31, count 0 2006.238.07:40:11.24#ibcon#read 5, iclass 31, count 0 2006.238.07:40:11.24#ibcon#about to read 6, iclass 31, count 0 2006.238.07:40:11.24#ibcon#read 6, iclass 31, count 0 2006.238.07:40:11.24#ibcon#end of sib2, iclass 31, count 0 2006.238.07:40:11.24#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:40:11.24#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:40:11.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:40:11.24#ibcon#*before write, iclass 31, count 0 2006.238.07:40:11.24#ibcon#enter sib2, iclass 31, count 0 2006.238.07:40:11.24#ibcon#flushed, iclass 31, count 0 2006.238.07:40:11.24#ibcon#about to write, iclass 31, count 0 2006.238.07:40:11.24#ibcon#wrote, iclass 31, count 0 2006.238.07:40:11.24#ibcon#about to read 3, iclass 31, count 0 2006.238.07:40:11.28#ibcon#read 3, iclass 31, count 0 2006.238.07:40:11.28#ibcon#about to read 4, iclass 31, count 0 2006.238.07:40:11.28#ibcon#read 4, iclass 31, count 0 2006.238.07:40:11.28#ibcon#about to read 5, iclass 31, count 0 2006.238.07:40:11.28#ibcon#read 5, iclass 31, count 0 2006.238.07:40:11.28#ibcon#about to read 6, iclass 31, count 0 2006.238.07:40:11.28#ibcon#read 6, iclass 31, count 0 2006.238.07:40:11.28#ibcon#end of sib2, iclass 31, count 0 2006.238.07:40:11.28#ibcon#*after write, iclass 31, count 0 2006.238.07:40:11.28#ibcon#*before return 0, iclass 31, count 0 2006.238.07:40:11.28#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:40:11.28#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:40:11.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:40:11.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:40:11.28$vc4f8/vb=3,4 2006.238.07:40:11.28#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:40:11.28#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:40:11.28#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:11.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:40:11.34#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:40:11.34#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:40:11.34#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:40:11.34#ibcon#first serial, iclass 33, count 2 2006.238.07:40:11.34#ibcon#enter sib2, iclass 33, count 2 2006.238.07:40:11.34#ibcon#flushed, iclass 33, count 2 2006.238.07:40:11.34#ibcon#about to write, iclass 33, count 2 2006.238.07:40:11.34#ibcon#wrote, iclass 33, count 2 2006.238.07:40:11.34#ibcon#about to read 3, iclass 33, count 2 2006.238.07:40:11.36#ibcon#read 3, iclass 33, count 2 2006.238.07:40:11.36#ibcon#about to read 4, iclass 33, count 2 2006.238.07:40:11.36#ibcon#read 4, iclass 33, count 2 2006.238.07:40:11.36#ibcon#about to read 5, iclass 33, count 2 2006.238.07:40:11.36#ibcon#read 5, iclass 33, count 2 2006.238.07:40:11.36#ibcon#about to read 6, iclass 33, count 2 2006.238.07:40:11.36#ibcon#read 6, iclass 33, count 2 2006.238.07:40:11.36#ibcon#end of sib2, iclass 33, count 2 2006.238.07:40:11.36#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:40:11.36#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:40:11.36#ibcon#[27=AT03-04\r\n] 2006.238.07:40:11.36#ibcon#*before write, iclass 33, count 2 2006.238.07:40:11.36#ibcon#enter sib2, iclass 33, count 2 2006.238.07:40:11.36#ibcon#flushed, iclass 33, count 2 2006.238.07:40:11.36#ibcon#about to write, iclass 33, count 2 2006.238.07:40:11.36#ibcon#wrote, iclass 33, count 2 2006.238.07:40:11.36#ibcon#about to read 3, iclass 33, count 2 2006.238.07:40:11.39#ibcon#read 3, iclass 33, count 2 2006.238.07:40:11.39#ibcon#about to read 4, iclass 33, count 2 2006.238.07:40:11.39#ibcon#read 4, iclass 33, count 2 2006.238.07:40:11.39#ibcon#about to read 5, iclass 33, count 2 2006.238.07:40:11.39#ibcon#read 5, iclass 33, count 2 2006.238.07:40:11.39#ibcon#about to read 6, iclass 33, count 2 2006.238.07:40:11.39#ibcon#read 6, iclass 33, count 2 2006.238.07:40:11.39#ibcon#end of sib2, iclass 33, count 2 2006.238.07:40:11.39#ibcon#*after write, iclass 33, count 2 2006.238.07:40:11.39#ibcon#*before return 0, iclass 33, count 2 2006.238.07:40:11.39#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:40:11.39#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:40:11.39#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:40:11.39#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:11.39#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:40:11.51#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:40:11.51#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:40:11.51#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:40:11.51#ibcon#first serial, iclass 33, count 0 2006.238.07:40:11.51#ibcon#enter sib2, iclass 33, count 0 2006.238.07:40:11.51#ibcon#flushed, iclass 33, count 0 2006.238.07:40:11.51#ibcon#about to write, iclass 33, count 0 2006.238.07:40:11.51#ibcon#wrote, iclass 33, count 0 2006.238.07:40:11.51#ibcon#about to read 3, iclass 33, count 0 2006.238.07:40:11.53#ibcon#read 3, iclass 33, count 0 2006.238.07:40:11.53#ibcon#about to read 4, iclass 33, count 0 2006.238.07:40:11.53#ibcon#read 4, iclass 33, count 0 2006.238.07:40:11.53#ibcon#about to read 5, iclass 33, count 0 2006.238.07:40:11.53#ibcon#read 5, iclass 33, count 0 2006.238.07:40:11.53#ibcon#about to read 6, iclass 33, count 0 2006.238.07:40:11.53#ibcon#read 6, iclass 33, count 0 2006.238.07:40:11.53#ibcon#end of sib2, iclass 33, count 0 2006.238.07:40:11.53#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:40:11.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:40:11.53#ibcon#[27=USB\r\n] 2006.238.07:40:11.53#ibcon#*before write, iclass 33, count 0 2006.238.07:40:11.53#ibcon#enter sib2, iclass 33, count 0 2006.238.07:40:11.53#ibcon#flushed, iclass 33, count 0 2006.238.07:40:11.53#ibcon#about to write, iclass 33, count 0 2006.238.07:40:11.53#ibcon#wrote, iclass 33, count 0 2006.238.07:40:11.53#ibcon#about to read 3, iclass 33, count 0 2006.238.07:40:11.56#ibcon#read 3, iclass 33, count 0 2006.238.07:40:11.56#ibcon#about to read 4, iclass 33, count 0 2006.238.07:40:11.56#ibcon#read 4, iclass 33, count 0 2006.238.07:40:11.56#ibcon#about to read 5, iclass 33, count 0 2006.238.07:40:11.56#ibcon#read 5, iclass 33, count 0 2006.238.07:40:11.56#ibcon#about to read 6, iclass 33, count 0 2006.238.07:40:11.56#ibcon#read 6, iclass 33, count 0 2006.238.07:40:11.56#ibcon#end of sib2, iclass 33, count 0 2006.238.07:40:11.56#ibcon#*after write, iclass 33, count 0 2006.238.07:40:11.56#ibcon#*before return 0, iclass 33, count 0 2006.238.07:40:11.56#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:40:11.56#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:40:11.56#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:40:11.56#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:40:11.56$vc4f8/vblo=4,712.99 2006.238.07:40:11.56#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:40:11.56#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:40:11.56#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:11.56#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:40:11.56#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:40:11.56#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:40:11.56#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:40:11.56#ibcon#first serial, iclass 35, count 0 2006.238.07:40:11.56#ibcon#enter sib2, iclass 35, count 0 2006.238.07:40:11.56#ibcon#flushed, iclass 35, count 0 2006.238.07:40:11.56#ibcon#about to write, iclass 35, count 0 2006.238.07:40:11.56#ibcon#wrote, iclass 35, count 0 2006.238.07:40:11.56#ibcon#about to read 3, iclass 35, count 0 2006.238.07:40:11.58#ibcon#read 3, iclass 35, count 0 2006.238.07:40:11.58#ibcon#about to read 4, iclass 35, count 0 2006.238.07:40:11.58#ibcon#read 4, iclass 35, count 0 2006.238.07:40:11.58#ibcon#about to read 5, iclass 35, count 0 2006.238.07:40:11.58#ibcon#read 5, iclass 35, count 0 2006.238.07:40:11.58#ibcon#about to read 6, iclass 35, count 0 2006.238.07:40:11.58#ibcon#read 6, iclass 35, count 0 2006.238.07:40:11.58#ibcon#end of sib2, iclass 35, count 0 2006.238.07:40:11.58#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:40:11.58#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:40:11.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:40:11.58#ibcon#*before write, iclass 35, count 0 2006.238.07:40:11.58#ibcon#enter sib2, iclass 35, count 0 2006.238.07:40:11.58#ibcon#flushed, iclass 35, count 0 2006.238.07:40:11.58#ibcon#about to write, iclass 35, count 0 2006.238.07:40:11.58#ibcon#wrote, iclass 35, count 0 2006.238.07:40:11.58#ibcon#about to read 3, iclass 35, count 0 2006.238.07:40:11.62#ibcon#read 3, iclass 35, count 0 2006.238.07:40:11.62#ibcon#about to read 4, iclass 35, count 0 2006.238.07:40:11.62#ibcon#read 4, iclass 35, count 0 2006.238.07:40:11.62#ibcon#about to read 5, iclass 35, count 0 2006.238.07:40:11.62#ibcon#read 5, iclass 35, count 0 2006.238.07:40:11.62#ibcon#about to read 6, iclass 35, count 0 2006.238.07:40:11.62#ibcon#read 6, iclass 35, count 0 2006.238.07:40:11.62#ibcon#end of sib2, iclass 35, count 0 2006.238.07:40:11.62#ibcon#*after write, iclass 35, count 0 2006.238.07:40:11.62#ibcon#*before return 0, iclass 35, count 0 2006.238.07:40:11.62#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:40:11.62#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:40:11.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:40:11.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:40:11.62$vc4f8/vb=4,4 2006.238.07:40:11.62#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.07:40:11.62#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.07:40:11.62#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:11.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:40:11.68#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:40:11.68#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:40:11.68#ibcon#enter wrdev, iclass 37, count 2 2006.238.07:40:11.68#ibcon#first serial, iclass 37, count 2 2006.238.07:40:11.68#ibcon#enter sib2, iclass 37, count 2 2006.238.07:40:11.68#ibcon#flushed, iclass 37, count 2 2006.238.07:40:11.68#ibcon#about to write, iclass 37, count 2 2006.238.07:40:11.68#ibcon#wrote, iclass 37, count 2 2006.238.07:40:11.68#ibcon#about to read 3, iclass 37, count 2 2006.238.07:40:11.70#ibcon#read 3, iclass 37, count 2 2006.238.07:40:11.70#ibcon#about to read 4, iclass 37, count 2 2006.238.07:40:11.70#ibcon#read 4, iclass 37, count 2 2006.238.07:40:11.70#ibcon#about to read 5, iclass 37, count 2 2006.238.07:40:11.70#ibcon#read 5, iclass 37, count 2 2006.238.07:40:11.70#ibcon#about to read 6, iclass 37, count 2 2006.238.07:40:11.70#ibcon#read 6, iclass 37, count 2 2006.238.07:40:11.70#ibcon#end of sib2, iclass 37, count 2 2006.238.07:40:11.70#ibcon#*mode == 0, iclass 37, count 2 2006.238.07:40:11.70#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.07:40:11.70#ibcon#[27=AT04-04\r\n] 2006.238.07:40:11.70#ibcon#*before write, iclass 37, count 2 2006.238.07:40:11.70#ibcon#enter sib2, iclass 37, count 2 2006.238.07:40:11.70#ibcon#flushed, iclass 37, count 2 2006.238.07:40:11.70#ibcon#about to write, iclass 37, count 2 2006.238.07:40:11.70#ibcon#wrote, iclass 37, count 2 2006.238.07:40:11.70#ibcon#about to read 3, iclass 37, count 2 2006.238.07:40:11.73#ibcon#read 3, iclass 37, count 2 2006.238.07:40:11.73#ibcon#about to read 4, iclass 37, count 2 2006.238.07:40:11.73#ibcon#read 4, iclass 37, count 2 2006.238.07:40:11.73#ibcon#about to read 5, iclass 37, count 2 2006.238.07:40:11.73#ibcon#read 5, iclass 37, count 2 2006.238.07:40:11.73#ibcon#about to read 6, iclass 37, count 2 2006.238.07:40:11.73#ibcon#read 6, iclass 37, count 2 2006.238.07:40:11.73#ibcon#end of sib2, iclass 37, count 2 2006.238.07:40:11.73#ibcon#*after write, iclass 37, count 2 2006.238.07:40:11.73#ibcon#*before return 0, iclass 37, count 2 2006.238.07:40:11.73#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:40:11.73#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:40:11.73#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.07:40:11.73#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:11.73#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:40:11.85#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:40:11.85#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:40:11.85#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:40:11.85#ibcon#first serial, iclass 37, count 0 2006.238.07:40:11.85#ibcon#enter sib2, iclass 37, count 0 2006.238.07:40:11.85#ibcon#flushed, iclass 37, count 0 2006.238.07:40:11.85#ibcon#about to write, iclass 37, count 0 2006.238.07:40:11.85#ibcon#wrote, iclass 37, count 0 2006.238.07:40:11.85#ibcon#about to read 3, iclass 37, count 0 2006.238.07:40:11.87#ibcon#read 3, iclass 37, count 0 2006.238.07:40:11.87#ibcon#about to read 4, iclass 37, count 0 2006.238.07:40:11.87#ibcon#read 4, iclass 37, count 0 2006.238.07:40:11.87#ibcon#about to read 5, iclass 37, count 0 2006.238.07:40:11.87#ibcon#read 5, iclass 37, count 0 2006.238.07:40:11.87#ibcon#about to read 6, iclass 37, count 0 2006.238.07:40:11.87#ibcon#read 6, iclass 37, count 0 2006.238.07:40:11.87#ibcon#end of sib2, iclass 37, count 0 2006.238.07:40:11.87#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:40:11.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:40:11.87#ibcon#[27=USB\r\n] 2006.238.07:40:11.87#ibcon#*before write, iclass 37, count 0 2006.238.07:40:11.87#ibcon#enter sib2, iclass 37, count 0 2006.238.07:40:11.87#ibcon#flushed, iclass 37, count 0 2006.238.07:40:11.87#ibcon#about to write, iclass 37, count 0 2006.238.07:40:11.87#ibcon#wrote, iclass 37, count 0 2006.238.07:40:11.87#ibcon#about to read 3, iclass 37, count 0 2006.238.07:40:11.90#ibcon#read 3, iclass 37, count 0 2006.238.07:40:11.90#ibcon#about to read 4, iclass 37, count 0 2006.238.07:40:11.90#ibcon#read 4, iclass 37, count 0 2006.238.07:40:11.90#ibcon#about to read 5, iclass 37, count 0 2006.238.07:40:11.90#ibcon#read 5, iclass 37, count 0 2006.238.07:40:11.90#ibcon#about to read 6, iclass 37, count 0 2006.238.07:40:11.90#ibcon#read 6, iclass 37, count 0 2006.238.07:40:11.90#ibcon#end of sib2, iclass 37, count 0 2006.238.07:40:11.90#ibcon#*after write, iclass 37, count 0 2006.238.07:40:11.90#ibcon#*before return 0, iclass 37, count 0 2006.238.07:40:11.90#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:40:11.90#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:40:11.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:40:11.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:40:11.90$vc4f8/vblo=5,744.99 2006.238.07:40:11.90#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.07:40:11.90#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.07:40:11.90#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:11.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:40:11.90#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:40:11.90#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:40:11.90#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:40:11.90#ibcon#first serial, iclass 39, count 0 2006.238.07:40:11.90#ibcon#enter sib2, iclass 39, count 0 2006.238.07:40:11.90#ibcon#flushed, iclass 39, count 0 2006.238.07:40:11.90#ibcon#about to write, iclass 39, count 0 2006.238.07:40:11.90#ibcon#wrote, iclass 39, count 0 2006.238.07:40:11.90#ibcon#about to read 3, iclass 39, count 0 2006.238.07:40:11.92#ibcon#read 3, iclass 39, count 0 2006.238.07:40:11.92#ibcon#about to read 4, iclass 39, count 0 2006.238.07:40:11.92#ibcon#read 4, iclass 39, count 0 2006.238.07:40:11.92#ibcon#about to read 5, iclass 39, count 0 2006.238.07:40:11.92#ibcon#read 5, iclass 39, count 0 2006.238.07:40:11.92#ibcon#about to read 6, iclass 39, count 0 2006.238.07:40:11.92#ibcon#read 6, iclass 39, count 0 2006.238.07:40:11.92#ibcon#end of sib2, iclass 39, count 0 2006.238.07:40:11.92#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:40:11.92#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:40:11.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:40:11.92#ibcon#*before write, iclass 39, count 0 2006.238.07:40:11.92#ibcon#enter sib2, iclass 39, count 0 2006.238.07:40:11.92#ibcon#flushed, iclass 39, count 0 2006.238.07:40:11.92#ibcon#about to write, iclass 39, count 0 2006.238.07:40:11.92#ibcon#wrote, iclass 39, count 0 2006.238.07:40:11.92#ibcon#about to read 3, iclass 39, count 0 2006.238.07:40:11.96#ibcon#read 3, iclass 39, count 0 2006.238.07:40:11.96#ibcon#about to read 4, iclass 39, count 0 2006.238.07:40:11.96#ibcon#read 4, iclass 39, count 0 2006.238.07:40:11.96#ibcon#about to read 5, iclass 39, count 0 2006.238.07:40:11.96#ibcon#read 5, iclass 39, count 0 2006.238.07:40:11.96#ibcon#about to read 6, iclass 39, count 0 2006.238.07:40:11.96#ibcon#read 6, iclass 39, count 0 2006.238.07:40:11.96#ibcon#end of sib2, iclass 39, count 0 2006.238.07:40:11.96#ibcon#*after write, iclass 39, count 0 2006.238.07:40:11.96#ibcon#*before return 0, iclass 39, count 0 2006.238.07:40:11.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:40:11.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:40:11.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:40:11.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:40:11.96$vc4f8/vb=5,4 2006.238.07:40:11.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.07:40:11.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.07:40:11.96#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:11.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:40:12.02#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:40:12.02#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:40:12.02#ibcon#enter wrdev, iclass 3, count 2 2006.238.07:40:12.02#ibcon#first serial, iclass 3, count 2 2006.238.07:40:12.02#ibcon#enter sib2, iclass 3, count 2 2006.238.07:40:12.02#ibcon#flushed, iclass 3, count 2 2006.238.07:40:12.02#ibcon#about to write, iclass 3, count 2 2006.238.07:40:12.02#ibcon#wrote, iclass 3, count 2 2006.238.07:40:12.02#ibcon#about to read 3, iclass 3, count 2 2006.238.07:40:12.04#ibcon#read 3, iclass 3, count 2 2006.238.07:40:12.04#ibcon#about to read 4, iclass 3, count 2 2006.238.07:40:12.04#ibcon#read 4, iclass 3, count 2 2006.238.07:40:12.04#ibcon#about to read 5, iclass 3, count 2 2006.238.07:40:12.04#ibcon#read 5, iclass 3, count 2 2006.238.07:40:12.04#ibcon#about to read 6, iclass 3, count 2 2006.238.07:40:12.04#ibcon#read 6, iclass 3, count 2 2006.238.07:40:12.04#ibcon#end of sib2, iclass 3, count 2 2006.238.07:40:12.04#ibcon#*mode == 0, iclass 3, count 2 2006.238.07:40:12.04#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.07:40:12.04#ibcon#[27=AT05-04\r\n] 2006.238.07:40:12.04#ibcon#*before write, iclass 3, count 2 2006.238.07:40:12.04#ibcon#enter sib2, iclass 3, count 2 2006.238.07:40:12.04#ibcon#flushed, iclass 3, count 2 2006.238.07:40:12.04#ibcon#about to write, iclass 3, count 2 2006.238.07:40:12.04#ibcon#wrote, iclass 3, count 2 2006.238.07:40:12.04#ibcon#about to read 3, iclass 3, count 2 2006.238.07:40:12.07#ibcon#read 3, iclass 3, count 2 2006.238.07:40:12.07#ibcon#about to read 4, iclass 3, count 2 2006.238.07:40:12.07#ibcon#read 4, iclass 3, count 2 2006.238.07:40:12.07#ibcon#about to read 5, iclass 3, count 2 2006.238.07:40:12.07#ibcon#read 5, iclass 3, count 2 2006.238.07:40:12.07#ibcon#about to read 6, iclass 3, count 2 2006.238.07:40:12.07#ibcon#read 6, iclass 3, count 2 2006.238.07:40:12.07#ibcon#end of sib2, iclass 3, count 2 2006.238.07:40:12.07#ibcon#*after write, iclass 3, count 2 2006.238.07:40:12.07#ibcon#*before return 0, iclass 3, count 2 2006.238.07:40:12.07#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:40:12.07#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:40:12.07#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.07:40:12.07#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:12.07#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:40:12.19#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:40:12.19#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:40:12.19#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:40:12.19#ibcon#first serial, iclass 3, count 0 2006.238.07:40:12.19#ibcon#enter sib2, iclass 3, count 0 2006.238.07:40:12.19#ibcon#flushed, iclass 3, count 0 2006.238.07:40:12.19#ibcon#about to write, iclass 3, count 0 2006.238.07:40:12.19#ibcon#wrote, iclass 3, count 0 2006.238.07:40:12.19#ibcon#about to read 3, iclass 3, count 0 2006.238.07:40:12.21#ibcon#read 3, iclass 3, count 0 2006.238.07:40:12.21#ibcon#about to read 4, iclass 3, count 0 2006.238.07:40:12.21#ibcon#read 4, iclass 3, count 0 2006.238.07:40:12.21#ibcon#about to read 5, iclass 3, count 0 2006.238.07:40:12.21#ibcon#read 5, iclass 3, count 0 2006.238.07:40:12.21#ibcon#about to read 6, iclass 3, count 0 2006.238.07:40:12.21#ibcon#read 6, iclass 3, count 0 2006.238.07:40:12.21#ibcon#end of sib2, iclass 3, count 0 2006.238.07:40:12.21#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:40:12.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:40:12.21#ibcon#[27=USB\r\n] 2006.238.07:40:12.21#ibcon#*before write, iclass 3, count 0 2006.238.07:40:12.21#ibcon#enter sib2, iclass 3, count 0 2006.238.07:40:12.21#ibcon#flushed, iclass 3, count 0 2006.238.07:40:12.21#ibcon#about to write, iclass 3, count 0 2006.238.07:40:12.21#ibcon#wrote, iclass 3, count 0 2006.238.07:40:12.21#ibcon#about to read 3, iclass 3, count 0 2006.238.07:40:12.24#ibcon#read 3, iclass 3, count 0 2006.238.07:40:12.24#ibcon#about to read 4, iclass 3, count 0 2006.238.07:40:12.24#ibcon#read 4, iclass 3, count 0 2006.238.07:40:12.24#ibcon#about to read 5, iclass 3, count 0 2006.238.07:40:12.24#ibcon#read 5, iclass 3, count 0 2006.238.07:40:12.24#ibcon#about to read 6, iclass 3, count 0 2006.238.07:40:12.24#ibcon#read 6, iclass 3, count 0 2006.238.07:40:12.24#ibcon#end of sib2, iclass 3, count 0 2006.238.07:40:12.24#ibcon#*after write, iclass 3, count 0 2006.238.07:40:12.24#ibcon#*before return 0, iclass 3, count 0 2006.238.07:40:12.24#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:40:12.24#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:40:12.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:40:12.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:40:12.24$vc4f8/vblo=6,752.99 2006.238.07:40:12.24#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.07:40:12.24#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.07:40:12.24#ibcon#ireg 17 cls_cnt 0 2006.238.07:40:12.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:40:12.24#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:40:12.24#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:40:12.24#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:40:12.24#ibcon#first serial, iclass 5, count 0 2006.238.07:40:12.24#ibcon#enter sib2, iclass 5, count 0 2006.238.07:40:12.24#ibcon#flushed, iclass 5, count 0 2006.238.07:40:12.24#ibcon#about to write, iclass 5, count 0 2006.238.07:40:12.24#ibcon#wrote, iclass 5, count 0 2006.238.07:40:12.24#ibcon#about to read 3, iclass 5, count 0 2006.238.07:40:12.26#ibcon#read 3, iclass 5, count 0 2006.238.07:40:12.26#ibcon#about to read 4, iclass 5, count 0 2006.238.07:40:12.26#ibcon#read 4, iclass 5, count 0 2006.238.07:40:12.26#ibcon#about to read 5, iclass 5, count 0 2006.238.07:40:12.26#ibcon#read 5, iclass 5, count 0 2006.238.07:40:12.26#ibcon#about to read 6, iclass 5, count 0 2006.238.07:40:12.26#ibcon#read 6, iclass 5, count 0 2006.238.07:40:12.26#ibcon#end of sib2, iclass 5, count 0 2006.238.07:40:12.26#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:40:12.26#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:40:12.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:40:12.26#ibcon#*before write, iclass 5, count 0 2006.238.07:40:12.26#ibcon#enter sib2, iclass 5, count 0 2006.238.07:40:12.26#ibcon#flushed, iclass 5, count 0 2006.238.07:40:12.26#ibcon#about to write, iclass 5, count 0 2006.238.07:40:12.26#ibcon#wrote, iclass 5, count 0 2006.238.07:40:12.26#ibcon#about to read 3, iclass 5, count 0 2006.238.07:40:12.30#ibcon#read 3, iclass 5, count 0 2006.238.07:40:12.30#ibcon#about to read 4, iclass 5, count 0 2006.238.07:40:12.30#ibcon#read 4, iclass 5, count 0 2006.238.07:40:12.30#ibcon#about to read 5, iclass 5, count 0 2006.238.07:40:12.30#ibcon#read 5, iclass 5, count 0 2006.238.07:40:12.30#ibcon#about to read 6, iclass 5, count 0 2006.238.07:40:12.30#ibcon#read 6, iclass 5, count 0 2006.238.07:40:12.30#ibcon#end of sib2, iclass 5, count 0 2006.238.07:40:12.30#ibcon#*after write, iclass 5, count 0 2006.238.07:40:12.30#ibcon#*before return 0, iclass 5, count 0 2006.238.07:40:12.30#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:40:12.30#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:40:12.30#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:40:12.30#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:40:12.30$vc4f8/vb=6,4 2006.238.07:40:12.30#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.07:40:12.30#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.07:40:12.30#ibcon#ireg 11 cls_cnt 2 2006.238.07:40:12.30#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:40:12.36#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:40:12.36#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:40:12.36#ibcon#enter wrdev, iclass 7, count 2 2006.238.07:40:12.36#ibcon#first serial, iclass 7, count 2 2006.238.07:40:12.36#ibcon#enter sib2, iclass 7, count 2 2006.238.07:40:12.36#ibcon#flushed, iclass 7, count 2 2006.238.07:40:12.36#ibcon#about to write, iclass 7, count 2 2006.238.07:40:12.36#ibcon#wrote, iclass 7, count 2 2006.238.07:40:12.36#ibcon#about to read 3, iclass 7, count 2 2006.238.07:40:12.38#ibcon#read 3, iclass 7, count 2 2006.238.07:40:12.38#ibcon#about to read 4, iclass 7, count 2 2006.238.07:40:12.38#ibcon#read 4, iclass 7, count 2 2006.238.07:40:12.38#ibcon#about to read 5, iclass 7, count 2 2006.238.07:40:12.38#ibcon#read 5, iclass 7, count 2 2006.238.07:40:12.38#ibcon#about to read 6, iclass 7, count 2 2006.238.07:40:12.38#ibcon#read 6, iclass 7, count 2 2006.238.07:40:12.38#ibcon#end of sib2, iclass 7, count 2 2006.238.07:40:12.38#ibcon#*mode == 0, iclass 7, count 2 2006.238.07:40:12.38#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.07:40:12.38#ibcon#[27=AT06-04\r\n] 2006.238.07:40:12.38#ibcon#*before write, iclass 7, count 2 2006.238.07:40:12.38#ibcon#enter sib2, iclass 7, count 2 2006.238.07:40:12.38#ibcon#flushed, iclass 7, count 2 2006.238.07:40:12.38#ibcon#about to write, iclass 7, count 2 2006.238.07:40:12.38#ibcon#wrote, iclass 7, count 2 2006.238.07:40:12.38#ibcon#about to read 3, iclass 7, count 2 2006.238.07:40:12.41#ibcon#read 3, iclass 7, count 2 2006.238.07:40:12.41#ibcon#about to read 4, iclass 7, count 2 2006.238.07:40:12.41#ibcon#read 4, iclass 7, count 2 2006.238.07:40:12.41#ibcon#about to read 5, iclass 7, count 2 2006.238.07:40:12.41#ibcon#read 5, iclass 7, count 2 2006.238.07:40:12.41#ibcon#about to read 6, iclass 7, count 2 2006.238.07:40:12.41#ibcon#read 6, iclass 7, count 2 2006.238.07:40:12.41#ibcon#end of sib2, iclass 7, count 2 2006.238.07:40:12.41#ibcon#*after write, iclass 7, count 2 2006.238.07:40:12.41#ibcon#*before return 0, iclass 7, count 2 2006.238.07:40:12.41#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:40:12.41#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:40:12.41#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.07:40:12.41#ibcon#ireg 7 cls_cnt 0 2006.238.07:40:12.41#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:40:12.53#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:40:12.53#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:40:12.53#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:40:12.53#ibcon#first serial, iclass 7, count 0 2006.238.07:40:12.53#ibcon#enter sib2, iclass 7, count 0 2006.238.07:40:12.53#ibcon#flushed, iclass 7, count 0 2006.238.07:40:12.53#ibcon#about to write, iclass 7, count 0 2006.238.07:40:12.53#ibcon#wrote, iclass 7, count 0 2006.238.07:40:12.53#ibcon#about to read 3, iclass 7, count 0 2006.238.07:40:12.55#ibcon#read 3, iclass 7, count 0 2006.238.07:40:12.55#ibcon#about to read 4, iclass 7, count 0 2006.238.07:40:12.55#ibcon#read 4, iclass 7, count 0 2006.238.07:40:12.55#ibcon#about to read 5, iclass 7, count 0 2006.238.07:40:12.55#ibcon#read 5, iclass 7, count 0 2006.238.07:40:12.55#ibcon#about to read 6, iclass 7, count 0 2006.238.07:40:12.55#ibcon#read 6, iclass 7, count 0 2006.238.07:40:12.55#ibcon#end of sib2, iclass 7, count 0 2006.238.07:40:12.55#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:40:12.55#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:40:12.55#ibcon#[27=USB\r\n] 2006.238.07:40:12.55#ibcon#*before write, iclass 7, count 0 2006.238.07:40:12.55#ibcon#enter sib2, iclass 7, count 0 2006.238.07:40:12.55#ibcon#flushed, iclass 7, count 0 2006.238.07:40:12.55#ibcon#about to write, iclass 7, count 0 2006.238.07:40:12.55#ibcon#wrote, iclass 7, count 0 2006.238.07:40:12.55#ibcon#about to read 3, iclass 7, count 0 2006.238.07:40:12.58#ibcon#read 3, iclass 7, count 0 2006.238.07:40:12.58#ibcon#about to read 4, iclass 7, count 0 2006.238.07:40:12.58#ibcon#read 4, iclass 7, count 0 2006.238.07:40:12.58#ibcon#about to read 5, iclass 7, count 0 2006.238.07:40:12.58#ibcon#read 5, iclass 7, count 0 2006.238.07:40:12.58#ibcon#about to read 6, iclass 7, count 0 2006.238.07:40:12.58#ibcon#read 6, iclass 7, count 0 2006.238.07:40:12.58#ibcon#end of sib2, iclass 7, count 0 2006.238.07:40:12.58#ibcon#*after write, iclass 7, count 0 2006.238.07:40:12.58#ibcon#*before return 0, iclass 7, count 0 2006.238.07:40:12.58#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:40:12.58#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:40:12.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:40:12.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:40:12.58$vc4f8/vabw=wide 2006.238.07:40:12.58#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.07:40:12.58#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.07:40:12.58#ibcon#ireg 8 cls_cnt 0 2006.238.07:40:12.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:40:12.58#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:40:12.58#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:40:12.58#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:40:12.58#ibcon#first serial, iclass 11, count 0 2006.238.07:40:12.58#ibcon#enter sib2, iclass 11, count 0 2006.238.07:40:12.58#ibcon#flushed, iclass 11, count 0 2006.238.07:40:12.58#ibcon#about to write, iclass 11, count 0 2006.238.07:40:12.58#ibcon#wrote, iclass 11, count 0 2006.238.07:40:12.58#ibcon#about to read 3, iclass 11, count 0 2006.238.07:40:12.60#ibcon#read 3, iclass 11, count 0 2006.238.07:40:12.60#ibcon#about to read 4, iclass 11, count 0 2006.238.07:40:12.60#ibcon#read 4, iclass 11, count 0 2006.238.07:40:12.60#ibcon#about to read 5, iclass 11, count 0 2006.238.07:40:12.60#ibcon#read 5, iclass 11, count 0 2006.238.07:40:12.60#ibcon#about to read 6, iclass 11, count 0 2006.238.07:40:12.60#ibcon#read 6, iclass 11, count 0 2006.238.07:40:12.60#ibcon#end of sib2, iclass 11, count 0 2006.238.07:40:12.60#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:40:12.60#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:40:12.60#ibcon#[25=BW32\r\n] 2006.238.07:40:12.60#ibcon#*before write, iclass 11, count 0 2006.238.07:40:12.60#ibcon#enter sib2, iclass 11, count 0 2006.238.07:40:12.60#ibcon#flushed, iclass 11, count 0 2006.238.07:40:12.60#ibcon#about to write, iclass 11, count 0 2006.238.07:40:12.60#ibcon#wrote, iclass 11, count 0 2006.238.07:40:12.60#ibcon#about to read 3, iclass 11, count 0 2006.238.07:40:12.63#ibcon#read 3, iclass 11, count 0 2006.238.07:40:12.63#ibcon#about to read 4, iclass 11, count 0 2006.238.07:40:12.63#ibcon#read 4, iclass 11, count 0 2006.238.07:40:12.63#ibcon#about to read 5, iclass 11, count 0 2006.238.07:40:12.63#ibcon#read 5, iclass 11, count 0 2006.238.07:40:12.63#ibcon#about to read 6, iclass 11, count 0 2006.238.07:40:12.63#ibcon#read 6, iclass 11, count 0 2006.238.07:40:12.63#ibcon#end of sib2, iclass 11, count 0 2006.238.07:40:12.63#ibcon#*after write, iclass 11, count 0 2006.238.07:40:12.63#ibcon#*before return 0, iclass 11, count 0 2006.238.07:40:12.63#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:40:12.63#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:40:12.63#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:40:12.63#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:40:12.63$vc4f8/vbbw=wide 2006.238.07:40:12.63#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.07:40:12.63#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.07:40:12.63#ibcon#ireg 8 cls_cnt 0 2006.238.07:40:12.63#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:40:12.70#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:40:12.70#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:40:12.70#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:40:12.70#ibcon#first serial, iclass 13, count 0 2006.238.07:40:12.70#ibcon#enter sib2, iclass 13, count 0 2006.238.07:40:12.70#ibcon#flushed, iclass 13, count 0 2006.238.07:40:12.70#ibcon#about to write, iclass 13, count 0 2006.238.07:40:12.70#ibcon#wrote, iclass 13, count 0 2006.238.07:40:12.70#ibcon#about to read 3, iclass 13, count 0 2006.238.07:40:12.72#ibcon#read 3, iclass 13, count 0 2006.238.07:40:12.72#ibcon#about to read 4, iclass 13, count 0 2006.238.07:40:12.72#ibcon#read 4, iclass 13, count 0 2006.238.07:40:12.72#ibcon#about to read 5, iclass 13, count 0 2006.238.07:40:12.72#ibcon#read 5, iclass 13, count 0 2006.238.07:40:12.72#ibcon#about to read 6, iclass 13, count 0 2006.238.07:40:12.72#ibcon#read 6, iclass 13, count 0 2006.238.07:40:12.72#ibcon#end of sib2, iclass 13, count 0 2006.238.07:40:12.72#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:40:12.72#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:40:12.72#ibcon#[27=BW32\r\n] 2006.238.07:40:12.72#ibcon#*before write, iclass 13, count 0 2006.238.07:40:12.72#ibcon#enter sib2, iclass 13, count 0 2006.238.07:40:12.72#ibcon#flushed, iclass 13, count 0 2006.238.07:40:12.72#ibcon#about to write, iclass 13, count 0 2006.238.07:40:12.72#ibcon#wrote, iclass 13, count 0 2006.238.07:40:12.72#ibcon#about to read 3, iclass 13, count 0 2006.238.07:40:12.75#ibcon#read 3, iclass 13, count 0 2006.238.07:40:12.75#ibcon#about to read 4, iclass 13, count 0 2006.238.07:40:12.75#ibcon#read 4, iclass 13, count 0 2006.238.07:40:12.75#ibcon#about to read 5, iclass 13, count 0 2006.238.07:40:12.75#ibcon#read 5, iclass 13, count 0 2006.238.07:40:12.75#ibcon#about to read 6, iclass 13, count 0 2006.238.07:40:12.75#ibcon#read 6, iclass 13, count 0 2006.238.07:40:12.75#ibcon#end of sib2, iclass 13, count 0 2006.238.07:40:12.75#ibcon#*after write, iclass 13, count 0 2006.238.07:40:12.75#ibcon#*before return 0, iclass 13, count 0 2006.238.07:40:12.75#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:40:12.75#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:40:12.75#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:40:12.75#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:40:12.75$4f8m12a/ifd4f 2006.238.07:40:12.75$ifd4f/lo= 2006.238.07:40:12.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:40:12.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:40:12.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:40:12.75$ifd4f/patch= 2006.238.07:40:12.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:40:12.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:40:12.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:40:12.75$4f8m12a/"form=m,16.000,1:2 2006.238.07:40:12.75$4f8m12a/"tpicd 2006.238.07:40:12.75$4f8m12a/echo=off 2006.238.07:40:12.75$4f8m12a/xlog=off 2006.238.07:40:12.75:!2006.238.07:40:40 2006.238.07:40:27.14#trakl#Source acquired 2006.238.07:40:28.14#flagr#flagr/antenna,acquired 2006.238.07:40:40.00:preob 2006.238.07:40:41.14/onsource/TRACKING 2006.238.07:40:41.14:!2006.238.07:40:50 2006.238.07:40:50.00:data_valid=on 2006.238.07:40:50.00:midob 2006.238.07:40:50.14/onsource/TRACKING 2006.238.07:40:50.14/wx/25.31,1012.2,87 2006.238.07:40:50.21/cable/+6.4190E-03 2006.238.07:40:51.30/va/01,08,usb,yes,34,35 2006.238.07:40:51.30/va/02,07,usb,yes,34,35 2006.238.07:40:51.30/va/03,07,usb,yes,32,32 2006.238.07:40:51.30/va/04,07,usb,yes,35,38 2006.238.07:40:51.30/va/05,08,usb,yes,33,34 2006.238.07:40:51.30/va/06,07,usb,yes,35,35 2006.238.07:40:51.30/va/07,07,usb,yes,35,35 2006.238.07:40:51.30/va/08,07,usb,yes,38,38 2006.238.07:40:51.53/valo/01,532.99,yes,locked 2006.238.07:40:51.53/valo/02,572.99,yes,locked 2006.238.07:40:51.53/valo/03,672.99,yes,locked 2006.238.07:40:51.53/valo/04,832.99,yes,locked 2006.238.07:40:51.53/valo/05,652.99,yes,locked 2006.238.07:40:51.53/valo/06,772.99,yes,locked 2006.238.07:40:51.53/valo/07,832.99,yes,locked 2006.238.07:40:51.53/valo/08,852.99,yes,locked 2006.238.07:40:52.62/vb/01,04,usb,yes,32,31 2006.238.07:40:52.62/vb/02,04,usb,yes,34,35 2006.238.07:40:52.62/vb/03,04,usb,yes,30,34 2006.238.07:40:52.62/vb/04,04,usb,yes,31,31 2006.238.07:40:52.62/vb/05,04,usb,yes,29,34 2006.238.07:40:52.62/vb/06,04,usb,yes,30,34 2006.238.07:40:52.62/vb/07,04,usb,yes,33,33 2006.238.07:40:52.62/vb/08,04,usb,yes,30,34 2006.238.07:40:52.86/vblo/01,632.99,yes,locked 2006.238.07:40:52.86/vblo/02,640.99,yes,locked 2006.238.07:40:52.86/vblo/03,656.99,yes,locked 2006.238.07:40:52.86/vblo/04,712.99,yes,locked 2006.238.07:40:52.86/vblo/05,744.99,yes,locked 2006.238.07:40:52.86/vblo/06,752.99,yes,locked 2006.238.07:40:52.86/vblo/07,734.99,yes,locked 2006.238.07:40:52.86/vblo/08,744.99,yes,locked 2006.238.07:40:53.01/vabw/8 2006.238.07:40:53.16/vbbw/8 2006.238.07:40:53.25/xfe/off,on,13.2 2006.238.07:40:53.63/ifatt/23,28,28,28 2006.238.07:40:54.08/fmout-gps/S +4.37E-07 2006.238.07:40:54.12:!2006.238.07:41:50 2006.238.07:41:50.01:data_valid=off 2006.238.07:41:50.01:postob 2006.238.07:41:50.25/cable/+6.4181E-03 2006.238.07:41:50.25/wx/25.30,1012.2,87 2006.238.07:41:51.08/fmout-gps/S +4.37E-07 2006.238.07:41:51.08:scan_name=238-0742,k06238,60 2006.238.07:41:51.09:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.238.07:41:51.14#flagr#flagr/antenna,new-source 2006.238.07:41:52.14:checkk5 2006.238.07:41:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:41:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:41:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:41:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:41:54.01/chk_obsdata//k5ts1/T2380740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:41:54.39/chk_obsdata//k5ts2/T2380740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:41:54.76/chk_obsdata//k5ts3/T2380740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:41:55.13/chk_obsdata//k5ts4/T2380740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:41:55.82/k5log//k5ts1_log_newline 2006.238.07:41:56.51/k5log//k5ts2_log_newline 2006.238.07:41:57.20/k5log//k5ts3_log_newline 2006.238.07:41:57.90/k5log//k5ts4_log_newline 2006.238.07:41:57.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:41:57.92:4f8m12a=1 2006.238.07:41:57.92$4f8m12a/echo=on 2006.238.07:41:57.92$4f8m12a/pcalon 2006.238.07:41:57.92$pcalon/"no phase cal control is implemented here 2006.238.07:41:57.92$4f8m12a/"tpicd=stop 2006.238.07:41:57.92$4f8m12a/vc4f8 2006.238.07:41:57.92$vc4f8/valo=1,532.99 2006.238.07:41:57.92#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.07:41:57.92#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.07:41:57.92#ibcon#ireg 17 cls_cnt 0 2006.238.07:41:57.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:41:57.92#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:41:57.92#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:41:57.92#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:41:57.92#ibcon#first serial, iclass 24, count 0 2006.238.07:41:57.92#ibcon#enter sib2, iclass 24, count 0 2006.238.07:41:57.92#ibcon#flushed, iclass 24, count 0 2006.238.07:41:57.92#ibcon#about to write, iclass 24, count 0 2006.238.07:41:57.92#ibcon#wrote, iclass 24, count 0 2006.238.07:41:57.92#ibcon#about to read 3, iclass 24, count 0 2006.238.07:41:57.94#ibcon#read 3, iclass 24, count 0 2006.238.07:41:57.94#ibcon#about to read 4, iclass 24, count 0 2006.238.07:41:57.94#ibcon#read 4, iclass 24, count 0 2006.238.07:41:57.94#ibcon#about to read 5, iclass 24, count 0 2006.238.07:41:57.94#ibcon#read 5, iclass 24, count 0 2006.238.07:41:57.94#ibcon#about to read 6, iclass 24, count 0 2006.238.07:41:57.94#ibcon#read 6, iclass 24, count 0 2006.238.07:41:57.94#ibcon#end of sib2, iclass 24, count 0 2006.238.07:41:57.94#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:41:57.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:41:57.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:41:57.94#ibcon#*before write, iclass 24, count 0 2006.238.07:41:57.94#ibcon#enter sib2, iclass 24, count 0 2006.238.07:41:57.94#ibcon#flushed, iclass 24, count 0 2006.238.07:41:57.94#ibcon#about to write, iclass 24, count 0 2006.238.07:41:57.94#ibcon#wrote, iclass 24, count 0 2006.238.07:41:57.94#ibcon#about to read 3, iclass 24, count 0 2006.238.07:41:57.99#ibcon#read 3, iclass 24, count 0 2006.238.07:41:57.99#ibcon#about to read 4, iclass 24, count 0 2006.238.07:41:57.99#ibcon#read 4, iclass 24, count 0 2006.238.07:41:57.99#ibcon#about to read 5, iclass 24, count 0 2006.238.07:41:57.99#ibcon#read 5, iclass 24, count 0 2006.238.07:41:57.99#ibcon#about to read 6, iclass 24, count 0 2006.238.07:41:57.99#ibcon#read 6, iclass 24, count 0 2006.238.07:41:57.99#ibcon#end of sib2, iclass 24, count 0 2006.238.07:41:57.99#ibcon#*after write, iclass 24, count 0 2006.238.07:41:57.99#ibcon#*before return 0, iclass 24, count 0 2006.238.07:41:57.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:41:57.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:41:57.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:41:57.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:41:57.99$vc4f8/va=1,8 2006.238.07:41:57.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.238.07:41:57.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.238.07:41:57.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:41:57.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:41:57.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:41:57.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:41:57.99#ibcon#enter wrdev, iclass 26, count 2 2006.238.07:41:57.99#ibcon#first serial, iclass 26, count 2 2006.238.07:41:57.99#ibcon#enter sib2, iclass 26, count 2 2006.238.07:41:57.99#ibcon#flushed, iclass 26, count 2 2006.238.07:41:57.99#ibcon#about to write, iclass 26, count 2 2006.238.07:41:57.99#ibcon#wrote, iclass 26, count 2 2006.238.07:41:57.99#ibcon#about to read 3, iclass 26, count 2 2006.238.07:41:58.01#ibcon#read 3, iclass 26, count 2 2006.238.07:41:58.01#ibcon#about to read 4, iclass 26, count 2 2006.238.07:41:58.01#ibcon#read 4, iclass 26, count 2 2006.238.07:41:58.01#ibcon#about to read 5, iclass 26, count 2 2006.238.07:41:58.01#ibcon#read 5, iclass 26, count 2 2006.238.07:41:58.01#ibcon#about to read 6, iclass 26, count 2 2006.238.07:41:58.01#ibcon#read 6, iclass 26, count 2 2006.238.07:41:58.01#ibcon#end of sib2, iclass 26, count 2 2006.238.07:41:58.01#ibcon#*mode == 0, iclass 26, count 2 2006.238.07:41:58.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.238.07:41:58.01#ibcon#[25=AT01-08\r\n] 2006.238.07:41:58.01#ibcon#*before write, iclass 26, count 2 2006.238.07:41:58.01#ibcon#enter sib2, iclass 26, count 2 2006.238.07:41:58.01#ibcon#flushed, iclass 26, count 2 2006.238.07:41:58.01#ibcon#about to write, iclass 26, count 2 2006.238.07:41:58.01#ibcon#wrote, iclass 26, count 2 2006.238.07:41:58.01#ibcon#about to read 3, iclass 26, count 2 2006.238.07:41:58.04#ibcon#read 3, iclass 26, count 2 2006.238.07:41:58.04#ibcon#about to read 4, iclass 26, count 2 2006.238.07:41:58.04#ibcon#read 4, iclass 26, count 2 2006.238.07:41:58.04#ibcon#about to read 5, iclass 26, count 2 2006.238.07:41:58.04#ibcon#read 5, iclass 26, count 2 2006.238.07:41:58.04#ibcon#about to read 6, iclass 26, count 2 2006.238.07:41:58.04#ibcon#read 6, iclass 26, count 2 2006.238.07:41:58.04#ibcon#end of sib2, iclass 26, count 2 2006.238.07:41:58.04#ibcon#*after write, iclass 26, count 2 2006.238.07:41:58.04#ibcon#*before return 0, iclass 26, count 2 2006.238.07:41:58.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:41:58.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:41:58.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.238.07:41:58.04#ibcon#ireg 7 cls_cnt 0 2006.238.07:41:58.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:41:58.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:41:58.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:41:58.16#ibcon#enter wrdev, iclass 26, count 0 2006.238.07:41:58.16#ibcon#first serial, iclass 26, count 0 2006.238.07:41:58.16#ibcon#enter sib2, iclass 26, count 0 2006.238.07:41:58.16#ibcon#flushed, iclass 26, count 0 2006.238.07:41:58.16#ibcon#about to write, iclass 26, count 0 2006.238.07:41:58.16#ibcon#wrote, iclass 26, count 0 2006.238.07:41:58.16#ibcon#about to read 3, iclass 26, count 0 2006.238.07:41:58.18#ibcon#read 3, iclass 26, count 0 2006.238.07:41:58.18#ibcon#about to read 4, iclass 26, count 0 2006.238.07:41:58.18#ibcon#read 4, iclass 26, count 0 2006.238.07:41:58.18#ibcon#about to read 5, iclass 26, count 0 2006.238.07:41:58.18#ibcon#read 5, iclass 26, count 0 2006.238.07:41:58.18#ibcon#about to read 6, iclass 26, count 0 2006.238.07:41:58.18#ibcon#read 6, iclass 26, count 0 2006.238.07:41:58.18#ibcon#end of sib2, iclass 26, count 0 2006.238.07:41:58.18#ibcon#*mode == 0, iclass 26, count 0 2006.238.07:41:58.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.07:41:58.18#ibcon#[25=USB\r\n] 2006.238.07:41:58.18#ibcon#*before write, iclass 26, count 0 2006.238.07:41:58.18#ibcon#enter sib2, iclass 26, count 0 2006.238.07:41:58.18#ibcon#flushed, iclass 26, count 0 2006.238.07:41:58.18#ibcon#about to write, iclass 26, count 0 2006.238.07:41:58.18#ibcon#wrote, iclass 26, count 0 2006.238.07:41:58.18#ibcon#about to read 3, iclass 26, count 0 2006.238.07:41:58.21#ibcon#read 3, iclass 26, count 0 2006.238.07:41:58.21#ibcon#about to read 4, iclass 26, count 0 2006.238.07:41:58.21#ibcon#read 4, iclass 26, count 0 2006.238.07:41:58.21#ibcon#about to read 5, iclass 26, count 0 2006.238.07:41:58.21#ibcon#read 5, iclass 26, count 0 2006.238.07:41:58.21#ibcon#about to read 6, iclass 26, count 0 2006.238.07:41:58.21#ibcon#read 6, iclass 26, count 0 2006.238.07:41:58.21#ibcon#end of sib2, iclass 26, count 0 2006.238.07:41:58.21#ibcon#*after write, iclass 26, count 0 2006.238.07:41:58.21#ibcon#*before return 0, iclass 26, count 0 2006.238.07:41:58.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:41:58.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:41:58.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.07:41:58.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.07:41:58.21$vc4f8/valo=2,572.99 2006.238.07:41:58.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.238.07:41:58.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.238.07:41:58.21#ibcon#ireg 17 cls_cnt 0 2006.238.07:41:58.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:41:58.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:41:58.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:41:58.21#ibcon#enter wrdev, iclass 28, count 0 2006.238.07:41:58.21#ibcon#first serial, iclass 28, count 0 2006.238.07:41:58.21#ibcon#enter sib2, iclass 28, count 0 2006.238.07:41:58.21#ibcon#flushed, iclass 28, count 0 2006.238.07:41:58.21#ibcon#about to write, iclass 28, count 0 2006.238.07:41:58.21#ibcon#wrote, iclass 28, count 0 2006.238.07:41:58.21#ibcon#about to read 3, iclass 28, count 0 2006.238.07:41:58.23#ibcon#read 3, iclass 28, count 0 2006.238.07:41:58.23#ibcon#about to read 4, iclass 28, count 0 2006.238.07:41:58.23#ibcon#read 4, iclass 28, count 0 2006.238.07:41:58.23#ibcon#about to read 5, iclass 28, count 0 2006.238.07:41:58.23#ibcon#read 5, iclass 28, count 0 2006.238.07:41:58.23#ibcon#about to read 6, iclass 28, count 0 2006.238.07:41:58.23#ibcon#read 6, iclass 28, count 0 2006.238.07:41:58.23#ibcon#end of sib2, iclass 28, count 0 2006.238.07:41:58.23#ibcon#*mode == 0, iclass 28, count 0 2006.238.07:41:58.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.07:41:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:41:58.23#ibcon#*before write, iclass 28, count 0 2006.238.07:41:58.23#ibcon#enter sib2, iclass 28, count 0 2006.238.07:41:58.23#ibcon#flushed, iclass 28, count 0 2006.238.07:41:58.23#ibcon#about to write, iclass 28, count 0 2006.238.07:41:58.23#ibcon#wrote, iclass 28, count 0 2006.238.07:41:58.23#ibcon#about to read 3, iclass 28, count 0 2006.238.07:41:58.27#ibcon#read 3, iclass 28, count 0 2006.238.07:41:58.27#ibcon#about to read 4, iclass 28, count 0 2006.238.07:41:58.27#ibcon#read 4, iclass 28, count 0 2006.238.07:41:58.27#ibcon#about to read 5, iclass 28, count 0 2006.238.07:41:58.27#ibcon#read 5, iclass 28, count 0 2006.238.07:41:58.27#ibcon#about to read 6, iclass 28, count 0 2006.238.07:41:58.27#ibcon#read 6, iclass 28, count 0 2006.238.07:41:58.27#ibcon#end of sib2, iclass 28, count 0 2006.238.07:41:58.27#ibcon#*after write, iclass 28, count 0 2006.238.07:41:58.27#ibcon#*before return 0, iclass 28, count 0 2006.238.07:41:58.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:41:58.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:41:58.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.07:41:58.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.07:41:58.27$vc4f8/va=2,7 2006.238.07:41:58.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.238.07:41:58.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.238.07:41:58.27#ibcon#ireg 11 cls_cnt 2 2006.238.07:41:58.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:41:58.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:41:58.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:41:58.33#ibcon#enter wrdev, iclass 30, count 2 2006.238.07:41:58.33#ibcon#first serial, iclass 30, count 2 2006.238.07:41:58.33#ibcon#enter sib2, iclass 30, count 2 2006.238.07:41:58.33#ibcon#flushed, iclass 30, count 2 2006.238.07:41:58.33#ibcon#about to write, iclass 30, count 2 2006.238.07:41:58.33#ibcon#wrote, iclass 30, count 2 2006.238.07:41:58.33#ibcon#about to read 3, iclass 30, count 2 2006.238.07:41:58.35#ibcon#read 3, iclass 30, count 2 2006.238.07:41:58.35#ibcon#about to read 4, iclass 30, count 2 2006.238.07:41:58.35#ibcon#read 4, iclass 30, count 2 2006.238.07:41:58.35#ibcon#about to read 5, iclass 30, count 2 2006.238.07:41:58.35#ibcon#read 5, iclass 30, count 2 2006.238.07:41:58.35#ibcon#about to read 6, iclass 30, count 2 2006.238.07:41:58.35#ibcon#read 6, iclass 30, count 2 2006.238.07:41:58.35#ibcon#end of sib2, iclass 30, count 2 2006.238.07:41:58.35#ibcon#*mode == 0, iclass 30, count 2 2006.238.07:41:58.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.238.07:41:58.35#ibcon#[25=AT02-07\r\n] 2006.238.07:41:58.35#ibcon#*before write, iclass 30, count 2 2006.238.07:41:58.35#ibcon#enter sib2, iclass 30, count 2 2006.238.07:41:58.35#ibcon#flushed, iclass 30, count 2 2006.238.07:41:58.35#ibcon#about to write, iclass 30, count 2 2006.238.07:41:58.35#ibcon#wrote, iclass 30, count 2 2006.238.07:41:58.35#ibcon#about to read 3, iclass 30, count 2 2006.238.07:41:58.38#ibcon#read 3, iclass 30, count 2 2006.238.07:41:58.38#ibcon#about to read 4, iclass 30, count 2 2006.238.07:41:58.38#ibcon#read 4, iclass 30, count 2 2006.238.07:41:58.38#ibcon#about to read 5, iclass 30, count 2 2006.238.07:41:58.38#ibcon#read 5, iclass 30, count 2 2006.238.07:41:58.38#ibcon#about to read 6, iclass 30, count 2 2006.238.07:41:58.38#ibcon#read 6, iclass 30, count 2 2006.238.07:41:58.38#ibcon#end of sib2, iclass 30, count 2 2006.238.07:41:58.38#ibcon#*after write, iclass 30, count 2 2006.238.07:41:58.38#ibcon#*before return 0, iclass 30, count 2 2006.238.07:41:58.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:41:58.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:41:58.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.238.07:41:58.38#ibcon#ireg 7 cls_cnt 0 2006.238.07:41:58.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:41:58.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:41:58.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:41:58.50#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:41:58.50#ibcon#first serial, iclass 30, count 0 2006.238.07:41:58.50#ibcon#enter sib2, iclass 30, count 0 2006.238.07:41:58.50#ibcon#flushed, iclass 30, count 0 2006.238.07:41:58.50#ibcon#about to write, iclass 30, count 0 2006.238.07:41:58.50#ibcon#wrote, iclass 30, count 0 2006.238.07:41:58.50#ibcon#about to read 3, iclass 30, count 0 2006.238.07:41:58.52#ibcon#read 3, iclass 30, count 0 2006.238.07:41:58.52#ibcon#about to read 4, iclass 30, count 0 2006.238.07:41:58.52#ibcon#read 4, iclass 30, count 0 2006.238.07:41:58.52#ibcon#about to read 5, iclass 30, count 0 2006.238.07:41:58.52#ibcon#read 5, iclass 30, count 0 2006.238.07:41:58.52#ibcon#about to read 6, iclass 30, count 0 2006.238.07:41:58.52#ibcon#read 6, iclass 30, count 0 2006.238.07:41:58.52#ibcon#end of sib2, iclass 30, count 0 2006.238.07:41:58.52#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:41:58.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:41:58.52#ibcon#[25=USB\r\n] 2006.238.07:41:58.52#ibcon#*before write, iclass 30, count 0 2006.238.07:41:58.52#ibcon#enter sib2, iclass 30, count 0 2006.238.07:41:58.52#ibcon#flushed, iclass 30, count 0 2006.238.07:41:58.52#ibcon#about to write, iclass 30, count 0 2006.238.07:41:58.52#ibcon#wrote, iclass 30, count 0 2006.238.07:41:58.52#ibcon#about to read 3, iclass 30, count 0 2006.238.07:41:58.55#ibcon#read 3, iclass 30, count 0 2006.238.07:41:58.55#ibcon#about to read 4, iclass 30, count 0 2006.238.07:41:58.55#ibcon#read 4, iclass 30, count 0 2006.238.07:41:58.55#ibcon#about to read 5, iclass 30, count 0 2006.238.07:41:58.55#ibcon#read 5, iclass 30, count 0 2006.238.07:41:58.55#ibcon#about to read 6, iclass 30, count 0 2006.238.07:41:58.55#ibcon#read 6, iclass 30, count 0 2006.238.07:41:58.55#ibcon#end of sib2, iclass 30, count 0 2006.238.07:41:58.55#ibcon#*after write, iclass 30, count 0 2006.238.07:41:58.55#ibcon#*before return 0, iclass 30, count 0 2006.238.07:41:58.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:41:58.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:41:58.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:41:58.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:41:58.55$vc4f8/valo=3,672.99 2006.238.07:41:58.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.07:41:58.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.07:41:58.55#ibcon#ireg 17 cls_cnt 0 2006.238.07:41:58.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:41:58.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:41:58.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:41:58.55#ibcon#enter wrdev, iclass 32, count 0 2006.238.07:41:58.55#ibcon#first serial, iclass 32, count 0 2006.238.07:41:58.55#ibcon#enter sib2, iclass 32, count 0 2006.238.07:41:58.55#ibcon#flushed, iclass 32, count 0 2006.238.07:41:58.55#ibcon#about to write, iclass 32, count 0 2006.238.07:41:58.55#ibcon#wrote, iclass 32, count 0 2006.238.07:41:58.55#ibcon#about to read 3, iclass 32, count 0 2006.238.07:41:58.57#ibcon#read 3, iclass 32, count 0 2006.238.07:41:58.57#ibcon#about to read 4, iclass 32, count 0 2006.238.07:41:58.57#ibcon#read 4, iclass 32, count 0 2006.238.07:41:58.57#ibcon#about to read 5, iclass 32, count 0 2006.238.07:41:58.57#ibcon#read 5, iclass 32, count 0 2006.238.07:41:58.57#ibcon#about to read 6, iclass 32, count 0 2006.238.07:41:58.57#ibcon#read 6, iclass 32, count 0 2006.238.07:41:58.57#ibcon#end of sib2, iclass 32, count 0 2006.238.07:41:58.57#ibcon#*mode == 0, iclass 32, count 0 2006.238.07:41:58.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.07:41:58.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:41:58.57#ibcon#*before write, iclass 32, count 0 2006.238.07:41:58.57#ibcon#enter sib2, iclass 32, count 0 2006.238.07:41:58.57#ibcon#flushed, iclass 32, count 0 2006.238.07:41:58.57#ibcon#about to write, iclass 32, count 0 2006.238.07:41:58.57#ibcon#wrote, iclass 32, count 0 2006.238.07:41:58.57#ibcon#about to read 3, iclass 32, count 0 2006.238.07:41:58.61#ibcon#read 3, iclass 32, count 0 2006.238.07:41:58.61#ibcon#about to read 4, iclass 32, count 0 2006.238.07:41:58.61#ibcon#read 4, iclass 32, count 0 2006.238.07:41:58.61#ibcon#about to read 5, iclass 32, count 0 2006.238.07:41:58.61#ibcon#read 5, iclass 32, count 0 2006.238.07:41:58.61#ibcon#about to read 6, iclass 32, count 0 2006.238.07:41:58.61#ibcon#read 6, iclass 32, count 0 2006.238.07:41:58.61#ibcon#end of sib2, iclass 32, count 0 2006.238.07:41:58.61#ibcon#*after write, iclass 32, count 0 2006.238.07:41:58.61#ibcon#*before return 0, iclass 32, count 0 2006.238.07:41:58.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:41:58.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:41:58.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.07:41:58.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.07:41:58.61$vc4f8/va=3,7 2006.238.07:41:58.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.238.07:41:58.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.238.07:41:58.61#ibcon#ireg 11 cls_cnt 2 2006.238.07:41:58.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:41:58.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:41:58.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:41:58.68#ibcon#enter wrdev, iclass 34, count 2 2006.238.07:41:58.68#ibcon#first serial, iclass 34, count 2 2006.238.07:41:58.68#ibcon#enter sib2, iclass 34, count 2 2006.238.07:41:58.68#ibcon#flushed, iclass 34, count 2 2006.238.07:41:58.68#ibcon#about to write, iclass 34, count 2 2006.238.07:41:58.68#ibcon#wrote, iclass 34, count 2 2006.238.07:41:58.68#ibcon#about to read 3, iclass 34, count 2 2006.238.07:41:58.69#ibcon#read 3, iclass 34, count 2 2006.238.07:41:58.69#ibcon#about to read 4, iclass 34, count 2 2006.238.07:41:58.69#ibcon#read 4, iclass 34, count 2 2006.238.07:41:58.69#ibcon#about to read 5, iclass 34, count 2 2006.238.07:41:58.69#ibcon#read 5, iclass 34, count 2 2006.238.07:41:58.69#ibcon#about to read 6, iclass 34, count 2 2006.238.07:41:58.69#ibcon#read 6, iclass 34, count 2 2006.238.07:41:58.69#ibcon#end of sib2, iclass 34, count 2 2006.238.07:41:58.69#ibcon#*mode == 0, iclass 34, count 2 2006.238.07:41:58.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.238.07:41:58.69#ibcon#[25=AT03-07\r\n] 2006.238.07:41:58.69#ibcon#*before write, iclass 34, count 2 2006.238.07:41:58.69#ibcon#enter sib2, iclass 34, count 2 2006.238.07:41:58.69#ibcon#flushed, iclass 34, count 2 2006.238.07:41:58.69#ibcon#about to write, iclass 34, count 2 2006.238.07:41:58.69#ibcon#wrote, iclass 34, count 2 2006.238.07:41:58.69#ibcon#about to read 3, iclass 34, count 2 2006.238.07:41:58.72#ibcon#read 3, iclass 34, count 2 2006.238.07:41:58.72#ibcon#about to read 4, iclass 34, count 2 2006.238.07:41:58.72#ibcon#read 4, iclass 34, count 2 2006.238.07:41:58.72#ibcon#about to read 5, iclass 34, count 2 2006.238.07:41:58.72#ibcon#read 5, iclass 34, count 2 2006.238.07:41:58.72#ibcon#about to read 6, iclass 34, count 2 2006.238.07:41:58.72#ibcon#read 6, iclass 34, count 2 2006.238.07:41:58.72#ibcon#end of sib2, iclass 34, count 2 2006.238.07:41:58.72#ibcon#*after write, iclass 34, count 2 2006.238.07:41:58.72#ibcon#*before return 0, iclass 34, count 2 2006.238.07:41:58.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:41:58.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:41:58.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.238.07:41:58.72#ibcon#ireg 7 cls_cnt 0 2006.238.07:41:58.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:41:58.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:41:58.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:41:58.84#ibcon#enter wrdev, iclass 34, count 0 2006.238.07:41:58.84#ibcon#first serial, iclass 34, count 0 2006.238.07:41:58.84#ibcon#enter sib2, iclass 34, count 0 2006.238.07:41:58.84#ibcon#flushed, iclass 34, count 0 2006.238.07:41:58.84#ibcon#about to write, iclass 34, count 0 2006.238.07:41:58.84#ibcon#wrote, iclass 34, count 0 2006.238.07:41:58.84#ibcon#about to read 3, iclass 34, count 0 2006.238.07:41:58.86#ibcon#read 3, iclass 34, count 0 2006.238.07:41:58.86#ibcon#about to read 4, iclass 34, count 0 2006.238.07:41:58.86#ibcon#read 4, iclass 34, count 0 2006.238.07:41:58.86#ibcon#about to read 5, iclass 34, count 0 2006.238.07:41:58.86#ibcon#read 5, iclass 34, count 0 2006.238.07:41:58.86#ibcon#about to read 6, iclass 34, count 0 2006.238.07:41:58.86#ibcon#read 6, iclass 34, count 0 2006.238.07:41:58.86#ibcon#end of sib2, iclass 34, count 0 2006.238.07:41:58.86#ibcon#*mode == 0, iclass 34, count 0 2006.238.07:41:58.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.07:41:58.86#ibcon#[25=USB\r\n] 2006.238.07:41:58.86#ibcon#*before write, iclass 34, count 0 2006.238.07:41:58.86#ibcon#enter sib2, iclass 34, count 0 2006.238.07:41:58.86#ibcon#flushed, iclass 34, count 0 2006.238.07:41:58.86#ibcon#about to write, iclass 34, count 0 2006.238.07:41:58.86#ibcon#wrote, iclass 34, count 0 2006.238.07:41:58.86#ibcon#about to read 3, iclass 34, count 0 2006.238.07:41:58.89#ibcon#read 3, iclass 34, count 0 2006.238.07:41:58.89#ibcon#about to read 4, iclass 34, count 0 2006.238.07:41:58.89#ibcon#read 4, iclass 34, count 0 2006.238.07:41:58.89#ibcon#about to read 5, iclass 34, count 0 2006.238.07:41:58.89#ibcon#read 5, iclass 34, count 0 2006.238.07:41:58.89#ibcon#about to read 6, iclass 34, count 0 2006.238.07:41:58.89#ibcon#read 6, iclass 34, count 0 2006.238.07:41:58.89#ibcon#end of sib2, iclass 34, count 0 2006.238.07:41:58.89#ibcon#*after write, iclass 34, count 0 2006.238.07:41:58.89#ibcon#*before return 0, iclass 34, count 0 2006.238.07:41:58.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:41:58.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:41:58.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.07:41:58.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.07:41:58.89$vc4f8/valo=4,832.99 2006.238.07:41:58.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.07:41:58.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.07:41:58.89#ibcon#ireg 17 cls_cnt 0 2006.238.07:41:58.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:41:58.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:41:58.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:41:58.89#ibcon#enter wrdev, iclass 36, count 0 2006.238.07:41:58.89#ibcon#first serial, iclass 36, count 0 2006.238.07:41:58.89#ibcon#enter sib2, iclass 36, count 0 2006.238.07:41:58.89#ibcon#flushed, iclass 36, count 0 2006.238.07:41:58.89#ibcon#about to write, iclass 36, count 0 2006.238.07:41:58.89#ibcon#wrote, iclass 36, count 0 2006.238.07:41:58.89#ibcon#about to read 3, iclass 36, count 0 2006.238.07:41:58.91#ibcon#read 3, iclass 36, count 0 2006.238.07:41:58.91#ibcon#about to read 4, iclass 36, count 0 2006.238.07:41:58.91#ibcon#read 4, iclass 36, count 0 2006.238.07:41:58.91#ibcon#about to read 5, iclass 36, count 0 2006.238.07:41:58.91#ibcon#read 5, iclass 36, count 0 2006.238.07:41:58.91#ibcon#about to read 6, iclass 36, count 0 2006.238.07:41:58.91#ibcon#read 6, iclass 36, count 0 2006.238.07:41:58.91#ibcon#end of sib2, iclass 36, count 0 2006.238.07:41:58.91#ibcon#*mode == 0, iclass 36, count 0 2006.238.07:41:58.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.07:41:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:41:58.91#ibcon#*before write, iclass 36, count 0 2006.238.07:41:58.91#ibcon#enter sib2, iclass 36, count 0 2006.238.07:41:58.91#ibcon#flushed, iclass 36, count 0 2006.238.07:41:58.91#ibcon#about to write, iclass 36, count 0 2006.238.07:41:58.91#ibcon#wrote, iclass 36, count 0 2006.238.07:41:58.91#ibcon#about to read 3, iclass 36, count 0 2006.238.07:41:58.95#ibcon#read 3, iclass 36, count 0 2006.238.07:41:58.95#ibcon#about to read 4, iclass 36, count 0 2006.238.07:41:58.95#ibcon#read 4, iclass 36, count 0 2006.238.07:41:58.95#ibcon#about to read 5, iclass 36, count 0 2006.238.07:41:58.95#ibcon#read 5, iclass 36, count 0 2006.238.07:41:58.95#ibcon#about to read 6, iclass 36, count 0 2006.238.07:41:58.95#ibcon#read 6, iclass 36, count 0 2006.238.07:41:58.95#ibcon#end of sib2, iclass 36, count 0 2006.238.07:41:58.95#ibcon#*after write, iclass 36, count 0 2006.238.07:41:58.95#ibcon#*before return 0, iclass 36, count 0 2006.238.07:41:58.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:41:58.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:41:58.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.07:41:58.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.07:41:58.95$vc4f8/va=4,7 2006.238.07:41:58.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.238.07:41:58.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.238.07:41:58.95#ibcon#ireg 11 cls_cnt 2 2006.238.07:41:58.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:41:59.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:41:59.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:41:59.01#ibcon#enter wrdev, iclass 38, count 2 2006.238.07:41:59.01#ibcon#first serial, iclass 38, count 2 2006.238.07:41:59.01#ibcon#enter sib2, iclass 38, count 2 2006.238.07:41:59.01#ibcon#flushed, iclass 38, count 2 2006.238.07:41:59.01#ibcon#about to write, iclass 38, count 2 2006.238.07:41:59.01#ibcon#wrote, iclass 38, count 2 2006.238.07:41:59.01#ibcon#about to read 3, iclass 38, count 2 2006.238.07:41:59.03#ibcon#read 3, iclass 38, count 2 2006.238.07:41:59.03#ibcon#about to read 4, iclass 38, count 2 2006.238.07:41:59.03#ibcon#read 4, iclass 38, count 2 2006.238.07:41:59.03#ibcon#about to read 5, iclass 38, count 2 2006.238.07:41:59.03#ibcon#read 5, iclass 38, count 2 2006.238.07:41:59.03#ibcon#about to read 6, iclass 38, count 2 2006.238.07:41:59.03#ibcon#read 6, iclass 38, count 2 2006.238.07:41:59.03#ibcon#end of sib2, iclass 38, count 2 2006.238.07:41:59.03#ibcon#*mode == 0, iclass 38, count 2 2006.238.07:41:59.03#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.238.07:41:59.03#ibcon#[25=AT04-07\r\n] 2006.238.07:41:59.03#ibcon#*before write, iclass 38, count 2 2006.238.07:41:59.03#ibcon#enter sib2, iclass 38, count 2 2006.238.07:41:59.03#ibcon#flushed, iclass 38, count 2 2006.238.07:41:59.03#ibcon#about to write, iclass 38, count 2 2006.238.07:41:59.03#ibcon#wrote, iclass 38, count 2 2006.238.07:41:59.03#ibcon#about to read 3, iclass 38, count 2 2006.238.07:41:59.06#ibcon#read 3, iclass 38, count 2 2006.238.07:41:59.06#ibcon#about to read 4, iclass 38, count 2 2006.238.07:41:59.06#ibcon#read 4, iclass 38, count 2 2006.238.07:41:59.06#ibcon#about to read 5, iclass 38, count 2 2006.238.07:41:59.06#ibcon#read 5, iclass 38, count 2 2006.238.07:41:59.06#ibcon#about to read 6, iclass 38, count 2 2006.238.07:41:59.06#ibcon#read 6, iclass 38, count 2 2006.238.07:41:59.06#ibcon#end of sib2, iclass 38, count 2 2006.238.07:41:59.06#ibcon#*after write, iclass 38, count 2 2006.238.07:41:59.06#ibcon#*before return 0, iclass 38, count 2 2006.238.07:41:59.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:41:59.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:41:59.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.238.07:41:59.06#ibcon#ireg 7 cls_cnt 0 2006.238.07:41:59.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:41:59.18#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:41:59.18#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:41:59.18#ibcon#enter wrdev, iclass 38, count 0 2006.238.07:41:59.18#ibcon#first serial, iclass 38, count 0 2006.238.07:41:59.18#ibcon#enter sib2, iclass 38, count 0 2006.238.07:41:59.18#ibcon#flushed, iclass 38, count 0 2006.238.07:41:59.18#ibcon#about to write, iclass 38, count 0 2006.238.07:41:59.18#ibcon#wrote, iclass 38, count 0 2006.238.07:41:59.18#ibcon#about to read 3, iclass 38, count 0 2006.238.07:41:59.22#ibcon#read 3, iclass 38, count 0 2006.238.07:41:59.22#ibcon#about to read 4, iclass 38, count 0 2006.238.07:41:59.22#ibcon#read 4, iclass 38, count 0 2006.238.07:41:59.22#ibcon#about to read 5, iclass 38, count 0 2006.238.07:41:59.22#ibcon#read 5, iclass 38, count 0 2006.238.07:41:59.22#ibcon#about to read 6, iclass 38, count 0 2006.238.07:41:59.22#ibcon#read 6, iclass 38, count 0 2006.238.07:41:59.22#ibcon#end of sib2, iclass 38, count 0 2006.238.07:41:59.22#ibcon#*mode == 0, iclass 38, count 0 2006.238.07:41:59.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.07:41:59.22#ibcon#[25=USB\r\n] 2006.238.07:41:59.22#ibcon#*before write, iclass 38, count 0 2006.238.07:41:59.22#ibcon#enter sib2, iclass 38, count 0 2006.238.07:41:59.22#ibcon#flushed, iclass 38, count 0 2006.238.07:41:59.22#ibcon#about to write, iclass 38, count 0 2006.238.07:41:59.22#ibcon#wrote, iclass 38, count 0 2006.238.07:41:59.22#ibcon#about to read 3, iclass 38, count 0 2006.238.07:41:59.25#ibcon#read 3, iclass 38, count 0 2006.238.07:41:59.25#ibcon#about to read 4, iclass 38, count 0 2006.238.07:41:59.25#ibcon#read 4, iclass 38, count 0 2006.238.07:41:59.25#ibcon#about to read 5, iclass 38, count 0 2006.238.07:41:59.25#ibcon#read 5, iclass 38, count 0 2006.238.07:41:59.25#ibcon#about to read 6, iclass 38, count 0 2006.238.07:41:59.25#ibcon#read 6, iclass 38, count 0 2006.238.07:41:59.25#ibcon#end of sib2, iclass 38, count 0 2006.238.07:41:59.25#ibcon#*after write, iclass 38, count 0 2006.238.07:41:59.25#ibcon#*before return 0, iclass 38, count 0 2006.238.07:41:59.25#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:41:59.25#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:41:59.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.07:41:59.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.07:41:59.25$vc4f8/valo=5,652.99 2006.238.07:41:59.25#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.07:41:59.25#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.07:41:59.25#ibcon#ireg 17 cls_cnt 0 2006.238.07:41:59.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:41:59.25#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:41:59.25#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:41:59.25#ibcon#enter wrdev, iclass 40, count 0 2006.238.07:41:59.25#ibcon#first serial, iclass 40, count 0 2006.238.07:41:59.25#ibcon#enter sib2, iclass 40, count 0 2006.238.07:41:59.25#ibcon#flushed, iclass 40, count 0 2006.238.07:41:59.25#ibcon#about to write, iclass 40, count 0 2006.238.07:41:59.25#ibcon#wrote, iclass 40, count 0 2006.238.07:41:59.25#ibcon#about to read 3, iclass 40, count 0 2006.238.07:41:59.27#ibcon#read 3, iclass 40, count 0 2006.238.07:41:59.27#ibcon#about to read 4, iclass 40, count 0 2006.238.07:41:59.27#ibcon#read 4, iclass 40, count 0 2006.238.07:41:59.27#ibcon#about to read 5, iclass 40, count 0 2006.238.07:41:59.27#ibcon#read 5, iclass 40, count 0 2006.238.07:41:59.27#ibcon#about to read 6, iclass 40, count 0 2006.238.07:41:59.27#ibcon#read 6, iclass 40, count 0 2006.238.07:41:59.27#ibcon#end of sib2, iclass 40, count 0 2006.238.07:41:59.27#ibcon#*mode == 0, iclass 40, count 0 2006.238.07:41:59.27#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.07:41:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:41:59.27#ibcon#*before write, iclass 40, count 0 2006.238.07:41:59.27#ibcon#enter sib2, iclass 40, count 0 2006.238.07:41:59.27#ibcon#flushed, iclass 40, count 0 2006.238.07:41:59.27#ibcon#about to write, iclass 40, count 0 2006.238.07:41:59.27#ibcon#wrote, iclass 40, count 0 2006.238.07:41:59.27#ibcon#about to read 3, iclass 40, count 0 2006.238.07:41:59.31#ibcon#read 3, iclass 40, count 0 2006.238.07:41:59.31#ibcon#about to read 4, iclass 40, count 0 2006.238.07:41:59.31#ibcon#read 4, iclass 40, count 0 2006.238.07:41:59.31#ibcon#about to read 5, iclass 40, count 0 2006.238.07:41:59.31#ibcon#read 5, iclass 40, count 0 2006.238.07:41:59.31#ibcon#about to read 6, iclass 40, count 0 2006.238.07:41:59.31#ibcon#read 6, iclass 40, count 0 2006.238.07:41:59.31#ibcon#end of sib2, iclass 40, count 0 2006.238.07:41:59.31#ibcon#*after write, iclass 40, count 0 2006.238.07:41:59.31#ibcon#*before return 0, iclass 40, count 0 2006.238.07:41:59.31#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:41:59.31#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:41:59.31#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.07:41:59.31#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.07:41:59.31$vc4f8/va=5,8 2006.238.07:41:59.31#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.238.07:41:59.31#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.238.07:41:59.31#ibcon#ireg 11 cls_cnt 2 2006.238.07:41:59.31#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:41:59.37#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:41:59.37#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:41:59.37#ibcon#enter wrdev, iclass 4, count 2 2006.238.07:41:59.37#ibcon#first serial, iclass 4, count 2 2006.238.07:41:59.37#ibcon#enter sib2, iclass 4, count 2 2006.238.07:41:59.37#ibcon#flushed, iclass 4, count 2 2006.238.07:41:59.37#ibcon#about to write, iclass 4, count 2 2006.238.07:41:59.37#ibcon#wrote, iclass 4, count 2 2006.238.07:41:59.37#ibcon#about to read 3, iclass 4, count 2 2006.238.07:41:59.39#ibcon#read 3, iclass 4, count 2 2006.238.07:41:59.39#ibcon#about to read 4, iclass 4, count 2 2006.238.07:41:59.39#ibcon#read 4, iclass 4, count 2 2006.238.07:41:59.39#ibcon#about to read 5, iclass 4, count 2 2006.238.07:41:59.39#ibcon#read 5, iclass 4, count 2 2006.238.07:41:59.39#ibcon#about to read 6, iclass 4, count 2 2006.238.07:41:59.39#ibcon#read 6, iclass 4, count 2 2006.238.07:41:59.39#ibcon#end of sib2, iclass 4, count 2 2006.238.07:41:59.39#ibcon#*mode == 0, iclass 4, count 2 2006.238.07:41:59.39#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.238.07:41:59.39#ibcon#[25=AT05-08\r\n] 2006.238.07:41:59.39#ibcon#*before write, iclass 4, count 2 2006.238.07:41:59.39#ibcon#enter sib2, iclass 4, count 2 2006.238.07:41:59.39#ibcon#flushed, iclass 4, count 2 2006.238.07:41:59.39#ibcon#about to write, iclass 4, count 2 2006.238.07:41:59.39#ibcon#wrote, iclass 4, count 2 2006.238.07:41:59.39#ibcon#about to read 3, iclass 4, count 2 2006.238.07:41:59.42#ibcon#read 3, iclass 4, count 2 2006.238.07:41:59.42#ibcon#about to read 4, iclass 4, count 2 2006.238.07:41:59.42#ibcon#read 4, iclass 4, count 2 2006.238.07:41:59.42#ibcon#about to read 5, iclass 4, count 2 2006.238.07:41:59.42#ibcon#read 5, iclass 4, count 2 2006.238.07:41:59.42#ibcon#about to read 6, iclass 4, count 2 2006.238.07:41:59.42#ibcon#read 6, iclass 4, count 2 2006.238.07:41:59.42#ibcon#end of sib2, iclass 4, count 2 2006.238.07:41:59.42#ibcon#*after write, iclass 4, count 2 2006.238.07:41:59.42#ibcon#*before return 0, iclass 4, count 2 2006.238.07:41:59.42#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:41:59.42#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:41:59.42#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.238.07:41:59.42#ibcon#ireg 7 cls_cnt 0 2006.238.07:41:59.42#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:41:59.54#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:41:59.54#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:41:59.54#ibcon#enter wrdev, iclass 4, count 0 2006.238.07:41:59.54#ibcon#first serial, iclass 4, count 0 2006.238.07:41:59.54#ibcon#enter sib2, iclass 4, count 0 2006.238.07:41:59.54#ibcon#flushed, iclass 4, count 0 2006.238.07:41:59.54#ibcon#about to write, iclass 4, count 0 2006.238.07:41:59.54#ibcon#wrote, iclass 4, count 0 2006.238.07:41:59.54#ibcon#about to read 3, iclass 4, count 0 2006.238.07:41:59.56#ibcon#read 3, iclass 4, count 0 2006.238.07:41:59.56#ibcon#about to read 4, iclass 4, count 0 2006.238.07:41:59.56#ibcon#read 4, iclass 4, count 0 2006.238.07:41:59.56#ibcon#about to read 5, iclass 4, count 0 2006.238.07:41:59.56#ibcon#read 5, iclass 4, count 0 2006.238.07:41:59.56#ibcon#about to read 6, iclass 4, count 0 2006.238.07:41:59.56#ibcon#read 6, iclass 4, count 0 2006.238.07:41:59.56#ibcon#end of sib2, iclass 4, count 0 2006.238.07:41:59.56#ibcon#*mode == 0, iclass 4, count 0 2006.238.07:41:59.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.07:41:59.56#ibcon#[25=USB\r\n] 2006.238.07:41:59.56#ibcon#*before write, iclass 4, count 0 2006.238.07:41:59.56#ibcon#enter sib2, iclass 4, count 0 2006.238.07:41:59.56#ibcon#flushed, iclass 4, count 0 2006.238.07:41:59.56#ibcon#about to write, iclass 4, count 0 2006.238.07:41:59.56#ibcon#wrote, iclass 4, count 0 2006.238.07:41:59.56#ibcon#about to read 3, iclass 4, count 0 2006.238.07:41:59.59#ibcon#read 3, iclass 4, count 0 2006.238.07:41:59.59#ibcon#about to read 4, iclass 4, count 0 2006.238.07:41:59.59#ibcon#read 4, iclass 4, count 0 2006.238.07:41:59.59#ibcon#about to read 5, iclass 4, count 0 2006.238.07:41:59.59#ibcon#read 5, iclass 4, count 0 2006.238.07:41:59.59#ibcon#about to read 6, iclass 4, count 0 2006.238.07:41:59.59#ibcon#read 6, iclass 4, count 0 2006.238.07:41:59.59#ibcon#end of sib2, iclass 4, count 0 2006.238.07:41:59.59#ibcon#*after write, iclass 4, count 0 2006.238.07:41:59.59#ibcon#*before return 0, iclass 4, count 0 2006.238.07:41:59.59#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:41:59.59#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:41:59.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.07:41:59.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.07:41:59.59$vc4f8/valo=6,772.99 2006.238.07:41:59.59#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.238.07:41:59.59#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.238.07:41:59.59#ibcon#ireg 17 cls_cnt 0 2006.238.07:41:59.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:41:59.59#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:41:59.59#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:41:59.59#ibcon#enter wrdev, iclass 6, count 0 2006.238.07:41:59.59#ibcon#first serial, iclass 6, count 0 2006.238.07:41:59.59#ibcon#enter sib2, iclass 6, count 0 2006.238.07:41:59.59#ibcon#flushed, iclass 6, count 0 2006.238.07:41:59.59#ibcon#about to write, iclass 6, count 0 2006.238.07:41:59.59#ibcon#wrote, iclass 6, count 0 2006.238.07:41:59.59#ibcon#about to read 3, iclass 6, count 0 2006.238.07:41:59.61#ibcon#read 3, iclass 6, count 0 2006.238.07:41:59.61#ibcon#about to read 4, iclass 6, count 0 2006.238.07:41:59.61#ibcon#read 4, iclass 6, count 0 2006.238.07:41:59.61#ibcon#about to read 5, iclass 6, count 0 2006.238.07:41:59.61#ibcon#read 5, iclass 6, count 0 2006.238.07:41:59.61#ibcon#about to read 6, iclass 6, count 0 2006.238.07:41:59.61#ibcon#read 6, iclass 6, count 0 2006.238.07:41:59.61#ibcon#end of sib2, iclass 6, count 0 2006.238.07:41:59.61#ibcon#*mode == 0, iclass 6, count 0 2006.238.07:41:59.61#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.07:41:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:41:59.61#ibcon#*before write, iclass 6, count 0 2006.238.07:41:59.61#ibcon#enter sib2, iclass 6, count 0 2006.238.07:41:59.61#ibcon#flushed, iclass 6, count 0 2006.238.07:41:59.61#ibcon#about to write, iclass 6, count 0 2006.238.07:41:59.61#ibcon#wrote, iclass 6, count 0 2006.238.07:41:59.61#ibcon#about to read 3, iclass 6, count 0 2006.238.07:41:59.65#ibcon#read 3, iclass 6, count 0 2006.238.07:41:59.65#ibcon#about to read 4, iclass 6, count 0 2006.238.07:41:59.65#ibcon#read 4, iclass 6, count 0 2006.238.07:41:59.65#ibcon#about to read 5, iclass 6, count 0 2006.238.07:41:59.65#ibcon#read 5, iclass 6, count 0 2006.238.07:41:59.65#ibcon#about to read 6, iclass 6, count 0 2006.238.07:41:59.65#ibcon#read 6, iclass 6, count 0 2006.238.07:41:59.65#ibcon#end of sib2, iclass 6, count 0 2006.238.07:41:59.65#ibcon#*after write, iclass 6, count 0 2006.238.07:41:59.65#ibcon#*before return 0, iclass 6, count 0 2006.238.07:41:59.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:41:59.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:41:59.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.07:41:59.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.07:41:59.65$vc4f8/va=6,7 2006.238.07:41:59.65#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.238.07:41:59.65#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.238.07:41:59.65#ibcon#ireg 11 cls_cnt 2 2006.238.07:41:59.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:41:59.71#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:41:59.71#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:41:59.71#ibcon#enter wrdev, iclass 10, count 2 2006.238.07:41:59.71#ibcon#first serial, iclass 10, count 2 2006.238.07:41:59.71#ibcon#enter sib2, iclass 10, count 2 2006.238.07:41:59.71#ibcon#flushed, iclass 10, count 2 2006.238.07:41:59.71#ibcon#about to write, iclass 10, count 2 2006.238.07:41:59.71#ibcon#wrote, iclass 10, count 2 2006.238.07:41:59.71#ibcon#about to read 3, iclass 10, count 2 2006.238.07:41:59.73#ibcon#read 3, iclass 10, count 2 2006.238.07:41:59.73#ibcon#about to read 4, iclass 10, count 2 2006.238.07:41:59.73#ibcon#read 4, iclass 10, count 2 2006.238.07:41:59.73#ibcon#about to read 5, iclass 10, count 2 2006.238.07:41:59.73#ibcon#read 5, iclass 10, count 2 2006.238.07:41:59.73#ibcon#about to read 6, iclass 10, count 2 2006.238.07:41:59.73#ibcon#read 6, iclass 10, count 2 2006.238.07:41:59.73#ibcon#end of sib2, iclass 10, count 2 2006.238.07:41:59.73#ibcon#*mode == 0, iclass 10, count 2 2006.238.07:41:59.73#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.238.07:41:59.73#ibcon#[25=AT06-07\r\n] 2006.238.07:41:59.73#ibcon#*before write, iclass 10, count 2 2006.238.07:41:59.73#ibcon#enter sib2, iclass 10, count 2 2006.238.07:41:59.73#ibcon#flushed, iclass 10, count 2 2006.238.07:41:59.73#ibcon#about to write, iclass 10, count 2 2006.238.07:41:59.73#ibcon#wrote, iclass 10, count 2 2006.238.07:41:59.73#ibcon#about to read 3, iclass 10, count 2 2006.238.07:41:59.76#ibcon#read 3, iclass 10, count 2 2006.238.07:41:59.76#ibcon#about to read 4, iclass 10, count 2 2006.238.07:41:59.76#ibcon#read 4, iclass 10, count 2 2006.238.07:41:59.76#ibcon#about to read 5, iclass 10, count 2 2006.238.07:41:59.76#ibcon#read 5, iclass 10, count 2 2006.238.07:41:59.76#ibcon#about to read 6, iclass 10, count 2 2006.238.07:41:59.76#ibcon#read 6, iclass 10, count 2 2006.238.07:41:59.76#ibcon#end of sib2, iclass 10, count 2 2006.238.07:41:59.76#ibcon#*after write, iclass 10, count 2 2006.238.07:41:59.76#ibcon#*before return 0, iclass 10, count 2 2006.238.07:41:59.76#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:41:59.76#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:41:59.76#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.238.07:41:59.76#ibcon#ireg 7 cls_cnt 0 2006.238.07:41:59.76#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:41:59.88#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:41:59.88#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:41:59.88#ibcon#enter wrdev, iclass 10, count 0 2006.238.07:41:59.88#ibcon#first serial, iclass 10, count 0 2006.238.07:41:59.88#ibcon#enter sib2, iclass 10, count 0 2006.238.07:41:59.88#ibcon#flushed, iclass 10, count 0 2006.238.07:41:59.88#ibcon#about to write, iclass 10, count 0 2006.238.07:41:59.88#ibcon#wrote, iclass 10, count 0 2006.238.07:41:59.88#ibcon#about to read 3, iclass 10, count 0 2006.238.07:41:59.90#ibcon#read 3, iclass 10, count 0 2006.238.07:41:59.90#ibcon#about to read 4, iclass 10, count 0 2006.238.07:41:59.90#ibcon#read 4, iclass 10, count 0 2006.238.07:41:59.90#ibcon#about to read 5, iclass 10, count 0 2006.238.07:41:59.90#ibcon#read 5, iclass 10, count 0 2006.238.07:41:59.90#ibcon#about to read 6, iclass 10, count 0 2006.238.07:41:59.90#ibcon#read 6, iclass 10, count 0 2006.238.07:41:59.90#ibcon#end of sib2, iclass 10, count 0 2006.238.07:41:59.90#ibcon#*mode == 0, iclass 10, count 0 2006.238.07:41:59.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.07:41:59.90#ibcon#[25=USB\r\n] 2006.238.07:41:59.90#ibcon#*before write, iclass 10, count 0 2006.238.07:41:59.90#ibcon#enter sib2, iclass 10, count 0 2006.238.07:41:59.90#ibcon#flushed, iclass 10, count 0 2006.238.07:41:59.90#ibcon#about to write, iclass 10, count 0 2006.238.07:41:59.90#ibcon#wrote, iclass 10, count 0 2006.238.07:41:59.90#ibcon#about to read 3, iclass 10, count 0 2006.238.07:41:59.93#ibcon#read 3, iclass 10, count 0 2006.238.07:41:59.93#ibcon#about to read 4, iclass 10, count 0 2006.238.07:41:59.93#ibcon#read 4, iclass 10, count 0 2006.238.07:41:59.93#ibcon#about to read 5, iclass 10, count 0 2006.238.07:41:59.93#ibcon#read 5, iclass 10, count 0 2006.238.07:41:59.93#ibcon#about to read 6, iclass 10, count 0 2006.238.07:41:59.93#ibcon#read 6, iclass 10, count 0 2006.238.07:41:59.93#ibcon#end of sib2, iclass 10, count 0 2006.238.07:41:59.93#ibcon#*after write, iclass 10, count 0 2006.238.07:41:59.93#ibcon#*before return 0, iclass 10, count 0 2006.238.07:41:59.93#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:41:59.93#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:41:59.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.07:41:59.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.07:41:59.93$vc4f8/valo=7,832.99 2006.238.07:41:59.93#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.238.07:41:59.93#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.238.07:41:59.93#ibcon#ireg 17 cls_cnt 0 2006.238.07:41:59.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:41:59.93#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:41:59.93#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:41:59.93#ibcon#enter wrdev, iclass 12, count 0 2006.238.07:41:59.93#ibcon#first serial, iclass 12, count 0 2006.238.07:41:59.93#ibcon#enter sib2, iclass 12, count 0 2006.238.07:41:59.93#ibcon#flushed, iclass 12, count 0 2006.238.07:41:59.93#ibcon#about to write, iclass 12, count 0 2006.238.07:41:59.93#ibcon#wrote, iclass 12, count 0 2006.238.07:41:59.93#ibcon#about to read 3, iclass 12, count 0 2006.238.07:41:59.95#ibcon#read 3, iclass 12, count 0 2006.238.07:41:59.95#ibcon#about to read 4, iclass 12, count 0 2006.238.07:41:59.95#ibcon#read 4, iclass 12, count 0 2006.238.07:41:59.95#ibcon#about to read 5, iclass 12, count 0 2006.238.07:41:59.95#ibcon#read 5, iclass 12, count 0 2006.238.07:41:59.95#ibcon#about to read 6, iclass 12, count 0 2006.238.07:41:59.95#ibcon#read 6, iclass 12, count 0 2006.238.07:41:59.95#ibcon#end of sib2, iclass 12, count 0 2006.238.07:41:59.95#ibcon#*mode == 0, iclass 12, count 0 2006.238.07:41:59.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.07:41:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:41:59.95#ibcon#*before write, iclass 12, count 0 2006.238.07:41:59.95#ibcon#enter sib2, iclass 12, count 0 2006.238.07:41:59.95#ibcon#flushed, iclass 12, count 0 2006.238.07:41:59.95#ibcon#about to write, iclass 12, count 0 2006.238.07:41:59.95#ibcon#wrote, iclass 12, count 0 2006.238.07:41:59.95#ibcon#about to read 3, iclass 12, count 0 2006.238.07:41:59.99#ibcon#read 3, iclass 12, count 0 2006.238.07:41:59.99#ibcon#about to read 4, iclass 12, count 0 2006.238.07:41:59.99#ibcon#read 4, iclass 12, count 0 2006.238.07:41:59.99#ibcon#about to read 5, iclass 12, count 0 2006.238.07:41:59.99#ibcon#read 5, iclass 12, count 0 2006.238.07:41:59.99#ibcon#about to read 6, iclass 12, count 0 2006.238.07:41:59.99#ibcon#read 6, iclass 12, count 0 2006.238.07:41:59.99#ibcon#end of sib2, iclass 12, count 0 2006.238.07:41:59.99#ibcon#*after write, iclass 12, count 0 2006.238.07:41:59.99#ibcon#*before return 0, iclass 12, count 0 2006.238.07:41:59.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:41:59.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:41:59.99#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.07:41:59.99#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.07:41:59.99$vc4f8/va=7,7 2006.238.07:41:59.99#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.238.07:41:59.99#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.238.07:41:59.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:41:59.99#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:42:00.06#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:42:00.06#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:42:00.06#ibcon#enter wrdev, iclass 14, count 2 2006.238.07:42:00.06#ibcon#first serial, iclass 14, count 2 2006.238.07:42:00.06#ibcon#enter sib2, iclass 14, count 2 2006.238.07:42:00.06#ibcon#flushed, iclass 14, count 2 2006.238.07:42:00.06#ibcon#about to write, iclass 14, count 2 2006.238.07:42:00.06#ibcon#wrote, iclass 14, count 2 2006.238.07:42:00.06#ibcon#about to read 3, iclass 14, count 2 2006.238.07:42:00.07#ibcon#read 3, iclass 14, count 2 2006.238.07:42:00.07#ibcon#about to read 4, iclass 14, count 2 2006.238.07:42:00.07#ibcon#read 4, iclass 14, count 2 2006.238.07:42:00.07#ibcon#about to read 5, iclass 14, count 2 2006.238.07:42:00.07#ibcon#read 5, iclass 14, count 2 2006.238.07:42:00.07#ibcon#about to read 6, iclass 14, count 2 2006.238.07:42:00.07#ibcon#read 6, iclass 14, count 2 2006.238.07:42:00.07#ibcon#end of sib2, iclass 14, count 2 2006.238.07:42:00.07#ibcon#*mode == 0, iclass 14, count 2 2006.238.07:42:00.07#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.238.07:42:00.07#ibcon#[25=AT07-07\r\n] 2006.238.07:42:00.07#ibcon#*before write, iclass 14, count 2 2006.238.07:42:00.07#ibcon#enter sib2, iclass 14, count 2 2006.238.07:42:00.07#ibcon#flushed, iclass 14, count 2 2006.238.07:42:00.07#ibcon#about to write, iclass 14, count 2 2006.238.07:42:00.07#ibcon#wrote, iclass 14, count 2 2006.238.07:42:00.07#ibcon#about to read 3, iclass 14, count 2 2006.238.07:42:00.10#ibcon#read 3, iclass 14, count 2 2006.238.07:42:00.10#ibcon#about to read 4, iclass 14, count 2 2006.238.07:42:00.10#ibcon#read 4, iclass 14, count 2 2006.238.07:42:00.10#ibcon#about to read 5, iclass 14, count 2 2006.238.07:42:00.10#ibcon#read 5, iclass 14, count 2 2006.238.07:42:00.10#ibcon#about to read 6, iclass 14, count 2 2006.238.07:42:00.10#ibcon#read 6, iclass 14, count 2 2006.238.07:42:00.10#ibcon#end of sib2, iclass 14, count 2 2006.238.07:42:00.10#ibcon#*after write, iclass 14, count 2 2006.238.07:42:00.10#ibcon#*before return 0, iclass 14, count 2 2006.238.07:42:00.10#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:42:00.10#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:42:00.10#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.238.07:42:00.10#ibcon#ireg 7 cls_cnt 0 2006.238.07:42:00.10#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:42:00.22#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:42:00.22#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:42:00.22#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:42:00.22#ibcon#first serial, iclass 14, count 0 2006.238.07:42:00.22#ibcon#enter sib2, iclass 14, count 0 2006.238.07:42:00.22#ibcon#flushed, iclass 14, count 0 2006.238.07:42:00.22#ibcon#about to write, iclass 14, count 0 2006.238.07:42:00.22#ibcon#wrote, iclass 14, count 0 2006.238.07:42:00.22#ibcon#about to read 3, iclass 14, count 0 2006.238.07:42:00.24#ibcon#read 3, iclass 14, count 0 2006.238.07:42:00.24#ibcon#about to read 4, iclass 14, count 0 2006.238.07:42:00.24#ibcon#read 4, iclass 14, count 0 2006.238.07:42:00.24#ibcon#about to read 5, iclass 14, count 0 2006.238.07:42:00.24#ibcon#read 5, iclass 14, count 0 2006.238.07:42:00.24#ibcon#about to read 6, iclass 14, count 0 2006.238.07:42:00.24#ibcon#read 6, iclass 14, count 0 2006.238.07:42:00.24#ibcon#end of sib2, iclass 14, count 0 2006.238.07:42:00.24#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:42:00.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:42:00.24#ibcon#[25=USB\r\n] 2006.238.07:42:00.24#ibcon#*before write, iclass 14, count 0 2006.238.07:42:00.24#ibcon#enter sib2, iclass 14, count 0 2006.238.07:42:00.24#ibcon#flushed, iclass 14, count 0 2006.238.07:42:00.24#ibcon#about to write, iclass 14, count 0 2006.238.07:42:00.24#ibcon#wrote, iclass 14, count 0 2006.238.07:42:00.24#ibcon#about to read 3, iclass 14, count 0 2006.238.07:42:00.27#ibcon#read 3, iclass 14, count 0 2006.238.07:42:00.27#ibcon#about to read 4, iclass 14, count 0 2006.238.07:42:00.27#ibcon#read 4, iclass 14, count 0 2006.238.07:42:00.27#ibcon#about to read 5, iclass 14, count 0 2006.238.07:42:00.27#ibcon#read 5, iclass 14, count 0 2006.238.07:42:00.27#ibcon#about to read 6, iclass 14, count 0 2006.238.07:42:00.27#ibcon#read 6, iclass 14, count 0 2006.238.07:42:00.27#ibcon#end of sib2, iclass 14, count 0 2006.238.07:42:00.27#ibcon#*after write, iclass 14, count 0 2006.238.07:42:00.27#ibcon#*before return 0, iclass 14, count 0 2006.238.07:42:00.27#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:42:00.27#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:42:00.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:42:00.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:42:00.27$vc4f8/valo=8,852.99 2006.238.07:42:00.27#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.07:42:00.27#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.07:42:00.27#ibcon#ireg 17 cls_cnt 0 2006.238.07:42:00.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:42:00.27#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:42:00.27#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:42:00.27#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:42:00.27#ibcon#first serial, iclass 16, count 0 2006.238.07:42:00.27#ibcon#enter sib2, iclass 16, count 0 2006.238.07:42:00.27#ibcon#flushed, iclass 16, count 0 2006.238.07:42:00.27#ibcon#about to write, iclass 16, count 0 2006.238.07:42:00.27#ibcon#wrote, iclass 16, count 0 2006.238.07:42:00.27#ibcon#about to read 3, iclass 16, count 0 2006.238.07:42:00.29#ibcon#read 3, iclass 16, count 0 2006.238.07:42:00.29#ibcon#about to read 4, iclass 16, count 0 2006.238.07:42:00.29#ibcon#read 4, iclass 16, count 0 2006.238.07:42:00.29#ibcon#about to read 5, iclass 16, count 0 2006.238.07:42:00.29#ibcon#read 5, iclass 16, count 0 2006.238.07:42:00.29#ibcon#about to read 6, iclass 16, count 0 2006.238.07:42:00.29#ibcon#read 6, iclass 16, count 0 2006.238.07:42:00.29#ibcon#end of sib2, iclass 16, count 0 2006.238.07:42:00.29#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:42:00.29#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:42:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:42:00.29#ibcon#*before write, iclass 16, count 0 2006.238.07:42:00.29#ibcon#enter sib2, iclass 16, count 0 2006.238.07:42:00.29#ibcon#flushed, iclass 16, count 0 2006.238.07:42:00.29#ibcon#about to write, iclass 16, count 0 2006.238.07:42:00.29#ibcon#wrote, iclass 16, count 0 2006.238.07:42:00.29#ibcon#about to read 3, iclass 16, count 0 2006.238.07:42:00.33#ibcon#read 3, iclass 16, count 0 2006.238.07:42:00.33#ibcon#about to read 4, iclass 16, count 0 2006.238.07:42:00.33#ibcon#read 4, iclass 16, count 0 2006.238.07:42:00.33#ibcon#about to read 5, iclass 16, count 0 2006.238.07:42:00.33#ibcon#read 5, iclass 16, count 0 2006.238.07:42:00.33#ibcon#about to read 6, iclass 16, count 0 2006.238.07:42:00.33#ibcon#read 6, iclass 16, count 0 2006.238.07:42:00.33#ibcon#end of sib2, iclass 16, count 0 2006.238.07:42:00.33#ibcon#*after write, iclass 16, count 0 2006.238.07:42:00.33#ibcon#*before return 0, iclass 16, count 0 2006.238.07:42:00.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:42:00.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:42:00.33#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:42:00.33#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:42:00.33$vc4f8/va=8,7 2006.238.07:42:00.33#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.238.07:42:00.33#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.238.07:42:00.33#ibcon#ireg 11 cls_cnt 2 2006.238.07:42:00.33#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:42:00.39#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:42:00.39#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:42:00.39#ibcon#enter wrdev, iclass 18, count 2 2006.238.07:42:00.39#ibcon#first serial, iclass 18, count 2 2006.238.07:42:00.39#ibcon#enter sib2, iclass 18, count 2 2006.238.07:42:00.39#ibcon#flushed, iclass 18, count 2 2006.238.07:42:00.39#ibcon#about to write, iclass 18, count 2 2006.238.07:42:00.39#ibcon#wrote, iclass 18, count 2 2006.238.07:42:00.39#ibcon#about to read 3, iclass 18, count 2 2006.238.07:42:00.41#ibcon#read 3, iclass 18, count 2 2006.238.07:42:00.41#ibcon#about to read 4, iclass 18, count 2 2006.238.07:42:00.41#ibcon#read 4, iclass 18, count 2 2006.238.07:42:00.41#ibcon#about to read 5, iclass 18, count 2 2006.238.07:42:00.41#ibcon#read 5, iclass 18, count 2 2006.238.07:42:00.41#ibcon#about to read 6, iclass 18, count 2 2006.238.07:42:00.41#ibcon#read 6, iclass 18, count 2 2006.238.07:42:00.41#ibcon#end of sib2, iclass 18, count 2 2006.238.07:42:00.41#ibcon#*mode == 0, iclass 18, count 2 2006.238.07:42:00.41#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.238.07:42:00.41#ibcon#[25=AT08-07\r\n] 2006.238.07:42:00.41#ibcon#*before write, iclass 18, count 2 2006.238.07:42:00.41#ibcon#enter sib2, iclass 18, count 2 2006.238.07:42:00.41#ibcon#flushed, iclass 18, count 2 2006.238.07:42:00.41#ibcon#about to write, iclass 18, count 2 2006.238.07:42:00.41#ibcon#wrote, iclass 18, count 2 2006.238.07:42:00.41#ibcon#about to read 3, iclass 18, count 2 2006.238.07:42:00.44#ibcon#read 3, iclass 18, count 2 2006.238.07:42:00.44#ibcon#about to read 4, iclass 18, count 2 2006.238.07:42:00.44#ibcon#read 4, iclass 18, count 2 2006.238.07:42:00.44#ibcon#about to read 5, iclass 18, count 2 2006.238.07:42:00.44#ibcon#read 5, iclass 18, count 2 2006.238.07:42:00.44#ibcon#about to read 6, iclass 18, count 2 2006.238.07:42:00.44#ibcon#read 6, iclass 18, count 2 2006.238.07:42:00.44#ibcon#end of sib2, iclass 18, count 2 2006.238.07:42:00.44#ibcon#*after write, iclass 18, count 2 2006.238.07:42:00.44#ibcon#*before return 0, iclass 18, count 2 2006.238.07:42:00.44#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:42:00.44#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:42:00.44#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.238.07:42:00.44#ibcon#ireg 7 cls_cnt 0 2006.238.07:42:00.44#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:42:00.56#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:42:00.56#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:42:00.56#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:42:00.56#ibcon#first serial, iclass 18, count 0 2006.238.07:42:00.56#ibcon#enter sib2, iclass 18, count 0 2006.238.07:42:00.56#ibcon#flushed, iclass 18, count 0 2006.238.07:42:00.56#ibcon#about to write, iclass 18, count 0 2006.238.07:42:00.56#ibcon#wrote, iclass 18, count 0 2006.238.07:42:00.56#ibcon#about to read 3, iclass 18, count 0 2006.238.07:42:00.58#ibcon#read 3, iclass 18, count 0 2006.238.07:42:00.58#ibcon#about to read 4, iclass 18, count 0 2006.238.07:42:00.58#ibcon#read 4, iclass 18, count 0 2006.238.07:42:00.58#ibcon#about to read 5, iclass 18, count 0 2006.238.07:42:00.58#ibcon#read 5, iclass 18, count 0 2006.238.07:42:00.58#ibcon#about to read 6, iclass 18, count 0 2006.238.07:42:00.58#ibcon#read 6, iclass 18, count 0 2006.238.07:42:00.58#ibcon#end of sib2, iclass 18, count 0 2006.238.07:42:00.58#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:42:00.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:42:00.58#ibcon#[25=USB\r\n] 2006.238.07:42:00.58#ibcon#*before write, iclass 18, count 0 2006.238.07:42:00.58#ibcon#enter sib2, iclass 18, count 0 2006.238.07:42:00.58#ibcon#flushed, iclass 18, count 0 2006.238.07:42:00.58#ibcon#about to write, iclass 18, count 0 2006.238.07:42:00.58#ibcon#wrote, iclass 18, count 0 2006.238.07:42:00.58#ibcon#about to read 3, iclass 18, count 0 2006.238.07:42:00.61#ibcon#read 3, iclass 18, count 0 2006.238.07:42:00.61#ibcon#about to read 4, iclass 18, count 0 2006.238.07:42:00.61#ibcon#read 4, iclass 18, count 0 2006.238.07:42:00.61#ibcon#about to read 5, iclass 18, count 0 2006.238.07:42:00.61#ibcon#read 5, iclass 18, count 0 2006.238.07:42:00.61#ibcon#about to read 6, iclass 18, count 0 2006.238.07:42:00.61#ibcon#read 6, iclass 18, count 0 2006.238.07:42:00.61#ibcon#end of sib2, iclass 18, count 0 2006.238.07:42:00.61#ibcon#*after write, iclass 18, count 0 2006.238.07:42:00.61#ibcon#*before return 0, iclass 18, count 0 2006.238.07:42:00.61#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:42:00.61#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:42:00.61#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:42:00.61#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:42:00.61$vc4f8/vblo=1,632.99 2006.238.07:42:00.61#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.07:42:00.61#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.07:42:00.61#ibcon#ireg 17 cls_cnt 0 2006.238.07:42:00.61#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:42:00.61#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:42:00.61#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:42:00.61#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:42:00.61#ibcon#first serial, iclass 20, count 0 2006.238.07:42:00.61#ibcon#enter sib2, iclass 20, count 0 2006.238.07:42:00.61#ibcon#flushed, iclass 20, count 0 2006.238.07:42:00.61#ibcon#about to write, iclass 20, count 0 2006.238.07:42:00.61#ibcon#wrote, iclass 20, count 0 2006.238.07:42:00.61#ibcon#about to read 3, iclass 20, count 0 2006.238.07:42:00.63#ibcon#read 3, iclass 20, count 0 2006.238.07:42:00.63#ibcon#about to read 4, iclass 20, count 0 2006.238.07:42:00.63#ibcon#read 4, iclass 20, count 0 2006.238.07:42:00.63#ibcon#about to read 5, iclass 20, count 0 2006.238.07:42:00.63#ibcon#read 5, iclass 20, count 0 2006.238.07:42:00.63#ibcon#about to read 6, iclass 20, count 0 2006.238.07:42:00.63#ibcon#read 6, iclass 20, count 0 2006.238.07:42:00.63#ibcon#end of sib2, iclass 20, count 0 2006.238.07:42:00.63#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:42:00.63#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:42:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:42:00.63#ibcon#*before write, iclass 20, count 0 2006.238.07:42:00.63#ibcon#enter sib2, iclass 20, count 0 2006.238.07:42:00.63#ibcon#flushed, iclass 20, count 0 2006.238.07:42:00.63#ibcon#about to write, iclass 20, count 0 2006.238.07:42:00.63#ibcon#wrote, iclass 20, count 0 2006.238.07:42:00.63#ibcon#about to read 3, iclass 20, count 0 2006.238.07:42:00.67#ibcon#read 3, iclass 20, count 0 2006.238.07:42:00.67#ibcon#about to read 4, iclass 20, count 0 2006.238.07:42:00.67#ibcon#read 4, iclass 20, count 0 2006.238.07:42:00.67#ibcon#about to read 5, iclass 20, count 0 2006.238.07:42:00.67#ibcon#read 5, iclass 20, count 0 2006.238.07:42:00.67#ibcon#about to read 6, iclass 20, count 0 2006.238.07:42:00.67#ibcon#read 6, iclass 20, count 0 2006.238.07:42:00.67#ibcon#end of sib2, iclass 20, count 0 2006.238.07:42:00.67#ibcon#*after write, iclass 20, count 0 2006.238.07:42:00.67#ibcon#*before return 0, iclass 20, count 0 2006.238.07:42:00.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:42:00.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:42:00.67#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:42:00.67#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:42:00.67$vc4f8/vb=1,4 2006.238.07:42:00.67#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.238.07:42:00.67#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.238.07:42:00.67#ibcon#ireg 11 cls_cnt 2 2006.238.07:42:00.67#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:42:00.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:42:00.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:42:00.67#ibcon#enter wrdev, iclass 22, count 2 2006.238.07:42:00.67#ibcon#first serial, iclass 22, count 2 2006.238.07:42:00.67#ibcon#enter sib2, iclass 22, count 2 2006.238.07:42:00.67#ibcon#flushed, iclass 22, count 2 2006.238.07:42:00.67#ibcon#about to write, iclass 22, count 2 2006.238.07:42:00.67#ibcon#wrote, iclass 22, count 2 2006.238.07:42:00.67#ibcon#about to read 3, iclass 22, count 2 2006.238.07:42:00.69#ibcon#read 3, iclass 22, count 2 2006.238.07:42:00.69#ibcon#about to read 4, iclass 22, count 2 2006.238.07:42:00.69#ibcon#read 4, iclass 22, count 2 2006.238.07:42:00.69#ibcon#about to read 5, iclass 22, count 2 2006.238.07:42:00.69#ibcon#read 5, iclass 22, count 2 2006.238.07:42:00.69#ibcon#about to read 6, iclass 22, count 2 2006.238.07:42:00.69#ibcon#read 6, iclass 22, count 2 2006.238.07:42:00.69#ibcon#end of sib2, iclass 22, count 2 2006.238.07:42:00.69#ibcon#*mode == 0, iclass 22, count 2 2006.238.07:42:00.69#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.238.07:42:00.69#ibcon#[27=AT01-04\r\n] 2006.238.07:42:00.69#ibcon#*before write, iclass 22, count 2 2006.238.07:42:00.69#ibcon#enter sib2, iclass 22, count 2 2006.238.07:42:00.69#ibcon#flushed, iclass 22, count 2 2006.238.07:42:00.69#ibcon#about to write, iclass 22, count 2 2006.238.07:42:00.69#ibcon#wrote, iclass 22, count 2 2006.238.07:42:00.69#ibcon#about to read 3, iclass 22, count 2 2006.238.07:42:00.72#ibcon#read 3, iclass 22, count 2 2006.238.07:42:00.72#ibcon#about to read 4, iclass 22, count 2 2006.238.07:42:00.72#ibcon#read 4, iclass 22, count 2 2006.238.07:42:00.72#ibcon#about to read 5, iclass 22, count 2 2006.238.07:42:00.72#ibcon#read 5, iclass 22, count 2 2006.238.07:42:00.72#ibcon#about to read 6, iclass 22, count 2 2006.238.07:42:00.72#ibcon#read 6, iclass 22, count 2 2006.238.07:42:00.72#ibcon#end of sib2, iclass 22, count 2 2006.238.07:42:00.72#ibcon#*after write, iclass 22, count 2 2006.238.07:42:00.72#ibcon#*before return 0, iclass 22, count 2 2006.238.07:42:00.72#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:42:00.72#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:42:00.72#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.238.07:42:00.72#ibcon#ireg 7 cls_cnt 0 2006.238.07:42:00.72#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:42:00.85#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:42:00.85#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:42:00.85#ibcon#enter wrdev, iclass 22, count 0 2006.238.07:42:00.85#ibcon#first serial, iclass 22, count 0 2006.238.07:42:00.85#ibcon#enter sib2, iclass 22, count 0 2006.238.07:42:00.85#ibcon#flushed, iclass 22, count 0 2006.238.07:42:00.85#ibcon#about to write, iclass 22, count 0 2006.238.07:42:00.85#ibcon#wrote, iclass 22, count 0 2006.238.07:42:00.85#ibcon#about to read 3, iclass 22, count 0 2006.238.07:42:00.87#ibcon#read 3, iclass 22, count 0 2006.238.07:42:00.87#ibcon#about to read 4, iclass 22, count 0 2006.238.07:42:00.87#ibcon#read 4, iclass 22, count 0 2006.238.07:42:00.87#ibcon#about to read 5, iclass 22, count 0 2006.238.07:42:00.87#ibcon#read 5, iclass 22, count 0 2006.238.07:42:00.87#ibcon#about to read 6, iclass 22, count 0 2006.238.07:42:00.87#ibcon#read 6, iclass 22, count 0 2006.238.07:42:00.87#ibcon#end of sib2, iclass 22, count 0 2006.238.07:42:00.87#ibcon#*mode == 0, iclass 22, count 0 2006.238.07:42:00.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.07:42:00.87#ibcon#[27=USB\r\n] 2006.238.07:42:00.87#ibcon#*before write, iclass 22, count 0 2006.238.07:42:00.87#ibcon#enter sib2, iclass 22, count 0 2006.238.07:42:00.87#ibcon#flushed, iclass 22, count 0 2006.238.07:42:00.87#ibcon#about to write, iclass 22, count 0 2006.238.07:42:00.87#ibcon#wrote, iclass 22, count 0 2006.238.07:42:00.87#ibcon#about to read 3, iclass 22, count 0 2006.238.07:42:00.90#ibcon#read 3, iclass 22, count 0 2006.238.07:42:00.90#ibcon#about to read 4, iclass 22, count 0 2006.238.07:42:00.90#ibcon#read 4, iclass 22, count 0 2006.238.07:42:00.90#ibcon#about to read 5, iclass 22, count 0 2006.238.07:42:00.90#ibcon#read 5, iclass 22, count 0 2006.238.07:42:00.90#ibcon#about to read 6, iclass 22, count 0 2006.238.07:42:00.90#ibcon#read 6, iclass 22, count 0 2006.238.07:42:00.90#ibcon#end of sib2, iclass 22, count 0 2006.238.07:42:00.90#ibcon#*after write, iclass 22, count 0 2006.238.07:42:00.90#ibcon#*before return 0, iclass 22, count 0 2006.238.07:42:00.90#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:42:00.90#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:42:00.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.07:42:00.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.07:42:00.90$vc4f8/vblo=2,640.99 2006.238.07:42:00.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.07:42:00.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.07:42:00.90#ibcon#ireg 17 cls_cnt 0 2006.238.07:42:00.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:42:00.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:42:00.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:42:00.90#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:42:00.90#ibcon#first serial, iclass 24, count 0 2006.238.07:42:00.90#ibcon#enter sib2, iclass 24, count 0 2006.238.07:42:00.90#ibcon#flushed, iclass 24, count 0 2006.238.07:42:00.90#ibcon#about to write, iclass 24, count 0 2006.238.07:42:00.90#ibcon#wrote, iclass 24, count 0 2006.238.07:42:00.90#ibcon#about to read 3, iclass 24, count 0 2006.238.07:42:00.92#ibcon#read 3, iclass 24, count 0 2006.238.07:42:00.92#ibcon#about to read 4, iclass 24, count 0 2006.238.07:42:00.92#ibcon#read 4, iclass 24, count 0 2006.238.07:42:00.92#ibcon#about to read 5, iclass 24, count 0 2006.238.07:42:00.92#ibcon#read 5, iclass 24, count 0 2006.238.07:42:00.92#ibcon#about to read 6, iclass 24, count 0 2006.238.07:42:00.92#ibcon#read 6, iclass 24, count 0 2006.238.07:42:00.92#ibcon#end of sib2, iclass 24, count 0 2006.238.07:42:00.92#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:42:00.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:42:00.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:42:00.92#ibcon#*before write, iclass 24, count 0 2006.238.07:42:00.92#ibcon#enter sib2, iclass 24, count 0 2006.238.07:42:00.92#ibcon#flushed, iclass 24, count 0 2006.238.07:42:00.92#ibcon#about to write, iclass 24, count 0 2006.238.07:42:00.92#ibcon#wrote, iclass 24, count 0 2006.238.07:42:00.92#ibcon#about to read 3, iclass 24, count 0 2006.238.07:42:00.96#ibcon#read 3, iclass 24, count 0 2006.238.07:42:00.96#ibcon#about to read 4, iclass 24, count 0 2006.238.07:42:00.96#ibcon#read 4, iclass 24, count 0 2006.238.07:42:00.96#ibcon#about to read 5, iclass 24, count 0 2006.238.07:42:00.96#ibcon#read 5, iclass 24, count 0 2006.238.07:42:00.96#ibcon#about to read 6, iclass 24, count 0 2006.238.07:42:00.96#ibcon#read 6, iclass 24, count 0 2006.238.07:42:00.96#ibcon#end of sib2, iclass 24, count 0 2006.238.07:42:00.96#ibcon#*after write, iclass 24, count 0 2006.238.07:42:00.96#ibcon#*before return 0, iclass 24, count 0 2006.238.07:42:00.96#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:42:00.96#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:42:00.96#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:42:00.96#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:42:00.96$vc4f8/vb=2,4 2006.238.07:42:00.96#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.238.07:42:00.96#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.238.07:42:00.96#ibcon#ireg 11 cls_cnt 2 2006.238.07:42:00.96#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:42:01.02#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:42:01.02#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:42:01.02#ibcon#enter wrdev, iclass 26, count 2 2006.238.07:42:01.02#ibcon#first serial, iclass 26, count 2 2006.238.07:42:01.02#ibcon#enter sib2, iclass 26, count 2 2006.238.07:42:01.02#ibcon#flushed, iclass 26, count 2 2006.238.07:42:01.02#ibcon#about to write, iclass 26, count 2 2006.238.07:42:01.02#ibcon#wrote, iclass 26, count 2 2006.238.07:42:01.02#ibcon#about to read 3, iclass 26, count 2 2006.238.07:42:01.04#ibcon#read 3, iclass 26, count 2 2006.238.07:42:01.04#ibcon#about to read 4, iclass 26, count 2 2006.238.07:42:01.04#ibcon#read 4, iclass 26, count 2 2006.238.07:42:01.04#ibcon#about to read 5, iclass 26, count 2 2006.238.07:42:01.04#ibcon#read 5, iclass 26, count 2 2006.238.07:42:01.04#ibcon#about to read 6, iclass 26, count 2 2006.238.07:42:01.04#ibcon#read 6, iclass 26, count 2 2006.238.07:42:01.04#ibcon#end of sib2, iclass 26, count 2 2006.238.07:42:01.04#ibcon#*mode == 0, iclass 26, count 2 2006.238.07:42:01.04#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.238.07:42:01.04#ibcon#[27=AT02-04\r\n] 2006.238.07:42:01.04#ibcon#*before write, iclass 26, count 2 2006.238.07:42:01.04#ibcon#enter sib2, iclass 26, count 2 2006.238.07:42:01.04#ibcon#flushed, iclass 26, count 2 2006.238.07:42:01.04#ibcon#about to write, iclass 26, count 2 2006.238.07:42:01.04#ibcon#wrote, iclass 26, count 2 2006.238.07:42:01.04#ibcon#about to read 3, iclass 26, count 2 2006.238.07:42:01.07#ibcon#read 3, iclass 26, count 2 2006.238.07:42:01.07#ibcon#about to read 4, iclass 26, count 2 2006.238.07:42:01.07#ibcon#read 4, iclass 26, count 2 2006.238.07:42:01.07#ibcon#about to read 5, iclass 26, count 2 2006.238.07:42:01.07#ibcon#read 5, iclass 26, count 2 2006.238.07:42:01.07#ibcon#about to read 6, iclass 26, count 2 2006.238.07:42:01.07#ibcon#read 6, iclass 26, count 2 2006.238.07:42:01.07#ibcon#end of sib2, iclass 26, count 2 2006.238.07:42:01.07#ibcon#*after write, iclass 26, count 2 2006.238.07:42:01.07#ibcon#*before return 0, iclass 26, count 2 2006.238.07:42:01.07#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:42:01.07#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:42:01.07#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.238.07:42:01.07#ibcon#ireg 7 cls_cnt 0 2006.238.07:42:01.07#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:42:01.19#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:42:01.19#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:42:01.19#ibcon#enter wrdev, iclass 26, count 0 2006.238.07:42:01.19#ibcon#first serial, iclass 26, count 0 2006.238.07:42:01.19#ibcon#enter sib2, iclass 26, count 0 2006.238.07:42:01.19#ibcon#flushed, iclass 26, count 0 2006.238.07:42:01.19#ibcon#about to write, iclass 26, count 0 2006.238.07:42:01.19#ibcon#wrote, iclass 26, count 0 2006.238.07:42:01.19#ibcon#about to read 3, iclass 26, count 0 2006.238.07:42:01.21#ibcon#read 3, iclass 26, count 0 2006.238.07:42:01.21#ibcon#about to read 4, iclass 26, count 0 2006.238.07:42:01.21#ibcon#read 4, iclass 26, count 0 2006.238.07:42:01.21#ibcon#about to read 5, iclass 26, count 0 2006.238.07:42:01.21#ibcon#read 5, iclass 26, count 0 2006.238.07:42:01.21#ibcon#about to read 6, iclass 26, count 0 2006.238.07:42:01.21#ibcon#read 6, iclass 26, count 0 2006.238.07:42:01.21#ibcon#end of sib2, iclass 26, count 0 2006.238.07:42:01.21#ibcon#*mode == 0, iclass 26, count 0 2006.238.07:42:01.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.07:42:01.21#ibcon#[27=USB\r\n] 2006.238.07:42:01.21#ibcon#*before write, iclass 26, count 0 2006.238.07:42:01.21#ibcon#enter sib2, iclass 26, count 0 2006.238.07:42:01.21#ibcon#flushed, iclass 26, count 0 2006.238.07:42:01.21#ibcon#about to write, iclass 26, count 0 2006.238.07:42:01.21#ibcon#wrote, iclass 26, count 0 2006.238.07:42:01.21#ibcon#about to read 3, iclass 26, count 0 2006.238.07:42:01.24#ibcon#read 3, iclass 26, count 0 2006.238.07:42:01.24#ibcon#about to read 4, iclass 26, count 0 2006.238.07:42:01.24#ibcon#read 4, iclass 26, count 0 2006.238.07:42:01.24#ibcon#about to read 5, iclass 26, count 0 2006.238.07:42:01.24#ibcon#read 5, iclass 26, count 0 2006.238.07:42:01.24#ibcon#about to read 6, iclass 26, count 0 2006.238.07:42:01.24#ibcon#read 6, iclass 26, count 0 2006.238.07:42:01.24#ibcon#end of sib2, iclass 26, count 0 2006.238.07:42:01.24#ibcon#*after write, iclass 26, count 0 2006.238.07:42:01.24#ibcon#*before return 0, iclass 26, count 0 2006.238.07:42:01.24#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:42:01.24#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:42:01.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.07:42:01.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.07:42:01.24$vc4f8/vblo=3,656.99 2006.238.07:42:01.24#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.238.07:42:01.24#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.238.07:42:01.24#ibcon#ireg 17 cls_cnt 0 2006.238.07:42:01.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:42:01.24#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:42:01.24#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:42:01.24#ibcon#enter wrdev, iclass 28, count 0 2006.238.07:42:01.24#ibcon#first serial, iclass 28, count 0 2006.238.07:42:01.24#ibcon#enter sib2, iclass 28, count 0 2006.238.07:42:01.24#ibcon#flushed, iclass 28, count 0 2006.238.07:42:01.24#ibcon#about to write, iclass 28, count 0 2006.238.07:42:01.24#ibcon#wrote, iclass 28, count 0 2006.238.07:42:01.24#ibcon#about to read 3, iclass 28, count 0 2006.238.07:42:01.26#ibcon#read 3, iclass 28, count 0 2006.238.07:42:01.26#ibcon#about to read 4, iclass 28, count 0 2006.238.07:42:01.26#ibcon#read 4, iclass 28, count 0 2006.238.07:42:01.26#ibcon#about to read 5, iclass 28, count 0 2006.238.07:42:01.26#ibcon#read 5, iclass 28, count 0 2006.238.07:42:01.26#ibcon#about to read 6, iclass 28, count 0 2006.238.07:42:01.26#ibcon#read 6, iclass 28, count 0 2006.238.07:42:01.26#ibcon#end of sib2, iclass 28, count 0 2006.238.07:42:01.26#ibcon#*mode == 0, iclass 28, count 0 2006.238.07:42:01.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.07:42:01.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:42:01.26#ibcon#*before write, iclass 28, count 0 2006.238.07:42:01.26#ibcon#enter sib2, iclass 28, count 0 2006.238.07:42:01.26#ibcon#flushed, iclass 28, count 0 2006.238.07:42:01.26#ibcon#about to write, iclass 28, count 0 2006.238.07:42:01.26#ibcon#wrote, iclass 28, count 0 2006.238.07:42:01.26#ibcon#about to read 3, iclass 28, count 0 2006.238.07:42:01.30#ibcon#read 3, iclass 28, count 0 2006.238.07:42:01.30#ibcon#about to read 4, iclass 28, count 0 2006.238.07:42:01.30#ibcon#read 4, iclass 28, count 0 2006.238.07:42:01.30#ibcon#about to read 5, iclass 28, count 0 2006.238.07:42:01.30#ibcon#read 5, iclass 28, count 0 2006.238.07:42:01.30#ibcon#about to read 6, iclass 28, count 0 2006.238.07:42:01.30#ibcon#read 6, iclass 28, count 0 2006.238.07:42:01.30#ibcon#end of sib2, iclass 28, count 0 2006.238.07:42:01.30#ibcon#*after write, iclass 28, count 0 2006.238.07:42:01.30#ibcon#*before return 0, iclass 28, count 0 2006.238.07:42:01.30#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:42:01.30#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:42:01.30#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.07:42:01.30#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.07:42:01.30$vc4f8/vb=3,4 2006.238.07:42:01.30#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.238.07:42:01.30#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.238.07:42:01.30#ibcon#ireg 11 cls_cnt 2 2006.238.07:42:01.30#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:42:01.36#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:42:01.36#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:42:01.36#ibcon#enter wrdev, iclass 30, count 2 2006.238.07:42:01.36#ibcon#first serial, iclass 30, count 2 2006.238.07:42:01.36#ibcon#enter sib2, iclass 30, count 2 2006.238.07:42:01.36#ibcon#flushed, iclass 30, count 2 2006.238.07:42:01.36#ibcon#about to write, iclass 30, count 2 2006.238.07:42:01.36#ibcon#wrote, iclass 30, count 2 2006.238.07:42:01.36#ibcon#about to read 3, iclass 30, count 2 2006.238.07:42:01.38#ibcon#read 3, iclass 30, count 2 2006.238.07:42:01.38#ibcon#about to read 4, iclass 30, count 2 2006.238.07:42:01.38#ibcon#read 4, iclass 30, count 2 2006.238.07:42:01.38#ibcon#about to read 5, iclass 30, count 2 2006.238.07:42:01.38#ibcon#read 5, iclass 30, count 2 2006.238.07:42:01.38#ibcon#about to read 6, iclass 30, count 2 2006.238.07:42:01.38#ibcon#read 6, iclass 30, count 2 2006.238.07:42:01.38#ibcon#end of sib2, iclass 30, count 2 2006.238.07:42:01.38#ibcon#*mode == 0, iclass 30, count 2 2006.238.07:42:01.38#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.238.07:42:01.38#ibcon#[27=AT03-04\r\n] 2006.238.07:42:01.38#ibcon#*before write, iclass 30, count 2 2006.238.07:42:01.38#ibcon#enter sib2, iclass 30, count 2 2006.238.07:42:01.38#ibcon#flushed, iclass 30, count 2 2006.238.07:42:01.38#ibcon#about to write, iclass 30, count 2 2006.238.07:42:01.38#ibcon#wrote, iclass 30, count 2 2006.238.07:42:01.38#ibcon#about to read 3, iclass 30, count 2 2006.238.07:42:01.41#ibcon#read 3, iclass 30, count 2 2006.238.07:42:01.41#ibcon#about to read 4, iclass 30, count 2 2006.238.07:42:01.41#ibcon#read 4, iclass 30, count 2 2006.238.07:42:01.41#ibcon#about to read 5, iclass 30, count 2 2006.238.07:42:01.41#ibcon#read 5, iclass 30, count 2 2006.238.07:42:01.41#ibcon#about to read 6, iclass 30, count 2 2006.238.07:42:01.41#ibcon#read 6, iclass 30, count 2 2006.238.07:42:01.41#ibcon#end of sib2, iclass 30, count 2 2006.238.07:42:01.41#ibcon#*after write, iclass 30, count 2 2006.238.07:42:01.41#ibcon#*before return 0, iclass 30, count 2 2006.238.07:42:01.41#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:42:01.41#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:42:01.41#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.238.07:42:01.41#ibcon#ireg 7 cls_cnt 0 2006.238.07:42:01.41#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:42:01.53#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:42:01.53#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:42:01.53#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:42:01.53#ibcon#first serial, iclass 30, count 0 2006.238.07:42:01.53#ibcon#enter sib2, iclass 30, count 0 2006.238.07:42:01.53#ibcon#flushed, iclass 30, count 0 2006.238.07:42:01.53#ibcon#about to write, iclass 30, count 0 2006.238.07:42:01.53#ibcon#wrote, iclass 30, count 0 2006.238.07:42:01.53#ibcon#about to read 3, iclass 30, count 0 2006.238.07:42:01.55#ibcon#read 3, iclass 30, count 0 2006.238.07:42:01.55#ibcon#about to read 4, iclass 30, count 0 2006.238.07:42:01.55#ibcon#read 4, iclass 30, count 0 2006.238.07:42:01.55#ibcon#about to read 5, iclass 30, count 0 2006.238.07:42:01.55#ibcon#read 5, iclass 30, count 0 2006.238.07:42:01.55#ibcon#about to read 6, iclass 30, count 0 2006.238.07:42:01.55#ibcon#read 6, iclass 30, count 0 2006.238.07:42:01.55#ibcon#end of sib2, iclass 30, count 0 2006.238.07:42:01.55#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:42:01.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:42:01.55#ibcon#[27=USB\r\n] 2006.238.07:42:01.55#ibcon#*before write, iclass 30, count 0 2006.238.07:42:01.55#ibcon#enter sib2, iclass 30, count 0 2006.238.07:42:01.55#ibcon#flushed, iclass 30, count 0 2006.238.07:42:01.55#ibcon#about to write, iclass 30, count 0 2006.238.07:42:01.55#ibcon#wrote, iclass 30, count 0 2006.238.07:42:01.55#ibcon#about to read 3, iclass 30, count 0 2006.238.07:42:01.58#ibcon#read 3, iclass 30, count 0 2006.238.07:42:01.58#ibcon#about to read 4, iclass 30, count 0 2006.238.07:42:01.58#ibcon#read 4, iclass 30, count 0 2006.238.07:42:01.58#ibcon#about to read 5, iclass 30, count 0 2006.238.07:42:01.58#ibcon#read 5, iclass 30, count 0 2006.238.07:42:01.58#ibcon#about to read 6, iclass 30, count 0 2006.238.07:42:01.58#ibcon#read 6, iclass 30, count 0 2006.238.07:42:01.58#ibcon#end of sib2, iclass 30, count 0 2006.238.07:42:01.58#ibcon#*after write, iclass 30, count 0 2006.238.07:42:01.58#ibcon#*before return 0, iclass 30, count 0 2006.238.07:42:01.58#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:42:01.58#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:42:01.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:42:01.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:42:01.58$vc4f8/vblo=4,712.99 2006.238.07:42:01.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.07:42:01.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.07:42:01.58#ibcon#ireg 17 cls_cnt 0 2006.238.07:42:01.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:42:01.58#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:42:01.58#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:42:01.58#ibcon#enter wrdev, iclass 32, count 0 2006.238.07:42:01.58#ibcon#first serial, iclass 32, count 0 2006.238.07:42:01.58#ibcon#enter sib2, iclass 32, count 0 2006.238.07:42:01.58#ibcon#flushed, iclass 32, count 0 2006.238.07:42:01.58#ibcon#about to write, iclass 32, count 0 2006.238.07:42:01.58#ibcon#wrote, iclass 32, count 0 2006.238.07:42:01.58#ibcon#about to read 3, iclass 32, count 0 2006.238.07:42:01.60#ibcon#read 3, iclass 32, count 0 2006.238.07:42:01.60#ibcon#about to read 4, iclass 32, count 0 2006.238.07:42:01.60#ibcon#read 4, iclass 32, count 0 2006.238.07:42:01.60#ibcon#about to read 5, iclass 32, count 0 2006.238.07:42:01.60#ibcon#read 5, iclass 32, count 0 2006.238.07:42:01.60#ibcon#about to read 6, iclass 32, count 0 2006.238.07:42:01.60#ibcon#read 6, iclass 32, count 0 2006.238.07:42:01.60#ibcon#end of sib2, iclass 32, count 0 2006.238.07:42:01.60#ibcon#*mode == 0, iclass 32, count 0 2006.238.07:42:01.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.07:42:01.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:42:01.60#ibcon#*before write, iclass 32, count 0 2006.238.07:42:01.60#ibcon#enter sib2, iclass 32, count 0 2006.238.07:42:01.60#ibcon#flushed, iclass 32, count 0 2006.238.07:42:01.60#ibcon#about to write, iclass 32, count 0 2006.238.07:42:01.60#ibcon#wrote, iclass 32, count 0 2006.238.07:42:01.60#ibcon#about to read 3, iclass 32, count 0 2006.238.07:42:01.64#ibcon#read 3, iclass 32, count 0 2006.238.07:42:01.64#ibcon#about to read 4, iclass 32, count 0 2006.238.07:42:01.64#ibcon#read 4, iclass 32, count 0 2006.238.07:42:01.64#ibcon#about to read 5, iclass 32, count 0 2006.238.07:42:01.64#ibcon#read 5, iclass 32, count 0 2006.238.07:42:01.64#ibcon#about to read 6, iclass 32, count 0 2006.238.07:42:01.64#ibcon#read 6, iclass 32, count 0 2006.238.07:42:01.64#ibcon#end of sib2, iclass 32, count 0 2006.238.07:42:01.64#ibcon#*after write, iclass 32, count 0 2006.238.07:42:01.64#ibcon#*before return 0, iclass 32, count 0 2006.238.07:42:01.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:42:01.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:42:01.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.07:42:01.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.07:42:01.64$vc4f8/vb=4,4 2006.238.07:42:01.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.238.07:42:01.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.238.07:42:01.64#ibcon#ireg 11 cls_cnt 2 2006.238.07:42:01.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:42:01.71#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:42:01.71#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:42:01.71#ibcon#enter wrdev, iclass 34, count 2 2006.238.07:42:01.71#ibcon#first serial, iclass 34, count 2 2006.238.07:42:01.71#ibcon#enter sib2, iclass 34, count 2 2006.238.07:42:01.71#ibcon#flushed, iclass 34, count 2 2006.238.07:42:01.71#ibcon#about to write, iclass 34, count 2 2006.238.07:42:01.71#ibcon#wrote, iclass 34, count 2 2006.238.07:42:01.71#ibcon#about to read 3, iclass 34, count 2 2006.238.07:42:01.72#ibcon#read 3, iclass 34, count 2 2006.238.07:42:01.72#ibcon#about to read 4, iclass 34, count 2 2006.238.07:42:01.72#ibcon#read 4, iclass 34, count 2 2006.238.07:42:01.72#ibcon#about to read 5, iclass 34, count 2 2006.238.07:42:01.72#ibcon#read 5, iclass 34, count 2 2006.238.07:42:01.72#ibcon#about to read 6, iclass 34, count 2 2006.238.07:42:01.72#ibcon#read 6, iclass 34, count 2 2006.238.07:42:01.72#ibcon#end of sib2, iclass 34, count 2 2006.238.07:42:01.72#ibcon#*mode == 0, iclass 34, count 2 2006.238.07:42:01.72#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.238.07:42:01.72#ibcon#[27=AT04-04\r\n] 2006.238.07:42:01.72#ibcon#*before write, iclass 34, count 2 2006.238.07:42:01.72#ibcon#enter sib2, iclass 34, count 2 2006.238.07:42:01.72#ibcon#flushed, iclass 34, count 2 2006.238.07:42:01.72#ibcon#about to write, iclass 34, count 2 2006.238.07:42:01.72#ibcon#wrote, iclass 34, count 2 2006.238.07:42:01.72#ibcon#about to read 3, iclass 34, count 2 2006.238.07:42:01.75#ibcon#read 3, iclass 34, count 2 2006.238.07:42:01.75#ibcon#about to read 4, iclass 34, count 2 2006.238.07:42:01.75#ibcon#read 4, iclass 34, count 2 2006.238.07:42:01.75#ibcon#about to read 5, iclass 34, count 2 2006.238.07:42:01.75#ibcon#read 5, iclass 34, count 2 2006.238.07:42:01.75#ibcon#about to read 6, iclass 34, count 2 2006.238.07:42:01.75#ibcon#read 6, iclass 34, count 2 2006.238.07:42:01.75#ibcon#end of sib2, iclass 34, count 2 2006.238.07:42:01.75#ibcon#*after write, iclass 34, count 2 2006.238.07:42:01.75#ibcon#*before return 0, iclass 34, count 2 2006.238.07:42:01.75#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:42:01.75#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:42:01.75#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.238.07:42:01.75#ibcon#ireg 7 cls_cnt 0 2006.238.07:42:01.75#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:42:01.87#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:42:01.87#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:42:01.87#ibcon#enter wrdev, iclass 34, count 0 2006.238.07:42:01.87#ibcon#first serial, iclass 34, count 0 2006.238.07:42:01.87#ibcon#enter sib2, iclass 34, count 0 2006.238.07:42:01.87#ibcon#flushed, iclass 34, count 0 2006.238.07:42:01.87#ibcon#about to write, iclass 34, count 0 2006.238.07:42:01.87#ibcon#wrote, iclass 34, count 0 2006.238.07:42:01.87#ibcon#about to read 3, iclass 34, count 0 2006.238.07:42:01.89#ibcon#read 3, iclass 34, count 0 2006.238.07:42:01.89#ibcon#about to read 4, iclass 34, count 0 2006.238.07:42:01.89#ibcon#read 4, iclass 34, count 0 2006.238.07:42:01.89#ibcon#about to read 5, iclass 34, count 0 2006.238.07:42:01.89#ibcon#read 5, iclass 34, count 0 2006.238.07:42:01.89#ibcon#about to read 6, iclass 34, count 0 2006.238.07:42:01.89#ibcon#read 6, iclass 34, count 0 2006.238.07:42:01.89#ibcon#end of sib2, iclass 34, count 0 2006.238.07:42:01.89#ibcon#*mode == 0, iclass 34, count 0 2006.238.07:42:01.89#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.07:42:01.89#ibcon#[27=USB\r\n] 2006.238.07:42:01.89#ibcon#*before write, iclass 34, count 0 2006.238.07:42:01.89#ibcon#enter sib2, iclass 34, count 0 2006.238.07:42:01.89#ibcon#flushed, iclass 34, count 0 2006.238.07:42:01.89#ibcon#about to write, iclass 34, count 0 2006.238.07:42:01.89#ibcon#wrote, iclass 34, count 0 2006.238.07:42:01.89#ibcon#about to read 3, iclass 34, count 0 2006.238.07:42:01.92#ibcon#read 3, iclass 34, count 0 2006.238.07:42:01.92#ibcon#about to read 4, iclass 34, count 0 2006.238.07:42:01.92#ibcon#read 4, iclass 34, count 0 2006.238.07:42:01.92#ibcon#about to read 5, iclass 34, count 0 2006.238.07:42:01.92#ibcon#read 5, iclass 34, count 0 2006.238.07:42:01.92#ibcon#about to read 6, iclass 34, count 0 2006.238.07:42:01.92#ibcon#read 6, iclass 34, count 0 2006.238.07:42:01.92#ibcon#end of sib2, iclass 34, count 0 2006.238.07:42:01.92#ibcon#*after write, iclass 34, count 0 2006.238.07:42:01.92#ibcon#*before return 0, iclass 34, count 0 2006.238.07:42:01.92#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:42:01.92#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:42:01.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.07:42:01.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.07:42:01.92$vc4f8/vblo=5,744.99 2006.238.07:42:01.92#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.07:42:01.92#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.07:42:01.92#ibcon#ireg 17 cls_cnt 0 2006.238.07:42:01.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:42:01.92#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:42:01.92#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:42:01.92#ibcon#enter wrdev, iclass 36, count 0 2006.238.07:42:01.92#ibcon#first serial, iclass 36, count 0 2006.238.07:42:01.92#ibcon#enter sib2, iclass 36, count 0 2006.238.07:42:01.92#ibcon#flushed, iclass 36, count 0 2006.238.07:42:01.92#ibcon#about to write, iclass 36, count 0 2006.238.07:42:01.92#ibcon#wrote, iclass 36, count 0 2006.238.07:42:01.92#ibcon#about to read 3, iclass 36, count 0 2006.238.07:42:01.94#ibcon#read 3, iclass 36, count 0 2006.238.07:42:01.94#ibcon#about to read 4, iclass 36, count 0 2006.238.07:42:01.94#ibcon#read 4, iclass 36, count 0 2006.238.07:42:01.94#ibcon#about to read 5, iclass 36, count 0 2006.238.07:42:01.94#ibcon#read 5, iclass 36, count 0 2006.238.07:42:01.94#ibcon#about to read 6, iclass 36, count 0 2006.238.07:42:01.94#ibcon#read 6, iclass 36, count 0 2006.238.07:42:01.94#ibcon#end of sib2, iclass 36, count 0 2006.238.07:42:01.94#ibcon#*mode == 0, iclass 36, count 0 2006.238.07:42:01.94#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.07:42:01.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:42:01.94#ibcon#*before write, iclass 36, count 0 2006.238.07:42:01.94#ibcon#enter sib2, iclass 36, count 0 2006.238.07:42:01.94#ibcon#flushed, iclass 36, count 0 2006.238.07:42:01.94#ibcon#about to write, iclass 36, count 0 2006.238.07:42:01.94#ibcon#wrote, iclass 36, count 0 2006.238.07:42:01.94#ibcon#about to read 3, iclass 36, count 0 2006.238.07:42:01.98#ibcon#read 3, iclass 36, count 0 2006.238.07:42:01.98#ibcon#about to read 4, iclass 36, count 0 2006.238.07:42:01.98#ibcon#read 4, iclass 36, count 0 2006.238.07:42:01.98#ibcon#about to read 5, iclass 36, count 0 2006.238.07:42:01.98#ibcon#read 5, iclass 36, count 0 2006.238.07:42:01.98#ibcon#about to read 6, iclass 36, count 0 2006.238.07:42:01.98#ibcon#read 6, iclass 36, count 0 2006.238.07:42:01.98#ibcon#end of sib2, iclass 36, count 0 2006.238.07:42:01.98#ibcon#*after write, iclass 36, count 0 2006.238.07:42:01.98#ibcon#*before return 0, iclass 36, count 0 2006.238.07:42:01.98#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:42:01.98#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:42:01.98#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.07:42:01.98#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.07:42:01.98$vc4f8/vb=5,4 2006.238.07:42:01.98#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.238.07:42:01.98#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.238.07:42:01.98#ibcon#ireg 11 cls_cnt 2 2006.238.07:42:01.98#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:42:02.04#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:42:02.04#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:42:02.04#ibcon#enter wrdev, iclass 38, count 2 2006.238.07:42:02.04#ibcon#first serial, iclass 38, count 2 2006.238.07:42:02.04#ibcon#enter sib2, iclass 38, count 2 2006.238.07:42:02.04#ibcon#flushed, iclass 38, count 2 2006.238.07:42:02.04#ibcon#about to write, iclass 38, count 2 2006.238.07:42:02.04#ibcon#wrote, iclass 38, count 2 2006.238.07:42:02.04#ibcon#about to read 3, iclass 38, count 2 2006.238.07:42:02.06#ibcon#read 3, iclass 38, count 2 2006.238.07:42:02.06#ibcon#about to read 4, iclass 38, count 2 2006.238.07:42:02.06#ibcon#read 4, iclass 38, count 2 2006.238.07:42:02.06#ibcon#about to read 5, iclass 38, count 2 2006.238.07:42:02.06#ibcon#read 5, iclass 38, count 2 2006.238.07:42:02.06#ibcon#about to read 6, iclass 38, count 2 2006.238.07:42:02.06#ibcon#read 6, iclass 38, count 2 2006.238.07:42:02.06#ibcon#end of sib2, iclass 38, count 2 2006.238.07:42:02.06#ibcon#*mode == 0, iclass 38, count 2 2006.238.07:42:02.06#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.238.07:42:02.06#ibcon#[27=AT05-04\r\n] 2006.238.07:42:02.06#ibcon#*before write, iclass 38, count 2 2006.238.07:42:02.06#ibcon#enter sib2, iclass 38, count 2 2006.238.07:42:02.06#ibcon#flushed, iclass 38, count 2 2006.238.07:42:02.06#ibcon#about to write, iclass 38, count 2 2006.238.07:42:02.06#ibcon#wrote, iclass 38, count 2 2006.238.07:42:02.06#ibcon#about to read 3, iclass 38, count 2 2006.238.07:42:02.09#ibcon#read 3, iclass 38, count 2 2006.238.07:42:02.09#ibcon#about to read 4, iclass 38, count 2 2006.238.07:42:02.09#ibcon#read 4, iclass 38, count 2 2006.238.07:42:02.09#ibcon#about to read 5, iclass 38, count 2 2006.238.07:42:02.09#ibcon#read 5, iclass 38, count 2 2006.238.07:42:02.09#ibcon#about to read 6, iclass 38, count 2 2006.238.07:42:02.09#ibcon#read 6, iclass 38, count 2 2006.238.07:42:02.09#ibcon#end of sib2, iclass 38, count 2 2006.238.07:42:02.09#ibcon#*after write, iclass 38, count 2 2006.238.07:42:02.09#ibcon#*before return 0, iclass 38, count 2 2006.238.07:42:02.09#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:42:02.09#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:42:02.09#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.238.07:42:02.09#ibcon#ireg 7 cls_cnt 0 2006.238.07:42:02.09#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:42:02.21#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:42:02.21#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:42:02.21#ibcon#enter wrdev, iclass 38, count 0 2006.238.07:42:02.21#ibcon#first serial, iclass 38, count 0 2006.238.07:42:02.21#ibcon#enter sib2, iclass 38, count 0 2006.238.07:42:02.21#ibcon#flushed, iclass 38, count 0 2006.238.07:42:02.21#ibcon#about to write, iclass 38, count 0 2006.238.07:42:02.21#ibcon#wrote, iclass 38, count 0 2006.238.07:42:02.21#ibcon#about to read 3, iclass 38, count 0 2006.238.07:42:02.23#ibcon#read 3, iclass 38, count 0 2006.238.07:42:02.23#ibcon#about to read 4, iclass 38, count 0 2006.238.07:42:02.23#ibcon#read 4, iclass 38, count 0 2006.238.07:42:02.23#ibcon#about to read 5, iclass 38, count 0 2006.238.07:42:02.23#ibcon#read 5, iclass 38, count 0 2006.238.07:42:02.23#ibcon#about to read 6, iclass 38, count 0 2006.238.07:42:02.23#ibcon#read 6, iclass 38, count 0 2006.238.07:42:02.23#ibcon#end of sib2, iclass 38, count 0 2006.238.07:42:02.23#ibcon#*mode == 0, iclass 38, count 0 2006.238.07:42:02.23#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.07:42:02.23#ibcon#[27=USB\r\n] 2006.238.07:42:02.23#ibcon#*before write, iclass 38, count 0 2006.238.07:42:02.23#ibcon#enter sib2, iclass 38, count 0 2006.238.07:42:02.23#ibcon#flushed, iclass 38, count 0 2006.238.07:42:02.23#ibcon#about to write, iclass 38, count 0 2006.238.07:42:02.23#ibcon#wrote, iclass 38, count 0 2006.238.07:42:02.23#ibcon#about to read 3, iclass 38, count 0 2006.238.07:42:02.26#ibcon#read 3, iclass 38, count 0 2006.238.07:42:02.26#ibcon#about to read 4, iclass 38, count 0 2006.238.07:42:02.26#ibcon#read 4, iclass 38, count 0 2006.238.07:42:02.26#ibcon#about to read 5, iclass 38, count 0 2006.238.07:42:02.26#ibcon#read 5, iclass 38, count 0 2006.238.07:42:02.26#ibcon#about to read 6, iclass 38, count 0 2006.238.07:42:02.26#ibcon#read 6, iclass 38, count 0 2006.238.07:42:02.26#ibcon#end of sib2, iclass 38, count 0 2006.238.07:42:02.26#ibcon#*after write, iclass 38, count 0 2006.238.07:42:02.26#ibcon#*before return 0, iclass 38, count 0 2006.238.07:42:02.26#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:42:02.26#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:42:02.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.07:42:02.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.07:42:02.26$vc4f8/vblo=6,752.99 2006.238.07:42:02.26#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.07:42:02.26#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.07:42:02.26#ibcon#ireg 17 cls_cnt 0 2006.238.07:42:02.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:42:02.26#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:42:02.26#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:42:02.26#ibcon#enter wrdev, iclass 40, count 0 2006.238.07:42:02.26#ibcon#first serial, iclass 40, count 0 2006.238.07:42:02.26#ibcon#enter sib2, iclass 40, count 0 2006.238.07:42:02.26#ibcon#flushed, iclass 40, count 0 2006.238.07:42:02.26#ibcon#about to write, iclass 40, count 0 2006.238.07:42:02.26#ibcon#wrote, iclass 40, count 0 2006.238.07:42:02.26#ibcon#about to read 3, iclass 40, count 0 2006.238.07:42:02.28#ibcon#read 3, iclass 40, count 0 2006.238.07:42:02.28#ibcon#about to read 4, iclass 40, count 0 2006.238.07:42:02.28#ibcon#read 4, iclass 40, count 0 2006.238.07:42:02.28#ibcon#about to read 5, iclass 40, count 0 2006.238.07:42:02.28#ibcon#read 5, iclass 40, count 0 2006.238.07:42:02.28#ibcon#about to read 6, iclass 40, count 0 2006.238.07:42:02.28#ibcon#read 6, iclass 40, count 0 2006.238.07:42:02.28#ibcon#end of sib2, iclass 40, count 0 2006.238.07:42:02.28#ibcon#*mode == 0, iclass 40, count 0 2006.238.07:42:02.28#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.07:42:02.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:42:02.28#ibcon#*before write, iclass 40, count 0 2006.238.07:42:02.28#ibcon#enter sib2, iclass 40, count 0 2006.238.07:42:02.28#ibcon#flushed, iclass 40, count 0 2006.238.07:42:02.28#ibcon#about to write, iclass 40, count 0 2006.238.07:42:02.28#ibcon#wrote, iclass 40, count 0 2006.238.07:42:02.28#ibcon#about to read 3, iclass 40, count 0 2006.238.07:42:02.32#ibcon#read 3, iclass 40, count 0 2006.238.07:42:02.32#ibcon#about to read 4, iclass 40, count 0 2006.238.07:42:02.32#ibcon#read 4, iclass 40, count 0 2006.238.07:42:02.32#ibcon#about to read 5, iclass 40, count 0 2006.238.07:42:02.32#ibcon#read 5, iclass 40, count 0 2006.238.07:42:02.32#ibcon#about to read 6, iclass 40, count 0 2006.238.07:42:02.32#ibcon#read 6, iclass 40, count 0 2006.238.07:42:02.32#ibcon#end of sib2, iclass 40, count 0 2006.238.07:42:02.32#ibcon#*after write, iclass 40, count 0 2006.238.07:42:02.32#ibcon#*before return 0, iclass 40, count 0 2006.238.07:42:02.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:42:02.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:42:02.32#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.07:42:02.32#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.07:42:02.32$vc4f8/vb=6,4 2006.238.07:42:02.32#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.238.07:42:02.32#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.238.07:42:02.32#ibcon#ireg 11 cls_cnt 2 2006.238.07:42:02.32#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:42:02.38#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:42:02.38#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:42:02.38#ibcon#enter wrdev, iclass 4, count 2 2006.238.07:42:02.38#ibcon#first serial, iclass 4, count 2 2006.238.07:42:02.38#ibcon#enter sib2, iclass 4, count 2 2006.238.07:42:02.38#ibcon#flushed, iclass 4, count 2 2006.238.07:42:02.38#ibcon#about to write, iclass 4, count 2 2006.238.07:42:02.38#ibcon#wrote, iclass 4, count 2 2006.238.07:42:02.38#ibcon#about to read 3, iclass 4, count 2 2006.238.07:42:02.40#ibcon#read 3, iclass 4, count 2 2006.238.07:42:02.40#ibcon#about to read 4, iclass 4, count 2 2006.238.07:42:02.40#ibcon#read 4, iclass 4, count 2 2006.238.07:42:02.40#ibcon#about to read 5, iclass 4, count 2 2006.238.07:42:02.40#ibcon#read 5, iclass 4, count 2 2006.238.07:42:02.40#ibcon#about to read 6, iclass 4, count 2 2006.238.07:42:02.40#ibcon#read 6, iclass 4, count 2 2006.238.07:42:02.40#ibcon#end of sib2, iclass 4, count 2 2006.238.07:42:02.40#ibcon#*mode == 0, iclass 4, count 2 2006.238.07:42:02.40#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.238.07:42:02.40#ibcon#[27=AT06-04\r\n] 2006.238.07:42:02.40#ibcon#*before write, iclass 4, count 2 2006.238.07:42:02.40#ibcon#enter sib2, iclass 4, count 2 2006.238.07:42:02.40#ibcon#flushed, iclass 4, count 2 2006.238.07:42:02.40#ibcon#about to write, iclass 4, count 2 2006.238.07:42:02.40#ibcon#wrote, iclass 4, count 2 2006.238.07:42:02.40#ibcon#about to read 3, iclass 4, count 2 2006.238.07:42:02.43#ibcon#read 3, iclass 4, count 2 2006.238.07:42:02.43#ibcon#about to read 4, iclass 4, count 2 2006.238.07:42:02.43#ibcon#read 4, iclass 4, count 2 2006.238.07:42:02.43#ibcon#about to read 5, iclass 4, count 2 2006.238.07:42:02.43#ibcon#read 5, iclass 4, count 2 2006.238.07:42:02.43#ibcon#about to read 6, iclass 4, count 2 2006.238.07:42:02.43#ibcon#read 6, iclass 4, count 2 2006.238.07:42:02.43#ibcon#end of sib2, iclass 4, count 2 2006.238.07:42:02.43#ibcon#*after write, iclass 4, count 2 2006.238.07:42:02.43#ibcon#*before return 0, iclass 4, count 2 2006.238.07:42:02.43#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:42:02.43#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:42:02.43#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.238.07:42:02.43#ibcon#ireg 7 cls_cnt 0 2006.238.07:42:02.43#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:42:02.55#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:42:02.55#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:42:02.55#ibcon#enter wrdev, iclass 4, count 0 2006.238.07:42:02.55#ibcon#first serial, iclass 4, count 0 2006.238.07:42:02.55#ibcon#enter sib2, iclass 4, count 0 2006.238.07:42:02.55#ibcon#flushed, iclass 4, count 0 2006.238.07:42:02.55#ibcon#about to write, iclass 4, count 0 2006.238.07:42:02.55#ibcon#wrote, iclass 4, count 0 2006.238.07:42:02.55#ibcon#about to read 3, iclass 4, count 0 2006.238.07:42:02.57#ibcon#read 3, iclass 4, count 0 2006.238.07:42:02.57#ibcon#about to read 4, iclass 4, count 0 2006.238.07:42:02.57#ibcon#read 4, iclass 4, count 0 2006.238.07:42:02.57#ibcon#about to read 5, iclass 4, count 0 2006.238.07:42:02.57#ibcon#read 5, iclass 4, count 0 2006.238.07:42:02.57#ibcon#about to read 6, iclass 4, count 0 2006.238.07:42:02.57#ibcon#read 6, iclass 4, count 0 2006.238.07:42:02.57#ibcon#end of sib2, iclass 4, count 0 2006.238.07:42:02.57#ibcon#*mode == 0, iclass 4, count 0 2006.238.07:42:02.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.07:42:02.57#ibcon#[27=USB\r\n] 2006.238.07:42:02.57#ibcon#*before write, iclass 4, count 0 2006.238.07:42:02.57#ibcon#enter sib2, iclass 4, count 0 2006.238.07:42:02.57#ibcon#flushed, iclass 4, count 0 2006.238.07:42:02.57#ibcon#about to write, iclass 4, count 0 2006.238.07:42:02.57#ibcon#wrote, iclass 4, count 0 2006.238.07:42:02.57#ibcon#about to read 3, iclass 4, count 0 2006.238.07:42:02.60#ibcon#read 3, iclass 4, count 0 2006.238.07:42:02.60#ibcon#about to read 4, iclass 4, count 0 2006.238.07:42:02.60#ibcon#read 4, iclass 4, count 0 2006.238.07:42:02.60#ibcon#about to read 5, iclass 4, count 0 2006.238.07:42:02.60#ibcon#read 5, iclass 4, count 0 2006.238.07:42:02.60#ibcon#about to read 6, iclass 4, count 0 2006.238.07:42:02.60#ibcon#read 6, iclass 4, count 0 2006.238.07:42:02.60#ibcon#end of sib2, iclass 4, count 0 2006.238.07:42:02.60#ibcon#*after write, iclass 4, count 0 2006.238.07:42:02.60#ibcon#*before return 0, iclass 4, count 0 2006.238.07:42:02.60#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:42:02.60#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:42:02.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.07:42:02.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.07:42:02.60$vc4f8/vabw=wide 2006.238.07:42:02.60#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.238.07:42:02.60#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.238.07:42:02.60#ibcon#ireg 8 cls_cnt 0 2006.238.07:42:02.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:42:02.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:42:02.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:42:02.60#ibcon#enter wrdev, iclass 6, count 0 2006.238.07:42:02.60#ibcon#first serial, iclass 6, count 0 2006.238.07:42:02.60#ibcon#enter sib2, iclass 6, count 0 2006.238.07:42:02.60#ibcon#flushed, iclass 6, count 0 2006.238.07:42:02.60#ibcon#about to write, iclass 6, count 0 2006.238.07:42:02.60#ibcon#wrote, iclass 6, count 0 2006.238.07:42:02.60#ibcon#about to read 3, iclass 6, count 0 2006.238.07:42:02.62#ibcon#read 3, iclass 6, count 0 2006.238.07:42:02.62#ibcon#about to read 4, iclass 6, count 0 2006.238.07:42:02.62#ibcon#read 4, iclass 6, count 0 2006.238.07:42:02.62#ibcon#about to read 5, iclass 6, count 0 2006.238.07:42:02.62#ibcon#read 5, iclass 6, count 0 2006.238.07:42:02.62#ibcon#about to read 6, iclass 6, count 0 2006.238.07:42:02.62#ibcon#read 6, iclass 6, count 0 2006.238.07:42:02.62#ibcon#end of sib2, iclass 6, count 0 2006.238.07:42:02.62#ibcon#*mode == 0, iclass 6, count 0 2006.238.07:42:02.62#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.07:42:02.62#ibcon#[25=BW32\r\n] 2006.238.07:42:02.62#ibcon#*before write, iclass 6, count 0 2006.238.07:42:02.62#ibcon#enter sib2, iclass 6, count 0 2006.238.07:42:02.62#ibcon#flushed, iclass 6, count 0 2006.238.07:42:02.62#ibcon#about to write, iclass 6, count 0 2006.238.07:42:02.62#ibcon#wrote, iclass 6, count 0 2006.238.07:42:02.62#ibcon#about to read 3, iclass 6, count 0 2006.238.07:42:02.65#ibcon#read 3, iclass 6, count 0 2006.238.07:42:02.65#ibcon#about to read 4, iclass 6, count 0 2006.238.07:42:02.65#ibcon#read 4, iclass 6, count 0 2006.238.07:42:02.65#ibcon#about to read 5, iclass 6, count 0 2006.238.07:42:02.65#ibcon#read 5, iclass 6, count 0 2006.238.07:42:02.65#ibcon#about to read 6, iclass 6, count 0 2006.238.07:42:02.65#ibcon#read 6, iclass 6, count 0 2006.238.07:42:02.65#ibcon#end of sib2, iclass 6, count 0 2006.238.07:42:02.65#ibcon#*after write, iclass 6, count 0 2006.238.07:42:02.65#ibcon#*before return 0, iclass 6, count 0 2006.238.07:42:02.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:42:02.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:42:02.65#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.07:42:02.65#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.07:42:02.65$vc4f8/vbbw=wide 2006.238.07:42:02.65#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.07:42:02.65#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.07:42:02.65#ibcon#ireg 8 cls_cnt 0 2006.238.07:42:02.65#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:42:02.72#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:42:02.72#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:42:02.72#ibcon#enter wrdev, iclass 10, count 0 2006.238.07:42:02.72#ibcon#first serial, iclass 10, count 0 2006.238.07:42:02.72#ibcon#enter sib2, iclass 10, count 0 2006.238.07:42:02.72#ibcon#flushed, iclass 10, count 0 2006.238.07:42:02.72#ibcon#about to write, iclass 10, count 0 2006.238.07:42:02.72#ibcon#wrote, iclass 10, count 0 2006.238.07:42:02.72#ibcon#about to read 3, iclass 10, count 0 2006.238.07:42:02.74#ibcon#read 3, iclass 10, count 0 2006.238.07:42:02.74#ibcon#about to read 4, iclass 10, count 0 2006.238.07:42:02.74#ibcon#read 4, iclass 10, count 0 2006.238.07:42:02.74#ibcon#about to read 5, iclass 10, count 0 2006.238.07:42:02.74#ibcon#read 5, iclass 10, count 0 2006.238.07:42:02.74#ibcon#about to read 6, iclass 10, count 0 2006.238.07:42:02.74#ibcon#read 6, iclass 10, count 0 2006.238.07:42:02.74#ibcon#end of sib2, iclass 10, count 0 2006.238.07:42:02.74#ibcon#*mode == 0, iclass 10, count 0 2006.238.07:42:02.74#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.07:42:02.74#ibcon#[27=BW32\r\n] 2006.238.07:42:02.74#ibcon#*before write, iclass 10, count 0 2006.238.07:42:02.74#ibcon#enter sib2, iclass 10, count 0 2006.238.07:42:02.74#ibcon#flushed, iclass 10, count 0 2006.238.07:42:02.74#ibcon#about to write, iclass 10, count 0 2006.238.07:42:02.74#ibcon#wrote, iclass 10, count 0 2006.238.07:42:02.74#ibcon#about to read 3, iclass 10, count 0 2006.238.07:42:02.77#ibcon#read 3, iclass 10, count 0 2006.238.07:42:02.77#ibcon#about to read 4, iclass 10, count 0 2006.238.07:42:02.77#ibcon#read 4, iclass 10, count 0 2006.238.07:42:02.77#ibcon#about to read 5, iclass 10, count 0 2006.238.07:42:02.77#ibcon#read 5, iclass 10, count 0 2006.238.07:42:02.77#ibcon#about to read 6, iclass 10, count 0 2006.238.07:42:02.77#ibcon#read 6, iclass 10, count 0 2006.238.07:42:02.77#ibcon#end of sib2, iclass 10, count 0 2006.238.07:42:02.77#ibcon#*after write, iclass 10, count 0 2006.238.07:42:02.77#ibcon#*before return 0, iclass 10, count 0 2006.238.07:42:02.77#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:42:02.77#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:42:02.77#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.07:42:02.77#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.07:42:02.77$4f8m12a/ifd4f 2006.238.07:42:02.77$ifd4f/lo= 2006.238.07:42:02.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:42:02.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:42:02.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:42:02.77$ifd4f/patch= 2006.238.07:42:02.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:42:02.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:42:02.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:42:02.77$4f8m12a/"form=m,16.000,1:2 2006.238.07:42:02.77$4f8m12a/"tpicd 2006.238.07:42:02.77$4f8m12a/echo=off 2006.238.07:42:02.77$4f8m12a/xlog=off 2006.238.07:42:02.77:!2006.238.07:42:30 2006.238.07:42:10.13#trakl#Source acquired 2006.238.07:42:12.13#flagr#flagr/antenna,acquired 2006.238.07:42:30.00:preob 2006.238.07:42:31.13/onsource/TRACKING 2006.238.07:42:31.13:!2006.238.07:42:40 2006.238.07:42:40.00:data_valid=on 2006.238.07:42:40.00:midob 2006.238.07:42:40.13/onsource/TRACKING 2006.238.07:42:40.13/wx/25.30,1012.2,87 2006.238.07:42:40.22/cable/+6.4193E-03 2006.238.07:42:41.31/va/01,08,usb,yes,32,33 2006.238.07:42:41.31/va/02,07,usb,yes,32,33 2006.238.07:42:41.31/va/03,07,usb,yes,30,30 2006.238.07:42:41.31/va/04,07,usb,yes,33,36 2006.238.07:42:41.31/va/05,08,usb,yes,30,31 2006.238.07:42:41.31/va/06,07,usb,yes,32,32 2006.238.07:42:41.31/va/07,07,usb,yes,32,32 2006.238.07:42:41.31/va/08,07,usb,yes,35,35 2006.238.07:42:41.54/valo/01,532.99,yes,locked 2006.238.07:42:41.54/valo/02,572.99,yes,locked 2006.238.07:42:41.54/valo/03,672.99,yes,locked 2006.238.07:42:41.54/valo/04,832.99,yes,locked 2006.238.07:42:41.54/valo/05,652.99,yes,locked 2006.238.07:42:41.54/valo/06,772.99,yes,locked 2006.238.07:42:41.54/valo/07,832.99,yes,locked 2006.238.07:42:41.54/valo/08,852.99,yes,locked 2006.238.07:42:42.63/vb/01,04,usb,yes,30,29 2006.238.07:42:42.63/vb/02,04,usb,yes,32,34 2006.238.07:42:42.63/vb/03,04,usb,yes,29,32 2006.238.07:42:42.63/vb/04,04,usb,yes,29,30 2006.238.07:42:42.63/vb/05,04,usb,yes,28,32 2006.238.07:42:42.63/vb/06,04,usb,yes,29,32 2006.238.07:42:42.63/vb/07,04,usb,yes,31,31 2006.238.07:42:42.63/vb/08,04,usb,yes,28,32 2006.238.07:42:42.87/vblo/01,632.99,yes,locked 2006.238.07:42:42.87/vblo/02,640.99,yes,locked 2006.238.07:42:42.87/vblo/03,656.99,yes,locked 2006.238.07:42:42.87/vblo/04,712.99,yes,locked 2006.238.07:42:42.87/vblo/05,744.99,yes,locked 2006.238.07:42:42.87/vblo/06,752.99,yes,locked 2006.238.07:42:42.87/vblo/07,734.99,yes,locked 2006.238.07:42:42.87/vblo/08,744.99,yes,locked 2006.238.07:42:43.02/vabw/8 2006.238.07:42:43.17/vbbw/8 2006.238.07:42:43.26/xfe/off,on,14.7 2006.238.07:42:43.64/ifatt/23,28,28,28 2006.238.07:42:44.08/fmout-gps/S +4.39E-07 2006.238.07:42:44.12:!2006.238.07:43:40 2006.238.07:43:40.00:data_valid=off 2006.238.07:43:40.00:postob 2006.238.07:43:40.18/cable/+6.4167E-03 2006.238.07:43:40.18/wx/25.30,1012.2,87 2006.238.07:43:41.08/fmout-gps/S +4.37E-07 2006.238.07:43:41.08:scan_name=238-0744,k06238,60 2006.238.07:43:41.09:source=0059+581,010245.76,582411.1,2000.0,cw 2006.238.07:43:41.13#flagr#flagr/antenna,new-source 2006.238.07:43:42.13:checkk5 2006.238.07:43:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:43:42.88/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:43:43.28/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:43:43.66/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:43:44.03/chk_obsdata//k5ts1/T2380742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:43:44.41/chk_obsdata//k5ts2/T2380742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:43:44.78/chk_obsdata//k5ts3/T2380742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:43:45.15/chk_obsdata//k5ts4/T2380742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:43:45.84/k5log//k5ts1_log_newline 2006.238.07:43:46.52/k5log//k5ts2_log_newline 2006.238.07:43:47.21/k5log//k5ts3_log_newline 2006.238.07:43:47.90/k5log//k5ts4_log_newline 2006.238.07:43:47.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:43:47.92:4f8m12a=1 2006.238.07:43:47.93$4f8m12a/echo=on 2006.238.07:43:47.93$4f8m12a/pcalon 2006.238.07:43:47.93$pcalon/"no phase cal control is implemented here 2006.238.07:43:47.93$4f8m12a/"tpicd=stop 2006.238.07:43:47.93$4f8m12a/vc4f8 2006.238.07:43:47.93$vc4f8/valo=1,532.99 2006.238.07:43:47.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.07:43:47.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.07:43:47.93#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:47.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:43:47.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:43:47.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:43:47.93#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:43:47.93#ibcon#first serial, iclass 21, count 0 2006.238.07:43:47.93#ibcon#enter sib2, iclass 21, count 0 2006.238.07:43:47.93#ibcon#flushed, iclass 21, count 0 2006.238.07:43:47.93#ibcon#about to write, iclass 21, count 0 2006.238.07:43:47.93#ibcon#wrote, iclass 21, count 0 2006.238.07:43:47.93#ibcon#about to read 3, iclass 21, count 0 2006.238.07:43:47.97#ibcon#read 3, iclass 21, count 0 2006.238.07:43:47.97#ibcon#about to read 4, iclass 21, count 0 2006.238.07:43:47.97#ibcon#read 4, iclass 21, count 0 2006.238.07:43:47.97#ibcon#about to read 5, iclass 21, count 0 2006.238.07:43:47.97#ibcon#read 5, iclass 21, count 0 2006.238.07:43:47.97#ibcon#about to read 6, iclass 21, count 0 2006.238.07:43:47.97#ibcon#read 6, iclass 21, count 0 2006.238.07:43:47.97#ibcon#end of sib2, iclass 21, count 0 2006.238.07:43:47.97#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:43:47.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:43:47.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:43:47.97#ibcon#*before write, iclass 21, count 0 2006.238.07:43:47.97#ibcon#enter sib2, iclass 21, count 0 2006.238.07:43:47.97#ibcon#flushed, iclass 21, count 0 2006.238.07:43:47.97#ibcon#about to write, iclass 21, count 0 2006.238.07:43:47.97#ibcon#wrote, iclass 21, count 0 2006.238.07:43:47.97#ibcon#about to read 3, iclass 21, count 0 2006.238.07:43:48.02#ibcon#read 3, iclass 21, count 0 2006.238.07:43:48.02#ibcon#about to read 4, iclass 21, count 0 2006.238.07:43:48.02#ibcon#read 4, iclass 21, count 0 2006.238.07:43:48.02#ibcon#about to read 5, iclass 21, count 0 2006.238.07:43:48.02#ibcon#read 5, iclass 21, count 0 2006.238.07:43:48.02#ibcon#about to read 6, iclass 21, count 0 2006.238.07:43:48.02#ibcon#read 6, iclass 21, count 0 2006.238.07:43:48.02#ibcon#end of sib2, iclass 21, count 0 2006.238.07:43:48.02#ibcon#*after write, iclass 21, count 0 2006.238.07:43:48.02#ibcon#*before return 0, iclass 21, count 0 2006.238.07:43:48.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:43:48.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:43:48.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:43:48.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:43:48.02$vc4f8/va=1,8 2006.238.07:43:48.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.238.07:43:48.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.238.07:43:48.02#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:48.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:43:48.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:43:48.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:43:48.02#ibcon#enter wrdev, iclass 23, count 2 2006.238.07:43:48.02#ibcon#first serial, iclass 23, count 2 2006.238.07:43:48.02#ibcon#enter sib2, iclass 23, count 2 2006.238.07:43:48.02#ibcon#flushed, iclass 23, count 2 2006.238.07:43:48.02#ibcon#about to write, iclass 23, count 2 2006.238.07:43:48.02#ibcon#wrote, iclass 23, count 2 2006.238.07:43:48.02#ibcon#about to read 3, iclass 23, count 2 2006.238.07:43:48.04#ibcon#read 3, iclass 23, count 2 2006.238.07:43:48.04#ibcon#about to read 4, iclass 23, count 2 2006.238.07:43:48.04#ibcon#read 4, iclass 23, count 2 2006.238.07:43:48.04#ibcon#about to read 5, iclass 23, count 2 2006.238.07:43:48.04#ibcon#read 5, iclass 23, count 2 2006.238.07:43:48.04#ibcon#about to read 6, iclass 23, count 2 2006.238.07:43:48.04#ibcon#read 6, iclass 23, count 2 2006.238.07:43:48.04#ibcon#end of sib2, iclass 23, count 2 2006.238.07:43:48.04#ibcon#*mode == 0, iclass 23, count 2 2006.238.07:43:48.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.238.07:43:48.04#ibcon#[25=AT01-08\r\n] 2006.238.07:43:48.04#ibcon#*before write, iclass 23, count 2 2006.238.07:43:48.04#ibcon#enter sib2, iclass 23, count 2 2006.238.07:43:48.04#ibcon#flushed, iclass 23, count 2 2006.238.07:43:48.04#ibcon#about to write, iclass 23, count 2 2006.238.07:43:48.04#ibcon#wrote, iclass 23, count 2 2006.238.07:43:48.04#ibcon#about to read 3, iclass 23, count 2 2006.238.07:43:48.07#ibcon#read 3, iclass 23, count 2 2006.238.07:43:48.07#ibcon#about to read 4, iclass 23, count 2 2006.238.07:43:48.07#ibcon#read 4, iclass 23, count 2 2006.238.07:43:48.07#ibcon#about to read 5, iclass 23, count 2 2006.238.07:43:48.07#ibcon#read 5, iclass 23, count 2 2006.238.07:43:48.07#ibcon#about to read 6, iclass 23, count 2 2006.238.07:43:48.07#ibcon#read 6, iclass 23, count 2 2006.238.07:43:48.07#ibcon#end of sib2, iclass 23, count 2 2006.238.07:43:48.07#ibcon#*after write, iclass 23, count 2 2006.238.07:43:48.07#ibcon#*before return 0, iclass 23, count 2 2006.238.07:43:48.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:43:48.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:43:48.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.238.07:43:48.07#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:48.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:43:48.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:43:48.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:43:48.19#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:43:48.19#ibcon#first serial, iclass 23, count 0 2006.238.07:43:48.19#ibcon#enter sib2, iclass 23, count 0 2006.238.07:43:48.19#ibcon#flushed, iclass 23, count 0 2006.238.07:43:48.19#ibcon#about to write, iclass 23, count 0 2006.238.07:43:48.19#ibcon#wrote, iclass 23, count 0 2006.238.07:43:48.19#ibcon#about to read 3, iclass 23, count 0 2006.238.07:43:48.21#ibcon#read 3, iclass 23, count 0 2006.238.07:43:48.21#ibcon#about to read 4, iclass 23, count 0 2006.238.07:43:48.21#ibcon#read 4, iclass 23, count 0 2006.238.07:43:48.21#ibcon#about to read 5, iclass 23, count 0 2006.238.07:43:48.21#ibcon#read 5, iclass 23, count 0 2006.238.07:43:48.21#ibcon#about to read 6, iclass 23, count 0 2006.238.07:43:48.21#ibcon#read 6, iclass 23, count 0 2006.238.07:43:48.21#ibcon#end of sib2, iclass 23, count 0 2006.238.07:43:48.21#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:43:48.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:43:48.21#ibcon#[25=USB\r\n] 2006.238.07:43:48.21#ibcon#*before write, iclass 23, count 0 2006.238.07:43:48.21#ibcon#enter sib2, iclass 23, count 0 2006.238.07:43:48.21#ibcon#flushed, iclass 23, count 0 2006.238.07:43:48.21#ibcon#about to write, iclass 23, count 0 2006.238.07:43:48.21#ibcon#wrote, iclass 23, count 0 2006.238.07:43:48.21#ibcon#about to read 3, iclass 23, count 0 2006.238.07:43:48.24#ibcon#read 3, iclass 23, count 0 2006.238.07:43:48.24#ibcon#about to read 4, iclass 23, count 0 2006.238.07:43:48.24#ibcon#read 4, iclass 23, count 0 2006.238.07:43:48.24#ibcon#about to read 5, iclass 23, count 0 2006.238.07:43:48.24#ibcon#read 5, iclass 23, count 0 2006.238.07:43:48.24#ibcon#about to read 6, iclass 23, count 0 2006.238.07:43:48.24#ibcon#read 6, iclass 23, count 0 2006.238.07:43:48.24#ibcon#end of sib2, iclass 23, count 0 2006.238.07:43:48.24#ibcon#*after write, iclass 23, count 0 2006.238.07:43:48.24#ibcon#*before return 0, iclass 23, count 0 2006.238.07:43:48.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:43:48.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:43:48.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:43:48.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:43:48.24$vc4f8/valo=2,572.99 2006.238.07:43:48.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.07:43:48.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.07:43:48.24#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:48.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:43:48.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:43:48.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:43:48.24#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:43:48.24#ibcon#first serial, iclass 25, count 0 2006.238.07:43:48.24#ibcon#enter sib2, iclass 25, count 0 2006.238.07:43:48.24#ibcon#flushed, iclass 25, count 0 2006.238.07:43:48.24#ibcon#about to write, iclass 25, count 0 2006.238.07:43:48.24#ibcon#wrote, iclass 25, count 0 2006.238.07:43:48.24#ibcon#about to read 3, iclass 25, count 0 2006.238.07:43:48.26#ibcon#read 3, iclass 25, count 0 2006.238.07:43:48.26#ibcon#about to read 4, iclass 25, count 0 2006.238.07:43:48.26#ibcon#read 4, iclass 25, count 0 2006.238.07:43:48.26#ibcon#about to read 5, iclass 25, count 0 2006.238.07:43:48.26#ibcon#read 5, iclass 25, count 0 2006.238.07:43:48.26#ibcon#about to read 6, iclass 25, count 0 2006.238.07:43:48.26#ibcon#read 6, iclass 25, count 0 2006.238.07:43:48.26#ibcon#end of sib2, iclass 25, count 0 2006.238.07:43:48.26#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:43:48.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:43:48.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:43:48.26#ibcon#*before write, iclass 25, count 0 2006.238.07:43:48.26#ibcon#enter sib2, iclass 25, count 0 2006.238.07:43:48.26#ibcon#flushed, iclass 25, count 0 2006.238.07:43:48.26#ibcon#about to write, iclass 25, count 0 2006.238.07:43:48.26#ibcon#wrote, iclass 25, count 0 2006.238.07:43:48.26#ibcon#about to read 3, iclass 25, count 0 2006.238.07:43:48.30#ibcon#read 3, iclass 25, count 0 2006.238.07:43:48.30#ibcon#about to read 4, iclass 25, count 0 2006.238.07:43:48.30#ibcon#read 4, iclass 25, count 0 2006.238.07:43:48.30#ibcon#about to read 5, iclass 25, count 0 2006.238.07:43:48.30#ibcon#read 5, iclass 25, count 0 2006.238.07:43:48.30#ibcon#about to read 6, iclass 25, count 0 2006.238.07:43:48.30#ibcon#read 6, iclass 25, count 0 2006.238.07:43:48.30#ibcon#end of sib2, iclass 25, count 0 2006.238.07:43:48.30#ibcon#*after write, iclass 25, count 0 2006.238.07:43:48.30#ibcon#*before return 0, iclass 25, count 0 2006.238.07:43:48.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:43:48.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:43:48.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:43:48.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:43:48.30$vc4f8/va=2,7 2006.238.07:43:48.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.238.07:43:48.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.238.07:43:48.30#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:48.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:43:48.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:43:48.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:43:48.36#ibcon#enter wrdev, iclass 27, count 2 2006.238.07:43:48.36#ibcon#first serial, iclass 27, count 2 2006.238.07:43:48.36#ibcon#enter sib2, iclass 27, count 2 2006.238.07:43:48.36#ibcon#flushed, iclass 27, count 2 2006.238.07:43:48.36#ibcon#about to write, iclass 27, count 2 2006.238.07:43:48.36#ibcon#wrote, iclass 27, count 2 2006.238.07:43:48.36#ibcon#about to read 3, iclass 27, count 2 2006.238.07:43:48.38#ibcon#read 3, iclass 27, count 2 2006.238.07:43:48.38#ibcon#about to read 4, iclass 27, count 2 2006.238.07:43:48.38#ibcon#read 4, iclass 27, count 2 2006.238.07:43:48.38#ibcon#about to read 5, iclass 27, count 2 2006.238.07:43:48.38#ibcon#read 5, iclass 27, count 2 2006.238.07:43:48.38#ibcon#about to read 6, iclass 27, count 2 2006.238.07:43:48.38#ibcon#read 6, iclass 27, count 2 2006.238.07:43:48.38#ibcon#end of sib2, iclass 27, count 2 2006.238.07:43:48.38#ibcon#*mode == 0, iclass 27, count 2 2006.238.07:43:48.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.238.07:43:48.38#ibcon#[25=AT02-07\r\n] 2006.238.07:43:48.38#ibcon#*before write, iclass 27, count 2 2006.238.07:43:48.38#ibcon#enter sib2, iclass 27, count 2 2006.238.07:43:48.38#ibcon#flushed, iclass 27, count 2 2006.238.07:43:48.38#ibcon#about to write, iclass 27, count 2 2006.238.07:43:48.38#ibcon#wrote, iclass 27, count 2 2006.238.07:43:48.38#ibcon#about to read 3, iclass 27, count 2 2006.238.07:43:48.41#ibcon#read 3, iclass 27, count 2 2006.238.07:43:48.41#ibcon#about to read 4, iclass 27, count 2 2006.238.07:43:48.41#ibcon#read 4, iclass 27, count 2 2006.238.07:43:48.41#ibcon#about to read 5, iclass 27, count 2 2006.238.07:43:48.41#ibcon#read 5, iclass 27, count 2 2006.238.07:43:48.41#ibcon#about to read 6, iclass 27, count 2 2006.238.07:43:48.41#ibcon#read 6, iclass 27, count 2 2006.238.07:43:48.41#ibcon#end of sib2, iclass 27, count 2 2006.238.07:43:48.41#ibcon#*after write, iclass 27, count 2 2006.238.07:43:48.41#ibcon#*before return 0, iclass 27, count 2 2006.238.07:43:48.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:43:48.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:43:48.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.238.07:43:48.41#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:48.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:43:48.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:43:48.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:43:48.53#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:43:48.53#ibcon#first serial, iclass 27, count 0 2006.238.07:43:48.53#ibcon#enter sib2, iclass 27, count 0 2006.238.07:43:48.53#ibcon#flushed, iclass 27, count 0 2006.238.07:43:48.53#ibcon#about to write, iclass 27, count 0 2006.238.07:43:48.53#ibcon#wrote, iclass 27, count 0 2006.238.07:43:48.53#ibcon#about to read 3, iclass 27, count 0 2006.238.07:43:48.55#ibcon#read 3, iclass 27, count 0 2006.238.07:43:48.55#ibcon#about to read 4, iclass 27, count 0 2006.238.07:43:48.55#ibcon#read 4, iclass 27, count 0 2006.238.07:43:48.55#ibcon#about to read 5, iclass 27, count 0 2006.238.07:43:48.55#ibcon#read 5, iclass 27, count 0 2006.238.07:43:48.55#ibcon#about to read 6, iclass 27, count 0 2006.238.07:43:48.55#ibcon#read 6, iclass 27, count 0 2006.238.07:43:48.55#ibcon#end of sib2, iclass 27, count 0 2006.238.07:43:48.55#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:43:48.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:43:48.55#ibcon#[25=USB\r\n] 2006.238.07:43:48.55#ibcon#*before write, iclass 27, count 0 2006.238.07:43:48.55#ibcon#enter sib2, iclass 27, count 0 2006.238.07:43:48.55#ibcon#flushed, iclass 27, count 0 2006.238.07:43:48.55#ibcon#about to write, iclass 27, count 0 2006.238.07:43:48.55#ibcon#wrote, iclass 27, count 0 2006.238.07:43:48.55#ibcon#about to read 3, iclass 27, count 0 2006.238.07:43:48.58#ibcon#read 3, iclass 27, count 0 2006.238.07:43:48.58#ibcon#about to read 4, iclass 27, count 0 2006.238.07:43:48.58#ibcon#read 4, iclass 27, count 0 2006.238.07:43:48.58#ibcon#about to read 5, iclass 27, count 0 2006.238.07:43:48.58#ibcon#read 5, iclass 27, count 0 2006.238.07:43:48.58#ibcon#about to read 6, iclass 27, count 0 2006.238.07:43:48.58#ibcon#read 6, iclass 27, count 0 2006.238.07:43:48.58#ibcon#end of sib2, iclass 27, count 0 2006.238.07:43:48.58#ibcon#*after write, iclass 27, count 0 2006.238.07:43:48.58#ibcon#*before return 0, iclass 27, count 0 2006.238.07:43:48.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:43:48.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:43:48.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:43:48.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:43:48.58$vc4f8/valo=3,672.99 2006.238.07:43:48.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.238.07:43:48.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.238.07:43:48.58#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:48.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:43:48.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:43:48.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:43:48.58#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:43:48.58#ibcon#first serial, iclass 29, count 0 2006.238.07:43:48.58#ibcon#enter sib2, iclass 29, count 0 2006.238.07:43:48.58#ibcon#flushed, iclass 29, count 0 2006.238.07:43:48.58#ibcon#about to write, iclass 29, count 0 2006.238.07:43:48.58#ibcon#wrote, iclass 29, count 0 2006.238.07:43:48.58#ibcon#about to read 3, iclass 29, count 0 2006.238.07:43:48.60#ibcon#read 3, iclass 29, count 0 2006.238.07:43:48.60#ibcon#about to read 4, iclass 29, count 0 2006.238.07:43:48.60#ibcon#read 4, iclass 29, count 0 2006.238.07:43:48.60#ibcon#about to read 5, iclass 29, count 0 2006.238.07:43:48.60#ibcon#read 5, iclass 29, count 0 2006.238.07:43:48.60#ibcon#about to read 6, iclass 29, count 0 2006.238.07:43:48.60#ibcon#read 6, iclass 29, count 0 2006.238.07:43:48.60#ibcon#end of sib2, iclass 29, count 0 2006.238.07:43:48.60#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:43:48.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:43:48.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:43:48.60#ibcon#*before write, iclass 29, count 0 2006.238.07:43:48.60#ibcon#enter sib2, iclass 29, count 0 2006.238.07:43:48.60#ibcon#flushed, iclass 29, count 0 2006.238.07:43:48.60#ibcon#about to write, iclass 29, count 0 2006.238.07:43:48.60#ibcon#wrote, iclass 29, count 0 2006.238.07:43:48.60#ibcon#about to read 3, iclass 29, count 0 2006.238.07:43:48.64#ibcon#read 3, iclass 29, count 0 2006.238.07:43:48.64#ibcon#about to read 4, iclass 29, count 0 2006.238.07:43:48.64#ibcon#read 4, iclass 29, count 0 2006.238.07:43:48.64#ibcon#about to read 5, iclass 29, count 0 2006.238.07:43:48.64#ibcon#read 5, iclass 29, count 0 2006.238.07:43:48.64#ibcon#about to read 6, iclass 29, count 0 2006.238.07:43:48.64#ibcon#read 6, iclass 29, count 0 2006.238.07:43:48.64#ibcon#end of sib2, iclass 29, count 0 2006.238.07:43:48.64#ibcon#*after write, iclass 29, count 0 2006.238.07:43:48.64#ibcon#*before return 0, iclass 29, count 0 2006.238.07:43:48.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:43:48.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:43:48.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:43:48.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:43:48.64$vc4f8/va=3,7 2006.238.07:43:48.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.238.07:43:48.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.238.07:43:48.64#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:48.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:43:48.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:43:48.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:43:48.70#ibcon#enter wrdev, iclass 31, count 2 2006.238.07:43:48.70#ibcon#first serial, iclass 31, count 2 2006.238.07:43:48.70#ibcon#enter sib2, iclass 31, count 2 2006.238.07:43:48.70#ibcon#flushed, iclass 31, count 2 2006.238.07:43:48.70#ibcon#about to write, iclass 31, count 2 2006.238.07:43:48.70#ibcon#wrote, iclass 31, count 2 2006.238.07:43:48.70#ibcon#about to read 3, iclass 31, count 2 2006.238.07:43:48.73#ibcon#read 3, iclass 31, count 2 2006.238.07:43:48.73#ibcon#about to read 4, iclass 31, count 2 2006.238.07:43:48.73#ibcon#read 4, iclass 31, count 2 2006.238.07:43:48.73#ibcon#about to read 5, iclass 31, count 2 2006.238.07:43:48.73#ibcon#read 5, iclass 31, count 2 2006.238.07:43:48.73#ibcon#about to read 6, iclass 31, count 2 2006.238.07:43:48.73#ibcon#read 6, iclass 31, count 2 2006.238.07:43:48.73#ibcon#end of sib2, iclass 31, count 2 2006.238.07:43:48.73#ibcon#*mode == 0, iclass 31, count 2 2006.238.07:43:48.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.238.07:43:48.73#ibcon#[25=AT03-07\r\n] 2006.238.07:43:48.73#ibcon#*before write, iclass 31, count 2 2006.238.07:43:48.73#ibcon#enter sib2, iclass 31, count 2 2006.238.07:43:48.73#ibcon#flushed, iclass 31, count 2 2006.238.07:43:48.73#ibcon#about to write, iclass 31, count 2 2006.238.07:43:48.73#ibcon#wrote, iclass 31, count 2 2006.238.07:43:48.73#ibcon#about to read 3, iclass 31, count 2 2006.238.07:43:48.76#ibcon#read 3, iclass 31, count 2 2006.238.07:43:48.76#ibcon#about to read 4, iclass 31, count 2 2006.238.07:43:48.76#ibcon#read 4, iclass 31, count 2 2006.238.07:43:48.76#ibcon#about to read 5, iclass 31, count 2 2006.238.07:43:48.76#ibcon#read 5, iclass 31, count 2 2006.238.07:43:48.76#ibcon#about to read 6, iclass 31, count 2 2006.238.07:43:48.76#ibcon#read 6, iclass 31, count 2 2006.238.07:43:48.76#ibcon#end of sib2, iclass 31, count 2 2006.238.07:43:48.76#ibcon#*after write, iclass 31, count 2 2006.238.07:43:48.76#ibcon#*before return 0, iclass 31, count 2 2006.238.07:43:48.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:43:48.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:43:48.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.238.07:43:48.76#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:48.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:43:48.88#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:43:48.88#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:43:48.88#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:43:48.88#ibcon#first serial, iclass 31, count 0 2006.238.07:43:48.88#ibcon#enter sib2, iclass 31, count 0 2006.238.07:43:48.88#ibcon#flushed, iclass 31, count 0 2006.238.07:43:48.88#ibcon#about to write, iclass 31, count 0 2006.238.07:43:48.88#ibcon#wrote, iclass 31, count 0 2006.238.07:43:48.88#ibcon#about to read 3, iclass 31, count 0 2006.238.07:43:48.90#ibcon#read 3, iclass 31, count 0 2006.238.07:43:48.90#ibcon#about to read 4, iclass 31, count 0 2006.238.07:43:48.90#ibcon#read 4, iclass 31, count 0 2006.238.07:43:48.90#ibcon#about to read 5, iclass 31, count 0 2006.238.07:43:48.90#ibcon#read 5, iclass 31, count 0 2006.238.07:43:48.90#ibcon#about to read 6, iclass 31, count 0 2006.238.07:43:48.90#ibcon#read 6, iclass 31, count 0 2006.238.07:43:48.90#ibcon#end of sib2, iclass 31, count 0 2006.238.07:43:48.90#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:43:48.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:43:48.90#ibcon#[25=USB\r\n] 2006.238.07:43:48.90#ibcon#*before write, iclass 31, count 0 2006.238.07:43:48.90#ibcon#enter sib2, iclass 31, count 0 2006.238.07:43:48.90#ibcon#flushed, iclass 31, count 0 2006.238.07:43:48.90#ibcon#about to write, iclass 31, count 0 2006.238.07:43:48.90#ibcon#wrote, iclass 31, count 0 2006.238.07:43:48.90#ibcon#about to read 3, iclass 31, count 0 2006.238.07:43:48.93#ibcon#read 3, iclass 31, count 0 2006.238.07:43:48.93#ibcon#about to read 4, iclass 31, count 0 2006.238.07:43:48.93#ibcon#read 4, iclass 31, count 0 2006.238.07:43:48.93#ibcon#about to read 5, iclass 31, count 0 2006.238.07:43:48.93#ibcon#read 5, iclass 31, count 0 2006.238.07:43:48.93#ibcon#about to read 6, iclass 31, count 0 2006.238.07:43:48.93#ibcon#read 6, iclass 31, count 0 2006.238.07:43:48.93#ibcon#end of sib2, iclass 31, count 0 2006.238.07:43:48.93#ibcon#*after write, iclass 31, count 0 2006.238.07:43:48.93#ibcon#*before return 0, iclass 31, count 0 2006.238.07:43:48.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:43:48.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:43:48.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:43:48.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:43:48.93$vc4f8/valo=4,832.99 2006.238.07:43:48.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.07:43:48.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.07:43:48.93#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:48.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:43:48.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:43:48.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:43:48.93#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:43:48.93#ibcon#first serial, iclass 33, count 0 2006.238.07:43:48.93#ibcon#enter sib2, iclass 33, count 0 2006.238.07:43:48.93#ibcon#flushed, iclass 33, count 0 2006.238.07:43:48.93#ibcon#about to write, iclass 33, count 0 2006.238.07:43:48.93#ibcon#wrote, iclass 33, count 0 2006.238.07:43:48.93#ibcon#about to read 3, iclass 33, count 0 2006.238.07:43:48.95#ibcon#read 3, iclass 33, count 0 2006.238.07:43:48.95#ibcon#about to read 4, iclass 33, count 0 2006.238.07:43:48.95#ibcon#read 4, iclass 33, count 0 2006.238.07:43:48.95#ibcon#about to read 5, iclass 33, count 0 2006.238.07:43:48.95#ibcon#read 5, iclass 33, count 0 2006.238.07:43:48.95#ibcon#about to read 6, iclass 33, count 0 2006.238.07:43:48.95#ibcon#read 6, iclass 33, count 0 2006.238.07:43:48.95#ibcon#end of sib2, iclass 33, count 0 2006.238.07:43:48.95#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:43:48.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:43:48.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:43:48.95#ibcon#*before write, iclass 33, count 0 2006.238.07:43:48.95#ibcon#enter sib2, iclass 33, count 0 2006.238.07:43:48.95#ibcon#flushed, iclass 33, count 0 2006.238.07:43:48.95#ibcon#about to write, iclass 33, count 0 2006.238.07:43:48.95#ibcon#wrote, iclass 33, count 0 2006.238.07:43:48.95#ibcon#about to read 3, iclass 33, count 0 2006.238.07:43:48.99#ibcon#read 3, iclass 33, count 0 2006.238.07:43:48.99#ibcon#about to read 4, iclass 33, count 0 2006.238.07:43:48.99#ibcon#read 4, iclass 33, count 0 2006.238.07:43:48.99#ibcon#about to read 5, iclass 33, count 0 2006.238.07:43:48.99#ibcon#read 5, iclass 33, count 0 2006.238.07:43:48.99#ibcon#about to read 6, iclass 33, count 0 2006.238.07:43:48.99#ibcon#read 6, iclass 33, count 0 2006.238.07:43:48.99#ibcon#end of sib2, iclass 33, count 0 2006.238.07:43:48.99#ibcon#*after write, iclass 33, count 0 2006.238.07:43:48.99#ibcon#*before return 0, iclass 33, count 0 2006.238.07:43:48.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:43:48.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:43:48.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:43:48.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:43:48.99$vc4f8/va=4,7 2006.238.07:43:48.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.238.07:43:48.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.238.07:43:48.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:48.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:43:49.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:43:49.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:43:49.05#ibcon#enter wrdev, iclass 35, count 2 2006.238.07:43:49.05#ibcon#first serial, iclass 35, count 2 2006.238.07:43:49.05#ibcon#enter sib2, iclass 35, count 2 2006.238.07:43:49.05#ibcon#flushed, iclass 35, count 2 2006.238.07:43:49.05#ibcon#about to write, iclass 35, count 2 2006.238.07:43:49.05#ibcon#wrote, iclass 35, count 2 2006.238.07:43:49.05#ibcon#about to read 3, iclass 35, count 2 2006.238.07:43:49.07#ibcon#read 3, iclass 35, count 2 2006.238.07:43:49.07#ibcon#about to read 4, iclass 35, count 2 2006.238.07:43:49.07#ibcon#read 4, iclass 35, count 2 2006.238.07:43:49.07#ibcon#about to read 5, iclass 35, count 2 2006.238.07:43:49.07#ibcon#read 5, iclass 35, count 2 2006.238.07:43:49.07#ibcon#about to read 6, iclass 35, count 2 2006.238.07:43:49.07#ibcon#read 6, iclass 35, count 2 2006.238.07:43:49.07#ibcon#end of sib2, iclass 35, count 2 2006.238.07:43:49.07#ibcon#*mode == 0, iclass 35, count 2 2006.238.07:43:49.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.238.07:43:49.07#ibcon#[25=AT04-07\r\n] 2006.238.07:43:49.07#ibcon#*before write, iclass 35, count 2 2006.238.07:43:49.07#ibcon#enter sib2, iclass 35, count 2 2006.238.07:43:49.07#ibcon#flushed, iclass 35, count 2 2006.238.07:43:49.07#ibcon#about to write, iclass 35, count 2 2006.238.07:43:49.07#ibcon#wrote, iclass 35, count 2 2006.238.07:43:49.07#ibcon#about to read 3, iclass 35, count 2 2006.238.07:43:49.10#ibcon#read 3, iclass 35, count 2 2006.238.07:43:49.10#ibcon#about to read 4, iclass 35, count 2 2006.238.07:43:49.10#ibcon#read 4, iclass 35, count 2 2006.238.07:43:49.10#ibcon#about to read 5, iclass 35, count 2 2006.238.07:43:49.10#ibcon#read 5, iclass 35, count 2 2006.238.07:43:49.10#ibcon#about to read 6, iclass 35, count 2 2006.238.07:43:49.10#ibcon#read 6, iclass 35, count 2 2006.238.07:43:49.10#ibcon#end of sib2, iclass 35, count 2 2006.238.07:43:49.10#ibcon#*after write, iclass 35, count 2 2006.238.07:43:49.10#ibcon#*before return 0, iclass 35, count 2 2006.238.07:43:49.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:43:49.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:43:49.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.238.07:43:49.10#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:49.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:43:49.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:43:49.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:43:49.22#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:43:49.22#ibcon#first serial, iclass 35, count 0 2006.238.07:43:49.22#ibcon#enter sib2, iclass 35, count 0 2006.238.07:43:49.22#ibcon#flushed, iclass 35, count 0 2006.238.07:43:49.22#ibcon#about to write, iclass 35, count 0 2006.238.07:43:49.22#ibcon#wrote, iclass 35, count 0 2006.238.07:43:49.22#ibcon#about to read 3, iclass 35, count 0 2006.238.07:43:49.24#ibcon#read 3, iclass 35, count 0 2006.238.07:43:49.24#ibcon#about to read 4, iclass 35, count 0 2006.238.07:43:49.24#ibcon#read 4, iclass 35, count 0 2006.238.07:43:49.24#ibcon#about to read 5, iclass 35, count 0 2006.238.07:43:49.24#ibcon#read 5, iclass 35, count 0 2006.238.07:43:49.24#ibcon#about to read 6, iclass 35, count 0 2006.238.07:43:49.24#ibcon#read 6, iclass 35, count 0 2006.238.07:43:49.24#ibcon#end of sib2, iclass 35, count 0 2006.238.07:43:49.24#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:43:49.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:43:49.24#ibcon#[25=USB\r\n] 2006.238.07:43:49.24#ibcon#*before write, iclass 35, count 0 2006.238.07:43:49.24#ibcon#enter sib2, iclass 35, count 0 2006.238.07:43:49.24#ibcon#flushed, iclass 35, count 0 2006.238.07:43:49.24#ibcon#about to write, iclass 35, count 0 2006.238.07:43:49.24#ibcon#wrote, iclass 35, count 0 2006.238.07:43:49.24#ibcon#about to read 3, iclass 35, count 0 2006.238.07:43:49.27#ibcon#read 3, iclass 35, count 0 2006.238.07:43:49.27#ibcon#about to read 4, iclass 35, count 0 2006.238.07:43:49.27#ibcon#read 4, iclass 35, count 0 2006.238.07:43:49.27#ibcon#about to read 5, iclass 35, count 0 2006.238.07:43:49.27#ibcon#read 5, iclass 35, count 0 2006.238.07:43:49.27#ibcon#about to read 6, iclass 35, count 0 2006.238.07:43:49.27#ibcon#read 6, iclass 35, count 0 2006.238.07:43:49.27#ibcon#end of sib2, iclass 35, count 0 2006.238.07:43:49.27#ibcon#*after write, iclass 35, count 0 2006.238.07:43:49.27#ibcon#*before return 0, iclass 35, count 0 2006.238.07:43:49.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:43:49.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:43:49.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:43:49.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:43:49.27$vc4f8/valo=5,652.99 2006.238.07:43:49.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.07:43:49.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.07:43:49.27#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:49.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:43:49.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:43:49.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:43:49.27#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:43:49.27#ibcon#first serial, iclass 37, count 0 2006.238.07:43:49.27#ibcon#enter sib2, iclass 37, count 0 2006.238.07:43:49.27#ibcon#flushed, iclass 37, count 0 2006.238.07:43:49.27#ibcon#about to write, iclass 37, count 0 2006.238.07:43:49.27#ibcon#wrote, iclass 37, count 0 2006.238.07:43:49.27#ibcon#about to read 3, iclass 37, count 0 2006.238.07:43:49.29#ibcon#read 3, iclass 37, count 0 2006.238.07:43:49.29#ibcon#about to read 4, iclass 37, count 0 2006.238.07:43:49.29#ibcon#read 4, iclass 37, count 0 2006.238.07:43:49.29#ibcon#about to read 5, iclass 37, count 0 2006.238.07:43:49.29#ibcon#read 5, iclass 37, count 0 2006.238.07:43:49.29#ibcon#about to read 6, iclass 37, count 0 2006.238.07:43:49.29#ibcon#read 6, iclass 37, count 0 2006.238.07:43:49.29#ibcon#end of sib2, iclass 37, count 0 2006.238.07:43:49.29#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:43:49.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:43:49.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:43:49.29#ibcon#*before write, iclass 37, count 0 2006.238.07:43:49.29#ibcon#enter sib2, iclass 37, count 0 2006.238.07:43:49.29#ibcon#flushed, iclass 37, count 0 2006.238.07:43:49.29#ibcon#about to write, iclass 37, count 0 2006.238.07:43:49.29#ibcon#wrote, iclass 37, count 0 2006.238.07:43:49.29#ibcon#about to read 3, iclass 37, count 0 2006.238.07:43:49.33#ibcon#read 3, iclass 37, count 0 2006.238.07:43:49.33#ibcon#about to read 4, iclass 37, count 0 2006.238.07:43:49.33#ibcon#read 4, iclass 37, count 0 2006.238.07:43:49.33#ibcon#about to read 5, iclass 37, count 0 2006.238.07:43:49.33#ibcon#read 5, iclass 37, count 0 2006.238.07:43:49.33#ibcon#about to read 6, iclass 37, count 0 2006.238.07:43:49.33#ibcon#read 6, iclass 37, count 0 2006.238.07:43:49.33#ibcon#end of sib2, iclass 37, count 0 2006.238.07:43:49.33#ibcon#*after write, iclass 37, count 0 2006.238.07:43:49.33#ibcon#*before return 0, iclass 37, count 0 2006.238.07:43:49.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:43:49.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:43:49.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:43:49.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:43:49.33$vc4f8/va=5,8 2006.238.07:43:49.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.238.07:43:49.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.238.07:43:49.33#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:49.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:43:49.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:43:49.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:43:49.39#ibcon#enter wrdev, iclass 39, count 2 2006.238.07:43:49.39#ibcon#first serial, iclass 39, count 2 2006.238.07:43:49.39#ibcon#enter sib2, iclass 39, count 2 2006.238.07:43:49.39#ibcon#flushed, iclass 39, count 2 2006.238.07:43:49.39#ibcon#about to write, iclass 39, count 2 2006.238.07:43:49.39#ibcon#wrote, iclass 39, count 2 2006.238.07:43:49.39#ibcon#about to read 3, iclass 39, count 2 2006.238.07:43:49.41#ibcon#read 3, iclass 39, count 2 2006.238.07:43:49.41#ibcon#about to read 4, iclass 39, count 2 2006.238.07:43:49.41#ibcon#read 4, iclass 39, count 2 2006.238.07:43:49.41#ibcon#about to read 5, iclass 39, count 2 2006.238.07:43:49.41#ibcon#read 5, iclass 39, count 2 2006.238.07:43:49.41#ibcon#about to read 6, iclass 39, count 2 2006.238.07:43:49.41#ibcon#read 6, iclass 39, count 2 2006.238.07:43:49.41#ibcon#end of sib2, iclass 39, count 2 2006.238.07:43:49.41#ibcon#*mode == 0, iclass 39, count 2 2006.238.07:43:49.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.238.07:43:49.41#ibcon#[25=AT05-08\r\n] 2006.238.07:43:49.41#ibcon#*before write, iclass 39, count 2 2006.238.07:43:49.41#ibcon#enter sib2, iclass 39, count 2 2006.238.07:43:49.41#ibcon#flushed, iclass 39, count 2 2006.238.07:43:49.41#ibcon#about to write, iclass 39, count 2 2006.238.07:43:49.41#ibcon#wrote, iclass 39, count 2 2006.238.07:43:49.41#ibcon#about to read 3, iclass 39, count 2 2006.238.07:43:49.44#ibcon#read 3, iclass 39, count 2 2006.238.07:43:49.44#ibcon#about to read 4, iclass 39, count 2 2006.238.07:43:49.44#ibcon#read 4, iclass 39, count 2 2006.238.07:43:49.44#ibcon#about to read 5, iclass 39, count 2 2006.238.07:43:49.44#ibcon#read 5, iclass 39, count 2 2006.238.07:43:49.44#ibcon#about to read 6, iclass 39, count 2 2006.238.07:43:49.44#ibcon#read 6, iclass 39, count 2 2006.238.07:43:49.44#ibcon#end of sib2, iclass 39, count 2 2006.238.07:43:49.44#ibcon#*after write, iclass 39, count 2 2006.238.07:43:49.44#ibcon#*before return 0, iclass 39, count 2 2006.238.07:43:49.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:43:49.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:43:49.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.238.07:43:49.44#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:49.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:43:49.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:43:49.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:43:49.56#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:43:49.56#ibcon#first serial, iclass 39, count 0 2006.238.07:43:49.56#ibcon#enter sib2, iclass 39, count 0 2006.238.07:43:49.56#ibcon#flushed, iclass 39, count 0 2006.238.07:43:49.56#ibcon#about to write, iclass 39, count 0 2006.238.07:43:49.56#ibcon#wrote, iclass 39, count 0 2006.238.07:43:49.56#ibcon#about to read 3, iclass 39, count 0 2006.238.07:43:49.58#ibcon#read 3, iclass 39, count 0 2006.238.07:43:49.58#ibcon#about to read 4, iclass 39, count 0 2006.238.07:43:49.58#ibcon#read 4, iclass 39, count 0 2006.238.07:43:49.58#ibcon#about to read 5, iclass 39, count 0 2006.238.07:43:49.58#ibcon#read 5, iclass 39, count 0 2006.238.07:43:49.58#ibcon#about to read 6, iclass 39, count 0 2006.238.07:43:49.58#ibcon#read 6, iclass 39, count 0 2006.238.07:43:49.58#ibcon#end of sib2, iclass 39, count 0 2006.238.07:43:49.58#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:43:49.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:43:49.58#ibcon#[25=USB\r\n] 2006.238.07:43:49.58#ibcon#*before write, iclass 39, count 0 2006.238.07:43:49.58#ibcon#enter sib2, iclass 39, count 0 2006.238.07:43:49.58#ibcon#flushed, iclass 39, count 0 2006.238.07:43:49.58#ibcon#about to write, iclass 39, count 0 2006.238.07:43:49.58#ibcon#wrote, iclass 39, count 0 2006.238.07:43:49.58#ibcon#about to read 3, iclass 39, count 0 2006.238.07:43:49.61#ibcon#read 3, iclass 39, count 0 2006.238.07:43:49.61#ibcon#about to read 4, iclass 39, count 0 2006.238.07:43:49.61#ibcon#read 4, iclass 39, count 0 2006.238.07:43:49.61#ibcon#about to read 5, iclass 39, count 0 2006.238.07:43:49.61#ibcon#read 5, iclass 39, count 0 2006.238.07:43:49.61#ibcon#about to read 6, iclass 39, count 0 2006.238.07:43:49.61#ibcon#read 6, iclass 39, count 0 2006.238.07:43:49.61#ibcon#end of sib2, iclass 39, count 0 2006.238.07:43:49.61#ibcon#*after write, iclass 39, count 0 2006.238.07:43:49.61#ibcon#*before return 0, iclass 39, count 0 2006.238.07:43:49.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:43:49.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:43:49.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:43:49.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:43:49.61$vc4f8/valo=6,772.99 2006.238.07:43:49.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.07:43:49.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.07:43:49.61#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:49.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:43:49.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:43:49.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:43:49.61#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:43:49.61#ibcon#first serial, iclass 3, count 0 2006.238.07:43:49.61#ibcon#enter sib2, iclass 3, count 0 2006.238.07:43:49.61#ibcon#flushed, iclass 3, count 0 2006.238.07:43:49.61#ibcon#about to write, iclass 3, count 0 2006.238.07:43:49.61#ibcon#wrote, iclass 3, count 0 2006.238.07:43:49.61#ibcon#about to read 3, iclass 3, count 0 2006.238.07:43:49.63#ibcon#read 3, iclass 3, count 0 2006.238.07:43:49.63#ibcon#about to read 4, iclass 3, count 0 2006.238.07:43:49.63#ibcon#read 4, iclass 3, count 0 2006.238.07:43:49.63#ibcon#about to read 5, iclass 3, count 0 2006.238.07:43:49.63#ibcon#read 5, iclass 3, count 0 2006.238.07:43:49.63#ibcon#about to read 6, iclass 3, count 0 2006.238.07:43:49.63#ibcon#read 6, iclass 3, count 0 2006.238.07:43:49.63#ibcon#end of sib2, iclass 3, count 0 2006.238.07:43:49.63#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:43:49.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:43:49.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:43:49.63#ibcon#*before write, iclass 3, count 0 2006.238.07:43:49.63#ibcon#enter sib2, iclass 3, count 0 2006.238.07:43:49.63#ibcon#flushed, iclass 3, count 0 2006.238.07:43:49.63#ibcon#about to write, iclass 3, count 0 2006.238.07:43:49.63#ibcon#wrote, iclass 3, count 0 2006.238.07:43:49.63#ibcon#about to read 3, iclass 3, count 0 2006.238.07:43:49.67#ibcon#read 3, iclass 3, count 0 2006.238.07:43:49.67#ibcon#about to read 4, iclass 3, count 0 2006.238.07:43:49.67#ibcon#read 4, iclass 3, count 0 2006.238.07:43:49.67#ibcon#about to read 5, iclass 3, count 0 2006.238.07:43:49.67#ibcon#read 5, iclass 3, count 0 2006.238.07:43:49.67#ibcon#about to read 6, iclass 3, count 0 2006.238.07:43:49.67#ibcon#read 6, iclass 3, count 0 2006.238.07:43:49.67#ibcon#end of sib2, iclass 3, count 0 2006.238.07:43:49.67#ibcon#*after write, iclass 3, count 0 2006.238.07:43:49.67#ibcon#*before return 0, iclass 3, count 0 2006.238.07:43:49.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:43:49.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:43:49.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:43:49.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:43:49.67$vc4f8/va=6,7 2006.238.07:43:49.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.238.07:43:49.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.238.07:43:49.67#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:49.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:43:49.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:43:49.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:43:49.73#ibcon#enter wrdev, iclass 5, count 2 2006.238.07:43:49.73#ibcon#first serial, iclass 5, count 2 2006.238.07:43:49.73#ibcon#enter sib2, iclass 5, count 2 2006.238.07:43:49.73#ibcon#flushed, iclass 5, count 2 2006.238.07:43:49.73#ibcon#about to write, iclass 5, count 2 2006.238.07:43:49.73#ibcon#wrote, iclass 5, count 2 2006.238.07:43:49.73#ibcon#about to read 3, iclass 5, count 2 2006.238.07:43:49.75#ibcon#read 3, iclass 5, count 2 2006.238.07:43:49.75#ibcon#about to read 4, iclass 5, count 2 2006.238.07:43:49.75#ibcon#read 4, iclass 5, count 2 2006.238.07:43:49.75#ibcon#about to read 5, iclass 5, count 2 2006.238.07:43:49.75#ibcon#read 5, iclass 5, count 2 2006.238.07:43:49.75#ibcon#about to read 6, iclass 5, count 2 2006.238.07:43:49.75#ibcon#read 6, iclass 5, count 2 2006.238.07:43:49.75#ibcon#end of sib2, iclass 5, count 2 2006.238.07:43:49.75#ibcon#*mode == 0, iclass 5, count 2 2006.238.07:43:49.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.238.07:43:49.75#ibcon#[25=AT06-07\r\n] 2006.238.07:43:49.75#ibcon#*before write, iclass 5, count 2 2006.238.07:43:49.75#ibcon#enter sib2, iclass 5, count 2 2006.238.07:43:49.75#ibcon#flushed, iclass 5, count 2 2006.238.07:43:49.75#ibcon#about to write, iclass 5, count 2 2006.238.07:43:49.75#ibcon#wrote, iclass 5, count 2 2006.238.07:43:49.75#ibcon#about to read 3, iclass 5, count 2 2006.238.07:43:49.78#ibcon#read 3, iclass 5, count 2 2006.238.07:43:49.78#ibcon#about to read 4, iclass 5, count 2 2006.238.07:43:49.78#ibcon#read 4, iclass 5, count 2 2006.238.07:43:49.78#ibcon#about to read 5, iclass 5, count 2 2006.238.07:43:49.78#ibcon#read 5, iclass 5, count 2 2006.238.07:43:49.78#ibcon#about to read 6, iclass 5, count 2 2006.238.07:43:49.78#ibcon#read 6, iclass 5, count 2 2006.238.07:43:49.78#ibcon#end of sib2, iclass 5, count 2 2006.238.07:43:49.78#ibcon#*after write, iclass 5, count 2 2006.238.07:43:49.78#ibcon#*before return 0, iclass 5, count 2 2006.238.07:43:49.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:43:49.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:43:49.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.238.07:43:49.78#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:49.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:43:49.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:43:49.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:43:49.90#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:43:49.90#ibcon#first serial, iclass 5, count 0 2006.238.07:43:49.90#ibcon#enter sib2, iclass 5, count 0 2006.238.07:43:49.90#ibcon#flushed, iclass 5, count 0 2006.238.07:43:49.90#ibcon#about to write, iclass 5, count 0 2006.238.07:43:49.90#ibcon#wrote, iclass 5, count 0 2006.238.07:43:49.90#ibcon#about to read 3, iclass 5, count 0 2006.238.07:43:49.92#ibcon#read 3, iclass 5, count 0 2006.238.07:43:49.92#ibcon#about to read 4, iclass 5, count 0 2006.238.07:43:49.92#ibcon#read 4, iclass 5, count 0 2006.238.07:43:49.92#ibcon#about to read 5, iclass 5, count 0 2006.238.07:43:49.92#ibcon#read 5, iclass 5, count 0 2006.238.07:43:49.92#ibcon#about to read 6, iclass 5, count 0 2006.238.07:43:49.92#ibcon#read 6, iclass 5, count 0 2006.238.07:43:49.92#ibcon#end of sib2, iclass 5, count 0 2006.238.07:43:49.92#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:43:49.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:43:49.92#ibcon#[25=USB\r\n] 2006.238.07:43:49.92#ibcon#*before write, iclass 5, count 0 2006.238.07:43:49.92#ibcon#enter sib2, iclass 5, count 0 2006.238.07:43:49.92#ibcon#flushed, iclass 5, count 0 2006.238.07:43:49.92#ibcon#about to write, iclass 5, count 0 2006.238.07:43:49.92#ibcon#wrote, iclass 5, count 0 2006.238.07:43:49.92#ibcon#about to read 3, iclass 5, count 0 2006.238.07:43:49.95#ibcon#read 3, iclass 5, count 0 2006.238.07:43:49.95#ibcon#about to read 4, iclass 5, count 0 2006.238.07:43:49.95#ibcon#read 4, iclass 5, count 0 2006.238.07:43:49.95#ibcon#about to read 5, iclass 5, count 0 2006.238.07:43:49.95#ibcon#read 5, iclass 5, count 0 2006.238.07:43:49.95#ibcon#about to read 6, iclass 5, count 0 2006.238.07:43:49.95#ibcon#read 6, iclass 5, count 0 2006.238.07:43:49.95#ibcon#end of sib2, iclass 5, count 0 2006.238.07:43:49.95#ibcon#*after write, iclass 5, count 0 2006.238.07:43:49.95#ibcon#*before return 0, iclass 5, count 0 2006.238.07:43:49.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:43:49.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:43:49.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:43:49.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:43:49.95$vc4f8/valo=7,832.99 2006.238.07:43:49.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.238.07:43:49.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.238.07:43:49.95#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:49.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:43:49.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:43:49.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:43:49.95#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:43:49.95#ibcon#first serial, iclass 7, count 0 2006.238.07:43:49.95#ibcon#enter sib2, iclass 7, count 0 2006.238.07:43:49.95#ibcon#flushed, iclass 7, count 0 2006.238.07:43:49.95#ibcon#about to write, iclass 7, count 0 2006.238.07:43:49.95#ibcon#wrote, iclass 7, count 0 2006.238.07:43:49.95#ibcon#about to read 3, iclass 7, count 0 2006.238.07:43:49.97#ibcon#read 3, iclass 7, count 0 2006.238.07:43:49.97#ibcon#about to read 4, iclass 7, count 0 2006.238.07:43:49.97#ibcon#read 4, iclass 7, count 0 2006.238.07:43:49.97#ibcon#about to read 5, iclass 7, count 0 2006.238.07:43:49.97#ibcon#read 5, iclass 7, count 0 2006.238.07:43:49.97#ibcon#about to read 6, iclass 7, count 0 2006.238.07:43:49.97#ibcon#read 6, iclass 7, count 0 2006.238.07:43:49.97#ibcon#end of sib2, iclass 7, count 0 2006.238.07:43:49.97#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:43:49.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:43:49.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:43:49.97#ibcon#*before write, iclass 7, count 0 2006.238.07:43:49.97#ibcon#enter sib2, iclass 7, count 0 2006.238.07:43:49.97#ibcon#flushed, iclass 7, count 0 2006.238.07:43:49.97#ibcon#about to write, iclass 7, count 0 2006.238.07:43:49.97#ibcon#wrote, iclass 7, count 0 2006.238.07:43:49.97#ibcon#about to read 3, iclass 7, count 0 2006.238.07:43:50.01#ibcon#read 3, iclass 7, count 0 2006.238.07:43:50.01#ibcon#about to read 4, iclass 7, count 0 2006.238.07:43:50.01#ibcon#read 4, iclass 7, count 0 2006.238.07:43:50.01#ibcon#about to read 5, iclass 7, count 0 2006.238.07:43:50.01#ibcon#read 5, iclass 7, count 0 2006.238.07:43:50.01#ibcon#about to read 6, iclass 7, count 0 2006.238.07:43:50.01#ibcon#read 6, iclass 7, count 0 2006.238.07:43:50.01#ibcon#end of sib2, iclass 7, count 0 2006.238.07:43:50.01#ibcon#*after write, iclass 7, count 0 2006.238.07:43:50.01#ibcon#*before return 0, iclass 7, count 0 2006.238.07:43:50.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:43:50.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:43:50.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:43:50.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:43:50.01$vc4f8/va=7,7 2006.238.07:43:50.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.238.07:43:50.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.238.07:43:50.01#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:50.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:43:50.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:43:50.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:43:50.07#ibcon#enter wrdev, iclass 11, count 2 2006.238.07:43:50.07#ibcon#first serial, iclass 11, count 2 2006.238.07:43:50.07#ibcon#enter sib2, iclass 11, count 2 2006.238.07:43:50.07#ibcon#flushed, iclass 11, count 2 2006.238.07:43:50.07#ibcon#about to write, iclass 11, count 2 2006.238.07:43:50.07#ibcon#wrote, iclass 11, count 2 2006.238.07:43:50.07#ibcon#about to read 3, iclass 11, count 2 2006.238.07:43:50.09#ibcon#read 3, iclass 11, count 2 2006.238.07:43:50.09#ibcon#about to read 4, iclass 11, count 2 2006.238.07:43:50.09#ibcon#read 4, iclass 11, count 2 2006.238.07:43:50.09#ibcon#about to read 5, iclass 11, count 2 2006.238.07:43:50.09#ibcon#read 5, iclass 11, count 2 2006.238.07:43:50.09#ibcon#about to read 6, iclass 11, count 2 2006.238.07:43:50.09#ibcon#read 6, iclass 11, count 2 2006.238.07:43:50.09#ibcon#end of sib2, iclass 11, count 2 2006.238.07:43:50.09#ibcon#*mode == 0, iclass 11, count 2 2006.238.07:43:50.09#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.238.07:43:50.09#ibcon#[25=AT07-07\r\n] 2006.238.07:43:50.09#ibcon#*before write, iclass 11, count 2 2006.238.07:43:50.09#ibcon#enter sib2, iclass 11, count 2 2006.238.07:43:50.09#ibcon#flushed, iclass 11, count 2 2006.238.07:43:50.09#ibcon#about to write, iclass 11, count 2 2006.238.07:43:50.09#ibcon#wrote, iclass 11, count 2 2006.238.07:43:50.09#ibcon#about to read 3, iclass 11, count 2 2006.238.07:43:50.12#ibcon#read 3, iclass 11, count 2 2006.238.07:43:50.12#ibcon#about to read 4, iclass 11, count 2 2006.238.07:43:50.12#ibcon#read 4, iclass 11, count 2 2006.238.07:43:50.12#ibcon#about to read 5, iclass 11, count 2 2006.238.07:43:50.12#ibcon#read 5, iclass 11, count 2 2006.238.07:43:50.12#ibcon#about to read 6, iclass 11, count 2 2006.238.07:43:50.12#ibcon#read 6, iclass 11, count 2 2006.238.07:43:50.12#ibcon#end of sib2, iclass 11, count 2 2006.238.07:43:50.12#ibcon#*after write, iclass 11, count 2 2006.238.07:43:50.12#ibcon#*before return 0, iclass 11, count 2 2006.238.07:43:50.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:43:50.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:43:50.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.238.07:43:50.12#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:50.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:43:50.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:43:50.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:43:50.24#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:43:50.24#ibcon#first serial, iclass 11, count 0 2006.238.07:43:50.24#ibcon#enter sib2, iclass 11, count 0 2006.238.07:43:50.24#ibcon#flushed, iclass 11, count 0 2006.238.07:43:50.24#ibcon#about to write, iclass 11, count 0 2006.238.07:43:50.24#ibcon#wrote, iclass 11, count 0 2006.238.07:43:50.24#ibcon#about to read 3, iclass 11, count 0 2006.238.07:43:50.26#ibcon#read 3, iclass 11, count 0 2006.238.07:43:50.26#ibcon#about to read 4, iclass 11, count 0 2006.238.07:43:50.26#ibcon#read 4, iclass 11, count 0 2006.238.07:43:50.26#ibcon#about to read 5, iclass 11, count 0 2006.238.07:43:50.26#ibcon#read 5, iclass 11, count 0 2006.238.07:43:50.26#ibcon#about to read 6, iclass 11, count 0 2006.238.07:43:50.26#ibcon#read 6, iclass 11, count 0 2006.238.07:43:50.26#ibcon#end of sib2, iclass 11, count 0 2006.238.07:43:50.26#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:43:50.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:43:50.26#ibcon#[25=USB\r\n] 2006.238.07:43:50.26#ibcon#*before write, iclass 11, count 0 2006.238.07:43:50.26#ibcon#enter sib2, iclass 11, count 0 2006.238.07:43:50.26#ibcon#flushed, iclass 11, count 0 2006.238.07:43:50.26#ibcon#about to write, iclass 11, count 0 2006.238.07:43:50.26#ibcon#wrote, iclass 11, count 0 2006.238.07:43:50.26#ibcon#about to read 3, iclass 11, count 0 2006.238.07:43:50.29#ibcon#read 3, iclass 11, count 0 2006.238.07:43:50.29#ibcon#about to read 4, iclass 11, count 0 2006.238.07:43:50.29#ibcon#read 4, iclass 11, count 0 2006.238.07:43:50.29#ibcon#about to read 5, iclass 11, count 0 2006.238.07:43:50.29#ibcon#read 5, iclass 11, count 0 2006.238.07:43:50.29#ibcon#about to read 6, iclass 11, count 0 2006.238.07:43:50.29#ibcon#read 6, iclass 11, count 0 2006.238.07:43:50.29#ibcon#end of sib2, iclass 11, count 0 2006.238.07:43:50.29#ibcon#*after write, iclass 11, count 0 2006.238.07:43:50.29#ibcon#*before return 0, iclass 11, count 0 2006.238.07:43:50.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:43:50.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:43:50.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:43:50.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:43:50.29$vc4f8/valo=8,852.99 2006.238.07:43:50.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.07:43:50.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.07:43:50.29#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:50.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:43:50.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:43:50.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:43:50.29#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:43:50.29#ibcon#first serial, iclass 13, count 0 2006.238.07:43:50.29#ibcon#enter sib2, iclass 13, count 0 2006.238.07:43:50.29#ibcon#flushed, iclass 13, count 0 2006.238.07:43:50.29#ibcon#about to write, iclass 13, count 0 2006.238.07:43:50.29#ibcon#wrote, iclass 13, count 0 2006.238.07:43:50.29#ibcon#about to read 3, iclass 13, count 0 2006.238.07:43:50.31#ibcon#read 3, iclass 13, count 0 2006.238.07:43:50.31#ibcon#about to read 4, iclass 13, count 0 2006.238.07:43:50.31#ibcon#read 4, iclass 13, count 0 2006.238.07:43:50.31#ibcon#about to read 5, iclass 13, count 0 2006.238.07:43:50.31#ibcon#read 5, iclass 13, count 0 2006.238.07:43:50.31#ibcon#about to read 6, iclass 13, count 0 2006.238.07:43:50.31#ibcon#read 6, iclass 13, count 0 2006.238.07:43:50.31#ibcon#end of sib2, iclass 13, count 0 2006.238.07:43:50.31#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:43:50.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:43:50.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:43:50.31#ibcon#*before write, iclass 13, count 0 2006.238.07:43:50.31#ibcon#enter sib2, iclass 13, count 0 2006.238.07:43:50.31#ibcon#flushed, iclass 13, count 0 2006.238.07:43:50.31#ibcon#about to write, iclass 13, count 0 2006.238.07:43:50.31#ibcon#wrote, iclass 13, count 0 2006.238.07:43:50.31#ibcon#about to read 3, iclass 13, count 0 2006.238.07:43:50.35#ibcon#read 3, iclass 13, count 0 2006.238.07:43:50.35#ibcon#about to read 4, iclass 13, count 0 2006.238.07:43:50.35#ibcon#read 4, iclass 13, count 0 2006.238.07:43:50.35#ibcon#about to read 5, iclass 13, count 0 2006.238.07:43:50.35#ibcon#read 5, iclass 13, count 0 2006.238.07:43:50.35#ibcon#about to read 6, iclass 13, count 0 2006.238.07:43:50.35#ibcon#read 6, iclass 13, count 0 2006.238.07:43:50.35#ibcon#end of sib2, iclass 13, count 0 2006.238.07:43:50.35#ibcon#*after write, iclass 13, count 0 2006.238.07:43:50.35#ibcon#*before return 0, iclass 13, count 0 2006.238.07:43:50.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:43:50.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:43:50.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:43:50.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:43:50.35$vc4f8/va=8,7 2006.238.07:43:50.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.238.07:43:50.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.238.07:43:50.35#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:50.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:43:50.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:43:50.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:43:50.41#ibcon#enter wrdev, iclass 15, count 2 2006.238.07:43:50.41#ibcon#first serial, iclass 15, count 2 2006.238.07:43:50.41#ibcon#enter sib2, iclass 15, count 2 2006.238.07:43:50.41#ibcon#flushed, iclass 15, count 2 2006.238.07:43:50.41#ibcon#about to write, iclass 15, count 2 2006.238.07:43:50.41#ibcon#wrote, iclass 15, count 2 2006.238.07:43:50.41#ibcon#about to read 3, iclass 15, count 2 2006.238.07:43:50.43#ibcon#read 3, iclass 15, count 2 2006.238.07:43:50.43#ibcon#about to read 4, iclass 15, count 2 2006.238.07:43:50.43#ibcon#read 4, iclass 15, count 2 2006.238.07:43:50.43#ibcon#about to read 5, iclass 15, count 2 2006.238.07:43:50.43#ibcon#read 5, iclass 15, count 2 2006.238.07:43:50.43#ibcon#about to read 6, iclass 15, count 2 2006.238.07:43:50.43#ibcon#read 6, iclass 15, count 2 2006.238.07:43:50.43#ibcon#end of sib2, iclass 15, count 2 2006.238.07:43:50.43#ibcon#*mode == 0, iclass 15, count 2 2006.238.07:43:50.43#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.238.07:43:50.43#ibcon#[25=AT08-07\r\n] 2006.238.07:43:50.43#ibcon#*before write, iclass 15, count 2 2006.238.07:43:50.43#ibcon#enter sib2, iclass 15, count 2 2006.238.07:43:50.43#ibcon#flushed, iclass 15, count 2 2006.238.07:43:50.43#ibcon#about to write, iclass 15, count 2 2006.238.07:43:50.43#ibcon#wrote, iclass 15, count 2 2006.238.07:43:50.43#ibcon#about to read 3, iclass 15, count 2 2006.238.07:43:50.46#ibcon#read 3, iclass 15, count 2 2006.238.07:43:50.46#ibcon#about to read 4, iclass 15, count 2 2006.238.07:43:50.46#ibcon#read 4, iclass 15, count 2 2006.238.07:43:50.46#ibcon#about to read 5, iclass 15, count 2 2006.238.07:43:50.46#ibcon#read 5, iclass 15, count 2 2006.238.07:43:50.46#ibcon#about to read 6, iclass 15, count 2 2006.238.07:43:50.46#ibcon#read 6, iclass 15, count 2 2006.238.07:43:50.46#ibcon#end of sib2, iclass 15, count 2 2006.238.07:43:50.46#ibcon#*after write, iclass 15, count 2 2006.238.07:43:50.46#ibcon#*before return 0, iclass 15, count 2 2006.238.07:43:50.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:43:50.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:43:50.46#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.238.07:43:50.46#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:50.46#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:43:50.58#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:43:50.58#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:43:50.58#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:43:50.58#ibcon#first serial, iclass 15, count 0 2006.238.07:43:50.58#ibcon#enter sib2, iclass 15, count 0 2006.238.07:43:50.58#ibcon#flushed, iclass 15, count 0 2006.238.07:43:50.58#ibcon#about to write, iclass 15, count 0 2006.238.07:43:50.58#ibcon#wrote, iclass 15, count 0 2006.238.07:43:50.58#ibcon#about to read 3, iclass 15, count 0 2006.238.07:43:50.60#ibcon#read 3, iclass 15, count 0 2006.238.07:43:50.60#ibcon#about to read 4, iclass 15, count 0 2006.238.07:43:50.60#ibcon#read 4, iclass 15, count 0 2006.238.07:43:50.60#ibcon#about to read 5, iclass 15, count 0 2006.238.07:43:50.60#ibcon#read 5, iclass 15, count 0 2006.238.07:43:50.60#ibcon#about to read 6, iclass 15, count 0 2006.238.07:43:50.60#ibcon#read 6, iclass 15, count 0 2006.238.07:43:50.60#ibcon#end of sib2, iclass 15, count 0 2006.238.07:43:50.60#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:43:50.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:43:50.60#ibcon#[25=USB\r\n] 2006.238.07:43:50.60#ibcon#*before write, iclass 15, count 0 2006.238.07:43:50.60#ibcon#enter sib2, iclass 15, count 0 2006.238.07:43:50.60#ibcon#flushed, iclass 15, count 0 2006.238.07:43:50.60#ibcon#about to write, iclass 15, count 0 2006.238.07:43:50.60#ibcon#wrote, iclass 15, count 0 2006.238.07:43:50.60#ibcon#about to read 3, iclass 15, count 0 2006.238.07:43:50.63#ibcon#read 3, iclass 15, count 0 2006.238.07:43:50.63#ibcon#about to read 4, iclass 15, count 0 2006.238.07:43:50.63#ibcon#read 4, iclass 15, count 0 2006.238.07:43:50.63#ibcon#about to read 5, iclass 15, count 0 2006.238.07:43:50.63#ibcon#read 5, iclass 15, count 0 2006.238.07:43:50.63#ibcon#about to read 6, iclass 15, count 0 2006.238.07:43:50.63#ibcon#read 6, iclass 15, count 0 2006.238.07:43:50.63#ibcon#end of sib2, iclass 15, count 0 2006.238.07:43:50.63#ibcon#*after write, iclass 15, count 0 2006.238.07:43:50.63#ibcon#*before return 0, iclass 15, count 0 2006.238.07:43:50.63#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:43:50.63#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:43:50.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:43:50.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:43:50.63$vc4f8/vblo=1,632.99 2006.238.07:43:50.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.07:43:50.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.07:43:50.63#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:50.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:43:50.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:43:50.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:43:50.63#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:43:50.63#ibcon#first serial, iclass 17, count 0 2006.238.07:43:50.63#ibcon#enter sib2, iclass 17, count 0 2006.238.07:43:50.63#ibcon#flushed, iclass 17, count 0 2006.238.07:43:50.63#ibcon#about to write, iclass 17, count 0 2006.238.07:43:50.63#ibcon#wrote, iclass 17, count 0 2006.238.07:43:50.63#ibcon#about to read 3, iclass 17, count 0 2006.238.07:43:50.65#ibcon#read 3, iclass 17, count 0 2006.238.07:43:50.65#ibcon#about to read 4, iclass 17, count 0 2006.238.07:43:50.65#ibcon#read 4, iclass 17, count 0 2006.238.07:43:50.65#ibcon#about to read 5, iclass 17, count 0 2006.238.07:43:50.65#ibcon#read 5, iclass 17, count 0 2006.238.07:43:50.65#ibcon#about to read 6, iclass 17, count 0 2006.238.07:43:50.65#ibcon#read 6, iclass 17, count 0 2006.238.07:43:50.65#ibcon#end of sib2, iclass 17, count 0 2006.238.07:43:50.65#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:43:50.65#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:43:50.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:43:50.65#ibcon#*before write, iclass 17, count 0 2006.238.07:43:50.65#ibcon#enter sib2, iclass 17, count 0 2006.238.07:43:50.65#ibcon#flushed, iclass 17, count 0 2006.238.07:43:50.65#ibcon#about to write, iclass 17, count 0 2006.238.07:43:50.65#ibcon#wrote, iclass 17, count 0 2006.238.07:43:50.65#ibcon#about to read 3, iclass 17, count 0 2006.238.07:43:50.69#ibcon#read 3, iclass 17, count 0 2006.238.07:43:50.69#ibcon#about to read 4, iclass 17, count 0 2006.238.07:43:50.69#ibcon#read 4, iclass 17, count 0 2006.238.07:43:50.69#ibcon#about to read 5, iclass 17, count 0 2006.238.07:43:50.69#ibcon#read 5, iclass 17, count 0 2006.238.07:43:50.69#ibcon#about to read 6, iclass 17, count 0 2006.238.07:43:50.69#ibcon#read 6, iclass 17, count 0 2006.238.07:43:50.69#ibcon#end of sib2, iclass 17, count 0 2006.238.07:43:50.69#ibcon#*after write, iclass 17, count 0 2006.238.07:43:50.69#ibcon#*before return 0, iclass 17, count 0 2006.238.07:43:50.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:43:50.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:43:50.69#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:43:50.69#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:43:50.69$vc4f8/vb=1,4 2006.238.07:43:50.69#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.238.07:43:50.69#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.238.07:43:50.69#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:50.69#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:43:50.69#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:43:50.69#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:43:50.69#ibcon#enter wrdev, iclass 19, count 2 2006.238.07:43:50.69#ibcon#first serial, iclass 19, count 2 2006.238.07:43:50.69#ibcon#enter sib2, iclass 19, count 2 2006.238.07:43:50.69#ibcon#flushed, iclass 19, count 2 2006.238.07:43:50.69#ibcon#about to write, iclass 19, count 2 2006.238.07:43:50.69#ibcon#wrote, iclass 19, count 2 2006.238.07:43:50.69#ibcon#about to read 3, iclass 19, count 2 2006.238.07:43:50.71#ibcon#read 3, iclass 19, count 2 2006.238.07:43:50.71#ibcon#about to read 4, iclass 19, count 2 2006.238.07:43:50.71#ibcon#read 4, iclass 19, count 2 2006.238.07:43:50.71#ibcon#about to read 5, iclass 19, count 2 2006.238.07:43:50.71#ibcon#read 5, iclass 19, count 2 2006.238.07:43:50.71#ibcon#about to read 6, iclass 19, count 2 2006.238.07:43:50.71#ibcon#read 6, iclass 19, count 2 2006.238.07:43:50.71#ibcon#end of sib2, iclass 19, count 2 2006.238.07:43:50.71#ibcon#*mode == 0, iclass 19, count 2 2006.238.07:43:50.71#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.238.07:43:50.71#ibcon#[27=AT01-04\r\n] 2006.238.07:43:50.71#ibcon#*before write, iclass 19, count 2 2006.238.07:43:50.71#ibcon#enter sib2, iclass 19, count 2 2006.238.07:43:50.71#ibcon#flushed, iclass 19, count 2 2006.238.07:43:50.71#ibcon#about to write, iclass 19, count 2 2006.238.07:43:50.71#ibcon#wrote, iclass 19, count 2 2006.238.07:43:50.71#ibcon#about to read 3, iclass 19, count 2 2006.238.07:43:50.74#ibcon#read 3, iclass 19, count 2 2006.238.07:43:50.74#ibcon#about to read 4, iclass 19, count 2 2006.238.07:43:50.74#ibcon#read 4, iclass 19, count 2 2006.238.07:43:50.74#ibcon#about to read 5, iclass 19, count 2 2006.238.07:43:50.74#ibcon#read 5, iclass 19, count 2 2006.238.07:43:50.74#ibcon#about to read 6, iclass 19, count 2 2006.238.07:43:50.74#ibcon#read 6, iclass 19, count 2 2006.238.07:43:50.74#ibcon#end of sib2, iclass 19, count 2 2006.238.07:43:50.74#ibcon#*after write, iclass 19, count 2 2006.238.07:43:50.74#ibcon#*before return 0, iclass 19, count 2 2006.238.07:43:50.74#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:43:50.74#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:43:50.74#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.238.07:43:50.74#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:50.74#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:43:50.86#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:43:50.86#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:43:50.86#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:43:50.86#ibcon#first serial, iclass 19, count 0 2006.238.07:43:50.86#ibcon#enter sib2, iclass 19, count 0 2006.238.07:43:50.86#ibcon#flushed, iclass 19, count 0 2006.238.07:43:50.86#ibcon#about to write, iclass 19, count 0 2006.238.07:43:50.86#ibcon#wrote, iclass 19, count 0 2006.238.07:43:50.86#ibcon#about to read 3, iclass 19, count 0 2006.238.07:43:50.88#ibcon#read 3, iclass 19, count 0 2006.238.07:43:50.88#ibcon#about to read 4, iclass 19, count 0 2006.238.07:43:50.88#ibcon#read 4, iclass 19, count 0 2006.238.07:43:50.88#ibcon#about to read 5, iclass 19, count 0 2006.238.07:43:50.88#ibcon#read 5, iclass 19, count 0 2006.238.07:43:50.88#ibcon#about to read 6, iclass 19, count 0 2006.238.07:43:50.88#ibcon#read 6, iclass 19, count 0 2006.238.07:43:50.88#ibcon#end of sib2, iclass 19, count 0 2006.238.07:43:50.88#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:43:50.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:43:50.88#ibcon#[27=USB\r\n] 2006.238.07:43:50.88#ibcon#*before write, iclass 19, count 0 2006.238.07:43:50.88#ibcon#enter sib2, iclass 19, count 0 2006.238.07:43:50.88#ibcon#flushed, iclass 19, count 0 2006.238.07:43:50.88#ibcon#about to write, iclass 19, count 0 2006.238.07:43:50.88#ibcon#wrote, iclass 19, count 0 2006.238.07:43:50.88#ibcon#about to read 3, iclass 19, count 0 2006.238.07:43:50.91#ibcon#read 3, iclass 19, count 0 2006.238.07:43:50.91#ibcon#about to read 4, iclass 19, count 0 2006.238.07:43:50.91#ibcon#read 4, iclass 19, count 0 2006.238.07:43:50.91#ibcon#about to read 5, iclass 19, count 0 2006.238.07:43:50.91#ibcon#read 5, iclass 19, count 0 2006.238.07:43:50.91#ibcon#about to read 6, iclass 19, count 0 2006.238.07:43:50.91#ibcon#read 6, iclass 19, count 0 2006.238.07:43:50.91#ibcon#end of sib2, iclass 19, count 0 2006.238.07:43:50.91#ibcon#*after write, iclass 19, count 0 2006.238.07:43:50.91#ibcon#*before return 0, iclass 19, count 0 2006.238.07:43:50.91#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:43:50.91#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:43:50.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:43:50.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:43:50.91$vc4f8/vblo=2,640.99 2006.238.07:43:50.91#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.07:43:50.91#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.07:43:50.91#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:50.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:43:50.91#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:43:50.91#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:43:50.91#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:43:50.91#ibcon#first serial, iclass 21, count 0 2006.238.07:43:50.91#ibcon#enter sib2, iclass 21, count 0 2006.238.07:43:50.91#ibcon#flushed, iclass 21, count 0 2006.238.07:43:50.91#ibcon#about to write, iclass 21, count 0 2006.238.07:43:50.91#ibcon#wrote, iclass 21, count 0 2006.238.07:43:50.91#ibcon#about to read 3, iclass 21, count 0 2006.238.07:43:50.93#ibcon#read 3, iclass 21, count 0 2006.238.07:43:50.93#ibcon#about to read 4, iclass 21, count 0 2006.238.07:43:50.93#ibcon#read 4, iclass 21, count 0 2006.238.07:43:50.93#ibcon#about to read 5, iclass 21, count 0 2006.238.07:43:50.93#ibcon#read 5, iclass 21, count 0 2006.238.07:43:50.93#ibcon#about to read 6, iclass 21, count 0 2006.238.07:43:50.93#ibcon#read 6, iclass 21, count 0 2006.238.07:43:50.93#ibcon#end of sib2, iclass 21, count 0 2006.238.07:43:50.93#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:43:50.93#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:43:50.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:43:50.93#ibcon#*before write, iclass 21, count 0 2006.238.07:43:50.93#ibcon#enter sib2, iclass 21, count 0 2006.238.07:43:50.93#ibcon#flushed, iclass 21, count 0 2006.238.07:43:50.93#ibcon#about to write, iclass 21, count 0 2006.238.07:43:50.93#ibcon#wrote, iclass 21, count 0 2006.238.07:43:50.93#ibcon#about to read 3, iclass 21, count 0 2006.238.07:43:50.97#ibcon#read 3, iclass 21, count 0 2006.238.07:43:50.97#ibcon#about to read 4, iclass 21, count 0 2006.238.07:43:50.97#ibcon#read 4, iclass 21, count 0 2006.238.07:43:50.97#ibcon#about to read 5, iclass 21, count 0 2006.238.07:43:50.97#ibcon#read 5, iclass 21, count 0 2006.238.07:43:50.97#ibcon#about to read 6, iclass 21, count 0 2006.238.07:43:50.97#ibcon#read 6, iclass 21, count 0 2006.238.07:43:50.97#ibcon#end of sib2, iclass 21, count 0 2006.238.07:43:50.97#ibcon#*after write, iclass 21, count 0 2006.238.07:43:50.97#ibcon#*before return 0, iclass 21, count 0 2006.238.07:43:50.97#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:43:50.97#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:43:50.97#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:43:50.97#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:43:50.97$vc4f8/vb=2,4 2006.238.07:43:50.97#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.238.07:43:50.97#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.238.07:43:50.97#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:50.97#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:43:51.03#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:43:51.03#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:43:51.03#ibcon#enter wrdev, iclass 23, count 2 2006.238.07:43:51.03#ibcon#first serial, iclass 23, count 2 2006.238.07:43:51.03#ibcon#enter sib2, iclass 23, count 2 2006.238.07:43:51.03#ibcon#flushed, iclass 23, count 2 2006.238.07:43:51.03#ibcon#about to write, iclass 23, count 2 2006.238.07:43:51.03#ibcon#wrote, iclass 23, count 2 2006.238.07:43:51.03#ibcon#about to read 3, iclass 23, count 2 2006.238.07:43:51.05#ibcon#read 3, iclass 23, count 2 2006.238.07:43:51.05#ibcon#about to read 4, iclass 23, count 2 2006.238.07:43:51.05#ibcon#read 4, iclass 23, count 2 2006.238.07:43:51.05#ibcon#about to read 5, iclass 23, count 2 2006.238.07:43:51.05#ibcon#read 5, iclass 23, count 2 2006.238.07:43:51.05#ibcon#about to read 6, iclass 23, count 2 2006.238.07:43:51.05#ibcon#read 6, iclass 23, count 2 2006.238.07:43:51.05#ibcon#end of sib2, iclass 23, count 2 2006.238.07:43:51.05#ibcon#*mode == 0, iclass 23, count 2 2006.238.07:43:51.05#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.238.07:43:51.05#ibcon#[27=AT02-04\r\n] 2006.238.07:43:51.05#ibcon#*before write, iclass 23, count 2 2006.238.07:43:51.05#ibcon#enter sib2, iclass 23, count 2 2006.238.07:43:51.05#ibcon#flushed, iclass 23, count 2 2006.238.07:43:51.05#ibcon#about to write, iclass 23, count 2 2006.238.07:43:51.05#ibcon#wrote, iclass 23, count 2 2006.238.07:43:51.05#ibcon#about to read 3, iclass 23, count 2 2006.238.07:43:51.08#ibcon#read 3, iclass 23, count 2 2006.238.07:43:51.08#ibcon#about to read 4, iclass 23, count 2 2006.238.07:43:51.08#ibcon#read 4, iclass 23, count 2 2006.238.07:43:51.08#ibcon#about to read 5, iclass 23, count 2 2006.238.07:43:51.08#ibcon#read 5, iclass 23, count 2 2006.238.07:43:51.08#ibcon#about to read 6, iclass 23, count 2 2006.238.07:43:51.08#ibcon#read 6, iclass 23, count 2 2006.238.07:43:51.08#ibcon#end of sib2, iclass 23, count 2 2006.238.07:43:51.08#ibcon#*after write, iclass 23, count 2 2006.238.07:43:51.08#ibcon#*before return 0, iclass 23, count 2 2006.238.07:43:51.08#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:43:51.08#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:43:51.08#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.238.07:43:51.08#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:51.08#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:43:51.20#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:43:51.20#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:43:51.20#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:43:51.20#ibcon#first serial, iclass 23, count 0 2006.238.07:43:51.20#ibcon#enter sib2, iclass 23, count 0 2006.238.07:43:51.20#ibcon#flushed, iclass 23, count 0 2006.238.07:43:51.20#ibcon#about to write, iclass 23, count 0 2006.238.07:43:51.20#ibcon#wrote, iclass 23, count 0 2006.238.07:43:51.20#ibcon#about to read 3, iclass 23, count 0 2006.238.07:43:51.22#ibcon#read 3, iclass 23, count 0 2006.238.07:43:51.22#ibcon#about to read 4, iclass 23, count 0 2006.238.07:43:51.22#ibcon#read 4, iclass 23, count 0 2006.238.07:43:51.22#ibcon#about to read 5, iclass 23, count 0 2006.238.07:43:51.22#ibcon#read 5, iclass 23, count 0 2006.238.07:43:51.22#ibcon#about to read 6, iclass 23, count 0 2006.238.07:43:51.22#ibcon#read 6, iclass 23, count 0 2006.238.07:43:51.22#ibcon#end of sib2, iclass 23, count 0 2006.238.07:43:51.22#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:43:51.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:43:51.22#ibcon#[27=USB\r\n] 2006.238.07:43:51.22#ibcon#*before write, iclass 23, count 0 2006.238.07:43:51.22#ibcon#enter sib2, iclass 23, count 0 2006.238.07:43:51.22#ibcon#flushed, iclass 23, count 0 2006.238.07:43:51.22#ibcon#about to write, iclass 23, count 0 2006.238.07:43:51.22#ibcon#wrote, iclass 23, count 0 2006.238.07:43:51.22#ibcon#about to read 3, iclass 23, count 0 2006.238.07:43:51.25#ibcon#read 3, iclass 23, count 0 2006.238.07:43:51.25#ibcon#about to read 4, iclass 23, count 0 2006.238.07:43:51.25#ibcon#read 4, iclass 23, count 0 2006.238.07:43:51.25#ibcon#about to read 5, iclass 23, count 0 2006.238.07:43:51.25#ibcon#read 5, iclass 23, count 0 2006.238.07:43:51.25#ibcon#about to read 6, iclass 23, count 0 2006.238.07:43:51.25#ibcon#read 6, iclass 23, count 0 2006.238.07:43:51.25#ibcon#end of sib2, iclass 23, count 0 2006.238.07:43:51.25#ibcon#*after write, iclass 23, count 0 2006.238.07:43:51.25#ibcon#*before return 0, iclass 23, count 0 2006.238.07:43:51.25#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:43:51.25#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:43:51.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:43:51.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:43:51.25$vc4f8/vblo=3,656.99 2006.238.07:43:51.25#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.07:43:51.25#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.07:43:51.25#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:51.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:43:51.25#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:43:51.25#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:43:51.25#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:43:51.25#ibcon#first serial, iclass 25, count 0 2006.238.07:43:51.25#ibcon#enter sib2, iclass 25, count 0 2006.238.07:43:51.25#ibcon#flushed, iclass 25, count 0 2006.238.07:43:51.25#ibcon#about to write, iclass 25, count 0 2006.238.07:43:51.25#ibcon#wrote, iclass 25, count 0 2006.238.07:43:51.25#ibcon#about to read 3, iclass 25, count 0 2006.238.07:43:51.27#ibcon#read 3, iclass 25, count 0 2006.238.07:43:51.27#ibcon#about to read 4, iclass 25, count 0 2006.238.07:43:51.27#ibcon#read 4, iclass 25, count 0 2006.238.07:43:51.27#ibcon#about to read 5, iclass 25, count 0 2006.238.07:43:51.27#ibcon#read 5, iclass 25, count 0 2006.238.07:43:51.27#ibcon#about to read 6, iclass 25, count 0 2006.238.07:43:51.27#ibcon#read 6, iclass 25, count 0 2006.238.07:43:51.27#ibcon#end of sib2, iclass 25, count 0 2006.238.07:43:51.27#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:43:51.27#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:43:51.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:43:51.27#ibcon#*before write, iclass 25, count 0 2006.238.07:43:51.27#ibcon#enter sib2, iclass 25, count 0 2006.238.07:43:51.27#ibcon#flushed, iclass 25, count 0 2006.238.07:43:51.27#ibcon#about to write, iclass 25, count 0 2006.238.07:43:51.27#ibcon#wrote, iclass 25, count 0 2006.238.07:43:51.27#ibcon#about to read 3, iclass 25, count 0 2006.238.07:43:51.31#ibcon#read 3, iclass 25, count 0 2006.238.07:43:51.31#ibcon#about to read 4, iclass 25, count 0 2006.238.07:43:51.31#ibcon#read 4, iclass 25, count 0 2006.238.07:43:51.31#ibcon#about to read 5, iclass 25, count 0 2006.238.07:43:51.31#ibcon#read 5, iclass 25, count 0 2006.238.07:43:51.31#ibcon#about to read 6, iclass 25, count 0 2006.238.07:43:51.31#ibcon#read 6, iclass 25, count 0 2006.238.07:43:51.31#ibcon#end of sib2, iclass 25, count 0 2006.238.07:43:51.31#ibcon#*after write, iclass 25, count 0 2006.238.07:43:51.31#ibcon#*before return 0, iclass 25, count 0 2006.238.07:43:51.31#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:43:51.31#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:43:51.31#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:43:51.31#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:43:51.31$vc4f8/vb=3,4 2006.238.07:43:51.31#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.238.07:43:51.31#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.238.07:43:51.31#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:51.31#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:43:51.37#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:43:51.37#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:43:51.37#ibcon#enter wrdev, iclass 27, count 2 2006.238.07:43:51.37#ibcon#first serial, iclass 27, count 2 2006.238.07:43:51.37#ibcon#enter sib2, iclass 27, count 2 2006.238.07:43:51.37#ibcon#flushed, iclass 27, count 2 2006.238.07:43:51.37#ibcon#about to write, iclass 27, count 2 2006.238.07:43:51.37#ibcon#wrote, iclass 27, count 2 2006.238.07:43:51.37#ibcon#about to read 3, iclass 27, count 2 2006.238.07:43:51.39#ibcon#read 3, iclass 27, count 2 2006.238.07:43:51.39#ibcon#about to read 4, iclass 27, count 2 2006.238.07:43:51.39#ibcon#read 4, iclass 27, count 2 2006.238.07:43:51.39#ibcon#about to read 5, iclass 27, count 2 2006.238.07:43:51.39#ibcon#read 5, iclass 27, count 2 2006.238.07:43:51.39#ibcon#about to read 6, iclass 27, count 2 2006.238.07:43:51.39#ibcon#read 6, iclass 27, count 2 2006.238.07:43:51.39#ibcon#end of sib2, iclass 27, count 2 2006.238.07:43:51.39#ibcon#*mode == 0, iclass 27, count 2 2006.238.07:43:51.39#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.238.07:43:51.39#ibcon#[27=AT03-04\r\n] 2006.238.07:43:51.39#ibcon#*before write, iclass 27, count 2 2006.238.07:43:51.39#ibcon#enter sib2, iclass 27, count 2 2006.238.07:43:51.39#ibcon#flushed, iclass 27, count 2 2006.238.07:43:51.39#ibcon#about to write, iclass 27, count 2 2006.238.07:43:51.39#ibcon#wrote, iclass 27, count 2 2006.238.07:43:51.39#ibcon#about to read 3, iclass 27, count 2 2006.238.07:43:51.42#ibcon#read 3, iclass 27, count 2 2006.238.07:43:51.42#ibcon#about to read 4, iclass 27, count 2 2006.238.07:43:51.42#ibcon#read 4, iclass 27, count 2 2006.238.07:43:51.42#ibcon#about to read 5, iclass 27, count 2 2006.238.07:43:51.42#ibcon#read 5, iclass 27, count 2 2006.238.07:43:51.42#ibcon#about to read 6, iclass 27, count 2 2006.238.07:43:51.42#ibcon#read 6, iclass 27, count 2 2006.238.07:43:51.42#ibcon#end of sib2, iclass 27, count 2 2006.238.07:43:51.42#ibcon#*after write, iclass 27, count 2 2006.238.07:43:51.42#ibcon#*before return 0, iclass 27, count 2 2006.238.07:43:51.42#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:43:51.42#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:43:51.42#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.238.07:43:51.42#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:51.42#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:43:51.54#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:43:51.54#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:43:51.54#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:43:51.54#ibcon#first serial, iclass 27, count 0 2006.238.07:43:51.54#ibcon#enter sib2, iclass 27, count 0 2006.238.07:43:51.54#ibcon#flushed, iclass 27, count 0 2006.238.07:43:51.54#ibcon#about to write, iclass 27, count 0 2006.238.07:43:51.54#ibcon#wrote, iclass 27, count 0 2006.238.07:43:51.54#ibcon#about to read 3, iclass 27, count 0 2006.238.07:43:51.56#ibcon#read 3, iclass 27, count 0 2006.238.07:43:51.56#ibcon#about to read 4, iclass 27, count 0 2006.238.07:43:51.56#ibcon#read 4, iclass 27, count 0 2006.238.07:43:51.56#ibcon#about to read 5, iclass 27, count 0 2006.238.07:43:51.56#ibcon#read 5, iclass 27, count 0 2006.238.07:43:51.56#ibcon#about to read 6, iclass 27, count 0 2006.238.07:43:51.56#ibcon#read 6, iclass 27, count 0 2006.238.07:43:51.56#ibcon#end of sib2, iclass 27, count 0 2006.238.07:43:51.56#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:43:51.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:43:51.56#ibcon#[27=USB\r\n] 2006.238.07:43:51.56#ibcon#*before write, iclass 27, count 0 2006.238.07:43:51.56#ibcon#enter sib2, iclass 27, count 0 2006.238.07:43:51.56#ibcon#flushed, iclass 27, count 0 2006.238.07:43:51.56#ibcon#about to write, iclass 27, count 0 2006.238.07:43:51.56#ibcon#wrote, iclass 27, count 0 2006.238.07:43:51.56#ibcon#about to read 3, iclass 27, count 0 2006.238.07:43:51.59#ibcon#read 3, iclass 27, count 0 2006.238.07:43:51.59#ibcon#about to read 4, iclass 27, count 0 2006.238.07:43:51.59#ibcon#read 4, iclass 27, count 0 2006.238.07:43:51.59#ibcon#about to read 5, iclass 27, count 0 2006.238.07:43:51.59#ibcon#read 5, iclass 27, count 0 2006.238.07:43:51.59#ibcon#about to read 6, iclass 27, count 0 2006.238.07:43:51.59#ibcon#read 6, iclass 27, count 0 2006.238.07:43:51.59#ibcon#end of sib2, iclass 27, count 0 2006.238.07:43:51.59#ibcon#*after write, iclass 27, count 0 2006.238.07:43:51.59#ibcon#*before return 0, iclass 27, count 0 2006.238.07:43:51.59#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:43:51.59#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:43:51.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:43:51.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:43:51.59$vc4f8/vblo=4,712.99 2006.238.07:43:51.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.238.07:43:51.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.238.07:43:51.59#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:51.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:43:51.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:43:51.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:43:51.59#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:43:51.59#ibcon#first serial, iclass 29, count 0 2006.238.07:43:51.59#ibcon#enter sib2, iclass 29, count 0 2006.238.07:43:51.59#ibcon#flushed, iclass 29, count 0 2006.238.07:43:51.59#ibcon#about to write, iclass 29, count 0 2006.238.07:43:51.59#ibcon#wrote, iclass 29, count 0 2006.238.07:43:51.59#ibcon#about to read 3, iclass 29, count 0 2006.238.07:43:51.61#ibcon#read 3, iclass 29, count 0 2006.238.07:43:51.61#ibcon#about to read 4, iclass 29, count 0 2006.238.07:43:51.61#ibcon#read 4, iclass 29, count 0 2006.238.07:43:51.61#ibcon#about to read 5, iclass 29, count 0 2006.238.07:43:51.61#ibcon#read 5, iclass 29, count 0 2006.238.07:43:51.61#ibcon#about to read 6, iclass 29, count 0 2006.238.07:43:51.61#ibcon#read 6, iclass 29, count 0 2006.238.07:43:51.61#ibcon#end of sib2, iclass 29, count 0 2006.238.07:43:51.61#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:43:51.61#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:43:51.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:43:51.61#ibcon#*before write, iclass 29, count 0 2006.238.07:43:51.61#ibcon#enter sib2, iclass 29, count 0 2006.238.07:43:51.61#ibcon#flushed, iclass 29, count 0 2006.238.07:43:51.61#ibcon#about to write, iclass 29, count 0 2006.238.07:43:51.61#ibcon#wrote, iclass 29, count 0 2006.238.07:43:51.61#ibcon#about to read 3, iclass 29, count 0 2006.238.07:43:51.65#ibcon#read 3, iclass 29, count 0 2006.238.07:43:51.65#ibcon#about to read 4, iclass 29, count 0 2006.238.07:43:51.65#ibcon#read 4, iclass 29, count 0 2006.238.07:43:51.65#ibcon#about to read 5, iclass 29, count 0 2006.238.07:43:51.65#ibcon#read 5, iclass 29, count 0 2006.238.07:43:51.65#ibcon#about to read 6, iclass 29, count 0 2006.238.07:43:51.65#ibcon#read 6, iclass 29, count 0 2006.238.07:43:51.65#ibcon#end of sib2, iclass 29, count 0 2006.238.07:43:51.65#ibcon#*after write, iclass 29, count 0 2006.238.07:43:51.65#ibcon#*before return 0, iclass 29, count 0 2006.238.07:43:51.65#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:43:51.65#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:43:51.65#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:43:51.65#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:43:51.65$vc4f8/vb=4,4 2006.238.07:43:51.65#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.238.07:43:51.65#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.238.07:43:51.65#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:51.65#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:43:51.71#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:43:51.71#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:43:51.71#ibcon#enter wrdev, iclass 31, count 2 2006.238.07:43:51.71#ibcon#first serial, iclass 31, count 2 2006.238.07:43:51.71#ibcon#enter sib2, iclass 31, count 2 2006.238.07:43:51.71#ibcon#flushed, iclass 31, count 2 2006.238.07:43:51.71#ibcon#about to write, iclass 31, count 2 2006.238.07:43:51.71#ibcon#wrote, iclass 31, count 2 2006.238.07:43:51.71#ibcon#about to read 3, iclass 31, count 2 2006.238.07:43:51.73#ibcon#read 3, iclass 31, count 2 2006.238.07:43:51.73#ibcon#about to read 4, iclass 31, count 2 2006.238.07:43:51.73#ibcon#read 4, iclass 31, count 2 2006.238.07:43:51.73#ibcon#about to read 5, iclass 31, count 2 2006.238.07:43:51.73#ibcon#read 5, iclass 31, count 2 2006.238.07:43:51.73#ibcon#about to read 6, iclass 31, count 2 2006.238.07:43:51.73#ibcon#read 6, iclass 31, count 2 2006.238.07:43:51.73#ibcon#end of sib2, iclass 31, count 2 2006.238.07:43:51.73#ibcon#*mode == 0, iclass 31, count 2 2006.238.07:43:51.73#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.238.07:43:51.73#ibcon#[27=AT04-04\r\n] 2006.238.07:43:51.73#ibcon#*before write, iclass 31, count 2 2006.238.07:43:51.73#ibcon#enter sib2, iclass 31, count 2 2006.238.07:43:51.73#ibcon#flushed, iclass 31, count 2 2006.238.07:43:51.73#ibcon#about to write, iclass 31, count 2 2006.238.07:43:51.73#ibcon#wrote, iclass 31, count 2 2006.238.07:43:51.73#ibcon#about to read 3, iclass 31, count 2 2006.238.07:43:51.76#ibcon#read 3, iclass 31, count 2 2006.238.07:43:51.76#ibcon#about to read 4, iclass 31, count 2 2006.238.07:43:51.76#ibcon#read 4, iclass 31, count 2 2006.238.07:43:51.76#ibcon#about to read 5, iclass 31, count 2 2006.238.07:43:51.76#ibcon#read 5, iclass 31, count 2 2006.238.07:43:51.76#ibcon#about to read 6, iclass 31, count 2 2006.238.07:43:51.76#ibcon#read 6, iclass 31, count 2 2006.238.07:43:51.76#ibcon#end of sib2, iclass 31, count 2 2006.238.07:43:51.76#ibcon#*after write, iclass 31, count 2 2006.238.07:43:51.76#ibcon#*before return 0, iclass 31, count 2 2006.238.07:43:51.76#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:43:51.76#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:43:51.76#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.238.07:43:51.76#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:51.76#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:43:51.88#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:43:51.88#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:43:51.88#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:43:51.88#ibcon#first serial, iclass 31, count 0 2006.238.07:43:51.88#ibcon#enter sib2, iclass 31, count 0 2006.238.07:43:51.88#ibcon#flushed, iclass 31, count 0 2006.238.07:43:51.88#ibcon#about to write, iclass 31, count 0 2006.238.07:43:51.88#ibcon#wrote, iclass 31, count 0 2006.238.07:43:51.88#ibcon#about to read 3, iclass 31, count 0 2006.238.07:43:51.90#ibcon#read 3, iclass 31, count 0 2006.238.07:43:51.90#ibcon#about to read 4, iclass 31, count 0 2006.238.07:43:51.90#ibcon#read 4, iclass 31, count 0 2006.238.07:43:51.90#ibcon#about to read 5, iclass 31, count 0 2006.238.07:43:51.90#ibcon#read 5, iclass 31, count 0 2006.238.07:43:51.90#ibcon#about to read 6, iclass 31, count 0 2006.238.07:43:51.90#ibcon#read 6, iclass 31, count 0 2006.238.07:43:51.90#ibcon#end of sib2, iclass 31, count 0 2006.238.07:43:51.90#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:43:51.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:43:51.90#ibcon#[27=USB\r\n] 2006.238.07:43:51.90#ibcon#*before write, iclass 31, count 0 2006.238.07:43:51.90#ibcon#enter sib2, iclass 31, count 0 2006.238.07:43:51.90#ibcon#flushed, iclass 31, count 0 2006.238.07:43:51.90#ibcon#about to write, iclass 31, count 0 2006.238.07:43:51.90#ibcon#wrote, iclass 31, count 0 2006.238.07:43:51.90#ibcon#about to read 3, iclass 31, count 0 2006.238.07:43:51.93#ibcon#read 3, iclass 31, count 0 2006.238.07:43:51.93#ibcon#about to read 4, iclass 31, count 0 2006.238.07:43:51.93#ibcon#read 4, iclass 31, count 0 2006.238.07:43:51.93#ibcon#about to read 5, iclass 31, count 0 2006.238.07:43:51.93#ibcon#read 5, iclass 31, count 0 2006.238.07:43:51.93#ibcon#about to read 6, iclass 31, count 0 2006.238.07:43:51.93#ibcon#read 6, iclass 31, count 0 2006.238.07:43:51.93#ibcon#end of sib2, iclass 31, count 0 2006.238.07:43:51.93#ibcon#*after write, iclass 31, count 0 2006.238.07:43:51.93#ibcon#*before return 0, iclass 31, count 0 2006.238.07:43:51.93#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:43:51.93#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:43:51.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:43:51.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:43:51.93$vc4f8/vblo=5,744.99 2006.238.07:43:51.93#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.07:43:51.93#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.07:43:51.93#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:51.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:43:51.93#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:43:51.93#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:43:51.93#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:43:51.93#ibcon#first serial, iclass 33, count 0 2006.238.07:43:51.93#ibcon#enter sib2, iclass 33, count 0 2006.238.07:43:51.93#ibcon#flushed, iclass 33, count 0 2006.238.07:43:51.93#ibcon#about to write, iclass 33, count 0 2006.238.07:43:51.93#ibcon#wrote, iclass 33, count 0 2006.238.07:43:51.93#ibcon#about to read 3, iclass 33, count 0 2006.238.07:43:51.95#ibcon#read 3, iclass 33, count 0 2006.238.07:43:51.95#ibcon#about to read 4, iclass 33, count 0 2006.238.07:43:51.95#ibcon#read 4, iclass 33, count 0 2006.238.07:43:51.95#ibcon#about to read 5, iclass 33, count 0 2006.238.07:43:51.95#ibcon#read 5, iclass 33, count 0 2006.238.07:43:51.95#ibcon#about to read 6, iclass 33, count 0 2006.238.07:43:51.95#ibcon#read 6, iclass 33, count 0 2006.238.07:43:51.95#ibcon#end of sib2, iclass 33, count 0 2006.238.07:43:51.95#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:43:51.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:43:51.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:43:51.95#ibcon#*before write, iclass 33, count 0 2006.238.07:43:51.95#ibcon#enter sib2, iclass 33, count 0 2006.238.07:43:51.95#ibcon#flushed, iclass 33, count 0 2006.238.07:43:51.95#ibcon#about to write, iclass 33, count 0 2006.238.07:43:51.95#ibcon#wrote, iclass 33, count 0 2006.238.07:43:51.95#ibcon#about to read 3, iclass 33, count 0 2006.238.07:43:51.99#ibcon#read 3, iclass 33, count 0 2006.238.07:43:51.99#ibcon#about to read 4, iclass 33, count 0 2006.238.07:43:51.99#ibcon#read 4, iclass 33, count 0 2006.238.07:43:51.99#ibcon#about to read 5, iclass 33, count 0 2006.238.07:43:51.99#ibcon#read 5, iclass 33, count 0 2006.238.07:43:51.99#ibcon#about to read 6, iclass 33, count 0 2006.238.07:43:51.99#ibcon#read 6, iclass 33, count 0 2006.238.07:43:51.99#ibcon#end of sib2, iclass 33, count 0 2006.238.07:43:51.99#ibcon#*after write, iclass 33, count 0 2006.238.07:43:51.99#ibcon#*before return 0, iclass 33, count 0 2006.238.07:43:51.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:43:51.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:43:51.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:43:51.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:43:51.99$vc4f8/vb=5,4 2006.238.07:43:51.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.238.07:43:51.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.238.07:43:51.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:51.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:43:52.05#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:43:52.05#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:43:52.05#ibcon#enter wrdev, iclass 35, count 2 2006.238.07:43:52.05#ibcon#first serial, iclass 35, count 2 2006.238.07:43:52.05#ibcon#enter sib2, iclass 35, count 2 2006.238.07:43:52.05#ibcon#flushed, iclass 35, count 2 2006.238.07:43:52.05#ibcon#about to write, iclass 35, count 2 2006.238.07:43:52.05#ibcon#wrote, iclass 35, count 2 2006.238.07:43:52.05#ibcon#about to read 3, iclass 35, count 2 2006.238.07:43:52.07#ibcon#read 3, iclass 35, count 2 2006.238.07:43:52.07#ibcon#about to read 4, iclass 35, count 2 2006.238.07:43:52.07#ibcon#read 4, iclass 35, count 2 2006.238.07:43:52.07#ibcon#about to read 5, iclass 35, count 2 2006.238.07:43:52.07#ibcon#read 5, iclass 35, count 2 2006.238.07:43:52.07#ibcon#about to read 6, iclass 35, count 2 2006.238.07:43:52.07#ibcon#read 6, iclass 35, count 2 2006.238.07:43:52.07#ibcon#end of sib2, iclass 35, count 2 2006.238.07:43:52.07#ibcon#*mode == 0, iclass 35, count 2 2006.238.07:43:52.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.238.07:43:52.07#ibcon#[27=AT05-04\r\n] 2006.238.07:43:52.07#ibcon#*before write, iclass 35, count 2 2006.238.07:43:52.07#ibcon#enter sib2, iclass 35, count 2 2006.238.07:43:52.07#ibcon#flushed, iclass 35, count 2 2006.238.07:43:52.07#ibcon#about to write, iclass 35, count 2 2006.238.07:43:52.07#ibcon#wrote, iclass 35, count 2 2006.238.07:43:52.07#ibcon#about to read 3, iclass 35, count 2 2006.238.07:43:52.10#ibcon#read 3, iclass 35, count 2 2006.238.07:43:52.10#ibcon#about to read 4, iclass 35, count 2 2006.238.07:43:52.10#ibcon#read 4, iclass 35, count 2 2006.238.07:43:52.10#ibcon#about to read 5, iclass 35, count 2 2006.238.07:43:52.10#ibcon#read 5, iclass 35, count 2 2006.238.07:43:52.10#ibcon#about to read 6, iclass 35, count 2 2006.238.07:43:52.10#ibcon#read 6, iclass 35, count 2 2006.238.07:43:52.10#ibcon#end of sib2, iclass 35, count 2 2006.238.07:43:52.10#ibcon#*after write, iclass 35, count 2 2006.238.07:43:52.10#ibcon#*before return 0, iclass 35, count 2 2006.238.07:43:52.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:43:52.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:43:52.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.238.07:43:52.10#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:52.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:43:52.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:43:52.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:43:52.22#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:43:52.22#ibcon#first serial, iclass 35, count 0 2006.238.07:43:52.22#ibcon#enter sib2, iclass 35, count 0 2006.238.07:43:52.22#ibcon#flushed, iclass 35, count 0 2006.238.07:43:52.22#ibcon#about to write, iclass 35, count 0 2006.238.07:43:52.22#ibcon#wrote, iclass 35, count 0 2006.238.07:43:52.22#ibcon#about to read 3, iclass 35, count 0 2006.238.07:43:52.24#ibcon#read 3, iclass 35, count 0 2006.238.07:43:52.24#ibcon#about to read 4, iclass 35, count 0 2006.238.07:43:52.24#ibcon#read 4, iclass 35, count 0 2006.238.07:43:52.24#ibcon#about to read 5, iclass 35, count 0 2006.238.07:43:52.24#ibcon#read 5, iclass 35, count 0 2006.238.07:43:52.24#ibcon#about to read 6, iclass 35, count 0 2006.238.07:43:52.24#ibcon#read 6, iclass 35, count 0 2006.238.07:43:52.24#ibcon#end of sib2, iclass 35, count 0 2006.238.07:43:52.24#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:43:52.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:43:52.24#ibcon#[27=USB\r\n] 2006.238.07:43:52.24#ibcon#*before write, iclass 35, count 0 2006.238.07:43:52.24#ibcon#enter sib2, iclass 35, count 0 2006.238.07:43:52.24#ibcon#flushed, iclass 35, count 0 2006.238.07:43:52.24#ibcon#about to write, iclass 35, count 0 2006.238.07:43:52.24#ibcon#wrote, iclass 35, count 0 2006.238.07:43:52.24#ibcon#about to read 3, iclass 35, count 0 2006.238.07:43:52.27#ibcon#read 3, iclass 35, count 0 2006.238.07:43:52.27#ibcon#about to read 4, iclass 35, count 0 2006.238.07:43:52.27#ibcon#read 4, iclass 35, count 0 2006.238.07:43:52.27#ibcon#about to read 5, iclass 35, count 0 2006.238.07:43:52.27#ibcon#read 5, iclass 35, count 0 2006.238.07:43:52.27#ibcon#about to read 6, iclass 35, count 0 2006.238.07:43:52.27#ibcon#read 6, iclass 35, count 0 2006.238.07:43:52.27#ibcon#end of sib2, iclass 35, count 0 2006.238.07:43:52.27#ibcon#*after write, iclass 35, count 0 2006.238.07:43:52.27#ibcon#*before return 0, iclass 35, count 0 2006.238.07:43:52.27#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:43:52.27#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:43:52.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:43:52.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:43:52.27$vc4f8/vblo=6,752.99 2006.238.07:43:52.27#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.07:43:52.27#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.07:43:52.27#ibcon#ireg 17 cls_cnt 0 2006.238.07:43:52.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:43:52.27#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:43:52.27#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:43:52.27#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:43:52.27#ibcon#first serial, iclass 37, count 0 2006.238.07:43:52.27#ibcon#enter sib2, iclass 37, count 0 2006.238.07:43:52.27#ibcon#flushed, iclass 37, count 0 2006.238.07:43:52.27#ibcon#about to write, iclass 37, count 0 2006.238.07:43:52.27#ibcon#wrote, iclass 37, count 0 2006.238.07:43:52.27#ibcon#about to read 3, iclass 37, count 0 2006.238.07:43:52.29#ibcon#read 3, iclass 37, count 0 2006.238.07:43:52.29#ibcon#about to read 4, iclass 37, count 0 2006.238.07:43:52.29#ibcon#read 4, iclass 37, count 0 2006.238.07:43:52.29#ibcon#about to read 5, iclass 37, count 0 2006.238.07:43:52.29#ibcon#read 5, iclass 37, count 0 2006.238.07:43:52.29#ibcon#about to read 6, iclass 37, count 0 2006.238.07:43:52.29#ibcon#read 6, iclass 37, count 0 2006.238.07:43:52.29#ibcon#end of sib2, iclass 37, count 0 2006.238.07:43:52.29#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:43:52.29#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:43:52.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:43:52.29#ibcon#*before write, iclass 37, count 0 2006.238.07:43:52.29#ibcon#enter sib2, iclass 37, count 0 2006.238.07:43:52.29#ibcon#flushed, iclass 37, count 0 2006.238.07:43:52.29#ibcon#about to write, iclass 37, count 0 2006.238.07:43:52.29#ibcon#wrote, iclass 37, count 0 2006.238.07:43:52.29#ibcon#about to read 3, iclass 37, count 0 2006.238.07:43:52.33#ibcon#read 3, iclass 37, count 0 2006.238.07:43:52.33#ibcon#about to read 4, iclass 37, count 0 2006.238.07:43:52.33#ibcon#read 4, iclass 37, count 0 2006.238.07:43:52.33#ibcon#about to read 5, iclass 37, count 0 2006.238.07:43:52.33#ibcon#read 5, iclass 37, count 0 2006.238.07:43:52.33#ibcon#about to read 6, iclass 37, count 0 2006.238.07:43:52.33#ibcon#read 6, iclass 37, count 0 2006.238.07:43:52.33#ibcon#end of sib2, iclass 37, count 0 2006.238.07:43:52.33#ibcon#*after write, iclass 37, count 0 2006.238.07:43:52.33#ibcon#*before return 0, iclass 37, count 0 2006.238.07:43:52.33#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:43:52.33#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:43:52.33#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:43:52.33#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:43:52.33$vc4f8/vb=6,4 2006.238.07:43:52.33#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.238.07:43:52.33#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.238.07:43:52.33#ibcon#ireg 11 cls_cnt 2 2006.238.07:43:52.33#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:43:52.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:43:52.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:43:52.39#ibcon#enter wrdev, iclass 39, count 2 2006.238.07:43:52.39#ibcon#first serial, iclass 39, count 2 2006.238.07:43:52.39#ibcon#enter sib2, iclass 39, count 2 2006.238.07:43:52.39#ibcon#flushed, iclass 39, count 2 2006.238.07:43:52.39#ibcon#about to write, iclass 39, count 2 2006.238.07:43:52.39#ibcon#wrote, iclass 39, count 2 2006.238.07:43:52.39#ibcon#about to read 3, iclass 39, count 2 2006.238.07:43:52.41#ibcon#read 3, iclass 39, count 2 2006.238.07:43:52.41#ibcon#about to read 4, iclass 39, count 2 2006.238.07:43:52.41#ibcon#read 4, iclass 39, count 2 2006.238.07:43:52.41#ibcon#about to read 5, iclass 39, count 2 2006.238.07:43:52.41#ibcon#read 5, iclass 39, count 2 2006.238.07:43:52.41#ibcon#about to read 6, iclass 39, count 2 2006.238.07:43:52.41#ibcon#read 6, iclass 39, count 2 2006.238.07:43:52.41#ibcon#end of sib2, iclass 39, count 2 2006.238.07:43:52.41#ibcon#*mode == 0, iclass 39, count 2 2006.238.07:43:52.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.238.07:43:52.41#ibcon#[27=AT06-04\r\n] 2006.238.07:43:52.41#ibcon#*before write, iclass 39, count 2 2006.238.07:43:52.41#ibcon#enter sib2, iclass 39, count 2 2006.238.07:43:52.41#ibcon#flushed, iclass 39, count 2 2006.238.07:43:52.41#ibcon#about to write, iclass 39, count 2 2006.238.07:43:52.41#ibcon#wrote, iclass 39, count 2 2006.238.07:43:52.41#ibcon#about to read 3, iclass 39, count 2 2006.238.07:43:52.44#ibcon#read 3, iclass 39, count 2 2006.238.07:43:52.44#ibcon#about to read 4, iclass 39, count 2 2006.238.07:43:52.44#ibcon#read 4, iclass 39, count 2 2006.238.07:43:52.44#ibcon#about to read 5, iclass 39, count 2 2006.238.07:43:52.44#ibcon#read 5, iclass 39, count 2 2006.238.07:43:52.44#ibcon#about to read 6, iclass 39, count 2 2006.238.07:43:52.44#ibcon#read 6, iclass 39, count 2 2006.238.07:43:52.44#ibcon#end of sib2, iclass 39, count 2 2006.238.07:43:52.44#ibcon#*after write, iclass 39, count 2 2006.238.07:43:52.44#ibcon#*before return 0, iclass 39, count 2 2006.238.07:43:52.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:43:52.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:43:52.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.238.07:43:52.44#ibcon#ireg 7 cls_cnt 0 2006.238.07:43:52.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:43:52.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:43:52.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:43:52.56#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:43:52.56#ibcon#first serial, iclass 39, count 0 2006.238.07:43:52.56#ibcon#enter sib2, iclass 39, count 0 2006.238.07:43:52.56#ibcon#flushed, iclass 39, count 0 2006.238.07:43:52.56#ibcon#about to write, iclass 39, count 0 2006.238.07:43:52.56#ibcon#wrote, iclass 39, count 0 2006.238.07:43:52.56#ibcon#about to read 3, iclass 39, count 0 2006.238.07:43:52.58#ibcon#read 3, iclass 39, count 0 2006.238.07:43:52.58#ibcon#about to read 4, iclass 39, count 0 2006.238.07:43:52.58#ibcon#read 4, iclass 39, count 0 2006.238.07:43:52.58#ibcon#about to read 5, iclass 39, count 0 2006.238.07:43:52.58#ibcon#read 5, iclass 39, count 0 2006.238.07:43:52.58#ibcon#about to read 6, iclass 39, count 0 2006.238.07:43:52.58#ibcon#read 6, iclass 39, count 0 2006.238.07:43:52.58#ibcon#end of sib2, iclass 39, count 0 2006.238.07:43:52.58#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:43:52.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:43:52.58#ibcon#[27=USB\r\n] 2006.238.07:43:52.58#ibcon#*before write, iclass 39, count 0 2006.238.07:43:52.58#ibcon#enter sib2, iclass 39, count 0 2006.238.07:43:52.58#ibcon#flushed, iclass 39, count 0 2006.238.07:43:52.58#ibcon#about to write, iclass 39, count 0 2006.238.07:43:52.58#ibcon#wrote, iclass 39, count 0 2006.238.07:43:52.58#ibcon#about to read 3, iclass 39, count 0 2006.238.07:43:52.61#ibcon#read 3, iclass 39, count 0 2006.238.07:43:52.61#ibcon#about to read 4, iclass 39, count 0 2006.238.07:43:52.61#ibcon#read 4, iclass 39, count 0 2006.238.07:43:52.61#ibcon#about to read 5, iclass 39, count 0 2006.238.07:43:52.61#ibcon#read 5, iclass 39, count 0 2006.238.07:43:52.61#ibcon#about to read 6, iclass 39, count 0 2006.238.07:43:52.61#ibcon#read 6, iclass 39, count 0 2006.238.07:43:52.61#ibcon#end of sib2, iclass 39, count 0 2006.238.07:43:52.61#ibcon#*after write, iclass 39, count 0 2006.238.07:43:52.61#ibcon#*before return 0, iclass 39, count 0 2006.238.07:43:52.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:43:52.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:43:52.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:43:52.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:43:52.61$vc4f8/vabw=wide 2006.238.07:43:52.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.07:43:52.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.07:43:52.61#ibcon#ireg 8 cls_cnt 0 2006.238.07:43:52.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:43:52.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:43:52.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:43:52.61#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:43:52.61#ibcon#first serial, iclass 3, count 0 2006.238.07:43:52.61#ibcon#enter sib2, iclass 3, count 0 2006.238.07:43:52.61#ibcon#flushed, iclass 3, count 0 2006.238.07:43:52.61#ibcon#about to write, iclass 3, count 0 2006.238.07:43:52.61#ibcon#wrote, iclass 3, count 0 2006.238.07:43:52.61#ibcon#about to read 3, iclass 3, count 0 2006.238.07:43:52.63#ibcon#read 3, iclass 3, count 0 2006.238.07:43:52.63#ibcon#about to read 4, iclass 3, count 0 2006.238.07:43:52.63#ibcon#read 4, iclass 3, count 0 2006.238.07:43:52.63#ibcon#about to read 5, iclass 3, count 0 2006.238.07:43:52.63#ibcon#read 5, iclass 3, count 0 2006.238.07:43:52.63#ibcon#about to read 6, iclass 3, count 0 2006.238.07:43:52.63#ibcon#read 6, iclass 3, count 0 2006.238.07:43:52.63#ibcon#end of sib2, iclass 3, count 0 2006.238.07:43:52.63#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:43:52.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:43:52.63#ibcon#[25=BW32\r\n] 2006.238.07:43:52.63#ibcon#*before write, iclass 3, count 0 2006.238.07:43:52.63#ibcon#enter sib2, iclass 3, count 0 2006.238.07:43:52.63#ibcon#flushed, iclass 3, count 0 2006.238.07:43:52.63#ibcon#about to write, iclass 3, count 0 2006.238.07:43:52.63#ibcon#wrote, iclass 3, count 0 2006.238.07:43:52.63#ibcon#about to read 3, iclass 3, count 0 2006.238.07:43:52.66#ibcon#read 3, iclass 3, count 0 2006.238.07:43:52.66#ibcon#about to read 4, iclass 3, count 0 2006.238.07:43:52.66#ibcon#read 4, iclass 3, count 0 2006.238.07:43:52.66#ibcon#about to read 5, iclass 3, count 0 2006.238.07:43:52.66#ibcon#read 5, iclass 3, count 0 2006.238.07:43:52.66#ibcon#about to read 6, iclass 3, count 0 2006.238.07:43:52.66#ibcon#read 6, iclass 3, count 0 2006.238.07:43:52.66#ibcon#end of sib2, iclass 3, count 0 2006.238.07:43:52.66#ibcon#*after write, iclass 3, count 0 2006.238.07:43:52.66#ibcon#*before return 0, iclass 3, count 0 2006.238.07:43:52.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:43:52.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:43:52.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:43:52.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:43:52.66$vc4f8/vbbw=wide 2006.238.07:43:52.66#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.07:43:52.66#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.07:43:52.66#ibcon#ireg 8 cls_cnt 0 2006.238.07:43:52.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:43:52.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:43:52.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:43:52.73#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:43:52.73#ibcon#first serial, iclass 5, count 0 2006.238.07:43:52.73#ibcon#enter sib2, iclass 5, count 0 2006.238.07:43:52.73#ibcon#flushed, iclass 5, count 0 2006.238.07:43:52.73#ibcon#about to write, iclass 5, count 0 2006.238.07:43:52.73#ibcon#wrote, iclass 5, count 0 2006.238.07:43:52.73#ibcon#about to read 3, iclass 5, count 0 2006.238.07:43:52.75#ibcon#read 3, iclass 5, count 0 2006.238.07:43:52.75#ibcon#about to read 4, iclass 5, count 0 2006.238.07:43:52.75#ibcon#read 4, iclass 5, count 0 2006.238.07:43:52.75#ibcon#about to read 5, iclass 5, count 0 2006.238.07:43:52.75#ibcon#read 5, iclass 5, count 0 2006.238.07:43:52.75#ibcon#about to read 6, iclass 5, count 0 2006.238.07:43:52.75#ibcon#read 6, iclass 5, count 0 2006.238.07:43:52.75#ibcon#end of sib2, iclass 5, count 0 2006.238.07:43:52.75#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:43:52.75#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:43:52.75#ibcon#[27=BW32\r\n] 2006.238.07:43:52.75#ibcon#*before write, iclass 5, count 0 2006.238.07:43:52.75#ibcon#enter sib2, iclass 5, count 0 2006.238.07:43:52.75#ibcon#flushed, iclass 5, count 0 2006.238.07:43:52.75#ibcon#about to write, iclass 5, count 0 2006.238.07:43:52.75#ibcon#wrote, iclass 5, count 0 2006.238.07:43:52.75#ibcon#about to read 3, iclass 5, count 0 2006.238.07:43:52.78#ibcon#read 3, iclass 5, count 0 2006.238.07:43:52.78#ibcon#about to read 4, iclass 5, count 0 2006.238.07:43:52.78#ibcon#read 4, iclass 5, count 0 2006.238.07:43:52.78#ibcon#about to read 5, iclass 5, count 0 2006.238.07:43:52.78#ibcon#read 5, iclass 5, count 0 2006.238.07:43:52.78#ibcon#about to read 6, iclass 5, count 0 2006.238.07:43:52.78#ibcon#read 6, iclass 5, count 0 2006.238.07:43:52.78#ibcon#end of sib2, iclass 5, count 0 2006.238.07:43:52.78#ibcon#*after write, iclass 5, count 0 2006.238.07:43:52.78#ibcon#*before return 0, iclass 5, count 0 2006.238.07:43:52.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:43:52.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:43:52.78#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:43:52.78#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:43:52.78$4f8m12a/ifd4f 2006.238.07:43:52.78$ifd4f/lo= 2006.238.07:43:52.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:43:52.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:43:52.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:43:52.78$ifd4f/patch= 2006.238.07:43:52.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:43:52.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:43:52.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:43:52.78$4f8m12a/"form=m,16.000,1:2 2006.238.07:43:52.78$4f8m12a/"tpicd 2006.238.07:43:52.78$4f8m12a/echo=off 2006.238.07:43:52.78$4f8m12a/xlog=off 2006.238.07:43:52.78:!2006.238.07:44:20 2006.238.07:44:04.14#trakl#Source acquired 2006.238.07:44:05.14#flagr#flagr/antenna,acquired 2006.238.07:44:20.00:preob 2006.238.07:44:21.14/onsource/TRACKING 2006.238.07:44:21.14:!2006.238.07:44:30 2006.238.07:44:30.00:data_valid=on 2006.238.07:44:30.00:midob 2006.238.07:44:30.14/onsource/TRACKING 2006.238.07:44:30.14/wx/25.31,1012.2,87 2006.238.07:44:30.21/cable/+6.4178E-03 2006.238.07:44:31.30/va/01,08,usb,yes,39,41 2006.238.07:44:31.30/va/02,07,usb,yes,39,41 2006.238.07:44:31.30/va/03,07,usb,yes,37,37 2006.238.07:44:31.30/va/04,07,usb,yes,41,44 2006.238.07:44:31.30/va/05,08,usb,yes,38,40 2006.238.07:44:31.30/va/06,07,usb,yes,41,41 2006.238.07:44:31.30/va/07,07,usb,yes,41,41 2006.238.07:44:31.30/va/08,07,usb,yes,44,43 2006.238.07:44:31.53/valo/01,532.99,yes,locked 2006.238.07:44:31.53/valo/02,572.99,yes,locked 2006.238.07:44:31.53/valo/03,672.99,yes,locked 2006.238.07:44:31.53/valo/04,832.99,yes,locked 2006.238.07:44:31.53/valo/05,652.99,yes,locked 2006.238.07:44:31.53/valo/06,772.99,yes,locked 2006.238.07:44:31.53/valo/07,832.99,yes,locked 2006.238.07:44:31.53/valo/08,852.99,yes,locked 2006.238.07:44:32.62/vb/01,04,usb,yes,34,66 2006.238.07:44:32.62/vb/02,04,usb,yes,35,70 2006.238.07:44:32.62/vb/03,04,usb,yes,32,40 2006.238.07:44:32.62/vb/04,04,usb,yes,33,33 2006.238.07:44:32.62/vb/05,04,usb,yes,32,36 2006.238.07:44:32.62/vb/06,04,usb,yes,33,36 2006.238.07:44:32.62/vb/07,04,usb,yes,35,35 2006.238.07:44:32.62/vb/08,04,usb,yes,32,36 2006.238.07:44:32.85/vblo/01,632.99,yes,locked 2006.238.07:44:32.85/vblo/02,640.99,yes,locked 2006.238.07:44:32.85/vblo/03,656.99,yes,locked 2006.238.07:44:32.85/vblo/04,712.99,yes,locked 2006.238.07:44:32.85/vblo/05,744.99,yes,locked 2006.238.07:44:32.85/vblo/06,752.99,yes,locked 2006.238.07:44:32.85/vblo/07,734.99,yes,locked 2006.238.07:44:32.85/vblo/08,744.99,yes,locked 2006.238.07:44:33.00/vabw/8 2006.238.07:44:33.15/vbbw/8 2006.238.07:44:33.24/xfe/off,on,14.0 2006.238.07:44:33.61/ifatt/23,28,28,28 2006.238.07:44:34.08/fmout-gps/S +4.35E-07 2006.238.07:44:34.12:!2006.238.07:45:30 2006.238.07:45:30.00:data_valid=off 2006.238.07:45:30.00:postob 2006.238.07:45:30.09/cable/+6.4172E-03 2006.238.07:45:30.09/wx/25.31,1012.2,88 2006.238.07:45:31.08/fmout-gps/S +4.33E-07 2006.238.07:45:31.08:scan_name=238-0746,k06238,60 2006.238.07:45:31.09:source=3c371,180650.68,694928.1,2000.0,cw 2006.238.07:45:31.14#flagr#flagr/antenna,new-source 2006.238.07:45:32.14:checkk5 2006.238.07:45:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:45:32.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:45:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:45:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:45:34.02/chk_obsdata//k5ts1/T2380744??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:45:34.39/chk_obsdata//k5ts2/T2380744??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:45:34.76/chk_obsdata//k5ts3/T2380744??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:45:35.13/chk_obsdata//k5ts4/T2380744??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:45:35.83/k5log//k5ts1_log_newline 2006.238.07:45:36.55/k5log//k5ts2_log_newline 2006.238.07:45:37.25/k5log//k5ts3_log_newline 2006.238.07:45:37.95/k5log//k5ts4_log_newline 2006.238.07:45:37.97/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:45:37.97:4f8m12a=1 2006.238.07:45:37.97$4f8m12a/echo=on 2006.238.07:45:37.97$4f8m12a/pcalon 2006.238.07:45:37.97$pcalon/"no phase cal control is implemented here 2006.238.07:45:37.97$4f8m12a/"tpicd=stop 2006.238.07:45:37.97$4f8m12a/vc4f8 2006.238.07:45:37.97$vc4f8/valo=1,532.99 2006.238.07:45:37.98#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.07:45:37.98#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.07:45:37.98#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:37.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:45:37.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:45:37.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:45:37.98#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:45:37.98#ibcon#first serial, iclass 14, count 0 2006.238.07:45:37.98#ibcon#enter sib2, iclass 14, count 0 2006.238.07:45:37.98#ibcon#flushed, iclass 14, count 0 2006.238.07:45:37.98#ibcon#about to write, iclass 14, count 0 2006.238.07:45:37.98#ibcon#wrote, iclass 14, count 0 2006.238.07:45:37.98#ibcon#about to read 3, iclass 14, count 0 2006.238.07:45:38.02#ibcon#read 3, iclass 14, count 0 2006.238.07:45:38.02#ibcon#about to read 4, iclass 14, count 0 2006.238.07:45:38.02#ibcon#read 4, iclass 14, count 0 2006.238.07:45:38.02#ibcon#about to read 5, iclass 14, count 0 2006.238.07:45:38.02#ibcon#read 5, iclass 14, count 0 2006.238.07:45:38.02#ibcon#about to read 6, iclass 14, count 0 2006.238.07:45:38.02#ibcon#read 6, iclass 14, count 0 2006.238.07:45:38.02#ibcon#end of sib2, iclass 14, count 0 2006.238.07:45:38.02#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:45:38.02#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:45:38.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:45:38.02#ibcon#*before write, iclass 14, count 0 2006.238.07:45:38.02#ibcon#enter sib2, iclass 14, count 0 2006.238.07:45:38.02#ibcon#flushed, iclass 14, count 0 2006.238.07:45:38.02#ibcon#about to write, iclass 14, count 0 2006.238.07:45:38.02#ibcon#wrote, iclass 14, count 0 2006.238.07:45:38.02#ibcon#about to read 3, iclass 14, count 0 2006.238.07:45:38.07#ibcon#read 3, iclass 14, count 0 2006.238.07:45:38.07#ibcon#about to read 4, iclass 14, count 0 2006.238.07:45:38.07#ibcon#read 4, iclass 14, count 0 2006.238.07:45:38.07#ibcon#about to read 5, iclass 14, count 0 2006.238.07:45:38.07#ibcon#read 5, iclass 14, count 0 2006.238.07:45:38.07#ibcon#about to read 6, iclass 14, count 0 2006.238.07:45:38.07#ibcon#read 6, iclass 14, count 0 2006.238.07:45:38.07#ibcon#end of sib2, iclass 14, count 0 2006.238.07:45:38.07#ibcon#*after write, iclass 14, count 0 2006.238.07:45:38.07#ibcon#*before return 0, iclass 14, count 0 2006.238.07:45:38.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:45:38.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:45:38.07#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:45:38.07#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:45:38.07$vc4f8/va=1,8 2006.238.07:45:38.07#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.238.07:45:38.07#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.238.07:45:38.07#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:38.07#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:45:38.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:45:38.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:45:38.07#ibcon#enter wrdev, iclass 16, count 2 2006.238.07:45:38.07#ibcon#first serial, iclass 16, count 2 2006.238.07:45:38.07#ibcon#enter sib2, iclass 16, count 2 2006.238.07:45:38.07#ibcon#flushed, iclass 16, count 2 2006.238.07:45:38.07#ibcon#about to write, iclass 16, count 2 2006.238.07:45:38.07#ibcon#wrote, iclass 16, count 2 2006.238.07:45:38.07#ibcon#about to read 3, iclass 16, count 2 2006.238.07:45:38.09#ibcon#read 3, iclass 16, count 2 2006.238.07:45:38.09#ibcon#about to read 4, iclass 16, count 2 2006.238.07:45:38.09#ibcon#read 4, iclass 16, count 2 2006.238.07:45:38.09#ibcon#about to read 5, iclass 16, count 2 2006.238.07:45:38.09#ibcon#read 5, iclass 16, count 2 2006.238.07:45:38.09#ibcon#about to read 6, iclass 16, count 2 2006.238.07:45:38.09#ibcon#read 6, iclass 16, count 2 2006.238.07:45:38.09#ibcon#end of sib2, iclass 16, count 2 2006.238.07:45:38.09#ibcon#*mode == 0, iclass 16, count 2 2006.238.07:45:38.09#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.238.07:45:38.09#ibcon#[25=AT01-08\r\n] 2006.238.07:45:38.09#ibcon#*before write, iclass 16, count 2 2006.238.07:45:38.09#ibcon#enter sib2, iclass 16, count 2 2006.238.07:45:38.09#ibcon#flushed, iclass 16, count 2 2006.238.07:45:38.09#ibcon#about to write, iclass 16, count 2 2006.238.07:45:38.09#ibcon#wrote, iclass 16, count 2 2006.238.07:45:38.09#ibcon#about to read 3, iclass 16, count 2 2006.238.07:45:38.13#ibcon#read 3, iclass 16, count 2 2006.238.07:45:38.13#ibcon#about to read 4, iclass 16, count 2 2006.238.07:45:38.13#ibcon#read 4, iclass 16, count 2 2006.238.07:45:38.13#ibcon#about to read 5, iclass 16, count 2 2006.238.07:45:38.13#ibcon#read 5, iclass 16, count 2 2006.238.07:45:38.13#ibcon#about to read 6, iclass 16, count 2 2006.238.07:45:38.13#ibcon#read 6, iclass 16, count 2 2006.238.07:45:38.13#ibcon#end of sib2, iclass 16, count 2 2006.238.07:45:38.13#ibcon#*after write, iclass 16, count 2 2006.238.07:45:38.13#ibcon#*before return 0, iclass 16, count 2 2006.238.07:45:38.13#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:45:38.13#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:45:38.13#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.238.07:45:38.13#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:38.13#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:45:38.25#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:45:38.25#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:45:38.25#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:45:38.25#ibcon#first serial, iclass 16, count 0 2006.238.07:45:38.25#ibcon#enter sib2, iclass 16, count 0 2006.238.07:45:38.25#ibcon#flushed, iclass 16, count 0 2006.238.07:45:38.25#ibcon#about to write, iclass 16, count 0 2006.238.07:45:38.25#ibcon#wrote, iclass 16, count 0 2006.238.07:45:38.25#ibcon#about to read 3, iclass 16, count 0 2006.238.07:45:38.27#ibcon#read 3, iclass 16, count 0 2006.238.07:45:38.27#ibcon#about to read 4, iclass 16, count 0 2006.238.07:45:38.27#ibcon#read 4, iclass 16, count 0 2006.238.07:45:38.27#ibcon#about to read 5, iclass 16, count 0 2006.238.07:45:38.27#ibcon#read 5, iclass 16, count 0 2006.238.07:45:38.27#ibcon#about to read 6, iclass 16, count 0 2006.238.07:45:38.27#ibcon#read 6, iclass 16, count 0 2006.238.07:45:38.27#ibcon#end of sib2, iclass 16, count 0 2006.238.07:45:38.27#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:45:38.27#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:45:38.27#ibcon#[25=USB\r\n] 2006.238.07:45:38.27#ibcon#*before write, iclass 16, count 0 2006.238.07:45:38.27#ibcon#enter sib2, iclass 16, count 0 2006.238.07:45:38.27#ibcon#flushed, iclass 16, count 0 2006.238.07:45:38.27#ibcon#about to write, iclass 16, count 0 2006.238.07:45:38.27#ibcon#wrote, iclass 16, count 0 2006.238.07:45:38.27#ibcon#about to read 3, iclass 16, count 0 2006.238.07:45:38.30#ibcon#read 3, iclass 16, count 0 2006.238.07:45:38.30#ibcon#about to read 4, iclass 16, count 0 2006.238.07:45:38.30#ibcon#read 4, iclass 16, count 0 2006.238.07:45:38.30#ibcon#about to read 5, iclass 16, count 0 2006.238.07:45:38.30#ibcon#read 5, iclass 16, count 0 2006.238.07:45:38.30#ibcon#about to read 6, iclass 16, count 0 2006.238.07:45:38.30#ibcon#read 6, iclass 16, count 0 2006.238.07:45:38.30#ibcon#end of sib2, iclass 16, count 0 2006.238.07:45:38.30#ibcon#*after write, iclass 16, count 0 2006.238.07:45:38.30#ibcon#*before return 0, iclass 16, count 0 2006.238.07:45:38.30#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:45:38.30#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:45:38.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:45:38.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:45:38.30$vc4f8/valo=2,572.99 2006.238.07:45:38.30#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.07:45:38.30#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.07:45:38.30#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:38.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:45:38.30#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:45:38.30#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:45:38.30#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:45:38.30#ibcon#first serial, iclass 18, count 0 2006.238.07:45:38.30#ibcon#enter sib2, iclass 18, count 0 2006.238.07:45:38.30#ibcon#flushed, iclass 18, count 0 2006.238.07:45:38.30#ibcon#about to write, iclass 18, count 0 2006.238.07:45:38.30#ibcon#wrote, iclass 18, count 0 2006.238.07:45:38.30#ibcon#about to read 3, iclass 18, count 0 2006.238.07:45:38.32#ibcon#read 3, iclass 18, count 0 2006.238.07:45:38.32#ibcon#about to read 4, iclass 18, count 0 2006.238.07:45:38.32#ibcon#read 4, iclass 18, count 0 2006.238.07:45:38.32#ibcon#about to read 5, iclass 18, count 0 2006.238.07:45:38.32#ibcon#read 5, iclass 18, count 0 2006.238.07:45:38.32#ibcon#about to read 6, iclass 18, count 0 2006.238.07:45:38.32#ibcon#read 6, iclass 18, count 0 2006.238.07:45:38.32#ibcon#end of sib2, iclass 18, count 0 2006.238.07:45:38.32#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:45:38.32#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:45:38.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:45:38.32#ibcon#*before write, iclass 18, count 0 2006.238.07:45:38.32#ibcon#enter sib2, iclass 18, count 0 2006.238.07:45:38.32#ibcon#flushed, iclass 18, count 0 2006.238.07:45:38.32#ibcon#about to write, iclass 18, count 0 2006.238.07:45:38.32#ibcon#wrote, iclass 18, count 0 2006.238.07:45:38.32#ibcon#about to read 3, iclass 18, count 0 2006.238.07:45:38.36#ibcon#read 3, iclass 18, count 0 2006.238.07:45:38.36#ibcon#about to read 4, iclass 18, count 0 2006.238.07:45:38.36#ibcon#read 4, iclass 18, count 0 2006.238.07:45:38.36#ibcon#about to read 5, iclass 18, count 0 2006.238.07:45:38.36#ibcon#read 5, iclass 18, count 0 2006.238.07:45:38.36#ibcon#about to read 6, iclass 18, count 0 2006.238.07:45:38.36#ibcon#read 6, iclass 18, count 0 2006.238.07:45:38.36#ibcon#end of sib2, iclass 18, count 0 2006.238.07:45:38.36#ibcon#*after write, iclass 18, count 0 2006.238.07:45:38.36#ibcon#*before return 0, iclass 18, count 0 2006.238.07:45:38.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:45:38.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:45:38.36#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:45:38.36#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:45:38.36$vc4f8/va=2,7 2006.238.07:45:38.36#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.238.07:45:38.36#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.238.07:45:38.36#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:38.36#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:45:38.42#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:45:38.42#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:45:38.42#ibcon#enter wrdev, iclass 20, count 2 2006.238.07:45:38.42#ibcon#first serial, iclass 20, count 2 2006.238.07:45:38.42#ibcon#enter sib2, iclass 20, count 2 2006.238.07:45:38.42#ibcon#flushed, iclass 20, count 2 2006.238.07:45:38.42#ibcon#about to write, iclass 20, count 2 2006.238.07:45:38.42#ibcon#wrote, iclass 20, count 2 2006.238.07:45:38.42#ibcon#about to read 3, iclass 20, count 2 2006.238.07:45:38.44#ibcon#read 3, iclass 20, count 2 2006.238.07:45:38.44#ibcon#about to read 4, iclass 20, count 2 2006.238.07:45:38.44#ibcon#read 4, iclass 20, count 2 2006.238.07:45:38.44#ibcon#about to read 5, iclass 20, count 2 2006.238.07:45:38.44#ibcon#read 5, iclass 20, count 2 2006.238.07:45:38.44#ibcon#about to read 6, iclass 20, count 2 2006.238.07:45:38.44#ibcon#read 6, iclass 20, count 2 2006.238.07:45:38.44#ibcon#end of sib2, iclass 20, count 2 2006.238.07:45:38.44#ibcon#*mode == 0, iclass 20, count 2 2006.238.07:45:38.44#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.238.07:45:38.44#ibcon#[25=AT02-07\r\n] 2006.238.07:45:38.44#ibcon#*before write, iclass 20, count 2 2006.238.07:45:38.44#ibcon#enter sib2, iclass 20, count 2 2006.238.07:45:38.44#ibcon#flushed, iclass 20, count 2 2006.238.07:45:38.44#ibcon#about to write, iclass 20, count 2 2006.238.07:45:38.44#ibcon#wrote, iclass 20, count 2 2006.238.07:45:38.44#ibcon#about to read 3, iclass 20, count 2 2006.238.07:45:38.47#ibcon#read 3, iclass 20, count 2 2006.238.07:45:38.47#ibcon#about to read 4, iclass 20, count 2 2006.238.07:45:38.47#ibcon#read 4, iclass 20, count 2 2006.238.07:45:38.47#ibcon#about to read 5, iclass 20, count 2 2006.238.07:45:38.47#ibcon#read 5, iclass 20, count 2 2006.238.07:45:38.47#ibcon#about to read 6, iclass 20, count 2 2006.238.07:45:38.47#ibcon#read 6, iclass 20, count 2 2006.238.07:45:38.47#ibcon#end of sib2, iclass 20, count 2 2006.238.07:45:38.47#ibcon#*after write, iclass 20, count 2 2006.238.07:45:38.47#ibcon#*before return 0, iclass 20, count 2 2006.238.07:45:38.47#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:45:38.47#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:45:38.47#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.238.07:45:38.47#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:38.47#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:45:38.59#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:45:38.59#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:45:38.59#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:45:38.59#ibcon#first serial, iclass 20, count 0 2006.238.07:45:38.59#ibcon#enter sib2, iclass 20, count 0 2006.238.07:45:38.59#ibcon#flushed, iclass 20, count 0 2006.238.07:45:38.59#ibcon#about to write, iclass 20, count 0 2006.238.07:45:38.59#ibcon#wrote, iclass 20, count 0 2006.238.07:45:38.59#ibcon#about to read 3, iclass 20, count 0 2006.238.07:45:38.61#ibcon#read 3, iclass 20, count 0 2006.238.07:45:38.61#ibcon#about to read 4, iclass 20, count 0 2006.238.07:45:38.61#ibcon#read 4, iclass 20, count 0 2006.238.07:45:38.61#ibcon#about to read 5, iclass 20, count 0 2006.238.07:45:38.61#ibcon#read 5, iclass 20, count 0 2006.238.07:45:38.61#ibcon#about to read 6, iclass 20, count 0 2006.238.07:45:38.61#ibcon#read 6, iclass 20, count 0 2006.238.07:45:38.61#ibcon#end of sib2, iclass 20, count 0 2006.238.07:45:38.61#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:45:38.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:45:38.61#ibcon#[25=USB\r\n] 2006.238.07:45:38.61#ibcon#*before write, iclass 20, count 0 2006.238.07:45:38.61#ibcon#enter sib2, iclass 20, count 0 2006.238.07:45:38.61#ibcon#flushed, iclass 20, count 0 2006.238.07:45:38.61#ibcon#about to write, iclass 20, count 0 2006.238.07:45:38.61#ibcon#wrote, iclass 20, count 0 2006.238.07:45:38.61#ibcon#about to read 3, iclass 20, count 0 2006.238.07:45:38.64#ibcon#read 3, iclass 20, count 0 2006.238.07:45:38.64#ibcon#about to read 4, iclass 20, count 0 2006.238.07:45:38.64#ibcon#read 4, iclass 20, count 0 2006.238.07:45:38.64#ibcon#about to read 5, iclass 20, count 0 2006.238.07:45:38.64#ibcon#read 5, iclass 20, count 0 2006.238.07:45:38.64#ibcon#about to read 6, iclass 20, count 0 2006.238.07:45:38.64#ibcon#read 6, iclass 20, count 0 2006.238.07:45:38.64#ibcon#end of sib2, iclass 20, count 0 2006.238.07:45:38.64#ibcon#*after write, iclass 20, count 0 2006.238.07:45:38.64#ibcon#*before return 0, iclass 20, count 0 2006.238.07:45:38.64#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:45:38.64#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:45:38.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:45:38.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:45:38.64$vc4f8/valo=3,672.99 2006.238.07:45:38.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.07:45:38.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.07:45:38.64#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:38.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:45:38.64#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:45:38.64#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:45:38.64#ibcon#enter wrdev, iclass 22, count 0 2006.238.07:45:38.64#ibcon#first serial, iclass 22, count 0 2006.238.07:45:38.64#ibcon#enter sib2, iclass 22, count 0 2006.238.07:45:38.64#ibcon#flushed, iclass 22, count 0 2006.238.07:45:38.64#ibcon#about to write, iclass 22, count 0 2006.238.07:45:38.64#ibcon#wrote, iclass 22, count 0 2006.238.07:45:38.64#ibcon#about to read 3, iclass 22, count 0 2006.238.07:45:38.66#ibcon#read 3, iclass 22, count 0 2006.238.07:45:38.66#ibcon#about to read 4, iclass 22, count 0 2006.238.07:45:38.66#ibcon#read 4, iclass 22, count 0 2006.238.07:45:38.66#ibcon#about to read 5, iclass 22, count 0 2006.238.07:45:38.66#ibcon#read 5, iclass 22, count 0 2006.238.07:45:38.66#ibcon#about to read 6, iclass 22, count 0 2006.238.07:45:38.66#ibcon#read 6, iclass 22, count 0 2006.238.07:45:38.66#ibcon#end of sib2, iclass 22, count 0 2006.238.07:45:38.66#ibcon#*mode == 0, iclass 22, count 0 2006.238.07:45:38.66#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.07:45:38.66#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:45:38.66#ibcon#*before write, iclass 22, count 0 2006.238.07:45:38.66#ibcon#enter sib2, iclass 22, count 0 2006.238.07:45:38.66#ibcon#flushed, iclass 22, count 0 2006.238.07:45:38.66#ibcon#about to write, iclass 22, count 0 2006.238.07:45:38.66#ibcon#wrote, iclass 22, count 0 2006.238.07:45:38.66#ibcon#about to read 3, iclass 22, count 0 2006.238.07:45:38.70#ibcon#read 3, iclass 22, count 0 2006.238.07:45:38.70#ibcon#about to read 4, iclass 22, count 0 2006.238.07:45:38.70#ibcon#read 4, iclass 22, count 0 2006.238.07:45:38.70#ibcon#about to read 5, iclass 22, count 0 2006.238.07:45:38.70#ibcon#read 5, iclass 22, count 0 2006.238.07:45:38.70#ibcon#about to read 6, iclass 22, count 0 2006.238.07:45:38.70#ibcon#read 6, iclass 22, count 0 2006.238.07:45:38.70#ibcon#end of sib2, iclass 22, count 0 2006.238.07:45:38.70#ibcon#*after write, iclass 22, count 0 2006.238.07:45:38.70#ibcon#*before return 0, iclass 22, count 0 2006.238.07:45:38.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:45:38.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:45:38.70#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.07:45:38.70#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.07:45:38.70$vc4f8/va=3,7 2006.238.07:45:38.70#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.238.07:45:38.70#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.238.07:45:38.70#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:38.70#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:45:38.76#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:45:38.76#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:45:38.76#ibcon#enter wrdev, iclass 24, count 2 2006.238.07:45:38.76#ibcon#first serial, iclass 24, count 2 2006.238.07:45:38.76#ibcon#enter sib2, iclass 24, count 2 2006.238.07:45:38.76#ibcon#flushed, iclass 24, count 2 2006.238.07:45:38.76#ibcon#about to write, iclass 24, count 2 2006.238.07:45:38.76#ibcon#wrote, iclass 24, count 2 2006.238.07:45:38.76#ibcon#about to read 3, iclass 24, count 2 2006.238.07:45:38.78#ibcon#read 3, iclass 24, count 2 2006.238.07:45:38.78#ibcon#about to read 4, iclass 24, count 2 2006.238.07:45:38.78#ibcon#read 4, iclass 24, count 2 2006.238.07:45:38.78#ibcon#about to read 5, iclass 24, count 2 2006.238.07:45:38.78#ibcon#read 5, iclass 24, count 2 2006.238.07:45:38.78#ibcon#about to read 6, iclass 24, count 2 2006.238.07:45:38.78#ibcon#read 6, iclass 24, count 2 2006.238.07:45:38.78#ibcon#end of sib2, iclass 24, count 2 2006.238.07:45:38.78#ibcon#*mode == 0, iclass 24, count 2 2006.238.07:45:38.78#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.238.07:45:38.78#ibcon#[25=AT03-07\r\n] 2006.238.07:45:38.78#ibcon#*before write, iclass 24, count 2 2006.238.07:45:38.78#ibcon#enter sib2, iclass 24, count 2 2006.238.07:45:38.78#ibcon#flushed, iclass 24, count 2 2006.238.07:45:38.78#ibcon#about to write, iclass 24, count 2 2006.238.07:45:38.78#ibcon#wrote, iclass 24, count 2 2006.238.07:45:38.78#ibcon#about to read 3, iclass 24, count 2 2006.238.07:45:38.81#ibcon#read 3, iclass 24, count 2 2006.238.07:45:38.81#ibcon#about to read 4, iclass 24, count 2 2006.238.07:45:38.81#ibcon#read 4, iclass 24, count 2 2006.238.07:45:38.81#ibcon#about to read 5, iclass 24, count 2 2006.238.07:45:38.81#ibcon#read 5, iclass 24, count 2 2006.238.07:45:38.81#ibcon#about to read 6, iclass 24, count 2 2006.238.07:45:38.81#ibcon#read 6, iclass 24, count 2 2006.238.07:45:38.81#ibcon#end of sib2, iclass 24, count 2 2006.238.07:45:38.81#ibcon#*after write, iclass 24, count 2 2006.238.07:45:38.81#ibcon#*before return 0, iclass 24, count 2 2006.238.07:45:38.81#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:45:38.81#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:45:38.81#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.238.07:45:38.81#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:38.81#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:45:38.93#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:45:38.93#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:45:38.93#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:45:38.93#ibcon#first serial, iclass 24, count 0 2006.238.07:45:38.93#ibcon#enter sib2, iclass 24, count 0 2006.238.07:45:38.93#ibcon#flushed, iclass 24, count 0 2006.238.07:45:38.93#ibcon#about to write, iclass 24, count 0 2006.238.07:45:38.93#ibcon#wrote, iclass 24, count 0 2006.238.07:45:38.93#ibcon#about to read 3, iclass 24, count 0 2006.238.07:45:38.95#ibcon#read 3, iclass 24, count 0 2006.238.07:45:38.95#ibcon#about to read 4, iclass 24, count 0 2006.238.07:45:38.95#ibcon#read 4, iclass 24, count 0 2006.238.07:45:38.95#ibcon#about to read 5, iclass 24, count 0 2006.238.07:45:38.95#ibcon#read 5, iclass 24, count 0 2006.238.07:45:38.95#ibcon#about to read 6, iclass 24, count 0 2006.238.07:45:38.95#ibcon#read 6, iclass 24, count 0 2006.238.07:45:38.95#ibcon#end of sib2, iclass 24, count 0 2006.238.07:45:38.95#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:45:38.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:45:38.95#ibcon#[25=USB\r\n] 2006.238.07:45:38.95#ibcon#*before write, iclass 24, count 0 2006.238.07:45:38.95#ibcon#enter sib2, iclass 24, count 0 2006.238.07:45:38.95#ibcon#flushed, iclass 24, count 0 2006.238.07:45:38.95#ibcon#about to write, iclass 24, count 0 2006.238.07:45:38.95#ibcon#wrote, iclass 24, count 0 2006.238.07:45:38.95#ibcon#about to read 3, iclass 24, count 0 2006.238.07:45:38.98#ibcon#read 3, iclass 24, count 0 2006.238.07:45:38.98#ibcon#about to read 4, iclass 24, count 0 2006.238.07:45:38.98#ibcon#read 4, iclass 24, count 0 2006.238.07:45:38.98#ibcon#about to read 5, iclass 24, count 0 2006.238.07:45:38.98#ibcon#read 5, iclass 24, count 0 2006.238.07:45:38.98#ibcon#about to read 6, iclass 24, count 0 2006.238.07:45:38.98#ibcon#read 6, iclass 24, count 0 2006.238.07:45:38.98#ibcon#end of sib2, iclass 24, count 0 2006.238.07:45:38.98#ibcon#*after write, iclass 24, count 0 2006.238.07:45:38.98#ibcon#*before return 0, iclass 24, count 0 2006.238.07:45:38.98#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:45:38.98#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:45:38.98#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:45:38.98#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:45:38.98$vc4f8/valo=4,832.99 2006.238.07:45:38.98#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.07:45:38.98#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.07:45:38.98#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:38.98#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:45:38.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:45:38.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:45:38.98#ibcon#enter wrdev, iclass 26, count 0 2006.238.07:45:38.98#ibcon#first serial, iclass 26, count 0 2006.238.07:45:38.98#ibcon#enter sib2, iclass 26, count 0 2006.238.07:45:38.98#ibcon#flushed, iclass 26, count 0 2006.238.07:45:38.98#ibcon#about to write, iclass 26, count 0 2006.238.07:45:38.98#ibcon#wrote, iclass 26, count 0 2006.238.07:45:38.98#ibcon#about to read 3, iclass 26, count 0 2006.238.07:45:39.00#ibcon#read 3, iclass 26, count 0 2006.238.07:45:39.00#ibcon#about to read 4, iclass 26, count 0 2006.238.07:45:39.00#ibcon#read 4, iclass 26, count 0 2006.238.07:45:39.00#ibcon#about to read 5, iclass 26, count 0 2006.238.07:45:39.00#ibcon#read 5, iclass 26, count 0 2006.238.07:45:39.00#ibcon#about to read 6, iclass 26, count 0 2006.238.07:45:39.00#ibcon#read 6, iclass 26, count 0 2006.238.07:45:39.00#ibcon#end of sib2, iclass 26, count 0 2006.238.07:45:39.00#ibcon#*mode == 0, iclass 26, count 0 2006.238.07:45:39.00#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.07:45:39.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:45:39.00#ibcon#*before write, iclass 26, count 0 2006.238.07:45:39.00#ibcon#enter sib2, iclass 26, count 0 2006.238.07:45:39.00#ibcon#flushed, iclass 26, count 0 2006.238.07:45:39.00#ibcon#about to write, iclass 26, count 0 2006.238.07:45:39.00#ibcon#wrote, iclass 26, count 0 2006.238.07:45:39.00#ibcon#about to read 3, iclass 26, count 0 2006.238.07:45:39.04#ibcon#read 3, iclass 26, count 0 2006.238.07:45:39.04#ibcon#about to read 4, iclass 26, count 0 2006.238.07:45:39.04#ibcon#read 4, iclass 26, count 0 2006.238.07:45:39.04#ibcon#about to read 5, iclass 26, count 0 2006.238.07:45:39.04#ibcon#read 5, iclass 26, count 0 2006.238.07:45:39.04#ibcon#about to read 6, iclass 26, count 0 2006.238.07:45:39.04#ibcon#read 6, iclass 26, count 0 2006.238.07:45:39.04#ibcon#end of sib2, iclass 26, count 0 2006.238.07:45:39.04#ibcon#*after write, iclass 26, count 0 2006.238.07:45:39.04#ibcon#*before return 0, iclass 26, count 0 2006.238.07:45:39.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:45:39.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:45:39.04#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.07:45:39.04#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.07:45:39.04$vc4f8/va=4,7 2006.238.07:45:39.04#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.07:45:39.04#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.07:45:39.04#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:39.04#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:45:39.10#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:45:39.10#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:45:39.10#ibcon#enter wrdev, iclass 28, count 2 2006.238.07:45:39.10#ibcon#first serial, iclass 28, count 2 2006.238.07:45:39.10#ibcon#enter sib2, iclass 28, count 2 2006.238.07:45:39.10#ibcon#flushed, iclass 28, count 2 2006.238.07:45:39.10#ibcon#about to write, iclass 28, count 2 2006.238.07:45:39.10#ibcon#wrote, iclass 28, count 2 2006.238.07:45:39.10#ibcon#about to read 3, iclass 28, count 2 2006.238.07:45:39.12#ibcon#read 3, iclass 28, count 2 2006.238.07:45:39.12#ibcon#about to read 4, iclass 28, count 2 2006.238.07:45:39.12#ibcon#read 4, iclass 28, count 2 2006.238.07:45:39.12#ibcon#about to read 5, iclass 28, count 2 2006.238.07:45:39.12#ibcon#read 5, iclass 28, count 2 2006.238.07:45:39.12#ibcon#about to read 6, iclass 28, count 2 2006.238.07:45:39.12#ibcon#read 6, iclass 28, count 2 2006.238.07:45:39.12#ibcon#end of sib2, iclass 28, count 2 2006.238.07:45:39.12#ibcon#*mode == 0, iclass 28, count 2 2006.238.07:45:39.12#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.07:45:39.12#ibcon#[25=AT04-07\r\n] 2006.238.07:45:39.12#ibcon#*before write, iclass 28, count 2 2006.238.07:45:39.12#ibcon#enter sib2, iclass 28, count 2 2006.238.07:45:39.12#ibcon#flushed, iclass 28, count 2 2006.238.07:45:39.12#ibcon#about to write, iclass 28, count 2 2006.238.07:45:39.12#ibcon#wrote, iclass 28, count 2 2006.238.07:45:39.12#ibcon#about to read 3, iclass 28, count 2 2006.238.07:45:39.15#ibcon#read 3, iclass 28, count 2 2006.238.07:45:39.15#ibcon#about to read 4, iclass 28, count 2 2006.238.07:45:39.15#ibcon#read 4, iclass 28, count 2 2006.238.07:45:39.15#ibcon#about to read 5, iclass 28, count 2 2006.238.07:45:39.15#ibcon#read 5, iclass 28, count 2 2006.238.07:45:39.15#ibcon#about to read 6, iclass 28, count 2 2006.238.07:45:39.15#ibcon#read 6, iclass 28, count 2 2006.238.07:45:39.15#ibcon#end of sib2, iclass 28, count 2 2006.238.07:45:39.15#ibcon#*after write, iclass 28, count 2 2006.238.07:45:39.15#ibcon#*before return 0, iclass 28, count 2 2006.238.07:45:39.15#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:45:39.15#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:45:39.15#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.07:45:39.15#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:39.15#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:45:39.27#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:45:39.27#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:45:39.27#ibcon#enter wrdev, iclass 28, count 0 2006.238.07:45:39.27#ibcon#first serial, iclass 28, count 0 2006.238.07:45:39.27#ibcon#enter sib2, iclass 28, count 0 2006.238.07:45:39.27#ibcon#flushed, iclass 28, count 0 2006.238.07:45:39.27#ibcon#about to write, iclass 28, count 0 2006.238.07:45:39.27#ibcon#wrote, iclass 28, count 0 2006.238.07:45:39.27#ibcon#about to read 3, iclass 28, count 0 2006.238.07:45:39.29#ibcon#read 3, iclass 28, count 0 2006.238.07:45:39.29#ibcon#about to read 4, iclass 28, count 0 2006.238.07:45:39.29#ibcon#read 4, iclass 28, count 0 2006.238.07:45:39.29#ibcon#about to read 5, iclass 28, count 0 2006.238.07:45:39.29#ibcon#read 5, iclass 28, count 0 2006.238.07:45:39.29#ibcon#about to read 6, iclass 28, count 0 2006.238.07:45:39.29#ibcon#read 6, iclass 28, count 0 2006.238.07:45:39.29#ibcon#end of sib2, iclass 28, count 0 2006.238.07:45:39.29#ibcon#*mode == 0, iclass 28, count 0 2006.238.07:45:39.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.07:45:39.29#ibcon#[25=USB\r\n] 2006.238.07:45:39.29#ibcon#*before write, iclass 28, count 0 2006.238.07:45:39.29#ibcon#enter sib2, iclass 28, count 0 2006.238.07:45:39.29#ibcon#flushed, iclass 28, count 0 2006.238.07:45:39.29#ibcon#about to write, iclass 28, count 0 2006.238.07:45:39.29#ibcon#wrote, iclass 28, count 0 2006.238.07:45:39.29#ibcon#about to read 3, iclass 28, count 0 2006.238.07:45:39.32#ibcon#read 3, iclass 28, count 0 2006.238.07:45:39.32#ibcon#about to read 4, iclass 28, count 0 2006.238.07:45:39.32#ibcon#read 4, iclass 28, count 0 2006.238.07:45:39.32#ibcon#about to read 5, iclass 28, count 0 2006.238.07:45:39.32#ibcon#read 5, iclass 28, count 0 2006.238.07:45:39.32#ibcon#about to read 6, iclass 28, count 0 2006.238.07:45:39.32#ibcon#read 6, iclass 28, count 0 2006.238.07:45:39.32#ibcon#end of sib2, iclass 28, count 0 2006.238.07:45:39.32#ibcon#*after write, iclass 28, count 0 2006.238.07:45:39.32#ibcon#*before return 0, iclass 28, count 0 2006.238.07:45:39.32#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:45:39.32#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:45:39.32#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.07:45:39.32#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.07:45:39.32$vc4f8/valo=5,652.99 2006.238.07:45:39.32#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.07:45:39.32#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.07:45:39.32#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:39.32#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:45:39.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:45:39.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:45:39.32#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:45:39.32#ibcon#first serial, iclass 30, count 0 2006.238.07:45:39.32#ibcon#enter sib2, iclass 30, count 0 2006.238.07:45:39.32#ibcon#flushed, iclass 30, count 0 2006.238.07:45:39.32#ibcon#about to write, iclass 30, count 0 2006.238.07:45:39.32#ibcon#wrote, iclass 30, count 0 2006.238.07:45:39.32#ibcon#about to read 3, iclass 30, count 0 2006.238.07:45:39.34#ibcon#read 3, iclass 30, count 0 2006.238.07:45:39.34#ibcon#about to read 4, iclass 30, count 0 2006.238.07:45:39.34#ibcon#read 4, iclass 30, count 0 2006.238.07:45:39.34#ibcon#about to read 5, iclass 30, count 0 2006.238.07:45:39.34#ibcon#read 5, iclass 30, count 0 2006.238.07:45:39.34#ibcon#about to read 6, iclass 30, count 0 2006.238.07:45:39.34#ibcon#read 6, iclass 30, count 0 2006.238.07:45:39.34#ibcon#end of sib2, iclass 30, count 0 2006.238.07:45:39.34#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:45:39.34#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:45:39.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:45:39.34#ibcon#*before write, iclass 30, count 0 2006.238.07:45:39.34#ibcon#enter sib2, iclass 30, count 0 2006.238.07:45:39.34#ibcon#flushed, iclass 30, count 0 2006.238.07:45:39.34#ibcon#about to write, iclass 30, count 0 2006.238.07:45:39.34#ibcon#wrote, iclass 30, count 0 2006.238.07:45:39.34#ibcon#about to read 3, iclass 30, count 0 2006.238.07:45:39.38#ibcon#read 3, iclass 30, count 0 2006.238.07:45:39.38#ibcon#about to read 4, iclass 30, count 0 2006.238.07:45:39.38#ibcon#read 4, iclass 30, count 0 2006.238.07:45:39.38#ibcon#about to read 5, iclass 30, count 0 2006.238.07:45:39.38#ibcon#read 5, iclass 30, count 0 2006.238.07:45:39.38#ibcon#about to read 6, iclass 30, count 0 2006.238.07:45:39.38#ibcon#read 6, iclass 30, count 0 2006.238.07:45:39.38#ibcon#end of sib2, iclass 30, count 0 2006.238.07:45:39.38#ibcon#*after write, iclass 30, count 0 2006.238.07:45:39.38#ibcon#*before return 0, iclass 30, count 0 2006.238.07:45:39.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:45:39.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:45:39.38#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:45:39.38#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:45:39.38$vc4f8/va=5,8 2006.238.07:45:39.38#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.238.07:45:39.38#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.238.07:45:39.38#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:39.38#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:45:39.44#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:45:39.44#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:45:39.44#ibcon#enter wrdev, iclass 32, count 2 2006.238.07:45:39.44#ibcon#first serial, iclass 32, count 2 2006.238.07:45:39.44#ibcon#enter sib2, iclass 32, count 2 2006.238.07:45:39.44#ibcon#flushed, iclass 32, count 2 2006.238.07:45:39.44#ibcon#about to write, iclass 32, count 2 2006.238.07:45:39.44#ibcon#wrote, iclass 32, count 2 2006.238.07:45:39.44#ibcon#about to read 3, iclass 32, count 2 2006.238.07:45:39.46#ibcon#read 3, iclass 32, count 2 2006.238.07:45:39.46#ibcon#about to read 4, iclass 32, count 2 2006.238.07:45:39.46#ibcon#read 4, iclass 32, count 2 2006.238.07:45:39.46#ibcon#about to read 5, iclass 32, count 2 2006.238.07:45:39.46#ibcon#read 5, iclass 32, count 2 2006.238.07:45:39.46#ibcon#about to read 6, iclass 32, count 2 2006.238.07:45:39.46#ibcon#read 6, iclass 32, count 2 2006.238.07:45:39.46#ibcon#end of sib2, iclass 32, count 2 2006.238.07:45:39.46#ibcon#*mode == 0, iclass 32, count 2 2006.238.07:45:39.46#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.238.07:45:39.46#ibcon#[25=AT05-08\r\n] 2006.238.07:45:39.46#ibcon#*before write, iclass 32, count 2 2006.238.07:45:39.46#ibcon#enter sib2, iclass 32, count 2 2006.238.07:45:39.46#ibcon#flushed, iclass 32, count 2 2006.238.07:45:39.46#ibcon#about to write, iclass 32, count 2 2006.238.07:45:39.46#ibcon#wrote, iclass 32, count 2 2006.238.07:45:39.46#ibcon#about to read 3, iclass 32, count 2 2006.238.07:45:39.49#ibcon#read 3, iclass 32, count 2 2006.238.07:45:39.49#ibcon#about to read 4, iclass 32, count 2 2006.238.07:45:39.49#ibcon#read 4, iclass 32, count 2 2006.238.07:45:39.49#ibcon#about to read 5, iclass 32, count 2 2006.238.07:45:39.49#ibcon#read 5, iclass 32, count 2 2006.238.07:45:39.49#ibcon#about to read 6, iclass 32, count 2 2006.238.07:45:39.49#ibcon#read 6, iclass 32, count 2 2006.238.07:45:39.49#ibcon#end of sib2, iclass 32, count 2 2006.238.07:45:39.49#ibcon#*after write, iclass 32, count 2 2006.238.07:45:39.49#ibcon#*before return 0, iclass 32, count 2 2006.238.07:45:39.49#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:45:39.49#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:45:39.49#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.238.07:45:39.49#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:39.49#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:45:39.61#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:45:39.61#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:45:39.61#ibcon#enter wrdev, iclass 32, count 0 2006.238.07:45:39.61#ibcon#first serial, iclass 32, count 0 2006.238.07:45:39.61#ibcon#enter sib2, iclass 32, count 0 2006.238.07:45:39.61#ibcon#flushed, iclass 32, count 0 2006.238.07:45:39.61#ibcon#about to write, iclass 32, count 0 2006.238.07:45:39.61#ibcon#wrote, iclass 32, count 0 2006.238.07:45:39.61#ibcon#about to read 3, iclass 32, count 0 2006.238.07:45:39.63#ibcon#read 3, iclass 32, count 0 2006.238.07:45:39.63#ibcon#about to read 4, iclass 32, count 0 2006.238.07:45:39.63#ibcon#read 4, iclass 32, count 0 2006.238.07:45:39.63#ibcon#about to read 5, iclass 32, count 0 2006.238.07:45:39.63#ibcon#read 5, iclass 32, count 0 2006.238.07:45:39.63#ibcon#about to read 6, iclass 32, count 0 2006.238.07:45:39.63#ibcon#read 6, iclass 32, count 0 2006.238.07:45:39.63#ibcon#end of sib2, iclass 32, count 0 2006.238.07:45:39.63#ibcon#*mode == 0, iclass 32, count 0 2006.238.07:45:39.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.07:45:39.63#ibcon#[25=USB\r\n] 2006.238.07:45:39.63#ibcon#*before write, iclass 32, count 0 2006.238.07:45:39.63#ibcon#enter sib2, iclass 32, count 0 2006.238.07:45:39.63#ibcon#flushed, iclass 32, count 0 2006.238.07:45:39.63#ibcon#about to write, iclass 32, count 0 2006.238.07:45:39.63#ibcon#wrote, iclass 32, count 0 2006.238.07:45:39.63#ibcon#about to read 3, iclass 32, count 0 2006.238.07:45:39.66#ibcon#read 3, iclass 32, count 0 2006.238.07:45:39.66#ibcon#about to read 4, iclass 32, count 0 2006.238.07:45:39.66#ibcon#read 4, iclass 32, count 0 2006.238.07:45:39.66#ibcon#about to read 5, iclass 32, count 0 2006.238.07:45:39.66#ibcon#read 5, iclass 32, count 0 2006.238.07:45:39.66#ibcon#about to read 6, iclass 32, count 0 2006.238.07:45:39.66#ibcon#read 6, iclass 32, count 0 2006.238.07:45:39.66#ibcon#end of sib2, iclass 32, count 0 2006.238.07:45:39.66#ibcon#*after write, iclass 32, count 0 2006.238.07:45:39.66#ibcon#*before return 0, iclass 32, count 0 2006.238.07:45:39.66#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:45:39.66#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:45:39.66#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.07:45:39.66#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.07:45:39.66$vc4f8/valo=6,772.99 2006.238.07:45:39.66#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.238.07:45:39.66#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.238.07:45:39.66#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:39.66#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:45:39.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:45:39.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:45:39.66#ibcon#enter wrdev, iclass 34, count 0 2006.238.07:45:39.66#ibcon#first serial, iclass 34, count 0 2006.238.07:45:39.66#ibcon#enter sib2, iclass 34, count 0 2006.238.07:45:39.66#ibcon#flushed, iclass 34, count 0 2006.238.07:45:39.66#ibcon#about to write, iclass 34, count 0 2006.238.07:45:39.66#ibcon#wrote, iclass 34, count 0 2006.238.07:45:39.66#ibcon#about to read 3, iclass 34, count 0 2006.238.07:45:39.68#ibcon#read 3, iclass 34, count 0 2006.238.07:45:39.68#ibcon#about to read 4, iclass 34, count 0 2006.238.07:45:39.68#ibcon#read 4, iclass 34, count 0 2006.238.07:45:39.68#ibcon#about to read 5, iclass 34, count 0 2006.238.07:45:39.68#ibcon#read 5, iclass 34, count 0 2006.238.07:45:39.68#ibcon#about to read 6, iclass 34, count 0 2006.238.07:45:39.68#ibcon#read 6, iclass 34, count 0 2006.238.07:45:39.68#ibcon#end of sib2, iclass 34, count 0 2006.238.07:45:39.68#ibcon#*mode == 0, iclass 34, count 0 2006.238.07:45:39.68#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.07:45:39.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:45:39.68#ibcon#*before write, iclass 34, count 0 2006.238.07:45:39.68#ibcon#enter sib2, iclass 34, count 0 2006.238.07:45:39.68#ibcon#flushed, iclass 34, count 0 2006.238.07:45:39.68#ibcon#about to write, iclass 34, count 0 2006.238.07:45:39.68#ibcon#wrote, iclass 34, count 0 2006.238.07:45:39.68#ibcon#about to read 3, iclass 34, count 0 2006.238.07:45:39.72#ibcon#read 3, iclass 34, count 0 2006.238.07:45:39.72#ibcon#about to read 4, iclass 34, count 0 2006.238.07:45:39.72#ibcon#read 4, iclass 34, count 0 2006.238.07:45:39.72#ibcon#about to read 5, iclass 34, count 0 2006.238.07:45:39.72#ibcon#read 5, iclass 34, count 0 2006.238.07:45:39.72#ibcon#about to read 6, iclass 34, count 0 2006.238.07:45:39.72#ibcon#read 6, iclass 34, count 0 2006.238.07:45:39.72#ibcon#end of sib2, iclass 34, count 0 2006.238.07:45:39.72#ibcon#*after write, iclass 34, count 0 2006.238.07:45:39.72#ibcon#*before return 0, iclass 34, count 0 2006.238.07:45:39.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:45:39.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:45:39.72#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.07:45:39.72#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.07:45:39.72$vc4f8/va=6,7 2006.238.07:45:39.72#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.07:45:39.72#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.07:45:39.72#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:39.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:45:39.74#abcon#<5=/05 2.4 4.1 25.31 881012.2\r\n> 2006.238.07:45:39.76#abcon#{5=INTERFACE CLEAR} 2006.238.07:45:39.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:45:39.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:45:39.78#ibcon#enter wrdev, iclass 37, count 2 2006.238.07:45:39.78#ibcon#first serial, iclass 37, count 2 2006.238.07:45:39.78#ibcon#enter sib2, iclass 37, count 2 2006.238.07:45:39.78#ibcon#flushed, iclass 37, count 2 2006.238.07:45:39.78#ibcon#about to write, iclass 37, count 2 2006.238.07:45:39.78#ibcon#wrote, iclass 37, count 2 2006.238.07:45:39.78#ibcon#about to read 3, iclass 37, count 2 2006.238.07:45:39.80#ibcon#read 3, iclass 37, count 2 2006.238.07:45:39.80#ibcon#about to read 4, iclass 37, count 2 2006.238.07:45:39.80#ibcon#read 4, iclass 37, count 2 2006.238.07:45:39.80#ibcon#about to read 5, iclass 37, count 2 2006.238.07:45:39.80#ibcon#read 5, iclass 37, count 2 2006.238.07:45:39.80#ibcon#about to read 6, iclass 37, count 2 2006.238.07:45:39.80#ibcon#read 6, iclass 37, count 2 2006.238.07:45:39.80#ibcon#end of sib2, iclass 37, count 2 2006.238.07:45:39.80#ibcon#*mode == 0, iclass 37, count 2 2006.238.07:45:39.80#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.07:45:39.80#ibcon#[25=AT06-07\r\n] 2006.238.07:45:39.80#ibcon#*before write, iclass 37, count 2 2006.238.07:45:39.80#ibcon#enter sib2, iclass 37, count 2 2006.238.07:45:39.80#ibcon#flushed, iclass 37, count 2 2006.238.07:45:39.80#ibcon#about to write, iclass 37, count 2 2006.238.07:45:39.80#ibcon#wrote, iclass 37, count 2 2006.238.07:45:39.80#ibcon#about to read 3, iclass 37, count 2 2006.238.07:45:39.82#abcon#[5=S1D000X0/0*\r\n] 2006.238.07:45:39.83#ibcon#read 3, iclass 37, count 2 2006.238.07:45:39.83#ibcon#about to read 4, iclass 37, count 2 2006.238.07:45:39.83#ibcon#read 4, iclass 37, count 2 2006.238.07:45:39.83#ibcon#about to read 5, iclass 37, count 2 2006.238.07:45:39.83#ibcon#read 5, iclass 37, count 2 2006.238.07:45:39.83#ibcon#about to read 6, iclass 37, count 2 2006.238.07:45:39.83#ibcon#read 6, iclass 37, count 2 2006.238.07:45:39.83#ibcon#end of sib2, iclass 37, count 2 2006.238.07:45:39.83#ibcon#*after write, iclass 37, count 2 2006.238.07:45:39.83#ibcon#*before return 0, iclass 37, count 2 2006.238.07:45:39.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:45:39.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:45:39.83#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.07:45:39.83#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:39.83#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:45:39.95#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:45:39.95#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:45:39.95#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:45:39.95#ibcon#first serial, iclass 37, count 0 2006.238.07:45:39.95#ibcon#enter sib2, iclass 37, count 0 2006.238.07:45:39.95#ibcon#flushed, iclass 37, count 0 2006.238.07:45:39.95#ibcon#about to write, iclass 37, count 0 2006.238.07:45:39.95#ibcon#wrote, iclass 37, count 0 2006.238.07:45:39.95#ibcon#about to read 3, iclass 37, count 0 2006.238.07:45:39.97#ibcon#read 3, iclass 37, count 0 2006.238.07:45:39.97#ibcon#about to read 4, iclass 37, count 0 2006.238.07:45:39.97#ibcon#read 4, iclass 37, count 0 2006.238.07:45:39.97#ibcon#about to read 5, iclass 37, count 0 2006.238.07:45:39.97#ibcon#read 5, iclass 37, count 0 2006.238.07:45:39.97#ibcon#about to read 6, iclass 37, count 0 2006.238.07:45:39.97#ibcon#read 6, iclass 37, count 0 2006.238.07:45:39.97#ibcon#end of sib2, iclass 37, count 0 2006.238.07:45:39.97#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:45:39.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:45:39.97#ibcon#[25=USB\r\n] 2006.238.07:45:39.97#ibcon#*before write, iclass 37, count 0 2006.238.07:45:39.97#ibcon#enter sib2, iclass 37, count 0 2006.238.07:45:39.97#ibcon#flushed, iclass 37, count 0 2006.238.07:45:39.97#ibcon#about to write, iclass 37, count 0 2006.238.07:45:39.97#ibcon#wrote, iclass 37, count 0 2006.238.07:45:39.97#ibcon#about to read 3, iclass 37, count 0 2006.238.07:45:40.00#ibcon#read 3, iclass 37, count 0 2006.238.07:45:40.00#ibcon#about to read 4, iclass 37, count 0 2006.238.07:45:40.00#ibcon#read 4, iclass 37, count 0 2006.238.07:45:40.00#ibcon#about to read 5, iclass 37, count 0 2006.238.07:45:40.00#ibcon#read 5, iclass 37, count 0 2006.238.07:45:40.00#ibcon#about to read 6, iclass 37, count 0 2006.238.07:45:40.00#ibcon#read 6, iclass 37, count 0 2006.238.07:45:40.00#ibcon#end of sib2, iclass 37, count 0 2006.238.07:45:40.00#ibcon#*after write, iclass 37, count 0 2006.238.07:45:40.00#ibcon#*before return 0, iclass 37, count 0 2006.238.07:45:40.00#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:45:40.00#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:45:40.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:45:40.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:45:40.00$vc4f8/valo=7,832.99 2006.238.07:45:40.00#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.07:45:40.00#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.07:45:40.00#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:40.00#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:45:40.00#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:45:40.00#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:45:40.00#ibcon#enter wrdev, iclass 4, count 0 2006.238.07:45:40.00#ibcon#first serial, iclass 4, count 0 2006.238.07:45:40.00#ibcon#enter sib2, iclass 4, count 0 2006.238.07:45:40.00#ibcon#flushed, iclass 4, count 0 2006.238.07:45:40.00#ibcon#about to write, iclass 4, count 0 2006.238.07:45:40.00#ibcon#wrote, iclass 4, count 0 2006.238.07:45:40.00#ibcon#about to read 3, iclass 4, count 0 2006.238.07:45:40.02#ibcon#read 3, iclass 4, count 0 2006.238.07:45:40.02#ibcon#about to read 4, iclass 4, count 0 2006.238.07:45:40.02#ibcon#read 4, iclass 4, count 0 2006.238.07:45:40.02#ibcon#about to read 5, iclass 4, count 0 2006.238.07:45:40.02#ibcon#read 5, iclass 4, count 0 2006.238.07:45:40.02#ibcon#about to read 6, iclass 4, count 0 2006.238.07:45:40.02#ibcon#read 6, iclass 4, count 0 2006.238.07:45:40.02#ibcon#end of sib2, iclass 4, count 0 2006.238.07:45:40.02#ibcon#*mode == 0, iclass 4, count 0 2006.238.07:45:40.02#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.07:45:40.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:45:40.02#ibcon#*before write, iclass 4, count 0 2006.238.07:45:40.02#ibcon#enter sib2, iclass 4, count 0 2006.238.07:45:40.02#ibcon#flushed, iclass 4, count 0 2006.238.07:45:40.02#ibcon#about to write, iclass 4, count 0 2006.238.07:45:40.02#ibcon#wrote, iclass 4, count 0 2006.238.07:45:40.02#ibcon#about to read 3, iclass 4, count 0 2006.238.07:45:40.06#ibcon#read 3, iclass 4, count 0 2006.238.07:45:40.06#ibcon#about to read 4, iclass 4, count 0 2006.238.07:45:40.06#ibcon#read 4, iclass 4, count 0 2006.238.07:45:40.06#ibcon#about to read 5, iclass 4, count 0 2006.238.07:45:40.06#ibcon#read 5, iclass 4, count 0 2006.238.07:45:40.06#ibcon#about to read 6, iclass 4, count 0 2006.238.07:45:40.06#ibcon#read 6, iclass 4, count 0 2006.238.07:45:40.06#ibcon#end of sib2, iclass 4, count 0 2006.238.07:45:40.06#ibcon#*after write, iclass 4, count 0 2006.238.07:45:40.06#ibcon#*before return 0, iclass 4, count 0 2006.238.07:45:40.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:45:40.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:45:40.06#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.07:45:40.06#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.07:45:40.06$vc4f8/va=7,7 2006.238.07:45:40.06#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.07:45:40.06#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.07:45:40.06#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:40.06#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:45:40.12#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:45:40.12#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:45:40.12#ibcon#enter wrdev, iclass 6, count 2 2006.238.07:45:40.12#ibcon#first serial, iclass 6, count 2 2006.238.07:45:40.12#ibcon#enter sib2, iclass 6, count 2 2006.238.07:45:40.12#ibcon#flushed, iclass 6, count 2 2006.238.07:45:40.12#ibcon#about to write, iclass 6, count 2 2006.238.07:45:40.12#ibcon#wrote, iclass 6, count 2 2006.238.07:45:40.12#ibcon#about to read 3, iclass 6, count 2 2006.238.07:45:40.14#ibcon#read 3, iclass 6, count 2 2006.238.07:45:40.14#ibcon#about to read 4, iclass 6, count 2 2006.238.07:45:40.14#ibcon#read 4, iclass 6, count 2 2006.238.07:45:40.14#ibcon#about to read 5, iclass 6, count 2 2006.238.07:45:40.14#ibcon#read 5, iclass 6, count 2 2006.238.07:45:40.14#ibcon#about to read 6, iclass 6, count 2 2006.238.07:45:40.14#ibcon#read 6, iclass 6, count 2 2006.238.07:45:40.14#ibcon#end of sib2, iclass 6, count 2 2006.238.07:45:40.14#ibcon#*mode == 0, iclass 6, count 2 2006.238.07:45:40.14#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.07:45:40.14#ibcon#[25=AT07-07\r\n] 2006.238.07:45:40.14#ibcon#*before write, iclass 6, count 2 2006.238.07:45:40.14#ibcon#enter sib2, iclass 6, count 2 2006.238.07:45:40.14#ibcon#flushed, iclass 6, count 2 2006.238.07:45:40.14#ibcon#about to write, iclass 6, count 2 2006.238.07:45:40.14#ibcon#wrote, iclass 6, count 2 2006.238.07:45:40.14#ibcon#about to read 3, iclass 6, count 2 2006.238.07:45:40.17#ibcon#read 3, iclass 6, count 2 2006.238.07:45:40.17#ibcon#about to read 4, iclass 6, count 2 2006.238.07:45:40.17#ibcon#read 4, iclass 6, count 2 2006.238.07:45:40.17#ibcon#about to read 5, iclass 6, count 2 2006.238.07:45:40.17#ibcon#read 5, iclass 6, count 2 2006.238.07:45:40.17#ibcon#about to read 6, iclass 6, count 2 2006.238.07:45:40.17#ibcon#read 6, iclass 6, count 2 2006.238.07:45:40.17#ibcon#end of sib2, iclass 6, count 2 2006.238.07:45:40.17#ibcon#*after write, iclass 6, count 2 2006.238.07:45:40.17#ibcon#*before return 0, iclass 6, count 2 2006.238.07:45:40.17#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:45:40.17#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:45:40.17#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.07:45:40.17#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:40.17#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:45:40.29#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:45:40.29#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:45:40.29#ibcon#enter wrdev, iclass 6, count 0 2006.238.07:45:40.29#ibcon#first serial, iclass 6, count 0 2006.238.07:45:40.29#ibcon#enter sib2, iclass 6, count 0 2006.238.07:45:40.29#ibcon#flushed, iclass 6, count 0 2006.238.07:45:40.29#ibcon#about to write, iclass 6, count 0 2006.238.07:45:40.29#ibcon#wrote, iclass 6, count 0 2006.238.07:45:40.29#ibcon#about to read 3, iclass 6, count 0 2006.238.07:45:40.31#ibcon#read 3, iclass 6, count 0 2006.238.07:45:40.31#ibcon#about to read 4, iclass 6, count 0 2006.238.07:45:40.31#ibcon#read 4, iclass 6, count 0 2006.238.07:45:40.31#ibcon#about to read 5, iclass 6, count 0 2006.238.07:45:40.31#ibcon#read 5, iclass 6, count 0 2006.238.07:45:40.31#ibcon#about to read 6, iclass 6, count 0 2006.238.07:45:40.31#ibcon#read 6, iclass 6, count 0 2006.238.07:45:40.31#ibcon#end of sib2, iclass 6, count 0 2006.238.07:45:40.31#ibcon#*mode == 0, iclass 6, count 0 2006.238.07:45:40.31#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.07:45:40.31#ibcon#[25=USB\r\n] 2006.238.07:45:40.31#ibcon#*before write, iclass 6, count 0 2006.238.07:45:40.31#ibcon#enter sib2, iclass 6, count 0 2006.238.07:45:40.31#ibcon#flushed, iclass 6, count 0 2006.238.07:45:40.31#ibcon#about to write, iclass 6, count 0 2006.238.07:45:40.31#ibcon#wrote, iclass 6, count 0 2006.238.07:45:40.31#ibcon#about to read 3, iclass 6, count 0 2006.238.07:45:40.34#ibcon#read 3, iclass 6, count 0 2006.238.07:45:40.34#ibcon#about to read 4, iclass 6, count 0 2006.238.07:45:40.34#ibcon#read 4, iclass 6, count 0 2006.238.07:45:40.34#ibcon#about to read 5, iclass 6, count 0 2006.238.07:45:40.34#ibcon#read 5, iclass 6, count 0 2006.238.07:45:40.34#ibcon#about to read 6, iclass 6, count 0 2006.238.07:45:40.34#ibcon#read 6, iclass 6, count 0 2006.238.07:45:40.34#ibcon#end of sib2, iclass 6, count 0 2006.238.07:45:40.34#ibcon#*after write, iclass 6, count 0 2006.238.07:45:40.34#ibcon#*before return 0, iclass 6, count 0 2006.238.07:45:40.34#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:45:40.34#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:45:40.34#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.07:45:40.34#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.07:45:40.34$vc4f8/valo=8,852.99 2006.238.07:45:40.34#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.07:45:40.34#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.07:45:40.34#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:40.34#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:45:40.34#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:45:40.34#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:45:40.34#ibcon#enter wrdev, iclass 10, count 0 2006.238.07:45:40.34#ibcon#first serial, iclass 10, count 0 2006.238.07:45:40.34#ibcon#enter sib2, iclass 10, count 0 2006.238.07:45:40.34#ibcon#flushed, iclass 10, count 0 2006.238.07:45:40.34#ibcon#about to write, iclass 10, count 0 2006.238.07:45:40.34#ibcon#wrote, iclass 10, count 0 2006.238.07:45:40.34#ibcon#about to read 3, iclass 10, count 0 2006.238.07:45:40.36#ibcon#read 3, iclass 10, count 0 2006.238.07:45:40.36#ibcon#about to read 4, iclass 10, count 0 2006.238.07:45:40.36#ibcon#read 4, iclass 10, count 0 2006.238.07:45:40.36#ibcon#about to read 5, iclass 10, count 0 2006.238.07:45:40.36#ibcon#read 5, iclass 10, count 0 2006.238.07:45:40.36#ibcon#about to read 6, iclass 10, count 0 2006.238.07:45:40.36#ibcon#read 6, iclass 10, count 0 2006.238.07:45:40.36#ibcon#end of sib2, iclass 10, count 0 2006.238.07:45:40.36#ibcon#*mode == 0, iclass 10, count 0 2006.238.07:45:40.36#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.07:45:40.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:45:40.36#ibcon#*before write, iclass 10, count 0 2006.238.07:45:40.36#ibcon#enter sib2, iclass 10, count 0 2006.238.07:45:40.36#ibcon#flushed, iclass 10, count 0 2006.238.07:45:40.36#ibcon#about to write, iclass 10, count 0 2006.238.07:45:40.36#ibcon#wrote, iclass 10, count 0 2006.238.07:45:40.36#ibcon#about to read 3, iclass 10, count 0 2006.238.07:45:40.40#ibcon#read 3, iclass 10, count 0 2006.238.07:45:40.40#ibcon#about to read 4, iclass 10, count 0 2006.238.07:45:40.40#ibcon#read 4, iclass 10, count 0 2006.238.07:45:40.40#ibcon#about to read 5, iclass 10, count 0 2006.238.07:45:40.40#ibcon#read 5, iclass 10, count 0 2006.238.07:45:40.40#ibcon#about to read 6, iclass 10, count 0 2006.238.07:45:40.40#ibcon#read 6, iclass 10, count 0 2006.238.07:45:40.40#ibcon#end of sib2, iclass 10, count 0 2006.238.07:45:40.40#ibcon#*after write, iclass 10, count 0 2006.238.07:45:40.40#ibcon#*before return 0, iclass 10, count 0 2006.238.07:45:40.40#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:45:40.40#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:45:40.40#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.07:45:40.40#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.07:45:40.40$vc4f8/va=8,7 2006.238.07:45:40.40#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.238.07:45:40.40#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.238.07:45:40.40#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:40.40#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:45:40.46#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:45:40.46#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:45:40.46#ibcon#enter wrdev, iclass 12, count 2 2006.238.07:45:40.46#ibcon#first serial, iclass 12, count 2 2006.238.07:45:40.46#ibcon#enter sib2, iclass 12, count 2 2006.238.07:45:40.46#ibcon#flushed, iclass 12, count 2 2006.238.07:45:40.46#ibcon#about to write, iclass 12, count 2 2006.238.07:45:40.46#ibcon#wrote, iclass 12, count 2 2006.238.07:45:40.46#ibcon#about to read 3, iclass 12, count 2 2006.238.07:45:40.48#ibcon#read 3, iclass 12, count 2 2006.238.07:45:40.48#ibcon#about to read 4, iclass 12, count 2 2006.238.07:45:40.48#ibcon#read 4, iclass 12, count 2 2006.238.07:45:40.48#ibcon#about to read 5, iclass 12, count 2 2006.238.07:45:40.48#ibcon#read 5, iclass 12, count 2 2006.238.07:45:40.48#ibcon#about to read 6, iclass 12, count 2 2006.238.07:45:40.48#ibcon#read 6, iclass 12, count 2 2006.238.07:45:40.48#ibcon#end of sib2, iclass 12, count 2 2006.238.07:45:40.48#ibcon#*mode == 0, iclass 12, count 2 2006.238.07:45:40.48#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.238.07:45:40.48#ibcon#[25=AT08-07\r\n] 2006.238.07:45:40.48#ibcon#*before write, iclass 12, count 2 2006.238.07:45:40.48#ibcon#enter sib2, iclass 12, count 2 2006.238.07:45:40.48#ibcon#flushed, iclass 12, count 2 2006.238.07:45:40.48#ibcon#about to write, iclass 12, count 2 2006.238.07:45:40.48#ibcon#wrote, iclass 12, count 2 2006.238.07:45:40.48#ibcon#about to read 3, iclass 12, count 2 2006.238.07:45:40.51#ibcon#read 3, iclass 12, count 2 2006.238.07:45:40.51#ibcon#about to read 4, iclass 12, count 2 2006.238.07:45:40.51#ibcon#read 4, iclass 12, count 2 2006.238.07:45:40.51#ibcon#about to read 5, iclass 12, count 2 2006.238.07:45:40.51#ibcon#read 5, iclass 12, count 2 2006.238.07:45:40.51#ibcon#about to read 6, iclass 12, count 2 2006.238.07:45:40.51#ibcon#read 6, iclass 12, count 2 2006.238.07:45:40.51#ibcon#end of sib2, iclass 12, count 2 2006.238.07:45:40.51#ibcon#*after write, iclass 12, count 2 2006.238.07:45:40.51#ibcon#*before return 0, iclass 12, count 2 2006.238.07:45:40.51#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:45:40.51#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:45:40.51#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.238.07:45:40.51#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:40.51#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:45:40.63#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:45:40.63#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:45:40.63#ibcon#enter wrdev, iclass 12, count 0 2006.238.07:45:40.63#ibcon#first serial, iclass 12, count 0 2006.238.07:45:40.63#ibcon#enter sib2, iclass 12, count 0 2006.238.07:45:40.63#ibcon#flushed, iclass 12, count 0 2006.238.07:45:40.63#ibcon#about to write, iclass 12, count 0 2006.238.07:45:40.63#ibcon#wrote, iclass 12, count 0 2006.238.07:45:40.63#ibcon#about to read 3, iclass 12, count 0 2006.238.07:45:40.65#ibcon#read 3, iclass 12, count 0 2006.238.07:45:40.65#ibcon#about to read 4, iclass 12, count 0 2006.238.07:45:40.65#ibcon#read 4, iclass 12, count 0 2006.238.07:45:40.65#ibcon#about to read 5, iclass 12, count 0 2006.238.07:45:40.65#ibcon#read 5, iclass 12, count 0 2006.238.07:45:40.65#ibcon#about to read 6, iclass 12, count 0 2006.238.07:45:40.65#ibcon#read 6, iclass 12, count 0 2006.238.07:45:40.65#ibcon#end of sib2, iclass 12, count 0 2006.238.07:45:40.65#ibcon#*mode == 0, iclass 12, count 0 2006.238.07:45:40.65#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.07:45:40.65#ibcon#[25=USB\r\n] 2006.238.07:45:40.65#ibcon#*before write, iclass 12, count 0 2006.238.07:45:40.65#ibcon#enter sib2, iclass 12, count 0 2006.238.07:45:40.65#ibcon#flushed, iclass 12, count 0 2006.238.07:45:40.65#ibcon#about to write, iclass 12, count 0 2006.238.07:45:40.65#ibcon#wrote, iclass 12, count 0 2006.238.07:45:40.65#ibcon#about to read 3, iclass 12, count 0 2006.238.07:45:40.68#ibcon#read 3, iclass 12, count 0 2006.238.07:45:40.68#ibcon#about to read 4, iclass 12, count 0 2006.238.07:45:40.68#ibcon#read 4, iclass 12, count 0 2006.238.07:45:40.68#ibcon#about to read 5, iclass 12, count 0 2006.238.07:45:40.68#ibcon#read 5, iclass 12, count 0 2006.238.07:45:40.68#ibcon#about to read 6, iclass 12, count 0 2006.238.07:45:40.68#ibcon#read 6, iclass 12, count 0 2006.238.07:45:40.68#ibcon#end of sib2, iclass 12, count 0 2006.238.07:45:40.68#ibcon#*after write, iclass 12, count 0 2006.238.07:45:40.68#ibcon#*before return 0, iclass 12, count 0 2006.238.07:45:40.68#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:45:40.68#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:45:40.68#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.07:45:40.68#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.07:45:40.68$vc4f8/vblo=1,632.99 2006.238.07:45:40.68#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.07:45:40.68#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.07:45:40.68#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:40.68#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:45:40.68#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:45:40.68#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:45:40.68#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:45:40.68#ibcon#first serial, iclass 14, count 0 2006.238.07:45:40.68#ibcon#enter sib2, iclass 14, count 0 2006.238.07:45:40.68#ibcon#flushed, iclass 14, count 0 2006.238.07:45:40.68#ibcon#about to write, iclass 14, count 0 2006.238.07:45:40.68#ibcon#wrote, iclass 14, count 0 2006.238.07:45:40.68#ibcon#about to read 3, iclass 14, count 0 2006.238.07:45:40.70#ibcon#read 3, iclass 14, count 0 2006.238.07:45:40.70#ibcon#about to read 4, iclass 14, count 0 2006.238.07:45:40.70#ibcon#read 4, iclass 14, count 0 2006.238.07:45:40.70#ibcon#about to read 5, iclass 14, count 0 2006.238.07:45:40.70#ibcon#read 5, iclass 14, count 0 2006.238.07:45:40.70#ibcon#about to read 6, iclass 14, count 0 2006.238.07:45:40.70#ibcon#read 6, iclass 14, count 0 2006.238.07:45:40.70#ibcon#end of sib2, iclass 14, count 0 2006.238.07:45:40.70#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:45:40.70#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:45:40.70#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:45:40.70#ibcon#*before write, iclass 14, count 0 2006.238.07:45:40.70#ibcon#enter sib2, iclass 14, count 0 2006.238.07:45:40.70#ibcon#flushed, iclass 14, count 0 2006.238.07:45:40.70#ibcon#about to write, iclass 14, count 0 2006.238.07:45:40.70#ibcon#wrote, iclass 14, count 0 2006.238.07:45:40.70#ibcon#about to read 3, iclass 14, count 0 2006.238.07:45:40.74#ibcon#read 3, iclass 14, count 0 2006.238.07:45:40.74#ibcon#about to read 4, iclass 14, count 0 2006.238.07:45:40.74#ibcon#read 4, iclass 14, count 0 2006.238.07:45:40.74#ibcon#about to read 5, iclass 14, count 0 2006.238.07:45:40.74#ibcon#read 5, iclass 14, count 0 2006.238.07:45:40.74#ibcon#about to read 6, iclass 14, count 0 2006.238.07:45:40.74#ibcon#read 6, iclass 14, count 0 2006.238.07:45:40.74#ibcon#end of sib2, iclass 14, count 0 2006.238.07:45:40.74#ibcon#*after write, iclass 14, count 0 2006.238.07:45:40.74#ibcon#*before return 0, iclass 14, count 0 2006.238.07:45:40.74#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:45:40.74#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:45:40.74#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:45:40.74#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:45:40.74$vc4f8/vb=1,4 2006.238.07:45:40.74#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.238.07:45:40.74#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.238.07:45:40.74#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:40.74#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:45:40.74#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:45:40.74#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:45:40.74#ibcon#enter wrdev, iclass 16, count 2 2006.238.07:45:40.74#ibcon#first serial, iclass 16, count 2 2006.238.07:45:40.74#ibcon#enter sib2, iclass 16, count 2 2006.238.07:45:40.74#ibcon#flushed, iclass 16, count 2 2006.238.07:45:40.74#ibcon#about to write, iclass 16, count 2 2006.238.07:45:40.74#ibcon#wrote, iclass 16, count 2 2006.238.07:45:40.74#ibcon#about to read 3, iclass 16, count 2 2006.238.07:45:40.76#ibcon#read 3, iclass 16, count 2 2006.238.07:45:40.76#ibcon#about to read 4, iclass 16, count 2 2006.238.07:45:40.76#ibcon#read 4, iclass 16, count 2 2006.238.07:45:40.76#ibcon#about to read 5, iclass 16, count 2 2006.238.07:45:40.76#ibcon#read 5, iclass 16, count 2 2006.238.07:45:40.76#ibcon#about to read 6, iclass 16, count 2 2006.238.07:45:40.76#ibcon#read 6, iclass 16, count 2 2006.238.07:45:40.76#ibcon#end of sib2, iclass 16, count 2 2006.238.07:45:40.76#ibcon#*mode == 0, iclass 16, count 2 2006.238.07:45:40.76#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.238.07:45:40.76#ibcon#[27=AT01-04\r\n] 2006.238.07:45:40.76#ibcon#*before write, iclass 16, count 2 2006.238.07:45:40.76#ibcon#enter sib2, iclass 16, count 2 2006.238.07:45:40.76#ibcon#flushed, iclass 16, count 2 2006.238.07:45:40.76#ibcon#about to write, iclass 16, count 2 2006.238.07:45:40.76#ibcon#wrote, iclass 16, count 2 2006.238.07:45:40.76#ibcon#about to read 3, iclass 16, count 2 2006.238.07:45:40.79#ibcon#read 3, iclass 16, count 2 2006.238.07:45:40.79#ibcon#about to read 4, iclass 16, count 2 2006.238.07:45:40.79#ibcon#read 4, iclass 16, count 2 2006.238.07:45:40.79#ibcon#about to read 5, iclass 16, count 2 2006.238.07:45:40.79#ibcon#read 5, iclass 16, count 2 2006.238.07:45:40.79#ibcon#about to read 6, iclass 16, count 2 2006.238.07:45:40.79#ibcon#read 6, iclass 16, count 2 2006.238.07:45:40.79#ibcon#end of sib2, iclass 16, count 2 2006.238.07:45:40.79#ibcon#*after write, iclass 16, count 2 2006.238.07:45:40.79#ibcon#*before return 0, iclass 16, count 2 2006.238.07:45:40.79#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:45:40.79#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:45:40.79#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.238.07:45:40.79#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:40.79#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:45:40.91#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:45:40.91#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:45:40.91#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:45:40.91#ibcon#first serial, iclass 16, count 0 2006.238.07:45:40.91#ibcon#enter sib2, iclass 16, count 0 2006.238.07:45:40.91#ibcon#flushed, iclass 16, count 0 2006.238.07:45:40.91#ibcon#about to write, iclass 16, count 0 2006.238.07:45:40.91#ibcon#wrote, iclass 16, count 0 2006.238.07:45:40.91#ibcon#about to read 3, iclass 16, count 0 2006.238.07:45:40.93#ibcon#read 3, iclass 16, count 0 2006.238.07:45:40.93#ibcon#about to read 4, iclass 16, count 0 2006.238.07:45:40.93#ibcon#read 4, iclass 16, count 0 2006.238.07:45:40.93#ibcon#about to read 5, iclass 16, count 0 2006.238.07:45:40.93#ibcon#read 5, iclass 16, count 0 2006.238.07:45:40.93#ibcon#about to read 6, iclass 16, count 0 2006.238.07:45:40.93#ibcon#read 6, iclass 16, count 0 2006.238.07:45:40.93#ibcon#end of sib2, iclass 16, count 0 2006.238.07:45:40.93#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:45:40.93#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:45:40.93#ibcon#[27=USB\r\n] 2006.238.07:45:40.93#ibcon#*before write, iclass 16, count 0 2006.238.07:45:40.93#ibcon#enter sib2, iclass 16, count 0 2006.238.07:45:40.93#ibcon#flushed, iclass 16, count 0 2006.238.07:45:40.93#ibcon#about to write, iclass 16, count 0 2006.238.07:45:40.93#ibcon#wrote, iclass 16, count 0 2006.238.07:45:40.93#ibcon#about to read 3, iclass 16, count 0 2006.238.07:45:40.96#ibcon#read 3, iclass 16, count 0 2006.238.07:45:40.96#ibcon#about to read 4, iclass 16, count 0 2006.238.07:45:40.96#ibcon#read 4, iclass 16, count 0 2006.238.07:45:40.96#ibcon#about to read 5, iclass 16, count 0 2006.238.07:45:40.96#ibcon#read 5, iclass 16, count 0 2006.238.07:45:40.96#ibcon#about to read 6, iclass 16, count 0 2006.238.07:45:40.96#ibcon#read 6, iclass 16, count 0 2006.238.07:45:40.96#ibcon#end of sib2, iclass 16, count 0 2006.238.07:45:40.96#ibcon#*after write, iclass 16, count 0 2006.238.07:45:40.96#ibcon#*before return 0, iclass 16, count 0 2006.238.07:45:40.96#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:45:40.96#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:45:40.96#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:45:40.96#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:45:40.96$vc4f8/vblo=2,640.99 2006.238.07:45:40.96#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.07:45:40.96#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.07:45:40.96#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:40.96#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:45:40.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:45:40.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:45:40.96#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:45:40.96#ibcon#first serial, iclass 18, count 0 2006.238.07:45:40.96#ibcon#enter sib2, iclass 18, count 0 2006.238.07:45:40.96#ibcon#flushed, iclass 18, count 0 2006.238.07:45:40.96#ibcon#about to write, iclass 18, count 0 2006.238.07:45:40.96#ibcon#wrote, iclass 18, count 0 2006.238.07:45:40.96#ibcon#about to read 3, iclass 18, count 0 2006.238.07:45:40.98#ibcon#read 3, iclass 18, count 0 2006.238.07:45:40.98#ibcon#about to read 4, iclass 18, count 0 2006.238.07:45:40.98#ibcon#read 4, iclass 18, count 0 2006.238.07:45:40.98#ibcon#about to read 5, iclass 18, count 0 2006.238.07:45:40.98#ibcon#read 5, iclass 18, count 0 2006.238.07:45:40.98#ibcon#about to read 6, iclass 18, count 0 2006.238.07:45:40.98#ibcon#read 6, iclass 18, count 0 2006.238.07:45:40.98#ibcon#end of sib2, iclass 18, count 0 2006.238.07:45:40.98#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:45:40.98#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:45:40.98#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:45:40.98#ibcon#*before write, iclass 18, count 0 2006.238.07:45:40.98#ibcon#enter sib2, iclass 18, count 0 2006.238.07:45:40.98#ibcon#flushed, iclass 18, count 0 2006.238.07:45:40.98#ibcon#about to write, iclass 18, count 0 2006.238.07:45:40.98#ibcon#wrote, iclass 18, count 0 2006.238.07:45:40.98#ibcon#about to read 3, iclass 18, count 0 2006.238.07:45:41.02#ibcon#read 3, iclass 18, count 0 2006.238.07:45:41.02#ibcon#about to read 4, iclass 18, count 0 2006.238.07:45:41.02#ibcon#read 4, iclass 18, count 0 2006.238.07:45:41.02#ibcon#about to read 5, iclass 18, count 0 2006.238.07:45:41.02#ibcon#read 5, iclass 18, count 0 2006.238.07:45:41.02#ibcon#about to read 6, iclass 18, count 0 2006.238.07:45:41.02#ibcon#read 6, iclass 18, count 0 2006.238.07:45:41.02#ibcon#end of sib2, iclass 18, count 0 2006.238.07:45:41.02#ibcon#*after write, iclass 18, count 0 2006.238.07:45:41.02#ibcon#*before return 0, iclass 18, count 0 2006.238.07:45:41.02#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:45:41.02#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:45:41.02#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:45:41.02#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:45:41.02$vc4f8/vb=2,4 2006.238.07:45:41.02#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.238.07:45:41.02#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.238.07:45:41.02#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:41.02#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:45:41.08#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:45:41.08#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:45:41.08#ibcon#enter wrdev, iclass 20, count 2 2006.238.07:45:41.08#ibcon#first serial, iclass 20, count 2 2006.238.07:45:41.08#ibcon#enter sib2, iclass 20, count 2 2006.238.07:45:41.08#ibcon#flushed, iclass 20, count 2 2006.238.07:45:41.08#ibcon#about to write, iclass 20, count 2 2006.238.07:45:41.08#ibcon#wrote, iclass 20, count 2 2006.238.07:45:41.08#ibcon#about to read 3, iclass 20, count 2 2006.238.07:45:41.10#ibcon#read 3, iclass 20, count 2 2006.238.07:45:41.10#ibcon#about to read 4, iclass 20, count 2 2006.238.07:45:41.10#ibcon#read 4, iclass 20, count 2 2006.238.07:45:41.10#ibcon#about to read 5, iclass 20, count 2 2006.238.07:45:41.10#ibcon#read 5, iclass 20, count 2 2006.238.07:45:41.10#ibcon#about to read 6, iclass 20, count 2 2006.238.07:45:41.10#ibcon#read 6, iclass 20, count 2 2006.238.07:45:41.10#ibcon#end of sib2, iclass 20, count 2 2006.238.07:45:41.10#ibcon#*mode == 0, iclass 20, count 2 2006.238.07:45:41.10#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.238.07:45:41.10#ibcon#[27=AT02-04\r\n] 2006.238.07:45:41.10#ibcon#*before write, iclass 20, count 2 2006.238.07:45:41.10#ibcon#enter sib2, iclass 20, count 2 2006.238.07:45:41.10#ibcon#flushed, iclass 20, count 2 2006.238.07:45:41.10#ibcon#about to write, iclass 20, count 2 2006.238.07:45:41.10#ibcon#wrote, iclass 20, count 2 2006.238.07:45:41.10#ibcon#about to read 3, iclass 20, count 2 2006.238.07:45:41.13#ibcon#read 3, iclass 20, count 2 2006.238.07:45:41.13#ibcon#about to read 4, iclass 20, count 2 2006.238.07:45:41.13#ibcon#read 4, iclass 20, count 2 2006.238.07:45:41.13#ibcon#about to read 5, iclass 20, count 2 2006.238.07:45:41.13#ibcon#read 5, iclass 20, count 2 2006.238.07:45:41.13#ibcon#about to read 6, iclass 20, count 2 2006.238.07:45:41.13#ibcon#read 6, iclass 20, count 2 2006.238.07:45:41.13#ibcon#end of sib2, iclass 20, count 2 2006.238.07:45:41.13#ibcon#*after write, iclass 20, count 2 2006.238.07:45:41.13#ibcon#*before return 0, iclass 20, count 2 2006.238.07:45:41.13#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:45:41.13#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:45:41.13#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.238.07:45:41.13#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:41.13#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:45:41.25#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:45:41.25#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:45:41.25#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:45:41.25#ibcon#first serial, iclass 20, count 0 2006.238.07:45:41.25#ibcon#enter sib2, iclass 20, count 0 2006.238.07:45:41.25#ibcon#flushed, iclass 20, count 0 2006.238.07:45:41.25#ibcon#about to write, iclass 20, count 0 2006.238.07:45:41.25#ibcon#wrote, iclass 20, count 0 2006.238.07:45:41.25#ibcon#about to read 3, iclass 20, count 0 2006.238.07:45:41.27#ibcon#read 3, iclass 20, count 0 2006.238.07:45:41.27#ibcon#about to read 4, iclass 20, count 0 2006.238.07:45:41.27#ibcon#read 4, iclass 20, count 0 2006.238.07:45:41.27#ibcon#about to read 5, iclass 20, count 0 2006.238.07:45:41.27#ibcon#read 5, iclass 20, count 0 2006.238.07:45:41.27#ibcon#about to read 6, iclass 20, count 0 2006.238.07:45:41.27#ibcon#read 6, iclass 20, count 0 2006.238.07:45:41.27#ibcon#end of sib2, iclass 20, count 0 2006.238.07:45:41.27#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:45:41.27#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:45:41.27#ibcon#[27=USB\r\n] 2006.238.07:45:41.27#ibcon#*before write, iclass 20, count 0 2006.238.07:45:41.27#ibcon#enter sib2, iclass 20, count 0 2006.238.07:45:41.27#ibcon#flushed, iclass 20, count 0 2006.238.07:45:41.27#ibcon#about to write, iclass 20, count 0 2006.238.07:45:41.27#ibcon#wrote, iclass 20, count 0 2006.238.07:45:41.27#ibcon#about to read 3, iclass 20, count 0 2006.238.07:45:41.30#ibcon#read 3, iclass 20, count 0 2006.238.07:45:41.30#ibcon#about to read 4, iclass 20, count 0 2006.238.07:45:41.30#ibcon#read 4, iclass 20, count 0 2006.238.07:45:41.30#ibcon#about to read 5, iclass 20, count 0 2006.238.07:45:41.30#ibcon#read 5, iclass 20, count 0 2006.238.07:45:41.30#ibcon#about to read 6, iclass 20, count 0 2006.238.07:45:41.30#ibcon#read 6, iclass 20, count 0 2006.238.07:45:41.30#ibcon#end of sib2, iclass 20, count 0 2006.238.07:45:41.30#ibcon#*after write, iclass 20, count 0 2006.238.07:45:41.30#ibcon#*before return 0, iclass 20, count 0 2006.238.07:45:41.30#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:45:41.30#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:45:41.30#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:45:41.30#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:45:41.30$vc4f8/vblo=3,656.99 2006.238.07:45:41.30#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.07:45:41.30#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.07:45:41.30#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:41.30#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:45:41.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:45:41.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:45:41.30#ibcon#enter wrdev, iclass 22, count 0 2006.238.07:45:41.30#ibcon#first serial, iclass 22, count 0 2006.238.07:45:41.30#ibcon#enter sib2, iclass 22, count 0 2006.238.07:45:41.30#ibcon#flushed, iclass 22, count 0 2006.238.07:45:41.30#ibcon#about to write, iclass 22, count 0 2006.238.07:45:41.30#ibcon#wrote, iclass 22, count 0 2006.238.07:45:41.30#ibcon#about to read 3, iclass 22, count 0 2006.238.07:45:41.32#ibcon#read 3, iclass 22, count 0 2006.238.07:45:41.32#ibcon#about to read 4, iclass 22, count 0 2006.238.07:45:41.32#ibcon#read 4, iclass 22, count 0 2006.238.07:45:41.32#ibcon#about to read 5, iclass 22, count 0 2006.238.07:45:41.32#ibcon#read 5, iclass 22, count 0 2006.238.07:45:41.32#ibcon#about to read 6, iclass 22, count 0 2006.238.07:45:41.32#ibcon#read 6, iclass 22, count 0 2006.238.07:45:41.32#ibcon#end of sib2, iclass 22, count 0 2006.238.07:45:41.32#ibcon#*mode == 0, iclass 22, count 0 2006.238.07:45:41.32#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.07:45:41.32#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:45:41.32#ibcon#*before write, iclass 22, count 0 2006.238.07:45:41.32#ibcon#enter sib2, iclass 22, count 0 2006.238.07:45:41.32#ibcon#flushed, iclass 22, count 0 2006.238.07:45:41.32#ibcon#about to write, iclass 22, count 0 2006.238.07:45:41.32#ibcon#wrote, iclass 22, count 0 2006.238.07:45:41.32#ibcon#about to read 3, iclass 22, count 0 2006.238.07:45:41.36#ibcon#read 3, iclass 22, count 0 2006.238.07:45:41.36#ibcon#about to read 4, iclass 22, count 0 2006.238.07:45:41.36#ibcon#read 4, iclass 22, count 0 2006.238.07:45:41.36#ibcon#about to read 5, iclass 22, count 0 2006.238.07:45:41.36#ibcon#read 5, iclass 22, count 0 2006.238.07:45:41.36#ibcon#about to read 6, iclass 22, count 0 2006.238.07:45:41.36#ibcon#read 6, iclass 22, count 0 2006.238.07:45:41.36#ibcon#end of sib2, iclass 22, count 0 2006.238.07:45:41.36#ibcon#*after write, iclass 22, count 0 2006.238.07:45:41.36#ibcon#*before return 0, iclass 22, count 0 2006.238.07:45:41.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:45:41.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:45:41.36#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.07:45:41.36#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.07:45:41.36$vc4f8/vb=3,4 2006.238.07:45:41.36#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.238.07:45:41.36#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.238.07:45:41.36#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:41.36#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:45:41.42#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:45:41.42#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:45:41.42#ibcon#enter wrdev, iclass 24, count 2 2006.238.07:45:41.42#ibcon#first serial, iclass 24, count 2 2006.238.07:45:41.42#ibcon#enter sib2, iclass 24, count 2 2006.238.07:45:41.42#ibcon#flushed, iclass 24, count 2 2006.238.07:45:41.42#ibcon#about to write, iclass 24, count 2 2006.238.07:45:41.42#ibcon#wrote, iclass 24, count 2 2006.238.07:45:41.42#ibcon#about to read 3, iclass 24, count 2 2006.238.07:45:41.44#ibcon#read 3, iclass 24, count 2 2006.238.07:45:41.44#ibcon#about to read 4, iclass 24, count 2 2006.238.07:45:41.44#ibcon#read 4, iclass 24, count 2 2006.238.07:45:41.44#ibcon#about to read 5, iclass 24, count 2 2006.238.07:45:41.44#ibcon#read 5, iclass 24, count 2 2006.238.07:45:41.44#ibcon#about to read 6, iclass 24, count 2 2006.238.07:45:41.44#ibcon#read 6, iclass 24, count 2 2006.238.07:45:41.44#ibcon#end of sib2, iclass 24, count 2 2006.238.07:45:41.44#ibcon#*mode == 0, iclass 24, count 2 2006.238.07:45:41.44#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.238.07:45:41.44#ibcon#[27=AT03-04\r\n] 2006.238.07:45:41.44#ibcon#*before write, iclass 24, count 2 2006.238.07:45:41.44#ibcon#enter sib2, iclass 24, count 2 2006.238.07:45:41.44#ibcon#flushed, iclass 24, count 2 2006.238.07:45:41.44#ibcon#about to write, iclass 24, count 2 2006.238.07:45:41.44#ibcon#wrote, iclass 24, count 2 2006.238.07:45:41.44#ibcon#about to read 3, iclass 24, count 2 2006.238.07:45:41.47#ibcon#read 3, iclass 24, count 2 2006.238.07:45:41.47#ibcon#about to read 4, iclass 24, count 2 2006.238.07:45:41.47#ibcon#read 4, iclass 24, count 2 2006.238.07:45:41.47#ibcon#about to read 5, iclass 24, count 2 2006.238.07:45:41.47#ibcon#read 5, iclass 24, count 2 2006.238.07:45:41.47#ibcon#about to read 6, iclass 24, count 2 2006.238.07:45:41.47#ibcon#read 6, iclass 24, count 2 2006.238.07:45:41.47#ibcon#end of sib2, iclass 24, count 2 2006.238.07:45:41.47#ibcon#*after write, iclass 24, count 2 2006.238.07:45:41.47#ibcon#*before return 0, iclass 24, count 2 2006.238.07:45:41.47#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:45:41.47#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:45:41.47#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.238.07:45:41.47#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:41.47#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:45:41.59#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:45:41.59#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:45:41.59#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:45:41.59#ibcon#first serial, iclass 24, count 0 2006.238.07:45:41.59#ibcon#enter sib2, iclass 24, count 0 2006.238.07:45:41.59#ibcon#flushed, iclass 24, count 0 2006.238.07:45:41.59#ibcon#about to write, iclass 24, count 0 2006.238.07:45:41.59#ibcon#wrote, iclass 24, count 0 2006.238.07:45:41.59#ibcon#about to read 3, iclass 24, count 0 2006.238.07:45:41.61#ibcon#read 3, iclass 24, count 0 2006.238.07:45:41.61#ibcon#about to read 4, iclass 24, count 0 2006.238.07:45:41.61#ibcon#read 4, iclass 24, count 0 2006.238.07:45:41.61#ibcon#about to read 5, iclass 24, count 0 2006.238.07:45:41.61#ibcon#read 5, iclass 24, count 0 2006.238.07:45:41.61#ibcon#about to read 6, iclass 24, count 0 2006.238.07:45:41.61#ibcon#read 6, iclass 24, count 0 2006.238.07:45:41.61#ibcon#end of sib2, iclass 24, count 0 2006.238.07:45:41.61#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:45:41.61#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:45:41.61#ibcon#[27=USB\r\n] 2006.238.07:45:41.61#ibcon#*before write, iclass 24, count 0 2006.238.07:45:41.61#ibcon#enter sib2, iclass 24, count 0 2006.238.07:45:41.61#ibcon#flushed, iclass 24, count 0 2006.238.07:45:41.61#ibcon#about to write, iclass 24, count 0 2006.238.07:45:41.61#ibcon#wrote, iclass 24, count 0 2006.238.07:45:41.61#ibcon#about to read 3, iclass 24, count 0 2006.238.07:45:41.64#ibcon#read 3, iclass 24, count 0 2006.238.07:45:41.64#ibcon#about to read 4, iclass 24, count 0 2006.238.07:45:41.64#ibcon#read 4, iclass 24, count 0 2006.238.07:45:41.64#ibcon#about to read 5, iclass 24, count 0 2006.238.07:45:41.64#ibcon#read 5, iclass 24, count 0 2006.238.07:45:41.64#ibcon#about to read 6, iclass 24, count 0 2006.238.07:45:41.64#ibcon#read 6, iclass 24, count 0 2006.238.07:45:41.64#ibcon#end of sib2, iclass 24, count 0 2006.238.07:45:41.64#ibcon#*after write, iclass 24, count 0 2006.238.07:45:41.64#ibcon#*before return 0, iclass 24, count 0 2006.238.07:45:41.64#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:45:41.64#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:45:41.64#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:45:41.64#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:45:41.64$vc4f8/vblo=4,712.99 2006.238.07:45:41.64#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.07:45:41.64#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.07:45:41.64#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:41.64#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:45:41.64#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:45:41.64#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:45:41.64#ibcon#enter wrdev, iclass 26, count 0 2006.238.07:45:41.64#ibcon#first serial, iclass 26, count 0 2006.238.07:45:41.64#ibcon#enter sib2, iclass 26, count 0 2006.238.07:45:41.64#ibcon#flushed, iclass 26, count 0 2006.238.07:45:41.64#ibcon#about to write, iclass 26, count 0 2006.238.07:45:41.64#ibcon#wrote, iclass 26, count 0 2006.238.07:45:41.64#ibcon#about to read 3, iclass 26, count 0 2006.238.07:45:41.66#ibcon#read 3, iclass 26, count 0 2006.238.07:45:41.66#ibcon#about to read 4, iclass 26, count 0 2006.238.07:45:41.66#ibcon#read 4, iclass 26, count 0 2006.238.07:45:41.66#ibcon#about to read 5, iclass 26, count 0 2006.238.07:45:41.66#ibcon#read 5, iclass 26, count 0 2006.238.07:45:41.66#ibcon#about to read 6, iclass 26, count 0 2006.238.07:45:41.66#ibcon#read 6, iclass 26, count 0 2006.238.07:45:41.66#ibcon#end of sib2, iclass 26, count 0 2006.238.07:45:41.66#ibcon#*mode == 0, iclass 26, count 0 2006.238.07:45:41.66#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.07:45:41.66#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:45:41.66#ibcon#*before write, iclass 26, count 0 2006.238.07:45:41.66#ibcon#enter sib2, iclass 26, count 0 2006.238.07:45:41.66#ibcon#flushed, iclass 26, count 0 2006.238.07:45:41.66#ibcon#about to write, iclass 26, count 0 2006.238.07:45:41.66#ibcon#wrote, iclass 26, count 0 2006.238.07:45:41.66#ibcon#about to read 3, iclass 26, count 0 2006.238.07:45:41.70#ibcon#read 3, iclass 26, count 0 2006.238.07:45:41.70#ibcon#about to read 4, iclass 26, count 0 2006.238.07:45:41.70#ibcon#read 4, iclass 26, count 0 2006.238.07:45:41.70#ibcon#about to read 5, iclass 26, count 0 2006.238.07:45:41.70#ibcon#read 5, iclass 26, count 0 2006.238.07:45:41.70#ibcon#about to read 6, iclass 26, count 0 2006.238.07:45:41.70#ibcon#read 6, iclass 26, count 0 2006.238.07:45:41.70#ibcon#end of sib2, iclass 26, count 0 2006.238.07:45:41.70#ibcon#*after write, iclass 26, count 0 2006.238.07:45:41.70#ibcon#*before return 0, iclass 26, count 0 2006.238.07:45:41.70#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:45:41.70#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:45:41.70#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.07:45:41.70#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.07:45:41.70$vc4f8/vb=4,4 2006.238.07:45:41.70#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.07:45:41.70#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.07:45:41.70#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:41.70#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:45:41.76#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:45:41.76#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:45:41.76#ibcon#enter wrdev, iclass 28, count 2 2006.238.07:45:41.76#ibcon#first serial, iclass 28, count 2 2006.238.07:45:41.76#ibcon#enter sib2, iclass 28, count 2 2006.238.07:45:41.76#ibcon#flushed, iclass 28, count 2 2006.238.07:45:41.76#ibcon#about to write, iclass 28, count 2 2006.238.07:45:41.76#ibcon#wrote, iclass 28, count 2 2006.238.07:45:41.76#ibcon#about to read 3, iclass 28, count 2 2006.238.07:45:41.78#ibcon#read 3, iclass 28, count 2 2006.238.07:45:41.78#ibcon#about to read 4, iclass 28, count 2 2006.238.07:45:41.78#ibcon#read 4, iclass 28, count 2 2006.238.07:45:41.78#ibcon#about to read 5, iclass 28, count 2 2006.238.07:45:41.78#ibcon#read 5, iclass 28, count 2 2006.238.07:45:41.78#ibcon#about to read 6, iclass 28, count 2 2006.238.07:45:41.78#ibcon#read 6, iclass 28, count 2 2006.238.07:45:41.78#ibcon#end of sib2, iclass 28, count 2 2006.238.07:45:41.78#ibcon#*mode == 0, iclass 28, count 2 2006.238.07:45:41.78#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.07:45:41.78#ibcon#[27=AT04-04\r\n] 2006.238.07:45:41.78#ibcon#*before write, iclass 28, count 2 2006.238.07:45:41.78#ibcon#enter sib2, iclass 28, count 2 2006.238.07:45:41.78#ibcon#flushed, iclass 28, count 2 2006.238.07:45:41.78#ibcon#about to write, iclass 28, count 2 2006.238.07:45:41.78#ibcon#wrote, iclass 28, count 2 2006.238.07:45:41.78#ibcon#about to read 3, iclass 28, count 2 2006.238.07:45:41.81#ibcon#read 3, iclass 28, count 2 2006.238.07:45:41.81#ibcon#about to read 4, iclass 28, count 2 2006.238.07:45:41.81#ibcon#read 4, iclass 28, count 2 2006.238.07:45:41.81#ibcon#about to read 5, iclass 28, count 2 2006.238.07:45:41.81#ibcon#read 5, iclass 28, count 2 2006.238.07:45:41.81#ibcon#about to read 6, iclass 28, count 2 2006.238.07:45:41.81#ibcon#read 6, iclass 28, count 2 2006.238.07:45:41.81#ibcon#end of sib2, iclass 28, count 2 2006.238.07:45:41.81#ibcon#*after write, iclass 28, count 2 2006.238.07:45:41.81#ibcon#*before return 0, iclass 28, count 2 2006.238.07:45:41.81#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:45:41.81#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:45:41.81#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.07:45:41.81#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:41.81#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:45:41.93#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:45:41.93#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:45:41.93#ibcon#enter wrdev, iclass 28, count 0 2006.238.07:45:41.93#ibcon#first serial, iclass 28, count 0 2006.238.07:45:41.93#ibcon#enter sib2, iclass 28, count 0 2006.238.07:45:41.93#ibcon#flushed, iclass 28, count 0 2006.238.07:45:41.93#ibcon#about to write, iclass 28, count 0 2006.238.07:45:41.93#ibcon#wrote, iclass 28, count 0 2006.238.07:45:41.93#ibcon#about to read 3, iclass 28, count 0 2006.238.07:45:41.95#ibcon#read 3, iclass 28, count 0 2006.238.07:45:41.95#ibcon#about to read 4, iclass 28, count 0 2006.238.07:45:41.95#ibcon#read 4, iclass 28, count 0 2006.238.07:45:41.95#ibcon#about to read 5, iclass 28, count 0 2006.238.07:45:41.95#ibcon#read 5, iclass 28, count 0 2006.238.07:45:41.95#ibcon#about to read 6, iclass 28, count 0 2006.238.07:45:41.95#ibcon#read 6, iclass 28, count 0 2006.238.07:45:41.95#ibcon#end of sib2, iclass 28, count 0 2006.238.07:45:41.95#ibcon#*mode == 0, iclass 28, count 0 2006.238.07:45:41.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.07:45:41.95#ibcon#[27=USB\r\n] 2006.238.07:45:41.95#ibcon#*before write, iclass 28, count 0 2006.238.07:45:41.95#ibcon#enter sib2, iclass 28, count 0 2006.238.07:45:41.95#ibcon#flushed, iclass 28, count 0 2006.238.07:45:41.95#ibcon#about to write, iclass 28, count 0 2006.238.07:45:41.95#ibcon#wrote, iclass 28, count 0 2006.238.07:45:41.95#ibcon#about to read 3, iclass 28, count 0 2006.238.07:45:41.98#ibcon#read 3, iclass 28, count 0 2006.238.07:45:41.98#ibcon#about to read 4, iclass 28, count 0 2006.238.07:45:41.98#ibcon#read 4, iclass 28, count 0 2006.238.07:45:41.98#ibcon#about to read 5, iclass 28, count 0 2006.238.07:45:41.98#ibcon#read 5, iclass 28, count 0 2006.238.07:45:41.98#ibcon#about to read 6, iclass 28, count 0 2006.238.07:45:41.98#ibcon#read 6, iclass 28, count 0 2006.238.07:45:41.98#ibcon#end of sib2, iclass 28, count 0 2006.238.07:45:41.98#ibcon#*after write, iclass 28, count 0 2006.238.07:45:41.98#ibcon#*before return 0, iclass 28, count 0 2006.238.07:45:41.98#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:45:41.98#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:45:41.98#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.07:45:41.98#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.07:45:41.98$vc4f8/vblo=5,744.99 2006.238.07:45:41.98#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.07:45:41.98#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.07:45:41.98#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:41.98#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:45:41.98#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:45:41.98#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:45:41.98#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:45:41.98#ibcon#first serial, iclass 30, count 0 2006.238.07:45:41.98#ibcon#enter sib2, iclass 30, count 0 2006.238.07:45:41.98#ibcon#flushed, iclass 30, count 0 2006.238.07:45:41.98#ibcon#about to write, iclass 30, count 0 2006.238.07:45:41.98#ibcon#wrote, iclass 30, count 0 2006.238.07:45:41.98#ibcon#about to read 3, iclass 30, count 0 2006.238.07:45:42.00#ibcon#read 3, iclass 30, count 0 2006.238.07:45:42.00#ibcon#about to read 4, iclass 30, count 0 2006.238.07:45:42.00#ibcon#read 4, iclass 30, count 0 2006.238.07:45:42.00#ibcon#about to read 5, iclass 30, count 0 2006.238.07:45:42.00#ibcon#read 5, iclass 30, count 0 2006.238.07:45:42.00#ibcon#about to read 6, iclass 30, count 0 2006.238.07:45:42.00#ibcon#read 6, iclass 30, count 0 2006.238.07:45:42.00#ibcon#end of sib2, iclass 30, count 0 2006.238.07:45:42.00#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:45:42.00#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:45:42.00#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:45:42.00#ibcon#*before write, iclass 30, count 0 2006.238.07:45:42.00#ibcon#enter sib2, iclass 30, count 0 2006.238.07:45:42.00#ibcon#flushed, iclass 30, count 0 2006.238.07:45:42.00#ibcon#about to write, iclass 30, count 0 2006.238.07:45:42.00#ibcon#wrote, iclass 30, count 0 2006.238.07:45:42.00#ibcon#about to read 3, iclass 30, count 0 2006.238.07:45:42.04#ibcon#read 3, iclass 30, count 0 2006.238.07:45:42.04#ibcon#about to read 4, iclass 30, count 0 2006.238.07:45:42.04#ibcon#read 4, iclass 30, count 0 2006.238.07:45:42.04#ibcon#about to read 5, iclass 30, count 0 2006.238.07:45:42.04#ibcon#read 5, iclass 30, count 0 2006.238.07:45:42.04#ibcon#about to read 6, iclass 30, count 0 2006.238.07:45:42.04#ibcon#read 6, iclass 30, count 0 2006.238.07:45:42.04#ibcon#end of sib2, iclass 30, count 0 2006.238.07:45:42.04#ibcon#*after write, iclass 30, count 0 2006.238.07:45:42.04#ibcon#*before return 0, iclass 30, count 0 2006.238.07:45:42.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:45:42.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:45:42.04#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:45:42.04#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:45:42.04$vc4f8/vb=5,4 2006.238.07:45:42.04#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.238.07:45:42.04#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.238.07:45:42.04#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:42.04#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:45:42.10#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:45:42.10#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:45:42.10#ibcon#enter wrdev, iclass 32, count 2 2006.238.07:45:42.10#ibcon#first serial, iclass 32, count 2 2006.238.07:45:42.10#ibcon#enter sib2, iclass 32, count 2 2006.238.07:45:42.10#ibcon#flushed, iclass 32, count 2 2006.238.07:45:42.10#ibcon#about to write, iclass 32, count 2 2006.238.07:45:42.10#ibcon#wrote, iclass 32, count 2 2006.238.07:45:42.10#ibcon#about to read 3, iclass 32, count 2 2006.238.07:45:42.12#ibcon#read 3, iclass 32, count 2 2006.238.07:45:42.12#ibcon#about to read 4, iclass 32, count 2 2006.238.07:45:42.12#ibcon#read 4, iclass 32, count 2 2006.238.07:45:42.12#ibcon#about to read 5, iclass 32, count 2 2006.238.07:45:42.12#ibcon#read 5, iclass 32, count 2 2006.238.07:45:42.12#ibcon#about to read 6, iclass 32, count 2 2006.238.07:45:42.12#ibcon#read 6, iclass 32, count 2 2006.238.07:45:42.12#ibcon#end of sib2, iclass 32, count 2 2006.238.07:45:42.12#ibcon#*mode == 0, iclass 32, count 2 2006.238.07:45:42.12#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.238.07:45:42.12#ibcon#[27=AT05-04\r\n] 2006.238.07:45:42.12#ibcon#*before write, iclass 32, count 2 2006.238.07:45:42.12#ibcon#enter sib2, iclass 32, count 2 2006.238.07:45:42.12#ibcon#flushed, iclass 32, count 2 2006.238.07:45:42.12#ibcon#about to write, iclass 32, count 2 2006.238.07:45:42.12#ibcon#wrote, iclass 32, count 2 2006.238.07:45:42.12#ibcon#about to read 3, iclass 32, count 2 2006.238.07:45:42.15#ibcon#read 3, iclass 32, count 2 2006.238.07:45:42.15#ibcon#about to read 4, iclass 32, count 2 2006.238.07:45:42.15#ibcon#read 4, iclass 32, count 2 2006.238.07:45:42.15#ibcon#about to read 5, iclass 32, count 2 2006.238.07:45:42.15#ibcon#read 5, iclass 32, count 2 2006.238.07:45:42.15#ibcon#about to read 6, iclass 32, count 2 2006.238.07:45:42.15#ibcon#read 6, iclass 32, count 2 2006.238.07:45:42.15#ibcon#end of sib2, iclass 32, count 2 2006.238.07:45:42.15#ibcon#*after write, iclass 32, count 2 2006.238.07:45:42.15#ibcon#*before return 0, iclass 32, count 2 2006.238.07:45:42.15#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:45:42.15#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:45:42.15#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.238.07:45:42.15#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:42.15#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:45:42.27#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:45:42.27#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:45:42.27#ibcon#enter wrdev, iclass 32, count 0 2006.238.07:45:42.27#ibcon#first serial, iclass 32, count 0 2006.238.07:45:42.27#ibcon#enter sib2, iclass 32, count 0 2006.238.07:45:42.27#ibcon#flushed, iclass 32, count 0 2006.238.07:45:42.27#ibcon#about to write, iclass 32, count 0 2006.238.07:45:42.27#ibcon#wrote, iclass 32, count 0 2006.238.07:45:42.27#ibcon#about to read 3, iclass 32, count 0 2006.238.07:45:42.29#ibcon#read 3, iclass 32, count 0 2006.238.07:45:42.29#ibcon#about to read 4, iclass 32, count 0 2006.238.07:45:42.29#ibcon#read 4, iclass 32, count 0 2006.238.07:45:42.29#ibcon#about to read 5, iclass 32, count 0 2006.238.07:45:42.29#ibcon#read 5, iclass 32, count 0 2006.238.07:45:42.29#ibcon#about to read 6, iclass 32, count 0 2006.238.07:45:42.29#ibcon#read 6, iclass 32, count 0 2006.238.07:45:42.29#ibcon#end of sib2, iclass 32, count 0 2006.238.07:45:42.29#ibcon#*mode == 0, iclass 32, count 0 2006.238.07:45:42.29#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.07:45:42.29#ibcon#[27=USB\r\n] 2006.238.07:45:42.29#ibcon#*before write, iclass 32, count 0 2006.238.07:45:42.29#ibcon#enter sib2, iclass 32, count 0 2006.238.07:45:42.29#ibcon#flushed, iclass 32, count 0 2006.238.07:45:42.29#ibcon#about to write, iclass 32, count 0 2006.238.07:45:42.29#ibcon#wrote, iclass 32, count 0 2006.238.07:45:42.29#ibcon#about to read 3, iclass 32, count 0 2006.238.07:45:42.32#ibcon#read 3, iclass 32, count 0 2006.238.07:45:42.32#ibcon#about to read 4, iclass 32, count 0 2006.238.07:45:42.32#ibcon#read 4, iclass 32, count 0 2006.238.07:45:42.32#ibcon#about to read 5, iclass 32, count 0 2006.238.07:45:42.32#ibcon#read 5, iclass 32, count 0 2006.238.07:45:42.32#ibcon#about to read 6, iclass 32, count 0 2006.238.07:45:42.32#ibcon#read 6, iclass 32, count 0 2006.238.07:45:42.32#ibcon#end of sib2, iclass 32, count 0 2006.238.07:45:42.32#ibcon#*after write, iclass 32, count 0 2006.238.07:45:42.32#ibcon#*before return 0, iclass 32, count 0 2006.238.07:45:42.32#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:45:42.32#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:45:42.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.07:45:42.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.07:45:42.32$vc4f8/vblo=6,752.99 2006.238.07:45:42.32#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.238.07:45:42.32#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.238.07:45:42.32#ibcon#ireg 17 cls_cnt 0 2006.238.07:45:42.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:45:42.32#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:45:42.32#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:45:42.32#ibcon#enter wrdev, iclass 34, count 0 2006.238.07:45:42.32#ibcon#first serial, iclass 34, count 0 2006.238.07:45:42.32#ibcon#enter sib2, iclass 34, count 0 2006.238.07:45:42.32#ibcon#flushed, iclass 34, count 0 2006.238.07:45:42.32#ibcon#about to write, iclass 34, count 0 2006.238.07:45:42.32#ibcon#wrote, iclass 34, count 0 2006.238.07:45:42.32#ibcon#about to read 3, iclass 34, count 0 2006.238.07:45:42.34#ibcon#read 3, iclass 34, count 0 2006.238.07:45:42.34#ibcon#about to read 4, iclass 34, count 0 2006.238.07:45:42.34#ibcon#read 4, iclass 34, count 0 2006.238.07:45:42.34#ibcon#about to read 5, iclass 34, count 0 2006.238.07:45:42.34#ibcon#read 5, iclass 34, count 0 2006.238.07:45:42.34#ibcon#about to read 6, iclass 34, count 0 2006.238.07:45:42.34#ibcon#read 6, iclass 34, count 0 2006.238.07:45:42.34#ibcon#end of sib2, iclass 34, count 0 2006.238.07:45:42.34#ibcon#*mode == 0, iclass 34, count 0 2006.238.07:45:42.34#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.07:45:42.34#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:45:42.34#ibcon#*before write, iclass 34, count 0 2006.238.07:45:42.34#ibcon#enter sib2, iclass 34, count 0 2006.238.07:45:42.34#ibcon#flushed, iclass 34, count 0 2006.238.07:45:42.34#ibcon#about to write, iclass 34, count 0 2006.238.07:45:42.34#ibcon#wrote, iclass 34, count 0 2006.238.07:45:42.34#ibcon#about to read 3, iclass 34, count 0 2006.238.07:45:42.38#ibcon#read 3, iclass 34, count 0 2006.238.07:45:42.38#ibcon#about to read 4, iclass 34, count 0 2006.238.07:45:42.38#ibcon#read 4, iclass 34, count 0 2006.238.07:45:42.38#ibcon#about to read 5, iclass 34, count 0 2006.238.07:45:42.38#ibcon#read 5, iclass 34, count 0 2006.238.07:45:42.38#ibcon#about to read 6, iclass 34, count 0 2006.238.07:45:42.38#ibcon#read 6, iclass 34, count 0 2006.238.07:45:42.38#ibcon#end of sib2, iclass 34, count 0 2006.238.07:45:42.38#ibcon#*after write, iclass 34, count 0 2006.238.07:45:42.38#ibcon#*before return 0, iclass 34, count 0 2006.238.07:45:42.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:45:42.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:45:42.38#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.07:45:42.38#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.07:45:42.38$vc4f8/vb=6,4 2006.238.07:45:42.38#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.238.07:45:42.38#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.238.07:45:42.38#ibcon#ireg 11 cls_cnt 2 2006.238.07:45:42.38#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:45:42.44#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:45:42.44#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:45:42.44#ibcon#enter wrdev, iclass 36, count 2 2006.238.07:45:42.44#ibcon#first serial, iclass 36, count 2 2006.238.07:45:42.44#ibcon#enter sib2, iclass 36, count 2 2006.238.07:45:42.44#ibcon#flushed, iclass 36, count 2 2006.238.07:45:42.44#ibcon#about to write, iclass 36, count 2 2006.238.07:45:42.44#ibcon#wrote, iclass 36, count 2 2006.238.07:45:42.44#ibcon#about to read 3, iclass 36, count 2 2006.238.07:45:42.46#ibcon#read 3, iclass 36, count 2 2006.238.07:45:42.46#ibcon#about to read 4, iclass 36, count 2 2006.238.07:45:42.46#ibcon#read 4, iclass 36, count 2 2006.238.07:45:42.46#ibcon#about to read 5, iclass 36, count 2 2006.238.07:45:42.46#ibcon#read 5, iclass 36, count 2 2006.238.07:45:42.46#ibcon#about to read 6, iclass 36, count 2 2006.238.07:45:42.46#ibcon#read 6, iclass 36, count 2 2006.238.07:45:42.46#ibcon#end of sib2, iclass 36, count 2 2006.238.07:45:42.46#ibcon#*mode == 0, iclass 36, count 2 2006.238.07:45:42.46#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.238.07:45:42.46#ibcon#[27=AT06-04\r\n] 2006.238.07:45:42.46#ibcon#*before write, iclass 36, count 2 2006.238.07:45:42.46#ibcon#enter sib2, iclass 36, count 2 2006.238.07:45:42.46#ibcon#flushed, iclass 36, count 2 2006.238.07:45:42.46#ibcon#about to write, iclass 36, count 2 2006.238.07:45:42.46#ibcon#wrote, iclass 36, count 2 2006.238.07:45:42.46#ibcon#about to read 3, iclass 36, count 2 2006.238.07:45:42.49#ibcon#read 3, iclass 36, count 2 2006.238.07:45:42.49#ibcon#about to read 4, iclass 36, count 2 2006.238.07:45:42.49#ibcon#read 4, iclass 36, count 2 2006.238.07:45:42.49#ibcon#about to read 5, iclass 36, count 2 2006.238.07:45:42.49#ibcon#read 5, iclass 36, count 2 2006.238.07:45:42.49#ibcon#about to read 6, iclass 36, count 2 2006.238.07:45:42.49#ibcon#read 6, iclass 36, count 2 2006.238.07:45:42.49#ibcon#end of sib2, iclass 36, count 2 2006.238.07:45:42.49#ibcon#*after write, iclass 36, count 2 2006.238.07:45:42.49#ibcon#*before return 0, iclass 36, count 2 2006.238.07:45:42.49#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:45:42.49#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:45:42.49#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.238.07:45:42.49#ibcon#ireg 7 cls_cnt 0 2006.238.07:45:42.49#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:45:42.61#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:45:42.61#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:45:42.61#ibcon#enter wrdev, iclass 36, count 0 2006.238.07:45:42.61#ibcon#first serial, iclass 36, count 0 2006.238.07:45:42.61#ibcon#enter sib2, iclass 36, count 0 2006.238.07:45:42.61#ibcon#flushed, iclass 36, count 0 2006.238.07:45:42.61#ibcon#about to write, iclass 36, count 0 2006.238.07:45:42.61#ibcon#wrote, iclass 36, count 0 2006.238.07:45:42.61#ibcon#about to read 3, iclass 36, count 0 2006.238.07:45:42.63#ibcon#read 3, iclass 36, count 0 2006.238.07:45:42.63#ibcon#about to read 4, iclass 36, count 0 2006.238.07:45:42.63#ibcon#read 4, iclass 36, count 0 2006.238.07:45:42.63#ibcon#about to read 5, iclass 36, count 0 2006.238.07:45:42.63#ibcon#read 5, iclass 36, count 0 2006.238.07:45:42.63#ibcon#about to read 6, iclass 36, count 0 2006.238.07:45:42.63#ibcon#read 6, iclass 36, count 0 2006.238.07:45:42.63#ibcon#end of sib2, iclass 36, count 0 2006.238.07:45:42.63#ibcon#*mode == 0, iclass 36, count 0 2006.238.07:45:42.63#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.07:45:42.63#ibcon#[27=USB\r\n] 2006.238.07:45:42.63#ibcon#*before write, iclass 36, count 0 2006.238.07:45:42.63#ibcon#enter sib2, iclass 36, count 0 2006.238.07:45:42.63#ibcon#flushed, iclass 36, count 0 2006.238.07:45:42.63#ibcon#about to write, iclass 36, count 0 2006.238.07:45:42.63#ibcon#wrote, iclass 36, count 0 2006.238.07:45:42.63#ibcon#about to read 3, iclass 36, count 0 2006.238.07:45:42.66#ibcon#read 3, iclass 36, count 0 2006.238.07:45:42.66#ibcon#about to read 4, iclass 36, count 0 2006.238.07:45:42.66#ibcon#read 4, iclass 36, count 0 2006.238.07:45:42.66#ibcon#about to read 5, iclass 36, count 0 2006.238.07:45:42.66#ibcon#read 5, iclass 36, count 0 2006.238.07:45:42.66#ibcon#about to read 6, iclass 36, count 0 2006.238.07:45:42.66#ibcon#read 6, iclass 36, count 0 2006.238.07:45:42.66#ibcon#end of sib2, iclass 36, count 0 2006.238.07:45:42.66#ibcon#*after write, iclass 36, count 0 2006.238.07:45:42.66#ibcon#*before return 0, iclass 36, count 0 2006.238.07:45:42.66#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:45:42.66#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:45:42.66#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.07:45:42.66#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.07:45:42.66$vc4f8/vabw=wide 2006.238.07:45:42.66#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.238.07:45:42.66#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.238.07:45:42.66#ibcon#ireg 8 cls_cnt 0 2006.238.07:45:42.66#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:45:42.66#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:45:42.66#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:45:42.66#ibcon#enter wrdev, iclass 38, count 0 2006.238.07:45:42.66#ibcon#first serial, iclass 38, count 0 2006.238.07:45:42.66#ibcon#enter sib2, iclass 38, count 0 2006.238.07:45:42.66#ibcon#flushed, iclass 38, count 0 2006.238.07:45:42.66#ibcon#about to write, iclass 38, count 0 2006.238.07:45:42.66#ibcon#wrote, iclass 38, count 0 2006.238.07:45:42.66#ibcon#about to read 3, iclass 38, count 0 2006.238.07:45:42.68#ibcon#read 3, iclass 38, count 0 2006.238.07:45:42.68#ibcon#about to read 4, iclass 38, count 0 2006.238.07:45:42.68#ibcon#read 4, iclass 38, count 0 2006.238.07:45:42.68#ibcon#about to read 5, iclass 38, count 0 2006.238.07:45:42.68#ibcon#read 5, iclass 38, count 0 2006.238.07:45:42.68#ibcon#about to read 6, iclass 38, count 0 2006.238.07:45:42.68#ibcon#read 6, iclass 38, count 0 2006.238.07:45:42.68#ibcon#end of sib2, iclass 38, count 0 2006.238.07:45:42.68#ibcon#*mode == 0, iclass 38, count 0 2006.238.07:45:42.68#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.07:45:42.68#ibcon#[25=BW32\r\n] 2006.238.07:45:42.68#ibcon#*before write, iclass 38, count 0 2006.238.07:45:42.68#ibcon#enter sib2, iclass 38, count 0 2006.238.07:45:42.68#ibcon#flushed, iclass 38, count 0 2006.238.07:45:42.68#ibcon#about to write, iclass 38, count 0 2006.238.07:45:42.68#ibcon#wrote, iclass 38, count 0 2006.238.07:45:42.68#ibcon#about to read 3, iclass 38, count 0 2006.238.07:45:42.71#ibcon#read 3, iclass 38, count 0 2006.238.07:45:42.71#ibcon#about to read 4, iclass 38, count 0 2006.238.07:45:42.71#ibcon#read 4, iclass 38, count 0 2006.238.07:45:42.71#ibcon#about to read 5, iclass 38, count 0 2006.238.07:45:42.71#ibcon#read 5, iclass 38, count 0 2006.238.07:45:42.71#ibcon#about to read 6, iclass 38, count 0 2006.238.07:45:42.71#ibcon#read 6, iclass 38, count 0 2006.238.07:45:42.71#ibcon#end of sib2, iclass 38, count 0 2006.238.07:45:42.71#ibcon#*after write, iclass 38, count 0 2006.238.07:45:42.71#ibcon#*before return 0, iclass 38, count 0 2006.238.07:45:42.71#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:45:42.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:45:42.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.07:45:42.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.07:45:42.71$vc4f8/vbbw=wide 2006.238.07:45:42.71#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.07:45:42.71#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.07:45:42.71#ibcon#ireg 8 cls_cnt 0 2006.238.07:45:42.71#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:45:42.78#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:45:42.78#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:45:42.78#ibcon#enter wrdev, iclass 40, count 0 2006.238.07:45:42.78#ibcon#first serial, iclass 40, count 0 2006.238.07:45:42.78#ibcon#enter sib2, iclass 40, count 0 2006.238.07:45:42.78#ibcon#flushed, iclass 40, count 0 2006.238.07:45:42.78#ibcon#about to write, iclass 40, count 0 2006.238.07:45:42.78#ibcon#wrote, iclass 40, count 0 2006.238.07:45:42.78#ibcon#about to read 3, iclass 40, count 0 2006.238.07:45:42.80#ibcon#read 3, iclass 40, count 0 2006.238.07:45:42.80#ibcon#about to read 4, iclass 40, count 0 2006.238.07:45:42.80#ibcon#read 4, iclass 40, count 0 2006.238.07:45:42.80#ibcon#about to read 5, iclass 40, count 0 2006.238.07:45:42.80#ibcon#read 5, iclass 40, count 0 2006.238.07:45:42.80#ibcon#about to read 6, iclass 40, count 0 2006.238.07:45:42.80#ibcon#read 6, iclass 40, count 0 2006.238.07:45:42.80#ibcon#end of sib2, iclass 40, count 0 2006.238.07:45:42.80#ibcon#*mode == 0, iclass 40, count 0 2006.238.07:45:42.80#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.07:45:42.80#ibcon#[27=BW32\r\n] 2006.238.07:45:42.80#ibcon#*before write, iclass 40, count 0 2006.238.07:45:42.80#ibcon#enter sib2, iclass 40, count 0 2006.238.07:45:42.80#ibcon#flushed, iclass 40, count 0 2006.238.07:45:42.80#ibcon#about to write, iclass 40, count 0 2006.238.07:45:42.80#ibcon#wrote, iclass 40, count 0 2006.238.07:45:42.80#ibcon#about to read 3, iclass 40, count 0 2006.238.07:45:42.83#ibcon#read 3, iclass 40, count 0 2006.238.07:45:42.83#ibcon#about to read 4, iclass 40, count 0 2006.238.07:45:42.83#ibcon#read 4, iclass 40, count 0 2006.238.07:45:42.83#ibcon#about to read 5, iclass 40, count 0 2006.238.07:45:42.83#ibcon#read 5, iclass 40, count 0 2006.238.07:45:42.83#ibcon#about to read 6, iclass 40, count 0 2006.238.07:45:42.83#ibcon#read 6, iclass 40, count 0 2006.238.07:45:42.83#ibcon#end of sib2, iclass 40, count 0 2006.238.07:45:42.83#ibcon#*after write, iclass 40, count 0 2006.238.07:45:42.83#ibcon#*before return 0, iclass 40, count 0 2006.238.07:45:42.83#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:45:42.83#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:45:42.83#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.07:45:42.83#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.07:45:42.83$4f8m12a/ifd4f 2006.238.07:45:42.83$ifd4f/lo= 2006.238.07:45:42.83$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:45:42.83$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:45:42.83$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:45:42.83$ifd4f/patch= 2006.238.07:45:42.83$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:45:42.83$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:45:42.83$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:45:42.83$4f8m12a/"form=m,16.000,1:2 2006.238.07:45:42.83$4f8m12a/"tpicd 2006.238.07:45:42.83$4f8m12a/echo=off 2006.238.07:45:42.83$4f8m12a/xlog=off 2006.238.07:45:42.83:!2006.238.07:46:10 2006.238.07:45:56.14#trakl#Source acquired 2006.238.07:45:58.14#flagr#flagr/antenna,acquired 2006.238.07:46:10.00:preob 2006.238.07:46:11.14/onsource/TRACKING 2006.238.07:46:11.14:!2006.238.07:46:20 2006.238.07:46:20.00:data_valid=on 2006.238.07:46:20.00:midob 2006.238.07:46:20.14/onsource/TRACKING 2006.238.07:46:20.14/wx/25.32,1012.1,88 2006.238.07:46:20.35/cable/+6.4185E-03 2006.238.07:46:21.44/va/01,08,usb,yes,32,33 2006.238.07:46:21.44/va/02,07,usb,yes,31,33 2006.238.07:46:21.44/va/03,07,usb,yes,30,30 2006.238.07:46:21.44/va/04,07,usb,yes,33,36 2006.238.07:46:21.44/va/05,08,usb,yes,30,32 2006.238.07:46:21.44/va/06,07,usb,yes,33,32 2006.238.07:46:21.44/va/07,07,usb,yes,33,32 2006.238.07:46:21.44/va/08,07,usb,yes,35,35 2006.238.07:46:21.67/valo/01,532.99,yes,locked 2006.238.07:46:21.67/valo/02,572.99,yes,locked 2006.238.07:46:21.67/valo/03,672.99,yes,locked 2006.238.07:46:21.67/valo/04,832.99,yes,locked 2006.238.07:46:21.67/valo/05,652.99,yes,locked 2006.238.07:46:21.67/valo/06,772.99,yes,locked 2006.238.07:46:21.67/valo/07,832.99,yes,locked 2006.238.07:46:21.67/valo/08,852.99,yes,locked 2006.238.07:46:22.76/vb/01,04,usb,yes,30,29 2006.238.07:46:22.76/vb/02,04,usb,yes,32,33 2006.238.07:46:22.76/vb/03,04,usb,yes,28,32 2006.238.07:46:22.76/vb/04,04,usb,yes,29,29 2006.238.07:46:22.76/vb/05,04,usb,yes,28,32 2006.238.07:46:22.76/vb/06,04,usb,yes,29,31 2006.238.07:46:22.76/vb/07,04,usb,yes,31,31 2006.238.07:46:22.76/vb/08,04,usb,yes,28,32 2006.238.07:46:23.00/vblo/01,632.99,yes,locked 2006.238.07:46:23.00/vblo/02,640.99,yes,locked 2006.238.07:46:23.00/vblo/03,656.99,yes,locked 2006.238.07:46:23.00/vblo/04,712.99,yes,locked 2006.238.07:46:23.00/vblo/05,744.99,yes,locked 2006.238.07:46:23.00/vblo/06,752.99,yes,locked 2006.238.07:46:23.00/vblo/07,734.99,yes,locked 2006.238.07:46:23.00/vblo/08,744.99,yes,locked 2006.238.07:46:23.15/vabw/8 2006.238.07:46:23.30/vbbw/8 2006.238.07:46:23.41/xfe/off,on,13.0 2006.238.07:46:23.78/ifatt/23,28,28,28 2006.238.07:46:24.08/fmout-gps/S +4.32E-07 2006.238.07:46:24.12:!2006.238.07:47:20 2006.238.07:47:20.00:data_valid=off 2006.238.07:47:20.00:postob 2006.238.07:47:20.10/cable/+6.4192E-03 2006.238.07:47:20.10/wx/25.32,1012.2,87 2006.238.07:47:21.08/fmout-gps/S +4.31E-07 2006.238.07:47:21.08:scan_name=238-0748,k06238,60 2006.238.07:47:21.09:source=1739+522,174036.98,521143.4,2000.0,cw 2006.238.07:47:21.14#flagr#flagr/antenna,new-source 2006.238.07:47:22.14:checkk5 2006.238.07:47:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:47:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:47:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:47:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:47:24.01/chk_obsdata//k5ts1/T2380746??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:47:24.38/chk_obsdata//k5ts2/T2380746??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:47:24.75/chk_obsdata//k5ts3/T2380746??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:47:25.12/chk_obsdata//k5ts4/T2380746??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:47:25.81/k5log//k5ts1_log_newline 2006.238.07:47:26.52/k5log//k5ts2_log_newline 2006.238.07:47:27.21/k5log//k5ts3_log_newline 2006.238.07:47:27.90/k5log//k5ts4_log_newline 2006.238.07:47:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:47:27.93:4f8m12a=1 2006.238.07:47:27.93$4f8m12a/echo=on 2006.238.07:47:27.93$4f8m12a/pcalon 2006.238.07:47:27.93$pcalon/"no phase cal control is implemented here 2006.238.07:47:27.93$4f8m12a/"tpicd=stop 2006.238.07:47:27.93$4f8m12a/vc4f8 2006.238.07:47:27.93$vc4f8/valo=1,532.99 2006.238.07:47:27.93#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.07:47:27.93#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.07:47:27.93#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:27.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:47:27.93#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:47:27.93#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:47:27.93#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:47:27.93#ibcon#first serial, iclass 11, count 0 2006.238.07:47:27.93#ibcon#enter sib2, iclass 11, count 0 2006.238.07:47:27.93#ibcon#flushed, iclass 11, count 0 2006.238.07:47:27.93#ibcon#about to write, iclass 11, count 0 2006.238.07:47:27.93#ibcon#wrote, iclass 11, count 0 2006.238.07:47:27.93#ibcon#about to read 3, iclass 11, count 0 2006.238.07:47:27.97#ibcon#read 3, iclass 11, count 0 2006.238.07:47:27.97#ibcon#about to read 4, iclass 11, count 0 2006.238.07:47:27.97#ibcon#read 4, iclass 11, count 0 2006.238.07:47:27.97#ibcon#about to read 5, iclass 11, count 0 2006.238.07:47:27.97#ibcon#read 5, iclass 11, count 0 2006.238.07:47:27.97#ibcon#about to read 6, iclass 11, count 0 2006.238.07:47:27.97#ibcon#read 6, iclass 11, count 0 2006.238.07:47:27.97#ibcon#end of sib2, iclass 11, count 0 2006.238.07:47:27.97#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:47:27.97#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:47:27.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:47:27.97#ibcon#*before write, iclass 11, count 0 2006.238.07:47:27.97#ibcon#enter sib2, iclass 11, count 0 2006.238.07:47:27.97#ibcon#flushed, iclass 11, count 0 2006.238.07:47:27.97#ibcon#about to write, iclass 11, count 0 2006.238.07:47:27.97#ibcon#wrote, iclass 11, count 0 2006.238.07:47:27.97#ibcon#about to read 3, iclass 11, count 0 2006.238.07:47:28.02#ibcon#read 3, iclass 11, count 0 2006.238.07:47:28.02#ibcon#about to read 4, iclass 11, count 0 2006.238.07:47:28.02#ibcon#read 4, iclass 11, count 0 2006.238.07:47:28.02#ibcon#about to read 5, iclass 11, count 0 2006.238.07:47:28.02#ibcon#read 5, iclass 11, count 0 2006.238.07:47:28.02#ibcon#about to read 6, iclass 11, count 0 2006.238.07:47:28.02#ibcon#read 6, iclass 11, count 0 2006.238.07:47:28.02#ibcon#end of sib2, iclass 11, count 0 2006.238.07:47:28.02#ibcon#*after write, iclass 11, count 0 2006.238.07:47:28.02#ibcon#*before return 0, iclass 11, count 0 2006.238.07:47:28.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:47:28.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:47:28.02#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:47:28.02#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:47:28.02$vc4f8/va=1,8 2006.238.07:47:28.02#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.07:47:28.02#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.07:47:28.02#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:28.02#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:47:28.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:47:28.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:47:28.02#ibcon#enter wrdev, iclass 13, count 2 2006.238.07:47:28.02#ibcon#first serial, iclass 13, count 2 2006.238.07:47:28.02#ibcon#enter sib2, iclass 13, count 2 2006.238.07:47:28.02#ibcon#flushed, iclass 13, count 2 2006.238.07:47:28.02#ibcon#about to write, iclass 13, count 2 2006.238.07:47:28.02#ibcon#wrote, iclass 13, count 2 2006.238.07:47:28.02#ibcon#about to read 3, iclass 13, count 2 2006.238.07:47:28.04#ibcon#read 3, iclass 13, count 2 2006.238.07:47:28.04#ibcon#about to read 4, iclass 13, count 2 2006.238.07:47:28.04#ibcon#read 4, iclass 13, count 2 2006.238.07:47:28.04#ibcon#about to read 5, iclass 13, count 2 2006.238.07:47:28.04#ibcon#read 5, iclass 13, count 2 2006.238.07:47:28.04#ibcon#about to read 6, iclass 13, count 2 2006.238.07:47:28.04#ibcon#read 6, iclass 13, count 2 2006.238.07:47:28.04#ibcon#end of sib2, iclass 13, count 2 2006.238.07:47:28.04#ibcon#*mode == 0, iclass 13, count 2 2006.238.07:47:28.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.07:47:28.04#ibcon#[25=AT01-08\r\n] 2006.238.07:47:28.04#ibcon#*before write, iclass 13, count 2 2006.238.07:47:28.04#ibcon#enter sib2, iclass 13, count 2 2006.238.07:47:28.04#ibcon#flushed, iclass 13, count 2 2006.238.07:47:28.04#ibcon#about to write, iclass 13, count 2 2006.238.07:47:28.04#ibcon#wrote, iclass 13, count 2 2006.238.07:47:28.04#ibcon#about to read 3, iclass 13, count 2 2006.238.07:47:28.07#ibcon#read 3, iclass 13, count 2 2006.238.07:47:28.07#ibcon#about to read 4, iclass 13, count 2 2006.238.07:47:28.07#ibcon#read 4, iclass 13, count 2 2006.238.07:47:28.07#ibcon#about to read 5, iclass 13, count 2 2006.238.07:47:28.07#ibcon#read 5, iclass 13, count 2 2006.238.07:47:28.07#ibcon#about to read 6, iclass 13, count 2 2006.238.07:47:28.07#ibcon#read 6, iclass 13, count 2 2006.238.07:47:28.07#ibcon#end of sib2, iclass 13, count 2 2006.238.07:47:28.07#ibcon#*after write, iclass 13, count 2 2006.238.07:47:28.07#ibcon#*before return 0, iclass 13, count 2 2006.238.07:47:28.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:47:28.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:47:28.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.07:47:28.07#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:28.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:47:28.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:47:28.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:47:28.19#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:47:28.19#ibcon#first serial, iclass 13, count 0 2006.238.07:47:28.19#ibcon#enter sib2, iclass 13, count 0 2006.238.07:47:28.19#ibcon#flushed, iclass 13, count 0 2006.238.07:47:28.19#ibcon#about to write, iclass 13, count 0 2006.238.07:47:28.19#ibcon#wrote, iclass 13, count 0 2006.238.07:47:28.19#ibcon#about to read 3, iclass 13, count 0 2006.238.07:47:28.21#ibcon#read 3, iclass 13, count 0 2006.238.07:47:28.21#ibcon#about to read 4, iclass 13, count 0 2006.238.07:47:28.21#ibcon#read 4, iclass 13, count 0 2006.238.07:47:28.21#ibcon#about to read 5, iclass 13, count 0 2006.238.07:47:28.21#ibcon#read 5, iclass 13, count 0 2006.238.07:47:28.21#ibcon#about to read 6, iclass 13, count 0 2006.238.07:47:28.21#ibcon#read 6, iclass 13, count 0 2006.238.07:47:28.21#ibcon#end of sib2, iclass 13, count 0 2006.238.07:47:28.21#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:47:28.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:47:28.21#ibcon#[25=USB\r\n] 2006.238.07:47:28.21#ibcon#*before write, iclass 13, count 0 2006.238.07:47:28.21#ibcon#enter sib2, iclass 13, count 0 2006.238.07:47:28.21#ibcon#flushed, iclass 13, count 0 2006.238.07:47:28.21#ibcon#about to write, iclass 13, count 0 2006.238.07:47:28.21#ibcon#wrote, iclass 13, count 0 2006.238.07:47:28.21#ibcon#about to read 3, iclass 13, count 0 2006.238.07:47:28.24#ibcon#read 3, iclass 13, count 0 2006.238.07:47:28.24#ibcon#about to read 4, iclass 13, count 0 2006.238.07:47:28.24#ibcon#read 4, iclass 13, count 0 2006.238.07:47:28.24#ibcon#about to read 5, iclass 13, count 0 2006.238.07:47:28.24#ibcon#read 5, iclass 13, count 0 2006.238.07:47:28.24#ibcon#about to read 6, iclass 13, count 0 2006.238.07:47:28.24#ibcon#read 6, iclass 13, count 0 2006.238.07:47:28.24#ibcon#end of sib2, iclass 13, count 0 2006.238.07:47:28.24#ibcon#*after write, iclass 13, count 0 2006.238.07:47:28.24#ibcon#*before return 0, iclass 13, count 0 2006.238.07:47:28.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:47:28.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:47:28.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:47:28.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:47:28.24$vc4f8/valo=2,572.99 2006.238.07:47:28.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.07:47:28.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.07:47:28.24#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:28.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:47:28.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:47:28.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:47:28.24#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:47:28.24#ibcon#first serial, iclass 15, count 0 2006.238.07:47:28.24#ibcon#enter sib2, iclass 15, count 0 2006.238.07:47:28.24#ibcon#flushed, iclass 15, count 0 2006.238.07:47:28.24#ibcon#about to write, iclass 15, count 0 2006.238.07:47:28.24#ibcon#wrote, iclass 15, count 0 2006.238.07:47:28.24#ibcon#about to read 3, iclass 15, count 0 2006.238.07:47:28.26#ibcon#read 3, iclass 15, count 0 2006.238.07:47:28.26#ibcon#about to read 4, iclass 15, count 0 2006.238.07:47:28.26#ibcon#read 4, iclass 15, count 0 2006.238.07:47:28.26#ibcon#about to read 5, iclass 15, count 0 2006.238.07:47:28.26#ibcon#read 5, iclass 15, count 0 2006.238.07:47:28.26#ibcon#about to read 6, iclass 15, count 0 2006.238.07:47:28.26#ibcon#read 6, iclass 15, count 0 2006.238.07:47:28.26#ibcon#end of sib2, iclass 15, count 0 2006.238.07:47:28.26#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:47:28.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:47:28.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:47:28.26#ibcon#*before write, iclass 15, count 0 2006.238.07:47:28.26#ibcon#enter sib2, iclass 15, count 0 2006.238.07:47:28.26#ibcon#flushed, iclass 15, count 0 2006.238.07:47:28.26#ibcon#about to write, iclass 15, count 0 2006.238.07:47:28.26#ibcon#wrote, iclass 15, count 0 2006.238.07:47:28.26#ibcon#about to read 3, iclass 15, count 0 2006.238.07:47:28.30#ibcon#read 3, iclass 15, count 0 2006.238.07:47:28.30#ibcon#about to read 4, iclass 15, count 0 2006.238.07:47:28.30#ibcon#read 4, iclass 15, count 0 2006.238.07:47:28.30#ibcon#about to read 5, iclass 15, count 0 2006.238.07:47:28.30#ibcon#read 5, iclass 15, count 0 2006.238.07:47:28.30#ibcon#about to read 6, iclass 15, count 0 2006.238.07:47:28.30#ibcon#read 6, iclass 15, count 0 2006.238.07:47:28.30#ibcon#end of sib2, iclass 15, count 0 2006.238.07:47:28.30#ibcon#*after write, iclass 15, count 0 2006.238.07:47:28.30#ibcon#*before return 0, iclass 15, count 0 2006.238.07:47:28.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:47:28.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:47:28.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:47:28.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:47:28.30$vc4f8/va=2,7 2006.238.07:47:28.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.07:47:28.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.07:47:28.30#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:28.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:47:28.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:47:28.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:47:28.36#ibcon#enter wrdev, iclass 17, count 2 2006.238.07:47:28.36#ibcon#first serial, iclass 17, count 2 2006.238.07:47:28.36#ibcon#enter sib2, iclass 17, count 2 2006.238.07:47:28.36#ibcon#flushed, iclass 17, count 2 2006.238.07:47:28.36#ibcon#about to write, iclass 17, count 2 2006.238.07:47:28.36#ibcon#wrote, iclass 17, count 2 2006.238.07:47:28.36#ibcon#about to read 3, iclass 17, count 2 2006.238.07:47:28.38#ibcon#read 3, iclass 17, count 2 2006.238.07:47:28.38#ibcon#about to read 4, iclass 17, count 2 2006.238.07:47:28.38#ibcon#read 4, iclass 17, count 2 2006.238.07:47:28.38#ibcon#about to read 5, iclass 17, count 2 2006.238.07:47:28.38#ibcon#read 5, iclass 17, count 2 2006.238.07:47:28.38#ibcon#about to read 6, iclass 17, count 2 2006.238.07:47:28.38#ibcon#read 6, iclass 17, count 2 2006.238.07:47:28.38#ibcon#end of sib2, iclass 17, count 2 2006.238.07:47:28.38#ibcon#*mode == 0, iclass 17, count 2 2006.238.07:47:28.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.07:47:28.38#ibcon#[25=AT02-07\r\n] 2006.238.07:47:28.38#ibcon#*before write, iclass 17, count 2 2006.238.07:47:28.38#ibcon#enter sib2, iclass 17, count 2 2006.238.07:47:28.38#ibcon#flushed, iclass 17, count 2 2006.238.07:47:28.38#ibcon#about to write, iclass 17, count 2 2006.238.07:47:28.38#ibcon#wrote, iclass 17, count 2 2006.238.07:47:28.38#ibcon#about to read 3, iclass 17, count 2 2006.238.07:47:28.41#ibcon#read 3, iclass 17, count 2 2006.238.07:47:28.41#ibcon#about to read 4, iclass 17, count 2 2006.238.07:47:28.41#ibcon#read 4, iclass 17, count 2 2006.238.07:47:28.41#ibcon#about to read 5, iclass 17, count 2 2006.238.07:47:28.41#ibcon#read 5, iclass 17, count 2 2006.238.07:47:28.41#ibcon#about to read 6, iclass 17, count 2 2006.238.07:47:28.41#ibcon#read 6, iclass 17, count 2 2006.238.07:47:28.41#ibcon#end of sib2, iclass 17, count 2 2006.238.07:47:28.41#ibcon#*after write, iclass 17, count 2 2006.238.07:47:28.41#ibcon#*before return 0, iclass 17, count 2 2006.238.07:47:28.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:47:28.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:47:28.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.07:47:28.41#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:28.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:47:28.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:47:28.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:47:28.53#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:47:28.53#ibcon#first serial, iclass 17, count 0 2006.238.07:47:28.53#ibcon#enter sib2, iclass 17, count 0 2006.238.07:47:28.53#ibcon#flushed, iclass 17, count 0 2006.238.07:47:28.53#ibcon#about to write, iclass 17, count 0 2006.238.07:47:28.53#ibcon#wrote, iclass 17, count 0 2006.238.07:47:28.53#ibcon#about to read 3, iclass 17, count 0 2006.238.07:47:28.55#ibcon#read 3, iclass 17, count 0 2006.238.07:47:28.55#ibcon#about to read 4, iclass 17, count 0 2006.238.07:47:28.55#ibcon#read 4, iclass 17, count 0 2006.238.07:47:28.55#ibcon#about to read 5, iclass 17, count 0 2006.238.07:47:28.55#ibcon#read 5, iclass 17, count 0 2006.238.07:47:28.55#ibcon#about to read 6, iclass 17, count 0 2006.238.07:47:28.55#ibcon#read 6, iclass 17, count 0 2006.238.07:47:28.55#ibcon#end of sib2, iclass 17, count 0 2006.238.07:47:28.55#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:47:28.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:47:28.55#ibcon#[25=USB\r\n] 2006.238.07:47:28.55#ibcon#*before write, iclass 17, count 0 2006.238.07:47:28.55#ibcon#enter sib2, iclass 17, count 0 2006.238.07:47:28.55#ibcon#flushed, iclass 17, count 0 2006.238.07:47:28.55#ibcon#about to write, iclass 17, count 0 2006.238.07:47:28.55#ibcon#wrote, iclass 17, count 0 2006.238.07:47:28.55#ibcon#about to read 3, iclass 17, count 0 2006.238.07:47:28.58#ibcon#read 3, iclass 17, count 0 2006.238.07:47:28.58#ibcon#about to read 4, iclass 17, count 0 2006.238.07:47:28.58#ibcon#read 4, iclass 17, count 0 2006.238.07:47:28.58#ibcon#about to read 5, iclass 17, count 0 2006.238.07:47:28.58#ibcon#read 5, iclass 17, count 0 2006.238.07:47:28.58#ibcon#about to read 6, iclass 17, count 0 2006.238.07:47:28.58#ibcon#read 6, iclass 17, count 0 2006.238.07:47:28.58#ibcon#end of sib2, iclass 17, count 0 2006.238.07:47:28.58#ibcon#*after write, iclass 17, count 0 2006.238.07:47:28.58#ibcon#*before return 0, iclass 17, count 0 2006.238.07:47:28.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:47:28.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:47:28.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:47:28.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:47:28.58$vc4f8/valo=3,672.99 2006.238.07:47:28.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.07:47:28.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.07:47:28.58#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:28.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:47:28.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:47:28.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:47:28.58#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:47:28.58#ibcon#first serial, iclass 19, count 0 2006.238.07:47:28.58#ibcon#enter sib2, iclass 19, count 0 2006.238.07:47:28.58#ibcon#flushed, iclass 19, count 0 2006.238.07:47:28.58#ibcon#about to write, iclass 19, count 0 2006.238.07:47:28.58#ibcon#wrote, iclass 19, count 0 2006.238.07:47:28.58#ibcon#about to read 3, iclass 19, count 0 2006.238.07:47:28.60#ibcon#read 3, iclass 19, count 0 2006.238.07:47:28.60#ibcon#about to read 4, iclass 19, count 0 2006.238.07:47:28.60#ibcon#read 4, iclass 19, count 0 2006.238.07:47:28.60#ibcon#about to read 5, iclass 19, count 0 2006.238.07:47:28.60#ibcon#read 5, iclass 19, count 0 2006.238.07:47:28.60#ibcon#about to read 6, iclass 19, count 0 2006.238.07:47:28.60#ibcon#read 6, iclass 19, count 0 2006.238.07:47:28.60#ibcon#end of sib2, iclass 19, count 0 2006.238.07:47:28.60#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:47:28.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:47:28.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:47:28.60#ibcon#*before write, iclass 19, count 0 2006.238.07:47:28.60#ibcon#enter sib2, iclass 19, count 0 2006.238.07:47:28.60#ibcon#flushed, iclass 19, count 0 2006.238.07:47:28.60#ibcon#about to write, iclass 19, count 0 2006.238.07:47:28.60#ibcon#wrote, iclass 19, count 0 2006.238.07:47:28.60#ibcon#about to read 3, iclass 19, count 0 2006.238.07:47:28.64#ibcon#read 3, iclass 19, count 0 2006.238.07:47:28.64#ibcon#about to read 4, iclass 19, count 0 2006.238.07:47:28.64#ibcon#read 4, iclass 19, count 0 2006.238.07:47:28.64#ibcon#about to read 5, iclass 19, count 0 2006.238.07:47:28.64#ibcon#read 5, iclass 19, count 0 2006.238.07:47:28.64#ibcon#about to read 6, iclass 19, count 0 2006.238.07:47:28.64#ibcon#read 6, iclass 19, count 0 2006.238.07:47:28.64#ibcon#end of sib2, iclass 19, count 0 2006.238.07:47:28.64#ibcon#*after write, iclass 19, count 0 2006.238.07:47:28.64#ibcon#*before return 0, iclass 19, count 0 2006.238.07:47:28.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:47:28.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:47:28.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:47:28.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:47:28.64$vc4f8/va=3,7 2006.238.07:47:28.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.07:47:28.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.07:47:28.64#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:28.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:47:28.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:47:28.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:47:28.70#ibcon#enter wrdev, iclass 21, count 2 2006.238.07:47:28.70#ibcon#first serial, iclass 21, count 2 2006.238.07:47:28.70#ibcon#enter sib2, iclass 21, count 2 2006.238.07:47:28.70#ibcon#flushed, iclass 21, count 2 2006.238.07:47:28.70#ibcon#about to write, iclass 21, count 2 2006.238.07:47:28.70#ibcon#wrote, iclass 21, count 2 2006.238.07:47:28.70#ibcon#about to read 3, iclass 21, count 2 2006.238.07:47:28.72#ibcon#read 3, iclass 21, count 2 2006.238.07:47:28.72#ibcon#about to read 4, iclass 21, count 2 2006.238.07:47:28.72#ibcon#read 4, iclass 21, count 2 2006.238.07:47:28.72#ibcon#about to read 5, iclass 21, count 2 2006.238.07:47:28.72#ibcon#read 5, iclass 21, count 2 2006.238.07:47:28.72#ibcon#about to read 6, iclass 21, count 2 2006.238.07:47:28.72#ibcon#read 6, iclass 21, count 2 2006.238.07:47:28.72#ibcon#end of sib2, iclass 21, count 2 2006.238.07:47:28.72#ibcon#*mode == 0, iclass 21, count 2 2006.238.07:47:28.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.07:47:28.72#ibcon#[25=AT03-07\r\n] 2006.238.07:47:28.72#ibcon#*before write, iclass 21, count 2 2006.238.07:47:28.72#ibcon#enter sib2, iclass 21, count 2 2006.238.07:47:28.72#ibcon#flushed, iclass 21, count 2 2006.238.07:47:28.72#ibcon#about to write, iclass 21, count 2 2006.238.07:47:28.72#ibcon#wrote, iclass 21, count 2 2006.238.07:47:28.72#ibcon#about to read 3, iclass 21, count 2 2006.238.07:47:28.75#ibcon#read 3, iclass 21, count 2 2006.238.07:47:28.75#ibcon#about to read 4, iclass 21, count 2 2006.238.07:47:28.75#ibcon#read 4, iclass 21, count 2 2006.238.07:47:28.75#ibcon#about to read 5, iclass 21, count 2 2006.238.07:47:28.75#ibcon#read 5, iclass 21, count 2 2006.238.07:47:28.75#ibcon#about to read 6, iclass 21, count 2 2006.238.07:47:28.75#ibcon#read 6, iclass 21, count 2 2006.238.07:47:28.75#ibcon#end of sib2, iclass 21, count 2 2006.238.07:47:28.75#ibcon#*after write, iclass 21, count 2 2006.238.07:47:28.75#ibcon#*before return 0, iclass 21, count 2 2006.238.07:47:28.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:47:28.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:47:28.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.07:47:28.75#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:28.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:47:28.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:47:28.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:47:28.87#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:47:28.87#ibcon#first serial, iclass 21, count 0 2006.238.07:47:28.87#ibcon#enter sib2, iclass 21, count 0 2006.238.07:47:28.87#ibcon#flushed, iclass 21, count 0 2006.238.07:47:28.87#ibcon#about to write, iclass 21, count 0 2006.238.07:47:28.87#ibcon#wrote, iclass 21, count 0 2006.238.07:47:28.87#ibcon#about to read 3, iclass 21, count 0 2006.238.07:47:28.89#ibcon#read 3, iclass 21, count 0 2006.238.07:47:28.89#ibcon#about to read 4, iclass 21, count 0 2006.238.07:47:28.89#ibcon#read 4, iclass 21, count 0 2006.238.07:47:28.89#ibcon#about to read 5, iclass 21, count 0 2006.238.07:47:28.89#ibcon#read 5, iclass 21, count 0 2006.238.07:47:28.89#ibcon#about to read 6, iclass 21, count 0 2006.238.07:47:28.89#ibcon#read 6, iclass 21, count 0 2006.238.07:47:28.89#ibcon#end of sib2, iclass 21, count 0 2006.238.07:47:28.89#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:47:28.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:47:28.89#ibcon#[25=USB\r\n] 2006.238.07:47:28.89#ibcon#*before write, iclass 21, count 0 2006.238.07:47:28.89#ibcon#enter sib2, iclass 21, count 0 2006.238.07:47:28.89#ibcon#flushed, iclass 21, count 0 2006.238.07:47:28.89#ibcon#about to write, iclass 21, count 0 2006.238.07:47:28.89#ibcon#wrote, iclass 21, count 0 2006.238.07:47:28.89#ibcon#about to read 3, iclass 21, count 0 2006.238.07:47:28.92#ibcon#read 3, iclass 21, count 0 2006.238.07:47:28.92#ibcon#about to read 4, iclass 21, count 0 2006.238.07:47:28.92#ibcon#read 4, iclass 21, count 0 2006.238.07:47:28.92#ibcon#about to read 5, iclass 21, count 0 2006.238.07:47:28.92#ibcon#read 5, iclass 21, count 0 2006.238.07:47:28.92#ibcon#about to read 6, iclass 21, count 0 2006.238.07:47:28.92#ibcon#read 6, iclass 21, count 0 2006.238.07:47:28.92#ibcon#end of sib2, iclass 21, count 0 2006.238.07:47:28.92#ibcon#*after write, iclass 21, count 0 2006.238.07:47:28.92#ibcon#*before return 0, iclass 21, count 0 2006.238.07:47:28.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:47:28.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:47:28.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:47:28.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:47:28.92$vc4f8/valo=4,832.99 2006.238.07:47:28.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:47:28.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:47:28.92#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:28.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:47:28.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:47:28.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:47:28.92#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:47:28.92#ibcon#first serial, iclass 23, count 0 2006.238.07:47:28.92#ibcon#enter sib2, iclass 23, count 0 2006.238.07:47:28.92#ibcon#flushed, iclass 23, count 0 2006.238.07:47:28.92#ibcon#about to write, iclass 23, count 0 2006.238.07:47:28.92#ibcon#wrote, iclass 23, count 0 2006.238.07:47:28.92#ibcon#about to read 3, iclass 23, count 0 2006.238.07:47:28.94#ibcon#read 3, iclass 23, count 0 2006.238.07:47:28.94#ibcon#about to read 4, iclass 23, count 0 2006.238.07:47:28.94#ibcon#read 4, iclass 23, count 0 2006.238.07:47:28.94#ibcon#about to read 5, iclass 23, count 0 2006.238.07:47:28.94#ibcon#read 5, iclass 23, count 0 2006.238.07:47:28.94#ibcon#about to read 6, iclass 23, count 0 2006.238.07:47:28.94#ibcon#read 6, iclass 23, count 0 2006.238.07:47:28.94#ibcon#end of sib2, iclass 23, count 0 2006.238.07:47:28.94#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:47:28.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:47:28.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:47:28.94#ibcon#*before write, iclass 23, count 0 2006.238.07:47:28.94#ibcon#enter sib2, iclass 23, count 0 2006.238.07:47:28.94#ibcon#flushed, iclass 23, count 0 2006.238.07:47:28.94#ibcon#about to write, iclass 23, count 0 2006.238.07:47:28.94#ibcon#wrote, iclass 23, count 0 2006.238.07:47:28.94#ibcon#about to read 3, iclass 23, count 0 2006.238.07:47:28.98#ibcon#read 3, iclass 23, count 0 2006.238.07:47:28.98#ibcon#about to read 4, iclass 23, count 0 2006.238.07:47:28.98#ibcon#read 4, iclass 23, count 0 2006.238.07:47:28.98#ibcon#about to read 5, iclass 23, count 0 2006.238.07:47:28.98#ibcon#read 5, iclass 23, count 0 2006.238.07:47:28.98#ibcon#about to read 6, iclass 23, count 0 2006.238.07:47:28.98#ibcon#read 6, iclass 23, count 0 2006.238.07:47:28.98#ibcon#end of sib2, iclass 23, count 0 2006.238.07:47:28.98#ibcon#*after write, iclass 23, count 0 2006.238.07:47:28.98#ibcon#*before return 0, iclass 23, count 0 2006.238.07:47:28.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:47:28.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:47:28.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:47:28.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:47:28.98$vc4f8/va=4,7 2006.238.07:47:28.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.07:47:28.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.07:47:28.98#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:28.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:47:29.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:47:29.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:47:29.04#ibcon#enter wrdev, iclass 25, count 2 2006.238.07:47:29.04#ibcon#first serial, iclass 25, count 2 2006.238.07:47:29.04#ibcon#enter sib2, iclass 25, count 2 2006.238.07:47:29.04#ibcon#flushed, iclass 25, count 2 2006.238.07:47:29.04#ibcon#about to write, iclass 25, count 2 2006.238.07:47:29.04#ibcon#wrote, iclass 25, count 2 2006.238.07:47:29.04#ibcon#about to read 3, iclass 25, count 2 2006.238.07:47:29.06#ibcon#read 3, iclass 25, count 2 2006.238.07:47:29.06#ibcon#about to read 4, iclass 25, count 2 2006.238.07:47:29.06#ibcon#read 4, iclass 25, count 2 2006.238.07:47:29.06#ibcon#about to read 5, iclass 25, count 2 2006.238.07:47:29.06#ibcon#read 5, iclass 25, count 2 2006.238.07:47:29.06#ibcon#about to read 6, iclass 25, count 2 2006.238.07:47:29.06#ibcon#read 6, iclass 25, count 2 2006.238.07:47:29.06#ibcon#end of sib2, iclass 25, count 2 2006.238.07:47:29.06#ibcon#*mode == 0, iclass 25, count 2 2006.238.07:47:29.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.07:47:29.06#ibcon#[25=AT04-07\r\n] 2006.238.07:47:29.06#ibcon#*before write, iclass 25, count 2 2006.238.07:47:29.06#ibcon#enter sib2, iclass 25, count 2 2006.238.07:47:29.06#ibcon#flushed, iclass 25, count 2 2006.238.07:47:29.06#ibcon#about to write, iclass 25, count 2 2006.238.07:47:29.06#ibcon#wrote, iclass 25, count 2 2006.238.07:47:29.06#ibcon#about to read 3, iclass 25, count 2 2006.238.07:47:29.09#ibcon#read 3, iclass 25, count 2 2006.238.07:47:29.09#ibcon#about to read 4, iclass 25, count 2 2006.238.07:47:29.09#ibcon#read 4, iclass 25, count 2 2006.238.07:47:29.09#ibcon#about to read 5, iclass 25, count 2 2006.238.07:47:29.09#ibcon#read 5, iclass 25, count 2 2006.238.07:47:29.09#ibcon#about to read 6, iclass 25, count 2 2006.238.07:47:29.09#ibcon#read 6, iclass 25, count 2 2006.238.07:47:29.09#ibcon#end of sib2, iclass 25, count 2 2006.238.07:47:29.09#ibcon#*after write, iclass 25, count 2 2006.238.07:47:29.09#ibcon#*before return 0, iclass 25, count 2 2006.238.07:47:29.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:47:29.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:47:29.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.07:47:29.09#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:29.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:47:29.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:47:29.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:47:29.21#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:47:29.21#ibcon#first serial, iclass 25, count 0 2006.238.07:47:29.21#ibcon#enter sib2, iclass 25, count 0 2006.238.07:47:29.21#ibcon#flushed, iclass 25, count 0 2006.238.07:47:29.21#ibcon#about to write, iclass 25, count 0 2006.238.07:47:29.21#ibcon#wrote, iclass 25, count 0 2006.238.07:47:29.21#ibcon#about to read 3, iclass 25, count 0 2006.238.07:47:29.23#ibcon#read 3, iclass 25, count 0 2006.238.07:47:29.23#ibcon#about to read 4, iclass 25, count 0 2006.238.07:47:29.23#ibcon#read 4, iclass 25, count 0 2006.238.07:47:29.23#ibcon#about to read 5, iclass 25, count 0 2006.238.07:47:29.23#ibcon#read 5, iclass 25, count 0 2006.238.07:47:29.23#ibcon#about to read 6, iclass 25, count 0 2006.238.07:47:29.23#ibcon#read 6, iclass 25, count 0 2006.238.07:47:29.23#ibcon#end of sib2, iclass 25, count 0 2006.238.07:47:29.23#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:47:29.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:47:29.23#ibcon#[25=USB\r\n] 2006.238.07:47:29.23#ibcon#*before write, iclass 25, count 0 2006.238.07:47:29.23#ibcon#enter sib2, iclass 25, count 0 2006.238.07:47:29.23#ibcon#flushed, iclass 25, count 0 2006.238.07:47:29.23#ibcon#about to write, iclass 25, count 0 2006.238.07:47:29.23#ibcon#wrote, iclass 25, count 0 2006.238.07:47:29.23#ibcon#about to read 3, iclass 25, count 0 2006.238.07:47:29.26#ibcon#read 3, iclass 25, count 0 2006.238.07:47:29.26#ibcon#about to read 4, iclass 25, count 0 2006.238.07:47:29.26#ibcon#read 4, iclass 25, count 0 2006.238.07:47:29.26#ibcon#about to read 5, iclass 25, count 0 2006.238.07:47:29.26#ibcon#read 5, iclass 25, count 0 2006.238.07:47:29.26#ibcon#about to read 6, iclass 25, count 0 2006.238.07:47:29.26#ibcon#read 6, iclass 25, count 0 2006.238.07:47:29.26#ibcon#end of sib2, iclass 25, count 0 2006.238.07:47:29.26#ibcon#*after write, iclass 25, count 0 2006.238.07:47:29.26#ibcon#*before return 0, iclass 25, count 0 2006.238.07:47:29.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:47:29.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:47:29.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:47:29.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:47:29.26$vc4f8/valo=5,652.99 2006.238.07:47:29.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:47:29.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:47:29.26#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:29.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:47:29.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:47:29.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:47:29.26#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:47:29.26#ibcon#first serial, iclass 27, count 0 2006.238.07:47:29.26#ibcon#enter sib2, iclass 27, count 0 2006.238.07:47:29.26#ibcon#flushed, iclass 27, count 0 2006.238.07:47:29.26#ibcon#about to write, iclass 27, count 0 2006.238.07:47:29.26#ibcon#wrote, iclass 27, count 0 2006.238.07:47:29.26#ibcon#about to read 3, iclass 27, count 0 2006.238.07:47:29.28#ibcon#read 3, iclass 27, count 0 2006.238.07:47:29.28#ibcon#about to read 4, iclass 27, count 0 2006.238.07:47:29.28#ibcon#read 4, iclass 27, count 0 2006.238.07:47:29.28#ibcon#about to read 5, iclass 27, count 0 2006.238.07:47:29.28#ibcon#read 5, iclass 27, count 0 2006.238.07:47:29.28#ibcon#about to read 6, iclass 27, count 0 2006.238.07:47:29.28#ibcon#read 6, iclass 27, count 0 2006.238.07:47:29.28#ibcon#end of sib2, iclass 27, count 0 2006.238.07:47:29.28#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:47:29.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:47:29.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:47:29.28#ibcon#*before write, iclass 27, count 0 2006.238.07:47:29.28#ibcon#enter sib2, iclass 27, count 0 2006.238.07:47:29.28#ibcon#flushed, iclass 27, count 0 2006.238.07:47:29.28#ibcon#about to write, iclass 27, count 0 2006.238.07:47:29.28#ibcon#wrote, iclass 27, count 0 2006.238.07:47:29.28#ibcon#about to read 3, iclass 27, count 0 2006.238.07:47:29.32#ibcon#read 3, iclass 27, count 0 2006.238.07:47:29.32#ibcon#about to read 4, iclass 27, count 0 2006.238.07:47:29.32#ibcon#read 4, iclass 27, count 0 2006.238.07:47:29.32#ibcon#about to read 5, iclass 27, count 0 2006.238.07:47:29.32#ibcon#read 5, iclass 27, count 0 2006.238.07:47:29.32#ibcon#about to read 6, iclass 27, count 0 2006.238.07:47:29.32#ibcon#read 6, iclass 27, count 0 2006.238.07:47:29.32#ibcon#end of sib2, iclass 27, count 0 2006.238.07:47:29.32#ibcon#*after write, iclass 27, count 0 2006.238.07:47:29.32#ibcon#*before return 0, iclass 27, count 0 2006.238.07:47:29.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:47:29.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:47:29.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:47:29.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:47:29.32$vc4f8/va=5,8 2006.238.07:47:29.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.07:47:29.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.07:47:29.32#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:29.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:47:29.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:47:29.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:47:29.38#ibcon#enter wrdev, iclass 29, count 2 2006.238.07:47:29.38#ibcon#first serial, iclass 29, count 2 2006.238.07:47:29.38#ibcon#enter sib2, iclass 29, count 2 2006.238.07:47:29.38#ibcon#flushed, iclass 29, count 2 2006.238.07:47:29.38#ibcon#about to write, iclass 29, count 2 2006.238.07:47:29.38#ibcon#wrote, iclass 29, count 2 2006.238.07:47:29.38#ibcon#about to read 3, iclass 29, count 2 2006.238.07:47:29.40#ibcon#read 3, iclass 29, count 2 2006.238.07:47:29.40#ibcon#about to read 4, iclass 29, count 2 2006.238.07:47:29.40#ibcon#read 4, iclass 29, count 2 2006.238.07:47:29.40#ibcon#about to read 5, iclass 29, count 2 2006.238.07:47:29.40#ibcon#read 5, iclass 29, count 2 2006.238.07:47:29.40#ibcon#about to read 6, iclass 29, count 2 2006.238.07:47:29.40#ibcon#read 6, iclass 29, count 2 2006.238.07:47:29.40#ibcon#end of sib2, iclass 29, count 2 2006.238.07:47:29.40#ibcon#*mode == 0, iclass 29, count 2 2006.238.07:47:29.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.07:47:29.40#ibcon#[25=AT05-08\r\n] 2006.238.07:47:29.40#ibcon#*before write, iclass 29, count 2 2006.238.07:47:29.40#ibcon#enter sib2, iclass 29, count 2 2006.238.07:47:29.40#ibcon#flushed, iclass 29, count 2 2006.238.07:47:29.40#ibcon#about to write, iclass 29, count 2 2006.238.07:47:29.40#ibcon#wrote, iclass 29, count 2 2006.238.07:47:29.40#ibcon#about to read 3, iclass 29, count 2 2006.238.07:47:29.43#ibcon#read 3, iclass 29, count 2 2006.238.07:47:29.43#ibcon#about to read 4, iclass 29, count 2 2006.238.07:47:29.43#ibcon#read 4, iclass 29, count 2 2006.238.07:47:29.43#ibcon#about to read 5, iclass 29, count 2 2006.238.07:47:29.43#ibcon#read 5, iclass 29, count 2 2006.238.07:47:29.43#ibcon#about to read 6, iclass 29, count 2 2006.238.07:47:29.43#ibcon#read 6, iclass 29, count 2 2006.238.07:47:29.43#ibcon#end of sib2, iclass 29, count 2 2006.238.07:47:29.43#ibcon#*after write, iclass 29, count 2 2006.238.07:47:29.43#ibcon#*before return 0, iclass 29, count 2 2006.238.07:47:29.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:47:29.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:47:29.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.07:47:29.43#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:29.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:47:29.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:47:29.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:47:29.55#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:47:29.55#ibcon#first serial, iclass 29, count 0 2006.238.07:47:29.55#ibcon#enter sib2, iclass 29, count 0 2006.238.07:47:29.55#ibcon#flushed, iclass 29, count 0 2006.238.07:47:29.55#ibcon#about to write, iclass 29, count 0 2006.238.07:47:29.55#ibcon#wrote, iclass 29, count 0 2006.238.07:47:29.55#ibcon#about to read 3, iclass 29, count 0 2006.238.07:47:29.57#ibcon#read 3, iclass 29, count 0 2006.238.07:47:29.57#ibcon#about to read 4, iclass 29, count 0 2006.238.07:47:29.57#ibcon#read 4, iclass 29, count 0 2006.238.07:47:29.57#ibcon#about to read 5, iclass 29, count 0 2006.238.07:47:29.57#ibcon#read 5, iclass 29, count 0 2006.238.07:47:29.57#ibcon#about to read 6, iclass 29, count 0 2006.238.07:47:29.57#ibcon#read 6, iclass 29, count 0 2006.238.07:47:29.57#ibcon#end of sib2, iclass 29, count 0 2006.238.07:47:29.57#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:47:29.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:47:29.57#ibcon#[25=USB\r\n] 2006.238.07:47:29.57#ibcon#*before write, iclass 29, count 0 2006.238.07:47:29.57#ibcon#enter sib2, iclass 29, count 0 2006.238.07:47:29.57#ibcon#flushed, iclass 29, count 0 2006.238.07:47:29.57#ibcon#about to write, iclass 29, count 0 2006.238.07:47:29.57#ibcon#wrote, iclass 29, count 0 2006.238.07:47:29.57#ibcon#about to read 3, iclass 29, count 0 2006.238.07:47:29.61#ibcon#read 3, iclass 29, count 0 2006.238.07:47:29.61#ibcon#about to read 4, iclass 29, count 0 2006.238.07:47:29.61#ibcon#read 4, iclass 29, count 0 2006.238.07:47:29.61#ibcon#about to read 5, iclass 29, count 0 2006.238.07:47:29.61#ibcon#read 5, iclass 29, count 0 2006.238.07:47:29.61#ibcon#about to read 6, iclass 29, count 0 2006.238.07:47:29.61#ibcon#read 6, iclass 29, count 0 2006.238.07:47:29.61#ibcon#end of sib2, iclass 29, count 0 2006.238.07:47:29.61#ibcon#*after write, iclass 29, count 0 2006.238.07:47:29.61#ibcon#*before return 0, iclass 29, count 0 2006.238.07:47:29.61#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:47:29.61#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:47:29.61#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:47:29.61#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:47:29.61$vc4f8/valo=6,772.99 2006.238.07:47:29.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.07:47:29.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.07:47:29.61#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:29.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:47:29.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:47:29.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:47:29.61#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:47:29.61#ibcon#first serial, iclass 31, count 0 2006.238.07:47:29.61#ibcon#enter sib2, iclass 31, count 0 2006.238.07:47:29.61#ibcon#flushed, iclass 31, count 0 2006.238.07:47:29.61#ibcon#about to write, iclass 31, count 0 2006.238.07:47:29.61#ibcon#wrote, iclass 31, count 0 2006.238.07:47:29.61#ibcon#about to read 3, iclass 31, count 0 2006.238.07:47:29.63#ibcon#read 3, iclass 31, count 0 2006.238.07:47:29.63#ibcon#about to read 4, iclass 31, count 0 2006.238.07:47:29.63#ibcon#read 4, iclass 31, count 0 2006.238.07:47:29.63#ibcon#about to read 5, iclass 31, count 0 2006.238.07:47:29.63#ibcon#read 5, iclass 31, count 0 2006.238.07:47:29.63#ibcon#about to read 6, iclass 31, count 0 2006.238.07:47:29.63#ibcon#read 6, iclass 31, count 0 2006.238.07:47:29.63#ibcon#end of sib2, iclass 31, count 0 2006.238.07:47:29.63#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:47:29.63#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:47:29.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:47:29.63#ibcon#*before write, iclass 31, count 0 2006.238.07:47:29.63#ibcon#enter sib2, iclass 31, count 0 2006.238.07:47:29.63#ibcon#flushed, iclass 31, count 0 2006.238.07:47:29.63#ibcon#about to write, iclass 31, count 0 2006.238.07:47:29.63#ibcon#wrote, iclass 31, count 0 2006.238.07:47:29.63#ibcon#about to read 3, iclass 31, count 0 2006.238.07:47:29.67#ibcon#read 3, iclass 31, count 0 2006.238.07:47:29.67#ibcon#about to read 4, iclass 31, count 0 2006.238.07:47:29.67#ibcon#read 4, iclass 31, count 0 2006.238.07:47:29.67#ibcon#about to read 5, iclass 31, count 0 2006.238.07:47:29.67#ibcon#read 5, iclass 31, count 0 2006.238.07:47:29.67#ibcon#about to read 6, iclass 31, count 0 2006.238.07:47:29.67#ibcon#read 6, iclass 31, count 0 2006.238.07:47:29.67#ibcon#end of sib2, iclass 31, count 0 2006.238.07:47:29.67#ibcon#*after write, iclass 31, count 0 2006.238.07:47:29.67#ibcon#*before return 0, iclass 31, count 0 2006.238.07:47:29.67#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:47:29.67#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:47:29.67#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:47:29.67#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:47:29.67$vc4f8/va=6,7 2006.238.07:47:29.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:47:29.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:47:29.67#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:29.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:47:29.73#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:47:29.73#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:47:29.73#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:47:29.73#ibcon#first serial, iclass 33, count 2 2006.238.07:47:29.73#ibcon#enter sib2, iclass 33, count 2 2006.238.07:47:29.73#ibcon#flushed, iclass 33, count 2 2006.238.07:47:29.73#ibcon#about to write, iclass 33, count 2 2006.238.07:47:29.73#ibcon#wrote, iclass 33, count 2 2006.238.07:47:29.73#ibcon#about to read 3, iclass 33, count 2 2006.238.07:47:29.75#ibcon#read 3, iclass 33, count 2 2006.238.07:47:29.75#ibcon#about to read 4, iclass 33, count 2 2006.238.07:47:29.75#ibcon#read 4, iclass 33, count 2 2006.238.07:47:29.75#ibcon#about to read 5, iclass 33, count 2 2006.238.07:47:29.75#ibcon#read 5, iclass 33, count 2 2006.238.07:47:29.75#ibcon#about to read 6, iclass 33, count 2 2006.238.07:47:29.75#ibcon#read 6, iclass 33, count 2 2006.238.07:47:29.75#ibcon#end of sib2, iclass 33, count 2 2006.238.07:47:29.75#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:47:29.75#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:47:29.75#ibcon#[25=AT06-07\r\n] 2006.238.07:47:29.75#ibcon#*before write, iclass 33, count 2 2006.238.07:47:29.75#ibcon#enter sib2, iclass 33, count 2 2006.238.07:47:29.75#ibcon#flushed, iclass 33, count 2 2006.238.07:47:29.75#ibcon#about to write, iclass 33, count 2 2006.238.07:47:29.75#ibcon#wrote, iclass 33, count 2 2006.238.07:47:29.75#ibcon#about to read 3, iclass 33, count 2 2006.238.07:47:29.78#ibcon#read 3, iclass 33, count 2 2006.238.07:47:29.78#ibcon#about to read 4, iclass 33, count 2 2006.238.07:47:29.78#ibcon#read 4, iclass 33, count 2 2006.238.07:47:29.78#ibcon#about to read 5, iclass 33, count 2 2006.238.07:47:29.78#ibcon#read 5, iclass 33, count 2 2006.238.07:47:29.78#ibcon#about to read 6, iclass 33, count 2 2006.238.07:47:29.78#ibcon#read 6, iclass 33, count 2 2006.238.07:47:29.78#ibcon#end of sib2, iclass 33, count 2 2006.238.07:47:29.78#ibcon#*after write, iclass 33, count 2 2006.238.07:47:29.78#ibcon#*before return 0, iclass 33, count 2 2006.238.07:47:29.78#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:47:29.78#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:47:29.78#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:47:29.78#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:29.78#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:47:29.90#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:47:29.90#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:47:29.90#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:47:29.90#ibcon#first serial, iclass 33, count 0 2006.238.07:47:29.90#ibcon#enter sib2, iclass 33, count 0 2006.238.07:47:29.90#ibcon#flushed, iclass 33, count 0 2006.238.07:47:29.90#ibcon#about to write, iclass 33, count 0 2006.238.07:47:29.90#ibcon#wrote, iclass 33, count 0 2006.238.07:47:29.90#ibcon#about to read 3, iclass 33, count 0 2006.238.07:47:29.92#ibcon#read 3, iclass 33, count 0 2006.238.07:47:29.92#ibcon#about to read 4, iclass 33, count 0 2006.238.07:47:29.92#ibcon#read 4, iclass 33, count 0 2006.238.07:47:29.92#ibcon#about to read 5, iclass 33, count 0 2006.238.07:47:29.92#ibcon#read 5, iclass 33, count 0 2006.238.07:47:29.92#ibcon#about to read 6, iclass 33, count 0 2006.238.07:47:29.92#ibcon#read 6, iclass 33, count 0 2006.238.07:47:29.92#ibcon#end of sib2, iclass 33, count 0 2006.238.07:47:29.92#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:47:29.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:47:29.92#ibcon#[25=USB\r\n] 2006.238.07:47:29.92#ibcon#*before write, iclass 33, count 0 2006.238.07:47:29.92#ibcon#enter sib2, iclass 33, count 0 2006.238.07:47:29.92#ibcon#flushed, iclass 33, count 0 2006.238.07:47:29.92#ibcon#about to write, iclass 33, count 0 2006.238.07:47:29.92#ibcon#wrote, iclass 33, count 0 2006.238.07:47:29.92#ibcon#about to read 3, iclass 33, count 0 2006.238.07:47:29.95#ibcon#read 3, iclass 33, count 0 2006.238.07:47:29.95#ibcon#about to read 4, iclass 33, count 0 2006.238.07:47:29.95#ibcon#read 4, iclass 33, count 0 2006.238.07:47:29.95#ibcon#about to read 5, iclass 33, count 0 2006.238.07:47:29.95#ibcon#read 5, iclass 33, count 0 2006.238.07:47:29.95#ibcon#about to read 6, iclass 33, count 0 2006.238.07:47:29.95#ibcon#read 6, iclass 33, count 0 2006.238.07:47:29.95#ibcon#end of sib2, iclass 33, count 0 2006.238.07:47:29.95#ibcon#*after write, iclass 33, count 0 2006.238.07:47:29.95#ibcon#*before return 0, iclass 33, count 0 2006.238.07:47:29.95#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:47:29.95#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:47:29.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:47:29.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:47:29.95$vc4f8/valo=7,832.99 2006.238.07:47:29.95#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:47:29.95#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:47:29.95#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:29.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:47:29.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:47:29.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:47:29.95#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:47:29.95#ibcon#first serial, iclass 35, count 0 2006.238.07:47:29.95#ibcon#enter sib2, iclass 35, count 0 2006.238.07:47:29.95#ibcon#flushed, iclass 35, count 0 2006.238.07:47:29.95#ibcon#about to write, iclass 35, count 0 2006.238.07:47:29.95#ibcon#wrote, iclass 35, count 0 2006.238.07:47:29.95#ibcon#about to read 3, iclass 35, count 0 2006.238.07:47:29.97#ibcon#read 3, iclass 35, count 0 2006.238.07:47:29.97#ibcon#about to read 4, iclass 35, count 0 2006.238.07:47:29.97#ibcon#read 4, iclass 35, count 0 2006.238.07:47:29.97#ibcon#about to read 5, iclass 35, count 0 2006.238.07:47:29.97#ibcon#read 5, iclass 35, count 0 2006.238.07:47:29.97#ibcon#about to read 6, iclass 35, count 0 2006.238.07:47:29.97#ibcon#read 6, iclass 35, count 0 2006.238.07:47:29.97#ibcon#end of sib2, iclass 35, count 0 2006.238.07:47:29.97#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:47:29.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:47:29.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:47:29.97#ibcon#*before write, iclass 35, count 0 2006.238.07:47:29.97#ibcon#enter sib2, iclass 35, count 0 2006.238.07:47:29.97#ibcon#flushed, iclass 35, count 0 2006.238.07:47:29.97#ibcon#about to write, iclass 35, count 0 2006.238.07:47:29.97#ibcon#wrote, iclass 35, count 0 2006.238.07:47:29.97#ibcon#about to read 3, iclass 35, count 0 2006.238.07:47:30.01#ibcon#read 3, iclass 35, count 0 2006.238.07:47:30.01#ibcon#about to read 4, iclass 35, count 0 2006.238.07:47:30.01#ibcon#read 4, iclass 35, count 0 2006.238.07:47:30.01#ibcon#about to read 5, iclass 35, count 0 2006.238.07:47:30.01#ibcon#read 5, iclass 35, count 0 2006.238.07:47:30.01#ibcon#about to read 6, iclass 35, count 0 2006.238.07:47:30.01#ibcon#read 6, iclass 35, count 0 2006.238.07:47:30.01#ibcon#end of sib2, iclass 35, count 0 2006.238.07:47:30.01#ibcon#*after write, iclass 35, count 0 2006.238.07:47:30.01#ibcon#*before return 0, iclass 35, count 0 2006.238.07:47:30.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:47:30.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:47:30.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:47:30.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:47:30.01$vc4f8/va=7,7 2006.238.07:47:30.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.07:47:30.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.07:47:30.01#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:30.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:47:30.07#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:47:30.07#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:47:30.07#ibcon#enter wrdev, iclass 37, count 2 2006.238.07:47:30.07#ibcon#first serial, iclass 37, count 2 2006.238.07:47:30.07#ibcon#enter sib2, iclass 37, count 2 2006.238.07:47:30.07#ibcon#flushed, iclass 37, count 2 2006.238.07:47:30.07#ibcon#about to write, iclass 37, count 2 2006.238.07:47:30.07#ibcon#wrote, iclass 37, count 2 2006.238.07:47:30.07#ibcon#about to read 3, iclass 37, count 2 2006.238.07:47:30.09#ibcon#read 3, iclass 37, count 2 2006.238.07:47:30.09#ibcon#about to read 4, iclass 37, count 2 2006.238.07:47:30.09#ibcon#read 4, iclass 37, count 2 2006.238.07:47:30.09#ibcon#about to read 5, iclass 37, count 2 2006.238.07:47:30.09#ibcon#read 5, iclass 37, count 2 2006.238.07:47:30.09#ibcon#about to read 6, iclass 37, count 2 2006.238.07:47:30.09#ibcon#read 6, iclass 37, count 2 2006.238.07:47:30.09#ibcon#end of sib2, iclass 37, count 2 2006.238.07:47:30.09#ibcon#*mode == 0, iclass 37, count 2 2006.238.07:47:30.09#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.07:47:30.09#ibcon#[25=AT07-07\r\n] 2006.238.07:47:30.09#ibcon#*before write, iclass 37, count 2 2006.238.07:47:30.09#ibcon#enter sib2, iclass 37, count 2 2006.238.07:47:30.09#ibcon#flushed, iclass 37, count 2 2006.238.07:47:30.09#ibcon#about to write, iclass 37, count 2 2006.238.07:47:30.09#ibcon#wrote, iclass 37, count 2 2006.238.07:47:30.09#ibcon#about to read 3, iclass 37, count 2 2006.238.07:47:30.12#ibcon#read 3, iclass 37, count 2 2006.238.07:47:30.12#ibcon#about to read 4, iclass 37, count 2 2006.238.07:47:30.12#ibcon#read 4, iclass 37, count 2 2006.238.07:47:30.12#ibcon#about to read 5, iclass 37, count 2 2006.238.07:47:30.12#ibcon#read 5, iclass 37, count 2 2006.238.07:47:30.12#ibcon#about to read 6, iclass 37, count 2 2006.238.07:47:30.12#ibcon#read 6, iclass 37, count 2 2006.238.07:47:30.12#ibcon#end of sib2, iclass 37, count 2 2006.238.07:47:30.12#ibcon#*after write, iclass 37, count 2 2006.238.07:47:30.12#ibcon#*before return 0, iclass 37, count 2 2006.238.07:47:30.12#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:47:30.12#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:47:30.12#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.07:47:30.12#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:30.12#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:47:30.24#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:47:30.24#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:47:30.24#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:47:30.24#ibcon#first serial, iclass 37, count 0 2006.238.07:47:30.24#ibcon#enter sib2, iclass 37, count 0 2006.238.07:47:30.24#ibcon#flushed, iclass 37, count 0 2006.238.07:47:30.24#ibcon#about to write, iclass 37, count 0 2006.238.07:47:30.24#ibcon#wrote, iclass 37, count 0 2006.238.07:47:30.24#ibcon#about to read 3, iclass 37, count 0 2006.238.07:47:30.26#ibcon#read 3, iclass 37, count 0 2006.238.07:47:30.26#ibcon#about to read 4, iclass 37, count 0 2006.238.07:47:30.26#ibcon#read 4, iclass 37, count 0 2006.238.07:47:30.26#ibcon#about to read 5, iclass 37, count 0 2006.238.07:47:30.26#ibcon#read 5, iclass 37, count 0 2006.238.07:47:30.26#ibcon#about to read 6, iclass 37, count 0 2006.238.07:47:30.26#ibcon#read 6, iclass 37, count 0 2006.238.07:47:30.26#ibcon#end of sib2, iclass 37, count 0 2006.238.07:47:30.26#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:47:30.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:47:30.26#ibcon#[25=USB\r\n] 2006.238.07:47:30.26#ibcon#*before write, iclass 37, count 0 2006.238.07:47:30.26#ibcon#enter sib2, iclass 37, count 0 2006.238.07:47:30.26#ibcon#flushed, iclass 37, count 0 2006.238.07:47:30.26#ibcon#about to write, iclass 37, count 0 2006.238.07:47:30.26#ibcon#wrote, iclass 37, count 0 2006.238.07:47:30.26#ibcon#about to read 3, iclass 37, count 0 2006.238.07:47:30.29#ibcon#read 3, iclass 37, count 0 2006.238.07:47:30.29#ibcon#about to read 4, iclass 37, count 0 2006.238.07:47:30.29#ibcon#read 4, iclass 37, count 0 2006.238.07:47:30.29#ibcon#about to read 5, iclass 37, count 0 2006.238.07:47:30.29#ibcon#read 5, iclass 37, count 0 2006.238.07:47:30.29#ibcon#about to read 6, iclass 37, count 0 2006.238.07:47:30.29#ibcon#read 6, iclass 37, count 0 2006.238.07:47:30.29#ibcon#end of sib2, iclass 37, count 0 2006.238.07:47:30.29#ibcon#*after write, iclass 37, count 0 2006.238.07:47:30.29#ibcon#*before return 0, iclass 37, count 0 2006.238.07:47:30.29#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:47:30.29#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:47:30.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:47:30.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:47:30.29$vc4f8/valo=8,852.99 2006.238.07:47:30.29#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.07:47:30.29#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.07:47:30.29#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:30.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:47:30.29#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:47:30.29#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:47:30.29#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:47:30.29#ibcon#first serial, iclass 39, count 0 2006.238.07:47:30.29#ibcon#enter sib2, iclass 39, count 0 2006.238.07:47:30.29#ibcon#flushed, iclass 39, count 0 2006.238.07:47:30.29#ibcon#about to write, iclass 39, count 0 2006.238.07:47:30.29#ibcon#wrote, iclass 39, count 0 2006.238.07:47:30.29#ibcon#about to read 3, iclass 39, count 0 2006.238.07:47:30.31#ibcon#read 3, iclass 39, count 0 2006.238.07:47:30.31#ibcon#about to read 4, iclass 39, count 0 2006.238.07:47:30.31#ibcon#read 4, iclass 39, count 0 2006.238.07:47:30.31#ibcon#about to read 5, iclass 39, count 0 2006.238.07:47:30.31#ibcon#read 5, iclass 39, count 0 2006.238.07:47:30.31#ibcon#about to read 6, iclass 39, count 0 2006.238.07:47:30.31#ibcon#read 6, iclass 39, count 0 2006.238.07:47:30.31#ibcon#end of sib2, iclass 39, count 0 2006.238.07:47:30.31#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:47:30.31#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:47:30.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:47:30.31#ibcon#*before write, iclass 39, count 0 2006.238.07:47:30.31#ibcon#enter sib2, iclass 39, count 0 2006.238.07:47:30.31#ibcon#flushed, iclass 39, count 0 2006.238.07:47:30.31#ibcon#about to write, iclass 39, count 0 2006.238.07:47:30.31#ibcon#wrote, iclass 39, count 0 2006.238.07:47:30.31#ibcon#about to read 3, iclass 39, count 0 2006.238.07:47:30.35#ibcon#read 3, iclass 39, count 0 2006.238.07:47:30.35#ibcon#about to read 4, iclass 39, count 0 2006.238.07:47:30.35#ibcon#read 4, iclass 39, count 0 2006.238.07:47:30.35#ibcon#about to read 5, iclass 39, count 0 2006.238.07:47:30.35#ibcon#read 5, iclass 39, count 0 2006.238.07:47:30.35#ibcon#about to read 6, iclass 39, count 0 2006.238.07:47:30.35#ibcon#read 6, iclass 39, count 0 2006.238.07:47:30.35#ibcon#end of sib2, iclass 39, count 0 2006.238.07:47:30.35#ibcon#*after write, iclass 39, count 0 2006.238.07:47:30.35#ibcon#*before return 0, iclass 39, count 0 2006.238.07:47:30.35#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:47:30.35#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:47:30.35#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:47:30.35#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:47:30.35$vc4f8/va=8,7 2006.238.07:47:30.35#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.07:47:30.35#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.07:47:30.35#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:30.35#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:47:30.41#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:47:30.41#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:47:30.41#ibcon#enter wrdev, iclass 3, count 2 2006.238.07:47:30.41#ibcon#first serial, iclass 3, count 2 2006.238.07:47:30.41#ibcon#enter sib2, iclass 3, count 2 2006.238.07:47:30.41#ibcon#flushed, iclass 3, count 2 2006.238.07:47:30.41#ibcon#about to write, iclass 3, count 2 2006.238.07:47:30.41#ibcon#wrote, iclass 3, count 2 2006.238.07:47:30.41#ibcon#about to read 3, iclass 3, count 2 2006.238.07:47:30.43#ibcon#read 3, iclass 3, count 2 2006.238.07:47:30.43#ibcon#about to read 4, iclass 3, count 2 2006.238.07:47:30.43#ibcon#read 4, iclass 3, count 2 2006.238.07:47:30.43#ibcon#about to read 5, iclass 3, count 2 2006.238.07:47:30.43#ibcon#read 5, iclass 3, count 2 2006.238.07:47:30.43#ibcon#about to read 6, iclass 3, count 2 2006.238.07:47:30.43#ibcon#read 6, iclass 3, count 2 2006.238.07:47:30.43#ibcon#end of sib2, iclass 3, count 2 2006.238.07:47:30.43#ibcon#*mode == 0, iclass 3, count 2 2006.238.07:47:30.43#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.07:47:30.43#ibcon#[25=AT08-07\r\n] 2006.238.07:47:30.43#ibcon#*before write, iclass 3, count 2 2006.238.07:47:30.43#ibcon#enter sib2, iclass 3, count 2 2006.238.07:47:30.43#ibcon#flushed, iclass 3, count 2 2006.238.07:47:30.43#ibcon#about to write, iclass 3, count 2 2006.238.07:47:30.43#ibcon#wrote, iclass 3, count 2 2006.238.07:47:30.43#ibcon#about to read 3, iclass 3, count 2 2006.238.07:47:30.46#ibcon#read 3, iclass 3, count 2 2006.238.07:47:30.46#ibcon#about to read 4, iclass 3, count 2 2006.238.07:47:30.46#ibcon#read 4, iclass 3, count 2 2006.238.07:47:30.46#ibcon#about to read 5, iclass 3, count 2 2006.238.07:47:30.46#ibcon#read 5, iclass 3, count 2 2006.238.07:47:30.46#ibcon#about to read 6, iclass 3, count 2 2006.238.07:47:30.46#ibcon#read 6, iclass 3, count 2 2006.238.07:47:30.46#ibcon#end of sib2, iclass 3, count 2 2006.238.07:47:30.46#ibcon#*after write, iclass 3, count 2 2006.238.07:47:30.46#ibcon#*before return 0, iclass 3, count 2 2006.238.07:47:30.46#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:47:30.46#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:47:30.46#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.07:47:30.46#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:30.46#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:47:30.58#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:47:30.58#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:47:30.58#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:47:30.58#ibcon#first serial, iclass 3, count 0 2006.238.07:47:30.58#ibcon#enter sib2, iclass 3, count 0 2006.238.07:47:30.58#ibcon#flushed, iclass 3, count 0 2006.238.07:47:30.58#ibcon#about to write, iclass 3, count 0 2006.238.07:47:30.58#ibcon#wrote, iclass 3, count 0 2006.238.07:47:30.58#ibcon#about to read 3, iclass 3, count 0 2006.238.07:47:30.60#ibcon#read 3, iclass 3, count 0 2006.238.07:47:30.60#ibcon#about to read 4, iclass 3, count 0 2006.238.07:47:30.60#ibcon#read 4, iclass 3, count 0 2006.238.07:47:30.60#ibcon#about to read 5, iclass 3, count 0 2006.238.07:47:30.60#ibcon#read 5, iclass 3, count 0 2006.238.07:47:30.60#ibcon#about to read 6, iclass 3, count 0 2006.238.07:47:30.60#ibcon#read 6, iclass 3, count 0 2006.238.07:47:30.60#ibcon#end of sib2, iclass 3, count 0 2006.238.07:47:30.60#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:47:30.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:47:30.60#ibcon#[25=USB\r\n] 2006.238.07:47:30.60#ibcon#*before write, iclass 3, count 0 2006.238.07:47:30.60#ibcon#enter sib2, iclass 3, count 0 2006.238.07:47:30.60#ibcon#flushed, iclass 3, count 0 2006.238.07:47:30.60#ibcon#about to write, iclass 3, count 0 2006.238.07:47:30.60#ibcon#wrote, iclass 3, count 0 2006.238.07:47:30.60#ibcon#about to read 3, iclass 3, count 0 2006.238.07:47:30.63#ibcon#read 3, iclass 3, count 0 2006.238.07:47:30.63#ibcon#about to read 4, iclass 3, count 0 2006.238.07:47:30.63#ibcon#read 4, iclass 3, count 0 2006.238.07:47:30.63#ibcon#about to read 5, iclass 3, count 0 2006.238.07:47:30.63#ibcon#read 5, iclass 3, count 0 2006.238.07:47:30.63#ibcon#about to read 6, iclass 3, count 0 2006.238.07:47:30.63#ibcon#read 6, iclass 3, count 0 2006.238.07:47:30.63#ibcon#end of sib2, iclass 3, count 0 2006.238.07:47:30.63#ibcon#*after write, iclass 3, count 0 2006.238.07:47:30.63#ibcon#*before return 0, iclass 3, count 0 2006.238.07:47:30.63#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:47:30.63#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:47:30.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:47:30.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:47:30.63$vc4f8/vblo=1,632.99 2006.238.07:47:30.63#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.07:47:30.63#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.07:47:30.63#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:30.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:47:30.63#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:47:30.63#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:47:30.63#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:47:30.63#ibcon#first serial, iclass 5, count 0 2006.238.07:47:30.63#ibcon#enter sib2, iclass 5, count 0 2006.238.07:47:30.63#ibcon#flushed, iclass 5, count 0 2006.238.07:47:30.63#ibcon#about to write, iclass 5, count 0 2006.238.07:47:30.63#ibcon#wrote, iclass 5, count 0 2006.238.07:47:30.63#ibcon#about to read 3, iclass 5, count 0 2006.238.07:47:30.65#ibcon#read 3, iclass 5, count 0 2006.238.07:47:30.65#ibcon#about to read 4, iclass 5, count 0 2006.238.07:47:30.65#ibcon#read 4, iclass 5, count 0 2006.238.07:47:30.65#ibcon#about to read 5, iclass 5, count 0 2006.238.07:47:30.65#ibcon#read 5, iclass 5, count 0 2006.238.07:47:30.65#ibcon#about to read 6, iclass 5, count 0 2006.238.07:47:30.65#ibcon#read 6, iclass 5, count 0 2006.238.07:47:30.65#ibcon#end of sib2, iclass 5, count 0 2006.238.07:47:30.65#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:47:30.65#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:47:30.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:47:30.65#ibcon#*before write, iclass 5, count 0 2006.238.07:47:30.65#ibcon#enter sib2, iclass 5, count 0 2006.238.07:47:30.65#ibcon#flushed, iclass 5, count 0 2006.238.07:47:30.65#ibcon#about to write, iclass 5, count 0 2006.238.07:47:30.65#ibcon#wrote, iclass 5, count 0 2006.238.07:47:30.65#ibcon#about to read 3, iclass 5, count 0 2006.238.07:47:30.69#ibcon#read 3, iclass 5, count 0 2006.238.07:47:30.69#ibcon#about to read 4, iclass 5, count 0 2006.238.07:47:30.69#ibcon#read 4, iclass 5, count 0 2006.238.07:47:30.69#ibcon#about to read 5, iclass 5, count 0 2006.238.07:47:30.69#ibcon#read 5, iclass 5, count 0 2006.238.07:47:30.69#ibcon#about to read 6, iclass 5, count 0 2006.238.07:47:30.69#ibcon#read 6, iclass 5, count 0 2006.238.07:47:30.69#ibcon#end of sib2, iclass 5, count 0 2006.238.07:47:30.69#ibcon#*after write, iclass 5, count 0 2006.238.07:47:30.69#ibcon#*before return 0, iclass 5, count 0 2006.238.07:47:30.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:47:30.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:47:30.69#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:47:30.69#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:47:30.69$vc4f8/vb=1,4 2006.238.07:47:30.69#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.07:47:30.69#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.07:47:30.69#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:30.69#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:47:30.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:47:30.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:47:30.69#ibcon#enter wrdev, iclass 7, count 2 2006.238.07:47:30.69#ibcon#first serial, iclass 7, count 2 2006.238.07:47:30.69#ibcon#enter sib2, iclass 7, count 2 2006.238.07:47:30.69#ibcon#flushed, iclass 7, count 2 2006.238.07:47:30.69#ibcon#about to write, iclass 7, count 2 2006.238.07:47:30.69#ibcon#wrote, iclass 7, count 2 2006.238.07:47:30.69#ibcon#about to read 3, iclass 7, count 2 2006.238.07:47:30.71#ibcon#read 3, iclass 7, count 2 2006.238.07:47:30.71#ibcon#about to read 4, iclass 7, count 2 2006.238.07:47:30.71#ibcon#read 4, iclass 7, count 2 2006.238.07:47:30.71#ibcon#about to read 5, iclass 7, count 2 2006.238.07:47:30.71#ibcon#read 5, iclass 7, count 2 2006.238.07:47:30.71#ibcon#about to read 6, iclass 7, count 2 2006.238.07:47:30.71#ibcon#read 6, iclass 7, count 2 2006.238.07:47:30.71#ibcon#end of sib2, iclass 7, count 2 2006.238.07:47:30.71#ibcon#*mode == 0, iclass 7, count 2 2006.238.07:47:30.71#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.07:47:30.71#ibcon#[27=AT01-04\r\n] 2006.238.07:47:30.71#ibcon#*before write, iclass 7, count 2 2006.238.07:47:30.71#ibcon#enter sib2, iclass 7, count 2 2006.238.07:47:30.71#ibcon#flushed, iclass 7, count 2 2006.238.07:47:30.71#ibcon#about to write, iclass 7, count 2 2006.238.07:47:30.71#ibcon#wrote, iclass 7, count 2 2006.238.07:47:30.71#ibcon#about to read 3, iclass 7, count 2 2006.238.07:47:30.74#ibcon#read 3, iclass 7, count 2 2006.238.07:47:30.74#ibcon#about to read 4, iclass 7, count 2 2006.238.07:47:30.74#ibcon#read 4, iclass 7, count 2 2006.238.07:47:30.74#ibcon#about to read 5, iclass 7, count 2 2006.238.07:47:30.74#ibcon#read 5, iclass 7, count 2 2006.238.07:47:30.74#ibcon#about to read 6, iclass 7, count 2 2006.238.07:47:30.74#ibcon#read 6, iclass 7, count 2 2006.238.07:47:30.74#ibcon#end of sib2, iclass 7, count 2 2006.238.07:47:30.74#ibcon#*after write, iclass 7, count 2 2006.238.07:47:30.74#ibcon#*before return 0, iclass 7, count 2 2006.238.07:47:30.74#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:47:30.74#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:47:30.74#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.07:47:30.74#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:30.74#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:47:30.86#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:47:30.86#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:47:30.86#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:47:30.86#ibcon#first serial, iclass 7, count 0 2006.238.07:47:30.86#ibcon#enter sib2, iclass 7, count 0 2006.238.07:47:30.86#ibcon#flushed, iclass 7, count 0 2006.238.07:47:30.86#ibcon#about to write, iclass 7, count 0 2006.238.07:47:30.86#ibcon#wrote, iclass 7, count 0 2006.238.07:47:30.86#ibcon#about to read 3, iclass 7, count 0 2006.238.07:47:30.88#ibcon#read 3, iclass 7, count 0 2006.238.07:47:30.88#ibcon#about to read 4, iclass 7, count 0 2006.238.07:47:30.88#ibcon#read 4, iclass 7, count 0 2006.238.07:47:30.88#ibcon#about to read 5, iclass 7, count 0 2006.238.07:47:30.88#ibcon#read 5, iclass 7, count 0 2006.238.07:47:30.88#ibcon#about to read 6, iclass 7, count 0 2006.238.07:47:30.88#ibcon#read 6, iclass 7, count 0 2006.238.07:47:30.88#ibcon#end of sib2, iclass 7, count 0 2006.238.07:47:30.88#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:47:30.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:47:30.88#ibcon#[27=USB\r\n] 2006.238.07:47:30.88#ibcon#*before write, iclass 7, count 0 2006.238.07:47:30.88#ibcon#enter sib2, iclass 7, count 0 2006.238.07:47:30.88#ibcon#flushed, iclass 7, count 0 2006.238.07:47:30.88#ibcon#about to write, iclass 7, count 0 2006.238.07:47:30.88#ibcon#wrote, iclass 7, count 0 2006.238.07:47:30.88#ibcon#about to read 3, iclass 7, count 0 2006.238.07:47:30.91#ibcon#read 3, iclass 7, count 0 2006.238.07:47:30.91#ibcon#about to read 4, iclass 7, count 0 2006.238.07:47:30.91#ibcon#read 4, iclass 7, count 0 2006.238.07:47:30.91#ibcon#about to read 5, iclass 7, count 0 2006.238.07:47:30.91#ibcon#read 5, iclass 7, count 0 2006.238.07:47:30.91#ibcon#about to read 6, iclass 7, count 0 2006.238.07:47:30.91#ibcon#read 6, iclass 7, count 0 2006.238.07:47:30.91#ibcon#end of sib2, iclass 7, count 0 2006.238.07:47:30.91#ibcon#*after write, iclass 7, count 0 2006.238.07:47:30.91#ibcon#*before return 0, iclass 7, count 0 2006.238.07:47:30.91#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:47:30.91#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:47:30.91#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:47:30.91#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:47:30.91$vc4f8/vblo=2,640.99 2006.238.07:47:30.91#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.07:47:30.91#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.07:47:30.91#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:30.91#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:47:30.91#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:47:30.91#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:47:30.91#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:47:30.91#ibcon#first serial, iclass 11, count 0 2006.238.07:47:30.91#ibcon#enter sib2, iclass 11, count 0 2006.238.07:47:30.91#ibcon#flushed, iclass 11, count 0 2006.238.07:47:30.91#ibcon#about to write, iclass 11, count 0 2006.238.07:47:30.91#ibcon#wrote, iclass 11, count 0 2006.238.07:47:30.91#ibcon#about to read 3, iclass 11, count 0 2006.238.07:47:30.93#ibcon#read 3, iclass 11, count 0 2006.238.07:47:30.93#ibcon#about to read 4, iclass 11, count 0 2006.238.07:47:30.93#ibcon#read 4, iclass 11, count 0 2006.238.07:47:30.93#ibcon#about to read 5, iclass 11, count 0 2006.238.07:47:30.93#ibcon#read 5, iclass 11, count 0 2006.238.07:47:30.93#ibcon#about to read 6, iclass 11, count 0 2006.238.07:47:30.93#ibcon#read 6, iclass 11, count 0 2006.238.07:47:30.93#ibcon#end of sib2, iclass 11, count 0 2006.238.07:47:30.93#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:47:30.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:47:30.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:47:30.93#ibcon#*before write, iclass 11, count 0 2006.238.07:47:30.93#ibcon#enter sib2, iclass 11, count 0 2006.238.07:47:30.93#ibcon#flushed, iclass 11, count 0 2006.238.07:47:30.93#ibcon#about to write, iclass 11, count 0 2006.238.07:47:30.93#ibcon#wrote, iclass 11, count 0 2006.238.07:47:30.93#ibcon#about to read 3, iclass 11, count 0 2006.238.07:47:30.97#ibcon#read 3, iclass 11, count 0 2006.238.07:47:30.97#ibcon#about to read 4, iclass 11, count 0 2006.238.07:47:30.97#ibcon#read 4, iclass 11, count 0 2006.238.07:47:30.97#ibcon#about to read 5, iclass 11, count 0 2006.238.07:47:30.97#ibcon#read 5, iclass 11, count 0 2006.238.07:47:30.97#ibcon#about to read 6, iclass 11, count 0 2006.238.07:47:30.97#ibcon#read 6, iclass 11, count 0 2006.238.07:47:30.97#ibcon#end of sib2, iclass 11, count 0 2006.238.07:47:30.97#ibcon#*after write, iclass 11, count 0 2006.238.07:47:30.97#ibcon#*before return 0, iclass 11, count 0 2006.238.07:47:30.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:47:30.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:47:30.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:47:30.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:47:30.97$vc4f8/vb=2,4 2006.238.07:47:30.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.07:47:30.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.07:47:30.97#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:30.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:47:31.03#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:47:31.03#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:47:31.03#ibcon#enter wrdev, iclass 13, count 2 2006.238.07:47:31.03#ibcon#first serial, iclass 13, count 2 2006.238.07:47:31.03#ibcon#enter sib2, iclass 13, count 2 2006.238.07:47:31.03#ibcon#flushed, iclass 13, count 2 2006.238.07:47:31.03#ibcon#about to write, iclass 13, count 2 2006.238.07:47:31.03#ibcon#wrote, iclass 13, count 2 2006.238.07:47:31.03#ibcon#about to read 3, iclass 13, count 2 2006.238.07:47:31.05#ibcon#read 3, iclass 13, count 2 2006.238.07:47:31.05#ibcon#about to read 4, iclass 13, count 2 2006.238.07:47:31.05#ibcon#read 4, iclass 13, count 2 2006.238.07:47:31.05#ibcon#about to read 5, iclass 13, count 2 2006.238.07:47:31.05#ibcon#read 5, iclass 13, count 2 2006.238.07:47:31.05#ibcon#about to read 6, iclass 13, count 2 2006.238.07:47:31.05#ibcon#read 6, iclass 13, count 2 2006.238.07:47:31.05#ibcon#end of sib2, iclass 13, count 2 2006.238.07:47:31.05#ibcon#*mode == 0, iclass 13, count 2 2006.238.07:47:31.05#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.07:47:31.05#ibcon#[27=AT02-04\r\n] 2006.238.07:47:31.05#ibcon#*before write, iclass 13, count 2 2006.238.07:47:31.05#ibcon#enter sib2, iclass 13, count 2 2006.238.07:47:31.05#ibcon#flushed, iclass 13, count 2 2006.238.07:47:31.05#ibcon#about to write, iclass 13, count 2 2006.238.07:47:31.05#ibcon#wrote, iclass 13, count 2 2006.238.07:47:31.05#ibcon#about to read 3, iclass 13, count 2 2006.238.07:47:31.08#ibcon#read 3, iclass 13, count 2 2006.238.07:47:31.08#ibcon#about to read 4, iclass 13, count 2 2006.238.07:47:31.08#ibcon#read 4, iclass 13, count 2 2006.238.07:47:31.08#ibcon#about to read 5, iclass 13, count 2 2006.238.07:47:31.08#ibcon#read 5, iclass 13, count 2 2006.238.07:47:31.08#ibcon#about to read 6, iclass 13, count 2 2006.238.07:47:31.08#ibcon#read 6, iclass 13, count 2 2006.238.07:47:31.08#ibcon#end of sib2, iclass 13, count 2 2006.238.07:47:31.08#ibcon#*after write, iclass 13, count 2 2006.238.07:47:31.08#ibcon#*before return 0, iclass 13, count 2 2006.238.07:47:31.08#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:47:31.08#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:47:31.08#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.07:47:31.08#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:31.08#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:47:31.20#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:47:31.20#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:47:31.20#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:47:31.20#ibcon#first serial, iclass 13, count 0 2006.238.07:47:31.20#ibcon#enter sib2, iclass 13, count 0 2006.238.07:47:31.20#ibcon#flushed, iclass 13, count 0 2006.238.07:47:31.20#ibcon#about to write, iclass 13, count 0 2006.238.07:47:31.20#ibcon#wrote, iclass 13, count 0 2006.238.07:47:31.20#ibcon#about to read 3, iclass 13, count 0 2006.238.07:47:31.22#ibcon#read 3, iclass 13, count 0 2006.238.07:47:31.22#ibcon#about to read 4, iclass 13, count 0 2006.238.07:47:31.22#ibcon#read 4, iclass 13, count 0 2006.238.07:47:31.22#ibcon#about to read 5, iclass 13, count 0 2006.238.07:47:31.22#ibcon#read 5, iclass 13, count 0 2006.238.07:47:31.22#ibcon#about to read 6, iclass 13, count 0 2006.238.07:47:31.22#ibcon#read 6, iclass 13, count 0 2006.238.07:47:31.22#ibcon#end of sib2, iclass 13, count 0 2006.238.07:47:31.22#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:47:31.22#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:47:31.22#ibcon#[27=USB\r\n] 2006.238.07:47:31.22#ibcon#*before write, iclass 13, count 0 2006.238.07:47:31.22#ibcon#enter sib2, iclass 13, count 0 2006.238.07:47:31.22#ibcon#flushed, iclass 13, count 0 2006.238.07:47:31.22#ibcon#about to write, iclass 13, count 0 2006.238.07:47:31.22#ibcon#wrote, iclass 13, count 0 2006.238.07:47:31.22#ibcon#about to read 3, iclass 13, count 0 2006.238.07:47:31.25#ibcon#read 3, iclass 13, count 0 2006.238.07:47:31.25#ibcon#about to read 4, iclass 13, count 0 2006.238.07:47:31.25#ibcon#read 4, iclass 13, count 0 2006.238.07:47:31.25#ibcon#about to read 5, iclass 13, count 0 2006.238.07:47:31.25#ibcon#read 5, iclass 13, count 0 2006.238.07:47:31.25#ibcon#about to read 6, iclass 13, count 0 2006.238.07:47:31.25#ibcon#read 6, iclass 13, count 0 2006.238.07:47:31.25#ibcon#end of sib2, iclass 13, count 0 2006.238.07:47:31.25#ibcon#*after write, iclass 13, count 0 2006.238.07:47:31.25#ibcon#*before return 0, iclass 13, count 0 2006.238.07:47:31.25#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:47:31.25#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:47:31.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:47:31.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:47:31.25$vc4f8/vblo=3,656.99 2006.238.07:47:31.25#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.07:47:31.25#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.07:47:31.25#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:31.25#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:47:31.25#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:47:31.25#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:47:31.25#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:47:31.25#ibcon#first serial, iclass 15, count 0 2006.238.07:47:31.25#ibcon#enter sib2, iclass 15, count 0 2006.238.07:47:31.25#ibcon#flushed, iclass 15, count 0 2006.238.07:47:31.25#ibcon#about to write, iclass 15, count 0 2006.238.07:47:31.25#ibcon#wrote, iclass 15, count 0 2006.238.07:47:31.25#ibcon#about to read 3, iclass 15, count 0 2006.238.07:47:31.27#ibcon#read 3, iclass 15, count 0 2006.238.07:47:31.27#ibcon#about to read 4, iclass 15, count 0 2006.238.07:47:31.27#ibcon#read 4, iclass 15, count 0 2006.238.07:47:31.27#ibcon#about to read 5, iclass 15, count 0 2006.238.07:47:31.27#ibcon#read 5, iclass 15, count 0 2006.238.07:47:31.27#ibcon#about to read 6, iclass 15, count 0 2006.238.07:47:31.27#ibcon#read 6, iclass 15, count 0 2006.238.07:47:31.27#ibcon#end of sib2, iclass 15, count 0 2006.238.07:47:31.27#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:47:31.27#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:47:31.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:47:31.27#ibcon#*before write, iclass 15, count 0 2006.238.07:47:31.27#ibcon#enter sib2, iclass 15, count 0 2006.238.07:47:31.27#ibcon#flushed, iclass 15, count 0 2006.238.07:47:31.27#ibcon#about to write, iclass 15, count 0 2006.238.07:47:31.27#ibcon#wrote, iclass 15, count 0 2006.238.07:47:31.27#ibcon#about to read 3, iclass 15, count 0 2006.238.07:47:31.31#ibcon#read 3, iclass 15, count 0 2006.238.07:47:31.31#ibcon#about to read 4, iclass 15, count 0 2006.238.07:47:31.31#ibcon#read 4, iclass 15, count 0 2006.238.07:47:31.31#ibcon#about to read 5, iclass 15, count 0 2006.238.07:47:31.31#ibcon#read 5, iclass 15, count 0 2006.238.07:47:31.31#ibcon#about to read 6, iclass 15, count 0 2006.238.07:47:31.31#ibcon#read 6, iclass 15, count 0 2006.238.07:47:31.31#ibcon#end of sib2, iclass 15, count 0 2006.238.07:47:31.31#ibcon#*after write, iclass 15, count 0 2006.238.07:47:31.31#ibcon#*before return 0, iclass 15, count 0 2006.238.07:47:31.31#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:47:31.31#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:47:31.31#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:47:31.31#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:47:31.31$vc4f8/vb=3,4 2006.238.07:47:31.31#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.07:47:31.31#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.07:47:31.31#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:31.31#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:47:31.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:47:31.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:47:31.37#ibcon#enter wrdev, iclass 17, count 2 2006.238.07:47:31.37#ibcon#first serial, iclass 17, count 2 2006.238.07:47:31.37#ibcon#enter sib2, iclass 17, count 2 2006.238.07:47:31.37#ibcon#flushed, iclass 17, count 2 2006.238.07:47:31.37#ibcon#about to write, iclass 17, count 2 2006.238.07:47:31.37#ibcon#wrote, iclass 17, count 2 2006.238.07:47:31.37#ibcon#about to read 3, iclass 17, count 2 2006.238.07:47:31.39#ibcon#read 3, iclass 17, count 2 2006.238.07:47:31.39#ibcon#about to read 4, iclass 17, count 2 2006.238.07:47:31.39#ibcon#read 4, iclass 17, count 2 2006.238.07:47:31.39#ibcon#about to read 5, iclass 17, count 2 2006.238.07:47:31.39#ibcon#read 5, iclass 17, count 2 2006.238.07:47:31.39#ibcon#about to read 6, iclass 17, count 2 2006.238.07:47:31.39#ibcon#read 6, iclass 17, count 2 2006.238.07:47:31.39#ibcon#end of sib2, iclass 17, count 2 2006.238.07:47:31.39#ibcon#*mode == 0, iclass 17, count 2 2006.238.07:47:31.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.07:47:31.39#ibcon#[27=AT03-04\r\n] 2006.238.07:47:31.39#ibcon#*before write, iclass 17, count 2 2006.238.07:47:31.39#ibcon#enter sib2, iclass 17, count 2 2006.238.07:47:31.39#ibcon#flushed, iclass 17, count 2 2006.238.07:47:31.39#ibcon#about to write, iclass 17, count 2 2006.238.07:47:31.39#ibcon#wrote, iclass 17, count 2 2006.238.07:47:31.39#ibcon#about to read 3, iclass 17, count 2 2006.238.07:47:31.42#ibcon#read 3, iclass 17, count 2 2006.238.07:47:31.42#ibcon#about to read 4, iclass 17, count 2 2006.238.07:47:31.42#ibcon#read 4, iclass 17, count 2 2006.238.07:47:31.42#ibcon#about to read 5, iclass 17, count 2 2006.238.07:47:31.42#ibcon#read 5, iclass 17, count 2 2006.238.07:47:31.42#ibcon#about to read 6, iclass 17, count 2 2006.238.07:47:31.42#ibcon#read 6, iclass 17, count 2 2006.238.07:47:31.42#ibcon#end of sib2, iclass 17, count 2 2006.238.07:47:31.42#ibcon#*after write, iclass 17, count 2 2006.238.07:47:31.42#ibcon#*before return 0, iclass 17, count 2 2006.238.07:47:31.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:47:31.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:47:31.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.07:47:31.42#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:31.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:47:31.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:47:31.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:47:31.54#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:47:31.54#ibcon#first serial, iclass 17, count 0 2006.238.07:47:31.54#ibcon#enter sib2, iclass 17, count 0 2006.238.07:47:31.54#ibcon#flushed, iclass 17, count 0 2006.238.07:47:31.54#ibcon#about to write, iclass 17, count 0 2006.238.07:47:31.54#ibcon#wrote, iclass 17, count 0 2006.238.07:47:31.54#ibcon#about to read 3, iclass 17, count 0 2006.238.07:47:31.56#ibcon#read 3, iclass 17, count 0 2006.238.07:47:31.56#ibcon#about to read 4, iclass 17, count 0 2006.238.07:47:31.56#ibcon#read 4, iclass 17, count 0 2006.238.07:47:31.56#ibcon#about to read 5, iclass 17, count 0 2006.238.07:47:31.56#ibcon#read 5, iclass 17, count 0 2006.238.07:47:31.56#ibcon#about to read 6, iclass 17, count 0 2006.238.07:47:31.56#ibcon#read 6, iclass 17, count 0 2006.238.07:47:31.56#ibcon#end of sib2, iclass 17, count 0 2006.238.07:47:31.56#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:47:31.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:47:31.56#ibcon#[27=USB\r\n] 2006.238.07:47:31.56#ibcon#*before write, iclass 17, count 0 2006.238.07:47:31.56#ibcon#enter sib2, iclass 17, count 0 2006.238.07:47:31.56#ibcon#flushed, iclass 17, count 0 2006.238.07:47:31.56#ibcon#about to write, iclass 17, count 0 2006.238.07:47:31.56#ibcon#wrote, iclass 17, count 0 2006.238.07:47:31.56#ibcon#about to read 3, iclass 17, count 0 2006.238.07:47:31.59#ibcon#read 3, iclass 17, count 0 2006.238.07:47:31.59#ibcon#about to read 4, iclass 17, count 0 2006.238.07:47:31.59#ibcon#read 4, iclass 17, count 0 2006.238.07:47:31.59#ibcon#about to read 5, iclass 17, count 0 2006.238.07:47:31.59#ibcon#read 5, iclass 17, count 0 2006.238.07:47:31.59#ibcon#about to read 6, iclass 17, count 0 2006.238.07:47:31.59#ibcon#read 6, iclass 17, count 0 2006.238.07:47:31.59#ibcon#end of sib2, iclass 17, count 0 2006.238.07:47:31.59#ibcon#*after write, iclass 17, count 0 2006.238.07:47:31.59#ibcon#*before return 0, iclass 17, count 0 2006.238.07:47:31.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:47:31.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:47:31.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:47:31.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:47:31.59$vc4f8/vblo=4,712.99 2006.238.07:47:31.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.07:47:31.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.07:47:31.59#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:31.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:47:31.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:47:31.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:47:31.59#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:47:31.59#ibcon#first serial, iclass 20, count 0 2006.238.07:47:31.59#ibcon#enter sib2, iclass 20, count 0 2006.238.07:47:31.59#ibcon#flushed, iclass 20, count 0 2006.238.07:47:31.59#ibcon#about to write, iclass 20, count 0 2006.238.07:47:31.59#ibcon#wrote, iclass 20, count 0 2006.238.07:47:31.59#ibcon#about to read 3, iclass 20, count 0 2006.238.07:47:31.61#ibcon#read 3, iclass 20, count 0 2006.238.07:47:31.61#ibcon#about to read 4, iclass 20, count 0 2006.238.07:47:31.61#ibcon#read 4, iclass 20, count 0 2006.238.07:47:31.61#ibcon#about to read 5, iclass 20, count 0 2006.238.07:47:31.61#ibcon#read 5, iclass 20, count 0 2006.238.07:47:31.61#ibcon#about to read 6, iclass 20, count 0 2006.238.07:47:31.61#ibcon#read 6, iclass 20, count 0 2006.238.07:47:31.61#ibcon#end of sib2, iclass 20, count 0 2006.238.07:47:31.61#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:47:31.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:47:31.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:47:31.61#ibcon#*before write, iclass 20, count 0 2006.238.07:47:31.61#ibcon#enter sib2, iclass 20, count 0 2006.238.07:47:31.61#ibcon#flushed, iclass 20, count 0 2006.238.07:47:31.61#ibcon#about to write, iclass 20, count 0 2006.238.07:47:31.61#ibcon#wrote, iclass 20, count 0 2006.238.07:47:31.61#ibcon#about to read 3, iclass 20, count 0 2006.238.07:47:31.61#abcon#<5=/05 2.5 4.1 25.32 861012.2\r\n> 2006.238.07:47:31.63#abcon#{5=INTERFACE CLEAR} 2006.238.07:47:31.65#ibcon#read 3, iclass 20, count 0 2006.238.07:47:31.65#ibcon#about to read 4, iclass 20, count 0 2006.238.07:47:31.65#ibcon#read 4, iclass 20, count 0 2006.238.07:47:31.65#ibcon#about to read 5, iclass 20, count 0 2006.238.07:47:31.65#ibcon#read 5, iclass 20, count 0 2006.238.07:47:31.65#ibcon#about to read 6, iclass 20, count 0 2006.238.07:47:31.65#ibcon#read 6, iclass 20, count 0 2006.238.07:47:31.65#ibcon#end of sib2, iclass 20, count 0 2006.238.07:47:31.65#ibcon#*after write, iclass 20, count 0 2006.238.07:47:31.65#ibcon#*before return 0, iclass 20, count 0 2006.238.07:47:31.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:47:31.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:47:31.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:47:31.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:47:31.65$vc4f8/vb=4,4 2006.238.07:47:31.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.238.07:47:31.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.238.07:47:31.65#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:31.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:47:31.69#abcon#[5=S1D000X0/0*\r\n] 2006.238.07:47:31.71#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:47:31.71#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:47:31.71#ibcon#enter wrdev, iclass 24, count 2 2006.238.07:47:31.71#ibcon#first serial, iclass 24, count 2 2006.238.07:47:31.71#ibcon#enter sib2, iclass 24, count 2 2006.238.07:47:31.71#ibcon#flushed, iclass 24, count 2 2006.238.07:47:31.71#ibcon#about to write, iclass 24, count 2 2006.238.07:47:31.71#ibcon#wrote, iclass 24, count 2 2006.238.07:47:31.71#ibcon#about to read 3, iclass 24, count 2 2006.238.07:47:31.73#ibcon#read 3, iclass 24, count 2 2006.238.07:47:31.73#ibcon#about to read 4, iclass 24, count 2 2006.238.07:47:31.73#ibcon#read 4, iclass 24, count 2 2006.238.07:47:31.73#ibcon#about to read 5, iclass 24, count 2 2006.238.07:47:31.73#ibcon#read 5, iclass 24, count 2 2006.238.07:47:31.73#ibcon#about to read 6, iclass 24, count 2 2006.238.07:47:31.73#ibcon#read 6, iclass 24, count 2 2006.238.07:47:31.73#ibcon#end of sib2, iclass 24, count 2 2006.238.07:47:31.73#ibcon#*mode == 0, iclass 24, count 2 2006.238.07:47:31.73#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.238.07:47:31.73#ibcon#[27=AT04-04\r\n] 2006.238.07:47:31.73#ibcon#*before write, iclass 24, count 2 2006.238.07:47:31.73#ibcon#enter sib2, iclass 24, count 2 2006.238.07:47:31.73#ibcon#flushed, iclass 24, count 2 2006.238.07:47:31.73#ibcon#about to write, iclass 24, count 2 2006.238.07:47:31.73#ibcon#wrote, iclass 24, count 2 2006.238.07:47:31.73#ibcon#about to read 3, iclass 24, count 2 2006.238.07:47:31.76#ibcon#read 3, iclass 24, count 2 2006.238.07:47:31.76#ibcon#about to read 4, iclass 24, count 2 2006.238.07:47:31.76#ibcon#read 4, iclass 24, count 2 2006.238.07:47:31.76#ibcon#about to read 5, iclass 24, count 2 2006.238.07:47:31.76#ibcon#read 5, iclass 24, count 2 2006.238.07:47:31.76#ibcon#about to read 6, iclass 24, count 2 2006.238.07:47:31.76#ibcon#read 6, iclass 24, count 2 2006.238.07:47:31.76#ibcon#end of sib2, iclass 24, count 2 2006.238.07:47:31.76#ibcon#*after write, iclass 24, count 2 2006.238.07:47:31.76#ibcon#*before return 0, iclass 24, count 2 2006.238.07:47:31.76#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:47:31.76#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:47:31.76#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.238.07:47:31.76#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:31.76#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:47:31.88#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:47:31.88#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:47:31.88#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:47:31.88#ibcon#first serial, iclass 24, count 0 2006.238.07:47:31.88#ibcon#enter sib2, iclass 24, count 0 2006.238.07:47:31.88#ibcon#flushed, iclass 24, count 0 2006.238.07:47:31.88#ibcon#about to write, iclass 24, count 0 2006.238.07:47:31.88#ibcon#wrote, iclass 24, count 0 2006.238.07:47:31.88#ibcon#about to read 3, iclass 24, count 0 2006.238.07:47:31.90#ibcon#read 3, iclass 24, count 0 2006.238.07:47:31.90#ibcon#about to read 4, iclass 24, count 0 2006.238.07:47:31.90#ibcon#read 4, iclass 24, count 0 2006.238.07:47:31.90#ibcon#about to read 5, iclass 24, count 0 2006.238.07:47:31.90#ibcon#read 5, iclass 24, count 0 2006.238.07:47:31.90#ibcon#about to read 6, iclass 24, count 0 2006.238.07:47:31.90#ibcon#read 6, iclass 24, count 0 2006.238.07:47:31.90#ibcon#end of sib2, iclass 24, count 0 2006.238.07:47:31.90#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:47:31.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:47:31.90#ibcon#[27=USB\r\n] 2006.238.07:47:31.90#ibcon#*before write, iclass 24, count 0 2006.238.07:47:31.90#ibcon#enter sib2, iclass 24, count 0 2006.238.07:47:31.90#ibcon#flushed, iclass 24, count 0 2006.238.07:47:31.90#ibcon#about to write, iclass 24, count 0 2006.238.07:47:31.90#ibcon#wrote, iclass 24, count 0 2006.238.07:47:31.90#ibcon#about to read 3, iclass 24, count 0 2006.238.07:47:31.93#ibcon#read 3, iclass 24, count 0 2006.238.07:47:31.93#ibcon#about to read 4, iclass 24, count 0 2006.238.07:47:31.93#ibcon#read 4, iclass 24, count 0 2006.238.07:47:31.93#ibcon#about to read 5, iclass 24, count 0 2006.238.07:47:31.93#ibcon#read 5, iclass 24, count 0 2006.238.07:47:31.93#ibcon#about to read 6, iclass 24, count 0 2006.238.07:47:31.93#ibcon#read 6, iclass 24, count 0 2006.238.07:47:31.93#ibcon#end of sib2, iclass 24, count 0 2006.238.07:47:31.93#ibcon#*after write, iclass 24, count 0 2006.238.07:47:31.93#ibcon#*before return 0, iclass 24, count 0 2006.238.07:47:31.93#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:47:31.93#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:47:31.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:47:31.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:47:31.93$vc4f8/vblo=5,744.99 2006.238.07:47:31.93#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:47:31.93#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:47:31.93#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:31.93#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:47:31.93#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:47:31.93#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:47:31.93#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:47:31.93#ibcon#first serial, iclass 27, count 0 2006.238.07:47:31.93#ibcon#enter sib2, iclass 27, count 0 2006.238.07:47:31.93#ibcon#flushed, iclass 27, count 0 2006.238.07:47:31.93#ibcon#about to write, iclass 27, count 0 2006.238.07:47:31.93#ibcon#wrote, iclass 27, count 0 2006.238.07:47:31.93#ibcon#about to read 3, iclass 27, count 0 2006.238.07:47:31.95#ibcon#read 3, iclass 27, count 0 2006.238.07:47:31.95#ibcon#about to read 4, iclass 27, count 0 2006.238.07:47:31.95#ibcon#read 4, iclass 27, count 0 2006.238.07:47:31.95#ibcon#about to read 5, iclass 27, count 0 2006.238.07:47:31.95#ibcon#read 5, iclass 27, count 0 2006.238.07:47:31.95#ibcon#about to read 6, iclass 27, count 0 2006.238.07:47:31.95#ibcon#read 6, iclass 27, count 0 2006.238.07:47:31.95#ibcon#end of sib2, iclass 27, count 0 2006.238.07:47:31.95#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:47:31.95#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:47:31.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:47:31.95#ibcon#*before write, iclass 27, count 0 2006.238.07:47:31.95#ibcon#enter sib2, iclass 27, count 0 2006.238.07:47:31.95#ibcon#flushed, iclass 27, count 0 2006.238.07:47:31.95#ibcon#about to write, iclass 27, count 0 2006.238.07:47:31.95#ibcon#wrote, iclass 27, count 0 2006.238.07:47:31.95#ibcon#about to read 3, iclass 27, count 0 2006.238.07:47:31.99#ibcon#read 3, iclass 27, count 0 2006.238.07:47:31.99#ibcon#about to read 4, iclass 27, count 0 2006.238.07:47:31.99#ibcon#read 4, iclass 27, count 0 2006.238.07:47:31.99#ibcon#about to read 5, iclass 27, count 0 2006.238.07:47:31.99#ibcon#read 5, iclass 27, count 0 2006.238.07:47:31.99#ibcon#about to read 6, iclass 27, count 0 2006.238.07:47:31.99#ibcon#read 6, iclass 27, count 0 2006.238.07:47:31.99#ibcon#end of sib2, iclass 27, count 0 2006.238.07:47:31.99#ibcon#*after write, iclass 27, count 0 2006.238.07:47:31.99#ibcon#*before return 0, iclass 27, count 0 2006.238.07:47:31.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:47:31.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:47:31.99#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:47:31.99#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:47:31.99$vc4f8/vb=5,4 2006.238.07:47:31.99#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.07:47:31.99#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.07:47:31.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:31.99#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:47:32.05#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:47:32.05#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:47:32.05#ibcon#enter wrdev, iclass 29, count 2 2006.238.07:47:32.05#ibcon#first serial, iclass 29, count 2 2006.238.07:47:32.05#ibcon#enter sib2, iclass 29, count 2 2006.238.07:47:32.05#ibcon#flushed, iclass 29, count 2 2006.238.07:47:32.05#ibcon#about to write, iclass 29, count 2 2006.238.07:47:32.05#ibcon#wrote, iclass 29, count 2 2006.238.07:47:32.05#ibcon#about to read 3, iclass 29, count 2 2006.238.07:47:32.07#ibcon#read 3, iclass 29, count 2 2006.238.07:47:32.07#ibcon#about to read 4, iclass 29, count 2 2006.238.07:47:32.07#ibcon#read 4, iclass 29, count 2 2006.238.07:47:32.07#ibcon#about to read 5, iclass 29, count 2 2006.238.07:47:32.07#ibcon#read 5, iclass 29, count 2 2006.238.07:47:32.07#ibcon#about to read 6, iclass 29, count 2 2006.238.07:47:32.07#ibcon#read 6, iclass 29, count 2 2006.238.07:47:32.07#ibcon#end of sib2, iclass 29, count 2 2006.238.07:47:32.07#ibcon#*mode == 0, iclass 29, count 2 2006.238.07:47:32.07#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.07:47:32.07#ibcon#[27=AT05-04\r\n] 2006.238.07:47:32.07#ibcon#*before write, iclass 29, count 2 2006.238.07:47:32.07#ibcon#enter sib2, iclass 29, count 2 2006.238.07:47:32.07#ibcon#flushed, iclass 29, count 2 2006.238.07:47:32.07#ibcon#about to write, iclass 29, count 2 2006.238.07:47:32.07#ibcon#wrote, iclass 29, count 2 2006.238.07:47:32.07#ibcon#about to read 3, iclass 29, count 2 2006.238.07:47:32.10#ibcon#read 3, iclass 29, count 2 2006.238.07:47:32.10#ibcon#about to read 4, iclass 29, count 2 2006.238.07:47:32.10#ibcon#read 4, iclass 29, count 2 2006.238.07:47:32.10#ibcon#about to read 5, iclass 29, count 2 2006.238.07:47:32.10#ibcon#read 5, iclass 29, count 2 2006.238.07:47:32.10#ibcon#about to read 6, iclass 29, count 2 2006.238.07:47:32.10#ibcon#read 6, iclass 29, count 2 2006.238.07:47:32.10#ibcon#end of sib2, iclass 29, count 2 2006.238.07:47:32.10#ibcon#*after write, iclass 29, count 2 2006.238.07:47:32.10#ibcon#*before return 0, iclass 29, count 2 2006.238.07:47:32.10#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:47:32.10#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:47:32.10#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.07:47:32.10#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:32.10#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:47:32.22#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:47:32.22#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:47:32.22#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:47:32.22#ibcon#first serial, iclass 29, count 0 2006.238.07:47:32.22#ibcon#enter sib2, iclass 29, count 0 2006.238.07:47:32.22#ibcon#flushed, iclass 29, count 0 2006.238.07:47:32.22#ibcon#about to write, iclass 29, count 0 2006.238.07:47:32.22#ibcon#wrote, iclass 29, count 0 2006.238.07:47:32.22#ibcon#about to read 3, iclass 29, count 0 2006.238.07:47:32.24#ibcon#read 3, iclass 29, count 0 2006.238.07:47:32.24#ibcon#about to read 4, iclass 29, count 0 2006.238.07:47:32.24#ibcon#read 4, iclass 29, count 0 2006.238.07:47:32.24#ibcon#about to read 5, iclass 29, count 0 2006.238.07:47:32.24#ibcon#read 5, iclass 29, count 0 2006.238.07:47:32.24#ibcon#about to read 6, iclass 29, count 0 2006.238.07:47:32.24#ibcon#read 6, iclass 29, count 0 2006.238.07:47:32.24#ibcon#end of sib2, iclass 29, count 0 2006.238.07:47:32.24#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:47:32.24#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:47:32.24#ibcon#[27=USB\r\n] 2006.238.07:47:32.24#ibcon#*before write, iclass 29, count 0 2006.238.07:47:32.24#ibcon#enter sib2, iclass 29, count 0 2006.238.07:47:32.24#ibcon#flushed, iclass 29, count 0 2006.238.07:47:32.24#ibcon#about to write, iclass 29, count 0 2006.238.07:47:32.24#ibcon#wrote, iclass 29, count 0 2006.238.07:47:32.24#ibcon#about to read 3, iclass 29, count 0 2006.238.07:47:32.27#ibcon#read 3, iclass 29, count 0 2006.238.07:47:32.27#ibcon#about to read 4, iclass 29, count 0 2006.238.07:47:32.27#ibcon#read 4, iclass 29, count 0 2006.238.07:47:32.27#ibcon#about to read 5, iclass 29, count 0 2006.238.07:47:32.27#ibcon#read 5, iclass 29, count 0 2006.238.07:47:32.27#ibcon#about to read 6, iclass 29, count 0 2006.238.07:47:32.27#ibcon#read 6, iclass 29, count 0 2006.238.07:47:32.27#ibcon#end of sib2, iclass 29, count 0 2006.238.07:47:32.27#ibcon#*after write, iclass 29, count 0 2006.238.07:47:32.27#ibcon#*before return 0, iclass 29, count 0 2006.238.07:47:32.27#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:47:32.27#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:47:32.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:47:32.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:47:32.27$vc4f8/vblo=6,752.99 2006.238.07:47:32.27#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.07:47:32.27#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.07:47:32.27#ibcon#ireg 17 cls_cnt 0 2006.238.07:47:32.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:47:32.27#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:47:32.27#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:47:32.27#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:47:32.27#ibcon#first serial, iclass 31, count 0 2006.238.07:47:32.27#ibcon#enter sib2, iclass 31, count 0 2006.238.07:47:32.27#ibcon#flushed, iclass 31, count 0 2006.238.07:47:32.27#ibcon#about to write, iclass 31, count 0 2006.238.07:47:32.27#ibcon#wrote, iclass 31, count 0 2006.238.07:47:32.27#ibcon#about to read 3, iclass 31, count 0 2006.238.07:47:32.29#ibcon#read 3, iclass 31, count 0 2006.238.07:47:32.29#ibcon#about to read 4, iclass 31, count 0 2006.238.07:47:32.29#ibcon#read 4, iclass 31, count 0 2006.238.07:47:32.29#ibcon#about to read 5, iclass 31, count 0 2006.238.07:47:32.29#ibcon#read 5, iclass 31, count 0 2006.238.07:47:32.29#ibcon#about to read 6, iclass 31, count 0 2006.238.07:47:32.29#ibcon#read 6, iclass 31, count 0 2006.238.07:47:32.29#ibcon#end of sib2, iclass 31, count 0 2006.238.07:47:32.29#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:47:32.29#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:47:32.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:47:32.29#ibcon#*before write, iclass 31, count 0 2006.238.07:47:32.29#ibcon#enter sib2, iclass 31, count 0 2006.238.07:47:32.29#ibcon#flushed, iclass 31, count 0 2006.238.07:47:32.29#ibcon#about to write, iclass 31, count 0 2006.238.07:47:32.29#ibcon#wrote, iclass 31, count 0 2006.238.07:47:32.29#ibcon#about to read 3, iclass 31, count 0 2006.238.07:47:32.33#ibcon#read 3, iclass 31, count 0 2006.238.07:47:32.33#ibcon#about to read 4, iclass 31, count 0 2006.238.07:47:32.33#ibcon#read 4, iclass 31, count 0 2006.238.07:47:32.33#ibcon#about to read 5, iclass 31, count 0 2006.238.07:47:32.33#ibcon#read 5, iclass 31, count 0 2006.238.07:47:32.33#ibcon#about to read 6, iclass 31, count 0 2006.238.07:47:32.33#ibcon#read 6, iclass 31, count 0 2006.238.07:47:32.33#ibcon#end of sib2, iclass 31, count 0 2006.238.07:47:32.33#ibcon#*after write, iclass 31, count 0 2006.238.07:47:32.33#ibcon#*before return 0, iclass 31, count 0 2006.238.07:47:32.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:47:32.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:47:32.33#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:47:32.33#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:47:32.33$vc4f8/vb=6,4 2006.238.07:47:32.33#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:47:32.33#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:47:32.33#ibcon#ireg 11 cls_cnt 2 2006.238.07:47:32.33#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:47:32.39#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:47:32.39#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:47:32.39#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:47:32.39#ibcon#first serial, iclass 33, count 2 2006.238.07:47:32.39#ibcon#enter sib2, iclass 33, count 2 2006.238.07:47:32.39#ibcon#flushed, iclass 33, count 2 2006.238.07:47:32.39#ibcon#about to write, iclass 33, count 2 2006.238.07:47:32.39#ibcon#wrote, iclass 33, count 2 2006.238.07:47:32.39#ibcon#about to read 3, iclass 33, count 2 2006.238.07:47:32.41#ibcon#read 3, iclass 33, count 2 2006.238.07:47:32.41#ibcon#about to read 4, iclass 33, count 2 2006.238.07:47:32.41#ibcon#read 4, iclass 33, count 2 2006.238.07:47:32.41#ibcon#about to read 5, iclass 33, count 2 2006.238.07:47:32.41#ibcon#read 5, iclass 33, count 2 2006.238.07:47:32.41#ibcon#about to read 6, iclass 33, count 2 2006.238.07:47:32.41#ibcon#read 6, iclass 33, count 2 2006.238.07:47:32.41#ibcon#end of sib2, iclass 33, count 2 2006.238.07:47:32.41#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:47:32.41#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:47:32.41#ibcon#[27=AT06-04\r\n] 2006.238.07:47:32.41#ibcon#*before write, iclass 33, count 2 2006.238.07:47:32.41#ibcon#enter sib2, iclass 33, count 2 2006.238.07:47:32.41#ibcon#flushed, iclass 33, count 2 2006.238.07:47:32.41#ibcon#about to write, iclass 33, count 2 2006.238.07:47:32.41#ibcon#wrote, iclass 33, count 2 2006.238.07:47:32.41#ibcon#about to read 3, iclass 33, count 2 2006.238.07:47:32.44#ibcon#read 3, iclass 33, count 2 2006.238.07:47:32.44#ibcon#about to read 4, iclass 33, count 2 2006.238.07:47:32.44#ibcon#read 4, iclass 33, count 2 2006.238.07:47:32.44#ibcon#about to read 5, iclass 33, count 2 2006.238.07:47:32.44#ibcon#read 5, iclass 33, count 2 2006.238.07:47:32.44#ibcon#about to read 6, iclass 33, count 2 2006.238.07:47:32.44#ibcon#read 6, iclass 33, count 2 2006.238.07:47:32.44#ibcon#end of sib2, iclass 33, count 2 2006.238.07:47:32.44#ibcon#*after write, iclass 33, count 2 2006.238.07:47:32.44#ibcon#*before return 0, iclass 33, count 2 2006.238.07:47:32.44#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:47:32.44#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:47:32.44#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:47:32.44#ibcon#ireg 7 cls_cnt 0 2006.238.07:47:32.44#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:47:32.56#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:47:32.56#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:47:32.56#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:47:32.56#ibcon#first serial, iclass 33, count 0 2006.238.07:47:32.56#ibcon#enter sib2, iclass 33, count 0 2006.238.07:47:32.56#ibcon#flushed, iclass 33, count 0 2006.238.07:47:32.56#ibcon#about to write, iclass 33, count 0 2006.238.07:47:32.56#ibcon#wrote, iclass 33, count 0 2006.238.07:47:32.56#ibcon#about to read 3, iclass 33, count 0 2006.238.07:47:32.58#ibcon#read 3, iclass 33, count 0 2006.238.07:47:32.58#ibcon#about to read 4, iclass 33, count 0 2006.238.07:47:32.58#ibcon#read 4, iclass 33, count 0 2006.238.07:47:32.58#ibcon#about to read 5, iclass 33, count 0 2006.238.07:47:32.58#ibcon#read 5, iclass 33, count 0 2006.238.07:47:32.58#ibcon#about to read 6, iclass 33, count 0 2006.238.07:47:32.58#ibcon#read 6, iclass 33, count 0 2006.238.07:47:32.58#ibcon#end of sib2, iclass 33, count 0 2006.238.07:47:32.58#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:47:32.58#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:47:32.58#ibcon#[27=USB\r\n] 2006.238.07:47:32.58#ibcon#*before write, iclass 33, count 0 2006.238.07:47:32.58#ibcon#enter sib2, iclass 33, count 0 2006.238.07:47:32.58#ibcon#flushed, iclass 33, count 0 2006.238.07:47:32.58#ibcon#about to write, iclass 33, count 0 2006.238.07:47:32.58#ibcon#wrote, iclass 33, count 0 2006.238.07:47:32.58#ibcon#about to read 3, iclass 33, count 0 2006.238.07:47:32.61#ibcon#read 3, iclass 33, count 0 2006.238.07:47:32.61#ibcon#about to read 4, iclass 33, count 0 2006.238.07:47:32.61#ibcon#read 4, iclass 33, count 0 2006.238.07:47:32.61#ibcon#about to read 5, iclass 33, count 0 2006.238.07:47:32.61#ibcon#read 5, iclass 33, count 0 2006.238.07:47:32.61#ibcon#about to read 6, iclass 33, count 0 2006.238.07:47:32.61#ibcon#read 6, iclass 33, count 0 2006.238.07:47:32.61#ibcon#end of sib2, iclass 33, count 0 2006.238.07:47:32.61#ibcon#*after write, iclass 33, count 0 2006.238.07:47:32.61#ibcon#*before return 0, iclass 33, count 0 2006.238.07:47:32.61#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:47:32.61#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:47:32.61#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:47:32.61#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:47:32.61$vc4f8/vabw=wide 2006.238.07:47:32.61#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:47:32.61#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:47:32.61#ibcon#ireg 8 cls_cnt 0 2006.238.07:47:32.61#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:47:32.61#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:47:32.61#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:47:32.61#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:47:32.61#ibcon#first serial, iclass 35, count 0 2006.238.07:47:32.61#ibcon#enter sib2, iclass 35, count 0 2006.238.07:47:32.61#ibcon#flushed, iclass 35, count 0 2006.238.07:47:32.61#ibcon#about to write, iclass 35, count 0 2006.238.07:47:32.61#ibcon#wrote, iclass 35, count 0 2006.238.07:47:32.61#ibcon#about to read 3, iclass 35, count 0 2006.238.07:47:32.63#ibcon#read 3, iclass 35, count 0 2006.238.07:47:32.63#ibcon#about to read 4, iclass 35, count 0 2006.238.07:47:32.63#ibcon#read 4, iclass 35, count 0 2006.238.07:47:32.63#ibcon#about to read 5, iclass 35, count 0 2006.238.07:47:32.63#ibcon#read 5, iclass 35, count 0 2006.238.07:47:32.63#ibcon#about to read 6, iclass 35, count 0 2006.238.07:47:32.63#ibcon#read 6, iclass 35, count 0 2006.238.07:47:32.63#ibcon#end of sib2, iclass 35, count 0 2006.238.07:47:32.63#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:47:32.63#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:47:32.63#ibcon#[25=BW32\r\n] 2006.238.07:47:32.63#ibcon#*before write, iclass 35, count 0 2006.238.07:47:32.63#ibcon#enter sib2, iclass 35, count 0 2006.238.07:47:32.63#ibcon#flushed, iclass 35, count 0 2006.238.07:47:32.63#ibcon#about to write, iclass 35, count 0 2006.238.07:47:32.63#ibcon#wrote, iclass 35, count 0 2006.238.07:47:32.63#ibcon#about to read 3, iclass 35, count 0 2006.238.07:47:32.66#ibcon#read 3, iclass 35, count 0 2006.238.07:47:32.66#ibcon#about to read 4, iclass 35, count 0 2006.238.07:47:32.66#ibcon#read 4, iclass 35, count 0 2006.238.07:47:32.66#ibcon#about to read 5, iclass 35, count 0 2006.238.07:47:32.66#ibcon#read 5, iclass 35, count 0 2006.238.07:47:32.66#ibcon#about to read 6, iclass 35, count 0 2006.238.07:47:32.66#ibcon#read 6, iclass 35, count 0 2006.238.07:47:32.66#ibcon#end of sib2, iclass 35, count 0 2006.238.07:47:32.66#ibcon#*after write, iclass 35, count 0 2006.238.07:47:32.66#ibcon#*before return 0, iclass 35, count 0 2006.238.07:47:32.66#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:47:32.66#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:47:32.66#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:47:32.66#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:47:32.66$vc4f8/vbbw=wide 2006.238.07:47:32.66#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.07:47:32.66#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.07:47:32.66#ibcon#ireg 8 cls_cnt 0 2006.238.07:47:32.66#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:47:32.73#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:47:32.73#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:47:32.73#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:47:32.73#ibcon#first serial, iclass 37, count 0 2006.238.07:47:32.73#ibcon#enter sib2, iclass 37, count 0 2006.238.07:47:32.73#ibcon#flushed, iclass 37, count 0 2006.238.07:47:32.73#ibcon#about to write, iclass 37, count 0 2006.238.07:47:32.73#ibcon#wrote, iclass 37, count 0 2006.238.07:47:32.73#ibcon#about to read 3, iclass 37, count 0 2006.238.07:47:32.75#ibcon#read 3, iclass 37, count 0 2006.238.07:47:32.75#ibcon#about to read 4, iclass 37, count 0 2006.238.07:47:32.75#ibcon#read 4, iclass 37, count 0 2006.238.07:47:32.75#ibcon#about to read 5, iclass 37, count 0 2006.238.07:47:32.75#ibcon#read 5, iclass 37, count 0 2006.238.07:47:32.75#ibcon#about to read 6, iclass 37, count 0 2006.238.07:47:32.75#ibcon#read 6, iclass 37, count 0 2006.238.07:47:32.75#ibcon#end of sib2, iclass 37, count 0 2006.238.07:47:32.75#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:47:32.75#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:47:32.75#ibcon#[27=BW32\r\n] 2006.238.07:47:32.75#ibcon#*before write, iclass 37, count 0 2006.238.07:47:32.75#ibcon#enter sib2, iclass 37, count 0 2006.238.07:47:32.75#ibcon#flushed, iclass 37, count 0 2006.238.07:47:32.75#ibcon#about to write, iclass 37, count 0 2006.238.07:47:32.75#ibcon#wrote, iclass 37, count 0 2006.238.07:47:32.75#ibcon#about to read 3, iclass 37, count 0 2006.238.07:47:32.78#ibcon#read 3, iclass 37, count 0 2006.238.07:47:32.78#ibcon#about to read 4, iclass 37, count 0 2006.238.07:47:32.78#ibcon#read 4, iclass 37, count 0 2006.238.07:47:32.78#ibcon#about to read 5, iclass 37, count 0 2006.238.07:47:32.78#ibcon#read 5, iclass 37, count 0 2006.238.07:47:32.78#ibcon#about to read 6, iclass 37, count 0 2006.238.07:47:32.78#ibcon#read 6, iclass 37, count 0 2006.238.07:47:32.78#ibcon#end of sib2, iclass 37, count 0 2006.238.07:47:32.78#ibcon#*after write, iclass 37, count 0 2006.238.07:47:32.78#ibcon#*before return 0, iclass 37, count 0 2006.238.07:47:32.78#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:47:32.78#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:47:32.78#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:47:32.78#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:47:32.78$4f8m12a/ifd4f 2006.238.07:47:32.78$ifd4f/lo= 2006.238.07:47:32.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:47:32.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:47:32.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:47:32.78$ifd4f/patch= 2006.238.07:47:32.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:47:32.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:47:32.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:47:32.78$4f8m12a/"form=m,16.000,1:2 2006.238.07:47:32.78$4f8m12a/"tpicd 2006.238.07:47:32.78$4f8m12a/echo=off 2006.238.07:47:32.78$4f8m12a/xlog=off 2006.238.07:47:32.78:!2006.238.07:48:00 2006.238.07:47:39.14#trakl#Source acquired 2006.238.07:47:39.14#flagr#flagr/antenna,acquired 2006.238.07:48:00.00:preob 2006.238.07:48:01.14/onsource/TRACKING 2006.238.07:48:01.14:!2006.238.07:48:10 2006.238.07:48:10.00:data_valid=on 2006.238.07:48:10.00:midob 2006.238.07:48:10.14/onsource/TRACKING 2006.238.07:48:10.14/wx/25.33,1012.2,87 2006.238.07:48:10.29/cable/+6.4178E-03 2006.238.07:48:11.38/va/01,08,usb,yes,31,33 2006.238.07:48:11.38/va/02,07,usb,yes,31,33 2006.238.07:48:11.38/va/03,07,usb,yes,29,30 2006.238.07:48:11.38/va/04,07,usb,yes,33,35 2006.238.07:48:11.38/va/05,08,usb,yes,30,32 2006.238.07:48:11.38/va/06,07,usb,yes,33,33 2006.238.07:48:11.38/va/07,07,usb,yes,33,33 2006.238.07:48:11.38/va/08,07,usb,yes,35,35 2006.238.07:48:11.61/valo/01,532.99,yes,locked 2006.238.07:48:11.61/valo/02,572.99,yes,locked 2006.238.07:48:11.61/valo/03,672.99,yes,locked 2006.238.07:48:11.61/valo/04,832.99,yes,locked 2006.238.07:48:11.61/valo/05,652.99,yes,locked 2006.238.07:48:11.61/valo/06,772.99,yes,locked 2006.238.07:48:11.61/valo/07,832.99,yes,locked 2006.238.07:48:11.61/valo/08,852.99,yes,locked 2006.238.07:48:12.70/vb/01,04,usb,yes,30,29 2006.238.07:48:12.70/vb/02,04,usb,yes,32,33 2006.238.07:48:12.70/vb/03,04,usb,yes,28,32 2006.238.07:48:12.70/vb/04,04,usb,yes,29,29 2006.238.07:48:12.70/vb/05,04,usb,yes,28,32 2006.238.07:48:12.70/vb/06,04,usb,yes,28,31 2006.238.07:48:12.70/vb/07,04,usb,yes,31,31 2006.238.07:48:12.70/vb/08,04,usb,yes,28,32 2006.238.07:48:12.94/vblo/01,632.99,yes,locked 2006.238.07:48:12.94/vblo/02,640.99,yes,locked 2006.238.07:48:12.94/vblo/03,656.99,yes,locked 2006.238.07:48:12.94/vblo/04,712.99,yes,locked 2006.238.07:48:12.94/vblo/05,744.99,yes,locked 2006.238.07:48:12.94/vblo/06,752.99,yes,locked 2006.238.07:48:12.94/vblo/07,734.99,yes,locked 2006.238.07:48:12.94/vblo/08,744.99,yes,locked 2006.238.07:48:13.09/vabw/8 2006.238.07:48:13.24/vbbw/8 2006.238.07:48:13.35/xfe/off,on,13.5 2006.238.07:48:13.73/ifatt/23,28,28,28 2006.238.07:48:14.08/fmout-gps/S +4.31E-07 2006.238.07:48:14.12:!2006.238.07:49:10 2006.238.07:49:10.00:data_valid=off 2006.238.07:49:10.00:postob 2006.238.07:49:10.18/cable/+6.4180E-03 2006.238.07:49:10.22/wx/25.34,1012.1,87 2006.238.07:49:11.08/fmout-gps/S +4.30E-07 2006.238.07:49:11.08:scan_name=238-0750,k06238,60 2006.238.07:49:11.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.238.07:49:11.14#flagr#flagr/antenna,new-source 2006.238.07:49:12.14:checkk5 2006.238.07:49:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:49:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:49:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:49:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:49:14.01/chk_obsdata//k5ts1/T2380748??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.07:49:14.38/chk_obsdata//k5ts2/T2380748??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.07:49:14.75/chk_obsdata//k5ts3/T2380748??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.07:49:15.12/chk_obsdata//k5ts4/T2380748??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.07:49:15.81/k5log//k5ts1_log_newline 2006.238.07:49:16.50/k5log//k5ts2_log_newline 2006.238.07:49:17.18/k5log//k5ts3_log_newline 2006.238.07:49:17.87/k5log//k5ts4_log_newline 2006.238.07:49:17.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:49:17.90:4f8m12a=1 2006.238.07:49:17.90$4f8m12a/echo=on 2006.238.07:49:17.90$4f8m12a/pcalon 2006.238.07:49:17.90$pcalon/"no phase cal control is implemented here 2006.238.07:49:17.90$4f8m12a/"tpicd=stop 2006.238.07:49:17.90$4f8m12a/vc4f8 2006.238.07:49:17.90$vc4f8/valo=1,532.99 2006.238.07:49:17.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.238.07:49:17.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.238.07:49:17.90#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:17.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:49:17.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:49:17.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:49:17.90#ibcon#enter wrdev, iclass 6, count 0 2006.238.07:49:17.90#ibcon#first serial, iclass 6, count 0 2006.238.07:49:17.90#ibcon#enter sib2, iclass 6, count 0 2006.238.07:49:17.90#ibcon#flushed, iclass 6, count 0 2006.238.07:49:17.90#ibcon#about to write, iclass 6, count 0 2006.238.07:49:17.90#ibcon#wrote, iclass 6, count 0 2006.238.07:49:17.90#ibcon#about to read 3, iclass 6, count 0 2006.238.07:49:17.94#ibcon#read 3, iclass 6, count 0 2006.238.07:49:17.94#ibcon#about to read 4, iclass 6, count 0 2006.238.07:49:17.94#ibcon#read 4, iclass 6, count 0 2006.238.07:49:17.94#ibcon#about to read 5, iclass 6, count 0 2006.238.07:49:17.94#ibcon#read 5, iclass 6, count 0 2006.238.07:49:17.94#ibcon#about to read 6, iclass 6, count 0 2006.238.07:49:17.94#ibcon#read 6, iclass 6, count 0 2006.238.07:49:17.94#ibcon#end of sib2, iclass 6, count 0 2006.238.07:49:17.94#ibcon#*mode == 0, iclass 6, count 0 2006.238.07:49:17.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.07:49:17.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:49:17.94#ibcon#*before write, iclass 6, count 0 2006.238.07:49:17.94#ibcon#enter sib2, iclass 6, count 0 2006.238.07:49:17.94#ibcon#flushed, iclass 6, count 0 2006.238.07:49:17.94#ibcon#about to write, iclass 6, count 0 2006.238.07:49:17.94#ibcon#wrote, iclass 6, count 0 2006.238.07:49:17.94#ibcon#about to read 3, iclass 6, count 0 2006.238.07:49:17.99#ibcon#read 3, iclass 6, count 0 2006.238.07:49:17.99#ibcon#about to read 4, iclass 6, count 0 2006.238.07:49:17.99#ibcon#read 4, iclass 6, count 0 2006.238.07:49:17.99#ibcon#about to read 5, iclass 6, count 0 2006.238.07:49:17.99#ibcon#read 5, iclass 6, count 0 2006.238.07:49:17.99#ibcon#about to read 6, iclass 6, count 0 2006.238.07:49:17.99#ibcon#read 6, iclass 6, count 0 2006.238.07:49:17.99#ibcon#end of sib2, iclass 6, count 0 2006.238.07:49:17.99#ibcon#*after write, iclass 6, count 0 2006.238.07:49:17.99#ibcon#*before return 0, iclass 6, count 0 2006.238.07:49:17.99#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:49:17.99#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:49:17.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.07:49:17.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.07:49:17.99$vc4f8/va=1,8 2006.238.07:49:17.99#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.238.07:49:17.99#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.238.07:49:17.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:17.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:49:17.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:49:17.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:49:17.99#ibcon#enter wrdev, iclass 10, count 2 2006.238.07:49:17.99#ibcon#first serial, iclass 10, count 2 2006.238.07:49:17.99#ibcon#enter sib2, iclass 10, count 2 2006.238.07:49:17.99#ibcon#flushed, iclass 10, count 2 2006.238.07:49:17.99#ibcon#about to write, iclass 10, count 2 2006.238.07:49:17.99#ibcon#wrote, iclass 10, count 2 2006.238.07:49:17.99#ibcon#about to read 3, iclass 10, count 2 2006.238.07:49:18.01#ibcon#read 3, iclass 10, count 2 2006.238.07:49:18.01#ibcon#about to read 4, iclass 10, count 2 2006.238.07:49:18.01#ibcon#read 4, iclass 10, count 2 2006.238.07:49:18.01#ibcon#about to read 5, iclass 10, count 2 2006.238.07:49:18.01#ibcon#read 5, iclass 10, count 2 2006.238.07:49:18.01#ibcon#about to read 6, iclass 10, count 2 2006.238.07:49:18.01#ibcon#read 6, iclass 10, count 2 2006.238.07:49:18.01#ibcon#end of sib2, iclass 10, count 2 2006.238.07:49:18.01#ibcon#*mode == 0, iclass 10, count 2 2006.238.07:49:18.01#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.238.07:49:18.01#ibcon#[25=AT01-08\r\n] 2006.238.07:49:18.01#ibcon#*before write, iclass 10, count 2 2006.238.07:49:18.01#ibcon#enter sib2, iclass 10, count 2 2006.238.07:49:18.01#ibcon#flushed, iclass 10, count 2 2006.238.07:49:18.01#ibcon#about to write, iclass 10, count 2 2006.238.07:49:18.01#ibcon#wrote, iclass 10, count 2 2006.238.07:49:18.01#ibcon#about to read 3, iclass 10, count 2 2006.238.07:49:18.04#ibcon#read 3, iclass 10, count 2 2006.238.07:49:18.04#ibcon#about to read 4, iclass 10, count 2 2006.238.07:49:18.04#ibcon#read 4, iclass 10, count 2 2006.238.07:49:18.04#ibcon#about to read 5, iclass 10, count 2 2006.238.07:49:18.04#ibcon#read 5, iclass 10, count 2 2006.238.07:49:18.04#ibcon#about to read 6, iclass 10, count 2 2006.238.07:49:18.04#ibcon#read 6, iclass 10, count 2 2006.238.07:49:18.04#ibcon#end of sib2, iclass 10, count 2 2006.238.07:49:18.04#ibcon#*after write, iclass 10, count 2 2006.238.07:49:18.04#ibcon#*before return 0, iclass 10, count 2 2006.238.07:49:18.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:49:18.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:49:18.04#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.238.07:49:18.04#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:18.04#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:49:18.16#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:49:18.16#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:49:18.16#ibcon#enter wrdev, iclass 10, count 0 2006.238.07:49:18.16#ibcon#first serial, iclass 10, count 0 2006.238.07:49:18.16#ibcon#enter sib2, iclass 10, count 0 2006.238.07:49:18.16#ibcon#flushed, iclass 10, count 0 2006.238.07:49:18.16#ibcon#about to write, iclass 10, count 0 2006.238.07:49:18.16#ibcon#wrote, iclass 10, count 0 2006.238.07:49:18.16#ibcon#about to read 3, iclass 10, count 0 2006.238.07:49:18.18#ibcon#read 3, iclass 10, count 0 2006.238.07:49:18.18#ibcon#about to read 4, iclass 10, count 0 2006.238.07:49:18.18#ibcon#read 4, iclass 10, count 0 2006.238.07:49:18.18#ibcon#about to read 5, iclass 10, count 0 2006.238.07:49:18.18#ibcon#read 5, iclass 10, count 0 2006.238.07:49:18.18#ibcon#about to read 6, iclass 10, count 0 2006.238.07:49:18.18#ibcon#read 6, iclass 10, count 0 2006.238.07:49:18.18#ibcon#end of sib2, iclass 10, count 0 2006.238.07:49:18.18#ibcon#*mode == 0, iclass 10, count 0 2006.238.07:49:18.18#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.07:49:18.18#ibcon#[25=USB\r\n] 2006.238.07:49:18.18#ibcon#*before write, iclass 10, count 0 2006.238.07:49:18.18#ibcon#enter sib2, iclass 10, count 0 2006.238.07:49:18.18#ibcon#flushed, iclass 10, count 0 2006.238.07:49:18.18#ibcon#about to write, iclass 10, count 0 2006.238.07:49:18.18#ibcon#wrote, iclass 10, count 0 2006.238.07:49:18.18#ibcon#about to read 3, iclass 10, count 0 2006.238.07:49:18.21#ibcon#read 3, iclass 10, count 0 2006.238.07:49:18.21#ibcon#about to read 4, iclass 10, count 0 2006.238.07:49:18.21#ibcon#read 4, iclass 10, count 0 2006.238.07:49:18.21#ibcon#about to read 5, iclass 10, count 0 2006.238.07:49:18.21#ibcon#read 5, iclass 10, count 0 2006.238.07:49:18.21#ibcon#about to read 6, iclass 10, count 0 2006.238.07:49:18.21#ibcon#read 6, iclass 10, count 0 2006.238.07:49:18.21#ibcon#end of sib2, iclass 10, count 0 2006.238.07:49:18.21#ibcon#*after write, iclass 10, count 0 2006.238.07:49:18.21#ibcon#*before return 0, iclass 10, count 0 2006.238.07:49:18.21#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:49:18.21#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:49:18.21#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.07:49:18.21#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.07:49:18.21$vc4f8/valo=2,572.99 2006.238.07:49:18.21#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.238.07:49:18.21#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.238.07:49:18.21#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:18.21#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:49:18.21#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:49:18.21#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:49:18.21#ibcon#enter wrdev, iclass 12, count 0 2006.238.07:49:18.21#ibcon#first serial, iclass 12, count 0 2006.238.07:49:18.21#ibcon#enter sib2, iclass 12, count 0 2006.238.07:49:18.21#ibcon#flushed, iclass 12, count 0 2006.238.07:49:18.21#ibcon#about to write, iclass 12, count 0 2006.238.07:49:18.21#ibcon#wrote, iclass 12, count 0 2006.238.07:49:18.21#ibcon#about to read 3, iclass 12, count 0 2006.238.07:49:18.23#ibcon#read 3, iclass 12, count 0 2006.238.07:49:18.23#ibcon#about to read 4, iclass 12, count 0 2006.238.07:49:18.23#ibcon#read 4, iclass 12, count 0 2006.238.07:49:18.23#ibcon#about to read 5, iclass 12, count 0 2006.238.07:49:18.23#ibcon#read 5, iclass 12, count 0 2006.238.07:49:18.23#ibcon#about to read 6, iclass 12, count 0 2006.238.07:49:18.23#ibcon#read 6, iclass 12, count 0 2006.238.07:49:18.23#ibcon#end of sib2, iclass 12, count 0 2006.238.07:49:18.23#ibcon#*mode == 0, iclass 12, count 0 2006.238.07:49:18.23#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.07:49:18.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:49:18.23#ibcon#*before write, iclass 12, count 0 2006.238.07:49:18.23#ibcon#enter sib2, iclass 12, count 0 2006.238.07:49:18.23#ibcon#flushed, iclass 12, count 0 2006.238.07:49:18.23#ibcon#about to write, iclass 12, count 0 2006.238.07:49:18.23#ibcon#wrote, iclass 12, count 0 2006.238.07:49:18.23#ibcon#about to read 3, iclass 12, count 0 2006.238.07:49:18.27#ibcon#read 3, iclass 12, count 0 2006.238.07:49:18.27#ibcon#about to read 4, iclass 12, count 0 2006.238.07:49:18.27#ibcon#read 4, iclass 12, count 0 2006.238.07:49:18.27#ibcon#about to read 5, iclass 12, count 0 2006.238.07:49:18.27#ibcon#read 5, iclass 12, count 0 2006.238.07:49:18.27#ibcon#about to read 6, iclass 12, count 0 2006.238.07:49:18.27#ibcon#read 6, iclass 12, count 0 2006.238.07:49:18.27#ibcon#end of sib2, iclass 12, count 0 2006.238.07:49:18.27#ibcon#*after write, iclass 12, count 0 2006.238.07:49:18.27#ibcon#*before return 0, iclass 12, count 0 2006.238.07:49:18.27#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:49:18.27#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:49:18.27#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.07:49:18.27#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.07:49:18.27$vc4f8/va=2,7 2006.238.07:49:18.27#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.238.07:49:18.27#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.238.07:49:18.27#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:18.27#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:49:18.33#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:49:18.33#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:49:18.33#ibcon#enter wrdev, iclass 14, count 2 2006.238.07:49:18.33#ibcon#first serial, iclass 14, count 2 2006.238.07:49:18.33#ibcon#enter sib2, iclass 14, count 2 2006.238.07:49:18.33#ibcon#flushed, iclass 14, count 2 2006.238.07:49:18.33#ibcon#about to write, iclass 14, count 2 2006.238.07:49:18.33#ibcon#wrote, iclass 14, count 2 2006.238.07:49:18.33#ibcon#about to read 3, iclass 14, count 2 2006.238.07:49:18.35#ibcon#read 3, iclass 14, count 2 2006.238.07:49:18.35#ibcon#about to read 4, iclass 14, count 2 2006.238.07:49:18.35#ibcon#read 4, iclass 14, count 2 2006.238.07:49:18.35#ibcon#about to read 5, iclass 14, count 2 2006.238.07:49:18.35#ibcon#read 5, iclass 14, count 2 2006.238.07:49:18.35#ibcon#about to read 6, iclass 14, count 2 2006.238.07:49:18.35#ibcon#read 6, iclass 14, count 2 2006.238.07:49:18.35#ibcon#end of sib2, iclass 14, count 2 2006.238.07:49:18.35#ibcon#*mode == 0, iclass 14, count 2 2006.238.07:49:18.35#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.238.07:49:18.35#ibcon#[25=AT02-07\r\n] 2006.238.07:49:18.35#ibcon#*before write, iclass 14, count 2 2006.238.07:49:18.35#ibcon#enter sib2, iclass 14, count 2 2006.238.07:49:18.35#ibcon#flushed, iclass 14, count 2 2006.238.07:49:18.35#ibcon#about to write, iclass 14, count 2 2006.238.07:49:18.35#ibcon#wrote, iclass 14, count 2 2006.238.07:49:18.35#ibcon#about to read 3, iclass 14, count 2 2006.238.07:49:18.39#ibcon#read 3, iclass 14, count 2 2006.238.07:49:18.39#ibcon#about to read 4, iclass 14, count 2 2006.238.07:49:18.39#ibcon#read 4, iclass 14, count 2 2006.238.07:49:18.39#ibcon#about to read 5, iclass 14, count 2 2006.238.07:49:18.39#ibcon#read 5, iclass 14, count 2 2006.238.07:49:18.39#ibcon#about to read 6, iclass 14, count 2 2006.238.07:49:18.39#ibcon#read 6, iclass 14, count 2 2006.238.07:49:18.39#ibcon#end of sib2, iclass 14, count 2 2006.238.07:49:18.39#ibcon#*after write, iclass 14, count 2 2006.238.07:49:18.39#ibcon#*before return 0, iclass 14, count 2 2006.238.07:49:18.39#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:49:18.39#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:49:18.39#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.238.07:49:18.39#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:18.39#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:49:18.51#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:49:18.51#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:49:18.51#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:49:18.51#ibcon#first serial, iclass 14, count 0 2006.238.07:49:18.51#ibcon#enter sib2, iclass 14, count 0 2006.238.07:49:18.51#ibcon#flushed, iclass 14, count 0 2006.238.07:49:18.51#ibcon#about to write, iclass 14, count 0 2006.238.07:49:18.51#ibcon#wrote, iclass 14, count 0 2006.238.07:49:18.51#ibcon#about to read 3, iclass 14, count 0 2006.238.07:49:18.53#ibcon#read 3, iclass 14, count 0 2006.238.07:49:18.53#ibcon#about to read 4, iclass 14, count 0 2006.238.07:49:18.53#ibcon#read 4, iclass 14, count 0 2006.238.07:49:18.53#ibcon#about to read 5, iclass 14, count 0 2006.238.07:49:18.53#ibcon#read 5, iclass 14, count 0 2006.238.07:49:18.53#ibcon#about to read 6, iclass 14, count 0 2006.238.07:49:18.53#ibcon#read 6, iclass 14, count 0 2006.238.07:49:18.53#ibcon#end of sib2, iclass 14, count 0 2006.238.07:49:18.53#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:49:18.53#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:49:18.53#ibcon#[25=USB\r\n] 2006.238.07:49:18.53#ibcon#*before write, iclass 14, count 0 2006.238.07:49:18.53#ibcon#enter sib2, iclass 14, count 0 2006.238.07:49:18.53#ibcon#flushed, iclass 14, count 0 2006.238.07:49:18.53#ibcon#about to write, iclass 14, count 0 2006.238.07:49:18.53#ibcon#wrote, iclass 14, count 0 2006.238.07:49:18.53#ibcon#about to read 3, iclass 14, count 0 2006.238.07:49:18.56#ibcon#read 3, iclass 14, count 0 2006.238.07:49:18.56#ibcon#about to read 4, iclass 14, count 0 2006.238.07:49:18.56#ibcon#read 4, iclass 14, count 0 2006.238.07:49:18.56#ibcon#about to read 5, iclass 14, count 0 2006.238.07:49:18.56#ibcon#read 5, iclass 14, count 0 2006.238.07:49:18.56#ibcon#about to read 6, iclass 14, count 0 2006.238.07:49:18.56#ibcon#read 6, iclass 14, count 0 2006.238.07:49:18.56#ibcon#end of sib2, iclass 14, count 0 2006.238.07:49:18.56#ibcon#*after write, iclass 14, count 0 2006.238.07:49:18.56#ibcon#*before return 0, iclass 14, count 0 2006.238.07:49:18.56#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:49:18.56#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:49:18.56#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:49:18.56#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:49:18.56$vc4f8/valo=3,672.99 2006.238.07:49:18.56#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.07:49:18.56#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.07:49:18.56#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:18.56#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:49:18.56#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:49:18.56#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:49:18.56#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:49:18.56#ibcon#first serial, iclass 16, count 0 2006.238.07:49:18.56#ibcon#enter sib2, iclass 16, count 0 2006.238.07:49:18.56#ibcon#flushed, iclass 16, count 0 2006.238.07:49:18.56#ibcon#about to write, iclass 16, count 0 2006.238.07:49:18.56#ibcon#wrote, iclass 16, count 0 2006.238.07:49:18.56#ibcon#about to read 3, iclass 16, count 0 2006.238.07:49:18.58#ibcon#read 3, iclass 16, count 0 2006.238.07:49:18.58#ibcon#about to read 4, iclass 16, count 0 2006.238.07:49:18.58#ibcon#read 4, iclass 16, count 0 2006.238.07:49:18.58#ibcon#about to read 5, iclass 16, count 0 2006.238.07:49:18.58#ibcon#read 5, iclass 16, count 0 2006.238.07:49:18.58#ibcon#about to read 6, iclass 16, count 0 2006.238.07:49:18.58#ibcon#read 6, iclass 16, count 0 2006.238.07:49:18.58#ibcon#end of sib2, iclass 16, count 0 2006.238.07:49:18.58#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:49:18.58#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:49:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:49:18.58#ibcon#*before write, iclass 16, count 0 2006.238.07:49:18.58#ibcon#enter sib2, iclass 16, count 0 2006.238.07:49:18.58#ibcon#flushed, iclass 16, count 0 2006.238.07:49:18.58#ibcon#about to write, iclass 16, count 0 2006.238.07:49:18.58#ibcon#wrote, iclass 16, count 0 2006.238.07:49:18.58#ibcon#about to read 3, iclass 16, count 0 2006.238.07:49:18.62#ibcon#read 3, iclass 16, count 0 2006.238.07:49:18.62#ibcon#about to read 4, iclass 16, count 0 2006.238.07:49:18.62#ibcon#read 4, iclass 16, count 0 2006.238.07:49:18.62#ibcon#about to read 5, iclass 16, count 0 2006.238.07:49:18.62#ibcon#read 5, iclass 16, count 0 2006.238.07:49:18.62#ibcon#about to read 6, iclass 16, count 0 2006.238.07:49:18.62#ibcon#read 6, iclass 16, count 0 2006.238.07:49:18.62#ibcon#end of sib2, iclass 16, count 0 2006.238.07:49:18.62#ibcon#*after write, iclass 16, count 0 2006.238.07:49:18.62#ibcon#*before return 0, iclass 16, count 0 2006.238.07:49:18.62#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:49:18.62#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:49:18.62#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:49:18.62#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:49:18.62$vc4f8/va=3,7 2006.238.07:49:18.62#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.238.07:49:18.62#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.238.07:49:18.62#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:18.62#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:49:18.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:49:18.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:49:18.68#ibcon#enter wrdev, iclass 18, count 2 2006.238.07:49:18.68#ibcon#first serial, iclass 18, count 2 2006.238.07:49:18.68#ibcon#enter sib2, iclass 18, count 2 2006.238.07:49:18.68#ibcon#flushed, iclass 18, count 2 2006.238.07:49:18.68#ibcon#about to write, iclass 18, count 2 2006.238.07:49:18.68#ibcon#wrote, iclass 18, count 2 2006.238.07:49:18.68#ibcon#about to read 3, iclass 18, count 2 2006.238.07:49:18.70#ibcon#read 3, iclass 18, count 2 2006.238.07:49:18.70#ibcon#about to read 4, iclass 18, count 2 2006.238.07:49:18.70#ibcon#read 4, iclass 18, count 2 2006.238.07:49:18.70#ibcon#about to read 5, iclass 18, count 2 2006.238.07:49:18.70#ibcon#read 5, iclass 18, count 2 2006.238.07:49:18.70#ibcon#about to read 6, iclass 18, count 2 2006.238.07:49:18.70#ibcon#read 6, iclass 18, count 2 2006.238.07:49:18.70#ibcon#end of sib2, iclass 18, count 2 2006.238.07:49:18.70#ibcon#*mode == 0, iclass 18, count 2 2006.238.07:49:18.70#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.238.07:49:18.70#ibcon#[25=AT03-07\r\n] 2006.238.07:49:18.70#ibcon#*before write, iclass 18, count 2 2006.238.07:49:18.70#ibcon#enter sib2, iclass 18, count 2 2006.238.07:49:18.70#ibcon#flushed, iclass 18, count 2 2006.238.07:49:18.70#ibcon#about to write, iclass 18, count 2 2006.238.07:49:18.70#ibcon#wrote, iclass 18, count 2 2006.238.07:49:18.70#ibcon#about to read 3, iclass 18, count 2 2006.238.07:49:18.73#ibcon#read 3, iclass 18, count 2 2006.238.07:49:18.73#ibcon#about to read 4, iclass 18, count 2 2006.238.07:49:18.73#ibcon#read 4, iclass 18, count 2 2006.238.07:49:18.73#ibcon#about to read 5, iclass 18, count 2 2006.238.07:49:18.73#ibcon#read 5, iclass 18, count 2 2006.238.07:49:18.73#ibcon#about to read 6, iclass 18, count 2 2006.238.07:49:18.73#ibcon#read 6, iclass 18, count 2 2006.238.07:49:18.73#ibcon#end of sib2, iclass 18, count 2 2006.238.07:49:18.73#ibcon#*after write, iclass 18, count 2 2006.238.07:49:18.73#ibcon#*before return 0, iclass 18, count 2 2006.238.07:49:18.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:49:18.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:49:18.73#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.238.07:49:18.73#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:18.73#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:49:18.85#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:49:18.85#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:49:18.85#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:49:18.85#ibcon#first serial, iclass 18, count 0 2006.238.07:49:18.85#ibcon#enter sib2, iclass 18, count 0 2006.238.07:49:18.85#ibcon#flushed, iclass 18, count 0 2006.238.07:49:18.85#ibcon#about to write, iclass 18, count 0 2006.238.07:49:18.85#ibcon#wrote, iclass 18, count 0 2006.238.07:49:18.85#ibcon#about to read 3, iclass 18, count 0 2006.238.07:49:18.87#ibcon#read 3, iclass 18, count 0 2006.238.07:49:18.87#ibcon#about to read 4, iclass 18, count 0 2006.238.07:49:18.87#ibcon#read 4, iclass 18, count 0 2006.238.07:49:18.87#ibcon#about to read 5, iclass 18, count 0 2006.238.07:49:18.87#ibcon#read 5, iclass 18, count 0 2006.238.07:49:18.87#ibcon#about to read 6, iclass 18, count 0 2006.238.07:49:18.87#ibcon#read 6, iclass 18, count 0 2006.238.07:49:18.87#ibcon#end of sib2, iclass 18, count 0 2006.238.07:49:18.87#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:49:18.87#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:49:18.87#ibcon#[25=USB\r\n] 2006.238.07:49:18.87#ibcon#*before write, iclass 18, count 0 2006.238.07:49:18.87#ibcon#enter sib2, iclass 18, count 0 2006.238.07:49:18.87#ibcon#flushed, iclass 18, count 0 2006.238.07:49:18.87#ibcon#about to write, iclass 18, count 0 2006.238.07:49:18.87#ibcon#wrote, iclass 18, count 0 2006.238.07:49:18.87#ibcon#about to read 3, iclass 18, count 0 2006.238.07:49:18.90#ibcon#read 3, iclass 18, count 0 2006.238.07:49:18.90#ibcon#about to read 4, iclass 18, count 0 2006.238.07:49:18.90#ibcon#read 4, iclass 18, count 0 2006.238.07:49:18.90#ibcon#about to read 5, iclass 18, count 0 2006.238.07:49:18.90#ibcon#read 5, iclass 18, count 0 2006.238.07:49:18.90#ibcon#about to read 6, iclass 18, count 0 2006.238.07:49:18.90#ibcon#read 6, iclass 18, count 0 2006.238.07:49:18.90#ibcon#end of sib2, iclass 18, count 0 2006.238.07:49:18.90#ibcon#*after write, iclass 18, count 0 2006.238.07:49:18.90#ibcon#*before return 0, iclass 18, count 0 2006.238.07:49:18.90#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:49:18.90#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:49:18.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:49:18.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:49:18.90$vc4f8/valo=4,832.99 2006.238.07:49:18.90#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.07:49:18.90#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.07:49:18.90#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:18.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:49:18.90#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:49:18.90#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:49:18.90#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:49:18.90#ibcon#first serial, iclass 20, count 0 2006.238.07:49:18.90#ibcon#enter sib2, iclass 20, count 0 2006.238.07:49:18.90#ibcon#flushed, iclass 20, count 0 2006.238.07:49:18.90#ibcon#about to write, iclass 20, count 0 2006.238.07:49:18.90#ibcon#wrote, iclass 20, count 0 2006.238.07:49:18.90#ibcon#about to read 3, iclass 20, count 0 2006.238.07:49:18.92#ibcon#read 3, iclass 20, count 0 2006.238.07:49:18.92#ibcon#about to read 4, iclass 20, count 0 2006.238.07:49:18.92#ibcon#read 4, iclass 20, count 0 2006.238.07:49:18.92#ibcon#about to read 5, iclass 20, count 0 2006.238.07:49:18.92#ibcon#read 5, iclass 20, count 0 2006.238.07:49:18.92#ibcon#about to read 6, iclass 20, count 0 2006.238.07:49:18.92#ibcon#read 6, iclass 20, count 0 2006.238.07:49:18.92#ibcon#end of sib2, iclass 20, count 0 2006.238.07:49:18.92#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:49:18.92#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:49:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:49:18.92#ibcon#*before write, iclass 20, count 0 2006.238.07:49:18.92#ibcon#enter sib2, iclass 20, count 0 2006.238.07:49:18.92#ibcon#flushed, iclass 20, count 0 2006.238.07:49:18.92#ibcon#about to write, iclass 20, count 0 2006.238.07:49:18.92#ibcon#wrote, iclass 20, count 0 2006.238.07:49:18.92#ibcon#about to read 3, iclass 20, count 0 2006.238.07:49:18.96#ibcon#read 3, iclass 20, count 0 2006.238.07:49:18.96#ibcon#about to read 4, iclass 20, count 0 2006.238.07:49:18.96#ibcon#read 4, iclass 20, count 0 2006.238.07:49:18.96#ibcon#about to read 5, iclass 20, count 0 2006.238.07:49:18.96#ibcon#read 5, iclass 20, count 0 2006.238.07:49:18.96#ibcon#about to read 6, iclass 20, count 0 2006.238.07:49:18.96#ibcon#read 6, iclass 20, count 0 2006.238.07:49:18.96#ibcon#end of sib2, iclass 20, count 0 2006.238.07:49:18.96#ibcon#*after write, iclass 20, count 0 2006.238.07:49:18.96#ibcon#*before return 0, iclass 20, count 0 2006.238.07:49:18.96#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:49:18.96#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:49:18.96#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:49:18.96#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:49:18.96$vc4f8/va=4,7 2006.238.07:49:18.96#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.238.07:49:18.96#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.238.07:49:18.96#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:18.96#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:49:19.02#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:49:19.02#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:49:19.02#ibcon#enter wrdev, iclass 22, count 2 2006.238.07:49:19.02#ibcon#first serial, iclass 22, count 2 2006.238.07:49:19.02#ibcon#enter sib2, iclass 22, count 2 2006.238.07:49:19.02#ibcon#flushed, iclass 22, count 2 2006.238.07:49:19.02#ibcon#about to write, iclass 22, count 2 2006.238.07:49:19.02#ibcon#wrote, iclass 22, count 2 2006.238.07:49:19.02#ibcon#about to read 3, iclass 22, count 2 2006.238.07:49:19.04#ibcon#read 3, iclass 22, count 2 2006.238.07:49:19.04#ibcon#about to read 4, iclass 22, count 2 2006.238.07:49:19.04#ibcon#read 4, iclass 22, count 2 2006.238.07:49:19.04#ibcon#about to read 5, iclass 22, count 2 2006.238.07:49:19.04#ibcon#read 5, iclass 22, count 2 2006.238.07:49:19.04#ibcon#about to read 6, iclass 22, count 2 2006.238.07:49:19.04#ibcon#read 6, iclass 22, count 2 2006.238.07:49:19.04#ibcon#end of sib2, iclass 22, count 2 2006.238.07:49:19.04#ibcon#*mode == 0, iclass 22, count 2 2006.238.07:49:19.04#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.238.07:49:19.04#ibcon#[25=AT04-07\r\n] 2006.238.07:49:19.04#ibcon#*before write, iclass 22, count 2 2006.238.07:49:19.04#ibcon#enter sib2, iclass 22, count 2 2006.238.07:49:19.04#ibcon#flushed, iclass 22, count 2 2006.238.07:49:19.04#ibcon#about to write, iclass 22, count 2 2006.238.07:49:19.04#ibcon#wrote, iclass 22, count 2 2006.238.07:49:19.04#ibcon#about to read 3, iclass 22, count 2 2006.238.07:49:19.07#ibcon#read 3, iclass 22, count 2 2006.238.07:49:19.07#ibcon#about to read 4, iclass 22, count 2 2006.238.07:49:19.07#ibcon#read 4, iclass 22, count 2 2006.238.07:49:19.07#ibcon#about to read 5, iclass 22, count 2 2006.238.07:49:19.07#ibcon#read 5, iclass 22, count 2 2006.238.07:49:19.07#ibcon#about to read 6, iclass 22, count 2 2006.238.07:49:19.07#ibcon#read 6, iclass 22, count 2 2006.238.07:49:19.07#ibcon#end of sib2, iclass 22, count 2 2006.238.07:49:19.07#ibcon#*after write, iclass 22, count 2 2006.238.07:49:19.07#ibcon#*before return 0, iclass 22, count 2 2006.238.07:49:19.07#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:49:19.07#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:49:19.07#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.238.07:49:19.07#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:19.07#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:49:19.19#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:49:19.19#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:49:19.19#ibcon#enter wrdev, iclass 22, count 0 2006.238.07:49:19.19#ibcon#first serial, iclass 22, count 0 2006.238.07:49:19.19#ibcon#enter sib2, iclass 22, count 0 2006.238.07:49:19.19#ibcon#flushed, iclass 22, count 0 2006.238.07:49:19.19#ibcon#about to write, iclass 22, count 0 2006.238.07:49:19.19#ibcon#wrote, iclass 22, count 0 2006.238.07:49:19.19#ibcon#about to read 3, iclass 22, count 0 2006.238.07:49:19.21#ibcon#read 3, iclass 22, count 0 2006.238.07:49:19.21#ibcon#about to read 4, iclass 22, count 0 2006.238.07:49:19.21#ibcon#read 4, iclass 22, count 0 2006.238.07:49:19.21#ibcon#about to read 5, iclass 22, count 0 2006.238.07:49:19.21#ibcon#read 5, iclass 22, count 0 2006.238.07:49:19.21#ibcon#about to read 6, iclass 22, count 0 2006.238.07:49:19.21#ibcon#read 6, iclass 22, count 0 2006.238.07:49:19.21#ibcon#end of sib2, iclass 22, count 0 2006.238.07:49:19.21#ibcon#*mode == 0, iclass 22, count 0 2006.238.07:49:19.21#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.07:49:19.21#ibcon#[25=USB\r\n] 2006.238.07:49:19.21#ibcon#*before write, iclass 22, count 0 2006.238.07:49:19.21#ibcon#enter sib2, iclass 22, count 0 2006.238.07:49:19.21#ibcon#flushed, iclass 22, count 0 2006.238.07:49:19.21#ibcon#about to write, iclass 22, count 0 2006.238.07:49:19.21#ibcon#wrote, iclass 22, count 0 2006.238.07:49:19.21#ibcon#about to read 3, iclass 22, count 0 2006.238.07:49:19.24#ibcon#read 3, iclass 22, count 0 2006.238.07:49:19.24#ibcon#about to read 4, iclass 22, count 0 2006.238.07:49:19.24#ibcon#read 4, iclass 22, count 0 2006.238.07:49:19.24#ibcon#about to read 5, iclass 22, count 0 2006.238.07:49:19.24#ibcon#read 5, iclass 22, count 0 2006.238.07:49:19.24#ibcon#about to read 6, iclass 22, count 0 2006.238.07:49:19.24#ibcon#read 6, iclass 22, count 0 2006.238.07:49:19.24#ibcon#end of sib2, iclass 22, count 0 2006.238.07:49:19.24#ibcon#*after write, iclass 22, count 0 2006.238.07:49:19.24#ibcon#*before return 0, iclass 22, count 0 2006.238.07:49:19.24#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:49:19.24#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:49:19.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.07:49:19.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.07:49:19.24$vc4f8/valo=5,652.99 2006.238.07:49:19.24#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.07:49:19.24#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.07:49:19.24#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:19.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:49:19.24#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:49:19.24#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:49:19.24#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:49:19.24#ibcon#first serial, iclass 24, count 0 2006.238.07:49:19.24#ibcon#enter sib2, iclass 24, count 0 2006.238.07:49:19.24#ibcon#flushed, iclass 24, count 0 2006.238.07:49:19.24#ibcon#about to write, iclass 24, count 0 2006.238.07:49:19.24#ibcon#wrote, iclass 24, count 0 2006.238.07:49:19.24#ibcon#about to read 3, iclass 24, count 0 2006.238.07:49:19.26#ibcon#read 3, iclass 24, count 0 2006.238.07:49:19.26#ibcon#about to read 4, iclass 24, count 0 2006.238.07:49:19.26#ibcon#read 4, iclass 24, count 0 2006.238.07:49:19.26#ibcon#about to read 5, iclass 24, count 0 2006.238.07:49:19.26#ibcon#read 5, iclass 24, count 0 2006.238.07:49:19.26#ibcon#about to read 6, iclass 24, count 0 2006.238.07:49:19.26#ibcon#read 6, iclass 24, count 0 2006.238.07:49:19.26#ibcon#end of sib2, iclass 24, count 0 2006.238.07:49:19.26#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:49:19.26#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:49:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:49:19.26#ibcon#*before write, iclass 24, count 0 2006.238.07:49:19.26#ibcon#enter sib2, iclass 24, count 0 2006.238.07:49:19.26#ibcon#flushed, iclass 24, count 0 2006.238.07:49:19.26#ibcon#about to write, iclass 24, count 0 2006.238.07:49:19.26#ibcon#wrote, iclass 24, count 0 2006.238.07:49:19.26#ibcon#about to read 3, iclass 24, count 0 2006.238.07:49:19.30#ibcon#read 3, iclass 24, count 0 2006.238.07:49:19.30#ibcon#about to read 4, iclass 24, count 0 2006.238.07:49:19.30#ibcon#read 4, iclass 24, count 0 2006.238.07:49:19.30#ibcon#about to read 5, iclass 24, count 0 2006.238.07:49:19.30#ibcon#read 5, iclass 24, count 0 2006.238.07:49:19.30#ibcon#about to read 6, iclass 24, count 0 2006.238.07:49:19.30#ibcon#read 6, iclass 24, count 0 2006.238.07:49:19.30#ibcon#end of sib2, iclass 24, count 0 2006.238.07:49:19.30#ibcon#*after write, iclass 24, count 0 2006.238.07:49:19.30#ibcon#*before return 0, iclass 24, count 0 2006.238.07:49:19.30#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:49:19.30#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:49:19.30#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:49:19.30#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:49:19.30$vc4f8/va=5,8 2006.238.07:49:19.30#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.238.07:49:19.30#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.238.07:49:19.30#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:19.30#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:49:19.36#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:49:19.36#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:49:19.36#ibcon#enter wrdev, iclass 26, count 2 2006.238.07:49:19.36#ibcon#first serial, iclass 26, count 2 2006.238.07:49:19.36#ibcon#enter sib2, iclass 26, count 2 2006.238.07:49:19.36#ibcon#flushed, iclass 26, count 2 2006.238.07:49:19.36#ibcon#about to write, iclass 26, count 2 2006.238.07:49:19.36#ibcon#wrote, iclass 26, count 2 2006.238.07:49:19.36#ibcon#about to read 3, iclass 26, count 2 2006.238.07:49:19.38#ibcon#read 3, iclass 26, count 2 2006.238.07:49:19.38#ibcon#about to read 4, iclass 26, count 2 2006.238.07:49:19.38#ibcon#read 4, iclass 26, count 2 2006.238.07:49:19.38#ibcon#about to read 5, iclass 26, count 2 2006.238.07:49:19.38#ibcon#read 5, iclass 26, count 2 2006.238.07:49:19.38#ibcon#about to read 6, iclass 26, count 2 2006.238.07:49:19.38#ibcon#read 6, iclass 26, count 2 2006.238.07:49:19.38#ibcon#end of sib2, iclass 26, count 2 2006.238.07:49:19.38#ibcon#*mode == 0, iclass 26, count 2 2006.238.07:49:19.38#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.238.07:49:19.38#ibcon#[25=AT05-08\r\n] 2006.238.07:49:19.38#ibcon#*before write, iclass 26, count 2 2006.238.07:49:19.38#ibcon#enter sib2, iclass 26, count 2 2006.238.07:49:19.38#ibcon#flushed, iclass 26, count 2 2006.238.07:49:19.38#ibcon#about to write, iclass 26, count 2 2006.238.07:49:19.38#ibcon#wrote, iclass 26, count 2 2006.238.07:49:19.38#ibcon#about to read 3, iclass 26, count 2 2006.238.07:49:19.41#ibcon#read 3, iclass 26, count 2 2006.238.07:49:19.41#ibcon#about to read 4, iclass 26, count 2 2006.238.07:49:19.41#ibcon#read 4, iclass 26, count 2 2006.238.07:49:19.41#ibcon#about to read 5, iclass 26, count 2 2006.238.07:49:19.41#ibcon#read 5, iclass 26, count 2 2006.238.07:49:19.41#ibcon#about to read 6, iclass 26, count 2 2006.238.07:49:19.41#ibcon#read 6, iclass 26, count 2 2006.238.07:49:19.41#ibcon#end of sib2, iclass 26, count 2 2006.238.07:49:19.41#ibcon#*after write, iclass 26, count 2 2006.238.07:49:19.41#ibcon#*before return 0, iclass 26, count 2 2006.238.07:49:19.41#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:49:19.41#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:49:19.41#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.238.07:49:19.41#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:19.41#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:49:19.53#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:49:19.53#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:49:19.53#ibcon#enter wrdev, iclass 26, count 0 2006.238.07:49:19.53#ibcon#first serial, iclass 26, count 0 2006.238.07:49:19.53#ibcon#enter sib2, iclass 26, count 0 2006.238.07:49:19.53#ibcon#flushed, iclass 26, count 0 2006.238.07:49:19.53#ibcon#about to write, iclass 26, count 0 2006.238.07:49:19.53#ibcon#wrote, iclass 26, count 0 2006.238.07:49:19.53#ibcon#about to read 3, iclass 26, count 0 2006.238.07:49:19.55#ibcon#read 3, iclass 26, count 0 2006.238.07:49:19.55#ibcon#about to read 4, iclass 26, count 0 2006.238.07:49:19.55#ibcon#read 4, iclass 26, count 0 2006.238.07:49:19.55#ibcon#about to read 5, iclass 26, count 0 2006.238.07:49:19.55#ibcon#read 5, iclass 26, count 0 2006.238.07:49:19.55#ibcon#about to read 6, iclass 26, count 0 2006.238.07:49:19.55#ibcon#read 6, iclass 26, count 0 2006.238.07:49:19.55#ibcon#end of sib2, iclass 26, count 0 2006.238.07:49:19.55#ibcon#*mode == 0, iclass 26, count 0 2006.238.07:49:19.55#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.07:49:19.55#ibcon#[25=USB\r\n] 2006.238.07:49:19.55#ibcon#*before write, iclass 26, count 0 2006.238.07:49:19.55#ibcon#enter sib2, iclass 26, count 0 2006.238.07:49:19.55#ibcon#flushed, iclass 26, count 0 2006.238.07:49:19.55#ibcon#about to write, iclass 26, count 0 2006.238.07:49:19.55#ibcon#wrote, iclass 26, count 0 2006.238.07:49:19.55#ibcon#about to read 3, iclass 26, count 0 2006.238.07:49:19.58#ibcon#read 3, iclass 26, count 0 2006.238.07:49:19.58#ibcon#about to read 4, iclass 26, count 0 2006.238.07:49:19.58#ibcon#read 4, iclass 26, count 0 2006.238.07:49:19.58#ibcon#about to read 5, iclass 26, count 0 2006.238.07:49:19.58#ibcon#read 5, iclass 26, count 0 2006.238.07:49:19.58#ibcon#about to read 6, iclass 26, count 0 2006.238.07:49:19.58#ibcon#read 6, iclass 26, count 0 2006.238.07:49:19.58#ibcon#end of sib2, iclass 26, count 0 2006.238.07:49:19.58#ibcon#*after write, iclass 26, count 0 2006.238.07:49:19.58#ibcon#*before return 0, iclass 26, count 0 2006.238.07:49:19.58#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:49:19.58#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:49:19.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.07:49:19.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.07:49:19.58$vc4f8/valo=6,772.99 2006.238.07:49:19.58#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.238.07:49:19.58#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.238.07:49:19.58#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:19.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:49:19.58#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:49:19.58#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:49:19.58#ibcon#enter wrdev, iclass 28, count 0 2006.238.07:49:19.58#ibcon#first serial, iclass 28, count 0 2006.238.07:49:19.58#ibcon#enter sib2, iclass 28, count 0 2006.238.07:49:19.58#ibcon#flushed, iclass 28, count 0 2006.238.07:49:19.58#ibcon#about to write, iclass 28, count 0 2006.238.07:49:19.58#ibcon#wrote, iclass 28, count 0 2006.238.07:49:19.58#ibcon#about to read 3, iclass 28, count 0 2006.238.07:49:19.60#ibcon#read 3, iclass 28, count 0 2006.238.07:49:19.60#ibcon#about to read 4, iclass 28, count 0 2006.238.07:49:19.60#ibcon#read 4, iclass 28, count 0 2006.238.07:49:19.60#ibcon#about to read 5, iclass 28, count 0 2006.238.07:49:19.60#ibcon#read 5, iclass 28, count 0 2006.238.07:49:19.60#ibcon#about to read 6, iclass 28, count 0 2006.238.07:49:19.60#ibcon#read 6, iclass 28, count 0 2006.238.07:49:19.60#ibcon#end of sib2, iclass 28, count 0 2006.238.07:49:19.60#ibcon#*mode == 0, iclass 28, count 0 2006.238.07:49:19.60#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.07:49:19.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:49:19.60#ibcon#*before write, iclass 28, count 0 2006.238.07:49:19.60#ibcon#enter sib2, iclass 28, count 0 2006.238.07:49:19.60#ibcon#flushed, iclass 28, count 0 2006.238.07:49:19.60#ibcon#about to write, iclass 28, count 0 2006.238.07:49:19.60#ibcon#wrote, iclass 28, count 0 2006.238.07:49:19.60#ibcon#about to read 3, iclass 28, count 0 2006.238.07:49:19.64#ibcon#read 3, iclass 28, count 0 2006.238.07:49:19.64#ibcon#about to read 4, iclass 28, count 0 2006.238.07:49:19.64#ibcon#read 4, iclass 28, count 0 2006.238.07:49:19.64#ibcon#about to read 5, iclass 28, count 0 2006.238.07:49:19.64#ibcon#read 5, iclass 28, count 0 2006.238.07:49:19.64#ibcon#about to read 6, iclass 28, count 0 2006.238.07:49:19.64#ibcon#read 6, iclass 28, count 0 2006.238.07:49:19.64#ibcon#end of sib2, iclass 28, count 0 2006.238.07:49:19.64#ibcon#*after write, iclass 28, count 0 2006.238.07:49:19.64#ibcon#*before return 0, iclass 28, count 0 2006.238.07:49:19.64#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:49:19.64#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:49:19.64#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.07:49:19.64#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.07:49:19.64$vc4f8/va=6,7 2006.238.07:49:19.64#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.238.07:49:19.64#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.238.07:49:19.64#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:19.64#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:49:19.70#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:49:19.70#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:49:19.70#ibcon#enter wrdev, iclass 30, count 2 2006.238.07:49:19.70#ibcon#first serial, iclass 30, count 2 2006.238.07:49:19.70#ibcon#enter sib2, iclass 30, count 2 2006.238.07:49:19.70#ibcon#flushed, iclass 30, count 2 2006.238.07:49:19.70#ibcon#about to write, iclass 30, count 2 2006.238.07:49:19.70#ibcon#wrote, iclass 30, count 2 2006.238.07:49:19.70#ibcon#about to read 3, iclass 30, count 2 2006.238.07:49:19.72#ibcon#read 3, iclass 30, count 2 2006.238.07:49:19.72#ibcon#about to read 4, iclass 30, count 2 2006.238.07:49:19.72#ibcon#read 4, iclass 30, count 2 2006.238.07:49:19.72#ibcon#about to read 5, iclass 30, count 2 2006.238.07:49:19.72#ibcon#read 5, iclass 30, count 2 2006.238.07:49:19.72#ibcon#about to read 6, iclass 30, count 2 2006.238.07:49:19.72#ibcon#read 6, iclass 30, count 2 2006.238.07:49:19.72#ibcon#end of sib2, iclass 30, count 2 2006.238.07:49:19.72#ibcon#*mode == 0, iclass 30, count 2 2006.238.07:49:19.72#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.238.07:49:19.72#ibcon#[25=AT06-07\r\n] 2006.238.07:49:19.72#ibcon#*before write, iclass 30, count 2 2006.238.07:49:19.72#ibcon#enter sib2, iclass 30, count 2 2006.238.07:49:19.72#ibcon#flushed, iclass 30, count 2 2006.238.07:49:19.72#ibcon#about to write, iclass 30, count 2 2006.238.07:49:19.72#ibcon#wrote, iclass 30, count 2 2006.238.07:49:19.72#ibcon#about to read 3, iclass 30, count 2 2006.238.07:49:19.75#ibcon#read 3, iclass 30, count 2 2006.238.07:49:19.75#ibcon#about to read 4, iclass 30, count 2 2006.238.07:49:19.75#ibcon#read 4, iclass 30, count 2 2006.238.07:49:19.75#ibcon#about to read 5, iclass 30, count 2 2006.238.07:49:19.75#ibcon#read 5, iclass 30, count 2 2006.238.07:49:19.75#ibcon#about to read 6, iclass 30, count 2 2006.238.07:49:19.75#ibcon#read 6, iclass 30, count 2 2006.238.07:49:19.75#ibcon#end of sib2, iclass 30, count 2 2006.238.07:49:19.75#ibcon#*after write, iclass 30, count 2 2006.238.07:49:19.75#ibcon#*before return 0, iclass 30, count 2 2006.238.07:49:19.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:49:19.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.238.07:49:19.75#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.238.07:49:19.75#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:19.75#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:49:19.87#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:49:19.87#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:49:19.87#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:49:19.87#ibcon#first serial, iclass 30, count 0 2006.238.07:49:19.87#ibcon#enter sib2, iclass 30, count 0 2006.238.07:49:19.87#ibcon#flushed, iclass 30, count 0 2006.238.07:49:19.87#ibcon#about to write, iclass 30, count 0 2006.238.07:49:19.87#ibcon#wrote, iclass 30, count 0 2006.238.07:49:19.87#ibcon#about to read 3, iclass 30, count 0 2006.238.07:49:19.89#ibcon#read 3, iclass 30, count 0 2006.238.07:49:19.89#ibcon#about to read 4, iclass 30, count 0 2006.238.07:49:19.89#ibcon#read 4, iclass 30, count 0 2006.238.07:49:19.89#ibcon#about to read 5, iclass 30, count 0 2006.238.07:49:19.89#ibcon#read 5, iclass 30, count 0 2006.238.07:49:19.89#ibcon#about to read 6, iclass 30, count 0 2006.238.07:49:19.89#ibcon#read 6, iclass 30, count 0 2006.238.07:49:19.89#ibcon#end of sib2, iclass 30, count 0 2006.238.07:49:19.89#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:49:19.89#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:49:19.89#ibcon#[25=USB\r\n] 2006.238.07:49:19.89#ibcon#*before write, iclass 30, count 0 2006.238.07:49:19.89#ibcon#enter sib2, iclass 30, count 0 2006.238.07:49:19.89#ibcon#flushed, iclass 30, count 0 2006.238.07:49:19.89#ibcon#about to write, iclass 30, count 0 2006.238.07:49:19.89#ibcon#wrote, iclass 30, count 0 2006.238.07:49:19.89#ibcon#about to read 3, iclass 30, count 0 2006.238.07:49:19.92#ibcon#read 3, iclass 30, count 0 2006.238.07:49:19.92#ibcon#about to read 4, iclass 30, count 0 2006.238.07:49:19.92#ibcon#read 4, iclass 30, count 0 2006.238.07:49:19.92#ibcon#about to read 5, iclass 30, count 0 2006.238.07:49:19.92#ibcon#read 5, iclass 30, count 0 2006.238.07:49:19.92#ibcon#about to read 6, iclass 30, count 0 2006.238.07:49:19.92#ibcon#read 6, iclass 30, count 0 2006.238.07:49:19.92#ibcon#end of sib2, iclass 30, count 0 2006.238.07:49:19.92#ibcon#*after write, iclass 30, count 0 2006.238.07:49:19.92#ibcon#*before return 0, iclass 30, count 0 2006.238.07:49:19.92#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:49:19.92#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.238.07:49:19.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:49:19.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:49:19.92$vc4f8/valo=7,832.99 2006.238.07:49:19.92#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.07:49:19.92#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.07:49:19.92#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:19.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:49:19.92#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:49:19.92#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:49:19.92#ibcon#enter wrdev, iclass 32, count 0 2006.238.07:49:19.92#ibcon#first serial, iclass 32, count 0 2006.238.07:49:19.92#ibcon#enter sib2, iclass 32, count 0 2006.238.07:49:19.92#ibcon#flushed, iclass 32, count 0 2006.238.07:49:19.92#ibcon#about to write, iclass 32, count 0 2006.238.07:49:19.92#ibcon#wrote, iclass 32, count 0 2006.238.07:49:19.92#ibcon#about to read 3, iclass 32, count 0 2006.238.07:49:19.94#ibcon#read 3, iclass 32, count 0 2006.238.07:49:19.94#ibcon#about to read 4, iclass 32, count 0 2006.238.07:49:19.94#ibcon#read 4, iclass 32, count 0 2006.238.07:49:19.94#ibcon#about to read 5, iclass 32, count 0 2006.238.07:49:19.94#ibcon#read 5, iclass 32, count 0 2006.238.07:49:19.94#ibcon#about to read 6, iclass 32, count 0 2006.238.07:49:19.94#ibcon#read 6, iclass 32, count 0 2006.238.07:49:19.94#ibcon#end of sib2, iclass 32, count 0 2006.238.07:49:19.94#ibcon#*mode == 0, iclass 32, count 0 2006.238.07:49:19.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.07:49:19.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:49:19.94#ibcon#*before write, iclass 32, count 0 2006.238.07:49:19.94#ibcon#enter sib2, iclass 32, count 0 2006.238.07:49:19.94#ibcon#flushed, iclass 32, count 0 2006.238.07:49:19.94#ibcon#about to write, iclass 32, count 0 2006.238.07:49:19.94#ibcon#wrote, iclass 32, count 0 2006.238.07:49:19.94#ibcon#about to read 3, iclass 32, count 0 2006.238.07:49:19.98#ibcon#read 3, iclass 32, count 0 2006.238.07:49:19.98#ibcon#about to read 4, iclass 32, count 0 2006.238.07:49:19.98#ibcon#read 4, iclass 32, count 0 2006.238.07:49:19.98#ibcon#about to read 5, iclass 32, count 0 2006.238.07:49:19.98#ibcon#read 5, iclass 32, count 0 2006.238.07:49:19.98#ibcon#about to read 6, iclass 32, count 0 2006.238.07:49:19.98#ibcon#read 6, iclass 32, count 0 2006.238.07:49:19.98#ibcon#end of sib2, iclass 32, count 0 2006.238.07:49:19.98#ibcon#*after write, iclass 32, count 0 2006.238.07:49:19.98#ibcon#*before return 0, iclass 32, count 0 2006.238.07:49:19.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:49:19.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.07:49:19.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.07:49:19.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.07:49:19.98$vc4f8/va=7,7 2006.238.07:49:19.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.238.07:49:19.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.238.07:49:19.98#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:19.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:49:20.04#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:49:20.04#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:49:20.04#ibcon#enter wrdev, iclass 34, count 2 2006.238.07:49:20.04#ibcon#first serial, iclass 34, count 2 2006.238.07:49:20.04#ibcon#enter sib2, iclass 34, count 2 2006.238.07:49:20.04#ibcon#flushed, iclass 34, count 2 2006.238.07:49:20.04#ibcon#about to write, iclass 34, count 2 2006.238.07:49:20.04#ibcon#wrote, iclass 34, count 2 2006.238.07:49:20.04#ibcon#about to read 3, iclass 34, count 2 2006.238.07:49:20.06#ibcon#read 3, iclass 34, count 2 2006.238.07:49:20.06#ibcon#about to read 4, iclass 34, count 2 2006.238.07:49:20.06#ibcon#read 4, iclass 34, count 2 2006.238.07:49:20.06#ibcon#about to read 5, iclass 34, count 2 2006.238.07:49:20.06#ibcon#read 5, iclass 34, count 2 2006.238.07:49:20.06#ibcon#about to read 6, iclass 34, count 2 2006.238.07:49:20.06#ibcon#read 6, iclass 34, count 2 2006.238.07:49:20.06#ibcon#end of sib2, iclass 34, count 2 2006.238.07:49:20.06#ibcon#*mode == 0, iclass 34, count 2 2006.238.07:49:20.06#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.238.07:49:20.06#ibcon#[25=AT07-07\r\n] 2006.238.07:49:20.06#ibcon#*before write, iclass 34, count 2 2006.238.07:49:20.06#ibcon#enter sib2, iclass 34, count 2 2006.238.07:49:20.06#ibcon#flushed, iclass 34, count 2 2006.238.07:49:20.06#ibcon#about to write, iclass 34, count 2 2006.238.07:49:20.06#ibcon#wrote, iclass 34, count 2 2006.238.07:49:20.06#ibcon#about to read 3, iclass 34, count 2 2006.238.07:49:20.09#ibcon#read 3, iclass 34, count 2 2006.238.07:49:20.09#ibcon#about to read 4, iclass 34, count 2 2006.238.07:49:20.09#ibcon#read 4, iclass 34, count 2 2006.238.07:49:20.09#ibcon#about to read 5, iclass 34, count 2 2006.238.07:49:20.09#ibcon#read 5, iclass 34, count 2 2006.238.07:49:20.09#ibcon#about to read 6, iclass 34, count 2 2006.238.07:49:20.09#ibcon#read 6, iclass 34, count 2 2006.238.07:49:20.09#ibcon#end of sib2, iclass 34, count 2 2006.238.07:49:20.09#ibcon#*after write, iclass 34, count 2 2006.238.07:49:20.09#ibcon#*before return 0, iclass 34, count 2 2006.238.07:49:20.09#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:49:20.09#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.238.07:49:20.09#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.238.07:49:20.09#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:20.09#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:49:20.21#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:49:20.21#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:49:20.21#ibcon#enter wrdev, iclass 34, count 0 2006.238.07:49:20.21#ibcon#first serial, iclass 34, count 0 2006.238.07:49:20.21#ibcon#enter sib2, iclass 34, count 0 2006.238.07:49:20.21#ibcon#flushed, iclass 34, count 0 2006.238.07:49:20.21#ibcon#about to write, iclass 34, count 0 2006.238.07:49:20.21#ibcon#wrote, iclass 34, count 0 2006.238.07:49:20.21#ibcon#about to read 3, iclass 34, count 0 2006.238.07:49:20.24#ibcon#read 3, iclass 34, count 0 2006.238.07:49:20.24#ibcon#about to read 4, iclass 34, count 0 2006.238.07:49:20.24#ibcon#read 4, iclass 34, count 0 2006.238.07:49:20.24#ibcon#about to read 5, iclass 34, count 0 2006.238.07:49:20.24#ibcon#read 5, iclass 34, count 0 2006.238.07:49:20.24#ibcon#about to read 6, iclass 34, count 0 2006.238.07:49:20.24#ibcon#read 6, iclass 34, count 0 2006.238.07:49:20.24#ibcon#end of sib2, iclass 34, count 0 2006.238.07:49:20.24#ibcon#*mode == 0, iclass 34, count 0 2006.238.07:49:20.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.07:49:20.24#ibcon#[25=USB\r\n] 2006.238.07:49:20.24#ibcon#*before write, iclass 34, count 0 2006.238.07:49:20.24#ibcon#enter sib2, iclass 34, count 0 2006.238.07:49:20.24#ibcon#flushed, iclass 34, count 0 2006.238.07:49:20.24#ibcon#about to write, iclass 34, count 0 2006.238.07:49:20.24#ibcon#wrote, iclass 34, count 0 2006.238.07:49:20.24#ibcon#about to read 3, iclass 34, count 0 2006.238.07:49:20.28#ibcon#read 3, iclass 34, count 0 2006.238.07:49:20.28#ibcon#about to read 4, iclass 34, count 0 2006.238.07:49:20.28#ibcon#read 4, iclass 34, count 0 2006.238.07:49:20.28#ibcon#about to read 5, iclass 34, count 0 2006.238.07:49:20.28#ibcon#read 5, iclass 34, count 0 2006.238.07:49:20.28#ibcon#about to read 6, iclass 34, count 0 2006.238.07:49:20.28#ibcon#read 6, iclass 34, count 0 2006.238.07:49:20.28#ibcon#end of sib2, iclass 34, count 0 2006.238.07:49:20.28#ibcon#*after write, iclass 34, count 0 2006.238.07:49:20.28#ibcon#*before return 0, iclass 34, count 0 2006.238.07:49:20.28#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:49:20.28#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.238.07:49:20.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.07:49:20.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.07:49:20.28$vc4f8/valo=8,852.99 2006.238.07:49:20.28#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.07:49:20.28#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.07:49:20.28#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:20.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:49:20.28#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:49:20.28#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:49:20.28#ibcon#enter wrdev, iclass 36, count 0 2006.238.07:49:20.28#ibcon#first serial, iclass 36, count 0 2006.238.07:49:20.28#ibcon#enter sib2, iclass 36, count 0 2006.238.07:49:20.28#ibcon#flushed, iclass 36, count 0 2006.238.07:49:20.28#ibcon#about to write, iclass 36, count 0 2006.238.07:49:20.28#ibcon#wrote, iclass 36, count 0 2006.238.07:49:20.28#ibcon#about to read 3, iclass 36, count 0 2006.238.07:49:20.30#ibcon#read 3, iclass 36, count 0 2006.238.07:49:20.30#ibcon#about to read 4, iclass 36, count 0 2006.238.07:49:20.30#ibcon#read 4, iclass 36, count 0 2006.238.07:49:20.30#ibcon#about to read 5, iclass 36, count 0 2006.238.07:49:20.30#ibcon#read 5, iclass 36, count 0 2006.238.07:49:20.30#ibcon#about to read 6, iclass 36, count 0 2006.238.07:49:20.30#ibcon#read 6, iclass 36, count 0 2006.238.07:49:20.30#ibcon#end of sib2, iclass 36, count 0 2006.238.07:49:20.30#ibcon#*mode == 0, iclass 36, count 0 2006.238.07:49:20.30#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.07:49:20.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:49:20.30#ibcon#*before write, iclass 36, count 0 2006.238.07:49:20.30#ibcon#enter sib2, iclass 36, count 0 2006.238.07:49:20.30#ibcon#flushed, iclass 36, count 0 2006.238.07:49:20.30#ibcon#about to write, iclass 36, count 0 2006.238.07:49:20.30#ibcon#wrote, iclass 36, count 0 2006.238.07:49:20.30#ibcon#about to read 3, iclass 36, count 0 2006.238.07:49:20.34#ibcon#read 3, iclass 36, count 0 2006.238.07:49:20.34#ibcon#about to read 4, iclass 36, count 0 2006.238.07:49:20.34#ibcon#read 4, iclass 36, count 0 2006.238.07:49:20.34#ibcon#about to read 5, iclass 36, count 0 2006.238.07:49:20.34#ibcon#read 5, iclass 36, count 0 2006.238.07:49:20.34#ibcon#about to read 6, iclass 36, count 0 2006.238.07:49:20.34#ibcon#read 6, iclass 36, count 0 2006.238.07:49:20.34#ibcon#end of sib2, iclass 36, count 0 2006.238.07:49:20.34#ibcon#*after write, iclass 36, count 0 2006.238.07:49:20.34#ibcon#*before return 0, iclass 36, count 0 2006.238.07:49:20.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:49:20.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.07:49:20.34#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.07:49:20.34#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.07:49:20.34$vc4f8/va=8,7 2006.238.07:49:20.34#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.238.07:49:20.34#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.238.07:49:20.34#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:20.34#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:49:20.40#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:49:20.40#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:49:20.40#ibcon#enter wrdev, iclass 38, count 2 2006.238.07:49:20.40#ibcon#first serial, iclass 38, count 2 2006.238.07:49:20.40#ibcon#enter sib2, iclass 38, count 2 2006.238.07:49:20.40#ibcon#flushed, iclass 38, count 2 2006.238.07:49:20.40#ibcon#about to write, iclass 38, count 2 2006.238.07:49:20.40#ibcon#wrote, iclass 38, count 2 2006.238.07:49:20.40#ibcon#about to read 3, iclass 38, count 2 2006.238.07:49:20.42#ibcon#read 3, iclass 38, count 2 2006.238.07:49:20.42#ibcon#about to read 4, iclass 38, count 2 2006.238.07:49:20.42#ibcon#read 4, iclass 38, count 2 2006.238.07:49:20.42#ibcon#about to read 5, iclass 38, count 2 2006.238.07:49:20.42#ibcon#read 5, iclass 38, count 2 2006.238.07:49:20.42#ibcon#about to read 6, iclass 38, count 2 2006.238.07:49:20.42#ibcon#read 6, iclass 38, count 2 2006.238.07:49:20.42#ibcon#end of sib2, iclass 38, count 2 2006.238.07:49:20.42#ibcon#*mode == 0, iclass 38, count 2 2006.238.07:49:20.42#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.238.07:49:20.42#ibcon#[25=AT08-07\r\n] 2006.238.07:49:20.42#ibcon#*before write, iclass 38, count 2 2006.238.07:49:20.42#ibcon#enter sib2, iclass 38, count 2 2006.238.07:49:20.42#ibcon#flushed, iclass 38, count 2 2006.238.07:49:20.42#ibcon#about to write, iclass 38, count 2 2006.238.07:49:20.42#ibcon#wrote, iclass 38, count 2 2006.238.07:49:20.42#ibcon#about to read 3, iclass 38, count 2 2006.238.07:49:20.45#ibcon#read 3, iclass 38, count 2 2006.238.07:49:20.45#ibcon#about to read 4, iclass 38, count 2 2006.238.07:49:20.45#ibcon#read 4, iclass 38, count 2 2006.238.07:49:20.45#ibcon#about to read 5, iclass 38, count 2 2006.238.07:49:20.45#ibcon#read 5, iclass 38, count 2 2006.238.07:49:20.45#ibcon#about to read 6, iclass 38, count 2 2006.238.07:49:20.45#ibcon#read 6, iclass 38, count 2 2006.238.07:49:20.45#ibcon#end of sib2, iclass 38, count 2 2006.238.07:49:20.45#ibcon#*after write, iclass 38, count 2 2006.238.07:49:20.45#ibcon#*before return 0, iclass 38, count 2 2006.238.07:49:20.45#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:49:20.45#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.238.07:49:20.45#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.238.07:49:20.45#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:20.45#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:49:20.57#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:49:20.57#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:49:20.57#ibcon#enter wrdev, iclass 38, count 0 2006.238.07:49:20.57#ibcon#first serial, iclass 38, count 0 2006.238.07:49:20.57#ibcon#enter sib2, iclass 38, count 0 2006.238.07:49:20.57#ibcon#flushed, iclass 38, count 0 2006.238.07:49:20.57#ibcon#about to write, iclass 38, count 0 2006.238.07:49:20.57#ibcon#wrote, iclass 38, count 0 2006.238.07:49:20.57#ibcon#about to read 3, iclass 38, count 0 2006.238.07:49:20.59#ibcon#read 3, iclass 38, count 0 2006.238.07:49:20.59#ibcon#about to read 4, iclass 38, count 0 2006.238.07:49:20.59#ibcon#read 4, iclass 38, count 0 2006.238.07:49:20.59#ibcon#about to read 5, iclass 38, count 0 2006.238.07:49:20.59#ibcon#read 5, iclass 38, count 0 2006.238.07:49:20.59#ibcon#about to read 6, iclass 38, count 0 2006.238.07:49:20.59#ibcon#read 6, iclass 38, count 0 2006.238.07:49:20.59#ibcon#end of sib2, iclass 38, count 0 2006.238.07:49:20.59#ibcon#*mode == 0, iclass 38, count 0 2006.238.07:49:20.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.07:49:20.59#ibcon#[25=USB\r\n] 2006.238.07:49:20.59#ibcon#*before write, iclass 38, count 0 2006.238.07:49:20.59#ibcon#enter sib2, iclass 38, count 0 2006.238.07:49:20.59#ibcon#flushed, iclass 38, count 0 2006.238.07:49:20.59#ibcon#about to write, iclass 38, count 0 2006.238.07:49:20.59#ibcon#wrote, iclass 38, count 0 2006.238.07:49:20.59#ibcon#about to read 3, iclass 38, count 0 2006.238.07:49:20.62#ibcon#read 3, iclass 38, count 0 2006.238.07:49:20.62#ibcon#about to read 4, iclass 38, count 0 2006.238.07:49:20.62#ibcon#read 4, iclass 38, count 0 2006.238.07:49:20.62#ibcon#about to read 5, iclass 38, count 0 2006.238.07:49:20.62#ibcon#read 5, iclass 38, count 0 2006.238.07:49:20.62#ibcon#about to read 6, iclass 38, count 0 2006.238.07:49:20.62#ibcon#read 6, iclass 38, count 0 2006.238.07:49:20.62#ibcon#end of sib2, iclass 38, count 0 2006.238.07:49:20.62#ibcon#*after write, iclass 38, count 0 2006.238.07:49:20.62#ibcon#*before return 0, iclass 38, count 0 2006.238.07:49:20.62#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:49:20.62#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.238.07:49:20.62#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.07:49:20.62#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.07:49:20.62$vc4f8/vblo=1,632.99 2006.238.07:49:20.62#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.07:49:20.62#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.07:49:20.62#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:20.62#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:49:20.62#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:49:20.62#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:49:20.62#ibcon#enter wrdev, iclass 40, count 0 2006.238.07:49:20.62#ibcon#first serial, iclass 40, count 0 2006.238.07:49:20.62#ibcon#enter sib2, iclass 40, count 0 2006.238.07:49:20.62#ibcon#flushed, iclass 40, count 0 2006.238.07:49:20.62#ibcon#about to write, iclass 40, count 0 2006.238.07:49:20.62#ibcon#wrote, iclass 40, count 0 2006.238.07:49:20.62#ibcon#about to read 3, iclass 40, count 0 2006.238.07:49:20.64#ibcon#read 3, iclass 40, count 0 2006.238.07:49:20.64#ibcon#about to read 4, iclass 40, count 0 2006.238.07:49:20.64#ibcon#read 4, iclass 40, count 0 2006.238.07:49:20.64#ibcon#about to read 5, iclass 40, count 0 2006.238.07:49:20.64#ibcon#read 5, iclass 40, count 0 2006.238.07:49:20.64#ibcon#about to read 6, iclass 40, count 0 2006.238.07:49:20.64#ibcon#read 6, iclass 40, count 0 2006.238.07:49:20.64#ibcon#end of sib2, iclass 40, count 0 2006.238.07:49:20.64#ibcon#*mode == 0, iclass 40, count 0 2006.238.07:49:20.64#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.07:49:20.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:49:20.64#ibcon#*before write, iclass 40, count 0 2006.238.07:49:20.64#ibcon#enter sib2, iclass 40, count 0 2006.238.07:49:20.64#ibcon#flushed, iclass 40, count 0 2006.238.07:49:20.64#ibcon#about to write, iclass 40, count 0 2006.238.07:49:20.64#ibcon#wrote, iclass 40, count 0 2006.238.07:49:20.64#ibcon#about to read 3, iclass 40, count 0 2006.238.07:49:20.68#ibcon#read 3, iclass 40, count 0 2006.238.07:49:20.68#ibcon#about to read 4, iclass 40, count 0 2006.238.07:49:20.68#ibcon#read 4, iclass 40, count 0 2006.238.07:49:20.68#ibcon#about to read 5, iclass 40, count 0 2006.238.07:49:20.68#ibcon#read 5, iclass 40, count 0 2006.238.07:49:20.68#ibcon#about to read 6, iclass 40, count 0 2006.238.07:49:20.68#ibcon#read 6, iclass 40, count 0 2006.238.07:49:20.68#ibcon#end of sib2, iclass 40, count 0 2006.238.07:49:20.68#ibcon#*after write, iclass 40, count 0 2006.238.07:49:20.68#ibcon#*before return 0, iclass 40, count 0 2006.238.07:49:20.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:49:20.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.07:49:20.68#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.07:49:20.68#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.07:49:20.68$vc4f8/vb=1,4 2006.238.07:49:20.68#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.238.07:49:20.68#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.238.07:49:20.68#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:20.68#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:49:20.68#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:49:20.68#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:49:20.68#ibcon#enter wrdev, iclass 4, count 2 2006.238.07:49:20.68#ibcon#first serial, iclass 4, count 2 2006.238.07:49:20.68#ibcon#enter sib2, iclass 4, count 2 2006.238.07:49:20.68#ibcon#flushed, iclass 4, count 2 2006.238.07:49:20.68#ibcon#about to write, iclass 4, count 2 2006.238.07:49:20.68#ibcon#wrote, iclass 4, count 2 2006.238.07:49:20.68#ibcon#about to read 3, iclass 4, count 2 2006.238.07:49:20.70#ibcon#read 3, iclass 4, count 2 2006.238.07:49:20.70#ibcon#about to read 4, iclass 4, count 2 2006.238.07:49:20.70#ibcon#read 4, iclass 4, count 2 2006.238.07:49:20.70#ibcon#about to read 5, iclass 4, count 2 2006.238.07:49:20.70#ibcon#read 5, iclass 4, count 2 2006.238.07:49:20.70#ibcon#about to read 6, iclass 4, count 2 2006.238.07:49:20.70#ibcon#read 6, iclass 4, count 2 2006.238.07:49:20.70#ibcon#end of sib2, iclass 4, count 2 2006.238.07:49:20.70#ibcon#*mode == 0, iclass 4, count 2 2006.238.07:49:20.70#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.238.07:49:20.70#ibcon#[27=AT01-04\r\n] 2006.238.07:49:20.70#ibcon#*before write, iclass 4, count 2 2006.238.07:49:20.70#ibcon#enter sib2, iclass 4, count 2 2006.238.07:49:20.70#ibcon#flushed, iclass 4, count 2 2006.238.07:49:20.70#ibcon#about to write, iclass 4, count 2 2006.238.07:49:20.70#ibcon#wrote, iclass 4, count 2 2006.238.07:49:20.70#ibcon#about to read 3, iclass 4, count 2 2006.238.07:49:20.73#ibcon#read 3, iclass 4, count 2 2006.238.07:49:20.73#ibcon#about to read 4, iclass 4, count 2 2006.238.07:49:20.73#ibcon#read 4, iclass 4, count 2 2006.238.07:49:20.73#ibcon#about to read 5, iclass 4, count 2 2006.238.07:49:20.73#ibcon#read 5, iclass 4, count 2 2006.238.07:49:20.73#ibcon#about to read 6, iclass 4, count 2 2006.238.07:49:20.73#ibcon#read 6, iclass 4, count 2 2006.238.07:49:20.73#ibcon#end of sib2, iclass 4, count 2 2006.238.07:49:20.73#ibcon#*after write, iclass 4, count 2 2006.238.07:49:20.73#ibcon#*before return 0, iclass 4, count 2 2006.238.07:49:20.73#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:49:20.73#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.238.07:49:20.73#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.238.07:49:20.73#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:20.73#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:49:20.85#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:49:20.85#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:49:20.85#ibcon#enter wrdev, iclass 4, count 0 2006.238.07:49:20.85#ibcon#first serial, iclass 4, count 0 2006.238.07:49:20.85#ibcon#enter sib2, iclass 4, count 0 2006.238.07:49:20.85#ibcon#flushed, iclass 4, count 0 2006.238.07:49:20.85#ibcon#about to write, iclass 4, count 0 2006.238.07:49:20.85#ibcon#wrote, iclass 4, count 0 2006.238.07:49:20.85#ibcon#about to read 3, iclass 4, count 0 2006.238.07:49:20.87#ibcon#read 3, iclass 4, count 0 2006.238.07:49:20.87#ibcon#about to read 4, iclass 4, count 0 2006.238.07:49:20.87#ibcon#read 4, iclass 4, count 0 2006.238.07:49:20.87#ibcon#about to read 5, iclass 4, count 0 2006.238.07:49:20.87#ibcon#read 5, iclass 4, count 0 2006.238.07:49:20.87#ibcon#about to read 6, iclass 4, count 0 2006.238.07:49:20.87#ibcon#read 6, iclass 4, count 0 2006.238.07:49:20.87#ibcon#end of sib2, iclass 4, count 0 2006.238.07:49:20.87#ibcon#*mode == 0, iclass 4, count 0 2006.238.07:49:20.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.07:49:20.87#ibcon#[27=USB\r\n] 2006.238.07:49:20.87#ibcon#*before write, iclass 4, count 0 2006.238.07:49:20.87#ibcon#enter sib2, iclass 4, count 0 2006.238.07:49:20.87#ibcon#flushed, iclass 4, count 0 2006.238.07:49:20.87#ibcon#about to write, iclass 4, count 0 2006.238.07:49:20.87#ibcon#wrote, iclass 4, count 0 2006.238.07:49:20.87#ibcon#about to read 3, iclass 4, count 0 2006.238.07:49:20.90#ibcon#read 3, iclass 4, count 0 2006.238.07:49:20.90#ibcon#about to read 4, iclass 4, count 0 2006.238.07:49:20.90#ibcon#read 4, iclass 4, count 0 2006.238.07:49:20.90#ibcon#about to read 5, iclass 4, count 0 2006.238.07:49:20.90#ibcon#read 5, iclass 4, count 0 2006.238.07:49:20.90#ibcon#about to read 6, iclass 4, count 0 2006.238.07:49:20.90#ibcon#read 6, iclass 4, count 0 2006.238.07:49:20.90#ibcon#end of sib2, iclass 4, count 0 2006.238.07:49:20.90#ibcon#*after write, iclass 4, count 0 2006.238.07:49:20.90#ibcon#*before return 0, iclass 4, count 0 2006.238.07:49:20.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:49:20.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.238.07:49:20.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.07:49:20.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.07:49:20.90$vc4f8/vblo=2,640.99 2006.238.07:49:20.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.238.07:49:20.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.238.07:49:20.90#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:20.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:49:20.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:49:20.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:49:20.90#ibcon#enter wrdev, iclass 6, count 0 2006.238.07:49:20.90#ibcon#first serial, iclass 6, count 0 2006.238.07:49:20.90#ibcon#enter sib2, iclass 6, count 0 2006.238.07:49:20.90#ibcon#flushed, iclass 6, count 0 2006.238.07:49:20.90#ibcon#about to write, iclass 6, count 0 2006.238.07:49:20.90#ibcon#wrote, iclass 6, count 0 2006.238.07:49:20.90#ibcon#about to read 3, iclass 6, count 0 2006.238.07:49:20.92#ibcon#read 3, iclass 6, count 0 2006.238.07:49:20.92#ibcon#about to read 4, iclass 6, count 0 2006.238.07:49:20.92#ibcon#read 4, iclass 6, count 0 2006.238.07:49:20.92#ibcon#about to read 5, iclass 6, count 0 2006.238.07:49:20.92#ibcon#read 5, iclass 6, count 0 2006.238.07:49:20.92#ibcon#about to read 6, iclass 6, count 0 2006.238.07:49:20.92#ibcon#read 6, iclass 6, count 0 2006.238.07:49:20.92#ibcon#end of sib2, iclass 6, count 0 2006.238.07:49:20.92#ibcon#*mode == 0, iclass 6, count 0 2006.238.07:49:20.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.07:49:20.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:49:20.92#ibcon#*before write, iclass 6, count 0 2006.238.07:49:20.92#ibcon#enter sib2, iclass 6, count 0 2006.238.07:49:20.92#ibcon#flushed, iclass 6, count 0 2006.238.07:49:20.92#ibcon#about to write, iclass 6, count 0 2006.238.07:49:20.92#ibcon#wrote, iclass 6, count 0 2006.238.07:49:20.92#ibcon#about to read 3, iclass 6, count 0 2006.238.07:49:20.96#ibcon#read 3, iclass 6, count 0 2006.238.07:49:20.96#ibcon#about to read 4, iclass 6, count 0 2006.238.07:49:20.96#ibcon#read 4, iclass 6, count 0 2006.238.07:49:20.96#ibcon#about to read 5, iclass 6, count 0 2006.238.07:49:20.96#ibcon#read 5, iclass 6, count 0 2006.238.07:49:20.96#ibcon#about to read 6, iclass 6, count 0 2006.238.07:49:20.96#ibcon#read 6, iclass 6, count 0 2006.238.07:49:20.96#ibcon#end of sib2, iclass 6, count 0 2006.238.07:49:20.96#ibcon#*after write, iclass 6, count 0 2006.238.07:49:20.96#ibcon#*before return 0, iclass 6, count 0 2006.238.07:49:20.96#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:49:20.96#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.238.07:49:20.96#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.07:49:20.96#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.07:49:20.96$vc4f8/vb=2,4 2006.238.07:49:20.96#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.238.07:49:20.96#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.238.07:49:20.96#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:20.96#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:49:21.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:49:21.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:49:21.02#ibcon#enter wrdev, iclass 10, count 2 2006.238.07:49:21.02#ibcon#first serial, iclass 10, count 2 2006.238.07:49:21.02#ibcon#enter sib2, iclass 10, count 2 2006.238.07:49:21.02#ibcon#flushed, iclass 10, count 2 2006.238.07:49:21.02#ibcon#about to write, iclass 10, count 2 2006.238.07:49:21.02#ibcon#wrote, iclass 10, count 2 2006.238.07:49:21.02#ibcon#about to read 3, iclass 10, count 2 2006.238.07:49:21.04#ibcon#read 3, iclass 10, count 2 2006.238.07:49:21.04#ibcon#about to read 4, iclass 10, count 2 2006.238.07:49:21.04#ibcon#read 4, iclass 10, count 2 2006.238.07:49:21.04#ibcon#about to read 5, iclass 10, count 2 2006.238.07:49:21.04#ibcon#read 5, iclass 10, count 2 2006.238.07:49:21.04#ibcon#about to read 6, iclass 10, count 2 2006.238.07:49:21.04#ibcon#read 6, iclass 10, count 2 2006.238.07:49:21.04#ibcon#end of sib2, iclass 10, count 2 2006.238.07:49:21.04#ibcon#*mode == 0, iclass 10, count 2 2006.238.07:49:21.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.238.07:49:21.04#ibcon#[27=AT02-04\r\n] 2006.238.07:49:21.04#ibcon#*before write, iclass 10, count 2 2006.238.07:49:21.04#ibcon#enter sib2, iclass 10, count 2 2006.238.07:49:21.04#ibcon#flushed, iclass 10, count 2 2006.238.07:49:21.04#ibcon#about to write, iclass 10, count 2 2006.238.07:49:21.04#ibcon#wrote, iclass 10, count 2 2006.238.07:49:21.04#ibcon#about to read 3, iclass 10, count 2 2006.238.07:49:21.07#ibcon#read 3, iclass 10, count 2 2006.238.07:49:21.07#ibcon#about to read 4, iclass 10, count 2 2006.238.07:49:21.07#ibcon#read 4, iclass 10, count 2 2006.238.07:49:21.07#ibcon#about to read 5, iclass 10, count 2 2006.238.07:49:21.07#ibcon#read 5, iclass 10, count 2 2006.238.07:49:21.07#ibcon#about to read 6, iclass 10, count 2 2006.238.07:49:21.07#ibcon#read 6, iclass 10, count 2 2006.238.07:49:21.07#ibcon#end of sib2, iclass 10, count 2 2006.238.07:49:21.07#ibcon#*after write, iclass 10, count 2 2006.238.07:49:21.07#ibcon#*before return 0, iclass 10, count 2 2006.238.07:49:21.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:49:21.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.238.07:49:21.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.238.07:49:21.07#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:21.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:49:21.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:49:21.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:49:21.19#ibcon#enter wrdev, iclass 10, count 0 2006.238.07:49:21.19#ibcon#first serial, iclass 10, count 0 2006.238.07:49:21.19#ibcon#enter sib2, iclass 10, count 0 2006.238.07:49:21.19#ibcon#flushed, iclass 10, count 0 2006.238.07:49:21.19#ibcon#about to write, iclass 10, count 0 2006.238.07:49:21.19#ibcon#wrote, iclass 10, count 0 2006.238.07:49:21.19#ibcon#about to read 3, iclass 10, count 0 2006.238.07:49:21.21#ibcon#read 3, iclass 10, count 0 2006.238.07:49:21.21#ibcon#about to read 4, iclass 10, count 0 2006.238.07:49:21.21#ibcon#read 4, iclass 10, count 0 2006.238.07:49:21.21#ibcon#about to read 5, iclass 10, count 0 2006.238.07:49:21.21#ibcon#read 5, iclass 10, count 0 2006.238.07:49:21.21#ibcon#about to read 6, iclass 10, count 0 2006.238.07:49:21.21#ibcon#read 6, iclass 10, count 0 2006.238.07:49:21.21#ibcon#end of sib2, iclass 10, count 0 2006.238.07:49:21.21#ibcon#*mode == 0, iclass 10, count 0 2006.238.07:49:21.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.07:49:21.21#ibcon#[27=USB\r\n] 2006.238.07:49:21.21#ibcon#*before write, iclass 10, count 0 2006.238.07:49:21.21#ibcon#enter sib2, iclass 10, count 0 2006.238.07:49:21.21#ibcon#flushed, iclass 10, count 0 2006.238.07:49:21.21#ibcon#about to write, iclass 10, count 0 2006.238.07:49:21.21#ibcon#wrote, iclass 10, count 0 2006.238.07:49:21.21#ibcon#about to read 3, iclass 10, count 0 2006.238.07:49:21.24#ibcon#read 3, iclass 10, count 0 2006.238.07:49:21.24#ibcon#about to read 4, iclass 10, count 0 2006.238.07:49:21.24#ibcon#read 4, iclass 10, count 0 2006.238.07:49:21.24#ibcon#about to read 5, iclass 10, count 0 2006.238.07:49:21.24#ibcon#read 5, iclass 10, count 0 2006.238.07:49:21.24#ibcon#about to read 6, iclass 10, count 0 2006.238.07:49:21.24#ibcon#read 6, iclass 10, count 0 2006.238.07:49:21.24#ibcon#end of sib2, iclass 10, count 0 2006.238.07:49:21.24#ibcon#*after write, iclass 10, count 0 2006.238.07:49:21.24#ibcon#*before return 0, iclass 10, count 0 2006.238.07:49:21.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:49:21.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.238.07:49:21.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.07:49:21.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.07:49:21.24$vc4f8/vblo=3,656.99 2006.238.07:49:21.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.238.07:49:21.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.238.07:49:21.24#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:21.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:49:21.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:49:21.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:49:21.24#ibcon#enter wrdev, iclass 12, count 0 2006.238.07:49:21.24#ibcon#first serial, iclass 12, count 0 2006.238.07:49:21.24#ibcon#enter sib2, iclass 12, count 0 2006.238.07:49:21.24#ibcon#flushed, iclass 12, count 0 2006.238.07:49:21.24#ibcon#about to write, iclass 12, count 0 2006.238.07:49:21.24#ibcon#wrote, iclass 12, count 0 2006.238.07:49:21.24#ibcon#about to read 3, iclass 12, count 0 2006.238.07:49:21.26#ibcon#read 3, iclass 12, count 0 2006.238.07:49:21.26#ibcon#about to read 4, iclass 12, count 0 2006.238.07:49:21.26#ibcon#read 4, iclass 12, count 0 2006.238.07:49:21.26#ibcon#about to read 5, iclass 12, count 0 2006.238.07:49:21.26#ibcon#read 5, iclass 12, count 0 2006.238.07:49:21.26#ibcon#about to read 6, iclass 12, count 0 2006.238.07:49:21.26#ibcon#read 6, iclass 12, count 0 2006.238.07:49:21.26#ibcon#end of sib2, iclass 12, count 0 2006.238.07:49:21.26#ibcon#*mode == 0, iclass 12, count 0 2006.238.07:49:21.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.07:49:21.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:49:21.26#ibcon#*before write, iclass 12, count 0 2006.238.07:49:21.26#ibcon#enter sib2, iclass 12, count 0 2006.238.07:49:21.26#ibcon#flushed, iclass 12, count 0 2006.238.07:49:21.26#ibcon#about to write, iclass 12, count 0 2006.238.07:49:21.26#ibcon#wrote, iclass 12, count 0 2006.238.07:49:21.26#ibcon#about to read 3, iclass 12, count 0 2006.238.07:49:21.30#ibcon#read 3, iclass 12, count 0 2006.238.07:49:21.30#ibcon#about to read 4, iclass 12, count 0 2006.238.07:49:21.30#ibcon#read 4, iclass 12, count 0 2006.238.07:49:21.30#ibcon#about to read 5, iclass 12, count 0 2006.238.07:49:21.30#ibcon#read 5, iclass 12, count 0 2006.238.07:49:21.30#ibcon#about to read 6, iclass 12, count 0 2006.238.07:49:21.30#ibcon#read 6, iclass 12, count 0 2006.238.07:49:21.30#ibcon#end of sib2, iclass 12, count 0 2006.238.07:49:21.30#ibcon#*after write, iclass 12, count 0 2006.238.07:49:21.30#ibcon#*before return 0, iclass 12, count 0 2006.238.07:49:21.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:49:21.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.238.07:49:21.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.07:49:21.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.07:49:21.30$vc4f8/vb=3,4 2006.238.07:49:21.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.238.07:49:21.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.238.07:49:21.30#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:21.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:49:21.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:49:21.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:49:21.36#ibcon#enter wrdev, iclass 14, count 2 2006.238.07:49:21.36#ibcon#first serial, iclass 14, count 2 2006.238.07:49:21.36#ibcon#enter sib2, iclass 14, count 2 2006.238.07:49:21.36#ibcon#flushed, iclass 14, count 2 2006.238.07:49:21.36#ibcon#about to write, iclass 14, count 2 2006.238.07:49:21.36#ibcon#wrote, iclass 14, count 2 2006.238.07:49:21.36#ibcon#about to read 3, iclass 14, count 2 2006.238.07:49:21.38#ibcon#read 3, iclass 14, count 2 2006.238.07:49:21.38#ibcon#about to read 4, iclass 14, count 2 2006.238.07:49:21.38#ibcon#read 4, iclass 14, count 2 2006.238.07:49:21.38#ibcon#about to read 5, iclass 14, count 2 2006.238.07:49:21.38#ibcon#read 5, iclass 14, count 2 2006.238.07:49:21.38#ibcon#about to read 6, iclass 14, count 2 2006.238.07:49:21.38#ibcon#read 6, iclass 14, count 2 2006.238.07:49:21.38#ibcon#end of sib2, iclass 14, count 2 2006.238.07:49:21.38#ibcon#*mode == 0, iclass 14, count 2 2006.238.07:49:21.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.238.07:49:21.38#ibcon#[27=AT03-04\r\n] 2006.238.07:49:21.38#ibcon#*before write, iclass 14, count 2 2006.238.07:49:21.38#ibcon#enter sib2, iclass 14, count 2 2006.238.07:49:21.38#ibcon#flushed, iclass 14, count 2 2006.238.07:49:21.38#ibcon#about to write, iclass 14, count 2 2006.238.07:49:21.38#ibcon#wrote, iclass 14, count 2 2006.238.07:49:21.38#ibcon#about to read 3, iclass 14, count 2 2006.238.07:49:21.41#ibcon#read 3, iclass 14, count 2 2006.238.07:49:21.41#ibcon#about to read 4, iclass 14, count 2 2006.238.07:49:21.41#ibcon#read 4, iclass 14, count 2 2006.238.07:49:21.41#ibcon#about to read 5, iclass 14, count 2 2006.238.07:49:21.41#ibcon#read 5, iclass 14, count 2 2006.238.07:49:21.41#ibcon#about to read 6, iclass 14, count 2 2006.238.07:49:21.41#ibcon#read 6, iclass 14, count 2 2006.238.07:49:21.41#ibcon#end of sib2, iclass 14, count 2 2006.238.07:49:21.41#ibcon#*after write, iclass 14, count 2 2006.238.07:49:21.41#ibcon#*before return 0, iclass 14, count 2 2006.238.07:49:21.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:49:21.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.238.07:49:21.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.238.07:49:21.41#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:21.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:49:21.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:49:21.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:49:21.53#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:49:21.53#ibcon#first serial, iclass 14, count 0 2006.238.07:49:21.53#ibcon#enter sib2, iclass 14, count 0 2006.238.07:49:21.53#ibcon#flushed, iclass 14, count 0 2006.238.07:49:21.53#ibcon#about to write, iclass 14, count 0 2006.238.07:49:21.53#ibcon#wrote, iclass 14, count 0 2006.238.07:49:21.53#ibcon#about to read 3, iclass 14, count 0 2006.238.07:49:21.55#ibcon#read 3, iclass 14, count 0 2006.238.07:49:21.55#ibcon#about to read 4, iclass 14, count 0 2006.238.07:49:21.55#ibcon#read 4, iclass 14, count 0 2006.238.07:49:21.55#ibcon#about to read 5, iclass 14, count 0 2006.238.07:49:21.55#ibcon#read 5, iclass 14, count 0 2006.238.07:49:21.55#ibcon#about to read 6, iclass 14, count 0 2006.238.07:49:21.55#ibcon#read 6, iclass 14, count 0 2006.238.07:49:21.55#ibcon#end of sib2, iclass 14, count 0 2006.238.07:49:21.55#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:49:21.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:49:21.55#ibcon#[27=USB\r\n] 2006.238.07:49:21.55#ibcon#*before write, iclass 14, count 0 2006.238.07:49:21.55#ibcon#enter sib2, iclass 14, count 0 2006.238.07:49:21.55#ibcon#flushed, iclass 14, count 0 2006.238.07:49:21.55#ibcon#about to write, iclass 14, count 0 2006.238.07:49:21.55#ibcon#wrote, iclass 14, count 0 2006.238.07:49:21.55#ibcon#about to read 3, iclass 14, count 0 2006.238.07:49:21.58#ibcon#read 3, iclass 14, count 0 2006.238.07:49:21.58#ibcon#about to read 4, iclass 14, count 0 2006.238.07:49:21.58#ibcon#read 4, iclass 14, count 0 2006.238.07:49:21.58#ibcon#about to read 5, iclass 14, count 0 2006.238.07:49:21.58#ibcon#read 5, iclass 14, count 0 2006.238.07:49:21.58#ibcon#about to read 6, iclass 14, count 0 2006.238.07:49:21.58#ibcon#read 6, iclass 14, count 0 2006.238.07:49:21.58#ibcon#end of sib2, iclass 14, count 0 2006.238.07:49:21.58#ibcon#*after write, iclass 14, count 0 2006.238.07:49:21.58#ibcon#*before return 0, iclass 14, count 0 2006.238.07:49:21.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:49:21.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.238.07:49:21.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:49:21.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:49:21.58$vc4f8/vblo=4,712.99 2006.238.07:49:21.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.07:49:21.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.07:49:21.58#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:21.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:49:21.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:49:21.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:49:21.58#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:49:21.58#ibcon#first serial, iclass 16, count 0 2006.238.07:49:21.58#ibcon#enter sib2, iclass 16, count 0 2006.238.07:49:21.58#ibcon#flushed, iclass 16, count 0 2006.238.07:49:21.58#ibcon#about to write, iclass 16, count 0 2006.238.07:49:21.58#ibcon#wrote, iclass 16, count 0 2006.238.07:49:21.58#ibcon#about to read 3, iclass 16, count 0 2006.238.07:49:21.60#ibcon#read 3, iclass 16, count 0 2006.238.07:49:21.60#ibcon#about to read 4, iclass 16, count 0 2006.238.07:49:21.60#ibcon#read 4, iclass 16, count 0 2006.238.07:49:21.60#ibcon#about to read 5, iclass 16, count 0 2006.238.07:49:21.60#ibcon#read 5, iclass 16, count 0 2006.238.07:49:21.60#ibcon#about to read 6, iclass 16, count 0 2006.238.07:49:21.60#ibcon#read 6, iclass 16, count 0 2006.238.07:49:21.60#ibcon#end of sib2, iclass 16, count 0 2006.238.07:49:21.60#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:49:21.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:49:21.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:49:21.60#ibcon#*before write, iclass 16, count 0 2006.238.07:49:21.60#ibcon#enter sib2, iclass 16, count 0 2006.238.07:49:21.60#ibcon#flushed, iclass 16, count 0 2006.238.07:49:21.60#ibcon#about to write, iclass 16, count 0 2006.238.07:49:21.60#ibcon#wrote, iclass 16, count 0 2006.238.07:49:21.60#ibcon#about to read 3, iclass 16, count 0 2006.238.07:49:21.64#ibcon#read 3, iclass 16, count 0 2006.238.07:49:21.64#ibcon#about to read 4, iclass 16, count 0 2006.238.07:49:21.64#ibcon#read 4, iclass 16, count 0 2006.238.07:49:21.64#ibcon#about to read 5, iclass 16, count 0 2006.238.07:49:21.64#ibcon#read 5, iclass 16, count 0 2006.238.07:49:21.64#ibcon#about to read 6, iclass 16, count 0 2006.238.07:49:21.64#ibcon#read 6, iclass 16, count 0 2006.238.07:49:21.64#ibcon#end of sib2, iclass 16, count 0 2006.238.07:49:21.64#ibcon#*after write, iclass 16, count 0 2006.238.07:49:21.64#ibcon#*before return 0, iclass 16, count 0 2006.238.07:49:21.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:49:21.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.07:49:21.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:49:21.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:49:21.64$vc4f8/vb=4,4 2006.238.07:49:21.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.238.07:49:21.64#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.238.07:49:21.64#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:21.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:49:21.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:49:21.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:49:21.70#ibcon#enter wrdev, iclass 18, count 2 2006.238.07:49:21.70#ibcon#first serial, iclass 18, count 2 2006.238.07:49:21.70#ibcon#enter sib2, iclass 18, count 2 2006.238.07:49:21.70#ibcon#flushed, iclass 18, count 2 2006.238.07:49:21.70#ibcon#about to write, iclass 18, count 2 2006.238.07:49:21.70#ibcon#wrote, iclass 18, count 2 2006.238.07:49:21.70#ibcon#about to read 3, iclass 18, count 2 2006.238.07:49:21.72#ibcon#read 3, iclass 18, count 2 2006.238.07:49:21.72#ibcon#about to read 4, iclass 18, count 2 2006.238.07:49:21.72#ibcon#read 4, iclass 18, count 2 2006.238.07:49:21.72#ibcon#about to read 5, iclass 18, count 2 2006.238.07:49:21.72#ibcon#read 5, iclass 18, count 2 2006.238.07:49:21.72#ibcon#about to read 6, iclass 18, count 2 2006.238.07:49:21.72#ibcon#read 6, iclass 18, count 2 2006.238.07:49:21.72#ibcon#end of sib2, iclass 18, count 2 2006.238.07:49:21.72#ibcon#*mode == 0, iclass 18, count 2 2006.238.07:49:21.72#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.238.07:49:21.72#ibcon#[27=AT04-04\r\n] 2006.238.07:49:21.72#ibcon#*before write, iclass 18, count 2 2006.238.07:49:21.72#ibcon#enter sib2, iclass 18, count 2 2006.238.07:49:21.72#ibcon#flushed, iclass 18, count 2 2006.238.07:49:21.72#ibcon#about to write, iclass 18, count 2 2006.238.07:49:21.72#ibcon#wrote, iclass 18, count 2 2006.238.07:49:21.72#ibcon#about to read 3, iclass 18, count 2 2006.238.07:49:21.75#ibcon#read 3, iclass 18, count 2 2006.238.07:49:21.75#ibcon#about to read 4, iclass 18, count 2 2006.238.07:49:21.75#ibcon#read 4, iclass 18, count 2 2006.238.07:49:21.75#ibcon#about to read 5, iclass 18, count 2 2006.238.07:49:21.75#ibcon#read 5, iclass 18, count 2 2006.238.07:49:21.75#ibcon#about to read 6, iclass 18, count 2 2006.238.07:49:21.75#ibcon#read 6, iclass 18, count 2 2006.238.07:49:21.75#ibcon#end of sib2, iclass 18, count 2 2006.238.07:49:21.75#ibcon#*after write, iclass 18, count 2 2006.238.07:49:21.75#ibcon#*before return 0, iclass 18, count 2 2006.238.07:49:21.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:49:21.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.238.07:49:21.75#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.238.07:49:21.75#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:21.75#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:49:21.87#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:49:21.87#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:49:21.87#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:49:21.87#ibcon#first serial, iclass 18, count 0 2006.238.07:49:21.87#ibcon#enter sib2, iclass 18, count 0 2006.238.07:49:21.87#ibcon#flushed, iclass 18, count 0 2006.238.07:49:21.87#ibcon#about to write, iclass 18, count 0 2006.238.07:49:21.87#ibcon#wrote, iclass 18, count 0 2006.238.07:49:21.87#ibcon#about to read 3, iclass 18, count 0 2006.238.07:49:21.89#ibcon#read 3, iclass 18, count 0 2006.238.07:49:21.89#ibcon#about to read 4, iclass 18, count 0 2006.238.07:49:21.89#ibcon#read 4, iclass 18, count 0 2006.238.07:49:21.89#ibcon#about to read 5, iclass 18, count 0 2006.238.07:49:21.89#ibcon#read 5, iclass 18, count 0 2006.238.07:49:21.89#ibcon#about to read 6, iclass 18, count 0 2006.238.07:49:21.89#ibcon#read 6, iclass 18, count 0 2006.238.07:49:21.89#ibcon#end of sib2, iclass 18, count 0 2006.238.07:49:21.89#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:49:21.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:49:21.89#ibcon#[27=USB\r\n] 2006.238.07:49:21.89#ibcon#*before write, iclass 18, count 0 2006.238.07:49:21.89#ibcon#enter sib2, iclass 18, count 0 2006.238.07:49:21.89#ibcon#flushed, iclass 18, count 0 2006.238.07:49:21.89#ibcon#about to write, iclass 18, count 0 2006.238.07:49:21.89#ibcon#wrote, iclass 18, count 0 2006.238.07:49:21.89#ibcon#about to read 3, iclass 18, count 0 2006.238.07:49:21.92#ibcon#read 3, iclass 18, count 0 2006.238.07:49:21.92#ibcon#about to read 4, iclass 18, count 0 2006.238.07:49:21.92#ibcon#read 4, iclass 18, count 0 2006.238.07:49:21.92#ibcon#about to read 5, iclass 18, count 0 2006.238.07:49:21.92#ibcon#read 5, iclass 18, count 0 2006.238.07:49:21.92#ibcon#about to read 6, iclass 18, count 0 2006.238.07:49:21.92#ibcon#read 6, iclass 18, count 0 2006.238.07:49:21.92#ibcon#end of sib2, iclass 18, count 0 2006.238.07:49:21.92#ibcon#*after write, iclass 18, count 0 2006.238.07:49:21.92#ibcon#*before return 0, iclass 18, count 0 2006.238.07:49:21.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:49:21.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.238.07:49:21.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:49:21.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:49:21.92$vc4f8/vblo=5,744.99 2006.238.07:49:21.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.07:49:21.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.07:49:21.92#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:21.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:49:21.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:49:21.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:49:21.92#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:49:21.92#ibcon#first serial, iclass 20, count 0 2006.238.07:49:21.92#ibcon#enter sib2, iclass 20, count 0 2006.238.07:49:21.92#ibcon#flushed, iclass 20, count 0 2006.238.07:49:21.92#ibcon#about to write, iclass 20, count 0 2006.238.07:49:21.92#ibcon#wrote, iclass 20, count 0 2006.238.07:49:21.92#ibcon#about to read 3, iclass 20, count 0 2006.238.07:49:21.94#ibcon#read 3, iclass 20, count 0 2006.238.07:49:21.94#ibcon#about to read 4, iclass 20, count 0 2006.238.07:49:21.94#ibcon#read 4, iclass 20, count 0 2006.238.07:49:21.94#ibcon#about to read 5, iclass 20, count 0 2006.238.07:49:21.94#ibcon#read 5, iclass 20, count 0 2006.238.07:49:21.94#ibcon#about to read 6, iclass 20, count 0 2006.238.07:49:21.94#ibcon#read 6, iclass 20, count 0 2006.238.07:49:21.94#ibcon#end of sib2, iclass 20, count 0 2006.238.07:49:21.94#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:49:21.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:49:21.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:49:21.94#ibcon#*before write, iclass 20, count 0 2006.238.07:49:21.94#ibcon#enter sib2, iclass 20, count 0 2006.238.07:49:21.94#ibcon#flushed, iclass 20, count 0 2006.238.07:49:21.94#ibcon#about to write, iclass 20, count 0 2006.238.07:49:21.94#ibcon#wrote, iclass 20, count 0 2006.238.07:49:21.94#ibcon#about to read 3, iclass 20, count 0 2006.238.07:49:21.98#ibcon#read 3, iclass 20, count 0 2006.238.07:49:21.98#ibcon#about to read 4, iclass 20, count 0 2006.238.07:49:21.98#ibcon#read 4, iclass 20, count 0 2006.238.07:49:21.98#ibcon#about to read 5, iclass 20, count 0 2006.238.07:49:21.98#ibcon#read 5, iclass 20, count 0 2006.238.07:49:21.98#ibcon#about to read 6, iclass 20, count 0 2006.238.07:49:21.98#ibcon#read 6, iclass 20, count 0 2006.238.07:49:21.98#ibcon#end of sib2, iclass 20, count 0 2006.238.07:49:21.98#ibcon#*after write, iclass 20, count 0 2006.238.07:49:21.98#ibcon#*before return 0, iclass 20, count 0 2006.238.07:49:21.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:49:21.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.07:49:21.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:49:21.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:49:21.98$vc4f8/vb=5,4 2006.238.07:49:21.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.238.07:49:21.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.238.07:49:21.98#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:21.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:49:22.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:49:22.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:49:22.04#ibcon#enter wrdev, iclass 22, count 2 2006.238.07:49:22.04#ibcon#first serial, iclass 22, count 2 2006.238.07:49:22.04#ibcon#enter sib2, iclass 22, count 2 2006.238.07:49:22.04#ibcon#flushed, iclass 22, count 2 2006.238.07:49:22.04#ibcon#about to write, iclass 22, count 2 2006.238.07:49:22.04#ibcon#wrote, iclass 22, count 2 2006.238.07:49:22.04#ibcon#about to read 3, iclass 22, count 2 2006.238.07:49:22.06#ibcon#read 3, iclass 22, count 2 2006.238.07:49:22.06#ibcon#about to read 4, iclass 22, count 2 2006.238.07:49:22.06#ibcon#read 4, iclass 22, count 2 2006.238.07:49:22.06#ibcon#about to read 5, iclass 22, count 2 2006.238.07:49:22.06#ibcon#read 5, iclass 22, count 2 2006.238.07:49:22.06#ibcon#about to read 6, iclass 22, count 2 2006.238.07:49:22.06#ibcon#read 6, iclass 22, count 2 2006.238.07:49:22.06#ibcon#end of sib2, iclass 22, count 2 2006.238.07:49:22.06#ibcon#*mode == 0, iclass 22, count 2 2006.238.07:49:22.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.238.07:49:22.06#ibcon#[27=AT05-04\r\n] 2006.238.07:49:22.06#ibcon#*before write, iclass 22, count 2 2006.238.07:49:22.06#ibcon#enter sib2, iclass 22, count 2 2006.238.07:49:22.06#ibcon#flushed, iclass 22, count 2 2006.238.07:49:22.06#ibcon#about to write, iclass 22, count 2 2006.238.07:49:22.06#ibcon#wrote, iclass 22, count 2 2006.238.07:49:22.06#ibcon#about to read 3, iclass 22, count 2 2006.238.07:49:22.09#ibcon#read 3, iclass 22, count 2 2006.238.07:49:22.09#ibcon#about to read 4, iclass 22, count 2 2006.238.07:49:22.09#ibcon#read 4, iclass 22, count 2 2006.238.07:49:22.09#ibcon#about to read 5, iclass 22, count 2 2006.238.07:49:22.09#ibcon#read 5, iclass 22, count 2 2006.238.07:49:22.09#ibcon#about to read 6, iclass 22, count 2 2006.238.07:49:22.09#ibcon#read 6, iclass 22, count 2 2006.238.07:49:22.09#ibcon#end of sib2, iclass 22, count 2 2006.238.07:49:22.09#ibcon#*after write, iclass 22, count 2 2006.238.07:49:22.09#ibcon#*before return 0, iclass 22, count 2 2006.238.07:49:22.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:49:22.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.238.07:49:22.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.238.07:49:22.09#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:22.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:49:22.21#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:49:22.21#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:49:22.21#ibcon#enter wrdev, iclass 22, count 0 2006.238.07:49:22.21#ibcon#first serial, iclass 22, count 0 2006.238.07:49:22.21#ibcon#enter sib2, iclass 22, count 0 2006.238.07:49:22.21#ibcon#flushed, iclass 22, count 0 2006.238.07:49:22.21#ibcon#about to write, iclass 22, count 0 2006.238.07:49:22.21#ibcon#wrote, iclass 22, count 0 2006.238.07:49:22.21#ibcon#about to read 3, iclass 22, count 0 2006.238.07:49:22.23#ibcon#read 3, iclass 22, count 0 2006.238.07:49:22.23#ibcon#about to read 4, iclass 22, count 0 2006.238.07:49:22.23#ibcon#read 4, iclass 22, count 0 2006.238.07:49:22.23#ibcon#about to read 5, iclass 22, count 0 2006.238.07:49:22.23#ibcon#read 5, iclass 22, count 0 2006.238.07:49:22.23#ibcon#about to read 6, iclass 22, count 0 2006.238.07:49:22.23#ibcon#read 6, iclass 22, count 0 2006.238.07:49:22.23#ibcon#end of sib2, iclass 22, count 0 2006.238.07:49:22.23#ibcon#*mode == 0, iclass 22, count 0 2006.238.07:49:22.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.07:49:22.23#ibcon#[27=USB\r\n] 2006.238.07:49:22.23#ibcon#*before write, iclass 22, count 0 2006.238.07:49:22.23#ibcon#enter sib2, iclass 22, count 0 2006.238.07:49:22.23#ibcon#flushed, iclass 22, count 0 2006.238.07:49:22.23#ibcon#about to write, iclass 22, count 0 2006.238.07:49:22.23#ibcon#wrote, iclass 22, count 0 2006.238.07:49:22.23#ibcon#about to read 3, iclass 22, count 0 2006.238.07:49:22.26#ibcon#read 3, iclass 22, count 0 2006.238.07:49:22.26#ibcon#about to read 4, iclass 22, count 0 2006.238.07:49:22.26#ibcon#read 4, iclass 22, count 0 2006.238.07:49:22.26#ibcon#about to read 5, iclass 22, count 0 2006.238.07:49:22.26#ibcon#read 5, iclass 22, count 0 2006.238.07:49:22.26#ibcon#about to read 6, iclass 22, count 0 2006.238.07:49:22.26#ibcon#read 6, iclass 22, count 0 2006.238.07:49:22.26#ibcon#end of sib2, iclass 22, count 0 2006.238.07:49:22.26#ibcon#*after write, iclass 22, count 0 2006.238.07:49:22.26#ibcon#*before return 0, iclass 22, count 0 2006.238.07:49:22.26#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:49:22.26#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.238.07:49:22.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.07:49:22.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.07:49:22.26$vc4f8/vblo=6,752.99 2006.238.07:49:22.26#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.07:49:22.26#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.07:49:22.26#ibcon#ireg 17 cls_cnt 0 2006.238.07:49:22.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:49:22.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:49:22.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:49:22.26#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:49:22.26#ibcon#first serial, iclass 24, count 0 2006.238.07:49:22.26#ibcon#enter sib2, iclass 24, count 0 2006.238.07:49:22.26#ibcon#flushed, iclass 24, count 0 2006.238.07:49:22.26#ibcon#about to write, iclass 24, count 0 2006.238.07:49:22.26#ibcon#wrote, iclass 24, count 0 2006.238.07:49:22.26#ibcon#about to read 3, iclass 24, count 0 2006.238.07:49:22.28#ibcon#read 3, iclass 24, count 0 2006.238.07:49:22.28#ibcon#about to read 4, iclass 24, count 0 2006.238.07:49:22.28#ibcon#read 4, iclass 24, count 0 2006.238.07:49:22.28#ibcon#about to read 5, iclass 24, count 0 2006.238.07:49:22.28#ibcon#read 5, iclass 24, count 0 2006.238.07:49:22.28#ibcon#about to read 6, iclass 24, count 0 2006.238.07:49:22.28#ibcon#read 6, iclass 24, count 0 2006.238.07:49:22.28#ibcon#end of sib2, iclass 24, count 0 2006.238.07:49:22.28#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:49:22.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:49:22.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:49:22.28#ibcon#*before write, iclass 24, count 0 2006.238.07:49:22.28#ibcon#enter sib2, iclass 24, count 0 2006.238.07:49:22.28#ibcon#flushed, iclass 24, count 0 2006.238.07:49:22.28#ibcon#about to write, iclass 24, count 0 2006.238.07:49:22.28#ibcon#wrote, iclass 24, count 0 2006.238.07:49:22.28#ibcon#about to read 3, iclass 24, count 0 2006.238.07:49:22.32#ibcon#read 3, iclass 24, count 0 2006.238.07:49:22.32#ibcon#about to read 4, iclass 24, count 0 2006.238.07:49:22.32#ibcon#read 4, iclass 24, count 0 2006.238.07:49:22.32#ibcon#about to read 5, iclass 24, count 0 2006.238.07:49:22.32#ibcon#read 5, iclass 24, count 0 2006.238.07:49:22.32#ibcon#about to read 6, iclass 24, count 0 2006.238.07:49:22.32#ibcon#read 6, iclass 24, count 0 2006.238.07:49:22.32#ibcon#end of sib2, iclass 24, count 0 2006.238.07:49:22.32#ibcon#*after write, iclass 24, count 0 2006.238.07:49:22.32#ibcon#*before return 0, iclass 24, count 0 2006.238.07:49:22.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:49:22.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:49:22.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:49:22.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:49:22.32$vc4f8/vb=6,4 2006.238.07:49:22.32#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.238.07:49:22.32#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.238.07:49:22.32#ibcon#ireg 11 cls_cnt 2 2006.238.07:49:22.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:49:22.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:49:22.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:49:22.38#ibcon#enter wrdev, iclass 26, count 2 2006.238.07:49:22.38#ibcon#first serial, iclass 26, count 2 2006.238.07:49:22.38#ibcon#enter sib2, iclass 26, count 2 2006.238.07:49:22.38#ibcon#flushed, iclass 26, count 2 2006.238.07:49:22.38#ibcon#about to write, iclass 26, count 2 2006.238.07:49:22.38#ibcon#wrote, iclass 26, count 2 2006.238.07:49:22.38#ibcon#about to read 3, iclass 26, count 2 2006.238.07:49:22.40#ibcon#read 3, iclass 26, count 2 2006.238.07:49:22.40#ibcon#about to read 4, iclass 26, count 2 2006.238.07:49:22.40#ibcon#read 4, iclass 26, count 2 2006.238.07:49:22.40#ibcon#about to read 5, iclass 26, count 2 2006.238.07:49:22.40#ibcon#read 5, iclass 26, count 2 2006.238.07:49:22.40#ibcon#about to read 6, iclass 26, count 2 2006.238.07:49:22.40#ibcon#read 6, iclass 26, count 2 2006.238.07:49:22.40#ibcon#end of sib2, iclass 26, count 2 2006.238.07:49:22.40#ibcon#*mode == 0, iclass 26, count 2 2006.238.07:49:22.40#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.238.07:49:22.40#ibcon#[27=AT06-04\r\n] 2006.238.07:49:22.40#ibcon#*before write, iclass 26, count 2 2006.238.07:49:22.40#ibcon#enter sib2, iclass 26, count 2 2006.238.07:49:22.40#ibcon#flushed, iclass 26, count 2 2006.238.07:49:22.40#ibcon#about to write, iclass 26, count 2 2006.238.07:49:22.40#ibcon#wrote, iclass 26, count 2 2006.238.07:49:22.40#ibcon#about to read 3, iclass 26, count 2 2006.238.07:49:22.43#ibcon#read 3, iclass 26, count 2 2006.238.07:49:22.43#ibcon#about to read 4, iclass 26, count 2 2006.238.07:49:22.43#ibcon#read 4, iclass 26, count 2 2006.238.07:49:22.43#ibcon#about to read 5, iclass 26, count 2 2006.238.07:49:22.43#ibcon#read 5, iclass 26, count 2 2006.238.07:49:22.43#ibcon#about to read 6, iclass 26, count 2 2006.238.07:49:22.43#ibcon#read 6, iclass 26, count 2 2006.238.07:49:22.43#ibcon#end of sib2, iclass 26, count 2 2006.238.07:49:22.43#ibcon#*after write, iclass 26, count 2 2006.238.07:49:22.43#ibcon#*before return 0, iclass 26, count 2 2006.238.07:49:22.43#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:49:22.43#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.238.07:49:22.43#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.238.07:49:22.43#ibcon#ireg 7 cls_cnt 0 2006.238.07:49:22.43#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:49:22.55#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:49:22.55#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:49:22.55#ibcon#enter wrdev, iclass 26, count 0 2006.238.07:49:22.55#ibcon#first serial, iclass 26, count 0 2006.238.07:49:22.55#ibcon#enter sib2, iclass 26, count 0 2006.238.07:49:22.55#ibcon#flushed, iclass 26, count 0 2006.238.07:49:22.55#ibcon#about to write, iclass 26, count 0 2006.238.07:49:22.55#ibcon#wrote, iclass 26, count 0 2006.238.07:49:22.55#ibcon#about to read 3, iclass 26, count 0 2006.238.07:49:22.57#ibcon#read 3, iclass 26, count 0 2006.238.07:49:22.57#ibcon#about to read 4, iclass 26, count 0 2006.238.07:49:22.57#ibcon#read 4, iclass 26, count 0 2006.238.07:49:22.57#ibcon#about to read 5, iclass 26, count 0 2006.238.07:49:22.57#ibcon#read 5, iclass 26, count 0 2006.238.07:49:22.57#ibcon#about to read 6, iclass 26, count 0 2006.238.07:49:22.57#ibcon#read 6, iclass 26, count 0 2006.238.07:49:22.57#ibcon#end of sib2, iclass 26, count 0 2006.238.07:49:22.57#ibcon#*mode == 0, iclass 26, count 0 2006.238.07:49:22.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.07:49:22.57#ibcon#[27=USB\r\n] 2006.238.07:49:22.57#ibcon#*before write, iclass 26, count 0 2006.238.07:49:22.57#ibcon#enter sib2, iclass 26, count 0 2006.238.07:49:22.57#ibcon#flushed, iclass 26, count 0 2006.238.07:49:22.57#ibcon#about to write, iclass 26, count 0 2006.238.07:49:22.57#ibcon#wrote, iclass 26, count 0 2006.238.07:49:22.57#ibcon#about to read 3, iclass 26, count 0 2006.238.07:49:22.60#ibcon#read 3, iclass 26, count 0 2006.238.07:49:22.60#ibcon#about to read 4, iclass 26, count 0 2006.238.07:49:22.60#ibcon#read 4, iclass 26, count 0 2006.238.07:49:22.60#ibcon#about to read 5, iclass 26, count 0 2006.238.07:49:22.60#ibcon#read 5, iclass 26, count 0 2006.238.07:49:22.60#ibcon#about to read 6, iclass 26, count 0 2006.238.07:49:22.60#ibcon#read 6, iclass 26, count 0 2006.238.07:49:22.60#ibcon#end of sib2, iclass 26, count 0 2006.238.07:49:22.60#ibcon#*after write, iclass 26, count 0 2006.238.07:49:22.60#ibcon#*before return 0, iclass 26, count 0 2006.238.07:49:22.60#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:49:22.60#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.238.07:49:22.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.07:49:22.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.07:49:22.60$vc4f8/vabw=wide 2006.238.07:49:22.60#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.238.07:49:22.60#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.238.07:49:22.60#ibcon#ireg 8 cls_cnt 0 2006.238.07:49:22.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:49:22.60#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:49:22.60#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:49:22.60#ibcon#enter wrdev, iclass 28, count 0 2006.238.07:49:22.60#ibcon#first serial, iclass 28, count 0 2006.238.07:49:22.60#ibcon#enter sib2, iclass 28, count 0 2006.238.07:49:22.60#ibcon#flushed, iclass 28, count 0 2006.238.07:49:22.60#ibcon#about to write, iclass 28, count 0 2006.238.07:49:22.60#ibcon#wrote, iclass 28, count 0 2006.238.07:49:22.60#ibcon#about to read 3, iclass 28, count 0 2006.238.07:49:22.62#ibcon#read 3, iclass 28, count 0 2006.238.07:49:22.62#ibcon#about to read 4, iclass 28, count 0 2006.238.07:49:22.62#ibcon#read 4, iclass 28, count 0 2006.238.07:49:22.62#ibcon#about to read 5, iclass 28, count 0 2006.238.07:49:22.62#ibcon#read 5, iclass 28, count 0 2006.238.07:49:22.62#ibcon#about to read 6, iclass 28, count 0 2006.238.07:49:22.62#ibcon#read 6, iclass 28, count 0 2006.238.07:49:22.62#ibcon#end of sib2, iclass 28, count 0 2006.238.07:49:22.62#ibcon#*mode == 0, iclass 28, count 0 2006.238.07:49:22.62#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.07:49:22.62#ibcon#[25=BW32\r\n] 2006.238.07:49:22.62#ibcon#*before write, iclass 28, count 0 2006.238.07:49:22.62#ibcon#enter sib2, iclass 28, count 0 2006.238.07:49:22.62#ibcon#flushed, iclass 28, count 0 2006.238.07:49:22.62#ibcon#about to write, iclass 28, count 0 2006.238.07:49:22.62#ibcon#wrote, iclass 28, count 0 2006.238.07:49:22.62#ibcon#about to read 3, iclass 28, count 0 2006.238.07:49:22.65#ibcon#read 3, iclass 28, count 0 2006.238.07:49:22.65#ibcon#about to read 4, iclass 28, count 0 2006.238.07:49:22.65#ibcon#read 4, iclass 28, count 0 2006.238.07:49:22.65#ibcon#about to read 5, iclass 28, count 0 2006.238.07:49:22.65#ibcon#read 5, iclass 28, count 0 2006.238.07:49:22.65#ibcon#about to read 6, iclass 28, count 0 2006.238.07:49:22.65#ibcon#read 6, iclass 28, count 0 2006.238.07:49:22.65#ibcon#end of sib2, iclass 28, count 0 2006.238.07:49:22.65#ibcon#*after write, iclass 28, count 0 2006.238.07:49:22.65#ibcon#*before return 0, iclass 28, count 0 2006.238.07:49:22.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:49:22.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.238.07:49:22.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.07:49:22.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.07:49:22.65$vc4f8/vbbw=wide 2006.238.07:49:22.65#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.07:49:22.65#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.07:49:22.65#ibcon#ireg 8 cls_cnt 0 2006.238.07:49:22.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:49:22.72#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:49:22.72#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:49:22.72#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:49:22.72#ibcon#first serial, iclass 30, count 0 2006.238.07:49:22.72#ibcon#enter sib2, iclass 30, count 0 2006.238.07:49:22.72#ibcon#flushed, iclass 30, count 0 2006.238.07:49:22.72#ibcon#about to write, iclass 30, count 0 2006.238.07:49:22.72#ibcon#wrote, iclass 30, count 0 2006.238.07:49:22.72#ibcon#about to read 3, iclass 30, count 0 2006.238.07:49:22.74#ibcon#read 3, iclass 30, count 0 2006.238.07:49:22.74#ibcon#about to read 4, iclass 30, count 0 2006.238.07:49:22.74#ibcon#read 4, iclass 30, count 0 2006.238.07:49:22.74#ibcon#about to read 5, iclass 30, count 0 2006.238.07:49:22.74#ibcon#read 5, iclass 30, count 0 2006.238.07:49:22.74#ibcon#about to read 6, iclass 30, count 0 2006.238.07:49:22.74#ibcon#read 6, iclass 30, count 0 2006.238.07:49:22.74#ibcon#end of sib2, iclass 30, count 0 2006.238.07:49:22.74#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:49:22.74#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:49:22.74#ibcon#[27=BW32\r\n] 2006.238.07:49:22.74#ibcon#*before write, iclass 30, count 0 2006.238.07:49:22.74#ibcon#enter sib2, iclass 30, count 0 2006.238.07:49:22.74#ibcon#flushed, iclass 30, count 0 2006.238.07:49:22.74#ibcon#about to write, iclass 30, count 0 2006.238.07:49:22.74#ibcon#wrote, iclass 30, count 0 2006.238.07:49:22.74#ibcon#about to read 3, iclass 30, count 0 2006.238.07:49:22.77#ibcon#read 3, iclass 30, count 0 2006.238.07:49:22.77#ibcon#about to read 4, iclass 30, count 0 2006.238.07:49:22.77#ibcon#read 4, iclass 30, count 0 2006.238.07:49:22.77#ibcon#about to read 5, iclass 30, count 0 2006.238.07:49:22.77#ibcon#read 5, iclass 30, count 0 2006.238.07:49:22.77#ibcon#about to read 6, iclass 30, count 0 2006.238.07:49:22.77#ibcon#read 6, iclass 30, count 0 2006.238.07:49:22.77#ibcon#end of sib2, iclass 30, count 0 2006.238.07:49:22.77#ibcon#*after write, iclass 30, count 0 2006.238.07:49:22.77#ibcon#*before return 0, iclass 30, count 0 2006.238.07:49:22.77#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:49:22.77#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:49:22.77#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:49:22.77#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:49:22.77$4f8m12a/ifd4f 2006.238.07:49:22.77$ifd4f/lo= 2006.238.07:49:22.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:49:22.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:49:22.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:49:22.77$ifd4f/patch= 2006.238.07:49:22.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:49:22.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:49:22.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:49:22.77$4f8m12a/"form=m,16.000,1:2 2006.238.07:49:22.77$4f8m12a/"tpicd 2006.238.07:49:22.77$4f8m12a/echo=off 2006.238.07:49:22.77$4f8m12a/xlog=off 2006.238.07:49:22.77:!2006.238.07:49:50 2006.238.07:49:33.14#trakl#Source acquired 2006.238.07:49:35.14#flagr#flagr/antenna,acquired 2006.238.07:49:50.00:preob 2006.238.07:49:51.14/onsource/TRACKING 2006.238.07:49:51.14:!2006.238.07:50:00 2006.238.07:50:00.00:data_valid=on 2006.238.07:50:00.00:midob 2006.238.07:50:00.14/onsource/TRACKING 2006.238.07:50:00.14/wx/25.35,1012.1,87 2006.238.07:50:00.23/cable/+6.4184E-03 2006.238.07:50:01.32/va/01,08,usb,yes,32,33 2006.238.07:50:01.32/va/02,07,usb,yes,32,33 2006.238.07:50:01.32/va/03,07,usb,yes,30,30 2006.238.07:50:01.32/va/04,07,usb,yes,33,36 2006.238.07:50:01.32/va/05,08,usb,yes,30,32 2006.238.07:50:01.32/va/06,07,usb,yes,33,33 2006.238.07:50:01.32/va/07,07,usb,yes,33,33 2006.238.07:50:01.32/va/08,07,usb,yes,35,35 2006.238.07:50:01.55/valo/01,532.99,yes,locked 2006.238.07:50:01.55/valo/02,572.99,yes,locked 2006.238.07:50:01.55/valo/03,672.99,yes,locked 2006.238.07:50:01.55/valo/04,832.99,yes,locked 2006.238.07:50:01.55/valo/05,652.99,yes,locked 2006.238.07:50:01.55/valo/06,772.99,yes,locked 2006.238.07:50:01.55/valo/07,832.99,yes,locked 2006.238.07:50:01.55/valo/08,852.99,yes,locked 2006.238.07:50:02.64/vb/01,04,usb,yes,31,29 2006.238.07:50:02.64/vb/02,04,usb,yes,32,34 2006.238.07:50:02.64/vb/03,04,usb,yes,29,32 2006.238.07:50:02.64/vb/04,04,usb,yes,29,30 2006.238.07:50:02.64/vb/05,04,usb,yes,28,32 2006.238.07:50:02.64/vb/06,04,usb,yes,29,32 2006.238.07:50:02.64/vb/07,04,usb,yes,31,31 2006.238.07:50:02.64/vb/08,04,usb,yes,28,32 2006.238.07:50:02.87/vblo/01,632.99,yes,locked 2006.238.07:50:02.87/vblo/02,640.99,yes,locked 2006.238.07:50:02.87/vblo/03,656.99,yes,locked 2006.238.07:50:02.87/vblo/04,712.99,yes,locked 2006.238.07:50:02.87/vblo/05,744.99,yes,locked 2006.238.07:50:02.87/vblo/06,752.99,yes,locked 2006.238.07:50:02.87/vblo/07,734.99,yes,locked 2006.238.07:50:02.87/vblo/08,744.99,yes,locked 2006.238.07:50:03.02/vabw/8 2006.238.07:50:03.17/vbbw/8 2006.238.07:50:03.38/xfe/off,on,13.2 2006.238.07:50:03.75/ifatt/23,28,28,28 2006.238.07:50:04.08/fmout-gps/S +4.29E-07 2006.238.07:50:04.12:!2006.238.07:51:00 2006.238.07:51:00.00:data_valid=off 2006.238.07:51:00.00:postob 2006.238.07:51:00.10/cable/+6.4183E-03 2006.238.07:51:00.10/wx/25.36,1012.2,88 2006.238.07:51:01.08/fmout-gps/S +4.29E-07 2006.238.07:51:01.08:scan_name=238-0751,k06238,60 2006.238.07:51:01.08:source=1418+546,141946.60,542314.8,2000.0,cw 2006.238.07:51:01.13#flagr#flagr/antenna,new-source 2006.238.07:51:02.13:checkk5 2006.238.07:51:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:51:02.87/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:51:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:51:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:51:04.01/chk_obsdata//k5ts1/T2380750??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:51:04.38/chk_obsdata//k5ts2/T2380750??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:51:04.75/chk_obsdata//k5ts3/T2380750??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:51:05.12/chk_obsdata//k5ts4/T2380750??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:51:05.81/k5log//k5ts1_log_newline 2006.238.07:51:06.51/k5log//k5ts2_log_newline 2006.238.07:51:07.19/k5log//k5ts3_log_newline 2006.238.07:51:07.88/k5log//k5ts4_log_newline 2006.238.07:51:07.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:51:07.91:4f8m12a=1 2006.238.07:51:07.91$4f8m12a/echo=on 2006.238.07:51:07.91$4f8m12a/pcalon 2006.238.07:51:07.91$pcalon/"no phase cal control is implemented here 2006.238.07:51:07.91$4f8m12a/"tpicd=stop 2006.238.07:51:07.91$4f8m12a/vc4f8 2006.238.07:51:07.91$vc4f8/valo=1,532.99 2006.238.07:51:07.91#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.07:51:07.91#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.07:51:07.91#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:07.92#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:51:07.92#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:51:07.92#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:51:07.92#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:51:07.92#ibcon#first serial, iclass 3, count 0 2006.238.07:51:07.92#ibcon#enter sib2, iclass 3, count 0 2006.238.07:51:07.92#ibcon#flushed, iclass 3, count 0 2006.238.07:51:07.92#ibcon#about to write, iclass 3, count 0 2006.238.07:51:07.92#ibcon#wrote, iclass 3, count 0 2006.238.07:51:07.92#ibcon#about to read 3, iclass 3, count 0 2006.238.07:51:07.95#ibcon#read 3, iclass 3, count 0 2006.238.07:51:07.95#ibcon#about to read 4, iclass 3, count 0 2006.238.07:51:07.95#ibcon#read 4, iclass 3, count 0 2006.238.07:51:07.95#ibcon#about to read 5, iclass 3, count 0 2006.238.07:51:07.95#ibcon#read 5, iclass 3, count 0 2006.238.07:51:07.95#ibcon#about to read 6, iclass 3, count 0 2006.238.07:51:07.95#ibcon#read 6, iclass 3, count 0 2006.238.07:51:07.95#ibcon#end of sib2, iclass 3, count 0 2006.238.07:51:07.95#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:51:07.95#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:51:07.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:51:07.95#ibcon#*before write, iclass 3, count 0 2006.238.07:51:07.95#ibcon#enter sib2, iclass 3, count 0 2006.238.07:51:07.95#ibcon#flushed, iclass 3, count 0 2006.238.07:51:07.95#ibcon#about to write, iclass 3, count 0 2006.238.07:51:07.95#ibcon#wrote, iclass 3, count 0 2006.238.07:51:07.95#ibcon#about to read 3, iclass 3, count 0 2006.238.07:51:08.00#ibcon#read 3, iclass 3, count 0 2006.238.07:51:08.00#ibcon#about to read 4, iclass 3, count 0 2006.238.07:51:08.00#ibcon#read 4, iclass 3, count 0 2006.238.07:51:08.00#ibcon#about to read 5, iclass 3, count 0 2006.238.07:51:08.00#ibcon#read 5, iclass 3, count 0 2006.238.07:51:08.00#ibcon#about to read 6, iclass 3, count 0 2006.238.07:51:08.00#ibcon#read 6, iclass 3, count 0 2006.238.07:51:08.00#ibcon#end of sib2, iclass 3, count 0 2006.238.07:51:08.00#ibcon#*after write, iclass 3, count 0 2006.238.07:51:08.00#ibcon#*before return 0, iclass 3, count 0 2006.238.07:51:08.00#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:51:08.00#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:51:08.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:51:08.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:51:08.00$vc4f8/va=1,8 2006.238.07:51:08.00#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.238.07:51:08.00#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.238.07:51:08.00#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:08.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:51:08.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:51:08.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:51:08.00#ibcon#enter wrdev, iclass 5, count 2 2006.238.07:51:08.00#ibcon#first serial, iclass 5, count 2 2006.238.07:51:08.00#ibcon#enter sib2, iclass 5, count 2 2006.238.07:51:08.00#ibcon#flushed, iclass 5, count 2 2006.238.07:51:08.00#ibcon#about to write, iclass 5, count 2 2006.238.07:51:08.00#ibcon#wrote, iclass 5, count 2 2006.238.07:51:08.00#ibcon#about to read 3, iclass 5, count 2 2006.238.07:51:08.02#ibcon#read 3, iclass 5, count 2 2006.238.07:51:08.02#ibcon#about to read 4, iclass 5, count 2 2006.238.07:51:08.02#ibcon#read 4, iclass 5, count 2 2006.238.07:51:08.02#ibcon#about to read 5, iclass 5, count 2 2006.238.07:51:08.02#ibcon#read 5, iclass 5, count 2 2006.238.07:51:08.02#ibcon#about to read 6, iclass 5, count 2 2006.238.07:51:08.02#ibcon#read 6, iclass 5, count 2 2006.238.07:51:08.02#ibcon#end of sib2, iclass 5, count 2 2006.238.07:51:08.02#ibcon#*mode == 0, iclass 5, count 2 2006.238.07:51:08.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.238.07:51:08.02#ibcon#[25=AT01-08\r\n] 2006.238.07:51:08.02#ibcon#*before write, iclass 5, count 2 2006.238.07:51:08.02#ibcon#enter sib2, iclass 5, count 2 2006.238.07:51:08.02#ibcon#flushed, iclass 5, count 2 2006.238.07:51:08.02#ibcon#about to write, iclass 5, count 2 2006.238.07:51:08.02#ibcon#wrote, iclass 5, count 2 2006.238.07:51:08.02#ibcon#about to read 3, iclass 5, count 2 2006.238.07:51:08.05#ibcon#read 3, iclass 5, count 2 2006.238.07:51:08.05#ibcon#about to read 4, iclass 5, count 2 2006.238.07:51:08.05#ibcon#read 4, iclass 5, count 2 2006.238.07:51:08.05#ibcon#about to read 5, iclass 5, count 2 2006.238.07:51:08.05#ibcon#read 5, iclass 5, count 2 2006.238.07:51:08.05#ibcon#about to read 6, iclass 5, count 2 2006.238.07:51:08.05#ibcon#read 6, iclass 5, count 2 2006.238.07:51:08.05#ibcon#end of sib2, iclass 5, count 2 2006.238.07:51:08.05#ibcon#*after write, iclass 5, count 2 2006.238.07:51:08.05#ibcon#*before return 0, iclass 5, count 2 2006.238.07:51:08.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:51:08.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:51:08.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.238.07:51:08.05#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:08.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:51:08.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:51:08.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:51:08.17#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:51:08.17#ibcon#first serial, iclass 5, count 0 2006.238.07:51:08.17#ibcon#enter sib2, iclass 5, count 0 2006.238.07:51:08.17#ibcon#flushed, iclass 5, count 0 2006.238.07:51:08.17#ibcon#about to write, iclass 5, count 0 2006.238.07:51:08.17#ibcon#wrote, iclass 5, count 0 2006.238.07:51:08.17#ibcon#about to read 3, iclass 5, count 0 2006.238.07:51:08.19#ibcon#read 3, iclass 5, count 0 2006.238.07:51:08.19#ibcon#about to read 4, iclass 5, count 0 2006.238.07:51:08.19#ibcon#read 4, iclass 5, count 0 2006.238.07:51:08.19#ibcon#about to read 5, iclass 5, count 0 2006.238.07:51:08.19#ibcon#read 5, iclass 5, count 0 2006.238.07:51:08.19#ibcon#about to read 6, iclass 5, count 0 2006.238.07:51:08.19#ibcon#read 6, iclass 5, count 0 2006.238.07:51:08.19#ibcon#end of sib2, iclass 5, count 0 2006.238.07:51:08.19#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:51:08.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:51:08.19#ibcon#[25=USB\r\n] 2006.238.07:51:08.19#ibcon#*before write, iclass 5, count 0 2006.238.07:51:08.19#ibcon#enter sib2, iclass 5, count 0 2006.238.07:51:08.19#ibcon#flushed, iclass 5, count 0 2006.238.07:51:08.19#ibcon#about to write, iclass 5, count 0 2006.238.07:51:08.19#ibcon#wrote, iclass 5, count 0 2006.238.07:51:08.19#ibcon#about to read 3, iclass 5, count 0 2006.238.07:51:08.22#ibcon#read 3, iclass 5, count 0 2006.238.07:51:08.22#ibcon#about to read 4, iclass 5, count 0 2006.238.07:51:08.22#ibcon#read 4, iclass 5, count 0 2006.238.07:51:08.22#ibcon#about to read 5, iclass 5, count 0 2006.238.07:51:08.22#ibcon#read 5, iclass 5, count 0 2006.238.07:51:08.22#ibcon#about to read 6, iclass 5, count 0 2006.238.07:51:08.22#ibcon#read 6, iclass 5, count 0 2006.238.07:51:08.22#ibcon#end of sib2, iclass 5, count 0 2006.238.07:51:08.22#ibcon#*after write, iclass 5, count 0 2006.238.07:51:08.22#ibcon#*before return 0, iclass 5, count 0 2006.238.07:51:08.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:51:08.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:51:08.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:51:08.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:51:08.22$vc4f8/valo=2,572.99 2006.238.07:51:08.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.238.07:51:08.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.238.07:51:08.22#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:08.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:51:08.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:51:08.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:51:08.22#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:51:08.22#ibcon#first serial, iclass 7, count 0 2006.238.07:51:08.22#ibcon#enter sib2, iclass 7, count 0 2006.238.07:51:08.22#ibcon#flushed, iclass 7, count 0 2006.238.07:51:08.22#ibcon#about to write, iclass 7, count 0 2006.238.07:51:08.22#ibcon#wrote, iclass 7, count 0 2006.238.07:51:08.22#ibcon#about to read 3, iclass 7, count 0 2006.238.07:51:08.24#ibcon#read 3, iclass 7, count 0 2006.238.07:51:08.24#ibcon#about to read 4, iclass 7, count 0 2006.238.07:51:08.24#ibcon#read 4, iclass 7, count 0 2006.238.07:51:08.24#ibcon#about to read 5, iclass 7, count 0 2006.238.07:51:08.24#ibcon#read 5, iclass 7, count 0 2006.238.07:51:08.24#ibcon#about to read 6, iclass 7, count 0 2006.238.07:51:08.24#ibcon#read 6, iclass 7, count 0 2006.238.07:51:08.24#ibcon#end of sib2, iclass 7, count 0 2006.238.07:51:08.24#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:51:08.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:51:08.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:51:08.24#ibcon#*before write, iclass 7, count 0 2006.238.07:51:08.24#ibcon#enter sib2, iclass 7, count 0 2006.238.07:51:08.24#ibcon#flushed, iclass 7, count 0 2006.238.07:51:08.24#ibcon#about to write, iclass 7, count 0 2006.238.07:51:08.24#ibcon#wrote, iclass 7, count 0 2006.238.07:51:08.24#ibcon#about to read 3, iclass 7, count 0 2006.238.07:51:08.28#ibcon#read 3, iclass 7, count 0 2006.238.07:51:08.28#ibcon#about to read 4, iclass 7, count 0 2006.238.07:51:08.28#ibcon#read 4, iclass 7, count 0 2006.238.07:51:08.28#ibcon#about to read 5, iclass 7, count 0 2006.238.07:51:08.28#ibcon#read 5, iclass 7, count 0 2006.238.07:51:08.28#ibcon#about to read 6, iclass 7, count 0 2006.238.07:51:08.28#ibcon#read 6, iclass 7, count 0 2006.238.07:51:08.28#ibcon#end of sib2, iclass 7, count 0 2006.238.07:51:08.28#ibcon#*after write, iclass 7, count 0 2006.238.07:51:08.28#ibcon#*before return 0, iclass 7, count 0 2006.238.07:51:08.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:51:08.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:51:08.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:51:08.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:51:08.28$vc4f8/va=2,7 2006.238.07:51:08.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.238.07:51:08.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.238.07:51:08.28#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:08.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:51:08.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:51:08.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:51:08.34#ibcon#enter wrdev, iclass 11, count 2 2006.238.07:51:08.34#ibcon#first serial, iclass 11, count 2 2006.238.07:51:08.34#ibcon#enter sib2, iclass 11, count 2 2006.238.07:51:08.34#ibcon#flushed, iclass 11, count 2 2006.238.07:51:08.34#ibcon#about to write, iclass 11, count 2 2006.238.07:51:08.34#ibcon#wrote, iclass 11, count 2 2006.238.07:51:08.34#ibcon#about to read 3, iclass 11, count 2 2006.238.07:51:08.36#ibcon#read 3, iclass 11, count 2 2006.238.07:51:08.36#ibcon#about to read 4, iclass 11, count 2 2006.238.07:51:08.36#ibcon#read 4, iclass 11, count 2 2006.238.07:51:08.36#ibcon#about to read 5, iclass 11, count 2 2006.238.07:51:08.36#ibcon#read 5, iclass 11, count 2 2006.238.07:51:08.36#ibcon#about to read 6, iclass 11, count 2 2006.238.07:51:08.36#ibcon#read 6, iclass 11, count 2 2006.238.07:51:08.36#ibcon#end of sib2, iclass 11, count 2 2006.238.07:51:08.36#ibcon#*mode == 0, iclass 11, count 2 2006.238.07:51:08.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.238.07:51:08.36#ibcon#[25=AT02-07\r\n] 2006.238.07:51:08.36#ibcon#*before write, iclass 11, count 2 2006.238.07:51:08.36#ibcon#enter sib2, iclass 11, count 2 2006.238.07:51:08.36#ibcon#flushed, iclass 11, count 2 2006.238.07:51:08.36#ibcon#about to write, iclass 11, count 2 2006.238.07:51:08.36#ibcon#wrote, iclass 11, count 2 2006.238.07:51:08.36#ibcon#about to read 3, iclass 11, count 2 2006.238.07:51:08.40#ibcon#read 3, iclass 11, count 2 2006.238.07:51:08.40#ibcon#about to read 4, iclass 11, count 2 2006.238.07:51:08.40#ibcon#read 4, iclass 11, count 2 2006.238.07:51:08.40#ibcon#about to read 5, iclass 11, count 2 2006.238.07:51:08.40#ibcon#read 5, iclass 11, count 2 2006.238.07:51:08.40#ibcon#about to read 6, iclass 11, count 2 2006.238.07:51:08.40#ibcon#read 6, iclass 11, count 2 2006.238.07:51:08.40#ibcon#end of sib2, iclass 11, count 2 2006.238.07:51:08.40#ibcon#*after write, iclass 11, count 2 2006.238.07:51:08.40#ibcon#*before return 0, iclass 11, count 2 2006.238.07:51:08.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:51:08.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:51:08.40#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.238.07:51:08.40#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:08.40#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:51:08.52#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:51:08.52#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:51:08.52#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:51:08.52#ibcon#first serial, iclass 11, count 0 2006.238.07:51:08.52#ibcon#enter sib2, iclass 11, count 0 2006.238.07:51:08.52#ibcon#flushed, iclass 11, count 0 2006.238.07:51:08.52#ibcon#about to write, iclass 11, count 0 2006.238.07:51:08.52#ibcon#wrote, iclass 11, count 0 2006.238.07:51:08.52#ibcon#about to read 3, iclass 11, count 0 2006.238.07:51:08.54#ibcon#read 3, iclass 11, count 0 2006.238.07:51:08.54#ibcon#about to read 4, iclass 11, count 0 2006.238.07:51:08.54#ibcon#read 4, iclass 11, count 0 2006.238.07:51:08.54#ibcon#about to read 5, iclass 11, count 0 2006.238.07:51:08.54#ibcon#read 5, iclass 11, count 0 2006.238.07:51:08.54#ibcon#about to read 6, iclass 11, count 0 2006.238.07:51:08.54#ibcon#read 6, iclass 11, count 0 2006.238.07:51:08.54#ibcon#end of sib2, iclass 11, count 0 2006.238.07:51:08.54#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:51:08.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:51:08.54#ibcon#[25=USB\r\n] 2006.238.07:51:08.54#ibcon#*before write, iclass 11, count 0 2006.238.07:51:08.54#ibcon#enter sib2, iclass 11, count 0 2006.238.07:51:08.54#ibcon#flushed, iclass 11, count 0 2006.238.07:51:08.54#ibcon#about to write, iclass 11, count 0 2006.238.07:51:08.54#ibcon#wrote, iclass 11, count 0 2006.238.07:51:08.54#ibcon#about to read 3, iclass 11, count 0 2006.238.07:51:08.57#ibcon#read 3, iclass 11, count 0 2006.238.07:51:08.57#ibcon#about to read 4, iclass 11, count 0 2006.238.07:51:08.57#ibcon#read 4, iclass 11, count 0 2006.238.07:51:08.57#ibcon#about to read 5, iclass 11, count 0 2006.238.07:51:08.57#ibcon#read 5, iclass 11, count 0 2006.238.07:51:08.57#ibcon#about to read 6, iclass 11, count 0 2006.238.07:51:08.57#ibcon#read 6, iclass 11, count 0 2006.238.07:51:08.57#ibcon#end of sib2, iclass 11, count 0 2006.238.07:51:08.57#ibcon#*after write, iclass 11, count 0 2006.238.07:51:08.57#ibcon#*before return 0, iclass 11, count 0 2006.238.07:51:08.57#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:51:08.57#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:51:08.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:51:08.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:51:08.57$vc4f8/valo=3,672.99 2006.238.07:51:08.57#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.07:51:08.57#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.07:51:08.57#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:08.57#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:51:08.57#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:51:08.57#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:51:08.57#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:51:08.57#ibcon#first serial, iclass 13, count 0 2006.238.07:51:08.57#ibcon#enter sib2, iclass 13, count 0 2006.238.07:51:08.57#ibcon#flushed, iclass 13, count 0 2006.238.07:51:08.57#ibcon#about to write, iclass 13, count 0 2006.238.07:51:08.57#ibcon#wrote, iclass 13, count 0 2006.238.07:51:08.57#ibcon#about to read 3, iclass 13, count 0 2006.238.07:51:08.59#ibcon#read 3, iclass 13, count 0 2006.238.07:51:08.59#ibcon#about to read 4, iclass 13, count 0 2006.238.07:51:08.59#ibcon#read 4, iclass 13, count 0 2006.238.07:51:08.59#ibcon#about to read 5, iclass 13, count 0 2006.238.07:51:08.59#ibcon#read 5, iclass 13, count 0 2006.238.07:51:08.59#ibcon#about to read 6, iclass 13, count 0 2006.238.07:51:08.59#ibcon#read 6, iclass 13, count 0 2006.238.07:51:08.59#ibcon#end of sib2, iclass 13, count 0 2006.238.07:51:08.59#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:51:08.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:51:08.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:51:08.59#ibcon#*before write, iclass 13, count 0 2006.238.07:51:08.59#ibcon#enter sib2, iclass 13, count 0 2006.238.07:51:08.59#ibcon#flushed, iclass 13, count 0 2006.238.07:51:08.59#ibcon#about to write, iclass 13, count 0 2006.238.07:51:08.59#ibcon#wrote, iclass 13, count 0 2006.238.07:51:08.59#ibcon#about to read 3, iclass 13, count 0 2006.238.07:51:08.63#ibcon#read 3, iclass 13, count 0 2006.238.07:51:08.63#ibcon#about to read 4, iclass 13, count 0 2006.238.07:51:08.63#ibcon#read 4, iclass 13, count 0 2006.238.07:51:08.63#ibcon#about to read 5, iclass 13, count 0 2006.238.07:51:08.63#ibcon#read 5, iclass 13, count 0 2006.238.07:51:08.63#ibcon#about to read 6, iclass 13, count 0 2006.238.07:51:08.63#ibcon#read 6, iclass 13, count 0 2006.238.07:51:08.63#ibcon#end of sib2, iclass 13, count 0 2006.238.07:51:08.63#ibcon#*after write, iclass 13, count 0 2006.238.07:51:08.63#ibcon#*before return 0, iclass 13, count 0 2006.238.07:51:08.63#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:51:08.63#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:51:08.63#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:51:08.63#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:51:08.63$vc4f8/va=3,7 2006.238.07:51:08.63#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.238.07:51:08.63#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.238.07:51:08.63#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:08.63#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:51:08.69#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:51:08.69#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:51:08.69#ibcon#enter wrdev, iclass 15, count 2 2006.238.07:51:08.69#ibcon#first serial, iclass 15, count 2 2006.238.07:51:08.69#ibcon#enter sib2, iclass 15, count 2 2006.238.07:51:08.69#ibcon#flushed, iclass 15, count 2 2006.238.07:51:08.69#ibcon#about to write, iclass 15, count 2 2006.238.07:51:08.69#ibcon#wrote, iclass 15, count 2 2006.238.07:51:08.69#ibcon#about to read 3, iclass 15, count 2 2006.238.07:51:08.71#ibcon#read 3, iclass 15, count 2 2006.238.07:51:08.71#ibcon#about to read 4, iclass 15, count 2 2006.238.07:51:08.71#ibcon#read 4, iclass 15, count 2 2006.238.07:51:08.71#ibcon#about to read 5, iclass 15, count 2 2006.238.07:51:08.71#ibcon#read 5, iclass 15, count 2 2006.238.07:51:08.71#ibcon#about to read 6, iclass 15, count 2 2006.238.07:51:08.71#ibcon#read 6, iclass 15, count 2 2006.238.07:51:08.71#ibcon#end of sib2, iclass 15, count 2 2006.238.07:51:08.71#ibcon#*mode == 0, iclass 15, count 2 2006.238.07:51:08.71#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.238.07:51:08.71#ibcon#[25=AT03-07\r\n] 2006.238.07:51:08.71#ibcon#*before write, iclass 15, count 2 2006.238.07:51:08.71#ibcon#enter sib2, iclass 15, count 2 2006.238.07:51:08.71#ibcon#flushed, iclass 15, count 2 2006.238.07:51:08.71#ibcon#about to write, iclass 15, count 2 2006.238.07:51:08.71#ibcon#wrote, iclass 15, count 2 2006.238.07:51:08.71#ibcon#about to read 3, iclass 15, count 2 2006.238.07:51:08.75#ibcon#read 3, iclass 15, count 2 2006.238.07:51:08.75#ibcon#about to read 4, iclass 15, count 2 2006.238.07:51:08.75#ibcon#read 4, iclass 15, count 2 2006.238.07:51:08.75#ibcon#about to read 5, iclass 15, count 2 2006.238.07:51:08.75#ibcon#read 5, iclass 15, count 2 2006.238.07:51:08.75#ibcon#about to read 6, iclass 15, count 2 2006.238.07:51:08.75#ibcon#read 6, iclass 15, count 2 2006.238.07:51:08.75#ibcon#end of sib2, iclass 15, count 2 2006.238.07:51:08.75#ibcon#*after write, iclass 15, count 2 2006.238.07:51:08.75#ibcon#*before return 0, iclass 15, count 2 2006.238.07:51:08.75#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:51:08.75#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:51:08.75#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.238.07:51:08.75#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:08.75#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:51:08.87#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:51:08.87#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:51:08.87#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:51:08.87#ibcon#first serial, iclass 15, count 0 2006.238.07:51:08.87#ibcon#enter sib2, iclass 15, count 0 2006.238.07:51:08.87#ibcon#flushed, iclass 15, count 0 2006.238.07:51:08.87#ibcon#about to write, iclass 15, count 0 2006.238.07:51:08.87#ibcon#wrote, iclass 15, count 0 2006.238.07:51:08.87#ibcon#about to read 3, iclass 15, count 0 2006.238.07:51:08.89#ibcon#read 3, iclass 15, count 0 2006.238.07:51:08.89#ibcon#about to read 4, iclass 15, count 0 2006.238.07:51:08.89#ibcon#read 4, iclass 15, count 0 2006.238.07:51:08.89#ibcon#about to read 5, iclass 15, count 0 2006.238.07:51:08.89#ibcon#read 5, iclass 15, count 0 2006.238.07:51:08.89#ibcon#about to read 6, iclass 15, count 0 2006.238.07:51:08.89#ibcon#read 6, iclass 15, count 0 2006.238.07:51:08.89#ibcon#end of sib2, iclass 15, count 0 2006.238.07:51:08.89#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:51:08.89#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:51:08.89#ibcon#[25=USB\r\n] 2006.238.07:51:08.89#ibcon#*before write, iclass 15, count 0 2006.238.07:51:08.89#ibcon#enter sib2, iclass 15, count 0 2006.238.07:51:08.89#ibcon#flushed, iclass 15, count 0 2006.238.07:51:08.89#ibcon#about to write, iclass 15, count 0 2006.238.07:51:08.89#ibcon#wrote, iclass 15, count 0 2006.238.07:51:08.89#ibcon#about to read 3, iclass 15, count 0 2006.238.07:51:08.92#ibcon#read 3, iclass 15, count 0 2006.238.07:51:08.92#ibcon#about to read 4, iclass 15, count 0 2006.238.07:51:08.92#ibcon#read 4, iclass 15, count 0 2006.238.07:51:08.92#ibcon#about to read 5, iclass 15, count 0 2006.238.07:51:08.92#ibcon#read 5, iclass 15, count 0 2006.238.07:51:08.92#ibcon#about to read 6, iclass 15, count 0 2006.238.07:51:08.92#ibcon#read 6, iclass 15, count 0 2006.238.07:51:08.92#ibcon#end of sib2, iclass 15, count 0 2006.238.07:51:08.92#ibcon#*after write, iclass 15, count 0 2006.238.07:51:08.92#ibcon#*before return 0, iclass 15, count 0 2006.238.07:51:08.92#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:51:08.92#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:51:08.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:51:08.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:51:08.92$vc4f8/valo=4,832.99 2006.238.07:51:08.92#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.07:51:08.92#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.07:51:08.92#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:08.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:51:08.92#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:51:08.92#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:51:08.92#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:51:08.92#ibcon#first serial, iclass 17, count 0 2006.238.07:51:08.92#ibcon#enter sib2, iclass 17, count 0 2006.238.07:51:08.92#ibcon#flushed, iclass 17, count 0 2006.238.07:51:08.92#ibcon#about to write, iclass 17, count 0 2006.238.07:51:08.92#ibcon#wrote, iclass 17, count 0 2006.238.07:51:08.92#ibcon#about to read 3, iclass 17, count 0 2006.238.07:51:08.94#ibcon#read 3, iclass 17, count 0 2006.238.07:51:08.94#ibcon#about to read 4, iclass 17, count 0 2006.238.07:51:08.94#ibcon#read 4, iclass 17, count 0 2006.238.07:51:08.94#ibcon#about to read 5, iclass 17, count 0 2006.238.07:51:08.94#ibcon#read 5, iclass 17, count 0 2006.238.07:51:08.94#ibcon#about to read 6, iclass 17, count 0 2006.238.07:51:08.94#ibcon#read 6, iclass 17, count 0 2006.238.07:51:08.94#ibcon#end of sib2, iclass 17, count 0 2006.238.07:51:08.94#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:51:08.94#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:51:08.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:51:08.94#ibcon#*before write, iclass 17, count 0 2006.238.07:51:08.94#ibcon#enter sib2, iclass 17, count 0 2006.238.07:51:08.94#ibcon#flushed, iclass 17, count 0 2006.238.07:51:08.94#ibcon#about to write, iclass 17, count 0 2006.238.07:51:08.94#ibcon#wrote, iclass 17, count 0 2006.238.07:51:08.94#ibcon#about to read 3, iclass 17, count 0 2006.238.07:51:08.98#ibcon#read 3, iclass 17, count 0 2006.238.07:51:08.98#ibcon#about to read 4, iclass 17, count 0 2006.238.07:51:08.98#ibcon#read 4, iclass 17, count 0 2006.238.07:51:08.98#ibcon#about to read 5, iclass 17, count 0 2006.238.07:51:08.98#ibcon#read 5, iclass 17, count 0 2006.238.07:51:08.98#ibcon#about to read 6, iclass 17, count 0 2006.238.07:51:08.98#ibcon#read 6, iclass 17, count 0 2006.238.07:51:08.98#ibcon#end of sib2, iclass 17, count 0 2006.238.07:51:08.98#ibcon#*after write, iclass 17, count 0 2006.238.07:51:08.98#ibcon#*before return 0, iclass 17, count 0 2006.238.07:51:08.98#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:51:08.98#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:51:08.98#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:51:08.98#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:51:08.98$vc4f8/va=4,7 2006.238.07:51:08.98#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.238.07:51:08.98#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.238.07:51:08.98#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:08.98#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:51:09.04#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:51:09.04#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:51:09.04#ibcon#enter wrdev, iclass 19, count 2 2006.238.07:51:09.04#ibcon#first serial, iclass 19, count 2 2006.238.07:51:09.04#ibcon#enter sib2, iclass 19, count 2 2006.238.07:51:09.04#ibcon#flushed, iclass 19, count 2 2006.238.07:51:09.04#ibcon#about to write, iclass 19, count 2 2006.238.07:51:09.04#ibcon#wrote, iclass 19, count 2 2006.238.07:51:09.04#ibcon#about to read 3, iclass 19, count 2 2006.238.07:51:09.06#ibcon#read 3, iclass 19, count 2 2006.238.07:51:09.06#ibcon#about to read 4, iclass 19, count 2 2006.238.07:51:09.06#ibcon#read 4, iclass 19, count 2 2006.238.07:51:09.06#ibcon#about to read 5, iclass 19, count 2 2006.238.07:51:09.06#ibcon#read 5, iclass 19, count 2 2006.238.07:51:09.06#ibcon#about to read 6, iclass 19, count 2 2006.238.07:51:09.06#ibcon#read 6, iclass 19, count 2 2006.238.07:51:09.06#ibcon#end of sib2, iclass 19, count 2 2006.238.07:51:09.06#ibcon#*mode == 0, iclass 19, count 2 2006.238.07:51:09.06#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.238.07:51:09.06#ibcon#[25=AT04-07\r\n] 2006.238.07:51:09.06#ibcon#*before write, iclass 19, count 2 2006.238.07:51:09.06#ibcon#enter sib2, iclass 19, count 2 2006.238.07:51:09.06#ibcon#flushed, iclass 19, count 2 2006.238.07:51:09.06#ibcon#about to write, iclass 19, count 2 2006.238.07:51:09.06#ibcon#wrote, iclass 19, count 2 2006.238.07:51:09.06#ibcon#about to read 3, iclass 19, count 2 2006.238.07:51:09.09#ibcon#read 3, iclass 19, count 2 2006.238.07:51:09.09#ibcon#about to read 4, iclass 19, count 2 2006.238.07:51:09.09#ibcon#read 4, iclass 19, count 2 2006.238.07:51:09.09#ibcon#about to read 5, iclass 19, count 2 2006.238.07:51:09.09#ibcon#read 5, iclass 19, count 2 2006.238.07:51:09.09#ibcon#about to read 6, iclass 19, count 2 2006.238.07:51:09.09#ibcon#read 6, iclass 19, count 2 2006.238.07:51:09.09#ibcon#end of sib2, iclass 19, count 2 2006.238.07:51:09.09#ibcon#*after write, iclass 19, count 2 2006.238.07:51:09.09#ibcon#*before return 0, iclass 19, count 2 2006.238.07:51:09.09#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:51:09.09#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:51:09.09#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.238.07:51:09.09#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:09.09#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:51:09.21#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:51:09.21#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:51:09.21#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:51:09.21#ibcon#first serial, iclass 19, count 0 2006.238.07:51:09.21#ibcon#enter sib2, iclass 19, count 0 2006.238.07:51:09.21#ibcon#flushed, iclass 19, count 0 2006.238.07:51:09.21#ibcon#about to write, iclass 19, count 0 2006.238.07:51:09.21#ibcon#wrote, iclass 19, count 0 2006.238.07:51:09.21#ibcon#about to read 3, iclass 19, count 0 2006.238.07:51:09.23#ibcon#read 3, iclass 19, count 0 2006.238.07:51:09.23#ibcon#about to read 4, iclass 19, count 0 2006.238.07:51:09.23#ibcon#read 4, iclass 19, count 0 2006.238.07:51:09.23#ibcon#about to read 5, iclass 19, count 0 2006.238.07:51:09.23#ibcon#read 5, iclass 19, count 0 2006.238.07:51:09.23#ibcon#about to read 6, iclass 19, count 0 2006.238.07:51:09.23#ibcon#read 6, iclass 19, count 0 2006.238.07:51:09.23#ibcon#end of sib2, iclass 19, count 0 2006.238.07:51:09.23#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:51:09.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:51:09.23#ibcon#[25=USB\r\n] 2006.238.07:51:09.23#ibcon#*before write, iclass 19, count 0 2006.238.07:51:09.23#ibcon#enter sib2, iclass 19, count 0 2006.238.07:51:09.23#ibcon#flushed, iclass 19, count 0 2006.238.07:51:09.23#ibcon#about to write, iclass 19, count 0 2006.238.07:51:09.23#ibcon#wrote, iclass 19, count 0 2006.238.07:51:09.23#ibcon#about to read 3, iclass 19, count 0 2006.238.07:51:09.26#ibcon#read 3, iclass 19, count 0 2006.238.07:51:09.26#ibcon#about to read 4, iclass 19, count 0 2006.238.07:51:09.26#ibcon#read 4, iclass 19, count 0 2006.238.07:51:09.26#ibcon#about to read 5, iclass 19, count 0 2006.238.07:51:09.26#ibcon#read 5, iclass 19, count 0 2006.238.07:51:09.26#ibcon#about to read 6, iclass 19, count 0 2006.238.07:51:09.26#ibcon#read 6, iclass 19, count 0 2006.238.07:51:09.26#ibcon#end of sib2, iclass 19, count 0 2006.238.07:51:09.26#ibcon#*after write, iclass 19, count 0 2006.238.07:51:09.26#ibcon#*before return 0, iclass 19, count 0 2006.238.07:51:09.26#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:51:09.26#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:51:09.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:51:09.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:51:09.26$vc4f8/valo=5,652.99 2006.238.07:51:09.26#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.07:51:09.26#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.07:51:09.26#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:09.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:51:09.26#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:51:09.26#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:51:09.26#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:51:09.26#ibcon#first serial, iclass 21, count 0 2006.238.07:51:09.26#ibcon#enter sib2, iclass 21, count 0 2006.238.07:51:09.26#ibcon#flushed, iclass 21, count 0 2006.238.07:51:09.26#ibcon#about to write, iclass 21, count 0 2006.238.07:51:09.26#ibcon#wrote, iclass 21, count 0 2006.238.07:51:09.26#ibcon#about to read 3, iclass 21, count 0 2006.238.07:51:09.28#ibcon#read 3, iclass 21, count 0 2006.238.07:51:09.28#ibcon#about to read 4, iclass 21, count 0 2006.238.07:51:09.28#ibcon#read 4, iclass 21, count 0 2006.238.07:51:09.28#ibcon#about to read 5, iclass 21, count 0 2006.238.07:51:09.28#ibcon#read 5, iclass 21, count 0 2006.238.07:51:09.28#ibcon#about to read 6, iclass 21, count 0 2006.238.07:51:09.28#ibcon#read 6, iclass 21, count 0 2006.238.07:51:09.28#ibcon#end of sib2, iclass 21, count 0 2006.238.07:51:09.28#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:51:09.28#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:51:09.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:51:09.28#ibcon#*before write, iclass 21, count 0 2006.238.07:51:09.28#ibcon#enter sib2, iclass 21, count 0 2006.238.07:51:09.28#ibcon#flushed, iclass 21, count 0 2006.238.07:51:09.28#ibcon#about to write, iclass 21, count 0 2006.238.07:51:09.28#ibcon#wrote, iclass 21, count 0 2006.238.07:51:09.28#ibcon#about to read 3, iclass 21, count 0 2006.238.07:51:09.32#ibcon#read 3, iclass 21, count 0 2006.238.07:51:09.32#ibcon#about to read 4, iclass 21, count 0 2006.238.07:51:09.32#ibcon#read 4, iclass 21, count 0 2006.238.07:51:09.32#ibcon#about to read 5, iclass 21, count 0 2006.238.07:51:09.32#ibcon#read 5, iclass 21, count 0 2006.238.07:51:09.32#ibcon#about to read 6, iclass 21, count 0 2006.238.07:51:09.32#ibcon#read 6, iclass 21, count 0 2006.238.07:51:09.32#ibcon#end of sib2, iclass 21, count 0 2006.238.07:51:09.32#ibcon#*after write, iclass 21, count 0 2006.238.07:51:09.32#ibcon#*before return 0, iclass 21, count 0 2006.238.07:51:09.32#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:51:09.32#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:51:09.32#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:51:09.32#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:51:09.32$vc4f8/va=5,8 2006.238.07:51:09.32#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.238.07:51:09.32#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.238.07:51:09.32#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:09.32#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:51:09.38#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:51:09.38#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:51:09.38#ibcon#enter wrdev, iclass 23, count 2 2006.238.07:51:09.38#ibcon#first serial, iclass 23, count 2 2006.238.07:51:09.38#ibcon#enter sib2, iclass 23, count 2 2006.238.07:51:09.38#ibcon#flushed, iclass 23, count 2 2006.238.07:51:09.38#ibcon#about to write, iclass 23, count 2 2006.238.07:51:09.38#ibcon#wrote, iclass 23, count 2 2006.238.07:51:09.38#ibcon#about to read 3, iclass 23, count 2 2006.238.07:51:09.40#ibcon#read 3, iclass 23, count 2 2006.238.07:51:09.40#ibcon#about to read 4, iclass 23, count 2 2006.238.07:51:09.40#ibcon#read 4, iclass 23, count 2 2006.238.07:51:09.40#ibcon#about to read 5, iclass 23, count 2 2006.238.07:51:09.40#ibcon#read 5, iclass 23, count 2 2006.238.07:51:09.40#ibcon#about to read 6, iclass 23, count 2 2006.238.07:51:09.40#ibcon#read 6, iclass 23, count 2 2006.238.07:51:09.40#ibcon#end of sib2, iclass 23, count 2 2006.238.07:51:09.40#ibcon#*mode == 0, iclass 23, count 2 2006.238.07:51:09.40#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.238.07:51:09.40#ibcon#[25=AT05-08\r\n] 2006.238.07:51:09.40#ibcon#*before write, iclass 23, count 2 2006.238.07:51:09.40#ibcon#enter sib2, iclass 23, count 2 2006.238.07:51:09.40#ibcon#flushed, iclass 23, count 2 2006.238.07:51:09.40#ibcon#about to write, iclass 23, count 2 2006.238.07:51:09.40#ibcon#wrote, iclass 23, count 2 2006.238.07:51:09.40#ibcon#about to read 3, iclass 23, count 2 2006.238.07:51:09.43#ibcon#read 3, iclass 23, count 2 2006.238.07:51:09.43#ibcon#about to read 4, iclass 23, count 2 2006.238.07:51:09.43#ibcon#read 4, iclass 23, count 2 2006.238.07:51:09.43#ibcon#about to read 5, iclass 23, count 2 2006.238.07:51:09.43#ibcon#read 5, iclass 23, count 2 2006.238.07:51:09.43#ibcon#about to read 6, iclass 23, count 2 2006.238.07:51:09.43#ibcon#read 6, iclass 23, count 2 2006.238.07:51:09.43#ibcon#end of sib2, iclass 23, count 2 2006.238.07:51:09.43#ibcon#*after write, iclass 23, count 2 2006.238.07:51:09.43#ibcon#*before return 0, iclass 23, count 2 2006.238.07:51:09.43#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:51:09.43#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:51:09.43#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.238.07:51:09.43#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:09.43#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:51:09.55#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:51:09.55#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:51:09.55#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:51:09.55#ibcon#first serial, iclass 23, count 0 2006.238.07:51:09.55#ibcon#enter sib2, iclass 23, count 0 2006.238.07:51:09.55#ibcon#flushed, iclass 23, count 0 2006.238.07:51:09.55#ibcon#about to write, iclass 23, count 0 2006.238.07:51:09.55#ibcon#wrote, iclass 23, count 0 2006.238.07:51:09.55#ibcon#about to read 3, iclass 23, count 0 2006.238.07:51:09.57#ibcon#read 3, iclass 23, count 0 2006.238.07:51:09.57#ibcon#about to read 4, iclass 23, count 0 2006.238.07:51:09.57#ibcon#read 4, iclass 23, count 0 2006.238.07:51:09.57#ibcon#about to read 5, iclass 23, count 0 2006.238.07:51:09.57#ibcon#read 5, iclass 23, count 0 2006.238.07:51:09.57#ibcon#about to read 6, iclass 23, count 0 2006.238.07:51:09.57#ibcon#read 6, iclass 23, count 0 2006.238.07:51:09.57#ibcon#end of sib2, iclass 23, count 0 2006.238.07:51:09.57#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:51:09.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:51:09.57#ibcon#[25=USB\r\n] 2006.238.07:51:09.57#ibcon#*before write, iclass 23, count 0 2006.238.07:51:09.57#ibcon#enter sib2, iclass 23, count 0 2006.238.07:51:09.57#ibcon#flushed, iclass 23, count 0 2006.238.07:51:09.57#ibcon#about to write, iclass 23, count 0 2006.238.07:51:09.57#ibcon#wrote, iclass 23, count 0 2006.238.07:51:09.57#ibcon#about to read 3, iclass 23, count 0 2006.238.07:51:09.60#ibcon#read 3, iclass 23, count 0 2006.238.07:51:09.60#ibcon#about to read 4, iclass 23, count 0 2006.238.07:51:09.60#ibcon#read 4, iclass 23, count 0 2006.238.07:51:09.60#ibcon#about to read 5, iclass 23, count 0 2006.238.07:51:09.60#ibcon#read 5, iclass 23, count 0 2006.238.07:51:09.60#ibcon#about to read 6, iclass 23, count 0 2006.238.07:51:09.60#ibcon#read 6, iclass 23, count 0 2006.238.07:51:09.60#ibcon#end of sib2, iclass 23, count 0 2006.238.07:51:09.60#ibcon#*after write, iclass 23, count 0 2006.238.07:51:09.60#ibcon#*before return 0, iclass 23, count 0 2006.238.07:51:09.60#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:51:09.60#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:51:09.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:51:09.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:51:09.60$vc4f8/valo=6,772.99 2006.238.07:51:09.60#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.07:51:09.60#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.07:51:09.60#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:09.60#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:51:09.60#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:51:09.60#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:51:09.60#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:51:09.60#ibcon#first serial, iclass 25, count 0 2006.238.07:51:09.60#ibcon#enter sib2, iclass 25, count 0 2006.238.07:51:09.60#ibcon#flushed, iclass 25, count 0 2006.238.07:51:09.60#ibcon#about to write, iclass 25, count 0 2006.238.07:51:09.60#ibcon#wrote, iclass 25, count 0 2006.238.07:51:09.60#ibcon#about to read 3, iclass 25, count 0 2006.238.07:51:09.62#ibcon#read 3, iclass 25, count 0 2006.238.07:51:09.62#ibcon#about to read 4, iclass 25, count 0 2006.238.07:51:09.62#ibcon#read 4, iclass 25, count 0 2006.238.07:51:09.62#ibcon#about to read 5, iclass 25, count 0 2006.238.07:51:09.62#ibcon#read 5, iclass 25, count 0 2006.238.07:51:09.62#ibcon#about to read 6, iclass 25, count 0 2006.238.07:51:09.62#ibcon#read 6, iclass 25, count 0 2006.238.07:51:09.62#ibcon#end of sib2, iclass 25, count 0 2006.238.07:51:09.62#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:51:09.62#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:51:09.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:51:09.62#ibcon#*before write, iclass 25, count 0 2006.238.07:51:09.62#ibcon#enter sib2, iclass 25, count 0 2006.238.07:51:09.62#ibcon#flushed, iclass 25, count 0 2006.238.07:51:09.62#ibcon#about to write, iclass 25, count 0 2006.238.07:51:09.62#ibcon#wrote, iclass 25, count 0 2006.238.07:51:09.62#ibcon#about to read 3, iclass 25, count 0 2006.238.07:51:09.66#ibcon#read 3, iclass 25, count 0 2006.238.07:51:09.66#ibcon#about to read 4, iclass 25, count 0 2006.238.07:51:09.66#ibcon#read 4, iclass 25, count 0 2006.238.07:51:09.66#ibcon#about to read 5, iclass 25, count 0 2006.238.07:51:09.66#ibcon#read 5, iclass 25, count 0 2006.238.07:51:09.66#ibcon#about to read 6, iclass 25, count 0 2006.238.07:51:09.66#ibcon#read 6, iclass 25, count 0 2006.238.07:51:09.66#ibcon#end of sib2, iclass 25, count 0 2006.238.07:51:09.66#ibcon#*after write, iclass 25, count 0 2006.238.07:51:09.66#ibcon#*before return 0, iclass 25, count 0 2006.238.07:51:09.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:51:09.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:51:09.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:51:09.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:51:09.66$vc4f8/va=6,7 2006.238.07:51:09.66#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.238.07:51:09.66#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.238.07:51:09.66#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:09.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:51:09.72#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:51:09.72#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:51:09.72#ibcon#enter wrdev, iclass 27, count 2 2006.238.07:51:09.72#ibcon#first serial, iclass 27, count 2 2006.238.07:51:09.72#ibcon#enter sib2, iclass 27, count 2 2006.238.07:51:09.72#ibcon#flushed, iclass 27, count 2 2006.238.07:51:09.72#ibcon#about to write, iclass 27, count 2 2006.238.07:51:09.72#ibcon#wrote, iclass 27, count 2 2006.238.07:51:09.72#ibcon#about to read 3, iclass 27, count 2 2006.238.07:51:09.74#ibcon#read 3, iclass 27, count 2 2006.238.07:51:09.74#ibcon#about to read 4, iclass 27, count 2 2006.238.07:51:09.74#ibcon#read 4, iclass 27, count 2 2006.238.07:51:09.74#ibcon#about to read 5, iclass 27, count 2 2006.238.07:51:09.74#ibcon#read 5, iclass 27, count 2 2006.238.07:51:09.74#ibcon#about to read 6, iclass 27, count 2 2006.238.07:51:09.74#ibcon#read 6, iclass 27, count 2 2006.238.07:51:09.74#ibcon#end of sib2, iclass 27, count 2 2006.238.07:51:09.74#ibcon#*mode == 0, iclass 27, count 2 2006.238.07:51:09.74#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.238.07:51:09.74#ibcon#[25=AT06-07\r\n] 2006.238.07:51:09.74#ibcon#*before write, iclass 27, count 2 2006.238.07:51:09.74#ibcon#enter sib2, iclass 27, count 2 2006.238.07:51:09.74#ibcon#flushed, iclass 27, count 2 2006.238.07:51:09.74#ibcon#about to write, iclass 27, count 2 2006.238.07:51:09.74#ibcon#wrote, iclass 27, count 2 2006.238.07:51:09.74#ibcon#about to read 3, iclass 27, count 2 2006.238.07:51:09.77#ibcon#read 3, iclass 27, count 2 2006.238.07:51:09.77#ibcon#about to read 4, iclass 27, count 2 2006.238.07:51:09.77#ibcon#read 4, iclass 27, count 2 2006.238.07:51:09.77#ibcon#about to read 5, iclass 27, count 2 2006.238.07:51:09.77#ibcon#read 5, iclass 27, count 2 2006.238.07:51:09.77#ibcon#about to read 6, iclass 27, count 2 2006.238.07:51:09.77#ibcon#read 6, iclass 27, count 2 2006.238.07:51:09.77#ibcon#end of sib2, iclass 27, count 2 2006.238.07:51:09.77#ibcon#*after write, iclass 27, count 2 2006.238.07:51:09.77#ibcon#*before return 0, iclass 27, count 2 2006.238.07:51:09.77#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:51:09.77#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.238.07:51:09.77#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.238.07:51:09.77#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:09.77#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:51:09.89#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:51:09.89#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:51:09.89#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:51:09.89#ibcon#first serial, iclass 27, count 0 2006.238.07:51:09.89#ibcon#enter sib2, iclass 27, count 0 2006.238.07:51:09.89#ibcon#flushed, iclass 27, count 0 2006.238.07:51:09.89#ibcon#about to write, iclass 27, count 0 2006.238.07:51:09.89#ibcon#wrote, iclass 27, count 0 2006.238.07:51:09.89#ibcon#about to read 3, iclass 27, count 0 2006.238.07:51:09.91#ibcon#read 3, iclass 27, count 0 2006.238.07:51:09.91#ibcon#about to read 4, iclass 27, count 0 2006.238.07:51:09.91#ibcon#read 4, iclass 27, count 0 2006.238.07:51:09.91#ibcon#about to read 5, iclass 27, count 0 2006.238.07:51:09.91#ibcon#read 5, iclass 27, count 0 2006.238.07:51:09.91#ibcon#about to read 6, iclass 27, count 0 2006.238.07:51:09.91#ibcon#read 6, iclass 27, count 0 2006.238.07:51:09.91#ibcon#end of sib2, iclass 27, count 0 2006.238.07:51:09.91#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:51:09.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:51:09.91#ibcon#[25=USB\r\n] 2006.238.07:51:09.91#ibcon#*before write, iclass 27, count 0 2006.238.07:51:09.91#ibcon#enter sib2, iclass 27, count 0 2006.238.07:51:09.91#ibcon#flushed, iclass 27, count 0 2006.238.07:51:09.91#ibcon#about to write, iclass 27, count 0 2006.238.07:51:09.91#ibcon#wrote, iclass 27, count 0 2006.238.07:51:09.91#ibcon#about to read 3, iclass 27, count 0 2006.238.07:51:09.94#ibcon#read 3, iclass 27, count 0 2006.238.07:51:09.94#ibcon#about to read 4, iclass 27, count 0 2006.238.07:51:09.94#ibcon#read 4, iclass 27, count 0 2006.238.07:51:09.94#ibcon#about to read 5, iclass 27, count 0 2006.238.07:51:09.94#ibcon#read 5, iclass 27, count 0 2006.238.07:51:09.94#ibcon#about to read 6, iclass 27, count 0 2006.238.07:51:09.94#ibcon#read 6, iclass 27, count 0 2006.238.07:51:09.94#ibcon#end of sib2, iclass 27, count 0 2006.238.07:51:09.94#ibcon#*after write, iclass 27, count 0 2006.238.07:51:09.94#ibcon#*before return 0, iclass 27, count 0 2006.238.07:51:09.94#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:51:09.94#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.238.07:51:09.94#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:51:09.94#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:51:09.94$vc4f8/valo=7,832.99 2006.238.07:51:09.94#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.238.07:51:09.94#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.238.07:51:09.94#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:09.94#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:51:09.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:51:09.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:51:09.94#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:51:09.94#ibcon#first serial, iclass 29, count 0 2006.238.07:51:09.94#ibcon#enter sib2, iclass 29, count 0 2006.238.07:51:09.94#ibcon#flushed, iclass 29, count 0 2006.238.07:51:09.94#ibcon#about to write, iclass 29, count 0 2006.238.07:51:09.94#ibcon#wrote, iclass 29, count 0 2006.238.07:51:09.94#ibcon#about to read 3, iclass 29, count 0 2006.238.07:51:09.96#ibcon#read 3, iclass 29, count 0 2006.238.07:51:09.96#ibcon#about to read 4, iclass 29, count 0 2006.238.07:51:09.96#ibcon#read 4, iclass 29, count 0 2006.238.07:51:09.96#ibcon#about to read 5, iclass 29, count 0 2006.238.07:51:09.96#ibcon#read 5, iclass 29, count 0 2006.238.07:51:09.96#ibcon#about to read 6, iclass 29, count 0 2006.238.07:51:09.96#ibcon#read 6, iclass 29, count 0 2006.238.07:51:09.96#ibcon#end of sib2, iclass 29, count 0 2006.238.07:51:09.96#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:51:09.96#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:51:09.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:51:09.96#ibcon#*before write, iclass 29, count 0 2006.238.07:51:09.96#ibcon#enter sib2, iclass 29, count 0 2006.238.07:51:09.96#ibcon#flushed, iclass 29, count 0 2006.238.07:51:09.96#ibcon#about to write, iclass 29, count 0 2006.238.07:51:09.96#ibcon#wrote, iclass 29, count 0 2006.238.07:51:09.96#ibcon#about to read 3, iclass 29, count 0 2006.238.07:51:10.00#ibcon#read 3, iclass 29, count 0 2006.238.07:51:10.00#ibcon#about to read 4, iclass 29, count 0 2006.238.07:51:10.00#ibcon#read 4, iclass 29, count 0 2006.238.07:51:10.00#ibcon#about to read 5, iclass 29, count 0 2006.238.07:51:10.00#ibcon#read 5, iclass 29, count 0 2006.238.07:51:10.00#ibcon#about to read 6, iclass 29, count 0 2006.238.07:51:10.00#ibcon#read 6, iclass 29, count 0 2006.238.07:51:10.00#ibcon#end of sib2, iclass 29, count 0 2006.238.07:51:10.00#ibcon#*after write, iclass 29, count 0 2006.238.07:51:10.00#ibcon#*before return 0, iclass 29, count 0 2006.238.07:51:10.00#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:51:10.00#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.238.07:51:10.00#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:51:10.00#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:51:10.00$vc4f8/va=7,7 2006.238.07:51:10.00#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.238.07:51:10.00#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.238.07:51:10.00#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:10.00#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:51:10.06#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:51:10.06#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:51:10.06#ibcon#enter wrdev, iclass 31, count 2 2006.238.07:51:10.06#ibcon#first serial, iclass 31, count 2 2006.238.07:51:10.06#ibcon#enter sib2, iclass 31, count 2 2006.238.07:51:10.06#ibcon#flushed, iclass 31, count 2 2006.238.07:51:10.06#ibcon#about to write, iclass 31, count 2 2006.238.07:51:10.06#ibcon#wrote, iclass 31, count 2 2006.238.07:51:10.06#ibcon#about to read 3, iclass 31, count 2 2006.238.07:51:10.08#ibcon#read 3, iclass 31, count 2 2006.238.07:51:10.08#ibcon#about to read 4, iclass 31, count 2 2006.238.07:51:10.08#ibcon#read 4, iclass 31, count 2 2006.238.07:51:10.08#ibcon#about to read 5, iclass 31, count 2 2006.238.07:51:10.08#ibcon#read 5, iclass 31, count 2 2006.238.07:51:10.08#ibcon#about to read 6, iclass 31, count 2 2006.238.07:51:10.08#ibcon#read 6, iclass 31, count 2 2006.238.07:51:10.08#ibcon#end of sib2, iclass 31, count 2 2006.238.07:51:10.08#ibcon#*mode == 0, iclass 31, count 2 2006.238.07:51:10.08#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.238.07:51:10.08#ibcon#[25=AT07-07\r\n] 2006.238.07:51:10.08#ibcon#*before write, iclass 31, count 2 2006.238.07:51:10.08#ibcon#enter sib2, iclass 31, count 2 2006.238.07:51:10.08#ibcon#flushed, iclass 31, count 2 2006.238.07:51:10.08#ibcon#about to write, iclass 31, count 2 2006.238.07:51:10.08#ibcon#wrote, iclass 31, count 2 2006.238.07:51:10.08#ibcon#about to read 3, iclass 31, count 2 2006.238.07:51:10.11#ibcon#read 3, iclass 31, count 2 2006.238.07:51:10.11#ibcon#about to read 4, iclass 31, count 2 2006.238.07:51:10.11#ibcon#read 4, iclass 31, count 2 2006.238.07:51:10.11#ibcon#about to read 5, iclass 31, count 2 2006.238.07:51:10.11#ibcon#read 5, iclass 31, count 2 2006.238.07:51:10.11#ibcon#about to read 6, iclass 31, count 2 2006.238.07:51:10.11#ibcon#read 6, iclass 31, count 2 2006.238.07:51:10.11#ibcon#end of sib2, iclass 31, count 2 2006.238.07:51:10.11#ibcon#*after write, iclass 31, count 2 2006.238.07:51:10.11#ibcon#*before return 0, iclass 31, count 2 2006.238.07:51:10.11#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:51:10.11#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.238.07:51:10.11#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.238.07:51:10.11#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:10.11#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:51:10.23#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:51:10.23#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:51:10.23#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:51:10.23#ibcon#first serial, iclass 31, count 0 2006.238.07:51:10.23#ibcon#enter sib2, iclass 31, count 0 2006.238.07:51:10.23#ibcon#flushed, iclass 31, count 0 2006.238.07:51:10.23#ibcon#about to write, iclass 31, count 0 2006.238.07:51:10.23#ibcon#wrote, iclass 31, count 0 2006.238.07:51:10.23#ibcon#about to read 3, iclass 31, count 0 2006.238.07:51:10.25#ibcon#read 3, iclass 31, count 0 2006.238.07:51:10.25#ibcon#about to read 4, iclass 31, count 0 2006.238.07:51:10.25#ibcon#read 4, iclass 31, count 0 2006.238.07:51:10.25#ibcon#about to read 5, iclass 31, count 0 2006.238.07:51:10.25#ibcon#read 5, iclass 31, count 0 2006.238.07:51:10.25#ibcon#about to read 6, iclass 31, count 0 2006.238.07:51:10.25#ibcon#read 6, iclass 31, count 0 2006.238.07:51:10.25#ibcon#end of sib2, iclass 31, count 0 2006.238.07:51:10.25#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:51:10.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:51:10.25#ibcon#[25=USB\r\n] 2006.238.07:51:10.25#ibcon#*before write, iclass 31, count 0 2006.238.07:51:10.25#ibcon#enter sib2, iclass 31, count 0 2006.238.07:51:10.25#ibcon#flushed, iclass 31, count 0 2006.238.07:51:10.25#ibcon#about to write, iclass 31, count 0 2006.238.07:51:10.25#ibcon#wrote, iclass 31, count 0 2006.238.07:51:10.25#ibcon#about to read 3, iclass 31, count 0 2006.238.07:51:10.28#ibcon#read 3, iclass 31, count 0 2006.238.07:51:10.28#ibcon#about to read 4, iclass 31, count 0 2006.238.07:51:10.28#ibcon#read 4, iclass 31, count 0 2006.238.07:51:10.28#ibcon#about to read 5, iclass 31, count 0 2006.238.07:51:10.28#ibcon#read 5, iclass 31, count 0 2006.238.07:51:10.28#ibcon#about to read 6, iclass 31, count 0 2006.238.07:51:10.28#ibcon#read 6, iclass 31, count 0 2006.238.07:51:10.28#ibcon#end of sib2, iclass 31, count 0 2006.238.07:51:10.28#ibcon#*after write, iclass 31, count 0 2006.238.07:51:10.28#ibcon#*before return 0, iclass 31, count 0 2006.238.07:51:10.28#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:51:10.28#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.238.07:51:10.28#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:51:10.28#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:51:10.28$vc4f8/valo=8,852.99 2006.238.07:51:10.28#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.07:51:10.28#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.07:51:10.28#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:10.28#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:51:10.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:51:10.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:51:10.28#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:51:10.28#ibcon#first serial, iclass 33, count 0 2006.238.07:51:10.28#ibcon#enter sib2, iclass 33, count 0 2006.238.07:51:10.28#ibcon#flushed, iclass 33, count 0 2006.238.07:51:10.28#ibcon#about to write, iclass 33, count 0 2006.238.07:51:10.28#ibcon#wrote, iclass 33, count 0 2006.238.07:51:10.28#ibcon#about to read 3, iclass 33, count 0 2006.238.07:51:10.30#ibcon#read 3, iclass 33, count 0 2006.238.07:51:10.30#ibcon#about to read 4, iclass 33, count 0 2006.238.07:51:10.30#ibcon#read 4, iclass 33, count 0 2006.238.07:51:10.30#ibcon#about to read 5, iclass 33, count 0 2006.238.07:51:10.30#ibcon#read 5, iclass 33, count 0 2006.238.07:51:10.30#ibcon#about to read 6, iclass 33, count 0 2006.238.07:51:10.30#ibcon#read 6, iclass 33, count 0 2006.238.07:51:10.30#ibcon#end of sib2, iclass 33, count 0 2006.238.07:51:10.30#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:51:10.30#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:51:10.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:51:10.30#ibcon#*before write, iclass 33, count 0 2006.238.07:51:10.30#ibcon#enter sib2, iclass 33, count 0 2006.238.07:51:10.30#ibcon#flushed, iclass 33, count 0 2006.238.07:51:10.30#ibcon#about to write, iclass 33, count 0 2006.238.07:51:10.30#ibcon#wrote, iclass 33, count 0 2006.238.07:51:10.30#ibcon#about to read 3, iclass 33, count 0 2006.238.07:51:10.34#ibcon#read 3, iclass 33, count 0 2006.238.07:51:10.34#ibcon#about to read 4, iclass 33, count 0 2006.238.07:51:10.34#ibcon#read 4, iclass 33, count 0 2006.238.07:51:10.34#ibcon#about to read 5, iclass 33, count 0 2006.238.07:51:10.34#ibcon#read 5, iclass 33, count 0 2006.238.07:51:10.34#ibcon#about to read 6, iclass 33, count 0 2006.238.07:51:10.34#ibcon#read 6, iclass 33, count 0 2006.238.07:51:10.34#ibcon#end of sib2, iclass 33, count 0 2006.238.07:51:10.34#ibcon#*after write, iclass 33, count 0 2006.238.07:51:10.34#ibcon#*before return 0, iclass 33, count 0 2006.238.07:51:10.34#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:51:10.34#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.07:51:10.34#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:51:10.34#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:51:10.34$vc4f8/va=8,7 2006.238.07:51:10.34#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.238.07:51:10.34#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.238.07:51:10.34#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:10.34#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:51:10.40#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:51:10.40#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:51:10.40#ibcon#enter wrdev, iclass 35, count 2 2006.238.07:51:10.40#ibcon#first serial, iclass 35, count 2 2006.238.07:51:10.40#ibcon#enter sib2, iclass 35, count 2 2006.238.07:51:10.40#ibcon#flushed, iclass 35, count 2 2006.238.07:51:10.40#ibcon#about to write, iclass 35, count 2 2006.238.07:51:10.40#ibcon#wrote, iclass 35, count 2 2006.238.07:51:10.40#ibcon#about to read 3, iclass 35, count 2 2006.238.07:51:10.42#ibcon#read 3, iclass 35, count 2 2006.238.07:51:10.42#ibcon#about to read 4, iclass 35, count 2 2006.238.07:51:10.42#ibcon#read 4, iclass 35, count 2 2006.238.07:51:10.42#ibcon#about to read 5, iclass 35, count 2 2006.238.07:51:10.42#ibcon#read 5, iclass 35, count 2 2006.238.07:51:10.42#ibcon#about to read 6, iclass 35, count 2 2006.238.07:51:10.42#ibcon#read 6, iclass 35, count 2 2006.238.07:51:10.42#ibcon#end of sib2, iclass 35, count 2 2006.238.07:51:10.42#ibcon#*mode == 0, iclass 35, count 2 2006.238.07:51:10.42#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.238.07:51:10.42#ibcon#[25=AT08-07\r\n] 2006.238.07:51:10.42#ibcon#*before write, iclass 35, count 2 2006.238.07:51:10.42#ibcon#enter sib2, iclass 35, count 2 2006.238.07:51:10.42#ibcon#flushed, iclass 35, count 2 2006.238.07:51:10.42#ibcon#about to write, iclass 35, count 2 2006.238.07:51:10.42#ibcon#wrote, iclass 35, count 2 2006.238.07:51:10.42#ibcon#about to read 3, iclass 35, count 2 2006.238.07:51:10.45#ibcon#read 3, iclass 35, count 2 2006.238.07:51:10.45#ibcon#about to read 4, iclass 35, count 2 2006.238.07:51:10.45#ibcon#read 4, iclass 35, count 2 2006.238.07:51:10.45#ibcon#about to read 5, iclass 35, count 2 2006.238.07:51:10.45#ibcon#read 5, iclass 35, count 2 2006.238.07:51:10.45#ibcon#about to read 6, iclass 35, count 2 2006.238.07:51:10.45#ibcon#read 6, iclass 35, count 2 2006.238.07:51:10.45#ibcon#end of sib2, iclass 35, count 2 2006.238.07:51:10.45#ibcon#*after write, iclass 35, count 2 2006.238.07:51:10.45#ibcon#*before return 0, iclass 35, count 2 2006.238.07:51:10.45#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:51:10.45#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.238.07:51:10.45#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.238.07:51:10.45#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:10.45#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:51:10.57#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:51:10.57#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:51:10.57#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:51:10.57#ibcon#first serial, iclass 35, count 0 2006.238.07:51:10.57#ibcon#enter sib2, iclass 35, count 0 2006.238.07:51:10.57#ibcon#flushed, iclass 35, count 0 2006.238.07:51:10.57#ibcon#about to write, iclass 35, count 0 2006.238.07:51:10.57#ibcon#wrote, iclass 35, count 0 2006.238.07:51:10.57#ibcon#about to read 3, iclass 35, count 0 2006.238.07:51:10.59#ibcon#read 3, iclass 35, count 0 2006.238.07:51:10.59#ibcon#about to read 4, iclass 35, count 0 2006.238.07:51:10.59#ibcon#read 4, iclass 35, count 0 2006.238.07:51:10.59#ibcon#about to read 5, iclass 35, count 0 2006.238.07:51:10.59#ibcon#read 5, iclass 35, count 0 2006.238.07:51:10.59#ibcon#about to read 6, iclass 35, count 0 2006.238.07:51:10.59#ibcon#read 6, iclass 35, count 0 2006.238.07:51:10.59#ibcon#end of sib2, iclass 35, count 0 2006.238.07:51:10.59#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:51:10.59#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:51:10.59#ibcon#[25=USB\r\n] 2006.238.07:51:10.59#ibcon#*before write, iclass 35, count 0 2006.238.07:51:10.59#ibcon#enter sib2, iclass 35, count 0 2006.238.07:51:10.59#ibcon#flushed, iclass 35, count 0 2006.238.07:51:10.59#ibcon#about to write, iclass 35, count 0 2006.238.07:51:10.59#ibcon#wrote, iclass 35, count 0 2006.238.07:51:10.59#ibcon#about to read 3, iclass 35, count 0 2006.238.07:51:10.62#ibcon#read 3, iclass 35, count 0 2006.238.07:51:10.62#ibcon#about to read 4, iclass 35, count 0 2006.238.07:51:10.62#ibcon#read 4, iclass 35, count 0 2006.238.07:51:10.62#ibcon#about to read 5, iclass 35, count 0 2006.238.07:51:10.62#ibcon#read 5, iclass 35, count 0 2006.238.07:51:10.62#ibcon#about to read 6, iclass 35, count 0 2006.238.07:51:10.62#ibcon#read 6, iclass 35, count 0 2006.238.07:51:10.62#ibcon#end of sib2, iclass 35, count 0 2006.238.07:51:10.62#ibcon#*after write, iclass 35, count 0 2006.238.07:51:10.62#ibcon#*before return 0, iclass 35, count 0 2006.238.07:51:10.62#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:51:10.62#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.238.07:51:10.62#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:51:10.62#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:51:10.62$vc4f8/vblo=1,632.99 2006.238.07:51:10.62#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.07:51:10.62#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.07:51:10.62#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:10.62#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:51:10.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:51:10.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:51:10.62#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:51:10.62#ibcon#first serial, iclass 37, count 0 2006.238.07:51:10.62#ibcon#enter sib2, iclass 37, count 0 2006.238.07:51:10.62#ibcon#flushed, iclass 37, count 0 2006.238.07:51:10.62#ibcon#about to write, iclass 37, count 0 2006.238.07:51:10.62#ibcon#wrote, iclass 37, count 0 2006.238.07:51:10.62#ibcon#about to read 3, iclass 37, count 0 2006.238.07:51:10.64#ibcon#read 3, iclass 37, count 0 2006.238.07:51:10.64#ibcon#about to read 4, iclass 37, count 0 2006.238.07:51:10.64#ibcon#read 4, iclass 37, count 0 2006.238.07:51:10.64#ibcon#about to read 5, iclass 37, count 0 2006.238.07:51:10.64#ibcon#read 5, iclass 37, count 0 2006.238.07:51:10.64#ibcon#about to read 6, iclass 37, count 0 2006.238.07:51:10.64#ibcon#read 6, iclass 37, count 0 2006.238.07:51:10.64#ibcon#end of sib2, iclass 37, count 0 2006.238.07:51:10.64#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:51:10.64#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:51:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:51:10.64#ibcon#*before write, iclass 37, count 0 2006.238.07:51:10.64#ibcon#enter sib2, iclass 37, count 0 2006.238.07:51:10.64#ibcon#flushed, iclass 37, count 0 2006.238.07:51:10.64#ibcon#about to write, iclass 37, count 0 2006.238.07:51:10.64#ibcon#wrote, iclass 37, count 0 2006.238.07:51:10.64#ibcon#about to read 3, iclass 37, count 0 2006.238.07:51:10.68#ibcon#read 3, iclass 37, count 0 2006.238.07:51:10.68#ibcon#about to read 4, iclass 37, count 0 2006.238.07:51:10.68#ibcon#read 4, iclass 37, count 0 2006.238.07:51:10.68#ibcon#about to read 5, iclass 37, count 0 2006.238.07:51:10.68#ibcon#read 5, iclass 37, count 0 2006.238.07:51:10.68#ibcon#about to read 6, iclass 37, count 0 2006.238.07:51:10.68#ibcon#read 6, iclass 37, count 0 2006.238.07:51:10.68#ibcon#end of sib2, iclass 37, count 0 2006.238.07:51:10.68#ibcon#*after write, iclass 37, count 0 2006.238.07:51:10.68#ibcon#*before return 0, iclass 37, count 0 2006.238.07:51:10.68#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:51:10.68#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.07:51:10.68#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:51:10.68#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:51:10.68$vc4f8/vb=1,4 2006.238.07:51:10.68#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.238.07:51:10.68#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.238.07:51:10.68#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:10.68#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:51:10.68#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:51:10.68#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:51:10.68#ibcon#enter wrdev, iclass 39, count 2 2006.238.07:51:10.68#ibcon#first serial, iclass 39, count 2 2006.238.07:51:10.68#ibcon#enter sib2, iclass 39, count 2 2006.238.07:51:10.68#ibcon#flushed, iclass 39, count 2 2006.238.07:51:10.68#ibcon#about to write, iclass 39, count 2 2006.238.07:51:10.68#ibcon#wrote, iclass 39, count 2 2006.238.07:51:10.68#ibcon#about to read 3, iclass 39, count 2 2006.238.07:51:10.70#ibcon#read 3, iclass 39, count 2 2006.238.07:51:10.70#ibcon#about to read 4, iclass 39, count 2 2006.238.07:51:10.70#ibcon#read 4, iclass 39, count 2 2006.238.07:51:10.70#ibcon#about to read 5, iclass 39, count 2 2006.238.07:51:10.70#ibcon#read 5, iclass 39, count 2 2006.238.07:51:10.70#ibcon#about to read 6, iclass 39, count 2 2006.238.07:51:10.70#ibcon#read 6, iclass 39, count 2 2006.238.07:51:10.70#ibcon#end of sib2, iclass 39, count 2 2006.238.07:51:10.70#ibcon#*mode == 0, iclass 39, count 2 2006.238.07:51:10.70#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.238.07:51:10.70#ibcon#[27=AT01-04\r\n] 2006.238.07:51:10.70#ibcon#*before write, iclass 39, count 2 2006.238.07:51:10.70#ibcon#enter sib2, iclass 39, count 2 2006.238.07:51:10.70#ibcon#flushed, iclass 39, count 2 2006.238.07:51:10.70#ibcon#about to write, iclass 39, count 2 2006.238.07:51:10.70#ibcon#wrote, iclass 39, count 2 2006.238.07:51:10.70#ibcon#about to read 3, iclass 39, count 2 2006.238.07:51:10.73#ibcon#read 3, iclass 39, count 2 2006.238.07:51:10.73#ibcon#about to read 4, iclass 39, count 2 2006.238.07:51:10.73#ibcon#read 4, iclass 39, count 2 2006.238.07:51:10.73#ibcon#about to read 5, iclass 39, count 2 2006.238.07:51:10.73#ibcon#read 5, iclass 39, count 2 2006.238.07:51:10.73#ibcon#about to read 6, iclass 39, count 2 2006.238.07:51:10.73#ibcon#read 6, iclass 39, count 2 2006.238.07:51:10.73#ibcon#end of sib2, iclass 39, count 2 2006.238.07:51:10.73#ibcon#*after write, iclass 39, count 2 2006.238.07:51:10.73#ibcon#*before return 0, iclass 39, count 2 2006.238.07:51:10.73#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:51:10.73#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.238.07:51:10.73#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.238.07:51:10.73#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:10.73#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:51:10.85#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:51:10.85#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:51:10.85#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:51:10.85#ibcon#first serial, iclass 39, count 0 2006.238.07:51:10.85#ibcon#enter sib2, iclass 39, count 0 2006.238.07:51:10.85#ibcon#flushed, iclass 39, count 0 2006.238.07:51:10.85#ibcon#about to write, iclass 39, count 0 2006.238.07:51:10.85#ibcon#wrote, iclass 39, count 0 2006.238.07:51:10.85#ibcon#about to read 3, iclass 39, count 0 2006.238.07:51:10.87#ibcon#read 3, iclass 39, count 0 2006.238.07:51:10.87#ibcon#about to read 4, iclass 39, count 0 2006.238.07:51:10.87#ibcon#read 4, iclass 39, count 0 2006.238.07:51:10.87#ibcon#about to read 5, iclass 39, count 0 2006.238.07:51:10.87#ibcon#read 5, iclass 39, count 0 2006.238.07:51:10.87#ibcon#about to read 6, iclass 39, count 0 2006.238.07:51:10.87#ibcon#read 6, iclass 39, count 0 2006.238.07:51:10.87#ibcon#end of sib2, iclass 39, count 0 2006.238.07:51:10.87#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:51:10.87#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:51:10.87#ibcon#[27=USB\r\n] 2006.238.07:51:10.87#ibcon#*before write, iclass 39, count 0 2006.238.07:51:10.87#ibcon#enter sib2, iclass 39, count 0 2006.238.07:51:10.87#ibcon#flushed, iclass 39, count 0 2006.238.07:51:10.87#ibcon#about to write, iclass 39, count 0 2006.238.07:51:10.87#ibcon#wrote, iclass 39, count 0 2006.238.07:51:10.87#ibcon#about to read 3, iclass 39, count 0 2006.238.07:51:10.90#ibcon#read 3, iclass 39, count 0 2006.238.07:51:10.90#ibcon#about to read 4, iclass 39, count 0 2006.238.07:51:10.90#ibcon#read 4, iclass 39, count 0 2006.238.07:51:10.90#ibcon#about to read 5, iclass 39, count 0 2006.238.07:51:10.90#ibcon#read 5, iclass 39, count 0 2006.238.07:51:10.90#ibcon#about to read 6, iclass 39, count 0 2006.238.07:51:10.90#ibcon#read 6, iclass 39, count 0 2006.238.07:51:10.90#ibcon#end of sib2, iclass 39, count 0 2006.238.07:51:10.90#ibcon#*after write, iclass 39, count 0 2006.238.07:51:10.90#ibcon#*before return 0, iclass 39, count 0 2006.238.07:51:10.90#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:51:10.90#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.238.07:51:10.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:51:10.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:51:10.90$vc4f8/vblo=2,640.99 2006.238.07:51:10.90#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.07:51:10.90#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.07:51:10.90#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:10.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:51:10.90#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:51:10.90#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:51:10.90#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:51:10.90#ibcon#first serial, iclass 3, count 0 2006.238.07:51:10.90#ibcon#enter sib2, iclass 3, count 0 2006.238.07:51:10.90#ibcon#flushed, iclass 3, count 0 2006.238.07:51:10.90#ibcon#about to write, iclass 3, count 0 2006.238.07:51:10.90#ibcon#wrote, iclass 3, count 0 2006.238.07:51:10.90#ibcon#about to read 3, iclass 3, count 0 2006.238.07:51:10.92#ibcon#read 3, iclass 3, count 0 2006.238.07:51:10.92#ibcon#about to read 4, iclass 3, count 0 2006.238.07:51:10.92#ibcon#read 4, iclass 3, count 0 2006.238.07:51:10.92#ibcon#about to read 5, iclass 3, count 0 2006.238.07:51:10.92#ibcon#read 5, iclass 3, count 0 2006.238.07:51:10.92#ibcon#about to read 6, iclass 3, count 0 2006.238.07:51:10.92#ibcon#read 6, iclass 3, count 0 2006.238.07:51:10.92#ibcon#end of sib2, iclass 3, count 0 2006.238.07:51:10.92#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:51:10.92#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:51:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:51:10.92#ibcon#*before write, iclass 3, count 0 2006.238.07:51:10.92#ibcon#enter sib2, iclass 3, count 0 2006.238.07:51:10.92#ibcon#flushed, iclass 3, count 0 2006.238.07:51:10.92#ibcon#about to write, iclass 3, count 0 2006.238.07:51:10.92#ibcon#wrote, iclass 3, count 0 2006.238.07:51:10.92#ibcon#about to read 3, iclass 3, count 0 2006.238.07:51:10.96#ibcon#read 3, iclass 3, count 0 2006.238.07:51:10.96#ibcon#about to read 4, iclass 3, count 0 2006.238.07:51:10.96#ibcon#read 4, iclass 3, count 0 2006.238.07:51:10.96#ibcon#about to read 5, iclass 3, count 0 2006.238.07:51:10.96#ibcon#read 5, iclass 3, count 0 2006.238.07:51:10.96#ibcon#about to read 6, iclass 3, count 0 2006.238.07:51:10.96#ibcon#read 6, iclass 3, count 0 2006.238.07:51:10.96#ibcon#end of sib2, iclass 3, count 0 2006.238.07:51:10.96#ibcon#*after write, iclass 3, count 0 2006.238.07:51:10.96#ibcon#*before return 0, iclass 3, count 0 2006.238.07:51:10.96#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:51:10.96#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:51:10.96#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:51:10.96#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:51:10.96$vc4f8/vb=2,4 2006.238.07:51:10.96#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.238.07:51:10.96#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.238.07:51:10.96#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:10.96#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:51:11.02#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:51:11.02#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:51:11.02#ibcon#enter wrdev, iclass 5, count 2 2006.238.07:51:11.02#ibcon#first serial, iclass 5, count 2 2006.238.07:51:11.02#ibcon#enter sib2, iclass 5, count 2 2006.238.07:51:11.02#ibcon#flushed, iclass 5, count 2 2006.238.07:51:11.02#ibcon#about to write, iclass 5, count 2 2006.238.07:51:11.02#ibcon#wrote, iclass 5, count 2 2006.238.07:51:11.02#ibcon#about to read 3, iclass 5, count 2 2006.238.07:51:11.04#ibcon#read 3, iclass 5, count 2 2006.238.07:51:11.04#ibcon#about to read 4, iclass 5, count 2 2006.238.07:51:11.04#ibcon#read 4, iclass 5, count 2 2006.238.07:51:11.04#ibcon#about to read 5, iclass 5, count 2 2006.238.07:51:11.04#ibcon#read 5, iclass 5, count 2 2006.238.07:51:11.04#ibcon#about to read 6, iclass 5, count 2 2006.238.07:51:11.04#ibcon#read 6, iclass 5, count 2 2006.238.07:51:11.04#ibcon#end of sib2, iclass 5, count 2 2006.238.07:51:11.04#ibcon#*mode == 0, iclass 5, count 2 2006.238.07:51:11.04#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.238.07:51:11.04#ibcon#[27=AT02-04\r\n] 2006.238.07:51:11.04#ibcon#*before write, iclass 5, count 2 2006.238.07:51:11.04#ibcon#enter sib2, iclass 5, count 2 2006.238.07:51:11.04#ibcon#flushed, iclass 5, count 2 2006.238.07:51:11.04#ibcon#about to write, iclass 5, count 2 2006.238.07:51:11.04#ibcon#wrote, iclass 5, count 2 2006.238.07:51:11.04#ibcon#about to read 3, iclass 5, count 2 2006.238.07:51:11.07#ibcon#read 3, iclass 5, count 2 2006.238.07:51:11.07#ibcon#about to read 4, iclass 5, count 2 2006.238.07:51:11.07#ibcon#read 4, iclass 5, count 2 2006.238.07:51:11.07#ibcon#about to read 5, iclass 5, count 2 2006.238.07:51:11.07#ibcon#read 5, iclass 5, count 2 2006.238.07:51:11.07#ibcon#about to read 6, iclass 5, count 2 2006.238.07:51:11.07#ibcon#read 6, iclass 5, count 2 2006.238.07:51:11.07#ibcon#end of sib2, iclass 5, count 2 2006.238.07:51:11.07#ibcon#*after write, iclass 5, count 2 2006.238.07:51:11.07#ibcon#*before return 0, iclass 5, count 2 2006.238.07:51:11.07#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:51:11.07#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.238.07:51:11.07#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.238.07:51:11.07#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:11.07#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:51:11.19#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:51:11.19#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:51:11.19#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:51:11.19#ibcon#first serial, iclass 5, count 0 2006.238.07:51:11.19#ibcon#enter sib2, iclass 5, count 0 2006.238.07:51:11.19#ibcon#flushed, iclass 5, count 0 2006.238.07:51:11.19#ibcon#about to write, iclass 5, count 0 2006.238.07:51:11.19#ibcon#wrote, iclass 5, count 0 2006.238.07:51:11.19#ibcon#about to read 3, iclass 5, count 0 2006.238.07:51:11.21#ibcon#read 3, iclass 5, count 0 2006.238.07:51:11.21#ibcon#about to read 4, iclass 5, count 0 2006.238.07:51:11.21#ibcon#read 4, iclass 5, count 0 2006.238.07:51:11.21#ibcon#about to read 5, iclass 5, count 0 2006.238.07:51:11.21#ibcon#read 5, iclass 5, count 0 2006.238.07:51:11.21#ibcon#about to read 6, iclass 5, count 0 2006.238.07:51:11.21#ibcon#read 6, iclass 5, count 0 2006.238.07:51:11.21#ibcon#end of sib2, iclass 5, count 0 2006.238.07:51:11.21#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:51:11.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:51:11.21#ibcon#[27=USB\r\n] 2006.238.07:51:11.21#ibcon#*before write, iclass 5, count 0 2006.238.07:51:11.21#ibcon#enter sib2, iclass 5, count 0 2006.238.07:51:11.21#ibcon#flushed, iclass 5, count 0 2006.238.07:51:11.21#ibcon#about to write, iclass 5, count 0 2006.238.07:51:11.21#ibcon#wrote, iclass 5, count 0 2006.238.07:51:11.21#ibcon#about to read 3, iclass 5, count 0 2006.238.07:51:11.24#ibcon#read 3, iclass 5, count 0 2006.238.07:51:11.24#ibcon#about to read 4, iclass 5, count 0 2006.238.07:51:11.24#ibcon#read 4, iclass 5, count 0 2006.238.07:51:11.24#ibcon#about to read 5, iclass 5, count 0 2006.238.07:51:11.24#ibcon#read 5, iclass 5, count 0 2006.238.07:51:11.24#ibcon#about to read 6, iclass 5, count 0 2006.238.07:51:11.24#ibcon#read 6, iclass 5, count 0 2006.238.07:51:11.24#ibcon#end of sib2, iclass 5, count 0 2006.238.07:51:11.24#ibcon#*after write, iclass 5, count 0 2006.238.07:51:11.24#ibcon#*before return 0, iclass 5, count 0 2006.238.07:51:11.24#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:51:11.24#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.238.07:51:11.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:51:11.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:51:11.24$vc4f8/vblo=3,656.99 2006.238.07:51:11.24#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.238.07:51:11.24#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.238.07:51:11.24#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:11.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:51:11.24#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:51:11.24#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:51:11.24#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:51:11.24#ibcon#first serial, iclass 7, count 0 2006.238.07:51:11.24#ibcon#enter sib2, iclass 7, count 0 2006.238.07:51:11.24#ibcon#flushed, iclass 7, count 0 2006.238.07:51:11.24#ibcon#about to write, iclass 7, count 0 2006.238.07:51:11.24#ibcon#wrote, iclass 7, count 0 2006.238.07:51:11.24#ibcon#about to read 3, iclass 7, count 0 2006.238.07:51:11.26#ibcon#read 3, iclass 7, count 0 2006.238.07:51:11.26#ibcon#about to read 4, iclass 7, count 0 2006.238.07:51:11.26#ibcon#read 4, iclass 7, count 0 2006.238.07:51:11.26#ibcon#about to read 5, iclass 7, count 0 2006.238.07:51:11.26#ibcon#read 5, iclass 7, count 0 2006.238.07:51:11.26#ibcon#about to read 6, iclass 7, count 0 2006.238.07:51:11.26#ibcon#read 6, iclass 7, count 0 2006.238.07:51:11.26#ibcon#end of sib2, iclass 7, count 0 2006.238.07:51:11.26#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:51:11.26#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:51:11.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:51:11.26#ibcon#*before write, iclass 7, count 0 2006.238.07:51:11.26#ibcon#enter sib2, iclass 7, count 0 2006.238.07:51:11.26#ibcon#flushed, iclass 7, count 0 2006.238.07:51:11.26#ibcon#about to write, iclass 7, count 0 2006.238.07:51:11.26#ibcon#wrote, iclass 7, count 0 2006.238.07:51:11.26#ibcon#about to read 3, iclass 7, count 0 2006.238.07:51:11.30#ibcon#read 3, iclass 7, count 0 2006.238.07:51:11.30#ibcon#about to read 4, iclass 7, count 0 2006.238.07:51:11.30#ibcon#read 4, iclass 7, count 0 2006.238.07:51:11.30#ibcon#about to read 5, iclass 7, count 0 2006.238.07:51:11.30#ibcon#read 5, iclass 7, count 0 2006.238.07:51:11.30#ibcon#about to read 6, iclass 7, count 0 2006.238.07:51:11.30#ibcon#read 6, iclass 7, count 0 2006.238.07:51:11.30#ibcon#end of sib2, iclass 7, count 0 2006.238.07:51:11.30#ibcon#*after write, iclass 7, count 0 2006.238.07:51:11.30#ibcon#*before return 0, iclass 7, count 0 2006.238.07:51:11.30#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:51:11.30#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.238.07:51:11.30#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:51:11.30#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:51:11.30$vc4f8/vb=3,4 2006.238.07:51:11.30#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.238.07:51:11.30#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.238.07:51:11.30#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:11.30#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:51:11.36#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:51:11.36#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:51:11.36#ibcon#enter wrdev, iclass 11, count 2 2006.238.07:51:11.36#ibcon#first serial, iclass 11, count 2 2006.238.07:51:11.36#ibcon#enter sib2, iclass 11, count 2 2006.238.07:51:11.36#ibcon#flushed, iclass 11, count 2 2006.238.07:51:11.36#ibcon#about to write, iclass 11, count 2 2006.238.07:51:11.36#ibcon#wrote, iclass 11, count 2 2006.238.07:51:11.36#ibcon#about to read 3, iclass 11, count 2 2006.238.07:51:11.38#ibcon#read 3, iclass 11, count 2 2006.238.07:51:11.38#ibcon#about to read 4, iclass 11, count 2 2006.238.07:51:11.38#ibcon#read 4, iclass 11, count 2 2006.238.07:51:11.38#ibcon#about to read 5, iclass 11, count 2 2006.238.07:51:11.38#ibcon#read 5, iclass 11, count 2 2006.238.07:51:11.38#ibcon#about to read 6, iclass 11, count 2 2006.238.07:51:11.38#ibcon#read 6, iclass 11, count 2 2006.238.07:51:11.38#ibcon#end of sib2, iclass 11, count 2 2006.238.07:51:11.38#ibcon#*mode == 0, iclass 11, count 2 2006.238.07:51:11.38#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.238.07:51:11.38#ibcon#[27=AT03-04\r\n] 2006.238.07:51:11.38#ibcon#*before write, iclass 11, count 2 2006.238.07:51:11.38#ibcon#enter sib2, iclass 11, count 2 2006.238.07:51:11.38#ibcon#flushed, iclass 11, count 2 2006.238.07:51:11.38#ibcon#about to write, iclass 11, count 2 2006.238.07:51:11.38#ibcon#wrote, iclass 11, count 2 2006.238.07:51:11.38#ibcon#about to read 3, iclass 11, count 2 2006.238.07:51:11.42#ibcon#read 3, iclass 11, count 2 2006.238.07:51:11.42#ibcon#about to read 4, iclass 11, count 2 2006.238.07:51:11.42#ibcon#read 4, iclass 11, count 2 2006.238.07:51:11.42#ibcon#about to read 5, iclass 11, count 2 2006.238.07:51:11.42#ibcon#read 5, iclass 11, count 2 2006.238.07:51:11.42#ibcon#about to read 6, iclass 11, count 2 2006.238.07:51:11.42#ibcon#read 6, iclass 11, count 2 2006.238.07:51:11.42#ibcon#end of sib2, iclass 11, count 2 2006.238.07:51:11.42#ibcon#*after write, iclass 11, count 2 2006.238.07:51:11.42#ibcon#*before return 0, iclass 11, count 2 2006.238.07:51:11.42#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:51:11.42#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.238.07:51:11.42#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.238.07:51:11.42#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:11.42#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:51:11.54#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:51:11.54#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:51:11.54#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:51:11.54#ibcon#first serial, iclass 11, count 0 2006.238.07:51:11.54#ibcon#enter sib2, iclass 11, count 0 2006.238.07:51:11.54#ibcon#flushed, iclass 11, count 0 2006.238.07:51:11.54#ibcon#about to write, iclass 11, count 0 2006.238.07:51:11.54#ibcon#wrote, iclass 11, count 0 2006.238.07:51:11.54#ibcon#about to read 3, iclass 11, count 0 2006.238.07:51:11.56#ibcon#read 3, iclass 11, count 0 2006.238.07:51:11.56#ibcon#about to read 4, iclass 11, count 0 2006.238.07:51:11.56#ibcon#read 4, iclass 11, count 0 2006.238.07:51:11.56#ibcon#about to read 5, iclass 11, count 0 2006.238.07:51:11.56#ibcon#read 5, iclass 11, count 0 2006.238.07:51:11.56#ibcon#about to read 6, iclass 11, count 0 2006.238.07:51:11.56#ibcon#read 6, iclass 11, count 0 2006.238.07:51:11.56#ibcon#end of sib2, iclass 11, count 0 2006.238.07:51:11.56#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:51:11.56#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:51:11.56#ibcon#[27=USB\r\n] 2006.238.07:51:11.56#ibcon#*before write, iclass 11, count 0 2006.238.07:51:11.56#ibcon#enter sib2, iclass 11, count 0 2006.238.07:51:11.56#ibcon#flushed, iclass 11, count 0 2006.238.07:51:11.56#ibcon#about to write, iclass 11, count 0 2006.238.07:51:11.56#ibcon#wrote, iclass 11, count 0 2006.238.07:51:11.56#ibcon#about to read 3, iclass 11, count 0 2006.238.07:51:11.59#ibcon#read 3, iclass 11, count 0 2006.238.07:51:11.59#ibcon#about to read 4, iclass 11, count 0 2006.238.07:51:11.59#ibcon#read 4, iclass 11, count 0 2006.238.07:51:11.59#ibcon#about to read 5, iclass 11, count 0 2006.238.07:51:11.59#ibcon#read 5, iclass 11, count 0 2006.238.07:51:11.59#ibcon#about to read 6, iclass 11, count 0 2006.238.07:51:11.59#ibcon#read 6, iclass 11, count 0 2006.238.07:51:11.59#ibcon#end of sib2, iclass 11, count 0 2006.238.07:51:11.59#ibcon#*after write, iclass 11, count 0 2006.238.07:51:11.59#ibcon#*before return 0, iclass 11, count 0 2006.238.07:51:11.59#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:51:11.59#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.238.07:51:11.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:51:11.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:51:11.59$vc4f8/vblo=4,712.99 2006.238.07:51:11.59#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.07:51:11.59#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.07:51:11.59#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:11.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:51:11.59#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:51:11.59#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:51:11.59#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:51:11.59#ibcon#first serial, iclass 13, count 0 2006.238.07:51:11.59#ibcon#enter sib2, iclass 13, count 0 2006.238.07:51:11.59#ibcon#flushed, iclass 13, count 0 2006.238.07:51:11.59#ibcon#about to write, iclass 13, count 0 2006.238.07:51:11.59#ibcon#wrote, iclass 13, count 0 2006.238.07:51:11.59#ibcon#about to read 3, iclass 13, count 0 2006.238.07:51:11.61#ibcon#read 3, iclass 13, count 0 2006.238.07:51:11.61#ibcon#about to read 4, iclass 13, count 0 2006.238.07:51:11.61#ibcon#read 4, iclass 13, count 0 2006.238.07:51:11.61#ibcon#about to read 5, iclass 13, count 0 2006.238.07:51:11.61#ibcon#read 5, iclass 13, count 0 2006.238.07:51:11.61#ibcon#about to read 6, iclass 13, count 0 2006.238.07:51:11.61#ibcon#read 6, iclass 13, count 0 2006.238.07:51:11.61#ibcon#end of sib2, iclass 13, count 0 2006.238.07:51:11.61#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:51:11.61#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:51:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:51:11.61#ibcon#*before write, iclass 13, count 0 2006.238.07:51:11.61#ibcon#enter sib2, iclass 13, count 0 2006.238.07:51:11.61#ibcon#flushed, iclass 13, count 0 2006.238.07:51:11.61#ibcon#about to write, iclass 13, count 0 2006.238.07:51:11.61#ibcon#wrote, iclass 13, count 0 2006.238.07:51:11.61#ibcon#about to read 3, iclass 13, count 0 2006.238.07:51:11.65#ibcon#read 3, iclass 13, count 0 2006.238.07:51:11.65#ibcon#about to read 4, iclass 13, count 0 2006.238.07:51:11.65#ibcon#read 4, iclass 13, count 0 2006.238.07:51:11.65#ibcon#about to read 5, iclass 13, count 0 2006.238.07:51:11.65#ibcon#read 5, iclass 13, count 0 2006.238.07:51:11.65#ibcon#about to read 6, iclass 13, count 0 2006.238.07:51:11.65#ibcon#read 6, iclass 13, count 0 2006.238.07:51:11.65#ibcon#end of sib2, iclass 13, count 0 2006.238.07:51:11.65#ibcon#*after write, iclass 13, count 0 2006.238.07:51:11.65#ibcon#*before return 0, iclass 13, count 0 2006.238.07:51:11.65#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:51:11.65#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:51:11.65#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:51:11.65#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:51:11.65$vc4f8/vb=4,4 2006.238.07:51:11.65#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.238.07:51:11.65#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.238.07:51:11.65#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:11.65#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:51:11.71#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:51:11.71#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:51:11.71#ibcon#enter wrdev, iclass 15, count 2 2006.238.07:51:11.71#ibcon#first serial, iclass 15, count 2 2006.238.07:51:11.71#ibcon#enter sib2, iclass 15, count 2 2006.238.07:51:11.71#ibcon#flushed, iclass 15, count 2 2006.238.07:51:11.71#ibcon#about to write, iclass 15, count 2 2006.238.07:51:11.71#ibcon#wrote, iclass 15, count 2 2006.238.07:51:11.71#ibcon#about to read 3, iclass 15, count 2 2006.238.07:51:11.73#ibcon#read 3, iclass 15, count 2 2006.238.07:51:11.73#ibcon#about to read 4, iclass 15, count 2 2006.238.07:51:11.73#ibcon#read 4, iclass 15, count 2 2006.238.07:51:11.73#ibcon#about to read 5, iclass 15, count 2 2006.238.07:51:11.73#ibcon#read 5, iclass 15, count 2 2006.238.07:51:11.73#ibcon#about to read 6, iclass 15, count 2 2006.238.07:51:11.73#ibcon#read 6, iclass 15, count 2 2006.238.07:51:11.73#ibcon#end of sib2, iclass 15, count 2 2006.238.07:51:11.73#ibcon#*mode == 0, iclass 15, count 2 2006.238.07:51:11.73#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.238.07:51:11.73#ibcon#[27=AT04-04\r\n] 2006.238.07:51:11.73#ibcon#*before write, iclass 15, count 2 2006.238.07:51:11.73#ibcon#enter sib2, iclass 15, count 2 2006.238.07:51:11.73#ibcon#flushed, iclass 15, count 2 2006.238.07:51:11.73#ibcon#about to write, iclass 15, count 2 2006.238.07:51:11.73#ibcon#wrote, iclass 15, count 2 2006.238.07:51:11.73#ibcon#about to read 3, iclass 15, count 2 2006.238.07:51:11.76#ibcon#read 3, iclass 15, count 2 2006.238.07:51:11.76#ibcon#about to read 4, iclass 15, count 2 2006.238.07:51:11.76#ibcon#read 4, iclass 15, count 2 2006.238.07:51:11.76#ibcon#about to read 5, iclass 15, count 2 2006.238.07:51:11.76#ibcon#read 5, iclass 15, count 2 2006.238.07:51:11.76#ibcon#about to read 6, iclass 15, count 2 2006.238.07:51:11.76#ibcon#read 6, iclass 15, count 2 2006.238.07:51:11.76#ibcon#end of sib2, iclass 15, count 2 2006.238.07:51:11.76#ibcon#*after write, iclass 15, count 2 2006.238.07:51:11.76#ibcon#*before return 0, iclass 15, count 2 2006.238.07:51:11.76#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:51:11.76#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.238.07:51:11.76#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.238.07:51:11.76#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:11.76#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:51:11.88#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:51:11.88#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:51:11.88#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:51:11.88#ibcon#first serial, iclass 15, count 0 2006.238.07:51:11.88#ibcon#enter sib2, iclass 15, count 0 2006.238.07:51:11.88#ibcon#flushed, iclass 15, count 0 2006.238.07:51:11.88#ibcon#about to write, iclass 15, count 0 2006.238.07:51:11.88#ibcon#wrote, iclass 15, count 0 2006.238.07:51:11.88#ibcon#about to read 3, iclass 15, count 0 2006.238.07:51:11.90#ibcon#read 3, iclass 15, count 0 2006.238.07:51:11.90#ibcon#about to read 4, iclass 15, count 0 2006.238.07:51:11.90#ibcon#read 4, iclass 15, count 0 2006.238.07:51:11.90#ibcon#about to read 5, iclass 15, count 0 2006.238.07:51:11.90#ibcon#read 5, iclass 15, count 0 2006.238.07:51:11.90#ibcon#about to read 6, iclass 15, count 0 2006.238.07:51:11.90#ibcon#read 6, iclass 15, count 0 2006.238.07:51:11.90#ibcon#end of sib2, iclass 15, count 0 2006.238.07:51:11.90#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:51:11.90#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:51:11.90#ibcon#[27=USB\r\n] 2006.238.07:51:11.90#ibcon#*before write, iclass 15, count 0 2006.238.07:51:11.90#ibcon#enter sib2, iclass 15, count 0 2006.238.07:51:11.90#ibcon#flushed, iclass 15, count 0 2006.238.07:51:11.90#ibcon#about to write, iclass 15, count 0 2006.238.07:51:11.90#ibcon#wrote, iclass 15, count 0 2006.238.07:51:11.90#ibcon#about to read 3, iclass 15, count 0 2006.238.07:51:11.93#ibcon#read 3, iclass 15, count 0 2006.238.07:51:11.93#ibcon#about to read 4, iclass 15, count 0 2006.238.07:51:11.93#ibcon#read 4, iclass 15, count 0 2006.238.07:51:11.93#ibcon#about to read 5, iclass 15, count 0 2006.238.07:51:11.93#ibcon#read 5, iclass 15, count 0 2006.238.07:51:11.93#ibcon#about to read 6, iclass 15, count 0 2006.238.07:51:11.93#ibcon#read 6, iclass 15, count 0 2006.238.07:51:11.93#ibcon#end of sib2, iclass 15, count 0 2006.238.07:51:11.93#ibcon#*after write, iclass 15, count 0 2006.238.07:51:11.93#ibcon#*before return 0, iclass 15, count 0 2006.238.07:51:11.93#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:51:11.93#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.238.07:51:11.93#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:51:11.93#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:51:11.93$vc4f8/vblo=5,744.99 2006.238.07:51:11.93#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.07:51:11.93#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.07:51:11.93#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:11.93#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:51:11.93#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:51:11.93#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:51:11.93#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:51:11.93#ibcon#first serial, iclass 17, count 0 2006.238.07:51:11.93#ibcon#enter sib2, iclass 17, count 0 2006.238.07:51:11.93#ibcon#flushed, iclass 17, count 0 2006.238.07:51:11.93#ibcon#about to write, iclass 17, count 0 2006.238.07:51:11.93#ibcon#wrote, iclass 17, count 0 2006.238.07:51:11.93#ibcon#about to read 3, iclass 17, count 0 2006.238.07:51:11.95#ibcon#read 3, iclass 17, count 0 2006.238.07:51:11.95#ibcon#about to read 4, iclass 17, count 0 2006.238.07:51:11.95#ibcon#read 4, iclass 17, count 0 2006.238.07:51:11.95#ibcon#about to read 5, iclass 17, count 0 2006.238.07:51:11.95#ibcon#read 5, iclass 17, count 0 2006.238.07:51:11.95#ibcon#about to read 6, iclass 17, count 0 2006.238.07:51:11.95#ibcon#read 6, iclass 17, count 0 2006.238.07:51:11.95#ibcon#end of sib2, iclass 17, count 0 2006.238.07:51:11.95#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:51:11.95#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:51:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:51:11.95#ibcon#*before write, iclass 17, count 0 2006.238.07:51:11.95#ibcon#enter sib2, iclass 17, count 0 2006.238.07:51:11.95#ibcon#flushed, iclass 17, count 0 2006.238.07:51:11.95#ibcon#about to write, iclass 17, count 0 2006.238.07:51:11.95#ibcon#wrote, iclass 17, count 0 2006.238.07:51:11.95#ibcon#about to read 3, iclass 17, count 0 2006.238.07:51:11.99#ibcon#read 3, iclass 17, count 0 2006.238.07:51:11.99#ibcon#about to read 4, iclass 17, count 0 2006.238.07:51:11.99#ibcon#read 4, iclass 17, count 0 2006.238.07:51:11.99#ibcon#about to read 5, iclass 17, count 0 2006.238.07:51:11.99#ibcon#read 5, iclass 17, count 0 2006.238.07:51:11.99#ibcon#about to read 6, iclass 17, count 0 2006.238.07:51:11.99#ibcon#read 6, iclass 17, count 0 2006.238.07:51:11.99#ibcon#end of sib2, iclass 17, count 0 2006.238.07:51:11.99#ibcon#*after write, iclass 17, count 0 2006.238.07:51:11.99#ibcon#*before return 0, iclass 17, count 0 2006.238.07:51:11.99#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:51:11.99#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.07:51:11.99#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:51:11.99#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:51:11.99$vc4f8/vb=5,4 2006.238.07:51:11.99#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.238.07:51:11.99#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.238.07:51:11.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:11.99#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:51:12.05#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:51:12.05#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:51:12.05#ibcon#enter wrdev, iclass 19, count 2 2006.238.07:51:12.05#ibcon#first serial, iclass 19, count 2 2006.238.07:51:12.05#ibcon#enter sib2, iclass 19, count 2 2006.238.07:51:12.05#ibcon#flushed, iclass 19, count 2 2006.238.07:51:12.05#ibcon#about to write, iclass 19, count 2 2006.238.07:51:12.05#ibcon#wrote, iclass 19, count 2 2006.238.07:51:12.05#ibcon#about to read 3, iclass 19, count 2 2006.238.07:51:12.07#ibcon#read 3, iclass 19, count 2 2006.238.07:51:12.07#ibcon#about to read 4, iclass 19, count 2 2006.238.07:51:12.07#ibcon#read 4, iclass 19, count 2 2006.238.07:51:12.07#ibcon#about to read 5, iclass 19, count 2 2006.238.07:51:12.07#ibcon#read 5, iclass 19, count 2 2006.238.07:51:12.07#ibcon#about to read 6, iclass 19, count 2 2006.238.07:51:12.07#ibcon#read 6, iclass 19, count 2 2006.238.07:51:12.07#ibcon#end of sib2, iclass 19, count 2 2006.238.07:51:12.07#ibcon#*mode == 0, iclass 19, count 2 2006.238.07:51:12.07#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.238.07:51:12.07#ibcon#[27=AT05-04\r\n] 2006.238.07:51:12.07#ibcon#*before write, iclass 19, count 2 2006.238.07:51:12.07#ibcon#enter sib2, iclass 19, count 2 2006.238.07:51:12.07#ibcon#flushed, iclass 19, count 2 2006.238.07:51:12.07#ibcon#about to write, iclass 19, count 2 2006.238.07:51:12.07#ibcon#wrote, iclass 19, count 2 2006.238.07:51:12.07#ibcon#about to read 3, iclass 19, count 2 2006.238.07:51:12.10#ibcon#read 3, iclass 19, count 2 2006.238.07:51:12.10#ibcon#about to read 4, iclass 19, count 2 2006.238.07:51:12.10#ibcon#read 4, iclass 19, count 2 2006.238.07:51:12.10#ibcon#about to read 5, iclass 19, count 2 2006.238.07:51:12.10#ibcon#read 5, iclass 19, count 2 2006.238.07:51:12.10#ibcon#about to read 6, iclass 19, count 2 2006.238.07:51:12.10#ibcon#read 6, iclass 19, count 2 2006.238.07:51:12.10#ibcon#end of sib2, iclass 19, count 2 2006.238.07:51:12.10#ibcon#*after write, iclass 19, count 2 2006.238.07:51:12.10#ibcon#*before return 0, iclass 19, count 2 2006.238.07:51:12.10#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:51:12.10#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.238.07:51:12.10#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.238.07:51:12.10#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:12.10#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:51:12.22#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:51:12.22#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:51:12.22#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:51:12.22#ibcon#first serial, iclass 19, count 0 2006.238.07:51:12.22#ibcon#enter sib2, iclass 19, count 0 2006.238.07:51:12.22#ibcon#flushed, iclass 19, count 0 2006.238.07:51:12.22#ibcon#about to write, iclass 19, count 0 2006.238.07:51:12.22#ibcon#wrote, iclass 19, count 0 2006.238.07:51:12.22#ibcon#about to read 3, iclass 19, count 0 2006.238.07:51:12.24#ibcon#read 3, iclass 19, count 0 2006.238.07:51:12.24#ibcon#about to read 4, iclass 19, count 0 2006.238.07:51:12.24#ibcon#read 4, iclass 19, count 0 2006.238.07:51:12.24#ibcon#about to read 5, iclass 19, count 0 2006.238.07:51:12.24#ibcon#read 5, iclass 19, count 0 2006.238.07:51:12.24#ibcon#about to read 6, iclass 19, count 0 2006.238.07:51:12.24#ibcon#read 6, iclass 19, count 0 2006.238.07:51:12.24#ibcon#end of sib2, iclass 19, count 0 2006.238.07:51:12.24#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:51:12.24#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:51:12.24#ibcon#[27=USB\r\n] 2006.238.07:51:12.24#ibcon#*before write, iclass 19, count 0 2006.238.07:51:12.24#ibcon#enter sib2, iclass 19, count 0 2006.238.07:51:12.24#ibcon#flushed, iclass 19, count 0 2006.238.07:51:12.24#ibcon#about to write, iclass 19, count 0 2006.238.07:51:12.24#ibcon#wrote, iclass 19, count 0 2006.238.07:51:12.24#ibcon#about to read 3, iclass 19, count 0 2006.238.07:51:12.27#ibcon#read 3, iclass 19, count 0 2006.238.07:51:12.27#ibcon#about to read 4, iclass 19, count 0 2006.238.07:51:12.27#ibcon#read 4, iclass 19, count 0 2006.238.07:51:12.27#ibcon#about to read 5, iclass 19, count 0 2006.238.07:51:12.27#ibcon#read 5, iclass 19, count 0 2006.238.07:51:12.27#ibcon#about to read 6, iclass 19, count 0 2006.238.07:51:12.27#ibcon#read 6, iclass 19, count 0 2006.238.07:51:12.27#ibcon#end of sib2, iclass 19, count 0 2006.238.07:51:12.27#ibcon#*after write, iclass 19, count 0 2006.238.07:51:12.27#ibcon#*before return 0, iclass 19, count 0 2006.238.07:51:12.27#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:51:12.27#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.238.07:51:12.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:51:12.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:51:12.27$vc4f8/vblo=6,752.99 2006.238.07:51:12.27#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.07:51:12.27#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.07:51:12.27#ibcon#ireg 17 cls_cnt 0 2006.238.07:51:12.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:51:12.27#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:51:12.27#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:51:12.27#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:51:12.27#ibcon#first serial, iclass 21, count 0 2006.238.07:51:12.27#ibcon#enter sib2, iclass 21, count 0 2006.238.07:51:12.27#ibcon#flushed, iclass 21, count 0 2006.238.07:51:12.27#ibcon#about to write, iclass 21, count 0 2006.238.07:51:12.27#ibcon#wrote, iclass 21, count 0 2006.238.07:51:12.27#ibcon#about to read 3, iclass 21, count 0 2006.238.07:51:12.29#ibcon#read 3, iclass 21, count 0 2006.238.07:51:12.29#ibcon#about to read 4, iclass 21, count 0 2006.238.07:51:12.29#ibcon#read 4, iclass 21, count 0 2006.238.07:51:12.29#ibcon#about to read 5, iclass 21, count 0 2006.238.07:51:12.29#ibcon#read 5, iclass 21, count 0 2006.238.07:51:12.29#ibcon#about to read 6, iclass 21, count 0 2006.238.07:51:12.29#ibcon#read 6, iclass 21, count 0 2006.238.07:51:12.29#ibcon#end of sib2, iclass 21, count 0 2006.238.07:51:12.29#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:51:12.29#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:51:12.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:51:12.29#ibcon#*before write, iclass 21, count 0 2006.238.07:51:12.29#ibcon#enter sib2, iclass 21, count 0 2006.238.07:51:12.29#ibcon#flushed, iclass 21, count 0 2006.238.07:51:12.29#ibcon#about to write, iclass 21, count 0 2006.238.07:51:12.29#ibcon#wrote, iclass 21, count 0 2006.238.07:51:12.29#ibcon#about to read 3, iclass 21, count 0 2006.238.07:51:12.33#ibcon#read 3, iclass 21, count 0 2006.238.07:51:12.33#ibcon#about to read 4, iclass 21, count 0 2006.238.07:51:12.33#ibcon#read 4, iclass 21, count 0 2006.238.07:51:12.33#ibcon#about to read 5, iclass 21, count 0 2006.238.07:51:12.33#ibcon#read 5, iclass 21, count 0 2006.238.07:51:12.33#ibcon#about to read 6, iclass 21, count 0 2006.238.07:51:12.33#ibcon#read 6, iclass 21, count 0 2006.238.07:51:12.33#ibcon#end of sib2, iclass 21, count 0 2006.238.07:51:12.33#ibcon#*after write, iclass 21, count 0 2006.238.07:51:12.33#ibcon#*before return 0, iclass 21, count 0 2006.238.07:51:12.33#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:51:12.33#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.07:51:12.33#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:51:12.33#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:51:12.33$vc4f8/vb=6,4 2006.238.07:51:12.33#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.238.07:51:12.33#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.238.07:51:12.33#ibcon#ireg 11 cls_cnt 2 2006.238.07:51:12.33#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:51:12.39#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:51:12.39#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:51:12.39#ibcon#enter wrdev, iclass 23, count 2 2006.238.07:51:12.39#ibcon#first serial, iclass 23, count 2 2006.238.07:51:12.39#ibcon#enter sib2, iclass 23, count 2 2006.238.07:51:12.39#ibcon#flushed, iclass 23, count 2 2006.238.07:51:12.39#ibcon#about to write, iclass 23, count 2 2006.238.07:51:12.39#ibcon#wrote, iclass 23, count 2 2006.238.07:51:12.39#ibcon#about to read 3, iclass 23, count 2 2006.238.07:51:12.41#ibcon#read 3, iclass 23, count 2 2006.238.07:51:12.41#ibcon#about to read 4, iclass 23, count 2 2006.238.07:51:12.41#ibcon#read 4, iclass 23, count 2 2006.238.07:51:12.41#ibcon#about to read 5, iclass 23, count 2 2006.238.07:51:12.41#ibcon#read 5, iclass 23, count 2 2006.238.07:51:12.41#ibcon#about to read 6, iclass 23, count 2 2006.238.07:51:12.41#ibcon#read 6, iclass 23, count 2 2006.238.07:51:12.41#ibcon#end of sib2, iclass 23, count 2 2006.238.07:51:12.41#ibcon#*mode == 0, iclass 23, count 2 2006.238.07:51:12.41#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.238.07:51:12.41#ibcon#[27=AT06-04\r\n] 2006.238.07:51:12.41#ibcon#*before write, iclass 23, count 2 2006.238.07:51:12.41#ibcon#enter sib2, iclass 23, count 2 2006.238.07:51:12.41#ibcon#flushed, iclass 23, count 2 2006.238.07:51:12.41#ibcon#about to write, iclass 23, count 2 2006.238.07:51:12.41#ibcon#wrote, iclass 23, count 2 2006.238.07:51:12.41#ibcon#about to read 3, iclass 23, count 2 2006.238.07:51:12.44#ibcon#read 3, iclass 23, count 2 2006.238.07:51:12.44#ibcon#about to read 4, iclass 23, count 2 2006.238.07:51:12.44#ibcon#read 4, iclass 23, count 2 2006.238.07:51:12.44#ibcon#about to read 5, iclass 23, count 2 2006.238.07:51:12.44#ibcon#read 5, iclass 23, count 2 2006.238.07:51:12.44#ibcon#about to read 6, iclass 23, count 2 2006.238.07:51:12.44#ibcon#read 6, iclass 23, count 2 2006.238.07:51:12.44#ibcon#end of sib2, iclass 23, count 2 2006.238.07:51:12.44#ibcon#*after write, iclass 23, count 2 2006.238.07:51:12.44#ibcon#*before return 0, iclass 23, count 2 2006.238.07:51:12.44#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:51:12.44#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.238.07:51:12.44#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.238.07:51:12.44#ibcon#ireg 7 cls_cnt 0 2006.238.07:51:12.44#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:51:12.56#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:51:12.56#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:51:12.56#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:51:12.56#ibcon#first serial, iclass 23, count 0 2006.238.07:51:12.56#ibcon#enter sib2, iclass 23, count 0 2006.238.07:51:12.56#ibcon#flushed, iclass 23, count 0 2006.238.07:51:12.56#ibcon#about to write, iclass 23, count 0 2006.238.07:51:12.56#ibcon#wrote, iclass 23, count 0 2006.238.07:51:12.56#ibcon#about to read 3, iclass 23, count 0 2006.238.07:51:12.58#ibcon#read 3, iclass 23, count 0 2006.238.07:51:12.58#ibcon#about to read 4, iclass 23, count 0 2006.238.07:51:12.58#ibcon#read 4, iclass 23, count 0 2006.238.07:51:12.58#ibcon#about to read 5, iclass 23, count 0 2006.238.07:51:12.58#ibcon#read 5, iclass 23, count 0 2006.238.07:51:12.58#ibcon#about to read 6, iclass 23, count 0 2006.238.07:51:12.58#ibcon#read 6, iclass 23, count 0 2006.238.07:51:12.58#ibcon#end of sib2, iclass 23, count 0 2006.238.07:51:12.58#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:51:12.58#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:51:12.58#ibcon#[27=USB\r\n] 2006.238.07:51:12.58#ibcon#*before write, iclass 23, count 0 2006.238.07:51:12.58#ibcon#enter sib2, iclass 23, count 0 2006.238.07:51:12.58#ibcon#flushed, iclass 23, count 0 2006.238.07:51:12.58#ibcon#about to write, iclass 23, count 0 2006.238.07:51:12.58#ibcon#wrote, iclass 23, count 0 2006.238.07:51:12.58#ibcon#about to read 3, iclass 23, count 0 2006.238.07:51:12.61#ibcon#read 3, iclass 23, count 0 2006.238.07:51:12.61#ibcon#about to read 4, iclass 23, count 0 2006.238.07:51:12.61#ibcon#read 4, iclass 23, count 0 2006.238.07:51:12.61#ibcon#about to read 5, iclass 23, count 0 2006.238.07:51:12.61#ibcon#read 5, iclass 23, count 0 2006.238.07:51:12.61#ibcon#about to read 6, iclass 23, count 0 2006.238.07:51:12.61#ibcon#read 6, iclass 23, count 0 2006.238.07:51:12.61#ibcon#end of sib2, iclass 23, count 0 2006.238.07:51:12.61#ibcon#*after write, iclass 23, count 0 2006.238.07:51:12.61#ibcon#*before return 0, iclass 23, count 0 2006.238.07:51:12.61#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:51:12.61#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.238.07:51:12.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:51:12.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:51:12.61$vc4f8/vabw=wide 2006.238.07:51:12.61#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.07:51:12.61#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.07:51:12.61#ibcon#ireg 8 cls_cnt 0 2006.238.07:51:12.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:51:12.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:51:12.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:51:12.61#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:51:12.61#ibcon#first serial, iclass 25, count 0 2006.238.07:51:12.61#ibcon#enter sib2, iclass 25, count 0 2006.238.07:51:12.61#ibcon#flushed, iclass 25, count 0 2006.238.07:51:12.61#ibcon#about to write, iclass 25, count 0 2006.238.07:51:12.61#ibcon#wrote, iclass 25, count 0 2006.238.07:51:12.61#ibcon#about to read 3, iclass 25, count 0 2006.238.07:51:12.63#ibcon#read 3, iclass 25, count 0 2006.238.07:51:12.63#ibcon#about to read 4, iclass 25, count 0 2006.238.07:51:12.63#ibcon#read 4, iclass 25, count 0 2006.238.07:51:12.63#ibcon#about to read 5, iclass 25, count 0 2006.238.07:51:12.63#ibcon#read 5, iclass 25, count 0 2006.238.07:51:12.63#ibcon#about to read 6, iclass 25, count 0 2006.238.07:51:12.63#ibcon#read 6, iclass 25, count 0 2006.238.07:51:12.63#ibcon#end of sib2, iclass 25, count 0 2006.238.07:51:12.63#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:51:12.63#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:51:12.63#ibcon#[25=BW32\r\n] 2006.238.07:51:12.63#ibcon#*before write, iclass 25, count 0 2006.238.07:51:12.63#ibcon#enter sib2, iclass 25, count 0 2006.238.07:51:12.63#ibcon#flushed, iclass 25, count 0 2006.238.07:51:12.63#ibcon#about to write, iclass 25, count 0 2006.238.07:51:12.63#ibcon#wrote, iclass 25, count 0 2006.238.07:51:12.63#ibcon#about to read 3, iclass 25, count 0 2006.238.07:51:12.66#ibcon#read 3, iclass 25, count 0 2006.238.07:51:12.66#ibcon#about to read 4, iclass 25, count 0 2006.238.07:51:12.66#ibcon#read 4, iclass 25, count 0 2006.238.07:51:12.66#ibcon#about to read 5, iclass 25, count 0 2006.238.07:51:12.66#ibcon#read 5, iclass 25, count 0 2006.238.07:51:12.66#ibcon#about to read 6, iclass 25, count 0 2006.238.07:51:12.66#ibcon#read 6, iclass 25, count 0 2006.238.07:51:12.66#ibcon#end of sib2, iclass 25, count 0 2006.238.07:51:12.66#ibcon#*after write, iclass 25, count 0 2006.238.07:51:12.66#ibcon#*before return 0, iclass 25, count 0 2006.238.07:51:12.66#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:51:12.66#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.07:51:12.66#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:51:12.66#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:51:12.66$vc4f8/vbbw=wide 2006.238.07:51:12.66#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:51:12.66#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:51:12.66#ibcon#ireg 8 cls_cnt 0 2006.238.07:51:12.66#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:51:12.73#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:51:12.73#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:51:12.73#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:51:12.73#ibcon#first serial, iclass 27, count 0 2006.238.07:51:12.73#ibcon#enter sib2, iclass 27, count 0 2006.238.07:51:12.73#ibcon#flushed, iclass 27, count 0 2006.238.07:51:12.73#ibcon#about to write, iclass 27, count 0 2006.238.07:51:12.73#ibcon#wrote, iclass 27, count 0 2006.238.07:51:12.73#ibcon#about to read 3, iclass 27, count 0 2006.238.07:51:12.75#ibcon#read 3, iclass 27, count 0 2006.238.07:51:12.75#ibcon#about to read 4, iclass 27, count 0 2006.238.07:51:12.75#ibcon#read 4, iclass 27, count 0 2006.238.07:51:12.75#ibcon#about to read 5, iclass 27, count 0 2006.238.07:51:12.75#ibcon#read 5, iclass 27, count 0 2006.238.07:51:12.75#ibcon#about to read 6, iclass 27, count 0 2006.238.07:51:12.75#ibcon#read 6, iclass 27, count 0 2006.238.07:51:12.75#ibcon#end of sib2, iclass 27, count 0 2006.238.07:51:12.75#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:51:12.75#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:51:12.75#ibcon#[27=BW32\r\n] 2006.238.07:51:12.75#ibcon#*before write, iclass 27, count 0 2006.238.07:51:12.75#ibcon#enter sib2, iclass 27, count 0 2006.238.07:51:12.75#ibcon#flushed, iclass 27, count 0 2006.238.07:51:12.75#ibcon#about to write, iclass 27, count 0 2006.238.07:51:12.75#ibcon#wrote, iclass 27, count 0 2006.238.07:51:12.75#ibcon#about to read 3, iclass 27, count 0 2006.238.07:51:12.78#ibcon#read 3, iclass 27, count 0 2006.238.07:51:12.78#ibcon#about to read 4, iclass 27, count 0 2006.238.07:51:12.78#ibcon#read 4, iclass 27, count 0 2006.238.07:51:12.78#ibcon#about to read 5, iclass 27, count 0 2006.238.07:51:12.78#ibcon#read 5, iclass 27, count 0 2006.238.07:51:12.78#ibcon#about to read 6, iclass 27, count 0 2006.238.07:51:12.78#ibcon#read 6, iclass 27, count 0 2006.238.07:51:12.78#ibcon#end of sib2, iclass 27, count 0 2006.238.07:51:12.78#ibcon#*after write, iclass 27, count 0 2006.238.07:51:12.78#ibcon#*before return 0, iclass 27, count 0 2006.238.07:51:12.78#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:51:12.78#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:51:12.78#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:51:12.78#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:51:12.78$4f8m12a/ifd4f 2006.238.07:51:12.78$ifd4f/lo= 2006.238.07:51:12.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:51:12.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:51:12.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:51:12.78$ifd4f/patch= 2006.238.07:51:12.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:51:12.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:51:12.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:51:12.78$4f8m12a/"form=m,16.000,1:2 2006.238.07:51:12.78$4f8m12a/"tpicd 2006.238.07:51:12.78$4f8m12a/echo=off 2006.238.07:51:12.78$4f8m12a/xlog=off 2006.238.07:51:12.78:!2006.238.07:51:40 2006.238.07:51:23.13#trakl#Source acquired 2006.238.07:51:25.13#flagr#flagr/antenna,acquired 2006.238.07:51:40.00:preob 2006.238.07:51:41.13/onsource/TRACKING 2006.238.07:51:41.13:!2006.238.07:51:50 2006.238.07:51:50.00:data_valid=on 2006.238.07:51:50.00:midob 2006.238.07:51:50.13/onsource/TRACKING 2006.238.07:51:50.13/wx/25.37,1012.1,87 2006.238.07:51:50.30/cable/+6.4182E-03 2006.238.07:51:51.39/va/01,08,usb,yes,31,33 2006.238.07:51:51.39/va/02,07,usb,yes,31,33 2006.238.07:51:51.39/va/03,07,usb,yes,30,30 2006.238.07:51:51.39/va/04,07,usb,yes,33,35 2006.238.07:51:51.39/va/05,08,usb,yes,30,31 2006.238.07:51:51.39/va/06,07,usb,yes,32,32 2006.238.07:51:51.39/va/07,07,usb,yes,32,32 2006.238.07:51:51.39/va/08,07,usb,yes,35,35 2006.238.07:51:51.62/valo/01,532.99,yes,locked 2006.238.07:51:51.62/valo/02,572.99,yes,locked 2006.238.07:51:51.62/valo/03,672.99,yes,locked 2006.238.07:51:51.62/valo/04,832.99,yes,locked 2006.238.07:51:51.62/valo/05,652.99,yes,locked 2006.238.07:51:51.62/valo/06,772.99,yes,locked 2006.238.07:51:51.62/valo/07,832.99,yes,locked 2006.238.07:51:51.62/valo/08,852.99,yes,locked 2006.238.07:51:52.71/vb/01,04,usb,yes,30,29 2006.238.07:51:52.71/vb/02,04,usb,yes,32,33 2006.238.07:51:52.71/vb/03,04,usb,yes,28,32 2006.238.07:51:52.71/vb/04,04,usb,yes,29,29 2006.238.07:51:52.71/vb/05,04,usb,yes,27,31 2006.238.07:51:52.71/vb/06,04,usb,yes,28,31 2006.238.07:51:52.71/vb/07,04,usb,yes,31,30 2006.238.07:51:52.71/vb/08,04,usb,yes,28,31 2006.238.07:51:52.94/vblo/01,632.99,yes,locked 2006.238.07:51:52.94/vblo/02,640.99,yes,locked 2006.238.07:51:52.94/vblo/03,656.99,yes,locked 2006.238.07:51:52.94/vblo/04,712.99,yes,locked 2006.238.07:51:52.94/vblo/05,744.99,yes,locked 2006.238.07:51:52.94/vblo/06,752.99,yes,locked 2006.238.07:51:52.94/vblo/07,734.99,yes,locked 2006.238.07:51:52.94/vblo/08,744.99,yes,locked 2006.238.07:51:53.09/vabw/8 2006.238.07:51:53.24/vbbw/8 2006.238.07:51:53.33/xfe/off,on,13.7 2006.238.07:51:53.71/ifatt/23,28,28,28 2006.238.07:51:54.08/fmout-gps/S +4.30E-07 2006.238.07:51:54.12:!2006.238.07:52:50 2006.238.07:52:50.00:data_valid=off 2006.238.07:52:50.00:postob 2006.238.07:52:50.15/cable/+6.4198E-03 2006.238.07:52:50.15/wx/25.37,1012.1,87 2006.238.07:52:51.08/fmout-gps/S +4.31E-07 2006.238.07:52:51.08:scan_name=238-0754,k06238,60 2006.238.07:52:51.08:source=oq208,140700.39,282714.7,2000.0,cw 2006.238.07:52:51.14#flagr#flagr/antenna,new-source 2006.238.07:52:52.14:checkk5 2006.238.07:52:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:52:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:52:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:52:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:52:54.01/chk_obsdata//k5ts1/T2380751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:52:54.38/chk_obsdata//k5ts2/T2380751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:52:54.76/chk_obsdata//k5ts3/T2380751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:52:55.12/chk_obsdata//k5ts4/T2380751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:52:55.82/k5log//k5ts1_log_newline 2006.238.07:52:56.51/k5log//k5ts2_log_newline 2006.238.07:52:57.19/k5log//k5ts3_log_newline 2006.238.07:52:57.88/k5log//k5ts4_log_newline 2006.238.07:52:57.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:52:57.91:4f8m12a=2 2006.238.07:52:57.91$4f8m12a/echo=on 2006.238.07:52:57.91$4f8m12a/pcalon 2006.238.07:52:57.91$pcalon/"no phase cal control is implemented here 2006.238.07:52:57.91$4f8m12a/"tpicd=stop 2006.238.07:52:57.91$4f8m12a/vc4f8 2006.238.07:52:57.91$vc4f8/valo=1,532.99 2006.238.07:52:57.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.238.07:52:57.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.238.07:52:57.91#ibcon#ireg 17 cls_cnt 0 2006.238.07:52:57.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:52:57.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:52:57.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:52:57.91#ibcon#enter wrdev, iclass 38, count 0 2006.238.07:52:57.91#ibcon#first serial, iclass 38, count 0 2006.238.07:52:57.91#ibcon#enter sib2, iclass 38, count 0 2006.238.07:52:57.91#ibcon#flushed, iclass 38, count 0 2006.238.07:52:57.91#ibcon#about to write, iclass 38, count 0 2006.238.07:52:57.91#ibcon#wrote, iclass 38, count 0 2006.238.07:52:57.91#ibcon#about to read 3, iclass 38, count 0 2006.238.07:52:57.96#ibcon#read 3, iclass 38, count 0 2006.238.07:52:57.96#ibcon#about to read 4, iclass 38, count 0 2006.238.07:52:57.96#ibcon#read 4, iclass 38, count 0 2006.238.07:52:57.96#ibcon#about to read 5, iclass 38, count 0 2006.238.07:52:57.96#ibcon#read 5, iclass 38, count 0 2006.238.07:52:57.96#ibcon#about to read 6, iclass 38, count 0 2006.238.07:52:57.96#ibcon#read 6, iclass 38, count 0 2006.238.07:52:57.96#ibcon#end of sib2, iclass 38, count 0 2006.238.07:52:57.96#ibcon#*mode == 0, iclass 38, count 0 2006.238.07:52:57.96#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.07:52:57.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:52:57.96#ibcon#*before write, iclass 38, count 0 2006.238.07:52:57.96#ibcon#enter sib2, iclass 38, count 0 2006.238.07:52:57.96#ibcon#flushed, iclass 38, count 0 2006.238.07:52:57.96#ibcon#about to write, iclass 38, count 0 2006.238.07:52:57.96#ibcon#wrote, iclass 38, count 0 2006.238.07:52:57.96#ibcon#about to read 3, iclass 38, count 0 2006.238.07:52:58.01#ibcon#read 3, iclass 38, count 0 2006.238.07:52:58.01#ibcon#about to read 4, iclass 38, count 0 2006.238.07:52:58.01#ibcon#read 4, iclass 38, count 0 2006.238.07:52:58.01#ibcon#about to read 5, iclass 38, count 0 2006.238.07:52:58.01#ibcon#read 5, iclass 38, count 0 2006.238.07:52:58.01#ibcon#about to read 6, iclass 38, count 0 2006.238.07:52:58.01#ibcon#read 6, iclass 38, count 0 2006.238.07:52:58.01#ibcon#end of sib2, iclass 38, count 0 2006.238.07:52:58.01#ibcon#*after write, iclass 38, count 0 2006.238.07:52:58.01#ibcon#*before return 0, iclass 38, count 0 2006.238.07:52:58.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:52:58.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:52:58.01#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.07:52:58.01#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.07:52:58.01$vc4f8/va=1,8 2006.238.07:52:58.01#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.238.07:52:58.01#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.238.07:52:58.01#ibcon#ireg 11 cls_cnt 2 2006.238.07:52:58.01#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:52:58.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:52:58.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:52:58.01#ibcon#enter wrdev, iclass 40, count 2 2006.238.07:52:58.01#ibcon#first serial, iclass 40, count 2 2006.238.07:52:58.01#ibcon#enter sib2, iclass 40, count 2 2006.238.07:52:58.01#ibcon#flushed, iclass 40, count 2 2006.238.07:52:58.01#ibcon#about to write, iclass 40, count 2 2006.238.07:52:58.01#ibcon#wrote, iclass 40, count 2 2006.238.07:52:58.01#ibcon#about to read 3, iclass 40, count 2 2006.238.07:52:58.03#ibcon#read 3, iclass 40, count 2 2006.238.07:52:58.03#ibcon#about to read 4, iclass 40, count 2 2006.238.07:52:58.03#ibcon#read 4, iclass 40, count 2 2006.238.07:52:58.03#ibcon#about to read 5, iclass 40, count 2 2006.238.07:52:58.03#ibcon#read 5, iclass 40, count 2 2006.238.07:52:58.03#ibcon#about to read 6, iclass 40, count 2 2006.238.07:52:58.03#ibcon#read 6, iclass 40, count 2 2006.238.07:52:58.03#ibcon#end of sib2, iclass 40, count 2 2006.238.07:52:58.03#ibcon#*mode == 0, iclass 40, count 2 2006.238.07:52:58.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.238.07:52:58.03#ibcon#[25=AT01-08\r\n] 2006.238.07:52:58.03#ibcon#*before write, iclass 40, count 2 2006.238.07:52:58.03#ibcon#enter sib2, iclass 40, count 2 2006.238.07:52:58.03#ibcon#flushed, iclass 40, count 2 2006.238.07:52:58.03#ibcon#about to write, iclass 40, count 2 2006.238.07:52:58.03#ibcon#wrote, iclass 40, count 2 2006.238.07:52:58.03#ibcon#about to read 3, iclass 40, count 2 2006.238.07:52:58.07#ibcon#read 3, iclass 40, count 2 2006.238.07:52:58.07#ibcon#about to read 4, iclass 40, count 2 2006.238.07:52:58.07#ibcon#read 4, iclass 40, count 2 2006.238.07:52:58.07#ibcon#about to read 5, iclass 40, count 2 2006.238.07:52:58.07#ibcon#read 5, iclass 40, count 2 2006.238.07:52:58.07#ibcon#about to read 6, iclass 40, count 2 2006.238.07:52:58.07#ibcon#read 6, iclass 40, count 2 2006.238.07:52:58.07#ibcon#end of sib2, iclass 40, count 2 2006.238.07:52:58.07#ibcon#*after write, iclass 40, count 2 2006.238.07:52:58.07#ibcon#*before return 0, iclass 40, count 2 2006.238.07:52:58.07#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:52:58.07#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:52:58.07#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.238.07:52:58.07#ibcon#ireg 7 cls_cnt 0 2006.238.07:52:58.07#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:52:58.19#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:52:58.19#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:52:58.19#ibcon#enter wrdev, iclass 40, count 0 2006.238.07:52:58.19#ibcon#first serial, iclass 40, count 0 2006.238.07:52:58.19#ibcon#enter sib2, iclass 40, count 0 2006.238.07:52:58.19#ibcon#flushed, iclass 40, count 0 2006.238.07:52:58.19#ibcon#about to write, iclass 40, count 0 2006.238.07:52:58.19#ibcon#wrote, iclass 40, count 0 2006.238.07:52:58.19#ibcon#about to read 3, iclass 40, count 0 2006.238.07:52:58.21#ibcon#read 3, iclass 40, count 0 2006.238.07:52:58.21#ibcon#about to read 4, iclass 40, count 0 2006.238.07:52:58.21#ibcon#read 4, iclass 40, count 0 2006.238.07:52:58.21#ibcon#about to read 5, iclass 40, count 0 2006.238.07:52:58.21#ibcon#read 5, iclass 40, count 0 2006.238.07:52:58.21#ibcon#about to read 6, iclass 40, count 0 2006.238.07:52:58.21#ibcon#read 6, iclass 40, count 0 2006.238.07:52:58.21#ibcon#end of sib2, iclass 40, count 0 2006.238.07:52:58.21#ibcon#*mode == 0, iclass 40, count 0 2006.238.07:52:58.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.07:52:58.21#ibcon#[25=USB\r\n] 2006.238.07:52:58.21#ibcon#*before write, iclass 40, count 0 2006.238.07:52:58.21#ibcon#enter sib2, iclass 40, count 0 2006.238.07:52:58.21#ibcon#flushed, iclass 40, count 0 2006.238.07:52:58.21#ibcon#about to write, iclass 40, count 0 2006.238.07:52:58.21#ibcon#wrote, iclass 40, count 0 2006.238.07:52:58.21#ibcon#about to read 3, iclass 40, count 0 2006.238.07:52:58.24#ibcon#read 3, iclass 40, count 0 2006.238.07:52:58.24#ibcon#about to read 4, iclass 40, count 0 2006.238.07:52:58.24#ibcon#read 4, iclass 40, count 0 2006.238.07:52:58.24#ibcon#about to read 5, iclass 40, count 0 2006.238.07:52:58.24#ibcon#read 5, iclass 40, count 0 2006.238.07:52:58.24#ibcon#about to read 6, iclass 40, count 0 2006.238.07:52:58.24#ibcon#read 6, iclass 40, count 0 2006.238.07:52:58.24#ibcon#end of sib2, iclass 40, count 0 2006.238.07:52:58.24#ibcon#*after write, iclass 40, count 0 2006.238.07:52:58.24#ibcon#*before return 0, iclass 40, count 0 2006.238.07:52:58.24#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:52:58.24#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:52:58.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.07:52:58.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.07:52:58.24$vc4f8/valo=2,572.99 2006.238.07:52:58.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.07:52:58.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.07:52:58.24#ibcon#ireg 17 cls_cnt 0 2006.238.07:52:58.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:52:58.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:52:58.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:52:58.24#ibcon#enter wrdev, iclass 4, count 0 2006.238.07:52:58.24#ibcon#first serial, iclass 4, count 0 2006.238.07:52:58.24#ibcon#enter sib2, iclass 4, count 0 2006.238.07:52:58.24#ibcon#flushed, iclass 4, count 0 2006.238.07:52:58.24#ibcon#about to write, iclass 4, count 0 2006.238.07:52:58.24#ibcon#wrote, iclass 4, count 0 2006.238.07:52:58.24#ibcon#about to read 3, iclass 4, count 0 2006.238.07:52:58.26#ibcon#read 3, iclass 4, count 0 2006.238.07:52:58.26#ibcon#about to read 4, iclass 4, count 0 2006.238.07:52:58.26#ibcon#read 4, iclass 4, count 0 2006.238.07:52:58.26#ibcon#about to read 5, iclass 4, count 0 2006.238.07:52:58.26#ibcon#read 5, iclass 4, count 0 2006.238.07:52:58.26#ibcon#about to read 6, iclass 4, count 0 2006.238.07:52:58.26#ibcon#read 6, iclass 4, count 0 2006.238.07:52:58.26#ibcon#end of sib2, iclass 4, count 0 2006.238.07:52:58.26#ibcon#*mode == 0, iclass 4, count 0 2006.238.07:52:58.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.07:52:58.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:52:58.26#ibcon#*before write, iclass 4, count 0 2006.238.07:52:58.26#ibcon#enter sib2, iclass 4, count 0 2006.238.07:52:58.26#ibcon#flushed, iclass 4, count 0 2006.238.07:52:58.26#ibcon#about to write, iclass 4, count 0 2006.238.07:52:58.26#ibcon#wrote, iclass 4, count 0 2006.238.07:52:58.26#ibcon#about to read 3, iclass 4, count 0 2006.238.07:52:58.30#ibcon#read 3, iclass 4, count 0 2006.238.07:52:58.30#ibcon#about to read 4, iclass 4, count 0 2006.238.07:52:58.30#ibcon#read 4, iclass 4, count 0 2006.238.07:52:58.30#ibcon#about to read 5, iclass 4, count 0 2006.238.07:52:58.30#ibcon#read 5, iclass 4, count 0 2006.238.07:52:58.30#ibcon#about to read 6, iclass 4, count 0 2006.238.07:52:58.30#ibcon#read 6, iclass 4, count 0 2006.238.07:52:58.30#ibcon#end of sib2, iclass 4, count 0 2006.238.07:52:58.30#ibcon#*after write, iclass 4, count 0 2006.238.07:52:58.30#ibcon#*before return 0, iclass 4, count 0 2006.238.07:52:58.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:52:58.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:52:58.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.07:52:58.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.07:52:58.30$vc4f8/va=2,7 2006.238.07:52:58.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.07:52:58.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.07:52:58.30#ibcon#ireg 11 cls_cnt 2 2006.238.07:52:58.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:52:58.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:52:58.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:52:58.36#ibcon#enter wrdev, iclass 6, count 2 2006.238.07:52:58.36#ibcon#first serial, iclass 6, count 2 2006.238.07:52:58.36#ibcon#enter sib2, iclass 6, count 2 2006.238.07:52:58.36#ibcon#flushed, iclass 6, count 2 2006.238.07:52:58.36#ibcon#about to write, iclass 6, count 2 2006.238.07:52:58.36#ibcon#wrote, iclass 6, count 2 2006.238.07:52:58.36#ibcon#about to read 3, iclass 6, count 2 2006.238.07:52:58.38#ibcon#read 3, iclass 6, count 2 2006.238.07:52:58.38#ibcon#about to read 4, iclass 6, count 2 2006.238.07:52:58.38#ibcon#read 4, iclass 6, count 2 2006.238.07:52:58.38#ibcon#about to read 5, iclass 6, count 2 2006.238.07:52:58.38#ibcon#read 5, iclass 6, count 2 2006.238.07:52:58.38#ibcon#about to read 6, iclass 6, count 2 2006.238.07:52:58.38#ibcon#read 6, iclass 6, count 2 2006.238.07:52:58.38#ibcon#end of sib2, iclass 6, count 2 2006.238.07:52:58.38#ibcon#*mode == 0, iclass 6, count 2 2006.238.07:52:58.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.07:52:58.38#ibcon#[25=AT02-07\r\n] 2006.238.07:52:58.38#ibcon#*before write, iclass 6, count 2 2006.238.07:52:58.38#ibcon#enter sib2, iclass 6, count 2 2006.238.07:52:58.38#ibcon#flushed, iclass 6, count 2 2006.238.07:52:58.38#ibcon#about to write, iclass 6, count 2 2006.238.07:52:58.38#ibcon#wrote, iclass 6, count 2 2006.238.07:52:58.38#ibcon#about to read 3, iclass 6, count 2 2006.238.07:52:58.41#ibcon#read 3, iclass 6, count 2 2006.238.07:52:58.41#ibcon#about to read 4, iclass 6, count 2 2006.238.07:52:58.41#ibcon#read 4, iclass 6, count 2 2006.238.07:52:58.41#ibcon#about to read 5, iclass 6, count 2 2006.238.07:52:58.41#ibcon#read 5, iclass 6, count 2 2006.238.07:52:58.41#ibcon#about to read 6, iclass 6, count 2 2006.238.07:52:58.41#ibcon#read 6, iclass 6, count 2 2006.238.07:52:58.41#ibcon#end of sib2, iclass 6, count 2 2006.238.07:52:58.41#ibcon#*after write, iclass 6, count 2 2006.238.07:52:58.41#ibcon#*before return 0, iclass 6, count 2 2006.238.07:52:58.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:52:58.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:52:58.41#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.07:52:58.41#ibcon#ireg 7 cls_cnt 0 2006.238.07:52:58.41#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:52:58.54#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:52:58.54#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:52:58.54#ibcon#enter wrdev, iclass 6, count 0 2006.238.07:52:58.54#ibcon#first serial, iclass 6, count 0 2006.238.07:52:58.54#ibcon#enter sib2, iclass 6, count 0 2006.238.07:52:58.54#ibcon#flushed, iclass 6, count 0 2006.238.07:52:58.54#ibcon#about to write, iclass 6, count 0 2006.238.07:52:58.54#ibcon#wrote, iclass 6, count 0 2006.238.07:52:58.54#ibcon#about to read 3, iclass 6, count 0 2006.238.07:52:58.56#ibcon#read 3, iclass 6, count 0 2006.238.07:52:58.56#ibcon#about to read 4, iclass 6, count 0 2006.238.07:52:58.56#ibcon#read 4, iclass 6, count 0 2006.238.07:52:58.56#ibcon#about to read 5, iclass 6, count 0 2006.238.07:52:58.56#ibcon#read 5, iclass 6, count 0 2006.238.07:52:58.56#ibcon#about to read 6, iclass 6, count 0 2006.238.07:52:58.56#ibcon#read 6, iclass 6, count 0 2006.238.07:52:58.56#ibcon#end of sib2, iclass 6, count 0 2006.238.07:52:58.56#ibcon#*mode == 0, iclass 6, count 0 2006.238.07:52:58.56#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.07:52:58.56#ibcon#[25=USB\r\n] 2006.238.07:52:58.56#ibcon#*before write, iclass 6, count 0 2006.238.07:52:58.56#ibcon#enter sib2, iclass 6, count 0 2006.238.07:52:58.56#ibcon#flushed, iclass 6, count 0 2006.238.07:52:58.56#ibcon#about to write, iclass 6, count 0 2006.238.07:52:58.56#ibcon#wrote, iclass 6, count 0 2006.238.07:52:58.56#ibcon#about to read 3, iclass 6, count 0 2006.238.07:52:58.59#ibcon#read 3, iclass 6, count 0 2006.238.07:52:58.59#ibcon#about to read 4, iclass 6, count 0 2006.238.07:52:58.59#ibcon#read 4, iclass 6, count 0 2006.238.07:52:58.59#ibcon#about to read 5, iclass 6, count 0 2006.238.07:52:58.59#ibcon#read 5, iclass 6, count 0 2006.238.07:52:58.59#ibcon#about to read 6, iclass 6, count 0 2006.238.07:52:58.59#ibcon#read 6, iclass 6, count 0 2006.238.07:52:58.59#ibcon#end of sib2, iclass 6, count 0 2006.238.07:52:58.59#ibcon#*after write, iclass 6, count 0 2006.238.07:52:58.59#ibcon#*before return 0, iclass 6, count 0 2006.238.07:52:58.59#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:52:58.59#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:52:58.59#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.07:52:58.59#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.07:52:58.59$vc4f8/valo=3,672.99 2006.238.07:52:58.59#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.07:52:58.59#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.07:52:58.59#ibcon#ireg 17 cls_cnt 0 2006.238.07:52:58.59#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:52:58.59#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:52:58.59#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:52:58.59#ibcon#enter wrdev, iclass 10, count 0 2006.238.07:52:58.59#ibcon#first serial, iclass 10, count 0 2006.238.07:52:58.59#ibcon#enter sib2, iclass 10, count 0 2006.238.07:52:58.59#ibcon#flushed, iclass 10, count 0 2006.238.07:52:58.59#ibcon#about to write, iclass 10, count 0 2006.238.07:52:58.59#ibcon#wrote, iclass 10, count 0 2006.238.07:52:58.59#ibcon#about to read 3, iclass 10, count 0 2006.238.07:52:58.61#ibcon#read 3, iclass 10, count 0 2006.238.07:52:58.61#ibcon#about to read 4, iclass 10, count 0 2006.238.07:52:58.61#ibcon#read 4, iclass 10, count 0 2006.238.07:52:58.61#ibcon#about to read 5, iclass 10, count 0 2006.238.07:52:58.61#ibcon#read 5, iclass 10, count 0 2006.238.07:52:58.61#ibcon#about to read 6, iclass 10, count 0 2006.238.07:52:58.61#ibcon#read 6, iclass 10, count 0 2006.238.07:52:58.61#ibcon#end of sib2, iclass 10, count 0 2006.238.07:52:58.61#ibcon#*mode == 0, iclass 10, count 0 2006.238.07:52:58.61#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.07:52:58.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:52:58.61#ibcon#*before write, iclass 10, count 0 2006.238.07:52:58.61#ibcon#enter sib2, iclass 10, count 0 2006.238.07:52:58.61#ibcon#flushed, iclass 10, count 0 2006.238.07:52:58.61#ibcon#about to write, iclass 10, count 0 2006.238.07:52:58.61#ibcon#wrote, iclass 10, count 0 2006.238.07:52:58.61#ibcon#about to read 3, iclass 10, count 0 2006.238.07:52:58.65#ibcon#read 3, iclass 10, count 0 2006.238.07:52:58.65#ibcon#about to read 4, iclass 10, count 0 2006.238.07:52:58.65#ibcon#read 4, iclass 10, count 0 2006.238.07:52:58.65#ibcon#about to read 5, iclass 10, count 0 2006.238.07:52:58.65#ibcon#read 5, iclass 10, count 0 2006.238.07:52:58.65#ibcon#about to read 6, iclass 10, count 0 2006.238.07:52:58.65#ibcon#read 6, iclass 10, count 0 2006.238.07:52:58.65#ibcon#end of sib2, iclass 10, count 0 2006.238.07:52:58.65#ibcon#*after write, iclass 10, count 0 2006.238.07:52:58.65#ibcon#*before return 0, iclass 10, count 0 2006.238.07:52:58.65#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:52:58.65#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:52:58.65#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.07:52:58.65#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.07:52:58.65$vc4f8/va=3,7 2006.238.07:52:58.65#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.238.07:52:58.65#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.238.07:52:58.65#ibcon#ireg 11 cls_cnt 2 2006.238.07:52:58.65#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:52:58.71#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:52:58.71#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:52:58.71#ibcon#enter wrdev, iclass 12, count 2 2006.238.07:52:58.71#ibcon#first serial, iclass 12, count 2 2006.238.07:52:58.71#ibcon#enter sib2, iclass 12, count 2 2006.238.07:52:58.71#ibcon#flushed, iclass 12, count 2 2006.238.07:52:58.71#ibcon#about to write, iclass 12, count 2 2006.238.07:52:58.71#ibcon#wrote, iclass 12, count 2 2006.238.07:52:58.71#ibcon#about to read 3, iclass 12, count 2 2006.238.07:52:58.73#ibcon#read 3, iclass 12, count 2 2006.238.07:52:58.73#ibcon#about to read 4, iclass 12, count 2 2006.238.07:52:58.73#ibcon#read 4, iclass 12, count 2 2006.238.07:52:58.73#ibcon#about to read 5, iclass 12, count 2 2006.238.07:52:58.73#ibcon#read 5, iclass 12, count 2 2006.238.07:52:58.73#ibcon#about to read 6, iclass 12, count 2 2006.238.07:52:58.73#ibcon#read 6, iclass 12, count 2 2006.238.07:52:58.73#ibcon#end of sib2, iclass 12, count 2 2006.238.07:52:58.73#ibcon#*mode == 0, iclass 12, count 2 2006.238.07:52:58.73#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.238.07:52:58.73#ibcon#[25=AT03-07\r\n] 2006.238.07:52:58.73#ibcon#*before write, iclass 12, count 2 2006.238.07:52:58.73#ibcon#enter sib2, iclass 12, count 2 2006.238.07:52:58.73#ibcon#flushed, iclass 12, count 2 2006.238.07:52:58.73#ibcon#about to write, iclass 12, count 2 2006.238.07:52:58.73#ibcon#wrote, iclass 12, count 2 2006.238.07:52:58.73#ibcon#about to read 3, iclass 12, count 2 2006.238.07:52:58.76#ibcon#read 3, iclass 12, count 2 2006.238.07:52:58.76#ibcon#about to read 4, iclass 12, count 2 2006.238.07:52:58.76#ibcon#read 4, iclass 12, count 2 2006.238.07:52:58.76#ibcon#about to read 5, iclass 12, count 2 2006.238.07:52:58.76#ibcon#read 5, iclass 12, count 2 2006.238.07:52:58.76#ibcon#about to read 6, iclass 12, count 2 2006.238.07:52:58.76#ibcon#read 6, iclass 12, count 2 2006.238.07:52:58.76#ibcon#end of sib2, iclass 12, count 2 2006.238.07:52:58.76#ibcon#*after write, iclass 12, count 2 2006.238.07:52:58.76#ibcon#*before return 0, iclass 12, count 2 2006.238.07:52:58.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:52:58.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:52:58.76#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.238.07:52:58.76#ibcon#ireg 7 cls_cnt 0 2006.238.07:52:58.76#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:52:58.88#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:52:58.88#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:52:58.88#ibcon#enter wrdev, iclass 12, count 0 2006.238.07:52:58.88#ibcon#first serial, iclass 12, count 0 2006.238.07:52:58.88#ibcon#enter sib2, iclass 12, count 0 2006.238.07:52:58.88#ibcon#flushed, iclass 12, count 0 2006.238.07:52:58.88#ibcon#about to write, iclass 12, count 0 2006.238.07:52:58.88#ibcon#wrote, iclass 12, count 0 2006.238.07:52:58.88#ibcon#about to read 3, iclass 12, count 0 2006.238.07:52:58.90#ibcon#read 3, iclass 12, count 0 2006.238.07:52:58.90#ibcon#about to read 4, iclass 12, count 0 2006.238.07:52:58.90#ibcon#read 4, iclass 12, count 0 2006.238.07:52:58.90#ibcon#about to read 5, iclass 12, count 0 2006.238.07:52:58.90#ibcon#read 5, iclass 12, count 0 2006.238.07:52:58.90#ibcon#about to read 6, iclass 12, count 0 2006.238.07:52:58.90#ibcon#read 6, iclass 12, count 0 2006.238.07:52:58.90#ibcon#end of sib2, iclass 12, count 0 2006.238.07:52:58.90#ibcon#*mode == 0, iclass 12, count 0 2006.238.07:52:58.90#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.07:52:58.90#ibcon#[25=USB\r\n] 2006.238.07:52:58.90#ibcon#*before write, iclass 12, count 0 2006.238.07:52:58.90#ibcon#enter sib2, iclass 12, count 0 2006.238.07:52:58.90#ibcon#flushed, iclass 12, count 0 2006.238.07:52:58.90#ibcon#about to write, iclass 12, count 0 2006.238.07:52:58.90#ibcon#wrote, iclass 12, count 0 2006.238.07:52:58.90#ibcon#about to read 3, iclass 12, count 0 2006.238.07:52:58.93#ibcon#read 3, iclass 12, count 0 2006.238.07:52:58.93#ibcon#about to read 4, iclass 12, count 0 2006.238.07:52:58.93#ibcon#read 4, iclass 12, count 0 2006.238.07:52:58.93#ibcon#about to read 5, iclass 12, count 0 2006.238.07:52:58.93#ibcon#read 5, iclass 12, count 0 2006.238.07:52:58.93#ibcon#about to read 6, iclass 12, count 0 2006.238.07:52:58.93#ibcon#read 6, iclass 12, count 0 2006.238.07:52:58.93#ibcon#end of sib2, iclass 12, count 0 2006.238.07:52:58.93#ibcon#*after write, iclass 12, count 0 2006.238.07:52:58.93#ibcon#*before return 0, iclass 12, count 0 2006.238.07:52:58.93#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:52:58.93#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:52:58.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.07:52:58.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.07:52:58.93$vc4f8/valo=4,832.99 2006.238.07:52:58.93#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.07:52:58.93#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.07:52:58.93#ibcon#ireg 17 cls_cnt 0 2006.238.07:52:58.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:52:58.93#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:52:58.93#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:52:58.93#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:52:58.93#ibcon#first serial, iclass 14, count 0 2006.238.07:52:58.93#ibcon#enter sib2, iclass 14, count 0 2006.238.07:52:58.93#ibcon#flushed, iclass 14, count 0 2006.238.07:52:58.93#ibcon#about to write, iclass 14, count 0 2006.238.07:52:58.93#ibcon#wrote, iclass 14, count 0 2006.238.07:52:58.93#ibcon#about to read 3, iclass 14, count 0 2006.238.07:52:58.95#ibcon#read 3, iclass 14, count 0 2006.238.07:52:58.95#ibcon#about to read 4, iclass 14, count 0 2006.238.07:52:58.95#ibcon#read 4, iclass 14, count 0 2006.238.07:52:58.95#ibcon#about to read 5, iclass 14, count 0 2006.238.07:52:58.95#ibcon#read 5, iclass 14, count 0 2006.238.07:52:58.95#ibcon#about to read 6, iclass 14, count 0 2006.238.07:52:58.95#ibcon#read 6, iclass 14, count 0 2006.238.07:52:58.95#ibcon#end of sib2, iclass 14, count 0 2006.238.07:52:58.95#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:52:58.95#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:52:58.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:52:58.95#ibcon#*before write, iclass 14, count 0 2006.238.07:52:58.95#ibcon#enter sib2, iclass 14, count 0 2006.238.07:52:58.95#ibcon#flushed, iclass 14, count 0 2006.238.07:52:58.95#ibcon#about to write, iclass 14, count 0 2006.238.07:52:58.95#ibcon#wrote, iclass 14, count 0 2006.238.07:52:58.95#ibcon#about to read 3, iclass 14, count 0 2006.238.07:52:58.99#ibcon#read 3, iclass 14, count 0 2006.238.07:52:58.99#ibcon#about to read 4, iclass 14, count 0 2006.238.07:52:58.99#ibcon#read 4, iclass 14, count 0 2006.238.07:52:58.99#ibcon#about to read 5, iclass 14, count 0 2006.238.07:52:58.99#ibcon#read 5, iclass 14, count 0 2006.238.07:52:58.99#ibcon#about to read 6, iclass 14, count 0 2006.238.07:52:58.99#ibcon#read 6, iclass 14, count 0 2006.238.07:52:58.99#ibcon#end of sib2, iclass 14, count 0 2006.238.07:52:58.99#ibcon#*after write, iclass 14, count 0 2006.238.07:52:58.99#ibcon#*before return 0, iclass 14, count 0 2006.238.07:52:58.99#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:52:58.99#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:52:58.99#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:52:58.99#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:52:58.99$vc4f8/va=4,7 2006.238.07:52:58.99#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.238.07:52:58.99#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.238.07:52:58.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:52:58.99#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:52:59.05#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:52:59.05#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:52:59.05#ibcon#enter wrdev, iclass 16, count 2 2006.238.07:52:59.05#ibcon#first serial, iclass 16, count 2 2006.238.07:52:59.05#ibcon#enter sib2, iclass 16, count 2 2006.238.07:52:59.05#ibcon#flushed, iclass 16, count 2 2006.238.07:52:59.05#ibcon#about to write, iclass 16, count 2 2006.238.07:52:59.05#ibcon#wrote, iclass 16, count 2 2006.238.07:52:59.05#ibcon#about to read 3, iclass 16, count 2 2006.238.07:52:59.07#ibcon#read 3, iclass 16, count 2 2006.238.07:52:59.07#ibcon#about to read 4, iclass 16, count 2 2006.238.07:52:59.07#ibcon#read 4, iclass 16, count 2 2006.238.07:52:59.07#ibcon#about to read 5, iclass 16, count 2 2006.238.07:52:59.07#ibcon#read 5, iclass 16, count 2 2006.238.07:52:59.07#ibcon#about to read 6, iclass 16, count 2 2006.238.07:52:59.07#ibcon#read 6, iclass 16, count 2 2006.238.07:52:59.07#ibcon#end of sib2, iclass 16, count 2 2006.238.07:52:59.07#ibcon#*mode == 0, iclass 16, count 2 2006.238.07:52:59.07#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.238.07:52:59.07#ibcon#[25=AT04-07\r\n] 2006.238.07:52:59.07#ibcon#*before write, iclass 16, count 2 2006.238.07:52:59.07#ibcon#enter sib2, iclass 16, count 2 2006.238.07:52:59.07#ibcon#flushed, iclass 16, count 2 2006.238.07:52:59.07#ibcon#about to write, iclass 16, count 2 2006.238.07:52:59.07#ibcon#wrote, iclass 16, count 2 2006.238.07:52:59.07#ibcon#about to read 3, iclass 16, count 2 2006.238.07:52:59.10#ibcon#read 3, iclass 16, count 2 2006.238.07:52:59.10#ibcon#about to read 4, iclass 16, count 2 2006.238.07:52:59.10#ibcon#read 4, iclass 16, count 2 2006.238.07:52:59.10#ibcon#about to read 5, iclass 16, count 2 2006.238.07:52:59.10#ibcon#read 5, iclass 16, count 2 2006.238.07:52:59.10#ibcon#about to read 6, iclass 16, count 2 2006.238.07:52:59.10#ibcon#read 6, iclass 16, count 2 2006.238.07:52:59.10#ibcon#end of sib2, iclass 16, count 2 2006.238.07:52:59.10#ibcon#*after write, iclass 16, count 2 2006.238.07:52:59.10#ibcon#*before return 0, iclass 16, count 2 2006.238.07:52:59.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:52:59.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:52:59.10#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.238.07:52:59.10#ibcon#ireg 7 cls_cnt 0 2006.238.07:52:59.10#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:52:59.22#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:52:59.22#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:52:59.22#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:52:59.22#ibcon#first serial, iclass 16, count 0 2006.238.07:52:59.22#ibcon#enter sib2, iclass 16, count 0 2006.238.07:52:59.22#ibcon#flushed, iclass 16, count 0 2006.238.07:52:59.22#ibcon#about to write, iclass 16, count 0 2006.238.07:52:59.22#ibcon#wrote, iclass 16, count 0 2006.238.07:52:59.22#ibcon#about to read 3, iclass 16, count 0 2006.238.07:52:59.24#ibcon#read 3, iclass 16, count 0 2006.238.07:52:59.24#ibcon#about to read 4, iclass 16, count 0 2006.238.07:52:59.24#ibcon#read 4, iclass 16, count 0 2006.238.07:52:59.24#ibcon#about to read 5, iclass 16, count 0 2006.238.07:52:59.24#ibcon#read 5, iclass 16, count 0 2006.238.07:52:59.24#ibcon#about to read 6, iclass 16, count 0 2006.238.07:52:59.24#ibcon#read 6, iclass 16, count 0 2006.238.07:52:59.24#ibcon#end of sib2, iclass 16, count 0 2006.238.07:52:59.24#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:52:59.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:52:59.24#ibcon#[25=USB\r\n] 2006.238.07:52:59.24#ibcon#*before write, iclass 16, count 0 2006.238.07:52:59.24#ibcon#enter sib2, iclass 16, count 0 2006.238.07:52:59.24#ibcon#flushed, iclass 16, count 0 2006.238.07:52:59.24#ibcon#about to write, iclass 16, count 0 2006.238.07:52:59.24#ibcon#wrote, iclass 16, count 0 2006.238.07:52:59.24#ibcon#about to read 3, iclass 16, count 0 2006.238.07:52:59.27#ibcon#read 3, iclass 16, count 0 2006.238.07:52:59.27#ibcon#about to read 4, iclass 16, count 0 2006.238.07:52:59.27#ibcon#read 4, iclass 16, count 0 2006.238.07:52:59.27#ibcon#about to read 5, iclass 16, count 0 2006.238.07:52:59.27#ibcon#read 5, iclass 16, count 0 2006.238.07:52:59.27#ibcon#about to read 6, iclass 16, count 0 2006.238.07:52:59.27#ibcon#read 6, iclass 16, count 0 2006.238.07:52:59.27#ibcon#end of sib2, iclass 16, count 0 2006.238.07:52:59.27#ibcon#*after write, iclass 16, count 0 2006.238.07:52:59.27#ibcon#*before return 0, iclass 16, count 0 2006.238.07:52:59.27#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:52:59.27#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:52:59.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:52:59.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:52:59.27$vc4f8/valo=5,652.99 2006.238.07:52:59.27#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.07:52:59.27#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.07:52:59.27#ibcon#ireg 17 cls_cnt 0 2006.238.07:52:59.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:52:59.27#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:52:59.27#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:52:59.27#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:52:59.27#ibcon#first serial, iclass 18, count 0 2006.238.07:52:59.27#ibcon#enter sib2, iclass 18, count 0 2006.238.07:52:59.27#ibcon#flushed, iclass 18, count 0 2006.238.07:52:59.27#ibcon#about to write, iclass 18, count 0 2006.238.07:52:59.27#ibcon#wrote, iclass 18, count 0 2006.238.07:52:59.27#ibcon#about to read 3, iclass 18, count 0 2006.238.07:52:59.29#ibcon#read 3, iclass 18, count 0 2006.238.07:52:59.29#ibcon#about to read 4, iclass 18, count 0 2006.238.07:52:59.29#ibcon#read 4, iclass 18, count 0 2006.238.07:52:59.29#ibcon#about to read 5, iclass 18, count 0 2006.238.07:52:59.29#ibcon#read 5, iclass 18, count 0 2006.238.07:52:59.29#ibcon#about to read 6, iclass 18, count 0 2006.238.07:52:59.29#ibcon#read 6, iclass 18, count 0 2006.238.07:52:59.29#ibcon#end of sib2, iclass 18, count 0 2006.238.07:52:59.29#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:52:59.29#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:52:59.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:52:59.29#ibcon#*before write, iclass 18, count 0 2006.238.07:52:59.29#ibcon#enter sib2, iclass 18, count 0 2006.238.07:52:59.29#ibcon#flushed, iclass 18, count 0 2006.238.07:52:59.29#ibcon#about to write, iclass 18, count 0 2006.238.07:52:59.29#ibcon#wrote, iclass 18, count 0 2006.238.07:52:59.29#ibcon#about to read 3, iclass 18, count 0 2006.238.07:52:59.33#ibcon#read 3, iclass 18, count 0 2006.238.07:52:59.33#ibcon#about to read 4, iclass 18, count 0 2006.238.07:52:59.33#ibcon#read 4, iclass 18, count 0 2006.238.07:52:59.33#ibcon#about to read 5, iclass 18, count 0 2006.238.07:52:59.33#ibcon#read 5, iclass 18, count 0 2006.238.07:52:59.33#ibcon#about to read 6, iclass 18, count 0 2006.238.07:52:59.33#ibcon#read 6, iclass 18, count 0 2006.238.07:52:59.33#ibcon#end of sib2, iclass 18, count 0 2006.238.07:52:59.33#ibcon#*after write, iclass 18, count 0 2006.238.07:52:59.33#ibcon#*before return 0, iclass 18, count 0 2006.238.07:52:59.33#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:52:59.33#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:52:59.33#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:52:59.33#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:52:59.33$vc4f8/va=5,8 2006.238.07:52:59.33#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.238.07:52:59.33#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.238.07:52:59.33#ibcon#ireg 11 cls_cnt 2 2006.238.07:52:59.33#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:52:59.39#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:52:59.39#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:52:59.39#ibcon#enter wrdev, iclass 20, count 2 2006.238.07:52:59.39#ibcon#first serial, iclass 20, count 2 2006.238.07:52:59.39#ibcon#enter sib2, iclass 20, count 2 2006.238.07:52:59.39#ibcon#flushed, iclass 20, count 2 2006.238.07:52:59.39#ibcon#about to write, iclass 20, count 2 2006.238.07:52:59.39#ibcon#wrote, iclass 20, count 2 2006.238.07:52:59.39#ibcon#about to read 3, iclass 20, count 2 2006.238.07:52:59.41#ibcon#read 3, iclass 20, count 2 2006.238.07:52:59.41#ibcon#about to read 4, iclass 20, count 2 2006.238.07:52:59.41#ibcon#read 4, iclass 20, count 2 2006.238.07:52:59.41#ibcon#about to read 5, iclass 20, count 2 2006.238.07:52:59.41#ibcon#read 5, iclass 20, count 2 2006.238.07:52:59.41#ibcon#about to read 6, iclass 20, count 2 2006.238.07:52:59.41#ibcon#read 6, iclass 20, count 2 2006.238.07:52:59.41#ibcon#end of sib2, iclass 20, count 2 2006.238.07:52:59.41#ibcon#*mode == 0, iclass 20, count 2 2006.238.07:52:59.41#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.238.07:52:59.41#ibcon#[25=AT05-08\r\n] 2006.238.07:52:59.41#ibcon#*before write, iclass 20, count 2 2006.238.07:52:59.41#ibcon#enter sib2, iclass 20, count 2 2006.238.07:52:59.41#ibcon#flushed, iclass 20, count 2 2006.238.07:52:59.41#ibcon#about to write, iclass 20, count 2 2006.238.07:52:59.41#ibcon#wrote, iclass 20, count 2 2006.238.07:52:59.41#ibcon#about to read 3, iclass 20, count 2 2006.238.07:52:59.44#ibcon#read 3, iclass 20, count 2 2006.238.07:52:59.44#ibcon#about to read 4, iclass 20, count 2 2006.238.07:52:59.44#ibcon#read 4, iclass 20, count 2 2006.238.07:52:59.44#ibcon#about to read 5, iclass 20, count 2 2006.238.07:52:59.44#ibcon#read 5, iclass 20, count 2 2006.238.07:52:59.44#ibcon#about to read 6, iclass 20, count 2 2006.238.07:52:59.44#ibcon#read 6, iclass 20, count 2 2006.238.07:52:59.44#ibcon#end of sib2, iclass 20, count 2 2006.238.07:52:59.44#ibcon#*after write, iclass 20, count 2 2006.238.07:52:59.44#ibcon#*before return 0, iclass 20, count 2 2006.238.07:52:59.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:52:59.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:52:59.44#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.238.07:52:59.44#ibcon#ireg 7 cls_cnt 0 2006.238.07:52:59.44#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:52:59.56#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:52:59.56#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:52:59.56#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:52:59.56#ibcon#first serial, iclass 20, count 0 2006.238.07:52:59.56#ibcon#enter sib2, iclass 20, count 0 2006.238.07:52:59.56#ibcon#flushed, iclass 20, count 0 2006.238.07:52:59.56#ibcon#about to write, iclass 20, count 0 2006.238.07:52:59.56#ibcon#wrote, iclass 20, count 0 2006.238.07:52:59.56#ibcon#about to read 3, iclass 20, count 0 2006.238.07:52:59.58#ibcon#read 3, iclass 20, count 0 2006.238.07:52:59.58#ibcon#about to read 4, iclass 20, count 0 2006.238.07:52:59.58#ibcon#read 4, iclass 20, count 0 2006.238.07:52:59.58#ibcon#about to read 5, iclass 20, count 0 2006.238.07:52:59.58#ibcon#read 5, iclass 20, count 0 2006.238.07:52:59.58#ibcon#about to read 6, iclass 20, count 0 2006.238.07:52:59.58#ibcon#read 6, iclass 20, count 0 2006.238.07:52:59.58#ibcon#end of sib2, iclass 20, count 0 2006.238.07:52:59.58#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:52:59.58#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:52:59.58#ibcon#[25=USB\r\n] 2006.238.07:52:59.58#ibcon#*before write, iclass 20, count 0 2006.238.07:52:59.58#ibcon#enter sib2, iclass 20, count 0 2006.238.07:52:59.58#ibcon#flushed, iclass 20, count 0 2006.238.07:52:59.58#ibcon#about to write, iclass 20, count 0 2006.238.07:52:59.58#ibcon#wrote, iclass 20, count 0 2006.238.07:52:59.58#ibcon#about to read 3, iclass 20, count 0 2006.238.07:52:59.61#ibcon#read 3, iclass 20, count 0 2006.238.07:52:59.61#ibcon#about to read 4, iclass 20, count 0 2006.238.07:52:59.61#ibcon#read 4, iclass 20, count 0 2006.238.07:52:59.61#ibcon#about to read 5, iclass 20, count 0 2006.238.07:52:59.61#ibcon#read 5, iclass 20, count 0 2006.238.07:52:59.61#ibcon#about to read 6, iclass 20, count 0 2006.238.07:52:59.61#ibcon#read 6, iclass 20, count 0 2006.238.07:52:59.61#ibcon#end of sib2, iclass 20, count 0 2006.238.07:52:59.61#ibcon#*after write, iclass 20, count 0 2006.238.07:52:59.61#ibcon#*before return 0, iclass 20, count 0 2006.238.07:52:59.61#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:52:59.61#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:52:59.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:52:59.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:52:59.61$vc4f8/valo=6,772.99 2006.238.07:52:59.61#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.07:52:59.61#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.07:52:59.61#ibcon#ireg 17 cls_cnt 0 2006.238.07:52:59.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:52:59.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:52:59.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:52:59.61#ibcon#enter wrdev, iclass 22, count 0 2006.238.07:52:59.61#ibcon#first serial, iclass 22, count 0 2006.238.07:52:59.61#ibcon#enter sib2, iclass 22, count 0 2006.238.07:52:59.61#ibcon#flushed, iclass 22, count 0 2006.238.07:52:59.61#ibcon#about to write, iclass 22, count 0 2006.238.07:52:59.61#ibcon#wrote, iclass 22, count 0 2006.238.07:52:59.61#ibcon#about to read 3, iclass 22, count 0 2006.238.07:52:59.63#ibcon#read 3, iclass 22, count 0 2006.238.07:52:59.63#ibcon#about to read 4, iclass 22, count 0 2006.238.07:52:59.63#ibcon#read 4, iclass 22, count 0 2006.238.07:52:59.63#ibcon#about to read 5, iclass 22, count 0 2006.238.07:52:59.63#ibcon#read 5, iclass 22, count 0 2006.238.07:52:59.63#ibcon#about to read 6, iclass 22, count 0 2006.238.07:52:59.63#ibcon#read 6, iclass 22, count 0 2006.238.07:52:59.63#ibcon#end of sib2, iclass 22, count 0 2006.238.07:52:59.63#ibcon#*mode == 0, iclass 22, count 0 2006.238.07:52:59.63#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.07:52:59.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:52:59.63#ibcon#*before write, iclass 22, count 0 2006.238.07:52:59.63#ibcon#enter sib2, iclass 22, count 0 2006.238.07:52:59.63#ibcon#flushed, iclass 22, count 0 2006.238.07:52:59.63#ibcon#about to write, iclass 22, count 0 2006.238.07:52:59.63#ibcon#wrote, iclass 22, count 0 2006.238.07:52:59.63#ibcon#about to read 3, iclass 22, count 0 2006.238.07:52:59.67#ibcon#read 3, iclass 22, count 0 2006.238.07:52:59.67#ibcon#about to read 4, iclass 22, count 0 2006.238.07:52:59.67#ibcon#read 4, iclass 22, count 0 2006.238.07:52:59.67#ibcon#about to read 5, iclass 22, count 0 2006.238.07:52:59.67#ibcon#read 5, iclass 22, count 0 2006.238.07:52:59.67#ibcon#about to read 6, iclass 22, count 0 2006.238.07:52:59.67#ibcon#read 6, iclass 22, count 0 2006.238.07:52:59.67#ibcon#end of sib2, iclass 22, count 0 2006.238.07:52:59.67#ibcon#*after write, iclass 22, count 0 2006.238.07:52:59.67#ibcon#*before return 0, iclass 22, count 0 2006.238.07:52:59.67#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:52:59.67#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:52:59.67#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.07:52:59.67#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.07:52:59.67$vc4f8/va=6,7 2006.238.07:52:59.67#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.238.07:52:59.67#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.238.07:52:59.67#ibcon#ireg 11 cls_cnt 2 2006.238.07:52:59.67#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:52:59.73#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:52:59.73#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:52:59.73#ibcon#enter wrdev, iclass 24, count 2 2006.238.07:52:59.73#ibcon#first serial, iclass 24, count 2 2006.238.07:52:59.73#ibcon#enter sib2, iclass 24, count 2 2006.238.07:52:59.73#ibcon#flushed, iclass 24, count 2 2006.238.07:52:59.73#ibcon#about to write, iclass 24, count 2 2006.238.07:52:59.73#ibcon#wrote, iclass 24, count 2 2006.238.07:52:59.73#ibcon#about to read 3, iclass 24, count 2 2006.238.07:52:59.75#ibcon#read 3, iclass 24, count 2 2006.238.07:52:59.75#ibcon#about to read 4, iclass 24, count 2 2006.238.07:52:59.75#ibcon#read 4, iclass 24, count 2 2006.238.07:52:59.75#ibcon#about to read 5, iclass 24, count 2 2006.238.07:52:59.75#ibcon#read 5, iclass 24, count 2 2006.238.07:52:59.75#ibcon#about to read 6, iclass 24, count 2 2006.238.07:52:59.75#ibcon#read 6, iclass 24, count 2 2006.238.07:52:59.75#ibcon#end of sib2, iclass 24, count 2 2006.238.07:52:59.75#ibcon#*mode == 0, iclass 24, count 2 2006.238.07:52:59.75#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.238.07:52:59.75#ibcon#[25=AT06-07\r\n] 2006.238.07:52:59.75#ibcon#*before write, iclass 24, count 2 2006.238.07:52:59.75#ibcon#enter sib2, iclass 24, count 2 2006.238.07:52:59.75#ibcon#flushed, iclass 24, count 2 2006.238.07:52:59.75#ibcon#about to write, iclass 24, count 2 2006.238.07:52:59.75#ibcon#wrote, iclass 24, count 2 2006.238.07:52:59.75#ibcon#about to read 3, iclass 24, count 2 2006.238.07:52:59.78#ibcon#read 3, iclass 24, count 2 2006.238.07:52:59.78#ibcon#about to read 4, iclass 24, count 2 2006.238.07:52:59.78#ibcon#read 4, iclass 24, count 2 2006.238.07:52:59.78#ibcon#about to read 5, iclass 24, count 2 2006.238.07:52:59.78#ibcon#read 5, iclass 24, count 2 2006.238.07:52:59.78#ibcon#about to read 6, iclass 24, count 2 2006.238.07:52:59.78#ibcon#read 6, iclass 24, count 2 2006.238.07:52:59.78#ibcon#end of sib2, iclass 24, count 2 2006.238.07:52:59.78#ibcon#*after write, iclass 24, count 2 2006.238.07:52:59.78#ibcon#*before return 0, iclass 24, count 2 2006.238.07:52:59.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:52:59.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.238.07:52:59.78#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.238.07:52:59.78#ibcon#ireg 7 cls_cnt 0 2006.238.07:52:59.78#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:52:59.90#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:52:59.90#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:52:59.90#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:52:59.90#ibcon#first serial, iclass 24, count 0 2006.238.07:52:59.90#ibcon#enter sib2, iclass 24, count 0 2006.238.07:52:59.90#ibcon#flushed, iclass 24, count 0 2006.238.07:52:59.90#ibcon#about to write, iclass 24, count 0 2006.238.07:52:59.90#ibcon#wrote, iclass 24, count 0 2006.238.07:52:59.90#ibcon#about to read 3, iclass 24, count 0 2006.238.07:52:59.92#ibcon#read 3, iclass 24, count 0 2006.238.07:52:59.92#ibcon#about to read 4, iclass 24, count 0 2006.238.07:52:59.92#ibcon#read 4, iclass 24, count 0 2006.238.07:52:59.92#ibcon#about to read 5, iclass 24, count 0 2006.238.07:52:59.92#ibcon#read 5, iclass 24, count 0 2006.238.07:52:59.92#ibcon#about to read 6, iclass 24, count 0 2006.238.07:52:59.92#ibcon#read 6, iclass 24, count 0 2006.238.07:52:59.92#ibcon#end of sib2, iclass 24, count 0 2006.238.07:52:59.92#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:52:59.92#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:52:59.92#ibcon#[25=USB\r\n] 2006.238.07:52:59.92#ibcon#*before write, iclass 24, count 0 2006.238.07:52:59.92#ibcon#enter sib2, iclass 24, count 0 2006.238.07:52:59.92#ibcon#flushed, iclass 24, count 0 2006.238.07:52:59.92#ibcon#about to write, iclass 24, count 0 2006.238.07:52:59.92#ibcon#wrote, iclass 24, count 0 2006.238.07:52:59.92#ibcon#about to read 3, iclass 24, count 0 2006.238.07:52:59.95#ibcon#read 3, iclass 24, count 0 2006.238.07:52:59.95#ibcon#about to read 4, iclass 24, count 0 2006.238.07:52:59.95#ibcon#read 4, iclass 24, count 0 2006.238.07:52:59.95#ibcon#about to read 5, iclass 24, count 0 2006.238.07:52:59.95#ibcon#read 5, iclass 24, count 0 2006.238.07:52:59.95#ibcon#about to read 6, iclass 24, count 0 2006.238.07:52:59.95#ibcon#read 6, iclass 24, count 0 2006.238.07:52:59.95#ibcon#end of sib2, iclass 24, count 0 2006.238.07:52:59.95#ibcon#*after write, iclass 24, count 0 2006.238.07:52:59.95#ibcon#*before return 0, iclass 24, count 0 2006.238.07:52:59.95#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:52:59.95#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.238.07:52:59.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:52:59.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:52:59.95$vc4f8/valo=7,832.99 2006.238.07:52:59.95#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.07:52:59.95#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.07:52:59.95#ibcon#ireg 17 cls_cnt 0 2006.238.07:52:59.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:52:59.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:52:59.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:52:59.95#ibcon#enter wrdev, iclass 26, count 0 2006.238.07:52:59.95#ibcon#first serial, iclass 26, count 0 2006.238.07:52:59.95#ibcon#enter sib2, iclass 26, count 0 2006.238.07:52:59.95#ibcon#flushed, iclass 26, count 0 2006.238.07:52:59.95#ibcon#about to write, iclass 26, count 0 2006.238.07:52:59.95#ibcon#wrote, iclass 26, count 0 2006.238.07:52:59.95#ibcon#about to read 3, iclass 26, count 0 2006.238.07:52:59.97#ibcon#read 3, iclass 26, count 0 2006.238.07:52:59.97#ibcon#about to read 4, iclass 26, count 0 2006.238.07:52:59.97#ibcon#read 4, iclass 26, count 0 2006.238.07:52:59.97#ibcon#about to read 5, iclass 26, count 0 2006.238.07:52:59.97#ibcon#read 5, iclass 26, count 0 2006.238.07:52:59.97#ibcon#about to read 6, iclass 26, count 0 2006.238.07:52:59.97#ibcon#read 6, iclass 26, count 0 2006.238.07:52:59.97#ibcon#end of sib2, iclass 26, count 0 2006.238.07:52:59.97#ibcon#*mode == 0, iclass 26, count 0 2006.238.07:52:59.97#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.07:52:59.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:52:59.97#ibcon#*before write, iclass 26, count 0 2006.238.07:52:59.97#ibcon#enter sib2, iclass 26, count 0 2006.238.07:52:59.97#ibcon#flushed, iclass 26, count 0 2006.238.07:52:59.97#ibcon#about to write, iclass 26, count 0 2006.238.07:52:59.97#ibcon#wrote, iclass 26, count 0 2006.238.07:52:59.97#ibcon#about to read 3, iclass 26, count 0 2006.238.07:53:00.01#ibcon#read 3, iclass 26, count 0 2006.238.07:53:00.01#ibcon#about to read 4, iclass 26, count 0 2006.238.07:53:00.01#ibcon#read 4, iclass 26, count 0 2006.238.07:53:00.01#ibcon#about to read 5, iclass 26, count 0 2006.238.07:53:00.01#ibcon#read 5, iclass 26, count 0 2006.238.07:53:00.01#ibcon#about to read 6, iclass 26, count 0 2006.238.07:53:00.01#ibcon#read 6, iclass 26, count 0 2006.238.07:53:00.01#ibcon#end of sib2, iclass 26, count 0 2006.238.07:53:00.01#ibcon#*after write, iclass 26, count 0 2006.238.07:53:00.01#ibcon#*before return 0, iclass 26, count 0 2006.238.07:53:00.01#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:53:00.01#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.07:53:00.01#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.07:53:00.01#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.07:53:00.01$vc4f8/va=7,7 2006.238.07:53:00.01#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.07:53:00.01#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.07:53:00.01#ibcon#ireg 11 cls_cnt 2 2006.238.07:53:00.01#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:53:00.07#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:53:00.07#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:53:00.07#ibcon#enter wrdev, iclass 28, count 2 2006.238.07:53:00.07#ibcon#first serial, iclass 28, count 2 2006.238.07:53:00.07#ibcon#enter sib2, iclass 28, count 2 2006.238.07:53:00.07#ibcon#flushed, iclass 28, count 2 2006.238.07:53:00.07#ibcon#about to write, iclass 28, count 2 2006.238.07:53:00.07#ibcon#wrote, iclass 28, count 2 2006.238.07:53:00.07#ibcon#about to read 3, iclass 28, count 2 2006.238.07:53:00.09#ibcon#read 3, iclass 28, count 2 2006.238.07:53:00.09#ibcon#about to read 4, iclass 28, count 2 2006.238.07:53:00.09#ibcon#read 4, iclass 28, count 2 2006.238.07:53:00.09#ibcon#about to read 5, iclass 28, count 2 2006.238.07:53:00.09#ibcon#read 5, iclass 28, count 2 2006.238.07:53:00.09#ibcon#about to read 6, iclass 28, count 2 2006.238.07:53:00.09#ibcon#read 6, iclass 28, count 2 2006.238.07:53:00.09#ibcon#end of sib2, iclass 28, count 2 2006.238.07:53:00.09#ibcon#*mode == 0, iclass 28, count 2 2006.238.07:53:00.09#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.07:53:00.09#ibcon#[25=AT07-07\r\n] 2006.238.07:53:00.09#ibcon#*before write, iclass 28, count 2 2006.238.07:53:00.09#ibcon#enter sib2, iclass 28, count 2 2006.238.07:53:00.09#ibcon#flushed, iclass 28, count 2 2006.238.07:53:00.09#ibcon#about to write, iclass 28, count 2 2006.238.07:53:00.09#ibcon#wrote, iclass 28, count 2 2006.238.07:53:00.09#ibcon#about to read 3, iclass 28, count 2 2006.238.07:53:00.12#ibcon#read 3, iclass 28, count 2 2006.238.07:53:00.12#ibcon#about to read 4, iclass 28, count 2 2006.238.07:53:00.12#ibcon#read 4, iclass 28, count 2 2006.238.07:53:00.12#ibcon#about to read 5, iclass 28, count 2 2006.238.07:53:00.12#ibcon#read 5, iclass 28, count 2 2006.238.07:53:00.12#ibcon#about to read 6, iclass 28, count 2 2006.238.07:53:00.12#ibcon#read 6, iclass 28, count 2 2006.238.07:53:00.12#ibcon#end of sib2, iclass 28, count 2 2006.238.07:53:00.12#ibcon#*after write, iclass 28, count 2 2006.238.07:53:00.12#ibcon#*before return 0, iclass 28, count 2 2006.238.07:53:00.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:53:00.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.07:53:00.12#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.07:53:00.12#ibcon#ireg 7 cls_cnt 0 2006.238.07:53:00.12#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:53:00.24#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:53:00.24#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:53:00.24#ibcon#enter wrdev, iclass 28, count 0 2006.238.07:53:00.24#ibcon#first serial, iclass 28, count 0 2006.238.07:53:00.24#ibcon#enter sib2, iclass 28, count 0 2006.238.07:53:00.24#ibcon#flushed, iclass 28, count 0 2006.238.07:53:00.24#ibcon#about to write, iclass 28, count 0 2006.238.07:53:00.24#ibcon#wrote, iclass 28, count 0 2006.238.07:53:00.24#ibcon#about to read 3, iclass 28, count 0 2006.238.07:53:00.26#ibcon#read 3, iclass 28, count 0 2006.238.07:53:00.26#ibcon#about to read 4, iclass 28, count 0 2006.238.07:53:00.26#ibcon#read 4, iclass 28, count 0 2006.238.07:53:00.26#ibcon#about to read 5, iclass 28, count 0 2006.238.07:53:00.26#ibcon#read 5, iclass 28, count 0 2006.238.07:53:00.26#ibcon#about to read 6, iclass 28, count 0 2006.238.07:53:00.26#ibcon#read 6, iclass 28, count 0 2006.238.07:53:00.26#ibcon#end of sib2, iclass 28, count 0 2006.238.07:53:00.26#ibcon#*mode == 0, iclass 28, count 0 2006.238.07:53:00.26#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.07:53:00.26#ibcon#[25=USB\r\n] 2006.238.07:53:00.26#ibcon#*before write, iclass 28, count 0 2006.238.07:53:00.26#ibcon#enter sib2, iclass 28, count 0 2006.238.07:53:00.26#ibcon#flushed, iclass 28, count 0 2006.238.07:53:00.26#ibcon#about to write, iclass 28, count 0 2006.238.07:53:00.26#ibcon#wrote, iclass 28, count 0 2006.238.07:53:00.26#ibcon#about to read 3, iclass 28, count 0 2006.238.07:53:00.29#ibcon#read 3, iclass 28, count 0 2006.238.07:53:00.29#ibcon#about to read 4, iclass 28, count 0 2006.238.07:53:00.29#ibcon#read 4, iclass 28, count 0 2006.238.07:53:00.29#ibcon#about to read 5, iclass 28, count 0 2006.238.07:53:00.29#ibcon#read 5, iclass 28, count 0 2006.238.07:53:00.29#ibcon#about to read 6, iclass 28, count 0 2006.238.07:53:00.29#ibcon#read 6, iclass 28, count 0 2006.238.07:53:00.29#ibcon#end of sib2, iclass 28, count 0 2006.238.07:53:00.29#ibcon#*after write, iclass 28, count 0 2006.238.07:53:00.29#ibcon#*before return 0, iclass 28, count 0 2006.238.07:53:00.29#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:53:00.29#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.07:53:00.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.07:53:00.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.07:53:00.29$vc4f8/valo=8,852.99 2006.238.07:53:00.29#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.07:53:00.29#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.07:53:00.29#ibcon#ireg 17 cls_cnt 0 2006.238.07:53:00.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:53:00.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:53:00.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:53:00.29#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:53:00.29#ibcon#first serial, iclass 30, count 0 2006.238.07:53:00.29#ibcon#enter sib2, iclass 30, count 0 2006.238.07:53:00.29#ibcon#flushed, iclass 30, count 0 2006.238.07:53:00.29#ibcon#about to write, iclass 30, count 0 2006.238.07:53:00.29#ibcon#wrote, iclass 30, count 0 2006.238.07:53:00.29#ibcon#about to read 3, iclass 30, count 0 2006.238.07:53:00.31#ibcon#read 3, iclass 30, count 0 2006.238.07:53:00.31#ibcon#about to read 4, iclass 30, count 0 2006.238.07:53:00.31#ibcon#read 4, iclass 30, count 0 2006.238.07:53:00.31#ibcon#about to read 5, iclass 30, count 0 2006.238.07:53:00.31#ibcon#read 5, iclass 30, count 0 2006.238.07:53:00.31#ibcon#about to read 6, iclass 30, count 0 2006.238.07:53:00.31#ibcon#read 6, iclass 30, count 0 2006.238.07:53:00.31#ibcon#end of sib2, iclass 30, count 0 2006.238.07:53:00.31#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:53:00.31#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:53:00.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:53:00.31#ibcon#*before write, iclass 30, count 0 2006.238.07:53:00.31#ibcon#enter sib2, iclass 30, count 0 2006.238.07:53:00.31#ibcon#flushed, iclass 30, count 0 2006.238.07:53:00.31#ibcon#about to write, iclass 30, count 0 2006.238.07:53:00.31#ibcon#wrote, iclass 30, count 0 2006.238.07:53:00.31#ibcon#about to read 3, iclass 30, count 0 2006.238.07:53:00.35#ibcon#read 3, iclass 30, count 0 2006.238.07:53:00.35#ibcon#about to read 4, iclass 30, count 0 2006.238.07:53:00.35#ibcon#read 4, iclass 30, count 0 2006.238.07:53:00.35#ibcon#about to read 5, iclass 30, count 0 2006.238.07:53:00.35#ibcon#read 5, iclass 30, count 0 2006.238.07:53:00.35#ibcon#about to read 6, iclass 30, count 0 2006.238.07:53:00.35#ibcon#read 6, iclass 30, count 0 2006.238.07:53:00.35#ibcon#end of sib2, iclass 30, count 0 2006.238.07:53:00.35#ibcon#*after write, iclass 30, count 0 2006.238.07:53:00.35#ibcon#*before return 0, iclass 30, count 0 2006.238.07:53:00.35#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:53:00.35#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:53:00.35#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:53:00.35#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:53:00.35$vc4f8/va=8,7 2006.238.07:53:00.35#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.238.07:53:00.35#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.238.07:53:00.35#ibcon#ireg 11 cls_cnt 2 2006.238.07:53:00.35#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:53:00.41#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:53:00.41#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:53:00.41#ibcon#enter wrdev, iclass 32, count 2 2006.238.07:53:00.41#ibcon#first serial, iclass 32, count 2 2006.238.07:53:00.41#ibcon#enter sib2, iclass 32, count 2 2006.238.07:53:00.41#ibcon#flushed, iclass 32, count 2 2006.238.07:53:00.41#ibcon#about to write, iclass 32, count 2 2006.238.07:53:00.41#ibcon#wrote, iclass 32, count 2 2006.238.07:53:00.41#ibcon#about to read 3, iclass 32, count 2 2006.238.07:53:00.43#ibcon#read 3, iclass 32, count 2 2006.238.07:53:00.43#ibcon#about to read 4, iclass 32, count 2 2006.238.07:53:00.43#ibcon#read 4, iclass 32, count 2 2006.238.07:53:00.43#ibcon#about to read 5, iclass 32, count 2 2006.238.07:53:00.43#ibcon#read 5, iclass 32, count 2 2006.238.07:53:00.43#ibcon#about to read 6, iclass 32, count 2 2006.238.07:53:00.43#ibcon#read 6, iclass 32, count 2 2006.238.07:53:00.43#ibcon#end of sib2, iclass 32, count 2 2006.238.07:53:00.43#ibcon#*mode == 0, iclass 32, count 2 2006.238.07:53:00.43#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.238.07:53:00.43#ibcon#[25=AT08-07\r\n] 2006.238.07:53:00.43#ibcon#*before write, iclass 32, count 2 2006.238.07:53:00.43#ibcon#enter sib2, iclass 32, count 2 2006.238.07:53:00.43#ibcon#flushed, iclass 32, count 2 2006.238.07:53:00.43#ibcon#about to write, iclass 32, count 2 2006.238.07:53:00.43#ibcon#wrote, iclass 32, count 2 2006.238.07:53:00.43#ibcon#about to read 3, iclass 32, count 2 2006.238.07:53:00.46#ibcon#read 3, iclass 32, count 2 2006.238.07:53:00.46#ibcon#about to read 4, iclass 32, count 2 2006.238.07:53:00.46#ibcon#read 4, iclass 32, count 2 2006.238.07:53:00.46#ibcon#about to read 5, iclass 32, count 2 2006.238.07:53:00.46#ibcon#read 5, iclass 32, count 2 2006.238.07:53:00.46#ibcon#about to read 6, iclass 32, count 2 2006.238.07:53:00.46#ibcon#read 6, iclass 32, count 2 2006.238.07:53:00.46#ibcon#end of sib2, iclass 32, count 2 2006.238.07:53:00.46#ibcon#*after write, iclass 32, count 2 2006.238.07:53:00.46#ibcon#*before return 0, iclass 32, count 2 2006.238.07:53:00.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:53:00.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.238.07:53:00.46#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.238.07:53:00.46#ibcon#ireg 7 cls_cnt 0 2006.238.07:53:00.46#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:53:00.58#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:53:00.58#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:53:00.58#ibcon#enter wrdev, iclass 32, count 0 2006.238.07:53:00.58#ibcon#first serial, iclass 32, count 0 2006.238.07:53:00.58#ibcon#enter sib2, iclass 32, count 0 2006.238.07:53:00.58#ibcon#flushed, iclass 32, count 0 2006.238.07:53:00.58#ibcon#about to write, iclass 32, count 0 2006.238.07:53:00.58#ibcon#wrote, iclass 32, count 0 2006.238.07:53:00.58#ibcon#about to read 3, iclass 32, count 0 2006.238.07:53:00.60#ibcon#read 3, iclass 32, count 0 2006.238.07:53:00.60#ibcon#about to read 4, iclass 32, count 0 2006.238.07:53:00.60#ibcon#read 4, iclass 32, count 0 2006.238.07:53:00.60#ibcon#about to read 5, iclass 32, count 0 2006.238.07:53:00.60#ibcon#read 5, iclass 32, count 0 2006.238.07:53:00.60#ibcon#about to read 6, iclass 32, count 0 2006.238.07:53:00.60#ibcon#read 6, iclass 32, count 0 2006.238.07:53:00.60#ibcon#end of sib2, iclass 32, count 0 2006.238.07:53:00.60#ibcon#*mode == 0, iclass 32, count 0 2006.238.07:53:00.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.07:53:00.60#ibcon#[25=USB\r\n] 2006.238.07:53:00.60#ibcon#*before write, iclass 32, count 0 2006.238.07:53:00.60#ibcon#enter sib2, iclass 32, count 0 2006.238.07:53:00.60#ibcon#flushed, iclass 32, count 0 2006.238.07:53:00.60#ibcon#about to write, iclass 32, count 0 2006.238.07:53:00.60#ibcon#wrote, iclass 32, count 0 2006.238.07:53:00.60#ibcon#about to read 3, iclass 32, count 0 2006.238.07:53:00.63#ibcon#read 3, iclass 32, count 0 2006.238.07:53:00.63#ibcon#about to read 4, iclass 32, count 0 2006.238.07:53:00.63#ibcon#read 4, iclass 32, count 0 2006.238.07:53:00.63#ibcon#about to read 5, iclass 32, count 0 2006.238.07:53:00.63#ibcon#read 5, iclass 32, count 0 2006.238.07:53:00.63#ibcon#about to read 6, iclass 32, count 0 2006.238.07:53:00.63#ibcon#read 6, iclass 32, count 0 2006.238.07:53:00.63#ibcon#end of sib2, iclass 32, count 0 2006.238.07:53:00.63#ibcon#*after write, iclass 32, count 0 2006.238.07:53:00.63#ibcon#*before return 0, iclass 32, count 0 2006.238.07:53:00.63#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:53:00.63#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.238.07:53:00.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.07:53:00.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.07:53:00.63$vc4f8/vblo=1,632.99 2006.238.07:53:00.63#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.238.07:53:00.63#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.238.07:53:00.63#ibcon#ireg 17 cls_cnt 0 2006.238.07:53:00.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:53:00.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:53:00.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:53:00.63#ibcon#enter wrdev, iclass 34, count 0 2006.238.07:53:00.63#ibcon#first serial, iclass 34, count 0 2006.238.07:53:00.63#ibcon#enter sib2, iclass 34, count 0 2006.238.07:53:00.63#ibcon#flushed, iclass 34, count 0 2006.238.07:53:00.63#ibcon#about to write, iclass 34, count 0 2006.238.07:53:00.63#ibcon#wrote, iclass 34, count 0 2006.238.07:53:00.63#ibcon#about to read 3, iclass 34, count 0 2006.238.07:53:00.65#ibcon#read 3, iclass 34, count 0 2006.238.07:53:00.65#ibcon#about to read 4, iclass 34, count 0 2006.238.07:53:00.65#ibcon#read 4, iclass 34, count 0 2006.238.07:53:00.65#ibcon#about to read 5, iclass 34, count 0 2006.238.07:53:00.65#ibcon#read 5, iclass 34, count 0 2006.238.07:53:00.65#ibcon#about to read 6, iclass 34, count 0 2006.238.07:53:00.65#ibcon#read 6, iclass 34, count 0 2006.238.07:53:00.65#ibcon#end of sib2, iclass 34, count 0 2006.238.07:53:00.65#ibcon#*mode == 0, iclass 34, count 0 2006.238.07:53:00.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.07:53:00.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:53:00.65#ibcon#*before write, iclass 34, count 0 2006.238.07:53:00.65#ibcon#enter sib2, iclass 34, count 0 2006.238.07:53:00.65#ibcon#flushed, iclass 34, count 0 2006.238.07:53:00.65#ibcon#about to write, iclass 34, count 0 2006.238.07:53:00.65#ibcon#wrote, iclass 34, count 0 2006.238.07:53:00.65#ibcon#about to read 3, iclass 34, count 0 2006.238.07:53:00.69#ibcon#read 3, iclass 34, count 0 2006.238.07:53:00.69#ibcon#about to read 4, iclass 34, count 0 2006.238.07:53:00.69#ibcon#read 4, iclass 34, count 0 2006.238.07:53:00.69#ibcon#about to read 5, iclass 34, count 0 2006.238.07:53:00.69#ibcon#read 5, iclass 34, count 0 2006.238.07:53:00.69#ibcon#about to read 6, iclass 34, count 0 2006.238.07:53:00.69#ibcon#read 6, iclass 34, count 0 2006.238.07:53:00.69#ibcon#end of sib2, iclass 34, count 0 2006.238.07:53:00.69#ibcon#*after write, iclass 34, count 0 2006.238.07:53:00.69#ibcon#*before return 0, iclass 34, count 0 2006.238.07:53:00.69#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:53:00.69#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.238.07:53:00.69#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.07:53:00.69#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.07:53:00.69$vc4f8/vb=1,4 2006.238.07:53:00.69#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.238.07:53:00.69#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.238.07:53:00.69#ibcon#ireg 11 cls_cnt 2 2006.238.07:53:00.69#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:53:00.69#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:53:00.69#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:53:00.69#ibcon#enter wrdev, iclass 36, count 2 2006.238.07:53:00.69#ibcon#first serial, iclass 36, count 2 2006.238.07:53:00.69#ibcon#enter sib2, iclass 36, count 2 2006.238.07:53:00.69#ibcon#flushed, iclass 36, count 2 2006.238.07:53:00.69#ibcon#about to write, iclass 36, count 2 2006.238.07:53:00.69#ibcon#wrote, iclass 36, count 2 2006.238.07:53:00.69#ibcon#about to read 3, iclass 36, count 2 2006.238.07:53:00.71#ibcon#read 3, iclass 36, count 2 2006.238.07:53:00.71#ibcon#about to read 4, iclass 36, count 2 2006.238.07:53:00.71#ibcon#read 4, iclass 36, count 2 2006.238.07:53:00.71#ibcon#about to read 5, iclass 36, count 2 2006.238.07:53:00.71#ibcon#read 5, iclass 36, count 2 2006.238.07:53:00.71#ibcon#about to read 6, iclass 36, count 2 2006.238.07:53:00.71#ibcon#read 6, iclass 36, count 2 2006.238.07:53:00.71#ibcon#end of sib2, iclass 36, count 2 2006.238.07:53:00.71#ibcon#*mode == 0, iclass 36, count 2 2006.238.07:53:00.71#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.238.07:53:00.71#ibcon#[27=AT01-04\r\n] 2006.238.07:53:00.71#ibcon#*before write, iclass 36, count 2 2006.238.07:53:00.71#ibcon#enter sib2, iclass 36, count 2 2006.238.07:53:00.71#ibcon#flushed, iclass 36, count 2 2006.238.07:53:00.71#ibcon#about to write, iclass 36, count 2 2006.238.07:53:00.71#ibcon#wrote, iclass 36, count 2 2006.238.07:53:00.71#ibcon#about to read 3, iclass 36, count 2 2006.238.07:53:00.74#ibcon#read 3, iclass 36, count 2 2006.238.07:53:00.74#ibcon#about to read 4, iclass 36, count 2 2006.238.07:53:00.74#ibcon#read 4, iclass 36, count 2 2006.238.07:53:00.74#ibcon#about to read 5, iclass 36, count 2 2006.238.07:53:00.74#ibcon#read 5, iclass 36, count 2 2006.238.07:53:00.74#ibcon#about to read 6, iclass 36, count 2 2006.238.07:53:00.74#ibcon#read 6, iclass 36, count 2 2006.238.07:53:00.74#ibcon#end of sib2, iclass 36, count 2 2006.238.07:53:00.74#ibcon#*after write, iclass 36, count 2 2006.238.07:53:00.74#ibcon#*before return 0, iclass 36, count 2 2006.238.07:53:00.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:53:00.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.238.07:53:00.74#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.238.07:53:00.74#ibcon#ireg 7 cls_cnt 0 2006.238.07:53:00.74#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:53:00.86#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:53:00.86#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:53:00.86#ibcon#enter wrdev, iclass 36, count 0 2006.238.07:53:00.86#ibcon#first serial, iclass 36, count 0 2006.238.07:53:00.86#ibcon#enter sib2, iclass 36, count 0 2006.238.07:53:00.86#ibcon#flushed, iclass 36, count 0 2006.238.07:53:00.86#ibcon#about to write, iclass 36, count 0 2006.238.07:53:00.86#ibcon#wrote, iclass 36, count 0 2006.238.07:53:00.86#ibcon#about to read 3, iclass 36, count 0 2006.238.07:53:00.88#ibcon#read 3, iclass 36, count 0 2006.238.07:53:00.88#ibcon#about to read 4, iclass 36, count 0 2006.238.07:53:00.88#ibcon#read 4, iclass 36, count 0 2006.238.07:53:00.88#ibcon#about to read 5, iclass 36, count 0 2006.238.07:53:00.88#ibcon#read 5, iclass 36, count 0 2006.238.07:53:00.88#ibcon#about to read 6, iclass 36, count 0 2006.238.07:53:00.88#ibcon#read 6, iclass 36, count 0 2006.238.07:53:00.88#ibcon#end of sib2, iclass 36, count 0 2006.238.07:53:00.88#ibcon#*mode == 0, iclass 36, count 0 2006.238.07:53:00.88#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.07:53:00.88#ibcon#[27=USB\r\n] 2006.238.07:53:00.88#ibcon#*before write, iclass 36, count 0 2006.238.07:53:00.88#ibcon#enter sib2, iclass 36, count 0 2006.238.07:53:00.88#ibcon#flushed, iclass 36, count 0 2006.238.07:53:00.88#ibcon#about to write, iclass 36, count 0 2006.238.07:53:00.88#ibcon#wrote, iclass 36, count 0 2006.238.07:53:00.88#ibcon#about to read 3, iclass 36, count 0 2006.238.07:53:00.91#ibcon#read 3, iclass 36, count 0 2006.238.07:53:00.91#ibcon#about to read 4, iclass 36, count 0 2006.238.07:53:00.91#ibcon#read 4, iclass 36, count 0 2006.238.07:53:00.91#ibcon#about to read 5, iclass 36, count 0 2006.238.07:53:00.91#ibcon#read 5, iclass 36, count 0 2006.238.07:53:00.91#ibcon#about to read 6, iclass 36, count 0 2006.238.07:53:00.91#ibcon#read 6, iclass 36, count 0 2006.238.07:53:00.91#ibcon#end of sib2, iclass 36, count 0 2006.238.07:53:00.91#ibcon#*after write, iclass 36, count 0 2006.238.07:53:00.91#ibcon#*before return 0, iclass 36, count 0 2006.238.07:53:00.91#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:53:00.91#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.238.07:53:00.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.07:53:00.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.07:53:00.91$vc4f8/vblo=2,640.99 2006.238.07:53:00.91#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.238.07:53:00.91#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.238.07:53:00.91#ibcon#ireg 17 cls_cnt 0 2006.238.07:53:00.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:53:00.91#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:53:00.91#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:53:00.91#ibcon#enter wrdev, iclass 38, count 0 2006.238.07:53:00.91#ibcon#first serial, iclass 38, count 0 2006.238.07:53:00.91#ibcon#enter sib2, iclass 38, count 0 2006.238.07:53:00.91#ibcon#flushed, iclass 38, count 0 2006.238.07:53:00.91#ibcon#about to write, iclass 38, count 0 2006.238.07:53:00.91#ibcon#wrote, iclass 38, count 0 2006.238.07:53:00.91#ibcon#about to read 3, iclass 38, count 0 2006.238.07:53:00.93#ibcon#read 3, iclass 38, count 0 2006.238.07:53:00.93#ibcon#about to read 4, iclass 38, count 0 2006.238.07:53:00.93#ibcon#read 4, iclass 38, count 0 2006.238.07:53:00.93#ibcon#about to read 5, iclass 38, count 0 2006.238.07:53:00.93#ibcon#read 5, iclass 38, count 0 2006.238.07:53:00.93#ibcon#about to read 6, iclass 38, count 0 2006.238.07:53:00.93#ibcon#read 6, iclass 38, count 0 2006.238.07:53:00.93#ibcon#end of sib2, iclass 38, count 0 2006.238.07:53:00.93#ibcon#*mode == 0, iclass 38, count 0 2006.238.07:53:00.93#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.07:53:00.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:53:00.93#ibcon#*before write, iclass 38, count 0 2006.238.07:53:00.93#ibcon#enter sib2, iclass 38, count 0 2006.238.07:53:00.93#ibcon#flushed, iclass 38, count 0 2006.238.07:53:00.93#ibcon#about to write, iclass 38, count 0 2006.238.07:53:00.93#ibcon#wrote, iclass 38, count 0 2006.238.07:53:00.93#ibcon#about to read 3, iclass 38, count 0 2006.238.07:53:00.97#ibcon#read 3, iclass 38, count 0 2006.238.07:53:00.97#ibcon#about to read 4, iclass 38, count 0 2006.238.07:53:00.97#ibcon#read 4, iclass 38, count 0 2006.238.07:53:00.97#ibcon#about to read 5, iclass 38, count 0 2006.238.07:53:00.97#ibcon#read 5, iclass 38, count 0 2006.238.07:53:00.97#ibcon#about to read 6, iclass 38, count 0 2006.238.07:53:00.97#ibcon#read 6, iclass 38, count 0 2006.238.07:53:00.97#ibcon#end of sib2, iclass 38, count 0 2006.238.07:53:00.97#ibcon#*after write, iclass 38, count 0 2006.238.07:53:00.97#ibcon#*before return 0, iclass 38, count 0 2006.238.07:53:00.97#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:53:00.97#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.238.07:53:00.97#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.07:53:00.97#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.07:53:00.97$vc4f8/vb=2,4 2006.238.07:53:00.97#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.238.07:53:00.97#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.238.07:53:00.97#ibcon#ireg 11 cls_cnt 2 2006.238.07:53:00.97#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:53:01.03#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:53:01.03#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:53:01.03#ibcon#enter wrdev, iclass 40, count 2 2006.238.07:53:01.03#ibcon#first serial, iclass 40, count 2 2006.238.07:53:01.03#ibcon#enter sib2, iclass 40, count 2 2006.238.07:53:01.03#ibcon#flushed, iclass 40, count 2 2006.238.07:53:01.03#ibcon#about to write, iclass 40, count 2 2006.238.07:53:01.03#ibcon#wrote, iclass 40, count 2 2006.238.07:53:01.03#ibcon#about to read 3, iclass 40, count 2 2006.238.07:53:01.05#ibcon#read 3, iclass 40, count 2 2006.238.07:53:01.05#ibcon#about to read 4, iclass 40, count 2 2006.238.07:53:01.05#ibcon#read 4, iclass 40, count 2 2006.238.07:53:01.05#ibcon#about to read 5, iclass 40, count 2 2006.238.07:53:01.05#ibcon#read 5, iclass 40, count 2 2006.238.07:53:01.05#ibcon#about to read 6, iclass 40, count 2 2006.238.07:53:01.05#ibcon#read 6, iclass 40, count 2 2006.238.07:53:01.05#ibcon#end of sib2, iclass 40, count 2 2006.238.07:53:01.05#ibcon#*mode == 0, iclass 40, count 2 2006.238.07:53:01.05#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.238.07:53:01.05#ibcon#[27=AT02-04\r\n] 2006.238.07:53:01.05#ibcon#*before write, iclass 40, count 2 2006.238.07:53:01.05#ibcon#enter sib2, iclass 40, count 2 2006.238.07:53:01.05#ibcon#flushed, iclass 40, count 2 2006.238.07:53:01.05#ibcon#about to write, iclass 40, count 2 2006.238.07:53:01.05#ibcon#wrote, iclass 40, count 2 2006.238.07:53:01.05#ibcon#about to read 3, iclass 40, count 2 2006.238.07:53:01.09#ibcon#read 3, iclass 40, count 2 2006.238.07:53:01.09#ibcon#about to read 4, iclass 40, count 2 2006.238.07:53:01.09#ibcon#read 4, iclass 40, count 2 2006.238.07:53:01.09#ibcon#about to read 5, iclass 40, count 2 2006.238.07:53:01.09#ibcon#read 5, iclass 40, count 2 2006.238.07:53:01.09#ibcon#about to read 6, iclass 40, count 2 2006.238.07:53:01.09#ibcon#read 6, iclass 40, count 2 2006.238.07:53:01.09#ibcon#end of sib2, iclass 40, count 2 2006.238.07:53:01.09#ibcon#*after write, iclass 40, count 2 2006.238.07:53:01.09#ibcon#*before return 0, iclass 40, count 2 2006.238.07:53:01.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:53:01.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.238.07:53:01.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.238.07:53:01.09#ibcon#ireg 7 cls_cnt 0 2006.238.07:53:01.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:53:01.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:53:01.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:53:01.21#ibcon#enter wrdev, iclass 40, count 0 2006.238.07:53:01.21#ibcon#first serial, iclass 40, count 0 2006.238.07:53:01.21#ibcon#enter sib2, iclass 40, count 0 2006.238.07:53:01.21#ibcon#flushed, iclass 40, count 0 2006.238.07:53:01.21#ibcon#about to write, iclass 40, count 0 2006.238.07:53:01.21#ibcon#wrote, iclass 40, count 0 2006.238.07:53:01.21#ibcon#about to read 3, iclass 40, count 0 2006.238.07:53:01.23#ibcon#read 3, iclass 40, count 0 2006.238.07:53:01.23#ibcon#about to read 4, iclass 40, count 0 2006.238.07:53:01.23#ibcon#read 4, iclass 40, count 0 2006.238.07:53:01.23#ibcon#about to read 5, iclass 40, count 0 2006.238.07:53:01.23#ibcon#read 5, iclass 40, count 0 2006.238.07:53:01.23#ibcon#about to read 6, iclass 40, count 0 2006.238.07:53:01.23#ibcon#read 6, iclass 40, count 0 2006.238.07:53:01.23#ibcon#end of sib2, iclass 40, count 0 2006.238.07:53:01.23#ibcon#*mode == 0, iclass 40, count 0 2006.238.07:53:01.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.07:53:01.23#ibcon#[27=USB\r\n] 2006.238.07:53:01.23#ibcon#*before write, iclass 40, count 0 2006.238.07:53:01.23#ibcon#enter sib2, iclass 40, count 0 2006.238.07:53:01.23#ibcon#flushed, iclass 40, count 0 2006.238.07:53:01.23#ibcon#about to write, iclass 40, count 0 2006.238.07:53:01.23#ibcon#wrote, iclass 40, count 0 2006.238.07:53:01.23#ibcon#about to read 3, iclass 40, count 0 2006.238.07:53:01.26#ibcon#read 3, iclass 40, count 0 2006.238.07:53:01.26#ibcon#about to read 4, iclass 40, count 0 2006.238.07:53:01.26#ibcon#read 4, iclass 40, count 0 2006.238.07:53:01.26#ibcon#about to read 5, iclass 40, count 0 2006.238.07:53:01.26#ibcon#read 5, iclass 40, count 0 2006.238.07:53:01.26#ibcon#about to read 6, iclass 40, count 0 2006.238.07:53:01.26#ibcon#read 6, iclass 40, count 0 2006.238.07:53:01.26#ibcon#end of sib2, iclass 40, count 0 2006.238.07:53:01.26#ibcon#*after write, iclass 40, count 0 2006.238.07:53:01.26#ibcon#*before return 0, iclass 40, count 0 2006.238.07:53:01.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:53:01.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.238.07:53:01.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.07:53:01.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.07:53:01.26$vc4f8/vblo=3,656.99 2006.238.07:53:01.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.07:53:01.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.07:53:01.26#ibcon#ireg 17 cls_cnt 0 2006.238.07:53:01.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:53:01.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:53:01.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:53:01.26#ibcon#enter wrdev, iclass 4, count 0 2006.238.07:53:01.26#ibcon#first serial, iclass 4, count 0 2006.238.07:53:01.26#ibcon#enter sib2, iclass 4, count 0 2006.238.07:53:01.26#ibcon#flushed, iclass 4, count 0 2006.238.07:53:01.26#ibcon#about to write, iclass 4, count 0 2006.238.07:53:01.26#ibcon#wrote, iclass 4, count 0 2006.238.07:53:01.26#ibcon#about to read 3, iclass 4, count 0 2006.238.07:53:01.28#ibcon#read 3, iclass 4, count 0 2006.238.07:53:01.28#ibcon#about to read 4, iclass 4, count 0 2006.238.07:53:01.28#ibcon#read 4, iclass 4, count 0 2006.238.07:53:01.28#ibcon#about to read 5, iclass 4, count 0 2006.238.07:53:01.28#ibcon#read 5, iclass 4, count 0 2006.238.07:53:01.28#ibcon#about to read 6, iclass 4, count 0 2006.238.07:53:01.28#ibcon#read 6, iclass 4, count 0 2006.238.07:53:01.28#ibcon#end of sib2, iclass 4, count 0 2006.238.07:53:01.28#ibcon#*mode == 0, iclass 4, count 0 2006.238.07:53:01.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.07:53:01.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:53:01.28#ibcon#*before write, iclass 4, count 0 2006.238.07:53:01.28#ibcon#enter sib2, iclass 4, count 0 2006.238.07:53:01.28#ibcon#flushed, iclass 4, count 0 2006.238.07:53:01.28#ibcon#about to write, iclass 4, count 0 2006.238.07:53:01.28#ibcon#wrote, iclass 4, count 0 2006.238.07:53:01.28#ibcon#about to read 3, iclass 4, count 0 2006.238.07:53:01.32#ibcon#read 3, iclass 4, count 0 2006.238.07:53:01.32#ibcon#about to read 4, iclass 4, count 0 2006.238.07:53:01.32#ibcon#read 4, iclass 4, count 0 2006.238.07:53:01.32#ibcon#about to read 5, iclass 4, count 0 2006.238.07:53:01.32#ibcon#read 5, iclass 4, count 0 2006.238.07:53:01.32#ibcon#about to read 6, iclass 4, count 0 2006.238.07:53:01.32#ibcon#read 6, iclass 4, count 0 2006.238.07:53:01.32#ibcon#end of sib2, iclass 4, count 0 2006.238.07:53:01.32#ibcon#*after write, iclass 4, count 0 2006.238.07:53:01.32#ibcon#*before return 0, iclass 4, count 0 2006.238.07:53:01.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:53:01.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.07:53:01.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.07:53:01.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.07:53:01.32$vc4f8/vb=3,4 2006.238.07:53:01.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.07:53:01.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.07:53:01.32#ibcon#ireg 11 cls_cnt 2 2006.238.07:53:01.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:53:01.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:53:01.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:53:01.38#ibcon#enter wrdev, iclass 6, count 2 2006.238.07:53:01.38#ibcon#first serial, iclass 6, count 2 2006.238.07:53:01.38#ibcon#enter sib2, iclass 6, count 2 2006.238.07:53:01.38#ibcon#flushed, iclass 6, count 2 2006.238.07:53:01.38#ibcon#about to write, iclass 6, count 2 2006.238.07:53:01.38#ibcon#wrote, iclass 6, count 2 2006.238.07:53:01.38#ibcon#about to read 3, iclass 6, count 2 2006.238.07:53:01.40#ibcon#read 3, iclass 6, count 2 2006.238.07:53:01.40#ibcon#about to read 4, iclass 6, count 2 2006.238.07:53:01.40#ibcon#read 4, iclass 6, count 2 2006.238.07:53:01.40#ibcon#about to read 5, iclass 6, count 2 2006.238.07:53:01.40#ibcon#read 5, iclass 6, count 2 2006.238.07:53:01.40#ibcon#about to read 6, iclass 6, count 2 2006.238.07:53:01.40#ibcon#read 6, iclass 6, count 2 2006.238.07:53:01.40#ibcon#end of sib2, iclass 6, count 2 2006.238.07:53:01.40#ibcon#*mode == 0, iclass 6, count 2 2006.238.07:53:01.40#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.07:53:01.40#ibcon#[27=AT03-04\r\n] 2006.238.07:53:01.40#ibcon#*before write, iclass 6, count 2 2006.238.07:53:01.40#ibcon#enter sib2, iclass 6, count 2 2006.238.07:53:01.40#ibcon#flushed, iclass 6, count 2 2006.238.07:53:01.40#ibcon#about to write, iclass 6, count 2 2006.238.07:53:01.40#ibcon#wrote, iclass 6, count 2 2006.238.07:53:01.40#ibcon#about to read 3, iclass 6, count 2 2006.238.07:53:01.43#ibcon#read 3, iclass 6, count 2 2006.238.07:53:01.43#ibcon#about to read 4, iclass 6, count 2 2006.238.07:53:01.43#ibcon#read 4, iclass 6, count 2 2006.238.07:53:01.43#ibcon#about to read 5, iclass 6, count 2 2006.238.07:53:01.43#ibcon#read 5, iclass 6, count 2 2006.238.07:53:01.43#ibcon#about to read 6, iclass 6, count 2 2006.238.07:53:01.43#ibcon#read 6, iclass 6, count 2 2006.238.07:53:01.43#ibcon#end of sib2, iclass 6, count 2 2006.238.07:53:01.43#ibcon#*after write, iclass 6, count 2 2006.238.07:53:01.43#ibcon#*before return 0, iclass 6, count 2 2006.238.07:53:01.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:53:01.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.07:53:01.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.07:53:01.43#ibcon#ireg 7 cls_cnt 0 2006.238.07:53:01.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:53:01.55#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:53:01.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:53:01.55#ibcon#enter wrdev, iclass 6, count 0 2006.238.07:53:01.55#ibcon#first serial, iclass 6, count 0 2006.238.07:53:01.55#ibcon#enter sib2, iclass 6, count 0 2006.238.07:53:01.55#ibcon#flushed, iclass 6, count 0 2006.238.07:53:01.55#ibcon#about to write, iclass 6, count 0 2006.238.07:53:01.55#ibcon#wrote, iclass 6, count 0 2006.238.07:53:01.55#ibcon#about to read 3, iclass 6, count 0 2006.238.07:53:01.57#ibcon#read 3, iclass 6, count 0 2006.238.07:53:01.57#ibcon#about to read 4, iclass 6, count 0 2006.238.07:53:01.57#ibcon#read 4, iclass 6, count 0 2006.238.07:53:01.57#ibcon#about to read 5, iclass 6, count 0 2006.238.07:53:01.57#ibcon#read 5, iclass 6, count 0 2006.238.07:53:01.57#ibcon#about to read 6, iclass 6, count 0 2006.238.07:53:01.57#ibcon#read 6, iclass 6, count 0 2006.238.07:53:01.57#ibcon#end of sib2, iclass 6, count 0 2006.238.07:53:01.57#ibcon#*mode == 0, iclass 6, count 0 2006.238.07:53:01.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.07:53:01.57#ibcon#[27=USB\r\n] 2006.238.07:53:01.57#ibcon#*before write, iclass 6, count 0 2006.238.07:53:01.57#ibcon#enter sib2, iclass 6, count 0 2006.238.07:53:01.57#ibcon#flushed, iclass 6, count 0 2006.238.07:53:01.57#ibcon#about to write, iclass 6, count 0 2006.238.07:53:01.57#ibcon#wrote, iclass 6, count 0 2006.238.07:53:01.57#ibcon#about to read 3, iclass 6, count 0 2006.238.07:53:01.60#ibcon#read 3, iclass 6, count 0 2006.238.07:53:01.60#ibcon#about to read 4, iclass 6, count 0 2006.238.07:53:01.60#ibcon#read 4, iclass 6, count 0 2006.238.07:53:01.60#ibcon#about to read 5, iclass 6, count 0 2006.238.07:53:01.60#ibcon#read 5, iclass 6, count 0 2006.238.07:53:01.60#ibcon#about to read 6, iclass 6, count 0 2006.238.07:53:01.60#ibcon#read 6, iclass 6, count 0 2006.238.07:53:01.60#ibcon#end of sib2, iclass 6, count 0 2006.238.07:53:01.60#ibcon#*after write, iclass 6, count 0 2006.238.07:53:01.60#ibcon#*before return 0, iclass 6, count 0 2006.238.07:53:01.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:53:01.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.07:53:01.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.07:53:01.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.07:53:01.60$vc4f8/vblo=4,712.99 2006.238.07:53:01.60#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.07:53:01.60#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.07:53:01.60#ibcon#ireg 17 cls_cnt 0 2006.238.07:53:01.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:53:01.60#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:53:01.60#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:53:01.60#ibcon#enter wrdev, iclass 10, count 0 2006.238.07:53:01.60#ibcon#first serial, iclass 10, count 0 2006.238.07:53:01.60#ibcon#enter sib2, iclass 10, count 0 2006.238.07:53:01.60#ibcon#flushed, iclass 10, count 0 2006.238.07:53:01.60#ibcon#about to write, iclass 10, count 0 2006.238.07:53:01.60#ibcon#wrote, iclass 10, count 0 2006.238.07:53:01.60#ibcon#about to read 3, iclass 10, count 0 2006.238.07:53:01.62#ibcon#read 3, iclass 10, count 0 2006.238.07:53:01.62#ibcon#about to read 4, iclass 10, count 0 2006.238.07:53:01.62#ibcon#read 4, iclass 10, count 0 2006.238.07:53:01.62#ibcon#about to read 5, iclass 10, count 0 2006.238.07:53:01.62#ibcon#read 5, iclass 10, count 0 2006.238.07:53:01.62#ibcon#about to read 6, iclass 10, count 0 2006.238.07:53:01.62#ibcon#read 6, iclass 10, count 0 2006.238.07:53:01.62#ibcon#end of sib2, iclass 10, count 0 2006.238.07:53:01.62#ibcon#*mode == 0, iclass 10, count 0 2006.238.07:53:01.62#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.07:53:01.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:53:01.62#ibcon#*before write, iclass 10, count 0 2006.238.07:53:01.62#ibcon#enter sib2, iclass 10, count 0 2006.238.07:53:01.62#ibcon#flushed, iclass 10, count 0 2006.238.07:53:01.62#ibcon#about to write, iclass 10, count 0 2006.238.07:53:01.62#ibcon#wrote, iclass 10, count 0 2006.238.07:53:01.62#ibcon#about to read 3, iclass 10, count 0 2006.238.07:53:01.66#ibcon#read 3, iclass 10, count 0 2006.238.07:53:01.66#ibcon#about to read 4, iclass 10, count 0 2006.238.07:53:01.66#ibcon#read 4, iclass 10, count 0 2006.238.07:53:01.66#ibcon#about to read 5, iclass 10, count 0 2006.238.07:53:01.66#ibcon#read 5, iclass 10, count 0 2006.238.07:53:01.66#ibcon#about to read 6, iclass 10, count 0 2006.238.07:53:01.66#ibcon#read 6, iclass 10, count 0 2006.238.07:53:01.66#ibcon#end of sib2, iclass 10, count 0 2006.238.07:53:01.66#ibcon#*after write, iclass 10, count 0 2006.238.07:53:01.66#ibcon#*before return 0, iclass 10, count 0 2006.238.07:53:01.66#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:53:01.66#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.07:53:01.66#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.07:53:01.66#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.07:53:01.66$vc4f8/vb=4,4 2006.238.07:53:01.66#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.238.07:53:01.66#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.238.07:53:01.66#ibcon#ireg 11 cls_cnt 2 2006.238.07:53:01.66#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:53:01.72#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:53:01.72#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:53:01.72#ibcon#enter wrdev, iclass 12, count 2 2006.238.07:53:01.72#ibcon#first serial, iclass 12, count 2 2006.238.07:53:01.72#ibcon#enter sib2, iclass 12, count 2 2006.238.07:53:01.72#ibcon#flushed, iclass 12, count 2 2006.238.07:53:01.72#ibcon#about to write, iclass 12, count 2 2006.238.07:53:01.72#ibcon#wrote, iclass 12, count 2 2006.238.07:53:01.72#ibcon#about to read 3, iclass 12, count 2 2006.238.07:53:01.74#ibcon#read 3, iclass 12, count 2 2006.238.07:53:01.74#ibcon#about to read 4, iclass 12, count 2 2006.238.07:53:01.74#ibcon#read 4, iclass 12, count 2 2006.238.07:53:01.74#ibcon#about to read 5, iclass 12, count 2 2006.238.07:53:01.74#ibcon#read 5, iclass 12, count 2 2006.238.07:53:01.74#ibcon#about to read 6, iclass 12, count 2 2006.238.07:53:01.74#ibcon#read 6, iclass 12, count 2 2006.238.07:53:01.74#ibcon#end of sib2, iclass 12, count 2 2006.238.07:53:01.74#ibcon#*mode == 0, iclass 12, count 2 2006.238.07:53:01.74#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.238.07:53:01.74#ibcon#[27=AT04-04\r\n] 2006.238.07:53:01.74#ibcon#*before write, iclass 12, count 2 2006.238.07:53:01.74#ibcon#enter sib2, iclass 12, count 2 2006.238.07:53:01.74#ibcon#flushed, iclass 12, count 2 2006.238.07:53:01.74#ibcon#about to write, iclass 12, count 2 2006.238.07:53:01.74#ibcon#wrote, iclass 12, count 2 2006.238.07:53:01.74#ibcon#about to read 3, iclass 12, count 2 2006.238.07:53:01.78#ibcon#read 3, iclass 12, count 2 2006.238.07:53:01.78#ibcon#about to read 4, iclass 12, count 2 2006.238.07:53:01.78#ibcon#read 4, iclass 12, count 2 2006.238.07:53:01.78#ibcon#about to read 5, iclass 12, count 2 2006.238.07:53:01.78#ibcon#read 5, iclass 12, count 2 2006.238.07:53:01.78#ibcon#about to read 6, iclass 12, count 2 2006.238.07:53:01.78#ibcon#read 6, iclass 12, count 2 2006.238.07:53:01.78#ibcon#end of sib2, iclass 12, count 2 2006.238.07:53:01.78#ibcon#*after write, iclass 12, count 2 2006.238.07:53:01.78#ibcon#*before return 0, iclass 12, count 2 2006.238.07:53:01.78#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:53:01.78#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.238.07:53:01.78#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.238.07:53:01.78#ibcon#ireg 7 cls_cnt 0 2006.238.07:53:01.78#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:53:01.90#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:53:01.90#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:53:01.90#ibcon#enter wrdev, iclass 12, count 0 2006.238.07:53:01.90#ibcon#first serial, iclass 12, count 0 2006.238.07:53:01.90#ibcon#enter sib2, iclass 12, count 0 2006.238.07:53:01.90#ibcon#flushed, iclass 12, count 0 2006.238.07:53:01.90#ibcon#about to write, iclass 12, count 0 2006.238.07:53:01.90#ibcon#wrote, iclass 12, count 0 2006.238.07:53:01.90#ibcon#about to read 3, iclass 12, count 0 2006.238.07:53:01.92#ibcon#read 3, iclass 12, count 0 2006.238.07:53:01.92#ibcon#about to read 4, iclass 12, count 0 2006.238.07:53:01.92#ibcon#read 4, iclass 12, count 0 2006.238.07:53:01.92#ibcon#about to read 5, iclass 12, count 0 2006.238.07:53:01.92#ibcon#read 5, iclass 12, count 0 2006.238.07:53:01.92#ibcon#about to read 6, iclass 12, count 0 2006.238.07:53:01.92#ibcon#read 6, iclass 12, count 0 2006.238.07:53:01.92#ibcon#end of sib2, iclass 12, count 0 2006.238.07:53:01.92#ibcon#*mode == 0, iclass 12, count 0 2006.238.07:53:01.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.07:53:01.92#ibcon#[27=USB\r\n] 2006.238.07:53:01.92#ibcon#*before write, iclass 12, count 0 2006.238.07:53:01.92#ibcon#enter sib2, iclass 12, count 0 2006.238.07:53:01.92#ibcon#flushed, iclass 12, count 0 2006.238.07:53:01.92#ibcon#about to write, iclass 12, count 0 2006.238.07:53:01.92#ibcon#wrote, iclass 12, count 0 2006.238.07:53:01.92#ibcon#about to read 3, iclass 12, count 0 2006.238.07:53:01.95#ibcon#read 3, iclass 12, count 0 2006.238.07:53:01.95#ibcon#about to read 4, iclass 12, count 0 2006.238.07:53:01.95#ibcon#read 4, iclass 12, count 0 2006.238.07:53:01.95#ibcon#about to read 5, iclass 12, count 0 2006.238.07:53:01.95#ibcon#read 5, iclass 12, count 0 2006.238.07:53:01.95#ibcon#about to read 6, iclass 12, count 0 2006.238.07:53:01.95#ibcon#read 6, iclass 12, count 0 2006.238.07:53:01.95#ibcon#end of sib2, iclass 12, count 0 2006.238.07:53:01.95#ibcon#*after write, iclass 12, count 0 2006.238.07:53:01.95#ibcon#*before return 0, iclass 12, count 0 2006.238.07:53:01.95#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:53:01.95#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.238.07:53:01.95#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.07:53:01.95#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.07:53:01.95$vc4f8/vblo=5,744.99 2006.238.07:53:01.95#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.07:53:01.95#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.07:53:01.95#ibcon#ireg 17 cls_cnt 0 2006.238.07:53:01.95#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:53:01.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:53:01.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:53:01.95#ibcon#enter wrdev, iclass 14, count 0 2006.238.07:53:01.95#ibcon#first serial, iclass 14, count 0 2006.238.07:53:01.95#ibcon#enter sib2, iclass 14, count 0 2006.238.07:53:01.95#ibcon#flushed, iclass 14, count 0 2006.238.07:53:01.95#ibcon#about to write, iclass 14, count 0 2006.238.07:53:01.95#ibcon#wrote, iclass 14, count 0 2006.238.07:53:01.95#ibcon#about to read 3, iclass 14, count 0 2006.238.07:53:01.97#ibcon#read 3, iclass 14, count 0 2006.238.07:53:01.97#ibcon#about to read 4, iclass 14, count 0 2006.238.07:53:01.97#ibcon#read 4, iclass 14, count 0 2006.238.07:53:01.97#ibcon#about to read 5, iclass 14, count 0 2006.238.07:53:01.97#ibcon#read 5, iclass 14, count 0 2006.238.07:53:01.97#ibcon#about to read 6, iclass 14, count 0 2006.238.07:53:01.97#ibcon#read 6, iclass 14, count 0 2006.238.07:53:01.97#ibcon#end of sib2, iclass 14, count 0 2006.238.07:53:01.97#ibcon#*mode == 0, iclass 14, count 0 2006.238.07:53:01.97#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.07:53:01.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:53:01.97#ibcon#*before write, iclass 14, count 0 2006.238.07:53:01.97#ibcon#enter sib2, iclass 14, count 0 2006.238.07:53:01.97#ibcon#flushed, iclass 14, count 0 2006.238.07:53:01.97#ibcon#about to write, iclass 14, count 0 2006.238.07:53:01.97#ibcon#wrote, iclass 14, count 0 2006.238.07:53:01.97#ibcon#about to read 3, iclass 14, count 0 2006.238.07:53:02.01#ibcon#read 3, iclass 14, count 0 2006.238.07:53:02.01#ibcon#about to read 4, iclass 14, count 0 2006.238.07:53:02.01#ibcon#read 4, iclass 14, count 0 2006.238.07:53:02.01#ibcon#about to read 5, iclass 14, count 0 2006.238.07:53:02.01#ibcon#read 5, iclass 14, count 0 2006.238.07:53:02.01#ibcon#about to read 6, iclass 14, count 0 2006.238.07:53:02.01#ibcon#read 6, iclass 14, count 0 2006.238.07:53:02.01#ibcon#end of sib2, iclass 14, count 0 2006.238.07:53:02.01#ibcon#*after write, iclass 14, count 0 2006.238.07:53:02.01#ibcon#*before return 0, iclass 14, count 0 2006.238.07:53:02.01#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:53:02.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.07:53:02.01#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.07:53:02.01#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.07:53:02.01$vc4f8/vb=5,4 2006.238.07:53:02.01#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.238.07:53:02.01#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.238.07:53:02.01#ibcon#ireg 11 cls_cnt 2 2006.238.07:53:02.01#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:53:02.07#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:53:02.07#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:53:02.07#ibcon#enter wrdev, iclass 16, count 2 2006.238.07:53:02.07#ibcon#first serial, iclass 16, count 2 2006.238.07:53:02.07#ibcon#enter sib2, iclass 16, count 2 2006.238.07:53:02.07#ibcon#flushed, iclass 16, count 2 2006.238.07:53:02.07#ibcon#about to write, iclass 16, count 2 2006.238.07:53:02.07#ibcon#wrote, iclass 16, count 2 2006.238.07:53:02.07#ibcon#about to read 3, iclass 16, count 2 2006.238.07:53:02.09#ibcon#read 3, iclass 16, count 2 2006.238.07:53:02.09#ibcon#about to read 4, iclass 16, count 2 2006.238.07:53:02.09#ibcon#read 4, iclass 16, count 2 2006.238.07:53:02.09#ibcon#about to read 5, iclass 16, count 2 2006.238.07:53:02.09#ibcon#read 5, iclass 16, count 2 2006.238.07:53:02.09#ibcon#about to read 6, iclass 16, count 2 2006.238.07:53:02.09#ibcon#read 6, iclass 16, count 2 2006.238.07:53:02.09#ibcon#end of sib2, iclass 16, count 2 2006.238.07:53:02.09#ibcon#*mode == 0, iclass 16, count 2 2006.238.07:53:02.09#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.238.07:53:02.09#ibcon#[27=AT05-04\r\n] 2006.238.07:53:02.09#ibcon#*before write, iclass 16, count 2 2006.238.07:53:02.09#ibcon#enter sib2, iclass 16, count 2 2006.238.07:53:02.09#ibcon#flushed, iclass 16, count 2 2006.238.07:53:02.09#ibcon#about to write, iclass 16, count 2 2006.238.07:53:02.09#ibcon#wrote, iclass 16, count 2 2006.238.07:53:02.09#ibcon#about to read 3, iclass 16, count 2 2006.238.07:53:02.12#ibcon#read 3, iclass 16, count 2 2006.238.07:53:02.12#ibcon#about to read 4, iclass 16, count 2 2006.238.07:53:02.12#ibcon#read 4, iclass 16, count 2 2006.238.07:53:02.12#ibcon#about to read 5, iclass 16, count 2 2006.238.07:53:02.12#ibcon#read 5, iclass 16, count 2 2006.238.07:53:02.12#ibcon#about to read 6, iclass 16, count 2 2006.238.07:53:02.12#ibcon#read 6, iclass 16, count 2 2006.238.07:53:02.12#ibcon#end of sib2, iclass 16, count 2 2006.238.07:53:02.12#ibcon#*after write, iclass 16, count 2 2006.238.07:53:02.12#ibcon#*before return 0, iclass 16, count 2 2006.238.07:53:02.12#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:53:02.12#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.238.07:53:02.12#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.238.07:53:02.12#ibcon#ireg 7 cls_cnt 0 2006.238.07:53:02.12#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:53:02.24#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:53:02.24#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:53:02.24#ibcon#enter wrdev, iclass 16, count 0 2006.238.07:53:02.24#ibcon#first serial, iclass 16, count 0 2006.238.07:53:02.24#ibcon#enter sib2, iclass 16, count 0 2006.238.07:53:02.24#ibcon#flushed, iclass 16, count 0 2006.238.07:53:02.24#ibcon#about to write, iclass 16, count 0 2006.238.07:53:02.24#ibcon#wrote, iclass 16, count 0 2006.238.07:53:02.24#ibcon#about to read 3, iclass 16, count 0 2006.238.07:53:02.26#ibcon#read 3, iclass 16, count 0 2006.238.07:53:02.26#ibcon#about to read 4, iclass 16, count 0 2006.238.07:53:02.26#ibcon#read 4, iclass 16, count 0 2006.238.07:53:02.26#ibcon#about to read 5, iclass 16, count 0 2006.238.07:53:02.26#ibcon#read 5, iclass 16, count 0 2006.238.07:53:02.26#ibcon#about to read 6, iclass 16, count 0 2006.238.07:53:02.26#ibcon#read 6, iclass 16, count 0 2006.238.07:53:02.26#ibcon#end of sib2, iclass 16, count 0 2006.238.07:53:02.26#ibcon#*mode == 0, iclass 16, count 0 2006.238.07:53:02.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.07:53:02.26#ibcon#[27=USB\r\n] 2006.238.07:53:02.26#ibcon#*before write, iclass 16, count 0 2006.238.07:53:02.26#ibcon#enter sib2, iclass 16, count 0 2006.238.07:53:02.26#ibcon#flushed, iclass 16, count 0 2006.238.07:53:02.26#ibcon#about to write, iclass 16, count 0 2006.238.07:53:02.26#ibcon#wrote, iclass 16, count 0 2006.238.07:53:02.26#ibcon#about to read 3, iclass 16, count 0 2006.238.07:53:02.29#ibcon#read 3, iclass 16, count 0 2006.238.07:53:02.29#ibcon#about to read 4, iclass 16, count 0 2006.238.07:53:02.29#ibcon#read 4, iclass 16, count 0 2006.238.07:53:02.29#ibcon#about to read 5, iclass 16, count 0 2006.238.07:53:02.29#ibcon#read 5, iclass 16, count 0 2006.238.07:53:02.29#ibcon#about to read 6, iclass 16, count 0 2006.238.07:53:02.29#ibcon#read 6, iclass 16, count 0 2006.238.07:53:02.29#ibcon#end of sib2, iclass 16, count 0 2006.238.07:53:02.29#ibcon#*after write, iclass 16, count 0 2006.238.07:53:02.29#ibcon#*before return 0, iclass 16, count 0 2006.238.07:53:02.29#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:53:02.29#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.238.07:53:02.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.07:53:02.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.07:53:02.29$vc4f8/vblo=6,752.99 2006.238.07:53:02.29#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.07:53:02.29#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.07:53:02.29#ibcon#ireg 17 cls_cnt 0 2006.238.07:53:02.29#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:53:02.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:53:02.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:53:02.29#ibcon#enter wrdev, iclass 18, count 0 2006.238.07:53:02.29#ibcon#first serial, iclass 18, count 0 2006.238.07:53:02.29#ibcon#enter sib2, iclass 18, count 0 2006.238.07:53:02.29#ibcon#flushed, iclass 18, count 0 2006.238.07:53:02.29#ibcon#about to write, iclass 18, count 0 2006.238.07:53:02.29#ibcon#wrote, iclass 18, count 0 2006.238.07:53:02.29#ibcon#about to read 3, iclass 18, count 0 2006.238.07:53:02.31#ibcon#read 3, iclass 18, count 0 2006.238.07:53:02.31#ibcon#about to read 4, iclass 18, count 0 2006.238.07:53:02.31#ibcon#read 4, iclass 18, count 0 2006.238.07:53:02.31#ibcon#about to read 5, iclass 18, count 0 2006.238.07:53:02.31#ibcon#read 5, iclass 18, count 0 2006.238.07:53:02.31#ibcon#about to read 6, iclass 18, count 0 2006.238.07:53:02.31#ibcon#read 6, iclass 18, count 0 2006.238.07:53:02.31#ibcon#end of sib2, iclass 18, count 0 2006.238.07:53:02.31#ibcon#*mode == 0, iclass 18, count 0 2006.238.07:53:02.31#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.07:53:02.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:53:02.31#ibcon#*before write, iclass 18, count 0 2006.238.07:53:02.31#ibcon#enter sib2, iclass 18, count 0 2006.238.07:53:02.31#ibcon#flushed, iclass 18, count 0 2006.238.07:53:02.31#ibcon#about to write, iclass 18, count 0 2006.238.07:53:02.31#ibcon#wrote, iclass 18, count 0 2006.238.07:53:02.31#ibcon#about to read 3, iclass 18, count 0 2006.238.07:53:02.35#ibcon#read 3, iclass 18, count 0 2006.238.07:53:02.35#ibcon#about to read 4, iclass 18, count 0 2006.238.07:53:02.35#ibcon#read 4, iclass 18, count 0 2006.238.07:53:02.35#ibcon#about to read 5, iclass 18, count 0 2006.238.07:53:02.35#ibcon#read 5, iclass 18, count 0 2006.238.07:53:02.35#ibcon#about to read 6, iclass 18, count 0 2006.238.07:53:02.35#ibcon#read 6, iclass 18, count 0 2006.238.07:53:02.35#ibcon#end of sib2, iclass 18, count 0 2006.238.07:53:02.35#ibcon#*after write, iclass 18, count 0 2006.238.07:53:02.35#ibcon#*before return 0, iclass 18, count 0 2006.238.07:53:02.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:53:02.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.07:53:02.35#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.07:53:02.35#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.07:53:02.35$vc4f8/vb=6,4 2006.238.07:53:02.35#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.238.07:53:02.35#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.238.07:53:02.35#ibcon#ireg 11 cls_cnt 2 2006.238.07:53:02.35#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:53:02.41#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:53:02.41#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:53:02.41#ibcon#enter wrdev, iclass 20, count 2 2006.238.07:53:02.41#ibcon#first serial, iclass 20, count 2 2006.238.07:53:02.41#ibcon#enter sib2, iclass 20, count 2 2006.238.07:53:02.41#ibcon#flushed, iclass 20, count 2 2006.238.07:53:02.41#ibcon#about to write, iclass 20, count 2 2006.238.07:53:02.41#ibcon#wrote, iclass 20, count 2 2006.238.07:53:02.41#ibcon#about to read 3, iclass 20, count 2 2006.238.07:53:02.43#ibcon#read 3, iclass 20, count 2 2006.238.07:53:02.43#ibcon#about to read 4, iclass 20, count 2 2006.238.07:53:02.43#ibcon#read 4, iclass 20, count 2 2006.238.07:53:02.43#ibcon#about to read 5, iclass 20, count 2 2006.238.07:53:02.43#ibcon#read 5, iclass 20, count 2 2006.238.07:53:02.43#ibcon#about to read 6, iclass 20, count 2 2006.238.07:53:02.43#ibcon#read 6, iclass 20, count 2 2006.238.07:53:02.43#ibcon#end of sib2, iclass 20, count 2 2006.238.07:53:02.43#ibcon#*mode == 0, iclass 20, count 2 2006.238.07:53:02.43#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.238.07:53:02.43#ibcon#[27=AT06-04\r\n] 2006.238.07:53:02.43#ibcon#*before write, iclass 20, count 2 2006.238.07:53:02.43#ibcon#enter sib2, iclass 20, count 2 2006.238.07:53:02.43#ibcon#flushed, iclass 20, count 2 2006.238.07:53:02.43#ibcon#about to write, iclass 20, count 2 2006.238.07:53:02.43#ibcon#wrote, iclass 20, count 2 2006.238.07:53:02.43#ibcon#about to read 3, iclass 20, count 2 2006.238.07:53:02.46#ibcon#read 3, iclass 20, count 2 2006.238.07:53:02.46#ibcon#about to read 4, iclass 20, count 2 2006.238.07:53:02.46#ibcon#read 4, iclass 20, count 2 2006.238.07:53:02.46#ibcon#about to read 5, iclass 20, count 2 2006.238.07:53:02.46#ibcon#read 5, iclass 20, count 2 2006.238.07:53:02.46#ibcon#about to read 6, iclass 20, count 2 2006.238.07:53:02.46#ibcon#read 6, iclass 20, count 2 2006.238.07:53:02.46#ibcon#end of sib2, iclass 20, count 2 2006.238.07:53:02.46#ibcon#*after write, iclass 20, count 2 2006.238.07:53:02.46#ibcon#*before return 0, iclass 20, count 2 2006.238.07:53:02.46#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:53:02.46#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.238.07:53:02.46#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.238.07:53:02.46#ibcon#ireg 7 cls_cnt 0 2006.238.07:53:02.46#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:53:02.58#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:53:02.58#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:53:02.58#ibcon#enter wrdev, iclass 20, count 0 2006.238.07:53:02.58#ibcon#first serial, iclass 20, count 0 2006.238.07:53:02.58#ibcon#enter sib2, iclass 20, count 0 2006.238.07:53:02.58#ibcon#flushed, iclass 20, count 0 2006.238.07:53:02.58#ibcon#about to write, iclass 20, count 0 2006.238.07:53:02.58#ibcon#wrote, iclass 20, count 0 2006.238.07:53:02.58#ibcon#about to read 3, iclass 20, count 0 2006.238.07:53:02.60#ibcon#read 3, iclass 20, count 0 2006.238.07:53:02.60#ibcon#about to read 4, iclass 20, count 0 2006.238.07:53:02.60#ibcon#read 4, iclass 20, count 0 2006.238.07:53:02.60#ibcon#about to read 5, iclass 20, count 0 2006.238.07:53:02.60#ibcon#read 5, iclass 20, count 0 2006.238.07:53:02.60#ibcon#about to read 6, iclass 20, count 0 2006.238.07:53:02.60#ibcon#read 6, iclass 20, count 0 2006.238.07:53:02.60#ibcon#end of sib2, iclass 20, count 0 2006.238.07:53:02.60#ibcon#*mode == 0, iclass 20, count 0 2006.238.07:53:02.60#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.07:53:02.60#ibcon#[27=USB\r\n] 2006.238.07:53:02.60#ibcon#*before write, iclass 20, count 0 2006.238.07:53:02.60#ibcon#enter sib2, iclass 20, count 0 2006.238.07:53:02.60#ibcon#flushed, iclass 20, count 0 2006.238.07:53:02.60#ibcon#about to write, iclass 20, count 0 2006.238.07:53:02.60#ibcon#wrote, iclass 20, count 0 2006.238.07:53:02.60#ibcon#about to read 3, iclass 20, count 0 2006.238.07:53:02.63#ibcon#read 3, iclass 20, count 0 2006.238.07:53:02.63#ibcon#about to read 4, iclass 20, count 0 2006.238.07:53:02.63#ibcon#read 4, iclass 20, count 0 2006.238.07:53:02.63#ibcon#about to read 5, iclass 20, count 0 2006.238.07:53:02.63#ibcon#read 5, iclass 20, count 0 2006.238.07:53:02.63#ibcon#about to read 6, iclass 20, count 0 2006.238.07:53:02.63#ibcon#read 6, iclass 20, count 0 2006.238.07:53:02.63#ibcon#end of sib2, iclass 20, count 0 2006.238.07:53:02.63#ibcon#*after write, iclass 20, count 0 2006.238.07:53:02.63#ibcon#*before return 0, iclass 20, count 0 2006.238.07:53:02.63#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:53:02.63#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.238.07:53:02.63#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.07:53:02.63#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.07:53:02.63$vc4f8/vabw=wide 2006.238.07:53:02.63#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.07:53:02.63#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.07:53:02.63#ibcon#ireg 8 cls_cnt 0 2006.238.07:53:02.63#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:53:02.63#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:53:02.63#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:53:02.63#ibcon#enter wrdev, iclass 22, count 0 2006.238.07:53:02.63#ibcon#first serial, iclass 22, count 0 2006.238.07:53:02.63#ibcon#enter sib2, iclass 22, count 0 2006.238.07:53:02.63#ibcon#flushed, iclass 22, count 0 2006.238.07:53:02.63#ibcon#about to write, iclass 22, count 0 2006.238.07:53:02.63#ibcon#wrote, iclass 22, count 0 2006.238.07:53:02.63#ibcon#about to read 3, iclass 22, count 0 2006.238.07:53:02.65#ibcon#read 3, iclass 22, count 0 2006.238.07:53:02.65#ibcon#about to read 4, iclass 22, count 0 2006.238.07:53:02.65#ibcon#read 4, iclass 22, count 0 2006.238.07:53:02.65#ibcon#about to read 5, iclass 22, count 0 2006.238.07:53:02.65#ibcon#read 5, iclass 22, count 0 2006.238.07:53:02.65#ibcon#about to read 6, iclass 22, count 0 2006.238.07:53:02.65#ibcon#read 6, iclass 22, count 0 2006.238.07:53:02.65#ibcon#end of sib2, iclass 22, count 0 2006.238.07:53:02.65#ibcon#*mode == 0, iclass 22, count 0 2006.238.07:53:02.65#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.07:53:02.65#ibcon#[25=BW32\r\n] 2006.238.07:53:02.65#ibcon#*before write, iclass 22, count 0 2006.238.07:53:02.65#ibcon#enter sib2, iclass 22, count 0 2006.238.07:53:02.65#ibcon#flushed, iclass 22, count 0 2006.238.07:53:02.65#ibcon#about to write, iclass 22, count 0 2006.238.07:53:02.65#ibcon#wrote, iclass 22, count 0 2006.238.07:53:02.65#ibcon#about to read 3, iclass 22, count 0 2006.238.07:53:02.68#ibcon#read 3, iclass 22, count 0 2006.238.07:53:02.68#ibcon#about to read 4, iclass 22, count 0 2006.238.07:53:02.68#ibcon#read 4, iclass 22, count 0 2006.238.07:53:02.68#ibcon#about to read 5, iclass 22, count 0 2006.238.07:53:02.68#ibcon#read 5, iclass 22, count 0 2006.238.07:53:02.68#ibcon#about to read 6, iclass 22, count 0 2006.238.07:53:02.68#ibcon#read 6, iclass 22, count 0 2006.238.07:53:02.68#ibcon#end of sib2, iclass 22, count 0 2006.238.07:53:02.68#ibcon#*after write, iclass 22, count 0 2006.238.07:53:02.68#ibcon#*before return 0, iclass 22, count 0 2006.238.07:53:02.68#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:53:02.68#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.07:53:02.68#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.07:53:02.68#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.07:53:02.68$vc4f8/vbbw=wide 2006.238.07:53:02.68#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.07:53:02.68#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.07:53:02.68#ibcon#ireg 8 cls_cnt 0 2006.238.07:53:02.68#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:53:02.75#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:53:02.75#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:53:02.75#ibcon#enter wrdev, iclass 24, count 0 2006.238.07:53:02.75#ibcon#first serial, iclass 24, count 0 2006.238.07:53:02.75#ibcon#enter sib2, iclass 24, count 0 2006.238.07:53:02.75#ibcon#flushed, iclass 24, count 0 2006.238.07:53:02.75#ibcon#about to write, iclass 24, count 0 2006.238.07:53:02.75#ibcon#wrote, iclass 24, count 0 2006.238.07:53:02.75#ibcon#about to read 3, iclass 24, count 0 2006.238.07:53:02.77#ibcon#read 3, iclass 24, count 0 2006.238.07:53:02.77#ibcon#about to read 4, iclass 24, count 0 2006.238.07:53:02.77#ibcon#read 4, iclass 24, count 0 2006.238.07:53:02.77#ibcon#about to read 5, iclass 24, count 0 2006.238.07:53:02.77#ibcon#read 5, iclass 24, count 0 2006.238.07:53:02.77#ibcon#about to read 6, iclass 24, count 0 2006.238.07:53:02.77#ibcon#read 6, iclass 24, count 0 2006.238.07:53:02.77#ibcon#end of sib2, iclass 24, count 0 2006.238.07:53:02.77#ibcon#*mode == 0, iclass 24, count 0 2006.238.07:53:02.77#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.07:53:02.77#ibcon#[27=BW32\r\n] 2006.238.07:53:02.77#ibcon#*before write, iclass 24, count 0 2006.238.07:53:02.77#ibcon#enter sib2, iclass 24, count 0 2006.238.07:53:02.77#ibcon#flushed, iclass 24, count 0 2006.238.07:53:02.77#ibcon#about to write, iclass 24, count 0 2006.238.07:53:02.77#ibcon#wrote, iclass 24, count 0 2006.238.07:53:02.77#ibcon#about to read 3, iclass 24, count 0 2006.238.07:53:02.80#ibcon#read 3, iclass 24, count 0 2006.238.07:53:02.80#ibcon#about to read 4, iclass 24, count 0 2006.238.07:53:02.80#ibcon#read 4, iclass 24, count 0 2006.238.07:53:02.80#ibcon#about to read 5, iclass 24, count 0 2006.238.07:53:02.80#ibcon#read 5, iclass 24, count 0 2006.238.07:53:02.80#ibcon#about to read 6, iclass 24, count 0 2006.238.07:53:02.80#ibcon#read 6, iclass 24, count 0 2006.238.07:53:02.80#ibcon#end of sib2, iclass 24, count 0 2006.238.07:53:02.80#ibcon#*after write, iclass 24, count 0 2006.238.07:53:02.80#ibcon#*before return 0, iclass 24, count 0 2006.238.07:53:02.80#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:53:02.80#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.07:53:02.80#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.07:53:02.80#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.07:53:02.80$4f8m12a/ifd4f 2006.238.07:53:02.80$ifd4f/lo= 2006.238.07:53:02.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:53:02.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:53:02.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:53:02.80$ifd4f/patch= 2006.238.07:53:02.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:53:02.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:53:02.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:53:02.80$4f8m12a/"form=m,16.000,1:2 2006.238.07:53:02.80$4f8m12a/"tpicd 2006.238.07:53:02.80$4f8m12a/echo=off 2006.238.07:53:02.80$4f8m12a/xlog=off 2006.238.07:53:02.80:!2006.238.07:54:40 2006.238.07:53:26.14#trakl#Source acquired 2006.238.07:53:27.14#flagr#flagr/antenna,acquired 2006.238.07:54:40.02:preob 2006.238.07:54:41.14/onsource/TRACKING 2006.238.07:54:41.14:!2006.238.07:54:50 2006.238.07:54:50.02:data_valid=on 2006.238.07:54:50.02:midob 2006.238.07:54:51.15/onsource/TRACKING 2006.238.07:54:51.15/wx/25.39,1012.1,88 2006.238.07:54:51.22/cable/+6.4190E-03 2006.238.07:54:52.31/va/01,08,usb,yes,32,33 2006.238.07:54:52.32/va/02,07,usb,yes,31,33 2006.238.07:54:52.32/va/03,07,usb,yes,30,30 2006.238.07:54:52.32/va/04,07,usb,yes,33,35 2006.238.07:54:52.32/va/05,08,usb,yes,30,31 2006.238.07:54:52.32/va/06,07,usb,yes,32,32 2006.238.07:54:52.32/va/07,07,usb,yes,32,32 2006.238.07:54:52.32/va/08,07,usb,yes,35,34 2006.238.07:54:52.55/valo/01,532.99,yes,locked 2006.238.07:54:52.55/valo/02,572.99,yes,locked 2006.238.07:54:52.55/valo/03,672.99,yes,locked 2006.238.07:54:52.55/valo/04,832.99,yes,locked 2006.238.07:54:52.55/valo/05,652.99,yes,locked 2006.238.07:54:52.55/valo/06,772.99,yes,locked 2006.238.07:54:52.55/valo/07,832.99,yes,locked 2006.238.07:54:52.55/valo/08,852.99,yes,locked 2006.238.07:54:53.63/vb/01,04,usb,yes,30,29 2006.238.07:54:53.63/vb/02,04,usb,yes,32,33 2006.238.07:54:53.63/vb/03,04,usb,yes,28,32 2006.238.07:54:53.64/vb/04,04,usb,yes,29,29 2006.238.07:54:53.64/vb/05,04,usb,yes,27,31 2006.238.07:54:53.64/vb/06,04,usb,yes,28,31 2006.238.07:54:53.64/vb/07,04,usb,yes,31,31 2006.238.07:54:53.64/vb/08,04,usb,yes,28,31 2006.238.07:54:53.87/vblo/01,632.99,yes,locked 2006.238.07:54:53.87/vblo/02,640.99,yes,locked 2006.238.07:54:53.87/vblo/03,656.99,yes,locked 2006.238.07:54:53.87/vblo/04,712.99,yes,locked 2006.238.07:54:53.87/vblo/05,744.99,yes,locked 2006.238.07:54:53.87/vblo/06,752.99,yes,locked 2006.238.07:54:53.87/vblo/07,734.99,yes,locked 2006.238.07:54:53.87/vblo/08,744.99,yes,locked 2006.238.07:54:54.01/vabw/8 2006.238.07:54:54.16/vbbw/8 2006.238.07:54:54.25/xfe/off,on,13.0 2006.238.07:54:54.64/ifatt/23,28,28,28 2006.238.07:54:55.07/fmout-gps/S +4.32E-07 2006.238.07:54:55.12:!2006.238.07:55:50 2006.238.07:55:50.02:data_valid=off 2006.238.07:55:50.02:postob 2006.238.07:55:50.13/cable/+6.4188E-03 2006.238.07:55:50.14/wx/25.40,1012.1,88 2006.238.07:55:50.22/fmout-gps/S +4.30E-07 2006.238.07:55:50.22:scan_name=238-0758,k06238,60 2006.238.07:55:50.23:source=0059+581,010245.76,582411.1,2000.0,cw 2006.238.07:55:51.15#flagr#flagr/antenna,new-source 2006.238.07:55:51.15:checkk5 2006.238.07:55:51.53/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:55:51.90/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:55:52.28/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:55:52.66/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:55:53.03/chk_obsdata//k5ts1/T2380754??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:55:53.40/chk_obsdata//k5ts2/T2380754??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:55:53.77/chk_obsdata//k5ts3/T2380754??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:55:54.14/chk_obsdata//k5ts4/T2380754??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:55:54.84/k5log//k5ts1_log_newline 2006.238.07:55:55.54/k5log//k5ts2_log_newline 2006.238.07:55:56.23/k5log//k5ts3_log_newline 2006.238.07:55:56.91/k5log//k5ts4_log_newline 2006.238.07:55:56.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:55:56.94:4f8m12a=2 2006.238.07:55:56.94$4f8m12a/echo=on 2006.238.07:55:56.94$4f8m12a/pcalon 2006.238.07:55:56.94$pcalon/"no phase cal control is implemented here 2006.238.07:55:56.94$4f8m12a/"tpicd=stop 2006.238.07:55:56.94$4f8m12a/vc4f8 2006.238.07:55:56.94$vc4f8/valo=1,532.99 2006.238.07:55:56.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:55:56.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:55:56.94#ibcon#ireg 17 cls_cnt 0 2006.238.07:55:56.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:55:56.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:55:56.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:55:56.94#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:55:56.94#ibcon#first serial, iclass 23, count 0 2006.238.07:55:56.94#ibcon#enter sib2, iclass 23, count 0 2006.238.07:55:56.94#ibcon#flushed, iclass 23, count 0 2006.238.07:55:56.94#ibcon#about to write, iclass 23, count 0 2006.238.07:55:56.94#ibcon#wrote, iclass 23, count 0 2006.238.07:55:56.94#ibcon#about to read 3, iclass 23, count 0 2006.238.07:55:56.98#ibcon#read 3, iclass 23, count 0 2006.238.07:55:56.98#ibcon#about to read 4, iclass 23, count 0 2006.238.07:55:56.98#ibcon#read 4, iclass 23, count 0 2006.238.07:55:56.98#ibcon#about to read 5, iclass 23, count 0 2006.238.07:55:56.98#ibcon#read 5, iclass 23, count 0 2006.238.07:55:56.98#ibcon#about to read 6, iclass 23, count 0 2006.238.07:55:56.98#ibcon#read 6, iclass 23, count 0 2006.238.07:55:56.98#ibcon#end of sib2, iclass 23, count 0 2006.238.07:55:56.98#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:55:56.98#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:55:56.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:55:56.98#ibcon#*before write, iclass 23, count 0 2006.238.07:55:56.98#ibcon#enter sib2, iclass 23, count 0 2006.238.07:55:56.98#ibcon#flushed, iclass 23, count 0 2006.238.07:55:56.98#ibcon#about to write, iclass 23, count 0 2006.238.07:55:56.98#ibcon#wrote, iclass 23, count 0 2006.238.07:55:56.98#ibcon#about to read 3, iclass 23, count 0 2006.238.07:55:57.03#ibcon#read 3, iclass 23, count 0 2006.238.07:55:57.03#ibcon#about to read 4, iclass 23, count 0 2006.238.07:55:57.03#ibcon#read 4, iclass 23, count 0 2006.238.07:55:57.03#ibcon#about to read 5, iclass 23, count 0 2006.238.07:55:57.03#ibcon#read 5, iclass 23, count 0 2006.238.07:55:57.03#ibcon#about to read 6, iclass 23, count 0 2006.238.07:55:57.03#ibcon#read 6, iclass 23, count 0 2006.238.07:55:57.03#ibcon#end of sib2, iclass 23, count 0 2006.238.07:55:57.03#ibcon#*after write, iclass 23, count 0 2006.238.07:55:57.03#ibcon#*before return 0, iclass 23, count 0 2006.238.07:55:57.03#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:55:57.03#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:55:57.03#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:55:57.03#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:55:57.04$vc4f8/va=1,8 2006.238.07:55:57.04#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.07:55:57.04#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.07:55:57.04#ibcon#ireg 11 cls_cnt 2 2006.238.07:55:57.04#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:55:57.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:55:57.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:55:57.04#ibcon#enter wrdev, iclass 25, count 2 2006.238.07:55:57.04#ibcon#first serial, iclass 25, count 2 2006.238.07:55:57.04#ibcon#enter sib2, iclass 25, count 2 2006.238.07:55:57.04#ibcon#flushed, iclass 25, count 2 2006.238.07:55:57.04#ibcon#about to write, iclass 25, count 2 2006.238.07:55:57.04#ibcon#wrote, iclass 25, count 2 2006.238.07:55:57.04#ibcon#about to read 3, iclass 25, count 2 2006.238.07:55:57.06#ibcon#read 3, iclass 25, count 2 2006.238.07:55:57.06#ibcon#about to read 4, iclass 25, count 2 2006.238.07:55:57.06#ibcon#read 4, iclass 25, count 2 2006.238.07:55:57.06#ibcon#about to read 5, iclass 25, count 2 2006.238.07:55:57.06#ibcon#read 5, iclass 25, count 2 2006.238.07:55:57.06#ibcon#about to read 6, iclass 25, count 2 2006.238.07:55:57.06#ibcon#read 6, iclass 25, count 2 2006.238.07:55:57.06#ibcon#end of sib2, iclass 25, count 2 2006.238.07:55:57.06#ibcon#*mode == 0, iclass 25, count 2 2006.238.07:55:57.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.07:55:57.06#ibcon#[25=AT01-08\r\n] 2006.238.07:55:57.06#ibcon#*before write, iclass 25, count 2 2006.238.07:55:57.06#ibcon#enter sib2, iclass 25, count 2 2006.238.07:55:57.06#ibcon#flushed, iclass 25, count 2 2006.238.07:55:57.06#ibcon#about to write, iclass 25, count 2 2006.238.07:55:57.06#ibcon#wrote, iclass 25, count 2 2006.238.07:55:57.06#ibcon#about to read 3, iclass 25, count 2 2006.238.07:55:57.10#ibcon#read 3, iclass 25, count 2 2006.238.07:55:57.10#ibcon#about to read 4, iclass 25, count 2 2006.238.07:55:57.10#ibcon#read 4, iclass 25, count 2 2006.238.07:55:57.10#ibcon#about to read 5, iclass 25, count 2 2006.238.07:55:57.10#ibcon#read 5, iclass 25, count 2 2006.238.07:55:57.10#ibcon#about to read 6, iclass 25, count 2 2006.238.07:55:57.10#ibcon#read 6, iclass 25, count 2 2006.238.07:55:57.10#ibcon#end of sib2, iclass 25, count 2 2006.238.07:55:57.10#ibcon#*after write, iclass 25, count 2 2006.238.07:55:57.10#ibcon#*before return 0, iclass 25, count 2 2006.238.07:55:57.10#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:55:57.10#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:55:57.10#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.07:55:57.10#ibcon#ireg 7 cls_cnt 0 2006.238.07:55:57.10#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:55:57.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:55:57.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:55:57.21#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:55:57.21#ibcon#first serial, iclass 25, count 0 2006.238.07:55:57.21#ibcon#enter sib2, iclass 25, count 0 2006.238.07:55:57.21#ibcon#flushed, iclass 25, count 0 2006.238.07:55:57.21#ibcon#about to write, iclass 25, count 0 2006.238.07:55:57.21#ibcon#wrote, iclass 25, count 0 2006.238.07:55:57.21#ibcon#about to read 3, iclass 25, count 0 2006.238.07:55:57.23#ibcon#read 3, iclass 25, count 0 2006.238.07:55:57.23#ibcon#about to read 4, iclass 25, count 0 2006.238.07:55:57.23#ibcon#read 4, iclass 25, count 0 2006.238.07:55:57.23#ibcon#about to read 5, iclass 25, count 0 2006.238.07:55:57.23#ibcon#read 5, iclass 25, count 0 2006.238.07:55:57.23#ibcon#about to read 6, iclass 25, count 0 2006.238.07:55:57.23#ibcon#read 6, iclass 25, count 0 2006.238.07:55:57.23#ibcon#end of sib2, iclass 25, count 0 2006.238.07:55:57.23#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:55:57.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:55:57.23#ibcon#[25=USB\r\n] 2006.238.07:55:57.23#ibcon#*before write, iclass 25, count 0 2006.238.07:55:57.23#ibcon#enter sib2, iclass 25, count 0 2006.238.07:55:57.23#ibcon#flushed, iclass 25, count 0 2006.238.07:55:57.23#ibcon#about to write, iclass 25, count 0 2006.238.07:55:57.23#ibcon#wrote, iclass 25, count 0 2006.238.07:55:57.23#ibcon#about to read 3, iclass 25, count 0 2006.238.07:55:57.26#ibcon#read 3, iclass 25, count 0 2006.238.07:55:57.26#ibcon#about to read 4, iclass 25, count 0 2006.238.07:55:57.26#ibcon#read 4, iclass 25, count 0 2006.238.07:55:57.26#ibcon#about to read 5, iclass 25, count 0 2006.238.07:55:57.26#ibcon#read 5, iclass 25, count 0 2006.238.07:55:57.26#ibcon#about to read 6, iclass 25, count 0 2006.238.07:55:57.26#ibcon#read 6, iclass 25, count 0 2006.238.07:55:57.26#ibcon#end of sib2, iclass 25, count 0 2006.238.07:55:57.26#ibcon#*after write, iclass 25, count 0 2006.238.07:55:57.26#ibcon#*before return 0, iclass 25, count 0 2006.238.07:55:57.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:55:57.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:55:57.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:55:57.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:55:57.27$vc4f8/valo=2,572.99 2006.238.07:55:57.27#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:55:57.27#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:55:57.27#ibcon#ireg 17 cls_cnt 0 2006.238.07:55:57.27#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:55:57.27#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:55:57.27#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:55:57.27#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:55:57.27#ibcon#first serial, iclass 27, count 0 2006.238.07:55:57.27#ibcon#enter sib2, iclass 27, count 0 2006.238.07:55:57.27#ibcon#flushed, iclass 27, count 0 2006.238.07:55:57.27#ibcon#about to write, iclass 27, count 0 2006.238.07:55:57.27#ibcon#wrote, iclass 27, count 0 2006.238.07:55:57.27#ibcon#about to read 3, iclass 27, count 0 2006.238.07:55:57.28#ibcon#read 3, iclass 27, count 0 2006.238.07:55:57.28#ibcon#about to read 4, iclass 27, count 0 2006.238.07:55:57.28#ibcon#read 4, iclass 27, count 0 2006.238.07:55:57.28#ibcon#about to read 5, iclass 27, count 0 2006.238.07:55:57.28#ibcon#read 5, iclass 27, count 0 2006.238.07:55:57.28#ibcon#about to read 6, iclass 27, count 0 2006.238.07:55:57.28#ibcon#read 6, iclass 27, count 0 2006.238.07:55:57.28#ibcon#end of sib2, iclass 27, count 0 2006.238.07:55:57.28#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:55:57.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:55:57.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:55:57.28#ibcon#*before write, iclass 27, count 0 2006.238.07:55:57.28#ibcon#enter sib2, iclass 27, count 0 2006.238.07:55:57.29#ibcon#flushed, iclass 27, count 0 2006.238.07:55:57.29#ibcon#about to write, iclass 27, count 0 2006.238.07:55:57.29#ibcon#wrote, iclass 27, count 0 2006.238.07:55:57.29#ibcon#about to read 3, iclass 27, count 0 2006.238.07:55:57.32#ibcon#read 3, iclass 27, count 0 2006.238.07:55:57.32#ibcon#about to read 4, iclass 27, count 0 2006.238.07:55:57.32#ibcon#read 4, iclass 27, count 0 2006.238.07:55:57.32#ibcon#about to read 5, iclass 27, count 0 2006.238.07:55:57.32#ibcon#read 5, iclass 27, count 0 2006.238.07:55:57.32#ibcon#about to read 6, iclass 27, count 0 2006.238.07:55:57.32#ibcon#read 6, iclass 27, count 0 2006.238.07:55:57.32#ibcon#end of sib2, iclass 27, count 0 2006.238.07:55:57.32#ibcon#*after write, iclass 27, count 0 2006.238.07:55:57.32#ibcon#*before return 0, iclass 27, count 0 2006.238.07:55:57.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:55:57.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:55:57.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:55:57.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:55:57.33$vc4f8/va=2,7 2006.238.07:55:57.33#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.07:55:57.33#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.07:55:57.33#ibcon#ireg 11 cls_cnt 2 2006.238.07:55:57.33#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:55:57.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:55:57.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:55:57.37#ibcon#enter wrdev, iclass 29, count 2 2006.238.07:55:57.37#ibcon#first serial, iclass 29, count 2 2006.238.07:55:57.37#ibcon#enter sib2, iclass 29, count 2 2006.238.07:55:57.37#ibcon#flushed, iclass 29, count 2 2006.238.07:55:57.37#ibcon#about to write, iclass 29, count 2 2006.238.07:55:57.37#ibcon#wrote, iclass 29, count 2 2006.238.07:55:57.37#ibcon#about to read 3, iclass 29, count 2 2006.238.07:55:57.40#ibcon#read 3, iclass 29, count 2 2006.238.07:55:57.40#ibcon#about to read 4, iclass 29, count 2 2006.238.07:55:57.40#ibcon#read 4, iclass 29, count 2 2006.238.07:55:57.40#ibcon#about to read 5, iclass 29, count 2 2006.238.07:55:57.40#ibcon#read 5, iclass 29, count 2 2006.238.07:55:57.40#ibcon#about to read 6, iclass 29, count 2 2006.238.07:55:57.40#ibcon#read 6, iclass 29, count 2 2006.238.07:55:57.40#ibcon#end of sib2, iclass 29, count 2 2006.238.07:55:57.40#ibcon#*mode == 0, iclass 29, count 2 2006.238.07:55:57.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.07:55:57.40#ibcon#[25=AT02-07\r\n] 2006.238.07:55:57.40#ibcon#*before write, iclass 29, count 2 2006.238.07:55:57.40#ibcon#enter sib2, iclass 29, count 2 2006.238.07:55:57.40#ibcon#flushed, iclass 29, count 2 2006.238.07:55:57.40#ibcon#about to write, iclass 29, count 2 2006.238.07:55:57.40#ibcon#wrote, iclass 29, count 2 2006.238.07:55:57.40#ibcon#about to read 3, iclass 29, count 2 2006.238.07:55:57.43#ibcon#read 3, iclass 29, count 2 2006.238.07:55:57.43#ibcon#about to read 4, iclass 29, count 2 2006.238.07:55:57.43#ibcon#read 4, iclass 29, count 2 2006.238.07:55:57.43#ibcon#about to read 5, iclass 29, count 2 2006.238.07:55:57.43#ibcon#read 5, iclass 29, count 2 2006.238.07:55:57.43#ibcon#about to read 6, iclass 29, count 2 2006.238.07:55:57.43#ibcon#read 6, iclass 29, count 2 2006.238.07:55:57.43#ibcon#end of sib2, iclass 29, count 2 2006.238.07:55:57.43#ibcon#*after write, iclass 29, count 2 2006.238.07:55:57.43#ibcon#*before return 0, iclass 29, count 2 2006.238.07:55:57.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:55:57.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:55:57.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.07:55:57.43#ibcon#ireg 7 cls_cnt 0 2006.238.07:55:57.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:55:57.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:55:57.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:55:57.55#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:55:57.55#ibcon#first serial, iclass 29, count 0 2006.238.07:55:57.55#ibcon#enter sib2, iclass 29, count 0 2006.238.07:55:57.55#ibcon#flushed, iclass 29, count 0 2006.238.07:55:57.55#ibcon#about to write, iclass 29, count 0 2006.238.07:55:57.55#ibcon#wrote, iclass 29, count 0 2006.238.07:55:57.55#ibcon#about to read 3, iclass 29, count 0 2006.238.07:55:57.57#ibcon#read 3, iclass 29, count 0 2006.238.07:55:57.57#ibcon#about to read 4, iclass 29, count 0 2006.238.07:55:57.57#ibcon#read 4, iclass 29, count 0 2006.238.07:55:57.57#ibcon#about to read 5, iclass 29, count 0 2006.238.07:55:57.57#ibcon#read 5, iclass 29, count 0 2006.238.07:55:57.57#ibcon#about to read 6, iclass 29, count 0 2006.238.07:55:57.57#ibcon#read 6, iclass 29, count 0 2006.238.07:55:57.57#ibcon#end of sib2, iclass 29, count 0 2006.238.07:55:57.57#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:55:57.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:55:57.57#ibcon#[25=USB\r\n] 2006.238.07:55:57.57#ibcon#*before write, iclass 29, count 0 2006.238.07:55:57.57#ibcon#enter sib2, iclass 29, count 0 2006.238.07:55:57.57#ibcon#flushed, iclass 29, count 0 2006.238.07:55:57.57#ibcon#about to write, iclass 29, count 0 2006.238.07:55:57.57#ibcon#wrote, iclass 29, count 0 2006.238.07:55:57.57#ibcon#about to read 3, iclass 29, count 0 2006.238.07:55:57.60#ibcon#read 3, iclass 29, count 0 2006.238.07:55:57.60#ibcon#about to read 4, iclass 29, count 0 2006.238.07:55:57.60#ibcon#read 4, iclass 29, count 0 2006.238.07:55:57.60#ibcon#about to read 5, iclass 29, count 0 2006.238.07:55:57.60#ibcon#read 5, iclass 29, count 0 2006.238.07:55:57.60#ibcon#about to read 6, iclass 29, count 0 2006.238.07:55:57.60#ibcon#read 6, iclass 29, count 0 2006.238.07:55:57.60#ibcon#end of sib2, iclass 29, count 0 2006.238.07:55:57.60#ibcon#*after write, iclass 29, count 0 2006.238.07:55:57.60#ibcon#*before return 0, iclass 29, count 0 2006.238.07:55:57.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:55:57.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:55:57.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:55:57.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:55:57.61$vc4f8/valo=3,672.99 2006.238.07:55:57.61#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.07:55:57.61#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.07:55:57.61#ibcon#ireg 17 cls_cnt 0 2006.238.07:55:57.61#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:55:57.61#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:55:57.61#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:55:57.61#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:55:57.61#ibcon#first serial, iclass 31, count 0 2006.238.07:55:57.61#ibcon#enter sib2, iclass 31, count 0 2006.238.07:55:57.61#ibcon#flushed, iclass 31, count 0 2006.238.07:55:57.61#ibcon#about to write, iclass 31, count 0 2006.238.07:55:57.61#ibcon#wrote, iclass 31, count 0 2006.238.07:55:57.61#ibcon#about to read 3, iclass 31, count 0 2006.238.07:55:57.62#ibcon#read 3, iclass 31, count 0 2006.238.07:55:57.62#ibcon#about to read 4, iclass 31, count 0 2006.238.07:55:57.62#ibcon#read 4, iclass 31, count 0 2006.238.07:55:57.62#ibcon#about to read 5, iclass 31, count 0 2006.238.07:55:57.62#ibcon#read 5, iclass 31, count 0 2006.238.07:55:57.62#ibcon#about to read 6, iclass 31, count 0 2006.238.07:55:57.62#ibcon#read 6, iclass 31, count 0 2006.238.07:55:57.62#ibcon#end of sib2, iclass 31, count 0 2006.238.07:55:57.62#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:55:57.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:55:57.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:55:57.62#ibcon#*before write, iclass 31, count 0 2006.238.07:55:57.62#ibcon#enter sib2, iclass 31, count 0 2006.238.07:55:57.62#ibcon#flushed, iclass 31, count 0 2006.238.07:55:57.62#ibcon#about to write, iclass 31, count 0 2006.238.07:55:57.62#ibcon#wrote, iclass 31, count 0 2006.238.07:55:57.62#ibcon#about to read 3, iclass 31, count 0 2006.238.07:55:57.66#ibcon#read 3, iclass 31, count 0 2006.238.07:55:57.66#ibcon#about to read 4, iclass 31, count 0 2006.238.07:55:57.66#ibcon#read 4, iclass 31, count 0 2006.238.07:55:57.66#ibcon#about to read 5, iclass 31, count 0 2006.238.07:55:57.66#ibcon#read 5, iclass 31, count 0 2006.238.07:55:57.66#ibcon#about to read 6, iclass 31, count 0 2006.238.07:55:57.66#ibcon#read 6, iclass 31, count 0 2006.238.07:55:57.66#ibcon#end of sib2, iclass 31, count 0 2006.238.07:55:57.66#ibcon#*after write, iclass 31, count 0 2006.238.07:55:57.66#ibcon#*before return 0, iclass 31, count 0 2006.238.07:55:57.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:55:57.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:55:57.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:55:57.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:55:57.67$vc4f8/va=3,7 2006.238.07:55:57.67#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:55:57.67#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:55:57.67#ibcon#ireg 11 cls_cnt 2 2006.238.07:55:57.67#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:55:57.71#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:55:57.71#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:55:57.71#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:55:57.71#ibcon#first serial, iclass 33, count 2 2006.238.07:55:57.71#ibcon#enter sib2, iclass 33, count 2 2006.238.07:55:57.71#ibcon#flushed, iclass 33, count 2 2006.238.07:55:57.71#ibcon#about to write, iclass 33, count 2 2006.238.07:55:57.71#ibcon#wrote, iclass 33, count 2 2006.238.07:55:57.71#ibcon#about to read 3, iclass 33, count 2 2006.238.07:55:57.74#ibcon#read 3, iclass 33, count 2 2006.238.07:55:57.74#ibcon#about to read 4, iclass 33, count 2 2006.238.07:55:57.74#ibcon#read 4, iclass 33, count 2 2006.238.07:55:57.74#ibcon#about to read 5, iclass 33, count 2 2006.238.07:55:57.74#ibcon#read 5, iclass 33, count 2 2006.238.07:55:57.74#ibcon#about to read 6, iclass 33, count 2 2006.238.07:55:57.74#ibcon#read 6, iclass 33, count 2 2006.238.07:55:57.74#ibcon#end of sib2, iclass 33, count 2 2006.238.07:55:57.74#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:55:57.74#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:55:57.74#ibcon#[25=AT03-07\r\n] 2006.238.07:55:57.74#ibcon#*before write, iclass 33, count 2 2006.238.07:55:57.74#ibcon#enter sib2, iclass 33, count 2 2006.238.07:55:57.74#ibcon#flushed, iclass 33, count 2 2006.238.07:55:57.74#ibcon#about to write, iclass 33, count 2 2006.238.07:55:57.74#ibcon#wrote, iclass 33, count 2 2006.238.07:55:57.74#ibcon#about to read 3, iclass 33, count 2 2006.238.07:55:57.77#ibcon#read 3, iclass 33, count 2 2006.238.07:55:57.77#ibcon#about to read 4, iclass 33, count 2 2006.238.07:55:57.77#ibcon#read 4, iclass 33, count 2 2006.238.07:55:57.77#ibcon#about to read 5, iclass 33, count 2 2006.238.07:55:57.77#ibcon#read 5, iclass 33, count 2 2006.238.07:55:57.77#ibcon#about to read 6, iclass 33, count 2 2006.238.07:55:57.77#ibcon#read 6, iclass 33, count 2 2006.238.07:55:57.77#ibcon#end of sib2, iclass 33, count 2 2006.238.07:55:57.77#ibcon#*after write, iclass 33, count 2 2006.238.07:55:57.77#ibcon#*before return 0, iclass 33, count 2 2006.238.07:55:57.77#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:55:57.77#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:55:57.77#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:55:57.77#ibcon#ireg 7 cls_cnt 0 2006.238.07:55:57.77#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:55:57.89#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:55:57.89#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:55:57.89#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:55:57.89#ibcon#first serial, iclass 33, count 0 2006.238.07:55:57.89#ibcon#enter sib2, iclass 33, count 0 2006.238.07:55:57.89#ibcon#flushed, iclass 33, count 0 2006.238.07:55:57.89#ibcon#about to write, iclass 33, count 0 2006.238.07:55:57.89#ibcon#wrote, iclass 33, count 0 2006.238.07:55:57.89#ibcon#about to read 3, iclass 33, count 0 2006.238.07:55:57.91#ibcon#read 3, iclass 33, count 0 2006.238.07:55:57.91#ibcon#about to read 4, iclass 33, count 0 2006.238.07:55:57.91#ibcon#read 4, iclass 33, count 0 2006.238.07:55:57.91#ibcon#about to read 5, iclass 33, count 0 2006.238.07:55:57.91#ibcon#read 5, iclass 33, count 0 2006.238.07:55:57.91#ibcon#about to read 6, iclass 33, count 0 2006.238.07:55:57.91#ibcon#read 6, iclass 33, count 0 2006.238.07:55:57.91#ibcon#end of sib2, iclass 33, count 0 2006.238.07:55:57.91#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:55:57.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:55:57.91#ibcon#[25=USB\r\n] 2006.238.07:55:57.91#ibcon#*before write, iclass 33, count 0 2006.238.07:55:57.91#ibcon#enter sib2, iclass 33, count 0 2006.238.07:55:57.91#ibcon#flushed, iclass 33, count 0 2006.238.07:55:57.91#ibcon#about to write, iclass 33, count 0 2006.238.07:55:57.91#ibcon#wrote, iclass 33, count 0 2006.238.07:55:57.91#ibcon#about to read 3, iclass 33, count 0 2006.238.07:55:57.94#ibcon#read 3, iclass 33, count 0 2006.238.07:55:57.94#ibcon#about to read 4, iclass 33, count 0 2006.238.07:55:57.94#ibcon#read 4, iclass 33, count 0 2006.238.07:55:57.94#ibcon#about to read 5, iclass 33, count 0 2006.238.07:55:57.94#ibcon#read 5, iclass 33, count 0 2006.238.07:55:57.94#ibcon#about to read 6, iclass 33, count 0 2006.238.07:55:57.94#ibcon#read 6, iclass 33, count 0 2006.238.07:55:57.94#ibcon#end of sib2, iclass 33, count 0 2006.238.07:55:57.94#ibcon#*after write, iclass 33, count 0 2006.238.07:55:57.94#ibcon#*before return 0, iclass 33, count 0 2006.238.07:55:57.94#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:55:57.94#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:55:57.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:55:57.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:55:57.95$vc4f8/valo=4,832.99 2006.238.07:55:57.95#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:55:57.95#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:55:57.95#ibcon#ireg 17 cls_cnt 0 2006.238.07:55:57.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:55:57.95#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:55:57.95#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:55:57.95#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:55:57.95#ibcon#first serial, iclass 35, count 0 2006.238.07:55:57.95#ibcon#enter sib2, iclass 35, count 0 2006.238.07:55:57.95#ibcon#flushed, iclass 35, count 0 2006.238.07:55:57.95#ibcon#about to write, iclass 35, count 0 2006.238.07:55:57.95#ibcon#wrote, iclass 35, count 0 2006.238.07:55:57.95#ibcon#about to read 3, iclass 35, count 0 2006.238.07:55:57.96#ibcon#read 3, iclass 35, count 0 2006.238.07:55:57.96#ibcon#about to read 4, iclass 35, count 0 2006.238.07:55:57.96#ibcon#read 4, iclass 35, count 0 2006.238.07:55:57.96#ibcon#about to read 5, iclass 35, count 0 2006.238.07:55:57.96#ibcon#read 5, iclass 35, count 0 2006.238.07:55:57.96#ibcon#about to read 6, iclass 35, count 0 2006.238.07:55:57.96#ibcon#read 6, iclass 35, count 0 2006.238.07:55:57.96#ibcon#end of sib2, iclass 35, count 0 2006.238.07:55:57.96#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:55:57.96#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:55:57.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:55:57.96#ibcon#*before write, iclass 35, count 0 2006.238.07:55:57.96#ibcon#enter sib2, iclass 35, count 0 2006.238.07:55:57.96#ibcon#flushed, iclass 35, count 0 2006.238.07:55:57.96#ibcon#about to write, iclass 35, count 0 2006.238.07:55:57.96#ibcon#wrote, iclass 35, count 0 2006.238.07:55:57.96#ibcon#about to read 3, iclass 35, count 0 2006.238.07:55:58.00#ibcon#read 3, iclass 35, count 0 2006.238.07:55:58.00#ibcon#about to read 4, iclass 35, count 0 2006.238.07:55:58.00#ibcon#read 4, iclass 35, count 0 2006.238.07:55:58.00#ibcon#about to read 5, iclass 35, count 0 2006.238.07:55:58.00#ibcon#read 5, iclass 35, count 0 2006.238.07:55:58.00#ibcon#about to read 6, iclass 35, count 0 2006.238.07:55:58.00#ibcon#read 6, iclass 35, count 0 2006.238.07:55:58.00#ibcon#end of sib2, iclass 35, count 0 2006.238.07:55:58.00#ibcon#*after write, iclass 35, count 0 2006.238.07:55:58.00#ibcon#*before return 0, iclass 35, count 0 2006.238.07:55:58.00#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:55:58.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:55:58.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:55:58.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:55:58.01$vc4f8/va=4,7 2006.238.07:55:58.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.07:55:58.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.07:55:58.01#ibcon#ireg 11 cls_cnt 2 2006.238.07:55:58.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:55:58.05#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:55:58.05#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:55:58.05#ibcon#enter wrdev, iclass 37, count 2 2006.238.07:55:58.05#ibcon#first serial, iclass 37, count 2 2006.238.07:55:58.05#ibcon#enter sib2, iclass 37, count 2 2006.238.07:55:58.05#ibcon#flushed, iclass 37, count 2 2006.238.07:55:58.05#ibcon#about to write, iclass 37, count 2 2006.238.07:55:58.05#ibcon#wrote, iclass 37, count 2 2006.238.07:55:58.05#ibcon#about to read 3, iclass 37, count 2 2006.238.07:55:58.07#ibcon#read 3, iclass 37, count 2 2006.238.07:55:58.07#ibcon#about to read 4, iclass 37, count 2 2006.238.07:55:58.07#ibcon#read 4, iclass 37, count 2 2006.238.07:55:58.07#ibcon#about to read 5, iclass 37, count 2 2006.238.07:55:58.07#ibcon#read 5, iclass 37, count 2 2006.238.07:55:58.07#ibcon#about to read 6, iclass 37, count 2 2006.238.07:55:58.07#ibcon#read 6, iclass 37, count 2 2006.238.07:55:58.07#ibcon#end of sib2, iclass 37, count 2 2006.238.07:55:58.07#ibcon#*mode == 0, iclass 37, count 2 2006.238.07:55:58.07#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.07:55:58.07#ibcon#[25=AT04-07\r\n] 2006.238.07:55:58.07#ibcon#*before write, iclass 37, count 2 2006.238.07:55:58.07#ibcon#enter sib2, iclass 37, count 2 2006.238.07:55:58.07#ibcon#flushed, iclass 37, count 2 2006.238.07:55:58.07#ibcon#about to write, iclass 37, count 2 2006.238.07:55:58.07#ibcon#wrote, iclass 37, count 2 2006.238.07:55:58.07#ibcon#about to read 3, iclass 37, count 2 2006.238.07:55:58.10#ibcon#read 3, iclass 37, count 2 2006.238.07:55:58.10#ibcon#about to read 4, iclass 37, count 2 2006.238.07:55:58.10#ibcon#read 4, iclass 37, count 2 2006.238.07:55:58.10#ibcon#about to read 5, iclass 37, count 2 2006.238.07:55:58.10#ibcon#read 5, iclass 37, count 2 2006.238.07:55:58.10#ibcon#about to read 6, iclass 37, count 2 2006.238.07:55:58.10#ibcon#read 6, iclass 37, count 2 2006.238.07:55:58.10#ibcon#end of sib2, iclass 37, count 2 2006.238.07:55:58.10#ibcon#*after write, iclass 37, count 2 2006.238.07:55:58.10#ibcon#*before return 0, iclass 37, count 2 2006.238.07:55:58.10#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:55:58.10#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:55:58.10#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.07:55:58.10#ibcon#ireg 7 cls_cnt 0 2006.238.07:55:58.10#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:55:58.22#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:55:58.22#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:55:58.22#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:55:58.22#ibcon#first serial, iclass 37, count 0 2006.238.07:55:58.22#ibcon#enter sib2, iclass 37, count 0 2006.238.07:55:58.22#ibcon#flushed, iclass 37, count 0 2006.238.07:55:58.22#ibcon#about to write, iclass 37, count 0 2006.238.07:55:58.22#ibcon#wrote, iclass 37, count 0 2006.238.07:55:58.22#ibcon#about to read 3, iclass 37, count 0 2006.238.07:55:58.24#ibcon#read 3, iclass 37, count 0 2006.238.07:55:58.24#ibcon#about to read 4, iclass 37, count 0 2006.238.07:55:58.24#ibcon#read 4, iclass 37, count 0 2006.238.07:55:58.24#ibcon#about to read 5, iclass 37, count 0 2006.238.07:55:58.24#ibcon#read 5, iclass 37, count 0 2006.238.07:55:58.24#ibcon#about to read 6, iclass 37, count 0 2006.238.07:55:58.24#ibcon#read 6, iclass 37, count 0 2006.238.07:55:58.24#ibcon#end of sib2, iclass 37, count 0 2006.238.07:55:58.24#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:55:58.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:55:58.24#ibcon#[25=USB\r\n] 2006.238.07:55:58.24#ibcon#*before write, iclass 37, count 0 2006.238.07:55:58.24#ibcon#enter sib2, iclass 37, count 0 2006.238.07:55:58.24#ibcon#flushed, iclass 37, count 0 2006.238.07:55:58.24#ibcon#about to write, iclass 37, count 0 2006.238.07:55:58.24#ibcon#wrote, iclass 37, count 0 2006.238.07:55:58.24#ibcon#about to read 3, iclass 37, count 0 2006.238.07:55:58.27#ibcon#read 3, iclass 37, count 0 2006.238.07:55:58.27#ibcon#about to read 4, iclass 37, count 0 2006.238.07:55:58.27#ibcon#read 4, iclass 37, count 0 2006.238.07:55:58.27#ibcon#about to read 5, iclass 37, count 0 2006.238.07:55:58.27#ibcon#read 5, iclass 37, count 0 2006.238.07:55:58.27#ibcon#about to read 6, iclass 37, count 0 2006.238.07:55:58.27#ibcon#read 6, iclass 37, count 0 2006.238.07:55:58.27#ibcon#end of sib2, iclass 37, count 0 2006.238.07:55:58.27#ibcon#*after write, iclass 37, count 0 2006.238.07:55:58.27#ibcon#*before return 0, iclass 37, count 0 2006.238.07:55:58.27#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:55:58.27#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:55:58.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:55:58.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:55:58.28$vc4f8/valo=5,652.99 2006.238.07:55:58.28#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.07:55:58.28#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.07:55:58.28#ibcon#ireg 17 cls_cnt 0 2006.238.07:55:58.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:55:58.28#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:55:58.28#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:55:58.28#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:55:58.28#ibcon#first serial, iclass 39, count 0 2006.238.07:55:58.28#ibcon#enter sib2, iclass 39, count 0 2006.238.07:55:58.28#ibcon#flushed, iclass 39, count 0 2006.238.07:55:58.28#ibcon#about to write, iclass 39, count 0 2006.238.07:55:58.28#ibcon#wrote, iclass 39, count 0 2006.238.07:55:58.28#ibcon#about to read 3, iclass 39, count 0 2006.238.07:55:58.29#ibcon#read 3, iclass 39, count 0 2006.238.07:55:58.29#ibcon#about to read 4, iclass 39, count 0 2006.238.07:55:58.29#ibcon#read 4, iclass 39, count 0 2006.238.07:55:58.29#ibcon#about to read 5, iclass 39, count 0 2006.238.07:55:58.29#ibcon#read 5, iclass 39, count 0 2006.238.07:55:58.29#ibcon#about to read 6, iclass 39, count 0 2006.238.07:55:58.29#ibcon#read 6, iclass 39, count 0 2006.238.07:55:58.29#ibcon#end of sib2, iclass 39, count 0 2006.238.07:55:58.29#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:55:58.29#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:55:58.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:55:58.29#ibcon#*before write, iclass 39, count 0 2006.238.07:55:58.29#ibcon#enter sib2, iclass 39, count 0 2006.238.07:55:58.29#ibcon#flushed, iclass 39, count 0 2006.238.07:55:58.29#ibcon#about to write, iclass 39, count 0 2006.238.07:55:58.29#ibcon#wrote, iclass 39, count 0 2006.238.07:55:58.29#ibcon#about to read 3, iclass 39, count 0 2006.238.07:55:58.33#ibcon#read 3, iclass 39, count 0 2006.238.07:55:58.33#ibcon#about to read 4, iclass 39, count 0 2006.238.07:55:58.33#ibcon#read 4, iclass 39, count 0 2006.238.07:55:58.33#ibcon#about to read 5, iclass 39, count 0 2006.238.07:55:58.33#ibcon#read 5, iclass 39, count 0 2006.238.07:55:58.33#ibcon#about to read 6, iclass 39, count 0 2006.238.07:55:58.33#ibcon#read 6, iclass 39, count 0 2006.238.07:55:58.33#ibcon#end of sib2, iclass 39, count 0 2006.238.07:55:58.33#ibcon#*after write, iclass 39, count 0 2006.238.07:55:58.33#ibcon#*before return 0, iclass 39, count 0 2006.238.07:55:58.33#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:55:58.33#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:55:58.33#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:55:58.33#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:55:58.34$vc4f8/va=5,8 2006.238.07:55:58.34#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.07:55:58.34#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.07:55:58.34#ibcon#ireg 11 cls_cnt 2 2006.238.07:55:58.34#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:55:58.38#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:55:58.38#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:55:58.38#ibcon#enter wrdev, iclass 3, count 2 2006.238.07:55:58.38#ibcon#first serial, iclass 3, count 2 2006.238.07:55:58.38#ibcon#enter sib2, iclass 3, count 2 2006.238.07:55:58.38#ibcon#flushed, iclass 3, count 2 2006.238.07:55:58.38#ibcon#about to write, iclass 3, count 2 2006.238.07:55:58.38#ibcon#wrote, iclass 3, count 2 2006.238.07:55:58.38#ibcon#about to read 3, iclass 3, count 2 2006.238.07:55:58.40#ibcon#read 3, iclass 3, count 2 2006.238.07:55:58.40#ibcon#about to read 4, iclass 3, count 2 2006.238.07:55:58.40#ibcon#read 4, iclass 3, count 2 2006.238.07:55:58.40#ibcon#about to read 5, iclass 3, count 2 2006.238.07:55:58.40#ibcon#read 5, iclass 3, count 2 2006.238.07:55:58.40#ibcon#about to read 6, iclass 3, count 2 2006.238.07:55:58.40#ibcon#read 6, iclass 3, count 2 2006.238.07:55:58.40#ibcon#end of sib2, iclass 3, count 2 2006.238.07:55:58.40#ibcon#*mode == 0, iclass 3, count 2 2006.238.07:55:58.40#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.07:55:58.40#ibcon#[25=AT05-08\r\n] 2006.238.07:55:58.40#ibcon#*before write, iclass 3, count 2 2006.238.07:55:58.40#ibcon#enter sib2, iclass 3, count 2 2006.238.07:55:58.40#ibcon#flushed, iclass 3, count 2 2006.238.07:55:58.40#ibcon#about to write, iclass 3, count 2 2006.238.07:55:58.40#ibcon#wrote, iclass 3, count 2 2006.238.07:55:58.40#ibcon#about to read 3, iclass 3, count 2 2006.238.07:55:58.43#ibcon#read 3, iclass 3, count 2 2006.238.07:55:58.43#ibcon#about to read 4, iclass 3, count 2 2006.238.07:55:58.43#ibcon#read 4, iclass 3, count 2 2006.238.07:55:58.43#ibcon#about to read 5, iclass 3, count 2 2006.238.07:55:58.43#ibcon#read 5, iclass 3, count 2 2006.238.07:55:58.43#ibcon#about to read 6, iclass 3, count 2 2006.238.07:55:58.43#ibcon#read 6, iclass 3, count 2 2006.238.07:55:58.43#ibcon#end of sib2, iclass 3, count 2 2006.238.07:55:58.43#ibcon#*after write, iclass 3, count 2 2006.238.07:55:58.43#ibcon#*before return 0, iclass 3, count 2 2006.238.07:55:58.43#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:55:58.43#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:55:58.43#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.07:55:58.43#ibcon#ireg 7 cls_cnt 0 2006.238.07:55:58.43#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:55:58.55#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:55:58.55#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:55:58.55#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:55:58.55#ibcon#first serial, iclass 3, count 0 2006.238.07:55:58.55#ibcon#enter sib2, iclass 3, count 0 2006.238.07:55:58.55#ibcon#flushed, iclass 3, count 0 2006.238.07:55:58.55#ibcon#about to write, iclass 3, count 0 2006.238.07:55:58.55#ibcon#wrote, iclass 3, count 0 2006.238.07:55:58.55#ibcon#about to read 3, iclass 3, count 0 2006.238.07:55:58.57#ibcon#read 3, iclass 3, count 0 2006.238.07:55:58.57#ibcon#about to read 4, iclass 3, count 0 2006.238.07:55:58.57#ibcon#read 4, iclass 3, count 0 2006.238.07:55:58.57#ibcon#about to read 5, iclass 3, count 0 2006.238.07:55:58.57#ibcon#read 5, iclass 3, count 0 2006.238.07:55:58.57#ibcon#about to read 6, iclass 3, count 0 2006.238.07:55:58.57#ibcon#read 6, iclass 3, count 0 2006.238.07:55:58.57#ibcon#end of sib2, iclass 3, count 0 2006.238.07:55:58.57#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:55:58.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:55:58.57#ibcon#[25=USB\r\n] 2006.238.07:55:58.57#ibcon#*before write, iclass 3, count 0 2006.238.07:55:58.57#ibcon#enter sib2, iclass 3, count 0 2006.238.07:55:58.57#ibcon#flushed, iclass 3, count 0 2006.238.07:55:58.57#ibcon#about to write, iclass 3, count 0 2006.238.07:55:58.57#ibcon#wrote, iclass 3, count 0 2006.238.07:55:58.57#ibcon#about to read 3, iclass 3, count 0 2006.238.07:55:58.60#ibcon#read 3, iclass 3, count 0 2006.238.07:55:58.60#ibcon#about to read 4, iclass 3, count 0 2006.238.07:55:58.60#ibcon#read 4, iclass 3, count 0 2006.238.07:55:58.60#ibcon#about to read 5, iclass 3, count 0 2006.238.07:55:58.60#ibcon#read 5, iclass 3, count 0 2006.238.07:55:58.60#ibcon#about to read 6, iclass 3, count 0 2006.238.07:55:58.60#ibcon#read 6, iclass 3, count 0 2006.238.07:55:58.60#ibcon#end of sib2, iclass 3, count 0 2006.238.07:55:58.60#ibcon#*after write, iclass 3, count 0 2006.238.07:55:58.60#ibcon#*before return 0, iclass 3, count 0 2006.238.07:55:58.60#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:55:58.60#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:55:58.60#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:55:58.60#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:55:58.61$vc4f8/valo=6,772.99 2006.238.07:55:58.61#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.07:55:58.61#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.07:55:58.61#ibcon#ireg 17 cls_cnt 0 2006.238.07:55:58.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:55:58.61#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:55:58.61#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:55:58.61#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:55:58.61#ibcon#first serial, iclass 5, count 0 2006.238.07:55:58.61#ibcon#enter sib2, iclass 5, count 0 2006.238.07:55:58.61#ibcon#flushed, iclass 5, count 0 2006.238.07:55:58.61#ibcon#about to write, iclass 5, count 0 2006.238.07:55:58.61#ibcon#wrote, iclass 5, count 0 2006.238.07:55:58.61#ibcon#about to read 3, iclass 5, count 0 2006.238.07:55:58.62#ibcon#read 3, iclass 5, count 0 2006.238.07:55:58.62#ibcon#about to read 4, iclass 5, count 0 2006.238.07:55:58.62#ibcon#read 4, iclass 5, count 0 2006.238.07:55:58.62#ibcon#about to read 5, iclass 5, count 0 2006.238.07:55:58.62#ibcon#read 5, iclass 5, count 0 2006.238.07:55:58.62#ibcon#about to read 6, iclass 5, count 0 2006.238.07:55:58.62#ibcon#read 6, iclass 5, count 0 2006.238.07:55:58.62#ibcon#end of sib2, iclass 5, count 0 2006.238.07:55:58.62#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:55:58.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:55:58.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:55:58.62#ibcon#*before write, iclass 5, count 0 2006.238.07:55:58.62#ibcon#enter sib2, iclass 5, count 0 2006.238.07:55:58.62#ibcon#flushed, iclass 5, count 0 2006.238.07:55:58.62#ibcon#about to write, iclass 5, count 0 2006.238.07:55:58.62#ibcon#wrote, iclass 5, count 0 2006.238.07:55:58.62#ibcon#about to read 3, iclass 5, count 0 2006.238.07:55:58.66#ibcon#read 3, iclass 5, count 0 2006.238.07:55:58.66#ibcon#about to read 4, iclass 5, count 0 2006.238.07:55:58.66#ibcon#read 4, iclass 5, count 0 2006.238.07:55:58.66#ibcon#about to read 5, iclass 5, count 0 2006.238.07:55:58.66#ibcon#read 5, iclass 5, count 0 2006.238.07:55:58.66#ibcon#about to read 6, iclass 5, count 0 2006.238.07:55:58.66#ibcon#read 6, iclass 5, count 0 2006.238.07:55:58.66#ibcon#end of sib2, iclass 5, count 0 2006.238.07:55:58.66#ibcon#*after write, iclass 5, count 0 2006.238.07:55:58.66#ibcon#*before return 0, iclass 5, count 0 2006.238.07:55:58.66#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:55:58.66#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:55:58.66#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:55:58.66#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:55:58.67$vc4f8/va=6,7 2006.238.07:55:58.67#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.07:55:58.67#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.07:55:58.67#ibcon#ireg 11 cls_cnt 2 2006.238.07:55:58.67#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:55:58.71#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:55:58.71#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:55:58.71#ibcon#enter wrdev, iclass 7, count 2 2006.238.07:55:58.71#ibcon#first serial, iclass 7, count 2 2006.238.07:55:58.71#ibcon#enter sib2, iclass 7, count 2 2006.238.07:55:58.71#ibcon#flushed, iclass 7, count 2 2006.238.07:55:58.71#ibcon#about to write, iclass 7, count 2 2006.238.07:55:58.71#ibcon#wrote, iclass 7, count 2 2006.238.07:55:58.71#ibcon#about to read 3, iclass 7, count 2 2006.238.07:55:58.73#ibcon#read 3, iclass 7, count 2 2006.238.07:55:58.73#ibcon#about to read 4, iclass 7, count 2 2006.238.07:55:58.73#ibcon#read 4, iclass 7, count 2 2006.238.07:55:58.73#ibcon#about to read 5, iclass 7, count 2 2006.238.07:55:58.73#ibcon#read 5, iclass 7, count 2 2006.238.07:55:58.73#ibcon#about to read 6, iclass 7, count 2 2006.238.07:55:58.73#ibcon#read 6, iclass 7, count 2 2006.238.07:55:58.73#ibcon#end of sib2, iclass 7, count 2 2006.238.07:55:58.73#ibcon#*mode == 0, iclass 7, count 2 2006.238.07:55:58.73#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.07:55:58.73#ibcon#[25=AT06-07\r\n] 2006.238.07:55:58.73#ibcon#*before write, iclass 7, count 2 2006.238.07:55:58.73#ibcon#enter sib2, iclass 7, count 2 2006.238.07:55:58.73#ibcon#flushed, iclass 7, count 2 2006.238.07:55:58.73#ibcon#about to write, iclass 7, count 2 2006.238.07:55:58.73#ibcon#wrote, iclass 7, count 2 2006.238.07:55:58.73#ibcon#about to read 3, iclass 7, count 2 2006.238.07:55:58.76#ibcon#read 3, iclass 7, count 2 2006.238.07:55:58.76#ibcon#about to read 4, iclass 7, count 2 2006.238.07:55:58.76#ibcon#read 4, iclass 7, count 2 2006.238.07:55:58.76#ibcon#about to read 5, iclass 7, count 2 2006.238.07:55:58.76#ibcon#read 5, iclass 7, count 2 2006.238.07:55:58.76#ibcon#about to read 6, iclass 7, count 2 2006.238.07:55:58.76#ibcon#read 6, iclass 7, count 2 2006.238.07:55:58.76#ibcon#end of sib2, iclass 7, count 2 2006.238.07:55:58.76#ibcon#*after write, iclass 7, count 2 2006.238.07:55:58.76#ibcon#*before return 0, iclass 7, count 2 2006.238.07:55:58.76#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:55:58.76#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:55:58.76#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.07:55:58.76#ibcon#ireg 7 cls_cnt 0 2006.238.07:55:58.76#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:55:58.88#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:55:58.88#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:55:58.88#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:55:58.88#ibcon#first serial, iclass 7, count 0 2006.238.07:55:58.88#ibcon#enter sib2, iclass 7, count 0 2006.238.07:55:58.88#ibcon#flushed, iclass 7, count 0 2006.238.07:55:58.88#ibcon#about to write, iclass 7, count 0 2006.238.07:55:58.88#ibcon#wrote, iclass 7, count 0 2006.238.07:55:58.88#ibcon#about to read 3, iclass 7, count 0 2006.238.07:55:58.90#ibcon#read 3, iclass 7, count 0 2006.238.07:55:58.90#ibcon#about to read 4, iclass 7, count 0 2006.238.07:55:58.90#ibcon#read 4, iclass 7, count 0 2006.238.07:55:58.90#ibcon#about to read 5, iclass 7, count 0 2006.238.07:55:58.90#ibcon#read 5, iclass 7, count 0 2006.238.07:55:58.90#ibcon#about to read 6, iclass 7, count 0 2006.238.07:55:58.90#ibcon#read 6, iclass 7, count 0 2006.238.07:55:58.90#ibcon#end of sib2, iclass 7, count 0 2006.238.07:55:58.90#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:55:58.90#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:55:58.90#ibcon#[25=USB\r\n] 2006.238.07:55:58.90#ibcon#*before write, iclass 7, count 0 2006.238.07:55:58.90#ibcon#enter sib2, iclass 7, count 0 2006.238.07:55:58.90#ibcon#flushed, iclass 7, count 0 2006.238.07:55:58.90#ibcon#about to write, iclass 7, count 0 2006.238.07:55:58.90#ibcon#wrote, iclass 7, count 0 2006.238.07:55:58.90#ibcon#about to read 3, iclass 7, count 0 2006.238.07:55:58.93#ibcon#read 3, iclass 7, count 0 2006.238.07:55:58.93#ibcon#about to read 4, iclass 7, count 0 2006.238.07:55:58.93#ibcon#read 4, iclass 7, count 0 2006.238.07:55:58.93#ibcon#about to read 5, iclass 7, count 0 2006.238.07:55:58.93#ibcon#read 5, iclass 7, count 0 2006.238.07:55:58.93#ibcon#about to read 6, iclass 7, count 0 2006.238.07:55:58.93#ibcon#read 6, iclass 7, count 0 2006.238.07:55:58.93#ibcon#end of sib2, iclass 7, count 0 2006.238.07:55:58.93#ibcon#*after write, iclass 7, count 0 2006.238.07:55:58.93#ibcon#*before return 0, iclass 7, count 0 2006.238.07:55:58.93#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:55:58.93#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:55:58.93#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:55:58.93#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:55:58.94$vc4f8/valo=7,832.99 2006.238.07:55:58.94#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.07:55:58.94#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.07:55:58.94#ibcon#ireg 17 cls_cnt 0 2006.238.07:55:58.94#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:55:58.94#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:55:58.94#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:55:58.94#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:55:58.94#ibcon#first serial, iclass 11, count 0 2006.238.07:55:58.94#ibcon#enter sib2, iclass 11, count 0 2006.238.07:55:58.94#ibcon#flushed, iclass 11, count 0 2006.238.07:55:58.94#ibcon#about to write, iclass 11, count 0 2006.238.07:55:58.94#ibcon#wrote, iclass 11, count 0 2006.238.07:55:58.94#ibcon#about to read 3, iclass 11, count 0 2006.238.07:55:58.95#ibcon#read 3, iclass 11, count 0 2006.238.07:55:58.95#ibcon#about to read 4, iclass 11, count 0 2006.238.07:55:58.95#ibcon#read 4, iclass 11, count 0 2006.238.07:55:58.95#ibcon#about to read 5, iclass 11, count 0 2006.238.07:55:58.95#ibcon#read 5, iclass 11, count 0 2006.238.07:55:58.95#ibcon#about to read 6, iclass 11, count 0 2006.238.07:55:58.95#ibcon#read 6, iclass 11, count 0 2006.238.07:55:58.95#ibcon#end of sib2, iclass 11, count 0 2006.238.07:55:58.95#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:55:58.95#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:55:58.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:55:58.95#ibcon#*before write, iclass 11, count 0 2006.238.07:55:58.95#ibcon#enter sib2, iclass 11, count 0 2006.238.07:55:58.95#ibcon#flushed, iclass 11, count 0 2006.238.07:55:58.95#ibcon#about to write, iclass 11, count 0 2006.238.07:55:58.95#ibcon#wrote, iclass 11, count 0 2006.238.07:55:58.95#ibcon#about to read 3, iclass 11, count 0 2006.238.07:55:58.99#ibcon#read 3, iclass 11, count 0 2006.238.07:55:58.99#ibcon#about to read 4, iclass 11, count 0 2006.238.07:55:58.99#ibcon#read 4, iclass 11, count 0 2006.238.07:55:58.99#ibcon#about to read 5, iclass 11, count 0 2006.238.07:55:58.99#ibcon#read 5, iclass 11, count 0 2006.238.07:55:58.99#ibcon#about to read 6, iclass 11, count 0 2006.238.07:55:58.99#ibcon#read 6, iclass 11, count 0 2006.238.07:55:58.99#ibcon#end of sib2, iclass 11, count 0 2006.238.07:55:58.99#ibcon#*after write, iclass 11, count 0 2006.238.07:55:58.99#ibcon#*before return 0, iclass 11, count 0 2006.238.07:55:58.99#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:55:58.99#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:55:58.99#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:55:58.99#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:55:59.00$vc4f8/va=7,7 2006.238.07:55:59.00#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.07:55:59.00#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.07:55:59.00#ibcon#ireg 11 cls_cnt 2 2006.238.07:55:59.00#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:55:59.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:55:59.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:55:59.04#ibcon#enter wrdev, iclass 13, count 2 2006.238.07:55:59.04#ibcon#first serial, iclass 13, count 2 2006.238.07:55:59.04#ibcon#enter sib2, iclass 13, count 2 2006.238.07:55:59.04#ibcon#flushed, iclass 13, count 2 2006.238.07:55:59.04#ibcon#about to write, iclass 13, count 2 2006.238.07:55:59.04#ibcon#wrote, iclass 13, count 2 2006.238.07:55:59.04#ibcon#about to read 3, iclass 13, count 2 2006.238.07:55:59.06#ibcon#read 3, iclass 13, count 2 2006.238.07:55:59.06#ibcon#about to read 4, iclass 13, count 2 2006.238.07:55:59.06#ibcon#read 4, iclass 13, count 2 2006.238.07:55:59.06#ibcon#about to read 5, iclass 13, count 2 2006.238.07:55:59.06#ibcon#read 5, iclass 13, count 2 2006.238.07:55:59.06#ibcon#about to read 6, iclass 13, count 2 2006.238.07:55:59.06#ibcon#read 6, iclass 13, count 2 2006.238.07:55:59.06#ibcon#end of sib2, iclass 13, count 2 2006.238.07:55:59.06#ibcon#*mode == 0, iclass 13, count 2 2006.238.07:55:59.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.07:55:59.06#ibcon#[25=AT07-07\r\n] 2006.238.07:55:59.06#ibcon#*before write, iclass 13, count 2 2006.238.07:55:59.06#ibcon#enter sib2, iclass 13, count 2 2006.238.07:55:59.06#ibcon#flushed, iclass 13, count 2 2006.238.07:55:59.06#ibcon#about to write, iclass 13, count 2 2006.238.07:55:59.06#ibcon#wrote, iclass 13, count 2 2006.238.07:55:59.06#ibcon#about to read 3, iclass 13, count 2 2006.238.07:55:59.09#ibcon#read 3, iclass 13, count 2 2006.238.07:55:59.09#ibcon#about to read 4, iclass 13, count 2 2006.238.07:55:59.09#ibcon#read 4, iclass 13, count 2 2006.238.07:55:59.09#ibcon#about to read 5, iclass 13, count 2 2006.238.07:55:59.09#ibcon#read 5, iclass 13, count 2 2006.238.07:55:59.09#ibcon#about to read 6, iclass 13, count 2 2006.238.07:55:59.09#ibcon#read 6, iclass 13, count 2 2006.238.07:55:59.09#ibcon#end of sib2, iclass 13, count 2 2006.238.07:55:59.09#ibcon#*after write, iclass 13, count 2 2006.238.07:55:59.09#ibcon#*before return 0, iclass 13, count 2 2006.238.07:55:59.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:55:59.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:55:59.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.07:55:59.09#ibcon#ireg 7 cls_cnt 0 2006.238.07:55:59.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:55:59.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:55:59.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:55:59.21#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:55:59.21#ibcon#first serial, iclass 13, count 0 2006.238.07:55:59.21#ibcon#enter sib2, iclass 13, count 0 2006.238.07:55:59.21#ibcon#flushed, iclass 13, count 0 2006.238.07:55:59.21#ibcon#about to write, iclass 13, count 0 2006.238.07:55:59.21#ibcon#wrote, iclass 13, count 0 2006.238.07:55:59.21#ibcon#about to read 3, iclass 13, count 0 2006.238.07:55:59.23#ibcon#read 3, iclass 13, count 0 2006.238.07:55:59.23#ibcon#about to read 4, iclass 13, count 0 2006.238.07:55:59.23#ibcon#read 4, iclass 13, count 0 2006.238.07:55:59.23#ibcon#about to read 5, iclass 13, count 0 2006.238.07:55:59.23#ibcon#read 5, iclass 13, count 0 2006.238.07:55:59.23#ibcon#about to read 6, iclass 13, count 0 2006.238.07:55:59.23#ibcon#read 6, iclass 13, count 0 2006.238.07:55:59.23#ibcon#end of sib2, iclass 13, count 0 2006.238.07:55:59.23#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:55:59.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:55:59.23#ibcon#[25=USB\r\n] 2006.238.07:55:59.23#ibcon#*before write, iclass 13, count 0 2006.238.07:55:59.23#ibcon#enter sib2, iclass 13, count 0 2006.238.07:55:59.23#ibcon#flushed, iclass 13, count 0 2006.238.07:55:59.23#ibcon#about to write, iclass 13, count 0 2006.238.07:55:59.23#ibcon#wrote, iclass 13, count 0 2006.238.07:55:59.23#ibcon#about to read 3, iclass 13, count 0 2006.238.07:55:59.26#ibcon#read 3, iclass 13, count 0 2006.238.07:55:59.26#ibcon#about to read 4, iclass 13, count 0 2006.238.07:55:59.26#ibcon#read 4, iclass 13, count 0 2006.238.07:55:59.26#ibcon#about to read 5, iclass 13, count 0 2006.238.07:55:59.26#ibcon#read 5, iclass 13, count 0 2006.238.07:55:59.26#ibcon#about to read 6, iclass 13, count 0 2006.238.07:55:59.26#ibcon#read 6, iclass 13, count 0 2006.238.07:55:59.26#ibcon#end of sib2, iclass 13, count 0 2006.238.07:55:59.26#ibcon#*after write, iclass 13, count 0 2006.238.07:55:59.26#ibcon#*before return 0, iclass 13, count 0 2006.238.07:55:59.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:55:59.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:55:59.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:55:59.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:55:59.27$vc4f8/valo=8,852.99 2006.238.07:55:59.27#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.07:55:59.27#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.07:55:59.27#ibcon#ireg 17 cls_cnt 0 2006.238.07:55:59.27#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:55:59.27#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:55:59.27#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:55:59.27#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:55:59.27#ibcon#first serial, iclass 15, count 0 2006.238.07:55:59.27#ibcon#enter sib2, iclass 15, count 0 2006.238.07:55:59.27#ibcon#flushed, iclass 15, count 0 2006.238.07:55:59.27#ibcon#about to write, iclass 15, count 0 2006.238.07:55:59.27#ibcon#wrote, iclass 15, count 0 2006.238.07:55:59.27#ibcon#about to read 3, iclass 15, count 0 2006.238.07:55:59.28#ibcon#read 3, iclass 15, count 0 2006.238.07:55:59.28#ibcon#about to read 4, iclass 15, count 0 2006.238.07:55:59.28#ibcon#read 4, iclass 15, count 0 2006.238.07:55:59.28#ibcon#about to read 5, iclass 15, count 0 2006.238.07:55:59.28#ibcon#read 5, iclass 15, count 0 2006.238.07:55:59.28#ibcon#about to read 6, iclass 15, count 0 2006.238.07:55:59.28#ibcon#read 6, iclass 15, count 0 2006.238.07:55:59.28#ibcon#end of sib2, iclass 15, count 0 2006.238.07:55:59.28#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:55:59.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:55:59.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:55:59.28#ibcon#*before write, iclass 15, count 0 2006.238.07:55:59.28#ibcon#enter sib2, iclass 15, count 0 2006.238.07:55:59.28#ibcon#flushed, iclass 15, count 0 2006.238.07:55:59.28#ibcon#about to write, iclass 15, count 0 2006.238.07:55:59.28#ibcon#wrote, iclass 15, count 0 2006.238.07:55:59.28#ibcon#about to read 3, iclass 15, count 0 2006.238.07:55:59.32#ibcon#read 3, iclass 15, count 0 2006.238.07:55:59.32#ibcon#about to read 4, iclass 15, count 0 2006.238.07:55:59.32#ibcon#read 4, iclass 15, count 0 2006.238.07:55:59.32#ibcon#about to read 5, iclass 15, count 0 2006.238.07:55:59.32#ibcon#read 5, iclass 15, count 0 2006.238.07:55:59.32#ibcon#about to read 6, iclass 15, count 0 2006.238.07:55:59.32#ibcon#read 6, iclass 15, count 0 2006.238.07:55:59.32#ibcon#end of sib2, iclass 15, count 0 2006.238.07:55:59.32#ibcon#*after write, iclass 15, count 0 2006.238.07:55:59.32#ibcon#*before return 0, iclass 15, count 0 2006.238.07:55:59.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:55:59.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:55:59.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:55:59.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:55:59.33$vc4f8/va=8,7 2006.238.07:55:59.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.07:55:59.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.07:55:59.33#ibcon#ireg 11 cls_cnt 2 2006.238.07:55:59.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:55:59.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:55:59.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:55:59.37#ibcon#enter wrdev, iclass 17, count 2 2006.238.07:55:59.37#ibcon#first serial, iclass 17, count 2 2006.238.07:55:59.37#ibcon#enter sib2, iclass 17, count 2 2006.238.07:55:59.37#ibcon#flushed, iclass 17, count 2 2006.238.07:55:59.37#ibcon#about to write, iclass 17, count 2 2006.238.07:55:59.37#ibcon#wrote, iclass 17, count 2 2006.238.07:55:59.37#ibcon#about to read 3, iclass 17, count 2 2006.238.07:55:59.39#ibcon#read 3, iclass 17, count 2 2006.238.07:55:59.39#ibcon#about to read 4, iclass 17, count 2 2006.238.07:55:59.39#ibcon#read 4, iclass 17, count 2 2006.238.07:55:59.39#ibcon#about to read 5, iclass 17, count 2 2006.238.07:55:59.39#ibcon#read 5, iclass 17, count 2 2006.238.07:55:59.39#ibcon#about to read 6, iclass 17, count 2 2006.238.07:55:59.39#ibcon#read 6, iclass 17, count 2 2006.238.07:55:59.39#ibcon#end of sib2, iclass 17, count 2 2006.238.07:55:59.39#ibcon#*mode == 0, iclass 17, count 2 2006.238.07:55:59.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.07:55:59.39#ibcon#[25=AT08-07\r\n] 2006.238.07:55:59.39#ibcon#*before write, iclass 17, count 2 2006.238.07:55:59.39#ibcon#enter sib2, iclass 17, count 2 2006.238.07:55:59.39#ibcon#flushed, iclass 17, count 2 2006.238.07:55:59.39#ibcon#about to write, iclass 17, count 2 2006.238.07:55:59.39#ibcon#wrote, iclass 17, count 2 2006.238.07:55:59.39#ibcon#about to read 3, iclass 17, count 2 2006.238.07:55:59.42#ibcon#read 3, iclass 17, count 2 2006.238.07:55:59.42#ibcon#about to read 4, iclass 17, count 2 2006.238.07:55:59.42#ibcon#read 4, iclass 17, count 2 2006.238.07:55:59.42#ibcon#about to read 5, iclass 17, count 2 2006.238.07:55:59.42#ibcon#read 5, iclass 17, count 2 2006.238.07:55:59.42#ibcon#about to read 6, iclass 17, count 2 2006.238.07:55:59.42#ibcon#read 6, iclass 17, count 2 2006.238.07:55:59.42#ibcon#end of sib2, iclass 17, count 2 2006.238.07:55:59.42#ibcon#*after write, iclass 17, count 2 2006.238.07:55:59.42#ibcon#*before return 0, iclass 17, count 2 2006.238.07:55:59.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:55:59.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:55:59.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.07:55:59.42#ibcon#ireg 7 cls_cnt 0 2006.238.07:55:59.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:55:59.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:55:59.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:55:59.54#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:55:59.54#ibcon#first serial, iclass 17, count 0 2006.238.07:55:59.54#ibcon#enter sib2, iclass 17, count 0 2006.238.07:55:59.54#ibcon#flushed, iclass 17, count 0 2006.238.07:55:59.54#ibcon#about to write, iclass 17, count 0 2006.238.07:55:59.54#ibcon#wrote, iclass 17, count 0 2006.238.07:55:59.54#ibcon#about to read 3, iclass 17, count 0 2006.238.07:55:59.56#ibcon#read 3, iclass 17, count 0 2006.238.07:55:59.56#ibcon#about to read 4, iclass 17, count 0 2006.238.07:55:59.56#ibcon#read 4, iclass 17, count 0 2006.238.07:55:59.56#ibcon#about to read 5, iclass 17, count 0 2006.238.07:55:59.56#ibcon#read 5, iclass 17, count 0 2006.238.07:55:59.56#ibcon#about to read 6, iclass 17, count 0 2006.238.07:55:59.56#ibcon#read 6, iclass 17, count 0 2006.238.07:55:59.56#ibcon#end of sib2, iclass 17, count 0 2006.238.07:55:59.56#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:55:59.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:55:59.56#ibcon#[25=USB\r\n] 2006.238.07:55:59.56#ibcon#*before write, iclass 17, count 0 2006.238.07:55:59.56#ibcon#enter sib2, iclass 17, count 0 2006.238.07:55:59.56#ibcon#flushed, iclass 17, count 0 2006.238.07:55:59.56#ibcon#about to write, iclass 17, count 0 2006.238.07:55:59.56#ibcon#wrote, iclass 17, count 0 2006.238.07:55:59.56#ibcon#about to read 3, iclass 17, count 0 2006.238.07:55:59.59#ibcon#read 3, iclass 17, count 0 2006.238.07:55:59.59#ibcon#about to read 4, iclass 17, count 0 2006.238.07:55:59.59#ibcon#read 4, iclass 17, count 0 2006.238.07:55:59.59#ibcon#about to read 5, iclass 17, count 0 2006.238.07:55:59.59#ibcon#read 5, iclass 17, count 0 2006.238.07:55:59.59#ibcon#about to read 6, iclass 17, count 0 2006.238.07:55:59.59#ibcon#read 6, iclass 17, count 0 2006.238.07:55:59.59#ibcon#end of sib2, iclass 17, count 0 2006.238.07:55:59.59#ibcon#*after write, iclass 17, count 0 2006.238.07:55:59.59#ibcon#*before return 0, iclass 17, count 0 2006.238.07:55:59.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:55:59.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:55:59.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:55:59.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:55:59.60$vc4f8/vblo=1,632.99 2006.238.07:55:59.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.07:55:59.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.07:55:59.60#ibcon#ireg 17 cls_cnt 0 2006.238.07:55:59.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:55:59.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:55:59.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:55:59.60#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:55:59.60#ibcon#first serial, iclass 19, count 0 2006.238.07:55:59.60#ibcon#enter sib2, iclass 19, count 0 2006.238.07:55:59.60#ibcon#flushed, iclass 19, count 0 2006.238.07:55:59.60#ibcon#about to write, iclass 19, count 0 2006.238.07:55:59.60#ibcon#wrote, iclass 19, count 0 2006.238.07:55:59.60#ibcon#about to read 3, iclass 19, count 0 2006.238.07:55:59.61#ibcon#read 3, iclass 19, count 0 2006.238.07:55:59.61#ibcon#about to read 4, iclass 19, count 0 2006.238.07:55:59.61#ibcon#read 4, iclass 19, count 0 2006.238.07:55:59.61#ibcon#about to read 5, iclass 19, count 0 2006.238.07:55:59.61#ibcon#read 5, iclass 19, count 0 2006.238.07:55:59.61#ibcon#about to read 6, iclass 19, count 0 2006.238.07:55:59.61#ibcon#read 6, iclass 19, count 0 2006.238.07:55:59.61#ibcon#end of sib2, iclass 19, count 0 2006.238.07:55:59.61#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:55:59.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:55:59.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:55:59.61#ibcon#*before write, iclass 19, count 0 2006.238.07:55:59.61#ibcon#enter sib2, iclass 19, count 0 2006.238.07:55:59.61#ibcon#flushed, iclass 19, count 0 2006.238.07:55:59.61#ibcon#about to write, iclass 19, count 0 2006.238.07:55:59.61#ibcon#wrote, iclass 19, count 0 2006.238.07:55:59.61#ibcon#about to read 3, iclass 19, count 0 2006.238.07:55:59.65#ibcon#read 3, iclass 19, count 0 2006.238.07:55:59.65#ibcon#about to read 4, iclass 19, count 0 2006.238.07:55:59.65#ibcon#read 4, iclass 19, count 0 2006.238.07:55:59.65#ibcon#about to read 5, iclass 19, count 0 2006.238.07:55:59.65#ibcon#read 5, iclass 19, count 0 2006.238.07:55:59.65#ibcon#about to read 6, iclass 19, count 0 2006.238.07:55:59.65#ibcon#read 6, iclass 19, count 0 2006.238.07:55:59.65#ibcon#end of sib2, iclass 19, count 0 2006.238.07:55:59.65#ibcon#*after write, iclass 19, count 0 2006.238.07:55:59.65#ibcon#*before return 0, iclass 19, count 0 2006.238.07:55:59.65#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:55:59.65#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:55:59.65#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:55:59.65#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:55:59.66$vc4f8/vb=1,4 2006.238.07:55:59.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.07:55:59.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.07:55:59.66#ibcon#ireg 11 cls_cnt 2 2006.238.07:55:59.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:55:59.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:55:59.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:55:59.66#ibcon#enter wrdev, iclass 21, count 2 2006.238.07:55:59.66#ibcon#first serial, iclass 21, count 2 2006.238.07:55:59.66#ibcon#enter sib2, iclass 21, count 2 2006.238.07:55:59.66#ibcon#flushed, iclass 21, count 2 2006.238.07:55:59.66#ibcon#about to write, iclass 21, count 2 2006.238.07:55:59.66#ibcon#wrote, iclass 21, count 2 2006.238.07:55:59.66#ibcon#about to read 3, iclass 21, count 2 2006.238.07:55:59.67#ibcon#read 3, iclass 21, count 2 2006.238.07:55:59.67#ibcon#about to read 4, iclass 21, count 2 2006.238.07:55:59.67#ibcon#read 4, iclass 21, count 2 2006.238.07:55:59.67#ibcon#about to read 5, iclass 21, count 2 2006.238.07:55:59.67#ibcon#read 5, iclass 21, count 2 2006.238.07:55:59.67#ibcon#about to read 6, iclass 21, count 2 2006.238.07:55:59.67#ibcon#read 6, iclass 21, count 2 2006.238.07:55:59.67#ibcon#end of sib2, iclass 21, count 2 2006.238.07:55:59.67#ibcon#*mode == 0, iclass 21, count 2 2006.238.07:55:59.67#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.07:55:59.67#ibcon#[27=AT01-04\r\n] 2006.238.07:55:59.67#ibcon#*before write, iclass 21, count 2 2006.238.07:55:59.67#ibcon#enter sib2, iclass 21, count 2 2006.238.07:55:59.67#ibcon#flushed, iclass 21, count 2 2006.238.07:55:59.67#ibcon#about to write, iclass 21, count 2 2006.238.07:55:59.67#ibcon#wrote, iclass 21, count 2 2006.238.07:55:59.67#ibcon#about to read 3, iclass 21, count 2 2006.238.07:55:59.70#ibcon#read 3, iclass 21, count 2 2006.238.07:55:59.70#ibcon#about to read 4, iclass 21, count 2 2006.238.07:55:59.70#ibcon#read 4, iclass 21, count 2 2006.238.07:55:59.70#ibcon#about to read 5, iclass 21, count 2 2006.238.07:55:59.70#ibcon#read 5, iclass 21, count 2 2006.238.07:55:59.70#ibcon#about to read 6, iclass 21, count 2 2006.238.07:55:59.70#ibcon#read 6, iclass 21, count 2 2006.238.07:55:59.70#ibcon#end of sib2, iclass 21, count 2 2006.238.07:55:59.70#ibcon#*after write, iclass 21, count 2 2006.238.07:55:59.70#ibcon#*before return 0, iclass 21, count 2 2006.238.07:55:59.70#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:55:59.70#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:55:59.70#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.07:55:59.70#ibcon#ireg 7 cls_cnt 0 2006.238.07:55:59.70#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:55:59.82#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:55:59.82#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:55:59.82#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:55:59.82#ibcon#first serial, iclass 21, count 0 2006.238.07:55:59.82#ibcon#enter sib2, iclass 21, count 0 2006.238.07:55:59.82#ibcon#flushed, iclass 21, count 0 2006.238.07:55:59.82#ibcon#about to write, iclass 21, count 0 2006.238.07:55:59.82#ibcon#wrote, iclass 21, count 0 2006.238.07:55:59.82#ibcon#about to read 3, iclass 21, count 0 2006.238.07:55:59.84#ibcon#read 3, iclass 21, count 0 2006.238.07:55:59.84#ibcon#about to read 4, iclass 21, count 0 2006.238.07:55:59.84#ibcon#read 4, iclass 21, count 0 2006.238.07:55:59.84#ibcon#about to read 5, iclass 21, count 0 2006.238.07:55:59.84#ibcon#read 5, iclass 21, count 0 2006.238.07:55:59.84#ibcon#about to read 6, iclass 21, count 0 2006.238.07:55:59.84#ibcon#read 6, iclass 21, count 0 2006.238.07:55:59.84#ibcon#end of sib2, iclass 21, count 0 2006.238.07:55:59.84#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:55:59.84#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:55:59.84#ibcon#[27=USB\r\n] 2006.238.07:55:59.84#ibcon#*before write, iclass 21, count 0 2006.238.07:55:59.84#ibcon#enter sib2, iclass 21, count 0 2006.238.07:55:59.84#ibcon#flushed, iclass 21, count 0 2006.238.07:55:59.84#ibcon#about to write, iclass 21, count 0 2006.238.07:55:59.84#ibcon#wrote, iclass 21, count 0 2006.238.07:55:59.84#ibcon#about to read 3, iclass 21, count 0 2006.238.07:55:59.87#ibcon#read 3, iclass 21, count 0 2006.238.07:55:59.87#ibcon#about to read 4, iclass 21, count 0 2006.238.07:55:59.87#ibcon#read 4, iclass 21, count 0 2006.238.07:55:59.87#ibcon#about to read 5, iclass 21, count 0 2006.238.07:55:59.87#ibcon#read 5, iclass 21, count 0 2006.238.07:55:59.87#ibcon#about to read 6, iclass 21, count 0 2006.238.07:55:59.87#ibcon#read 6, iclass 21, count 0 2006.238.07:55:59.87#ibcon#end of sib2, iclass 21, count 0 2006.238.07:55:59.87#ibcon#*after write, iclass 21, count 0 2006.238.07:55:59.87#ibcon#*before return 0, iclass 21, count 0 2006.238.07:55:59.87#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:55:59.87#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:55:59.87#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:55:59.87#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:55:59.88$vc4f8/vblo=2,640.99 2006.238.07:55:59.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:55:59.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:55:59.88#ibcon#ireg 17 cls_cnt 0 2006.238.07:55:59.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:55:59.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:55:59.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:55:59.88#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:55:59.88#ibcon#first serial, iclass 23, count 0 2006.238.07:55:59.88#ibcon#enter sib2, iclass 23, count 0 2006.238.07:55:59.88#ibcon#flushed, iclass 23, count 0 2006.238.07:55:59.88#ibcon#about to write, iclass 23, count 0 2006.238.07:55:59.88#ibcon#wrote, iclass 23, count 0 2006.238.07:55:59.88#ibcon#about to read 3, iclass 23, count 0 2006.238.07:55:59.89#ibcon#read 3, iclass 23, count 0 2006.238.07:55:59.89#ibcon#about to read 4, iclass 23, count 0 2006.238.07:55:59.89#ibcon#read 4, iclass 23, count 0 2006.238.07:55:59.89#ibcon#about to read 5, iclass 23, count 0 2006.238.07:55:59.89#ibcon#read 5, iclass 23, count 0 2006.238.07:55:59.89#ibcon#about to read 6, iclass 23, count 0 2006.238.07:55:59.89#ibcon#read 6, iclass 23, count 0 2006.238.07:55:59.89#ibcon#end of sib2, iclass 23, count 0 2006.238.07:55:59.89#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:55:59.89#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:55:59.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:55:59.89#ibcon#*before write, iclass 23, count 0 2006.238.07:55:59.89#ibcon#enter sib2, iclass 23, count 0 2006.238.07:55:59.89#ibcon#flushed, iclass 23, count 0 2006.238.07:55:59.89#ibcon#about to write, iclass 23, count 0 2006.238.07:55:59.89#ibcon#wrote, iclass 23, count 0 2006.238.07:55:59.89#ibcon#about to read 3, iclass 23, count 0 2006.238.07:55:59.93#ibcon#read 3, iclass 23, count 0 2006.238.07:55:59.93#ibcon#about to read 4, iclass 23, count 0 2006.238.07:55:59.93#ibcon#read 4, iclass 23, count 0 2006.238.07:55:59.93#ibcon#about to read 5, iclass 23, count 0 2006.238.07:55:59.93#ibcon#read 5, iclass 23, count 0 2006.238.07:55:59.93#ibcon#about to read 6, iclass 23, count 0 2006.238.07:55:59.93#ibcon#read 6, iclass 23, count 0 2006.238.07:55:59.93#ibcon#end of sib2, iclass 23, count 0 2006.238.07:55:59.93#ibcon#*after write, iclass 23, count 0 2006.238.07:55:59.93#ibcon#*before return 0, iclass 23, count 0 2006.238.07:55:59.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:55:59.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:55:59.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:55:59.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:55:59.94$vc4f8/vb=2,4 2006.238.07:55:59.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.07:55:59.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.07:55:59.94#ibcon#ireg 11 cls_cnt 2 2006.238.07:55:59.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:55:59.98#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:55:59.98#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:55:59.98#ibcon#enter wrdev, iclass 25, count 2 2006.238.07:55:59.98#ibcon#first serial, iclass 25, count 2 2006.238.07:55:59.98#ibcon#enter sib2, iclass 25, count 2 2006.238.07:55:59.98#ibcon#flushed, iclass 25, count 2 2006.238.07:55:59.98#ibcon#about to write, iclass 25, count 2 2006.238.07:55:59.98#ibcon#wrote, iclass 25, count 2 2006.238.07:55:59.98#ibcon#about to read 3, iclass 25, count 2 2006.238.07:56:00.00#ibcon#read 3, iclass 25, count 2 2006.238.07:56:00.00#ibcon#about to read 4, iclass 25, count 2 2006.238.07:56:00.00#ibcon#read 4, iclass 25, count 2 2006.238.07:56:00.00#ibcon#about to read 5, iclass 25, count 2 2006.238.07:56:00.00#ibcon#read 5, iclass 25, count 2 2006.238.07:56:00.00#ibcon#about to read 6, iclass 25, count 2 2006.238.07:56:00.00#ibcon#read 6, iclass 25, count 2 2006.238.07:56:00.00#ibcon#end of sib2, iclass 25, count 2 2006.238.07:56:00.00#ibcon#*mode == 0, iclass 25, count 2 2006.238.07:56:00.00#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.07:56:00.00#ibcon#[27=AT02-04\r\n] 2006.238.07:56:00.00#ibcon#*before write, iclass 25, count 2 2006.238.07:56:00.00#ibcon#enter sib2, iclass 25, count 2 2006.238.07:56:00.00#ibcon#flushed, iclass 25, count 2 2006.238.07:56:00.00#ibcon#about to write, iclass 25, count 2 2006.238.07:56:00.00#ibcon#wrote, iclass 25, count 2 2006.238.07:56:00.00#ibcon#about to read 3, iclass 25, count 2 2006.238.07:56:00.03#ibcon#read 3, iclass 25, count 2 2006.238.07:56:00.03#ibcon#about to read 4, iclass 25, count 2 2006.238.07:56:00.03#ibcon#read 4, iclass 25, count 2 2006.238.07:56:00.03#ibcon#about to read 5, iclass 25, count 2 2006.238.07:56:00.03#ibcon#read 5, iclass 25, count 2 2006.238.07:56:00.03#ibcon#about to read 6, iclass 25, count 2 2006.238.07:56:00.03#ibcon#read 6, iclass 25, count 2 2006.238.07:56:00.03#ibcon#end of sib2, iclass 25, count 2 2006.238.07:56:00.03#ibcon#*after write, iclass 25, count 2 2006.238.07:56:00.03#ibcon#*before return 0, iclass 25, count 2 2006.238.07:56:00.03#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:56:00.03#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:56:00.03#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.07:56:00.03#ibcon#ireg 7 cls_cnt 0 2006.238.07:56:00.03#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:56:00.15#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:56:00.15#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:56:00.15#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:56:00.15#ibcon#first serial, iclass 25, count 0 2006.238.07:56:00.15#ibcon#enter sib2, iclass 25, count 0 2006.238.07:56:00.15#ibcon#flushed, iclass 25, count 0 2006.238.07:56:00.15#ibcon#about to write, iclass 25, count 0 2006.238.07:56:00.15#ibcon#wrote, iclass 25, count 0 2006.238.07:56:00.15#ibcon#about to read 3, iclass 25, count 0 2006.238.07:56:00.17#ibcon#read 3, iclass 25, count 0 2006.238.07:56:00.17#ibcon#about to read 4, iclass 25, count 0 2006.238.07:56:00.17#ibcon#read 4, iclass 25, count 0 2006.238.07:56:00.17#ibcon#about to read 5, iclass 25, count 0 2006.238.07:56:00.17#ibcon#read 5, iclass 25, count 0 2006.238.07:56:00.17#ibcon#about to read 6, iclass 25, count 0 2006.238.07:56:00.17#ibcon#read 6, iclass 25, count 0 2006.238.07:56:00.17#ibcon#end of sib2, iclass 25, count 0 2006.238.07:56:00.17#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:56:00.17#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:56:00.17#ibcon#[27=USB\r\n] 2006.238.07:56:00.17#ibcon#*before write, iclass 25, count 0 2006.238.07:56:00.17#ibcon#enter sib2, iclass 25, count 0 2006.238.07:56:00.17#ibcon#flushed, iclass 25, count 0 2006.238.07:56:00.17#ibcon#about to write, iclass 25, count 0 2006.238.07:56:00.17#ibcon#wrote, iclass 25, count 0 2006.238.07:56:00.17#ibcon#about to read 3, iclass 25, count 0 2006.238.07:56:00.19#abcon#<5=/05 2.1 3.8 25.40 891012.2\r\n> 2006.238.07:56:00.20#ibcon#read 3, iclass 25, count 0 2006.238.07:56:00.20#ibcon#about to read 4, iclass 25, count 0 2006.238.07:56:00.20#ibcon#read 4, iclass 25, count 0 2006.238.07:56:00.20#ibcon#about to read 5, iclass 25, count 0 2006.238.07:56:00.20#ibcon#read 5, iclass 25, count 0 2006.238.07:56:00.20#ibcon#about to read 6, iclass 25, count 0 2006.238.07:56:00.20#ibcon#read 6, iclass 25, count 0 2006.238.07:56:00.20#ibcon#end of sib2, iclass 25, count 0 2006.238.07:56:00.20#ibcon#*after write, iclass 25, count 0 2006.238.07:56:00.20#ibcon#*before return 0, iclass 25, count 0 2006.238.07:56:00.20#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:56:00.20#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:56:00.20#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:56:00.20#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:56:00.21$vc4f8/vblo=3,656.99 2006.238.07:56:00.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.07:56:00.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.07:56:00.21#ibcon#ireg 17 cls_cnt 0 2006.238.07:56:00.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:56:00.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:56:00.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:56:00.21#ibcon#enter wrdev, iclass 30, count 0 2006.238.07:56:00.21#ibcon#first serial, iclass 30, count 0 2006.238.07:56:00.21#ibcon#enter sib2, iclass 30, count 0 2006.238.07:56:00.21#ibcon#flushed, iclass 30, count 0 2006.238.07:56:00.21#ibcon#about to write, iclass 30, count 0 2006.238.07:56:00.21#ibcon#wrote, iclass 30, count 0 2006.238.07:56:00.21#ibcon#about to read 3, iclass 30, count 0 2006.238.07:56:00.21#abcon#{5=INTERFACE CLEAR} 2006.238.07:56:00.22#ibcon#read 3, iclass 30, count 0 2006.238.07:56:00.22#ibcon#about to read 4, iclass 30, count 0 2006.238.07:56:00.22#ibcon#read 4, iclass 30, count 0 2006.238.07:56:00.22#ibcon#about to read 5, iclass 30, count 0 2006.238.07:56:00.22#ibcon#read 5, iclass 30, count 0 2006.238.07:56:00.22#ibcon#about to read 6, iclass 30, count 0 2006.238.07:56:00.22#ibcon#read 6, iclass 30, count 0 2006.238.07:56:00.22#ibcon#end of sib2, iclass 30, count 0 2006.238.07:56:00.22#ibcon#*mode == 0, iclass 30, count 0 2006.238.07:56:00.22#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.07:56:00.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:56:00.22#ibcon#*before write, iclass 30, count 0 2006.238.07:56:00.22#ibcon#enter sib2, iclass 30, count 0 2006.238.07:56:00.22#ibcon#flushed, iclass 30, count 0 2006.238.07:56:00.22#ibcon#about to write, iclass 30, count 0 2006.238.07:56:00.22#ibcon#wrote, iclass 30, count 0 2006.238.07:56:00.22#ibcon#about to read 3, iclass 30, count 0 2006.238.07:56:00.27#ibcon#read 3, iclass 30, count 0 2006.238.07:56:00.27#ibcon#about to read 4, iclass 30, count 0 2006.238.07:56:00.27#ibcon#read 4, iclass 30, count 0 2006.238.07:56:00.27#ibcon#about to read 5, iclass 30, count 0 2006.238.07:56:00.27#ibcon#read 5, iclass 30, count 0 2006.238.07:56:00.27#ibcon#about to read 6, iclass 30, count 0 2006.238.07:56:00.27#ibcon#read 6, iclass 30, count 0 2006.238.07:56:00.27#ibcon#end of sib2, iclass 30, count 0 2006.238.07:56:00.27#ibcon#*after write, iclass 30, count 0 2006.238.07:56:00.27#ibcon#*before return 0, iclass 30, count 0 2006.238.07:56:00.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:56:00.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.07:56:00.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.07:56:00.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.07:56:00.27$vc4f8/vb=3,4 2006.238.07:56:00.27#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:56:00.27#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:56:00.27#ibcon#ireg 11 cls_cnt 2 2006.238.07:56:00.27#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:56:00.27#abcon#[5=S1D000X0/0*\r\n] 2006.238.07:56:00.31#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:56:00.31#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:56:00.31#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:56:00.31#ibcon#first serial, iclass 33, count 2 2006.238.07:56:00.31#ibcon#enter sib2, iclass 33, count 2 2006.238.07:56:00.31#ibcon#flushed, iclass 33, count 2 2006.238.07:56:00.31#ibcon#about to write, iclass 33, count 2 2006.238.07:56:00.31#ibcon#wrote, iclass 33, count 2 2006.238.07:56:00.31#ibcon#about to read 3, iclass 33, count 2 2006.238.07:56:00.33#ibcon#read 3, iclass 33, count 2 2006.238.07:56:00.33#ibcon#about to read 4, iclass 33, count 2 2006.238.07:56:00.33#ibcon#read 4, iclass 33, count 2 2006.238.07:56:00.33#ibcon#about to read 5, iclass 33, count 2 2006.238.07:56:00.33#ibcon#read 5, iclass 33, count 2 2006.238.07:56:00.33#ibcon#about to read 6, iclass 33, count 2 2006.238.07:56:00.33#ibcon#read 6, iclass 33, count 2 2006.238.07:56:00.33#ibcon#end of sib2, iclass 33, count 2 2006.238.07:56:00.33#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:56:00.33#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:56:00.33#ibcon#[27=AT03-04\r\n] 2006.238.07:56:00.33#ibcon#*before write, iclass 33, count 2 2006.238.07:56:00.33#ibcon#enter sib2, iclass 33, count 2 2006.238.07:56:00.33#ibcon#flushed, iclass 33, count 2 2006.238.07:56:00.33#ibcon#about to write, iclass 33, count 2 2006.238.07:56:00.33#ibcon#wrote, iclass 33, count 2 2006.238.07:56:00.33#ibcon#about to read 3, iclass 33, count 2 2006.238.07:56:00.36#ibcon#read 3, iclass 33, count 2 2006.238.07:56:00.36#ibcon#about to read 4, iclass 33, count 2 2006.238.07:56:00.36#ibcon#read 4, iclass 33, count 2 2006.238.07:56:00.36#ibcon#about to read 5, iclass 33, count 2 2006.238.07:56:00.36#ibcon#read 5, iclass 33, count 2 2006.238.07:56:00.36#ibcon#about to read 6, iclass 33, count 2 2006.238.07:56:00.36#ibcon#read 6, iclass 33, count 2 2006.238.07:56:00.36#ibcon#end of sib2, iclass 33, count 2 2006.238.07:56:00.36#ibcon#*after write, iclass 33, count 2 2006.238.07:56:00.36#ibcon#*before return 0, iclass 33, count 2 2006.238.07:56:00.36#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:56:00.36#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:56:00.36#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:56:00.36#ibcon#ireg 7 cls_cnt 0 2006.238.07:56:00.36#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:56:00.48#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:56:00.48#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:56:00.48#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:56:00.48#ibcon#first serial, iclass 33, count 0 2006.238.07:56:00.48#ibcon#enter sib2, iclass 33, count 0 2006.238.07:56:00.48#ibcon#flushed, iclass 33, count 0 2006.238.07:56:00.48#ibcon#about to write, iclass 33, count 0 2006.238.07:56:00.48#ibcon#wrote, iclass 33, count 0 2006.238.07:56:00.48#ibcon#about to read 3, iclass 33, count 0 2006.238.07:56:00.50#ibcon#read 3, iclass 33, count 0 2006.238.07:56:00.50#ibcon#about to read 4, iclass 33, count 0 2006.238.07:56:00.50#ibcon#read 4, iclass 33, count 0 2006.238.07:56:00.50#ibcon#about to read 5, iclass 33, count 0 2006.238.07:56:00.50#ibcon#read 5, iclass 33, count 0 2006.238.07:56:00.50#ibcon#about to read 6, iclass 33, count 0 2006.238.07:56:00.50#ibcon#read 6, iclass 33, count 0 2006.238.07:56:00.50#ibcon#end of sib2, iclass 33, count 0 2006.238.07:56:00.50#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:56:00.50#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:56:00.50#ibcon#[27=USB\r\n] 2006.238.07:56:00.50#ibcon#*before write, iclass 33, count 0 2006.238.07:56:00.50#ibcon#enter sib2, iclass 33, count 0 2006.238.07:56:00.50#ibcon#flushed, iclass 33, count 0 2006.238.07:56:00.50#ibcon#about to write, iclass 33, count 0 2006.238.07:56:00.50#ibcon#wrote, iclass 33, count 0 2006.238.07:56:00.50#ibcon#about to read 3, iclass 33, count 0 2006.238.07:56:00.53#ibcon#read 3, iclass 33, count 0 2006.238.07:56:00.53#ibcon#about to read 4, iclass 33, count 0 2006.238.07:56:00.53#ibcon#read 4, iclass 33, count 0 2006.238.07:56:00.53#ibcon#about to read 5, iclass 33, count 0 2006.238.07:56:00.53#ibcon#read 5, iclass 33, count 0 2006.238.07:56:00.53#ibcon#about to read 6, iclass 33, count 0 2006.238.07:56:00.53#ibcon#read 6, iclass 33, count 0 2006.238.07:56:00.53#ibcon#end of sib2, iclass 33, count 0 2006.238.07:56:00.53#ibcon#*after write, iclass 33, count 0 2006.238.07:56:00.53#ibcon#*before return 0, iclass 33, count 0 2006.238.07:56:00.53#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:56:00.53#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:56:00.53#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:56:00.53#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:56:00.54$vc4f8/vblo=4,712.99 2006.238.07:56:00.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:56:00.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:56:00.54#ibcon#ireg 17 cls_cnt 0 2006.238.07:56:00.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:56:00.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:56:00.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:56:00.54#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:56:00.54#ibcon#first serial, iclass 35, count 0 2006.238.07:56:00.54#ibcon#enter sib2, iclass 35, count 0 2006.238.07:56:00.54#ibcon#flushed, iclass 35, count 0 2006.238.07:56:00.54#ibcon#about to write, iclass 35, count 0 2006.238.07:56:00.54#ibcon#wrote, iclass 35, count 0 2006.238.07:56:00.54#ibcon#about to read 3, iclass 35, count 0 2006.238.07:56:00.55#ibcon#read 3, iclass 35, count 0 2006.238.07:56:00.55#ibcon#about to read 4, iclass 35, count 0 2006.238.07:56:00.55#ibcon#read 4, iclass 35, count 0 2006.238.07:56:00.55#ibcon#about to read 5, iclass 35, count 0 2006.238.07:56:00.55#ibcon#read 5, iclass 35, count 0 2006.238.07:56:00.55#ibcon#about to read 6, iclass 35, count 0 2006.238.07:56:00.55#ibcon#read 6, iclass 35, count 0 2006.238.07:56:00.55#ibcon#end of sib2, iclass 35, count 0 2006.238.07:56:00.55#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:56:00.55#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:56:00.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:56:00.55#ibcon#*before write, iclass 35, count 0 2006.238.07:56:00.55#ibcon#enter sib2, iclass 35, count 0 2006.238.07:56:00.55#ibcon#flushed, iclass 35, count 0 2006.238.07:56:00.55#ibcon#about to write, iclass 35, count 0 2006.238.07:56:00.55#ibcon#wrote, iclass 35, count 0 2006.238.07:56:00.55#ibcon#about to read 3, iclass 35, count 0 2006.238.07:56:00.59#ibcon#read 3, iclass 35, count 0 2006.238.07:56:00.59#ibcon#about to read 4, iclass 35, count 0 2006.238.07:56:00.59#ibcon#read 4, iclass 35, count 0 2006.238.07:56:00.59#ibcon#about to read 5, iclass 35, count 0 2006.238.07:56:00.59#ibcon#read 5, iclass 35, count 0 2006.238.07:56:00.59#ibcon#about to read 6, iclass 35, count 0 2006.238.07:56:00.59#ibcon#read 6, iclass 35, count 0 2006.238.07:56:00.59#ibcon#end of sib2, iclass 35, count 0 2006.238.07:56:00.59#ibcon#*after write, iclass 35, count 0 2006.238.07:56:00.59#ibcon#*before return 0, iclass 35, count 0 2006.238.07:56:00.59#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:56:00.59#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:56:00.59#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:56:00.59#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:56:00.60$vc4f8/vb=4,4 2006.238.07:56:00.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.07:56:00.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.07:56:00.60#ibcon#ireg 11 cls_cnt 2 2006.238.07:56:00.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:56:00.64#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:56:00.64#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:56:00.64#ibcon#enter wrdev, iclass 37, count 2 2006.238.07:56:00.64#ibcon#first serial, iclass 37, count 2 2006.238.07:56:00.64#ibcon#enter sib2, iclass 37, count 2 2006.238.07:56:00.64#ibcon#flushed, iclass 37, count 2 2006.238.07:56:00.64#ibcon#about to write, iclass 37, count 2 2006.238.07:56:00.64#ibcon#wrote, iclass 37, count 2 2006.238.07:56:00.64#ibcon#about to read 3, iclass 37, count 2 2006.238.07:56:00.66#ibcon#read 3, iclass 37, count 2 2006.238.07:56:00.66#ibcon#about to read 4, iclass 37, count 2 2006.238.07:56:00.66#ibcon#read 4, iclass 37, count 2 2006.238.07:56:00.66#ibcon#about to read 5, iclass 37, count 2 2006.238.07:56:00.66#ibcon#read 5, iclass 37, count 2 2006.238.07:56:00.66#ibcon#about to read 6, iclass 37, count 2 2006.238.07:56:00.66#ibcon#read 6, iclass 37, count 2 2006.238.07:56:00.66#ibcon#end of sib2, iclass 37, count 2 2006.238.07:56:00.66#ibcon#*mode == 0, iclass 37, count 2 2006.238.07:56:00.66#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.07:56:00.66#ibcon#[27=AT04-04\r\n] 2006.238.07:56:00.66#ibcon#*before write, iclass 37, count 2 2006.238.07:56:00.66#ibcon#enter sib2, iclass 37, count 2 2006.238.07:56:00.66#ibcon#flushed, iclass 37, count 2 2006.238.07:56:00.66#ibcon#about to write, iclass 37, count 2 2006.238.07:56:00.66#ibcon#wrote, iclass 37, count 2 2006.238.07:56:00.66#ibcon#about to read 3, iclass 37, count 2 2006.238.07:56:00.69#ibcon#read 3, iclass 37, count 2 2006.238.07:56:00.69#ibcon#about to read 4, iclass 37, count 2 2006.238.07:56:00.69#ibcon#read 4, iclass 37, count 2 2006.238.07:56:00.69#ibcon#about to read 5, iclass 37, count 2 2006.238.07:56:00.69#ibcon#read 5, iclass 37, count 2 2006.238.07:56:00.69#ibcon#about to read 6, iclass 37, count 2 2006.238.07:56:00.69#ibcon#read 6, iclass 37, count 2 2006.238.07:56:00.69#ibcon#end of sib2, iclass 37, count 2 2006.238.07:56:00.69#ibcon#*after write, iclass 37, count 2 2006.238.07:56:00.69#ibcon#*before return 0, iclass 37, count 2 2006.238.07:56:00.69#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:56:00.69#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:56:00.69#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.07:56:00.69#ibcon#ireg 7 cls_cnt 0 2006.238.07:56:00.69#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:56:00.81#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:56:00.81#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:56:00.81#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:56:00.81#ibcon#first serial, iclass 37, count 0 2006.238.07:56:00.81#ibcon#enter sib2, iclass 37, count 0 2006.238.07:56:00.81#ibcon#flushed, iclass 37, count 0 2006.238.07:56:00.81#ibcon#about to write, iclass 37, count 0 2006.238.07:56:00.81#ibcon#wrote, iclass 37, count 0 2006.238.07:56:00.81#ibcon#about to read 3, iclass 37, count 0 2006.238.07:56:00.83#ibcon#read 3, iclass 37, count 0 2006.238.07:56:00.83#ibcon#about to read 4, iclass 37, count 0 2006.238.07:56:00.83#ibcon#read 4, iclass 37, count 0 2006.238.07:56:00.83#ibcon#about to read 5, iclass 37, count 0 2006.238.07:56:00.83#ibcon#read 5, iclass 37, count 0 2006.238.07:56:00.83#ibcon#about to read 6, iclass 37, count 0 2006.238.07:56:00.83#ibcon#read 6, iclass 37, count 0 2006.238.07:56:00.83#ibcon#end of sib2, iclass 37, count 0 2006.238.07:56:00.83#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:56:00.83#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:56:00.83#ibcon#[27=USB\r\n] 2006.238.07:56:00.83#ibcon#*before write, iclass 37, count 0 2006.238.07:56:00.83#ibcon#enter sib2, iclass 37, count 0 2006.238.07:56:00.83#ibcon#flushed, iclass 37, count 0 2006.238.07:56:00.83#ibcon#about to write, iclass 37, count 0 2006.238.07:56:00.83#ibcon#wrote, iclass 37, count 0 2006.238.07:56:00.83#ibcon#about to read 3, iclass 37, count 0 2006.238.07:56:00.86#ibcon#read 3, iclass 37, count 0 2006.238.07:56:00.86#ibcon#about to read 4, iclass 37, count 0 2006.238.07:56:00.86#ibcon#read 4, iclass 37, count 0 2006.238.07:56:00.86#ibcon#about to read 5, iclass 37, count 0 2006.238.07:56:00.86#ibcon#read 5, iclass 37, count 0 2006.238.07:56:00.86#ibcon#about to read 6, iclass 37, count 0 2006.238.07:56:00.86#ibcon#read 6, iclass 37, count 0 2006.238.07:56:00.86#ibcon#end of sib2, iclass 37, count 0 2006.238.07:56:00.86#ibcon#*after write, iclass 37, count 0 2006.238.07:56:00.86#ibcon#*before return 0, iclass 37, count 0 2006.238.07:56:00.86#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:56:00.86#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:56:00.86#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:56:00.86#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:56:00.87$vc4f8/vblo=5,744.99 2006.238.07:56:00.87#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.07:56:00.87#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.07:56:00.87#ibcon#ireg 17 cls_cnt 0 2006.238.07:56:00.87#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:56:00.87#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:56:00.87#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:56:00.87#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:56:00.87#ibcon#first serial, iclass 39, count 0 2006.238.07:56:00.87#ibcon#enter sib2, iclass 39, count 0 2006.238.07:56:00.87#ibcon#flushed, iclass 39, count 0 2006.238.07:56:00.87#ibcon#about to write, iclass 39, count 0 2006.238.07:56:00.87#ibcon#wrote, iclass 39, count 0 2006.238.07:56:00.87#ibcon#about to read 3, iclass 39, count 0 2006.238.07:56:00.88#ibcon#read 3, iclass 39, count 0 2006.238.07:56:00.88#ibcon#about to read 4, iclass 39, count 0 2006.238.07:56:00.88#ibcon#read 4, iclass 39, count 0 2006.238.07:56:00.88#ibcon#about to read 5, iclass 39, count 0 2006.238.07:56:00.88#ibcon#read 5, iclass 39, count 0 2006.238.07:56:00.88#ibcon#about to read 6, iclass 39, count 0 2006.238.07:56:00.88#ibcon#read 6, iclass 39, count 0 2006.238.07:56:00.88#ibcon#end of sib2, iclass 39, count 0 2006.238.07:56:00.88#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:56:00.88#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:56:00.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:56:00.88#ibcon#*before write, iclass 39, count 0 2006.238.07:56:00.88#ibcon#enter sib2, iclass 39, count 0 2006.238.07:56:00.88#ibcon#flushed, iclass 39, count 0 2006.238.07:56:00.88#ibcon#about to write, iclass 39, count 0 2006.238.07:56:00.88#ibcon#wrote, iclass 39, count 0 2006.238.07:56:00.88#ibcon#about to read 3, iclass 39, count 0 2006.238.07:56:00.92#ibcon#read 3, iclass 39, count 0 2006.238.07:56:00.92#ibcon#about to read 4, iclass 39, count 0 2006.238.07:56:00.92#ibcon#read 4, iclass 39, count 0 2006.238.07:56:00.92#ibcon#about to read 5, iclass 39, count 0 2006.238.07:56:00.92#ibcon#read 5, iclass 39, count 0 2006.238.07:56:00.92#ibcon#about to read 6, iclass 39, count 0 2006.238.07:56:00.92#ibcon#read 6, iclass 39, count 0 2006.238.07:56:00.92#ibcon#end of sib2, iclass 39, count 0 2006.238.07:56:00.92#ibcon#*after write, iclass 39, count 0 2006.238.07:56:00.92#ibcon#*before return 0, iclass 39, count 0 2006.238.07:56:00.92#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:56:00.92#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:56:00.92#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:56:00.92#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:56:00.93$vc4f8/vb=5,4 2006.238.07:56:00.93#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.07:56:00.93#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.07:56:00.93#ibcon#ireg 11 cls_cnt 2 2006.238.07:56:00.93#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:56:00.97#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:56:00.97#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:56:00.97#ibcon#enter wrdev, iclass 3, count 2 2006.238.07:56:00.97#ibcon#first serial, iclass 3, count 2 2006.238.07:56:00.97#ibcon#enter sib2, iclass 3, count 2 2006.238.07:56:00.97#ibcon#flushed, iclass 3, count 2 2006.238.07:56:00.97#ibcon#about to write, iclass 3, count 2 2006.238.07:56:00.97#ibcon#wrote, iclass 3, count 2 2006.238.07:56:00.97#ibcon#about to read 3, iclass 3, count 2 2006.238.07:56:00.99#ibcon#read 3, iclass 3, count 2 2006.238.07:56:00.99#ibcon#about to read 4, iclass 3, count 2 2006.238.07:56:00.99#ibcon#read 4, iclass 3, count 2 2006.238.07:56:00.99#ibcon#about to read 5, iclass 3, count 2 2006.238.07:56:00.99#ibcon#read 5, iclass 3, count 2 2006.238.07:56:00.99#ibcon#about to read 6, iclass 3, count 2 2006.238.07:56:00.99#ibcon#read 6, iclass 3, count 2 2006.238.07:56:00.99#ibcon#end of sib2, iclass 3, count 2 2006.238.07:56:00.99#ibcon#*mode == 0, iclass 3, count 2 2006.238.07:56:00.99#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.07:56:00.99#ibcon#[27=AT05-04\r\n] 2006.238.07:56:00.99#ibcon#*before write, iclass 3, count 2 2006.238.07:56:00.99#ibcon#enter sib2, iclass 3, count 2 2006.238.07:56:00.99#ibcon#flushed, iclass 3, count 2 2006.238.07:56:00.99#ibcon#about to write, iclass 3, count 2 2006.238.07:56:00.99#ibcon#wrote, iclass 3, count 2 2006.238.07:56:00.99#ibcon#about to read 3, iclass 3, count 2 2006.238.07:56:01.02#ibcon#read 3, iclass 3, count 2 2006.238.07:56:01.02#ibcon#about to read 4, iclass 3, count 2 2006.238.07:56:01.02#ibcon#read 4, iclass 3, count 2 2006.238.07:56:01.02#ibcon#about to read 5, iclass 3, count 2 2006.238.07:56:01.02#ibcon#read 5, iclass 3, count 2 2006.238.07:56:01.02#ibcon#about to read 6, iclass 3, count 2 2006.238.07:56:01.02#ibcon#read 6, iclass 3, count 2 2006.238.07:56:01.02#ibcon#end of sib2, iclass 3, count 2 2006.238.07:56:01.02#ibcon#*after write, iclass 3, count 2 2006.238.07:56:01.02#ibcon#*before return 0, iclass 3, count 2 2006.238.07:56:01.02#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:56:01.02#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:56:01.02#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.07:56:01.02#ibcon#ireg 7 cls_cnt 0 2006.238.07:56:01.02#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:56:01.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:56:01.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:56:01.15#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:56:01.15#ibcon#first serial, iclass 3, count 0 2006.238.07:56:01.15#ibcon#enter sib2, iclass 3, count 0 2006.238.07:56:01.15#ibcon#flushed, iclass 3, count 0 2006.238.07:56:01.15#ibcon#about to write, iclass 3, count 0 2006.238.07:56:01.15#ibcon#wrote, iclass 3, count 0 2006.238.07:56:01.15#ibcon#about to read 3, iclass 3, count 0 2006.238.07:56:01.16#ibcon#read 3, iclass 3, count 0 2006.238.07:56:01.16#ibcon#about to read 4, iclass 3, count 0 2006.238.07:56:01.16#ibcon#read 4, iclass 3, count 0 2006.238.07:56:01.16#ibcon#about to read 5, iclass 3, count 0 2006.238.07:56:01.16#ibcon#read 5, iclass 3, count 0 2006.238.07:56:01.16#ibcon#about to read 6, iclass 3, count 0 2006.238.07:56:01.16#ibcon#read 6, iclass 3, count 0 2006.238.07:56:01.16#ibcon#end of sib2, iclass 3, count 0 2006.238.07:56:01.16#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:56:01.16#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:56:01.16#ibcon#[27=USB\r\n] 2006.238.07:56:01.16#ibcon#*before write, iclass 3, count 0 2006.238.07:56:01.16#ibcon#enter sib2, iclass 3, count 0 2006.238.07:56:01.16#ibcon#flushed, iclass 3, count 0 2006.238.07:56:01.16#ibcon#about to write, iclass 3, count 0 2006.238.07:56:01.16#ibcon#wrote, iclass 3, count 0 2006.238.07:56:01.16#ibcon#about to read 3, iclass 3, count 0 2006.238.07:56:01.19#ibcon#read 3, iclass 3, count 0 2006.238.07:56:01.19#ibcon#about to read 4, iclass 3, count 0 2006.238.07:56:01.19#ibcon#read 4, iclass 3, count 0 2006.238.07:56:01.19#ibcon#about to read 5, iclass 3, count 0 2006.238.07:56:01.19#ibcon#read 5, iclass 3, count 0 2006.238.07:56:01.19#ibcon#about to read 6, iclass 3, count 0 2006.238.07:56:01.19#ibcon#read 6, iclass 3, count 0 2006.238.07:56:01.19#ibcon#end of sib2, iclass 3, count 0 2006.238.07:56:01.19#ibcon#*after write, iclass 3, count 0 2006.238.07:56:01.19#ibcon#*before return 0, iclass 3, count 0 2006.238.07:56:01.19#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:56:01.19#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:56:01.19#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:56:01.19#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:56:01.20$vc4f8/vblo=6,752.99 2006.238.07:56:01.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.07:56:01.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.07:56:01.20#ibcon#ireg 17 cls_cnt 0 2006.238.07:56:01.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:56:01.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:56:01.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:56:01.20#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:56:01.20#ibcon#first serial, iclass 5, count 0 2006.238.07:56:01.20#ibcon#enter sib2, iclass 5, count 0 2006.238.07:56:01.20#ibcon#flushed, iclass 5, count 0 2006.238.07:56:01.20#ibcon#about to write, iclass 5, count 0 2006.238.07:56:01.20#ibcon#wrote, iclass 5, count 0 2006.238.07:56:01.20#ibcon#about to read 3, iclass 5, count 0 2006.238.07:56:01.21#ibcon#read 3, iclass 5, count 0 2006.238.07:56:01.21#ibcon#about to read 4, iclass 5, count 0 2006.238.07:56:01.21#ibcon#read 4, iclass 5, count 0 2006.238.07:56:01.21#ibcon#about to read 5, iclass 5, count 0 2006.238.07:56:01.21#ibcon#read 5, iclass 5, count 0 2006.238.07:56:01.21#ibcon#about to read 6, iclass 5, count 0 2006.238.07:56:01.21#ibcon#read 6, iclass 5, count 0 2006.238.07:56:01.21#ibcon#end of sib2, iclass 5, count 0 2006.238.07:56:01.21#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:56:01.21#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:56:01.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:56:01.21#ibcon#*before write, iclass 5, count 0 2006.238.07:56:01.21#ibcon#enter sib2, iclass 5, count 0 2006.238.07:56:01.21#ibcon#flushed, iclass 5, count 0 2006.238.07:56:01.21#ibcon#about to write, iclass 5, count 0 2006.238.07:56:01.21#ibcon#wrote, iclass 5, count 0 2006.238.07:56:01.21#ibcon#about to read 3, iclass 5, count 0 2006.238.07:56:01.25#ibcon#read 3, iclass 5, count 0 2006.238.07:56:01.25#ibcon#about to read 4, iclass 5, count 0 2006.238.07:56:01.25#ibcon#read 4, iclass 5, count 0 2006.238.07:56:01.25#ibcon#about to read 5, iclass 5, count 0 2006.238.07:56:01.25#ibcon#read 5, iclass 5, count 0 2006.238.07:56:01.25#ibcon#about to read 6, iclass 5, count 0 2006.238.07:56:01.25#ibcon#read 6, iclass 5, count 0 2006.238.07:56:01.25#ibcon#end of sib2, iclass 5, count 0 2006.238.07:56:01.25#ibcon#*after write, iclass 5, count 0 2006.238.07:56:01.25#ibcon#*before return 0, iclass 5, count 0 2006.238.07:56:01.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:56:01.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:56:01.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:56:01.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:56:01.26$vc4f8/vb=6,4 2006.238.07:56:01.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.07:56:01.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.07:56:01.26#ibcon#ireg 11 cls_cnt 2 2006.238.07:56:01.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:56:01.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:56:01.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:56:01.30#ibcon#enter wrdev, iclass 7, count 2 2006.238.07:56:01.30#ibcon#first serial, iclass 7, count 2 2006.238.07:56:01.30#ibcon#enter sib2, iclass 7, count 2 2006.238.07:56:01.30#ibcon#flushed, iclass 7, count 2 2006.238.07:56:01.30#ibcon#about to write, iclass 7, count 2 2006.238.07:56:01.30#ibcon#wrote, iclass 7, count 2 2006.238.07:56:01.30#ibcon#about to read 3, iclass 7, count 2 2006.238.07:56:01.32#ibcon#read 3, iclass 7, count 2 2006.238.07:56:01.32#ibcon#about to read 4, iclass 7, count 2 2006.238.07:56:01.32#ibcon#read 4, iclass 7, count 2 2006.238.07:56:01.32#ibcon#about to read 5, iclass 7, count 2 2006.238.07:56:01.32#ibcon#read 5, iclass 7, count 2 2006.238.07:56:01.32#ibcon#about to read 6, iclass 7, count 2 2006.238.07:56:01.32#ibcon#read 6, iclass 7, count 2 2006.238.07:56:01.32#ibcon#end of sib2, iclass 7, count 2 2006.238.07:56:01.32#ibcon#*mode == 0, iclass 7, count 2 2006.238.07:56:01.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.07:56:01.32#ibcon#[27=AT06-04\r\n] 2006.238.07:56:01.32#ibcon#*before write, iclass 7, count 2 2006.238.07:56:01.32#ibcon#enter sib2, iclass 7, count 2 2006.238.07:56:01.32#ibcon#flushed, iclass 7, count 2 2006.238.07:56:01.32#ibcon#about to write, iclass 7, count 2 2006.238.07:56:01.32#ibcon#wrote, iclass 7, count 2 2006.238.07:56:01.32#ibcon#about to read 3, iclass 7, count 2 2006.238.07:56:01.35#ibcon#read 3, iclass 7, count 2 2006.238.07:56:01.35#ibcon#about to read 4, iclass 7, count 2 2006.238.07:56:01.35#ibcon#read 4, iclass 7, count 2 2006.238.07:56:01.35#ibcon#about to read 5, iclass 7, count 2 2006.238.07:56:01.35#ibcon#read 5, iclass 7, count 2 2006.238.07:56:01.35#ibcon#about to read 6, iclass 7, count 2 2006.238.07:56:01.35#ibcon#read 6, iclass 7, count 2 2006.238.07:56:01.35#ibcon#end of sib2, iclass 7, count 2 2006.238.07:56:01.35#ibcon#*after write, iclass 7, count 2 2006.238.07:56:01.35#ibcon#*before return 0, iclass 7, count 2 2006.238.07:56:01.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:56:01.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:56:01.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.07:56:01.35#ibcon#ireg 7 cls_cnt 0 2006.238.07:56:01.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:56:01.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:56:01.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:56:01.47#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:56:01.47#ibcon#first serial, iclass 7, count 0 2006.238.07:56:01.47#ibcon#enter sib2, iclass 7, count 0 2006.238.07:56:01.47#ibcon#flushed, iclass 7, count 0 2006.238.07:56:01.47#ibcon#about to write, iclass 7, count 0 2006.238.07:56:01.47#ibcon#wrote, iclass 7, count 0 2006.238.07:56:01.47#ibcon#about to read 3, iclass 7, count 0 2006.238.07:56:01.49#ibcon#read 3, iclass 7, count 0 2006.238.07:56:01.49#ibcon#about to read 4, iclass 7, count 0 2006.238.07:56:01.49#ibcon#read 4, iclass 7, count 0 2006.238.07:56:01.49#ibcon#about to read 5, iclass 7, count 0 2006.238.07:56:01.49#ibcon#read 5, iclass 7, count 0 2006.238.07:56:01.49#ibcon#about to read 6, iclass 7, count 0 2006.238.07:56:01.49#ibcon#read 6, iclass 7, count 0 2006.238.07:56:01.49#ibcon#end of sib2, iclass 7, count 0 2006.238.07:56:01.49#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:56:01.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:56:01.49#ibcon#[27=USB\r\n] 2006.238.07:56:01.49#ibcon#*before write, iclass 7, count 0 2006.238.07:56:01.49#ibcon#enter sib2, iclass 7, count 0 2006.238.07:56:01.49#ibcon#flushed, iclass 7, count 0 2006.238.07:56:01.49#ibcon#about to write, iclass 7, count 0 2006.238.07:56:01.49#ibcon#wrote, iclass 7, count 0 2006.238.07:56:01.49#ibcon#about to read 3, iclass 7, count 0 2006.238.07:56:01.52#ibcon#read 3, iclass 7, count 0 2006.238.07:56:01.52#ibcon#about to read 4, iclass 7, count 0 2006.238.07:56:01.52#ibcon#read 4, iclass 7, count 0 2006.238.07:56:01.52#ibcon#about to read 5, iclass 7, count 0 2006.238.07:56:01.52#ibcon#read 5, iclass 7, count 0 2006.238.07:56:01.52#ibcon#about to read 6, iclass 7, count 0 2006.238.07:56:01.52#ibcon#read 6, iclass 7, count 0 2006.238.07:56:01.52#ibcon#end of sib2, iclass 7, count 0 2006.238.07:56:01.52#ibcon#*after write, iclass 7, count 0 2006.238.07:56:01.52#ibcon#*before return 0, iclass 7, count 0 2006.238.07:56:01.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:56:01.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:56:01.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:56:01.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:56:01.53$vc4f8/vabw=wide 2006.238.07:56:01.53#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.07:56:01.53#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.07:56:01.53#ibcon#ireg 8 cls_cnt 0 2006.238.07:56:01.53#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:56:01.53#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:56:01.53#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:56:01.53#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:56:01.53#ibcon#first serial, iclass 11, count 0 2006.238.07:56:01.53#ibcon#enter sib2, iclass 11, count 0 2006.238.07:56:01.53#ibcon#flushed, iclass 11, count 0 2006.238.07:56:01.53#ibcon#about to write, iclass 11, count 0 2006.238.07:56:01.53#ibcon#wrote, iclass 11, count 0 2006.238.07:56:01.53#ibcon#about to read 3, iclass 11, count 0 2006.238.07:56:01.54#ibcon#read 3, iclass 11, count 0 2006.238.07:56:01.54#ibcon#about to read 4, iclass 11, count 0 2006.238.07:56:01.54#ibcon#read 4, iclass 11, count 0 2006.238.07:56:01.54#ibcon#about to read 5, iclass 11, count 0 2006.238.07:56:01.54#ibcon#read 5, iclass 11, count 0 2006.238.07:56:01.54#ibcon#about to read 6, iclass 11, count 0 2006.238.07:56:01.54#ibcon#read 6, iclass 11, count 0 2006.238.07:56:01.54#ibcon#end of sib2, iclass 11, count 0 2006.238.07:56:01.54#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:56:01.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:56:01.54#ibcon#[25=BW32\r\n] 2006.238.07:56:01.54#ibcon#*before write, iclass 11, count 0 2006.238.07:56:01.54#ibcon#enter sib2, iclass 11, count 0 2006.238.07:56:01.54#ibcon#flushed, iclass 11, count 0 2006.238.07:56:01.54#ibcon#about to write, iclass 11, count 0 2006.238.07:56:01.54#ibcon#wrote, iclass 11, count 0 2006.238.07:56:01.54#ibcon#about to read 3, iclass 11, count 0 2006.238.07:56:01.57#ibcon#read 3, iclass 11, count 0 2006.238.07:56:01.57#ibcon#about to read 4, iclass 11, count 0 2006.238.07:56:01.57#ibcon#read 4, iclass 11, count 0 2006.238.07:56:01.57#ibcon#about to read 5, iclass 11, count 0 2006.238.07:56:01.57#ibcon#read 5, iclass 11, count 0 2006.238.07:56:01.57#ibcon#about to read 6, iclass 11, count 0 2006.238.07:56:01.57#ibcon#read 6, iclass 11, count 0 2006.238.07:56:01.57#ibcon#end of sib2, iclass 11, count 0 2006.238.07:56:01.57#ibcon#*after write, iclass 11, count 0 2006.238.07:56:01.57#ibcon#*before return 0, iclass 11, count 0 2006.238.07:56:01.57#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:56:01.57#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:56:01.57#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:56:01.57#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:56:01.58$vc4f8/vbbw=wide 2006.238.07:56:01.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.07:56:01.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.07:56:01.58#ibcon#ireg 8 cls_cnt 0 2006.238.07:56:01.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:56:01.63#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:56:01.63#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:56:01.63#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:56:01.63#ibcon#first serial, iclass 13, count 0 2006.238.07:56:01.63#ibcon#enter sib2, iclass 13, count 0 2006.238.07:56:01.63#ibcon#flushed, iclass 13, count 0 2006.238.07:56:01.63#ibcon#about to write, iclass 13, count 0 2006.238.07:56:01.63#ibcon#wrote, iclass 13, count 0 2006.238.07:56:01.63#ibcon#about to read 3, iclass 13, count 0 2006.238.07:56:01.65#ibcon#read 3, iclass 13, count 0 2006.238.07:56:01.65#ibcon#about to read 4, iclass 13, count 0 2006.238.07:56:01.65#ibcon#read 4, iclass 13, count 0 2006.238.07:56:01.65#ibcon#about to read 5, iclass 13, count 0 2006.238.07:56:01.65#ibcon#read 5, iclass 13, count 0 2006.238.07:56:01.65#ibcon#about to read 6, iclass 13, count 0 2006.238.07:56:01.65#ibcon#read 6, iclass 13, count 0 2006.238.07:56:01.65#ibcon#end of sib2, iclass 13, count 0 2006.238.07:56:01.65#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:56:01.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:56:01.65#ibcon#[27=BW32\r\n] 2006.238.07:56:01.65#ibcon#*before write, iclass 13, count 0 2006.238.07:56:01.65#ibcon#enter sib2, iclass 13, count 0 2006.238.07:56:01.65#ibcon#flushed, iclass 13, count 0 2006.238.07:56:01.65#ibcon#about to write, iclass 13, count 0 2006.238.07:56:01.65#ibcon#wrote, iclass 13, count 0 2006.238.07:56:01.65#ibcon#about to read 3, iclass 13, count 0 2006.238.07:56:01.68#ibcon#read 3, iclass 13, count 0 2006.238.07:56:01.68#ibcon#about to read 4, iclass 13, count 0 2006.238.07:56:01.68#ibcon#read 4, iclass 13, count 0 2006.238.07:56:01.68#ibcon#about to read 5, iclass 13, count 0 2006.238.07:56:01.68#ibcon#read 5, iclass 13, count 0 2006.238.07:56:01.68#ibcon#about to read 6, iclass 13, count 0 2006.238.07:56:01.68#ibcon#read 6, iclass 13, count 0 2006.238.07:56:01.68#ibcon#end of sib2, iclass 13, count 0 2006.238.07:56:01.68#ibcon#*after write, iclass 13, count 0 2006.238.07:56:01.68#ibcon#*before return 0, iclass 13, count 0 2006.238.07:56:01.68#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:56:01.68#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.07:56:01.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:56:01.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:56:01.69$4f8m12a/ifd4f 2006.238.07:56:01.69$ifd4f/lo= 2006.238.07:56:01.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:56:01.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:56:01.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:56:01.69$ifd4f/patch= 2006.238.07:56:01.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:56:01.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:56:01.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:56:01.69$4f8m12a/"form=m,16.000,1:2 2006.238.07:56:01.69$4f8m12a/"tpicd 2006.238.07:56:01.69$4f8m12a/echo=off 2006.238.07:56:01.69$4f8m12a/xlog=off 2006.238.07:56:01.69:!2006.238.07:58:10 2006.238.07:56:39.14#trakl#Source acquired 2006.238.07:56:40.14#flagr#flagr/antenna,acquired 2006.238.07:58:10.01:preob 2006.238.07:58:11.14/onsource/TRACKING 2006.238.07:58:11.14:!2006.238.07:58:20 2006.238.07:58:20.00:data_valid=on 2006.238.07:58:20.00:midob 2006.238.07:58:20.14/onsource/TRACKING 2006.238.07:58:20.15/wx/25.42,1012.2,88 2006.238.07:58:20.33/cable/+6.4179E-03 2006.238.07:58:21.42/va/01,08,usb,yes,37,39 2006.238.07:58:21.42/va/02,07,usb,yes,37,39 2006.238.07:58:21.42/va/03,07,usb,yes,35,35 2006.238.07:58:21.42/va/04,07,usb,yes,38,41 2006.238.07:58:21.42/va/05,08,usb,yes,36,37 2006.238.07:58:21.42/va/06,07,usb,yes,38,38 2006.238.07:58:21.42/va/07,07,usb,yes,38,38 2006.238.07:58:21.42/va/08,07,usb,yes,41,41 2006.238.07:58:21.65/valo/01,532.99,yes,locked 2006.238.07:58:21.65/valo/02,572.99,yes,locked 2006.238.07:58:21.65/valo/03,672.99,yes,locked 2006.238.07:58:21.65/valo/04,832.99,yes,locked 2006.238.07:58:21.65/valo/05,652.99,yes,locked 2006.238.07:58:21.65/valo/06,772.99,yes,locked 2006.238.07:58:21.65/valo/07,832.99,yes,locked 2006.238.07:58:21.65/valo/08,852.99,yes,locked 2006.238.07:58:22.74/vb/01,04,usb,yes,33,60 2006.238.07:58:22.74/vb/02,04,usb,yes,34,60 2006.238.07:58:22.74/vb/03,04,usb,yes,31,36 2006.238.07:58:22.74/vb/04,04,usb,yes,33,32 2006.238.07:58:22.74/vb/05,04,usb,yes,31,36 2006.238.07:58:22.74/vb/06,04,usb,yes,32,35 2006.238.07:58:22.74/vb/07,04,usb,yes,34,35 2006.238.07:58:22.74/vb/08,04,usb,yes,31,36 2006.238.07:58:22.97/vblo/01,632.99,yes,locked 2006.238.07:58:22.97/vblo/02,640.99,yes,locked 2006.238.07:58:22.97/vblo/03,656.99,yes,locked 2006.238.07:58:22.97/vblo/04,712.99,yes,locked 2006.238.07:58:22.97/vblo/05,744.99,yes,locked 2006.238.07:58:22.97/vblo/06,752.99,yes,locked 2006.238.07:58:22.97/vblo/07,734.99,yes,locked 2006.238.07:58:22.97/vblo/08,744.99,yes,locked 2006.238.07:58:23.12/vabw/8 2006.238.07:58:23.27/vbbw/8 2006.238.07:58:25.65/xfe/off,on,12.7 2006.238.07:58:26.04/ifatt/23,28,28,28 2006.238.07:58:27.07/fmout-gps/S +4.29E-07 2006.238.07:58:27.12:!2006.238.07:59:20 2006.238.07:59:20.01:data_valid=off 2006.238.07:59:20.02:postob 2006.238.07:59:20.21/cable/+6.4174E-03 2006.238.07:59:20.22/wx/25.42,1012.2,88 2006.238.07:59:20.27/fmout-gps/S +4.30E-07 2006.238.07:59:20.28:scan_name=238-0800,k06238,60 2006.238.07:59:20.28:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.238.07:59:21.13#flagr#flagr/antenna,new-source 2006.238.07:59:21.14:checkk5 2006.238.07:59:21.51/chk_autoobs//k5ts1/ autoobs is running! 2006.238.07:59:21.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.07:59:22.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.07:59:22.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.07:59:23.03/chk_obsdata//k5ts1/T2380758??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:59:23.40/chk_obsdata//k5ts2/T2380758??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:59:23.77/chk_obsdata//k5ts3/T2380758??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:59:24.14/chk_obsdata//k5ts4/T2380758??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.07:59:24.83/k5log//k5ts1_log_newline 2006.238.07:59:25.52/k5log//k5ts2_log_newline 2006.238.07:59:26.21/k5log//k5ts3_log_newline 2006.238.07:59:26.90/k5log//k5ts4_log_newline 2006.238.07:59:26.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.07:59:26.93:4f8m12a=2 2006.238.07:59:26.93$4f8m12a/echo=on 2006.238.07:59:26.93$4f8m12a/pcalon 2006.238.07:59:26.93$pcalon/"no phase cal control is implemented here 2006.238.07:59:26.93$4f8m12a/"tpicd=stop 2006.238.07:59:26.93$4f8m12a/vc4f8 2006.238.07:59:26.93$vc4f8/valo=1,532.99 2006.238.07:59:26.93#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.07:59:26.93#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.07:59:26.93#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:26.93#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:59:26.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:59:26.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:59:26.93#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:59:26.93#ibcon#first serial, iclass 19, count 0 2006.238.07:59:26.93#ibcon#enter sib2, iclass 19, count 0 2006.238.07:59:26.93#ibcon#flushed, iclass 19, count 0 2006.238.07:59:26.93#ibcon#about to write, iclass 19, count 0 2006.238.07:59:26.93#ibcon#wrote, iclass 19, count 0 2006.238.07:59:26.93#ibcon#about to read 3, iclass 19, count 0 2006.238.07:59:26.94#ibcon#read 3, iclass 19, count 0 2006.238.07:59:26.94#ibcon#about to read 4, iclass 19, count 0 2006.238.07:59:26.94#ibcon#read 4, iclass 19, count 0 2006.238.07:59:26.94#ibcon#about to read 5, iclass 19, count 0 2006.238.07:59:26.94#ibcon#read 5, iclass 19, count 0 2006.238.07:59:26.94#ibcon#about to read 6, iclass 19, count 0 2006.238.07:59:26.94#ibcon#read 6, iclass 19, count 0 2006.238.07:59:26.94#ibcon#end of sib2, iclass 19, count 0 2006.238.07:59:26.94#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:59:26.94#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:59:26.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.07:59:26.94#ibcon#*before write, iclass 19, count 0 2006.238.07:59:26.94#ibcon#enter sib2, iclass 19, count 0 2006.238.07:59:26.94#ibcon#flushed, iclass 19, count 0 2006.238.07:59:26.94#ibcon#about to write, iclass 19, count 0 2006.238.07:59:26.94#ibcon#wrote, iclass 19, count 0 2006.238.07:59:26.94#ibcon#about to read 3, iclass 19, count 0 2006.238.07:59:26.99#ibcon#read 3, iclass 19, count 0 2006.238.07:59:26.99#ibcon#about to read 4, iclass 19, count 0 2006.238.07:59:26.99#ibcon#read 4, iclass 19, count 0 2006.238.07:59:26.99#ibcon#about to read 5, iclass 19, count 0 2006.238.07:59:26.99#ibcon#read 5, iclass 19, count 0 2006.238.07:59:26.99#ibcon#about to read 6, iclass 19, count 0 2006.238.07:59:26.99#ibcon#read 6, iclass 19, count 0 2006.238.07:59:26.99#ibcon#end of sib2, iclass 19, count 0 2006.238.07:59:26.99#ibcon#*after write, iclass 19, count 0 2006.238.07:59:26.99#ibcon#*before return 0, iclass 19, count 0 2006.238.07:59:26.99#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:59:26.99#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:59:26.99#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:59:26.99#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:59:26.99$vc4f8/va=1,8 2006.238.07:59:26.99#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.07:59:26.99#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.07:59:26.99#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:26.99#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:59:26.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:59:26.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:59:26.99#ibcon#enter wrdev, iclass 21, count 2 2006.238.07:59:26.99#ibcon#first serial, iclass 21, count 2 2006.238.07:59:26.99#ibcon#enter sib2, iclass 21, count 2 2006.238.07:59:26.99#ibcon#flushed, iclass 21, count 2 2006.238.07:59:26.99#ibcon#about to write, iclass 21, count 2 2006.238.07:59:26.99#ibcon#wrote, iclass 21, count 2 2006.238.07:59:26.99#ibcon#about to read 3, iclass 21, count 2 2006.238.07:59:27.01#ibcon#read 3, iclass 21, count 2 2006.238.07:59:27.01#ibcon#about to read 4, iclass 21, count 2 2006.238.07:59:27.01#ibcon#read 4, iclass 21, count 2 2006.238.07:59:27.01#ibcon#about to read 5, iclass 21, count 2 2006.238.07:59:27.01#ibcon#read 5, iclass 21, count 2 2006.238.07:59:27.01#ibcon#about to read 6, iclass 21, count 2 2006.238.07:59:27.01#ibcon#read 6, iclass 21, count 2 2006.238.07:59:27.01#ibcon#end of sib2, iclass 21, count 2 2006.238.07:59:27.01#ibcon#*mode == 0, iclass 21, count 2 2006.238.07:59:27.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.07:59:27.01#ibcon#[25=AT01-08\r\n] 2006.238.07:59:27.01#ibcon#*before write, iclass 21, count 2 2006.238.07:59:27.01#ibcon#enter sib2, iclass 21, count 2 2006.238.07:59:27.01#ibcon#flushed, iclass 21, count 2 2006.238.07:59:27.01#ibcon#about to write, iclass 21, count 2 2006.238.07:59:27.01#ibcon#wrote, iclass 21, count 2 2006.238.07:59:27.01#ibcon#about to read 3, iclass 21, count 2 2006.238.07:59:27.05#ibcon#read 3, iclass 21, count 2 2006.238.07:59:27.05#ibcon#about to read 4, iclass 21, count 2 2006.238.07:59:27.05#ibcon#read 4, iclass 21, count 2 2006.238.07:59:27.05#ibcon#about to read 5, iclass 21, count 2 2006.238.07:59:27.05#ibcon#read 5, iclass 21, count 2 2006.238.07:59:27.05#ibcon#about to read 6, iclass 21, count 2 2006.238.07:59:27.05#ibcon#read 6, iclass 21, count 2 2006.238.07:59:27.05#ibcon#end of sib2, iclass 21, count 2 2006.238.07:59:27.05#ibcon#*after write, iclass 21, count 2 2006.238.07:59:27.05#ibcon#*before return 0, iclass 21, count 2 2006.238.07:59:27.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:59:27.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:59:27.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.07:59:27.05#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:27.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:59:27.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:59:27.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:59:27.16#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:59:27.16#ibcon#first serial, iclass 21, count 0 2006.238.07:59:27.16#ibcon#enter sib2, iclass 21, count 0 2006.238.07:59:27.16#ibcon#flushed, iclass 21, count 0 2006.238.07:59:27.16#ibcon#about to write, iclass 21, count 0 2006.238.07:59:27.16#ibcon#wrote, iclass 21, count 0 2006.238.07:59:27.16#ibcon#about to read 3, iclass 21, count 0 2006.238.07:59:27.18#ibcon#read 3, iclass 21, count 0 2006.238.07:59:27.18#ibcon#about to read 4, iclass 21, count 0 2006.238.07:59:27.18#ibcon#read 4, iclass 21, count 0 2006.238.07:59:27.18#ibcon#about to read 5, iclass 21, count 0 2006.238.07:59:27.18#ibcon#read 5, iclass 21, count 0 2006.238.07:59:27.18#ibcon#about to read 6, iclass 21, count 0 2006.238.07:59:27.18#ibcon#read 6, iclass 21, count 0 2006.238.07:59:27.18#ibcon#end of sib2, iclass 21, count 0 2006.238.07:59:27.18#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:59:27.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:59:27.18#ibcon#[25=USB\r\n] 2006.238.07:59:27.18#ibcon#*before write, iclass 21, count 0 2006.238.07:59:27.18#ibcon#enter sib2, iclass 21, count 0 2006.238.07:59:27.18#ibcon#flushed, iclass 21, count 0 2006.238.07:59:27.18#ibcon#about to write, iclass 21, count 0 2006.238.07:59:27.18#ibcon#wrote, iclass 21, count 0 2006.238.07:59:27.18#ibcon#about to read 3, iclass 21, count 0 2006.238.07:59:27.21#ibcon#read 3, iclass 21, count 0 2006.238.07:59:27.21#ibcon#about to read 4, iclass 21, count 0 2006.238.07:59:27.21#ibcon#read 4, iclass 21, count 0 2006.238.07:59:27.21#ibcon#about to read 5, iclass 21, count 0 2006.238.07:59:27.21#ibcon#read 5, iclass 21, count 0 2006.238.07:59:27.21#ibcon#about to read 6, iclass 21, count 0 2006.238.07:59:27.21#ibcon#read 6, iclass 21, count 0 2006.238.07:59:27.21#ibcon#end of sib2, iclass 21, count 0 2006.238.07:59:27.21#ibcon#*after write, iclass 21, count 0 2006.238.07:59:27.21#ibcon#*before return 0, iclass 21, count 0 2006.238.07:59:27.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:59:27.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:59:27.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:59:27.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:59:27.21$vc4f8/valo=2,572.99 2006.238.07:59:27.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:59:27.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:59:27.21#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:27.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:59:27.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:59:27.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:59:27.21#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:59:27.21#ibcon#first serial, iclass 23, count 0 2006.238.07:59:27.21#ibcon#enter sib2, iclass 23, count 0 2006.238.07:59:27.21#ibcon#flushed, iclass 23, count 0 2006.238.07:59:27.21#ibcon#about to write, iclass 23, count 0 2006.238.07:59:27.21#ibcon#wrote, iclass 23, count 0 2006.238.07:59:27.21#ibcon#about to read 3, iclass 23, count 0 2006.238.07:59:27.23#ibcon#read 3, iclass 23, count 0 2006.238.07:59:27.23#ibcon#about to read 4, iclass 23, count 0 2006.238.07:59:27.23#ibcon#read 4, iclass 23, count 0 2006.238.07:59:27.23#ibcon#about to read 5, iclass 23, count 0 2006.238.07:59:27.23#ibcon#read 5, iclass 23, count 0 2006.238.07:59:27.23#ibcon#about to read 6, iclass 23, count 0 2006.238.07:59:27.23#ibcon#read 6, iclass 23, count 0 2006.238.07:59:27.23#ibcon#end of sib2, iclass 23, count 0 2006.238.07:59:27.23#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:59:27.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:59:27.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.07:59:27.23#ibcon#*before write, iclass 23, count 0 2006.238.07:59:27.23#ibcon#enter sib2, iclass 23, count 0 2006.238.07:59:27.23#ibcon#flushed, iclass 23, count 0 2006.238.07:59:27.23#ibcon#about to write, iclass 23, count 0 2006.238.07:59:27.23#ibcon#wrote, iclass 23, count 0 2006.238.07:59:27.23#ibcon#about to read 3, iclass 23, count 0 2006.238.07:59:27.28#ibcon#read 3, iclass 23, count 0 2006.238.07:59:27.28#ibcon#about to read 4, iclass 23, count 0 2006.238.07:59:27.28#ibcon#read 4, iclass 23, count 0 2006.238.07:59:27.28#ibcon#about to read 5, iclass 23, count 0 2006.238.07:59:27.28#ibcon#read 5, iclass 23, count 0 2006.238.07:59:27.28#ibcon#about to read 6, iclass 23, count 0 2006.238.07:59:27.28#ibcon#read 6, iclass 23, count 0 2006.238.07:59:27.28#ibcon#end of sib2, iclass 23, count 0 2006.238.07:59:27.28#ibcon#*after write, iclass 23, count 0 2006.238.07:59:27.28#ibcon#*before return 0, iclass 23, count 0 2006.238.07:59:27.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:59:27.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:59:27.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:59:27.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:59:27.28$vc4f8/va=2,7 2006.238.07:59:27.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.07:59:27.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.07:59:27.28#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:27.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:59:27.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:59:27.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:59:27.32#ibcon#enter wrdev, iclass 25, count 2 2006.238.07:59:27.32#ibcon#first serial, iclass 25, count 2 2006.238.07:59:27.32#ibcon#enter sib2, iclass 25, count 2 2006.238.07:59:27.32#ibcon#flushed, iclass 25, count 2 2006.238.07:59:27.32#ibcon#about to write, iclass 25, count 2 2006.238.07:59:27.32#ibcon#wrote, iclass 25, count 2 2006.238.07:59:27.32#ibcon#about to read 3, iclass 25, count 2 2006.238.07:59:27.35#ibcon#read 3, iclass 25, count 2 2006.238.07:59:27.35#ibcon#about to read 4, iclass 25, count 2 2006.238.07:59:27.35#ibcon#read 4, iclass 25, count 2 2006.238.07:59:27.35#ibcon#about to read 5, iclass 25, count 2 2006.238.07:59:27.35#ibcon#read 5, iclass 25, count 2 2006.238.07:59:27.35#ibcon#about to read 6, iclass 25, count 2 2006.238.07:59:27.35#ibcon#read 6, iclass 25, count 2 2006.238.07:59:27.35#ibcon#end of sib2, iclass 25, count 2 2006.238.07:59:27.35#ibcon#*mode == 0, iclass 25, count 2 2006.238.07:59:27.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.07:59:27.35#ibcon#[25=AT02-07\r\n] 2006.238.07:59:27.35#ibcon#*before write, iclass 25, count 2 2006.238.07:59:27.35#ibcon#enter sib2, iclass 25, count 2 2006.238.07:59:27.35#ibcon#flushed, iclass 25, count 2 2006.238.07:59:27.35#ibcon#about to write, iclass 25, count 2 2006.238.07:59:27.35#ibcon#wrote, iclass 25, count 2 2006.238.07:59:27.35#ibcon#about to read 3, iclass 25, count 2 2006.238.07:59:27.38#ibcon#read 3, iclass 25, count 2 2006.238.07:59:27.38#ibcon#about to read 4, iclass 25, count 2 2006.238.07:59:27.38#ibcon#read 4, iclass 25, count 2 2006.238.07:59:27.38#ibcon#about to read 5, iclass 25, count 2 2006.238.07:59:27.38#ibcon#read 5, iclass 25, count 2 2006.238.07:59:27.38#ibcon#about to read 6, iclass 25, count 2 2006.238.07:59:27.38#ibcon#read 6, iclass 25, count 2 2006.238.07:59:27.38#ibcon#end of sib2, iclass 25, count 2 2006.238.07:59:27.38#ibcon#*after write, iclass 25, count 2 2006.238.07:59:27.38#ibcon#*before return 0, iclass 25, count 2 2006.238.07:59:27.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:59:27.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:59:27.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.07:59:27.38#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:27.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:59:27.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:59:27.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:59:27.50#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:59:27.50#ibcon#first serial, iclass 25, count 0 2006.238.07:59:27.50#ibcon#enter sib2, iclass 25, count 0 2006.238.07:59:27.50#ibcon#flushed, iclass 25, count 0 2006.238.07:59:27.50#ibcon#about to write, iclass 25, count 0 2006.238.07:59:27.50#ibcon#wrote, iclass 25, count 0 2006.238.07:59:27.50#ibcon#about to read 3, iclass 25, count 0 2006.238.07:59:27.52#ibcon#read 3, iclass 25, count 0 2006.238.07:59:27.52#ibcon#about to read 4, iclass 25, count 0 2006.238.07:59:27.52#ibcon#read 4, iclass 25, count 0 2006.238.07:59:27.52#ibcon#about to read 5, iclass 25, count 0 2006.238.07:59:27.52#ibcon#read 5, iclass 25, count 0 2006.238.07:59:27.52#ibcon#about to read 6, iclass 25, count 0 2006.238.07:59:27.52#ibcon#read 6, iclass 25, count 0 2006.238.07:59:27.52#ibcon#end of sib2, iclass 25, count 0 2006.238.07:59:27.52#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:59:27.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:59:27.52#ibcon#[25=USB\r\n] 2006.238.07:59:27.52#ibcon#*before write, iclass 25, count 0 2006.238.07:59:27.52#ibcon#enter sib2, iclass 25, count 0 2006.238.07:59:27.52#ibcon#flushed, iclass 25, count 0 2006.238.07:59:27.52#ibcon#about to write, iclass 25, count 0 2006.238.07:59:27.52#ibcon#wrote, iclass 25, count 0 2006.238.07:59:27.52#ibcon#about to read 3, iclass 25, count 0 2006.238.07:59:27.55#ibcon#read 3, iclass 25, count 0 2006.238.07:59:27.55#ibcon#about to read 4, iclass 25, count 0 2006.238.07:59:27.55#ibcon#read 4, iclass 25, count 0 2006.238.07:59:27.55#ibcon#about to read 5, iclass 25, count 0 2006.238.07:59:27.55#ibcon#read 5, iclass 25, count 0 2006.238.07:59:27.55#ibcon#about to read 6, iclass 25, count 0 2006.238.07:59:27.55#ibcon#read 6, iclass 25, count 0 2006.238.07:59:27.55#ibcon#end of sib2, iclass 25, count 0 2006.238.07:59:27.55#ibcon#*after write, iclass 25, count 0 2006.238.07:59:27.55#ibcon#*before return 0, iclass 25, count 0 2006.238.07:59:27.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:59:27.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:59:27.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:59:27.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:59:27.55$vc4f8/valo=3,672.99 2006.238.07:59:27.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:59:27.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:59:27.55#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:27.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:59:27.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:59:27.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:59:27.55#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:59:27.55#ibcon#first serial, iclass 27, count 0 2006.238.07:59:27.55#ibcon#enter sib2, iclass 27, count 0 2006.238.07:59:27.55#ibcon#flushed, iclass 27, count 0 2006.238.07:59:27.55#ibcon#about to write, iclass 27, count 0 2006.238.07:59:27.55#ibcon#wrote, iclass 27, count 0 2006.238.07:59:27.55#ibcon#about to read 3, iclass 27, count 0 2006.238.07:59:27.57#ibcon#read 3, iclass 27, count 0 2006.238.07:59:27.57#ibcon#about to read 4, iclass 27, count 0 2006.238.07:59:27.57#ibcon#read 4, iclass 27, count 0 2006.238.07:59:27.57#ibcon#about to read 5, iclass 27, count 0 2006.238.07:59:27.57#ibcon#read 5, iclass 27, count 0 2006.238.07:59:27.57#ibcon#about to read 6, iclass 27, count 0 2006.238.07:59:27.57#ibcon#read 6, iclass 27, count 0 2006.238.07:59:27.57#ibcon#end of sib2, iclass 27, count 0 2006.238.07:59:27.57#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:59:27.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:59:27.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.07:59:27.57#ibcon#*before write, iclass 27, count 0 2006.238.07:59:27.57#ibcon#enter sib2, iclass 27, count 0 2006.238.07:59:27.57#ibcon#flushed, iclass 27, count 0 2006.238.07:59:27.57#ibcon#about to write, iclass 27, count 0 2006.238.07:59:27.57#ibcon#wrote, iclass 27, count 0 2006.238.07:59:27.57#ibcon#about to read 3, iclass 27, count 0 2006.238.07:59:27.61#ibcon#read 3, iclass 27, count 0 2006.238.07:59:27.61#ibcon#about to read 4, iclass 27, count 0 2006.238.07:59:27.61#ibcon#read 4, iclass 27, count 0 2006.238.07:59:27.61#ibcon#about to read 5, iclass 27, count 0 2006.238.07:59:27.61#ibcon#read 5, iclass 27, count 0 2006.238.07:59:27.61#ibcon#about to read 6, iclass 27, count 0 2006.238.07:59:27.61#ibcon#read 6, iclass 27, count 0 2006.238.07:59:27.61#ibcon#end of sib2, iclass 27, count 0 2006.238.07:59:27.61#ibcon#*after write, iclass 27, count 0 2006.238.07:59:27.61#ibcon#*before return 0, iclass 27, count 0 2006.238.07:59:27.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:59:27.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:59:27.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:59:27.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:59:27.61$vc4f8/va=3,7 2006.238.07:59:27.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.07:59:27.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.07:59:27.61#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:27.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:59:27.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:59:27.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:59:27.67#ibcon#enter wrdev, iclass 29, count 2 2006.238.07:59:27.67#ibcon#first serial, iclass 29, count 2 2006.238.07:59:27.67#ibcon#enter sib2, iclass 29, count 2 2006.238.07:59:27.67#ibcon#flushed, iclass 29, count 2 2006.238.07:59:27.67#ibcon#about to write, iclass 29, count 2 2006.238.07:59:27.67#ibcon#wrote, iclass 29, count 2 2006.238.07:59:27.67#ibcon#about to read 3, iclass 29, count 2 2006.238.07:59:27.69#ibcon#read 3, iclass 29, count 2 2006.238.07:59:27.69#ibcon#about to read 4, iclass 29, count 2 2006.238.07:59:27.69#ibcon#read 4, iclass 29, count 2 2006.238.07:59:27.69#ibcon#about to read 5, iclass 29, count 2 2006.238.07:59:27.69#ibcon#read 5, iclass 29, count 2 2006.238.07:59:27.69#ibcon#about to read 6, iclass 29, count 2 2006.238.07:59:27.69#ibcon#read 6, iclass 29, count 2 2006.238.07:59:27.69#ibcon#end of sib2, iclass 29, count 2 2006.238.07:59:27.69#ibcon#*mode == 0, iclass 29, count 2 2006.238.07:59:27.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.07:59:27.69#ibcon#[25=AT03-07\r\n] 2006.238.07:59:27.69#ibcon#*before write, iclass 29, count 2 2006.238.07:59:27.69#ibcon#enter sib2, iclass 29, count 2 2006.238.07:59:27.69#ibcon#flushed, iclass 29, count 2 2006.238.07:59:27.69#ibcon#about to write, iclass 29, count 2 2006.238.07:59:27.69#ibcon#wrote, iclass 29, count 2 2006.238.07:59:27.69#ibcon#about to read 3, iclass 29, count 2 2006.238.07:59:27.72#ibcon#read 3, iclass 29, count 2 2006.238.07:59:27.72#ibcon#about to read 4, iclass 29, count 2 2006.238.07:59:27.72#ibcon#read 4, iclass 29, count 2 2006.238.07:59:27.72#ibcon#about to read 5, iclass 29, count 2 2006.238.07:59:27.72#ibcon#read 5, iclass 29, count 2 2006.238.07:59:27.72#ibcon#about to read 6, iclass 29, count 2 2006.238.07:59:27.72#ibcon#read 6, iclass 29, count 2 2006.238.07:59:27.72#ibcon#end of sib2, iclass 29, count 2 2006.238.07:59:27.72#ibcon#*after write, iclass 29, count 2 2006.238.07:59:27.72#ibcon#*before return 0, iclass 29, count 2 2006.238.07:59:27.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:59:27.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:59:27.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.07:59:27.72#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:27.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:59:27.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:59:27.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:59:27.84#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:59:27.84#ibcon#first serial, iclass 29, count 0 2006.238.07:59:27.84#ibcon#enter sib2, iclass 29, count 0 2006.238.07:59:27.84#ibcon#flushed, iclass 29, count 0 2006.238.07:59:27.84#ibcon#about to write, iclass 29, count 0 2006.238.07:59:27.84#ibcon#wrote, iclass 29, count 0 2006.238.07:59:27.84#ibcon#about to read 3, iclass 29, count 0 2006.238.07:59:27.86#ibcon#read 3, iclass 29, count 0 2006.238.07:59:27.86#ibcon#about to read 4, iclass 29, count 0 2006.238.07:59:27.86#ibcon#read 4, iclass 29, count 0 2006.238.07:59:27.86#ibcon#about to read 5, iclass 29, count 0 2006.238.07:59:27.86#ibcon#read 5, iclass 29, count 0 2006.238.07:59:27.86#ibcon#about to read 6, iclass 29, count 0 2006.238.07:59:27.86#ibcon#read 6, iclass 29, count 0 2006.238.07:59:27.86#ibcon#end of sib2, iclass 29, count 0 2006.238.07:59:27.86#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:59:27.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:59:27.86#ibcon#[25=USB\r\n] 2006.238.07:59:27.86#ibcon#*before write, iclass 29, count 0 2006.238.07:59:27.86#ibcon#enter sib2, iclass 29, count 0 2006.238.07:59:27.86#ibcon#flushed, iclass 29, count 0 2006.238.07:59:27.86#ibcon#about to write, iclass 29, count 0 2006.238.07:59:27.86#ibcon#wrote, iclass 29, count 0 2006.238.07:59:27.86#ibcon#about to read 3, iclass 29, count 0 2006.238.07:59:27.89#ibcon#read 3, iclass 29, count 0 2006.238.07:59:27.89#ibcon#about to read 4, iclass 29, count 0 2006.238.07:59:27.89#ibcon#read 4, iclass 29, count 0 2006.238.07:59:27.89#ibcon#about to read 5, iclass 29, count 0 2006.238.07:59:27.89#ibcon#read 5, iclass 29, count 0 2006.238.07:59:27.89#ibcon#about to read 6, iclass 29, count 0 2006.238.07:59:27.89#ibcon#read 6, iclass 29, count 0 2006.238.07:59:27.89#ibcon#end of sib2, iclass 29, count 0 2006.238.07:59:27.89#ibcon#*after write, iclass 29, count 0 2006.238.07:59:27.89#ibcon#*before return 0, iclass 29, count 0 2006.238.07:59:27.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:59:27.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:59:27.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:59:27.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:59:27.89$vc4f8/valo=4,832.99 2006.238.07:59:27.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.07:59:27.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.07:59:27.89#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:27.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:59:27.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:59:27.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:59:27.89#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:59:27.89#ibcon#first serial, iclass 31, count 0 2006.238.07:59:27.89#ibcon#enter sib2, iclass 31, count 0 2006.238.07:59:27.89#ibcon#flushed, iclass 31, count 0 2006.238.07:59:27.89#ibcon#about to write, iclass 31, count 0 2006.238.07:59:27.89#ibcon#wrote, iclass 31, count 0 2006.238.07:59:27.89#ibcon#about to read 3, iclass 31, count 0 2006.238.07:59:27.91#ibcon#read 3, iclass 31, count 0 2006.238.07:59:27.91#ibcon#about to read 4, iclass 31, count 0 2006.238.07:59:27.91#ibcon#read 4, iclass 31, count 0 2006.238.07:59:27.91#ibcon#about to read 5, iclass 31, count 0 2006.238.07:59:27.91#ibcon#read 5, iclass 31, count 0 2006.238.07:59:27.91#ibcon#about to read 6, iclass 31, count 0 2006.238.07:59:27.91#ibcon#read 6, iclass 31, count 0 2006.238.07:59:27.91#ibcon#end of sib2, iclass 31, count 0 2006.238.07:59:27.91#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:59:27.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:59:27.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.07:59:27.91#ibcon#*before write, iclass 31, count 0 2006.238.07:59:27.91#ibcon#enter sib2, iclass 31, count 0 2006.238.07:59:27.91#ibcon#flushed, iclass 31, count 0 2006.238.07:59:27.91#ibcon#about to write, iclass 31, count 0 2006.238.07:59:27.91#ibcon#wrote, iclass 31, count 0 2006.238.07:59:27.91#ibcon#about to read 3, iclass 31, count 0 2006.238.07:59:27.95#ibcon#read 3, iclass 31, count 0 2006.238.07:59:27.95#ibcon#about to read 4, iclass 31, count 0 2006.238.07:59:27.95#ibcon#read 4, iclass 31, count 0 2006.238.07:59:27.95#ibcon#about to read 5, iclass 31, count 0 2006.238.07:59:27.95#ibcon#read 5, iclass 31, count 0 2006.238.07:59:27.95#ibcon#about to read 6, iclass 31, count 0 2006.238.07:59:27.95#ibcon#read 6, iclass 31, count 0 2006.238.07:59:27.95#ibcon#end of sib2, iclass 31, count 0 2006.238.07:59:27.95#ibcon#*after write, iclass 31, count 0 2006.238.07:59:27.95#ibcon#*before return 0, iclass 31, count 0 2006.238.07:59:27.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:59:27.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:59:27.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:59:27.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:59:27.95$vc4f8/va=4,7 2006.238.07:59:27.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:59:27.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:59:27.95#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:27.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:59:28.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:59:28.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:59:28.01#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:59:28.01#ibcon#first serial, iclass 33, count 2 2006.238.07:59:28.01#ibcon#enter sib2, iclass 33, count 2 2006.238.07:59:28.01#ibcon#flushed, iclass 33, count 2 2006.238.07:59:28.01#ibcon#about to write, iclass 33, count 2 2006.238.07:59:28.01#ibcon#wrote, iclass 33, count 2 2006.238.07:59:28.01#ibcon#about to read 3, iclass 33, count 2 2006.238.07:59:28.03#ibcon#read 3, iclass 33, count 2 2006.238.07:59:28.03#ibcon#about to read 4, iclass 33, count 2 2006.238.07:59:28.03#ibcon#read 4, iclass 33, count 2 2006.238.07:59:28.03#ibcon#about to read 5, iclass 33, count 2 2006.238.07:59:28.03#ibcon#read 5, iclass 33, count 2 2006.238.07:59:28.03#ibcon#about to read 6, iclass 33, count 2 2006.238.07:59:28.03#ibcon#read 6, iclass 33, count 2 2006.238.07:59:28.03#ibcon#end of sib2, iclass 33, count 2 2006.238.07:59:28.03#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:59:28.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:59:28.03#ibcon#[25=AT04-07\r\n] 2006.238.07:59:28.03#ibcon#*before write, iclass 33, count 2 2006.238.07:59:28.03#ibcon#enter sib2, iclass 33, count 2 2006.238.07:59:28.03#ibcon#flushed, iclass 33, count 2 2006.238.07:59:28.03#ibcon#about to write, iclass 33, count 2 2006.238.07:59:28.03#ibcon#wrote, iclass 33, count 2 2006.238.07:59:28.03#ibcon#about to read 3, iclass 33, count 2 2006.238.07:59:28.06#ibcon#read 3, iclass 33, count 2 2006.238.07:59:28.06#ibcon#about to read 4, iclass 33, count 2 2006.238.07:59:28.06#ibcon#read 4, iclass 33, count 2 2006.238.07:59:28.06#ibcon#about to read 5, iclass 33, count 2 2006.238.07:59:28.06#ibcon#read 5, iclass 33, count 2 2006.238.07:59:28.06#ibcon#about to read 6, iclass 33, count 2 2006.238.07:59:28.06#ibcon#read 6, iclass 33, count 2 2006.238.07:59:28.06#ibcon#end of sib2, iclass 33, count 2 2006.238.07:59:28.06#ibcon#*after write, iclass 33, count 2 2006.238.07:59:28.06#ibcon#*before return 0, iclass 33, count 2 2006.238.07:59:28.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:59:28.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:59:28.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:59:28.06#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:28.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:59:28.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:59:28.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:59:28.18#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:59:28.18#ibcon#first serial, iclass 33, count 0 2006.238.07:59:28.18#ibcon#enter sib2, iclass 33, count 0 2006.238.07:59:28.18#ibcon#flushed, iclass 33, count 0 2006.238.07:59:28.18#ibcon#about to write, iclass 33, count 0 2006.238.07:59:28.18#ibcon#wrote, iclass 33, count 0 2006.238.07:59:28.18#ibcon#about to read 3, iclass 33, count 0 2006.238.07:59:28.20#ibcon#read 3, iclass 33, count 0 2006.238.07:59:28.20#ibcon#about to read 4, iclass 33, count 0 2006.238.07:59:28.20#ibcon#read 4, iclass 33, count 0 2006.238.07:59:28.20#ibcon#about to read 5, iclass 33, count 0 2006.238.07:59:28.20#ibcon#read 5, iclass 33, count 0 2006.238.07:59:28.20#ibcon#about to read 6, iclass 33, count 0 2006.238.07:59:28.20#ibcon#read 6, iclass 33, count 0 2006.238.07:59:28.20#ibcon#end of sib2, iclass 33, count 0 2006.238.07:59:28.20#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:59:28.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:59:28.20#ibcon#[25=USB\r\n] 2006.238.07:59:28.20#ibcon#*before write, iclass 33, count 0 2006.238.07:59:28.20#ibcon#enter sib2, iclass 33, count 0 2006.238.07:59:28.20#ibcon#flushed, iclass 33, count 0 2006.238.07:59:28.20#ibcon#about to write, iclass 33, count 0 2006.238.07:59:28.20#ibcon#wrote, iclass 33, count 0 2006.238.07:59:28.20#ibcon#about to read 3, iclass 33, count 0 2006.238.07:59:28.23#ibcon#read 3, iclass 33, count 0 2006.238.07:59:28.23#ibcon#about to read 4, iclass 33, count 0 2006.238.07:59:28.23#ibcon#read 4, iclass 33, count 0 2006.238.07:59:28.23#ibcon#about to read 5, iclass 33, count 0 2006.238.07:59:28.23#ibcon#read 5, iclass 33, count 0 2006.238.07:59:28.23#ibcon#about to read 6, iclass 33, count 0 2006.238.07:59:28.23#ibcon#read 6, iclass 33, count 0 2006.238.07:59:28.23#ibcon#end of sib2, iclass 33, count 0 2006.238.07:59:28.23#ibcon#*after write, iclass 33, count 0 2006.238.07:59:28.23#ibcon#*before return 0, iclass 33, count 0 2006.238.07:59:28.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:59:28.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:59:28.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:59:28.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:59:28.23$vc4f8/valo=5,652.99 2006.238.07:59:28.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:59:28.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:59:28.23#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:28.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:59:28.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:59:28.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:59:28.23#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:59:28.23#ibcon#first serial, iclass 35, count 0 2006.238.07:59:28.23#ibcon#enter sib2, iclass 35, count 0 2006.238.07:59:28.23#ibcon#flushed, iclass 35, count 0 2006.238.07:59:28.23#ibcon#about to write, iclass 35, count 0 2006.238.07:59:28.23#ibcon#wrote, iclass 35, count 0 2006.238.07:59:28.23#ibcon#about to read 3, iclass 35, count 0 2006.238.07:59:28.25#ibcon#read 3, iclass 35, count 0 2006.238.07:59:28.25#ibcon#about to read 4, iclass 35, count 0 2006.238.07:59:28.25#ibcon#read 4, iclass 35, count 0 2006.238.07:59:28.25#ibcon#about to read 5, iclass 35, count 0 2006.238.07:59:28.25#ibcon#read 5, iclass 35, count 0 2006.238.07:59:28.25#ibcon#about to read 6, iclass 35, count 0 2006.238.07:59:28.25#ibcon#read 6, iclass 35, count 0 2006.238.07:59:28.25#ibcon#end of sib2, iclass 35, count 0 2006.238.07:59:28.25#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:59:28.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:59:28.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.07:59:28.25#ibcon#*before write, iclass 35, count 0 2006.238.07:59:28.25#ibcon#enter sib2, iclass 35, count 0 2006.238.07:59:28.25#ibcon#flushed, iclass 35, count 0 2006.238.07:59:28.25#ibcon#about to write, iclass 35, count 0 2006.238.07:59:28.25#ibcon#wrote, iclass 35, count 0 2006.238.07:59:28.25#ibcon#about to read 3, iclass 35, count 0 2006.238.07:59:28.29#ibcon#read 3, iclass 35, count 0 2006.238.07:59:28.29#ibcon#about to read 4, iclass 35, count 0 2006.238.07:59:28.29#ibcon#read 4, iclass 35, count 0 2006.238.07:59:28.29#ibcon#about to read 5, iclass 35, count 0 2006.238.07:59:28.29#ibcon#read 5, iclass 35, count 0 2006.238.07:59:28.29#ibcon#about to read 6, iclass 35, count 0 2006.238.07:59:28.29#ibcon#read 6, iclass 35, count 0 2006.238.07:59:28.29#ibcon#end of sib2, iclass 35, count 0 2006.238.07:59:28.29#ibcon#*after write, iclass 35, count 0 2006.238.07:59:28.29#ibcon#*before return 0, iclass 35, count 0 2006.238.07:59:28.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:59:28.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:59:28.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:59:28.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:59:28.29$vc4f8/va=5,8 2006.238.07:59:28.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.07:59:28.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.07:59:28.29#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:28.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:59:28.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:59:28.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:59:28.35#ibcon#enter wrdev, iclass 37, count 2 2006.238.07:59:28.35#ibcon#first serial, iclass 37, count 2 2006.238.07:59:28.35#ibcon#enter sib2, iclass 37, count 2 2006.238.07:59:28.35#ibcon#flushed, iclass 37, count 2 2006.238.07:59:28.35#ibcon#about to write, iclass 37, count 2 2006.238.07:59:28.35#ibcon#wrote, iclass 37, count 2 2006.238.07:59:28.35#ibcon#about to read 3, iclass 37, count 2 2006.238.07:59:28.37#ibcon#read 3, iclass 37, count 2 2006.238.07:59:28.37#ibcon#about to read 4, iclass 37, count 2 2006.238.07:59:28.37#ibcon#read 4, iclass 37, count 2 2006.238.07:59:28.37#ibcon#about to read 5, iclass 37, count 2 2006.238.07:59:28.37#ibcon#read 5, iclass 37, count 2 2006.238.07:59:28.37#ibcon#about to read 6, iclass 37, count 2 2006.238.07:59:28.37#ibcon#read 6, iclass 37, count 2 2006.238.07:59:28.37#ibcon#end of sib2, iclass 37, count 2 2006.238.07:59:28.37#ibcon#*mode == 0, iclass 37, count 2 2006.238.07:59:28.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.07:59:28.37#ibcon#[25=AT05-08\r\n] 2006.238.07:59:28.37#ibcon#*before write, iclass 37, count 2 2006.238.07:59:28.37#ibcon#enter sib2, iclass 37, count 2 2006.238.07:59:28.37#ibcon#flushed, iclass 37, count 2 2006.238.07:59:28.37#ibcon#about to write, iclass 37, count 2 2006.238.07:59:28.37#ibcon#wrote, iclass 37, count 2 2006.238.07:59:28.37#ibcon#about to read 3, iclass 37, count 2 2006.238.07:59:28.40#ibcon#read 3, iclass 37, count 2 2006.238.07:59:28.40#ibcon#about to read 4, iclass 37, count 2 2006.238.07:59:28.40#ibcon#read 4, iclass 37, count 2 2006.238.07:59:28.40#ibcon#about to read 5, iclass 37, count 2 2006.238.07:59:28.40#ibcon#read 5, iclass 37, count 2 2006.238.07:59:28.40#ibcon#about to read 6, iclass 37, count 2 2006.238.07:59:28.40#ibcon#read 6, iclass 37, count 2 2006.238.07:59:28.40#ibcon#end of sib2, iclass 37, count 2 2006.238.07:59:28.40#ibcon#*after write, iclass 37, count 2 2006.238.07:59:28.40#ibcon#*before return 0, iclass 37, count 2 2006.238.07:59:28.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:59:28.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:59:28.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.07:59:28.40#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:28.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:59:28.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:59:28.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:59:28.52#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:59:28.52#ibcon#first serial, iclass 37, count 0 2006.238.07:59:28.52#ibcon#enter sib2, iclass 37, count 0 2006.238.07:59:28.52#ibcon#flushed, iclass 37, count 0 2006.238.07:59:28.52#ibcon#about to write, iclass 37, count 0 2006.238.07:59:28.52#ibcon#wrote, iclass 37, count 0 2006.238.07:59:28.52#ibcon#about to read 3, iclass 37, count 0 2006.238.07:59:28.54#ibcon#read 3, iclass 37, count 0 2006.238.07:59:28.54#ibcon#about to read 4, iclass 37, count 0 2006.238.07:59:28.54#ibcon#read 4, iclass 37, count 0 2006.238.07:59:28.54#ibcon#about to read 5, iclass 37, count 0 2006.238.07:59:28.54#ibcon#read 5, iclass 37, count 0 2006.238.07:59:28.54#ibcon#about to read 6, iclass 37, count 0 2006.238.07:59:28.54#ibcon#read 6, iclass 37, count 0 2006.238.07:59:28.54#ibcon#end of sib2, iclass 37, count 0 2006.238.07:59:28.54#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:59:28.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:59:28.54#ibcon#[25=USB\r\n] 2006.238.07:59:28.54#ibcon#*before write, iclass 37, count 0 2006.238.07:59:28.54#ibcon#enter sib2, iclass 37, count 0 2006.238.07:59:28.54#ibcon#flushed, iclass 37, count 0 2006.238.07:59:28.54#ibcon#about to write, iclass 37, count 0 2006.238.07:59:28.54#ibcon#wrote, iclass 37, count 0 2006.238.07:59:28.54#ibcon#about to read 3, iclass 37, count 0 2006.238.07:59:28.57#ibcon#read 3, iclass 37, count 0 2006.238.07:59:28.57#ibcon#about to read 4, iclass 37, count 0 2006.238.07:59:28.57#ibcon#read 4, iclass 37, count 0 2006.238.07:59:28.57#ibcon#about to read 5, iclass 37, count 0 2006.238.07:59:28.57#ibcon#read 5, iclass 37, count 0 2006.238.07:59:28.57#ibcon#about to read 6, iclass 37, count 0 2006.238.07:59:28.57#ibcon#read 6, iclass 37, count 0 2006.238.07:59:28.57#ibcon#end of sib2, iclass 37, count 0 2006.238.07:59:28.57#ibcon#*after write, iclass 37, count 0 2006.238.07:59:28.57#ibcon#*before return 0, iclass 37, count 0 2006.238.07:59:28.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:59:28.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:59:28.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:59:28.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:59:28.57$vc4f8/valo=6,772.99 2006.238.07:59:28.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.07:59:28.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.07:59:28.57#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:28.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:59:28.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:59:28.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:59:28.57#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:59:28.57#ibcon#first serial, iclass 39, count 0 2006.238.07:59:28.57#ibcon#enter sib2, iclass 39, count 0 2006.238.07:59:28.57#ibcon#flushed, iclass 39, count 0 2006.238.07:59:28.57#ibcon#about to write, iclass 39, count 0 2006.238.07:59:28.57#ibcon#wrote, iclass 39, count 0 2006.238.07:59:28.57#ibcon#about to read 3, iclass 39, count 0 2006.238.07:59:28.59#ibcon#read 3, iclass 39, count 0 2006.238.07:59:28.59#ibcon#about to read 4, iclass 39, count 0 2006.238.07:59:28.59#ibcon#read 4, iclass 39, count 0 2006.238.07:59:28.59#ibcon#about to read 5, iclass 39, count 0 2006.238.07:59:28.59#ibcon#read 5, iclass 39, count 0 2006.238.07:59:28.59#ibcon#about to read 6, iclass 39, count 0 2006.238.07:59:28.59#ibcon#read 6, iclass 39, count 0 2006.238.07:59:28.59#ibcon#end of sib2, iclass 39, count 0 2006.238.07:59:28.59#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:59:28.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:59:28.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.07:59:28.59#ibcon#*before write, iclass 39, count 0 2006.238.07:59:28.59#ibcon#enter sib2, iclass 39, count 0 2006.238.07:59:28.59#ibcon#flushed, iclass 39, count 0 2006.238.07:59:28.59#ibcon#about to write, iclass 39, count 0 2006.238.07:59:28.59#ibcon#wrote, iclass 39, count 0 2006.238.07:59:28.59#ibcon#about to read 3, iclass 39, count 0 2006.238.07:59:28.63#ibcon#read 3, iclass 39, count 0 2006.238.07:59:28.63#ibcon#about to read 4, iclass 39, count 0 2006.238.07:59:28.63#ibcon#read 4, iclass 39, count 0 2006.238.07:59:28.63#ibcon#about to read 5, iclass 39, count 0 2006.238.07:59:28.63#ibcon#read 5, iclass 39, count 0 2006.238.07:59:28.63#ibcon#about to read 6, iclass 39, count 0 2006.238.07:59:28.63#ibcon#read 6, iclass 39, count 0 2006.238.07:59:28.63#ibcon#end of sib2, iclass 39, count 0 2006.238.07:59:28.63#ibcon#*after write, iclass 39, count 0 2006.238.07:59:28.63#ibcon#*before return 0, iclass 39, count 0 2006.238.07:59:28.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:59:28.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:59:28.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:59:28.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:59:28.63$vc4f8/va=6,7 2006.238.07:59:28.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.07:59:28.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.07:59:28.63#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:28.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:59:28.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:59:28.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:59:28.69#ibcon#enter wrdev, iclass 3, count 2 2006.238.07:59:28.69#ibcon#first serial, iclass 3, count 2 2006.238.07:59:28.69#ibcon#enter sib2, iclass 3, count 2 2006.238.07:59:28.69#ibcon#flushed, iclass 3, count 2 2006.238.07:59:28.69#ibcon#about to write, iclass 3, count 2 2006.238.07:59:28.69#ibcon#wrote, iclass 3, count 2 2006.238.07:59:28.69#ibcon#about to read 3, iclass 3, count 2 2006.238.07:59:28.71#ibcon#read 3, iclass 3, count 2 2006.238.07:59:28.71#ibcon#about to read 4, iclass 3, count 2 2006.238.07:59:28.71#ibcon#read 4, iclass 3, count 2 2006.238.07:59:28.71#ibcon#about to read 5, iclass 3, count 2 2006.238.07:59:28.71#ibcon#read 5, iclass 3, count 2 2006.238.07:59:28.71#ibcon#about to read 6, iclass 3, count 2 2006.238.07:59:28.71#ibcon#read 6, iclass 3, count 2 2006.238.07:59:28.71#ibcon#end of sib2, iclass 3, count 2 2006.238.07:59:28.71#ibcon#*mode == 0, iclass 3, count 2 2006.238.07:59:28.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.07:59:28.71#ibcon#[25=AT06-07\r\n] 2006.238.07:59:28.71#ibcon#*before write, iclass 3, count 2 2006.238.07:59:28.71#ibcon#enter sib2, iclass 3, count 2 2006.238.07:59:28.71#ibcon#flushed, iclass 3, count 2 2006.238.07:59:28.71#ibcon#about to write, iclass 3, count 2 2006.238.07:59:28.71#ibcon#wrote, iclass 3, count 2 2006.238.07:59:28.71#ibcon#about to read 3, iclass 3, count 2 2006.238.07:59:28.74#ibcon#read 3, iclass 3, count 2 2006.238.07:59:28.74#ibcon#about to read 4, iclass 3, count 2 2006.238.07:59:28.74#ibcon#read 4, iclass 3, count 2 2006.238.07:59:28.74#ibcon#about to read 5, iclass 3, count 2 2006.238.07:59:28.74#ibcon#read 5, iclass 3, count 2 2006.238.07:59:28.74#ibcon#about to read 6, iclass 3, count 2 2006.238.07:59:28.74#ibcon#read 6, iclass 3, count 2 2006.238.07:59:28.74#ibcon#end of sib2, iclass 3, count 2 2006.238.07:59:28.74#ibcon#*after write, iclass 3, count 2 2006.238.07:59:28.74#ibcon#*before return 0, iclass 3, count 2 2006.238.07:59:28.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:59:28.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.07:59:28.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.07:59:28.74#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:28.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:59:28.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:59:28.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:59:28.86#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:59:28.86#ibcon#first serial, iclass 3, count 0 2006.238.07:59:28.86#ibcon#enter sib2, iclass 3, count 0 2006.238.07:59:28.86#ibcon#flushed, iclass 3, count 0 2006.238.07:59:28.86#ibcon#about to write, iclass 3, count 0 2006.238.07:59:28.86#ibcon#wrote, iclass 3, count 0 2006.238.07:59:28.86#ibcon#about to read 3, iclass 3, count 0 2006.238.07:59:28.88#ibcon#read 3, iclass 3, count 0 2006.238.07:59:28.88#ibcon#about to read 4, iclass 3, count 0 2006.238.07:59:28.88#ibcon#read 4, iclass 3, count 0 2006.238.07:59:28.88#ibcon#about to read 5, iclass 3, count 0 2006.238.07:59:28.88#ibcon#read 5, iclass 3, count 0 2006.238.07:59:28.88#ibcon#about to read 6, iclass 3, count 0 2006.238.07:59:28.88#ibcon#read 6, iclass 3, count 0 2006.238.07:59:28.88#ibcon#end of sib2, iclass 3, count 0 2006.238.07:59:28.88#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:59:28.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:59:28.88#ibcon#[25=USB\r\n] 2006.238.07:59:28.88#ibcon#*before write, iclass 3, count 0 2006.238.07:59:28.88#ibcon#enter sib2, iclass 3, count 0 2006.238.07:59:28.88#ibcon#flushed, iclass 3, count 0 2006.238.07:59:28.88#ibcon#about to write, iclass 3, count 0 2006.238.07:59:28.88#ibcon#wrote, iclass 3, count 0 2006.238.07:59:28.88#ibcon#about to read 3, iclass 3, count 0 2006.238.07:59:28.91#ibcon#read 3, iclass 3, count 0 2006.238.07:59:28.91#ibcon#about to read 4, iclass 3, count 0 2006.238.07:59:28.91#ibcon#read 4, iclass 3, count 0 2006.238.07:59:28.91#ibcon#about to read 5, iclass 3, count 0 2006.238.07:59:28.91#ibcon#read 5, iclass 3, count 0 2006.238.07:59:28.91#ibcon#about to read 6, iclass 3, count 0 2006.238.07:59:28.91#ibcon#read 6, iclass 3, count 0 2006.238.07:59:28.91#ibcon#end of sib2, iclass 3, count 0 2006.238.07:59:28.91#ibcon#*after write, iclass 3, count 0 2006.238.07:59:28.91#ibcon#*before return 0, iclass 3, count 0 2006.238.07:59:28.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:59:28.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.07:59:28.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:59:28.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:59:28.91$vc4f8/valo=7,832.99 2006.238.07:59:28.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.07:59:28.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.07:59:28.91#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:28.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:59:28.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:59:28.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:59:28.91#ibcon#enter wrdev, iclass 5, count 0 2006.238.07:59:28.91#ibcon#first serial, iclass 5, count 0 2006.238.07:59:28.91#ibcon#enter sib2, iclass 5, count 0 2006.238.07:59:28.91#ibcon#flushed, iclass 5, count 0 2006.238.07:59:28.91#ibcon#about to write, iclass 5, count 0 2006.238.07:59:28.91#ibcon#wrote, iclass 5, count 0 2006.238.07:59:28.91#ibcon#about to read 3, iclass 5, count 0 2006.238.07:59:28.93#ibcon#read 3, iclass 5, count 0 2006.238.07:59:28.93#ibcon#about to read 4, iclass 5, count 0 2006.238.07:59:28.93#ibcon#read 4, iclass 5, count 0 2006.238.07:59:28.93#ibcon#about to read 5, iclass 5, count 0 2006.238.07:59:28.93#ibcon#read 5, iclass 5, count 0 2006.238.07:59:28.93#ibcon#about to read 6, iclass 5, count 0 2006.238.07:59:28.93#ibcon#read 6, iclass 5, count 0 2006.238.07:59:28.93#ibcon#end of sib2, iclass 5, count 0 2006.238.07:59:28.93#ibcon#*mode == 0, iclass 5, count 0 2006.238.07:59:28.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.07:59:28.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.07:59:28.93#ibcon#*before write, iclass 5, count 0 2006.238.07:59:28.93#ibcon#enter sib2, iclass 5, count 0 2006.238.07:59:28.93#ibcon#flushed, iclass 5, count 0 2006.238.07:59:28.93#ibcon#about to write, iclass 5, count 0 2006.238.07:59:28.93#ibcon#wrote, iclass 5, count 0 2006.238.07:59:28.93#ibcon#about to read 3, iclass 5, count 0 2006.238.07:59:28.97#ibcon#read 3, iclass 5, count 0 2006.238.07:59:28.97#ibcon#about to read 4, iclass 5, count 0 2006.238.07:59:28.97#ibcon#read 4, iclass 5, count 0 2006.238.07:59:28.97#ibcon#about to read 5, iclass 5, count 0 2006.238.07:59:28.97#ibcon#read 5, iclass 5, count 0 2006.238.07:59:28.97#ibcon#about to read 6, iclass 5, count 0 2006.238.07:59:28.97#ibcon#read 6, iclass 5, count 0 2006.238.07:59:28.97#ibcon#end of sib2, iclass 5, count 0 2006.238.07:59:28.97#ibcon#*after write, iclass 5, count 0 2006.238.07:59:28.97#ibcon#*before return 0, iclass 5, count 0 2006.238.07:59:28.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:59:28.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.07:59:28.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.07:59:28.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.07:59:28.97$vc4f8/va=7,7 2006.238.07:59:28.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.07:59:28.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.07:59:28.97#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:28.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:59:29.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:59:29.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:59:29.03#ibcon#enter wrdev, iclass 7, count 2 2006.238.07:59:29.03#ibcon#first serial, iclass 7, count 2 2006.238.07:59:29.03#ibcon#enter sib2, iclass 7, count 2 2006.238.07:59:29.03#ibcon#flushed, iclass 7, count 2 2006.238.07:59:29.03#ibcon#about to write, iclass 7, count 2 2006.238.07:59:29.03#ibcon#wrote, iclass 7, count 2 2006.238.07:59:29.03#ibcon#about to read 3, iclass 7, count 2 2006.238.07:59:29.05#ibcon#read 3, iclass 7, count 2 2006.238.07:59:29.05#ibcon#about to read 4, iclass 7, count 2 2006.238.07:59:29.05#ibcon#read 4, iclass 7, count 2 2006.238.07:59:29.05#ibcon#about to read 5, iclass 7, count 2 2006.238.07:59:29.05#ibcon#read 5, iclass 7, count 2 2006.238.07:59:29.05#ibcon#about to read 6, iclass 7, count 2 2006.238.07:59:29.05#ibcon#read 6, iclass 7, count 2 2006.238.07:59:29.05#ibcon#end of sib2, iclass 7, count 2 2006.238.07:59:29.05#ibcon#*mode == 0, iclass 7, count 2 2006.238.07:59:29.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.07:59:29.05#ibcon#[25=AT07-07\r\n] 2006.238.07:59:29.05#ibcon#*before write, iclass 7, count 2 2006.238.07:59:29.05#ibcon#enter sib2, iclass 7, count 2 2006.238.07:59:29.05#ibcon#flushed, iclass 7, count 2 2006.238.07:59:29.05#ibcon#about to write, iclass 7, count 2 2006.238.07:59:29.05#ibcon#wrote, iclass 7, count 2 2006.238.07:59:29.05#ibcon#about to read 3, iclass 7, count 2 2006.238.07:59:29.08#ibcon#read 3, iclass 7, count 2 2006.238.07:59:29.08#ibcon#about to read 4, iclass 7, count 2 2006.238.07:59:29.08#ibcon#read 4, iclass 7, count 2 2006.238.07:59:29.08#ibcon#about to read 5, iclass 7, count 2 2006.238.07:59:29.08#ibcon#read 5, iclass 7, count 2 2006.238.07:59:29.08#ibcon#about to read 6, iclass 7, count 2 2006.238.07:59:29.08#ibcon#read 6, iclass 7, count 2 2006.238.07:59:29.08#ibcon#end of sib2, iclass 7, count 2 2006.238.07:59:29.08#ibcon#*after write, iclass 7, count 2 2006.238.07:59:29.08#ibcon#*before return 0, iclass 7, count 2 2006.238.07:59:29.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:59:29.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.07:59:29.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.07:59:29.08#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:29.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:59:29.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:59:29.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:59:29.20#ibcon#enter wrdev, iclass 7, count 0 2006.238.07:59:29.20#ibcon#first serial, iclass 7, count 0 2006.238.07:59:29.20#ibcon#enter sib2, iclass 7, count 0 2006.238.07:59:29.20#ibcon#flushed, iclass 7, count 0 2006.238.07:59:29.20#ibcon#about to write, iclass 7, count 0 2006.238.07:59:29.20#ibcon#wrote, iclass 7, count 0 2006.238.07:59:29.20#ibcon#about to read 3, iclass 7, count 0 2006.238.07:59:29.22#ibcon#read 3, iclass 7, count 0 2006.238.07:59:29.22#ibcon#about to read 4, iclass 7, count 0 2006.238.07:59:29.22#ibcon#read 4, iclass 7, count 0 2006.238.07:59:29.22#ibcon#about to read 5, iclass 7, count 0 2006.238.07:59:29.22#ibcon#read 5, iclass 7, count 0 2006.238.07:59:29.22#ibcon#about to read 6, iclass 7, count 0 2006.238.07:59:29.22#ibcon#read 6, iclass 7, count 0 2006.238.07:59:29.22#ibcon#end of sib2, iclass 7, count 0 2006.238.07:59:29.22#ibcon#*mode == 0, iclass 7, count 0 2006.238.07:59:29.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.07:59:29.22#ibcon#[25=USB\r\n] 2006.238.07:59:29.22#ibcon#*before write, iclass 7, count 0 2006.238.07:59:29.22#ibcon#enter sib2, iclass 7, count 0 2006.238.07:59:29.22#ibcon#flushed, iclass 7, count 0 2006.238.07:59:29.22#ibcon#about to write, iclass 7, count 0 2006.238.07:59:29.22#ibcon#wrote, iclass 7, count 0 2006.238.07:59:29.22#ibcon#about to read 3, iclass 7, count 0 2006.238.07:59:29.25#ibcon#read 3, iclass 7, count 0 2006.238.07:59:29.25#ibcon#about to read 4, iclass 7, count 0 2006.238.07:59:29.25#ibcon#read 4, iclass 7, count 0 2006.238.07:59:29.25#ibcon#about to read 5, iclass 7, count 0 2006.238.07:59:29.25#ibcon#read 5, iclass 7, count 0 2006.238.07:59:29.25#ibcon#about to read 6, iclass 7, count 0 2006.238.07:59:29.25#ibcon#read 6, iclass 7, count 0 2006.238.07:59:29.25#ibcon#end of sib2, iclass 7, count 0 2006.238.07:59:29.25#ibcon#*after write, iclass 7, count 0 2006.238.07:59:29.25#ibcon#*before return 0, iclass 7, count 0 2006.238.07:59:29.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:59:29.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.07:59:29.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.07:59:29.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.07:59:29.25$vc4f8/valo=8,852.99 2006.238.07:59:29.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.07:59:29.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.07:59:29.25#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:29.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:59:29.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:59:29.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:59:29.25#ibcon#enter wrdev, iclass 11, count 0 2006.238.07:59:29.25#ibcon#first serial, iclass 11, count 0 2006.238.07:59:29.25#ibcon#enter sib2, iclass 11, count 0 2006.238.07:59:29.25#ibcon#flushed, iclass 11, count 0 2006.238.07:59:29.25#ibcon#about to write, iclass 11, count 0 2006.238.07:59:29.25#ibcon#wrote, iclass 11, count 0 2006.238.07:59:29.25#ibcon#about to read 3, iclass 11, count 0 2006.238.07:59:29.27#ibcon#read 3, iclass 11, count 0 2006.238.07:59:29.27#ibcon#about to read 4, iclass 11, count 0 2006.238.07:59:29.27#ibcon#read 4, iclass 11, count 0 2006.238.07:59:29.27#ibcon#about to read 5, iclass 11, count 0 2006.238.07:59:29.27#ibcon#read 5, iclass 11, count 0 2006.238.07:59:29.27#ibcon#about to read 6, iclass 11, count 0 2006.238.07:59:29.27#ibcon#read 6, iclass 11, count 0 2006.238.07:59:29.27#ibcon#end of sib2, iclass 11, count 0 2006.238.07:59:29.27#ibcon#*mode == 0, iclass 11, count 0 2006.238.07:59:29.27#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.07:59:29.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.07:59:29.27#ibcon#*before write, iclass 11, count 0 2006.238.07:59:29.27#ibcon#enter sib2, iclass 11, count 0 2006.238.07:59:29.27#ibcon#flushed, iclass 11, count 0 2006.238.07:59:29.27#ibcon#about to write, iclass 11, count 0 2006.238.07:59:29.27#ibcon#wrote, iclass 11, count 0 2006.238.07:59:29.27#ibcon#about to read 3, iclass 11, count 0 2006.238.07:59:29.31#ibcon#read 3, iclass 11, count 0 2006.238.07:59:29.31#ibcon#about to read 4, iclass 11, count 0 2006.238.07:59:29.31#ibcon#read 4, iclass 11, count 0 2006.238.07:59:29.31#ibcon#about to read 5, iclass 11, count 0 2006.238.07:59:29.31#ibcon#read 5, iclass 11, count 0 2006.238.07:59:29.31#ibcon#about to read 6, iclass 11, count 0 2006.238.07:59:29.31#ibcon#read 6, iclass 11, count 0 2006.238.07:59:29.31#ibcon#end of sib2, iclass 11, count 0 2006.238.07:59:29.31#ibcon#*after write, iclass 11, count 0 2006.238.07:59:29.31#ibcon#*before return 0, iclass 11, count 0 2006.238.07:59:29.31#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:59:29.31#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.07:59:29.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.07:59:29.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.07:59:29.31$vc4f8/va=8,7 2006.238.07:59:29.31#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.07:59:29.31#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.07:59:29.31#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:29.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:59:29.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:59:29.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:59:29.37#ibcon#enter wrdev, iclass 13, count 2 2006.238.07:59:29.37#ibcon#first serial, iclass 13, count 2 2006.238.07:59:29.37#ibcon#enter sib2, iclass 13, count 2 2006.238.07:59:29.37#ibcon#flushed, iclass 13, count 2 2006.238.07:59:29.37#ibcon#about to write, iclass 13, count 2 2006.238.07:59:29.37#ibcon#wrote, iclass 13, count 2 2006.238.07:59:29.37#ibcon#about to read 3, iclass 13, count 2 2006.238.07:59:29.39#ibcon#read 3, iclass 13, count 2 2006.238.07:59:29.39#ibcon#about to read 4, iclass 13, count 2 2006.238.07:59:29.39#ibcon#read 4, iclass 13, count 2 2006.238.07:59:29.39#ibcon#about to read 5, iclass 13, count 2 2006.238.07:59:29.39#ibcon#read 5, iclass 13, count 2 2006.238.07:59:29.39#ibcon#about to read 6, iclass 13, count 2 2006.238.07:59:29.39#ibcon#read 6, iclass 13, count 2 2006.238.07:59:29.39#ibcon#end of sib2, iclass 13, count 2 2006.238.07:59:29.39#ibcon#*mode == 0, iclass 13, count 2 2006.238.07:59:29.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.07:59:29.39#ibcon#[25=AT08-07\r\n] 2006.238.07:59:29.39#ibcon#*before write, iclass 13, count 2 2006.238.07:59:29.39#ibcon#enter sib2, iclass 13, count 2 2006.238.07:59:29.39#ibcon#flushed, iclass 13, count 2 2006.238.07:59:29.39#ibcon#about to write, iclass 13, count 2 2006.238.07:59:29.39#ibcon#wrote, iclass 13, count 2 2006.238.07:59:29.39#ibcon#about to read 3, iclass 13, count 2 2006.238.07:59:29.42#ibcon#read 3, iclass 13, count 2 2006.238.07:59:29.42#ibcon#about to read 4, iclass 13, count 2 2006.238.07:59:29.42#ibcon#read 4, iclass 13, count 2 2006.238.07:59:29.42#ibcon#about to read 5, iclass 13, count 2 2006.238.07:59:29.42#ibcon#read 5, iclass 13, count 2 2006.238.07:59:29.42#ibcon#about to read 6, iclass 13, count 2 2006.238.07:59:29.42#ibcon#read 6, iclass 13, count 2 2006.238.07:59:29.42#ibcon#end of sib2, iclass 13, count 2 2006.238.07:59:29.42#ibcon#*after write, iclass 13, count 2 2006.238.07:59:29.42#ibcon#*before return 0, iclass 13, count 2 2006.238.07:59:29.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:59:29.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.07:59:29.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.07:59:29.42#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:29.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:59:29.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:59:29.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:59:29.54#ibcon#enter wrdev, iclass 13, count 0 2006.238.07:59:29.54#ibcon#first serial, iclass 13, count 0 2006.238.07:59:29.54#ibcon#enter sib2, iclass 13, count 0 2006.238.07:59:29.54#ibcon#flushed, iclass 13, count 0 2006.238.07:59:29.54#ibcon#about to write, iclass 13, count 0 2006.238.07:59:29.54#ibcon#wrote, iclass 13, count 0 2006.238.07:59:29.54#ibcon#about to read 3, iclass 13, count 0 2006.238.07:59:29.56#ibcon#read 3, iclass 13, count 0 2006.238.07:59:29.56#ibcon#about to read 4, iclass 13, count 0 2006.238.07:59:29.56#ibcon#read 4, iclass 13, count 0 2006.238.07:59:29.56#ibcon#about to read 5, iclass 13, count 0 2006.238.07:59:29.56#ibcon#read 5, iclass 13, count 0 2006.238.07:59:29.56#ibcon#about to read 6, iclass 13, count 0 2006.238.07:59:29.56#ibcon#read 6, iclass 13, count 0 2006.238.07:59:29.56#ibcon#end of sib2, iclass 13, count 0 2006.238.07:59:29.56#ibcon#*mode == 0, iclass 13, count 0 2006.238.07:59:29.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.07:59:29.56#ibcon#[25=USB\r\n] 2006.238.07:59:29.56#ibcon#*before write, iclass 13, count 0 2006.238.07:59:29.56#ibcon#enter sib2, iclass 13, count 0 2006.238.07:59:29.56#ibcon#flushed, iclass 13, count 0 2006.238.07:59:29.56#ibcon#about to write, iclass 13, count 0 2006.238.07:59:29.56#ibcon#wrote, iclass 13, count 0 2006.238.07:59:29.56#ibcon#about to read 3, iclass 13, count 0 2006.238.07:59:29.59#ibcon#read 3, iclass 13, count 0 2006.238.07:59:29.59#ibcon#about to read 4, iclass 13, count 0 2006.238.07:59:29.59#ibcon#read 4, iclass 13, count 0 2006.238.07:59:29.59#ibcon#about to read 5, iclass 13, count 0 2006.238.07:59:29.59#ibcon#read 5, iclass 13, count 0 2006.238.07:59:29.59#ibcon#about to read 6, iclass 13, count 0 2006.238.07:59:29.59#ibcon#read 6, iclass 13, count 0 2006.238.07:59:29.59#ibcon#end of sib2, iclass 13, count 0 2006.238.07:59:29.59#ibcon#*after write, iclass 13, count 0 2006.238.07:59:29.59#ibcon#*before return 0, iclass 13, count 0 2006.238.07:59:29.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:59:29.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.07:59:29.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.07:59:29.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.07:59:29.59$vc4f8/vblo=1,632.99 2006.238.07:59:29.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.07:59:29.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.07:59:29.59#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:29.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:59:29.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:59:29.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:59:29.59#ibcon#enter wrdev, iclass 15, count 0 2006.238.07:59:29.59#ibcon#first serial, iclass 15, count 0 2006.238.07:59:29.59#ibcon#enter sib2, iclass 15, count 0 2006.238.07:59:29.59#ibcon#flushed, iclass 15, count 0 2006.238.07:59:29.59#ibcon#about to write, iclass 15, count 0 2006.238.07:59:29.59#ibcon#wrote, iclass 15, count 0 2006.238.07:59:29.59#ibcon#about to read 3, iclass 15, count 0 2006.238.07:59:29.61#ibcon#read 3, iclass 15, count 0 2006.238.07:59:29.61#ibcon#about to read 4, iclass 15, count 0 2006.238.07:59:29.61#ibcon#read 4, iclass 15, count 0 2006.238.07:59:29.61#ibcon#about to read 5, iclass 15, count 0 2006.238.07:59:29.61#ibcon#read 5, iclass 15, count 0 2006.238.07:59:29.61#ibcon#about to read 6, iclass 15, count 0 2006.238.07:59:29.61#ibcon#read 6, iclass 15, count 0 2006.238.07:59:29.61#ibcon#end of sib2, iclass 15, count 0 2006.238.07:59:29.61#ibcon#*mode == 0, iclass 15, count 0 2006.238.07:59:29.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.07:59:29.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.07:59:29.61#ibcon#*before write, iclass 15, count 0 2006.238.07:59:29.61#ibcon#enter sib2, iclass 15, count 0 2006.238.07:59:29.61#ibcon#flushed, iclass 15, count 0 2006.238.07:59:29.61#ibcon#about to write, iclass 15, count 0 2006.238.07:59:29.61#ibcon#wrote, iclass 15, count 0 2006.238.07:59:29.61#ibcon#about to read 3, iclass 15, count 0 2006.238.07:59:29.65#ibcon#read 3, iclass 15, count 0 2006.238.07:59:29.65#ibcon#about to read 4, iclass 15, count 0 2006.238.07:59:29.65#ibcon#read 4, iclass 15, count 0 2006.238.07:59:29.65#ibcon#about to read 5, iclass 15, count 0 2006.238.07:59:29.65#ibcon#read 5, iclass 15, count 0 2006.238.07:59:29.65#ibcon#about to read 6, iclass 15, count 0 2006.238.07:59:29.65#ibcon#read 6, iclass 15, count 0 2006.238.07:59:29.65#ibcon#end of sib2, iclass 15, count 0 2006.238.07:59:29.65#ibcon#*after write, iclass 15, count 0 2006.238.07:59:29.65#ibcon#*before return 0, iclass 15, count 0 2006.238.07:59:29.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:59:29.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.07:59:29.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.07:59:29.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.07:59:29.65$vc4f8/vb=1,4 2006.238.07:59:29.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.07:59:29.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.07:59:29.65#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:29.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:59:29.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:59:29.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:59:29.65#ibcon#enter wrdev, iclass 17, count 2 2006.238.07:59:29.65#ibcon#first serial, iclass 17, count 2 2006.238.07:59:29.65#ibcon#enter sib2, iclass 17, count 2 2006.238.07:59:29.65#ibcon#flushed, iclass 17, count 2 2006.238.07:59:29.65#ibcon#about to write, iclass 17, count 2 2006.238.07:59:29.65#ibcon#wrote, iclass 17, count 2 2006.238.07:59:29.65#ibcon#about to read 3, iclass 17, count 2 2006.238.07:59:29.67#ibcon#read 3, iclass 17, count 2 2006.238.07:59:29.67#ibcon#about to read 4, iclass 17, count 2 2006.238.07:59:29.67#ibcon#read 4, iclass 17, count 2 2006.238.07:59:29.67#ibcon#about to read 5, iclass 17, count 2 2006.238.07:59:29.67#ibcon#read 5, iclass 17, count 2 2006.238.07:59:29.67#ibcon#about to read 6, iclass 17, count 2 2006.238.07:59:29.67#ibcon#read 6, iclass 17, count 2 2006.238.07:59:29.67#ibcon#end of sib2, iclass 17, count 2 2006.238.07:59:29.67#ibcon#*mode == 0, iclass 17, count 2 2006.238.07:59:29.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.07:59:29.67#ibcon#[27=AT01-04\r\n] 2006.238.07:59:29.67#ibcon#*before write, iclass 17, count 2 2006.238.07:59:29.67#ibcon#enter sib2, iclass 17, count 2 2006.238.07:59:29.67#ibcon#flushed, iclass 17, count 2 2006.238.07:59:29.67#ibcon#about to write, iclass 17, count 2 2006.238.07:59:29.67#ibcon#wrote, iclass 17, count 2 2006.238.07:59:29.67#ibcon#about to read 3, iclass 17, count 2 2006.238.07:59:29.70#ibcon#read 3, iclass 17, count 2 2006.238.07:59:29.70#ibcon#about to read 4, iclass 17, count 2 2006.238.07:59:29.70#ibcon#read 4, iclass 17, count 2 2006.238.07:59:29.70#ibcon#about to read 5, iclass 17, count 2 2006.238.07:59:29.70#ibcon#read 5, iclass 17, count 2 2006.238.07:59:29.70#ibcon#about to read 6, iclass 17, count 2 2006.238.07:59:29.70#ibcon#read 6, iclass 17, count 2 2006.238.07:59:29.70#ibcon#end of sib2, iclass 17, count 2 2006.238.07:59:29.70#ibcon#*after write, iclass 17, count 2 2006.238.07:59:29.70#ibcon#*before return 0, iclass 17, count 2 2006.238.07:59:29.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:59:29.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.07:59:29.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.07:59:29.70#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:29.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:59:29.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:59:29.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:59:29.82#ibcon#enter wrdev, iclass 17, count 0 2006.238.07:59:29.82#ibcon#first serial, iclass 17, count 0 2006.238.07:59:29.82#ibcon#enter sib2, iclass 17, count 0 2006.238.07:59:29.82#ibcon#flushed, iclass 17, count 0 2006.238.07:59:29.82#ibcon#about to write, iclass 17, count 0 2006.238.07:59:29.82#ibcon#wrote, iclass 17, count 0 2006.238.07:59:29.82#ibcon#about to read 3, iclass 17, count 0 2006.238.07:59:29.84#ibcon#read 3, iclass 17, count 0 2006.238.07:59:29.84#ibcon#about to read 4, iclass 17, count 0 2006.238.07:59:29.84#ibcon#read 4, iclass 17, count 0 2006.238.07:59:29.84#ibcon#about to read 5, iclass 17, count 0 2006.238.07:59:29.84#ibcon#read 5, iclass 17, count 0 2006.238.07:59:29.84#ibcon#about to read 6, iclass 17, count 0 2006.238.07:59:29.84#ibcon#read 6, iclass 17, count 0 2006.238.07:59:29.84#ibcon#end of sib2, iclass 17, count 0 2006.238.07:59:29.84#ibcon#*mode == 0, iclass 17, count 0 2006.238.07:59:29.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.07:59:29.84#ibcon#[27=USB\r\n] 2006.238.07:59:29.84#ibcon#*before write, iclass 17, count 0 2006.238.07:59:29.84#ibcon#enter sib2, iclass 17, count 0 2006.238.07:59:29.84#ibcon#flushed, iclass 17, count 0 2006.238.07:59:29.84#ibcon#about to write, iclass 17, count 0 2006.238.07:59:29.84#ibcon#wrote, iclass 17, count 0 2006.238.07:59:29.84#ibcon#about to read 3, iclass 17, count 0 2006.238.07:59:29.87#ibcon#read 3, iclass 17, count 0 2006.238.07:59:29.87#ibcon#about to read 4, iclass 17, count 0 2006.238.07:59:29.87#ibcon#read 4, iclass 17, count 0 2006.238.07:59:29.87#ibcon#about to read 5, iclass 17, count 0 2006.238.07:59:29.87#ibcon#read 5, iclass 17, count 0 2006.238.07:59:29.87#ibcon#about to read 6, iclass 17, count 0 2006.238.07:59:29.87#ibcon#read 6, iclass 17, count 0 2006.238.07:59:29.87#ibcon#end of sib2, iclass 17, count 0 2006.238.07:59:29.87#ibcon#*after write, iclass 17, count 0 2006.238.07:59:29.87#ibcon#*before return 0, iclass 17, count 0 2006.238.07:59:29.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:59:29.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.07:59:29.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.07:59:29.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.07:59:29.87$vc4f8/vblo=2,640.99 2006.238.07:59:29.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.07:59:29.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.07:59:29.87#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:29.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:59:29.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:59:29.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:59:29.87#ibcon#enter wrdev, iclass 19, count 0 2006.238.07:59:29.87#ibcon#first serial, iclass 19, count 0 2006.238.07:59:29.87#ibcon#enter sib2, iclass 19, count 0 2006.238.07:59:29.87#ibcon#flushed, iclass 19, count 0 2006.238.07:59:29.87#ibcon#about to write, iclass 19, count 0 2006.238.07:59:29.87#ibcon#wrote, iclass 19, count 0 2006.238.07:59:29.87#ibcon#about to read 3, iclass 19, count 0 2006.238.07:59:29.89#ibcon#read 3, iclass 19, count 0 2006.238.07:59:29.89#ibcon#about to read 4, iclass 19, count 0 2006.238.07:59:29.89#ibcon#read 4, iclass 19, count 0 2006.238.07:59:29.89#ibcon#about to read 5, iclass 19, count 0 2006.238.07:59:29.89#ibcon#read 5, iclass 19, count 0 2006.238.07:59:29.89#ibcon#about to read 6, iclass 19, count 0 2006.238.07:59:29.89#ibcon#read 6, iclass 19, count 0 2006.238.07:59:29.89#ibcon#end of sib2, iclass 19, count 0 2006.238.07:59:29.89#ibcon#*mode == 0, iclass 19, count 0 2006.238.07:59:29.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.07:59:29.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.07:59:29.89#ibcon#*before write, iclass 19, count 0 2006.238.07:59:29.89#ibcon#enter sib2, iclass 19, count 0 2006.238.07:59:29.89#ibcon#flushed, iclass 19, count 0 2006.238.07:59:29.89#ibcon#about to write, iclass 19, count 0 2006.238.07:59:29.89#ibcon#wrote, iclass 19, count 0 2006.238.07:59:29.89#ibcon#about to read 3, iclass 19, count 0 2006.238.07:59:29.93#ibcon#read 3, iclass 19, count 0 2006.238.07:59:29.93#ibcon#about to read 4, iclass 19, count 0 2006.238.07:59:29.93#ibcon#read 4, iclass 19, count 0 2006.238.07:59:29.93#ibcon#about to read 5, iclass 19, count 0 2006.238.07:59:29.93#ibcon#read 5, iclass 19, count 0 2006.238.07:59:29.93#ibcon#about to read 6, iclass 19, count 0 2006.238.07:59:29.93#ibcon#read 6, iclass 19, count 0 2006.238.07:59:29.93#ibcon#end of sib2, iclass 19, count 0 2006.238.07:59:29.93#ibcon#*after write, iclass 19, count 0 2006.238.07:59:29.93#ibcon#*before return 0, iclass 19, count 0 2006.238.07:59:29.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:59:29.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.07:59:29.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.07:59:29.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.07:59:29.93$vc4f8/vb=2,4 2006.238.07:59:29.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.07:59:29.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.07:59:29.93#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:29.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:59:29.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:59:29.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:59:29.99#ibcon#enter wrdev, iclass 21, count 2 2006.238.07:59:29.99#ibcon#first serial, iclass 21, count 2 2006.238.07:59:29.99#ibcon#enter sib2, iclass 21, count 2 2006.238.07:59:29.99#ibcon#flushed, iclass 21, count 2 2006.238.07:59:29.99#ibcon#about to write, iclass 21, count 2 2006.238.07:59:29.99#ibcon#wrote, iclass 21, count 2 2006.238.07:59:29.99#ibcon#about to read 3, iclass 21, count 2 2006.238.07:59:30.01#ibcon#read 3, iclass 21, count 2 2006.238.07:59:30.01#ibcon#about to read 4, iclass 21, count 2 2006.238.07:59:30.01#ibcon#read 4, iclass 21, count 2 2006.238.07:59:30.01#ibcon#about to read 5, iclass 21, count 2 2006.238.07:59:30.01#ibcon#read 5, iclass 21, count 2 2006.238.07:59:30.02#ibcon#about to read 6, iclass 21, count 2 2006.238.07:59:30.02#ibcon#read 6, iclass 21, count 2 2006.238.07:59:30.02#ibcon#end of sib2, iclass 21, count 2 2006.238.07:59:30.02#ibcon#*mode == 0, iclass 21, count 2 2006.238.07:59:30.02#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.07:59:30.02#ibcon#[27=AT02-04\r\n] 2006.238.07:59:30.02#ibcon#*before write, iclass 21, count 2 2006.238.07:59:30.02#ibcon#enter sib2, iclass 21, count 2 2006.238.07:59:30.02#ibcon#flushed, iclass 21, count 2 2006.238.07:59:30.02#ibcon#about to write, iclass 21, count 2 2006.238.07:59:30.02#ibcon#wrote, iclass 21, count 2 2006.238.07:59:30.02#ibcon#about to read 3, iclass 21, count 2 2006.238.07:59:30.05#ibcon#read 3, iclass 21, count 2 2006.238.07:59:30.05#ibcon#about to read 4, iclass 21, count 2 2006.238.07:59:30.05#ibcon#read 4, iclass 21, count 2 2006.238.07:59:30.05#ibcon#about to read 5, iclass 21, count 2 2006.238.07:59:30.05#ibcon#read 5, iclass 21, count 2 2006.238.07:59:30.05#ibcon#about to read 6, iclass 21, count 2 2006.238.07:59:30.05#ibcon#read 6, iclass 21, count 2 2006.238.07:59:30.05#ibcon#end of sib2, iclass 21, count 2 2006.238.07:59:30.05#ibcon#*after write, iclass 21, count 2 2006.238.07:59:30.05#ibcon#*before return 0, iclass 21, count 2 2006.238.07:59:30.05#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:59:30.05#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.07:59:30.05#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.07:59:30.05#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:30.05#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:59:30.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:59:30.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:59:30.16#ibcon#enter wrdev, iclass 21, count 0 2006.238.07:59:30.16#ibcon#first serial, iclass 21, count 0 2006.238.07:59:30.16#ibcon#enter sib2, iclass 21, count 0 2006.238.07:59:30.16#ibcon#flushed, iclass 21, count 0 2006.238.07:59:30.16#ibcon#about to write, iclass 21, count 0 2006.238.07:59:30.16#ibcon#wrote, iclass 21, count 0 2006.238.07:59:30.16#ibcon#about to read 3, iclass 21, count 0 2006.238.07:59:30.18#ibcon#read 3, iclass 21, count 0 2006.238.07:59:30.18#ibcon#about to read 4, iclass 21, count 0 2006.238.07:59:30.18#ibcon#read 4, iclass 21, count 0 2006.238.07:59:30.18#ibcon#about to read 5, iclass 21, count 0 2006.238.07:59:30.18#ibcon#read 5, iclass 21, count 0 2006.238.07:59:30.18#ibcon#about to read 6, iclass 21, count 0 2006.238.07:59:30.18#ibcon#read 6, iclass 21, count 0 2006.238.07:59:30.18#ibcon#end of sib2, iclass 21, count 0 2006.238.07:59:30.18#ibcon#*mode == 0, iclass 21, count 0 2006.238.07:59:30.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.07:59:30.18#ibcon#[27=USB\r\n] 2006.238.07:59:30.18#ibcon#*before write, iclass 21, count 0 2006.238.07:59:30.18#ibcon#enter sib2, iclass 21, count 0 2006.238.07:59:30.18#ibcon#flushed, iclass 21, count 0 2006.238.07:59:30.18#ibcon#about to write, iclass 21, count 0 2006.238.07:59:30.18#ibcon#wrote, iclass 21, count 0 2006.238.07:59:30.18#ibcon#about to read 3, iclass 21, count 0 2006.238.07:59:30.21#ibcon#read 3, iclass 21, count 0 2006.238.07:59:30.21#ibcon#about to read 4, iclass 21, count 0 2006.238.07:59:30.21#ibcon#read 4, iclass 21, count 0 2006.238.07:59:30.21#ibcon#about to read 5, iclass 21, count 0 2006.238.07:59:30.21#ibcon#read 5, iclass 21, count 0 2006.238.07:59:30.21#ibcon#about to read 6, iclass 21, count 0 2006.238.07:59:30.21#ibcon#read 6, iclass 21, count 0 2006.238.07:59:30.21#ibcon#end of sib2, iclass 21, count 0 2006.238.07:59:30.21#ibcon#*after write, iclass 21, count 0 2006.238.07:59:30.21#ibcon#*before return 0, iclass 21, count 0 2006.238.07:59:30.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:59:30.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.07:59:30.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.07:59:30.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.07:59:30.21$vc4f8/vblo=3,656.99 2006.238.07:59:30.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.07:59:30.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.07:59:30.21#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:30.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:59:30.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:59:30.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:59:30.21#ibcon#enter wrdev, iclass 23, count 0 2006.238.07:59:30.21#ibcon#first serial, iclass 23, count 0 2006.238.07:59:30.21#ibcon#enter sib2, iclass 23, count 0 2006.238.07:59:30.21#ibcon#flushed, iclass 23, count 0 2006.238.07:59:30.21#ibcon#about to write, iclass 23, count 0 2006.238.07:59:30.21#ibcon#wrote, iclass 23, count 0 2006.238.07:59:30.21#ibcon#about to read 3, iclass 23, count 0 2006.238.07:59:30.23#ibcon#read 3, iclass 23, count 0 2006.238.07:59:30.23#ibcon#about to read 4, iclass 23, count 0 2006.238.07:59:30.23#ibcon#read 4, iclass 23, count 0 2006.238.07:59:30.23#ibcon#about to read 5, iclass 23, count 0 2006.238.07:59:30.23#ibcon#read 5, iclass 23, count 0 2006.238.07:59:30.23#ibcon#about to read 6, iclass 23, count 0 2006.238.07:59:30.23#ibcon#read 6, iclass 23, count 0 2006.238.07:59:30.23#ibcon#end of sib2, iclass 23, count 0 2006.238.07:59:30.23#ibcon#*mode == 0, iclass 23, count 0 2006.238.07:59:30.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.07:59:30.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.07:59:30.23#ibcon#*before write, iclass 23, count 0 2006.238.07:59:30.23#ibcon#enter sib2, iclass 23, count 0 2006.238.07:59:30.23#ibcon#flushed, iclass 23, count 0 2006.238.07:59:30.23#ibcon#about to write, iclass 23, count 0 2006.238.07:59:30.23#ibcon#wrote, iclass 23, count 0 2006.238.07:59:30.23#ibcon#about to read 3, iclass 23, count 0 2006.238.07:59:30.27#ibcon#read 3, iclass 23, count 0 2006.238.07:59:30.27#ibcon#about to read 4, iclass 23, count 0 2006.238.07:59:30.27#ibcon#read 4, iclass 23, count 0 2006.238.07:59:30.27#ibcon#about to read 5, iclass 23, count 0 2006.238.07:59:30.27#ibcon#read 5, iclass 23, count 0 2006.238.07:59:30.27#ibcon#about to read 6, iclass 23, count 0 2006.238.07:59:30.27#ibcon#read 6, iclass 23, count 0 2006.238.07:59:30.27#ibcon#end of sib2, iclass 23, count 0 2006.238.07:59:30.27#ibcon#*after write, iclass 23, count 0 2006.238.07:59:30.27#ibcon#*before return 0, iclass 23, count 0 2006.238.07:59:30.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:59:30.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.07:59:30.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.07:59:30.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.07:59:30.27$vc4f8/vb=3,4 2006.238.07:59:30.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.07:59:30.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.07:59:30.27#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:30.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:59:30.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:59:30.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:59:30.33#ibcon#enter wrdev, iclass 25, count 2 2006.238.07:59:30.33#ibcon#first serial, iclass 25, count 2 2006.238.07:59:30.33#ibcon#enter sib2, iclass 25, count 2 2006.238.07:59:30.33#ibcon#flushed, iclass 25, count 2 2006.238.07:59:30.33#ibcon#about to write, iclass 25, count 2 2006.238.07:59:30.33#ibcon#wrote, iclass 25, count 2 2006.238.07:59:30.33#ibcon#about to read 3, iclass 25, count 2 2006.238.07:59:30.35#ibcon#read 3, iclass 25, count 2 2006.238.07:59:30.35#ibcon#about to read 4, iclass 25, count 2 2006.238.07:59:30.35#ibcon#read 4, iclass 25, count 2 2006.238.07:59:30.35#ibcon#about to read 5, iclass 25, count 2 2006.238.07:59:30.35#ibcon#read 5, iclass 25, count 2 2006.238.07:59:30.35#ibcon#about to read 6, iclass 25, count 2 2006.238.07:59:30.35#ibcon#read 6, iclass 25, count 2 2006.238.07:59:30.35#ibcon#end of sib2, iclass 25, count 2 2006.238.07:59:30.35#ibcon#*mode == 0, iclass 25, count 2 2006.238.07:59:30.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.07:59:30.35#ibcon#[27=AT03-04\r\n] 2006.238.07:59:30.35#ibcon#*before write, iclass 25, count 2 2006.238.07:59:30.35#ibcon#enter sib2, iclass 25, count 2 2006.238.07:59:30.35#ibcon#flushed, iclass 25, count 2 2006.238.07:59:30.35#ibcon#about to write, iclass 25, count 2 2006.238.07:59:30.35#ibcon#wrote, iclass 25, count 2 2006.238.07:59:30.35#ibcon#about to read 3, iclass 25, count 2 2006.238.07:59:30.38#ibcon#read 3, iclass 25, count 2 2006.238.07:59:30.38#ibcon#about to read 4, iclass 25, count 2 2006.238.07:59:30.38#ibcon#read 4, iclass 25, count 2 2006.238.07:59:30.38#ibcon#about to read 5, iclass 25, count 2 2006.238.07:59:30.38#ibcon#read 5, iclass 25, count 2 2006.238.07:59:30.38#ibcon#about to read 6, iclass 25, count 2 2006.238.07:59:30.38#ibcon#read 6, iclass 25, count 2 2006.238.07:59:30.38#ibcon#end of sib2, iclass 25, count 2 2006.238.07:59:30.38#ibcon#*after write, iclass 25, count 2 2006.238.07:59:30.38#ibcon#*before return 0, iclass 25, count 2 2006.238.07:59:30.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:59:30.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.07:59:30.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.07:59:30.38#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:30.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:59:30.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:59:30.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:59:30.50#ibcon#enter wrdev, iclass 25, count 0 2006.238.07:59:30.50#ibcon#first serial, iclass 25, count 0 2006.238.07:59:30.50#ibcon#enter sib2, iclass 25, count 0 2006.238.07:59:30.50#ibcon#flushed, iclass 25, count 0 2006.238.07:59:30.50#ibcon#about to write, iclass 25, count 0 2006.238.07:59:30.50#ibcon#wrote, iclass 25, count 0 2006.238.07:59:30.50#ibcon#about to read 3, iclass 25, count 0 2006.238.07:59:30.52#ibcon#read 3, iclass 25, count 0 2006.238.07:59:30.52#ibcon#about to read 4, iclass 25, count 0 2006.238.07:59:30.52#ibcon#read 4, iclass 25, count 0 2006.238.07:59:30.52#ibcon#about to read 5, iclass 25, count 0 2006.238.07:59:30.52#ibcon#read 5, iclass 25, count 0 2006.238.07:59:30.52#ibcon#about to read 6, iclass 25, count 0 2006.238.07:59:30.52#ibcon#read 6, iclass 25, count 0 2006.238.07:59:30.52#ibcon#end of sib2, iclass 25, count 0 2006.238.07:59:30.52#ibcon#*mode == 0, iclass 25, count 0 2006.238.07:59:30.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.07:59:30.52#ibcon#[27=USB\r\n] 2006.238.07:59:30.52#ibcon#*before write, iclass 25, count 0 2006.238.07:59:30.52#ibcon#enter sib2, iclass 25, count 0 2006.238.07:59:30.52#ibcon#flushed, iclass 25, count 0 2006.238.07:59:30.52#ibcon#about to write, iclass 25, count 0 2006.238.07:59:30.52#ibcon#wrote, iclass 25, count 0 2006.238.07:59:30.52#ibcon#about to read 3, iclass 25, count 0 2006.238.07:59:30.55#ibcon#read 3, iclass 25, count 0 2006.238.07:59:30.55#ibcon#about to read 4, iclass 25, count 0 2006.238.07:59:30.55#ibcon#read 4, iclass 25, count 0 2006.238.07:59:30.55#ibcon#about to read 5, iclass 25, count 0 2006.238.07:59:30.55#ibcon#read 5, iclass 25, count 0 2006.238.07:59:30.55#ibcon#about to read 6, iclass 25, count 0 2006.238.07:59:30.55#ibcon#read 6, iclass 25, count 0 2006.238.07:59:30.55#ibcon#end of sib2, iclass 25, count 0 2006.238.07:59:30.55#ibcon#*after write, iclass 25, count 0 2006.238.07:59:30.55#ibcon#*before return 0, iclass 25, count 0 2006.238.07:59:30.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:59:30.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.07:59:30.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.07:59:30.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.07:59:30.55$vc4f8/vblo=4,712.99 2006.238.07:59:30.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.07:59:30.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.07:59:30.55#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:30.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:59:30.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:59:30.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:59:30.55#ibcon#enter wrdev, iclass 27, count 0 2006.238.07:59:30.55#ibcon#first serial, iclass 27, count 0 2006.238.07:59:30.55#ibcon#enter sib2, iclass 27, count 0 2006.238.07:59:30.55#ibcon#flushed, iclass 27, count 0 2006.238.07:59:30.55#ibcon#about to write, iclass 27, count 0 2006.238.07:59:30.55#ibcon#wrote, iclass 27, count 0 2006.238.07:59:30.55#ibcon#about to read 3, iclass 27, count 0 2006.238.07:59:30.57#ibcon#read 3, iclass 27, count 0 2006.238.07:59:30.57#ibcon#about to read 4, iclass 27, count 0 2006.238.07:59:30.57#ibcon#read 4, iclass 27, count 0 2006.238.07:59:30.57#ibcon#about to read 5, iclass 27, count 0 2006.238.07:59:30.57#ibcon#read 5, iclass 27, count 0 2006.238.07:59:30.57#ibcon#about to read 6, iclass 27, count 0 2006.238.07:59:30.57#ibcon#read 6, iclass 27, count 0 2006.238.07:59:30.57#ibcon#end of sib2, iclass 27, count 0 2006.238.07:59:30.57#ibcon#*mode == 0, iclass 27, count 0 2006.238.07:59:30.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.07:59:30.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.07:59:30.57#ibcon#*before write, iclass 27, count 0 2006.238.07:59:30.57#ibcon#enter sib2, iclass 27, count 0 2006.238.07:59:30.57#ibcon#flushed, iclass 27, count 0 2006.238.07:59:30.57#ibcon#about to write, iclass 27, count 0 2006.238.07:59:30.57#ibcon#wrote, iclass 27, count 0 2006.238.07:59:30.57#ibcon#about to read 3, iclass 27, count 0 2006.238.07:59:30.61#ibcon#read 3, iclass 27, count 0 2006.238.07:59:30.61#ibcon#about to read 4, iclass 27, count 0 2006.238.07:59:30.61#ibcon#read 4, iclass 27, count 0 2006.238.07:59:30.61#ibcon#about to read 5, iclass 27, count 0 2006.238.07:59:30.61#ibcon#read 5, iclass 27, count 0 2006.238.07:59:30.61#ibcon#about to read 6, iclass 27, count 0 2006.238.07:59:30.61#ibcon#read 6, iclass 27, count 0 2006.238.07:59:30.61#ibcon#end of sib2, iclass 27, count 0 2006.238.07:59:30.61#ibcon#*after write, iclass 27, count 0 2006.238.07:59:30.61#ibcon#*before return 0, iclass 27, count 0 2006.238.07:59:30.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:59:30.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.07:59:30.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.07:59:30.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.07:59:30.61$vc4f8/vb=4,4 2006.238.07:59:30.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.07:59:30.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.07:59:30.61#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:30.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:59:30.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:59:30.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:59:30.67#ibcon#enter wrdev, iclass 29, count 2 2006.238.07:59:30.67#ibcon#first serial, iclass 29, count 2 2006.238.07:59:30.67#ibcon#enter sib2, iclass 29, count 2 2006.238.07:59:30.67#ibcon#flushed, iclass 29, count 2 2006.238.07:59:30.67#ibcon#about to write, iclass 29, count 2 2006.238.07:59:30.67#ibcon#wrote, iclass 29, count 2 2006.238.07:59:30.67#ibcon#about to read 3, iclass 29, count 2 2006.238.07:59:30.69#ibcon#read 3, iclass 29, count 2 2006.238.07:59:30.69#ibcon#about to read 4, iclass 29, count 2 2006.238.07:59:30.69#ibcon#read 4, iclass 29, count 2 2006.238.07:59:30.69#ibcon#about to read 5, iclass 29, count 2 2006.238.07:59:30.69#ibcon#read 5, iclass 29, count 2 2006.238.07:59:30.69#ibcon#about to read 6, iclass 29, count 2 2006.238.07:59:30.69#ibcon#read 6, iclass 29, count 2 2006.238.07:59:30.69#ibcon#end of sib2, iclass 29, count 2 2006.238.07:59:30.69#ibcon#*mode == 0, iclass 29, count 2 2006.238.07:59:30.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.07:59:30.69#ibcon#[27=AT04-04\r\n] 2006.238.07:59:30.69#ibcon#*before write, iclass 29, count 2 2006.238.07:59:30.69#ibcon#enter sib2, iclass 29, count 2 2006.238.07:59:30.69#ibcon#flushed, iclass 29, count 2 2006.238.07:59:30.69#ibcon#about to write, iclass 29, count 2 2006.238.07:59:30.69#ibcon#wrote, iclass 29, count 2 2006.238.07:59:30.69#ibcon#about to read 3, iclass 29, count 2 2006.238.07:59:30.72#ibcon#read 3, iclass 29, count 2 2006.238.07:59:30.72#ibcon#about to read 4, iclass 29, count 2 2006.238.07:59:30.72#ibcon#read 4, iclass 29, count 2 2006.238.07:59:30.72#ibcon#about to read 5, iclass 29, count 2 2006.238.07:59:30.72#ibcon#read 5, iclass 29, count 2 2006.238.07:59:30.72#ibcon#about to read 6, iclass 29, count 2 2006.238.07:59:30.72#ibcon#read 6, iclass 29, count 2 2006.238.07:59:30.72#ibcon#end of sib2, iclass 29, count 2 2006.238.07:59:30.72#ibcon#*after write, iclass 29, count 2 2006.238.07:59:30.72#ibcon#*before return 0, iclass 29, count 2 2006.238.07:59:30.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:59:30.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.07:59:30.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.07:59:30.72#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:30.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:59:30.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:59:30.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:59:30.84#ibcon#enter wrdev, iclass 29, count 0 2006.238.07:59:30.84#ibcon#first serial, iclass 29, count 0 2006.238.07:59:30.84#ibcon#enter sib2, iclass 29, count 0 2006.238.07:59:30.84#ibcon#flushed, iclass 29, count 0 2006.238.07:59:30.84#ibcon#about to write, iclass 29, count 0 2006.238.07:59:30.84#ibcon#wrote, iclass 29, count 0 2006.238.07:59:30.84#ibcon#about to read 3, iclass 29, count 0 2006.238.07:59:30.86#ibcon#read 3, iclass 29, count 0 2006.238.07:59:30.86#ibcon#about to read 4, iclass 29, count 0 2006.238.07:59:30.86#ibcon#read 4, iclass 29, count 0 2006.238.07:59:30.86#ibcon#about to read 5, iclass 29, count 0 2006.238.07:59:30.86#ibcon#read 5, iclass 29, count 0 2006.238.07:59:30.86#ibcon#about to read 6, iclass 29, count 0 2006.238.07:59:30.86#ibcon#read 6, iclass 29, count 0 2006.238.07:59:30.86#ibcon#end of sib2, iclass 29, count 0 2006.238.07:59:30.86#ibcon#*mode == 0, iclass 29, count 0 2006.238.07:59:30.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.07:59:30.86#ibcon#[27=USB\r\n] 2006.238.07:59:30.86#ibcon#*before write, iclass 29, count 0 2006.238.07:59:30.86#ibcon#enter sib2, iclass 29, count 0 2006.238.07:59:30.86#ibcon#flushed, iclass 29, count 0 2006.238.07:59:30.86#ibcon#about to write, iclass 29, count 0 2006.238.07:59:30.86#ibcon#wrote, iclass 29, count 0 2006.238.07:59:30.86#ibcon#about to read 3, iclass 29, count 0 2006.238.07:59:30.89#ibcon#read 3, iclass 29, count 0 2006.238.07:59:30.89#ibcon#about to read 4, iclass 29, count 0 2006.238.07:59:30.89#ibcon#read 4, iclass 29, count 0 2006.238.07:59:30.89#ibcon#about to read 5, iclass 29, count 0 2006.238.07:59:30.89#ibcon#read 5, iclass 29, count 0 2006.238.07:59:30.89#ibcon#about to read 6, iclass 29, count 0 2006.238.07:59:30.89#ibcon#read 6, iclass 29, count 0 2006.238.07:59:30.89#ibcon#end of sib2, iclass 29, count 0 2006.238.07:59:30.89#ibcon#*after write, iclass 29, count 0 2006.238.07:59:30.89#ibcon#*before return 0, iclass 29, count 0 2006.238.07:59:30.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:59:30.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.07:59:30.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.07:59:30.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.07:59:30.89$vc4f8/vblo=5,744.99 2006.238.07:59:30.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.07:59:30.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.07:59:30.89#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:30.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:59:30.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:59:30.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:59:30.89#ibcon#enter wrdev, iclass 31, count 0 2006.238.07:59:30.89#ibcon#first serial, iclass 31, count 0 2006.238.07:59:30.89#ibcon#enter sib2, iclass 31, count 0 2006.238.07:59:30.89#ibcon#flushed, iclass 31, count 0 2006.238.07:59:30.89#ibcon#about to write, iclass 31, count 0 2006.238.07:59:30.89#ibcon#wrote, iclass 31, count 0 2006.238.07:59:30.89#ibcon#about to read 3, iclass 31, count 0 2006.238.07:59:30.91#ibcon#read 3, iclass 31, count 0 2006.238.07:59:30.91#ibcon#about to read 4, iclass 31, count 0 2006.238.07:59:30.91#ibcon#read 4, iclass 31, count 0 2006.238.07:59:30.91#ibcon#about to read 5, iclass 31, count 0 2006.238.07:59:30.91#ibcon#read 5, iclass 31, count 0 2006.238.07:59:30.91#ibcon#about to read 6, iclass 31, count 0 2006.238.07:59:30.91#ibcon#read 6, iclass 31, count 0 2006.238.07:59:30.91#ibcon#end of sib2, iclass 31, count 0 2006.238.07:59:30.91#ibcon#*mode == 0, iclass 31, count 0 2006.238.07:59:30.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.07:59:30.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.07:59:30.91#ibcon#*before write, iclass 31, count 0 2006.238.07:59:30.91#ibcon#enter sib2, iclass 31, count 0 2006.238.07:59:30.91#ibcon#flushed, iclass 31, count 0 2006.238.07:59:30.91#ibcon#about to write, iclass 31, count 0 2006.238.07:59:30.91#ibcon#wrote, iclass 31, count 0 2006.238.07:59:30.91#ibcon#about to read 3, iclass 31, count 0 2006.238.07:59:30.95#ibcon#read 3, iclass 31, count 0 2006.238.07:59:30.95#ibcon#about to read 4, iclass 31, count 0 2006.238.07:59:30.95#ibcon#read 4, iclass 31, count 0 2006.238.07:59:30.95#ibcon#about to read 5, iclass 31, count 0 2006.238.07:59:30.95#ibcon#read 5, iclass 31, count 0 2006.238.07:59:30.95#ibcon#about to read 6, iclass 31, count 0 2006.238.07:59:30.95#ibcon#read 6, iclass 31, count 0 2006.238.07:59:30.95#ibcon#end of sib2, iclass 31, count 0 2006.238.07:59:30.95#ibcon#*after write, iclass 31, count 0 2006.238.07:59:30.95#ibcon#*before return 0, iclass 31, count 0 2006.238.07:59:30.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:59:30.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.07:59:30.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.07:59:30.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.07:59:30.95$vc4f8/vb=5,4 2006.238.07:59:30.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.07:59:30.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.07:59:30.95#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:30.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:59:31.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:59:31.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:59:31.01#ibcon#enter wrdev, iclass 33, count 2 2006.238.07:59:31.01#ibcon#first serial, iclass 33, count 2 2006.238.07:59:31.01#ibcon#enter sib2, iclass 33, count 2 2006.238.07:59:31.01#ibcon#flushed, iclass 33, count 2 2006.238.07:59:31.01#ibcon#about to write, iclass 33, count 2 2006.238.07:59:31.01#ibcon#wrote, iclass 33, count 2 2006.238.07:59:31.01#ibcon#about to read 3, iclass 33, count 2 2006.238.07:59:31.03#ibcon#read 3, iclass 33, count 2 2006.238.07:59:31.03#ibcon#about to read 4, iclass 33, count 2 2006.238.07:59:31.03#ibcon#read 4, iclass 33, count 2 2006.238.07:59:31.03#ibcon#about to read 5, iclass 33, count 2 2006.238.07:59:31.03#ibcon#read 5, iclass 33, count 2 2006.238.07:59:31.03#ibcon#about to read 6, iclass 33, count 2 2006.238.07:59:31.03#ibcon#read 6, iclass 33, count 2 2006.238.07:59:31.03#ibcon#end of sib2, iclass 33, count 2 2006.238.07:59:31.03#ibcon#*mode == 0, iclass 33, count 2 2006.238.07:59:31.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.07:59:31.03#ibcon#[27=AT05-04\r\n] 2006.238.07:59:31.03#ibcon#*before write, iclass 33, count 2 2006.238.07:59:31.03#ibcon#enter sib2, iclass 33, count 2 2006.238.07:59:31.03#ibcon#flushed, iclass 33, count 2 2006.238.07:59:31.03#ibcon#about to write, iclass 33, count 2 2006.238.07:59:31.03#ibcon#wrote, iclass 33, count 2 2006.238.07:59:31.03#ibcon#about to read 3, iclass 33, count 2 2006.238.07:59:31.06#ibcon#read 3, iclass 33, count 2 2006.238.07:59:31.06#ibcon#about to read 4, iclass 33, count 2 2006.238.07:59:31.06#ibcon#read 4, iclass 33, count 2 2006.238.07:59:31.06#ibcon#about to read 5, iclass 33, count 2 2006.238.07:59:31.06#ibcon#read 5, iclass 33, count 2 2006.238.07:59:31.06#ibcon#about to read 6, iclass 33, count 2 2006.238.07:59:31.06#ibcon#read 6, iclass 33, count 2 2006.238.07:59:31.06#ibcon#end of sib2, iclass 33, count 2 2006.238.07:59:31.06#ibcon#*after write, iclass 33, count 2 2006.238.07:59:31.06#ibcon#*before return 0, iclass 33, count 2 2006.238.07:59:31.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:59:31.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.07:59:31.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.07:59:31.06#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:31.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:59:31.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:59:31.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:59:31.18#ibcon#enter wrdev, iclass 33, count 0 2006.238.07:59:31.18#ibcon#first serial, iclass 33, count 0 2006.238.07:59:31.18#ibcon#enter sib2, iclass 33, count 0 2006.238.07:59:31.18#ibcon#flushed, iclass 33, count 0 2006.238.07:59:31.18#ibcon#about to write, iclass 33, count 0 2006.238.07:59:31.18#ibcon#wrote, iclass 33, count 0 2006.238.07:59:31.18#ibcon#about to read 3, iclass 33, count 0 2006.238.07:59:31.20#ibcon#read 3, iclass 33, count 0 2006.238.07:59:31.20#ibcon#about to read 4, iclass 33, count 0 2006.238.07:59:31.20#ibcon#read 4, iclass 33, count 0 2006.238.07:59:31.20#ibcon#about to read 5, iclass 33, count 0 2006.238.07:59:31.20#ibcon#read 5, iclass 33, count 0 2006.238.07:59:31.20#ibcon#about to read 6, iclass 33, count 0 2006.238.07:59:31.20#ibcon#read 6, iclass 33, count 0 2006.238.07:59:31.20#ibcon#end of sib2, iclass 33, count 0 2006.238.07:59:31.20#ibcon#*mode == 0, iclass 33, count 0 2006.238.07:59:31.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.07:59:31.20#ibcon#[27=USB\r\n] 2006.238.07:59:31.20#ibcon#*before write, iclass 33, count 0 2006.238.07:59:31.20#ibcon#enter sib2, iclass 33, count 0 2006.238.07:59:31.20#ibcon#flushed, iclass 33, count 0 2006.238.07:59:31.20#ibcon#about to write, iclass 33, count 0 2006.238.07:59:31.20#ibcon#wrote, iclass 33, count 0 2006.238.07:59:31.20#ibcon#about to read 3, iclass 33, count 0 2006.238.07:59:31.23#ibcon#read 3, iclass 33, count 0 2006.238.07:59:31.23#ibcon#about to read 4, iclass 33, count 0 2006.238.07:59:31.23#ibcon#read 4, iclass 33, count 0 2006.238.07:59:31.23#ibcon#about to read 5, iclass 33, count 0 2006.238.07:59:31.23#ibcon#read 5, iclass 33, count 0 2006.238.07:59:31.23#ibcon#about to read 6, iclass 33, count 0 2006.238.07:59:31.23#ibcon#read 6, iclass 33, count 0 2006.238.07:59:31.23#ibcon#end of sib2, iclass 33, count 0 2006.238.07:59:31.23#ibcon#*after write, iclass 33, count 0 2006.238.07:59:31.23#ibcon#*before return 0, iclass 33, count 0 2006.238.07:59:31.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:59:31.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.07:59:31.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.07:59:31.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.07:59:31.23$vc4f8/vblo=6,752.99 2006.238.07:59:31.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.07:59:31.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.07:59:31.23#ibcon#ireg 17 cls_cnt 0 2006.238.07:59:31.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:59:31.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:59:31.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:59:31.23#ibcon#enter wrdev, iclass 35, count 0 2006.238.07:59:31.23#ibcon#first serial, iclass 35, count 0 2006.238.07:59:31.23#ibcon#enter sib2, iclass 35, count 0 2006.238.07:59:31.23#ibcon#flushed, iclass 35, count 0 2006.238.07:59:31.23#ibcon#about to write, iclass 35, count 0 2006.238.07:59:31.23#ibcon#wrote, iclass 35, count 0 2006.238.07:59:31.23#ibcon#about to read 3, iclass 35, count 0 2006.238.07:59:31.25#ibcon#read 3, iclass 35, count 0 2006.238.07:59:31.25#ibcon#about to read 4, iclass 35, count 0 2006.238.07:59:31.25#ibcon#read 4, iclass 35, count 0 2006.238.07:59:31.25#ibcon#about to read 5, iclass 35, count 0 2006.238.07:59:31.25#ibcon#read 5, iclass 35, count 0 2006.238.07:59:31.25#ibcon#about to read 6, iclass 35, count 0 2006.238.07:59:31.25#ibcon#read 6, iclass 35, count 0 2006.238.07:59:31.25#ibcon#end of sib2, iclass 35, count 0 2006.238.07:59:31.25#ibcon#*mode == 0, iclass 35, count 0 2006.238.07:59:31.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.07:59:31.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.07:59:31.25#ibcon#*before write, iclass 35, count 0 2006.238.07:59:31.25#ibcon#enter sib2, iclass 35, count 0 2006.238.07:59:31.25#ibcon#flushed, iclass 35, count 0 2006.238.07:59:31.25#ibcon#about to write, iclass 35, count 0 2006.238.07:59:31.25#ibcon#wrote, iclass 35, count 0 2006.238.07:59:31.25#ibcon#about to read 3, iclass 35, count 0 2006.238.07:59:31.29#ibcon#read 3, iclass 35, count 0 2006.238.07:59:31.29#ibcon#about to read 4, iclass 35, count 0 2006.238.07:59:31.29#ibcon#read 4, iclass 35, count 0 2006.238.07:59:31.29#ibcon#about to read 5, iclass 35, count 0 2006.238.07:59:31.29#ibcon#read 5, iclass 35, count 0 2006.238.07:59:31.29#ibcon#about to read 6, iclass 35, count 0 2006.238.07:59:31.29#ibcon#read 6, iclass 35, count 0 2006.238.07:59:31.29#ibcon#end of sib2, iclass 35, count 0 2006.238.07:59:31.29#ibcon#*after write, iclass 35, count 0 2006.238.07:59:31.29#ibcon#*before return 0, iclass 35, count 0 2006.238.07:59:31.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:59:31.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.07:59:31.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.07:59:31.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.07:59:31.29$vc4f8/vb=6,4 2006.238.07:59:31.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.07:59:31.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.07:59:31.29#ibcon#ireg 11 cls_cnt 2 2006.238.07:59:31.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:59:31.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:59:31.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:59:31.35#ibcon#enter wrdev, iclass 37, count 2 2006.238.07:59:31.35#ibcon#first serial, iclass 37, count 2 2006.238.07:59:31.35#ibcon#enter sib2, iclass 37, count 2 2006.238.07:59:31.35#ibcon#flushed, iclass 37, count 2 2006.238.07:59:31.35#ibcon#about to write, iclass 37, count 2 2006.238.07:59:31.35#ibcon#wrote, iclass 37, count 2 2006.238.07:59:31.35#ibcon#about to read 3, iclass 37, count 2 2006.238.07:59:31.37#ibcon#read 3, iclass 37, count 2 2006.238.07:59:31.37#ibcon#about to read 4, iclass 37, count 2 2006.238.07:59:31.37#ibcon#read 4, iclass 37, count 2 2006.238.07:59:31.37#ibcon#about to read 5, iclass 37, count 2 2006.238.07:59:31.37#ibcon#read 5, iclass 37, count 2 2006.238.07:59:31.37#ibcon#about to read 6, iclass 37, count 2 2006.238.07:59:31.37#ibcon#read 6, iclass 37, count 2 2006.238.07:59:31.37#ibcon#end of sib2, iclass 37, count 2 2006.238.07:59:31.37#ibcon#*mode == 0, iclass 37, count 2 2006.238.07:59:31.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.07:59:31.37#ibcon#[27=AT06-04\r\n] 2006.238.07:59:31.37#ibcon#*before write, iclass 37, count 2 2006.238.07:59:31.37#ibcon#enter sib2, iclass 37, count 2 2006.238.07:59:31.37#ibcon#flushed, iclass 37, count 2 2006.238.07:59:31.37#ibcon#about to write, iclass 37, count 2 2006.238.07:59:31.37#ibcon#wrote, iclass 37, count 2 2006.238.07:59:31.37#ibcon#about to read 3, iclass 37, count 2 2006.238.07:59:31.40#ibcon#read 3, iclass 37, count 2 2006.238.07:59:31.40#ibcon#about to read 4, iclass 37, count 2 2006.238.07:59:31.40#ibcon#read 4, iclass 37, count 2 2006.238.07:59:31.40#ibcon#about to read 5, iclass 37, count 2 2006.238.07:59:31.40#ibcon#read 5, iclass 37, count 2 2006.238.07:59:31.40#ibcon#about to read 6, iclass 37, count 2 2006.238.07:59:31.40#ibcon#read 6, iclass 37, count 2 2006.238.07:59:31.40#ibcon#end of sib2, iclass 37, count 2 2006.238.07:59:31.40#ibcon#*after write, iclass 37, count 2 2006.238.07:59:31.40#ibcon#*before return 0, iclass 37, count 2 2006.238.07:59:31.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:59:31.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.07:59:31.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.07:59:31.40#ibcon#ireg 7 cls_cnt 0 2006.238.07:59:31.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:59:31.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:59:31.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:59:31.52#ibcon#enter wrdev, iclass 37, count 0 2006.238.07:59:31.52#ibcon#first serial, iclass 37, count 0 2006.238.07:59:31.52#ibcon#enter sib2, iclass 37, count 0 2006.238.07:59:31.52#ibcon#flushed, iclass 37, count 0 2006.238.07:59:31.52#ibcon#about to write, iclass 37, count 0 2006.238.07:59:31.52#ibcon#wrote, iclass 37, count 0 2006.238.07:59:31.52#ibcon#about to read 3, iclass 37, count 0 2006.238.07:59:31.54#ibcon#read 3, iclass 37, count 0 2006.238.07:59:31.54#ibcon#about to read 4, iclass 37, count 0 2006.238.07:59:31.54#ibcon#read 4, iclass 37, count 0 2006.238.07:59:31.54#ibcon#about to read 5, iclass 37, count 0 2006.238.07:59:31.54#ibcon#read 5, iclass 37, count 0 2006.238.07:59:31.54#ibcon#about to read 6, iclass 37, count 0 2006.238.07:59:31.54#ibcon#read 6, iclass 37, count 0 2006.238.07:59:31.54#ibcon#end of sib2, iclass 37, count 0 2006.238.07:59:31.54#ibcon#*mode == 0, iclass 37, count 0 2006.238.07:59:31.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.07:59:31.54#ibcon#[27=USB\r\n] 2006.238.07:59:31.54#ibcon#*before write, iclass 37, count 0 2006.238.07:59:31.54#ibcon#enter sib2, iclass 37, count 0 2006.238.07:59:31.54#ibcon#flushed, iclass 37, count 0 2006.238.07:59:31.54#ibcon#about to write, iclass 37, count 0 2006.238.07:59:31.54#ibcon#wrote, iclass 37, count 0 2006.238.07:59:31.54#ibcon#about to read 3, iclass 37, count 0 2006.238.07:59:31.57#ibcon#read 3, iclass 37, count 0 2006.238.07:59:31.57#ibcon#about to read 4, iclass 37, count 0 2006.238.07:59:31.57#ibcon#read 4, iclass 37, count 0 2006.238.07:59:31.57#ibcon#about to read 5, iclass 37, count 0 2006.238.07:59:31.57#ibcon#read 5, iclass 37, count 0 2006.238.07:59:31.57#ibcon#about to read 6, iclass 37, count 0 2006.238.07:59:31.57#ibcon#read 6, iclass 37, count 0 2006.238.07:59:31.57#ibcon#end of sib2, iclass 37, count 0 2006.238.07:59:31.57#ibcon#*after write, iclass 37, count 0 2006.238.07:59:31.57#ibcon#*before return 0, iclass 37, count 0 2006.238.07:59:31.57#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:59:31.57#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.07:59:31.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.07:59:31.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.07:59:31.57$vc4f8/vabw=wide 2006.238.07:59:31.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.07:59:31.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.07:59:31.57#ibcon#ireg 8 cls_cnt 0 2006.238.07:59:31.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:59:31.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:59:31.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:59:31.57#ibcon#enter wrdev, iclass 39, count 0 2006.238.07:59:31.57#ibcon#first serial, iclass 39, count 0 2006.238.07:59:31.57#ibcon#enter sib2, iclass 39, count 0 2006.238.07:59:31.57#ibcon#flushed, iclass 39, count 0 2006.238.07:59:31.57#ibcon#about to write, iclass 39, count 0 2006.238.07:59:31.57#ibcon#wrote, iclass 39, count 0 2006.238.07:59:31.57#ibcon#about to read 3, iclass 39, count 0 2006.238.07:59:31.59#ibcon#read 3, iclass 39, count 0 2006.238.07:59:31.59#ibcon#about to read 4, iclass 39, count 0 2006.238.07:59:31.59#ibcon#read 4, iclass 39, count 0 2006.238.07:59:31.59#ibcon#about to read 5, iclass 39, count 0 2006.238.07:59:31.59#ibcon#read 5, iclass 39, count 0 2006.238.07:59:31.59#ibcon#about to read 6, iclass 39, count 0 2006.238.07:59:31.59#ibcon#read 6, iclass 39, count 0 2006.238.07:59:31.59#ibcon#end of sib2, iclass 39, count 0 2006.238.07:59:31.59#ibcon#*mode == 0, iclass 39, count 0 2006.238.07:59:31.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.07:59:31.59#ibcon#[25=BW32\r\n] 2006.238.07:59:31.59#ibcon#*before write, iclass 39, count 0 2006.238.07:59:31.59#ibcon#enter sib2, iclass 39, count 0 2006.238.07:59:31.59#ibcon#flushed, iclass 39, count 0 2006.238.07:59:31.59#ibcon#about to write, iclass 39, count 0 2006.238.07:59:31.59#ibcon#wrote, iclass 39, count 0 2006.238.07:59:31.59#ibcon#about to read 3, iclass 39, count 0 2006.238.07:59:31.62#ibcon#read 3, iclass 39, count 0 2006.238.07:59:31.62#ibcon#about to read 4, iclass 39, count 0 2006.238.07:59:31.62#ibcon#read 4, iclass 39, count 0 2006.238.07:59:31.62#ibcon#about to read 5, iclass 39, count 0 2006.238.07:59:31.62#ibcon#read 5, iclass 39, count 0 2006.238.07:59:31.62#ibcon#about to read 6, iclass 39, count 0 2006.238.07:59:31.62#ibcon#read 6, iclass 39, count 0 2006.238.07:59:31.62#ibcon#end of sib2, iclass 39, count 0 2006.238.07:59:31.62#ibcon#*after write, iclass 39, count 0 2006.238.07:59:31.62#ibcon#*before return 0, iclass 39, count 0 2006.238.07:59:31.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:59:31.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.07:59:31.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.07:59:31.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.07:59:31.62$vc4f8/vbbw=wide 2006.238.07:59:31.62#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.07:59:31.62#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.07:59:31.62#ibcon#ireg 8 cls_cnt 0 2006.238.07:59:31.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:59:31.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:59:31.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:59:31.69#ibcon#enter wrdev, iclass 3, count 0 2006.238.07:59:31.69#ibcon#first serial, iclass 3, count 0 2006.238.07:59:31.69#ibcon#enter sib2, iclass 3, count 0 2006.238.07:59:31.69#ibcon#flushed, iclass 3, count 0 2006.238.07:59:31.69#ibcon#about to write, iclass 3, count 0 2006.238.07:59:31.69#ibcon#wrote, iclass 3, count 0 2006.238.07:59:31.69#ibcon#about to read 3, iclass 3, count 0 2006.238.07:59:31.71#ibcon#read 3, iclass 3, count 0 2006.238.07:59:31.71#ibcon#about to read 4, iclass 3, count 0 2006.238.07:59:31.71#ibcon#read 4, iclass 3, count 0 2006.238.07:59:31.71#ibcon#about to read 5, iclass 3, count 0 2006.238.07:59:31.71#ibcon#read 5, iclass 3, count 0 2006.238.07:59:31.71#ibcon#about to read 6, iclass 3, count 0 2006.238.07:59:31.71#ibcon#read 6, iclass 3, count 0 2006.238.07:59:31.71#ibcon#end of sib2, iclass 3, count 0 2006.238.07:59:31.71#ibcon#*mode == 0, iclass 3, count 0 2006.238.07:59:31.71#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.07:59:31.71#ibcon#[27=BW32\r\n] 2006.238.07:59:31.71#ibcon#*before write, iclass 3, count 0 2006.238.07:59:31.71#ibcon#enter sib2, iclass 3, count 0 2006.238.07:59:31.71#ibcon#flushed, iclass 3, count 0 2006.238.07:59:31.71#ibcon#about to write, iclass 3, count 0 2006.238.07:59:31.71#ibcon#wrote, iclass 3, count 0 2006.238.07:59:31.71#ibcon#about to read 3, iclass 3, count 0 2006.238.07:59:31.74#ibcon#read 3, iclass 3, count 0 2006.238.07:59:31.74#ibcon#about to read 4, iclass 3, count 0 2006.238.07:59:31.74#ibcon#read 4, iclass 3, count 0 2006.238.07:59:31.74#ibcon#about to read 5, iclass 3, count 0 2006.238.07:59:31.74#ibcon#read 5, iclass 3, count 0 2006.238.07:59:31.74#ibcon#about to read 6, iclass 3, count 0 2006.238.07:59:31.74#ibcon#read 6, iclass 3, count 0 2006.238.07:59:31.74#ibcon#end of sib2, iclass 3, count 0 2006.238.07:59:31.74#ibcon#*after write, iclass 3, count 0 2006.238.07:59:31.74#ibcon#*before return 0, iclass 3, count 0 2006.238.07:59:31.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:59:31.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.07:59:31.74#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.07:59:31.74#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.07:59:31.74$4f8m12a/ifd4f 2006.238.07:59:31.74$ifd4f/lo= 2006.238.07:59:31.74$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.07:59:31.74$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.07:59:31.74$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.07:59:31.74$ifd4f/patch= 2006.238.07:59:31.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.07:59:31.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.07:59:31.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.07:59:31.75$4f8m12a/"form=m,16.000,1:2 2006.238.07:59:31.75$4f8m12a/"tpicd 2006.238.07:59:31.75$4f8m12a/echo=off 2006.238.07:59:31.75$4f8m12a/xlog=off 2006.238.07:59:31.75:!2006.238.08:00:00 2006.238.07:59:44.13#trakl#Source acquired 2006.238.07:59:44.13#flagr#flagr/antenna,acquired 2006.238.08:00:00.01:preob 2006.238.08:00:01.13/onsource/TRACKING 2006.238.08:00:01.13:!2006.238.08:00:10 2006.238.08:00:10.00:data_valid=on 2006.238.08:00:10.00:midob 2006.238.08:00:10.13/onsource/TRACKING 2006.238.08:00:10.13/wx/25.43,1012.2,88 2006.238.08:00:10.34/cable/+6.4164E-03 2006.238.08:00:11.43/va/01,08,usb,yes,32,33 2006.238.08:00:11.43/va/02,07,usb,yes,32,33 2006.238.08:00:11.43/va/03,07,usb,yes,30,30 2006.238.08:00:11.43/va/04,07,usb,yes,33,36 2006.238.08:00:11.43/va/05,08,usb,yes,30,31 2006.238.08:00:11.43/va/06,07,usb,yes,32,32 2006.238.08:00:11.43/va/07,07,usb,yes,32,32 2006.238.08:00:11.43/va/08,07,usb,yes,35,35 2006.238.08:00:11.66/valo/01,532.99,yes,locked 2006.238.08:00:11.66/valo/02,572.99,yes,locked 2006.238.08:00:11.66/valo/03,672.99,yes,locked 2006.238.08:00:11.66/valo/04,832.99,yes,locked 2006.238.08:00:11.66/valo/05,652.99,yes,locked 2006.238.08:00:11.66/valo/06,772.99,yes,locked 2006.238.08:00:11.66/valo/07,832.99,yes,locked 2006.238.08:00:11.66/valo/08,852.99,yes,locked 2006.238.08:00:12.75/vb/01,04,usb,yes,30,29 2006.238.08:00:12.75/vb/02,04,usb,yes,32,33 2006.238.08:00:12.75/vb/03,04,usb,yes,28,32 2006.238.08:00:12.75/vb/04,04,usb,yes,29,29 2006.238.08:00:12.75/vb/05,04,usb,yes,28,32 2006.238.08:00:12.75/vb/06,04,usb,yes,28,31 2006.238.08:00:12.75/vb/07,04,usb,yes,31,31 2006.238.08:00:12.75/vb/08,04,usb,yes,28,32 2006.238.08:00:12.99/vblo/01,632.99,yes,locked 2006.238.08:00:12.99/vblo/02,640.99,yes,locked 2006.238.08:00:12.99/vblo/03,656.99,yes,locked 2006.238.08:00:12.99/vblo/04,712.99,yes,locked 2006.238.08:00:12.99/vblo/05,744.99,yes,locked 2006.238.08:00:12.99/vblo/06,752.99,yes,locked 2006.238.08:00:12.99/vblo/07,734.99,yes,locked 2006.238.08:00:12.99/vblo/08,744.99,yes,locked 2006.238.08:00:13.14/vabw/8 2006.238.08:00:13.29/vbbw/8 2006.238.08:00:13.38/xfe/off,on,12.7 2006.238.08:00:13.75/ifatt/23,28,28,28 2006.238.08:00:14.07/fmout-gps/S +4.30E-07 2006.238.08:00:14.12:!2006.238.08:01:10 2006.238.08:01:10.01:data_valid=off 2006.238.08:01:10.02:postob 2006.238.08:01:10.13/cable/+6.4181E-03 2006.238.08:01:10.14/wx/25.43,1012.2,88 2006.238.08:01:11.07/fmout-gps/S +4.29E-07 2006.238.08:01:11.08:scan_name=238-0802,k06238,60 2006.238.08:01:11.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.238.08:01:12.14#flagr#flagr/antenna,new-source 2006.238.08:01:12.15:checkk5 2006.238.08:01:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:01:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:01:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:01:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:01:14.02/chk_obsdata//k5ts1/T2380800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:01:14.39/chk_obsdata//k5ts2/T2380800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:01:14.76/chk_obsdata//k5ts3/T2380800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:01:15.14/chk_obsdata//k5ts4/T2380800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:01:15.84/k5log//k5ts1_log_newline 2006.238.08:01:16.53/k5log//k5ts2_log_newline 2006.238.08:01:17.22/k5log//k5ts3_log_newline 2006.238.08:01:17.91/k5log//k5ts4_log_newline 2006.238.08:01:17.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:01:17.94:4f8m12a=2 2006.238.08:01:17.94$4f8m12a/echo=on 2006.238.08:01:17.94$4f8m12a/pcalon 2006.238.08:01:17.94$pcalon/"no phase cal control is implemented here 2006.238.08:01:17.94$4f8m12a/"tpicd=stop 2006.238.08:01:17.94$4f8m12a/vc4f8 2006.238.08:01:17.94$vc4f8/valo=1,532.99 2006.238.08:01:17.94#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.238.08:01:17.94#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.238.08:01:17.94#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:17.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:01:17.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:01:17.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:01:17.94#ibcon#enter wrdev, iclass 12, count 0 2006.238.08:01:17.94#ibcon#first serial, iclass 12, count 0 2006.238.08:01:17.94#ibcon#enter sib2, iclass 12, count 0 2006.238.08:01:17.94#ibcon#flushed, iclass 12, count 0 2006.238.08:01:17.94#ibcon#about to write, iclass 12, count 0 2006.238.08:01:17.94#ibcon#wrote, iclass 12, count 0 2006.238.08:01:17.94#ibcon#about to read 3, iclass 12, count 0 2006.238.08:01:17.95#ibcon#read 3, iclass 12, count 0 2006.238.08:01:17.95#ibcon#about to read 4, iclass 12, count 0 2006.238.08:01:17.95#ibcon#read 4, iclass 12, count 0 2006.238.08:01:17.95#ibcon#about to read 5, iclass 12, count 0 2006.238.08:01:17.95#ibcon#read 5, iclass 12, count 0 2006.238.08:01:17.95#ibcon#about to read 6, iclass 12, count 0 2006.238.08:01:17.95#ibcon#read 6, iclass 12, count 0 2006.238.08:01:17.95#ibcon#end of sib2, iclass 12, count 0 2006.238.08:01:17.95#ibcon#*mode == 0, iclass 12, count 0 2006.238.08:01:17.95#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.08:01:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:01:17.95#ibcon#*before write, iclass 12, count 0 2006.238.08:01:17.95#ibcon#enter sib2, iclass 12, count 0 2006.238.08:01:17.95#ibcon#flushed, iclass 12, count 0 2006.238.08:01:17.95#ibcon#about to write, iclass 12, count 0 2006.238.08:01:17.95#ibcon#wrote, iclass 12, count 0 2006.238.08:01:17.95#ibcon#about to read 3, iclass 12, count 0 2006.238.08:01:18.00#ibcon#read 3, iclass 12, count 0 2006.238.08:01:18.00#ibcon#about to read 4, iclass 12, count 0 2006.238.08:01:18.00#ibcon#read 4, iclass 12, count 0 2006.238.08:01:18.00#ibcon#about to read 5, iclass 12, count 0 2006.238.08:01:18.00#ibcon#read 5, iclass 12, count 0 2006.238.08:01:18.00#ibcon#about to read 6, iclass 12, count 0 2006.238.08:01:18.00#ibcon#read 6, iclass 12, count 0 2006.238.08:01:18.00#ibcon#end of sib2, iclass 12, count 0 2006.238.08:01:18.00#ibcon#*after write, iclass 12, count 0 2006.238.08:01:18.00#ibcon#*before return 0, iclass 12, count 0 2006.238.08:01:18.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:01:18.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:01:18.00#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.08:01:18.00#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.08:01:18.00$vc4f8/va=1,8 2006.238.08:01:18.00#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.238.08:01:18.00#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.238.08:01:18.00#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:18.00#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:01:18.00#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:01:18.00#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:01:18.00#ibcon#enter wrdev, iclass 14, count 2 2006.238.08:01:18.00#ibcon#first serial, iclass 14, count 2 2006.238.08:01:18.00#ibcon#enter sib2, iclass 14, count 2 2006.238.08:01:18.00#ibcon#flushed, iclass 14, count 2 2006.238.08:01:18.00#ibcon#about to write, iclass 14, count 2 2006.238.08:01:18.00#ibcon#wrote, iclass 14, count 2 2006.238.08:01:18.00#ibcon#about to read 3, iclass 14, count 2 2006.238.08:01:18.02#ibcon#read 3, iclass 14, count 2 2006.238.08:01:18.02#ibcon#about to read 4, iclass 14, count 2 2006.238.08:01:18.02#ibcon#read 4, iclass 14, count 2 2006.238.08:01:18.02#ibcon#about to read 5, iclass 14, count 2 2006.238.08:01:18.02#ibcon#read 5, iclass 14, count 2 2006.238.08:01:18.02#ibcon#about to read 6, iclass 14, count 2 2006.238.08:01:18.02#ibcon#read 6, iclass 14, count 2 2006.238.08:01:18.02#ibcon#end of sib2, iclass 14, count 2 2006.238.08:01:18.02#ibcon#*mode == 0, iclass 14, count 2 2006.238.08:01:18.02#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.238.08:01:18.02#ibcon#[25=AT01-08\r\n] 2006.238.08:01:18.02#ibcon#*before write, iclass 14, count 2 2006.238.08:01:18.02#ibcon#enter sib2, iclass 14, count 2 2006.238.08:01:18.02#ibcon#flushed, iclass 14, count 2 2006.238.08:01:18.02#ibcon#about to write, iclass 14, count 2 2006.238.08:01:18.02#ibcon#wrote, iclass 14, count 2 2006.238.08:01:18.02#ibcon#about to read 3, iclass 14, count 2 2006.238.08:01:18.05#ibcon#read 3, iclass 14, count 2 2006.238.08:01:18.05#ibcon#about to read 4, iclass 14, count 2 2006.238.08:01:18.05#ibcon#read 4, iclass 14, count 2 2006.238.08:01:18.05#ibcon#about to read 5, iclass 14, count 2 2006.238.08:01:18.05#ibcon#read 5, iclass 14, count 2 2006.238.08:01:18.05#ibcon#about to read 6, iclass 14, count 2 2006.238.08:01:18.05#ibcon#read 6, iclass 14, count 2 2006.238.08:01:18.05#ibcon#end of sib2, iclass 14, count 2 2006.238.08:01:18.05#ibcon#*after write, iclass 14, count 2 2006.238.08:01:18.05#ibcon#*before return 0, iclass 14, count 2 2006.238.08:01:18.05#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:01:18.05#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:01:18.05#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.238.08:01:18.05#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:18.05#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:01:18.17#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:01:18.17#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:01:18.17#ibcon#enter wrdev, iclass 14, count 0 2006.238.08:01:18.17#ibcon#first serial, iclass 14, count 0 2006.238.08:01:18.17#ibcon#enter sib2, iclass 14, count 0 2006.238.08:01:18.17#ibcon#flushed, iclass 14, count 0 2006.238.08:01:18.17#ibcon#about to write, iclass 14, count 0 2006.238.08:01:18.17#ibcon#wrote, iclass 14, count 0 2006.238.08:01:18.17#ibcon#about to read 3, iclass 14, count 0 2006.238.08:01:18.19#ibcon#read 3, iclass 14, count 0 2006.238.08:01:18.19#ibcon#about to read 4, iclass 14, count 0 2006.238.08:01:18.19#ibcon#read 4, iclass 14, count 0 2006.238.08:01:18.19#ibcon#about to read 5, iclass 14, count 0 2006.238.08:01:18.19#ibcon#read 5, iclass 14, count 0 2006.238.08:01:18.19#ibcon#about to read 6, iclass 14, count 0 2006.238.08:01:18.19#ibcon#read 6, iclass 14, count 0 2006.238.08:01:18.19#ibcon#end of sib2, iclass 14, count 0 2006.238.08:01:18.19#ibcon#*mode == 0, iclass 14, count 0 2006.238.08:01:18.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.08:01:18.19#ibcon#[25=USB\r\n] 2006.238.08:01:18.19#ibcon#*before write, iclass 14, count 0 2006.238.08:01:18.19#ibcon#enter sib2, iclass 14, count 0 2006.238.08:01:18.19#ibcon#flushed, iclass 14, count 0 2006.238.08:01:18.19#ibcon#about to write, iclass 14, count 0 2006.238.08:01:18.19#ibcon#wrote, iclass 14, count 0 2006.238.08:01:18.19#ibcon#about to read 3, iclass 14, count 0 2006.238.08:01:18.22#ibcon#read 3, iclass 14, count 0 2006.238.08:01:18.22#ibcon#about to read 4, iclass 14, count 0 2006.238.08:01:18.22#ibcon#read 4, iclass 14, count 0 2006.238.08:01:18.22#ibcon#about to read 5, iclass 14, count 0 2006.238.08:01:18.22#ibcon#read 5, iclass 14, count 0 2006.238.08:01:18.22#ibcon#about to read 6, iclass 14, count 0 2006.238.08:01:18.22#ibcon#read 6, iclass 14, count 0 2006.238.08:01:18.22#ibcon#end of sib2, iclass 14, count 0 2006.238.08:01:18.22#ibcon#*after write, iclass 14, count 0 2006.238.08:01:18.22#ibcon#*before return 0, iclass 14, count 0 2006.238.08:01:18.22#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:01:18.22#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:01:18.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.08:01:18.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.08:01:18.22$vc4f8/valo=2,572.99 2006.238.08:01:18.22#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.08:01:18.22#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.08:01:18.22#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:18.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:01:18.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:01:18.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:01:18.22#ibcon#enter wrdev, iclass 16, count 0 2006.238.08:01:18.22#ibcon#first serial, iclass 16, count 0 2006.238.08:01:18.22#ibcon#enter sib2, iclass 16, count 0 2006.238.08:01:18.22#ibcon#flushed, iclass 16, count 0 2006.238.08:01:18.22#ibcon#about to write, iclass 16, count 0 2006.238.08:01:18.22#ibcon#wrote, iclass 16, count 0 2006.238.08:01:18.22#ibcon#about to read 3, iclass 16, count 0 2006.238.08:01:18.24#ibcon#read 3, iclass 16, count 0 2006.238.08:01:18.24#ibcon#about to read 4, iclass 16, count 0 2006.238.08:01:18.24#ibcon#read 4, iclass 16, count 0 2006.238.08:01:18.24#ibcon#about to read 5, iclass 16, count 0 2006.238.08:01:18.24#ibcon#read 5, iclass 16, count 0 2006.238.08:01:18.24#ibcon#about to read 6, iclass 16, count 0 2006.238.08:01:18.24#ibcon#read 6, iclass 16, count 0 2006.238.08:01:18.24#ibcon#end of sib2, iclass 16, count 0 2006.238.08:01:18.24#ibcon#*mode == 0, iclass 16, count 0 2006.238.08:01:18.24#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.08:01:18.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:01:18.24#ibcon#*before write, iclass 16, count 0 2006.238.08:01:18.24#ibcon#enter sib2, iclass 16, count 0 2006.238.08:01:18.24#ibcon#flushed, iclass 16, count 0 2006.238.08:01:18.24#ibcon#about to write, iclass 16, count 0 2006.238.08:01:18.24#ibcon#wrote, iclass 16, count 0 2006.238.08:01:18.24#ibcon#about to read 3, iclass 16, count 0 2006.238.08:01:18.29#ibcon#read 3, iclass 16, count 0 2006.238.08:01:18.29#ibcon#about to read 4, iclass 16, count 0 2006.238.08:01:18.29#ibcon#read 4, iclass 16, count 0 2006.238.08:01:18.29#ibcon#about to read 5, iclass 16, count 0 2006.238.08:01:18.29#ibcon#read 5, iclass 16, count 0 2006.238.08:01:18.29#ibcon#about to read 6, iclass 16, count 0 2006.238.08:01:18.29#ibcon#read 6, iclass 16, count 0 2006.238.08:01:18.29#ibcon#end of sib2, iclass 16, count 0 2006.238.08:01:18.29#ibcon#*after write, iclass 16, count 0 2006.238.08:01:18.29#ibcon#*before return 0, iclass 16, count 0 2006.238.08:01:18.29#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:01:18.29#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:01:18.29#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.08:01:18.29#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.08:01:18.29$vc4f8/va=2,7 2006.238.08:01:18.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.238.08:01:18.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.238.08:01:18.29#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:18.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:01:18.29#abcon#<5=/05 2.1 3.8 25.43 881012.2\r\n> 2006.238.08:01:18.31#abcon#{5=INTERFACE CLEAR} 2006.238.08:01:18.33#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:01:18.33#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:01:18.33#ibcon#enter wrdev, iclass 19, count 2 2006.238.08:01:18.33#ibcon#first serial, iclass 19, count 2 2006.238.08:01:18.33#ibcon#enter sib2, iclass 19, count 2 2006.238.08:01:18.33#ibcon#flushed, iclass 19, count 2 2006.238.08:01:18.33#ibcon#about to write, iclass 19, count 2 2006.238.08:01:18.33#ibcon#wrote, iclass 19, count 2 2006.238.08:01:18.33#ibcon#about to read 3, iclass 19, count 2 2006.238.08:01:18.36#ibcon#read 3, iclass 19, count 2 2006.238.08:01:18.36#ibcon#about to read 4, iclass 19, count 2 2006.238.08:01:18.36#ibcon#read 4, iclass 19, count 2 2006.238.08:01:18.36#ibcon#about to read 5, iclass 19, count 2 2006.238.08:01:18.36#ibcon#read 5, iclass 19, count 2 2006.238.08:01:18.36#ibcon#about to read 6, iclass 19, count 2 2006.238.08:01:18.36#ibcon#read 6, iclass 19, count 2 2006.238.08:01:18.36#ibcon#end of sib2, iclass 19, count 2 2006.238.08:01:18.36#ibcon#*mode == 0, iclass 19, count 2 2006.238.08:01:18.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.238.08:01:18.36#ibcon#[25=AT02-07\r\n] 2006.238.08:01:18.36#ibcon#*before write, iclass 19, count 2 2006.238.08:01:18.36#ibcon#enter sib2, iclass 19, count 2 2006.238.08:01:18.36#ibcon#flushed, iclass 19, count 2 2006.238.08:01:18.36#ibcon#about to write, iclass 19, count 2 2006.238.08:01:18.36#ibcon#wrote, iclass 19, count 2 2006.238.08:01:18.36#ibcon#about to read 3, iclass 19, count 2 2006.238.08:01:18.38#abcon#[5=S1D000X0/0*\r\n] 2006.238.08:01:18.39#ibcon#read 3, iclass 19, count 2 2006.238.08:01:18.39#ibcon#about to read 4, iclass 19, count 2 2006.238.08:01:18.39#ibcon#read 4, iclass 19, count 2 2006.238.08:01:18.39#ibcon#about to read 5, iclass 19, count 2 2006.238.08:01:18.39#ibcon#read 5, iclass 19, count 2 2006.238.08:01:18.39#ibcon#about to read 6, iclass 19, count 2 2006.238.08:01:18.39#ibcon#read 6, iclass 19, count 2 2006.238.08:01:18.39#ibcon#end of sib2, iclass 19, count 2 2006.238.08:01:18.39#ibcon#*after write, iclass 19, count 2 2006.238.08:01:18.39#ibcon#*before return 0, iclass 19, count 2 2006.238.08:01:18.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:01:18.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:01:18.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.238.08:01:18.39#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:18.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:01:18.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:01:18.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:01:18.51#ibcon#enter wrdev, iclass 19, count 0 2006.238.08:01:18.51#ibcon#first serial, iclass 19, count 0 2006.238.08:01:18.51#ibcon#enter sib2, iclass 19, count 0 2006.238.08:01:18.51#ibcon#flushed, iclass 19, count 0 2006.238.08:01:18.51#ibcon#about to write, iclass 19, count 0 2006.238.08:01:18.51#ibcon#wrote, iclass 19, count 0 2006.238.08:01:18.51#ibcon#about to read 3, iclass 19, count 0 2006.238.08:01:18.53#ibcon#read 3, iclass 19, count 0 2006.238.08:01:18.53#ibcon#about to read 4, iclass 19, count 0 2006.238.08:01:18.53#ibcon#read 4, iclass 19, count 0 2006.238.08:01:18.53#ibcon#about to read 5, iclass 19, count 0 2006.238.08:01:18.53#ibcon#read 5, iclass 19, count 0 2006.238.08:01:18.53#ibcon#about to read 6, iclass 19, count 0 2006.238.08:01:18.53#ibcon#read 6, iclass 19, count 0 2006.238.08:01:18.53#ibcon#end of sib2, iclass 19, count 0 2006.238.08:01:18.53#ibcon#*mode == 0, iclass 19, count 0 2006.238.08:01:18.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.08:01:18.53#ibcon#[25=USB\r\n] 2006.238.08:01:18.53#ibcon#*before write, iclass 19, count 0 2006.238.08:01:18.53#ibcon#enter sib2, iclass 19, count 0 2006.238.08:01:18.53#ibcon#flushed, iclass 19, count 0 2006.238.08:01:18.53#ibcon#about to write, iclass 19, count 0 2006.238.08:01:18.53#ibcon#wrote, iclass 19, count 0 2006.238.08:01:18.53#ibcon#about to read 3, iclass 19, count 0 2006.238.08:01:18.56#ibcon#read 3, iclass 19, count 0 2006.238.08:01:18.56#ibcon#about to read 4, iclass 19, count 0 2006.238.08:01:18.56#ibcon#read 4, iclass 19, count 0 2006.238.08:01:18.56#ibcon#about to read 5, iclass 19, count 0 2006.238.08:01:18.56#ibcon#read 5, iclass 19, count 0 2006.238.08:01:18.56#ibcon#about to read 6, iclass 19, count 0 2006.238.08:01:18.56#ibcon#read 6, iclass 19, count 0 2006.238.08:01:18.56#ibcon#end of sib2, iclass 19, count 0 2006.238.08:01:18.56#ibcon#*after write, iclass 19, count 0 2006.238.08:01:18.56#ibcon#*before return 0, iclass 19, count 0 2006.238.08:01:18.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:01:18.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:01:18.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.08:01:18.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.08:01:18.56$vc4f8/valo=3,672.99 2006.238.08:01:18.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.08:01:18.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.08:01:18.56#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:18.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:01:18.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:01:18.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:01:18.56#ibcon#enter wrdev, iclass 24, count 0 2006.238.08:01:18.56#ibcon#first serial, iclass 24, count 0 2006.238.08:01:18.56#ibcon#enter sib2, iclass 24, count 0 2006.238.08:01:18.56#ibcon#flushed, iclass 24, count 0 2006.238.08:01:18.56#ibcon#about to write, iclass 24, count 0 2006.238.08:01:18.56#ibcon#wrote, iclass 24, count 0 2006.238.08:01:18.56#ibcon#about to read 3, iclass 24, count 0 2006.238.08:01:18.58#ibcon#read 3, iclass 24, count 0 2006.238.08:01:18.58#ibcon#about to read 4, iclass 24, count 0 2006.238.08:01:18.58#ibcon#read 4, iclass 24, count 0 2006.238.08:01:18.58#ibcon#about to read 5, iclass 24, count 0 2006.238.08:01:18.58#ibcon#read 5, iclass 24, count 0 2006.238.08:01:18.58#ibcon#about to read 6, iclass 24, count 0 2006.238.08:01:18.58#ibcon#read 6, iclass 24, count 0 2006.238.08:01:18.58#ibcon#end of sib2, iclass 24, count 0 2006.238.08:01:18.58#ibcon#*mode == 0, iclass 24, count 0 2006.238.08:01:18.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.08:01:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:01:18.58#ibcon#*before write, iclass 24, count 0 2006.238.08:01:18.58#ibcon#enter sib2, iclass 24, count 0 2006.238.08:01:18.58#ibcon#flushed, iclass 24, count 0 2006.238.08:01:18.58#ibcon#about to write, iclass 24, count 0 2006.238.08:01:18.58#ibcon#wrote, iclass 24, count 0 2006.238.08:01:18.58#ibcon#about to read 3, iclass 24, count 0 2006.238.08:01:18.62#ibcon#read 3, iclass 24, count 0 2006.238.08:01:18.62#ibcon#about to read 4, iclass 24, count 0 2006.238.08:01:18.62#ibcon#read 4, iclass 24, count 0 2006.238.08:01:18.62#ibcon#about to read 5, iclass 24, count 0 2006.238.08:01:18.62#ibcon#read 5, iclass 24, count 0 2006.238.08:01:18.62#ibcon#about to read 6, iclass 24, count 0 2006.238.08:01:18.62#ibcon#read 6, iclass 24, count 0 2006.238.08:01:18.62#ibcon#end of sib2, iclass 24, count 0 2006.238.08:01:18.62#ibcon#*after write, iclass 24, count 0 2006.238.08:01:18.62#ibcon#*before return 0, iclass 24, count 0 2006.238.08:01:18.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:01:18.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:01:18.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.08:01:18.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.08:01:18.62$vc4f8/va=3,7 2006.238.08:01:18.62#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.238.08:01:18.62#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.238.08:01:18.62#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:18.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:01:18.68#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:01:18.68#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:01:18.68#ibcon#enter wrdev, iclass 26, count 2 2006.238.08:01:18.68#ibcon#first serial, iclass 26, count 2 2006.238.08:01:18.68#ibcon#enter sib2, iclass 26, count 2 2006.238.08:01:18.68#ibcon#flushed, iclass 26, count 2 2006.238.08:01:18.68#ibcon#about to write, iclass 26, count 2 2006.238.08:01:18.68#ibcon#wrote, iclass 26, count 2 2006.238.08:01:18.68#ibcon#about to read 3, iclass 26, count 2 2006.238.08:01:18.70#ibcon#read 3, iclass 26, count 2 2006.238.08:01:18.70#ibcon#about to read 4, iclass 26, count 2 2006.238.08:01:18.70#ibcon#read 4, iclass 26, count 2 2006.238.08:01:18.70#ibcon#about to read 5, iclass 26, count 2 2006.238.08:01:18.70#ibcon#read 5, iclass 26, count 2 2006.238.08:01:18.70#ibcon#about to read 6, iclass 26, count 2 2006.238.08:01:18.70#ibcon#read 6, iclass 26, count 2 2006.238.08:01:18.70#ibcon#end of sib2, iclass 26, count 2 2006.238.08:01:18.70#ibcon#*mode == 0, iclass 26, count 2 2006.238.08:01:18.70#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.238.08:01:18.70#ibcon#[25=AT03-07\r\n] 2006.238.08:01:18.70#ibcon#*before write, iclass 26, count 2 2006.238.08:01:18.70#ibcon#enter sib2, iclass 26, count 2 2006.238.08:01:18.70#ibcon#flushed, iclass 26, count 2 2006.238.08:01:18.70#ibcon#about to write, iclass 26, count 2 2006.238.08:01:18.70#ibcon#wrote, iclass 26, count 2 2006.238.08:01:18.70#ibcon#about to read 3, iclass 26, count 2 2006.238.08:01:18.73#ibcon#read 3, iclass 26, count 2 2006.238.08:01:18.73#ibcon#about to read 4, iclass 26, count 2 2006.238.08:01:18.73#ibcon#read 4, iclass 26, count 2 2006.238.08:01:18.73#ibcon#about to read 5, iclass 26, count 2 2006.238.08:01:18.73#ibcon#read 5, iclass 26, count 2 2006.238.08:01:18.73#ibcon#about to read 6, iclass 26, count 2 2006.238.08:01:18.73#ibcon#read 6, iclass 26, count 2 2006.238.08:01:18.73#ibcon#end of sib2, iclass 26, count 2 2006.238.08:01:18.73#ibcon#*after write, iclass 26, count 2 2006.238.08:01:18.73#ibcon#*before return 0, iclass 26, count 2 2006.238.08:01:18.73#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:01:18.73#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:01:18.73#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.238.08:01:18.73#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:18.73#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:01:18.85#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:01:18.85#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:01:18.85#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:01:18.85#ibcon#first serial, iclass 26, count 0 2006.238.08:01:18.85#ibcon#enter sib2, iclass 26, count 0 2006.238.08:01:18.85#ibcon#flushed, iclass 26, count 0 2006.238.08:01:18.85#ibcon#about to write, iclass 26, count 0 2006.238.08:01:18.85#ibcon#wrote, iclass 26, count 0 2006.238.08:01:18.85#ibcon#about to read 3, iclass 26, count 0 2006.238.08:01:18.87#ibcon#read 3, iclass 26, count 0 2006.238.08:01:18.87#ibcon#about to read 4, iclass 26, count 0 2006.238.08:01:18.87#ibcon#read 4, iclass 26, count 0 2006.238.08:01:18.87#ibcon#about to read 5, iclass 26, count 0 2006.238.08:01:18.87#ibcon#read 5, iclass 26, count 0 2006.238.08:01:18.87#ibcon#about to read 6, iclass 26, count 0 2006.238.08:01:18.87#ibcon#read 6, iclass 26, count 0 2006.238.08:01:18.87#ibcon#end of sib2, iclass 26, count 0 2006.238.08:01:18.87#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:01:18.87#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:01:18.87#ibcon#[25=USB\r\n] 2006.238.08:01:18.87#ibcon#*before write, iclass 26, count 0 2006.238.08:01:18.87#ibcon#enter sib2, iclass 26, count 0 2006.238.08:01:18.87#ibcon#flushed, iclass 26, count 0 2006.238.08:01:18.87#ibcon#about to write, iclass 26, count 0 2006.238.08:01:18.87#ibcon#wrote, iclass 26, count 0 2006.238.08:01:18.87#ibcon#about to read 3, iclass 26, count 0 2006.238.08:01:18.90#ibcon#read 3, iclass 26, count 0 2006.238.08:01:18.90#ibcon#about to read 4, iclass 26, count 0 2006.238.08:01:18.90#ibcon#read 4, iclass 26, count 0 2006.238.08:01:18.90#ibcon#about to read 5, iclass 26, count 0 2006.238.08:01:18.90#ibcon#read 5, iclass 26, count 0 2006.238.08:01:18.90#ibcon#about to read 6, iclass 26, count 0 2006.238.08:01:18.90#ibcon#read 6, iclass 26, count 0 2006.238.08:01:18.90#ibcon#end of sib2, iclass 26, count 0 2006.238.08:01:18.90#ibcon#*after write, iclass 26, count 0 2006.238.08:01:18.90#ibcon#*before return 0, iclass 26, count 0 2006.238.08:01:18.90#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:01:18.90#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:01:18.90#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:01:18.90#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:01:18.90$vc4f8/valo=4,832.99 2006.238.08:01:18.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.238.08:01:18.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.238.08:01:18.90#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:18.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:01:18.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:01:18.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:01:18.90#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:01:18.90#ibcon#first serial, iclass 28, count 0 2006.238.08:01:18.90#ibcon#enter sib2, iclass 28, count 0 2006.238.08:01:18.90#ibcon#flushed, iclass 28, count 0 2006.238.08:01:18.90#ibcon#about to write, iclass 28, count 0 2006.238.08:01:18.90#ibcon#wrote, iclass 28, count 0 2006.238.08:01:18.90#ibcon#about to read 3, iclass 28, count 0 2006.238.08:01:18.92#ibcon#read 3, iclass 28, count 0 2006.238.08:01:18.92#ibcon#about to read 4, iclass 28, count 0 2006.238.08:01:18.92#ibcon#read 4, iclass 28, count 0 2006.238.08:01:18.92#ibcon#about to read 5, iclass 28, count 0 2006.238.08:01:18.92#ibcon#read 5, iclass 28, count 0 2006.238.08:01:18.92#ibcon#about to read 6, iclass 28, count 0 2006.238.08:01:18.92#ibcon#read 6, iclass 28, count 0 2006.238.08:01:18.92#ibcon#end of sib2, iclass 28, count 0 2006.238.08:01:18.92#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:01:18.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:01:18.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:01:18.92#ibcon#*before write, iclass 28, count 0 2006.238.08:01:18.92#ibcon#enter sib2, iclass 28, count 0 2006.238.08:01:18.92#ibcon#flushed, iclass 28, count 0 2006.238.08:01:18.92#ibcon#about to write, iclass 28, count 0 2006.238.08:01:18.92#ibcon#wrote, iclass 28, count 0 2006.238.08:01:18.92#ibcon#about to read 3, iclass 28, count 0 2006.238.08:01:18.96#ibcon#read 3, iclass 28, count 0 2006.238.08:01:18.96#ibcon#about to read 4, iclass 28, count 0 2006.238.08:01:18.96#ibcon#read 4, iclass 28, count 0 2006.238.08:01:18.96#ibcon#about to read 5, iclass 28, count 0 2006.238.08:01:18.96#ibcon#read 5, iclass 28, count 0 2006.238.08:01:18.96#ibcon#about to read 6, iclass 28, count 0 2006.238.08:01:18.96#ibcon#read 6, iclass 28, count 0 2006.238.08:01:18.96#ibcon#end of sib2, iclass 28, count 0 2006.238.08:01:18.96#ibcon#*after write, iclass 28, count 0 2006.238.08:01:18.96#ibcon#*before return 0, iclass 28, count 0 2006.238.08:01:18.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:01:18.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:01:18.96#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:01:18.96#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:01:18.96$vc4f8/va=4,7 2006.238.08:01:18.96#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.238.08:01:18.96#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.238.08:01:18.96#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:18.96#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:01:19.02#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:01:19.02#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:01:19.02#ibcon#enter wrdev, iclass 30, count 2 2006.238.08:01:19.02#ibcon#first serial, iclass 30, count 2 2006.238.08:01:19.02#ibcon#enter sib2, iclass 30, count 2 2006.238.08:01:19.02#ibcon#flushed, iclass 30, count 2 2006.238.08:01:19.02#ibcon#about to write, iclass 30, count 2 2006.238.08:01:19.02#ibcon#wrote, iclass 30, count 2 2006.238.08:01:19.02#ibcon#about to read 3, iclass 30, count 2 2006.238.08:01:19.04#ibcon#read 3, iclass 30, count 2 2006.238.08:01:19.04#ibcon#about to read 4, iclass 30, count 2 2006.238.08:01:19.04#ibcon#read 4, iclass 30, count 2 2006.238.08:01:19.04#ibcon#about to read 5, iclass 30, count 2 2006.238.08:01:19.04#ibcon#read 5, iclass 30, count 2 2006.238.08:01:19.04#ibcon#about to read 6, iclass 30, count 2 2006.238.08:01:19.04#ibcon#read 6, iclass 30, count 2 2006.238.08:01:19.04#ibcon#end of sib2, iclass 30, count 2 2006.238.08:01:19.04#ibcon#*mode == 0, iclass 30, count 2 2006.238.08:01:19.04#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.238.08:01:19.04#ibcon#[25=AT04-07\r\n] 2006.238.08:01:19.04#ibcon#*before write, iclass 30, count 2 2006.238.08:01:19.04#ibcon#enter sib2, iclass 30, count 2 2006.238.08:01:19.04#ibcon#flushed, iclass 30, count 2 2006.238.08:01:19.04#ibcon#about to write, iclass 30, count 2 2006.238.08:01:19.04#ibcon#wrote, iclass 30, count 2 2006.238.08:01:19.04#ibcon#about to read 3, iclass 30, count 2 2006.238.08:01:19.07#ibcon#read 3, iclass 30, count 2 2006.238.08:01:19.07#ibcon#about to read 4, iclass 30, count 2 2006.238.08:01:19.07#ibcon#read 4, iclass 30, count 2 2006.238.08:01:19.07#ibcon#about to read 5, iclass 30, count 2 2006.238.08:01:19.07#ibcon#read 5, iclass 30, count 2 2006.238.08:01:19.07#ibcon#about to read 6, iclass 30, count 2 2006.238.08:01:19.07#ibcon#read 6, iclass 30, count 2 2006.238.08:01:19.07#ibcon#end of sib2, iclass 30, count 2 2006.238.08:01:19.07#ibcon#*after write, iclass 30, count 2 2006.238.08:01:19.07#ibcon#*before return 0, iclass 30, count 2 2006.238.08:01:19.07#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:01:19.07#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:01:19.07#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.238.08:01:19.07#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:19.07#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:01:19.19#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:01:19.19#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:01:19.19#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:01:19.19#ibcon#first serial, iclass 30, count 0 2006.238.08:01:19.19#ibcon#enter sib2, iclass 30, count 0 2006.238.08:01:19.19#ibcon#flushed, iclass 30, count 0 2006.238.08:01:19.19#ibcon#about to write, iclass 30, count 0 2006.238.08:01:19.19#ibcon#wrote, iclass 30, count 0 2006.238.08:01:19.19#ibcon#about to read 3, iclass 30, count 0 2006.238.08:01:19.21#ibcon#read 3, iclass 30, count 0 2006.238.08:01:19.21#ibcon#about to read 4, iclass 30, count 0 2006.238.08:01:19.21#ibcon#read 4, iclass 30, count 0 2006.238.08:01:19.21#ibcon#about to read 5, iclass 30, count 0 2006.238.08:01:19.21#ibcon#read 5, iclass 30, count 0 2006.238.08:01:19.21#ibcon#about to read 6, iclass 30, count 0 2006.238.08:01:19.21#ibcon#read 6, iclass 30, count 0 2006.238.08:01:19.21#ibcon#end of sib2, iclass 30, count 0 2006.238.08:01:19.21#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:01:19.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:01:19.21#ibcon#[25=USB\r\n] 2006.238.08:01:19.21#ibcon#*before write, iclass 30, count 0 2006.238.08:01:19.21#ibcon#enter sib2, iclass 30, count 0 2006.238.08:01:19.21#ibcon#flushed, iclass 30, count 0 2006.238.08:01:19.21#ibcon#about to write, iclass 30, count 0 2006.238.08:01:19.21#ibcon#wrote, iclass 30, count 0 2006.238.08:01:19.21#ibcon#about to read 3, iclass 30, count 0 2006.238.08:01:19.24#ibcon#read 3, iclass 30, count 0 2006.238.08:01:19.24#ibcon#about to read 4, iclass 30, count 0 2006.238.08:01:19.24#ibcon#read 4, iclass 30, count 0 2006.238.08:01:19.24#ibcon#about to read 5, iclass 30, count 0 2006.238.08:01:19.24#ibcon#read 5, iclass 30, count 0 2006.238.08:01:19.24#ibcon#about to read 6, iclass 30, count 0 2006.238.08:01:19.24#ibcon#read 6, iclass 30, count 0 2006.238.08:01:19.24#ibcon#end of sib2, iclass 30, count 0 2006.238.08:01:19.24#ibcon#*after write, iclass 30, count 0 2006.238.08:01:19.24#ibcon#*before return 0, iclass 30, count 0 2006.238.08:01:19.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:01:19.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:01:19.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:01:19.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:01:19.24$vc4f8/valo=5,652.99 2006.238.08:01:19.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.08:01:19.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.08:01:19.24#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:19.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:01:19.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:01:19.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:01:19.24#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:01:19.24#ibcon#first serial, iclass 32, count 0 2006.238.08:01:19.24#ibcon#enter sib2, iclass 32, count 0 2006.238.08:01:19.24#ibcon#flushed, iclass 32, count 0 2006.238.08:01:19.24#ibcon#about to write, iclass 32, count 0 2006.238.08:01:19.24#ibcon#wrote, iclass 32, count 0 2006.238.08:01:19.24#ibcon#about to read 3, iclass 32, count 0 2006.238.08:01:19.26#ibcon#read 3, iclass 32, count 0 2006.238.08:01:19.26#ibcon#about to read 4, iclass 32, count 0 2006.238.08:01:19.26#ibcon#read 4, iclass 32, count 0 2006.238.08:01:19.26#ibcon#about to read 5, iclass 32, count 0 2006.238.08:01:19.26#ibcon#read 5, iclass 32, count 0 2006.238.08:01:19.26#ibcon#about to read 6, iclass 32, count 0 2006.238.08:01:19.26#ibcon#read 6, iclass 32, count 0 2006.238.08:01:19.26#ibcon#end of sib2, iclass 32, count 0 2006.238.08:01:19.26#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:01:19.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:01:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:01:19.26#ibcon#*before write, iclass 32, count 0 2006.238.08:01:19.26#ibcon#enter sib2, iclass 32, count 0 2006.238.08:01:19.26#ibcon#flushed, iclass 32, count 0 2006.238.08:01:19.26#ibcon#about to write, iclass 32, count 0 2006.238.08:01:19.26#ibcon#wrote, iclass 32, count 0 2006.238.08:01:19.26#ibcon#about to read 3, iclass 32, count 0 2006.238.08:01:19.30#ibcon#read 3, iclass 32, count 0 2006.238.08:01:19.30#ibcon#about to read 4, iclass 32, count 0 2006.238.08:01:19.30#ibcon#read 4, iclass 32, count 0 2006.238.08:01:19.30#ibcon#about to read 5, iclass 32, count 0 2006.238.08:01:19.30#ibcon#read 5, iclass 32, count 0 2006.238.08:01:19.30#ibcon#about to read 6, iclass 32, count 0 2006.238.08:01:19.30#ibcon#read 6, iclass 32, count 0 2006.238.08:01:19.30#ibcon#end of sib2, iclass 32, count 0 2006.238.08:01:19.30#ibcon#*after write, iclass 32, count 0 2006.238.08:01:19.30#ibcon#*before return 0, iclass 32, count 0 2006.238.08:01:19.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:01:19.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:01:19.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:01:19.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:01:19.30$vc4f8/va=5,8 2006.238.08:01:19.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.238.08:01:19.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.238.08:01:19.30#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:19.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:01:19.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:01:19.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:01:19.36#ibcon#enter wrdev, iclass 34, count 2 2006.238.08:01:19.36#ibcon#first serial, iclass 34, count 2 2006.238.08:01:19.36#ibcon#enter sib2, iclass 34, count 2 2006.238.08:01:19.36#ibcon#flushed, iclass 34, count 2 2006.238.08:01:19.36#ibcon#about to write, iclass 34, count 2 2006.238.08:01:19.36#ibcon#wrote, iclass 34, count 2 2006.238.08:01:19.36#ibcon#about to read 3, iclass 34, count 2 2006.238.08:01:19.38#ibcon#read 3, iclass 34, count 2 2006.238.08:01:19.38#ibcon#about to read 4, iclass 34, count 2 2006.238.08:01:19.38#ibcon#read 4, iclass 34, count 2 2006.238.08:01:19.38#ibcon#about to read 5, iclass 34, count 2 2006.238.08:01:19.38#ibcon#read 5, iclass 34, count 2 2006.238.08:01:19.38#ibcon#about to read 6, iclass 34, count 2 2006.238.08:01:19.38#ibcon#read 6, iclass 34, count 2 2006.238.08:01:19.38#ibcon#end of sib2, iclass 34, count 2 2006.238.08:01:19.38#ibcon#*mode == 0, iclass 34, count 2 2006.238.08:01:19.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.238.08:01:19.38#ibcon#[25=AT05-08\r\n] 2006.238.08:01:19.38#ibcon#*before write, iclass 34, count 2 2006.238.08:01:19.38#ibcon#enter sib2, iclass 34, count 2 2006.238.08:01:19.38#ibcon#flushed, iclass 34, count 2 2006.238.08:01:19.38#ibcon#about to write, iclass 34, count 2 2006.238.08:01:19.38#ibcon#wrote, iclass 34, count 2 2006.238.08:01:19.38#ibcon#about to read 3, iclass 34, count 2 2006.238.08:01:19.41#ibcon#read 3, iclass 34, count 2 2006.238.08:01:19.41#ibcon#about to read 4, iclass 34, count 2 2006.238.08:01:19.41#ibcon#read 4, iclass 34, count 2 2006.238.08:01:19.41#ibcon#about to read 5, iclass 34, count 2 2006.238.08:01:19.41#ibcon#read 5, iclass 34, count 2 2006.238.08:01:19.41#ibcon#about to read 6, iclass 34, count 2 2006.238.08:01:19.41#ibcon#read 6, iclass 34, count 2 2006.238.08:01:19.41#ibcon#end of sib2, iclass 34, count 2 2006.238.08:01:19.41#ibcon#*after write, iclass 34, count 2 2006.238.08:01:19.41#ibcon#*before return 0, iclass 34, count 2 2006.238.08:01:19.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:01:19.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:01:19.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.238.08:01:19.41#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:19.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:01:19.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:01:19.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:01:19.55#ibcon#enter wrdev, iclass 34, count 0 2006.238.08:01:19.55#ibcon#first serial, iclass 34, count 0 2006.238.08:01:19.55#ibcon#enter sib2, iclass 34, count 0 2006.238.08:01:19.55#ibcon#flushed, iclass 34, count 0 2006.238.08:01:19.55#ibcon#about to write, iclass 34, count 0 2006.238.08:01:19.55#ibcon#wrote, iclass 34, count 0 2006.238.08:01:19.55#ibcon#about to read 3, iclass 34, count 0 2006.238.08:01:19.56#ibcon#read 3, iclass 34, count 0 2006.238.08:01:19.56#ibcon#about to read 4, iclass 34, count 0 2006.238.08:01:19.56#ibcon#read 4, iclass 34, count 0 2006.238.08:01:19.56#ibcon#about to read 5, iclass 34, count 0 2006.238.08:01:19.56#ibcon#read 5, iclass 34, count 0 2006.238.08:01:19.56#ibcon#about to read 6, iclass 34, count 0 2006.238.08:01:19.56#ibcon#read 6, iclass 34, count 0 2006.238.08:01:19.56#ibcon#end of sib2, iclass 34, count 0 2006.238.08:01:19.56#ibcon#*mode == 0, iclass 34, count 0 2006.238.08:01:19.56#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.08:01:19.56#ibcon#[25=USB\r\n] 2006.238.08:01:19.56#ibcon#*before write, iclass 34, count 0 2006.238.08:01:19.56#ibcon#enter sib2, iclass 34, count 0 2006.238.08:01:19.56#ibcon#flushed, iclass 34, count 0 2006.238.08:01:19.56#ibcon#about to write, iclass 34, count 0 2006.238.08:01:19.56#ibcon#wrote, iclass 34, count 0 2006.238.08:01:19.56#ibcon#about to read 3, iclass 34, count 0 2006.238.08:01:19.59#ibcon#read 3, iclass 34, count 0 2006.238.08:01:19.59#ibcon#about to read 4, iclass 34, count 0 2006.238.08:01:19.59#ibcon#read 4, iclass 34, count 0 2006.238.08:01:19.59#ibcon#about to read 5, iclass 34, count 0 2006.238.08:01:19.59#ibcon#read 5, iclass 34, count 0 2006.238.08:01:19.59#ibcon#about to read 6, iclass 34, count 0 2006.238.08:01:19.59#ibcon#read 6, iclass 34, count 0 2006.238.08:01:19.59#ibcon#end of sib2, iclass 34, count 0 2006.238.08:01:19.59#ibcon#*after write, iclass 34, count 0 2006.238.08:01:19.59#ibcon#*before return 0, iclass 34, count 0 2006.238.08:01:19.59#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:01:19.59#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:01:19.59#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.08:01:19.59#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.08:01:19.59$vc4f8/valo=6,772.99 2006.238.08:01:19.59#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.08:01:19.59#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.08:01:19.59#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:19.59#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:01:19.59#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:01:19.59#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:01:19.59#ibcon#enter wrdev, iclass 36, count 0 2006.238.08:01:19.59#ibcon#first serial, iclass 36, count 0 2006.238.08:01:19.59#ibcon#enter sib2, iclass 36, count 0 2006.238.08:01:19.59#ibcon#flushed, iclass 36, count 0 2006.238.08:01:19.59#ibcon#about to write, iclass 36, count 0 2006.238.08:01:19.59#ibcon#wrote, iclass 36, count 0 2006.238.08:01:19.59#ibcon#about to read 3, iclass 36, count 0 2006.238.08:01:19.61#ibcon#read 3, iclass 36, count 0 2006.238.08:01:19.61#ibcon#about to read 4, iclass 36, count 0 2006.238.08:01:19.61#ibcon#read 4, iclass 36, count 0 2006.238.08:01:19.61#ibcon#about to read 5, iclass 36, count 0 2006.238.08:01:19.61#ibcon#read 5, iclass 36, count 0 2006.238.08:01:19.61#ibcon#about to read 6, iclass 36, count 0 2006.238.08:01:19.61#ibcon#read 6, iclass 36, count 0 2006.238.08:01:19.61#ibcon#end of sib2, iclass 36, count 0 2006.238.08:01:19.61#ibcon#*mode == 0, iclass 36, count 0 2006.238.08:01:19.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.08:01:19.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:01:19.61#ibcon#*before write, iclass 36, count 0 2006.238.08:01:19.61#ibcon#enter sib2, iclass 36, count 0 2006.238.08:01:19.61#ibcon#flushed, iclass 36, count 0 2006.238.08:01:19.61#ibcon#about to write, iclass 36, count 0 2006.238.08:01:19.61#ibcon#wrote, iclass 36, count 0 2006.238.08:01:19.61#ibcon#about to read 3, iclass 36, count 0 2006.238.08:01:19.65#ibcon#read 3, iclass 36, count 0 2006.238.08:01:19.65#ibcon#about to read 4, iclass 36, count 0 2006.238.08:01:19.65#ibcon#read 4, iclass 36, count 0 2006.238.08:01:19.65#ibcon#about to read 5, iclass 36, count 0 2006.238.08:01:19.65#ibcon#read 5, iclass 36, count 0 2006.238.08:01:19.65#ibcon#about to read 6, iclass 36, count 0 2006.238.08:01:19.65#ibcon#read 6, iclass 36, count 0 2006.238.08:01:19.65#ibcon#end of sib2, iclass 36, count 0 2006.238.08:01:19.65#ibcon#*after write, iclass 36, count 0 2006.238.08:01:19.65#ibcon#*before return 0, iclass 36, count 0 2006.238.08:01:19.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:01:19.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:01:19.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.08:01:19.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.08:01:19.65$vc4f8/va=6,7 2006.238.08:01:19.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.238.08:01:19.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.238.08:01:19.65#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:19.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:01:19.71#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:01:19.71#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:01:19.71#ibcon#enter wrdev, iclass 38, count 2 2006.238.08:01:19.71#ibcon#first serial, iclass 38, count 2 2006.238.08:01:19.71#ibcon#enter sib2, iclass 38, count 2 2006.238.08:01:19.71#ibcon#flushed, iclass 38, count 2 2006.238.08:01:19.71#ibcon#about to write, iclass 38, count 2 2006.238.08:01:19.71#ibcon#wrote, iclass 38, count 2 2006.238.08:01:19.71#ibcon#about to read 3, iclass 38, count 2 2006.238.08:01:19.73#ibcon#read 3, iclass 38, count 2 2006.238.08:01:19.73#ibcon#about to read 4, iclass 38, count 2 2006.238.08:01:19.73#ibcon#read 4, iclass 38, count 2 2006.238.08:01:19.73#ibcon#about to read 5, iclass 38, count 2 2006.238.08:01:19.73#ibcon#read 5, iclass 38, count 2 2006.238.08:01:19.73#ibcon#about to read 6, iclass 38, count 2 2006.238.08:01:19.73#ibcon#read 6, iclass 38, count 2 2006.238.08:01:19.73#ibcon#end of sib2, iclass 38, count 2 2006.238.08:01:19.73#ibcon#*mode == 0, iclass 38, count 2 2006.238.08:01:19.73#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.238.08:01:19.73#ibcon#[25=AT06-07\r\n] 2006.238.08:01:19.73#ibcon#*before write, iclass 38, count 2 2006.238.08:01:19.73#ibcon#enter sib2, iclass 38, count 2 2006.238.08:01:19.73#ibcon#flushed, iclass 38, count 2 2006.238.08:01:19.73#ibcon#about to write, iclass 38, count 2 2006.238.08:01:19.73#ibcon#wrote, iclass 38, count 2 2006.238.08:01:19.73#ibcon#about to read 3, iclass 38, count 2 2006.238.08:01:19.76#ibcon#read 3, iclass 38, count 2 2006.238.08:01:19.76#ibcon#about to read 4, iclass 38, count 2 2006.238.08:01:19.76#ibcon#read 4, iclass 38, count 2 2006.238.08:01:19.76#ibcon#about to read 5, iclass 38, count 2 2006.238.08:01:19.76#ibcon#read 5, iclass 38, count 2 2006.238.08:01:19.76#ibcon#about to read 6, iclass 38, count 2 2006.238.08:01:19.76#ibcon#read 6, iclass 38, count 2 2006.238.08:01:19.76#ibcon#end of sib2, iclass 38, count 2 2006.238.08:01:19.76#ibcon#*after write, iclass 38, count 2 2006.238.08:01:19.76#ibcon#*before return 0, iclass 38, count 2 2006.238.08:01:19.76#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:01:19.76#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:01:19.76#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.238.08:01:19.76#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:19.76#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:01:19.88#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:01:19.88#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:01:19.88#ibcon#enter wrdev, iclass 38, count 0 2006.238.08:01:19.88#ibcon#first serial, iclass 38, count 0 2006.238.08:01:19.88#ibcon#enter sib2, iclass 38, count 0 2006.238.08:01:19.88#ibcon#flushed, iclass 38, count 0 2006.238.08:01:19.88#ibcon#about to write, iclass 38, count 0 2006.238.08:01:19.88#ibcon#wrote, iclass 38, count 0 2006.238.08:01:19.88#ibcon#about to read 3, iclass 38, count 0 2006.238.08:01:19.90#ibcon#read 3, iclass 38, count 0 2006.238.08:01:19.90#ibcon#about to read 4, iclass 38, count 0 2006.238.08:01:19.90#ibcon#read 4, iclass 38, count 0 2006.238.08:01:19.90#ibcon#about to read 5, iclass 38, count 0 2006.238.08:01:19.90#ibcon#read 5, iclass 38, count 0 2006.238.08:01:19.90#ibcon#about to read 6, iclass 38, count 0 2006.238.08:01:19.90#ibcon#read 6, iclass 38, count 0 2006.238.08:01:19.90#ibcon#end of sib2, iclass 38, count 0 2006.238.08:01:19.90#ibcon#*mode == 0, iclass 38, count 0 2006.238.08:01:19.90#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.08:01:19.90#ibcon#[25=USB\r\n] 2006.238.08:01:19.90#ibcon#*before write, iclass 38, count 0 2006.238.08:01:19.90#ibcon#enter sib2, iclass 38, count 0 2006.238.08:01:19.90#ibcon#flushed, iclass 38, count 0 2006.238.08:01:19.90#ibcon#about to write, iclass 38, count 0 2006.238.08:01:19.90#ibcon#wrote, iclass 38, count 0 2006.238.08:01:19.90#ibcon#about to read 3, iclass 38, count 0 2006.238.08:01:19.93#ibcon#read 3, iclass 38, count 0 2006.238.08:01:19.93#ibcon#about to read 4, iclass 38, count 0 2006.238.08:01:19.93#ibcon#read 4, iclass 38, count 0 2006.238.08:01:19.93#ibcon#about to read 5, iclass 38, count 0 2006.238.08:01:19.93#ibcon#read 5, iclass 38, count 0 2006.238.08:01:19.93#ibcon#about to read 6, iclass 38, count 0 2006.238.08:01:19.93#ibcon#read 6, iclass 38, count 0 2006.238.08:01:19.93#ibcon#end of sib2, iclass 38, count 0 2006.238.08:01:19.93#ibcon#*after write, iclass 38, count 0 2006.238.08:01:19.93#ibcon#*before return 0, iclass 38, count 0 2006.238.08:01:19.93#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:01:19.93#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:01:19.93#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.08:01:19.93#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.08:01:19.93$vc4f8/valo=7,832.99 2006.238.08:01:19.93#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.08:01:19.93#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.08:01:19.93#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:19.93#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:01:19.93#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:01:19.93#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:01:19.93#ibcon#enter wrdev, iclass 40, count 0 2006.238.08:01:19.93#ibcon#first serial, iclass 40, count 0 2006.238.08:01:19.93#ibcon#enter sib2, iclass 40, count 0 2006.238.08:01:19.93#ibcon#flushed, iclass 40, count 0 2006.238.08:01:19.93#ibcon#about to write, iclass 40, count 0 2006.238.08:01:19.93#ibcon#wrote, iclass 40, count 0 2006.238.08:01:19.93#ibcon#about to read 3, iclass 40, count 0 2006.238.08:01:19.95#ibcon#read 3, iclass 40, count 0 2006.238.08:01:19.95#ibcon#about to read 4, iclass 40, count 0 2006.238.08:01:19.95#ibcon#read 4, iclass 40, count 0 2006.238.08:01:19.95#ibcon#about to read 5, iclass 40, count 0 2006.238.08:01:19.95#ibcon#read 5, iclass 40, count 0 2006.238.08:01:19.95#ibcon#about to read 6, iclass 40, count 0 2006.238.08:01:19.95#ibcon#read 6, iclass 40, count 0 2006.238.08:01:19.95#ibcon#end of sib2, iclass 40, count 0 2006.238.08:01:19.95#ibcon#*mode == 0, iclass 40, count 0 2006.238.08:01:19.95#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.08:01:19.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:01:19.95#ibcon#*before write, iclass 40, count 0 2006.238.08:01:19.95#ibcon#enter sib2, iclass 40, count 0 2006.238.08:01:19.95#ibcon#flushed, iclass 40, count 0 2006.238.08:01:19.95#ibcon#about to write, iclass 40, count 0 2006.238.08:01:19.95#ibcon#wrote, iclass 40, count 0 2006.238.08:01:19.95#ibcon#about to read 3, iclass 40, count 0 2006.238.08:01:19.99#ibcon#read 3, iclass 40, count 0 2006.238.08:01:19.99#ibcon#about to read 4, iclass 40, count 0 2006.238.08:01:19.99#ibcon#read 4, iclass 40, count 0 2006.238.08:01:19.99#ibcon#about to read 5, iclass 40, count 0 2006.238.08:01:19.99#ibcon#read 5, iclass 40, count 0 2006.238.08:01:19.99#ibcon#about to read 6, iclass 40, count 0 2006.238.08:01:19.99#ibcon#read 6, iclass 40, count 0 2006.238.08:01:19.99#ibcon#end of sib2, iclass 40, count 0 2006.238.08:01:19.99#ibcon#*after write, iclass 40, count 0 2006.238.08:01:19.99#ibcon#*before return 0, iclass 40, count 0 2006.238.08:01:19.99#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:01:19.99#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:01:19.99#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.08:01:19.99#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.08:01:19.99$vc4f8/va=7,7 2006.238.08:01:19.99#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.238.08:01:19.99#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.238.08:01:19.99#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:19.99#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:01:20.05#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:01:20.05#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:01:20.05#ibcon#enter wrdev, iclass 4, count 2 2006.238.08:01:20.05#ibcon#first serial, iclass 4, count 2 2006.238.08:01:20.05#ibcon#enter sib2, iclass 4, count 2 2006.238.08:01:20.05#ibcon#flushed, iclass 4, count 2 2006.238.08:01:20.05#ibcon#about to write, iclass 4, count 2 2006.238.08:01:20.05#ibcon#wrote, iclass 4, count 2 2006.238.08:01:20.05#ibcon#about to read 3, iclass 4, count 2 2006.238.08:01:20.07#ibcon#read 3, iclass 4, count 2 2006.238.08:01:20.07#ibcon#about to read 4, iclass 4, count 2 2006.238.08:01:20.07#ibcon#read 4, iclass 4, count 2 2006.238.08:01:20.07#ibcon#about to read 5, iclass 4, count 2 2006.238.08:01:20.07#ibcon#read 5, iclass 4, count 2 2006.238.08:01:20.07#ibcon#about to read 6, iclass 4, count 2 2006.238.08:01:20.07#ibcon#read 6, iclass 4, count 2 2006.238.08:01:20.07#ibcon#end of sib2, iclass 4, count 2 2006.238.08:01:20.07#ibcon#*mode == 0, iclass 4, count 2 2006.238.08:01:20.07#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.238.08:01:20.07#ibcon#[25=AT07-07\r\n] 2006.238.08:01:20.07#ibcon#*before write, iclass 4, count 2 2006.238.08:01:20.07#ibcon#enter sib2, iclass 4, count 2 2006.238.08:01:20.07#ibcon#flushed, iclass 4, count 2 2006.238.08:01:20.07#ibcon#about to write, iclass 4, count 2 2006.238.08:01:20.07#ibcon#wrote, iclass 4, count 2 2006.238.08:01:20.07#ibcon#about to read 3, iclass 4, count 2 2006.238.08:01:20.10#ibcon#read 3, iclass 4, count 2 2006.238.08:01:20.10#ibcon#about to read 4, iclass 4, count 2 2006.238.08:01:20.10#ibcon#read 4, iclass 4, count 2 2006.238.08:01:20.10#ibcon#about to read 5, iclass 4, count 2 2006.238.08:01:20.10#ibcon#read 5, iclass 4, count 2 2006.238.08:01:20.10#ibcon#about to read 6, iclass 4, count 2 2006.238.08:01:20.10#ibcon#read 6, iclass 4, count 2 2006.238.08:01:20.10#ibcon#end of sib2, iclass 4, count 2 2006.238.08:01:20.10#ibcon#*after write, iclass 4, count 2 2006.238.08:01:20.10#ibcon#*before return 0, iclass 4, count 2 2006.238.08:01:20.10#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:01:20.10#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:01:20.10#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.238.08:01:20.10#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:20.10#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:01:20.22#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:01:20.22#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:01:20.22#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:01:20.22#ibcon#first serial, iclass 4, count 0 2006.238.08:01:20.22#ibcon#enter sib2, iclass 4, count 0 2006.238.08:01:20.22#ibcon#flushed, iclass 4, count 0 2006.238.08:01:20.22#ibcon#about to write, iclass 4, count 0 2006.238.08:01:20.22#ibcon#wrote, iclass 4, count 0 2006.238.08:01:20.22#ibcon#about to read 3, iclass 4, count 0 2006.238.08:01:20.24#ibcon#read 3, iclass 4, count 0 2006.238.08:01:20.24#ibcon#about to read 4, iclass 4, count 0 2006.238.08:01:20.24#ibcon#read 4, iclass 4, count 0 2006.238.08:01:20.24#ibcon#about to read 5, iclass 4, count 0 2006.238.08:01:20.24#ibcon#read 5, iclass 4, count 0 2006.238.08:01:20.24#ibcon#about to read 6, iclass 4, count 0 2006.238.08:01:20.24#ibcon#read 6, iclass 4, count 0 2006.238.08:01:20.24#ibcon#end of sib2, iclass 4, count 0 2006.238.08:01:20.24#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:01:20.24#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:01:20.24#ibcon#[25=USB\r\n] 2006.238.08:01:20.24#ibcon#*before write, iclass 4, count 0 2006.238.08:01:20.24#ibcon#enter sib2, iclass 4, count 0 2006.238.08:01:20.24#ibcon#flushed, iclass 4, count 0 2006.238.08:01:20.24#ibcon#about to write, iclass 4, count 0 2006.238.08:01:20.24#ibcon#wrote, iclass 4, count 0 2006.238.08:01:20.24#ibcon#about to read 3, iclass 4, count 0 2006.238.08:01:20.27#ibcon#read 3, iclass 4, count 0 2006.238.08:01:20.27#ibcon#about to read 4, iclass 4, count 0 2006.238.08:01:20.27#ibcon#read 4, iclass 4, count 0 2006.238.08:01:20.27#ibcon#about to read 5, iclass 4, count 0 2006.238.08:01:20.27#ibcon#read 5, iclass 4, count 0 2006.238.08:01:20.27#ibcon#about to read 6, iclass 4, count 0 2006.238.08:01:20.27#ibcon#read 6, iclass 4, count 0 2006.238.08:01:20.27#ibcon#end of sib2, iclass 4, count 0 2006.238.08:01:20.27#ibcon#*after write, iclass 4, count 0 2006.238.08:01:20.27#ibcon#*before return 0, iclass 4, count 0 2006.238.08:01:20.27#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:01:20.27#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:01:20.27#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:01:20.27#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:01:20.27$vc4f8/valo=8,852.99 2006.238.08:01:20.27#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.238.08:01:20.27#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.238.08:01:20.27#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:20.27#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:01:20.27#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:01:20.27#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:01:20.27#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:01:20.27#ibcon#first serial, iclass 6, count 0 2006.238.08:01:20.27#ibcon#enter sib2, iclass 6, count 0 2006.238.08:01:20.27#ibcon#flushed, iclass 6, count 0 2006.238.08:01:20.27#ibcon#about to write, iclass 6, count 0 2006.238.08:01:20.27#ibcon#wrote, iclass 6, count 0 2006.238.08:01:20.27#ibcon#about to read 3, iclass 6, count 0 2006.238.08:01:20.29#ibcon#read 3, iclass 6, count 0 2006.238.08:01:20.29#ibcon#about to read 4, iclass 6, count 0 2006.238.08:01:20.29#ibcon#read 4, iclass 6, count 0 2006.238.08:01:20.29#ibcon#about to read 5, iclass 6, count 0 2006.238.08:01:20.29#ibcon#read 5, iclass 6, count 0 2006.238.08:01:20.29#ibcon#about to read 6, iclass 6, count 0 2006.238.08:01:20.29#ibcon#read 6, iclass 6, count 0 2006.238.08:01:20.29#ibcon#end of sib2, iclass 6, count 0 2006.238.08:01:20.29#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:01:20.29#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:01:20.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:01:20.29#ibcon#*before write, iclass 6, count 0 2006.238.08:01:20.29#ibcon#enter sib2, iclass 6, count 0 2006.238.08:01:20.29#ibcon#flushed, iclass 6, count 0 2006.238.08:01:20.29#ibcon#about to write, iclass 6, count 0 2006.238.08:01:20.29#ibcon#wrote, iclass 6, count 0 2006.238.08:01:20.29#ibcon#about to read 3, iclass 6, count 0 2006.238.08:01:20.33#ibcon#read 3, iclass 6, count 0 2006.238.08:01:20.33#ibcon#about to read 4, iclass 6, count 0 2006.238.08:01:20.33#ibcon#read 4, iclass 6, count 0 2006.238.08:01:20.33#ibcon#about to read 5, iclass 6, count 0 2006.238.08:01:20.33#ibcon#read 5, iclass 6, count 0 2006.238.08:01:20.33#ibcon#about to read 6, iclass 6, count 0 2006.238.08:01:20.33#ibcon#read 6, iclass 6, count 0 2006.238.08:01:20.33#ibcon#end of sib2, iclass 6, count 0 2006.238.08:01:20.33#ibcon#*after write, iclass 6, count 0 2006.238.08:01:20.33#ibcon#*before return 0, iclass 6, count 0 2006.238.08:01:20.33#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:01:20.33#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:01:20.33#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:01:20.33#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:01:20.33$vc4f8/va=8,7 2006.238.08:01:20.33#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.238.08:01:20.33#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.238.08:01:20.33#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:20.33#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:01:20.39#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:01:20.39#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:01:20.39#ibcon#enter wrdev, iclass 10, count 2 2006.238.08:01:20.39#ibcon#first serial, iclass 10, count 2 2006.238.08:01:20.39#ibcon#enter sib2, iclass 10, count 2 2006.238.08:01:20.39#ibcon#flushed, iclass 10, count 2 2006.238.08:01:20.39#ibcon#about to write, iclass 10, count 2 2006.238.08:01:20.39#ibcon#wrote, iclass 10, count 2 2006.238.08:01:20.39#ibcon#about to read 3, iclass 10, count 2 2006.238.08:01:20.41#ibcon#read 3, iclass 10, count 2 2006.238.08:01:20.41#ibcon#about to read 4, iclass 10, count 2 2006.238.08:01:20.41#ibcon#read 4, iclass 10, count 2 2006.238.08:01:20.41#ibcon#about to read 5, iclass 10, count 2 2006.238.08:01:20.41#ibcon#read 5, iclass 10, count 2 2006.238.08:01:20.41#ibcon#about to read 6, iclass 10, count 2 2006.238.08:01:20.41#ibcon#read 6, iclass 10, count 2 2006.238.08:01:20.41#ibcon#end of sib2, iclass 10, count 2 2006.238.08:01:20.41#ibcon#*mode == 0, iclass 10, count 2 2006.238.08:01:20.41#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.238.08:01:20.41#ibcon#[25=AT08-07\r\n] 2006.238.08:01:20.41#ibcon#*before write, iclass 10, count 2 2006.238.08:01:20.41#ibcon#enter sib2, iclass 10, count 2 2006.238.08:01:20.41#ibcon#flushed, iclass 10, count 2 2006.238.08:01:20.41#ibcon#about to write, iclass 10, count 2 2006.238.08:01:20.41#ibcon#wrote, iclass 10, count 2 2006.238.08:01:20.41#ibcon#about to read 3, iclass 10, count 2 2006.238.08:01:20.44#ibcon#read 3, iclass 10, count 2 2006.238.08:01:20.44#ibcon#about to read 4, iclass 10, count 2 2006.238.08:01:20.44#ibcon#read 4, iclass 10, count 2 2006.238.08:01:20.44#ibcon#about to read 5, iclass 10, count 2 2006.238.08:01:20.44#ibcon#read 5, iclass 10, count 2 2006.238.08:01:20.44#ibcon#about to read 6, iclass 10, count 2 2006.238.08:01:20.44#ibcon#read 6, iclass 10, count 2 2006.238.08:01:20.44#ibcon#end of sib2, iclass 10, count 2 2006.238.08:01:20.44#ibcon#*after write, iclass 10, count 2 2006.238.08:01:20.44#ibcon#*before return 0, iclass 10, count 2 2006.238.08:01:20.44#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:01:20.44#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:01:20.44#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.238.08:01:20.44#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:20.44#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:01:20.56#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:01:20.56#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:01:20.56#ibcon#enter wrdev, iclass 10, count 0 2006.238.08:01:20.56#ibcon#first serial, iclass 10, count 0 2006.238.08:01:20.56#ibcon#enter sib2, iclass 10, count 0 2006.238.08:01:20.56#ibcon#flushed, iclass 10, count 0 2006.238.08:01:20.56#ibcon#about to write, iclass 10, count 0 2006.238.08:01:20.56#ibcon#wrote, iclass 10, count 0 2006.238.08:01:20.56#ibcon#about to read 3, iclass 10, count 0 2006.238.08:01:20.58#ibcon#read 3, iclass 10, count 0 2006.238.08:01:20.58#ibcon#about to read 4, iclass 10, count 0 2006.238.08:01:20.58#ibcon#read 4, iclass 10, count 0 2006.238.08:01:20.58#ibcon#about to read 5, iclass 10, count 0 2006.238.08:01:20.58#ibcon#read 5, iclass 10, count 0 2006.238.08:01:20.58#ibcon#about to read 6, iclass 10, count 0 2006.238.08:01:20.58#ibcon#read 6, iclass 10, count 0 2006.238.08:01:20.58#ibcon#end of sib2, iclass 10, count 0 2006.238.08:01:20.58#ibcon#*mode == 0, iclass 10, count 0 2006.238.08:01:20.58#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.08:01:20.58#ibcon#[25=USB\r\n] 2006.238.08:01:20.58#ibcon#*before write, iclass 10, count 0 2006.238.08:01:20.58#ibcon#enter sib2, iclass 10, count 0 2006.238.08:01:20.58#ibcon#flushed, iclass 10, count 0 2006.238.08:01:20.58#ibcon#about to write, iclass 10, count 0 2006.238.08:01:20.58#ibcon#wrote, iclass 10, count 0 2006.238.08:01:20.58#ibcon#about to read 3, iclass 10, count 0 2006.238.08:01:20.61#ibcon#read 3, iclass 10, count 0 2006.238.08:01:20.61#ibcon#about to read 4, iclass 10, count 0 2006.238.08:01:20.61#ibcon#read 4, iclass 10, count 0 2006.238.08:01:20.61#ibcon#about to read 5, iclass 10, count 0 2006.238.08:01:20.61#ibcon#read 5, iclass 10, count 0 2006.238.08:01:20.61#ibcon#about to read 6, iclass 10, count 0 2006.238.08:01:20.61#ibcon#read 6, iclass 10, count 0 2006.238.08:01:20.61#ibcon#end of sib2, iclass 10, count 0 2006.238.08:01:20.61#ibcon#*after write, iclass 10, count 0 2006.238.08:01:20.61#ibcon#*before return 0, iclass 10, count 0 2006.238.08:01:20.61#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:01:20.61#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:01:20.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.08:01:20.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.08:01:20.61$vc4f8/vblo=1,632.99 2006.238.08:01:20.61#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.238.08:01:20.61#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.238.08:01:20.61#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:20.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:01:20.61#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:01:20.61#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:01:20.61#ibcon#enter wrdev, iclass 12, count 0 2006.238.08:01:20.61#ibcon#first serial, iclass 12, count 0 2006.238.08:01:20.61#ibcon#enter sib2, iclass 12, count 0 2006.238.08:01:20.61#ibcon#flushed, iclass 12, count 0 2006.238.08:01:20.61#ibcon#about to write, iclass 12, count 0 2006.238.08:01:20.61#ibcon#wrote, iclass 12, count 0 2006.238.08:01:20.61#ibcon#about to read 3, iclass 12, count 0 2006.238.08:01:20.63#ibcon#read 3, iclass 12, count 0 2006.238.08:01:20.63#ibcon#about to read 4, iclass 12, count 0 2006.238.08:01:20.63#ibcon#read 4, iclass 12, count 0 2006.238.08:01:20.63#ibcon#about to read 5, iclass 12, count 0 2006.238.08:01:20.63#ibcon#read 5, iclass 12, count 0 2006.238.08:01:20.63#ibcon#about to read 6, iclass 12, count 0 2006.238.08:01:20.63#ibcon#read 6, iclass 12, count 0 2006.238.08:01:20.63#ibcon#end of sib2, iclass 12, count 0 2006.238.08:01:20.63#ibcon#*mode == 0, iclass 12, count 0 2006.238.08:01:20.63#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.08:01:20.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:01:20.63#ibcon#*before write, iclass 12, count 0 2006.238.08:01:20.63#ibcon#enter sib2, iclass 12, count 0 2006.238.08:01:20.63#ibcon#flushed, iclass 12, count 0 2006.238.08:01:20.63#ibcon#about to write, iclass 12, count 0 2006.238.08:01:20.63#ibcon#wrote, iclass 12, count 0 2006.238.08:01:20.63#ibcon#about to read 3, iclass 12, count 0 2006.238.08:01:20.67#ibcon#read 3, iclass 12, count 0 2006.238.08:01:20.67#ibcon#about to read 4, iclass 12, count 0 2006.238.08:01:20.67#ibcon#read 4, iclass 12, count 0 2006.238.08:01:20.67#ibcon#about to read 5, iclass 12, count 0 2006.238.08:01:20.67#ibcon#read 5, iclass 12, count 0 2006.238.08:01:20.67#ibcon#about to read 6, iclass 12, count 0 2006.238.08:01:20.67#ibcon#read 6, iclass 12, count 0 2006.238.08:01:20.67#ibcon#end of sib2, iclass 12, count 0 2006.238.08:01:20.67#ibcon#*after write, iclass 12, count 0 2006.238.08:01:20.67#ibcon#*before return 0, iclass 12, count 0 2006.238.08:01:20.67#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:01:20.67#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:01:20.67#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.08:01:20.67#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.08:01:20.67$vc4f8/vb=1,4 2006.238.08:01:20.67#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.238.08:01:20.67#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.238.08:01:20.67#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:20.67#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:01:20.67#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:01:20.67#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:01:20.67#ibcon#enter wrdev, iclass 14, count 2 2006.238.08:01:20.67#ibcon#first serial, iclass 14, count 2 2006.238.08:01:20.67#ibcon#enter sib2, iclass 14, count 2 2006.238.08:01:20.67#ibcon#flushed, iclass 14, count 2 2006.238.08:01:20.67#ibcon#about to write, iclass 14, count 2 2006.238.08:01:20.67#ibcon#wrote, iclass 14, count 2 2006.238.08:01:20.67#ibcon#about to read 3, iclass 14, count 2 2006.238.08:01:20.69#ibcon#read 3, iclass 14, count 2 2006.238.08:01:20.69#ibcon#about to read 4, iclass 14, count 2 2006.238.08:01:20.69#ibcon#read 4, iclass 14, count 2 2006.238.08:01:20.69#ibcon#about to read 5, iclass 14, count 2 2006.238.08:01:20.69#ibcon#read 5, iclass 14, count 2 2006.238.08:01:20.69#ibcon#about to read 6, iclass 14, count 2 2006.238.08:01:20.69#ibcon#read 6, iclass 14, count 2 2006.238.08:01:20.69#ibcon#end of sib2, iclass 14, count 2 2006.238.08:01:20.69#ibcon#*mode == 0, iclass 14, count 2 2006.238.08:01:20.69#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.238.08:01:20.69#ibcon#[27=AT01-04\r\n] 2006.238.08:01:20.69#ibcon#*before write, iclass 14, count 2 2006.238.08:01:20.69#ibcon#enter sib2, iclass 14, count 2 2006.238.08:01:20.69#ibcon#flushed, iclass 14, count 2 2006.238.08:01:20.69#ibcon#about to write, iclass 14, count 2 2006.238.08:01:20.69#ibcon#wrote, iclass 14, count 2 2006.238.08:01:20.69#ibcon#about to read 3, iclass 14, count 2 2006.238.08:01:20.72#ibcon#read 3, iclass 14, count 2 2006.238.08:01:20.72#ibcon#about to read 4, iclass 14, count 2 2006.238.08:01:20.72#ibcon#read 4, iclass 14, count 2 2006.238.08:01:20.72#ibcon#about to read 5, iclass 14, count 2 2006.238.08:01:20.72#ibcon#read 5, iclass 14, count 2 2006.238.08:01:20.72#ibcon#about to read 6, iclass 14, count 2 2006.238.08:01:20.72#ibcon#read 6, iclass 14, count 2 2006.238.08:01:20.72#ibcon#end of sib2, iclass 14, count 2 2006.238.08:01:20.72#ibcon#*after write, iclass 14, count 2 2006.238.08:01:20.72#ibcon#*before return 0, iclass 14, count 2 2006.238.08:01:20.72#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:01:20.72#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:01:20.72#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.238.08:01:20.72#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:20.72#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:01:20.84#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:01:20.84#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:01:20.84#ibcon#enter wrdev, iclass 14, count 0 2006.238.08:01:20.84#ibcon#first serial, iclass 14, count 0 2006.238.08:01:20.84#ibcon#enter sib2, iclass 14, count 0 2006.238.08:01:20.84#ibcon#flushed, iclass 14, count 0 2006.238.08:01:20.84#ibcon#about to write, iclass 14, count 0 2006.238.08:01:20.84#ibcon#wrote, iclass 14, count 0 2006.238.08:01:20.84#ibcon#about to read 3, iclass 14, count 0 2006.238.08:01:20.86#ibcon#read 3, iclass 14, count 0 2006.238.08:01:20.86#ibcon#about to read 4, iclass 14, count 0 2006.238.08:01:20.86#ibcon#read 4, iclass 14, count 0 2006.238.08:01:20.86#ibcon#about to read 5, iclass 14, count 0 2006.238.08:01:20.86#ibcon#read 5, iclass 14, count 0 2006.238.08:01:20.86#ibcon#about to read 6, iclass 14, count 0 2006.238.08:01:20.86#ibcon#read 6, iclass 14, count 0 2006.238.08:01:20.86#ibcon#end of sib2, iclass 14, count 0 2006.238.08:01:20.86#ibcon#*mode == 0, iclass 14, count 0 2006.238.08:01:20.86#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.08:01:20.86#ibcon#[27=USB\r\n] 2006.238.08:01:20.86#ibcon#*before write, iclass 14, count 0 2006.238.08:01:20.86#ibcon#enter sib2, iclass 14, count 0 2006.238.08:01:20.86#ibcon#flushed, iclass 14, count 0 2006.238.08:01:20.86#ibcon#about to write, iclass 14, count 0 2006.238.08:01:20.86#ibcon#wrote, iclass 14, count 0 2006.238.08:01:20.86#ibcon#about to read 3, iclass 14, count 0 2006.238.08:01:20.89#ibcon#read 3, iclass 14, count 0 2006.238.08:01:20.89#ibcon#about to read 4, iclass 14, count 0 2006.238.08:01:20.89#ibcon#read 4, iclass 14, count 0 2006.238.08:01:20.89#ibcon#about to read 5, iclass 14, count 0 2006.238.08:01:20.89#ibcon#read 5, iclass 14, count 0 2006.238.08:01:20.89#ibcon#about to read 6, iclass 14, count 0 2006.238.08:01:20.89#ibcon#read 6, iclass 14, count 0 2006.238.08:01:20.89#ibcon#end of sib2, iclass 14, count 0 2006.238.08:01:20.89#ibcon#*after write, iclass 14, count 0 2006.238.08:01:20.89#ibcon#*before return 0, iclass 14, count 0 2006.238.08:01:20.89#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:01:20.89#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:01:20.89#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.08:01:20.89#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.08:01:20.89$vc4f8/vblo=2,640.99 2006.238.08:01:20.89#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.08:01:20.89#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.08:01:20.89#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:20.89#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:01:20.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:01:20.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:01:20.89#ibcon#enter wrdev, iclass 16, count 0 2006.238.08:01:20.89#ibcon#first serial, iclass 16, count 0 2006.238.08:01:20.89#ibcon#enter sib2, iclass 16, count 0 2006.238.08:01:20.89#ibcon#flushed, iclass 16, count 0 2006.238.08:01:20.89#ibcon#about to write, iclass 16, count 0 2006.238.08:01:20.89#ibcon#wrote, iclass 16, count 0 2006.238.08:01:20.89#ibcon#about to read 3, iclass 16, count 0 2006.238.08:01:20.91#ibcon#read 3, iclass 16, count 0 2006.238.08:01:20.91#ibcon#about to read 4, iclass 16, count 0 2006.238.08:01:20.91#ibcon#read 4, iclass 16, count 0 2006.238.08:01:20.91#ibcon#about to read 5, iclass 16, count 0 2006.238.08:01:20.91#ibcon#read 5, iclass 16, count 0 2006.238.08:01:20.91#ibcon#about to read 6, iclass 16, count 0 2006.238.08:01:20.91#ibcon#read 6, iclass 16, count 0 2006.238.08:01:20.91#ibcon#end of sib2, iclass 16, count 0 2006.238.08:01:20.91#ibcon#*mode == 0, iclass 16, count 0 2006.238.08:01:20.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.08:01:20.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:01:20.91#ibcon#*before write, iclass 16, count 0 2006.238.08:01:20.91#ibcon#enter sib2, iclass 16, count 0 2006.238.08:01:20.91#ibcon#flushed, iclass 16, count 0 2006.238.08:01:20.91#ibcon#about to write, iclass 16, count 0 2006.238.08:01:20.91#ibcon#wrote, iclass 16, count 0 2006.238.08:01:20.91#ibcon#about to read 3, iclass 16, count 0 2006.238.08:01:20.95#ibcon#read 3, iclass 16, count 0 2006.238.08:01:20.95#ibcon#about to read 4, iclass 16, count 0 2006.238.08:01:20.95#ibcon#read 4, iclass 16, count 0 2006.238.08:01:20.95#ibcon#about to read 5, iclass 16, count 0 2006.238.08:01:20.95#ibcon#read 5, iclass 16, count 0 2006.238.08:01:20.95#ibcon#about to read 6, iclass 16, count 0 2006.238.08:01:20.95#ibcon#read 6, iclass 16, count 0 2006.238.08:01:20.95#ibcon#end of sib2, iclass 16, count 0 2006.238.08:01:20.95#ibcon#*after write, iclass 16, count 0 2006.238.08:01:20.95#ibcon#*before return 0, iclass 16, count 0 2006.238.08:01:20.95#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:01:20.95#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:01:20.95#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.08:01:20.95#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.08:01:20.95$vc4f8/vb=2,4 2006.238.08:01:20.95#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.238.08:01:20.95#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.238.08:01:20.95#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:20.95#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:01:21.01#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:01:21.01#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:01:21.01#ibcon#enter wrdev, iclass 18, count 2 2006.238.08:01:21.01#ibcon#first serial, iclass 18, count 2 2006.238.08:01:21.01#ibcon#enter sib2, iclass 18, count 2 2006.238.08:01:21.01#ibcon#flushed, iclass 18, count 2 2006.238.08:01:21.01#ibcon#about to write, iclass 18, count 2 2006.238.08:01:21.01#ibcon#wrote, iclass 18, count 2 2006.238.08:01:21.01#ibcon#about to read 3, iclass 18, count 2 2006.238.08:01:21.03#ibcon#read 3, iclass 18, count 2 2006.238.08:01:21.03#ibcon#about to read 4, iclass 18, count 2 2006.238.08:01:21.03#ibcon#read 4, iclass 18, count 2 2006.238.08:01:21.03#ibcon#about to read 5, iclass 18, count 2 2006.238.08:01:21.03#ibcon#read 5, iclass 18, count 2 2006.238.08:01:21.03#ibcon#about to read 6, iclass 18, count 2 2006.238.08:01:21.03#ibcon#read 6, iclass 18, count 2 2006.238.08:01:21.03#ibcon#end of sib2, iclass 18, count 2 2006.238.08:01:21.03#ibcon#*mode == 0, iclass 18, count 2 2006.238.08:01:21.03#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.238.08:01:21.03#ibcon#[27=AT02-04\r\n] 2006.238.08:01:21.03#ibcon#*before write, iclass 18, count 2 2006.238.08:01:21.03#ibcon#enter sib2, iclass 18, count 2 2006.238.08:01:21.03#ibcon#flushed, iclass 18, count 2 2006.238.08:01:21.03#ibcon#about to write, iclass 18, count 2 2006.238.08:01:21.03#ibcon#wrote, iclass 18, count 2 2006.238.08:01:21.03#ibcon#about to read 3, iclass 18, count 2 2006.238.08:01:21.06#ibcon#read 3, iclass 18, count 2 2006.238.08:01:21.06#ibcon#about to read 4, iclass 18, count 2 2006.238.08:01:21.06#ibcon#read 4, iclass 18, count 2 2006.238.08:01:21.06#ibcon#about to read 5, iclass 18, count 2 2006.238.08:01:21.06#ibcon#read 5, iclass 18, count 2 2006.238.08:01:21.06#ibcon#about to read 6, iclass 18, count 2 2006.238.08:01:21.06#ibcon#read 6, iclass 18, count 2 2006.238.08:01:21.06#ibcon#end of sib2, iclass 18, count 2 2006.238.08:01:21.06#ibcon#*after write, iclass 18, count 2 2006.238.08:01:21.06#ibcon#*before return 0, iclass 18, count 2 2006.238.08:01:21.06#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:01:21.06#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:01:21.06#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.238.08:01:21.06#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:21.06#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:01:21.18#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:01:21.18#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:01:21.18#ibcon#enter wrdev, iclass 18, count 0 2006.238.08:01:21.18#ibcon#first serial, iclass 18, count 0 2006.238.08:01:21.18#ibcon#enter sib2, iclass 18, count 0 2006.238.08:01:21.18#ibcon#flushed, iclass 18, count 0 2006.238.08:01:21.18#ibcon#about to write, iclass 18, count 0 2006.238.08:01:21.18#ibcon#wrote, iclass 18, count 0 2006.238.08:01:21.18#ibcon#about to read 3, iclass 18, count 0 2006.238.08:01:21.20#ibcon#read 3, iclass 18, count 0 2006.238.08:01:21.20#ibcon#about to read 4, iclass 18, count 0 2006.238.08:01:21.20#ibcon#read 4, iclass 18, count 0 2006.238.08:01:21.20#ibcon#about to read 5, iclass 18, count 0 2006.238.08:01:21.20#ibcon#read 5, iclass 18, count 0 2006.238.08:01:21.20#ibcon#about to read 6, iclass 18, count 0 2006.238.08:01:21.20#ibcon#read 6, iclass 18, count 0 2006.238.08:01:21.20#ibcon#end of sib2, iclass 18, count 0 2006.238.08:01:21.20#ibcon#*mode == 0, iclass 18, count 0 2006.238.08:01:21.20#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.08:01:21.20#ibcon#[27=USB\r\n] 2006.238.08:01:21.20#ibcon#*before write, iclass 18, count 0 2006.238.08:01:21.20#ibcon#enter sib2, iclass 18, count 0 2006.238.08:01:21.20#ibcon#flushed, iclass 18, count 0 2006.238.08:01:21.20#ibcon#about to write, iclass 18, count 0 2006.238.08:01:21.20#ibcon#wrote, iclass 18, count 0 2006.238.08:01:21.20#ibcon#about to read 3, iclass 18, count 0 2006.238.08:01:21.23#ibcon#read 3, iclass 18, count 0 2006.238.08:01:21.23#ibcon#about to read 4, iclass 18, count 0 2006.238.08:01:21.23#ibcon#read 4, iclass 18, count 0 2006.238.08:01:21.23#ibcon#about to read 5, iclass 18, count 0 2006.238.08:01:21.23#ibcon#read 5, iclass 18, count 0 2006.238.08:01:21.23#ibcon#about to read 6, iclass 18, count 0 2006.238.08:01:21.23#ibcon#read 6, iclass 18, count 0 2006.238.08:01:21.23#ibcon#end of sib2, iclass 18, count 0 2006.238.08:01:21.23#ibcon#*after write, iclass 18, count 0 2006.238.08:01:21.23#ibcon#*before return 0, iclass 18, count 0 2006.238.08:01:21.23#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:01:21.23#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:01:21.23#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.08:01:21.23#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.08:01:21.23$vc4f8/vblo=3,656.99 2006.238.08:01:21.23#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.08:01:21.23#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.08:01:21.23#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:21.23#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:01:21.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:01:21.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:01:21.23#ibcon#enter wrdev, iclass 20, count 0 2006.238.08:01:21.23#ibcon#first serial, iclass 20, count 0 2006.238.08:01:21.23#ibcon#enter sib2, iclass 20, count 0 2006.238.08:01:21.23#ibcon#flushed, iclass 20, count 0 2006.238.08:01:21.23#ibcon#about to write, iclass 20, count 0 2006.238.08:01:21.23#ibcon#wrote, iclass 20, count 0 2006.238.08:01:21.23#ibcon#about to read 3, iclass 20, count 0 2006.238.08:01:21.25#ibcon#read 3, iclass 20, count 0 2006.238.08:01:21.25#ibcon#about to read 4, iclass 20, count 0 2006.238.08:01:21.25#ibcon#read 4, iclass 20, count 0 2006.238.08:01:21.25#ibcon#about to read 5, iclass 20, count 0 2006.238.08:01:21.25#ibcon#read 5, iclass 20, count 0 2006.238.08:01:21.25#ibcon#about to read 6, iclass 20, count 0 2006.238.08:01:21.25#ibcon#read 6, iclass 20, count 0 2006.238.08:01:21.25#ibcon#end of sib2, iclass 20, count 0 2006.238.08:01:21.25#ibcon#*mode == 0, iclass 20, count 0 2006.238.08:01:21.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.08:01:21.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:01:21.25#ibcon#*before write, iclass 20, count 0 2006.238.08:01:21.25#ibcon#enter sib2, iclass 20, count 0 2006.238.08:01:21.25#ibcon#flushed, iclass 20, count 0 2006.238.08:01:21.25#ibcon#about to write, iclass 20, count 0 2006.238.08:01:21.25#ibcon#wrote, iclass 20, count 0 2006.238.08:01:21.25#ibcon#about to read 3, iclass 20, count 0 2006.238.08:01:21.29#ibcon#read 3, iclass 20, count 0 2006.238.08:01:21.29#ibcon#about to read 4, iclass 20, count 0 2006.238.08:01:21.29#ibcon#read 4, iclass 20, count 0 2006.238.08:01:21.29#ibcon#about to read 5, iclass 20, count 0 2006.238.08:01:21.29#ibcon#read 5, iclass 20, count 0 2006.238.08:01:21.29#ibcon#about to read 6, iclass 20, count 0 2006.238.08:01:21.29#ibcon#read 6, iclass 20, count 0 2006.238.08:01:21.29#ibcon#end of sib2, iclass 20, count 0 2006.238.08:01:21.29#ibcon#*after write, iclass 20, count 0 2006.238.08:01:21.29#ibcon#*before return 0, iclass 20, count 0 2006.238.08:01:21.29#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:01:21.29#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:01:21.29#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.08:01:21.29#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.08:01:21.29$vc4f8/vb=3,4 2006.238.08:01:21.29#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.238.08:01:21.29#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.238.08:01:21.29#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:21.29#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:01:21.35#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:01:21.35#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:01:21.35#ibcon#enter wrdev, iclass 22, count 2 2006.238.08:01:21.35#ibcon#first serial, iclass 22, count 2 2006.238.08:01:21.35#ibcon#enter sib2, iclass 22, count 2 2006.238.08:01:21.35#ibcon#flushed, iclass 22, count 2 2006.238.08:01:21.35#ibcon#about to write, iclass 22, count 2 2006.238.08:01:21.35#ibcon#wrote, iclass 22, count 2 2006.238.08:01:21.35#ibcon#about to read 3, iclass 22, count 2 2006.238.08:01:21.37#ibcon#read 3, iclass 22, count 2 2006.238.08:01:21.37#ibcon#about to read 4, iclass 22, count 2 2006.238.08:01:21.37#ibcon#read 4, iclass 22, count 2 2006.238.08:01:21.37#ibcon#about to read 5, iclass 22, count 2 2006.238.08:01:21.37#ibcon#read 5, iclass 22, count 2 2006.238.08:01:21.37#ibcon#about to read 6, iclass 22, count 2 2006.238.08:01:21.37#ibcon#read 6, iclass 22, count 2 2006.238.08:01:21.37#ibcon#end of sib2, iclass 22, count 2 2006.238.08:01:21.37#ibcon#*mode == 0, iclass 22, count 2 2006.238.08:01:21.37#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.238.08:01:21.37#ibcon#[27=AT03-04\r\n] 2006.238.08:01:21.37#ibcon#*before write, iclass 22, count 2 2006.238.08:01:21.37#ibcon#enter sib2, iclass 22, count 2 2006.238.08:01:21.37#ibcon#flushed, iclass 22, count 2 2006.238.08:01:21.37#ibcon#about to write, iclass 22, count 2 2006.238.08:01:21.37#ibcon#wrote, iclass 22, count 2 2006.238.08:01:21.37#ibcon#about to read 3, iclass 22, count 2 2006.238.08:01:21.40#ibcon#read 3, iclass 22, count 2 2006.238.08:01:21.40#ibcon#about to read 4, iclass 22, count 2 2006.238.08:01:21.40#ibcon#read 4, iclass 22, count 2 2006.238.08:01:21.40#ibcon#about to read 5, iclass 22, count 2 2006.238.08:01:21.40#ibcon#read 5, iclass 22, count 2 2006.238.08:01:21.40#ibcon#about to read 6, iclass 22, count 2 2006.238.08:01:21.40#ibcon#read 6, iclass 22, count 2 2006.238.08:01:21.40#ibcon#end of sib2, iclass 22, count 2 2006.238.08:01:21.40#ibcon#*after write, iclass 22, count 2 2006.238.08:01:21.40#ibcon#*before return 0, iclass 22, count 2 2006.238.08:01:21.40#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:01:21.40#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:01:21.40#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.238.08:01:21.40#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:21.40#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:01:21.52#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:01:21.52#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:01:21.52#ibcon#enter wrdev, iclass 22, count 0 2006.238.08:01:21.52#ibcon#first serial, iclass 22, count 0 2006.238.08:01:21.52#ibcon#enter sib2, iclass 22, count 0 2006.238.08:01:21.52#ibcon#flushed, iclass 22, count 0 2006.238.08:01:21.52#ibcon#about to write, iclass 22, count 0 2006.238.08:01:21.52#ibcon#wrote, iclass 22, count 0 2006.238.08:01:21.52#ibcon#about to read 3, iclass 22, count 0 2006.238.08:01:21.54#ibcon#read 3, iclass 22, count 0 2006.238.08:01:21.54#ibcon#about to read 4, iclass 22, count 0 2006.238.08:01:21.54#ibcon#read 4, iclass 22, count 0 2006.238.08:01:21.54#ibcon#about to read 5, iclass 22, count 0 2006.238.08:01:21.54#ibcon#read 5, iclass 22, count 0 2006.238.08:01:21.54#ibcon#about to read 6, iclass 22, count 0 2006.238.08:01:21.54#ibcon#read 6, iclass 22, count 0 2006.238.08:01:21.54#ibcon#end of sib2, iclass 22, count 0 2006.238.08:01:21.54#ibcon#*mode == 0, iclass 22, count 0 2006.238.08:01:21.54#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.08:01:21.54#ibcon#[27=USB\r\n] 2006.238.08:01:21.54#ibcon#*before write, iclass 22, count 0 2006.238.08:01:21.54#ibcon#enter sib2, iclass 22, count 0 2006.238.08:01:21.54#ibcon#flushed, iclass 22, count 0 2006.238.08:01:21.54#ibcon#about to write, iclass 22, count 0 2006.238.08:01:21.54#ibcon#wrote, iclass 22, count 0 2006.238.08:01:21.54#ibcon#about to read 3, iclass 22, count 0 2006.238.08:01:21.57#ibcon#read 3, iclass 22, count 0 2006.238.08:01:21.57#ibcon#about to read 4, iclass 22, count 0 2006.238.08:01:21.57#ibcon#read 4, iclass 22, count 0 2006.238.08:01:21.57#ibcon#about to read 5, iclass 22, count 0 2006.238.08:01:21.57#ibcon#read 5, iclass 22, count 0 2006.238.08:01:21.57#ibcon#about to read 6, iclass 22, count 0 2006.238.08:01:21.57#ibcon#read 6, iclass 22, count 0 2006.238.08:01:21.57#ibcon#end of sib2, iclass 22, count 0 2006.238.08:01:21.57#ibcon#*after write, iclass 22, count 0 2006.238.08:01:21.57#ibcon#*before return 0, iclass 22, count 0 2006.238.08:01:21.57#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:01:21.57#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:01:21.57#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.08:01:21.57#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.08:01:21.57$vc4f8/vblo=4,712.99 2006.238.08:01:21.57#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.08:01:21.57#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.08:01:21.57#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:21.57#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:01:21.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:01:21.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:01:21.57#ibcon#enter wrdev, iclass 24, count 0 2006.238.08:01:21.57#ibcon#first serial, iclass 24, count 0 2006.238.08:01:21.57#ibcon#enter sib2, iclass 24, count 0 2006.238.08:01:21.57#ibcon#flushed, iclass 24, count 0 2006.238.08:01:21.57#ibcon#about to write, iclass 24, count 0 2006.238.08:01:21.57#ibcon#wrote, iclass 24, count 0 2006.238.08:01:21.57#ibcon#about to read 3, iclass 24, count 0 2006.238.08:01:21.59#ibcon#read 3, iclass 24, count 0 2006.238.08:01:21.59#ibcon#about to read 4, iclass 24, count 0 2006.238.08:01:21.59#ibcon#read 4, iclass 24, count 0 2006.238.08:01:21.59#ibcon#about to read 5, iclass 24, count 0 2006.238.08:01:21.59#ibcon#read 5, iclass 24, count 0 2006.238.08:01:21.59#ibcon#about to read 6, iclass 24, count 0 2006.238.08:01:21.59#ibcon#read 6, iclass 24, count 0 2006.238.08:01:21.59#ibcon#end of sib2, iclass 24, count 0 2006.238.08:01:21.59#ibcon#*mode == 0, iclass 24, count 0 2006.238.08:01:21.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.08:01:21.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:01:21.59#ibcon#*before write, iclass 24, count 0 2006.238.08:01:21.59#ibcon#enter sib2, iclass 24, count 0 2006.238.08:01:21.59#ibcon#flushed, iclass 24, count 0 2006.238.08:01:21.59#ibcon#about to write, iclass 24, count 0 2006.238.08:01:21.59#ibcon#wrote, iclass 24, count 0 2006.238.08:01:21.59#ibcon#about to read 3, iclass 24, count 0 2006.238.08:01:21.63#ibcon#read 3, iclass 24, count 0 2006.238.08:01:21.63#ibcon#about to read 4, iclass 24, count 0 2006.238.08:01:21.63#ibcon#read 4, iclass 24, count 0 2006.238.08:01:21.63#ibcon#about to read 5, iclass 24, count 0 2006.238.08:01:21.63#ibcon#read 5, iclass 24, count 0 2006.238.08:01:21.63#ibcon#about to read 6, iclass 24, count 0 2006.238.08:01:21.63#ibcon#read 6, iclass 24, count 0 2006.238.08:01:21.63#ibcon#end of sib2, iclass 24, count 0 2006.238.08:01:21.63#ibcon#*after write, iclass 24, count 0 2006.238.08:01:21.63#ibcon#*before return 0, iclass 24, count 0 2006.238.08:01:21.63#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:01:21.63#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:01:21.63#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.08:01:21.63#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.08:01:21.63$vc4f8/vb=4,4 2006.238.08:01:21.63#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.238.08:01:21.63#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.238.08:01:21.63#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:21.63#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:01:21.69#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:01:21.69#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:01:21.69#ibcon#enter wrdev, iclass 26, count 2 2006.238.08:01:21.69#ibcon#first serial, iclass 26, count 2 2006.238.08:01:21.69#ibcon#enter sib2, iclass 26, count 2 2006.238.08:01:21.69#ibcon#flushed, iclass 26, count 2 2006.238.08:01:21.69#ibcon#about to write, iclass 26, count 2 2006.238.08:01:21.69#ibcon#wrote, iclass 26, count 2 2006.238.08:01:21.69#ibcon#about to read 3, iclass 26, count 2 2006.238.08:01:21.71#ibcon#read 3, iclass 26, count 2 2006.238.08:01:21.71#ibcon#about to read 4, iclass 26, count 2 2006.238.08:01:21.71#ibcon#read 4, iclass 26, count 2 2006.238.08:01:21.71#ibcon#about to read 5, iclass 26, count 2 2006.238.08:01:21.71#ibcon#read 5, iclass 26, count 2 2006.238.08:01:21.71#ibcon#about to read 6, iclass 26, count 2 2006.238.08:01:21.71#ibcon#read 6, iclass 26, count 2 2006.238.08:01:21.71#ibcon#end of sib2, iclass 26, count 2 2006.238.08:01:21.71#ibcon#*mode == 0, iclass 26, count 2 2006.238.08:01:21.71#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.238.08:01:21.71#ibcon#[27=AT04-04\r\n] 2006.238.08:01:21.71#ibcon#*before write, iclass 26, count 2 2006.238.08:01:21.71#ibcon#enter sib2, iclass 26, count 2 2006.238.08:01:21.71#ibcon#flushed, iclass 26, count 2 2006.238.08:01:21.71#ibcon#about to write, iclass 26, count 2 2006.238.08:01:21.71#ibcon#wrote, iclass 26, count 2 2006.238.08:01:21.71#ibcon#about to read 3, iclass 26, count 2 2006.238.08:01:21.74#ibcon#read 3, iclass 26, count 2 2006.238.08:01:21.74#ibcon#about to read 4, iclass 26, count 2 2006.238.08:01:21.74#ibcon#read 4, iclass 26, count 2 2006.238.08:01:21.74#ibcon#about to read 5, iclass 26, count 2 2006.238.08:01:21.74#ibcon#read 5, iclass 26, count 2 2006.238.08:01:21.74#ibcon#about to read 6, iclass 26, count 2 2006.238.08:01:21.74#ibcon#read 6, iclass 26, count 2 2006.238.08:01:21.74#ibcon#end of sib2, iclass 26, count 2 2006.238.08:01:21.74#ibcon#*after write, iclass 26, count 2 2006.238.08:01:21.74#ibcon#*before return 0, iclass 26, count 2 2006.238.08:01:21.74#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:01:21.74#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:01:21.74#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.238.08:01:21.74#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:21.74#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:01:21.86#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:01:21.86#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:01:21.86#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:01:21.86#ibcon#first serial, iclass 26, count 0 2006.238.08:01:21.86#ibcon#enter sib2, iclass 26, count 0 2006.238.08:01:21.86#ibcon#flushed, iclass 26, count 0 2006.238.08:01:21.86#ibcon#about to write, iclass 26, count 0 2006.238.08:01:21.86#ibcon#wrote, iclass 26, count 0 2006.238.08:01:21.86#ibcon#about to read 3, iclass 26, count 0 2006.238.08:01:21.88#ibcon#read 3, iclass 26, count 0 2006.238.08:01:21.88#ibcon#about to read 4, iclass 26, count 0 2006.238.08:01:21.88#ibcon#read 4, iclass 26, count 0 2006.238.08:01:21.88#ibcon#about to read 5, iclass 26, count 0 2006.238.08:01:21.88#ibcon#read 5, iclass 26, count 0 2006.238.08:01:21.88#ibcon#about to read 6, iclass 26, count 0 2006.238.08:01:21.88#ibcon#read 6, iclass 26, count 0 2006.238.08:01:21.88#ibcon#end of sib2, iclass 26, count 0 2006.238.08:01:21.88#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:01:21.88#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:01:21.88#ibcon#[27=USB\r\n] 2006.238.08:01:21.88#ibcon#*before write, iclass 26, count 0 2006.238.08:01:21.88#ibcon#enter sib2, iclass 26, count 0 2006.238.08:01:21.88#ibcon#flushed, iclass 26, count 0 2006.238.08:01:21.88#ibcon#about to write, iclass 26, count 0 2006.238.08:01:21.88#ibcon#wrote, iclass 26, count 0 2006.238.08:01:21.88#ibcon#about to read 3, iclass 26, count 0 2006.238.08:01:21.91#ibcon#read 3, iclass 26, count 0 2006.238.08:01:21.91#ibcon#about to read 4, iclass 26, count 0 2006.238.08:01:21.91#ibcon#read 4, iclass 26, count 0 2006.238.08:01:21.91#ibcon#about to read 5, iclass 26, count 0 2006.238.08:01:21.91#ibcon#read 5, iclass 26, count 0 2006.238.08:01:21.91#ibcon#about to read 6, iclass 26, count 0 2006.238.08:01:21.91#ibcon#read 6, iclass 26, count 0 2006.238.08:01:21.91#ibcon#end of sib2, iclass 26, count 0 2006.238.08:01:21.91#ibcon#*after write, iclass 26, count 0 2006.238.08:01:21.91#ibcon#*before return 0, iclass 26, count 0 2006.238.08:01:21.91#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:01:21.91#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:01:21.91#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:01:21.91#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:01:21.91$vc4f8/vblo=5,744.99 2006.238.08:01:21.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.238.08:01:21.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.238.08:01:21.91#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:21.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:01:21.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:01:21.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:01:21.91#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:01:21.91#ibcon#first serial, iclass 28, count 0 2006.238.08:01:21.91#ibcon#enter sib2, iclass 28, count 0 2006.238.08:01:21.91#ibcon#flushed, iclass 28, count 0 2006.238.08:01:21.91#ibcon#about to write, iclass 28, count 0 2006.238.08:01:21.91#ibcon#wrote, iclass 28, count 0 2006.238.08:01:21.91#ibcon#about to read 3, iclass 28, count 0 2006.238.08:01:21.93#ibcon#read 3, iclass 28, count 0 2006.238.08:01:21.93#ibcon#about to read 4, iclass 28, count 0 2006.238.08:01:21.93#ibcon#read 4, iclass 28, count 0 2006.238.08:01:21.93#ibcon#about to read 5, iclass 28, count 0 2006.238.08:01:21.93#ibcon#read 5, iclass 28, count 0 2006.238.08:01:21.93#ibcon#about to read 6, iclass 28, count 0 2006.238.08:01:21.93#ibcon#read 6, iclass 28, count 0 2006.238.08:01:21.93#ibcon#end of sib2, iclass 28, count 0 2006.238.08:01:21.93#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:01:21.93#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:01:21.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:01:21.93#ibcon#*before write, iclass 28, count 0 2006.238.08:01:21.93#ibcon#enter sib2, iclass 28, count 0 2006.238.08:01:21.93#ibcon#flushed, iclass 28, count 0 2006.238.08:01:21.93#ibcon#about to write, iclass 28, count 0 2006.238.08:01:21.93#ibcon#wrote, iclass 28, count 0 2006.238.08:01:21.93#ibcon#about to read 3, iclass 28, count 0 2006.238.08:01:21.97#ibcon#read 3, iclass 28, count 0 2006.238.08:01:21.97#ibcon#about to read 4, iclass 28, count 0 2006.238.08:01:21.97#ibcon#read 4, iclass 28, count 0 2006.238.08:01:21.97#ibcon#about to read 5, iclass 28, count 0 2006.238.08:01:21.97#ibcon#read 5, iclass 28, count 0 2006.238.08:01:21.97#ibcon#about to read 6, iclass 28, count 0 2006.238.08:01:21.97#ibcon#read 6, iclass 28, count 0 2006.238.08:01:21.97#ibcon#end of sib2, iclass 28, count 0 2006.238.08:01:21.97#ibcon#*after write, iclass 28, count 0 2006.238.08:01:21.97#ibcon#*before return 0, iclass 28, count 0 2006.238.08:01:21.97#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:01:21.97#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:01:21.97#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:01:21.97#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:01:21.97$vc4f8/vb=5,4 2006.238.08:01:21.97#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.238.08:01:21.97#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.238.08:01:21.97#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:21.97#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:01:22.03#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:01:22.03#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:01:22.03#ibcon#enter wrdev, iclass 30, count 2 2006.238.08:01:22.03#ibcon#first serial, iclass 30, count 2 2006.238.08:01:22.03#ibcon#enter sib2, iclass 30, count 2 2006.238.08:01:22.03#ibcon#flushed, iclass 30, count 2 2006.238.08:01:22.03#ibcon#about to write, iclass 30, count 2 2006.238.08:01:22.03#ibcon#wrote, iclass 30, count 2 2006.238.08:01:22.03#ibcon#about to read 3, iclass 30, count 2 2006.238.08:01:22.06#ibcon#read 3, iclass 30, count 2 2006.238.08:01:22.06#ibcon#about to read 4, iclass 30, count 2 2006.238.08:01:22.06#ibcon#read 4, iclass 30, count 2 2006.238.08:01:22.06#ibcon#about to read 5, iclass 30, count 2 2006.238.08:01:22.06#ibcon#read 5, iclass 30, count 2 2006.238.08:01:22.06#ibcon#about to read 6, iclass 30, count 2 2006.238.08:01:22.06#ibcon#read 6, iclass 30, count 2 2006.238.08:01:22.06#ibcon#end of sib2, iclass 30, count 2 2006.238.08:01:22.06#ibcon#*mode == 0, iclass 30, count 2 2006.238.08:01:22.06#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.238.08:01:22.06#ibcon#[27=AT05-04\r\n] 2006.238.08:01:22.06#ibcon#*before write, iclass 30, count 2 2006.238.08:01:22.06#ibcon#enter sib2, iclass 30, count 2 2006.238.08:01:22.06#ibcon#flushed, iclass 30, count 2 2006.238.08:01:22.06#ibcon#about to write, iclass 30, count 2 2006.238.08:01:22.06#ibcon#wrote, iclass 30, count 2 2006.238.08:01:22.06#ibcon#about to read 3, iclass 30, count 2 2006.238.08:01:22.09#ibcon#read 3, iclass 30, count 2 2006.238.08:01:22.09#ibcon#about to read 4, iclass 30, count 2 2006.238.08:01:22.09#ibcon#read 4, iclass 30, count 2 2006.238.08:01:22.09#ibcon#about to read 5, iclass 30, count 2 2006.238.08:01:22.09#ibcon#read 5, iclass 30, count 2 2006.238.08:01:22.09#ibcon#about to read 6, iclass 30, count 2 2006.238.08:01:22.09#ibcon#read 6, iclass 30, count 2 2006.238.08:01:22.09#ibcon#end of sib2, iclass 30, count 2 2006.238.08:01:22.09#ibcon#*after write, iclass 30, count 2 2006.238.08:01:22.09#ibcon#*before return 0, iclass 30, count 2 2006.238.08:01:22.09#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:01:22.09#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:01:22.09#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.238.08:01:22.09#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:22.09#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:01:22.21#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:01:22.21#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:01:22.21#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:01:22.21#ibcon#first serial, iclass 30, count 0 2006.238.08:01:22.21#ibcon#enter sib2, iclass 30, count 0 2006.238.08:01:22.21#ibcon#flushed, iclass 30, count 0 2006.238.08:01:22.21#ibcon#about to write, iclass 30, count 0 2006.238.08:01:22.21#ibcon#wrote, iclass 30, count 0 2006.238.08:01:22.21#ibcon#about to read 3, iclass 30, count 0 2006.238.08:01:22.23#ibcon#read 3, iclass 30, count 0 2006.238.08:01:22.23#ibcon#about to read 4, iclass 30, count 0 2006.238.08:01:22.23#ibcon#read 4, iclass 30, count 0 2006.238.08:01:22.23#ibcon#about to read 5, iclass 30, count 0 2006.238.08:01:22.23#ibcon#read 5, iclass 30, count 0 2006.238.08:01:22.23#ibcon#about to read 6, iclass 30, count 0 2006.238.08:01:22.23#ibcon#read 6, iclass 30, count 0 2006.238.08:01:22.23#ibcon#end of sib2, iclass 30, count 0 2006.238.08:01:22.23#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:01:22.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:01:22.23#ibcon#[27=USB\r\n] 2006.238.08:01:22.23#ibcon#*before write, iclass 30, count 0 2006.238.08:01:22.23#ibcon#enter sib2, iclass 30, count 0 2006.238.08:01:22.23#ibcon#flushed, iclass 30, count 0 2006.238.08:01:22.23#ibcon#about to write, iclass 30, count 0 2006.238.08:01:22.23#ibcon#wrote, iclass 30, count 0 2006.238.08:01:22.23#ibcon#about to read 3, iclass 30, count 0 2006.238.08:01:22.26#ibcon#read 3, iclass 30, count 0 2006.238.08:01:22.26#ibcon#about to read 4, iclass 30, count 0 2006.238.08:01:22.26#ibcon#read 4, iclass 30, count 0 2006.238.08:01:22.26#ibcon#about to read 5, iclass 30, count 0 2006.238.08:01:22.26#ibcon#read 5, iclass 30, count 0 2006.238.08:01:22.26#ibcon#about to read 6, iclass 30, count 0 2006.238.08:01:22.26#ibcon#read 6, iclass 30, count 0 2006.238.08:01:22.26#ibcon#end of sib2, iclass 30, count 0 2006.238.08:01:22.26#ibcon#*after write, iclass 30, count 0 2006.238.08:01:22.26#ibcon#*before return 0, iclass 30, count 0 2006.238.08:01:22.26#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:01:22.26#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:01:22.26#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:01:22.26#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:01:22.26$vc4f8/vblo=6,752.99 2006.238.08:01:22.26#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.08:01:22.26#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.08:01:22.26#ibcon#ireg 17 cls_cnt 0 2006.238.08:01:22.26#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:01:22.26#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:01:22.26#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:01:22.26#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:01:22.26#ibcon#first serial, iclass 32, count 0 2006.238.08:01:22.26#ibcon#enter sib2, iclass 32, count 0 2006.238.08:01:22.26#ibcon#flushed, iclass 32, count 0 2006.238.08:01:22.26#ibcon#about to write, iclass 32, count 0 2006.238.08:01:22.26#ibcon#wrote, iclass 32, count 0 2006.238.08:01:22.26#ibcon#about to read 3, iclass 32, count 0 2006.238.08:01:22.28#ibcon#read 3, iclass 32, count 0 2006.238.08:01:22.28#ibcon#about to read 4, iclass 32, count 0 2006.238.08:01:22.28#ibcon#read 4, iclass 32, count 0 2006.238.08:01:22.28#ibcon#about to read 5, iclass 32, count 0 2006.238.08:01:22.28#ibcon#read 5, iclass 32, count 0 2006.238.08:01:22.28#ibcon#about to read 6, iclass 32, count 0 2006.238.08:01:22.28#ibcon#read 6, iclass 32, count 0 2006.238.08:01:22.28#ibcon#end of sib2, iclass 32, count 0 2006.238.08:01:22.28#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:01:22.28#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:01:22.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:01:22.28#ibcon#*before write, iclass 32, count 0 2006.238.08:01:22.28#ibcon#enter sib2, iclass 32, count 0 2006.238.08:01:22.28#ibcon#flushed, iclass 32, count 0 2006.238.08:01:22.28#ibcon#about to write, iclass 32, count 0 2006.238.08:01:22.28#ibcon#wrote, iclass 32, count 0 2006.238.08:01:22.28#ibcon#about to read 3, iclass 32, count 0 2006.238.08:01:22.32#ibcon#read 3, iclass 32, count 0 2006.238.08:01:22.32#ibcon#about to read 4, iclass 32, count 0 2006.238.08:01:22.32#ibcon#read 4, iclass 32, count 0 2006.238.08:01:22.32#ibcon#about to read 5, iclass 32, count 0 2006.238.08:01:22.32#ibcon#read 5, iclass 32, count 0 2006.238.08:01:22.32#ibcon#about to read 6, iclass 32, count 0 2006.238.08:01:22.32#ibcon#read 6, iclass 32, count 0 2006.238.08:01:22.32#ibcon#end of sib2, iclass 32, count 0 2006.238.08:01:22.32#ibcon#*after write, iclass 32, count 0 2006.238.08:01:22.32#ibcon#*before return 0, iclass 32, count 0 2006.238.08:01:22.32#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:01:22.32#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:01:22.32#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:01:22.32#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:01:22.32$vc4f8/vb=6,4 2006.238.08:01:22.32#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.238.08:01:22.32#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.238.08:01:22.32#ibcon#ireg 11 cls_cnt 2 2006.238.08:01:22.32#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:01:22.38#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:01:22.38#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:01:22.38#ibcon#enter wrdev, iclass 34, count 2 2006.238.08:01:22.38#ibcon#first serial, iclass 34, count 2 2006.238.08:01:22.38#ibcon#enter sib2, iclass 34, count 2 2006.238.08:01:22.38#ibcon#flushed, iclass 34, count 2 2006.238.08:01:22.38#ibcon#about to write, iclass 34, count 2 2006.238.08:01:22.38#ibcon#wrote, iclass 34, count 2 2006.238.08:01:22.38#ibcon#about to read 3, iclass 34, count 2 2006.238.08:01:22.40#ibcon#read 3, iclass 34, count 2 2006.238.08:01:22.40#ibcon#about to read 4, iclass 34, count 2 2006.238.08:01:22.40#ibcon#read 4, iclass 34, count 2 2006.238.08:01:22.40#ibcon#about to read 5, iclass 34, count 2 2006.238.08:01:22.40#ibcon#read 5, iclass 34, count 2 2006.238.08:01:22.40#ibcon#about to read 6, iclass 34, count 2 2006.238.08:01:22.40#ibcon#read 6, iclass 34, count 2 2006.238.08:01:22.40#ibcon#end of sib2, iclass 34, count 2 2006.238.08:01:22.40#ibcon#*mode == 0, iclass 34, count 2 2006.238.08:01:22.40#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.238.08:01:22.40#ibcon#[27=AT06-04\r\n] 2006.238.08:01:22.40#ibcon#*before write, iclass 34, count 2 2006.238.08:01:22.40#ibcon#enter sib2, iclass 34, count 2 2006.238.08:01:22.40#ibcon#flushed, iclass 34, count 2 2006.238.08:01:22.40#ibcon#about to write, iclass 34, count 2 2006.238.08:01:22.40#ibcon#wrote, iclass 34, count 2 2006.238.08:01:22.40#ibcon#about to read 3, iclass 34, count 2 2006.238.08:01:22.43#ibcon#read 3, iclass 34, count 2 2006.238.08:01:22.43#ibcon#about to read 4, iclass 34, count 2 2006.238.08:01:22.43#ibcon#read 4, iclass 34, count 2 2006.238.08:01:22.43#ibcon#about to read 5, iclass 34, count 2 2006.238.08:01:22.43#ibcon#read 5, iclass 34, count 2 2006.238.08:01:22.43#ibcon#about to read 6, iclass 34, count 2 2006.238.08:01:22.43#ibcon#read 6, iclass 34, count 2 2006.238.08:01:22.43#ibcon#end of sib2, iclass 34, count 2 2006.238.08:01:22.43#ibcon#*after write, iclass 34, count 2 2006.238.08:01:22.43#ibcon#*before return 0, iclass 34, count 2 2006.238.08:01:22.43#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:01:22.43#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:01:22.43#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.238.08:01:22.43#ibcon#ireg 7 cls_cnt 0 2006.238.08:01:22.43#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:01:22.55#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:01:22.55#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:01:22.55#ibcon#enter wrdev, iclass 34, count 0 2006.238.08:01:22.55#ibcon#first serial, iclass 34, count 0 2006.238.08:01:22.55#ibcon#enter sib2, iclass 34, count 0 2006.238.08:01:22.55#ibcon#flushed, iclass 34, count 0 2006.238.08:01:22.55#ibcon#about to write, iclass 34, count 0 2006.238.08:01:22.55#ibcon#wrote, iclass 34, count 0 2006.238.08:01:22.55#ibcon#about to read 3, iclass 34, count 0 2006.238.08:01:22.57#ibcon#read 3, iclass 34, count 0 2006.238.08:01:22.57#ibcon#about to read 4, iclass 34, count 0 2006.238.08:01:22.57#ibcon#read 4, iclass 34, count 0 2006.238.08:01:22.57#ibcon#about to read 5, iclass 34, count 0 2006.238.08:01:22.57#ibcon#read 5, iclass 34, count 0 2006.238.08:01:22.57#ibcon#about to read 6, iclass 34, count 0 2006.238.08:01:22.57#ibcon#read 6, iclass 34, count 0 2006.238.08:01:22.57#ibcon#end of sib2, iclass 34, count 0 2006.238.08:01:22.57#ibcon#*mode == 0, iclass 34, count 0 2006.238.08:01:22.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.08:01:22.57#ibcon#[27=USB\r\n] 2006.238.08:01:22.57#ibcon#*before write, iclass 34, count 0 2006.238.08:01:22.57#ibcon#enter sib2, iclass 34, count 0 2006.238.08:01:22.57#ibcon#flushed, iclass 34, count 0 2006.238.08:01:22.57#ibcon#about to write, iclass 34, count 0 2006.238.08:01:22.57#ibcon#wrote, iclass 34, count 0 2006.238.08:01:22.57#ibcon#about to read 3, iclass 34, count 0 2006.238.08:01:22.60#ibcon#read 3, iclass 34, count 0 2006.238.08:01:22.60#ibcon#about to read 4, iclass 34, count 0 2006.238.08:01:22.60#ibcon#read 4, iclass 34, count 0 2006.238.08:01:22.60#ibcon#about to read 5, iclass 34, count 0 2006.238.08:01:22.60#ibcon#read 5, iclass 34, count 0 2006.238.08:01:22.60#ibcon#about to read 6, iclass 34, count 0 2006.238.08:01:22.60#ibcon#read 6, iclass 34, count 0 2006.238.08:01:22.60#ibcon#end of sib2, iclass 34, count 0 2006.238.08:01:22.60#ibcon#*after write, iclass 34, count 0 2006.238.08:01:22.60#ibcon#*before return 0, iclass 34, count 0 2006.238.08:01:22.60#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:01:22.60#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:01:22.60#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.08:01:22.60#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.08:01:22.60$vc4f8/vabw=wide 2006.238.08:01:22.60#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.08:01:22.60#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.08:01:22.60#ibcon#ireg 8 cls_cnt 0 2006.238.08:01:22.60#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:01:22.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:01:22.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:01:22.60#ibcon#enter wrdev, iclass 36, count 0 2006.238.08:01:22.60#ibcon#first serial, iclass 36, count 0 2006.238.08:01:22.60#ibcon#enter sib2, iclass 36, count 0 2006.238.08:01:22.60#ibcon#flushed, iclass 36, count 0 2006.238.08:01:22.60#ibcon#about to write, iclass 36, count 0 2006.238.08:01:22.60#ibcon#wrote, iclass 36, count 0 2006.238.08:01:22.60#ibcon#about to read 3, iclass 36, count 0 2006.238.08:01:22.62#ibcon#read 3, iclass 36, count 0 2006.238.08:01:22.62#ibcon#about to read 4, iclass 36, count 0 2006.238.08:01:22.62#ibcon#read 4, iclass 36, count 0 2006.238.08:01:22.62#ibcon#about to read 5, iclass 36, count 0 2006.238.08:01:22.62#ibcon#read 5, iclass 36, count 0 2006.238.08:01:22.62#ibcon#about to read 6, iclass 36, count 0 2006.238.08:01:22.62#ibcon#read 6, iclass 36, count 0 2006.238.08:01:22.62#ibcon#end of sib2, iclass 36, count 0 2006.238.08:01:22.62#ibcon#*mode == 0, iclass 36, count 0 2006.238.08:01:22.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.08:01:22.62#ibcon#[25=BW32\r\n] 2006.238.08:01:22.62#ibcon#*before write, iclass 36, count 0 2006.238.08:01:22.62#ibcon#enter sib2, iclass 36, count 0 2006.238.08:01:22.62#ibcon#flushed, iclass 36, count 0 2006.238.08:01:22.62#ibcon#about to write, iclass 36, count 0 2006.238.08:01:22.62#ibcon#wrote, iclass 36, count 0 2006.238.08:01:22.62#ibcon#about to read 3, iclass 36, count 0 2006.238.08:01:22.65#ibcon#read 3, iclass 36, count 0 2006.238.08:01:22.65#ibcon#about to read 4, iclass 36, count 0 2006.238.08:01:22.65#ibcon#read 4, iclass 36, count 0 2006.238.08:01:22.65#ibcon#about to read 5, iclass 36, count 0 2006.238.08:01:22.65#ibcon#read 5, iclass 36, count 0 2006.238.08:01:22.65#ibcon#about to read 6, iclass 36, count 0 2006.238.08:01:22.65#ibcon#read 6, iclass 36, count 0 2006.238.08:01:22.65#ibcon#end of sib2, iclass 36, count 0 2006.238.08:01:22.65#ibcon#*after write, iclass 36, count 0 2006.238.08:01:22.65#ibcon#*before return 0, iclass 36, count 0 2006.238.08:01:22.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:01:22.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:01:22.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.08:01:22.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.08:01:22.65$vc4f8/vbbw=wide 2006.238.08:01:22.65#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.238.08:01:22.65#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.238.08:01:22.65#ibcon#ireg 8 cls_cnt 0 2006.238.08:01:22.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:01:22.72#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:01:22.72#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:01:22.72#ibcon#enter wrdev, iclass 38, count 0 2006.238.08:01:22.72#ibcon#first serial, iclass 38, count 0 2006.238.08:01:22.72#ibcon#enter sib2, iclass 38, count 0 2006.238.08:01:22.72#ibcon#flushed, iclass 38, count 0 2006.238.08:01:22.72#ibcon#about to write, iclass 38, count 0 2006.238.08:01:22.72#ibcon#wrote, iclass 38, count 0 2006.238.08:01:22.72#ibcon#about to read 3, iclass 38, count 0 2006.238.08:01:22.74#ibcon#read 3, iclass 38, count 0 2006.238.08:01:22.74#ibcon#about to read 4, iclass 38, count 0 2006.238.08:01:22.74#ibcon#read 4, iclass 38, count 0 2006.238.08:01:22.74#ibcon#about to read 5, iclass 38, count 0 2006.238.08:01:22.74#ibcon#read 5, iclass 38, count 0 2006.238.08:01:22.74#ibcon#about to read 6, iclass 38, count 0 2006.238.08:01:22.74#ibcon#read 6, iclass 38, count 0 2006.238.08:01:22.74#ibcon#end of sib2, iclass 38, count 0 2006.238.08:01:22.74#ibcon#*mode == 0, iclass 38, count 0 2006.238.08:01:22.74#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.08:01:22.74#ibcon#[27=BW32\r\n] 2006.238.08:01:22.74#ibcon#*before write, iclass 38, count 0 2006.238.08:01:22.74#ibcon#enter sib2, iclass 38, count 0 2006.238.08:01:22.74#ibcon#flushed, iclass 38, count 0 2006.238.08:01:22.74#ibcon#about to write, iclass 38, count 0 2006.238.08:01:22.74#ibcon#wrote, iclass 38, count 0 2006.238.08:01:22.74#ibcon#about to read 3, iclass 38, count 0 2006.238.08:01:22.77#ibcon#read 3, iclass 38, count 0 2006.238.08:01:22.77#ibcon#about to read 4, iclass 38, count 0 2006.238.08:01:22.77#ibcon#read 4, iclass 38, count 0 2006.238.08:01:22.77#ibcon#about to read 5, iclass 38, count 0 2006.238.08:01:22.77#ibcon#read 5, iclass 38, count 0 2006.238.08:01:22.77#ibcon#about to read 6, iclass 38, count 0 2006.238.08:01:22.77#ibcon#read 6, iclass 38, count 0 2006.238.08:01:22.77#ibcon#end of sib2, iclass 38, count 0 2006.238.08:01:22.77#ibcon#*after write, iclass 38, count 0 2006.238.08:01:22.77#ibcon#*before return 0, iclass 38, count 0 2006.238.08:01:22.77#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:01:22.77#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:01:22.77#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.08:01:22.77#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.08:01:22.77$4f8m12a/ifd4f 2006.238.08:01:22.77$ifd4f/lo= 2006.238.08:01:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:01:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:01:22.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:01:22.78$ifd4f/patch= 2006.238.08:01:22.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:01:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:01:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:01:22.78$4f8m12a/"form=m,16.000,1:2 2006.238.08:01:22.78$4f8m12a/"tpicd 2006.238.08:01:22.78$4f8m12a/echo=off 2006.238.08:01:22.78$4f8m12a/xlog=off 2006.238.08:01:22.78:!2006.238.08:01:50 2006.238.08:01:35.14#trakl#Source acquired 2006.238.08:01:37.14#flagr#flagr/antenna,acquired 2006.238.08:01:50.01:preob 2006.238.08:01:51.14/onsource/TRACKING 2006.238.08:01:51.14:!2006.238.08:02:00 2006.238.08:02:00.00:data_valid=on 2006.238.08:02:00.00:midob 2006.238.08:02:00.14/onsource/TRACKING 2006.238.08:02:00.14/wx/25.44,1012.2,88 2006.238.08:02:00.31/cable/+6.4169E-03 2006.238.08:02:01.40/va/01,08,usb,yes,33,34 2006.238.08:02:01.40/va/02,07,usb,yes,33,34 2006.238.08:02:01.40/va/03,07,usb,yes,31,31 2006.238.08:02:01.40/va/04,07,usb,yes,34,37 2006.238.08:02:01.40/va/05,08,usb,yes,32,33 2006.238.08:02:01.40/va/06,07,usb,yes,34,34 2006.238.08:02:01.40/va/07,07,usb,yes,34,34 2006.238.08:02:01.40/va/08,07,usb,yes,37,36 2006.238.08:02:01.63/valo/01,532.99,yes,locked 2006.238.08:02:01.63/valo/02,572.99,yes,locked 2006.238.08:02:01.63/valo/03,672.99,yes,locked 2006.238.08:02:01.63/valo/04,832.99,yes,locked 2006.238.08:02:01.63/valo/05,652.99,yes,locked 2006.238.08:02:01.63/valo/06,772.99,yes,locked 2006.238.08:02:01.63/valo/07,832.99,yes,locked 2006.238.08:02:01.63/valo/08,852.99,yes,locked 2006.238.08:02:02.72/vb/01,04,usb,yes,31,30 2006.238.08:02:02.72/vb/02,04,usb,yes,33,34 2006.238.08:02:02.72/vb/03,04,usb,yes,29,33 2006.238.08:02:02.72/vb/04,04,usb,yes,30,30 2006.238.08:02:02.72/vb/05,04,usb,yes,28,32 2006.238.08:02:02.72/vb/06,04,usb,yes,29,32 2006.238.08:02:02.72/vb/07,04,usb,yes,32,31 2006.238.08:02:02.72/vb/08,04,usb,yes,29,32 2006.238.08:02:02.96/vblo/01,632.99,yes,locked 2006.238.08:02:02.96/vblo/02,640.99,yes,locked 2006.238.08:02:02.96/vblo/03,656.99,yes,locked 2006.238.08:02:02.96/vblo/04,712.99,yes,locked 2006.238.08:02:02.96/vblo/05,744.99,yes,locked 2006.238.08:02:02.96/vblo/06,752.99,yes,locked 2006.238.08:02:02.96/vblo/07,734.99,yes,locked 2006.238.08:02:02.96/vblo/08,744.99,yes,locked 2006.238.08:02:03.11/vabw/8 2006.238.08:02:03.26/vbbw/8 2006.238.08:02:03.35/xfe/off,on,13.5 2006.238.08:02:03.72/ifatt/23,28,28,28 2006.238.08:02:04.08/fmout-gps/S +4.30E-07 2006.238.08:02:04.12:!2006.238.08:03:00 2006.238.08:03:00.00:data_valid=off 2006.238.08:03:00.01:postob 2006.238.08:03:00.06/cable/+6.4191E-03 2006.238.08:03:00.07/wx/25.44,1012.2,88 2006.238.08:03:01.08/fmout-gps/S +4.31E-07 2006.238.08:03:01.09:scan_name=238-0803,k06238,60 2006.238.08:03:01.09:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.238.08:03:02.14#flagr#flagr/antenna,new-source 2006.238.08:03:02.15:checkk5 2006.238.08:03:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:03:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:03:03.29/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:03:03.67/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:03:04.05/chk_obsdata//k5ts1/T2380802??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:03:04.42/chk_obsdata//k5ts2/T2380802??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:03:04.79/chk_obsdata//k5ts3/T2380802??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:03:05.16/chk_obsdata//k5ts4/T2380802??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:03:05.85/k5log//k5ts1_log_newline 2006.238.08:03:06.54/k5log//k5ts2_log_newline 2006.238.08:03:07.23/k5log//k5ts3_log_newline 2006.238.08:03:07.92/k5log//k5ts4_log_newline 2006.238.08:03:07.95/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:03:07.95:4f8m12a=2 2006.238.08:03:07.95$4f8m12a/echo=on 2006.238.08:03:07.95$4f8m12a/pcalon 2006.238.08:03:07.95$pcalon/"no phase cal control is implemented here 2006.238.08:03:07.95$4f8m12a/"tpicd=stop 2006.238.08:03:07.95$4f8m12a/vc4f8 2006.238.08:03:07.95$vc4f8/valo=1,532.99 2006.238.08:03:07.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.238.08:03:07.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.238.08:03:07.95#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:07.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:03:07.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:03:07.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:03:07.95#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:03:07.95#ibcon#first serial, iclass 7, count 0 2006.238.08:03:07.95#ibcon#enter sib2, iclass 7, count 0 2006.238.08:03:07.95#ibcon#flushed, iclass 7, count 0 2006.238.08:03:07.95#ibcon#about to write, iclass 7, count 0 2006.238.08:03:07.95#ibcon#wrote, iclass 7, count 0 2006.238.08:03:07.95#ibcon#about to read 3, iclass 7, count 0 2006.238.08:03:08.00#ibcon#read 3, iclass 7, count 0 2006.238.08:03:08.00#ibcon#about to read 4, iclass 7, count 0 2006.238.08:03:08.00#ibcon#read 4, iclass 7, count 0 2006.238.08:03:08.00#ibcon#about to read 5, iclass 7, count 0 2006.238.08:03:08.00#ibcon#read 5, iclass 7, count 0 2006.238.08:03:08.00#ibcon#about to read 6, iclass 7, count 0 2006.238.08:03:08.00#ibcon#read 6, iclass 7, count 0 2006.238.08:03:08.00#ibcon#end of sib2, iclass 7, count 0 2006.238.08:03:08.00#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:03:08.00#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:03:08.00#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:03:08.00#ibcon#*before write, iclass 7, count 0 2006.238.08:03:08.00#ibcon#enter sib2, iclass 7, count 0 2006.238.08:03:08.00#ibcon#flushed, iclass 7, count 0 2006.238.08:03:08.00#ibcon#about to write, iclass 7, count 0 2006.238.08:03:08.00#ibcon#wrote, iclass 7, count 0 2006.238.08:03:08.00#ibcon#about to read 3, iclass 7, count 0 2006.238.08:03:08.04#ibcon#read 3, iclass 7, count 0 2006.238.08:03:08.04#ibcon#about to read 4, iclass 7, count 0 2006.238.08:03:08.04#ibcon#read 4, iclass 7, count 0 2006.238.08:03:08.04#ibcon#about to read 5, iclass 7, count 0 2006.238.08:03:08.04#ibcon#read 5, iclass 7, count 0 2006.238.08:03:08.04#ibcon#about to read 6, iclass 7, count 0 2006.238.08:03:08.04#ibcon#read 6, iclass 7, count 0 2006.238.08:03:08.04#ibcon#end of sib2, iclass 7, count 0 2006.238.08:03:08.04#ibcon#*after write, iclass 7, count 0 2006.238.08:03:08.04#ibcon#*before return 0, iclass 7, count 0 2006.238.08:03:08.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:03:08.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:03:08.04#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:03:08.04#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:03:08.04$vc4f8/va=1,8 2006.238.08:03:08.04#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.238.08:03:08.04#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.238.08:03:08.04#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:08.04#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:03:08.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:03:08.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:03:08.04#ibcon#enter wrdev, iclass 11, count 2 2006.238.08:03:08.04#ibcon#first serial, iclass 11, count 2 2006.238.08:03:08.04#ibcon#enter sib2, iclass 11, count 2 2006.238.08:03:08.04#ibcon#flushed, iclass 11, count 2 2006.238.08:03:08.04#ibcon#about to write, iclass 11, count 2 2006.238.08:03:08.04#ibcon#wrote, iclass 11, count 2 2006.238.08:03:08.04#ibcon#about to read 3, iclass 11, count 2 2006.238.08:03:08.07#ibcon#read 3, iclass 11, count 2 2006.238.08:03:08.07#ibcon#about to read 4, iclass 11, count 2 2006.238.08:03:08.07#ibcon#read 4, iclass 11, count 2 2006.238.08:03:08.07#ibcon#about to read 5, iclass 11, count 2 2006.238.08:03:08.07#ibcon#read 5, iclass 11, count 2 2006.238.08:03:08.07#ibcon#about to read 6, iclass 11, count 2 2006.238.08:03:08.07#ibcon#read 6, iclass 11, count 2 2006.238.08:03:08.07#ibcon#end of sib2, iclass 11, count 2 2006.238.08:03:08.07#ibcon#*mode == 0, iclass 11, count 2 2006.238.08:03:08.07#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.238.08:03:08.07#ibcon#[25=AT01-08\r\n] 2006.238.08:03:08.07#ibcon#*before write, iclass 11, count 2 2006.238.08:03:08.07#ibcon#enter sib2, iclass 11, count 2 2006.238.08:03:08.07#ibcon#flushed, iclass 11, count 2 2006.238.08:03:08.07#ibcon#about to write, iclass 11, count 2 2006.238.08:03:08.07#ibcon#wrote, iclass 11, count 2 2006.238.08:03:08.07#ibcon#about to read 3, iclass 11, count 2 2006.238.08:03:08.10#ibcon#read 3, iclass 11, count 2 2006.238.08:03:08.10#ibcon#about to read 4, iclass 11, count 2 2006.238.08:03:08.10#ibcon#read 4, iclass 11, count 2 2006.238.08:03:08.10#ibcon#about to read 5, iclass 11, count 2 2006.238.08:03:08.10#ibcon#read 5, iclass 11, count 2 2006.238.08:03:08.10#ibcon#about to read 6, iclass 11, count 2 2006.238.08:03:08.10#ibcon#read 6, iclass 11, count 2 2006.238.08:03:08.10#ibcon#end of sib2, iclass 11, count 2 2006.238.08:03:08.10#ibcon#*after write, iclass 11, count 2 2006.238.08:03:08.10#ibcon#*before return 0, iclass 11, count 2 2006.238.08:03:08.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:03:08.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:03:08.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.238.08:03:08.10#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:08.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:03:08.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:03:08.22#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:03:08.22#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:03:08.22#ibcon#first serial, iclass 11, count 0 2006.238.08:03:08.22#ibcon#enter sib2, iclass 11, count 0 2006.238.08:03:08.22#ibcon#flushed, iclass 11, count 0 2006.238.08:03:08.22#ibcon#about to write, iclass 11, count 0 2006.238.08:03:08.22#ibcon#wrote, iclass 11, count 0 2006.238.08:03:08.22#ibcon#about to read 3, iclass 11, count 0 2006.238.08:03:08.24#ibcon#read 3, iclass 11, count 0 2006.238.08:03:08.24#ibcon#about to read 4, iclass 11, count 0 2006.238.08:03:08.24#ibcon#read 4, iclass 11, count 0 2006.238.08:03:08.24#ibcon#about to read 5, iclass 11, count 0 2006.238.08:03:08.24#ibcon#read 5, iclass 11, count 0 2006.238.08:03:08.24#ibcon#about to read 6, iclass 11, count 0 2006.238.08:03:08.24#ibcon#read 6, iclass 11, count 0 2006.238.08:03:08.24#ibcon#end of sib2, iclass 11, count 0 2006.238.08:03:08.24#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:03:08.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:03:08.24#ibcon#[25=USB\r\n] 2006.238.08:03:08.24#ibcon#*before write, iclass 11, count 0 2006.238.08:03:08.24#ibcon#enter sib2, iclass 11, count 0 2006.238.08:03:08.24#ibcon#flushed, iclass 11, count 0 2006.238.08:03:08.24#ibcon#about to write, iclass 11, count 0 2006.238.08:03:08.24#ibcon#wrote, iclass 11, count 0 2006.238.08:03:08.24#ibcon#about to read 3, iclass 11, count 0 2006.238.08:03:08.27#ibcon#read 3, iclass 11, count 0 2006.238.08:03:08.27#ibcon#about to read 4, iclass 11, count 0 2006.238.08:03:08.27#ibcon#read 4, iclass 11, count 0 2006.238.08:03:08.27#ibcon#about to read 5, iclass 11, count 0 2006.238.08:03:08.27#ibcon#read 5, iclass 11, count 0 2006.238.08:03:08.27#ibcon#about to read 6, iclass 11, count 0 2006.238.08:03:08.27#ibcon#read 6, iclass 11, count 0 2006.238.08:03:08.27#ibcon#end of sib2, iclass 11, count 0 2006.238.08:03:08.27#ibcon#*after write, iclass 11, count 0 2006.238.08:03:08.27#ibcon#*before return 0, iclass 11, count 0 2006.238.08:03:08.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:03:08.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:03:08.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:03:08.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:03:08.27$vc4f8/valo=2,572.99 2006.238.08:03:08.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.08:03:08.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.08:03:08.27#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:08.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:03:08.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:03:08.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:03:08.27#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:03:08.27#ibcon#first serial, iclass 13, count 0 2006.238.08:03:08.27#ibcon#enter sib2, iclass 13, count 0 2006.238.08:03:08.27#ibcon#flushed, iclass 13, count 0 2006.238.08:03:08.27#ibcon#about to write, iclass 13, count 0 2006.238.08:03:08.27#ibcon#wrote, iclass 13, count 0 2006.238.08:03:08.27#ibcon#about to read 3, iclass 13, count 0 2006.238.08:03:08.29#ibcon#read 3, iclass 13, count 0 2006.238.08:03:08.29#ibcon#about to read 4, iclass 13, count 0 2006.238.08:03:08.29#ibcon#read 4, iclass 13, count 0 2006.238.08:03:08.29#ibcon#about to read 5, iclass 13, count 0 2006.238.08:03:08.29#ibcon#read 5, iclass 13, count 0 2006.238.08:03:08.29#ibcon#about to read 6, iclass 13, count 0 2006.238.08:03:08.29#ibcon#read 6, iclass 13, count 0 2006.238.08:03:08.29#ibcon#end of sib2, iclass 13, count 0 2006.238.08:03:08.29#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:03:08.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:03:08.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:03:08.29#ibcon#*before write, iclass 13, count 0 2006.238.08:03:08.29#ibcon#enter sib2, iclass 13, count 0 2006.238.08:03:08.29#ibcon#flushed, iclass 13, count 0 2006.238.08:03:08.29#ibcon#about to write, iclass 13, count 0 2006.238.08:03:08.29#ibcon#wrote, iclass 13, count 0 2006.238.08:03:08.29#ibcon#about to read 3, iclass 13, count 0 2006.238.08:03:08.33#ibcon#read 3, iclass 13, count 0 2006.238.08:03:08.33#ibcon#about to read 4, iclass 13, count 0 2006.238.08:03:08.33#ibcon#read 4, iclass 13, count 0 2006.238.08:03:08.33#ibcon#about to read 5, iclass 13, count 0 2006.238.08:03:08.33#ibcon#read 5, iclass 13, count 0 2006.238.08:03:08.33#ibcon#about to read 6, iclass 13, count 0 2006.238.08:03:08.33#ibcon#read 6, iclass 13, count 0 2006.238.08:03:08.33#ibcon#end of sib2, iclass 13, count 0 2006.238.08:03:08.33#ibcon#*after write, iclass 13, count 0 2006.238.08:03:08.33#ibcon#*before return 0, iclass 13, count 0 2006.238.08:03:08.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:03:08.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:03:08.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:03:08.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:03:08.33$vc4f8/va=2,7 2006.238.08:03:08.33#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.238.08:03:08.33#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.238.08:03:08.33#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:08.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:03:08.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:03:08.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:03:08.39#ibcon#enter wrdev, iclass 15, count 2 2006.238.08:03:08.39#ibcon#first serial, iclass 15, count 2 2006.238.08:03:08.39#ibcon#enter sib2, iclass 15, count 2 2006.238.08:03:08.39#ibcon#flushed, iclass 15, count 2 2006.238.08:03:08.39#ibcon#about to write, iclass 15, count 2 2006.238.08:03:08.39#ibcon#wrote, iclass 15, count 2 2006.238.08:03:08.39#ibcon#about to read 3, iclass 15, count 2 2006.238.08:03:08.41#ibcon#read 3, iclass 15, count 2 2006.238.08:03:08.41#ibcon#about to read 4, iclass 15, count 2 2006.238.08:03:08.41#ibcon#read 4, iclass 15, count 2 2006.238.08:03:08.41#ibcon#about to read 5, iclass 15, count 2 2006.238.08:03:08.41#ibcon#read 5, iclass 15, count 2 2006.238.08:03:08.41#ibcon#about to read 6, iclass 15, count 2 2006.238.08:03:08.41#ibcon#read 6, iclass 15, count 2 2006.238.08:03:08.41#ibcon#end of sib2, iclass 15, count 2 2006.238.08:03:08.41#ibcon#*mode == 0, iclass 15, count 2 2006.238.08:03:08.41#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.238.08:03:08.41#ibcon#[25=AT02-07\r\n] 2006.238.08:03:08.41#ibcon#*before write, iclass 15, count 2 2006.238.08:03:08.41#ibcon#enter sib2, iclass 15, count 2 2006.238.08:03:08.41#ibcon#flushed, iclass 15, count 2 2006.238.08:03:08.41#ibcon#about to write, iclass 15, count 2 2006.238.08:03:08.41#ibcon#wrote, iclass 15, count 2 2006.238.08:03:08.41#ibcon#about to read 3, iclass 15, count 2 2006.238.08:03:08.44#ibcon#read 3, iclass 15, count 2 2006.238.08:03:08.44#ibcon#about to read 4, iclass 15, count 2 2006.238.08:03:08.44#ibcon#read 4, iclass 15, count 2 2006.238.08:03:08.44#ibcon#about to read 5, iclass 15, count 2 2006.238.08:03:08.44#ibcon#read 5, iclass 15, count 2 2006.238.08:03:08.44#ibcon#about to read 6, iclass 15, count 2 2006.238.08:03:08.44#ibcon#read 6, iclass 15, count 2 2006.238.08:03:08.44#ibcon#end of sib2, iclass 15, count 2 2006.238.08:03:08.44#ibcon#*after write, iclass 15, count 2 2006.238.08:03:08.44#ibcon#*before return 0, iclass 15, count 2 2006.238.08:03:08.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:03:08.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:03:08.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.238.08:03:08.44#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:08.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:03:08.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:03:08.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:03:08.56#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:03:08.56#ibcon#first serial, iclass 15, count 0 2006.238.08:03:08.56#ibcon#enter sib2, iclass 15, count 0 2006.238.08:03:08.56#ibcon#flushed, iclass 15, count 0 2006.238.08:03:08.56#ibcon#about to write, iclass 15, count 0 2006.238.08:03:08.56#ibcon#wrote, iclass 15, count 0 2006.238.08:03:08.56#ibcon#about to read 3, iclass 15, count 0 2006.238.08:03:08.58#ibcon#read 3, iclass 15, count 0 2006.238.08:03:08.58#ibcon#about to read 4, iclass 15, count 0 2006.238.08:03:08.58#ibcon#read 4, iclass 15, count 0 2006.238.08:03:08.58#ibcon#about to read 5, iclass 15, count 0 2006.238.08:03:08.58#ibcon#read 5, iclass 15, count 0 2006.238.08:03:08.58#ibcon#about to read 6, iclass 15, count 0 2006.238.08:03:08.58#ibcon#read 6, iclass 15, count 0 2006.238.08:03:08.58#ibcon#end of sib2, iclass 15, count 0 2006.238.08:03:08.58#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:03:08.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:03:08.58#ibcon#[25=USB\r\n] 2006.238.08:03:08.58#ibcon#*before write, iclass 15, count 0 2006.238.08:03:08.58#ibcon#enter sib2, iclass 15, count 0 2006.238.08:03:08.58#ibcon#flushed, iclass 15, count 0 2006.238.08:03:08.58#ibcon#about to write, iclass 15, count 0 2006.238.08:03:08.58#ibcon#wrote, iclass 15, count 0 2006.238.08:03:08.58#ibcon#about to read 3, iclass 15, count 0 2006.238.08:03:08.61#ibcon#read 3, iclass 15, count 0 2006.238.08:03:08.61#ibcon#about to read 4, iclass 15, count 0 2006.238.08:03:08.61#ibcon#read 4, iclass 15, count 0 2006.238.08:03:08.61#ibcon#about to read 5, iclass 15, count 0 2006.238.08:03:08.61#ibcon#read 5, iclass 15, count 0 2006.238.08:03:08.61#ibcon#about to read 6, iclass 15, count 0 2006.238.08:03:08.61#ibcon#read 6, iclass 15, count 0 2006.238.08:03:08.61#ibcon#end of sib2, iclass 15, count 0 2006.238.08:03:08.61#ibcon#*after write, iclass 15, count 0 2006.238.08:03:08.61#ibcon#*before return 0, iclass 15, count 0 2006.238.08:03:08.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:03:08.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:03:08.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:03:08.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:03:08.61$vc4f8/valo=3,672.99 2006.238.08:03:08.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.08:03:08.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.08:03:08.61#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:08.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:03:08.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:03:08.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:03:08.61#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:03:08.61#ibcon#first serial, iclass 17, count 0 2006.238.08:03:08.61#ibcon#enter sib2, iclass 17, count 0 2006.238.08:03:08.61#ibcon#flushed, iclass 17, count 0 2006.238.08:03:08.61#ibcon#about to write, iclass 17, count 0 2006.238.08:03:08.61#ibcon#wrote, iclass 17, count 0 2006.238.08:03:08.61#ibcon#about to read 3, iclass 17, count 0 2006.238.08:03:08.63#ibcon#read 3, iclass 17, count 0 2006.238.08:03:08.63#ibcon#about to read 4, iclass 17, count 0 2006.238.08:03:08.63#ibcon#read 4, iclass 17, count 0 2006.238.08:03:08.63#ibcon#about to read 5, iclass 17, count 0 2006.238.08:03:08.63#ibcon#read 5, iclass 17, count 0 2006.238.08:03:08.63#ibcon#about to read 6, iclass 17, count 0 2006.238.08:03:08.63#ibcon#read 6, iclass 17, count 0 2006.238.08:03:08.63#ibcon#end of sib2, iclass 17, count 0 2006.238.08:03:08.63#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:03:08.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:03:08.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:03:08.63#ibcon#*before write, iclass 17, count 0 2006.238.08:03:08.63#ibcon#enter sib2, iclass 17, count 0 2006.238.08:03:08.63#ibcon#flushed, iclass 17, count 0 2006.238.08:03:08.63#ibcon#about to write, iclass 17, count 0 2006.238.08:03:08.63#ibcon#wrote, iclass 17, count 0 2006.238.08:03:08.63#ibcon#about to read 3, iclass 17, count 0 2006.238.08:03:08.67#ibcon#read 3, iclass 17, count 0 2006.238.08:03:08.67#ibcon#about to read 4, iclass 17, count 0 2006.238.08:03:08.67#ibcon#read 4, iclass 17, count 0 2006.238.08:03:08.67#ibcon#about to read 5, iclass 17, count 0 2006.238.08:03:08.67#ibcon#read 5, iclass 17, count 0 2006.238.08:03:08.67#ibcon#about to read 6, iclass 17, count 0 2006.238.08:03:08.67#ibcon#read 6, iclass 17, count 0 2006.238.08:03:08.67#ibcon#end of sib2, iclass 17, count 0 2006.238.08:03:08.67#ibcon#*after write, iclass 17, count 0 2006.238.08:03:08.67#ibcon#*before return 0, iclass 17, count 0 2006.238.08:03:08.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:03:08.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:03:08.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:03:08.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:03:08.67$vc4f8/va=3,7 2006.238.08:03:08.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.238.08:03:08.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.238.08:03:08.67#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:08.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:03:08.73#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:03:08.73#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:03:08.73#ibcon#enter wrdev, iclass 19, count 2 2006.238.08:03:08.73#ibcon#first serial, iclass 19, count 2 2006.238.08:03:08.73#ibcon#enter sib2, iclass 19, count 2 2006.238.08:03:08.73#ibcon#flushed, iclass 19, count 2 2006.238.08:03:08.73#ibcon#about to write, iclass 19, count 2 2006.238.08:03:08.73#ibcon#wrote, iclass 19, count 2 2006.238.08:03:08.73#ibcon#about to read 3, iclass 19, count 2 2006.238.08:03:08.75#ibcon#read 3, iclass 19, count 2 2006.238.08:03:08.75#ibcon#about to read 4, iclass 19, count 2 2006.238.08:03:08.75#ibcon#read 4, iclass 19, count 2 2006.238.08:03:08.75#ibcon#about to read 5, iclass 19, count 2 2006.238.08:03:08.75#ibcon#read 5, iclass 19, count 2 2006.238.08:03:08.75#ibcon#about to read 6, iclass 19, count 2 2006.238.08:03:08.75#ibcon#read 6, iclass 19, count 2 2006.238.08:03:08.75#ibcon#end of sib2, iclass 19, count 2 2006.238.08:03:08.75#ibcon#*mode == 0, iclass 19, count 2 2006.238.08:03:08.75#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.238.08:03:08.75#ibcon#[25=AT03-07\r\n] 2006.238.08:03:08.75#ibcon#*before write, iclass 19, count 2 2006.238.08:03:08.75#ibcon#enter sib2, iclass 19, count 2 2006.238.08:03:08.75#ibcon#flushed, iclass 19, count 2 2006.238.08:03:08.75#ibcon#about to write, iclass 19, count 2 2006.238.08:03:08.75#ibcon#wrote, iclass 19, count 2 2006.238.08:03:08.75#ibcon#about to read 3, iclass 19, count 2 2006.238.08:03:08.78#ibcon#read 3, iclass 19, count 2 2006.238.08:03:08.78#ibcon#about to read 4, iclass 19, count 2 2006.238.08:03:08.78#ibcon#read 4, iclass 19, count 2 2006.238.08:03:08.78#ibcon#about to read 5, iclass 19, count 2 2006.238.08:03:08.78#ibcon#read 5, iclass 19, count 2 2006.238.08:03:08.78#ibcon#about to read 6, iclass 19, count 2 2006.238.08:03:08.78#ibcon#read 6, iclass 19, count 2 2006.238.08:03:08.78#ibcon#end of sib2, iclass 19, count 2 2006.238.08:03:08.78#ibcon#*after write, iclass 19, count 2 2006.238.08:03:08.78#ibcon#*before return 0, iclass 19, count 2 2006.238.08:03:08.78#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:03:08.78#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:03:08.78#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.238.08:03:08.78#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:08.78#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:03:08.90#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:03:08.90#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:03:08.90#ibcon#enter wrdev, iclass 19, count 0 2006.238.08:03:08.90#ibcon#first serial, iclass 19, count 0 2006.238.08:03:08.90#ibcon#enter sib2, iclass 19, count 0 2006.238.08:03:08.90#ibcon#flushed, iclass 19, count 0 2006.238.08:03:08.90#ibcon#about to write, iclass 19, count 0 2006.238.08:03:08.90#ibcon#wrote, iclass 19, count 0 2006.238.08:03:08.90#ibcon#about to read 3, iclass 19, count 0 2006.238.08:03:08.92#ibcon#read 3, iclass 19, count 0 2006.238.08:03:08.92#ibcon#about to read 4, iclass 19, count 0 2006.238.08:03:08.92#ibcon#read 4, iclass 19, count 0 2006.238.08:03:08.92#ibcon#about to read 5, iclass 19, count 0 2006.238.08:03:08.92#ibcon#read 5, iclass 19, count 0 2006.238.08:03:08.92#ibcon#about to read 6, iclass 19, count 0 2006.238.08:03:08.92#ibcon#read 6, iclass 19, count 0 2006.238.08:03:08.92#ibcon#end of sib2, iclass 19, count 0 2006.238.08:03:08.92#ibcon#*mode == 0, iclass 19, count 0 2006.238.08:03:08.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.08:03:08.92#ibcon#[25=USB\r\n] 2006.238.08:03:08.92#ibcon#*before write, iclass 19, count 0 2006.238.08:03:08.92#ibcon#enter sib2, iclass 19, count 0 2006.238.08:03:08.92#ibcon#flushed, iclass 19, count 0 2006.238.08:03:08.92#ibcon#about to write, iclass 19, count 0 2006.238.08:03:08.92#ibcon#wrote, iclass 19, count 0 2006.238.08:03:08.92#ibcon#about to read 3, iclass 19, count 0 2006.238.08:03:08.95#ibcon#read 3, iclass 19, count 0 2006.238.08:03:08.95#ibcon#about to read 4, iclass 19, count 0 2006.238.08:03:08.95#ibcon#read 4, iclass 19, count 0 2006.238.08:03:08.95#ibcon#about to read 5, iclass 19, count 0 2006.238.08:03:08.95#ibcon#read 5, iclass 19, count 0 2006.238.08:03:08.95#ibcon#about to read 6, iclass 19, count 0 2006.238.08:03:08.95#ibcon#read 6, iclass 19, count 0 2006.238.08:03:08.95#ibcon#end of sib2, iclass 19, count 0 2006.238.08:03:08.95#ibcon#*after write, iclass 19, count 0 2006.238.08:03:08.95#ibcon#*before return 0, iclass 19, count 0 2006.238.08:03:08.95#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:03:08.95#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:03:08.95#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.08:03:08.95#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.08:03:08.95$vc4f8/valo=4,832.99 2006.238.08:03:08.95#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.08:03:08.95#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.08:03:08.95#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:08.95#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:03:08.95#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:03:08.95#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:03:08.95#ibcon#enter wrdev, iclass 21, count 0 2006.238.08:03:08.95#ibcon#first serial, iclass 21, count 0 2006.238.08:03:08.95#ibcon#enter sib2, iclass 21, count 0 2006.238.08:03:08.95#ibcon#flushed, iclass 21, count 0 2006.238.08:03:08.95#ibcon#about to write, iclass 21, count 0 2006.238.08:03:08.95#ibcon#wrote, iclass 21, count 0 2006.238.08:03:08.95#ibcon#about to read 3, iclass 21, count 0 2006.238.08:03:08.97#ibcon#read 3, iclass 21, count 0 2006.238.08:03:08.97#ibcon#about to read 4, iclass 21, count 0 2006.238.08:03:08.97#ibcon#read 4, iclass 21, count 0 2006.238.08:03:08.97#ibcon#about to read 5, iclass 21, count 0 2006.238.08:03:08.97#ibcon#read 5, iclass 21, count 0 2006.238.08:03:08.97#ibcon#about to read 6, iclass 21, count 0 2006.238.08:03:08.97#ibcon#read 6, iclass 21, count 0 2006.238.08:03:08.97#ibcon#end of sib2, iclass 21, count 0 2006.238.08:03:08.97#ibcon#*mode == 0, iclass 21, count 0 2006.238.08:03:08.97#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.08:03:08.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:03:08.97#ibcon#*before write, iclass 21, count 0 2006.238.08:03:08.97#ibcon#enter sib2, iclass 21, count 0 2006.238.08:03:08.97#ibcon#flushed, iclass 21, count 0 2006.238.08:03:08.97#ibcon#about to write, iclass 21, count 0 2006.238.08:03:08.97#ibcon#wrote, iclass 21, count 0 2006.238.08:03:08.97#ibcon#about to read 3, iclass 21, count 0 2006.238.08:03:09.01#ibcon#read 3, iclass 21, count 0 2006.238.08:03:09.01#ibcon#about to read 4, iclass 21, count 0 2006.238.08:03:09.01#ibcon#read 4, iclass 21, count 0 2006.238.08:03:09.01#ibcon#about to read 5, iclass 21, count 0 2006.238.08:03:09.01#ibcon#read 5, iclass 21, count 0 2006.238.08:03:09.01#ibcon#about to read 6, iclass 21, count 0 2006.238.08:03:09.01#ibcon#read 6, iclass 21, count 0 2006.238.08:03:09.01#ibcon#end of sib2, iclass 21, count 0 2006.238.08:03:09.01#ibcon#*after write, iclass 21, count 0 2006.238.08:03:09.01#ibcon#*before return 0, iclass 21, count 0 2006.238.08:03:09.01#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:03:09.01#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:03:09.01#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.08:03:09.01#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.08:03:09.01$vc4f8/va=4,7 2006.238.08:03:09.01#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.238.08:03:09.01#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.238.08:03:09.01#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:09.01#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:03:09.07#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:03:09.07#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:03:09.07#ibcon#enter wrdev, iclass 23, count 2 2006.238.08:03:09.07#ibcon#first serial, iclass 23, count 2 2006.238.08:03:09.07#ibcon#enter sib2, iclass 23, count 2 2006.238.08:03:09.07#ibcon#flushed, iclass 23, count 2 2006.238.08:03:09.07#ibcon#about to write, iclass 23, count 2 2006.238.08:03:09.07#ibcon#wrote, iclass 23, count 2 2006.238.08:03:09.07#ibcon#about to read 3, iclass 23, count 2 2006.238.08:03:09.09#ibcon#read 3, iclass 23, count 2 2006.238.08:03:09.09#ibcon#about to read 4, iclass 23, count 2 2006.238.08:03:09.09#ibcon#read 4, iclass 23, count 2 2006.238.08:03:09.09#ibcon#about to read 5, iclass 23, count 2 2006.238.08:03:09.09#ibcon#read 5, iclass 23, count 2 2006.238.08:03:09.09#ibcon#about to read 6, iclass 23, count 2 2006.238.08:03:09.09#ibcon#read 6, iclass 23, count 2 2006.238.08:03:09.09#ibcon#end of sib2, iclass 23, count 2 2006.238.08:03:09.09#ibcon#*mode == 0, iclass 23, count 2 2006.238.08:03:09.09#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.238.08:03:09.09#ibcon#[25=AT04-07\r\n] 2006.238.08:03:09.09#ibcon#*before write, iclass 23, count 2 2006.238.08:03:09.09#ibcon#enter sib2, iclass 23, count 2 2006.238.08:03:09.09#ibcon#flushed, iclass 23, count 2 2006.238.08:03:09.09#ibcon#about to write, iclass 23, count 2 2006.238.08:03:09.09#ibcon#wrote, iclass 23, count 2 2006.238.08:03:09.09#ibcon#about to read 3, iclass 23, count 2 2006.238.08:03:09.12#ibcon#read 3, iclass 23, count 2 2006.238.08:03:09.12#ibcon#about to read 4, iclass 23, count 2 2006.238.08:03:09.12#ibcon#read 4, iclass 23, count 2 2006.238.08:03:09.12#ibcon#about to read 5, iclass 23, count 2 2006.238.08:03:09.12#ibcon#read 5, iclass 23, count 2 2006.238.08:03:09.12#ibcon#about to read 6, iclass 23, count 2 2006.238.08:03:09.12#ibcon#read 6, iclass 23, count 2 2006.238.08:03:09.12#ibcon#end of sib2, iclass 23, count 2 2006.238.08:03:09.12#ibcon#*after write, iclass 23, count 2 2006.238.08:03:09.12#ibcon#*before return 0, iclass 23, count 2 2006.238.08:03:09.12#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:03:09.12#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:03:09.12#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.238.08:03:09.12#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:09.12#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:03:09.24#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:03:09.24#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:03:09.24#ibcon#enter wrdev, iclass 23, count 0 2006.238.08:03:09.24#ibcon#first serial, iclass 23, count 0 2006.238.08:03:09.24#ibcon#enter sib2, iclass 23, count 0 2006.238.08:03:09.24#ibcon#flushed, iclass 23, count 0 2006.238.08:03:09.24#ibcon#about to write, iclass 23, count 0 2006.238.08:03:09.24#ibcon#wrote, iclass 23, count 0 2006.238.08:03:09.24#ibcon#about to read 3, iclass 23, count 0 2006.238.08:03:09.26#ibcon#read 3, iclass 23, count 0 2006.238.08:03:09.26#ibcon#about to read 4, iclass 23, count 0 2006.238.08:03:09.26#ibcon#read 4, iclass 23, count 0 2006.238.08:03:09.26#ibcon#about to read 5, iclass 23, count 0 2006.238.08:03:09.26#ibcon#read 5, iclass 23, count 0 2006.238.08:03:09.26#ibcon#about to read 6, iclass 23, count 0 2006.238.08:03:09.26#ibcon#read 6, iclass 23, count 0 2006.238.08:03:09.26#ibcon#end of sib2, iclass 23, count 0 2006.238.08:03:09.26#ibcon#*mode == 0, iclass 23, count 0 2006.238.08:03:09.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.08:03:09.26#ibcon#[25=USB\r\n] 2006.238.08:03:09.26#ibcon#*before write, iclass 23, count 0 2006.238.08:03:09.26#ibcon#enter sib2, iclass 23, count 0 2006.238.08:03:09.26#ibcon#flushed, iclass 23, count 0 2006.238.08:03:09.26#ibcon#about to write, iclass 23, count 0 2006.238.08:03:09.26#ibcon#wrote, iclass 23, count 0 2006.238.08:03:09.26#ibcon#about to read 3, iclass 23, count 0 2006.238.08:03:09.29#ibcon#read 3, iclass 23, count 0 2006.238.08:03:09.29#ibcon#about to read 4, iclass 23, count 0 2006.238.08:03:09.29#ibcon#read 4, iclass 23, count 0 2006.238.08:03:09.29#ibcon#about to read 5, iclass 23, count 0 2006.238.08:03:09.29#ibcon#read 5, iclass 23, count 0 2006.238.08:03:09.29#ibcon#about to read 6, iclass 23, count 0 2006.238.08:03:09.29#ibcon#read 6, iclass 23, count 0 2006.238.08:03:09.29#ibcon#end of sib2, iclass 23, count 0 2006.238.08:03:09.29#ibcon#*after write, iclass 23, count 0 2006.238.08:03:09.29#ibcon#*before return 0, iclass 23, count 0 2006.238.08:03:09.29#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:03:09.29#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:03:09.29#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.08:03:09.29#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.08:03:09.29$vc4f8/valo=5,652.99 2006.238.08:03:09.29#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.08:03:09.29#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.08:03:09.29#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:09.29#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:03:09.29#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:03:09.29#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:03:09.29#ibcon#enter wrdev, iclass 25, count 0 2006.238.08:03:09.29#ibcon#first serial, iclass 25, count 0 2006.238.08:03:09.29#ibcon#enter sib2, iclass 25, count 0 2006.238.08:03:09.29#ibcon#flushed, iclass 25, count 0 2006.238.08:03:09.29#ibcon#about to write, iclass 25, count 0 2006.238.08:03:09.29#ibcon#wrote, iclass 25, count 0 2006.238.08:03:09.29#ibcon#about to read 3, iclass 25, count 0 2006.238.08:03:09.31#ibcon#read 3, iclass 25, count 0 2006.238.08:03:09.31#ibcon#about to read 4, iclass 25, count 0 2006.238.08:03:09.31#ibcon#read 4, iclass 25, count 0 2006.238.08:03:09.31#ibcon#about to read 5, iclass 25, count 0 2006.238.08:03:09.31#ibcon#read 5, iclass 25, count 0 2006.238.08:03:09.31#ibcon#about to read 6, iclass 25, count 0 2006.238.08:03:09.31#ibcon#read 6, iclass 25, count 0 2006.238.08:03:09.31#ibcon#end of sib2, iclass 25, count 0 2006.238.08:03:09.31#ibcon#*mode == 0, iclass 25, count 0 2006.238.08:03:09.31#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.08:03:09.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:03:09.31#ibcon#*before write, iclass 25, count 0 2006.238.08:03:09.31#ibcon#enter sib2, iclass 25, count 0 2006.238.08:03:09.31#ibcon#flushed, iclass 25, count 0 2006.238.08:03:09.31#ibcon#about to write, iclass 25, count 0 2006.238.08:03:09.31#ibcon#wrote, iclass 25, count 0 2006.238.08:03:09.31#ibcon#about to read 3, iclass 25, count 0 2006.238.08:03:09.35#ibcon#read 3, iclass 25, count 0 2006.238.08:03:09.35#ibcon#about to read 4, iclass 25, count 0 2006.238.08:03:09.35#ibcon#read 4, iclass 25, count 0 2006.238.08:03:09.35#ibcon#about to read 5, iclass 25, count 0 2006.238.08:03:09.35#ibcon#read 5, iclass 25, count 0 2006.238.08:03:09.35#ibcon#about to read 6, iclass 25, count 0 2006.238.08:03:09.35#ibcon#read 6, iclass 25, count 0 2006.238.08:03:09.35#ibcon#end of sib2, iclass 25, count 0 2006.238.08:03:09.35#ibcon#*after write, iclass 25, count 0 2006.238.08:03:09.35#ibcon#*before return 0, iclass 25, count 0 2006.238.08:03:09.35#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:03:09.35#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:03:09.35#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.08:03:09.35#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.08:03:09.35$vc4f8/va=5,8 2006.238.08:03:09.35#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.238.08:03:09.35#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.238.08:03:09.35#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:09.35#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:03:09.41#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:03:09.41#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:03:09.41#ibcon#enter wrdev, iclass 27, count 2 2006.238.08:03:09.41#ibcon#first serial, iclass 27, count 2 2006.238.08:03:09.41#ibcon#enter sib2, iclass 27, count 2 2006.238.08:03:09.41#ibcon#flushed, iclass 27, count 2 2006.238.08:03:09.41#ibcon#about to write, iclass 27, count 2 2006.238.08:03:09.41#ibcon#wrote, iclass 27, count 2 2006.238.08:03:09.41#ibcon#about to read 3, iclass 27, count 2 2006.238.08:03:09.43#ibcon#read 3, iclass 27, count 2 2006.238.08:03:09.43#ibcon#about to read 4, iclass 27, count 2 2006.238.08:03:09.43#ibcon#read 4, iclass 27, count 2 2006.238.08:03:09.43#ibcon#about to read 5, iclass 27, count 2 2006.238.08:03:09.43#ibcon#read 5, iclass 27, count 2 2006.238.08:03:09.43#ibcon#about to read 6, iclass 27, count 2 2006.238.08:03:09.43#ibcon#read 6, iclass 27, count 2 2006.238.08:03:09.43#ibcon#end of sib2, iclass 27, count 2 2006.238.08:03:09.43#ibcon#*mode == 0, iclass 27, count 2 2006.238.08:03:09.43#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.238.08:03:09.43#ibcon#[25=AT05-08\r\n] 2006.238.08:03:09.43#ibcon#*before write, iclass 27, count 2 2006.238.08:03:09.43#ibcon#enter sib2, iclass 27, count 2 2006.238.08:03:09.43#ibcon#flushed, iclass 27, count 2 2006.238.08:03:09.43#ibcon#about to write, iclass 27, count 2 2006.238.08:03:09.43#ibcon#wrote, iclass 27, count 2 2006.238.08:03:09.43#ibcon#about to read 3, iclass 27, count 2 2006.238.08:03:09.46#ibcon#read 3, iclass 27, count 2 2006.238.08:03:09.46#ibcon#about to read 4, iclass 27, count 2 2006.238.08:03:09.46#ibcon#read 4, iclass 27, count 2 2006.238.08:03:09.46#ibcon#about to read 5, iclass 27, count 2 2006.238.08:03:09.46#ibcon#read 5, iclass 27, count 2 2006.238.08:03:09.46#ibcon#about to read 6, iclass 27, count 2 2006.238.08:03:09.46#ibcon#read 6, iclass 27, count 2 2006.238.08:03:09.46#ibcon#end of sib2, iclass 27, count 2 2006.238.08:03:09.46#ibcon#*after write, iclass 27, count 2 2006.238.08:03:09.46#ibcon#*before return 0, iclass 27, count 2 2006.238.08:03:09.46#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:03:09.46#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:03:09.46#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.238.08:03:09.46#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:09.46#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:03:09.58#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:03:09.58#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:03:09.58#ibcon#enter wrdev, iclass 27, count 0 2006.238.08:03:09.58#ibcon#first serial, iclass 27, count 0 2006.238.08:03:09.58#ibcon#enter sib2, iclass 27, count 0 2006.238.08:03:09.58#ibcon#flushed, iclass 27, count 0 2006.238.08:03:09.58#ibcon#about to write, iclass 27, count 0 2006.238.08:03:09.58#ibcon#wrote, iclass 27, count 0 2006.238.08:03:09.58#ibcon#about to read 3, iclass 27, count 0 2006.238.08:03:09.60#ibcon#read 3, iclass 27, count 0 2006.238.08:03:09.60#ibcon#about to read 4, iclass 27, count 0 2006.238.08:03:09.60#ibcon#read 4, iclass 27, count 0 2006.238.08:03:09.60#ibcon#about to read 5, iclass 27, count 0 2006.238.08:03:09.60#ibcon#read 5, iclass 27, count 0 2006.238.08:03:09.60#ibcon#about to read 6, iclass 27, count 0 2006.238.08:03:09.60#ibcon#read 6, iclass 27, count 0 2006.238.08:03:09.60#ibcon#end of sib2, iclass 27, count 0 2006.238.08:03:09.60#ibcon#*mode == 0, iclass 27, count 0 2006.238.08:03:09.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.08:03:09.60#ibcon#[25=USB\r\n] 2006.238.08:03:09.60#ibcon#*before write, iclass 27, count 0 2006.238.08:03:09.60#ibcon#enter sib2, iclass 27, count 0 2006.238.08:03:09.60#ibcon#flushed, iclass 27, count 0 2006.238.08:03:09.60#ibcon#about to write, iclass 27, count 0 2006.238.08:03:09.60#ibcon#wrote, iclass 27, count 0 2006.238.08:03:09.60#ibcon#about to read 3, iclass 27, count 0 2006.238.08:03:09.63#ibcon#read 3, iclass 27, count 0 2006.238.08:03:09.63#ibcon#about to read 4, iclass 27, count 0 2006.238.08:03:09.63#ibcon#read 4, iclass 27, count 0 2006.238.08:03:09.63#ibcon#about to read 5, iclass 27, count 0 2006.238.08:03:09.63#ibcon#read 5, iclass 27, count 0 2006.238.08:03:09.63#ibcon#about to read 6, iclass 27, count 0 2006.238.08:03:09.63#ibcon#read 6, iclass 27, count 0 2006.238.08:03:09.63#ibcon#end of sib2, iclass 27, count 0 2006.238.08:03:09.63#ibcon#*after write, iclass 27, count 0 2006.238.08:03:09.63#ibcon#*before return 0, iclass 27, count 0 2006.238.08:03:09.63#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:03:09.63#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:03:09.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.08:03:09.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.08:03:09.63$vc4f8/valo=6,772.99 2006.238.08:03:09.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.238.08:03:09.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.238.08:03:09.63#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:09.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:03:09.63#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:03:09.63#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:03:09.63#ibcon#enter wrdev, iclass 29, count 0 2006.238.08:03:09.63#ibcon#first serial, iclass 29, count 0 2006.238.08:03:09.63#ibcon#enter sib2, iclass 29, count 0 2006.238.08:03:09.63#ibcon#flushed, iclass 29, count 0 2006.238.08:03:09.63#ibcon#about to write, iclass 29, count 0 2006.238.08:03:09.63#ibcon#wrote, iclass 29, count 0 2006.238.08:03:09.63#ibcon#about to read 3, iclass 29, count 0 2006.238.08:03:09.65#ibcon#read 3, iclass 29, count 0 2006.238.08:03:09.65#ibcon#about to read 4, iclass 29, count 0 2006.238.08:03:09.65#ibcon#read 4, iclass 29, count 0 2006.238.08:03:09.65#ibcon#about to read 5, iclass 29, count 0 2006.238.08:03:09.65#ibcon#read 5, iclass 29, count 0 2006.238.08:03:09.65#ibcon#about to read 6, iclass 29, count 0 2006.238.08:03:09.65#ibcon#read 6, iclass 29, count 0 2006.238.08:03:09.65#ibcon#end of sib2, iclass 29, count 0 2006.238.08:03:09.65#ibcon#*mode == 0, iclass 29, count 0 2006.238.08:03:09.65#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.08:03:09.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:03:09.65#ibcon#*before write, iclass 29, count 0 2006.238.08:03:09.65#ibcon#enter sib2, iclass 29, count 0 2006.238.08:03:09.65#ibcon#flushed, iclass 29, count 0 2006.238.08:03:09.65#ibcon#about to write, iclass 29, count 0 2006.238.08:03:09.65#ibcon#wrote, iclass 29, count 0 2006.238.08:03:09.65#ibcon#about to read 3, iclass 29, count 0 2006.238.08:03:09.69#ibcon#read 3, iclass 29, count 0 2006.238.08:03:09.69#ibcon#about to read 4, iclass 29, count 0 2006.238.08:03:09.69#ibcon#read 4, iclass 29, count 0 2006.238.08:03:09.69#ibcon#about to read 5, iclass 29, count 0 2006.238.08:03:09.69#ibcon#read 5, iclass 29, count 0 2006.238.08:03:09.69#ibcon#about to read 6, iclass 29, count 0 2006.238.08:03:09.69#ibcon#read 6, iclass 29, count 0 2006.238.08:03:09.69#ibcon#end of sib2, iclass 29, count 0 2006.238.08:03:09.69#ibcon#*after write, iclass 29, count 0 2006.238.08:03:09.69#ibcon#*before return 0, iclass 29, count 0 2006.238.08:03:09.69#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:03:09.69#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:03:09.69#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.08:03:09.69#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.08:03:09.69$vc4f8/va=6,7 2006.238.08:03:09.69#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.238.08:03:09.69#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.238.08:03:09.69#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:09.69#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:03:09.75#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:03:09.75#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:03:09.75#ibcon#enter wrdev, iclass 31, count 2 2006.238.08:03:09.75#ibcon#first serial, iclass 31, count 2 2006.238.08:03:09.75#ibcon#enter sib2, iclass 31, count 2 2006.238.08:03:09.75#ibcon#flushed, iclass 31, count 2 2006.238.08:03:09.75#ibcon#about to write, iclass 31, count 2 2006.238.08:03:09.75#ibcon#wrote, iclass 31, count 2 2006.238.08:03:09.75#ibcon#about to read 3, iclass 31, count 2 2006.238.08:03:09.77#ibcon#read 3, iclass 31, count 2 2006.238.08:03:09.77#ibcon#about to read 4, iclass 31, count 2 2006.238.08:03:09.77#ibcon#read 4, iclass 31, count 2 2006.238.08:03:09.77#ibcon#about to read 5, iclass 31, count 2 2006.238.08:03:09.77#ibcon#read 5, iclass 31, count 2 2006.238.08:03:09.77#ibcon#about to read 6, iclass 31, count 2 2006.238.08:03:09.77#ibcon#read 6, iclass 31, count 2 2006.238.08:03:09.77#ibcon#end of sib2, iclass 31, count 2 2006.238.08:03:09.77#ibcon#*mode == 0, iclass 31, count 2 2006.238.08:03:09.77#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.238.08:03:09.77#ibcon#[25=AT06-07\r\n] 2006.238.08:03:09.77#ibcon#*before write, iclass 31, count 2 2006.238.08:03:09.77#ibcon#enter sib2, iclass 31, count 2 2006.238.08:03:09.77#ibcon#flushed, iclass 31, count 2 2006.238.08:03:09.77#ibcon#about to write, iclass 31, count 2 2006.238.08:03:09.77#ibcon#wrote, iclass 31, count 2 2006.238.08:03:09.77#ibcon#about to read 3, iclass 31, count 2 2006.238.08:03:09.80#ibcon#read 3, iclass 31, count 2 2006.238.08:03:09.80#ibcon#about to read 4, iclass 31, count 2 2006.238.08:03:09.80#ibcon#read 4, iclass 31, count 2 2006.238.08:03:09.80#ibcon#about to read 5, iclass 31, count 2 2006.238.08:03:09.80#ibcon#read 5, iclass 31, count 2 2006.238.08:03:09.80#ibcon#about to read 6, iclass 31, count 2 2006.238.08:03:09.80#ibcon#read 6, iclass 31, count 2 2006.238.08:03:09.80#ibcon#end of sib2, iclass 31, count 2 2006.238.08:03:09.80#ibcon#*after write, iclass 31, count 2 2006.238.08:03:09.80#ibcon#*before return 0, iclass 31, count 2 2006.238.08:03:09.80#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:03:09.80#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:03:09.80#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.238.08:03:09.80#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:09.80#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:03:09.92#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:03:09.92#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:03:09.92#ibcon#enter wrdev, iclass 31, count 0 2006.238.08:03:09.92#ibcon#first serial, iclass 31, count 0 2006.238.08:03:09.92#ibcon#enter sib2, iclass 31, count 0 2006.238.08:03:09.92#ibcon#flushed, iclass 31, count 0 2006.238.08:03:09.92#ibcon#about to write, iclass 31, count 0 2006.238.08:03:09.92#ibcon#wrote, iclass 31, count 0 2006.238.08:03:09.92#ibcon#about to read 3, iclass 31, count 0 2006.238.08:03:09.94#ibcon#read 3, iclass 31, count 0 2006.238.08:03:09.94#ibcon#about to read 4, iclass 31, count 0 2006.238.08:03:09.94#ibcon#read 4, iclass 31, count 0 2006.238.08:03:09.94#ibcon#about to read 5, iclass 31, count 0 2006.238.08:03:09.94#ibcon#read 5, iclass 31, count 0 2006.238.08:03:09.94#ibcon#about to read 6, iclass 31, count 0 2006.238.08:03:09.94#ibcon#read 6, iclass 31, count 0 2006.238.08:03:09.94#ibcon#end of sib2, iclass 31, count 0 2006.238.08:03:09.94#ibcon#*mode == 0, iclass 31, count 0 2006.238.08:03:09.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.08:03:09.94#ibcon#[25=USB\r\n] 2006.238.08:03:09.94#ibcon#*before write, iclass 31, count 0 2006.238.08:03:09.94#ibcon#enter sib2, iclass 31, count 0 2006.238.08:03:09.94#ibcon#flushed, iclass 31, count 0 2006.238.08:03:09.94#ibcon#about to write, iclass 31, count 0 2006.238.08:03:09.94#ibcon#wrote, iclass 31, count 0 2006.238.08:03:09.94#ibcon#about to read 3, iclass 31, count 0 2006.238.08:03:09.97#ibcon#read 3, iclass 31, count 0 2006.238.08:03:09.97#ibcon#about to read 4, iclass 31, count 0 2006.238.08:03:09.97#ibcon#read 4, iclass 31, count 0 2006.238.08:03:09.97#ibcon#about to read 5, iclass 31, count 0 2006.238.08:03:09.97#ibcon#read 5, iclass 31, count 0 2006.238.08:03:09.97#ibcon#about to read 6, iclass 31, count 0 2006.238.08:03:09.97#ibcon#read 6, iclass 31, count 0 2006.238.08:03:09.97#ibcon#end of sib2, iclass 31, count 0 2006.238.08:03:09.97#ibcon#*after write, iclass 31, count 0 2006.238.08:03:09.97#ibcon#*before return 0, iclass 31, count 0 2006.238.08:03:09.97#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:03:09.97#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:03:09.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.08:03:09.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.08:03:09.97$vc4f8/valo=7,832.99 2006.238.08:03:09.97#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.08:03:09.97#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.08:03:09.97#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:09.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:03:09.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:03:09.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:03:09.97#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:03:09.97#ibcon#first serial, iclass 33, count 0 2006.238.08:03:09.97#ibcon#enter sib2, iclass 33, count 0 2006.238.08:03:09.97#ibcon#flushed, iclass 33, count 0 2006.238.08:03:09.97#ibcon#about to write, iclass 33, count 0 2006.238.08:03:09.97#ibcon#wrote, iclass 33, count 0 2006.238.08:03:09.97#ibcon#about to read 3, iclass 33, count 0 2006.238.08:03:09.99#ibcon#read 3, iclass 33, count 0 2006.238.08:03:09.99#ibcon#about to read 4, iclass 33, count 0 2006.238.08:03:09.99#ibcon#read 4, iclass 33, count 0 2006.238.08:03:09.99#ibcon#about to read 5, iclass 33, count 0 2006.238.08:03:09.99#ibcon#read 5, iclass 33, count 0 2006.238.08:03:09.99#ibcon#about to read 6, iclass 33, count 0 2006.238.08:03:09.99#ibcon#read 6, iclass 33, count 0 2006.238.08:03:09.99#ibcon#end of sib2, iclass 33, count 0 2006.238.08:03:09.99#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:03:09.99#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:03:09.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:03:09.99#ibcon#*before write, iclass 33, count 0 2006.238.08:03:09.99#ibcon#enter sib2, iclass 33, count 0 2006.238.08:03:09.99#ibcon#flushed, iclass 33, count 0 2006.238.08:03:09.99#ibcon#about to write, iclass 33, count 0 2006.238.08:03:09.99#ibcon#wrote, iclass 33, count 0 2006.238.08:03:09.99#ibcon#about to read 3, iclass 33, count 0 2006.238.08:03:10.03#ibcon#read 3, iclass 33, count 0 2006.238.08:03:10.03#ibcon#about to read 4, iclass 33, count 0 2006.238.08:03:10.03#ibcon#read 4, iclass 33, count 0 2006.238.08:03:10.03#ibcon#about to read 5, iclass 33, count 0 2006.238.08:03:10.03#ibcon#read 5, iclass 33, count 0 2006.238.08:03:10.03#ibcon#about to read 6, iclass 33, count 0 2006.238.08:03:10.03#ibcon#read 6, iclass 33, count 0 2006.238.08:03:10.03#ibcon#end of sib2, iclass 33, count 0 2006.238.08:03:10.03#ibcon#*after write, iclass 33, count 0 2006.238.08:03:10.03#ibcon#*before return 0, iclass 33, count 0 2006.238.08:03:10.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:03:10.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:03:10.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:03:10.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:03:10.03$vc4f8/va=7,7 2006.238.08:03:10.03#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.238.08:03:10.03#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.238.08:03:10.03#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:10.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:03:10.09#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:03:10.09#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:03:10.09#ibcon#enter wrdev, iclass 35, count 2 2006.238.08:03:10.09#ibcon#first serial, iclass 35, count 2 2006.238.08:03:10.09#ibcon#enter sib2, iclass 35, count 2 2006.238.08:03:10.09#ibcon#flushed, iclass 35, count 2 2006.238.08:03:10.09#ibcon#about to write, iclass 35, count 2 2006.238.08:03:10.09#ibcon#wrote, iclass 35, count 2 2006.238.08:03:10.09#ibcon#about to read 3, iclass 35, count 2 2006.238.08:03:10.11#ibcon#read 3, iclass 35, count 2 2006.238.08:03:10.11#ibcon#about to read 4, iclass 35, count 2 2006.238.08:03:10.11#ibcon#read 4, iclass 35, count 2 2006.238.08:03:10.11#ibcon#about to read 5, iclass 35, count 2 2006.238.08:03:10.11#ibcon#read 5, iclass 35, count 2 2006.238.08:03:10.11#ibcon#about to read 6, iclass 35, count 2 2006.238.08:03:10.11#ibcon#read 6, iclass 35, count 2 2006.238.08:03:10.11#ibcon#end of sib2, iclass 35, count 2 2006.238.08:03:10.11#ibcon#*mode == 0, iclass 35, count 2 2006.238.08:03:10.11#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.238.08:03:10.11#ibcon#[25=AT07-07\r\n] 2006.238.08:03:10.11#ibcon#*before write, iclass 35, count 2 2006.238.08:03:10.11#ibcon#enter sib2, iclass 35, count 2 2006.238.08:03:10.11#ibcon#flushed, iclass 35, count 2 2006.238.08:03:10.11#ibcon#about to write, iclass 35, count 2 2006.238.08:03:10.11#ibcon#wrote, iclass 35, count 2 2006.238.08:03:10.11#ibcon#about to read 3, iclass 35, count 2 2006.238.08:03:10.14#ibcon#read 3, iclass 35, count 2 2006.238.08:03:10.14#ibcon#about to read 4, iclass 35, count 2 2006.238.08:03:10.14#ibcon#read 4, iclass 35, count 2 2006.238.08:03:10.14#ibcon#about to read 5, iclass 35, count 2 2006.238.08:03:10.14#ibcon#read 5, iclass 35, count 2 2006.238.08:03:10.14#ibcon#about to read 6, iclass 35, count 2 2006.238.08:03:10.14#ibcon#read 6, iclass 35, count 2 2006.238.08:03:10.14#ibcon#end of sib2, iclass 35, count 2 2006.238.08:03:10.14#ibcon#*after write, iclass 35, count 2 2006.238.08:03:10.14#ibcon#*before return 0, iclass 35, count 2 2006.238.08:03:10.14#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:03:10.14#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:03:10.14#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.238.08:03:10.14#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:10.14#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:03:10.17#abcon#<5=/04 1.9 3.4 25.44 881012.2\r\n> 2006.238.08:03:10.19#abcon#{5=INTERFACE CLEAR} 2006.238.08:03:10.25#abcon#[5=S1D000X0/0*\r\n] 2006.238.08:03:10.26#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:03:10.26#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:03:10.26#ibcon#enter wrdev, iclass 35, count 0 2006.238.08:03:10.26#ibcon#first serial, iclass 35, count 0 2006.238.08:03:10.26#ibcon#enter sib2, iclass 35, count 0 2006.238.08:03:10.26#ibcon#flushed, iclass 35, count 0 2006.238.08:03:10.26#ibcon#about to write, iclass 35, count 0 2006.238.08:03:10.26#ibcon#wrote, iclass 35, count 0 2006.238.08:03:10.26#ibcon#about to read 3, iclass 35, count 0 2006.238.08:03:10.28#ibcon#read 3, iclass 35, count 0 2006.238.08:03:10.28#ibcon#about to read 4, iclass 35, count 0 2006.238.08:03:10.28#ibcon#read 4, iclass 35, count 0 2006.238.08:03:10.28#ibcon#about to read 5, iclass 35, count 0 2006.238.08:03:10.28#ibcon#read 5, iclass 35, count 0 2006.238.08:03:10.28#ibcon#about to read 6, iclass 35, count 0 2006.238.08:03:10.28#ibcon#read 6, iclass 35, count 0 2006.238.08:03:10.28#ibcon#end of sib2, iclass 35, count 0 2006.238.08:03:10.28#ibcon#*mode == 0, iclass 35, count 0 2006.238.08:03:10.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.08:03:10.28#ibcon#[25=USB\r\n] 2006.238.08:03:10.28#ibcon#*before write, iclass 35, count 0 2006.238.08:03:10.28#ibcon#enter sib2, iclass 35, count 0 2006.238.08:03:10.28#ibcon#flushed, iclass 35, count 0 2006.238.08:03:10.28#ibcon#about to write, iclass 35, count 0 2006.238.08:03:10.28#ibcon#wrote, iclass 35, count 0 2006.238.08:03:10.28#ibcon#about to read 3, iclass 35, count 0 2006.238.08:03:10.31#ibcon#read 3, iclass 35, count 0 2006.238.08:03:10.31#ibcon#about to read 4, iclass 35, count 0 2006.238.08:03:10.31#ibcon#read 4, iclass 35, count 0 2006.238.08:03:10.31#ibcon#about to read 5, iclass 35, count 0 2006.238.08:03:10.31#ibcon#read 5, iclass 35, count 0 2006.238.08:03:10.31#ibcon#about to read 6, iclass 35, count 0 2006.238.08:03:10.31#ibcon#read 6, iclass 35, count 0 2006.238.08:03:10.31#ibcon#end of sib2, iclass 35, count 0 2006.238.08:03:10.31#ibcon#*after write, iclass 35, count 0 2006.238.08:03:10.31#ibcon#*before return 0, iclass 35, count 0 2006.238.08:03:10.31#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:03:10.31#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:03:10.31#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.08:03:10.31#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.08:03:10.31$vc4f8/valo=8,852.99 2006.238.08:03:10.31#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.08:03:10.31#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.08:03:10.31#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:10.31#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:03:10.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:03:10.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:03:10.31#ibcon#enter wrdev, iclass 3, count 0 2006.238.08:03:10.31#ibcon#first serial, iclass 3, count 0 2006.238.08:03:10.31#ibcon#enter sib2, iclass 3, count 0 2006.238.08:03:10.31#ibcon#flushed, iclass 3, count 0 2006.238.08:03:10.31#ibcon#about to write, iclass 3, count 0 2006.238.08:03:10.31#ibcon#wrote, iclass 3, count 0 2006.238.08:03:10.31#ibcon#about to read 3, iclass 3, count 0 2006.238.08:03:10.33#ibcon#read 3, iclass 3, count 0 2006.238.08:03:10.33#ibcon#about to read 4, iclass 3, count 0 2006.238.08:03:10.33#ibcon#read 4, iclass 3, count 0 2006.238.08:03:10.33#ibcon#about to read 5, iclass 3, count 0 2006.238.08:03:10.33#ibcon#read 5, iclass 3, count 0 2006.238.08:03:10.33#ibcon#about to read 6, iclass 3, count 0 2006.238.08:03:10.33#ibcon#read 6, iclass 3, count 0 2006.238.08:03:10.33#ibcon#end of sib2, iclass 3, count 0 2006.238.08:03:10.33#ibcon#*mode == 0, iclass 3, count 0 2006.238.08:03:10.33#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.08:03:10.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:03:10.33#ibcon#*before write, iclass 3, count 0 2006.238.08:03:10.33#ibcon#enter sib2, iclass 3, count 0 2006.238.08:03:10.33#ibcon#flushed, iclass 3, count 0 2006.238.08:03:10.33#ibcon#about to write, iclass 3, count 0 2006.238.08:03:10.33#ibcon#wrote, iclass 3, count 0 2006.238.08:03:10.33#ibcon#about to read 3, iclass 3, count 0 2006.238.08:03:10.37#ibcon#read 3, iclass 3, count 0 2006.238.08:03:10.37#ibcon#about to read 4, iclass 3, count 0 2006.238.08:03:10.37#ibcon#read 4, iclass 3, count 0 2006.238.08:03:10.37#ibcon#about to read 5, iclass 3, count 0 2006.238.08:03:10.37#ibcon#read 5, iclass 3, count 0 2006.238.08:03:10.37#ibcon#about to read 6, iclass 3, count 0 2006.238.08:03:10.37#ibcon#read 6, iclass 3, count 0 2006.238.08:03:10.37#ibcon#end of sib2, iclass 3, count 0 2006.238.08:03:10.37#ibcon#*after write, iclass 3, count 0 2006.238.08:03:10.37#ibcon#*before return 0, iclass 3, count 0 2006.238.08:03:10.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:03:10.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:03:10.37#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.08:03:10.37#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.08:03:10.37$vc4f8/va=8,7 2006.238.08:03:10.37#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.238.08:03:10.37#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.238.08:03:10.37#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:10.37#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:03:10.43#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:03:10.43#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:03:10.43#ibcon#enter wrdev, iclass 5, count 2 2006.238.08:03:10.43#ibcon#first serial, iclass 5, count 2 2006.238.08:03:10.43#ibcon#enter sib2, iclass 5, count 2 2006.238.08:03:10.43#ibcon#flushed, iclass 5, count 2 2006.238.08:03:10.43#ibcon#about to write, iclass 5, count 2 2006.238.08:03:10.43#ibcon#wrote, iclass 5, count 2 2006.238.08:03:10.43#ibcon#about to read 3, iclass 5, count 2 2006.238.08:03:10.45#ibcon#read 3, iclass 5, count 2 2006.238.08:03:10.45#ibcon#about to read 4, iclass 5, count 2 2006.238.08:03:10.45#ibcon#read 4, iclass 5, count 2 2006.238.08:03:10.45#ibcon#about to read 5, iclass 5, count 2 2006.238.08:03:10.45#ibcon#read 5, iclass 5, count 2 2006.238.08:03:10.45#ibcon#about to read 6, iclass 5, count 2 2006.238.08:03:10.45#ibcon#read 6, iclass 5, count 2 2006.238.08:03:10.45#ibcon#end of sib2, iclass 5, count 2 2006.238.08:03:10.45#ibcon#*mode == 0, iclass 5, count 2 2006.238.08:03:10.45#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.238.08:03:10.45#ibcon#[25=AT08-07\r\n] 2006.238.08:03:10.45#ibcon#*before write, iclass 5, count 2 2006.238.08:03:10.45#ibcon#enter sib2, iclass 5, count 2 2006.238.08:03:10.45#ibcon#flushed, iclass 5, count 2 2006.238.08:03:10.45#ibcon#about to write, iclass 5, count 2 2006.238.08:03:10.45#ibcon#wrote, iclass 5, count 2 2006.238.08:03:10.45#ibcon#about to read 3, iclass 5, count 2 2006.238.08:03:10.48#ibcon#read 3, iclass 5, count 2 2006.238.08:03:10.48#ibcon#about to read 4, iclass 5, count 2 2006.238.08:03:10.48#ibcon#read 4, iclass 5, count 2 2006.238.08:03:10.48#ibcon#about to read 5, iclass 5, count 2 2006.238.08:03:10.48#ibcon#read 5, iclass 5, count 2 2006.238.08:03:10.48#ibcon#about to read 6, iclass 5, count 2 2006.238.08:03:10.48#ibcon#read 6, iclass 5, count 2 2006.238.08:03:10.48#ibcon#end of sib2, iclass 5, count 2 2006.238.08:03:10.48#ibcon#*after write, iclass 5, count 2 2006.238.08:03:10.48#ibcon#*before return 0, iclass 5, count 2 2006.238.08:03:10.48#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:03:10.48#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:03:10.48#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.238.08:03:10.48#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:10.48#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:03:10.60#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:03:10.60#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:03:10.60#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:03:10.60#ibcon#first serial, iclass 5, count 0 2006.238.08:03:10.60#ibcon#enter sib2, iclass 5, count 0 2006.238.08:03:10.60#ibcon#flushed, iclass 5, count 0 2006.238.08:03:10.60#ibcon#about to write, iclass 5, count 0 2006.238.08:03:10.60#ibcon#wrote, iclass 5, count 0 2006.238.08:03:10.60#ibcon#about to read 3, iclass 5, count 0 2006.238.08:03:10.62#ibcon#read 3, iclass 5, count 0 2006.238.08:03:10.62#ibcon#about to read 4, iclass 5, count 0 2006.238.08:03:10.62#ibcon#read 4, iclass 5, count 0 2006.238.08:03:10.62#ibcon#about to read 5, iclass 5, count 0 2006.238.08:03:10.62#ibcon#read 5, iclass 5, count 0 2006.238.08:03:10.62#ibcon#about to read 6, iclass 5, count 0 2006.238.08:03:10.62#ibcon#read 6, iclass 5, count 0 2006.238.08:03:10.62#ibcon#end of sib2, iclass 5, count 0 2006.238.08:03:10.62#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:03:10.62#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:03:10.62#ibcon#[25=USB\r\n] 2006.238.08:03:10.62#ibcon#*before write, iclass 5, count 0 2006.238.08:03:10.62#ibcon#enter sib2, iclass 5, count 0 2006.238.08:03:10.62#ibcon#flushed, iclass 5, count 0 2006.238.08:03:10.62#ibcon#about to write, iclass 5, count 0 2006.238.08:03:10.62#ibcon#wrote, iclass 5, count 0 2006.238.08:03:10.62#ibcon#about to read 3, iclass 5, count 0 2006.238.08:03:10.65#ibcon#read 3, iclass 5, count 0 2006.238.08:03:10.65#ibcon#about to read 4, iclass 5, count 0 2006.238.08:03:10.65#ibcon#read 4, iclass 5, count 0 2006.238.08:03:10.65#ibcon#about to read 5, iclass 5, count 0 2006.238.08:03:10.65#ibcon#read 5, iclass 5, count 0 2006.238.08:03:10.65#ibcon#about to read 6, iclass 5, count 0 2006.238.08:03:10.65#ibcon#read 6, iclass 5, count 0 2006.238.08:03:10.65#ibcon#end of sib2, iclass 5, count 0 2006.238.08:03:10.65#ibcon#*after write, iclass 5, count 0 2006.238.08:03:10.65#ibcon#*before return 0, iclass 5, count 0 2006.238.08:03:10.65#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:03:10.65#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:03:10.65#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:03:10.65#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:03:10.65$vc4f8/vblo=1,632.99 2006.238.08:03:10.65#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.238.08:03:10.65#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.238.08:03:10.65#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:10.65#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:03:10.65#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:03:10.65#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:03:10.65#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:03:10.65#ibcon#first serial, iclass 7, count 0 2006.238.08:03:10.65#ibcon#enter sib2, iclass 7, count 0 2006.238.08:03:10.65#ibcon#flushed, iclass 7, count 0 2006.238.08:03:10.65#ibcon#about to write, iclass 7, count 0 2006.238.08:03:10.65#ibcon#wrote, iclass 7, count 0 2006.238.08:03:10.65#ibcon#about to read 3, iclass 7, count 0 2006.238.08:03:10.67#ibcon#read 3, iclass 7, count 0 2006.238.08:03:10.67#ibcon#about to read 4, iclass 7, count 0 2006.238.08:03:10.67#ibcon#read 4, iclass 7, count 0 2006.238.08:03:10.67#ibcon#about to read 5, iclass 7, count 0 2006.238.08:03:10.67#ibcon#read 5, iclass 7, count 0 2006.238.08:03:10.67#ibcon#about to read 6, iclass 7, count 0 2006.238.08:03:10.67#ibcon#read 6, iclass 7, count 0 2006.238.08:03:10.67#ibcon#end of sib2, iclass 7, count 0 2006.238.08:03:10.67#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:03:10.67#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:03:10.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:03:10.67#ibcon#*before write, iclass 7, count 0 2006.238.08:03:10.67#ibcon#enter sib2, iclass 7, count 0 2006.238.08:03:10.67#ibcon#flushed, iclass 7, count 0 2006.238.08:03:10.67#ibcon#about to write, iclass 7, count 0 2006.238.08:03:10.67#ibcon#wrote, iclass 7, count 0 2006.238.08:03:10.67#ibcon#about to read 3, iclass 7, count 0 2006.238.08:03:10.71#ibcon#read 3, iclass 7, count 0 2006.238.08:03:10.71#ibcon#about to read 4, iclass 7, count 0 2006.238.08:03:10.71#ibcon#read 4, iclass 7, count 0 2006.238.08:03:10.71#ibcon#about to read 5, iclass 7, count 0 2006.238.08:03:10.71#ibcon#read 5, iclass 7, count 0 2006.238.08:03:10.71#ibcon#about to read 6, iclass 7, count 0 2006.238.08:03:10.71#ibcon#read 6, iclass 7, count 0 2006.238.08:03:10.71#ibcon#end of sib2, iclass 7, count 0 2006.238.08:03:10.71#ibcon#*after write, iclass 7, count 0 2006.238.08:03:10.71#ibcon#*before return 0, iclass 7, count 0 2006.238.08:03:10.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:03:10.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:03:10.71#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:03:10.71#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:03:10.71$vc4f8/vb=1,4 2006.238.08:03:10.71#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.238.08:03:10.71#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.238.08:03:10.71#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:10.71#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:03:10.71#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:03:10.71#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:03:10.71#ibcon#enter wrdev, iclass 11, count 2 2006.238.08:03:10.71#ibcon#first serial, iclass 11, count 2 2006.238.08:03:10.71#ibcon#enter sib2, iclass 11, count 2 2006.238.08:03:10.71#ibcon#flushed, iclass 11, count 2 2006.238.08:03:10.71#ibcon#about to write, iclass 11, count 2 2006.238.08:03:10.71#ibcon#wrote, iclass 11, count 2 2006.238.08:03:10.71#ibcon#about to read 3, iclass 11, count 2 2006.238.08:03:10.73#ibcon#read 3, iclass 11, count 2 2006.238.08:03:10.73#ibcon#about to read 4, iclass 11, count 2 2006.238.08:03:10.73#ibcon#read 4, iclass 11, count 2 2006.238.08:03:10.73#ibcon#about to read 5, iclass 11, count 2 2006.238.08:03:10.73#ibcon#read 5, iclass 11, count 2 2006.238.08:03:10.73#ibcon#about to read 6, iclass 11, count 2 2006.238.08:03:10.73#ibcon#read 6, iclass 11, count 2 2006.238.08:03:10.73#ibcon#end of sib2, iclass 11, count 2 2006.238.08:03:10.73#ibcon#*mode == 0, iclass 11, count 2 2006.238.08:03:10.73#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.238.08:03:10.73#ibcon#[27=AT01-04\r\n] 2006.238.08:03:10.73#ibcon#*before write, iclass 11, count 2 2006.238.08:03:10.73#ibcon#enter sib2, iclass 11, count 2 2006.238.08:03:10.73#ibcon#flushed, iclass 11, count 2 2006.238.08:03:10.73#ibcon#about to write, iclass 11, count 2 2006.238.08:03:10.73#ibcon#wrote, iclass 11, count 2 2006.238.08:03:10.73#ibcon#about to read 3, iclass 11, count 2 2006.238.08:03:10.76#ibcon#read 3, iclass 11, count 2 2006.238.08:03:10.76#ibcon#about to read 4, iclass 11, count 2 2006.238.08:03:10.76#ibcon#read 4, iclass 11, count 2 2006.238.08:03:10.76#ibcon#about to read 5, iclass 11, count 2 2006.238.08:03:10.76#ibcon#read 5, iclass 11, count 2 2006.238.08:03:10.76#ibcon#about to read 6, iclass 11, count 2 2006.238.08:03:10.76#ibcon#read 6, iclass 11, count 2 2006.238.08:03:10.76#ibcon#end of sib2, iclass 11, count 2 2006.238.08:03:10.76#ibcon#*after write, iclass 11, count 2 2006.238.08:03:10.76#ibcon#*before return 0, iclass 11, count 2 2006.238.08:03:10.76#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:03:10.76#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:03:10.76#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.238.08:03:10.76#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:10.76#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:03:10.88#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:03:10.88#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:03:10.88#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:03:10.88#ibcon#first serial, iclass 11, count 0 2006.238.08:03:10.88#ibcon#enter sib2, iclass 11, count 0 2006.238.08:03:10.88#ibcon#flushed, iclass 11, count 0 2006.238.08:03:10.88#ibcon#about to write, iclass 11, count 0 2006.238.08:03:10.88#ibcon#wrote, iclass 11, count 0 2006.238.08:03:10.88#ibcon#about to read 3, iclass 11, count 0 2006.238.08:03:10.90#ibcon#read 3, iclass 11, count 0 2006.238.08:03:10.90#ibcon#about to read 4, iclass 11, count 0 2006.238.08:03:10.90#ibcon#read 4, iclass 11, count 0 2006.238.08:03:10.90#ibcon#about to read 5, iclass 11, count 0 2006.238.08:03:10.90#ibcon#read 5, iclass 11, count 0 2006.238.08:03:10.90#ibcon#about to read 6, iclass 11, count 0 2006.238.08:03:10.90#ibcon#read 6, iclass 11, count 0 2006.238.08:03:10.90#ibcon#end of sib2, iclass 11, count 0 2006.238.08:03:10.90#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:03:10.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:03:10.90#ibcon#[27=USB\r\n] 2006.238.08:03:10.90#ibcon#*before write, iclass 11, count 0 2006.238.08:03:10.90#ibcon#enter sib2, iclass 11, count 0 2006.238.08:03:10.90#ibcon#flushed, iclass 11, count 0 2006.238.08:03:10.90#ibcon#about to write, iclass 11, count 0 2006.238.08:03:10.90#ibcon#wrote, iclass 11, count 0 2006.238.08:03:10.90#ibcon#about to read 3, iclass 11, count 0 2006.238.08:03:10.93#ibcon#read 3, iclass 11, count 0 2006.238.08:03:10.93#ibcon#about to read 4, iclass 11, count 0 2006.238.08:03:10.93#ibcon#read 4, iclass 11, count 0 2006.238.08:03:10.93#ibcon#about to read 5, iclass 11, count 0 2006.238.08:03:10.93#ibcon#read 5, iclass 11, count 0 2006.238.08:03:10.93#ibcon#about to read 6, iclass 11, count 0 2006.238.08:03:10.93#ibcon#read 6, iclass 11, count 0 2006.238.08:03:10.93#ibcon#end of sib2, iclass 11, count 0 2006.238.08:03:10.93#ibcon#*after write, iclass 11, count 0 2006.238.08:03:10.93#ibcon#*before return 0, iclass 11, count 0 2006.238.08:03:10.93#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:03:10.93#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:03:10.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:03:10.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:03:10.93$vc4f8/vblo=2,640.99 2006.238.08:03:10.93#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.08:03:10.93#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.08:03:10.93#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:10.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:03:10.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:03:10.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:03:10.93#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:03:10.93#ibcon#first serial, iclass 13, count 0 2006.238.08:03:10.93#ibcon#enter sib2, iclass 13, count 0 2006.238.08:03:10.93#ibcon#flushed, iclass 13, count 0 2006.238.08:03:10.93#ibcon#about to write, iclass 13, count 0 2006.238.08:03:10.93#ibcon#wrote, iclass 13, count 0 2006.238.08:03:10.93#ibcon#about to read 3, iclass 13, count 0 2006.238.08:03:10.95#ibcon#read 3, iclass 13, count 0 2006.238.08:03:10.95#ibcon#about to read 4, iclass 13, count 0 2006.238.08:03:10.95#ibcon#read 4, iclass 13, count 0 2006.238.08:03:10.95#ibcon#about to read 5, iclass 13, count 0 2006.238.08:03:10.95#ibcon#read 5, iclass 13, count 0 2006.238.08:03:10.95#ibcon#about to read 6, iclass 13, count 0 2006.238.08:03:10.95#ibcon#read 6, iclass 13, count 0 2006.238.08:03:10.95#ibcon#end of sib2, iclass 13, count 0 2006.238.08:03:10.95#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:03:10.95#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:03:10.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:03:10.95#ibcon#*before write, iclass 13, count 0 2006.238.08:03:10.95#ibcon#enter sib2, iclass 13, count 0 2006.238.08:03:10.95#ibcon#flushed, iclass 13, count 0 2006.238.08:03:10.95#ibcon#about to write, iclass 13, count 0 2006.238.08:03:10.95#ibcon#wrote, iclass 13, count 0 2006.238.08:03:10.95#ibcon#about to read 3, iclass 13, count 0 2006.238.08:03:10.99#ibcon#read 3, iclass 13, count 0 2006.238.08:03:10.99#ibcon#about to read 4, iclass 13, count 0 2006.238.08:03:10.99#ibcon#read 4, iclass 13, count 0 2006.238.08:03:10.99#ibcon#about to read 5, iclass 13, count 0 2006.238.08:03:10.99#ibcon#read 5, iclass 13, count 0 2006.238.08:03:10.99#ibcon#about to read 6, iclass 13, count 0 2006.238.08:03:10.99#ibcon#read 6, iclass 13, count 0 2006.238.08:03:10.99#ibcon#end of sib2, iclass 13, count 0 2006.238.08:03:10.99#ibcon#*after write, iclass 13, count 0 2006.238.08:03:10.99#ibcon#*before return 0, iclass 13, count 0 2006.238.08:03:10.99#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:03:10.99#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:03:10.99#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:03:10.99#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:03:10.99$vc4f8/vb=2,4 2006.238.08:03:10.99#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.238.08:03:10.99#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.238.08:03:10.99#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:10.99#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:03:11.05#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:03:11.05#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:03:11.05#ibcon#enter wrdev, iclass 15, count 2 2006.238.08:03:11.05#ibcon#first serial, iclass 15, count 2 2006.238.08:03:11.05#ibcon#enter sib2, iclass 15, count 2 2006.238.08:03:11.05#ibcon#flushed, iclass 15, count 2 2006.238.08:03:11.05#ibcon#about to write, iclass 15, count 2 2006.238.08:03:11.05#ibcon#wrote, iclass 15, count 2 2006.238.08:03:11.05#ibcon#about to read 3, iclass 15, count 2 2006.238.08:03:11.07#ibcon#read 3, iclass 15, count 2 2006.238.08:03:11.07#ibcon#about to read 4, iclass 15, count 2 2006.238.08:03:11.07#ibcon#read 4, iclass 15, count 2 2006.238.08:03:11.07#ibcon#about to read 5, iclass 15, count 2 2006.238.08:03:11.07#ibcon#read 5, iclass 15, count 2 2006.238.08:03:11.07#ibcon#about to read 6, iclass 15, count 2 2006.238.08:03:11.07#ibcon#read 6, iclass 15, count 2 2006.238.08:03:11.07#ibcon#end of sib2, iclass 15, count 2 2006.238.08:03:11.07#ibcon#*mode == 0, iclass 15, count 2 2006.238.08:03:11.07#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.238.08:03:11.07#ibcon#[27=AT02-04\r\n] 2006.238.08:03:11.07#ibcon#*before write, iclass 15, count 2 2006.238.08:03:11.07#ibcon#enter sib2, iclass 15, count 2 2006.238.08:03:11.07#ibcon#flushed, iclass 15, count 2 2006.238.08:03:11.07#ibcon#about to write, iclass 15, count 2 2006.238.08:03:11.07#ibcon#wrote, iclass 15, count 2 2006.238.08:03:11.07#ibcon#about to read 3, iclass 15, count 2 2006.238.08:03:11.10#ibcon#read 3, iclass 15, count 2 2006.238.08:03:11.10#ibcon#about to read 4, iclass 15, count 2 2006.238.08:03:11.10#ibcon#read 4, iclass 15, count 2 2006.238.08:03:11.10#ibcon#about to read 5, iclass 15, count 2 2006.238.08:03:11.10#ibcon#read 5, iclass 15, count 2 2006.238.08:03:11.10#ibcon#about to read 6, iclass 15, count 2 2006.238.08:03:11.10#ibcon#read 6, iclass 15, count 2 2006.238.08:03:11.10#ibcon#end of sib2, iclass 15, count 2 2006.238.08:03:11.10#ibcon#*after write, iclass 15, count 2 2006.238.08:03:11.10#ibcon#*before return 0, iclass 15, count 2 2006.238.08:03:11.10#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:03:11.10#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:03:11.10#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.238.08:03:11.10#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:11.10#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:03:11.22#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:03:11.22#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:03:11.22#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:03:11.22#ibcon#first serial, iclass 15, count 0 2006.238.08:03:11.22#ibcon#enter sib2, iclass 15, count 0 2006.238.08:03:11.22#ibcon#flushed, iclass 15, count 0 2006.238.08:03:11.22#ibcon#about to write, iclass 15, count 0 2006.238.08:03:11.22#ibcon#wrote, iclass 15, count 0 2006.238.08:03:11.22#ibcon#about to read 3, iclass 15, count 0 2006.238.08:03:11.24#ibcon#read 3, iclass 15, count 0 2006.238.08:03:11.24#ibcon#about to read 4, iclass 15, count 0 2006.238.08:03:11.24#ibcon#read 4, iclass 15, count 0 2006.238.08:03:11.24#ibcon#about to read 5, iclass 15, count 0 2006.238.08:03:11.24#ibcon#read 5, iclass 15, count 0 2006.238.08:03:11.24#ibcon#about to read 6, iclass 15, count 0 2006.238.08:03:11.24#ibcon#read 6, iclass 15, count 0 2006.238.08:03:11.24#ibcon#end of sib2, iclass 15, count 0 2006.238.08:03:11.24#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:03:11.24#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:03:11.24#ibcon#[27=USB\r\n] 2006.238.08:03:11.24#ibcon#*before write, iclass 15, count 0 2006.238.08:03:11.24#ibcon#enter sib2, iclass 15, count 0 2006.238.08:03:11.24#ibcon#flushed, iclass 15, count 0 2006.238.08:03:11.24#ibcon#about to write, iclass 15, count 0 2006.238.08:03:11.24#ibcon#wrote, iclass 15, count 0 2006.238.08:03:11.24#ibcon#about to read 3, iclass 15, count 0 2006.238.08:03:11.27#ibcon#read 3, iclass 15, count 0 2006.238.08:03:11.27#ibcon#about to read 4, iclass 15, count 0 2006.238.08:03:11.27#ibcon#read 4, iclass 15, count 0 2006.238.08:03:11.27#ibcon#about to read 5, iclass 15, count 0 2006.238.08:03:11.27#ibcon#read 5, iclass 15, count 0 2006.238.08:03:11.27#ibcon#about to read 6, iclass 15, count 0 2006.238.08:03:11.27#ibcon#read 6, iclass 15, count 0 2006.238.08:03:11.27#ibcon#end of sib2, iclass 15, count 0 2006.238.08:03:11.27#ibcon#*after write, iclass 15, count 0 2006.238.08:03:11.27#ibcon#*before return 0, iclass 15, count 0 2006.238.08:03:11.27#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:03:11.27#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:03:11.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:03:11.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:03:11.27$vc4f8/vblo=3,656.99 2006.238.08:03:11.27#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.08:03:11.27#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.08:03:11.27#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:11.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:03:11.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:03:11.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:03:11.27#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:03:11.27#ibcon#first serial, iclass 17, count 0 2006.238.08:03:11.27#ibcon#enter sib2, iclass 17, count 0 2006.238.08:03:11.27#ibcon#flushed, iclass 17, count 0 2006.238.08:03:11.27#ibcon#about to write, iclass 17, count 0 2006.238.08:03:11.27#ibcon#wrote, iclass 17, count 0 2006.238.08:03:11.27#ibcon#about to read 3, iclass 17, count 0 2006.238.08:03:11.29#ibcon#read 3, iclass 17, count 0 2006.238.08:03:11.29#ibcon#about to read 4, iclass 17, count 0 2006.238.08:03:11.29#ibcon#read 4, iclass 17, count 0 2006.238.08:03:11.29#ibcon#about to read 5, iclass 17, count 0 2006.238.08:03:11.29#ibcon#read 5, iclass 17, count 0 2006.238.08:03:11.29#ibcon#about to read 6, iclass 17, count 0 2006.238.08:03:11.29#ibcon#read 6, iclass 17, count 0 2006.238.08:03:11.29#ibcon#end of sib2, iclass 17, count 0 2006.238.08:03:11.29#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:03:11.29#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:03:11.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:03:11.29#ibcon#*before write, iclass 17, count 0 2006.238.08:03:11.29#ibcon#enter sib2, iclass 17, count 0 2006.238.08:03:11.29#ibcon#flushed, iclass 17, count 0 2006.238.08:03:11.29#ibcon#about to write, iclass 17, count 0 2006.238.08:03:11.29#ibcon#wrote, iclass 17, count 0 2006.238.08:03:11.29#ibcon#about to read 3, iclass 17, count 0 2006.238.08:03:11.33#ibcon#read 3, iclass 17, count 0 2006.238.08:03:11.33#ibcon#about to read 4, iclass 17, count 0 2006.238.08:03:11.33#ibcon#read 4, iclass 17, count 0 2006.238.08:03:11.33#ibcon#about to read 5, iclass 17, count 0 2006.238.08:03:11.33#ibcon#read 5, iclass 17, count 0 2006.238.08:03:11.33#ibcon#about to read 6, iclass 17, count 0 2006.238.08:03:11.33#ibcon#read 6, iclass 17, count 0 2006.238.08:03:11.33#ibcon#end of sib2, iclass 17, count 0 2006.238.08:03:11.33#ibcon#*after write, iclass 17, count 0 2006.238.08:03:11.33#ibcon#*before return 0, iclass 17, count 0 2006.238.08:03:11.33#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:03:11.33#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:03:11.33#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:03:11.33#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:03:11.33$vc4f8/vb=3,4 2006.238.08:03:11.33#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.238.08:03:11.33#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.238.08:03:11.33#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:11.33#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:03:11.39#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:03:11.39#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:03:11.39#ibcon#enter wrdev, iclass 19, count 2 2006.238.08:03:11.39#ibcon#first serial, iclass 19, count 2 2006.238.08:03:11.39#ibcon#enter sib2, iclass 19, count 2 2006.238.08:03:11.39#ibcon#flushed, iclass 19, count 2 2006.238.08:03:11.39#ibcon#about to write, iclass 19, count 2 2006.238.08:03:11.39#ibcon#wrote, iclass 19, count 2 2006.238.08:03:11.39#ibcon#about to read 3, iclass 19, count 2 2006.238.08:03:11.41#ibcon#read 3, iclass 19, count 2 2006.238.08:03:11.41#ibcon#about to read 4, iclass 19, count 2 2006.238.08:03:11.41#ibcon#read 4, iclass 19, count 2 2006.238.08:03:11.41#ibcon#about to read 5, iclass 19, count 2 2006.238.08:03:11.41#ibcon#read 5, iclass 19, count 2 2006.238.08:03:11.41#ibcon#about to read 6, iclass 19, count 2 2006.238.08:03:11.41#ibcon#read 6, iclass 19, count 2 2006.238.08:03:11.41#ibcon#end of sib2, iclass 19, count 2 2006.238.08:03:11.41#ibcon#*mode == 0, iclass 19, count 2 2006.238.08:03:11.41#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.238.08:03:11.41#ibcon#[27=AT03-04\r\n] 2006.238.08:03:11.41#ibcon#*before write, iclass 19, count 2 2006.238.08:03:11.41#ibcon#enter sib2, iclass 19, count 2 2006.238.08:03:11.41#ibcon#flushed, iclass 19, count 2 2006.238.08:03:11.41#ibcon#about to write, iclass 19, count 2 2006.238.08:03:11.41#ibcon#wrote, iclass 19, count 2 2006.238.08:03:11.41#ibcon#about to read 3, iclass 19, count 2 2006.238.08:03:11.44#ibcon#read 3, iclass 19, count 2 2006.238.08:03:11.44#ibcon#about to read 4, iclass 19, count 2 2006.238.08:03:11.44#ibcon#read 4, iclass 19, count 2 2006.238.08:03:11.44#ibcon#about to read 5, iclass 19, count 2 2006.238.08:03:11.44#ibcon#read 5, iclass 19, count 2 2006.238.08:03:11.44#ibcon#about to read 6, iclass 19, count 2 2006.238.08:03:11.44#ibcon#read 6, iclass 19, count 2 2006.238.08:03:11.44#ibcon#end of sib2, iclass 19, count 2 2006.238.08:03:11.44#ibcon#*after write, iclass 19, count 2 2006.238.08:03:11.44#ibcon#*before return 0, iclass 19, count 2 2006.238.08:03:11.44#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:03:11.44#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:03:11.44#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.238.08:03:11.44#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:11.44#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:03:11.56#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:03:11.56#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:03:11.56#ibcon#enter wrdev, iclass 19, count 0 2006.238.08:03:11.56#ibcon#first serial, iclass 19, count 0 2006.238.08:03:11.56#ibcon#enter sib2, iclass 19, count 0 2006.238.08:03:11.56#ibcon#flushed, iclass 19, count 0 2006.238.08:03:11.56#ibcon#about to write, iclass 19, count 0 2006.238.08:03:11.56#ibcon#wrote, iclass 19, count 0 2006.238.08:03:11.56#ibcon#about to read 3, iclass 19, count 0 2006.238.08:03:11.58#ibcon#read 3, iclass 19, count 0 2006.238.08:03:11.58#ibcon#about to read 4, iclass 19, count 0 2006.238.08:03:11.58#ibcon#read 4, iclass 19, count 0 2006.238.08:03:11.58#ibcon#about to read 5, iclass 19, count 0 2006.238.08:03:11.58#ibcon#read 5, iclass 19, count 0 2006.238.08:03:11.58#ibcon#about to read 6, iclass 19, count 0 2006.238.08:03:11.58#ibcon#read 6, iclass 19, count 0 2006.238.08:03:11.58#ibcon#end of sib2, iclass 19, count 0 2006.238.08:03:11.58#ibcon#*mode == 0, iclass 19, count 0 2006.238.08:03:11.58#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.08:03:11.58#ibcon#[27=USB\r\n] 2006.238.08:03:11.58#ibcon#*before write, iclass 19, count 0 2006.238.08:03:11.58#ibcon#enter sib2, iclass 19, count 0 2006.238.08:03:11.58#ibcon#flushed, iclass 19, count 0 2006.238.08:03:11.58#ibcon#about to write, iclass 19, count 0 2006.238.08:03:11.58#ibcon#wrote, iclass 19, count 0 2006.238.08:03:11.58#ibcon#about to read 3, iclass 19, count 0 2006.238.08:03:11.61#ibcon#read 3, iclass 19, count 0 2006.238.08:03:11.61#ibcon#about to read 4, iclass 19, count 0 2006.238.08:03:11.61#ibcon#read 4, iclass 19, count 0 2006.238.08:03:11.61#ibcon#about to read 5, iclass 19, count 0 2006.238.08:03:11.61#ibcon#read 5, iclass 19, count 0 2006.238.08:03:11.61#ibcon#about to read 6, iclass 19, count 0 2006.238.08:03:11.61#ibcon#read 6, iclass 19, count 0 2006.238.08:03:11.61#ibcon#end of sib2, iclass 19, count 0 2006.238.08:03:11.61#ibcon#*after write, iclass 19, count 0 2006.238.08:03:11.61#ibcon#*before return 0, iclass 19, count 0 2006.238.08:03:11.61#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:03:11.61#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:03:11.61#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.08:03:11.61#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.08:03:11.61$vc4f8/vblo=4,712.99 2006.238.08:03:11.61#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.08:03:11.61#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.08:03:11.61#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:11.61#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:03:11.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:03:11.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:03:11.61#ibcon#enter wrdev, iclass 21, count 0 2006.238.08:03:11.61#ibcon#first serial, iclass 21, count 0 2006.238.08:03:11.61#ibcon#enter sib2, iclass 21, count 0 2006.238.08:03:11.61#ibcon#flushed, iclass 21, count 0 2006.238.08:03:11.61#ibcon#about to write, iclass 21, count 0 2006.238.08:03:11.61#ibcon#wrote, iclass 21, count 0 2006.238.08:03:11.61#ibcon#about to read 3, iclass 21, count 0 2006.238.08:03:11.63#ibcon#read 3, iclass 21, count 0 2006.238.08:03:11.63#ibcon#about to read 4, iclass 21, count 0 2006.238.08:03:11.63#ibcon#read 4, iclass 21, count 0 2006.238.08:03:11.63#ibcon#about to read 5, iclass 21, count 0 2006.238.08:03:11.63#ibcon#read 5, iclass 21, count 0 2006.238.08:03:11.63#ibcon#about to read 6, iclass 21, count 0 2006.238.08:03:11.63#ibcon#read 6, iclass 21, count 0 2006.238.08:03:11.63#ibcon#end of sib2, iclass 21, count 0 2006.238.08:03:11.63#ibcon#*mode == 0, iclass 21, count 0 2006.238.08:03:11.63#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.08:03:11.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:03:11.63#ibcon#*before write, iclass 21, count 0 2006.238.08:03:11.63#ibcon#enter sib2, iclass 21, count 0 2006.238.08:03:11.63#ibcon#flushed, iclass 21, count 0 2006.238.08:03:11.63#ibcon#about to write, iclass 21, count 0 2006.238.08:03:11.63#ibcon#wrote, iclass 21, count 0 2006.238.08:03:11.63#ibcon#about to read 3, iclass 21, count 0 2006.238.08:03:11.67#ibcon#read 3, iclass 21, count 0 2006.238.08:03:11.67#ibcon#about to read 4, iclass 21, count 0 2006.238.08:03:11.67#ibcon#read 4, iclass 21, count 0 2006.238.08:03:11.67#ibcon#about to read 5, iclass 21, count 0 2006.238.08:03:11.67#ibcon#read 5, iclass 21, count 0 2006.238.08:03:11.67#ibcon#about to read 6, iclass 21, count 0 2006.238.08:03:11.67#ibcon#read 6, iclass 21, count 0 2006.238.08:03:11.67#ibcon#end of sib2, iclass 21, count 0 2006.238.08:03:11.67#ibcon#*after write, iclass 21, count 0 2006.238.08:03:11.67#ibcon#*before return 0, iclass 21, count 0 2006.238.08:03:11.67#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:03:11.67#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:03:11.67#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.08:03:11.67#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.08:03:11.67$vc4f8/vb=4,4 2006.238.08:03:11.67#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.238.08:03:11.67#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.238.08:03:11.67#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:11.67#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:03:11.73#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:03:11.73#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:03:11.73#ibcon#enter wrdev, iclass 23, count 2 2006.238.08:03:11.73#ibcon#first serial, iclass 23, count 2 2006.238.08:03:11.73#ibcon#enter sib2, iclass 23, count 2 2006.238.08:03:11.73#ibcon#flushed, iclass 23, count 2 2006.238.08:03:11.73#ibcon#about to write, iclass 23, count 2 2006.238.08:03:11.73#ibcon#wrote, iclass 23, count 2 2006.238.08:03:11.73#ibcon#about to read 3, iclass 23, count 2 2006.238.08:03:11.75#ibcon#read 3, iclass 23, count 2 2006.238.08:03:11.75#ibcon#about to read 4, iclass 23, count 2 2006.238.08:03:11.75#ibcon#read 4, iclass 23, count 2 2006.238.08:03:11.75#ibcon#about to read 5, iclass 23, count 2 2006.238.08:03:11.75#ibcon#read 5, iclass 23, count 2 2006.238.08:03:11.75#ibcon#about to read 6, iclass 23, count 2 2006.238.08:03:11.75#ibcon#read 6, iclass 23, count 2 2006.238.08:03:11.75#ibcon#end of sib2, iclass 23, count 2 2006.238.08:03:11.75#ibcon#*mode == 0, iclass 23, count 2 2006.238.08:03:11.75#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.238.08:03:11.75#ibcon#[27=AT04-04\r\n] 2006.238.08:03:11.75#ibcon#*before write, iclass 23, count 2 2006.238.08:03:11.75#ibcon#enter sib2, iclass 23, count 2 2006.238.08:03:11.75#ibcon#flushed, iclass 23, count 2 2006.238.08:03:11.75#ibcon#about to write, iclass 23, count 2 2006.238.08:03:11.75#ibcon#wrote, iclass 23, count 2 2006.238.08:03:11.75#ibcon#about to read 3, iclass 23, count 2 2006.238.08:03:11.78#ibcon#read 3, iclass 23, count 2 2006.238.08:03:11.78#ibcon#about to read 4, iclass 23, count 2 2006.238.08:03:11.78#ibcon#read 4, iclass 23, count 2 2006.238.08:03:11.78#ibcon#about to read 5, iclass 23, count 2 2006.238.08:03:11.78#ibcon#read 5, iclass 23, count 2 2006.238.08:03:11.78#ibcon#about to read 6, iclass 23, count 2 2006.238.08:03:11.78#ibcon#read 6, iclass 23, count 2 2006.238.08:03:11.78#ibcon#end of sib2, iclass 23, count 2 2006.238.08:03:11.78#ibcon#*after write, iclass 23, count 2 2006.238.08:03:11.78#ibcon#*before return 0, iclass 23, count 2 2006.238.08:03:11.78#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:03:11.78#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:03:11.78#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.238.08:03:11.78#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:11.78#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:03:11.90#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:03:11.90#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:03:11.90#ibcon#enter wrdev, iclass 23, count 0 2006.238.08:03:11.90#ibcon#first serial, iclass 23, count 0 2006.238.08:03:11.90#ibcon#enter sib2, iclass 23, count 0 2006.238.08:03:11.90#ibcon#flushed, iclass 23, count 0 2006.238.08:03:11.90#ibcon#about to write, iclass 23, count 0 2006.238.08:03:11.90#ibcon#wrote, iclass 23, count 0 2006.238.08:03:11.90#ibcon#about to read 3, iclass 23, count 0 2006.238.08:03:11.92#ibcon#read 3, iclass 23, count 0 2006.238.08:03:11.92#ibcon#about to read 4, iclass 23, count 0 2006.238.08:03:11.92#ibcon#read 4, iclass 23, count 0 2006.238.08:03:11.92#ibcon#about to read 5, iclass 23, count 0 2006.238.08:03:11.92#ibcon#read 5, iclass 23, count 0 2006.238.08:03:11.92#ibcon#about to read 6, iclass 23, count 0 2006.238.08:03:11.92#ibcon#read 6, iclass 23, count 0 2006.238.08:03:11.92#ibcon#end of sib2, iclass 23, count 0 2006.238.08:03:11.92#ibcon#*mode == 0, iclass 23, count 0 2006.238.08:03:11.92#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.08:03:11.92#ibcon#[27=USB\r\n] 2006.238.08:03:11.92#ibcon#*before write, iclass 23, count 0 2006.238.08:03:11.92#ibcon#enter sib2, iclass 23, count 0 2006.238.08:03:11.92#ibcon#flushed, iclass 23, count 0 2006.238.08:03:11.92#ibcon#about to write, iclass 23, count 0 2006.238.08:03:11.92#ibcon#wrote, iclass 23, count 0 2006.238.08:03:11.92#ibcon#about to read 3, iclass 23, count 0 2006.238.08:03:11.95#ibcon#read 3, iclass 23, count 0 2006.238.08:03:11.95#ibcon#about to read 4, iclass 23, count 0 2006.238.08:03:11.95#ibcon#read 4, iclass 23, count 0 2006.238.08:03:11.95#ibcon#about to read 5, iclass 23, count 0 2006.238.08:03:11.95#ibcon#read 5, iclass 23, count 0 2006.238.08:03:11.95#ibcon#about to read 6, iclass 23, count 0 2006.238.08:03:11.95#ibcon#read 6, iclass 23, count 0 2006.238.08:03:11.95#ibcon#end of sib2, iclass 23, count 0 2006.238.08:03:11.95#ibcon#*after write, iclass 23, count 0 2006.238.08:03:11.95#ibcon#*before return 0, iclass 23, count 0 2006.238.08:03:11.95#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:03:11.95#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:03:11.95#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.08:03:11.95#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.08:03:11.95$vc4f8/vblo=5,744.99 2006.238.08:03:11.95#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.08:03:11.95#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.08:03:11.95#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:11.95#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:03:11.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:03:11.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:03:11.95#ibcon#enter wrdev, iclass 25, count 0 2006.238.08:03:11.95#ibcon#first serial, iclass 25, count 0 2006.238.08:03:11.95#ibcon#enter sib2, iclass 25, count 0 2006.238.08:03:11.95#ibcon#flushed, iclass 25, count 0 2006.238.08:03:11.95#ibcon#about to write, iclass 25, count 0 2006.238.08:03:11.95#ibcon#wrote, iclass 25, count 0 2006.238.08:03:11.95#ibcon#about to read 3, iclass 25, count 0 2006.238.08:03:11.97#ibcon#read 3, iclass 25, count 0 2006.238.08:03:11.97#ibcon#about to read 4, iclass 25, count 0 2006.238.08:03:11.97#ibcon#read 4, iclass 25, count 0 2006.238.08:03:11.97#ibcon#about to read 5, iclass 25, count 0 2006.238.08:03:11.97#ibcon#read 5, iclass 25, count 0 2006.238.08:03:11.97#ibcon#about to read 6, iclass 25, count 0 2006.238.08:03:11.97#ibcon#read 6, iclass 25, count 0 2006.238.08:03:11.97#ibcon#end of sib2, iclass 25, count 0 2006.238.08:03:11.97#ibcon#*mode == 0, iclass 25, count 0 2006.238.08:03:11.97#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.08:03:11.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:03:11.97#ibcon#*before write, iclass 25, count 0 2006.238.08:03:11.97#ibcon#enter sib2, iclass 25, count 0 2006.238.08:03:11.97#ibcon#flushed, iclass 25, count 0 2006.238.08:03:11.97#ibcon#about to write, iclass 25, count 0 2006.238.08:03:11.97#ibcon#wrote, iclass 25, count 0 2006.238.08:03:11.97#ibcon#about to read 3, iclass 25, count 0 2006.238.08:03:12.01#ibcon#read 3, iclass 25, count 0 2006.238.08:03:12.01#ibcon#about to read 4, iclass 25, count 0 2006.238.08:03:12.01#ibcon#read 4, iclass 25, count 0 2006.238.08:03:12.01#ibcon#about to read 5, iclass 25, count 0 2006.238.08:03:12.01#ibcon#read 5, iclass 25, count 0 2006.238.08:03:12.01#ibcon#about to read 6, iclass 25, count 0 2006.238.08:03:12.01#ibcon#read 6, iclass 25, count 0 2006.238.08:03:12.01#ibcon#end of sib2, iclass 25, count 0 2006.238.08:03:12.01#ibcon#*after write, iclass 25, count 0 2006.238.08:03:12.01#ibcon#*before return 0, iclass 25, count 0 2006.238.08:03:12.01#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:03:12.01#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:03:12.01#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.08:03:12.01#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.08:03:12.01$vc4f8/vb=5,4 2006.238.08:03:12.01#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.238.08:03:12.01#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.238.08:03:12.01#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:12.01#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:03:12.07#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:03:12.07#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:03:12.07#ibcon#enter wrdev, iclass 27, count 2 2006.238.08:03:12.07#ibcon#first serial, iclass 27, count 2 2006.238.08:03:12.07#ibcon#enter sib2, iclass 27, count 2 2006.238.08:03:12.07#ibcon#flushed, iclass 27, count 2 2006.238.08:03:12.07#ibcon#about to write, iclass 27, count 2 2006.238.08:03:12.07#ibcon#wrote, iclass 27, count 2 2006.238.08:03:12.07#ibcon#about to read 3, iclass 27, count 2 2006.238.08:03:12.09#ibcon#read 3, iclass 27, count 2 2006.238.08:03:12.09#ibcon#about to read 4, iclass 27, count 2 2006.238.08:03:12.09#ibcon#read 4, iclass 27, count 2 2006.238.08:03:12.09#ibcon#about to read 5, iclass 27, count 2 2006.238.08:03:12.09#ibcon#read 5, iclass 27, count 2 2006.238.08:03:12.09#ibcon#about to read 6, iclass 27, count 2 2006.238.08:03:12.09#ibcon#read 6, iclass 27, count 2 2006.238.08:03:12.09#ibcon#end of sib2, iclass 27, count 2 2006.238.08:03:12.09#ibcon#*mode == 0, iclass 27, count 2 2006.238.08:03:12.09#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.238.08:03:12.09#ibcon#[27=AT05-04\r\n] 2006.238.08:03:12.09#ibcon#*before write, iclass 27, count 2 2006.238.08:03:12.09#ibcon#enter sib2, iclass 27, count 2 2006.238.08:03:12.09#ibcon#flushed, iclass 27, count 2 2006.238.08:03:12.09#ibcon#about to write, iclass 27, count 2 2006.238.08:03:12.09#ibcon#wrote, iclass 27, count 2 2006.238.08:03:12.09#ibcon#about to read 3, iclass 27, count 2 2006.238.08:03:12.12#ibcon#read 3, iclass 27, count 2 2006.238.08:03:12.12#ibcon#about to read 4, iclass 27, count 2 2006.238.08:03:12.12#ibcon#read 4, iclass 27, count 2 2006.238.08:03:12.12#ibcon#about to read 5, iclass 27, count 2 2006.238.08:03:12.12#ibcon#read 5, iclass 27, count 2 2006.238.08:03:12.12#ibcon#about to read 6, iclass 27, count 2 2006.238.08:03:12.12#ibcon#read 6, iclass 27, count 2 2006.238.08:03:12.12#ibcon#end of sib2, iclass 27, count 2 2006.238.08:03:12.12#ibcon#*after write, iclass 27, count 2 2006.238.08:03:12.12#ibcon#*before return 0, iclass 27, count 2 2006.238.08:03:12.12#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:03:12.12#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:03:12.12#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.238.08:03:12.12#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:12.12#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:03:12.24#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:03:12.24#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:03:12.24#ibcon#enter wrdev, iclass 27, count 0 2006.238.08:03:12.24#ibcon#first serial, iclass 27, count 0 2006.238.08:03:12.24#ibcon#enter sib2, iclass 27, count 0 2006.238.08:03:12.24#ibcon#flushed, iclass 27, count 0 2006.238.08:03:12.24#ibcon#about to write, iclass 27, count 0 2006.238.08:03:12.24#ibcon#wrote, iclass 27, count 0 2006.238.08:03:12.24#ibcon#about to read 3, iclass 27, count 0 2006.238.08:03:12.26#ibcon#read 3, iclass 27, count 0 2006.238.08:03:12.26#ibcon#about to read 4, iclass 27, count 0 2006.238.08:03:12.26#ibcon#read 4, iclass 27, count 0 2006.238.08:03:12.26#ibcon#about to read 5, iclass 27, count 0 2006.238.08:03:12.26#ibcon#read 5, iclass 27, count 0 2006.238.08:03:12.26#ibcon#about to read 6, iclass 27, count 0 2006.238.08:03:12.26#ibcon#read 6, iclass 27, count 0 2006.238.08:03:12.26#ibcon#end of sib2, iclass 27, count 0 2006.238.08:03:12.26#ibcon#*mode == 0, iclass 27, count 0 2006.238.08:03:12.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.08:03:12.26#ibcon#[27=USB\r\n] 2006.238.08:03:12.26#ibcon#*before write, iclass 27, count 0 2006.238.08:03:12.26#ibcon#enter sib2, iclass 27, count 0 2006.238.08:03:12.26#ibcon#flushed, iclass 27, count 0 2006.238.08:03:12.26#ibcon#about to write, iclass 27, count 0 2006.238.08:03:12.26#ibcon#wrote, iclass 27, count 0 2006.238.08:03:12.26#ibcon#about to read 3, iclass 27, count 0 2006.238.08:03:12.29#ibcon#read 3, iclass 27, count 0 2006.238.08:03:12.29#ibcon#about to read 4, iclass 27, count 0 2006.238.08:03:12.29#ibcon#read 4, iclass 27, count 0 2006.238.08:03:12.29#ibcon#about to read 5, iclass 27, count 0 2006.238.08:03:12.29#ibcon#read 5, iclass 27, count 0 2006.238.08:03:12.29#ibcon#about to read 6, iclass 27, count 0 2006.238.08:03:12.29#ibcon#read 6, iclass 27, count 0 2006.238.08:03:12.29#ibcon#end of sib2, iclass 27, count 0 2006.238.08:03:12.29#ibcon#*after write, iclass 27, count 0 2006.238.08:03:12.29#ibcon#*before return 0, iclass 27, count 0 2006.238.08:03:12.29#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:03:12.29#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:03:12.29#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.08:03:12.29#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.08:03:12.29$vc4f8/vblo=6,752.99 2006.238.08:03:12.29#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.238.08:03:12.29#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.238.08:03:12.29#ibcon#ireg 17 cls_cnt 0 2006.238.08:03:12.29#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:03:12.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:03:12.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:03:12.29#ibcon#enter wrdev, iclass 29, count 0 2006.238.08:03:12.29#ibcon#first serial, iclass 29, count 0 2006.238.08:03:12.29#ibcon#enter sib2, iclass 29, count 0 2006.238.08:03:12.29#ibcon#flushed, iclass 29, count 0 2006.238.08:03:12.29#ibcon#about to write, iclass 29, count 0 2006.238.08:03:12.29#ibcon#wrote, iclass 29, count 0 2006.238.08:03:12.29#ibcon#about to read 3, iclass 29, count 0 2006.238.08:03:12.31#ibcon#read 3, iclass 29, count 0 2006.238.08:03:12.31#ibcon#about to read 4, iclass 29, count 0 2006.238.08:03:12.31#ibcon#read 4, iclass 29, count 0 2006.238.08:03:12.31#ibcon#about to read 5, iclass 29, count 0 2006.238.08:03:12.31#ibcon#read 5, iclass 29, count 0 2006.238.08:03:12.31#ibcon#about to read 6, iclass 29, count 0 2006.238.08:03:12.31#ibcon#read 6, iclass 29, count 0 2006.238.08:03:12.31#ibcon#end of sib2, iclass 29, count 0 2006.238.08:03:12.31#ibcon#*mode == 0, iclass 29, count 0 2006.238.08:03:12.31#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.08:03:12.31#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:03:12.31#ibcon#*before write, iclass 29, count 0 2006.238.08:03:12.31#ibcon#enter sib2, iclass 29, count 0 2006.238.08:03:12.31#ibcon#flushed, iclass 29, count 0 2006.238.08:03:12.31#ibcon#about to write, iclass 29, count 0 2006.238.08:03:12.31#ibcon#wrote, iclass 29, count 0 2006.238.08:03:12.31#ibcon#about to read 3, iclass 29, count 0 2006.238.08:03:12.35#ibcon#read 3, iclass 29, count 0 2006.238.08:03:12.35#ibcon#about to read 4, iclass 29, count 0 2006.238.08:03:12.35#ibcon#read 4, iclass 29, count 0 2006.238.08:03:12.35#ibcon#about to read 5, iclass 29, count 0 2006.238.08:03:12.35#ibcon#read 5, iclass 29, count 0 2006.238.08:03:12.35#ibcon#about to read 6, iclass 29, count 0 2006.238.08:03:12.35#ibcon#read 6, iclass 29, count 0 2006.238.08:03:12.35#ibcon#end of sib2, iclass 29, count 0 2006.238.08:03:12.35#ibcon#*after write, iclass 29, count 0 2006.238.08:03:12.35#ibcon#*before return 0, iclass 29, count 0 2006.238.08:03:12.35#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:03:12.35#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:03:12.35#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.08:03:12.35#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.08:03:12.35$vc4f8/vb=6,4 2006.238.08:03:12.35#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.238.08:03:12.35#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.238.08:03:12.35#ibcon#ireg 11 cls_cnt 2 2006.238.08:03:12.35#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:03:12.41#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:03:12.41#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:03:12.41#ibcon#enter wrdev, iclass 31, count 2 2006.238.08:03:12.41#ibcon#first serial, iclass 31, count 2 2006.238.08:03:12.41#ibcon#enter sib2, iclass 31, count 2 2006.238.08:03:12.41#ibcon#flushed, iclass 31, count 2 2006.238.08:03:12.41#ibcon#about to write, iclass 31, count 2 2006.238.08:03:12.41#ibcon#wrote, iclass 31, count 2 2006.238.08:03:12.41#ibcon#about to read 3, iclass 31, count 2 2006.238.08:03:12.43#ibcon#read 3, iclass 31, count 2 2006.238.08:03:12.43#ibcon#about to read 4, iclass 31, count 2 2006.238.08:03:12.43#ibcon#read 4, iclass 31, count 2 2006.238.08:03:12.43#ibcon#about to read 5, iclass 31, count 2 2006.238.08:03:12.43#ibcon#read 5, iclass 31, count 2 2006.238.08:03:12.43#ibcon#about to read 6, iclass 31, count 2 2006.238.08:03:12.43#ibcon#read 6, iclass 31, count 2 2006.238.08:03:12.43#ibcon#end of sib2, iclass 31, count 2 2006.238.08:03:12.43#ibcon#*mode == 0, iclass 31, count 2 2006.238.08:03:12.43#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.238.08:03:12.43#ibcon#[27=AT06-04\r\n] 2006.238.08:03:12.43#ibcon#*before write, iclass 31, count 2 2006.238.08:03:12.43#ibcon#enter sib2, iclass 31, count 2 2006.238.08:03:12.43#ibcon#flushed, iclass 31, count 2 2006.238.08:03:12.43#ibcon#about to write, iclass 31, count 2 2006.238.08:03:12.43#ibcon#wrote, iclass 31, count 2 2006.238.08:03:12.43#ibcon#about to read 3, iclass 31, count 2 2006.238.08:03:12.46#ibcon#read 3, iclass 31, count 2 2006.238.08:03:12.46#ibcon#about to read 4, iclass 31, count 2 2006.238.08:03:12.46#ibcon#read 4, iclass 31, count 2 2006.238.08:03:12.46#ibcon#about to read 5, iclass 31, count 2 2006.238.08:03:12.46#ibcon#read 5, iclass 31, count 2 2006.238.08:03:12.46#ibcon#about to read 6, iclass 31, count 2 2006.238.08:03:12.46#ibcon#read 6, iclass 31, count 2 2006.238.08:03:12.46#ibcon#end of sib2, iclass 31, count 2 2006.238.08:03:12.46#ibcon#*after write, iclass 31, count 2 2006.238.08:03:12.46#ibcon#*before return 0, iclass 31, count 2 2006.238.08:03:12.46#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:03:12.46#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:03:12.46#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.238.08:03:12.46#ibcon#ireg 7 cls_cnt 0 2006.238.08:03:12.46#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:03:12.58#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:03:12.58#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:03:12.58#ibcon#enter wrdev, iclass 31, count 0 2006.238.08:03:12.58#ibcon#first serial, iclass 31, count 0 2006.238.08:03:12.58#ibcon#enter sib2, iclass 31, count 0 2006.238.08:03:12.58#ibcon#flushed, iclass 31, count 0 2006.238.08:03:12.58#ibcon#about to write, iclass 31, count 0 2006.238.08:03:12.58#ibcon#wrote, iclass 31, count 0 2006.238.08:03:12.58#ibcon#about to read 3, iclass 31, count 0 2006.238.08:03:12.60#ibcon#read 3, iclass 31, count 0 2006.238.08:03:12.60#ibcon#about to read 4, iclass 31, count 0 2006.238.08:03:12.60#ibcon#read 4, iclass 31, count 0 2006.238.08:03:12.60#ibcon#about to read 5, iclass 31, count 0 2006.238.08:03:12.60#ibcon#read 5, iclass 31, count 0 2006.238.08:03:12.60#ibcon#about to read 6, iclass 31, count 0 2006.238.08:03:12.60#ibcon#read 6, iclass 31, count 0 2006.238.08:03:12.60#ibcon#end of sib2, iclass 31, count 0 2006.238.08:03:12.60#ibcon#*mode == 0, iclass 31, count 0 2006.238.08:03:12.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.08:03:12.60#ibcon#[27=USB\r\n] 2006.238.08:03:12.60#ibcon#*before write, iclass 31, count 0 2006.238.08:03:12.60#ibcon#enter sib2, iclass 31, count 0 2006.238.08:03:12.60#ibcon#flushed, iclass 31, count 0 2006.238.08:03:12.60#ibcon#about to write, iclass 31, count 0 2006.238.08:03:12.60#ibcon#wrote, iclass 31, count 0 2006.238.08:03:12.60#ibcon#about to read 3, iclass 31, count 0 2006.238.08:03:12.63#ibcon#read 3, iclass 31, count 0 2006.238.08:03:12.63#ibcon#about to read 4, iclass 31, count 0 2006.238.08:03:12.63#ibcon#read 4, iclass 31, count 0 2006.238.08:03:12.63#ibcon#about to read 5, iclass 31, count 0 2006.238.08:03:12.63#ibcon#read 5, iclass 31, count 0 2006.238.08:03:12.63#ibcon#about to read 6, iclass 31, count 0 2006.238.08:03:12.63#ibcon#read 6, iclass 31, count 0 2006.238.08:03:12.63#ibcon#end of sib2, iclass 31, count 0 2006.238.08:03:12.63#ibcon#*after write, iclass 31, count 0 2006.238.08:03:12.63#ibcon#*before return 0, iclass 31, count 0 2006.238.08:03:12.63#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:03:12.63#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:03:12.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.08:03:12.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.08:03:12.63$vc4f8/vabw=wide 2006.238.08:03:12.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.08:03:12.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.08:03:12.63#ibcon#ireg 8 cls_cnt 0 2006.238.08:03:12.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:03:12.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:03:12.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:03:12.63#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:03:12.63#ibcon#first serial, iclass 33, count 0 2006.238.08:03:12.63#ibcon#enter sib2, iclass 33, count 0 2006.238.08:03:12.63#ibcon#flushed, iclass 33, count 0 2006.238.08:03:12.63#ibcon#about to write, iclass 33, count 0 2006.238.08:03:12.63#ibcon#wrote, iclass 33, count 0 2006.238.08:03:12.63#ibcon#about to read 3, iclass 33, count 0 2006.238.08:03:12.65#ibcon#read 3, iclass 33, count 0 2006.238.08:03:12.65#ibcon#about to read 4, iclass 33, count 0 2006.238.08:03:12.65#ibcon#read 4, iclass 33, count 0 2006.238.08:03:12.65#ibcon#about to read 5, iclass 33, count 0 2006.238.08:03:12.65#ibcon#read 5, iclass 33, count 0 2006.238.08:03:12.65#ibcon#about to read 6, iclass 33, count 0 2006.238.08:03:12.65#ibcon#read 6, iclass 33, count 0 2006.238.08:03:12.65#ibcon#end of sib2, iclass 33, count 0 2006.238.08:03:12.65#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:03:12.65#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:03:12.65#ibcon#[25=BW32\r\n] 2006.238.08:03:12.65#ibcon#*before write, iclass 33, count 0 2006.238.08:03:12.65#ibcon#enter sib2, iclass 33, count 0 2006.238.08:03:12.65#ibcon#flushed, iclass 33, count 0 2006.238.08:03:12.65#ibcon#about to write, iclass 33, count 0 2006.238.08:03:12.65#ibcon#wrote, iclass 33, count 0 2006.238.08:03:12.65#ibcon#about to read 3, iclass 33, count 0 2006.238.08:03:12.68#ibcon#read 3, iclass 33, count 0 2006.238.08:03:12.68#ibcon#about to read 4, iclass 33, count 0 2006.238.08:03:12.68#ibcon#read 4, iclass 33, count 0 2006.238.08:03:12.68#ibcon#about to read 5, iclass 33, count 0 2006.238.08:03:12.68#ibcon#read 5, iclass 33, count 0 2006.238.08:03:12.68#ibcon#about to read 6, iclass 33, count 0 2006.238.08:03:12.68#ibcon#read 6, iclass 33, count 0 2006.238.08:03:12.68#ibcon#end of sib2, iclass 33, count 0 2006.238.08:03:12.68#ibcon#*after write, iclass 33, count 0 2006.238.08:03:12.68#ibcon#*before return 0, iclass 33, count 0 2006.238.08:03:12.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:03:12.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:03:12.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:03:12.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:03:12.68$vc4f8/vbbw=wide 2006.238.08:03:12.68#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.08:03:12.68#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.08:03:12.68#ibcon#ireg 8 cls_cnt 0 2006.238.08:03:12.68#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:03:12.75#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:03:12.75#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:03:12.75#ibcon#enter wrdev, iclass 35, count 0 2006.238.08:03:12.75#ibcon#first serial, iclass 35, count 0 2006.238.08:03:12.75#ibcon#enter sib2, iclass 35, count 0 2006.238.08:03:12.75#ibcon#flushed, iclass 35, count 0 2006.238.08:03:12.75#ibcon#about to write, iclass 35, count 0 2006.238.08:03:12.75#ibcon#wrote, iclass 35, count 0 2006.238.08:03:12.75#ibcon#about to read 3, iclass 35, count 0 2006.238.08:03:12.77#ibcon#read 3, iclass 35, count 0 2006.238.08:03:12.77#ibcon#about to read 4, iclass 35, count 0 2006.238.08:03:12.77#ibcon#read 4, iclass 35, count 0 2006.238.08:03:12.77#ibcon#about to read 5, iclass 35, count 0 2006.238.08:03:12.77#ibcon#read 5, iclass 35, count 0 2006.238.08:03:12.77#ibcon#about to read 6, iclass 35, count 0 2006.238.08:03:12.77#ibcon#read 6, iclass 35, count 0 2006.238.08:03:12.77#ibcon#end of sib2, iclass 35, count 0 2006.238.08:03:12.77#ibcon#*mode == 0, iclass 35, count 0 2006.238.08:03:12.77#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.08:03:12.77#ibcon#[27=BW32\r\n] 2006.238.08:03:12.77#ibcon#*before write, iclass 35, count 0 2006.238.08:03:12.77#ibcon#enter sib2, iclass 35, count 0 2006.238.08:03:12.77#ibcon#flushed, iclass 35, count 0 2006.238.08:03:12.77#ibcon#about to write, iclass 35, count 0 2006.238.08:03:12.77#ibcon#wrote, iclass 35, count 0 2006.238.08:03:12.77#ibcon#about to read 3, iclass 35, count 0 2006.238.08:03:12.80#ibcon#read 3, iclass 35, count 0 2006.238.08:03:12.80#ibcon#about to read 4, iclass 35, count 0 2006.238.08:03:12.80#ibcon#read 4, iclass 35, count 0 2006.238.08:03:12.80#ibcon#about to read 5, iclass 35, count 0 2006.238.08:03:12.80#ibcon#read 5, iclass 35, count 0 2006.238.08:03:12.80#ibcon#about to read 6, iclass 35, count 0 2006.238.08:03:12.80#ibcon#read 6, iclass 35, count 0 2006.238.08:03:12.80#ibcon#end of sib2, iclass 35, count 0 2006.238.08:03:12.80#ibcon#*after write, iclass 35, count 0 2006.238.08:03:12.80#ibcon#*before return 0, iclass 35, count 0 2006.238.08:03:12.80#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:03:12.80#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:03:12.80#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.08:03:12.80#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.08:03:12.80$4f8m12a/ifd4f 2006.238.08:03:12.80$ifd4f/lo= 2006.238.08:03:12.80$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:03:12.80$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:03:12.80$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:03:12.80$ifd4f/patch= 2006.238.08:03:12.80$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:03:12.80$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:03:12.80$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:03:12.80$4f8m12a/"form=m,16.000,1:2 2006.238.08:03:12.80$4f8m12a/"tpicd 2006.238.08:03:12.80$4f8m12a/echo=off 2006.238.08:03:12.81$4f8m12a/xlog=off 2006.238.08:03:12.81:!2006.238.08:03:40 2006.238.08:03:17.14#trakl#Source acquired 2006.238.08:03:18.14#flagr#flagr/antenna,acquired 2006.238.08:03:40.01:preob 2006.238.08:03:41.14/onsource/TRACKING 2006.238.08:03:41.14:!2006.238.08:03:50 2006.238.08:03:50.00:data_valid=on 2006.238.08:03:50.00:midob 2006.238.08:03:50.14/onsource/TRACKING 2006.238.08:03:50.14/wx/25.45,1012.2,88 2006.238.08:03:50.33/cable/+6.4184E-03 2006.238.08:03:51.42/va/01,08,usb,yes,34,36 2006.238.08:03:51.42/va/02,07,usb,yes,34,36 2006.238.08:03:51.42/va/03,07,usb,yes,32,33 2006.238.08:03:51.42/va/04,07,usb,yes,36,39 2006.238.08:03:51.42/va/05,08,usb,yes,33,35 2006.238.08:03:51.42/va/06,07,usb,yes,36,36 2006.238.08:03:51.42/va/07,07,usb,yes,36,36 2006.238.08:03:51.42/va/08,07,usb,yes,39,38 2006.238.08:03:51.65/valo/01,532.99,yes,locked 2006.238.08:03:51.65/valo/02,572.99,yes,locked 2006.238.08:03:51.65/valo/03,672.99,yes,locked 2006.238.08:03:51.65/valo/04,832.99,yes,locked 2006.238.08:03:51.65/valo/05,652.99,yes,locked 2006.238.08:03:51.65/valo/06,772.99,yes,locked 2006.238.08:03:51.65/valo/07,832.99,yes,locked 2006.238.08:03:51.65/valo/08,852.99,yes,locked 2006.238.08:03:52.74/vb/01,04,usb,yes,32,31 2006.238.08:03:52.74/vb/02,04,usb,yes,34,35 2006.238.08:03:52.74/vb/03,04,usb,yes,30,34 2006.238.08:03:52.74/vb/04,04,usb,yes,31,31 2006.238.08:03:52.74/vb/05,04,usb,yes,29,34 2006.238.08:03:52.74/vb/06,04,usb,yes,30,33 2006.238.08:03:52.74/vb/07,04,usb,yes,33,33 2006.238.08:03:52.74/vb/08,04,usb,yes,30,34 2006.238.08:03:52.97/vblo/01,632.99,yes,locked 2006.238.08:03:52.97/vblo/02,640.99,yes,locked 2006.238.08:03:52.97/vblo/03,656.99,yes,locked 2006.238.08:03:52.97/vblo/04,712.99,yes,locked 2006.238.08:03:52.97/vblo/05,744.99,yes,locked 2006.238.08:03:52.97/vblo/06,752.99,yes,locked 2006.238.08:03:52.97/vblo/07,734.99,yes,locked 2006.238.08:03:52.97/vblo/08,744.99,yes,locked 2006.238.08:03:53.12/vabw/8 2006.238.08:03:53.27/vbbw/8 2006.238.08:03:53.38/xfe/off,on,14.2 2006.238.08:03:53.75/ifatt/23,28,28,28 2006.238.08:03:54.07/fmout-gps/S +4.31E-07 2006.238.08:03:54.11:!2006.238.08:04:50 2006.238.08:04:50.01:data_valid=off 2006.238.08:04:50.02:postob 2006.238.08:04:50.21/cable/+6.4194E-03 2006.238.08:04:50.22/wx/25.45,1012.2,89 2006.238.08:04:50.29/fmout-gps/S +4.31E-07 2006.238.08:04:50.29:scan_name=238-0805,k06238,60 2006.238.08:04:50.30:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.238.08:04:52.14#flagr#flagr/antenna,new-source 2006.238.08:04:52.15:checkk5 2006.238.08:04:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:04:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:04:53.30/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:04:53.67/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:04:54.05/chk_obsdata//k5ts1/T2380803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:04:54.41/chk_obsdata//k5ts2/T2380803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:04:54.78/chk_obsdata//k5ts3/T2380803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:04:55.15/chk_obsdata//k5ts4/T2380803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:04:55.84/k5log//k5ts1_log_newline 2006.238.08:04:56.53/k5log//k5ts2_log_newline 2006.238.08:04:57.22/k5log//k5ts3_log_newline 2006.238.08:04:57.91/k5log//k5ts4_log_newline 2006.238.08:04:57.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:04:57.94:4f8m12a=2 2006.238.08:04:57.94$4f8m12a/echo=on 2006.238.08:04:57.94$4f8m12a/pcalon 2006.238.08:04:57.94$pcalon/"no phase cal control is implemented here 2006.238.08:04:57.94$4f8m12a/"tpicd=stop 2006.238.08:04:57.94$4f8m12a/vc4f8 2006.238.08:04:57.94$vc4f8/valo=1,532.99 2006.238.08:04:57.94#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.08:04:57.94#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.08:04:57.94#ibcon#ireg 17 cls_cnt 0 2006.238.08:04:57.94#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:04:57.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:04:57.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:04:57.94#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:04:57.94#ibcon#first serial, iclass 4, count 0 2006.238.08:04:57.94#ibcon#enter sib2, iclass 4, count 0 2006.238.08:04:57.94#ibcon#flushed, iclass 4, count 0 2006.238.08:04:57.94#ibcon#about to write, iclass 4, count 0 2006.238.08:04:57.94#ibcon#wrote, iclass 4, count 0 2006.238.08:04:57.94#ibcon#about to read 3, iclass 4, count 0 2006.238.08:04:57.99#ibcon#read 3, iclass 4, count 0 2006.238.08:04:57.99#ibcon#about to read 4, iclass 4, count 0 2006.238.08:04:57.99#ibcon#read 4, iclass 4, count 0 2006.238.08:04:57.99#ibcon#about to read 5, iclass 4, count 0 2006.238.08:04:57.99#ibcon#read 5, iclass 4, count 0 2006.238.08:04:57.99#ibcon#about to read 6, iclass 4, count 0 2006.238.08:04:57.99#ibcon#read 6, iclass 4, count 0 2006.238.08:04:57.99#ibcon#end of sib2, iclass 4, count 0 2006.238.08:04:57.99#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:04:57.99#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:04:57.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:04:57.99#ibcon#*before write, iclass 4, count 0 2006.238.08:04:57.99#ibcon#enter sib2, iclass 4, count 0 2006.238.08:04:57.99#ibcon#flushed, iclass 4, count 0 2006.238.08:04:57.99#ibcon#about to write, iclass 4, count 0 2006.238.08:04:57.99#ibcon#wrote, iclass 4, count 0 2006.238.08:04:57.99#ibcon#about to read 3, iclass 4, count 0 2006.238.08:04:58.03#ibcon#read 3, iclass 4, count 0 2006.238.08:04:58.03#ibcon#about to read 4, iclass 4, count 0 2006.238.08:04:58.03#ibcon#read 4, iclass 4, count 0 2006.238.08:04:58.03#ibcon#about to read 5, iclass 4, count 0 2006.238.08:04:58.03#ibcon#read 5, iclass 4, count 0 2006.238.08:04:58.03#ibcon#about to read 6, iclass 4, count 0 2006.238.08:04:58.03#ibcon#read 6, iclass 4, count 0 2006.238.08:04:58.03#ibcon#end of sib2, iclass 4, count 0 2006.238.08:04:58.03#ibcon#*after write, iclass 4, count 0 2006.238.08:04:58.03#ibcon#*before return 0, iclass 4, count 0 2006.238.08:04:58.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:04:58.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:04:58.03#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:04:58.03#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:04:58.03$vc4f8/va=1,8 2006.238.08:04:58.03#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.08:04:58.03#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.08:04:58.03#ibcon#ireg 11 cls_cnt 2 2006.238.08:04:58.03#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:04:58.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:04:58.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:04:58.03#ibcon#enter wrdev, iclass 6, count 2 2006.238.08:04:58.03#ibcon#first serial, iclass 6, count 2 2006.238.08:04:58.03#ibcon#enter sib2, iclass 6, count 2 2006.238.08:04:58.03#ibcon#flushed, iclass 6, count 2 2006.238.08:04:58.03#ibcon#about to write, iclass 6, count 2 2006.238.08:04:58.03#ibcon#wrote, iclass 6, count 2 2006.238.08:04:58.03#ibcon#about to read 3, iclass 6, count 2 2006.238.08:04:58.05#ibcon#read 3, iclass 6, count 2 2006.238.08:04:58.05#ibcon#about to read 4, iclass 6, count 2 2006.238.08:04:58.05#ibcon#read 4, iclass 6, count 2 2006.238.08:04:58.05#ibcon#about to read 5, iclass 6, count 2 2006.238.08:04:58.05#ibcon#read 5, iclass 6, count 2 2006.238.08:04:58.05#ibcon#about to read 6, iclass 6, count 2 2006.238.08:04:58.05#ibcon#read 6, iclass 6, count 2 2006.238.08:04:58.05#ibcon#end of sib2, iclass 6, count 2 2006.238.08:04:58.05#ibcon#*mode == 0, iclass 6, count 2 2006.238.08:04:58.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.08:04:58.05#ibcon#[25=AT01-08\r\n] 2006.238.08:04:58.05#ibcon#*before write, iclass 6, count 2 2006.238.08:04:58.05#ibcon#enter sib2, iclass 6, count 2 2006.238.08:04:58.05#ibcon#flushed, iclass 6, count 2 2006.238.08:04:58.05#ibcon#about to write, iclass 6, count 2 2006.238.08:04:58.05#ibcon#wrote, iclass 6, count 2 2006.238.08:04:58.05#ibcon#about to read 3, iclass 6, count 2 2006.238.08:04:58.08#ibcon#read 3, iclass 6, count 2 2006.238.08:04:58.08#ibcon#about to read 4, iclass 6, count 2 2006.238.08:04:58.08#ibcon#read 4, iclass 6, count 2 2006.238.08:04:58.08#ibcon#about to read 5, iclass 6, count 2 2006.238.08:04:58.08#ibcon#read 5, iclass 6, count 2 2006.238.08:04:58.08#ibcon#about to read 6, iclass 6, count 2 2006.238.08:04:58.08#ibcon#read 6, iclass 6, count 2 2006.238.08:04:58.08#ibcon#end of sib2, iclass 6, count 2 2006.238.08:04:58.08#ibcon#*after write, iclass 6, count 2 2006.238.08:04:58.08#ibcon#*before return 0, iclass 6, count 2 2006.238.08:04:58.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:04:58.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:04:58.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.08:04:58.08#ibcon#ireg 7 cls_cnt 0 2006.238.08:04:58.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:04:58.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:04:58.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:04:58.20#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:04:58.20#ibcon#first serial, iclass 6, count 0 2006.238.08:04:58.20#ibcon#enter sib2, iclass 6, count 0 2006.238.08:04:58.20#ibcon#flushed, iclass 6, count 0 2006.238.08:04:58.20#ibcon#about to write, iclass 6, count 0 2006.238.08:04:58.21#ibcon#wrote, iclass 6, count 0 2006.238.08:04:58.21#ibcon#about to read 3, iclass 6, count 0 2006.238.08:04:58.22#ibcon#read 3, iclass 6, count 0 2006.238.08:04:58.22#ibcon#about to read 4, iclass 6, count 0 2006.238.08:04:58.22#ibcon#read 4, iclass 6, count 0 2006.238.08:04:58.22#ibcon#about to read 5, iclass 6, count 0 2006.238.08:04:58.22#ibcon#read 5, iclass 6, count 0 2006.238.08:04:58.22#ibcon#about to read 6, iclass 6, count 0 2006.238.08:04:58.22#ibcon#read 6, iclass 6, count 0 2006.238.08:04:58.22#ibcon#end of sib2, iclass 6, count 0 2006.238.08:04:58.22#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:04:58.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:04:58.22#ibcon#[25=USB\r\n] 2006.238.08:04:58.22#ibcon#*before write, iclass 6, count 0 2006.238.08:04:58.22#ibcon#enter sib2, iclass 6, count 0 2006.238.08:04:58.22#ibcon#flushed, iclass 6, count 0 2006.238.08:04:58.22#ibcon#about to write, iclass 6, count 0 2006.238.08:04:58.22#ibcon#wrote, iclass 6, count 0 2006.238.08:04:58.22#ibcon#about to read 3, iclass 6, count 0 2006.238.08:04:58.25#ibcon#read 3, iclass 6, count 0 2006.238.08:04:58.25#ibcon#about to read 4, iclass 6, count 0 2006.238.08:04:58.25#ibcon#read 4, iclass 6, count 0 2006.238.08:04:58.25#ibcon#about to read 5, iclass 6, count 0 2006.238.08:04:58.25#ibcon#read 5, iclass 6, count 0 2006.238.08:04:58.25#ibcon#about to read 6, iclass 6, count 0 2006.238.08:04:58.25#ibcon#read 6, iclass 6, count 0 2006.238.08:04:58.25#ibcon#end of sib2, iclass 6, count 0 2006.238.08:04:58.25#ibcon#*after write, iclass 6, count 0 2006.238.08:04:58.25#ibcon#*before return 0, iclass 6, count 0 2006.238.08:04:58.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:04:58.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:04:58.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:04:58.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:04:58.25$vc4f8/valo=2,572.99 2006.238.08:04:58.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.08:04:58.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.08:04:58.25#ibcon#ireg 17 cls_cnt 0 2006.238.08:04:58.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:04:58.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:04:58.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:04:58.25#ibcon#enter wrdev, iclass 10, count 0 2006.238.08:04:58.25#ibcon#first serial, iclass 10, count 0 2006.238.08:04:58.25#ibcon#enter sib2, iclass 10, count 0 2006.238.08:04:58.25#ibcon#flushed, iclass 10, count 0 2006.238.08:04:58.25#ibcon#about to write, iclass 10, count 0 2006.238.08:04:58.25#ibcon#wrote, iclass 10, count 0 2006.238.08:04:58.25#ibcon#about to read 3, iclass 10, count 0 2006.238.08:04:58.27#ibcon#read 3, iclass 10, count 0 2006.238.08:04:58.27#ibcon#about to read 4, iclass 10, count 0 2006.238.08:04:58.27#ibcon#read 4, iclass 10, count 0 2006.238.08:04:58.27#ibcon#about to read 5, iclass 10, count 0 2006.238.08:04:58.27#ibcon#read 5, iclass 10, count 0 2006.238.08:04:58.27#ibcon#about to read 6, iclass 10, count 0 2006.238.08:04:58.27#ibcon#read 6, iclass 10, count 0 2006.238.08:04:58.27#ibcon#end of sib2, iclass 10, count 0 2006.238.08:04:58.27#ibcon#*mode == 0, iclass 10, count 0 2006.238.08:04:58.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.08:04:58.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:04:58.27#ibcon#*before write, iclass 10, count 0 2006.238.08:04:58.27#ibcon#enter sib2, iclass 10, count 0 2006.238.08:04:58.27#ibcon#flushed, iclass 10, count 0 2006.238.08:04:58.27#ibcon#about to write, iclass 10, count 0 2006.238.08:04:58.27#ibcon#wrote, iclass 10, count 0 2006.238.08:04:58.27#ibcon#about to read 3, iclass 10, count 0 2006.238.08:04:58.31#ibcon#read 3, iclass 10, count 0 2006.238.08:04:58.31#ibcon#about to read 4, iclass 10, count 0 2006.238.08:04:58.31#ibcon#read 4, iclass 10, count 0 2006.238.08:04:58.31#ibcon#about to read 5, iclass 10, count 0 2006.238.08:04:58.31#ibcon#read 5, iclass 10, count 0 2006.238.08:04:58.31#ibcon#about to read 6, iclass 10, count 0 2006.238.08:04:58.31#ibcon#read 6, iclass 10, count 0 2006.238.08:04:58.31#ibcon#end of sib2, iclass 10, count 0 2006.238.08:04:58.31#ibcon#*after write, iclass 10, count 0 2006.238.08:04:58.31#ibcon#*before return 0, iclass 10, count 0 2006.238.08:04:58.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:04:58.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:04:58.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.08:04:58.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.08:04:58.31$vc4f8/va=2,7 2006.238.08:04:58.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.238.08:04:58.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.238.08:04:58.31#ibcon#ireg 11 cls_cnt 2 2006.238.08:04:58.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:04:58.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:04:58.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:04:58.37#ibcon#enter wrdev, iclass 12, count 2 2006.238.08:04:58.37#ibcon#first serial, iclass 12, count 2 2006.238.08:04:58.37#ibcon#enter sib2, iclass 12, count 2 2006.238.08:04:58.37#ibcon#flushed, iclass 12, count 2 2006.238.08:04:58.37#ibcon#about to write, iclass 12, count 2 2006.238.08:04:58.37#ibcon#wrote, iclass 12, count 2 2006.238.08:04:58.37#ibcon#about to read 3, iclass 12, count 2 2006.238.08:04:58.39#ibcon#read 3, iclass 12, count 2 2006.238.08:04:58.39#ibcon#about to read 4, iclass 12, count 2 2006.238.08:04:58.39#ibcon#read 4, iclass 12, count 2 2006.238.08:04:58.39#ibcon#about to read 5, iclass 12, count 2 2006.238.08:04:58.39#ibcon#read 5, iclass 12, count 2 2006.238.08:04:58.39#ibcon#about to read 6, iclass 12, count 2 2006.238.08:04:58.39#ibcon#read 6, iclass 12, count 2 2006.238.08:04:58.39#ibcon#end of sib2, iclass 12, count 2 2006.238.08:04:58.39#ibcon#*mode == 0, iclass 12, count 2 2006.238.08:04:58.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.238.08:04:58.39#ibcon#[25=AT02-07\r\n] 2006.238.08:04:58.39#ibcon#*before write, iclass 12, count 2 2006.238.08:04:58.39#ibcon#enter sib2, iclass 12, count 2 2006.238.08:04:58.39#ibcon#flushed, iclass 12, count 2 2006.238.08:04:58.39#ibcon#about to write, iclass 12, count 2 2006.238.08:04:58.39#ibcon#wrote, iclass 12, count 2 2006.238.08:04:58.39#ibcon#about to read 3, iclass 12, count 2 2006.238.08:04:58.42#ibcon#read 3, iclass 12, count 2 2006.238.08:04:58.42#ibcon#about to read 4, iclass 12, count 2 2006.238.08:04:58.42#ibcon#read 4, iclass 12, count 2 2006.238.08:04:58.42#ibcon#about to read 5, iclass 12, count 2 2006.238.08:04:58.42#ibcon#read 5, iclass 12, count 2 2006.238.08:04:58.42#ibcon#about to read 6, iclass 12, count 2 2006.238.08:04:58.42#ibcon#read 6, iclass 12, count 2 2006.238.08:04:58.42#ibcon#end of sib2, iclass 12, count 2 2006.238.08:04:58.42#ibcon#*after write, iclass 12, count 2 2006.238.08:04:58.42#ibcon#*before return 0, iclass 12, count 2 2006.238.08:04:58.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:04:58.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:04:58.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.238.08:04:58.42#ibcon#ireg 7 cls_cnt 0 2006.238.08:04:58.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:04:58.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:04:58.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:04:58.54#ibcon#enter wrdev, iclass 12, count 0 2006.238.08:04:58.54#ibcon#first serial, iclass 12, count 0 2006.238.08:04:58.54#ibcon#enter sib2, iclass 12, count 0 2006.238.08:04:58.54#ibcon#flushed, iclass 12, count 0 2006.238.08:04:58.54#ibcon#about to write, iclass 12, count 0 2006.238.08:04:58.54#ibcon#wrote, iclass 12, count 0 2006.238.08:04:58.54#ibcon#about to read 3, iclass 12, count 0 2006.238.08:04:58.56#ibcon#read 3, iclass 12, count 0 2006.238.08:04:58.56#ibcon#about to read 4, iclass 12, count 0 2006.238.08:04:58.56#ibcon#read 4, iclass 12, count 0 2006.238.08:04:58.56#ibcon#about to read 5, iclass 12, count 0 2006.238.08:04:58.56#ibcon#read 5, iclass 12, count 0 2006.238.08:04:58.56#ibcon#about to read 6, iclass 12, count 0 2006.238.08:04:58.56#ibcon#read 6, iclass 12, count 0 2006.238.08:04:58.56#ibcon#end of sib2, iclass 12, count 0 2006.238.08:04:58.56#ibcon#*mode == 0, iclass 12, count 0 2006.238.08:04:58.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.08:04:58.56#ibcon#[25=USB\r\n] 2006.238.08:04:58.56#ibcon#*before write, iclass 12, count 0 2006.238.08:04:58.56#ibcon#enter sib2, iclass 12, count 0 2006.238.08:04:58.56#ibcon#flushed, iclass 12, count 0 2006.238.08:04:58.56#ibcon#about to write, iclass 12, count 0 2006.238.08:04:58.56#ibcon#wrote, iclass 12, count 0 2006.238.08:04:58.56#ibcon#about to read 3, iclass 12, count 0 2006.238.08:04:58.59#ibcon#read 3, iclass 12, count 0 2006.238.08:04:58.59#ibcon#about to read 4, iclass 12, count 0 2006.238.08:04:58.59#ibcon#read 4, iclass 12, count 0 2006.238.08:04:58.59#ibcon#about to read 5, iclass 12, count 0 2006.238.08:04:58.59#ibcon#read 5, iclass 12, count 0 2006.238.08:04:58.59#ibcon#about to read 6, iclass 12, count 0 2006.238.08:04:58.59#ibcon#read 6, iclass 12, count 0 2006.238.08:04:58.59#ibcon#end of sib2, iclass 12, count 0 2006.238.08:04:58.59#ibcon#*after write, iclass 12, count 0 2006.238.08:04:58.59#ibcon#*before return 0, iclass 12, count 0 2006.238.08:04:58.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:04:58.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:04:58.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.08:04:58.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.08:04:58.59$vc4f8/valo=3,672.99 2006.238.08:04:58.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.08:04:58.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.08:04:58.59#ibcon#ireg 17 cls_cnt 0 2006.238.08:04:58.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:04:58.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:04:58.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:04:58.59#ibcon#enter wrdev, iclass 14, count 0 2006.238.08:04:58.59#ibcon#first serial, iclass 14, count 0 2006.238.08:04:58.59#ibcon#enter sib2, iclass 14, count 0 2006.238.08:04:58.59#ibcon#flushed, iclass 14, count 0 2006.238.08:04:58.59#ibcon#about to write, iclass 14, count 0 2006.238.08:04:58.59#ibcon#wrote, iclass 14, count 0 2006.238.08:04:58.59#ibcon#about to read 3, iclass 14, count 0 2006.238.08:04:58.61#ibcon#read 3, iclass 14, count 0 2006.238.08:04:58.61#ibcon#about to read 4, iclass 14, count 0 2006.238.08:04:58.61#ibcon#read 4, iclass 14, count 0 2006.238.08:04:58.61#ibcon#about to read 5, iclass 14, count 0 2006.238.08:04:58.61#ibcon#read 5, iclass 14, count 0 2006.238.08:04:58.61#ibcon#about to read 6, iclass 14, count 0 2006.238.08:04:58.61#ibcon#read 6, iclass 14, count 0 2006.238.08:04:58.61#ibcon#end of sib2, iclass 14, count 0 2006.238.08:04:58.61#ibcon#*mode == 0, iclass 14, count 0 2006.238.08:04:58.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.08:04:58.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:04:58.61#ibcon#*before write, iclass 14, count 0 2006.238.08:04:58.61#ibcon#enter sib2, iclass 14, count 0 2006.238.08:04:58.61#ibcon#flushed, iclass 14, count 0 2006.238.08:04:58.61#ibcon#about to write, iclass 14, count 0 2006.238.08:04:58.61#ibcon#wrote, iclass 14, count 0 2006.238.08:04:58.61#ibcon#about to read 3, iclass 14, count 0 2006.238.08:04:58.65#ibcon#read 3, iclass 14, count 0 2006.238.08:04:58.65#ibcon#about to read 4, iclass 14, count 0 2006.238.08:04:58.65#ibcon#read 4, iclass 14, count 0 2006.238.08:04:58.65#ibcon#about to read 5, iclass 14, count 0 2006.238.08:04:58.65#ibcon#read 5, iclass 14, count 0 2006.238.08:04:58.65#ibcon#about to read 6, iclass 14, count 0 2006.238.08:04:58.65#ibcon#read 6, iclass 14, count 0 2006.238.08:04:58.65#ibcon#end of sib2, iclass 14, count 0 2006.238.08:04:58.65#ibcon#*after write, iclass 14, count 0 2006.238.08:04:58.65#ibcon#*before return 0, iclass 14, count 0 2006.238.08:04:58.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:04:58.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:04:58.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.08:04:58.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.08:04:58.65$vc4f8/va=3,7 2006.238.08:04:58.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.238.08:04:58.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.238.08:04:58.65#ibcon#ireg 11 cls_cnt 2 2006.238.08:04:58.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:04:58.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:04:58.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:04:58.71#ibcon#enter wrdev, iclass 16, count 2 2006.238.08:04:58.71#ibcon#first serial, iclass 16, count 2 2006.238.08:04:58.71#ibcon#enter sib2, iclass 16, count 2 2006.238.08:04:58.71#ibcon#flushed, iclass 16, count 2 2006.238.08:04:58.71#ibcon#about to write, iclass 16, count 2 2006.238.08:04:58.71#ibcon#wrote, iclass 16, count 2 2006.238.08:04:58.71#ibcon#about to read 3, iclass 16, count 2 2006.238.08:04:58.73#ibcon#read 3, iclass 16, count 2 2006.238.08:04:58.73#ibcon#about to read 4, iclass 16, count 2 2006.238.08:04:58.73#ibcon#read 4, iclass 16, count 2 2006.238.08:04:58.73#ibcon#about to read 5, iclass 16, count 2 2006.238.08:04:58.73#ibcon#read 5, iclass 16, count 2 2006.238.08:04:58.73#ibcon#about to read 6, iclass 16, count 2 2006.238.08:04:58.73#ibcon#read 6, iclass 16, count 2 2006.238.08:04:58.73#ibcon#end of sib2, iclass 16, count 2 2006.238.08:04:58.73#ibcon#*mode == 0, iclass 16, count 2 2006.238.08:04:58.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.238.08:04:58.73#ibcon#[25=AT03-07\r\n] 2006.238.08:04:58.73#ibcon#*before write, iclass 16, count 2 2006.238.08:04:58.73#ibcon#enter sib2, iclass 16, count 2 2006.238.08:04:58.73#ibcon#flushed, iclass 16, count 2 2006.238.08:04:58.73#ibcon#about to write, iclass 16, count 2 2006.238.08:04:58.73#ibcon#wrote, iclass 16, count 2 2006.238.08:04:58.73#ibcon#about to read 3, iclass 16, count 2 2006.238.08:04:58.76#ibcon#read 3, iclass 16, count 2 2006.238.08:04:58.76#ibcon#about to read 4, iclass 16, count 2 2006.238.08:04:58.76#ibcon#read 4, iclass 16, count 2 2006.238.08:04:58.76#ibcon#about to read 5, iclass 16, count 2 2006.238.08:04:58.76#ibcon#read 5, iclass 16, count 2 2006.238.08:04:58.76#ibcon#about to read 6, iclass 16, count 2 2006.238.08:04:58.76#ibcon#read 6, iclass 16, count 2 2006.238.08:04:58.76#ibcon#end of sib2, iclass 16, count 2 2006.238.08:04:58.76#ibcon#*after write, iclass 16, count 2 2006.238.08:04:58.76#ibcon#*before return 0, iclass 16, count 2 2006.238.08:04:58.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:04:58.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:04:58.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.238.08:04:58.76#ibcon#ireg 7 cls_cnt 0 2006.238.08:04:58.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:04:58.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:04:58.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:04:58.88#ibcon#enter wrdev, iclass 16, count 0 2006.238.08:04:58.88#ibcon#first serial, iclass 16, count 0 2006.238.08:04:58.88#ibcon#enter sib2, iclass 16, count 0 2006.238.08:04:58.88#ibcon#flushed, iclass 16, count 0 2006.238.08:04:58.88#ibcon#about to write, iclass 16, count 0 2006.238.08:04:58.88#ibcon#wrote, iclass 16, count 0 2006.238.08:04:58.88#ibcon#about to read 3, iclass 16, count 0 2006.238.08:04:58.90#ibcon#read 3, iclass 16, count 0 2006.238.08:04:58.90#ibcon#about to read 4, iclass 16, count 0 2006.238.08:04:58.90#ibcon#read 4, iclass 16, count 0 2006.238.08:04:58.90#ibcon#about to read 5, iclass 16, count 0 2006.238.08:04:58.90#ibcon#read 5, iclass 16, count 0 2006.238.08:04:58.90#ibcon#about to read 6, iclass 16, count 0 2006.238.08:04:58.90#ibcon#read 6, iclass 16, count 0 2006.238.08:04:58.90#ibcon#end of sib2, iclass 16, count 0 2006.238.08:04:58.90#ibcon#*mode == 0, iclass 16, count 0 2006.238.08:04:58.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.08:04:58.90#ibcon#[25=USB\r\n] 2006.238.08:04:58.90#ibcon#*before write, iclass 16, count 0 2006.238.08:04:58.90#ibcon#enter sib2, iclass 16, count 0 2006.238.08:04:58.90#ibcon#flushed, iclass 16, count 0 2006.238.08:04:58.90#ibcon#about to write, iclass 16, count 0 2006.238.08:04:58.90#ibcon#wrote, iclass 16, count 0 2006.238.08:04:58.90#ibcon#about to read 3, iclass 16, count 0 2006.238.08:04:58.93#ibcon#read 3, iclass 16, count 0 2006.238.08:04:58.93#ibcon#about to read 4, iclass 16, count 0 2006.238.08:04:58.93#ibcon#read 4, iclass 16, count 0 2006.238.08:04:58.93#ibcon#about to read 5, iclass 16, count 0 2006.238.08:04:58.93#ibcon#read 5, iclass 16, count 0 2006.238.08:04:58.93#ibcon#about to read 6, iclass 16, count 0 2006.238.08:04:58.93#ibcon#read 6, iclass 16, count 0 2006.238.08:04:58.93#ibcon#end of sib2, iclass 16, count 0 2006.238.08:04:58.93#ibcon#*after write, iclass 16, count 0 2006.238.08:04:58.93#ibcon#*before return 0, iclass 16, count 0 2006.238.08:04:58.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:04:58.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:04:58.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.08:04:58.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.08:04:58.93$vc4f8/valo=4,832.99 2006.238.08:04:58.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.08:04:58.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.08:04:58.93#ibcon#ireg 17 cls_cnt 0 2006.238.08:04:58.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:04:58.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:04:58.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:04:58.93#ibcon#enter wrdev, iclass 18, count 0 2006.238.08:04:58.93#ibcon#first serial, iclass 18, count 0 2006.238.08:04:58.93#ibcon#enter sib2, iclass 18, count 0 2006.238.08:04:58.93#ibcon#flushed, iclass 18, count 0 2006.238.08:04:58.93#ibcon#about to write, iclass 18, count 0 2006.238.08:04:58.93#ibcon#wrote, iclass 18, count 0 2006.238.08:04:58.93#ibcon#about to read 3, iclass 18, count 0 2006.238.08:04:58.95#ibcon#read 3, iclass 18, count 0 2006.238.08:04:58.95#ibcon#about to read 4, iclass 18, count 0 2006.238.08:04:58.95#ibcon#read 4, iclass 18, count 0 2006.238.08:04:58.95#ibcon#about to read 5, iclass 18, count 0 2006.238.08:04:58.95#ibcon#read 5, iclass 18, count 0 2006.238.08:04:58.95#ibcon#about to read 6, iclass 18, count 0 2006.238.08:04:58.95#ibcon#read 6, iclass 18, count 0 2006.238.08:04:58.95#ibcon#end of sib2, iclass 18, count 0 2006.238.08:04:58.95#ibcon#*mode == 0, iclass 18, count 0 2006.238.08:04:58.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.08:04:58.95#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:04:58.95#ibcon#*before write, iclass 18, count 0 2006.238.08:04:58.95#ibcon#enter sib2, iclass 18, count 0 2006.238.08:04:58.95#ibcon#flushed, iclass 18, count 0 2006.238.08:04:58.95#ibcon#about to write, iclass 18, count 0 2006.238.08:04:58.95#ibcon#wrote, iclass 18, count 0 2006.238.08:04:58.95#ibcon#about to read 3, iclass 18, count 0 2006.238.08:04:58.99#ibcon#read 3, iclass 18, count 0 2006.238.08:04:58.99#ibcon#about to read 4, iclass 18, count 0 2006.238.08:04:58.99#ibcon#read 4, iclass 18, count 0 2006.238.08:04:58.99#ibcon#about to read 5, iclass 18, count 0 2006.238.08:04:58.99#ibcon#read 5, iclass 18, count 0 2006.238.08:04:58.99#ibcon#about to read 6, iclass 18, count 0 2006.238.08:04:58.99#ibcon#read 6, iclass 18, count 0 2006.238.08:04:58.99#ibcon#end of sib2, iclass 18, count 0 2006.238.08:04:58.99#ibcon#*after write, iclass 18, count 0 2006.238.08:04:58.99#ibcon#*before return 0, iclass 18, count 0 2006.238.08:04:58.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:04:58.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:04:58.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.08:04:58.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.08:04:58.99$vc4f8/va=4,7 2006.238.08:04:58.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.238.08:04:58.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.238.08:04:58.99#ibcon#ireg 11 cls_cnt 2 2006.238.08:04:58.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:04:59.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:04:59.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:04:59.05#ibcon#enter wrdev, iclass 20, count 2 2006.238.08:04:59.05#ibcon#first serial, iclass 20, count 2 2006.238.08:04:59.05#ibcon#enter sib2, iclass 20, count 2 2006.238.08:04:59.05#ibcon#flushed, iclass 20, count 2 2006.238.08:04:59.05#ibcon#about to write, iclass 20, count 2 2006.238.08:04:59.05#ibcon#wrote, iclass 20, count 2 2006.238.08:04:59.05#ibcon#about to read 3, iclass 20, count 2 2006.238.08:04:59.07#ibcon#read 3, iclass 20, count 2 2006.238.08:04:59.07#ibcon#about to read 4, iclass 20, count 2 2006.238.08:04:59.07#ibcon#read 4, iclass 20, count 2 2006.238.08:04:59.07#ibcon#about to read 5, iclass 20, count 2 2006.238.08:04:59.07#ibcon#read 5, iclass 20, count 2 2006.238.08:04:59.07#ibcon#about to read 6, iclass 20, count 2 2006.238.08:04:59.07#ibcon#read 6, iclass 20, count 2 2006.238.08:04:59.07#ibcon#end of sib2, iclass 20, count 2 2006.238.08:04:59.07#ibcon#*mode == 0, iclass 20, count 2 2006.238.08:04:59.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.238.08:04:59.07#ibcon#[25=AT04-07\r\n] 2006.238.08:04:59.07#ibcon#*before write, iclass 20, count 2 2006.238.08:04:59.07#ibcon#enter sib2, iclass 20, count 2 2006.238.08:04:59.07#ibcon#flushed, iclass 20, count 2 2006.238.08:04:59.07#ibcon#about to write, iclass 20, count 2 2006.238.08:04:59.07#ibcon#wrote, iclass 20, count 2 2006.238.08:04:59.07#ibcon#about to read 3, iclass 20, count 2 2006.238.08:04:59.10#ibcon#read 3, iclass 20, count 2 2006.238.08:04:59.10#ibcon#about to read 4, iclass 20, count 2 2006.238.08:04:59.10#ibcon#read 4, iclass 20, count 2 2006.238.08:04:59.10#ibcon#about to read 5, iclass 20, count 2 2006.238.08:04:59.10#ibcon#read 5, iclass 20, count 2 2006.238.08:04:59.10#ibcon#about to read 6, iclass 20, count 2 2006.238.08:04:59.10#ibcon#read 6, iclass 20, count 2 2006.238.08:04:59.10#ibcon#end of sib2, iclass 20, count 2 2006.238.08:04:59.10#ibcon#*after write, iclass 20, count 2 2006.238.08:04:59.10#ibcon#*before return 0, iclass 20, count 2 2006.238.08:04:59.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:04:59.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:04:59.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.238.08:04:59.10#ibcon#ireg 7 cls_cnt 0 2006.238.08:04:59.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:04:59.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:04:59.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:04:59.22#ibcon#enter wrdev, iclass 20, count 0 2006.238.08:04:59.22#ibcon#first serial, iclass 20, count 0 2006.238.08:04:59.22#ibcon#enter sib2, iclass 20, count 0 2006.238.08:04:59.22#ibcon#flushed, iclass 20, count 0 2006.238.08:04:59.22#ibcon#about to write, iclass 20, count 0 2006.238.08:04:59.22#ibcon#wrote, iclass 20, count 0 2006.238.08:04:59.22#ibcon#about to read 3, iclass 20, count 0 2006.238.08:04:59.24#ibcon#read 3, iclass 20, count 0 2006.238.08:04:59.24#ibcon#about to read 4, iclass 20, count 0 2006.238.08:04:59.24#ibcon#read 4, iclass 20, count 0 2006.238.08:04:59.24#ibcon#about to read 5, iclass 20, count 0 2006.238.08:04:59.24#ibcon#read 5, iclass 20, count 0 2006.238.08:04:59.24#ibcon#about to read 6, iclass 20, count 0 2006.238.08:04:59.24#ibcon#read 6, iclass 20, count 0 2006.238.08:04:59.24#ibcon#end of sib2, iclass 20, count 0 2006.238.08:04:59.24#ibcon#*mode == 0, iclass 20, count 0 2006.238.08:04:59.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.08:04:59.24#ibcon#[25=USB\r\n] 2006.238.08:04:59.24#ibcon#*before write, iclass 20, count 0 2006.238.08:04:59.24#ibcon#enter sib2, iclass 20, count 0 2006.238.08:04:59.24#ibcon#flushed, iclass 20, count 0 2006.238.08:04:59.24#ibcon#about to write, iclass 20, count 0 2006.238.08:04:59.24#ibcon#wrote, iclass 20, count 0 2006.238.08:04:59.24#ibcon#about to read 3, iclass 20, count 0 2006.238.08:04:59.27#ibcon#read 3, iclass 20, count 0 2006.238.08:04:59.27#ibcon#about to read 4, iclass 20, count 0 2006.238.08:04:59.27#ibcon#read 4, iclass 20, count 0 2006.238.08:04:59.27#ibcon#about to read 5, iclass 20, count 0 2006.238.08:04:59.27#ibcon#read 5, iclass 20, count 0 2006.238.08:04:59.27#ibcon#about to read 6, iclass 20, count 0 2006.238.08:04:59.27#ibcon#read 6, iclass 20, count 0 2006.238.08:04:59.27#ibcon#end of sib2, iclass 20, count 0 2006.238.08:04:59.27#ibcon#*after write, iclass 20, count 0 2006.238.08:04:59.27#ibcon#*before return 0, iclass 20, count 0 2006.238.08:04:59.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:04:59.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:04:59.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.08:04:59.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.08:04:59.27$vc4f8/valo=5,652.99 2006.238.08:04:59.27#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.08:04:59.27#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.08:04:59.27#ibcon#ireg 17 cls_cnt 0 2006.238.08:04:59.27#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:04:59.27#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:04:59.27#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:04:59.27#ibcon#enter wrdev, iclass 22, count 0 2006.238.08:04:59.27#ibcon#first serial, iclass 22, count 0 2006.238.08:04:59.27#ibcon#enter sib2, iclass 22, count 0 2006.238.08:04:59.27#ibcon#flushed, iclass 22, count 0 2006.238.08:04:59.27#ibcon#about to write, iclass 22, count 0 2006.238.08:04:59.27#ibcon#wrote, iclass 22, count 0 2006.238.08:04:59.27#ibcon#about to read 3, iclass 22, count 0 2006.238.08:04:59.29#ibcon#read 3, iclass 22, count 0 2006.238.08:04:59.29#ibcon#about to read 4, iclass 22, count 0 2006.238.08:04:59.29#ibcon#read 4, iclass 22, count 0 2006.238.08:04:59.29#ibcon#about to read 5, iclass 22, count 0 2006.238.08:04:59.29#ibcon#read 5, iclass 22, count 0 2006.238.08:04:59.29#ibcon#about to read 6, iclass 22, count 0 2006.238.08:04:59.29#ibcon#read 6, iclass 22, count 0 2006.238.08:04:59.29#ibcon#end of sib2, iclass 22, count 0 2006.238.08:04:59.29#ibcon#*mode == 0, iclass 22, count 0 2006.238.08:04:59.29#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.08:04:59.29#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:04:59.29#ibcon#*before write, iclass 22, count 0 2006.238.08:04:59.29#ibcon#enter sib2, iclass 22, count 0 2006.238.08:04:59.29#ibcon#flushed, iclass 22, count 0 2006.238.08:04:59.29#ibcon#about to write, iclass 22, count 0 2006.238.08:04:59.29#ibcon#wrote, iclass 22, count 0 2006.238.08:04:59.29#ibcon#about to read 3, iclass 22, count 0 2006.238.08:04:59.33#ibcon#read 3, iclass 22, count 0 2006.238.08:04:59.33#ibcon#about to read 4, iclass 22, count 0 2006.238.08:04:59.33#ibcon#read 4, iclass 22, count 0 2006.238.08:04:59.33#ibcon#about to read 5, iclass 22, count 0 2006.238.08:04:59.33#ibcon#read 5, iclass 22, count 0 2006.238.08:04:59.33#ibcon#about to read 6, iclass 22, count 0 2006.238.08:04:59.33#ibcon#read 6, iclass 22, count 0 2006.238.08:04:59.33#ibcon#end of sib2, iclass 22, count 0 2006.238.08:04:59.33#ibcon#*after write, iclass 22, count 0 2006.238.08:04:59.33#ibcon#*before return 0, iclass 22, count 0 2006.238.08:04:59.33#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:04:59.33#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:04:59.33#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.08:04:59.33#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.08:04:59.33$vc4f8/va=5,8 2006.238.08:04:59.33#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.238.08:04:59.33#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.238.08:04:59.33#ibcon#ireg 11 cls_cnt 2 2006.238.08:04:59.33#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:04:59.39#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:04:59.39#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:04:59.39#ibcon#enter wrdev, iclass 24, count 2 2006.238.08:04:59.39#ibcon#first serial, iclass 24, count 2 2006.238.08:04:59.39#ibcon#enter sib2, iclass 24, count 2 2006.238.08:04:59.39#ibcon#flushed, iclass 24, count 2 2006.238.08:04:59.39#ibcon#about to write, iclass 24, count 2 2006.238.08:04:59.39#ibcon#wrote, iclass 24, count 2 2006.238.08:04:59.39#ibcon#about to read 3, iclass 24, count 2 2006.238.08:04:59.41#ibcon#read 3, iclass 24, count 2 2006.238.08:04:59.41#ibcon#about to read 4, iclass 24, count 2 2006.238.08:04:59.41#ibcon#read 4, iclass 24, count 2 2006.238.08:04:59.41#ibcon#about to read 5, iclass 24, count 2 2006.238.08:04:59.41#ibcon#read 5, iclass 24, count 2 2006.238.08:04:59.41#ibcon#about to read 6, iclass 24, count 2 2006.238.08:04:59.41#ibcon#read 6, iclass 24, count 2 2006.238.08:04:59.41#ibcon#end of sib2, iclass 24, count 2 2006.238.08:04:59.41#ibcon#*mode == 0, iclass 24, count 2 2006.238.08:04:59.41#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.238.08:04:59.41#ibcon#[25=AT05-08\r\n] 2006.238.08:04:59.41#ibcon#*before write, iclass 24, count 2 2006.238.08:04:59.41#ibcon#enter sib2, iclass 24, count 2 2006.238.08:04:59.41#ibcon#flushed, iclass 24, count 2 2006.238.08:04:59.41#ibcon#about to write, iclass 24, count 2 2006.238.08:04:59.41#ibcon#wrote, iclass 24, count 2 2006.238.08:04:59.41#ibcon#about to read 3, iclass 24, count 2 2006.238.08:04:59.44#ibcon#read 3, iclass 24, count 2 2006.238.08:04:59.44#ibcon#about to read 4, iclass 24, count 2 2006.238.08:04:59.44#ibcon#read 4, iclass 24, count 2 2006.238.08:04:59.44#ibcon#about to read 5, iclass 24, count 2 2006.238.08:04:59.44#ibcon#read 5, iclass 24, count 2 2006.238.08:04:59.44#ibcon#about to read 6, iclass 24, count 2 2006.238.08:04:59.44#ibcon#read 6, iclass 24, count 2 2006.238.08:04:59.44#ibcon#end of sib2, iclass 24, count 2 2006.238.08:04:59.44#ibcon#*after write, iclass 24, count 2 2006.238.08:04:59.44#ibcon#*before return 0, iclass 24, count 2 2006.238.08:04:59.44#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:04:59.44#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:04:59.44#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.238.08:04:59.44#ibcon#ireg 7 cls_cnt 0 2006.238.08:04:59.44#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:04:59.56#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:04:59.56#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:04:59.56#ibcon#enter wrdev, iclass 24, count 0 2006.238.08:04:59.56#ibcon#first serial, iclass 24, count 0 2006.238.08:04:59.56#ibcon#enter sib2, iclass 24, count 0 2006.238.08:04:59.56#ibcon#flushed, iclass 24, count 0 2006.238.08:04:59.56#ibcon#about to write, iclass 24, count 0 2006.238.08:04:59.56#ibcon#wrote, iclass 24, count 0 2006.238.08:04:59.56#ibcon#about to read 3, iclass 24, count 0 2006.238.08:04:59.58#ibcon#read 3, iclass 24, count 0 2006.238.08:04:59.58#ibcon#about to read 4, iclass 24, count 0 2006.238.08:04:59.58#ibcon#read 4, iclass 24, count 0 2006.238.08:04:59.58#ibcon#about to read 5, iclass 24, count 0 2006.238.08:04:59.58#ibcon#read 5, iclass 24, count 0 2006.238.08:04:59.58#ibcon#about to read 6, iclass 24, count 0 2006.238.08:04:59.58#ibcon#read 6, iclass 24, count 0 2006.238.08:04:59.58#ibcon#end of sib2, iclass 24, count 0 2006.238.08:04:59.58#ibcon#*mode == 0, iclass 24, count 0 2006.238.08:04:59.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.08:04:59.58#ibcon#[25=USB\r\n] 2006.238.08:04:59.58#ibcon#*before write, iclass 24, count 0 2006.238.08:04:59.58#ibcon#enter sib2, iclass 24, count 0 2006.238.08:04:59.58#ibcon#flushed, iclass 24, count 0 2006.238.08:04:59.58#ibcon#about to write, iclass 24, count 0 2006.238.08:04:59.58#ibcon#wrote, iclass 24, count 0 2006.238.08:04:59.58#ibcon#about to read 3, iclass 24, count 0 2006.238.08:04:59.61#ibcon#read 3, iclass 24, count 0 2006.238.08:04:59.61#ibcon#about to read 4, iclass 24, count 0 2006.238.08:04:59.61#ibcon#read 4, iclass 24, count 0 2006.238.08:04:59.61#ibcon#about to read 5, iclass 24, count 0 2006.238.08:04:59.61#ibcon#read 5, iclass 24, count 0 2006.238.08:04:59.61#ibcon#about to read 6, iclass 24, count 0 2006.238.08:04:59.61#ibcon#read 6, iclass 24, count 0 2006.238.08:04:59.61#ibcon#end of sib2, iclass 24, count 0 2006.238.08:04:59.61#ibcon#*after write, iclass 24, count 0 2006.238.08:04:59.61#ibcon#*before return 0, iclass 24, count 0 2006.238.08:04:59.61#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:04:59.61#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:04:59.61#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.08:04:59.61#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.08:04:59.61$vc4f8/valo=6,772.99 2006.238.08:04:59.61#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.08:04:59.61#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.08:04:59.61#ibcon#ireg 17 cls_cnt 0 2006.238.08:04:59.61#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:04:59.61#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:04:59.61#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:04:59.61#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:04:59.61#ibcon#first serial, iclass 26, count 0 2006.238.08:04:59.61#ibcon#enter sib2, iclass 26, count 0 2006.238.08:04:59.61#ibcon#flushed, iclass 26, count 0 2006.238.08:04:59.61#ibcon#about to write, iclass 26, count 0 2006.238.08:04:59.61#ibcon#wrote, iclass 26, count 0 2006.238.08:04:59.61#ibcon#about to read 3, iclass 26, count 0 2006.238.08:04:59.63#ibcon#read 3, iclass 26, count 0 2006.238.08:04:59.63#ibcon#about to read 4, iclass 26, count 0 2006.238.08:04:59.63#ibcon#read 4, iclass 26, count 0 2006.238.08:04:59.63#ibcon#about to read 5, iclass 26, count 0 2006.238.08:04:59.63#ibcon#read 5, iclass 26, count 0 2006.238.08:04:59.63#ibcon#about to read 6, iclass 26, count 0 2006.238.08:04:59.63#ibcon#read 6, iclass 26, count 0 2006.238.08:04:59.63#ibcon#end of sib2, iclass 26, count 0 2006.238.08:04:59.63#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:04:59.63#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:04:59.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:04:59.63#ibcon#*before write, iclass 26, count 0 2006.238.08:04:59.63#ibcon#enter sib2, iclass 26, count 0 2006.238.08:04:59.63#ibcon#flushed, iclass 26, count 0 2006.238.08:04:59.63#ibcon#about to write, iclass 26, count 0 2006.238.08:04:59.63#ibcon#wrote, iclass 26, count 0 2006.238.08:04:59.63#ibcon#about to read 3, iclass 26, count 0 2006.238.08:04:59.67#ibcon#read 3, iclass 26, count 0 2006.238.08:04:59.67#ibcon#about to read 4, iclass 26, count 0 2006.238.08:04:59.67#ibcon#read 4, iclass 26, count 0 2006.238.08:04:59.67#ibcon#about to read 5, iclass 26, count 0 2006.238.08:04:59.67#ibcon#read 5, iclass 26, count 0 2006.238.08:04:59.67#ibcon#about to read 6, iclass 26, count 0 2006.238.08:04:59.67#ibcon#read 6, iclass 26, count 0 2006.238.08:04:59.67#ibcon#end of sib2, iclass 26, count 0 2006.238.08:04:59.67#ibcon#*after write, iclass 26, count 0 2006.238.08:04:59.67#ibcon#*before return 0, iclass 26, count 0 2006.238.08:04:59.67#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:04:59.67#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:04:59.67#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:04:59.67#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:04:59.67$vc4f8/va=6,7 2006.238.08:04:59.67#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.08:04:59.67#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.08:04:59.67#ibcon#ireg 11 cls_cnt 2 2006.238.08:04:59.67#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:04:59.73#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:04:59.73#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:04:59.73#ibcon#enter wrdev, iclass 28, count 2 2006.238.08:04:59.73#ibcon#first serial, iclass 28, count 2 2006.238.08:04:59.73#ibcon#enter sib2, iclass 28, count 2 2006.238.08:04:59.73#ibcon#flushed, iclass 28, count 2 2006.238.08:04:59.73#ibcon#about to write, iclass 28, count 2 2006.238.08:04:59.73#ibcon#wrote, iclass 28, count 2 2006.238.08:04:59.73#ibcon#about to read 3, iclass 28, count 2 2006.238.08:04:59.75#ibcon#read 3, iclass 28, count 2 2006.238.08:04:59.75#ibcon#about to read 4, iclass 28, count 2 2006.238.08:04:59.75#ibcon#read 4, iclass 28, count 2 2006.238.08:04:59.75#ibcon#about to read 5, iclass 28, count 2 2006.238.08:04:59.75#ibcon#read 5, iclass 28, count 2 2006.238.08:04:59.75#ibcon#about to read 6, iclass 28, count 2 2006.238.08:04:59.75#ibcon#read 6, iclass 28, count 2 2006.238.08:04:59.75#ibcon#end of sib2, iclass 28, count 2 2006.238.08:04:59.75#ibcon#*mode == 0, iclass 28, count 2 2006.238.08:04:59.75#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.08:04:59.75#ibcon#[25=AT06-07\r\n] 2006.238.08:04:59.75#ibcon#*before write, iclass 28, count 2 2006.238.08:04:59.75#ibcon#enter sib2, iclass 28, count 2 2006.238.08:04:59.75#ibcon#flushed, iclass 28, count 2 2006.238.08:04:59.75#ibcon#about to write, iclass 28, count 2 2006.238.08:04:59.75#ibcon#wrote, iclass 28, count 2 2006.238.08:04:59.75#ibcon#about to read 3, iclass 28, count 2 2006.238.08:04:59.78#ibcon#read 3, iclass 28, count 2 2006.238.08:04:59.78#ibcon#about to read 4, iclass 28, count 2 2006.238.08:04:59.78#ibcon#read 4, iclass 28, count 2 2006.238.08:04:59.78#ibcon#about to read 5, iclass 28, count 2 2006.238.08:04:59.78#ibcon#read 5, iclass 28, count 2 2006.238.08:04:59.78#ibcon#about to read 6, iclass 28, count 2 2006.238.08:04:59.78#ibcon#read 6, iclass 28, count 2 2006.238.08:04:59.78#ibcon#end of sib2, iclass 28, count 2 2006.238.08:04:59.78#ibcon#*after write, iclass 28, count 2 2006.238.08:04:59.78#ibcon#*before return 0, iclass 28, count 2 2006.238.08:04:59.78#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:04:59.78#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:04:59.78#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.08:04:59.78#ibcon#ireg 7 cls_cnt 0 2006.238.08:04:59.78#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:04:59.90#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:04:59.90#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:04:59.90#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:04:59.90#ibcon#first serial, iclass 28, count 0 2006.238.08:04:59.90#ibcon#enter sib2, iclass 28, count 0 2006.238.08:04:59.90#ibcon#flushed, iclass 28, count 0 2006.238.08:04:59.90#ibcon#about to write, iclass 28, count 0 2006.238.08:04:59.90#ibcon#wrote, iclass 28, count 0 2006.238.08:04:59.90#ibcon#about to read 3, iclass 28, count 0 2006.238.08:04:59.92#ibcon#read 3, iclass 28, count 0 2006.238.08:04:59.92#ibcon#about to read 4, iclass 28, count 0 2006.238.08:04:59.92#ibcon#read 4, iclass 28, count 0 2006.238.08:04:59.92#ibcon#about to read 5, iclass 28, count 0 2006.238.08:04:59.92#ibcon#read 5, iclass 28, count 0 2006.238.08:04:59.92#ibcon#about to read 6, iclass 28, count 0 2006.238.08:04:59.92#ibcon#read 6, iclass 28, count 0 2006.238.08:04:59.92#ibcon#end of sib2, iclass 28, count 0 2006.238.08:04:59.92#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:04:59.92#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:04:59.92#ibcon#[25=USB\r\n] 2006.238.08:04:59.92#ibcon#*before write, iclass 28, count 0 2006.238.08:04:59.92#ibcon#enter sib2, iclass 28, count 0 2006.238.08:04:59.92#ibcon#flushed, iclass 28, count 0 2006.238.08:04:59.92#ibcon#about to write, iclass 28, count 0 2006.238.08:04:59.92#ibcon#wrote, iclass 28, count 0 2006.238.08:04:59.92#ibcon#about to read 3, iclass 28, count 0 2006.238.08:04:59.95#ibcon#read 3, iclass 28, count 0 2006.238.08:04:59.95#ibcon#about to read 4, iclass 28, count 0 2006.238.08:04:59.95#ibcon#read 4, iclass 28, count 0 2006.238.08:04:59.95#ibcon#about to read 5, iclass 28, count 0 2006.238.08:04:59.95#ibcon#read 5, iclass 28, count 0 2006.238.08:04:59.95#ibcon#about to read 6, iclass 28, count 0 2006.238.08:04:59.95#ibcon#read 6, iclass 28, count 0 2006.238.08:04:59.95#ibcon#end of sib2, iclass 28, count 0 2006.238.08:04:59.95#ibcon#*after write, iclass 28, count 0 2006.238.08:04:59.95#ibcon#*before return 0, iclass 28, count 0 2006.238.08:04:59.95#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:04:59.95#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:04:59.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:04:59.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:04:59.95$vc4f8/valo=7,832.99 2006.238.08:04:59.95#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.08:04:59.95#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.08:04:59.95#ibcon#ireg 17 cls_cnt 0 2006.238.08:04:59.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:04:59.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:04:59.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:04:59.95#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:04:59.95#ibcon#first serial, iclass 30, count 0 2006.238.08:04:59.95#ibcon#enter sib2, iclass 30, count 0 2006.238.08:04:59.95#ibcon#flushed, iclass 30, count 0 2006.238.08:04:59.95#ibcon#about to write, iclass 30, count 0 2006.238.08:04:59.95#ibcon#wrote, iclass 30, count 0 2006.238.08:04:59.95#ibcon#about to read 3, iclass 30, count 0 2006.238.08:04:59.97#ibcon#read 3, iclass 30, count 0 2006.238.08:04:59.97#ibcon#about to read 4, iclass 30, count 0 2006.238.08:04:59.97#ibcon#read 4, iclass 30, count 0 2006.238.08:04:59.97#ibcon#about to read 5, iclass 30, count 0 2006.238.08:04:59.97#ibcon#read 5, iclass 30, count 0 2006.238.08:04:59.97#ibcon#about to read 6, iclass 30, count 0 2006.238.08:04:59.97#ibcon#read 6, iclass 30, count 0 2006.238.08:04:59.97#ibcon#end of sib2, iclass 30, count 0 2006.238.08:04:59.97#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:04:59.97#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:04:59.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:04:59.97#ibcon#*before write, iclass 30, count 0 2006.238.08:04:59.97#ibcon#enter sib2, iclass 30, count 0 2006.238.08:04:59.97#ibcon#flushed, iclass 30, count 0 2006.238.08:04:59.97#ibcon#about to write, iclass 30, count 0 2006.238.08:04:59.97#ibcon#wrote, iclass 30, count 0 2006.238.08:04:59.97#ibcon#about to read 3, iclass 30, count 0 2006.238.08:05:00.01#ibcon#read 3, iclass 30, count 0 2006.238.08:05:00.01#ibcon#about to read 4, iclass 30, count 0 2006.238.08:05:00.01#ibcon#read 4, iclass 30, count 0 2006.238.08:05:00.01#ibcon#about to read 5, iclass 30, count 0 2006.238.08:05:00.01#ibcon#read 5, iclass 30, count 0 2006.238.08:05:00.01#ibcon#about to read 6, iclass 30, count 0 2006.238.08:05:00.01#ibcon#read 6, iclass 30, count 0 2006.238.08:05:00.01#ibcon#end of sib2, iclass 30, count 0 2006.238.08:05:00.01#ibcon#*after write, iclass 30, count 0 2006.238.08:05:00.01#ibcon#*before return 0, iclass 30, count 0 2006.238.08:05:00.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:05:00.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:05:00.01#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:05:00.01#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:05:00.01$vc4f8/va=7,7 2006.238.08:05:00.01#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.238.08:05:00.01#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.238.08:05:00.01#ibcon#ireg 11 cls_cnt 2 2006.238.08:05:00.01#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:05:00.07#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:05:00.07#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:05:00.07#ibcon#enter wrdev, iclass 32, count 2 2006.238.08:05:00.07#ibcon#first serial, iclass 32, count 2 2006.238.08:05:00.07#ibcon#enter sib2, iclass 32, count 2 2006.238.08:05:00.07#ibcon#flushed, iclass 32, count 2 2006.238.08:05:00.07#ibcon#about to write, iclass 32, count 2 2006.238.08:05:00.07#ibcon#wrote, iclass 32, count 2 2006.238.08:05:00.07#ibcon#about to read 3, iclass 32, count 2 2006.238.08:05:00.09#ibcon#read 3, iclass 32, count 2 2006.238.08:05:00.09#ibcon#about to read 4, iclass 32, count 2 2006.238.08:05:00.09#ibcon#read 4, iclass 32, count 2 2006.238.08:05:00.09#ibcon#about to read 5, iclass 32, count 2 2006.238.08:05:00.09#ibcon#read 5, iclass 32, count 2 2006.238.08:05:00.09#ibcon#about to read 6, iclass 32, count 2 2006.238.08:05:00.09#ibcon#read 6, iclass 32, count 2 2006.238.08:05:00.09#ibcon#end of sib2, iclass 32, count 2 2006.238.08:05:00.09#ibcon#*mode == 0, iclass 32, count 2 2006.238.08:05:00.09#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.238.08:05:00.09#ibcon#[25=AT07-07\r\n] 2006.238.08:05:00.09#ibcon#*before write, iclass 32, count 2 2006.238.08:05:00.09#ibcon#enter sib2, iclass 32, count 2 2006.238.08:05:00.09#ibcon#flushed, iclass 32, count 2 2006.238.08:05:00.09#ibcon#about to write, iclass 32, count 2 2006.238.08:05:00.09#ibcon#wrote, iclass 32, count 2 2006.238.08:05:00.09#ibcon#about to read 3, iclass 32, count 2 2006.238.08:05:00.12#ibcon#read 3, iclass 32, count 2 2006.238.08:05:00.12#ibcon#about to read 4, iclass 32, count 2 2006.238.08:05:00.12#ibcon#read 4, iclass 32, count 2 2006.238.08:05:00.12#ibcon#about to read 5, iclass 32, count 2 2006.238.08:05:00.12#ibcon#read 5, iclass 32, count 2 2006.238.08:05:00.12#ibcon#about to read 6, iclass 32, count 2 2006.238.08:05:00.12#ibcon#read 6, iclass 32, count 2 2006.238.08:05:00.12#ibcon#end of sib2, iclass 32, count 2 2006.238.08:05:00.12#ibcon#*after write, iclass 32, count 2 2006.238.08:05:00.12#ibcon#*before return 0, iclass 32, count 2 2006.238.08:05:00.12#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:05:00.12#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:05:00.12#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.238.08:05:00.12#ibcon#ireg 7 cls_cnt 0 2006.238.08:05:00.12#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:05:00.24#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:05:00.24#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:05:00.24#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:05:00.24#ibcon#first serial, iclass 32, count 0 2006.238.08:05:00.24#ibcon#enter sib2, iclass 32, count 0 2006.238.08:05:00.24#ibcon#flushed, iclass 32, count 0 2006.238.08:05:00.24#ibcon#about to write, iclass 32, count 0 2006.238.08:05:00.24#ibcon#wrote, iclass 32, count 0 2006.238.08:05:00.24#ibcon#about to read 3, iclass 32, count 0 2006.238.08:05:00.26#ibcon#read 3, iclass 32, count 0 2006.238.08:05:00.26#ibcon#about to read 4, iclass 32, count 0 2006.238.08:05:00.26#ibcon#read 4, iclass 32, count 0 2006.238.08:05:00.26#ibcon#about to read 5, iclass 32, count 0 2006.238.08:05:00.26#ibcon#read 5, iclass 32, count 0 2006.238.08:05:00.26#ibcon#about to read 6, iclass 32, count 0 2006.238.08:05:00.26#ibcon#read 6, iclass 32, count 0 2006.238.08:05:00.26#ibcon#end of sib2, iclass 32, count 0 2006.238.08:05:00.26#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:05:00.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:05:00.26#ibcon#[25=USB\r\n] 2006.238.08:05:00.26#ibcon#*before write, iclass 32, count 0 2006.238.08:05:00.26#ibcon#enter sib2, iclass 32, count 0 2006.238.08:05:00.26#ibcon#flushed, iclass 32, count 0 2006.238.08:05:00.26#ibcon#about to write, iclass 32, count 0 2006.238.08:05:00.26#ibcon#wrote, iclass 32, count 0 2006.238.08:05:00.26#ibcon#about to read 3, iclass 32, count 0 2006.238.08:05:00.29#ibcon#read 3, iclass 32, count 0 2006.238.08:05:00.29#ibcon#about to read 4, iclass 32, count 0 2006.238.08:05:00.29#ibcon#read 4, iclass 32, count 0 2006.238.08:05:00.29#ibcon#about to read 5, iclass 32, count 0 2006.238.08:05:00.29#ibcon#read 5, iclass 32, count 0 2006.238.08:05:00.29#ibcon#about to read 6, iclass 32, count 0 2006.238.08:05:00.29#ibcon#read 6, iclass 32, count 0 2006.238.08:05:00.29#ibcon#end of sib2, iclass 32, count 0 2006.238.08:05:00.29#ibcon#*after write, iclass 32, count 0 2006.238.08:05:00.29#ibcon#*before return 0, iclass 32, count 0 2006.238.08:05:00.29#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:05:00.29#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:05:00.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:05:00.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:05:00.29$vc4f8/valo=8,852.99 2006.238.08:05:00.29#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.238.08:05:00.29#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.238.08:05:00.29#ibcon#ireg 17 cls_cnt 0 2006.238.08:05:00.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:05:00.29#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:05:00.29#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:05:00.29#ibcon#enter wrdev, iclass 34, count 0 2006.238.08:05:00.29#ibcon#first serial, iclass 34, count 0 2006.238.08:05:00.29#ibcon#enter sib2, iclass 34, count 0 2006.238.08:05:00.29#ibcon#flushed, iclass 34, count 0 2006.238.08:05:00.29#ibcon#about to write, iclass 34, count 0 2006.238.08:05:00.29#ibcon#wrote, iclass 34, count 0 2006.238.08:05:00.29#ibcon#about to read 3, iclass 34, count 0 2006.238.08:05:00.31#ibcon#read 3, iclass 34, count 0 2006.238.08:05:00.31#ibcon#about to read 4, iclass 34, count 0 2006.238.08:05:00.31#ibcon#read 4, iclass 34, count 0 2006.238.08:05:00.31#ibcon#about to read 5, iclass 34, count 0 2006.238.08:05:00.31#ibcon#read 5, iclass 34, count 0 2006.238.08:05:00.31#ibcon#about to read 6, iclass 34, count 0 2006.238.08:05:00.31#ibcon#read 6, iclass 34, count 0 2006.238.08:05:00.31#ibcon#end of sib2, iclass 34, count 0 2006.238.08:05:00.31#ibcon#*mode == 0, iclass 34, count 0 2006.238.08:05:00.31#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.08:05:00.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:05:00.31#ibcon#*before write, iclass 34, count 0 2006.238.08:05:00.31#ibcon#enter sib2, iclass 34, count 0 2006.238.08:05:00.31#ibcon#flushed, iclass 34, count 0 2006.238.08:05:00.31#ibcon#about to write, iclass 34, count 0 2006.238.08:05:00.31#ibcon#wrote, iclass 34, count 0 2006.238.08:05:00.31#ibcon#about to read 3, iclass 34, count 0 2006.238.08:05:00.35#ibcon#read 3, iclass 34, count 0 2006.238.08:05:00.35#ibcon#about to read 4, iclass 34, count 0 2006.238.08:05:00.35#ibcon#read 4, iclass 34, count 0 2006.238.08:05:00.35#ibcon#about to read 5, iclass 34, count 0 2006.238.08:05:00.35#ibcon#read 5, iclass 34, count 0 2006.238.08:05:00.35#ibcon#about to read 6, iclass 34, count 0 2006.238.08:05:00.35#ibcon#read 6, iclass 34, count 0 2006.238.08:05:00.35#ibcon#end of sib2, iclass 34, count 0 2006.238.08:05:00.35#ibcon#*after write, iclass 34, count 0 2006.238.08:05:00.35#ibcon#*before return 0, iclass 34, count 0 2006.238.08:05:00.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:05:00.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:05:00.35#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.08:05:00.35#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.08:05:00.35$vc4f8/va=8,7 2006.238.08:05:00.35#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.238.08:05:00.35#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.238.08:05:00.35#ibcon#ireg 11 cls_cnt 2 2006.238.08:05:00.35#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:05:00.41#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:05:00.41#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:05:00.41#ibcon#enter wrdev, iclass 36, count 2 2006.238.08:05:00.41#ibcon#first serial, iclass 36, count 2 2006.238.08:05:00.41#ibcon#enter sib2, iclass 36, count 2 2006.238.08:05:00.41#ibcon#flushed, iclass 36, count 2 2006.238.08:05:00.41#ibcon#about to write, iclass 36, count 2 2006.238.08:05:00.41#ibcon#wrote, iclass 36, count 2 2006.238.08:05:00.41#ibcon#about to read 3, iclass 36, count 2 2006.238.08:05:00.43#ibcon#read 3, iclass 36, count 2 2006.238.08:05:00.43#ibcon#about to read 4, iclass 36, count 2 2006.238.08:05:00.43#ibcon#read 4, iclass 36, count 2 2006.238.08:05:00.43#ibcon#about to read 5, iclass 36, count 2 2006.238.08:05:00.43#ibcon#read 5, iclass 36, count 2 2006.238.08:05:00.43#ibcon#about to read 6, iclass 36, count 2 2006.238.08:05:00.43#ibcon#read 6, iclass 36, count 2 2006.238.08:05:00.43#ibcon#end of sib2, iclass 36, count 2 2006.238.08:05:00.43#ibcon#*mode == 0, iclass 36, count 2 2006.238.08:05:00.43#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.238.08:05:00.43#ibcon#[25=AT08-07\r\n] 2006.238.08:05:00.43#ibcon#*before write, iclass 36, count 2 2006.238.08:05:00.43#ibcon#enter sib2, iclass 36, count 2 2006.238.08:05:00.43#ibcon#flushed, iclass 36, count 2 2006.238.08:05:00.43#ibcon#about to write, iclass 36, count 2 2006.238.08:05:00.43#ibcon#wrote, iclass 36, count 2 2006.238.08:05:00.43#ibcon#about to read 3, iclass 36, count 2 2006.238.08:05:00.46#ibcon#read 3, iclass 36, count 2 2006.238.08:05:00.46#ibcon#about to read 4, iclass 36, count 2 2006.238.08:05:00.46#ibcon#read 4, iclass 36, count 2 2006.238.08:05:00.46#ibcon#about to read 5, iclass 36, count 2 2006.238.08:05:00.46#ibcon#read 5, iclass 36, count 2 2006.238.08:05:00.46#ibcon#about to read 6, iclass 36, count 2 2006.238.08:05:00.46#ibcon#read 6, iclass 36, count 2 2006.238.08:05:00.46#ibcon#end of sib2, iclass 36, count 2 2006.238.08:05:00.46#ibcon#*after write, iclass 36, count 2 2006.238.08:05:00.46#ibcon#*before return 0, iclass 36, count 2 2006.238.08:05:00.46#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:05:00.46#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:05:00.46#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.238.08:05:00.46#ibcon#ireg 7 cls_cnt 0 2006.238.08:05:00.46#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:05:00.58#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:05:00.58#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:05:00.58#ibcon#enter wrdev, iclass 36, count 0 2006.238.08:05:00.58#ibcon#first serial, iclass 36, count 0 2006.238.08:05:00.58#ibcon#enter sib2, iclass 36, count 0 2006.238.08:05:00.58#ibcon#flushed, iclass 36, count 0 2006.238.08:05:00.58#ibcon#about to write, iclass 36, count 0 2006.238.08:05:00.58#ibcon#wrote, iclass 36, count 0 2006.238.08:05:00.58#ibcon#about to read 3, iclass 36, count 0 2006.238.08:05:00.60#ibcon#read 3, iclass 36, count 0 2006.238.08:05:00.60#ibcon#about to read 4, iclass 36, count 0 2006.238.08:05:00.60#ibcon#read 4, iclass 36, count 0 2006.238.08:05:00.60#ibcon#about to read 5, iclass 36, count 0 2006.238.08:05:00.60#ibcon#read 5, iclass 36, count 0 2006.238.08:05:00.60#ibcon#about to read 6, iclass 36, count 0 2006.238.08:05:00.60#ibcon#read 6, iclass 36, count 0 2006.238.08:05:00.60#ibcon#end of sib2, iclass 36, count 0 2006.238.08:05:00.60#ibcon#*mode == 0, iclass 36, count 0 2006.238.08:05:00.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.08:05:00.60#ibcon#[25=USB\r\n] 2006.238.08:05:00.60#ibcon#*before write, iclass 36, count 0 2006.238.08:05:00.60#ibcon#enter sib2, iclass 36, count 0 2006.238.08:05:00.60#ibcon#flushed, iclass 36, count 0 2006.238.08:05:00.60#ibcon#about to write, iclass 36, count 0 2006.238.08:05:00.60#ibcon#wrote, iclass 36, count 0 2006.238.08:05:00.60#ibcon#about to read 3, iclass 36, count 0 2006.238.08:05:00.63#ibcon#read 3, iclass 36, count 0 2006.238.08:05:00.63#ibcon#about to read 4, iclass 36, count 0 2006.238.08:05:00.63#ibcon#read 4, iclass 36, count 0 2006.238.08:05:00.63#ibcon#about to read 5, iclass 36, count 0 2006.238.08:05:00.63#ibcon#read 5, iclass 36, count 0 2006.238.08:05:00.63#ibcon#about to read 6, iclass 36, count 0 2006.238.08:05:00.63#ibcon#read 6, iclass 36, count 0 2006.238.08:05:00.63#ibcon#end of sib2, iclass 36, count 0 2006.238.08:05:00.63#ibcon#*after write, iclass 36, count 0 2006.238.08:05:00.63#ibcon#*before return 0, iclass 36, count 0 2006.238.08:05:00.63#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:05:00.63#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:05:00.63#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.08:05:00.63#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.08:05:00.63$vc4f8/vblo=1,632.99 2006.238.08:05:00.63#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.238.08:05:00.63#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.238.08:05:00.63#ibcon#ireg 17 cls_cnt 0 2006.238.08:05:00.63#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:05:00.63#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:05:00.63#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:05:00.63#ibcon#enter wrdev, iclass 38, count 0 2006.238.08:05:00.63#ibcon#first serial, iclass 38, count 0 2006.238.08:05:00.63#ibcon#enter sib2, iclass 38, count 0 2006.238.08:05:00.63#ibcon#flushed, iclass 38, count 0 2006.238.08:05:00.63#ibcon#about to write, iclass 38, count 0 2006.238.08:05:00.63#ibcon#wrote, iclass 38, count 0 2006.238.08:05:00.63#ibcon#about to read 3, iclass 38, count 0 2006.238.08:05:00.65#ibcon#read 3, iclass 38, count 0 2006.238.08:05:00.65#ibcon#about to read 4, iclass 38, count 0 2006.238.08:05:00.65#ibcon#read 4, iclass 38, count 0 2006.238.08:05:00.65#ibcon#about to read 5, iclass 38, count 0 2006.238.08:05:00.65#ibcon#read 5, iclass 38, count 0 2006.238.08:05:00.65#ibcon#about to read 6, iclass 38, count 0 2006.238.08:05:00.65#ibcon#read 6, iclass 38, count 0 2006.238.08:05:00.65#ibcon#end of sib2, iclass 38, count 0 2006.238.08:05:00.65#ibcon#*mode == 0, iclass 38, count 0 2006.238.08:05:00.65#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.08:05:00.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:05:00.65#ibcon#*before write, iclass 38, count 0 2006.238.08:05:00.65#ibcon#enter sib2, iclass 38, count 0 2006.238.08:05:00.65#ibcon#flushed, iclass 38, count 0 2006.238.08:05:00.65#ibcon#about to write, iclass 38, count 0 2006.238.08:05:00.65#ibcon#wrote, iclass 38, count 0 2006.238.08:05:00.65#ibcon#about to read 3, iclass 38, count 0 2006.238.08:05:00.69#ibcon#read 3, iclass 38, count 0 2006.238.08:05:00.69#ibcon#about to read 4, iclass 38, count 0 2006.238.08:05:00.69#ibcon#read 4, iclass 38, count 0 2006.238.08:05:00.69#ibcon#about to read 5, iclass 38, count 0 2006.238.08:05:00.69#ibcon#read 5, iclass 38, count 0 2006.238.08:05:00.69#ibcon#about to read 6, iclass 38, count 0 2006.238.08:05:00.69#ibcon#read 6, iclass 38, count 0 2006.238.08:05:00.69#ibcon#end of sib2, iclass 38, count 0 2006.238.08:05:00.69#ibcon#*after write, iclass 38, count 0 2006.238.08:05:00.69#ibcon#*before return 0, iclass 38, count 0 2006.238.08:05:00.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:05:00.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:05:00.69#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.08:05:00.69#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.08:05:00.69$vc4f8/vb=1,4 2006.238.08:05:00.69#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.238.08:05:00.69#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.238.08:05:00.69#ibcon#ireg 11 cls_cnt 2 2006.238.08:05:00.69#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:05:00.69#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:05:00.69#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:05:00.69#ibcon#enter wrdev, iclass 40, count 2 2006.238.08:05:00.69#ibcon#first serial, iclass 40, count 2 2006.238.08:05:00.69#ibcon#enter sib2, iclass 40, count 2 2006.238.08:05:00.69#ibcon#flushed, iclass 40, count 2 2006.238.08:05:00.69#ibcon#about to write, iclass 40, count 2 2006.238.08:05:00.69#ibcon#wrote, iclass 40, count 2 2006.238.08:05:00.69#ibcon#about to read 3, iclass 40, count 2 2006.238.08:05:00.71#ibcon#read 3, iclass 40, count 2 2006.238.08:05:00.71#ibcon#about to read 4, iclass 40, count 2 2006.238.08:05:00.71#ibcon#read 4, iclass 40, count 2 2006.238.08:05:00.71#ibcon#about to read 5, iclass 40, count 2 2006.238.08:05:00.71#ibcon#read 5, iclass 40, count 2 2006.238.08:05:00.71#ibcon#about to read 6, iclass 40, count 2 2006.238.08:05:00.71#ibcon#read 6, iclass 40, count 2 2006.238.08:05:00.71#ibcon#end of sib2, iclass 40, count 2 2006.238.08:05:00.71#ibcon#*mode == 0, iclass 40, count 2 2006.238.08:05:00.71#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.238.08:05:00.71#ibcon#[27=AT01-04\r\n] 2006.238.08:05:00.71#ibcon#*before write, iclass 40, count 2 2006.238.08:05:00.71#ibcon#enter sib2, iclass 40, count 2 2006.238.08:05:00.71#ibcon#flushed, iclass 40, count 2 2006.238.08:05:00.71#ibcon#about to write, iclass 40, count 2 2006.238.08:05:00.71#ibcon#wrote, iclass 40, count 2 2006.238.08:05:00.71#ibcon#about to read 3, iclass 40, count 2 2006.238.08:05:00.74#ibcon#read 3, iclass 40, count 2 2006.238.08:05:00.74#ibcon#about to read 4, iclass 40, count 2 2006.238.08:05:00.74#ibcon#read 4, iclass 40, count 2 2006.238.08:05:00.74#ibcon#about to read 5, iclass 40, count 2 2006.238.08:05:00.74#ibcon#read 5, iclass 40, count 2 2006.238.08:05:00.74#ibcon#about to read 6, iclass 40, count 2 2006.238.08:05:00.74#ibcon#read 6, iclass 40, count 2 2006.238.08:05:00.74#ibcon#end of sib2, iclass 40, count 2 2006.238.08:05:00.74#ibcon#*after write, iclass 40, count 2 2006.238.08:05:00.74#ibcon#*before return 0, iclass 40, count 2 2006.238.08:05:00.74#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:05:00.74#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:05:00.74#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.238.08:05:00.74#ibcon#ireg 7 cls_cnt 0 2006.238.08:05:00.74#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:05:00.86#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:05:00.86#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:05:00.86#ibcon#enter wrdev, iclass 40, count 0 2006.238.08:05:00.86#ibcon#first serial, iclass 40, count 0 2006.238.08:05:00.86#ibcon#enter sib2, iclass 40, count 0 2006.238.08:05:00.86#ibcon#flushed, iclass 40, count 0 2006.238.08:05:00.86#ibcon#about to write, iclass 40, count 0 2006.238.08:05:00.86#ibcon#wrote, iclass 40, count 0 2006.238.08:05:00.86#ibcon#about to read 3, iclass 40, count 0 2006.238.08:05:00.88#ibcon#read 3, iclass 40, count 0 2006.238.08:05:00.88#ibcon#about to read 4, iclass 40, count 0 2006.238.08:05:00.88#ibcon#read 4, iclass 40, count 0 2006.238.08:05:00.88#ibcon#about to read 5, iclass 40, count 0 2006.238.08:05:00.88#ibcon#read 5, iclass 40, count 0 2006.238.08:05:00.88#ibcon#about to read 6, iclass 40, count 0 2006.238.08:05:00.88#ibcon#read 6, iclass 40, count 0 2006.238.08:05:00.88#ibcon#end of sib2, iclass 40, count 0 2006.238.08:05:00.88#ibcon#*mode == 0, iclass 40, count 0 2006.238.08:05:00.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.08:05:00.88#ibcon#[27=USB\r\n] 2006.238.08:05:00.88#ibcon#*before write, iclass 40, count 0 2006.238.08:05:00.88#ibcon#enter sib2, iclass 40, count 0 2006.238.08:05:00.88#ibcon#flushed, iclass 40, count 0 2006.238.08:05:00.88#ibcon#about to write, iclass 40, count 0 2006.238.08:05:00.88#ibcon#wrote, iclass 40, count 0 2006.238.08:05:00.88#ibcon#about to read 3, iclass 40, count 0 2006.238.08:05:00.91#ibcon#read 3, iclass 40, count 0 2006.238.08:05:00.91#ibcon#about to read 4, iclass 40, count 0 2006.238.08:05:00.91#ibcon#read 4, iclass 40, count 0 2006.238.08:05:00.91#ibcon#about to read 5, iclass 40, count 0 2006.238.08:05:00.91#ibcon#read 5, iclass 40, count 0 2006.238.08:05:00.91#ibcon#about to read 6, iclass 40, count 0 2006.238.08:05:00.91#ibcon#read 6, iclass 40, count 0 2006.238.08:05:00.91#ibcon#end of sib2, iclass 40, count 0 2006.238.08:05:00.91#ibcon#*after write, iclass 40, count 0 2006.238.08:05:00.91#ibcon#*before return 0, iclass 40, count 0 2006.238.08:05:00.91#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:05:00.91#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:05:00.91#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.08:05:00.91#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.08:05:00.91$vc4f8/vblo=2,640.99 2006.238.08:05:00.91#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.08:05:00.91#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.08:05:00.91#ibcon#ireg 17 cls_cnt 0 2006.238.08:05:00.91#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:05:00.91#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:05:00.91#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:05:00.91#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:05:00.91#ibcon#first serial, iclass 4, count 0 2006.238.08:05:00.91#ibcon#enter sib2, iclass 4, count 0 2006.238.08:05:00.91#ibcon#flushed, iclass 4, count 0 2006.238.08:05:00.91#ibcon#about to write, iclass 4, count 0 2006.238.08:05:00.91#ibcon#wrote, iclass 4, count 0 2006.238.08:05:00.91#ibcon#about to read 3, iclass 4, count 0 2006.238.08:05:00.93#ibcon#read 3, iclass 4, count 0 2006.238.08:05:00.93#ibcon#about to read 4, iclass 4, count 0 2006.238.08:05:00.93#ibcon#read 4, iclass 4, count 0 2006.238.08:05:00.93#ibcon#about to read 5, iclass 4, count 0 2006.238.08:05:00.93#ibcon#read 5, iclass 4, count 0 2006.238.08:05:00.93#ibcon#about to read 6, iclass 4, count 0 2006.238.08:05:00.93#ibcon#read 6, iclass 4, count 0 2006.238.08:05:00.93#ibcon#end of sib2, iclass 4, count 0 2006.238.08:05:00.93#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:05:00.93#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:05:00.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:05:00.93#ibcon#*before write, iclass 4, count 0 2006.238.08:05:00.93#ibcon#enter sib2, iclass 4, count 0 2006.238.08:05:00.93#ibcon#flushed, iclass 4, count 0 2006.238.08:05:00.93#ibcon#about to write, iclass 4, count 0 2006.238.08:05:00.93#ibcon#wrote, iclass 4, count 0 2006.238.08:05:00.93#ibcon#about to read 3, iclass 4, count 0 2006.238.08:05:00.97#ibcon#read 3, iclass 4, count 0 2006.238.08:05:00.97#ibcon#about to read 4, iclass 4, count 0 2006.238.08:05:00.97#ibcon#read 4, iclass 4, count 0 2006.238.08:05:00.97#ibcon#about to read 5, iclass 4, count 0 2006.238.08:05:00.97#ibcon#read 5, iclass 4, count 0 2006.238.08:05:00.97#ibcon#about to read 6, iclass 4, count 0 2006.238.08:05:00.97#ibcon#read 6, iclass 4, count 0 2006.238.08:05:00.97#ibcon#end of sib2, iclass 4, count 0 2006.238.08:05:00.97#ibcon#*after write, iclass 4, count 0 2006.238.08:05:00.97#ibcon#*before return 0, iclass 4, count 0 2006.238.08:05:00.97#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:05:00.97#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:05:00.97#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:05:00.97#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:05:00.97$vc4f8/vb=2,4 2006.238.08:05:00.97#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.08:05:00.97#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.08:05:00.97#ibcon#ireg 11 cls_cnt 2 2006.238.08:05:00.97#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:05:01.03#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:05:01.03#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:05:01.03#ibcon#enter wrdev, iclass 6, count 2 2006.238.08:05:01.03#ibcon#first serial, iclass 6, count 2 2006.238.08:05:01.03#ibcon#enter sib2, iclass 6, count 2 2006.238.08:05:01.03#ibcon#flushed, iclass 6, count 2 2006.238.08:05:01.03#ibcon#about to write, iclass 6, count 2 2006.238.08:05:01.03#ibcon#wrote, iclass 6, count 2 2006.238.08:05:01.03#ibcon#about to read 3, iclass 6, count 2 2006.238.08:05:01.05#ibcon#read 3, iclass 6, count 2 2006.238.08:05:01.05#ibcon#about to read 4, iclass 6, count 2 2006.238.08:05:01.05#ibcon#read 4, iclass 6, count 2 2006.238.08:05:01.05#ibcon#about to read 5, iclass 6, count 2 2006.238.08:05:01.05#ibcon#read 5, iclass 6, count 2 2006.238.08:05:01.05#ibcon#about to read 6, iclass 6, count 2 2006.238.08:05:01.05#ibcon#read 6, iclass 6, count 2 2006.238.08:05:01.05#ibcon#end of sib2, iclass 6, count 2 2006.238.08:05:01.05#ibcon#*mode == 0, iclass 6, count 2 2006.238.08:05:01.05#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.08:05:01.05#ibcon#[27=AT02-04\r\n] 2006.238.08:05:01.05#ibcon#*before write, iclass 6, count 2 2006.238.08:05:01.05#ibcon#enter sib2, iclass 6, count 2 2006.238.08:05:01.05#ibcon#flushed, iclass 6, count 2 2006.238.08:05:01.05#ibcon#about to write, iclass 6, count 2 2006.238.08:05:01.05#ibcon#wrote, iclass 6, count 2 2006.238.08:05:01.05#ibcon#about to read 3, iclass 6, count 2 2006.238.08:05:01.08#ibcon#read 3, iclass 6, count 2 2006.238.08:05:01.08#ibcon#about to read 4, iclass 6, count 2 2006.238.08:05:01.08#ibcon#read 4, iclass 6, count 2 2006.238.08:05:01.08#ibcon#about to read 5, iclass 6, count 2 2006.238.08:05:01.08#ibcon#read 5, iclass 6, count 2 2006.238.08:05:01.08#ibcon#about to read 6, iclass 6, count 2 2006.238.08:05:01.08#ibcon#read 6, iclass 6, count 2 2006.238.08:05:01.08#ibcon#end of sib2, iclass 6, count 2 2006.238.08:05:01.08#ibcon#*after write, iclass 6, count 2 2006.238.08:05:01.08#ibcon#*before return 0, iclass 6, count 2 2006.238.08:05:01.08#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:05:01.08#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:05:01.08#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.08:05:01.08#ibcon#ireg 7 cls_cnt 0 2006.238.08:05:01.08#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:05:01.20#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:05:01.20#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:05:01.20#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:05:01.20#ibcon#first serial, iclass 6, count 0 2006.238.08:05:01.20#ibcon#enter sib2, iclass 6, count 0 2006.238.08:05:01.20#ibcon#flushed, iclass 6, count 0 2006.238.08:05:01.20#ibcon#about to write, iclass 6, count 0 2006.238.08:05:01.20#ibcon#wrote, iclass 6, count 0 2006.238.08:05:01.20#ibcon#about to read 3, iclass 6, count 0 2006.238.08:05:01.22#ibcon#read 3, iclass 6, count 0 2006.238.08:05:01.22#ibcon#about to read 4, iclass 6, count 0 2006.238.08:05:01.22#ibcon#read 4, iclass 6, count 0 2006.238.08:05:01.22#ibcon#about to read 5, iclass 6, count 0 2006.238.08:05:01.22#ibcon#read 5, iclass 6, count 0 2006.238.08:05:01.22#ibcon#about to read 6, iclass 6, count 0 2006.238.08:05:01.22#ibcon#read 6, iclass 6, count 0 2006.238.08:05:01.22#ibcon#end of sib2, iclass 6, count 0 2006.238.08:05:01.22#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:05:01.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:05:01.22#ibcon#[27=USB\r\n] 2006.238.08:05:01.22#ibcon#*before write, iclass 6, count 0 2006.238.08:05:01.22#ibcon#enter sib2, iclass 6, count 0 2006.238.08:05:01.22#ibcon#flushed, iclass 6, count 0 2006.238.08:05:01.22#ibcon#about to write, iclass 6, count 0 2006.238.08:05:01.22#ibcon#wrote, iclass 6, count 0 2006.238.08:05:01.22#ibcon#about to read 3, iclass 6, count 0 2006.238.08:05:01.25#ibcon#read 3, iclass 6, count 0 2006.238.08:05:01.25#ibcon#about to read 4, iclass 6, count 0 2006.238.08:05:01.25#ibcon#read 4, iclass 6, count 0 2006.238.08:05:01.25#ibcon#about to read 5, iclass 6, count 0 2006.238.08:05:01.25#ibcon#read 5, iclass 6, count 0 2006.238.08:05:01.25#ibcon#about to read 6, iclass 6, count 0 2006.238.08:05:01.25#ibcon#read 6, iclass 6, count 0 2006.238.08:05:01.25#ibcon#end of sib2, iclass 6, count 0 2006.238.08:05:01.25#ibcon#*after write, iclass 6, count 0 2006.238.08:05:01.25#ibcon#*before return 0, iclass 6, count 0 2006.238.08:05:01.25#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:05:01.25#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:05:01.25#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:05:01.25#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:05:01.25$vc4f8/vblo=3,656.99 2006.238.08:05:01.25#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.08:05:01.25#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.08:05:01.25#ibcon#ireg 17 cls_cnt 0 2006.238.08:05:01.25#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:05:01.25#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:05:01.25#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:05:01.25#ibcon#enter wrdev, iclass 10, count 0 2006.238.08:05:01.25#ibcon#first serial, iclass 10, count 0 2006.238.08:05:01.25#ibcon#enter sib2, iclass 10, count 0 2006.238.08:05:01.25#ibcon#flushed, iclass 10, count 0 2006.238.08:05:01.25#ibcon#about to write, iclass 10, count 0 2006.238.08:05:01.25#ibcon#wrote, iclass 10, count 0 2006.238.08:05:01.25#ibcon#about to read 3, iclass 10, count 0 2006.238.08:05:01.27#ibcon#read 3, iclass 10, count 0 2006.238.08:05:01.27#ibcon#about to read 4, iclass 10, count 0 2006.238.08:05:01.27#ibcon#read 4, iclass 10, count 0 2006.238.08:05:01.27#ibcon#about to read 5, iclass 10, count 0 2006.238.08:05:01.27#ibcon#read 5, iclass 10, count 0 2006.238.08:05:01.27#ibcon#about to read 6, iclass 10, count 0 2006.238.08:05:01.27#ibcon#read 6, iclass 10, count 0 2006.238.08:05:01.27#ibcon#end of sib2, iclass 10, count 0 2006.238.08:05:01.27#ibcon#*mode == 0, iclass 10, count 0 2006.238.08:05:01.27#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.08:05:01.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:05:01.27#ibcon#*before write, iclass 10, count 0 2006.238.08:05:01.27#ibcon#enter sib2, iclass 10, count 0 2006.238.08:05:01.27#ibcon#flushed, iclass 10, count 0 2006.238.08:05:01.27#ibcon#about to write, iclass 10, count 0 2006.238.08:05:01.27#ibcon#wrote, iclass 10, count 0 2006.238.08:05:01.27#ibcon#about to read 3, iclass 10, count 0 2006.238.08:05:01.31#ibcon#read 3, iclass 10, count 0 2006.238.08:05:01.31#ibcon#about to read 4, iclass 10, count 0 2006.238.08:05:01.31#ibcon#read 4, iclass 10, count 0 2006.238.08:05:01.31#ibcon#about to read 5, iclass 10, count 0 2006.238.08:05:01.31#ibcon#read 5, iclass 10, count 0 2006.238.08:05:01.31#ibcon#about to read 6, iclass 10, count 0 2006.238.08:05:01.31#ibcon#read 6, iclass 10, count 0 2006.238.08:05:01.31#ibcon#end of sib2, iclass 10, count 0 2006.238.08:05:01.31#ibcon#*after write, iclass 10, count 0 2006.238.08:05:01.31#ibcon#*before return 0, iclass 10, count 0 2006.238.08:05:01.31#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:05:01.31#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:05:01.31#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.08:05:01.31#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.08:05:01.31$vc4f8/vb=3,4 2006.238.08:05:01.31#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.238.08:05:01.31#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.238.08:05:01.31#ibcon#ireg 11 cls_cnt 2 2006.238.08:05:01.31#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:05:01.37#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:05:01.37#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:05:01.37#ibcon#enter wrdev, iclass 12, count 2 2006.238.08:05:01.37#ibcon#first serial, iclass 12, count 2 2006.238.08:05:01.37#ibcon#enter sib2, iclass 12, count 2 2006.238.08:05:01.37#ibcon#flushed, iclass 12, count 2 2006.238.08:05:01.37#ibcon#about to write, iclass 12, count 2 2006.238.08:05:01.37#ibcon#wrote, iclass 12, count 2 2006.238.08:05:01.37#ibcon#about to read 3, iclass 12, count 2 2006.238.08:05:01.39#ibcon#read 3, iclass 12, count 2 2006.238.08:05:01.39#ibcon#about to read 4, iclass 12, count 2 2006.238.08:05:01.39#ibcon#read 4, iclass 12, count 2 2006.238.08:05:01.39#ibcon#about to read 5, iclass 12, count 2 2006.238.08:05:01.39#ibcon#read 5, iclass 12, count 2 2006.238.08:05:01.39#ibcon#about to read 6, iclass 12, count 2 2006.238.08:05:01.39#ibcon#read 6, iclass 12, count 2 2006.238.08:05:01.39#ibcon#end of sib2, iclass 12, count 2 2006.238.08:05:01.39#ibcon#*mode == 0, iclass 12, count 2 2006.238.08:05:01.39#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.238.08:05:01.39#ibcon#[27=AT03-04\r\n] 2006.238.08:05:01.39#ibcon#*before write, iclass 12, count 2 2006.238.08:05:01.39#ibcon#enter sib2, iclass 12, count 2 2006.238.08:05:01.39#ibcon#flushed, iclass 12, count 2 2006.238.08:05:01.39#ibcon#about to write, iclass 12, count 2 2006.238.08:05:01.39#ibcon#wrote, iclass 12, count 2 2006.238.08:05:01.39#ibcon#about to read 3, iclass 12, count 2 2006.238.08:05:01.42#ibcon#read 3, iclass 12, count 2 2006.238.08:05:01.42#ibcon#about to read 4, iclass 12, count 2 2006.238.08:05:01.42#ibcon#read 4, iclass 12, count 2 2006.238.08:05:01.42#ibcon#about to read 5, iclass 12, count 2 2006.238.08:05:01.42#ibcon#read 5, iclass 12, count 2 2006.238.08:05:01.42#ibcon#about to read 6, iclass 12, count 2 2006.238.08:05:01.42#ibcon#read 6, iclass 12, count 2 2006.238.08:05:01.42#ibcon#end of sib2, iclass 12, count 2 2006.238.08:05:01.42#ibcon#*after write, iclass 12, count 2 2006.238.08:05:01.42#ibcon#*before return 0, iclass 12, count 2 2006.238.08:05:01.42#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:05:01.42#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:05:01.42#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.238.08:05:01.42#ibcon#ireg 7 cls_cnt 0 2006.238.08:05:01.42#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:05:01.54#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:05:01.54#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:05:01.54#ibcon#enter wrdev, iclass 12, count 0 2006.238.08:05:01.54#ibcon#first serial, iclass 12, count 0 2006.238.08:05:01.54#ibcon#enter sib2, iclass 12, count 0 2006.238.08:05:01.54#ibcon#flushed, iclass 12, count 0 2006.238.08:05:01.54#ibcon#about to write, iclass 12, count 0 2006.238.08:05:01.54#ibcon#wrote, iclass 12, count 0 2006.238.08:05:01.54#ibcon#about to read 3, iclass 12, count 0 2006.238.08:05:01.56#ibcon#read 3, iclass 12, count 0 2006.238.08:05:01.56#ibcon#about to read 4, iclass 12, count 0 2006.238.08:05:01.56#ibcon#read 4, iclass 12, count 0 2006.238.08:05:01.56#ibcon#about to read 5, iclass 12, count 0 2006.238.08:05:01.56#ibcon#read 5, iclass 12, count 0 2006.238.08:05:01.56#ibcon#about to read 6, iclass 12, count 0 2006.238.08:05:01.56#ibcon#read 6, iclass 12, count 0 2006.238.08:05:01.56#ibcon#end of sib2, iclass 12, count 0 2006.238.08:05:01.56#ibcon#*mode == 0, iclass 12, count 0 2006.238.08:05:01.56#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.08:05:01.56#ibcon#[27=USB\r\n] 2006.238.08:05:01.56#ibcon#*before write, iclass 12, count 0 2006.238.08:05:01.56#ibcon#enter sib2, iclass 12, count 0 2006.238.08:05:01.56#ibcon#flushed, iclass 12, count 0 2006.238.08:05:01.56#ibcon#about to write, iclass 12, count 0 2006.238.08:05:01.56#ibcon#wrote, iclass 12, count 0 2006.238.08:05:01.56#ibcon#about to read 3, iclass 12, count 0 2006.238.08:05:01.59#ibcon#read 3, iclass 12, count 0 2006.238.08:05:01.59#ibcon#about to read 4, iclass 12, count 0 2006.238.08:05:01.59#ibcon#read 4, iclass 12, count 0 2006.238.08:05:01.59#ibcon#about to read 5, iclass 12, count 0 2006.238.08:05:01.59#ibcon#read 5, iclass 12, count 0 2006.238.08:05:01.59#ibcon#about to read 6, iclass 12, count 0 2006.238.08:05:01.59#ibcon#read 6, iclass 12, count 0 2006.238.08:05:01.59#ibcon#end of sib2, iclass 12, count 0 2006.238.08:05:01.59#ibcon#*after write, iclass 12, count 0 2006.238.08:05:01.59#ibcon#*before return 0, iclass 12, count 0 2006.238.08:05:01.59#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:05:01.59#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:05:01.59#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.08:05:01.59#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.08:05:01.59$vc4f8/vblo=4,712.99 2006.238.08:05:01.59#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.08:05:01.59#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.08:05:01.59#ibcon#ireg 17 cls_cnt 0 2006.238.08:05:01.59#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:05:01.59#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:05:01.59#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:05:01.59#ibcon#enter wrdev, iclass 14, count 0 2006.238.08:05:01.59#ibcon#first serial, iclass 14, count 0 2006.238.08:05:01.59#ibcon#enter sib2, iclass 14, count 0 2006.238.08:05:01.59#ibcon#flushed, iclass 14, count 0 2006.238.08:05:01.59#ibcon#about to write, iclass 14, count 0 2006.238.08:05:01.59#ibcon#wrote, iclass 14, count 0 2006.238.08:05:01.59#ibcon#about to read 3, iclass 14, count 0 2006.238.08:05:01.61#ibcon#read 3, iclass 14, count 0 2006.238.08:05:01.61#ibcon#about to read 4, iclass 14, count 0 2006.238.08:05:01.61#ibcon#read 4, iclass 14, count 0 2006.238.08:05:01.61#ibcon#about to read 5, iclass 14, count 0 2006.238.08:05:01.61#ibcon#read 5, iclass 14, count 0 2006.238.08:05:01.61#ibcon#about to read 6, iclass 14, count 0 2006.238.08:05:01.61#ibcon#read 6, iclass 14, count 0 2006.238.08:05:01.61#ibcon#end of sib2, iclass 14, count 0 2006.238.08:05:01.61#ibcon#*mode == 0, iclass 14, count 0 2006.238.08:05:01.61#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.08:05:01.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:05:01.61#ibcon#*before write, iclass 14, count 0 2006.238.08:05:01.61#ibcon#enter sib2, iclass 14, count 0 2006.238.08:05:01.61#ibcon#flushed, iclass 14, count 0 2006.238.08:05:01.61#ibcon#about to write, iclass 14, count 0 2006.238.08:05:01.61#ibcon#wrote, iclass 14, count 0 2006.238.08:05:01.61#ibcon#about to read 3, iclass 14, count 0 2006.238.08:05:01.65#ibcon#read 3, iclass 14, count 0 2006.238.08:05:01.65#ibcon#about to read 4, iclass 14, count 0 2006.238.08:05:01.65#ibcon#read 4, iclass 14, count 0 2006.238.08:05:01.65#ibcon#about to read 5, iclass 14, count 0 2006.238.08:05:01.65#ibcon#read 5, iclass 14, count 0 2006.238.08:05:01.65#ibcon#about to read 6, iclass 14, count 0 2006.238.08:05:01.65#ibcon#read 6, iclass 14, count 0 2006.238.08:05:01.65#ibcon#end of sib2, iclass 14, count 0 2006.238.08:05:01.65#ibcon#*after write, iclass 14, count 0 2006.238.08:05:01.65#ibcon#*before return 0, iclass 14, count 0 2006.238.08:05:01.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:05:01.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:05:01.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.08:05:01.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.08:05:01.65$vc4f8/vb=4,4 2006.238.08:05:01.65#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.238.08:05:01.65#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.238.08:05:01.65#ibcon#ireg 11 cls_cnt 2 2006.238.08:05:01.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:05:01.71#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:05:01.71#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:05:01.71#ibcon#enter wrdev, iclass 16, count 2 2006.238.08:05:01.71#ibcon#first serial, iclass 16, count 2 2006.238.08:05:01.71#ibcon#enter sib2, iclass 16, count 2 2006.238.08:05:01.71#ibcon#flushed, iclass 16, count 2 2006.238.08:05:01.71#ibcon#about to write, iclass 16, count 2 2006.238.08:05:01.71#ibcon#wrote, iclass 16, count 2 2006.238.08:05:01.71#ibcon#about to read 3, iclass 16, count 2 2006.238.08:05:01.73#ibcon#read 3, iclass 16, count 2 2006.238.08:05:01.73#ibcon#about to read 4, iclass 16, count 2 2006.238.08:05:01.73#ibcon#read 4, iclass 16, count 2 2006.238.08:05:01.73#ibcon#about to read 5, iclass 16, count 2 2006.238.08:05:01.73#ibcon#read 5, iclass 16, count 2 2006.238.08:05:01.73#ibcon#about to read 6, iclass 16, count 2 2006.238.08:05:01.73#ibcon#read 6, iclass 16, count 2 2006.238.08:05:01.73#ibcon#end of sib2, iclass 16, count 2 2006.238.08:05:01.73#ibcon#*mode == 0, iclass 16, count 2 2006.238.08:05:01.73#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.238.08:05:01.73#ibcon#[27=AT04-04\r\n] 2006.238.08:05:01.73#ibcon#*before write, iclass 16, count 2 2006.238.08:05:01.73#ibcon#enter sib2, iclass 16, count 2 2006.238.08:05:01.73#ibcon#flushed, iclass 16, count 2 2006.238.08:05:01.73#ibcon#about to write, iclass 16, count 2 2006.238.08:05:01.73#ibcon#wrote, iclass 16, count 2 2006.238.08:05:01.73#ibcon#about to read 3, iclass 16, count 2 2006.238.08:05:01.76#ibcon#read 3, iclass 16, count 2 2006.238.08:05:01.76#ibcon#about to read 4, iclass 16, count 2 2006.238.08:05:01.76#ibcon#read 4, iclass 16, count 2 2006.238.08:05:01.76#ibcon#about to read 5, iclass 16, count 2 2006.238.08:05:01.76#ibcon#read 5, iclass 16, count 2 2006.238.08:05:01.76#ibcon#about to read 6, iclass 16, count 2 2006.238.08:05:01.76#ibcon#read 6, iclass 16, count 2 2006.238.08:05:01.76#ibcon#end of sib2, iclass 16, count 2 2006.238.08:05:01.76#ibcon#*after write, iclass 16, count 2 2006.238.08:05:01.76#ibcon#*before return 0, iclass 16, count 2 2006.238.08:05:01.76#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:05:01.76#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:05:01.76#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.238.08:05:01.76#ibcon#ireg 7 cls_cnt 0 2006.238.08:05:01.76#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:05:01.88#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:05:01.88#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:05:01.88#ibcon#enter wrdev, iclass 16, count 0 2006.238.08:05:01.88#ibcon#first serial, iclass 16, count 0 2006.238.08:05:01.88#ibcon#enter sib2, iclass 16, count 0 2006.238.08:05:01.88#ibcon#flushed, iclass 16, count 0 2006.238.08:05:01.88#ibcon#about to write, iclass 16, count 0 2006.238.08:05:01.88#ibcon#wrote, iclass 16, count 0 2006.238.08:05:01.88#ibcon#about to read 3, iclass 16, count 0 2006.238.08:05:01.90#ibcon#read 3, iclass 16, count 0 2006.238.08:05:01.90#ibcon#about to read 4, iclass 16, count 0 2006.238.08:05:01.90#ibcon#read 4, iclass 16, count 0 2006.238.08:05:01.90#ibcon#about to read 5, iclass 16, count 0 2006.238.08:05:01.90#ibcon#read 5, iclass 16, count 0 2006.238.08:05:01.90#ibcon#about to read 6, iclass 16, count 0 2006.238.08:05:01.90#ibcon#read 6, iclass 16, count 0 2006.238.08:05:01.90#ibcon#end of sib2, iclass 16, count 0 2006.238.08:05:01.90#ibcon#*mode == 0, iclass 16, count 0 2006.238.08:05:01.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.08:05:01.90#ibcon#[27=USB\r\n] 2006.238.08:05:01.90#ibcon#*before write, iclass 16, count 0 2006.238.08:05:01.90#ibcon#enter sib2, iclass 16, count 0 2006.238.08:05:01.90#ibcon#flushed, iclass 16, count 0 2006.238.08:05:01.90#ibcon#about to write, iclass 16, count 0 2006.238.08:05:01.90#ibcon#wrote, iclass 16, count 0 2006.238.08:05:01.90#ibcon#about to read 3, iclass 16, count 0 2006.238.08:05:01.93#ibcon#read 3, iclass 16, count 0 2006.238.08:05:01.93#ibcon#about to read 4, iclass 16, count 0 2006.238.08:05:01.93#ibcon#read 4, iclass 16, count 0 2006.238.08:05:01.93#ibcon#about to read 5, iclass 16, count 0 2006.238.08:05:01.93#ibcon#read 5, iclass 16, count 0 2006.238.08:05:01.93#ibcon#about to read 6, iclass 16, count 0 2006.238.08:05:01.93#ibcon#read 6, iclass 16, count 0 2006.238.08:05:01.93#ibcon#end of sib2, iclass 16, count 0 2006.238.08:05:01.93#ibcon#*after write, iclass 16, count 0 2006.238.08:05:01.93#ibcon#*before return 0, iclass 16, count 0 2006.238.08:05:01.93#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:05:01.93#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:05:01.93#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.08:05:01.93#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.08:05:01.93$vc4f8/vblo=5,744.99 2006.238.08:05:01.93#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.08:05:01.93#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.08:05:01.93#ibcon#ireg 17 cls_cnt 0 2006.238.08:05:01.93#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:05:01.93#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:05:01.93#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:05:01.93#ibcon#enter wrdev, iclass 18, count 0 2006.238.08:05:01.93#ibcon#first serial, iclass 18, count 0 2006.238.08:05:01.93#ibcon#enter sib2, iclass 18, count 0 2006.238.08:05:01.93#ibcon#flushed, iclass 18, count 0 2006.238.08:05:01.93#ibcon#about to write, iclass 18, count 0 2006.238.08:05:01.93#ibcon#wrote, iclass 18, count 0 2006.238.08:05:01.93#ibcon#about to read 3, iclass 18, count 0 2006.238.08:05:01.95#ibcon#read 3, iclass 18, count 0 2006.238.08:05:01.95#ibcon#about to read 4, iclass 18, count 0 2006.238.08:05:01.95#ibcon#read 4, iclass 18, count 0 2006.238.08:05:01.95#ibcon#about to read 5, iclass 18, count 0 2006.238.08:05:01.95#ibcon#read 5, iclass 18, count 0 2006.238.08:05:01.95#ibcon#about to read 6, iclass 18, count 0 2006.238.08:05:01.95#ibcon#read 6, iclass 18, count 0 2006.238.08:05:01.95#ibcon#end of sib2, iclass 18, count 0 2006.238.08:05:01.95#ibcon#*mode == 0, iclass 18, count 0 2006.238.08:05:01.95#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.08:05:01.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:05:01.95#ibcon#*before write, iclass 18, count 0 2006.238.08:05:01.95#ibcon#enter sib2, iclass 18, count 0 2006.238.08:05:01.95#ibcon#flushed, iclass 18, count 0 2006.238.08:05:01.95#ibcon#about to write, iclass 18, count 0 2006.238.08:05:01.95#ibcon#wrote, iclass 18, count 0 2006.238.08:05:01.95#ibcon#about to read 3, iclass 18, count 0 2006.238.08:05:01.99#ibcon#read 3, iclass 18, count 0 2006.238.08:05:01.99#ibcon#about to read 4, iclass 18, count 0 2006.238.08:05:01.99#ibcon#read 4, iclass 18, count 0 2006.238.08:05:01.99#ibcon#about to read 5, iclass 18, count 0 2006.238.08:05:01.99#ibcon#read 5, iclass 18, count 0 2006.238.08:05:01.99#ibcon#about to read 6, iclass 18, count 0 2006.238.08:05:01.99#ibcon#read 6, iclass 18, count 0 2006.238.08:05:01.99#ibcon#end of sib2, iclass 18, count 0 2006.238.08:05:01.99#ibcon#*after write, iclass 18, count 0 2006.238.08:05:01.99#ibcon#*before return 0, iclass 18, count 0 2006.238.08:05:01.99#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:05:01.99#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:05:01.99#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.08:05:01.99#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.08:05:01.99$vc4f8/vb=5,4 2006.238.08:05:01.99#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.238.08:05:01.99#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.238.08:05:01.99#ibcon#ireg 11 cls_cnt 2 2006.238.08:05:01.99#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:05:02.04#abcon#<5=/04 1.9 3.4 25.45 881012.1\r\n> 2006.238.08:05:02.05#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:05:02.05#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:05:02.05#ibcon#enter wrdev, iclass 20, count 2 2006.238.08:05:02.05#ibcon#first serial, iclass 20, count 2 2006.238.08:05:02.05#ibcon#enter sib2, iclass 20, count 2 2006.238.08:05:02.05#ibcon#flushed, iclass 20, count 2 2006.238.08:05:02.05#ibcon#about to write, iclass 20, count 2 2006.238.08:05:02.05#ibcon#wrote, iclass 20, count 2 2006.238.08:05:02.05#ibcon#about to read 3, iclass 20, count 2 2006.238.08:05:02.06#abcon#{5=INTERFACE CLEAR} 2006.238.08:05:02.07#ibcon#read 3, iclass 20, count 2 2006.238.08:05:02.07#ibcon#about to read 4, iclass 20, count 2 2006.238.08:05:02.07#ibcon#read 4, iclass 20, count 2 2006.238.08:05:02.07#ibcon#about to read 5, iclass 20, count 2 2006.238.08:05:02.07#ibcon#read 5, iclass 20, count 2 2006.238.08:05:02.07#ibcon#about to read 6, iclass 20, count 2 2006.238.08:05:02.07#ibcon#read 6, iclass 20, count 2 2006.238.08:05:02.07#ibcon#end of sib2, iclass 20, count 2 2006.238.08:05:02.07#ibcon#*mode == 0, iclass 20, count 2 2006.238.08:05:02.07#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.238.08:05:02.07#ibcon#[27=AT05-04\r\n] 2006.238.08:05:02.07#ibcon#*before write, iclass 20, count 2 2006.238.08:05:02.07#ibcon#enter sib2, iclass 20, count 2 2006.238.08:05:02.07#ibcon#flushed, iclass 20, count 2 2006.238.08:05:02.07#ibcon#about to write, iclass 20, count 2 2006.238.08:05:02.07#ibcon#wrote, iclass 20, count 2 2006.238.08:05:02.07#ibcon#about to read 3, iclass 20, count 2 2006.238.08:05:02.10#ibcon#read 3, iclass 20, count 2 2006.238.08:05:02.10#ibcon#about to read 4, iclass 20, count 2 2006.238.08:05:02.10#ibcon#read 4, iclass 20, count 2 2006.238.08:05:02.10#ibcon#about to read 5, iclass 20, count 2 2006.238.08:05:02.10#ibcon#read 5, iclass 20, count 2 2006.238.08:05:02.10#ibcon#about to read 6, iclass 20, count 2 2006.238.08:05:02.10#ibcon#read 6, iclass 20, count 2 2006.238.08:05:02.10#ibcon#end of sib2, iclass 20, count 2 2006.238.08:05:02.10#ibcon#*after write, iclass 20, count 2 2006.238.08:05:02.10#ibcon#*before return 0, iclass 20, count 2 2006.238.08:05:02.10#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:05:02.10#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:05:02.10#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.238.08:05:02.10#ibcon#ireg 7 cls_cnt 0 2006.238.08:05:02.10#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:05:02.12#abcon#[5=S1D000X0/0*\r\n] 2006.238.08:05:02.22#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:05:02.22#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:05:02.22#ibcon#enter wrdev, iclass 20, count 0 2006.238.08:05:02.22#ibcon#first serial, iclass 20, count 0 2006.238.08:05:02.22#ibcon#enter sib2, iclass 20, count 0 2006.238.08:05:02.22#ibcon#flushed, iclass 20, count 0 2006.238.08:05:02.22#ibcon#about to write, iclass 20, count 0 2006.238.08:05:02.22#ibcon#wrote, iclass 20, count 0 2006.238.08:05:02.22#ibcon#about to read 3, iclass 20, count 0 2006.238.08:05:02.24#ibcon#read 3, iclass 20, count 0 2006.238.08:05:02.24#ibcon#about to read 4, iclass 20, count 0 2006.238.08:05:02.24#ibcon#read 4, iclass 20, count 0 2006.238.08:05:02.24#ibcon#about to read 5, iclass 20, count 0 2006.238.08:05:02.24#ibcon#read 5, iclass 20, count 0 2006.238.08:05:02.24#ibcon#about to read 6, iclass 20, count 0 2006.238.08:05:02.24#ibcon#read 6, iclass 20, count 0 2006.238.08:05:02.24#ibcon#end of sib2, iclass 20, count 0 2006.238.08:05:02.24#ibcon#*mode == 0, iclass 20, count 0 2006.238.08:05:02.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.08:05:02.24#ibcon#[27=USB\r\n] 2006.238.08:05:02.24#ibcon#*before write, iclass 20, count 0 2006.238.08:05:02.24#ibcon#enter sib2, iclass 20, count 0 2006.238.08:05:02.24#ibcon#flushed, iclass 20, count 0 2006.238.08:05:02.24#ibcon#about to write, iclass 20, count 0 2006.238.08:05:02.24#ibcon#wrote, iclass 20, count 0 2006.238.08:05:02.24#ibcon#about to read 3, iclass 20, count 0 2006.238.08:05:02.27#ibcon#read 3, iclass 20, count 0 2006.238.08:05:02.27#ibcon#about to read 4, iclass 20, count 0 2006.238.08:05:02.27#ibcon#read 4, iclass 20, count 0 2006.238.08:05:02.27#ibcon#about to read 5, iclass 20, count 0 2006.238.08:05:02.27#ibcon#read 5, iclass 20, count 0 2006.238.08:05:02.27#ibcon#about to read 6, iclass 20, count 0 2006.238.08:05:02.27#ibcon#read 6, iclass 20, count 0 2006.238.08:05:02.27#ibcon#end of sib2, iclass 20, count 0 2006.238.08:05:02.27#ibcon#*after write, iclass 20, count 0 2006.238.08:05:02.27#ibcon#*before return 0, iclass 20, count 0 2006.238.08:05:02.27#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:05:02.27#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:05:02.27#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.08:05:02.27#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.08:05:02.27$vc4f8/vblo=6,752.99 2006.238.08:05:02.27#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.08:05:02.27#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.08:05:02.27#ibcon#ireg 17 cls_cnt 0 2006.238.08:05:02.27#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:05:02.27#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:05:02.27#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:05:02.27#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:05:02.27#ibcon#first serial, iclass 26, count 0 2006.238.08:05:02.27#ibcon#enter sib2, iclass 26, count 0 2006.238.08:05:02.27#ibcon#flushed, iclass 26, count 0 2006.238.08:05:02.27#ibcon#about to write, iclass 26, count 0 2006.238.08:05:02.27#ibcon#wrote, iclass 26, count 0 2006.238.08:05:02.27#ibcon#about to read 3, iclass 26, count 0 2006.238.08:05:02.29#ibcon#read 3, iclass 26, count 0 2006.238.08:05:02.29#ibcon#about to read 4, iclass 26, count 0 2006.238.08:05:02.29#ibcon#read 4, iclass 26, count 0 2006.238.08:05:02.29#ibcon#about to read 5, iclass 26, count 0 2006.238.08:05:02.29#ibcon#read 5, iclass 26, count 0 2006.238.08:05:02.29#ibcon#about to read 6, iclass 26, count 0 2006.238.08:05:02.29#ibcon#read 6, iclass 26, count 0 2006.238.08:05:02.29#ibcon#end of sib2, iclass 26, count 0 2006.238.08:05:02.29#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:05:02.29#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:05:02.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:05:02.29#ibcon#*before write, iclass 26, count 0 2006.238.08:05:02.29#ibcon#enter sib2, iclass 26, count 0 2006.238.08:05:02.29#ibcon#flushed, iclass 26, count 0 2006.238.08:05:02.29#ibcon#about to write, iclass 26, count 0 2006.238.08:05:02.29#ibcon#wrote, iclass 26, count 0 2006.238.08:05:02.29#ibcon#about to read 3, iclass 26, count 0 2006.238.08:05:02.33#ibcon#read 3, iclass 26, count 0 2006.238.08:05:02.33#ibcon#about to read 4, iclass 26, count 0 2006.238.08:05:02.33#ibcon#read 4, iclass 26, count 0 2006.238.08:05:02.33#ibcon#about to read 5, iclass 26, count 0 2006.238.08:05:02.33#ibcon#read 5, iclass 26, count 0 2006.238.08:05:02.33#ibcon#about to read 6, iclass 26, count 0 2006.238.08:05:02.33#ibcon#read 6, iclass 26, count 0 2006.238.08:05:02.33#ibcon#end of sib2, iclass 26, count 0 2006.238.08:05:02.33#ibcon#*after write, iclass 26, count 0 2006.238.08:05:02.33#ibcon#*before return 0, iclass 26, count 0 2006.238.08:05:02.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:05:02.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:05:02.33#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:05:02.33#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:05:02.33$vc4f8/vb=6,4 2006.238.08:05:02.33#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.08:05:02.33#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.08:05:02.33#ibcon#ireg 11 cls_cnt 2 2006.238.08:05:02.33#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:05:02.39#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:05:02.39#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:05:02.39#ibcon#enter wrdev, iclass 28, count 2 2006.238.08:05:02.39#ibcon#first serial, iclass 28, count 2 2006.238.08:05:02.39#ibcon#enter sib2, iclass 28, count 2 2006.238.08:05:02.39#ibcon#flushed, iclass 28, count 2 2006.238.08:05:02.39#ibcon#about to write, iclass 28, count 2 2006.238.08:05:02.39#ibcon#wrote, iclass 28, count 2 2006.238.08:05:02.39#ibcon#about to read 3, iclass 28, count 2 2006.238.08:05:02.41#ibcon#read 3, iclass 28, count 2 2006.238.08:05:02.41#ibcon#about to read 4, iclass 28, count 2 2006.238.08:05:02.41#ibcon#read 4, iclass 28, count 2 2006.238.08:05:02.41#ibcon#about to read 5, iclass 28, count 2 2006.238.08:05:02.41#ibcon#read 5, iclass 28, count 2 2006.238.08:05:02.41#ibcon#about to read 6, iclass 28, count 2 2006.238.08:05:02.41#ibcon#read 6, iclass 28, count 2 2006.238.08:05:02.41#ibcon#end of sib2, iclass 28, count 2 2006.238.08:05:02.41#ibcon#*mode == 0, iclass 28, count 2 2006.238.08:05:02.41#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.08:05:02.41#ibcon#[27=AT06-04\r\n] 2006.238.08:05:02.41#ibcon#*before write, iclass 28, count 2 2006.238.08:05:02.41#ibcon#enter sib2, iclass 28, count 2 2006.238.08:05:02.41#ibcon#flushed, iclass 28, count 2 2006.238.08:05:02.41#ibcon#about to write, iclass 28, count 2 2006.238.08:05:02.41#ibcon#wrote, iclass 28, count 2 2006.238.08:05:02.41#ibcon#about to read 3, iclass 28, count 2 2006.238.08:05:02.44#ibcon#read 3, iclass 28, count 2 2006.238.08:05:02.44#ibcon#about to read 4, iclass 28, count 2 2006.238.08:05:02.44#ibcon#read 4, iclass 28, count 2 2006.238.08:05:02.44#ibcon#about to read 5, iclass 28, count 2 2006.238.08:05:02.44#ibcon#read 5, iclass 28, count 2 2006.238.08:05:02.44#ibcon#about to read 6, iclass 28, count 2 2006.238.08:05:02.44#ibcon#read 6, iclass 28, count 2 2006.238.08:05:02.44#ibcon#end of sib2, iclass 28, count 2 2006.238.08:05:02.44#ibcon#*after write, iclass 28, count 2 2006.238.08:05:02.44#ibcon#*before return 0, iclass 28, count 2 2006.238.08:05:02.44#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:05:02.44#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:05:02.44#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.08:05:02.44#ibcon#ireg 7 cls_cnt 0 2006.238.08:05:02.44#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:05:02.56#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:05:02.56#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:05:02.56#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:05:02.56#ibcon#first serial, iclass 28, count 0 2006.238.08:05:02.56#ibcon#enter sib2, iclass 28, count 0 2006.238.08:05:02.56#ibcon#flushed, iclass 28, count 0 2006.238.08:05:02.56#ibcon#about to write, iclass 28, count 0 2006.238.08:05:02.56#ibcon#wrote, iclass 28, count 0 2006.238.08:05:02.56#ibcon#about to read 3, iclass 28, count 0 2006.238.08:05:02.58#ibcon#read 3, iclass 28, count 0 2006.238.08:05:02.58#ibcon#about to read 4, iclass 28, count 0 2006.238.08:05:02.58#ibcon#read 4, iclass 28, count 0 2006.238.08:05:02.58#ibcon#about to read 5, iclass 28, count 0 2006.238.08:05:02.58#ibcon#read 5, iclass 28, count 0 2006.238.08:05:02.58#ibcon#about to read 6, iclass 28, count 0 2006.238.08:05:02.58#ibcon#read 6, iclass 28, count 0 2006.238.08:05:02.58#ibcon#end of sib2, iclass 28, count 0 2006.238.08:05:02.58#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:05:02.58#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:05:02.58#ibcon#[27=USB\r\n] 2006.238.08:05:02.58#ibcon#*before write, iclass 28, count 0 2006.238.08:05:02.58#ibcon#enter sib2, iclass 28, count 0 2006.238.08:05:02.58#ibcon#flushed, iclass 28, count 0 2006.238.08:05:02.58#ibcon#about to write, iclass 28, count 0 2006.238.08:05:02.58#ibcon#wrote, iclass 28, count 0 2006.238.08:05:02.58#ibcon#about to read 3, iclass 28, count 0 2006.238.08:05:02.61#ibcon#read 3, iclass 28, count 0 2006.238.08:05:02.61#ibcon#about to read 4, iclass 28, count 0 2006.238.08:05:02.61#ibcon#read 4, iclass 28, count 0 2006.238.08:05:02.61#ibcon#about to read 5, iclass 28, count 0 2006.238.08:05:02.61#ibcon#read 5, iclass 28, count 0 2006.238.08:05:02.61#ibcon#about to read 6, iclass 28, count 0 2006.238.08:05:02.61#ibcon#read 6, iclass 28, count 0 2006.238.08:05:02.61#ibcon#end of sib2, iclass 28, count 0 2006.238.08:05:02.61#ibcon#*after write, iclass 28, count 0 2006.238.08:05:02.61#ibcon#*before return 0, iclass 28, count 0 2006.238.08:05:02.61#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:05:02.61#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:05:02.61#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:05:02.61#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:05:02.61$vc4f8/vabw=wide 2006.238.08:05:02.61#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.08:05:02.61#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.08:05:02.61#ibcon#ireg 8 cls_cnt 0 2006.238.08:05:02.61#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:05:02.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:05:02.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:05:02.61#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:05:02.61#ibcon#first serial, iclass 30, count 0 2006.238.08:05:02.61#ibcon#enter sib2, iclass 30, count 0 2006.238.08:05:02.61#ibcon#flushed, iclass 30, count 0 2006.238.08:05:02.61#ibcon#about to write, iclass 30, count 0 2006.238.08:05:02.61#ibcon#wrote, iclass 30, count 0 2006.238.08:05:02.61#ibcon#about to read 3, iclass 30, count 0 2006.238.08:05:02.63#ibcon#read 3, iclass 30, count 0 2006.238.08:05:02.63#ibcon#about to read 4, iclass 30, count 0 2006.238.08:05:02.63#ibcon#read 4, iclass 30, count 0 2006.238.08:05:02.63#ibcon#about to read 5, iclass 30, count 0 2006.238.08:05:02.63#ibcon#read 5, iclass 30, count 0 2006.238.08:05:02.63#ibcon#about to read 6, iclass 30, count 0 2006.238.08:05:02.63#ibcon#read 6, iclass 30, count 0 2006.238.08:05:02.63#ibcon#end of sib2, iclass 30, count 0 2006.238.08:05:02.63#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:05:02.63#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:05:02.63#ibcon#[25=BW32\r\n] 2006.238.08:05:02.63#ibcon#*before write, iclass 30, count 0 2006.238.08:05:02.63#ibcon#enter sib2, iclass 30, count 0 2006.238.08:05:02.63#ibcon#flushed, iclass 30, count 0 2006.238.08:05:02.63#ibcon#about to write, iclass 30, count 0 2006.238.08:05:02.63#ibcon#wrote, iclass 30, count 0 2006.238.08:05:02.63#ibcon#about to read 3, iclass 30, count 0 2006.238.08:05:02.66#ibcon#read 3, iclass 30, count 0 2006.238.08:05:02.66#ibcon#about to read 4, iclass 30, count 0 2006.238.08:05:02.66#ibcon#read 4, iclass 30, count 0 2006.238.08:05:02.66#ibcon#about to read 5, iclass 30, count 0 2006.238.08:05:02.66#ibcon#read 5, iclass 30, count 0 2006.238.08:05:02.66#ibcon#about to read 6, iclass 30, count 0 2006.238.08:05:02.66#ibcon#read 6, iclass 30, count 0 2006.238.08:05:02.66#ibcon#end of sib2, iclass 30, count 0 2006.238.08:05:02.66#ibcon#*after write, iclass 30, count 0 2006.238.08:05:02.66#ibcon#*before return 0, iclass 30, count 0 2006.238.08:05:02.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:05:02.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:05:02.66#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:05:02.66#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:05:02.66$vc4f8/vbbw=wide 2006.238.08:05:02.66#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.08:05:02.66#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.08:05:02.66#ibcon#ireg 8 cls_cnt 0 2006.238.08:05:02.66#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:05:02.73#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:05:02.73#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:05:02.73#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:05:02.73#ibcon#first serial, iclass 32, count 0 2006.238.08:05:02.73#ibcon#enter sib2, iclass 32, count 0 2006.238.08:05:02.73#ibcon#flushed, iclass 32, count 0 2006.238.08:05:02.73#ibcon#about to write, iclass 32, count 0 2006.238.08:05:02.73#ibcon#wrote, iclass 32, count 0 2006.238.08:05:02.73#ibcon#about to read 3, iclass 32, count 0 2006.238.08:05:02.75#ibcon#read 3, iclass 32, count 0 2006.238.08:05:02.75#ibcon#about to read 4, iclass 32, count 0 2006.238.08:05:02.75#ibcon#read 4, iclass 32, count 0 2006.238.08:05:02.75#ibcon#about to read 5, iclass 32, count 0 2006.238.08:05:02.75#ibcon#read 5, iclass 32, count 0 2006.238.08:05:02.75#ibcon#about to read 6, iclass 32, count 0 2006.238.08:05:02.75#ibcon#read 6, iclass 32, count 0 2006.238.08:05:02.75#ibcon#end of sib2, iclass 32, count 0 2006.238.08:05:02.75#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:05:02.75#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:05:02.75#ibcon#[27=BW32\r\n] 2006.238.08:05:02.75#ibcon#*before write, iclass 32, count 0 2006.238.08:05:02.75#ibcon#enter sib2, iclass 32, count 0 2006.238.08:05:02.75#ibcon#flushed, iclass 32, count 0 2006.238.08:05:02.75#ibcon#about to write, iclass 32, count 0 2006.238.08:05:02.75#ibcon#wrote, iclass 32, count 0 2006.238.08:05:02.75#ibcon#about to read 3, iclass 32, count 0 2006.238.08:05:02.78#ibcon#read 3, iclass 32, count 0 2006.238.08:05:02.78#ibcon#about to read 4, iclass 32, count 0 2006.238.08:05:02.78#ibcon#read 4, iclass 32, count 0 2006.238.08:05:02.78#ibcon#about to read 5, iclass 32, count 0 2006.238.08:05:02.78#ibcon#read 5, iclass 32, count 0 2006.238.08:05:02.78#ibcon#about to read 6, iclass 32, count 0 2006.238.08:05:02.78#ibcon#read 6, iclass 32, count 0 2006.238.08:05:02.78#ibcon#end of sib2, iclass 32, count 0 2006.238.08:05:02.78#ibcon#*after write, iclass 32, count 0 2006.238.08:05:02.78#ibcon#*before return 0, iclass 32, count 0 2006.238.08:05:02.78#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:05:02.78#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:05:02.78#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:05:02.78#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:05:02.78$4f8m12a/ifd4f 2006.238.08:05:02.78$ifd4f/lo= 2006.238.08:05:02.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:05:02.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:05:02.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:05:02.78$ifd4f/patch= 2006.238.08:05:02.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:05:02.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:05:02.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:05:02.78$4f8m12a/"form=m,16.000,1:2 2006.238.08:05:02.78$4f8m12a/"tpicd 2006.238.08:05:02.78$4f8m12a/echo=off 2006.238.08:05:02.78$4f8m12a/xlog=off 2006.238.08:05:02.78:!2006.238.08:05:30 2006.238.08:05:12.14#trakl#Source acquired 2006.238.08:05:14.14#flagr#flagr/antenna,acquired 2006.238.08:05:30.00:preob 2006.238.08:05:30.14/onsource/TRACKING 2006.238.08:05:30.14:!2006.238.08:05:40 2006.238.08:05:40.00:data_valid=on 2006.238.08:05:40.00:midob 2006.238.08:05:41.14/onsource/TRACKING 2006.238.08:05:41.14/wx/25.45,1012.2,89 2006.238.08:05:41.21/cable/+6.4167E-03 2006.238.08:05:42.30/va/01,08,usb,yes,32,34 2006.238.08:05:42.30/va/02,07,usb,yes,32,34 2006.238.08:05:42.30/va/03,07,usb,yes,30,30 2006.238.08:05:42.30/va/04,07,usb,yes,33,36 2006.238.08:05:42.30/va/05,08,usb,yes,30,32 2006.238.08:05:42.30/va/06,07,usb,yes,33,33 2006.238.08:05:42.30/va/07,07,usb,yes,33,33 2006.238.08:05:42.30/va/08,07,usb,yes,36,35 2006.238.08:05:42.53/valo/01,532.99,yes,locked 2006.238.08:05:42.53/valo/02,572.99,yes,locked 2006.238.08:05:42.53/valo/03,672.99,yes,locked 2006.238.08:05:42.53/valo/04,832.99,yes,locked 2006.238.08:05:42.53/valo/05,652.99,yes,locked 2006.238.08:05:42.53/valo/06,772.99,yes,locked 2006.238.08:05:42.53/valo/07,832.99,yes,locked 2006.238.08:05:42.53/valo/08,852.99,yes,locked 2006.238.08:05:43.62/vb/01,04,usb,yes,30,29 2006.238.08:05:43.62/vb/02,04,usb,yes,32,34 2006.238.08:05:43.62/vb/03,04,usb,yes,29,32 2006.238.08:05:43.62/vb/04,04,usb,yes,29,30 2006.238.08:05:43.62/vb/05,04,usb,yes,28,32 2006.238.08:05:43.62/vb/06,04,usb,yes,29,32 2006.238.08:05:43.62/vb/07,04,usb,yes,31,31 2006.238.08:05:43.62/vb/08,04,usb,yes,29,32 2006.238.08:05:43.85/vblo/01,632.99,yes,locked 2006.238.08:05:43.85/vblo/02,640.99,yes,locked 2006.238.08:05:43.85/vblo/03,656.99,yes,locked 2006.238.08:05:43.85/vblo/04,712.99,yes,locked 2006.238.08:05:43.85/vblo/05,744.99,yes,locked 2006.238.08:05:43.85/vblo/06,752.99,yes,locked 2006.238.08:05:43.85/vblo/07,734.99,yes,locked 2006.238.08:05:43.85/vblo/08,744.99,yes,locked 2006.238.08:05:44.00/vabw/8 2006.238.08:05:44.15/vbbw/8 2006.238.08:05:44.24/xfe/off,on,13.5 2006.238.08:05:44.61/ifatt/23,28,28,28 2006.238.08:05:45.08/fmout-gps/S +4.32E-07 2006.238.08:05:45.12:!2006.238.08:06:40 2006.238.08:06:40.01:data_valid=off 2006.238.08:06:40.02:postob 2006.238.08:06:40.13/cable/+6.4198E-03 2006.238.08:06:40.14/wx/25.46,1012.2,88 2006.238.08:06:40.22/fmout-gps/S +4.33E-07 2006.238.08:06:40.22:scan_name=238-0807,k06238,60 2006.238.08:06:40.23:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.238.08:06:41.14#flagr#flagr/antenna,new-source 2006.238.08:06:41.15:checkk5 2006.238.08:06:41.53/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:06:41.91/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:06:42.28/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:06:42.66/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:06:43.03/chk_obsdata//k5ts1/T2380805??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:06:43.41/chk_obsdata//k5ts2/T2380805??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:06:43.77/chk_obsdata//k5ts3/T2380805??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:06:44.15/chk_obsdata//k5ts4/T2380805??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:06:44.84/k5log//k5ts1_log_newline 2006.238.08:06:45.54/k5log//k5ts2_log_newline 2006.238.08:06:46.22/k5log//k5ts3_log_newline 2006.238.08:06:46.91/k5log//k5ts4_log_newline 2006.238.08:06:46.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:06:46.94:4f8m12a=2 2006.238.08:06:46.94$4f8m12a/echo=on 2006.238.08:06:46.94$4f8m12a/pcalon 2006.238.08:06:46.94$pcalon/"no phase cal control is implemented here 2006.238.08:06:46.94$4f8m12a/"tpicd=stop 2006.238.08:06:46.94$4f8m12a/vc4f8 2006.238.08:06:46.94$vc4f8/valo=1,532.99 2006.238.08:06:46.94#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.08:06:46.94#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.08:06:46.94#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:46.94#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:06:46.94#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:06:46.94#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:06:46.94#ibcon#enter wrdev, iclass 39, count 0 2006.238.08:06:46.94#ibcon#first serial, iclass 39, count 0 2006.238.08:06:46.94#ibcon#enter sib2, iclass 39, count 0 2006.238.08:06:46.94#ibcon#flushed, iclass 39, count 0 2006.238.08:06:46.94#ibcon#about to write, iclass 39, count 0 2006.238.08:06:46.94#ibcon#wrote, iclass 39, count 0 2006.238.08:06:46.94#ibcon#about to read 3, iclass 39, count 0 2006.238.08:06:46.98#ibcon#read 3, iclass 39, count 0 2006.238.08:06:46.98#ibcon#about to read 4, iclass 39, count 0 2006.238.08:06:46.99#ibcon#read 4, iclass 39, count 0 2006.238.08:06:46.99#ibcon#about to read 5, iclass 39, count 0 2006.238.08:06:46.99#ibcon#read 5, iclass 39, count 0 2006.238.08:06:46.99#ibcon#about to read 6, iclass 39, count 0 2006.238.08:06:46.99#ibcon#read 6, iclass 39, count 0 2006.238.08:06:46.99#ibcon#end of sib2, iclass 39, count 0 2006.238.08:06:46.99#ibcon#*mode == 0, iclass 39, count 0 2006.238.08:06:46.99#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.08:06:46.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:06:46.99#ibcon#*before write, iclass 39, count 0 2006.238.08:06:46.99#ibcon#enter sib2, iclass 39, count 0 2006.238.08:06:46.99#ibcon#flushed, iclass 39, count 0 2006.238.08:06:46.99#ibcon#about to write, iclass 39, count 0 2006.238.08:06:46.99#ibcon#wrote, iclass 39, count 0 2006.238.08:06:46.99#ibcon#about to read 3, iclass 39, count 0 2006.238.08:06:47.03#ibcon#read 3, iclass 39, count 0 2006.238.08:06:47.03#ibcon#about to read 4, iclass 39, count 0 2006.238.08:06:47.03#ibcon#read 4, iclass 39, count 0 2006.238.08:06:47.03#ibcon#about to read 5, iclass 39, count 0 2006.238.08:06:47.03#ibcon#read 5, iclass 39, count 0 2006.238.08:06:47.03#ibcon#about to read 6, iclass 39, count 0 2006.238.08:06:47.03#ibcon#read 6, iclass 39, count 0 2006.238.08:06:47.03#ibcon#end of sib2, iclass 39, count 0 2006.238.08:06:47.03#ibcon#*after write, iclass 39, count 0 2006.238.08:06:47.03#ibcon#*before return 0, iclass 39, count 0 2006.238.08:06:47.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:06:47.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:06:47.03#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.08:06:47.03#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.08:06:47.03$vc4f8/va=1,8 2006.238.08:06:47.03#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.08:06:47.03#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.08:06:47.03#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:47.03#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:06:47.03#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:06:47.03#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:06:47.03#ibcon#enter wrdev, iclass 3, count 2 2006.238.08:06:47.03#ibcon#first serial, iclass 3, count 2 2006.238.08:06:47.03#ibcon#enter sib2, iclass 3, count 2 2006.238.08:06:47.03#ibcon#flushed, iclass 3, count 2 2006.238.08:06:47.03#ibcon#about to write, iclass 3, count 2 2006.238.08:06:47.03#ibcon#wrote, iclass 3, count 2 2006.238.08:06:47.03#ibcon#about to read 3, iclass 3, count 2 2006.238.08:06:47.06#ibcon#read 3, iclass 3, count 2 2006.238.08:06:47.06#ibcon#about to read 4, iclass 3, count 2 2006.238.08:06:47.06#ibcon#read 4, iclass 3, count 2 2006.238.08:06:47.06#ibcon#about to read 5, iclass 3, count 2 2006.238.08:06:47.06#ibcon#read 5, iclass 3, count 2 2006.238.08:06:47.06#ibcon#about to read 6, iclass 3, count 2 2006.238.08:06:47.06#ibcon#read 6, iclass 3, count 2 2006.238.08:06:47.06#ibcon#end of sib2, iclass 3, count 2 2006.238.08:06:47.06#ibcon#*mode == 0, iclass 3, count 2 2006.238.08:06:47.06#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.08:06:47.06#ibcon#[25=AT01-08\r\n] 2006.238.08:06:47.06#ibcon#*before write, iclass 3, count 2 2006.238.08:06:47.06#ibcon#enter sib2, iclass 3, count 2 2006.238.08:06:47.06#ibcon#flushed, iclass 3, count 2 2006.238.08:06:47.06#ibcon#about to write, iclass 3, count 2 2006.238.08:06:47.06#ibcon#wrote, iclass 3, count 2 2006.238.08:06:47.06#ibcon#about to read 3, iclass 3, count 2 2006.238.08:06:47.09#ibcon#read 3, iclass 3, count 2 2006.238.08:06:47.09#ibcon#about to read 4, iclass 3, count 2 2006.238.08:06:47.09#ibcon#read 4, iclass 3, count 2 2006.238.08:06:47.09#ibcon#about to read 5, iclass 3, count 2 2006.238.08:06:47.09#ibcon#read 5, iclass 3, count 2 2006.238.08:06:47.09#ibcon#about to read 6, iclass 3, count 2 2006.238.08:06:47.09#ibcon#read 6, iclass 3, count 2 2006.238.08:06:47.09#ibcon#end of sib2, iclass 3, count 2 2006.238.08:06:47.09#ibcon#*after write, iclass 3, count 2 2006.238.08:06:47.09#ibcon#*before return 0, iclass 3, count 2 2006.238.08:06:47.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:06:47.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:06:47.09#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.08:06:47.09#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:47.09#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:06:47.21#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:06:47.21#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:06:47.21#ibcon#enter wrdev, iclass 3, count 0 2006.238.08:06:47.21#ibcon#first serial, iclass 3, count 0 2006.238.08:06:47.21#ibcon#enter sib2, iclass 3, count 0 2006.238.08:06:47.21#ibcon#flushed, iclass 3, count 0 2006.238.08:06:47.21#ibcon#about to write, iclass 3, count 0 2006.238.08:06:47.21#ibcon#wrote, iclass 3, count 0 2006.238.08:06:47.21#ibcon#about to read 3, iclass 3, count 0 2006.238.08:06:47.23#ibcon#read 3, iclass 3, count 0 2006.238.08:06:47.23#ibcon#about to read 4, iclass 3, count 0 2006.238.08:06:47.23#ibcon#read 4, iclass 3, count 0 2006.238.08:06:47.23#ibcon#about to read 5, iclass 3, count 0 2006.238.08:06:47.23#ibcon#read 5, iclass 3, count 0 2006.238.08:06:47.23#ibcon#about to read 6, iclass 3, count 0 2006.238.08:06:47.23#ibcon#read 6, iclass 3, count 0 2006.238.08:06:47.23#ibcon#end of sib2, iclass 3, count 0 2006.238.08:06:47.23#ibcon#*mode == 0, iclass 3, count 0 2006.238.08:06:47.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.08:06:47.23#ibcon#[25=USB\r\n] 2006.238.08:06:47.23#ibcon#*before write, iclass 3, count 0 2006.238.08:06:47.23#ibcon#enter sib2, iclass 3, count 0 2006.238.08:06:47.23#ibcon#flushed, iclass 3, count 0 2006.238.08:06:47.23#ibcon#about to write, iclass 3, count 0 2006.238.08:06:47.23#ibcon#wrote, iclass 3, count 0 2006.238.08:06:47.23#ibcon#about to read 3, iclass 3, count 0 2006.238.08:06:47.26#ibcon#read 3, iclass 3, count 0 2006.238.08:06:47.26#ibcon#about to read 4, iclass 3, count 0 2006.238.08:06:47.26#ibcon#read 4, iclass 3, count 0 2006.238.08:06:47.26#ibcon#about to read 5, iclass 3, count 0 2006.238.08:06:47.26#ibcon#read 5, iclass 3, count 0 2006.238.08:06:47.26#ibcon#about to read 6, iclass 3, count 0 2006.238.08:06:47.26#ibcon#read 6, iclass 3, count 0 2006.238.08:06:47.26#ibcon#end of sib2, iclass 3, count 0 2006.238.08:06:47.26#ibcon#*after write, iclass 3, count 0 2006.238.08:06:47.26#ibcon#*before return 0, iclass 3, count 0 2006.238.08:06:47.26#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:06:47.26#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:06:47.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.08:06:47.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.08:06:47.26$vc4f8/valo=2,572.99 2006.238.08:06:47.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.08:06:47.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.08:06:47.26#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:47.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:06:47.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:06:47.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:06:47.26#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:06:47.26#ibcon#first serial, iclass 5, count 0 2006.238.08:06:47.26#ibcon#enter sib2, iclass 5, count 0 2006.238.08:06:47.26#ibcon#flushed, iclass 5, count 0 2006.238.08:06:47.26#ibcon#about to write, iclass 5, count 0 2006.238.08:06:47.26#ibcon#wrote, iclass 5, count 0 2006.238.08:06:47.26#ibcon#about to read 3, iclass 5, count 0 2006.238.08:06:47.28#ibcon#read 3, iclass 5, count 0 2006.238.08:06:47.28#ibcon#about to read 4, iclass 5, count 0 2006.238.08:06:47.28#ibcon#read 4, iclass 5, count 0 2006.238.08:06:47.28#ibcon#about to read 5, iclass 5, count 0 2006.238.08:06:47.28#ibcon#read 5, iclass 5, count 0 2006.238.08:06:47.28#ibcon#about to read 6, iclass 5, count 0 2006.238.08:06:47.28#ibcon#read 6, iclass 5, count 0 2006.238.08:06:47.28#ibcon#end of sib2, iclass 5, count 0 2006.238.08:06:47.28#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:06:47.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:06:47.28#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:06:47.28#ibcon#*before write, iclass 5, count 0 2006.238.08:06:47.28#ibcon#enter sib2, iclass 5, count 0 2006.238.08:06:47.28#ibcon#flushed, iclass 5, count 0 2006.238.08:06:47.28#ibcon#about to write, iclass 5, count 0 2006.238.08:06:47.28#ibcon#wrote, iclass 5, count 0 2006.238.08:06:47.28#ibcon#about to read 3, iclass 5, count 0 2006.238.08:06:47.32#ibcon#read 3, iclass 5, count 0 2006.238.08:06:47.32#ibcon#about to read 4, iclass 5, count 0 2006.238.08:06:47.32#ibcon#read 4, iclass 5, count 0 2006.238.08:06:47.32#ibcon#about to read 5, iclass 5, count 0 2006.238.08:06:47.32#ibcon#read 5, iclass 5, count 0 2006.238.08:06:47.32#ibcon#about to read 6, iclass 5, count 0 2006.238.08:06:47.32#ibcon#read 6, iclass 5, count 0 2006.238.08:06:47.32#ibcon#end of sib2, iclass 5, count 0 2006.238.08:06:47.32#ibcon#*after write, iclass 5, count 0 2006.238.08:06:47.32#ibcon#*before return 0, iclass 5, count 0 2006.238.08:06:47.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:06:47.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:06:47.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:06:47.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:06:47.32$vc4f8/va=2,7 2006.238.08:06:47.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.08:06:47.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.08:06:47.32#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:47.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:06:47.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:06:47.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:06:47.38#ibcon#enter wrdev, iclass 7, count 2 2006.238.08:06:47.38#ibcon#first serial, iclass 7, count 2 2006.238.08:06:47.38#ibcon#enter sib2, iclass 7, count 2 2006.238.08:06:47.38#ibcon#flushed, iclass 7, count 2 2006.238.08:06:47.38#ibcon#about to write, iclass 7, count 2 2006.238.08:06:47.38#ibcon#wrote, iclass 7, count 2 2006.238.08:06:47.38#ibcon#about to read 3, iclass 7, count 2 2006.238.08:06:47.40#ibcon#read 3, iclass 7, count 2 2006.238.08:06:47.40#ibcon#about to read 4, iclass 7, count 2 2006.238.08:06:47.40#ibcon#read 4, iclass 7, count 2 2006.238.08:06:47.40#ibcon#about to read 5, iclass 7, count 2 2006.238.08:06:47.40#ibcon#read 5, iclass 7, count 2 2006.238.08:06:47.40#ibcon#about to read 6, iclass 7, count 2 2006.238.08:06:47.40#ibcon#read 6, iclass 7, count 2 2006.238.08:06:47.40#ibcon#end of sib2, iclass 7, count 2 2006.238.08:06:47.40#ibcon#*mode == 0, iclass 7, count 2 2006.238.08:06:47.40#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.08:06:47.40#ibcon#[25=AT02-07\r\n] 2006.238.08:06:47.40#ibcon#*before write, iclass 7, count 2 2006.238.08:06:47.40#ibcon#enter sib2, iclass 7, count 2 2006.238.08:06:47.40#ibcon#flushed, iclass 7, count 2 2006.238.08:06:47.40#ibcon#about to write, iclass 7, count 2 2006.238.08:06:47.40#ibcon#wrote, iclass 7, count 2 2006.238.08:06:47.40#ibcon#about to read 3, iclass 7, count 2 2006.238.08:06:47.43#ibcon#read 3, iclass 7, count 2 2006.238.08:06:47.43#ibcon#about to read 4, iclass 7, count 2 2006.238.08:06:47.43#ibcon#read 4, iclass 7, count 2 2006.238.08:06:47.43#ibcon#about to read 5, iclass 7, count 2 2006.238.08:06:47.43#ibcon#read 5, iclass 7, count 2 2006.238.08:06:47.43#ibcon#about to read 6, iclass 7, count 2 2006.238.08:06:47.43#ibcon#read 6, iclass 7, count 2 2006.238.08:06:47.43#ibcon#end of sib2, iclass 7, count 2 2006.238.08:06:47.43#ibcon#*after write, iclass 7, count 2 2006.238.08:06:47.43#ibcon#*before return 0, iclass 7, count 2 2006.238.08:06:47.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:06:47.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:06:47.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.08:06:47.43#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:47.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:06:47.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:06:47.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:06:47.55#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:06:47.55#ibcon#first serial, iclass 7, count 0 2006.238.08:06:47.55#ibcon#enter sib2, iclass 7, count 0 2006.238.08:06:47.55#ibcon#flushed, iclass 7, count 0 2006.238.08:06:47.55#ibcon#about to write, iclass 7, count 0 2006.238.08:06:47.55#ibcon#wrote, iclass 7, count 0 2006.238.08:06:47.55#ibcon#about to read 3, iclass 7, count 0 2006.238.08:06:47.57#ibcon#read 3, iclass 7, count 0 2006.238.08:06:47.57#ibcon#about to read 4, iclass 7, count 0 2006.238.08:06:47.57#ibcon#read 4, iclass 7, count 0 2006.238.08:06:47.57#ibcon#about to read 5, iclass 7, count 0 2006.238.08:06:47.57#ibcon#read 5, iclass 7, count 0 2006.238.08:06:47.57#ibcon#about to read 6, iclass 7, count 0 2006.238.08:06:47.57#ibcon#read 6, iclass 7, count 0 2006.238.08:06:47.57#ibcon#end of sib2, iclass 7, count 0 2006.238.08:06:47.57#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:06:47.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:06:47.57#ibcon#[25=USB\r\n] 2006.238.08:06:47.57#ibcon#*before write, iclass 7, count 0 2006.238.08:06:47.57#ibcon#enter sib2, iclass 7, count 0 2006.238.08:06:47.57#ibcon#flushed, iclass 7, count 0 2006.238.08:06:47.57#ibcon#about to write, iclass 7, count 0 2006.238.08:06:47.57#ibcon#wrote, iclass 7, count 0 2006.238.08:06:47.57#ibcon#about to read 3, iclass 7, count 0 2006.238.08:06:47.60#ibcon#read 3, iclass 7, count 0 2006.238.08:06:47.60#ibcon#about to read 4, iclass 7, count 0 2006.238.08:06:47.60#ibcon#read 4, iclass 7, count 0 2006.238.08:06:47.60#ibcon#about to read 5, iclass 7, count 0 2006.238.08:06:47.60#ibcon#read 5, iclass 7, count 0 2006.238.08:06:47.60#ibcon#about to read 6, iclass 7, count 0 2006.238.08:06:47.60#ibcon#read 6, iclass 7, count 0 2006.238.08:06:47.60#ibcon#end of sib2, iclass 7, count 0 2006.238.08:06:47.60#ibcon#*after write, iclass 7, count 0 2006.238.08:06:47.60#ibcon#*before return 0, iclass 7, count 0 2006.238.08:06:47.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:06:47.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:06:47.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:06:47.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:06:47.60$vc4f8/valo=3,672.99 2006.238.08:06:47.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.08:06:47.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.08:06:47.60#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:47.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:06:47.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:06:47.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:06:47.60#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:06:47.60#ibcon#first serial, iclass 11, count 0 2006.238.08:06:47.60#ibcon#enter sib2, iclass 11, count 0 2006.238.08:06:47.60#ibcon#flushed, iclass 11, count 0 2006.238.08:06:47.60#ibcon#about to write, iclass 11, count 0 2006.238.08:06:47.60#ibcon#wrote, iclass 11, count 0 2006.238.08:06:47.60#ibcon#about to read 3, iclass 11, count 0 2006.238.08:06:47.62#ibcon#read 3, iclass 11, count 0 2006.238.08:06:47.62#ibcon#about to read 4, iclass 11, count 0 2006.238.08:06:47.62#ibcon#read 4, iclass 11, count 0 2006.238.08:06:47.62#ibcon#about to read 5, iclass 11, count 0 2006.238.08:06:47.62#ibcon#read 5, iclass 11, count 0 2006.238.08:06:47.62#ibcon#about to read 6, iclass 11, count 0 2006.238.08:06:47.62#ibcon#read 6, iclass 11, count 0 2006.238.08:06:47.62#ibcon#end of sib2, iclass 11, count 0 2006.238.08:06:47.62#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:06:47.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:06:47.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:06:47.62#ibcon#*before write, iclass 11, count 0 2006.238.08:06:47.62#ibcon#enter sib2, iclass 11, count 0 2006.238.08:06:47.62#ibcon#flushed, iclass 11, count 0 2006.238.08:06:47.62#ibcon#about to write, iclass 11, count 0 2006.238.08:06:47.62#ibcon#wrote, iclass 11, count 0 2006.238.08:06:47.62#ibcon#about to read 3, iclass 11, count 0 2006.238.08:06:47.66#ibcon#read 3, iclass 11, count 0 2006.238.08:06:47.66#ibcon#about to read 4, iclass 11, count 0 2006.238.08:06:47.66#ibcon#read 4, iclass 11, count 0 2006.238.08:06:47.66#ibcon#about to read 5, iclass 11, count 0 2006.238.08:06:47.66#ibcon#read 5, iclass 11, count 0 2006.238.08:06:47.66#ibcon#about to read 6, iclass 11, count 0 2006.238.08:06:47.66#ibcon#read 6, iclass 11, count 0 2006.238.08:06:47.66#ibcon#end of sib2, iclass 11, count 0 2006.238.08:06:47.66#ibcon#*after write, iclass 11, count 0 2006.238.08:06:47.66#ibcon#*before return 0, iclass 11, count 0 2006.238.08:06:47.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:06:47.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:06:47.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:06:47.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:06:47.66$vc4f8/va=3,7 2006.238.08:06:47.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.08:06:47.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.08:06:47.66#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:47.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:06:47.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:06:47.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:06:47.72#ibcon#enter wrdev, iclass 13, count 2 2006.238.08:06:47.72#ibcon#first serial, iclass 13, count 2 2006.238.08:06:47.72#ibcon#enter sib2, iclass 13, count 2 2006.238.08:06:47.72#ibcon#flushed, iclass 13, count 2 2006.238.08:06:47.72#ibcon#about to write, iclass 13, count 2 2006.238.08:06:47.72#ibcon#wrote, iclass 13, count 2 2006.238.08:06:47.72#ibcon#about to read 3, iclass 13, count 2 2006.238.08:06:47.74#ibcon#read 3, iclass 13, count 2 2006.238.08:06:47.74#ibcon#about to read 4, iclass 13, count 2 2006.238.08:06:47.74#ibcon#read 4, iclass 13, count 2 2006.238.08:06:47.74#ibcon#about to read 5, iclass 13, count 2 2006.238.08:06:47.74#ibcon#read 5, iclass 13, count 2 2006.238.08:06:47.74#ibcon#about to read 6, iclass 13, count 2 2006.238.08:06:47.74#ibcon#read 6, iclass 13, count 2 2006.238.08:06:47.74#ibcon#end of sib2, iclass 13, count 2 2006.238.08:06:47.74#ibcon#*mode == 0, iclass 13, count 2 2006.238.08:06:47.74#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.08:06:47.74#ibcon#[25=AT03-07\r\n] 2006.238.08:06:47.74#ibcon#*before write, iclass 13, count 2 2006.238.08:06:47.74#ibcon#enter sib2, iclass 13, count 2 2006.238.08:06:47.74#ibcon#flushed, iclass 13, count 2 2006.238.08:06:47.74#ibcon#about to write, iclass 13, count 2 2006.238.08:06:47.74#ibcon#wrote, iclass 13, count 2 2006.238.08:06:47.74#ibcon#about to read 3, iclass 13, count 2 2006.238.08:06:47.77#ibcon#read 3, iclass 13, count 2 2006.238.08:06:47.77#ibcon#about to read 4, iclass 13, count 2 2006.238.08:06:47.77#ibcon#read 4, iclass 13, count 2 2006.238.08:06:47.77#ibcon#about to read 5, iclass 13, count 2 2006.238.08:06:47.77#ibcon#read 5, iclass 13, count 2 2006.238.08:06:47.77#ibcon#about to read 6, iclass 13, count 2 2006.238.08:06:47.77#ibcon#read 6, iclass 13, count 2 2006.238.08:06:47.77#ibcon#end of sib2, iclass 13, count 2 2006.238.08:06:47.77#ibcon#*after write, iclass 13, count 2 2006.238.08:06:47.77#ibcon#*before return 0, iclass 13, count 2 2006.238.08:06:47.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:06:47.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:06:47.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.08:06:47.77#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:47.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:06:47.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:06:47.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:06:47.89#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:06:47.89#ibcon#first serial, iclass 13, count 0 2006.238.08:06:47.89#ibcon#enter sib2, iclass 13, count 0 2006.238.08:06:47.89#ibcon#flushed, iclass 13, count 0 2006.238.08:06:47.89#ibcon#about to write, iclass 13, count 0 2006.238.08:06:47.89#ibcon#wrote, iclass 13, count 0 2006.238.08:06:47.89#ibcon#about to read 3, iclass 13, count 0 2006.238.08:06:47.91#ibcon#read 3, iclass 13, count 0 2006.238.08:06:47.91#ibcon#about to read 4, iclass 13, count 0 2006.238.08:06:47.91#ibcon#read 4, iclass 13, count 0 2006.238.08:06:47.91#ibcon#about to read 5, iclass 13, count 0 2006.238.08:06:47.91#ibcon#read 5, iclass 13, count 0 2006.238.08:06:47.91#ibcon#about to read 6, iclass 13, count 0 2006.238.08:06:47.91#ibcon#read 6, iclass 13, count 0 2006.238.08:06:47.91#ibcon#end of sib2, iclass 13, count 0 2006.238.08:06:47.91#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:06:47.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:06:47.91#ibcon#[25=USB\r\n] 2006.238.08:06:47.91#ibcon#*before write, iclass 13, count 0 2006.238.08:06:47.91#ibcon#enter sib2, iclass 13, count 0 2006.238.08:06:47.91#ibcon#flushed, iclass 13, count 0 2006.238.08:06:47.91#ibcon#about to write, iclass 13, count 0 2006.238.08:06:47.91#ibcon#wrote, iclass 13, count 0 2006.238.08:06:47.91#ibcon#about to read 3, iclass 13, count 0 2006.238.08:06:47.94#ibcon#read 3, iclass 13, count 0 2006.238.08:06:47.94#ibcon#about to read 4, iclass 13, count 0 2006.238.08:06:47.94#ibcon#read 4, iclass 13, count 0 2006.238.08:06:47.94#ibcon#about to read 5, iclass 13, count 0 2006.238.08:06:47.94#ibcon#read 5, iclass 13, count 0 2006.238.08:06:47.94#ibcon#about to read 6, iclass 13, count 0 2006.238.08:06:47.94#ibcon#read 6, iclass 13, count 0 2006.238.08:06:47.94#ibcon#end of sib2, iclass 13, count 0 2006.238.08:06:47.94#ibcon#*after write, iclass 13, count 0 2006.238.08:06:47.94#ibcon#*before return 0, iclass 13, count 0 2006.238.08:06:47.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:06:47.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:06:47.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:06:47.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:06:47.94$vc4f8/valo=4,832.99 2006.238.08:06:47.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.08:06:47.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.08:06:47.94#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:47.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:06:47.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:06:47.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:06:47.94#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:06:47.94#ibcon#first serial, iclass 15, count 0 2006.238.08:06:47.94#ibcon#enter sib2, iclass 15, count 0 2006.238.08:06:47.94#ibcon#flushed, iclass 15, count 0 2006.238.08:06:47.94#ibcon#about to write, iclass 15, count 0 2006.238.08:06:47.94#ibcon#wrote, iclass 15, count 0 2006.238.08:06:47.94#ibcon#about to read 3, iclass 15, count 0 2006.238.08:06:47.96#ibcon#read 3, iclass 15, count 0 2006.238.08:06:47.96#ibcon#about to read 4, iclass 15, count 0 2006.238.08:06:47.96#ibcon#read 4, iclass 15, count 0 2006.238.08:06:47.96#ibcon#about to read 5, iclass 15, count 0 2006.238.08:06:47.96#ibcon#read 5, iclass 15, count 0 2006.238.08:06:47.96#ibcon#about to read 6, iclass 15, count 0 2006.238.08:06:47.96#ibcon#read 6, iclass 15, count 0 2006.238.08:06:47.96#ibcon#end of sib2, iclass 15, count 0 2006.238.08:06:47.96#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:06:47.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:06:47.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:06:47.96#ibcon#*before write, iclass 15, count 0 2006.238.08:06:47.96#ibcon#enter sib2, iclass 15, count 0 2006.238.08:06:47.96#ibcon#flushed, iclass 15, count 0 2006.238.08:06:47.96#ibcon#about to write, iclass 15, count 0 2006.238.08:06:47.96#ibcon#wrote, iclass 15, count 0 2006.238.08:06:47.96#ibcon#about to read 3, iclass 15, count 0 2006.238.08:06:48.00#ibcon#read 3, iclass 15, count 0 2006.238.08:06:48.00#ibcon#about to read 4, iclass 15, count 0 2006.238.08:06:48.00#ibcon#read 4, iclass 15, count 0 2006.238.08:06:48.00#ibcon#about to read 5, iclass 15, count 0 2006.238.08:06:48.00#ibcon#read 5, iclass 15, count 0 2006.238.08:06:48.00#ibcon#about to read 6, iclass 15, count 0 2006.238.08:06:48.00#ibcon#read 6, iclass 15, count 0 2006.238.08:06:48.00#ibcon#end of sib2, iclass 15, count 0 2006.238.08:06:48.00#ibcon#*after write, iclass 15, count 0 2006.238.08:06:48.00#ibcon#*before return 0, iclass 15, count 0 2006.238.08:06:48.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:06:48.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:06:48.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:06:48.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:06:48.00$vc4f8/va=4,7 2006.238.08:06:48.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.08:06:48.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.08:06:48.00#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:48.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:06:48.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:06:48.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:06:48.06#ibcon#enter wrdev, iclass 17, count 2 2006.238.08:06:48.06#ibcon#first serial, iclass 17, count 2 2006.238.08:06:48.06#ibcon#enter sib2, iclass 17, count 2 2006.238.08:06:48.06#ibcon#flushed, iclass 17, count 2 2006.238.08:06:48.06#ibcon#about to write, iclass 17, count 2 2006.238.08:06:48.06#ibcon#wrote, iclass 17, count 2 2006.238.08:06:48.06#ibcon#about to read 3, iclass 17, count 2 2006.238.08:06:48.08#ibcon#read 3, iclass 17, count 2 2006.238.08:06:48.08#ibcon#about to read 4, iclass 17, count 2 2006.238.08:06:48.08#ibcon#read 4, iclass 17, count 2 2006.238.08:06:48.08#ibcon#about to read 5, iclass 17, count 2 2006.238.08:06:48.08#ibcon#read 5, iclass 17, count 2 2006.238.08:06:48.08#ibcon#about to read 6, iclass 17, count 2 2006.238.08:06:48.08#ibcon#read 6, iclass 17, count 2 2006.238.08:06:48.08#ibcon#end of sib2, iclass 17, count 2 2006.238.08:06:48.08#ibcon#*mode == 0, iclass 17, count 2 2006.238.08:06:48.08#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.08:06:48.08#ibcon#[25=AT04-07\r\n] 2006.238.08:06:48.08#ibcon#*before write, iclass 17, count 2 2006.238.08:06:48.08#ibcon#enter sib2, iclass 17, count 2 2006.238.08:06:48.08#ibcon#flushed, iclass 17, count 2 2006.238.08:06:48.08#ibcon#about to write, iclass 17, count 2 2006.238.08:06:48.08#ibcon#wrote, iclass 17, count 2 2006.238.08:06:48.08#ibcon#about to read 3, iclass 17, count 2 2006.238.08:06:48.11#ibcon#read 3, iclass 17, count 2 2006.238.08:06:48.11#ibcon#about to read 4, iclass 17, count 2 2006.238.08:06:48.11#ibcon#read 4, iclass 17, count 2 2006.238.08:06:48.11#ibcon#about to read 5, iclass 17, count 2 2006.238.08:06:48.11#ibcon#read 5, iclass 17, count 2 2006.238.08:06:48.11#ibcon#about to read 6, iclass 17, count 2 2006.238.08:06:48.11#ibcon#read 6, iclass 17, count 2 2006.238.08:06:48.11#ibcon#end of sib2, iclass 17, count 2 2006.238.08:06:48.11#ibcon#*after write, iclass 17, count 2 2006.238.08:06:48.11#ibcon#*before return 0, iclass 17, count 2 2006.238.08:06:48.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:06:48.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:06:48.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.08:06:48.11#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:48.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:06:48.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:06:48.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:06:48.23#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:06:48.23#ibcon#first serial, iclass 17, count 0 2006.238.08:06:48.23#ibcon#enter sib2, iclass 17, count 0 2006.238.08:06:48.23#ibcon#flushed, iclass 17, count 0 2006.238.08:06:48.23#ibcon#about to write, iclass 17, count 0 2006.238.08:06:48.23#ibcon#wrote, iclass 17, count 0 2006.238.08:06:48.23#ibcon#about to read 3, iclass 17, count 0 2006.238.08:06:48.25#ibcon#read 3, iclass 17, count 0 2006.238.08:06:48.25#ibcon#about to read 4, iclass 17, count 0 2006.238.08:06:48.25#ibcon#read 4, iclass 17, count 0 2006.238.08:06:48.25#ibcon#about to read 5, iclass 17, count 0 2006.238.08:06:48.25#ibcon#read 5, iclass 17, count 0 2006.238.08:06:48.25#ibcon#about to read 6, iclass 17, count 0 2006.238.08:06:48.25#ibcon#read 6, iclass 17, count 0 2006.238.08:06:48.25#ibcon#end of sib2, iclass 17, count 0 2006.238.08:06:48.25#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:06:48.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:06:48.25#ibcon#[25=USB\r\n] 2006.238.08:06:48.25#ibcon#*before write, iclass 17, count 0 2006.238.08:06:48.25#ibcon#enter sib2, iclass 17, count 0 2006.238.08:06:48.25#ibcon#flushed, iclass 17, count 0 2006.238.08:06:48.25#ibcon#about to write, iclass 17, count 0 2006.238.08:06:48.25#ibcon#wrote, iclass 17, count 0 2006.238.08:06:48.25#ibcon#about to read 3, iclass 17, count 0 2006.238.08:06:48.28#ibcon#read 3, iclass 17, count 0 2006.238.08:06:48.28#ibcon#about to read 4, iclass 17, count 0 2006.238.08:06:48.28#ibcon#read 4, iclass 17, count 0 2006.238.08:06:48.28#ibcon#about to read 5, iclass 17, count 0 2006.238.08:06:48.28#ibcon#read 5, iclass 17, count 0 2006.238.08:06:48.28#ibcon#about to read 6, iclass 17, count 0 2006.238.08:06:48.28#ibcon#read 6, iclass 17, count 0 2006.238.08:06:48.28#ibcon#end of sib2, iclass 17, count 0 2006.238.08:06:48.28#ibcon#*after write, iclass 17, count 0 2006.238.08:06:48.28#ibcon#*before return 0, iclass 17, count 0 2006.238.08:06:48.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:06:48.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:06:48.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:06:48.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:06:48.28$vc4f8/valo=5,652.99 2006.238.08:06:48.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.08:06:48.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.08:06:48.28#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:48.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:06:48.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:06:48.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:06:48.28#ibcon#enter wrdev, iclass 19, count 0 2006.238.08:06:48.28#ibcon#first serial, iclass 19, count 0 2006.238.08:06:48.28#ibcon#enter sib2, iclass 19, count 0 2006.238.08:06:48.28#ibcon#flushed, iclass 19, count 0 2006.238.08:06:48.28#ibcon#about to write, iclass 19, count 0 2006.238.08:06:48.28#ibcon#wrote, iclass 19, count 0 2006.238.08:06:48.28#ibcon#about to read 3, iclass 19, count 0 2006.238.08:06:48.30#ibcon#read 3, iclass 19, count 0 2006.238.08:06:48.30#ibcon#about to read 4, iclass 19, count 0 2006.238.08:06:48.30#ibcon#read 4, iclass 19, count 0 2006.238.08:06:48.30#ibcon#about to read 5, iclass 19, count 0 2006.238.08:06:48.30#ibcon#read 5, iclass 19, count 0 2006.238.08:06:48.30#ibcon#about to read 6, iclass 19, count 0 2006.238.08:06:48.30#ibcon#read 6, iclass 19, count 0 2006.238.08:06:48.30#ibcon#end of sib2, iclass 19, count 0 2006.238.08:06:48.30#ibcon#*mode == 0, iclass 19, count 0 2006.238.08:06:48.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.08:06:48.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:06:48.30#ibcon#*before write, iclass 19, count 0 2006.238.08:06:48.30#ibcon#enter sib2, iclass 19, count 0 2006.238.08:06:48.30#ibcon#flushed, iclass 19, count 0 2006.238.08:06:48.30#ibcon#about to write, iclass 19, count 0 2006.238.08:06:48.30#ibcon#wrote, iclass 19, count 0 2006.238.08:06:48.30#ibcon#about to read 3, iclass 19, count 0 2006.238.08:06:48.34#ibcon#read 3, iclass 19, count 0 2006.238.08:06:48.34#ibcon#about to read 4, iclass 19, count 0 2006.238.08:06:48.34#ibcon#read 4, iclass 19, count 0 2006.238.08:06:48.34#ibcon#about to read 5, iclass 19, count 0 2006.238.08:06:48.34#ibcon#read 5, iclass 19, count 0 2006.238.08:06:48.34#ibcon#about to read 6, iclass 19, count 0 2006.238.08:06:48.34#ibcon#read 6, iclass 19, count 0 2006.238.08:06:48.34#ibcon#end of sib2, iclass 19, count 0 2006.238.08:06:48.34#ibcon#*after write, iclass 19, count 0 2006.238.08:06:48.34#ibcon#*before return 0, iclass 19, count 0 2006.238.08:06:48.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:06:48.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:06:48.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.08:06:48.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.08:06:48.34$vc4f8/va=5,8 2006.238.08:06:48.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.08:06:48.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.08:06:48.34#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:48.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:06:48.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:06:48.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:06:48.40#ibcon#enter wrdev, iclass 21, count 2 2006.238.08:06:48.40#ibcon#first serial, iclass 21, count 2 2006.238.08:06:48.40#ibcon#enter sib2, iclass 21, count 2 2006.238.08:06:48.40#ibcon#flushed, iclass 21, count 2 2006.238.08:06:48.40#ibcon#about to write, iclass 21, count 2 2006.238.08:06:48.40#ibcon#wrote, iclass 21, count 2 2006.238.08:06:48.40#ibcon#about to read 3, iclass 21, count 2 2006.238.08:06:48.42#ibcon#read 3, iclass 21, count 2 2006.238.08:06:48.42#ibcon#about to read 4, iclass 21, count 2 2006.238.08:06:48.42#ibcon#read 4, iclass 21, count 2 2006.238.08:06:48.42#ibcon#about to read 5, iclass 21, count 2 2006.238.08:06:48.42#ibcon#read 5, iclass 21, count 2 2006.238.08:06:48.42#ibcon#about to read 6, iclass 21, count 2 2006.238.08:06:48.42#ibcon#read 6, iclass 21, count 2 2006.238.08:06:48.42#ibcon#end of sib2, iclass 21, count 2 2006.238.08:06:48.42#ibcon#*mode == 0, iclass 21, count 2 2006.238.08:06:48.42#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.08:06:48.42#ibcon#[25=AT05-08\r\n] 2006.238.08:06:48.42#ibcon#*before write, iclass 21, count 2 2006.238.08:06:48.42#ibcon#enter sib2, iclass 21, count 2 2006.238.08:06:48.42#ibcon#flushed, iclass 21, count 2 2006.238.08:06:48.42#ibcon#about to write, iclass 21, count 2 2006.238.08:06:48.42#ibcon#wrote, iclass 21, count 2 2006.238.08:06:48.42#ibcon#about to read 3, iclass 21, count 2 2006.238.08:06:48.45#ibcon#read 3, iclass 21, count 2 2006.238.08:06:48.45#ibcon#about to read 4, iclass 21, count 2 2006.238.08:06:48.45#ibcon#read 4, iclass 21, count 2 2006.238.08:06:48.45#ibcon#about to read 5, iclass 21, count 2 2006.238.08:06:48.45#ibcon#read 5, iclass 21, count 2 2006.238.08:06:48.45#ibcon#about to read 6, iclass 21, count 2 2006.238.08:06:48.45#ibcon#read 6, iclass 21, count 2 2006.238.08:06:48.45#ibcon#end of sib2, iclass 21, count 2 2006.238.08:06:48.45#ibcon#*after write, iclass 21, count 2 2006.238.08:06:48.45#ibcon#*before return 0, iclass 21, count 2 2006.238.08:06:48.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:06:48.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:06:48.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.08:06:48.45#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:48.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:06:48.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:06:48.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:06:48.57#ibcon#enter wrdev, iclass 21, count 0 2006.238.08:06:48.57#ibcon#first serial, iclass 21, count 0 2006.238.08:06:48.57#ibcon#enter sib2, iclass 21, count 0 2006.238.08:06:48.57#ibcon#flushed, iclass 21, count 0 2006.238.08:06:48.57#ibcon#about to write, iclass 21, count 0 2006.238.08:06:48.57#ibcon#wrote, iclass 21, count 0 2006.238.08:06:48.57#ibcon#about to read 3, iclass 21, count 0 2006.238.08:06:48.59#ibcon#read 3, iclass 21, count 0 2006.238.08:06:48.59#ibcon#about to read 4, iclass 21, count 0 2006.238.08:06:48.59#ibcon#read 4, iclass 21, count 0 2006.238.08:06:48.59#ibcon#about to read 5, iclass 21, count 0 2006.238.08:06:48.59#ibcon#read 5, iclass 21, count 0 2006.238.08:06:48.59#ibcon#about to read 6, iclass 21, count 0 2006.238.08:06:48.59#ibcon#read 6, iclass 21, count 0 2006.238.08:06:48.59#ibcon#end of sib2, iclass 21, count 0 2006.238.08:06:48.59#ibcon#*mode == 0, iclass 21, count 0 2006.238.08:06:48.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.08:06:48.59#ibcon#[25=USB\r\n] 2006.238.08:06:48.59#ibcon#*before write, iclass 21, count 0 2006.238.08:06:48.59#ibcon#enter sib2, iclass 21, count 0 2006.238.08:06:48.59#ibcon#flushed, iclass 21, count 0 2006.238.08:06:48.59#ibcon#about to write, iclass 21, count 0 2006.238.08:06:48.59#ibcon#wrote, iclass 21, count 0 2006.238.08:06:48.59#ibcon#about to read 3, iclass 21, count 0 2006.238.08:06:48.62#ibcon#read 3, iclass 21, count 0 2006.238.08:06:48.62#ibcon#about to read 4, iclass 21, count 0 2006.238.08:06:48.62#ibcon#read 4, iclass 21, count 0 2006.238.08:06:48.62#ibcon#about to read 5, iclass 21, count 0 2006.238.08:06:48.62#ibcon#read 5, iclass 21, count 0 2006.238.08:06:48.62#ibcon#about to read 6, iclass 21, count 0 2006.238.08:06:48.62#ibcon#read 6, iclass 21, count 0 2006.238.08:06:48.62#ibcon#end of sib2, iclass 21, count 0 2006.238.08:06:48.62#ibcon#*after write, iclass 21, count 0 2006.238.08:06:48.62#ibcon#*before return 0, iclass 21, count 0 2006.238.08:06:48.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:06:48.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:06:48.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.08:06:48.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.08:06:48.62$vc4f8/valo=6,772.99 2006.238.08:06:48.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.08:06:48.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.08:06:48.62#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:48.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:06:48.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:06:48.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:06:48.62#ibcon#enter wrdev, iclass 23, count 0 2006.238.08:06:48.62#ibcon#first serial, iclass 23, count 0 2006.238.08:06:48.62#ibcon#enter sib2, iclass 23, count 0 2006.238.08:06:48.62#ibcon#flushed, iclass 23, count 0 2006.238.08:06:48.62#ibcon#about to write, iclass 23, count 0 2006.238.08:06:48.62#ibcon#wrote, iclass 23, count 0 2006.238.08:06:48.62#ibcon#about to read 3, iclass 23, count 0 2006.238.08:06:48.64#ibcon#read 3, iclass 23, count 0 2006.238.08:06:48.64#ibcon#about to read 4, iclass 23, count 0 2006.238.08:06:48.64#ibcon#read 4, iclass 23, count 0 2006.238.08:06:48.64#ibcon#about to read 5, iclass 23, count 0 2006.238.08:06:48.64#ibcon#read 5, iclass 23, count 0 2006.238.08:06:48.64#ibcon#about to read 6, iclass 23, count 0 2006.238.08:06:48.64#ibcon#read 6, iclass 23, count 0 2006.238.08:06:48.64#ibcon#end of sib2, iclass 23, count 0 2006.238.08:06:48.64#ibcon#*mode == 0, iclass 23, count 0 2006.238.08:06:48.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.08:06:48.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:06:48.64#ibcon#*before write, iclass 23, count 0 2006.238.08:06:48.64#ibcon#enter sib2, iclass 23, count 0 2006.238.08:06:48.64#ibcon#flushed, iclass 23, count 0 2006.238.08:06:48.64#ibcon#about to write, iclass 23, count 0 2006.238.08:06:48.64#ibcon#wrote, iclass 23, count 0 2006.238.08:06:48.64#ibcon#about to read 3, iclass 23, count 0 2006.238.08:06:48.68#ibcon#read 3, iclass 23, count 0 2006.238.08:06:48.68#ibcon#about to read 4, iclass 23, count 0 2006.238.08:06:48.68#ibcon#read 4, iclass 23, count 0 2006.238.08:06:48.68#ibcon#about to read 5, iclass 23, count 0 2006.238.08:06:48.68#ibcon#read 5, iclass 23, count 0 2006.238.08:06:48.68#ibcon#about to read 6, iclass 23, count 0 2006.238.08:06:48.68#ibcon#read 6, iclass 23, count 0 2006.238.08:06:48.68#ibcon#end of sib2, iclass 23, count 0 2006.238.08:06:48.68#ibcon#*after write, iclass 23, count 0 2006.238.08:06:48.68#ibcon#*before return 0, iclass 23, count 0 2006.238.08:06:48.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:06:48.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:06:48.68#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.08:06:48.68#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.08:06:48.68$vc4f8/va=6,7 2006.238.08:06:48.68#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.08:06:48.68#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.08:06:48.68#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:48.68#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:06:48.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:06:48.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:06:48.74#ibcon#enter wrdev, iclass 25, count 2 2006.238.08:06:48.74#ibcon#first serial, iclass 25, count 2 2006.238.08:06:48.74#ibcon#enter sib2, iclass 25, count 2 2006.238.08:06:48.74#ibcon#flushed, iclass 25, count 2 2006.238.08:06:48.74#ibcon#about to write, iclass 25, count 2 2006.238.08:06:48.74#ibcon#wrote, iclass 25, count 2 2006.238.08:06:48.74#ibcon#about to read 3, iclass 25, count 2 2006.238.08:06:48.76#ibcon#read 3, iclass 25, count 2 2006.238.08:06:48.76#ibcon#about to read 4, iclass 25, count 2 2006.238.08:06:48.76#ibcon#read 4, iclass 25, count 2 2006.238.08:06:48.76#ibcon#about to read 5, iclass 25, count 2 2006.238.08:06:48.76#ibcon#read 5, iclass 25, count 2 2006.238.08:06:48.76#ibcon#about to read 6, iclass 25, count 2 2006.238.08:06:48.76#ibcon#read 6, iclass 25, count 2 2006.238.08:06:48.76#ibcon#end of sib2, iclass 25, count 2 2006.238.08:06:48.76#ibcon#*mode == 0, iclass 25, count 2 2006.238.08:06:48.76#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.08:06:48.76#ibcon#[25=AT06-07\r\n] 2006.238.08:06:48.76#ibcon#*before write, iclass 25, count 2 2006.238.08:06:48.76#ibcon#enter sib2, iclass 25, count 2 2006.238.08:06:48.76#ibcon#flushed, iclass 25, count 2 2006.238.08:06:48.76#ibcon#about to write, iclass 25, count 2 2006.238.08:06:48.76#ibcon#wrote, iclass 25, count 2 2006.238.08:06:48.76#ibcon#about to read 3, iclass 25, count 2 2006.238.08:06:48.79#ibcon#read 3, iclass 25, count 2 2006.238.08:06:48.79#ibcon#about to read 4, iclass 25, count 2 2006.238.08:06:48.79#ibcon#read 4, iclass 25, count 2 2006.238.08:06:48.79#ibcon#about to read 5, iclass 25, count 2 2006.238.08:06:48.79#ibcon#read 5, iclass 25, count 2 2006.238.08:06:48.79#ibcon#about to read 6, iclass 25, count 2 2006.238.08:06:48.79#ibcon#read 6, iclass 25, count 2 2006.238.08:06:48.79#ibcon#end of sib2, iclass 25, count 2 2006.238.08:06:48.79#ibcon#*after write, iclass 25, count 2 2006.238.08:06:48.79#ibcon#*before return 0, iclass 25, count 2 2006.238.08:06:48.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:06:48.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:06:48.79#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.08:06:48.79#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:48.79#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:06:48.91#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:06:48.91#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:06:48.91#ibcon#enter wrdev, iclass 25, count 0 2006.238.08:06:48.91#ibcon#first serial, iclass 25, count 0 2006.238.08:06:48.91#ibcon#enter sib2, iclass 25, count 0 2006.238.08:06:48.91#ibcon#flushed, iclass 25, count 0 2006.238.08:06:48.91#ibcon#about to write, iclass 25, count 0 2006.238.08:06:48.91#ibcon#wrote, iclass 25, count 0 2006.238.08:06:48.91#ibcon#about to read 3, iclass 25, count 0 2006.238.08:06:48.93#ibcon#read 3, iclass 25, count 0 2006.238.08:06:48.93#ibcon#about to read 4, iclass 25, count 0 2006.238.08:06:48.93#ibcon#read 4, iclass 25, count 0 2006.238.08:06:48.93#ibcon#about to read 5, iclass 25, count 0 2006.238.08:06:48.93#ibcon#read 5, iclass 25, count 0 2006.238.08:06:48.93#ibcon#about to read 6, iclass 25, count 0 2006.238.08:06:48.93#ibcon#read 6, iclass 25, count 0 2006.238.08:06:48.93#ibcon#end of sib2, iclass 25, count 0 2006.238.08:06:48.93#ibcon#*mode == 0, iclass 25, count 0 2006.238.08:06:48.93#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.08:06:48.93#ibcon#[25=USB\r\n] 2006.238.08:06:48.93#ibcon#*before write, iclass 25, count 0 2006.238.08:06:48.93#ibcon#enter sib2, iclass 25, count 0 2006.238.08:06:48.93#ibcon#flushed, iclass 25, count 0 2006.238.08:06:48.93#ibcon#about to write, iclass 25, count 0 2006.238.08:06:48.93#ibcon#wrote, iclass 25, count 0 2006.238.08:06:48.93#ibcon#about to read 3, iclass 25, count 0 2006.238.08:06:48.96#ibcon#read 3, iclass 25, count 0 2006.238.08:06:48.96#ibcon#about to read 4, iclass 25, count 0 2006.238.08:06:48.96#ibcon#read 4, iclass 25, count 0 2006.238.08:06:48.96#ibcon#about to read 5, iclass 25, count 0 2006.238.08:06:48.96#ibcon#read 5, iclass 25, count 0 2006.238.08:06:48.96#ibcon#about to read 6, iclass 25, count 0 2006.238.08:06:48.96#ibcon#read 6, iclass 25, count 0 2006.238.08:06:48.96#ibcon#end of sib2, iclass 25, count 0 2006.238.08:06:48.96#ibcon#*after write, iclass 25, count 0 2006.238.08:06:48.96#ibcon#*before return 0, iclass 25, count 0 2006.238.08:06:48.96#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:06:48.96#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:06:48.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.08:06:48.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.08:06:48.96$vc4f8/valo=7,832.99 2006.238.08:06:48.96#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.08:06:48.96#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.08:06:48.96#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:48.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:06:48.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:06:48.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:06:48.96#ibcon#enter wrdev, iclass 27, count 0 2006.238.08:06:48.96#ibcon#first serial, iclass 27, count 0 2006.238.08:06:48.96#ibcon#enter sib2, iclass 27, count 0 2006.238.08:06:48.96#ibcon#flushed, iclass 27, count 0 2006.238.08:06:48.96#ibcon#about to write, iclass 27, count 0 2006.238.08:06:48.96#ibcon#wrote, iclass 27, count 0 2006.238.08:06:48.96#ibcon#about to read 3, iclass 27, count 0 2006.238.08:06:48.98#ibcon#read 3, iclass 27, count 0 2006.238.08:06:48.98#ibcon#about to read 4, iclass 27, count 0 2006.238.08:06:48.98#ibcon#read 4, iclass 27, count 0 2006.238.08:06:48.98#ibcon#about to read 5, iclass 27, count 0 2006.238.08:06:48.98#ibcon#read 5, iclass 27, count 0 2006.238.08:06:48.98#ibcon#about to read 6, iclass 27, count 0 2006.238.08:06:48.98#ibcon#read 6, iclass 27, count 0 2006.238.08:06:48.98#ibcon#end of sib2, iclass 27, count 0 2006.238.08:06:48.98#ibcon#*mode == 0, iclass 27, count 0 2006.238.08:06:48.98#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.08:06:48.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:06:48.98#ibcon#*before write, iclass 27, count 0 2006.238.08:06:48.98#ibcon#enter sib2, iclass 27, count 0 2006.238.08:06:48.98#ibcon#flushed, iclass 27, count 0 2006.238.08:06:48.98#ibcon#about to write, iclass 27, count 0 2006.238.08:06:48.98#ibcon#wrote, iclass 27, count 0 2006.238.08:06:48.98#ibcon#about to read 3, iclass 27, count 0 2006.238.08:06:49.02#ibcon#read 3, iclass 27, count 0 2006.238.08:06:49.02#ibcon#about to read 4, iclass 27, count 0 2006.238.08:06:49.02#ibcon#read 4, iclass 27, count 0 2006.238.08:06:49.02#ibcon#about to read 5, iclass 27, count 0 2006.238.08:06:49.02#ibcon#read 5, iclass 27, count 0 2006.238.08:06:49.02#ibcon#about to read 6, iclass 27, count 0 2006.238.08:06:49.02#ibcon#read 6, iclass 27, count 0 2006.238.08:06:49.02#ibcon#end of sib2, iclass 27, count 0 2006.238.08:06:49.02#ibcon#*after write, iclass 27, count 0 2006.238.08:06:49.02#ibcon#*before return 0, iclass 27, count 0 2006.238.08:06:49.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:06:49.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:06:49.02#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.08:06:49.02#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.08:06:49.02$vc4f8/va=7,7 2006.238.08:06:49.02#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.08:06:49.02#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.08:06:49.02#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:49.02#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:06:49.08#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:06:49.08#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:06:49.08#ibcon#enter wrdev, iclass 29, count 2 2006.238.08:06:49.08#ibcon#first serial, iclass 29, count 2 2006.238.08:06:49.08#ibcon#enter sib2, iclass 29, count 2 2006.238.08:06:49.08#ibcon#flushed, iclass 29, count 2 2006.238.08:06:49.08#ibcon#about to write, iclass 29, count 2 2006.238.08:06:49.08#ibcon#wrote, iclass 29, count 2 2006.238.08:06:49.08#ibcon#about to read 3, iclass 29, count 2 2006.238.08:06:49.10#ibcon#read 3, iclass 29, count 2 2006.238.08:06:49.10#ibcon#about to read 4, iclass 29, count 2 2006.238.08:06:49.10#ibcon#read 4, iclass 29, count 2 2006.238.08:06:49.10#ibcon#about to read 5, iclass 29, count 2 2006.238.08:06:49.10#ibcon#read 5, iclass 29, count 2 2006.238.08:06:49.10#ibcon#about to read 6, iclass 29, count 2 2006.238.08:06:49.10#ibcon#read 6, iclass 29, count 2 2006.238.08:06:49.10#ibcon#end of sib2, iclass 29, count 2 2006.238.08:06:49.10#ibcon#*mode == 0, iclass 29, count 2 2006.238.08:06:49.10#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.08:06:49.10#ibcon#[25=AT07-07\r\n] 2006.238.08:06:49.10#ibcon#*before write, iclass 29, count 2 2006.238.08:06:49.10#ibcon#enter sib2, iclass 29, count 2 2006.238.08:06:49.10#ibcon#flushed, iclass 29, count 2 2006.238.08:06:49.10#ibcon#about to write, iclass 29, count 2 2006.238.08:06:49.10#ibcon#wrote, iclass 29, count 2 2006.238.08:06:49.10#ibcon#about to read 3, iclass 29, count 2 2006.238.08:06:49.13#ibcon#read 3, iclass 29, count 2 2006.238.08:06:49.13#ibcon#about to read 4, iclass 29, count 2 2006.238.08:06:49.13#ibcon#read 4, iclass 29, count 2 2006.238.08:06:49.13#ibcon#about to read 5, iclass 29, count 2 2006.238.08:06:49.13#ibcon#read 5, iclass 29, count 2 2006.238.08:06:49.13#ibcon#about to read 6, iclass 29, count 2 2006.238.08:06:49.13#ibcon#read 6, iclass 29, count 2 2006.238.08:06:49.13#ibcon#end of sib2, iclass 29, count 2 2006.238.08:06:49.13#ibcon#*after write, iclass 29, count 2 2006.238.08:06:49.13#ibcon#*before return 0, iclass 29, count 2 2006.238.08:06:49.13#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:06:49.13#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:06:49.13#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.08:06:49.13#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:49.13#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:06:49.25#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:06:49.25#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:06:49.25#ibcon#enter wrdev, iclass 29, count 0 2006.238.08:06:49.25#ibcon#first serial, iclass 29, count 0 2006.238.08:06:49.25#ibcon#enter sib2, iclass 29, count 0 2006.238.08:06:49.25#ibcon#flushed, iclass 29, count 0 2006.238.08:06:49.25#ibcon#about to write, iclass 29, count 0 2006.238.08:06:49.25#ibcon#wrote, iclass 29, count 0 2006.238.08:06:49.25#ibcon#about to read 3, iclass 29, count 0 2006.238.08:06:49.27#ibcon#read 3, iclass 29, count 0 2006.238.08:06:49.27#ibcon#about to read 4, iclass 29, count 0 2006.238.08:06:49.27#ibcon#read 4, iclass 29, count 0 2006.238.08:06:49.27#ibcon#about to read 5, iclass 29, count 0 2006.238.08:06:49.27#ibcon#read 5, iclass 29, count 0 2006.238.08:06:49.27#ibcon#about to read 6, iclass 29, count 0 2006.238.08:06:49.27#ibcon#read 6, iclass 29, count 0 2006.238.08:06:49.27#ibcon#end of sib2, iclass 29, count 0 2006.238.08:06:49.27#ibcon#*mode == 0, iclass 29, count 0 2006.238.08:06:49.27#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.08:06:49.27#ibcon#[25=USB\r\n] 2006.238.08:06:49.27#ibcon#*before write, iclass 29, count 0 2006.238.08:06:49.27#ibcon#enter sib2, iclass 29, count 0 2006.238.08:06:49.27#ibcon#flushed, iclass 29, count 0 2006.238.08:06:49.27#ibcon#about to write, iclass 29, count 0 2006.238.08:06:49.27#ibcon#wrote, iclass 29, count 0 2006.238.08:06:49.27#ibcon#about to read 3, iclass 29, count 0 2006.238.08:06:49.30#ibcon#read 3, iclass 29, count 0 2006.238.08:06:49.30#ibcon#about to read 4, iclass 29, count 0 2006.238.08:06:49.30#ibcon#read 4, iclass 29, count 0 2006.238.08:06:49.30#ibcon#about to read 5, iclass 29, count 0 2006.238.08:06:49.30#ibcon#read 5, iclass 29, count 0 2006.238.08:06:49.30#ibcon#about to read 6, iclass 29, count 0 2006.238.08:06:49.30#ibcon#read 6, iclass 29, count 0 2006.238.08:06:49.30#ibcon#end of sib2, iclass 29, count 0 2006.238.08:06:49.30#ibcon#*after write, iclass 29, count 0 2006.238.08:06:49.30#ibcon#*before return 0, iclass 29, count 0 2006.238.08:06:49.30#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:06:49.30#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:06:49.30#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.08:06:49.30#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.08:06:49.30$vc4f8/valo=8,852.99 2006.238.08:06:49.30#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.08:06:49.30#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.08:06:49.30#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:49.30#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:06:49.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:06:49.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:06:49.30#ibcon#enter wrdev, iclass 31, count 0 2006.238.08:06:49.30#ibcon#first serial, iclass 31, count 0 2006.238.08:06:49.30#ibcon#enter sib2, iclass 31, count 0 2006.238.08:06:49.30#ibcon#flushed, iclass 31, count 0 2006.238.08:06:49.30#ibcon#about to write, iclass 31, count 0 2006.238.08:06:49.30#ibcon#wrote, iclass 31, count 0 2006.238.08:06:49.30#ibcon#about to read 3, iclass 31, count 0 2006.238.08:06:49.32#ibcon#read 3, iclass 31, count 0 2006.238.08:06:49.32#ibcon#about to read 4, iclass 31, count 0 2006.238.08:06:49.32#ibcon#read 4, iclass 31, count 0 2006.238.08:06:49.32#ibcon#about to read 5, iclass 31, count 0 2006.238.08:06:49.32#ibcon#read 5, iclass 31, count 0 2006.238.08:06:49.32#ibcon#about to read 6, iclass 31, count 0 2006.238.08:06:49.32#ibcon#read 6, iclass 31, count 0 2006.238.08:06:49.32#ibcon#end of sib2, iclass 31, count 0 2006.238.08:06:49.32#ibcon#*mode == 0, iclass 31, count 0 2006.238.08:06:49.32#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.08:06:49.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:06:49.32#ibcon#*before write, iclass 31, count 0 2006.238.08:06:49.32#ibcon#enter sib2, iclass 31, count 0 2006.238.08:06:49.32#ibcon#flushed, iclass 31, count 0 2006.238.08:06:49.32#ibcon#about to write, iclass 31, count 0 2006.238.08:06:49.32#ibcon#wrote, iclass 31, count 0 2006.238.08:06:49.32#ibcon#about to read 3, iclass 31, count 0 2006.238.08:06:49.36#ibcon#read 3, iclass 31, count 0 2006.238.08:06:49.36#ibcon#about to read 4, iclass 31, count 0 2006.238.08:06:49.36#ibcon#read 4, iclass 31, count 0 2006.238.08:06:49.36#ibcon#about to read 5, iclass 31, count 0 2006.238.08:06:49.36#ibcon#read 5, iclass 31, count 0 2006.238.08:06:49.36#ibcon#about to read 6, iclass 31, count 0 2006.238.08:06:49.36#ibcon#read 6, iclass 31, count 0 2006.238.08:06:49.36#ibcon#end of sib2, iclass 31, count 0 2006.238.08:06:49.36#ibcon#*after write, iclass 31, count 0 2006.238.08:06:49.36#ibcon#*before return 0, iclass 31, count 0 2006.238.08:06:49.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:06:49.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:06:49.36#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.08:06:49.36#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.08:06:49.36$vc4f8/va=8,7 2006.238.08:06:49.36#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.08:06:49.36#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.08:06:49.36#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:49.36#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:06:49.42#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:06:49.42#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:06:49.42#ibcon#enter wrdev, iclass 33, count 2 2006.238.08:06:49.42#ibcon#first serial, iclass 33, count 2 2006.238.08:06:49.42#ibcon#enter sib2, iclass 33, count 2 2006.238.08:06:49.42#ibcon#flushed, iclass 33, count 2 2006.238.08:06:49.42#ibcon#about to write, iclass 33, count 2 2006.238.08:06:49.42#ibcon#wrote, iclass 33, count 2 2006.238.08:06:49.42#ibcon#about to read 3, iclass 33, count 2 2006.238.08:06:49.44#ibcon#read 3, iclass 33, count 2 2006.238.08:06:49.44#ibcon#about to read 4, iclass 33, count 2 2006.238.08:06:49.44#ibcon#read 4, iclass 33, count 2 2006.238.08:06:49.44#ibcon#about to read 5, iclass 33, count 2 2006.238.08:06:49.44#ibcon#read 5, iclass 33, count 2 2006.238.08:06:49.44#ibcon#about to read 6, iclass 33, count 2 2006.238.08:06:49.44#ibcon#read 6, iclass 33, count 2 2006.238.08:06:49.44#ibcon#end of sib2, iclass 33, count 2 2006.238.08:06:49.44#ibcon#*mode == 0, iclass 33, count 2 2006.238.08:06:49.44#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.08:06:49.44#ibcon#[25=AT08-07\r\n] 2006.238.08:06:49.44#ibcon#*before write, iclass 33, count 2 2006.238.08:06:49.44#ibcon#enter sib2, iclass 33, count 2 2006.238.08:06:49.44#ibcon#flushed, iclass 33, count 2 2006.238.08:06:49.44#ibcon#about to write, iclass 33, count 2 2006.238.08:06:49.44#ibcon#wrote, iclass 33, count 2 2006.238.08:06:49.44#ibcon#about to read 3, iclass 33, count 2 2006.238.08:06:49.47#ibcon#read 3, iclass 33, count 2 2006.238.08:06:49.47#ibcon#about to read 4, iclass 33, count 2 2006.238.08:06:49.47#ibcon#read 4, iclass 33, count 2 2006.238.08:06:49.47#ibcon#about to read 5, iclass 33, count 2 2006.238.08:06:49.47#ibcon#read 5, iclass 33, count 2 2006.238.08:06:49.47#ibcon#about to read 6, iclass 33, count 2 2006.238.08:06:49.47#ibcon#read 6, iclass 33, count 2 2006.238.08:06:49.47#ibcon#end of sib2, iclass 33, count 2 2006.238.08:06:49.47#ibcon#*after write, iclass 33, count 2 2006.238.08:06:49.47#ibcon#*before return 0, iclass 33, count 2 2006.238.08:06:49.47#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:06:49.47#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:06:49.47#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.08:06:49.47#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:49.47#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:06:49.59#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:06:49.59#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:06:49.59#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:06:49.59#ibcon#first serial, iclass 33, count 0 2006.238.08:06:49.59#ibcon#enter sib2, iclass 33, count 0 2006.238.08:06:49.59#ibcon#flushed, iclass 33, count 0 2006.238.08:06:49.59#ibcon#about to write, iclass 33, count 0 2006.238.08:06:49.59#ibcon#wrote, iclass 33, count 0 2006.238.08:06:49.59#ibcon#about to read 3, iclass 33, count 0 2006.238.08:06:49.61#ibcon#read 3, iclass 33, count 0 2006.238.08:06:49.61#ibcon#about to read 4, iclass 33, count 0 2006.238.08:06:49.61#ibcon#read 4, iclass 33, count 0 2006.238.08:06:49.61#ibcon#about to read 5, iclass 33, count 0 2006.238.08:06:49.61#ibcon#read 5, iclass 33, count 0 2006.238.08:06:49.61#ibcon#about to read 6, iclass 33, count 0 2006.238.08:06:49.61#ibcon#read 6, iclass 33, count 0 2006.238.08:06:49.61#ibcon#end of sib2, iclass 33, count 0 2006.238.08:06:49.61#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:06:49.61#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:06:49.61#ibcon#[25=USB\r\n] 2006.238.08:06:49.61#ibcon#*before write, iclass 33, count 0 2006.238.08:06:49.61#ibcon#enter sib2, iclass 33, count 0 2006.238.08:06:49.61#ibcon#flushed, iclass 33, count 0 2006.238.08:06:49.61#ibcon#about to write, iclass 33, count 0 2006.238.08:06:49.61#ibcon#wrote, iclass 33, count 0 2006.238.08:06:49.61#ibcon#about to read 3, iclass 33, count 0 2006.238.08:06:49.64#ibcon#read 3, iclass 33, count 0 2006.238.08:06:49.64#ibcon#about to read 4, iclass 33, count 0 2006.238.08:06:49.64#ibcon#read 4, iclass 33, count 0 2006.238.08:06:49.64#ibcon#about to read 5, iclass 33, count 0 2006.238.08:06:49.64#ibcon#read 5, iclass 33, count 0 2006.238.08:06:49.64#ibcon#about to read 6, iclass 33, count 0 2006.238.08:06:49.64#ibcon#read 6, iclass 33, count 0 2006.238.08:06:49.64#ibcon#end of sib2, iclass 33, count 0 2006.238.08:06:49.64#ibcon#*after write, iclass 33, count 0 2006.238.08:06:49.64#ibcon#*before return 0, iclass 33, count 0 2006.238.08:06:49.64#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:06:49.64#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:06:49.64#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:06:49.64#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:06:49.64$vc4f8/vblo=1,632.99 2006.238.08:06:49.64#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.08:06:49.64#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.08:06:49.64#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:49.64#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:06:49.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:06:49.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:06:49.64#ibcon#enter wrdev, iclass 35, count 0 2006.238.08:06:49.64#ibcon#first serial, iclass 35, count 0 2006.238.08:06:49.64#ibcon#enter sib2, iclass 35, count 0 2006.238.08:06:49.64#ibcon#flushed, iclass 35, count 0 2006.238.08:06:49.64#ibcon#about to write, iclass 35, count 0 2006.238.08:06:49.64#ibcon#wrote, iclass 35, count 0 2006.238.08:06:49.64#ibcon#about to read 3, iclass 35, count 0 2006.238.08:06:49.66#ibcon#read 3, iclass 35, count 0 2006.238.08:06:49.66#ibcon#about to read 4, iclass 35, count 0 2006.238.08:06:49.66#ibcon#read 4, iclass 35, count 0 2006.238.08:06:49.66#ibcon#about to read 5, iclass 35, count 0 2006.238.08:06:49.66#ibcon#read 5, iclass 35, count 0 2006.238.08:06:49.66#ibcon#about to read 6, iclass 35, count 0 2006.238.08:06:49.66#ibcon#read 6, iclass 35, count 0 2006.238.08:06:49.66#ibcon#end of sib2, iclass 35, count 0 2006.238.08:06:49.66#ibcon#*mode == 0, iclass 35, count 0 2006.238.08:06:49.66#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.08:06:49.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:06:49.66#ibcon#*before write, iclass 35, count 0 2006.238.08:06:49.66#ibcon#enter sib2, iclass 35, count 0 2006.238.08:06:49.66#ibcon#flushed, iclass 35, count 0 2006.238.08:06:49.66#ibcon#about to write, iclass 35, count 0 2006.238.08:06:49.66#ibcon#wrote, iclass 35, count 0 2006.238.08:06:49.66#ibcon#about to read 3, iclass 35, count 0 2006.238.08:06:49.70#ibcon#read 3, iclass 35, count 0 2006.238.08:06:49.70#ibcon#about to read 4, iclass 35, count 0 2006.238.08:06:49.70#ibcon#read 4, iclass 35, count 0 2006.238.08:06:49.70#ibcon#about to read 5, iclass 35, count 0 2006.238.08:06:49.70#ibcon#read 5, iclass 35, count 0 2006.238.08:06:49.70#ibcon#about to read 6, iclass 35, count 0 2006.238.08:06:49.70#ibcon#read 6, iclass 35, count 0 2006.238.08:06:49.70#ibcon#end of sib2, iclass 35, count 0 2006.238.08:06:49.70#ibcon#*after write, iclass 35, count 0 2006.238.08:06:49.70#ibcon#*before return 0, iclass 35, count 0 2006.238.08:06:49.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:06:49.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:06:49.70#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.08:06:49.70#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.08:06:49.70$vc4f8/vb=1,4 2006.238.08:06:49.70#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.08:06:49.70#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.08:06:49.70#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:49.70#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:06:49.70#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:06:49.70#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:06:49.70#ibcon#enter wrdev, iclass 37, count 2 2006.238.08:06:49.70#ibcon#first serial, iclass 37, count 2 2006.238.08:06:49.70#ibcon#enter sib2, iclass 37, count 2 2006.238.08:06:49.70#ibcon#flushed, iclass 37, count 2 2006.238.08:06:49.70#ibcon#about to write, iclass 37, count 2 2006.238.08:06:49.70#ibcon#wrote, iclass 37, count 2 2006.238.08:06:49.70#ibcon#about to read 3, iclass 37, count 2 2006.238.08:06:49.72#ibcon#read 3, iclass 37, count 2 2006.238.08:06:49.72#ibcon#about to read 4, iclass 37, count 2 2006.238.08:06:49.72#ibcon#read 4, iclass 37, count 2 2006.238.08:06:49.72#ibcon#about to read 5, iclass 37, count 2 2006.238.08:06:49.72#ibcon#read 5, iclass 37, count 2 2006.238.08:06:49.72#ibcon#about to read 6, iclass 37, count 2 2006.238.08:06:49.72#ibcon#read 6, iclass 37, count 2 2006.238.08:06:49.72#ibcon#end of sib2, iclass 37, count 2 2006.238.08:06:49.72#ibcon#*mode == 0, iclass 37, count 2 2006.238.08:06:49.72#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.08:06:49.72#ibcon#[27=AT01-04\r\n] 2006.238.08:06:49.72#ibcon#*before write, iclass 37, count 2 2006.238.08:06:49.72#ibcon#enter sib2, iclass 37, count 2 2006.238.08:06:49.72#ibcon#flushed, iclass 37, count 2 2006.238.08:06:49.72#ibcon#about to write, iclass 37, count 2 2006.238.08:06:49.72#ibcon#wrote, iclass 37, count 2 2006.238.08:06:49.72#ibcon#about to read 3, iclass 37, count 2 2006.238.08:06:49.75#ibcon#read 3, iclass 37, count 2 2006.238.08:06:49.75#ibcon#about to read 4, iclass 37, count 2 2006.238.08:06:49.75#ibcon#read 4, iclass 37, count 2 2006.238.08:06:49.75#ibcon#about to read 5, iclass 37, count 2 2006.238.08:06:49.75#ibcon#read 5, iclass 37, count 2 2006.238.08:06:49.75#ibcon#about to read 6, iclass 37, count 2 2006.238.08:06:49.75#ibcon#read 6, iclass 37, count 2 2006.238.08:06:49.75#ibcon#end of sib2, iclass 37, count 2 2006.238.08:06:49.75#ibcon#*after write, iclass 37, count 2 2006.238.08:06:49.75#ibcon#*before return 0, iclass 37, count 2 2006.238.08:06:49.75#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:06:49.75#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:06:49.75#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.08:06:49.75#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:49.75#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:06:49.87#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:06:49.87#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:06:49.87#ibcon#enter wrdev, iclass 37, count 0 2006.238.08:06:49.87#ibcon#first serial, iclass 37, count 0 2006.238.08:06:49.87#ibcon#enter sib2, iclass 37, count 0 2006.238.08:06:49.87#ibcon#flushed, iclass 37, count 0 2006.238.08:06:49.87#ibcon#about to write, iclass 37, count 0 2006.238.08:06:49.87#ibcon#wrote, iclass 37, count 0 2006.238.08:06:49.87#ibcon#about to read 3, iclass 37, count 0 2006.238.08:06:49.89#ibcon#read 3, iclass 37, count 0 2006.238.08:06:49.89#ibcon#about to read 4, iclass 37, count 0 2006.238.08:06:49.89#ibcon#read 4, iclass 37, count 0 2006.238.08:06:49.89#ibcon#about to read 5, iclass 37, count 0 2006.238.08:06:49.89#ibcon#read 5, iclass 37, count 0 2006.238.08:06:49.89#ibcon#about to read 6, iclass 37, count 0 2006.238.08:06:49.89#ibcon#read 6, iclass 37, count 0 2006.238.08:06:49.89#ibcon#end of sib2, iclass 37, count 0 2006.238.08:06:49.89#ibcon#*mode == 0, iclass 37, count 0 2006.238.08:06:49.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.08:06:49.89#ibcon#[27=USB\r\n] 2006.238.08:06:49.89#ibcon#*before write, iclass 37, count 0 2006.238.08:06:49.89#ibcon#enter sib2, iclass 37, count 0 2006.238.08:06:49.89#ibcon#flushed, iclass 37, count 0 2006.238.08:06:49.89#ibcon#about to write, iclass 37, count 0 2006.238.08:06:49.89#ibcon#wrote, iclass 37, count 0 2006.238.08:06:49.89#ibcon#about to read 3, iclass 37, count 0 2006.238.08:06:49.92#ibcon#read 3, iclass 37, count 0 2006.238.08:06:49.92#ibcon#about to read 4, iclass 37, count 0 2006.238.08:06:49.92#ibcon#read 4, iclass 37, count 0 2006.238.08:06:49.92#ibcon#about to read 5, iclass 37, count 0 2006.238.08:06:49.92#ibcon#read 5, iclass 37, count 0 2006.238.08:06:49.92#ibcon#about to read 6, iclass 37, count 0 2006.238.08:06:49.92#ibcon#read 6, iclass 37, count 0 2006.238.08:06:49.92#ibcon#end of sib2, iclass 37, count 0 2006.238.08:06:49.92#ibcon#*after write, iclass 37, count 0 2006.238.08:06:49.92#ibcon#*before return 0, iclass 37, count 0 2006.238.08:06:49.92#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:06:49.92#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:06:49.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.08:06:49.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.08:06:49.92$vc4f8/vblo=2,640.99 2006.238.08:06:49.92#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.08:06:49.92#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.08:06:49.92#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:49.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:06:49.92#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:06:49.92#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:06:49.92#ibcon#enter wrdev, iclass 39, count 0 2006.238.08:06:49.92#ibcon#first serial, iclass 39, count 0 2006.238.08:06:49.92#ibcon#enter sib2, iclass 39, count 0 2006.238.08:06:49.92#ibcon#flushed, iclass 39, count 0 2006.238.08:06:49.92#ibcon#about to write, iclass 39, count 0 2006.238.08:06:49.92#ibcon#wrote, iclass 39, count 0 2006.238.08:06:49.92#ibcon#about to read 3, iclass 39, count 0 2006.238.08:06:49.94#ibcon#read 3, iclass 39, count 0 2006.238.08:06:49.94#ibcon#about to read 4, iclass 39, count 0 2006.238.08:06:49.94#ibcon#read 4, iclass 39, count 0 2006.238.08:06:49.94#ibcon#about to read 5, iclass 39, count 0 2006.238.08:06:49.94#ibcon#read 5, iclass 39, count 0 2006.238.08:06:49.94#ibcon#about to read 6, iclass 39, count 0 2006.238.08:06:49.94#ibcon#read 6, iclass 39, count 0 2006.238.08:06:49.94#ibcon#end of sib2, iclass 39, count 0 2006.238.08:06:49.94#ibcon#*mode == 0, iclass 39, count 0 2006.238.08:06:49.94#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.08:06:49.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:06:49.94#ibcon#*before write, iclass 39, count 0 2006.238.08:06:49.94#ibcon#enter sib2, iclass 39, count 0 2006.238.08:06:49.94#ibcon#flushed, iclass 39, count 0 2006.238.08:06:49.94#ibcon#about to write, iclass 39, count 0 2006.238.08:06:49.94#ibcon#wrote, iclass 39, count 0 2006.238.08:06:49.94#ibcon#about to read 3, iclass 39, count 0 2006.238.08:06:49.98#ibcon#read 3, iclass 39, count 0 2006.238.08:06:49.98#ibcon#about to read 4, iclass 39, count 0 2006.238.08:06:49.98#ibcon#read 4, iclass 39, count 0 2006.238.08:06:49.98#ibcon#about to read 5, iclass 39, count 0 2006.238.08:06:49.98#ibcon#read 5, iclass 39, count 0 2006.238.08:06:49.98#ibcon#about to read 6, iclass 39, count 0 2006.238.08:06:49.98#ibcon#read 6, iclass 39, count 0 2006.238.08:06:49.98#ibcon#end of sib2, iclass 39, count 0 2006.238.08:06:49.98#ibcon#*after write, iclass 39, count 0 2006.238.08:06:49.98#ibcon#*before return 0, iclass 39, count 0 2006.238.08:06:49.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:06:49.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:06:49.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.08:06:49.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.08:06:49.98$vc4f8/vb=2,4 2006.238.08:06:49.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.08:06:49.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.08:06:49.98#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:49.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:06:50.04#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:06:50.04#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:06:50.04#ibcon#enter wrdev, iclass 3, count 2 2006.238.08:06:50.04#ibcon#first serial, iclass 3, count 2 2006.238.08:06:50.04#ibcon#enter sib2, iclass 3, count 2 2006.238.08:06:50.04#ibcon#flushed, iclass 3, count 2 2006.238.08:06:50.04#ibcon#about to write, iclass 3, count 2 2006.238.08:06:50.04#ibcon#wrote, iclass 3, count 2 2006.238.08:06:50.04#ibcon#about to read 3, iclass 3, count 2 2006.238.08:06:50.06#ibcon#read 3, iclass 3, count 2 2006.238.08:06:50.06#ibcon#about to read 4, iclass 3, count 2 2006.238.08:06:50.06#ibcon#read 4, iclass 3, count 2 2006.238.08:06:50.06#ibcon#about to read 5, iclass 3, count 2 2006.238.08:06:50.06#ibcon#read 5, iclass 3, count 2 2006.238.08:06:50.06#ibcon#about to read 6, iclass 3, count 2 2006.238.08:06:50.06#ibcon#read 6, iclass 3, count 2 2006.238.08:06:50.06#ibcon#end of sib2, iclass 3, count 2 2006.238.08:06:50.06#ibcon#*mode == 0, iclass 3, count 2 2006.238.08:06:50.06#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.08:06:50.06#ibcon#[27=AT02-04\r\n] 2006.238.08:06:50.06#ibcon#*before write, iclass 3, count 2 2006.238.08:06:50.06#ibcon#enter sib2, iclass 3, count 2 2006.238.08:06:50.06#ibcon#flushed, iclass 3, count 2 2006.238.08:06:50.06#ibcon#about to write, iclass 3, count 2 2006.238.08:06:50.06#ibcon#wrote, iclass 3, count 2 2006.238.08:06:50.06#ibcon#about to read 3, iclass 3, count 2 2006.238.08:06:50.09#ibcon#read 3, iclass 3, count 2 2006.238.08:06:50.09#ibcon#about to read 4, iclass 3, count 2 2006.238.08:06:50.09#ibcon#read 4, iclass 3, count 2 2006.238.08:06:50.09#ibcon#about to read 5, iclass 3, count 2 2006.238.08:06:50.09#ibcon#read 5, iclass 3, count 2 2006.238.08:06:50.09#ibcon#about to read 6, iclass 3, count 2 2006.238.08:06:50.09#ibcon#read 6, iclass 3, count 2 2006.238.08:06:50.09#ibcon#end of sib2, iclass 3, count 2 2006.238.08:06:50.09#ibcon#*after write, iclass 3, count 2 2006.238.08:06:50.09#ibcon#*before return 0, iclass 3, count 2 2006.238.08:06:50.09#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:06:50.09#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:06:50.09#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.08:06:50.09#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:50.09#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:06:50.22#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:06:50.22#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:06:50.22#ibcon#enter wrdev, iclass 3, count 0 2006.238.08:06:50.22#ibcon#first serial, iclass 3, count 0 2006.238.08:06:50.22#ibcon#enter sib2, iclass 3, count 0 2006.238.08:06:50.22#ibcon#flushed, iclass 3, count 0 2006.238.08:06:50.22#ibcon#about to write, iclass 3, count 0 2006.238.08:06:50.22#ibcon#wrote, iclass 3, count 0 2006.238.08:06:50.22#ibcon#about to read 3, iclass 3, count 0 2006.238.08:06:50.23#ibcon#read 3, iclass 3, count 0 2006.238.08:06:50.23#ibcon#about to read 4, iclass 3, count 0 2006.238.08:06:50.23#ibcon#read 4, iclass 3, count 0 2006.238.08:06:50.23#ibcon#about to read 5, iclass 3, count 0 2006.238.08:06:50.23#ibcon#read 5, iclass 3, count 0 2006.238.08:06:50.23#ibcon#about to read 6, iclass 3, count 0 2006.238.08:06:50.23#ibcon#read 6, iclass 3, count 0 2006.238.08:06:50.23#ibcon#end of sib2, iclass 3, count 0 2006.238.08:06:50.23#ibcon#*mode == 0, iclass 3, count 0 2006.238.08:06:50.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.08:06:50.23#ibcon#[27=USB\r\n] 2006.238.08:06:50.23#ibcon#*before write, iclass 3, count 0 2006.238.08:06:50.23#ibcon#enter sib2, iclass 3, count 0 2006.238.08:06:50.23#ibcon#flushed, iclass 3, count 0 2006.238.08:06:50.23#ibcon#about to write, iclass 3, count 0 2006.238.08:06:50.23#ibcon#wrote, iclass 3, count 0 2006.238.08:06:50.23#ibcon#about to read 3, iclass 3, count 0 2006.238.08:06:50.26#ibcon#read 3, iclass 3, count 0 2006.238.08:06:50.26#ibcon#about to read 4, iclass 3, count 0 2006.238.08:06:50.26#ibcon#read 4, iclass 3, count 0 2006.238.08:06:50.26#ibcon#about to read 5, iclass 3, count 0 2006.238.08:06:50.26#ibcon#read 5, iclass 3, count 0 2006.238.08:06:50.26#ibcon#about to read 6, iclass 3, count 0 2006.238.08:06:50.26#ibcon#read 6, iclass 3, count 0 2006.238.08:06:50.26#ibcon#end of sib2, iclass 3, count 0 2006.238.08:06:50.26#ibcon#*after write, iclass 3, count 0 2006.238.08:06:50.26#ibcon#*before return 0, iclass 3, count 0 2006.238.08:06:50.26#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:06:50.26#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:06:50.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.08:06:50.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.08:06:50.26$vc4f8/vblo=3,656.99 2006.238.08:06:50.26#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.08:06:50.26#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.08:06:50.26#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:50.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:06:50.26#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:06:50.26#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:06:50.26#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:06:50.26#ibcon#first serial, iclass 5, count 0 2006.238.08:06:50.26#ibcon#enter sib2, iclass 5, count 0 2006.238.08:06:50.26#ibcon#flushed, iclass 5, count 0 2006.238.08:06:50.26#ibcon#about to write, iclass 5, count 0 2006.238.08:06:50.26#ibcon#wrote, iclass 5, count 0 2006.238.08:06:50.26#ibcon#about to read 3, iclass 5, count 0 2006.238.08:06:50.28#ibcon#read 3, iclass 5, count 0 2006.238.08:06:50.28#ibcon#about to read 4, iclass 5, count 0 2006.238.08:06:50.28#ibcon#read 4, iclass 5, count 0 2006.238.08:06:50.28#ibcon#about to read 5, iclass 5, count 0 2006.238.08:06:50.28#ibcon#read 5, iclass 5, count 0 2006.238.08:06:50.28#ibcon#about to read 6, iclass 5, count 0 2006.238.08:06:50.28#ibcon#read 6, iclass 5, count 0 2006.238.08:06:50.28#ibcon#end of sib2, iclass 5, count 0 2006.238.08:06:50.28#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:06:50.28#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:06:50.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:06:50.28#ibcon#*before write, iclass 5, count 0 2006.238.08:06:50.28#ibcon#enter sib2, iclass 5, count 0 2006.238.08:06:50.28#ibcon#flushed, iclass 5, count 0 2006.238.08:06:50.28#ibcon#about to write, iclass 5, count 0 2006.238.08:06:50.28#ibcon#wrote, iclass 5, count 0 2006.238.08:06:50.28#ibcon#about to read 3, iclass 5, count 0 2006.238.08:06:50.32#ibcon#read 3, iclass 5, count 0 2006.238.08:06:50.32#ibcon#about to read 4, iclass 5, count 0 2006.238.08:06:50.32#ibcon#read 4, iclass 5, count 0 2006.238.08:06:50.32#ibcon#about to read 5, iclass 5, count 0 2006.238.08:06:50.32#ibcon#read 5, iclass 5, count 0 2006.238.08:06:50.32#ibcon#about to read 6, iclass 5, count 0 2006.238.08:06:50.32#ibcon#read 6, iclass 5, count 0 2006.238.08:06:50.32#ibcon#end of sib2, iclass 5, count 0 2006.238.08:06:50.32#ibcon#*after write, iclass 5, count 0 2006.238.08:06:50.32#ibcon#*before return 0, iclass 5, count 0 2006.238.08:06:50.32#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:06:50.32#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:06:50.32#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:06:50.32#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:06:50.32$vc4f8/vb=3,4 2006.238.08:06:50.32#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.08:06:50.32#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.08:06:50.32#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:50.32#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:06:50.38#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:06:50.38#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:06:50.38#ibcon#enter wrdev, iclass 7, count 2 2006.238.08:06:50.38#ibcon#first serial, iclass 7, count 2 2006.238.08:06:50.38#ibcon#enter sib2, iclass 7, count 2 2006.238.08:06:50.38#ibcon#flushed, iclass 7, count 2 2006.238.08:06:50.38#ibcon#about to write, iclass 7, count 2 2006.238.08:06:50.38#ibcon#wrote, iclass 7, count 2 2006.238.08:06:50.38#ibcon#about to read 3, iclass 7, count 2 2006.238.08:06:50.40#ibcon#read 3, iclass 7, count 2 2006.238.08:06:50.40#ibcon#about to read 4, iclass 7, count 2 2006.238.08:06:50.40#ibcon#read 4, iclass 7, count 2 2006.238.08:06:50.40#ibcon#about to read 5, iclass 7, count 2 2006.238.08:06:50.40#ibcon#read 5, iclass 7, count 2 2006.238.08:06:50.40#ibcon#about to read 6, iclass 7, count 2 2006.238.08:06:50.40#ibcon#read 6, iclass 7, count 2 2006.238.08:06:50.40#ibcon#end of sib2, iclass 7, count 2 2006.238.08:06:50.40#ibcon#*mode == 0, iclass 7, count 2 2006.238.08:06:50.40#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.08:06:50.40#ibcon#[27=AT03-04\r\n] 2006.238.08:06:50.40#ibcon#*before write, iclass 7, count 2 2006.238.08:06:50.40#ibcon#enter sib2, iclass 7, count 2 2006.238.08:06:50.40#ibcon#flushed, iclass 7, count 2 2006.238.08:06:50.40#ibcon#about to write, iclass 7, count 2 2006.238.08:06:50.40#ibcon#wrote, iclass 7, count 2 2006.238.08:06:50.40#ibcon#about to read 3, iclass 7, count 2 2006.238.08:06:50.43#ibcon#read 3, iclass 7, count 2 2006.238.08:06:50.43#ibcon#about to read 4, iclass 7, count 2 2006.238.08:06:50.43#ibcon#read 4, iclass 7, count 2 2006.238.08:06:50.43#ibcon#about to read 5, iclass 7, count 2 2006.238.08:06:50.43#ibcon#read 5, iclass 7, count 2 2006.238.08:06:50.43#ibcon#about to read 6, iclass 7, count 2 2006.238.08:06:50.43#ibcon#read 6, iclass 7, count 2 2006.238.08:06:50.43#ibcon#end of sib2, iclass 7, count 2 2006.238.08:06:50.43#ibcon#*after write, iclass 7, count 2 2006.238.08:06:50.43#ibcon#*before return 0, iclass 7, count 2 2006.238.08:06:50.43#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:06:50.43#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:06:50.43#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.08:06:50.43#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:50.43#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:06:50.55#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:06:50.55#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:06:50.55#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:06:50.55#ibcon#first serial, iclass 7, count 0 2006.238.08:06:50.55#ibcon#enter sib2, iclass 7, count 0 2006.238.08:06:50.55#ibcon#flushed, iclass 7, count 0 2006.238.08:06:50.55#ibcon#about to write, iclass 7, count 0 2006.238.08:06:50.55#ibcon#wrote, iclass 7, count 0 2006.238.08:06:50.55#ibcon#about to read 3, iclass 7, count 0 2006.238.08:06:50.57#ibcon#read 3, iclass 7, count 0 2006.238.08:06:50.57#ibcon#about to read 4, iclass 7, count 0 2006.238.08:06:50.57#ibcon#read 4, iclass 7, count 0 2006.238.08:06:50.57#ibcon#about to read 5, iclass 7, count 0 2006.238.08:06:50.57#ibcon#read 5, iclass 7, count 0 2006.238.08:06:50.57#ibcon#about to read 6, iclass 7, count 0 2006.238.08:06:50.57#ibcon#read 6, iclass 7, count 0 2006.238.08:06:50.57#ibcon#end of sib2, iclass 7, count 0 2006.238.08:06:50.57#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:06:50.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:06:50.57#ibcon#[27=USB\r\n] 2006.238.08:06:50.57#ibcon#*before write, iclass 7, count 0 2006.238.08:06:50.57#ibcon#enter sib2, iclass 7, count 0 2006.238.08:06:50.57#ibcon#flushed, iclass 7, count 0 2006.238.08:06:50.57#ibcon#about to write, iclass 7, count 0 2006.238.08:06:50.57#ibcon#wrote, iclass 7, count 0 2006.238.08:06:50.57#ibcon#about to read 3, iclass 7, count 0 2006.238.08:06:50.60#ibcon#read 3, iclass 7, count 0 2006.238.08:06:50.60#ibcon#about to read 4, iclass 7, count 0 2006.238.08:06:50.60#ibcon#read 4, iclass 7, count 0 2006.238.08:06:50.60#ibcon#about to read 5, iclass 7, count 0 2006.238.08:06:50.60#ibcon#read 5, iclass 7, count 0 2006.238.08:06:50.60#ibcon#about to read 6, iclass 7, count 0 2006.238.08:06:50.60#ibcon#read 6, iclass 7, count 0 2006.238.08:06:50.60#ibcon#end of sib2, iclass 7, count 0 2006.238.08:06:50.60#ibcon#*after write, iclass 7, count 0 2006.238.08:06:50.60#ibcon#*before return 0, iclass 7, count 0 2006.238.08:06:50.60#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:06:50.60#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:06:50.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:06:50.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:06:50.60$vc4f8/vblo=4,712.99 2006.238.08:06:50.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.08:06:50.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.08:06:50.60#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:50.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:06:50.60#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:06:50.60#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:06:50.60#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:06:50.60#ibcon#first serial, iclass 11, count 0 2006.238.08:06:50.60#ibcon#enter sib2, iclass 11, count 0 2006.238.08:06:50.60#ibcon#flushed, iclass 11, count 0 2006.238.08:06:50.60#ibcon#about to write, iclass 11, count 0 2006.238.08:06:50.60#ibcon#wrote, iclass 11, count 0 2006.238.08:06:50.60#ibcon#about to read 3, iclass 11, count 0 2006.238.08:06:50.62#ibcon#read 3, iclass 11, count 0 2006.238.08:06:50.62#ibcon#about to read 4, iclass 11, count 0 2006.238.08:06:50.62#ibcon#read 4, iclass 11, count 0 2006.238.08:06:50.62#ibcon#about to read 5, iclass 11, count 0 2006.238.08:06:50.62#ibcon#read 5, iclass 11, count 0 2006.238.08:06:50.62#ibcon#about to read 6, iclass 11, count 0 2006.238.08:06:50.62#ibcon#read 6, iclass 11, count 0 2006.238.08:06:50.62#ibcon#end of sib2, iclass 11, count 0 2006.238.08:06:50.62#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:06:50.62#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:06:50.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:06:50.62#ibcon#*before write, iclass 11, count 0 2006.238.08:06:50.62#ibcon#enter sib2, iclass 11, count 0 2006.238.08:06:50.62#ibcon#flushed, iclass 11, count 0 2006.238.08:06:50.62#ibcon#about to write, iclass 11, count 0 2006.238.08:06:50.62#ibcon#wrote, iclass 11, count 0 2006.238.08:06:50.62#ibcon#about to read 3, iclass 11, count 0 2006.238.08:06:50.66#ibcon#read 3, iclass 11, count 0 2006.238.08:06:50.66#ibcon#about to read 4, iclass 11, count 0 2006.238.08:06:50.66#ibcon#read 4, iclass 11, count 0 2006.238.08:06:50.66#ibcon#about to read 5, iclass 11, count 0 2006.238.08:06:50.66#ibcon#read 5, iclass 11, count 0 2006.238.08:06:50.66#ibcon#about to read 6, iclass 11, count 0 2006.238.08:06:50.66#ibcon#read 6, iclass 11, count 0 2006.238.08:06:50.66#ibcon#end of sib2, iclass 11, count 0 2006.238.08:06:50.66#ibcon#*after write, iclass 11, count 0 2006.238.08:06:50.66#ibcon#*before return 0, iclass 11, count 0 2006.238.08:06:50.66#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:06:50.66#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:06:50.66#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:06:50.66#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:06:50.66$vc4f8/vb=4,4 2006.238.08:06:50.66#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.08:06:50.66#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.08:06:50.66#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:50.66#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:06:50.72#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:06:50.72#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:06:50.72#ibcon#enter wrdev, iclass 13, count 2 2006.238.08:06:50.72#ibcon#first serial, iclass 13, count 2 2006.238.08:06:50.72#ibcon#enter sib2, iclass 13, count 2 2006.238.08:06:50.72#ibcon#flushed, iclass 13, count 2 2006.238.08:06:50.72#ibcon#about to write, iclass 13, count 2 2006.238.08:06:50.72#ibcon#wrote, iclass 13, count 2 2006.238.08:06:50.72#ibcon#about to read 3, iclass 13, count 2 2006.238.08:06:50.74#ibcon#read 3, iclass 13, count 2 2006.238.08:06:50.74#ibcon#about to read 4, iclass 13, count 2 2006.238.08:06:50.74#ibcon#read 4, iclass 13, count 2 2006.238.08:06:50.74#ibcon#about to read 5, iclass 13, count 2 2006.238.08:06:50.74#ibcon#read 5, iclass 13, count 2 2006.238.08:06:50.74#ibcon#about to read 6, iclass 13, count 2 2006.238.08:06:50.74#ibcon#read 6, iclass 13, count 2 2006.238.08:06:50.74#ibcon#end of sib2, iclass 13, count 2 2006.238.08:06:50.74#ibcon#*mode == 0, iclass 13, count 2 2006.238.08:06:50.74#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.08:06:50.74#ibcon#[27=AT04-04\r\n] 2006.238.08:06:50.74#ibcon#*before write, iclass 13, count 2 2006.238.08:06:50.74#ibcon#enter sib2, iclass 13, count 2 2006.238.08:06:50.74#ibcon#flushed, iclass 13, count 2 2006.238.08:06:50.74#ibcon#about to write, iclass 13, count 2 2006.238.08:06:50.74#ibcon#wrote, iclass 13, count 2 2006.238.08:06:50.74#ibcon#about to read 3, iclass 13, count 2 2006.238.08:06:50.77#ibcon#read 3, iclass 13, count 2 2006.238.08:06:50.77#ibcon#about to read 4, iclass 13, count 2 2006.238.08:06:50.77#ibcon#read 4, iclass 13, count 2 2006.238.08:06:50.77#ibcon#about to read 5, iclass 13, count 2 2006.238.08:06:50.77#ibcon#read 5, iclass 13, count 2 2006.238.08:06:50.77#ibcon#about to read 6, iclass 13, count 2 2006.238.08:06:50.77#ibcon#read 6, iclass 13, count 2 2006.238.08:06:50.77#ibcon#end of sib2, iclass 13, count 2 2006.238.08:06:50.77#ibcon#*after write, iclass 13, count 2 2006.238.08:06:50.77#ibcon#*before return 0, iclass 13, count 2 2006.238.08:06:50.77#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:06:50.77#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:06:50.77#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.08:06:50.77#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:50.77#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:06:50.89#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:06:50.89#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:06:50.89#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:06:50.89#ibcon#first serial, iclass 13, count 0 2006.238.08:06:50.89#ibcon#enter sib2, iclass 13, count 0 2006.238.08:06:50.89#ibcon#flushed, iclass 13, count 0 2006.238.08:06:50.89#ibcon#about to write, iclass 13, count 0 2006.238.08:06:50.89#ibcon#wrote, iclass 13, count 0 2006.238.08:06:50.89#ibcon#about to read 3, iclass 13, count 0 2006.238.08:06:50.91#ibcon#read 3, iclass 13, count 0 2006.238.08:06:50.91#ibcon#about to read 4, iclass 13, count 0 2006.238.08:06:50.91#ibcon#read 4, iclass 13, count 0 2006.238.08:06:50.91#ibcon#about to read 5, iclass 13, count 0 2006.238.08:06:50.91#ibcon#read 5, iclass 13, count 0 2006.238.08:06:50.91#ibcon#about to read 6, iclass 13, count 0 2006.238.08:06:50.91#ibcon#read 6, iclass 13, count 0 2006.238.08:06:50.91#ibcon#end of sib2, iclass 13, count 0 2006.238.08:06:50.91#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:06:50.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:06:50.91#ibcon#[27=USB\r\n] 2006.238.08:06:50.91#ibcon#*before write, iclass 13, count 0 2006.238.08:06:50.91#ibcon#enter sib2, iclass 13, count 0 2006.238.08:06:50.91#ibcon#flushed, iclass 13, count 0 2006.238.08:06:50.91#ibcon#about to write, iclass 13, count 0 2006.238.08:06:50.91#ibcon#wrote, iclass 13, count 0 2006.238.08:06:50.91#ibcon#about to read 3, iclass 13, count 0 2006.238.08:06:50.94#ibcon#read 3, iclass 13, count 0 2006.238.08:06:50.94#ibcon#about to read 4, iclass 13, count 0 2006.238.08:06:50.94#ibcon#read 4, iclass 13, count 0 2006.238.08:06:50.94#ibcon#about to read 5, iclass 13, count 0 2006.238.08:06:50.94#ibcon#read 5, iclass 13, count 0 2006.238.08:06:50.94#ibcon#about to read 6, iclass 13, count 0 2006.238.08:06:50.94#ibcon#read 6, iclass 13, count 0 2006.238.08:06:50.94#ibcon#end of sib2, iclass 13, count 0 2006.238.08:06:50.94#ibcon#*after write, iclass 13, count 0 2006.238.08:06:50.94#ibcon#*before return 0, iclass 13, count 0 2006.238.08:06:50.94#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:06:50.94#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:06:50.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:06:50.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:06:50.94$vc4f8/vblo=5,744.99 2006.238.08:06:50.94#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.08:06:50.94#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.08:06:50.94#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:50.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:06:50.94#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:06:50.94#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:06:50.94#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:06:50.94#ibcon#first serial, iclass 15, count 0 2006.238.08:06:50.94#ibcon#enter sib2, iclass 15, count 0 2006.238.08:06:50.94#ibcon#flushed, iclass 15, count 0 2006.238.08:06:50.94#ibcon#about to write, iclass 15, count 0 2006.238.08:06:50.94#ibcon#wrote, iclass 15, count 0 2006.238.08:06:50.94#ibcon#about to read 3, iclass 15, count 0 2006.238.08:06:50.96#ibcon#read 3, iclass 15, count 0 2006.238.08:06:50.96#ibcon#about to read 4, iclass 15, count 0 2006.238.08:06:50.96#ibcon#read 4, iclass 15, count 0 2006.238.08:06:50.96#ibcon#about to read 5, iclass 15, count 0 2006.238.08:06:50.96#ibcon#read 5, iclass 15, count 0 2006.238.08:06:50.96#ibcon#about to read 6, iclass 15, count 0 2006.238.08:06:50.96#ibcon#read 6, iclass 15, count 0 2006.238.08:06:50.96#ibcon#end of sib2, iclass 15, count 0 2006.238.08:06:50.96#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:06:50.96#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:06:50.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:06:50.96#ibcon#*before write, iclass 15, count 0 2006.238.08:06:50.96#ibcon#enter sib2, iclass 15, count 0 2006.238.08:06:50.96#ibcon#flushed, iclass 15, count 0 2006.238.08:06:50.96#ibcon#about to write, iclass 15, count 0 2006.238.08:06:50.96#ibcon#wrote, iclass 15, count 0 2006.238.08:06:50.96#ibcon#about to read 3, iclass 15, count 0 2006.238.08:06:51.00#ibcon#read 3, iclass 15, count 0 2006.238.08:06:51.00#ibcon#about to read 4, iclass 15, count 0 2006.238.08:06:51.00#ibcon#read 4, iclass 15, count 0 2006.238.08:06:51.00#ibcon#about to read 5, iclass 15, count 0 2006.238.08:06:51.00#ibcon#read 5, iclass 15, count 0 2006.238.08:06:51.00#ibcon#about to read 6, iclass 15, count 0 2006.238.08:06:51.00#ibcon#read 6, iclass 15, count 0 2006.238.08:06:51.00#ibcon#end of sib2, iclass 15, count 0 2006.238.08:06:51.00#ibcon#*after write, iclass 15, count 0 2006.238.08:06:51.00#ibcon#*before return 0, iclass 15, count 0 2006.238.08:06:51.00#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:06:51.00#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:06:51.00#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:06:51.00#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:06:51.00$vc4f8/vb=5,4 2006.238.08:06:51.00#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.08:06:51.00#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.08:06:51.00#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:51.00#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:06:51.06#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:06:51.06#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:06:51.06#ibcon#enter wrdev, iclass 17, count 2 2006.238.08:06:51.06#ibcon#first serial, iclass 17, count 2 2006.238.08:06:51.06#ibcon#enter sib2, iclass 17, count 2 2006.238.08:06:51.06#ibcon#flushed, iclass 17, count 2 2006.238.08:06:51.06#ibcon#about to write, iclass 17, count 2 2006.238.08:06:51.06#ibcon#wrote, iclass 17, count 2 2006.238.08:06:51.06#ibcon#about to read 3, iclass 17, count 2 2006.238.08:06:51.08#ibcon#read 3, iclass 17, count 2 2006.238.08:06:51.08#ibcon#about to read 4, iclass 17, count 2 2006.238.08:06:51.08#ibcon#read 4, iclass 17, count 2 2006.238.08:06:51.08#ibcon#about to read 5, iclass 17, count 2 2006.238.08:06:51.08#ibcon#read 5, iclass 17, count 2 2006.238.08:06:51.08#ibcon#about to read 6, iclass 17, count 2 2006.238.08:06:51.08#ibcon#read 6, iclass 17, count 2 2006.238.08:06:51.08#ibcon#end of sib2, iclass 17, count 2 2006.238.08:06:51.08#ibcon#*mode == 0, iclass 17, count 2 2006.238.08:06:51.08#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.08:06:51.08#ibcon#[27=AT05-04\r\n] 2006.238.08:06:51.08#ibcon#*before write, iclass 17, count 2 2006.238.08:06:51.08#ibcon#enter sib2, iclass 17, count 2 2006.238.08:06:51.08#ibcon#flushed, iclass 17, count 2 2006.238.08:06:51.08#ibcon#about to write, iclass 17, count 2 2006.238.08:06:51.08#ibcon#wrote, iclass 17, count 2 2006.238.08:06:51.08#ibcon#about to read 3, iclass 17, count 2 2006.238.08:06:51.11#ibcon#read 3, iclass 17, count 2 2006.238.08:06:51.11#ibcon#about to read 4, iclass 17, count 2 2006.238.08:06:51.11#ibcon#read 4, iclass 17, count 2 2006.238.08:06:51.11#ibcon#about to read 5, iclass 17, count 2 2006.238.08:06:51.11#ibcon#read 5, iclass 17, count 2 2006.238.08:06:51.11#ibcon#about to read 6, iclass 17, count 2 2006.238.08:06:51.11#ibcon#read 6, iclass 17, count 2 2006.238.08:06:51.11#ibcon#end of sib2, iclass 17, count 2 2006.238.08:06:51.11#ibcon#*after write, iclass 17, count 2 2006.238.08:06:51.11#ibcon#*before return 0, iclass 17, count 2 2006.238.08:06:51.11#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:06:51.11#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:06:51.11#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.08:06:51.11#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:51.11#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:06:51.23#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:06:51.23#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:06:51.23#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:06:51.23#ibcon#first serial, iclass 17, count 0 2006.238.08:06:51.23#ibcon#enter sib2, iclass 17, count 0 2006.238.08:06:51.23#ibcon#flushed, iclass 17, count 0 2006.238.08:06:51.23#ibcon#about to write, iclass 17, count 0 2006.238.08:06:51.23#ibcon#wrote, iclass 17, count 0 2006.238.08:06:51.23#ibcon#about to read 3, iclass 17, count 0 2006.238.08:06:51.25#ibcon#read 3, iclass 17, count 0 2006.238.08:06:51.25#ibcon#about to read 4, iclass 17, count 0 2006.238.08:06:51.25#ibcon#read 4, iclass 17, count 0 2006.238.08:06:51.25#ibcon#about to read 5, iclass 17, count 0 2006.238.08:06:51.25#ibcon#read 5, iclass 17, count 0 2006.238.08:06:51.25#ibcon#about to read 6, iclass 17, count 0 2006.238.08:06:51.25#ibcon#read 6, iclass 17, count 0 2006.238.08:06:51.25#ibcon#end of sib2, iclass 17, count 0 2006.238.08:06:51.25#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:06:51.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:06:51.25#ibcon#[27=USB\r\n] 2006.238.08:06:51.25#ibcon#*before write, iclass 17, count 0 2006.238.08:06:51.25#ibcon#enter sib2, iclass 17, count 0 2006.238.08:06:51.25#ibcon#flushed, iclass 17, count 0 2006.238.08:06:51.25#ibcon#about to write, iclass 17, count 0 2006.238.08:06:51.25#ibcon#wrote, iclass 17, count 0 2006.238.08:06:51.25#ibcon#about to read 3, iclass 17, count 0 2006.238.08:06:51.28#ibcon#read 3, iclass 17, count 0 2006.238.08:06:51.28#ibcon#about to read 4, iclass 17, count 0 2006.238.08:06:51.28#ibcon#read 4, iclass 17, count 0 2006.238.08:06:51.28#ibcon#about to read 5, iclass 17, count 0 2006.238.08:06:51.28#ibcon#read 5, iclass 17, count 0 2006.238.08:06:51.28#ibcon#about to read 6, iclass 17, count 0 2006.238.08:06:51.28#ibcon#read 6, iclass 17, count 0 2006.238.08:06:51.28#ibcon#end of sib2, iclass 17, count 0 2006.238.08:06:51.28#ibcon#*after write, iclass 17, count 0 2006.238.08:06:51.28#ibcon#*before return 0, iclass 17, count 0 2006.238.08:06:51.28#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:06:51.28#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:06:51.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:06:51.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:06:51.28$vc4f8/vblo=6,752.99 2006.238.08:06:51.28#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.08:06:51.28#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.08:06:51.28#ibcon#ireg 17 cls_cnt 0 2006.238.08:06:51.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:06:51.28#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:06:51.28#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:06:51.28#ibcon#enter wrdev, iclass 19, count 0 2006.238.08:06:51.28#ibcon#first serial, iclass 19, count 0 2006.238.08:06:51.28#ibcon#enter sib2, iclass 19, count 0 2006.238.08:06:51.28#ibcon#flushed, iclass 19, count 0 2006.238.08:06:51.28#ibcon#about to write, iclass 19, count 0 2006.238.08:06:51.28#ibcon#wrote, iclass 19, count 0 2006.238.08:06:51.28#ibcon#about to read 3, iclass 19, count 0 2006.238.08:06:51.30#ibcon#read 3, iclass 19, count 0 2006.238.08:06:51.30#ibcon#about to read 4, iclass 19, count 0 2006.238.08:06:51.30#ibcon#read 4, iclass 19, count 0 2006.238.08:06:51.30#ibcon#about to read 5, iclass 19, count 0 2006.238.08:06:51.30#ibcon#read 5, iclass 19, count 0 2006.238.08:06:51.30#ibcon#about to read 6, iclass 19, count 0 2006.238.08:06:51.30#ibcon#read 6, iclass 19, count 0 2006.238.08:06:51.30#ibcon#end of sib2, iclass 19, count 0 2006.238.08:06:51.30#ibcon#*mode == 0, iclass 19, count 0 2006.238.08:06:51.30#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.08:06:51.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:06:51.30#ibcon#*before write, iclass 19, count 0 2006.238.08:06:51.30#ibcon#enter sib2, iclass 19, count 0 2006.238.08:06:51.30#ibcon#flushed, iclass 19, count 0 2006.238.08:06:51.30#ibcon#about to write, iclass 19, count 0 2006.238.08:06:51.30#ibcon#wrote, iclass 19, count 0 2006.238.08:06:51.30#ibcon#about to read 3, iclass 19, count 0 2006.238.08:06:51.34#ibcon#read 3, iclass 19, count 0 2006.238.08:06:51.34#ibcon#about to read 4, iclass 19, count 0 2006.238.08:06:51.34#ibcon#read 4, iclass 19, count 0 2006.238.08:06:51.34#ibcon#about to read 5, iclass 19, count 0 2006.238.08:06:51.34#ibcon#read 5, iclass 19, count 0 2006.238.08:06:51.34#ibcon#about to read 6, iclass 19, count 0 2006.238.08:06:51.34#ibcon#read 6, iclass 19, count 0 2006.238.08:06:51.34#ibcon#end of sib2, iclass 19, count 0 2006.238.08:06:51.34#ibcon#*after write, iclass 19, count 0 2006.238.08:06:51.34#ibcon#*before return 0, iclass 19, count 0 2006.238.08:06:51.34#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:06:51.34#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:06:51.34#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.08:06:51.34#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.08:06:51.34$vc4f8/vb=6,4 2006.238.08:06:51.34#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.08:06:51.34#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.08:06:51.34#ibcon#ireg 11 cls_cnt 2 2006.238.08:06:51.34#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:06:51.40#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:06:51.40#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:06:51.40#ibcon#enter wrdev, iclass 21, count 2 2006.238.08:06:51.40#ibcon#first serial, iclass 21, count 2 2006.238.08:06:51.40#ibcon#enter sib2, iclass 21, count 2 2006.238.08:06:51.40#ibcon#flushed, iclass 21, count 2 2006.238.08:06:51.40#ibcon#about to write, iclass 21, count 2 2006.238.08:06:51.40#ibcon#wrote, iclass 21, count 2 2006.238.08:06:51.40#ibcon#about to read 3, iclass 21, count 2 2006.238.08:06:51.42#ibcon#read 3, iclass 21, count 2 2006.238.08:06:51.42#ibcon#about to read 4, iclass 21, count 2 2006.238.08:06:51.42#ibcon#read 4, iclass 21, count 2 2006.238.08:06:51.42#ibcon#about to read 5, iclass 21, count 2 2006.238.08:06:51.42#ibcon#read 5, iclass 21, count 2 2006.238.08:06:51.42#ibcon#about to read 6, iclass 21, count 2 2006.238.08:06:51.42#ibcon#read 6, iclass 21, count 2 2006.238.08:06:51.42#ibcon#end of sib2, iclass 21, count 2 2006.238.08:06:51.42#ibcon#*mode == 0, iclass 21, count 2 2006.238.08:06:51.42#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.08:06:51.42#ibcon#[27=AT06-04\r\n] 2006.238.08:06:51.42#ibcon#*before write, iclass 21, count 2 2006.238.08:06:51.42#ibcon#enter sib2, iclass 21, count 2 2006.238.08:06:51.42#ibcon#flushed, iclass 21, count 2 2006.238.08:06:51.42#ibcon#about to write, iclass 21, count 2 2006.238.08:06:51.42#ibcon#wrote, iclass 21, count 2 2006.238.08:06:51.42#ibcon#about to read 3, iclass 21, count 2 2006.238.08:06:51.45#ibcon#read 3, iclass 21, count 2 2006.238.08:06:51.45#ibcon#about to read 4, iclass 21, count 2 2006.238.08:06:51.45#ibcon#read 4, iclass 21, count 2 2006.238.08:06:51.45#ibcon#about to read 5, iclass 21, count 2 2006.238.08:06:51.45#ibcon#read 5, iclass 21, count 2 2006.238.08:06:51.45#ibcon#about to read 6, iclass 21, count 2 2006.238.08:06:51.45#ibcon#read 6, iclass 21, count 2 2006.238.08:06:51.45#ibcon#end of sib2, iclass 21, count 2 2006.238.08:06:51.45#ibcon#*after write, iclass 21, count 2 2006.238.08:06:51.45#ibcon#*before return 0, iclass 21, count 2 2006.238.08:06:51.45#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:06:51.45#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:06:51.45#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.08:06:51.45#ibcon#ireg 7 cls_cnt 0 2006.238.08:06:51.45#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:06:51.57#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:06:51.57#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:06:51.57#ibcon#enter wrdev, iclass 21, count 0 2006.238.08:06:51.57#ibcon#first serial, iclass 21, count 0 2006.238.08:06:51.57#ibcon#enter sib2, iclass 21, count 0 2006.238.08:06:51.57#ibcon#flushed, iclass 21, count 0 2006.238.08:06:51.57#ibcon#about to write, iclass 21, count 0 2006.238.08:06:51.57#ibcon#wrote, iclass 21, count 0 2006.238.08:06:51.57#ibcon#about to read 3, iclass 21, count 0 2006.238.08:06:51.59#ibcon#read 3, iclass 21, count 0 2006.238.08:06:51.59#ibcon#about to read 4, iclass 21, count 0 2006.238.08:06:51.59#ibcon#read 4, iclass 21, count 0 2006.238.08:06:51.59#ibcon#about to read 5, iclass 21, count 0 2006.238.08:06:51.59#ibcon#read 5, iclass 21, count 0 2006.238.08:06:51.59#ibcon#about to read 6, iclass 21, count 0 2006.238.08:06:51.59#ibcon#read 6, iclass 21, count 0 2006.238.08:06:51.59#ibcon#end of sib2, iclass 21, count 0 2006.238.08:06:51.59#ibcon#*mode == 0, iclass 21, count 0 2006.238.08:06:51.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.08:06:51.59#ibcon#[27=USB\r\n] 2006.238.08:06:51.59#ibcon#*before write, iclass 21, count 0 2006.238.08:06:51.59#ibcon#enter sib2, iclass 21, count 0 2006.238.08:06:51.59#ibcon#flushed, iclass 21, count 0 2006.238.08:06:51.59#ibcon#about to write, iclass 21, count 0 2006.238.08:06:51.59#ibcon#wrote, iclass 21, count 0 2006.238.08:06:51.59#ibcon#about to read 3, iclass 21, count 0 2006.238.08:06:51.62#ibcon#read 3, iclass 21, count 0 2006.238.08:06:51.62#ibcon#about to read 4, iclass 21, count 0 2006.238.08:06:51.62#ibcon#read 4, iclass 21, count 0 2006.238.08:06:51.62#ibcon#about to read 5, iclass 21, count 0 2006.238.08:06:51.62#ibcon#read 5, iclass 21, count 0 2006.238.08:06:51.62#ibcon#about to read 6, iclass 21, count 0 2006.238.08:06:51.62#ibcon#read 6, iclass 21, count 0 2006.238.08:06:51.62#ibcon#end of sib2, iclass 21, count 0 2006.238.08:06:51.62#ibcon#*after write, iclass 21, count 0 2006.238.08:06:51.62#ibcon#*before return 0, iclass 21, count 0 2006.238.08:06:51.62#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:06:51.62#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:06:51.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.08:06:51.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.08:06:51.62$vc4f8/vabw=wide 2006.238.08:06:51.62#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.08:06:51.62#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.08:06:51.62#ibcon#ireg 8 cls_cnt 0 2006.238.08:06:51.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:06:51.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:06:51.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:06:51.62#ibcon#enter wrdev, iclass 23, count 0 2006.238.08:06:51.62#ibcon#first serial, iclass 23, count 0 2006.238.08:06:51.62#ibcon#enter sib2, iclass 23, count 0 2006.238.08:06:51.62#ibcon#flushed, iclass 23, count 0 2006.238.08:06:51.62#ibcon#about to write, iclass 23, count 0 2006.238.08:06:51.62#ibcon#wrote, iclass 23, count 0 2006.238.08:06:51.62#ibcon#about to read 3, iclass 23, count 0 2006.238.08:06:51.64#ibcon#read 3, iclass 23, count 0 2006.238.08:06:51.64#ibcon#about to read 4, iclass 23, count 0 2006.238.08:06:51.64#ibcon#read 4, iclass 23, count 0 2006.238.08:06:51.64#ibcon#about to read 5, iclass 23, count 0 2006.238.08:06:51.64#ibcon#read 5, iclass 23, count 0 2006.238.08:06:51.64#ibcon#about to read 6, iclass 23, count 0 2006.238.08:06:51.64#ibcon#read 6, iclass 23, count 0 2006.238.08:06:51.64#ibcon#end of sib2, iclass 23, count 0 2006.238.08:06:51.64#ibcon#*mode == 0, iclass 23, count 0 2006.238.08:06:51.64#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.08:06:51.64#ibcon#[25=BW32\r\n] 2006.238.08:06:51.64#ibcon#*before write, iclass 23, count 0 2006.238.08:06:51.64#ibcon#enter sib2, iclass 23, count 0 2006.238.08:06:51.64#ibcon#flushed, iclass 23, count 0 2006.238.08:06:51.64#ibcon#about to write, iclass 23, count 0 2006.238.08:06:51.64#ibcon#wrote, iclass 23, count 0 2006.238.08:06:51.64#ibcon#about to read 3, iclass 23, count 0 2006.238.08:06:51.67#ibcon#read 3, iclass 23, count 0 2006.238.08:06:51.67#ibcon#about to read 4, iclass 23, count 0 2006.238.08:06:51.67#ibcon#read 4, iclass 23, count 0 2006.238.08:06:51.67#ibcon#about to read 5, iclass 23, count 0 2006.238.08:06:51.67#ibcon#read 5, iclass 23, count 0 2006.238.08:06:51.67#ibcon#about to read 6, iclass 23, count 0 2006.238.08:06:51.67#ibcon#read 6, iclass 23, count 0 2006.238.08:06:51.67#ibcon#end of sib2, iclass 23, count 0 2006.238.08:06:51.67#ibcon#*after write, iclass 23, count 0 2006.238.08:06:51.67#ibcon#*before return 0, iclass 23, count 0 2006.238.08:06:51.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:06:51.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:06:51.67#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.08:06:51.67#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.08:06:51.67$vc4f8/vbbw=wide 2006.238.08:06:51.67#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.08:06:51.67#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.08:06:51.67#ibcon#ireg 8 cls_cnt 0 2006.238.08:06:51.67#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:06:51.74#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:06:51.74#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:06:51.74#ibcon#enter wrdev, iclass 25, count 0 2006.238.08:06:51.74#ibcon#first serial, iclass 25, count 0 2006.238.08:06:51.74#ibcon#enter sib2, iclass 25, count 0 2006.238.08:06:51.74#ibcon#flushed, iclass 25, count 0 2006.238.08:06:51.74#ibcon#about to write, iclass 25, count 0 2006.238.08:06:51.74#ibcon#wrote, iclass 25, count 0 2006.238.08:06:51.74#ibcon#about to read 3, iclass 25, count 0 2006.238.08:06:51.76#ibcon#read 3, iclass 25, count 0 2006.238.08:06:51.76#ibcon#about to read 4, iclass 25, count 0 2006.238.08:06:51.76#ibcon#read 4, iclass 25, count 0 2006.238.08:06:51.76#ibcon#about to read 5, iclass 25, count 0 2006.238.08:06:51.76#ibcon#read 5, iclass 25, count 0 2006.238.08:06:51.76#ibcon#about to read 6, iclass 25, count 0 2006.238.08:06:51.76#ibcon#read 6, iclass 25, count 0 2006.238.08:06:51.76#ibcon#end of sib2, iclass 25, count 0 2006.238.08:06:51.76#ibcon#*mode == 0, iclass 25, count 0 2006.238.08:06:51.76#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.08:06:51.76#ibcon#[27=BW32\r\n] 2006.238.08:06:51.76#ibcon#*before write, iclass 25, count 0 2006.238.08:06:51.76#ibcon#enter sib2, iclass 25, count 0 2006.238.08:06:51.76#ibcon#flushed, iclass 25, count 0 2006.238.08:06:51.76#ibcon#about to write, iclass 25, count 0 2006.238.08:06:51.76#ibcon#wrote, iclass 25, count 0 2006.238.08:06:51.76#ibcon#about to read 3, iclass 25, count 0 2006.238.08:06:51.79#ibcon#read 3, iclass 25, count 0 2006.238.08:06:51.79#ibcon#about to read 4, iclass 25, count 0 2006.238.08:06:51.79#ibcon#read 4, iclass 25, count 0 2006.238.08:06:51.79#ibcon#about to read 5, iclass 25, count 0 2006.238.08:06:51.79#ibcon#read 5, iclass 25, count 0 2006.238.08:06:51.79#ibcon#about to read 6, iclass 25, count 0 2006.238.08:06:51.79#ibcon#read 6, iclass 25, count 0 2006.238.08:06:51.79#ibcon#end of sib2, iclass 25, count 0 2006.238.08:06:51.79#ibcon#*after write, iclass 25, count 0 2006.238.08:06:51.79#ibcon#*before return 0, iclass 25, count 0 2006.238.08:06:51.79#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:06:51.79#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:06:51.79#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.08:06:51.79#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.08:06:51.79$4f8m12a/ifd4f 2006.238.08:06:51.79$ifd4f/lo= 2006.238.08:06:51.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:06:51.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:06:51.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:06:51.79$ifd4f/patch= 2006.238.08:06:51.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:06:51.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:06:51.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:06:51.79$4f8m12a/"form=m,16.000,1:2 2006.238.08:06:51.79$4f8m12a/"tpicd 2006.238.08:06:51.79$4f8m12a/echo=off 2006.238.08:06:51.79$4f8m12a/xlog=off 2006.238.08:06:51.79:!2006.238.08:07:20 2006.238.08:07:01.14#trakl#Source acquired 2006.238.08:07:01.14#flagr#flagr/antenna,acquired 2006.238.08:07:20.00:preob 2006.238.08:07:20.13/onsource/TRACKING 2006.238.08:07:20.13:!2006.238.08:07:30 2006.238.08:07:30.00:data_valid=on 2006.238.08:07:30.00:midob 2006.238.08:07:31.13/onsource/TRACKING 2006.238.08:07:31.13/wx/25.46,1012.1,89 2006.238.08:07:31.19/cable/+6.4169E-03 2006.238.08:07:32.28/va/01,08,usb,yes,32,33 2006.238.08:07:32.28/va/02,07,usb,yes,32,33 2006.238.08:07:32.28/va/03,07,usb,yes,30,30 2006.238.08:07:32.28/va/04,07,usb,yes,33,36 2006.238.08:07:32.28/va/05,08,usb,yes,30,31 2006.238.08:07:32.28/va/06,07,usb,yes,32,32 2006.238.08:07:32.28/va/07,07,usb,yes,33,32 2006.238.08:07:32.28/va/08,07,usb,yes,35,35 2006.238.08:07:32.51/valo/01,532.99,yes,locked 2006.238.08:07:32.51/valo/02,572.99,yes,locked 2006.238.08:07:32.51/valo/03,672.99,yes,locked 2006.238.08:07:32.51/valo/04,832.99,yes,locked 2006.238.08:07:32.51/valo/05,652.99,yes,locked 2006.238.08:07:32.51/valo/06,772.99,yes,locked 2006.238.08:07:32.51/valo/07,832.99,yes,locked 2006.238.08:07:32.51/valo/08,852.99,yes,locked 2006.238.08:07:33.60/vb/01,04,usb,yes,30,29 2006.238.08:07:33.60/vb/02,04,usb,yes,32,34 2006.238.08:07:33.60/vb/03,04,usb,yes,29,32 2006.238.08:07:33.60/vb/04,04,usb,yes,29,30 2006.238.08:07:33.60/vb/05,04,usb,yes,28,32 2006.238.08:07:33.60/vb/06,04,usb,yes,29,32 2006.238.08:07:33.60/vb/07,04,usb,yes,31,31 2006.238.08:07:33.60/vb/08,04,usb,yes,28,32 2006.238.08:07:33.83/vblo/01,632.99,yes,locked 2006.238.08:07:33.83/vblo/02,640.99,yes,locked 2006.238.08:07:33.83/vblo/03,656.99,yes,locked 2006.238.08:07:33.83/vblo/04,712.99,yes,locked 2006.238.08:07:33.83/vblo/05,744.99,yes,locked 2006.238.08:07:33.83/vblo/06,752.99,yes,locked 2006.238.08:07:33.83/vblo/07,734.99,yes,locked 2006.238.08:07:33.83/vblo/08,744.99,yes,locked 2006.238.08:07:33.98/vabw/8 2006.238.08:07:34.13/vbbw/8 2006.238.08:07:34.22/xfe/off,on,13.5 2006.238.08:07:34.59/ifatt/23,28,28,28 2006.238.08:07:35.07/fmout-gps/S +4.34E-07 2006.238.08:07:35.11:!2006.238.08:08:30 2006.238.08:08:30.01:data_valid=off 2006.238.08:08:30.02:postob 2006.238.08:08:30.25/cable/+6.4170E-03 2006.238.08:08:30.26/wx/25.47,1012.2,89 2006.238.08:08:31.08/fmout-gps/S +4.35E-07 2006.238.08:08:31.09:scan_name=238-0809,k06238,60 2006.238.08:08:31.09:source=3c371,180650.68,694928.1,2000.0,cw 2006.238.08:08:31.13#flagr#flagr/antenna,new-source 2006.238.08:08:32.13:checkk5 2006.238.08:08:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:08:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:08:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:08:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:08:34.01/chk_obsdata//k5ts1/T2380807??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:08:34.38/chk_obsdata//k5ts2/T2380807??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:08:34.74/chk_obsdata//k5ts3/T2380807??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:08:35.12/chk_obsdata//k5ts4/T2380807??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:08:35.81/k5log//k5ts1_log_newline 2006.238.08:08:36.51/k5log//k5ts2_log_newline 2006.238.08:08:37.20/k5log//k5ts3_log_newline 2006.238.08:08:37.88/k5log//k5ts4_log_newline 2006.238.08:08:37.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:08:37.91:4f8m12a=2 2006.238.08:08:37.91$4f8m12a/echo=on 2006.238.08:08:37.91$4f8m12a/pcalon 2006.238.08:08:37.91$pcalon/"no phase cal control is implemented here 2006.238.08:08:37.91$4f8m12a/"tpicd=stop 2006.238.08:08:37.91$4f8m12a/vc4f8 2006.238.08:08:37.91$vc4f8/valo=1,532.99 2006.238.08:08:37.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.08:08:37.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.08:08:37.91#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:37.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:08:37.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:08:37.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:08:37.91#ibcon#enter wrdev, iclass 36, count 0 2006.238.08:08:37.91#ibcon#first serial, iclass 36, count 0 2006.238.08:08:37.91#ibcon#enter sib2, iclass 36, count 0 2006.238.08:08:37.91#ibcon#flushed, iclass 36, count 0 2006.238.08:08:37.91#ibcon#about to write, iclass 36, count 0 2006.238.08:08:37.91#ibcon#wrote, iclass 36, count 0 2006.238.08:08:37.91#ibcon#about to read 3, iclass 36, count 0 2006.238.08:08:37.96#ibcon#read 3, iclass 36, count 0 2006.238.08:08:37.96#ibcon#about to read 4, iclass 36, count 0 2006.238.08:08:37.96#ibcon#read 4, iclass 36, count 0 2006.238.08:08:37.96#ibcon#about to read 5, iclass 36, count 0 2006.238.08:08:37.96#ibcon#read 5, iclass 36, count 0 2006.238.08:08:37.96#ibcon#about to read 6, iclass 36, count 0 2006.238.08:08:37.96#ibcon#read 6, iclass 36, count 0 2006.238.08:08:37.96#ibcon#end of sib2, iclass 36, count 0 2006.238.08:08:37.96#ibcon#*mode == 0, iclass 36, count 0 2006.238.08:08:37.96#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.08:08:37.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:08:37.96#ibcon#*before write, iclass 36, count 0 2006.238.08:08:37.96#ibcon#enter sib2, iclass 36, count 0 2006.238.08:08:37.96#ibcon#flushed, iclass 36, count 0 2006.238.08:08:37.96#ibcon#about to write, iclass 36, count 0 2006.238.08:08:37.96#ibcon#wrote, iclass 36, count 0 2006.238.08:08:37.96#ibcon#about to read 3, iclass 36, count 0 2006.238.08:08:38.00#ibcon#read 3, iclass 36, count 0 2006.238.08:08:38.00#ibcon#about to read 4, iclass 36, count 0 2006.238.08:08:38.00#ibcon#read 4, iclass 36, count 0 2006.238.08:08:38.00#ibcon#about to read 5, iclass 36, count 0 2006.238.08:08:38.00#ibcon#read 5, iclass 36, count 0 2006.238.08:08:38.00#ibcon#about to read 6, iclass 36, count 0 2006.238.08:08:38.00#ibcon#read 6, iclass 36, count 0 2006.238.08:08:38.00#ibcon#end of sib2, iclass 36, count 0 2006.238.08:08:38.00#ibcon#*after write, iclass 36, count 0 2006.238.08:08:38.00#ibcon#*before return 0, iclass 36, count 0 2006.238.08:08:38.00#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:08:38.00#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:08:38.00#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.08:08:38.00#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.08:08:38.00$vc4f8/va=1,8 2006.238.08:08:38.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.238.08:08:38.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.238.08:08:38.00#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:38.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:08:38.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:08:38.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:08:38.00#ibcon#enter wrdev, iclass 38, count 2 2006.238.08:08:38.00#ibcon#first serial, iclass 38, count 2 2006.238.08:08:38.00#ibcon#enter sib2, iclass 38, count 2 2006.238.08:08:38.00#ibcon#flushed, iclass 38, count 2 2006.238.08:08:38.00#ibcon#about to write, iclass 38, count 2 2006.238.08:08:38.00#ibcon#wrote, iclass 38, count 2 2006.238.08:08:38.00#ibcon#about to read 3, iclass 38, count 2 2006.238.08:08:38.02#ibcon#read 3, iclass 38, count 2 2006.238.08:08:38.02#ibcon#about to read 4, iclass 38, count 2 2006.238.08:08:38.02#ibcon#read 4, iclass 38, count 2 2006.238.08:08:38.02#ibcon#about to read 5, iclass 38, count 2 2006.238.08:08:38.02#ibcon#read 5, iclass 38, count 2 2006.238.08:08:38.02#ibcon#about to read 6, iclass 38, count 2 2006.238.08:08:38.02#ibcon#read 6, iclass 38, count 2 2006.238.08:08:38.02#ibcon#end of sib2, iclass 38, count 2 2006.238.08:08:38.02#ibcon#*mode == 0, iclass 38, count 2 2006.238.08:08:38.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.238.08:08:38.02#ibcon#[25=AT01-08\r\n] 2006.238.08:08:38.02#ibcon#*before write, iclass 38, count 2 2006.238.08:08:38.02#ibcon#enter sib2, iclass 38, count 2 2006.238.08:08:38.02#ibcon#flushed, iclass 38, count 2 2006.238.08:08:38.02#ibcon#about to write, iclass 38, count 2 2006.238.08:08:38.02#ibcon#wrote, iclass 38, count 2 2006.238.08:08:38.02#ibcon#about to read 3, iclass 38, count 2 2006.238.08:08:38.05#ibcon#read 3, iclass 38, count 2 2006.238.08:08:38.05#ibcon#about to read 4, iclass 38, count 2 2006.238.08:08:38.05#ibcon#read 4, iclass 38, count 2 2006.238.08:08:38.05#ibcon#about to read 5, iclass 38, count 2 2006.238.08:08:38.05#ibcon#read 5, iclass 38, count 2 2006.238.08:08:38.05#ibcon#about to read 6, iclass 38, count 2 2006.238.08:08:38.05#ibcon#read 6, iclass 38, count 2 2006.238.08:08:38.05#ibcon#end of sib2, iclass 38, count 2 2006.238.08:08:38.05#ibcon#*after write, iclass 38, count 2 2006.238.08:08:38.05#ibcon#*before return 0, iclass 38, count 2 2006.238.08:08:38.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:08:38.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:08:38.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.238.08:08:38.05#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:38.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:08:38.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:08:38.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:08:38.17#ibcon#enter wrdev, iclass 38, count 0 2006.238.08:08:38.17#ibcon#first serial, iclass 38, count 0 2006.238.08:08:38.17#ibcon#enter sib2, iclass 38, count 0 2006.238.08:08:38.17#ibcon#flushed, iclass 38, count 0 2006.238.08:08:38.17#ibcon#about to write, iclass 38, count 0 2006.238.08:08:38.17#ibcon#wrote, iclass 38, count 0 2006.238.08:08:38.17#ibcon#about to read 3, iclass 38, count 0 2006.238.08:08:38.19#ibcon#read 3, iclass 38, count 0 2006.238.08:08:38.19#ibcon#about to read 4, iclass 38, count 0 2006.238.08:08:38.19#ibcon#read 4, iclass 38, count 0 2006.238.08:08:38.19#ibcon#about to read 5, iclass 38, count 0 2006.238.08:08:38.19#ibcon#read 5, iclass 38, count 0 2006.238.08:08:38.19#ibcon#about to read 6, iclass 38, count 0 2006.238.08:08:38.19#ibcon#read 6, iclass 38, count 0 2006.238.08:08:38.19#ibcon#end of sib2, iclass 38, count 0 2006.238.08:08:38.19#ibcon#*mode == 0, iclass 38, count 0 2006.238.08:08:38.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.08:08:38.19#ibcon#[25=USB\r\n] 2006.238.08:08:38.19#ibcon#*before write, iclass 38, count 0 2006.238.08:08:38.19#ibcon#enter sib2, iclass 38, count 0 2006.238.08:08:38.19#ibcon#flushed, iclass 38, count 0 2006.238.08:08:38.19#ibcon#about to write, iclass 38, count 0 2006.238.08:08:38.19#ibcon#wrote, iclass 38, count 0 2006.238.08:08:38.19#ibcon#about to read 3, iclass 38, count 0 2006.238.08:08:38.22#ibcon#read 3, iclass 38, count 0 2006.238.08:08:38.22#ibcon#about to read 4, iclass 38, count 0 2006.238.08:08:38.22#ibcon#read 4, iclass 38, count 0 2006.238.08:08:38.22#ibcon#about to read 5, iclass 38, count 0 2006.238.08:08:38.22#ibcon#read 5, iclass 38, count 0 2006.238.08:08:38.22#ibcon#about to read 6, iclass 38, count 0 2006.238.08:08:38.22#ibcon#read 6, iclass 38, count 0 2006.238.08:08:38.22#ibcon#end of sib2, iclass 38, count 0 2006.238.08:08:38.22#ibcon#*after write, iclass 38, count 0 2006.238.08:08:38.22#ibcon#*before return 0, iclass 38, count 0 2006.238.08:08:38.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:08:38.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:08:38.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.08:08:38.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.08:08:38.22$vc4f8/valo=2,572.99 2006.238.08:08:38.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.08:08:38.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.08:08:38.22#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:38.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:08:38.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:08:38.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:08:38.22#ibcon#enter wrdev, iclass 40, count 0 2006.238.08:08:38.22#ibcon#first serial, iclass 40, count 0 2006.238.08:08:38.22#ibcon#enter sib2, iclass 40, count 0 2006.238.08:08:38.22#ibcon#flushed, iclass 40, count 0 2006.238.08:08:38.22#ibcon#about to write, iclass 40, count 0 2006.238.08:08:38.22#ibcon#wrote, iclass 40, count 0 2006.238.08:08:38.22#ibcon#about to read 3, iclass 40, count 0 2006.238.08:08:38.24#ibcon#read 3, iclass 40, count 0 2006.238.08:08:38.24#ibcon#about to read 4, iclass 40, count 0 2006.238.08:08:38.24#ibcon#read 4, iclass 40, count 0 2006.238.08:08:38.24#ibcon#about to read 5, iclass 40, count 0 2006.238.08:08:38.24#ibcon#read 5, iclass 40, count 0 2006.238.08:08:38.24#ibcon#about to read 6, iclass 40, count 0 2006.238.08:08:38.24#ibcon#read 6, iclass 40, count 0 2006.238.08:08:38.24#ibcon#end of sib2, iclass 40, count 0 2006.238.08:08:38.24#ibcon#*mode == 0, iclass 40, count 0 2006.238.08:08:38.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.08:08:38.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:08:38.24#ibcon#*before write, iclass 40, count 0 2006.238.08:08:38.24#ibcon#enter sib2, iclass 40, count 0 2006.238.08:08:38.24#ibcon#flushed, iclass 40, count 0 2006.238.08:08:38.24#ibcon#about to write, iclass 40, count 0 2006.238.08:08:38.24#ibcon#wrote, iclass 40, count 0 2006.238.08:08:38.24#ibcon#about to read 3, iclass 40, count 0 2006.238.08:08:38.28#ibcon#read 3, iclass 40, count 0 2006.238.08:08:38.28#ibcon#about to read 4, iclass 40, count 0 2006.238.08:08:38.28#ibcon#read 4, iclass 40, count 0 2006.238.08:08:38.28#ibcon#about to read 5, iclass 40, count 0 2006.238.08:08:38.28#ibcon#read 5, iclass 40, count 0 2006.238.08:08:38.28#ibcon#about to read 6, iclass 40, count 0 2006.238.08:08:38.28#ibcon#read 6, iclass 40, count 0 2006.238.08:08:38.28#ibcon#end of sib2, iclass 40, count 0 2006.238.08:08:38.28#ibcon#*after write, iclass 40, count 0 2006.238.08:08:38.28#ibcon#*before return 0, iclass 40, count 0 2006.238.08:08:38.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:08:38.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:08:38.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.08:08:38.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.08:08:38.28$vc4f8/va=2,7 2006.238.08:08:38.28#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.238.08:08:38.28#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.238.08:08:38.28#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:38.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:08:38.35#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:08:38.35#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:08:38.35#ibcon#enter wrdev, iclass 4, count 2 2006.238.08:08:38.35#ibcon#first serial, iclass 4, count 2 2006.238.08:08:38.35#ibcon#enter sib2, iclass 4, count 2 2006.238.08:08:38.35#ibcon#flushed, iclass 4, count 2 2006.238.08:08:38.35#ibcon#about to write, iclass 4, count 2 2006.238.08:08:38.35#ibcon#wrote, iclass 4, count 2 2006.238.08:08:38.35#ibcon#about to read 3, iclass 4, count 2 2006.238.08:08:38.36#ibcon#read 3, iclass 4, count 2 2006.238.08:08:38.36#ibcon#about to read 4, iclass 4, count 2 2006.238.08:08:38.36#ibcon#read 4, iclass 4, count 2 2006.238.08:08:38.36#ibcon#about to read 5, iclass 4, count 2 2006.238.08:08:38.36#ibcon#read 5, iclass 4, count 2 2006.238.08:08:38.36#ibcon#about to read 6, iclass 4, count 2 2006.238.08:08:38.36#ibcon#read 6, iclass 4, count 2 2006.238.08:08:38.36#ibcon#end of sib2, iclass 4, count 2 2006.238.08:08:38.36#ibcon#*mode == 0, iclass 4, count 2 2006.238.08:08:38.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.238.08:08:38.36#ibcon#[25=AT02-07\r\n] 2006.238.08:08:38.36#ibcon#*before write, iclass 4, count 2 2006.238.08:08:38.36#ibcon#enter sib2, iclass 4, count 2 2006.238.08:08:38.36#ibcon#flushed, iclass 4, count 2 2006.238.08:08:38.36#ibcon#about to write, iclass 4, count 2 2006.238.08:08:38.36#ibcon#wrote, iclass 4, count 2 2006.238.08:08:38.36#ibcon#about to read 3, iclass 4, count 2 2006.238.08:08:38.39#ibcon#read 3, iclass 4, count 2 2006.238.08:08:38.39#ibcon#about to read 4, iclass 4, count 2 2006.238.08:08:38.39#ibcon#read 4, iclass 4, count 2 2006.238.08:08:38.39#ibcon#about to read 5, iclass 4, count 2 2006.238.08:08:38.39#ibcon#read 5, iclass 4, count 2 2006.238.08:08:38.39#ibcon#about to read 6, iclass 4, count 2 2006.238.08:08:38.39#ibcon#read 6, iclass 4, count 2 2006.238.08:08:38.39#ibcon#end of sib2, iclass 4, count 2 2006.238.08:08:38.39#ibcon#*after write, iclass 4, count 2 2006.238.08:08:38.39#ibcon#*before return 0, iclass 4, count 2 2006.238.08:08:38.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:08:38.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:08:38.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.238.08:08:38.39#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:38.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:08:38.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:08:38.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:08:38.51#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:08:38.51#ibcon#first serial, iclass 4, count 0 2006.238.08:08:38.51#ibcon#enter sib2, iclass 4, count 0 2006.238.08:08:38.51#ibcon#flushed, iclass 4, count 0 2006.238.08:08:38.51#ibcon#about to write, iclass 4, count 0 2006.238.08:08:38.51#ibcon#wrote, iclass 4, count 0 2006.238.08:08:38.51#ibcon#about to read 3, iclass 4, count 0 2006.238.08:08:38.53#ibcon#read 3, iclass 4, count 0 2006.238.08:08:38.53#ibcon#about to read 4, iclass 4, count 0 2006.238.08:08:38.53#ibcon#read 4, iclass 4, count 0 2006.238.08:08:38.53#ibcon#about to read 5, iclass 4, count 0 2006.238.08:08:38.53#ibcon#read 5, iclass 4, count 0 2006.238.08:08:38.53#ibcon#about to read 6, iclass 4, count 0 2006.238.08:08:38.53#ibcon#read 6, iclass 4, count 0 2006.238.08:08:38.53#ibcon#end of sib2, iclass 4, count 0 2006.238.08:08:38.53#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:08:38.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:08:38.53#ibcon#[25=USB\r\n] 2006.238.08:08:38.53#ibcon#*before write, iclass 4, count 0 2006.238.08:08:38.53#ibcon#enter sib2, iclass 4, count 0 2006.238.08:08:38.53#ibcon#flushed, iclass 4, count 0 2006.238.08:08:38.53#ibcon#about to write, iclass 4, count 0 2006.238.08:08:38.53#ibcon#wrote, iclass 4, count 0 2006.238.08:08:38.53#ibcon#about to read 3, iclass 4, count 0 2006.238.08:08:38.56#ibcon#read 3, iclass 4, count 0 2006.238.08:08:38.56#ibcon#about to read 4, iclass 4, count 0 2006.238.08:08:38.56#ibcon#read 4, iclass 4, count 0 2006.238.08:08:38.56#ibcon#about to read 5, iclass 4, count 0 2006.238.08:08:38.56#ibcon#read 5, iclass 4, count 0 2006.238.08:08:38.56#ibcon#about to read 6, iclass 4, count 0 2006.238.08:08:38.56#ibcon#read 6, iclass 4, count 0 2006.238.08:08:38.56#ibcon#end of sib2, iclass 4, count 0 2006.238.08:08:38.56#ibcon#*after write, iclass 4, count 0 2006.238.08:08:38.56#ibcon#*before return 0, iclass 4, count 0 2006.238.08:08:38.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:08:38.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:08:38.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:08:38.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:08:38.56$vc4f8/valo=3,672.99 2006.238.08:08:38.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.238.08:08:38.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.238.08:08:38.56#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:38.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:08:38.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:08:38.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:08:38.56#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:08:38.56#ibcon#first serial, iclass 6, count 0 2006.238.08:08:38.56#ibcon#enter sib2, iclass 6, count 0 2006.238.08:08:38.56#ibcon#flushed, iclass 6, count 0 2006.238.08:08:38.56#ibcon#about to write, iclass 6, count 0 2006.238.08:08:38.56#ibcon#wrote, iclass 6, count 0 2006.238.08:08:38.56#ibcon#about to read 3, iclass 6, count 0 2006.238.08:08:38.58#ibcon#read 3, iclass 6, count 0 2006.238.08:08:38.58#ibcon#about to read 4, iclass 6, count 0 2006.238.08:08:38.58#ibcon#read 4, iclass 6, count 0 2006.238.08:08:38.58#ibcon#about to read 5, iclass 6, count 0 2006.238.08:08:38.58#ibcon#read 5, iclass 6, count 0 2006.238.08:08:38.58#ibcon#about to read 6, iclass 6, count 0 2006.238.08:08:38.58#ibcon#read 6, iclass 6, count 0 2006.238.08:08:38.58#ibcon#end of sib2, iclass 6, count 0 2006.238.08:08:38.58#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:08:38.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:08:38.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:08:38.58#ibcon#*before write, iclass 6, count 0 2006.238.08:08:38.58#ibcon#enter sib2, iclass 6, count 0 2006.238.08:08:38.58#ibcon#flushed, iclass 6, count 0 2006.238.08:08:38.58#ibcon#about to write, iclass 6, count 0 2006.238.08:08:38.58#ibcon#wrote, iclass 6, count 0 2006.238.08:08:38.58#ibcon#about to read 3, iclass 6, count 0 2006.238.08:08:38.62#ibcon#read 3, iclass 6, count 0 2006.238.08:08:38.62#ibcon#about to read 4, iclass 6, count 0 2006.238.08:08:38.62#ibcon#read 4, iclass 6, count 0 2006.238.08:08:38.62#ibcon#about to read 5, iclass 6, count 0 2006.238.08:08:38.62#ibcon#read 5, iclass 6, count 0 2006.238.08:08:38.62#ibcon#about to read 6, iclass 6, count 0 2006.238.08:08:38.62#ibcon#read 6, iclass 6, count 0 2006.238.08:08:38.62#ibcon#end of sib2, iclass 6, count 0 2006.238.08:08:38.62#ibcon#*after write, iclass 6, count 0 2006.238.08:08:38.62#ibcon#*before return 0, iclass 6, count 0 2006.238.08:08:38.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:08:38.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:08:38.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:08:38.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:08:38.62$vc4f8/va=3,7 2006.238.08:08:38.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.238.08:08:38.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.238.08:08:38.62#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:38.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:08:38.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:08:38.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:08:38.68#ibcon#enter wrdev, iclass 10, count 2 2006.238.08:08:38.68#ibcon#first serial, iclass 10, count 2 2006.238.08:08:38.68#ibcon#enter sib2, iclass 10, count 2 2006.238.08:08:38.68#ibcon#flushed, iclass 10, count 2 2006.238.08:08:38.68#ibcon#about to write, iclass 10, count 2 2006.238.08:08:38.68#ibcon#wrote, iclass 10, count 2 2006.238.08:08:38.68#ibcon#about to read 3, iclass 10, count 2 2006.238.08:08:38.70#ibcon#read 3, iclass 10, count 2 2006.238.08:08:38.70#ibcon#about to read 4, iclass 10, count 2 2006.238.08:08:38.70#ibcon#read 4, iclass 10, count 2 2006.238.08:08:38.70#ibcon#about to read 5, iclass 10, count 2 2006.238.08:08:38.70#ibcon#read 5, iclass 10, count 2 2006.238.08:08:38.70#ibcon#about to read 6, iclass 10, count 2 2006.238.08:08:38.70#ibcon#read 6, iclass 10, count 2 2006.238.08:08:38.70#ibcon#end of sib2, iclass 10, count 2 2006.238.08:08:38.70#ibcon#*mode == 0, iclass 10, count 2 2006.238.08:08:38.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.238.08:08:38.70#ibcon#[25=AT03-07\r\n] 2006.238.08:08:38.70#ibcon#*before write, iclass 10, count 2 2006.238.08:08:38.70#ibcon#enter sib2, iclass 10, count 2 2006.238.08:08:38.70#ibcon#flushed, iclass 10, count 2 2006.238.08:08:38.70#ibcon#about to write, iclass 10, count 2 2006.238.08:08:38.70#ibcon#wrote, iclass 10, count 2 2006.238.08:08:38.70#ibcon#about to read 3, iclass 10, count 2 2006.238.08:08:38.73#ibcon#read 3, iclass 10, count 2 2006.238.08:08:38.73#ibcon#about to read 4, iclass 10, count 2 2006.238.08:08:38.73#ibcon#read 4, iclass 10, count 2 2006.238.08:08:38.73#ibcon#about to read 5, iclass 10, count 2 2006.238.08:08:38.73#ibcon#read 5, iclass 10, count 2 2006.238.08:08:38.73#ibcon#about to read 6, iclass 10, count 2 2006.238.08:08:38.73#ibcon#read 6, iclass 10, count 2 2006.238.08:08:38.73#ibcon#end of sib2, iclass 10, count 2 2006.238.08:08:38.73#ibcon#*after write, iclass 10, count 2 2006.238.08:08:38.73#ibcon#*before return 0, iclass 10, count 2 2006.238.08:08:38.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:08:38.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:08:38.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.238.08:08:38.73#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:38.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:08:38.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:08:38.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:08:38.85#ibcon#enter wrdev, iclass 10, count 0 2006.238.08:08:38.85#ibcon#first serial, iclass 10, count 0 2006.238.08:08:38.85#ibcon#enter sib2, iclass 10, count 0 2006.238.08:08:38.85#ibcon#flushed, iclass 10, count 0 2006.238.08:08:38.85#ibcon#about to write, iclass 10, count 0 2006.238.08:08:38.85#ibcon#wrote, iclass 10, count 0 2006.238.08:08:38.85#ibcon#about to read 3, iclass 10, count 0 2006.238.08:08:38.87#ibcon#read 3, iclass 10, count 0 2006.238.08:08:38.87#ibcon#about to read 4, iclass 10, count 0 2006.238.08:08:38.87#ibcon#read 4, iclass 10, count 0 2006.238.08:08:38.87#ibcon#about to read 5, iclass 10, count 0 2006.238.08:08:38.87#ibcon#read 5, iclass 10, count 0 2006.238.08:08:38.87#ibcon#about to read 6, iclass 10, count 0 2006.238.08:08:38.87#ibcon#read 6, iclass 10, count 0 2006.238.08:08:38.87#ibcon#end of sib2, iclass 10, count 0 2006.238.08:08:38.87#ibcon#*mode == 0, iclass 10, count 0 2006.238.08:08:38.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.08:08:38.87#ibcon#[25=USB\r\n] 2006.238.08:08:38.87#ibcon#*before write, iclass 10, count 0 2006.238.08:08:38.87#ibcon#enter sib2, iclass 10, count 0 2006.238.08:08:38.87#ibcon#flushed, iclass 10, count 0 2006.238.08:08:38.87#ibcon#about to write, iclass 10, count 0 2006.238.08:08:38.87#ibcon#wrote, iclass 10, count 0 2006.238.08:08:38.87#ibcon#about to read 3, iclass 10, count 0 2006.238.08:08:38.90#ibcon#read 3, iclass 10, count 0 2006.238.08:08:38.90#ibcon#about to read 4, iclass 10, count 0 2006.238.08:08:38.90#ibcon#read 4, iclass 10, count 0 2006.238.08:08:38.90#ibcon#about to read 5, iclass 10, count 0 2006.238.08:08:38.90#ibcon#read 5, iclass 10, count 0 2006.238.08:08:38.90#ibcon#about to read 6, iclass 10, count 0 2006.238.08:08:38.90#ibcon#read 6, iclass 10, count 0 2006.238.08:08:38.90#ibcon#end of sib2, iclass 10, count 0 2006.238.08:08:38.90#ibcon#*after write, iclass 10, count 0 2006.238.08:08:38.90#ibcon#*before return 0, iclass 10, count 0 2006.238.08:08:38.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:08:38.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:08:38.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.08:08:38.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.08:08:38.90$vc4f8/valo=4,832.99 2006.238.08:08:38.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.238.08:08:38.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.238.08:08:38.90#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:38.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:08:38.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:08:38.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:08:38.90#ibcon#enter wrdev, iclass 12, count 0 2006.238.08:08:38.90#ibcon#first serial, iclass 12, count 0 2006.238.08:08:38.90#ibcon#enter sib2, iclass 12, count 0 2006.238.08:08:38.90#ibcon#flushed, iclass 12, count 0 2006.238.08:08:38.90#ibcon#about to write, iclass 12, count 0 2006.238.08:08:38.90#ibcon#wrote, iclass 12, count 0 2006.238.08:08:38.90#ibcon#about to read 3, iclass 12, count 0 2006.238.08:08:38.92#ibcon#read 3, iclass 12, count 0 2006.238.08:08:38.92#ibcon#about to read 4, iclass 12, count 0 2006.238.08:08:38.92#ibcon#read 4, iclass 12, count 0 2006.238.08:08:38.92#ibcon#about to read 5, iclass 12, count 0 2006.238.08:08:38.92#ibcon#read 5, iclass 12, count 0 2006.238.08:08:38.92#ibcon#about to read 6, iclass 12, count 0 2006.238.08:08:38.92#ibcon#read 6, iclass 12, count 0 2006.238.08:08:38.92#ibcon#end of sib2, iclass 12, count 0 2006.238.08:08:38.92#ibcon#*mode == 0, iclass 12, count 0 2006.238.08:08:38.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.08:08:38.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:08:38.92#ibcon#*before write, iclass 12, count 0 2006.238.08:08:38.92#ibcon#enter sib2, iclass 12, count 0 2006.238.08:08:38.92#ibcon#flushed, iclass 12, count 0 2006.238.08:08:38.92#ibcon#about to write, iclass 12, count 0 2006.238.08:08:38.92#ibcon#wrote, iclass 12, count 0 2006.238.08:08:38.92#ibcon#about to read 3, iclass 12, count 0 2006.238.08:08:38.96#ibcon#read 3, iclass 12, count 0 2006.238.08:08:38.96#ibcon#about to read 4, iclass 12, count 0 2006.238.08:08:38.96#ibcon#read 4, iclass 12, count 0 2006.238.08:08:38.96#ibcon#about to read 5, iclass 12, count 0 2006.238.08:08:38.96#ibcon#read 5, iclass 12, count 0 2006.238.08:08:38.96#ibcon#about to read 6, iclass 12, count 0 2006.238.08:08:38.96#ibcon#read 6, iclass 12, count 0 2006.238.08:08:38.96#ibcon#end of sib2, iclass 12, count 0 2006.238.08:08:38.96#ibcon#*after write, iclass 12, count 0 2006.238.08:08:38.96#ibcon#*before return 0, iclass 12, count 0 2006.238.08:08:38.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:08:38.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:08:38.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.08:08:38.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.08:08:38.96$vc4f8/va=4,7 2006.238.08:08:38.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.238.08:08:38.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.238.08:08:38.96#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:38.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:08:39.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:08:39.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:08:39.02#ibcon#enter wrdev, iclass 14, count 2 2006.238.08:08:39.02#ibcon#first serial, iclass 14, count 2 2006.238.08:08:39.02#ibcon#enter sib2, iclass 14, count 2 2006.238.08:08:39.02#ibcon#flushed, iclass 14, count 2 2006.238.08:08:39.02#ibcon#about to write, iclass 14, count 2 2006.238.08:08:39.02#ibcon#wrote, iclass 14, count 2 2006.238.08:08:39.02#ibcon#about to read 3, iclass 14, count 2 2006.238.08:08:39.04#ibcon#read 3, iclass 14, count 2 2006.238.08:08:39.04#ibcon#about to read 4, iclass 14, count 2 2006.238.08:08:39.04#ibcon#read 4, iclass 14, count 2 2006.238.08:08:39.04#ibcon#about to read 5, iclass 14, count 2 2006.238.08:08:39.04#ibcon#read 5, iclass 14, count 2 2006.238.08:08:39.04#ibcon#about to read 6, iclass 14, count 2 2006.238.08:08:39.04#ibcon#read 6, iclass 14, count 2 2006.238.08:08:39.04#ibcon#end of sib2, iclass 14, count 2 2006.238.08:08:39.04#ibcon#*mode == 0, iclass 14, count 2 2006.238.08:08:39.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.238.08:08:39.04#ibcon#[25=AT04-07\r\n] 2006.238.08:08:39.04#ibcon#*before write, iclass 14, count 2 2006.238.08:08:39.04#ibcon#enter sib2, iclass 14, count 2 2006.238.08:08:39.04#ibcon#flushed, iclass 14, count 2 2006.238.08:08:39.04#ibcon#about to write, iclass 14, count 2 2006.238.08:08:39.04#ibcon#wrote, iclass 14, count 2 2006.238.08:08:39.04#ibcon#about to read 3, iclass 14, count 2 2006.238.08:08:39.07#ibcon#read 3, iclass 14, count 2 2006.238.08:08:39.07#ibcon#about to read 4, iclass 14, count 2 2006.238.08:08:39.07#ibcon#read 4, iclass 14, count 2 2006.238.08:08:39.07#ibcon#about to read 5, iclass 14, count 2 2006.238.08:08:39.07#ibcon#read 5, iclass 14, count 2 2006.238.08:08:39.07#ibcon#about to read 6, iclass 14, count 2 2006.238.08:08:39.07#ibcon#read 6, iclass 14, count 2 2006.238.08:08:39.07#ibcon#end of sib2, iclass 14, count 2 2006.238.08:08:39.07#ibcon#*after write, iclass 14, count 2 2006.238.08:08:39.07#ibcon#*before return 0, iclass 14, count 2 2006.238.08:08:39.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:08:39.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:08:39.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.238.08:08:39.07#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:39.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:08:39.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:08:39.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:08:39.19#ibcon#enter wrdev, iclass 14, count 0 2006.238.08:08:39.19#ibcon#first serial, iclass 14, count 0 2006.238.08:08:39.19#ibcon#enter sib2, iclass 14, count 0 2006.238.08:08:39.19#ibcon#flushed, iclass 14, count 0 2006.238.08:08:39.19#ibcon#about to write, iclass 14, count 0 2006.238.08:08:39.19#ibcon#wrote, iclass 14, count 0 2006.238.08:08:39.19#ibcon#about to read 3, iclass 14, count 0 2006.238.08:08:39.21#ibcon#read 3, iclass 14, count 0 2006.238.08:08:39.21#ibcon#about to read 4, iclass 14, count 0 2006.238.08:08:39.21#ibcon#read 4, iclass 14, count 0 2006.238.08:08:39.21#ibcon#about to read 5, iclass 14, count 0 2006.238.08:08:39.21#ibcon#read 5, iclass 14, count 0 2006.238.08:08:39.21#ibcon#about to read 6, iclass 14, count 0 2006.238.08:08:39.21#ibcon#read 6, iclass 14, count 0 2006.238.08:08:39.21#ibcon#end of sib2, iclass 14, count 0 2006.238.08:08:39.21#ibcon#*mode == 0, iclass 14, count 0 2006.238.08:08:39.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.08:08:39.21#ibcon#[25=USB\r\n] 2006.238.08:08:39.21#ibcon#*before write, iclass 14, count 0 2006.238.08:08:39.21#ibcon#enter sib2, iclass 14, count 0 2006.238.08:08:39.21#ibcon#flushed, iclass 14, count 0 2006.238.08:08:39.21#ibcon#about to write, iclass 14, count 0 2006.238.08:08:39.21#ibcon#wrote, iclass 14, count 0 2006.238.08:08:39.21#ibcon#about to read 3, iclass 14, count 0 2006.238.08:08:39.24#ibcon#read 3, iclass 14, count 0 2006.238.08:08:39.24#ibcon#about to read 4, iclass 14, count 0 2006.238.08:08:39.24#ibcon#read 4, iclass 14, count 0 2006.238.08:08:39.24#ibcon#about to read 5, iclass 14, count 0 2006.238.08:08:39.24#ibcon#read 5, iclass 14, count 0 2006.238.08:08:39.24#ibcon#about to read 6, iclass 14, count 0 2006.238.08:08:39.24#ibcon#read 6, iclass 14, count 0 2006.238.08:08:39.24#ibcon#end of sib2, iclass 14, count 0 2006.238.08:08:39.24#ibcon#*after write, iclass 14, count 0 2006.238.08:08:39.24#ibcon#*before return 0, iclass 14, count 0 2006.238.08:08:39.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:08:39.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:08:39.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.08:08:39.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.08:08:39.24$vc4f8/valo=5,652.99 2006.238.08:08:39.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.08:08:39.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.08:08:39.24#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:39.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:08:39.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:08:39.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:08:39.24#ibcon#enter wrdev, iclass 16, count 0 2006.238.08:08:39.24#ibcon#first serial, iclass 16, count 0 2006.238.08:08:39.24#ibcon#enter sib2, iclass 16, count 0 2006.238.08:08:39.24#ibcon#flushed, iclass 16, count 0 2006.238.08:08:39.24#ibcon#about to write, iclass 16, count 0 2006.238.08:08:39.24#ibcon#wrote, iclass 16, count 0 2006.238.08:08:39.24#ibcon#about to read 3, iclass 16, count 0 2006.238.08:08:39.26#ibcon#read 3, iclass 16, count 0 2006.238.08:08:39.26#ibcon#about to read 4, iclass 16, count 0 2006.238.08:08:39.26#ibcon#read 4, iclass 16, count 0 2006.238.08:08:39.26#ibcon#about to read 5, iclass 16, count 0 2006.238.08:08:39.26#ibcon#read 5, iclass 16, count 0 2006.238.08:08:39.26#ibcon#about to read 6, iclass 16, count 0 2006.238.08:08:39.26#ibcon#read 6, iclass 16, count 0 2006.238.08:08:39.26#ibcon#end of sib2, iclass 16, count 0 2006.238.08:08:39.26#ibcon#*mode == 0, iclass 16, count 0 2006.238.08:08:39.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.08:08:39.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:08:39.26#ibcon#*before write, iclass 16, count 0 2006.238.08:08:39.26#ibcon#enter sib2, iclass 16, count 0 2006.238.08:08:39.26#ibcon#flushed, iclass 16, count 0 2006.238.08:08:39.26#ibcon#about to write, iclass 16, count 0 2006.238.08:08:39.26#ibcon#wrote, iclass 16, count 0 2006.238.08:08:39.26#ibcon#about to read 3, iclass 16, count 0 2006.238.08:08:39.30#ibcon#read 3, iclass 16, count 0 2006.238.08:08:39.30#ibcon#about to read 4, iclass 16, count 0 2006.238.08:08:39.30#ibcon#read 4, iclass 16, count 0 2006.238.08:08:39.30#ibcon#about to read 5, iclass 16, count 0 2006.238.08:08:39.30#ibcon#read 5, iclass 16, count 0 2006.238.08:08:39.30#ibcon#about to read 6, iclass 16, count 0 2006.238.08:08:39.30#ibcon#read 6, iclass 16, count 0 2006.238.08:08:39.30#ibcon#end of sib2, iclass 16, count 0 2006.238.08:08:39.30#ibcon#*after write, iclass 16, count 0 2006.238.08:08:39.30#ibcon#*before return 0, iclass 16, count 0 2006.238.08:08:39.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:08:39.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:08:39.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.08:08:39.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.08:08:39.30$vc4f8/va=5,8 2006.238.08:08:39.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.238.08:08:39.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.238.08:08:39.30#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:39.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:08:39.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:08:39.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:08:39.36#ibcon#enter wrdev, iclass 18, count 2 2006.238.08:08:39.36#ibcon#first serial, iclass 18, count 2 2006.238.08:08:39.36#ibcon#enter sib2, iclass 18, count 2 2006.238.08:08:39.36#ibcon#flushed, iclass 18, count 2 2006.238.08:08:39.36#ibcon#about to write, iclass 18, count 2 2006.238.08:08:39.36#ibcon#wrote, iclass 18, count 2 2006.238.08:08:39.36#ibcon#about to read 3, iclass 18, count 2 2006.238.08:08:39.38#ibcon#read 3, iclass 18, count 2 2006.238.08:08:39.38#ibcon#about to read 4, iclass 18, count 2 2006.238.08:08:39.38#ibcon#read 4, iclass 18, count 2 2006.238.08:08:39.38#ibcon#about to read 5, iclass 18, count 2 2006.238.08:08:39.38#ibcon#read 5, iclass 18, count 2 2006.238.08:08:39.38#ibcon#about to read 6, iclass 18, count 2 2006.238.08:08:39.38#ibcon#read 6, iclass 18, count 2 2006.238.08:08:39.38#ibcon#end of sib2, iclass 18, count 2 2006.238.08:08:39.38#ibcon#*mode == 0, iclass 18, count 2 2006.238.08:08:39.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.238.08:08:39.38#ibcon#[25=AT05-08\r\n] 2006.238.08:08:39.38#ibcon#*before write, iclass 18, count 2 2006.238.08:08:39.38#ibcon#enter sib2, iclass 18, count 2 2006.238.08:08:39.38#ibcon#flushed, iclass 18, count 2 2006.238.08:08:39.38#ibcon#about to write, iclass 18, count 2 2006.238.08:08:39.38#ibcon#wrote, iclass 18, count 2 2006.238.08:08:39.38#ibcon#about to read 3, iclass 18, count 2 2006.238.08:08:39.41#ibcon#read 3, iclass 18, count 2 2006.238.08:08:39.41#ibcon#about to read 4, iclass 18, count 2 2006.238.08:08:39.41#ibcon#read 4, iclass 18, count 2 2006.238.08:08:39.41#ibcon#about to read 5, iclass 18, count 2 2006.238.08:08:39.41#ibcon#read 5, iclass 18, count 2 2006.238.08:08:39.41#ibcon#about to read 6, iclass 18, count 2 2006.238.08:08:39.41#ibcon#read 6, iclass 18, count 2 2006.238.08:08:39.41#ibcon#end of sib2, iclass 18, count 2 2006.238.08:08:39.41#ibcon#*after write, iclass 18, count 2 2006.238.08:08:39.41#ibcon#*before return 0, iclass 18, count 2 2006.238.08:08:39.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:08:39.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:08:39.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.238.08:08:39.41#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:39.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:08:39.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:08:39.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:08:39.54#ibcon#enter wrdev, iclass 18, count 0 2006.238.08:08:39.54#ibcon#first serial, iclass 18, count 0 2006.238.08:08:39.54#ibcon#enter sib2, iclass 18, count 0 2006.238.08:08:39.54#ibcon#flushed, iclass 18, count 0 2006.238.08:08:39.54#ibcon#about to write, iclass 18, count 0 2006.238.08:08:39.54#ibcon#wrote, iclass 18, count 0 2006.238.08:08:39.54#ibcon#about to read 3, iclass 18, count 0 2006.238.08:08:39.56#ibcon#read 3, iclass 18, count 0 2006.238.08:08:39.56#ibcon#about to read 4, iclass 18, count 0 2006.238.08:08:39.56#ibcon#read 4, iclass 18, count 0 2006.238.08:08:39.56#ibcon#about to read 5, iclass 18, count 0 2006.238.08:08:39.56#ibcon#read 5, iclass 18, count 0 2006.238.08:08:39.56#ibcon#about to read 6, iclass 18, count 0 2006.238.08:08:39.56#ibcon#read 6, iclass 18, count 0 2006.238.08:08:39.56#ibcon#end of sib2, iclass 18, count 0 2006.238.08:08:39.56#ibcon#*mode == 0, iclass 18, count 0 2006.238.08:08:39.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.08:08:39.56#ibcon#[25=USB\r\n] 2006.238.08:08:39.56#ibcon#*before write, iclass 18, count 0 2006.238.08:08:39.56#ibcon#enter sib2, iclass 18, count 0 2006.238.08:08:39.56#ibcon#flushed, iclass 18, count 0 2006.238.08:08:39.56#ibcon#about to write, iclass 18, count 0 2006.238.08:08:39.56#ibcon#wrote, iclass 18, count 0 2006.238.08:08:39.56#ibcon#about to read 3, iclass 18, count 0 2006.238.08:08:39.59#ibcon#read 3, iclass 18, count 0 2006.238.08:08:39.59#ibcon#about to read 4, iclass 18, count 0 2006.238.08:08:39.59#ibcon#read 4, iclass 18, count 0 2006.238.08:08:39.59#ibcon#about to read 5, iclass 18, count 0 2006.238.08:08:39.59#ibcon#read 5, iclass 18, count 0 2006.238.08:08:39.59#ibcon#about to read 6, iclass 18, count 0 2006.238.08:08:39.59#ibcon#read 6, iclass 18, count 0 2006.238.08:08:39.59#ibcon#end of sib2, iclass 18, count 0 2006.238.08:08:39.59#ibcon#*after write, iclass 18, count 0 2006.238.08:08:39.59#ibcon#*before return 0, iclass 18, count 0 2006.238.08:08:39.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:08:39.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:08:39.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.08:08:39.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.08:08:39.59$vc4f8/valo=6,772.99 2006.238.08:08:39.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.08:08:39.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.08:08:39.59#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:39.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:08:39.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:08:39.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:08:39.59#ibcon#enter wrdev, iclass 20, count 0 2006.238.08:08:39.59#ibcon#first serial, iclass 20, count 0 2006.238.08:08:39.59#ibcon#enter sib2, iclass 20, count 0 2006.238.08:08:39.59#ibcon#flushed, iclass 20, count 0 2006.238.08:08:39.59#ibcon#about to write, iclass 20, count 0 2006.238.08:08:39.59#ibcon#wrote, iclass 20, count 0 2006.238.08:08:39.59#ibcon#about to read 3, iclass 20, count 0 2006.238.08:08:39.61#ibcon#read 3, iclass 20, count 0 2006.238.08:08:39.61#ibcon#about to read 4, iclass 20, count 0 2006.238.08:08:39.61#ibcon#read 4, iclass 20, count 0 2006.238.08:08:39.61#ibcon#about to read 5, iclass 20, count 0 2006.238.08:08:39.61#ibcon#read 5, iclass 20, count 0 2006.238.08:08:39.61#ibcon#about to read 6, iclass 20, count 0 2006.238.08:08:39.61#ibcon#read 6, iclass 20, count 0 2006.238.08:08:39.61#ibcon#end of sib2, iclass 20, count 0 2006.238.08:08:39.61#ibcon#*mode == 0, iclass 20, count 0 2006.238.08:08:39.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.08:08:39.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:08:39.61#ibcon#*before write, iclass 20, count 0 2006.238.08:08:39.61#ibcon#enter sib2, iclass 20, count 0 2006.238.08:08:39.61#ibcon#flushed, iclass 20, count 0 2006.238.08:08:39.61#ibcon#about to write, iclass 20, count 0 2006.238.08:08:39.61#ibcon#wrote, iclass 20, count 0 2006.238.08:08:39.61#ibcon#about to read 3, iclass 20, count 0 2006.238.08:08:39.65#ibcon#read 3, iclass 20, count 0 2006.238.08:08:39.65#ibcon#about to read 4, iclass 20, count 0 2006.238.08:08:39.65#ibcon#read 4, iclass 20, count 0 2006.238.08:08:39.65#ibcon#about to read 5, iclass 20, count 0 2006.238.08:08:39.65#ibcon#read 5, iclass 20, count 0 2006.238.08:08:39.65#ibcon#about to read 6, iclass 20, count 0 2006.238.08:08:39.65#ibcon#read 6, iclass 20, count 0 2006.238.08:08:39.65#ibcon#end of sib2, iclass 20, count 0 2006.238.08:08:39.65#ibcon#*after write, iclass 20, count 0 2006.238.08:08:39.65#ibcon#*before return 0, iclass 20, count 0 2006.238.08:08:39.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:08:39.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:08:39.65#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.08:08:39.65#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.08:08:39.65$vc4f8/va=6,7 2006.238.08:08:39.65#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.238.08:08:39.65#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.238.08:08:39.65#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:39.65#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:08:39.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:08:39.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:08:39.71#ibcon#enter wrdev, iclass 22, count 2 2006.238.08:08:39.71#ibcon#first serial, iclass 22, count 2 2006.238.08:08:39.71#ibcon#enter sib2, iclass 22, count 2 2006.238.08:08:39.71#ibcon#flushed, iclass 22, count 2 2006.238.08:08:39.71#ibcon#about to write, iclass 22, count 2 2006.238.08:08:39.71#ibcon#wrote, iclass 22, count 2 2006.238.08:08:39.71#ibcon#about to read 3, iclass 22, count 2 2006.238.08:08:39.73#ibcon#read 3, iclass 22, count 2 2006.238.08:08:39.73#ibcon#about to read 4, iclass 22, count 2 2006.238.08:08:39.73#ibcon#read 4, iclass 22, count 2 2006.238.08:08:39.73#ibcon#about to read 5, iclass 22, count 2 2006.238.08:08:39.73#ibcon#read 5, iclass 22, count 2 2006.238.08:08:39.73#ibcon#about to read 6, iclass 22, count 2 2006.238.08:08:39.73#ibcon#read 6, iclass 22, count 2 2006.238.08:08:39.73#ibcon#end of sib2, iclass 22, count 2 2006.238.08:08:39.73#ibcon#*mode == 0, iclass 22, count 2 2006.238.08:08:39.73#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.238.08:08:39.73#ibcon#[25=AT06-07\r\n] 2006.238.08:08:39.73#ibcon#*before write, iclass 22, count 2 2006.238.08:08:39.73#ibcon#enter sib2, iclass 22, count 2 2006.238.08:08:39.73#ibcon#flushed, iclass 22, count 2 2006.238.08:08:39.73#ibcon#about to write, iclass 22, count 2 2006.238.08:08:39.73#ibcon#wrote, iclass 22, count 2 2006.238.08:08:39.73#ibcon#about to read 3, iclass 22, count 2 2006.238.08:08:39.76#ibcon#read 3, iclass 22, count 2 2006.238.08:08:39.76#ibcon#about to read 4, iclass 22, count 2 2006.238.08:08:39.76#ibcon#read 4, iclass 22, count 2 2006.238.08:08:39.76#ibcon#about to read 5, iclass 22, count 2 2006.238.08:08:39.76#ibcon#read 5, iclass 22, count 2 2006.238.08:08:39.76#ibcon#about to read 6, iclass 22, count 2 2006.238.08:08:39.76#ibcon#read 6, iclass 22, count 2 2006.238.08:08:39.76#ibcon#end of sib2, iclass 22, count 2 2006.238.08:08:39.76#ibcon#*after write, iclass 22, count 2 2006.238.08:08:39.76#ibcon#*before return 0, iclass 22, count 2 2006.238.08:08:39.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:08:39.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:08:39.76#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.238.08:08:39.76#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:39.76#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:08:39.88#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:08:39.88#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:08:39.88#ibcon#enter wrdev, iclass 22, count 0 2006.238.08:08:39.88#ibcon#first serial, iclass 22, count 0 2006.238.08:08:39.88#ibcon#enter sib2, iclass 22, count 0 2006.238.08:08:39.88#ibcon#flushed, iclass 22, count 0 2006.238.08:08:39.88#ibcon#about to write, iclass 22, count 0 2006.238.08:08:39.88#ibcon#wrote, iclass 22, count 0 2006.238.08:08:39.88#ibcon#about to read 3, iclass 22, count 0 2006.238.08:08:39.90#ibcon#read 3, iclass 22, count 0 2006.238.08:08:39.90#ibcon#about to read 4, iclass 22, count 0 2006.238.08:08:39.90#ibcon#read 4, iclass 22, count 0 2006.238.08:08:39.90#ibcon#about to read 5, iclass 22, count 0 2006.238.08:08:39.90#ibcon#read 5, iclass 22, count 0 2006.238.08:08:39.90#ibcon#about to read 6, iclass 22, count 0 2006.238.08:08:39.90#ibcon#read 6, iclass 22, count 0 2006.238.08:08:39.90#ibcon#end of sib2, iclass 22, count 0 2006.238.08:08:39.90#ibcon#*mode == 0, iclass 22, count 0 2006.238.08:08:39.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.08:08:39.90#ibcon#[25=USB\r\n] 2006.238.08:08:39.90#ibcon#*before write, iclass 22, count 0 2006.238.08:08:39.90#ibcon#enter sib2, iclass 22, count 0 2006.238.08:08:39.90#ibcon#flushed, iclass 22, count 0 2006.238.08:08:39.90#ibcon#about to write, iclass 22, count 0 2006.238.08:08:39.90#ibcon#wrote, iclass 22, count 0 2006.238.08:08:39.90#ibcon#about to read 3, iclass 22, count 0 2006.238.08:08:39.93#ibcon#read 3, iclass 22, count 0 2006.238.08:08:39.93#ibcon#about to read 4, iclass 22, count 0 2006.238.08:08:39.93#ibcon#read 4, iclass 22, count 0 2006.238.08:08:39.93#ibcon#about to read 5, iclass 22, count 0 2006.238.08:08:39.93#ibcon#read 5, iclass 22, count 0 2006.238.08:08:39.93#ibcon#about to read 6, iclass 22, count 0 2006.238.08:08:39.93#ibcon#read 6, iclass 22, count 0 2006.238.08:08:39.93#ibcon#end of sib2, iclass 22, count 0 2006.238.08:08:39.93#ibcon#*after write, iclass 22, count 0 2006.238.08:08:39.93#ibcon#*before return 0, iclass 22, count 0 2006.238.08:08:39.93#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:08:39.93#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:08:39.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.08:08:39.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.08:08:39.93$vc4f8/valo=7,832.99 2006.238.08:08:39.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.08:08:39.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.08:08:39.93#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:39.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:08:39.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:08:39.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:08:39.93#ibcon#enter wrdev, iclass 24, count 0 2006.238.08:08:39.93#ibcon#first serial, iclass 24, count 0 2006.238.08:08:39.93#ibcon#enter sib2, iclass 24, count 0 2006.238.08:08:39.93#ibcon#flushed, iclass 24, count 0 2006.238.08:08:39.93#ibcon#about to write, iclass 24, count 0 2006.238.08:08:39.93#ibcon#wrote, iclass 24, count 0 2006.238.08:08:39.93#ibcon#about to read 3, iclass 24, count 0 2006.238.08:08:39.95#ibcon#read 3, iclass 24, count 0 2006.238.08:08:39.95#ibcon#about to read 4, iclass 24, count 0 2006.238.08:08:39.95#ibcon#read 4, iclass 24, count 0 2006.238.08:08:39.95#ibcon#about to read 5, iclass 24, count 0 2006.238.08:08:39.95#ibcon#read 5, iclass 24, count 0 2006.238.08:08:39.95#ibcon#about to read 6, iclass 24, count 0 2006.238.08:08:39.95#ibcon#read 6, iclass 24, count 0 2006.238.08:08:39.95#ibcon#end of sib2, iclass 24, count 0 2006.238.08:08:39.95#ibcon#*mode == 0, iclass 24, count 0 2006.238.08:08:39.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.08:08:39.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:08:39.95#ibcon#*before write, iclass 24, count 0 2006.238.08:08:39.95#ibcon#enter sib2, iclass 24, count 0 2006.238.08:08:39.95#ibcon#flushed, iclass 24, count 0 2006.238.08:08:39.95#ibcon#about to write, iclass 24, count 0 2006.238.08:08:39.95#ibcon#wrote, iclass 24, count 0 2006.238.08:08:39.95#ibcon#about to read 3, iclass 24, count 0 2006.238.08:08:39.99#ibcon#read 3, iclass 24, count 0 2006.238.08:08:39.99#ibcon#about to read 4, iclass 24, count 0 2006.238.08:08:39.99#ibcon#read 4, iclass 24, count 0 2006.238.08:08:39.99#ibcon#about to read 5, iclass 24, count 0 2006.238.08:08:39.99#ibcon#read 5, iclass 24, count 0 2006.238.08:08:39.99#ibcon#about to read 6, iclass 24, count 0 2006.238.08:08:39.99#ibcon#read 6, iclass 24, count 0 2006.238.08:08:39.99#ibcon#end of sib2, iclass 24, count 0 2006.238.08:08:39.99#ibcon#*after write, iclass 24, count 0 2006.238.08:08:39.99#ibcon#*before return 0, iclass 24, count 0 2006.238.08:08:39.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:08:39.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:08:39.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.08:08:39.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.08:08:39.99$vc4f8/va=7,7 2006.238.08:08:39.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.238.08:08:39.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.238.08:08:39.99#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:39.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:08:40.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:08:40.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:08:40.05#ibcon#enter wrdev, iclass 26, count 2 2006.238.08:08:40.05#ibcon#first serial, iclass 26, count 2 2006.238.08:08:40.05#ibcon#enter sib2, iclass 26, count 2 2006.238.08:08:40.05#ibcon#flushed, iclass 26, count 2 2006.238.08:08:40.05#ibcon#about to write, iclass 26, count 2 2006.238.08:08:40.05#ibcon#wrote, iclass 26, count 2 2006.238.08:08:40.05#ibcon#about to read 3, iclass 26, count 2 2006.238.08:08:40.07#ibcon#read 3, iclass 26, count 2 2006.238.08:08:40.07#ibcon#about to read 4, iclass 26, count 2 2006.238.08:08:40.07#ibcon#read 4, iclass 26, count 2 2006.238.08:08:40.07#ibcon#about to read 5, iclass 26, count 2 2006.238.08:08:40.07#ibcon#read 5, iclass 26, count 2 2006.238.08:08:40.07#ibcon#about to read 6, iclass 26, count 2 2006.238.08:08:40.07#ibcon#read 6, iclass 26, count 2 2006.238.08:08:40.07#ibcon#end of sib2, iclass 26, count 2 2006.238.08:08:40.07#ibcon#*mode == 0, iclass 26, count 2 2006.238.08:08:40.07#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.238.08:08:40.07#ibcon#[25=AT07-07\r\n] 2006.238.08:08:40.07#ibcon#*before write, iclass 26, count 2 2006.238.08:08:40.07#ibcon#enter sib2, iclass 26, count 2 2006.238.08:08:40.07#ibcon#flushed, iclass 26, count 2 2006.238.08:08:40.07#ibcon#about to write, iclass 26, count 2 2006.238.08:08:40.07#ibcon#wrote, iclass 26, count 2 2006.238.08:08:40.07#ibcon#about to read 3, iclass 26, count 2 2006.238.08:08:40.10#ibcon#read 3, iclass 26, count 2 2006.238.08:08:40.10#ibcon#about to read 4, iclass 26, count 2 2006.238.08:08:40.10#ibcon#read 4, iclass 26, count 2 2006.238.08:08:40.10#ibcon#about to read 5, iclass 26, count 2 2006.238.08:08:40.10#ibcon#read 5, iclass 26, count 2 2006.238.08:08:40.10#ibcon#about to read 6, iclass 26, count 2 2006.238.08:08:40.10#ibcon#read 6, iclass 26, count 2 2006.238.08:08:40.10#ibcon#end of sib2, iclass 26, count 2 2006.238.08:08:40.10#ibcon#*after write, iclass 26, count 2 2006.238.08:08:40.10#ibcon#*before return 0, iclass 26, count 2 2006.238.08:08:40.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:08:40.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:08:40.10#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.238.08:08:40.10#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:40.10#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:08:40.22#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:08:40.22#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:08:40.22#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:08:40.22#ibcon#first serial, iclass 26, count 0 2006.238.08:08:40.22#ibcon#enter sib2, iclass 26, count 0 2006.238.08:08:40.22#ibcon#flushed, iclass 26, count 0 2006.238.08:08:40.22#ibcon#about to write, iclass 26, count 0 2006.238.08:08:40.22#ibcon#wrote, iclass 26, count 0 2006.238.08:08:40.22#ibcon#about to read 3, iclass 26, count 0 2006.238.08:08:40.24#ibcon#read 3, iclass 26, count 0 2006.238.08:08:40.24#ibcon#about to read 4, iclass 26, count 0 2006.238.08:08:40.24#ibcon#read 4, iclass 26, count 0 2006.238.08:08:40.24#ibcon#about to read 5, iclass 26, count 0 2006.238.08:08:40.24#ibcon#read 5, iclass 26, count 0 2006.238.08:08:40.24#ibcon#about to read 6, iclass 26, count 0 2006.238.08:08:40.24#ibcon#read 6, iclass 26, count 0 2006.238.08:08:40.24#ibcon#end of sib2, iclass 26, count 0 2006.238.08:08:40.24#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:08:40.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:08:40.24#ibcon#[25=USB\r\n] 2006.238.08:08:40.24#ibcon#*before write, iclass 26, count 0 2006.238.08:08:40.24#ibcon#enter sib2, iclass 26, count 0 2006.238.08:08:40.24#ibcon#flushed, iclass 26, count 0 2006.238.08:08:40.24#ibcon#about to write, iclass 26, count 0 2006.238.08:08:40.24#ibcon#wrote, iclass 26, count 0 2006.238.08:08:40.24#ibcon#about to read 3, iclass 26, count 0 2006.238.08:08:40.27#ibcon#read 3, iclass 26, count 0 2006.238.08:08:40.27#ibcon#about to read 4, iclass 26, count 0 2006.238.08:08:40.27#ibcon#read 4, iclass 26, count 0 2006.238.08:08:40.27#ibcon#about to read 5, iclass 26, count 0 2006.238.08:08:40.27#ibcon#read 5, iclass 26, count 0 2006.238.08:08:40.27#ibcon#about to read 6, iclass 26, count 0 2006.238.08:08:40.27#ibcon#read 6, iclass 26, count 0 2006.238.08:08:40.27#ibcon#end of sib2, iclass 26, count 0 2006.238.08:08:40.27#ibcon#*after write, iclass 26, count 0 2006.238.08:08:40.27#ibcon#*before return 0, iclass 26, count 0 2006.238.08:08:40.27#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:08:40.27#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:08:40.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:08:40.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:08:40.27$vc4f8/valo=8,852.99 2006.238.08:08:40.27#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.238.08:08:40.27#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.238.08:08:40.27#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:40.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:08:40.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:08:40.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:08:40.27#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:08:40.27#ibcon#first serial, iclass 28, count 0 2006.238.08:08:40.27#ibcon#enter sib2, iclass 28, count 0 2006.238.08:08:40.27#ibcon#flushed, iclass 28, count 0 2006.238.08:08:40.27#ibcon#about to write, iclass 28, count 0 2006.238.08:08:40.27#ibcon#wrote, iclass 28, count 0 2006.238.08:08:40.27#ibcon#about to read 3, iclass 28, count 0 2006.238.08:08:40.29#ibcon#read 3, iclass 28, count 0 2006.238.08:08:40.29#ibcon#about to read 4, iclass 28, count 0 2006.238.08:08:40.29#ibcon#read 4, iclass 28, count 0 2006.238.08:08:40.29#ibcon#about to read 5, iclass 28, count 0 2006.238.08:08:40.29#ibcon#read 5, iclass 28, count 0 2006.238.08:08:40.29#ibcon#about to read 6, iclass 28, count 0 2006.238.08:08:40.29#ibcon#read 6, iclass 28, count 0 2006.238.08:08:40.29#ibcon#end of sib2, iclass 28, count 0 2006.238.08:08:40.29#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:08:40.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:08:40.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:08:40.29#ibcon#*before write, iclass 28, count 0 2006.238.08:08:40.29#ibcon#enter sib2, iclass 28, count 0 2006.238.08:08:40.29#ibcon#flushed, iclass 28, count 0 2006.238.08:08:40.29#ibcon#about to write, iclass 28, count 0 2006.238.08:08:40.29#ibcon#wrote, iclass 28, count 0 2006.238.08:08:40.29#ibcon#about to read 3, iclass 28, count 0 2006.238.08:08:40.33#ibcon#read 3, iclass 28, count 0 2006.238.08:08:40.33#ibcon#about to read 4, iclass 28, count 0 2006.238.08:08:40.33#ibcon#read 4, iclass 28, count 0 2006.238.08:08:40.33#ibcon#about to read 5, iclass 28, count 0 2006.238.08:08:40.33#ibcon#read 5, iclass 28, count 0 2006.238.08:08:40.33#ibcon#about to read 6, iclass 28, count 0 2006.238.08:08:40.33#ibcon#read 6, iclass 28, count 0 2006.238.08:08:40.33#ibcon#end of sib2, iclass 28, count 0 2006.238.08:08:40.33#ibcon#*after write, iclass 28, count 0 2006.238.08:08:40.33#ibcon#*before return 0, iclass 28, count 0 2006.238.08:08:40.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:08:40.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:08:40.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:08:40.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:08:40.33$vc4f8/va=8,7 2006.238.08:08:40.33#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.238.08:08:40.33#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.238.08:08:40.33#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:40.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:08:40.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:08:40.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:08:40.39#ibcon#enter wrdev, iclass 30, count 2 2006.238.08:08:40.39#ibcon#first serial, iclass 30, count 2 2006.238.08:08:40.39#ibcon#enter sib2, iclass 30, count 2 2006.238.08:08:40.39#ibcon#flushed, iclass 30, count 2 2006.238.08:08:40.39#ibcon#about to write, iclass 30, count 2 2006.238.08:08:40.39#ibcon#wrote, iclass 30, count 2 2006.238.08:08:40.39#ibcon#about to read 3, iclass 30, count 2 2006.238.08:08:40.41#ibcon#read 3, iclass 30, count 2 2006.238.08:08:40.41#ibcon#about to read 4, iclass 30, count 2 2006.238.08:08:40.41#ibcon#read 4, iclass 30, count 2 2006.238.08:08:40.41#ibcon#about to read 5, iclass 30, count 2 2006.238.08:08:40.41#ibcon#read 5, iclass 30, count 2 2006.238.08:08:40.41#ibcon#about to read 6, iclass 30, count 2 2006.238.08:08:40.41#ibcon#read 6, iclass 30, count 2 2006.238.08:08:40.41#ibcon#end of sib2, iclass 30, count 2 2006.238.08:08:40.41#ibcon#*mode == 0, iclass 30, count 2 2006.238.08:08:40.41#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.238.08:08:40.41#ibcon#[25=AT08-07\r\n] 2006.238.08:08:40.41#ibcon#*before write, iclass 30, count 2 2006.238.08:08:40.41#ibcon#enter sib2, iclass 30, count 2 2006.238.08:08:40.41#ibcon#flushed, iclass 30, count 2 2006.238.08:08:40.41#ibcon#about to write, iclass 30, count 2 2006.238.08:08:40.41#ibcon#wrote, iclass 30, count 2 2006.238.08:08:40.41#ibcon#about to read 3, iclass 30, count 2 2006.238.08:08:40.44#ibcon#read 3, iclass 30, count 2 2006.238.08:08:40.44#ibcon#about to read 4, iclass 30, count 2 2006.238.08:08:40.44#ibcon#read 4, iclass 30, count 2 2006.238.08:08:40.44#ibcon#about to read 5, iclass 30, count 2 2006.238.08:08:40.44#ibcon#read 5, iclass 30, count 2 2006.238.08:08:40.44#ibcon#about to read 6, iclass 30, count 2 2006.238.08:08:40.44#ibcon#read 6, iclass 30, count 2 2006.238.08:08:40.44#ibcon#end of sib2, iclass 30, count 2 2006.238.08:08:40.44#ibcon#*after write, iclass 30, count 2 2006.238.08:08:40.44#ibcon#*before return 0, iclass 30, count 2 2006.238.08:08:40.44#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:08:40.44#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:08:40.44#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.238.08:08:40.44#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:40.44#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:08:40.56#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:08:40.56#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:08:40.56#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:08:40.56#ibcon#first serial, iclass 30, count 0 2006.238.08:08:40.56#ibcon#enter sib2, iclass 30, count 0 2006.238.08:08:40.56#ibcon#flushed, iclass 30, count 0 2006.238.08:08:40.56#ibcon#about to write, iclass 30, count 0 2006.238.08:08:40.56#ibcon#wrote, iclass 30, count 0 2006.238.08:08:40.56#ibcon#about to read 3, iclass 30, count 0 2006.238.08:08:40.58#ibcon#read 3, iclass 30, count 0 2006.238.08:08:40.58#ibcon#about to read 4, iclass 30, count 0 2006.238.08:08:40.58#ibcon#read 4, iclass 30, count 0 2006.238.08:08:40.58#ibcon#about to read 5, iclass 30, count 0 2006.238.08:08:40.58#ibcon#read 5, iclass 30, count 0 2006.238.08:08:40.58#ibcon#about to read 6, iclass 30, count 0 2006.238.08:08:40.58#ibcon#read 6, iclass 30, count 0 2006.238.08:08:40.58#ibcon#end of sib2, iclass 30, count 0 2006.238.08:08:40.58#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:08:40.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:08:40.58#ibcon#[25=USB\r\n] 2006.238.08:08:40.58#ibcon#*before write, iclass 30, count 0 2006.238.08:08:40.58#ibcon#enter sib2, iclass 30, count 0 2006.238.08:08:40.58#ibcon#flushed, iclass 30, count 0 2006.238.08:08:40.58#ibcon#about to write, iclass 30, count 0 2006.238.08:08:40.58#ibcon#wrote, iclass 30, count 0 2006.238.08:08:40.58#ibcon#about to read 3, iclass 30, count 0 2006.238.08:08:40.61#ibcon#read 3, iclass 30, count 0 2006.238.08:08:40.61#ibcon#about to read 4, iclass 30, count 0 2006.238.08:08:40.61#ibcon#read 4, iclass 30, count 0 2006.238.08:08:40.61#ibcon#about to read 5, iclass 30, count 0 2006.238.08:08:40.61#ibcon#read 5, iclass 30, count 0 2006.238.08:08:40.61#ibcon#about to read 6, iclass 30, count 0 2006.238.08:08:40.61#ibcon#read 6, iclass 30, count 0 2006.238.08:08:40.61#ibcon#end of sib2, iclass 30, count 0 2006.238.08:08:40.61#ibcon#*after write, iclass 30, count 0 2006.238.08:08:40.61#ibcon#*before return 0, iclass 30, count 0 2006.238.08:08:40.61#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:08:40.61#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:08:40.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:08:40.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:08:40.61$vc4f8/vblo=1,632.99 2006.238.08:08:40.61#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.08:08:40.61#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.08:08:40.61#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:40.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:08:40.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:08:40.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:08:40.61#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:08:40.61#ibcon#first serial, iclass 32, count 0 2006.238.08:08:40.61#ibcon#enter sib2, iclass 32, count 0 2006.238.08:08:40.61#ibcon#flushed, iclass 32, count 0 2006.238.08:08:40.61#ibcon#about to write, iclass 32, count 0 2006.238.08:08:40.61#ibcon#wrote, iclass 32, count 0 2006.238.08:08:40.61#ibcon#about to read 3, iclass 32, count 0 2006.238.08:08:40.63#ibcon#read 3, iclass 32, count 0 2006.238.08:08:40.63#ibcon#about to read 4, iclass 32, count 0 2006.238.08:08:40.63#ibcon#read 4, iclass 32, count 0 2006.238.08:08:40.63#ibcon#about to read 5, iclass 32, count 0 2006.238.08:08:40.63#ibcon#read 5, iclass 32, count 0 2006.238.08:08:40.63#ibcon#about to read 6, iclass 32, count 0 2006.238.08:08:40.63#ibcon#read 6, iclass 32, count 0 2006.238.08:08:40.63#ibcon#end of sib2, iclass 32, count 0 2006.238.08:08:40.63#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:08:40.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:08:40.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:08:40.63#ibcon#*before write, iclass 32, count 0 2006.238.08:08:40.63#ibcon#enter sib2, iclass 32, count 0 2006.238.08:08:40.63#ibcon#flushed, iclass 32, count 0 2006.238.08:08:40.63#ibcon#about to write, iclass 32, count 0 2006.238.08:08:40.63#ibcon#wrote, iclass 32, count 0 2006.238.08:08:40.63#ibcon#about to read 3, iclass 32, count 0 2006.238.08:08:40.67#ibcon#read 3, iclass 32, count 0 2006.238.08:08:40.67#ibcon#about to read 4, iclass 32, count 0 2006.238.08:08:40.67#ibcon#read 4, iclass 32, count 0 2006.238.08:08:40.67#ibcon#about to read 5, iclass 32, count 0 2006.238.08:08:40.67#ibcon#read 5, iclass 32, count 0 2006.238.08:08:40.67#ibcon#about to read 6, iclass 32, count 0 2006.238.08:08:40.67#ibcon#read 6, iclass 32, count 0 2006.238.08:08:40.67#ibcon#end of sib2, iclass 32, count 0 2006.238.08:08:40.67#ibcon#*after write, iclass 32, count 0 2006.238.08:08:40.67#ibcon#*before return 0, iclass 32, count 0 2006.238.08:08:40.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:08:40.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:08:40.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:08:40.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:08:40.67$vc4f8/vb=1,4 2006.238.08:08:40.67#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.238.08:08:40.67#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.238.08:08:40.67#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:40.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:08:40.67#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:08:40.67#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:08:40.67#ibcon#enter wrdev, iclass 34, count 2 2006.238.08:08:40.67#ibcon#first serial, iclass 34, count 2 2006.238.08:08:40.67#ibcon#enter sib2, iclass 34, count 2 2006.238.08:08:40.67#ibcon#flushed, iclass 34, count 2 2006.238.08:08:40.67#ibcon#about to write, iclass 34, count 2 2006.238.08:08:40.67#ibcon#wrote, iclass 34, count 2 2006.238.08:08:40.67#ibcon#about to read 3, iclass 34, count 2 2006.238.08:08:40.69#ibcon#read 3, iclass 34, count 2 2006.238.08:08:40.69#ibcon#about to read 4, iclass 34, count 2 2006.238.08:08:40.69#ibcon#read 4, iclass 34, count 2 2006.238.08:08:40.69#ibcon#about to read 5, iclass 34, count 2 2006.238.08:08:40.69#ibcon#read 5, iclass 34, count 2 2006.238.08:08:40.69#ibcon#about to read 6, iclass 34, count 2 2006.238.08:08:40.69#ibcon#read 6, iclass 34, count 2 2006.238.08:08:40.69#ibcon#end of sib2, iclass 34, count 2 2006.238.08:08:40.69#ibcon#*mode == 0, iclass 34, count 2 2006.238.08:08:40.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.238.08:08:40.69#ibcon#[27=AT01-04\r\n] 2006.238.08:08:40.69#ibcon#*before write, iclass 34, count 2 2006.238.08:08:40.69#ibcon#enter sib2, iclass 34, count 2 2006.238.08:08:40.69#ibcon#flushed, iclass 34, count 2 2006.238.08:08:40.69#ibcon#about to write, iclass 34, count 2 2006.238.08:08:40.69#ibcon#wrote, iclass 34, count 2 2006.238.08:08:40.69#ibcon#about to read 3, iclass 34, count 2 2006.238.08:08:40.72#ibcon#read 3, iclass 34, count 2 2006.238.08:08:40.72#ibcon#about to read 4, iclass 34, count 2 2006.238.08:08:40.72#ibcon#read 4, iclass 34, count 2 2006.238.08:08:40.72#ibcon#about to read 5, iclass 34, count 2 2006.238.08:08:40.72#ibcon#read 5, iclass 34, count 2 2006.238.08:08:40.72#ibcon#about to read 6, iclass 34, count 2 2006.238.08:08:40.72#ibcon#read 6, iclass 34, count 2 2006.238.08:08:40.72#ibcon#end of sib2, iclass 34, count 2 2006.238.08:08:40.72#ibcon#*after write, iclass 34, count 2 2006.238.08:08:40.72#ibcon#*before return 0, iclass 34, count 2 2006.238.08:08:40.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:08:40.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:08:40.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.238.08:08:40.72#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:40.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:08:40.84#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:08:40.84#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:08:40.84#ibcon#enter wrdev, iclass 34, count 0 2006.238.08:08:40.84#ibcon#first serial, iclass 34, count 0 2006.238.08:08:40.84#ibcon#enter sib2, iclass 34, count 0 2006.238.08:08:40.84#ibcon#flushed, iclass 34, count 0 2006.238.08:08:40.84#ibcon#about to write, iclass 34, count 0 2006.238.08:08:40.84#ibcon#wrote, iclass 34, count 0 2006.238.08:08:40.84#ibcon#about to read 3, iclass 34, count 0 2006.238.08:08:40.86#ibcon#read 3, iclass 34, count 0 2006.238.08:08:40.86#ibcon#about to read 4, iclass 34, count 0 2006.238.08:08:40.86#ibcon#read 4, iclass 34, count 0 2006.238.08:08:40.86#ibcon#about to read 5, iclass 34, count 0 2006.238.08:08:40.86#ibcon#read 5, iclass 34, count 0 2006.238.08:08:40.86#ibcon#about to read 6, iclass 34, count 0 2006.238.08:08:40.86#ibcon#read 6, iclass 34, count 0 2006.238.08:08:40.86#ibcon#end of sib2, iclass 34, count 0 2006.238.08:08:40.86#ibcon#*mode == 0, iclass 34, count 0 2006.238.08:08:40.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.08:08:40.86#ibcon#[27=USB\r\n] 2006.238.08:08:40.86#ibcon#*before write, iclass 34, count 0 2006.238.08:08:40.86#ibcon#enter sib2, iclass 34, count 0 2006.238.08:08:40.86#ibcon#flushed, iclass 34, count 0 2006.238.08:08:40.86#ibcon#about to write, iclass 34, count 0 2006.238.08:08:40.86#ibcon#wrote, iclass 34, count 0 2006.238.08:08:40.86#ibcon#about to read 3, iclass 34, count 0 2006.238.08:08:40.89#ibcon#read 3, iclass 34, count 0 2006.238.08:08:40.89#ibcon#about to read 4, iclass 34, count 0 2006.238.08:08:40.89#ibcon#read 4, iclass 34, count 0 2006.238.08:08:40.89#ibcon#about to read 5, iclass 34, count 0 2006.238.08:08:40.89#ibcon#read 5, iclass 34, count 0 2006.238.08:08:40.89#ibcon#about to read 6, iclass 34, count 0 2006.238.08:08:40.89#ibcon#read 6, iclass 34, count 0 2006.238.08:08:40.89#ibcon#end of sib2, iclass 34, count 0 2006.238.08:08:40.89#ibcon#*after write, iclass 34, count 0 2006.238.08:08:40.89#ibcon#*before return 0, iclass 34, count 0 2006.238.08:08:40.89#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:08:40.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:08:40.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.08:08:40.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.08:08:40.89$vc4f8/vblo=2,640.99 2006.238.08:08:40.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.08:08:40.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.08:08:40.89#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:40.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:08:40.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:08:40.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:08:40.89#ibcon#enter wrdev, iclass 36, count 0 2006.238.08:08:40.89#ibcon#first serial, iclass 36, count 0 2006.238.08:08:40.89#ibcon#enter sib2, iclass 36, count 0 2006.238.08:08:40.89#ibcon#flushed, iclass 36, count 0 2006.238.08:08:40.89#ibcon#about to write, iclass 36, count 0 2006.238.08:08:40.89#ibcon#wrote, iclass 36, count 0 2006.238.08:08:40.89#ibcon#about to read 3, iclass 36, count 0 2006.238.08:08:40.91#ibcon#read 3, iclass 36, count 0 2006.238.08:08:40.91#ibcon#about to read 4, iclass 36, count 0 2006.238.08:08:40.91#ibcon#read 4, iclass 36, count 0 2006.238.08:08:40.91#ibcon#about to read 5, iclass 36, count 0 2006.238.08:08:40.91#ibcon#read 5, iclass 36, count 0 2006.238.08:08:40.91#ibcon#about to read 6, iclass 36, count 0 2006.238.08:08:40.91#ibcon#read 6, iclass 36, count 0 2006.238.08:08:40.91#ibcon#end of sib2, iclass 36, count 0 2006.238.08:08:40.91#ibcon#*mode == 0, iclass 36, count 0 2006.238.08:08:40.91#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.08:08:40.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:08:40.91#ibcon#*before write, iclass 36, count 0 2006.238.08:08:40.91#ibcon#enter sib2, iclass 36, count 0 2006.238.08:08:40.91#ibcon#flushed, iclass 36, count 0 2006.238.08:08:40.91#ibcon#about to write, iclass 36, count 0 2006.238.08:08:40.91#ibcon#wrote, iclass 36, count 0 2006.238.08:08:40.91#ibcon#about to read 3, iclass 36, count 0 2006.238.08:08:40.96#ibcon#read 3, iclass 36, count 0 2006.238.08:08:40.96#ibcon#about to read 4, iclass 36, count 0 2006.238.08:08:40.96#ibcon#read 4, iclass 36, count 0 2006.238.08:08:40.96#ibcon#about to read 5, iclass 36, count 0 2006.238.08:08:40.96#ibcon#read 5, iclass 36, count 0 2006.238.08:08:40.96#ibcon#about to read 6, iclass 36, count 0 2006.238.08:08:40.96#ibcon#read 6, iclass 36, count 0 2006.238.08:08:40.96#ibcon#end of sib2, iclass 36, count 0 2006.238.08:08:40.96#ibcon#*after write, iclass 36, count 0 2006.238.08:08:40.96#ibcon#*before return 0, iclass 36, count 0 2006.238.08:08:40.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:08:40.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:08:40.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.08:08:40.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.08:08:40.96$vc4f8/vb=2,4 2006.238.08:08:40.96#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.238.08:08:40.96#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.238.08:08:40.96#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:40.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:08:41.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:08:41.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:08:41.00#ibcon#enter wrdev, iclass 38, count 2 2006.238.08:08:41.00#ibcon#first serial, iclass 38, count 2 2006.238.08:08:41.00#ibcon#enter sib2, iclass 38, count 2 2006.238.08:08:41.00#ibcon#flushed, iclass 38, count 2 2006.238.08:08:41.00#ibcon#about to write, iclass 38, count 2 2006.238.08:08:41.00#ibcon#wrote, iclass 38, count 2 2006.238.08:08:41.00#ibcon#about to read 3, iclass 38, count 2 2006.238.08:08:41.02#ibcon#read 3, iclass 38, count 2 2006.238.08:08:41.02#ibcon#about to read 4, iclass 38, count 2 2006.238.08:08:41.02#ibcon#read 4, iclass 38, count 2 2006.238.08:08:41.02#ibcon#about to read 5, iclass 38, count 2 2006.238.08:08:41.02#ibcon#read 5, iclass 38, count 2 2006.238.08:08:41.02#ibcon#about to read 6, iclass 38, count 2 2006.238.08:08:41.02#ibcon#read 6, iclass 38, count 2 2006.238.08:08:41.02#ibcon#end of sib2, iclass 38, count 2 2006.238.08:08:41.02#ibcon#*mode == 0, iclass 38, count 2 2006.238.08:08:41.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.238.08:08:41.02#ibcon#[27=AT02-04\r\n] 2006.238.08:08:41.02#ibcon#*before write, iclass 38, count 2 2006.238.08:08:41.02#ibcon#enter sib2, iclass 38, count 2 2006.238.08:08:41.02#ibcon#flushed, iclass 38, count 2 2006.238.08:08:41.02#ibcon#about to write, iclass 38, count 2 2006.238.08:08:41.02#ibcon#wrote, iclass 38, count 2 2006.238.08:08:41.02#ibcon#about to read 3, iclass 38, count 2 2006.238.08:08:41.05#ibcon#read 3, iclass 38, count 2 2006.238.08:08:41.05#ibcon#about to read 4, iclass 38, count 2 2006.238.08:08:41.05#ibcon#read 4, iclass 38, count 2 2006.238.08:08:41.05#ibcon#about to read 5, iclass 38, count 2 2006.238.08:08:41.05#ibcon#read 5, iclass 38, count 2 2006.238.08:08:41.05#ibcon#about to read 6, iclass 38, count 2 2006.238.08:08:41.05#ibcon#read 6, iclass 38, count 2 2006.238.08:08:41.05#ibcon#end of sib2, iclass 38, count 2 2006.238.08:08:41.05#ibcon#*after write, iclass 38, count 2 2006.238.08:08:41.05#ibcon#*before return 0, iclass 38, count 2 2006.238.08:08:41.05#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:08:41.05#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:08:41.05#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.238.08:08:41.05#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:41.05#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:08:41.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:08:41.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:08:41.17#ibcon#enter wrdev, iclass 38, count 0 2006.238.08:08:41.17#ibcon#first serial, iclass 38, count 0 2006.238.08:08:41.17#ibcon#enter sib2, iclass 38, count 0 2006.238.08:08:41.17#ibcon#flushed, iclass 38, count 0 2006.238.08:08:41.17#ibcon#about to write, iclass 38, count 0 2006.238.08:08:41.17#ibcon#wrote, iclass 38, count 0 2006.238.08:08:41.17#ibcon#about to read 3, iclass 38, count 0 2006.238.08:08:41.19#ibcon#read 3, iclass 38, count 0 2006.238.08:08:41.19#ibcon#about to read 4, iclass 38, count 0 2006.238.08:08:41.19#ibcon#read 4, iclass 38, count 0 2006.238.08:08:41.19#ibcon#about to read 5, iclass 38, count 0 2006.238.08:08:41.19#ibcon#read 5, iclass 38, count 0 2006.238.08:08:41.19#ibcon#about to read 6, iclass 38, count 0 2006.238.08:08:41.19#ibcon#read 6, iclass 38, count 0 2006.238.08:08:41.19#ibcon#end of sib2, iclass 38, count 0 2006.238.08:08:41.19#ibcon#*mode == 0, iclass 38, count 0 2006.238.08:08:41.19#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.08:08:41.19#ibcon#[27=USB\r\n] 2006.238.08:08:41.19#ibcon#*before write, iclass 38, count 0 2006.238.08:08:41.19#ibcon#enter sib2, iclass 38, count 0 2006.238.08:08:41.19#ibcon#flushed, iclass 38, count 0 2006.238.08:08:41.19#ibcon#about to write, iclass 38, count 0 2006.238.08:08:41.19#ibcon#wrote, iclass 38, count 0 2006.238.08:08:41.19#ibcon#about to read 3, iclass 38, count 0 2006.238.08:08:41.22#ibcon#read 3, iclass 38, count 0 2006.238.08:08:41.22#ibcon#about to read 4, iclass 38, count 0 2006.238.08:08:41.22#ibcon#read 4, iclass 38, count 0 2006.238.08:08:41.22#ibcon#about to read 5, iclass 38, count 0 2006.238.08:08:41.22#ibcon#read 5, iclass 38, count 0 2006.238.08:08:41.22#ibcon#about to read 6, iclass 38, count 0 2006.238.08:08:41.22#ibcon#read 6, iclass 38, count 0 2006.238.08:08:41.22#ibcon#end of sib2, iclass 38, count 0 2006.238.08:08:41.22#ibcon#*after write, iclass 38, count 0 2006.238.08:08:41.22#ibcon#*before return 0, iclass 38, count 0 2006.238.08:08:41.22#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:08:41.22#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:08:41.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.08:08:41.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.08:08:41.22$vc4f8/vblo=3,656.99 2006.238.08:08:41.22#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.08:08:41.22#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.08:08:41.22#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:41.22#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:08:41.22#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:08:41.22#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:08:41.22#ibcon#enter wrdev, iclass 40, count 0 2006.238.08:08:41.22#ibcon#first serial, iclass 40, count 0 2006.238.08:08:41.22#ibcon#enter sib2, iclass 40, count 0 2006.238.08:08:41.22#ibcon#flushed, iclass 40, count 0 2006.238.08:08:41.22#ibcon#about to write, iclass 40, count 0 2006.238.08:08:41.22#ibcon#wrote, iclass 40, count 0 2006.238.08:08:41.22#ibcon#about to read 3, iclass 40, count 0 2006.238.08:08:41.24#ibcon#read 3, iclass 40, count 0 2006.238.08:08:41.24#ibcon#about to read 4, iclass 40, count 0 2006.238.08:08:41.24#ibcon#read 4, iclass 40, count 0 2006.238.08:08:41.24#ibcon#about to read 5, iclass 40, count 0 2006.238.08:08:41.24#ibcon#read 5, iclass 40, count 0 2006.238.08:08:41.24#ibcon#about to read 6, iclass 40, count 0 2006.238.08:08:41.24#ibcon#read 6, iclass 40, count 0 2006.238.08:08:41.24#ibcon#end of sib2, iclass 40, count 0 2006.238.08:08:41.24#ibcon#*mode == 0, iclass 40, count 0 2006.238.08:08:41.24#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.08:08:41.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:08:41.24#ibcon#*before write, iclass 40, count 0 2006.238.08:08:41.24#ibcon#enter sib2, iclass 40, count 0 2006.238.08:08:41.24#ibcon#flushed, iclass 40, count 0 2006.238.08:08:41.24#ibcon#about to write, iclass 40, count 0 2006.238.08:08:41.24#ibcon#wrote, iclass 40, count 0 2006.238.08:08:41.24#ibcon#about to read 3, iclass 40, count 0 2006.238.08:08:41.28#ibcon#read 3, iclass 40, count 0 2006.238.08:08:41.28#ibcon#about to read 4, iclass 40, count 0 2006.238.08:08:41.28#ibcon#read 4, iclass 40, count 0 2006.238.08:08:41.28#ibcon#about to read 5, iclass 40, count 0 2006.238.08:08:41.28#ibcon#read 5, iclass 40, count 0 2006.238.08:08:41.28#ibcon#about to read 6, iclass 40, count 0 2006.238.08:08:41.28#ibcon#read 6, iclass 40, count 0 2006.238.08:08:41.28#ibcon#end of sib2, iclass 40, count 0 2006.238.08:08:41.28#ibcon#*after write, iclass 40, count 0 2006.238.08:08:41.28#ibcon#*before return 0, iclass 40, count 0 2006.238.08:08:41.28#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:08:41.28#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:08:41.28#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.08:08:41.28#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.08:08:41.28$vc4f8/vb=3,4 2006.238.08:08:41.28#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.238.08:08:41.28#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.238.08:08:41.28#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:41.28#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:08:41.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:08:41.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:08:41.34#ibcon#enter wrdev, iclass 4, count 2 2006.238.08:08:41.34#ibcon#first serial, iclass 4, count 2 2006.238.08:08:41.34#ibcon#enter sib2, iclass 4, count 2 2006.238.08:08:41.34#ibcon#flushed, iclass 4, count 2 2006.238.08:08:41.34#ibcon#about to write, iclass 4, count 2 2006.238.08:08:41.34#ibcon#wrote, iclass 4, count 2 2006.238.08:08:41.34#ibcon#about to read 3, iclass 4, count 2 2006.238.08:08:41.36#ibcon#read 3, iclass 4, count 2 2006.238.08:08:41.36#ibcon#about to read 4, iclass 4, count 2 2006.238.08:08:41.36#ibcon#read 4, iclass 4, count 2 2006.238.08:08:41.36#ibcon#about to read 5, iclass 4, count 2 2006.238.08:08:41.36#ibcon#read 5, iclass 4, count 2 2006.238.08:08:41.36#ibcon#about to read 6, iclass 4, count 2 2006.238.08:08:41.36#ibcon#read 6, iclass 4, count 2 2006.238.08:08:41.36#ibcon#end of sib2, iclass 4, count 2 2006.238.08:08:41.36#ibcon#*mode == 0, iclass 4, count 2 2006.238.08:08:41.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.238.08:08:41.36#ibcon#[27=AT03-04\r\n] 2006.238.08:08:41.36#ibcon#*before write, iclass 4, count 2 2006.238.08:08:41.36#ibcon#enter sib2, iclass 4, count 2 2006.238.08:08:41.36#ibcon#flushed, iclass 4, count 2 2006.238.08:08:41.36#ibcon#about to write, iclass 4, count 2 2006.238.08:08:41.36#ibcon#wrote, iclass 4, count 2 2006.238.08:08:41.36#ibcon#about to read 3, iclass 4, count 2 2006.238.08:08:41.39#ibcon#read 3, iclass 4, count 2 2006.238.08:08:41.39#ibcon#about to read 4, iclass 4, count 2 2006.238.08:08:41.39#ibcon#read 4, iclass 4, count 2 2006.238.08:08:41.39#ibcon#about to read 5, iclass 4, count 2 2006.238.08:08:41.39#ibcon#read 5, iclass 4, count 2 2006.238.08:08:41.39#ibcon#about to read 6, iclass 4, count 2 2006.238.08:08:41.39#ibcon#read 6, iclass 4, count 2 2006.238.08:08:41.39#ibcon#end of sib2, iclass 4, count 2 2006.238.08:08:41.39#ibcon#*after write, iclass 4, count 2 2006.238.08:08:41.39#ibcon#*before return 0, iclass 4, count 2 2006.238.08:08:41.39#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:08:41.39#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:08:41.39#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.238.08:08:41.39#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:41.39#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:08:41.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:08:41.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:08:41.51#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:08:41.51#ibcon#first serial, iclass 4, count 0 2006.238.08:08:41.51#ibcon#enter sib2, iclass 4, count 0 2006.238.08:08:41.51#ibcon#flushed, iclass 4, count 0 2006.238.08:08:41.51#ibcon#about to write, iclass 4, count 0 2006.238.08:08:41.51#ibcon#wrote, iclass 4, count 0 2006.238.08:08:41.51#ibcon#about to read 3, iclass 4, count 0 2006.238.08:08:41.53#ibcon#read 3, iclass 4, count 0 2006.238.08:08:41.53#ibcon#about to read 4, iclass 4, count 0 2006.238.08:08:41.53#ibcon#read 4, iclass 4, count 0 2006.238.08:08:41.53#ibcon#about to read 5, iclass 4, count 0 2006.238.08:08:41.53#ibcon#read 5, iclass 4, count 0 2006.238.08:08:41.53#ibcon#about to read 6, iclass 4, count 0 2006.238.08:08:41.53#ibcon#read 6, iclass 4, count 0 2006.238.08:08:41.53#ibcon#end of sib2, iclass 4, count 0 2006.238.08:08:41.53#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:08:41.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:08:41.53#ibcon#[27=USB\r\n] 2006.238.08:08:41.53#ibcon#*before write, iclass 4, count 0 2006.238.08:08:41.53#ibcon#enter sib2, iclass 4, count 0 2006.238.08:08:41.53#ibcon#flushed, iclass 4, count 0 2006.238.08:08:41.53#ibcon#about to write, iclass 4, count 0 2006.238.08:08:41.53#ibcon#wrote, iclass 4, count 0 2006.238.08:08:41.53#ibcon#about to read 3, iclass 4, count 0 2006.238.08:08:41.56#ibcon#read 3, iclass 4, count 0 2006.238.08:08:41.56#ibcon#about to read 4, iclass 4, count 0 2006.238.08:08:41.56#ibcon#read 4, iclass 4, count 0 2006.238.08:08:41.56#ibcon#about to read 5, iclass 4, count 0 2006.238.08:08:41.56#ibcon#read 5, iclass 4, count 0 2006.238.08:08:41.56#ibcon#about to read 6, iclass 4, count 0 2006.238.08:08:41.56#ibcon#read 6, iclass 4, count 0 2006.238.08:08:41.56#ibcon#end of sib2, iclass 4, count 0 2006.238.08:08:41.56#ibcon#*after write, iclass 4, count 0 2006.238.08:08:41.56#ibcon#*before return 0, iclass 4, count 0 2006.238.08:08:41.56#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:08:41.56#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:08:41.56#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:08:41.56#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:08:41.56$vc4f8/vblo=4,712.99 2006.238.08:08:41.56#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.238.08:08:41.56#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.238.08:08:41.56#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:41.56#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:08:41.56#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:08:41.56#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:08:41.56#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:08:41.56#ibcon#first serial, iclass 6, count 0 2006.238.08:08:41.56#ibcon#enter sib2, iclass 6, count 0 2006.238.08:08:41.56#ibcon#flushed, iclass 6, count 0 2006.238.08:08:41.56#ibcon#about to write, iclass 6, count 0 2006.238.08:08:41.56#ibcon#wrote, iclass 6, count 0 2006.238.08:08:41.56#ibcon#about to read 3, iclass 6, count 0 2006.238.08:08:41.58#ibcon#read 3, iclass 6, count 0 2006.238.08:08:41.58#ibcon#about to read 4, iclass 6, count 0 2006.238.08:08:41.58#ibcon#read 4, iclass 6, count 0 2006.238.08:08:41.58#ibcon#about to read 5, iclass 6, count 0 2006.238.08:08:41.58#ibcon#read 5, iclass 6, count 0 2006.238.08:08:41.58#ibcon#about to read 6, iclass 6, count 0 2006.238.08:08:41.58#ibcon#read 6, iclass 6, count 0 2006.238.08:08:41.58#ibcon#end of sib2, iclass 6, count 0 2006.238.08:08:41.58#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:08:41.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:08:41.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:08:41.58#ibcon#*before write, iclass 6, count 0 2006.238.08:08:41.58#ibcon#enter sib2, iclass 6, count 0 2006.238.08:08:41.58#ibcon#flushed, iclass 6, count 0 2006.238.08:08:41.58#ibcon#about to write, iclass 6, count 0 2006.238.08:08:41.58#ibcon#wrote, iclass 6, count 0 2006.238.08:08:41.58#ibcon#about to read 3, iclass 6, count 0 2006.238.08:08:41.62#ibcon#read 3, iclass 6, count 0 2006.238.08:08:41.62#ibcon#about to read 4, iclass 6, count 0 2006.238.08:08:41.62#ibcon#read 4, iclass 6, count 0 2006.238.08:08:41.62#ibcon#about to read 5, iclass 6, count 0 2006.238.08:08:41.62#ibcon#read 5, iclass 6, count 0 2006.238.08:08:41.62#ibcon#about to read 6, iclass 6, count 0 2006.238.08:08:41.62#ibcon#read 6, iclass 6, count 0 2006.238.08:08:41.62#ibcon#end of sib2, iclass 6, count 0 2006.238.08:08:41.62#ibcon#*after write, iclass 6, count 0 2006.238.08:08:41.62#ibcon#*before return 0, iclass 6, count 0 2006.238.08:08:41.62#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:08:41.62#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:08:41.62#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:08:41.62#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:08:41.62$vc4f8/vb=4,4 2006.238.08:08:41.62#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.238.08:08:41.62#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.238.08:08:41.62#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:41.62#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:08:41.68#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:08:41.68#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:08:41.68#ibcon#enter wrdev, iclass 10, count 2 2006.238.08:08:41.68#ibcon#first serial, iclass 10, count 2 2006.238.08:08:41.68#ibcon#enter sib2, iclass 10, count 2 2006.238.08:08:41.68#ibcon#flushed, iclass 10, count 2 2006.238.08:08:41.68#ibcon#about to write, iclass 10, count 2 2006.238.08:08:41.68#ibcon#wrote, iclass 10, count 2 2006.238.08:08:41.68#ibcon#about to read 3, iclass 10, count 2 2006.238.08:08:41.70#ibcon#read 3, iclass 10, count 2 2006.238.08:08:41.70#ibcon#about to read 4, iclass 10, count 2 2006.238.08:08:41.70#ibcon#read 4, iclass 10, count 2 2006.238.08:08:41.70#ibcon#about to read 5, iclass 10, count 2 2006.238.08:08:41.70#ibcon#read 5, iclass 10, count 2 2006.238.08:08:41.70#ibcon#about to read 6, iclass 10, count 2 2006.238.08:08:41.70#ibcon#read 6, iclass 10, count 2 2006.238.08:08:41.70#ibcon#end of sib2, iclass 10, count 2 2006.238.08:08:41.70#ibcon#*mode == 0, iclass 10, count 2 2006.238.08:08:41.70#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.238.08:08:41.70#ibcon#[27=AT04-04\r\n] 2006.238.08:08:41.70#ibcon#*before write, iclass 10, count 2 2006.238.08:08:41.70#ibcon#enter sib2, iclass 10, count 2 2006.238.08:08:41.70#ibcon#flushed, iclass 10, count 2 2006.238.08:08:41.70#ibcon#about to write, iclass 10, count 2 2006.238.08:08:41.70#ibcon#wrote, iclass 10, count 2 2006.238.08:08:41.70#ibcon#about to read 3, iclass 10, count 2 2006.238.08:08:41.73#ibcon#read 3, iclass 10, count 2 2006.238.08:08:41.73#ibcon#about to read 4, iclass 10, count 2 2006.238.08:08:41.73#ibcon#read 4, iclass 10, count 2 2006.238.08:08:41.73#ibcon#about to read 5, iclass 10, count 2 2006.238.08:08:41.73#ibcon#read 5, iclass 10, count 2 2006.238.08:08:41.73#ibcon#about to read 6, iclass 10, count 2 2006.238.08:08:41.73#ibcon#read 6, iclass 10, count 2 2006.238.08:08:41.73#ibcon#end of sib2, iclass 10, count 2 2006.238.08:08:41.73#ibcon#*after write, iclass 10, count 2 2006.238.08:08:41.73#ibcon#*before return 0, iclass 10, count 2 2006.238.08:08:41.73#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:08:41.73#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:08:41.73#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.238.08:08:41.73#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:41.73#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:08:41.85#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:08:41.85#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:08:41.85#ibcon#enter wrdev, iclass 10, count 0 2006.238.08:08:41.85#ibcon#first serial, iclass 10, count 0 2006.238.08:08:41.85#ibcon#enter sib2, iclass 10, count 0 2006.238.08:08:41.85#ibcon#flushed, iclass 10, count 0 2006.238.08:08:41.85#ibcon#about to write, iclass 10, count 0 2006.238.08:08:41.85#ibcon#wrote, iclass 10, count 0 2006.238.08:08:41.85#ibcon#about to read 3, iclass 10, count 0 2006.238.08:08:41.87#ibcon#read 3, iclass 10, count 0 2006.238.08:08:41.87#ibcon#about to read 4, iclass 10, count 0 2006.238.08:08:41.87#ibcon#read 4, iclass 10, count 0 2006.238.08:08:41.87#ibcon#about to read 5, iclass 10, count 0 2006.238.08:08:41.87#ibcon#read 5, iclass 10, count 0 2006.238.08:08:41.87#ibcon#about to read 6, iclass 10, count 0 2006.238.08:08:41.87#ibcon#read 6, iclass 10, count 0 2006.238.08:08:41.87#ibcon#end of sib2, iclass 10, count 0 2006.238.08:08:41.87#ibcon#*mode == 0, iclass 10, count 0 2006.238.08:08:41.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.08:08:41.87#ibcon#[27=USB\r\n] 2006.238.08:08:41.87#ibcon#*before write, iclass 10, count 0 2006.238.08:08:41.87#ibcon#enter sib2, iclass 10, count 0 2006.238.08:08:41.87#ibcon#flushed, iclass 10, count 0 2006.238.08:08:41.87#ibcon#about to write, iclass 10, count 0 2006.238.08:08:41.87#ibcon#wrote, iclass 10, count 0 2006.238.08:08:41.87#ibcon#about to read 3, iclass 10, count 0 2006.238.08:08:41.90#ibcon#read 3, iclass 10, count 0 2006.238.08:08:41.90#ibcon#about to read 4, iclass 10, count 0 2006.238.08:08:41.90#ibcon#read 4, iclass 10, count 0 2006.238.08:08:41.90#ibcon#about to read 5, iclass 10, count 0 2006.238.08:08:41.90#ibcon#read 5, iclass 10, count 0 2006.238.08:08:41.90#ibcon#about to read 6, iclass 10, count 0 2006.238.08:08:41.90#ibcon#read 6, iclass 10, count 0 2006.238.08:08:41.90#ibcon#end of sib2, iclass 10, count 0 2006.238.08:08:41.90#ibcon#*after write, iclass 10, count 0 2006.238.08:08:41.90#ibcon#*before return 0, iclass 10, count 0 2006.238.08:08:41.90#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:08:41.90#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:08:41.90#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.08:08:41.90#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.08:08:41.90$vc4f8/vblo=5,744.99 2006.238.08:08:41.90#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.238.08:08:41.90#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.238.08:08:41.90#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:41.90#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:08:41.90#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:08:41.90#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:08:41.90#ibcon#enter wrdev, iclass 12, count 0 2006.238.08:08:41.90#ibcon#first serial, iclass 12, count 0 2006.238.08:08:41.90#ibcon#enter sib2, iclass 12, count 0 2006.238.08:08:41.90#ibcon#flushed, iclass 12, count 0 2006.238.08:08:41.90#ibcon#about to write, iclass 12, count 0 2006.238.08:08:41.90#ibcon#wrote, iclass 12, count 0 2006.238.08:08:41.90#ibcon#about to read 3, iclass 12, count 0 2006.238.08:08:41.92#ibcon#read 3, iclass 12, count 0 2006.238.08:08:41.92#ibcon#about to read 4, iclass 12, count 0 2006.238.08:08:41.92#ibcon#read 4, iclass 12, count 0 2006.238.08:08:41.92#ibcon#about to read 5, iclass 12, count 0 2006.238.08:08:41.92#ibcon#read 5, iclass 12, count 0 2006.238.08:08:41.92#ibcon#about to read 6, iclass 12, count 0 2006.238.08:08:41.92#ibcon#read 6, iclass 12, count 0 2006.238.08:08:41.92#ibcon#end of sib2, iclass 12, count 0 2006.238.08:08:41.92#ibcon#*mode == 0, iclass 12, count 0 2006.238.08:08:41.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.08:08:41.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:08:41.92#ibcon#*before write, iclass 12, count 0 2006.238.08:08:41.92#ibcon#enter sib2, iclass 12, count 0 2006.238.08:08:41.92#ibcon#flushed, iclass 12, count 0 2006.238.08:08:41.92#ibcon#about to write, iclass 12, count 0 2006.238.08:08:41.92#ibcon#wrote, iclass 12, count 0 2006.238.08:08:41.92#ibcon#about to read 3, iclass 12, count 0 2006.238.08:08:41.96#ibcon#read 3, iclass 12, count 0 2006.238.08:08:41.96#ibcon#about to read 4, iclass 12, count 0 2006.238.08:08:41.96#ibcon#read 4, iclass 12, count 0 2006.238.08:08:41.96#ibcon#about to read 5, iclass 12, count 0 2006.238.08:08:41.96#ibcon#read 5, iclass 12, count 0 2006.238.08:08:41.96#ibcon#about to read 6, iclass 12, count 0 2006.238.08:08:41.96#ibcon#read 6, iclass 12, count 0 2006.238.08:08:41.96#ibcon#end of sib2, iclass 12, count 0 2006.238.08:08:41.96#ibcon#*after write, iclass 12, count 0 2006.238.08:08:41.96#ibcon#*before return 0, iclass 12, count 0 2006.238.08:08:41.96#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:08:41.96#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:08:41.96#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.08:08:41.96#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.08:08:41.96$vc4f8/vb=5,4 2006.238.08:08:41.96#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.238.08:08:41.96#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.238.08:08:41.96#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:41.96#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:08:42.02#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:08:42.02#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:08:42.02#ibcon#enter wrdev, iclass 14, count 2 2006.238.08:08:42.02#ibcon#first serial, iclass 14, count 2 2006.238.08:08:42.02#ibcon#enter sib2, iclass 14, count 2 2006.238.08:08:42.02#ibcon#flushed, iclass 14, count 2 2006.238.08:08:42.02#ibcon#about to write, iclass 14, count 2 2006.238.08:08:42.02#ibcon#wrote, iclass 14, count 2 2006.238.08:08:42.02#ibcon#about to read 3, iclass 14, count 2 2006.238.08:08:42.04#ibcon#read 3, iclass 14, count 2 2006.238.08:08:42.04#ibcon#about to read 4, iclass 14, count 2 2006.238.08:08:42.04#ibcon#read 4, iclass 14, count 2 2006.238.08:08:42.04#ibcon#about to read 5, iclass 14, count 2 2006.238.08:08:42.04#ibcon#read 5, iclass 14, count 2 2006.238.08:08:42.04#ibcon#about to read 6, iclass 14, count 2 2006.238.08:08:42.04#ibcon#read 6, iclass 14, count 2 2006.238.08:08:42.04#ibcon#end of sib2, iclass 14, count 2 2006.238.08:08:42.04#ibcon#*mode == 0, iclass 14, count 2 2006.238.08:08:42.04#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.238.08:08:42.04#ibcon#[27=AT05-04\r\n] 2006.238.08:08:42.04#ibcon#*before write, iclass 14, count 2 2006.238.08:08:42.04#ibcon#enter sib2, iclass 14, count 2 2006.238.08:08:42.04#ibcon#flushed, iclass 14, count 2 2006.238.08:08:42.04#ibcon#about to write, iclass 14, count 2 2006.238.08:08:42.04#ibcon#wrote, iclass 14, count 2 2006.238.08:08:42.04#ibcon#about to read 3, iclass 14, count 2 2006.238.08:08:42.07#ibcon#read 3, iclass 14, count 2 2006.238.08:08:42.07#ibcon#about to read 4, iclass 14, count 2 2006.238.08:08:42.07#ibcon#read 4, iclass 14, count 2 2006.238.08:08:42.07#ibcon#about to read 5, iclass 14, count 2 2006.238.08:08:42.07#ibcon#read 5, iclass 14, count 2 2006.238.08:08:42.07#ibcon#about to read 6, iclass 14, count 2 2006.238.08:08:42.07#ibcon#read 6, iclass 14, count 2 2006.238.08:08:42.07#ibcon#end of sib2, iclass 14, count 2 2006.238.08:08:42.07#ibcon#*after write, iclass 14, count 2 2006.238.08:08:42.07#ibcon#*before return 0, iclass 14, count 2 2006.238.08:08:42.07#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:08:42.07#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:08:42.07#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.238.08:08:42.07#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:42.07#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:08:42.19#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:08:42.19#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:08:42.19#ibcon#enter wrdev, iclass 14, count 0 2006.238.08:08:42.19#ibcon#first serial, iclass 14, count 0 2006.238.08:08:42.19#ibcon#enter sib2, iclass 14, count 0 2006.238.08:08:42.19#ibcon#flushed, iclass 14, count 0 2006.238.08:08:42.19#ibcon#about to write, iclass 14, count 0 2006.238.08:08:42.19#ibcon#wrote, iclass 14, count 0 2006.238.08:08:42.19#ibcon#about to read 3, iclass 14, count 0 2006.238.08:08:42.21#ibcon#read 3, iclass 14, count 0 2006.238.08:08:42.21#ibcon#about to read 4, iclass 14, count 0 2006.238.08:08:42.21#ibcon#read 4, iclass 14, count 0 2006.238.08:08:42.21#ibcon#about to read 5, iclass 14, count 0 2006.238.08:08:42.21#ibcon#read 5, iclass 14, count 0 2006.238.08:08:42.21#ibcon#about to read 6, iclass 14, count 0 2006.238.08:08:42.21#ibcon#read 6, iclass 14, count 0 2006.238.08:08:42.21#ibcon#end of sib2, iclass 14, count 0 2006.238.08:08:42.21#ibcon#*mode == 0, iclass 14, count 0 2006.238.08:08:42.21#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.08:08:42.21#ibcon#[27=USB\r\n] 2006.238.08:08:42.21#ibcon#*before write, iclass 14, count 0 2006.238.08:08:42.21#ibcon#enter sib2, iclass 14, count 0 2006.238.08:08:42.21#ibcon#flushed, iclass 14, count 0 2006.238.08:08:42.21#ibcon#about to write, iclass 14, count 0 2006.238.08:08:42.21#ibcon#wrote, iclass 14, count 0 2006.238.08:08:42.21#ibcon#about to read 3, iclass 14, count 0 2006.238.08:08:42.24#ibcon#read 3, iclass 14, count 0 2006.238.08:08:42.24#ibcon#about to read 4, iclass 14, count 0 2006.238.08:08:42.24#ibcon#read 4, iclass 14, count 0 2006.238.08:08:42.24#ibcon#about to read 5, iclass 14, count 0 2006.238.08:08:42.24#ibcon#read 5, iclass 14, count 0 2006.238.08:08:42.24#ibcon#about to read 6, iclass 14, count 0 2006.238.08:08:42.24#ibcon#read 6, iclass 14, count 0 2006.238.08:08:42.24#ibcon#end of sib2, iclass 14, count 0 2006.238.08:08:42.24#ibcon#*after write, iclass 14, count 0 2006.238.08:08:42.24#ibcon#*before return 0, iclass 14, count 0 2006.238.08:08:42.24#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:08:42.24#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:08:42.24#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.08:08:42.24#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.08:08:42.24$vc4f8/vblo=6,752.99 2006.238.08:08:42.24#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.08:08:42.24#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.08:08:42.24#ibcon#ireg 17 cls_cnt 0 2006.238.08:08:42.24#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:08:42.24#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:08:42.24#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:08:42.24#ibcon#enter wrdev, iclass 16, count 0 2006.238.08:08:42.24#ibcon#first serial, iclass 16, count 0 2006.238.08:08:42.24#ibcon#enter sib2, iclass 16, count 0 2006.238.08:08:42.24#ibcon#flushed, iclass 16, count 0 2006.238.08:08:42.24#ibcon#about to write, iclass 16, count 0 2006.238.08:08:42.24#ibcon#wrote, iclass 16, count 0 2006.238.08:08:42.24#ibcon#about to read 3, iclass 16, count 0 2006.238.08:08:42.26#ibcon#read 3, iclass 16, count 0 2006.238.08:08:42.26#ibcon#about to read 4, iclass 16, count 0 2006.238.08:08:42.26#ibcon#read 4, iclass 16, count 0 2006.238.08:08:42.26#ibcon#about to read 5, iclass 16, count 0 2006.238.08:08:42.26#ibcon#read 5, iclass 16, count 0 2006.238.08:08:42.26#ibcon#about to read 6, iclass 16, count 0 2006.238.08:08:42.26#ibcon#read 6, iclass 16, count 0 2006.238.08:08:42.26#ibcon#end of sib2, iclass 16, count 0 2006.238.08:08:42.26#ibcon#*mode == 0, iclass 16, count 0 2006.238.08:08:42.26#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.08:08:42.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:08:42.26#ibcon#*before write, iclass 16, count 0 2006.238.08:08:42.26#ibcon#enter sib2, iclass 16, count 0 2006.238.08:08:42.26#ibcon#flushed, iclass 16, count 0 2006.238.08:08:42.26#ibcon#about to write, iclass 16, count 0 2006.238.08:08:42.26#ibcon#wrote, iclass 16, count 0 2006.238.08:08:42.26#ibcon#about to read 3, iclass 16, count 0 2006.238.08:08:42.30#ibcon#read 3, iclass 16, count 0 2006.238.08:08:42.30#ibcon#about to read 4, iclass 16, count 0 2006.238.08:08:42.30#ibcon#read 4, iclass 16, count 0 2006.238.08:08:42.30#ibcon#about to read 5, iclass 16, count 0 2006.238.08:08:42.30#ibcon#read 5, iclass 16, count 0 2006.238.08:08:42.30#ibcon#about to read 6, iclass 16, count 0 2006.238.08:08:42.30#ibcon#read 6, iclass 16, count 0 2006.238.08:08:42.30#ibcon#end of sib2, iclass 16, count 0 2006.238.08:08:42.30#ibcon#*after write, iclass 16, count 0 2006.238.08:08:42.30#ibcon#*before return 0, iclass 16, count 0 2006.238.08:08:42.30#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:08:42.30#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:08:42.30#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.08:08:42.30#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.08:08:42.30$vc4f8/vb=6,4 2006.238.08:08:42.30#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.238.08:08:42.30#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.238.08:08:42.30#ibcon#ireg 11 cls_cnt 2 2006.238.08:08:42.30#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:08:42.36#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:08:42.36#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:08:42.36#ibcon#enter wrdev, iclass 18, count 2 2006.238.08:08:42.36#ibcon#first serial, iclass 18, count 2 2006.238.08:08:42.36#ibcon#enter sib2, iclass 18, count 2 2006.238.08:08:42.36#ibcon#flushed, iclass 18, count 2 2006.238.08:08:42.36#ibcon#about to write, iclass 18, count 2 2006.238.08:08:42.36#ibcon#wrote, iclass 18, count 2 2006.238.08:08:42.36#ibcon#about to read 3, iclass 18, count 2 2006.238.08:08:42.38#ibcon#read 3, iclass 18, count 2 2006.238.08:08:42.38#ibcon#about to read 4, iclass 18, count 2 2006.238.08:08:42.38#ibcon#read 4, iclass 18, count 2 2006.238.08:08:42.38#ibcon#about to read 5, iclass 18, count 2 2006.238.08:08:42.38#ibcon#read 5, iclass 18, count 2 2006.238.08:08:42.38#ibcon#about to read 6, iclass 18, count 2 2006.238.08:08:42.38#ibcon#read 6, iclass 18, count 2 2006.238.08:08:42.38#ibcon#end of sib2, iclass 18, count 2 2006.238.08:08:42.38#ibcon#*mode == 0, iclass 18, count 2 2006.238.08:08:42.38#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.238.08:08:42.38#ibcon#[27=AT06-04\r\n] 2006.238.08:08:42.38#ibcon#*before write, iclass 18, count 2 2006.238.08:08:42.38#ibcon#enter sib2, iclass 18, count 2 2006.238.08:08:42.38#ibcon#flushed, iclass 18, count 2 2006.238.08:08:42.38#ibcon#about to write, iclass 18, count 2 2006.238.08:08:42.38#ibcon#wrote, iclass 18, count 2 2006.238.08:08:42.38#ibcon#about to read 3, iclass 18, count 2 2006.238.08:08:42.41#ibcon#read 3, iclass 18, count 2 2006.238.08:08:42.41#ibcon#about to read 4, iclass 18, count 2 2006.238.08:08:42.41#ibcon#read 4, iclass 18, count 2 2006.238.08:08:42.41#ibcon#about to read 5, iclass 18, count 2 2006.238.08:08:42.41#ibcon#read 5, iclass 18, count 2 2006.238.08:08:42.41#ibcon#about to read 6, iclass 18, count 2 2006.238.08:08:42.41#ibcon#read 6, iclass 18, count 2 2006.238.08:08:42.41#ibcon#end of sib2, iclass 18, count 2 2006.238.08:08:42.41#ibcon#*after write, iclass 18, count 2 2006.238.08:08:42.41#ibcon#*before return 0, iclass 18, count 2 2006.238.08:08:42.41#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:08:42.41#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:08:42.41#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.238.08:08:42.41#ibcon#ireg 7 cls_cnt 0 2006.238.08:08:42.41#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:08:42.54#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:08:42.54#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:08:42.54#ibcon#enter wrdev, iclass 18, count 0 2006.238.08:08:42.54#ibcon#first serial, iclass 18, count 0 2006.238.08:08:42.54#ibcon#enter sib2, iclass 18, count 0 2006.238.08:08:42.54#ibcon#flushed, iclass 18, count 0 2006.238.08:08:42.54#ibcon#about to write, iclass 18, count 0 2006.238.08:08:42.54#ibcon#wrote, iclass 18, count 0 2006.238.08:08:42.54#ibcon#about to read 3, iclass 18, count 0 2006.238.08:08:42.56#ibcon#read 3, iclass 18, count 0 2006.238.08:08:42.56#ibcon#about to read 4, iclass 18, count 0 2006.238.08:08:42.56#ibcon#read 4, iclass 18, count 0 2006.238.08:08:42.56#ibcon#about to read 5, iclass 18, count 0 2006.238.08:08:42.56#ibcon#read 5, iclass 18, count 0 2006.238.08:08:42.56#ibcon#about to read 6, iclass 18, count 0 2006.238.08:08:42.56#ibcon#read 6, iclass 18, count 0 2006.238.08:08:42.56#ibcon#end of sib2, iclass 18, count 0 2006.238.08:08:42.56#ibcon#*mode == 0, iclass 18, count 0 2006.238.08:08:42.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.08:08:42.56#ibcon#[27=USB\r\n] 2006.238.08:08:42.56#ibcon#*before write, iclass 18, count 0 2006.238.08:08:42.56#ibcon#enter sib2, iclass 18, count 0 2006.238.08:08:42.56#ibcon#flushed, iclass 18, count 0 2006.238.08:08:42.56#ibcon#about to write, iclass 18, count 0 2006.238.08:08:42.56#ibcon#wrote, iclass 18, count 0 2006.238.08:08:42.56#ibcon#about to read 3, iclass 18, count 0 2006.238.08:08:42.59#ibcon#read 3, iclass 18, count 0 2006.238.08:08:42.59#ibcon#about to read 4, iclass 18, count 0 2006.238.08:08:42.59#ibcon#read 4, iclass 18, count 0 2006.238.08:08:42.59#ibcon#about to read 5, iclass 18, count 0 2006.238.08:08:42.59#ibcon#read 5, iclass 18, count 0 2006.238.08:08:42.59#ibcon#about to read 6, iclass 18, count 0 2006.238.08:08:42.59#ibcon#read 6, iclass 18, count 0 2006.238.08:08:42.59#ibcon#end of sib2, iclass 18, count 0 2006.238.08:08:42.59#ibcon#*after write, iclass 18, count 0 2006.238.08:08:42.59#ibcon#*before return 0, iclass 18, count 0 2006.238.08:08:42.59#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:08:42.59#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:08:42.59#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.08:08:42.59#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.08:08:42.59$vc4f8/vabw=wide 2006.238.08:08:42.59#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.08:08:42.59#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.08:08:42.59#ibcon#ireg 8 cls_cnt 0 2006.238.08:08:42.59#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:08:42.59#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:08:42.59#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:08:42.59#ibcon#enter wrdev, iclass 20, count 0 2006.238.08:08:42.59#ibcon#first serial, iclass 20, count 0 2006.238.08:08:42.59#ibcon#enter sib2, iclass 20, count 0 2006.238.08:08:42.59#ibcon#flushed, iclass 20, count 0 2006.238.08:08:42.59#ibcon#about to write, iclass 20, count 0 2006.238.08:08:42.59#ibcon#wrote, iclass 20, count 0 2006.238.08:08:42.59#ibcon#about to read 3, iclass 20, count 0 2006.238.08:08:42.61#ibcon#read 3, iclass 20, count 0 2006.238.08:08:42.61#ibcon#about to read 4, iclass 20, count 0 2006.238.08:08:42.61#ibcon#read 4, iclass 20, count 0 2006.238.08:08:42.61#ibcon#about to read 5, iclass 20, count 0 2006.238.08:08:42.61#ibcon#read 5, iclass 20, count 0 2006.238.08:08:42.61#ibcon#about to read 6, iclass 20, count 0 2006.238.08:08:42.61#ibcon#read 6, iclass 20, count 0 2006.238.08:08:42.61#ibcon#end of sib2, iclass 20, count 0 2006.238.08:08:42.61#ibcon#*mode == 0, iclass 20, count 0 2006.238.08:08:42.61#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.08:08:42.61#ibcon#[25=BW32\r\n] 2006.238.08:08:42.61#ibcon#*before write, iclass 20, count 0 2006.238.08:08:42.61#ibcon#enter sib2, iclass 20, count 0 2006.238.08:08:42.61#ibcon#flushed, iclass 20, count 0 2006.238.08:08:42.61#ibcon#about to write, iclass 20, count 0 2006.238.08:08:42.61#ibcon#wrote, iclass 20, count 0 2006.238.08:08:42.61#ibcon#about to read 3, iclass 20, count 0 2006.238.08:08:42.64#ibcon#read 3, iclass 20, count 0 2006.238.08:08:42.64#ibcon#about to read 4, iclass 20, count 0 2006.238.08:08:42.64#ibcon#read 4, iclass 20, count 0 2006.238.08:08:42.64#ibcon#about to read 5, iclass 20, count 0 2006.238.08:08:42.64#ibcon#read 5, iclass 20, count 0 2006.238.08:08:42.64#ibcon#about to read 6, iclass 20, count 0 2006.238.08:08:42.64#ibcon#read 6, iclass 20, count 0 2006.238.08:08:42.64#ibcon#end of sib2, iclass 20, count 0 2006.238.08:08:42.64#ibcon#*after write, iclass 20, count 0 2006.238.08:08:42.64#ibcon#*before return 0, iclass 20, count 0 2006.238.08:08:42.64#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:08:42.64#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:08:42.64#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.08:08:42.64#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.08:08:42.64$vc4f8/vbbw=wide 2006.238.08:08:42.64#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.08:08:42.64#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.08:08:42.64#ibcon#ireg 8 cls_cnt 0 2006.238.08:08:42.64#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:08:42.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:08:42.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:08:42.71#ibcon#enter wrdev, iclass 22, count 0 2006.238.08:08:42.71#ibcon#first serial, iclass 22, count 0 2006.238.08:08:42.71#ibcon#enter sib2, iclass 22, count 0 2006.238.08:08:42.71#ibcon#flushed, iclass 22, count 0 2006.238.08:08:42.71#ibcon#about to write, iclass 22, count 0 2006.238.08:08:42.71#ibcon#wrote, iclass 22, count 0 2006.238.08:08:42.71#ibcon#about to read 3, iclass 22, count 0 2006.238.08:08:42.73#ibcon#read 3, iclass 22, count 0 2006.238.08:08:42.73#ibcon#about to read 4, iclass 22, count 0 2006.238.08:08:42.73#ibcon#read 4, iclass 22, count 0 2006.238.08:08:42.73#ibcon#about to read 5, iclass 22, count 0 2006.238.08:08:42.73#ibcon#read 5, iclass 22, count 0 2006.238.08:08:42.73#ibcon#about to read 6, iclass 22, count 0 2006.238.08:08:42.73#ibcon#read 6, iclass 22, count 0 2006.238.08:08:42.73#ibcon#end of sib2, iclass 22, count 0 2006.238.08:08:42.73#ibcon#*mode == 0, iclass 22, count 0 2006.238.08:08:42.73#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.08:08:42.73#ibcon#[27=BW32\r\n] 2006.238.08:08:42.73#ibcon#*before write, iclass 22, count 0 2006.238.08:08:42.73#ibcon#enter sib2, iclass 22, count 0 2006.238.08:08:42.73#ibcon#flushed, iclass 22, count 0 2006.238.08:08:42.73#ibcon#about to write, iclass 22, count 0 2006.238.08:08:42.73#ibcon#wrote, iclass 22, count 0 2006.238.08:08:42.73#ibcon#about to read 3, iclass 22, count 0 2006.238.08:08:42.76#ibcon#read 3, iclass 22, count 0 2006.238.08:08:42.76#ibcon#about to read 4, iclass 22, count 0 2006.238.08:08:42.76#ibcon#read 4, iclass 22, count 0 2006.238.08:08:42.76#ibcon#about to read 5, iclass 22, count 0 2006.238.08:08:42.76#ibcon#read 5, iclass 22, count 0 2006.238.08:08:42.76#ibcon#about to read 6, iclass 22, count 0 2006.238.08:08:42.76#ibcon#read 6, iclass 22, count 0 2006.238.08:08:42.76#ibcon#end of sib2, iclass 22, count 0 2006.238.08:08:42.76#ibcon#*after write, iclass 22, count 0 2006.238.08:08:42.76#ibcon#*before return 0, iclass 22, count 0 2006.238.08:08:42.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:08:42.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:08:42.76#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.08:08:42.76#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.08:08:42.76$4f8m12a/ifd4f 2006.238.08:08:42.76$ifd4f/lo= 2006.238.08:08:42.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:08:42.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:08:42.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:08:42.76$ifd4f/patch= 2006.238.08:08:42.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:08:42.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:08:42.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:08:42.76$4f8m12a/"form=m,16.000,1:2 2006.238.08:08:42.76$4f8m12a/"tpicd 2006.238.08:08:42.76$4f8m12a/echo=off 2006.238.08:08:42.76$4f8m12a/xlog=off 2006.238.08:08:42.76:!2006.238.08:09:10 2006.238.08:08:45.13#trakl#Source acquired 2006.238.08:08:46.13#flagr#flagr/antenna,acquired 2006.238.08:09:10.00:preob 2006.238.08:09:11.13/onsource/TRACKING 2006.238.08:09:11.13:!2006.238.08:09:20 2006.238.08:09:20.00:data_valid=on 2006.238.08:09:20.00:midob 2006.238.08:09:20.14/onsource/TRACKING 2006.238.08:09:20.14/wx/25.47,1012.2,89 2006.238.08:09:20.23/cable/+6.4182E-03 2006.238.08:09:21.31/va/01,08,usb,yes,32,33 2006.238.08:09:21.31/va/02,07,usb,yes,32,33 2006.238.08:09:21.31/va/03,07,usb,yes,30,30 2006.238.08:09:21.31/va/04,07,usb,yes,33,36 2006.238.08:09:21.31/va/05,08,usb,yes,30,31 2006.238.08:09:21.31/va/06,07,usb,yes,32,32 2006.238.08:09:21.31/va/07,07,usb,yes,33,32 2006.238.08:09:21.31/va/08,07,usb,yes,35,35 2006.238.08:09:21.54/valo/01,532.99,yes,locked 2006.238.08:09:21.54/valo/02,572.99,yes,locked 2006.238.08:09:21.54/valo/03,672.99,yes,locked 2006.238.08:09:21.54/valo/04,832.99,yes,locked 2006.238.08:09:21.54/valo/05,652.99,yes,locked 2006.238.08:09:21.54/valo/06,772.99,yes,locked 2006.238.08:09:21.54/valo/07,832.99,yes,locked 2006.238.08:09:21.54/valo/08,852.99,yes,locked 2006.238.08:09:22.63/vb/01,04,usb,yes,30,29 2006.238.08:09:22.63/vb/02,04,usb,yes,32,33 2006.238.08:09:22.63/vb/03,04,usb,yes,28,32 2006.238.08:09:22.63/vb/04,04,usb,yes,29,29 2006.238.08:09:22.63/vb/05,04,usb,yes,28,32 2006.238.08:09:22.63/vb/06,04,usb,yes,28,31 2006.238.08:09:22.63/vb/07,04,usb,yes,31,31 2006.238.08:09:22.63/vb/08,04,usb,yes,28,32 2006.238.08:09:22.86/vblo/01,632.99,yes,locked 2006.238.08:09:22.86/vblo/02,640.99,yes,locked 2006.238.08:09:22.86/vblo/03,656.99,yes,locked 2006.238.08:09:22.86/vblo/04,712.99,yes,locked 2006.238.08:09:22.86/vblo/05,744.99,yes,locked 2006.238.08:09:22.86/vblo/06,752.99,yes,locked 2006.238.08:09:22.86/vblo/07,734.99,yes,locked 2006.238.08:09:22.86/vblo/08,744.99,yes,locked 2006.238.08:09:23.01/vabw/8 2006.238.08:09:23.16/vbbw/8 2006.238.08:09:23.29/xfe/off,on,13.2 2006.238.08:09:23.67/ifatt/23,28,28,28 2006.238.08:09:24.07/fmout-gps/S +4.37E-07 2006.238.08:09:24.11:!2006.238.08:10:20 2006.238.08:10:20.00:data_valid=off 2006.238.08:10:20.00:postob 2006.238.08:10:20.22/cable/+6.4164E-03 2006.238.08:10:20.22/wx/25.47,1012.2,89 2006.238.08:10:21.07/fmout-gps/S +4.38E-07 2006.238.08:10:21.07:scan_name=238-0811,k06238,60 2006.238.08:10:21.07:source=0059+581,010245.76,582411.1,2000.0,cw 2006.238.08:10:21.14#flagr#flagr/antenna,new-source 2006.238.08:10:22.14:checkk5 2006.238.08:10:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:10:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:10:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:10:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:10:24.02/chk_obsdata//k5ts1/T2380809??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:10:24.39/chk_obsdata//k5ts2/T2380809??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:10:24.76/chk_obsdata//k5ts3/T2380809??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:10:25.13/chk_obsdata//k5ts4/T2380809??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:10:25.83/k5log//k5ts1_log_newline 2006.238.08:10:26.54/k5log//k5ts2_log_newline 2006.238.08:10:27.23/k5log//k5ts3_log_newline 2006.238.08:10:27.91/k5log//k5ts4_log_newline 2006.238.08:10:27.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:10:27.94:4f8m12a=2 2006.238.08:10:27.94$4f8m12a/echo=on 2006.238.08:10:27.94$4f8m12a/pcalon 2006.238.08:10:27.94$pcalon/"no phase cal control is implemented here 2006.238.08:10:27.94$4f8m12a/"tpicd=stop 2006.238.08:10:27.94$4f8m12a/vc4f8 2006.238.08:10:27.94$vc4f8/valo=1,532.99 2006.238.08:10:27.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.08:10:27.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.08:10:27.94#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:27.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:10:27.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:10:27.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:10:27.94#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:10:27.94#ibcon#first serial, iclass 33, count 0 2006.238.08:10:27.94#ibcon#enter sib2, iclass 33, count 0 2006.238.08:10:27.94#ibcon#flushed, iclass 33, count 0 2006.238.08:10:27.94#ibcon#about to write, iclass 33, count 0 2006.238.08:10:27.94#ibcon#wrote, iclass 33, count 0 2006.238.08:10:27.94#ibcon#about to read 3, iclass 33, count 0 2006.238.08:10:27.99#ibcon#read 3, iclass 33, count 0 2006.238.08:10:27.99#ibcon#about to read 4, iclass 33, count 0 2006.238.08:10:27.99#ibcon#read 4, iclass 33, count 0 2006.238.08:10:27.99#ibcon#about to read 5, iclass 33, count 0 2006.238.08:10:27.99#ibcon#read 5, iclass 33, count 0 2006.238.08:10:27.99#ibcon#about to read 6, iclass 33, count 0 2006.238.08:10:27.99#ibcon#read 6, iclass 33, count 0 2006.238.08:10:27.99#ibcon#end of sib2, iclass 33, count 0 2006.238.08:10:27.99#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:10:27.99#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:10:27.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:10:27.99#ibcon#*before write, iclass 33, count 0 2006.238.08:10:27.99#ibcon#enter sib2, iclass 33, count 0 2006.238.08:10:27.99#ibcon#flushed, iclass 33, count 0 2006.238.08:10:27.99#ibcon#about to write, iclass 33, count 0 2006.238.08:10:27.99#ibcon#wrote, iclass 33, count 0 2006.238.08:10:27.99#ibcon#about to read 3, iclass 33, count 0 2006.238.08:10:28.03#ibcon#read 3, iclass 33, count 0 2006.238.08:10:28.03#ibcon#about to read 4, iclass 33, count 0 2006.238.08:10:28.03#ibcon#read 4, iclass 33, count 0 2006.238.08:10:28.03#ibcon#about to read 5, iclass 33, count 0 2006.238.08:10:28.03#ibcon#read 5, iclass 33, count 0 2006.238.08:10:28.03#ibcon#about to read 6, iclass 33, count 0 2006.238.08:10:28.03#ibcon#read 6, iclass 33, count 0 2006.238.08:10:28.03#ibcon#end of sib2, iclass 33, count 0 2006.238.08:10:28.03#ibcon#*after write, iclass 33, count 0 2006.238.08:10:28.03#ibcon#*before return 0, iclass 33, count 0 2006.238.08:10:28.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:10:28.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:10:28.03#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:10:28.03#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:10:28.03$vc4f8/va=1,8 2006.238.08:10:28.03#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.238.08:10:28.03#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.238.08:10:28.03#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:28.03#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:10:28.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:10:28.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:10:28.03#ibcon#enter wrdev, iclass 35, count 2 2006.238.08:10:28.03#ibcon#first serial, iclass 35, count 2 2006.238.08:10:28.03#ibcon#enter sib2, iclass 35, count 2 2006.238.08:10:28.03#ibcon#flushed, iclass 35, count 2 2006.238.08:10:28.03#ibcon#about to write, iclass 35, count 2 2006.238.08:10:28.03#ibcon#wrote, iclass 35, count 2 2006.238.08:10:28.03#ibcon#about to read 3, iclass 35, count 2 2006.238.08:10:28.05#ibcon#read 3, iclass 35, count 2 2006.238.08:10:28.05#ibcon#about to read 4, iclass 35, count 2 2006.238.08:10:28.05#ibcon#read 4, iclass 35, count 2 2006.238.08:10:28.05#ibcon#about to read 5, iclass 35, count 2 2006.238.08:10:28.05#ibcon#read 5, iclass 35, count 2 2006.238.08:10:28.05#ibcon#about to read 6, iclass 35, count 2 2006.238.08:10:28.05#ibcon#read 6, iclass 35, count 2 2006.238.08:10:28.05#ibcon#end of sib2, iclass 35, count 2 2006.238.08:10:28.05#ibcon#*mode == 0, iclass 35, count 2 2006.238.08:10:28.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.238.08:10:28.05#ibcon#[25=AT01-08\r\n] 2006.238.08:10:28.05#ibcon#*before write, iclass 35, count 2 2006.238.08:10:28.05#ibcon#enter sib2, iclass 35, count 2 2006.238.08:10:28.05#ibcon#flushed, iclass 35, count 2 2006.238.08:10:28.05#ibcon#about to write, iclass 35, count 2 2006.238.08:10:28.05#ibcon#wrote, iclass 35, count 2 2006.238.08:10:28.05#ibcon#about to read 3, iclass 35, count 2 2006.238.08:10:28.08#ibcon#read 3, iclass 35, count 2 2006.238.08:10:28.08#ibcon#about to read 4, iclass 35, count 2 2006.238.08:10:28.08#ibcon#read 4, iclass 35, count 2 2006.238.08:10:28.08#ibcon#about to read 5, iclass 35, count 2 2006.238.08:10:28.08#ibcon#read 5, iclass 35, count 2 2006.238.08:10:28.08#ibcon#about to read 6, iclass 35, count 2 2006.238.08:10:28.08#ibcon#read 6, iclass 35, count 2 2006.238.08:10:28.08#ibcon#end of sib2, iclass 35, count 2 2006.238.08:10:28.08#ibcon#*after write, iclass 35, count 2 2006.238.08:10:28.08#ibcon#*before return 0, iclass 35, count 2 2006.238.08:10:28.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:10:28.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:10:28.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.238.08:10:28.08#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:28.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:10:28.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:10:28.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:10:28.20#ibcon#enter wrdev, iclass 35, count 0 2006.238.08:10:28.20#ibcon#first serial, iclass 35, count 0 2006.238.08:10:28.20#ibcon#enter sib2, iclass 35, count 0 2006.238.08:10:28.20#ibcon#flushed, iclass 35, count 0 2006.238.08:10:28.20#ibcon#about to write, iclass 35, count 0 2006.238.08:10:28.20#ibcon#wrote, iclass 35, count 0 2006.238.08:10:28.20#ibcon#about to read 3, iclass 35, count 0 2006.238.08:10:28.22#ibcon#read 3, iclass 35, count 0 2006.238.08:10:28.22#ibcon#about to read 4, iclass 35, count 0 2006.238.08:10:28.22#ibcon#read 4, iclass 35, count 0 2006.238.08:10:28.22#ibcon#about to read 5, iclass 35, count 0 2006.238.08:10:28.22#ibcon#read 5, iclass 35, count 0 2006.238.08:10:28.22#ibcon#about to read 6, iclass 35, count 0 2006.238.08:10:28.22#ibcon#read 6, iclass 35, count 0 2006.238.08:10:28.22#ibcon#end of sib2, iclass 35, count 0 2006.238.08:10:28.22#ibcon#*mode == 0, iclass 35, count 0 2006.238.08:10:28.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.08:10:28.22#ibcon#[25=USB\r\n] 2006.238.08:10:28.22#ibcon#*before write, iclass 35, count 0 2006.238.08:10:28.22#ibcon#enter sib2, iclass 35, count 0 2006.238.08:10:28.22#ibcon#flushed, iclass 35, count 0 2006.238.08:10:28.22#ibcon#about to write, iclass 35, count 0 2006.238.08:10:28.22#ibcon#wrote, iclass 35, count 0 2006.238.08:10:28.22#ibcon#about to read 3, iclass 35, count 0 2006.238.08:10:28.25#ibcon#read 3, iclass 35, count 0 2006.238.08:10:28.25#ibcon#about to read 4, iclass 35, count 0 2006.238.08:10:28.25#ibcon#read 4, iclass 35, count 0 2006.238.08:10:28.25#ibcon#about to read 5, iclass 35, count 0 2006.238.08:10:28.25#ibcon#read 5, iclass 35, count 0 2006.238.08:10:28.25#ibcon#about to read 6, iclass 35, count 0 2006.238.08:10:28.25#ibcon#read 6, iclass 35, count 0 2006.238.08:10:28.25#ibcon#end of sib2, iclass 35, count 0 2006.238.08:10:28.25#ibcon#*after write, iclass 35, count 0 2006.238.08:10:28.25#ibcon#*before return 0, iclass 35, count 0 2006.238.08:10:28.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:10:28.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:10:28.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.08:10:28.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.08:10:28.25$vc4f8/valo=2,572.99 2006.238.08:10:28.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.08:10:28.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.08:10:28.25#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:28.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:10:28.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:10:28.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:10:28.25#ibcon#enter wrdev, iclass 37, count 0 2006.238.08:10:28.25#ibcon#first serial, iclass 37, count 0 2006.238.08:10:28.25#ibcon#enter sib2, iclass 37, count 0 2006.238.08:10:28.25#ibcon#flushed, iclass 37, count 0 2006.238.08:10:28.25#ibcon#about to write, iclass 37, count 0 2006.238.08:10:28.25#ibcon#wrote, iclass 37, count 0 2006.238.08:10:28.25#ibcon#about to read 3, iclass 37, count 0 2006.238.08:10:28.27#ibcon#read 3, iclass 37, count 0 2006.238.08:10:28.27#ibcon#about to read 4, iclass 37, count 0 2006.238.08:10:28.27#ibcon#read 4, iclass 37, count 0 2006.238.08:10:28.27#ibcon#about to read 5, iclass 37, count 0 2006.238.08:10:28.27#ibcon#read 5, iclass 37, count 0 2006.238.08:10:28.27#ibcon#about to read 6, iclass 37, count 0 2006.238.08:10:28.27#ibcon#read 6, iclass 37, count 0 2006.238.08:10:28.27#ibcon#end of sib2, iclass 37, count 0 2006.238.08:10:28.27#ibcon#*mode == 0, iclass 37, count 0 2006.238.08:10:28.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.08:10:28.27#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:10:28.27#ibcon#*before write, iclass 37, count 0 2006.238.08:10:28.27#ibcon#enter sib2, iclass 37, count 0 2006.238.08:10:28.27#ibcon#flushed, iclass 37, count 0 2006.238.08:10:28.27#ibcon#about to write, iclass 37, count 0 2006.238.08:10:28.27#ibcon#wrote, iclass 37, count 0 2006.238.08:10:28.27#ibcon#about to read 3, iclass 37, count 0 2006.238.08:10:28.31#ibcon#read 3, iclass 37, count 0 2006.238.08:10:28.31#ibcon#about to read 4, iclass 37, count 0 2006.238.08:10:28.31#ibcon#read 4, iclass 37, count 0 2006.238.08:10:28.31#ibcon#about to read 5, iclass 37, count 0 2006.238.08:10:28.31#ibcon#read 5, iclass 37, count 0 2006.238.08:10:28.31#ibcon#about to read 6, iclass 37, count 0 2006.238.08:10:28.31#ibcon#read 6, iclass 37, count 0 2006.238.08:10:28.31#ibcon#end of sib2, iclass 37, count 0 2006.238.08:10:28.31#ibcon#*after write, iclass 37, count 0 2006.238.08:10:28.31#ibcon#*before return 0, iclass 37, count 0 2006.238.08:10:28.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:10:28.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:10:28.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.08:10:28.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.08:10:28.31$vc4f8/va=2,7 2006.238.08:10:28.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.238.08:10:28.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.238.08:10:28.31#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:28.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:10:28.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:10:28.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:10:28.37#ibcon#enter wrdev, iclass 39, count 2 2006.238.08:10:28.37#ibcon#first serial, iclass 39, count 2 2006.238.08:10:28.37#ibcon#enter sib2, iclass 39, count 2 2006.238.08:10:28.37#ibcon#flushed, iclass 39, count 2 2006.238.08:10:28.37#ibcon#about to write, iclass 39, count 2 2006.238.08:10:28.37#ibcon#wrote, iclass 39, count 2 2006.238.08:10:28.37#ibcon#about to read 3, iclass 39, count 2 2006.238.08:10:28.40#ibcon#read 3, iclass 39, count 2 2006.238.08:10:28.40#ibcon#about to read 4, iclass 39, count 2 2006.238.08:10:28.40#ibcon#read 4, iclass 39, count 2 2006.238.08:10:28.40#ibcon#about to read 5, iclass 39, count 2 2006.238.08:10:28.40#ibcon#read 5, iclass 39, count 2 2006.238.08:10:28.40#ibcon#about to read 6, iclass 39, count 2 2006.238.08:10:28.40#ibcon#read 6, iclass 39, count 2 2006.238.08:10:28.40#ibcon#end of sib2, iclass 39, count 2 2006.238.08:10:28.40#ibcon#*mode == 0, iclass 39, count 2 2006.238.08:10:28.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.238.08:10:28.40#ibcon#[25=AT02-07\r\n] 2006.238.08:10:28.40#ibcon#*before write, iclass 39, count 2 2006.238.08:10:28.40#ibcon#enter sib2, iclass 39, count 2 2006.238.08:10:28.40#ibcon#flushed, iclass 39, count 2 2006.238.08:10:28.40#ibcon#about to write, iclass 39, count 2 2006.238.08:10:28.40#ibcon#wrote, iclass 39, count 2 2006.238.08:10:28.40#ibcon#about to read 3, iclass 39, count 2 2006.238.08:10:28.43#ibcon#read 3, iclass 39, count 2 2006.238.08:10:28.43#ibcon#about to read 4, iclass 39, count 2 2006.238.08:10:28.43#ibcon#read 4, iclass 39, count 2 2006.238.08:10:28.43#ibcon#about to read 5, iclass 39, count 2 2006.238.08:10:28.43#ibcon#read 5, iclass 39, count 2 2006.238.08:10:28.43#ibcon#about to read 6, iclass 39, count 2 2006.238.08:10:28.43#ibcon#read 6, iclass 39, count 2 2006.238.08:10:28.43#ibcon#end of sib2, iclass 39, count 2 2006.238.08:10:28.43#ibcon#*after write, iclass 39, count 2 2006.238.08:10:28.43#ibcon#*before return 0, iclass 39, count 2 2006.238.08:10:28.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:10:28.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:10:28.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.238.08:10:28.43#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:28.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:10:28.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:10:28.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:10:28.55#ibcon#enter wrdev, iclass 39, count 0 2006.238.08:10:28.55#ibcon#first serial, iclass 39, count 0 2006.238.08:10:28.55#ibcon#enter sib2, iclass 39, count 0 2006.238.08:10:28.55#ibcon#flushed, iclass 39, count 0 2006.238.08:10:28.55#ibcon#about to write, iclass 39, count 0 2006.238.08:10:28.55#ibcon#wrote, iclass 39, count 0 2006.238.08:10:28.55#ibcon#about to read 3, iclass 39, count 0 2006.238.08:10:28.57#ibcon#read 3, iclass 39, count 0 2006.238.08:10:28.57#ibcon#about to read 4, iclass 39, count 0 2006.238.08:10:28.57#ibcon#read 4, iclass 39, count 0 2006.238.08:10:28.57#ibcon#about to read 5, iclass 39, count 0 2006.238.08:10:28.57#ibcon#read 5, iclass 39, count 0 2006.238.08:10:28.57#ibcon#about to read 6, iclass 39, count 0 2006.238.08:10:28.57#ibcon#read 6, iclass 39, count 0 2006.238.08:10:28.57#ibcon#end of sib2, iclass 39, count 0 2006.238.08:10:28.57#ibcon#*mode == 0, iclass 39, count 0 2006.238.08:10:28.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.08:10:28.57#ibcon#[25=USB\r\n] 2006.238.08:10:28.57#ibcon#*before write, iclass 39, count 0 2006.238.08:10:28.57#ibcon#enter sib2, iclass 39, count 0 2006.238.08:10:28.57#ibcon#flushed, iclass 39, count 0 2006.238.08:10:28.57#ibcon#about to write, iclass 39, count 0 2006.238.08:10:28.57#ibcon#wrote, iclass 39, count 0 2006.238.08:10:28.57#ibcon#about to read 3, iclass 39, count 0 2006.238.08:10:28.60#ibcon#read 3, iclass 39, count 0 2006.238.08:10:28.60#ibcon#about to read 4, iclass 39, count 0 2006.238.08:10:28.60#ibcon#read 4, iclass 39, count 0 2006.238.08:10:28.60#ibcon#about to read 5, iclass 39, count 0 2006.238.08:10:28.60#ibcon#read 5, iclass 39, count 0 2006.238.08:10:28.60#ibcon#about to read 6, iclass 39, count 0 2006.238.08:10:28.60#ibcon#read 6, iclass 39, count 0 2006.238.08:10:28.60#ibcon#end of sib2, iclass 39, count 0 2006.238.08:10:28.60#ibcon#*after write, iclass 39, count 0 2006.238.08:10:28.60#ibcon#*before return 0, iclass 39, count 0 2006.238.08:10:28.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:10:28.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:10:28.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.08:10:28.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.08:10:28.60$vc4f8/valo=3,672.99 2006.238.08:10:28.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.08:10:28.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.08:10:28.60#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:28.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:10:28.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:10:28.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:10:28.60#ibcon#enter wrdev, iclass 3, count 0 2006.238.08:10:28.60#ibcon#first serial, iclass 3, count 0 2006.238.08:10:28.60#ibcon#enter sib2, iclass 3, count 0 2006.238.08:10:28.60#ibcon#flushed, iclass 3, count 0 2006.238.08:10:28.60#ibcon#about to write, iclass 3, count 0 2006.238.08:10:28.60#ibcon#wrote, iclass 3, count 0 2006.238.08:10:28.60#ibcon#about to read 3, iclass 3, count 0 2006.238.08:10:28.62#ibcon#read 3, iclass 3, count 0 2006.238.08:10:28.62#ibcon#about to read 4, iclass 3, count 0 2006.238.08:10:28.62#ibcon#read 4, iclass 3, count 0 2006.238.08:10:28.62#ibcon#about to read 5, iclass 3, count 0 2006.238.08:10:28.62#ibcon#read 5, iclass 3, count 0 2006.238.08:10:28.62#ibcon#about to read 6, iclass 3, count 0 2006.238.08:10:28.62#ibcon#read 6, iclass 3, count 0 2006.238.08:10:28.62#ibcon#end of sib2, iclass 3, count 0 2006.238.08:10:28.62#ibcon#*mode == 0, iclass 3, count 0 2006.238.08:10:28.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.08:10:28.62#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:10:28.62#ibcon#*before write, iclass 3, count 0 2006.238.08:10:28.62#ibcon#enter sib2, iclass 3, count 0 2006.238.08:10:28.62#ibcon#flushed, iclass 3, count 0 2006.238.08:10:28.62#ibcon#about to write, iclass 3, count 0 2006.238.08:10:28.62#ibcon#wrote, iclass 3, count 0 2006.238.08:10:28.62#ibcon#about to read 3, iclass 3, count 0 2006.238.08:10:28.66#ibcon#read 3, iclass 3, count 0 2006.238.08:10:28.66#ibcon#about to read 4, iclass 3, count 0 2006.238.08:10:28.66#ibcon#read 4, iclass 3, count 0 2006.238.08:10:28.66#ibcon#about to read 5, iclass 3, count 0 2006.238.08:10:28.66#ibcon#read 5, iclass 3, count 0 2006.238.08:10:28.66#ibcon#about to read 6, iclass 3, count 0 2006.238.08:10:28.66#ibcon#read 6, iclass 3, count 0 2006.238.08:10:28.66#ibcon#end of sib2, iclass 3, count 0 2006.238.08:10:28.66#ibcon#*after write, iclass 3, count 0 2006.238.08:10:28.66#ibcon#*before return 0, iclass 3, count 0 2006.238.08:10:28.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:10:28.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:10:28.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.08:10:28.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.08:10:28.66$vc4f8/va=3,7 2006.238.08:10:28.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.238.08:10:28.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.238.08:10:28.66#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:28.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:10:28.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:10:28.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:10:28.72#ibcon#enter wrdev, iclass 5, count 2 2006.238.08:10:28.72#ibcon#first serial, iclass 5, count 2 2006.238.08:10:28.72#ibcon#enter sib2, iclass 5, count 2 2006.238.08:10:28.72#ibcon#flushed, iclass 5, count 2 2006.238.08:10:28.72#ibcon#about to write, iclass 5, count 2 2006.238.08:10:28.72#ibcon#wrote, iclass 5, count 2 2006.238.08:10:28.72#ibcon#about to read 3, iclass 5, count 2 2006.238.08:10:28.74#ibcon#read 3, iclass 5, count 2 2006.238.08:10:28.74#ibcon#about to read 4, iclass 5, count 2 2006.238.08:10:28.74#ibcon#read 4, iclass 5, count 2 2006.238.08:10:28.74#ibcon#about to read 5, iclass 5, count 2 2006.238.08:10:28.74#ibcon#read 5, iclass 5, count 2 2006.238.08:10:28.74#ibcon#about to read 6, iclass 5, count 2 2006.238.08:10:28.74#ibcon#read 6, iclass 5, count 2 2006.238.08:10:28.74#ibcon#end of sib2, iclass 5, count 2 2006.238.08:10:28.74#ibcon#*mode == 0, iclass 5, count 2 2006.238.08:10:28.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.238.08:10:28.74#ibcon#[25=AT03-07\r\n] 2006.238.08:10:28.74#ibcon#*before write, iclass 5, count 2 2006.238.08:10:28.74#ibcon#enter sib2, iclass 5, count 2 2006.238.08:10:28.74#ibcon#flushed, iclass 5, count 2 2006.238.08:10:28.74#ibcon#about to write, iclass 5, count 2 2006.238.08:10:28.74#ibcon#wrote, iclass 5, count 2 2006.238.08:10:28.74#ibcon#about to read 3, iclass 5, count 2 2006.238.08:10:28.77#ibcon#read 3, iclass 5, count 2 2006.238.08:10:28.77#ibcon#about to read 4, iclass 5, count 2 2006.238.08:10:28.77#ibcon#read 4, iclass 5, count 2 2006.238.08:10:28.77#ibcon#about to read 5, iclass 5, count 2 2006.238.08:10:28.77#ibcon#read 5, iclass 5, count 2 2006.238.08:10:28.77#ibcon#about to read 6, iclass 5, count 2 2006.238.08:10:28.77#ibcon#read 6, iclass 5, count 2 2006.238.08:10:28.77#ibcon#end of sib2, iclass 5, count 2 2006.238.08:10:28.77#ibcon#*after write, iclass 5, count 2 2006.238.08:10:28.77#ibcon#*before return 0, iclass 5, count 2 2006.238.08:10:28.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:10:28.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:10:28.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.238.08:10:28.77#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:28.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:10:28.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:10:28.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:10:28.89#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:10:28.89#ibcon#first serial, iclass 5, count 0 2006.238.08:10:28.89#ibcon#enter sib2, iclass 5, count 0 2006.238.08:10:28.89#ibcon#flushed, iclass 5, count 0 2006.238.08:10:28.89#ibcon#about to write, iclass 5, count 0 2006.238.08:10:28.89#ibcon#wrote, iclass 5, count 0 2006.238.08:10:28.89#ibcon#about to read 3, iclass 5, count 0 2006.238.08:10:28.91#ibcon#read 3, iclass 5, count 0 2006.238.08:10:28.91#ibcon#about to read 4, iclass 5, count 0 2006.238.08:10:28.91#ibcon#read 4, iclass 5, count 0 2006.238.08:10:28.91#ibcon#about to read 5, iclass 5, count 0 2006.238.08:10:28.91#ibcon#read 5, iclass 5, count 0 2006.238.08:10:28.91#ibcon#about to read 6, iclass 5, count 0 2006.238.08:10:28.91#ibcon#read 6, iclass 5, count 0 2006.238.08:10:28.91#ibcon#end of sib2, iclass 5, count 0 2006.238.08:10:28.91#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:10:28.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:10:28.91#ibcon#[25=USB\r\n] 2006.238.08:10:28.91#ibcon#*before write, iclass 5, count 0 2006.238.08:10:28.91#ibcon#enter sib2, iclass 5, count 0 2006.238.08:10:28.91#ibcon#flushed, iclass 5, count 0 2006.238.08:10:28.91#ibcon#about to write, iclass 5, count 0 2006.238.08:10:28.91#ibcon#wrote, iclass 5, count 0 2006.238.08:10:28.91#ibcon#about to read 3, iclass 5, count 0 2006.238.08:10:28.94#ibcon#read 3, iclass 5, count 0 2006.238.08:10:28.94#ibcon#about to read 4, iclass 5, count 0 2006.238.08:10:28.94#ibcon#read 4, iclass 5, count 0 2006.238.08:10:28.94#ibcon#about to read 5, iclass 5, count 0 2006.238.08:10:28.94#ibcon#read 5, iclass 5, count 0 2006.238.08:10:28.94#ibcon#about to read 6, iclass 5, count 0 2006.238.08:10:28.94#ibcon#read 6, iclass 5, count 0 2006.238.08:10:28.94#ibcon#end of sib2, iclass 5, count 0 2006.238.08:10:28.94#ibcon#*after write, iclass 5, count 0 2006.238.08:10:28.94#ibcon#*before return 0, iclass 5, count 0 2006.238.08:10:28.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:10:28.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:10:28.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:10:28.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:10:28.94$vc4f8/valo=4,832.99 2006.238.08:10:28.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.238.08:10:28.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.238.08:10:28.94#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:28.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:10:28.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:10:28.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:10:28.94#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:10:28.94#ibcon#first serial, iclass 7, count 0 2006.238.08:10:28.94#ibcon#enter sib2, iclass 7, count 0 2006.238.08:10:28.94#ibcon#flushed, iclass 7, count 0 2006.238.08:10:28.94#ibcon#about to write, iclass 7, count 0 2006.238.08:10:28.94#ibcon#wrote, iclass 7, count 0 2006.238.08:10:28.94#ibcon#about to read 3, iclass 7, count 0 2006.238.08:10:28.96#ibcon#read 3, iclass 7, count 0 2006.238.08:10:28.96#ibcon#about to read 4, iclass 7, count 0 2006.238.08:10:28.96#ibcon#read 4, iclass 7, count 0 2006.238.08:10:28.96#ibcon#about to read 5, iclass 7, count 0 2006.238.08:10:28.96#ibcon#read 5, iclass 7, count 0 2006.238.08:10:28.96#ibcon#about to read 6, iclass 7, count 0 2006.238.08:10:28.96#ibcon#read 6, iclass 7, count 0 2006.238.08:10:28.96#ibcon#end of sib2, iclass 7, count 0 2006.238.08:10:28.96#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:10:28.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:10:28.96#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:10:28.96#ibcon#*before write, iclass 7, count 0 2006.238.08:10:28.96#ibcon#enter sib2, iclass 7, count 0 2006.238.08:10:28.96#ibcon#flushed, iclass 7, count 0 2006.238.08:10:28.96#ibcon#about to write, iclass 7, count 0 2006.238.08:10:28.96#ibcon#wrote, iclass 7, count 0 2006.238.08:10:28.96#ibcon#about to read 3, iclass 7, count 0 2006.238.08:10:29.00#ibcon#read 3, iclass 7, count 0 2006.238.08:10:29.00#ibcon#about to read 4, iclass 7, count 0 2006.238.08:10:29.00#ibcon#read 4, iclass 7, count 0 2006.238.08:10:29.00#ibcon#about to read 5, iclass 7, count 0 2006.238.08:10:29.00#ibcon#read 5, iclass 7, count 0 2006.238.08:10:29.00#ibcon#about to read 6, iclass 7, count 0 2006.238.08:10:29.00#ibcon#read 6, iclass 7, count 0 2006.238.08:10:29.00#ibcon#end of sib2, iclass 7, count 0 2006.238.08:10:29.00#ibcon#*after write, iclass 7, count 0 2006.238.08:10:29.00#ibcon#*before return 0, iclass 7, count 0 2006.238.08:10:29.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:10:29.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:10:29.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:10:29.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:10:29.00$vc4f8/va=4,7 2006.238.08:10:29.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.238.08:10:29.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.238.08:10:29.00#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:29.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:10:29.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:10:29.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:10:29.06#ibcon#enter wrdev, iclass 11, count 2 2006.238.08:10:29.06#ibcon#first serial, iclass 11, count 2 2006.238.08:10:29.06#ibcon#enter sib2, iclass 11, count 2 2006.238.08:10:29.06#ibcon#flushed, iclass 11, count 2 2006.238.08:10:29.06#ibcon#about to write, iclass 11, count 2 2006.238.08:10:29.06#ibcon#wrote, iclass 11, count 2 2006.238.08:10:29.06#ibcon#about to read 3, iclass 11, count 2 2006.238.08:10:29.08#ibcon#read 3, iclass 11, count 2 2006.238.08:10:29.08#ibcon#about to read 4, iclass 11, count 2 2006.238.08:10:29.08#ibcon#read 4, iclass 11, count 2 2006.238.08:10:29.08#ibcon#about to read 5, iclass 11, count 2 2006.238.08:10:29.08#ibcon#read 5, iclass 11, count 2 2006.238.08:10:29.08#ibcon#about to read 6, iclass 11, count 2 2006.238.08:10:29.08#ibcon#read 6, iclass 11, count 2 2006.238.08:10:29.08#ibcon#end of sib2, iclass 11, count 2 2006.238.08:10:29.08#ibcon#*mode == 0, iclass 11, count 2 2006.238.08:10:29.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.238.08:10:29.08#ibcon#[25=AT04-07\r\n] 2006.238.08:10:29.08#ibcon#*before write, iclass 11, count 2 2006.238.08:10:29.08#ibcon#enter sib2, iclass 11, count 2 2006.238.08:10:29.08#ibcon#flushed, iclass 11, count 2 2006.238.08:10:29.08#ibcon#about to write, iclass 11, count 2 2006.238.08:10:29.08#ibcon#wrote, iclass 11, count 2 2006.238.08:10:29.08#ibcon#about to read 3, iclass 11, count 2 2006.238.08:10:29.11#ibcon#read 3, iclass 11, count 2 2006.238.08:10:29.11#ibcon#about to read 4, iclass 11, count 2 2006.238.08:10:29.11#ibcon#read 4, iclass 11, count 2 2006.238.08:10:29.11#ibcon#about to read 5, iclass 11, count 2 2006.238.08:10:29.11#ibcon#read 5, iclass 11, count 2 2006.238.08:10:29.11#ibcon#about to read 6, iclass 11, count 2 2006.238.08:10:29.11#ibcon#read 6, iclass 11, count 2 2006.238.08:10:29.11#ibcon#end of sib2, iclass 11, count 2 2006.238.08:10:29.11#ibcon#*after write, iclass 11, count 2 2006.238.08:10:29.11#ibcon#*before return 0, iclass 11, count 2 2006.238.08:10:29.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:10:29.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:10:29.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.238.08:10:29.11#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:29.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:10:29.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:10:29.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:10:29.23#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:10:29.23#ibcon#first serial, iclass 11, count 0 2006.238.08:10:29.23#ibcon#enter sib2, iclass 11, count 0 2006.238.08:10:29.23#ibcon#flushed, iclass 11, count 0 2006.238.08:10:29.23#ibcon#about to write, iclass 11, count 0 2006.238.08:10:29.23#ibcon#wrote, iclass 11, count 0 2006.238.08:10:29.23#ibcon#about to read 3, iclass 11, count 0 2006.238.08:10:29.25#ibcon#read 3, iclass 11, count 0 2006.238.08:10:29.25#ibcon#about to read 4, iclass 11, count 0 2006.238.08:10:29.25#ibcon#read 4, iclass 11, count 0 2006.238.08:10:29.25#ibcon#about to read 5, iclass 11, count 0 2006.238.08:10:29.25#ibcon#read 5, iclass 11, count 0 2006.238.08:10:29.25#ibcon#about to read 6, iclass 11, count 0 2006.238.08:10:29.25#ibcon#read 6, iclass 11, count 0 2006.238.08:10:29.25#ibcon#end of sib2, iclass 11, count 0 2006.238.08:10:29.25#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:10:29.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:10:29.25#ibcon#[25=USB\r\n] 2006.238.08:10:29.25#ibcon#*before write, iclass 11, count 0 2006.238.08:10:29.25#ibcon#enter sib2, iclass 11, count 0 2006.238.08:10:29.25#ibcon#flushed, iclass 11, count 0 2006.238.08:10:29.25#ibcon#about to write, iclass 11, count 0 2006.238.08:10:29.25#ibcon#wrote, iclass 11, count 0 2006.238.08:10:29.25#ibcon#about to read 3, iclass 11, count 0 2006.238.08:10:29.28#ibcon#read 3, iclass 11, count 0 2006.238.08:10:29.28#ibcon#about to read 4, iclass 11, count 0 2006.238.08:10:29.28#ibcon#read 4, iclass 11, count 0 2006.238.08:10:29.28#ibcon#about to read 5, iclass 11, count 0 2006.238.08:10:29.28#ibcon#read 5, iclass 11, count 0 2006.238.08:10:29.28#ibcon#about to read 6, iclass 11, count 0 2006.238.08:10:29.28#ibcon#read 6, iclass 11, count 0 2006.238.08:10:29.28#ibcon#end of sib2, iclass 11, count 0 2006.238.08:10:29.28#ibcon#*after write, iclass 11, count 0 2006.238.08:10:29.28#ibcon#*before return 0, iclass 11, count 0 2006.238.08:10:29.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:10:29.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:10:29.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:10:29.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:10:29.28$vc4f8/valo=5,652.99 2006.238.08:10:29.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.08:10:29.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.08:10:29.28#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:29.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:10:29.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:10:29.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:10:29.28#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:10:29.28#ibcon#first serial, iclass 13, count 0 2006.238.08:10:29.28#ibcon#enter sib2, iclass 13, count 0 2006.238.08:10:29.28#ibcon#flushed, iclass 13, count 0 2006.238.08:10:29.28#ibcon#about to write, iclass 13, count 0 2006.238.08:10:29.28#ibcon#wrote, iclass 13, count 0 2006.238.08:10:29.28#ibcon#about to read 3, iclass 13, count 0 2006.238.08:10:29.30#ibcon#read 3, iclass 13, count 0 2006.238.08:10:29.30#ibcon#about to read 4, iclass 13, count 0 2006.238.08:10:29.30#ibcon#read 4, iclass 13, count 0 2006.238.08:10:29.30#ibcon#about to read 5, iclass 13, count 0 2006.238.08:10:29.30#ibcon#read 5, iclass 13, count 0 2006.238.08:10:29.30#ibcon#about to read 6, iclass 13, count 0 2006.238.08:10:29.30#ibcon#read 6, iclass 13, count 0 2006.238.08:10:29.30#ibcon#end of sib2, iclass 13, count 0 2006.238.08:10:29.30#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:10:29.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:10:29.30#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:10:29.30#ibcon#*before write, iclass 13, count 0 2006.238.08:10:29.30#ibcon#enter sib2, iclass 13, count 0 2006.238.08:10:29.30#ibcon#flushed, iclass 13, count 0 2006.238.08:10:29.30#ibcon#about to write, iclass 13, count 0 2006.238.08:10:29.30#ibcon#wrote, iclass 13, count 0 2006.238.08:10:29.30#ibcon#about to read 3, iclass 13, count 0 2006.238.08:10:29.34#ibcon#read 3, iclass 13, count 0 2006.238.08:10:29.34#ibcon#about to read 4, iclass 13, count 0 2006.238.08:10:29.34#ibcon#read 4, iclass 13, count 0 2006.238.08:10:29.34#ibcon#about to read 5, iclass 13, count 0 2006.238.08:10:29.34#ibcon#read 5, iclass 13, count 0 2006.238.08:10:29.34#ibcon#about to read 6, iclass 13, count 0 2006.238.08:10:29.34#ibcon#read 6, iclass 13, count 0 2006.238.08:10:29.34#ibcon#end of sib2, iclass 13, count 0 2006.238.08:10:29.34#ibcon#*after write, iclass 13, count 0 2006.238.08:10:29.34#ibcon#*before return 0, iclass 13, count 0 2006.238.08:10:29.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:10:29.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:10:29.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:10:29.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:10:29.34$vc4f8/va=5,8 2006.238.08:10:29.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.238.08:10:29.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.238.08:10:29.34#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:29.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:10:29.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:10:29.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:10:29.40#ibcon#enter wrdev, iclass 15, count 2 2006.238.08:10:29.40#ibcon#first serial, iclass 15, count 2 2006.238.08:10:29.40#ibcon#enter sib2, iclass 15, count 2 2006.238.08:10:29.40#ibcon#flushed, iclass 15, count 2 2006.238.08:10:29.40#ibcon#about to write, iclass 15, count 2 2006.238.08:10:29.40#ibcon#wrote, iclass 15, count 2 2006.238.08:10:29.40#ibcon#about to read 3, iclass 15, count 2 2006.238.08:10:29.42#ibcon#read 3, iclass 15, count 2 2006.238.08:10:29.42#ibcon#about to read 4, iclass 15, count 2 2006.238.08:10:29.42#ibcon#read 4, iclass 15, count 2 2006.238.08:10:29.42#ibcon#about to read 5, iclass 15, count 2 2006.238.08:10:29.42#ibcon#read 5, iclass 15, count 2 2006.238.08:10:29.42#ibcon#about to read 6, iclass 15, count 2 2006.238.08:10:29.42#ibcon#read 6, iclass 15, count 2 2006.238.08:10:29.42#ibcon#end of sib2, iclass 15, count 2 2006.238.08:10:29.42#ibcon#*mode == 0, iclass 15, count 2 2006.238.08:10:29.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.238.08:10:29.42#ibcon#[25=AT05-08\r\n] 2006.238.08:10:29.42#ibcon#*before write, iclass 15, count 2 2006.238.08:10:29.42#ibcon#enter sib2, iclass 15, count 2 2006.238.08:10:29.42#ibcon#flushed, iclass 15, count 2 2006.238.08:10:29.42#ibcon#about to write, iclass 15, count 2 2006.238.08:10:29.42#ibcon#wrote, iclass 15, count 2 2006.238.08:10:29.42#ibcon#about to read 3, iclass 15, count 2 2006.238.08:10:29.45#ibcon#read 3, iclass 15, count 2 2006.238.08:10:29.45#ibcon#about to read 4, iclass 15, count 2 2006.238.08:10:29.45#ibcon#read 4, iclass 15, count 2 2006.238.08:10:29.45#ibcon#about to read 5, iclass 15, count 2 2006.238.08:10:29.45#ibcon#read 5, iclass 15, count 2 2006.238.08:10:29.45#ibcon#about to read 6, iclass 15, count 2 2006.238.08:10:29.45#ibcon#read 6, iclass 15, count 2 2006.238.08:10:29.45#ibcon#end of sib2, iclass 15, count 2 2006.238.08:10:29.45#ibcon#*after write, iclass 15, count 2 2006.238.08:10:29.45#ibcon#*before return 0, iclass 15, count 2 2006.238.08:10:29.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:10:29.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:10:29.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.238.08:10:29.45#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:29.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:10:29.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:10:29.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:10:29.57#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:10:29.57#ibcon#first serial, iclass 15, count 0 2006.238.08:10:29.57#ibcon#enter sib2, iclass 15, count 0 2006.238.08:10:29.57#ibcon#flushed, iclass 15, count 0 2006.238.08:10:29.57#ibcon#about to write, iclass 15, count 0 2006.238.08:10:29.57#ibcon#wrote, iclass 15, count 0 2006.238.08:10:29.57#ibcon#about to read 3, iclass 15, count 0 2006.238.08:10:29.59#ibcon#read 3, iclass 15, count 0 2006.238.08:10:29.59#ibcon#about to read 4, iclass 15, count 0 2006.238.08:10:29.59#ibcon#read 4, iclass 15, count 0 2006.238.08:10:29.59#ibcon#about to read 5, iclass 15, count 0 2006.238.08:10:29.59#ibcon#read 5, iclass 15, count 0 2006.238.08:10:29.59#ibcon#about to read 6, iclass 15, count 0 2006.238.08:10:29.59#ibcon#read 6, iclass 15, count 0 2006.238.08:10:29.59#ibcon#end of sib2, iclass 15, count 0 2006.238.08:10:29.59#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:10:29.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:10:29.59#ibcon#[25=USB\r\n] 2006.238.08:10:29.59#ibcon#*before write, iclass 15, count 0 2006.238.08:10:29.59#ibcon#enter sib2, iclass 15, count 0 2006.238.08:10:29.59#ibcon#flushed, iclass 15, count 0 2006.238.08:10:29.59#ibcon#about to write, iclass 15, count 0 2006.238.08:10:29.59#ibcon#wrote, iclass 15, count 0 2006.238.08:10:29.59#ibcon#about to read 3, iclass 15, count 0 2006.238.08:10:29.62#ibcon#read 3, iclass 15, count 0 2006.238.08:10:29.62#ibcon#about to read 4, iclass 15, count 0 2006.238.08:10:29.62#ibcon#read 4, iclass 15, count 0 2006.238.08:10:29.62#ibcon#about to read 5, iclass 15, count 0 2006.238.08:10:29.62#ibcon#read 5, iclass 15, count 0 2006.238.08:10:29.62#ibcon#about to read 6, iclass 15, count 0 2006.238.08:10:29.62#ibcon#read 6, iclass 15, count 0 2006.238.08:10:29.62#ibcon#end of sib2, iclass 15, count 0 2006.238.08:10:29.62#ibcon#*after write, iclass 15, count 0 2006.238.08:10:29.62#ibcon#*before return 0, iclass 15, count 0 2006.238.08:10:29.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:10:29.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:10:29.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:10:29.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:10:29.62$vc4f8/valo=6,772.99 2006.238.08:10:29.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.08:10:29.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.08:10:29.62#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:29.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:10:29.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:10:29.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:10:29.62#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:10:29.62#ibcon#first serial, iclass 17, count 0 2006.238.08:10:29.62#ibcon#enter sib2, iclass 17, count 0 2006.238.08:10:29.62#ibcon#flushed, iclass 17, count 0 2006.238.08:10:29.62#ibcon#about to write, iclass 17, count 0 2006.238.08:10:29.62#ibcon#wrote, iclass 17, count 0 2006.238.08:10:29.62#ibcon#about to read 3, iclass 17, count 0 2006.238.08:10:29.64#ibcon#read 3, iclass 17, count 0 2006.238.08:10:29.64#ibcon#about to read 4, iclass 17, count 0 2006.238.08:10:29.64#ibcon#read 4, iclass 17, count 0 2006.238.08:10:29.64#ibcon#about to read 5, iclass 17, count 0 2006.238.08:10:29.64#ibcon#read 5, iclass 17, count 0 2006.238.08:10:29.64#ibcon#about to read 6, iclass 17, count 0 2006.238.08:10:29.64#ibcon#read 6, iclass 17, count 0 2006.238.08:10:29.64#ibcon#end of sib2, iclass 17, count 0 2006.238.08:10:29.64#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:10:29.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:10:29.64#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:10:29.64#ibcon#*before write, iclass 17, count 0 2006.238.08:10:29.64#ibcon#enter sib2, iclass 17, count 0 2006.238.08:10:29.64#ibcon#flushed, iclass 17, count 0 2006.238.08:10:29.64#ibcon#about to write, iclass 17, count 0 2006.238.08:10:29.64#ibcon#wrote, iclass 17, count 0 2006.238.08:10:29.64#ibcon#about to read 3, iclass 17, count 0 2006.238.08:10:29.68#ibcon#read 3, iclass 17, count 0 2006.238.08:10:29.68#ibcon#about to read 4, iclass 17, count 0 2006.238.08:10:29.68#ibcon#read 4, iclass 17, count 0 2006.238.08:10:29.68#ibcon#about to read 5, iclass 17, count 0 2006.238.08:10:29.68#ibcon#read 5, iclass 17, count 0 2006.238.08:10:29.68#ibcon#about to read 6, iclass 17, count 0 2006.238.08:10:29.68#ibcon#read 6, iclass 17, count 0 2006.238.08:10:29.68#ibcon#end of sib2, iclass 17, count 0 2006.238.08:10:29.68#ibcon#*after write, iclass 17, count 0 2006.238.08:10:29.68#ibcon#*before return 0, iclass 17, count 0 2006.238.08:10:29.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:10:29.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:10:29.68#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:10:29.68#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:10:29.68$vc4f8/va=6,7 2006.238.08:10:29.68#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.238.08:10:29.68#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.238.08:10:29.68#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:29.68#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:10:29.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:10:29.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:10:29.74#ibcon#enter wrdev, iclass 19, count 2 2006.238.08:10:29.74#ibcon#first serial, iclass 19, count 2 2006.238.08:10:29.74#ibcon#enter sib2, iclass 19, count 2 2006.238.08:10:29.74#ibcon#flushed, iclass 19, count 2 2006.238.08:10:29.74#ibcon#about to write, iclass 19, count 2 2006.238.08:10:29.74#ibcon#wrote, iclass 19, count 2 2006.238.08:10:29.74#ibcon#about to read 3, iclass 19, count 2 2006.238.08:10:29.76#ibcon#read 3, iclass 19, count 2 2006.238.08:10:29.76#ibcon#about to read 4, iclass 19, count 2 2006.238.08:10:29.76#ibcon#read 4, iclass 19, count 2 2006.238.08:10:29.76#ibcon#about to read 5, iclass 19, count 2 2006.238.08:10:29.76#ibcon#read 5, iclass 19, count 2 2006.238.08:10:29.76#ibcon#about to read 6, iclass 19, count 2 2006.238.08:10:29.76#ibcon#read 6, iclass 19, count 2 2006.238.08:10:29.76#ibcon#end of sib2, iclass 19, count 2 2006.238.08:10:29.76#ibcon#*mode == 0, iclass 19, count 2 2006.238.08:10:29.76#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.238.08:10:29.76#ibcon#[25=AT06-07\r\n] 2006.238.08:10:29.76#ibcon#*before write, iclass 19, count 2 2006.238.08:10:29.76#ibcon#enter sib2, iclass 19, count 2 2006.238.08:10:29.76#ibcon#flushed, iclass 19, count 2 2006.238.08:10:29.76#ibcon#about to write, iclass 19, count 2 2006.238.08:10:29.76#ibcon#wrote, iclass 19, count 2 2006.238.08:10:29.76#ibcon#about to read 3, iclass 19, count 2 2006.238.08:10:29.79#ibcon#read 3, iclass 19, count 2 2006.238.08:10:29.79#ibcon#about to read 4, iclass 19, count 2 2006.238.08:10:29.79#ibcon#read 4, iclass 19, count 2 2006.238.08:10:29.79#ibcon#about to read 5, iclass 19, count 2 2006.238.08:10:29.79#ibcon#read 5, iclass 19, count 2 2006.238.08:10:29.79#ibcon#about to read 6, iclass 19, count 2 2006.238.08:10:29.79#ibcon#read 6, iclass 19, count 2 2006.238.08:10:29.79#ibcon#end of sib2, iclass 19, count 2 2006.238.08:10:29.79#ibcon#*after write, iclass 19, count 2 2006.238.08:10:29.79#ibcon#*before return 0, iclass 19, count 2 2006.238.08:10:29.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:10:29.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:10:29.79#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.238.08:10:29.79#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:29.79#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:10:29.91#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:10:29.91#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:10:29.91#ibcon#enter wrdev, iclass 19, count 0 2006.238.08:10:29.91#ibcon#first serial, iclass 19, count 0 2006.238.08:10:29.91#ibcon#enter sib2, iclass 19, count 0 2006.238.08:10:29.91#ibcon#flushed, iclass 19, count 0 2006.238.08:10:29.91#ibcon#about to write, iclass 19, count 0 2006.238.08:10:29.91#ibcon#wrote, iclass 19, count 0 2006.238.08:10:29.91#ibcon#about to read 3, iclass 19, count 0 2006.238.08:10:29.93#ibcon#read 3, iclass 19, count 0 2006.238.08:10:29.93#ibcon#about to read 4, iclass 19, count 0 2006.238.08:10:29.93#ibcon#read 4, iclass 19, count 0 2006.238.08:10:29.93#ibcon#about to read 5, iclass 19, count 0 2006.238.08:10:29.93#ibcon#read 5, iclass 19, count 0 2006.238.08:10:29.93#ibcon#about to read 6, iclass 19, count 0 2006.238.08:10:29.93#ibcon#read 6, iclass 19, count 0 2006.238.08:10:29.93#ibcon#end of sib2, iclass 19, count 0 2006.238.08:10:29.93#ibcon#*mode == 0, iclass 19, count 0 2006.238.08:10:29.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.08:10:29.93#ibcon#[25=USB\r\n] 2006.238.08:10:29.93#ibcon#*before write, iclass 19, count 0 2006.238.08:10:29.93#ibcon#enter sib2, iclass 19, count 0 2006.238.08:10:29.93#ibcon#flushed, iclass 19, count 0 2006.238.08:10:29.93#ibcon#about to write, iclass 19, count 0 2006.238.08:10:29.93#ibcon#wrote, iclass 19, count 0 2006.238.08:10:29.93#ibcon#about to read 3, iclass 19, count 0 2006.238.08:10:29.96#ibcon#read 3, iclass 19, count 0 2006.238.08:10:29.96#ibcon#about to read 4, iclass 19, count 0 2006.238.08:10:29.96#ibcon#read 4, iclass 19, count 0 2006.238.08:10:29.96#ibcon#about to read 5, iclass 19, count 0 2006.238.08:10:29.96#ibcon#read 5, iclass 19, count 0 2006.238.08:10:29.96#ibcon#about to read 6, iclass 19, count 0 2006.238.08:10:29.96#ibcon#read 6, iclass 19, count 0 2006.238.08:10:29.96#ibcon#end of sib2, iclass 19, count 0 2006.238.08:10:29.96#ibcon#*after write, iclass 19, count 0 2006.238.08:10:29.96#ibcon#*before return 0, iclass 19, count 0 2006.238.08:10:29.96#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:10:29.96#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:10:29.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.08:10:29.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.08:10:29.96$vc4f8/valo=7,832.99 2006.238.08:10:29.96#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.08:10:29.96#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.08:10:29.96#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:29.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:10:29.96#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:10:29.96#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:10:29.96#ibcon#enter wrdev, iclass 21, count 0 2006.238.08:10:29.96#ibcon#first serial, iclass 21, count 0 2006.238.08:10:29.96#ibcon#enter sib2, iclass 21, count 0 2006.238.08:10:29.96#ibcon#flushed, iclass 21, count 0 2006.238.08:10:29.96#ibcon#about to write, iclass 21, count 0 2006.238.08:10:29.96#ibcon#wrote, iclass 21, count 0 2006.238.08:10:29.96#ibcon#about to read 3, iclass 21, count 0 2006.238.08:10:29.98#ibcon#read 3, iclass 21, count 0 2006.238.08:10:29.98#ibcon#about to read 4, iclass 21, count 0 2006.238.08:10:29.98#ibcon#read 4, iclass 21, count 0 2006.238.08:10:29.98#ibcon#about to read 5, iclass 21, count 0 2006.238.08:10:29.98#ibcon#read 5, iclass 21, count 0 2006.238.08:10:29.98#ibcon#about to read 6, iclass 21, count 0 2006.238.08:10:29.98#ibcon#read 6, iclass 21, count 0 2006.238.08:10:29.98#ibcon#end of sib2, iclass 21, count 0 2006.238.08:10:29.98#ibcon#*mode == 0, iclass 21, count 0 2006.238.08:10:29.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.08:10:29.98#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:10:29.98#ibcon#*before write, iclass 21, count 0 2006.238.08:10:29.98#ibcon#enter sib2, iclass 21, count 0 2006.238.08:10:29.98#ibcon#flushed, iclass 21, count 0 2006.238.08:10:29.98#ibcon#about to write, iclass 21, count 0 2006.238.08:10:29.98#ibcon#wrote, iclass 21, count 0 2006.238.08:10:29.98#ibcon#about to read 3, iclass 21, count 0 2006.238.08:10:30.02#ibcon#read 3, iclass 21, count 0 2006.238.08:10:30.02#ibcon#about to read 4, iclass 21, count 0 2006.238.08:10:30.02#ibcon#read 4, iclass 21, count 0 2006.238.08:10:30.02#ibcon#about to read 5, iclass 21, count 0 2006.238.08:10:30.02#ibcon#read 5, iclass 21, count 0 2006.238.08:10:30.02#ibcon#about to read 6, iclass 21, count 0 2006.238.08:10:30.02#ibcon#read 6, iclass 21, count 0 2006.238.08:10:30.02#ibcon#end of sib2, iclass 21, count 0 2006.238.08:10:30.02#ibcon#*after write, iclass 21, count 0 2006.238.08:10:30.02#ibcon#*before return 0, iclass 21, count 0 2006.238.08:10:30.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:10:30.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:10:30.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.08:10:30.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.08:10:30.02$vc4f8/va=7,7 2006.238.08:10:30.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.238.08:10:30.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.238.08:10:30.02#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:30.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:10:30.08#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:10:30.08#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:10:30.08#ibcon#enter wrdev, iclass 23, count 2 2006.238.08:10:30.08#ibcon#first serial, iclass 23, count 2 2006.238.08:10:30.08#ibcon#enter sib2, iclass 23, count 2 2006.238.08:10:30.08#ibcon#flushed, iclass 23, count 2 2006.238.08:10:30.08#ibcon#about to write, iclass 23, count 2 2006.238.08:10:30.08#ibcon#wrote, iclass 23, count 2 2006.238.08:10:30.08#ibcon#about to read 3, iclass 23, count 2 2006.238.08:10:30.10#ibcon#read 3, iclass 23, count 2 2006.238.08:10:30.10#ibcon#about to read 4, iclass 23, count 2 2006.238.08:10:30.10#ibcon#read 4, iclass 23, count 2 2006.238.08:10:30.10#ibcon#about to read 5, iclass 23, count 2 2006.238.08:10:30.10#ibcon#read 5, iclass 23, count 2 2006.238.08:10:30.10#ibcon#about to read 6, iclass 23, count 2 2006.238.08:10:30.10#ibcon#read 6, iclass 23, count 2 2006.238.08:10:30.10#ibcon#end of sib2, iclass 23, count 2 2006.238.08:10:30.10#ibcon#*mode == 0, iclass 23, count 2 2006.238.08:10:30.10#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.238.08:10:30.10#ibcon#[25=AT07-07\r\n] 2006.238.08:10:30.10#ibcon#*before write, iclass 23, count 2 2006.238.08:10:30.10#ibcon#enter sib2, iclass 23, count 2 2006.238.08:10:30.10#ibcon#flushed, iclass 23, count 2 2006.238.08:10:30.10#ibcon#about to write, iclass 23, count 2 2006.238.08:10:30.10#ibcon#wrote, iclass 23, count 2 2006.238.08:10:30.10#ibcon#about to read 3, iclass 23, count 2 2006.238.08:10:30.13#ibcon#read 3, iclass 23, count 2 2006.238.08:10:30.13#ibcon#about to read 4, iclass 23, count 2 2006.238.08:10:30.13#ibcon#read 4, iclass 23, count 2 2006.238.08:10:30.13#ibcon#about to read 5, iclass 23, count 2 2006.238.08:10:30.13#ibcon#read 5, iclass 23, count 2 2006.238.08:10:30.13#ibcon#about to read 6, iclass 23, count 2 2006.238.08:10:30.13#ibcon#read 6, iclass 23, count 2 2006.238.08:10:30.13#ibcon#end of sib2, iclass 23, count 2 2006.238.08:10:30.13#ibcon#*after write, iclass 23, count 2 2006.238.08:10:30.13#ibcon#*before return 0, iclass 23, count 2 2006.238.08:10:30.13#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:10:30.13#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:10:30.13#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.238.08:10:30.13#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:30.13#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:10:30.25#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:10:30.25#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:10:30.25#ibcon#enter wrdev, iclass 23, count 0 2006.238.08:10:30.25#ibcon#first serial, iclass 23, count 0 2006.238.08:10:30.25#ibcon#enter sib2, iclass 23, count 0 2006.238.08:10:30.25#ibcon#flushed, iclass 23, count 0 2006.238.08:10:30.25#ibcon#about to write, iclass 23, count 0 2006.238.08:10:30.25#ibcon#wrote, iclass 23, count 0 2006.238.08:10:30.25#ibcon#about to read 3, iclass 23, count 0 2006.238.08:10:30.27#ibcon#read 3, iclass 23, count 0 2006.238.08:10:30.27#ibcon#about to read 4, iclass 23, count 0 2006.238.08:10:30.27#ibcon#read 4, iclass 23, count 0 2006.238.08:10:30.27#ibcon#about to read 5, iclass 23, count 0 2006.238.08:10:30.27#ibcon#read 5, iclass 23, count 0 2006.238.08:10:30.27#ibcon#about to read 6, iclass 23, count 0 2006.238.08:10:30.27#ibcon#read 6, iclass 23, count 0 2006.238.08:10:30.27#ibcon#end of sib2, iclass 23, count 0 2006.238.08:10:30.27#ibcon#*mode == 0, iclass 23, count 0 2006.238.08:10:30.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.08:10:30.27#ibcon#[25=USB\r\n] 2006.238.08:10:30.27#ibcon#*before write, iclass 23, count 0 2006.238.08:10:30.27#ibcon#enter sib2, iclass 23, count 0 2006.238.08:10:30.27#ibcon#flushed, iclass 23, count 0 2006.238.08:10:30.27#ibcon#about to write, iclass 23, count 0 2006.238.08:10:30.27#ibcon#wrote, iclass 23, count 0 2006.238.08:10:30.27#ibcon#about to read 3, iclass 23, count 0 2006.238.08:10:30.30#ibcon#read 3, iclass 23, count 0 2006.238.08:10:30.30#ibcon#about to read 4, iclass 23, count 0 2006.238.08:10:30.30#ibcon#read 4, iclass 23, count 0 2006.238.08:10:30.30#ibcon#about to read 5, iclass 23, count 0 2006.238.08:10:30.30#ibcon#read 5, iclass 23, count 0 2006.238.08:10:30.30#ibcon#about to read 6, iclass 23, count 0 2006.238.08:10:30.30#ibcon#read 6, iclass 23, count 0 2006.238.08:10:30.30#ibcon#end of sib2, iclass 23, count 0 2006.238.08:10:30.30#ibcon#*after write, iclass 23, count 0 2006.238.08:10:30.30#ibcon#*before return 0, iclass 23, count 0 2006.238.08:10:30.30#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:10:30.30#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:10:30.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.08:10:30.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.08:10:30.30$vc4f8/valo=8,852.99 2006.238.08:10:30.30#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.08:10:30.30#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.08:10:30.30#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:30.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:10:30.30#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:10:30.30#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:10:30.30#ibcon#enter wrdev, iclass 25, count 0 2006.238.08:10:30.30#ibcon#first serial, iclass 25, count 0 2006.238.08:10:30.30#ibcon#enter sib2, iclass 25, count 0 2006.238.08:10:30.30#ibcon#flushed, iclass 25, count 0 2006.238.08:10:30.30#ibcon#about to write, iclass 25, count 0 2006.238.08:10:30.30#ibcon#wrote, iclass 25, count 0 2006.238.08:10:30.30#ibcon#about to read 3, iclass 25, count 0 2006.238.08:10:30.32#ibcon#read 3, iclass 25, count 0 2006.238.08:10:30.32#ibcon#about to read 4, iclass 25, count 0 2006.238.08:10:30.32#ibcon#read 4, iclass 25, count 0 2006.238.08:10:30.32#ibcon#about to read 5, iclass 25, count 0 2006.238.08:10:30.32#ibcon#read 5, iclass 25, count 0 2006.238.08:10:30.32#ibcon#about to read 6, iclass 25, count 0 2006.238.08:10:30.32#ibcon#read 6, iclass 25, count 0 2006.238.08:10:30.32#ibcon#end of sib2, iclass 25, count 0 2006.238.08:10:30.32#ibcon#*mode == 0, iclass 25, count 0 2006.238.08:10:30.32#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.08:10:30.32#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:10:30.32#ibcon#*before write, iclass 25, count 0 2006.238.08:10:30.32#ibcon#enter sib2, iclass 25, count 0 2006.238.08:10:30.32#ibcon#flushed, iclass 25, count 0 2006.238.08:10:30.32#ibcon#about to write, iclass 25, count 0 2006.238.08:10:30.32#ibcon#wrote, iclass 25, count 0 2006.238.08:10:30.32#ibcon#about to read 3, iclass 25, count 0 2006.238.08:10:30.36#ibcon#read 3, iclass 25, count 0 2006.238.08:10:30.36#ibcon#about to read 4, iclass 25, count 0 2006.238.08:10:30.36#ibcon#read 4, iclass 25, count 0 2006.238.08:10:30.36#ibcon#about to read 5, iclass 25, count 0 2006.238.08:10:30.36#ibcon#read 5, iclass 25, count 0 2006.238.08:10:30.36#ibcon#about to read 6, iclass 25, count 0 2006.238.08:10:30.36#ibcon#read 6, iclass 25, count 0 2006.238.08:10:30.36#ibcon#end of sib2, iclass 25, count 0 2006.238.08:10:30.36#ibcon#*after write, iclass 25, count 0 2006.238.08:10:30.36#ibcon#*before return 0, iclass 25, count 0 2006.238.08:10:30.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:10:30.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:10:30.36#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.08:10:30.36#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.08:10:30.36$vc4f8/va=8,7 2006.238.08:10:30.36#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.238.08:10:30.36#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.238.08:10:30.36#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:30.36#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:10:30.42#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:10:30.42#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:10:30.42#ibcon#enter wrdev, iclass 27, count 2 2006.238.08:10:30.42#ibcon#first serial, iclass 27, count 2 2006.238.08:10:30.42#ibcon#enter sib2, iclass 27, count 2 2006.238.08:10:30.42#ibcon#flushed, iclass 27, count 2 2006.238.08:10:30.42#ibcon#about to write, iclass 27, count 2 2006.238.08:10:30.42#ibcon#wrote, iclass 27, count 2 2006.238.08:10:30.42#ibcon#about to read 3, iclass 27, count 2 2006.238.08:10:30.44#ibcon#read 3, iclass 27, count 2 2006.238.08:10:30.44#ibcon#about to read 4, iclass 27, count 2 2006.238.08:10:30.44#ibcon#read 4, iclass 27, count 2 2006.238.08:10:30.44#ibcon#about to read 5, iclass 27, count 2 2006.238.08:10:30.44#ibcon#read 5, iclass 27, count 2 2006.238.08:10:30.44#ibcon#about to read 6, iclass 27, count 2 2006.238.08:10:30.44#ibcon#read 6, iclass 27, count 2 2006.238.08:10:30.44#ibcon#end of sib2, iclass 27, count 2 2006.238.08:10:30.44#ibcon#*mode == 0, iclass 27, count 2 2006.238.08:10:30.44#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.238.08:10:30.44#ibcon#[25=AT08-07\r\n] 2006.238.08:10:30.44#ibcon#*before write, iclass 27, count 2 2006.238.08:10:30.44#ibcon#enter sib2, iclass 27, count 2 2006.238.08:10:30.44#ibcon#flushed, iclass 27, count 2 2006.238.08:10:30.44#ibcon#about to write, iclass 27, count 2 2006.238.08:10:30.44#ibcon#wrote, iclass 27, count 2 2006.238.08:10:30.44#ibcon#about to read 3, iclass 27, count 2 2006.238.08:10:30.47#ibcon#read 3, iclass 27, count 2 2006.238.08:10:30.47#ibcon#about to read 4, iclass 27, count 2 2006.238.08:10:30.47#ibcon#read 4, iclass 27, count 2 2006.238.08:10:30.47#ibcon#about to read 5, iclass 27, count 2 2006.238.08:10:30.47#ibcon#read 5, iclass 27, count 2 2006.238.08:10:30.47#ibcon#about to read 6, iclass 27, count 2 2006.238.08:10:30.47#ibcon#read 6, iclass 27, count 2 2006.238.08:10:30.47#ibcon#end of sib2, iclass 27, count 2 2006.238.08:10:30.47#ibcon#*after write, iclass 27, count 2 2006.238.08:10:30.47#ibcon#*before return 0, iclass 27, count 2 2006.238.08:10:30.47#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:10:30.47#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:10:30.47#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.238.08:10:30.47#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:30.47#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:10:30.59#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:10:30.59#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:10:30.59#ibcon#enter wrdev, iclass 27, count 0 2006.238.08:10:30.59#ibcon#first serial, iclass 27, count 0 2006.238.08:10:30.59#ibcon#enter sib2, iclass 27, count 0 2006.238.08:10:30.59#ibcon#flushed, iclass 27, count 0 2006.238.08:10:30.59#ibcon#about to write, iclass 27, count 0 2006.238.08:10:30.59#ibcon#wrote, iclass 27, count 0 2006.238.08:10:30.59#ibcon#about to read 3, iclass 27, count 0 2006.238.08:10:30.61#ibcon#read 3, iclass 27, count 0 2006.238.08:10:30.61#ibcon#about to read 4, iclass 27, count 0 2006.238.08:10:30.61#ibcon#read 4, iclass 27, count 0 2006.238.08:10:30.61#ibcon#about to read 5, iclass 27, count 0 2006.238.08:10:30.61#ibcon#read 5, iclass 27, count 0 2006.238.08:10:30.61#ibcon#about to read 6, iclass 27, count 0 2006.238.08:10:30.61#ibcon#read 6, iclass 27, count 0 2006.238.08:10:30.61#ibcon#end of sib2, iclass 27, count 0 2006.238.08:10:30.61#ibcon#*mode == 0, iclass 27, count 0 2006.238.08:10:30.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.08:10:30.61#ibcon#[25=USB\r\n] 2006.238.08:10:30.61#ibcon#*before write, iclass 27, count 0 2006.238.08:10:30.61#ibcon#enter sib2, iclass 27, count 0 2006.238.08:10:30.61#ibcon#flushed, iclass 27, count 0 2006.238.08:10:30.61#ibcon#about to write, iclass 27, count 0 2006.238.08:10:30.61#ibcon#wrote, iclass 27, count 0 2006.238.08:10:30.61#ibcon#about to read 3, iclass 27, count 0 2006.238.08:10:30.64#ibcon#read 3, iclass 27, count 0 2006.238.08:10:30.64#ibcon#about to read 4, iclass 27, count 0 2006.238.08:10:30.64#ibcon#read 4, iclass 27, count 0 2006.238.08:10:30.64#ibcon#about to read 5, iclass 27, count 0 2006.238.08:10:30.64#ibcon#read 5, iclass 27, count 0 2006.238.08:10:30.64#ibcon#about to read 6, iclass 27, count 0 2006.238.08:10:30.64#ibcon#read 6, iclass 27, count 0 2006.238.08:10:30.64#ibcon#end of sib2, iclass 27, count 0 2006.238.08:10:30.64#ibcon#*after write, iclass 27, count 0 2006.238.08:10:30.64#ibcon#*before return 0, iclass 27, count 0 2006.238.08:10:30.64#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:10:30.64#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:10:30.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.08:10:30.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.08:10:30.64$vc4f8/vblo=1,632.99 2006.238.08:10:30.64#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.238.08:10:30.64#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.238.08:10:30.64#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:30.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:10:30.64#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:10:30.64#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:10:30.64#ibcon#enter wrdev, iclass 29, count 0 2006.238.08:10:30.64#ibcon#first serial, iclass 29, count 0 2006.238.08:10:30.64#ibcon#enter sib2, iclass 29, count 0 2006.238.08:10:30.64#ibcon#flushed, iclass 29, count 0 2006.238.08:10:30.64#ibcon#about to write, iclass 29, count 0 2006.238.08:10:30.64#ibcon#wrote, iclass 29, count 0 2006.238.08:10:30.64#ibcon#about to read 3, iclass 29, count 0 2006.238.08:10:30.66#ibcon#read 3, iclass 29, count 0 2006.238.08:10:30.66#ibcon#about to read 4, iclass 29, count 0 2006.238.08:10:30.66#ibcon#read 4, iclass 29, count 0 2006.238.08:10:30.66#ibcon#about to read 5, iclass 29, count 0 2006.238.08:10:30.66#ibcon#read 5, iclass 29, count 0 2006.238.08:10:30.66#ibcon#about to read 6, iclass 29, count 0 2006.238.08:10:30.66#ibcon#read 6, iclass 29, count 0 2006.238.08:10:30.66#ibcon#end of sib2, iclass 29, count 0 2006.238.08:10:30.66#ibcon#*mode == 0, iclass 29, count 0 2006.238.08:10:30.66#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.08:10:30.66#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:10:30.66#ibcon#*before write, iclass 29, count 0 2006.238.08:10:30.66#ibcon#enter sib2, iclass 29, count 0 2006.238.08:10:30.66#ibcon#flushed, iclass 29, count 0 2006.238.08:10:30.66#ibcon#about to write, iclass 29, count 0 2006.238.08:10:30.66#ibcon#wrote, iclass 29, count 0 2006.238.08:10:30.66#ibcon#about to read 3, iclass 29, count 0 2006.238.08:10:30.70#ibcon#read 3, iclass 29, count 0 2006.238.08:10:30.70#ibcon#about to read 4, iclass 29, count 0 2006.238.08:10:30.70#ibcon#read 4, iclass 29, count 0 2006.238.08:10:30.70#ibcon#about to read 5, iclass 29, count 0 2006.238.08:10:30.70#ibcon#read 5, iclass 29, count 0 2006.238.08:10:30.70#ibcon#about to read 6, iclass 29, count 0 2006.238.08:10:30.70#ibcon#read 6, iclass 29, count 0 2006.238.08:10:30.70#ibcon#end of sib2, iclass 29, count 0 2006.238.08:10:30.70#ibcon#*after write, iclass 29, count 0 2006.238.08:10:30.70#ibcon#*before return 0, iclass 29, count 0 2006.238.08:10:30.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:10:30.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:10:30.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.08:10:30.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.08:10:30.70$vc4f8/vb=1,4 2006.238.08:10:30.70#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.238.08:10:30.70#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.238.08:10:30.70#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:30.70#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:10:30.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:10:30.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:10:30.70#ibcon#enter wrdev, iclass 31, count 2 2006.238.08:10:30.70#ibcon#first serial, iclass 31, count 2 2006.238.08:10:30.70#ibcon#enter sib2, iclass 31, count 2 2006.238.08:10:30.70#ibcon#flushed, iclass 31, count 2 2006.238.08:10:30.70#ibcon#about to write, iclass 31, count 2 2006.238.08:10:30.70#ibcon#wrote, iclass 31, count 2 2006.238.08:10:30.70#ibcon#about to read 3, iclass 31, count 2 2006.238.08:10:30.72#ibcon#read 3, iclass 31, count 2 2006.238.08:10:30.72#ibcon#about to read 4, iclass 31, count 2 2006.238.08:10:30.72#ibcon#read 4, iclass 31, count 2 2006.238.08:10:30.72#ibcon#about to read 5, iclass 31, count 2 2006.238.08:10:30.72#ibcon#read 5, iclass 31, count 2 2006.238.08:10:30.72#ibcon#about to read 6, iclass 31, count 2 2006.238.08:10:30.72#ibcon#read 6, iclass 31, count 2 2006.238.08:10:30.72#ibcon#end of sib2, iclass 31, count 2 2006.238.08:10:30.72#ibcon#*mode == 0, iclass 31, count 2 2006.238.08:10:30.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.238.08:10:30.72#ibcon#[27=AT01-04\r\n] 2006.238.08:10:30.72#ibcon#*before write, iclass 31, count 2 2006.238.08:10:30.72#ibcon#enter sib2, iclass 31, count 2 2006.238.08:10:30.72#ibcon#flushed, iclass 31, count 2 2006.238.08:10:30.72#ibcon#about to write, iclass 31, count 2 2006.238.08:10:30.72#ibcon#wrote, iclass 31, count 2 2006.238.08:10:30.72#ibcon#about to read 3, iclass 31, count 2 2006.238.08:10:30.75#ibcon#read 3, iclass 31, count 2 2006.238.08:10:30.75#ibcon#about to read 4, iclass 31, count 2 2006.238.08:10:30.75#ibcon#read 4, iclass 31, count 2 2006.238.08:10:30.75#ibcon#about to read 5, iclass 31, count 2 2006.238.08:10:30.75#ibcon#read 5, iclass 31, count 2 2006.238.08:10:30.75#ibcon#about to read 6, iclass 31, count 2 2006.238.08:10:30.75#ibcon#read 6, iclass 31, count 2 2006.238.08:10:30.75#ibcon#end of sib2, iclass 31, count 2 2006.238.08:10:30.75#ibcon#*after write, iclass 31, count 2 2006.238.08:10:30.75#ibcon#*before return 0, iclass 31, count 2 2006.238.08:10:30.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:10:30.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:10:30.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.238.08:10:30.75#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:30.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:10:30.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:10:30.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:10:30.87#ibcon#enter wrdev, iclass 31, count 0 2006.238.08:10:30.87#ibcon#first serial, iclass 31, count 0 2006.238.08:10:30.87#ibcon#enter sib2, iclass 31, count 0 2006.238.08:10:30.87#ibcon#flushed, iclass 31, count 0 2006.238.08:10:30.87#ibcon#about to write, iclass 31, count 0 2006.238.08:10:30.87#ibcon#wrote, iclass 31, count 0 2006.238.08:10:30.87#ibcon#about to read 3, iclass 31, count 0 2006.238.08:10:30.89#ibcon#read 3, iclass 31, count 0 2006.238.08:10:30.89#ibcon#about to read 4, iclass 31, count 0 2006.238.08:10:30.89#ibcon#read 4, iclass 31, count 0 2006.238.08:10:30.89#ibcon#about to read 5, iclass 31, count 0 2006.238.08:10:30.89#ibcon#read 5, iclass 31, count 0 2006.238.08:10:30.89#ibcon#about to read 6, iclass 31, count 0 2006.238.08:10:30.89#ibcon#read 6, iclass 31, count 0 2006.238.08:10:30.89#ibcon#end of sib2, iclass 31, count 0 2006.238.08:10:30.89#ibcon#*mode == 0, iclass 31, count 0 2006.238.08:10:30.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.08:10:30.89#ibcon#[27=USB\r\n] 2006.238.08:10:30.89#ibcon#*before write, iclass 31, count 0 2006.238.08:10:30.89#ibcon#enter sib2, iclass 31, count 0 2006.238.08:10:30.89#ibcon#flushed, iclass 31, count 0 2006.238.08:10:30.89#ibcon#about to write, iclass 31, count 0 2006.238.08:10:30.89#ibcon#wrote, iclass 31, count 0 2006.238.08:10:30.89#ibcon#about to read 3, iclass 31, count 0 2006.238.08:10:30.92#ibcon#read 3, iclass 31, count 0 2006.238.08:10:30.92#ibcon#about to read 4, iclass 31, count 0 2006.238.08:10:30.92#ibcon#read 4, iclass 31, count 0 2006.238.08:10:30.92#ibcon#about to read 5, iclass 31, count 0 2006.238.08:10:30.92#ibcon#read 5, iclass 31, count 0 2006.238.08:10:30.92#ibcon#about to read 6, iclass 31, count 0 2006.238.08:10:30.92#ibcon#read 6, iclass 31, count 0 2006.238.08:10:30.92#ibcon#end of sib2, iclass 31, count 0 2006.238.08:10:30.92#ibcon#*after write, iclass 31, count 0 2006.238.08:10:30.92#ibcon#*before return 0, iclass 31, count 0 2006.238.08:10:30.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:10:30.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:10:30.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.08:10:30.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.08:10:30.92$vc4f8/vblo=2,640.99 2006.238.08:10:30.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.08:10:30.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.08:10:30.92#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:30.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:10:30.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:10:30.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:10:30.92#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:10:30.92#ibcon#first serial, iclass 33, count 0 2006.238.08:10:30.92#ibcon#enter sib2, iclass 33, count 0 2006.238.08:10:30.92#ibcon#flushed, iclass 33, count 0 2006.238.08:10:30.92#ibcon#about to write, iclass 33, count 0 2006.238.08:10:30.92#ibcon#wrote, iclass 33, count 0 2006.238.08:10:30.92#ibcon#about to read 3, iclass 33, count 0 2006.238.08:10:30.94#ibcon#read 3, iclass 33, count 0 2006.238.08:10:30.94#ibcon#about to read 4, iclass 33, count 0 2006.238.08:10:30.94#ibcon#read 4, iclass 33, count 0 2006.238.08:10:30.94#ibcon#about to read 5, iclass 33, count 0 2006.238.08:10:30.94#ibcon#read 5, iclass 33, count 0 2006.238.08:10:30.94#ibcon#about to read 6, iclass 33, count 0 2006.238.08:10:30.94#ibcon#read 6, iclass 33, count 0 2006.238.08:10:30.94#ibcon#end of sib2, iclass 33, count 0 2006.238.08:10:30.94#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:10:30.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:10:30.94#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:10:30.94#ibcon#*before write, iclass 33, count 0 2006.238.08:10:30.94#ibcon#enter sib2, iclass 33, count 0 2006.238.08:10:30.94#ibcon#flushed, iclass 33, count 0 2006.238.08:10:30.94#ibcon#about to write, iclass 33, count 0 2006.238.08:10:30.94#ibcon#wrote, iclass 33, count 0 2006.238.08:10:30.94#ibcon#about to read 3, iclass 33, count 0 2006.238.08:10:30.98#ibcon#read 3, iclass 33, count 0 2006.238.08:10:30.98#ibcon#about to read 4, iclass 33, count 0 2006.238.08:10:30.98#ibcon#read 4, iclass 33, count 0 2006.238.08:10:30.98#ibcon#about to read 5, iclass 33, count 0 2006.238.08:10:30.98#ibcon#read 5, iclass 33, count 0 2006.238.08:10:30.98#ibcon#about to read 6, iclass 33, count 0 2006.238.08:10:30.98#ibcon#read 6, iclass 33, count 0 2006.238.08:10:30.98#ibcon#end of sib2, iclass 33, count 0 2006.238.08:10:30.98#ibcon#*after write, iclass 33, count 0 2006.238.08:10:30.98#ibcon#*before return 0, iclass 33, count 0 2006.238.08:10:30.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:10:30.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:10:30.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:10:30.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:10:30.98$vc4f8/vb=2,4 2006.238.08:10:30.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.238.08:10:30.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.238.08:10:30.98#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:30.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:10:31.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:10:31.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:10:31.04#ibcon#enter wrdev, iclass 35, count 2 2006.238.08:10:31.04#ibcon#first serial, iclass 35, count 2 2006.238.08:10:31.04#ibcon#enter sib2, iclass 35, count 2 2006.238.08:10:31.04#ibcon#flushed, iclass 35, count 2 2006.238.08:10:31.04#ibcon#about to write, iclass 35, count 2 2006.238.08:10:31.04#ibcon#wrote, iclass 35, count 2 2006.238.08:10:31.04#ibcon#about to read 3, iclass 35, count 2 2006.238.08:10:31.06#ibcon#read 3, iclass 35, count 2 2006.238.08:10:31.06#ibcon#about to read 4, iclass 35, count 2 2006.238.08:10:31.06#ibcon#read 4, iclass 35, count 2 2006.238.08:10:31.06#ibcon#about to read 5, iclass 35, count 2 2006.238.08:10:31.06#ibcon#read 5, iclass 35, count 2 2006.238.08:10:31.06#ibcon#about to read 6, iclass 35, count 2 2006.238.08:10:31.06#ibcon#read 6, iclass 35, count 2 2006.238.08:10:31.06#ibcon#end of sib2, iclass 35, count 2 2006.238.08:10:31.06#ibcon#*mode == 0, iclass 35, count 2 2006.238.08:10:31.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.238.08:10:31.06#ibcon#[27=AT02-04\r\n] 2006.238.08:10:31.06#ibcon#*before write, iclass 35, count 2 2006.238.08:10:31.06#ibcon#enter sib2, iclass 35, count 2 2006.238.08:10:31.06#ibcon#flushed, iclass 35, count 2 2006.238.08:10:31.06#ibcon#about to write, iclass 35, count 2 2006.238.08:10:31.06#ibcon#wrote, iclass 35, count 2 2006.238.08:10:31.06#ibcon#about to read 3, iclass 35, count 2 2006.238.08:10:31.09#ibcon#read 3, iclass 35, count 2 2006.238.08:10:31.09#ibcon#about to read 4, iclass 35, count 2 2006.238.08:10:31.09#ibcon#read 4, iclass 35, count 2 2006.238.08:10:31.09#ibcon#about to read 5, iclass 35, count 2 2006.238.08:10:31.09#ibcon#read 5, iclass 35, count 2 2006.238.08:10:31.09#ibcon#about to read 6, iclass 35, count 2 2006.238.08:10:31.09#ibcon#read 6, iclass 35, count 2 2006.238.08:10:31.09#ibcon#end of sib2, iclass 35, count 2 2006.238.08:10:31.09#ibcon#*after write, iclass 35, count 2 2006.238.08:10:31.09#ibcon#*before return 0, iclass 35, count 2 2006.238.08:10:31.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:10:31.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:10:31.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.238.08:10:31.09#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:31.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:10:31.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:10:31.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:10:31.21#ibcon#enter wrdev, iclass 35, count 0 2006.238.08:10:31.21#ibcon#first serial, iclass 35, count 0 2006.238.08:10:31.21#ibcon#enter sib2, iclass 35, count 0 2006.238.08:10:31.21#ibcon#flushed, iclass 35, count 0 2006.238.08:10:31.21#ibcon#about to write, iclass 35, count 0 2006.238.08:10:31.21#ibcon#wrote, iclass 35, count 0 2006.238.08:10:31.21#ibcon#about to read 3, iclass 35, count 0 2006.238.08:10:31.23#ibcon#read 3, iclass 35, count 0 2006.238.08:10:31.23#ibcon#about to read 4, iclass 35, count 0 2006.238.08:10:31.23#ibcon#read 4, iclass 35, count 0 2006.238.08:10:31.23#ibcon#about to read 5, iclass 35, count 0 2006.238.08:10:31.23#ibcon#read 5, iclass 35, count 0 2006.238.08:10:31.23#ibcon#about to read 6, iclass 35, count 0 2006.238.08:10:31.23#ibcon#read 6, iclass 35, count 0 2006.238.08:10:31.23#ibcon#end of sib2, iclass 35, count 0 2006.238.08:10:31.23#ibcon#*mode == 0, iclass 35, count 0 2006.238.08:10:31.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.08:10:31.23#ibcon#[27=USB\r\n] 2006.238.08:10:31.23#ibcon#*before write, iclass 35, count 0 2006.238.08:10:31.23#ibcon#enter sib2, iclass 35, count 0 2006.238.08:10:31.23#ibcon#flushed, iclass 35, count 0 2006.238.08:10:31.23#ibcon#about to write, iclass 35, count 0 2006.238.08:10:31.23#ibcon#wrote, iclass 35, count 0 2006.238.08:10:31.23#ibcon#about to read 3, iclass 35, count 0 2006.238.08:10:31.26#ibcon#read 3, iclass 35, count 0 2006.238.08:10:31.26#ibcon#about to read 4, iclass 35, count 0 2006.238.08:10:31.26#ibcon#read 4, iclass 35, count 0 2006.238.08:10:31.26#ibcon#about to read 5, iclass 35, count 0 2006.238.08:10:31.26#ibcon#read 5, iclass 35, count 0 2006.238.08:10:31.26#ibcon#about to read 6, iclass 35, count 0 2006.238.08:10:31.26#ibcon#read 6, iclass 35, count 0 2006.238.08:10:31.26#ibcon#end of sib2, iclass 35, count 0 2006.238.08:10:31.26#ibcon#*after write, iclass 35, count 0 2006.238.08:10:31.26#ibcon#*before return 0, iclass 35, count 0 2006.238.08:10:31.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:10:31.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:10:31.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.08:10:31.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.08:10:31.26$vc4f8/vblo=3,656.99 2006.238.08:10:31.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.08:10:31.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.08:10:31.26#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:31.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:10:31.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:10:31.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:10:31.26#ibcon#enter wrdev, iclass 37, count 0 2006.238.08:10:31.26#ibcon#first serial, iclass 37, count 0 2006.238.08:10:31.26#ibcon#enter sib2, iclass 37, count 0 2006.238.08:10:31.26#ibcon#flushed, iclass 37, count 0 2006.238.08:10:31.26#ibcon#about to write, iclass 37, count 0 2006.238.08:10:31.26#ibcon#wrote, iclass 37, count 0 2006.238.08:10:31.26#ibcon#about to read 3, iclass 37, count 0 2006.238.08:10:31.28#ibcon#read 3, iclass 37, count 0 2006.238.08:10:31.28#ibcon#about to read 4, iclass 37, count 0 2006.238.08:10:31.28#ibcon#read 4, iclass 37, count 0 2006.238.08:10:31.28#ibcon#about to read 5, iclass 37, count 0 2006.238.08:10:31.28#ibcon#read 5, iclass 37, count 0 2006.238.08:10:31.28#ibcon#about to read 6, iclass 37, count 0 2006.238.08:10:31.28#ibcon#read 6, iclass 37, count 0 2006.238.08:10:31.28#ibcon#end of sib2, iclass 37, count 0 2006.238.08:10:31.28#ibcon#*mode == 0, iclass 37, count 0 2006.238.08:10:31.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.08:10:31.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:10:31.28#ibcon#*before write, iclass 37, count 0 2006.238.08:10:31.28#ibcon#enter sib2, iclass 37, count 0 2006.238.08:10:31.28#ibcon#flushed, iclass 37, count 0 2006.238.08:10:31.28#ibcon#about to write, iclass 37, count 0 2006.238.08:10:31.28#ibcon#wrote, iclass 37, count 0 2006.238.08:10:31.28#ibcon#about to read 3, iclass 37, count 0 2006.238.08:10:31.32#ibcon#read 3, iclass 37, count 0 2006.238.08:10:31.32#ibcon#about to read 4, iclass 37, count 0 2006.238.08:10:31.32#ibcon#read 4, iclass 37, count 0 2006.238.08:10:31.32#ibcon#about to read 5, iclass 37, count 0 2006.238.08:10:31.32#ibcon#read 5, iclass 37, count 0 2006.238.08:10:31.32#ibcon#about to read 6, iclass 37, count 0 2006.238.08:10:31.32#ibcon#read 6, iclass 37, count 0 2006.238.08:10:31.32#ibcon#end of sib2, iclass 37, count 0 2006.238.08:10:31.32#ibcon#*after write, iclass 37, count 0 2006.238.08:10:31.32#ibcon#*before return 0, iclass 37, count 0 2006.238.08:10:31.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:10:31.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:10:31.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.08:10:31.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.08:10:31.32$vc4f8/vb=3,4 2006.238.08:10:31.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.238.08:10:31.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.238.08:10:31.32#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:31.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:10:31.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:10:31.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:10:31.38#ibcon#enter wrdev, iclass 39, count 2 2006.238.08:10:31.38#ibcon#first serial, iclass 39, count 2 2006.238.08:10:31.38#ibcon#enter sib2, iclass 39, count 2 2006.238.08:10:31.38#ibcon#flushed, iclass 39, count 2 2006.238.08:10:31.38#ibcon#about to write, iclass 39, count 2 2006.238.08:10:31.38#ibcon#wrote, iclass 39, count 2 2006.238.08:10:31.38#ibcon#about to read 3, iclass 39, count 2 2006.238.08:10:31.40#ibcon#read 3, iclass 39, count 2 2006.238.08:10:31.40#ibcon#about to read 4, iclass 39, count 2 2006.238.08:10:31.40#ibcon#read 4, iclass 39, count 2 2006.238.08:10:31.40#ibcon#about to read 5, iclass 39, count 2 2006.238.08:10:31.40#ibcon#read 5, iclass 39, count 2 2006.238.08:10:31.40#ibcon#about to read 6, iclass 39, count 2 2006.238.08:10:31.40#ibcon#read 6, iclass 39, count 2 2006.238.08:10:31.40#ibcon#end of sib2, iclass 39, count 2 2006.238.08:10:31.40#ibcon#*mode == 0, iclass 39, count 2 2006.238.08:10:31.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.238.08:10:31.40#ibcon#[27=AT03-04\r\n] 2006.238.08:10:31.40#ibcon#*before write, iclass 39, count 2 2006.238.08:10:31.40#ibcon#enter sib2, iclass 39, count 2 2006.238.08:10:31.40#ibcon#flushed, iclass 39, count 2 2006.238.08:10:31.40#ibcon#about to write, iclass 39, count 2 2006.238.08:10:31.40#ibcon#wrote, iclass 39, count 2 2006.238.08:10:31.40#ibcon#about to read 3, iclass 39, count 2 2006.238.08:10:31.43#ibcon#read 3, iclass 39, count 2 2006.238.08:10:31.43#ibcon#about to read 4, iclass 39, count 2 2006.238.08:10:31.43#ibcon#read 4, iclass 39, count 2 2006.238.08:10:31.43#ibcon#about to read 5, iclass 39, count 2 2006.238.08:10:31.43#ibcon#read 5, iclass 39, count 2 2006.238.08:10:31.43#ibcon#about to read 6, iclass 39, count 2 2006.238.08:10:31.43#ibcon#read 6, iclass 39, count 2 2006.238.08:10:31.43#ibcon#end of sib2, iclass 39, count 2 2006.238.08:10:31.43#ibcon#*after write, iclass 39, count 2 2006.238.08:10:31.43#ibcon#*before return 0, iclass 39, count 2 2006.238.08:10:31.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:10:31.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:10:31.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.238.08:10:31.43#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:31.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:10:31.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:10:31.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:10:31.55#ibcon#enter wrdev, iclass 39, count 0 2006.238.08:10:31.55#ibcon#first serial, iclass 39, count 0 2006.238.08:10:31.55#ibcon#enter sib2, iclass 39, count 0 2006.238.08:10:31.55#ibcon#flushed, iclass 39, count 0 2006.238.08:10:31.55#ibcon#about to write, iclass 39, count 0 2006.238.08:10:31.55#ibcon#wrote, iclass 39, count 0 2006.238.08:10:31.55#ibcon#about to read 3, iclass 39, count 0 2006.238.08:10:31.57#ibcon#read 3, iclass 39, count 0 2006.238.08:10:31.57#ibcon#about to read 4, iclass 39, count 0 2006.238.08:10:31.57#ibcon#read 4, iclass 39, count 0 2006.238.08:10:31.57#ibcon#about to read 5, iclass 39, count 0 2006.238.08:10:31.57#ibcon#read 5, iclass 39, count 0 2006.238.08:10:31.57#ibcon#about to read 6, iclass 39, count 0 2006.238.08:10:31.57#ibcon#read 6, iclass 39, count 0 2006.238.08:10:31.57#ibcon#end of sib2, iclass 39, count 0 2006.238.08:10:31.57#ibcon#*mode == 0, iclass 39, count 0 2006.238.08:10:31.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.08:10:31.57#ibcon#[27=USB\r\n] 2006.238.08:10:31.57#ibcon#*before write, iclass 39, count 0 2006.238.08:10:31.57#ibcon#enter sib2, iclass 39, count 0 2006.238.08:10:31.57#ibcon#flushed, iclass 39, count 0 2006.238.08:10:31.57#ibcon#about to write, iclass 39, count 0 2006.238.08:10:31.57#ibcon#wrote, iclass 39, count 0 2006.238.08:10:31.57#ibcon#about to read 3, iclass 39, count 0 2006.238.08:10:31.60#ibcon#read 3, iclass 39, count 0 2006.238.08:10:31.60#ibcon#about to read 4, iclass 39, count 0 2006.238.08:10:31.60#ibcon#read 4, iclass 39, count 0 2006.238.08:10:31.60#ibcon#about to read 5, iclass 39, count 0 2006.238.08:10:31.60#ibcon#read 5, iclass 39, count 0 2006.238.08:10:31.60#ibcon#about to read 6, iclass 39, count 0 2006.238.08:10:31.60#ibcon#read 6, iclass 39, count 0 2006.238.08:10:31.60#ibcon#end of sib2, iclass 39, count 0 2006.238.08:10:31.60#ibcon#*after write, iclass 39, count 0 2006.238.08:10:31.60#ibcon#*before return 0, iclass 39, count 0 2006.238.08:10:31.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:10:31.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:10:31.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.08:10:31.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.08:10:31.60$vc4f8/vblo=4,712.99 2006.238.08:10:31.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.08:10:31.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.08:10:31.60#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:31.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:10:31.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:10:31.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:10:31.60#ibcon#enter wrdev, iclass 3, count 0 2006.238.08:10:31.60#ibcon#first serial, iclass 3, count 0 2006.238.08:10:31.60#ibcon#enter sib2, iclass 3, count 0 2006.238.08:10:31.60#ibcon#flushed, iclass 3, count 0 2006.238.08:10:31.60#ibcon#about to write, iclass 3, count 0 2006.238.08:10:31.60#ibcon#wrote, iclass 3, count 0 2006.238.08:10:31.60#ibcon#about to read 3, iclass 3, count 0 2006.238.08:10:31.62#ibcon#read 3, iclass 3, count 0 2006.238.08:10:31.62#ibcon#about to read 4, iclass 3, count 0 2006.238.08:10:31.62#ibcon#read 4, iclass 3, count 0 2006.238.08:10:31.62#ibcon#about to read 5, iclass 3, count 0 2006.238.08:10:31.62#ibcon#read 5, iclass 3, count 0 2006.238.08:10:31.62#ibcon#about to read 6, iclass 3, count 0 2006.238.08:10:31.62#ibcon#read 6, iclass 3, count 0 2006.238.08:10:31.62#ibcon#end of sib2, iclass 3, count 0 2006.238.08:10:31.62#ibcon#*mode == 0, iclass 3, count 0 2006.238.08:10:31.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.08:10:31.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:10:31.62#ibcon#*before write, iclass 3, count 0 2006.238.08:10:31.62#ibcon#enter sib2, iclass 3, count 0 2006.238.08:10:31.62#ibcon#flushed, iclass 3, count 0 2006.238.08:10:31.62#ibcon#about to write, iclass 3, count 0 2006.238.08:10:31.62#ibcon#wrote, iclass 3, count 0 2006.238.08:10:31.62#ibcon#about to read 3, iclass 3, count 0 2006.238.08:10:31.66#ibcon#read 3, iclass 3, count 0 2006.238.08:10:31.66#ibcon#about to read 4, iclass 3, count 0 2006.238.08:10:31.66#ibcon#read 4, iclass 3, count 0 2006.238.08:10:31.66#ibcon#about to read 5, iclass 3, count 0 2006.238.08:10:31.66#ibcon#read 5, iclass 3, count 0 2006.238.08:10:31.66#ibcon#about to read 6, iclass 3, count 0 2006.238.08:10:31.66#ibcon#read 6, iclass 3, count 0 2006.238.08:10:31.66#ibcon#end of sib2, iclass 3, count 0 2006.238.08:10:31.66#ibcon#*after write, iclass 3, count 0 2006.238.08:10:31.66#ibcon#*before return 0, iclass 3, count 0 2006.238.08:10:31.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:10:31.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:10:31.66#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.08:10:31.66#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.08:10:31.66$vc4f8/vb=4,4 2006.238.08:10:31.66#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.238.08:10:31.66#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.238.08:10:31.66#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:31.66#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:10:31.72#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:10:31.72#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:10:31.72#ibcon#enter wrdev, iclass 5, count 2 2006.238.08:10:31.72#ibcon#first serial, iclass 5, count 2 2006.238.08:10:31.72#ibcon#enter sib2, iclass 5, count 2 2006.238.08:10:31.72#ibcon#flushed, iclass 5, count 2 2006.238.08:10:31.72#ibcon#about to write, iclass 5, count 2 2006.238.08:10:31.72#ibcon#wrote, iclass 5, count 2 2006.238.08:10:31.72#ibcon#about to read 3, iclass 5, count 2 2006.238.08:10:31.74#ibcon#read 3, iclass 5, count 2 2006.238.08:10:31.74#ibcon#about to read 4, iclass 5, count 2 2006.238.08:10:31.74#ibcon#read 4, iclass 5, count 2 2006.238.08:10:31.74#ibcon#about to read 5, iclass 5, count 2 2006.238.08:10:31.74#ibcon#read 5, iclass 5, count 2 2006.238.08:10:31.74#ibcon#about to read 6, iclass 5, count 2 2006.238.08:10:31.74#ibcon#read 6, iclass 5, count 2 2006.238.08:10:31.74#ibcon#end of sib2, iclass 5, count 2 2006.238.08:10:31.74#ibcon#*mode == 0, iclass 5, count 2 2006.238.08:10:31.74#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.238.08:10:31.74#ibcon#[27=AT04-04\r\n] 2006.238.08:10:31.74#ibcon#*before write, iclass 5, count 2 2006.238.08:10:31.74#ibcon#enter sib2, iclass 5, count 2 2006.238.08:10:31.74#ibcon#flushed, iclass 5, count 2 2006.238.08:10:31.74#ibcon#about to write, iclass 5, count 2 2006.238.08:10:31.74#ibcon#wrote, iclass 5, count 2 2006.238.08:10:31.74#ibcon#about to read 3, iclass 5, count 2 2006.238.08:10:31.77#ibcon#read 3, iclass 5, count 2 2006.238.08:10:31.77#ibcon#about to read 4, iclass 5, count 2 2006.238.08:10:31.77#ibcon#read 4, iclass 5, count 2 2006.238.08:10:31.77#ibcon#about to read 5, iclass 5, count 2 2006.238.08:10:31.77#ibcon#read 5, iclass 5, count 2 2006.238.08:10:31.77#ibcon#about to read 6, iclass 5, count 2 2006.238.08:10:31.77#ibcon#read 6, iclass 5, count 2 2006.238.08:10:31.77#ibcon#end of sib2, iclass 5, count 2 2006.238.08:10:31.77#ibcon#*after write, iclass 5, count 2 2006.238.08:10:31.77#ibcon#*before return 0, iclass 5, count 2 2006.238.08:10:31.77#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:10:31.77#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:10:31.77#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.238.08:10:31.77#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:31.77#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:10:31.89#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:10:31.89#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:10:31.89#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:10:31.89#ibcon#first serial, iclass 5, count 0 2006.238.08:10:31.89#ibcon#enter sib2, iclass 5, count 0 2006.238.08:10:31.89#ibcon#flushed, iclass 5, count 0 2006.238.08:10:31.89#ibcon#about to write, iclass 5, count 0 2006.238.08:10:31.89#ibcon#wrote, iclass 5, count 0 2006.238.08:10:31.89#ibcon#about to read 3, iclass 5, count 0 2006.238.08:10:31.91#ibcon#read 3, iclass 5, count 0 2006.238.08:10:31.91#ibcon#about to read 4, iclass 5, count 0 2006.238.08:10:31.91#ibcon#read 4, iclass 5, count 0 2006.238.08:10:31.91#ibcon#about to read 5, iclass 5, count 0 2006.238.08:10:31.91#ibcon#read 5, iclass 5, count 0 2006.238.08:10:31.91#ibcon#about to read 6, iclass 5, count 0 2006.238.08:10:31.91#ibcon#read 6, iclass 5, count 0 2006.238.08:10:31.91#ibcon#end of sib2, iclass 5, count 0 2006.238.08:10:31.91#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:10:31.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:10:31.91#ibcon#[27=USB\r\n] 2006.238.08:10:31.91#ibcon#*before write, iclass 5, count 0 2006.238.08:10:31.91#ibcon#enter sib2, iclass 5, count 0 2006.238.08:10:31.91#ibcon#flushed, iclass 5, count 0 2006.238.08:10:31.91#ibcon#about to write, iclass 5, count 0 2006.238.08:10:31.91#ibcon#wrote, iclass 5, count 0 2006.238.08:10:31.91#ibcon#about to read 3, iclass 5, count 0 2006.238.08:10:31.94#ibcon#read 3, iclass 5, count 0 2006.238.08:10:31.94#ibcon#about to read 4, iclass 5, count 0 2006.238.08:10:31.94#ibcon#read 4, iclass 5, count 0 2006.238.08:10:31.94#ibcon#about to read 5, iclass 5, count 0 2006.238.08:10:31.94#ibcon#read 5, iclass 5, count 0 2006.238.08:10:31.94#ibcon#about to read 6, iclass 5, count 0 2006.238.08:10:31.94#ibcon#read 6, iclass 5, count 0 2006.238.08:10:31.94#ibcon#end of sib2, iclass 5, count 0 2006.238.08:10:31.94#ibcon#*after write, iclass 5, count 0 2006.238.08:10:31.94#ibcon#*before return 0, iclass 5, count 0 2006.238.08:10:31.94#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:10:31.94#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:10:31.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:10:31.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:10:31.94$vc4f8/vblo=5,744.99 2006.238.08:10:31.94#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.238.08:10:31.94#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.238.08:10:31.94#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:31.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:10:31.94#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:10:31.94#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:10:31.94#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:10:31.94#ibcon#first serial, iclass 7, count 0 2006.238.08:10:31.94#ibcon#enter sib2, iclass 7, count 0 2006.238.08:10:31.94#ibcon#flushed, iclass 7, count 0 2006.238.08:10:31.94#ibcon#about to write, iclass 7, count 0 2006.238.08:10:31.94#ibcon#wrote, iclass 7, count 0 2006.238.08:10:31.94#ibcon#about to read 3, iclass 7, count 0 2006.238.08:10:31.96#ibcon#read 3, iclass 7, count 0 2006.238.08:10:31.96#ibcon#about to read 4, iclass 7, count 0 2006.238.08:10:31.96#ibcon#read 4, iclass 7, count 0 2006.238.08:10:31.96#ibcon#about to read 5, iclass 7, count 0 2006.238.08:10:31.96#ibcon#read 5, iclass 7, count 0 2006.238.08:10:31.96#ibcon#about to read 6, iclass 7, count 0 2006.238.08:10:31.96#ibcon#read 6, iclass 7, count 0 2006.238.08:10:31.96#ibcon#end of sib2, iclass 7, count 0 2006.238.08:10:31.96#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:10:31.96#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:10:31.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:10:31.96#ibcon#*before write, iclass 7, count 0 2006.238.08:10:31.96#ibcon#enter sib2, iclass 7, count 0 2006.238.08:10:31.96#ibcon#flushed, iclass 7, count 0 2006.238.08:10:31.96#ibcon#about to write, iclass 7, count 0 2006.238.08:10:31.96#ibcon#wrote, iclass 7, count 0 2006.238.08:10:31.96#ibcon#about to read 3, iclass 7, count 0 2006.238.08:10:32.00#ibcon#read 3, iclass 7, count 0 2006.238.08:10:32.00#ibcon#about to read 4, iclass 7, count 0 2006.238.08:10:32.00#ibcon#read 4, iclass 7, count 0 2006.238.08:10:32.00#ibcon#about to read 5, iclass 7, count 0 2006.238.08:10:32.00#ibcon#read 5, iclass 7, count 0 2006.238.08:10:32.00#ibcon#about to read 6, iclass 7, count 0 2006.238.08:10:32.00#ibcon#read 6, iclass 7, count 0 2006.238.08:10:32.00#ibcon#end of sib2, iclass 7, count 0 2006.238.08:10:32.00#ibcon#*after write, iclass 7, count 0 2006.238.08:10:32.00#ibcon#*before return 0, iclass 7, count 0 2006.238.08:10:32.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:10:32.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:10:32.00#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:10:32.00#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:10:32.00$vc4f8/vb=5,4 2006.238.08:10:32.00#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.238.08:10:32.00#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.238.08:10:32.00#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:32.00#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:10:32.06#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:10:32.06#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:10:32.06#ibcon#enter wrdev, iclass 11, count 2 2006.238.08:10:32.06#ibcon#first serial, iclass 11, count 2 2006.238.08:10:32.06#ibcon#enter sib2, iclass 11, count 2 2006.238.08:10:32.06#ibcon#flushed, iclass 11, count 2 2006.238.08:10:32.06#ibcon#about to write, iclass 11, count 2 2006.238.08:10:32.06#ibcon#wrote, iclass 11, count 2 2006.238.08:10:32.06#ibcon#about to read 3, iclass 11, count 2 2006.238.08:10:32.08#ibcon#read 3, iclass 11, count 2 2006.238.08:10:32.08#ibcon#about to read 4, iclass 11, count 2 2006.238.08:10:32.08#ibcon#read 4, iclass 11, count 2 2006.238.08:10:32.08#ibcon#about to read 5, iclass 11, count 2 2006.238.08:10:32.08#ibcon#read 5, iclass 11, count 2 2006.238.08:10:32.08#ibcon#about to read 6, iclass 11, count 2 2006.238.08:10:32.08#ibcon#read 6, iclass 11, count 2 2006.238.08:10:32.08#ibcon#end of sib2, iclass 11, count 2 2006.238.08:10:32.08#ibcon#*mode == 0, iclass 11, count 2 2006.238.08:10:32.08#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.238.08:10:32.08#ibcon#[27=AT05-04\r\n] 2006.238.08:10:32.08#ibcon#*before write, iclass 11, count 2 2006.238.08:10:32.08#ibcon#enter sib2, iclass 11, count 2 2006.238.08:10:32.08#ibcon#flushed, iclass 11, count 2 2006.238.08:10:32.08#ibcon#about to write, iclass 11, count 2 2006.238.08:10:32.08#ibcon#wrote, iclass 11, count 2 2006.238.08:10:32.08#ibcon#about to read 3, iclass 11, count 2 2006.238.08:10:32.11#ibcon#read 3, iclass 11, count 2 2006.238.08:10:32.11#ibcon#about to read 4, iclass 11, count 2 2006.238.08:10:32.11#ibcon#read 4, iclass 11, count 2 2006.238.08:10:32.11#ibcon#about to read 5, iclass 11, count 2 2006.238.08:10:32.11#ibcon#read 5, iclass 11, count 2 2006.238.08:10:32.11#ibcon#about to read 6, iclass 11, count 2 2006.238.08:10:32.11#ibcon#read 6, iclass 11, count 2 2006.238.08:10:32.11#ibcon#end of sib2, iclass 11, count 2 2006.238.08:10:32.11#ibcon#*after write, iclass 11, count 2 2006.238.08:10:32.11#ibcon#*before return 0, iclass 11, count 2 2006.238.08:10:32.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:10:32.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:10:32.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.238.08:10:32.11#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:32.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:10:32.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:10:32.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:10:32.23#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:10:32.23#ibcon#first serial, iclass 11, count 0 2006.238.08:10:32.23#ibcon#enter sib2, iclass 11, count 0 2006.238.08:10:32.23#ibcon#flushed, iclass 11, count 0 2006.238.08:10:32.23#ibcon#about to write, iclass 11, count 0 2006.238.08:10:32.23#ibcon#wrote, iclass 11, count 0 2006.238.08:10:32.23#ibcon#about to read 3, iclass 11, count 0 2006.238.08:10:32.25#ibcon#read 3, iclass 11, count 0 2006.238.08:10:32.25#ibcon#about to read 4, iclass 11, count 0 2006.238.08:10:32.25#ibcon#read 4, iclass 11, count 0 2006.238.08:10:32.25#ibcon#about to read 5, iclass 11, count 0 2006.238.08:10:32.25#ibcon#read 5, iclass 11, count 0 2006.238.08:10:32.25#ibcon#about to read 6, iclass 11, count 0 2006.238.08:10:32.25#ibcon#read 6, iclass 11, count 0 2006.238.08:10:32.25#ibcon#end of sib2, iclass 11, count 0 2006.238.08:10:32.25#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:10:32.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:10:32.25#ibcon#[27=USB\r\n] 2006.238.08:10:32.25#ibcon#*before write, iclass 11, count 0 2006.238.08:10:32.25#ibcon#enter sib2, iclass 11, count 0 2006.238.08:10:32.25#ibcon#flushed, iclass 11, count 0 2006.238.08:10:32.25#ibcon#about to write, iclass 11, count 0 2006.238.08:10:32.25#ibcon#wrote, iclass 11, count 0 2006.238.08:10:32.25#ibcon#about to read 3, iclass 11, count 0 2006.238.08:10:32.28#ibcon#read 3, iclass 11, count 0 2006.238.08:10:32.28#ibcon#about to read 4, iclass 11, count 0 2006.238.08:10:32.28#ibcon#read 4, iclass 11, count 0 2006.238.08:10:32.28#ibcon#about to read 5, iclass 11, count 0 2006.238.08:10:32.28#ibcon#read 5, iclass 11, count 0 2006.238.08:10:32.28#ibcon#about to read 6, iclass 11, count 0 2006.238.08:10:32.28#ibcon#read 6, iclass 11, count 0 2006.238.08:10:32.28#ibcon#end of sib2, iclass 11, count 0 2006.238.08:10:32.28#ibcon#*after write, iclass 11, count 0 2006.238.08:10:32.28#ibcon#*before return 0, iclass 11, count 0 2006.238.08:10:32.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:10:32.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:10:32.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:10:32.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:10:32.28$vc4f8/vblo=6,752.99 2006.238.08:10:32.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.08:10:32.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.08:10:32.28#ibcon#ireg 17 cls_cnt 0 2006.238.08:10:32.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:10:32.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:10:32.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:10:32.28#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:10:32.28#ibcon#first serial, iclass 13, count 0 2006.238.08:10:32.28#ibcon#enter sib2, iclass 13, count 0 2006.238.08:10:32.28#ibcon#flushed, iclass 13, count 0 2006.238.08:10:32.28#ibcon#about to write, iclass 13, count 0 2006.238.08:10:32.28#ibcon#wrote, iclass 13, count 0 2006.238.08:10:32.28#ibcon#about to read 3, iclass 13, count 0 2006.238.08:10:32.30#ibcon#read 3, iclass 13, count 0 2006.238.08:10:32.30#ibcon#about to read 4, iclass 13, count 0 2006.238.08:10:32.30#ibcon#read 4, iclass 13, count 0 2006.238.08:10:32.30#ibcon#about to read 5, iclass 13, count 0 2006.238.08:10:32.30#ibcon#read 5, iclass 13, count 0 2006.238.08:10:32.30#ibcon#about to read 6, iclass 13, count 0 2006.238.08:10:32.30#ibcon#read 6, iclass 13, count 0 2006.238.08:10:32.30#ibcon#end of sib2, iclass 13, count 0 2006.238.08:10:32.30#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:10:32.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:10:32.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:10:32.30#ibcon#*before write, iclass 13, count 0 2006.238.08:10:32.30#ibcon#enter sib2, iclass 13, count 0 2006.238.08:10:32.30#ibcon#flushed, iclass 13, count 0 2006.238.08:10:32.30#ibcon#about to write, iclass 13, count 0 2006.238.08:10:32.30#ibcon#wrote, iclass 13, count 0 2006.238.08:10:32.30#ibcon#about to read 3, iclass 13, count 0 2006.238.08:10:32.34#ibcon#read 3, iclass 13, count 0 2006.238.08:10:32.34#ibcon#about to read 4, iclass 13, count 0 2006.238.08:10:32.34#ibcon#read 4, iclass 13, count 0 2006.238.08:10:32.34#ibcon#about to read 5, iclass 13, count 0 2006.238.08:10:32.34#ibcon#read 5, iclass 13, count 0 2006.238.08:10:32.34#ibcon#about to read 6, iclass 13, count 0 2006.238.08:10:32.34#ibcon#read 6, iclass 13, count 0 2006.238.08:10:32.34#ibcon#end of sib2, iclass 13, count 0 2006.238.08:10:32.34#ibcon#*after write, iclass 13, count 0 2006.238.08:10:32.34#ibcon#*before return 0, iclass 13, count 0 2006.238.08:10:32.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:10:32.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:10:32.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:10:32.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:10:32.34$vc4f8/vb=6,4 2006.238.08:10:32.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.238.08:10:32.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.238.08:10:32.34#ibcon#ireg 11 cls_cnt 2 2006.238.08:10:32.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:10:32.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:10:32.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:10:32.40#ibcon#enter wrdev, iclass 15, count 2 2006.238.08:10:32.40#ibcon#first serial, iclass 15, count 2 2006.238.08:10:32.40#ibcon#enter sib2, iclass 15, count 2 2006.238.08:10:32.40#ibcon#flushed, iclass 15, count 2 2006.238.08:10:32.40#ibcon#about to write, iclass 15, count 2 2006.238.08:10:32.40#ibcon#wrote, iclass 15, count 2 2006.238.08:10:32.40#ibcon#about to read 3, iclass 15, count 2 2006.238.08:10:32.42#ibcon#read 3, iclass 15, count 2 2006.238.08:10:32.42#ibcon#about to read 4, iclass 15, count 2 2006.238.08:10:32.42#ibcon#read 4, iclass 15, count 2 2006.238.08:10:32.42#ibcon#about to read 5, iclass 15, count 2 2006.238.08:10:32.42#ibcon#read 5, iclass 15, count 2 2006.238.08:10:32.42#ibcon#about to read 6, iclass 15, count 2 2006.238.08:10:32.42#ibcon#read 6, iclass 15, count 2 2006.238.08:10:32.42#ibcon#end of sib2, iclass 15, count 2 2006.238.08:10:32.42#ibcon#*mode == 0, iclass 15, count 2 2006.238.08:10:32.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.238.08:10:32.42#ibcon#[27=AT06-04\r\n] 2006.238.08:10:32.42#ibcon#*before write, iclass 15, count 2 2006.238.08:10:32.42#ibcon#enter sib2, iclass 15, count 2 2006.238.08:10:32.42#ibcon#flushed, iclass 15, count 2 2006.238.08:10:32.42#ibcon#about to write, iclass 15, count 2 2006.238.08:10:32.42#ibcon#wrote, iclass 15, count 2 2006.238.08:10:32.42#ibcon#about to read 3, iclass 15, count 2 2006.238.08:10:32.45#ibcon#read 3, iclass 15, count 2 2006.238.08:10:32.45#ibcon#about to read 4, iclass 15, count 2 2006.238.08:10:32.45#ibcon#read 4, iclass 15, count 2 2006.238.08:10:32.45#ibcon#about to read 5, iclass 15, count 2 2006.238.08:10:32.45#ibcon#read 5, iclass 15, count 2 2006.238.08:10:32.45#ibcon#about to read 6, iclass 15, count 2 2006.238.08:10:32.45#ibcon#read 6, iclass 15, count 2 2006.238.08:10:32.45#ibcon#end of sib2, iclass 15, count 2 2006.238.08:10:32.45#ibcon#*after write, iclass 15, count 2 2006.238.08:10:32.45#ibcon#*before return 0, iclass 15, count 2 2006.238.08:10:32.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:10:32.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:10:32.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.238.08:10:32.45#ibcon#ireg 7 cls_cnt 0 2006.238.08:10:32.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:10:32.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:10:32.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:10:32.57#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:10:32.57#ibcon#first serial, iclass 15, count 0 2006.238.08:10:32.57#ibcon#enter sib2, iclass 15, count 0 2006.238.08:10:32.57#ibcon#flushed, iclass 15, count 0 2006.238.08:10:32.57#ibcon#about to write, iclass 15, count 0 2006.238.08:10:32.57#ibcon#wrote, iclass 15, count 0 2006.238.08:10:32.57#ibcon#about to read 3, iclass 15, count 0 2006.238.08:10:32.59#ibcon#read 3, iclass 15, count 0 2006.238.08:10:32.59#ibcon#about to read 4, iclass 15, count 0 2006.238.08:10:32.59#ibcon#read 4, iclass 15, count 0 2006.238.08:10:32.59#ibcon#about to read 5, iclass 15, count 0 2006.238.08:10:32.59#ibcon#read 5, iclass 15, count 0 2006.238.08:10:32.59#ibcon#about to read 6, iclass 15, count 0 2006.238.08:10:32.59#ibcon#read 6, iclass 15, count 0 2006.238.08:10:32.59#ibcon#end of sib2, iclass 15, count 0 2006.238.08:10:32.59#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:10:32.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:10:32.59#ibcon#[27=USB\r\n] 2006.238.08:10:32.59#ibcon#*before write, iclass 15, count 0 2006.238.08:10:32.59#ibcon#enter sib2, iclass 15, count 0 2006.238.08:10:32.59#ibcon#flushed, iclass 15, count 0 2006.238.08:10:32.59#ibcon#about to write, iclass 15, count 0 2006.238.08:10:32.59#ibcon#wrote, iclass 15, count 0 2006.238.08:10:32.59#ibcon#about to read 3, iclass 15, count 0 2006.238.08:10:32.62#ibcon#read 3, iclass 15, count 0 2006.238.08:10:32.62#ibcon#about to read 4, iclass 15, count 0 2006.238.08:10:32.62#ibcon#read 4, iclass 15, count 0 2006.238.08:10:32.62#ibcon#about to read 5, iclass 15, count 0 2006.238.08:10:32.62#ibcon#read 5, iclass 15, count 0 2006.238.08:10:32.62#ibcon#about to read 6, iclass 15, count 0 2006.238.08:10:32.62#ibcon#read 6, iclass 15, count 0 2006.238.08:10:32.62#ibcon#end of sib2, iclass 15, count 0 2006.238.08:10:32.62#ibcon#*after write, iclass 15, count 0 2006.238.08:10:32.62#ibcon#*before return 0, iclass 15, count 0 2006.238.08:10:32.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:10:32.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:10:32.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:10:32.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:10:32.62$vc4f8/vabw=wide 2006.238.08:10:32.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.08:10:32.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.08:10:32.62#ibcon#ireg 8 cls_cnt 0 2006.238.08:10:32.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:10:32.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:10:32.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:10:32.62#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:10:32.62#ibcon#first serial, iclass 17, count 0 2006.238.08:10:32.62#ibcon#enter sib2, iclass 17, count 0 2006.238.08:10:32.62#ibcon#flushed, iclass 17, count 0 2006.238.08:10:32.62#ibcon#about to write, iclass 17, count 0 2006.238.08:10:32.62#ibcon#wrote, iclass 17, count 0 2006.238.08:10:32.62#ibcon#about to read 3, iclass 17, count 0 2006.238.08:10:32.64#ibcon#read 3, iclass 17, count 0 2006.238.08:10:32.64#ibcon#about to read 4, iclass 17, count 0 2006.238.08:10:32.64#ibcon#read 4, iclass 17, count 0 2006.238.08:10:32.64#ibcon#about to read 5, iclass 17, count 0 2006.238.08:10:32.64#ibcon#read 5, iclass 17, count 0 2006.238.08:10:32.64#ibcon#about to read 6, iclass 17, count 0 2006.238.08:10:32.64#ibcon#read 6, iclass 17, count 0 2006.238.08:10:32.64#ibcon#end of sib2, iclass 17, count 0 2006.238.08:10:32.64#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:10:32.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:10:32.64#ibcon#[25=BW32\r\n] 2006.238.08:10:32.64#ibcon#*before write, iclass 17, count 0 2006.238.08:10:32.64#ibcon#enter sib2, iclass 17, count 0 2006.238.08:10:32.64#ibcon#flushed, iclass 17, count 0 2006.238.08:10:32.64#ibcon#about to write, iclass 17, count 0 2006.238.08:10:32.64#ibcon#wrote, iclass 17, count 0 2006.238.08:10:32.64#ibcon#about to read 3, iclass 17, count 0 2006.238.08:10:32.67#ibcon#read 3, iclass 17, count 0 2006.238.08:10:32.67#ibcon#about to read 4, iclass 17, count 0 2006.238.08:10:32.67#ibcon#read 4, iclass 17, count 0 2006.238.08:10:32.67#ibcon#about to read 5, iclass 17, count 0 2006.238.08:10:32.67#ibcon#read 5, iclass 17, count 0 2006.238.08:10:32.67#ibcon#about to read 6, iclass 17, count 0 2006.238.08:10:32.67#ibcon#read 6, iclass 17, count 0 2006.238.08:10:32.67#ibcon#end of sib2, iclass 17, count 0 2006.238.08:10:32.67#ibcon#*after write, iclass 17, count 0 2006.238.08:10:32.67#ibcon#*before return 0, iclass 17, count 0 2006.238.08:10:32.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:10:32.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:10:32.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:10:32.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:10:32.67$vc4f8/vbbw=wide 2006.238.08:10:32.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.08:10:32.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.08:10:32.67#ibcon#ireg 8 cls_cnt 0 2006.238.08:10:32.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:10:32.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:10:32.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:10:32.74#ibcon#enter wrdev, iclass 19, count 0 2006.238.08:10:32.74#ibcon#first serial, iclass 19, count 0 2006.238.08:10:32.74#ibcon#enter sib2, iclass 19, count 0 2006.238.08:10:32.74#ibcon#flushed, iclass 19, count 0 2006.238.08:10:32.74#ibcon#about to write, iclass 19, count 0 2006.238.08:10:32.74#ibcon#wrote, iclass 19, count 0 2006.238.08:10:32.74#ibcon#about to read 3, iclass 19, count 0 2006.238.08:10:32.76#ibcon#read 3, iclass 19, count 0 2006.238.08:10:32.76#ibcon#about to read 4, iclass 19, count 0 2006.238.08:10:32.76#ibcon#read 4, iclass 19, count 0 2006.238.08:10:32.76#ibcon#about to read 5, iclass 19, count 0 2006.238.08:10:32.76#ibcon#read 5, iclass 19, count 0 2006.238.08:10:32.76#ibcon#about to read 6, iclass 19, count 0 2006.238.08:10:32.76#ibcon#read 6, iclass 19, count 0 2006.238.08:10:32.76#ibcon#end of sib2, iclass 19, count 0 2006.238.08:10:32.76#ibcon#*mode == 0, iclass 19, count 0 2006.238.08:10:32.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.08:10:32.76#ibcon#[27=BW32\r\n] 2006.238.08:10:32.76#ibcon#*before write, iclass 19, count 0 2006.238.08:10:32.76#ibcon#enter sib2, iclass 19, count 0 2006.238.08:10:32.76#ibcon#flushed, iclass 19, count 0 2006.238.08:10:32.76#ibcon#about to write, iclass 19, count 0 2006.238.08:10:32.76#ibcon#wrote, iclass 19, count 0 2006.238.08:10:32.76#ibcon#about to read 3, iclass 19, count 0 2006.238.08:10:32.79#ibcon#read 3, iclass 19, count 0 2006.238.08:10:32.79#ibcon#about to read 4, iclass 19, count 0 2006.238.08:10:32.79#ibcon#read 4, iclass 19, count 0 2006.238.08:10:32.79#ibcon#about to read 5, iclass 19, count 0 2006.238.08:10:32.79#ibcon#read 5, iclass 19, count 0 2006.238.08:10:32.79#ibcon#about to read 6, iclass 19, count 0 2006.238.08:10:32.79#ibcon#read 6, iclass 19, count 0 2006.238.08:10:32.79#ibcon#end of sib2, iclass 19, count 0 2006.238.08:10:32.79#ibcon#*after write, iclass 19, count 0 2006.238.08:10:32.79#ibcon#*before return 0, iclass 19, count 0 2006.238.08:10:32.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:10:32.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:10:32.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.08:10:32.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.08:10:32.79$4f8m12a/ifd4f 2006.238.08:10:32.79$ifd4f/lo= 2006.238.08:10:32.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:10:32.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:10:32.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:10:32.79$ifd4f/patch= 2006.238.08:10:32.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:10:32.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:10:32.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:10:32.79$4f8m12a/"form=m,16.000,1:2 2006.238.08:10:32.79$4f8m12a/"tpicd 2006.238.08:10:32.79$4f8m12a/echo=off 2006.238.08:10:32.79$4f8m12a/xlog=off 2006.238.08:10:32.79:!2006.238.08:11:00 2006.238.08:10:47.14#trakl#Source acquired 2006.238.08:10:48.14#flagr#flagr/antenna,acquired 2006.238.08:11:00.00:preob 2006.238.08:11:01.14/onsource/TRACKING 2006.238.08:11:01.14:!2006.238.08:11:10 2006.238.08:11:10.00:data_valid=on 2006.238.08:11:10.00:midob 2006.238.08:11:10.14/onsource/TRACKING 2006.238.08:11:10.14/wx/25.47,1012.2,90 2006.238.08:11:10.34/cable/+6.4167E-03 2006.238.08:11:11.43/va/01,08,usb,yes,36,38 2006.238.08:11:11.43/va/02,07,usb,yes,36,38 2006.238.08:11:11.43/va/03,07,usb,yes,34,34 2006.238.08:11:11.43/va/04,07,usb,yes,38,41 2006.238.08:11:11.43/va/05,08,usb,yes,35,36 2006.238.08:11:11.43/va/06,07,usb,yes,38,38 2006.238.08:11:11.43/va/07,07,usb,yes,38,37 2006.238.08:11:11.43/va/08,07,usb,yes,41,40 2006.238.08:11:11.66/valo/01,532.99,yes,locked 2006.238.08:11:11.66/valo/02,572.99,yes,locked 2006.238.08:11:11.66/valo/03,672.99,yes,locked 2006.238.08:11:11.66/valo/04,832.99,yes,locked 2006.238.08:11:11.66/valo/05,652.99,yes,locked 2006.238.08:11:11.66/valo/06,772.99,yes,locked 2006.238.08:11:11.66/valo/07,832.99,yes,locked 2006.238.08:11:11.66/valo/08,852.99,yes,locked 2006.238.08:11:12.75/vb/01,04,usb,yes,33,49 2006.238.08:11:12.75/vb/02,04,usb,yes,35,48 2006.238.08:11:12.75/vb/03,04,usb,yes,31,36 2006.238.08:11:12.75/vb/04,04,usb,yes,32,32 2006.238.08:11:12.75/vb/05,04,usb,yes,31,36 2006.238.08:11:12.75/vb/06,04,usb,yes,32,35 2006.238.08:11:12.75/vb/07,04,usb,yes,34,34 2006.238.08:11:12.75/vb/08,04,usb,yes,31,35 2006.238.08:11:12.98/vblo/01,632.99,yes,locked 2006.238.08:11:12.98/vblo/02,640.99,yes,locked 2006.238.08:11:12.98/vblo/03,656.99,yes,locked 2006.238.08:11:12.98/vblo/04,712.99,yes,locked 2006.238.08:11:12.98/vblo/05,744.99,yes,locked 2006.238.08:11:12.98/vblo/06,752.99,yes,locked 2006.238.08:11:12.98/vblo/07,734.99,yes,locked 2006.238.08:11:12.98/vblo/08,744.99,yes,locked 2006.238.08:11:13.13/vabw/8 2006.238.08:11:13.28/vbbw/8 2006.238.08:11:13.37/xfe/off,on,13.2 2006.238.08:11:13.75/ifatt/23,28,28,28 2006.238.08:11:14.07/fmout-gps/S +4.40E-07 2006.238.08:11:14.11:!2006.238.08:12:10 2006.238.08:12:10.00:data_valid=off 2006.238.08:12:10.00:postob 2006.238.08:12:10.10/cable/+6.4186E-03 2006.238.08:12:10.10/wx/25.47,1012.2,90 2006.238.08:12:11.08/fmout-gps/S +4.42E-07 2006.238.08:12:11.08:scan_name=238-0813,k06238,60 2006.238.08:12:11.09:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.238.08:12:11.14#flagr#flagr/antenna,new-source 2006.238.08:12:12.14:checkk5 2006.238.08:12:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:12:12.91/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:12:13.29/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:12:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:12:14.04/chk_obsdata//k5ts1/T2380811??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:12:14.41/chk_obsdata//k5ts2/T2380811??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:12:14.78/chk_obsdata//k5ts3/T2380811??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:12:15.15/chk_obsdata//k5ts4/T2380811??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:12:15.83/k5log//k5ts1_log_newline 2006.238.08:12:16.53/k5log//k5ts2_log_newline 2006.238.08:12:17.22/k5log//k5ts3_log_newline 2006.238.08:12:17.90/k5log//k5ts4_log_newline 2006.238.08:12:17.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:12:17.93:4f8m12a=2 2006.238.08:12:17.93$4f8m12a/echo=on 2006.238.08:12:17.93$4f8m12a/pcalon 2006.238.08:12:17.93$pcalon/"no phase cal control is implemented here 2006.238.08:12:17.93$4f8m12a/"tpicd=stop 2006.238.08:12:17.93$4f8m12a/vc4f8 2006.238.08:12:17.93$vc4f8/valo=1,532.99 2006.238.08:12:17.93#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.08:12:17.93#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.08:12:17.93#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:17.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:12:17.93#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:12:17.93#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:12:17.93#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:12:17.93#ibcon#first serial, iclass 26, count 0 2006.238.08:12:17.93#ibcon#enter sib2, iclass 26, count 0 2006.238.08:12:17.93#ibcon#flushed, iclass 26, count 0 2006.238.08:12:17.93#ibcon#about to write, iclass 26, count 0 2006.238.08:12:17.93#ibcon#wrote, iclass 26, count 0 2006.238.08:12:17.93#ibcon#about to read 3, iclass 26, count 0 2006.238.08:12:17.98#ibcon#read 3, iclass 26, count 0 2006.238.08:12:17.98#ibcon#about to read 4, iclass 26, count 0 2006.238.08:12:17.98#ibcon#read 4, iclass 26, count 0 2006.238.08:12:17.98#ibcon#about to read 5, iclass 26, count 0 2006.238.08:12:17.98#ibcon#read 5, iclass 26, count 0 2006.238.08:12:17.98#ibcon#about to read 6, iclass 26, count 0 2006.238.08:12:17.98#ibcon#read 6, iclass 26, count 0 2006.238.08:12:17.98#ibcon#end of sib2, iclass 26, count 0 2006.238.08:12:17.98#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:12:17.98#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:12:17.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:12:17.98#ibcon#*before write, iclass 26, count 0 2006.238.08:12:17.98#ibcon#enter sib2, iclass 26, count 0 2006.238.08:12:17.98#ibcon#flushed, iclass 26, count 0 2006.238.08:12:17.98#ibcon#about to write, iclass 26, count 0 2006.238.08:12:17.98#ibcon#wrote, iclass 26, count 0 2006.238.08:12:17.98#ibcon#about to read 3, iclass 26, count 0 2006.238.08:12:18.02#ibcon#read 3, iclass 26, count 0 2006.238.08:12:18.02#ibcon#about to read 4, iclass 26, count 0 2006.238.08:12:18.02#ibcon#read 4, iclass 26, count 0 2006.238.08:12:18.02#ibcon#about to read 5, iclass 26, count 0 2006.238.08:12:18.02#ibcon#read 5, iclass 26, count 0 2006.238.08:12:18.02#ibcon#about to read 6, iclass 26, count 0 2006.238.08:12:18.02#ibcon#read 6, iclass 26, count 0 2006.238.08:12:18.02#ibcon#end of sib2, iclass 26, count 0 2006.238.08:12:18.02#ibcon#*after write, iclass 26, count 0 2006.238.08:12:18.02#ibcon#*before return 0, iclass 26, count 0 2006.238.08:12:18.02#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:12:18.02#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:12:18.02#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:12:18.02#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:12:18.02$vc4f8/va=1,8 2006.238.08:12:18.02#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.08:12:18.02#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.08:12:18.02#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:18.02#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:12:18.02#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:12:18.02#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:12:18.02#ibcon#enter wrdev, iclass 28, count 2 2006.238.08:12:18.02#ibcon#first serial, iclass 28, count 2 2006.238.08:12:18.02#ibcon#enter sib2, iclass 28, count 2 2006.238.08:12:18.02#ibcon#flushed, iclass 28, count 2 2006.238.08:12:18.02#ibcon#about to write, iclass 28, count 2 2006.238.08:12:18.02#ibcon#wrote, iclass 28, count 2 2006.238.08:12:18.02#ibcon#about to read 3, iclass 28, count 2 2006.238.08:12:18.04#ibcon#read 3, iclass 28, count 2 2006.238.08:12:18.04#ibcon#about to read 4, iclass 28, count 2 2006.238.08:12:18.04#ibcon#read 4, iclass 28, count 2 2006.238.08:12:18.04#ibcon#about to read 5, iclass 28, count 2 2006.238.08:12:18.04#ibcon#read 5, iclass 28, count 2 2006.238.08:12:18.04#ibcon#about to read 6, iclass 28, count 2 2006.238.08:12:18.04#ibcon#read 6, iclass 28, count 2 2006.238.08:12:18.04#ibcon#end of sib2, iclass 28, count 2 2006.238.08:12:18.04#ibcon#*mode == 0, iclass 28, count 2 2006.238.08:12:18.04#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.08:12:18.04#ibcon#[25=AT01-08\r\n] 2006.238.08:12:18.04#ibcon#*before write, iclass 28, count 2 2006.238.08:12:18.04#ibcon#enter sib2, iclass 28, count 2 2006.238.08:12:18.04#ibcon#flushed, iclass 28, count 2 2006.238.08:12:18.04#ibcon#about to write, iclass 28, count 2 2006.238.08:12:18.04#ibcon#wrote, iclass 28, count 2 2006.238.08:12:18.04#ibcon#about to read 3, iclass 28, count 2 2006.238.08:12:18.07#ibcon#read 3, iclass 28, count 2 2006.238.08:12:18.07#ibcon#about to read 4, iclass 28, count 2 2006.238.08:12:18.07#ibcon#read 4, iclass 28, count 2 2006.238.08:12:18.07#ibcon#about to read 5, iclass 28, count 2 2006.238.08:12:18.07#ibcon#read 5, iclass 28, count 2 2006.238.08:12:18.07#ibcon#about to read 6, iclass 28, count 2 2006.238.08:12:18.07#ibcon#read 6, iclass 28, count 2 2006.238.08:12:18.07#ibcon#end of sib2, iclass 28, count 2 2006.238.08:12:18.07#ibcon#*after write, iclass 28, count 2 2006.238.08:12:18.07#ibcon#*before return 0, iclass 28, count 2 2006.238.08:12:18.07#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:12:18.07#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:12:18.07#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.08:12:18.07#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:18.07#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:12:18.19#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:12:18.19#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:12:18.19#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:12:18.19#ibcon#first serial, iclass 28, count 0 2006.238.08:12:18.19#ibcon#enter sib2, iclass 28, count 0 2006.238.08:12:18.19#ibcon#flushed, iclass 28, count 0 2006.238.08:12:18.19#ibcon#about to write, iclass 28, count 0 2006.238.08:12:18.19#ibcon#wrote, iclass 28, count 0 2006.238.08:12:18.19#ibcon#about to read 3, iclass 28, count 0 2006.238.08:12:18.21#ibcon#read 3, iclass 28, count 0 2006.238.08:12:18.21#ibcon#about to read 4, iclass 28, count 0 2006.238.08:12:18.21#ibcon#read 4, iclass 28, count 0 2006.238.08:12:18.21#ibcon#about to read 5, iclass 28, count 0 2006.238.08:12:18.21#ibcon#read 5, iclass 28, count 0 2006.238.08:12:18.21#ibcon#about to read 6, iclass 28, count 0 2006.238.08:12:18.21#ibcon#read 6, iclass 28, count 0 2006.238.08:12:18.21#ibcon#end of sib2, iclass 28, count 0 2006.238.08:12:18.21#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:12:18.21#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:12:18.21#ibcon#[25=USB\r\n] 2006.238.08:12:18.21#ibcon#*before write, iclass 28, count 0 2006.238.08:12:18.21#ibcon#enter sib2, iclass 28, count 0 2006.238.08:12:18.21#ibcon#flushed, iclass 28, count 0 2006.238.08:12:18.21#ibcon#about to write, iclass 28, count 0 2006.238.08:12:18.21#ibcon#wrote, iclass 28, count 0 2006.238.08:12:18.21#ibcon#about to read 3, iclass 28, count 0 2006.238.08:12:18.24#ibcon#read 3, iclass 28, count 0 2006.238.08:12:18.24#ibcon#about to read 4, iclass 28, count 0 2006.238.08:12:18.24#ibcon#read 4, iclass 28, count 0 2006.238.08:12:18.24#ibcon#about to read 5, iclass 28, count 0 2006.238.08:12:18.24#ibcon#read 5, iclass 28, count 0 2006.238.08:12:18.24#ibcon#about to read 6, iclass 28, count 0 2006.238.08:12:18.24#ibcon#read 6, iclass 28, count 0 2006.238.08:12:18.24#ibcon#end of sib2, iclass 28, count 0 2006.238.08:12:18.24#ibcon#*after write, iclass 28, count 0 2006.238.08:12:18.24#ibcon#*before return 0, iclass 28, count 0 2006.238.08:12:18.24#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:12:18.24#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:12:18.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:12:18.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:12:18.24$vc4f8/valo=2,572.99 2006.238.08:12:18.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.08:12:18.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.08:12:18.24#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:18.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:12:18.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:12:18.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:12:18.24#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:12:18.24#ibcon#first serial, iclass 30, count 0 2006.238.08:12:18.24#ibcon#enter sib2, iclass 30, count 0 2006.238.08:12:18.24#ibcon#flushed, iclass 30, count 0 2006.238.08:12:18.24#ibcon#about to write, iclass 30, count 0 2006.238.08:12:18.24#ibcon#wrote, iclass 30, count 0 2006.238.08:12:18.24#ibcon#about to read 3, iclass 30, count 0 2006.238.08:12:18.26#ibcon#read 3, iclass 30, count 0 2006.238.08:12:18.26#ibcon#about to read 4, iclass 30, count 0 2006.238.08:12:18.26#ibcon#read 4, iclass 30, count 0 2006.238.08:12:18.26#ibcon#about to read 5, iclass 30, count 0 2006.238.08:12:18.26#ibcon#read 5, iclass 30, count 0 2006.238.08:12:18.26#ibcon#about to read 6, iclass 30, count 0 2006.238.08:12:18.26#ibcon#read 6, iclass 30, count 0 2006.238.08:12:18.26#ibcon#end of sib2, iclass 30, count 0 2006.238.08:12:18.26#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:12:18.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:12:18.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:12:18.26#ibcon#*before write, iclass 30, count 0 2006.238.08:12:18.26#ibcon#enter sib2, iclass 30, count 0 2006.238.08:12:18.26#ibcon#flushed, iclass 30, count 0 2006.238.08:12:18.26#ibcon#about to write, iclass 30, count 0 2006.238.08:12:18.26#ibcon#wrote, iclass 30, count 0 2006.238.08:12:18.26#ibcon#about to read 3, iclass 30, count 0 2006.238.08:12:18.30#ibcon#read 3, iclass 30, count 0 2006.238.08:12:18.30#ibcon#about to read 4, iclass 30, count 0 2006.238.08:12:18.30#ibcon#read 4, iclass 30, count 0 2006.238.08:12:18.30#ibcon#about to read 5, iclass 30, count 0 2006.238.08:12:18.30#ibcon#read 5, iclass 30, count 0 2006.238.08:12:18.30#ibcon#about to read 6, iclass 30, count 0 2006.238.08:12:18.30#ibcon#read 6, iclass 30, count 0 2006.238.08:12:18.30#ibcon#end of sib2, iclass 30, count 0 2006.238.08:12:18.30#ibcon#*after write, iclass 30, count 0 2006.238.08:12:18.30#ibcon#*before return 0, iclass 30, count 0 2006.238.08:12:18.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:12:18.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:12:18.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:12:18.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:12:18.30$vc4f8/va=2,7 2006.238.08:12:18.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.238.08:12:18.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.238.08:12:18.30#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:18.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:12:18.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:12:18.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:12:18.36#ibcon#enter wrdev, iclass 32, count 2 2006.238.08:12:18.36#ibcon#first serial, iclass 32, count 2 2006.238.08:12:18.36#ibcon#enter sib2, iclass 32, count 2 2006.238.08:12:18.36#ibcon#flushed, iclass 32, count 2 2006.238.08:12:18.36#ibcon#about to write, iclass 32, count 2 2006.238.08:12:18.36#ibcon#wrote, iclass 32, count 2 2006.238.08:12:18.36#ibcon#about to read 3, iclass 32, count 2 2006.238.08:12:18.38#ibcon#read 3, iclass 32, count 2 2006.238.08:12:18.38#ibcon#about to read 4, iclass 32, count 2 2006.238.08:12:18.38#ibcon#read 4, iclass 32, count 2 2006.238.08:12:18.38#ibcon#about to read 5, iclass 32, count 2 2006.238.08:12:18.38#ibcon#read 5, iclass 32, count 2 2006.238.08:12:18.38#ibcon#about to read 6, iclass 32, count 2 2006.238.08:12:18.38#ibcon#read 6, iclass 32, count 2 2006.238.08:12:18.38#ibcon#end of sib2, iclass 32, count 2 2006.238.08:12:18.38#ibcon#*mode == 0, iclass 32, count 2 2006.238.08:12:18.38#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.238.08:12:18.38#ibcon#[25=AT02-07\r\n] 2006.238.08:12:18.38#ibcon#*before write, iclass 32, count 2 2006.238.08:12:18.38#ibcon#enter sib2, iclass 32, count 2 2006.238.08:12:18.38#ibcon#flushed, iclass 32, count 2 2006.238.08:12:18.38#ibcon#about to write, iclass 32, count 2 2006.238.08:12:18.38#ibcon#wrote, iclass 32, count 2 2006.238.08:12:18.38#ibcon#about to read 3, iclass 32, count 2 2006.238.08:12:18.41#ibcon#read 3, iclass 32, count 2 2006.238.08:12:18.41#ibcon#about to read 4, iclass 32, count 2 2006.238.08:12:18.41#ibcon#read 4, iclass 32, count 2 2006.238.08:12:18.41#ibcon#about to read 5, iclass 32, count 2 2006.238.08:12:18.41#ibcon#read 5, iclass 32, count 2 2006.238.08:12:18.41#ibcon#about to read 6, iclass 32, count 2 2006.238.08:12:18.41#ibcon#read 6, iclass 32, count 2 2006.238.08:12:18.41#ibcon#end of sib2, iclass 32, count 2 2006.238.08:12:18.41#ibcon#*after write, iclass 32, count 2 2006.238.08:12:18.41#ibcon#*before return 0, iclass 32, count 2 2006.238.08:12:18.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:12:18.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:12:18.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.238.08:12:18.41#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:18.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:12:18.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:12:18.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:12:18.53#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:12:18.53#ibcon#first serial, iclass 32, count 0 2006.238.08:12:18.53#ibcon#enter sib2, iclass 32, count 0 2006.238.08:12:18.53#ibcon#flushed, iclass 32, count 0 2006.238.08:12:18.53#ibcon#about to write, iclass 32, count 0 2006.238.08:12:18.53#ibcon#wrote, iclass 32, count 0 2006.238.08:12:18.53#ibcon#about to read 3, iclass 32, count 0 2006.238.08:12:18.55#ibcon#read 3, iclass 32, count 0 2006.238.08:12:18.55#ibcon#about to read 4, iclass 32, count 0 2006.238.08:12:18.55#ibcon#read 4, iclass 32, count 0 2006.238.08:12:18.55#ibcon#about to read 5, iclass 32, count 0 2006.238.08:12:18.55#ibcon#read 5, iclass 32, count 0 2006.238.08:12:18.55#ibcon#about to read 6, iclass 32, count 0 2006.238.08:12:18.55#ibcon#read 6, iclass 32, count 0 2006.238.08:12:18.55#ibcon#end of sib2, iclass 32, count 0 2006.238.08:12:18.55#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:12:18.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:12:18.55#ibcon#[25=USB\r\n] 2006.238.08:12:18.55#ibcon#*before write, iclass 32, count 0 2006.238.08:12:18.55#ibcon#enter sib2, iclass 32, count 0 2006.238.08:12:18.55#ibcon#flushed, iclass 32, count 0 2006.238.08:12:18.55#ibcon#about to write, iclass 32, count 0 2006.238.08:12:18.55#ibcon#wrote, iclass 32, count 0 2006.238.08:12:18.55#ibcon#about to read 3, iclass 32, count 0 2006.238.08:12:18.58#ibcon#read 3, iclass 32, count 0 2006.238.08:12:18.58#ibcon#about to read 4, iclass 32, count 0 2006.238.08:12:18.58#ibcon#read 4, iclass 32, count 0 2006.238.08:12:18.58#ibcon#about to read 5, iclass 32, count 0 2006.238.08:12:18.58#ibcon#read 5, iclass 32, count 0 2006.238.08:12:18.58#ibcon#about to read 6, iclass 32, count 0 2006.238.08:12:18.58#ibcon#read 6, iclass 32, count 0 2006.238.08:12:18.58#ibcon#end of sib2, iclass 32, count 0 2006.238.08:12:18.58#ibcon#*after write, iclass 32, count 0 2006.238.08:12:18.58#ibcon#*before return 0, iclass 32, count 0 2006.238.08:12:18.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:12:18.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:12:18.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:12:18.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:12:18.58$vc4f8/valo=3,672.99 2006.238.08:12:18.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.238.08:12:18.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.238.08:12:18.58#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:18.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:12:18.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:12:18.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:12:18.58#ibcon#enter wrdev, iclass 34, count 0 2006.238.08:12:18.58#ibcon#first serial, iclass 34, count 0 2006.238.08:12:18.58#ibcon#enter sib2, iclass 34, count 0 2006.238.08:12:18.58#ibcon#flushed, iclass 34, count 0 2006.238.08:12:18.58#ibcon#about to write, iclass 34, count 0 2006.238.08:12:18.58#ibcon#wrote, iclass 34, count 0 2006.238.08:12:18.58#ibcon#about to read 3, iclass 34, count 0 2006.238.08:12:18.60#ibcon#read 3, iclass 34, count 0 2006.238.08:12:18.60#ibcon#about to read 4, iclass 34, count 0 2006.238.08:12:18.60#ibcon#read 4, iclass 34, count 0 2006.238.08:12:18.60#ibcon#about to read 5, iclass 34, count 0 2006.238.08:12:18.60#ibcon#read 5, iclass 34, count 0 2006.238.08:12:18.60#ibcon#about to read 6, iclass 34, count 0 2006.238.08:12:18.60#ibcon#read 6, iclass 34, count 0 2006.238.08:12:18.60#ibcon#end of sib2, iclass 34, count 0 2006.238.08:12:18.60#ibcon#*mode == 0, iclass 34, count 0 2006.238.08:12:18.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.08:12:18.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:12:18.60#ibcon#*before write, iclass 34, count 0 2006.238.08:12:18.60#ibcon#enter sib2, iclass 34, count 0 2006.238.08:12:18.60#ibcon#flushed, iclass 34, count 0 2006.238.08:12:18.60#ibcon#about to write, iclass 34, count 0 2006.238.08:12:18.60#ibcon#wrote, iclass 34, count 0 2006.238.08:12:18.60#ibcon#about to read 3, iclass 34, count 0 2006.238.08:12:18.64#ibcon#read 3, iclass 34, count 0 2006.238.08:12:18.64#ibcon#about to read 4, iclass 34, count 0 2006.238.08:12:18.64#ibcon#read 4, iclass 34, count 0 2006.238.08:12:18.64#ibcon#about to read 5, iclass 34, count 0 2006.238.08:12:18.64#ibcon#read 5, iclass 34, count 0 2006.238.08:12:18.64#ibcon#about to read 6, iclass 34, count 0 2006.238.08:12:18.64#ibcon#read 6, iclass 34, count 0 2006.238.08:12:18.64#ibcon#end of sib2, iclass 34, count 0 2006.238.08:12:18.64#ibcon#*after write, iclass 34, count 0 2006.238.08:12:18.64#ibcon#*before return 0, iclass 34, count 0 2006.238.08:12:18.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:12:18.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:12:18.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.08:12:18.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.08:12:18.64$vc4f8/va=3,7 2006.238.08:12:18.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.238.08:12:18.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.238.08:12:18.64#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:18.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:12:18.70#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:12:18.70#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:12:18.70#ibcon#enter wrdev, iclass 36, count 2 2006.238.08:12:18.70#ibcon#first serial, iclass 36, count 2 2006.238.08:12:18.70#ibcon#enter sib2, iclass 36, count 2 2006.238.08:12:18.70#ibcon#flushed, iclass 36, count 2 2006.238.08:12:18.70#ibcon#about to write, iclass 36, count 2 2006.238.08:12:18.70#ibcon#wrote, iclass 36, count 2 2006.238.08:12:18.70#ibcon#about to read 3, iclass 36, count 2 2006.238.08:12:18.72#ibcon#read 3, iclass 36, count 2 2006.238.08:12:18.72#ibcon#about to read 4, iclass 36, count 2 2006.238.08:12:18.72#ibcon#read 4, iclass 36, count 2 2006.238.08:12:18.72#ibcon#about to read 5, iclass 36, count 2 2006.238.08:12:18.72#ibcon#read 5, iclass 36, count 2 2006.238.08:12:18.72#ibcon#about to read 6, iclass 36, count 2 2006.238.08:12:18.72#ibcon#read 6, iclass 36, count 2 2006.238.08:12:18.72#ibcon#end of sib2, iclass 36, count 2 2006.238.08:12:18.72#ibcon#*mode == 0, iclass 36, count 2 2006.238.08:12:18.72#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.238.08:12:18.72#ibcon#[25=AT03-07\r\n] 2006.238.08:12:18.72#ibcon#*before write, iclass 36, count 2 2006.238.08:12:18.72#ibcon#enter sib2, iclass 36, count 2 2006.238.08:12:18.72#ibcon#flushed, iclass 36, count 2 2006.238.08:12:18.72#ibcon#about to write, iclass 36, count 2 2006.238.08:12:18.72#ibcon#wrote, iclass 36, count 2 2006.238.08:12:18.72#ibcon#about to read 3, iclass 36, count 2 2006.238.08:12:18.75#ibcon#read 3, iclass 36, count 2 2006.238.08:12:18.75#ibcon#about to read 4, iclass 36, count 2 2006.238.08:12:18.75#ibcon#read 4, iclass 36, count 2 2006.238.08:12:18.75#ibcon#about to read 5, iclass 36, count 2 2006.238.08:12:18.75#ibcon#read 5, iclass 36, count 2 2006.238.08:12:18.75#ibcon#about to read 6, iclass 36, count 2 2006.238.08:12:18.75#ibcon#read 6, iclass 36, count 2 2006.238.08:12:18.75#ibcon#end of sib2, iclass 36, count 2 2006.238.08:12:18.75#ibcon#*after write, iclass 36, count 2 2006.238.08:12:18.75#ibcon#*before return 0, iclass 36, count 2 2006.238.08:12:18.75#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:12:18.75#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:12:18.75#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.238.08:12:18.75#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:18.75#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:12:18.87#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:12:18.87#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:12:18.87#ibcon#enter wrdev, iclass 36, count 0 2006.238.08:12:18.87#ibcon#first serial, iclass 36, count 0 2006.238.08:12:18.87#ibcon#enter sib2, iclass 36, count 0 2006.238.08:12:18.87#ibcon#flushed, iclass 36, count 0 2006.238.08:12:18.87#ibcon#about to write, iclass 36, count 0 2006.238.08:12:18.87#ibcon#wrote, iclass 36, count 0 2006.238.08:12:18.87#ibcon#about to read 3, iclass 36, count 0 2006.238.08:12:18.89#ibcon#read 3, iclass 36, count 0 2006.238.08:12:18.89#ibcon#about to read 4, iclass 36, count 0 2006.238.08:12:18.89#ibcon#read 4, iclass 36, count 0 2006.238.08:12:18.89#ibcon#about to read 5, iclass 36, count 0 2006.238.08:12:18.89#ibcon#read 5, iclass 36, count 0 2006.238.08:12:18.89#ibcon#about to read 6, iclass 36, count 0 2006.238.08:12:18.89#ibcon#read 6, iclass 36, count 0 2006.238.08:12:18.89#ibcon#end of sib2, iclass 36, count 0 2006.238.08:12:18.89#ibcon#*mode == 0, iclass 36, count 0 2006.238.08:12:18.89#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.08:12:18.89#ibcon#[25=USB\r\n] 2006.238.08:12:18.89#ibcon#*before write, iclass 36, count 0 2006.238.08:12:18.89#ibcon#enter sib2, iclass 36, count 0 2006.238.08:12:18.89#ibcon#flushed, iclass 36, count 0 2006.238.08:12:18.89#ibcon#about to write, iclass 36, count 0 2006.238.08:12:18.89#ibcon#wrote, iclass 36, count 0 2006.238.08:12:18.89#ibcon#about to read 3, iclass 36, count 0 2006.238.08:12:18.92#ibcon#read 3, iclass 36, count 0 2006.238.08:12:18.92#ibcon#about to read 4, iclass 36, count 0 2006.238.08:12:18.92#ibcon#read 4, iclass 36, count 0 2006.238.08:12:18.92#ibcon#about to read 5, iclass 36, count 0 2006.238.08:12:18.92#ibcon#read 5, iclass 36, count 0 2006.238.08:12:18.92#ibcon#about to read 6, iclass 36, count 0 2006.238.08:12:18.92#ibcon#read 6, iclass 36, count 0 2006.238.08:12:18.92#ibcon#end of sib2, iclass 36, count 0 2006.238.08:12:18.92#ibcon#*after write, iclass 36, count 0 2006.238.08:12:18.92#ibcon#*before return 0, iclass 36, count 0 2006.238.08:12:18.92#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:12:18.92#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:12:18.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.08:12:18.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.08:12:18.92$vc4f8/valo=4,832.99 2006.238.08:12:18.92#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.238.08:12:18.92#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.238.08:12:18.92#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:18.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:12:18.92#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:12:18.92#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:12:18.92#ibcon#enter wrdev, iclass 38, count 0 2006.238.08:12:18.92#ibcon#first serial, iclass 38, count 0 2006.238.08:12:18.92#ibcon#enter sib2, iclass 38, count 0 2006.238.08:12:18.92#ibcon#flushed, iclass 38, count 0 2006.238.08:12:18.92#ibcon#about to write, iclass 38, count 0 2006.238.08:12:18.92#ibcon#wrote, iclass 38, count 0 2006.238.08:12:18.92#ibcon#about to read 3, iclass 38, count 0 2006.238.08:12:18.94#ibcon#read 3, iclass 38, count 0 2006.238.08:12:18.94#ibcon#about to read 4, iclass 38, count 0 2006.238.08:12:18.94#ibcon#read 4, iclass 38, count 0 2006.238.08:12:18.94#ibcon#about to read 5, iclass 38, count 0 2006.238.08:12:18.94#ibcon#read 5, iclass 38, count 0 2006.238.08:12:18.94#ibcon#about to read 6, iclass 38, count 0 2006.238.08:12:18.94#ibcon#read 6, iclass 38, count 0 2006.238.08:12:18.94#ibcon#end of sib2, iclass 38, count 0 2006.238.08:12:18.94#ibcon#*mode == 0, iclass 38, count 0 2006.238.08:12:18.94#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.08:12:18.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:12:18.94#ibcon#*before write, iclass 38, count 0 2006.238.08:12:18.94#ibcon#enter sib2, iclass 38, count 0 2006.238.08:12:18.94#ibcon#flushed, iclass 38, count 0 2006.238.08:12:18.94#ibcon#about to write, iclass 38, count 0 2006.238.08:12:18.94#ibcon#wrote, iclass 38, count 0 2006.238.08:12:18.94#ibcon#about to read 3, iclass 38, count 0 2006.238.08:12:18.98#ibcon#read 3, iclass 38, count 0 2006.238.08:12:18.98#ibcon#about to read 4, iclass 38, count 0 2006.238.08:12:18.98#ibcon#read 4, iclass 38, count 0 2006.238.08:12:18.98#ibcon#about to read 5, iclass 38, count 0 2006.238.08:12:18.98#ibcon#read 5, iclass 38, count 0 2006.238.08:12:18.98#ibcon#about to read 6, iclass 38, count 0 2006.238.08:12:18.98#ibcon#read 6, iclass 38, count 0 2006.238.08:12:18.98#ibcon#end of sib2, iclass 38, count 0 2006.238.08:12:18.98#ibcon#*after write, iclass 38, count 0 2006.238.08:12:18.98#ibcon#*before return 0, iclass 38, count 0 2006.238.08:12:18.98#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:12:18.98#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:12:18.98#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.08:12:18.98#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.08:12:18.98$vc4f8/va=4,7 2006.238.08:12:18.98#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.238.08:12:18.98#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.238.08:12:18.98#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:18.98#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:12:19.04#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:12:19.04#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:12:19.04#ibcon#enter wrdev, iclass 40, count 2 2006.238.08:12:19.04#ibcon#first serial, iclass 40, count 2 2006.238.08:12:19.04#ibcon#enter sib2, iclass 40, count 2 2006.238.08:12:19.04#ibcon#flushed, iclass 40, count 2 2006.238.08:12:19.04#ibcon#about to write, iclass 40, count 2 2006.238.08:12:19.04#ibcon#wrote, iclass 40, count 2 2006.238.08:12:19.04#ibcon#about to read 3, iclass 40, count 2 2006.238.08:12:19.06#ibcon#read 3, iclass 40, count 2 2006.238.08:12:19.06#ibcon#about to read 4, iclass 40, count 2 2006.238.08:12:19.06#ibcon#read 4, iclass 40, count 2 2006.238.08:12:19.06#ibcon#about to read 5, iclass 40, count 2 2006.238.08:12:19.06#ibcon#read 5, iclass 40, count 2 2006.238.08:12:19.06#ibcon#about to read 6, iclass 40, count 2 2006.238.08:12:19.06#ibcon#read 6, iclass 40, count 2 2006.238.08:12:19.06#ibcon#end of sib2, iclass 40, count 2 2006.238.08:12:19.06#ibcon#*mode == 0, iclass 40, count 2 2006.238.08:12:19.06#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.238.08:12:19.06#ibcon#[25=AT04-07\r\n] 2006.238.08:12:19.06#ibcon#*before write, iclass 40, count 2 2006.238.08:12:19.06#ibcon#enter sib2, iclass 40, count 2 2006.238.08:12:19.06#ibcon#flushed, iclass 40, count 2 2006.238.08:12:19.06#ibcon#about to write, iclass 40, count 2 2006.238.08:12:19.06#ibcon#wrote, iclass 40, count 2 2006.238.08:12:19.06#ibcon#about to read 3, iclass 40, count 2 2006.238.08:12:19.09#ibcon#read 3, iclass 40, count 2 2006.238.08:12:19.09#ibcon#about to read 4, iclass 40, count 2 2006.238.08:12:19.09#ibcon#read 4, iclass 40, count 2 2006.238.08:12:19.09#ibcon#about to read 5, iclass 40, count 2 2006.238.08:12:19.09#ibcon#read 5, iclass 40, count 2 2006.238.08:12:19.09#ibcon#about to read 6, iclass 40, count 2 2006.238.08:12:19.09#ibcon#read 6, iclass 40, count 2 2006.238.08:12:19.09#ibcon#end of sib2, iclass 40, count 2 2006.238.08:12:19.09#ibcon#*after write, iclass 40, count 2 2006.238.08:12:19.09#ibcon#*before return 0, iclass 40, count 2 2006.238.08:12:19.09#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:12:19.09#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:12:19.09#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.238.08:12:19.09#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:19.09#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:12:19.21#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:12:19.21#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:12:19.21#ibcon#enter wrdev, iclass 40, count 0 2006.238.08:12:19.21#ibcon#first serial, iclass 40, count 0 2006.238.08:12:19.21#ibcon#enter sib2, iclass 40, count 0 2006.238.08:12:19.21#ibcon#flushed, iclass 40, count 0 2006.238.08:12:19.21#ibcon#about to write, iclass 40, count 0 2006.238.08:12:19.21#ibcon#wrote, iclass 40, count 0 2006.238.08:12:19.21#ibcon#about to read 3, iclass 40, count 0 2006.238.08:12:19.23#ibcon#read 3, iclass 40, count 0 2006.238.08:12:19.23#ibcon#about to read 4, iclass 40, count 0 2006.238.08:12:19.23#ibcon#read 4, iclass 40, count 0 2006.238.08:12:19.23#ibcon#about to read 5, iclass 40, count 0 2006.238.08:12:19.23#ibcon#read 5, iclass 40, count 0 2006.238.08:12:19.23#ibcon#about to read 6, iclass 40, count 0 2006.238.08:12:19.23#ibcon#read 6, iclass 40, count 0 2006.238.08:12:19.23#ibcon#end of sib2, iclass 40, count 0 2006.238.08:12:19.23#ibcon#*mode == 0, iclass 40, count 0 2006.238.08:12:19.23#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.08:12:19.23#ibcon#[25=USB\r\n] 2006.238.08:12:19.23#ibcon#*before write, iclass 40, count 0 2006.238.08:12:19.23#ibcon#enter sib2, iclass 40, count 0 2006.238.08:12:19.23#ibcon#flushed, iclass 40, count 0 2006.238.08:12:19.23#ibcon#about to write, iclass 40, count 0 2006.238.08:12:19.23#ibcon#wrote, iclass 40, count 0 2006.238.08:12:19.23#ibcon#about to read 3, iclass 40, count 0 2006.238.08:12:19.26#ibcon#read 3, iclass 40, count 0 2006.238.08:12:19.26#ibcon#about to read 4, iclass 40, count 0 2006.238.08:12:19.26#ibcon#read 4, iclass 40, count 0 2006.238.08:12:19.26#ibcon#about to read 5, iclass 40, count 0 2006.238.08:12:19.26#ibcon#read 5, iclass 40, count 0 2006.238.08:12:19.26#ibcon#about to read 6, iclass 40, count 0 2006.238.08:12:19.26#ibcon#read 6, iclass 40, count 0 2006.238.08:12:19.26#ibcon#end of sib2, iclass 40, count 0 2006.238.08:12:19.26#ibcon#*after write, iclass 40, count 0 2006.238.08:12:19.26#ibcon#*before return 0, iclass 40, count 0 2006.238.08:12:19.26#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:12:19.26#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:12:19.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.08:12:19.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.08:12:19.26$vc4f8/valo=5,652.99 2006.238.08:12:19.26#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.08:12:19.26#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.08:12:19.26#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:19.26#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:12:19.26#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:12:19.26#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:12:19.26#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:12:19.26#ibcon#first serial, iclass 4, count 0 2006.238.08:12:19.26#ibcon#enter sib2, iclass 4, count 0 2006.238.08:12:19.26#ibcon#flushed, iclass 4, count 0 2006.238.08:12:19.26#ibcon#about to write, iclass 4, count 0 2006.238.08:12:19.26#ibcon#wrote, iclass 4, count 0 2006.238.08:12:19.26#ibcon#about to read 3, iclass 4, count 0 2006.238.08:12:19.28#ibcon#read 3, iclass 4, count 0 2006.238.08:12:19.28#ibcon#about to read 4, iclass 4, count 0 2006.238.08:12:19.28#ibcon#read 4, iclass 4, count 0 2006.238.08:12:19.28#ibcon#about to read 5, iclass 4, count 0 2006.238.08:12:19.28#ibcon#read 5, iclass 4, count 0 2006.238.08:12:19.28#ibcon#about to read 6, iclass 4, count 0 2006.238.08:12:19.28#ibcon#read 6, iclass 4, count 0 2006.238.08:12:19.28#ibcon#end of sib2, iclass 4, count 0 2006.238.08:12:19.28#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:12:19.28#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:12:19.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:12:19.28#ibcon#*before write, iclass 4, count 0 2006.238.08:12:19.28#ibcon#enter sib2, iclass 4, count 0 2006.238.08:12:19.28#ibcon#flushed, iclass 4, count 0 2006.238.08:12:19.28#ibcon#about to write, iclass 4, count 0 2006.238.08:12:19.28#ibcon#wrote, iclass 4, count 0 2006.238.08:12:19.28#ibcon#about to read 3, iclass 4, count 0 2006.238.08:12:19.32#ibcon#read 3, iclass 4, count 0 2006.238.08:12:19.32#ibcon#about to read 4, iclass 4, count 0 2006.238.08:12:19.32#ibcon#read 4, iclass 4, count 0 2006.238.08:12:19.32#ibcon#about to read 5, iclass 4, count 0 2006.238.08:12:19.32#ibcon#read 5, iclass 4, count 0 2006.238.08:12:19.32#ibcon#about to read 6, iclass 4, count 0 2006.238.08:12:19.32#ibcon#read 6, iclass 4, count 0 2006.238.08:12:19.32#ibcon#end of sib2, iclass 4, count 0 2006.238.08:12:19.32#ibcon#*after write, iclass 4, count 0 2006.238.08:12:19.32#ibcon#*before return 0, iclass 4, count 0 2006.238.08:12:19.32#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:12:19.32#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:12:19.32#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:12:19.32#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:12:19.32$vc4f8/va=5,8 2006.238.08:12:19.32#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.08:12:19.32#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.08:12:19.32#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:19.32#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:12:19.38#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:12:19.38#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:12:19.38#ibcon#enter wrdev, iclass 6, count 2 2006.238.08:12:19.38#ibcon#first serial, iclass 6, count 2 2006.238.08:12:19.38#ibcon#enter sib2, iclass 6, count 2 2006.238.08:12:19.38#ibcon#flushed, iclass 6, count 2 2006.238.08:12:19.38#ibcon#about to write, iclass 6, count 2 2006.238.08:12:19.38#ibcon#wrote, iclass 6, count 2 2006.238.08:12:19.38#ibcon#about to read 3, iclass 6, count 2 2006.238.08:12:19.40#ibcon#read 3, iclass 6, count 2 2006.238.08:12:19.40#ibcon#about to read 4, iclass 6, count 2 2006.238.08:12:19.40#ibcon#read 4, iclass 6, count 2 2006.238.08:12:19.40#ibcon#about to read 5, iclass 6, count 2 2006.238.08:12:19.40#ibcon#read 5, iclass 6, count 2 2006.238.08:12:19.40#ibcon#about to read 6, iclass 6, count 2 2006.238.08:12:19.40#ibcon#read 6, iclass 6, count 2 2006.238.08:12:19.40#ibcon#end of sib2, iclass 6, count 2 2006.238.08:12:19.40#ibcon#*mode == 0, iclass 6, count 2 2006.238.08:12:19.40#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.08:12:19.40#ibcon#[25=AT05-08\r\n] 2006.238.08:12:19.40#ibcon#*before write, iclass 6, count 2 2006.238.08:12:19.40#ibcon#enter sib2, iclass 6, count 2 2006.238.08:12:19.40#ibcon#flushed, iclass 6, count 2 2006.238.08:12:19.40#ibcon#about to write, iclass 6, count 2 2006.238.08:12:19.40#ibcon#wrote, iclass 6, count 2 2006.238.08:12:19.40#ibcon#about to read 3, iclass 6, count 2 2006.238.08:12:19.43#ibcon#read 3, iclass 6, count 2 2006.238.08:12:19.43#ibcon#about to read 4, iclass 6, count 2 2006.238.08:12:19.43#ibcon#read 4, iclass 6, count 2 2006.238.08:12:19.43#ibcon#about to read 5, iclass 6, count 2 2006.238.08:12:19.43#ibcon#read 5, iclass 6, count 2 2006.238.08:12:19.43#ibcon#about to read 6, iclass 6, count 2 2006.238.08:12:19.43#ibcon#read 6, iclass 6, count 2 2006.238.08:12:19.43#ibcon#end of sib2, iclass 6, count 2 2006.238.08:12:19.43#ibcon#*after write, iclass 6, count 2 2006.238.08:12:19.43#ibcon#*before return 0, iclass 6, count 2 2006.238.08:12:19.43#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:12:19.43#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:12:19.43#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.08:12:19.43#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:19.43#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:12:19.52#abcon#<5=/04 1.9 3.5 25.47 901012.2\r\n> 2006.238.08:12:19.54#abcon#{5=INTERFACE CLEAR} 2006.238.08:12:19.55#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:12:19.55#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:12:19.55#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:12:19.55#ibcon#first serial, iclass 6, count 0 2006.238.08:12:19.55#ibcon#enter sib2, iclass 6, count 0 2006.238.08:12:19.55#ibcon#flushed, iclass 6, count 0 2006.238.08:12:19.55#ibcon#about to write, iclass 6, count 0 2006.238.08:12:19.55#ibcon#wrote, iclass 6, count 0 2006.238.08:12:19.55#ibcon#about to read 3, iclass 6, count 0 2006.238.08:12:19.57#ibcon#read 3, iclass 6, count 0 2006.238.08:12:19.57#ibcon#about to read 4, iclass 6, count 0 2006.238.08:12:19.57#ibcon#read 4, iclass 6, count 0 2006.238.08:12:19.57#ibcon#about to read 5, iclass 6, count 0 2006.238.08:12:19.57#ibcon#read 5, iclass 6, count 0 2006.238.08:12:19.57#ibcon#about to read 6, iclass 6, count 0 2006.238.08:12:19.57#ibcon#read 6, iclass 6, count 0 2006.238.08:12:19.57#ibcon#end of sib2, iclass 6, count 0 2006.238.08:12:19.57#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:12:19.57#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:12:19.57#ibcon#[25=USB\r\n] 2006.238.08:12:19.57#ibcon#*before write, iclass 6, count 0 2006.238.08:12:19.57#ibcon#enter sib2, iclass 6, count 0 2006.238.08:12:19.57#ibcon#flushed, iclass 6, count 0 2006.238.08:12:19.57#ibcon#about to write, iclass 6, count 0 2006.238.08:12:19.57#ibcon#wrote, iclass 6, count 0 2006.238.08:12:19.57#ibcon#about to read 3, iclass 6, count 0 2006.238.08:12:19.60#abcon#[5=S1D000X0/0*\r\n] 2006.238.08:12:19.60#ibcon#read 3, iclass 6, count 0 2006.238.08:12:19.60#ibcon#about to read 4, iclass 6, count 0 2006.238.08:12:19.60#ibcon#read 4, iclass 6, count 0 2006.238.08:12:19.60#ibcon#about to read 5, iclass 6, count 0 2006.238.08:12:19.60#ibcon#read 5, iclass 6, count 0 2006.238.08:12:19.60#ibcon#about to read 6, iclass 6, count 0 2006.238.08:12:19.60#ibcon#read 6, iclass 6, count 0 2006.238.08:12:19.60#ibcon#end of sib2, iclass 6, count 0 2006.238.08:12:19.60#ibcon#*after write, iclass 6, count 0 2006.238.08:12:19.60#ibcon#*before return 0, iclass 6, count 0 2006.238.08:12:19.60#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:12:19.60#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:12:19.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:12:19.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:12:19.60$vc4f8/valo=6,772.99 2006.238.08:12:19.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.08:12:19.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.08:12:19.60#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:19.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:12:19.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:12:19.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:12:19.60#ibcon#enter wrdev, iclass 14, count 0 2006.238.08:12:19.60#ibcon#first serial, iclass 14, count 0 2006.238.08:12:19.60#ibcon#enter sib2, iclass 14, count 0 2006.238.08:12:19.60#ibcon#flushed, iclass 14, count 0 2006.238.08:12:19.60#ibcon#about to write, iclass 14, count 0 2006.238.08:12:19.60#ibcon#wrote, iclass 14, count 0 2006.238.08:12:19.60#ibcon#about to read 3, iclass 14, count 0 2006.238.08:12:19.62#ibcon#read 3, iclass 14, count 0 2006.238.08:12:19.62#ibcon#about to read 4, iclass 14, count 0 2006.238.08:12:19.62#ibcon#read 4, iclass 14, count 0 2006.238.08:12:19.62#ibcon#about to read 5, iclass 14, count 0 2006.238.08:12:19.62#ibcon#read 5, iclass 14, count 0 2006.238.08:12:19.62#ibcon#about to read 6, iclass 14, count 0 2006.238.08:12:19.62#ibcon#read 6, iclass 14, count 0 2006.238.08:12:19.62#ibcon#end of sib2, iclass 14, count 0 2006.238.08:12:19.62#ibcon#*mode == 0, iclass 14, count 0 2006.238.08:12:19.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.08:12:19.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:12:19.62#ibcon#*before write, iclass 14, count 0 2006.238.08:12:19.62#ibcon#enter sib2, iclass 14, count 0 2006.238.08:12:19.62#ibcon#flushed, iclass 14, count 0 2006.238.08:12:19.62#ibcon#about to write, iclass 14, count 0 2006.238.08:12:19.62#ibcon#wrote, iclass 14, count 0 2006.238.08:12:19.62#ibcon#about to read 3, iclass 14, count 0 2006.238.08:12:19.66#ibcon#read 3, iclass 14, count 0 2006.238.08:12:19.66#ibcon#about to read 4, iclass 14, count 0 2006.238.08:12:19.66#ibcon#read 4, iclass 14, count 0 2006.238.08:12:19.66#ibcon#about to read 5, iclass 14, count 0 2006.238.08:12:19.66#ibcon#read 5, iclass 14, count 0 2006.238.08:12:19.66#ibcon#about to read 6, iclass 14, count 0 2006.238.08:12:19.66#ibcon#read 6, iclass 14, count 0 2006.238.08:12:19.66#ibcon#end of sib2, iclass 14, count 0 2006.238.08:12:19.66#ibcon#*after write, iclass 14, count 0 2006.238.08:12:19.66#ibcon#*before return 0, iclass 14, count 0 2006.238.08:12:19.66#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:12:19.66#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:12:19.66#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.08:12:19.66#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.08:12:19.66$vc4f8/va=6,7 2006.238.08:12:19.66#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.238.08:12:19.66#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.238.08:12:19.66#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:19.66#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:12:19.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:12:19.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:12:19.72#ibcon#enter wrdev, iclass 16, count 2 2006.238.08:12:19.72#ibcon#first serial, iclass 16, count 2 2006.238.08:12:19.72#ibcon#enter sib2, iclass 16, count 2 2006.238.08:12:19.72#ibcon#flushed, iclass 16, count 2 2006.238.08:12:19.72#ibcon#about to write, iclass 16, count 2 2006.238.08:12:19.72#ibcon#wrote, iclass 16, count 2 2006.238.08:12:19.72#ibcon#about to read 3, iclass 16, count 2 2006.238.08:12:19.74#ibcon#read 3, iclass 16, count 2 2006.238.08:12:19.74#ibcon#about to read 4, iclass 16, count 2 2006.238.08:12:19.74#ibcon#read 4, iclass 16, count 2 2006.238.08:12:19.74#ibcon#about to read 5, iclass 16, count 2 2006.238.08:12:19.74#ibcon#read 5, iclass 16, count 2 2006.238.08:12:19.74#ibcon#about to read 6, iclass 16, count 2 2006.238.08:12:19.74#ibcon#read 6, iclass 16, count 2 2006.238.08:12:19.74#ibcon#end of sib2, iclass 16, count 2 2006.238.08:12:19.74#ibcon#*mode == 0, iclass 16, count 2 2006.238.08:12:19.74#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.238.08:12:19.74#ibcon#[25=AT06-07\r\n] 2006.238.08:12:19.74#ibcon#*before write, iclass 16, count 2 2006.238.08:12:19.74#ibcon#enter sib2, iclass 16, count 2 2006.238.08:12:19.74#ibcon#flushed, iclass 16, count 2 2006.238.08:12:19.74#ibcon#about to write, iclass 16, count 2 2006.238.08:12:19.74#ibcon#wrote, iclass 16, count 2 2006.238.08:12:19.74#ibcon#about to read 3, iclass 16, count 2 2006.238.08:12:19.77#ibcon#read 3, iclass 16, count 2 2006.238.08:12:19.77#ibcon#about to read 4, iclass 16, count 2 2006.238.08:12:19.77#ibcon#read 4, iclass 16, count 2 2006.238.08:12:19.77#ibcon#about to read 5, iclass 16, count 2 2006.238.08:12:19.77#ibcon#read 5, iclass 16, count 2 2006.238.08:12:19.77#ibcon#about to read 6, iclass 16, count 2 2006.238.08:12:19.77#ibcon#read 6, iclass 16, count 2 2006.238.08:12:19.77#ibcon#end of sib2, iclass 16, count 2 2006.238.08:12:19.77#ibcon#*after write, iclass 16, count 2 2006.238.08:12:19.77#ibcon#*before return 0, iclass 16, count 2 2006.238.08:12:19.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:12:19.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:12:19.77#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.238.08:12:19.77#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:19.77#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:12:19.89#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:12:19.89#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:12:19.89#ibcon#enter wrdev, iclass 16, count 0 2006.238.08:12:19.89#ibcon#first serial, iclass 16, count 0 2006.238.08:12:19.89#ibcon#enter sib2, iclass 16, count 0 2006.238.08:12:19.89#ibcon#flushed, iclass 16, count 0 2006.238.08:12:19.89#ibcon#about to write, iclass 16, count 0 2006.238.08:12:19.89#ibcon#wrote, iclass 16, count 0 2006.238.08:12:19.89#ibcon#about to read 3, iclass 16, count 0 2006.238.08:12:19.91#ibcon#read 3, iclass 16, count 0 2006.238.08:12:19.91#ibcon#about to read 4, iclass 16, count 0 2006.238.08:12:19.91#ibcon#read 4, iclass 16, count 0 2006.238.08:12:19.91#ibcon#about to read 5, iclass 16, count 0 2006.238.08:12:19.91#ibcon#read 5, iclass 16, count 0 2006.238.08:12:19.91#ibcon#about to read 6, iclass 16, count 0 2006.238.08:12:19.91#ibcon#read 6, iclass 16, count 0 2006.238.08:12:19.91#ibcon#end of sib2, iclass 16, count 0 2006.238.08:12:19.91#ibcon#*mode == 0, iclass 16, count 0 2006.238.08:12:19.91#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.08:12:19.91#ibcon#[25=USB\r\n] 2006.238.08:12:19.91#ibcon#*before write, iclass 16, count 0 2006.238.08:12:19.91#ibcon#enter sib2, iclass 16, count 0 2006.238.08:12:19.91#ibcon#flushed, iclass 16, count 0 2006.238.08:12:19.91#ibcon#about to write, iclass 16, count 0 2006.238.08:12:19.91#ibcon#wrote, iclass 16, count 0 2006.238.08:12:19.91#ibcon#about to read 3, iclass 16, count 0 2006.238.08:12:19.94#ibcon#read 3, iclass 16, count 0 2006.238.08:12:19.94#ibcon#about to read 4, iclass 16, count 0 2006.238.08:12:19.94#ibcon#read 4, iclass 16, count 0 2006.238.08:12:19.94#ibcon#about to read 5, iclass 16, count 0 2006.238.08:12:19.94#ibcon#read 5, iclass 16, count 0 2006.238.08:12:19.94#ibcon#about to read 6, iclass 16, count 0 2006.238.08:12:19.94#ibcon#read 6, iclass 16, count 0 2006.238.08:12:19.94#ibcon#end of sib2, iclass 16, count 0 2006.238.08:12:19.94#ibcon#*after write, iclass 16, count 0 2006.238.08:12:19.94#ibcon#*before return 0, iclass 16, count 0 2006.238.08:12:19.94#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:12:19.94#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:12:19.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.08:12:19.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.08:12:19.94$vc4f8/valo=7,832.99 2006.238.08:12:19.94#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.08:12:19.94#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.08:12:19.94#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:19.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:12:19.94#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:12:19.94#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:12:19.94#ibcon#enter wrdev, iclass 18, count 0 2006.238.08:12:19.94#ibcon#first serial, iclass 18, count 0 2006.238.08:12:19.94#ibcon#enter sib2, iclass 18, count 0 2006.238.08:12:19.94#ibcon#flushed, iclass 18, count 0 2006.238.08:12:19.94#ibcon#about to write, iclass 18, count 0 2006.238.08:12:19.94#ibcon#wrote, iclass 18, count 0 2006.238.08:12:19.94#ibcon#about to read 3, iclass 18, count 0 2006.238.08:12:19.96#ibcon#read 3, iclass 18, count 0 2006.238.08:12:19.96#ibcon#about to read 4, iclass 18, count 0 2006.238.08:12:19.96#ibcon#read 4, iclass 18, count 0 2006.238.08:12:19.96#ibcon#about to read 5, iclass 18, count 0 2006.238.08:12:19.96#ibcon#read 5, iclass 18, count 0 2006.238.08:12:19.96#ibcon#about to read 6, iclass 18, count 0 2006.238.08:12:19.96#ibcon#read 6, iclass 18, count 0 2006.238.08:12:19.96#ibcon#end of sib2, iclass 18, count 0 2006.238.08:12:19.96#ibcon#*mode == 0, iclass 18, count 0 2006.238.08:12:19.96#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.08:12:19.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:12:19.96#ibcon#*before write, iclass 18, count 0 2006.238.08:12:19.96#ibcon#enter sib2, iclass 18, count 0 2006.238.08:12:19.96#ibcon#flushed, iclass 18, count 0 2006.238.08:12:19.96#ibcon#about to write, iclass 18, count 0 2006.238.08:12:19.96#ibcon#wrote, iclass 18, count 0 2006.238.08:12:19.96#ibcon#about to read 3, iclass 18, count 0 2006.238.08:12:20.00#ibcon#read 3, iclass 18, count 0 2006.238.08:12:20.00#ibcon#about to read 4, iclass 18, count 0 2006.238.08:12:20.00#ibcon#read 4, iclass 18, count 0 2006.238.08:12:20.00#ibcon#about to read 5, iclass 18, count 0 2006.238.08:12:20.00#ibcon#read 5, iclass 18, count 0 2006.238.08:12:20.00#ibcon#about to read 6, iclass 18, count 0 2006.238.08:12:20.00#ibcon#read 6, iclass 18, count 0 2006.238.08:12:20.00#ibcon#end of sib2, iclass 18, count 0 2006.238.08:12:20.00#ibcon#*after write, iclass 18, count 0 2006.238.08:12:20.00#ibcon#*before return 0, iclass 18, count 0 2006.238.08:12:20.00#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:12:20.00#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:12:20.00#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.08:12:20.00#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.08:12:20.00$vc4f8/va=7,7 2006.238.08:12:20.00#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.238.08:12:20.00#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.238.08:12:20.00#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:20.00#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:12:20.06#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:12:20.06#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:12:20.06#ibcon#enter wrdev, iclass 20, count 2 2006.238.08:12:20.06#ibcon#first serial, iclass 20, count 2 2006.238.08:12:20.06#ibcon#enter sib2, iclass 20, count 2 2006.238.08:12:20.06#ibcon#flushed, iclass 20, count 2 2006.238.08:12:20.06#ibcon#about to write, iclass 20, count 2 2006.238.08:12:20.06#ibcon#wrote, iclass 20, count 2 2006.238.08:12:20.06#ibcon#about to read 3, iclass 20, count 2 2006.238.08:12:20.08#ibcon#read 3, iclass 20, count 2 2006.238.08:12:20.08#ibcon#about to read 4, iclass 20, count 2 2006.238.08:12:20.08#ibcon#read 4, iclass 20, count 2 2006.238.08:12:20.08#ibcon#about to read 5, iclass 20, count 2 2006.238.08:12:20.08#ibcon#read 5, iclass 20, count 2 2006.238.08:12:20.08#ibcon#about to read 6, iclass 20, count 2 2006.238.08:12:20.08#ibcon#read 6, iclass 20, count 2 2006.238.08:12:20.08#ibcon#end of sib2, iclass 20, count 2 2006.238.08:12:20.08#ibcon#*mode == 0, iclass 20, count 2 2006.238.08:12:20.08#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.238.08:12:20.08#ibcon#[25=AT07-07\r\n] 2006.238.08:12:20.08#ibcon#*before write, iclass 20, count 2 2006.238.08:12:20.08#ibcon#enter sib2, iclass 20, count 2 2006.238.08:12:20.08#ibcon#flushed, iclass 20, count 2 2006.238.08:12:20.08#ibcon#about to write, iclass 20, count 2 2006.238.08:12:20.08#ibcon#wrote, iclass 20, count 2 2006.238.08:12:20.08#ibcon#about to read 3, iclass 20, count 2 2006.238.08:12:20.11#ibcon#read 3, iclass 20, count 2 2006.238.08:12:20.11#ibcon#about to read 4, iclass 20, count 2 2006.238.08:12:20.11#ibcon#read 4, iclass 20, count 2 2006.238.08:12:20.11#ibcon#about to read 5, iclass 20, count 2 2006.238.08:12:20.11#ibcon#read 5, iclass 20, count 2 2006.238.08:12:20.11#ibcon#about to read 6, iclass 20, count 2 2006.238.08:12:20.11#ibcon#read 6, iclass 20, count 2 2006.238.08:12:20.11#ibcon#end of sib2, iclass 20, count 2 2006.238.08:12:20.11#ibcon#*after write, iclass 20, count 2 2006.238.08:12:20.11#ibcon#*before return 0, iclass 20, count 2 2006.238.08:12:20.11#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:12:20.11#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:12:20.11#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.238.08:12:20.11#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:20.11#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:12:20.23#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:12:20.23#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:12:20.23#ibcon#enter wrdev, iclass 20, count 0 2006.238.08:12:20.23#ibcon#first serial, iclass 20, count 0 2006.238.08:12:20.23#ibcon#enter sib2, iclass 20, count 0 2006.238.08:12:20.23#ibcon#flushed, iclass 20, count 0 2006.238.08:12:20.23#ibcon#about to write, iclass 20, count 0 2006.238.08:12:20.23#ibcon#wrote, iclass 20, count 0 2006.238.08:12:20.23#ibcon#about to read 3, iclass 20, count 0 2006.238.08:12:20.25#ibcon#read 3, iclass 20, count 0 2006.238.08:12:20.25#ibcon#about to read 4, iclass 20, count 0 2006.238.08:12:20.25#ibcon#read 4, iclass 20, count 0 2006.238.08:12:20.25#ibcon#about to read 5, iclass 20, count 0 2006.238.08:12:20.25#ibcon#read 5, iclass 20, count 0 2006.238.08:12:20.25#ibcon#about to read 6, iclass 20, count 0 2006.238.08:12:20.25#ibcon#read 6, iclass 20, count 0 2006.238.08:12:20.25#ibcon#end of sib2, iclass 20, count 0 2006.238.08:12:20.25#ibcon#*mode == 0, iclass 20, count 0 2006.238.08:12:20.25#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.08:12:20.25#ibcon#[25=USB\r\n] 2006.238.08:12:20.25#ibcon#*before write, iclass 20, count 0 2006.238.08:12:20.25#ibcon#enter sib2, iclass 20, count 0 2006.238.08:12:20.25#ibcon#flushed, iclass 20, count 0 2006.238.08:12:20.25#ibcon#about to write, iclass 20, count 0 2006.238.08:12:20.25#ibcon#wrote, iclass 20, count 0 2006.238.08:12:20.25#ibcon#about to read 3, iclass 20, count 0 2006.238.08:12:20.28#ibcon#read 3, iclass 20, count 0 2006.238.08:12:20.28#ibcon#about to read 4, iclass 20, count 0 2006.238.08:12:20.28#ibcon#read 4, iclass 20, count 0 2006.238.08:12:20.28#ibcon#about to read 5, iclass 20, count 0 2006.238.08:12:20.28#ibcon#read 5, iclass 20, count 0 2006.238.08:12:20.28#ibcon#about to read 6, iclass 20, count 0 2006.238.08:12:20.28#ibcon#read 6, iclass 20, count 0 2006.238.08:12:20.28#ibcon#end of sib2, iclass 20, count 0 2006.238.08:12:20.28#ibcon#*after write, iclass 20, count 0 2006.238.08:12:20.28#ibcon#*before return 0, iclass 20, count 0 2006.238.08:12:20.28#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:12:20.28#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:12:20.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.08:12:20.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.08:12:20.28$vc4f8/valo=8,852.99 2006.238.08:12:20.28#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.08:12:20.28#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.08:12:20.28#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:20.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:12:20.28#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:12:20.28#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:12:20.28#ibcon#enter wrdev, iclass 22, count 0 2006.238.08:12:20.28#ibcon#first serial, iclass 22, count 0 2006.238.08:12:20.28#ibcon#enter sib2, iclass 22, count 0 2006.238.08:12:20.28#ibcon#flushed, iclass 22, count 0 2006.238.08:12:20.28#ibcon#about to write, iclass 22, count 0 2006.238.08:12:20.28#ibcon#wrote, iclass 22, count 0 2006.238.08:12:20.28#ibcon#about to read 3, iclass 22, count 0 2006.238.08:12:20.30#ibcon#read 3, iclass 22, count 0 2006.238.08:12:20.30#ibcon#about to read 4, iclass 22, count 0 2006.238.08:12:20.30#ibcon#read 4, iclass 22, count 0 2006.238.08:12:20.30#ibcon#about to read 5, iclass 22, count 0 2006.238.08:12:20.30#ibcon#read 5, iclass 22, count 0 2006.238.08:12:20.30#ibcon#about to read 6, iclass 22, count 0 2006.238.08:12:20.30#ibcon#read 6, iclass 22, count 0 2006.238.08:12:20.30#ibcon#end of sib2, iclass 22, count 0 2006.238.08:12:20.30#ibcon#*mode == 0, iclass 22, count 0 2006.238.08:12:20.30#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.08:12:20.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:12:20.30#ibcon#*before write, iclass 22, count 0 2006.238.08:12:20.30#ibcon#enter sib2, iclass 22, count 0 2006.238.08:12:20.30#ibcon#flushed, iclass 22, count 0 2006.238.08:12:20.30#ibcon#about to write, iclass 22, count 0 2006.238.08:12:20.30#ibcon#wrote, iclass 22, count 0 2006.238.08:12:20.30#ibcon#about to read 3, iclass 22, count 0 2006.238.08:12:20.34#ibcon#read 3, iclass 22, count 0 2006.238.08:12:20.34#ibcon#about to read 4, iclass 22, count 0 2006.238.08:12:20.34#ibcon#read 4, iclass 22, count 0 2006.238.08:12:20.34#ibcon#about to read 5, iclass 22, count 0 2006.238.08:12:20.34#ibcon#read 5, iclass 22, count 0 2006.238.08:12:20.34#ibcon#about to read 6, iclass 22, count 0 2006.238.08:12:20.34#ibcon#read 6, iclass 22, count 0 2006.238.08:12:20.34#ibcon#end of sib2, iclass 22, count 0 2006.238.08:12:20.34#ibcon#*after write, iclass 22, count 0 2006.238.08:12:20.34#ibcon#*before return 0, iclass 22, count 0 2006.238.08:12:20.34#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:12:20.34#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:12:20.34#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.08:12:20.34#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.08:12:20.34$vc4f8/va=8,7 2006.238.08:12:20.34#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.238.08:12:20.34#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.238.08:12:20.34#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:20.34#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:12:20.40#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:12:20.40#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:12:20.40#ibcon#enter wrdev, iclass 24, count 2 2006.238.08:12:20.40#ibcon#first serial, iclass 24, count 2 2006.238.08:12:20.40#ibcon#enter sib2, iclass 24, count 2 2006.238.08:12:20.40#ibcon#flushed, iclass 24, count 2 2006.238.08:12:20.40#ibcon#about to write, iclass 24, count 2 2006.238.08:12:20.40#ibcon#wrote, iclass 24, count 2 2006.238.08:12:20.40#ibcon#about to read 3, iclass 24, count 2 2006.238.08:12:20.42#ibcon#read 3, iclass 24, count 2 2006.238.08:12:20.42#ibcon#about to read 4, iclass 24, count 2 2006.238.08:12:20.42#ibcon#read 4, iclass 24, count 2 2006.238.08:12:20.42#ibcon#about to read 5, iclass 24, count 2 2006.238.08:12:20.42#ibcon#read 5, iclass 24, count 2 2006.238.08:12:20.42#ibcon#about to read 6, iclass 24, count 2 2006.238.08:12:20.42#ibcon#read 6, iclass 24, count 2 2006.238.08:12:20.42#ibcon#end of sib2, iclass 24, count 2 2006.238.08:12:20.42#ibcon#*mode == 0, iclass 24, count 2 2006.238.08:12:20.42#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.238.08:12:20.42#ibcon#[25=AT08-07\r\n] 2006.238.08:12:20.42#ibcon#*before write, iclass 24, count 2 2006.238.08:12:20.42#ibcon#enter sib2, iclass 24, count 2 2006.238.08:12:20.42#ibcon#flushed, iclass 24, count 2 2006.238.08:12:20.42#ibcon#about to write, iclass 24, count 2 2006.238.08:12:20.42#ibcon#wrote, iclass 24, count 2 2006.238.08:12:20.42#ibcon#about to read 3, iclass 24, count 2 2006.238.08:12:20.45#ibcon#read 3, iclass 24, count 2 2006.238.08:12:20.45#ibcon#about to read 4, iclass 24, count 2 2006.238.08:12:20.45#ibcon#read 4, iclass 24, count 2 2006.238.08:12:20.45#ibcon#about to read 5, iclass 24, count 2 2006.238.08:12:20.45#ibcon#read 5, iclass 24, count 2 2006.238.08:12:20.45#ibcon#about to read 6, iclass 24, count 2 2006.238.08:12:20.45#ibcon#read 6, iclass 24, count 2 2006.238.08:12:20.45#ibcon#end of sib2, iclass 24, count 2 2006.238.08:12:20.45#ibcon#*after write, iclass 24, count 2 2006.238.08:12:20.45#ibcon#*before return 0, iclass 24, count 2 2006.238.08:12:20.45#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:12:20.45#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:12:20.45#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.238.08:12:20.45#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:20.45#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:12:20.57#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:12:20.57#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:12:20.57#ibcon#enter wrdev, iclass 24, count 0 2006.238.08:12:20.57#ibcon#first serial, iclass 24, count 0 2006.238.08:12:20.57#ibcon#enter sib2, iclass 24, count 0 2006.238.08:12:20.57#ibcon#flushed, iclass 24, count 0 2006.238.08:12:20.57#ibcon#about to write, iclass 24, count 0 2006.238.08:12:20.57#ibcon#wrote, iclass 24, count 0 2006.238.08:12:20.57#ibcon#about to read 3, iclass 24, count 0 2006.238.08:12:20.59#ibcon#read 3, iclass 24, count 0 2006.238.08:12:20.59#ibcon#about to read 4, iclass 24, count 0 2006.238.08:12:20.59#ibcon#read 4, iclass 24, count 0 2006.238.08:12:20.59#ibcon#about to read 5, iclass 24, count 0 2006.238.08:12:20.59#ibcon#read 5, iclass 24, count 0 2006.238.08:12:20.59#ibcon#about to read 6, iclass 24, count 0 2006.238.08:12:20.59#ibcon#read 6, iclass 24, count 0 2006.238.08:12:20.59#ibcon#end of sib2, iclass 24, count 0 2006.238.08:12:20.59#ibcon#*mode == 0, iclass 24, count 0 2006.238.08:12:20.59#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.08:12:20.59#ibcon#[25=USB\r\n] 2006.238.08:12:20.59#ibcon#*before write, iclass 24, count 0 2006.238.08:12:20.59#ibcon#enter sib2, iclass 24, count 0 2006.238.08:12:20.59#ibcon#flushed, iclass 24, count 0 2006.238.08:12:20.59#ibcon#about to write, iclass 24, count 0 2006.238.08:12:20.59#ibcon#wrote, iclass 24, count 0 2006.238.08:12:20.59#ibcon#about to read 3, iclass 24, count 0 2006.238.08:12:20.62#ibcon#read 3, iclass 24, count 0 2006.238.08:12:20.62#ibcon#about to read 4, iclass 24, count 0 2006.238.08:12:20.62#ibcon#read 4, iclass 24, count 0 2006.238.08:12:20.62#ibcon#about to read 5, iclass 24, count 0 2006.238.08:12:20.62#ibcon#read 5, iclass 24, count 0 2006.238.08:12:20.62#ibcon#about to read 6, iclass 24, count 0 2006.238.08:12:20.62#ibcon#read 6, iclass 24, count 0 2006.238.08:12:20.62#ibcon#end of sib2, iclass 24, count 0 2006.238.08:12:20.62#ibcon#*after write, iclass 24, count 0 2006.238.08:12:20.62#ibcon#*before return 0, iclass 24, count 0 2006.238.08:12:20.62#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:12:20.62#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:12:20.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.08:12:20.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.08:12:20.62$vc4f8/vblo=1,632.99 2006.238.08:12:20.62#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.08:12:20.62#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.08:12:20.62#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:20.62#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:12:20.62#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:12:20.62#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:12:20.62#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:12:20.62#ibcon#first serial, iclass 26, count 0 2006.238.08:12:20.62#ibcon#enter sib2, iclass 26, count 0 2006.238.08:12:20.62#ibcon#flushed, iclass 26, count 0 2006.238.08:12:20.62#ibcon#about to write, iclass 26, count 0 2006.238.08:12:20.62#ibcon#wrote, iclass 26, count 0 2006.238.08:12:20.62#ibcon#about to read 3, iclass 26, count 0 2006.238.08:12:20.64#ibcon#read 3, iclass 26, count 0 2006.238.08:12:20.64#ibcon#about to read 4, iclass 26, count 0 2006.238.08:12:20.64#ibcon#read 4, iclass 26, count 0 2006.238.08:12:20.64#ibcon#about to read 5, iclass 26, count 0 2006.238.08:12:20.64#ibcon#read 5, iclass 26, count 0 2006.238.08:12:20.64#ibcon#about to read 6, iclass 26, count 0 2006.238.08:12:20.64#ibcon#read 6, iclass 26, count 0 2006.238.08:12:20.64#ibcon#end of sib2, iclass 26, count 0 2006.238.08:12:20.64#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:12:20.64#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:12:20.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:12:20.64#ibcon#*before write, iclass 26, count 0 2006.238.08:12:20.64#ibcon#enter sib2, iclass 26, count 0 2006.238.08:12:20.64#ibcon#flushed, iclass 26, count 0 2006.238.08:12:20.64#ibcon#about to write, iclass 26, count 0 2006.238.08:12:20.64#ibcon#wrote, iclass 26, count 0 2006.238.08:12:20.64#ibcon#about to read 3, iclass 26, count 0 2006.238.08:12:20.68#ibcon#read 3, iclass 26, count 0 2006.238.08:12:20.68#ibcon#about to read 4, iclass 26, count 0 2006.238.08:12:20.68#ibcon#read 4, iclass 26, count 0 2006.238.08:12:20.68#ibcon#about to read 5, iclass 26, count 0 2006.238.08:12:20.68#ibcon#read 5, iclass 26, count 0 2006.238.08:12:20.68#ibcon#about to read 6, iclass 26, count 0 2006.238.08:12:20.68#ibcon#read 6, iclass 26, count 0 2006.238.08:12:20.68#ibcon#end of sib2, iclass 26, count 0 2006.238.08:12:20.68#ibcon#*after write, iclass 26, count 0 2006.238.08:12:20.68#ibcon#*before return 0, iclass 26, count 0 2006.238.08:12:20.68#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:12:20.68#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:12:20.68#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:12:20.68#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:12:20.68$vc4f8/vb=1,4 2006.238.08:12:20.68#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.08:12:20.68#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.08:12:20.68#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:20.68#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:12:20.68#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:12:20.68#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:12:20.68#ibcon#enter wrdev, iclass 28, count 2 2006.238.08:12:20.68#ibcon#first serial, iclass 28, count 2 2006.238.08:12:20.68#ibcon#enter sib2, iclass 28, count 2 2006.238.08:12:20.68#ibcon#flushed, iclass 28, count 2 2006.238.08:12:20.68#ibcon#about to write, iclass 28, count 2 2006.238.08:12:20.68#ibcon#wrote, iclass 28, count 2 2006.238.08:12:20.68#ibcon#about to read 3, iclass 28, count 2 2006.238.08:12:20.70#ibcon#read 3, iclass 28, count 2 2006.238.08:12:20.70#ibcon#about to read 4, iclass 28, count 2 2006.238.08:12:20.70#ibcon#read 4, iclass 28, count 2 2006.238.08:12:20.70#ibcon#about to read 5, iclass 28, count 2 2006.238.08:12:20.70#ibcon#read 5, iclass 28, count 2 2006.238.08:12:20.70#ibcon#about to read 6, iclass 28, count 2 2006.238.08:12:20.70#ibcon#read 6, iclass 28, count 2 2006.238.08:12:20.70#ibcon#end of sib2, iclass 28, count 2 2006.238.08:12:20.70#ibcon#*mode == 0, iclass 28, count 2 2006.238.08:12:20.70#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.08:12:20.70#ibcon#[27=AT01-04\r\n] 2006.238.08:12:20.70#ibcon#*before write, iclass 28, count 2 2006.238.08:12:20.70#ibcon#enter sib2, iclass 28, count 2 2006.238.08:12:20.70#ibcon#flushed, iclass 28, count 2 2006.238.08:12:20.70#ibcon#about to write, iclass 28, count 2 2006.238.08:12:20.70#ibcon#wrote, iclass 28, count 2 2006.238.08:12:20.70#ibcon#about to read 3, iclass 28, count 2 2006.238.08:12:20.73#ibcon#read 3, iclass 28, count 2 2006.238.08:12:20.73#ibcon#about to read 4, iclass 28, count 2 2006.238.08:12:20.73#ibcon#read 4, iclass 28, count 2 2006.238.08:12:20.73#ibcon#about to read 5, iclass 28, count 2 2006.238.08:12:20.73#ibcon#read 5, iclass 28, count 2 2006.238.08:12:20.73#ibcon#about to read 6, iclass 28, count 2 2006.238.08:12:20.73#ibcon#read 6, iclass 28, count 2 2006.238.08:12:20.73#ibcon#end of sib2, iclass 28, count 2 2006.238.08:12:20.73#ibcon#*after write, iclass 28, count 2 2006.238.08:12:20.73#ibcon#*before return 0, iclass 28, count 2 2006.238.08:12:20.73#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:12:20.73#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:12:20.73#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.08:12:20.73#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:20.73#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:12:20.85#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:12:20.85#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:12:20.85#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:12:20.85#ibcon#first serial, iclass 28, count 0 2006.238.08:12:20.85#ibcon#enter sib2, iclass 28, count 0 2006.238.08:12:20.85#ibcon#flushed, iclass 28, count 0 2006.238.08:12:20.85#ibcon#about to write, iclass 28, count 0 2006.238.08:12:20.85#ibcon#wrote, iclass 28, count 0 2006.238.08:12:20.85#ibcon#about to read 3, iclass 28, count 0 2006.238.08:12:20.87#ibcon#read 3, iclass 28, count 0 2006.238.08:12:20.87#ibcon#about to read 4, iclass 28, count 0 2006.238.08:12:20.87#ibcon#read 4, iclass 28, count 0 2006.238.08:12:20.87#ibcon#about to read 5, iclass 28, count 0 2006.238.08:12:20.87#ibcon#read 5, iclass 28, count 0 2006.238.08:12:20.87#ibcon#about to read 6, iclass 28, count 0 2006.238.08:12:20.87#ibcon#read 6, iclass 28, count 0 2006.238.08:12:20.87#ibcon#end of sib2, iclass 28, count 0 2006.238.08:12:20.87#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:12:20.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:12:20.87#ibcon#[27=USB\r\n] 2006.238.08:12:20.87#ibcon#*before write, iclass 28, count 0 2006.238.08:12:20.87#ibcon#enter sib2, iclass 28, count 0 2006.238.08:12:20.87#ibcon#flushed, iclass 28, count 0 2006.238.08:12:20.87#ibcon#about to write, iclass 28, count 0 2006.238.08:12:20.87#ibcon#wrote, iclass 28, count 0 2006.238.08:12:20.87#ibcon#about to read 3, iclass 28, count 0 2006.238.08:12:20.90#ibcon#read 3, iclass 28, count 0 2006.238.08:12:20.90#ibcon#about to read 4, iclass 28, count 0 2006.238.08:12:20.90#ibcon#read 4, iclass 28, count 0 2006.238.08:12:20.90#ibcon#about to read 5, iclass 28, count 0 2006.238.08:12:20.90#ibcon#read 5, iclass 28, count 0 2006.238.08:12:20.90#ibcon#about to read 6, iclass 28, count 0 2006.238.08:12:20.90#ibcon#read 6, iclass 28, count 0 2006.238.08:12:20.90#ibcon#end of sib2, iclass 28, count 0 2006.238.08:12:20.90#ibcon#*after write, iclass 28, count 0 2006.238.08:12:20.90#ibcon#*before return 0, iclass 28, count 0 2006.238.08:12:20.90#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:12:20.90#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:12:20.90#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:12:20.90#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:12:20.90$vc4f8/vblo=2,640.99 2006.238.08:12:20.90#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.08:12:20.90#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.08:12:20.90#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:20.90#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:12:20.90#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:12:20.90#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:12:20.90#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:12:20.90#ibcon#first serial, iclass 30, count 0 2006.238.08:12:20.90#ibcon#enter sib2, iclass 30, count 0 2006.238.08:12:20.90#ibcon#flushed, iclass 30, count 0 2006.238.08:12:20.90#ibcon#about to write, iclass 30, count 0 2006.238.08:12:20.90#ibcon#wrote, iclass 30, count 0 2006.238.08:12:20.90#ibcon#about to read 3, iclass 30, count 0 2006.238.08:12:20.92#ibcon#read 3, iclass 30, count 0 2006.238.08:12:20.92#ibcon#about to read 4, iclass 30, count 0 2006.238.08:12:20.92#ibcon#read 4, iclass 30, count 0 2006.238.08:12:20.92#ibcon#about to read 5, iclass 30, count 0 2006.238.08:12:20.92#ibcon#read 5, iclass 30, count 0 2006.238.08:12:20.92#ibcon#about to read 6, iclass 30, count 0 2006.238.08:12:20.92#ibcon#read 6, iclass 30, count 0 2006.238.08:12:20.92#ibcon#end of sib2, iclass 30, count 0 2006.238.08:12:20.92#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:12:20.92#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:12:20.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:12:20.92#ibcon#*before write, iclass 30, count 0 2006.238.08:12:20.92#ibcon#enter sib2, iclass 30, count 0 2006.238.08:12:20.92#ibcon#flushed, iclass 30, count 0 2006.238.08:12:20.92#ibcon#about to write, iclass 30, count 0 2006.238.08:12:20.92#ibcon#wrote, iclass 30, count 0 2006.238.08:12:20.92#ibcon#about to read 3, iclass 30, count 0 2006.238.08:12:20.96#ibcon#read 3, iclass 30, count 0 2006.238.08:12:20.96#ibcon#about to read 4, iclass 30, count 0 2006.238.08:12:20.96#ibcon#read 4, iclass 30, count 0 2006.238.08:12:20.96#ibcon#about to read 5, iclass 30, count 0 2006.238.08:12:20.96#ibcon#read 5, iclass 30, count 0 2006.238.08:12:20.96#ibcon#about to read 6, iclass 30, count 0 2006.238.08:12:20.96#ibcon#read 6, iclass 30, count 0 2006.238.08:12:20.96#ibcon#end of sib2, iclass 30, count 0 2006.238.08:12:20.96#ibcon#*after write, iclass 30, count 0 2006.238.08:12:20.96#ibcon#*before return 0, iclass 30, count 0 2006.238.08:12:20.96#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:12:20.96#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:12:20.96#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:12:20.96#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:12:20.96$vc4f8/vb=2,4 2006.238.08:12:20.96#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.238.08:12:20.96#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.238.08:12:20.96#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:20.96#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:12:21.02#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:12:21.02#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:12:21.02#ibcon#enter wrdev, iclass 32, count 2 2006.238.08:12:21.02#ibcon#first serial, iclass 32, count 2 2006.238.08:12:21.02#ibcon#enter sib2, iclass 32, count 2 2006.238.08:12:21.02#ibcon#flushed, iclass 32, count 2 2006.238.08:12:21.02#ibcon#about to write, iclass 32, count 2 2006.238.08:12:21.02#ibcon#wrote, iclass 32, count 2 2006.238.08:12:21.02#ibcon#about to read 3, iclass 32, count 2 2006.238.08:12:21.04#ibcon#read 3, iclass 32, count 2 2006.238.08:12:21.04#ibcon#about to read 4, iclass 32, count 2 2006.238.08:12:21.04#ibcon#read 4, iclass 32, count 2 2006.238.08:12:21.04#ibcon#about to read 5, iclass 32, count 2 2006.238.08:12:21.04#ibcon#read 5, iclass 32, count 2 2006.238.08:12:21.04#ibcon#about to read 6, iclass 32, count 2 2006.238.08:12:21.04#ibcon#read 6, iclass 32, count 2 2006.238.08:12:21.04#ibcon#end of sib2, iclass 32, count 2 2006.238.08:12:21.04#ibcon#*mode == 0, iclass 32, count 2 2006.238.08:12:21.04#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.238.08:12:21.04#ibcon#[27=AT02-04\r\n] 2006.238.08:12:21.04#ibcon#*before write, iclass 32, count 2 2006.238.08:12:21.04#ibcon#enter sib2, iclass 32, count 2 2006.238.08:12:21.04#ibcon#flushed, iclass 32, count 2 2006.238.08:12:21.04#ibcon#about to write, iclass 32, count 2 2006.238.08:12:21.04#ibcon#wrote, iclass 32, count 2 2006.238.08:12:21.04#ibcon#about to read 3, iclass 32, count 2 2006.238.08:12:21.07#ibcon#read 3, iclass 32, count 2 2006.238.08:12:21.07#ibcon#about to read 4, iclass 32, count 2 2006.238.08:12:21.07#ibcon#read 4, iclass 32, count 2 2006.238.08:12:21.07#ibcon#about to read 5, iclass 32, count 2 2006.238.08:12:21.07#ibcon#read 5, iclass 32, count 2 2006.238.08:12:21.07#ibcon#about to read 6, iclass 32, count 2 2006.238.08:12:21.07#ibcon#read 6, iclass 32, count 2 2006.238.08:12:21.07#ibcon#end of sib2, iclass 32, count 2 2006.238.08:12:21.07#ibcon#*after write, iclass 32, count 2 2006.238.08:12:21.07#ibcon#*before return 0, iclass 32, count 2 2006.238.08:12:21.07#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:12:21.07#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:12:21.07#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.238.08:12:21.07#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:21.07#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:12:21.19#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:12:21.19#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:12:21.19#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:12:21.19#ibcon#first serial, iclass 32, count 0 2006.238.08:12:21.19#ibcon#enter sib2, iclass 32, count 0 2006.238.08:12:21.19#ibcon#flushed, iclass 32, count 0 2006.238.08:12:21.19#ibcon#about to write, iclass 32, count 0 2006.238.08:12:21.19#ibcon#wrote, iclass 32, count 0 2006.238.08:12:21.19#ibcon#about to read 3, iclass 32, count 0 2006.238.08:12:21.21#ibcon#read 3, iclass 32, count 0 2006.238.08:12:21.21#ibcon#about to read 4, iclass 32, count 0 2006.238.08:12:21.21#ibcon#read 4, iclass 32, count 0 2006.238.08:12:21.21#ibcon#about to read 5, iclass 32, count 0 2006.238.08:12:21.21#ibcon#read 5, iclass 32, count 0 2006.238.08:12:21.21#ibcon#about to read 6, iclass 32, count 0 2006.238.08:12:21.21#ibcon#read 6, iclass 32, count 0 2006.238.08:12:21.21#ibcon#end of sib2, iclass 32, count 0 2006.238.08:12:21.21#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:12:21.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:12:21.21#ibcon#[27=USB\r\n] 2006.238.08:12:21.21#ibcon#*before write, iclass 32, count 0 2006.238.08:12:21.21#ibcon#enter sib2, iclass 32, count 0 2006.238.08:12:21.21#ibcon#flushed, iclass 32, count 0 2006.238.08:12:21.21#ibcon#about to write, iclass 32, count 0 2006.238.08:12:21.21#ibcon#wrote, iclass 32, count 0 2006.238.08:12:21.21#ibcon#about to read 3, iclass 32, count 0 2006.238.08:12:21.24#ibcon#read 3, iclass 32, count 0 2006.238.08:12:21.24#ibcon#about to read 4, iclass 32, count 0 2006.238.08:12:21.24#ibcon#read 4, iclass 32, count 0 2006.238.08:12:21.24#ibcon#about to read 5, iclass 32, count 0 2006.238.08:12:21.24#ibcon#read 5, iclass 32, count 0 2006.238.08:12:21.24#ibcon#about to read 6, iclass 32, count 0 2006.238.08:12:21.24#ibcon#read 6, iclass 32, count 0 2006.238.08:12:21.24#ibcon#end of sib2, iclass 32, count 0 2006.238.08:12:21.24#ibcon#*after write, iclass 32, count 0 2006.238.08:12:21.24#ibcon#*before return 0, iclass 32, count 0 2006.238.08:12:21.24#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:12:21.24#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:12:21.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:12:21.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:12:21.24$vc4f8/vblo=3,656.99 2006.238.08:12:21.24#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.238.08:12:21.24#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.238.08:12:21.24#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:21.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:12:21.24#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:12:21.24#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:12:21.24#ibcon#enter wrdev, iclass 34, count 0 2006.238.08:12:21.24#ibcon#first serial, iclass 34, count 0 2006.238.08:12:21.24#ibcon#enter sib2, iclass 34, count 0 2006.238.08:12:21.24#ibcon#flushed, iclass 34, count 0 2006.238.08:12:21.24#ibcon#about to write, iclass 34, count 0 2006.238.08:12:21.24#ibcon#wrote, iclass 34, count 0 2006.238.08:12:21.24#ibcon#about to read 3, iclass 34, count 0 2006.238.08:12:21.26#ibcon#read 3, iclass 34, count 0 2006.238.08:12:21.26#ibcon#about to read 4, iclass 34, count 0 2006.238.08:12:21.26#ibcon#read 4, iclass 34, count 0 2006.238.08:12:21.26#ibcon#about to read 5, iclass 34, count 0 2006.238.08:12:21.26#ibcon#read 5, iclass 34, count 0 2006.238.08:12:21.26#ibcon#about to read 6, iclass 34, count 0 2006.238.08:12:21.26#ibcon#read 6, iclass 34, count 0 2006.238.08:12:21.26#ibcon#end of sib2, iclass 34, count 0 2006.238.08:12:21.26#ibcon#*mode == 0, iclass 34, count 0 2006.238.08:12:21.26#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.08:12:21.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:12:21.26#ibcon#*before write, iclass 34, count 0 2006.238.08:12:21.26#ibcon#enter sib2, iclass 34, count 0 2006.238.08:12:21.26#ibcon#flushed, iclass 34, count 0 2006.238.08:12:21.26#ibcon#about to write, iclass 34, count 0 2006.238.08:12:21.26#ibcon#wrote, iclass 34, count 0 2006.238.08:12:21.26#ibcon#about to read 3, iclass 34, count 0 2006.238.08:12:21.30#ibcon#read 3, iclass 34, count 0 2006.238.08:12:21.30#ibcon#about to read 4, iclass 34, count 0 2006.238.08:12:21.30#ibcon#read 4, iclass 34, count 0 2006.238.08:12:21.30#ibcon#about to read 5, iclass 34, count 0 2006.238.08:12:21.30#ibcon#read 5, iclass 34, count 0 2006.238.08:12:21.30#ibcon#about to read 6, iclass 34, count 0 2006.238.08:12:21.30#ibcon#read 6, iclass 34, count 0 2006.238.08:12:21.30#ibcon#end of sib2, iclass 34, count 0 2006.238.08:12:21.30#ibcon#*after write, iclass 34, count 0 2006.238.08:12:21.30#ibcon#*before return 0, iclass 34, count 0 2006.238.08:12:21.30#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:12:21.30#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:12:21.30#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.08:12:21.30#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.08:12:21.30$vc4f8/vb=3,4 2006.238.08:12:21.30#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.238.08:12:21.30#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.238.08:12:21.30#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:21.30#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:12:21.36#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:12:21.36#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:12:21.36#ibcon#enter wrdev, iclass 36, count 2 2006.238.08:12:21.36#ibcon#first serial, iclass 36, count 2 2006.238.08:12:21.36#ibcon#enter sib2, iclass 36, count 2 2006.238.08:12:21.36#ibcon#flushed, iclass 36, count 2 2006.238.08:12:21.36#ibcon#about to write, iclass 36, count 2 2006.238.08:12:21.36#ibcon#wrote, iclass 36, count 2 2006.238.08:12:21.36#ibcon#about to read 3, iclass 36, count 2 2006.238.08:12:21.38#ibcon#read 3, iclass 36, count 2 2006.238.08:12:21.38#ibcon#about to read 4, iclass 36, count 2 2006.238.08:12:21.38#ibcon#read 4, iclass 36, count 2 2006.238.08:12:21.38#ibcon#about to read 5, iclass 36, count 2 2006.238.08:12:21.38#ibcon#read 5, iclass 36, count 2 2006.238.08:12:21.38#ibcon#about to read 6, iclass 36, count 2 2006.238.08:12:21.38#ibcon#read 6, iclass 36, count 2 2006.238.08:12:21.38#ibcon#end of sib2, iclass 36, count 2 2006.238.08:12:21.38#ibcon#*mode == 0, iclass 36, count 2 2006.238.08:12:21.38#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.238.08:12:21.38#ibcon#[27=AT03-04\r\n] 2006.238.08:12:21.38#ibcon#*before write, iclass 36, count 2 2006.238.08:12:21.38#ibcon#enter sib2, iclass 36, count 2 2006.238.08:12:21.38#ibcon#flushed, iclass 36, count 2 2006.238.08:12:21.38#ibcon#about to write, iclass 36, count 2 2006.238.08:12:21.38#ibcon#wrote, iclass 36, count 2 2006.238.08:12:21.38#ibcon#about to read 3, iclass 36, count 2 2006.238.08:12:21.41#ibcon#read 3, iclass 36, count 2 2006.238.08:12:21.41#ibcon#about to read 4, iclass 36, count 2 2006.238.08:12:21.41#ibcon#read 4, iclass 36, count 2 2006.238.08:12:21.41#ibcon#about to read 5, iclass 36, count 2 2006.238.08:12:21.41#ibcon#read 5, iclass 36, count 2 2006.238.08:12:21.41#ibcon#about to read 6, iclass 36, count 2 2006.238.08:12:21.41#ibcon#read 6, iclass 36, count 2 2006.238.08:12:21.41#ibcon#end of sib2, iclass 36, count 2 2006.238.08:12:21.41#ibcon#*after write, iclass 36, count 2 2006.238.08:12:21.41#ibcon#*before return 0, iclass 36, count 2 2006.238.08:12:21.41#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:12:21.41#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:12:21.41#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.238.08:12:21.41#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:21.41#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:12:21.53#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:12:21.53#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:12:21.53#ibcon#enter wrdev, iclass 36, count 0 2006.238.08:12:21.53#ibcon#first serial, iclass 36, count 0 2006.238.08:12:21.53#ibcon#enter sib2, iclass 36, count 0 2006.238.08:12:21.53#ibcon#flushed, iclass 36, count 0 2006.238.08:12:21.53#ibcon#about to write, iclass 36, count 0 2006.238.08:12:21.53#ibcon#wrote, iclass 36, count 0 2006.238.08:12:21.53#ibcon#about to read 3, iclass 36, count 0 2006.238.08:12:21.55#ibcon#read 3, iclass 36, count 0 2006.238.08:12:21.55#ibcon#about to read 4, iclass 36, count 0 2006.238.08:12:21.55#ibcon#read 4, iclass 36, count 0 2006.238.08:12:21.55#ibcon#about to read 5, iclass 36, count 0 2006.238.08:12:21.55#ibcon#read 5, iclass 36, count 0 2006.238.08:12:21.55#ibcon#about to read 6, iclass 36, count 0 2006.238.08:12:21.55#ibcon#read 6, iclass 36, count 0 2006.238.08:12:21.55#ibcon#end of sib2, iclass 36, count 0 2006.238.08:12:21.55#ibcon#*mode == 0, iclass 36, count 0 2006.238.08:12:21.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.08:12:21.55#ibcon#[27=USB\r\n] 2006.238.08:12:21.55#ibcon#*before write, iclass 36, count 0 2006.238.08:12:21.55#ibcon#enter sib2, iclass 36, count 0 2006.238.08:12:21.55#ibcon#flushed, iclass 36, count 0 2006.238.08:12:21.55#ibcon#about to write, iclass 36, count 0 2006.238.08:12:21.55#ibcon#wrote, iclass 36, count 0 2006.238.08:12:21.55#ibcon#about to read 3, iclass 36, count 0 2006.238.08:12:21.58#ibcon#read 3, iclass 36, count 0 2006.238.08:12:21.58#ibcon#about to read 4, iclass 36, count 0 2006.238.08:12:21.58#ibcon#read 4, iclass 36, count 0 2006.238.08:12:21.58#ibcon#about to read 5, iclass 36, count 0 2006.238.08:12:21.58#ibcon#read 5, iclass 36, count 0 2006.238.08:12:21.58#ibcon#about to read 6, iclass 36, count 0 2006.238.08:12:21.58#ibcon#read 6, iclass 36, count 0 2006.238.08:12:21.58#ibcon#end of sib2, iclass 36, count 0 2006.238.08:12:21.58#ibcon#*after write, iclass 36, count 0 2006.238.08:12:21.58#ibcon#*before return 0, iclass 36, count 0 2006.238.08:12:21.58#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:12:21.58#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:12:21.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.08:12:21.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.08:12:21.58$vc4f8/vblo=4,712.99 2006.238.08:12:21.58#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.238.08:12:21.58#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.238.08:12:21.58#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:21.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:12:21.58#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:12:21.58#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:12:21.58#ibcon#enter wrdev, iclass 38, count 0 2006.238.08:12:21.58#ibcon#first serial, iclass 38, count 0 2006.238.08:12:21.58#ibcon#enter sib2, iclass 38, count 0 2006.238.08:12:21.58#ibcon#flushed, iclass 38, count 0 2006.238.08:12:21.58#ibcon#about to write, iclass 38, count 0 2006.238.08:12:21.58#ibcon#wrote, iclass 38, count 0 2006.238.08:12:21.58#ibcon#about to read 3, iclass 38, count 0 2006.238.08:12:21.60#ibcon#read 3, iclass 38, count 0 2006.238.08:12:21.60#ibcon#about to read 4, iclass 38, count 0 2006.238.08:12:21.60#ibcon#read 4, iclass 38, count 0 2006.238.08:12:21.60#ibcon#about to read 5, iclass 38, count 0 2006.238.08:12:21.60#ibcon#read 5, iclass 38, count 0 2006.238.08:12:21.60#ibcon#about to read 6, iclass 38, count 0 2006.238.08:12:21.60#ibcon#read 6, iclass 38, count 0 2006.238.08:12:21.60#ibcon#end of sib2, iclass 38, count 0 2006.238.08:12:21.60#ibcon#*mode == 0, iclass 38, count 0 2006.238.08:12:21.60#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.08:12:21.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:12:21.60#ibcon#*before write, iclass 38, count 0 2006.238.08:12:21.60#ibcon#enter sib2, iclass 38, count 0 2006.238.08:12:21.60#ibcon#flushed, iclass 38, count 0 2006.238.08:12:21.60#ibcon#about to write, iclass 38, count 0 2006.238.08:12:21.60#ibcon#wrote, iclass 38, count 0 2006.238.08:12:21.60#ibcon#about to read 3, iclass 38, count 0 2006.238.08:12:21.64#ibcon#read 3, iclass 38, count 0 2006.238.08:12:21.64#ibcon#about to read 4, iclass 38, count 0 2006.238.08:12:21.64#ibcon#read 4, iclass 38, count 0 2006.238.08:12:21.64#ibcon#about to read 5, iclass 38, count 0 2006.238.08:12:21.64#ibcon#read 5, iclass 38, count 0 2006.238.08:12:21.64#ibcon#about to read 6, iclass 38, count 0 2006.238.08:12:21.64#ibcon#read 6, iclass 38, count 0 2006.238.08:12:21.64#ibcon#end of sib2, iclass 38, count 0 2006.238.08:12:21.64#ibcon#*after write, iclass 38, count 0 2006.238.08:12:21.64#ibcon#*before return 0, iclass 38, count 0 2006.238.08:12:21.64#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:12:21.64#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:12:21.64#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.08:12:21.64#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.08:12:21.64$vc4f8/vb=4,4 2006.238.08:12:21.64#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.238.08:12:21.64#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.238.08:12:21.64#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:21.64#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:12:21.70#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:12:21.70#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:12:21.70#ibcon#enter wrdev, iclass 40, count 2 2006.238.08:12:21.70#ibcon#first serial, iclass 40, count 2 2006.238.08:12:21.70#ibcon#enter sib2, iclass 40, count 2 2006.238.08:12:21.70#ibcon#flushed, iclass 40, count 2 2006.238.08:12:21.70#ibcon#about to write, iclass 40, count 2 2006.238.08:12:21.70#ibcon#wrote, iclass 40, count 2 2006.238.08:12:21.70#ibcon#about to read 3, iclass 40, count 2 2006.238.08:12:21.72#ibcon#read 3, iclass 40, count 2 2006.238.08:12:21.72#ibcon#about to read 4, iclass 40, count 2 2006.238.08:12:21.72#ibcon#read 4, iclass 40, count 2 2006.238.08:12:21.72#ibcon#about to read 5, iclass 40, count 2 2006.238.08:12:21.72#ibcon#read 5, iclass 40, count 2 2006.238.08:12:21.72#ibcon#about to read 6, iclass 40, count 2 2006.238.08:12:21.72#ibcon#read 6, iclass 40, count 2 2006.238.08:12:21.72#ibcon#end of sib2, iclass 40, count 2 2006.238.08:12:21.72#ibcon#*mode == 0, iclass 40, count 2 2006.238.08:12:21.72#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.238.08:12:21.72#ibcon#[27=AT04-04\r\n] 2006.238.08:12:21.72#ibcon#*before write, iclass 40, count 2 2006.238.08:12:21.72#ibcon#enter sib2, iclass 40, count 2 2006.238.08:12:21.72#ibcon#flushed, iclass 40, count 2 2006.238.08:12:21.72#ibcon#about to write, iclass 40, count 2 2006.238.08:12:21.72#ibcon#wrote, iclass 40, count 2 2006.238.08:12:21.72#ibcon#about to read 3, iclass 40, count 2 2006.238.08:12:21.75#ibcon#read 3, iclass 40, count 2 2006.238.08:12:21.75#ibcon#about to read 4, iclass 40, count 2 2006.238.08:12:21.75#ibcon#read 4, iclass 40, count 2 2006.238.08:12:21.75#ibcon#about to read 5, iclass 40, count 2 2006.238.08:12:21.75#ibcon#read 5, iclass 40, count 2 2006.238.08:12:21.75#ibcon#about to read 6, iclass 40, count 2 2006.238.08:12:21.75#ibcon#read 6, iclass 40, count 2 2006.238.08:12:21.75#ibcon#end of sib2, iclass 40, count 2 2006.238.08:12:21.75#ibcon#*after write, iclass 40, count 2 2006.238.08:12:21.75#ibcon#*before return 0, iclass 40, count 2 2006.238.08:12:21.75#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:12:21.75#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:12:21.75#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.238.08:12:21.75#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:21.75#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:12:21.87#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:12:21.87#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:12:21.87#ibcon#enter wrdev, iclass 40, count 0 2006.238.08:12:21.87#ibcon#first serial, iclass 40, count 0 2006.238.08:12:21.87#ibcon#enter sib2, iclass 40, count 0 2006.238.08:12:21.87#ibcon#flushed, iclass 40, count 0 2006.238.08:12:21.87#ibcon#about to write, iclass 40, count 0 2006.238.08:12:21.87#ibcon#wrote, iclass 40, count 0 2006.238.08:12:21.87#ibcon#about to read 3, iclass 40, count 0 2006.238.08:12:21.89#ibcon#read 3, iclass 40, count 0 2006.238.08:12:21.89#ibcon#about to read 4, iclass 40, count 0 2006.238.08:12:21.89#ibcon#read 4, iclass 40, count 0 2006.238.08:12:21.89#ibcon#about to read 5, iclass 40, count 0 2006.238.08:12:21.89#ibcon#read 5, iclass 40, count 0 2006.238.08:12:21.89#ibcon#about to read 6, iclass 40, count 0 2006.238.08:12:21.89#ibcon#read 6, iclass 40, count 0 2006.238.08:12:21.89#ibcon#end of sib2, iclass 40, count 0 2006.238.08:12:21.89#ibcon#*mode == 0, iclass 40, count 0 2006.238.08:12:21.89#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.08:12:21.89#ibcon#[27=USB\r\n] 2006.238.08:12:21.89#ibcon#*before write, iclass 40, count 0 2006.238.08:12:21.89#ibcon#enter sib2, iclass 40, count 0 2006.238.08:12:21.89#ibcon#flushed, iclass 40, count 0 2006.238.08:12:21.89#ibcon#about to write, iclass 40, count 0 2006.238.08:12:21.89#ibcon#wrote, iclass 40, count 0 2006.238.08:12:21.89#ibcon#about to read 3, iclass 40, count 0 2006.238.08:12:21.92#ibcon#read 3, iclass 40, count 0 2006.238.08:12:21.92#ibcon#about to read 4, iclass 40, count 0 2006.238.08:12:21.92#ibcon#read 4, iclass 40, count 0 2006.238.08:12:21.92#ibcon#about to read 5, iclass 40, count 0 2006.238.08:12:21.92#ibcon#read 5, iclass 40, count 0 2006.238.08:12:21.92#ibcon#about to read 6, iclass 40, count 0 2006.238.08:12:21.92#ibcon#read 6, iclass 40, count 0 2006.238.08:12:21.92#ibcon#end of sib2, iclass 40, count 0 2006.238.08:12:21.92#ibcon#*after write, iclass 40, count 0 2006.238.08:12:21.92#ibcon#*before return 0, iclass 40, count 0 2006.238.08:12:21.92#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:12:21.92#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:12:21.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.08:12:21.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.08:12:21.92$vc4f8/vblo=5,744.99 2006.238.08:12:21.92#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.08:12:21.92#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.08:12:21.92#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:21.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:12:21.92#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:12:21.92#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:12:21.92#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:12:21.92#ibcon#first serial, iclass 4, count 0 2006.238.08:12:21.92#ibcon#enter sib2, iclass 4, count 0 2006.238.08:12:21.92#ibcon#flushed, iclass 4, count 0 2006.238.08:12:21.92#ibcon#about to write, iclass 4, count 0 2006.238.08:12:21.92#ibcon#wrote, iclass 4, count 0 2006.238.08:12:21.92#ibcon#about to read 3, iclass 4, count 0 2006.238.08:12:21.94#ibcon#read 3, iclass 4, count 0 2006.238.08:12:21.94#ibcon#about to read 4, iclass 4, count 0 2006.238.08:12:21.94#ibcon#read 4, iclass 4, count 0 2006.238.08:12:21.94#ibcon#about to read 5, iclass 4, count 0 2006.238.08:12:21.94#ibcon#read 5, iclass 4, count 0 2006.238.08:12:21.94#ibcon#about to read 6, iclass 4, count 0 2006.238.08:12:21.94#ibcon#read 6, iclass 4, count 0 2006.238.08:12:21.94#ibcon#end of sib2, iclass 4, count 0 2006.238.08:12:21.94#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:12:21.94#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:12:21.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:12:21.94#ibcon#*before write, iclass 4, count 0 2006.238.08:12:21.94#ibcon#enter sib2, iclass 4, count 0 2006.238.08:12:21.94#ibcon#flushed, iclass 4, count 0 2006.238.08:12:21.94#ibcon#about to write, iclass 4, count 0 2006.238.08:12:21.94#ibcon#wrote, iclass 4, count 0 2006.238.08:12:21.94#ibcon#about to read 3, iclass 4, count 0 2006.238.08:12:21.98#ibcon#read 3, iclass 4, count 0 2006.238.08:12:21.98#ibcon#about to read 4, iclass 4, count 0 2006.238.08:12:21.98#ibcon#read 4, iclass 4, count 0 2006.238.08:12:21.98#ibcon#about to read 5, iclass 4, count 0 2006.238.08:12:21.98#ibcon#read 5, iclass 4, count 0 2006.238.08:12:21.98#ibcon#about to read 6, iclass 4, count 0 2006.238.08:12:21.98#ibcon#read 6, iclass 4, count 0 2006.238.08:12:21.98#ibcon#end of sib2, iclass 4, count 0 2006.238.08:12:21.98#ibcon#*after write, iclass 4, count 0 2006.238.08:12:21.98#ibcon#*before return 0, iclass 4, count 0 2006.238.08:12:21.98#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:12:21.98#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:12:21.98#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:12:21.98#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:12:21.98$vc4f8/vb=5,4 2006.238.08:12:21.98#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.08:12:21.98#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.08:12:21.98#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:21.98#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:12:22.04#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:12:22.04#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:12:22.04#ibcon#enter wrdev, iclass 6, count 2 2006.238.08:12:22.04#ibcon#first serial, iclass 6, count 2 2006.238.08:12:22.04#ibcon#enter sib2, iclass 6, count 2 2006.238.08:12:22.04#ibcon#flushed, iclass 6, count 2 2006.238.08:12:22.04#ibcon#about to write, iclass 6, count 2 2006.238.08:12:22.04#ibcon#wrote, iclass 6, count 2 2006.238.08:12:22.04#ibcon#about to read 3, iclass 6, count 2 2006.238.08:12:22.06#ibcon#read 3, iclass 6, count 2 2006.238.08:12:22.06#ibcon#about to read 4, iclass 6, count 2 2006.238.08:12:22.06#ibcon#read 4, iclass 6, count 2 2006.238.08:12:22.06#ibcon#about to read 5, iclass 6, count 2 2006.238.08:12:22.06#ibcon#read 5, iclass 6, count 2 2006.238.08:12:22.06#ibcon#about to read 6, iclass 6, count 2 2006.238.08:12:22.06#ibcon#read 6, iclass 6, count 2 2006.238.08:12:22.06#ibcon#end of sib2, iclass 6, count 2 2006.238.08:12:22.06#ibcon#*mode == 0, iclass 6, count 2 2006.238.08:12:22.06#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.08:12:22.06#ibcon#[27=AT05-04\r\n] 2006.238.08:12:22.06#ibcon#*before write, iclass 6, count 2 2006.238.08:12:22.06#ibcon#enter sib2, iclass 6, count 2 2006.238.08:12:22.06#ibcon#flushed, iclass 6, count 2 2006.238.08:12:22.06#ibcon#about to write, iclass 6, count 2 2006.238.08:12:22.06#ibcon#wrote, iclass 6, count 2 2006.238.08:12:22.06#ibcon#about to read 3, iclass 6, count 2 2006.238.08:12:22.09#ibcon#read 3, iclass 6, count 2 2006.238.08:12:22.09#ibcon#about to read 4, iclass 6, count 2 2006.238.08:12:22.09#ibcon#read 4, iclass 6, count 2 2006.238.08:12:22.09#ibcon#about to read 5, iclass 6, count 2 2006.238.08:12:22.09#ibcon#read 5, iclass 6, count 2 2006.238.08:12:22.09#ibcon#about to read 6, iclass 6, count 2 2006.238.08:12:22.09#ibcon#read 6, iclass 6, count 2 2006.238.08:12:22.09#ibcon#end of sib2, iclass 6, count 2 2006.238.08:12:22.09#ibcon#*after write, iclass 6, count 2 2006.238.08:12:22.09#ibcon#*before return 0, iclass 6, count 2 2006.238.08:12:22.09#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:12:22.09#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:12:22.09#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.08:12:22.09#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:22.09#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:12:22.21#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:12:22.21#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:12:22.21#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:12:22.21#ibcon#first serial, iclass 6, count 0 2006.238.08:12:22.21#ibcon#enter sib2, iclass 6, count 0 2006.238.08:12:22.21#ibcon#flushed, iclass 6, count 0 2006.238.08:12:22.21#ibcon#about to write, iclass 6, count 0 2006.238.08:12:22.21#ibcon#wrote, iclass 6, count 0 2006.238.08:12:22.21#ibcon#about to read 3, iclass 6, count 0 2006.238.08:12:22.23#ibcon#read 3, iclass 6, count 0 2006.238.08:12:22.23#ibcon#about to read 4, iclass 6, count 0 2006.238.08:12:22.23#ibcon#read 4, iclass 6, count 0 2006.238.08:12:22.23#ibcon#about to read 5, iclass 6, count 0 2006.238.08:12:22.23#ibcon#read 5, iclass 6, count 0 2006.238.08:12:22.23#ibcon#about to read 6, iclass 6, count 0 2006.238.08:12:22.23#ibcon#read 6, iclass 6, count 0 2006.238.08:12:22.23#ibcon#end of sib2, iclass 6, count 0 2006.238.08:12:22.23#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:12:22.23#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:12:22.23#ibcon#[27=USB\r\n] 2006.238.08:12:22.23#ibcon#*before write, iclass 6, count 0 2006.238.08:12:22.23#ibcon#enter sib2, iclass 6, count 0 2006.238.08:12:22.23#ibcon#flushed, iclass 6, count 0 2006.238.08:12:22.23#ibcon#about to write, iclass 6, count 0 2006.238.08:12:22.23#ibcon#wrote, iclass 6, count 0 2006.238.08:12:22.23#ibcon#about to read 3, iclass 6, count 0 2006.238.08:12:22.26#ibcon#read 3, iclass 6, count 0 2006.238.08:12:22.26#ibcon#about to read 4, iclass 6, count 0 2006.238.08:12:22.26#ibcon#read 4, iclass 6, count 0 2006.238.08:12:22.26#ibcon#about to read 5, iclass 6, count 0 2006.238.08:12:22.26#ibcon#read 5, iclass 6, count 0 2006.238.08:12:22.26#ibcon#about to read 6, iclass 6, count 0 2006.238.08:12:22.26#ibcon#read 6, iclass 6, count 0 2006.238.08:12:22.26#ibcon#end of sib2, iclass 6, count 0 2006.238.08:12:22.26#ibcon#*after write, iclass 6, count 0 2006.238.08:12:22.26#ibcon#*before return 0, iclass 6, count 0 2006.238.08:12:22.26#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:12:22.26#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:12:22.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:12:22.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:12:22.26$vc4f8/vblo=6,752.99 2006.238.08:12:22.26#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.08:12:22.26#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.08:12:22.26#ibcon#ireg 17 cls_cnt 0 2006.238.08:12:22.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:12:22.26#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:12:22.26#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:12:22.26#ibcon#enter wrdev, iclass 10, count 0 2006.238.08:12:22.26#ibcon#first serial, iclass 10, count 0 2006.238.08:12:22.26#ibcon#enter sib2, iclass 10, count 0 2006.238.08:12:22.26#ibcon#flushed, iclass 10, count 0 2006.238.08:12:22.26#ibcon#about to write, iclass 10, count 0 2006.238.08:12:22.26#ibcon#wrote, iclass 10, count 0 2006.238.08:12:22.26#ibcon#about to read 3, iclass 10, count 0 2006.238.08:12:22.28#ibcon#read 3, iclass 10, count 0 2006.238.08:12:22.28#ibcon#about to read 4, iclass 10, count 0 2006.238.08:12:22.28#ibcon#read 4, iclass 10, count 0 2006.238.08:12:22.28#ibcon#about to read 5, iclass 10, count 0 2006.238.08:12:22.28#ibcon#read 5, iclass 10, count 0 2006.238.08:12:22.28#ibcon#about to read 6, iclass 10, count 0 2006.238.08:12:22.28#ibcon#read 6, iclass 10, count 0 2006.238.08:12:22.28#ibcon#end of sib2, iclass 10, count 0 2006.238.08:12:22.28#ibcon#*mode == 0, iclass 10, count 0 2006.238.08:12:22.28#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.08:12:22.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:12:22.28#ibcon#*before write, iclass 10, count 0 2006.238.08:12:22.28#ibcon#enter sib2, iclass 10, count 0 2006.238.08:12:22.28#ibcon#flushed, iclass 10, count 0 2006.238.08:12:22.28#ibcon#about to write, iclass 10, count 0 2006.238.08:12:22.28#ibcon#wrote, iclass 10, count 0 2006.238.08:12:22.28#ibcon#about to read 3, iclass 10, count 0 2006.238.08:12:22.32#ibcon#read 3, iclass 10, count 0 2006.238.08:12:22.32#ibcon#about to read 4, iclass 10, count 0 2006.238.08:12:22.32#ibcon#read 4, iclass 10, count 0 2006.238.08:12:22.32#ibcon#about to read 5, iclass 10, count 0 2006.238.08:12:22.32#ibcon#read 5, iclass 10, count 0 2006.238.08:12:22.32#ibcon#about to read 6, iclass 10, count 0 2006.238.08:12:22.32#ibcon#read 6, iclass 10, count 0 2006.238.08:12:22.32#ibcon#end of sib2, iclass 10, count 0 2006.238.08:12:22.32#ibcon#*after write, iclass 10, count 0 2006.238.08:12:22.32#ibcon#*before return 0, iclass 10, count 0 2006.238.08:12:22.32#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:12:22.32#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:12:22.32#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.08:12:22.32#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.08:12:22.32$vc4f8/vb=6,4 2006.238.08:12:22.32#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.238.08:12:22.32#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.238.08:12:22.32#ibcon#ireg 11 cls_cnt 2 2006.238.08:12:22.32#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:12:22.38#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:12:22.38#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:12:22.38#ibcon#enter wrdev, iclass 12, count 2 2006.238.08:12:22.38#ibcon#first serial, iclass 12, count 2 2006.238.08:12:22.38#ibcon#enter sib2, iclass 12, count 2 2006.238.08:12:22.38#ibcon#flushed, iclass 12, count 2 2006.238.08:12:22.38#ibcon#about to write, iclass 12, count 2 2006.238.08:12:22.38#ibcon#wrote, iclass 12, count 2 2006.238.08:12:22.38#ibcon#about to read 3, iclass 12, count 2 2006.238.08:12:22.40#ibcon#read 3, iclass 12, count 2 2006.238.08:12:22.40#ibcon#about to read 4, iclass 12, count 2 2006.238.08:12:22.40#ibcon#read 4, iclass 12, count 2 2006.238.08:12:22.40#ibcon#about to read 5, iclass 12, count 2 2006.238.08:12:22.40#ibcon#read 5, iclass 12, count 2 2006.238.08:12:22.40#ibcon#about to read 6, iclass 12, count 2 2006.238.08:12:22.40#ibcon#read 6, iclass 12, count 2 2006.238.08:12:22.40#ibcon#end of sib2, iclass 12, count 2 2006.238.08:12:22.40#ibcon#*mode == 0, iclass 12, count 2 2006.238.08:12:22.40#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.238.08:12:22.40#ibcon#[27=AT06-04\r\n] 2006.238.08:12:22.40#ibcon#*before write, iclass 12, count 2 2006.238.08:12:22.40#ibcon#enter sib2, iclass 12, count 2 2006.238.08:12:22.40#ibcon#flushed, iclass 12, count 2 2006.238.08:12:22.40#ibcon#about to write, iclass 12, count 2 2006.238.08:12:22.40#ibcon#wrote, iclass 12, count 2 2006.238.08:12:22.40#ibcon#about to read 3, iclass 12, count 2 2006.238.08:12:22.43#ibcon#read 3, iclass 12, count 2 2006.238.08:12:22.43#ibcon#about to read 4, iclass 12, count 2 2006.238.08:12:22.43#ibcon#read 4, iclass 12, count 2 2006.238.08:12:22.43#ibcon#about to read 5, iclass 12, count 2 2006.238.08:12:22.43#ibcon#read 5, iclass 12, count 2 2006.238.08:12:22.43#ibcon#about to read 6, iclass 12, count 2 2006.238.08:12:22.43#ibcon#read 6, iclass 12, count 2 2006.238.08:12:22.43#ibcon#end of sib2, iclass 12, count 2 2006.238.08:12:22.43#ibcon#*after write, iclass 12, count 2 2006.238.08:12:22.43#ibcon#*before return 0, iclass 12, count 2 2006.238.08:12:22.43#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:12:22.43#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:12:22.43#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.238.08:12:22.43#ibcon#ireg 7 cls_cnt 0 2006.238.08:12:22.43#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:12:22.55#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:12:22.55#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:12:22.55#ibcon#enter wrdev, iclass 12, count 0 2006.238.08:12:22.55#ibcon#first serial, iclass 12, count 0 2006.238.08:12:22.55#ibcon#enter sib2, iclass 12, count 0 2006.238.08:12:22.55#ibcon#flushed, iclass 12, count 0 2006.238.08:12:22.55#ibcon#about to write, iclass 12, count 0 2006.238.08:12:22.55#ibcon#wrote, iclass 12, count 0 2006.238.08:12:22.55#ibcon#about to read 3, iclass 12, count 0 2006.238.08:12:22.57#ibcon#read 3, iclass 12, count 0 2006.238.08:12:22.57#ibcon#about to read 4, iclass 12, count 0 2006.238.08:12:22.57#ibcon#read 4, iclass 12, count 0 2006.238.08:12:22.57#ibcon#about to read 5, iclass 12, count 0 2006.238.08:12:22.57#ibcon#read 5, iclass 12, count 0 2006.238.08:12:22.57#ibcon#about to read 6, iclass 12, count 0 2006.238.08:12:22.57#ibcon#read 6, iclass 12, count 0 2006.238.08:12:22.57#ibcon#end of sib2, iclass 12, count 0 2006.238.08:12:22.57#ibcon#*mode == 0, iclass 12, count 0 2006.238.08:12:22.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.08:12:22.57#ibcon#[27=USB\r\n] 2006.238.08:12:22.57#ibcon#*before write, iclass 12, count 0 2006.238.08:12:22.57#ibcon#enter sib2, iclass 12, count 0 2006.238.08:12:22.57#ibcon#flushed, iclass 12, count 0 2006.238.08:12:22.57#ibcon#about to write, iclass 12, count 0 2006.238.08:12:22.57#ibcon#wrote, iclass 12, count 0 2006.238.08:12:22.57#ibcon#about to read 3, iclass 12, count 0 2006.238.08:12:22.60#ibcon#read 3, iclass 12, count 0 2006.238.08:12:22.60#ibcon#about to read 4, iclass 12, count 0 2006.238.08:12:22.60#ibcon#read 4, iclass 12, count 0 2006.238.08:12:22.60#ibcon#about to read 5, iclass 12, count 0 2006.238.08:12:22.60#ibcon#read 5, iclass 12, count 0 2006.238.08:12:22.60#ibcon#about to read 6, iclass 12, count 0 2006.238.08:12:22.60#ibcon#read 6, iclass 12, count 0 2006.238.08:12:22.60#ibcon#end of sib2, iclass 12, count 0 2006.238.08:12:22.60#ibcon#*after write, iclass 12, count 0 2006.238.08:12:22.60#ibcon#*before return 0, iclass 12, count 0 2006.238.08:12:22.60#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:12:22.60#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:12:22.60#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.08:12:22.60#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.08:12:22.60$vc4f8/vabw=wide 2006.238.08:12:22.60#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.08:12:22.60#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.08:12:22.60#ibcon#ireg 8 cls_cnt 0 2006.238.08:12:22.60#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:12:22.60#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:12:22.60#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:12:22.60#ibcon#enter wrdev, iclass 14, count 0 2006.238.08:12:22.60#ibcon#first serial, iclass 14, count 0 2006.238.08:12:22.60#ibcon#enter sib2, iclass 14, count 0 2006.238.08:12:22.60#ibcon#flushed, iclass 14, count 0 2006.238.08:12:22.60#ibcon#about to write, iclass 14, count 0 2006.238.08:12:22.60#ibcon#wrote, iclass 14, count 0 2006.238.08:12:22.60#ibcon#about to read 3, iclass 14, count 0 2006.238.08:12:22.62#ibcon#read 3, iclass 14, count 0 2006.238.08:12:22.62#ibcon#about to read 4, iclass 14, count 0 2006.238.08:12:22.62#ibcon#read 4, iclass 14, count 0 2006.238.08:12:22.62#ibcon#about to read 5, iclass 14, count 0 2006.238.08:12:22.62#ibcon#read 5, iclass 14, count 0 2006.238.08:12:22.62#ibcon#about to read 6, iclass 14, count 0 2006.238.08:12:22.62#ibcon#read 6, iclass 14, count 0 2006.238.08:12:22.62#ibcon#end of sib2, iclass 14, count 0 2006.238.08:12:22.62#ibcon#*mode == 0, iclass 14, count 0 2006.238.08:12:22.62#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.08:12:22.62#ibcon#[25=BW32\r\n] 2006.238.08:12:22.62#ibcon#*before write, iclass 14, count 0 2006.238.08:12:22.62#ibcon#enter sib2, iclass 14, count 0 2006.238.08:12:22.62#ibcon#flushed, iclass 14, count 0 2006.238.08:12:22.62#ibcon#about to write, iclass 14, count 0 2006.238.08:12:22.62#ibcon#wrote, iclass 14, count 0 2006.238.08:12:22.62#ibcon#about to read 3, iclass 14, count 0 2006.238.08:12:22.65#ibcon#read 3, iclass 14, count 0 2006.238.08:12:22.65#ibcon#about to read 4, iclass 14, count 0 2006.238.08:12:22.65#ibcon#read 4, iclass 14, count 0 2006.238.08:12:22.65#ibcon#about to read 5, iclass 14, count 0 2006.238.08:12:22.65#ibcon#read 5, iclass 14, count 0 2006.238.08:12:22.65#ibcon#about to read 6, iclass 14, count 0 2006.238.08:12:22.65#ibcon#read 6, iclass 14, count 0 2006.238.08:12:22.65#ibcon#end of sib2, iclass 14, count 0 2006.238.08:12:22.65#ibcon#*after write, iclass 14, count 0 2006.238.08:12:22.65#ibcon#*before return 0, iclass 14, count 0 2006.238.08:12:22.65#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:12:22.65#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:12:22.65#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.08:12:22.65#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.08:12:22.65$vc4f8/vbbw=wide 2006.238.08:12:22.65#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.08:12:22.65#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.08:12:22.65#ibcon#ireg 8 cls_cnt 0 2006.238.08:12:22.65#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:12:22.72#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:12:22.72#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:12:22.72#ibcon#enter wrdev, iclass 16, count 0 2006.238.08:12:22.72#ibcon#first serial, iclass 16, count 0 2006.238.08:12:22.72#ibcon#enter sib2, iclass 16, count 0 2006.238.08:12:22.72#ibcon#flushed, iclass 16, count 0 2006.238.08:12:22.72#ibcon#about to write, iclass 16, count 0 2006.238.08:12:22.72#ibcon#wrote, iclass 16, count 0 2006.238.08:12:22.72#ibcon#about to read 3, iclass 16, count 0 2006.238.08:12:22.74#ibcon#read 3, iclass 16, count 0 2006.238.08:12:22.74#ibcon#about to read 4, iclass 16, count 0 2006.238.08:12:22.74#ibcon#read 4, iclass 16, count 0 2006.238.08:12:22.74#ibcon#about to read 5, iclass 16, count 0 2006.238.08:12:22.74#ibcon#read 5, iclass 16, count 0 2006.238.08:12:22.74#ibcon#about to read 6, iclass 16, count 0 2006.238.08:12:22.74#ibcon#read 6, iclass 16, count 0 2006.238.08:12:22.74#ibcon#end of sib2, iclass 16, count 0 2006.238.08:12:22.74#ibcon#*mode == 0, iclass 16, count 0 2006.238.08:12:22.74#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.08:12:22.74#ibcon#[27=BW32\r\n] 2006.238.08:12:22.74#ibcon#*before write, iclass 16, count 0 2006.238.08:12:22.74#ibcon#enter sib2, iclass 16, count 0 2006.238.08:12:22.74#ibcon#flushed, iclass 16, count 0 2006.238.08:12:22.74#ibcon#about to write, iclass 16, count 0 2006.238.08:12:22.74#ibcon#wrote, iclass 16, count 0 2006.238.08:12:22.74#ibcon#about to read 3, iclass 16, count 0 2006.238.08:12:22.77#ibcon#read 3, iclass 16, count 0 2006.238.08:12:22.77#ibcon#about to read 4, iclass 16, count 0 2006.238.08:12:22.77#ibcon#read 4, iclass 16, count 0 2006.238.08:12:22.77#ibcon#about to read 5, iclass 16, count 0 2006.238.08:12:22.77#ibcon#read 5, iclass 16, count 0 2006.238.08:12:22.77#ibcon#about to read 6, iclass 16, count 0 2006.238.08:12:22.77#ibcon#read 6, iclass 16, count 0 2006.238.08:12:22.77#ibcon#end of sib2, iclass 16, count 0 2006.238.08:12:22.77#ibcon#*after write, iclass 16, count 0 2006.238.08:12:22.77#ibcon#*before return 0, iclass 16, count 0 2006.238.08:12:22.77#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:12:22.77#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:12:22.77#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.08:12:22.77#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.08:12:22.77$4f8m12a/ifd4f 2006.238.08:12:22.77$ifd4f/lo= 2006.238.08:12:22.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:12:22.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:12:22.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:12:22.77$ifd4f/patch= 2006.238.08:12:22.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:12:22.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:12:22.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:12:22.77$4f8m12a/"form=m,16.000,1:2 2006.238.08:12:22.77$4f8m12a/"tpicd 2006.238.08:12:22.77$4f8m12a/echo=off 2006.238.08:12:22.77$4f8m12a/xlog=off 2006.238.08:12:22.77:!2006.238.08:13:00 2006.238.08:12:40.14#trakl#Source acquired 2006.238.08:12:41.14#flagr#flagr/antenna,acquired 2006.238.08:13:00.00:preob 2006.238.08:13:00.14/onsource/TRACKING 2006.238.08:13:00.14:!2006.238.08:13:10 2006.238.08:13:10.00:data_valid=on 2006.238.08:13:10.00:midob 2006.238.08:13:11.14/onsource/TRACKING 2006.238.08:13:11.14/wx/25.48,1012.2,90 2006.238.08:13:11.25/cable/+6.4184E-03 2006.238.08:13:12.34/va/01,08,usb,yes,32,33 2006.238.08:13:12.34/va/02,07,usb,yes,31,33 2006.238.08:13:12.34/va/03,07,usb,yes,30,30 2006.238.08:13:12.34/va/04,07,usb,yes,33,35 2006.238.08:13:12.34/va/05,08,usb,yes,30,32 2006.238.08:13:12.34/va/06,07,usb,yes,33,33 2006.238.08:13:12.34/va/07,07,usb,yes,33,33 2006.238.08:13:12.34/va/08,07,usb,yes,35,35 2006.238.08:13:12.57/valo/01,532.99,yes,locked 2006.238.08:13:12.57/valo/02,572.99,yes,locked 2006.238.08:13:12.57/valo/03,672.99,yes,locked 2006.238.08:13:12.57/valo/04,832.99,yes,locked 2006.238.08:13:12.57/valo/05,652.99,yes,locked 2006.238.08:13:12.57/valo/06,772.99,yes,locked 2006.238.08:13:12.57/valo/07,832.99,yes,locked 2006.238.08:13:12.57/valo/08,852.99,yes,locked 2006.238.08:13:13.66/vb/01,04,usb,yes,30,29 2006.238.08:13:13.66/vb/02,04,usb,yes,32,33 2006.238.08:13:13.66/vb/03,04,usb,yes,28,32 2006.238.08:13:13.66/vb/04,04,usb,yes,29,29 2006.238.08:13:13.66/vb/05,04,usb,yes,27,31 2006.238.08:13:13.66/vb/06,04,usb,yes,28,31 2006.238.08:13:13.66/vb/07,04,usb,yes,31,31 2006.238.08:13:13.66/vb/08,04,usb,yes,28,31 2006.238.08:13:13.89/vblo/01,632.99,yes,locked 2006.238.08:13:13.89/vblo/02,640.99,yes,locked 2006.238.08:13:13.89/vblo/03,656.99,yes,locked 2006.238.08:13:13.89/vblo/04,712.99,yes,locked 2006.238.08:13:13.89/vblo/05,744.99,yes,locked 2006.238.08:13:13.89/vblo/06,752.99,yes,locked 2006.238.08:13:13.89/vblo/07,734.99,yes,locked 2006.238.08:13:13.89/vblo/08,744.99,yes,locked 2006.238.08:13:14.04/vabw/8 2006.238.08:13:14.19/vbbw/8 2006.238.08:13:14.28/xfe/off,on,12.7 2006.238.08:13:14.65/ifatt/23,28,28,28 2006.238.08:13:15.08/fmout-gps/S +4.42E-07 2006.238.08:13:15.12:!2006.238.08:14:10 2006.238.08:14:10.00:data_valid=off 2006.238.08:14:10.00:postob 2006.238.08:14:10.18/cable/+6.4170E-03 2006.238.08:14:10.19/wx/25.48,1012.2,90 2006.238.08:14:11.08/fmout-gps/S +4.44E-07 2006.238.08:14:11.08:scan_name=238-0815,k06238,60 2006.238.08:14:11.09:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.238.08:14:11.14#flagr#flagr/antenna,new-source 2006.238.08:14:12.14:checkk5 2006.238.08:14:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:14:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:14:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:14:13.66/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:14:14.04/chk_obsdata//k5ts1/T2380813??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:14:14.41/chk_obsdata//k5ts2/T2380813??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:14:14.78/chk_obsdata//k5ts3/T2380813??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:14:15.15/chk_obsdata//k5ts4/T2380813??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.238.08:14:15.85/k5log//k5ts1_log_newline 2006.238.08:14:16.55/k5log//k5ts2_log_newline 2006.238.08:14:17.26/k5log//k5ts3_log_newline 2006.238.08:14:17.97/k5log//k5ts4_log_newline 2006.238.08:14:17.99/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:14:17.99:4f8m12a=2 2006.238.08:14:17.99$4f8m12a/echo=on 2006.238.08:14:17.99$4f8m12a/pcalon 2006.238.08:14:17.99$pcalon/"no phase cal control is implemented here 2006.238.08:14:17.99$4f8m12a/"tpicd=stop 2006.238.08:14:17.99$4f8m12a/vc4f8 2006.238.08:14:18.00$vc4f8/valo=1,532.99 2006.238.08:14:18.00#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.08:14:18.00#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.08:14:18.00#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:18.00#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:14:18.00#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:14:18.00#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:14:18.00#ibcon#enter wrdev, iclass 27, count 0 2006.238.08:14:18.00#ibcon#first serial, iclass 27, count 0 2006.238.08:14:18.00#ibcon#enter sib2, iclass 27, count 0 2006.238.08:14:18.00#ibcon#flushed, iclass 27, count 0 2006.238.08:14:18.00#ibcon#about to write, iclass 27, count 0 2006.238.08:14:18.00#ibcon#wrote, iclass 27, count 0 2006.238.08:14:18.00#ibcon#about to read 3, iclass 27, count 0 2006.238.08:14:18.04#ibcon#read 3, iclass 27, count 0 2006.238.08:14:18.04#ibcon#about to read 4, iclass 27, count 0 2006.238.08:14:18.04#ibcon#read 4, iclass 27, count 0 2006.238.08:14:18.04#ibcon#about to read 5, iclass 27, count 0 2006.238.08:14:18.04#ibcon#read 5, iclass 27, count 0 2006.238.08:14:18.04#ibcon#about to read 6, iclass 27, count 0 2006.238.08:14:18.04#ibcon#read 6, iclass 27, count 0 2006.238.08:14:18.04#ibcon#end of sib2, iclass 27, count 0 2006.238.08:14:18.04#ibcon#*mode == 0, iclass 27, count 0 2006.238.08:14:18.04#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.08:14:18.04#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:14:18.04#ibcon#*before write, iclass 27, count 0 2006.238.08:14:18.04#ibcon#enter sib2, iclass 27, count 0 2006.238.08:14:18.04#ibcon#flushed, iclass 27, count 0 2006.238.08:14:18.04#ibcon#about to write, iclass 27, count 0 2006.238.08:14:18.04#ibcon#wrote, iclass 27, count 0 2006.238.08:14:18.04#ibcon#about to read 3, iclass 27, count 0 2006.238.08:14:18.09#ibcon#read 3, iclass 27, count 0 2006.238.08:14:18.09#ibcon#about to read 4, iclass 27, count 0 2006.238.08:14:18.09#ibcon#read 4, iclass 27, count 0 2006.238.08:14:18.09#ibcon#about to read 5, iclass 27, count 0 2006.238.08:14:18.09#ibcon#read 5, iclass 27, count 0 2006.238.08:14:18.09#ibcon#about to read 6, iclass 27, count 0 2006.238.08:14:18.09#ibcon#read 6, iclass 27, count 0 2006.238.08:14:18.09#ibcon#end of sib2, iclass 27, count 0 2006.238.08:14:18.09#ibcon#*after write, iclass 27, count 0 2006.238.08:14:18.09#ibcon#*before return 0, iclass 27, count 0 2006.238.08:14:18.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:14:18.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:14:18.09#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.08:14:18.09#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.08:14:18.09$vc4f8/va=1,8 2006.238.08:14:18.09#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.08:14:18.09#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.08:14:18.09#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:18.09#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:14:18.09#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:14:18.09#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:14:18.09#ibcon#enter wrdev, iclass 29, count 2 2006.238.08:14:18.09#ibcon#first serial, iclass 29, count 2 2006.238.08:14:18.09#ibcon#enter sib2, iclass 29, count 2 2006.238.08:14:18.09#ibcon#flushed, iclass 29, count 2 2006.238.08:14:18.09#ibcon#about to write, iclass 29, count 2 2006.238.08:14:18.09#ibcon#wrote, iclass 29, count 2 2006.238.08:14:18.09#ibcon#about to read 3, iclass 29, count 2 2006.238.08:14:18.12#ibcon#read 3, iclass 29, count 2 2006.238.08:14:18.12#ibcon#about to read 4, iclass 29, count 2 2006.238.08:14:18.12#ibcon#read 4, iclass 29, count 2 2006.238.08:14:18.12#ibcon#about to read 5, iclass 29, count 2 2006.238.08:14:18.12#ibcon#read 5, iclass 29, count 2 2006.238.08:14:18.12#ibcon#about to read 6, iclass 29, count 2 2006.238.08:14:18.12#ibcon#read 6, iclass 29, count 2 2006.238.08:14:18.12#ibcon#end of sib2, iclass 29, count 2 2006.238.08:14:18.12#ibcon#*mode == 0, iclass 29, count 2 2006.238.08:14:18.12#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.08:14:18.12#ibcon#[25=AT01-08\r\n] 2006.238.08:14:18.12#ibcon#*before write, iclass 29, count 2 2006.238.08:14:18.12#ibcon#enter sib2, iclass 29, count 2 2006.238.08:14:18.12#ibcon#flushed, iclass 29, count 2 2006.238.08:14:18.12#ibcon#about to write, iclass 29, count 2 2006.238.08:14:18.12#ibcon#wrote, iclass 29, count 2 2006.238.08:14:18.12#ibcon#about to read 3, iclass 29, count 2 2006.238.08:14:18.15#ibcon#read 3, iclass 29, count 2 2006.238.08:14:18.15#ibcon#about to read 4, iclass 29, count 2 2006.238.08:14:18.15#ibcon#read 4, iclass 29, count 2 2006.238.08:14:18.15#ibcon#about to read 5, iclass 29, count 2 2006.238.08:14:18.15#ibcon#read 5, iclass 29, count 2 2006.238.08:14:18.15#ibcon#about to read 6, iclass 29, count 2 2006.238.08:14:18.15#ibcon#read 6, iclass 29, count 2 2006.238.08:14:18.15#ibcon#end of sib2, iclass 29, count 2 2006.238.08:14:18.15#ibcon#*after write, iclass 29, count 2 2006.238.08:14:18.15#ibcon#*before return 0, iclass 29, count 2 2006.238.08:14:18.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:14:18.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:14:18.15#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.08:14:18.15#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:18.15#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:14:18.27#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:14:18.27#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:14:18.27#ibcon#enter wrdev, iclass 29, count 0 2006.238.08:14:18.27#ibcon#first serial, iclass 29, count 0 2006.238.08:14:18.27#ibcon#enter sib2, iclass 29, count 0 2006.238.08:14:18.27#ibcon#flushed, iclass 29, count 0 2006.238.08:14:18.27#ibcon#about to write, iclass 29, count 0 2006.238.08:14:18.27#ibcon#wrote, iclass 29, count 0 2006.238.08:14:18.27#ibcon#about to read 3, iclass 29, count 0 2006.238.08:14:18.29#ibcon#read 3, iclass 29, count 0 2006.238.08:14:18.29#ibcon#about to read 4, iclass 29, count 0 2006.238.08:14:18.29#ibcon#read 4, iclass 29, count 0 2006.238.08:14:18.29#ibcon#about to read 5, iclass 29, count 0 2006.238.08:14:18.29#ibcon#read 5, iclass 29, count 0 2006.238.08:14:18.29#ibcon#about to read 6, iclass 29, count 0 2006.238.08:14:18.29#ibcon#read 6, iclass 29, count 0 2006.238.08:14:18.29#ibcon#end of sib2, iclass 29, count 0 2006.238.08:14:18.29#ibcon#*mode == 0, iclass 29, count 0 2006.238.08:14:18.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.08:14:18.29#ibcon#[25=USB\r\n] 2006.238.08:14:18.29#ibcon#*before write, iclass 29, count 0 2006.238.08:14:18.29#ibcon#enter sib2, iclass 29, count 0 2006.238.08:14:18.29#ibcon#flushed, iclass 29, count 0 2006.238.08:14:18.29#ibcon#about to write, iclass 29, count 0 2006.238.08:14:18.29#ibcon#wrote, iclass 29, count 0 2006.238.08:14:18.29#ibcon#about to read 3, iclass 29, count 0 2006.238.08:14:18.32#ibcon#read 3, iclass 29, count 0 2006.238.08:14:18.32#ibcon#about to read 4, iclass 29, count 0 2006.238.08:14:18.32#ibcon#read 4, iclass 29, count 0 2006.238.08:14:18.32#ibcon#about to read 5, iclass 29, count 0 2006.238.08:14:18.32#ibcon#read 5, iclass 29, count 0 2006.238.08:14:18.32#ibcon#about to read 6, iclass 29, count 0 2006.238.08:14:18.32#ibcon#read 6, iclass 29, count 0 2006.238.08:14:18.32#ibcon#end of sib2, iclass 29, count 0 2006.238.08:14:18.32#ibcon#*after write, iclass 29, count 0 2006.238.08:14:18.32#ibcon#*before return 0, iclass 29, count 0 2006.238.08:14:18.32#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:14:18.32#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:14:18.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.08:14:18.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.08:14:18.32$vc4f8/valo=2,572.99 2006.238.08:14:18.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.08:14:18.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.08:14:18.32#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:18.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:14:18.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:14:18.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:14:18.32#ibcon#enter wrdev, iclass 31, count 0 2006.238.08:14:18.32#ibcon#first serial, iclass 31, count 0 2006.238.08:14:18.32#ibcon#enter sib2, iclass 31, count 0 2006.238.08:14:18.32#ibcon#flushed, iclass 31, count 0 2006.238.08:14:18.32#ibcon#about to write, iclass 31, count 0 2006.238.08:14:18.32#ibcon#wrote, iclass 31, count 0 2006.238.08:14:18.32#ibcon#about to read 3, iclass 31, count 0 2006.238.08:14:18.34#ibcon#read 3, iclass 31, count 0 2006.238.08:14:18.34#ibcon#about to read 4, iclass 31, count 0 2006.238.08:14:18.34#ibcon#read 4, iclass 31, count 0 2006.238.08:14:18.34#ibcon#about to read 5, iclass 31, count 0 2006.238.08:14:18.34#ibcon#read 5, iclass 31, count 0 2006.238.08:14:18.34#ibcon#about to read 6, iclass 31, count 0 2006.238.08:14:18.34#ibcon#read 6, iclass 31, count 0 2006.238.08:14:18.34#ibcon#end of sib2, iclass 31, count 0 2006.238.08:14:18.34#ibcon#*mode == 0, iclass 31, count 0 2006.238.08:14:18.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.08:14:18.34#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:14:18.34#ibcon#*before write, iclass 31, count 0 2006.238.08:14:18.34#ibcon#enter sib2, iclass 31, count 0 2006.238.08:14:18.34#ibcon#flushed, iclass 31, count 0 2006.238.08:14:18.34#ibcon#about to write, iclass 31, count 0 2006.238.08:14:18.34#ibcon#wrote, iclass 31, count 0 2006.238.08:14:18.34#ibcon#about to read 3, iclass 31, count 0 2006.238.08:14:18.38#ibcon#read 3, iclass 31, count 0 2006.238.08:14:18.38#ibcon#about to read 4, iclass 31, count 0 2006.238.08:14:18.38#ibcon#read 4, iclass 31, count 0 2006.238.08:14:18.38#ibcon#about to read 5, iclass 31, count 0 2006.238.08:14:18.38#ibcon#read 5, iclass 31, count 0 2006.238.08:14:18.38#ibcon#about to read 6, iclass 31, count 0 2006.238.08:14:18.38#ibcon#read 6, iclass 31, count 0 2006.238.08:14:18.38#ibcon#end of sib2, iclass 31, count 0 2006.238.08:14:18.38#ibcon#*after write, iclass 31, count 0 2006.238.08:14:18.38#ibcon#*before return 0, iclass 31, count 0 2006.238.08:14:18.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:14:18.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:14:18.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.08:14:18.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.08:14:18.38$vc4f8/va=2,7 2006.238.08:14:18.38#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.08:14:18.38#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.08:14:18.38#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:18.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:14:18.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:14:18.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:14:18.44#ibcon#enter wrdev, iclass 33, count 2 2006.238.08:14:18.44#ibcon#first serial, iclass 33, count 2 2006.238.08:14:18.44#ibcon#enter sib2, iclass 33, count 2 2006.238.08:14:18.44#ibcon#flushed, iclass 33, count 2 2006.238.08:14:18.44#ibcon#about to write, iclass 33, count 2 2006.238.08:14:18.44#ibcon#wrote, iclass 33, count 2 2006.238.08:14:18.44#ibcon#about to read 3, iclass 33, count 2 2006.238.08:14:18.46#ibcon#read 3, iclass 33, count 2 2006.238.08:14:18.46#ibcon#about to read 4, iclass 33, count 2 2006.238.08:14:18.46#ibcon#read 4, iclass 33, count 2 2006.238.08:14:18.46#ibcon#about to read 5, iclass 33, count 2 2006.238.08:14:18.46#ibcon#read 5, iclass 33, count 2 2006.238.08:14:18.46#ibcon#about to read 6, iclass 33, count 2 2006.238.08:14:18.46#ibcon#read 6, iclass 33, count 2 2006.238.08:14:18.46#ibcon#end of sib2, iclass 33, count 2 2006.238.08:14:18.46#ibcon#*mode == 0, iclass 33, count 2 2006.238.08:14:18.46#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.08:14:18.46#ibcon#[25=AT02-07\r\n] 2006.238.08:14:18.46#ibcon#*before write, iclass 33, count 2 2006.238.08:14:18.46#ibcon#enter sib2, iclass 33, count 2 2006.238.08:14:18.46#ibcon#flushed, iclass 33, count 2 2006.238.08:14:18.46#ibcon#about to write, iclass 33, count 2 2006.238.08:14:18.46#ibcon#wrote, iclass 33, count 2 2006.238.08:14:18.46#ibcon#about to read 3, iclass 33, count 2 2006.238.08:14:18.49#ibcon#read 3, iclass 33, count 2 2006.238.08:14:18.49#ibcon#about to read 4, iclass 33, count 2 2006.238.08:14:18.49#ibcon#read 4, iclass 33, count 2 2006.238.08:14:18.49#ibcon#about to read 5, iclass 33, count 2 2006.238.08:14:18.49#ibcon#read 5, iclass 33, count 2 2006.238.08:14:18.49#ibcon#about to read 6, iclass 33, count 2 2006.238.08:14:18.49#ibcon#read 6, iclass 33, count 2 2006.238.08:14:18.49#ibcon#end of sib2, iclass 33, count 2 2006.238.08:14:18.49#ibcon#*after write, iclass 33, count 2 2006.238.08:14:18.49#ibcon#*before return 0, iclass 33, count 2 2006.238.08:14:18.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:14:18.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:14:18.49#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.08:14:18.49#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:18.49#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:14:18.61#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:14:18.61#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:14:18.61#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:14:18.61#ibcon#first serial, iclass 33, count 0 2006.238.08:14:18.61#ibcon#enter sib2, iclass 33, count 0 2006.238.08:14:18.61#ibcon#flushed, iclass 33, count 0 2006.238.08:14:18.61#ibcon#about to write, iclass 33, count 0 2006.238.08:14:18.61#ibcon#wrote, iclass 33, count 0 2006.238.08:14:18.61#ibcon#about to read 3, iclass 33, count 0 2006.238.08:14:18.63#ibcon#read 3, iclass 33, count 0 2006.238.08:14:18.63#ibcon#about to read 4, iclass 33, count 0 2006.238.08:14:18.63#ibcon#read 4, iclass 33, count 0 2006.238.08:14:18.63#ibcon#about to read 5, iclass 33, count 0 2006.238.08:14:18.63#ibcon#read 5, iclass 33, count 0 2006.238.08:14:18.63#ibcon#about to read 6, iclass 33, count 0 2006.238.08:14:18.63#ibcon#read 6, iclass 33, count 0 2006.238.08:14:18.63#ibcon#end of sib2, iclass 33, count 0 2006.238.08:14:18.63#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:14:18.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:14:18.63#ibcon#[25=USB\r\n] 2006.238.08:14:18.63#ibcon#*before write, iclass 33, count 0 2006.238.08:14:18.63#ibcon#enter sib2, iclass 33, count 0 2006.238.08:14:18.63#ibcon#flushed, iclass 33, count 0 2006.238.08:14:18.63#ibcon#about to write, iclass 33, count 0 2006.238.08:14:18.63#ibcon#wrote, iclass 33, count 0 2006.238.08:14:18.63#ibcon#about to read 3, iclass 33, count 0 2006.238.08:14:18.66#ibcon#read 3, iclass 33, count 0 2006.238.08:14:18.66#ibcon#about to read 4, iclass 33, count 0 2006.238.08:14:18.66#ibcon#read 4, iclass 33, count 0 2006.238.08:14:18.66#ibcon#about to read 5, iclass 33, count 0 2006.238.08:14:18.66#ibcon#read 5, iclass 33, count 0 2006.238.08:14:18.66#ibcon#about to read 6, iclass 33, count 0 2006.238.08:14:18.66#ibcon#read 6, iclass 33, count 0 2006.238.08:14:18.66#ibcon#end of sib2, iclass 33, count 0 2006.238.08:14:18.66#ibcon#*after write, iclass 33, count 0 2006.238.08:14:18.66#ibcon#*before return 0, iclass 33, count 0 2006.238.08:14:18.66#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:14:18.66#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:14:18.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:14:18.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:14:18.66$vc4f8/valo=3,672.99 2006.238.08:14:18.66#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.08:14:18.66#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.08:14:18.66#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:18.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:14:18.66#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:14:18.66#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:14:18.66#ibcon#enter wrdev, iclass 35, count 0 2006.238.08:14:18.66#ibcon#first serial, iclass 35, count 0 2006.238.08:14:18.66#ibcon#enter sib2, iclass 35, count 0 2006.238.08:14:18.66#ibcon#flushed, iclass 35, count 0 2006.238.08:14:18.66#ibcon#about to write, iclass 35, count 0 2006.238.08:14:18.66#ibcon#wrote, iclass 35, count 0 2006.238.08:14:18.66#ibcon#about to read 3, iclass 35, count 0 2006.238.08:14:18.68#ibcon#read 3, iclass 35, count 0 2006.238.08:14:18.68#ibcon#about to read 4, iclass 35, count 0 2006.238.08:14:18.68#ibcon#read 4, iclass 35, count 0 2006.238.08:14:18.68#ibcon#about to read 5, iclass 35, count 0 2006.238.08:14:18.68#ibcon#read 5, iclass 35, count 0 2006.238.08:14:18.68#ibcon#about to read 6, iclass 35, count 0 2006.238.08:14:18.68#ibcon#read 6, iclass 35, count 0 2006.238.08:14:18.68#ibcon#end of sib2, iclass 35, count 0 2006.238.08:14:18.68#ibcon#*mode == 0, iclass 35, count 0 2006.238.08:14:18.68#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.08:14:18.68#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:14:18.68#ibcon#*before write, iclass 35, count 0 2006.238.08:14:18.68#ibcon#enter sib2, iclass 35, count 0 2006.238.08:14:18.68#ibcon#flushed, iclass 35, count 0 2006.238.08:14:18.68#ibcon#about to write, iclass 35, count 0 2006.238.08:14:18.68#ibcon#wrote, iclass 35, count 0 2006.238.08:14:18.68#ibcon#about to read 3, iclass 35, count 0 2006.238.08:14:18.72#ibcon#read 3, iclass 35, count 0 2006.238.08:14:18.72#ibcon#about to read 4, iclass 35, count 0 2006.238.08:14:18.72#ibcon#read 4, iclass 35, count 0 2006.238.08:14:18.72#ibcon#about to read 5, iclass 35, count 0 2006.238.08:14:18.72#ibcon#read 5, iclass 35, count 0 2006.238.08:14:18.72#ibcon#about to read 6, iclass 35, count 0 2006.238.08:14:18.72#ibcon#read 6, iclass 35, count 0 2006.238.08:14:18.72#ibcon#end of sib2, iclass 35, count 0 2006.238.08:14:18.72#ibcon#*after write, iclass 35, count 0 2006.238.08:14:18.72#ibcon#*before return 0, iclass 35, count 0 2006.238.08:14:18.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:14:18.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:14:18.72#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.08:14:18.72#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.08:14:18.72$vc4f8/va=3,7 2006.238.08:14:18.72#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.08:14:18.72#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.08:14:18.72#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:18.72#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:14:18.78#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:14:18.78#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:14:18.78#ibcon#enter wrdev, iclass 37, count 2 2006.238.08:14:18.78#ibcon#first serial, iclass 37, count 2 2006.238.08:14:18.78#ibcon#enter sib2, iclass 37, count 2 2006.238.08:14:18.78#ibcon#flushed, iclass 37, count 2 2006.238.08:14:18.78#ibcon#about to write, iclass 37, count 2 2006.238.08:14:18.78#ibcon#wrote, iclass 37, count 2 2006.238.08:14:18.78#ibcon#about to read 3, iclass 37, count 2 2006.238.08:14:18.80#ibcon#read 3, iclass 37, count 2 2006.238.08:14:18.80#ibcon#about to read 4, iclass 37, count 2 2006.238.08:14:18.80#ibcon#read 4, iclass 37, count 2 2006.238.08:14:18.80#ibcon#about to read 5, iclass 37, count 2 2006.238.08:14:18.80#ibcon#read 5, iclass 37, count 2 2006.238.08:14:18.80#ibcon#about to read 6, iclass 37, count 2 2006.238.08:14:18.80#ibcon#read 6, iclass 37, count 2 2006.238.08:14:18.80#ibcon#end of sib2, iclass 37, count 2 2006.238.08:14:18.80#ibcon#*mode == 0, iclass 37, count 2 2006.238.08:14:18.80#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.08:14:18.80#ibcon#[25=AT03-07\r\n] 2006.238.08:14:18.80#ibcon#*before write, iclass 37, count 2 2006.238.08:14:18.80#ibcon#enter sib2, iclass 37, count 2 2006.238.08:14:18.80#ibcon#flushed, iclass 37, count 2 2006.238.08:14:18.80#ibcon#about to write, iclass 37, count 2 2006.238.08:14:18.80#ibcon#wrote, iclass 37, count 2 2006.238.08:14:18.80#ibcon#about to read 3, iclass 37, count 2 2006.238.08:14:18.83#ibcon#read 3, iclass 37, count 2 2006.238.08:14:18.83#ibcon#about to read 4, iclass 37, count 2 2006.238.08:14:18.83#ibcon#read 4, iclass 37, count 2 2006.238.08:14:18.83#ibcon#about to read 5, iclass 37, count 2 2006.238.08:14:18.83#ibcon#read 5, iclass 37, count 2 2006.238.08:14:18.83#ibcon#about to read 6, iclass 37, count 2 2006.238.08:14:18.83#ibcon#read 6, iclass 37, count 2 2006.238.08:14:18.83#ibcon#end of sib2, iclass 37, count 2 2006.238.08:14:18.83#ibcon#*after write, iclass 37, count 2 2006.238.08:14:18.83#ibcon#*before return 0, iclass 37, count 2 2006.238.08:14:18.83#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:14:18.83#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:14:18.83#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.08:14:18.83#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:18.83#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:14:18.95#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:14:18.95#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:14:18.95#ibcon#enter wrdev, iclass 37, count 0 2006.238.08:14:18.95#ibcon#first serial, iclass 37, count 0 2006.238.08:14:18.95#ibcon#enter sib2, iclass 37, count 0 2006.238.08:14:18.95#ibcon#flushed, iclass 37, count 0 2006.238.08:14:18.95#ibcon#about to write, iclass 37, count 0 2006.238.08:14:18.95#ibcon#wrote, iclass 37, count 0 2006.238.08:14:18.95#ibcon#about to read 3, iclass 37, count 0 2006.238.08:14:18.97#ibcon#read 3, iclass 37, count 0 2006.238.08:14:18.97#ibcon#about to read 4, iclass 37, count 0 2006.238.08:14:18.97#ibcon#read 4, iclass 37, count 0 2006.238.08:14:18.97#ibcon#about to read 5, iclass 37, count 0 2006.238.08:14:18.97#ibcon#read 5, iclass 37, count 0 2006.238.08:14:18.97#ibcon#about to read 6, iclass 37, count 0 2006.238.08:14:18.97#ibcon#read 6, iclass 37, count 0 2006.238.08:14:18.97#ibcon#end of sib2, iclass 37, count 0 2006.238.08:14:18.97#ibcon#*mode == 0, iclass 37, count 0 2006.238.08:14:18.97#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.08:14:18.97#ibcon#[25=USB\r\n] 2006.238.08:14:18.97#ibcon#*before write, iclass 37, count 0 2006.238.08:14:18.97#ibcon#enter sib2, iclass 37, count 0 2006.238.08:14:18.97#ibcon#flushed, iclass 37, count 0 2006.238.08:14:18.97#ibcon#about to write, iclass 37, count 0 2006.238.08:14:18.97#ibcon#wrote, iclass 37, count 0 2006.238.08:14:18.97#ibcon#about to read 3, iclass 37, count 0 2006.238.08:14:19.00#ibcon#read 3, iclass 37, count 0 2006.238.08:14:19.00#ibcon#about to read 4, iclass 37, count 0 2006.238.08:14:19.00#ibcon#read 4, iclass 37, count 0 2006.238.08:14:19.00#ibcon#about to read 5, iclass 37, count 0 2006.238.08:14:19.00#ibcon#read 5, iclass 37, count 0 2006.238.08:14:19.00#ibcon#about to read 6, iclass 37, count 0 2006.238.08:14:19.00#ibcon#read 6, iclass 37, count 0 2006.238.08:14:19.00#ibcon#end of sib2, iclass 37, count 0 2006.238.08:14:19.00#ibcon#*after write, iclass 37, count 0 2006.238.08:14:19.00#ibcon#*before return 0, iclass 37, count 0 2006.238.08:14:19.00#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:14:19.00#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:14:19.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.08:14:19.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.08:14:19.00$vc4f8/valo=4,832.99 2006.238.08:14:19.00#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.08:14:19.00#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.08:14:19.00#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:19.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:14:19.00#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:14:19.00#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:14:19.00#ibcon#enter wrdev, iclass 39, count 0 2006.238.08:14:19.00#ibcon#first serial, iclass 39, count 0 2006.238.08:14:19.00#ibcon#enter sib2, iclass 39, count 0 2006.238.08:14:19.00#ibcon#flushed, iclass 39, count 0 2006.238.08:14:19.00#ibcon#about to write, iclass 39, count 0 2006.238.08:14:19.00#ibcon#wrote, iclass 39, count 0 2006.238.08:14:19.00#ibcon#about to read 3, iclass 39, count 0 2006.238.08:14:19.02#ibcon#read 3, iclass 39, count 0 2006.238.08:14:19.02#ibcon#about to read 4, iclass 39, count 0 2006.238.08:14:19.02#ibcon#read 4, iclass 39, count 0 2006.238.08:14:19.02#ibcon#about to read 5, iclass 39, count 0 2006.238.08:14:19.02#ibcon#read 5, iclass 39, count 0 2006.238.08:14:19.02#ibcon#about to read 6, iclass 39, count 0 2006.238.08:14:19.02#ibcon#read 6, iclass 39, count 0 2006.238.08:14:19.02#ibcon#end of sib2, iclass 39, count 0 2006.238.08:14:19.02#ibcon#*mode == 0, iclass 39, count 0 2006.238.08:14:19.02#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.08:14:19.02#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:14:19.02#ibcon#*before write, iclass 39, count 0 2006.238.08:14:19.02#ibcon#enter sib2, iclass 39, count 0 2006.238.08:14:19.02#ibcon#flushed, iclass 39, count 0 2006.238.08:14:19.02#ibcon#about to write, iclass 39, count 0 2006.238.08:14:19.02#ibcon#wrote, iclass 39, count 0 2006.238.08:14:19.02#ibcon#about to read 3, iclass 39, count 0 2006.238.08:14:19.06#ibcon#read 3, iclass 39, count 0 2006.238.08:14:19.06#ibcon#about to read 4, iclass 39, count 0 2006.238.08:14:19.06#ibcon#read 4, iclass 39, count 0 2006.238.08:14:19.06#ibcon#about to read 5, iclass 39, count 0 2006.238.08:14:19.06#ibcon#read 5, iclass 39, count 0 2006.238.08:14:19.06#ibcon#about to read 6, iclass 39, count 0 2006.238.08:14:19.06#ibcon#read 6, iclass 39, count 0 2006.238.08:14:19.06#ibcon#end of sib2, iclass 39, count 0 2006.238.08:14:19.06#ibcon#*after write, iclass 39, count 0 2006.238.08:14:19.06#ibcon#*before return 0, iclass 39, count 0 2006.238.08:14:19.06#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:14:19.06#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:14:19.06#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.08:14:19.06#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.08:14:19.06$vc4f8/va=4,7 2006.238.08:14:19.06#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.08:14:19.06#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.08:14:19.06#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:19.06#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:14:19.12#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:14:19.12#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:14:19.12#ibcon#enter wrdev, iclass 3, count 2 2006.238.08:14:19.12#ibcon#first serial, iclass 3, count 2 2006.238.08:14:19.12#ibcon#enter sib2, iclass 3, count 2 2006.238.08:14:19.12#ibcon#flushed, iclass 3, count 2 2006.238.08:14:19.12#ibcon#about to write, iclass 3, count 2 2006.238.08:14:19.12#ibcon#wrote, iclass 3, count 2 2006.238.08:14:19.12#ibcon#about to read 3, iclass 3, count 2 2006.238.08:14:19.14#ibcon#read 3, iclass 3, count 2 2006.238.08:14:19.14#ibcon#about to read 4, iclass 3, count 2 2006.238.08:14:19.14#ibcon#read 4, iclass 3, count 2 2006.238.08:14:19.14#ibcon#about to read 5, iclass 3, count 2 2006.238.08:14:19.14#ibcon#read 5, iclass 3, count 2 2006.238.08:14:19.14#ibcon#about to read 6, iclass 3, count 2 2006.238.08:14:19.14#ibcon#read 6, iclass 3, count 2 2006.238.08:14:19.14#ibcon#end of sib2, iclass 3, count 2 2006.238.08:14:19.14#ibcon#*mode == 0, iclass 3, count 2 2006.238.08:14:19.14#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.08:14:19.14#ibcon#[25=AT04-07\r\n] 2006.238.08:14:19.14#ibcon#*before write, iclass 3, count 2 2006.238.08:14:19.14#ibcon#enter sib2, iclass 3, count 2 2006.238.08:14:19.14#ibcon#flushed, iclass 3, count 2 2006.238.08:14:19.14#ibcon#about to write, iclass 3, count 2 2006.238.08:14:19.14#ibcon#wrote, iclass 3, count 2 2006.238.08:14:19.14#ibcon#about to read 3, iclass 3, count 2 2006.238.08:14:19.17#ibcon#read 3, iclass 3, count 2 2006.238.08:14:19.17#ibcon#about to read 4, iclass 3, count 2 2006.238.08:14:19.17#ibcon#read 4, iclass 3, count 2 2006.238.08:14:19.17#ibcon#about to read 5, iclass 3, count 2 2006.238.08:14:19.17#ibcon#read 5, iclass 3, count 2 2006.238.08:14:19.17#ibcon#about to read 6, iclass 3, count 2 2006.238.08:14:19.17#ibcon#read 6, iclass 3, count 2 2006.238.08:14:19.17#ibcon#end of sib2, iclass 3, count 2 2006.238.08:14:19.17#ibcon#*after write, iclass 3, count 2 2006.238.08:14:19.17#ibcon#*before return 0, iclass 3, count 2 2006.238.08:14:19.17#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:14:19.17#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:14:19.17#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.08:14:19.17#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:19.17#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:14:19.29#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:14:19.29#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:14:19.29#ibcon#enter wrdev, iclass 3, count 0 2006.238.08:14:19.29#ibcon#first serial, iclass 3, count 0 2006.238.08:14:19.29#ibcon#enter sib2, iclass 3, count 0 2006.238.08:14:19.29#ibcon#flushed, iclass 3, count 0 2006.238.08:14:19.29#ibcon#about to write, iclass 3, count 0 2006.238.08:14:19.29#ibcon#wrote, iclass 3, count 0 2006.238.08:14:19.29#ibcon#about to read 3, iclass 3, count 0 2006.238.08:14:19.31#ibcon#read 3, iclass 3, count 0 2006.238.08:14:19.31#ibcon#about to read 4, iclass 3, count 0 2006.238.08:14:19.31#ibcon#read 4, iclass 3, count 0 2006.238.08:14:19.31#ibcon#about to read 5, iclass 3, count 0 2006.238.08:14:19.31#ibcon#read 5, iclass 3, count 0 2006.238.08:14:19.31#ibcon#about to read 6, iclass 3, count 0 2006.238.08:14:19.31#ibcon#read 6, iclass 3, count 0 2006.238.08:14:19.31#ibcon#end of sib2, iclass 3, count 0 2006.238.08:14:19.31#ibcon#*mode == 0, iclass 3, count 0 2006.238.08:14:19.31#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.08:14:19.31#ibcon#[25=USB\r\n] 2006.238.08:14:19.31#ibcon#*before write, iclass 3, count 0 2006.238.08:14:19.31#ibcon#enter sib2, iclass 3, count 0 2006.238.08:14:19.31#ibcon#flushed, iclass 3, count 0 2006.238.08:14:19.31#ibcon#about to write, iclass 3, count 0 2006.238.08:14:19.31#ibcon#wrote, iclass 3, count 0 2006.238.08:14:19.31#ibcon#about to read 3, iclass 3, count 0 2006.238.08:14:19.34#ibcon#read 3, iclass 3, count 0 2006.238.08:14:19.34#ibcon#about to read 4, iclass 3, count 0 2006.238.08:14:19.34#ibcon#read 4, iclass 3, count 0 2006.238.08:14:19.34#ibcon#about to read 5, iclass 3, count 0 2006.238.08:14:19.34#ibcon#read 5, iclass 3, count 0 2006.238.08:14:19.34#ibcon#about to read 6, iclass 3, count 0 2006.238.08:14:19.34#ibcon#read 6, iclass 3, count 0 2006.238.08:14:19.34#ibcon#end of sib2, iclass 3, count 0 2006.238.08:14:19.34#ibcon#*after write, iclass 3, count 0 2006.238.08:14:19.34#ibcon#*before return 0, iclass 3, count 0 2006.238.08:14:19.34#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:14:19.34#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:14:19.34#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.08:14:19.34#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.08:14:19.34$vc4f8/valo=5,652.99 2006.238.08:14:19.34#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.08:14:19.34#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.08:14:19.34#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:19.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:14:19.34#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:14:19.34#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:14:19.34#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:14:19.34#ibcon#first serial, iclass 5, count 0 2006.238.08:14:19.34#ibcon#enter sib2, iclass 5, count 0 2006.238.08:14:19.34#ibcon#flushed, iclass 5, count 0 2006.238.08:14:19.34#ibcon#about to write, iclass 5, count 0 2006.238.08:14:19.34#ibcon#wrote, iclass 5, count 0 2006.238.08:14:19.34#ibcon#about to read 3, iclass 5, count 0 2006.238.08:14:19.36#ibcon#read 3, iclass 5, count 0 2006.238.08:14:19.36#ibcon#about to read 4, iclass 5, count 0 2006.238.08:14:19.36#ibcon#read 4, iclass 5, count 0 2006.238.08:14:19.36#ibcon#about to read 5, iclass 5, count 0 2006.238.08:14:19.36#ibcon#read 5, iclass 5, count 0 2006.238.08:14:19.36#ibcon#about to read 6, iclass 5, count 0 2006.238.08:14:19.36#ibcon#read 6, iclass 5, count 0 2006.238.08:14:19.36#ibcon#end of sib2, iclass 5, count 0 2006.238.08:14:19.36#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:14:19.36#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:14:19.36#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:14:19.36#ibcon#*before write, iclass 5, count 0 2006.238.08:14:19.36#ibcon#enter sib2, iclass 5, count 0 2006.238.08:14:19.36#ibcon#flushed, iclass 5, count 0 2006.238.08:14:19.36#ibcon#about to write, iclass 5, count 0 2006.238.08:14:19.36#ibcon#wrote, iclass 5, count 0 2006.238.08:14:19.36#ibcon#about to read 3, iclass 5, count 0 2006.238.08:14:19.40#ibcon#read 3, iclass 5, count 0 2006.238.08:14:19.40#ibcon#about to read 4, iclass 5, count 0 2006.238.08:14:19.40#ibcon#read 4, iclass 5, count 0 2006.238.08:14:19.40#ibcon#about to read 5, iclass 5, count 0 2006.238.08:14:19.40#ibcon#read 5, iclass 5, count 0 2006.238.08:14:19.40#ibcon#about to read 6, iclass 5, count 0 2006.238.08:14:19.40#ibcon#read 6, iclass 5, count 0 2006.238.08:14:19.40#ibcon#end of sib2, iclass 5, count 0 2006.238.08:14:19.40#ibcon#*after write, iclass 5, count 0 2006.238.08:14:19.40#ibcon#*before return 0, iclass 5, count 0 2006.238.08:14:19.40#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:14:19.40#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:14:19.40#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:14:19.40#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:14:19.40$vc4f8/va=5,8 2006.238.08:14:19.40#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.08:14:19.40#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.08:14:19.40#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:19.40#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:14:19.46#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:14:19.46#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:14:19.46#ibcon#enter wrdev, iclass 7, count 2 2006.238.08:14:19.46#ibcon#first serial, iclass 7, count 2 2006.238.08:14:19.46#ibcon#enter sib2, iclass 7, count 2 2006.238.08:14:19.46#ibcon#flushed, iclass 7, count 2 2006.238.08:14:19.46#ibcon#about to write, iclass 7, count 2 2006.238.08:14:19.46#ibcon#wrote, iclass 7, count 2 2006.238.08:14:19.46#ibcon#about to read 3, iclass 7, count 2 2006.238.08:14:19.48#ibcon#read 3, iclass 7, count 2 2006.238.08:14:19.48#ibcon#about to read 4, iclass 7, count 2 2006.238.08:14:19.48#ibcon#read 4, iclass 7, count 2 2006.238.08:14:19.48#ibcon#about to read 5, iclass 7, count 2 2006.238.08:14:19.48#ibcon#read 5, iclass 7, count 2 2006.238.08:14:19.48#ibcon#about to read 6, iclass 7, count 2 2006.238.08:14:19.48#ibcon#read 6, iclass 7, count 2 2006.238.08:14:19.48#ibcon#end of sib2, iclass 7, count 2 2006.238.08:14:19.48#ibcon#*mode == 0, iclass 7, count 2 2006.238.08:14:19.48#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.08:14:19.48#ibcon#[25=AT05-08\r\n] 2006.238.08:14:19.48#ibcon#*before write, iclass 7, count 2 2006.238.08:14:19.48#ibcon#enter sib2, iclass 7, count 2 2006.238.08:14:19.48#ibcon#flushed, iclass 7, count 2 2006.238.08:14:19.48#ibcon#about to write, iclass 7, count 2 2006.238.08:14:19.48#ibcon#wrote, iclass 7, count 2 2006.238.08:14:19.48#ibcon#about to read 3, iclass 7, count 2 2006.238.08:14:19.51#ibcon#read 3, iclass 7, count 2 2006.238.08:14:19.51#ibcon#about to read 4, iclass 7, count 2 2006.238.08:14:19.51#ibcon#read 4, iclass 7, count 2 2006.238.08:14:19.51#ibcon#about to read 5, iclass 7, count 2 2006.238.08:14:19.51#ibcon#read 5, iclass 7, count 2 2006.238.08:14:19.51#ibcon#about to read 6, iclass 7, count 2 2006.238.08:14:19.51#ibcon#read 6, iclass 7, count 2 2006.238.08:14:19.51#ibcon#end of sib2, iclass 7, count 2 2006.238.08:14:19.51#ibcon#*after write, iclass 7, count 2 2006.238.08:14:19.51#ibcon#*before return 0, iclass 7, count 2 2006.238.08:14:19.51#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:14:19.51#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:14:19.51#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.08:14:19.51#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:19.51#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:14:19.63#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:14:19.63#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:14:19.63#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:14:19.63#ibcon#first serial, iclass 7, count 0 2006.238.08:14:19.63#ibcon#enter sib2, iclass 7, count 0 2006.238.08:14:19.63#ibcon#flushed, iclass 7, count 0 2006.238.08:14:19.63#ibcon#about to write, iclass 7, count 0 2006.238.08:14:19.63#ibcon#wrote, iclass 7, count 0 2006.238.08:14:19.63#ibcon#about to read 3, iclass 7, count 0 2006.238.08:14:19.65#ibcon#read 3, iclass 7, count 0 2006.238.08:14:19.65#ibcon#about to read 4, iclass 7, count 0 2006.238.08:14:19.65#ibcon#read 4, iclass 7, count 0 2006.238.08:14:19.65#ibcon#about to read 5, iclass 7, count 0 2006.238.08:14:19.65#ibcon#read 5, iclass 7, count 0 2006.238.08:14:19.65#ibcon#about to read 6, iclass 7, count 0 2006.238.08:14:19.65#ibcon#read 6, iclass 7, count 0 2006.238.08:14:19.65#ibcon#end of sib2, iclass 7, count 0 2006.238.08:14:19.65#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:14:19.65#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:14:19.65#ibcon#[25=USB\r\n] 2006.238.08:14:19.65#ibcon#*before write, iclass 7, count 0 2006.238.08:14:19.65#ibcon#enter sib2, iclass 7, count 0 2006.238.08:14:19.65#ibcon#flushed, iclass 7, count 0 2006.238.08:14:19.65#ibcon#about to write, iclass 7, count 0 2006.238.08:14:19.65#ibcon#wrote, iclass 7, count 0 2006.238.08:14:19.65#ibcon#about to read 3, iclass 7, count 0 2006.238.08:14:19.68#ibcon#read 3, iclass 7, count 0 2006.238.08:14:19.68#ibcon#about to read 4, iclass 7, count 0 2006.238.08:14:19.68#ibcon#read 4, iclass 7, count 0 2006.238.08:14:19.68#ibcon#about to read 5, iclass 7, count 0 2006.238.08:14:19.68#ibcon#read 5, iclass 7, count 0 2006.238.08:14:19.68#ibcon#about to read 6, iclass 7, count 0 2006.238.08:14:19.68#ibcon#read 6, iclass 7, count 0 2006.238.08:14:19.68#ibcon#end of sib2, iclass 7, count 0 2006.238.08:14:19.68#ibcon#*after write, iclass 7, count 0 2006.238.08:14:19.68#ibcon#*before return 0, iclass 7, count 0 2006.238.08:14:19.68#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:14:19.68#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:14:19.68#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:14:19.68#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:14:19.68$vc4f8/valo=6,772.99 2006.238.08:14:19.68#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.08:14:19.68#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.08:14:19.68#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:19.68#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:14:19.68#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:14:19.68#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:14:19.68#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:14:19.68#ibcon#first serial, iclass 11, count 0 2006.238.08:14:19.68#ibcon#enter sib2, iclass 11, count 0 2006.238.08:14:19.68#ibcon#flushed, iclass 11, count 0 2006.238.08:14:19.68#ibcon#about to write, iclass 11, count 0 2006.238.08:14:19.68#ibcon#wrote, iclass 11, count 0 2006.238.08:14:19.68#ibcon#about to read 3, iclass 11, count 0 2006.238.08:14:19.70#ibcon#read 3, iclass 11, count 0 2006.238.08:14:19.70#ibcon#about to read 4, iclass 11, count 0 2006.238.08:14:19.70#ibcon#read 4, iclass 11, count 0 2006.238.08:14:19.70#ibcon#about to read 5, iclass 11, count 0 2006.238.08:14:19.70#ibcon#read 5, iclass 11, count 0 2006.238.08:14:19.70#ibcon#about to read 6, iclass 11, count 0 2006.238.08:14:19.70#ibcon#read 6, iclass 11, count 0 2006.238.08:14:19.70#ibcon#end of sib2, iclass 11, count 0 2006.238.08:14:19.70#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:14:19.70#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:14:19.70#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:14:19.70#ibcon#*before write, iclass 11, count 0 2006.238.08:14:19.70#ibcon#enter sib2, iclass 11, count 0 2006.238.08:14:19.70#ibcon#flushed, iclass 11, count 0 2006.238.08:14:19.70#ibcon#about to write, iclass 11, count 0 2006.238.08:14:19.70#ibcon#wrote, iclass 11, count 0 2006.238.08:14:19.70#ibcon#about to read 3, iclass 11, count 0 2006.238.08:14:19.74#ibcon#read 3, iclass 11, count 0 2006.238.08:14:19.74#ibcon#about to read 4, iclass 11, count 0 2006.238.08:14:19.74#ibcon#read 4, iclass 11, count 0 2006.238.08:14:19.74#ibcon#about to read 5, iclass 11, count 0 2006.238.08:14:19.74#ibcon#read 5, iclass 11, count 0 2006.238.08:14:19.74#ibcon#about to read 6, iclass 11, count 0 2006.238.08:14:19.74#ibcon#read 6, iclass 11, count 0 2006.238.08:14:19.74#ibcon#end of sib2, iclass 11, count 0 2006.238.08:14:19.74#ibcon#*after write, iclass 11, count 0 2006.238.08:14:19.74#ibcon#*before return 0, iclass 11, count 0 2006.238.08:14:19.74#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:14:19.74#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:14:19.74#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:14:19.74#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:14:19.74$vc4f8/va=6,7 2006.238.08:14:19.74#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.08:14:19.74#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.08:14:19.74#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:19.74#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:14:19.80#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:14:19.80#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:14:19.80#ibcon#enter wrdev, iclass 13, count 2 2006.238.08:14:19.80#ibcon#first serial, iclass 13, count 2 2006.238.08:14:19.80#ibcon#enter sib2, iclass 13, count 2 2006.238.08:14:19.80#ibcon#flushed, iclass 13, count 2 2006.238.08:14:19.80#ibcon#about to write, iclass 13, count 2 2006.238.08:14:19.80#ibcon#wrote, iclass 13, count 2 2006.238.08:14:19.80#ibcon#about to read 3, iclass 13, count 2 2006.238.08:14:19.82#ibcon#read 3, iclass 13, count 2 2006.238.08:14:19.82#ibcon#about to read 4, iclass 13, count 2 2006.238.08:14:19.82#ibcon#read 4, iclass 13, count 2 2006.238.08:14:19.82#ibcon#about to read 5, iclass 13, count 2 2006.238.08:14:19.82#ibcon#read 5, iclass 13, count 2 2006.238.08:14:19.82#ibcon#about to read 6, iclass 13, count 2 2006.238.08:14:19.82#ibcon#read 6, iclass 13, count 2 2006.238.08:14:19.82#ibcon#end of sib2, iclass 13, count 2 2006.238.08:14:19.82#ibcon#*mode == 0, iclass 13, count 2 2006.238.08:14:19.82#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.08:14:19.82#ibcon#[25=AT06-07\r\n] 2006.238.08:14:19.82#ibcon#*before write, iclass 13, count 2 2006.238.08:14:19.82#ibcon#enter sib2, iclass 13, count 2 2006.238.08:14:19.82#ibcon#flushed, iclass 13, count 2 2006.238.08:14:19.82#ibcon#about to write, iclass 13, count 2 2006.238.08:14:19.82#ibcon#wrote, iclass 13, count 2 2006.238.08:14:19.82#ibcon#about to read 3, iclass 13, count 2 2006.238.08:14:19.85#ibcon#read 3, iclass 13, count 2 2006.238.08:14:19.85#ibcon#about to read 4, iclass 13, count 2 2006.238.08:14:19.85#ibcon#read 4, iclass 13, count 2 2006.238.08:14:19.85#ibcon#about to read 5, iclass 13, count 2 2006.238.08:14:19.85#ibcon#read 5, iclass 13, count 2 2006.238.08:14:19.85#ibcon#about to read 6, iclass 13, count 2 2006.238.08:14:19.85#ibcon#read 6, iclass 13, count 2 2006.238.08:14:19.85#ibcon#end of sib2, iclass 13, count 2 2006.238.08:14:19.85#ibcon#*after write, iclass 13, count 2 2006.238.08:14:19.85#ibcon#*before return 0, iclass 13, count 2 2006.238.08:14:19.85#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:14:19.85#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:14:19.85#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.08:14:19.85#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:19.85#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:14:19.97#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:14:19.97#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:14:19.97#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:14:19.97#ibcon#first serial, iclass 13, count 0 2006.238.08:14:19.97#ibcon#enter sib2, iclass 13, count 0 2006.238.08:14:19.97#ibcon#flushed, iclass 13, count 0 2006.238.08:14:19.97#ibcon#about to write, iclass 13, count 0 2006.238.08:14:19.97#ibcon#wrote, iclass 13, count 0 2006.238.08:14:19.97#ibcon#about to read 3, iclass 13, count 0 2006.238.08:14:19.99#ibcon#read 3, iclass 13, count 0 2006.238.08:14:19.99#ibcon#about to read 4, iclass 13, count 0 2006.238.08:14:19.99#ibcon#read 4, iclass 13, count 0 2006.238.08:14:19.99#ibcon#about to read 5, iclass 13, count 0 2006.238.08:14:19.99#ibcon#read 5, iclass 13, count 0 2006.238.08:14:19.99#ibcon#about to read 6, iclass 13, count 0 2006.238.08:14:19.99#ibcon#read 6, iclass 13, count 0 2006.238.08:14:19.99#ibcon#end of sib2, iclass 13, count 0 2006.238.08:14:19.99#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:14:19.99#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:14:19.99#ibcon#[25=USB\r\n] 2006.238.08:14:19.99#ibcon#*before write, iclass 13, count 0 2006.238.08:14:19.99#ibcon#enter sib2, iclass 13, count 0 2006.238.08:14:19.99#ibcon#flushed, iclass 13, count 0 2006.238.08:14:19.99#ibcon#about to write, iclass 13, count 0 2006.238.08:14:19.99#ibcon#wrote, iclass 13, count 0 2006.238.08:14:19.99#ibcon#about to read 3, iclass 13, count 0 2006.238.08:14:20.02#ibcon#read 3, iclass 13, count 0 2006.238.08:14:20.02#ibcon#about to read 4, iclass 13, count 0 2006.238.08:14:20.02#ibcon#read 4, iclass 13, count 0 2006.238.08:14:20.02#ibcon#about to read 5, iclass 13, count 0 2006.238.08:14:20.02#ibcon#read 5, iclass 13, count 0 2006.238.08:14:20.02#ibcon#about to read 6, iclass 13, count 0 2006.238.08:14:20.02#ibcon#read 6, iclass 13, count 0 2006.238.08:14:20.02#ibcon#end of sib2, iclass 13, count 0 2006.238.08:14:20.02#ibcon#*after write, iclass 13, count 0 2006.238.08:14:20.02#ibcon#*before return 0, iclass 13, count 0 2006.238.08:14:20.02#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:14:20.02#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:14:20.02#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:14:20.02#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:14:20.02$vc4f8/valo=7,832.99 2006.238.08:14:20.02#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.08:14:20.02#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.08:14:20.02#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:20.02#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:14:20.02#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:14:20.02#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:14:20.02#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:14:20.02#ibcon#first serial, iclass 15, count 0 2006.238.08:14:20.02#ibcon#enter sib2, iclass 15, count 0 2006.238.08:14:20.02#ibcon#flushed, iclass 15, count 0 2006.238.08:14:20.02#ibcon#about to write, iclass 15, count 0 2006.238.08:14:20.02#ibcon#wrote, iclass 15, count 0 2006.238.08:14:20.02#ibcon#about to read 3, iclass 15, count 0 2006.238.08:14:20.04#ibcon#read 3, iclass 15, count 0 2006.238.08:14:20.04#ibcon#about to read 4, iclass 15, count 0 2006.238.08:14:20.04#ibcon#read 4, iclass 15, count 0 2006.238.08:14:20.04#ibcon#about to read 5, iclass 15, count 0 2006.238.08:14:20.04#ibcon#read 5, iclass 15, count 0 2006.238.08:14:20.04#ibcon#about to read 6, iclass 15, count 0 2006.238.08:14:20.04#ibcon#read 6, iclass 15, count 0 2006.238.08:14:20.04#ibcon#end of sib2, iclass 15, count 0 2006.238.08:14:20.04#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:14:20.04#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:14:20.04#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:14:20.04#ibcon#*before write, iclass 15, count 0 2006.238.08:14:20.04#ibcon#enter sib2, iclass 15, count 0 2006.238.08:14:20.04#ibcon#flushed, iclass 15, count 0 2006.238.08:14:20.04#ibcon#about to write, iclass 15, count 0 2006.238.08:14:20.04#ibcon#wrote, iclass 15, count 0 2006.238.08:14:20.04#ibcon#about to read 3, iclass 15, count 0 2006.238.08:14:20.08#ibcon#read 3, iclass 15, count 0 2006.238.08:14:20.08#ibcon#about to read 4, iclass 15, count 0 2006.238.08:14:20.08#ibcon#read 4, iclass 15, count 0 2006.238.08:14:20.08#ibcon#about to read 5, iclass 15, count 0 2006.238.08:14:20.08#ibcon#read 5, iclass 15, count 0 2006.238.08:14:20.08#ibcon#about to read 6, iclass 15, count 0 2006.238.08:14:20.08#ibcon#read 6, iclass 15, count 0 2006.238.08:14:20.08#ibcon#end of sib2, iclass 15, count 0 2006.238.08:14:20.08#ibcon#*after write, iclass 15, count 0 2006.238.08:14:20.08#ibcon#*before return 0, iclass 15, count 0 2006.238.08:14:20.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:14:20.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:14:20.08#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:14:20.08#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:14:20.08$vc4f8/va=7,7 2006.238.08:14:20.08#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.08:14:20.08#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.08:14:20.08#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:20.08#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:14:20.14#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:14:20.14#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:14:20.14#ibcon#enter wrdev, iclass 17, count 2 2006.238.08:14:20.14#ibcon#first serial, iclass 17, count 2 2006.238.08:14:20.14#ibcon#enter sib2, iclass 17, count 2 2006.238.08:14:20.14#ibcon#flushed, iclass 17, count 2 2006.238.08:14:20.14#ibcon#about to write, iclass 17, count 2 2006.238.08:14:20.14#ibcon#wrote, iclass 17, count 2 2006.238.08:14:20.14#ibcon#about to read 3, iclass 17, count 2 2006.238.08:14:20.16#ibcon#read 3, iclass 17, count 2 2006.238.08:14:20.16#ibcon#about to read 4, iclass 17, count 2 2006.238.08:14:20.16#ibcon#read 4, iclass 17, count 2 2006.238.08:14:20.16#ibcon#about to read 5, iclass 17, count 2 2006.238.08:14:20.16#ibcon#read 5, iclass 17, count 2 2006.238.08:14:20.16#ibcon#about to read 6, iclass 17, count 2 2006.238.08:14:20.16#ibcon#read 6, iclass 17, count 2 2006.238.08:14:20.16#ibcon#end of sib2, iclass 17, count 2 2006.238.08:14:20.16#ibcon#*mode == 0, iclass 17, count 2 2006.238.08:14:20.16#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.08:14:20.16#ibcon#[25=AT07-07\r\n] 2006.238.08:14:20.16#ibcon#*before write, iclass 17, count 2 2006.238.08:14:20.16#ibcon#enter sib2, iclass 17, count 2 2006.238.08:14:20.16#ibcon#flushed, iclass 17, count 2 2006.238.08:14:20.16#ibcon#about to write, iclass 17, count 2 2006.238.08:14:20.16#ibcon#wrote, iclass 17, count 2 2006.238.08:14:20.16#ibcon#about to read 3, iclass 17, count 2 2006.238.08:14:20.19#ibcon#read 3, iclass 17, count 2 2006.238.08:14:20.19#ibcon#about to read 4, iclass 17, count 2 2006.238.08:14:20.19#ibcon#read 4, iclass 17, count 2 2006.238.08:14:20.19#ibcon#about to read 5, iclass 17, count 2 2006.238.08:14:20.19#ibcon#read 5, iclass 17, count 2 2006.238.08:14:20.19#ibcon#about to read 6, iclass 17, count 2 2006.238.08:14:20.19#ibcon#read 6, iclass 17, count 2 2006.238.08:14:20.19#ibcon#end of sib2, iclass 17, count 2 2006.238.08:14:20.19#ibcon#*after write, iclass 17, count 2 2006.238.08:14:20.19#ibcon#*before return 0, iclass 17, count 2 2006.238.08:14:20.19#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:14:20.19#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:14:20.19#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.08:14:20.19#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:20.19#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:14:20.31#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:14:20.31#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:14:20.31#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:14:20.31#ibcon#first serial, iclass 17, count 0 2006.238.08:14:20.31#ibcon#enter sib2, iclass 17, count 0 2006.238.08:14:20.31#ibcon#flushed, iclass 17, count 0 2006.238.08:14:20.31#ibcon#about to write, iclass 17, count 0 2006.238.08:14:20.31#ibcon#wrote, iclass 17, count 0 2006.238.08:14:20.31#ibcon#about to read 3, iclass 17, count 0 2006.238.08:14:20.33#ibcon#read 3, iclass 17, count 0 2006.238.08:14:20.33#ibcon#about to read 4, iclass 17, count 0 2006.238.08:14:20.33#ibcon#read 4, iclass 17, count 0 2006.238.08:14:20.33#ibcon#about to read 5, iclass 17, count 0 2006.238.08:14:20.33#ibcon#read 5, iclass 17, count 0 2006.238.08:14:20.33#ibcon#about to read 6, iclass 17, count 0 2006.238.08:14:20.33#ibcon#read 6, iclass 17, count 0 2006.238.08:14:20.33#ibcon#end of sib2, iclass 17, count 0 2006.238.08:14:20.33#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:14:20.33#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:14:20.33#ibcon#[25=USB\r\n] 2006.238.08:14:20.33#ibcon#*before write, iclass 17, count 0 2006.238.08:14:20.33#ibcon#enter sib2, iclass 17, count 0 2006.238.08:14:20.33#ibcon#flushed, iclass 17, count 0 2006.238.08:14:20.33#ibcon#about to write, iclass 17, count 0 2006.238.08:14:20.33#ibcon#wrote, iclass 17, count 0 2006.238.08:14:20.33#ibcon#about to read 3, iclass 17, count 0 2006.238.08:14:20.36#ibcon#read 3, iclass 17, count 0 2006.238.08:14:20.36#ibcon#about to read 4, iclass 17, count 0 2006.238.08:14:20.36#ibcon#read 4, iclass 17, count 0 2006.238.08:14:20.36#ibcon#about to read 5, iclass 17, count 0 2006.238.08:14:20.36#ibcon#read 5, iclass 17, count 0 2006.238.08:14:20.36#ibcon#about to read 6, iclass 17, count 0 2006.238.08:14:20.36#ibcon#read 6, iclass 17, count 0 2006.238.08:14:20.36#ibcon#end of sib2, iclass 17, count 0 2006.238.08:14:20.36#ibcon#*after write, iclass 17, count 0 2006.238.08:14:20.36#ibcon#*before return 0, iclass 17, count 0 2006.238.08:14:20.36#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:14:20.36#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:14:20.36#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:14:20.36#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:14:20.36$vc4f8/valo=8,852.99 2006.238.08:14:20.36#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.08:14:20.36#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.08:14:20.36#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:20.36#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:14:20.36#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:14:20.36#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:14:20.36#ibcon#enter wrdev, iclass 19, count 0 2006.238.08:14:20.36#ibcon#first serial, iclass 19, count 0 2006.238.08:14:20.36#ibcon#enter sib2, iclass 19, count 0 2006.238.08:14:20.36#ibcon#flushed, iclass 19, count 0 2006.238.08:14:20.36#ibcon#about to write, iclass 19, count 0 2006.238.08:14:20.36#ibcon#wrote, iclass 19, count 0 2006.238.08:14:20.36#ibcon#about to read 3, iclass 19, count 0 2006.238.08:14:20.38#ibcon#read 3, iclass 19, count 0 2006.238.08:14:20.38#ibcon#about to read 4, iclass 19, count 0 2006.238.08:14:20.38#ibcon#read 4, iclass 19, count 0 2006.238.08:14:20.38#ibcon#about to read 5, iclass 19, count 0 2006.238.08:14:20.38#ibcon#read 5, iclass 19, count 0 2006.238.08:14:20.38#ibcon#about to read 6, iclass 19, count 0 2006.238.08:14:20.38#ibcon#read 6, iclass 19, count 0 2006.238.08:14:20.38#ibcon#end of sib2, iclass 19, count 0 2006.238.08:14:20.38#ibcon#*mode == 0, iclass 19, count 0 2006.238.08:14:20.38#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.08:14:20.38#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:14:20.38#ibcon#*before write, iclass 19, count 0 2006.238.08:14:20.38#ibcon#enter sib2, iclass 19, count 0 2006.238.08:14:20.38#ibcon#flushed, iclass 19, count 0 2006.238.08:14:20.38#ibcon#about to write, iclass 19, count 0 2006.238.08:14:20.38#ibcon#wrote, iclass 19, count 0 2006.238.08:14:20.38#ibcon#about to read 3, iclass 19, count 0 2006.238.08:14:20.42#ibcon#read 3, iclass 19, count 0 2006.238.08:14:20.42#ibcon#about to read 4, iclass 19, count 0 2006.238.08:14:20.42#ibcon#read 4, iclass 19, count 0 2006.238.08:14:20.42#ibcon#about to read 5, iclass 19, count 0 2006.238.08:14:20.42#ibcon#read 5, iclass 19, count 0 2006.238.08:14:20.42#ibcon#about to read 6, iclass 19, count 0 2006.238.08:14:20.42#ibcon#read 6, iclass 19, count 0 2006.238.08:14:20.42#ibcon#end of sib2, iclass 19, count 0 2006.238.08:14:20.42#ibcon#*after write, iclass 19, count 0 2006.238.08:14:20.42#ibcon#*before return 0, iclass 19, count 0 2006.238.08:14:20.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:14:20.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:14:20.42#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.08:14:20.42#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.08:14:20.42$vc4f8/va=8,7 2006.238.08:14:20.42#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.08:14:20.42#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.08:14:20.42#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:20.42#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:14:20.48#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:14:20.48#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:14:20.48#ibcon#enter wrdev, iclass 21, count 2 2006.238.08:14:20.48#ibcon#first serial, iclass 21, count 2 2006.238.08:14:20.48#ibcon#enter sib2, iclass 21, count 2 2006.238.08:14:20.48#ibcon#flushed, iclass 21, count 2 2006.238.08:14:20.48#ibcon#about to write, iclass 21, count 2 2006.238.08:14:20.48#ibcon#wrote, iclass 21, count 2 2006.238.08:14:20.48#ibcon#about to read 3, iclass 21, count 2 2006.238.08:14:20.50#ibcon#read 3, iclass 21, count 2 2006.238.08:14:20.50#ibcon#about to read 4, iclass 21, count 2 2006.238.08:14:20.50#ibcon#read 4, iclass 21, count 2 2006.238.08:14:20.50#ibcon#about to read 5, iclass 21, count 2 2006.238.08:14:20.50#ibcon#read 5, iclass 21, count 2 2006.238.08:14:20.50#ibcon#about to read 6, iclass 21, count 2 2006.238.08:14:20.50#ibcon#read 6, iclass 21, count 2 2006.238.08:14:20.50#ibcon#end of sib2, iclass 21, count 2 2006.238.08:14:20.50#ibcon#*mode == 0, iclass 21, count 2 2006.238.08:14:20.50#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.08:14:20.50#ibcon#[25=AT08-07\r\n] 2006.238.08:14:20.50#ibcon#*before write, iclass 21, count 2 2006.238.08:14:20.50#ibcon#enter sib2, iclass 21, count 2 2006.238.08:14:20.50#ibcon#flushed, iclass 21, count 2 2006.238.08:14:20.50#ibcon#about to write, iclass 21, count 2 2006.238.08:14:20.50#ibcon#wrote, iclass 21, count 2 2006.238.08:14:20.50#ibcon#about to read 3, iclass 21, count 2 2006.238.08:14:20.53#ibcon#read 3, iclass 21, count 2 2006.238.08:14:20.53#ibcon#about to read 4, iclass 21, count 2 2006.238.08:14:20.53#ibcon#read 4, iclass 21, count 2 2006.238.08:14:20.53#ibcon#about to read 5, iclass 21, count 2 2006.238.08:14:20.53#ibcon#read 5, iclass 21, count 2 2006.238.08:14:20.53#ibcon#about to read 6, iclass 21, count 2 2006.238.08:14:20.53#ibcon#read 6, iclass 21, count 2 2006.238.08:14:20.53#ibcon#end of sib2, iclass 21, count 2 2006.238.08:14:20.53#ibcon#*after write, iclass 21, count 2 2006.238.08:14:20.53#ibcon#*before return 0, iclass 21, count 2 2006.238.08:14:20.53#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:14:20.53#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:14:20.53#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.08:14:20.53#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:20.53#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:14:20.65#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:14:20.65#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:14:20.65#ibcon#enter wrdev, iclass 21, count 0 2006.238.08:14:20.65#ibcon#first serial, iclass 21, count 0 2006.238.08:14:20.65#ibcon#enter sib2, iclass 21, count 0 2006.238.08:14:20.65#ibcon#flushed, iclass 21, count 0 2006.238.08:14:20.65#ibcon#about to write, iclass 21, count 0 2006.238.08:14:20.65#ibcon#wrote, iclass 21, count 0 2006.238.08:14:20.65#ibcon#about to read 3, iclass 21, count 0 2006.238.08:14:20.67#ibcon#read 3, iclass 21, count 0 2006.238.08:14:20.67#ibcon#about to read 4, iclass 21, count 0 2006.238.08:14:20.67#ibcon#read 4, iclass 21, count 0 2006.238.08:14:20.67#ibcon#about to read 5, iclass 21, count 0 2006.238.08:14:20.67#ibcon#read 5, iclass 21, count 0 2006.238.08:14:20.67#ibcon#about to read 6, iclass 21, count 0 2006.238.08:14:20.67#ibcon#read 6, iclass 21, count 0 2006.238.08:14:20.67#ibcon#end of sib2, iclass 21, count 0 2006.238.08:14:20.67#ibcon#*mode == 0, iclass 21, count 0 2006.238.08:14:20.67#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.08:14:20.67#ibcon#[25=USB\r\n] 2006.238.08:14:20.67#ibcon#*before write, iclass 21, count 0 2006.238.08:14:20.67#ibcon#enter sib2, iclass 21, count 0 2006.238.08:14:20.67#ibcon#flushed, iclass 21, count 0 2006.238.08:14:20.67#ibcon#about to write, iclass 21, count 0 2006.238.08:14:20.67#ibcon#wrote, iclass 21, count 0 2006.238.08:14:20.67#ibcon#about to read 3, iclass 21, count 0 2006.238.08:14:20.70#ibcon#read 3, iclass 21, count 0 2006.238.08:14:20.70#ibcon#about to read 4, iclass 21, count 0 2006.238.08:14:20.70#ibcon#read 4, iclass 21, count 0 2006.238.08:14:20.70#ibcon#about to read 5, iclass 21, count 0 2006.238.08:14:20.70#ibcon#read 5, iclass 21, count 0 2006.238.08:14:20.70#ibcon#about to read 6, iclass 21, count 0 2006.238.08:14:20.70#ibcon#read 6, iclass 21, count 0 2006.238.08:14:20.70#ibcon#end of sib2, iclass 21, count 0 2006.238.08:14:20.70#ibcon#*after write, iclass 21, count 0 2006.238.08:14:20.70#ibcon#*before return 0, iclass 21, count 0 2006.238.08:14:20.70#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:14:20.70#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:14:20.70#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.08:14:20.70#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.08:14:20.70$vc4f8/vblo=1,632.99 2006.238.08:14:20.70#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.08:14:20.70#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.08:14:20.70#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:20.70#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:14:20.70#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:14:20.70#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:14:20.70#ibcon#enter wrdev, iclass 23, count 0 2006.238.08:14:20.70#ibcon#first serial, iclass 23, count 0 2006.238.08:14:20.70#ibcon#enter sib2, iclass 23, count 0 2006.238.08:14:20.70#ibcon#flushed, iclass 23, count 0 2006.238.08:14:20.70#ibcon#about to write, iclass 23, count 0 2006.238.08:14:20.70#ibcon#wrote, iclass 23, count 0 2006.238.08:14:20.70#ibcon#about to read 3, iclass 23, count 0 2006.238.08:14:20.72#ibcon#read 3, iclass 23, count 0 2006.238.08:14:20.72#ibcon#about to read 4, iclass 23, count 0 2006.238.08:14:20.72#ibcon#read 4, iclass 23, count 0 2006.238.08:14:20.72#ibcon#about to read 5, iclass 23, count 0 2006.238.08:14:20.72#ibcon#read 5, iclass 23, count 0 2006.238.08:14:20.72#ibcon#about to read 6, iclass 23, count 0 2006.238.08:14:20.72#ibcon#read 6, iclass 23, count 0 2006.238.08:14:20.72#ibcon#end of sib2, iclass 23, count 0 2006.238.08:14:20.72#ibcon#*mode == 0, iclass 23, count 0 2006.238.08:14:20.72#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.08:14:20.72#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:14:20.72#ibcon#*before write, iclass 23, count 0 2006.238.08:14:20.72#ibcon#enter sib2, iclass 23, count 0 2006.238.08:14:20.72#ibcon#flushed, iclass 23, count 0 2006.238.08:14:20.72#ibcon#about to write, iclass 23, count 0 2006.238.08:14:20.72#ibcon#wrote, iclass 23, count 0 2006.238.08:14:20.72#ibcon#about to read 3, iclass 23, count 0 2006.238.08:14:20.76#ibcon#read 3, iclass 23, count 0 2006.238.08:14:20.76#ibcon#about to read 4, iclass 23, count 0 2006.238.08:14:20.76#ibcon#read 4, iclass 23, count 0 2006.238.08:14:20.76#ibcon#about to read 5, iclass 23, count 0 2006.238.08:14:20.76#ibcon#read 5, iclass 23, count 0 2006.238.08:14:20.76#ibcon#about to read 6, iclass 23, count 0 2006.238.08:14:20.76#ibcon#read 6, iclass 23, count 0 2006.238.08:14:20.76#ibcon#end of sib2, iclass 23, count 0 2006.238.08:14:20.76#ibcon#*after write, iclass 23, count 0 2006.238.08:14:20.76#ibcon#*before return 0, iclass 23, count 0 2006.238.08:14:20.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:14:20.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:14:20.76#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.08:14:20.76#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.08:14:20.76$vc4f8/vb=1,4 2006.238.08:14:20.76#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.08:14:20.76#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.08:14:20.76#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:20.76#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:14:20.76#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:14:20.76#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:14:20.76#ibcon#enter wrdev, iclass 25, count 2 2006.238.08:14:20.76#ibcon#first serial, iclass 25, count 2 2006.238.08:14:20.76#ibcon#enter sib2, iclass 25, count 2 2006.238.08:14:20.76#ibcon#flushed, iclass 25, count 2 2006.238.08:14:20.76#ibcon#about to write, iclass 25, count 2 2006.238.08:14:20.76#ibcon#wrote, iclass 25, count 2 2006.238.08:14:20.76#ibcon#about to read 3, iclass 25, count 2 2006.238.08:14:20.78#ibcon#read 3, iclass 25, count 2 2006.238.08:14:20.78#ibcon#about to read 4, iclass 25, count 2 2006.238.08:14:20.78#ibcon#read 4, iclass 25, count 2 2006.238.08:14:20.78#ibcon#about to read 5, iclass 25, count 2 2006.238.08:14:20.78#ibcon#read 5, iclass 25, count 2 2006.238.08:14:20.78#ibcon#about to read 6, iclass 25, count 2 2006.238.08:14:20.78#ibcon#read 6, iclass 25, count 2 2006.238.08:14:20.78#ibcon#end of sib2, iclass 25, count 2 2006.238.08:14:20.78#ibcon#*mode == 0, iclass 25, count 2 2006.238.08:14:20.78#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.08:14:20.78#ibcon#[27=AT01-04\r\n] 2006.238.08:14:20.78#ibcon#*before write, iclass 25, count 2 2006.238.08:14:20.78#ibcon#enter sib2, iclass 25, count 2 2006.238.08:14:20.78#ibcon#flushed, iclass 25, count 2 2006.238.08:14:20.78#ibcon#about to write, iclass 25, count 2 2006.238.08:14:20.78#ibcon#wrote, iclass 25, count 2 2006.238.08:14:20.78#ibcon#about to read 3, iclass 25, count 2 2006.238.08:14:20.81#ibcon#read 3, iclass 25, count 2 2006.238.08:14:20.81#ibcon#about to read 4, iclass 25, count 2 2006.238.08:14:20.81#ibcon#read 4, iclass 25, count 2 2006.238.08:14:20.81#ibcon#about to read 5, iclass 25, count 2 2006.238.08:14:20.81#ibcon#read 5, iclass 25, count 2 2006.238.08:14:20.81#ibcon#about to read 6, iclass 25, count 2 2006.238.08:14:20.81#ibcon#read 6, iclass 25, count 2 2006.238.08:14:20.81#ibcon#end of sib2, iclass 25, count 2 2006.238.08:14:20.81#ibcon#*after write, iclass 25, count 2 2006.238.08:14:20.81#ibcon#*before return 0, iclass 25, count 2 2006.238.08:14:20.81#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:14:20.81#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:14:20.81#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.08:14:20.81#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:20.81#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:14:20.93#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:14:20.93#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:14:20.93#ibcon#enter wrdev, iclass 25, count 0 2006.238.08:14:20.93#ibcon#first serial, iclass 25, count 0 2006.238.08:14:20.93#ibcon#enter sib2, iclass 25, count 0 2006.238.08:14:20.93#ibcon#flushed, iclass 25, count 0 2006.238.08:14:20.93#ibcon#about to write, iclass 25, count 0 2006.238.08:14:20.93#ibcon#wrote, iclass 25, count 0 2006.238.08:14:20.93#ibcon#about to read 3, iclass 25, count 0 2006.238.08:14:20.95#ibcon#read 3, iclass 25, count 0 2006.238.08:14:20.95#ibcon#about to read 4, iclass 25, count 0 2006.238.08:14:20.95#ibcon#read 4, iclass 25, count 0 2006.238.08:14:20.95#ibcon#about to read 5, iclass 25, count 0 2006.238.08:14:20.95#ibcon#read 5, iclass 25, count 0 2006.238.08:14:20.95#ibcon#about to read 6, iclass 25, count 0 2006.238.08:14:20.95#ibcon#read 6, iclass 25, count 0 2006.238.08:14:20.95#ibcon#end of sib2, iclass 25, count 0 2006.238.08:14:20.95#ibcon#*mode == 0, iclass 25, count 0 2006.238.08:14:20.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.08:14:20.95#ibcon#[27=USB\r\n] 2006.238.08:14:20.95#ibcon#*before write, iclass 25, count 0 2006.238.08:14:20.95#ibcon#enter sib2, iclass 25, count 0 2006.238.08:14:20.95#ibcon#flushed, iclass 25, count 0 2006.238.08:14:20.95#ibcon#about to write, iclass 25, count 0 2006.238.08:14:20.95#ibcon#wrote, iclass 25, count 0 2006.238.08:14:20.95#ibcon#about to read 3, iclass 25, count 0 2006.238.08:14:20.98#ibcon#read 3, iclass 25, count 0 2006.238.08:14:20.98#ibcon#about to read 4, iclass 25, count 0 2006.238.08:14:20.98#ibcon#read 4, iclass 25, count 0 2006.238.08:14:20.98#ibcon#about to read 5, iclass 25, count 0 2006.238.08:14:20.98#ibcon#read 5, iclass 25, count 0 2006.238.08:14:20.98#ibcon#about to read 6, iclass 25, count 0 2006.238.08:14:20.98#ibcon#read 6, iclass 25, count 0 2006.238.08:14:20.98#ibcon#end of sib2, iclass 25, count 0 2006.238.08:14:20.98#ibcon#*after write, iclass 25, count 0 2006.238.08:14:20.98#ibcon#*before return 0, iclass 25, count 0 2006.238.08:14:20.98#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:14:20.98#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:14:20.98#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.08:14:20.98#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.08:14:20.98$vc4f8/vblo=2,640.99 2006.238.08:14:20.98#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.08:14:20.98#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.08:14:20.98#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:20.98#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:14:20.98#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:14:20.98#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:14:20.98#ibcon#enter wrdev, iclass 27, count 0 2006.238.08:14:20.98#ibcon#first serial, iclass 27, count 0 2006.238.08:14:20.98#ibcon#enter sib2, iclass 27, count 0 2006.238.08:14:20.98#ibcon#flushed, iclass 27, count 0 2006.238.08:14:20.98#ibcon#about to write, iclass 27, count 0 2006.238.08:14:20.98#ibcon#wrote, iclass 27, count 0 2006.238.08:14:20.98#ibcon#about to read 3, iclass 27, count 0 2006.238.08:14:21.00#ibcon#read 3, iclass 27, count 0 2006.238.08:14:21.00#ibcon#about to read 4, iclass 27, count 0 2006.238.08:14:21.00#ibcon#read 4, iclass 27, count 0 2006.238.08:14:21.00#ibcon#about to read 5, iclass 27, count 0 2006.238.08:14:21.00#ibcon#read 5, iclass 27, count 0 2006.238.08:14:21.00#ibcon#about to read 6, iclass 27, count 0 2006.238.08:14:21.00#ibcon#read 6, iclass 27, count 0 2006.238.08:14:21.00#ibcon#end of sib2, iclass 27, count 0 2006.238.08:14:21.00#ibcon#*mode == 0, iclass 27, count 0 2006.238.08:14:21.00#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.08:14:21.00#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:14:21.00#ibcon#*before write, iclass 27, count 0 2006.238.08:14:21.00#ibcon#enter sib2, iclass 27, count 0 2006.238.08:14:21.00#ibcon#flushed, iclass 27, count 0 2006.238.08:14:21.00#ibcon#about to write, iclass 27, count 0 2006.238.08:14:21.00#ibcon#wrote, iclass 27, count 0 2006.238.08:14:21.00#ibcon#about to read 3, iclass 27, count 0 2006.238.08:14:21.04#ibcon#read 3, iclass 27, count 0 2006.238.08:14:21.04#ibcon#about to read 4, iclass 27, count 0 2006.238.08:14:21.04#ibcon#read 4, iclass 27, count 0 2006.238.08:14:21.04#ibcon#about to read 5, iclass 27, count 0 2006.238.08:14:21.04#ibcon#read 5, iclass 27, count 0 2006.238.08:14:21.04#ibcon#about to read 6, iclass 27, count 0 2006.238.08:14:21.04#ibcon#read 6, iclass 27, count 0 2006.238.08:14:21.04#ibcon#end of sib2, iclass 27, count 0 2006.238.08:14:21.04#ibcon#*after write, iclass 27, count 0 2006.238.08:14:21.04#ibcon#*before return 0, iclass 27, count 0 2006.238.08:14:21.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:14:21.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:14:21.04#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.08:14:21.04#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.08:14:21.04$vc4f8/vb=2,4 2006.238.08:14:21.04#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.08:14:21.04#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.08:14:21.04#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:21.04#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:14:21.10#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:14:21.10#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:14:21.10#ibcon#enter wrdev, iclass 29, count 2 2006.238.08:14:21.10#ibcon#first serial, iclass 29, count 2 2006.238.08:14:21.10#ibcon#enter sib2, iclass 29, count 2 2006.238.08:14:21.10#ibcon#flushed, iclass 29, count 2 2006.238.08:14:21.10#ibcon#about to write, iclass 29, count 2 2006.238.08:14:21.10#ibcon#wrote, iclass 29, count 2 2006.238.08:14:21.10#ibcon#about to read 3, iclass 29, count 2 2006.238.08:14:21.12#ibcon#read 3, iclass 29, count 2 2006.238.08:14:21.12#ibcon#about to read 4, iclass 29, count 2 2006.238.08:14:21.12#ibcon#read 4, iclass 29, count 2 2006.238.08:14:21.12#ibcon#about to read 5, iclass 29, count 2 2006.238.08:14:21.12#ibcon#read 5, iclass 29, count 2 2006.238.08:14:21.12#ibcon#about to read 6, iclass 29, count 2 2006.238.08:14:21.12#ibcon#read 6, iclass 29, count 2 2006.238.08:14:21.12#ibcon#end of sib2, iclass 29, count 2 2006.238.08:14:21.12#ibcon#*mode == 0, iclass 29, count 2 2006.238.08:14:21.12#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.08:14:21.12#ibcon#[27=AT02-04\r\n] 2006.238.08:14:21.12#ibcon#*before write, iclass 29, count 2 2006.238.08:14:21.12#ibcon#enter sib2, iclass 29, count 2 2006.238.08:14:21.12#ibcon#flushed, iclass 29, count 2 2006.238.08:14:21.12#ibcon#about to write, iclass 29, count 2 2006.238.08:14:21.12#ibcon#wrote, iclass 29, count 2 2006.238.08:14:21.12#ibcon#about to read 3, iclass 29, count 2 2006.238.08:14:21.15#ibcon#read 3, iclass 29, count 2 2006.238.08:14:21.15#ibcon#about to read 4, iclass 29, count 2 2006.238.08:14:21.15#ibcon#read 4, iclass 29, count 2 2006.238.08:14:21.15#ibcon#about to read 5, iclass 29, count 2 2006.238.08:14:21.15#ibcon#read 5, iclass 29, count 2 2006.238.08:14:21.15#ibcon#about to read 6, iclass 29, count 2 2006.238.08:14:21.15#ibcon#read 6, iclass 29, count 2 2006.238.08:14:21.15#ibcon#end of sib2, iclass 29, count 2 2006.238.08:14:21.15#ibcon#*after write, iclass 29, count 2 2006.238.08:14:21.15#ibcon#*before return 0, iclass 29, count 2 2006.238.08:14:21.15#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:14:21.15#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:14:21.15#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.08:14:21.15#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:21.15#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:14:21.27#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:14:21.27#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:14:21.27#ibcon#enter wrdev, iclass 29, count 0 2006.238.08:14:21.27#ibcon#first serial, iclass 29, count 0 2006.238.08:14:21.27#ibcon#enter sib2, iclass 29, count 0 2006.238.08:14:21.27#ibcon#flushed, iclass 29, count 0 2006.238.08:14:21.27#ibcon#about to write, iclass 29, count 0 2006.238.08:14:21.27#ibcon#wrote, iclass 29, count 0 2006.238.08:14:21.27#ibcon#about to read 3, iclass 29, count 0 2006.238.08:14:21.29#ibcon#read 3, iclass 29, count 0 2006.238.08:14:21.29#ibcon#about to read 4, iclass 29, count 0 2006.238.08:14:21.29#ibcon#read 4, iclass 29, count 0 2006.238.08:14:21.29#ibcon#about to read 5, iclass 29, count 0 2006.238.08:14:21.29#ibcon#read 5, iclass 29, count 0 2006.238.08:14:21.29#ibcon#about to read 6, iclass 29, count 0 2006.238.08:14:21.29#ibcon#read 6, iclass 29, count 0 2006.238.08:14:21.29#ibcon#end of sib2, iclass 29, count 0 2006.238.08:14:21.29#ibcon#*mode == 0, iclass 29, count 0 2006.238.08:14:21.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.08:14:21.29#ibcon#[27=USB\r\n] 2006.238.08:14:21.29#ibcon#*before write, iclass 29, count 0 2006.238.08:14:21.29#ibcon#enter sib2, iclass 29, count 0 2006.238.08:14:21.29#ibcon#flushed, iclass 29, count 0 2006.238.08:14:21.29#ibcon#about to write, iclass 29, count 0 2006.238.08:14:21.29#ibcon#wrote, iclass 29, count 0 2006.238.08:14:21.29#ibcon#about to read 3, iclass 29, count 0 2006.238.08:14:21.32#ibcon#read 3, iclass 29, count 0 2006.238.08:14:21.32#ibcon#about to read 4, iclass 29, count 0 2006.238.08:14:21.32#ibcon#read 4, iclass 29, count 0 2006.238.08:14:21.32#ibcon#about to read 5, iclass 29, count 0 2006.238.08:14:21.32#ibcon#read 5, iclass 29, count 0 2006.238.08:14:21.32#ibcon#about to read 6, iclass 29, count 0 2006.238.08:14:21.32#ibcon#read 6, iclass 29, count 0 2006.238.08:14:21.32#ibcon#end of sib2, iclass 29, count 0 2006.238.08:14:21.32#ibcon#*after write, iclass 29, count 0 2006.238.08:14:21.32#ibcon#*before return 0, iclass 29, count 0 2006.238.08:14:21.32#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:14:21.32#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:14:21.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.08:14:21.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.08:14:21.32$vc4f8/vblo=3,656.99 2006.238.08:14:21.32#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.08:14:21.32#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.08:14:21.32#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:21.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:14:21.32#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:14:21.32#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:14:21.32#ibcon#enter wrdev, iclass 31, count 0 2006.238.08:14:21.32#ibcon#first serial, iclass 31, count 0 2006.238.08:14:21.32#ibcon#enter sib2, iclass 31, count 0 2006.238.08:14:21.32#ibcon#flushed, iclass 31, count 0 2006.238.08:14:21.32#ibcon#about to write, iclass 31, count 0 2006.238.08:14:21.32#ibcon#wrote, iclass 31, count 0 2006.238.08:14:21.32#ibcon#about to read 3, iclass 31, count 0 2006.238.08:14:21.34#ibcon#read 3, iclass 31, count 0 2006.238.08:14:21.34#ibcon#about to read 4, iclass 31, count 0 2006.238.08:14:21.34#ibcon#read 4, iclass 31, count 0 2006.238.08:14:21.34#ibcon#about to read 5, iclass 31, count 0 2006.238.08:14:21.34#ibcon#read 5, iclass 31, count 0 2006.238.08:14:21.34#ibcon#about to read 6, iclass 31, count 0 2006.238.08:14:21.34#ibcon#read 6, iclass 31, count 0 2006.238.08:14:21.34#ibcon#end of sib2, iclass 31, count 0 2006.238.08:14:21.34#ibcon#*mode == 0, iclass 31, count 0 2006.238.08:14:21.34#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.08:14:21.34#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:14:21.34#ibcon#*before write, iclass 31, count 0 2006.238.08:14:21.34#ibcon#enter sib2, iclass 31, count 0 2006.238.08:14:21.34#ibcon#flushed, iclass 31, count 0 2006.238.08:14:21.34#ibcon#about to write, iclass 31, count 0 2006.238.08:14:21.34#ibcon#wrote, iclass 31, count 0 2006.238.08:14:21.34#ibcon#about to read 3, iclass 31, count 0 2006.238.08:14:21.38#ibcon#read 3, iclass 31, count 0 2006.238.08:14:21.38#ibcon#about to read 4, iclass 31, count 0 2006.238.08:14:21.38#ibcon#read 4, iclass 31, count 0 2006.238.08:14:21.38#ibcon#about to read 5, iclass 31, count 0 2006.238.08:14:21.38#ibcon#read 5, iclass 31, count 0 2006.238.08:14:21.38#ibcon#about to read 6, iclass 31, count 0 2006.238.08:14:21.38#ibcon#read 6, iclass 31, count 0 2006.238.08:14:21.38#ibcon#end of sib2, iclass 31, count 0 2006.238.08:14:21.38#ibcon#*after write, iclass 31, count 0 2006.238.08:14:21.38#ibcon#*before return 0, iclass 31, count 0 2006.238.08:14:21.38#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:14:21.38#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:14:21.38#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.08:14:21.38#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.08:14:21.38$vc4f8/vb=3,4 2006.238.08:14:21.38#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.08:14:21.38#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.08:14:21.38#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:21.38#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:14:21.44#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:14:21.44#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:14:21.44#ibcon#enter wrdev, iclass 33, count 2 2006.238.08:14:21.44#ibcon#first serial, iclass 33, count 2 2006.238.08:14:21.44#ibcon#enter sib2, iclass 33, count 2 2006.238.08:14:21.44#ibcon#flushed, iclass 33, count 2 2006.238.08:14:21.44#ibcon#about to write, iclass 33, count 2 2006.238.08:14:21.44#ibcon#wrote, iclass 33, count 2 2006.238.08:14:21.44#ibcon#about to read 3, iclass 33, count 2 2006.238.08:14:21.46#ibcon#read 3, iclass 33, count 2 2006.238.08:14:21.46#ibcon#about to read 4, iclass 33, count 2 2006.238.08:14:21.46#ibcon#read 4, iclass 33, count 2 2006.238.08:14:21.46#ibcon#about to read 5, iclass 33, count 2 2006.238.08:14:21.46#ibcon#read 5, iclass 33, count 2 2006.238.08:14:21.46#ibcon#about to read 6, iclass 33, count 2 2006.238.08:14:21.46#ibcon#read 6, iclass 33, count 2 2006.238.08:14:21.46#ibcon#end of sib2, iclass 33, count 2 2006.238.08:14:21.46#ibcon#*mode == 0, iclass 33, count 2 2006.238.08:14:21.46#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.08:14:21.46#ibcon#[27=AT03-04\r\n] 2006.238.08:14:21.46#ibcon#*before write, iclass 33, count 2 2006.238.08:14:21.46#ibcon#enter sib2, iclass 33, count 2 2006.238.08:14:21.46#ibcon#flushed, iclass 33, count 2 2006.238.08:14:21.46#ibcon#about to write, iclass 33, count 2 2006.238.08:14:21.46#ibcon#wrote, iclass 33, count 2 2006.238.08:14:21.46#ibcon#about to read 3, iclass 33, count 2 2006.238.08:14:21.49#ibcon#read 3, iclass 33, count 2 2006.238.08:14:21.49#ibcon#about to read 4, iclass 33, count 2 2006.238.08:14:21.49#ibcon#read 4, iclass 33, count 2 2006.238.08:14:21.49#ibcon#about to read 5, iclass 33, count 2 2006.238.08:14:21.49#ibcon#read 5, iclass 33, count 2 2006.238.08:14:21.49#ibcon#about to read 6, iclass 33, count 2 2006.238.08:14:21.49#ibcon#read 6, iclass 33, count 2 2006.238.08:14:21.49#ibcon#end of sib2, iclass 33, count 2 2006.238.08:14:21.49#ibcon#*after write, iclass 33, count 2 2006.238.08:14:21.49#ibcon#*before return 0, iclass 33, count 2 2006.238.08:14:21.49#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:14:21.49#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:14:21.49#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.08:14:21.49#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:21.49#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:14:21.56#abcon#<5=/04 1.8 3.5 25.47 901012.2\r\n> 2006.238.08:14:21.58#abcon#{5=INTERFACE CLEAR} 2006.238.08:14:21.61#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:14:21.61#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:14:21.61#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:14:21.61#ibcon#first serial, iclass 33, count 0 2006.238.08:14:21.61#ibcon#enter sib2, iclass 33, count 0 2006.238.08:14:21.61#ibcon#flushed, iclass 33, count 0 2006.238.08:14:21.61#ibcon#about to write, iclass 33, count 0 2006.238.08:14:21.61#ibcon#wrote, iclass 33, count 0 2006.238.08:14:21.61#ibcon#about to read 3, iclass 33, count 0 2006.238.08:14:21.63#ibcon#read 3, iclass 33, count 0 2006.238.08:14:21.63#ibcon#about to read 4, iclass 33, count 0 2006.238.08:14:21.63#ibcon#read 4, iclass 33, count 0 2006.238.08:14:21.63#ibcon#about to read 5, iclass 33, count 0 2006.238.08:14:21.63#ibcon#read 5, iclass 33, count 0 2006.238.08:14:21.63#ibcon#about to read 6, iclass 33, count 0 2006.238.08:14:21.63#ibcon#read 6, iclass 33, count 0 2006.238.08:14:21.63#ibcon#end of sib2, iclass 33, count 0 2006.238.08:14:21.63#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:14:21.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:14:21.63#ibcon#[27=USB\r\n] 2006.238.08:14:21.63#ibcon#*before write, iclass 33, count 0 2006.238.08:14:21.63#ibcon#enter sib2, iclass 33, count 0 2006.238.08:14:21.63#ibcon#flushed, iclass 33, count 0 2006.238.08:14:21.63#ibcon#about to write, iclass 33, count 0 2006.238.08:14:21.63#ibcon#wrote, iclass 33, count 0 2006.238.08:14:21.63#ibcon#about to read 3, iclass 33, count 0 2006.238.08:14:21.64#abcon#[5=S1D000X0/0*\r\n] 2006.238.08:14:21.66#ibcon#read 3, iclass 33, count 0 2006.238.08:14:21.66#ibcon#about to read 4, iclass 33, count 0 2006.238.08:14:21.66#ibcon#read 4, iclass 33, count 0 2006.238.08:14:21.66#ibcon#about to read 5, iclass 33, count 0 2006.238.08:14:21.66#ibcon#read 5, iclass 33, count 0 2006.238.08:14:21.66#ibcon#about to read 6, iclass 33, count 0 2006.238.08:14:21.66#ibcon#read 6, iclass 33, count 0 2006.238.08:14:21.66#ibcon#end of sib2, iclass 33, count 0 2006.238.08:14:21.66#ibcon#*after write, iclass 33, count 0 2006.238.08:14:21.66#ibcon#*before return 0, iclass 33, count 0 2006.238.08:14:21.66#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:14:21.66#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:14:21.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:14:21.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:14:21.66$vc4f8/vblo=4,712.99 2006.238.08:14:21.66#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.08:14:21.66#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.08:14:21.66#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:21.66#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:14:21.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:14:21.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:14:21.66#ibcon#enter wrdev, iclass 39, count 0 2006.238.08:14:21.66#ibcon#first serial, iclass 39, count 0 2006.238.08:14:21.66#ibcon#enter sib2, iclass 39, count 0 2006.238.08:14:21.66#ibcon#flushed, iclass 39, count 0 2006.238.08:14:21.66#ibcon#about to write, iclass 39, count 0 2006.238.08:14:21.66#ibcon#wrote, iclass 39, count 0 2006.238.08:14:21.66#ibcon#about to read 3, iclass 39, count 0 2006.238.08:14:21.68#ibcon#read 3, iclass 39, count 0 2006.238.08:14:21.68#ibcon#about to read 4, iclass 39, count 0 2006.238.08:14:21.68#ibcon#read 4, iclass 39, count 0 2006.238.08:14:21.68#ibcon#about to read 5, iclass 39, count 0 2006.238.08:14:21.68#ibcon#read 5, iclass 39, count 0 2006.238.08:14:21.68#ibcon#about to read 6, iclass 39, count 0 2006.238.08:14:21.68#ibcon#read 6, iclass 39, count 0 2006.238.08:14:21.68#ibcon#end of sib2, iclass 39, count 0 2006.238.08:14:21.68#ibcon#*mode == 0, iclass 39, count 0 2006.238.08:14:21.68#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.08:14:21.68#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:14:21.68#ibcon#*before write, iclass 39, count 0 2006.238.08:14:21.68#ibcon#enter sib2, iclass 39, count 0 2006.238.08:14:21.68#ibcon#flushed, iclass 39, count 0 2006.238.08:14:21.68#ibcon#about to write, iclass 39, count 0 2006.238.08:14:21.68#ibcon#wrote, iclass 39, count 0 2006.238.08:14:21.68#ibcon#about to read 3, iclass 39, count 0 2006.238.08:14:21.72#ibcon#read 3, iclass 39, count 0 2006.238.08:14:21.72#ibcon#about to read 4, iclass 39, count 0 2006.238.08:14:21.72#ibcon#read 4, iclass 39, count 0 2006.238.08:14:21.72#ibcon#about to read 5, iclass 39, count 0 2006.238.08:14:21.72#ibcon#read 5, iclass 39, count 0 2006.238.08:14:21.72#ibcon#about to read 6, iclass 39, count 0 2006.238.08:14:21.72#ibcon#read 6, iclass 39, count 0 2006.238.08:14:21.72#ibcon#end of sib2, iclass 39, count 0 2006.238.08:14:21.72#ibcon#*after write, iclass 39, count 0 2006.238.08:14:21.72#ibcon#*before return 0, iclass 39, count 0 2006.238.08:14:21.72#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:14:21.72#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:14:21.72#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.08:14:21.72#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.08:14:21.72$vc4f8/vb=4,4 2006.238.08:14:21.72#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.08:14:21.72#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.08:14:21.72#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:21.72#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:14:21.78#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:14:21.78#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:14:21.78#ibcon#enter wrdev, iclass 3, count 2 2006.238.08:14:21.78#ibcon#first serial, iclass 3, count 2 2006.238.08:14:21.78#ibcon#enter sib2, iclass 3, count 2 2006.238.08:14:21.78#ibcon#flushed, iclass 3, count 2 2006.238.08:14:21.78#ibcon#about to write, iclass 3, count 2 2006.238.08:14:21.78#ibcon#wrote, iclass 3, count 2 2006.238.08:14:21.78#ibcon#about to read 3, iclass 3, count 2 2006.238.08:14:21.80#ibcon#read 3, iclass 3, count 2 2006.238.08:14:21.80#ibcon#about to read 4, iclass 3, count 2 2006.238.08:14:21.80#ibcon#read 4, iclass 3, count 2 2006.238.08:14:21.80#ibcon#about to read 5, iclass 3, count 2 2006.238.08:14:21.80#ibcon#read 5, iclass 3, count 2 2006.238.08:14:21.80#ibcon#about to read 6, iclass 3, count 2 2006.238.08:14:21.80#ibcon#read 6, iclass 3, count 2 2006.238.08:14:21.80#ibcon#end of sib2, iclass 3, count 2 2006.238.08:14:21.80#ibcon#*mode == 0, iclass 3, count 2 2006.238.08:14:21.80#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.08:14:21.80#ibcon#[27=AT04-04\r\n] 2006.238.08:14:21.80#ibcon#*before write, iclass 3, count 2 2006.238.08:14:21.80#ibcon#enter sib2, iclass 3, count 2 2006.238.08:14:21.80#ibcon#flushed, iclass 3, count 2 2006.238.08:14:21.80#ibcon#about to write, iclass 3, count 2 2006.238.08:14:21.80#ibcon#wrote, iclass 3, count 2 2006.238.08:14:21.80#ibcon#about to read 3, iclass 3, count 2 2006.238.08:14:21.83#ibcon#read 3, iclass 3, count 2 2006.238.08:14:21.83#ibcon#about to read 4, iclass 3, count 2 2006.238.08:14:21.83#ibcon#read 4, iclass 3, count 2 2006.238.08:14:21.83#ibcon#about to read 5, iclass 3, count 2 2006.238.08:14:21.83#ibcon#read 5, iclass 3, count 2 2006.238.08:14:21.83#ibcon#about to read 6, iclass 3, count 2 2006.238.08:14:21.83#ibcon#read 6, iclass 3, count 2 2006.238.08:14:21.83#ibcon#end of sib2, iclass 3, count 2 2006.238.08:14:21.83#ibcon#*after write, iclass 3, count 2 2006.238.08:14:21.83#ibcon#*before return 0, iclass 3, count 2 2006.238.08:14:21.83#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:14:21.83#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:14:21.83#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.08:14:21.83#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:21.83#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:14:21.95#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:14:21.95#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:14:21.95#ibcon#enter wrdev, iclass 3, count 0 2006.238.08:14:21.95#ibcon#first serial, iclass 3, count 0 2006.238.08:14:21.95#ibcon#enter sib2, iclass 3, count 0 2006.238.08:14:21.95#ibcon#flushed, iclass 3, count 0 2006.238.08:14:21.95#ibcon#about to write, iclass 3, count 0 2006.238.08:14:21.95#ibcon#wrote, iclass 3, count 0 2006.238.08:14:21.95#ibcon#about to read 3, iclass 3, count 0 2006.238.08:14:21.97#ibcon#read 3, iclass 3, count 0 2006.238.08:14:21.97#ibcon#about to read 4, iclass 3, count 0 2006.238.08:14:21.97#ibcon#read 4, iclass 3, count 0 2006.238.08:14:21.97#ibcon#about to read 5, iclass 3, count 0 2006.238.08:14:21.97#ibcon#read 5, iclass 3, count 0 2006.238.08:14:21.97#ibcon#about to read 6, iclass 3, count 0 2006.238.08:14:21.97#ibcon#read 6, iclass 3, count 0 2006.238.08:14:21.97#ibcon#end of sib2, iclass 3, count 0 2006.238.08:14:21.97#ibcon#*mode == 0, iclass 3, count 0 2006.238.08:14:21.97#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.08:14:21.97#ibcon#[27=USB\r\n] 2006.238.08:14:21.97#ibcon#*before write, iclass 3, count 0 2006.238.08:14:21.97#ibcon#enter sib2, iclass 3, count 0 2006.238.08:14:21.97#ibcon#flushed, iclass 3, count 0 2006.238.08:14:21.97#ibcon#about to write, iclass 3, count 0 2006.238.08:14:21.97#ibcon#wrote, iclass 3, count 0 2006.238.08:14:21.97#ibcon#about to read 3, iclass 3, count 0 2006.238.08:14:22.00#ibcon#read 3, iclass 3, count 0 2006.238.08:14:22.00#ibcon#about to read 4, iclass 3, count 0 2006.238.08:14:22.00#ibcon#read 4, iclass 3, count 0 2006.238.08:14:22.00#ibcon#about to read 5, iclass 3, count 0 2006.238.08:14:22.00#ibcon#read 5, iclass 3, count 0 2006.238.08:14:22.00#ibcon#about to read 6, iclass 3, count 0 2006.238.08:14:22.00#ibcon#read 6, iclass 3, count 0 2006.238.08:14:22.00#ibcon#end of sib2, iclass 3, count 0 2006.238.08:14:22.00#ibcon#*after write, iclass 3, count 0 2006.238.08:14:22.00#ibcon#*before return 0, iclass 3, count 0 2006.238.08:14:22.00#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:14:22.00#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:14:22.00#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.08:14:22.00#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.08:14:22.00$vc4f8/vblo=5,744.99 2006.238.08:14:22.00#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.08:14:22.00#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.08:14:22.00#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:22.00#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:14:22.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:14:22.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:14:22.00#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:14:22.00#ibcon#first serial, iclass 5, count 0 2006.238.08:14:22.00#ibcon#enter sib2, iclass 5, count 0 2006.238.08:14:22.00#ibcon#flushed, iclass 5, count 0 2006.238.08:14:22.00#ibcon#about to write, iclass 5, count 0 2006.238.08:14:22.00#ibcon#wrote, iclass 5, count 0 2006.238.08:14:22.00#ibcon#about to read 3, iclass 5, count 0 2006.238.08:14:22.02#ibcon#read 3, iclass 5, count 0 2006.238.08:14:22.02#ibcon#about to read 4, iclass 5, count 0 2006.238.08:14:22.02#ibcon#read 4, iclass 5, count 0 2006.238.08:14:22.02#ibcon#about to read 5, iclass 5, count 0 2006.238.08:14:22.02#ibcon#read 5, iclass 5, count 0 2006.238.08:14:22.02#ibcon#about to read 6, iclass 5, count 0 2006.238.08:14:22.02#ibcon#read 6, iclass 5, count 0 2006.238.08:14:22.02#ibcon#end of sib2, iclass 5, count 0 2006.238.08:14:22.02#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:14:22.02#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:14:22.02#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:14:22.02#ibcon#*before write, iclass 5, count 0 2006.238.08:14:22.02#ibcon#enter sib2, iclass 5, count 0 2006.238.08:14:22.02#ibcon#flushed, iclass 5, count 0 2006.238.08:14:22.02#ibcon#about to write, iclass 5, count 0 2006.238.08:14:22.02#ibcon#wrote, iclass 5, count 0 2006.238.08:14:22.02#ibcon#about to read 3, iclass 5, count 0 2006.238.08:14:22.06#ibcon#read 3, iclass 5, count 0 2006.238.08:14:22.06#ibcon#about to read 4, iclass 5, count 0 2006.238.08:14:22.06#ibcon#read 4, iclass 5, count 0 2006.238.08:14:22.06#ibcon#about to read 5, iclass 5, count 0 2006.238.08:14:22.06#ibcon#read 5, iclass 5, count 0 2006.238.08:14:22.06#ibcon#about to read 6, iclass 5, count 0 2006.238.08:14:22.06#ibcon#read 6, iclass 5, count 0 2006.238.08:14:22.06#ibcon#end of sib2, iclass 5, count 0 2006.238.08:14:22.06#ibcon#*after write, iclass 5, count 0 2006.238.08:14:22.06#ibcon#*before return 0, iclass 5, count 0 2006.238.08:14:22.06#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:14:22.06#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:14:22.06#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:14:22.06#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:14:22.06$vc4f8/vb=5,4 2006.238.08:14:22.06#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.08:14:22.06#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.08:14:22.06#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:22.06#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:14:22.12#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:14:22.12#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:14:22.12#ibcon#enter wrdev, iclass 7, count 2 2006.238.08:14:22.12#ibcon#first serial, iclass 7, count 2 2006.238.08:14:22.12#ibcon#enter sib2, iclass 7, count 2 2006.238.08:14:22.12#ibcon#flushed, iclass 7, count 2 2006.238.08:14:22.12#ibcon#about to write, iclass 7, count 2 2006.238.08:14:22.12#ibcon#wrote, iclass 7, count 2 2006.238.08:14:22.12#ibcon#about to read 3, iclass 7, count 2 2006.238.08:14:22.14#ibcon#read 3, iclass 7, count 2 2006.238.08:14:22.14#ibcon#about to read 4, iclass 7, count 2 2006.238.08:14:22.14#ibcon#read 4, iclass 7, count 2 2006.238.08:14:22.14#ibcon#about to read 5, iclass 7, count 2 2006.238.08:14:22.14#ibcon#read 5, iclass 7, count 2 2006.238.08:14:22.14#ibcon#about to read 6, iclass 7, count 2 2006.238.08:14:22.14#ibcon#read 6, iclass 7, count 2 2006.238.08:14:22.14#ibcon#end of sib2, iclass 7, count 2 2006.238.08:14:22.14#ibcon#*mode == 0, iclass 7, count 2 2006.238.08:14:22.14#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.08:14:22.14#ibcon#[27=AT05-04\r\n] 2006.238.08:14:22.14#ibcon#*before write, iclass 7, count 2 2006.238.08:14:22.14#ibcon#enter sib2, iclass 7, count 2 2006.238.08:14:22.14#ibcon#flushed, iclass 7, count 2 2006.238.08:14:22.14#ibcon#about to write, iclass 7, count 2 2006.238.08:14:22.14#ibcon#wrote, iclass 7, count 2 2006.238.08:14:22.14#ibcon#about to read 3, iclass 7, count 2 2006.238.08:14:22.17#ibcon#read 3, iclass 7, count 2 2006.238.08:14:22.17#ibcon#about to read 4, iclass 7, count 2 2006.238.08:14:22.17#ibcon#read 4, iclass 7, count 2 2006.238.08:14:22.17#ibcon#about to read 5, iclass 7, count 2 2006.238.08:14:22.17#ibcon#read 5, iclass 7, count 2 2006.238.08:14:22.17#ibcon#about to read 6, iclass 7, count 2 2006.238.08:14:22.17#ibcon#read 6, iclass 7, count 2 2006.238.08:14:22.17#ibcon#end of sib2, iclass 7, count 2 2006.238.08:14:22.17#ibcon#*after write, iclass 7, count 2 2006.238.08:14:22.17#ibcon#*before return 0, iclass 7, count 2 2006.238.08:14:22.17#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:14:22.17#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:14:22.17#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.08:14:22.17#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:22.17#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:14:22.29#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:14:22.29#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:14:22.29#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:14:22.29#ibcon#first serial, iclass 7, count 0 2006.238.08:14:22.29#ibcon#enter sib2, iclass 7, count 0 2006.238.08:14:22.29#ibcon#flushed, iclass 7, count 0 2006.238.08:14:22.29#ibcon#about to write, iclass 7, count 0 2006.238.08:14:22.29#ibcon#wrote, iclass 7, count 0 2006.238.08:14:22.29#ibcon#about to read 3, iclass 7, count 0 2006.238.08:14:22.31#ibcon#read 3, iclass 7, count 0 2006.238.08:14:22.31#ibcon#about to read 4, iclass 7, count 0 2006.238.08:14:22.31#ibcon#read 4, iclass 7, count 0 2006.238.08:14:22.31#ibcon#about to read 5, iclass 7, count 0 2006.238.08:14:22.31#ibcon#read 5, iclass 7, count 0 2006.238.08:14:22.31#ibcon#about to read 6, iclass 7, count 0 2006.238.08:14:22.31#ibcon#read 6, iclass 7, count 0 2006.238.08:14:22.31#ibcon#end of sib2, iclass 7, count 0 2006.238.08:14:22.31#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:14:22.31#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:14:22.31#ibcon#[27=USB\r\n] 2006.238.08:14:22.31#ibcon#*before write, iclass 7, count 0 2006.238.08:14:22.31#ibcon#enter sib2, iclass 7, count 0 2006.238.08:14:22.31#ibcon#flushed, iclass 7, count 0 2006.238.08:14:22.31#ibcon#about to write, iclass 7, count 0 2006.238.08:14:22.31#ibcon#wrote, iclass 7, count 0 2006.238.08:14:22.31#ibcon#about to read 3, iclass 7, count 0 2006.238.08:14:22.34#ibcon#read 3, iclass 7, count 0 2006.238.08:14:22.34#ibcon#about to read 4, iclass 7, count 0 2006.238.08:14:22.34#ibcon#read 4, iclass 7, count 0 2006.238.08:14:22.34#ibcon#about to read 5, iclass 7, count 0 2006.238.08:14:22.34#ibcon#read 5, iclass 7, count 0 2006.238.08:14:22.34#ibcon#about to read 6, iclass 7, count 0 2006.238.08:14:22.34#ibcon#read 6, iclass 7, count 0 2006.238.08:14:22.34#ibcon#end of sib2, iclass 7, count 0 2006.238.08:14:22.34#ibcon#*after write, iclass 7, count 0 2006.238.08:14:22.34#ibcon#*before return 0, iclass 7, count 0 2006.238.08:14:22.34#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:14:22.34#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:14:22.34#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:14:22.34#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:14:22.34$vc4f8/vblo=6,752.99 2006.238.08:14:22.34#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.08:14:22.34#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.08:14:22.34#ibcon#ireg 17 cls_cnt 0 2006.238.08:14:22.34#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:14:22.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:14:22.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:14:22.34#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:14:22.34#ibcon#first serial, iclass 11, count 0 2006.238.08:14:22.34#ibcon#enter sib2, iclass 11, count 0 2006.238.08:14:22.34#ibcon#flushed, iclass 11, count 0 2006.238.08:14:22.34#ibcon#about to write, iclass 11, count 0 2006.238.08:14:22.34#ibcon#wrote, iclass 11, count 0 2006.238.08:14:22.34#ibcon#about to read 3, iclass 11, count 0 2006.238.08:14:22.36#ibcon#read 3, iclass 11, count 0 2006.238.08:14:22.36#ibcon#about to read 4, iclass 11, count 0 2006.238.08:14:22.36#ibcon#read 4, iclass 11, count 0 2006.238.08:14:22.36#ibcon#about to read 5, iclass 11, count 0 2006.238.08:14:22.36#ibcon#read 5, iclass 11, count 0 2006.238.08:14:22.36#ibcon#about to read 6, iclass 11, count 0 2006.238.08:14:22.36#ibcon#read 6, iclass 11, count 0 2006.238.08:14:22.36#ibcon#end of sib2, iclass 11, count 0 2006.238.08:14:22.36#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:14:22.36#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:14:22.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:14:22.36#ibcon#*before write, iclass 11, count 0 2006.238.08:14:22.36#ibcon#enter sib2, iclass 11, count 0 2006.238.08:14:22.36#ibcon#flushed, iclass 11, count 0 2006.238.08:14:22.36#ibcon#about to write, iclass 11, count 0 2006.238.08:14:22.36#ibcon#wrote, iclass 11, count 0 2006.238.08:14:22.36#ibcon#about to read 3, iclass 11, count 0 2006.238.08:14:22.40#ibcon#read 3, iclass 11, count 0 2006.238.08:14:22.40#ibcon#about to read 4, iclass 11, count 0 2006.238.08:14:22.40#ibcon#read 4, iclass 11, count 0 2006.238.08:14:22.40#ibcon#about to read 5, iclass 11, count 0 2006.238.08:14:22.40#ibcon#read 5, iclass 11, count 0 2006.238.08:14:22.40#ibcon#about to read 6, iclass 11, count 0 2006.238.08:14:22.40#ibcon#read 6, iclass 11, count 0 2006.238.08:14:22.40#ibcon#end of sib2, iclass 11, count 0 2006.238.08:14:22.40#ibcon#*after write, iclass 11, count 0 2006.238.08:14:22.40#ibcon#*before return 0, iclass 11, count 0 2006.238.08:14:22.40#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:14:22.40#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:14:22.40#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:14:22.40#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:14:22.40$vc4f8/vb=6,4 2006.238.08:14:22.40#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.08:14:22.40#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.08:14:22.40#ibcon#ireg 11 cls_cnt 2 2006.238.08:14:22.40#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:14:22.46#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:14:22.46#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:14:22.46#ibcon#enter wrdev, iclass 13, count 2 2006.238.08:14:22.46#ibcon#first serial, iclass 13, count 2 2006.238.08:14:22.46#ibcon#enter sib2, iclass 13, count 2 2006.238.08:14:22.46#ibcon#flushed, iclass 13, count 2 2006.238.08:14:22.46#ibcon#about to write, iclass 13, count 2 2006.238.08:14:22.46#ibcon#wrote, iclass 13, count 2 2006.238.08:14:22.46#ibcon#about to read 3, iclass 13, count 2 2006.238.08:14:22.48#ibcon#read 3, iclass 13, count 2 2006.238.08:14:22.48#ibcon#about to read 4, iclass 13, count 2 2006.238.08:14:22.48#ibcon#read 4, iclass 13, count 2 2006.238.08:14:22.48#ibcon#about to read 5, iclass 13, count 2 2006.238.08:14:22.48#ibcon#read 5, iclass 13, count 2 2006.238.08:14:22.48#ibcon#about to read 6, iclass 13, count 2 2006.238.08:14:22.48#ibcon#read 6, iclass 13, count 2 2006.238.08:14:22.48#ibcon#end of sib2, iclass 13, count 2 2006.238.08:14:22.48#ibcon#*mode == 0, iclass 13, count 2 2006.238.08:14:22.48#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.08:14:22.48#ibcon#[27=AT06-04\r\n] 2006.238.08:14:22.48#ibcon#*before write, iclass 13, count 2 2006.238.08:14:22.48#ibcon#enter sib2, iclass 13, count 2 2006.238.08:14:22.48#ibcon#flushed, iclass 13, count 2 2006.238.08:14:22.48#ibcon#about to write, iclass 13, count 2 2006.238.08:14:22.48#ibcon#wrote, iclass 13, count 2 2006.238.08:14:22.48#ibcon#about to read 3, iclass 13, count 2 2006.238.08:14:22.51#ibcon#read 3, iclass 13, count 2 2006.238.08:14:22.51#ibcon#about to read 4, iclass 13, count 2 2006.238.08:14:22.51#ibcon#read 4, iclass 13, count 2 2006.238.08:14:22.51#ibcon#about to read 5, iclass 13, count 2 2006.238.08:14:22.51#ibcon#read 5, iclass 13, count 2 2006.238.08:14:22.51#ibcon#about to read 6, iclass 13, count 2 2006.238.08:14:22.51#ibcon#read 6, iclass 13, count 2 2006.238.08:14:22.51#ibcon#end of sib2, iclass 13, count 2 2006.238.08:14:22.51#ibcon#*after write, iclass 13, count 2 2006.238.08:14:22.51#ibcon#*before return 0, iclass 13, count 2 2006.238.08:14:22.51#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:14:22.51#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:14:22.51#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.08:14:22.51#ibcon#ireg 7 cls_cnt 0 2006.238.08:14:22.51#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:14:22.63#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:14:22.63#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:14:22.63#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:14:22.63#ibcon#first serial, iclass 13, count 0 2006.238.08:14:22.63#ibcon#enter sib2, iclass 13, count 0 2006.238.08:14:22.63#ibcon#flushed, iclass 13, count 0 2006.238.08:14:22.63#ibcon#about to write, iclass 13, count 0 2006.238.08:14:22.63#ibcon#wrote, iclass 13, count 0 2006.238.08:14:22.63#ibcon#about to read 3, iclass 13, count 0 2006.238.08:14:22.65#ibcon#read 3, iclass 13, count 0 2006.238.08:14:22.65#ibcon#about to read 4, iclass 13, count 0 2006.238.08:14:22.65#ibcon#read 4, iclass 13, count 0 2006.238.08:14:22.65#ibcon#about to read 5, iclass 13, count 0 2006.238.08:14:22.65#ibcon#read 5, iclass 13, count 0 2006.238.08:14:22.65#ibcon#about to read 6, iclass 13, count 0 2006.238.08:14:22.65#ibcon#read 6, iclass 13, count 0 2006.238.08:14:22.65#ibcon#end of sib2, iclass 13, count 0 2006.238.08:14:22.65#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:14:22.65#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:14:22.65#ibcon#[27=USB\r\n] 2006.238.08:14:22.65#ibcon#*before write, iclass 13, count 0 2006.238.08:14:22.65#ibcon#enter sib2, iclass 13, count 0 2006.238.08:14:22.65#ibcon#flushed, iclass 13, count 0 2006.238.08:14:22.65#ibcon#about to write, iclass 13, count 0 2006.238.08:14:22.65#ibcon#wrote, iclass 13, count 0 2006.238.08:14:22.65#ibcon#about to read 3, iclass 13, count 0 2006.238.08:14:22.68#ibcon#read 3, iclass 13, count 0 2006.238.08:14:22.68#ibcon#about to read 4, iclass 13, count 0 2006.238.08:14:22.68#ibcon#read 4, iclass 13, count 0 2006.238.08:14:22.68#ibcon#about to read 5, iclass 13, count 0 2006.238.08:14:22.68#ibcon#read 5, iclass 13, count 0 2006.238.08:14:22.68#ibcon#about to read 6, iclass 13, count 0 2006.238.08:14:22.68#ibcon#read 6, iclass 13, count 0 2006.238.08:14:22.68#ibcon#end of sib2, iclass 13, count 0 2006.238.08:14:22.68#ibcon#*after write, iclass 13, count 0 2006.238.08:14:22.68#ibcon#*before return 0, iclass 13, count 0 2006.238.08:14:22.68#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:14:22.68#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:14:22.68#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:14:22.68#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:14:22.68$vc4f8/vabw=wide 2006.238.08:14:22.68#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.08:14:22.68#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.08:14:22.68#ibcon#ireg 8 cls_cnt 0 2006.238.08:14:22.68#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:14:22.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:14:22.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:14:22.68#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:14:22.68#ibcon#first serial, iclass 15, count 0 2006.238.08:14:22.68#ibcon#enter sib2, iclass 15, count 0 2006.238.08:14:22.68#ibcon#flushed, iclass 15, count 0 2006.238.08:14:22.68#ibcon#about to write, iclass 15, count 0 2006.238.08:14:22.68#ibcon#wrote, iclass 15, count 0 2006.238.08:14:22.68#ibcon#about to read 3, iclass 15, count 0 2006.238.08:14:22.70#ibcon#read 3, iclass 15, count 0 2006.238.08:14:22.70#ibcon#about to read 4, iclass 15, count 0 2006.238.08:14:22.70#ibcon#read 4, iclass 15, count 0 2006.238.08:14:22.70#ibcon#about to read 5, iclass 15, count 0 2006.238.08:14:22.70#ibcon#read 5, iclass 15, count 0 2006.238.08:14:22.70#ibcon#about to read 6, iclass 15, count 0 2006.238.08:14:22.70#ibcon#read 6, iclass 15, count 0 2006.238.08:14:22.70#ibcon#end of sib2, iclass 15, count 0 2006.238.08:14:22.70#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:14:22.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:14:22.70#ibcon#[25=BW32\r\n] 2006.238.08:14:22.70#ibcon#*before write, iclass 15, count 0 2006.238.08:14:22.70#ibcon#enter sib2, iclass 15, count 0 2006.238.08:14:22.70#ibcon#flushed, iclass 15, count 0 2006.238.08:14:22.70#ibcon#about to write, iclass 15, count 0 2006.238.08:14:22.70#ibcon#wrote, iclass 15, count 0 2006.238.08:14:22.70#ibcon#about to read 3, iclass 15, count 0 2006.238.08:14:22.73#ibcon#read 3, iclass 15, count 0 2006.238.08:14:22.73#ibcon#about to read 4, iclass 15, count 0 2006.238.08:14:22.73#ibcon#read 4, iclass 15, count 0 2006.238.08:14:22.73#ibcon#about to read 5, iclass 15, count 0 2006.238.08:14:22.73#ibcon#read 5, iclass 15, count 0 2006.238.08:14:22.73#ibcon#about to read 6, iclass 15, count 0 2006.238.08:14:22.73#ibcon#read 6, iclass 15, count 0 2006.238.08:14:22.73#ibcon#end of sib2, iclass 15, count 0 2006.238.08:14:22.73#ibcon#*after write, iclass 15, count 0 2006.238.08:14:22.73#ibcon#*before return 0, iclass 15, count 0 2006.238.08:14:22.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:14:22.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:14:22.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:14:22.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:14:22.73$vc4f8/vbbw=wide 2006.238.08:14:22.73#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.08:14:22.73#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.08:14:22.73#ibcon#ireg 8 cls_cnt 0 2006.238.08:14:22.73#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:14:22.80#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:14:22.80#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:14:22.80#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:14:22.80#ibcon#first serial, iclass 17, count 0 2006.238.08:14:22.80#ibcon#enter sib2, iclass 17, count 0 2006.238.08:14:22.80#ibcon#flushed, iclass 17, count 0 2006.238.08:14:22.80#ibcon#about to write, iclass 17, count 0 2006.238.08:14:22.80#ibcon#wrote, iclass 17, count 0 2006.238.08:14:22.80#ibcon#about to read 3, iclass 17, count 0 2006.238.08:14:22.82#ibcon#read 3, iclass 17, count 0 2006.238.08:14:22.82#ibcon#about to read 4, iclass 17, count 0 2006.238.08:14:22.82#ibcon#read 4, iclass 17, count 0 2006.238.08:14:22.82#ibcon#about to read 5, iclass 17, count 0 2006.238.08:14:22.82#ibcon#read 5, iclass 17, count 0 2006.238.08:14:22.82#ibcon#about to read 6, iclass 17, count 0 2006.238.08:14:22.82#ibcon#read 6, iclass 17, count 0 2006.238.08:14:22.82#ibcon#end of sib2, iclass 17, count 0 2006.238.08:14:22.82#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:14:22.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:14:22.82#ibcon#[27=BW32\r\n] 2006.238.08:14:22.82#ibcon#*before write, iclass 17, count 0 2006.238.08:14:22.82#ibcon#enter sib2, iclass 17, count 0 2006.238.08:14:22.82#ibcon#flushed, iclass 17, count 0 2006.238.08:14:22.82#ibcon#about to write, iclass 17, count 0 2006.238.08:14:22.82#ibcon#wrote, iclass 17, count 0 2006.238.08:14:22.82#ibcon#about to read 3, iclass 17, count 0 2006.238.08:14:22.85#ibcon#read 3, iclass 17, count 0 2006.238.08:14:22.85#ibcon#about to read 4, iclass 17, count 0 2006.238.08:14:22.85#ibcon#read 4, iclass 17, count 0 2006.238.08:14:22.85#ibcon#about to read 5, iclass 17, count 0 2006.238.08:14:22.85#ibcon#read 5, iclass 17, count 0 2006.238.08:14:22.85#ibcon#about to read 6, iclass 17, count 0 2006.238.08:14:22.85#ibcon#read 6, iclass 17, count 0 2006.238.08:14:22.85#ibcon#end of sib2, iclass 17, count 0 2006.238.08:14:22.85#ibcon#*after write, iclass 17, count 0 2006.238.08:14:22.85#ibcon#*before return 0, iclass 17, count 0 2006.238.08:14:22.85#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:14:22.85#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:14:22.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:14:22.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:14:22.85$4f8m12a/ifd4f 2006.238.08:14:22.85$ifd4f/lo= 2006.238.08:14:22.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:14:22.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:14:22.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:14:22.85$ifd4f/patch= 2006.238.08:14:22.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:14:22.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:14:22.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:14:22.85$4f8m12a/"form=m,16.000,1:2 2006.238.08:14:22.85$4f8m12a/"tpicd 2006.238.08:14:22.85$4f8m12a/echo=off 2006.238.08:14:22.85$4f8m12a/xlog=off 2006.238.08:14:22.85:!2006.238.08:14:50 2006.238.08:14:31.14#trakl#Source acquired 2006.238.08:14:32.14#flagr#flagr/antenna,acquired 2006.238.08:14:50.00:preob 2006.238.08:14:51.14/onsource/TRACKING 2006.238.08:14:51.14:!2006.238.08:15:00 2006.238.08:15:00.00:data_valid=on 2006.238.08:15:00.00:midob 2006.238.08:15:00.14/onsource/TRACKING 2006.238.08:15:00.14/wx/25.47,1012.3,90 2006.238.08:15:00.25/cable/+6.4180E-03 2006.238.08:15:01.34/va/01,08,usb,yes,32,33 2006.238.08:15:01.34/va/02,07,usb,yes,32,33 2006.238.08:15:01.34/va/03,07,usb,yes,30,30 2006.238.08:15:01.34/va/04,07,usb,yes,33,36 2006.238.08:15:01.34/va/05,08,usb,yes,31,32 2006.238.08:15:01.34/va/06,07,usb,yes,33,33 2006.238.08:15:01.34/va/07,07,usb,yes,33,33 2006.238.08:15:01.34/va/08,07,usb,yes,36,35 2006.238.08:15:01.57/valo/01,532.99,yes,locked 2006.238.08:15:01.57/valo/02,572.99,yes,locked 2006.238.08:15:01.57/valo/03,672.99,yes,locked 2006.238.08:15:01.57/valo/04,832.99,yes,locked 2006.238.08:15:01.57/valo/05,652.99,yes,locked 2006.238.08:15:01.57/valo/06,772.99,yes,locked 2006.238.08:15:01.57/valo/07,832.99,yes,locked 2006.238.08:15:01.57/valo/08,852.99,yes,locked 2006.238.08:15:02.66/vb/01,04,usb,yes,31,29 2006.238.08:15:02.66/vb/02,04,usb,yes,32,34 2006.238.08:15:02.66/vb/03,04,usb,yes,29,33 2006.238.08:15:02.66/vb/04,04,usb,yes,30,30 2006.238.08:15:02.66/vb/05,04,usb,yes,28,32 2006.238.08:15:02.66/vb/06,04,usb,yes,29,32 2006.238.08:15:02.66/vb/07,04,usb,yes,31,31 2006.238.08:15:02.66/vb/08,04,usb,yes,29,32 2006.238.08:15:02.90/vblo/01,632.99,yes,locked 2006.238.08:15:02.90/vblo/02,640.99,yes,locked 2006.238.08:15:02.90/vblo/03,656.99,yes,locked 2006.238.08:15:02.90/vblo/04,712.99,yes,locked 2006.238.08:15:02.90/vblo/05,744.99,yes,locked 2006.238.08:15:02.90/vblo/06,752.99,yes,locked 2006.238.08:15:02.90/vblo/07,734.99,yes,locked 2006.238.08:15:02.90/vblo/08,744.99,yes,locked 2006.238.08:15:03.05/vabw/8 2006.238.08:15:03.20/vbbw/8 2006.238.08:15:03.30/xfe/off,on,12.7 2006.238.08:15:03.68/ifatt/23,28,28,28 2006.238.08:15:04.08/fmout-gps/S +4.44E-07 2006.238.08:15:04.12:!2006.238.08:16:00 2006.238.08:16:00.00:data_valid=off 2006.238.08:16:00.00:postob 2006.238.08:16:00.13/cable/+6.4167E-03 2006.238.08:16:00.13/wx/25.47,1012.3,91 2006.238.08:16:01.07/fmout-gps/S +4.45E-07 2006.238.08:16:01.07:scan_name=238-0816,k06238,60 2006.238.08:16:01.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.238.08:16:01.15#flagr#flagr/antenna,new-source 2006.238.08:16:02.13:checkk5 2006.238.08:16:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:16:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:16:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:16:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:16:04.02/chk_obsdata//k5ts1/T2380815??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:16:04.40/chk_obsdata//k5ts2/T2380815??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:16:04.77/chk_obsdata//k5ts3/T2380815??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:16:05.14/chk_obsdata//k5ts4/T2380815??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:16:05.84/k5log//k5ts1_log_newline 2006.238.08:16:06.53/k5log//k5ts2_log_newline 2006.238.08:16:07.23/k5log//k5ts3_log_newline 2006.238.08:16:07.93/k5log//k5ts4_log_newline 2006.238.08:16:07.96/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:16:07.96:4f8m12a=2 2006.238.08:16:07.96$4f8m12a/echo=on 2006.238.08:16:07.96$4f8m12a/pcalon 2006.238.08:16:07.96$pcalon/"no phase cal control is implemented here 2006.238.08:16:07.96$4f8m12a/"tpicd=stop 2006.238.08:16:07.96$4f8m12a/vc4f8 2006.238.08:16:07.96$vc4f8/valo=1,532.99 2006.238.08:16:07.96#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.08:16:07.96#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.08:16:07.96#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:07.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:16:07.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:16:07.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:16:07.96#ibcon#enter wrdev, iclass 24, count 0 2006.238.08:16:07.96#ibcon#first serial, iclass 24, count 0 2006.238.08:16:07.96#ibcon#enter sib2, iclass 24, count 0 2006.238.08:16:07.96#ibcon#flushed, iclass 24, count 0 2006.238.08:16:07.96#ibcon#about to write, iclass 24, count 0 2006.238.08:16:07.96#ibcon#wrote, iclass 24, count 0 2006.238.08:16:07.96#ibcon#about to read 3, iclass 24, count 0 2006.238.08:16:08.01#ibcon#read 3, iclass 24, count 0 2006.238.08:16:08.01#ibcon#about to read 4, iclass 24, count 0 2006.238.08:16:08.01#ibcon#read 4, iclass 24, count 0 2006.238.08:16:08.01#ibcon#about to read 5, iclass 24, count 0 2006.238.08:16:08.01#ibcon#read 5, iclass 24, count 0 2006.238.08:16:08.01#ibcon#about to read 6, iclass 24, count 0 2006.238.08:16:08.01#ibcon#read 6, iclass 24, count 0 2006.238.08:16:08.01#ibcon#end of sib2, iclass 24, count 0 2006.238.08:16:08.01#ibcon#*mode == 0, iclass 24, count 0 2006.238.08:16:08.01#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.08:16:08.01#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:16:08.01#ibcon#*before write, iclass 24, count 0 2006.238.08:16:08.01#ibcon#enter sib2, iclass 24, count 0 2006.238.08:16:08.01#ibcon#flushed, iclass 24, count 0 2006.238.08:16:08.01#ibcon#about to write, iclass 24, count 0 2006.238.08:16:08.01#ibcon#wrote, iclass 24, count 0 2006.238.08:16:08.01#ibcon#about to read 3, iclass 24, count 0 2006.238.08:16:08.05#ibcon#read 3, iclass 24, count 0 2006.238.08:16:08.05#ibcon#about to read 4, iclass 24, count 0 2006.238.08:16:08.05#ibcon#read 4, iclass 24, count 0 2006.238.08:16:08.05#ibcon#about to read 5, iclass 24, count 0 2006.238.08:16:08.05#ibcon#read 5, iclass 24, count 0 2006.238.08:16:08.05#ibcon#about to read 6, iclass 24, count 0 2006.238.08:16:08.05#ibcon#read 6, iclass 24, count 0 2006.238.08:16:08.05#ibcon#end of sib2, iclass 24, count 0 2006.238.08:16:08.05#ibcon#*after write, iclass 24, count 0 2006.238.08:16:08.05#ibcon#*before return 0, iclass 24, count 0 2006.238.08:16:08.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:16:08.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:16:08.05#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.08:16:08.05#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.08:16:08.05$vc4f8/va=1,8 2006.238.08:16:08.05#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.238.08:16:08.05#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.238.08:16:08.05#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:08.05#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:16:08.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:16:08.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:16:08.05#ibcon#enter wrdev, iclass 26, count 2 2006.238.08:16:08.05#ibcon#first serial, iclass 26, count 2 2006.238.08:16:08.05#ibcon#enter sib2, iclass 26, count 2 2006.238.08:16:08.05#ibcon#flushed, iclass 26, count 2 2006.238.08:16:08.05#ibcon#about to write, iclass 26, count 2 2006.238.08:16:08.05#ibcon#wrote, iclass 26, count 2 2006.238.08:16:08.05#ibcon#about to read 3, iclass 26, count 2 2006.238.08:16:08.07#ibcon#read 3, iclass 26, count 2 2006.238.08:16:08.07#ibcon#about to read 4, iclass 26, count 2 2006.238.08:16:08.07#ibcon#read 4, iclass 26, count 2 2006.238.08:16:08.07#ibcon#about to read 5, iclass 26, count 2 2006.238.08:16:08.07#ibcon#read 5, iclass 26, count 2 2006.238.08:16:08.07#ibcon#about to read 6, iclass 26, count 2 2006.238.08:16:08.07#ibcon#read 6, iclass 26, count 2 2006.238.08:16:08.07#ibcon#end of sib2, iclass 26, count 2 2006.238.08:16:08.07#ibcon#*mode == 0, iclass 26, count 2 2006.238.08:16:08.07#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.238.08:16:08.07#ibcon#[25=AT01-08\r\n] 2006.238.08:16:08.07#ibcon#*before write, iclass 26, count 2 2006.238.08:16:08.07#ibcon#enter sib2, iclass 26, count 2 2006.238.08:16:08.07#ibcon#flushed, iclass 26, count 2 2006.238.08:16:08.07#ibcon#about to write, iclass 26, count 2 2006.238.08:16:08.07#ibcon#wrote, iclass 26, count 2 2006.238.08:16:08.07#ibcon#about to read 3, iclass 26, count 2 2006.238.08:16:08.10#ibcon#read 3, iclass 26, count 2 2006.238.08:16:08.10#ibcon#about to read 4, iclass 26, count 2 2006.238.08:16:08.10#ibcon#read 4, iclass 26, count 2 2006.238.08:16:08.10#ibcon#about to read 5, iclass 26, count 2 2006.238.08:16:08.10#ibcon#read 5, iclass 26, count 2 2006.238.08:16:08.10#ibcon#about to read 6, iclass 26, count 2 2006.238.08:16:08.10#ibcon#read 6, iclass 26, count 2 2006.238.08:16:08.10#ibcon#end of sib2, iclass 26, count 2 2006.238.08:16:08.10#ibcon#*after write, iclass 26, count 2 2006.238.08:16:08.10#ibcon#*before return 0, iclass 26, count 2 2006.238.08:16:08.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:16:08.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:16:08.10#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.238.08:16:08.10#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:08.10#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:16:08.22#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:16:08.22#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:16:08.22#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:16:08.22#ibcon#first serial, iclass 26, count 0 2006.238.08:16:08.22#ibcon#enter sib2, iclass 26, count 0 2006.238.08:16:08.22#ibcon#flushed, iclass 26, count 0 2006.238.08:16:08.22#ibcon#about to write, iclass 26, count 0 2006.238.08:16:08.22#ibcon#wrote, iclass 26, count 0 2006.238.08:16:08.22#ibcon#about to read 3, iclass 26, count 0 2006.238.08:16:08.24#ibcon#read 3, iclass 26, count 0 2006.238.08:16:08.24#ibcon#about to read 4, iclass 26, count 0 2006.238.08:16:08.24#ibcon#read 4, iclass 26, count 0 2006.238.08:16:08.24#ibcon#about to read 5, iclass 26, count 0 2006.238.08:16:08.24#ibcon#read 5, iclass 26, count 0 2006.238.08:16:08.24#ibcon#about to read 6, iclass 26, count 0 2006.238.08:16:08.24#ibcon#read 6, iclass 26, count 0 2006.238.08:16:08.24#ibcon#end of sib2, iclass 26, count 0 2006.238.08:16:08.24#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:16:08.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:16:08.24#ibcon#[25=USB\r\n] 2006.238.08:16:08.24#ibcon#*before write, iclass 26, count 0 2006.238.08:16:08.24#ibcon#enter sib2, iclass 26, count 0 2006.238.08:16:08.24#ibcon#flushed, iclass 26, count 0 2006.238.08:16:08.24#ibcon#about to write, iclass 26, count 0 2006.238.08:16:08.24#ibcon#wrote, iclass 26, count 0 2006.238.08:16:08.24#ibcon#about to read 3, iclass 26, count 0 2006.238.08:16:08.27#ibcon#read 3, iclass 26, count 0 2006.238.08:16:08.27#ibcon#about to read 4, iclass 26, count 0 2006.238.08:16:08.27#ibcon#read 4, iclass 26, count 0 2006.238.08:16:08.27#ibcon#about to read 5, iclass 26, count 0 2006.238.08:16:08.27#ibcon#read 5, iclass 26, count 0 2006.238.08:16:08.27#ibcon#about to read 6, iclass 26, count 0 2006.238.08:16:08.27#ibcon#read 6, iclass 26, count 0 2006.238.08:16:08.27#ibcon#end of sib2, iclass 26, count 0 2006.238.08:16:08.27#ibcon#*after write, iclass 26, count 0 2006.238.08:16:08.27#ibcon#*before return 0, iclass 26, count 0 2006.238.08:16:08.27#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:16:08.27#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:16:08.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:16:08.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:16:08.27$vc4f8/valo=2,572.99 2006.238.08:16:08.27#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.238.08:16:08.27#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.238.08:16:08.27#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:08.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:16:08.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:16:08.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:16:08.27#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:16:08.27#ibcon#first serial, iclass 28, count 0 2006.238.08:16:08.27#ibcon#enter sib2, iclass 28, count 0 2006.238.08:16:08.27#ibcon#flushed, iclass 28, count 0 2006.238.08:16:08.27#ibcon#about to write, iclass 28, count 0 2006.238.08:16:08.27#ibcon#wrote, iclass 28, count 0 2006.238.08:16:08.27#ibcon#about to read 3, iclass 28, count 0 2006.238.08:16:08.29#ibcon#read 3, iclass 28, count 0 2006.238.08:16:08.29#ibcon#about to read 4, iclass 28, count 0 2006.238.08:16:08.29#ibcon#read 4, iclass 28, count 0 2006.238.08:16:08.29#ibcon#about to read 5, iclass 28, count 0 2006.238.08:16:08.29#ibcon#read 5, iclass 28, count 0 2006.238.08:16:08.29#ibcon#about to read 6, iclass 28, count 0 2006.238.08:16:08.29#ibcon#read 6, iclass 28, count 0 2006.238.08:16:08.29#ibcon#end of sib2, iclass 28, count 0 2006.238.08:16:08.29#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:16:08.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:16:08.29#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:16:08.29#ibcon#*before write, iclass 28, count 0 2006.238.08:16:08.29#ibcon#enter sib2, iclass 28, count 0 2006.238.08:16:08.29#ibcon#flushed, iclass 28, count 0 2006.238.08:16:08.29#ibcon#about to write, iclass 28, count 0 2006.238.08:16:08.29#ibcon#wrote, iclass 28, count 0 2006.238.08:16:08.29#ibcon#about to read 3, iclass 28, count 0 2006.238.08:16:08.33#ibcon#read 3, iclass 28, count 0 2006.238.08:16:08.33#ibcon#about to read 4, iclass 28, count 0 2006.238.08:16:08.33#ibcon#read 4, iclass 28, count 0 2006.238.08:16:08.33#ibcon#about to read 5, iclass 28, count 0 2006.238.08:16:08.33#ibcon#read 5, iclass 28, count 0 2006.238.08:16:08.33#ibcon#about to read 6, iclass 28, count 0 2006.238.08:16:08.33#ibcon#read 6, iclass 28, count 0 2006.238.08:16:08.33#ibcon#end of sib2, iclass 28, count 0 2006.238.08:16:08.33#ibcon#*after write, iclass 28, count 0 2006.238.08:16:08.33#ibcon#*before return 0, iclass 28, count 0 2006.238.08:16:08.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:16:08.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:16:08.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:16:08.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:16:08.33$vc4f8/va=2,7 2006.238.08:16:08.33#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.238.08:16:08.33#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.238.08:16:08.33#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:08.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:16:08.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:16:08.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:16:08.39#ibcon#enter wrdev, iclass 30, count 2 2006.238.08:16:08.39#ibcon#first serial, iclass 30, count 2 2006.238.08:16:08.39#ibcon#enter sib2, iclass 30, count 2 2006.238.08:16:08.39#ibcon#flushed, iclass 30, count 2 2006.238.08:16:08.39#ibcon#about to write, iclass 30, count 2 2006.238.08:16:08.39#ibcon#wrote, iclass 30, count 2 2006.238.08:16:08.39#ibcon#about to read 3, iclass 30, count 2 2006.238.08:16:08.41#ibcon#read 3, iclass 30, count 2 2006.238.08:16:08.41#ibcon#about to read 4, iclass 30, count 2 2006.238.08:16:08.41#ibcon#read 4, iclass 30, count 2 2006.238.08:16:08.41#ibcon#about to read 5, iclass 30, count 2 2006.238.08:16:08.41#ibcon#read 5, iclass 30, count 2 2006.238.08:16:08.41#ibcon#about to read 6, iclass 30, count 2 2006.238.08:16:08.41#ibcon#read 6, iclass 30, count 2 2006.238.08:16:08.41#ibcon#end of sib2, iclass 30, count 2 2006.238.08:16:08.41#ibcon#*mode == 0, iclass 30, count 2 2006.238.08:16:08.41#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.238.08:16:08.41#ibcon#[25=AT02-07\r\n] 2006.238.08:16:08.41#ibcon#*before write, iclass 30, count 2 2006.238.08:16:08.41#ibcon#enter sib2, iclass 30, count 2 2006.238.08:16:08.41#ibcon#flushed, iclass 30, count 2 2006.238.08:16:08.41#ibcon#about to write, iclass 30, count 2 2006.238.08:16:08.41#ibcon#wrote, iclass 30, count 2 2006.238.08:16:08.41#ibcon#about to read 3, iclass 30, count 2 2006.238.08:16:08.44#ibcon#read 3, iclass 30, count 2 2006.238.08:16:08.44#ibcon#about to read 4, iclass 30, count 2 2006.238.08:16:08.44#ibcon#read 4, iclass 30, count 2 2006.238.08:16:08.44#ibcon#about to read 5, iclass 30, count 2 2006.238.08:16:08.44#ibcon#read 5, iclass 30, count 2 2006.238.08:16:08.44#ibcon#about to read 6, iclass 30, count 2 2006.238.08:16:08.44#ibcon#read 6, iclass 30, count 2 2006.238.08:16:08.44#ibcon#end of sib2, iclass 30, count 2 2006.238.08:16:08.44#ibcon#*after write, iclass 30, count 2 2006.238.08:16:08.44#ibcon#*before return 0, iclass 30, count 2 2006.238.08:16:08.44#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:16:08.44#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:16:08.44#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.238.08:16:08.44#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:08.44#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:16:08.56#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:16:08.56#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:16:08.56#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:16:08.56#ibcon#first serial, iclass 30, count 0 2006.238.08:16:08.56#ibcon#enter sib2, iclass 30, count 0 2006.238.08:16:08.56#ibcon#flushed, iclass 30, count 0 2006.238.08:16:08.56#ibcon#about to write, iclass 30, count 0 2006.238.08:16:08.56#ibcon#wrote, iclass 30, count 0 2006.238.08:16:08.56#ibcon#about to read 3, iclass 30, count 0 2006.238.08:16:08.58#ibcon#read 3, iclass 30, count 0 2006.238.08:16:08.58#ibcon#about to read 4, iclass 30, count 0 2006.238.08:16:08.58#ibcon#read 4, iclass 30, count 0 2006.238.08:16:08.58#ibcon#about to read 5, iclass 30, count 0 2006.238.08:16:08.58#ibcon#read 5, iclass 30, count 0 2006.238.08:16:08.58#ibcon#about to read 6, iclass 30, count 0 2006.238.08:16:08.58#ibcon#read 6, iclass 30, count 0 2006.238.08:16:08.58#ibcon#end of sib2, iclass 30, count 0 2006.238.08:16:08.58#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:16:08.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:16:08.58#ibcon#[25=USB\r\n] 2006.238.08:16:08.58#ibcon#*before write, iclass 30, count 0 2006.238.08:16:08.58#ibcon#enter sib2, iclass 30, count 0 2006.238.08:16:08.58#ibcon#flushed, iclass 30, count 0 2006.238.08:16:08.58#ibcon#about to write, iclass 30, count 0 2006.238.08:16:08.58#ibcon#wrote, iclass 30, count 0 2006.238.08:16:08.58#ibcon#about to read 3, iclass 30, count 0 2006.238.08:16:08.61#ibcon#read 3, iclass 30, count 0 2006.238.08:16:08.61#ibcon#about to read 4, iclass 30, count 0 2006.238.08:16:08.61#ibcon#read 4, iclass 30, count 0 2006.238.08:16:08.61#ibcon#about to read 5, iclass 30, count 0 2006.238.08:16:08.61#ibcon#read 5, iclass 30, count 0 2006.238.08:16:08.61#ibcon#about to read 6, iclass 30, count 0 2006.238.08:16:08.61#ibcon#read 6, iclass 30, count 0 2006.238.08:16:08.61#ibcon#end of sib2, iclass 30, count 0 2006.238.08:16:08.61#ibcon#*after write, iclass 30, count 0 2006.238.08:16:08.61#ibcon#*before return 0, iclass 30, count 0 2006.238.08:16:08.61#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:16:08.61#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:16:08.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:16:08.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:16:08.61$vc4f8/valo=3,672.99 2006.238.08:16:08.61#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.08:16:08.61#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.08:16:08.61#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:08.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:16:08.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:16:08.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:16:08.61#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:16:08.61#ibcon#first serial, iclass 32, count 0 2006.238.08:16:08.61#ibcon#enter sib2, iclass 32, count 0 2006.238.08:16:08.61#ibcon#flushed, iclass 32, count 0 2006.238.08:16:08.61#ibcon#about to write, iclass 32, count 0 2006.238.08:16:08.61#ibcon#wrote, iclass 32, count 0 2006.238.08:16:08.61#ibcon#about to read 3, iclass 32, count 0 2006.238.08:16:08.63#ibcon#read 3, iclass 32, count 0 2006.238.08:16:08.63#ibcon#about to read 4, iclass 32, count 0 2006.238.08:16:08.63#ibcon#read 4, iclass 32, count 0 2006.238.08:16:08.63#ibcon#about to read 5, iclass 32, count 0 2006.238.08:16:08.63#ibcon#read 5, iclass 32, count 0 2006.238.08:16:08.63#ibcon#about to read 6, iclass 32, count 0 2006.238.08:16:08.63#ibcon#read 6, iclass 32, count 0 2006.238.08:16:08.63#ibcon#end of sib2, iclass 32, count 0 2006.238.08:16:08.63#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:16:08.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:16:08.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:16:08.63#ibcon#*before write, iclass 32, count 0 2006.238.08:16:08.63#ibcon#enter sib2, iclass 32, count 0 2006.238.08:16:08.63#ibcon#flushed, iclass 32, count 0 2006.238.08:16:08.63#ibcon#about to write, iclass 32, count 0 2006.238.08:16:08.63#ibcon#wrote, iclass 32, count 0 2006.238.08:16:08.63#ibcon#about to read 3, iclass 32, count 0 2006.238.08:16:08.67#ibcon#read 3, iclass 32, count 0 2006.238.08:16:08.67#ibcon#about to read 4, iclass 32, count 0 2006.238.08:16:08.67#ibcon#read 4, iclass 32, count 0 2006.238.08:16:08.67#ibcon#about to read 5, iclass 32, count 0 2006.238.08:16:08.67#ibcon#read 5, iclass 32, count 0 2006.238.08:16:08.67#ibcon#about to read 6, iclass 32, count 0 2006.238.08:16:08.67#ibcon#read 6, iclass 32, count 0 2006.238.08:16:08.67#ibcon#end of sib2, iclass 32, count 0 2006.238.08:16:08.67#ibcon#*after write, iclass 32, count 0 2006.238.08:16:08.67#ibcon#*before return 0, iclass 32, count 0 2006.238.08:16:08.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:16:08.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:16:08.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:16:08.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:16:08.67$vc4f8/va=3,7 2006.238.08:16:08.67#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.238.08:16:08.67#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.238.08:16:08.67#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:08.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:16:08.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:16:08.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:16:08.73#ibcon#enter wrdev, iclass 34, count 2 2006.238.08:16:08.73#ibcon#first serial, iclass 34, count 2 2006.238.08:16:08.73#ibcon#enter sib2, iclass 34, count 2 2006.238.08:16:08.73#ibcon#flushed, iclass 34, count 2 2006.238.08:16:08.73#ibcon#about to write, iclass 34, count 2 2006.238.08:16:08.73#ibcon#wrote, iclass 34, count 2 2006.238.08:16:08.73#ibcon#about to read 3, iclass 34, count 2 2006.238.08:16:08.75#ibcon#read 3, iclass 34, count 2 2006.238.08:16:08.75#ibcon#about to read 4, iclass 34, count 2 2006.238.08:16:08.75#ibcon#read 4, iclass 34, count 2 2006.238.08:16:08.75#ibcon#about to read 5, iclass 34, count 2 2006.238.08:16:08.75#ibcon#read 5, iclass 34, count 2 2006.238.08:16:08.75#ibcon#about to read 6, iclass 34, count 2 2006.238.08:16:08.75#ibcon#read 6, iclass 34, count 2 2006.238.08:16:08.75#ibcon#end of sib2, iclass 34, count 2 2006.238.08:16:08.75#ibcon#*mode == 0, iclass 34, count 2 2006.238.08:16:08.75#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.238.08:16:08.75#ibcon#[25=AT03-07\r\n] 2006.238.08:16:08.75#ibcon#*before write, iclass 34, count 2 2006.238.08:16:08.75#ibcon#enter sib2, iclass 34, count 2 2006.238.08:16:08.75#ibcon#flushed, iclass 34, count 2 2006.238.08:16:08.75#ibcon#about to write, iclass 34, count 2 2006.238.08:16:08.75#ibcon#wrote, iclass 34, count 2 2006.238.08:16:08.75#ibcon#about to read 3, iclass 34, count 2 2006.238.08:16:08.78#ibcon#read 3, iclass 34, count 2 2006.238.08:16:08.78#ibcon#about to read 4, iclass 34, count 2 2006.238.08:16:08.78#ibcon#read 4, iclass 34, count 2 2006.238.08:16:08.78#ibcon#about to read 5, iclass 34, count 2 2006.238.08:16:08.78#ibcon#read 5, iclass 34, count 2 2006.238.08:16:08.78#ibcon#about to read 6, iclass 34, count 2 2006.238.08:16:08.78#ibcon#read 6, iclass 34, count 2 2006.238.08:16:08.78#ibcon#end of sib2, iclass 34, count 2 2006.238.08:16:08.78#ibcon#*after write, iclass 34, count 2 2006.238.08:16:08.78#ibcon#*before return 0, iclass 34, count 2 2006.238.08:16:08.78#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:16:08.78#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:16:08.78#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.238.08:16:08.78#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:08.78#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:16:08.90#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:16:08.90#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:16:08.90#ibcon#enter wrdev, iclass 34, count 0 2006.238.08:16:08.90#ibcon#first serial, iclass 34, count 0 2006.238.08:16:08.90#ibcon#enter sib2, iclass 34, count 0 2006.238.08:16:08.90#ibcon#flushed, iclass 34, count 0 2006.238.08:16:08.90#ibcon#about to write, iclass 34, count 0 2006.238.08:16:08.90#ibcon#wrote, iclass 34, count 0 2006.238.08:16:08.90#ibcon#about to read 3, iclass 34, count 0 2006.238.08:16:08.92#ibcon#read 3, iclass 34, count 0 2006.238.08:16:08.92#ibcon#about to read 4, iclass 34, count 0 2006.238.08:16:08.92#ibcon#read 4, iclass 34, count 0 2006.238.08:16:08.92#ibcon#about to read 5, iclass 34, count 0 2006.238.08:16:08.92#ibcon#read 5, iclass 34, count 0 2006.238.08:16:08.92#ibcon#about to read 6, iclass 34, count 0 2006.238.08:16:08.92#ibcon#read 6, iclass 34, count 0 2006.238.08:16:08.92#ibcon#end of sib2, iclass 34, count 0 2006.238.08:16:08.92#ibcon#*mode == 0, iclass 34, count 0 2006.238.08:16:08.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.08:16:08.92#ibcon#[25=USB\r\n] 2006.238.08:16:08.92#ibcon#*before write, iclass 34, count 0 2006.238.08:16:08.92#ibcon#enter sib2, iclass 34, count 0 2006.238.08:16:08.92#ibcon#flushed, iclass 34, count 0 2006.238.08:16:08.92#ibcon#about to write, iclass 34, count 0 2006.238.08:16:08.92#ibcon#wrote, iclass 34, count 0 2006.238.08:16:08.92#ibcon#about to read 3, iclass 34, count 0 2006.238.08:16:08.95#ibcon#read 3, iclass 34, count 0 2006.238.08:16:08.95#ibcon#about to read 4, iclass 34, count 0 2006.238.08:16:08.95#ibcon#read 4, iclass 34, count 0 2006.238.08:16:08.95#ibcon#about to read 5, iclass 34, count 0 2006.238.08:16:08.95#ibcon#read 5, iclass 34, count 0 2006.238.08:16:08.95#ibcon#about to read 6, iclass 34, count 0 2006.238.08:16:08.95#ibcon#read 6, iclass 34, count 0 2006.238.08:16:08.95#ibcon#end of sib2, iclass 34, count 0 2006.238.08:16:08.95#ibcon#*after write, iclass 34, count 0 2006.238.08:16:08.95#ibcon#*before return 0, iclass 34, count 0 2006.238.08:16:08.95#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:16:08.95#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:16:08.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.08:16:08.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.08:16:08.95$vc4f8/valo=4,832.99 2006.238.08:16:08.95#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.08:16:08.95#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.08:16:08.95#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:08.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:16:08.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:16:08.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:16:08.95#ibcon#enter wrdev, iclass 36, count 0 2006.238.08:16:08.95#ibcon#first serial, iclass 36, count 0 2006.238.08:16:08.95#ibcon#enter sib2, iclass 36, count 0 2006.238.08:16:08.95#ibcon#flushed, iclass 36, count 0 2006.238.08:16:08.95#ibcon#about to write, iclass 36, count 0 2006.238.08:16:08.95#ibcon#wrote, iclass 36, count 0 2006.238.08:16:08.95#ibcon#about to read 3, iclass 36, count 0 2006.238.08:16:08.97#ibcon#read 3, iclass 36, count 0 2006.238.08:16:08.97#ibcon#about to read 4, iclass 36, count 0 2006.238.08:16:08.97#ibcon#read 4, iclass 36, count 0 2006.238.08:16:08.97#ibcon#about to read 5, iclass 36, count 0 2006.238.08:16:08.97#ibcon#read 5, iclass 36, count 0 2006.238.08:16:08.97#ibcon#about to read 6, iclass 36, count 0 2006.238.08:16:08.97#ibcon#read 6, iclass 36, count 0 2006.238.08:16:08.97#ibcon#end of sib2, iclass 36, count 0 2006.238.08:16:08.97#ibcon#*mode == 0, iclass 36, count 0 2006.238.08:16:08.97#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.08:16:08.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:16:08.97#ibcon#*before write, iclass 36, count 0 2006.238.08:16:08.97#ibcon#enter sib2, iclass 36, count 0 2006.238.08:16:08.97#ibcon#flushed, iclass 36, count 0 2006.238.08:16:08.97#ibcon#about to write, iclass 36, count 0 2006.238.08:16:08.97#ibcon#wrote, iclass 36, count 0 2006.238.08:16:08.97#ibcon#about to read 3, iclass 36, count 0 2006.238.08:16:09.01#ibcon#read 3, iclass 36, count 0 2006.238.08:16:09.01#ibcon#about to read 4, iclass 36, count 0 2006.238.08:16:09.01#ibcon#read 4, iclass 36, count 0 2006.238.08:16:09.01#ibcon#about to read 5, iclass 36, count 0 2006.238.08:16:09.01#ibcon#read 5, iclass 36, count 0 2006.238.08:16:09.01#ibcon#about to read 6, iclass 36, count 0 2006.238.08:16:09.01#ibcon#read 6, iclass 36, count 0 2006.238.08:16:09.01#ibcon#end of sib2, iclass 36, count 0 2006.238.08:16:09.01#ibcon#*after write, iclass 36, count 0 2006.238.08:16:09.01#ibcon#*before return 0, iclass 36, count 0 2006.238.08:16:09.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:16:09.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:16:09.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.08:16:09.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.08:16:09.01$vc4f8/va=4,7 2006.238.08:16:09.01#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.238.08:16:09.01#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.238.08:16:09.01#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:09.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:16:09.07#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:16:09.07#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:16:09.07#ibcon#enter wrdev, iclass 38, count 2 2006.238.08:16:09.07#ibcon#first serial, iclass 38, count 2 2006.238.08:16:09.07#ibcon#enter sib2, iclass 38, count 2 2006.238.08:16:09.07#ibcon#flushed, iclass 38, count 2 2006.238.08:16:09.07#ibcon#about to write, iclass 38, count 2 2006.238.08:16:09.07#ibcon#wrote, iclass 38, count 2 2006.238.08:16:09.07#ibcon#about to read 3, iclass 38, count 2 2006.238.08:16:09.09#ibcon#read 3, iclass 38, count 2 2006.238.08:16:09.09#ibcon#about to read 4, iclass 38, count 2 2006.238.08:16:09.09#ibcon#read 4, iclass 38, count 2 2006.238.08:16:09.09#ibcon#about to read 5, iclass 38, count 2 2006.238.08:16:09.09#ibcon#read 5, iclass 38, count 2 2006.238.08:16:09.09#ibcon#about to read 6, iclass 38, count 2 2006.238.08:16:09.09#ibcon#read 6, iclass 38, count 2 2006.238.08:16:09.09#ibcon#end of sib2, iclass 38, count 2 2006.238.08:16:09.09#ibcon#*mode == 0, iclass 38, count 2 2006.238.08:16:09.09#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.238.08:16:09.09#ibcon#[25=AT04-07\r\n] 2006.238.08:16:09.09#ibcon#*before write, iclass 38, count 2 2006.238.08:16:09.09#ibcon#enter sib2, iclass 38, count 2 2006.238.08:16:09.09#ibcon#flushed, iclass 38, count 2 2006.238.08:16:09.09#ibcon#about to write, iclass 38, count 2 2006.238.08:16:09.09#ibcon#wrote, iclass 38, count 2 2006.238.08:16:09.09#ibcon#about to read 3, iclass 38, count 2 2006.238.08:16:09.12#ibcon#read 3, iclass 38, count 2 2006.238.08:16:09.12#ibcon#about to read 4, iclass 38, count 2 2006.238.08:16:09.12#ibcon#read 4, iclass 38, count 2 2006.238.08:16:09.12#ibcon#about to read 5, iclass 38, count 2 2006.238.08:16:09.12#ibcon#read 5, iclass 38, count 2 2006.238.08:16:09.12#ibcon#about to read 6, iclass 38, count 2 2006.238.08:16:09.12#ibcon#read 6, iclass 38, count 2 2006.238.08:16:09.12#ibcon#end of sib2, iclass 38, count 2 2006.238.08:16:09.12#ibcon#*after write, iclass 38, count 2 2006.238.08:16:09.12#ibcon#*before return 0, iclass 38, count 2 2006.238.08:16:09.12#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:16:09.12#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:16:09.12#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.238.08:16:09.12#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:09.12#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:16:09.24#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:16:09.24#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:16:09.24#ibcon#enter wrdev, iclass 38, count 0 2006.238.08:16:09.24#ibcon#first serial, iclass 38, count 0 2006.238.08:16:09.24#ibcon#enter sib2, iclass 38, count 0 2006.238.08:16:09.24#ibcon#flushed, iclass 38, count 0 2006.238.08:16:09.24#ibcon#about to write, iclass 38, count 0 2006.238.08:16:09.24#ibcon#wrote, iclass 38, count 0 2006.238.08:16:09.24#ibcon#about to read 3, iclass 38, count 0 2006.238.08:16:09.26#ibcon#read 3, iclass 38, count 0 2006.238.08:16:09.26#ibcon#about to read 4, iclass 38, count 0 2006.238.08:16:09.26#ibcon#read 4, iclass 38, count 0 2006.238.08:16:09.26#ibcon#about to read 5, iclass 38, count 0 2006.238.08:16:09.26#ibcon#read 5, iclass 38, count 0 2006.238.08:16:09.26#ibcon#about to read 6, iclass 38, count 0 2006.238.08:16:09.26#ibcon#read 6, iclass 38, count 0 2006.238.08:16:09.26#ibcon#end of sib2, iclass 38, count 0 2006.238.08:16:09.26#ibcon#*mode == 0, iclass 38, count 0 2006.238.08:16:09.26#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.08:16:09.26#ibcon#[25=USB\r\n] 2006.238.08:16:09.26#ibcon#*before write, iclass 38, count 0 2006.238.08:16:09.26#ibcon#enter sib2, iclass 38, count 0 2006.238.08:16:09.26#ibcon#flushed, iclass 38, count 0 2006.238.08:16:09.26#ibcon#about to write, iclass 38, count 0 2006.238.08:16:09.26#ibcon#wrote, iclass 38, count 0 2006.238.08:16:09.26#ibcon#about to read 3, iclass 38, count 0 2006.238.08:16:09.29#ibcon#read 3, iclass 38, count 0 2006.238.08:16:09.29#ibcon#about to read 4, iclass 38, count 0 2006.238.08:16:09.29#ibcon#read 4, iclass 38, count 0 2006.238.08:16:09.29#ibcon#about to read 5, iclass 38, count 0 2006.238.08:16:09.29#ibcon#read 5, iclass 38, count 0 2006.238.08:16:09.29#ibcon#about to read 6, iclass 38, count 0 2006.238.08:16:09.29#ibcon#read 6, iclass 38, count 0 2006.238.08:16:09.29#ibcon#end of sib2, iclass 38, count 0 2006.238.08:16:09.29#ibcon#*after write, iclass 38, count 0 2006.238.08:16:09.29#ibcon#*before return 0, iclass 38, count 0 2006.238.08:16:09.29#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:16:09.29#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:16:09.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.08:16:09.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.08:16:09.29$vc4f8/valo=5,652.99 2006.238.08:16:09.29#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.08:16:09.29#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.08:16:09.29#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:09.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:16:09.29#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:16:09.29#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:16:09.29#ibcon#enter wrdev, iclass 40, count 0 2006.238.08:16:09.29#ibcon#first serial, iclass 40, count 0 2006.238.08:16:09.29#ibcon#enter sib2, iclass 40, count 0 2006.238.08:16:09.29#ibcon#flushed, iclass 40, count 0 2006.238.08:16:09.29#ibcon#about to write, iclass 40, count 0 2006.238.08:16:09.29#ibcon#wrote, iclass 40, count 0 2006.238.08:16:09.29#ibcon#about to read 3, iclass 40, count 0 2006.238.08:16:09.31#ibcon#read 3, iclass 40, count 0 2006.238.08:16:09.31#ibcon#about to read 4, iclass 40, count 0 2006.238.08:16:09.31#ibcon#read 4, iclass 40, count 0 2006.238.08:16:09.31#ibcon#about to read 5, iclass 40, count 0 2006.238.08:16:09.31#ibcon#read 5, iclass 40, count 0 2006.238.08:16:09.31#ibcon#about to read 6, iclass 40, count 0 2006.238.08:16:09.31#ibcon#read 6, iclass 40, count 0 2006.238.08:16:09.31#ibcon#end of sib2, iclass 40, count 0 2006.238.08:16:09.31#ibcon#*mode == 0, iclass 40, count 0 2006.238.08:16:09.31#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.08:16:09.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:16:09.31#ibcon#*before write, iclass 40, count 0 2006.238.08:16:09.31#ibcon#enter sib2, iclass 40, count 0 2006.238.08:16:09.31#ibcon#flushed, iclass 40, count 0 2006.238.08:16:09.31#ibcon#about to write, iclass 40, count 0 2006.238.08:16:09.31#ibcon#wrote, iclass 40, count 0 2006.238.08:16:09.31#ibcon#about to read 3, iclass 40, count 0 2006.238.08:16:09.35#ibcon#read 3, iclass 40, count 0 2006.238.08:16:09.35#ibcon#about to read 4, iclass 40, count 0 2006.238.08:16:09.35#ibcon#read 4, iclass 40, count 0 2006.238.08:16:09.35#ibcon#about to read 5, iclass 40, count 0 2006.238.08:16:09.35#ibcon#read 5, iclass 40, count 0 2006.238.08:16:09.35#ibcon#about to read 6, iclass 40, count 0 2006.238.08:16:09.35#ibcon#read 6, iclass 40, count 0 2006.238.08:16:09.35#ibcon#end of sib2, iclass 40, count 0 2006.238.08:16:09.35#ibcon#*after write, iclass 40, count 0 2006.238.08:16:09.35#ibcon#*before return 0, iclass 40, count 0 2006.238.08:16:09.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:16:09.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:16:09.35#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.08:16:09.35#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.08:16:09.35$vc4f8/va=5,8 2006.238.08:16:09.35#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.238.08:16:09.35#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.238.08:16:09.35#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:09.35#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:16:09.41#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:16:09.41#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:16:09.41#ibcon#enter wrdev, iclass 4, count 2 2006.238.08:16:09.41#ibcon#first serial, iclass 4, count 2 2006.238.08:16:09.41#ibcon#enter sib2, iclass 4, count 2 2006.238.08:16:09.41#ibcon#flushed, iclass 4, count 2 2006.238.08:16:09.41#ibcon#about to write, iclass 4, count 2 2006.238.08:16:09.41#ibcon#wrote, iclass 4, count 2 2006.238.08:16:09.41#ibcon#about to read 3, iclass 4, count 2 2006.238.08:16:09.43#ibcon#read 3, iclass 4, count 2 2006.238.08:16:09.43#ibcon#about to read 4, iclass 4, count 2 2006.238.08:16:09.43#ibcon#read 4, iclass 4, count 2 2006.238.08:16:09.43#ibcon#about to read 5, iclass 4, count 2 2006.238.08:16:09.43#ibcon#read 5, iclass 4, count 2 2006.238.08:16:09.43#ibcon#about to read 6, iclass 4, count 2 2006.238.08:16:09.43#ibcon#read 6, iclass 4, count 2 2006.238.08:16:09.43#ibcon#end of sib2, iclass 4, count 2 2006.238.08:16:09.43#ibcon#*mode == 0, iclass 4, count 2 2006.238.08:16:09.43#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.238.08:16:09.43#ibcon#[25=AT05-08\r\n] 2006.238.08:16:09.43#ibcon#*before write, iclass 4, count 2 2006.238.08:16:09.43#ibcon#enter sib2, iclass 4, count 2 2006.238.08:16:09.43#ibcon#flushed, iclass 4, count 2 2006.238.08:16:09.43#ibcon#about to write, iclass 4, count 2 2006.238.08:16:09.43#ibcon#wrote, iclass 4, count 2 2006.238.08:16:09.43#ibcon#about to read 3, iclass 4, count 2 2006.238.08:16:09.46#ibcon#read 3, iclass 4, count 2 2006.238.08:16:09.46#ibcon#about to read 4, iclass 4, count 2 2006.238.08:16:09.46#ibcon#read 4, iclass 4, count 2 2006.238.08:16:09.46#ibcon#about to read 5, iclass 4, count 2 2006.238.08:16:09.46#ibcon#read 5, iclass 4, count 2 2006.238.08:16:09.46#ibcon#about to read 6, iclass 4, count 2 2006.238.08:16:09.46#ibcon#read 6, iclass 4, count 2 2006.238.08:16:09.46#ibcon#end of sib2, iclass 4, count 2 2006.238.08:16:09.46#ibcon#*after write, iclass 4, count 2 2006.238.08:16:09.46#ibcon#*before return 0, iclass 4, count 2 2006.238.08:16:09.46#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:16:09.46#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:16:09.46#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.238.08:16:09.46#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:09.46#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:16:09.58#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:16:09.58#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:16:09.58#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:16:09.58#ibcon#first serial, iclass 4, count 0 2006.238.08:16:09.58#ibcon#enter sib2, iclass 4, count 0 2006.238.08:16:09.58#ibcon#flushed, iclass 4, count 0 2006.238.08:16:09.58#ibcon#about to write, iclass 4, count 0 2006.238.08:16:09.58#ibcon#wrote, iclass 4, count 0 2006.238.08:16:09.58#ibcon#about to read 3, iclass 4, count 0 2006.238.08:16:09.60#ibcon#read 3, iclass 4, count 0 2006.238.08:16:09.60#ibcon#about to read 4, iclass 4, count 0 2006.238.08:16:09.60#ibcon#read 4, iclass 4, count 0 2006.238.08:16:09.60#ibcon#about to read 5, iclass 4, count 0 2006.238.08:16:09.60#ibcon#read 5, iclass 4, count 0 2006.238.08:16:09.60#ibcon#about to read 6, iclass 4, count 0 2006.238.08:16:09.60#ibcon#read 6, iclass 4, count 0 2006.238.08:16:09.60#ibcon#end of sib2, iclass 4, count 0 2006.238.08:16:09.60#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:16:09.60#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:16:09.60#ibcon#[25=USB\r\n] 2006.238.08:16:09.60#ibcon#*before write, iclass 4, count 0 2006.238.08:16:09.60#ibcon#enter sib2, iclass 4, count 0 2006.238.08:16:09.60#ibcon#flushed, iclass 4, count 0 2006.238.08:16:09.60#ibcon#about to write, iclass 4, count 0 2006.238.08:16:09.60#ibcon#wrote, iclass 4, count 0 2006.238.08:16:09.60#ibcon#about to read 3, iclass 4, count 0 2006.238.08:16:09.63#ibcon#read 3, iclass 4, count 0 2006.238.08:16:09.63#ibcon#about to read 4, iclass 4, count 0 2006.238.08:16:09.63#ibcon#read 4, iclass 4, count 0 2006.238.08:16:09.63#ibcon#about to read 5, iclass 4, count 0 2006.238.08:16:09.63#ibcon#read 5, iclass 4, count 0 2006.238.08:16:09.63#ibcon#about to read 6, iclass 4, count 0 2006.238.08:16:09.63#ibcon#read 6, iclass 4, count 0 2006.238.08:16:09.63#ibcon#end of sib2, iclass 4, count 0 2006.238.08:16:09.63#ibcon#*after write, iclass 4, count 0 2006.238.08:16:09.63#ibcon#*before return 0, iclass 4, count 0 2006.238.08:16:09.63#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:16:09.63#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:16:09.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:16:09.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:16:09.63$vc4f8/valo=6,772.99 2006.238.08:16:09.63#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.238.08:16:09.63#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.238.08:16:09.63#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:09.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:16:09.63#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:16:09.63#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:16:09.63#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:16:09.63#ibcon#first serial, iclass 6, count 0 2006.238.08:16:09.63#ibcon#enter sib2, iclass 6, count 0 2006.238.08:16:09.63#ibcon#flushed, iclass 6, count 0 2006.238.08:16:09.63#ibcon#about to write, iclass 6, count 0 2006.238.08:16:09.63#ibcon#wrote, iclass 6, count 0 2006.238.08:16:09.63#ibcon#about to read 3, iclass 6, count 0 2006.238.08:16:09.65#ibcon#read 3, iclass 6, count 0 2006.238.08:16:09.65#ibcon#about to read 4, iclass 6, count 0 2006.238.08:16:09.65#ibcon#read 4, iclass 6, count 0 2006.238.08:16:09.65#ibcon#about to read 5, iclass 6, count 0 2006.238.08:16:09.65#ibcon#read 5, iclass 6, count 0 2006.238.08:16:09.65#ibcon#about to read 6, iclass 6, count 0 2006.238.08:16:09.65#ibcon#read 6, iclass 6, count 0 2006.238.08:16:09.65#ibcon#end of sib2, iclass 6, count 0 2006.238.08:16:09.65#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:16:09.65#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:16:09.65#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:16:09.65#ibcon#*before write, iclass 6, count 0 2006.238.08:16:09.65#ibcon#enter sib2, iclass 6, count 0 2006.238.08:16:09.65#ibcon#flushed, iclass 6, count 0 2006.238.08:16:09.65#ibcon#about to write, iclass 6, count 0 2006.238.08:16:09.65#ibcon#wrote, iclass 6, count 0 2006.238.08:16:09.65#ibcon#about to read 3, iclass 6, count 0 2006.238.08:16:09.69#ibcon#read 3, iclass 6, count 0 2006.238.08:16:09.69#ibcon#about to read 4, iclass 6, count 0 2006.238.08:16:09.69#ibcon#read 4, iclass 6, count 0 2006.238.08:16:09.69#ibcon#about to read 5, iclass 6, count 0 2006.238.08:16:09.69#ibcon#read 5, iclass 6, count 0 2006.238.08:16:09.69#ibcon#about to read 6, iclass 6, count 0 2006.238.08:16:09.69#ibcon#read 6, iclass 6, count 0 2006.238.08:16:09.69#ibcon#end of sib2, iclass 6, count 0 2006.238.08:16:09.69#ibcon#*after write, iclass 6, count 0 2006.238.08:16:09.69#ibcon#*before return 0, iclass 6, count 0 2006.238.08:16:09.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:16:09.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:16:09.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:16:09.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:16:09.69$vc4f8/va=6,7 2006.238.08:16:09.69#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.238.08:16:09.69#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.238.08:16:09.69#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:09.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:16:09.75#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:16:09.75#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:16:09.75#ibcon#enter wrdev, iclass 10, count 2 2006.238.08:16:09.75#ibcon#first serial, iclass 10, count 2 2006.238.08:16:09.75#ibcon#enter sib2, iclass 10, count 2 2006.238.08:16:09.75#ibcon#flushed, iclass 10, count 2 2006.238.08:16:09.75#ibcon#about to write, iclass 10, count 2 2006.238.08:16:09.75#ibcon#wrote, iclass 10, count 2 2006.238.08:16:09.75#ibcon#about to read 3, iclass 10, count 2 2006.238.08:16:09.77#ibcon#read 3, iclass 10, count 2 2006.238.08:16:09.77#ibcon#about to read 4, iclass 10, count 2 2006.238.08:16:09.77#ibcon#read 4, iclass 10, count 2 2006.238.08:16:09.77#ibcon#about to read 5, iclass 10, count 2 2006.238.08:16:09.77#ibcon#read 5, iclass 10, count 2 2006.238.08:16:09.77#ibcon#about to read 6, iclass 10, count 2 2006.238.08:16:09.77#ibcon#read 6, iclass 10, count 2 2006.238.08:16:09.77#ibcon#end of sib2, iclass 10, count 2 2006.238.08:16:09.77#ibcon#*mode == 0, iclass 10, count 2 2006.238.08:16:09.77#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.238.08:16:09.77#ibcon#[25=AT06-07\r\n] 2006.238.08:16:09.77#ibcon#*before write, iclass 10, count 2 2006.238.08:16:09.77#ibcon#enter sib2, iclass 10, count 2 2006.238.08:16:09.77#ibcon#flushed, iclass 10, count 2 2006.238.08:16:09.77#ibcon#about to write, iclass 10, count 2 2006.238.08:16:09.77#ibcon#wrote, iclass 10, count 2 2006.238.08:16:09.77#ibcon#about to read 3, iclass 10, count 2 2006.238.08:16:09.80#ibcon#read 3, iclass 10, count 2 2006.238.08:16:09.80#ibcon#about to read 4, iclass 10, count 2 2006.238.08:16:09.80#ibcon#read 4, iclass 10, count 2 2006.238.08:16:09.80#ibcon#about to read 5, iclass 10, count 2 2006.238.08:16:09.80#ibcon#read 5, iclass 10, count 2 2006.238.08:16:09.80#ibcon#about to read 6, iclass 10, count 2 2006.238.08:16:09.80#ibcon#read 6, iclass 10, count 2 2006.238.08:16:09.80#ibcon#end of sib2, iclass 10, count 2 2006.238.08:16:09.80#ibcon#*after write, iclass 10, count 2 2006.238.08:16:09.80#ibcon#*before return 0, iclass 10, count 2 2006.238.08:16:09.80#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:16:09.80#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.238.08:16:09.80#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.238.08:16:09.80#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:09.80#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:16:09.92#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:16:09.92#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:16:09.92#ibcon#enter wrdev, iclass 10, count 0 2006.238.08:16:09.92#ibcon#first serial, iclass 10, count 0 2006.238.08:16:09.92#ibcon#enter sib2, iclass 10, count 0 2006.238.08:16:09.92#ibcon#flushed, iclass 10, count 0 2006.238.08:16:09.92#ibcon#about to write, iclass 10, count 0 2006.238.08:16:09.92#ibcon#wrote, iclass 10, count 0 2006.238.08:16:09.92#ibcon#about to read 3, iclass 10, count 0 2006.238.08:16:09.94#ibcon#read 3, iclass 10, count 0 2006.238.08:16:09.94#ibcon#about to read 4, iclass 10, count 0 2006.238.08:16:09.94#ibcon#read 4, iclass 10, count 0 2006.238.08:16:09.94#ibcon#about to read 5, iclass 10, count 0 2006.238.08:16:09.94#ibcon#read 5, iclass 10, count 0 2006.238.08:16:09.94#ibcon#about to read 6, iclass 10, count 0 2006.238.08:16:09.94#ibcon#read 6, iclass 10, count 0 2006.238.08:16:09.94#ibcon#end of sib2, iclass 10, count 0 2006.238.08:16:09.94#ibcon#*mode == 0, iclass 10, count 0 2006.238.08:16:09.94#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.08:16:09.94#ibcon#[25=USB\r\n] 2006.238.08:16:09.94#ibcon#*before write, iclass 10, count 0 2006.238.08:16:09.94#ibcon#enter sib2, iclass 10, count 0 2006.238.08:16:09.94#ibcon#flushed, iclass 10, count 0 2006.238.08:16:09.94#ibcon#about to write, iclass 10, count 0 2006.238.08:16:09.94#ibcon#wrote, iclass 10, count 0 2006.238.08:16:09.94#ibcon#about to read 3, iclass 10, count 0 2006.238.08:16:09.97#ibcon#read 3, iclass 10, count 0 2006.238.08:16:09.97#ibcon#about to read 4, iclass 10, count 0 2006.238.08:16:09.97#ibcon#read 4, iclass 10, count 0 2006.238.08:16:09.97#ibcon#about to read 5, iclass 10, count 0 2006.238.08:16:09.97#ibcon#read 5, iclass 10, count 0 2006.238.08:16:09.97#ibcon#about to read 6, iclass 10, count 0 2006.238.08:16:09.97#ibcon#read 6, iclass 10, count 0 2006.238.08:16:09.97#ibcon#end of sib2, iclass 10, count 0 2006.238.08:16:09.97#ibcon#*after write, iclass 10, count 0 2006.238.08:16:09.97#ibcon#*before return 0, iclass 10, count 0 2006.238.08:16:09.97#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:16:09.97#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.238.08:16:09.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.08:16:09.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.08:16:09.97$vc4f8/valo=7,832.99 2006.238.08:16:09.97#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.238.08:16:09.97#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.238.08:16:09.97#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:09.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:16:09.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:16:09.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:16:09.97#ibcon#enter wrdev, iclass 12, count 0 2006.238.08:16:09.97#ibcon#first serial, iclass 12, count 0 2006.238.08:16:09.97#ibcon#enter sib2, iclass 12, count 0 2006.238.08:16:09.97#ibcon#flushed, iclass 12, count 0 2006.238.08:16:09.97#ibcon#about to write, iclass 12, count 0 2006.238.08:16:09.97#ibcon#wrote, iclass 12, count 0 2006.238.08:16:09.97#ibcon#about to read 3, iclass 12, count 0 2006.238.08:16:09.99#ibcon#read 3, iclass 12, count 0 2006.238.08:16:09.99#ibcon#about to read 4, iclass 12, count 0 2006.238.08:16:09.99#ibcon#read 4, iclass 12, count 0 2006.238.08:16:09.99#ibcon#about to read 5, iclass 12, count 0 2006.238.08:16:09.99#ibcon#read 5, iclass 12, count 0 2006.238.08:16:09.99#ibcon#about to read 6, iclass 12, count 0 2006.238.08:16:09.99#ibcon#read 6, iclass 12, count 0 2006.238.08:16:09.99#ibcon#end of sib2, iclass 12, count 0 2006.238.08:16:09.99#ibcon#*mode == 0, iclass 12, count 0 2006.238.08:16:09.99#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.08:16:09.99#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:16:09.99#ibcon#*before write, iclass 12, count 0 2006.238.08:16:09.99#ibcon#enter sib2, iclass 12, count 0 2006.238.08:16:09.99#ibcon#flushed, iclass 12, count 0 2006.238.08:16:09.99#ibcon#about to write, iclass 12, count 0 2006.238.08:16:09.99#ibcon#wrote, iclass 12, count 0 2006.238.08:16:09.99#ibcon#about to read 3, iclass 12, count 0 2006.238.08:16:10.03#ibcon#read 3, iclass 12, count 0 2006.238.08:16:10.03#ibcon#about to read 4, iclass 12, count 0 2006.238.08:16:10.03#ibcon#read 4, iclass 12, count 0 2006.238.08:16:10.03#ibcon#about to read 5, iclass 12, count 0 2006.238.08:16:10.03#ibcon#read 5, iclass 12, count 0 2006.238.08:16:10.03#ibcon#about to read 6, iclass 12, count 0 2006.238.08:16:10.03#ibcon#read 6, iclass 12, count 0 2006.238.08:16:10.03#ibcon#end of sib2, iclass 12, count 0 2006.238.08:16:10.03#ibcon#*after write, iclass 12, count 0 2006.238.08:16:10.03#ibcon#*before return 0, iclass 12, count 0 2006.238.08:16:10.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:16:10.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.238.08:16:10.03#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.08:16:10.03#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.08:16:10.03$vc4f8/va=7,7 2006.238.08:16:10.03#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.238.08:16:10.03#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.238.08:16:10.03#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:10.03#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:16:10.09#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:16:10.09#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:16:10.09#ibcon#enter wrdev, iclass 14, count 2 2006.238.08:16:10.09#ibcon#first serial, iclass 14, count 2 2006.238.08:16:10.09#ibcon#enter sib2, iclass 14, count 2 2006.238.08:16:10.09#ibcon#flushed, iclass 14, count 2 2006.238.08:16:10.09#ibcon#about to write, iclass 14, count 2 2006.238.08:16:10.09#ibcon#wrote, iclass 14, count 2 2006.238.08:16:10.09#ibcon#about to read 3, iclass 14, count 2 2006.238.08:16:10.11#ibcon#read 3, iclass 14, count 2 2006.238.08:16:10.11#ibcon#about to read 4, iclass 14, count 2 2006.238.08:16:10.11#ibcon#read 4, iclass 14, count 2 2006.238.08:16:10.11#ibcon#about to read 5, iclass 14, count 2 2006.238.08:16:10.11#ibcon#read 5, iclass 14, count 2 2006.238.08:16:10.11#ibcon#about to read 6, iclass 14, count 2 2006.238.08:16:10.11#ibcon#read 6, iclass 14, count 2 2006.238.08:16:10.11#ibcon#end of sib2, iclass 14, count 2 2006.238.08:16:10.11#ibcon#*mode == 0, iclass 14, count 2 2006.238.08:16:10.11#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.238.08:16:10.11#ibcon#[25=AT07-07\r\n] 2006.238.08:16:10.11#ibcon#*before write, iclass 14, count 2 2006.238.08:16:10.11#ibcon#enter sib2, iclass 14, count 2 2006.238.08:16:10.11#ibcon#flushed, iclass 14, count 2 2006.238.08:16:10.11#ibcon#about to write, iclass 14, count 2 2006.238.08:16:10.11#ibcon#wrote, iclass 14, count 2 2006.238.08:16:10.11#ibcon#about to read 3, iclass 14, count 2 2006.238.08:16:10.14#ibcon#read 3, iclass 14, count 2 2006.238.08:16:10.14#ibcon#about to read 4, iclass 14, count 2 2006.238.08:16:10.14#ibcon#read 4, iclass 14, count 2 2006.238.08:16:10.14#ibcon#about to read 5, iclass 14, count 2 2006.238.08:16:10.14#ibcon#read 5, iclass 14, count 2 2006.238.08:16:10.14#ibcon#about to read 6, iclass 14, count 2 2006.238.08:16:10.14#ibcon#read 6, iclass 14, count 2 2006.238.08:16:10.14#ibcon#end of sib2, iclass 14, count 2 2006.238.08:16:10.14#ibcon#*after write, iclass 14, count 2 2006.238.08:16:10.14#ibcon#*before return 0, iclass 14, count 2 2006.238.08:16:10.14#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:16:10.14#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.238.08:16:10.14#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.238.08:16:10.14#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:10.14#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:16:10.26#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:16:10.26#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:16:10.26#ibcon#enter wrdev, iclass 14, count 0 2006.238.08:16:10.26#ibcon#first serial, iclass 14, count 0 2006.238.08:16:10.26#ibcon#enter sib2, iclass 14, count 0 2006.238.08:16:10.26#ibcon#flushed, iclass 14, count 0 2006.238.08:16:10.26#ibcon#about to write, iclass 14, count 0 2006.238.08:16:10.26#ibcon#wrote, iclass 14, count 0 2006.238.08:16:10.26#ibcon#about to read 3, iclass 14, count 0 2006.238.08:16:10.28#ibcon#read 3, iclass 14, count 0 2006.238.08:16:10.28#ibcon#about to read 4, iclass 14, count 0 2006.238.08:16:10.28#ibcon#read 4, iclass 14, count 0 2006.238.08:16:10.28#ibcon#about to read 5, iclass 14, count 0 2006.238.08:16:10.28#ibcon#read 5, iclass 14, count 0 2006.238.08:16:10.28#ibcon#about to read 6, iclass 14, count 0 2006.238.08:16:10.28#ibcon#read 6, iclass 14, count 0 2006.238.08:16:10.28#ibcon#end of sib2, iclass 14, count 0 2006.238.08:16:10.28#ibcon#*mode == 0, iclass 14, count 0 2006.238.08:16:10.28#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.08:16:10.28#ibcon#[25=USB\r\n] 2006.238.08:16:10.28#ibcon#*before write, iclass 14, count 0 2006.238.08:16:10.28#ibcon#enter sib2, iclass 14, count 0 2006.238.08:16:10.28#ibcon#flushed, iclass 14, count 0 2006.238.08:16:10.28#ibcon#about to write, iclass 14, count 0 2006.238.08:16:10.28#ibcon#wrote, iclass 14, count 0 2006.238.08:16:10.28#ibcon#about to read 3, iclass 14, count 0 2006.238.08:16:10.31#ibcon#read 3, iclass 14, count 0 2006.238.08:16:10.31#ibcon#about to read 4, iclass 14, count 0 2006.238.08:16:10.31#ibcon#read 4, iclass 14, count 0 2006.238.08:16:10.31#ibcon#about to read 5, iclass 14, count 0 2006.238.08:16:10.31#ibcon#read 5, iclass 14, count 0 2006.238.08:16:10.31#ibcon#about to read 6, iclass 14, count 0 2006.238.08:16:10.31#ibcon#read 6, iclass 14, count 0 2006.238.08:16:10.31#ibcon#end of sib2, iclass 14, count 0 2006.238.08:16:10.31#ibcon#*after write, iclass 14, count 0 2006.238.08:16:10.31#ibcon#*before return 0, iclass 14, count 0 2006.238.08:16:10.31#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:16:10.31#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.238.08:16:10.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.08:16:10.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.08:16:10.31$vc4f8/valo=8,852.99 2006.238.08:16:10.31#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.238.08:16:10.31#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.238.08:16:10.31#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:10.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:16:10.31#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:16:10.31#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:16:10.31#ibcon#enter wrdev, iclass 16, count 0 2006.238.08:16:10.31#ibcon#first serial, iclass 16, count 0 2006.238.08:16:10.31#ibcon#enter sib2, iclass 16, count 0 2006.238.08:16:10.31#ibcon#flushed, iclass 16, count 0 2006.238.08:16:10.31#ibcon#about to write, iclass 16, count 0 2006.238.08:16:10.31#ibcon#wrote, iclass 16, count 0 2006.238.08:16:10.31#ibcon#about to read 3, iclass 16, count 0 2006.238.08:16:10.33#ibcon#read 3, iclass 16, count 0 2006.238.08:16:10.33#ibcon#about to read 4, iclass 16, count 0 2006.238.08:16:10.33#ibcon#read 4, iclass 16, count 0 2006.238.08:16:10.33#ibcon#about to read 5, iclass 16, count 0 2006.238.08:16:10.33#ibcon#read 5, iclass 16, count 0 2006.238.08:16:10.33#ibcon#about to read 6, iclass 16, count 0 2006.238.08:16:10.33#ibcon#read 6, iclass 16, count 0 2006.238.08:16:10.33#ibcon#end of sib2, iclass 16, count 0 2006.238.08:16:10.33#ibcon#*mode == 0, iclass 16, count 0 2006.238.08:16:10.33#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.08:16:10.33#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:16:10.33#ibcon#*before write, iclass 16, count 0 2006.238.08:16:10.33#ibcon#enter sib2, iclass 16, count 0 2006.238.08:16:10.33#ibcon#flushed, iclass 16, count 0 2006.238.08:16:10.33#ibcon#about to write, iclass 16, count 0 2006.238.08:16:10.33#ibcon#wrote, iclass 16, count 0 2006.238.08:16:10.33#ibcon#about to read 3, iclass 16, count 0 2006.238.08:16:10.37#ibcon#read 3, iclass 16, count 0 2006.238.08:16:10.37#ibcon#about to read 4, iclass 16, count 0 2006.238.08:16:10.37#ibcon#read 4, iclass 16, count 0 2006.238.08:16:10.37#ibcon#about to read 5, iclass 16, count 0 2006.238.08:16:10.37#ibcon#read 5, iclass 16, count 0 2006.238.08:16:10.37#ibcon#about to read 6, iclass 16, count 0 2006.238.08:16:10.37#ibcon#read 6, iclass 16, count 0 2006.238.08:16:10.37#ibcon#end of sib2, iclass 16, count 0 2006.238.08:16:10.37#ibcon#*after write, iclass 16, count 0 2006.238.08:16:10.37#ibcon#*before return 0, iclass 16, count 0 2006.238.08:16:10.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:16:10.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.238.08:16:10.37#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.08:16:10.37#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.08:16:10.37$vc4f8/va=8,7 2006.238.08:16:10.37#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.238.08:16:10.37#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.238.08:16:10.37#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:10.37#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:16:10.43#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:16:10.43#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:16:10.43#ibcon#enter wrdev, iclass 18, count 2 2006.238.08:16:10.43#ibcon#first serial, iclass 18, count 2 2006.238.08:16:10.43#ibcon#enter sib2, iclass 18, count 2 2006.238.08:16:10.43#ibcon#flushed, iclass 18, count 2 2006.238.08:16:10.43#ibcon#about to write, iclass 18, count 2 2006.238.08:16:10.43#ibcon#wrote, iclass 18, count 2 2006.238.08:16:10.43#ibcon#about to read 3, iclass 18, count 2 2006.238.08:16:10.45#ibcon#read 3, iclass 18, count 2 2006.238.08:16:10.45#ibcon#about to read 4, iclass 18, count 2 2006.238.08:16:10.45#ibcon#read 4, iclass 18, count 2 2006.238.08:16:10.45#ibcon#about to read 5, iclass 18, count 2 2006.238.08:16:10.45#ibcon#read 5, iclass 18, count 2 2006.238.08:16:10.45#ibcon#about to read 6, iclass 18, count 2 2006.238.08:16:10.45#ibcon#read 6, iclass 18, count 2 2006.238.08:16:10.45#ibcon#end of sib2, iclass 18, count 2 2006.238.08:16:10.45#ibcon#*mode == 0, iclass 18, count 2 2006.238.08:16:10.45#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.238.08:16:10.45#ibcon#[25=AT08-07\r\n] 2006.238.08:16:10.45#ibcon#*before write, iclass 18, count 2 2006.238.08:16:10.45#ibcon#enter sib2, iclass 18, count 2 2006.238.08:16:10.45#ibcon#flushed, iclass 18, count 2 2006.238.08:16:10.45#ibcon#about to write, iclass 18, count 2 2006.238.08:16:10.45#ibcon#wrote, iclass 18, count 2 2006.238.08:16:10.45#ibcon#about to read 3, iclass 18, count 2 2006.238.08:16:10.48#ibcon#read 3, iclass 18, count 2 2006.238.08:16:10.48#ibcon#about to read 4, iclass 18, count 2 2006.238.08:16:10.48#ibcon#read 4, iclass 18, count 2 2006.238.08:16:10.48#ibcon#about to read 5, iclass 18, count 2 2006.238.08:16:10.48#ibcon#read 5, iclass 18, count 2 2006.238.08:16:10.48#ibcon#about to read 6, iclass 18, count 2 2006.238.08:16:10.48#ibcon#read 6, iclass 18, count 2 2006.238.08:16:10.48#ibcon#end of sib2, iclass 18, count 2 2006.238.08:16:10.48#ibcon#*after write, iclass 18, count 2 2006.238.08:16:10.48#ibcon#*before return 0, iclass 18, count 2 2006.238.08:16:10.48#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:16:10.48#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.238.08:16:10.48#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.238.08:16:10.48#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:10.48#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:16:10.60#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:16:10.60#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:16:10.60#ibcon#enter wrdev, iclass 18, count 0 2006.238.08:16:10.60#ibcon#first serial, iclass 18, count 0 2006.238.08:16:10.60#ibcon#enter sib2, iclass 18, count 0 2006.238.08:16:10.60#ibcon#flushed, iclass 18, count 0 2006.238.08:16:10.60#ibcon#about to write, iclass 18, count 0 2006.238.08:16:10.60#ibcon#wrote, iclass 18, count 0 2006.238.08:16:10.60#ibcon#about to read 3, iclass 18, count 0 2006.238.08:16:10.62#ibcon#read 3, iclass 18, count 0 2006.238.08:16:10.62#ibcon#about to read 4, iclass 18, count 0 2006.238.08:16:10.62#ibcon#read 4, iclass 18, count 0 2006.238.08:16:10.62#ibcon#about to read 5, iclass 18, count 0 2006.238.08:16:10.62#ibcon#read 5, iclass 18, count 0 2006.238.08:16:10.62#ibcon#about to read 6, iclass 18, count 0 2006.238.08:16:10.62#ibcon#read 6, iclass 18, count 0 2006.238.08:16:10.62#ibcon#end of sib2, iclass 18, count 0 2006.238.08:16:10.62#ibcon#*mode == 0, iclass 18, count 0 2006.238.08:16:10.62#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.08:16:10.62#ibcon#[25=USB\r\n] 2006.238.08:16:10.62#ibcon#*before write, iclass 18, count 0 2006.238.08:16:10.62#ibcon#enter sib2, iclass 18, count 0 2006.238.08:16:10.62#ibcon#flushed, iclass 18, count 0 2006.238.08:16:10.62#ibcon#about to write, iclass 18, count 0 2006.238.08:16:10.62#ibcon#wrote, iclass 18, count 0 2006.238.08:16:10.62#ibcon#about to read 3, iclass 18, count 0 2006.238.08:16:10.65#ibcon#read 3, iclass 18, count 0 2006.238.08:16:10.65#ibcon#about to read 4, iclass 18, count 0 2006.238.08:16:10.65#ibcon#read 4, iclass 18, count 0 2006.238.08:16:10.65#ibcon#about to read 5, iclass 18, count 0 2006.238.08:16:10.65#ibcon#read 5, iclass 18, count 0 2006.238.08:16:10.65#ibcon#about to read 6, iclass 18, count 0 2006.238.08:16:10.65#ibcon#read 6, iclass 18, count 0 2006.238.08:16:10.65#ibcon#end of sib2, iclass 18, count 0 2006.238.08:16:10.65#ibcon#*after write, iclass 18, count 0 2006.238.08:16:10.65#ibcon#*before return 0, iclass 18, count 0 2006.238.08:16:10.65#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:16:10.65#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.238.08:16:10.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.08:16:10.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.08:16:10.65$vc4f8/vblo=1,632.99 2006.238.08:16:10.65#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.238.08:16:10.65#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.238.08:16:10.65#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:10.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:16:10.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:16:10.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:16:10.65#ibcon#enter wrdev, iclass 20, count 0 2006.238.08:16:10.65#ibcon#first serial, iclass 20, count 0 2006.238.08:16:10.65#ibcon#enter sib2, iclass 20, count 0 2006.238.08:16:10.65#ibcon#flushed, iclass 20, count 0 2006.238.08:16:10.65#ibcon#about to write, iclass 20, count 0 2006.238.08:16:10.65#ibcon#wrote, iclass 20, count 0 2006.238.08:16:10.65#ibcon#about to read 3, iclass 20, count 0 2006.238.08:16:10.67#ibcon#read 3, iclass 20, count 0 2006.238.08:16:10.67#ibcon#about to read 4, iclass 20, count 0 2006.238.08:16:10.67#ibcon#read 4, iclass 20, count 0 2006.238.08:16:10.67#ibcon#about to read 5, iclass 20, count 0 2006.238.08:16:10.67#ibcon#read 5, iclass 20, count 0 2006.238.08:16:10.67#ibcon#about to read 6, iclass 20, count 0 2006.238.08:16:10.67#ibcon#read 6, iclass 20, count 0 2006.238.08:16:10.67#ibcon#end of sib2, iclass 20, count 0 2006.238.08:16:10.67#ibcon#*mode == 0, iclass 20, count 0 2006.238.08:16:10.67#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.08:16:10.67#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:16:10.67#ibcon#*before write, iclass 20, count 0 2006.238.08:16:10.67#ibcon#enter sib2, iclass 20, count 0 2006.238.08:16:10.67#ibcon#flushed, iclass 20, count 0 2006.238.08:16:10.67#ibcon#about to write, iclass 20, count 0 2006.238.08:16:10.67#ibcon#wrote, iclass 20, count 0 2006.238.08:16:10.67#ibcon#about to read 3, iclass 20, count 0 2006.238.08:16:10.71#ibcon#read 3, iclass 20, count 0 2006.238.08:16:10.71#ibcon#about to read 4, iclass 20, count 0 2006.238.08:16:10.71#ibcon#read 4, iclass 20, count 0 2006.238.08:16:10.71#ibcon#about to read 5, iclass 20, count 0 2006.238.08:16:10.71#ibcon#read 5, iclass 20, count 0 2006.238.08:16:10.71#ibcon#about to read 6, iclass 20, count 0 2006.238.08:16:10.71#ibcon#read 6, iclass 20, count 0 2006.238.08:16:10.71#ibcon#end of sib2, iclass 20, count 0 2006.238.08:16:10.71#ibcon#*after write, iclass 20, count 0 2006.238.08:16:10.71#ibcon#*before return 0, iclass 20, count 0 2006.238.08:16:10.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:16:10.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.238.08:16:10.71#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.08:16:10.71#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.08:16:10.71$vc4f8/vb=1,4 2006.238.08:16:10.71#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.238.08:16:10.71#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.238.08:16:10.71#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:10.71#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:16:10.71#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:16:10.71#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:16:10.71#ibcon#enter wrdev, iclass 22, count 2 2006.238.08:16:10.71#ibcon#first serial, iclass 22, count 2 2006.238.08:16:10.71#ibcon#enter sib2, iclass 22, count 2 2006.238.08:16:10.71#ibcon#flushed, iclass 22, count 2 2006.238.08:16:10.71#ibcon#about to write, iclass 22, count 2 2006.238.08:16:10.71#ibcon#wrote, iclass 22, count 2 2006.238.08:16:10.71#ibcon#about to read 3, iclass 22, count 2 2006.238.08:16:10.73#ibcon#read 3, iclass 22, count 2 2006.238.08:16:10.73#ibcon#about to read 4, iclass 22, count 2 2006.238.08:16:10.73#ibcon#read 4, iclass 22, count 2 2006.238.08:16:10.73#ibcon#about to read 5, iclass 22, count 2 2006.238.08:16:10.73#ibcon#read 5, iclass 22, count 2 2006.238.08:16:10.73#ibcon#about to read 6, iclass 22, count 2 2006.238.08:16:10.73#ibcon#read 6, iclass 22, count 2 2006.238.08:16:10.73#ibcon#end of sib2, iclass 22, count 2 2006.238.08:16:10.73#ibcon#*mode == 0, iclass 22, count 2 2006.238.08:16:10.73#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.238.08:16:10.73#ibcon#[27=AT01-04\r\n] 2006.238.08:16:10.73#ibcon#*before write, iclass 22, count 2 2006.238.08:16:10.73#ibcon#enter sib2, iclass 22, count 2 2006.238.08:16:10.73#ibcon#flushed, iclass 22, count 2 2006.238.08:16:10.73#ibcon#about to write, iclass 22, count 2 2006.238.08:16:10.73#ibcon#wrote, iclass 22, count 2 2006.238.08:16:10.73#ibcon#about to read 3, iclass 22, count 2 2006.238.08:16:10.76#ibcon#read 3, iclass 22, count 2 2006.238.08:16:10.76#ibcon#about to read 4, iclass 22, count 2 2006.238.08:16:10.76#ibcon#read 4, iclass 22, count 2 2006.238.08:16:10.76#ibcon#about to read 5, iclass 22, count 2 2006.238.08:16:10.76#ibcon#read 5, iclass 22, count 2 2006.238.08:16:10.76#ibcon#about to read 6, iclass 22, count 2 2006.238.08:16:10.76#ibcon#read 6, iclass 22, count 2 2006.238.08:16:10.76#ibcon#end of sib2, iclass 22, count 2 2006.238.08:16:10.76#ibcon#*after write, iclass 22, count 2 2006.238.08:16:10.76#ibcon#*before return 0, iclass 22, count 2 2006.238.08:16:10.76#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:16:10.76#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.238.08:16:10.76#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.238.08:16:10.76#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:10.76#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:16:10.88#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:16:10.88#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:16:10.88#ibcon#enter wrdev, iclass 22, count 0 2006.238.08:16:10.88#ibcon#first serial, iclass 22, count 0 2006.238.08:16:10.88#ibcon#enter sib2, iclass 22, count 0 2006.238.08:16:10.88#ibcon#flushed, iclass 22, count 0 2006.238.08:16:10.88#ibcon#about to write, iclass 22, count 0 2006.238.08:16:10.88#ibcon#wrote, iclass 22, count 0 2006.238.08:16:10.88#ibcon#about to read 3, iclass 22, count 0 2006.238.08:16:10.90#ibcon#read 3, iclass 22, count 0 2006.238.08:16:10.90#ibcon#about to read 4, iclass 22, count 0 2006.238.08:16:10.90#ibcon#read 4, iclass 22, count 0 2006.238.08:16:10.90#ibcon#about to read 5, iclass 22, count 0 2006.238.08:16:10.90#ibcon#read 5, iclass 22, count 0 2006.238.08:16:10.90#ibcon#about to read 6, iclass 22, count 0 2006.238.08:16:10.90#ibcon#read 6, iclass 22, count 0 2006.238.08:16:10.90#ibcon#end of sib2, iclass 22, count 0 2006.238.08:16:10.90#ibcon#*mode == 0, iclass 22, count 0 2006.238.08:16:10.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.08:16:10.90#ibcon#[27=USB\r\n] 2006.238.08:16:10.90#ibcon#*before write, iclass 22, count 0 2006.238.08:16:10.90#ibcon#enter sib2, iclass 22, count 0 2006.238.08:16:10.90#ibcon#flushed, iclass 22, count 0 2006.238.08:16:10.90#ibcon#about to write, iclass 22, count 0 2006.238.08:16:10.90#ibcon#wrote, iclass 22, count 0 2006.238.08:16:10.90#ibcon#about to read 3, iclass 22, count 0 2006.238.08:16:10.93#ibcon#read 3, iclass 22, count 0 2006.238.08:16:10.93#ibcon#about to read 4, iclass 22, count 0 2006.238.08:16:10.93#ibcon#read 4, iclass 22, count 0 2006.238.08:16:10.93#ibcon#about to read 5, iclass 22, count 0 2006.238.08:16:10.93#ibcon#read 5, iclass 22, count 0 2006.238.08:16:10.93#ibcon#about to read 6, iclass 22, count 0 2006.238.08:16:10.93#ibcon#read 6, iclass 22, count 0 2006.238.08:16:10.93#ibcon#end of sib2, iclass 22, count 0 2006.238.08:16:10.93#ibcon#*after write, iclass 22, count 0 2006.238.08:16:10.93#ibcon#*before return 0, iclass 22, count 0 2006.238.08:16:10.93#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:16:10.93#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.238.08:16:10.93#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.08:16:10.93#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.08:16:10.93$vc4f8/vblo=2,640.99 2006.238.08:16:10.93#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.238.08:16:10.93#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.238.08:16:10.93#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:10.93#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:16:10.93#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:16:10.93#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:16:10.93#ibcon#enter wrdev, iclass 24, count 0 2006.238.08:16:10.93#ibcon#first serial, iclass 24, count 0 2006.238.08:16:10.93#ibcon#enter sib2, iclass 24, count 0 2006.238.08:16:10.93#ibcon#flushed, iclass 24, count 0 2006.238.08:16:10.93#ibcon#about to write, iclass 24, count 0 2006.238.08:16:10.93#ibcon#wrote, iclass 24, count 0 2006.238.08:16:10.93#ibcon#about to read 3, iclass 24, count 0 2006.238.08:16:10.95#ibcon#read 3, iclass 24, count 0 2006.238.08:16:10.95#ibcon#about to read 4, iclass 24, count 0 2006.238.08:16:10.95#ibcon#read 4, iclass 24, count 0 2006.238.08:16:10.95#ibcon#about to read 5, iclass 24, count 0 2006.238.08:16:10.95#ibcon#read 5, iclass 24, count 0 2006.238.08:16:10.95#ibcon#about to read 6, iclass 24, count 0 2006.238.08:16:10.95#ibcon#read 6, iclass 24, count 0 2006.238.08:16:10.95#ibcon#end of sib2, iclass 24, count 0 2006.238.08:16:10.95#ibcon#*mode == 0, iclass 24, count 0 2006.238.08:16:10.95#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.08:16:10.95#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:16:10.95#ibcon#*before write, iclass 24, count 0 2006.238.08:16:10.95#ibcon#enter sib2, iclass 24, count 0 2006.238.08:16:10.95#ibcon#flushed, iclass 24, count 0 2006.238.08:16:10.95#ibcon#about to write, iclass 24, count 0 2006.238.08:16:10.95#ibcon#wrote, iclass 24, count 0 2006.238.08:16:10.95#ibcon#about to read 3, iclass 24, count 0 2006.238.08:16:10.99#ibcon#read 3, iclass 24, count 0 2006.238.08:16:10.99#ibcon#about to read 4, iclass 24, count 0 2006.238.08:16:10.99#ibcon#read 4, iclass 24, count 0 2006.238.08:16:10.99#ibcon#about to read 5, iclass 24, count 0 2006.238.08:16:10.99#ibcon#read 5, iclass 24, count 0 2006.238.08:16:10.99#ibcon#about to read 6, iclass 24, count 0 2006.238.08:16:10.99#ibcon#read 6, iclass 24, count 0 2006.238.08:16:10.99#ibcon#end of sib2, iclass 24, count 0 2006.238.08:16:10.99#ibcon#*after write, iclass 24, count 0 2006.238.08:16:10.99#ibcon#*before return 0, iclass 24, count 0 2006.238.08:16:10.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:16:10.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.238.08:16:10.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.08:16:10.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.08:16:10.99$vc4f8/vb=2,4 2006.238.08:16:10.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.238.08:16:10.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.238.08:16:10.99#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:10.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:16:11.05#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:16:11.05#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:16:11.05#ibcon#enter wrdev, iclass 26, count 2 2006.238.08:16:11.05#ibcon#first serial, iclass 26, count 2 2006.238.08:16:11.05#ibcon#enter sib2, iclass 26, count 2 2006.238.08:16:11.05#ibcon#flushed, iclass 26, count 2 2006.238.08:16:11.05#ibcon#about to write, iclass 26, count 2 2006.238.08:16:11.05#ibcon#wrote, iclass 26, count 2 2006.238.08:16:11.05#ibcon#about to read 3, iclass 26, count 2 2006.238.08:16:11.07#ibcon#read 3, iclass 26, count 2 2006.238.08:16:11.07#ibcon#about to read 4, iclass 26, count 2 2006.238.08:16:11.07#ibcon#read 4, iclass 26, count 2 2006.238.08:16:11.07#ibcon#about to read 5, iclass 26, count 2 2006.238.08:16:11.07#ibcon#read 5, iclass 26, count 2 2006.238.08:16:11.07#ibcon#about to read 6, iclass 26, count 2 2006.238.08:16:11.07#ibcon#read 6, iclass 26, count 2 2006.238.08:16:11.07#ibcon#end of sib2, iclass 26, count 2 2006.238.08:16:11.07#ibcon#*mode == 0, iclass 26, count 2 2006.238.08:16:11.07#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.238.08:16:11.07#ibcon#[27=AT02-04\r\n] 2006.238.08:16:11.07#ibcon#*before write, iclass 26, count 2 2006.238.08:16:11.07#ibcon#enter sib2, iclass 26, count 2 2006.238.08:16:11.07#ibcon#flushed, iclass 26, count 2 2006.238.08:16:11.07#ibcon#about to write, iclass 26, count 2 2006.238.08:16:11.07#ibcon#wrote, iclass 26, count 2 2006.238.08:16:11.07#ibcon#about to read 3, iclass 26, count 2 2006.238.08:16:11.10#ibcon#read 3, iclass 26, count 2 2006.238.08:16:11.10#ibcon#about to read 4, iclass 26, count 2 2006.238.08:16:11.10#ibcon#read 4, iclass 26, count 2 2006.238.08:16:11.10#ibcon#about to read 5, iclass 26, count 2 2006.238.08:16:11.10#ibcon#read 5, iclass 26, count 2 2006.238.08:16:11.10#ibcon#about to read 6, iclass 26, count 2 2006.238.08:16:11.10#ibcon#read 6, iclass 26, count 2 2006.238.08:16:11.10#ibcon#end of sib2, iclass 26, count 2 2006.238.08:16:11.10#ibcon#*after write, iclass 26, count 2 2006.238.08:16:11.10#ibcon#*before return 0, iclass 26, count 2 2006.238.08:16:11.10#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:16:11.10#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.238.08:16:11.10#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.238.08:16:11.10#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:11.10#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:16:11.22#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:16:11.22#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:16:11.22#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:16:11.22#ibcon#first serial, iclass 26, count 0 2006.238.08:16:11.22#ibcon#enter sib2, iclass 26, count 0 2006.238.08:16:11.22#ibcon#flushed, iclass 26, count 0 2006.238.08:16:11.22#ibcon#about to write, iclass 26, count 0 2006.238.08:16:11.22#ibcon#wrote, iclass 26, count 0 2006.238.08:16:11.22#ibcon#about to read 3, iclass 26, count 0 2006.238.08:16:11.24#ibcon#read 3, iclass 26, count 0 2006.238.08:16:11.24#ibcon#about to read 4, iclass 26, count 0 2006.238.08:16:11.24#ibcon#read 4, iclass 26, count 0 2006.238.08:16:11.24#ibcon#about to read 5, iclass 26, count 0 2006.238.08:16:11.24#ibcon#read 5, iclass 26, count 0 2006.238.08:16:11.24#ibcon#about to read 6, iclass 26, count 0 2006.238.08:16:11.24#ibcon#read 6, iclass 26, count 0 2006.238.08:16:11.24#ibcon#end of sib2, iclass 26, count 0 2006.238.08:16:11.24#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:16:11.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:16:11.24#ibcon#[27=USB\r\n] 2006.238.08:16:11.24#ibcon#*before write, iclass 26, count 0 2006.238.08:16:11.24#ibcon#enter sib2, iclass 26, count 0 2006.238.08:16:11.24#ibcon#flushed, iclass 26, count 0 2006.238.08:16:11.24#ibcon#about to write, iclass 26, count 0 2006.238.08:16:11.24#ibcon#wrote, iclass 26, count 0 2006.238.08:16:11.24#ibcon#about to read 3, iclass 26, count 0 2006.238.08:16:11.27#ibcon#read 3, iclass 26, count 0 2006.238.08:16:11.27#ibcon#about to read 4, iclass 26, count 0 2006.238.08:16:11.27#ibcon#read 4, iclass 26, count 0 2006.238.08:16:11.27#ibcon#about to read 5, iclass 26, count 0 2006.238.08:16:11.27#ibcon#read 5, iclass 26, count 0 2006.238.08:16:11.27#ibcon#about to read 6, iclass 26, count 0 2006.238.08:16:11.27#ibcon#read 6, iclass 26, count 0 2006.238.08:16:11.27#ibcon#end of sib2, iclass 26, count 0 2006.238.08:16:11.27#ibcon#*after write, iclass 26, count 0 2006.238.08:16:11.27#ibcon#*before return 0, iclass 26, count 0 2006.238.08:16:11.27#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:16:11.27#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.238.08:16:11.27#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:16:11.27#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:16:11.27$vc4f8/vblo=3,656.99 2006.238.08:16:11.27#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.238.08:16:11.27#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.238.08:16:11.27#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:11.27#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:16:11.27#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:16:11.27#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:16:11.27#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:16:11.27#ibcon#first serial, iclass 28, count 0 2006.238.08:16:11.27#ibcon#enter sib2, iclass 28, count 0 2006.238.08:16:11.27#ibcon#flushed, iclass 28, count 0 2006.238.08:16:11.27#ibcon#about to write, iclass 28, count 0 2006.238.08:16:11.27#ibcon#wrote, iclass 28, count 0 2006.238.08:16:11.27#ibcon#about to read 3, iclass 28, count 0 2006.238.08:16:11.29#ibcon#read 3, iclass 28, count 0 2006.238.08:16:11.29#ibcon#about to read 4, iclass 28, count 0 2006.238.08:16:11.29#ibcon#read 4, iclass 28, count 0 2006.238.08:16:11.29#ibcon#about to read 5, iclass 28, count 0 2006.238.08:16:11.29#ibcon#read 5, iclass 28, count 0 2006.238.08:16:11.29#ibcon#about to read 6, iclass 28, count 0 2006.238.08:16:11.29#ibcon#read 6, iclass 28, count 0 2006.238.08:16:11.29#ibcon#end of sib2, iclass 28, count 0 2006.238.08:16:11.29#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:16:11.29#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:16:11.29#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:16:11.29#ibcon#*before write, iclass 28, count 0 2006.238.08:16:11.29#ibcon#enter sib2, iclass 28, count 0 2006.238.08:16:11.29#ibcon#flushed, iclass 28, count 0 2006.238.08:16:11.29#ibcon#about to write, iclass 28, count 0 2006.238.08:16:11.29#ibcon#wrote, iclass 28, count 0 2006.238.08:16:11.29#ibcon#about to read 3, iclass 28, count 0 2006.238.08:16:11.33#ibcon#read 3, iclass 28, count 0 2006.238.08:16:11.33#ibcon#about to read 4, iclass 28, count 0 2006.238.08:16:11.33#ibcon#read 4, iclass 28, count 0 2006.238.08:16:11.33#ibcon#about to read 5, iclass 28, count 0 2006.238.08:16:11.33#ibcon#read 5, iclass 28, count 0 2006.238.08:16:11.33#ibcon#about to read 6, iclass 28, count 0 2006.238.08:16:11.33#ibcon#read 6, iclass 28, count 0 2006.238.08:16:11.33#ibcon#end of sib2, iclass 28, count 0 2006.238.08:16:11.33#ibcon#*after write, iclass 28, count 0 2006.238.08:16:11.33#ibcon#*before return 0, iclass 28, count 0 2006.238.08:16:11.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:16:11.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.238.08:16:11.33#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:16:11.33#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:16:11.33$vc4f8/vb=3,4 2006.238.08:16:11.33#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.238.08:16:11.33#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.238.08:16:11.33#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:11.33#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:16:11.39#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:16:11.39#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:16:11.39#ibcon#enter wrdev, iclass 30, count 2 2006.238.08:16:11.39#ibcon#first serial, iclass 30, count 2 2006.238.08:16:11.39#ibcon#enter sib2, iclass 30, count 2 2006.238.08:16:11.39#ibcon#flushed, iclass 30, count 2 2006.238.08:16:11.39#ibcon#about to write, iclass 30, count 2 2006.238.08:16:11.39#ibcon#wrote, iclass 30, count 2 2006.238.08:16:11.39#ibcon#about to read 3, iclass 30, count 2 2006.238.08:16:11.41#ibcon#read 3, iclass 30, count 2 2006.238.08:16:11.41#ibcon#about to read 4, iclass 30, count 2 2006.238.08:16:11.41#ibcon#read 4, iclass 30, count 2 2006.238.08:16:11.41#ibcon#about to read 5, iclass 30, count 2 2006.238.08:16:11.41#ibcon#read 5, iclass 30, count 2 2006.238.08:16:11.41#ibcon#about to read 6, iclass 30, count 2 2006.238.08:16:11.41#ibcon#read 6, iclass 30, count 2 2006.238.08:16:11.41#ibcon#end of sib2, iclass 30, count 2 2006.238.08:16:11.41#ibcon#*mode == 0, iclass 30, count 2 2006.238.08:16:11.41#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.238.08:16:11.41#ibcon#[27=AT03-04\r\n] 2006.238.08:16:11.41#ibcon#*before write, iclass 30, count 2 2006.238.08:16:11.41#ibcon#enter sib2, iclass 30, count 2 2006.238.08:16:11.41#ibcon#flushed, iclass 30, count 2 2006.238.08:16:11.41#ibcon#about to write, iclass 30, count 2 2006.238.08:16:11.41#ibcon#wrote, iclass 30, count 2 2006.238.08:16:11.41#ibcon#about to read 3, iclass 30, count 2 2006.238.08:16:11.44#ibcon#read 3, iclass 30, count 2 2006.238.08:16:11.44#ibcon#about to read 4, iclass 30, count 2 2006.238.08:16:11.44#ibcon#read 4, iclass 30, count 2 2006.238.08:16:11.44#ibcon#about to read 5, iclass 30, count 2 2006.238.08:16:11.44#ibcon#read 5, iclass 30, count 2 2006.238.08:16:11.44#ibcon#about to read 6, iclass 30, count 2 2006.238.08:16:11.44#ibcon#read 6, iclass 30, count 2 2006.238.08:16:11.44#ibcon#end of sib2, iclass 30, count 2 2006.238.08:16:11.44#ibcon#*after write, iclass 30, count 2 2006.238.08:16:11.44#ibcon#*before return 0, iclass 30, count 2 2006.238.08:16:11.44#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:16:11.44#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.238.08:16:11.44#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.238.08:16:11.44#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:11.44#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:16:11.56#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:16:11.56#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:16:11.56#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:16:11.56#ibcon#first serial, iclass 30, count 0 2006.238.08:16:11.56#ibcon#enter sib2, iclass 30, count 0 2006.238.08:16:11.56#ibcon#flushed, iclass 30, count 0 2006.238.08:16:11.56#ibcon#about to write, iclass 30, count 0 2006.238.08:16:11.56#ibcon#wrote, iclass 30, count 0 2006.238.08:16:11.56#ibcon#about to read 3, iclass 30, count 0 2006.238.08:16:11.58#ibcon#read 3, iclass 30, count 0 2006.238.08:16:11.58#ibcon#about to read 4, iclass 30, count 0 2006.238.08:16:11.58#ibcon#read 4, iclass 30, count 0 2006.238.08:16:11.58#ibcon#about to read 5, iclass 30, count 0 2006.238.08:16:11.58#ibcon#read 5, iclass 30, count 0 2006.238.08:16:11.58#ibcon#about to read 6, iclass 30, count 0 2006.238.08:16:11.58#ibcon#read 6, iclass 30, count 0 2006.238.08:16:11.58#ibcon#end of sib2, iclass 30, count 0 2006.238.08:16:11.58#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:16:11.58#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:16:11.58#ibcon#[27=USB\r\n] 2006.238.08:16:11.58#ibcon#*before write, iclass 30, count 0 2006.238.08:16:11.58#ibcon#enter sib2, iclass 30, count 0 2006.238.08:16:11.58#ibcon#flushed, iclass 30, count 0 2006.238.08:16:11.58#ibcon#about to write, iclass 30, count 0 2006.238.08:16:11.58#ibcon#wrote, iclass 30, count 0 2006.238.08:16:11.58#ibcon#about to read 3, iclass 30, count 0 2006.238.08:16:11.61#ibcon#read 3, iclass 30, count 0 2006.238.08:16:11.61#ibcon#about to read 4, iclass 30, count 0 2006.238.08:16:11.61#ibcon#read 4, iclass 30, count 0 2006.238.08:16:11.61#ibcon#about to read 5, iclass 30, count 0 2006.238.08:16:11.61#ibcon#read 5, iclass 30, count 0 2006.238.08:16:11.61#ibcon#about to read 6, iclass 30, count 0 2006.238.08:16:11.61#ibcon#read 6, iclass 30, count 0 2006.238.08:16:11.61#ibcon#end of sib2, iclass 30, count 0 2006.238.08:16:11.61#ibcon#*after write, iclass 30, count 0 2006.238.08:16:11.61#ibcon#*before return 0, iclass 30, count 0 2006.238.08:16:11.61#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:16:11.61#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.238.08:16:11.61#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:16:11.61#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:16:11.61$vc4f8/vblo=4,712.99 2006.238.08:16:11.61#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.08:16:11.61#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.08:16:11.61#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:11.61#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:16:11.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:16:11.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:16:11.61#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:16:11.61#ibcon#first serial, iclass 32, count 0 2006.238.08:16:11.61#ibcon#enter sib2, iclass 32, count 0 2006.238.08:16:11.61#ibcon#flushed, iclass 32, count 0 2006.238.08:16:11.61#ibcon#about to write, iclass 32, count 0 2006.238.08:16:11.61#ibcon#wrote, iclass 32, count 0 2006.238.08:16:11.61#ibcon#about to read 3, iclass 32, count 0 2006.238.08:16:11.63#ibcon#read 3, iclass 32, count 0 2006.238.08:16:11.63#ibcon#about to read 4, iclass 32, count 0 2006.238.08:16:11.63#ibcon#read 4, iclass 32, count 0 2006.238.08:16:11.63#ibcon#about to read 5, iclass 32, count 0 2006.238.08:16:11.63#ibcon#read 5, iclass 32, count 0 2006.238.08:16:11.63#ibcon#about to read 6, iclass 32, count 0 2006.238.08:16:11.63#ibcon#read 6, iclass 32, count 0 2006.238.08:16:11.63#ibcon#end of sib2, iclass 32, count 0 2006.238.08:16:11.63#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:16:11.63#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:16:11.63#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:16:11.63#ibcon#*before write, iclass 32, count 0 2006.238.08:16:11.63#ibcon#enter sib2, iclass 32, count 0 2006.238.08:16:11.63#ibcon#flushed, iclass 32, count 0 2006.238.08:16:11.63#ibcon#about to write, iclass 32, count 0 2006.238.08:16:11.63#ibcon#wrote, iclass 32, count 0 2006.238.08:16:11.63#ibcon#about to read 3, iclass 32, count 0 2006.238.08:16:11.67#ibcon#read 3, iclass 32, count 0 2006.238.08:16:11.67#ibcon#about to read 4, iclass 32, count 0 2006.238.08:16:11.67#ibcon#read 4, iclass 32, count 0 2006.238.08:16:11.67#ibcon#about to read 5, iclass 32, count 0 2006.238.08:16:11.67#ibcon#read 5, iclass 32, count 0 2006.238.08:16:11.67#ibcon#about to read 6, iclass 32, count 0 2006.238.08:16:11.67#ibcon#read 6, iclass 32, count 0 2006.238.08:16:11.67#ibcon#end of sib2, iclass 32, count 0 2006.238.08:16:11.67#ibcon#*after write, iclass 32, count 0 2006.238.08:16:11.67#ibcon#*before return 0, iclass 32, count 0 2006.238.08:16:11.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:16:11.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:16:11.67#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:16:11.67#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:16:11.67$vc4f8/vb=4,4 2006.238.08:16:11.67#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.238.08:16:11.67#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.238.08:16:11.67#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:11.67#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:16:11.73#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:16:11.73#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:16:11.73#ibcon#enter wrdev, iclass 34, count 2 2006.238.08:16:11.73#ibcon#first serial, iclass 34, count 2 2006.238.08:16:11.73#ibcon#enter sib2, iclass 34, count 2 2006.238.08:16:11.73#ibcon#flushed, iclass 34, count 2 2006.238.08:16:11.73#ibcon#about to write, iclass 34, count 2 2006.238.08:16:11.73#ibcon#wrote, iclass 34, count 2 2006.238.08:16:11.73#ibcon#about to read 3, iclass 34, count 2 2006.238.08:16:11.75#ibcon#read 3, iclass 34, count 2 2006.238.08:16:11.75#ibcon#about to read 4, iclass 34, count 2 2006.238.08:16:11.75#ibcon#read 4, iclass 34, count 2 2006.238.08:16:11.75#ibcon#about to read 5, iclass 34, count 2 2006.238.08:16:11.75#ibcon#read 5, iclass 34, count 2 2006.238.08:16:11.75#ibcon#about to read 6, iclass 34, count 2 2006.238.08:16:11.75#ibcon#read 6, iclass 34, count 2 2006.238.08:16:11.75#ibcon#end of sib2, iclass 34, count 2 2006.238.08:16:11.75#ibcon#*mode == 0, iclass 34, count 2 2006.238.08:16:11.75#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.238.08:16:11.75#ibcon#[27=AT04-04\r\n] 2006.238.08:16:11.75#ibcon#*before write, iclass 34, count 2 2006.238.08:16:11.75#ibcon#enter sib2, iclass 34, count 2 2006.238.08:16:11.75#ibcon#flushed, iclass 34, count 2 2006.238.08:16:11.75#ibcon#about to write, iclass 34, count 2 2006.238.08:16:11.75#ibcon#wrote, iclass 34, count 2 2006.238.08:16:11.75#ibcon#about to read 3, iclass 34, count 2 2006.238.08:16:11.78#ibcon#read 3, iclass 34, count 2 2006.238.08:16:11.78#ibcon#about to read 4, iclass 34, count 2 2006.238.08:16:11.78#ibcon#read 4, iclass 34, count 2 2006.238.08:16:11.78#ibcon#about to read 5, iclass 34, count 2 2006.238.08:16:11.78#ibcon#read 5, iclass 34, count 2 2006.238.08:16:11.78#ibcon#about to read 6, iclass 34, count 2 2006.238.08:16:11.78#ibcon#read 6, iclass 34, count 2 2006.238.08:16:11.78#ibcon#end of sib2, iclass 34, count 2 2006.238.08:16:11.78#ibcon#*after write, iclass 34, count 2 2006.238.08:16:11.78#ibcon#*before return 0, iclass 34, count 2 2006.238.08:16:11.78#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:16:11.78#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.238.08:16:11.78#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.238.08:16:11.78#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:11.78#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:16:11.90#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:16:11.90#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:16:11.90#ibcon#enter wrdev, iclass 34, count 0 2006.238.08:16:11.90#ibcon#first serial, iclass 34, count 0 2006.238.08:16:11.90#ibcon#enter sib2, iclass 34, count 0 2006.238.08:16:11.90#ibcon#flushed, iclass 34, count 0 2006.238.08:16:11.90#ibcon#about to write, iclass 34, count 0 2006.238.08:16:11.90#ibcon#wrote, iclass 34, count 0 2006.238.08:16:11.90#ibcon#about to read 3, iclass 34, count 0 2006.238.08:16:11.92#ibcon#read 3, iclass 34, count 0 2006.238.08:16:11.92#ibcon#about to read 4, iclass 34, count 0 2006.238.08:16:11.92#ibcon#read 4, iclass 34, count 0 2006.238.08:16:11.92#ibcon#about to read 5, iclass 34, count 0 2006.238.08:16:11.92#ibcon#read 5, iclass 34, count 0 2006.238.08:16:11.92#ibcon#about to read 6, iclass 34, count 0 2006.238.08:16:11.92#ibcon#read 6, iclass 34, count 0 2006.238.08:16:11.92#ibcon#end of sib2, iclass 34, count 0 2006.238.08:16:11.92#ibcon#*mode == 0, iclass 34, count 0 2006.238.08:16:11.92#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.08:16:11.92#ibcon#[27=USB\r\n] 2006.238.08:16:11.92#ibcon#*before write, iclass 34, count 0 2006.238.08:16:11.92#ibcon#enter sib2, iclass 34, count 0 2006.238.08:16:11.92#ibcon#flushed, iclass 34, count 0 2006.238.08:16:11.92#ibcon#about to write, iclass 34, count 0 2006.238.08:16:11.92#ibcon#wrote, iclass 34, count 0 2006.238.08:16:11.92#ibcon#about to read 3, iclass 34, count 0 2006.238.08:16:11.95#ibcon#read 3, iclass 34, count 0 2006.238.08:16:11.95#ibcon#about to read 4, iclass 34, count 0 2006.238.08:16:11.95#ibcon#read 4, iclass 34, count 0 2006.238.08:16:11.95#ibcon#about to read 5, iclass 34, count 0 2006.238.08:16:11.95#ibcon#read 5, iclass 34, count 0 2006.238.08:16:11.95#ibcon#about to read 6, iclass 34, count 0 2006.238.08:16:11.95#ibcon#read 6, iclass 34, count 0 2006.238.08:16:11.95#ibcon#end of sib2, iclass 34, count 0 2006.238.08:16:11.95#ibcon#*after write, iclass 34, count 0 2006.238.08:16:11.95#ibcon#*before return 0, iclass 34, count 0 2006.238.08:16:11.95#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:16:11.95#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.238.08:16:11.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.08:16:11.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.08:16:11.95$vc4f8/vblo=5,744.99 2006.238.08:16:11.95#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.238.08:16:11.95#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.238.08:16:11.95#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:11.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:16:11.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:16:11.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:16:11.95#ibcon#enter wrdev, iclass 36, count 0 2006.238.08:16:11.95#ibcon#first serial, iclass 36, count 0 2006.238.08:16:11.95#ibcon#enter sib2, iclass 36, count 0 2006.238.08:16:11.95#ibcon#flushed, iclass 36, count 0 2006.238.08:16:11.95#ibcon#about to write, iclass 36, count 0 2006.238.08:16:11.95#ibcon#wrote, iclass 36, count 0 2006.238.08:16:11.95#ibcon#about to read 3, iclass 36, count 0 2006.238.08:16:11.97#ibcon#read 3, iclass 36, count 0 2006.238.08:16:11.97#ibcon#about to read 4, iclass 36, count 0 2006.238.08:16:11.97#ibcon#read 4, iclass 36, count 0 2006.238.08:16:11.97#ibcon#about to read 5, iclass 36, count 0 2006.238.08:16:11.97#ibcon#read 5, iclass 36, count 0 2006.238.08:16:11.97#ibcon#about to read 6, iclass 36, count 0 2006.238.08:16:11.97#ibcon#read 6, iclass 36, count 0 2006.238.08:16:11.97#ibcon#end of sib2, iclass 36, count 0 2006.238.08:16:11.97#ibcon#*mode == 0, iclass 36, count 0 2006.238.08:16:11.97#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.08:16:11.97#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:16:11.97#ibcon#*before write, iclass 36, count 0 2006.238.08:16:11.97#ibcon#enter sib2, iclass 36, count 0 2006.238.08:16:11.97#ibcon#flushed, iclass 36, count 0 2006.238.08:16:11.97#ibcon#about to write, iclass 36, count 0 2006.238.08:16:11.97#ibcon#wrote, iclass 36, count 0 2006.238.08:16:11.97#ibcon#about to read 3, iclass 36, count 0 2006.238.08:16:12.01#ibcon#read 3, iclass 36, count 0 2006.238.08:16:12.01#ibcon#about to read 4, iclass 36, count 0 2006.238.08:16:12.01#ibcon#read 4, iclass 36, count 0 2006.238.08:16:12.01#ibcon#about to read 5, iclass 36, count 0 2006.238.08:16:12.01#ibcon#read 5, iclass 36, count 0 2006.238.08:16:12.01#ibcon#about to read 6, iclass 36, count 0 2006.238.08:16:12.01#ibcon#read 6, iclass 36, count 0 2006.238.08:16:12.01#ibcon#end of sib2, iclass 36, count 0 2006.238.08:16:12.01#ibcon#*after write, iclass 36, count 0 2006.238.08:16:12.01#ibcon#*before return 0, iclass 36, count 0 2006.238.08:16:12.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:16:12.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.238.08:16:12.01#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.08:16:12.01#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.08:16:12.01$vc4f8/vb=5,4 2006.238.08:16:12.01#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.238.08:16:12.01#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.238.08:16:12.01#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:12.01#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:16:12.07#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:16:12.07#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:16:12.07#ibcon#enter wrdev, iclass 38, count 2 2006.238.08:16:12.07#ibcon#first serial, iclass 38, count 2 2006.238.08:16:12.07#ibcon#enter sib2, iclass 38, count 2 2006.238.08:16:12.07#ibcon#flushed, iclass 38, count 2 2006.238.08:16:12.07#ibcon#about to write, iclass 38, count 2 2006.238.08:16:12.07#ibcon#wrote, iclass 38, count 2 2006.238.08:16:12.07#ibcon#about to read 3, iclass 38, count 2 2006.238.08:16:12.10#ibcon#read 3, iclass 38, count 2 2006.238.08:16:12.10#ibcon#about to read 4, iclass 38, count 2 2006.238.08:16:12.10#ibcon#read 4, iclass 38, count 2 2006.238.08:16:12.10#ibcon#about to read 5, iclass 38, count 2 2006.238.08:16:12.10#ibcon#read 5, iclass 38, count 2 2006.238.08:16:12.10#ibcon#about to read 6, iclass 38, count 2 2006.238.08:16:12.10#ibcon#read 6, iclass 38, count 2 2006.238.08:16:12.10#ibcon#end of sib2, iclass 38, count 2 2006.238.08:16:12.10#ibcon#*mode == 0, iclass 38, count 2 2006.238.08:16:12.10#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.238.08:16:12.10#ibcon#[27=AT05-04\r\n] 2006.238.08:16:12.10#ibcon#*before write, iclass 38, count 2 2006.238.08:16:12.10#ibcon#enter sib2, iclass 38, count 2 2006.238.08:16:12.10#ibcon#flushed, iclass 38, count 2 2006.238.08:16:12.10#ibcon#about to write, iclass 38, count 2 2006.238.08:16:12.10#ibcon#wrote, iclass 38, count 2 2006.238.08:16:12.10#ibcon#about to read 3, iclass 38, count 2 2006.238.08:16:12.13#ibcon#read 3, iclass 38, count 2 2006.238.08:16:12.13#ibcon#about to read 4, iclass 38, count 2 2006.238.08:16:12.13#ibcon#read 4, iclass 38, count 2 2006.238.08:16:12.13#ibcon#about to read 5, iclass 38, count 2 2006.238.08:16:12.13#ibcon#read 5, iclass 38, count 2 2006.238.08:16:12.13#ibcon#about to read 6, iclass 38, count 2 2006.238.08:16:12.13#ibcon#read 6, iclass 38, count 2 2006.238.08:16:12.13#ibcon#end of sib2, iclass 38, count 2 2006.238.08:16:12.13#ibcon#*after write, iclass 38, count 2 2006.238.08:16:12.13#ibcon#*before return 0, iclass 38, count 2 2006.238.08:16:12.13#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:16:12.13#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.238.08:16:12.13#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.238.08:16:12.13#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:12.13#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:16:12.25#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:16:12.25#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:16:12.25#ibcon#enter wrdev, iclass 38, count 0 2006.238.08:16:12.25#ibcon#first serial, iclass 38, count 0 2006.238.08:16:12.25#ibcon#enter sib2, iclass 38, count 0 2006.238.08:16:12.25#ibcon#flushed, iclass 38, count 0 2006.238.08:16:12.25#ibcon#about to write, iclass 38, count 0 2006.238.08:16:12.25#ibcon#wrote, iclass 38, count 0 2006.238.08:16:12.25#ibcon#about to read 3, iclass 38, count 0 2006.238.08:16:12.27#ibcon#read 3, iclass 38, count 0 2006.238.08:16:12.27#ibcon#about to read 4, iclass 38, count 0 2006.238.08:16:12.27#ibcon#read 4, iclass 38, count 0 2006.238.08:16:12.27#ibcon#about to read 5, iclass 38, count 0 2006.238.08:16:12.27#ibcon#read 5, iclass 38, count 0 2006.238.08:16:12.27#ibcon#about to read 6, iclass 38, count 0 2006.238.08:16:12.27#ibcon#read 6, iclass 38, count 0 2006.238.08:16:12.27#ibcon#end of sib2, iclass 38, count 0 2006.238.08:16:12.27#ibcon#*mode == 0, iclass 38, count 0 2006.238.08:16:12.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.08:16:12.27#ibcon#[27=USB\r\n] 2006.238.08:16:12.27#ibcon#*before write, iclass 38, count 0 2006.238.08:16:12.27#ibcon#enter sib2, iclass 38, count 0 2006.238.08:16:12.27#ibcon#flushed, iclass 38, count 0 2006.238.08:16:12.27#ibcon#about to write, iclass 38, count 0 2006.238.08:16:12.27#ibcon#wrote, iclass 38, count 0 2006.238.08:16:12.27#ibcon#about to read 3, iclass 38, count 0 2006.238.08:16:12.30#ibcon#read 3, iclass 38, count 0 2006.238.08:16:12.30#ibcon#about to read 4, iclass 38, count 0 2006.238.08:16:12.30#ibcon#read 4, iclass 38, count 0 2006.238.08:16:12.30#ibcon#about to read 5, iclass 38, count 0 2006.238.08:16:12.30#ibcon#read 5, iclass 38, count 0 2006.238.08:16:12.30#ibcon#about to read 6, iclass 38, count 0 2006.238.08:16:12.30#ibcon#read 6, iclass 38, count 0 2006.238.08:16:12.30#ibcon#end of sib2, iclass 38, count 0 2006.238.08:16:12.30#ibcon#*after write, iclass 38, count 0 2006.238.08:16:12.30#ibcon#*before return 0, iclass 38, count 0 2006.238.08:16:12.30#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:16:12.30#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.238.08:16:12.30#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.08:16:12.30#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.08:16:12.30$vc4f8/vblo=6,752.99 2006.238.08:16:12.30#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.238.08:16:12.30#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.238.08:16:12.30#ibcon#ireg 17 cls_cnt 0 2006.238.08:16:12.30#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:16:12.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:16:12.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:16:12.30#ibcon#enter wrdev, iclass 40, count 0 2006.238.08:16:12.30#ibcon#first serial, iclass 40, count 0 2006.238.08:16:12.30#ibcon#enter sib2, iclass 40, count 0 2006.238.08:16:12.30#ibcon#flushed, iclass 40, count 0 2006.238.08:16:12.30#ibcon#about to write, iclass 40, count 0 2006.238.08:16:12.30#ibcon#wrote, iclass 40, count 0 2006.238.08:16:12.30#ibcon#about to read 3, iclass 40, count 0 2006.238.08:16:12.32#ibcon#read 3, iclass 40, count 0 2006.238.08:16:12.32#ibcon#about to read 4, iclass 40, count 0 2006.238.08:16:12.32#ibcon#read 4, iclass 40, count 0 2006.238.08:16:12.32#ibcon#about to read 5, iclass 40, count 0 2006.238.08:16:12.32#ibcon#read 5, iclass 40, count 0 2006.238.08:16:12.32#ibcon#about to read 6, iclass 40, count 0 2006.238.08:16:12.32#ibcon#read 6, iclass 40, count 0 2006.238.08:16:12.32#ibcon#end of sib2, iclass 40, count 0 2006.238.08:16:12.32#ibcon#*mode == 0, iclass 40, count 0 2006.238.08:16:12.32#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.08:16:12.32#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:16:12.32#ibcon#*before write, iclass 40, count 0 2006.238.08:16:12.32#ibcon#enter sib2, iclass 40, count 0 2006.238.08:16:12.32#ibcon#flushed, iclass 40, count 0 2006.238.08:16:12.32#ibcon#about to write, iclass 40, count 0 2006.238.08:16:12.32#ibcon#wrote, iclass 40, count 0 2006.238.08:16:12.32#ibcon#about to read 3, iclass 40, count 0 2006.238.08:16:12.36#ibcon#read 3, iclass 40, count 0 2006.238.08:16:12.36#ibcon#about to read 4, iclass 40, count 0 2006.238.08:16:12.36#ibcon#read 4, iclass 40, count 0 2006.238.08:16:12.36#ibcon#about to read 5, iclass 40, count 0 2006.238.08:16:12.36#ibcon#read 5, iclass 40, count 0 2006.238.08:16:12.36#ibcon#about to read 6, iclass 40, count 0 2006.238.08:16:12.36#ibcon#read 6, iclass 40, count 0 2006.238.08:16:12.36#ibcon#end of sib2, iclass 40, count 0 2006.238.08:16:12.36#ibcon#*after write, iclass 40, count 0 2006.238.08:16:12.36#ibcon#*before return 0, iclass 40, count 0 2006.238.08:16:12.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:16:12.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.238.08:16:12.36#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.08:16:12.36#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.08:16:12.36$vc4f8/vb=6,4 2006.238.08:16:12.36#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.238.08:16:12.36#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.238.08:16:12.36#ibcon#ireg 11 cls_cnt 2 2006.238.08:16:12.36#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:16:12.42#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:16:12.42#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:16:12.42#ibcon#enter wrdev, iclass 4, count 2 2006.238.08:16:12.42#ibcon#first serial, iclass 4, count 2 2006.238.08:16:12.42#ibcon#enter sib2, iclass 4, count 2 2006.238.08:16:12.42#ibcon#flushed, iclass 4, count 2 2006.238.08:16:12.42#ibcon#about to write, iclass 4, count 2 2006.238.08:16:12.42#ibcon#wrote, iclass 4, count 2 2006.238.08:16:12.42#ibcon#about to read 3, iclass 4, count 2 2006.238.08:16:12.44#ibcon#read 3, iclass 4, count 2 2006.238.08:16:12.44#ibcon#about to read 4, iclass 4, count 2 2006.238.08:16:12.44#ibcon#read 4, iclass 4, count 2 2006.238.08:16:12.44#ibcon#about to read 5, iclass 4, count 2 2006.238.08:16:12.44#ibcon#read 5, iclass 4, count 2 2006.238.08:16:12.44#ibcon#about to read 6, iclass 4, count 2 2006.238.08:16:12.44#ibcon#read 6, iclass 4, count 2 2006.238.08:16:12.44#ibcon#end of sib2, iclass 4, count 2 2006.238.08:16:12.44#ibcon#*mode == 0, iclass 4, count 2 2006.238.08:16:12.44#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.238.08:16:12.44#ibcon#[27=AT06-04\r\n] 2006.238.08:16:12.44#ibcon#*before write, iclass 4, count 2 2006.238.08:16:12.44#ibcon#enter sib2, iclass 4, count 2 2006.238.08:16:12.44#ibcon#flushed, iclass 4, count 2 2006.238.08:16:12.44#ibcon#about to write, iclass 4, count 2 2006.238.08:16:12.44#ibcon#wrote, iclass 4, count 2 2006.238.08:16:12.44#ibcon#about to read 3, iclass 4, count 2 2006.238.08:16:12.47#ibcon#read 3, iclass 4, count 2 2006.238.08:16:12.47#ibcon#about to read 4, iclass 4, count 2 2006.238.08:16:12.47#ibcon#read 4, iclass 4, count 2 2006.238.08:16:12.47#ibcon#about to read 5, iclass 4, count 2 2006.238.08:16:12.47#ibcon#read 5, iclass 4, count 2 2006.238.08:16:12.47#ibcon#about to read 6, iclass 4, count 2 2006.238.08:16:12.47#ibcon#read 6, iclass 4, count 2 2006.238.08:16:12.47#ibcon#end of sib2, iclass 4, count 2 2006.238.08:16:12.47#ibcon#*after write, iclass 4, count 2 2006.238.08:16:12.47#ibcon#*before return 0, iclass 4, count 2 2006.238.08:16:12.47#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:16:12.47#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.238.08:16:12.47#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.238.08:16:12.47#ibcon#ireg 7 cls_cnt 0 2006.238.08:16:12.47#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:16:12.59#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:16:12.59#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:16:12.59#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:16:12.59#ibcon#first serial, iclass 4, count 0 2006.238.08:16:12.59#ibcon#enter sib2, iclass 4, count 0 2006.238.08:16:12.59#ibcon#flushed, iclass 4, count 0 2006.238.08:16:12.59#ibcon#about to write, iclass 4, count 0 2006.238.08:16:12.59#ibcon#wrote, iclass 4, count 0 2006.238.08:16:12.59#ibcon#about to read 3, iclass 4, count 0 2006.238.08:16:12.61#ibcon#read 3, iclass 4, count 0 2006.238.08:16:12.61#ibcon#about to read 4, iclass 4, count 0 2006.238.08:16:12.61#ibcon#read 4, iclass 4, count 0 2006.238.08:16:12.61#ibcon#about to read 5, iclass 4, count 0 2006.238.08:16:12.61#ibcon#read 5, iclass 4, count 0 2006.238.08:16:12.61#ibcon#about to read 6, iclass 4, count 0 2006.238.08:16:12.61#ibcon#read 6, iclass 4, count 0 2006.238.08:16:12.61#ibcon#end of sib2, iclass 4, count 0 2006.238.08:16:12.61#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:16:12.61#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:16:12.61#ibcon#[27=USB\r\n] 2006.238.08:16:12.61#ibcon#*before write, iclass 4, count 0 2006.238.08:16:12.61#ibcon#enter sib2, iclass 4, count 0 2006.238.08:16:12.61#ibcon#flushed, iclass 4, count 0 2006.238.08:16:12.61#ibcon#about to write, iclass 4, count 0 2006.238.08:16:12.61#ibcon#wrote, iclass 4, count 0 2006.238.08:16:12.61#ibcon#about to read 3, iclass 4, count 0 2006.238.08:16:12.64#ibcon#read 3, iclass 4, count 0 2006.238.08:16:12.64#ibcon#about to read 4, iclass 4, count 0 2006.238.08:16:12.64#ibcon#read 4, iclass 4, count 0 2006.238.08:16:12.64#ibcon#about to read 5, iclass 4, count 0 2006.238.08:16:12.64#ibcon#read 5, iclass 4, count 0 2006.238.08:16:12.64#ibcon#about to read 6, iclass 4, count 0 2006.238.08:16:12.64#ibcon#read 6, iclass 4, count 0 2006.238.08:16:12.64#ibcon#end of sib2, iclass 4, count 0 2006.238.08:16:12.64#ibcon#*after write, iclass 4, count 0 2006.238.08:16:12.64#ibcon#*before return 0, iclass 4, count 0 2006.238.08:16:12.64#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:16:12.64#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.238.08:16:12.64#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:16:12.64#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:16:12.64$vc4f8/vabw=wide 2006.238.08:16:12.64#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.238.08:16:12.64#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.238.08:16:12.64#ibcon#ireg 8 cls_cnt 0 2006.238.08:16:12.64#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:16:12.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:16:12.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:16:12.64#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:16:12.64#ibcon#first serial, iclass 6, count 0 2006.238.08:16:12.64#ibcon#enter sib2, iclass 6, count 0 2006.238.08:16:12.64#ibcon#flushed, iclass 6, count 0 2006.238.08:16:12.64#ibcon#about to write, iclass 6, count 0 2006.238.08:16:12.64#ibcon#wrote, iclass 6, count 0 2006.238.08:16:12.64#ibcon#about to read 3, iclass 6, count 0 2006.238.08:16:12.66#ibcon#read 3, iclass 6, count 0 2006.238.08:16:12.66#ibcon#about to read 4, iclass 6, count 0 2006.238.08:16:12.66#ibcon#read 4, iclass 6, count 0 2006.238.08:16:12.66#ibcon#about to read 5, iclass 6, count 0 2006.238.08:16:12.66#ibcon#read 5, iclass 6, count 0 2006.238.08:16:12.66#ibcon#about to read 6, iclass 6, count 0 2006.238.08:16:12.66#ibcon#read 6, iclass 6, count 0 2006.238.08:16:12.66#ibcon#end of sib2, iclass 6, count 0 2006.238.08:16:12.66#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:16:12.66#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:16:12.66#ibcon#[25=BW32\r\n] 2006.238.08:16:12.66#ibcon#*before write, iclass 6, count 0 2006.238.08:16:12.66#ibcon#enter sib2, iclass 6, count 0 2006.238.08:16:12.66#ibcon#flushed, iclass 6, count 0 2006.238.08:16:12.66#ibcon#about to write, iclass 6, count 0 2006.238.08:16:12.66#ibcon#wrote, iclass 6, count 0 2006.238.08:16:12.66#ibcon#about to read 3, iclass 6, count 0 2006.238.08:16:12.69#ibcon#read 3, iclass 6, count 0 2006.238.08:16:12.69#ibcon#about to read 4, iclass 6, count 0 2006.238.08:16:12.69#ibcon#read 4, iclass 6, count 0 2006.238.08:16:12.69#ibcon#about to read 5, iclass 6, count 0 2006.238.08:16:12.69#ibcon#read 5, iclass 6, count 0 2006.238.08:16:12.69#ibcon#about to read 6, iclass 6, count 0 2006.238.08:16:12.69#ibcon#read 6, iclass 6, count 0 2006.238.08:16:12.69#ibcon#end of sib2, iclass 6, count 0 2006.238.08:16:12.69#ibcon#*after write, iclass 6, count 0 2006.238.08:16:12.69#ibcon#*before return 0, iclass 6, count 0 2006.238.08:16:12.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:16:12.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.238.08:16:12.69#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:16:12.69#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:16:12.69$vc4f8/vbbw=wide 2006.238.08:16:12.69#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.08:16:12.69#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.08:16:12.69#ibcon#ireg 8 cls_cnt 0 2006.238.08:16:12.69#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:16:12.76#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:16:12.76#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:16:12.76#ibcon#enter wrdev, iclass 10, count 0 2006.238.08:16:12.76#ibcon#first serial, iclass 10, count 0 2006.238.08:16:12.76#ibcon#enter sib2, iclass 10, count 0 2006.238.08:16:12.76#ibcon#flushed, iclass 10, count 0 2006.238.08:16:12.76#ibcon#about to write, iclass 10, count 0 2006.238.08:16:12.76#ibcon#wrote, iclass 10, count 0 2006.238.08:16:12.76#ibcon#about to read 3, iclass 10, count 0 2006.238.08:16:12.78#ibcon#read 3, iclass 10, count 0 2006.238.08:16:12.78#ibcon#about to read 4, iclass 10, count 0 2006.238.08:16:12.78#ibcon#read 4, iclass 10, count 0 2006.238.08:16:12.78#ibcon#about to read 5, iclass 10, count 0 2006.238.08:16:12.78#ibcon#read 5, iclass 10, count 0 2006.238.08:16:12.78#ibcon#about to read 6, iclass 10, count 0 2006.238.08:16:12.78#ibcon#read 6, iclass 10, count 0 2006.238.08:16:12.78#ibcon#end of sib2, iclass 10, count 0 2006.238.08:16:12.78#ibcon#*mode == 0, iclass 10, count 0 2006.238.08:16:12.78#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.08:16:12.78#ibcon#[27=BW32\r\n] 2006.238.08:16:12.78#ibcon#*before write, iclass 10, count 0 2006.238.08:16:12.78#ibcon#enter sib2, iclass 10, count 0 2006.238.08:16:12.78#ibcon#flushed, iclass 10, count 0 2006.238.08:16:12.78#ibcon#about to write, iclass 10, count 0 2006.238.08:16:12.78#ibcon#wrote, iclass 10, count 0 2006.238.08:16:12.78#ibcon#about to read 3, iclass 10, count 0 2006.238.08:16:12.81#ibcon#read 3, iclass 10, count 0 2006.238.08:16:12.81#ibcon#about to read 4, iclass 10, count 0 2006.238.08:16:12.81#ibcon#read 4, iclass 10, count 0 2006.238.08:16:12.81#ibcon#about to read 5, iclass 10, count 0 2006.238.08:16:12.81#ibcon#read 5, iclass 10, count 0 2006.238.08:16:12.81#ibcon#about to read 6, iclass 10, count 0 2006.238.08:16:12.81#ibcon#read 6, iclass 10, count 0 2006.238.08:16:12.81#ibcon#end of sib2, iclass 10, count 0 2006.238.08:16:12.81#ibcon#*after write, iclass 10, count 0 2006.238.08:16:12.81#ibcon#*before return 0, iclass 10, count 0 2006.238.08:16:12.81#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:16:12.81#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:16:12.81#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.08:16:12.81#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.08:16:12.81$4f8m12a/ifd4f 2006.238.08:16:12.81$ifd4f/lo= 2006.238.08:16:12.81$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:16:12.81$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:16:12.81$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:16:12.81$ifd4f/patch= 2006.238.08:16:12.81$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:16:12.81$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:16:12.81$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:16:12.81$4f8m12a/"form=m,16.000,1:2 2006.238.08:16:12.81$4f8m12a/"tpicd 2006.238.08:16:12.81$4f8m12a/echo=off 2006.238.08:16:12.81$4f8m12a/xlog=off 2006.238.08:16:12.81:!2006.238.08:16:40 2006.238.08:16:21.13#trakl#Source acquired 2006.238.08:16:22.13#flagr#flagr/antenna,acquired 2006.238.08:16:40.00:preob 2006.238.08:16:41.13/onsource/TRACKING 2006.238.08:16:41.13:!2006.238.08:16:50 2006.238.08:16:50.00:data_valid=on 2006.238.08:16:50.00:midob 2006.238.08:16:50.13/onsource/TRACKING 2006.238.08:16:50.13/wx/25.47,1012.3,91 2006.238.08:16:50.18/cable/+6.4168E-03 2006.238.08:16:51.27/va/01,08,usb,yes,35,37 2006.238.08:16:51.27/va/02,07,usb,yes,35,37 2006.238.08:16:51.27/va/03,07,usb,yes,33,33 2006.238.08:16:51.27/va/04,07,usb,yes,36,39 2006.238.08:16:51.27/va/05,08,usb,yes,34,36 2006.238.08:16:51.27/va/06,07,usb,yes,37,37 2006.238.08:16:51.27/va/07,07,usb,yes,37,36 2006.238.08:16:51.27/va/08,07,usb,yes,39,39 2006.238.08:16:51.50/valo/01,532.99,yes,locked 2006.238.08:16:51.50/valo/02,572.99,yes,locked 2006.238.08:16:51.50/valo/03,672.99,yes,locked 2006.238.08:16:51.50/valo/04,832.99,yes,locked 2006.238.08:16:51.50/valo/05,652.99,yes,locked 2006.238.08:16:51.50/valo/06,772.99,yes,locked 2006.238.08:16:51.50/valo/07,832.99,yes,locked 2006.238.08:16:51.50/valo/08,852.99,yes,locked 2006.238.08:16:52.59/vb/01,04,usb,yes,33,31 2006.238.08:16:52.59/vb/02,04,usb,yes,34,36 2006.238.08:16:52.59/vb/03,04,usb,yes,31,35 2006.238.08:16:52.59/vb/04,04,usb,yes,32,32 2006.238.08:16:52.59/vb/05,04,usb,yes,30,34 2006.238.08:16:52.59/vb/06,04,usb,yes,31,34 2006.238.08:16:52.59/vb/07,04,usb,yes,33,33 2006.238.08:16:52.59/vb/08,04,usb,yes,30,34 2006.238.08:16:52.83/vblo/01,632.99,yes,locked 2006.238.08:16:52.83/vblo/02,640.99,yes,locked 2006.238.08:16:52.83/vblo/03,656.99,yes,locked 2006.238.08:16:52.83/vblo/04,712.99,yes,locked 2006.238.08:16:52.83/vblo/05,744.99,yes,locked 2006.238.08:16:52.83/vblo/06,752.99,yes,locked 2006.238.08:16:52.83/vblo/07,734.99,yes,locked 2006.238.08:16:52.83/vblo/08,744.99,yes,locked 2006.238.08:16:52.98/vabw/8 2006.238.08:16:53.13/vbbw/8 2006.238.08:16:53.22/xfe/off,on,13.7 2006.238.08:16:53.60/ifatt/23,28,28,28 2006.238.08:16:54.08/fmout-gps/S +4.43E-07 2006.238.08:16:54.12:!2006.238.08:17:50 2006.238.08:17:50.00:data_valid=off 2006.238.08:17:50.00:postob 2006.238.08:17:50.06/cable/+6.4185E-03 2006.238.08:17:50.06/wx/25.46,1012.3,91 2006.238.08:17:51.07/fmout-gps/S +4.46E-07 2006.238.08:17:51.07:scan_name=238-0819,k06238,60 2006.238.08:17:51.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.238.08:17:51.13#flagr#flagr/antenna,new-source 2006.238.08:17:52.14:checkk5 2006.238.08:17:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:17:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:17:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:17:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:17:54.02/chk_obsdata//k5ts1/T2380816??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:17:54.39/chk_obsdata//k5ts2/T2380816??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:17:54.76/chk_obsdata//k5ts3/T2380816??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:17:55.14/chk_obsdata//k5ts4/T2380816??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:17:55.84/k5log//k5ts1_log_newline 2006.238.08:17:56.53/k5log//k5ts2_log_newline 2006.238.08:17:57.22/k5log//k5ts3_log_newline 2006.238.08:17:57.90/k5log//k5ts4_log_newline 2006.238.08:17:57.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:17:57.93:4f8m12a=3 2006.238.08:17:57.93$4f8m12a/echo=on 2006.238.08:17:57.93$4f8m12a/pcalon 2006.238.08:17:57.93$pcalon/"no phase cal control is implemented here 2006.238.08:17:57.93$4f8m12a/"tpicd=stop 2006.238.08:17:57.93$4f8m12a/vc4f8 2006.238.08:17:57.93$vc4f8/valo=1,532.99 2006.238.08:17:57.94#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.08:17:57.94#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.08:17:57.94#ibcon#ireg 17 cls_cnt 0 2006.238.08:17:57.94#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:17:57.94#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:17:57.94#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:17:57.94#ibcon#enter wrdev, iclass 21, count 0 2006.238.08:17:57.94#ibcon#first serial, iclass 21, count 0 2006.238.08:17:57.94#ibcon#enter sib2, iclass 21, count 0 2006.238.08:17:57.94#ibcon#flushed, iclass 21, count 0 2006.238.08:17:57.94#ibcon#about to write, iclass 21, count 0 2006.238.08:17:57.94#ibcon#wrote, iclass 21, count 0 2006.238.08:17:57.94#ibcon#about to read 3, iclass 21, count 0 2006.238.08:17:57.98#ibcon#read 3, iclass 21, count 0 2006.238.08:17:57.98#ibcon#about to read 4, iclass 21, count 0 2006.238.08:17:57.98#ibcon#read 4, iclass 21, count 0 2006.238.08:17:57.98#ibcon#about to read 5, iclass 21, count 0 2006.238.08:17:57.98#ibcon#read 5, iclass 21, count 0 2006.238.08:17:57.98#ibcon#about to read 6, iclass 21, count 0 2006.238.08:17:57.98#ibcon#read 6, iclass 21, count 0 2006.238.08:17:57.98#ibcon#end of sib2, iclass 21, count 0 2006.238.08:17:57.98#ibcon#*mode == 0, iclass 21, count 0 2006.238.08:17:57.98#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.08:17:57.98#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:17:57.98#ibcon#*before write, iclass 21, count 0 2006.238.08:17:57.98#ibcon#enter sib2, iclass 21, count 0 2006.238.08:17:57.98#ibcon#flushed, iclass 21, count 0 2006.238.08:17:57.98#ibcon#about to write, iclass 21, count 0 2006.238.08:17:57.98#ibcon#wrote, iclass 21, count 0 2006.238.08:17:57.98#ibcon#about to read 3, iclass 21, count 0 2006.238.08:17:58.02#ibcon#read 3, iclass 21, count 0 2006.238.08:17:58.02#ibcon#about to read 4, iclass 21, count 0 2006.238.08:17:58.02#ibcon#read 4, iclass 21, count 0 2006.238.08:17:58.02#ibcon#about to read 5, iclass 21, count 0 2006.238.08:17:58.02#ibcon#read 5, iclass 21, count 0 2006.238.08:17:58.02#ibcon#about to read 6, iclass 21, count 0 2006.238.08:17:58.02#ibcon#read 6, iclass 21, count 0 2006.238.08:17:58.02#ibcon#end of sib2, iclass 21, count 0 2006.238.08:17:58.02#ibcon#*after write, iclass 21, count 0 2006.238.08:17:58.02#ibcon#*before return 0, iclass 21, count 0 2006.238.08:17:58.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:17:58.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:17:58.02#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.08:17:58.02#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.08:17:58.02$vc4f8/va=1,8 2006.238.08:17:58.02#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.238.08:17:58.02#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.238.08:17:58.02#ibcon#ireg 11 cls_cnt 2 2006.238.08:17:58.02#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:17:58.02#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:17:58.02#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:17:58.02#ibcon#enter wrdev, iclass 23, count 2 2006.238.08:17:58.02#ibcon#first serial, iclass 23, count 2 2006.238.08:17:58.02#ibcon#enter sib2, iclass 23, count 2 2006.238.08:17:58.02#ibcon#flushed, iclass 23, count 2 2006.238.08:17:58.02#ibcon#about to write, iclass 23, count 2 2006.238.08:17:58.02#ibcon#wrote, iclass 23, count 2 2006.238.08:17:58.02#ibcon#about to read 3, iclass 23, count 2 2006.238.08:17:58.04#ibcon#read 3, iclass 23, count 2 2006.238.08:17:58.04#ibcon#about to read 4, iclass 23, count 2 2006.238.08:17:58.04#ibcon#read 4, iclass 23, count 2 2006.238.08:17:58.04#ibcon#about to read 5, iclass 23, count 2 2006.238.08:17:58.04#ibcon#read 5, iclass 23, count 2 2006.238.08:17:58.04#ibcon#about to read 6, iclass 23, count 2 2006.238.08:17:58.04#ibcon#read 6, iclass 23, count 2 2006.238.08:17:58.04#ibcon#end of sib2, iclass 23, count 2 2006.238.08:17:58.04#ibcon#*mode == 0, iclass 23, count 2 2006.238.08:17:58.04#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.238.08:17:58.04#ibcon#[25=AT01-08\r\n] 2006.238.08:17:58.04#ibcon#*before write, iclass 23, count 2 2006.238.08:17:58.04#ibcon#enter sib2, iclass 23, count 2 2006.238.08:17:58.04#ibcon#flushed, iclass 23, count 2 2006.238.08:17:58.04#ibcon#about to write, iclass 23, count 2 2006.238.08:17:58.04#ibcon#wrote, iclass 23, count 2 2006.238.08:17:58.04#ibcon#about to read 3, iclass 23, count 2 2006.238.08:17:58.07#ibcon#read 3, iclass 23, count 2 2006.238.08:17:58.07#ibcon#about to read 4, iclass 23, count 2 2006.238.08:17:58.07#ibcon#read 4, iclass 23, count 2 2006.238.08:17:58.07#ibcon#about to read 5, iclass 23, count 2 2006.238.08:17:58.07#ibcon#read 5, iclass 23, count 2 2006.238.08:17:58.07#ibcon#about to read 6, iclass 23, count 2 2006.238.08:17:58.07#ibcon#read 6, iclass 23, count 2 2006.238.08:17:58.07#ibcon#end of sib2, iclass 23, count 2 2006.238.08:17:58.07#ibcon#*after write, iclass 23, count 2 2006.238.08:17:58.07#ibcon#*before return 0, iclass 23, count 2 2006.238.08:17:58.07#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:17:58.07#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:17:58.07#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.238.08:17:58.07#ibcon#ireg 7 cls_cnt 0 2006.238.08:17:58.07#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:17:58.19#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:17:58.19#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:17:58.19#ibcon#enter wrdev, iclass 23, count 0 2006.238.08:17:58.19#ibcon#first serial, iclass 23, count 0 2006.238.08:17:58.19#ibcon#enter sib2, iclass 23, count 0 2006.238.08:17:58.19#ibcon#flushed, iclass 23, count 0 2006.238.08:17:58.19#ibcon#about to write, iclass 23, count 0 2006.238.08:17:58.19#ibcon#wrote, iclass 23, count 0 2006.238.08:17:58.19#ibcon#about to read 3, iclass 23, count 0 2006.238.08:17:58.21#ibcon#read 3, iclass 23, count 0 2006.238.08:17:58.21#ibcon#about to read 4, iclass 23, count 0 2006.238.08:17:58.21#ibcon#read 4, iclass 23, count 0 2006.238.08:17:58.21#ibcon#about to read 5, iclass 23, count 0 2006.238.08:17:58.21#ibcon#read 5, iclass 23, count 0 2006.238.08:17:58.21#ibcon#about to read 6, iclass 23, count 0 2006.238.08:17:58.21#ibcon#read 6, iclass 23, count 0 2006.238.08:17:58.21#ibcon#end of sib2, iclass 23, count 0 2006.238.08:17:58.21#ibcon#*mode == 0, iclass 23, count 0 2006.238.08:17:58.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.08:17:58.21#ibcon#[25=USB\r\n] 2006.238.08:17:58.21#ibcon#*before write, iclass 23, count 0 2006.238.08:17:58.21#ibcon#enter sib2, iclass 23, count 0 2006.238.08:17:58.21#ibcon#flushed, iclass 23, count 0 2006.238.08:17:58.21#ibcon#about to write, iclass 23, count 0 2006.238.08:17:58.21#ibcon#wrote, iclass 23, count 0 2006.238.08:17:58.21#ibcon#about to read 3, iclass 23, count 0 2006.238.08:17:58.24#ibcon#read 3, iclass 23, count 0 2006.238.08:17:58.24#ibcon#about to read 4, iclass 23, count 0 2006.238.08:17:58.24#ibcon#read 4, iclass 23, count 0 2006.238.08:17:58.24#ibcon#about to read 5, iclass 23, count 0 2006.238.08:17:58.24#ibcon#read 5, iclass 23, count 0 2006.238.08:17:58.24#ibcon#about to read 6, iclass 23, count 0 2006.238.08:17:58.24#ibcon#read 6, iclass 23, count 0 2006.238.08:17:58.24#ibcon#end of sib2, iclass 23, count 0 2006.238.08:17:58.24#ibcon#*after write, iclass 23, count 0 2006.238.08:17:58.24#ibcon#*before return 0, iclass 23, count 0 2006.238.08:17:58.24#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:17:58.24#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:17:58.24#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.08:17:58.24#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.08:17:58.24$vc4f8/valo=2,572.99 2006.238.08:17:58.24#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.08:17:58.24#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.08:17:58.24#ibcon#ireg 17 cls_cnt 0 2006.238.08:17:58.24#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:17:58.24#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:17:58.24#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:17:58.24#ibcon#enter wrdev, iclass 25, count 0 2006.238.08:17:58.24#ibcon#first serial, iclass 25, count 0 2006.238.08:17:58.24#ibcon#enter sib2, iclass 25, count 0 2006.238.08:17:58.24#ibcon#flushed, iclass 25, count 0 2006.238.08:17:58.24#ibcon#about to write, iclass 25, count 0 2006.238.08:17:58.24#ibcon#wrote, iclass 25, count 0 2006.238.08:17:58.24#ibcon#about to read 3, iclass 25, count 0 2006.238.08:17:58.26#ibcon#read 3, iclass 25, count 0 2006.238.08:17:58.26#ibcon#about to read 4, iclass 25, count 0 2006.238.08:17:58.26#ibcon#read 4, iclass 25, count 0 2006.238.08:17:58.26#ibcon#about to read 5, iclass 25, count 0 2006.238.08:17:58.26#ibcon#read 5, iclass 25, count 0 2006.238.08:17:58.26#ibcon#about to read 6, iclass 25, count 0 2006.238.08:17:58.26#ibcon#read 6, iclass 25, count 0 2006.238.08:17:58.26#ibcon#end of sib2, iclass 25, count 0 2006.238.08:17:58.26#ibcon#*mode == 0, iclass 25, count 0 2006.238.08:17:58.26#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.08:17:58.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:17:58.26#ibcon#*before write, iclass 25, count 0 2006.238.08:17:58.26#ibcon#enter sib2, iclass 25, count 0 2006.238.08:17:58.26#ibcon#flushed, iclass 25, count 0 2006.238.08:17:58.26#ibcon#about to write, iclass 25, count 0 2006.238.08:17:58.26#ibcon#wrote, iclass 25, count 0 2006.238.08:17:58.26#ibcon#about to read 3, iclass 25, count 0 2006.238.08:17:58.30#ibcon#read 3, iclass 25, count 0 2006.238.08:17:58.30#ibcon#about to read 4, iclass 25, count 0 2006.238.08:17:58.30#ibcon#read 4, iclass 25, count 0 2006.238.08:17:58.30#ibcon#about to read 5, iclass 25, count 0 2006.238.08:17:58.30#ibcon#read 5, iclass 25, count 0 2006.238.08:17:58.30#ibcon#about to read 6, iclass 25, count 0 2006.238.08:17:58.30#ibcon#read 6, iclass 25, count 0 2006.238.08:17:58.30#ibcon#end of sib2, iclass 25, count 0 2006.238.08:17:58.30#ibcon#*after write, iclass 25, count 0 2006.238.08:17:58.30#ibcon#*before return 0, iclass 25, count 0 2006.238.08:17:58.30#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:17:58.30#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:17:58.30#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.08:17:58.30#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.08:17:58.30$vc4f8/va=2,7 2006.238.08:17:58.30#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.238.08:17:58.30#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.238.08:17:58.30#ibcon#ireg 11 cls_cnt 2 2006.238.08:17:58.30#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:17:58.36#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:17:58.36#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:17:58.36#ibcon#enter wrdev, iclass 27, count 2 2006.238.08:17:58.36#ibcon#first serial, iclass 27, count 2 2006.238.08:17:58.36#ibcon#enter sib2, iclass 27, count 2 2006.238.08:17:58.36#ibcon#flushed, iclass 27, count 2 2006.238.08:17:58.36#ibcon#about to write, iclass 27, count 2 2006.238.08:17:58.36#ibcon#wrote, iclass 27, count 2 2006.238.08:17:58.36#ibcon#about to read 3, iclass 27, count 2 2006.238.08:17:58.38#ibcon#read 3, iclass 27, count 2 2006.238.08:17:58.38#ibcon#about to read 4, iclass 27, count 2 2006.238.08:17:58.38#ibcon#read 4, iclass 27, count 2 2006.238.08:17:58.38#ibcon#about to read 5, iclass 27, count 2 2006.238.08:17:58.38#ibcon#read 5, iclass 27, count 2 2006.238.08:17:58.38#ibcon#about to read 6, iclass 27, count 2 2006.238.08:17:58.38#ibcon#read 6, iclass 27, count 2 2006.238.08:17:58.38#ibcon#end of sib2, iclass 27, count 2 2006.238.08:17:58.38#ibcon#*mode == 0, iclass 27, count 2 2006.238.08:17:58.38#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.238.08:17:58.38#ibcon#[25=AT02-07\r\n] 2006.238.08:17:58.38#ibcon#*before write, iclass 27, count 2 2006.238.08:17:58.38#ibcon#enter sib2, iclass 27, count 2 2006.238.08:17:58.38#ibcon#flushed, iclass 27, count 2 2006.238.08:17:58.38#ibcon#about to write, iclass 27, count 2 2006.238.08:17:58.38#ibcon#wrote, iclass 27, count 2 2006.238.08:17:58.38#ibcon#about to read 3, iclass 27, count 2 2006.238.08:17:58.41#ibcon#read 3, iclass 27, count 2 2006.238.08:17:58.41#ibcon#about to read 4, iclass 27, count 2 2006.238.08:17:58.41#ibcon#read 4, iclass 27, count 2 2006.238.08:17:58.41#ibcon#about to read 5, iclass 27, count 2 2006.238.08:17:58.41#ibcon#read 5, iclass 27, count 2 2006.238.08:17:58.41#ibcon#about to read 6, iclass 27, count 2 2006.238.08:17:58.41#ibcon#read 6, iclass 27, count 2 2006.238.08:17:58.41#ibcon#end of sib2, iclass 27, count 2 2006.238.08:17:58.41#ibcon#*after write, iclass 27, count 2 2006.238.08:17:58.41#ibcon#*before return 0, iclass 27, count 2 2006.238.08:17:58.41#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:17:58.41#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:17:58.41#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.238.08:17:58.41#ibcon#ireg 7 cls_cnt 0 2006.238.08:17:58.41#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:17:58.53#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:17:58.53#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:17:58.53#ibcon#enter wrdev, iclass 27, count 0 2006.238.08:17:58.53#ibcon#first serial, iclass 27, count 0 2006.238.08:17:58.53#ibcon#enter sib2, iclass 27, count 0 2006.238.08:17:58.53#ibcon#flushed, iclass 27, count 0 2006.238.08:17:58.53#ibcon#about to write, iclass 27, count 0 2006.238.08:17:58.53#ibcon#wrote, iclass 27, count 0 2006.238.08:17:58.53#ibcon#about to read 3, iclass 27, count 0 2006.238.08:17:58.55#ibcon#read 3, iclass 27, count 0 2006.238.08:17:58.55#ibcon#about to read 4, iclass 27, count 0 2006.238.08:17:58.55#ibcon#read 4, iclass 27, count 0 2006.238.08:17:58.55#ibcon#about to read 5, iclass 27, count 0 2006.238.08:17:58.55#ibcon#read 5, iclass 27, count 0 2006.238.08:17:58.55#ibcon#about to read 6, iclass 27, count 0 2006.238.08:17:58.55#ibcon#read 6, iclass 27, count 0 2006.238.08:17:58.55#ibcon#end of sib2, iclass 27, count 0 2006.238.08:17:58.55#ibcon#*mode == 0, iclass 27, count 0 2006.238.08:17:58.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.08:17:58.55#ibcon#[25=USB\r\n] 2006.238.08:17:58.55#ibcon#*before write, iclass 27, count 0 2006.238.08:17:58.55#ibcon#enter sib2, iclass 27, count 0 2006.238.08:17:58.55#ibcon#flushed, iclass 27, count 0 2006.238.08:17:58.55#ibcon#about to write, iclass 27, count 0 2006.238.08:17:58.55#ibcon#wrote, iclass 27, count 0 2006.238.08:17:58.55#ibcon#about to read 3, iclass 27, count 0 2006.238.08:17:58.58#ibcon#read 3, iclass 27, count 0 2006.238.08:17:58.58#ibcon#about to read 4, iclass 27, count 0 2006.238.08:17:58.58#ibcon#read 4, iclass 27, count 0 2006.238.08:17:58.58#ibcon#about to read 5, iclass 27, count 0 2006.238.08:17:58.58#ibcon#read 5, iclass 27, count 0 2006.238.08:17:58.58#ibcon#about to read 6, iclass 27, count 0 2006.238.08:17:58.58#ibcon#read 6, iclass 27, count 0 2006.238.08:17:58.58#ibcon#end of sib2, iclass 27, count 0 2006.238.08:17:58.58#ibcon#*after write, iclass 27, count 0 2006.238.08:17:58.58#ibcon#*before return 0, iclass 27, count 0 2006.238.08:17:58.58#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:17:58.58#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:17:58.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.08:17:58.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.08:17:58.58$vc4f8/valo=3,672.99 2006.238.08:17:58.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.238.08:17:58.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.238.08:17:58.58#ibcon#ireg 17 cls_cnt 0 2006.238.08:17:58.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:17:58.58#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:17:58.58#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:17:58.58#ibcon#enter wrdev, iclass 29, count 0 2006.238.08:17:58.58#ibcon#first serial, iclass 29, count 0 2006.238.08:17:58.58#ibcon#enter sib2, iclass 29, count 0 2006.238.08:17:58.58#ibcon#flushed, iclass 29, count 0 2006.238.08:17:58.58#ibcon#about to write, iclass 29, count 0 2006.238.08:17:58.58#ibcon#wrote, iclass 29, count 0 2006.238.08:17:58.58#ibcon#about to read 3, iclass 29, count 0 2006.238.08:17:58.60#ibcon#read 3, iclass 29, count 0 2006.238.08:17:58.60#ibcon#about to read 4, iclass 29, count 0 2006.238.08:17:58.60#ibcon#read 4, iclass 29, count 0 2006.238.08:17:58.60#ibcon#about to read 5, iclass 29, count 0 2006.238.08:17:58.60#ibcon#read 5, iclass 29, count 0 2006.238.08:17:58.60#ibcon#about to read 6, iclass 29, count 0 2006.238.08:17:58.60#ibcon#read 6, iclass 29, count 0 2006.238.08:17:58.60#ibcon#end of sib2, iclass 29, count 0 2006.238.08:17:58.60#ibcon#*mode == 0, iclass 29, count 0 2006.238.08:17:58.60#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.08:17:58.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:17:58.60#ibcon#*before write, iclass 29, count 0 2006.238.08:17:58.60#ibcon#enter sib2, iclass 29, count 0 2006.238.08:17:58.60#ibcon#flushed, iclass 29, count 0 2006.238.08:17:58.60#ibcon#about to write, iclass 29, count 0 2006.238.08:17:58.60#ibcon#wrote, iclass 29, count 0 2006.238.08:17:58.60#ibcon#about to read 3, iclass 29, count 0 2006.238.08:17:58.64#ibcon#read 3, iclass 29, count 0 2006.238.08:17:58.64#ibcon#about to read 4, iclass 29, count 0 2006.238.08:17:58.64#ibcon#read 4, iclass 29, count 0 2006.238.08:17:58.64#ibcon#about to read 5, iclass 29, count 0 2006.238.08:17:58.64#ibcon#read 5, iclass 29, count 0 2006.238.08:17:58.64#ibcon#about to read 6, iclass 29, count 0 2006.238.08:17:58.64#ibcon#read 6, iclass 29, count 0 2006.238.08:17:58.64#ibcon#end of sib2, iclass 29, count 0 2006.238.08:17:58.64#ibcon#*after write, iclass 29, count 0 2006.238.08:17:58.64#ibcon#*before return 0, iclass 29, count 0 2006.238.08:17:58.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:17:58.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:17:58.64#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.08:17:58.64#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.08:17:58.64$vc4f8/va=3,7 2006.238.08:17:58.64#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.238.08:17:58.64#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.238.08:17:58.64#ibcon#ireg 11 cls_cnt 2 2006.238.08:17:58.64#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:17:58.70#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:17:58.70#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:17:58.70#ibcon#enter wrdev, iclass 31, count 2 2006.238.08:17:58.70#ibcon#first serial, iclass 31, count 2 2006.238.08:17:58.70#ibcon#enter sib2, iclass 31, count 2 2006.238.08:17:58.70#ibcon#flushed, iclass 31, count 2 2006.238.08:17:58.70#ibcon#about to write, iclass 31, count 2 2006.238.08:17:58.70#ibcon#wrote, iclass 31, count 2 2006.238.08:17:58.70#ibcon#about to read 3, iclass 31, count 2 2006.238.08:17:58.72#ibcon#read 3, iclass 31, count 2 2006.238.08:17:58.72#ibcon#about to read 4, iclass 31, count 2 2006.238.08:17:58.72#ibcon#read 4, iclass 31, count 2 2006.238.08:17:58.72#ibcon#about to read 5, iclass 31, count 2 2006.238.08:17:58.72#ibcon#read 5, iclass 31, count 2 2006.238.08:17:58.72#ibcon#about to read 6, iclass 31, count 2 2006.238.08:17:58.72#ibcon#read 6, iclass 31, count 2 2006.238.08:17:58.72#ibcon#end of sib2, iclass 31, count 2 2006.238.08:17:58.72#ibcon#*mode == 0, iclass 31, count 2 2006.238.08:17:58.72#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.238.08:17:58.72#ibcon#[25=AT03-07\r\n] 2006.238.08:17:58.72#ibcon#*before write, iclass 31, count 2 2006.238.08:17:58.72#ibcon#enter sib2, iclass 31, count 2 2006.238.08:17:58.72#ibcon#flushed, iclass 31, count 2 2006.238.08:17:58.72#ibcon#about to write, iclass 31, count 2 2006.238.08:17:58.72#ibcon#wrote, iclass 31, count 2 2006.238.08:17:58.72#ibcon#about to read 3, iclass 31, count 2 2006.238.08:17:58.75#ibcon#read 3, iclass 31, count 2 2006.238.08:17:58.75#ibcon#about to read 4, iclass 31, count 2 2006.238.08:17:58.75#ibcon#read 4, iclass 31, count 2 2006.238.08:17:58.75#ibcon#about to read 5, iclass 31, count 2 2006.238.08:17:58.75#ibcon#read 5, iclass 31, count 2 2006.238.08:17:58.75#ibcon#about to read 6, iclass 31, count 2 2006.238.08:17:58.75#ibcon#read 6, iclass 31, count 2 2006.238.08:17:58.75#ibcon#end of sib2, iclass 31, count 2 2006.238.08:17:58.75#ibcon#*after write, iclass 31, count 2 2006.238.08:17:58.75#ibcon#*before return 0, iclass 31, count 2 2006.238.08:17:58.75#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:17:58.75#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:17:58.75#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.238.08:17:58.75#ibcon#ireg 7 cls_cnt 0 2006.238.08:17:58.75#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:17:58.87#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:17:58.87#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:17:58.87#ibcon#enter wrdev, iclass 31, count 0 2006.238.08:17:58.87#ibcon#first serial, iclass 31, count 0 2006.238.08:17:58.87#ibcon#enter sib2, iclass 31, count 0 2006.238.08:17:58.87#ibcon#flushed, iclass 31, count 0 2006.238.08:17:58.87#ibcon#about to write, iclass 31, count 0 2006.238.08:17:58.87#ibcon#wrote, iclass 31, count 0 2006.238.08:17:58.87#ibcon#about to read 3, iclass 31, count 0 2006.238.08:17:58.89#ibcon#read 3, iclass 31, count 0 2006.238.08:17:58.89#ibcon#about to read 4, iclass 31, count 0 2006.238.08:17:58.89#ibcon#read 4, iclass 31, count 0 2006.238.08:17:58.89#ibcon#about to read 5, iclass 31, count 0 2006.238.08:17:58.89#ibcon#read 5, iclass 31, count 0 2006.238.08:17:58.89#ibcon#about to read 6, iclass 31, count 0 2006.238.08:17:58.89#ibcon#read 6, iclass 31, count 0 2006.238.08:17:58.89#ibcon#end of sib2, iclass 31, count 0 2006.238.08:17:58.89#ibcon#*mode == 0, iclass 31, count 0 2006.238.08:17:58.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.08:17:58.89#ibcon#[25=USB\r\n] 2006.238.08:17:58.89#ibcon#*before write, iclass 31, count 0 2006.238.08:17:58.89#ibcon#enter sib2, iclass 31, count 0 2006.238.08:17:58.89#ibcon#flushed, iclass 31, count 0 2006.238.08:17:58.89#ibcon#about to write, iclass 31, count 0 2006.238.08:17:58.89#ibcon#wrote, iclass 31, count 0 2006.238.08:17:58.89#ibcon#about to read 3, iclass 31, count 0 2006.238.08:17:58.92#ibcon#read 3, iclass 31, count 0 2006.238.08:17:58.92#ibcon#about to read 4, iclass 31, count 0 2006.238.08:17:58.92#ibcon#read 4, iclass 31, count 0 2006.238.08:17:58.92#ibcon#about to read 5, iclass 31, count 0 2006.238.08:17:58.92#ibcon#read 5, iclass 31, count 0 2006.238.08:17:58.92#ibcon#about to read 6, iclass 31, count 0 2006.238.08:17:58.92#ibcon#read 6, iclass 31, count 0 2006.238.08:17:58.92#ibcon#end of sib2, iclass 31, count 0 2006.238.08:17:58.92#ibcon#*after write, iclass 31, count 0 2006.238.08:17:58.92#ibcon#*before return 0, iclass 31, count 0 2006.238.08:17:58.92#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:17:58.92#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:17:58.92#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.08:17:58.92#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.08:17:58.92$vc4f8/valo=4,832.99 2006.238.08:17:58.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.08:17:58.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.08:17:58.92#ibcon#ireg 17 cls_cnt 0 2006.238.08:17:58.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:17:58.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:17:58.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:17:58.92#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:17:58.92#ibcon#first serial, iclass 33, count 0 2006.238.08:17:58.92#ibcon#enter sib2, iclass 33, count 0 2006.238.08:17:58.92#ibcon#flushed, iclass 33, count 0 2006.238.08:17:58.92#ibcon#about to write, iclass 33, count 0 2006.238.08:17:58.92#ibcon#wrote, iclass 33, count 0 2006.238.08:17:58.92#ibcon#about to read 3, iclass 33, count 0 2006.238.08:17:58.94#ibcon#read 3, iclass 33, count 0 2006.238.08:17:58.94#ibcon#about to read 4, iclass 33, count 0 2006.238.08:17:58.94#ibcon#read 4, iclass 33, count 0 2006.238.08:17:58.94#ibcon#about to read 5, iclass 33, count 0 2006.238.08:17:58.94#ibcon#read 5, iclass 33, count 0 2006.238.08:17:58.94#ibcon#about to read 6, iclass 33, count 0 2006.238.08:17:58.94#ibcon#read 6, iclass 33, count 0 2006.238.08:17:58.94#ibcon#end of sib2, iclass 33, count 0 2006.238.08:17:58.94#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:17:58.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:17:58.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:17:58.94#ibcon#*before write, iclass 33, count 0 2006.238.08:17:58.94#ibcon#enter sib2, iclass 33, count 0 2006.238.08:17:58.94#ibcon#flushed, iclass 33, count 0 2006.238.08:17:58.94#ibcon#about to write, iclass 33, count 0 2006.238.08:17:58.94#ibcon#wrote, iclass 33, count 0 2006.238.08:17:58.94#ibcon#about to read 3, iclass 33, count 0 2006.238.08:17:58.98#ibcon#read 3, iclass 33, count 0 2006.238.08:17:58.98#ibcon#about to read 4, iclass 33, count 0 2006.238.08:17:58.98#ibcon#read 4, iclass 33, count 0 2006.238.08:17:58.98#ibcon#about to read 5, iclass 33, count 0 2006.238.08:17:58.98#ibcon#read 5, iclass 33, count 0 2006.238.08:17:58.98#ibcon#about to read 6, iclass 33, count 0 2006.238.08:17:58.98#ibcon#read 6, iclass 33, count 0 2006.238.08:17:58.98#ibcon#end of sib2, iclass 33, count 0 2006.238.08:17:58.98#ibcon#*after write, iclass 33, count 0 2006.238.08:17:58.98#ibcon#*before return 0, iclass 33, count 0 2006.238.08:17:58.98#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:17:58.98#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:17:58.98#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:17:58.98#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:17:58.98$vc4f8/va=4,7 2006.238.08:17:58.98#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.238.08:17:58.98#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.238.08:17:58.98#ibcon#ireg 11 cls_cnt 2 2006.238.08:17:58.98#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:17:59.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:17:59.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:17:59.04#ibcon#enter wrdev, iclass 35, count 2 2006.238.08:17:59.04#ibcon#first serial, iclass 35, count 2 2006.238.08:17:59.04#ibcon#enter sib2, iclass 35, count 2 2006.238.08:17:59.04#ibcon#flushed, iclass 35, count 2 2006.238.08:17:59.04#ibcon#about to write, iclass 35, count 2 2006.238.08:17:59.04#ibcon#wrote, iclass 35, count 2 2006.238.08:17:59.04#ibcon#about to read 3, iclass 35, count 2 2006.238.08:17:59.06#ibcon#read 3, iclass 35, count 2 2006.238.08:17:59.06#ibcon#about to read 4, iclass 35, count 2 2006.238.08:17:59.06#ibcon#read 4, iclass 35, count 2 2006.238.08:17:59.06#ibcon#about to read 5, iclass 35, count 2 2006.238.08:17:59.06#ibcon#read 5, iclass 35, count 2 2006.238.08:17:59.06#ibcon#about to read 6, iclass 35, count 2 2006.238.08:17:59.06#ibcon#read 6, iclass 35, count 2 2006.238.08:17:59.06#ibcon#end of sib2, iclass 35, count 2 2006.238.08:17:59.06#ibcon#*mode == 0, iclass 35, count 2 2006.238.08:17:59.06#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.238.08:17:59.06#ibcon#[25=AT04-07\r\n] 2006.238.08:17:59.06#ibcon#*before write, iclass 35, count 2 2006.238.08:17:59.06#ibcon#enter sib2, iclass 35, count 2 2006.238.08:17:59.06#ibcon#flushed, iclass 35, count 2 2006.238.08:17:59.06#ibcon#about to write, iclass 35, count 2 2006.238.08:17:59.06#ibcon#wrote, iclass 35, count 2 2006.238.08:17:59.06#ibcon#about to read 3, iclass 35, count 2 2006.238.08:17:59.09#ibcon#read 3, iclass 35, count 2 2006.238.08:17:59.09#ibcon#about to read 4, iclass 35, count 2 2006.238.08:17:59.09#ibcon#read 4, iclass 35, count 2 2006.238.08:17:59.09#ibcon#about to read 5, iclass 35, count 2 2006.238.08:17:59.09#ibcon#read 5, iclass 35, count 2 2006.238.08:17:59.09#ibcon#about to read 6, iclass 35, count 2 2006.238.08:17:59.09#ibcon#read 6, iclass 35, count 2 2006.238.08:17:59.09#ibcon#end of sib2, iclass 35, count 2 2006.238.08:17:59.09#ibcon#*after write, iclass 35, count 2 2006.238.08:17:59.09#ibcon#*before return 0, iclass 35, count 2 2006.238.08:17:59.09#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:17:59.09#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:17:59.09#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.238.08:17:59.09#ibcon#ireg 7 cls_cnt 0 2006.238.08:17:59.09#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:17:59.21#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:17:59.21#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:17:59.21#ibcon#enter wrdev, iclass 35, count 0 2006.238.08:17:59.21#ibcon#first serial, iclass 35, count 0 2006.238.08:17:59.21#ibcon#enter sib2, iclass 35, count 0 2006.238.08:17:59.21#ibcon#flushed, iclass 35, count 0 2006.238.08:17:59.21#ibcon#about to write, iclass 35, count 0 2006.238.08:17:59.21#ibcon#wrote, iclass 35, count 0 2006.238.08:17:59.21#ibcon#about to read 3, iclass 35, count 0 2006.238.08:17:59.23#ibcon#read 3, iclass 35, count 0 2006.238.08:17:59.23#ibcon#about to read 4, iclass 35, count 0 2006.238.08:17:59.23#ibcon#read 4, iclass 35, count 0 2006.238.08:17:59.23#ibcon#about to read 5, iclass 35, count 0 2006.238.08:17:59.23#ibcon#read 5, iclass 35, count 0 2006.238.08:17:59.23#ibcon#about to read 6, iclass 35, count 0 2006.238.08:17:59.23#ibcon#read 6, iclass 35, count 0 2006.238.08:17:59.23#ibcon#end of sib2, iclass 35, count 0 2006.238.08:17:59.23#ibcon#*mode == 0, iclass 35, count 0 2006.238.08:17:59.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.08:17:59.23#ibcon#[25=USB\r\n] 2006.238.08:17:59.23#ibcon#*before write, iclass 35, count 0 2006.238.08:17:59.23#ibcon#enter sib2, iclass 35, count 0 2006.238.08:17:59.23#ibcon#flushed, iclass 35, count 0 2006.238.08:17:59.23#ibcon#about to write, iclass 35, count 0 2006.238.08:17:59.23#ibcon#wrote, iclass 35, count 0 2006.238.08:17:59.23#ibcon#about to read 3, iclass 35, count 0 2006.238.08:17:59.26#ibcon#read 3, iclass 35, count 0 2006.238.08:17:59.26#ibcon#about to read 4, iclass 35, count 0 2006.238.08:17:59.26#ibcon#read 4, iclass 35, count 0 2006.238.08:17:59.26#ibcon#about to read 5, iclass 35, count 0 2006.238.08:17:59.26#ibcon#read 5, iclass 35, count 0 2006.238.08:17:59.26#ibcon#about to read 6, iclass 35, count 0 2006.238.08:17:59.26#ibcon#read 6, iclass 35, count 0 2006.238.08:17:59.26#ibcon#end of sib2, iclass 35, count 0 2006.238.08:17:59.26#ibcon#*after write, iclass 35, count 0 2006.238.08:17:59.26#ibcon#*before return 0, iclass 35, count 0 2006.238.08:17:59.26#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:17:59.26#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:17:59.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.08:17:59.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.08:17:59.26$vc4f8/valo=5,652.99 2006.238.08:17:59.26#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.08:17:59.26#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.08:17:59.26#ibcon#ireg 17 cls_cnt 0 2006.238.08:17:59.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:17:59.26#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:17:59.26#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:17:59.26#ibcon#enter wrdev, iclass 37, count 0 2006.238.08:17:59.26#ibcon#first serial, iclass 37, count 0 2006.238.08:17:59.26#ibcon#enter sib2, iclass 37, count 0 2006.238.08:17:59.26#ibcon#flushed, iclass 37, count 0 2006.238.08:17:59.26#ibcon#about to write, iclass 37, count 0 2006.238.08:17:59.26#ibcon#wrote, iclass 37, count 0 2006.238.08:17:59.26#ibcon#about to read 3, iclass 37, count 0 2006.238.08:17:59.28#ibcon#read 3, iclass 37, count 0 2006.238.08:17:59.28#ibcon#about to read 4, iclass 37, count 0 2006.238.08:17:59.28#ibcon#read 4, iclass 37, count 0 2006.238.08:17:59.28#ibcon#about to read 5, iclass 37, count 0 2006.238.08:17:59.28#ibcon#read 5, iclass 37, count 0 2006.238.08:17:59.28#ibcon#about to read 6, iclass 37, count 0 2006.238.08:17:59.28#ibcon#read 6, iclass 37, count 0 2006.238.08:17:59.28#ibcon#end of sib2, iclass 37, count 0 2006.238.08:17:59.28#ibcon#*mode == 0, iclass 37, count 0 2006.238.08:17:59.28#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.08:17:59.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:17:59.28#ibcon#*before write, iclass 37, count 0 2006.238.08:17:59.28#ibcon#enter sib2, iclass 37, count 0 2006.238.08:17:59.28#ibcon#flushed, iclass 37, count 0 2006.238.08:17:59.28#ibcon#about to write, iclass 37, count 0 2006.238.08:17:59.28#ibcon#wrote, iclass 37, count 0 2006.238.08:17:59.28#ibcon#about to read 3, iclass 37, count 0 2006.238.08:17:59.32#ibcon#read 3, iclass 37, count 0 2006.238.08:17:59.32#ibcon#about to read 4, iclass 37, count 0 2006.238.08:17:59.32#ibcon#read 4, iclass 37, count 0 2006.238.08:17:59.32#ibcon#about to read 5, iclass 37, count 0 2006.238.08:17:59.32#ibcon#read 5, iclass 37, count 0 2006.238.08:17:59.32#ibcon#about to read 6, iclass 37, count 0 2006.238.08:17:59.32#ibcon#read 6, iclass 37, count 0 2006.238.08:17:59.32#ibcon#end of sib2, iclass 37, count 0 2006.238.08:17:59.32#ibcon#*after write, iclass 37, count 0 2006.238.08:17:59.32#ibcon#*before return 0, iclass 37, count 0 2006.238.08:17:59.32#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:17:59.32#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:17:59.32#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.08:17:59.32#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.08:17:59.32$vc4f8/va=5,8 2006.238.08:17:59.32#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.238.08:17:59.32#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.238.08:17:59.32#ibcon#ireg 11 cls_cnt 2 2006.238.08:17:59.32#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:17:59.38#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:17:59.38#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:17:59.38#ibcon#enter wrdev, iclass 39, count 2 2006.238.08:17:59.38#ibcon#first serial, iclass 39, count 2 2006.238.08:17:59.38#ibcon#enter sib2, iclass 39, count 2 2006.238.08:17:59.38#ibcon#flushed, iclass 39, count 2 2006.238.08:17:59.38#ibcon#about to write, iclass 39, count 2 2006.238.08:17:59.38#ibcon#wrote, iclass 39, count 2 2006.238.08:17:59.38#ibcon#about to read 3, iclass 39, count 2 2006.238.08:17:59.40#ibcon#read 3, iclass 39, count 2 2006.238.08:17:59.40#ibcon#about to read 4, iclass 39, count 2 2006.238.08:17:59.40#ibcon#read 4, iclass 39, count 2 2006.238.08:17:59.40#ibcon#about to read 5, iclass 39, count 2 2006.238.08:17:59.40#ibcon#read 5, iclass 39, count 2 2006.238.08:17:59.40#ibcon#about to read 6, iclass 39, count 2 2006.238.08:17:59.40#ibcon#read 6, iclass 39, count 2 2006.238.08:17:59.40#ibcon#end of sib2, iclass 39, count 2 2006.238.08:17:59.40#ibcon#*mode == 0, iclass 39, count 2 2006.238.08:17:59.40#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.238.08:17:59.40#ibcon#[25=AT05-08\r\n] 2006.238.08:17:59.40#ibcon#*before write, iclass 39, count 2 2006.238.08:17:59.40#ibcon#enter sib2, iclass 39, count 2 2006.238.08:17:59.40#ibcon#flushed, iclass 39, count 2 2006.238.08:17:59.40#ibcon#about to write, iclass 39, count 2 2006.238.08:17:59.40#ibcon#wrote, iclass 39, count 2 2006.238.08:17:59.40#ibcon#about to read 3, iclass 39, count 2 2006.238.08:17:59.43#ibcon#read 3, iclass 39, count 2 2006.238.08:17:59.43#ibcon#about to read 4, iclass 39, count 2 2006.238.08:17:59.43#ibcon#read 4, iclass 39, count 2 2006.238.08:17:59.43#ibcon#about to read 5, iclass 39, count 2 2006.238.08:17:59.43#ibcon#read 5, iclass 39, count 2 2006.238.08:17:59.43#ibcon#about to read 6, iclass 39, count 2 2006.238.08:17:59.43#ibcon#read 6, iclass 39, count 2 2006.238.08:17:59.43#ibcon#end of sib2, iclass 39, count 2 2006.238.08:17:59.43#ibcon#*after write, iclass 39, count 2 2006.238.08:17:59.43#ibcon#*before return 0, iclass 39, count 2 2006.238.08:17:59.43#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:17:59.43#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:17:59.43#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.238.08:17:59.43#ibcon#ireg 7 cls_cnt 0 2006.238.08:17:59.43#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:17:59.55#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:17:59.55#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:17:59.55#ibcon#enter wrdev, iclass 39, count 0 2006.238.08:17:59.55#ibcon#first serial, iclass 39, count 0 2006.238.08:17:59.55#ibcon#enter sib2, iclass 39, count 0 2006.238.08:17:59.55#ibcon#flushed, iclass 39, count 0 2006.238.08:17:59.55#ibcon#about to write, iclass 39, count 0 2006.238.08:17:59.55#ibcon#wrote, iclass 39, count 0 2006.238.08:17:59.55#ibcon#about to read 3, iclass 39, count 0 2006.238.08:17:59.57#ibcon#read 3, iclass 39, count 0 2006.238.08:17:59.57#ibcon#about to read 4, iclass 39, count 0 2006.238.08:17:59.57#ibcon#read 4, iclass 39, count 0 2006.238.08:17:59.57#ibcon#about to read 5, iclass 39, count 0 2006.238.08:17:59.57#ibcon#read 5, iclass 39, count 0 2006.238.08:17:59.57#ibcon#about to read 6, iclass 39, count 0 2006.238.08:17:59.57#ibcon#read 6, iclass 39, count 0 2006.238.08:17:59.57#ibcon#end of sib2, iclass 39, count 0 2006.238.08:17:59.57#ibcon#*mode == 0, iclass 39, count 0 2006.238.08:17:59.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.08:17:59.57#ibcon#[25=USB\r\n] 2006.238.08:17:59.57#ibcon#*before write, iclass 39, count 0 2006.238.08:17:59.57#ibcon#enter sib2, iclass 39, count 0 2006.238.08:17:59.57#ibcon#flushed, iclass 39, count 0 2006.238.08:17:59.57#ibcon#about to write, iclass 39, count 0 2006.238.08:17:59.57#ibcon#wrote, iclass 39, count 0 2006.238.08:17:59.57#ibcon#about to read 3, iclass 39, count 0 2006.238.08:17:59.60#ibcon#read 3, iclass 39, count 0 2006.238.08:17:59.60#ibcon#about to read 4, iclass 39, count 0 2006.238.08:17:59.60#ibcon#read 4, iclass 39, count 0 2006.238.08:17:59.60#ibcon#about to read 5, iclass 39, count 0 2006.238.08:17:59.60#ibcon#read 5, iclass 39, count 0 2006.238.08:17:59.60#ibcon#about to read 6, iclass 39, count 0 2006.238.08:17:59.60#ibcon#read 6, iclass 39, count 0 2006.238.08:17:59.60#ibcon#end of sib2, iclass 39, count 0 2006.238.08:17:59.60#ibcon#*after write, iclass 39, count 0 2006.238.08:17:59.60#ibcon#*before return 0, iclass 39, count 0 2006.238.08:17:59.60#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:17:59.60#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:17:59.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.08:17:59.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.08:17:59.60$vc4f8/valo=6,772.99 2006.238.08:17:59.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.08:17:59.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.08:17:59.60#ibcon#ireg 17 cls_cnt 0 2006.238.08:17:59.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:17:59.60#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:17:59.60#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:17:59.60#ibcon#enter wrdev, iclass 3, count 0 2006.238.08:17:59.60#ibcon#first serial, iclass 3, count 0 2006.238.08:17:59.60#ibcon#enter sib2, iclass 3, count 0 2006.238.08:17:59.60#ibcon#flushed, iclass 3, count 0 2006.238.08:17:59.60#ibcon#about to write, iclass 3, count 0 2006.238.08:17:59.60#ibcon#wrote, iclass 3, count 0 2006.238.08:17:59.60#ibcon#about to read 3, iclass 3, count 0 2006.238.08:17:59.62#ibcon#read 3, iclass 3, count 0 2006.238.08:17:59.62#ibcon#about to read 4, iclass 3, count 0 2006.238.08:17:59.62#ibcon#read 4, iclass 3, count 0 2006.238.08:17:59.62#ibcon#about to read 5, iclass 3, count 0 2006.238.08:17:59.62#ibcon#read 5, iclass 3, count 0 2006.238.08:17:59.62#ibcon#about to read 6, iclass 3, count 0 2006.238.08:17:59.62#ibcon#read 6, iclass 3, count 0 2006.238.08:17:59.62#ibcon#end of sib2, iclass 3, count 0 2006.238.08:17:59.62#ibcon#*mode == 0, iclass 3, count 0 2006.238.08:17:59.62#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.08:17:59.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:17:59.62#ibcon#*before write, iclass 3, count 0 2006.238.08:17:59.62#ibcon#enter sib2, iclass 3, count 0 2006.238.08:17:59.62#ibcon#flushed, iclass 3, count 0 2006.238.08:17:59.62#ibcon#about to write, iclass 3, count 0 2006.238.08:17:59.62#ibcon#wrote, iclass 3, count 0 2006.238.08:17:59.62#ibcon#about to read 3, iclass 3, count 0 2006.238.08:17:59.67#ibcon#read 3, iclass 3, count 0 2006.238.08:17:59.67#ibcon#about to read 4, iclass 3, count 0 2006.238.08:17:59.67#ibcon#read 4, iclass 3, count 0 2006.238.08:17:59.67#ibcon#about to read 5, iclass 3, count 0 2006.238.08:17:59.67#ibcon#read 5, iclass 3, count 0 2006.238.08:17:59.67#ibcon#about to read 6, iclass 3, count 0 2006.238.08:17:59.67#ibcon#read 6, iclass 3, count 0 2006.238.08:17:59.67#ibcon#end of sib2, iclass 3, count 0 2006.238.08:17:59.67#ibcon#*after write, iclass 3, count 0 2006.238.08:17:59.67#ibcon#*before return 0, iclass 3, count 0 2006.238.08:17:59.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:17:59.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:17:59.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.08:17:59.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.08:17:59.67$vc4f8/va=6,7 2006.238.08:17:59.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.238.08:17:59.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.238.08:17:59.67#ibcon#ireg 11 cls_cnt 2 2006.238.08:17:59.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:17:59.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:17:59.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:17:59.71#ibcon#enter wrdev, iclass 5, count 2 2006.238.08:17:59.71#ibcon#first serial, iclass 5, count 2 2006.238.08:17:59.71#ibcon#enter sib2, iclass 5, count 2 2006.238.08:17:59.71#ibcon#flushed, iclass 5, count 2 2006.238.08:17:59.71#ibcon#about to write, iclass 5, count 2 2006.238.08:17:59.71#ibcon#wrote, iclass 5, count 2 2006.238.08:17:59.71#ibcon#about to read 3, iclass 5, count 2 2006.238.08:17:59.73#ibcon#read 3, iclass 5, count 2 2006.238.08:17:59.73#ibcon#about to read 4, iclass 5, count 2 2006.238.08:17:59.73#ibcon#read 4, iclass 5, count 2 2006.238.08:17:59.73#ibcon#about to read 5, iclass 5, count 2 2006.238.08:17:59.73#ibcon#read 5, iclass 5, count 2 2006.238.08:17:59.73#ibcon#about to read 6, iclass 5, count 2 2006.238.08:17:59.73#ibcon#read 6, iclass 5, count 2 2006.238.08:17:59.73#ibcon#end of sib2, iclass 5, count 2 2006.238.08:17:59.73#ibcon#*mode == 0, iclass 5, count 2 2006.238.08:17:59.73#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.238.08:17:59.73#ibcon#[25=AT06-07\r\n] 2006.238.08:17:59.73#ibcon#*before write, iclass 5, count 2 2006.238.08:17:59.73#ibcon#enter sib2, iclass 5, count 2 2006.238.08:17:59.73#ibcon#flushed, iclass 5, count 2 2006.238.08:17:59.73#ibcon#about to write, iclass 5, count 2 2006.238.08:17:59.73#ibcon#wrote, iclass 5, count 2 2006.238.08:17:59.73#ibcon#about to read 3, iclass 5, count 2 2006.238.08:17:59.76#ibcon#read 3, iclass 5, count 2 2006.238.08:17:59.76#ibcon#about to read 4, iclass 5, count 2 2006.238.08:17:59.76#ibcon#read 4, iclass 5, count 2 2006.238.08:17:59.76#ibcon#about to read 5, iclass 5, count 2 2006.238.08:17:59.76#ibcon#read 5, iclass 5, count 2 2006.238.08:17:59.76#ibcon#about to read 6, iclass 5, count 2 2006.238.08:17:59.76#ibcon#read 6, iclass 5, count 2 2006.238.08:17:59.76#ibcon#end of sib2, iclass 5, count 2 2006.238.08:17:59.76#ibcon#*after write, iclass 5, count 2 2006.238.08:17:59.76#ibcon#*before return 0, iclass 5, count 2 2006.238.08:17:59.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:17:59.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.238.08:17:59.76#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.238.08:17:59.76#ibcon#ireg 7 cls_cnt 0 2006.238.08:17:59.76#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:17:59.88#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:17:59.88#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:17:59.88#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:17:59.88#ibcon#first serial, iclass 5, count 0 2006.238.08:17:59.88#ibcon#enter sib2, iclass 5, count 0 2006.238.08:17:59.88#ibcon#flushed, iclass 5, count 0 2006.238.08:17:59.88#ibcon#about to write, iclass 5, count 0 2006.238.08:17:59.88#ibcon#wrote, iclass 5, count 0 2006.238.08:17:59.88#ibcon#about to read 3, iclass 5, count 0 2006.238.08:17:59.90#ibcon#read 3, iclass 5, count 0 2006.238.08:17:59.90#ibcon#about to read 4, iclass 5, count 0 2006.238.08:17:59.90#ibcon#read 4, iclass 5, count 0 2006.238.08:17:59.90#ibcon#about to read 5, iclass 5, count 0 2006.238.08:17:59.90#ibcon#read 5, iclass 5, count 0 2006.238.08:17:59.90#ibcon#about to read 6, iclass 5, count 0 2006.238.08:17:59.90#ibcon#read 6, iclass 5, count 0 2006.238.08:17:59.90#ibcon#end of sib2, iclass 5, count 0 2006.238.08:17:59.90#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:17:59.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:17:59.90#ibcon#[25=USB\r\n] 2006.238.08:17:59.90#ibcon#*before write, iclass 5, count 0 2006.238.08:17:59.90#ibcon#enter sib2, iclass 5, count 0 2006.238.08:17:59.90#ibcon#flushed, iclass 5, count 0 2006.238.08:17:59.90#ibcon#about to write, iclass 5, count 0 2006.238.08:17:59.90#ibcon#wrote, iclass 5, count 0 2006.238.08:17:59.90#ibcon#about to read 3, iclass 5, count 0 2006.238.08:17:59.93#ibcon#read 3, iclass 5, count 0 2006.238.08:17:59.93#ibcon#about to read 4, iclass 5, count 0 2006.238.08:17:59.93#ibcon#read 4, iclass 5, count 0 2006.238.08:17:59.93#ibcon#about to read 5, iclass 5, count 0 2006.238.08:17:59.93#ibcon#read 5, iclass 5, count 0 2006.238.08:17:59.93#ibcon#about to read 6, iclass 5, count 0 2006.238.08:17:59.93#ibcon#read 6, iclass 5, count 0 2006.238.08:17:59.93#ibcon#end of sib2, iclass 5, count 0 2006.238.08:17:59.93#ibcon#*after write, iclass 5, count 0 2006.238.08:17:59.93#ibcon#*before return 0, iclass 5, count 0 2006.238.08:17:59.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:17:59.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.238.08:17:59.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:17:59.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:17:59.93$vc4f8/valo=7,832.99 2006.238.08:17:59.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.238.08:17:59.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.238.08:17:59.93#ibcon#ireg 17 cls_cnt 0 2006.238.08:17:59.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:17:59.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:17:59.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:17:59.93#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:17:59.93#ibcon#first serial, iclass 7, count 0 2006.238.08:17:59.93#ibcon#enter sib2, iclass 7, count 0 2006.238.08:17:59.93#ibcon#flushed, iclass 7, count 0 2006.238.08:17:59.93#ibcon#about to write, iclass 7, count 0 2006.238.08:17:59.93#ibcon#wrote, iclass 7, count 0 2006.238.08:17:59.93#ibcon#about to read 3, iclass 7, count 0 2006.238.08:17:59.95#ibcon#read 3, iclass 7, count 0 2006.238.08:17:59.95#ibcon#about to read 4, iclass 7, count 0 2006.238.08:17:59.95#ibcon#read 4, iclass 7, count 0 2006.238.08:17:59.95#ibcon#about to read 5, iclass 7, count 0 2006.238.08:17:59.95#ibcon#read 5, iclass 7, count 0 2006.238.08:17:59.95#ibcon#about to read 6, iclass 7, count 0 2006.238.08:17:59.95#ibcon#read 6, iclass 7, count 0 2006.238.08:17:59.95#ibcon#end of sib2, iclass 7, count 0 2006.238.08:17:59.95#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:17:59.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:17:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:17:59.95#ibcon#*before write, iclass 7, count 0 2006.238.08:17:59.95#ibcon#enter sib2, iclass 7, count 0 2006.238.08:17:59.95#ibcon#flushed, iclass 7, count 0 2006.238.08:17:59.95#ibcon#about to write, iclass 7, count 0 2006.238.08:17:59.95#ibcon#wrote, iclass 7, count 0 2006.238.08:17:59.95#ibcon#about to read 3, iclass 7, count 0 2006.238.08:17:59.99#ibcon#read 3, iclass 7, count 0 2006.238.08:17:59.99#ibcon#about to read 4, iclass 7, count 0 2006.238.08:17:59.99#ibcon#read 4, iclass 7, count 0 2006.238.08:17:59.99#ibcon#about to read 5, iclass 7, count 0 2006.238.08:17:59.99#ibcon#read 5, iclass 7, count 0 2006.238.08:17:59.99#ibcon#about to read 6, iclass 7, count 0 2006.238.08:17:59.99#ibcon#read 6, iclass 7, count 0 2006.238.08:17:59.99#ibcon#end of sib2, iclass 7, count 0 2006.238.08:17:59.99#ibcon#*after write, iclass 7, count 0 2006.238.08:17:59.99#ibcon#*before return 0, iclass 7, count 0 2006.238.08:17:59.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:17:59.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.238.08:17:59.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:17:59.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:17:59.99$vc4f8/va=7,7 2006.238.08:17:59.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.238.08:17:59.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.238.08:17:59.99#ibcon#ireg 11 cls_cnt 2 2006.238.08:17:59.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:18:00.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:18:00.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:18:00.05#ibcon#enter wrdev, iclass 11, count 2 2006.238.08:18:00.05#ibcon#first serial, iclass 11, count 2 2006.238.08:18:00.05#ibcon#enter sib2, iclass 11, count 2 2006.238.08:18:00.05#ibcon#flushed, iclass 11, count 2 2006.238.08:18:00.05#ibcon#about to write, iclass 11, count 2 2006.238.08:18:00.05#ibcon#wrote, iclass 11, count 2 2006.238.08:18:00.05#ibcon#about to read 3, iclass 11, count 2 2006.238.08:18:00.07#ibcon#read 3, iclass 11, count 2 2006.238.08:18:00.07#ibcon#about to read 4, iclass 11, count 2 2006.238.08:18:00.07#ibcon#read 4, iclass 11, count 2 2006.238.08:18:00.07#ibcon#about to read 5, iclass 11, count 2 2006.238.08:18:00.07#ibcon#read 5, iclass 11, count 2 2006.238.08:18:00.07#ibcon#about to read 6, iclass 11, count 2 2006.238.08:18:00.07#ibcon#read 6, iclass 11, count 2 2006.238.08:18:00.07#ibcon#end of sib2, iclass 11, count 2 2006.238.08:18:00.07#ibcon#*mode == 0, iclass 11, count 2 2006.238.08:18:00.07#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.238.08:18:00.07#ibcon#[25=AT07-07\r\n] 2006.238.08:18:00.07#ibcon#*before write, iclass 11, count 2 2006.238.08:18:00.07#ibcon#enter sib2, iclass 11, count 2 2006.238.08:18:00.07#ibcon#flushed, iclass 11, count 2 2006.238.08:18:00.07#ibcon#about to write, iclass 11, count 2 2006.238.08:18:00.07#ibcon#wrote, iclass 11, count 2 2006.238.08:18:00.07#ibcon#about to read 3, iclass 11, count 2 2006.238.08:18:00.10#ibcon#read 3, iclass 11, count 2 2006.238.08:18:00.10#ibcon#about to read 4, iclass 11, count 2 2006.238.08:18:00.10#ibcon#read 4, iclass 11, count 2 2006.238.08:18:00.10#ibcon#about to read 5, iclass 11, count 2 2006.238.08:18:00.10#ibcon#read 5, iclass 11, count 2 2006.238.08:18:00.10#ibcon#about to read 6, iclass 11, count 2 2006.238.08:18:00.10#ibcon#read 6, iclass 11, count 2 2006.238.08:18:00.10#ibcon#end of sib2, iclass 11, count 2 2006.238.08:18:00.10#ibcon#*after write, iclass 11, count 2 2006.238.08:18:00.10#ibcon#*before return 0, iclass 11, count 2 2006.238.08:18:00.10#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:18:00.10#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.238.08:18:00.10#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.238.08:18:00.10#ibcon#ireg 7 cls_cnt 0 2006.238.08:18:00.10#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:18:00.22#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:18:00.22#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:18:00.22#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:18:00.22#ibcon#first serial, iclass 11, count 0 2006.238.08:18:00.22#ibcon#enter sib2, iclass 11, count 0 2006.238.08:18:00.22#ibcon#flushed, iclass 11, count 0 2006.238.08:18:00.22#ibcon#about to write, iclass 11, count 0 2006.238.08:18:00.22#ibcon#wrote, iclass 11, count 0 2006.238.08:18:00.22#ibcon#about to read 3, iclass 11, count 0 2006.238.08:18:00.24#ibcon#read 3, iclass 11, count 0 2006.238.08:18:00.24#ibcon#about to read 4, iclass 11, count 0 2006.238.08:18:00.24#ibcon#read 4, iclass 11, count 0 2006.238.08:18:00.24#ibcon#about to read 5, iclass 11, count 0 2006.238.08:18:00.24#ibcon#read 5, iclass 11, count 0 2006.238.08:18:00.24#ibcon#about to read 6, iclass 11, count 0 2006.238.08:18:00.24#ibcon#read 6, iclass 11, count 0 2006.238.08:18:00.24#ibcon#end of sib2, iclass 11, count 0 2006.238.08:18:00.24#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:18:00.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:18:00.24#ibcon#[25=USB\r\n] 2006.238.08:18:00.24#ibcon#*before write, iclass 11, count 0 2006.238.08:18:00.24#ibcon#enter sib2, iclass 11, count 0 2006.238.08:18:00.24#ibcon#flushed, iclass 11, count 0 2006.238.08:18:00.24#ibcon#about to write, iclass 11, count 0 2006.238.08:18:00.24#ibcon#wrote, iclass 11, count 0 2006.238.08:18:00.24#ibcon#about to read 3, iclass 11, count 0 2006.238.08:18:00.27#ibcon#read 3, iclass 11, count 0 2006.238.08:18:00.27#ibcon#about to read 4, iclass 11, count 0 2006.238.08:18:00.27#ibcon#read 4, iclass 11, count 0 2006.238.08:18:00.27#ibcon#about to read 5, iclass 11, count 0 2006.238.08:18:00.27#ibcon#read 5, iclass 11, count 0 2006.238.08:18:00.27#ibcon#about to read 6, iclass 11, count 0 2006.238.08:18:00.27#ibcon#read 6, iclass 11, count 0 2006.238.08:18:00.27#ibcon#end of sib2, iclass 11, count 0 2006.238.08:18:00.27#ibcon#*after write, iclass 11, count 0 2006.238.08:18:00.27#ibcon#*before return 0, iclass 11, count 0 2006.238.08:18:00.27#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:18:00.27#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.238.08:18:00.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:18:00.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:18:00.27$vc4f8/valo=8,852.99 2006.238.08:18:00.27#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.238.08:18:00.27#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.238.08:18:00.27#ibcon#ireg 17 cls_cnt 0 2006.238.08:18:00.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:18:00.27#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:18:00.27#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:18:00.27#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:18:00.27#ibcon#first serial, iclass 13, count 0 2006.238.08:18:00.27#ibcon#enter sib2, iclass 13, count 0 2006.238.08:18:00.27#ibcon#flushed, iclass 13, count 0 2006.238.08:18:00.27#ibcon#about to write, iclass 13, count 0 2006.238.08:18:00.27#ibcon#wrote, iclass 13, count 0 2006.238.08:18:00.27#ibcon#about to read 3, iclass 13, count 0 2006.238.08:18:00.29#ibcon#read 3, iclass 13, count 0 2006.238.08:18:00.29#ibcon#about to read 4, iclass 13, count 0 2006.238.08:18:00.29#ibcon#read 4, iclass 13, count 0 2006.238.08:18:00.29#ibcon#about to read 5, iclass 13, count 0 2006.238.08:18:00.29#ibcon#read 5, iclass 13, count 0 2006.238.08:18:00.29#ibcon#about to read 6, iclass 13, count 0 2006.238.08:18:00.29#ibcon#read 6, iclass 13, count 0 2006.238.08:18:00.29#ibcon#end of sib2, iclass 13, count 0 2006.238.08:18:00.29#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:18:00.29#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:18:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:18:00.29#ibcon#*before write, iclass 13, count 0 2006.238.08:18:00.29#ibcon#enter sib2, iclass 13, count 0 2006.238.08:18:00.29#ibcon#flushed, iclass 13, count 0 2006.238.08:18:00.29#ibcon#about to write, iclass 13, count 0 2006.238.08:18:00.29#ibcon#wrote, iclass 13, count 0 2006.238.08:18:00.29#ibcon#about to read 3, iclass 13, count 0 2006.238.08:18:00.33#ibcon#read 3, iclass 13, count 0 2006.238.08:18:00.33#ibcon#about to read 4, iclass 13, count 0 2006.238.08:18:00.33#ibcon#read 4, iclass 13, count 0 2006.238.08:18:00.33#ibcon#about to read 5, iclass 13, count 0 2006.238.08:18:00.33#ibcon#read 5, iclass 13, count 0 2006.238.08:18:00.33#ibcon#about to read 6, iclass 13, count 0 2006.238.08:18:00.33#ibcon#read 6, iclass 13, count 0 2006.238.08:18:00.33#ibcon#end of sib2, iclass 13, count 0 2006.238.08:18:00.33#ibcon#*after write, iclass 13, count 0 2006.238.08:18:00.33#ibcon#*before return 0, iclass 13, count 0 2006.238.08:18:00.33#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:18:00.33#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.238.08:18:00.33#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:18:00.33#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:18:00.33$vc4f8/va=8,7 2006.238.08:18:00.33#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.238.08:18:00.33#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.238.08:18:00.33#ibcon#ireg 11 cls_cnt 2 2006.238.08:18:00.33#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:18:00.39#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:18:00.39#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:18:00.39#ibcon#enter wrdev, iclass 15, count 2 2006.238.08:18:00.39#ibcon#first serial, iclass 15, count 2 2006.238.08:18:00.39#ibcon#enter sib2, iclass 15, count 2 2006.238.08:18:00.39#ibcon#flushed, iclass 15, count 2 2006.238.08:18:00.39#ibcon#about to write, iclass 15, count 2 2006.238.08:18:00.39#ibcon#wrote, iclass 15, count 2 2006.238.08:18:00.39#ibcon#about to read 3, iclass 15, count 2 2006.238.08:18:00.41#ibcon#read 3, iclass 15, count 2 2006.238.08:18:00.41#ibcon#about to read 4, iclass 15, count 2 2006.238.08:18:00.41#ibcon#read 4, iclass 15, count 2 2006.238.08:18:00.41#ibcon#about to read 5, iclass 15, count 2 2006.238.08:18:00.41#ibcon#read 5, iclass 15, count 2 2006.238.08:18:00.41#ibcon#about to read 6, iclass 15, count 2 2006.238.08:18:00.41#ibcon#read 6, iclass 15, count 2 2006.238.08:18:00.41#ibcon#end of sib2, iclass 15, count 2 2006.238.08:18:00.41#ibcon#*mode == 0, iclass 15, count 2 2006.238.08:18:00.41#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.238.08:18:00.41#ibcon#[25=AT08-07\r\n] 2006.238.08:18:00.41#ibcon#*before write, iclass 15, count 2 2006.238.08:18:00.41#ibcon#enter sib2, iclass 15, count 2 2006.238.08:18:00.41#ibcon#flushed, iclass 15, count 2 2006.238.08:18:00.41#ibcon#about to write, iclass 15, count 2 2006.238.08:18:00.41#ibcon#wrote, iclass 15, count 2 2006.238.08:18:00.41#ibcon#about to read 3, iclass 15, count 2 2006.238.08:18:00.44#ibcon#read 3, iclass 15, count 2 2006.238.08:18:00.44#ibcon#about to read 4, iclass 15, count 2 2006.238.08:18:00.44#ibcon#read 4, iclass 15, count 2 2006.238.08:18:00.44#ibcon#about to read 5, iclass 15, count 2 2006.238.08:18:00.44#ibcon#read 5, iclass 15, count 2 2006.238.08:18:00.44#ibcon#about to read 6, iclass 15, count 2 2006.238.08:18:00.44#ibcon#read 6, iclass 15, count 2 2006.238.08:18:00.44#ibcon#end of sib2, iclass 15, count 2 2006.238.08:18:00.44#ibcon#*after write, iclass 15, count 2 2006.238.08:18:00.44#ibcon#*before return 0, iclass 15, count 2 2006.238.08:18:00.44#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:18:00.44#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.238.08:18:00.44#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.238.08:18:00.44#ibcon#ireg 7 cls_cnt 0 2006.238.08:18:00.44#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:18:00.56#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:18:00.56#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:18:00.56#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:18:00.56#ibcon#first serial, iclass 15, count 0 2006.238.08:18:00.56#ibcon#enter sib2, iclass 15, count 0 2006.238.08:18:00.56#ibcon#flushed, iclass 15, count 0 2006.238.08:18:00.56#ibcon#about to write, iclass 15, count 0 2006.238.08:18:00.56#ibcon#wrote, iclass 15, count 0 2006.238.08:18:00.56#ibcon#about to read 3, iclass 15, count 0 2006.238.08:18:00.58#ibcon#read 3, iclass 15, count 0 2006.238.08:18:00.58#ibcon#about to read 4, iclass 15, count 0 2006.238.08:18:00.58#ibcon#read 4, iclass 15, count 0 2006.238.08:18:00.58#ibcon#about to read 5, iclass 15, count 0 2006.238.08:18:00.58#ibcon#read 5, iclass 15, count 0 2006.238.08:18:00.58#ibcon#about to read 6, iclass 15, count 0 2006.238.08:18:00.58#ibcon#read 6, iclass 15, count 0 2006.238.08:18:00.58#ibcon#end of sib2, iclass 15, count 0 2006.238.08:18:00.58#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:18:00.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:18:00.58#ibcon#[25=USB\r\n] 2006.238.08:18:00.58#ibcon#*before write, iclass 15, count 0 2006.238.08:18:00.58#ibcon#enter sib2, iclass 15, count 0 2006.238.08:18:00.58#ibcon#flushed, iclass 15, count 0 2006.238.08:18:00.58#ibcon#about to write, iclass 15, count 0 2006.238.08:18:00.58#ibcon#wrote, iclass 15, count 0 2006.238.08:18:00.58#ibcon#about to read 3, iclass 15, count 0 2006.238.08:18:00.61#ibcon#read 3, iclass 15, count 0 2006.238.08:18:00.61#ibcon#about to read 4, iclass 15, count 0 2006.238.08:18:00.61#ibcon#read 4, iclass 15, count 0 2006.238.08:18:00.61#ibcon#about to read 5, iclass 15, count 0 2006.238.08:18:00.61#ibcon#read 5, iclass 15, count 0 2006.238.08:18:00.61#ibcon#about to read 6, iclass 15, count 0 2006.238.08:18:00.61#ibcon#read 6, iclass 15, count 0 2006.238.08:18:00.61#ibcon#end of sib2, iclass 15, count 0 2006.238.08:18:00.61#ibcon#*after write, iclass 15, count 0 2006.238.08:18:00.61#ibcon#*before return 0, iclass 15, count 0 2006.238.08:18:00.61#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:18:00.61#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.238.08:18:00.61#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:18:00.61#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:18:00.61$vc4f8/vblo=1,632.99 2006.238.08:18:00.61#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.238.08:18:00.61#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.238.08:18:00.61#ibcon#ireg 17 cls_cnt 0 2006.238.08:18:00.61#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:18:00.61#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:18:00.61#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:18:00.61#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:18:00.61#ibcon#first serial, iclass 17, count 0 2006.238.08:18:00.61#ibcon#enter sib2, iclass 17, count 0 2006.238.08:18:00.61#ibcon#flushed, iclass 17, count 0 2006.238.08:18:00.61#ibcon#about to write, iclass 17, count 0 2006.238.08:18:00.61#ibcon#wrote, iclass 17, count 0 2006.238.08:18:00.61#ibcon#about to read 3, iclass 17, count 0 2006.238.08:18:00.63#ibcon#read 3, iclass 17, count 0 2006.238.08:18:00.63#ibcon#about to read 4, iclass 17, count 0 2006.238.08:18:00.63#ibcon#read 4, iclass 17, count 0 2006.238.08:18:00.63#ibcon#about to read 5, iclass 17, count 0 2006.238.08:18:00.63#ibcon#read 5, iclass 17, count 0 2006.238.08:18:00.63#ibcon#about to read 6, iclass 17, count 0 2006.238.08:18:00.63#ibcon#read 6, iclass 17, count 0 2006.238.08:18:00.63#ibcon#end of sib2, iclass 17, count 0 2006.238.08:18:00.63#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:18:00.63#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:18:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:18:00.63#ibcon#*before write, iclass 17, count 0 2006.238.08:18:00.63#ibcon#enter sib2, iclass 17, count 0 2006.238.08:18:00.63#ibcon#flushed, iclass 17, count 0 2006.238.08:18:00.63#ibcon#about to write, iclass 17, count 0 2006.238.08:18:00.63#ibcon#wrote, iclass 17, count 0 2006.238.08:18:00.63#ibcon#about to read 3, iclass 17, count 0 2006.238.08:18:00.67#ibcon#read 3, iclass 17, count 0 2006.238.08:18:00.67#ibcon#about to read 4, iclass 17, count 0 2006.238.08:18:00.67#ibcon#read 4, iclass 17, count 0 2006.238.08:18:00.67#ibcon#about to read 5, iclass 17, count 0 2006.238.08:18:00.67#ibcon#read 5, iclass 17, count 0 2006.238.08:18:00.67#ibcon#about to read 6, iclass 17, count 0 2006.238.08:18:00.67#ibcon#read 6, iclass 17, count 0 2006.238.08:18:00.67#ibcon#end of sib2, iclass 17, count 0 2006.238.08:18:00.67#ibcon#*after write, iclass 17, count 0 2006.238.08:18:00.67#ibcon#*before return 0, iclass 17, count 0 2006.238.08:18:00.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:18:00.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.238.08:18:00.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:18:00.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:18:00.67$vc4f8/vb=1,4 2006.238.08:18:00.67#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.238.08:18:00.67#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.238.08:18:00.67#ibcon#ireg 11 cls_cnt 2 2006.238.08:18:00.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:18:00.67#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:18:00.67#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:18:00.67#ibcon#enter wrdev, iclass 19, count 2 2006.238.08:18:00.67#ibcon#first serial, iclass 19, count 2 2006.238.08:18:00.67#ibcon#enter sib2, iclass 19, count 2 2006.238.08:18:00.67#ibcon#flushed, iclass 19, count 2 2006.238.08:18:00.67#ibcon#about to write, iclass 19, count 2 2006.238.08:18:00.67#ibcon#wrote, iclass 19, count 2 2006.238.08:18:00.67#ibcon#about to read 3, iclass 19, count 2 2006.238.08:18:00.69#ibcon#read 3, iclass 19, count 2 2006.238.08:18:00.69#ibcon#about to read 4, iclass 19, count 2 2006.238.08:18:00.69#ibcon#read 4, iclass 19, count 2 2006.238.08:18:00.69#ibcon#about to read 5, iclass 19, count 2 2006.238.08:18:00.69#ibcon#read 5, iclass 19, count 2 2006.238.08:18:00.69#ibcon#about to read 6, iclass 19, count 2 2006.238.08:18:00.69#ibcon#read 6, iclass 19, count 2 2006.238.08:18:00.69#ibcon#end of sib2, iclass 19, count 2 2006.238.08:18:00.69#ibcon#*mode == 0, iclass 19, count 2 2006.238.08:18:00.69#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.238.08:18:00.69#ibcon#[27=AT01-04\r\n] 2006.238.08:18:00.69#ibcon#*before write, iclass 19, count 2 2006.238.08:18:00.69#ibcon#enter sib2, iclass 19, count 2 2006.238.08:18:00.69#ibcon#flushed, iclass 19, count 2 2006.238.08:18:00.69#ibcon#about to write, iclass 19, count 2 2006.238.08:18:00.69#ibcon#wrote, iclass 19, count 2 2006.238.08:18:00.69#ibcon#about to read 3, iclass 19, count 2 2006.238.08:18:00.72#ibcon#read 3, iclass 19, count 2 2006.238.08:18:00.72#ibcon#about to read 4, iclass 19, count 2 2006.238.08:18:00.72#ibcon#read 4, iclass 19, count 2 2006.238.08:18:00.72#ibcon#about to read 5, iclass 19, count 2 2006.238.08:18:00.72#ibcon#read 5, iclass 19, count 2 2006.238.08:18:00.72#ibcon#about to read 6, iclass 19, count 2 2006.238.08:18:00.72#ibcon#read 6, iclass 19, count 2 2006.238.08:18:00.72#ibcon#end of sib2, iclass 19, count 2 2006.238.08:18:00.72#ibcon#*after write, iclass 19, count 2 2006.238.08:18:00.72#ibcon#*before return 0, iclass 19, count 2 2006.238.08:18:00.72#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:18:00.72#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.238.08:18:00.72#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.238.08:18:00.72#ibcon#ireg 7 cls_cnt 0 2006.238.08:18:00.72#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:18:00.84#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:18:00.84#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:18:00.84#ibcon#enter wrdev, iclass 19, count 0 2006.238.08:18:00.84#ibcon#first serial, iclass 19, count 0 2006.238.08:18:00.84#ibcon#enter sib2, iclass 19, count 0 2006.238.08:18:00.84#ibcon#flushed, iclass 19, count 0 2006.238.08:18:00.84#ibcon#about to write, iclass 19, count 0 2006.238.08:18:00.84#ibcon#wrote, iclass 19, count 0 2006.238.08:18:00.84#ibcon#about to read 3, iclass 19, count 0 2006.238.08:18:00.86#ibcon#read 3, iclass 19, count 0 2006.238.08:18:00.86#ibcon#about to read 4, iclass 19, count 0 2006.238.08:18:00.86#ibcon#read 4, iclass 19, count 0 2006.238.08:18:00.86#ibcon#about to read 5, iclass 19, count 0 2006.238.08:18:00.86#ibcon#read 5, iclass 19, count 0 2006.238.08:18:00.86#ibcon#about to read 6, iclass 19, count 0 2006.238.08:18:00.86#ibcon#read 6, iclass 19, count 0 2006.238.08:18:00.86#ibcon#end of sib2, iclass 19, count 0 2006.238.08:18:00.86#ibcon#*mode == 0, iclass 19, count 0 2006.238.08:18:00.86#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.08:18:00.86#ibcon#[27=USB\r\n] 2006.238.08:18:00.86#ibcon#*before write, iclass 19, count 0 2006.238.08:18:00.86#ibcon#enter sib2, iclass 19, count 0 2006.238.08:18:00.86#ibcon#flushed, iclass 19, count 0 2006.238.08:18:00.86#ibcon#about to write, iclass 19, count 0 2006.238.08:18:00.86#ibcon#wrote, iclass 19, count 0 2006.238.08:18:00.86#ibcon#about to read 3, iclass 19, count 0 2006.238.08:18:00.89#ibcon#read 3, iclass 19, count 0 2006.238.08:18:00.89#ibcon#about to read 4, iclass 19, count 0 2006.238.08:18:00.89#ibcon#read 4, iclass 19, count 0 2006.238.08:18:00.89#ibcon#about to read 5, iclass 19, count 0 2006.238.08:18:00.89#ibcon#read 5, iclass 19, count 0 2006.238.08:18:00.89#ibcon#about to read 6, iclass 19, count 0 2006.238.08:18:00.89#ibcon#read 6, iclass 19, count 0 2006.238.08:18:00.89#ibcon#end of sib2, iclass 19, count 0 2006.238.08:18:00.89#ibcon#*after write, iclass 19, count 0 2006.238.08:18:00.89#ibcon#*before return 0, iclass 19, count 0 2006.238.08:18:00.89#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:18:00.89#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.238.08:18:00.89#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.08:18:00.89#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.08:18:00.89$vc4f8/vblo=2,640.99 2006.238.08:18:00.89#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.238.08:18:00.89#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.238.08:18:00.89#ibcon#ireg 17 cls_cnt 0 2006.238.08:18:00.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:18:00.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:18:00.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:18:00.89#ibcon#enter wrdev, iclass 21, count 0 2006.238.08:18:00.89#ibcon#first serial, iclass 21, count 0 2006.238.08:18:00.89#ibcon#enter sib2, iclass 21, count 0 2006.238.08:18:00.89#ibcon#flushed, iclass 21, count 0 2006.238.08:18:00.89#ibcon#about to write, iclass 21, count 0 2006.238.08:18:00.89#ibcon#wrote, iclass 21, count 0 2006.238.08:18:00.89#ibcon#about to read 3, iclass 21, count 0 2006.238.08:18:00.91#ibcon#read 3, iclass 21, count 0 2006.238.08:18:00.91#ibcon#about to read 4, iclass 21, count 0 2006.238.08:18:00.91#ibcon#read 4, iclass 21, count 0 2006.238.08:18:00.91#ibcon#about to read 5, iclass 21, count 0 2006.238.08:18:00.91#ibcon#read 5, iclass 21, count 0 2006.238.08:18:00.91#ibcon#about to read 6, iclass 21, count 0 2006.238.08:18:00.91#ibcon#read 6, iclass 21, count 0 2006.238.08:18:00.91#ibcon#end of sib2, iclass 21, count 0 2006.238.08:18:00.91#ibcon#*mode == 0, iclass 21, count 0 2006.238.08:18:00.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.08:18:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:18:00.91#ibcon#*before write, iclass 21, count 0 2006.238.08:18:00.91#ibcon#enter sib2, iclass 21, count 0 2006.238.08:18:00.91#ibcon#flushed, iclass 21, count 0 2006.238.08:18:00.91#ibcon#about to write, iclass 21, count 0 2006.238.08:18:00.91#ibcon#wrote, iclass 21, count 0 2006.238.08:18:00.91#ibcon#about to read 3, iclass 21, count 0 2006.238.08:18:00.95#ibcon#read 3, iclass 21, count 0 2006.238.08:18:00.95#ibcon#about to read 4, iclass 21, count 0 2006.238.08:18:00.95#ibcon#read 4, iclass 21, count 0 2006.238.08:18:00.95#ibcon#about to read 5, iclass 21, count 0 2006.238.08:18:00.95#ibcon#read 5, iclass 21, count 0 2006.238.08:18:00.95#ibcon#about to read 6, iclass 21, count 0 2006.238.08:18:00.95#ibcon#read 6, iclass 21, count 0 2006.238.08:18:00.95#ibcon#end of sib2, iclass 21, count 0 2006.238.08:18:00.95#ibcon#*after write, iclass 21, count 0 2006.238.08:18:00.95#ibcon#*before return 0, iclass 21, count 0 2006.238.08:18:00.95#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:18:00.95#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.238.08:18:00.95#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.08:18:00.95#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.08:18:00.95$vc4f8/vb=2,4 2006.238.08:18:00.95#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.238.08:18:00.95#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.238.08:18:00.95#ibcon#ireg 11 cls_cnt 2 2006.238.08:18:00.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:18:01.01#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:18:01.01#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:18:01.01#ibcon#enter wrdev, iclass 23, count 2 2006.238.08:18:01.01#ibcon#first serial, iclass 23, count 2 2006.238.08:18:01.01#ibcon#enter sib2, iclass 23, count 2 2006.238.08:18:01.01#ibcon#flushed, iclass 23, count 2 2006.238.08:18:01.01#ibcon#about to write, iclass 23, count 2 2006.238.08:18:01.01#ibcon#wrote, iclass 23, count 2 2006.238.08:18:01.01#ibcon#about to read 3, iclass 23, count 2 2006.238.08:18:01.03#ibcon#read 3, iclass 23, count 2 2006.238.08:18:01.03#ibcon#about to read 4, iclass 23, count 2 2006.238.08:18:01.03#ibcon#read 4, iclass 23, count 2 2006.238.08:18:01.03#ibcon#about to read 5, iclass 23, count 2 2006.238.08:18:01.03#ibcon#read 5, iclass 23, count 2 2006.238.08:18:01.03#ibcon#about to read 6, iclass 23, count 2 2006.238.08:18:01.03#ibcon#read 6, iclass 23, count 2 2006.238.08:18:01.03#ibcon#end of sib2, iclass 23, count 2 2006.238.08:18:01.03#ibcon#*mode == 0, iclass 23, count 2 2006.238.08:18:01.03#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.238.08:18:01.03#ibcon#[27=AT02-04\r\n] 2006.238.08:18:01.03#ibcon#*before write, iclass 23, count 2 2006.238.08:18:01.03#ibcon#enter sib2, iclass 23, count 2 2006.238.08:18:01.03#ibcon#flushed, iclass 23, count 2 2006.238.08:18:01.03#ibcon#about to write, iclass 23, count 2 2006.238.08:18:01.03#ibcon#wrote, iclass 23, count 2 2006.238.08:18:01.03#ibcon#about to read 3, iclass 23, count 2 2006.238.08:18:01.06#ibcon#read 3, iclass 23, count 2 2006.238.08:18:01.06#ibcon#about to read 4, iclass 23, count 2 2006.238.08:18:01.06#ibcon#read 4, iclass 23, count 2 2006.238.08:18:01.06#ibcon#about to read 5, iclass 23, count 2 2006.238.08:18:01.06#ibcon#read 5, iclass 23, count 2 2006.238.08:18:01.06#ibcon#about to read 6, iclass 23, count 2 2006.238.08:18:01.06#ibcon#read 6, iclass 23, count 2 2006.238.08:18:01.06#ibcon#end of sib2, iclass 23, count 2 2006.238.08:18:01.06#ibcon#*after write, iclass 23, count 2 2006.238.08:18:01.06#ibcon#*before return 0, iclass 23, count 2 2006.238.08:18:01.06#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:18:01.06#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.238.08:18:01.06#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.238.08:18:01.06#ibcon#ireg 7 cls_cnt 0 2006.238.08:18:01.06#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:18:01.18#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:18:01.18#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:18:01.18#ibcon#enter wrdev, iclass 23, count 0 2006.238.08:18:01.18#ibcon#first serial, iclass 23, count 0 2006.238.08:18:01.18#ibcon#enter sib2, iclass 23, count 0 2006.238.08:18:01.18#ibcon#flushed, iclass 23, count 0 2006.238.08:18:01.18#ibcon#about to write, iclass 23, count 0 2006.238.08:18:01.18#ibcon#wrote, iclass 23, count 0 2006.238.08:18:01.18#ibcon#about to read 3, iclass 23, count 0 2006.238.08:18:01.20#ibcon#read 3, iclass 23, count 0 2006.238.08:18:01.20#ibcon#about to read 4, iclass 23, count 0 2006.238.08:18:01.20#ibcon#read 4, iclass 23, count 0 2006.238.08:18:01.20#ibcon#about to read 5, iclass 23, count 0 2006.238.08:18:01.20#ibcon#read 5, iclass 23, count 0 2006.238.08:18:01.20#ibcon#about to read 6, iclass 23, count 0 2006.238.08:18:01.20#ibcon#read 6, iclass 23, count 0 2006.238.08:18:01.20#ibcon#end of sib2, iclass 23, count 0 2006.238.08:18:01.20#ibcon#*mode == 0, iclass 23, count 0 2006.238.08:18:01.20#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.08:18:01.20#ibcon#[27=USB\r\n] 2006.238.08:18:01.20#ibcon#*before write, iclass 23, count 0 2006.238.08:18:01.20#ibcon#enter sib2, iclass 23, count 0 2006.238.08:18:01.20#ibcon#flushed, iclass 23, count 0 2006.238.08:18:01.20#ibcon#about to write, iclass 23, count 0 2006.238.08:18:01.20#ibcon#wrote, iclass 23, count 0 2006.238.08:18:01.20#ibcon#about to read 3, iclass 23, count 0 2006.238.08:18:01.23#ibcon#read 3, iclass 23, count 0 2006.238.08:18:01.23#ibcon#about to read 4, iclass 23, count 0 2006.238.08:18:01.23#ibcon#read 4, iclass 23, count 0 2006.238.08:18:01.23#ibcon#about to read 5, iclass 23, count 0 2006.238.08:18:01.23#ibcon#read 5, iclass 23, count 0 2006.238.08:18:01.23#ibcon#about to read 6, iclass 23, count 0 2006.238.08:18:01.23#ibcon#read 6, iclass 23, count 0 2006.238.08:18:01.23#ibcon#end of sib2, iclass 23, count 0 2006.238.08:18:01.23#ibcon#*after write, iclass 23, count 0 2006.238.08:18:01.23#ibcon#*before return 0, iclass 23, count 0 2006.238.08:18:01.23#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:18:01.23#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.238.08:18:01.23#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.08:18:01.23#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.08:18:01.23$vc4f8/vblo=3,656.99 2006.238.08:18:01.23#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.238.08:18:01.23#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.238.08:18:01.23#ibcon#ireg 17 cls_cnt 0 2006.238.08:18:01.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:18:01.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:18:01.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:18:01.23#ibcon#enter wrdev, iclass 25, count 0 2006.238.08:18:01.23#ibcon#first serial, iclass 25, count 0 2006.238.08:18:01.23#ibcon#enter sib2, iclass 25, count 0 2006.238.08:18:01.23#ibcon#flushed, iclass 25, count 0 2006.238.08:18:01.23#ibcon#about to write, iclass 25, count 0 2006.238.08:18:01.23#ibcon#wrote, iclass 25, count 0 2006.238.08:18:01.23#ibcon#about to read 3, iclass 25, count 0 2006.238.08:18:01.25#ibcon#read 3, iclass 25, count 0 2006.238.08:18:01.25#ibcon#about to read 4, iclass 25, count 0 2006.238.08:18:01.25#ibcon#read 4, iclass 25, count 0 2006.238.08:18:01.25#ibcon#about to read 5, iclass 25, count 0 2006.238.08:18:01.25#ibcon#read 5, iclass 25, count 0 2006.238.08:18:01.25#ibcon#about to read 6, iclass 25, count 0 2006.238.08:18:01.25#ibcon#read 6, iclass 25, count 0 2006.238.08:18:01.25#ibcon#end of sib2, iclass 25, count 0 2006.238.08:18:01.25#ibcon#*mode == 0, iclass 25, count 0 2006.238.08:18:01.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.08:18:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:18:01.25#ibcon#*before write, iclass 25, count 0 2006.238.08:18:01.25#ibcon#enter sib2, iclass 25, count 0 2006.238.08:18:01.25#ibcon#flushed, iclass 25, count 0 2006.238.08:18:01.25#ibcon#about to write, iclass 25, count 0 2006.238.08:18:01.25#ibcon#wrote, iclass 25, count 0 2006.238.08:18:01.25#ibcon#about to read 3, iclass 25, count 0 2006.238.08:18:01.29#ibcon#read 3, iclass 25, count 0 2006.238.08:18:01.29#ibcon#about to read 4, iclass 25, count 0 2006.238.08:18:01.29#ibcon#read 4, iclass 25, count 0 2006.238.08:18:01.29#ibcon#about to read 5, iclass 25, count 0 2006.238.08:18:01.29#ibcon#read 5, iclass 25, count 0 2006.238.08:18:01.29#ibcon#about to read 6, iclass 25, count 0 2006.238.08:18:01.29#ibcon#read 6, iclass 25, count 0 2006.238.08:18:01.29#ibcon#end of sib2, iclass 25, count 0 2006.238.08:18:01.29#ibcon#*after write, iclass 25, count 0 2006.238.08:18:01.29#ibcon#*before return 0, iclass 25, count 0 2006.238.08:18:01.29#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:18:01.29#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.238.08:18:01.29#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.08:18:01.29#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.08:18:01.29$vc4f8/vb=3,4 2006.238.08:18:01.29#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.238.08:18:01.29#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.238.08:18:01.29#ibcon#ireg 11 cls_cnt 2 2006.238.08:18:01.29#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:18:01.35#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:18:01.35#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:18:01.35#ibcon#enter wrdev, iclass 27, count 2 2006.238.08:18:01.35#ibcon#first serial, iclass 27, count 2 2006.238.08:18:01.35#ibcon#enter sib2, iclass 27, count 2 2006.238.08:18:01.35#ibcon#flushed, iclass 27, count 2 2006.238.08:18:01.35#ibcon#about to write, iclass 27, count 2 2006.238.08:18:01.35#ibcon#wrote, iclass 27, count 2 2006.238.08:18:01.35#ibcon#about to read 3, iclass 27, count 2 2006.238.08:18:01.37#ibcon#read 3, iclass 27, count 2 2006.238.08:18:01.37#ibcon#about to read 4, iclass 27, count 2 2006.238.08:18:01.37#ibcon#read 4, iclass 27, count 2 2006.238.08:18:01.37#ibcon#about to read 5, iclass 27, count 2 2006.238.08:18:01.37#ibcon#read 5, iclass 27, count 2 2006.238.08:18:01.37#ibcon#about to read 6, iclass 27, count 2 2006.238.08:18:01.37#ibcon#read 6, iclass 27, count 2 2006.238.08:18:01.37#ibcon#end of sib2, iclass 27, count 2 2006.238.08:18:01.37#ibcon#*mode == 0, iclass 27, count 2 2006.238.08:18:01.37#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.238.08:18:01.37#ibcon#[27=AT03-04\r\n] 2006.238.08:18:01.37#ibcon#*before write, iclass 27, count 2 2006.238.08:18:01.37#ibcon#enter sib2, iclass 27, count 2 2006.238.08:18:01.37#ibcon#flushed, iclass 27, count 2 2006.238.08:18:01.37#ibcon#about to write, iclass 27, count 2 2006.238.08:18:01.37#ibcon#wrote, iclass 27, count 2 2006.238.08:18:01.37#ibcon#about to read 3, iclass 27, count 2 2006.238.08:18:01.40#ibcon#read 3, iclass 27, count 2 2006.238.08:18:01.40#ibcon#about to read 4, iclass 27, count 2 2006.238.08:18:01.40#ibcon#read 4, iclass 27, count 2 2006.238.08:18:01.40#ibcon#about to read 5, iclass 27, count 2 2006.238.08:18:01.40#ibcon#read 5, iclass 27, count 2 2006.238.08:18:01.40#ibcon#about to read 6, iclass 27, count 2 2006.238.08:18:01.40#ibcon#read 6, iclass 27, count 2 2006.238.08:18:01.40#ibcon#end of sib2, iclass 27, count 2 2006.238.08:18:01.40#ibcon#*after write, iclass 27, count 2 2006.238.08:18:01.40#ibcon#*before return 0, iclass 27, count 2 2006.238.08:18:01.40#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:18:01.40#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.238.08:18:01.40#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.238.08:18:01.40#ibcon#ireg 7 cls_cnt 0 2006.238.08:18:01.40#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:18:01.52#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:18:01.52#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:18:01.52#ibcon#enter wrdev, iclass 27, count 0 2006.238.08:18:01.52#ibcon#first serial, iclass 27, count 0 2006.238.08:18:01.52#ibcon#enter sib2, iclass 27, count 0 2006.238.08:18:01.52#ibcon#flushed, iclass 27, count 0 2006.238.08:18:01.52#ibcon#about to write, iclass 27, count 0 2006.238.08:18:01.52#ibcon#wrote, iclass 27, count 0 2006.238.08:18:01.52#ibcon#about to read 3, iclass 27, count 0 2006.238.08:18:01.54#ibcon#read 3, iclass 27, count 0 2006.238.08:18:01.54#ibcon#about to read 4, iclass 27, count 0 2006.238.08:18:01.54#ibcon#read 4, iclass 27, count 0 2006.238.08:18:01.54#ibcon#about to read 5, iclass 27, count 0 2006.238.08:18:01.54#ibcon#read 5, iclass 27, count 0 2006.238.08:18:01.54#ibcon#about to read 6, iclass 27, count 0 2006.238.08:18:01.54#ibcon#read 6, iclass 27, count 0 2006.238.08:18:01.54#ibcon#end of sib2, iclass 27, count 0 2006.238.08:18:01.54#ibcon#*mode == 0, iclass 27, count 0 2006.238.08:18:01.54#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.08:18:01.54#ibcon#[27=USB\r\n] 2006.238.08:18:01.54#ibcon#*before write, iclass 27, count 0 2006.238.08:18:01.54#ibcon#enter sib2, iclass 27, count 0 2006.238.08:18:01.54#ibcon#flushed, iclass 27, count 0 2006.238.08:18:01.54#ibcon#about to write, iclass 27, count 0 2006.238.08:18:01.54#ibcon#wrote, iclass 27, count 0 2006.238.08:18:01.54#ibcon#about to read 3, iclass 27, count 0 2006.238.08:18:01.57#ibcon#read 3, iclass 27, count 0 2006.238.08:18:01.57#ibcon#about to read 4, iclass 27, count 0 2006.238.08:18:01.57#ibcon#read 4, iclass 27, count 0 2006.238.08:18:01.57#ibcon#about to read 5, iclass 27, count 0 2006.238.08:18:01.57#ibcon#read 5, iclass 27, count 0 2006.238.08:18:01.57#ibcon#about to read 6, iclass 27, count 0 2006.238.08:18:01.57#ibcon#read 6, iclass 27, count 0 2006.238.08:18:01.57#ibcon#end of sib2, iclass 27, count 0 2006.238.08:18:01.57#ibcon#*after write, iclass 27, count 0 2006.238.08:18:01.57#ibcon#*before return 0, iclass 27, count 0 2006.238.08:18:01.57#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:18:01.57#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.238.08:18:01.57#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.08:18:01.57#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.08:18:01.57$vc4f8/vblo=4,712.99 2006.238.08:18:01.57#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.238.08:18:01.57#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.238.08:18:01.57#ibcon#ireg 17 cls_cnt 0 2006.238.08:18:01.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:18:01.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:18:01.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:18:01.57#ibcon#enter wrdev, iclass 29, count 0 2006.238.08:18:01.57#ibcon#first serial, iclass 29, count 0 2006.238.08:18:01.57#ibcon#enter sib2, iclass 29, count 0 2006.238.08:18:01.57#ibcon#flushed, iclass 29, count 0 2006.238.08:18:01.57#ibcon#about to write, iclass 29, count 0 2006.238.08:18:01.57#ibcon#wrote, iclass 29, count 0 2006.238.08:18:01.57#ibcon#about to read 3, iclass 29, count 0 2006.238.08:18:01.59#ibcon#read 3, iclass 29, count 0 2006.238.08:18:01.59#ibcon#about to read 4, iclass 29, count 0 2006.238.08:18:01.59#ibcon#read 4, iclass 29, count 0 2006.238.08:18:01.59#ibcon#about to read 5, iclass 29, count 0 2006.238.08:18:01.59#ibcon#read 5, iclass 29, count 0 2006.238.08:18:01.59#ibcon#about to read 6, iclass 29, count 0 2006.238.08:18:01.59#ibcon#read 6, iclass 29, count 0 2006.238.08:18:01.59#ibcon#end of sib2, iclass 29, count 0 2006.238.08:18:01.59#ibcon#*mode == 0, iclass 29, count 0 2006.238.08:18:01.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.08:18:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:18:01.59#ibcon#*before write, iclass 29, count 0 2006.238.08:18:01.59#ibcon#enter sib2, iclass 29, count 0 2006.238.08:18:01.59#ibcon#flushed, iclass 29, count 0 2006.238.08:18:01.59#ibcon#about to write, iclass 29, count 0 2006.238.08:18:01.59#ibcon#wrote, iclass 29, count 0 2006.238.08:18:01.59#ibcon#about to read 3, iclass 29, count 0 2006.238.08:18:01.63#ibcon#read 3, iclass 29, count 0 2006.238.08:18:01.63#ibcon#about to read 4, iclass 29, count 0 2006.238.08:18:01.63#ibcon#read 4, iclass 29, count 0 2006.238.08:18:01.63#ibcon#about to read 5, iclass 29, count 0 2006.238.08:18:01.63#ibcon#read 5, iclass 29, count 0 2006.238.08:18:01.63#ibcon#about to read 6, iclass 29, count 0 2006.238.08:18:01.63#ibcon#read 6, iclass 29, count 0 2006.238.08:18:01.63#ibcon#end of sib2, iclass 29, count 0 2006.238.08:18:01.63#ibcon#*after write, iclass 29, count 0 2006.238.08:18:01.63#ibcon#*before return 0, iclass 29, count 0 2006.238.08:18:01.63#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:18:01.63#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.238.08:18:01.63#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.08:18:01.63#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.08:18:01.63$vc4f8/vb=4,4 2006.238.08:18:01.63#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.238.08:18:01.63#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.238.08:18:01.63#ibcon#ireg 11 cls_cnt 2 2006.238.08:18:01.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:18:01.69#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:18:01.69#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:18:01.69#ibcon#enter wrdev, iclass 31, count 2 2006.238.08:18:01.69#ibcon#first serial, iclass 31, count 2 2006.238.08:18:01.69#ibcon#enter sib2, iclass 31, count 2 2006.238.08:18:01.69#ibcon#flushed, iclass 31, count 2 2006.238.08:18:01.69#ibcon#about to write, iclass 31, count 2 2006.238.08:18:01.69#ibcon#wrote, iclass 31, count 2 2006.238.08:18:01.69#ibcon#about to read 3, iclass 31, count 2 2006.238.08:18:01.71#ibcon#read 3, iclass 31, count 2 2006.238.08:18:01.71#ibcon#about to read 4, iclass 31, count 2 2006.238.08:18:01.71#ibcon#read 4, iclass 31, count 2 2006.238.08:18:01.71#ibcon#about to read 5, iclass 31, count 2 2006.238.08:18:01.71#ibcon#read 5, iclass 31, count 2 2006.238.08:18:01.71#ibcon#about to read 6, iclass 31, count 2 2006.238.08:18:01.71#ibcon#read 6, iclass 31, count 2 2006.238.08:18:01.71#ibcon#end of sib2, iclass 31, count 2 2006.238.08:18:01.71#ibcon#*mode == 0, iclass 31, count 2 2006.238.08:18:01.71#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.238.08:18:01.71#ibcon#[27=AT04-04\r\n] 2006.238.08:18:01.71#ibcon#*before write, iclass 31, count 2 2006.238.08:18:01.71#ibcon#enter sib2, iclass 31, count 2 2006.238.08:18:01.71#ibcon#flushed, iclass 31, count 2 2006.238.08:18:01.71#ibcon#about to write, iclass 31, count 2 2006.238.08:18:01.71#ibcon#wrote, iclass 31, count 2 2006.238.08:18:01.71#ibcon#about to read 3, iclass 31, count 2 2006.238.08:18:01.74#ibcon#read 3, iclass 31, count 2 2006.238.08:18:01.74#ibcon#about to read 4, iclass 31, count 2 2006.238.08:18:01.74#ibcon#read 4, iclass 31, count 2 2006.238.08:18:01.74#ibcon#about to read 5, iclass 31, count 2 2006.238.08:18:01.74#ibcon#read 5, iclass 31, count 2 2006.238.08:18:01.74#ibcon#about to read 6, iclass 31, count 2 2006.238.08:18:01.74#ibcon#read 6, iclass 31, count 2 2006.238.08:18:01.74#ibcon#end of sib2, iclass 31, count 2 2006.238.08:18:01.74#ibcon#*after write, iclass 31, count 2 2006.238.08:18:01.74#ibcon#*before return 0, iclass 31, count 2 2006.238.08:18:01.74#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:18:01.74#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.238.08:18:01.74#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.238.08:18:01.74#ibcon#ireg 7 cls_cnt 0 2006.238.08:18:01.74#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:18:01.86#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:18:01.86#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:18:01.86#ibcon#enter wrdev, iclass 31, count 0 2006.238.08:18:01.86#ibcon#first serial, iclass 31, count 0 2006.238.08:18:01.86#ibcon#enter sib2, iclass 31, count 0 2006.238.08:18:01.86#ibcon#flushed, iclass 31, count 0 2006.238.08:18:01.86#ibcon#about to write, iclass 31, count 0 2006.238.08:18:01.86#ibcon#wrote, iclass 31, count 0 2006.238.08:18:01.86#ibcon#about to read 3, iclass 31, count 0 2006.238.08:18:01.88#ibcon#read 3, iclass 31, count 0 2006.238.08:18:01.88#ibcon#about to read 4, iclass 31, count 0 2006.238.08:18:01.88#ibcon#read 4, iclass 31, count 0 2006.238.08:18:01.88#ibcon#about to read 5, iclass 31, count 0 2006.238.08:18:01.88#ibcon#read 5, iclass 31, count 0 2006.238.08:18:01.88#ibcon#about to read 6, iclass 31, count 0 2006.238.08:18:01.88#ibcon#read 6, iclass 31, count 0 2006.238.08:18:01.88#ibcon#end of sib2, iclass 31, count 0 2006.238.08:18:01.88#ibcon#*mode == 0, iclass 31, count 0 2006.238.08:18:01.88#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.08:18:01.88#ibcon#[27=USB\r\n] 2006.238.08:18:01.88#ibcon#*before write, iclass 31, count 0 2006.238.08:18:01.88#ibcon#enter sib2, iclass 31, count 0 2006.238.08:18:01.88#ibcon#flushed, iclass 31, count 0 2006.238.08:18:01.88#ibcon#about to write, iclass 31, count 0 2006.238.08:18:01.88#ibcon#wrote, iclass 31, count 0 2006.238.08:18:01.88#ibcon#about to read 3, iclass 31, count 0 2006.238.08:18:01.91#ibcon#read 3, iclass 31, count 0 2006.238.08:18:01.91#ibcon#about to read 4, iclass 31, count 0 2006.238.08:18:01.91#ibcon#read 4, iclass 31, count 0 2006.238.08:18:01.91#ibcon#about to read 5, iclass 31, count 0 2006.238.08:18:01.91#ibcon#read 5, iclass 31, count 0 2006.238.08:18:01.91#ibcon#about to read 6, iclass 31, count 0 2006.238.08:18:01.91#ibcon#read 6, iclass 31, count 0 2006.238.08:18:01.91#ibcon#end of sib2, iclass 31, count 0 2006.238.08:18:01.91#ibcon#*after write, iclass 31, count 0 2006.238.08:18:01.91#ibcon#*before return 0, iclass 31, count 0 2006.238.08:18:01.91#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:18:01.91#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.238.08:18:01.91#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.08:18:01.91#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.08:18:01.91$vc4f8/vblo=5,744.99 2006.238.08:18:01.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.08:18:01.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.08:18:01.91#ibcon#ireg 17 cls_cnt 0 2006.238.08:18:01.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:18:01.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:18:01.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:18:01.91#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:18:01.91#ibcon#first serial, iclass 33, count 0 2006.238.08:18:01.91#ibcon#enter sib2, iclass 33, count 0 2006.238.08:18:01.91#ibcon#flushed, iclass 33, count 0 2006.238.08:18:01.91#ibcon#about to write, iclass 33, count 0 2006.238.08:18:01.91#ibcon#wrote, iclass 33, count 0 2006.238.08:18:01.91#ibcon#about to read 3, iclass 33, count 0 2006.238.08:18:01.93#ibcon#read 3, iclass 33, count 0 2006.238.08:18:01.93#ibcon#about to read 4, iclass 33, count 0 2006.238.08:18:01.93#ibcon#read 4, iclass 33, count 0 2006.238.08:18:01.93#ibcon#about to read 5, iclass 33, count 0 2006.238.08:18:01.93#ibcon#read 5, iclass 33, count 0 2006.238.08:18:01.93#ibcon#about to read 6, iclass 33, count 0 2006.238.08:18:01.93#ibcon#read 6, iclass 33, count 0 2006.238.08:18:01.93#ibcon#end of sib2, iclass 33, count 0 2006.238.08:18:01.93#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:18:01.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:18:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:18:01.93#ibcon#*before write, iclass 33, count 0 2006.238.08:18:01.93#ibcon#enter sib2, iclass 33, count 0 2006.238.08:18:01.93#ibcon#flushed, iclass 33, count 0 2006.238.08:18:01.93#ibcon#about to write, iclass 33, count 0 2006.238.08:18:01.93#ibcon#wrote, iclass 33, count 0 2006.238.08:18:01.93#ibcon#about to read 3, iclass 33, count 0 2006.238.08:18:01.97#ibcon#read 3, iclass 33, count 0 2006.238.08:18:01.97#ibcon#about to read 4, iclass 33, count 0 2006.238.08:18:01.97#ibcon#read 4, iclass 33, count 0 2006.238.08:18:01.97#ibcon#about to read 5, iclass 33, count 0 2006.238.08:18:01.97#ibcon#read 5, iclass 33, count 0 2006.238.08:18:01.97#ibcon#about to read 6, iclass 33, count 0 2006.238.08:18:01.97#ibcon#read 6, iclass 33, count 0 2006.238.08:18:01.97#ibcon#end of sib2, iclass 33, count 0 2006.238.08:18:01.97#ibcon#*after write, iclass 33, count 0 2006.238.08:18:01.97#ibcon#*before return 0, iclass 33, count 0 2006.238.08:18:01.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:18:01.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:18:01.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:18:01.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:18:01.97$vc4f8/vb=5,4 2006.238.08:18:01.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.238.08:18:01.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.238.08:18:01.97#ibcon#ireg 11 cls_cnt 2 2006.238.08:18:01.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:18:02.03#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:18:02.03#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:18:02.03#ibcon#enter wrdev, iclass 35, count 2 2006.238.08:18:02.03#ibcon#first serial, iclass 35, count 2 2006.238.08:18:02.03#ibcon#enter sib2, iclass 35, count 2 2006.238.08:18:02.03#ibcon#flushed, iclass 35, count 2 2006.238.08:18:02.03#ibcon#about to write, iclass 35, count 2 2006.238.08:18:02.03#ibcon#wrote, iclass 35, count 2 2006.238.08:18:02.03#ibcon#about to read 3, iclass 35, count 2 2006.238.08:18:02.05#ibcon#read 3, iclass 35, count 2 2006.238.08:18:02.05#ibcon#about to read 4, iclass 35, count 2 2006.238.08:18:02.05#ibcon#read 4, iclass 35, count 2 2006.238.08:18:02.05#ibcon#about to read 5, iclass 35, count 2 2006.238.08:18:02.05#ibcon#read 5, iclass 35, count 2 2006.238.08:18:02.05#ibcon#about to read 6, iclass 35, count 2 2006.238.08:18:02.05#ibcon#read 6, iclass 35, count 2 2006.238.08:18:02.05#ibcon#end of sib2, iclass 35, count 2 2006.238.08:18:02.05#ibcon#*mode == 0, iclass 35, count 2 2006.238.08:18:02.05#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.238.08:18:02.05#ibcon#[27=AT05-04\r\n] 2006.238.08:18:02.05#ibcon#*before write, iclass 35, count 2 2006.238.08:18:02.05#ibcon#enter sib2, iclass 35, count 2 2006.238.08:18:02.05#ibcon#flushed, iclass 35, count 2 2006.238.08:18:02.05#ibcon#about to write, iclass 35, count 2 2006.238.08:18:02.05#ibcon#wrote, iclass 35, count 2 2006.238.08:18:02.05#ibcon#about to read 3, iclass 35, count 2 2006.238.08:18:02.08#ibcon#read 3, iclass 35, count 2 2006.238.08:18:02.08#ibcon#about to read 4, iclass 35, count 2 2006.238.08:18:02.08#ibcon#read 4, iclass 35, count 2 2006.238.08:18:02.08#ibcon#about to read 5, iclass 35, count 2 2006.238.08:18:02.08#ibcon#read 5, iclass 35, count 2 2006.238.08:18:02.08#ibcon#about to read 6, iclass 35, count 2 2006.238.08:18:02.08#ibcon#read 6, iclass 35, count 2 2006.238.08:18:02.08#ibcon#end of sib2, iclass 35, count 2 2006.238.08:18:02.08#ibcon#*after write, iclass 35, count 2 2006.238.08:18:02.08#ibcon#*before return 0, iclass 35, count 2 2006.238.08:18:02.08#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:18:02.08#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.238.08:18:02.08#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.238.08:18:02.08#ibcon#ireg 7 cls_cnt 0 2006.238.08:18:02.08#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:18:02.20#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:18:02.20#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:18:02.20#ibcon#enter wrdev, iclass 35, count 0 2006.238.08:18:02.20#ibcon#first serial, iclass 35, count 0 2006.238.08:18:02.20#ibcon#enter sib2, iclass 35, count 0 2006.238.08:18:02.20#ibcon#flushed, iclass 35, count 0 2006.238.08:18:02.20#ibcon#about to write, iclass 35, count 0 2006.238.08:18:02.20#ibcon#wrote, iclass 35, count 0 2006.238.08:18:02.20#ibcon#about to read 3, iclass 35, count 0 2006.238.08:18:02.22#ibcon#read 3, iclass 35, count 0 2006.238.08:18:02.22#ibcon#about to read 4, iclass 35, count 0 2006.238.08:18:02.22#ibcon#read 4, iclass 35, count 0 2006.238.08:18:02.22#ibcon#about to read 5, iclass 35, count 0 2006.238.08:18:02.22#ibcon#read 5, iclass 35, count 0 2006.238.08:18:02.22#ibcon#about to read 6, iclass 35, count 0 2006.238.08:18:02.22#ibcon#read 6, iclass 35, count 0 2006.238.08:18:02.22#ibcon#end of sib2, iclass 35, count 0 2006.238.08:18:02.22#ibcon#*mode == 0, iclass 35, count 0 2006.238.08:18:02.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.08:18:02.22#ibcon#[27=USB\r\n] 2006.238.08:18:02.22#ibcon#*before write, iclass 35, count 0 2006.238.08:18:02.22#ibcon#enter sib2, iclass 35, count 0 2006.238.08:18:02.22#ibcon#flushed, iclass 35, count 0 2006.238.08:18:02.22#ibcon#about to write, iclass 35, count 0 2006.238.08:18:02.22#ibcon#wrote, iclass 35, count 0 2006.238.08:18:02.22#ibcon#about to read 3, iclass 35, count 0 2006.238.08:18:02.25#ibcon#read 3, iclass 35, count 0 2006.238.08:18:02.25#ibcon#about to read 4, iclass 35, count 0 2006.238.08:18:02.25#ibcon#read 4, iclass 35, count 0 2006.238.08:18:02.25#ibcon#about to read 5, iclass 35, count 0 2006.238.08:18:02.25#ibcon#read 5, iclass 35, count 0 2006.238.08:18:02.25#ibcon#about to read 6, iclass 35, count 0 2006.238.08:18:02.25#ibcon#read 6, iclass 35, count 0 2006.238.08:18:02.25#ibcon#end of sib2, iclass 35, count 0 2006.238.08:18:02.25#ibcon#*after write, iclass 35, count 0 2006.238.08:18:02.25#ibcon#*before return 0, iclass 35, count 0 2006.238.08:18:02.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:18:02.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.238.08:18:02.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.08:18:02.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.08:18:02.25$vc4f8/vblo=6,752.99 2006.238.08:18:02.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.238.08:18:02.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.238.08:18:02.25#ibcon#ireg 17 cls_cnt 0 2006.238.08:18:02.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:18:02.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:18:02.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:18:02.25#ibcon#enter wrdev, iclass 37, count 0 2006.238.08:18:02.25#ibcon#first serial, iclass 37, count 0 2006.238.08:18:02.25#ibcon#enter sib2, iclass 37, count 0 2006.238.08:18:02.25#ibcon#flushed, iclass 37, count 0 2006.238.08:18:02.25#ibcon#about to write, iclass 37, count 0 2006.238.08:18:02.25#ibcon#wrote, iclass 37, count 0 2006.238.08:18:02.25#ibcon#about to read 3, iclass 37, count 0 2006.238.08:18:02.27#ibcon#read 3, iclass 37, count 0 2006.238.08:18:02.27#ibcon#about to read 4, iclass 37, count 0 2006.238.08:18:02.27#ibcon#read 4, iclass 37, count 0 2006.238.08:18:02.27#ibcon#about to read 5, iclass 37, count 0 2006.238.08:18:02.27#ibcon#read 5, iclass 37, count 0 2006.238.08:18:02.27#ibcon#about to read 6, iclass 37, count 0 2006.238.08:18:02.27#ibcon#read 6, iclass 37, count 0 2006.238.08:18:02.27#ibcon#end of sib2, iclass 37, count 0 2006.238.08:18:02.27#ibcon#*mode == 0, iclass 37, count 0 2006.238.08:18:02.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.08:18:02.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:18:02.27#ibcon#*before write, iclass 37, count 0 2006.238.08:18:02.27#ibcon#enter sib2, iclass 37, count 0 2006.238.08:18:02.27#ibcon#flushed, iclass 37, count 0 2006.238.08:18:02.27#ibcon#about to write, iclass 37, count 0 2006.238.08:18:02.27#ibcon#wrote, iclass 37, count 0 2006.238.08:18:02.27#ibcon#about to read 3, iclass 37, count 0 2006.238.08:18:02.31#ibcon#read 3, iclass 37, count 0 2006.238.08:18:02.31#ibcon#about to read 4, iclass 37, count 0 2006.238.08:18:02.31#ibcon#read 4, iclass 37, count 0 2006.238.08:18:02.31#ibcon#about to read 5, iclass 37, count 0 2006.238.08:18:02.31#ibcon#read 5, iclass 37, count 0 2006.238.08:18:02.31#ibcon#about to read 6, iclass 37, count 0 2006.238.08:18:02.31#ibcon#read 6, iclass 37, count 0 2006.238.08:18:02.31#ibcon#end of sib2, iclass 37, count 0 2006.238.08:18:02.31#ibcon#*after write, iclass 37, count 0 2006.238.08:18:02.31#ibcon#*before return 0, iclass 37, count 0 2006.238.08:18:02.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:18:02.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.238.08:18:02.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.08:18:02.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.08:18:02.31$vc4f8/vb=6,4 2006.238.08:18:02.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.238.08:18:02.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.238.08:18:02.31#ibcon#ireg 11 cls_cnt 2 2006.238.08:18:02.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:18:02.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:18:02.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:18:02.37#ibcon#enter wrdev, iclass 39, count 2 2006.238.08:18:02.37#ibcon#first serial, iclass 39, count 2 2006.238.08:18:02.37#ibcon#enter sib2, iclass 39, count 2 2006.238.08:18:02.37#ibcon#flushed, iclass 39, count 2 2006.238.08:18:02.37#ibcon#about to write, iclass 39, count 2 2006.238.08:18:02.37#ibcon#wrote, iclass 39, count 2 2006.238.08:18:02.37#ibcon#about to read 3, iclass 39, count 2 2006.238.08:18:02.39#ibcon#read 3, iclass 39, count 2 2006.238.08:18:02.39#ibcon#about to read 4, iclass 39, count 2 2006.238.08:18:02.39#ibcon#read 4, iclass 39, count 2 2006.238.08:18:02.39#ibcon#about to read 5, iclass 39, count 2 2006.238.08:18:02.39#ibcon#read 5, iclass 39, count 2 2006.238.08:18:02.39#ibcon#about to read 6, iclass 39, count 2 2006.238.08:18:02.39#ibcon#read 6, iclass 39, count 2 2006.238.08:18:02.39#ibcon#end of sib2, iclass 39, count 2 2006.238.08:18:02.39#ibcon#*mode == 0, iclass 39, count 2 2006.238.08:18:02.39#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.238.08:18:02.39#ibcon#[27=AT06-04\r\n] 2006.238.08:18:02.39#ibcon#*before write, iclass 39, count 2 2006.238.08:18:02.39#ibcon#enter sib2, iclass 39, count 2 2006.238.08:18:02.39#ibcon#flushed, iclass 39, count 2 2006.238.08:18:02.39#ibcon#about to write, iclass 39, count 2 2006.238.08:18:02.39#ibcon#wrote, iclass 39, count 2 2006.238.08:18:02.39#ibcon#about to read 3, iclass 39, count 2 2006.238.08:18:02.42#ibcon#read 3, iclass 39, count 2 2006.238.08:18:02.42#ibcon#about to read 4, iclass 39, count 2 2006.238.08:18:02.42#ibcon#read 4, iclass 39, count 2 2006.238.08:18:02.42#ibcon#about to read 5, iclass 39, count 2 2006.238.08:18:02.42#ibcon#read 5, iclass 39, count 2 2006.238.08:18:02.42#ibcon#about to read 6, iclass 39, count 2 2006.238.08:18:02.42#ibcon#read 6, iclass 39, count 2 2006.238.08:18:02.42#ibcon#end of sib2, iclass 39, count 2 2006.238.08:18:02.42#ibcon#*after write, iclass 39, count 2 2006.238.08:18:02.42#ibcon#*before return 0, iclass 39, count 2 2006.238.08:18:02.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:18:02.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.238.08:18:02.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.238.08:18:02.42#ibcon#ireg 7 cls_cnt 0 2006.238.08:18:02.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:18:02.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:18:02.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:18:02.54#ibcon#enter wrdev, iclass 39, count 0 2006.238.08:18:02.54#ibcon#first serial, iclass 39, count 0 2006.238.08:18:02.54#ibcon#enter sib2, iclass 39, count 0 2006.238.08:18:02.54#ibcon#flushed, iclass 39, count 0 2006.238.08:18:02.54#ibcon#about to write, iclass 39, count 0 2006.238.08:18:02.54#ibcon#wrote, iclass 39, count 0 2006.238.08:18:02.54#ibcon#about to read 3, iclass 39, count 0 2006.238.08:18:02.56#ibcon#read 3, iclass 39, count 0 2006.238.08:18:02.56#ibcon#about to read 4, iclass 39, count 0 2006.238.08:18:02.56#ibcon#read 4, iclass 39, count 0 2006.238.08:18:02.56#ibcon#about to read 5, iclass 39, count 0 2006.238.08:18:02.56#ibcon#read 5, iclass 39, count 0 2006.238.08:18:02.56#ibcon#about to read 6, iclass 39, count 0 2006.238.08:18:02.56#ibcon#read 6, iclass 39, count 0 2006.238.08:18:02.56#ibcon#end of sib2, iclass 39, count 0 2006.238.08:18:02.56#ibcon#*mode == 0, iclass 39, count 0 2006.238.08:18:02.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.08:18:02.56#ibcon#[27=USB\r\n] 2006.238.08:18:02.56#ibcon#*before write, iclass 39, count 0 2006.238.08:18:02.56#ibcon#enter sib2, iclass 39, count 0 2006.238.08:18:02.56#ibcon#flushed, iclass 39, count 0 2006.238.08:18:02.56#ibcon#about to write, iclass 39, count 0 2006.238.08:18:02.56#ibcon#wrote, iclass 39, count 0 2006.238.08:18:02.56#ibcon#about to read 3, iclass 39, count 0 2006.238.08:18:02.59#ibcon#read 3, iclass 39, count 0 2006.238.08:18:02.59#ibcon#about to read 4, iclass 39, count 0 2006.238.08:18:02.59#ibcon#read 4, iclass 39, count 0 2006.238.08:18:02.59#ibcon#about to read 5, iclass 39, count 0 2006.238.08:18:02.59#ibcon#read 5, iclass 39, count 0 2006.238.08:18:02.59#ibcon#about to read 6, iclass 39, count 0 2006.238.08:18:02.59#ibcon#read 6, iclass 39, count 0 2006.238.08:18:02.59#ibcon#end of sib2, iclass 39, count 0 2006.238.08:18:02.59#ibcon#*after write, iclass 39, count 0 2006.238.08:18:02.59#ibcon#*before return 0, iclass 39, count 0 2006.238.08:18:02.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:18:02.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.238.08:18:02.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.08:18:02.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.08:18:02.59$vc4f8/vabw=wide 2006.238.08:18:02.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.238.08:18:02.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.238.08:18:02.59#ibcon#ireg 8 cls_cnt 0 2006.238.08:18:02.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:18:02.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:18:02.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:18:02.59#ibcon#enter wrdev, iclass 3, count 0 2006.238.08:18:02.59#ibcon#first serial, iclass 3, count 0 2006.238.08:18:02.59#ibcon#enter sib2, iclass 3, count 0 2006.238.08:18:02.59#ibcon#flushed, iclass 3, count 0 2006.238.08:18:02.59#ibcon#about to write, iclass 3, count 0 2006.238.08:18:02.59#ibcon#wrote, iclass 3, count 0 2006.238.08:18:02.59#ibcon#about to read 3, iclass 3, count 0 2006.238.08:18:02.61#ibcon#read 3, iclass 3, count 0 2006.238.08:18:02.61#ibcon#about to read 4, iclass 3, count 0 2006.238.08:18:02.61#ibcon#read 4, iclass 3, count 0 2006.238.08:18:02.61#ibcon#about to read 5, iclass 3, count 0 2006.238.08:18:02.61#ibcon#read 5, iclass 3, count 0 2006.238.08:18:02.61#ibcon#about to read 6, iclass 3, count 0 2006.238.08:18:02.61#ibcon#read 6, iclass 3, count 0 2006.238.08:18:02.61#ibcon#end of sib2, iclass 3, count 0 2006.238.08:18:02.61#ibcon#*mode == 0, iclass 3, count 0 2006.238.08:18:02.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.08:18:02.61#ibcon#[25=BW32\r\n] 2006.238.08:18:02.61#ibcon#*before write, iclass 3, count 0 2006.238.08:18:02.61#ibcon#enter sib2, iclass 3, count 0 2006.238.08:18:02.61#ibcon#flushed, iclass 3, count 0 2006.238.08:18:02.61#ibcon#about to write, iclass 3, count 0 2006.238.08:18:02.61#ibcon#wrote, iclass 3, count 0 2006.238.08:18:02.61#ibcon#about to read 3, iclass 3, count 0 2006.238.08:18:02.64#ibcon#read 3, iclass 3, count 0 2006.238.08:18:02.64#ibcon#about to read 4, iclass 3, count 0 2006.238.08:18:02.64#ibcon#read 4, iclass 3, count 0 2006.238.08:18:02.64#ibcon#about to read 5, iclass 3, count 0 2006.238.08:18:02.64#ibcon#read 5, iclass 3, count 0 2006.238.08:18:02.64#ibcon#about to read 6, iclass 3, count 0 2006.238.08:18:02.64#ibcon#read 6, iclass 3, count 0 2006.238.08:18:02.64#ibcon#end of sib2, iclass 3, count 0 2006.238.08:18:02.64#ibcon#*after write, iclass 3, count 0 2006.238.08:18:02.64#ibcon#*before return 0, iclass 3, count 0 2006.238.08:18:02.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:18:02.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.238.08:18:02.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.08:18:02.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.08:18:02.64$vc4f8/vbbw=wide 2006.238.08:18:02.64#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.08:18:02.64#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.08:18:02.64#ibcon#ireg 8 cls_cnt 0 2006.238.08:18:02.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:18:02.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:18:02.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:18:02.71#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:18:02.71#ibcon#first serial, iclass 5, count 0 2006.238.08:18:02.71#ibcon#enter sib2, iclass 5, count 0 2006.238.08:18:02.71#ibcon#flushed, iclass 5, count 0 2006.238.08:18:02.71#ibcon#about to write, iclass 5, count 0 2006.238.08:18:02.71#ibcon#wrote, iclass 5, count 0 2006.238.08:18:02.71#ibcon#about to read 3, iclass 5, count 0 2006.238.08:18:02.73#ibcon#read 3, iclass 5, count 0 2006.238.08:18:02.73#ibcon#about to read 4, iclass 5, count 0 2006.238.08:18:02.73#ibcon#read 4, iclass 5, count 0 2006.238.08:18:02.73#ibcon#about to read 5, iclass 5, count 0 2006.238.08:18:02.73#ibcon#read 5, iclass 5, count 0 2006.238.08:18:02.73#ibcon#about to read 6, iclass 5, count 0 2006.238.08:18:02.73#ibcon#read 6, iclass 5, count 0 2006.238.08:18:02.73#ibcon#end of sib2, iclass 5, count 0 2006.238.08:18:02.73#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:18:02.73#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:18:02.73#ibcon#[27=BW32\r\n] 2006.238.08:18:02.73#ibcon#*before write, iclass 5, count 0 2006.238.08:18:02.73#ibcon#enter sib2, iclass 5, count 0 2006.238.08:18:02.73#ibcon#flushed, iclass 5, count 0 2006.238.08:18:02.73#ibcon#about to write, iclass 5, count 0 2006.238.08:18:02.73#ibcon#wrote, iclass 5, count 0 2006.238.08:18:02.73#ibcon#about to read 3, iclass 5, count 0 2006.238.08:18:02.76#ibcon#read 3, iclass 5, count 0 2006.238.08:18:02.76#ibcon#about to read 4, iclass 5, count 0 2006.238.08:18:02.76#ibcon#read 4, iclass 5, count 0 2006.238.08:18:02.76#ibcon#about to read 5, iclass 5, count 0 2006.238.08:18:02.76#ibcon#read 5, iclass 5, count 0 2006.238.08:18:02.76#ibcon#about to read 6, iclass 5, count 0 2006.238.08:18:02.76#ibcon#read 6, iclass 5, count 0 2006.238.08:18:02.76#ibcon#end of sib2, iclass 5, count 0 2006.238.08:18:02.76#ibcon#*after write, iclass 5, count 0 2006.238.08:18:02.76#ibcon#*before return 0, iclass 5, count 0 2006.238.08:18:02.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:18:02.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:18:02.76#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:18:02.76#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:18:02.76$4f8m12a/ifd4f 2006.238.08:18:02.76$ifd4f/lo= 2006.238.08:18:02.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:18:02.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:18:02.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:18:02.76$ifd4f/patch= 2006.238.08:18:02.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:18:02.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:18:02.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:18:02.76$4f8m12a/"form=m,16.000,1:2 2006.238.08:18:02.76$4f8m12a/"tpicd 2006.238.08:18:02.76$4f8m12a/echo=off 2006.238.08:18:02.76$4f8m12a/xlog=off 2006.238.08:18:02.76:!2006.238.08:19:40 2006.238.08:18:15.14#trakl#Source acquired 2006.238.08:18:15.14#flagr#flagr/antenna,acquired 2006.238.08:19:40.00:preob 2006.238.08:19:40.14/onsource/TRACKING 2006.238.08:19:40.14:!2006.238.08:19:50 2006.238.08:19:50.00:data_valid=on 2006.238.08:19:50.00:midob 2006.238.08:19:51.14/onsource/TRACKING 2006.238.08:19:51.14/wx/25.45,1012.3,91 2006.238.08:19:51.34/cable/+6.4175E-03 2006.238.08:19:52.43/va/01,08,usb,yes,32,33 2006.238.08:19:52.43/va/02,07,usb,yes,32,33 2006.238.08:19:52.43/va/03,07,usb,yes,30,30 2006.238.08:19:52.43/va/04,07,usb,yes,33,36 2006.238.08:19:52.43/va/05,08,usb,yes,30,31 2006.238.08:19:52.43/va/06,07,usb,yes,32,32 2006.238.08:19:52.43/va/07,07,usb,yes,32,32 2006.238.08:19:52.43/va/08,07,usb,yes,35,35 2006.238.08:19:52.66/valo/01,532.99,yes,locked 2006.238.08:19:52.66/valo/02,572.99,yes,locked 2006.238.08:19:52.66/valo/03,672.99,yes,locked 2006.238.08:19:52.66/valo/04,832.99,yes,locked 2006.238.08:19:52.66/valo/05,652.99,yes,locked 2006.238.08:19:52.66/valo/06,772.99,yes,locked 2006.238.08:19:52.66/valo/07,832.99,yes,locked 2006.238.08:19:52.66/valo/08,852.99,yes,locked 2006.238.08:19:53.75/vb/01,04,usb,yes,30,29 2006.238.08:19:53.75/vb/02,04,usb,yes,32,33 2006.238.08:19:53.75/vb/03,04,usb,yes,28,32 2006.238.08:19:53.75/vb/04,04,usb,yes,29,29 2006.238.08:19:53.75/vb/05,04,usb,yes,28,32 2006.238.08:19:53.75/vb/06,04,usb,yes,29,31 2006.238.08:19:53.75/vb/07,04,usb,yes,31,31 2006.238.08:19:53.75/vb/08,04,usb,yes,28,32 2006.238.08:19:53.98/vblo/01,632.99,yes,locked 2006.238.08:19:53.98/vblo/02,640.99,yes,locked 2006.238.08:19:53.98/vblo/03,656.99,yes,locked 2006.238.08:19:53.98/vblo/04,712.99,yes,locked 2006.238.08:19:53.98/vblo/05,744.99,yes,locked 2006.238.08:19:53.98/vblo/06,752.99,yes,locked 2006.238.08:19:53.98/vblo/07,734.99,yes,locked 2006.238.08:19:53.98/vblo/08,744.99,yes,locked 2006.238.08:19:54.13/vabw/8 2006.238.08:19:54.28/vbbw/8 2006.238.08:19:54.43/xfe/off,on,13.7 2006.238.08:19:54.80/ifatt/23,28,28,28 2006.238.08:19:55.08/fmout-gps/S +4.46E-07 2006.238.08:19:55.12:!2006.238.08:20:50 2006.238.08:20:50.00:data_valid=off 2006.238.08:20:50.00:postob 2006.238.08:20:50.18/cable/+6.4175E-03 2006.238.08:20:50.18/wx/25.44,1012.3,91 2006.238.08:20:51.08/fmout-gps/S +4.45E-07 2006.238.08:20:51.08:scan_name=238-0823,k06238,60 2006.238.08:20:51.09:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.238.08:20:51.14#flagr#flagr/antenna,new-source 2006.238.08:20:52.14:checkk5 2006.238.08:20:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:20:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:20:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:20:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:20:54.02/chk_obsdata//k5ts1/T2380819??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:20:54.39/chk_obsdata//k5ts2/T2380819??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:20:54.76/chk_obsdata//k5ts3/T2380819??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:20:55.14/chk_obsdata//k5ts4/T2380819??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:20:55.83/k5log//k5ts1_log_newline 2006.238.08:20:56.52/k5log//k5ts2_log_newline 2006.238.08:20:57.21/k5log//k5ts3_log_newline 2006.238.08:20:57.91/k5log//k5ts4_log_newline 2006.238.08:20:57.93/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:20:57.93:4f8m12a=3 2006.238.08:20:57.93$4f8m12a/echo=on 2006.238.08:20:57.93$4f8m12a/pcalon 2006.238.08:20:57.93$pcalon/"no phase cal control is implemented here 2006.238.08:20:57.93$4f8m12a/"tpicd=stop 2006.238.08:20:57.93$4f8m12a/vc4f8 2006.238.08:20:57.93$vc4f8/valo=1,532.99 2006.238.08:20:57.93#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.08:20:57.93#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.08:20:57.93#ibcon#ireg 17 cls_cnt 0 2006.238.08:20:57.93#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:20:57.93#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:20:57.93#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:20:57.93#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:20:57.93#ibcon#first serial, iclass 4, count 0 2006.238.08:20:57.93#ibcon#enter sib2, iclass 4, count 0 2006.238.08:20:57.93#ibcon#flushed, iclass 4, count 0 2006.238.08:20:57.93#ibcon#about to write, iclass 4, count 0 2006.238.08:20:57.93#ibcon#wrote, iclass 4, count 0 2006.238.08:20:57.93#ibcon#about to read 3, iclass 4, count 0 2006.238.08:20:57.95#ibcon#read 3, iclass 4, count 0 2006.238.08:20:57.95#ibcon#about to read 4, iclass 4, count 0 2006.238.08:20:57.95#ibcon#read 4, iclass 4, count 0 2006.238.08:20:57.95#ibcon#about to read 5, iclass 4, count 0 2006.238.08:20:57.95#ibcon#read 5, iclass 4, count 0 2006.238.08:20:57.95#ibcon#about to read 6, iclass 4, count 0 2006.238.08:20:57.95#ibcon#read 6, iclass 4, count 0 2006.238.08:20:57.95#ibcon#end of sib2, iclass 4, count 0 2006.238.08:20:57.95#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:20:57.95#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:20:57.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:20:57.95#ibcon#*before write, iclass 4, count 0 2006.238.08:20:57.95#ibcon#enter sib2, iclass 4, count 0 2006.238.08:20:57.95#ibcon#flushed, iclass 4, count 0 2006.238.08:20:57.95#ibcon#about to write, iclass 4, count 0 2006.238.08:20:57.95#ibcon#wrote, iclass 4, count 0 2006.238.08:20:57.95#ibcon#about to read 3, iclass 4, count 0 2006.238.08:20:58.00#ibcon#read 3, iclass 4, count 0 2006.238.08:20:58.00#ibcon#about to read 4, iclass 4, count 0 2006.238.08:20:58.00#ibcon#read 4, iclass 4, count 0 2006.238.08:20:58.00#ibcon#about to read 5, iclass 4, count 0 2006.238.08:20:58.00#ibcon#read 5, iclass 4, count 0 2006.238.08:20:58.00#ibcon#about to read 6, iclass 4, count 0 2006.238.08:20:58.00#ibcon#read 6, iclass 4, count 0 2006.238.08:20:58.00#ibcon#end of sib2, iclass 4, count 0 2006.238.08:20:58.00#ibcon#*after write, iclass 4, count 0 2006.238.08:20:58.00#ibcon#*before return 0, iclass 4, count 0 2006.238.08:20:58.00#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:20:58.00#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:20:58.00#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:20:58.00#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:20:58.00$vc4f8/va=1,8 2006.238.08:20:58.00#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.08:20:58.00#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.08:20:58.00#ibcon#ireg 11 cls_cnt 2 2006.238.08:20:58.00#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:20:58.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:20:58.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:20:58.00#ibcon#enter wrdev, iclass 6, count 2 2006.238.08:20:58.00#ibcon#first serial, iclass 6, count 2 2006.238.08:20:58.00#ibcon#enter sib2, iclass 6, count 2 2006.238.08:20:58.00#ibcon#flushed, iclass 6, count 2 2006.238.08:20:58.00#ibcon#about to write, iclass 6, count 2 2006.238.08:20:58.00#ibcon#wrote, iclass 6, count 2 2006.238.08:20:58.00#ibcon#about to read 3, iclass 6, count 2 2006.238.08:20:58.02#ibcon#read 3, iclass 6, count 2 2006.238.08:20:58.02#ibcon#about to read 4, iclass 6, count 2 2006.238.08:20:58.02#ibcon#read 4, iclass 6, count 2 2006.238.08:20:58.02#ibcon#about to read 5, iclass 6, count 2 2006.238.08:20:58.02#ibcon#read 5, iclass 6, count 2 2006.238.08:20:58.02#ibcon#about to read 6, iclass 6, count 2 2006.238.08:20:58.02#ibcon#read 6, iclass 6, count 2 2006.238.08:20:58.02#ibcon#end of sib2, iclass 6, count 2 2006.238.08:20:58.02#ibcon#*mode == 0, iclass 6, count 2 2006.238.08:20:58.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.08:20:58.02#ibcon#[25=AT01-08\r\n] 2006.238.08:20:58.02#ibcon#*before write, iclass 6, count 2 2006.238.08:20:58.02#ibcon#enter sib2, iclass 6, count 2 2006.238.08:20:58.02#ibcon#flushed, iclass 6, count 2 2006.238.08:20:58.02#ibcon#about to write, iclass 6, count 2 2006.238.08:20:58.02#ibcon#wrote, iclass 6, count 2 2006.238.08:20:58.02#ibcon#about to read 3, iclass 6, count 2 2006.238.08:20:58.05#ibcon#read 3, iclass 6, count 2 2006.238.08:20:58.05#ibcon#about to read 4, iclass 6, count 2 2006.238.08:20:58.05#ibcon#read 4, iclass 6, count 2 2006.238.08:20:58.05#ibcon#about to read 5, iclass 6, count 2 2006.238.08:20:58.05#ibcon#read 5, iclass 6, count 2 2006.238.08:20:58.05#ibcon#about to read 6, iclass 6, count 2 2006.238.08:20:58.05#ibcon#read 6, iclass 6, count 2 2006.238.08:20:58.05#ibcon#end of sib2, iclass 6, count 2 2006.238.08:20:58.05#ibcon#*after write, iclass 6, count 2 2006.238.08:20:58.05#ibcon#*before return 0, iclass 6, count 2 2006.238.08:20:58.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:20:58.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:20:58.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.08:20:58.05#ibcon#ireg 7 cls_cnt 0 2006.238.08:20:58.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:20:58.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:20:58.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:20:58.17#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:20:58.17#ibcon#first serial, iclass 6, count 0 2006.238.08:20:58.17#ibcon#enter sib2, iclass 6, count 0 2006.238.08:20:58.17#ibcon#flushed, iclass 6, count 0 2006.238.08:20:58.17#ibcon#about to write, iclass 6, count 0 2006.238.08:20:58.17#ibcon#wrote, iclass 6, count 0 2006.238.08:20:58.17#ibcon#about to read 3, iclass 6, count 0 2006.238.08:20:58.19#ibcon#read 3, iclass 6, count 0 2006.238.08:20:58.19#ibcon#about to read 4, iclass 6, count 0 2006.238.08:20:58.19#ibcon#read 4, iclass 6, count 0 2006.238.08:20:58.19#ibcon#about to read 5, iclass 6, count 0 2006.238.08:20:58.19#ibcon#read 5, iclass 6, count 0 2006.238.08:20:58.19#ibcon#about to read 6, iclass 6, count 0 2006.238.08:20:58.19#ibcon#read 6, iclass 6, count 0 2006.238.08:20:58.19#ibcon#end of sib2, iclass 6, count 0 2006.238.08:20:58.19#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:20:58.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:20:58.19#ibcon#[25=USB\r\n] 2006.238.08:20:58.19#ibcon#*before write, iclass 6, count 0 2006.238.08:20:58.19#ibcon#enter sib2, iclass 6, count 0 2006.238.08:20:58.19#ibcon#flushed, iclass 6, count 0 2006.238.08:20:58.19#ibcon#about to write, iclass 6, count 0 2006.238.08:20:58.19#ibcon#wrote, iclass 6, count 0 2006.238.08:20:58.19#ibcon#about to read 3, iclass 6, count 0 2006.238.08:20:58.22#ibcon#read 3, iclass 6, count 0 2006.238.08:20:58.22#ibcon#about to read 4, iclass 6, count 0 2006.238.08:20:58.22#ibcon#read 4, iclass 6, count 0 2006.238.08:20:58.22#ibcon#about to read 5, iclass 6, count 0 2006.238.08:20:58.22#ibcon#read 5, iclass 6, count 0 2006.238.08:20:58.22#ibcon#about to read 6, iclass 6, count 0 2006.238.08:20:58.22#ibcon#read 6, iclass 6, count 0 2006.238.08:20:58.22#ibcon#end of sib2, iclass 6, count 0 2006.238.08:20:58.22#ibcon#*after write, iclass 6, count 0 2006.238.08:20:58.22#ibcon#*before return 0, iclass 6, count 0 2006.238.08:20:58.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:20:58.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:20:58.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:20:58.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:20:58.22$vc4f8/valo=2,572.99 2006.238.08:20:58.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.08:20:58.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.08:20:58.22#ibcon#ireg 17 cls_cnt 0 2006.238.08:20:58.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:20:58.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:20:58.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:20:58.22#ibcon#enter wrdev, iclass 10, count 0 2006.238.08:20:58.22#ibcon#first serial, iclass 10, count 0 2006.238.08:20:58.22#ibcon#enter sib2, iclass 10, count 0 2006.238.08:20:58.22#ibcon#flushed, iclass 10, count 0 2006.238.08:20:58.22#ibcon#about to write, iclass 10, count 0 2006.238.08:20:58.22#ibcon#wrote, iclass 10, count 0 2006.238.08:20:58.22#ibcon#about to read 3, iclass 10, count 0 2006.238.08:20:58.24#ibcon#read 3, iclass 10, count 0 2006.238.08:20:58.24#ibcon#about to read 4, iclass 10, count 0 2006.238.08:20:58.24#ibcon#read 4, iclass 10, count 0 2006.238.08:20:58.24#ibcon#about to read 5, iclass 10, count 0 2006.238.08:20:58.24#ibcon#read 5, iclass 10, count 0 2006.238.08:20:58.24#ibcon#about to read 6, iclass 10, count 0 2006.238.08:20:58.24#ibcon#read 6, iclass 10, count 0 2006.238.08:20:58.24#ibcon#end of sib2, iclass 10, count 0 2006.238.08:20:58.24#ibcon#*mode == 0, iclass 10, count 0 2006.238.08:20:58.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.08:20:58.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:20:58.24#ibcon#*before write, iclass 10, count 0 2006.238.08:20:58.24#ibcon#enter sib2, iclass 10, count 0 2006.238.08:20:58.24#ibcon#flushed, iclass 10, count 0 2006.238.08:20:58.24#ibcon#about to write, iclass 10, count 0 2006.238.08:20:58.24#ibcon#wrote, iclass 10, count 0 2006.238.08:20:58.24#ibcon#about to read 3, iclass 10, count 0 2006.238.08:20:58.28#ibcon#read 3, iclass 10, count 0 2006.238.08:20:58.28#ibcon#about to read 4, iclass 10, count 0 2006.238.08:20:58.28#ibcon#read 4, iclass 10, count 0 2006.238.08:20:58.28#ibcon#about to read 5, iclass 10, count 0 2006.238.08:20:58.28#ibcon#read 5, iclass 10, count 0 2006.238.08:20:58.28#ibcon#about to read 6, iclass 10, count 0 2006.238.08:20:58.28#ibcon#read 6, iclass 10, count 0 2006.238.08:20:58.28#ibcon#end of sib2, iclass 10, count 0 2006.238.08:20:58.28#ibcon#*after write, iclass 10, count 0 2006.238.08:20:58.28#ibcon#*before return 0, iclass 10, count 0 2006.238.08:20:58.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:20:58.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:20:58.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.08:20:58.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.08:20:58.28$vc4f8/va=2,7 2006.238.08:20:58.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.238.08:20:58.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.238.08:20:58.28#ibcon#ireg 11 cls_cnt 2 2006.238.08:20:58.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:20:58.33#abcon#<5=/04 1.5 2.6 25.44 911012.3\r\n> 2006.238.08:20:58.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:20:58.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:20:58.34#ibcon#enter wrdev, iclass 12, count 2 2006.238.08:20:58.34#ibcon#first serial, iclass 12, count 2 2006.238.08:20:58.34#ibcon#enter sib2, iclass 12, count 2 2006.238.08:20:58.34#ibcon#flushed, iclass 12, count 2 2006.238.08:20:58.34#ibcon#about to write, iclass 12, count 2 2006.238.08:20:58.34#ibcon#wrote, iclass 12, count 2 2006.238.08:20:58.34#ibcon#about to read 3, iclass 12, count 2 2006.238.08:20:58.36#abcon#{5=INTERFACE CLEAR} 2006.238.08:20:58.36#ibcon#read 3, iclass 12, count 2 2006.238.08:20:58.36#ibcon#about to read 4, iclass 12, count 2 2006.238.08:20:58.36#ibcon#read 4, iclass 12, count 2 2006.238.08:20:58.36#ibcon#about to read 5, iclass 12, count 2 2006.238.08:20:58.36#ibcon#read 5, iclass 12, count 2 2006.238.08:20:58.36#ibcon#about to read 6, iclass 12, count 2 2006.238.08:20:58.36#ibcon#read 6, iclass 12, count 2 2006.238.08:20:58.36#ibcon#end of sib2, iclass 12, count 2 2006.238.08:20:58.36#ibcon#*mode == 0, iclass 12, count 2 2006.238.08:20:58.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.238.08:20:58.36#ibcon#[25=AT02-07\r\n] 2006.238.08:20:58.36#ibcon#*before write, iclass 12, count 2 2006.238.08:20:58.36#ibcon#enter sib2, iclass 12, count 2 2006.238.08:20:58.36#ibcon#flushed, iclass 12, count 2 2006.238.08:20:58.36#ibcon#about to write, iclass 12, count 2 2006.238.08:20:58.36#ibcon#wrote, iclass 12, count 2 2006.238.08:20:58.36#ibcon#about to read 3, iclass 12, count 2 2006.238.08:20:58.39#ibcon#read 3, iclass 12, count 2 2006.238.08:20:58.39#ibcon#about to read 4, iclass 12, count 2 2006.238.08:20:58.39#ibcon#read 4, iclass 12, count 2 2006.238.08:20:58.39#ibcon#about to read 5, iclass 12, count 2 2006.238.08:20:58.39#ibcon#read 5, iclass 12, count 2 2006.238.08:20:58.39#ibcon#about to read 6, iclass 12, count 2 2006.238.08:20:58.39#ibcon#read 6, iclass 12, count 2 2006.238.08:20:58.39#ibcon#end of sib2, iclass 12, count 2 2006.238.08:20:58.39#ibcon#*after write, iclass 12, count 2 2006.238.08:20:58.39#ibcon#*before return 0, iclass 12, count 2 2006.238.08:20:58.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:20:58.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:20:58.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.238.08:20:58.39#ibcon#ireg 7 cls_cnt 0 2006.238.08:20:58.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:20:58.41#abcon#[5=S1D000X0/0*\r\n] 2006.238.08:20:58.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:20:58.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:20:58.51#ibcon#enter wrdev, iclass 12, count 0 2006.238.08:20:58.51#ibcon#first serial, iclass 12, count 0 2006.238.08:20:58.51#ibcon#enter sib2, iclass 12, count 0 2006.238.08:20:58.51#ibcon#flushed, iclass 12, count 0 2006.238.08:20:58.51#ibcon#about to write, iclass 12, count 0 2006.238.08:20:58.51#ibcon#wrote, iclass 12, count 0 2006.238.08:20:58.51#ibcon#about to read 3, iclass 12, count 0 2006.238.08:20:58.53#ibcon#read 3, iclass 12, count 0 2006.238.08:20:58.53#ibcon#about to read 4, iclass 12, count 0 2006.238.08:20:58.53#ibcon#read 4, iclass 12, count 0 2006.238.08:20:58.53#ibcon#about to read 5, iclass 12, count 0 2006.238.08:20:58.53#ibcon#read 5, iclass 12, count 0 2006.238.08:20:58.53#ibcon#about to read 6, iclass 12, count 0 2006.238.08:20:58.53#ibcon#read 6, iclass 12, count 0 2006.238.08:20:58.53#ibcon#end of sib2, iclass 12, count 0 2006.238.08:20:58.53#ibcon#*mode == 0, iclass 12, count 0 2006.238.08:20:58.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.08:20:58.53#ibcon#[25=USB\r\n] 2006.238.08:20:58.53#ibcon#*before write, iclass 12, count 0 2006.238.08:20:58.53#ibcon#enter sib2, iclass 12, count 0 2006.238.08:20:58.53#ibcon#flushed, iclass 12, count 0 2006.238.08:20:58.53#ibcon#about to write, iclass 12, count 0 2006.238.08:20:58.53#ibcon#wrote, iclass 12, count 0 2006.238.08:20:58.53#ibcon#about to read 3, iclass 12, count 0 2006.238.08:20:58.56#ibcon#read 3, iclass 12, count 0 2006.238.08:20:58.56#ibcon#about to read 4, iclass 12, count 0 2006.238.08:20:58.56#ibcon#read 4, iclass 12, count 0 2006.238.08:20:58.56#ibcon#about to read 5, iclass 12, count 0 2006.238.08:20:58.56#ibcon#read 5, iclass 12, count 0 2006.238.08:20:58.56#ibcon#about to read 6, iclass 12, count 0 2006.238.08:20:58.56#ibcon#read 6, iclass 12, count 0 2006.238.08:20:58.56#ibcon#end of sib2, iclass 12, count 0 2006.238.08:20:58.56#ibcon#*after write, iclass 12, count 0 2006.238.08:20:58.56#ibcon#*before return 0, iclass 12, count 0 2006.238.08:20:58.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:20:58.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:20:58.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.08:20:58.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.08:20:58.56$vc4f8/valo=3,672.99 2006.238.08:20:58.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.08:20:58.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.08:20:58.56#ibcon#ireg 17 cls_cnt 0 2006.238.08:20:58.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:20:58.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:20:58.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:20:58.56#ibcon#enter wrdev, iclass 18, count 0 2006.238.08:20:58.56#ibcon#first serial, iclass 18, count 0 2006.238.08:20:58.56#ibcon#enter sib2, iclass 18, count 0 2006.238.08:20:58.56#ibcon#flushed, iclass 18, count 0 2006.238.08:20:58.56#ibcon#about to write, iclass 18, count 0 2006.238.08:20:58.56#ibcon#wrote, iclass 18, count 0 2006.238.08:20:58.56#ibcon#about to read 3, iclass 18, count 0 2006.238.08:20:58.58#ibcon#read 3, iclass 18, count 0 2006.238.08:20:58.58#ibcon#about to read 4, iclass 18, count 0 2006.238.08:20:58.58#ibcon#read 4, iclass 18, count 0 2006.238.08:20:58.58#ibcon#about to read 5, iclass 18, count 0 2006.238.08:20:58.58#ibcon#read 5, iclass 18, count 0 2006.238.08:20:58.58#ibcon#about to read 6, iclass 18, count 0 2006.238.08:20:58.58#ibcon#read 6, iclass 18, count 0 2006.238.08:20:58.58#ibcon#end of sib2, iclass 18, count 0 2006.238.08:20:58.58#ibcon#*mode == 0, iclass 18, count 0 2006.238.08:20:58.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.08:20:58.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:20:58.58#ibcon#*before write, iclass 18, count 0 2006.238.08:20:58.58#ibcon#enter sib2, iclass 18, count 0 2006.238.08:20:58.58#ibcon#flushed, iclass 18, count 0 2006.238.08:20:58.58#ibcon#about to write, iclass 18, count 0 2006.238.08:20:58.58#ibcon#wrote, iclass 18, count 0 2006.238.08:20:58.58#ibcon#about to read 3, iclass 18, count 0 2006.238.08:20:58.62#ibcon#read 3, iclass 18, count 0 2006.238.08:20:58.62#ibcon#about to read 4, iclass 18, count 0 2006.238.08:20:58.62#ibcon#read 4, iclass 18, count 0 2006.238.08:20:58.62#ibcon#about to read 5, iclass 18, count 0 2006.238.08:20:58.62#ibcon#read 5, iclass 18, count 0 2006.238.08:20:58.62#ibcon#about to read 6, iclass 18, count 0 2006.238.08:20:58.62#ibcon#read 6, iclass 18, count 0 2006.238.08:20:58.62#ibcon#end of sib2, iclass 18, count 0 2006.238.08:20:58.62#ibcon#*after write, iclass 18, count 0 2006.238.08:20:58.62#ibcon#*before return 0, iclass 18, count 0 2006.238.08:20:58.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:20:58.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:20:58.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.08:20:58.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.08:20:58.62$vc4f8/va=3,7 2006.238.08:20:58.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.238.08:20:58.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.238.08:20:58.62#ibcon#ireg 11 cls_cnt 2 2006.238.08:20:58.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:20:58.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:20:58.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:20:58.68#ibcon#enter wrdev, iclass 20, count 2 2006.238.08:20:58.68#ibcon#first serial, iclass 20, count 2 2006.238.08:20:58.68#ibcon#enter sib2, iclass 20, count 2 2006.238.08:20:58.68#ibcon#flushed, iclass 20, count 2 2006.238.08:20:58.68#ibcon#about to write, iclass 20, count 2 2006.238.08:20:58.68#ibcon#wrote, iclass 20, count 2 2006.238.08:20:58.68#ibcon#about to read 3, iclass 20, count 2 2006.238.08:20:58.70#ibcon#read 3, iclass 20, count 2 2006.238.08:20:58.70#ibcon#about to read 4, iclass 20, count 2 2006.238.08:20:58.70#ibcon#read 4, iclass 20, count 2 2006.238.08:20:58.70#ibcon#about to read 5, iclass 20, count 2 2006.238.08:20:58.70#ibcon#read 5, iclass 20, count 2 2006.238.08:20:58.70#ibcon#about to read 6, iclass 20, count 2 2006.238.08:20:58.70#ibcon#read 6, iclass 20, count 2 2006.238.08:20:58.70#ibcon#end of sib2, iclass 20, count 2 2006.238.08:20:58.70#ibcon#*mode == 0, iclass 20, count 2 2006.238.08:20:58.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.238.08:20:58.70#ibcon#[25=AT03-07\r\n] 2006.238.08:20:58.70#ibcon#*before write, iclass 20, count 2 2006.238.08:20:58.70#ibcon#enter sib2, iclass 20, count 2 2006.238.08:20:58.70#ibcon#flushed, iclass 20, count 2 2006.238.08:20:58.70#ibcon#about to write, iclass 20, count 2 2006.238.08:20:58.70#ibcon#wrote, iclass 20, count 2 2006.238.08:20:58.70#ibcon#about to read 3, iclass 20, count 2 2006.238.08:20:58.73#ibcon#read 3, iclass 20, count 2 2006.238.08:20:58.73#ibcon#about to read 4, iclass 20, count 2 2006.238.08:20:58.73#ibcon#read 4, iclass 20, count 2 2006.238.08:20:58.73#ibcon#about to read 5, iclass 20, count 2 2006.238.08:20:58.73#ibcon#read 5, iclass 20, count 2 2006.238.08:20:58.73#ibcon#about to read 6, iclass 20, count 2 2006.238.08:20:58.73#ibcon#read 6, iclass 20, count 2 2006.238.08:20:58.73#ibcon#end of sib2, iclass 20, count 2 2006.238.08:20:58.73#ibcon#*after write, iclass 20, count 2 2006.238.08:20:58.73#ibcon#*before return 0, iclass 20, count 2 2006.238.08:20:58.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:20:58.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:20:58.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.238.08:20:58.73#ibcon#ireg 7 cls_cnt 0 2006.238.08:20:58.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:20:58.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:20:58.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:20:58.85#ibcon#enter wrdev, iclass 20, count 0 2006.238.08:20:58.85#ibcon#first serial, iclass 20, count 0 2006.238.08:20:58.85#ibcon#enter sib2, iclass 20, count 0 2006.238.08:20:58.85#ibcon#flushed, iclass 20, count 0 2006.238.08:20:58.85#ibcon#about to write, iclass 20, count 0 2006.238.08:20:58.85#ibcon#wrote, iclass 20, count 0 2006.238.08:20:58.85#ibcon#about to read 3, iclass 20, count 0 2006.238.08:20:58.87#ibcon#read 3, iclass 20, count 0 2006.238.08:20:58.87#ibcon#about to read 4, iclass 20, count 0 2006.238.08:20:58.87#ibcon#read 4, iclass 20, count 0 2006.238.08:20:58.87#ibcon#about to read 5, iclass 20, count 0 2006.238.08:20:58.87#ibcon#read 5, iclass 20, count 0 2006.238.08:20:58.87#ibcon#about to read 6, iclass 20, count 0 2006.238.08:20:58.87#ibcon#read 6, iclass 20, count 0 2006.238.08:20:58.87#ibcon#end of sib2, iclass 20, count 0 2006.238.08:20:58.87#ibcon#*mode == 0, iclass 20, count 0 2006.238.08:20:58.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.08:20:58.87#ibcon#[25=USB\r\n] 2006.238.08:20:58.87#ibcon#*before write, iclass 20, count 0 2006.238.08:20:58.87#ibcon#enter sib2, iclass 20, count 0 2006.238.08:20:58.87#ibcon#flushed, iclass 20, count 0 2006.238.08:20:58.87#ibcon#about to write, iclass 20, count 0 2006.238.08:20:58.87#ibcon#wrote, iclass 20, count 0 2006.238.08:20:58.87#ibcon#about to read 3, iclass 20, count 0 2006.238.08:20:58.90#ibcon#read 3, iclass 20, count 0 2006.238.08:20:58.90#ibcon#about to read 4, iclass 20, count 0 2006.238.08:20:58.90#ibcon#read 4, iclass 20, count 0 2006.238.08:20:58.90#ibcon#about to read 5, iclass 20, count 0 2006.238.08:20:58.90#ibcon#read 5, iclass 20, count 0 2006.238.08:20:58.90#ibcon#about to read 6, iclass 20, count 0 2006.238.08:20:58.90#ibcon#read 6, iclass 20, count 0 2006.238.08:20:58.90#ibcon#end of sib2, iclass 20, count 0 2006.238.08:20:58.90#ibcon#*after write, iclass 20, count 0 2006.238.08:20:58.90#ibcon#*before return 0, iclass 20, count 0 2006.238.08:20:58.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:20:58.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:20:58.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.08:20:58.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.08:20:58.90$vc4f8/valo=4,832.99 2006.238.08:20:58.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.08:20:58.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.08:20:58.90#ibcon#ireg 17 cls_cnt 0 2006.238.08:20:58.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:20:58.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:20:58.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:20:58.90#ibcon#enter wrdev, iclass 22, count 0 2006.238.08:20:58.90#ibcon#first serial, iclass 22, count 0 2006.238.08:20:58.90#ibcon#enter sib2, iclass 22, count 0 2006.238.08:20:58.90#ibcon#flushed, iclass 22, count 0 2006.238.08:20:58.90#ibcon#about to write, iclass 22, count 0 2006.238.08:20:58.90#ibcon#wrote, iclass 22, count 0 2006.238.08:20:58.90#ibcon#about to read 3, iclass 22, count 0 2006.238.08:20:58.92#ibcon#read 3, iclass 22, count 0 2006.238.08:20:58.92#ibcon#about to read 4, iclass 22, count 0 2006.238.08:20:58.92#ibcon#read 4, iclass 22, count 0 2006.238.08:20:58.92#ibcon#about to read 5, iclass 22, count 0 2006.238.08:20:58.92#ibcon#read 5, iclass 22, count 0 2006.238.08:20:58.92#ibcon#about to read 6, iclass 22, count 0 2006.238.08:20:58.92#ibcon#read 6, iclass 22, count 0 2006.238.08:20:58.92#ibcon#end of sib2, iclass 22, count 0 2006.238.08:20:58.92#ibcon#*mode == 0, iclass 22, count 0 2006.238.08:20:58.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.08:20:58.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:20:58.92#ibcon#*before write, iclass 22, count 0 2006.238.08:20:58.92#ibcon#enter sib2, iclass 22, count 0 2006.238.08:20:58.92#ibcon#flushed, iclass 22, count 0 2006.238.08:20:58.92#ibcon#about to write, iclass 22, count 0 2006.238.08:20:58.92#ibcon#wrote, iclass 22, count 0 2006.238.08:20:58.92#ibcon#about to read 3, iclass 22, count 0 2006.238.08:20:58.96#ibcon#read 3, iclass 22, count 0 2006.238.08:20:58.96#ibcon#about to read 4, iclass 22, count 0 2006.238.08:20:58.96#ibcon#read 4, iclass 22, count 0 2006.238.08:20:58.96#ibcon#about to read 5, iclass 22, count 0 2006.238.08:20:58.96#ibcon#read 5, iclass 22, count 0 2006.238.08:20:58.96#ibcon#about to read 6, iclass 22, count 0 2006.238.08:20:58.96#ibcon#read 6, iclass 22, count 0 2006.238.08:20:58.96#ibcon#end of sib2, iclass 22, count 0 2006.238.08:20:58.96#ibcon#*after write, iclass 22, count 0 2006.238.08:20:58.96#ibcon#*before return 0, iclass 22, count 0 2006.238.08:20:58.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:20:58.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:20:58.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.08:20:58.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.08:20:58.96$vc4f8/va=4,7 2006.238.08:20:58.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.238.08:20:58.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.238.08:20:58.96#ibcon#ireg 11 cls_cnt 2 2006.238.08:20:58.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:20:59.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:20:59.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:20:59.02#ibcon#enter wrdev, iclass 24, count 2 2006.238.08:20:59.02#ibcon#first serial, iclass 24, count 2 2006.238.08:20:59.02#ibcon#enter sib2, iclass 24, count 2 2006.238.08:20:59.02#ibcon#flushed, iclass 24, count 2 2006.238.08:20:59.02#ibcon#about to write, iclass 24, count 2 2006.238.08:20:59.02#ibcon#wrote, iclass 24, count 2 2006.238.08:20:59.02#ibcon#about to read 3, iclass 24, count 2 2006.238.08:20:59.04#ibcon#read 3, iclass 24, count 2 2006.238.08:20:59.04#ibcon#about to read 4, iclass 24, count 2 2006.238.08:20:59.04#ibcon#read 4, iclass 24, count 2 2006.238.08:20:59.04#ibcon#about to read 5, iclass 24, count 2 2006.238.08:20:59.04#ibcon#read 5, iclass 24, count 2 2006.238.08:20:59.04#ibcon#about to read 6, iclass 24, count 2 2006.238.08:20:59.04#ibcon#read 6, iclass 24, count 2 2006.238.08:20:59.04#ibcon#end of sib2, iclass 24, count 2 2006.238.08:20:59.04#ibcon#*mode == 0, iclass 24, count 2 2006.238.08:20:59.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.238.08:20:59.04#ibcon#[25=AT04-07\r\n] 2006.238.08:20:59.04#ibcon#*before write, iclass 24, count 2 2006.238.08:20:59.04#ibcon#enter sib2, iclass 24, count 2 2006.238.08:20:59.04#ibcon#flushed, iclass 24, count 2 2006.238.08:20:59.04#ibcon#about to write, iclass 24, count 2 2006.238.08:20:59.04#ibcon#wrote, iclass 24, count 2 2006.238.08:20:59.04#ibcon#about to read 3, iclass 24, count 2 2006.238.08:20:59.07#ibcon#read 3, iclass 24, count 2 2006.238.08:20:59.07#ibcon#about to read 4, iclass 24, count 2 2006.238.08:20:59.07#ibcon#read 4, iclass 24, count 2 2006.238.08:20:59.07#ibcon#about to read 5, iclass 24, count 2 2006.238.08:20:59.07#ibcon#read 5, iclass 24, count 2 2006.238.08:20:59.07#ibcon#about to read 6, iclass 24, count 2 2006.238.08:20:59.07#ibcon#read 6, iclass 24, count 2 2006.238.08:20:59.07#ibcon#end of sib2, iclass 24, count 2 2006.238.08:20:59.07#ibcon#*after write, iclass 24, count 2 2006.238.08:20:59.07#ibcon#*before return 0, iclass 24, count 2 2006.238.08:20:59.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:20:59.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:20:59.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.238.08:20:59.07#ibcon#ireg 7 cls_cnt 0 2006.238.08:20:59.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:20:59.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:20:59.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:20:59.19#ibcon#enter wrdev, iclass 24, count 0 2006.238.08:20:59.19#ibcon#first serial, iclass 24, count 0 2006.238.08:20:59.19#ibcon#enter sib2, iclass 24, count 0 2006.238.08:20:59.19#ibcon#flushed, iclass 24, count 0 2006.238.08:20:59.19#ibcon#about to write, iclass 24, count 0 2006.238.08:20:59.19#ibcon#wrote, iclass 24, count 0 2006.238.08:20:59.19#ibcon#about to read 3, iclass 24, count 0 2006.238.08:20:59.21#ibcon#read 3, iclass 24, count 0 2006.238.08:20:59.21#ibcon#about to read 4, iclass 24, count 0 2006.238.08:20:59.21#ibcon#read 4, iclass 24, count 0 2006.238.08:20:59.21#ibcon#about to read 5, iclass 24, count 0 2006.238.08:20:59.21#ibcon#read 5, iclass 24, count 0 2006.238.08:20:59.21#ibcon#about to read 6, iclass 24, count 0 2006.238.08:20:59.21#ibcon#read 6, iclass 24, count 0 2006.238.08:20:59.21#ibcon#end of sib2, iclass 24, count 0 2006.238.08:20:59.21#ibcon#*mode == 0, iclass 24, count 0 2006.238.08:20:59.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.08:20:59.21#ibcon#[25=USB\r\n] 2006.238.08:20:59.21#ibcon#*before write, iclass 24, count 0 2006.238.08:20:59.21#ibcon#enter sib2, iclass 24, count 0 2006.238.08:20:59.21#ibcon#flushed, iclass 24, count 0 2006.238.08:20:59.21#ibcon#about to write, iclass 24, count 0 2006.238.08:20:59.21#ibcon#wrote, iclass 24, count 0 2006.238.08:20:59.21#ibcon#about to read 3, iclass 24, count 0 2006.238.08:20:59.24#ibcon#read 3, iclass 24, count 0 2006.238.08:20:59.24#ibcon#about to read 4, iclass 24, count 0 2006.238.08:20:59.24#ibcon#read 4, iclass 24, count 0 2006.238.08:20:59.24#ibcon#about to read 5, iclass 24, count 0 2006.238.08:20:59.24#ibcon#read 5, iclass 24, count 0 2006.238.08:20:59.24#ibcon#about to read 6, iclass 24, count 0 2006.238.08:20:59.24#ibcon#read 6, iclass 24, count 0 2006.238.08:20:59.24#ibcon#end of sib2, iclass 24, count 0 2006.238.08:20:59.24#ibcon#*after write, iclass 24, count 0 2006.238.08:20:59.24#ibcon#*before return 0, iclass 24, count 0 2006.238.08:20:59.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:20:59.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:20:59.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.08:20:59.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.08:20:59.24$vc4f8/valo=5,652.99 2006.238.08:20:59.24#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.08:20:59.24#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.08:20:59.24#ibcon#ireg 17 cls_cnt 0 2006.238.08:20:59.24#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:20:59.24#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:20:59.24#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:20:59.24#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:20:59.24#ibcon#first serial, iclass 26, count 0 2006.238.08:20:59.24#ibcon#enter sib2, iclass 26, count 0 2006.238.08:20:59.24#ibcon#flushed, iclass 26, count 0 2006.238.08:20:59.24#ibcon#about to write, iclass 26, count 0 2006.238.08:20:59.24#ibcon#wrote, iclass 26, count 0 2006.238.08:20:59.24#ibcon#about to read 3, iclass 26, count 0 2006.238.08:20:59.26#ibcon#read 3, iclass 26, count 0 2006.238.08:20:59.26#ibcon#about to read 4, iclass 26, count 0 2006.238.08:20:59.26#ibcon#read 4, iclass 26, count 0 2006.238.08:20:59.26#ibcon#about to read 5, iclass 26, count 0 2006.238.08:20:59.26#ibcon#read 5, iclass 26, count 0 2006.238.08:20:59.26#ibcon#about to read 6, iclass 26, count 0 2006.238.08:20:59.26#ibcon#read 6, iclass 26, count 0 2006.238.08:20:59.26#ibcon#end of sib2, iclass 26, count 0 2006.238.08:20:59.26#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:20:59.26#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:20:59.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:20:59.26#ibcon#*before write, iclass 26, count 0 2006.238.08:20:59.26#ibcon#enter sib2, iclass 26, count 0 2006.238.08:20:59.26#ibcon#flushed, iclass 26, count 0 2006.238.08:20:59.26#ibcon#about to write, iclass 26, count 0 2006.238.08:20:59.26#ibcon#wrote, iclass 26, count 0 2006.238.08:20:59.26#ibcon#about to read 3, iclass 26, count 0 2006.238.08:20:59.30#ibcon#read 3, iclass 26, count 0 2006.238.08:20:59.30#ibcon#about to read 4, iclass 26, count 0 2006.238.08:20:59.30#ibcon#read 4, iclass 26, count 0 2006.238.08:20:59.30#ibcon#about to read 5, iclass 26, count 0 2006.238.08:20:59.30#ibcon#read 5, iclass 26, count 0 2006.238.08:20:59.30#ibcon#about to read 6, iclass 26, count 0 2006.238.08:20:59.30#ibcon#read 6, iclass 26, count 0 2006.238.08:20:59.30#ibcon#end of sib2, iclass 26, count 0 2006.238.08:20:59.30#ibcon#*after write, iclass 26, count 0 2006.238.08:20:59.30#ibcon#*before return 0, iclass 26, count 0 2006.238.08:20:59.30#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:20:59.30#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:20:59.30#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:20:59.30#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:20:59.30$vc4f8/va=5,8 2006.238.08:20:59.30#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.08:20:59.30#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.08:20:59.30#ibcon#ireg 11 cls_cnt 2 2006.238.08:20:59.30#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:20:59.36#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:20:59.36#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:20:59.36#ibcon#enter wrdev, iclass 28, count 2 2006.238.08:20:59.36#ibcon#first serial, iclass 28, count 2 2006.238.08:20:59.36#ibcon#enter sib2, iclass 28, count 2 2006.238.08:20:59.36#ibcon#flushed, iclass 28, count 2 2006.238.08:20:59.36#ibcon#about to write, iclass 28, count 2 2006.238.08:20:59.36#ibcon#wrote, iclass 28, count 2 2006.238.08:20:59.36#ibcon#about to read 3, iclass 28, count 2 2006.238.08:20:59.38#ibcon#read 3, iclass 28, count 2 2006.238.08:20:59.38#ibcon#about to read 4, iclass 28, count 2 2006.238.08:20:59.38#ibcon#read 4, iclass 28, count 2 2006.238.08:20:59.38#ibcon#about to read 5, iclass 28, count 2 2006.238.08:20:59.38#ibcon#read 5, iclass 28, count 2 2006.238.08:20:59.38#ibcon#about to read 6, iclass 28, count 2 2006.238.08:20:59.38#ibcon#read 6, iclass 28, count 2 2006.238.08:20:59.38#ibcon#end of sib2, iclass 28, count 2 2006.238.08:20:59.38#ibcon#*mode == 0, iclass 28, count 2 2006.238.08:20:59.38#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.08:20:59.38#ibcon#[25=AT05-08\r\n] 2006.238.08:20:59.38#ibcon#*before write, iclass 28, count 2 2006.238.08:20:59.38#ibcon#enter sib2, iclass 28, count 2 2006.238.08:20:59.38#ibcon#flushed, iclass 28, count 2 2006.238.08:20:59.38#ibcon#about to write, iclass 28, count 2 2006.238.08:20:59.38#ibcon#wrote, iclass 28, count 2 2006.238.08:20:59.38#ibcon#about to read 3, iclass 28, count 2 2006.238.08:20:59.41#ibcon#read 3, iclass 28, count 2 2006.238.08:20:59.41#ibcon#about to read 4, iclass 28, count 2 2006.238.08:20:59.41#ibcon#read 4, iclass 28, count 2 2006.238.08:20:59.41#ibcon#about to read 5, iclass 28, count 2 2006.238.08:20:59.41#ibcon#read 5, iclass 28, count 2 2006.238.08:20:59.41#ibcon#about to read 6, iclass 28, count 2 2006.238.08:20:59.41#ibcon#read 6, iclass 28, count 2 2006.238.08:20:59.41#ibcon#end of sib2, iclass 28, count 2 2006.238.08:20:59.41#ibcon#*after write, iclass 28, count 2 2006.238.08:20:59.41#ibcon#*before return 0, iclass 28, count 2 2006.238.08:20:59.41#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:20:59.41#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:20:59.41#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.08:20:59.41#ibcon#ireg 7 cls_cnt 0 2006.238.08:20:59.41#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:20:59.53#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:20:59.53#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:20:59.53#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:20:59.53#ibcon#first serial, iclass 28, count 0 2006.238.08:20:59.53#ibcon#enter sib2, iclass 28, count 0 2006.238.08:20:59.53#ibcon#flushed, iclass 28, count 0 2006.238.08:20:59.53#ibcon#about to write, iclass 28, count 0 2006.238.08:20:59.53#ibcon#wrote, iclass 28, count 0 2006.238.08:20:59.53#ibcon#about to read 3, iclass 28, count 0 2006.238.08:20:59.55#ibcon#read 3, iclass 28, count 0 2006.238.08:20:59.55#ibcon#about to read 4, iclass 28, count 0 2006.238.08:20:59.55#ibcon#read 4, iclass 28, count 0 2006.238.08:20:59.55#ibcon#about to read 5, iclass 28, count 0 2006.238.08:20:59.55#ibcon#read 5, iclass 28, count 0 2006.238.08:20:59.55#ibcon#about to read 6, iclass 28, count 0 2006.238.08:20:59.55#ibcon#read 6, iclass 28, count 0 2006.238.08:20:59.56#ibcon#end of sib2, iclass 28, count 0 2006.238.08:20:59.56#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:20:59.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:20:59.56#ibcon#[25=USB\r\n] 2006.238.08:20:59.56#ibcon#*before write, iclass 28, count 0 2006.238.08:20:59.56#ibcon#enter sib2, iclass 28, count 0 2006.238.08:20:59.56#ibcon#flushed, iclass 28, count 0 2006.238.08:20:59.56#ibcon#about to write, iclass 28, count 0 2006.238.08:20:59.56#ibcon#wrote, iclass 28, count 0 2006.238.08:20:59.56#ibcon#about to read 3, iclass 28, count 0 2006.238.08:20:59.59#ibcon#read 3, iclass 28, count 0 2006.238.08:20:59.59#ibcon#about to read 4, iclass 28, count 0 2006.238.08:20:59.59#ibcon#read 4, iclass 28, count 0 2006.238.08:20:59.59#ibcon#about to read 5, iclass 28, count 0 2006.238.08:20:59.59#ibcon#read 5, iclass 28, count 0 2006.238.08:20:59.59#ibcon#about to read 6, iclass 28, count 0 2006.238.08:20:59.59#ibcon#read 6, iclass 28, count 0 2006.238.08:20:59.59#ibcon#end of sib2, iclass 28, count 0 2006.238.08:20:59.59#ibcon#*after write, iclass 28, count 0 2006.238.08:20:59.59#ibcon#*before return 0, iclass 28, count 0 2006.238.08:20:59.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:20:59.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:20:59.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:20:59.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:20:59.59$vc4f8/valo=6,772.99 2006.238.08:20:59.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.08:20:59.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.08:20:59.59#ibcon#ireg 17 cls_cnt 0 2006.238.08:20:59.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:20:59.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:20:59.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:20:59.59#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:20:59.59#ibcon#first serial, iclass 30, count 0 2006.238.08:20:59.59#ibcon#enter sib2, iclass 30, count 0 2006.238.08:20:59.59#ibcon#flushed, iclass 30, count 0 2006.238.08:20:59.59#ibcon#about to write, iclass 30, count 0 2006.238.08:20:59.59#ibcon#wrote, iclass 30, count 0 2006.238.08:20:59.59#ibcon#about to read 3, iclass 30, count 0 2006.238.08:20:59.61#ibcon#read 3, iclass 30, count 0 2006.238.08:20:59.61#ibcon#about to read 4, iclass 30, count 0 2006.238.08:20:59.61#ibcon#read 4, iclass 30, count 0 2006.238.08:20:59.61#ibcon#about to read 5, iclass 30, count 0 2006.238.08:20:59.61#ibcon#read 5, iclass 30, count 0 2006.238.08:20:59.61#ibcon#about to read 6, iclass 30, count 0 2006.238.08:20:59.61#ibcon#read 6, iclass 30, count 0 2006.238.08:20:59.61#ibcon#end of sib2, iclass 30, count 0 2006.238.08:20:59.61#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:20:59.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:20:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:20:59.61#ibcon#*before write, iclass 30, count 0 2006.238.08:20:59.61#ibcon#enter sib2, iclass 30, count 0 2006.238.08:20:59.61#ibcon#flushed, iclass 30, count 0 2006.238.08:20:59.61#ibcon#about to write, iclass 30, count 0 2006.238.08:20:59.61#ibcon#wrote, iclass 30, count 0 2006.238.08:20:59.61#ibcon#about to read 3, iclass 30, count 0 2006.238.08:20:59.65#ibcon#read 3, iclass 30, count 0 2006.238.08:20:59.65#ibcon#about to read 4, iclass 30, count 0 2006.238.08:20:59.65#ibcon#read 4, iclass 30, count 0 2006.238.08:20:59.65#ibcon#about to read 5, iclass 30, count 0 2006.238.08:20:59.65#ibcon#read 5, iclass 30, count 0 2006.238.08:20:59.65#ibcon#about to read 6, iclass 30, count 0 2006.238.08:20:59.65#ibcon#read 6, iclass 30, count 0 2006.238.08:20:59.65#ibcon#end of sib2, iclass 30, count 0 2006.238.08:20:59.65#ibcon#*after write, iclass 30, count 0 2006.238.08:20:59.65#ibcon#*before return 0, iclass 30, count 0 2006.238.08:20:59.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:20:59.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:20:59.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:20:59.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:20:59.65$vc4f8/va=6,7 2006.238.08:20:59.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.238.08:20:59.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.238.08:20:59.65#ibcon#ireg 11 cls_cnt 2 2006.238.08:20:59.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:20:59.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:20:59.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:20:59.71#ibcon#enter wrdev, iclass 32, count 2 2006.238.08:20:59.71#ibcon#first serial, iclass 32, count 2 2006.238.08:20:59.71#ibcon#enter sib2, iclass 32, count 2 2006.238.08:20:59.71#ibcon#flushed, iclass 32, count 2 2006.238.08:20:59.71#ibcon#about to write, iclass 32, count 2 2006.238.08:20:59.71#ibcon#wrote, iclass 32, count 2 2006.238.08:20:59.71#ibcon#about to read 3, iclass 32, count 2 2006.238.08:20:59.73#ibcon#read 3, iclass 32, count 2 2006.238.08:20:59.73#ibcon#about to read 4, iclass 32, count 2 2006.238.08:20:59.73#ibcon#read 4, iclass 32, count 2 2006.238.08:20:59.73#ibcon#about to read 5, iclass 32, count 2 2006.238.08:20:59.73#ibcon#read 5, iclass 32, count 2 2006.238.08:20:59.73#ibcon#about to read 6, iclass 32, count 2 2006.238.08:20:59.73#ibcon#read 6, iclass 32, count 2 2006.238.08:20:59.73#ibcon#end of sib2, iclass 32, count 2 2006.238.08:20:59.73#ibcon#*mode == 0, iclass 32, count 2 2006.238.08:20:59.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.238.08:20:59.73#ibcon#[25=AT06-07\r\n] 2006.238.08:20:59.73#ibcon#*before write, iclass 32, count 2 2006.238.08:20:59.73#ibcon#enter sib2, iclass 32, count 2 2006.238.08:20:59.73#ibcon#flushed, iclass 32, count 2 2006.238.08:20:59.73#ibcon#about to write, iclass 32, count 2 2006.238.08:20:59.73#ibcon#wrote, iclass 32, count 2 2006.238.08:20:59.73#ibcon#about to read 3, iclass 32, count 2 2006.238.08:20:59.76#ibcon#read 3, iclass 32, count 2 2006.238.08:20:59.76#ibcon#about to read 4, iclass 32, count 2 2006.238.08:20:59.76#ibcon#read 4, iclass 32, count 2 2006.238.08:20:59.76#ibcon#about to read 5, iclass 32, count 2 2006.238.08:20:59.76#ibcon#read 5, iclass 32, count 2 2006.238.08:20:59.76#ibcon#about to read 6, iclass 32, count 2 2006.238.08:20:59.76#ibcon#read 6, iclass 32, count 2 2006.238.08:20:59.76#ibcon#end of sib2, iclass 32, count 2 2006.238.08:20:59.76#ibcon#*after write, iclass 32, count 2 2006.238.08:20:59.76#ibcon#*before return 0, iclass 32, count 2 2006.238.08:20:59.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:20:59.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.238.08:20:59.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.238.08:20:59.76#ibcon#ireg 7 cls_cnt 0 2006.238.08:20:59.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:20:59.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:20:59.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:20:59.88#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:20:59.88#ibcon#first serial, iclass 32, count 0 2006.238.08:20:59.88#ibcon#enter sib2, iclass 32, count 0 2006.238.08:20:59.88#ibcon#flushed, iclass 32, count 0 2006.238.08:20:59.88#ibcon#about to write, iclass 32, count 0 2006.238.08:20:59.88#ibcon#wrote, iclass 32, count 0 2006.238.08:20:59.88#ibcon#about to read 3, iclass 32, count 0 2006.238.08:20:59.90#ibcon#read 3, iclass 32, count 0 2006.238.08:20:59.90#ibcon#about to read 4, iclass 32, count 0 2006.238.08:20:59.90#ibcon#read 4, iclass 32, count 0 2006.238.08:20:59.90#ibcon#about to read 5, iclass 32, count 0 2006.238.08:20:59.90#ibcon#read 5, iclass 32, count 0 2006.238.08:20:59.90#ibcon#about to read 6, iclass 32, count 0 2006.238.08:20:59.90#ibcon#read 6, iclass 32, count 0 2006.238.08:20:59.90#ibcon#end of sib2, iclass 32, count 0 2006.238.08:20:59.90#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:20:59.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:20:59.90#ibcon#[25=USB\r\n] 2006.238.08:20:59.90#ibcon#*before write, iclass 32, count 0 2006.238.08:20:59.90#ibcon#enter sib2, iclass 32, count 0 2006.238.08:20:59.90#ibcon#flushed, iclass 32, count 0 2006.238.08:20:59.90#ibcon#about to write, iclass 32, count 0 2006.238.08:20:59.90#ibcon#wrote, iclass 32, count 0 2006.238.08:20:59.90#ibcon#about to read 3, iclass 32, count 0 2006.238.08:20:59.93#ibcon#read 3, iclass 32, count 0 2006.238.08:20:59.93#ibcon#about to read 4, iclass 32, count 0 2006.238.08:20:59.93#ibcon#read 4, iclass 32, count 0 2006.238.08:20:59.93#ibcon#about to read 5, iclass 32, count 0 2006.238.08:20:59.93#ibcon#read 5, iclass 32, count 0 2006.238.08:20:59.93#ibcon#about to read 6, iclass 32, count 0 2006.238.08:20:59.93#ibcon#read 6, iclass 32, count 0 2006.238.08:20:59.93#ibcon#end of sib2, iclass 32, count 0 2006.238.08:20:59.93#ibcon#*after write, iclass 32, count 0 2006.238.08:20:59.93#ibcon#*before return 0, iclass 32, count 0 2006.238.08:20:59.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:20:59.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.238.08:20:59.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:20:59.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:20:59.93$vc4f8/valo=7,832.99 2006.238.08:20:59.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.238.08:20:59.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.238.08:20:59.93#ibcon#ireg 17 cls_cnt 0 2006.238.08:20:59.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:20:59.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:20:59.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:20:59.93#ibcon#enter wrdev, iclass 34, count 0 2006.238.08:20:59.93#ibcon#first serial, iclass 34, count 0 2006.238.08:20:59.93#ibcon#enter sib2, iclass 34, count 0 2006.238.08:20:59.93#ibcon#flushed, iclass 34, count 0 2006.238.08:20:59.93#ibcon#about to write, iclass 34, count 0 2006.238.08:20:59.93#ibcon#wrote, iclass 34, count 0 2006.238.08:20:59.93#ibcon#about to read 3, iclass 34, count 0 2006.238.08:20:59.95#ibcon#read 3, iclass 34, count 0 2006.238.08:20:59.95#ibcon#about to read 4, iclass 34, count 0 2006.238.08:20:59.95#ibcon#read 4, iclass 34, count 0 2006.238.08:20:59.95#ibcon#about to read 5, iclass 34, count 0 2006.238.08:20:59.95#ibcon#read 5, iclass 34, count 0 2006.238.08:20:59.95#ibcon#about to read 6, iclass 34, count 0 2006.238.08:20:59.95#ibcon#read 6, iclass 34, count 0 2006.238.08:20:59.95#ibcon#end of sib2, iclass 34, count 0 2006.238.08:20:59.95#ibcon#*mode == 0, iclass 34, count 0 2006.238.08:20:59.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.238.08:20:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:20:59.95#ibcon#*before write, iclass 34, count 0 2006.238.08:20:59.95#ibcon#enter sib2, iclass 34, count 0 2006.238.08:20:59.95#ibcon#flushed, iclass 34, count 0 2006.238.08:20:59.95#ibcon#about to write, iclass 34, count 0 2006.238.08:20:59.95#ibcon#wrote, iclass 34, count 0 2006.238.08:20:59.95#ibcon#about to read 3, iclass 34, count 0 2006.238.08:20:59.99#ibcon#read 3, iclass 34, count 0 2006.238.08:20:59.99#ibcon#about to read 4, iclass 34, count 0 2006.238.08:20:59.99#ibcon#read 4, iclass 34, count 0 2006.238.08:20:59.99#ibcon#about to read 5, iclass 34, count 0 2006.238.08:20:59.99#ibcon#read 5, iclass 34, count 0 2006.238.08:20:59.99#ibcon#about to read 6, iclass 34, count 0 2006.238.08:20:59.99#ibcon#read 6, iclass 34, count 0 2006.238.08:20:59.99#ibcon#end of sib2, iclass 34, count 0 2006.238.08:20:59.99#ibcon#*after write, iclass 34, count 0 2006.238.08:20:59.99#ibcon#*before return 0, iclass 34, count 0 2006.238.08:20:59.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:20:59.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.238.08:20:59.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.238.08:20:59.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.238.08:20:59.99$vc4f8/va=7,7 2006.238.08:20:59.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.238.08:20:59.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.238.08:20:59.99#ibcon#ireg 11 cls_cnt 2 2006.238.08:20:59.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:21:00.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:21:00.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:21:00.05#ibcon#enter wrdev, iclass 36, count 2 2006.238.08:21:00.05#ibcon#first serial, iclass 36, count 2 2006.238.08:21:00.05#ibcon#enter sib2, iclass 36, count 2 2006.238.08:21:00.05#ibcon#flushed, iclass 36, count 2 2006.238.08:21:00.05#ibcon#about to write, iclass 36, count 2 2006.238.08:21:00.05#ibcon#wrote, iclass 36, count 2 2006.238.08:21:00.05#ibcon#about to read 3, iclass 36, count 2 2006.238.08:21:00.07#ibcon#read 3, iclass 36, count 2 2006.238.08:21:00.07#ibcon#about to read 4, iclass 36, count 2 2006.238.08:21:00.07#ibcon#read 4, iclass 36, count 2 2006.238.08:21:00.07#ibcon#about to read 5, iclass 36, count 2 2006.238.08:21:00.07#ibcon#read 5, iclass 36, count 2 2006.238.08:21:00.07#ibcon#about to read 6, iclass 36, count 2 2006.238.08:21:00.07#ibcon#read 6, iclass 36, count 2 2006.238.08:21:00.07#ibcon#end of sib2, iclass 36, count 2 2006.238.08:21:00.07#ibcon#*mode == 0, iclass 36, count 2 2006.238.08:21:00.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.238.08:21:00.07#ibcon#[25=AT07-07\r\n] 2006.238.08:21:00.07#ibcon#*before write, iclass 36, count 2 2006.238.08:21:00.07#ibcon#enter sib2, iclass 36, count 2 2006.238.08:21:00.07#ibcon#flushed, iclass 36, count 2 2006.238.08:21:00.07#ibcon#about to write, iclass 36, count 2 2006.238.08:21:00.07#ibcon#wrote, iclass 36, count 2 2006.238.08:21:00.07#ibcon#about to read 3, iclass 36, count 2 2006.238.08:21:00.10#ibcon#read 3, iclass 36, count 2 2006.238.08:21:00.10#ibcon#about to read 4, iclass 36, count 2 2006.238.08:21:00.10#ibcon#read 4, iclass 36, count 2 2006.238.08:21:00.10#ibcon#about to read 5, iclass 36, count 2 2006.238.08:21:00.10#ibcon#read 5, iclass 36, count 2 2006.238.08:21:00.10#ibcon#about to read 6, iclass 36, count 2 2006.238.08:21:00.10#ibcon#read 6, iclass 36, count 2 2006.238.08:21:00.10#ibcon#end of sib2, iclass 36, count 2 2006.238.08:21:00.10#ibcon#*after write, iclass 36, count 2 2006.238.08:21:00.10#ibcon#*before return 0, iclass 36, count 2 2006.238.08:21:00.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:21:00.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.238.08:21:00.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.238.08:21:00.10#ibcon#ireg 7 cls_cnt 0 2006.238.08:21:00.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:21:00.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:21:00.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:21:00.22#ibcon#enter wrdev, iclass 36, count 0 2006.238.08:21:00.22#ibcon#first serial, iclass 36, count 0 2006.238.08:21:00.22#ibcon#enter sib2, iclass 36, count 0 2006.238.08:21:00.22#ibcon#flushed, iclass 36, count 0 2006.238.08:21:00.22#ibcon#about to write, iclass 36, count 0 2006.238.08:21:00.22#ibcon#wrote, iclass 36, count 0 2006.238.08:21:00.22#ibcon#about to read 3, iclass 36, count 0 2006.238.08:21:00.24#ibcon#read 3, iclass 36, count 0 2006.238.08:21:00.24#ibcon#about to read 4, iclass 36, count 0 2006.238.08:21:00.24#ibcon#read 4, iclass 36, count 0 2006.238.08:21:00.24#ibcon#about to read 5, iclass 36, count 0 2006.238.08:21:00.24#ibcon#read 5, iclass 36, count 0 2006.238.08:21:00.24#ibcon#about to read 6, iclass 36, count 0 2006.238.08:21:00.24#ibcon#read 6, iclass 36, count 0 2006.238.08:21:00.24#ibcon#end of sib2, iclass 36, count 0 2006.238.08:21:00.24#ibcon#*mode == 0, iclass 36, count 0 2006.238.08:21:00.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.238.08:21:00.24#ibcon#[25=USB\r\n] 2006.238.08:21:00.24#ibcon#*before write, iclass 36, count 0 2006.238.08:21:00.24#ibcon#enter sib2, iclass 36, count 0 2006.238.08:21:00.24#ibcon#flushed, iclass 36, count 0 2006.238.08:21:00.24#ibcon#about to write, iclass 36, count 0 2006.238.08:21:00.24#ibcon#wrote, iclass 36, count 0 2006.238.08:21:00.24#ibcon#about to read 3, iclass 36, count 0 2006.238.08:21:00.27#ibcon#read 3, iclass 36, count 0 2006.238.08:21:00.27#ibcon#about to read 4, iclass 36, count 0 2006.238.08:21:00.27#ibcon#read 4, iclass 36, count 0 2006.238.08:21:00.27#ibcon#about to read 5, iclass 36, count 0 2006.238.08:21:00.27#ibcon#read 5, iclass 36, count 0 2006.238.08:21:00.27#ibcon#about to read 6, iclass 36, count 0 2006.238.08:21:00.27#ibcon#read 6, iclass 36, count 0 2006.238.08:21:00.27#ibcon#end of sib2, iclass 36, count 0 2006.238.08:21:00.27#ibcon#*after write, iclass 36, count 0 2006.238.08:21:00.27#ibcon#*before return 0, iclass 36, count 0 2006.238.08:21:00.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:21:00.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.238.08:21:00.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.238.08:21:00.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.238.08:21:00.27$vc4f8/valo=8,852.99 2006.238.08:21:00.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.238.08:21:00.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.238.08:21:00.27#ibcon#ireg 17 cls_cnt 0 2006.238.08:21:00.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:21:00.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:21:00.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:21:00.27#ibcon#enter wrdev, iclass 38, count 0 2006.238.08:21:00.27#ibcon#first serial, iclass 38, count 0 2006.238.08:21:00.27#ibcon#enter sib2, iclass 38, count 0 2006.238.08:21:00.27#ibcon#flushed, iclass 38, count 0 2006.238.08:21:00.27#ibcon#about to write, iclass 38, count 0 2006.238.08:21:00.27#ibcon#wrote, iclass 38, count 0 2006.238.08:21:00.27#ibcon#about to read 3, iclass 38, count 0 2006.238.08:21:00.29#ibcon#read 3, iclass 38, count 0 2006.238.08:21:00.29#ibcon#about to read 4, iclass 38, count 0 2006.238.08:21:00.29#ibcon#read 4, iclass 38, count 0 2006.238.08:21:00.29#ibcon#about to read 5, iclass 38, count 0 2006.238.08:21:00.29#ibcon#read 5, iclass 38, count 0 2006.238.08:21:00.29#ibcon#about to read 6, iclass 38, count 0 2006.238.08:21:00.29#ibcon#read 6, iclass 38, count 0 2006.238.08:21:00.29#ibcon#end of sib2, iclass 38, count 0 2006.238.08:21:00.29#ibcon#*mode == 0, iclass 38, count 0 2006.238.08:21:00.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.238.08:21:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:21:00.29#ibcon#*before write, iclass 38, count 0 2006.238.08:21:00.29#ibcon#enter sib2, iclass 38, count 0 2006.238.08:21:00.29#ibcon#flushed, iclass 38, count 0 2006.238.08:21:00.29#ibcon#about to write, iclass 38, count 0 2006.238.08:21:00.29#ibcon#wrote, iclass 38, count 0 2006.238.08:21:00.29#ibcon#about to read 3, iclass 38, count 0 2006.238.08:21:00.33#ibcon#read 3, iclass 38, count 0 2006.238.08:21:00.33#ibcon#about to read 4, iclass 38, count 0 2006.238.08:21:00.33#ibcon#read 4, iclass 38, count 0 2006.238.08:21:00.33#ibcon#about to read 5, iclass 38, count 0 2006.238.08:21:00.33#ibcon#read 5, iclass 38, count 0 2006.238.08:21:00.33#ibcon#about to read 6, iclass 38, count 0 2006.238.08:21:00.33#ibcon#read 6, iclass 38, count 0 2006.238.08:21:00.33#ibcon#end of sib2, iclass 38, count 0 2006.238.08:21:00.33#ibcon#*after write, iclass 38, count 0 2006.238.08:21:00.33#ibcon#*before return 0, iclass 38, count 0 2006.238.08:21:00.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:21:00.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.238.08:21:00.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.238.08:21:00.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.238.08:21:00.33$vc4f8/va=8,7 2006.238.08:21:00.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.238.08:21:00.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.238.08:21:00.33#ibcon#ireg 11 cls_cnt 2 2006.238.08:21:00.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:21:00.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:21:00.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:21:00.39#ibcon#enter wrdev, iclass 40, count 2 2006.238.08:21:00.39#ibcon#first serial, iclass 40, count 2 2006.238.08:21:00.39#ibcon#enter sib2, iclass 40, count 2 2006.238.08:21:00.39#ibcon#flushed, iclass 40, count 2 2006.238.08:21:00.39#ibcon#about to write, iclass 40, count 2 2006.238.08:21:00.39#ibcon#wrote, iclass 40, count 2 2006.238.08:21:00.39#ibcon#about to read 3, iclass 40, count 2 2006.238.08:21:00.41#ibcon#read 3, iclass 40, count 2 2006.238.08:21:00.41#ibcon#about to read 4, iclass 40, count 2 2006.238.08:21:00.41#ibcon#read 4, iclass 40, count 2 2006.238.08:21:00.41#ibcon#about to read 5, iclass 40, count 2 2006.238.08:21:00.41#ibcon#read 5, iclass 40, count 2 2006.238.08:21:00.41#ibcon#about to read 6, iclass 40, count 2 2006.238.08:21:00.41#ibcon#read 6, iclass 40, count 2 2006.238.08:21:00.41#ibcon#end of sib2, iclass 40, count 2 2006.238.08:21:00.41#ibcon#*mode == 0, iclass 40, count 2 2006.238.08:21:00.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.238.08:21:00.41#ibcon#[25=AT08-07\r\n] 2006.238.08:21:00.41#ibcon#*before write, iclass 40, count 2 2006.238.08:21:00.41#ibcon#enter sib2, iclass 40, count 2 2006.238.08:21:00.41#ibcon#flushed, iclass 40, count 2 2006.238.08:21:00.41#ibcon#about to write, iclass 40, count 2 2006.238.08:21:00.41#ibcon#wrote, iclass 40, count 2 2006.238.08:21:00.41#ibcon#about to read 3, iclass 40, count 2 2006.238.08:21:00.44#ibcon#read 3, iclass 40, count 2 2006.238.08:21:00.44#ibcon#about to read 4, iclass 40, count 2 2006.238.08:21:00.44#ibcon#read 4, iclass 40, count 2 2006.238.08:21:00.44#ibcon#about to read 5, iclass 40, count 2 2006.238.08:21:00.44#ibcon#read 5, iclass 40, count 2 2006.238.08:21:00.44#ibcon#about to read 6, iclass 40, count 2 2006.238.08:21:00.44#ibcon#read 6, iclass 40, count 2 2006.238.08:21:00.44#ibcon#end of sib2, iclass 40, count 2 2006.238.08:21:00.44#ibcon#*after write, iclass 40, count 2 2006.238.08:21:00.44#ibcon#*before return 0, iclass 40, count 2 2006.238.08:21:00.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:21:00.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.238.08:21:00.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.238.08:21:00.44#ibcon#ireg 7 cls_cnt 0 2006.238.08:21:00.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:21:00.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:21:00.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:21:00.56#ibcon#enter wrdev, iclass 40, count 0 2006.238.08:21:00.56#ibcon#first serial, iclass 40, count 0 2006.238.08:21:00.56#ibcon#enter sib2, iclass 40, count 0 2006.238.08:21:00.56#ibcon#flushed, iclass 40, count 0 2006.238.08:21:00.56#ibcon#about to write, iclass 40, count 0 2006.238.08:21:00.56#ibcon#wrote, iclass 40, count 0 2006.238.08:21:00.56#ibcon#about to read 3, iclass 40, count 0 2006.238.08:21:00.58#ibcon#read 3, iclass 40, count 0 2006.238.08:21:00.58#ibcon#about to read 4, iclass 40, count 0 2006.238.08:21:00.58#ibcon#read 4, iclass 40, count 0 2006.238.08:21:00.58#ibcon#about to read 5, iclass 40, count 0 2006.238.08:21:00.58#ibcon#read 5, iclass 40, count 0 2006.238.08:21:00.58#ibcon#about to read 6, iclass 40, count 0 2006.238.08:21:00.58#ibcon#read 6, iclass 40, count 0 2006.238.08:21:00.58#ibcon#end of sib2, iclass 40, count 0 2006.238.08:21:00.58#ibcon#*mode == 0, iclass 40, count 0 2006.238.08:21:00.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.238.08:21:00.58#ibcon#[25=USB\r\n] 2006.238.08:21:00.58#ibcon#*before write, iclass 40, count 0 2006.238.08:21:00.58#ibcon#enter sib2, iclass 40, count 0 2006.238.08:21:00.58#ibcon#flushed, iclass 40, count 0 2006.238.08:21:00.58#ibcon#about to write, iclass 40, count 0 2006.238.08:21:00.58#ibcon#wrote, iclass 40, count 0 2006.238.08:21:00.58#ibcon#about to read 3, iclass 40, count 0 2006.238.08:21:00.61#ibcon#read 3, iclass 40, count 0 2006.238.08:21:00.61#ibcon#about to read 4, iclass 40, count 0 2006.238.08:21:00.61#ibcon#read 4, iclass 40, count 0 2006.238.08:21:00.61#ibcon#about to read 5, iclass 40, count 0 2006.238.08:21:00.61#ibcon#read 5, iclass 40, count 0 2006.238.08:21:00.61#ibcon#about to read 6, iclass 40, count 0 2006.238.08:21:00.61#ibcon#read 6, iclass 40, count 0 2006.238.08:21:00.61#ibcon#end of sib2, iclass 40, count 0 2006.238.08:21:00.61#ibcon#*after write, iclass 40, count 0 2006.238.08:21:00.61#ibcon#*before return 0, iclass 40, count 0 2006.238.08:21:00.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:21:00.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.238.08:21:00.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.238.08:21:00.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.238.08:21:00.61$vc4f8/vblo=1,632.99 2006.238.08:21:00.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.238.08:21:00.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.238.08:21:00.61#ibcon#ireg 17 cls_cnt 0 2006.238.08:21:00.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:21:00.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:21:00.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:21:00.61#ibcon#enter wrdev, iclass 4, count 0 2006.238.08:21:00.61#ibcon#first serial, iclass 4, count 0 2006.238.08:21:00.61#ibcon#enter sib2, iclass 4, count 0 2006.238.08:21:00.61#ibcon#flushed, iclass 4, count 0 2006.238.08:21:00.61#ibcon#about to write, iclass 4, count 0 2006.238.08:21:00.61#ibcon#wrote, iclass 4, count 0 2006.238.08:21:00.61#ibcon#about to read 3, iclass 4, count 0 2006.238.08:21:00.63#ibcon#read 3, iclass 4, count 0 2006.238.08:21:00.63#ibcon#about to read 4, iclass 4, count 0 2006.238.08:21:00.63#ibcon#read 4, iclass 4, count 0 2006.238.08:21:00.63#ibcon#about to read 5, iclass 4, count 0 2006.238.08:21:00.63#ibcon#read 5, iclass 4, count 0 2006.238.08:21:00.63#ibcon#about to read 6, iclass 4, count 0 2006.238.08:21:00.63#ibcon#read 6, iclass 4, count 0 2006.238.08:21:00.63#ibcon#end of sib2, iclass 4, count 0 2006.238.08:21:00.63#ibcon#*mode == 0, iclass 4, count 0 2006.238.08:21:00.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.238.08:21:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:21:00.63#ibcon#*before write, iclass 4, count 0 2006.238.08:21:00.63#ibcon#enter sib2, iclass 4, count 0 2006.238.08:21:00.63#ibcon#flushed, iclass 4, count 0 2006.238.08:21:00.63#ibcon#about to write, iclass 4, count 0 2006.238.08:21:00.63#ibcon#wrote, iclass 4, count 0 2006.238.08:21:00.63#ibcon#about to read 3, iclass 4, count 0 2006.238.08:21:00.67#ibcon#read 3, iclass 4, count 0 2006.238.08:21:00.67#ibcon#about to read 4, iclass 4, count 0 2006.238.08:21:00.67#ibcon#read 4, iclass 4, count 0 2006.238.08:21:00.67#ibcon#about to read 5, iclass 4, count 0 2006.238.08:21:00.67#ibcon#read 5, iclass 4, count 0 2006.238.08:21:00.67#ibcon#about to read 6, iclass 4, count 0 2006.238.08:21:00.67#ibcon#read 6, iclass 4, count 0 2006.238.08:21:00.67#ibcon#end of sib2, iclass 4, count 0 2006.238.08:21:00.67#ibcon#*after write, iclass 4, count 0 2006.238.08:21:00.67#ibcon#*before return 0, iclass 4, count 0 2006.238.08:21:00.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:21:00.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.238.08:21:00.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.238.08:21:00.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.238.08:21:00.67$vc4f8/vb=1,4 2006.238.08:21:00.67#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.238.08:21:00.67#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.238.08:21:00.67#ibcon#ireg 11 cls_cnt 2 2006.238.08:21:00.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:21:00.67#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:21:00.67#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:21:00.67#ibcon#enter wrdev, iclass 6, count 2 2006.238.08:21:00.67#ibcon#first serial, iclass 6, count 2 2006.238.08:21:00.67#ibcon#enter sib2, iclass 6, count 2 2006.238.08:21:00.67#ibcon#flushed, iclass 6, count 2 2006.238.08:21:00.67#ibcon#about to write, iclass 6, count 2 2006.238.08:21:00.67#ibcon#wrote, iclass 6, count 2 2006.238.08:21:00.67#ibcon#about to read 3, iclass 6, count 2 2006.238.08:21:00.69#ibcon#read 3, iclass 6, count 2 2006.238.08:21:00.69#ibcon#about to read 4, iclass 6, count 2 2006.238.08:21:00.69#ibcon#read 4, iclass 6, count 2 2006.238.08:21:00.69#ibcon#about to read 5, iclass 6, count 2 2006.238.08:21:00.69#ibcon#read 5, iclass 6, count 2 2006.238.08:21:00.69#ibcon#about to read 6, iclass 6, count 2 2006.238.08:21:00.69#ibcon#read 6, iclass 6, count 2 2006.238.08:21:00.69#ibcon#end of sib2, iclass 6, count 2 2006.238.08:21:00.69#ibcon#*mode == 0, iclass 6, count 2 2006.238.08:21:00.69#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.238.08:21:00.69#ibcon#[27=AT01-04\r\n] 2006.238.08:21:00.69#ibcon#*before write, iclass 6, count 2 2006.238.08:21:00.69#ibcon#enter sib2, iclass 6, count 2 2006.238.08:21:00.69#ibcon#flushed, iclass 6, count 2 2006.238.08:21:00.69#ibcon#about to write, iclass 6, count 2 2006.238.08:21:00.69#ibcon#wrote, iclass 6, count 2 2006.238.08:21:00.69#ibcon#about to read 3, iclass 6, count 2 2006.238.08:21:00.72#ibcon#read 3, iclass 6, count 2 2006.238.08:21:00.72#ibcon#about to read 4, iclass 6, count 2 2006.238.08:21:00.72#ibcon#read 4, iclass 6, count 2 2006.238.08:21:00.72#ibcon#about to read 5, iclass 6, count 2 2006.238.08:21:00.72#ibcon#read 5, iclass 6, count 2 2006.238.08:21:00.72#ibcon#about to read 6, iclass 6, count 2 2006.238.08:21:00.72#ibcon#read 6, iclass 6, count 2 2006.238.08:21:00.72#ibcon#end of sib2, iclass 6, count 2 2006.238.08:21:00.72#ibcon#*after write, iclass 6, count 2 2006.238.08:21:00.72#ibcon#*before return 0, iclass 6, count 2 2006.238.08:21:00.72#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:21:00.72#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.238.08:21:00.72#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.238.08:21:00.72#ibcon#ireg 7 cls_cnt 0 2006.238.08:21:00.72#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:21:00.84#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:21:00.84#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:21:00.84#ibcon#enter wrdev, iclass 6, count 0 2006.238.08:21:00.84#ibcon#first serial, iclass 6, count 0 2006.238.08:21:00.84#ibcon#enter sib2, iclass 6, count 0 2006.238.08:21:00.84#ibcon#flushed, iclass 6, count 0 2006.238.08:21:00.84#ibcon#about to write, iclass 6, count 0 2006.238.08:21:00.84#ibcon#wrote, iclass 6, count 0 2006.238.08:21:00.84#ibcon#about to read 3, iclass 6, count 0 2006.238.08:21:00.86#ibcon#read 3, iclass 6, count 0 2006.238.08:21:00.86#ibcon#about to read 4, iclass 6, count 0 2006.238.08:21:00.86#ibcon#read 4, iclass 6, count 0 2006.238.08:21:00.86#ibcon#about to read 5, iclass 6, count 0 2006.238.08:21:00.86#ibcon#read 5, iclass 6, count 0 2006.238.08:21:00.86#ibcon#about to read 6, iclass 6, count 0 2006.238.08:21:00.86#ibcon#read 6, iclass 6, count 0 2006.238.08:21:00.86#ibcon#end of sib2, iclass 6, count 0 2006.238.08:21:00.86#ibcon#*mode == 0, iclass 6, count 0 2006.238.08:21:00.86#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.238.08:21:00.86#ibcon#[27=USB\r\n] 2006.238.08:21:00.86#ibcon#*before write, iclass 6, count 0 2006.238.08:21:00.86#ibcon#enter sib2, iclass 6, count 0 2006.238.08:21:00.86#ibcon#flushed, iclass 6, count 0 2006.238.08:21:00.86#ibcon#about to write, iclass 6, count 0 2006.238.08:21:00.86#ibcon#wrote, iclass 6, count 0 2006.238.08:21:00.86#ibcon#about to read 3, iclass 6, count 0 2006.238.08:21:00.89#ibcon#read 3, iclass 6, count 0 2006.238.08:21:00.89#ibcon#about to read 4, iclass 6, count 0 2006.238.08:21:00.89#ibcon#read 4, iclass 6, count 0 2006.238.08:21:00.89#ibcon#about to read 5, iclass 6, count 0 2006.238.08:21:00.89#ibcon#read 5, iclass 6, count 0 2006.238.08:21:00.89#ibcon#about to read 6, iclass 6, count 0 2006.238.08:21:00.89#ibcon#read 6, iclass 6, count 0 2006.238.08:21:00.89#ibcon#end of sib2, iclass 6, count 0 2006.238.08:21:00.89#ibcon#*after write, iclass 6, count 0 2006.238.08:21:00.89#ibcon#*before return 0, iclass 6, count 0 2006.238.08:21:00.89#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:21:00.89#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.238.08:21:00.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.238.08:21:00.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.238.08:21:00.89$vc4f8/vblo=2,640.99 2006.238.08:21:00.89#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.238.08:21:00.89#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.238.08:21:00.89#ibcon#ireg 17 cls_cnt 0 2006.238.08:21:00.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:21:00.89#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:21:00.89#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:21:00.89#ibcon#enter wrdev, iclass 10, count 0 2006.238.08:21:00.89#ibcon#first serial, iclass 10, count 0 2006.238.08:21:00.89#ibcon#enter sib2, iclass 10, count 0 2006.238.08:21:00.89#ibcon#flushed, iclass 10, count 0 2006.238.08:21:00.89#ibcon#about to write, iclass 10, count 0 2006.238.08:21:00.89#ibcon#wrote, iclass 10, count 0 2006.238.08:21:00.89#ibcon#about to read 3, iclass 10, count 0 2006.238.08:21:00.91#ibcon#read 3, iclass 10, count 0 2006.238.08:21:00.91#ibcon#about to read 4, iclass 10, count 0 2006.238.08:21:00.91#ibcon#read 4, iclass 10, count 0 2006.238.08:21:00.91#ibcon#about to read 5, iclass 10, count 0 2006.238.08:21:00.91#ibcon#read 5, iclass 10, count 0 2006.238.08:21:00.91#ibcon#about to read 6, iclass 10, count 0 2006.238.08:21:00.91#ibcon#read 6, iclass 10, count 0 2006.238.08:21:00.91#ibcon#end of sib2, iclass 10, count 0 2006.238.08:21:00.91#ibcon#*mode == 0, iclass 10, count 0 2006.238.08:21:00.91#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.238.08:21:00.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:21:00.91#ibcon#*before write, iclass 10, count 0 2006.238.08:21:00.91#ibcon#enter sib2, iclass 10, count 0 2006.238.08:21:00.91#ibcon#flushed, iclass 10, count 0 2006.238.08:21:00.91#ibcon#about to write, iclass 10, count 0 2006.238.08:21:00.91#ibcon#wrote, iclass 10, count 0 2006.238.08:21:00.91#ibcon#about to read 3, iclass 10, count 0 2006.238.08:21:00.95#ibcon#read 3, iclass 10, count 0 2006.238.08:21:00.95#ibcon#about to read 4, iclass 10, count 0 2006.238.08:21:00.95#ibcon#read 4, iclass 10, count 0 2006.238.08:21:00.95#ibcon#about to read 5, iclass 10, count 0 2006.238.08:21:00.95#ibcon#read 5, iclass 10, count 0 2006.238.08:21:00.95#ibcon#about to read 6, iclass 10, count 0 2006.238.08:21:00.95#ibcon#read 6, iclass 10, count 0 2006.238.08:21:00.95#ibcon#end of sib2, iclass 10, count 0 2006.238.08:21:00.95#ibcon#*after write, iclass 10, count 0 2006.238.08:21:00.95#ibcon#*before return 0, iclass 10, count 0 2006.238.08:21:00.95#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:21:00.95#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.238.08:21:00.95#ibcon#about to clear, iclass 10 cls_cnt 0 2006.238.08:21:00.95#ibcon#cleared, iclass 10 cls_cnt 0 2006.238.08:21:00.95$vc4f8/vb=2,4 2006.238.08:21:00.95#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.238.08:21:00.95#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.238.08:21:00.95#ibcon#ireg 11 cls_cnt 2 2006.238.08:21:00.95#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:21:01.01#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:21:01.01#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:21:01.01#ibcon#enter wrdev, iclass 12, count 2 2006.238.08:21:01.01#ibcon#first serial, iclass 12, count 2 2006.238.08:21:01.01#ibcon#enter sib2, iclass 12, count 2 2006.238.08:21:01.01#ibcon#flushed, iclass 12, count 2 2006.238.08:21:01.01#ibcon#about to write, iclass 12, count 2 2006.238.08:21:01.01#ibcon#wrote, iclass 12, count 2 2006.238.08:21:01.01#ibcon#about to read 3, iclass 12, count 2 2006.238.08:21:01.03#ibcon#read 3, iclass 12, count 2 2006.238.08:21:01.03#ibcon#about to read 4, iclass 12, count 2 2006.238.08:21:01.03#ibcon#read 4, iclass 12, count 2 2006.238.08:21:01.03#ibcon#about to read 5, iclass 12, count 2 2006.238.08:21:01.03#ibcon#read 5, iclass 12, count 2 2006.238.08:21:01.03#ibcon#about to read 6, iclass 12, count 2 2006.238.08:21:01.03#ibcon#read 6, iclass 12, count 2 2006.238.08:21:01.03#ibcon#end of sib2, iclass 12, count 2 2006.238.08:21:01.03#ibcon#*mode == 0, iclass 12, count 2 2006.238.08:21:01.03#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.238.08:21:01.03#ibcon#[27=AT02-04\r\n] 2006.238.08:21:01.03#ibcon#*before write, iclass 12, count 2 2006.238.08:21:01.03#ibcon#enter sib2, iclass 12, count 2 2006.238.08:21:01.03#ibcon#flushed, iclass 12, count 2 2006.238.08:21:01.03#ibcon#about to write, iclass 12, count 2 2006.238.08:21:01.03#ibcon#wrote, iclass 12, count 2 2006.238.08:21:01.03#ibcon#about to read 3, iclass 12, count 2 2006.238.08:21:01.06#ibcon#read 3, iclass 12, count 2 2006.238.08:21:01.06#ibcon#about to read 4, iclass 12, count 2 2006.238.08:21:01.06#ibcon#read 4, iclass 12, count 2 2006.238.08:21:01.06#ibcon#about to read 5, iclass 12, count 2 2006.238.08:21:01.06#ibcon#read 5, iclass 12, count 2 2006.238.08:21:01.06#ibcon#about to read 6, iclass 12, count 2 2006.238.08:21:01.06#ibcon#read 6, iclass 12, count 2 2006.238.08:21:01.06#ibcon#end of sib2, iclass 12, count 2 2006.238.08:21:01.06#ibcon#*after write, iclass 12, count 2 2006.238.08:21:01.06#ibcon#*before return 0, iclass 12, count 2 2006.238.08:21:01.06#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:21:01.06#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.238.08:21:01.06#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.238.08:21:01.06#ibcon#ireg 7 cls_cnt 0 2006.238.08:21:01.06#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:21:01.18#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:21:01.18#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:21:01.18#ibcon#enter wrdev, iclass 12, count 0 2006.238.08:21:01.18#ibcon#first serial, iclass 12, count 0 2006.238.08:21:01.18#ibcon#enter sib2, iclass 12, count 0 2006.238.08:21:01.18#ibcon#flushed, iclass 12, count 0 2006.238.08:21:01.18#ibcon#about to write, iclass 12, count 0 2006.238.08:21:01.18#ibcon#wrote, iclass 12, count 0 2006.238.08:21:01.18#ibcon#about to read 3, iclass 12, count 0 2006.238.08:21:01.20#ibcon#read 3, iclass 12, count 0 2006.238.08:21:01.20#ibcon#about to read 4, iclass 12, count 0 2006.238.08:21:01.20#ibcon#read 4, iclass 12, count 0 2006.238.08:21:01.20#ibcon#about to read 5, iclass 12, count 0 2006.238.08:21:01.20#ibcon#read 5, iclass 12, count 0 2006.238.08:21:01.20#ibcon#about to read 6, iclass 12, count 0 2006.238.08:21:01.20#ibcon#read 6, iclass 12, count 0 2006.238.08:21:01.20#ibcon#end of sib2, iclass 12, count 0 2006.238.08:21:01.20#ibcon#*mode == 0, iclass 12, count 0 2006.238.08:21:01.20#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.238.08:21:01.20#ibcon#[27=USB\r\n] 2006.238.08:21:01.20#ibcon#*before write, iclass 12, count 0 2006.238.08:21:01.20#ibcon#enter sib2, iclass 12, count 0 2006.238.08:21:01.20#ibcon#flushed, iclass 12, count 0 2006.238.08:21:01.20#ibcon#about to write, iclass 12, count 0 2006.238.08:21:01.20#ibcon#wrote, iclass 12, count 0 2006.238.08:21:01.20#ibcon#about to read 3, iclass 12, count 0 2006.238.08:21:01.23#ibcon#read 3, iclass 12, count 0 2006.238.08:21:01.23#ibcon#about to read 4, iclass 12, count 0 2006.238.08:21:01.23#ibcon#read 4, iclass 12, count 0 2006.238.08:21:01.23#ibcon#about to read 5, iclass 12, count 0 2006.238.08:21:01.23#ibcon#read 5, iclass 12, count 0 2006.238.08:21:01.23#ibcon#about to read 6, iclass 12, count 0 2006.238.08:21:01.23#ibcon#read 6, iclass 12, count 0 2006.238.08:21:01.23#ibcon#end of sib2, iclass 12, count 0 2006.238.08:21:01.23#ibcon#*after write, iclass 12, count 0 2006.238.08:21:01.23#ibcon#*before return 0, iclass 12, count 0 2006.238.08:21:01.23#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:21:01.23#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.238.08:21:01.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.238.08:21:01.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.238.08:21:01.23$vc4f8/vblo=3,656.99 2006.238.08:21:01.23#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.238.08:21:01.23#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.238.08:21:01.23#ibcon#ireg 17 cls_cnt 0 2006.238.08:21:01.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:21:01.23#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:21:01.23#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:21:01.23#ibcon#enter wrdev, iclass 14, count 0 2006.238.08:21:01.23#ibcon#first serial, iclass 14, count 0 2006.238.08:21:01.23#ibcon#enter sib2, iclass 14, count 0 2006.238.08:21:01.23#ibcon#flushed, iclass 14, count 0 2006.238.08:21:01.23#ibcon#about to write, iclass 14, count 0 2006.238.08:21:01.23#ibcon#wrote, iclass 14, count 0 2006.238.08:21:01.23#ibcon#about to read 3, iclass 14, count 0 2006.238.08:21:01.25#ibcon#read 3, iclass 14, count 0 2006.238.08:21:01.25#ibcon#about to read 4, iclass 14, count 0 2006.238.08:21:01.25#ibcon#read 4, iclass 14, count 0 2006.238.08:21:01.25#ibcon#about to read 5, iclass 14, count 0 2006.238.08:21:01.25#ibcon#read 5, iclass 14, count 0 2006.238.08:21:01.25#ibcon#about to read 6, iclass 14, count 0 2006.238.08:21:01.25#ibcon#read 6, iclass 14, count 0 2006.238.08:21:01.25#ibcon#end of sib2, iclass 14, count 0 2006.238.08:21:01.25#ibcon#*mode == 0, iclass 14, count 0 2006.238.08:21:01.25#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.238.08:21:01.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:21:01.25#ibcon#*before write, iclass 14, count 0 2006.238.08:21:01.25#ibcon#enter sib2, iclass 14, count 0 2006.238.08:21:01.25#ibcon#flushed, iclass 14, count 0 2006.238.08:21:01.25#ibcon#about to write, iclass 14, count 0 2006.238.08:21:01.25#ibcon#wrote, iclass 14, count 0 2006.238.08:21:01.25#ibcon#about to read 3, iclass 14, count 0 2006.238.08:21:01.29#ibcon#read 3, iclass 14, count 0 2006.238.08:21:01.29#ibcon#about to read 4, iclass 14, count 0 2006.238.08:21:01.29#ibcon#read 4, iclass 14, count 0 2006.238.08:21:01.29#ibcon#about to read 5, iclass 14, count 0 2006.238.08:21:01.29#ibcon#read 5, iclass 14, count 0 2006.238.08:21:01.29#ibcon#about to read 6, iclass 14, count 0 2006.238.08:21:01.29#ibcon#read 6, iclass 14, count 0 2006.238.08:21:01.29#ibcon#end of sib2, iclass 14, count 0 2006.238.08:21:01.29#ibcon#*after write, iclass 14, count 0 2006.238.08:21:01.29#ibcon#*before return 0, iclass 14, count 0 2006.238.08:21:01.29#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:21:01.29#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.238.08:21:01.29#ibcon#about to clear, iclass 14 cls_cnt 0 2006.238.08:21:01.29#ibcon#cleared, iclass 14 cls_cnt 0 2006.238.08:21:01.29$vc4f8/vb=3,4 2006.238.08:21:01.29#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.238.08:21:01.29#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.238.08:21:01.29#ibcon#ireg 11 cls_cnt 2 2006.238.08:21:01.29#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:21:01.35#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:21:01.35#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:21:01.35#ibcon#enter wrdev, iclass 16, count 2 2006.238.08:21:01.35#ibcon#first serial, iclass 16, count 2 2006.238.08:21:01.35#ibcon#enter sib2, iclass 16, count 2 2006.238.08:21:01.35#ibcon#flushed, iclass 16, count 2 2006.238.08:21:01.35#ibcon#about to write, iclass 16, count 2 2006.238.08:21:01.35#ibcon#wrote, iclass 16, count 2 2006.238.08:21:01.35#ibcon#about to read 3, iclass 16, count 2 2006.238.08:21:01.37#ibcon#read 3, iclass 16, count 2 2006.238.08:21:01.37#ibcon#about to read 4, iclass 16, count 2 2006.238.08:21:01.37#ibcon#read 4, iclass 16, count 2 2006.238.08:21:01.37#ibcon#about to read 5, iclass 16, count 2 2006.238.08:21:01.37#ibcon#read 5, iclass 16, count 2 2006.238.08:21:01.37#ibcon#about to read 6, iclass 16, count 2 2006.238.08:21:01.37#ibcon#read 6, iclass 16, count 2 2006.238.08:21:01.37#ibcon#end of sib2, iclass 16, count 2 2006.238.08:21:01.37#ibcon#*mode == 0, iclass 16, count 2 2006.238.08:21:01.37#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.238.08:21:01.37#ibcon#[27=AT03-04\r\n] 2006.238.08:21:01.37#ibcon#*before write, iclass 16, count 2 2006.238.08:21:01.37#ibcon#enter sib2, iclass 16, count 2 2006.238.08:21:01.37#ibcon#flushed, iclass 16, count 2 2006.238.08:21:01.37#ibcon#about to write, iclass 16, count 2 2006.238.08:21:01.37#ibcon#wrote, iclass 16, count 2 2006.238.08:21:01.37#ibcon#about to read 3, iclass 16, count 2 2006.238.08:21:01.40#ibcon#read 3, iclass 16, count 2 2006.238.08:21:01.40#ibcon#about to read 4, iclass 16, count 2 2006.238.08:21:01.40#ibcon#read 4, iclass 16, count 2 2006.238.08:21:01.40#ibcon#about to read 5, iclass 16, count 2 2006.238.08:21:01.40#ibcon#read 5, iclass 16, count 2 2006.238.08:21:01.40#ibcon#about to read 6, iclass 16, count 2 2006.238.08:21:01.40#ibcon#read 6, iclass 16, count 2 2006.238.08:21:01.40#ibcon#end of sib2, iclass 16, count 2 2006.238.08:21:01.40#ibcon#*after write, iclass 16, count 2 2006.238.08:21:01.40#ibcon#*before return 0, iclass 16, count 2 2006.238.08:21:01.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:21:01.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.238.08:21:01.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.238.08:21:01.40#ibcon#ireg 7 cls_cnt 0 2006.238.08:21:01.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:21:01.52#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:21:01.52#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:21:01.52#ibcon#enter wrdev, iclass 16, count 0 2006.238.08:21:01.52#ibcon#first serial, iclass 16, count 0 2006.238.08:21:01.52#ibcon#enter sib2, iclass 16, count 0 2006.238.08:21:01.52#ibcon#flushed, iclass 16, count 0 2006.238.08:21:01.52#ibcon#about to write, iclass 16, count 0 2006.238.08:21:01.52#ibcon#wrote, iclass 16, count 0 2006.238.08:21:01.52#ibcon#about to read 3, iclass 16, count 0 2006.238.08:21:01.54#ibcon#read 3, iclass 16, count 0 2006.238.08:21:01.54#ibcon#about to read 4, iclass 16, count 0 2006.238.08:21:01.54#ibcon#read 4, iclass 16, count 0 2006.238.08:21:01.54#ibcon#about to read 5, iclass 16, count 0 2006.238.08:21:01.54#ibcon#read 5, iclass 16, count 0 2006.238.08:21:01.54#ibcon#about to read 6, iclass 16, count 0 2006.238.08:21:01.54#ibcon#read 6, iclass 16, count 0 2006.238.08:21:01.54#ibcon#end of sib2, iclass 16, count 0 2006.238.08:21:01.54#ibcon#*mode == 0, iclass 16, count 0 2006.238.08:21:01.54#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.238.08:21:01.54#ibcon#[27=USB\r\n] 2006.238.08:21:01.54#ibcon#*before write, iclass 16, count 0 2006.238.08:21:01.54#ibcon#enter sib2, iclass 16, count 0 2006.238.08:21:01.54#ibcon#flushed, iclass 16, count 0 2006.238.08:21:01.54#ibcon#about to write, iclass 16, count 0 2006.238.08:21:01.54#ibcon#wrote, iclass 16, count 0 2006.238.08:21:01.54#ibcon#about to read 3, iclass 16, count 0 2006.238.08:21:01.57#ibcon#read 3, iclass 16, count 0 2006.238.08:21:01.57#ibcon#about to read 4, iclass 16, count 0 2006.238.08:21:01.57#ibcon#read 4, iclass 16, count 0 2006.238.08:21:01.57#ibcon#about to read 5, iclass 16, count 0 2006.238.08:21:01.57#ibcon#read 5, iclass 16, count 0 2006.238.08:21:01.57#ibcon#about to read 6, iclass 16, count 0 2006.238.08:21:01.57#ibcon#read 6, iclass 16, count 0 2006.238.08:21:01.57#ibcon#end of sib2, iclass 16, count 0 2006.238.08:21:01.57#ibcon#*after write, iclass 16, count 0 2006.238.08:21:01.57#ibcon#*before return 0, iclass 16, count 0 2006.238.08:21:01.57#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:21:01.57#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.238.08:21:01.57#ibcon#about to clear, iclass 16 cls_cnt 0 2006.238.08:21:01.57#ibcon#cleared, iclass 16 cls_cnt 0 2006.238.08:21:01.57$vc4f8/vblo=4,712.99 2006.238.08:21:01.57#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.238.08:21:01.57#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.238.08:21:01.57#ibcon#ireg 17 cls_cnt 0 2006.238.08:21:01.57#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:21:01.57#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:21:01.57#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:21:01.57#ibcon#enter wrdev, iclass 18, count 0 2006.238.08:21:01.57#ibcon#first serial, iclass 18, count 0 2006.238.08:21:01.57#ibcon#enter sib2, iclass 18, count 0 2006.238.08:21:01.57#ibcon#flushed, iclass 18, count 0 2006.238.08:21:01.57#ibcon#about to write, iclass 18, count 0 2006.238.08:21:01.57#ibcon#wrote, iclass 18, count 0 2006.238.08:21:01.57#ibcon#about to read 3, iclass 18, count 0 2006.238.08:21:01.59#ibcon#read 3, iclass 18, count 0 2006.238.08:21:01.59#ibcon#about to read 4, iclass 18, count 0 2006.238.08:21:01.59#ibcon#read 4, iclass 18, count 0 2006.238.08:21:01.59#ibcon#about to read 5, iclass 18, count 0 2006.238.08:21:01.59#ibcon#read 5, iclass 18, count 0 2006.238.08:21:01.59#ibcon#about to read 6, iclass 18, count 0 2006.238.08:21:01.59#ibcon#read 6, iclass 18, count 0 2006.238.08:21:01.59#ibcon#end of sib2, iclass 18, count 0 2006.238.08:21:01.59#ibcon#*mode == 0, iclass 18, count 0 2006.238.08:21:01.59#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.238.08:21:01.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:21:01.59#ibcon#*before write, iclass 18, count 0 2006.238.08:21:01.59#ibcon#enter sib2, iclass 18, count 0 2006.238.08:21:01.59#ibcon#flushed, iclass 18, count 0 2006.238.08:21:01.59#ibcon#about to write, iclass 18, count 0 2006.238.08:21:01.59#ibcon#wrote, iclass 18, count 0 2006.238.08:21:01.59#ibcon#about to read 3, iclass 18, count 0 2006.238.08:21:01.63#ibcon#read 3, iclass 18, count 0 2006.238.08:21:01.63#ibcon#about to read 4, iclass 18, count 0 2006.238.08:21:01.63#ibcon#read 4, iclass 18, count 0 2006.238.08:21:01.63#ibcon#about to read 5, iclass 18, count 0 2006.238.08:21:01.63#ibcon#read 5, iclass 18, count 0 2006.238.08:21:01.63#ibcon#about to read 6, iclass 18, count 0 2006.238.08:21:01.63#ibcon#read 6, iclass 18, count 0 2006.238.08:21:01.63#ibcon#end of sib2, iclass 18, count 0 2006.238.08:21:01.63#ibcon#*after write, iclass 18, count 0 2006.238.08:21:01.63#ibcon#*before return 0, iclass 18, count 0 2006.238.08:21:01.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:21:01.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.238.08:21:01.63#ibcon#about to clear, iclass 18 cls_cnt 0 2006.238.08:21:01.63#ibcon#cleared, iclass 18 cls_cnt 0 2006.238.08:21:01.63$vc4f8/vb=4,4 2006.238.08:21:01.63#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.238.08:21:01.63#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.238.08:21:01.63#ibcon#ireg 11 cls_cnt 2 2006.238.08:21:01.63#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:21:01.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:21:01.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:21:01.69#ibcon#enter wrdev, iclass 20, count 2 2006.238.08:21:01.69#ibcon#first serial, iclass 20, count 2 2006.238.08:21:01.69#ibcon#enter sib2, iclass 20, count 2 2006.238.08:21:01.69#ibcon#flushed, iclass 20, count 2 2006.238.08:21:01.69#ibcon#about to write, iclass 20, count 2 2006.238.08:21:01.69#ibcon#wrote, iclass 20, count 2 2006.238.08:21:01.69#ibcon#about to read 3, iclass 20, count 2 2006.238.08:21:01.71#ibcon#read 3, iclass 20, count 2 2006.238.08:21:01.71#ibcon#about to read 4, iclass 20, count 2 2006.238.08:21:01.71#ibcon#read 4, iclass 20, count 2 2006.238.08:21:01.71#ibcon#about to read 5, iclass 20, count 2 2006.238.08:21:01.71#ibcon#read 5, iclass 20, count 2 2006.238.08:21:01.71#ibcon#about to read 6, iclass 20, count 2 2006.238.08:21:01.71#ibcon#read 6, iclass 20, count 2 2006.238.08:21:01.71#ibcon#end of sib2, iclass 20, count 2 2006.238.08:21:01.71#ibcon#*mode == 0, iclass 20, count 2 2006.238.08:21:01.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.238.08:21:01.71#ibcon#[27=AT04-04\r\n] 2006.238.08:21:01.71#ibcon#*before write, iclass 20, count 2 2006.238.08:21:01.71#ibcon#enter sib2, iclass 20, count 2 2006.238.08:21:01.71#ibcon#flushed, iclass 20, count 2 2006.238.08:21:01.71#ibcon#about to write, iclass 20, count 2 2006.238.08:21:01.71#ibcon#wrote, iclass 20, count 2 2006.238.08:21:01.71#ibcon#about to read 3, iclass 20, count 2 2006.238.08:21:01.74#ibcon#read 3, iclass 20, count 2 2006.238.08:21:01.74#ibcon#about to read 4, iclass 20, count 2 2006.238.08:21:01.74#ibcon#read 4, iclass 20, count 2 2006.238.08:21:01.74#ibcon#about to read 5, iclass 20, count 2 2006.238.08:21:01.74#ibcon#read 5, iclass 20, count 2 2006.238.08:21:01.74#ibcon#about to read 6, iclass 20, count 2 2006.238.08:21:01.74#ibcon#read 6, iclass 20, count 2 2006.238.08:21:01.74#ibcon#end of sib2, iclass 20, count 2 2006.238.08:21:01.74#ibcon#*after write, iclass 20, count 2 2006.238.08:21:01.74#ibcon#*before return 0, iclass 20, count 2 2006.238.08:21:01.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:21:01.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.238.08:21:01.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.238.08:21:01.74#ibcon#ireg 7 cls_cnt 0 2006.238.08:21:01.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:21:01.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:21:01.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:21:01.86#ibcon#enter wrdev, iclass 20, count 0 2006.238.08:21:01.86#ibcon#first serial, iclass 20, count 0 2006.238.08:21:01.86#ibcon#enter sib2, iclass 20, count 0 2006.238.08:21:01.86#ibcon#flushed, iclass 20, count 0 2006.238.08:21:01.86#ibcon#about to write, iclass 20, count 0 2006.238.08:21:01.86#ibcon#wrote, iclass 20, count 0 2006.238.08:21:01.86#ibcon#about to read 3, iclass 20, count 0 2006.238.08:21:01.88#ibcon#read 3, iclass 20, count 0 2006.238.08:21:01.88#ibcon#about to read 4, iclass 20, count 0 2006.238.08:21:01.88#ibcon#read 4, iclass 20, count 0 2006.238.08:21:01.88#ibcon#about to read 5, iclass 20, count 0 2006.238.08:21:01.88#ibcon#read 5, iclass 20, count 0 2006.238.08:21:01.88#ibcon#about to read 6, iclass 20, count 0 2006.238.08:21:01.88#ibcon#read 6, iclass 20, count 0 2006.238.08:21:01.88#ibcon#end of sib2, iclass 20, count 0 2006.238.08:21:01.88#ibcon#*mode == 0, iclass 20, count 0 2006.238.08:21:01.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.238.08:21:01.88#ibcon#[27=USB\r\n] 2006.238.08:21:01.88#ibcon#*before write, iclass 20, count 0 2006.238.08:21:01.88#ibcon#enter sib2, iclass 20, count 0 2006.238.08:21:01.88#ibcon#flushed, iclass 20, count 0 2006.238.08:21:01.88#ibcon#about to write, iclass 20, count 0 2006.238.08:21:01.88#ibcon#wrote, iclass 20, count 0 2006.238.08:21:01.88#ibcon#about to read 3, iclass 20, count 0 2006.238.08:21:01.91#ibcon#read 3, iclass 20, count 0 2006.238.08:21:01.91#ibcon#about to read 4, iclass 20, count 0 2006.238.08:21:01.91#ibcon#read 4, iclass 20, count 0 2006.238.08:21:01.91#ibcon#about to read 5, iclass 20, count 0 2006.238.08:21:01.91#ibcon#read 5, iclass 20, count 0 2006.238.08:21:01.91#ibcon#about to read 6, iclass 20, count 0 2006.238.08:21:01.91#ibcon#read 6, iclass 20, count 0 2006.238.08:21:01.91#ibcon#end of sib2, iclass 20, count 0 2006.238.08:21:01.91#ibcon#*after write, iclass 20, count 0 2006.238.08:21:01.91#ibcon#*before return 0, iclass 20, count 0 2006.238.08:21:01.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:21:01.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.238.08:21:01.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.238.08:21:01.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.238.08:21:01.91$vc4f8/vblo=5,744.99 2006.238.08:21:01.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.08:21:01.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.08:21:01.91#ibcon#ireg 17 cls_cnt 0 2006.238.08:21:01.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:21:01.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:21:01.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:21:01.91#ibcon#enter wrdev, iclass 22, count 0 2006.238.08:21:01.91#ibcon#first serial, iclass 22, count 0 2006.238.08:21:01.91#ibcon#enter sib2, iclass 22, count 0 2006.238.08:21:01.91#ibcon#flushed, iclass 22, count 0 2006.238.08:21:01.91#ibcon#about to write, iclass 22, count 0 2006.238.08:21:01.91#ibcon#wrote, iclass 22, count 0 2006.238.08:21:01.91#ibcon#about to read 3, iclass 22, count 0 2006.238.08:21:01.93#ibcon#read 3, iclass 22, count 0 2006.238.08:21:01.93#ibcon#about to read 4, iclass 22, count 0 2006.238.08:21:01.93#ibcon#read 4, iclass 22, count 0 2006.238.08:21:01.93#ibcon#about to read 5, iclass 22, count 0 2006.238.08:21:01.93#ibcon#read 5, iclass 22, count 0 2006.238.08:21:01.93#ibcon#about to read 6, iclass 22, count 0 2006.238.08:21:01.93#ibcon#read 6, iclass 22, count 0 2006.238.08:21:01.93#ibcon#end of sib2, iclass 22, count 0 2006.238.08:21:01.93#ibcon#*mode == 0, iclass 22, count 0 2006.238.08:21:01.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.08:21:01.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:21:01.93#ibcon#*before write, iclass 22, count 0 2006.238.08:21:01.93#ibcon#enter sib2, iclass 22, count 0 2006.238.08:21:01.93#ibcon#flushed, iclass 22, count 0 2006.238.08:21:01.93#ibcon#about to write, iclass 22, count 0 2006.238.08:21:01.93#ibcon#wrote, iclass 22, count 0 2006.238.08:21:01.93#ibcon#about to read 3, iclass 22, count 0 2006.238.08:21:01.97#ibcon#read 3, iclass 22, count 0 2006.238.08:21:01.97#ibcon#about to read 4, iclass 22, count 0 2006.238.08:21:01.97#ibcon#read 4, iclass 22, count 0 2006.238.08:21:01.97#ibcon#about to read 5, iclass 22, count 0 2006.238.08:21:01.97#ibcon#read 5, iclass 22, count 0 2006.238.08:21:01.97#ibcon#about to read 6, iclass 22, count 0 2006.238.08:21:01.97#ibcon#read 6, iclass 22, count 0 2006.238.08:21:01.97#ibcon#end of sib2, iclass 22, count 0 2006.238.08:21:01.97#ibcon#*after write, iclass 22, count 0 2006.238.08:21:01.97#ibcon#*before return 0, iclass 22, count 0 2006.238.08:21:01.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:21:01.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:21:01.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.08:21:01.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.08:21:01.97$vc4f8/vb=5,4 2006.238.08:21:01.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.238.08:21:01.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.238.08:21:01.97#ibcon#ireg 11 cls_cnt 2 2006.238.08:21:01.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:21:02.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:21:02.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:21:02.03#ibcon#enter wrdev, iclass 24, count 2 2006.238.08:21:02.03#ibcon#first serial, iclass 24, count 2 2006.238.08:21:02.03#ibcon#enter sib2, iclass 24, count 2 2006.238.08:21:02.03#ibcon#flushed, iclass 24, count 2 2006.238.08:21:02.03#ibcon#about to write, iclass 24, count 2 2006.238.08:21:02.03#ibcon#wrote, iclass 24, count 2 2006.238.08:21:02.03#ibcon#about to read 3, iclass 24, count 2 2006.238.08:21:02.05#ibcon#read 3, iclass 24, count 2 2006.238.08:21:02.05#ibcon#about to read 4, iclass 24, count 2 2006.238.08:21:02.05#ibcon#read 4, iclass 24, count 2 2006.238.08:21:02.05#ibcon#about to read 5, iclass 24, count 2 2006.238.08:21:02.05#ibcon#read 5, iclass 24, count 2 2006.238.08:21:02.05#ibcon#about to read 6, iclass 24, count 2 2006.238.08:21:02.05#ibcon#read 6, iclass 24, count 2 2006.238.08:21:02.05#ibcon#end of sib2, iclass 24, count 2 2006.238.08:21:02.05#ibcon#*mode == 0, iclass 24, count 2 2006.238.08:21:02.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.238.08:21:02.05#ibcon#[27=AT05-04\r\n] 2006.238.08:21:02.05#ibcon#*before write, iclass 24, count 2 2006.238.08:21:02.05#ibcon#enter sib2, iclass 24, count 2 2006.238.08:21:02.05#ibcon#flushed, iclass 24, count 2 2006.238.08:21:02.05#ibcon#about to write, iclass 24, count 2 2006.238.08:21:02.05#ibcon#wrote, iclass 24, count 2 2006.238.08:21:02.05#ibcon#about to read 3, iclass 24, count 2 2006.238.08:21:02.08#ibcon#read 3, iclass 24, count 2 2006.238.08:21:02.08#ibcon#about to read 4, iclass 24, count 2 2006.238.08:21:02.08#ibcon#read 4, iclass 24, count 2 2006.238.08:21:02.08#ibcon#about to read 5, iclass 24, count 2 2006.238.08:21:02.08#ibcon#read 5, iclass 24, count 2 2006.238.08:21:02.08#ibcon#about to read 6, iclass 24, count 2 2006.238.08:21:02.08#ibcon#read 6, iclass 24, count 2 2006.238.08:21:02.08#ibcon#end of sib2, iclass 24, count 2 2006.238.08:21:02.08#ibcon#*after write, iclass 24, count 2 2006.238.08:21:02.08#ibcon#*before return 0, iclass 24, count 2 2006.238.08:21:02.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:21:02.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:21:02.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.238.08:21:02.08#ibcon#ireg 7 cls_cnt 0 2006.238.08:21:02.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:21:02.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:21:02.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:21:02.20#ibcon#enter wrdev, iclass 24, count 0 2006.238.08:21:02.20#ibcon#first serial, iclass 24, count 0 2006.238.08:21:02.20#ibcon#enter sib2, iclass 24, count 0 2006.238.08:21:02.20#ibcon#flushed, iclass 24, count 0 2006.238.08:21:02.20#ibcon#about to write, iclass 24, count 0 2006.238.08:21:02.20#ibcon#wrote, iclass 24, count 0 2006.238.08:21:02.20#ibcon#about to read 3, iclass 24, count 0 2006.238.08:21:02.22#ibcon#read 3, iclass 24, count 0 2006.238.08:21:02.22#ibcon#about to read 4, iclass 24, count 0 2006.238.08:21:02.22#ibcon#read 4, iclass 24, count 0 2006.238.08:21:02.22#ibcon#about to read 5, iclass 24, count 0 2006.238.08:21:02.22#ibcon#read 5, iclass 24, count 0 2006.238.08:21:02.22#ibcon#about to read 6, iclass 24, count 0 2006.238.08:21:02.22#ibcon#read 6, iclass 24, count 0 2006.238.08:21:02.22#ibcon#end of sib2, iclass 24, count 0 2006.238.08:21:02.22#ibcon#*mode == 0, iclass 24, count 0 2006.238.08:21:02.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.08:21:02.22#ibcon#[27=USB\r\n] 2006.238.08:21:02.22#ibcon#*before write, iclass 24, count 0 2006.238.08:21:02.22#ibcon#enter sib2, iclass 24, count 0 2006.238.08:21:02.22#ibcon#flushed, iclass 24, count 0 2006.238.08:21:02.22#ibcon#about to write, iclass 24, count 0 2006.238.08:21:02.22#ibcon#wrote, iclass 24, count 0 2006.238.08:21:02.22#ibcon#about to read 3, iclass 24, count 0 2006.238.08:21:02.25#ibcon#read 3, iclass 24, count 0 2006.238.08:21:02.25#ibcon#about to read 4, iclass 24, count 0 2006.238.08:21:02.25#ibcon#read 4, iclass 24, count 0 2006.238.08:21:02.25#ibcon#about to read 5, iclass 24, count 0 2006.238.08:21:02.25#ibcon#read 5, iclass 24, count 0 2006.238.08:21:02.25#ibcon#about to read 6, iclass 24, count 0 2006.238.08:21:02.25#ibcon#read 6, iclass 24, count 0 2006.238.08:21:02.25#ibcon#end of sib2, iclass 24, count 0 2006.238.08:21:02.25#ibcon#*after write, iclass 24, count 0 2006.238.08:21:02.25#ibcon#*before return 0, iclass 24, count 0 2006.238.08:21:02.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:21:02.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:21:02.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.08:21:02.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.08:21:02.25$vc4f8/vblo=6,752.99 2006.238.08:21:02.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.238.08:21:02.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.238.08:21:02.25#ibcon#ireg 17 cls_cnt 0 2006.238.08:21:02.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:21:02.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:21:02.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:21:02.25#ibcon#enter wrdev, iclass 26, count 0 2006.238.08:21:02.25#ibcon#first serial, iclass 26, count 0 2006.238.08:21:02.25#ibcon#enter sib2, iclass 26, count 0 2006.238.08:21:02.25#ibcon#flushed, iclass 26, count 0 2006.238.08:21:02.25#ibcon#about to write, iclass 26, count 0 2006.238.08:21:02.25#ibcon#wrote, iclass 26, count 0 2006.238.08:21:02.25#ibcon#about to read 3, iclass 26, count 0 2006.238.08:21:02.27#ibcon#read 3, iclass 26, count 0 2006.238.08:21:02.27#ibcon#about to read 4, iclass 26, count 0 2006.238.08:21:02.27#ibcon#read 4, iclass 26, count 0 2006.238.08:21:02.27#ibcon#about to read 5, iclass 26, count 0 2006.238.08:21:02.27#ibcon#read 5, iclass 26, count 0 2006.238.08:21:02.27#ibcon#about to read 6, iclass 26, count 0 2006.238.08:21:02.27#ibcon#read 6, iclass 26, count 0 2006.238.08:21:02.27#ibcon#end of sib2, iclass 26, count 0 2006.238.08:21:02.27#ibcon#*mode == 0, iclass 26, count 0 2006.238.08:21:02.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.238.08:21:02.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:21:02.27#ibcon#*before write, iclass 26, count 0 2006.238.08:21:02.27#ibcon#enter sib2, iclass 26, count 0 2006.238.08:21:02.27#ibcon#flushed, iclass 26, count 0 2006.238.08:21:02.27#ibcon#about to write, iclass 26, count 0 2006.238.08:21:02.27#ibcon#wrote, iclass 26, count 0 2006.238.08:21:02.27#ibcon#about to read 3, iclass 26, count 0 2006.238.08:21:02.31#ibcon#read 3, iclass 26, count 0 2006.238.08:21:02.31#ibcon#about to read 4, iclass 26, count 0 2006.238.08:21:02.31#ibcon#read 4, iclass 26, count 0 2006.238.08:21:02.31#ibcon#about to read 5, iclass 26, count 0 2006.238.08:21:02.31#ibcon#read 5, iclass 26, count 0 2006.238.08:21:02.31#ibcon#about to read 6, iclass 26, count 0 2006.238.08:21:02.31#ibcon#read 6, iclass 26, count 0 2006.238.08:21:02.31#ibcon#end of sib2, iclass 26, count 0 2006.238.08:21:02.31#ibcon#*after write, iclass 26, count 0 2006.238.08:21:02.31#ibcon#*before return 0, iclass 26, count 0 2006.238.08:21:02.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:21:02.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.238.08:21:02.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.238.08:21:02.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.238.08:21:02.31$vc4f8/vb=6,4 2006.238.08:21:02.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.238.08:21:02.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.238.08:21:02.31#ibcon#ireg 11 cls_cnt 2 2006.238.08:21:02.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:21:02.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:21:02.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:21:02.37#ibcon#enter wrdev, iclass 28, count 2 2006.238.08:21:02.37#ibcon#first serial, iclass 28, count 2 2006.238.08:21:02.37#ibcon#enter sib2, iclass 28, count 2 2006.238.08:21:02.37#ibcon#flushed, iclass 28, count 2 2006.238.08:21:02.37#ibcon#about to write, iclass 28, count 2 2006.238.08:21:02.37#ibcon#wrote, iclass 28, count 2 2006.238.08:21:02.37#ibcon#about to read 3, iclass 28, count 2 2006.238.08:21:02.39#ibcon#read 3, iclass 28, count 2 2006.238.08:21:02.39#ibcon#about to read 4, iclass 28, count 2 2006.238.08:21:02.39#ibcon#read 4, iclass 28, count 2 2006.238.08:21:02.39#ibcon#about to read 5, iclass 28, count 2 2006.238.08:21:02.39#ibcon#read 5, iclass 28, count 2 2006.238.08:21:02.39#ibcon#about to read 6, iclass 28, count 2 2006.238.08:21:02.39#ibcon#read 6, iclass 28, count 2 2006.238.08:21:02.39#ibcon#end of sib2, iclass 28, count 2 2006.238.08:21:02.39#ibcon#*mode == 0, iclass 28, count 2 2006.238.08:21:02.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.238.08:21:02.39#ibcon#[27=AT06-04\r\n] 2006.238.08:21:02.39#ibcon#*before write, iclass 28, count 2 2006.238.08:21:02.39#ibcon#enter sib2, iclass 28, count 2 2006.238.08:21:02.39#ibcon#flushed, iclass 28, count 2 2006.238.08:21:02.39#ibcon#about to write, iclass 28, count 2 2006.238.08:21:02.39#ibcon#wrote, iclass 28, count 2 2006.238.08:21:02.39#ibcon#about to read 3, iclass 28, count 2 2006.238.08:21:02.42#ibcon#read 3, iclass 28, count 2 2006.238.08:21:02.42#ibcon#about to read 4, iclass 28, count 2 2006.238.08:21:02.42#ibcon#read 4, iclass 28, count 2 2006.238.08:21:02.42#ibcon#about to read 5, iclass 28, count 2 2006.238.08:21:02.42#ibcon#read 5, iclass 28, count 2 2006.238.08:21:02.42#ibcon#about to read 6, iclass 28, count 2 2006.238.08:21:02.42#ibcon#read 6, iclass 28, count 2 2006.238.08:21:02.42#ibcon#end of sib2, iclass 28, count 2 2006.238.08:21:02.42#ibcon#*after write, iclass 28, count 2 2006.238.08:21:02.42#ibcon#*before return 0, iclass 28, count 2 2006.238.08:21:02.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:21:02.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.238.08:21:02.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.238.08:21:02.42#ibcon#ireg 7 cls_cnt 0 2006.238.08:21:02.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:21:02.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:21:02.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:21:02.54#ibcon#enter wrdev, iclass 28, count 0 2006.238.08:21:02.54#ibcon#first serial, iclass 28, count 0 2006.238.08:21:02.54#ibcon#enter sib2, iclass 28, count 0 2006.238.08:21:02.54#ibcon#flushed, iclass 28, count 0 2006.238.08:21:02.54#ibcon#about to write, iclass 28, count 0 2006.238.08:21:02.54#ibcon#wrote, iclass 28, count 0 2006.238.08:21:02.54#ibcon#about to read 3, iclass 28, count 0 2006.238.08:21:02.56#ibcon#read 3, iclass 28, count 0 2006.238.08:21:02.56#ibcon#about to read 4, iclass 28, count 0 2006.238.08:21:02.56#ibcon#read 4, iclass 28, count 0 2006.238.08:21:02.56#ibcon#about to read 5, iclass 28, count 0 2006.238.08:21:02.56#ibcon#read 5, iclass 28, count 0 2006.238.08:21:02.56#ibcon#about to read 6, iclass 28, count 0 2006.238.08:21:02.56#ibcon#read 6, iclass 28, count 0 2006.238.08:21:02.56#ibcon#end of sib2, iclass 28, count 0 2006.238.08:21:02.56#ibcon#*mode == 0, iclass 28, count 0 2006.238.08:21:02.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.238.08:21:02.56#ibcon#[27=USB\r\n] 2006.238.08:21:02.56#ibcon#*before write, iclass 28, count 0 2006.238.08:21:02.56#ibcon#enter sib2, iclass 28, count 0 2006.238.08:21:02.56#ibcon#flushed, iclass 28, count 0 2006.238.08:21:02.56#ibcon#about to write, iclass 28, count 0 2006.238.08:21:02.56#ibcon#wrote, iclass 28, count 0 2006.238.08:21:02.56#ibcon#about to read 3, iclass 28, count 0 2006.238.08:21:02.59#ibcon#read 3, iclass 28, count 0 2006.238.08:21:02.59#ibcon#about to read 4, iclass 28, count 0 2006.238.08:21:02.59#ibcon#read 4, iclass 28, count 0 2006.238.08:21:02.59#ibcon#about to read 5, iclass 28, count 0 2006.238.08:21:02.59#ibcon#read 5, iclass 28, count 0 2006.238.08:21:02.59#ibcon#about to read 6, iclass 28, count 0 2006.238.08:21:02.59#ibcon#read 6, iclass 28, count 0 2006.238.08:21:02.59#ibcon#end of sib2, iclass 28, count 0 2006.238.08:21:02.59#ibcon#*after write, iclass 28, count 0 2006.238.08:21:02.59#ibcon#*before return 0, iclass 28, count 0 2006.238.08:21:02.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:21:02.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.238.08:21:02.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.238.08:21:02.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.238.08:21:02.59$vc4f8/vabw=wide 2006.238.08:21:02.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.238.08:21:02.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.238.08:21:02.59#ibcon#ireg 8 cls_cnt 0 2006.238.08:21:02.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:21:02.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:21:02.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:21:02.59#ibcon#enter wrdev, iclass 30, count 0 2006.238.08:21:02.59#ibcon#first serial, iclass 30, count 0 2006.238.08:21:02.59#ibcon#enter sib2, iclass 30, count 0 2006.238.08:21:02.59#ibcon#flushed, iclass 30, count 0 2006.238.08:21:02.59#ibcon#about to write, iclass 30, count 0 2006.238.08:21:02.59#ibcon#wrote, iclass 30, count 0 2006.238.08:21:02.59#ibcon#about to read 3, iclass 30, count 0 2006.238.08:21:02.61#ibcon#read 3, iclass 30, count 0 2006.238.08:21:02.61#ibcon#about to read 4, iclass 30, count 0 2006.238.08:21:02.61#ibcon#read 4, iclass 30, count 0 2006.238.08:21:02.61#ibcon#about to read 5, iclass 30, count 0 2006.238.08:21:02.61#ibcon#read 5, iclass 30, count 0 2006.238.08:21:02.61#ibcon#about to read 6, iclass 30, count 0 2006.238.08:21:02.61#ibcon#read 6, iclass 30, count 0 2006.238.08:21:02.61#ibcon#end of sib2, iclass 30, count 0 2006.238.08:21:02.61#ibcon#*mode == 0, iclass 30, count 0 2006.238.08:21:02.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.238.08:21:02.61#ibcon#[25=BW32\r\n] 2006.238.08:21:02.61#ibcon#*before write, iclass 30, count 0 2006.238.08:21:02.61#ibcon#enter sib2, iclass 30, count 0 2006.238.08:21:02.61#ibcon#flushed, iclass 30, count 0 2006.238.08:21:02.61#ibcon#about to write, iclass 30, count 0 2006.238.08:21:02.61#ibcon#wrote, iclass 30, count 0 2006.238.08:21:02.61#ibcon#about to read 3, iclass 30, count 0 2006.238.08:21:02.64#ibcon#read 3, iclass 30, count 0 2006.238.08:21:02.64#ibcon#about to read 4, iclass 30, count 0 2006.238.08:21:02.64#ibcon#read 4, iclass 30, count 0 2006.238.08:21:02.64#ibcon#about to read 5, iclass 30, count 0 2006.238.08:21:02.64#ibcon#read 5, iclass 30, count 0 2006.238.08:21:02.64#ibcon#about to read 6, iclass 30, count 0 2006.238.08:21:02.64#ibcon#read 6, iclass 30, count 0 2006.238.08:21:02.64#ibcon#end of sib2, iclass 30, count 0 2006.238.08:21:02.64#ibcon#*after write, iclass 30, count 0 2006.238.08:21:02.64#ibcon#*before return 0, iclass 30, count 0 2006.238.08:21:02.64#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:21:02.64#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.238.08:21:02.64#ibcon#about to clear, iclass 30 cls_cnt 0 2006.238.08:21:02.64#ibcon#cleared, iclass 30 cls_cnt 0 2006.238.08:21:02.64$vc4f8/vbbw=wide 2006.238.08:21:02.64#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.238.08:21:02.64#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.238.08:21:02.64#ibcon#ireg 8 cls_cnt 0 2006.238.08:21:02.64#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:21:02.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:21:02.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:21:02.71#ibcon#enter wrdev, iclass 32, count 0 2006.238.08:21:02.71#ibcon#first serial, iclass 32, count 0 2006.238.08:21:02.71#ibcon#enter sib2, iclass 32, count 0 2006.238.08:21:02.71#ibcon#flushed, iclass 32, count 0 2006.238.08:21:02.71#ibcon#about to write, iclass 32, count 0 2006.238.08:21:02.71#ibcon#wrote, iclass 32, count 0 2006.238.08:21:02.71#ibcon#about to read 3, iclass 32, count 0 2006.238.08:21:02.73#ibcon#read 3, iclass 32, count 0 2006.238.08:21:02.73#ibcon#about to read 4, iclass 32, count 0 2006.238.08:21:02.73#ibcon#read 4, iclass 32, count 0 2006.238.08:21:02.73#ibcon#about to read 5, iclass 32, count 0 2006.238.08:21:02.73#ibcon#read 5, iclass 32, count 0 2006.238.08:21:02.73#ibcon#about to read 6, iclass 32, count 0 2006.238.08:21:02.73#ibcon#read 6, iclass 32, count 0 2006.238.08:21:02.73#ibcon#end of sib2, iclass 32, count 0 2006.238.08:21:02.73#ibcon#*mode == 0, iclass 32, count 0 2006.238.08:21:02.73#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.238.08:21:02.73#ibcon#[27=BW32\r\n] 2006.238.08:21:02.73#ibcon#*before write, iclass 32, count 0 2006.238.08:21:02.73#ibcon#enter sib2, iclass 32, count 0 2006.238.08:21:02.73#ibcon#flushed, iclass 32, count 0 2006.238.08:21:02.73#ibcon#about to write, iclass 32, count 0 2006.238.08:21:02.73#ibcon#wrote, iclass 32, count 0 2006.238.08:21:02.73#ibcon#about to read 3, iclass 32, count 0 2006.238.08:21:02.76#ibcon#read 3, iclass 32, count 0 2006.238.08:21:02.76#ibcon#about to read 4, iclass 32, count 0 2006.238.08:21:02.76#ibcon#read 4, iclass 32, count 0 2006.238.08:21:02.76#ibcon#about to read 5, iclass 32, count 0 2006.238.08:21:02.76#ibcon#read 5, iclass 32, count 0 2006.238.08:21:02.76#ibcon#about to read 6, iclass 32, count 0 2006.238.08:21:02.76#ibcon#read 6, iclass 32, count 0 2006.238.08:21:02.76#ibcon#end of sib2, iclass 32, count 0 2006.238.08:21:02.76#ibcon#*after write, iclass 32, count 0 2006.238.08:21:02.76#ibcon#*before return 0, iclass 32, count 0 2006.238.08:21:02.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:21:02.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.238.08:21:02.76#ibcon#about to clear, iclass 32 cls_cnt 0 2006.238.08:21:02.76#ibcon#cleared, iclass 32 cls_cnt 0 2006.238.08:21:02.76$4f8m12a/ifd4f 2006.238.08:21:02.76$ifd4f/lo= 2006.238.08:21:02.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:21:02.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:21:02.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:21:02.76$ifd4f/patch= 2006.238.08:21:02.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:21:02.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:21:02.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:21:02.76$4f8m12a/"form=m,16.000,1:2 2006.238.08:21:02.76$4f8m12a/"tpicd 2006.238.08:21:02.76$4f8m12a/echo=off 2006.238.08:21:02.76$4f8m12a/xlog=off 2006.238.08:21:02.76:!2006.238.08:23:10 2006.238.08:21:07.14#trakl#Source acquired 2006.238.08:21:09.14#flagr#flagr/antenna,acquired 2006.238.08:23:10.00:preob 2006.238.08:23:10.14/onsource/TRACKING 2006.238.08:23:10.14:!2006.238.08:23:20 2006.238.08:23:20.00:data_valid=on 2006.238.08:23:20.00:midob 2006.238.08:23:21.14/onsource/TRACKING 2006.238.08:23:21.14/wx/25.42,1012.3,90 2006.238.08:23:21.34/cable/+6.4168E-03 2006.238.08:23:22.43/va/01,08,usb,yes,32,33 2006.238.08:23:22.43/va/02,07,usb,yes,32,33 2006.238.08:23:22.43/va/03,07,usb,yes,30,30 2006.238.08:23:22.43/va/04,07,usb,yes,33,36 2006.238.08:23:22.43/va/05,08,usb,yes,30,31 2006.238.08:23:22.43/va/06,07,usb,yes,32,32 2006.238.08:23:22.43/va/07,07,usb,yes,33,32 2006.238.08:23:22.43/va/08,07,usb,yes,35,35 2006.238.08:23:22.66/valo/01,532.99,yes,locked 2006.238.08:23:22.66/valo/02,572.99,yes,locked 2006.238.08:23:22.66/valo/03,672.99,yes,locked 2006.238.08:23:22.66/valo/04,832.99,yes,locked 2006.238.08:23:22.66/valo/05,652.99,yes,locked 2006.238.08:23:22.66/valo/06,772.99,yes,locked 2006.238.08:23:22.66/valo/07,832.99,yes,locked 2006.238.08:23:22.66/valo/08,852.99,yes,locked 2006.238.08:23:23.75/vb/01,04,usb,yes,30,29 2006.238.08:23:23.75/vb/02,04,usb,yes,32,34 2006.238.08:23:23.75/vb/03,04,usb,yes,29,32 2006.238.08:23:23.75/vb/04,04,usb,yes,29,30 2006.238.08:23:23.75/vb/05,04,usb,yes,28,32 2006.238.08:23:23.75/vb/06,04,usb,yes,29,32 2006.238.08:23:23.75/vb/07,04,usb,yes,31,31 2006.238.08:23:23.75/vb/08,04,usb,yes,28,32 2006.238.08:23:23.99/vblo/01,632.99,yes,locked 2006.238.08:23:23.99/vblo/02,640.99,yes,locked 2006.238.08:23:23.99/vblo/03,656.99,yes,locked 2006.238.08:23:23.99/vblo/04,712.99,yes,locked 2006.238.08:23:23.99/vblo/05,744.99,yes,locked 2006.238.08:23:23.99/vblo/06,752.99,yes,locked 2006.238.08:23:23.99/vblo/07,734.99,yes,locked 2006.238.08:23:23.99/vblo/08,744.99,yes,locked 2006.238.08:23:24.14/vabw/8 2006.238.08:23:24.29/vbbw/8 2006.238.08:23:24.38/xfe/off,on,14.0 2006.238.08:23:24.75/ifatt/23,28,28,28 2006.238.08:23:25.08/fmout-gps/S +4.50E-07 2006.238.08:23:25.16:!2006.238.08:24:20 2006.238.08:24:20.00:data_valid=off 2006.238.08:24:20.00:postob 2006.238.08:24:20.11/cable/+6.4173E-03 2006.238.08:24:20.11/wx/25.42,1012.3,91 2006.238.08:24:21.07/fmout-gps/S +4.50E-07 2006.238.08:24:21.07:scan_name=238-0825,k06238,60 2006.238.08:24:21.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.238.08:24:21.13#flagr#flagr/antenna,new-source 2006.238.08:24:22.13:checkk5 2006.238.08:24:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.238.08:24:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.238.08:24:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.238.08:24:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.238.08:24:24.02/chk_obsdata//k5ts1/T2380823??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:24:24.38/chk_obsdata//k5ts2/T2380823??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:24:24.75/chk_obsdata//k5ts3/T2380823??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:24:25.13/chk_obsdata//k5ts4/T2380823??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:24:25.82/k5log//k5ts1_log_newline 2006.238.08:24:26.51/k5log//k5ts2_log_newline 2006.238.08:24:27.21/k5log//k5ts3_log_newline 2006.238.08:24:27.90/k5log//k5ts4_log_newline 2006.238.08:24:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:24:27.92:4f8m12a=3 2006.238.08:24:27.92$4f8m12a/echo=on 2006.238.08:24:27.92$4f8m12a/pcalon 2006.238.08:24:27.92$pcalon/"no phase cal control is implemented here 2006.238.08:24:27.92$4f8m12a/"tpicd=stop 2006.238.08:24:27.92$4f8m12a/vc4f8 2006.238.08:24:27.92$vc4f8/valo=1,532.99 2006.238.08:24:27.92#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.08:24:27.92#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.08:24:27.92#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:27.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:24:27.92#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:24:27.92#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:24:27.92#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:24:27.92#ibcon#first serial, iclass 5, count 0 2006.238.08:24:27.92#ibcon#enter sib2, iclass 5, count 0 2006.238.08:24:27.92#ibcon#flushed, iclass 5, count 0 2006.238.08:24:27.92#ibcon#about to write, iclass 5, count 0 2006.238.08:24:27.92#ibcon#wrote, iclass 5, count 0 2006.238.08:24:27.92#ibcon#about to read 3, iclass 5, count 0 2006.238.08:24:27.94#ibcon#read 3, iclass 5, count 0 2006.238.08:24:27.94#ibcon#about to read 4, iclass 5, count 0 2006.238.08:24:27.94#ibcon#read 4, iclass 5, count 0 2006.238.08:24:27.94#ibcon#about to read 5, iclass 5, count 0 2006.238.08:24:27.94#ibcon#read 5, iclass 5, count 0 2006.238.08:24:27.94#ibcon#about to read 6, iclass 5, count 0 2006.238.08:24:27.94#ibcon#read 6, iclass 5, count 0 2006.238.08:24:27.94#ibcon#end of sib2, iclass 5, count 0 2006.238.08:24:27.94#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:24:27.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:24:27.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.238.08:24:27.94#ibcon#*before write, iclass 5, count 0 2006.238.08:24:27.94#ibcon#enter sib2, iclass 5, count 0 2006.238.08:24:27.94#ibcon#flushed, iclass 5, count 0 2006.238.08:24:27.94#ibcon#about to write, iclass 5, count 0 2006.238.08:24:27.94#ibcon#wrote, iclass 5, count 0 2006.238.08:24:27.94#ibcon#about to read 3, iclass 5, count 0 2006.238.08:24:27.99#ibcon#read 3, iclass 5, count 0 2006.238.08:24:27.99#ibcon#about to read 4, iclass 5, count 0 2006.238.08:24:27.99#ibcon#read 4, iclass 5, count 0 2006.238.08:24:27.99#ibcon#about to read 5, iclass 5, count 0 2006.238.08:24:27.99#ibcon#read 5, iclass 5, count 0 2006.238.08:24:27.99#ibcon#about to read 6, iclass 5, count 0 2006.238.08:24:27.99#ibcon#read 6, iclass 5, count 0 2006.238.08:24:27.99#ibcon#end of sib2, iclass 5, count 0 2006.238.08:24:27.99#ibcon#*after write, iclass 5, count 0 2006.238.08:24:27.99#ibcon#*before return 0, iclass 5, count 0 2006.238.08:24:27.99#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:24:27.99#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:24:27.99#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:24:27.99#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:24:27.99$vc4f8/va=1,8 2006.238.08:24:27.99#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.08:24:27.99#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.08:24:27.99#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:27.99#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:24:27.99#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:24:27.99#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:24:27.99#ibcon#enter wrdev, iclass 7, count 2 2006.238.08:24:27.99#ibcon#first serial, iclass 7, count 2 2006.238.08:24:27.99#ibcon#enter sib2, iclass 7, count 2 2006.238.08:24:27.99#ibcon#flushed, iclass 7, count 2 2006.238.08:24:27.99#ibcon#about to write, iclass 7, count 2 2006.238.08:24:27.99#ibcon#wrote, iclass 7, count 2 2006.238.08:24:27.99#ibcon#about to read 3, iclass 7, count 2 2006.238.08:24:28.01#ibcon#read 3, iclass 7, count 2 2006.238.08:24:28.01#ibcon#about to read 4, iclass 7, count 2 2006.238.08:24:28.01#ibcon#read 4, iclass 7, count 2 2006.238.08:24:28.01#ibcon#about to read 5, iclass 7, count 2 2006.238.08:24:28.01#ibcon#read 5, iclass 7, count 2 2006.238.08:24:28.01#ibcon#about to read 6, iclass 7, count 2 2006.238.08:24:28.01#ibcon#read 6, iclass 7, count 2 2006.238.08:24:28.01#ibcon#end of sib2, iclass 7, count 2 2006.238.08:24:28.01#ibcon#*mode == 0, iclass 7, count 2 2006.238.08:24:28.01#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.08:24:28.01#ibcon#[25=AT01-08\r\n] 2006.238.08:24:28.01#ibcon#*before write, iclass 7, count 2 2006.238.08:24:28.01#ibcon#enter sib2, iclass 7, count 2 2006.238.08:24:28.01#ibcon#flushed, iclass 7, count 2 2006.238.08:24:28.01#ibcon#about to write, iclass 7, count 2 2006.238.08:24:28.01#ibcon#wrote, iclass 7, count 2 2006.238.08:24:28.01#ibcon#about to read 3, iclass 7, count 2 2006.238.08:24:28.04#ibcon#read 3, iclass 7, count 2 2006.238.08:24:28.04#ibcon#about to read 4, iclass 7, count 2 2006.238.08:24:28.04#ibcon#read 4, iclass 7, count 2 2006.238.08:24:28.04#ibcon#about to read 5, iclass 7, count 2 2006.238.08:24:28.04#ibcon#read 5, iclass 7, count 2 2006.238.08:24:28.04#ibcon#about to read 6, iclass 7, count 2 2006.238.08:24:28.04#ibcon#read 6, iclass 7, count 2 2006.238.08:24:28.04#ibcon#end of sib2, iclass 7, count 2 2006.238.08:24:28.04#ibcon#*after write, iclass 7, count 2 2006.238.08:24:28.04#ibcon#*before return 0, iclass 7, count 2 2006.238.08:24:28.04#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:24:28.04#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:24:28.04#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.08:24:28.04#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:28.04#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:24:28.16#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:24:28.16#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:24:28.16#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:24:28.16#ibcon#first serial, iclass 7, count 0 2006.238.08:24:28.16#ibcon#enter sib2, iclass 7, count 0 2006.238.08:24:28.16#ibcon#flushed, iclass 7, count 0 2006.238.08:24:28.16#ibcon#about to write, iclass 7, count 0 2006.238.08:24:28.16#ibcon#wrote, iclass 7, count 0 2006.238.08:24:28.16#ibcon#about to read 3, iclass 7, count 0 2006.238.08:24:28.18#ibcon#read 3, iclass 7, count 0 2006.238.08:24:28.18#ibcon#about to read 4, iclass 7, count 0 2006.238.08:24:28.18#ibcon#read 4, iclass 7, count 0 2006.238.08:24:28.18#ibcon#about to read 5, iclass 7, count 0 2006.238.08:24:28.18#ibcon#read 5, iclass 7, count 0 2006.238.08:24:28.18#ibcon#about to read 6, iclass 7, count 0 2006.238.08:24:28.18#ibcon#read 6, iclass 7, count 0 2006.238.08:24:28.18#ibcon#end of sib2, iclass 7, count 0 2006.238.08:24:28.18#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:24:28.18#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:24:28.18#ibcon#[25=USB\r\n] 2006.238.08:24:28.18#ibcon#*before write, iclass 7, count 0 2006.238.08:24:28.18#ibcon#enter sib2, iclass 7, count 0 2006.238.08:24:28.18#ibcon#flushed, iclass 7, count 0 2006.238.08:24:28.18#ibcon#about to write, iclass 7, count 0 2006.238.08:24:28.18#ibcon#wrote, iclass 7, count 0 2006.238.08:24:28.18#ibcon#about to read 3, iclass 7, count 0 2006.238.08:24:28.21#ibcon#read 3, iclass 7, count 0 2006.238.08:24:28.21#ibcon#about to read 4, iclass 7, count 0 2006.238.08:24:28.21#ibcon#read 4, iclass 7, count 0 2006.238.08:24:28.21#ibcon#about to read 5, iclass 7, count 0 2006.238.08:24:28.21#ibcon#read 5, iclass 7, count 0 2006.238.08:24:28.21#ibcon#about to read 6, iclass 7, count 0 2006.238.08:24:28.21#ibcon#read 6, iclass 7, count 0 2006.238.08:24:28.21#ibcon#end of sib2, iclass 7, count 0 2006.238.08:24:28.21#ibcon#*after write, iclass 7, count 0 2006.238.08:24:28.21#ibcon#*before return 0, iclass 7, count 0 2006.238.08:24:28.21#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:24:28.21#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:24:28.21#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:24:28.21#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:24:28.21$vc4f8/valo=2,572.99 2006.238.08:24:28.21#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.08:24:28.21#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.08:24:28.21#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:28.21#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:24:28.21#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:24:28.21#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:24:28.21#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:24:28.21#ibcon#first serial, iclass 11, count 0 2006.238.08:24:28.21#ibcon#enter sib2, iclass 11, count 0 2006.238.08:24:28.21#ibcon#flushed, iclass 11, count 0 2006.238.08:24:28.21#ibcon#about to write, iclass 11, count 0 2006.238.08:24:28.21#ibcon#wrote, iclass 11, count 0 2006.238.08:24:28.21#ibcon#about to read 3, iclass 11, count 0 2006.238.08:24:28.23#ibcon#read 3, iclass 11, count 0 2006.238.08:24:28.23#ibcon#about to read 4, iclass 11, count 0 2006.238.08:24:28.23#ibcon#read 4, iclass 11, count 0 2006.238.08:24:28.23#ibcon#about to read 5, iclass 11, count 0 2006.238.08:24:28.23#ibcon#read 5, iclass 11, count 0 2006.238.08:24:28.23#ibcon#about to read 6, iclass 11, count 0 2006.238.08:24:28.23#ibcon#read 6, iclass 11, count 0 2006.238.08:24:28.23#ibcon#end of sib2, iclass 11, count 0 2006.238.08:24:28.23#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:24:28.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:24:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.238.08:24:28.23#ibcon#*before write, iclass 11, count 0 2006.238.08:24:28.23#ibcon#enter sib2, iclass 11, count 0 2006.238.08:24:28.23#ibcon#flushed, iclass 11, count 0 2006.238.08:24:28.23#ibcon#about to write, iclass 11, count 0 2006.238.08:24:28.23#ibcon#wrote, iclass 11, count 0 2006.238.08:24:28.23#ibcon#about to read 3, iclass 11, count 0 2006.238.08:24:28.27#ibcon#read 3, iclass 11, count 0 2006.238.08:24:28.27#ibcon#about to read 4, iclass 11, count 0 2006.238.08:24:28.27#ibcon#read 4, iclass 11, count 0 2006.238.08:24:28.27#ibcon#about to read 5, iclass 11, count 0 2006.238.08:24:28.27#ibcon#read 5, iclass 11, count 0 2006.238.08:24:28.27#ibcon#about to read 6, iclass 11, count 0 2006.238.08:24:28.27#ibcon#read 6, iclass 11, count 0 2006.238.08:24:28.27#ibcon#end of sib2, iclass 11, count 0 2006.238.08:24:28.27#ibcon#*after write, iclass 11, count 0 2006.238.08:24:28.27#ibcon#*before return 0, iclass 11, count 0 2006.238.08:24:28.27#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:24:28.27#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:24:28.27#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:24:28.27#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:24:28.27$vc4f8/va=2,7 2006.238.08:24:28.27#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.08:24:28.27#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.08:24:28.27#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:28.27#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:24:28.33#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:24:28.33#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:24:28.33#ibcon#enter wrdev, iclass 13, count 2 2006.238.08:24:28.33#ibcon#first serial, iclass 13, count 2 2006.238.08:24:28.33#ibcon#enter sib2, iclass 13, count 2 2006.238.08:24:28.33#ibcon#flushed, iclass 13, count 2 2006.238.08:24:28.33#ibcon#about to write, iclass 13, count 2 2006.238.08:24:28.33#ibcon#wrote, iclass 13, count 2 2006.238.08:24:28.33#ibcon#about to read 3, iclass 13, count 2 2006.238.08:24:28.35#ibcon#read 3, iclass 13, count 2 2006.238.08:24:28.35#ibcon#about to read 4, iclass 13, count 2 2006.238.08:24:28.35#ibcon#read 4, iclass 13, count 2 2006.238.08:24:28.35#ibcon#about to read 5, iclass 13, count 2 2006.238.08:24:28.35#ibcon#read 5, iclass 13, count 2 2006.238.08:24:28.35#ibcon#about to read 6, iclass 13, count 2 2006.238.08:24:28.35#ibcon#read 6, iclass 13, count 2 2006.238.08:24:28.35#ibcon#end of sib2, iclass 13, count 2 2006.238.08:24:28.35#ibcon#*mode == 0, iclass 13, count 2 2006.238.08:24:28.35#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.08:24:28.35#ibcon#[25=AT02-07\r\n] 2006.238.08:24:28.35#ibcon#*before write, iclass 13, count 2 2006.238.08:24:28.35#ibcon#enter sib2, iclass 13, count 2 2006.238.08:24:28.35#ibcon#flushed, iclass 13, count 2 2006.238.08:24:28.35#ibcon#about to write, iclass 13, count 2 2006.238.08:24:28.35#ibcon#wrote, iclass 13, count 2 2006.238.08:24:28.35#ibcon#about to read 3, iclass 13, count 2 2006.238.08:24:28.39#ibcon#read 3, iclass 13, count 2 2006.238.08:24:28.39#ibcon#about to read 4, iclass 13, count 2 2006.238.08:24:28.39#ibcon#read 4, iclass 13, count 2 2006.238.08:24:28.39#ibcon#about to read 5, iclass 13, count 2 2006.238.08:24:28.39#ibcon#read 5, iclass 13, count 2 2006.238.08:24:28.39#ibcon#about to read 6, iclass 13, count 2 2006.238.08:24:28.39#ibcon#read 6, iclass 13, count 2 2006.238.08:24:28.39#ibcon#end of sib2, iclass 13, count 2 2006.238.08:24:28.39#ibcon#*after write, iclass 13, count 2 2006.238.08:24:28.39#ibcon#*before return 0, iclass 13, count 2 2006.238.08:24:28.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:24:28.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:24:28.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.08:24:28.39#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:28.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:24:28.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:24:28.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:24:28.51#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:24:28.51#ibcon#first serial, iclass 13, count 0 2006.238.08:24:28.51#ibcon#enter sib2, iclass 13, count 0 2006.238.08:24:28.51#ibcon#flushed, iclass 13, count 0 2006.238.08:24:28.51#ibcon#about to write, iclass 13, count 0 2006.238.08:24:28.51#ibcon#wrote, iclass 13, count 0 2006.238.08:24:28.51#ibcon#about to read 3, iclass 13, count 0 2006.238.08:24:28.53#ibcon#read 3, iclass 13, count 0 2006.238.08:24:28.53#ibcon#about to read 4, iclass 13, count 0 2006.238.08:24:28.53#ibcon#read 4, iclass 13, count 0 2006.238.08:24:28.53#ibcon#about to read 5, iclass 13, count 0 2006.238.08:24:28.53#ibcon#read 5, iclass 13, count 0 2006.238.08:24:28.53#ibcon#about to read 6, iclass 13, count 0 2006.238.08:24:28.53#ibcon#read 6, iclass 13, count 0 2006.238.08:24:28.53#ibcon#end of sib2, iclass 13, count 0 2006.238.08:24:28.53#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:24:28.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:24:28.53#ibcon#[25=USB\r\n] 2006.238.08:24:28.53#ibcon#*before write, iclass 13, count 0 2006.238.08:24:28.53#ibcon#enter sib2, iclass 13, count 0 2006.238.08:24:28.53#ibcon#flushed, iclass 13, count 0 2006.238.08:24:28.53#ibcon#about to write, iclass 13, count 0 2006.238.08:24:28.53#ibcon#wrote, iclass 13, count 0 2006.238.08:24:28.53#ibcon#about to read 3, iclass 13, count 0 2006.238.08:24:28.56#ibcon#read 3, iclass 13, count 0 2006.238.08:24:28.56#ibcon#about to read 4, iclass 13, count 0 2006.238.08:24:28.56#ibcon#read 4, iclass 13, count 0 2006.238.08:24:28.56#ibcon#about to read 5, iclass 13, count 0 2006.238.08:24:28.56#ibcon#read 5, iclass 13, count 0 2006.238.08:24:28.56#ibcon#about to read 6, iclass 13, count 0 2006.238.08:24:28.56#ibcon#read 6, iclass 13, count 0 2006.238.08:24:28.56#ibcon#end of sib2, iclass 13, count 0 2006.238.08:24:28.56#ibcon#*after write, iclass 13, count 0 2006.238.08:24:28.56#ibcon#*before return 0, iclass 13, count 0 2006.238.08:24:28.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:24:28.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:24:28.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:24:28.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:24:28.56$vc4f8/valo=3,672.99 2006.238.08:24:28.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.08:24:28.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.08:24:28.56#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:28.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:24:28.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:24:28.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:24:28.56#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:24:28.56#ibcon#first serial, iclass 15, count 0 2006.238.08:24:28.56#ibcon#enter sib2, iclass 15, count 0 2006.238.08:24:28.56#ibcon#flushed, iclass 15, count 0 2006.238.08:24:28.56#ibcon#about to write, iclass 15, count 0 2006.238.08:24:28.56#ibcon#wrote, iclass 15, count 0 2006.238.08:24:28.56#ibcon#about to read 3, iclass 15, count 0 2006.238.08:24:28.58#ibcon#read 3, iclass 15, count 0 2006.238.08:24:28.58#ibcon#about to read 4, iclass 15, count 0 2006.238.08:24:28.58#ibcon#read 4, iclass 15, count 0 2006.238.08:24:28.58#ibcon#about to read 5, iclass 15, count 0 2006.238.08:24:28.58#ibcon#read 5, iclass 15, count 0 2006.238.08:24:28.58#ibcon#about to read 6, iclass 15, count 0 2006.238.08:24:28.58#ibcon#read 6, iclass 15, count 0 2006.238.08:24:28.58#ibcon#end of sib2, iclass 15, count 0 2006.238.08:24:28.58#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:24:28.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:24:28.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.238.08:24:28.58#ibcon#*before write, iclass 15, count 0 2006.238.08:24:28.58#ibcon#enter sib2, iclass 15, count 0 2006.238.08:24:28.58#ibcon#flushed, iclass 15, count 0 2006.238.08:24:28.58#ibcon#about to write, iclass 15, count 0 2006.238.08:24:28.58#ibcon#wrote, iclass 15, count 0 2006.238.08:24:28.58#ibcon#about to read 3, iclass 15, count 0 2006.238.08:24:28.62#ibcon#read 3, iclass 15, count 0 2006.238.08:24:28.62#ibcon#about to read 4, iclass 15, count 0 2006.238.08:24:28.62#ibcon#read 4, iclass 15, count 0 2006.238.08:24:28.62#ibcon#about to read 5, iclass 15, count 0 2006.238.08:24:28.62#ibcon#read 5, iclass 15, count 0 2006.238.08:24:28.62#ibcon#about to read 6, iclass 15, count 0 2006.238.08:24:28.62#ibcon#read 6, iclass 15, count 0 2006.238.08:24:28.62#ibcon#end of sib2, iclass 15, count 0 2006.238.08:24:28.62#ibcon#*after write, iclass 15, count 0 2006.238.08:24:28.62#ibcon#*before return 0, iclass 15, count 0 2006.238.08:24:28.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:24:28.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:24:28.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:24:28.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:24:28.62$vc4f8/va=3,7 2006.238.08:24:28.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.08:24:28.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.08:24:28.62#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:28.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:24:28.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:24:28.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:24:28.68#ibcon#enter wrdev, iclass 17, count 2 2006.238.08:24:28.68#ibcon#first serial, iclass 17, count 2 2006.238.08:24:28.68#ibcon#enter sib2, iclass 17, count 2 2006.238.08:24:28.68#ibcon#flushed, iclass 17, count 2 2006.238.08:24:28.68#ibcon#about to write, iclass 17, count 2 2006.238.08:24:28.68#ibcon#wrote, iclass 17, count 2 2006.238.08:24:28.68#ibcon#about to read 3, iclass 17, count 2 2006.238.08:24:28.70#ibcon#read 3, iclass 17, count 2 2006.238.08:24:28.70#ibcon#about to read 4, iclass 17, count 2 2006.238.08:24:28.70#ibcon#read 4, iclass 17, count 2 2006.238.08:24:28.70#ibcon#about to read 5, iclass 17, count 2 2006.238.08:24:28.70#ibcon#read 5, iclass 17, count 2 2006.238.08:24:28.70#ibcon#about to read 6, iclass 17, count 2 2006.238.08:24:28.70#ibcon#read 6, iclass 17, count 2 2006.238.08:24:28.70#ibcon#end of sib2, iclass 17, count 2 2006.238.08:24:28.70#ibcon#*mode == 0, iclass 17, count 2 2006.238.08:24:28.70#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.08:24:28.70#ibcon#[25=AT03-07\r\n] 2006.238.08:24:28.70#ibcon#*before write, iclass 17, count 2 2006.238.08:24:28.70#ibcon#enter sib2, iclass 17, count 2 2006.238.08:24:28.70#ibcon#flushed, iclass 17, count 2 2006.238.08:24:28.70#ibcon#about to write, iclass 17, count 2 2006.238.08:24:28.70#ibcon#wrote, iclass 17, count 2 2006.238.08:24:28.70#ibcon#about to read 3, iclass 17, count 2 2006.238.08:24:28.73#ibcon#read 3, iclass 17, count 2 2006.238.08:24:28.73#ibcon#about to read 4, iclass 17, count 2 2006.238.08:24:28.73#ibcon#read 4, iclass 17, count 2 2006.238.08:24:28.73#ibcon#about to read 5, iclass 17, count 2 2006.238.08:24:28.73#ibcon#read 5, iclass 17, count 2 2006.238.08:24:28.73#ibcon#about to read 6, iclass 17, count 2 2006.238.08:24:28.73#ibcon#read 6, iclass 17, count 2 2006.238.08:24:28.73#ibcon#end of sib2, iclass 17, count 2 2006.238.08:24:28.73#ibcon#*after write, iclass 17, count 2 2006.238.08:24:28.73#ibcon#*before return 0, iclass 17, count 2 2006.238.08:24:28.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:24:28.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:24:28.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.08:24:28.73#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:28.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:24:28.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:24:28.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:24:28.85#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:24:28.85#ibcon#first serial, iclass 17, count 0 2006.238.08:24:28.85#ibcon#enter sib2, iclass 17, count 0 2006.238.08:24:28.85#ibcon#flushed, iclass 17, count 0 2006.238.08:24:28.85#ibcon#about to write, iclass 17, count 0 2006.238.08:24:28.85#ibcon#wrote, iclass 17, count 0 2006.238.08:24:28.85#ibcon#about to read 3, iclass 17, count 0 2006.238.08:24:28.87#ibcon#read 3, iclass 17, count 0 2006.238.08:24:28.87#ibcon#about to read 4, iclass 17, count 0 2006.238.08:24:28.87#ibcon#read 4, iclass 17, count 0 2006.238.08:24:28.87#ibcon#about to read 5, iclass 17, count 0 2006.238.08:24:28.87#ibcon#read 5, iclass 17, count 0 2006.238.08:24:28.87#ibcon#about to read 6, iclass 17, count 0 2006.238.08:24:28.87#ibcon#read 6, iclass 17, count 0 2006.238.08:24:28.87#ibcon#end of sib2, iclass 17, count 0 2006.238.08:24:28.87#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:24:28.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:24:28.87#ibcon#[25=USB\r\n] 2006.238.08:24:28.87#ibcon#*before write, iclass 17, count 0 2006.238.08:24:28.87#ibcon#enter sib2, iclass 17, count 0 2006.238.08:24:28.87#ibcon#flushed, iclass 17, count 0 2006.238.08:24:28.87#ibcon#about to write, iclass 17, count 0 2006.238.08:24:28.87#ibcon#wrote, iclass 17, count 0 2006.238.08:24:28.87#ibcon#about to read 3, iclass 17, count 0 2006.238.08:24:28.90#ibcon#read 3, iclass 17, count 0 2006.238.08:24:28.90#ibcon#about to read 4, iclass 17, count 0 2006.238.08:24:28.90#ibcon#read 4, iclass 17, count 0 2006.238.08:24:28.90#ibcon#about to read 5, iclass 17, count 0 2006.238.08:24:28.90#ibcon#read 5, iclass 17, count 0 2006.238.08:24:28.90#ibcon#about to read 6, iclass 17, count 0 2006.238.08:24:28.90#ibcon#read 6, iclass 17, count 0 2006.238.08:24:28.90#ibcon#end of sib2, iclass 17, count 0 2006.238.08:24:28.90#ibcon#*after write, iclass 17, count 0 2006.238.08:24:28.90#ibcon#*before return 0, iclass 17, count 0 2006.238.08:24:28.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:24:28.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:24:28.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:24:28.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:24:28.90$vc4f8/valo=4,832.99 2006.238.08:24:28.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.238.08:24:28.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.238.08:24:28.90#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:28.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:24:28.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:24:28.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:24:28.90#ibcon#enter wrdev, iclass 19, count 0 2006.238.08:24:28.90#ibcon#first serial, iclass 19, count 0 2006.238.08:24:28.90#ibcon#enter sib2, iclass 19, count 0 2006.238.08:24:28.90#ibcon#flushed, iclass 19, count 0 2006.238.08:24:28.90#ibcon#about to write, iclass 19, count 0 2006.238.08:24:28.90#ibcon#wrote, iclass 19, count 0 2006.238.08:24:28.90#ibcon#about to read 3, iclass 19, count 0 2006.238.08:24:28.92#ibcon#read 3, iclass 19, count 0 2006.238.08:24:28.92#ibcon#about to read 4, iclass 19, count 0 2006.238.08:24:28.92#ibcon#read 4, iclass 19, count 0 2006.238.08:24:28.92#ibcon#about to read 5, iclass 19, count 0 2006.238.08:24:28.92#ibcon#read 5, iclass 19, count 0 2006.238.08:24:28.92#ibcon#about to read 6, iclass 19, count 0 2006.238.08:24:28.92#ibcon#read 6, iclass 19, count 0 2006.238.08:24:28.92#ibcon#end of sib2, iclass 19, count 0 2006.238.08:24:28.92#ibcon#*mode == 0, iclass 19, count 0 2006.238.08:24:28.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.238.08:24:28.92#ibcon#[26=FRQ=04,832.99\r\n] 2006.238.08:24:28.92#ibcon#*before write, iclass 19, count 0 2006.238.08:24:28.92#ibcon#enter sib2, iclass 19, count 0 2006.238.08:24:28.92#ibcon#flushed, iclass 19, count 0 2006.238.08:24:28.92#ibcon#about to write, iclass 19, count 0 2006.238.08:24:28.92#ibcon#wrote, iclass 19, count 0 2006.238.08:24:28.92#ibcon#about to read 3, iclass 19, count 0 2006.238.08:24:28.96#ibcon#read 3, iclass 19, count 0 2006.238.08:24:28.96#ibcon#about to read 4, iclass 19, count 0 2006.238.08:24:28.96#ibcon#read 4, iclass 19, count 0 2006.238.08:24:28.96#ibcon#about to read 5, iclass 19, count 0 2006.238.08:24:28.96#ibcon#read 5, iclass 19, count 0 2006.238.08:24:28.96#ibcon#about to read 6, iclass 19, count 0 2006.238.08:24:28.96#ibcon#read 6, iclass 19, count 0 2006.238.08:24:28.96#ibcon#end of sib2, iclass 19, count 0 2006.238.08:24:28.96#ibcon#*after write, iclass 19, count 0 2006.238.08:24:28.96#ibcon#*before return 0, iclass 19, count 0 2006.238.08:24:28.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:24:28.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.238.08:24:28.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.238.08:24:28.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.238.08:24:28.96$vc4f8/va=4,7 2006.238.08:24:28.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.238.08:24:28.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.238.08:24:28.96#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:28.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:24:29.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:24:29.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:24:29.02#ibcon#enter wrdev, iclass 21, count 2 2006.238.08:24:29.02#ibcon#first serial, iclass 21, count 2 2006.238.08:24:29.02#ibcon#enter sib2, iclass 21, count 2 2006.238.08:24:29.02#ibcon#flushed, iclass 21, count 2 2006.238.08:24:29.02#ibcon#about to write, iclass 21, count 2 2006.238.08:24:29.02#ibcon#wrote, iclass 21, count 2 2006.238.08:24:29.02#ibcon#about to read 3, iclass 21, count 2 2006.238.08:24:29.04#ibcon#read 3, iclass 21, count 2 2006.238.08:24:29.04#ibcon#about to read 4, iclass 21, count 2 2006.238.08:24:29.04#ibcon#read 4, iclass 21, count 2 2006.238.08:24:29.04#ibcon#about to read 5, iclass 21, count 2 2006.238.08:24:29.04#ibcon#read 5, iclass 21, count 2 2006.238.08:24:29.04#ibcon#about to read 6, iclass 21, count 2 2006.238.08:24:29.04#ibcon#read 6, iclass 21, count 2 2006.238.08:24:29.04#ibcon#end of sib2, iclass 21, count 2 2006.238.08:24:29.04#ibcon#*mode == 0, iclass 21, count 2 2006.238.08:24:29.04#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.238.08:24:29.04#ibcon#[25=AT04-07\r\n] 2006.238.08:24:29.04#ibcon#*before write, iclass 21, count 2 2006.238.08:24:29.04#ibcon#enter sib2, iclass 21, count 2 2006.238.08:24:29.04#ibcon#flushed, iclass 21, count 2 2006.238.08:24:29.04#ibcon#about to write, iclass 21, count 2 2006.238.08:24:29.04#ibcon#wrote, iclass 21, count 2 2006.238.08:24:29.04#ibcon#about to read 3, iclass 21, count 2 2006.238.08:24:29.07#ibcon#read 3, iclass 21, count 2 2006.238.08:24:29.07#ibcon#about to read 4, iclass 21, count 2 2006.238.08:24:29.07#ibcon#read 4, iclass 21, count 2 2006.238.08:24:29.07#ibcon#about to read 5, iclass 21, count 2 2006.238.08:24:29.07#ibcon#read 5, iclass 21, count 2 2006.238.08:24:29.07#ibcon#about to read 6, iclass 21, count 2 2006.238.08:24:29.07#ibcon#read 6, iclass 21, count 2 2006.238.08:24:29.07#ibcon#end of sib2, iclass 21, count 2 2006.238.08:24:29.07#ibcon#*after write, iclass 21, count 2 2006.238.08:24:29.07#ibcon#*before return 0, iclass 21, count 2 2006.238.08:24:29.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:24:29.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.238.08:24:29.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.238.08:24:29.07#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:29.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:24:29.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:24:29.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:24:29.19#ibcon#enter wrdev, iclass 21, count 0 2006.238.08:24:29.19#ibcon#first serial, iclass 21, count 0 2006.238.08:24:29.19#ibcon#enter sib2, iclass 21, count 0 2006.238.08:24:29.19#ibcon#flushed, iclass 21, count 0 2006.238.08:24:29.19#ibcon#about to write, iclass 21, count 0 2006.238.08:24:29.19#ibcon#wrote, iclass 21, count 0 2006.238.08:24:29.19#ibcon#about to read 3, iclass 21, count 0 2006.238.08:24:29.21#ibcon#read 3, iclass 21, count 0 2006.238.08:24:29.21#ibcon#about to read 4, iclass 21, count 0 2006.238.08:24:29.21#ibcon#read 4, iclass 21, count 0 2006.238.08:24:29.21#ibcon#about to read 5, iclass 21, count 0 2006.238.08:24:29.21#ibcon#read 5, iclass 21, count 0 2006.238.08:24:29.21#ibcon#about to read 6, iclass 21, count 0 2006.238.08:24:29.21#ibcon#read 6, iclass 21, count 0 2006.238.08:24:29.21#ibcon#end of sib2, iclass 21, count 0 2006.238.08:24:29.21#ibcon#*mode == 0, iclass 21, count 0 2006.238.08:24:29.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.238.08:24:29.21#ibcon#[25=USB\r\n] 2006.238.08:24:29.21#ibcon#*before write, iclass 21, count 0 2006.238.08:24:29.21#ibcon#enter sib2, iclass 21, count 0 2006.238.08:24:29.21#ibcon#flushed, iclass 21, count 0 2006.238.08:24:29.21#ibcon#about to write, iclass 21, count 0 2006.238.08:24:29.21#ibcon#wrote, iclass 21, count 0 2006.238.08:24:29.21#ibcon#about to read 3, iclass 21, count 0 2006.238.08:24:29.24#ibcon#read 3, iclass 21, count 0 2006.238.08:24:29.24#ibcon#about to read 4, iclass 21, count 0 2006.238.08:24:29.24#ibcon#read 4, iclass 21, count 0 2006.238.08:24:29.24#ibcon#about to read 5, iclass 21, count 0 2006.238.08:24:29.24#ibcon#read 5, iclass 21, count 0 2006.238.08:24:29.24#ibcon#about to read 6, iclass 21, count 0 2006.238.08:24:29.24#ibcon#read 6, iclass 21, count 0 2006.238.08:24:29.24#ibcon#end of sib2, iclass 21, count 0 2006.238.08:24:29.24#ibcon#*after write, iclass 21, count 0 2006.238.08:24:29.24#ibcon#*before return 0, iclass 21, count 0 2006.238.08:24:29.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:24:29.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.238.08:24:29.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.238.08:24:29.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.238.08:24:29.24$vc4f8/valo=5,652.99 2006.238.08:24:29.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.238.08:24:29.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.238.08:24:29.24#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:29.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:24:29.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:24:29.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:24:29.24#ibcon#enter wrdev, iclass 23, count 0 2006.238.08:24:29.24#ibcon#first serial, iclass 23, count 0 2006.238.08:24:29.24#ibcon#enter sib2, iclass 23, count 0 2006.238.08:24:29.24#ibcon#flushed, iclass 23, count 0 2006.238.08:24:29.24#ibcon#about to write, iclass 23, count 0 2006.238.08:24:29.24#ibcon#wrote, iclass 23, count 0 2006.238.08:24:29.24#ibcon#about to read 3, iclass 23, count 0 2006.238.08:24:29.26#ibcon#read 3, iclass 23, count 0 2006.238.08:24:29.26#ibcon#about to read 4, iclass 23, count 0 2006.238.08:24:29.26#ibcon#read 4, iclass 23, count 0 2006.238.08:24:29.26#ibcon#about to read 5, iclass 23, count 0 2006.238.08:24:29.26#ibcon#read 5, iclass 23, count 0 2006.238.08:24:29.26#ibcon#about to read 6, iclass 23, count 0 2006.238.08:24:29.26#ibcon#read 6, iclass 23, count 0 2006.238.08:24:29.26#ibcon#end of sib2, iclass 23, count 0 2006.238.08:24:29.26#ibcon#*mode == 0, iclass 23, count 0 2006.238.08:24:29.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.238.08:24:29.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.238.08:24:29.26#ibcon#*before write, iclass 23, count 0 2006.238.08:24:29.26#ibcon#enter sib2, iclass 23, count 0 2006.238.08:24:29.26#ibcon#flushed, iclass 23, count 0 2006.238.08:24:29.26#ibcon#about to write, iclass 23, count 0 2006.238.08:24:29.26#ibcon#wrote, iclass 23, count 0 2006.238.08:24:29.26#ibcon#about to read 3, iclass 23, count 0 2006.238.08:24:29.30#ibcon#read 3, iclass 23, count 0 2006.238.08:24:29.30#ibcon#about to read 4, iclass 23, count 0 2006.238.08:24:29.30#ibcon#read 4, iclass 23, count 0 2006.238.08:24:29.30#ibcon#about to read 5, iclass 23, count 0 2006.238.08:24:29.30#ibcon#read 5, iclass 23, count 0 2006.238.08:24:29.30#ibcon#about to read 6, iclass 23, count 0 2006.238.08:24:29.30#ibcon#read 6, iclass 23, count 0 2006.238.08:24:29.30#ibcon#end of sib2, iclass 23, count 0 2006.238.08:24:29.30#ibcon#*after write, iclass 23, count 0 2006.238.08:24:29.30#ibcon#*before return 0, iclass 23, count 0 2006.238.08:24:29.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:24:29.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.238.08:24:29.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.238.08:24:29.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.238.08:24:29.30$vc4f8/va=5,8 2006.238.08:24:29.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.238.08:24:29.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.238.08:24:29.30#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:29.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:24:29.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:24:29.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:24:29.36#ibcon#enter wrdev, iclass 25, count 2 2006.238.08:24:29.36#ibcon#first serial, iclass 25, count 2 2006.238.08:24:29.36#ibcon#enter sib2, iclass 25, count 2 2006.238.08:24:29.36#ibcon#flushed, iclass 25, count 2 2006.238.08:24:29.36#ibcon#about to write, iclass 25, count 2 2006.238.08:24:29.36#ibcon#wrote, iclass 25, count 2 2006.238.08:24:29.36#ibcon#about to read 3, iclass 25, count 2 2006.238.08:24:29.38#ibcon#read 3, iclass 25, count 2 2006.238.08:24:29.38#ibcon#about to read 4, iclass 25, count 2 2006.238.08:24:29.38#ibcon#read 4, iclass 25, count 2 2006.238.08:24:29.38#ibcon#about to read 5, iclass 25, count 2 2006.238.08:24:29.38#ibcon#read 5, iclass 25, count 2 2006.238.08:24:29.38#ibcon#about to read 6, iclass 25, count 2 2006.238.08:24:29.38#ibcon#read 6, iclass 25, count 2 2006.238.08:24:29.38#ibcon#end of sib2, iclass 25, count 2 2006.238.08:24:29.38#ibcon#*mode == 0, iclass 25, count 2 2006.238.08:24:29.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.238.08:24:29.38#ibcon#[25=AT05-08\r\n] 2006.238.08:24:29.38#ibcon#*before write, iclass 25, count 2 2006.238.08:24:29.38#ibcon#enter sib2, iclass 25, count 2 2006.238.08:24:29.38#ibcon#flushed, iclass 25, count 2 2006.238.08:24:29.38#ibcon#about to write, iclass 25, count 2 2006.238.08:24:29.38#ibcon#wrote, iclass 25, count 2 2006.238.08:24:29.38#ibcon#about to read 3, iclass 25, count 2 2006.238.08:24:29.41#ibcon#read 3, iclass 25, count 2 2006.238.08:24:29.41#ibcon#about to read 4, iclass 25, count 2 2006.238.08:24:29.41#ibcon#read 4, iclass 25, count 2 2006.238.08:24:29.41#ibcon#about to read 5, iclass 25, count 2 2006.238.08:24:29.41#ibcon#read 5, iclass 25, count 2 2006.238.08:24:29.41#ibcon#about to read 6, iclass 25, count 2 2006.238.08:24:29.41#ibcon#read 6, iclass 25, count 2 2006.238.08:24:29.41#ibcon#end of sib2, iclass 25, count 2 2006.238.08:24:29.41#ibcon#*after write, iclass 25, count 2 2006.238.08:24:29.41#ibcon#*before return 0, iclass 25, count 2 2006.238.08:24:29.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:24:29.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.238.08:24:29.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.238.08:24:29.41#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:29.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:24:29.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:24:29.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:24:29.53#ibcon#enter wrdev, iclass 25, count 0 2006.238.08:24:29.53#ibcon#first serial, iclass 25, count 0 2006.238.08:24:29.53#ibcon#enter sib2, iclass 25, count 0 2006.238.08:24:29.53#ibcon#flushed, iclass 25, count 0 2006.238.08:24:29.53#ibcon#about to write, iclass 25, count 0 2006.238.08:24:29.53#ibcon#wrote, iclass 25, count 0 2006.238.08:24:29.53#ibcon#about to read 3, iclass 25, count 0 2006.238.08:24:29.55#ibcon#read 3, iclass 25, count 0 2006.238.08:24:29.55#ibcon#about to read 4, iclass 25, count 0 2006.238.08:24:29.55#ibcon#read 4, iclass 25, count 0 2006.238.08:24:29.55#ibcon#about to read 5, iclass 25, count 0 2006.238.08:24:29.55#ibcon#read 5, iclass 25, count 0 2006.238.08:24:29.55#ibcon#about to read 6, iclass 25, count 0 2006.238.08:24:29.55#ibcon#read 6, iclass 25, count 0 2006.238.08:24:29.55#ibcon#end of sib2, iclass 25, count 0 2006.238.08:24:29.55#ibcon#*mode == 0, iclass 25, count 0 2006.238.08:24:29.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.238.08:24:29.55#ibcon#[25=USB\r\n] 2006.238.08:24:29.55#ibcon#*before write, iclass 25, count 0 2006.238.08:24:29.55#ibcon#enter sib2, iclass 25, count 0 2006.238.08:24:29.55#ibcon#flushed, iclass 25, count 0 2006.238.08:24:29.55#ibcon#about to write, iclass 25, count 0 2006.238.08:24:29.55#ibcon#wrote, iclass 25, count 0 2006.238.08:24:29.55#ibcon#about to read 3, iclass 25, count 0 2006.238.08:24:29.58#ibcon#read 3, iclass 25, count 0 2006.238.08:24:29.58#ibcon#about to read 4, iclass 25, count 0 2006.238.08:24:29.58#ibcon#read 4, iclass 25, count 0 2006.238.08:24:29.58#ibcon#about to read 5, iclass 25, count 0 2006.238.08:24:29.58#ibcon#read 5, iclass 25, count 0 2006.238.08:24:29.58#ibcon#about to read 6, iclass 25, count 0 2006.238.08:24:29.58#ibcon#read 6, iclass 25, count 0 2006.238.08:24:29.58#ibcon#end of sib2, iclass 25, count 0 2006.238.08:24:29.58#ibcon#*after write, iclass 25, count 0 2006.238.08:24:29.58#ibcon#*before return 0, iclass 25, count 0 2006.238.08:24:29.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:24:29.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.238.08:24:29.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.238.08:24:29.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.238.08:24:29.58$vc4f8/valo=6,772.99 2006.238.08:24:29.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.08:24:29.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.08:24:29.58#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:29.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:24:29.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:24:29.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:24:29.58#ibcon#enter wrdev, iclass 27, count 0 2006.238.08:24:29.58#ibcon#first serial, iclass 27, count 0 2006.238.08:24:29.58#ibcon#enter sib2, iclass 27, count 0 2006.238.08:24:29.58#ibcon#flushed, iclass 27, count 0 2006.238.08:24:29.58#ibcon#about to write, iclass 27, count 0 2006.238.08:24:29.58#ibcon#wrote, iclass 27, count 0 2006.238.08:24:29.58#ibcon#about to read 3, iclass 27, count 0 2006.238.08:24:29.60#ibcon#read 3, iclass 27, count 0 2006.238.08:24:29.60#ibcon#about to read 4, iclass 27, count 0 2006.238.08:24:29.60#ibcon#read 4, iclass 27, count 0 2006.238.08:24:29.60#ibcon#about to read 5, iclass 27, count 0 2006.238.08:24:29.60#ibcon#read 5, iclass 27, count 0 2006.238.08:24:29.60#ibcon#about to read 6, iclass 27, count 0 2006.238.08:24:29.60#ibcon#read 6, iclass 27, count 0 2006.238.08:24:29.60#ibcon#end of sib2, iclass 27, count 0 2006.238.08:24:29.60#ibcon#*mode == 0, iclass 27, count 0 2006.238.08:24:29.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.08:24:29.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.238.08:24:29.60#ibcon#*before write, iclass 27, count 0 2006.238.08:24:29.60#ibcon#enter sib2, iclass 27, count 0 2006.238.08:24:29.60#ibcon#flushed, iclass 27, count 0 2006.238.08:24:29.60#ibcon#about to write, iclass 27, count 0 2006.238.08:24:29.60#ibcon#wrote, iclass 27, count 0 2006.238.08:24:29.60#ibcon#about to read 3, iclass 27, count 0 2006.238.08:24:29.64#ibcon#read 3, iclass 27, count 0 2006.238.08:24:29.64#ibcon#about to read 4, iclass 27, count 0 2006.238.08:24:29.64#ibcon#read 4, iclass 27, count 0 2006.238.08:24:29.64#ibcon#about to read 5, iclass 27, count 0 2006.238.08:24:29.64#ibcon#read 5, iclass 27, count 0 2006.238.08:24:29.64#ibcon#about to read 6, iclass 27, count 0 2006.238.08:24:29.64#ibcon#read 6, iclass 27, count 0 2006.238.08:24:29.64#ibcon#end of sib2, iclass 27, count 0 2006.238.08:24:29.64#ibcon#*after write, iclass 27, count 0 2006.238.08:24:29.64#ibcon#*before return 0, iclass 27, count 0 2006.238.08:24:29.64#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:24:29.64#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:24:29.64#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.08:24:29.64#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.08:24:29.64$vc4f8/va=6,7 2006.238.08:24:29.64#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.08:24:29.64#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.08:24:29.64#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:29.64#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:24:29.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:24:29.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:24:29.70#ibcon#enter wrdev, iclass 29, count 2 2006.238.08:24:29.70#ibcon#first serial, iclass 29, count 2 2006.238.08:24:29.70#ibcon#enter sib2, iclass 29, count 2 2006.238.08:24:29.70#ibcon#flushed, iclass 29, count 2 2006.238.08:24:29.70#ibcon#about to write, iclass 29, count 2 2006.238.08:24:29.70#ibcon#wrote, iclass 29, count 2 2006.238.08:24:29.70#ibcon#about to read 3, iclass 29, count 2 2006.238.08:24:29.72#ibcon#read 3, iclass 29, count 2 2006.238.08:24:29.72#ibcon#about to read 4, iclass 29, count 2 2006.238.08:24:29.72#ibcon#read 4, iclass 29, count 2 2006.238.08:24:29.72#ibcon#about to read 5, iclass 29, count 2 2006.238.08:24:29.72#ibcon#read 5, iclass 29, count 2 2006.238.08:24:29.72#ibcon#about to read 6, iclass 29, count 2 2006.238.08:24:29.72#ibcon#read 6, iclass 29, count 2 2006.238.08:24:29.72#ibcon#end of sib2, iclass 29, count 2 2006.238.08:24:29.72#ibcon#*mode == 0, iclass 29, count 2 2006.238.08:24:29.72#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.08:24:29.72#ibcon#[25=AT06-07\r\n] 2006.238.08:24:29.72#ibcon#*before write, iclass 29, count 2 2006.238.08:24:29.72#ibcon#enter sib2, iclass 29, count 2 2006.238.08:24:29.72#ibcon#flushed, iclass 29, count 2 2006.238.08:24:29.72#ibcon#about to write, iclass 29, count 2 2006.238.08:24:29.72#ibcon#wrote, iclass 29, count 2 2006.238.08:24:29.72#ibcon#about to read 3, iclass 29, count 2 2006.238.08:24:29.75#ibcon#read 3, iclass 29, count 2 2006.238.08:24:29.75#ibcon#about to read 4, iclass 29, count 2 2006.238.08:24:29.75#ibcon#read 4, iclass 29, count 2 2006.238.08:24:29.75#ibcon#about to read 5, iclass 29, count 2 2006.238.08:24:29.75#ibcon#read 5, iclass 29, count 2 2006.238.08:24:29.75#ibcon#about to read 6, iclass 29, count 2 2006.238.08:24:29.75#ibcon#read 6, iclass 29, count 2 2006.238.08:24:29.75#ibcon#end of sib2, iclass 29, count 2 2006.238.08:24:29.75#ibcon#*after write, iclass 29, count 2 2006.238.08:24:29.75#ibcon#*before return 0, iclass 29, count 2 2006.238.08:24:29.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:24:29.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:24:29.75#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.08:24:29.75#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:29.75#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:24:29.87#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:24:29.87#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:24:29.87#ibcon#enter wrdev, iclass 29, count 0 2006.238.08:24:29.87#ibcon#first serial, iclass 29, count 0 2006.238.08:24:29.87#ibcon#enter sib2, iclass 29, count 0 2006.238.08:24:29.87#ibcon#flushed, iclass 29, count 0 2006.238.08:24:29.87#ibcon#about to write, iclass 29, count 0 2006.238.08:24:29.87#ibcon#wrote, iclass 29, count 0 2006.238.08:24:29.87#ibcon#about to read 3, iclass 29, count 0 2006.238.08:24:29.89#ibcon#read 3, iclass 29, count 0 2006.238.08:24:29.89#ibcon#about to read 4, iclass 29, count 0 2006.238.08:24:29.89#ibcon#read 4, iclass 29, count 0 2006.238.08:24:29.89#ibcon#about to read 5, iclass 29, count 0 2006.238.08:24:29.89#ibcon#read 5, iclass 29, count 0 2006.238.08:24:29.89#ibcon#about to read 6, iclass 29, count 0 2006.238.08:24:29.89#ibcon#read 6, iclass 29, count 0 2006.238.08:24:29.89#ibcon#end of sib2, iclass 29, count 0 2006.238.08:24:29.89#ibcon#*mode == 0, iclass 29, count 0 2006.238.08:24:29.89#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.08:24:29.89#ibcon#[25=USB\r\n] 2006.238.08:24:29.89#ibcon#*before write, iclass 29, count 0 2006.238.08:24:29.89#ibcon#enter sib2, iclass 29, count 0 2006.238.08:24:29.89#ibcon#flushed, iclass 29, count 0 2006.238.08:24:29.89#ibcon#about to write, iclass 29, count 0 2006.238.08:24:29.89#ibcon#wrote, iclass 29, count 0 2006.238.08:24:29.89#ibcon#about to read 3, iclass 29, count 0 2006.238.08:24:29.92#ibcon#read 3, iclass 29, count 0 2006.238.08:24:29.92#ibcon#about to read 4, iclass 29, count 0 2006.238.08:24:29.92#ibcon#read 4, iclass 29, count 0 2006.238.08:24:29.92#ibcon#about to read 5, iclass 29, count 0 2006.238.08:24:29.92#ibcon#read 5, iclass 29, count 0 2006.238.08:24:29.92#ibcon#about to read 6, iclass 29, count 0 2006.238.08:24:29.92#ibcon#read 6, iclass 29, count 0 2006.238.08:24:29.92#ibcon#end of sib2, iclass 29, count 0 2006.238.08:24:29.92#ibcon#*after write, iclass 29, count 0 2006.238.08:24:29.92#ibcon#*before return 0, iclass 29, count 0 2006.238.08:24:29.92#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:24:29.92#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:24:29.92#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.08:24:29.92#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.08:24:29.92$vc4f8/valo=7,832.99 2006.238.08:24:29.92#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.08:24:29.92#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.08:24:29.92#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:29.92#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:24:29.92#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:24:29.92#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:24:29.92#ibcon#enter wrdev, iclass 31, count 0 2006.238.08:24:29.92#ibcon#first serial, iclass 31, count 0 2006.238.08:24:29.92#ibcon#enter sib2, iclass 31, count 0 2006.238.08:24:29.92#ibcon#flushed, iclass 31, count 0 2006.238.08:24:29.92#ibcon#about to write, iclass 31, count 0 2006.238.08:24:29.92#ibcon#wrote, iclass 31, count 0 2006.238.08:24:29.92#ibcon#about to read 3, iclass 31, count 0 2006.238.08:24:29.94#ibcon#read 3, iclass 31, count 0 2006.238.08:24:29.94#ibcon#about to read 4, iclass 31, count 0 2006.238.08:24:29.94#ibcon#read 4, iclass 31, count 0 2006.238.08:24:29.94#ibcon#about to read 5, iclass 31, count 0 2006.238.08:24:29.94#ibcon#read 5, iclass 31, count 0 2006.238.08:24:29.94#ibcon#about to read 6, iclass 31, count 0 2006.238.08:24:29.94#ibcon#read 6, iclass 31, count 0 2006.238.08:24:29.94#ibcon#end of sib2, iclass 31, count 0 2006.238.08:24:29.94#ibcon#*mode == 0, iclass 31, count 0 2006.238.08:24:29.94#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.08:24:29.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.238.08:24:29.94#ibcon#*before write, iclass 31, count 0 2006.238.08:24:29.94#ibcon#enter sib2, iclass 31, count 0 2006.238.08:24:29.94#ibcon#flushed, iclass 31, count 0 2006.238.08:24:29.94#ibcon#about to write, iclass 31, count 0 2006.238.08:24:29.94#ibcon#wrote, iclass 31, count 0 2006.238.08:24:29.94#ibcon#about to read 3, iclass 31, count 0 2006.238.08:24:29.98#ibcon#read 3, iclass 31, count 0 2006.238.08:24:29.98#ibcon#about to read 4, iclass 31, count 0 2006.238.08:24:29.98#ibcon#read 4, iclass 31, count 0 2006.238.08:24:29.98#ibcon#about to read 5, iclass 31, count 0 2006.238.08:24:29.98#ibcon#read 5, iclass 31, count 0 2006.238.08:24:29.98#ibcon#about to read 6, iclass 31, count 0 2006.238.08:24:29.98#ibcon#read 6, iclass 31, count 0 2006.238.08:24:29.98#ibcon#end of sib2, iclass 31, count 0 2006.238.08:24:29.98#ibcon#*after write, iclass 31, count 0 2006.238.08:24:29.98#ibcon#*before return 0, iclass 31, count 0 2006.238.08:24:29.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:24:29.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:24:29.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.08:24:29.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.08:24:29.98$vc4f8/va=7,7 2006.238.08:24:29.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.238.08:24:29.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.238.08:24:29.98#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:29.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:24:30.04#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:24:30.04#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:24:30.04#ibcon#enter wrdev, iclass 33, count 2 2006.238.08:24:30.04#ibcon#first serial, iclass 33, count 2 2006.238.08:24:30.04#ibcon#enter sib2, iclass 33, count 2 2006.238.08:24:30.04#ibcon#flushed, iclass 33, count 2 2006.238.08:24:30.04#ibcon#about to write, iclass 33, count 2 2006.238.08:24:30.04#ibcon#wrote, iclass 33, count 2 2006.238.08:24:30.04#ibcon#about to read 3, iclass 33, count 2 2006.238.08:24:30.06#ibcon#read 3, iclass 33, count 2 2006.238.08:24:30.06#ibcon#about to read 4, iclass 33, count 2 2006.238.08:24:30.06#ibcon#read 4, iclass 33, count 2 2006.238.08:24:30.06#ibcon#about to read 5, iclass 33, count 2 2006.238.08:24:30.06#ibcon#read 5, iclass 33, count 2 2006.238.08:24:30.06#ibcon#about to read 6, iclass 33, count 2 2006.238.08:24:30.06#ibcon#read 6, iclass 33, count 2 2006.238.08:24:30.06#ibcon#end of sib2, iclass 33, count 2 2006.238.08:24:30.06#ibcon#*mode == 0, iclass 33, count 2 2006.238.08:24:30.06#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.238.08:24:30.06#ibcon#[25=AT07-07\r\n] 2006.238.08:24:30.06#ibcon#*before write, iclass 33, count 2 2006.238.08:24:30.06#ibcon#enter sib2, iclass 33, count 2 2006.238.08:24:30.06#ibcon#flushed, iclass 33, count 2 2006.238.08:24:30.06#ibcon#about to write, iclass 33, count 2 2006.238.08:24:30.06#ibcon#wrote, iclass 33, count 2 2006.238.08:24:30.06#ibcon#about to read 3, iclass 33, count 2 2006.238.08:24:30.09#ibcon#read 3, iclass 33, count 2 2006.238.08:24:30.09#ibcon#about to read 4, iclass 33, count 2 2006.238.08:24:30.09#ibcon#read 4, iclass 33, count 2 2006.238.08:24:30.09#ibcon#about to read 5, iclass 33, count 2 2006.238.08:24:30.09#ibcon#read 5, iclass 33, count 2 2006.238.08:24:30.09#ibcon#about to read 6, iclass 33, count 2 2006.238.08:24:30.09#ibcon#read 6, iclass 33, count 2 2006.238.08:24:30.09#ibcon#end of sib2, iclass 33, count 2 2006.238.08:24:30.09#ibcon#*after write, iclass 33, count 2 2006.238.08:24:30.09#ibcon#*before return 0, iclass 33, count 2 2006.238.08:24:30.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:24:30.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.238.08:24:30.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.238.08:24:30.09#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:30.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:24:30.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:24:30.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:24:30.21#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:24:30.21#ibcon#first serial, iclass 33, count 0 2006.238.08:24:30.21#ibcon#enter sib2, iclass 33, count 0 2006.238.08:24:30.21#ibcon#flushed, iclass 33, count 0 2006.238.08:24:30.21#ibcon#about to write, iclass 33, count 0 2006.238.08:24:30.21#ibcon#wrote, iclass 33, count 0 2006.238.08:24:30.21#ibcon#about to read 3, iclass 33, count 0 2006.238.08:24:30.23#ibcon#read 3, iclass 33, count 0 2006.238.08:24:30.23#ibcon#about to read 4, iclass 33, count 0 2006.238.08:24:30.23#ibcon#read 4, iclass 33, count 0 2006.238.08:24:30.23#ibcon#about to read 5, iclass 33, count 0 2006.238.08:24:30.23#ibcon#read 5, iclass 33, count 0 2006.238.08:24:30.23#ibcon#about to read 6, iclass 33, count 0 2006.238.08:24:30.23#ibcon#read 6, iclass 33, count 0 2006.238.08:24:30.23#ibcon#end of sib2, iclass 33, count 0 2006.238.08:24:30.23#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:24:30.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:24:30.23#ibcon#[25=USB\r\n] 2006.238.08:24:30.23#ibcon#*before write, iclass 33, count 0 2006.238.08:24:30.23#ibcon#enter sib2, iclass 33, count 0 2006.238.08:24:30.23#ibcon#flushed, iclass 33, count 0 2006.238.08:24:30.23#ibcon#about to write, iclass 33, count 0 2006.238.08:24:30.23#ibcon#wrote, iclass 33, count 0 2006.238.08:24:30.23#ibcon#about to read 3, iclass 33, count 0 2006.238.08:24:30.26#ibcon#read 3, iclass 33, count 0 2006.238.08:24:30.26#ibcon#about to read 4, iclass 33, count 0 2006.238.08:24:30.26#ibcon#read 4, iclass 33, count 0 2006.238.08:24:30.26#ibcon#about to read 5, iclass 33, count 0 2006.238.08:24:30.26#ibcon#read 5, iclass 33, count 0 2006.238.08:24:30.26#ibcon#about to read 6, iclass 33, count 0 2006.238.08:24:30.26#ibcon#read 6, iclass 33, count 0 2006.238.08:24:30.26#ibcon#end of sib2, iclass 33, count 0 2006.238.08:24:30.26#ibcon#*after write, iclass 33, count 0 2006.238.08:24:30.26#ibcon#*before return 0, iclass 33, count 0 2006.238.08:24:30.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:24:30.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.238.08:24:30.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:24:30.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:24:30.26$vc4f8/valo=8,852.99 2006.238.08:24:30.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.238.08:24:30.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.238.08:24:30.26#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:30.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:24:30.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:24:30.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:24:30.26#ibcon#enter wrdev, iclass 35, count 0 2006.238.08:24:30.26#ibcon#first serial, iclass 35, count 0 2006.238.08:24:30.26#ibcon#enter sib2, iclass 35, count 0 2006.238.08:24:30.26#ibcon#flushed, iclass 35, count 0 2006.238.08:24:30.26#ibcon#about to write, iclass 35, count 0 2006.238.08:24:30.26#ibcon#wrote, iclass 35, count 0 2006.238.08:24:30.26#ibcon#about to read 3, iclass 35, count 0 2006.238.08:24:30.28#ibcon#read 3, iclass 35, count 0 2006.238.08:24:30.28#ibcon#about to read 4, iclass 35, count 0 2006.238.08:24:30.28#ibcon#read 4, iclass 35, count 0 2006.238.08:24:30.28#ibcon#about to read 5, iclass 35, count 0 2006.238.08:24:30.28#ibcon#read 5, iclass 35, count 0 2006.238.08:24:30.28#ibcon#about to read 6, iclass 35, count 0 2006.238.08:24:30.28#ibcon#read 6, iclass 35, count 0 2006.238.08:24:30.28#ibcon#end of sib2, iclass 35, count 0 2006.238.08:24:30.28#ibcon#*mode == 0, iclass 35, count 0 2006.238.08:24:30.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.238.08:24:30.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.238.08:24:30.28#ibcon#*before write, iclass 35, count 0 2006.238.08:24:30.28#ibcon#enter sib2, iclass 35, count 0 2006.238.08:24:30.28#ibcon#flushed, iclass 35, count 0 2006.238.08:24:30.28#ibcon#about to write, iclass 35, count 0 2006.238.08:24:30.28#ibcon#wrote, iclass 35, count 0 2006.238.08:24:30.28#ibcon#about to read 3, iclass 35, count 0 2006.238.08:24:30.32#ibcon#read 3, iclass 35, count 0 2006.238.08:24:30.32#ibcon#about to read 4, iclass 35, count 0 2006.238.08:24:30.32#ibcon#read 4, iclass 35, count 0 2006.238.08:24:30.32#ibcon#about to read 5, iclass 35, count 0 2006.238.08:24:30.32#ibcon#read 5, iclass 35, count 0 2006.238.08:24:30.32#ibcon#about to read 6, iclass 35, count 0 2006.238.08:24:30.32#ibcon#read 6, iclass 35, count 0 2006.238.08:24:30.32#ibcon#end of sib2, iclass 35, count 0 2006.238.08:24:30.32#ibcon#*after write, iclass 35, count 0 2006.238.08:24:30.32#ibcon#*before return 0, iclass 35, count 0 2006.238.08:24:30.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:24:30.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.238.08:24:30.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.238.08:24:30.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.238.08:24:30.32$vc4f8/va=8,7 2006.238.08:24:30.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.238.08:24:30.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.238.08:24:30.32#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:30.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:24:30.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:24:30.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:24:30.38#ibcon#enter wrdev, iclass 37, count 2 2006.238.08:24:30.38#ibcon#first serial, iclass 37, count 2 2006.238.08:24:30.38#ibcon#enter sib2, iclass 37, count 2 2006.238.08:24:30.38#ibcon#flushed, iclass 37, count 2 2006.238.08:24:30.38#ibcon#about to write, iclass 37, count 2 2006.238.08:24:30.38#ibcon#wrote, iclass 37, count 2 2006.238.08:24:30.38#ibcon#about to read 3, iclass 37, count 2 2006.238.08:24:30.40#ibcon#read 3, iclass 37, count 2 2006.238.08:24:30.40#ibcon#about to read 4, iclass 37, count 2 2006.238.08:24:30.40#ibcon#read 4, iclass 37, count 2 2006.238.08:24:30.40#ibcon#about to read 5, iclass 37, count 2 2006.238.08:24:30.40#ibcon#read 5, iclass 37, count 2 2006.238.08:24:30.40#ibcon#about to read 6, iclass 37, count 2 2006.238.08:24:30.40#ibcon#read 6, iclass 37, count 2 2006.238.08:24:30.40#ibcon#end of sib2, iclass 37, count 2 2006.238.08:24:30.40#ibcon#*mode == 0, iclass 37, count 2 2006.238.08:24:30.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.238.08:24:30.40#ibcon#[25=AT08-07\r\n] 2006.238.08:24:30.40#ibcon#*before write, iclass 37, count 2 2006.238.08:24:30.40#ibcon#enter sib2, iclass 37, count 2 2006.238.08:24:30.40#ibcon#flushed, iclass 37, count 2 2006.238.08:24:30.40#ibcon#about to write, iclass 37, count 2 2006.238.08:24:30.40#ibcon#wrote, iclass 37, count 2 2006.238.08:24:30.40#ibcon#about to read 3, iclass 37, count 2 2006.238.08:24:30.43#ibcon#read 3, iclass 37, count 2 2006.238.08:24:30.43#ibcon#about to read 4, iclass 37, count 2 2006.238.08:24:30.43#ibcon#read 4, iclass 37, count 2 2006.238.08:24:30.43#ibcon#about to read 5, iclass 37, count 2 2006.238.08:24:30.43#ibcon#read 5, iclass 37, count 2 2006.238.08:24:30.43#ibcon#about to read 6, iclass 37, count 2 2006.238.08:24:30.43#ibcon#read 6, iclass 37, count 2 2006.238.08:24:30.43#ibcon#end of sib2, iclass 37, count 2 2006.238.08:24:30.43#ibcon#*after write, iclass 37, count 2 2006.238.08:24:30.43#ibcon#*before return 0, iclass 37, count 2 2006.238.08:24:30.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:24:30.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.238.08:24:30.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.238.08:24:30.43#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:30.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:24:30.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:24:30.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:24:30.55#ibcon#enter wrdev, iclass 37, count 0 2006.238.08:24:30.55#ibcon#first serial, iclass 37, count 0 2006.238.08:24:30.55#ibcon#enter sib2, iclass 37, count 0 2006.238.08:24:30.55#ibcon#flushed, iclass 37, count 0 2006.238.08:24:30.55#ibcon#about to write, iclass 37, count 0 2006.238.08:24:30.55#ibcon#wrote, iclass 37, count 0 2006.238.08:24:30.55#ibcon#about to read 3, iclass 37, count 0 2006.238.08:24:30.57#ibcon#read 3, iclass 37, count 0 2006.238.08:24:30.57#ibcon#about to read 4, iclass 37, count 0 2006.238.08:24:30.57#ibcon#read 4, iclass 37, count 0 2006.238.08:24:30.57#ibcon#about to read 5, iclass 37, count 0 2006.238.08:24:30.57#ibcon#read 5, iclass 37, count 0 2006.238.08:24:30.57#ibcon#about to read 6, iclass 37, count 0 2006.238.08:24:30.57#ibcon#read 6, iclass 37, count 0 2006.238.08:24:30.57#ibcon#end of sib2, iclass 37, count 0 2006.238.08:24:30.57#ibcon#*mode == 0, iclass 37, count 0 2006.238.08:24:30.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.238.08:24:30.57#ibcon#[25=USB\r\n] 2006.238.08:24:30.57#ibcon#*before write, iclass 37, count 0 2006.238.08:24:30.57#ibcon#enter sib2, iclass 37, count 0 2006.238.08:24:30.57#ibcon#flushed, iclass 37, count 0 2006.238.08:24:30.57#ibcon#about to write, iclass 37, count 0 2006.238.08:24:30.57#ibcon#wrote, iclass 37, count 0 2006.238.08:24:30.57#ibcon#about to read 3, iclass 37, count 0 2006.238.08:24:30.60#ibcon#read 3, iclass 37, count 0 2006.238.08:24:30.60#ibcon#about to read 4, iclass 37, count 0 2006.238.08:24:30.60#ibcon#read 4, iclass 37, count 0 2006.238.08:24:30.60#ibcon#about to read 5, iclass 37, count 0 2006.238.08:24:30.60#ibcon#read 5, iclass 37, count 0 2006.238.08:24:30.60#ibcon#about to read 6, iclass 37, count 0 2006.238.08:24:30.60#ibcon#read 6, iclass 37, count 0 2006.238.08:24:30.60#ibcon#end of sib2, iclass 37, count 0 2006.238.08:24:30.60#ibcon#*after write, iclass 37, count 0 2006.238.08:24:30.60#ibcon#*before return 0, iclass 37, count 0 2006.238.08:24:30.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:24:30.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.238.08:24:30.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.238.08:24:30.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.238.08:24:30.60$vc4f8/vblo=1,632.99 2006.238.08:24:30.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.238.08:24:30.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.238.08:24:30.60#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:30.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:24:30.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:24:30.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:24:30.60#ibcon#enter wrdev, iclass 39, count 0 2006.238.08:24:30.60#ibcon#first serial, iclass 39, count 0 2006.238.08:24:30.60#ibcon#enter sib2, iclass 39, count 0 2006.238.08:24:30.60#ibcon#flushed, iclass 39, count 0 2006.238.08:24:30.60#ibcon#about to write, iclass 39, count 0 2006.238.08:24:30.60#ibcon#wrote, iclass 39, count 0 2006.238.08:24:30.60#ibcon#about to read 3, iclass 39, count 0 2006.238.08:24:30.62#ibcon#read 3, iclass 39, count 0 2006.238.08:24:30.62#ibcon#about to read 4, iclass 39, count 0 2006.238.08:24:30.62#ibcon#read 4, iclass 39, count 0 2006.238.08:24:30.62#ibcon#about to read 5, iclass 39, count 0 2006.238.08:24:30.62#ibcon#read 5, iclass 39, count 0 2006.238.08:24:30.62#ibcon#about to read 6, iclass 39, count 0 2006.238.08:24:30.62#ibcon#read 6, iclass 39, count 0 2006.238.08:24:30.62#ibcon#end of sib2, iclass 39, count 0 2006.238.08:24:30.62#ibcon#*mode == 0, iclass 39, count 0 2006.238.08:24:30.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.238.08:24:30.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.238.08:24:30.62#ibcon#*before write, iclass 39, count 0 2006.238.08:24:30.62#ibcon#enter sib2, iclass 39, count 0 2006.238.08:24:30.62#ibcon#flushed, iclass 39, count 0 2006.238.08:24:30.62#ibcon#about to write, iclass 39, count 0 2006.238.08:24:30.62#ibcon#wrote, iclass 39, count 0 2006.238.08:24:30.62#ibcon#about to read 3, iclass 39, count 0 2006.238.08:24:30.66#ibcon#read 3, iclass 39, count 0 2006.238.08:24:30.66#ibcon#about to read 4, iclass 39, count 0 2006.238.08:24:30.66#ibcon#read 4, iclass 39, count 0 2006.238.08:24:30.66#ibcon#about to read 5, iclass 39, count 0 2006.238.08:24:30.66#ibcon#read 5, iclass 39, count 0 2006.238.08:24:30.66#ibcon#about to read 6, iclass 39, count 0 2006.238.08:24:30.66#ibcon#read 6, iclass 39, count 0 2006.238.08:24:30.66#ibcon#end of sib2, iclass 39, count 0 2006.238.08:24:30.66#ibcon#*after write, iclass 39, count 0 2006.238.08:24:30.66#ibcon#*before return 0, iclass 39, count 0 2006.238.08:24:30.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:24:30.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.238.08:24:30.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.238.08:24:30.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.238.08:24:30.66$vc4f8/vb=1,4 2006.238.08:24:30.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.238.08:24:30.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.238.08:24:30.66#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:30.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:24:30.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:24:30.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:24:30.66#ibcon#enter wrdev, iclass 3, count 2 2006.238.08:24:30.66#ibcon#first serial, iclass 3, count 2 2006.238.08:24:30.66#ibcon#enter sib2, iclass 3, count 2 2006.238.08:24:30.66#ibcon#flushed, iclass 3, count 2 2006.238.08:24:30.66#ibcon#about to write, iclass 3, count 2 2006.238.08:24:30.66#ibcon#wrote, iclass 3, count 2 2006.238.08:24:30.66#ibcon#about to read 3, iclass 3, count 2 2006.238.08:24:30.68#ibcon#read 3, iclass 3, count 2 2006.238.08:24:30.68#ibcon#about to read 4, iclass 3, count 2 2006.238.08:24:30.68#ibcon#read 4, iclass 3, count 2 2006.238.08:24:30.68#ibcon#about to read 5, iclass 3, count 2 2006.238.08:24:30.68#ibcon#read 5, iclass 3, count 2 2006.238.08:24:30.68#ibcon#about to read 6, iclass 3, count 2 2006.238.08:24:30.68#ibcon#read 6, iclass 3, count 2 2006.238.08:24:30.68#ibcon#end of sib2, iclass 3, count 2 2006.238.08:24:30.68#ibcon#*mode == 0, iclass 3, count 2 2006.238.08:24:30.68#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.238.08:24:30.68#ibcon#[27=AT01-04\r\n] 2006.238.08:24:30.68#ibcon#*before write, iclass 3, count 2 2006.238.08:24:30.68#ibcon#enter sib2, iclass 3, count 2 2006.238.08:24:30.68#ibcon#flushed, iclass 3, count 2 2006.238.08:24:30.68#ibcon#about to write, iclass 3, count 2 2006.238.08:24:30.68#ibcon#wrote, iclass 3, count 2 2006.238.08:24:30.68#ibcon#about to read 3, iclass 3, count 2 2006.238.08:24:30.71#ibcon#read 3, iclass 3, count 2 2006.238.08:24:30.71#ibcon#about to read 4, iclass 3, count 2 2006.238.08:24:30.71#ibcon#read 4, iclass 3, count 2 2006.238.08:24:30.71#ibcon#about to read 5, iclass 3, count 2 2006.238.08:24:30.71#ibcon#read 5, iclass 3, count 2 2006.238.08:24:30.71#ibcon#about to read 6, iclass 3, count 2 2006.238.08:24:30.71#ibcon#read 6, iclass 3, count 2 2006.238.08:24:30.71#ibcon#end of sib2, iclass 3, count 2 2006.238.08:24:30.71#ibcon#*after write, iclass 3, count 2 2006.238.08:24:30.71#ibcon#*before return 0, iclass 3, count 2 2006.238.08:24:30.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:24:30.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.238.08:24:30.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.238.08:24:30.71#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:30.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:24:30.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:24:30.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:24:30.83#ibcon#enter wrdev, iclass 3, count 0 2006.238.08:24:30.83#ibcon#first serial, iclass 3, count 0 2006.238.08:24:30.83#ibcon#enter sib2, iclass 3, count 0 2006.238.08:24:30.83#ibcon#flushed, iclass 3, count 0 2006.238.08:24:30.83#ibcon#about to write, iclass 3, count 0 2006.238.08:24:30.83#ibcon#wrote, iclass 3, count 0 2006.238.08:24:30.83#ibcon#about to read 3, iclass 3, count 0 2006.238.08:24:30.85#ibcon#read 3, iclass 3, count 0 2006.238.08:24:30.85#ibcon#about to read 4, iclass 3, count 0 2006.238.08:24:30.85#ibcon#read 4, iclass 3, count 0 2006.238.08:24:30.85#ibcon#about to read 5, iclass 3, count 0 2006.238.08:24:30.85#ibcon#read 5, iclass 3, count 0 2006.238.08:24:30.85#ibcon#about to read 6, iclass 3, count 0 2006.238.08:24:30.85#ibcon#read 6, iclass 3, count 0 2006.238.08:24:30.85#ibcon#end of sib2, iclass 3, count 0 2006.238.08:24:30.85#ibcon#*mode == 0, iclass 3, count 0 2006.238.08:24:30.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.238.08:24:30.85#ibcon#[27=USB\r\n] 2006.238.08:24:30.85#ibcon#*before write, iclass 3, count 0 2006.238.08:24:30.85#ibcon#enter sib2, iclass 3, count 0 2006.238.08:24:30.85#ibcon#flushed, iclass 3, count 0 2006.238.08:24:30.85#ibcon#about to write, iclass 3, count 0 2006.238.08:24:30.85#ibcon#wrote, iclass 3, count 0 2006.238.08:24:30.85#ibcon#about to read 3, iclass 3, count 0 2006.238.08:24:30.88#ibcon#read 3, iclass 3, count 0 2006.238.08:24:30.88#ibcon#about to read 4, iclass 3, count 0 2006.238.08:24:30.88#ibcon#read 4, iclass 3, count 0 2006.238.08:24:30.88#ibcon#about to read 5, iclass 3, count 0 2006.238.08:24:30.88#ibcon#read 5, iclass 3, count 0 2006.238.08:24:30.88#ibcon#about to read 6, iclass 3, count 0 2006.238.08:24:30.88#ibcon#read 6, iclass 3, count 0 2006.238.08:24:30.88#ibcon#end of sib2, iclass 3, count 0 2006.238.08:24:30.88#ibcon#*after write, iclass 3, count 0 2006.238.08:24:30.88#ibcon#*before return 0, iclass 3, count 0 2006.238.08:24:30.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:24:30.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.238.08:24:30.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.238.08:24:30.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.238.08:24:30.88$vc4f8/vblo=2,640.99 2006.238.08:24:30.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.238.08:24:30.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.238.08:24:30.88#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:30.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:24:30.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:24:30.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:24:30.88#ibcon#enter wrdev, iclass 5, count 0 2006.238.08:24:30.88#ibcon#first serial, iclass 5, count 0 2006.238.08:24:30.88#ibcon#enter sib2, iclass 5, count 0 2006.238.08:24:30.88#ibcon#flushed, iclass 5, count 0 2006.238.08:24:30.88#ibcon#about to write, iclass 5, count 0 2006.238.08:24:30.88#ibcon#wrote, iclass 5, count 0 2006.238.08:24:30.88#ibcon#about to read 3, iclass 5, count 0 2006.238.08:24:30.90#ibcon#read 3, iclass 5, count 0 2006.238.08:24:30.90#ibcon#about to read 4, iclass 5, count 0 2006.238.08:24:30.90#ibcon#read 4, iclass 5, count 0 2006.238.08:24:30.90#ibcon#about to read 5, iclass 5, count 0 2006.238.08:24:30.90#ibcon#read 5, iclass 5, count 0 2006.238.08:24:30.90#ibcon#about to read 6, iclass 5, count 0 2006.238.08:24:30.90#ibcon#read 6, iclass 5, count 0 2006.238.08:24:30.90#ibcon#end of sib2, iclass 5, count 0 2006.238.08:24:30.90#ibcon#*mode == 0, iclass 5, count 0 2006.238.08:24:30.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.238.08:24:30.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.238.08:24:30.90#ibcon#*before write, iclass 5, count 0 2006.238.08:24:30.90#ibcon#enter sib2, iclass 5, count 0 2006.238.08:24:30.90#ibcon#flushed, iclass 5, count 0 2006.238.08:24:30.90#ibcon#about to write, iclass 5, count 0 2006.238.08:24:30.90#ibcon#wrote, iclass 5, count 0 2006.238.08:24:30.90#ibcon#about to read 3, iclass 5, count 0 2006.238.08:24:30.94#ibcon#read 3, iclass 5, count 0 2006.238.08:24:30.94#ibcon#about to read 4, iclass 5, count 0 2006.238.08:24:30.94#ibcon#read 4, iclass 5, count 0 2006.238.08:24:30.94#ibcon#about to read 5, iclass 5, count 0 2006.238.08:24:30.94#ibcon#read 5, iclass 5, count 0 2006.238.08:24:30.94#ibcon#about to read 6, iclass 5, count 0 2006.238.08:24:30.94#ibcon#read 6, iclass 5, count 0 2006.238.08:24:30.94#ibcon#end of sib2, iclass 5, count 0 2006.238.08:24:30.94#ibcon#*after write, iclass 5, count 0 2006.238.08:24:30.94#ibcon#*before return 0, iclass 5, count 0 2006.238.08:24:30.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:24:30.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.238.08:24:30.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.238.08:24:30.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.238.08:24:30.94$vc4f8/vb=2,4 2006.238.08:24:30.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.238.08:24:30.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.238.08:24:30.94#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:30.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:24:31.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:24:31.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:24:31.00#ibcon#enter wrdev, iclass 7, count 2 2006.238.08:24:31.00#ibcon#first serial, iclass 7, count 2 2006.238.08:24:31.00#ibcon#enter sib2, iclass 7, count 2 2006.238.08:24:31.00#ibcon#flushed, iclass 7, count 2 2006.238.08:24:31.00#ibcon#about to write, iclass 7, count 2 2006.238.08:24:31.00#ibcon#wrote, iclass 7, count 2 2006.238.08:24:31.00#ibcon#about to read 3, iclass 7, count 2 2006.238.08:24:31.02#ibcon#read 3, iclass 7, count 2 2006.238.08:24:31.02#ibcon#about to read 4, iclass 7, count 2 2006.238.08:24:31.02#ibcon#read 4, iclass 7, count 2 2006.238.08:24:31.02#ibcon#about to read 5, iclass 7, count 2 2006.238.08:24:31.02#ibcon#read 5, iclass 7, count 2 2006.238.08:24:31.02#ibcon#about to read 6, iclass 7, count 2 2006.238.08:24:31.02#ibcon#read 6, iclass 7, count 2 2006.238.08:24:31.02#ibcon#end of sib2, iclass 7, count 2 2006.238.08:24:31.02#ibcon#*mode == 0, iclass 7, count 2 2006.238.08:24:31.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.238.08:24:31.02#ibcon#[27=AT02-04\r\n] 2006.238.08:24:31.02#ibcon#*before write, iclass 7, count 2 2006.238.08:24:31.02#ibcon#enter sib2, iclass 7, count 2 2006.238.08:24:31.02#ibcon#flushed, iclass 7, count 2 2006.238.08:24:31.02#ibcon#about to write, iclass 7, count 2 2006.238.08:24:31.02#ibcon#wrote, iclass 7, count 2 2006.238.08:24:31.02#ibcon#about to read 3, iclass 7, count 2 2006.238.08:24:31.05#ibcon#read 3, iclass 7, count 2 2006.238.08:24:31.05#ibcon#about to read 4, iclass 7, count 2 2006.238.08:24:31.05#ibcon#read 4, iclass 7, count 2 2006.238.08:24:31.05#ibcon#about to read 5, iclass 7, count 2 2006.238.08:24:31.05#ibcon#read 5, iclass 7, count 2 2006.238.08:24:31.05#ibcon#about to read 6, iclass 7, count 2 2006.238.08:24:31.05#ibcon#read 6, iclass 7, count 2 2006.238.08:24:31.05#ibcon#end of sib2, iclass 7, count 2 2006.238.08:24:31.05#ibcon#*after write, iclass 7, count 2 2006.238.08:24:31.05#ibcon#*before return 0, iclass 7, count 2 2006.238.08:24:31.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:24:31.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.238.08:24:31.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.238.08:24:31.05#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:31.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:24:31.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:24:31.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:24:31.17#ibcon#enter wrdev, iclass 7, count 0 2006.238.08:24:31.17#ibcon#first serial, iclass 7, count 0 2006.238.08:24:31.17#ibcon#enter sib2, iclass 7, count 0 2006.238.08:24:31.17#ibcon#flushed, iclass 7, count 0 2006.238.08:24:31.17#ibcon#about to write, iclass 7, count 0 2006.238.08:24:31.17#ibcon#wrote, iclass 7, count 0 2006.238.08:24:31.17#ibcon#about to read 3, iclass 7, count 0 2006.238.08:24:31.19#ibcon#read 3, iclass 7, count 0 2006.238.08:24:31.19#ibcon#about to read 4, iclass 7, count 0 2006.238.08:24:31.19#ibcon#read 4, iclass 7, count 0 2006.238.08:24:31.19#ibcon#about to read 5, iclass 7, count 0 2006.238.08:24:31.19#ibcon#read 5, iclass 7, count 0 2006.238.08:24:31.19#ibcon#about to read 6, iclass 7, count 0 2006.238.08:24:31.19#ibcon#read 6, iclass 7, count 0 2006.238.08:24:31.19#ibcon#end of sib2, iclass 7, count 0 2006.238.08:24:31.19#ibcon#*mode == 0, iclass 7, count 0 2006.238.08:24:31.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.238.08:24:31.19#ibcon#[27=USB\r\n] 2006.238.08:24:31.19#ibcon#*before write, iclass 7, count 0 2006.238.08:24:31.19#ibcon#enter sib2, iclass 7, count 0 2006.238.08:24:31.19#ibcon#flushed, iclass 7, count 0 2006.238.08:24:31.19#ibcon#about to write, iclass 7, count 0 2006.238.08:24:31.19#ibcon#wrote, iclass 7, count 0 2006.238.08:24:31.19#ibcon#about to read 3, iclass 7, count 0 2006.238.08:24:31.22#ibcon#read 3, iclass 7, count 0 2006.238.08:24:31.22#ibcon#about to read 4, iclass 7, count 0 2006.238.08:24:31.22#ibcon#read 4, iclass 7, count 0 2006.238.08:24:31.22#ibcon#about to read 5, iclass 7, count 0 2006.238.08:24:31.22#ibcon#read 5, iclass 7, count 0 2006.238.08:24:31.22#ibcon#about to read 6, iclass 7, count 0 2006.238.08:24:31.22#ibcon#read 6, iclass 7, count 0 2006.238.08:24:31.22#ibcon#end of sib2, iclass 7, count 0 2006.238.08:24:31.22#ibcon#*after write, iclass 7, count 0 2006.238.08:24:31.22#ibcon#*before return 0, iclass 7, count 0 2006.238.08:24:31.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:24:31.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.238.08:24:31.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.238.08:24:31.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.238.08:24:31.22$vc4f8/vblo=3,656.99 2006.238.08:24:31.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.238.08:24:31.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.238.08:24:31.22#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:31.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:24:31.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:24:31.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:24:31.22#ibcon#enter wrdev, iclass 11, count 0 2006.238.08:24:31.22#ibcon#first serial, iclass 11, count 0 2006.238.08:24:31.22#ibcon#enter sib2, iclass 11, count 0 2006.238.08:24:31.22#ibcon#flushed, iclass 11, count 0 2006.238.08:24:31.22#ibcon#about to write, iclass 11, count 0 2006.238.08:24:31.22#ibcon#wrote, iclass 11, count 0 2006.238.08:24:31.22#ibcon#about to read 3, iclass 11, count 0 2006.238.08:24:31.24#ibcon#read 3, iclass 11, count 0 2006.238.08:24:31.24#ibcon#about to read 4, iclass 11, count 0 2006.238.08:24:31.24#ibcon#read 4, iclass 11, count 0 2006.238.08:24:31.24#ibcon#about to read 5, iclass 11, count 0 2006.238.08:24:31.24#ibcon#read 5, iclass 11, count 0 2006.238.08:24:31.24#ibcon#about to read 6, iclass 11, count 0 2006.238.08:24:31.24#ibcon#read 6, iclass 11, count 0 2006.238.08:24:31.24#ibcon#end of sib2, iclass 11, count 0 2006.238.08:24:31.24#ibcon#*mode == 0, iclass 11, count 0 2006.238.08:24:31.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.238.08:24:31.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.238.08:24:31.24#ibcon#*before write, iclass 11, count 0 2006.238.08:24:31.24#ibcon#enter sib2, iclass 11, count 0 2006.238.08:24:31.24#ibcon#flushed, iclass 11, count 0 2006.238.08:24:31.24#ibcon#about to write, iclass 11, count 0 2006.238.08:24:31.24#ibcon#wrote, iclass 11, count 0 2006.238.08:24:31.24#ibcon#about to read 3, iclass 11, count 0 2006.238.08:24:31.28#ibcon#read 3, iclass 11, count 0 2006.238.08:24:31.28#ibcon#about to read 4, iclass 11, count 0 2006.238.08:24:31.28#ibcon#read 4, iclass 11, count 0 2006.238.08:24:31.28#ibcon#about to read 5, iclass 11, count 0 2006.238.08:24:31.28#ibcon#read 5, iclass 11, count 0 2006.238.08:24:31.28#ibcon#about to read 6, iclass 11, count 0 2006.238.08:24:31.28#ibcon#read 6, iclass 11, count 0 2006.238.08:24:31.28#ibcon#end of sib2, iclass 11, count 0 2006.238.08:24:31.28#ibcon#*after write, iclass 11, count 0 2006.238.08:24:31.28#ibcon#*before return 0, iclass 11, count 0 2006.238.08:24:31.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:24:31.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.238.08:24:31.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.238.08:24:31.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.238.08:24:31.28$vc4f8/vb=3,4 2006.238.08:24:31.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.238.08:24:31.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.238.08:24:31.28#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:31.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:24:31.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:24:31.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:24:31.34#ibcon#enter wrdev, iclass 13, count 2 2006.238.08:24:31.34#ibcon#first serial, iclass 13, count 2 2006.238.08:24:31.34#ibcon#enter sib2, iclass 13, count 2 2006.238.08:24:31.34#ibcon#flushed, iclass 13, count 2 2006.238.08:24:31.34#ibcon#about to write, iclass 13, count 2 2006.238.08:24:31.34#ibcon#wrote, iclass 13, count 2 2006.238.08:24:31.34#ibcon#about to read 3, iclass 13, count 2 2006.238.08:24:31.36#ibcon#read 3, iclass 13, count 2 2006.238.08:24:31.36#ibcon#about to read 4, iclass 13, count 2 2006.238.08:24:31.36#ibcon#read 4, iclass 13, count 2 2006.238.08:24:31.36#ibcon#about to read 5, iclass 13, count 2 2006.238.08:24:31.36#ibcon#read 5, iclass 13, count 2 2006.238.08:24:31.36#ibcon#about to read 6, iclass 13, count 2 2006.238.08:24:31.36#ibcon#read 6, iclass 13, count 2 2006.238.08:24:31.36#ibcon#end of sib2, iclass 13, count 2 2006.238.08:24:31.36#ibcon#*mode == 0, iclass 13, count 2 2006.238.08:24:31.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.238.08:24:31.36#ibcon#[27=AT03-04\r\n] 2006.238.08:24:31.36#ibcon#*before write, iclass 13, count 2 2006.238.08:24:31.36#ibcon#enter sib2, iclass 13, count 2 2006.238.08:24:31.36#ibcon#flushed, iclass 13, count 2 2006.238.08:24:31.36#ibcon#about to write, iclass 13, count 2 2006.238.08:24:31.36#ibcon#wrote, iclass 13, count 2 2006.238.08:24:31.36#ibcon#about to read 3, iclass 13, count 2 2006.238.08:24:31.39#ibcon#read 3, iclass 13, count 2 2006.238.08:24:31.39#ibcon#about to read 4, iclass 13, count 2 2006.238.08:24:31.39#ibcon#read 4, iclass 13, count 2 2006.238.08:24:31.39#ibcon#about to read 5, iclass 13, count 2 2006.238.08:24:31.39#ibcon#read 5, iclass 13, count 2 2006.238.08:24:31.39#ibcon#about to read 6, iclass 13, count 2 2006.238.08:24:31.39#ibcon#read 6, iclass 13, count 2 2006.238.08:24:31.39#ibcon#end of sib2, iclass 13, count 2 2006.238.08:24:31.39#ibcon#*after write, iclass 13, count 2 2006.238.08:24:31.39#ibcon#*before return 0, iclass 13, count 2 2006.238.08:24:31.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:24:31.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.238.08:24:31.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.238.08:24:31.39#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:31.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:24:31.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:24:31.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:24:31.51#ibcon#enter wrdev, iclass 13, count 0 2006.238.08:24:31.51#ibcon#first serial, iclass 13, count 0 2006.238.08:24:31.51#ibcon#enter sib2, iclass 13, count 0 2006.238.08:24:31.51#ibcon#flushed, iclass 13, count 0 2006.238.08:24:31.51#ibcon#about to write, iclass 13, count 0 2006.238.08:24:31.51#ibcon#wrote, iclass 13, count 0 2006.238.08:24:31.51#ibcon#about to read 3, iclass 13, count 0 2006.238.08:24:31.53#ibcon#read 3, iclass 13, count 0 2006.238.08:24:31.53#ibcon#about to read 4, iclass 13, count 0 2006.238.08:24:31.53#ibcon#read 4, iclass 13, count 0 2006.238.08:24:31.53#ibcon#about to read 5, iclass 13, count 0 2006.238.08:24:31.53#ibcon#read 5, iclass 13, count 0 2006.238.08:24:31.53#ibcon#about to read 6, iclass 13, count 0 2006.238.08:24:31.53#ibcon#read 6, iclass 13, count 0 2006.238.08:24:31.53#ibcon#end of sib2, iclass 13, count 0 2006.238.08:24:31.53#ibcon#*mode == 0, iclass 13, count 0 2006.238.08:24:31.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.238.08:24:31.53#ibcon#[27=USB\r\n] 2006.238.08:24:31.53#ibcon#*before write, iclass 13, count 0 2006.238.08:24:31.53#ibcon#enter sib2, iclass 13, count 0 2006.238.08:24:31.53#ibcon#flushed, iclass 13, count 0 2006.238.08:24:31.53#ibcon#about to write, iclass 13, count 0 2006.238.08:24:31.53#ibcon#wrote, iclass 13, count 0 2006.238.08:24:31.53#ibcon#about to read 3, iclass 13, count 0 2006.238.08:24:31.56#ibcon#read 3, iclass 13, count 0 2006.238.08:24:31.56#ibcon#about to read 4, iclass 13, count 0 2006.238.08:24:31.56#ibcon#read 4, iclass 13, count 0 2006.238.08:24:31.56#ibcon#about to read 5, iclass 13, count 0 2006.238.08:24:31.56#ibcon#read 5, iclass 13, count 0 2006.238.08:24:31.56#ibcon#about to read 6, iclass 13, count 0 2006.238.08:24:31.56#ibcon#read 6, iclass 13, count 0 2006.238.08:24:31.56#ibcon#end of sib2, iclass 13, count 0 2006.238.08:24:31.56#ibcon#*after write, iclass 13, count 0 2006.238.08:24:31.56#ibcon#*before return 0, iclass 13, count 0 2006.238.08:24:31.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:24:31.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.238.08:24:31.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.238.08:24:31.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.238.08:24:31.56$vc4f8/vblo=4,712.99 2006.238.08:24:31.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.238.08:24:31.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.238.08:24:31.56#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:31.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:24:31.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:24:31.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:24:31.56#ibcon#enter wrdev, iclass 15, count 0 2006.238.08:24:31.56#ibcon#first serial, iclass 15, count 0 2006.238.08:24:31.56#ibcon#enter sib2, iclass 15, count 0 2006.238.08:24:31.56#ibcon#flushed, iclass 15, count 0 2006.238.08:24:31.56#ibcon#about to write, iclass 15, count 0 2006.238.08:24:31.56#ibcon#wrote, iclass 15, count 0 2006.238.08:24:31.56#ibcon#about to read 3, iclass 15, count 0 2006.238.08:24:31.58#ibcon#read 3, iclass 15, count 0 2006.238.08:24:31.58#ibcon#about to read 4, iclass 15, count 0 2006.238.08:24:31.58#ibcon#read 4, iclass 15, count 0 2006.238.08:24:31.58#ibcon#about to read 5, iclass 15, count 0 2006.238.08:24:31.58#ibcon#read 5, iclass 15, count 0 2006.238.08:24:31.58#ibcon#about to read 6, iclass 15, count 0 2006.238.08:24:31.58#ibcon#read 6, iclass 15, count 0 2006.238.08:24:31.58#ibcon#end of sib2, iclass 15, count 0 2006.238.08:24:31.58#ibcon#*mode == 0, iclass 15, count 0 2006.238.08:24:31.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.238.08:24:31.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.238.08:24:31.58#ibcon#*before write, iclass 15, count 0 2006.238.08:24:31.58#ibcon#enter sib2, iclass 15, count 0 2006.238.08:24:31.58#ibcon#flushed, iclass 15, count 0 2006.238.08:24:31.58#ibcon#about to write, iclass 15, count 0 2006.238.08:24:31.58#ibcon#wrote, iclass 15, count 0 2006.238.08:24:31.58#ibcon#about to read 3, iclass 15, count 0 2006.238.08:24:31.62#ibcon#read 3, iclass 15, count 0 2006.238.08:24:31.62#ibcon#about to read 4, iclass 15, count 0 2006.238.08:24:31.62#ibcon#read 4, iclass 15, count 0 2006.238.08:24:31.62#ibcon#about to read 5, iclass 15, count 0 2006.238.08:24:31.62#ibcon#read 5, iclass 15, count 0 2006.238.08:24:31.62#ibcon#about to read 6, iclass 15, count 0 2006.238.08:24:31.62#ibcon#read 6, iclass 15, count 0 2006.238.08:24:31.62#ibcon#end of sib2, iclass 15, count 0 2006.238.08:24:31.62#ibcon#*after write, iclass 15, count 0 2006.238.08:24:31.62#ibcon#*before return 0, iclass 15, count 0 2006.238.08:24:31.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:24:31.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.238.08:24:31.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.238.08:24:31.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.238.08:24:31.62$vc4f8/vb=4,4 2006.238.08:24:31.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.238.08:24:31.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.238.08:24:31.62#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:31.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:24:31.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:24:31.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:24:31.68#ibcon#enter wrdev, iclass 17, count 2 2006.238.08:24:31.68#ibcon#first serial, iclass 17, count 2 2006.238.08:24:31.68#ibcon#enter sib2, iclass 17, count 2 2006.238.08:24:31.68#ibcon#flushed, iclass 17, count 2 2006.238.08:24:31.68#ibcon#about to write, iclass 17, count 2 2006.238.08:24:31.68#ibcon#wrote, iclass 17, count 2 2006.238.08:24:31.68#ibcon#about to read 3, iclass 17, count 2 2006.238.08:24:31.70#ibcon#read 3, iclass 17, count 2 2006.238.08:24:31.70#ibcon#about to read 4, iclass 17, count 2 2006.238.08:24:31.70#ibcon#read 4, iclass 17, count 2 2006.238.08:24:31.70#ibcon#about to read 5, iclass 17, count 2 2006.238.08:24:31.70#ibcon#read 5, iclass 17, count 2 2006.238.08:24:31.70#ibcon#about to read 6, iclass 17, count 2 2006.238.08:24:31.70#ibcon#read 6, iclass 17, count 2 2006.238.08:24:31.70#ibcon#end of sib2, iclass 17, count 2 2006.238.08:24:31.70#ibcon#*mode == 0, iclass 17, count 2 2006.238.08:24:31.70#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.238.08:24:31.70#ibcon#[27=AT04-04\r\n] 2006.238.08:24:31.70#ibcon#*before write, iclass 17, count 2 2006.238.08:24:31.70#ibcon#enter sib2, iclass 17, count 2 2006.238.08:24:31.70#ibcon#flushed, iclass 17, count 2 2006.238.08:24:31.70#ibcon#about to write, iclass 17, count 2 2006.238.08:24:31.70#ibcon#wrote, iclass 17, count 2 2006.238.08:24:31.70#ibcon#about to read 3, iclass 17, count 2 2006.238.08:24:31.73#ibcon#read 3, iclass 17, count 2 2006.238.08:24:31.73#ibcon#about to read 4, iclass 17, count 2 2006.238.08:24:31.73#ibcon#read 4, iclass 17, count 2 2006.238.08:24:31.73#ibcon#about to read 5, iclass 17, count 2 2006.238.08:24:31.73#ibcon#read 5, iclass 17, count 2 2006.238.08:24:31.73#ibcon#about to read 6, iclass 17, count 2 2006.238.08:24:31.73#ibcon#read 6, iclass 17, count 2 2006.238.08:24:31.73#ibcon#end of sib2, iclass 17, count 2 2006.238.08:24:31.73#ibcon#*after write, iclass 17, count 2 2006.238.08:24:31.73#ibcon#*before return 0, iclass 17, count 2 2006.238.08:24:31.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:24:31.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.238.08:24:31.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.238.08:24:31.73#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:31.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:24:31.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:24:31.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:24:31.85#ibcon#enter wrdev, iclass 17, count 0 2006.238.08:24:31.85#ibcon#first serial, iclass 17, count 0 2006.238.08:24:31.85#ibcon#enter sib2, iclass 17, count 0 2006.238.08:24:31.85#ibcon#flushed, iclass 17, count 0 2006.238.08:24:31.85#ibcon#about to write, iclass 17, count 0 2006.238.08:24:31.85#ibcon#wrote, iclass 17, count 0 2006.238.08:24:31.85#ibcon#about to read 3, iclass 17, count 0 2006.238.08:24:31.87#ibcon#read 3, iclass 17, count 0 2006.238.08:24:31.87#ibcon#about to read 4, iclass 17, count 0 2006.238.08:24:31.87#ibcon#read 4, iclass 17, count 0 2006.238.08:24:31.87#ibcon#about to read 5, iclass 17, count 0 2006.238.08:24:31.87#ibcon#read 5, iclass 17, count 0 2006.238.08:24:31.87#ibcon#about to read 6, iclass 17, count 0 2006.238.08:24:31.87#ibcon#read 6, iclass 17, count 0 2006.238.08:24:31.87#ibcon#end of sib2, iclass 17, count 0 2006.238.08:24:31.87#ibcon#*mode == 0, iclass 17, count 0 2006.238.08:24:31.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.238.08:24:31.87#ibcon#[27=USB\r\n] 2006.238.08:24:31.87#ibcon#*before write, iclass 17, count 0 2006.238.08:24:31.87#ibcon#enter sib2, iclass 17, count 0 2006.238.08:24:31.87#ibcon#flushed, iclass 17, count 0 2006.238.08:24:31.87#ibcon#about to write, iclass 17, count 0 2006.238.08:24:31.87#ibcon#wrote, iclass 17, count 0 2006.238.08:24:31.87#ibcon#about to read 3, iclass 17, count 0 2006.238.08:24:31.90#abcon#<5=/04 1.6 3.6 25.42 901012.3\r\n> 2006.238.08:24:31.90#ibcon#read 3, iclass 17, count 0 2006.238.08:24:31.90#ibcon#about to read 4, iclass 17, count 0 2006.238.08:24:31.90#ibcon#read 4, iclass 17, count 0 2006.238.08:24:31.90#ibcon#about to read 5, iclass 17, count 0 2006.238.08:24:31.90#ibcon#read 5, iclass 17, count 0 2006.238.08:24:31.90#ibcon#about to read 6, iclass 17, count 0 2006.238.08:24:31.90#ibcon#read 6, iclass 17, count 0 2006.238.08:24:31.90#ibcon#end of sib2, iclass 17, count 0 2006.238.08:24:31.90#ibcon#*after write, iclass 17, count 0 2006.238.08:24:31.90#ibcon#*before return 0, iclass 17, count 0 2006.238.08:24:31.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:24:31.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.238.08:24:31.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.238.08:24:31.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.238.08:24:31.90$vc4f8/vblo=5,744.99 2006.238.08:24:31.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.238.08:24:31.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.238.08:24:31.90#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:31.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:24:31.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:24:31.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:24:31.90#ibcon#enter wrdev, iclass 22, count 0 2006.238.08:24:31.90#ibcon#first serial, iclass 22, count 0 2006.238.08:24:31.90#ibcon#enter sib2, iclass 22, count 0 2006.238.08:24:31.90#ibcon#flushed, iclass 22, count 0 2006.238.08:24:31.90#ibcon#about to write, iclass 22, count 0 2006.238.08:24:31.90#ibcon#wrote, iclass 22, count 0 2006.238.08:24:31.90#ibcon#about to read 3, iclass 22, count 0 2006.238.08:24:31.92#abcon#{5=INTERFACE CLEAR} 2006.238.08:24:31.92#ibcon#read 3, iclass 22, count 0 2006.238.08:24:31.92#ibcon#about to read 4, iclass 22, count 0 2006.238.08:24:31.92#ibcon#read 4, iclass 22, count 0 2006.238.08:24:31.92#ibcon#about to read 5, iclass 22, count 0 2006.238.08:24:31.92#ibcon#read 5, iclass 22, count 0 2006.238.08:24:31.92#ibcon#about to read 6, iclass 22, count 0 2006.238.08:24:31.92#ibcon#read 6, iclass 22, count 0 2006.238.08:24:31.92#ibcon#end of sib2, iclass 22, count 0 2006.238.08:24:31.92#ibcon#*mode == 0, iclass 22, count 0 2006.238.08:24:31.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.238.08:24:31.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.238.08:24:31.92#ibcon#*before write, iclass 22, count 0 2006.238.08:24:31.92#ibcon#enter sib2, iclass 22, count 0 2006.238.08:24:31.92#ibcon#flushed, iclass 22, count 0 2006.238.08:24:31.92#ibcon#about to write, iclass 22, count 0 2006.238.08:24:31.92#ibcon#wrote, iclass 22, count 0 2006.238.08:24:31.92#ibcon#about to read 3, iclass 22, count 0 2006.238.08:24:31.96#ibcon#read 3, iclass 22, count 0 2006.238.08:24:31.96#ibcon#about to read 4, iclass 22, count 0 2006.238.08:24:31.96#ibcon#read 4, iclass 22, count 0 2006.238.08:24:31.96#ibcon#about to read 5, iclass 22, count 0 2006.238.08:24:31.96#ibcon#read 5, iclass 22, count 0 2006.238.08:24:31.96#ibcon#about to read 6, iclass 22, count 0 2006.238.08:24:31.96#ibcon#read 6, iclass 22, count 0 2006.238.08:24:31.96#ibcon#end of sib2, iclass 22, count 0 2006.238.08:24:31.96#ibcon#*after write, iclass 22, count 0 2006.238.08:24:31.96#ibcon#*before return 0, iclass 22, count 0 2006.238.08:24:31.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:24:31.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.238.08:24:31.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.238.08:24:31.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.238.08:24:31.96$vc4f8/vb=5,4 2006.238.08:24:31.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.238.08:24:31.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.238.08:24:31.96#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:31.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:24:31.98#abcon#[5=S1D000X0/0*\r\n] 2006.238.08:24:32.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:24:32.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:24:32.02#ibcon#enter wrdev, iclass 24, count 2 2006.238.08:24:32.02#ibcon#first serial, iclass 24, count 2 2006.238.08:24:32.02#ibcon#enter sib2, iclass 24, count 2 2006.238.08:24:32.02#ibcon#flushed, iclass 24, count 2 2006.238.08:24:32.02#ibcon#about to write, iclass 24, count 2 2006.238.08:24:32.02#ibcon#wrote, iclass 24, count 2 2006.238.08:24:32.02#ibcon#about to read 3, iclass 24, count 2 2006.238.08:24:32.04#ibcon#read 3, iclass 24, count 2 2006.238.08:24:32.04#ibcon#about to read 4, iclass 24, count 2 2006.238.08:24:32.04#ibcon#read 4, iclass 24, count 2 2006.238.08:24:32.04#ibcon#about to read 5, iclass 24, count 2 2006.238.08:24:32.04#ibcon#read 5, iclass 24, count 2 2006.238.08:24:32.04#ibcon#about to read 6, iclass 24, count 2 2006.238.08:24:32.04#ibcon#read 6, iclass 24, count 2 2006.238.08:24:32.04#ibcon#end of sib2, iclass 24, count 2 2006.238.08:24:32.04#ibcon#*mode == 0, iclass 24, count 2 2006.238.08:24:32.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.238.08:24:32.04#ibcon#[27=AT05-04\r\n] 2006.238.08:24:32.04#ibcon#*before write, iclass 24, count 2 2006.238.08:24:32.04#ibcon#enter sib2, iclass 24, count 2 2006.238.08:24:32.04#ibcon#flushed, iclass 24, count 2 2006.238.08:24:32.04#ibcon#about to write, iclass 24, count 2 2006.238.08:24:32.04#ibcon#wrote, iclass 24, count 2 2006.238.08:24:32.04#ibcon#about to read 3, iclass 24, count 2 2006.238.08:24:32.07#ibcon#read 3, iclass 24, count 2 2006.238.08:24:32.07#ibcon#about to read 4, iclass 24, count 2 2006.238.08:24:32.07#ibcon#read 4, iclass 24, count 2 2006.238.08:24:32.07#ibcon#about to read 5, iclass 24, count 2 2006.238.08:24:32.07#ibcon#read 5, iclass 24, count 2 2006.238.08:24:32.07#ibcon#about to read 6, iclass 24, count 2 2006.238.08:24:32.07#ibcon#read 6, iclass 24, count 2 2006.238.08:24:32.07#ibcon#end of sib2, iclass 24, count 2 2006.238.08:24:32.07#ibcon#*after write, iclass 24, count 2 2006.238.08:24:32.07#ibcon#*before return 0, iclass 24, count 2 2006.238.08:24:32.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:24:32.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.238.08:24:32.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.238.08:24:32.07#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:32.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:24:32.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:24:32.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:24:32.19#ibcon#enter wrdev, iclass 24, count 0 2006.238.08:24:32.19#ibcon#first serial, iclass 24, count 0 2006.238.08:24:32.19#ibcon#enter sib2, iclass 24, count 0 2006.238.08:24:32.19#ibcon#flushed, iclass 24, count 0 2006.238.08:24:32.19#ibcon#about to write, iclass 24, count 0 2006.238.08:24:32.19#ibcon#wrote, iclass 24, count 0 2006.238.08:24:32.19#ibcon#about to read 3, iclass 24, count 0 2006.238.08:24:32.21#ibcon#read 3, iclass 24, count 0 2006.238.08:24:32.21#ibcon#about to read 4, iclass 24, count 0 2006.238.08:24:32.21#ibcon#read 4, iclass 24, count 0 2006.238.08:24:32.21#ibcon#about to read 5, iclass 24, count 0 2006.238.08:24:32.21#ibcon#read 5, iclass 24, count 0 2006.238.08:24:32.21#ibcon#about to read 6, iclass 24, count 0 2006.238.08:24:32.21#ibcon#read 6, iclass 24, count 0 2006.238.08:24:32.21#ibcon#end of sib2, iclass 24, count 0 2006.238.08:24:32.21#ibcon#*mode == 0, iclass 24, count 0 2006.238.08:24:32.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.238.08:24:32.21#ibcon#[27=USB\r\n] 2006.238.08:24:32.21#ibcon#*before write, iclass 24, count 0 2006.238.08:24:32.21#ibcon#enter sib2, iclass 24, count 0 2006.238.08:24:32.21#ibcon#flushed, iclass 24, count 0 2006.238.08:24:32.21#ibcon#about to write, iclass 24, count 0 2006.238.08:24:32.21#ibcon#wrote, iclass 24, count 0 2006.238.08:24:32.21#ibcon#about to read 3, iclass 24, count 0 2006.238.08:24:32.24#ibcon#read 3, iclass 24, count 0 2006.238.08:24:32.24#ibcon#about to read 4, iclass 24, count 0 2006.238.08:24:32.24#ibcon#read 4, iclass 24, count 0 2006.238.08:24:32.24#ibcon#about to read 5, iclass 24, count 0 2006.238.08:24:32.24#ibcon#read 5, iclass 24, count 0 2006.238.08:24:32.24#ibcon#about to read 6, iclass 24, count 0 2006.238.08:24:32.24#ibcon#read 6, iclass 24, count 0 2006.238.08:24:32.24#ibcon#end of sib2, iclass 24, count 0 2006.238.08:24:32.24#ibcon#*after write, iclass 24, count 0 2006.238.08:24:32.24#ibcon#*before return 0, iclass 24, count 0 2006.238.08:24:32.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:24:32.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.238.08:24:32.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.238.08:24:32.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.238.08:24:32.24$vc4f8/vblo=6,752.99 2006.238.08:24:32.24#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.238.08:24:32.24#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.238.08:24:32.24#ibcon#ireg 17 cls_cnt 0 2006.238.08:24:32.24#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:24:32.24#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:24:32.24#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:24:32.24#ibcon#enter wrdev, iclass 27, count 0 2006.238.08:24:32.24#ibcon#first serial, iclass 27, count 0 2006.238.08:24:32.24#ibcon#enter sib2, iclass 27, count 0 2006.238.08:24:32.24#ibcon#flushed, iclass 27, count 0 2006.238.08:24:32.24#ibcon#about to write, iclass 27, count 0 2006.238.08:24:32.24#ibcon#wrote, iclass 27, count 0 2006.238.08:24:32.24#ibcon#about to read 3, iclass 27, count 0 2006.238.08:24:32.26#ibcon#read 3, iclass 27, count 0 2006.238.08:24:32.26#ibcon#about to read 4, iclass 27, count 0 2006.238.08:24:32.26#ibcon#read 4, iclass 27, count 0 2006.238.08:24:32.26#ibcon#about to read 5, iclass 27, count 0 2006.238.08:24:32.26#ibcon#read 5, iclass 27, count 0 2006.238.08:24:32.26#ibcon#about to read 6, iclass 27, count 0 2006.238.08:24:32.26#ibcon#read 6, iclass 27, count 0 2006.238.08:24:32.26#ibcon#end of sib2, iclass 27, count 0 2006.238.08:24:32.26#ibcon#*mode == 0, iclass 27, count 0 2006.238.08:24:32.26#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.238.08:24:32.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.238.08:24:32.26#ibcon#*before write, iclass 27, count 0 2006.238.08:24:32.26#ibcon#enter sib2, iclass 27, count 0 2006.238.08:24:32.26#ibcon#flushed, iclass 27, count 0 2006.238.08:24:32.26#ibcon#about to write, iclass 27, count 0 2006.238.08:24:32.26#ibcon#wrote, iclass 27, count 0 2006.238.08:24:32.26#ibcon#about to read 3, iclass 27, count 0 2006.238.08:24:32.30#ibcon#read 3, iclass 27, count 0 2006.238.08:24:32.30#ibcon#about to read 4, iclass 27, count 0 2006.238.08:24:32.30#ibcon#read 4, iclass 27, count 0 2006.238.08:24:32.30#ibcon#about to read 5, iclass 27, count 0 2006.238.08:24:32.30#ibcon#read 5, iclass 27, count 0 2006.238.08:24:32.30#ibcon#about to read 6, iclass 27, count 0 2006.238.08:24:32.30#ibcon#read 6, iclass 27, count 0 2006.238.08:24:32.30#ibcon#end of sib2, iclass 27, count 0 2006.238.08:24:32.30#ibcon#*after write, iclass 27, count 0 2006.238.08:24:32.30#ibcon#*before return 0, iclass 27, count 0 2006.238.08:24:32.30#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:24:32.30#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.238.08:24:32.30#ibcon#about to clear, iclass 27 cls_cnt 0 2006.238.08:24:32.30#ibcon#cleared, iclass 27 cls_cnt 0 2006.238.08:24:32.30$vc4f8/vb=6,4 2006.238.08:24:32.30#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.238.08:24:32.30#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.238.08:24:32.30#ibcon#ireg 11 cls_cnt 2 2006.238.08:24:32.30#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:24:32.36#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:24:32.36#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:24:32.36#ibcon#enter wrdev, iclass 29, count 2 2006.238.08:24:32.36#ibcon#first serial, iclass 29, count 2 2006.238.08:24:32.36#ibcon#enter sib2, iclass 29, count 2 2006.238.08:24:32.36#ibcon#flushed, iclass 29, count 2 2006.238.08:24:32.36#ibcon#about to write, iclass 29, count 2 2006.238.08:24:32.36#ibcon#wrote, iclass 29, count 2 2006.238.08:24:32.36#ibcon#about to read 3, iclass 29, count 2 2006.238.08:24:32.38#ibcon#read 3, iclass 29, count 2 2006.238.08:24:32.38#ibcon#about to read 4, iclass 29, count 2 2006.238.08:24:32.38#ibcon#read 4, iclass 29, count 2 2006.238.08:24:32.38#ibcon#about to read 5, iclass 29, count 2 2006.238.08:24:32.38#ibcon#read 5, iclass 29, count 2 2006.238.08:24:32.38#ibcon#about to read 6, iclass 29, count 2 2006.238.08:24:32.38#ibcon#read 6, iclass 29, count 2 2006.238.08:24:32.38#ibcon#end of sib2, iclass 29, count 2 2006.238.08:24:32.38#ibcon#*mode == 0, iclass 29, count 2 2006.238.08:24:32.38#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.238.08:24:32.38#ibcon#[27=AT06-04\r\n] 2006.238.08:24:32.38#ibcon#*before write, iclass 29, count 2 2006.238.08:24:32.38#ibcon#enter sib2, iclass 29, count 2 2006.238.08:24:32.38#ibcon#flushed, iclass 29, count 2 2006.238.08:24:32.38#ibcon#about to write, iclass 29, count 2 2006.238.08:24:32.38#ibcon#wrote, iclass 29, count 2 2006.238.08:24:32.38#ibcon#about to read 3, iclass 29, count 2 2006.238.08:24:32.41#ibcon#read 3, iclass 29, count 2 2006.238.08:24:32.41#ibcon#about to read 4, iclass 29, count 2 2006.238.08:24:32.41#ibcon#read 4, iclass 29, count 2 2006.238.08:24:32.41#ibcon#about to read 5, iclass 29, count 2 2006.238.08:24:32.41#ibcon#read 5, iclass 29, count 2 2006.238.08:24:32.41#ibcon#about to read 6, iclass 29, count 2 2006.238.08:24:32.41#ibcon#read 6, iclass 29, count 2 2006.238.08:24:32.41#ibcon#end of sib2, iclass 29, count 2 2006.238.08:24:32.41#ibcon#*after write, iclass 29, count 2 2006.238.08:24:32.41#ibcon#*before return 0, iclass 29, count 2 2006.238.08:24:32.41#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:24:32.41#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.238.08:24:32.41#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.238.08:24:32.41#ibcon#ireg 7 cls_cnt 0 2006.238.08:24:32.41#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:24:32.53#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:24:32.53#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:24:32.53#ibcon#enter wrdev, iclass 29, count 0 2006.238.08:24:32.53#ibcon#first serial, iclass 29, count 0 2006.238.08:24:32.53#ibcon#enter sib2, iclass 29, count 0 2006.238.08:24:32.53#ibcon#flushed, iclass 29, count 0 2006.238.08:24:32.53#ibcon#about to write, iclass 29, count 0 2006.238.08:24:32.53#ibcon#wrote, iclass 29, count 0 2006.238.08:24:32.53#ibcon#about to read 3, iclass 29, count 0 2006.238.08:24:32.55#ibcon#read 3, iclass 29, count 0 2006.238.08:24:32.55#ibcon#about to read 4, iclass 29, count 0 2006.238.08:24:32.55#ibcon#read 4, iclass 29, count 0 2006.238.08:24:32.55#ibcon#about to read 5, iclass 29, count 0 2006.238.08:24:32.55#ibcon#read 5, iclass 29, count 0 2006.238.08:24:32.55#ibcon#about to read 6, iclass 29, count 0 2006.238.08:24:32.55#ibcon#read 6, iclass 29, count 0 2006.238.08:24:32.55#ibcon#end of sib2, iclass 29, count 0 2006.238.08:24:32.55#ibcon#*mode == 0, iclass 29, count 0 2006.238.08:24:32.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.238.08:24:32.55#ibcon#[27=USB\r\n] 2006.238.08:24:32.55#ibcon#*before write, iclass 29, count 0 2006.238.08:24:32.55#ibcon#enter sib2, iclass 29, count 0 2006.238.08:24:32.55#ibcon#flushed, iclass 29, count 0 2006.238.08:24:32.55#ibcon#about to write, iclass 29, count 0 2006.238.08:24:32.55#ibcon#wrote, iclass 29, count 0 2006.238.08:24:32.55#ibcon#about to read 3, iclass 29, count 0 2006.238.08:24:32.58#ibcon#read 3, iclass 29, count 0 2006.238.08:24:32.58#ibcon#about to read 4, iclass 29, count 0 2006.238.08:24:32.58#ibcon#read 4, iclass 29, count 0 2006.238.08:24:32.58#ibcon#about to read 5, iclass 29, count 0 2006.238.08:24:32.58#ibcon#read 5, iclass 29, count 0 2006.238.08:24:32.58#ibcon#about to read 6, iclass 29, count 0 2006.238.08:24:32.58#ibcon#read 6, iclass 29, count 0 2006.238.08:24:32.58#ibcon#end of sib2, iclass 29, count 0 2006.238.08:24:32.58#ibcon#*after write, iclass 29, count 0 2006.238.08:24:32.58#ibcon#*before return 0, iclass 29, count 0 2006.238.08:24:32.58#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:24:32.58#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.238.08:24:32.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.238.08:24:32.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.238.08:24:32.58$vc4f8/vabw=wide 2006.238.08:24:32.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.238.08:24:32.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.238.08:24:32.58#ibcon#ireg 8 cls_cnt 0 2006.238.08:24:32.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:24:32.58#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:24:32.58#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:24:32.58#ibcon#enter wrdev, iclass 31, count 0 2006.238.08:24:32.58#ibcon#first serial, iclass 31, count 0 2006.238.08:24:32.58#ibcon#enter sib2, iclass 31, count 0 2006.238.08:24:32.58#ibcon#flushed, iclass 31, count 0 2006.238.08:24:32.58#ibcon#about to write, iclass 31, count 0 2006.238.08:24:32.58#ibcon#wrote, iclass 31, count 0 2006.238.08:24:32.58#ibcon#about to read 3, iclass 31, count 0 2006.238.08:24:32.60#ibcon#read 3, iclass 31, count 0 2006.238.08:24:32.60#ibcon#about to read 4, iclass 31, count 0 2006.238.08:24:32.60#ibcon#read 4, iclass 31, count 0 2006.238.08:24:32.60#ibcon#about to read 5, iclass 31, count 0 2006.238.08:24:32.60#ibcon#read 5, iclass 31, count 0 2006.238.08:24:32.60#ibcon#about to read 6, iclass 31, count 0 2006.238.08:24:32.60#ibcon#read 6, iclass 31, count 0 2006.238.08:24:32.60#ibcon#end of sib2, iclass 31, count 0 2006.238.08:24:32.60#ibcon#*mode == 0, iclass 31, count 0 2006.238.08:24:32.60#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.238.08:24:32.60#ibcon#[25=BW32\r\n] 2006.238.08:24:32.60#ibcon#*before write, iclass 31, count 0 2006.238.08:24:32.60#ibcon#enter sib2, iclass 31, count 0 2006.238.08:24:32.60#ibcon#flushed, iclass 31, count 0 2006.238.08:24:32.60#ibcon#about to write, iclass 31, count 0 2006.238.08:24:32.60#ibcon#wrote, iclass 31, count 0 2006.238.08:24:32.60#ibcon#about to read 3, iclass 31, count 0 2006.238.08:24:32.63#ibcon#read 3, iclass 31, count 0 2006.238.08:24:32.63#ibcon#about to read 4, iclass 31, count 0 2006.238.08:24:32.63#ibcon#read 4, iclass 31, count 0 2006.238.08:24:32.63#ibcon#about to read 5, iclass 31, count 0 2006.238.08:24:32.63#ibcon#read 5, iclass 31, count 0 2006.238.08:24:32.63#ibcon#about to read 6, iclass 31, count 0 2006.238.08:24:32.63#ibcon#read 6, iclass 31, count 0 2006.238.08:24:32.63#ibcon#end of sib2, iclass 31, count 0 2006.238.08:24:32.63#ibcon#*after write, iclass 31, count 0 2006.238.08:24:32.63#ibcon#*before return 0, iclass 31, count 0 2006.238.08:24:32.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:24:32.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.238.08:24:32.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.238.08:24:32.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.238.08:24:32.63$vc4f8/vbbw=wide 2006.238.08:24:32.63#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.238.08:24:32.63#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.238.08:24:32.63#ibcon#ireg 8 cls_cnt 0 2006.238.08:24:32.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:24:32.70#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:24:32.70#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:24:32.70#ibcon#enter wrdev, iclass 33, count 0 2006.238.08:24:32.70#ibcon#first serial, iclass 33, count 0 2006.238.08:24:32.70#ibcon#enter sib2, iclass 33, count 0 2006.238.08:24:32.70#ibcon#flushed, iclass 33, count 0 2006.238.08:24:32.70#ibcon#about to write, iclass 33, count 0 2006.238.08:24:32.70#ibcon#wrote, iclass 33, count 0 2006.238.08:24:32.70#ibcon#about to read 3, iclass 33, count 0 2006.238.08:24:32.72#ibcon#read 3, iclass 33, count 0 2006.238.08:24:32.72#ibcon#about to read 4, iclass 33, count 0 2006.238.08:24:32.72#ibcon#read 4, iclass 33, count 0 2006.238.08:24:32.72#ibcon#about to read 5, iclass 33, count 0 2006.238.08:24:32.72#ibcon#read 5, iclass 33, count 0 2006.238.08:24:32.72#ibcon#about to read 6, iclass 33, count 0 2006.238.08:24:32.72#ibcon#read 6, iclass 33, count 0 2006.238.08:24:32.72#ibcon#end of sib2, iclass 33, count 0 2006.238.08:24:32.72#ibcon#*mode == 0, iclass 33, count 0 2006.238.08:24:32.72#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.238.08:24:32.72#ibcon#[27=BW32\r\n] 2006.238.08:24:32.72#ibcon#*before write, iclass 33, count 0 2006.238.08:24:32.72#ibcon#enter sib2, iclass 33, count 0 2006.238.08:24:32.72#ibcon#flushed, iclass 33, count 0 2006.238.08:24:32.72#ibcon#about to write, iclass 33, count 0 2006.238.08:24:32.72#ibcon#wrote, iclass 33, count 0 2006.238.08:24:32.72#ibcon#about to read 3, iclass 33, count 0 2006.238.08:24:32.75#ibcon#read 3, iclass 33, count 0 2006.238.08:24:32.75#ibcon#about to read 4, iclass 33, count 0 2006.238.08:24:32.75#ibcon#read 4, iclass 33, count 0 2006.238.08:24:32.75#ibcon#about to read 5, iclass 33, count 0 2006.238.08:24:32.75#ibcon#read 5, iclass 33, count 0 2006.238.08:24:32.75#ibcon#about to read 6, iclass 33, count 0 2006.238.08:24:32.75#ibcon#read 6, iclass 33, count 0 2006.238.08:24:32.75#ibcon#end of sib2, iclass 33, count 0 2006.238.08:24:32.75#ibcon#*after write, iclass 33, count 0 2006.238.08:24:32.75#ibcon#*before return 0, iclass 33, count 0 2006.238.08:24:32.75#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:24:32.75#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.238.08:24:32.75#ibcon#about to clear, iclass 33 cls_cnt 0 2006.238.08:24:32.75#ibcon#cleared, iclass 33 cls_cnt 0 2006.238.08:24:32.75$4f8m12a/ifd4f 2006.238.08:24:32.75$ifd4f/lo= 2006.238.08:24:32.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.238.08:24:32.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.238.08:24:32.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.238.08:24:32.75$ifd4f/patch= 2006.238.08:24:32.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.238.08:24:32.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.238.08:24:32.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.238.08:24:32.75$4f8m12a/"form=m,16.000,1:2 2006.238.08:24:32.75$4f8m12a/"tpicd 2006.238.08:24:32.75$4f8m12a/echo=off 2006.238.08:24:32.75$4f8m12a/xlog=off 2006.238.08:24:32.75:!2006.238.08:25:00 2006.238.08:24:45.13#trakl#Source acquired 2006.238.08:24:45.13#flagr#flagr/antenna,acquired 2006.238.08:25:00.00:preob 2006.238.08:25:01.13/onsource/TRACKING 2006.238.08:25:01.13:!2006.238.08:25:10 2006.238.08:25:10.00:data_valid=on 2006.238.08:25:10.00:midob 2006.238.08:25:10.13/onsource/TRACKING 2006.238.08:25:10.13/wx/25.41,1012.3,90 2006.238.08:25:10.30/cable/+6.4171E-03 2006.238.08:25:11.39/va/01,08,usb,yes,36,38 2006.238.08:25:11.39/va/02,07,usb,yes,37,38 2006.238.08:25:11.39/va/03,07,usb,yes,34,35 2006.238.08:25:11.39/va/04,07,usb,yes,38,41 2006.238.08:25:11.39/va/05,08,usb,yes,35,37 2006.238.08:25:11.39/va/06,07,usb,yes,38,38 2006.238.08:25:11.39/va/07,07,usb,yes,38,38 2006.238.08:25:11.39/va/08,07,usb,yes,41,40 2006.238.08:25:11.62/valo/01,532.99,yes,locked 2006.238.08:25:11.62/valo/02,572.99,yes,locked 2006.238.08:25:11.62/valo/03,672.99,yes,locked 2006.238.08:25:11.62/valo/04,832.99,yes,locked 2006.238.08:25:11.62/valo/05,652.99,yes,locked 2006.238.08:25:11.62/valo/06,772.99,yes,locked 2006.238.08:25:11.62/valo/07,832.99,yes,locked 2006.238.08:25:11.62/valo/08,852.99,yes,locked 2006.238.08:25:12.71/vb/01,04,usb,yes,33,33 2006.238.08:25:12.71/vb/02,04,usb,yes,35,37 2006.238.08:25:12.71/vb/03,04,usb,yes,31,35 2006.238.08:25:12.71/vb/04,04,usb,yes,34,33 2006.238.08:25:12.71/vb/05,04,usb,yes,31,38 2006.238.08:25:12.71/vb/06,04,usb,yes,32,35 2006.238.08:25:12.71/vb/07,04,usb,yes,34,38 2006.238.08:25:12.71/vb/08,04,usb,yes,31,38 2006.238.08:25:12.95/vblo/01,632.99,yes,locked 2006.238.08:25:12.95/vblo/02,640.99,yes,locked 2006.238.08:25:12.95/vblo/03,656.99,yes,locked 2006.238.08:25:12.95/vblo/04,712.99,yes,locked 2006.238.08:25:12.95/vblo/05,744.99,yes,locked 2006.238.08:25:12.95/vblo/06,752.99,yes,locked 2006.238.08:25:12.95/vblo/07,734.99,yes,locked 2006.238.08:25:12.95/vblo/08,744.99,yes,locked 2006.238.08:25:13.10/vabw/8 2006.238.08:25:13.25/vbbw/8 2006.238.08:25:13.34/xfe/off,on,12.5 2006.238.08:25:13.72/ifatt/23,28,28,28 2006.238.08:25:14.08/fmout-gps/S +4.50E-07 2006.238.08:25:14.12:!2006.238.08:26:10 2006.238.08:26:10.00:data_valid=off 2006.238.08:26:10.00:postob 2006.238.08:26:10.18/cable/+6.4180E-03 2006.238.08:26:10.18/wx/25.40,1012.3,90 2006.238.08:26:11.08/fmout-gps/S +4.50E-07 2006.238.08:26:11.08:checkk5last 2006.238.08:26:11.08&checkk5last/chk_obsdata=1 2006.238.08:26:11.09&checkk5last/chk_obsdata=2 2006.238.08:26:11.09&checkk5last/chk_obsdata=3 2006.238.08:26:11.10&checkk5last/chk_obsdata=4 2006.238.08:26:11.10&checkk5last/k5log=1 2006.238.08:26:11.10&checkk5last/k5log=2 2006.238.08:26:11.11&checkk5last/k5log=3 2006.238.08:26:11.11&checkk5last/k5log=4 2006.238.08:26:11.11&checkk5last/obsinfo 2006.238.08:26:11.50/chk_obsdata//k5ts1/T2380825??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:26:11.87/chk_obsdata//k5ts2/T2380825??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:26:12.24/chk_obsdata//k5ts3/T2380825??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:26:12.61/chk_obsdata//k5ts4/T2380825??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.238.08:26:13.30/k5log//k5ts1_log_newline 2006.238.08:26:13.99/k5log//k5ts2_log_newline 2006.238.08:26:14.68/k5log//k5ts3_log_newline 2006.238.08:26:15.38/k5log//k5ts4_log_newline 2006.238.08:26:15.40/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.238.08:26:15.40:"sched_end 2006.238.08:26:15.40:source=idle 2006.238.08:26:16.14#flagr#flagr/antenna,new-source 2006.238.08:26:16.14:stow 2006.238.08:26:16.14&stow/source=idle 2006.238.08:26:16.14&stow/"this is stow command. 2006.238.08:26:16.14&stow/antenna=m3 2006.238.08:26:20.01:!+10m 2006.238.08:36:20.02:standby 2006.238.08:36:20.02&standby/"this is standby command. 2006.238.08:36:20.02&standby/antenna=m0 2006.238.08:36:21.01:checkk5hdd 2006.238.08:36:21.01&checkk5hdd/chk_hdd=1 2006.238.08:36:21.01&checkk5hdd/chk_hdd=2 2006.238.08:36:21.01&checkk5hdd/chk_hdd=3 2006.238.08:36:21.01&checkk5hdd/chk_hdd=4 2006.238.08:36:23.82/chk_hdd//k5ts1/GSI00275:T238073000a.dat~T238082510a.dat[12777488384Byte] 2006.238.08:36:26.61/chk_hdd//k5ts2/GSI00163:T238073000b.dat~T238082510b.dat[12777488384Byte] 2006.238.08:36:29.41/chk_hdd//k5ts3/GSI00278:T238073000c.dat~T238082510c.dat[12777488384Byte] 2006.238.08:36:32.19/chk_hdd//k5ts4/GSI00141:T238073000d.dat~T238082510d.dat[12777488384Byte] 2006.238.08:36:32.19:sy=cp /usr2/log/k06238ts.log /usr2/log_backup/ 2006.238.08:36:32.29:log=k06239ts