2006.230.07:16:08.16;Log Opened: Mark IV Field System Version 9.7.7 2006.230.07:16:08.16;location,TSUKUB32,-140.09,36.10,61.0 2006.230.07:16:08.16;horizon1,0.,5.,360. 2006.230.07:16:08.16;antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.230.07:16:08.16;equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.230.07:16:08.16;drivev11,330,270,no 2006.230.07:16:08.16;drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.230.07:16:08.16;drivev13,15.000,268,10.000,10.000,10.000 2006.230.07:16:08.16;drivev21,330,270,no 2006.230.07:16:08.16;drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.230.07:16:08.16;drivev23,15.000,268,10.000,10.000,10.000 2006.230.07:16:08.16;head10,all,all,all,odd,adaptive,no,5.0000,1 2006.230.07:16:08.16;head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.230.07:16:08.16;head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.230.07:16:08.16;head20,all,all,all,odd,adaptive,no,5.0000,1 2006.230.07:16:08.16;head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.230.07:16:08.16;head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.230.07:16:08.16;time,-0.364,101.533,rate 2006.230.07:16:08.16;flagr,200 2006.230.07:16:08.16:" K06231 2006 TSUKUB32 T Ts 2006.230.07:16:08.16:" T TSUKUB32 AZEL .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 Ts 108 2006.230.07:16:08.16:" Ts TSUKUB32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.230.07:16:08.16:" 108 TSUKUB32 14 17400 2006.230.07:16:08.16:" drudg version 050216 compiled under FS 9.7.07 2006.230.07:16:08.16:" Rack=K4-2/M4 Recorder 1=K5 Recorder 2=none 2006.230.07:16:08.16:exper_initi 2006.230.07:16:08.16&exper_initi/proc_library 2006.230.07:16:08.16&exper_initi/sched_initi 2006.230.07:16:08.16:!2006.231.06:29:50 2006.230.07:16:08.16&proc_library/" k06231 tsukub32 ts 2006.230.07:16:08.16&proc_library/" drudg version 050216 compiled under fs 9.7.7 2006.230.07:16:08.16&proc_library/"< k4-2/m4 rack >< k5 recorder 1> 2006.230.07:16:08.16&sched_initi/startcheck 2006.230.07:16:08.16&startcheck/sy=check_fsrun.pl & 2006.230.07:16:08.16&startcheck/" sy=/usr2/oper/temp/chmem.sh >& /dev/null & 2006.230.07:16:18.14;cable 2006.230.07:16:18.21/cable/+6.3683E-03 2006.230.07:17:33.06;cablelong 2006.230.07:17:33.18/cablelong/+6.9251E-03 2006.230.07:17:37.44;cablediff 2006.230.07:17:37.44/cablediff/556.8e-6,+ 2006.230.07:18:30.90;cable 2006.230.07:18:31.02/cable/+6.3708E-03 2006.230.07:18:39.26;wx 2006.230.07:18:39.26/wx/32.14,1001.6,72 2006.230.07:18:46.00;"Sky is fine. 2006.230.07:18:50.57;xfe 2006.230.07:18:50.65/xfe/off,on,12.5 2006.230.07:18:58.27;clockoff 2006.230.07:18:58.27&clockoff/"gps-fmout=1p 2006.230.07:18:58.27&clockoff/fmout-gps=1p 2006.230.07:18:59.07/fmout-gps/S +4.23E-07 2006.230.13:12:36.90?ERROR st -97 Trouble decoding pressure data 2006.230.13:12:36.90#wxget#07 1.2 2.9 27.18 991003.8 2006.231.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.231.06:29:50.02:!2006.231.07:19:50 2006.231.07:19:50.00:unstow 2006.231.07:19:50.00&unstow/antenna=e 2006.231.07:19:50.00&unstow/!+10s 2006.231.07:19:50.00&unstow/antenna=m2 2006.231.07:20:02.01:scan_name=231-0730,k06231,60 2006.231.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.231.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.231.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.231.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.231.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.231.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.231.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.231.07:20:03.14:ready_k5 2006.231.07:20:03.14&ready_k5/obsinfo=st 2006.231.07:20:03.14&ready_k5/autoobs=1 2006.231.07:20:03.14&ready_k5/autoobs=2 2006.231.07:20:03.14&ready_k5/autoobs=3 2006.231.07:20:03.14&ready_k5/autoobs=4 2006.231.07:20:03.14&ready_k5/obsinfo 2006.231.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.231.07:20:03.14#flagr#flagr/antenna,new-source 2006.231.07:20:06.35/autoobs//k5ts1/ autoobs started! 2006.231.07:20:09.45/autoobs//k5ts2/ autoobs started! 2006.231.07:20:12.58/autoobs//k5ts3/ autoobs started! 2006.231.07:20:15.70/autoobs//k5ts4/ autoobs started! 2006.231.07:20:15.73/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:20:15.73:4f8m12a=1 2006.231.07:20:15.73&4f8m12a/xlog=on 2006.231.07:20:15.73&4f8m12a/echo=on 2006.231.07:20:15.73&4f8m12a/pcalon 2006.231.07:20:15.73&4f8m12a/"tpicd=stop 2006.231.07:20:15.73&4f8m12a/vc4f8 2006.231.07:20:15.73&4f8m12a/ifd4f 2006.231.07:20:15.73&4f8m12a/"form=m,16.000,1:2 2006.231.07:20:15.73&4f8m12a/"tpicd 2006.231.07:20:15.73&4f8m12a/echo=off 2006.231.07:20:15.73&4f8m12a/xlog=off 2006.231.07:20:15.73$4f8m12a/echo=on 2006.231.07:20:15.73$4f8m12a/pcalon 2006.231.07:20:15.73&pcalon/"no phase cal control is implemented here 2006.231.07:20:15.73$pcalon/"no phase cal control is implemented here 2006.231.07:20:15.73$4f8m12a/"tpicd=stop 2006.231.07:20:15.73$4f8m12a/vc4f8 2006.231.07:20:15.73&vc4f8/valo=1,532.99 2006.231.07:20:15.74&vc4f8/va=1,8 2006.231.07:20:15.74&vc4f8/valo=2,572.99 2006.231.07:20:15.74&vc4f8/va=2,7 2006.231.07:20:15.74&vc4f8/valo=3,672.99 2006.231.07:20:15.74&vc4f8/va=3,8 2006.231.07:20:15.74&vc4f8/valo=4,832.99 2006.231.07:20:15.74&vc4f8/va=4,7 2006.231.07:20:15.74&vc4f8/valo=5,652.99 2006.231.07:20:15.74&vc4f8/va=5,7 2006.231.07:20:15.74&vc4f8/valo=6,772.99 2006.231.07:20:15.74&vc4f8/va=6,6 2006.231.07:20:15.74&vc4f8/valo=7,832.99 2006.231.07:20:15.74&vc4f8/va=7,6 2006.231.07:20:15.74&vc4f8/valo=8,852.99 2006.231.07:20:15.74&vc4f8/va=8,6 2006.231.07:20:15.74&vc4f8/vblo=1,632.99 2006.231.07:20:15.74&vc4f8/vb=1,4 2006.231.07:20:15.74&vc4f8/vblo=2,640.99 2006.231.07:20:15.74&vc4f8/vb=2,4 2006.231.07:20:15.74&vc4f8/vblo=3,656.99 2006.231.07:20:15.74&vc4f8/vb=3,4 2006.231.07:20:15.74&vc4f8/vblo=4,712.99 2006.231.07:20:15.74&vc4f8/vb=4,4 2006.231.07:20:15.74&vc4f8/vblo=5,744.99 2006.231.07:20:15.74&vc4f8/vb=5,3 2006.231.07:20:15.74&vc4f8/vblo=6,752.99 2006.231.07:20:15.74&vc4f8/vb=6,4 2006.231.07:20:15.74&vc4f8/vabw=wide 2006.231.07:20:15.74&vc4f8/vbbw=wide 2006.231.07:20:15.74$vc4f8/valo=1,532.99 2006.231.07:20:15.74#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.07:20:15.74#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.07:20:15.74#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:15.74#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:20:15.74#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:20:15.74#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:20:15.74#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:20:15.74#ibcon#first serial, iclass 10, count 0 2006.231.07:20:15.74#ibcon#enter sib2, iclass 10, count 0 2006.231.07:20:15.74#ibcon#flushed, iclass 10, count 0 2006.231.07:20:15.74#ibcon#about to write, iclass 10, count 0 2006.231.07:20:15.74#ibcon#wrote, iclass 10, count 0 2006.231.07:20:15.74#ibcon#about to read 3, iclass 10, count 0 2006.231.07:20:15.77#ibcon#read 3, iclass 10, count 0 2006.231.07:20:15.77#ibcon#about to read 4, iclass 10, count 0 2006.231.07:20:15.77#ibcon#read 4, iclass 10, count 0 2006.231.07:20:15.77#ibcon#about to read 5, iclass 10, count 0 2006.231.07:20:15.77#ibcon#read 5, iclass 10, count 0 2006.231.07:20:15.77#ibcon#about to read 6, iclass 10, count 0 2006.231.07:20:15.77#ibcon#read 6, iclass 10, count 0 2006.231.07:20:15.77#ibcon#end of sib2, iclass 10, count 0 2006.231.07:20:15.77#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:20:15.77#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:20:15.77#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:20:15.77#ibcon#*before write, iclass 10, count 0 2006.231.07:20:15.77#ibcon#enter sib2, iclass 10, count 0 2006.231.07:20:15.77#ibcon#flushed, iclass 10, count 0 2006.231.07:20:15.77#ibcon#about to write, iclass 10, count 0 2006.231.07:20:15.77#ibcon#wrote, iclass 10, count 0 2006.231.07:20:15.77#ibcon#about to read 3, iclass 10, count 0 2006.231.07:20:15.84#ibcon#read 3, iclass 10, count 0 2006.231.07:20:15.84#ibcon#about to read 4, iclass 10, count 0 2006.231.07:20:15.84#ibcon#read 4, iclass 10, count 0 2006.231.07:20:15.84#ibcon#about to read 5, iclass 10, count 0 2006.231.07:20:15.84#ibcon#read 5, iclass 10, count 0 2006.231.07:20:15.84#ibcon#about to read 6, iclass 10, count 0 2006.231.07:20:15.84#ibcon#read 6, iclass 10, count 0 2006.231.07:20:15.84#ibcon#end of sib2, iclass 10, count 0 2006.231.07:20:15.84#ibcon#*after write, iclass 10, count 0 2006.231.07:20:15.84#ibcon#*before return 0, iclass 10, count 0 2006.231.07:20:15.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:20:15.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:20:15.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:20:15.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:20:15.84$vc4f8/va=1,8 2006.231.07:20:15.84#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.07:20:15.84#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.07:20:15.84#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:15.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:20:15.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:20:15.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:20:15.84#ibcon#enter wrdev, iclass 12, count 2 2006.231.07:20:15.84#ibcon#first serial, iclass 12, count 2 2006.231.07:20:15.84#ibcon#enter sib2, iclass 12, count 2 2006.231.07:20:15.84#ibcon#flushed, iclass 12, count 2 2006.231.07:20:15.84#ibcon#about to write, iclass 12, count 2 2006.231.07:20:15.84#ibcon#wrote, iclass 12, count 2 2006.231.07:20:15.84#ibcon#about to read 3, iclass 12, count 2 2006.231.07:20:15.86#ibcon#read 3, iclass 12, count 2 2006.231.07:20:15.86#ibcon#about to read 4, iclass 12, count 2 2006.231.07:20:15.86#ibcon#read 4, iclass 12, count 2 2006.231.07:20:15.86#ibcon#about to read 5, iclass 12, count 2 2006.231.07:20:15.86#ibcon#read 5, iclass 12, count 2 2006.231.07:20:15.86#ibcon#about to read 6, iclass 12, count 2 2006.231.07:20:15.86#ibcon#read 6, iclass 12, count 2 2006.231.07:20:15.86#ibcon#end of sib2, iclass 12, count 2 2006.231.07:20:15.86#ibcon#*mode == 0, iclass 12, count 2 2006.231.07:20:15.86#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.07:20:15.86#ibcon#[25=AT01-08\r\n] 2006.231.07:20:15.86#ibcon#*before write, iclass 12, count 2 2006.231.07:20:15.86#ibcon#enter sib2, iclass 12, count 2 2006.231.07:20:15.86#ibcon#flushed, iclass 12, count 2 2006.231.07:20:15.86#ibcon#about to write, iclass 12, count 2 2006.231.07:20:15.86#ibcon#wrote, iclass 12, count 2 2006.231.07:20:15.86#ibcon#about to read 3, iclass 12, count 2 2006.231.07:20:15.90#ibcon#read 3, iclass 12, count 2 2006.231.07:20:15.90#ibcon#about to read 4, iclass 12, count 2 2006.231.07:20:15.90#ibcon#read 4, iclass 12, count 2 2006.231.07:20:15.90#ibcon#about to read 5, iclass 12, count 2 2006.231.07:20:15.90#ibcon#read 5, iclass 12, count 2 2006.231.07:20:15.90#ibcon#about to read 6, iclass 12, count 2 2006.231.07:20:15.90#ibcon#read 6, iclass 12, count 2 2006.231.07:20:15.90#ibcon#end of sib2, iclass 12, count 2 2006.231.07:20:15.90#ibcon#*after write, iclass 12, count 2 2006.231.07:20:15.90#ibcon#*before return 0, iclass 12, count 2 2006.231.07:20:15.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:20:15.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:20:15.90#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.07:20:15.90#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:15.90#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:20:16.02#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:20:16.02#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:20:16.02#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:20:16.02#ibcon#first serial, iclass 12, count 0 2006.231.07:20:16.02#ibcon#enter sib2, iclass 12, count 0 2006.231.07:20:16.02#ibcon#flushed, iclass 12, count 0 2006.231.07:20:16.02#ibcon#about to write, iclass 12, count 0 2006.231.07:20:16.02#ibcon#wrote, iclass 12, count 0 2006.231.07:20:16.02#ibcon#about to read 3, iclass 12, count 0 2006.231.07:20:16.04#ibcon#read 3, iclass 12, count 0 2006.231.07:20:16.04#ibcon#about to read 4, iclass 12, count 0 2006.231.07:20:16.04#ibcon#read 4, iclass 12, count 0 2006.231.07:20:16.04#ibcon#about to read 5, iclass 12, count 0 2006.231.07:20:16.04#ibcon#read 5, iclass 12, count 0 2006.231.07:20:16.04#ibcon#about to read 6, iclass 12, count 0 2006.231.07:20:16.04#ibcon#read 6, iclass 12, count 0 2006.231.07:20:16.04#ibcon#end of sib2, iclass 12, count 0 2006.231.07:20:16.04#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:20:16.04#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:20:16.04#ibcon#[25=USB\r\n] 2006.231.07:20:16.04#ibcon#*before write, iclass 12, count 0 2006.231.07:20:16.04#ibcon#enter sib2, iclass 12, count 0 2006.231.07:20:16.04#ibcon#flushed, iclass 12, count 0 2006.231.07:20:16.04#ibcon#about to write, iclass 12, count 0 2006.231.07:20:16.04#ibcon#wrote, iclass 12, count 0 2006.231.07:20:16.04#ibcon#about to read 3, iclass 12, count 0 2006.231.07:20:16.07#ibcon#read 3, iclass 12, count 0 2006.231.07:20:16.07#ibcon#about to read 4, iclass 12, count 0 2006.231.07:20:16.07#ibcon#read 4, iclass 12, count 0 2006.231.07:20:16.07#ibcon#about to read 5, iclass 12, count 0 2006.231.07:20:16.07#ibcon#read 5, iclass 12, count 0 2006.231.07:20:16.07#ibcon#about to read 6, iclass 12, count 0 2006.231.07:20:16.07#ibcon#read 6, iclass 12, count 0 2006.231.07:20:16.07#ibcon#end of sib2, iclass 12, count 0 2006.231.07:20:16.07#ibcon#*after write, iclass 12, count 0 2006.231.07:20:16.07#ibcon#*before return 0, iclass 12, count 0 2006.231.07:20:16.07#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:20:16.07#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:20:16.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:20:16.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:20:16.07$vc4f8/valo=2,572.99 2006.231.07:20:16.07#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.07:20:16.07#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.07:20:16.07#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:16.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:20:16.07#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:20:16.07#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:20:16.07#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:20:16.07#ibcon#first serial, iclass 14, count 0 2006.231.07:20:16.07#ibcon#enter sib2, iclass 14, count 0 2006.231.07:20:16.07#ibcon#flushed, iclass 14, count 0 2006.231.07:20:16.07#ibcon#about to write, iclass 14, count 0 2006.231.07:20:16.07#ibcon#wrote, iclass 14, count 0 2006.231.07:20:16.07#ibcon#about to read 3, iclass 14, count 0 2006.231.07:20:16.09#ibcon#read 3, iclass 14, count 0 2006.231.07:20:16.09#ibcon#about to read 4, iclass 14, count 0 2006.231.07:20:16.09#ibcon#read 4, iclass 14, count 0 2006.231.07:20:16.09#ibcon#about to read 5, iclass 14, count 0 2006.231.07:20:16.09#ibcon#read 5, iclass 14, count 0 2006.231.07:20:16.09#ibcon#about to read 6, iclass 14, count 0 2006.231.07:20:16.09#ibcon#read 6, iclass 14, count 0 2006.231.07:20:16.09#ibcon#end of sib2, iclass 14, count 0 2006.231.07:20:16.09#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:20:16.09#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:20:16.09#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:20:16.09#ibcon#*before write, iclass 14, count 0 2006.231.07:20:16.09#ibcon#enter sib2, iclass 14, count 0 2006.231.07:20:16.09#ibcon#flushed, iclass 14, count 0 2006.231.07:20:16.09#ibcon#about to write, iclass 14, count 0 2006.231.07:20:16.09#ibcon#wrote, iclass 14, count 0 2006.231.07:20:16.09#ibcon#about to read 3, iclass 14, count 0 2006.231.07:20:16.13#ibcon#read 3, iclass 14, count 0 2006.231.07:20:16.13#ibcon#about to read 4, iclass 14, count 0 2006.231.07:20:16.13#ibcon#read 4, iclass 14, count 0 2006.231.07:20:16.13#ibcon#about to read 5, iclass 14, count 0 2006.231.07:20:16.13#ibcon#read 5, iclass 14, count 0 2006.231.07:20:16.13#ibcon#about to read 6, iclass 14, count 0 2006.231.07:20:16.13#ibcon#read 6, iclass 14, count 0 2006.231.07:20:16.13#ibcon#end of sib2, iclass 14, count 0 2006.231.07:20:16.13#ibcon#*after write, iclass 14, count 0 2006.231.07:20:16.13#ibcon#*before return 0, iclass 14, count 0 2006.231.07:20:16.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:20:16.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:20:16.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:20:16.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:20:16.13$vc4f8/va=2,7 2006.231.07:20:16.13#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.07:20:16.13#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.07:20:16.13#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:16.13#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:20:16.15#abcon#<5=/07 3.2 7.3 31.08 851004.5\r\n> 2006.231.07:20:16.17#abcon#{5=INTERFACE CLEAR} 2006.231.07:20:16.19#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:20:16.19#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:20:16.19#ibcon#enter wrdev, iclass 17, count 2 2006.231.07:20:16.19#ibcon#first serial, iclass 17, count 2 2006.231.07:20:16.19#ibcon#enter sib2, iclass 17, count 2 2006.231.07:20:16.19#ibcon#flushed, iclass 17, count 2 2006.231.07:20:16.19#ibcon#about to write, iclass 17, count 2 2006.231.07:20:16.19#ibcon#wrote, iclass 17, count 2 2006.231.07:20:16.19#ibcon#about to read 3, iclass 17, count 2 2006.231.07:20:16.21#ibcon#read 3, iclass 17, count 2 2006.231.07:20:16.21#ibcon#about to read 4, iclass 17, count 2 2006.231.07:20:16.21#ibcon#read 4, iclass 17, count 2 2006.231.07:20:16.21#ibcon#about to read 5, iclass 17, count 2 2006.231.07:20:16.21#ibcon#read 5, iclass 17, count 2 2006.231.07:20:16.21#ibcon#about to read 6, iclass 17, count 2 2006.231.07:20:16.21#ibcon#read 6, iclass 17, count 2 2006.231.07:20:16.21#ibcon#end of sib2, iclass 17, count 2 2006.231.07:20:16.21#ibcon#*mode == 0, iclass 17, count 2 2006.231.07:20:16.21#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.07:20:16.21#ibcon#[25=AT02-07\r\n] 2006.231.07:20:16.21#ibcon#*before write, iclass 17, count 2 2006.231.07:20:16.21#ibcon#enter sib2, iclass 17, count 2 2006.231.07:20:16.21#ibcon#flushed, iclass 17, count 2 2006.231.07:20:16.21#ibcon#about to write, iclass 17, count 2 2006.231.07:20:16.21#ibcon#wrote, iclass 17, count 2 2006.231.07:20:16.21#ibcon#about to read 3, iclass 17, count 2 2006.231.07:20:16.23#abcon#[5=S1D000X0/0*\r\n] 2006.231.07:20:16.24#ibcon#read 3, iclass 17, count 2 2006.231.07:20:16.24#ibcon#about to read 4, iclass 17, count 2 2006.231.07:20:16.24#ibcon#read 4, iclass 17, count 2 2006.231.07:20:16.24#ibcon#about to read 5, iclass 17, count 2 2006.231.07:20:16.24#ibcon#read 5, iclass 17, count 2 2006.231.07:20:16.24#ibcon#about to read 6, iclass 17, count 2 2006.231.07:20:16.24#ibcon#read 6, iclass 17, count 2 2006.231.07:20:16.24#ibcon#end of sib2, iclass 17, count 2 2006.231.07:20:16.24#ibcon#*after write, iclass 17, count 2 2006.231.07:20:16.24#ibcon#*before return 0, iclass 17, count 2 2006.231.07:20:16.24#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:20:16.24#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:20:16.24#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.07:20:16.24#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:16.24#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:20:16.36#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:20:16.36#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:20:16.36#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:20:16.36#ibcon#first serial, iclass 17, count 0 2006.231.07:20:16.36#ibcon#enter sib2, iclass 17, count 0 2006.231.07:20:16.36#ibcon#flushed, iclass 17, count 0 2006.231.07:20:16.36#ibcon#about to write, iclass 17, count 0 2006.231.07:20:16.36#ibcon#wrote, iclass 17, count 0 2006.231.07:20:16.36#ibcon#about to read 3, iclass 17, count 0 2006.231.07:20:16.38#ibcon#read 3, iclass 17, count 0 2006.231.07:20:16.38#ibcon#about to read 4, iclass 17, count 0 2006.231.07:20:16.38#ibcon#read 4, iclass 17, count 0 2006.231.07:20:16.38#ibcon#about to read 5, iclass 17, count 0 2006.231.07:20:16.38#ibcon#read 5, iclass 17, count 0 2006.231.07:20:16.38#ibcon#about to read 6, iclass 17, count 0 2006.231.07:20:16.38#ibcon#read 6, iclass 17, count 0 2006.231.07:20:16.38#ibcon#end of sib2, iclass 17, count 0 2006.231.07:20:16.38#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:20:16.38#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:20:16.38#ibcon#[25=USB\r\n] 2006.231.07:20:16.38#ibcon#*before write, iclass 17, count 0 2006.231.07:20:16.38#ibcon#enter sib2, iclass 17, count 0 2006.231.07:20:16.38#ibcon#flushed, iclass 17, count 0 2006.231.07:20:16.38#ibcon#about to write, iclass 17, count 0 2006.231.07:20:16.38#ibcon#wrote, iclass 17, count 0 2006.231.07:20:16.38#ibcon#about to read 3, iclass 17, count 0 2006.231.07:20:16.41#ibcon#read 3, iclass 17, count 0 2006.231.07:20:16.41#ibcon#about to read 4, iclass 17, count 0 2006.231.07:20:16.41#ibcon#read 4, iclass 17, count 0 2006.231.07:20:16.41#ibcon#about to read 5, iclass 17, count 0 2006.231.07:20:16.41#ibcon#read 5, iclass 17, count 0 2006.231.07:20:16.41#ibcon#about to read 6, iclass 17, count 0 2006.231.07:20:16.41#ibcon#read 6, iclass 17, count 0 2006.231.07:20:16.41#ibcon#end of sib2, iclass 17, count 0 2006.231.07:20:16.41#ibcon#*after write, iclass 17, count 0 2006.231.07:20:16.41#ibcon#*before return 0, iclass 17, count 0 2006.231.07:20:16.41#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:20:16.41#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:20:16.41#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:20:16.41#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:20:16.41$vc4f8/valo=3,672.99 2006.231.07:20:16.41#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.07:20:16.41#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.07:20:16.41#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:16.41#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:20:16.41#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:20:16.41#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:20:16.41#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:20:16.41#ibcon#first serial, iclass 22, count 0 2006.231.07:20:16.41#ibcon#enter sib2, iclass 22, count 0 2006.231.07:20:16.41#ibcon#flushed, iclass 22, count 0 2006.231.07:20:16.41#ibcon#about to write, iclass 22, count 0 2006.231.07:20:16.41#ibcon#wrote, iclass 22, count 0 2006.231.07:20:16.41#ibcon#about to read 3, iclass 22, count 0 2006.231.07:20:16.43#ibcon#read 3, iclass 22, count 0 2006.231.07:20:16.43#ibcon#about to read 4, iclass 22, count 0 2006.231.07:20:16.43#ibcon#read 4, iclass 22, count 0 2006.231.07:20:16.43#ibcon#about to read 5, iclass 22, count 0 2006.231.07:20:16.43#ibcon#read 5, iclass 22, count 0 2006.231.07:20:16.43#ibcon#about to read 6, iclass 22, count 0 2006.231.07:20:16.43#ibcon#read 6, iclass 22, count 0 2006.231.07:20:16.43#ibcon#end of sib2, iclass 22, count 0 2006.231.07:20:16.43#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:20:16.43#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:20:16.43#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:20:16.43#ibcon#*before write, iclass 22, count 0 2006.231.07:20:16.43#ibcon#enter sib2, iclass 22, count 0 2006.231.07:20:16.43#ibcon#flushed, iclass 22, count 0 2006.231.07:20:16.43#ibcon#about to write, iclass 22, count 0 2006.231.07:20:16.43#ibcon#wrote, iclass 22, count 0 2006.231.07:20:16.43#ibcon#about to read 3, iclass 22, count 0 2006.231.07:20:16.47#ibcon#read 3, iclass 22, count 0 2006.231.07:20:16.47#ibcon#about to read 4, iclass 22, count 0 2006.231.07:20:16.47#ibcon#read 4, iclass 22, count 0 2006.231.07:20:16.47#ibcon#about to read 5, iclass 22, count 0 2006.231.07:20:16.47#ibcon#read 5, iclass 22, count 0 2006.231.07:20:16.47#ibcon#about to read 6, iclass 22, count 0 2006.231.07:20:16.47#ibcon#read 6, iclass 22, count 0 2006.231.07:20:16.47#ibcon#end of sib2, iclass 22, count 0 2006.231.07:20:16.47#ibcon#*after write, iclass 22, count 0 2006.231.07:20:16.47#ibcon#*before return 0, iclass 22, count 0 2006.231.07:20:16.47#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:20:16.47#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:20:16.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:20:16.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:20:16.47$vc4f8/va=3,8 2006.231.07:20:16.47#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.07:20:16.47#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.07:20:16.47#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:16.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:20:16.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:20:16.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:20:16.53#ibcon#enter wrdev, iclass 24, count 2 2006.231.07:20:16.53#ibcon#first serial, iclass 24, count 2 2006.231.07:20:16.53#ibcon#enter sib2, iclass 24, count 2 2006.231.07:20:16.53#ibcon#flushed, iclass 24, count 2 2006.231.07:20:16.53#ibcon#about to write, iclass 24, count 2 2006.231.07:20:16.53#ibcon#wrote, iclass 24, count 2 2006.231.07:20:16.53#ibcon#about to read 3, iclass 24, count 2 2006.231.07:20:16.55#ibcon#read 3, iclass 24, count 2 2006.231.07:20:16.55#ibcon#about to read 4, iclass 24, count 2 2006.231.07:20:16.55#ibcon#read 4, iclass 24, count 2 2006.231.07:20:16.55#ibcon#about to read 5, iclass 24, count 2 2006.231.07:20:16.55#ibcon#read 5, iclass 24, count 2 2006.231.07:20:16.55#ibcon#about to read 6, iclass 24, count 2 2006.231.07:20:16.55#ibcon#read 6, iclass 24, count 2 2006.231.07:20:16.55#ibcon#end of sib2, iclass 24, count 2 2006.231.07:20:16.55#ibcon#*mode == 0, iclass 24, count 2 2006.231.07:20:16.55#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.07:20:16.55#ibcon#[25=AT03-08\r\n] 2006.231.07:20:16.55#ibcon#*before write, iclass 24, count 2 2006.231.07:20:16.55#ibcon#enter sib2, iclass 24, count 2 2006.231.07:20:16.55#ibcon#flushed, iclass 24, count 2 2006.231.07:20:16.55#ibcon#about to write, iclass 24, count 2 2006.231.07:20:16.55#ibcon#wrote, iclass 24, count 2 2006.231.07:20:16.55#ibcon#about to read 3, iclass 24, count 2 2006.231.07:20:16.59#ibcon#read 3, iclass 24, count 2 2006.231.07:20:16.59#ibcon#about to read 4, iclass 24, count 2 2006.231.07:20:16.59#ibcon#read 4, iclass 24, count 2 2006.231.07:20:16.59#ibcon#about to read 5, iclass 24, count 2 2006.231.07:20:16.59#ibcon#read 5, iclass 24, count 2 2006.231.07:20:16.59#ibcon#about to read 6, iclass 24, count 2 2006.231.07:20:16.59#ibcon#read 6, iclass 24, count 2 2006.231.07:20:16.59#ibcon#end of sib2, iclass 24, count 2 2006.231.07:20:16.59#ibcon#*after write, iclass 24, count 2 2006.231.07:20:16.59#ibcon#*before return 0, iclass 24, count 2 2006.231.07:20:16.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:20:16.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:20:16.59#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.07:20:16.59#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:16.59#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:20:16.71#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:20:16.71#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:20:16.71#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:20:16.71#ibcon#first serial, iclass 24, count 0 2006.231.07:20:16.71#ibcon#enter sib2, iclass 24, count 0 2006.231.07:20:16.71#ibcon#flushed, iclass 24, count 0 2006.231.07:20:16.71#ibcon#about to write, iclass 24, count 0 2006.231.07:20:16.71#ibcon#wrote, iclass 24, count 0 2006.231.07:20:16.71#ibcon#about to read 3, iclass 24, count 0 2006.231.07:20:16.73#ibcon#read 3, iclass 24, count 0 2006.231.07:20:16.73#ibcon#about to read 4, iclass 24, count 0 2006.231.07:20:16.73#ibcon#read 4, iclass 24, count 0 2006.231.07:20:16.73#ibcon#about to read 5, iclass 24, count 0 2006.231.07:20:16.73#ibcon#read 5, iclass 24, count 0 2006.231.07:20:16.73#ibcon#about to read 6, iclass 24, count 0 2006.231.07:20:16.73#ibcon#read 6, iclass 24, count 0 2006.231.07:20:16.73#ibcon#end of sib2, iclass 24, count 0 2006.231.07:20:16.73#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:20:16.73#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:20:16.73#ibcon#[25=USB\r\n] 2006.231.07:20:16.73#ibcon#*before write, iclass 24, count 0 2006.231.07:20:16.73#ibcon#enter sib2, iclass 24, count 0 2006.231.07:20:16.73#ibcon#flushed, iclass 24, count 0 2006.231.07:20:16.73#ibcon#about to write, iclass 24, count 0 2006.231.07:20:16.73#ibcon#wrote, iclass 24, count 0 2006.231.07:20:16.73#ibcon#about to read 3, iclass 24, count 0 2006.231.07:20:16.76#ibcon#read 3, iclass 24, count 0 2006.231.07:20:16.76#ibcon#about to read 4, iclass 24, count 0 2006.231.07:20:16.76#ibcon#read 4, iclass 24, count 0 2006.231.07:20:16.76#ibcon#about to read 5, iclass 24, count 0 2006.231.07:20:16.76#ibcon#read 5, iclass 24, count 0 2006.231.07:20:16.76#ibcon#about to read 6, iclass 24, count 0 2006.231.07:20:16.76#ibcon#read 6, iclass 24, count 0 2006.231.07:20:16.76#ibcon#end of sib2, iclass 24, count 0 2006.231.07:20:16.76#ibcon#*after write, iclass 24, count 0 2006.231.07:20:16.76#ibcon#*before return 0, iclass 24, count 0 2006.231.07:20:16.76#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:20:16.76#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:20:16.76#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:20:16.76#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:20:16.76$vc4f8/valo=4,832.99 2006.231.07:20:16.76#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:20:16.76#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:20:16.76#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:16.76#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:20:16.76#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:20:16.76#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:20:16.76#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:20:16.76#ibcon#first serial, iclass 26, count 0 2006.231.07:20:16.76#ibcon#enter sib2, iclass 26, count 0 2006.231.07:20:16.76#ibcon#flushed, iclass 26, count 0 2006.231.07:20:16.76#ibcon#about to write, iclass 26, count 0 2006.231.07:20:16.76#ibcon#wrote, iclass 26, count 0 2006.231.07:20:16.76#ibcon#about to read 3, iclass 26, count 0 2006.231.07:20:16.78#ibcon#read 3, iclass 26, count 0 2006.231.07:20:16.78#ibcon#about to read 4, iclass 26, count 0 2006.231.07:20:16.78#ibcon#read 4, iclass 26, count 0 2006.231.07:20:16.78#ibcon#about to read 5, iclass 26, count 0 2006.231.07:20:16.78#ibcon#read 5, iclass 26, count 0 2006.231.07:20:16.78#ibcon#about to read 6, iclass 26, count 0 2006.231.07:20:16.78#ibcon#read 6, iclass 26, count 0 2006.231.07:20:16.78#ibcon#end of sib2, iclass 26, count 0 2006.231.07:20:16.78#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:20:16.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:20:16.78#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:20:16.78#ibcon#*before write, iclass 26, count 0 2006.231.07:20:16.78#ibcon#enter sib2, iclass 26, count 0 2006.231.07:20:16.78#ibcon#flushed, iclass 26, count 0 2006.231.07:20:16.78#ibcon#about to write, iclass 26, count 0 2006.231.07:20:16.78#ibcon#wrote, iclass 26, count 0 2006.231.07:20:16.78#ibcon#about to read 3, iclass 26, count 0 2006.231.07:20:16.82#ibcon#read 3, iclass 26, count 0 2006.231.07:20:16.82#ibcon#about to read 4, iclass 26, count 0 2006.231.07:20:16.82#ibcon#read 4, iclass 26, count 0 2006.231.07:20:16.82#ibcon#about to read 5, iclass 26, count 0 2006.231.07:20:16.82#ibcon#read 5, iclass 26, count 0 2006.231.07:20:16.82#ibcon#about to read 6, iclass 26, count 0 2006.231.07:20:16.82#ibcon#read 6, iclass 26, count 0 2006.231.07:20:16.82#ibcon#end of sib2, iclass 26, count 0 2006.231.07:20:16.82#ibcon#*after write, iclass 26, count 0 2006.231.07:20:16.82#ibcon#*before return 0, iclass 26, count 0 2006.231.07:20:16.82#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:20:16.82#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:20:16.82#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:20:16.82#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:20:16.82$vc4f8/va=4,7 2006.231.07:20:16.82#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.07:20:16.82#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.07:20:16.82#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:16.82#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:20:16.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:20:16.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:20:16.88#ibcon#enter wrdev, iclass 28, count 2 2006.231.07:20:16.88#ibcon#first serial, iclass 28, count 2 2006.231.07:20:16.88#ibcon#enter sib2, iclass 28, count 2 2006.231.07:20:16.88#ibcon#flushed, iclass 28, count 2 2006.231.07:20:16.88#ibcon#about to write, iclass 28, count 2 2006.231.07:20:16.88#ibcon#wrote, iclass 28, count 2 2006.231.07:20:16.88#ibcon#about to read 3, iclass 28, count 2 2006.231.07:20:16.90#ibcon#read 3, iclass 28, count 2 2006.231.07:20:16.90#ibcon#about to read 4, iclass 28, count 2 2006.231.07:20:16.90#ibcon#read 4, iclass 28, count 2 2006.231.07:20:16.90#ibcon#about to read 5, iclass 28, count 2 2006.231.07:20:16.90#ibcon#read 5, iclass 28, count 2 2006.231.07:20:16.90#ibcon#about to read 6, iclass 28, count 2 2006.231.07:20:16.90#ibcon#read 6, iclass 28, count 2 2006.231.07:20:16.90#ibcon#end of sib2, iclass 28, count 2 2006.231.07:20:16.90#ibcon#*mode == 0, iclass 28, count 2 2006.231.07:20:16.90#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.07:20:16.90#ibcon#[25=AT04-07\r\n] 2006.231.07:20:16.90#ibcon#*before write, iclass 28, count 2 2006.231.07:20:16.90#ibcon#enter sib2, iclass 28, count 2 2006.231.07:20:16.90#ibcon#flushed, iclass 28, count 2 2006.231.07:20:16.90#ibcon#about to write, iclass 28, count 2 2006.231.07:20:16.90#ibcon#wrote, iclass 28, count 2 2006.231.07:20:16.90#ibcon#about to read 3, iclass 28, count 2 2006.231.07:20:16.93#ibcon#read 3, iclass 28, count 2 2006.231.07:20:16.93#ibcon#about to read 4, iclass 28, count 2 2006.231.07:20:16.93#ibcon#read 4, iclass 28, count 2 2006.231.07:20:16.93#ibcon#about to read 5, iclass 28, count 2 2006.231.07:20:16.93#ibcon#read 5, iclass 28, count 2 2006.231.07:20:16.93#ibcon#about to read 6, iclass 28, count 2 2006.231.07:20:16.93#ibcon#read 6, iclass 28, count 2 2006.231.07:20:16.93#ibcon#end of sib2, iclass 28, count 2 2006.231.07:20:16.93#ibcon#*after write, iclass 28, count 2 2006.231.07:20:16.93#ibcon#*before return 0, iclass 28, count 2 2006.231.07:20:16.93#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:20:16.93#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:20:16.93#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.07:20:16.93#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:16.93#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:20:17.05#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:20:17.05#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:20:17.05#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:20:17.05#ibcon#first serial, iclass 28, count 0 2006.231.07:20:17.05#ibcon#enter sib2, iclass 28, count 0 2006.231.07:20:17.05#ibcon#flushed, iclass 28, count 0 2006.231.07:20:17.05#ibcon#about to write, iclass 28, count 0 2006.231.07:20:17.05#ibcon#wrote, iclass 28, count 0 2006.231.07:20:17.05#ibcon#about to read 3, iclass 28, count 0 2006.231.07:20:17.07#ibcon#read 3, iclass 28, count 0 2006.231.07:20:17.07#ibcon#about to read 4, iclass 28, count 0 2006.231.07:20:17.07#ibcon#read 4, iclass 28, count 0 2006.231.07:20:17.07#ibcon#about to read 5, iclass 28, count 0 2006.231.07:20:17.07#ibcon#read 5, iclass 28, count 0 2006.231.07:20:17.07#ibcon#about to read 6, iclass 28, count 0 2006.231.07:20:17.07#ibcon#read 6, iclass 28, count 0 2006.231.07:20:17.07#ibcon#end of sib2, iclass 28, count 0 2006.231.07:20:17.07#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:20:17.07#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:20:17.07#ibcon#[25=USB\r\n] 2006.231.07:20:17.07#ibcon#*before write, iclass 28, count 0 2006.231.07:20:17.07#ibcon#enter sib2, iclass 28, count 0 2006.231.07:20:17.07#ibcon#flushed, iclass 28, count 0 2006.231.07:20:17.07#ibcon#about to write, iclass 28, count 0 2006.231.07:20:17.07#ibcon#wrote, iclass 28, count 0 2006.231.07:20:17.07#ibcon#about to read 3, iclass 28, count 0 2006.231.07:20:17.10#ibcon#read 3, iclass 28, count 0 2006.231.07:20:17.10#ibcon#about to read 4, iclass 28, count 0 2006.231.07:20:17.10#ibcon#read 4, iclass 28, count 0 2006.231.07:20:17.10#ibcon#about to read 5, iclass 28, count 0 2006.231.07:20:17.10#ibcon#read 5, iclass 28, count 0 2006.231.07:20:17.10#ibcon#about to read 6, iclass 28, count 0 2006.231.07:20:17.10#ibcon#read 6, iclass 28, count 0 2006.231.07:20:17.10#ibcon#end of sib2, iclass 28, count 0 2006.231.07:20:17.10#ibcon#*after write, iclass 28, count 0 2006.231.07:20:17.10#ibcon#*before return 0, iclass 28, count 0 2006.231.07:20:17.10#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:20:17.10#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:20:17.10#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:20:17.10#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:20:17.10$vc4f8/valo=5,652.99 2006.231.07:20:17.10#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.07:20:17.10#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.07:20:17.10#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:17.10#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:20:17.10#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:20:17.10#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:20:17.10#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:20:17.10#ibcon#first serial, iclass 30, count 0 2006.231.07:20:17.10#ibcon#enter sib2, iclass 30, count 0 2006.231.07:20:17.10#ibcon#flushed, iclass 30, count 0 2006.231.07:20:17.10#ibcon#about to write, iclass 30, count 0 2006.231.07:20:17.10#ibcon#wrote, iclass 30, count 0 2006.231.07:20:17.10#ibcon#about to read 3, iclass 30, count 0 2006.231.07:20:17.12#ibcon#read 3, iclass 30, count 0 2006.231.07:20:17.12#ibcon#about to read 4, iclass 30, count 0 2006.231.07:20:17.12#ibcon#read 4, iclass 30, count 0 2006.231.07:20:17.12#ibcon#about to read 5, iclass 30, count 0 2006.231.07:20:17.12#ibcon#read 5, iclass 30, count 0 2006.231.07:20:17.12#ibcon#about to read 6, iclass 30, count 0 2006.231.07:20:17.12#ibcon#read 6, iclass 30, count 0 2006.231.07:20:17.12#ibcon#end of sib2, iclass 30, count 0 2006.231.07:20:17.12#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:20:17.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:20:17.12#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:20:17.12#ibcon#*before write, iclass 30, count 0 2006.231.07:20:17.12#ibcon#enter sib2, iclass 30, count 0 2006.231.07:20:17.12#ibcon#flushed, iclass 30, count 0 2006.231.07:20:17.12#ibcon#about to write, iclass 30, count 0 2006.231.07:20:17.12#ibcon#wrote, iclass 30, count 0 2006.231.07:20:17.12#ibcon#about to read 3, iclass 30, count 0 2006.231.07:20:17.16#ibcon#read 3, iclass 30, count 0 2006.231.07:20:17.16#ibcon#about to read 4, iclass 30, count 0 2006.231.07:20:17.16#ibcon#read 4, iclass 30, count 0 2006.231.07:20:17.16#ibcon#about to read 5, iclass 30, count 0 2006.231.07:20:17.16#ibcon#read 5, iclass 30, count 0 2006.231.07:20:17.16#ibcon#about to read 6, iclass 30, count 0 2006.231.07:20:17.16#ibcon#read 6, iclass 30, count 0 2006.231.07:20:17.16#ibcon#end of sib2, iclass 30, count 0 2006.231.07:20:17.16#ibcon#*after write, iclass 30, count 0 2006.231.07:20:17.16#ibcon#*before return 0, iclass 30, count 0 2006.231.07:20:17.16#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:20:17.16#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:20:17.16#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:20:17.16#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:20:17.16$vc4f8/va=5,7 2006.231.07:20:17.16#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.07:20:17.16#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.07:20:17.16#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:17.16#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:20:17.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:20:17.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:20:17.22#ibcon#enter wrdev, iclass 32, count 2 2006.231.07:20:17.22#ibcon#first serial, iclass 32, count 2 2006.231.07:20:17.22#ibcon#enter sib2, iclass 32, count 2 2006.231.07:20:17.22#ibcon#flushed, iclass 32, count 2 2006.231.07:20:17.22#ibcon#about to write, iclass 32, count 2 2006.231.07:20:17.22#ibcon#wrote, iclass 32, count 2 2006.231.07:20:17.22#ibcon#about to read 3, iclass 32, count 2 2006.231.07:20:17.24#ibcon#read 3, iclass 32, count 2 2006.231.07:20:17.24#ibcon#about to read 4, iclass 32, count 2 2006.231.07:20:17.24#ibcon#read 4, iclass 32, count 2 2006.231.07:20:17.24#ibcon#about to read 5, iclass 32, count 2 2006.231.07:20:17.24#ibcon#read 5, iclass 32, count 2 2006.231.07:20:17.24#ibcon#about to read 6, iclass 32, count 2 2006.231.07:20:17.24#ibcon#read 6, iclass 32, count 2 2006.231.07:20:17.24#ibcon#end of sib2, iclass 32, count 2 2006.231.07:20:17.24#ibcon#*mode == 0, iclass 32, count 2 2006.231.07:20:17.24#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.07:20:17.24#ibcon#[25=AT05-07\r\n] 2006.231.07:20:17.24#ibcon#*before write, iclass 32, count 2 2006.231.07:20:17.24#ibcon#enter sib2, iclass 32, count 2 2006.231.07:20:17.24#ibcon#flushed, iclass 32, count 2 2006.231.07:20:17.24#ibcon#about to write, iclass 32, count 2 2006.231.07:20:17.24#ibcon#wrote, iclass 32, count 2 2006.231.07:20:17.24#ibcon#about to read 3, iclass 32, count 2 2006.231.07:20:17.27#ibcon#read 3, iclass 32, count 2 2006.231.07:20:17.27#ibcon#about to read 4, iclass 32, count 2 2006.231.07:20:17.27#ibcon#read 4, iclass 32, count 2 2006.231.07:20:17.27#ibcon#about to read 5, iclass 32, count 2 2006.231.07:20:17.27#ibcon#read 5, iclass 32, count 2 2006.231.07:20:17.27#ibcon#about to read 6, iclass 32, count 2 2006.231.07:20:17.27#ibcon#read 6, iclass 32, count 2 2006.231.07:20:17.27#ibcon#end of sib2, iclass 32, count 2 2006.231.07:20:17.27#ibcon#*after write, iclass 32, count 2 2006.231.07:20:17.27#ibcon#*before return 0, iclass 32, count 2 2006.231.07:20:17.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:20:17.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:20:17.27#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.07:20:17.27#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:17.27#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:20:17.39#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:20:17.39#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:20:17.39#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:20:17.39#ibcon#first serial, iclass 32, count 0 2006.231.07:20:17.39#ibcon#enter sib2, iclass 32, count 0 2006.231.07:20:17.39#ibcon#flushed, iclass 32, count 0 2006.231.07:20:17.39#ibcon#about to write, iclass 32, count 0 2006.231.07:20:17.39#ibcon#wrote, iclass 32, count 0 2006.231.07:20:17.39#ibcon#about to read 3, iclass 32, count 0 2006.231.07:20:17.41#ibcon#read 3, iclass 32, count 0 2006.231.07:20:17.41#ibcon#about to read 4, iclass 32, count 0 2006.231.07:20:17.41#ibcon#read 4, iclass 32, count 0 2006.231.07:20:17.41#ibcon#about to read 5, iclass 32, count 0 2006.231.07:20:17.41#ibcon#read 5, iclass 32, count 0 2006.231.07:20:17.41#ibcon#about to read 6, iclass 32, count 0 2006.231.07:20:17.41#ibcon#read 6, iclass 32, count 0 2006.231.07:20:17.41#ibcon#end of sib2, iclass 32, count 0 2006.231.07:20:17.41#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:20:17.41#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:20:17.41#ibcon#[25=USB\r\n] 2006.231.07:20:17.41#ibcon#*before write, iclass 32, count 0 2006.231.07:20:17.41#ibcon#enter sib2, iclass 32, count 0 2006.231.07:20:17.41#ibcon#flushed, iclass 32, count 0 2006.231.07:20:17.41#ibcon#about to write, iclass 32, count 0 2006.231.07:20:17.41#ibcon#wrote, iclass 32, count 0 2006.231.07:20:17.41#ibcon#about to read 3, iclass 32, count 0 2006.231.07:20:17.44#ibcon#read 3, iclass 32, count 0 2006.231.07:20:17.44#ibcon#about to read 4, iclass 32, count 0 2006.231.07:20:17.44#ibcon#read 4, iclass 32, count 0 2006.231.07:20:17.44#ibcon#about to read 5, iclass 32, count 0 2006.231.07:20:17.44#ibcon#read 5, iclass 32, count 0 2006.231.07:20:17.44#ibcon#about to read 6, iclass 32, count 0 2006.231.07:20:17.44#ibcon#read 6, iclass 32, count 0 2006.231.07:20:17.44#ibcon#end of sib2, iclass 32, count 0 2006.231.07:20:17.44#ibcon#*after write, iclass 32, count 0 2006.231.07:20:17.44#ibcon#*before return 0, iclass 32, count 0 2006.231.07:20:17.44#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:20:17.44#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:20:17.44#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:20:17.44#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:20:17.44$vc4f8/valo=6,772.99 2006.231.07:20:17.44#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.07:20:17.44#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.07:20:17.44#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:17.44#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:20:17.44#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:20:17.44#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:20:17.44#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:20:17.44#ibcon#first serial, iclass 34, count 0 2006.231.07:20:17.44#ibcon#enter sib2, iclass 34, count 0 2006.231.07:20:17.44#ibcon#flushed, iclass 34, count 0 2006.231.07:20:17.44#ibcon#about to write, iclass 34, count 0 2006.231.07:20:17.44#ibcon#wrote, iclass 34, count 0 2006.231.07:20:17.44#ibcon#about to read 3, iclass 34, count 0 2006.231.07:20:17.46#ibcon#read 3, iclass 34, count 0 2006.231.07:20:17.46#ibcon#about to read 4, iclass 34, count 0 2006.231.07:20:17.46#ibcon#read 4, iclass 34, count 0 2006.231.07:20:17.46#ibcon#about to read 5, iclass 34, count 0 2006.231.07:20:17.46#ibcon#read 5, iclass 34, count 0 2006.231.07:20:17.46#ibcon#about to read 6, iclass 34, count 0 2006.231.07:20:17.46#ibcon#read 6, iclass 34, count 0 2006.231.07:20:17.46#ibcon#end of sib2, iclass 34, count 0 2006.231.07:20:17.46#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:20:17.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:20:17.46#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:20:17.46#ibcon#*before write, iclass 34, count 0 2006.231.07:20:17.46#ibcon#enter sib2, iclass 34, count 0 2006.231.07:20:17.46#ibcon#flushed, iclass 34, count 0 2006.231.07:20:17.46#ibcon#about to write, iclass 34, count 0 2006.231.07:20:17.46#ibcon#wrote, iclass 34, count 0 2006.231.07:20:17.46#ibcon#about to read 3, iclass 34, count 0 2006.231.07:20:17.50#ibcon#read 3, iclass 34, count 0 2006.231.07:20:17.50#ibcon#about to read 4, iclass 34, count 0 2006.231.07:20:17.50#ibcon#read 4, iclass 34, count 0 2006.231.07:20:17.50#ibcon#about to read 5, iclass 34, count 0 2006.231.07:20:17.50#ibcon#read 5, iclass 34, count 0 2006.231.07:20:17.50#ibcon#about to read 6, iclass 34, count 0 2006.231.07:20:17.50#ibcon#read 6, iclass 34, count 0 2006.231.07:20:17.50#ibcon#end of sib2, iclass 34, count 0 2006.231.07:20:17.50#ibcon#*after write, iclass 34, count 0 2006.231.07:20:17.50#ibcon#*before return 0, iclass 34, count 0 2006.231.07:20:17.50#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:20:17.50#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:20:17.50#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:20:17.50#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:20:17.50$vc4f8/va=6,6 2006.231.07:20:17.50#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.07:20:17.50#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.07:20:17.50#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:17.50#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:20:17.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:20:17.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:20:17.56#ibcon#enter wrdev, iclass 36, count 2 2006.231.07:20:17.56#ibcon#first serial, iclass 36, count 2 2006.231.07:20:17.56#ibcon#enter sib2, iclass 36, count 2 2006.231.07:20:17.56#ibcon#flushed, iclass 36, count 2 2006.231.07:20:17.56#ibcon#about to write, iclass 36, count 2 2006.231.07:20:17.56#ibcon#wrote, iclass 36, count 2 2006.231.07:20:17.56#ibcon#about to read 3, iclass 36, count 2 2006.231.07:20:17.58#ibcon#read 3, iclass 36, count 2 2006.231.07:20:17.58#ibcon#about to read 4, iclass 36, count 2 2006.231.07:20:17.58#ibcon#read 4, iclass 36, count 2 2006.231.07:20:17.58#ibcon#about to read 5, iclass 36, count 2 2006.231.07:20:17.58#ibcon#read 5, iclass 36, count 2 2006.231.07:20:17.58#ibcon#about to read 6, iclass 36, count 2 2006.231.07:20:17.58#ibcon#read 6, iclass 36, count 2 2006.231.07:20:17.58#ibcon#end of sib2, iclass 36, count 2 2006.231.07:20:17.58#ibcon#*mode == 0, iclass 36, count 2 2006.231.07:20:17.58#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.07:20:17.58#ibcon#[25=AT06-06\r\n] 2006.231.07:20:17.58#ibcon#*before write, iclass 36, count 2 2006.231.07:20:17.58#ibcon#enter sib2, iclass 36, count 2 2006.231.07:20:17.58#ibcon#flushed, iclass 36, count 2 2006.231.07:20:17.58#ibcon#about to write, iclass 36, count 2 2006.231.07:20:17.58#ibcon#wrote, iclass 36, count 2 2006.231.07:20:17.58#ibcon#about to read 3, iclass 36, count 2 2006.231.07:20:17.61#ibcon#read 3, iclass 36, count 2 2006.231.07:20:17.61#ibcon#about to read 4, iclass 36, count 2 2006.231.07:20:17.61#ibcon#read 4, iclass 36, count 2 2006.231.07:20:17.61#ibcon#about to read 5, iclass 36, count 2 2006.231.07:20:17.61#ibcon#read 5, iclass 36, count 2 2006.231.07:20:17.61#ibcon#about to read 6, iclass 36, count 2 2006.231.07:20:17.61#ibcon#read 6, iclass 36, count 2 2006.231.07:20:17.61#ibcon#end of sib2, iclass 36, count 2 2006.231.07:20:17.61#ibcon#*after write, iclass 36, count 2 2006.231.07:20:17.61#ibcon#*before return 0, iclass 36, count 2 2006.231.07:20:17.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:20:17.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:20:17.61#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.07:20:17.61#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:17.61#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:20:17.73#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:20:17.73#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:20:17.73#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:20:17.73#ibcon#first serial, iclass 36, count 0 2006.231.07:20:17.73#ibcon#enter sib2, iclass 36, count 0 2006.231.07:20:17.73#ibcon#flushed, iclass 36, count 0 2006.231.07:20:17.73#ibcon#about to write, iclass 36, count 0 2006.231.07:20:17.73#ibcon#wrote, iclass 36, count 0 2006.231.07:20:17.73#ibcon#about to read 3, iclass 36, count 0 2006.231.07:20:17.75#ibcon#read 3, iclass 36, count 0 2006.231.07:20:17.75#ibcon#about to read 4, iclass 36, count 0 2006.231.07:20:17.75#ibcon#read 4, iclass 36, count 0 2006.231.07:20:17.75#ibcon#about to read 5, iclass 36, count 0 2006.231.07:20:17.75#ibcon#read 5, iclass 36, count 0 2006.231.07:20:17.75#ibcon#about to read 6, iclass 36, count 0 2006.231.07:20:17.75#ibcon#read 6, iclass 36, count 0 2006.231.07:20:17.75#ibcon#end of sib2, iclass 36, count 0 2006.231.07:20:17.75#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:20:17.75#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:20:17.75#ibcon#[25=USB\r\n] 2006.231.07:20:17.75#ibcon#*before write, iclass 36, count 0 2006.231.07:20:17.75#ibcon#enter sib2, iclass 36, count 0 2006.231.07:20:17.75#ibcon#flushed, iclass 36, count 0 2006.231.07:20:17.75#ibcon#about to write, iclass 36, count 0 2006.231.07:20:17.75#ibcon#wrote, iclass 36, count 0 2006.231.07:20:17.75#ibcon#about to read 3, iclass 36, count 0 2006.231.07:20:17.78#ibcon#read 3, iclass 36, count 0 2006.231.07:20:17.78#ibcon#about to read 4, iclass 36, count 0 2006.231.07:20:17.78#ibcon#read 4, iclass 36, count 0 2006.231.07:20:17.78#ibcon#about to read 5, iclass 36, count 0 2006.231.07:20:17.78#ibcon#read 5, iclass 36, count 0 2006.231.07:20:17.78#ibcon#about to read 6, iclass 36, count 0 2006.231.07:20:17.78#ibcon#read 6, iclass 36, count 0 2006.231.07:20:17.78#ibcon#end of sib2, iclass 36, count 0 2006.231.07:20:17.78#ibcon#*after write, iclass 36, count 0 2006.231.07:20:17.78#ibcon#*before return 0, iclass 36, count 0 2006.231.07:20:17.78#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:20:17.78#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:20:17.78#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:20:17.78#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:20:17.78$vc4f8/valo=7,832.99 2006.231.07:20:17.78#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.07:20:17.78#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.07:20:17.78#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:17.78#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:20:17.78#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:20:17.78#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:20:17.78#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:20:17.78#ibcon#first serial, iclass 38, count 0 2006.231.07:20:17.78#ibcon#enter sib2, iclass 38, count 0 2006.231.07:20:17.78#ibcon#flushed, iclass 38, count 0 2006.231.07:20:17.78#ibcon#about to write, iclass 38, count 0 2006.231.07:20:17.78#ibcon#wrote, iclass 38, count 0 2006.231.07:20:17.78#ibcon#about to read 3, iclass 38, count 0 2006.231.07:20:17.80#ibcon#read 3, iclass 38, count 0 2006.231.07:20:17.80#ibcon#about to read 4, iclass 38, count 0 2006.231.07:20:17.80#ibcon#read 4, iclass 38, count 0 2006.231.07:20:17.80#ibcon#about to read 5, iclass 38, count 0 2006.231.07:20:17.80#ibcon#read 5, iclass 38, count 0 2006.231.07:20:17.80#ibcon#about to read 6, iclass 38, count 0 2006.231.07:20:17.80#ibcon#read 6, iclass 38, count 0 2006.231.07:20:17.80#ibcon#end of sib2, iclass 38, count 0 2006.231.07:20:17.80#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:20:17.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:20:17.80#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:20:17.80#ibcon#*before write, iclass 38, count 0 2006.231.07:20:17.80#ibcon#enter sib2, iclass 38, count 0 2006.231.07:20:17.80#ibcon#flushed, iclass 38, count 0 2006.231.07:20:17.80#ibcon#about to write, iclass 38, count 0 2006.231.07:20:17.80#ibcon#wrote, iclass 38, count 0 2006.231.07:20:17.80#ibcon#about to read 3, iclass 38, count 0 2006.231.07:20:17.84#ibcon#read 3, iclass 38, count 0 2006.231.07:20:17.84#ibcon#about to read 4, iclass 38, count 0 2006.231.07:20:17.84#ibcon#read 4, iclass 38, count 0 2006.231.07:20:17.84#ibcon#about to read 5, iclass 38, count 0 2006.231.07:20:17.84#ibcon#read 5, iclass 38, count 0 2006.231.07:20:17.84#ibcon#about to read 6, iclass 38, count 0 2006.231.07:20:17.84#ibcon#read 6, iclass 38, count 0 2006.231.07:20:17.84#ibcon#end of sib2, iclass 38, count 0 2006.231.07:20:17.84#ibcon#*after write, iclass 38, count 0 2006.231.07:20:17.84#ibcon#*before return 0, iclass 38, count 0 2006.231.07:20:17.84#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:20:17.84#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:20:17.84#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:20:17.84#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:20:17.84$vc4f8/va=7,6 2006.231.07:20:17.84#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.07:20:17.84#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.07:20:17.84#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:17.84#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:20:17.90#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:20:17.90#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:20:17.90#ibcon#enter wrdev, iclass 40, count 2 2006.231.07:20:17.90#ibcon#first serial, iclass 40, count 2 2006.231.07:20:17.90#ibcon#enter sib2, iclass 40, count 2 2006.231.07:20:17.90#ibcon#flushed, iclass 40, count 2 2006.231.07:20:17.90#ibcon#about to write, iclass 40, count 2 2006.231.07:20:17.90#ibcon#wrote, iclass 40, count 2 2006.231.07:20:17.90#ibcon#about to read 3, iclass 40, count 2 2006.231.07:20:17.92#ibcon#read 3, iclass 40, count 2 2006.231.07:20:17.92#ibcon#about to read 4, iclass 40, count 2 2006.231.07:20:17.92#ibcon#read 4, iclass 40, count 2 2006.231.07:20:17.92#ibcon#about to read 5, iclass 40, count 2 2006.231.07:20:17.92#ibcon#read 5, iclass 40, count 2 2006.231.07:20:17.92#ibcon#about to read 6, iclass 40, count 2 2006.231.07:20:17.92#ibcon#read 6, iclass 40, count 2 2006.231.07:20:17.92#ibcon#end of sib2, iclass 40, count 2 2006.231.07:20:17.92#ibcon#*mode == 0, iclass 40, count 2 2006.231.07:20:17.92#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.07:20:17.92#ibcon#[25=AT07-06\r\n] 2006.231.07:20:17.92#ibcon#*before write, iclass 40, count 2 2006.231.07:20:17.92#ibcon#enter sib2, iclass 40, count 2 2006.231.07:20:17.92#ibcon#flushed, iclass 40, count 2 2006.231.07:20:17.92#ibcon#about to write, iclass 40, count 2 2006.231.07:20:17.92#ibcon#wrote, iclass 40, count 2 2006.231.07:20:17.92#ibcon#about to read 3, iclass 40, count 2 2006.231.07:20:17.95#ibcon#read 3, iclass 40, count 2 2006.231.07:20:17.95#ibcon#about to read 4, iclass 40, count 2 2006.231.07:20:17.95#ibcon#read 4, iclass 40, count 2 2006.231.07:20:17.95#ibcon#about to read 5, iclass 40, count 2 2006.231.07:20:17.95#ibcon#read 5, iclass 40, count 2 2006.231.07:20:17.95#ibcon#about to read 6, iclass 40, count 2 2006.231.07:20:17.95#ibcon#read 6, iclass 40, count 2 2006.231.07:20:17.95#ibcon#end of sib2, iclass 40, count 2 2006.231.07:20:17.95#ibcon#*after write, iclass 40, count 2 2006.231.07:20:17.95#ibcon#*before return 0, iclass 40, count 2 2006.231.07:20:17.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:20:17.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:20:17.95#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.07:20:17.95#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:17.95#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:20:18.07#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:20:18.07#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:20:18.07#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:20:18.07#ibcon#first serial, iclass 40, count 0 2006.231.07:20:18.07#ibcon#enter sib2, iclass 40, count 0 2006.231.07:20:18.07#ibcon#flushed, iclass 40, count 0 2006.231.07:20:18.07#ibcon#about to write, iclass 40, count 0 2006.231.07:20:18.07#ibcon#wrote, iclass 40, count 0 2006.231.07:20:18.07#ibcon#about to read 3, iclass 40, count 0 2006.231.07:20:18.09#ibcon#read 3, iclass 40, count 0 2006.231.07:20:18.09#ibcon#about to read 4, iclass 40, count 0 2006.231.07:20:18.09#ibcon#read 4, iclass 40, count 0 2006.231.07:20:18.09#ibcon#about to read 5, iclass 40, count 0 2006.231.07:20:18.09#ibcon#read 5, iclass 40, count 0 2006.231.07:20:18.09#ibcon#about to read 6, iclass 40, count 0 2006.231.07:20:18.09#ibcon#read 6, iclass 40, count 0 2006.231.07:20:18.09#ibcon#end of sib2, iclass 40, count 0 2006.231.07:20:18.09#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:20:18.09#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:20:18.09#ibcon#[25=USB\r\n] 2006.231.07:20:18.09#ibcon#*before write, iclass 40, count 0 2006.231.07:20:18.09#ibcon#enter sib2, iclass 40, count 0 2006.231.07:20:18.09#ibcon#flushed, iclass 40, count 0 2006.231.07:20:18.09#ibcon#about to write, iclass 40, count 0 2006.231.07:20:18.09#ibcon#wrote, iclass 40, count 0 2006.231.07:20:18.09#ibcon#about to read 3, iclass 40, count 0 2006.231.07:20:18.12#ibcon#read 3, iclass 40, count 0 2006.231.07:20:18.12#ibcon#about to read 4, iclass 40, count 0 2006.231.07:20:18.12#ibcon#read 4, iclass 40, count 0 2006.231.07:20:18.12#ibcon#about to read 5, iclass 40, count 0 2006.231.07:20:18.12#ibcon#read 5, iclass 40, count 0 2006.231.07:20:18.12#ibcon#about to read 6, iclass 40, count 0 2006.231.07:20:18.12#ibcon#read 6, iclass 40, count 0 2006.231.07:20:18.12#ibcon#end of sib2, iclass 40, count 0 2006.231.07:20:18.12#ibcon#*after write, iclass 40, count 0 2006.231.07:20:18.12#ibcon#*before return 0, iclass 40, count 0 2006.231.07:20:18.12#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:20:18.12#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:20:18.12#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:20:18.12#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:20:18.12$vc4f8/valo=8,852.99 2006.231.07:20:18.12#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.07:20:18.12#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.07:20:18.12#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:18.12#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:20:18.12#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:20:18.12#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:20:18.12#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:20:18.12#ibcon#first serial, iclass 4, count 0 2006.231.07:20:18.12#ibcon#enter sib2, iclass 4, count 0 2006.231.07:20:18.12#ibcon#flushed, iclass 4, count 0 2006.231.07:20:18.12#ibcon#about to write, iclass 4, count 0 2006.231.07:20:18.12#ibcon#wrote, iclass 4, count 0 2006.231.07:20:18.12#ibcon#about to read 3, iclass 4, count 0 2006.231.07:20:18.14#ibcon#read 3, iclass 4, count 0 2006.231.07:20:18.14#ibcon#about to read 4, iclass 4, count 0 2006.231.07:20:18.14#ibcon#read 4, iclass 4, count 0 2006.231.07:20:18.14#ibcon#about to read 5, iclass 4, count 0 2006.231.07:20:18.14#ibcon#read 5, iclass 4, count 0 2006.231.07:20:18.14#ibcon#about to read 6, iclass 4, count 0 2006.231.07:20:18.14#ibcon#read 6, iclass 4, count 0 2006.231.07:20:18.14#ibcon#end of sib2, iclass 4, count 0 2006.231.07:20:18.14#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:20:18.14#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:20:18.14#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:20:18.14#ibcon#*before write, iclass 4, count 0 2006.231.07:20:18.14#ibcon#enter sib2, iclass 4, count 0 2006.231.07:20:18.14#ibcon#flushed, iclass 4, count 0 2006.231.07:20:18.14#ibcon#about to write, iclass 4, count 0 2006.231.07:20:18.14#ibcon#wrote, iclass 4, count 0 2006.231.07:20:18.14#ibcon#about to read 3, iclass 4, count 0 2006.231.07:20:18.18#ibcon#read 3, iclass 4, count 0 2006.231.07:20:18.18#ibcon#about to read 4, iclass 4, count 0 2006.231.07:20:18.18#ibcon#read 4, iclass 4, count 0 2006.231.07:20:18.18#ibcon#about to read 5, iclass 4, count 0 2006.231.07:20:18.18#ibcon#read 5, iclass 4, count 0 2006.231.07:20:18.18#ibcon#about to read 6, iclass 4, count 0 2006.231.07:20:18.18#ibcon#read 6, iclass 4, count 0 2006.231.07:20:18.18#ibcon#end of sib2, iclass 4, count 0 2006.231.07:20:18.18#ibcon#*after write, iclass 4, count 0 2006.231.07:20:18.18#ibcon#*before return 0, iclass 4, count 0 2006.231.07:20:18.18#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:20:18.18#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:20:18.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:20:18.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:20:18.18$vc4f8/va=8,6 2006.231.07:20:18.18#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.07:20:18.18#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.07:20:18.18#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:18.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:20:18.24#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:20:18.24#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:20:18.24#ibcon#enter wrdev, iclass 6, count 2 2006.231.07:20:18.24#ibcon#first serial, iclass 6, count 2 2006.231.07:20:18.24#ibcon#enter sib2, iclass 6, count 2 2006.231.07:20:18.24#ibcon#flushed, iclass 6, count 2 2006.231.07:20:18.24#ibcon#about to write, iclass 6, count 2 2006.231.07:20:18.24#ibcon#wrote, iclass 6, count 2 2006.231.07:20:18.24#ibcon#about to read 3, iclass 6, count 2 2006.231.07:20:18.26#ibcon#read 3, iclass 6, count 2 2006.231.07:20:18.26#ibcon#about to read 4, iclass 6, count 2 2006.231.07:20:18.26#ibcon#read 4, iclass 6, count 2 2006.231.07:20:18.26#ibcon#about to read 5, iclass 6, count 2 2006.231.07:20:18.26#ibcon#read 5, iclass 6, count 2 2006.231.07:20:18.26#ibcon#about to read 6, iclass 6, count 2 2006.231.07:20:18.26#ibcon#read 6, iclass 6, count 2 2006.231.07:20:18.26#ibcon#end of sib2, iclass 6, count 2 2006.231.07:20:18.26#ibcon#*mode == 0, iclass 6, count 2 2006.231.07:20:18.26#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.07:20:18.26#ibcon#[25=AT08-06\r\n] 2006.231.07:20:18.26#ibcon#*before write, iclass 6, count 2 2006.231.07:20:18.26#ibcon#enter sib2, iclass 6, count 2 2006.231.07:20:18.26#ibcon#flushed, iclass 6, count 2 2006.231.07:20:18.26#ibcon#about to write, iclass 6, count 2 2006.231.07:20:18.26#ibcon#wrote, iclass 6, count 2 2006.231.07:20:18.26#ibcon#about to read 3, iclass 6, count 2 2006.231.07:20:18.29#ibcon#read 3, iclass 6, count 2 2006.231.07:20:18.29#ibcon#about to read 4, iclass 6, count 2 2006.231.07:20:18.29#ibcon#read 4, iclass 6, count 2 2006.231.07:20:18.29#ibcon#about to read 5, iclass 6, count 2 2006.231.07:20:18.29#ibcon#read 5, iclass 6, count 2 2006.231.07:20:18.29#ibcon#about to read 6, iclass 6, count 2 2006.231.07:20:18.29#ibcon#read 6, iclass 6, count 2 2006.231.07:20:18.29#ibcon#end of sib2, iclass 6, count 2 2006.231.07:20:18.29#ibcon#*after write, iclass 6, count 2 2006.231.07:20:18.29#ibcon#*before return 0, iclass 6, count 2 2006.231.07:20:18.29#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:20:18.29#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:20:18.29#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.07:20:18.29#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:18.29#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:20:18.41#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:20:18.41#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:20:18.41#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:20:18.41#ibcon#first serial, iclass 6, count 0 2006.231.07:20:18.41#ibcon#enter sib2, iclass 6, count 0 2006.231.07:20:18.41#ibcon#flushed, iclass 6, count 0 2006.231.07:20:18.41#ibcon#about to write, iclass 6, count 0 2006.231.07:20:18.41#ibcon#wrote, iclass 6, count 0 2006.231.07:20:18.41#ibcon#about to read 3, iclass 6, count 0 2006.231.07:20:18.43#ibcon#read 3, iclass 6, count 0 2006.231.07:20:18.43#ibcon#about to read 4, iclass 6, count 0 2006.231.07:20:18.43#ibcon#read 4, iclass 6, count 0 2006.231.07:20:18.43#ibcon#about to read 5, iclass 6, count 0 2006.231.07:20:18.43#ibcon#read 5, iclass 6, count 0 2006.231.07:20:18.43#ibcon#about to read 6, iclass 6, count 0 2006.231.07:20:18.43#ibcon#read 6, iclass 6, count 0 2006.231.07:20:18.43#ibcon#end of sib2, iclass 6, count 0 2006.231.07:20:18.43#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:20:18.43#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:20:18.43#ibcon#[25=USB\r\n] 2006.231.07:20:18.43#ibcon#*before write, iclass 6, count 0 2006.231.07:20:18.43#ibcon#enter sib2, iclass 6, count 0 2006.231.07:20:18.43#ibcon#flushed, iclass 6, count 0 2006.231.07:20:18.43#ibcon#about to write, iclass 6, count 0 2006.231.07:20:18.43#ibcon#wrote, iclass 6, count 0 2006.231.07:20:18.43#ibcon#about to read 3, iclass 6, count 0 2006.231.07:20:18.46#ibcon#read 3, iclass 6, count 0 2006.231.07:20:18.46#ibcon#about to read 4, iclass 6, count 0 2006.231.07:20:18.46#ibcon#read 4, iclass 6, count 0 2006.231.07:20:18.46#ibcon#about to read 5, iclass 6, count 0 2006.231.07:20:18.46#ibcon#read 5, iclass 6, count 0 2006.231.07:20:18.46#ibcon#about to read 6, iclass 6, count 0 2006.231.07:20:18.46#ibcon#read 6, iclass 6, count 0 2006.231.07:20:18.46#ibcon#end of sib2, iclass 6, count 0 2006.231.07:20:18.46#ibcon#*after write, iclass 6, count 0 2006.231.07:20:18.46#ibcon#*before return 0, iclass 6, count 0 2006.231.07:20:18.46#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:20:18.46#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:20:18.46#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:20:18.46#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:20:18.46$vc4f8/vblo=1,632.99 2006.231.07:20:18.46#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.07:20:18.46#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.07:20:18.46#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:18.46#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:20:18.46#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:20:18.46#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:20:18.46#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:20:18.46#ibcon#first serial, iclass 10, count 0 2006.231.07:20:18.46#ibcon#enter sib2, iclass 10, count 0 2006.231.07:20:18.46#ibcon#flushed, iclass 10, count 0 2006.231.07:20:18.46#ibcon#about to write, iclass 10, count 0 2006.231.07:20:18.46#ibcon#wrote, iclass 10, count 0 2006.231.07:20:18.46#ibcon#about to read 3, iclass 10, count 0 2006.231.07:20:18.48#ibcon#read 3, iclass 10, count 0 2006.231.07:20:18.48#ibcon#about to read 4, iclass 10, count 0 2006.231.07:20:18.48#ibcon#read 4, iclass 10, count 0 2006.231.07:20:18.48#ibcon#about to read 5, iclass 10, count 0 2006.231.07:20:18.48#ibcon#read 5, iclass 10, count 0 2006.231.07:20:18.48#ibcon#about to read 6, iclass 10, count 0 2006.231.07:20:18.48#ibcon#read 6, iclass 10, count 0 2006.231.07:20:18.48#ibcon#end of sib2, iclass 10, count 0 2006.231.07:20:18.48#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:20:18.48#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:20:18.48#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:20:18.48#ibcon#*before write, iclass 10, count 0 2006.231.07:20:18.48#ibcon#enter sib2, iclass 10, count 0 2006.231.07:20:18.48#ibcon#flushed, iclass 10, count 0 2006.231.07:20:18.48#ibcon#about to write, iclass 10, count 0 2006.231.07:20:18.48#ibcon#wrote, iclass 10, count 0 2006.231.07:20:18.48#ibcon#about to read 3, iclass 10, count 0 2006.231.07:20:18.54#ibcon#read 3, iclass 10, count 0 2006.231.07:20:18.54#ibcon#about to read 4, iclass 10, count 0 2006.231.07:20:18.54#ibcon#read 4, iclass 10, count 0 2006.231.07:20:18.54#ibcon#about to read 5, iclass 10, count 0 2006.231.07:20:18.54#ibcon#read 5, iclass 10, count 0 2006.231.07:20:18.54#ibcon#about to read 6, iclass 10, count 0 2006.231.07:20:18.54#ibcon#read 6, iclass 10, count 0 2006.231.07:20:18.54#ibcon#end of sib2, iclass 10, count 0 2006.231.07:20:18.54#ibcon#*after write, iclass 10, count 0 2006.231.07:20:18.54#ibcon#*before return 0, iclass 10, count 0 2006.231.07:20:18.54#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:20:18.54#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:20:18.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:20:18.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:20:18.54$vc4f8/vb=1,4 2006.231.07:20:18.54#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.07:20:18.54#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.07:20:18.54#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:18.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:20:18.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:20:18.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:20:18.54#ibcon#enter wrdev, iclass 12, count 2 2006.231.07:20:18.54#ibcon#first serial, iclass 12, count 2 2006.231.07:20:18.54#ibcon#enter sib2, iclass 12, count 2 2006.231.07:20:18.54#ibcon#flushed, iclass 12, count 2 2006.231.07:20:18.54#ibcon#about to write, iclass 12, count 2 2006.231.07:20:18.54#ibcon#wrote, iclass 12, count 2 2006.231.07:20:18.54#ibcon#about to read 3, iclass 12, count 2 2006.231.07:20:18.56#ibcon#read 3, iclass 12, count 2 2006.231.07:20:18.56#ibcon#about to read 4, iclass 12, count 2 2006.231.07:20:18.56#ibcon#read 4, iclass 12, count 2 2006.231.07:20:18.56#ibcon#about to read 5, iclass 12, count 2 2006.231.07:20:18.56#ibcon#read 5, iclass 12, count 2 2006.231.07:20:18.56#ibcon#about to read 6, iclass 12, count 2 2006.231.07:20:18.56#ibcon#read 6, iclass 12, count 2 2006.231.07:20:18.56#ibcon#end of sib2, iclass 12, count 2 2006.231.07:20:18.56#ibcon#*mode == 0, iclass 12, count 2 2006.231.07:20:18.56#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.07:20:18.56#ibcon#[27=AT01-04\r\n] 2006.231.07:20:18.56#ibcon#*before write, iclass 12, count 2 2006.231.07:20:18.56#ibcon#enter sib2, iclass 12, count 2 2006.231.07:20:18.56#ibcon#flushed, iclass 12, count 2 2006.231.07:20:18.56#ibcon#about to write, iclass 12, count 2 2006.231.07:20:18.56#ibcon#wrote, iclass 12, count 2 2006.231.07:20:18.56#ibcon#about to read 3, iclass 12, count 2 2006.231.07:20:18.60#ibcon#read 3, iclass 12, count 2 2006.231.07:20:18.60#ibcon#about to read 4, iclass 12, count 2 2006.231.07:20:18.60#ibcon#read 4, iclass 12, count 2 2006.231.07:20:18.60#ibcon#about to read 5, iclass 12, count 2 2006.231.07:20:18.60#ibcon#read 5, iclass 12, count 2 2006.231.07:20:18.60#ibcon#about to read 6, iclass 12, count 2 2006.231.07:20:18.60#ibcon#read 6, iclass 12, count 2 2006.231.07:20:18.60#ibcon#end of sib2, iclass 12, count 2 2006.231.07:20:18.60#ibcon#*after write, iclass 12, count 2 2006.231.07:20:18.60#ibcon#*before return 0, iclass 12, count 2 2006.231.07:20:18.60#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:20:18.60#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:20:18.60#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.07:20:18.60#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:18.60#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:20:18.72#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:20:18.72#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:20:18.72#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:20:18.72#ibcon#first serial, iclass 12, count 0 2006.231.07:20:18.72#ibcon#enter sib2, iclass 12, count 0 2006.231.07:20:18.72#ibcon#flushed, iclass 12, count 0 2006.231.07:20:18.72#ibcon#about to write, iclass 12, count 0 2006.231.07:20:18.72#ibcon#wrote, iclass 12, count 0 2006.231.07:20:18.72#ibcon#about to read 3, iclass 12, count 0 2006.231.07:20:18.74#ibcon#read 3, iclass 12, count 0 2006.231.07:20:18.74#ibcon#about to read 4, iclass 12, count 0 2006.231.07:20:18.74#ibcon#read 4, iclass 12, count 0 2006.231.07:20:18.74#ibcon#about to read 5, iclass 12, count 0 2006.231.07:20:18.74#ibcon#read 5, iclass 12, count 0 2006.231.07:20:18.74#ibcon#about to read 6, iclass 12, count 0 2006.231.07:20:18.74#ibcon#read 6, iclass 12, count 0 2006.231.07:20:18.74#ibcon#end of sib2, iclass 12, count 0 2006.231.07:20:18.74#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:20:18.74#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:20:18.74#ibcon#[27=USB\r\n] 2006.231.07:20:18.74#ibcon#*before write, iclass 12, count 0 2006.231.07:20:18.74#ibcon#enter sib2, iclass 12, count 0 2006.231.07:20:18.74#ibcon#flushed, iclass 12, count 0 2006.231.07:20:18.74#ibcon#about to write, iclass 12, count 0 2006.231.07:20:18.74#ibcon#wrote, iclass 12, count 0 2006.231.07:20:18.74#ibcon#about to read 3, iclass 12, count 0 2006.231.07:20:18.77#ibcon#read 3, iclass 12, count 0 2006.231.07:20:18.77#ibcon#about to read 4, iclass 12, count 0 2006.231.07:20:18.77#ibcon#read 4, iclass 12, count 0 2006.231.07:20:18.77#ibcon#about to read 5, iclass 12, count 0 2006.231.07:20:18.77#ibcon#read 5, iclass 12, count 0 2006.231.07:20:18.77#ibcon#about to read 6, iclass 12, count 0 2006.231.07:20:18.77#ibcon#read 6, iclass 12, count 0 2006.231.07:20:18.77#ibcon#end of sib2, iclass 12, count 0 2006.231.07:20:18.77#ibcon#*after write, iclass 12, count 0 2006.231.07:20:18.77#ibcon#*before return 0, iclass 12, count 0 2006.231.07:20:18.77#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:20:18.77#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:20:18.77#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:20:18.77#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:20:18.77$vc4f8/vblo=2,640.99 2006.231.07:20:18.77#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.07:20:18.77#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.07:20:18.77#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:18.77#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:20:18.77#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:20:18.77#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:20:18.77#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:20:18.77#ibcon#first serial, iclass 14, count 0 2006.231.07:20:18.77#ibcon#enter sib2, iclass 14, count 0 2006.231.07:20:18.77#ibcon#flushed, iclass 14, count 0 2006.231.07:20:18.77#ibcon#about to write, iclass 14, count 0 2006.231.07:20:18.77#ibcon#wrote, iclass 14, count 0 2006.231.07:20:18.77#ibcon#about to read 3, iclass 14, count 0 2006.231.07:20:18.79#ibcon#read 3, iclass 14, count 0 2006.231.07:20:18.79#ibcon#about to read 4, iclass 14, count 0 2006.231.07:20:18.79#ibcon#read 4, iclass 14, count 0 2006.231.07:20:18.79#ibcon#about to read 5, iclass 14, count 0 2006.231.07:20:18.79#ibcon#read 5, iclass 14, count 0 2006.231.07:20:18.79#ibcon#about to read 6, iclass 14, count 0 2006.231.07:20:18.79#ibcon#read 6, iclass 14, count 0 2006.231.07:20:18.79#ibcon#end of sib2, iclass 14, count 0 2006.231.07:20:18.79#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:20:18.79#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:20:18.79#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:20:18.79#ibcon#*before write, iclass 14, count 0 2006.231.07:20:18.79#ibcon#enter sib2, iclass 14, count 0 2006.231.07:20:18.79#ibcon#flushed, iclass 14, count 0 2006.231.07:20:18.79#ibcon#about to write, iclass 14, count 0 2006.231.07:20:18.79#ibcon#wrote, iclass 14, count 0 2006.231.07:20:18.79#ibcon#about to read 3, iclass 14, count 0 2006.231.07:20:18.83#ibcon#read 3, iclass 14, count 0 2006.231.07:20:18.83#ibcon#about to read 4, iclass 14, count 0 2006.231.07:20:18.83#ibcon#read 4, iclass 14, count 0 2006.231.07:20:18.83#ibcon#about to read 5, iclass 14, count 0 2006.231.07:20:18.83#ibcon#read 5, iclass 14, count 0 2006.231.07:20:18.83#ibcon#about to read 6, iclass 14, count 0 2006.231.07:20:18.83#ibcon#read 6, iclass 14, count 0 2006.231.07:20:18.83#ibcon#end of sib2, iclass 14, count 0 2006.231.07:20:18.83#ibcon#*after write, iclass 14, count 0 2006.231.07:20:18.83#ibcon#*before return 0, iclass 14, count 0 2006.231.07:20:18.83#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:20:18.83#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:20:18.83#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:20:18.83#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:20:18.83$vc4f8/vb=2,4 2006.231.07:20:18.83#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.07:20:18.83#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.07:20:18.83#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:18.83#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:20:18.89#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:20:18.89#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:20:18.89#ibcon#enter wrdev, iclass 16, count 2 2006.231.07:20:18.89#ibcon#first serial, iclass 16, count 2 2006.231.07:20:18.89#ibcon#enter sib2, iclass 16, count 2 2006.231.07:20:18.89#ibcon#flushed, iclass 16, count 2 2006.231.07:20:18.89#ibcon#about to write, iclass 16, count 2 2006.231.07:20:18.89#ibcon#wrote, iclass 16, count 2 2006.231.07:20:18.89#ibcon#about to read 3, iclass 16, count 2 2006.231.07:20:18.91#ibcon#read 3, iclass 16, count 2 2006.231.07:20:18.91#ibcon#about to read 4, iclass 16, count 2 2006.231.07:20:18.91#ibcon#read 4, iclass 16, count 2 2006.231.07:20:18.91#ibcon#about to read 5, iclass 16, count 2 2006.231.07:20:18.91#ibcon#read 5, iclass 16, count 2 2006.231.07:20:18.91#ibcon#about to read 6, iclass 16, count 2 2006.231.07:20:18.91#ibcon#read 6, iclass 16, count 2 2006.231.07:20:18.91#ibcon#end of sib2, iclass 16, count 2 2006.231.07:20:18.91#ibcon#*mode == 0, iclass 16, count 2 2006.231.07:20:18.91#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.07:20:18.91#ibcon#[27=AT02-04\r\n] 2006.231.07:20:18.91#ibcon#*before write, iclass 16, count 2 2006.231.07:20:18.91#ibcon#enter sib2, iclass 16, count 2 2006.231.07:20:18.91#ibcon#flushed, iclass 16, count 2 2006.231.07:20:18.91#ibcon#about to write, iclass 16, count 2 2006.231.07:20:18.91#ibcon#wrote, iclass 16, count 2 2006.231.07:20:18.91#ibcon#about to read 3, iclass 16, count 2 2006.231.07:20:18.94#ibcon#read 3, iclass 16, count 2 2006.231.07:20:18.94#ibcon#about to read 4, iclass 16, count 2 2006.231.07:20:18.94#ibcon#read 4, iclass 16, count 2 2006.231.07:20:18.94#ibcon#about to read 5, iclass 16, count 2 2006.231.07:20:18.94#ibcon#read 5, iclass 16, count 2 2006.231.07:20:18.94#ibcon#about to read 6, iclass 16, count 2 2006.231.07:20:18.94#ibcon#read 6, iclass 16, count 2 2006.231.07:20:18.94#ibcon#end of sib2, iclass 16, count 2 2006.231.07:20:18.94#ibcon#*after write, iclass 16, count 2 2006.231.07:20:18.94#ibcon#*before return 0, iclass 16, count 2 2006.231.07:20:18.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:20:18.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:20:18.94#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.07:20:18.94#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:18.94#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:20:19.06#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:20:19.06#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:20:19.06#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:20:19.06#ibcon#first serial, iclass 16, count 0 2006.231.07:20:19.06#ibcon#enter sib2, iclass 16, count 0 2006.231.07:20:19.06#ibcon#flushed, iclass 16, count 0 2006.231.07:20:19.06#ibcon#about to write, iclass 16, count 0 2006.231.07:20:19.06#ibcon#wrote, iclass 16, count 0 2006.231.07:20:19.06#ibcon#about to read 3, iclass 16, count 0 2006.231.07:20:19.08#ibcon#read 3, iclass 16, count 0 2006.231.07:20:19.08#ibcon#about to read 4, iclass 16, count 0 2006.231.07:20:19.08#ibcon#read 4, iclass 16, count 0 2006.231.07:20:19.08#ibcon#about to read 5, iclass 16, count 0 2006.231.07:20:19.08#ibcon#read 5, iclass 16, count 0 2006.231.07:20:19.08#ibcon#about to read 6, iclass 16, count 0 2006.231.07:20:19.08#ibcon#read 6, iclass 16, count 0 2006.231.07:20:19.08#ibcon#end of sib2, iclass 16, count 0 2006.231.07:20:19.08#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:20:19.08#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:20:19.08#ibcon#[27=USB\r\n] 2006.231.07:20:19.08#ibcon#*before write, iclass 16, count 0 2006.231.07:20:19.08#ibcon#enter sib2, iclass 16, count 0 2006.231.07:20:19.08#ibcon#flushed, iclass 16, count 0 2006.231.07:20:19.08#ibcon#about to write, iclass 16, count 0 2006.231.07:20:19.08#ibcon#wrote, iclass 16, count 0 2006.231.07:20:19.08#ibcon#about to read 3, iclass 16, count 0 2006.231.07:20:19.11#ibcon#read 3, iclass 16, count 0 2006.231.07:20:19.11#ibcon#about to read 4, iclass 16, count 0 2006.231.07:20:19.11#ibcon#read 4, iclass 16, count 0 2006.231.07:20:19.11#ibcon#about to read 5, iclass 16, count 0 2006.231.07:20:19.11#ibcon#read 5, iclass 16, count 0 2006.231.07:20:19.11#ibcon#about to read 6, iclass 16, count 0 2006.231.07:20:19.11#ibcon#read 6, iclass 16, count 0 2006.231.07:20:19.11#ibcon#end of sib2, iclass 16, count 0 2006.231.07:20:19.11#ibcon#*after write, iclass 16, count 0 2006.231.07:20:19.11#ibcon#*before return 0, iclass 16, count 0 2006.231.07:20:19.11#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:20:19.11#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:20:19.11#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:20:19.11#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:20:19.11$vc4f8/vblo=3,656.99 2006.231.07:20:19.11#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.07:20:19.11#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.07:20:19.11#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:19.11#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:20:19.11#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:20:19.11#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:20:19.11#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:20:19.11#ibcon#first serial, iclass 18, count 0 2006.231.07:20:19.11#ibcon#enter sib2, iclass 18, count 0 2006.231.07:20:19.11#ibcon#flushed, iclass 18, count 0 2006.231.07:20:19.11#ibcon#about to write, iclass 18, count 0 2006.231.07:20:19.11#ibcon#wrote, iclass 18, count 0 2006.231.07:20:19.11#ibcon#about to read 3, iclass 18, count 0 2006.231.07:20:19.13#ibcon#read 3, iclass 18, count 0 2006.231.07:20:19.13#ibcon#about to read 4, iclass 18, count 0 2006.231.07:20:19.13#ibcon#read 4, iclass 18, count 0 2006.231.07:20:19.13#ibcon#about to read 5, iclass 18, count 0 2006.231.07:20:19.13#ibcon#read 5, iclass 18, count 0 2006.231.07:20:19.13#ibcon#about to read 6, iclass 18, count 0 2006.231.07:20:19.13#ibcon#read 6, iclass 18, count 0 2006.231.07:20:19.13#ibcon#end of sib2, iclass 18, count 0 2006.231.07:20:19.13#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:20:19.13#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:20:19.13#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:20:19.13#ibcon#*before write, iclass 18, count 0 2006.231.07:20:19.13#ibcon#enter sib2, iclass 18, count 0 2006.231.07:20:19.13#ibcon#flushed, iclass 18, count 0 2006.231.07:20:19.13#ibcon#about to write, iclass 18, count 0 2006.231.07:20:19.13#ibcon#wrote, iclass 18, count 0 2006.231.07:20:19.13#ibcon#about to read 3, iclass 18, count 0 2006.231.07:20:19.17#ibcon#read 3, iclass 18, count 0 2006.231.07:20:19.17#ibcon#about to read 4, iclass 18, count 0 2006.231.07:20:19.17#ibcon#read 4, iclass 18, count 0 2006.231.07:20:19.17#ibcon#about to read 5, iclass 18, count 0 2006.231.07:20:19.17#ibcon#read 5, iclass 18, count 0 2006.231.07:20:19.17#ibcon#about to read 6, iclass 18, count 0 2006.231.07:20:19.17#ibcon#read 6, iclass 18, count 0 2006.231.07:20:19.17#ibcon#end of sib2, iclass 18, count 0 2006.231.07:20:19.17#ibcon#*after write, iclass 18, count 0 2006.231.07:20:19.17#ibcon#*before return 0, iclass 18, count 0 2006.231.07:20:19.17#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:20:19.17#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:20:19.17#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:20:19.17#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:20:19.17$vc4f8/vb=3,4 2006.231.07:20:19.17#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.07:20:19.17#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.07:20:19.17#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:19.17#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:20:19.23#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:20:19.23#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:20:19.23#ibcon#enter wrdev, iclass 20, count 2 2006.231.07:20:19.23#ibcon#first serial, iclass 20, count 2 2006.231.07:20:19.23#ibcon#enter sib2, iclass 20, count 2 2006.231.07:20:19.23#ibcon#flushed, iclass 20, count 2 2006.231.07:20:19.23#ibcon#about to write, iclass 20, count 2 2006.231.07:20:19.23#ibcon#wrote, iclass 20, count 2 2006.231.07:20:19.23#ibcon#about to read 3, iclass 20, count 2 2006.231.07:20:19.25#ibcon#read 3, iclass 20, count 2 2006.231.07:20:19.25#ibcon#about to read 4, iclass 20, count 2 2006.231.07:20:19.25#ibcon#read 4, iclass 20, count 2 2006.231.07:20:19.25#ibcon#about to read 5, iclass 20, count 2 2006.231.07:20:19.25#ibcon#read 5, iclass 20, count 2 2006.231.07:20:19.25#ibcon#about to read 6, iclass 20, count 2 2006.231.07:20:19.25#ibcon#read 6, iclass 20, count 2 2006.231.07:20:19.25#ibcon#end of sib2, iclass 20, count 2 2006.231.07:20:19.25#ibcon#*mode == 0, iclass 20, count 2 2006.231.07:20:19.25#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.07:20:19.25#ibcon#[27=AT03-04\r\n] 2006.231.07:20:19.25#ibcon#*before write, iclass 20, count 2 2006.231.07:20:19.25#ibcon#enter sib2, iclass 20, count 2 2006.231.07:20:19.25#ibcon#flushed, iclass 20, count 2 2006.231.07:20:19.25#ibcon#about to write, iclass 20, count 2 2006.231.07:20:19.25#ibcon#wrote, iclass 20, count 2 2006.231.07:20:19.25#ibcon#about to read 3, iclass 20, count 2 2006.231.07:20:19.28#ibcon#read 3, iclass 20, count 2 2006.231.07:20:19.28#ibcon#about to read 4, iclass 20, count 2 2006.231.07:20:19.28#ibcon#read 4, iclass 20, count 2 2006.231.07:20:19.28#ibcon#about to read 5, iclass 20, count 2 2006.231.07:20:19.28#ibcon#read 5, iclass 20, count 2 2006.231.07:20:19.28#ibcon#about to read 6, iclass 20, count 2 2006.231.07:20:19.28#ibcon#read 6, iclass 20, count 2 2006.231.07:20:19.28#ibcon#end of sib2, iclass 20, count 2 2006.231.07:20:19.28#ibcon#*after write, iclass 20, count 2 2006.231.07:20:19.28#ibcon#*before return 0, iclass 20, count 2 2006.231.07:20:19.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:20:19.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:20:19.28#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.07:20:19.28#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:19.28#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:20:19.40#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:20:19.40#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:20:19.40#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:20:19.40#ibcon#first serial, iclass 20, count 0 2006.231.07:20:19.40#ibcon#enter sib2, iclass 20, count 0 2006.231.07:20:19.40#ibcon#flushed, iclass 20, count 0 2006.231.07:20:19.40#ibcon#about to write, iclass 20, count 0 2006.231.07:20:19.40#ibcon#wrote, iclass 20, count 0 2006.231.07:20:19.40#ibcon#about to read 3, iclass 20, count 0 2006.231.07:20:19.42#ibcon#read 3, iclass 20, count 0 2006.231.07:20:19.42#ibcon#about to read 4, iclass 20, count 0 2006.231.07:20:19.42#ibcon#read 4, iclass 20, count 0 2006.231.07:20:19.42#ibcon#about to read 5, iclass 20, count 0 2006.231.07:20:19.42#ibcon#read 5, iclass 20, count 0 2006.231.07:20:19.42#ibcon#about to read 6, iclass 20, count 0 2006.231.07:20:19.42#ibcon#read 6, iclass 20, count 0 2006.231.07:20:19.42#ibcon#end of sib2, iclass 20, count 0 2006.231.07:20:19.42#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:20:19.42#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:20:19.42#ibcon#[27=USB\r\n] 2006.231.07:20:19.42#ibcon#*before write, iclass 20, count 0 2006.231.07:20:19.42#ibcon#enter sib2, iclass 20, count 0 2006.231.07:20:19.42#ibcon#flushed, iclass 20, count 0 2006.231.07:20:19.42#ibcon#about to write, iclass 20, count 0 2006.231.07:20:19.42#ibcon#wrote, iclass 20, count 0 2006.231.07:20:19.42#ibcon#about to read 3, iclass 20, count 0 2006.231.07:20:19.45#ibcon#read 3, iclass 20, count 0 2006.231.07:20:19.45#ibcon#about to read 4, iclass 20, count 0 2006.231.07:20:19.45#ibcon#read 4, iclass 20, count 0 2006.231.07:20:19.45#ibcon#about to read 5, iclass 20, count 0 2006.231.07:20:19.45#ibcon#read 5, iclass 20, count 0 2006.231.07:20:19.45#ibcon#about to read 6, iclass 20, count 0 2006.231.07:20:19.45#ibcon#read 6, iclass 20, count 0 2006.231.07:20:19.45#ibcon#end of sib2, iclass 20, count 0 2006.231.07:20:19.45#ibcon#*after write, iclass 20, count 0 2006.231.07:20:19.45#ibcon#*before return 0, iclass 20, count 0 2006.231.07:20:19.45#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:20:19.45#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:20:19.45#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:20:19.45#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:20:19.45$vc4f8/vblo=4,712.99 2006.231.07:20:19.45#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.07:20:19.45#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.07:20:19.45#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:19.45#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:20:19.45#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:20:19.45#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:20:19.45#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:20:19.45#ibcon#first serial, iclass 22, count 0 2006.231.07:20:19.45#ibcon#enter sib2, iclass 22, count 0 2006.231.07:20:19.45#ibcon#flushed, iclass 22, count 0 2006.231.07:20:19.45#ibcon#about to write, iclass 22, count 0 2006.231.07:20:19.45#ibcon#wrote, iclass 22, count 0 2006.231.07:20:19.45#ibcon#about to read 3, iclass 22, count 0 2006.231.07:20:19.47#ibcon#read 3, iclass 22, count 0 2006.231.07:20:19.47#ibcon#about to read 4, iclass 22, count 0 2006.231.07:20:19.47#ibcon#read 4, iclass 22, count 0 2006.231.07:20:19.47#ibcon#about to read 5, iclass 22, count 0 2006.231.07:20:19.47#ibcon#read 5, iclass 22, count 0 2006.231.07:20:19.47#ibcon#about to read 6, iclass 22, count 0 2006.231.07:20:19.47#ibcon#read 6, iclass 22, count 0 2006.231.07:20:19.47#ibcon#end of sib2, iclass 22, count 0 2006.231.07:20:19.47#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:20:19.47#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:20:19.47#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:20:19.47#ibcon#*before write, iclass 22, count 0 2006.231.07:20:19.47#ibcon#enter sib2, iclass 22, count 0 2006.231.07:20:19.47#ibcon#flushed, iclass 22, count 0 2006.231.07:20:19.47#ibcon#about to write, iclass 22, count 0 2006.231.07:20:19.47#ibcon#wrote, iclass 22, count 0 2006.231.07:20:19.47#ibcon#about to read 3, iclass 22, count 0 2006.231.07:20:19.51#ibcon#read 3, iclass 22, count 0 2006.231.07:20:19.51#ibcon#about to read 4, iclass 22, count 0 2006.231.07:20:19.51#ibcon#read 4, iclass 22, count 0 2006.231.07:20:19.51#ibcon#about to read 5, iclass 22, count 0 2006.231.07:20:19.51#ibcon#read 5, iclass 22, count 0 2006.231.07:20:19.51#ibcon#about to read 6, iclass 22, count 0 2006.231.07:20:19.51#ibcon#read 6, iclass 22, count 0 2006.231.07:20:19.51#ibcon#end of sib2, iclass 22, count 0 2006.231.07:20:19.51#ibcon#*after write, iclass 22, count 0 2006.231.07:20:19.51#ibcon#*before return 0, iclass 22, count 0 2006.231.07:20:19.51#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:20:19.51#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:20:19.51#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:20:19.51#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:20:19.51$vc4f8/vb=4,4 2006.231.07:20:19.51#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.07:20:19.51#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.07:20:19.51#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:19.51#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:20:19.57#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:20:19.57#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:20:19.57#ibcon#enter wrdev, iclass 24, count 2 2006.231.07:20:19.57#ibcon#first serial, iclass 24, count 2 2006.231.07:20:19.57#ibcon#enter sib2, iclass 24, count 2 2006.231.07:20:19.57#ibcon#flushed, iclass 24, count 2 2006.231.07:20:19.57#ibcon#about to write, iclass 24, count 2 2006.231.07:20:19.57#ibcon#wrote, iclass 24, count 2 2006.231.07:20:19.57#ibcon#about to read 3, iclass 24, count 2 2006.231.07:20:19.59#ibcon#read 3, iclass 24, count 2 2006.231.07:20:19.59#ibcon#about to read 4, iclass 24, count 2 2006.231.07:20:19.59#ibcon#read 4, iclass 24, count 2 2006.231.07:20:19.59#ibcon#about to read 5, iclass 24, count 2 2006.231.07:20:19.59#ibcon#read 5, iclass 24, count 2 2006.231.07:20:19.59#ibcon#about to read 6, iclass 24, count 2 2006.231.07:20:19.59#ibcon#read 6, iclass 24, count 2 2006.231.07:20:19.59#ibcon#end of sib2, iclass 24, count 2 2006.231.07:20:19.59#ibcon#*mode == 0, iclass 24, count 2 2006.231.07:20:19.59#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.07:20:19.59#ibcon#[27=AT04-04\r\n] 2006.231.07:20:19.59#ibcon#*before write, iclass 24, count 2 2006.231.07:20:19.59#ibcon#enter sib2, iclass 24, count 2 2006.231.07:20:19.59#ibcon#flushed, iclass 24, count 2 2006.231.07:20:19.59#ibcon#about to write, iclass 24, count 2 2006.231.07:20:19.59#ibcon#wrote, iclass 24, count 2 2006.231.07:20:19.59#ibcon#about to read 3, iclass 24, count 2 2006.231.07:20:19.62#ibcon#read 3, iclass 24, count 2 2006.231.07:20:19.62#ibcon#about to read 4, iclass 24, count 2 2006.231.07:20:19.62#ibcon#read 4, iclass 24, count 2 2006.231.07:20:19.62#ibcon#about to read 5, iclass 24, count 2 2006.231.07:20:19.62#ibcon#read 5, iclass 24, count 2 2006.231.07:20:19.62#ibcon#about to read 6, iclass 24, count 2 2006.231.07:20:19.62#ibcon#read 6, iclass 24, count 2 2006.231.07:20:19.62#ibcon#end of sib2, iclass 24, count 2 2006.231.07:20:19.62#ibcon#*after write, iclass 24, count 2 2006.231.07:20:19.62#ibcon#*before return 0, iclass 24, count 2 2006.231.07:20:19.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:20:19.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:20:19.62#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.07:20:19.62#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:19.62#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:20:19.74#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:20:19.74#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:20:19.74#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:20:19.74#ibcon#first serial, iclass 24, count 0 2006.231.07:20:19.74#ibcon#enter sib2, iclass 24, count 0 2006.231.07:20:19.74#ibcon#flushed, iclass 24, count 0 2006.231.07:20:19.74#ibcon#about to write, iclass 24, count 0 2006.231.07:20:19.74#ibcon#wrote, iclass 24, count 0 2006.231.07:20:19.74#ibcon#about to read 3, iclass 24, count 0 2006.231.07:20:19.76#ibcon#read 3, iclass 24, count 0 2006.231.07:20:19.76#ibcon#about to read 4, iclass 24, count 0 2006.231.07:20:19.76#ibcon#read 4, iclass 24, count 0 2006.231.07:20:19.76#ibcon#about to read 5, iclass 24, count 0 2006.231.07:20:19.76#ibcon#read 5, iclass 24, count 0 2006.231.07:20:19.76#ibcon#about to read 6, iclass 24, count 0 2006.231.07:20:19.76#ibcon#read 6, iclass 24, count 0 2006.231.07:20:19.76#ibcon#end of sib2, iclass 24, count 0 2006.231.07:20:19.76#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:20:19.76#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:20:19.76#ibcon#[27=USB\r\n] 2006.231.07:20:19.76#ibcon#*before write, iclass 24, count 0 2006.231.07:20:19.76#ibcon#enter sib2, iclass 24, count 0 2006.231.07:20:19.76#ibcon#flushed, iclass 24, count 0 2006.231.07:20:19.76#ibcon#about to write, iclass 24, count 0 2006.231.07:20:19.76#ibcon#wrote, iclass 24, count 0 2006.231.07:20:19.76#ibcon#about to read 3, iclass 24, count 0 2006.231.07:20:19.79#ibcon#read 3, iclass 24, count 0 2006.231.07:20:19.79#ibcon#about to read 4, iclass 24, count 0 2006.231.07:20:19.79#ibcon#read 4, iclass 24, count 0 2006.231.07:20:19.79#ibcon#about to read 5, iclass 24, count 0 2006.231.07:20:19.79#ibcon#read 5, iclass 24, count 0 2006.231.07:20:19.79#ibcon#about to read 6, iclass 24, count 0 2006.231.07:20:19.79#ibcon#read 6, iclass 24, count 0 2006.231.07:20:19.79#ibcon#end of sib2, iclass 24, count 0 2006.231.07:20:19.79#ibcon#*after write, iclass 24, count 0 2006.231.07:20:19.79#ibcon#*before return 0, iclass 24, count 0 2006.231.07:20:19.79#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:20:19.79#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:20:19.79#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:20:19.79#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:20:19.79$vc4f8/vblo=5,744.99 2006.231.07:20:19.79#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:20:19.79#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:20:19.79#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:19.79#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:20:19.79#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:20:19.79#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:20:19.79#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:20:19.79#ibcon#first serial, iclass 26, count 0 2006.231.07:20:19.79#ibcon#enter sib2, iclass 26, count 0 2006.231.07:20:19.79#ibcon#flushed, iclass 26, count 0 2006.231.07:20:19.79#ibcon#about to write, iclass 26, count 0 2006.231.07:20:19.79#ibcon#wrote, iclass 26, count 0 2006.231.07:20:19.79#ibcon#about to read 3, iclass 26, count 0 2006.231.07:20:19.81#ibcon#read 3, iclass 26, count 0 2006.231.07:20:19.81#ibcon#about to read 4, iclass 26, count 0 2006.231.07:20:19.81#ibcon#read 4, iclass 26, count 0 2006.231.07:20:19.81#ibcon#about to read 5, iclass 26, count 0 2006.231.07:20:19.81#ibcon#read 5, iclass 26, count 0 2006.231.07:20:19.81#ibcon#about to read 6, iclass 26, count 0 2006.231.07:20:19.81#ibcon#read 6, iclass 26, count 0 2006.231.07:20:19.81#ibcon#end of sib2, iclass 26, count 0 2006.231.07:20:19.81#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:20:19.81#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:20:19.81#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:20:19.81#ibcon#*before write, iclass 26, count 0 2006.231.07:20:19.81#ibcon#enter sib2, iclass 26, count 0 2006.231.07:20:19.81#ibcon#flushed, iclass 26, count 0 2006.231.07:20:19.81#ibcon#about to write, iclass 26, count 0 2006.231.07:20:19.81#ibcon#wrote, iclass 26, count 0 2006.231.07:20:19.81#ibcon#about to read 3, iclass 26, count 0 2006.231.07:20:19.85#ibcon#read 3, iclass 26, count 0 2006.231.07:20:19.85#ibcon#about to read 4, iclass 26, count 0 2006.231.07:20:19.85#ibcon#read 4, iclass 26, count 0 2006.231.07:20:19.85#ibcon#about to read 5, iclass 26, count 0 2006.231.07:20:19.85#ibcon#read 5, iclass 26, count 0 2006.231.07:20:19.85#ibcon#about to read 6, iclass 26, count 0 2006.231.07:20:19.85#ibcon#read 6, iclass 26, count 0 2006.231.07:20:19.85#ibcon#end of sib2, iclass 26, count 0 2006.231.07:20:19.85#ibcon#*after write, iclass 26, count 0 2006.231.07:20:19.85#ibcon#*before return 0, iclass 26, count 0 2006.231.07:20:19.85#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:20:19.85#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:20:19.85#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:20:19.85#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:20:19.85$vc4f8/vb=5,3 2006.231.07:20:19.85#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.07:20:19.85#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.07:20:19.85#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:19.85#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:20:19.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:20:19.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:20:19.91#ibcon#enter wrdev, iclass 28, count 2 2006.231.07:20:19.91#ibcon#first serial, iclass 28, count 2 2006.231.07:20:19.91#ibcon#enter sib2, iclass 28, count 2 2006.231.07:20:19.91#ibcon#flushed, iclass 28, count 2 2006.231.07:20:19.91#ibcon#about to write, iclass 28, count 2 2006.231.07:20:19.91#ibcon#wrote, iclass 28, count 2 2006.231.07:20:19.91#ibcon#about to read 3, iclass 28, count 2 2006.231.07:20:19.93#ibcon#read 3, iclass 28, count 2 2006.231.07:20:19.93#ibcon#about to read 4, iclass 28, count 2 2006.231.07:20:19.93#ibcon#read 4, iclass 28, count 2 2006.231.07:20:19.93#ibcon#about to read 5, iclass 28, count 2 2006.231.07:20:19.93#ibcon#read 5, iclass 28, count 2 2006.231.07:20:19.93#ibcon#about to read 6, iclass 28, count 2 2006.231.07:20:19.93#ibcon#read 6, iclass 28, count 2 2006.231.07:20:19.93#ibcon#end of sib2, iclass 28, count 2 2006.231.07:20:19.93#ibcon#*mode == 0, iclass 28, count 2 2006.231.07:20:19.93#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.07:20:19.93#ibcon#[27=AT05-03\r\n] 2006.231.07:20:19.93#ibcon#*before write, iclass 28, count 2 2006.231.07:20:19.93#ibcon#enter sib2, iclass 28, count 2 2006.231.07:20:19.93#ibcon#flushed, iclass 28, count 2 2006.231.07:20:19.93#ibcon#about to write, iclass 28, count 2 2006.231.07:20:19.93#ibcon#wrote, iclass 28, count 2 2006.231.07:20:19.93#ibcon#about to read 3, iclass 28, count 2 2006.231.07:20:19.96#ibcon#read 3, iclass 28, count 2 2006.231.07:20:19.96#ibcon#about to read 4, iclass 28, count 2 2006.231.07:20:19.96#ibcon#read 4, iclass 28, count 2 2006.231.07:20:19.96#ibcon#about to read 5, iclass 28, count 2 2006.231.07:20:19.96#ibcon#read 5, iclass 28, count 2 2006.231.07:20:19.96#ibcon#about to read 6, iclass 28, count 2 2006.231.07:20:19.96#ibcon#read 6, iclass 28, count 2 2006.231.07:20:19.96#ibcon#end of sib2, iclass 28, count 2 2006.231.07:20:19.96#ibcon#*after write, iclass 28, count 2 2006.231.07:20:19.96#ibcon#*before return 0, iclass 28, count 2 2006.231.07:20:19.96#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:20:19.96#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:20:19.96#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.07:20:19.96#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:19.96#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:20:20.08#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:20:20.08#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:20:20.08#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:20:20.08#ibcon#first serial, iclass 28, count 0 2006.231.07:20:20.08#ibcon#enter sib2, iclass 28, count 0 2006.231.07:20:20.08#ibcon#flushed, iclass 28, count 0 2006.231.07:20:20.08#ibcon#about to write, iclass 28, count 0 2006.231.07:20:20.08#ibcon#wrote, iclass 28, count 0 2006.231.07:20:20.08#ibcon#about to read 3, iclass 28, count 0 2006.231.07:20:20.10#ibcon#read 3, iclass 28, count 0 2006.231.07:20:20.10#ibcon#about to read 4, iclass 28, count 0 2006.231.07:20:20.10#ibcon#read 4, iclass 28, count 0 2006.231.07:20:20.10#ibcon#about to read 5, iclass 28, count 0 2006.231.07:20:20.10#ibcon#read 5, iclass 28, count 0 2006.231.07:20:20.10#ibcon#about to read 6, iclass 28, count 0 2006.231.07:20:20.10#ibcon#read 6, iclass 28, count 0 2006.231.07:20:20.10#ibcon#end of sib2, iclass 28, count 0 2006.231.07:20:20.10#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:20:20.10#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:20:20.10#ibcon#[27=USB\r\n] 2006.231.07:20:20.10#ibcon#*before write, iclass 28, count 0 2006.231.07:20:20.10#ibcon#enter sib2, iclass 28, count 0 2006.231.07:20:20.10#ibcon#flushed, iclass 28, count 0 2006.231.07:20:20.10#ibcon#about to write, iclass 28, count 0 2006.231.07:20:20.10#ibcon#wrote, iclass 28, count 0 2006.231.07:20:20.10#ibcon#about to read 3, iclass 28, count 0 2006.231.07:20:20.13#ibcon#read 3, iclass 28, count 0 2006.231.07:20:20.13#ibcon#about to read 4, iclass 28, count 0 2006.231.07:20:20.13#ibcon#read 4, iclass 28, count 0 2006.231.07:20:20.13#ibcon#about to read 5, iclass 28, count 0 2006.231.07:20:20.13#ibcon#read 5, iclass 28, count 0 2006.231.07:20:20.13#ibcon#about to read 6, iclass 28, count 0 2006.231.07:20:20.13#ibcon#read 6, iclass 28, count 0 2006.231.07:20:20.13#ibcon#end of sib2, iclass 28, count 0 2006.231.07:20:20.13#ibcon#*after write, iclass 28, count 0 2006.231.07:20:20.13#ibcon#*before return 0, iclass 28, count 0 2006.231.07:20:20.13#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:20:20.13#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:20:20.13#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:20:20.13#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:20:20.13$vc4f8/vblo=6,752.99 2006.231.07:20:20.13#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.07:20:20.13#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.07:20:20.13#ibcon#ireg 17 cls_cnt 0 2006.231.07:20:20.13#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:20:20.13#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:20:20.13#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:20:20.13#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:20:20.13#ibcon#first serial, iclass 30, count 0 2006.231.07:20:20.13#ibcon#enter sib2, iclass 30, count 0 2006.231.07:20:20.13#ibcon#flushed, iclass 30, count 0 2006.231.07:20:20.13#ibcon#about to write, iclass 30, count 0 2006.231.07:20:20.13#ibcon#wrote, iclass 30, count 0 2006.231.07:20:20.13#ibcon#about to read 3, iclass 30, count 0 2006.231.07:20:20.15#ibcon#read 3, iclass 30, count 0 2006.231.07:20:20.15#ibcon#about to read 4, iclass 30, count 0 2006.231.07:20:20.15#ibcon#read 4, iclass 30, count 0 2006.231.07:20:20.15#ibcon#about to read 5, iclass 30, count 0 2006.231.07:20:20.15#ibcon#read 5, iclass 30, count 0 2006.231.07:20:20.15#ibcon#about to read 6, iclass 30, count 0 2006.231.07:20:20.15#ibcon#read 6, iclass 30, count 0 2006.231.07:20:20.15#ibcon#end of sib2, iclass 30, count 0 2006.231.07:20:20.15#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:20:20.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:20:20.15#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:20:20.15#ibcon#*before write, iclass 30, count 0 2006.231.07:20:20.15#ibcon#enter sib2, iclass 30, count 0 2006.231.07:20:20.15#ibcon#flushed, iclass 30, count 0 2006.231.07:20:20.15#ibcon#about to write, iclass 30, count 0 2006.231.07:20:20.15#ibcon#wrote, iclass 30, count 0 2006.231.07:20:20.15#ibcon#about to read 3, iclass 30, count 0 2006.231.07:20:20.19#ibcon#read 3, iclass 30, count 0 2006.231.07:20:20.19#ibcon#about to read 4, iclass 30, count 0 2006.231.07:20:20.19#ibcon#read 4, iclass 30, count 0 2006.231.07:20:20.19#ibcon#about to read 5, iclass 30, count 0 2006.231.07:20:20.19#ibcon#read 5, iclass 30, count 0 2006.231.07:20:20.19#ibcon#about to read 6, iclass 30, count 0 2006.231.07:20:20.19#ibcon#read 6, iclass 30, count 0 2006.231.07:20:20.19#ibcon#end of sib2, iclass 30, count 0 2006.231.07:20:20.19#ibcon#*after write, iclass 30, count 0 2006.231.07:20:20.19#ibcon#*before return 0, iclass 30, count 0 2006.231.07:20:20.19#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:20:20.19#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:20:20.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:20:20.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:20:20.19$vc4f8/vb=6,4 2006.231.07:20:20.19#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.07:20:20.19#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.07:20:20.19#ibcon#ireg 11 cls_cnt 2 2006.231.07:20:20.19#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:20:20.25#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:20:20.25#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:20:20.25#ibcon#enter wrdev, iclass 32, count 2 2006.231.07:20:20.25#ibcon#first serial, iclass 32, count 2 2006.231.07:20:20.25#ibcon#enter sib2, iclass 32, count 2 2006.231.07:20:20.25#ibcon#flushed, iclass 32, count 2 2006.231.07:20:20.25#ibcon#about to write, iclass 32, count 2 2006.231.07:20:20.25#ibcon#wrote, iclass 32, count 2 2006.231.07:20:20.25#ibcon#about to read 3, iclass 32, count 2 2006.231.07:20:20.27#ibcon#read 3, iclass 32, count 2 2006.231.07:20:20.27#ibcon#about to read 4, iclass 32, count 2 2006.231.07:20:20.27#ibcon#read 4, iclass 32, count 2 2006.231.07:20:20.27#ibcon#about to read 5, iclass 32, count 2 2006.231.07:20:20.27#ibcon#read 5, iclass 32, count 2 2006.231.07:20:20.27#ibcon#about to read 6, iclass 32, count 2 2006.231.07:20:20.27#ibcon#read 6, iclass 32, count 2 2006.231.07:20:20.27#ibcon#end of sib2, iclass 32, count 2 2006.231.07:20:20.27#ibcon#*mode == 0, iclass 32, count 2 2006.231.07:20:20.27#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.07:20:20.27#ibcon#[27=AT06-04\r\n] 2006.231.07:20:20.27#ibcon#*before write, iclass 32, count 2 2006.231.07:20:20.27#ibcon#enter sib2, iclass 32, count 2 2006.231.07:20:20.27#ibcon#flushed, iclass 32, count 2 2006.231.07:20:20.27#ibcon#about to write, iclass 32, count 2 2006.231.07:20:20.27#ibcon#wrote, iclass 32, count 2 2006.231.07:20:20.27#ibcon#about to read 3, iclass 32, count 2 2006.231.07:20:20.31#ibcon#read 3, iclass 32, count 2 2006.231.07:20:20.31#ibcon#about to read 4, iclass 32, count 2 2006.231.07:20:20.31#ibcon#read 4, iclass 32, count 2 2006.231.07:20:20.31#ibcon#about to read 5, iclass 32, count 2 2006.231.07:20:20.31#ibcon#read 5, iclass 32, count 2 2006.231.07:20:20.31#ibcon#about to read 6, iclass 32, count 2 2006.231.07:20:20.31#ibcon#read 6, iclass 32, count 2 2006.231.07:20:20.31#ibcon#end of sib2, iclass 32, count 2 2006.231.07:20:20.31#ibcon#*after write, iclass 32, count 2 2006.231.07:20:20.31#ibcon#*before return 0, iclass 32, count 2 2006.231.07:20:20.31#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:20:20.31#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:20:20.31#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.07:20:20.31#ibcon#ireg 7 cls_cnt 0 2006.231.07:20:20.31#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:20:20.43#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:20:20.43#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:20:20.43#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:20:20.43#ibcon#first serial, iclass 32, count 0 2006.231.07:20:20.43#ibcon#enter sib2, iclass 32, count 0 2006.231.07:20:20.43#ibcon#flushed, iclass 32, count 0 2006.231.07:20:20.43#ibcon#about to write, iclass 32, count 0 2006.231.07:20:20.43#ibcon#wrote, iclass 32, count 0 2006.231.07:20:20.43#ibcon#about to read 3, iclass 32, count 0 2006.231.07:20:20.45#ibcon#read 3, iclass 32, count 0 2006.231.07:20:20.45#ibcon#about to read 4, iclass 32, count 0 2006.231.07:20:20.45#ibcon#read 4, iclass 32, count 0 2006.231.07:20:20.45#ibcon#about to read 5, iclass 32, count 0 2006.231.07:20:20.45#ibcon#read 5, iclass 32, count 0 2006.231.07:20:20.45#ibcon#about to read 6, iclass 32, count 0 2006.231.07:20:20.45#ibcon#read 6, iclass 32, count 0 2006.231.07:20:20.45#ibcon#end of sib2, iclass 32, count 0 2006.231.07:20:20.45#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:20:20.45#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:20:20.45#ibcon#[27=USB\r\n] 2006.231.07:20:20.45#ibcon#*before write, iclass 32, count 0 2006.231.07:20:20.45#ibcon#enter sib2, iclass 32, count 0 2006.231.07:20:20.45#ibcon#flushed, iclass 32, count 0 2006.231.07:20:20.45#ibcon#about to write, iclass 32, count 0 2006.231.07:20:20.45#ibcon#wrote, iclass 32, count 0 2006.231.07:20:20.45#ibcon#about to read 3, iclass 32, count 0 2006.231.07:20:20.48#ibcon#read 3, iclass 32, count 0 2006.231.07:20:20.48#ibcon#about to read 4, iclass 32, count 0 2006.231.07:20:20.48#ibcon#read 4, iclass 32, count 0 2006.231.07:20:20.48#ibcon#about to read 5, iclass 32, count 0 2006.231.07:20:20.48#ibcon#read 5, iclass 32, count 0 2006.231.07:20:20.48#ibcon#about to read 6, iclass 32, count 0 2006.231.07:20:20.48#ibcon#read 6, iclass 32, count 0 2006.231.07:20:20.48#ibcon#end of sib2, iclass 32, count 0 2006.231.07:20:20.48#ibcon#*after write, iclass 32, count 0 2006.231.07:20:20.48#ibcon#*before return 0, iclass 32, count 0 2006.231.07:20:20.48#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:20:20.48#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:20:20.48#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:20:20.48#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:20:20.48$vc4f8/vabw=wide 2006.231.07:20:20.48#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.07:20:20.48#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.07:20:20.48#ibcon#ireg 8 cls_cnt 0 2006.231.07:20:20.48#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:20:20.48#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:20:20.48#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:20:20.48#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:20:20.48#ibcon#first serial, iclass 34, count 0 2006.231.07:20:20.48#ibcon#enter sib2, iclass 34, count 0 2006.231.07:20:20.48#ibcon#flushed, iclass 34, count 0 2006.231.07:20:20.48#ibcon#about to write, iclass 34, count 0 2006.231.07:20:20.48#ibcon#wrote, iclass 34, count 0 2006.231.07:20:20.48#ibcon#about to read 3, iclass 34, count 0 2006.231.07:20:20.50#ibcon#read 3, iclass 34, count 0 2006.231.07:20:20.50#ibcon#about to read 4, iclass 34, count 0 2006.231.07:20:20.50#ibcon#read 4, iclass 34, count 0 2006.231.07:20:20.50#ibcon#about to read 5, iclass 34, count 0 2006.231.07:20:20.50#ibcon#read 5, iclass 34, count 0 2006.231.07:20:20.50#ibcon#about to read 6, iclass 34, count 0 2006.231.07:20:20.50#ibcon#read 6, iclass 34, count 0 2006.231.07:20:20.50#ibcon#end of sib2, iclass 34, count 0 2006.231.07:20:20.50#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:20:20.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:20:20.50#ibcon#[25=BW32\r\n] 2006.231.07:20:20.50#ibcon#*before write, iclass 34, count 0 2006.231.07:20:20.50#ibcon#enter sib2, iclass 34, count 0 2006.231.07:20:20.50#ibcon#flushed, iclass 34, count 0 2006.231.07:20:20.50#ibcon#about to write, iclass 34, count 0 2006.231.07:20:20.50#ibcon#wrote, iclass 34, count 0 2006.231.07:20:20.50#ibcon#about to read 3, iclass 34, count 0 2006.231.07:20:20.53#ibcon#read 3, iclass 34, count 0 2006.231.07:20:20.53#ibcon#about to read 4, iclass 34, count 0 2006.231.07:20:20.53#ibcon#read 4, iclass 34, count 0 2006.231.07:20:20.53#ibcon#about to read 5, iclass 34, count 0 2006.231.07:20:20.53#ibcon#read 5, iclass 34, count 0 2006.231.07:20:20.53#ibcon#about to read 6, iclass 34, count 0 2006.231.07:20:20.53#ibcon#read 6, iclass 34, count 0 2006.231.07:20:20.53#ibcon#end of sib2, iclass 34, count 0 2006.231.07:20:20.53#ibcon#*after write, iclass 34, count 0 2006.231.07:20:20.53#ibcon#*before return 0, iclass 34, count 0 2006.231.07:20:20.53#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:20:20.53#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:20:20.53#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:20:20.53#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:20:20.53$vc4f8/vbbw=wide 2006.231.07:20:20.53#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.07:20:20.53#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.07:20:20.53#ibcon#ireg 8 cls_cnt 0 2006.231.07:20:20.53#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:20:20.60#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:20:20.60#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:20:20.60#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:20:20.60#ibcon#first serial, iclass 36, count 0 2006.231.07:20:20.60#ibcon#enter sib2, iclass 36, count 0 2006.231.07:20:20.60#ibcon#flushed, iclass 36, count 0 2006.231.07:20:20.60#ibcon#about to write, iclass 36, count 0 2006.231.07:20:20.60#ibcon#wrote, iclass 36, count 0 2006.231.07:20:20.60#ibcon#about to read 3, iclass 36, count 0 2006.231.07:20:20.62#ibcon#read 3, iclass 36, count 0 2006.231.07:20:20.62#ibcon#about to read 4, iclass 36, count 0 2006.231.07:20:20.62#ibcon#read 4, iclass 36, count 0 2006.231.07:20:20.62#ibcon#about to read 5, iclass 36, count 0 2006.231.07:20:20.62#ibcon#read 5, iclass 36, count 0 2006.231.07:20:20.62#ibcon#about to read 6, iclass 36, count 0 2006.231.07:20:20.62#ibcon#read 6, iclass 36, count 0 2006.231.07:20:20.62#ibcon#end of sib2, iclass 36, count 0 2006.231.07:20:20.62#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:20:20.62#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:20:20.62#ibcon#[27=BW32\r\n] 2006.231.07:20:20.62#ibcon#*before write, iclass 36, count 0 2006.231.07:20:20.62#ibcon#enter sib2, iclass 36, count 0 2006.231.07:20:20.62#ibcon#flushed, iclass 36, count 0 2006.231.07:20:20.62#ibcon#about to write, iclass 36, count 0 2006.231.07:20:20.62#ibcon#wrote, iclass 36, count 0 2006.231.07:20:20.62#ibcon#about to read 3, iclass 36, count 0 2006.231.07:20:20.65#ibcon#read 3, iclass 36, count 0 2006.231.07:20:20.65#ibcon#about to read 4, iclass 36, count 0 2006.231.07:20:20.65#ibcon#read 4, iclass 36, count 0 2006.231.07:20:20.65#ibcon#about to read 5, iclass 36, count 0 2006.231.07:20:20.65#ibcon#read 5, iclass 36, count 0 2006.231.07:20:20.65#ibcon#about to read 6, iclass 36, count 0 2006.231.07:20:20.65#ibcon#read 6, iclass 36, count 0 2006.231.07:20:20.65#ibcon#end of sib2, iclass 36, count 0 2006.231.07:20:20.65#ibcon#*after write, iclass 36, count 0 2006.231.07:20:20.65#ibcon#*before return 0, iclass 36, count 0 2006.231.07:20:20.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:20:20.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:20:20.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:20:20.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:20:20.65$4f8m12a/ifd4f 2006.231.07:20:20.65&ifd4f/lo= 2006.231.07:20:20.65&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:20:20.65&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:20:20.65&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:20:20.65&ifd4f/patch= 2006.231.07:20:20.65&ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:20:20.65&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:20:20.65&ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:20:20.65$ifd4f/lo= 2006.231.07:20:20.65$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:20:20.65$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:20:20.65$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:20:20.65$ifd4f/patch= 2006.231.07:20:20.65$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:20:20.65$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:20:20.65$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:20:20.65$4f8m12a/"form=m,16.000,1:2 2006.231.07:20:20.65$4f8m12a/"tpicd 2006.231.07:20:20.65$4f8m12a/echo=off 2006.231.07:20:20.65$4f8m12a/xlog=off 2006.231.07:20:20.65:!2006.231.07:29:50 2006.231.07:20:37.14#trakl#Source acquired 2006.231.07:20:38.14#flagr#flagr/antenna,acquired 2006.231.07:29:50.01:preob 2006.231.07:29:50.01&preob/onsource 2006.231.07:29:51.14/onsource/TRACKING 2006.231.07:29:51.14:!2006.231.07:30:00 2006.231.07:30:00.00:data_valid=on 2006.231.07:30:00.00:midob 2006.231.07:30:00.00&midob/onsource 2006.231.07:30:00.00&midob/wx 2006.231.07:30:00.00&midob/cable 2006.231.07:30:00.00&midob/va 2006.231.07:30:00.00&midob/valo 2006.231.07:30:00.00&midob/vb 2006.231.07:30:00.00&midob/vblo 2006.231.07:30:00.00&midob/vabw 2006.231.07:30:00.00&midob/vbbw 2006.231.07:30:00.00&midob/"form 2006.231.07:30:00.00&midob/xfe 2006.231.07:30:00.00&midob/ifatt 2006.231.07:30:00.00&midob/clockoff 2006.231.07:30:00.00&midob/sy=logmail 2006.231.07:30:00.00&midob/"sy=run setcl adapt & 2006.231.07:30:00.14/onsource/TRACKING 2006.231.07:30:00.14/wx/30.82,1004.5,84 2006.231.07:30:00.33/cable/+6.3690E-03 2006.231.07:30:01.42/va/01,08,usb,yes,31,32 2006.231.07:30:01.42/va/02,07,usb,yes,31,32 2006.231.07:30:01.42/va/03,08,usb,yes,23,23 2006.231.07:30:01.42/va/04,07,usb,yes,32,35 2006.231.07:30:01.42/va/05,07,usb,yes,36,38 2006.231.07:30:01.42/va/06,06,usb,yes,35,35 2006.231.07:30:01.42/va/07,06,usb,yes,36,36 2006.231.07:30:01.42/va/08,06,usb,yes,38,38 2006.231.07:30:01.65/valo/01,532.99,yes,locked 2006.231.07:30:01.65/valo/02,572.99,yes,locked 2006.231.07:30:01.65/valo/03,672.99,yes,locked 2006.231.07:30:01.65/valo/04,832.99,yes,locked 2006.231.07:30:01.65/valo/05,652.99,yes,locked 2006.231.07:30:01.65/valo/06,772.99,yes,locked 2006.231.07:30:01.65/valo/07,832.99,yes,locked 2006.231.07:30:01.65/valo/08,852.99,yes,locked 2006.231.07:30:02.74/vb/01,04,usb,yes,32,30 2006.231.07:30:02.74/vb/02,04,usb,yes,33,35 2006.231.07:30:02.74/vb/03,04,usb,yes,30,34 2006.231.07:30:02.74/vb/04,04,usb,yes,31,31 2006.231.07:30:02.74/vb/05,03,usb,yes,36,41 2006.231.07:30:02.74/vb/06,04,usb,yes,30,33 2006.231.07:30:02.74/vb/07,04,usb,yes,32,32 2006.231.07:30:02.74/vb/08,04,usb,yes,30,33 2006.231.07:30:02.97/vblo/01,632.99,yes,locked 2006.231.07:30:02.97/vblo/02,640.99,yes,locked 2006.231.07:30:02.97/vblo/03,656.99,yes,locked 2006.231.07:30:02.97/vblo/04,712.99,yes,locked 2006.231.07:30:02.97/vblo/05,744.99,yes,locked 2006.231.07:30:02.97/vblo/06,752.99,yes,locked 2006.231.07:30:02.97/vblo/07,734.99,yes,locked 2006.231.07:30:02.97/vblo/08,744.99,yes,locked 2006.231.07:30:03.12/vabw/8 2006.231.07:30:03.27/vbbw/8 2006.231.07:30:03.36/xfe/off,on,12.7 2006.231.07:30:03.73/ifatt/23,28,28,28 2006.231.07:30:04.07/fmout-gps/S +4.36E-07 2006.231.07:30:04.15:!2006.231.07:31:00 2006.231.07:31:00.01:data_valid=off 2006.231.07:31:00.02:postob 2006.231.07:31:00.02&postob/cable 2006.231.07:31:00.02&postob/wx 2006.231.07:31:00.03&postob/clockoff 2006.231.07:31:00.14/cable/+6.3687E-03 2006.231.07:31:00.15/wx/30.80,1004.5,85 2006.231.07:31:00.23/fmout-gps/S +4.36E-07 2006.231.07:31:00.23:scan_name=231-0733,k06231,60 2006.231.07:31:00.24:source=oj287,085448.87,200630.6,2000.0,ccw 2006.231.07:31:01.14#flagr#flagr/antenna,new-source 2006.231.07:31:01.15:checkk5 2006.231.07:31:01.15&checkk5/chk_autoobs=1 2006.231.07:31:01.15&checkk5/chk_autoobs=2 2006.231.07:31:01.16&checkk5/chk_autoobs=3 2006.231.07:31:01.16&checkk5/chk_autoobs=4 2006.231.07:31:01.17&checkk5/chk_obsdata=1 2006.231.07:31:01.17&checkk5/chk_obsdata=2 2006.231.07:31:01.17&checkk5/chk_obsdata=3 2006.231.07:31:01.18&checkk5/chk_obsdata=4 2006.231.07:31:01.18&checkk5/k5log=1 2006.231.07:31:01.18&checkk5/k5log=2 2006.231.07:31:01.23&checkk5/k5log=3 2006.231.07:31:01.23&checkk5/k5log=4 2006.231.07:31:01.24&checkk5/obsinfo 2006.231.07:31:02.01/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:31:02.99/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:31:03.39/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:31:03.77/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:31:04.15/chk_obsdata//k5ts1/T2310730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:31:04.52/chk_obsdata//k5ts2/T2310730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:31:04.88/chk_obsdata//k5ts3/T2310730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:31:05.26/chk_obsdata//k5ts4/T2310730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:31:05.97/k5log//k5ts1_log_newline 2006.231.07:31:06.69/k5log//k5ts2_log_newline 2006.231.07:31:07.38/k5log//k5ts3_log_newline 2006.231.07:31:08.08/k5log//k5ts4_log_newline 2006.231.07:31:08.10/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:31:08.10:4f8m12a=1 2006.231.07:31:08.10$4f8m12a/echo=on 2006.231.07:31:08.10$4f8m12a/pcalon 2006.231.07:31:08.10$pcalon/"no phase cal control is implemented here 2006.231.07:31:08.10$4f8m12a/"tpicd=stop 2006.231.07:31:08.10$4f8m12a/vc4f8 2006.231.07:31:08.10$vc4f8/valo=1,532.99 2006.231.07:31:08.11#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.07:31:08.11#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.07:31:08.11#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:08.11#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:31:08.11#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:31:08.11#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:31:08.11#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:31:08.11#ibcon#first serial, iclass 34, count 0 2006.231.07:31:08.11#ibcon#enter sib2, iclass 34, count 0 2006.231.07:31:08.11#ibcon#flushed, iclass 34, count 0 2006.231.07:31:08.11#ibcon#about to write, iclass 34, count 0 2006.231.07:31:08.11#ibcon#wrote, iclass 34, count 0 2006.231.07:31:08.11#ibcon#about to read 3, iclass 34, count 0 2006.231.07:31:08.15#ibcon#read 3, iclass 34, count 0 2006.231.07:31:08.15#ibcon#about to read 4, iclass 34, count 0 2006.231.07:31:08.15#ibcon#read 4, iclass 34, count 0 2006.231.07:31:08.15#ibcon#about to read 5, iclass 34, count 0 2006.231.07:31:08.15#ibcon#read 5, iclass 34, count 0 2006.231.07:31:08.15#ibcon#about to read 6, iclass 34, count 0 2006.231.07:31:08.15#ibcon#read 6, iclass 34, count 0 2006.231.07:31:08.15#ibcon#end of sib2, iclass 34, count 0 2006.231.07:31:08.15#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:31:08.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:31:08.15#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:31:08.15#ibcon#*before write, iclass 34, count 0 2006.231.07:31:08.15#ibcon#enter sib2, iclass 34, count 0 2006.231.07:31:08.15#ibcon#flushed, iclass 34, count 0 2006.231.07:31:08.15#ibcon#about to write, iclass 34, count 0 2006.231.07:31:08.15#ibcon#wrote, iclass 34, count 0 2006.231.07:31:08.15#ibcon#about to read 3, iclass 34, count 0 2006.231.07:31:08.19#ibcon#read 3, iclass 34, count 0 2006.231.07:31:08.19#ibcon#about to read 4, iclass 34, count 0 2006.231.07:31:08.19#ibcon#read 4, iclass 34, count 0 2006.231.07:31:08.19#ibcon#about to read 5, iclass 34, count 0 2006.231.07:31:08.19#ibcon#read 5, iclass 34, count 0 2006.231.07:31:08.19#ibcon#about to read 6, iclass 34, count 0 2006.231.07:31:08.19#ibcon#read 6, iclass 34, count 0 2006.231.07:31:08.19#ibcon#end of sib2, iclass 34, count 0 2006.231.07:31:08.19#ibcon#*after write, iclass 34, count 0 2006.231.07:31:08.19#ibcon#*before return 0, iclass 34, count 0 2006.231.07:31:08.19#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:31:08.19#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:31:08.19#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:31:08.19#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:31:08.19$vc4f8/va=1,8 2006.231.07:31:08.19#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.07:31:08.19#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.07:31:08.19#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:08.19#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:31:08.19#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:31:08.19#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:31:08.19#ibcon#enter wrdev, iclass 36, count 2 2006.231.07:31:08.19#ibcon#first serial, iclass 36, count 2 2006.231.07:31:08.19#ibcon#enter sib2, iclass 36, count 2 2006.231.07:31:08.19#ibcon#flushed, iclass 36, count 2 2006.231.07:31:08.19#ibcon#about to write, iclass 36, count 2 2006.231.07:31:08.19#ibcon#wrote, iclass 36, count 2 2006.231.07:31:08.19#ibcon#about to read 3, iclass 36, count 2 2006.231.07:31:08.21#ibcon#read 3, iclass 36, count 2 2006.231.07:31:08.21#ibcon#about to read 4, iclass 36, count 2 2006.231.07:31:08.21#ibcon#read 4, iclass 36, count 2 2006.231.07:31:08.21#ibcon#about to read 5, iclass 36, count 2 2006.231.07:31:08.21#ibcon#read 5, iclass 36, count 2 2006.231.07:31:08.21#ibcon#about to read 6, iclass 36, count 2 2006.231.07:31:08.21#ibcon#read 6, iclass 36, count 2 2006.231.07:31:08.21#ibcon#end of sib2, iclass 36, count 2 2006.231.07:31:08.21#ibcon#*mode == 0, iclass 36, count 2 2006.231.07:31:08.21#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.07:31:08.21#ibcon#[25=AT01-08\r\n] 2006.231.07:31:08.21#ibcon#*before write, iclass 36, count 2 2006.231.07:31:08.21#ibcon#enter sib2, iclass 36, count 2 2006.231.07:31:08.21#ibcon#flushed, iclass 36, count 2 2006.231.07:31:08.21#ibcon#about to write, iclass 36, count 2 2006.231.07:31:08.21#ibcon#wrote, iclass 36, count 2 2006.231.07:31:08.21#ibcon#about to read 3, iclass 36, count 2 2006.231.07:31:08.25#ibcon#read 3, iclass 36, count 2 2006.231.07:31:08.25#ibcon#about to read 4, iclass 36, count 2 2006.231.07:31:08.25#ibcon#read 4, iclass 36, count 2 2006.231.07:31:08.25#ibcon#about to read 5, iclass 36, count 2 2006.231.07:31:08.25#ibcon#read 5, iclass 36, count 2 2006.231.07:31:08.25#ibcon#about to read 6, iclass 36, count 2 2006.231.07:31:08.25#ibcon#read 6, iclass 36, count 2 2006.231.07:31:08.25#ibcon#end of sib2, iclass 36, count 2 2006.231.07:31:08.25#ibcon#*after write, iclass 36, count 2 2006.231.07:31:08.25#ibcon#*before return 0, iclass 36, count 2 2006.231.07:31:08.25#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:31:08.25#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:31:08.25#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.07:31:08.25#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:08.25#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:31:08.36#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:31:08.36#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:31:08.36#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:31:08.36#ibcon#first serial, iclass 36, count 0 2006.231.07:31:08.36#ibcon#enter sib2, iclass 36, count 0 2006.231.07:31:08.36#ibcon#flushed, iclass 36, count 0 2006.231.07:31:08.36#ibcon#about to write, iclass 36, count 0 2006.231.07:31:08.36#ibcon#wrote, iclass 36, count 0 2006.231.07:31:08.36#ibcon#about to read 3, iclass 36, count 0 2006.231.07:31:08.38#ibcon#read 3, iclass 36, count 0 2006.231.07:31:08.38#ibcon#about to read 4, iclass 36, count 0 2006.231.07:31:08.38#ibcon#read 4, iclass 36, count 0 2006.231.07:31:08.38#ibcon#about to read 5, iclass 36, count 0 2006.231.07:31:08.38#ibcon#read 5, iclass 36, count 0 2006.231.07:31:08.38#ibcon#about to read 6, iclass 36, count 0 2006.231.07:31:08.38#ibcon#read 6, iclass 36, count 0 2006.231.07:31:08.38#ibcon#end of sib2, iclass 36, count 0 2006.231.07:31:08.38#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:31:08.38#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:31:08.38#ibcon#[25=USB\r\n] 2006.231.07:31:08.38#ibcon#*before write, iclass 36, count 0 2006.231.07:31:08.38#ibcon#enter sib2, iclass 36, count 0 2006.231.07:31:08.38#ibcon#flushed, iclass 36, count 0 2006.231.07:31:08.38#ibcon#about to write, iclass 36, count 0 2006.231.07:31:08.38#ibcon#wrote, iclass 36, count 0 2006.231.07:31:08.38#ibcon#about to read 3, iclass 36, count 0 2006.231.07:31:08.41#ibcon#read 3, iclass 36, count 0 2006.231.07:31:08.41#ibcon#about to read 4, iclass 36, count 0 2006.231.07:31:08.41#ibcon#read 4, iclass 36, count 0 2006.231.07:31:08.41#ibcon#about to read 5, iclass 36, count 0 2006.231.07:31:08.41#ibcon#read 5, iclass 36, count 0 2006.231.07:31:08.41#ibcon#about to read 6, iclass 36, count 0 2006.231.07:31:08.41#ibcon#read 6, iclass 36, count 0 2006.231.07:31:08.41#ibcon#end of sib2, iclass 36, count 0 2006.231.07:31:08.41#ibcon#*after write, iclass 36, count 0 2006.231.07:31:08.41#ibcon#*before return 0, iclass 36, count 0 2006.231.07:31:08.41#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:31:08.41#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:31:08.41#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:31:08.41#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:31:08.41$vc4f8/valo=2,572.99 2006.231.07:31:08.41#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.07:31:08.41#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.07:31:08.41#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:08.41#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:31:08.41#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:31:08.41#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:31:08.41#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:31:08.41#ibcon#first serial, iclass 38, count 0 2006.231.07:31:08.41#ibcon#enter sib2, iclass 38, count 0 2006.231.07:31:08.41#ibcon#flushed, iclass 38, count 0 2006.231.07:31:08.41#ibcon#about to write, iclass 38, count 0 2006.231.07:31:08.41#ibcon#wrote, iclass 38, count 0 2006.231.07:31:08.41#ibcon#about to read 3, iclass 38, count 0 2006.231.07:31:08.43#ibcon#read 3, iclass 38, count 0 2006.231.07:31:08.43#ibcon#about to read 4, iclass 38, count 0 2006.231.07:31:08.43#ibcon#read 4, iclass 38, count 0 2006.231.07:31:08.43#ibcon#about to read 5, iclass 38, count 0 2006.231.07:31:08.43#ibcon#read 5, iclass 38, count 0 2006.231.07:31:08.43#ibcon#about to read 6, iclass 38, count 0 2006.231.07:31:08.43#ibcon#read 6, iclass 38, count 0 2006.231.07:31:08.43#ibcon#end of sib2, iclass 38, count 0 2006.231.07:31:08.43#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:31:08.43#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:31:08.43#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:31:08.43#ibcon#*before write, iclass 38, count 0 2006.231.07:31:08.43#ibcon#enter sib2, iclass 38, count 0 2006.231.07:31:08.43#ibcon#flushed, iclass 38, count 0 2006.231.07:31:08.43#ibcon#about to write, iclass 38, count 0 2006.231.07:31:08.43#ibcon#wrote, iclass 38, count 0 2006.231.07:31:08.43#ibcon#about to read 3, iclass 38, count 0 2006.231.07:31:08.47#ibcon#read 3, iclass 38, count 0 2006.231.07:31:08.47#ibcon#about to read 4, iclass 38, count 0 2006.231.07:31:08.47#ibcon#read 4, iclass 38, count 0 2006.231.07:31:08.47#ibcon#about to read 5, iclass 38, count 0 2006.231.07:31:08.47#ibcon#read 5, iclass 38, count 0 2006.231.07:31:08.47#ibcon#about to read 6, iclass 38, count 0 2006.231.07:31:08.47#ibcon#read 6, iclass 38, count 0 2006.231.07:31:08.47#ibcon#end of sib2, iclass 38, count 0 2006.231.07:31:08.47#ibcon#*after write, iclass 38, count 0 2006.231.07:31:08.47#ibcon#*before return 0, iclass 38, count 0 2006.231.07:31:08.47#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:31:08.47#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:31:08.47#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:31:08.47#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:31:08.47$vc4f8/va=2,7 2006.231.07:31:08.47#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.07:31:08.47#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.07:31:08.47#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:08.47#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:31:08.53#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:31:08.53#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:31:08.53#ibcon#enter wrdev, iclass 40, count 2 2006.231.07:31:08.53#ibcon#first serial, iclass 40, count 2 2006.231.07:31:08.53#ibcon#enter sib2, iclass 40, count 2 2006.231.07:31:08.53#ibcon#flushed, iclass 40, count 2 2006.231.07:31:08.53#ibcon#about to write, iclass 40, count 2 2006.231.07:31:08.53#ibcon#wrote, iclass 40, count 2 2006.231.07:31:08.53#ibcon#about to read 3, iclass 40, count 2 2006.231.07:31:08.55#ibcon#read 3, iclass 40, count 2 2006.231.07:31:08.55#ibcon#about to read 4, iclass 40, count 2 2006.231.07:31:08.55#ibcon#read 4, iclass 40, count 2 2006.231.07:31:08.55#ibcon#about to read 5, iclass 40, count 2 2006.231.07:31:08.55#ibcon#read 5, iclass 40, count 2 2006.231.07:31:08.55#ibcon#about to read 6, iclass 40, count 2 2006.231.07:31:08.55#ibcon#read 6, iclass 40, count 2 2006.231.07:31:08.55#ibcon#end of sib2, iclass 40, count 2 2006.231.07:31:08.55#ibcon#*mode == 0, iclass 40, count 2 2006.231.07:31:08.55#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.07:31:08.55#ibcon#[25=AT02-07\r\n] 2006.231.07:31:08.55#ibcon#*before write, iclass 40, count 2 2006.231.07:31:08.55#ibcon#enter sib2, iclass 40, count 2 2006.231.07:31:08.55#ibcon#flushed, iclass 40, count 2 2006.231.07:31:08.55#ibcon#about to write, iclass 40, count 2 2006.231.07:31:08.55#ibcon#wrote, iclass 40, count 2 2006.231.07:31:08.55#ibcon#about to read 3, iclass 40, count 2 2006.231.07:31:08.58#ibcon#read 3, iclass 40, count 2 2006.231.07:31:08.58#ibcon#about to read 4, iclass 40, count 2 2006.231.07:31:08.58#ibcon#read 4, iclass 40, count 2 2006.231.07:31:08.58#ibcon#about to read 5, iclass 40, count 2 2006.231.07:31:08.58#ibcon#read 5, iclass 40, count 2 2006.231.07:31:08.58#ibcon#about to read 6, iclass 40, count 2 2006.231.07:31:08.58#ibcon#read 6, iclass 40, count 2 2006.231.07:31:08.58#ibcon#end of sib2, iclass 40, count 2 2006.231.07:31:08.58#ibcon#*after write, iclass 40, count 2 2006.231.07:31:08.58#ibcon#*before return 0, iclass 40, count 2 2006.231.07:31:08.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:31:08.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:31:08.58#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.07:31:08.58#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:08.58#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:31:08.70#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:31:08.70#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:31:08.70#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:31:08.70#ibcon#first serial, iclass 40, count 0 2006.231.07:31:08.70#ibcon#enter sib2, iclass 40, count 0 2006.231.07:31:08.70#ibcon#flushed, iclass 40, count 0 2006.231.07:31:08.70#ibcon#about to write, iclass 40, count 0 2006.231.07:31:08.70#ibcon#wrote, iclass 40, count 0 2006.231.07:31:08.70#ibcon#about to read 3, iclass 40, count 0 2006.231.07:31:08.72#ibcon#read 3, iclass 40, count 0 2006.231.07:31:08.72#ibcon#about to read 4, iclass 40, count 0 2006.231.07:31:08.72#ibcon#read 4, iclass 40, count 0 2006.231.07:31:08.72#ibcon#about to read 5, iclass 40, count 0 2006.231.07:31:08.72#ibcon#read 5, iclass 40, count 0 2006.231.07:31:08.72#ibcon#about to read 6, iclass 40, count 0 2006.231.07:31:08.72#ibcon#read 6, iclass 40, count 0 2006.231.07:31:08.72#ibcon#end of sib2, iclass 40, count 0 2006.231.07:31:08.72#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:31:08.72#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:31:08.72#ibcon#[25=USB\r\n] 2006.231.07:31:08.72#ibcon#*before write, iclass 40, count 0 2006.231.07:31:08.72#ibcon#enter sib2, iclass 40, count 0 2006.231.07:31:08.72#ibcon#flushed, iclass 40, count 0 2006.231.07:31:08.72#ibcon#about to write, iclass 40, count 0 2006.231.07:31:08.72#ibcon#wrote, iclass 40, count 0 2006.231.07:31:08.72#ibcon#about to read 3, iclass 40, count 0 2006.231.07:31:08.75#ibcon#read 3, iclass 40, count 0 2006.231.07:31:08.75#ibcon#about to read 4, iclass 40, count 0 2006.231.07:31:08.75#ibcon#read 4, iclass 40, count 0 2006.231.07:31:08.75#ibcon#about to read 5, iclass 40, count 0 2006.231.07:31:08.75#ibcon#read 5, iclass 40, count 0 2006.231.07:31:08.75#ibcon#about to read 6, iclass 40, count 0 2006.231.07:31:08.75#ibcon#read 6, iclass 40, count 0 2006.231.07:31:08.75#ibcon#end of sib2, iclass 40, count 0 2006.231.07:31:08.75#ibcon#*after write, iclass 40, count 0 2006.231.07:31:08.75#ibcon#*before return 0, iclass 40, count 0 2006.231.07:31:08.75#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:31:08.75#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:31:08.75#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:31:08.75#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:31:08.75$vc4f8/valo=3,672.99 2006.231.07:31:08.75#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.07:31:08.75#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.07:31:08.75#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:08.75#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:31:08.75#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:31:08.75#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:31:08.75#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:31:08.75#ibcon#first serial, iclass 4, count 0 2006.231.07:31:08.75#ibcon#enter sib2, iclass 4, count 0 2006.231.07:31:08.75#ibcon#flushed, iclass 4, count 0 2006.231.07:31:08.75#ibcon#about to write, iclass 4, count 0 2006.231.07:31:08.75#ibcon#wrote, iclass 4, count 0 2006.231.07:31:08.75#ibcon#about to read 3, iclass 4, count 0 2006.231.07:31:08.77#ibcon#read 3, iclass 4, count 0 2006.231.07:31:08.77#ibcon#about to read 4, iclass 4, count 0 2006.231.07:31:08.77#ibcon#read 4, iclass 4, count 0 2006.231.07:31:08.77#ibcon#about to read 5, iclass 4, count 0 2006.231.07:31:08.77#ibcon#read 5, iclass 4, count 0 2006.231.07:31:08.77#ibcon#about to read 6, iclass 4, count 0 2006.231.07:31:08.77#ibcon#read 6, iclass 4, count 0 2006.231.07:31:08.77#ibcon#end of sib2, iclass 4, count 0 2006.231.07:31:08.77#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:31:08.77#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:31:08.77#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:31:08.77#ibcon#*before write, iclass 4, count 0 2006.231.07:31:08.77#ibcon#enter sib2, iclass 4, count 0 2006.231.07:31:08.77#ibcon#flushed, iclass 4, count 0 2006.231.07:31:08.77#ibcon#about to write, iclass 4, count 0 2006.231.07:31:08.77#ibcon#wrote, iclass 4, count 0 2006.231.07:31:08.77#ibcon#about to read 3, iclass 4, count 0 2006.231.07:31:08.82#ibcon#read 3, iclass 4, count 0 2006.231.07:31:08.82#ibcon#about to read 4, iclass 4, count 0 2006.231.07:31:08.82#ibcon#read 4, iclass 4, count 0 2006.231.07:31:08.82#ibcon#about to read 5, iclass 4, count 0 2006.231.07:31:08.82#ibcon#read 5, iclass 4, count 0 2006.231.07:31:08.82#ibcon#about to read 6, iclass 4, count 0 2006.231.07:31:08.82#ibcon#read 6, iclass 4, count 0 2006.231.07:31:08.82#ibcon#end of sib2, iclass 4, count 0 2006.231.07:31:08.82#ibcon#*after write, iclass 4, count 0 2006.231.07:31:08.82#ibcon#*before return 0, iclass 4, count 0 2006.231.07:31:08.82#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:31:08.82#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:31:08.82#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:31:08.82#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:31:08.82$vc4f8/va=3,8 2006.231.07:31:08.82#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.07:31:08.82#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.07:31:08.82#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:08.82#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:31:08.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:31:08.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:31:08.86#ibcon#enter wrdev, iclass 6, count 2 2006.231.07:31:08.86#ibcon#first serial, iclass 6, count 2 2006.231.07:31:08.86#ibcon#enter sib2, iclass 6, count 2 2006.231.07:31:08.86#ibcon#flushed, iclass 6, count 2 2006.231.07:31:08.86#ibcon#about to write, iclass 6, count 2 2006.231.07:31:08.86#ibcon#wrote, iclass 6, count 2 2006.231.07:31:08.86#ibcon#about to read 3, iclass 6, count 2 2006.231.07:31:08.88#ibcon#read 3, iclass 6, count 2 2006.231.07:31:08.88#ibcon#about to read 4, iclass 6, count 2 2006.231.07:31:08.88#ibcon#read 4, iclass 6, count 2 2006.231.07:31:08.88#ibcon#about to read 5, iclass 6, count 2 2006.231.07:31:08.88#ibcon#read 5, iclass 6, count 2 2006.231.07:31:08.88#ibcon#about to read 6, iclass 6, count 2 2006.231.07:31:08.88#ibcon#read 6, iclass 6, count 2 2006.231.07:31:08.88#ibcon#end of sib2, iclass 6, count 2 2006.231.07:31:08.88#ibcon#*mode == 0, iclass 6, count 2 2006.231.07:31:08.88#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.07:31:08.88#ibcon#[25=AT03-08\r\n] 2006.231.07:31:08.88#ibcon#*before write, iclass 6, count 2 2006.231.07:31:08.88#ibcon#enter sib2, iclass 6, count 2 2006.231.07:31:08.88#ibcon#flushed, iclass 6, count 2 2006.231.07:31:08.88#ibcon#about to write, iclass 6, count 2 2006.231.07:31:08.88#ibcon#wrote, iclass 6, count 2 2006.231.07:31:08.88#ibcon#about to read 3, iclass 6, count 2 2006.231.07:31:08.91#ibcon#read 3, iclass 6, count 2 2006.231.07:31:08.91#ibcon#about to read 4, iclass 6, count 2 2006.231.07:31:08.91#ibcon#read 4, iclass 6, count 2 2006.231.07:31:08.91#ibcon#about to read 5, iclass 6, count 2 2006.231.07:31:08.91#ibcon#read 5, iclass 6, count 2 2006.231.07:31:08.91#ibcon#about to read 6, iclass 6, count 2 2006.231.07:31:08.91#ibcon#read 6, iclass 6, count 2 2006.231.07:31:08.91#ibcon#end of sib2, iclass 6, count 2 2006.231.07:31:08.91#ibcon#*after write, iclass 6, count 2 2006.231.07:31:08.91#ibcon#*before return 0, iclass 6, count 2 2006.231.07:31:08.91#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:31:08.91#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:31:08.91#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.07:31:08.91#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:08.91#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:31:09.03#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:31:09.03#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:31:09.03#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:31:09.03#ibcon#first serial, iclass 6, count 0 2006.231.07:31:09.03#ibcon#enter sib2, iclass 6, count 0 2006.231.07:31:09.03#ibcon#flushed, iclass 6, count 0 2006.231.07:31:09.03#ibcon#about to write, iclass 6, count 0 2006.231.07:31:09.03#ibcon#wrote, iclass 6, count 0 2006.231.07:31:09.03#ibcon#about to read 3, iclass 6, count 0 2006.231.07:31:09.05#ibcon#read 3, iclass 6, count 0 2006.231.07:31:09.05#ibcon#about to read 4, iclass 6, count 0 2006.231.07:31:09.05#ibcon#read 4, iclass 6, count 0 2006.231.07:31:09.05#ibcon#about to read 5, iclass 6, count 0 2006.231.07:31:09.05#ibcon#read 5, iclass 6, count 0 2006.231.07:31:09.05#ibcon#about to read 6, iclass 6, count 0 2006.231.07:31:09.05#ibcon#read 6, iclass 6, count 0 2006.231.07:31:09.05#ibcon#end of sib2, iclass 6, count 0 2006.231.07:31:09.05#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:31:09.05#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:31:09.05#ibcon#[25=USB\r\n] 2006.231.07:31:09.05#ibcon#*before write, iclass 6, count 0 2006.231.07:31:09.05#ibcon#enter sib2, iclass 6, count 0 2006.231.07:31:09.05#ibcon#flushed, iclass 6, count 0 2006.231.07:31:09.05#ibcon#about to write, iclass 6, count 0 2006.231.07:31:09.05#ibcon#wrote, iclass 6, count 0 2006.231.07:31:09.05#ibcon#about to read 3, iclass 6, count 0 2006.231.07:31:09.08#ibcon#read 3, iclass 6, count 0 2006.231.07:31:09.08#ibcon#about to read 4, iclass 6, count 0 2006.231.07:31:09.08#ibcon#read 4, iclass 6, count 0 2006.231.07:31:09.08#ibcon#about to read 5, iclass 6, count 0 2006.231.07:31:09.08#ibcon#read 5, iclass 6, count 0 2006.231.07:31:09.08#ibcon#about to read 6, iclass 6, count 0 2006.231.07:31:09.08#ibcon#read 6, iclass 6, count 0 2006.231.07:31:09.08#ibcon#end of sib2, iclass 6, count 0 2006.231.07:31:09.08#ibcon#*after write, iclass 6, count 0 2006.231.07:31:09.08#ibcon#*before return 0, iclass 6, count 0 2006.231.07:31:09.08#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:31:09.08#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:31:09.08#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:31:09.08#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:31:09.08$vc4f8/valo=4,832.99 2006.231.07:31:09.08#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.07:31:09.08#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.07:31:09.08#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:09.08#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:31:09.08#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:31:09.08#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:31:09.08#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:31:09.08#ibcon#first serial, iclass 10, count 0 2006.231.07:31:09.08#ibcon#enter sib2, iclass 10, count 0 2006.231.07:31:09.08#ibcon#flushed, iclass 10, count 0 2006.231.07:31:09.08#ibcon#about to write, iclass 10, count 0 2006.231.07:31:09.08#ibcon#wrote, iclass 10, count 0 2006.231.07:31:09.08#ibcon#about to read 3, iclass 10, count 0 2006.231.07:31:09.10#ibcon#read 3, iclass 10, count 0 2006.231.07:31:09.10#ibcon#about to read 4, iclass 10, count 0 2006.231.07:31:09.10#ibcon#read 4, iclass 10, count 0 2006.231.07:31:09.10#ibcon#about to read 5, iclass 10, count 0 2006.231.07:31:09.10#ibcon#read 5, iclass 10, count 0 2006.231.07:31:09.10#ibcon#about to read 6, iclass 10, count 0 2006.231.07:31:09.10#ibcon#read 6, iclass 10, count 0 2006.231.07:31:09.10#ibcon#end of sib2, iclass 10, count 0 2006.231.07:31:09.10#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:31:09.10#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:31:09.10#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:31:09.10#ibcon#*before write, iclass 10, count 0 2006.231.07:31:09.10#ibcon#enter sib2, iclass 10, count 0 2006.231.07:31:09.10#ibcon#flushed, iclass 10, count 0 2006.231.07:31:09.10#ibcon#about to write, iclass 10, count 0 2006.231.07:31:09.10#ibcon#wrote, iclass 10, count 0 2006.231.07:31:09.10#ibcon#about to read 3, iclass 10, count 0 2006.231.07:31:09.14#ibcon#read 3, iclass 10, count 0 2006.231.07:31:09.14#ibcon#about to read 4, iclass 10, count 0 2006.231.07:31:09.14#ibcon#read 4, iclass 10, count 0 2006.231.07:31:09.14#ibcon#about to read 5, iclass 10, count 0 2006.231.07:31:09.14#ibcon#read 5, iclass 10, count 0 2006.231.07:31:09.14#ibcon#about to read 6, iclass 10, count 0 2006.231.07:31:09.14#ibcon#read 6, iclass 10, count 0 2006.231.07:31:09.14#ibcon#end of sib2, iclass 10, count 0 2006.231.07:31:09.14#ibcon#*after write, iclass 10, count 0 2006.231.07:31:09.14#ibcon#*before return 0, iclass 10, count 0 2006.231.07:31:09.14#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:31:09.14#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:31:09.14#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:31:09.14#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:31:09.14$vc4f8/va=4,7 2006.231.07:31:09.14#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.07:31:09.14#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.07:31:09.14#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:09.14#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:31:09.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:31:09.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:31:09.20#ibcon#enter wrdev, iclass 12, count 2 2006.231.07:31:09.20#ibcon#first serial, iclass 12, count 2 2006.231.07:31:09.20#ibcon#enter sib2, iclass 12, count 2 2006.231.07:31:09.20#ibcon#flushed, iclass 12, count 2 2006.231.07:31:09.20#ibcon#about to write, iclass 12, count 2 2006.231.07:31:09.20#ibcon#wrote, iclass 12, count 2 2006.231.07:31:09.20#ibcon#about to read 3, iclass 12, count 2 2006.231.07:31:09.22#ibcon#read 3, iclass 12, count 2 2006.231.07:31:09.22#ibcon#about to read 4, iclass 12, count 2 2006.231.07:31:09.22#ibcon#read 4, iclass 12, count 2 2006.231.07:31:09.22#ibcon#about to read 5, iclass 12, count 2 2006.231.07:31:09.22#ibcon#read 5, iclass 12, count 2 2006.231.07:31:09.22#ibcon#about to read 6, iclass 12, count 2 2006.231.07:31:09.22#ibcon#read 6, iclass 12, count 2 2006.231.07:31:09.22#ibcon#end of sib2, iclass 12, count 2 2006.231.07:31:09.22#ibcon#*mode == 0, iclass 12, count 2 2006.231.07:31:09.22#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.07:31:09.22#ibcon#[25=AT04-07\r\n] 2006.231.07:31:09.22#ibcon#*before write, iclass 12, count 2 2006.231.07:31:09.22#ibcon#enter sib2, iclass 12, count 2 2006.231.07:31:09.22#ibcon#flushed, iclass 12, count 2 2006.231.07:31:09.22#ibcon#about to write, iclass 12, count 2 2006.231.07:31:09.22#ibcon#wrote, iclass 12, count 2 2006.231.07:31:09.22#ibcon#about to read 3, iclass 12, count 2 2006.231.07:31:09.25#ibcon#read 3, iclass 12, count 2 2006.231.07:31:09.25#ibcon#about to read 4, iclass 12, count 2 2006.231.07:31:09.25#ibcon#read 4, iclass 12, count 2 2006.231.07:31:09.25#ibcon#about to read 5, iclass 12, count 2 2006.231.07:31:09.25#ibcon#read 5, iclass 12, count 2 2006.231.07:31:09.25#ibcon#about to read 6, iclass 12, count 2 2006.231.07:31:09.25#ibcon#read 6, iclass 12, count 2 2006.231.07:31:09.25#ibcon#end of sib2, iclass 12, count 2 2006.231.07:31:09.25#ibcon#*after write, iclass 12, count 2 2006.231.07:31:09.25#ibcon#*before return 0, iclass 12, count 2 2006.231.07:31:09.25#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:31:09.25#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:31:09.25#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.07:31:09.25#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:09.25#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:31:09.37#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:31:09.37#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:31:09.37#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:31:09.37#ibcon#first serial, iclass 12, count 0 2006.231.07:31:09.37#ibcon#enter sib2, iclass 12, count 0 2006.231.07:31:09.37#ibcon#flushed, iclass 12, count 0 2006.231.07:31:09.37#ibcon#about to write, iclass 12, count 0 2006.231.07:31:09.37#ibcon#wrote, iclass 12, count 0 2006.231.07:31:09.37#ibcon#about to read 3, iclass 12, count 0 2006.231.07:31:09.39#ibcon#read 3, iclass 12, count 0 2006.231.07:31:09.39#ibcon#about to read 4, iclass 12, count 0 2006.231.07:31:09.39#ibcon#read 4, iclass 12, count 0 2006.231.07:31:09.39#ibcon#about to read 5, iclass 12, count 0 2006.231.07:31:09.39#ibcon#read 5, iclass 12, count 0 2006.231.07:31:09.39#ibcon#about to read 6, iclass 12, count 0 2006.231.07:31:09.39#ibcon#read 6, iclass 12, count 0 2006.231.07:31:09.39#ibcon#end of sib2, iclass 12, count 0 2006.231.07:31:09.39#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:31:09.39#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:31:09.39#ibcon#[25=USB\r\n] 2006.231.07:31:09.39#ibcon#*before write, iclass 12, count 0 2006.231.07:31:09.39#ibcon#enter sib2, iclass 12, count 0 2006.231.07:31:09.39#ibcon#flushed, iclass 12, count 0 2006.231.07:31:09.39#ibcon#about to write, iclass 12, count 0 2006.231.07:31:09.39#ibcon#wrote, iclass 12, count 0 2006.231.07:31:09.39#ibcon#about to read 3, iclass 12, count 0 2006.231.07:31:09.42#ibcon#read 3, iclass 12, count 0 2006.231.07:31:09.42#ibcon#about to read 4, iclass 12, count 0 2006.231.07:31:09.42#ibcon#read 4, iclass 12, count 0 2006.231.07:31:09.42#ibcon#about to read 5, iclass 12, count 0 2006.231.07:31:09.42#ibcon#read 5, iclass 12, count 0 2006.231.07:31:09.42#ibcon#about to read 6, iclass 12, count 0 2006.231.07:31:09.42#ibcon#read 6, iclass 12, count 0 2006.231.07:31:09.42#ibcon#end of sib2, iclass 12, count 0 2006.231.07:31:09.42#ibcon#*after write, iclass 12, count 0 2006.231.07:31:09.42#ibcon#*before return 0, iclass 12, count 0 2006.231.07:31:09.42#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:31:09.42#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:31:09.42#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:31:09.42#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:31:09.42$vc4f8/valo=5,652.99 2006.231.07:31:09.42#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.07:31:09.42#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.07:31:09.42#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:09.42#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:31:09.42#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:31:09.42#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:31:09.42#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:31:09.42#ibcon#first serial, iclass 14, count 0 2006.231.07:31:09.42#ibcon#enter sib2, iclass 14, count 0 2006.231.07:31:09.42#ibcon#flushed, iclass 14, count 0 2006.231.07:31:09.42#ibcon#about to write, iclass 14, count 0 2006.231.07:31:09.42#ibcon#wrote, iclass 14, count 0 2006.231.07:31:09.42#ibcon#about to read 3, iclass 14, count 0 2006.231.07:31:09.44#ibcon#read 3, iclass 14, count 0 2006.231.07:31:09.44#ibcon#about to read 4, iclass 14, count 0 2006.231.07:31:09.44#ibcon#read 4, iclass 14, count 0 2006.231.07:31:09.44#ibcon#about to read 5, iclass 14, count 0 2006.231.07:31:09.44#ibcon#read 5, iclass 14, count 0 2006.231.07:31:09.44#ibcon#about to read 6, iclass 14, count 0 2006.231.07:31:09.44#ibcon#read 6, iclass 14, count 0 2006.231.07:31:09.44#ibcon#end of sib2, iclass 14, count 0 2006.231.07:31:09.44#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:31:09.44#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:31:09.44#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:31:09.44#ibcon#*before write, iclass 14, count 0 2006.231.07:31:09.44#ibcon#enter sib2, iclass 14, count 0 2006.231.07:31:09.44#ibcon#flushed, iclass 14, count 0 2006.231.07:31:09.44#ibcon#about to write, iclass 14, count 0 2006.231.07:31:09.44#ibcon#wrote, iclass 14, count 0 2006.231.07:31:09.44#ibcon#about to read 3, iclass 14, count 0 2006.231.07:31:09.48#ibcon#read 3, iclass 14, count 0 2006.231.07:31:09.48#ibcon#about to read 4, iclass 14, count 0 2006.231.07:31:09.48#ibcon#read 4, iclass 14, count 0 2006.231.07:31:09.48#ibcon#about to read 5, iclass 14, count 0 2006.231.07:31:09.48#ibcon#read 5, iclass 14, count 0 2006.231.07:31:09.48#ibcon#about to read 6, iclass 14, count 0 2006.231.07:31:09.48#ibcon#read 6, iclass 14, count 0 2006.231.07:31:09.48#ibcon#end of sib2, iclass 14, count 0 2006.231.07:31:09.48#ibcon#*after write, iclass 14, count 0 2006.231.07:31:09.48#ibcon#*before return 0, iclass 14, count 0 2006.231.07:31:09.48#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:31:09.48#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:31:09.48#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:31:09.48#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:31:09.48$vc4f8/va=5,7 2006.231.07:31:09.48#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.07:31:09.48#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.07:31:09.48#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:09.48#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:31:09.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:31:09.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:31:09.54#ibcon#enter wrdev, iclass 16, count 2 2006.231.07:31:09.54#ibcon#first serial, iclass 16, count 2 2006.231.07:31:09.54#ibcon#enter sib2, iclass 16, count 2 2006.231.07:31:09.54#ibcon#flushed, iclass 16, count 2 2006.231.07:31:09.54#ibcon#about to write, iclass 16, count 2 2006.231.07:31:09.54#ibcon#wrote, iclass 16, count 2 2006.231.07:31:09.54#ibcon#about to read 3, iclass 16, count 2 2006.231.07:31:09.56#ibcon#read 3, iclass 16, count 2 2006.231.07:31:09.56#ibcon#about to read 4, iclass 16, count 2 2006.231.07:31:09.56#ibcon#read 4, iclass 16, count 2 2006.231.07:31:09.56#ibcon#about to read 5, iclass 16, count 2 2006.231.07:31:09.56#ibcon#read 5, iclass 16, count 2 2006.231.07:31:09.56#ibcon#about to read 6, iclass 16, count 2 2006.231.07:31:09.56#ibcon#read 6, iclass 16, count 2 2006.231.07:31:09.56#ibcon#end of sib2, iclass 16, count 2 2006.231.07:31:09.56#ibcon#*mode == 0, iclass 16, count 2 2006.231.07:31:09.56#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.07:31:09.56#ibcon#[25=AT05-07\r\n] 2006.231.07:31:09.56#ibcon#*before write, iclass 16, count 2 2006.231.07:31:09.56#ibcon#enter sib2, iclass 16, count 2 2006.231.07:31:09.56#ibcon#flushed, iclass 16, count 2 2006.231.07:31:09.56#ibcon#about to write, iclass 16, count 2 2006.231.07:31:09.56#ibcon#wrote, iclass 16, count 2 2006.231.07:31:09.56#ibcon#about to read 3, iclass 16, count 2 2006.231.07:31:09.60#ibcon#read 3, iclass 16, count 2 2006.231.07:31:09.60#ibcon#about to read 4, iclass 16, count 2 2006.231.07:31:09.60#ibcon#read 4, iclass 16, count 2 2006.231.07:31:09.60#ibcon#about to read 5, iclass 16, count 2 2006.231.07:31:09.60#ibcon#read 5, iclass 16, count 2 2006.231.07:31:09.60#ibcon#about to read 6, iclass 16, count 2 2006.231.07:31:09.60#ibcon#read 6, iclass 16, count 2 2006.231.07:31:09.60#ibcon#end of sib2, iclass 16, count 2 2006.231.07:31:09.60#ibcon#*after write, iclass 16, count 2 2006.231.07:31:09.60#ibcon#*before return 0, iclass 16, count 2 2006.231.07:31:09.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:31:09.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:31:09.60#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.07:31:09.60#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:09.60#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:31:09.71#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:31:09.71#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:31:09.71#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:31:09.71#ibcon#first serial, iclass 16, count 0 2006.231.07:31:09.71#ibcon#enter sib2, iclass 16, count 0 2006.231.07:31:09.71#ibcon#flushed, iclass 16, count 0 2006.231.07:31:09.71#ibcon#about to write, iclass 16, count 0 2006.231.07:31:09.71#ibcon#wrote, iclass 16, count 0 2006.231.07:31:09.71#ibcon#about to read 3, iclass 16, count 0 2006.231.07:31:09.73#ibcon#read 3, iclass 16, count 0 2006.231.07:31:09.73#ibcon#about to read 4, iclass 16, count 0 2006.231.07:31:09.73#ibcon#read 4, iclass 16, count 0 2006.231.07:31:09.73#ibcon#about to read 5, iclass 16, count 0 2006.231.07:31:09.73#ibcon#read 5, iclass 16, count 0 2006.231.07:31:09.73#ibcon#about to read 6, iclass 16, count 0 2006.231.07:31:09.73#ibcon#read 6, iclass 16, count 0 2006.231.07:31:09.73#ibcon#end of sib2, iclass 16, count 0 2006.231.07:31:09.73#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:31:09.73#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:31:09.73#ibcon#[25=USB\r\n] 2006.231.07:31:09.73#ibcon#*before write, iclass 16, count 0 2006.231.07:31:09.73#ibcon#enter sib2, iclass 16, count 0 2006.231.07:31:09.73#ibcon#flushed, iclass 16, count 0 2006.231.07:31:09.73#ibcon#about to write, iclass 16, count 0 2006.231.07:31:09.73#ibcon#wrote, iclass 16, count 0 2006.231.07:31:09.73#ibcon#about to read 3, iclass 16, count 0 2006.231.07:31:09.76#ibcon#read 3, iclass 16, count 0 2006.231.07:31:09.76#ibcon#about to read 4, iclass 16, count 0 2006.231.07:31:09.76#ibcon#read 4, iclass 16, count 0 2006.231.07:31:09.76#ibcon#about to read 5, iclass 16, count 0 2006.231.07:31:09.76#ibcon#read 5, iclass 16, count 0 2006.231.07:31:09.76#ibcon#about to read 6, iclass 16, count 0 2006.231.07:31:09.76#ibcon#read 6, iclass 16, count 0 2006.231.07:31:09.76#ibcon#end of sib2, iclass 16, count 0 2006.231.07:31:09.76#ibcon#*after write, iclass 16, count 0 2006.231.07:31:09.76#ibcon#*before return 0, iclass 16, count 0 2006.231.07:31:09.76#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:31:09.76#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:31:09.76#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:31:09.76#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:31:09.76$vc4f8/valo=6,772.99 2006.231.07:31:09.76#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.07:31:09.76#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.07:31:09.76#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:09.76#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:31:09.76#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:31:09.76#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:31:09.76#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:31:09.76#ibcon#first serial, iclass 18, count 0 2006.231.07:31:09.76#ibcon#enter sib2, iclass 18, count 0 2006.231.07:31:09.76#ibcon#flushed, iclass 18, count 0 2006.231.07:31:09.76#ibcon#about to write, iclass 18, count 0 2006.231.07:31:09.76#ibcon#wrote, iclass 18, count 0 2006.231.07:31:09.76#ibcon#about to read 3, iclass 18, count 0 2006.231.07:31:09.78#ibcon#read 3, iclass 18, count 0 2006.231.07:31:09.78#ibcon#about to read 4, iclass 18, count 0 2006.231.07:31:09.78#ibcon#read 4, iclass 18, count 0 2006.231.07:31:09.78#ibcon#about to read 5, iclass 18, count 0 2006.231.07:31:09.78#ibcon#read 5, iclass 18, count 0 2006.231.07:31:09.78#ibcon#about to read 6, iclass 18, count 0 2006.231.07:31:09.78#ibcon#read 6, iclass 18, count 0 2006.231.07:31:09.78#ibcon#end of sib2, iclass 18, count 0 2006.231.07:31:09.78#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:31:09.78#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:31:09.78#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:31:09.78#ibcon#*before write, iclass 18, count 0 2006.231.07:31:09.78#ibcon#enter sib2, iclass 18, count 0 2006.231.07:31:09.78#ibcon#flushed, iclass 18, count 0 2006.231.07:31:09.78#ibcon#about to write, iclass 18, count 0 2006.231.07:31:09.78#ibcon#wrote, iclass 18, count 0 2006.231.07:31:09.78#ibcon#about to read 3, iclass 18, count 0 2006.231.07:31:09.82#ibcon#read 3, iclass 18, count 0 2006.231.07:31:09.82#ibcon#about to read 4, iclass 18, count 0 2006.231.07:31:09.82#ibcon#read 4, iclass 18, count 0 2006.231.07:31:09.82#ibcon#about to read 5, iclass 18, count 0 2006.231.07:31:09.82#ibcon#read 5, iclass 18, count 0 2006.231.07:31:09.82#ibcon#about to read 6, iclass 18, count 0 2006.231.07:31:09.82#ibcon#read 6, iclass 18, count 0 2006.231.07:31:09.82#ibcon#end of sib2, iclass 18, count 0 2006.231.07:31:09.82#ibcon#*after write, iclass 18, count 0 2006.231.07:31:09.82#ibcon#*before return 0, iclass 18, count 0 2006.231.07:31:09.82#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:31:09.82#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:31:09.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:31:09.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:31:09.82$vc4f8/va=6,6 2006.231.07:31:09.82#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.07:31:09.82#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.07:31:09.82#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:09.82#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:31:09.88#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:31:09.88#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:31:09.88#ibcon#enter wrdev, iclass 20, count 2 2006.231.07:31:09.88#ibcon#first serial, iclass 20, count 2 2006.231.07:31:09.88#ibcon#enter sib2, iclass 20, count 2 2006.231.07:31:09.88#ibcon#flushed, iclass 20, count 2 2006.231.07:31:09.88#ibcon#about to write, iclass 20, count 2 2006.231.07:31:09.88#ibcon#wrote, iclass 20, count 2 2006.231.07:31:09.88#ibcon#about to read 3, iclass 20, count 2 2006.231.07:31:09.90#ibcon#read 3, iclass 20, count 2 2006.231.07:31:09.90#ibcon#about to read 4, iclass 20, count 2 2006.231.07:31:09.90#ibcon#read 4, iclass 20, count 2 2006.231.07:31:09.90#ibcon#about to read 5, iclass 20, count 2 2006.231.07:31:09.90#ibcon#read 5, iclass 20, count 2 2006.231.07:31:09.90#ibcon#about to read 6, iclass 20, count 2 2006.231.07:31:09.90#ibcon#read 6, iclass 20, count 2 2006.231.07:31:09.90#ibcon#end of sib2, iclass 20, count 2 2006.231.07:31:09.90#ibcon#*mode == 0, iclass 20, count 2 2006.231.07:31:09.90#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.07:31:09.90#ibcon#[25=AT06-06\r\n] 2006.231.07:31:09.90#ibcon#*before write, iclass 20, count 2 2006.231.07:31:09.90#ibcon#enter sib2, iclass 20, count 2 2006.231.07:31:09.90#ibcon#flushed, iclass 20, count 2 2006.231.07:31:09.90#ibcon#about to write, iclass 20, count 2 2006.231.07:31:09.90#ibcon#wrote, iclass 20, count 2 2006.231.07:31:09.90#ibcon#about to read 3, iclass 20, count 2 2006.231.07:31:09.93#ibcon#read 3, iclass 20, count 2 2006.231.07:31:09.93#ibcon#about to read 4, iclass 20, count 2 2006.231.07:31:09.93#ibcon#read 4, iclass 20, count 2 2006.231.07:31:09.93#ibcon#about to read 5, iclass 20, count 2 2006.231.07:31:09.93#ibcon#read 5, iclass 20, count 2 2006.231.07:31:09.93#ibcon#about to read 6, iclass 20, count 2 2006.231.07:31:09.93#ibcon#read 6, iclass 20, count 2 2006.231.07:31:09.93#ibcon#end of sib2, iclass 20, count 2 2006.231.07:31:09.93#ibcon#*after write, iclass 20, count 2 2006.231.07:31:09.93#ibcon#*before return 0, iclass 20, count 2 2006.231.07:31:09.93#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:31:09.93#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:31:09.93#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.07:31:09.93#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:09.93#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:31:09.94#abcon#<5=/06 4.6 7.7 30.80 851004.5\r\n> 2006.231.07:31:09.96#abcon#{5=INTERFACE CLEAR} 2006.231.07:31:10.02#abcon#[5=S1D000X0/0*\r\n] 2006.231.07:31:10.05#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:31:10.05#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:31:10.05#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:31:10.05#ibcon#first serial, iclass 20, count 0 2006.231.07:31:10.05#ibcon#enter sib2, iclass 20, count 0 2006.231.07:31:10.05#ibcon#flushed, iclass 20, count 0 2006.231.07:31:10.05#ibcon#about to write, iclass 20, count 0 2006.231.07:31:10.05#ibcon#wrote, iclass 20, count 0 2006.231.07:31:10.05#ibcon#about to read 3, iclass 20, count 0 2006.231.07:31:10.07#ibcon#read 3, iclass 20, count 0 2006.231.07:31:10.07#ibcon#about to read 4, iclass 20, count 0 2006.231.07:31:10.07#ibcon#read 4, iclass 20, count 0 2006.231.07:31:10.07#ibcon#about to read 5, iclass 20, count 0 2006.231.07:31:10.07#ibcon#read 5, iclass 20, count 0 2006.231.07:31:10.07#ibcon#about to read 6, iclass 20, count 0 2006.231.07:31:10.07#ibcon#read 6, iclass 20, count 0 2006.231.07:31:10.07#ibcon#end of sib2, iclass 20, count 0 2006.231.07:31:10.07#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:31:10.07#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:31:10.07#ibcon#[25=USB\r\n] 2006.231.07:31:10.07#ibcon#*before write, iclass 20, count 0 2006.231.07:31:10.07#ibcon#enter sib2, iclass 20, count 0 2006.231.07:31:10.07#ibcon#flushed, iclass 20, count 0 2006.231.07:31:10.07#ibcon#about to write, iclass 20, count 0 2006.231.07:31:10.07#ibcon#wrote, iclass 20, count 0 2006.231.07:31:10.07#ibcon#about to read 3, iclass 20, count 0 2006.231.07:31:10.10#ibcon#read 3, iclass 20, count 0 2006.231.07:31:10.10#ibcon#about to read 4, iclass 20, count 0 2006.231.07:31:10.10#ibcon#read 4, iclass 20, count 0 2006.231.07:31:10.10#ibcon#about to read 5, iclass 20, count 0 2006.231.07:31:10.10#ibcon#read 5, iclass 20, count 0 2006.231.07:31:10.10#ibcon#about to read 6, iclass 20, count 0 2006.231.07:31:10.10#ibcon#read 6, iclass 20, count 0 2006.231.07:31:10.10#ibcon#end of sib2, iclass 20, count 0 2006.231.07:31:10.10#ibcon#*after write, iclass 20, count 0 2006.231.07:31:10.10#ibcon#*before return 0, iclass 20, count 0 2006.231.07:31:10.10#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:31:10.10#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:31:10.10#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:31:10.10#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:31:10.10$vc4f8/valo=7,832.99 2006.231.07:31:10.10#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:31:10.10#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:31:10.10#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:10.10#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:31:10.10#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:31:10.10#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:31:10.10#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:31:10.10#ibcon#first serial, iclass 26, count 0 2006.231.07:31:10.10#ibcon#enter sib2, iclass 26, count 0 2006.231.07:31:10.10#ibcon#flushed, iclass 26, count 0 2006.231.07:31:10.10#ibcon#about to write, iclass 26, count 0 2006.231.07:31:10.10#ibcon#wrote, iclass 26, count 0 2006.231.07:31:10.10#ibcon#about to read 3, iclass 26, count 0 2006.231.07:31:10.12#ibcon#read 3, iclass 26, count 0 2006.231.07:31:10.12#ibcon#about to read 4, iclass 26, count 0 2006.231.07:31:10.12#ibcon#read 4, iclass 26, count 0 2006.231.07:31:10.12#ibcon#about to read 5, iclass 26, count 0 2006.231.07:31:10.12#ibcon#read 5, iclass 26, count 0 2006.231.07:31:10.12#ibcon#about to read 6, iclass 26, count 0 2006.231.07:31:10.12#ibcon#read 6, iclass 26, count 0 2006.231.07:31:10.12#ibcon#end of sib2, iclass 26, count 0 2006.231.07:31:10.12#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:31:10.12#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:31:10.12#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:31:10.12#ibcon#*before write, iclass 26, count 0 2006.231.07:31:10.12#ibcon#enter sib2, iclass 26, count 0 2006.231.07:31:10.12#ibcon#flushed, iclass 26, count 0 2006.231.07:31:10.12#ibcon#about to write, iclass 26, count 0 2006.231.07:31:10.12#ibcon#wrote, iclass 26, count 0 2006.231.07:31:10.12#ibcon#about to read 3, iclass 26, count 0 2006.231.07:31:10.16#ibcon#read 3, iclass 26, count 0 2006.231.07:31:10.16#ibcon#about to read 4, iclass 26, count 0 2006.231.07:31:10.16#ibcon#read 4, iclass 26, count 0 2006.231.07:31:10.16#ibcon#about to read 5, iclass 26, count 0 2006.231.07:31:10.16#ibcon#read 5, iclass 26, count 0 2006.231.07:31:10.16#ibcon#about to read 6, iclass 26, count 0 2006.231.07:31:10.16#ibcon#read 6, iclass 26, count 0 2006.231.07:31:10.16#ibcon#end of sib2, iclass 26, count 0 2006.231.07:31:10.16#ibcon#*after write, iclass 26, count 0 2006.231.07:31:10.16#ibcon#*before return 0, iclass 26, count 0 2006.231.07:31:10.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:31:10.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:31:10.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:31:10.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:31:10.16$vc4f8/va=7,6 2006.231.07:31:10.16#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.07:31:10.16#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.07:31:10.16#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:10.16#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:31:10.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:31:10.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:31:10.22#ibcon#enter wrdev, iclass 28, count 2 2006.231.07:31:10.22#ibcon#first serial, iclass 28, count 2 2006.231.07:31:10.22#ibcon#enter sib2, iclass 28, count 2 2006.231.07:31:10.22#ibcon#flushed, iclass 28, count 2 2006.231.07:31:10.22#ibcon#about to write, iclass 28, count 2 2006.231.07:31:10.22#ibcon#wrote, iclass 28, count 2 2006.231.07:31:10.22#ibcon#about to read 3, iclass 28, count 2 2006.231.07:31:10.24#ibcon#read 3, iclass 28, count 2 2006.231.07:31:10.24#ibcon#about to read 4, iclass 28, count 2 2006.231.07:31:10.24#ibcon#read 4, iclass 28, count 2 2006.231.07:31:10.24#ibcon#about to read 5, iclass 28, count 2 2006.231.07:31:10.24#ibcon#read 5, iclass 28, count 2 2006.231.07:31:10.24#ibcon#about to read 6, iclass 28, count 2 2006.231.07:31:10.24#ibcon#read 6, iclass 28, count 2 2006.231.07:31:10.24#ibcon#end of sib2, iclass 28, count 2 2006.231.07:31:10.24#ibcon#*mode == 0, iclass 28, count 2 2006.231.07:31:10.24#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.07:31:10.24#ibcon#[25=AT07-06\r\n] 2006.231.07:31:10.24#ibcon#*before write, iclass 28, count 2 2006.231.07:31:10.24#ibcon#enter sib2, iclass 28, count 2 2006.231.07:31:10.24#ibcon#flushed, iclass 28, count 2 2006.231.07:31:10.24#ibcon#about to write, iclass 28, count 2 2006.231.07:31:10.24#ibcon#wrote, iclass 28, count 2 2006.231.07:31:10.24#ibcon#about to read 3, iclass 28, count 2 2006.231.07:31:10.27#ibcon#read 3, iclass 28, count 2 2006.231.07:31:10.27#ibcon#about to read 4, iclass 28, count 2 2006.231.07:31:10.27#ibcon#read 4, iclass 28, count 2 2006.231.07:31:10.27#ibcon#about to read 5, iclass 28, count 2 2006.231.07:31:10.27#ibcon#read 5, iclass 28, count 2 2006.231.07:31:10.27#ibcon#about to read 6, iclass 28, count 2 2006.231.07:31:10.27#ibcon#read 6, iclass 28, count 2 2006.231.07:31:10.27#ibcon#end of sib2, iclass 28, count 2 2006.231.07:31:10.27#ibcon#*after write, iclass 28, count 2 2006.231.07:31:10.27#ibcon#*before return 0, iclass 28, count 2 2006.231.07:31:10.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:31:10.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:31:10.27#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.07:31:10.27#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:10.27#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:31:10.39#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:31:10.39#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:31:10.39#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:31:10.39#ibcon#first serial, iclass 28, count 0 2006.231.07:31:10.39#ibcon#enter sib2, iclass 28, count 0 2006.231.07:31:10.39#ibcon#flushed, iclass 28, count 0 2006.231.07:31:10.39#ibcon#about to write, iclass 28, count 0 2006.231.07:31:10.39#ibcon#wrote, iclass 28, count 0 2006.231.07:31:10.39#ibcon#about to read 3, iclass 28, count 0 2006.231.07:31:10.41#ibcon#read 3, iclass 28, count 0 2006.231.07:31:10.41#ibcon#about to read 4, iclass 28, count 0 2006.231.07:31:10.41#ibcon#read 4, iclass 28, count 0 2006.231.07:31:10.41#ibcon#about to read 5, iclass 28, count 0 2006.231.07:31:10.41#ibcon#read 5, iclass 28, count 0 2006.231.07:31:10.41#ibcon#about to read 6, iclass 28, count 0 2006.231.07:31:10.41#ibcon#read 6, iclass 28, count 0 2006.231.07:31:10.41#ibcon#end of sib2, iclass 28, count 0 2006.231.07:31:10.41#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:31:10.41#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:31:10.41#ibcon#[25=USB\r\n] 2006.231.07:31:10.41#ibcon#*before write, iclass 28, count 0 2006.231.07:31:10.41#ibcon#enter sib2, iclass 28, count 0 2006.231.07:31:10.41#ibcon#flushed, iclass 28, count 0 2006.231.07:31:10.41#ibcon#about to write, iclass 28, count 0 2006.231.07:31:10.41#ibcon#wrote, iclass 28, count 0 2006.231.07:31:10.41#ibcon#about to read 3, iclass 28, count 0 2006.231.07:31:10.44#ibcon#read 3, iclass 28, count 0 2006.231.07:31:10.44#ibcon#about to read 4, iclass 28, count 0 2006.231.07:31:10.44#ibcon#read 4, iclass 28, count 0 2006.231.07:31:10.44#ibcon#about to read 5, iclass 28, count 0 2006.231.07:31:10.44#ibcon#read 5, iclass 28, count 0 2006.231.07:31:10.44#ibcon#about to read 6, iclass 28, count 0 2006.231.07:31:10.44#ibcon#read 6, iclass 28, count 0 2006.231.07:31:10.44#ibcon#end of sib2, iclass 28, count 0 2006.231.07:31:10.44#ibcon#*after write, iclass 28, count 0 2006.231.07:31:10.44#ibcon#*before return 0, iclass 28, count 0 2006.231.07:31:10.44#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:31:10.44#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:31:10.44#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:31:10.44#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:31:10.44$vc4f8/valo=8,852.99 2006.231.07:31:10.44#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.07:31:10.44#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.07:31:10.44#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:10.44#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:31:10.44#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:31:10.44#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:31:10.44#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:31:10.44#ibcon#first serial, iclass 30, count 0 2006.231.07:31:10.44#ibcon#enter sib2, iclass 30, count 0 2006.231.07:31:10.44#ibcon#flushed, iclass 30, count 0 2006.231.07:31:10.44#ibcon#about to write, iclass 30, count 0 2006.231.07:31:10.44#ibcon#wrote, iclass 30, count 0 2006.231.07:31:10.44#ibcon#about to read 3, iclass 30, count 0 2006.231.07:31:10.46#ibcon#read 3, iclass 30, count 0 2006.231.07:31:10.46#ibcon#about to read 4, iclass 30, count 0 2006.231.07:31:10.46#ibcon#read 4, iclass 30, count 0 2006.231.07:31:10.46#ibcon#about to read 5, iclass 30, count 0 2006.231.07:31:10.46#ibcon#read 5, iclass 30, count 0 2006.231.07:31:10.46#ibcon#about to read 6, iclass 30, count 0 2006.231.07:31:10.46#ibcon#read 6, iclass 30, count 0 2006.231.07:31:10.46#ibcon#end of sib2, iclass 30, count 0 2006.231.07:31:10.46#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:31:10.46#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:31:10.46#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:31:10.46#ibcon#*before write, iclass 30, count 0 2006.231.07:31:10.46#ibcon#enter sib2, iclass 30, count 0 2006.231.07:31:10.46#ibcon#flushed, iclass 30, count 0 2006.231.07:31:10.46#ibcon#about to write, iclass 30, count 0 2006.231.07:31:10.46#ibcon#wrote, iclass 30, count 0 2006.231.07:31:10.46#ibcon#about to read 3, iclass 30, count 0 2006.231.07:31:10.50#ibcon#read 3, iclass 30, count 0 2006.231.07:31:10.50#ibcon#about to read 4, iclass 30, count 0 2006.231.07:31:10.50#ibcon#read 4, iclass 30, count 0 2006.231.07:31:10.51#ibcon#about to read 5, iclass 30, count 0 2006.231.07:31:10.51#ibcon#read 5, iclass 30, count 0 2006.231.07:31:10.51#ibcon#about to read 6, iclass 30, count 0 2006.231.07:31:10.51#ibcon#read 6, iclass 30, count 0 2006.231.07:31:10.51#ibcon#end of sib2, iclass 30, count 0 2006.231.07:31:10.51#ibcon#*after write, iclass 30, count 0 2006.231.07:31:10.51#ibcon#*before return 0, iclass 30, count 0 2006.231.07:31:10.51#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:31:10.51#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:31:10.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:31:10.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:31:10.51$vc4f8/va=8,6 2006.231.07:31:10.51#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.07:31:10.51#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.07:31:10.51#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:10.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:31:10.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:31:10.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:31:10.55#ibcon#enter wrdev, iclass 32, count 2 2006.231.07:31:10.55#ibcon#first serial, iclass 32, count 2 2006.231.07:31:10.55#ibcon#enter sib2, iclass 32, count 2 2006.231.07:31:10.55#ibcon#flushed, iclass 32, count 2 2006.231.07:31:10.55#ibcon#about to write, iclass 32, count 2 2006.231.07:31:10.55#ibcon#wrote, iclass 32, count 2 2006.231.07:31:10.55#ibcon#about to read 3, iclass 32, count 2 2006.231.07:31:10.57#ibcon#read 3, iclass 32, count 2 2006.231.07:31:10.57#ibcon#about to read 4, iclass 32, count 2 2006.231.07:31:10.57#ibcon#read 4, iclass 32, count 2 2006.231.07:31:10.57#ibcon#about to read 5, iclass 32, count 2 2006.231.07:31:10.57#ibcon#read 5, iclass 32, count 2 2006.231.07:31:10.57#ibcon#about to read 6, iclass 32, count 2 2006.231.07:31:10.57#ibcon#read 6, iclass 32, count 2 2006.231.07:31:10.57#ibcon#end of sib2, iclass 32, count 2 2006.231.07:31:10.57#ibcon#*mode == 0, iclass 32, count 2 2006.231.07:31:10.57#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.07:31:10.57#ibcon#[25=AT08-06\r\n] 2006.231.07:31:10.57#ibcon#*before write, iclass 32, count 2 2006.231.07:31:10.57#ibcon#enter sib2, iclass 32, count 2 2006.231.07:31:10.57#ibcon#flushed, iclass 32, count 2 2006.231.07:31:10.57#ibcon#about to write, iclass 32, count 2 2006.231.07:31:10.57#ibcon#wrote, iclass 32, count 2 2006.231.07:31:10.57#ibcon#about to read 3, iclass 32, count 2 2006.231.07:31:10.60#ibcon#read 3, iclass 32, count 2 2006.231.07:31:10.60#ibcon#about to read 4, iclass 32, count 2 2006.231.07:31:10.60#ibcon#read 4, iclass 32, count 2 2006.231.07:31:10.60#ibcon#about to read 5, iclass 32, count 2 2006.231.07:31:10.60#ibcon#read 5, iclass 32, count 2 2006.231.07:31:10.60#ibcon#about to read 6, iclass 32, count 2 2006.231.07:31:10.60#ibcon#read 6, iclass 32, count 2 2006.231.07:31:10.60#ibcon#end of sib2, iclass 32, count 2 2006.231.07:31:10.60#ibcon#*after write, iclass 32, count 2 2006.231.07:31:10.60#ibcon#*before return 0, iclass 32, count 2 2006.231.07:31:10.60#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:31:10.60#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:31:10.60#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.07:31:10.60#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:10.60#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:31:10.72#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:31:10.72#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:31:10.72#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:31:10.72#ibcon#first serial, iclass 32, count 0 2006.231.07:31:10.72#ibcon#enter sib2, iclass 32, count 0 2006.231.07:31:10.72#ibcon#flushed, iclass 32, count 0 2006.231.07:31:10.72#ibcon#about to write, iclass 32, count 0 2006.231.07:31:10.72#ibcon#wrote, iclass 32, count 0 2006.231.07:31:10.72#ibcon#about to read 3, iclass 32, count 0 2006.231.07:31:10.74#ibcon#read 3, iclass 32, count 0 2006.231.07:31:10.74#ibcon#about to read 4, iclass 32, count 0 2006.231.07:31:10.74#ibcon#read 4, iclass 32, count 0 2006.231.07:31:10.74#ibcon#about to read 5, iclass 32, count 0 2006.231.07:31:10.74#ibcon#read 5, iclass 32, count 0 2006.231.07:31:10.74#ibcon#about to read 6, iclass 32, count 0 2006.231.07:31:10.74#ibcon#read 6, iclass 32, count 0 2006.231.07:31:10.74#ibcon#end of sib2, iclass 32, count 0 2006.231.07:31:10.74#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:31:10.74#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:31:10.74#ibcon#[25=USB\r\n] 2006.231.07:31:10.74#ibcon#*before write, iclass 32, count 0 2006.231.07:31:10.74#ibcon#enter sib2, iclass 32, count 0 2006.231.07:31:10.74#ibcon#flushed, iclass 32, count 0 2006.231.07:31:10.74#ibcon#about to write, iclass 32, count 0 2006.231.07:31:10.74#ibcon#wrote, iclass 32, count 0 2006.231.07:31:10.74#ibcon#about to read 3, iclass 32, count 0 2006.231.07:31:10.77#ibcon#read 3, iclass 32, count 0 2006.231.07:31:10.77#ibcon#about to read 4, iclass 32, count 0 2006.231.07:31:10.77#ibcon#read 4, iclass 32, count 0 2006.231.07:31:10.77#ibcon#about to read 5, iclass 32, count 0 2006.231.07:31:10.77#ibcon#read 5, iclass 32, count 0 2006.231.07:31:10.77#ibcon#about to read 6, iclass 32, count 0 2006.231.07:31:10.77#ibcon#read 6, iclass 32, count 0 2006.231.07:31:10.77#ibcon#end of sib2, iclass 32, count 0 2006.231.07:31:10.77#ibcon#*after write, iclass 32, count 0 2006.231.07:31:10.77#ibcon#*before return 0, iclass 32, count 0 2006.231.07:31:10.77#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:31:10.77#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:31:10.77#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:31:10.77#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:31:10.77$vc4f8/vblo=1,632.99 2006.231.07:31:10.77#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.07:31:10.77#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.07:31:10.77#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:10.77#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:31:10.77#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:31:10.77#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:31:10.77#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:31:10.77#ibcon#first serial, iclass 34, count 0 2006.231.07:31:10.77#ibcon#enter sib2, iclass 34, count 0 2006.231.07:31:10.77#ibcon#flushed, iclass 34, count 0 2006.231.07:31:10.77#ibcon#about to write, iclass 34, count 0 2006.231.07:31:10.77#ibcon#wrote, iclass 34, count 0 2006.231.07:31:10.77#ibcon#about to read 3, iclass 34, count 0 2006.231.07:31:10.79#ibcon#read 3, iclass 34, count 0 2006.231.07:31:10.79#ibcon#about to read 4, iclass 34, count 0 2006.231.07:31:10.79#ibcon#read 4, iclass 34, count 0 2006.231.07:31:10.79#ibcon#about to read 5, iclass 34, count 0 2006.231.07:31:10.79#ibcon#read 5, iclass 34, count 0 2006.231.07:31:10.79#ibcon#about to read 6, iclass 34, count 0 2006.231.07:31:10.79#ibcon#read 6, iclass 34, count 0 2006.231.07:31:10.79#ibcon#end of sib2, iclass 34, count 0 2006.231.07:31:10.79#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:31:10.79#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:31:10.79#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:31:10.79#ibcon#*before write, iclass 34, count 0 2006.231.07:31:10.79#ibcon#enter sib2, iclass 34, count 0 2006.231.07:31:10.79#ibcon#flushed, iclass 34, count 0 2006.231.07:31:10.79#ibcon#about to write, iclass 34, count 0 2006.231.07:31:10.79#ibcon#wrote, iclass 34, count 0 2006.231.07:31:10.79#ibcon#about to read 3, iclass 34, count 0 2006.231.07:31:10.83#ibcon#read 3, iclass 34, count 0 2006.231.07:31:10.83#ibcon#about to read 4, iclass 34, count 0 2006.231.07:31:10.83#ibcon#read 4, iclass 34, count 0 2006.231.07:31:10.83#ibcon#about to read 5, iclass 34, count 0 2006.231.07:31:10.83#ibcon#read 5, iclass 34, count 0 2006.231.07:31:10.83#ibcon#about to read 6, iclass 34, count 0 2006.231.07:31:10.83#ibcon#read 6, iclass 34, count 0 2006.231.07:31:10.83#ibcon#end of sib2, iclass 34, count 0 2006.231.07:31:10.83#ibcon#*after write, iclass 34, count 0 2006.231.07:31:10.83#ibcon#*before return 0, iclass 34, count 0 2006.231.07:31:10.83#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:31:10.83#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:31:10.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:31:10.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:31:10.83$vc4f8/vb=1,4 2006.231.07:31:10.83#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.07:31:10.83#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.07:31:10.83#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:10.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:31:10.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:31:10.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:31:10.83#ibcon#enter wrdev, iclass 36, count 2 2006.231.07:31:10.83#ibcon#first serial, iclass 36, count 2 2006.231.07:31:10.83#ibcon#enter sib2, iclass 36, count 2 2006.231.07:31:10.83#ibcon#flushed, iclass 36, count 2 2006.231.07:31:10.83#ibcon#about to write, iclass 36, count 2 2006.231.07:31:10.83#ibcon#wrote, iclass 36, count 2 2006.231.07:31:10.83#ibcon#about to read 3, iclass 36, count 2 2006.231.07:31:10.85#ibcon#read 3, iclass 36, count 2 2006.231.07:31:10.85#ibcon#about to read 4, iclass 36, count 2 2006.231.07:31:10.85#ibcon#read 4, iclass 36, count 2 2006.231.07:31:10.85#ibcon#about to read 5, iclass 36, count 2 2006.231.07:31:10.85#ibcon#read 5, iclass 36, count 2 2006.231.07:31:10.85#ibcon#about to read 6, iclass 36, count 2 2006.231.07:31:10.85#ibcon#read 6, iclass 36, count 2 2006.231.07:31:10.85#ibcon#end of sib2, iclass 36, count 2 2006.231.07:31:10.85#ibcon#*mode == 0, iclass 36, count 2 2006.231.07:31:10.85#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.07:31:10.85#ibcon#[27=AT01-04\r\n] 2006.231.07:31:10.85#ibcon#*before write, iclass 36, count 2 2006.231.07:31:10.85#ibcon#enter sib2, iclass 36, count 2 2006.231.07:31:10.85#ibcon#flushed, iclass 36, count 2 2006.231.07:31:10.85#ibcon#about to write, iclass 36, count 2 2006.231.07:31:10.85#ibcon#wrote, iclass 36, count 2 2006.231.07:31:10.85#ibcon#about to read 3, iclass 36, count 2 2006.231.07:31:10.88#ibcon#read 3, iclass 36, count 2 2006.231.07:31:10.88#ibcon#about to read 4, iclass 36, count 2 2006.231.07:31:10.88#ibcon#read 4, iclass 36, count 2 2006.231.07:31:10.88#ibcon#about to read 5, iclass 36, count 2 2006.231.07:31:10.88#ibcon#read 5, iclass 36, count 2 2006.231.07:31:10.88#ibcon#about to read 6, iclass 36, count 2 2006.231.07:31:10.88#ibcon#read 6, iclass 36, count 2 2006.231.07:31:10.88#ibcon#end of sib2, iclass 36, count 2 2006.231.07:31:10.88#ibcon#*after write, iclass 36, count 2 2006.231.07:31:10.88#ibcon#*before return 0, iclass 36, count 2 2006.231.07:31:10.88#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:31:10.88#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:31:10.88#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.07:31:10.88#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:10.88#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:31:11.00#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:31:11.00#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:31:11.00#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:31:11.00#ibcon#first serial, iclass 36, count 0 2006.231.07:31:11.00#ibcon#enter sib2, iclass 36, count 0 2006.231.07:31:11.00#ibcon#flushed, iclass 36, count 0 2006.231.07:31:11.00#ibcon#about to write, iclass 36, count 0 2006.231.07:31:11.00#ibcon#wrote, iclass 36, count 0 2006.231.07:31:11.00#ibcon#about to read 3, iclass 36, count 0 2006.231.07:31:11.02#ibcon#read 3, iclass 36, count 0 2006.231.07:31:11.02#ibcon#about to read 4, iclass 36, count 0 2006.231.07:31:11.02#ibcon#read 4, iclass 36, count 0 2006.231.07:31:11.02#ibcon#about to read 5, iclass 36, count 0 2006.231.07:31:11.02#ibcon#read 5, iclass 36, count 0 2006.231.07:31:11.02#ibcon#about to read 6, iclass 36, count 0 2006.231.07:31:11.02#ibcon#read 6, iclass 36, count 0 2006.231.07:31:11.02#ibcon#end of sib2, iclass 36, count 0 2006.231.07:31:11.02#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:31:11.02#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:31:11.02#ibcon#[27=USB\r\n] 2006.231.07:31:11.02#ibcon#*before write, iclass 36, count 0 2006.231.07:31:11.02#ibcon#enter sib2, iclass 36, count 0 2006.231.07:31:11.02#ibcon#flushed, iclass 36, count 0 2006.231.07:31:11.02#ibcon#about to write, iclass 36, count 0 2006.231.07:31:11.02#ibcon#wrote, iclass 36, count 0 2006.231.07:31:11.02#ibcon#about to read 3, iclass 36, count 0 2006.231.07:31:11.05#ibcon#read 3, iclass 36, count 0 2006.231.07:31:11.05#ibcon#about to read 4, iclass 36, count 0 2006.231.07:31:11.05#ibcon#read 4, iclass 36, count 0 2006.231.07:31:11.05#ibcon#about to read 5, iclass 36, count 0 2006.231.07:31:11.05#ibcon#read 5, iclass 36, count 0 2006.231.07:31:11.05#ibcon#about to read 6, iclass 36, count 0 2006.231.07:31:11.05#ibcon#read 6, iclass 36, count 0 2006.231.07:31:11.05#ibcon#end of sib2, iclass 36, count 0 2006.231.07:31:11.05#ibcon#*after write, iclass 36, count 0 2006.231.07:31:11.05#ibcon#*before return 0, iclass 36, count 0 2006.231.07:31:11.05#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:31:11.05#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:31:11.05#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:31:11.05#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:31:11.05$vc4f8/vblo=2,640.99 2006.231.07:31:11.05#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.07:31:11.05#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.07:31:11.05#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:11.05#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:31:11.05#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:31:11.05#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:31:11.05#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:31:11.05#ibcon#first serial, iclass 38, count 0 2006.231.07:31:11.05#ibcon#enter sib2, iclass 38, count 0 2006.231.07:31:11.05#ibcon#flushed, iclass 38, count 0 2006.231.07:31:11.05#ibcon#about to write, iclass 38, count 0 2006.231.07:31:11.05#ibcon#wrote, iclass 38, count 0 2006.231.07:31:11.05#ibcon#about to read 3, iclass 38, count 0 2006.231.07:31:11.07#ibcon#read 3, iclass 38, count 0 2006.231.07:31:11.07#ibcon#about to read 4, iclass 38, count 0 2006.231.07:31:11.07#ibcon#read 4, iclass 38, count 0 2006.231.07:31:11.07#ibcon#about to read 5, iclass 38, count 0 2006.231.07:31:11.07#ibcon#read 5, iclass 38, count 0 2006.231.07:31:11.07#ibcon#about to read 6, iclass 38, count 0 2006.231.07:31:11.07#ibcon#read 6, iclass 38, count 0 2006.231.07:31:11.07#ibcon#end of sib2, iclass 38, count 0 2006.231.07:31:11.07#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:31:11.07#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:31:11.07#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:31:11.07#ibcon#*before write, iclass 38, count 0 2006.231.07:31:11.07#ibcon#enter sib2, iclass 38, count 0 2006.231.07:31:11.07#ibcon#flushed, iclass 38, count 0 2006.231.07:31:11.07#ibcon#about to write, iclass 38, count 0 2006.231.07:31:11.07#ibcon#wrote, iclass 38, count 0 2006.231.07:31:11.07#ibcon#about to read 3, iclass 38, count 0 2006.231.07:31:11.11#ibcon#read 3, iclass 38, count 0 2006.231.07:31:11.11#ibcon#about to read 4, iclass 38, count 0 2006.231.07:31:11.11#ibcon#read 4, iclass 38, count 0 2006.231.07:31:11.11#ibcon#about to read 5, iclass 38, count 0 2006.231.07:31:11.11#ibcon#read 5, iclass 38, count 0 2006.231.07:31:11.11#ibcon#about to read 6, iclass 38, count 0 2006.231.07:31:11.11#ibcon#read 6, iclass 38, count 0 2006.231.07:31:11.11#ibcon#end of sib2, iclass 38, count 0 2006.231.07:31:11.11#ibcon#*after write, iclass 38, count 0 2006.231.07:31:11.11#ibcon#*before return 0, iclass 38, count 0 2006.231.07:31:11.11#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:31:11.11#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:31:11.11#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:31:11.11#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:31:11.11$vc4f8/vb=2,4 2006.231.07:31:11.11#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.07:31:11.11#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.07:31:11.11#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:11.11#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:31:11.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:31:11.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:31:11.17#ibcon#enter wrdev, iclass 40, count 2 2006.231.07:31:11.17#ibcon#first serial, iclass 40, count 2 2006.231.07:31:11.17#ibcon#enter sib2, iclass 40, count 2 2006.231.07:31:11.17#ibcon#flushed, iclass 40, count 2 2006.231.07:31:11.17#ibcon#about to write, iclass 40, count 2 2006.231.07:31:11.17#ibcon#wrote, iclass 40, count 2 2006.231.07:31:11.17#ibcon#about to read 3, iclass 40, count 2 2006.231.07:31:11.19#ibcon#read 3, iclass 40, count 2 2006.231.07:31:11.19#ibcon#about to read 4, iclass 40, count 2 2006.231.07:31:11.19#ibcon#read 4, iclass 40, count 2 2006.231.07:31:11.19#ibcon#about to read 5, iclass 40, count 2 2006.231.07:31:11.19#ibcon#read 5, iclass 40, count 2 2006.231.07:31:11.19#ibcon#about to read 6, iclass 40, count 2 2006.231.07:31:11.19#ibcon#read 6, iclass 40, count 2 2006.231.07:31:11.19#ibcon#end of sib2, iclass 40, count 2 2006.231.07:31:11.19#ibcon#*mode == 0, iclass 40, count 2 2006.231.07:31:11.19#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.07:31:11.19#ibcon#[27=AT02-04\r\n] 2006.231.07:31:11.19#ibcon#*before write, iclass 40, count 2 2006.231.07:31:11.19#ibcon#enter sib2, iclass 40, count 2 2006.231.07:31:11.19#ibcon#flushed, iclass 40, count 2 2006.231.07:31:11.19#ibcon#about to write, iclass 40, count 2 2006.231.07:31:11.19#ibcon#wrote, iclass 40, count 2 2006.231.07:31:11.19#ibcon#about to read 3, iclass 40, count 2 2006.231.07:31:11.22#ibcon#read 3, iclass 40, count 2 2006.231.07:31:11.22#ibcon#about to read 4, iclass 40, count 2 2006.231.07:31:11.22#ibcon#read 4, iclass 40, count 2 2006.231.07:31:11.22#ibcon#about to read 5, iclass 40, count 2 2006.231.07:31:11.22#ibcon#read 5, iclass 40, count 2 2006.231.07:31:11.22#ibcon#about to read 6, iclass 40, count 2 2006.231.07:31:11.22#ibcon#read 6, iclass 40, count 2 2006.231.07:31:11.22#ibcon#end of sib2, iclass 40, count 2 2006.231.07:31:11.22#ibcon#*after write, iclass 40, count 2 2006.231.07:31:11.22#ibcon#*before return 0, iclass 40, count 2 2006.231.07:31:11.22#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:31:11.22#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:31:11.22#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.07:31:11.22#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:11.22#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:31:11.34#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:31:11.34#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:31:11.34#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:31:11.34#ibcon#first serial, iclass 40, count 0 2006.231.07:31:11.34#ibcon#enter sib2, iclass 40, count 0 2006.231.07:31:11.34#ibcon#flushed, iclass 40, count 0 2006.231.07:31:11.34#ibcon#about to write, iclass 40, count 0 2006.231.07:31:11.34#ibcon#wrote, iclass 40, count 0 2006.231.07:31:11.34#ibcon#about to read 3, iclass 40, count 0 2006.231.07:31:11.36#ibcon#read 3, iclass 40, count 0 2006.231.07:31:11.36#ibcon#about to read 4, iclass 40, count 0 2006.231.07:31:11.36#ibcon#read 4, iclass 40, count 0 2006.231.07:31:11.36#ibcon#about to read 5, iclass 40, count 0 2006.231.07:31:11.36#ibcon#read 5, iclass 40, count 0 2006.231.07:31:11.36#ibcon#about to read 6, iclass 40, count 0 2006.231.07:31:11.36#ibcon#read 6, iclass 40, count 0 2006.231.07:31:11.36#ibcon#end of sib2, iclass 40, count 0 2006.231.07:31:11.36#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:31:11.36#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:31:11.36#ibcon#[27=USB\r\n] 2006.231.07:31:11.36#ibcon#*before write, iclass 40, count 0 2006.231.07:31:11.36#ibcon#enter sib2, iclass 40, count 0 2006.231.07:31:11.36#ibcon#flushed, iclass 40, count 0 2006.231.07:31:11.36#ibcon#about to write, iclass 40, count 0 2006.231.07:31:11.36#ibcon#wrote, iclass 40, count 0 2006.231.07:31:11.36#ibcon#about to read 3, iclass 40, count 0 2006.231.07:31:11.39#ibcon#read 3, iclass 40, count 0 2006.231.07:31:11.39#ibcon#about to read 4, iclass 40, count 0 2006.231.07:31:11.39#ibcon#read 4, iclass 40, count 0 2006.231.07:31:11.39#ibcon#about to read 5, iclass 40, count 0 2006.231.07:31:11.39#ibcon#read 5, iclass 40, count 0 2006.231.07:31:11.39#ibcon#about to read 6, iclass 40, count 0 2006.231.07:31:11.39#ibcon#read 6, iclass 40, count 0 2006.231.07:31:11.39#ibcon#end of sib2, iclass 40, count 0 2006.231.07:31:11.39#ibcon#*after write, iclass 40, count 0 2006.231.07:31:11.39#ibcon#*before return 0, iclass 40, count 0 2006.231.07:31:11.39#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:31:11.39#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:31:11.39#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:31:11.39#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:31:11.39$vc4f8/vblo=3,656.99 2006.231.07:31:11.39#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.07:31:11.39#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.07:31:11.39#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:11.39#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:31:11.39#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:31:11.39#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:31:11.39#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:31:11.39#ibcon#first serial, iclass 4, count 0 2006.231.07:31:11.39#ibcon#enter sib2, iclass 4, count 0 2006.231.07:31:11.39#ibcon#flushed, iclass 4, count 0 2006.231.07:31:11.39#ibcon#about to write, iclass 4, count 0 2006.231.07:31:11.39#ibcon#wrote, iclass 4, count 0 2006.231.07:31:11.39#ibcon#about to read 3, iclass 4, count 0 2006.231.07:31:11.42#ibcon#read 3, iclass 4, count 0 2006.231.07:31:11.42#ibcon#about to read 4, iclass 4, count 0 2006.231.07:31:11.42#ibcon#read 4, iclass 4, count 0 2006.231.07:31:11.42#ibcon#about to read 5, iclass 4, count 0 2006.231.07:31:11.42#ibcon#read 5, iclass 4, count 0 2006.231.07:31:11.42#ibcon#about to read 6, iclass 4, count 0 2006.231.07:31:11.42#ibcon#read 6, iclass 4, count 0 2006.231.07:31:11.42#ibcon#end of sib2, iclass 4, count 0 2006.231.07:31:11.42#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:31:11.42#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:31:11.42#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:31:11.42#ibcon#*before write, iclass 4, count 0 2006.231.07:31:11.42#ibcon#enter sib2, iclass 4, count 0 2006.231.07:31:11.42#ibcon#flushed, iclass 4, count 0 2006.231.07:31:11.42#ibcon#about to write, iclass 4, count 0 2006.231.07:31:11.42#ibcon#wrote, iclass 4, count 0 2006.231.07:31:11.42#ibcon#about to read 3, iclass 4, count 0 2006.231.07:31:11.46#ibcon#read 3, iclass 4, count 0 2006.231.07:31:11.46#ibcon#about to read 4, iclass 4, count 0 2006.231.07:31:11.46#ibcon#read 4, iclass 4, count 0 2006.231.07:31:11.46#ibcon#about to read 5, iclass 4, count 0 2006.231.07:31:11.46#ibcon#read 5, iclass 4, count 0 2006.231.07:31:11.46#ibcon#about to read 6, iclass 4, count 0 2006.231.07:31:11.46#ibcon#read 6, iclass 4, count 0 2006.231.07:31:11.46#ibcon#end of sib2, iclass 4, count 0 2006.231.07:31:11.46#ibcon#*after write, iclass 4, count 0 2006.231.07:31:11.46#ibcon#*before return 0, iclass 4, count 0 2006.231.07:31:11.46#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:31:11.46#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:31:11.46#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:31:11.46#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:31:11.46$vc4f8/vb=3,4 2006.231.07:31:11.46#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.07:31:11.46#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.07:31:11.46#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:11.46#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:31:11.50#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:31:11.50#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:31:11.50#ibcon#enter wrdev, iclass 6, count 2 2006.231.07:31:11.50#ibcon#first serial, iclass 6, count 2 2006.231.07:31:11.50#ibcon#enter sib2, iclass 6, count 2 2006.231.07:31:11.50#ibcon#flushed, iclass 6, count 2 2006.231.07:31:11.50#ibcon#about to write, iclass 6, count 2 2006.231.07:31:11.50#ibcon#wrote, iclass 6, count 2 2006.231.07:31:11.50#ibcon#about to read 3, iclass 6, count 2 2006.231.07:31:11.53#ibcon#read 3, iclass 6, count 2 2006.231.07:31:11.53#ibcon#about to read 4, iclass 6, count 2 2006.231.07:31:11.53#ibcon#read 4, iclass 6, count 2 2006.231.07:31:11.53#ibcon#about to read 5, iclass 6, count 2 2006.231.07:31:11.53#ibcon#read 5, iclass 6, count 2 2006.231.07:31:11.53#ibcon#about to read 6, iclass 6, count 2 2006.231.07:31:11.53#ibcon#read 6, iclass 6, count 2 2006.231.07:31:11.53#ibcon#end of sib2, iclass 6, count 2 2006.231.07:31:11.53#ibcon#*mode == 0, iclass 6, count 2 2006.231.07:31:11.53#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.07:31:11.53#ibcon#[27=AT03-04\r\n] 2006.231.07:31:11.53#ibcon#*before write, iclass 6, count 2 2006.231.07:31:11.53#ibcon#enter sib2, iclass 6, count 2 2006.231.07:31:11.53#ibcon#flushed, iclass 6, count 2 2006.231.07:31:11.53#ibcon#about to write, iclass 6, count 2 2006.231.07:31:11.53#ibcon#wrote, iclass 6, count 2 2006.231.07:31:11.53#ibcon#about to read 3, iclass 6, count 2 2006.231.07:31:11.56#ibcon#read 3, iclass 6, count 2 2006.231.07:31:11.56#ibcon#about to read 4, iclass 6, count 2 2006.231.07:31:11.56#ibcon#read 4, iclass 6, count 2 2006.231.07:31:11.56#ibcon#about to read 5, iclass 6, count 2 2006.231.07:31:11.56#ibcon#read 5, iclass 6, count 2 2006.231.07:31:11.56#ibcon#about to read 6, iclass 6, count 2 2006.231.07:31:11.56#ibcon#read 6, iclass 6, count 2 2006.231.07:31:11.56#ibcon#end of sib2, iclass 6, count 2 2006.231.07:31:11.56#ibcon#*after write, iclass 6, count 2 2006.231.07:31:11.56#ibcon#*before return 0, iclass 6, count 2 2006.231.07:31:11.56#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:31:11.56#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:31:11.56#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.07:31:11.56#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:11.56#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:31:11.68#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:31:11.68#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:31:11.68#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:31:11.68#ibcon#first serial, iclass 6, count 0 2006.231.07:31:11.68#ibcon#enter sib2, iclass 6, count 0 2006.231.07:31:11.68#ibcon#flushed, iclass 6, count 0 2006.231.07:31:11.68#ibcon#about to write, iclass 6, count 0 2006.231.07:31:11.68#ibcon#wrote, iclass 6, count 0 2006.231.07:31:11.68#ibcon#about to read 3, iclass 6, count 0 2006.231.07:31:11.70#ibcon#read 3, iclass 6, count 0 2006.231.07:31:11.70#ibcon#about to read 4, iclass 6, count 0 2006.231.07:31:11.70#ibcon#read 4, iclass 6, count 0 2006.231.07:31:11.70#ibcon#about to read 5, iclass 6, count 0 2006.231.07:31:11.70#ibcon#read 5, iclass 6, count 0 2006.231.07:31:11.70#ibcon#about to read 6, iclass 6, count 0 2006.231.07:31:11.70#ibcon#read 6, iclass 6, count 0 2006.231.07:31:11.70#ibcon#end of sib2, iclass 6, count 0 2006.231.07:31:11.70#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:31:11.70#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:31:11.70#ibcon#[27=USB\r\n] 2006.231.07:31:11.70#ibcon#*before write, iclass 6, count 0 2006.231.07:31:11.70#ibcon#enter sib2, iclass 6, count 0 2006.231.07:31:11.70#ibcon#flushed, iclass 6, count 0 2006.231.07:31:11.70#ibcon#about to write, iclass 6, count 0 2006.231.07:31:11.70#ibcon#wrote, iclass 6, count 0 2006.231.07:31:11.70#ibcon#about to read 3, iclass 6, count 0 2006.231.07:31:11.73#ibcon#read 3, iclass 6, count 0 2006.231.07:31:11.73#ibcon#about to read 4, iclass 6, count 0 2006.231.07:31:11.73#ibcon#read 4, iclass 6, count 0 2006.231.07:31:11.73#ibcon#about to read 5, iclass 6, count 0 2006.231.07:31:11.73#ibcon#read 5, iclass 6, count 0 2006.231.07:31:11.73#ibcon#about to read 6, iclass 6, count 0 2006.231.07:31:11.73#ibcon#read 6, iclass 6, count 0 2006.231.07:31:11.73#ibcon#end of sib2, iclass 6, count 0 2006.231.07:31:11.73#ibcon#*after write, iclass 6, count 0 2006.231.07:31:11.73#ibcon#*before return 0, iclass 6, count 0 2006.231.07:31:11.73#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:31:11.73#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:31:11.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:31:11.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:31:11.73$vc4f8/vblo=4,712.99 2006.231.07:31:11.73#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.07:31:11.73#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.07:31:11.73#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:11.73#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:31:11.73#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:31:11.73#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:31:11.73#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:31:11.73#ibcon#first serial, iclass 10, count 0 2006.231.07:31:11.73#ibcon#enter sib2, iclass 10, count 0 2006.231.07:31:11.73#ibcon#flushed, iclass 10, count 0 2006.231.07:31:11.73#ibcon#about to write, iclass 10, count 0 2006.231.07:31:11.73#ibcon#wrote, iclass 10, count 0 2006.231.07:31:11.73#ibcon#about to read 3, iclass 10, count 0 2006.231.07:31:11.75#ibcon#read 3, iclass 10, count 0 2006.231.07:31:11.75#ibcon#about to read 4, iclass 10, count 0 2006.231.07:31:11.75#ibcon#read 4, iclass 10, count 0 2006.231.07:31:11.75#ibcon#about to read 5, iclass 10, count 0 2006.231.07:31:11.75#ibcon#read 5, iclass 10, count 0 2006.231.07:31:11.75#ibcon#about to read 6, iclass 10, count 0 2006.231.07:31:11.75#ibcon#read 6, iclass 10, count 0 2006.231.07:31:11.75#ibcon#end of sib2, iclass 10, count 0 2006.231.07:31:11.75#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:31:11.75#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:31:11.75#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:31:11.75#ibcon#*before write, iclass 10, count 0 2006.231.07:31:11.75#ibcon#enter sib2, iclass 10, count 0 2006.231.07:31:11.75#ibcon#flushed, iclass 10, count 0 2006.231.07:31:11.75#ibcon#about to write, iclass 10, count 0 2006.231.07:31:11.75#ibcon#wrote, iclass 10, count 0 2006.231.07:31:11.75#ibcon#about to read 3, iclass 10, count 0 2006.231.07:31:11.79#ibcon#read 3, iclass 10, count 0 2006.231.07:31:11.79#ibcon#about to read 4, iclass 10, count 0 2006.231.07:31:11.79#ibcon#read 4, iclass 10, count 0 2006.231.07:31:11.79#ibcon#about to read 5, iclass 10, count 0 2006.231.07:31:11.79#ibcon#read 5, iclass 10, count 0 2006.231.07:31:11.79#ibcon#about to read 6, iclass 10, count 0 2006.231.07:31:11.79#ibcon#read 6, iclass 10, count 0 2006.231.07:31:11.79#ibcon#end of sib2, iclass 10, count 0 2006.231.07:31:11.79#ibcon#*after write, iclass 10, count 0 2006.231.07:31:11.79#ibcon#*before return 0, iclass 10, count 0 2006.231.07:31:11.79#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:31:11.79#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:31:11.79#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:31:11.79#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:31:11.79$vc4f8/vb=4,4 2006.231.07:31:11.79#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.07:31:11.79#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.07:31:11.79#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:11.79#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:31:11.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:31:11.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:31:11.85#ibcon#enter wrdev, iclass 12, count 2 2006.231.07:31:11.85#ibcon#first serial, iclass 12, count 2 2006.231.07:31:11.85#ibcon#enter sib2, iclass 12, count 2 2006.231.07:31:11.85#ibcon#flushed, iclass 12, count 2 2006.231.07:31:11.85#ibcon#about to write, iclass 12, count 2 2006.231.07:31:11.85#ibcon#wrote, iclass 12, count 2 2006.231.07:31:11.85#ibcon#about to read 3, iclass 12, count 2 2006.231.07:31:11.87#ibcon#read 3, iclass 12, count 2 2006.231.07:31:11.87#ibcon#about to read 4, iclass 12, count 2 2006.231.07:31:11.87#ibcon#read 4, iclass 12, count 2 2006.231.07:31:11.87#ibcon#about to read 5, iclass 12, count 2 2006.231.07:31:11.87#ibcon#read 5, iclass 12, count 2 2006.231.07:31:11.87#ibcon#about to read 6, iclass 12, count 2 2006.231.07:31:11.87#ibcon#read 6, iclass 12, count 2 2006.231.07:31:11.87#ibcon#end of sib2, iclass 12, count 2 2006.231.07:31:11.87#ibcon#*mode == 0, iclass 12, count 2 2006.231.07:31:11.87#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.07:31:11.87#ibcon#[27=AT04-04\r\n] 2006.231.07:31:11.87#ibcon#*before write, iclass 12, count 2 2006.231.07:31:11.87#ibcon#enter sib2, iclass 12, count 2 2006.231.07:31:11.87#ibcon#flushed, iclass 12, count 2 2006.231.07:31:11.87#ibcon#about to write, iclass 12, count 2 2006.231.07:31:11.87#ibcon#wrote, iclass 12, count 2 2006.231.07:31:11.87#ibcon#about to read 3, iclass 12, count 2 2006.231.07:31:11.90#ibcon#read 3, iclass 12, count 2 2006.231.07:31:11.90#ibcon#about to read 4, iclass 12, count 2 2006.231.07:31:11.90#ibcon#read 4, iclass 12, count 2 2006.231.07:31:11.90#ibcon#about to read 5, iclass 12, count 2 2006.231.07:31:11.90#ibcon#read 5, iclass 12, count 2 2006.231.07:31:11.90#ibcon#about to read 6, iclass 12, count 2 2006.231.07:31:11.90#ibcon#read 6, iclass 12, count 2 2006.231.07:31:11.90#ibcon#end of sib2, iclass 12, count 2 2006.231.07:31:11.90#ibcon#*after write, iclass 12, count 2 2006.231.07:31:11.90#ibcon#*before return 0, iclass 12, count 2 2006.231.07:31:11.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:31:11.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:31:11.90#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.07:31:11.90#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:11.90#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:31:12.02#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:31:12.02#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:31:12.02#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:31:12.02#ibcon#first serial, iclass 12, count 0 2006.231.07:31:12.02#ibcon#enter sib2, iclass 12, count 0 2006.231.07:31:12.02#ibcon#flushed, iclass 12, count 0 2006.231.07:31:12.02#ibcon#about to write, iclass 12, count 0 2006.231.07:31:12.02#ibcon#wrote, iclass 12, count 0 2006.231.07:31:12.02#ibcon#about to read 3, iclass 12, count 0 2006.231.07:31:12.04#ibcon#read 3, iclass 12, count 0 2006.231.07:31:12.04#ibcon#about to read 4, iclass 12, count 0 2006.231.07:31:12.04#ibcon#read 4, iclass 12, count 0 2006.231.07:31:12.04#ibcon#about to read 5, iclass 12, count 0 2006.231.07:31:12.04#ibcon#read 5, iclass 12, count 0 2006.231.07:31:12.04#ibcon#about to read 6, iclass 12, count 0 2006.231.07:31:12.04#ibcon#read 6, iclass 12, count 0 2006.231.07:31:12.04#ibcon#end of sib2, iclass 12, count 0 2006.231.07:31:12.04#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:31:12.04#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:31:12.04#ibcon#[27=USB\r\n] 2006.231.07:31:12.04#ibcon#*before write, iclass 12, count 0 2006.231.07:31:12.04#ibcon#enter sib2, iclass 12, count 0 2006.231.07:31:12.04#ibcon#flushed, iclass 12, count 0 2006.231.07:31:12.04#ibcon#about to write, iclass 12, count 0 2006.231.07:31:12.04#ibcon#wrote, iclass 12, count 0 2006.231.07:31:12.04#ibcon#about to read 3, iclass 12, count 0 2006.231.07:31:12.07#ibcon#read 3, iclass 12, count 0 2006.231.07:31:12.07#ibcon#about to read 4, iclass 12, count 0 2006.231.07:31:12.07#ibcon#read 4, iclass 12, count 0 2006.231.07:31:12.07#ibcon#about to read 5, iclass 12, count 0 2006.231.07:31:12.07#ibcon#read 5, iclass 12, count 0 2006.231.07:31:12.07#ibcon#about to read 6, iclass 12, count 0 2006.231.07:31:12.07#ibcon#read 6, iclass 12, count 0 2006.231.07:31:12.07#ibcon#end of sib2, iclass 12, count 0 2006.231.07:31:12.07#ibcon#*after write, iclass 12, count 0 2006.231.07:31:12.07#ibcon#*before return 0, iclass 12, count 0 2006.231.07:31:12.07#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:31:12.07#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:31:12.07#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:31:12.07#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:31:12.07$vc4f8/vblo=5,744.99 2006.231.07:31:12.07#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.07:31:12.07#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.07:31:12.07#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:12.07#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:31:12.07#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:31:12.07#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:31:12.07#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:31:12.07#ibcon#first serial, iclass 14, count 0 2006.231.07:31:12.07#ibcon#enter sib2, iclass 14, count 0 2006.231.07:31:12.07#ibcon#flushed, iclass 14, count 0 2006.231.07:31:12.07#ibcon#about to write, iclass 14, count 0 2006.231.07:31:12.07#ibcon#wrote, iclass 14, count 0 2006.231.07:31:12.07#ibcon#about to read 3, iclass 14, count 0 2006.231.07:31:12.09#ibcon#read 3, iclass 14, count 0 2006.231.07:31:12.09#ibcon#about to read 4, iclass 14, count 0 2006.231.07:31:12.09#ibcon#read 4, iclass 14, count 0 2006.231.07:31:12.09#ibcon#about to read 5, iclass 14, count 0 2006.231.07:31:12.09#ibcon#read 5, iclass 14, count 0 2006.231.07:31:12.09#ibcon#about to read 6, iclass 14, count 0 2006.231.07:31:12.09#ibcon#read 6, iclass 14, count 0 2006.231.07:31:12.09#ibcon#end of sib2, iclass 14, count 0 2006.231.07:31:12.09#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:31:12.09#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:31:12.09#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:31:12.09#ibcon#*before write, iclass 14, count 0 2006.231.07:31:12.09#ibcon#enter sib2, iclass 14, count 0 2006.231.07:31:12.09#ibcon#flushed, iclass 14, count 0 2006.231.07:31:12.09#ibcon#about to write, iclass 14, count 0 2006.231.07:31:12.09#ibcon#wrote, iclass 14, count 0 2006.231.07:31:12.09#ibcon#about to read 3, iclass 14, count 0 2006.231.07:31:12.13#ibcon#read 3, iclass 14, count 0 2006.231.07:31:12.13#ibcon#about to read 4, iclass 14, count 0 2006.231.07:31:12.13#ibcon#read 4, iclass 14, count 0 2006.231.07:31:12.13#ibcon#about to read 5, iclass 14, count 0 2006.231.07:31:12.13#ibcon#read 5, iclass 14, count 0 2006.231.07:31:12.13#ibcon#about to read 6, iclass 14, count 0 2006.231.07:31:12.13#ibcon#read 6, iclass 14, count 0 2006.231.07:31:12.13#ibcon#end of sib2, iclass 14, count 0 2006.231.07:31:12.13#ibcon#*after write, iclass 14, count 0 2006.231.07:31:12.13#ibcon#*before return 0, iclass 14, count 0 2006.231.07:31:12.13#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:31:12.13#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:31:12.13#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:31:12.13#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:31:12.13$vc4f8/vb=5,3 2006.231.07:31:12.13#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.07:31:12.13#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.07:31:12.13#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:12.13#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:31:12.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:31:12.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:31:12.19#ibcon#enter wrdev, iclass 16, count 2 2006.231.07:31:12.19#ibcon#first serial, iclass 16, count 2 2006.231.07:31:12.19#ibcon#enter sib2, iclass 16, count 2 2006.231.07:31:12.19#ibcon#flushed, iclass 16, count 2 2006.231.07:31:12.19#ibcon#about to write, iclass 16, count 2 2006.231.07:31:12.19#ibcon#wrote, iclass 16, count 2 2006.231.07:31:12.19#ibcon#about to read 3, iclass 16, count 2 2006.231.07:31:12.21#ibcon#read 3, iclass 16, count 2 2006.231.07:31:12.21#ibcon#about to read 4, iclass 16, count 2 2006.231.07:31:12.21#ibcon#read 4, iclass 16, count 2 2006.231.07:31:12.21#ibcon#about to read 5, iclass 16, count 2 2006.231.07:31:12.21#ibcon#read 5, iclass 16, count 2 2006.231.07:31:12.21#ibcon#about to read 6, iclass 16, count 2 2006.231.07:31:12.21#ibcon#read 6, iclass 16, count 2 2006.231.07:31:12.21#ibcon#end of sib2, iclass 16, count 2 2006.231.07:31:12.21#ibcon#*mode == 0, iclass 16, count 2 2006.231.07:31:12.21#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.07:31:12.21#ibcon#[27=AT05-03\r\n] 2006.231.07:31:12.21#ibcon#*before write, iclass 16, count 2 2006.231.07:31:12.21#ibcon#enter sib2, iclass 16, count 2 2006.231.07:31:12.21#ibcon#flushed, iclass 16, count 2 2006.231.07:31:12.21#ibcon#about to write, iclass 16, count 2 2006.231.07:31:12.21#ibcon#wrote, iclass 16, count 2 2006.231.07:31:12.21#ibcon#about to read 3, iclass 16, count 2 2006.231.07:31:12.24#ibcon#read 3, iclass 16, count 2 2006.231.07:31:12.24#ibcon#about to read 4, iclass 16, count 2 2006.231.07:31:12.24#ibcon#read 4, iclass 16, count 2 2006.231.07:31:12.24#ibcon#about to read 5, iclass 16, count 2 2006.231.07:31:12.24#ibcon#read 5, iclass 16, count 2 2006.231.07:31:12.24#ibcon#about to read 6, iclass 16, count 2 2006.231.07:31:12.24#ibcon#read 6, iclass 16, count 2 2006.231.07:31:12.24#ibcon#end of sib2, iclass 16, count 2 2006.231.07:31:12.24#ibcon#*after write, iclass 16, count 2 2006.231.07:31:12.24#ibcon#*before return 0, iclass 16, count 2 2006.231.07:31:12.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:31:12.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:31:12.24#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.07:31:12.24#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:12.24#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:31:12.36#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:31:12.36#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:31:12.36#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:31:12.36#ibcon#first serial, iclass 16, count 0 2006.231.07:31:12.36#ibcon#enter sib2, iclass 16, count 0 2006.231.07:31:12.36#ibcon#flushed, iclass 16, count 0 2006.231.07:31:12.36#ibcon#about to write, iclass 16, count 0 2006.231.07:31:12.36#ibcon#wrote, iclass 16, count 0 2006.231.07:31:12.36#ibcon#about to read 3, iclass 16, count 0 2006.231.07:31:12.38#ibcon#read 3, iclass 16, count 0 2006.231.07:31:12.38#ibcon#about to read 4, iclass 16, count 0 2006.231.07:31:12.38#ibcon#read 4, iclass 16, count 0 2006.231.07:31:12.38#ibcon#about to read 5, iclass 16, count 0 2006.231.07:31:12.38#ibcon#read 5, iclass 16, count 0 2006.231.07:31:12.38#ibcon#about to read 6, iclass 16, count 0 2006.231.07:31:12.38#ibcon#read 6, iclass 16, count 0 2006.231.07:31:12.38#ibcon#end of sib2, iclass 16, count 0 2006.231.07:31:12.38#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:31:12.38#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:31:12.38#ibcon#[27=USB\r\n] 2006.231.07:31:12.38#ibcon#*before write, iclass 16, count 0 2006.231.07:31:12.38#ibcon#enter sib2, iclass 16, count 0 2006.231.07:31:12.38#ibcon#flushed, iclass 16, count 0 2006.231.07:31:12.38#ibcon#about to write, iclass 16, count 0 2006.231.07:31:12.38#ibcon#wrote, iclass 16, count 0 2006.231.07:31:12.38#ibcon#about to read 3, iclass 16, count 0 2006.231.07:31:12.41#ibcon#read 3, iclass 16, count 0 2006.231.07:31:12.41#ibcon#about to read 4, iclass 16, count 0 2006.231.07:31:12.41#ibcon#read 4, iclass 16, count 0 2006.231.07:31:12.41#ibcon#about to read 5, iclass 16, count 0 2006.231.07:31:12.41#ibcon#read 5, iclass 16, count 0 2006.231.07:31:12.41#ibcon#about to read 6, iclass 16, count 0 2006.231.07:31:12.41#ibcon#read 6, iclass 16, count 0 2006.231.07:31:12.41#ibcon#end of sib2, iclass 16, count 0 2006.231.07:31:12.41#ibcon#*after write, iclass 16, count 0 2006.231.07:31:12.41#ibcon#*before return 0, iclass 16, count 0 2006.231.07:31:12.41#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:31:12.41#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:31:12.41#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:31:12.41#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:31:12.41$vc4f8/vblo=6,752.99 2006.231.07:31:12.41#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.07:31:12.41#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.07:31:12.41#ibcon#ireg 17 cls_cnt 0 2006.231.07:31:12.41#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:31:12.41#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:31:12.41#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:31:12.41#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:31:12.41#ibcon#first serial, iclass 18, count 0 2006.231.07:31:12.41#ibcon#enter sib2, iclass 18, count 0 2006.231.07:31:12.41#ibcon#flushed, iclass 18, count 0 2006.231.07:31:12.41#ibcon#about to write, iclass 18, count 0 2006.231.07:31:12.41#ibcon#wrote, iclass 18, count 0 2006.231.07:31:12.41#ibcon#about to read 3, iclass 18, count 0 2006.231.07:31:12.44#ibcon#read 3, iclass 18, count 0 2006.231.07:31:12.44#ibcon#about to read 4, iclass 18, count 0 2006.231.07:31:12.44#ibcon#read 4, iclass 18, count 0 2006.231.07:31:12.44#ibcon#about to read 5, iclass 18, count 0 2006.231.07:31:12.44#ibcon#read 5, iclass 18, count 0 2006.231.07:31:12.44#ibcon#about to read 6, iclass 18, count 0 2006.231.07:31:12.44#ibcon#read 6, iclass 18, count 0 2006.231.07:31:12.44#ibcon#end of sib2, iclass 18, count 0 2006.231.07:31:12.44#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:31:12.44#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:31:12.44#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:31:12.44#ibcon#*before write, iclass 18, count 0 2006.231.07:31:12.44#ibcon#enter sib2, iclass 18, count 0 2006.231.07:31:12.44#ibcon#flushed, iclass 18, count 0 2006.231.07:31:12.44#ibcon#about to write, iclass 18, count 0 2006.231.07:31:12.44#ibcon#wrote, iclass 18, count 0 2006.231.07:31:12.44#ibcon#about to read 3, iclass 18, count 0 2006.231.07:31:12.47#ibcon#read 3, iclass 18, count 0 2006.231.07:31:12.47#ibcon#about to read 4, iclass 18, count 0 2006.231.07:31:12.47#ibcon#read 4, iclass 18, count 0 2006.231.07:31:12.47#ibcon#about to read 5, iclass 18, count 0 2006.231.07:31:12.47#ibcon#read 5, iclass 18, count 0 2006.231.07:31:12.47#ibcon#about to read 6, iclass 18, count 0 2006.231.07:31:12.47#ibcon#read 6, iclass 18, count 0 2006.231.07:31:12.47#ibcon#end of sib2, iclass 18, count 0 2006.231.07:31:12.47#ibcon#*after write, iclass 18, count 0 2006.231.07:31:12.47#ibcon#*before return 0, iclass 18, count 0 2006.231.07:31:12.47#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:31:12.47#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:31:12.47#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:31:12.47#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:31:12.47$vc4f8/vb=6,4 2006.231.07:31:12.47#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.07:31:12.47#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.07:31:12.47#ibcon#ireg 11 cls_cnt 2 2006.231.07:31:12.47#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:31:12.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:31:12.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:31:12.53#ibcon#enter wrdev, iclass 20, count 2 2006.231.07:31:12.53#ibcon#first serial, iclass 20, count 2 2006.231.07:31:12.53#ibcon#enter sib2, iclass 20, count 2 2006.231.07:31:12.53#ibcon#flushed, iclass 20, count 2 2006.231.07:31:12.53#ibcon#about to write, iclass 20, count 2 2006.231.07:31:12.53#ibcon#wrote, iclass 20, count 2 2006.231.07:31:12.53#ibcon#about to read 3, iclass 20, count 2 2006.231.07:31:12.55#ibcon#read 3, iclass 20, count 2 2006.231.07:31:12.55#ibcon#about to read 4, iclass 20, count 2 2006.231.07:31:12.55#ibcon#read 4, iclass 20, count 2 2006.231.07:31:12.55#ibcon#about to read 5, iclass 20, count 2 2006.231.07:31:12.55#ibcon#read 5, iclass 20, count 2 2006.231.07:31:12.55#ibcon#about to read 6, iclass 20, count 2 2006.231.07:31:12.55#ibcon#read 6, iclass 20, count 2 2006.231.07:31:12.55#ibcon#end of sib2, iclass 20, count 2 2006.231.07:31:12.55#ibcon#*mode == 0, iclass 20, count 2 2006.231.07:31:12.55#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.07:31:12.55#ibcon#[27=AT06-04\r\n] 2006.231.07:31:12.55#ibcon#*before write, iclass 20, count 2 2006.231.07:31:12.55#ibcon#enter sib2, iclass 20, count 2 2006.231.07:31:12.55#ibcon#flushed, iclass 20, count 2 2006.231.07:31:12.55#ibcon#about to write, iclass 20, count 2 2006.231.07:31:12.55#ibcon#wrote, iclass 20, count 2 2006.231.07:31:12.55#ibcon#about to read 3, iclass 20, count 2 2006.231.07:31:12.58#ibcon#read 3, iclass 20, count 2 2006.231.07:31:12.58#ibcon#about to read 4, iclass 20, count 2 2006.231.07:31:12.58#ibcon#read 4, iclass 20, count 2 2006.231.07:31:12.58#ibcon#about to read 5, iclass 20, count 2 2006.231.07:31:12.58#ibcon#read 5, iclass 20, count 2 2006.231.07:31:12.58#ibcon#about to read 6, iclass 20, count 2 2006.231.07:31:12.58#ibcon#read 6, iclass 20, count 2 2006.231.07:31:12.58#ibcon#end of sib2, iclass 20, count 2 2006.231.07:31:12.58#ibcon#*after write, iclass 20, count 2 2006.231.07:31:12.58#ibcon#*before return 0, iclass 20, count 2 2006.231.07:31:12.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:31:12.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:31:12.58#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.07:31:12.58#ibcon#ireg 7 cls_cnt 0 2006.231.07:31:12.58#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:31:12.70#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:31:12.70#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:31:12.70#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:31:12.70#ibcon#first serial, iclass 20, count 0 2006.231.07:31:12.70#ibcon#enter sib2, iclass 20, count 0 2006.231.07:31:12.70#ibcon#flushed, iclass 20, count 0 2006.231.07:31:12.70#ibcon#about to write, iclass 20, count 0 2006.231.07:31:12.70#ibcon#wrote, iclass 20, count 0 2006.231.07:31:12.70#ibcon#about to read 3, iclass 20, count 0 2006.231.07:31:12.72#ibcon#read 3, iclass 20, count 0 2006.231.07:31:12.72#ibcon#about to read 4, iclass 20, count 0 2006.231.07:31:12.72#ibcon#read 4, iclass 20, count 0 2006.231.07:31:12.72#ibcon#about to read 5, iclass 20, count 0 2006.231.07:31:12.72#ibcon#read 5, iclass 20, count 0 2006.231.07:31:12.72#ibcon#about to read 6, iclass 20, count 0 2006.231.07:31:12.72#ibcon#read 6, iclass 20, count 0 2006.231.07:31:12.72#ibcon#end of sib2, iclass 20, count 0 2006.231.07:31:12.72#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:31:12.72#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:31:12.72#ibcon#[27=USB\r\n] 2006.231.07:31:12.72#ibcon#*before write, iclass 20, count 0 2006.231.07:31:12.72#ibcon#enter sib2, iclass 20, count 0 2006.231.07:31:12.72#ibcon#flushed, iclass 20, count 0 2006.231.07:31:12.72#ibcon#about to write, iclass 20, count 0 2006.231.07:31:12.72#ibcon#wrote, iclass 20, count 0 2006.231.07:31:12.72#ibcon#about to read 3, iclass 20, count 0 2006.231.07:31:12.75#ibcon#read 3, iclass 20, count 0 2006.231.07:31:12.75#ibcon#about to read 4, iclass 20, count 0 2006.231.07:31:12.75#ibcon#read 4, iclass 20, count 0 2006.231.07:31:12.75#ibcon#about to read 5, iclass 20, count 0 2006.231.07:31:12.75#ibcon#read 5, iclass 20, count 0 2006.231.07:31:12.75#ibcon#about to read 6, iclass 20, count 0 2006.231.07:31:12.75#ibcon#read 6, iclass 20, count 0 2006.231.07:31:12.75#ibcon#end of sib2, iclass 20, count 0 2006.231.07:31:12.75#ibcon#*after write, iclass 20, count 0 2006.231.07:31:12.75#ibcon#*before return 0, iclass 20, count 0 2006.231.07:31:12.75#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:31:12.75#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:31:12.75#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:31:12.75#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:31:12.75$vc4f8/vabw=wide 2006.231.07:31:12.75#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.07:31:12.75#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.07:31:12.75#ibcon#ireg 8 cls_cnt 0 2006.231.07:31:12.75#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:31:12.75#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:31:12.75#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:31:12.75#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:31:12.75#ibcon#first serial, iclass 22, count 0 2006.231.07:31:12.75#ibcon#enter sib2, iclass 22, count 0 2006.231.07:31:12.75#ibcon#flushed, iclass 22, count 0 2006.231.07:31:12.75#ibcon#about to write, iclass 22, count 0 2006.231.07:31:12.75#ibcon#wrote, iclass 22, count 0 2006.231.07:31:12.75#ibcon#about to read 3, iclass 22, count 0 2006.231.07:31:12.77#ibcon#read 3, iclass 22, count 0 2006.231.07:31:12.77#ibcon#about to read 4, iclass 22, count 0 2006.231.07:31:12.77#ibcon#read 4, iclass 22, count 0 2006.231.07:31:12.77#ibcon#about to read 5, iclass 22, count 0 2006.231.07:31:12.77#ibcon#read 5, iclass 22, count 0 2006.231.07:31:12.77#ibcon#about to read 6, iclass 22, count 0 2006.231.07:31:12.77#ibcon#read 6, iclass 22, count 0 2006.231.07:31:12.77#ibcon#end of sib2, iclass 22, count 0 2006.231.07:31:12.77#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:31:12.77#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:31:12.77#ibcon#[25=BW32\r\n] 2006.231.07:31:12.77#ibcon#*before write, iclass 22, count 0 2006.231.07:31:12.77#ibcon#enter sib2, iclass 22, count 0 2006.231.07:31:12.77#ibcon#flushed, iclass 22, count 0 2006.231.07:31:12.77#ibcon#about to write, iclass 22, count 0 2006.231.07:31:12.77#ibcon#wrote, iclass 22, count 0 2006.231.07:31:12.77#ibcon#about to read 3, iclass 22, count 0 2006.231.07:31:12.80#ibcon#read 3, iclass 22, count 0 2006.231.07:31:12.80#ibcon#about to read 4, iclass 22, count 0 2006.231.07:31:12.80#ibcon#read 4, iclass 22, count 0 2006.231.07:31:12.80#ibcon#about to read 5, iclass 22, count 0 2006.231.07:31:12.80#ibcon#read 5, iclass 22, count 0 2006.231.07:31:12.80#ibcon#about to read 6, iclass 22, count 0 2006.231.07:31:12.80#ibcon#read 6, iclass 22, count 0 2006.231.07:31:12.80#ibcon#end of sib2, iclass 22, count 0 2006.231.07:31:12.80#ibcon#*after write, iclass 22, count 0 2006.231.07:31:12.80#ibcon#*before return 0, iclass 22, count 0 2006.231.07:31:12.80#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:31:12.80#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:31:12.80#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:31:12.80#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:31:12.80$vc4f8/vbbw=wide 2006.231.07:31:12.80#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.231.07:31:12.80#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.231.07:31:12.80#ibcon#ireg 8 cls_cnt 0 2006.231.07:31:12.80#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:31:12.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:31:12.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:31:12.87#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:31:12.87#ibcon#first serial, iclass 24, count 0 2006.231.07:31:12.87#ibcon#enter sib2, iclass 24, count 0 2006.231.07:31:12.87#ibcon#flushed, iclass 24, count 0 2006.231.07:31:12.87#ibcon#about to write, iclass 24, count 0 2006.231.07:31:12.87#ibcon#wrote, iclass 24, count 0 2006.231.07:31:12.87#ibcon#about to read 3, iclass 24, count 0 2006.231.07:31:12.89#ibcon#read 3, iclass 24, count 0 2006.231.07:31:12.89#ibcon#about to read 4, iclass 24, count 0 2006.231.07:31:12.89#ibcon#read 4, iclass 24, count 0 2006.231.07:31:12.89#ibcon#about to read 5, iclass 24, count 0 2006.231.07:31:12.89#ibcon#read 5, iclass 24, count 0 2006.231.07:31:12.89#ibcon#about to read 6, iclass 24, count 0 2006.231.07:31:12.89#ibcon#read 6, iclass 24, count 0 2006.231.07:31:12.89#ibcon#end of sib2, iclass 24, count 0 2006.231.07:31:12.89#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:31:12.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:31:12.89#ibcon#[27=BW32\r\n] 2006.231.07:31:12.89#ibcon#*before write, iclass 24, count 0 2006.231.07:31:12.89#ibcon#enter sib2, iclass 24, count 0 2006.231.07:31:12.89#ibcon#flushed, iclass 24, count 0 2006.231.07:31:12.89#ibcon#about to write, iclass 24, count 0 2006.231.07:31:12.89#ibcon#wrote, iclass 24, count 0 2006.231.07:31:12.89#ibcon#about to read 3, iclass 24, count 0 2006.231.07:31:12.92#ibcon#read 3, iclass 24, count 0 2006.231.07:31:12.92#ibcon#about to read 4, iclass 24, count 0 2006.231.07:31:12.92#ibcon#read 4, iclass 24, count 0 2006.231.07:31:12.92#ibcon#about to read 5, iclass 24, count 0 2006.231.07:31:12.92#ibcon#read 5, iclass 24, count 0 2006.231.07:31:12.92#ibcon#about to read 6, iclass 24, count 0 2006.231.07:31:12.92#ibcon#read 6, iclass 24, count 0 2006.231.07:31:12.92#ibcon#end of sib2, iclass 24, count 0 2006.231.07:31:12.92#ibcon#*after write, iclass 24, count 0 2006.231.07:31:12.92#ibcon#*before return 0, iclass 24, count 0 2006.231.07:31:12.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:31:12.92#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:31:12.92#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:31:12.92#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:31:12.92$4f8m12a/ifd4f 2006.231.07:31:12.92$ifd4f/lo= 2006.231.07:31:12.92$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:31:12.92$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:31:12.92$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:31:12.92$ifd4f/patch= 2006.231.07:31:12.93$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:31:12.93$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:31:12.93$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:31:12.93$4f8m12a/"form=m,16.000,1:2 2006.231.07:31:12.93$4f8m12a/"tpicd 2006.231.07:31:12.93$4f8m12a/echo=off 2006.231.07:31:12.93$4f8m12a/xlog=off 2006.231.07:31:12.93:!2006.231.07:33:20 2006.231.07:31:48.14#trakl#Source acquired 2006.231.07:31:48.14#flagr#flagr/antenna,acquired 2006.231.07:33:20.01:preob 2006.231.07:33:21.14/onsource/TRACKING 2006.231.07:33:21.14:!2006.231.07:33:30 2006.231.07:33:30.00:data_valid=on 2006.231.07:33:30.00:midob 2006.231.07:33:30.14/onsource/TRACKING 2006.231.07:33:30.14/wx/30.78,1004.4,85 2006.231.07:33:30.22/cable/+6.3709E-03 2006.231.07:33:31.31/va/01,08,usb,yes,33,35 2006.231.07:33:31.31/va/02,07,usb,yes,33,35 2006.231.07:33:31.31/va/03,08,usb,yes,25,25 2006.231.07:33:31.31/va/04,07,usb,yes,35,38 2006.231.07:33:31.31/va/05,07,usb,yes,39,41 2006.231.07:33:31.31/va/06,06,usb,yes,38,38 2006.231.07:33:31.31/va/07,06,usb,yes,39,39 2006.231.07:33:31.31/va/08,06,usb,yes,41,41 2006.231.07:33:31.54/valo/01,532.99,yes,locked 2006.231.07:33:31.54/valo/02,572.99,yes,locked 2006.231.07:33:31.54/valo/03,672.99,yes,locked 2006.231.07:33:31.54/valo/04,832.99,yes,locked 2006.231.07:33:31.54/valo/05,652.99,yes,locked 2006.231.07:33:31.54/valo/06,772.99,yes,locked 2006.231.07:33:31.54/valo/07,832.99,yes,locked 2006.231.07:33:31.54/valo/08,852.99,yes,locked 2006.231.07:33:32.63/vb/01,04,usb,yes,33,31 2006.231.07:33:32.63/vb/02,04,usb,yes,35,36 2006.231.07:33:32.63/vb/03,04,usb,yes,31,35 2006.231.07:33:32.63/vb/04,04,usb,yes,32,32 2006.231.07:33:32.63/vb/05,03,usb,yes,38,42 2006.231.07:33:32.63/vb/06,04,usb,yes,31,34 2006.231.07:33:32.63/vb/07,04,usb,yes,34,33 2006.231.07:33:32.63/vb/08,04,usb,yes,31,34 2006.231.07:33:32.87/vblo/01,632.99,yes,locked 2006.231.07:33:32.87/vblo/02,640.99,yes,locked 2006.231.07:33:32.87/vblo/03,656.99,yes,locked 2006.231.07:33:32.87/vblo/04,712.99,yes,locked 2006.231.07:33:32.87/vblo/05,744.99,yes,locked 2006.231.07:33:32.87/vblo/06,752.99,yes,locked 2006.231.07:33:32.87/vblo/07,734.99,yes,locked 2006.231.07:33:32.87/vblo/08,744.99,yes,locked 2006.231.07:33:33.02/vabw/8 2006.231.07:33:33.17/vbbw/8 2006.231.07:33:33.26/xfe/off,on,12.5 2006.231.07:33:33.64/ifatt/23,28,28,28 2006.231.07:33:34.07/fmout-gps/S +4.38E-07 2006.231.07:33:34.11:!2006.231.07:34:30 2006.231.07:34:30.00:data_valid=off 2006.231.07:34:30.01:postob 2006.231.07:34:30.09/cable/+6.3725E-03 2006.231.07:34:30.10/wx/30.77,1004.4,83 2006.231.07:34:31.07/fmout-gps/S +4.37E-07 2006.231.07:34:31.08:scan_name=231-0735,k06231,60 2006.231.07:34:31.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.231.07:34:32.13#flagr#flagr/antenna,new-source 2006.231.07:34:32.14:checkk5 2006.231.07:34:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:34:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:34:33.26/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:34:33.63/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:34:34.00/chk_obsdata//k5ts1/T2310733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:34:34.36/chk_obsdata//k5ts2/T2310733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:34:34.73/chk_obsdata//k5ts3/T2310733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:34:35.09/chk_obsdata//k5ts4/T2310733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:34:35.79/k5log//k5ts1_log_newline 2006.231.07:34:36.48/k5log//k5ts2_log_newline 2006.231.07:34:37.17/k5log//k5ts3_log_newline 2006.231.07:34:37.85/k5log//k5ts4_log_newline 2006.231.07:34:37.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:34:37.88:4f8m12a=1 2006.231.07:34:37.88$4f8m12a/echo=on 2006.231.07:34:37.88$4f8m12a/pcalon 2006.231.07:34:37.88$pcalon/"no phase cal control is implemented here 2006.231.07:34:37.88$4f8m12a/"tpicd=stop 2006.231.07:34:37.88$4f8m12a/vc4f8 2006.231.07:34:37.88$vc4f8/valo=1,532.99 2006.231.07:34:37.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.231.07:34:37.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.231.07:34:37.88#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:37.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:34:37.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:34:37.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:34:37.88#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:34:37.88#ibcon#first serial, iclass 35, count 0 2006.231.07:34:37.88#ibcon#enter sib2, iclass 35, count 0 2006.231.07:34:37.88#ibcon#flushed, iclass 35, count 0 2006.231.07:34:37.88#ibcon#about to write, iclass 35, count 0 2006.231.07:34:37.88#ibcon#wrote, iclass 35, count 0 2006.231.07:34:37.88#ibcon#about to read 3, iclass 35, count 0 2006.231.07:34:37.92#ibcon#read 3, iclass 35, count 0 2006.231.07:34:37.92#ibcon#about to read 4, iclass 35, count 0 2006.231.07:34:37.92#ibcon#read 4, iclass 35, count 0 2006.231.07:34:37.92#ibcon#about to read 5, iclass 35, count 0 2006.231.07:34:37.92#ibcon#read 5, iclass 35, count 0 2006.231.07:34:37.92#ibcon#about to read 6, iclass 35, count 0 2006.231.07:34:37.92#ibcon#read 6, iclass 35, count 0 2006.231.07:34:37.92#ibcon#end of sib2, iclass 35, count 0 2006.231.07:34:37.92#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:34:37.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:34:37.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:34:37.92#ibcon#*before write, iclass 35, count 0 2006.231.07:34:37.92#ibcon#enter sib2, iclass 35, count 0 2006.231.07:34:37.92#ibcon#flushed, iclass 35, count 0 2006.231.07:34:37.92#ibcon#about to write, iclass 35, count 0 2006.231.07:34:37.92#ibcon#wrote, iclass 35, count 0 2006.231.07:34:37.92#ibcon#about to read 3, iclass 35, count 0 2006.231.07:34:37.96#ibcon#read 3, iclass 35, count 0 2006.231.07:34:37.96#ibcon#about to read 4, iclass 35, count 0 2006.231.07:34:37.96#ibcon#read 4, iclass 35, count 0 2006.231.07:34:37.96#ibcon#about to read 5, iclass 35, count 0 2006.231.07:34:37.96#ibcon#read 5, iclass 35, count 0 2006.231.07:34:37.96#ibcon#about to read 6, iclass 35, count 0 2006.231.07:34:37.96#ibcon#read 6, iclass 35, count 0 2006.231.07:34:37.96#ibcon#end of sib2, iclass 35, count 0 2006.231.07:34:37.96#ibcon#*after write, iclass 35, count 0 2006.231.07:34:37.96#ibcon#*before return 0, iclass 35, count 0 2006.231.07:34:37.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:34:37.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:34:37.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:34:37.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:34:37.96$vc4f8/va=1,8 2006.231.07:34:37.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.231.07:34:37.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.231.07:34:37.96#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:37.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:34:37.96#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:34:37.96#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:34:37.96#ibcon#enter wrdev, iclass 37, count 2 2006.231.07:34:37.96#ibcon#first serial, iclass 37, count 2 2006.231.07:34:37.96#ibcon#enter sib2, iclass 37, count 2 2006.231.07:34:37.96#ibcon#flushed, iclass 37, count 2 2006.231.07:34:37.96#ibcon#about to write, iclass 37, count 2 2006.231.07:34:37.96#ibcon#wrote, iclass 37, count 2 2006.231.07:34:37.96#ibcon#about to read 3, iclass 37, count 2 2006.231.07:34:37.98#ibcon#read 3, iclass 37, count 2 2006.231.07:34:37.98#ibcon#about to read 4, iclass 37, count 2 2006.231.07:34:37.98#ibcon#read 4, iclass 37, count 2 2006.231.07:34:37.98#ibcon#about to read 5, iclass 37, count 2 2006.231.07:34:37.98#ibcon#read 5, iclass 37, count 2 2006.231.07:34:37.98#ibcon#about to read 6, iclass 37, count 2 2006.231.07:34:37.98#ibcon#read 6, iclass 37, count 2 2006.231.07:34:37.98#ibcon#end of sib2, iclass 37, count 2 2006.231.07:34:37.98#ibcon#*mode == 0, iclass 37, count 2 2006.231.07:34:37.98#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.231.07:34:37.98#ibcon#[25=AT01-08\r\n] 2006.231.07:34:37.98#ibcon#*before write, iclass 37, count 2 2006.231.07:34:37.98#ibcon#enter sib2, iclass 37, count 2 2006.231.07:34:37.98#ibcon#flushed, iclass 37, count 2 2006.231.07:34:37.98#ibcon#about to write, iclass 37, count 2 2006.231.07:34:37.98#ibcon#wrote, iclass 37, count 2 2006.231.07:34:37.98#ibcon#about to read 3, iclass 37, count 2 2006.231.07:34:38.02#ibcon#read 3, iclass 37, count 2 2006.231.07:34:38.02#ibcon#about to read 4, iclass 37, count 2 2006.231.07:34:38.02#ibcon#read 4, iclass 37, count 2 2006.231.07:34:38.02#ibcon#about to read 5, iclass 37, count 2 2006.231.07:34:38.02#ibcon#read 5, iclass 37, count 2 2006.231.07:34:38.02#ibcon#about to read 6, iclass 37, count 2 2006.231.07:34:38.02#ibcon#read 6, iclass 37, count 2 2006.231.07:34:38.02#ibcon#end of sib2, iclass 37, count 2 2006.231.07:34:38.02#ibcon#*after write, iclass 37, count 2 2006.231.07:34:38.02#ibcon#*before return 0, iclass 37, count 2 2006.231.07:34:38.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:34:38.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:34:38.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.231.07:34:38.02#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:38.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:34:38.13#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:34:38.13#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:34:38.13#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:34:38.13#ibcon#first serial, iclass 37, count 0 2006.231.07:34:38.13#ibcon#enter sib2, iclass 37, count 0 2006.231.07:34:38.13#ibcon#flushed, iclass 37, count 0 2006.231.07:34:38.13#ibcon#about to write, iclass 37, count 0 2006.231.07:34:38.13#ibcon#wrote, iclass 37, count 0 2006.231.07:34:38.13#ibcon#about to read 3, iclass 37, count 0 2006.231.07:34:38.15#ibcon#read 3, iclass 37, count 0 2006.231.07:34:38.15#ibcon#about to read 4, iclass 37, count 0 2006.231.07:34:38.15#ibcon#read 4, iclass 37, count 0 2006.231.07:34:38.15#ibcon#about to read 5, iclass 37, count 0 2006.231.07:34:38.15#ibcon#read 5, iclass 37, count 0 2006.231.07:34:38.15#ibcon#about to read 6, iclass 37, count 0 2006.231.07:34:38.15#ibcon#read 6, iclass 37, count 0 2006.231.07:34:38.15#ibcon#end of sib2, iclass 37, count 0 2006.231.07:34:38.15#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:34:38.15#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:34:38.15#ibcon#[25=USB\r\n] 2006.231.07:34:38.15#ibcon#*before write, iclass 37, count 0 2006.231.07:34:38.15#ibcon#enter sib2, iclass 37, count 0 2006.231.07:34:38.15#ibcon#flushed, iclass 37, count 0 2006.231.07:34:38.15#ibcon#about to write, iclass 37, count 0 2006.231.07:34:38.15#ibcon#wrote, iclass 37, count 0 2006.231.07:34:38.15#ibcon#about to read 3, iclass 37, count 0 2006.231.07:34:38.18#ibcon#read 3, iclass 37, count 0 2006.231.07:34:38.18#ibcon#about to read 4, iclass 37, count 0 2006.231.07:34:38.18#ibcon#read 4, iclass 37, count 0 2006.231.07:34:38.18#ibcon#about to read 5, iclass 37, count 0 2006.231.07:34:38.18#ibcon#read 5, iclass 37, count 0 2006.231.07:34:38.18#ibcon#about to read 6, iclass 37, count 0 2006.231.07:34:38.18#ibcon#read 6, iclass 37, count 0 2006.231.07:34:38.18#ibcon#end of sib2, iclass 37, count 0 2006.231.07:34:38.18#ibcon#*after write, iclass 37, count 0 2006.231.07:34:38.18#ibcon#*before return 0, iclass 37, count 0 2006.231.07:34:38.18#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:34:38.18#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:34:38.18#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:34:38.18#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:34:38.18$vc4f8/valo=2,572.99 2006.231.07:34:38.18#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.07:34:38.18#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.07:34:38.18#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:38.18#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:34:38.18#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:34:38.18#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:34:38.18#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:34:38.18#ibcon#first serial, iclass 39, count 0 2006.231.07:34:38.18#ibcon#enter sib2, iclass 39, count 0 2006.231.07:34:38.18#ibcon#flushed, iclass 39, count 0 2006.231.07:34:38.18#ibcon#about to write, iclass 39, count 0 2006.231.07:34:38.18#ibcon#wrote, iclass 39, count 0 2006.231.07:34:38.18#ibcon#about to read 3, iclass 39, count 0 2006.231.07:34:38.20#ibcon#read 3, iclass 39, count 0 2006.231.07:34:38.20#ibcon#about to read 4, iclass 39, count 0 2006.231.07:34:38.20#ibcon#read 4, iclass 39, count 0 2006.231.07:34:38.20#ibcon#about to read 5, iclass 39, count 0 2006.231.07:34:38.20#ibcon#read 5, iclass 39, count 0 2006.231.07:34:38.20#ibcon#about to read 6, iclass 39, count 0 2006.231.07:34:38.20#ibcon#read 6, iclass 39, count 0 2006.231.07:34:38.20#ibcon#end of sib2, iclass 39, count 0 2006.231.07:34:38.20#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:34:38.20#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:34:38.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:34:38.20#ibcon#*before write, iclass 39, count 0 2006.231.07:34:38.20#ibcon#enter sib2, iclass 39, count 0 2006.231.07:34:38.20#ibcon#flushed, iclass 39, count 0 2006.231.07:34:38.20#ibcon#about to write, iclass 39, count 0 2006.231.07:34:38.20#ibcon#wrote, iclass 39, count 0 2006.231.07:34:38.20#ibcon#about to read 3, iclass 39, count 0 2006.231.07:34:38.24#ibcon#read 3, iclass 39, count 0 2006.231.07:34:38.24#ibcon#about to read 4, iclass 39, count 0 2006.231.07:34:38.24#ibcon#read 4, iclass 39, count 0 2006.231.07:34:38.24#ibcon#about to read 5, iclass 39, count 0 2006.231.07:34:38.24#ibcon#read 5, iclass 39, count 0 2006.231.07:34:38.24#ibcon#about to read 6, iclass 39, count 0 2006.231.07:34:38.24#ibcon#read 6, iclass 39, count 0 2006.231.07:34:38.24#ibcon#end of sib2, iclass 39, count 0 2006.231.07:34:38.24#ibcon#*after write, iclass 39, count 0 2006.231.07:34:38.24#ibcon#*before return 0, iclass 39, count 0 2006.231.07:34:38.24#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:34:38.24#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:34:38.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:34:38.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:34:38.24$vc4f8/va=2,7 2006.231.07:34:38.24#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.231.07:34:38.24#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.231.07:34:38.24#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:38.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:34:38.30#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:34:38.30#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:34:38.30#ibcon#enter wrdev, iclass 3, count 2 2006.231.07:34:38.30#ibcon#first serial, iclass 3, count 2 2006.231.07:34:38.30#ibcon#enter sib2, iclass 3, count 2 2006.231.07:34:38.30#ibcon#flushed, iclass 3, count 2 2006.231.07:34:38.30#ibcon#about to write, iclass 3, count 2 2006.231.07:34:38.30#ibcon#wrote, iclass 3, count 2 2006.231.07:34:38.30#ibcon#about to read 3, iclass 3, count 2 2006.231.07:34:38.32#ibcon#read 3, iclass 3, count 2 2006.231.07:34:38.32#ibcon#about to read 4, iclass 3, count 2 2006.231.07:34:38.32#ibcon#read 4, iclass 3, count 2 2006.231.07:34:38.32#ibcon#about to read 5, iclass 3, count 2 2006.231.07:34:38.32#ibcon#read 5, iclass 3, count 2 2006.231.07:34:38.32#ibcon#about to read 6, iclass 3, count 2 2006.231.07:34:38.32#ibcon#read 6, iclass 3, count 2 2006.231.07:34:38.32#ibcon#end of sib2, iclass 3, count 2 2006.231.07:34:38.32#ibcon#*mode == 0, iclass 3, count 2 2006.231.07:34:38.32#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.231.07:34:38.32#ibcon#[25=AT02-07\r\n] 2006.231.07:34:38.32#ibcon#*before write, iclass 3, count 2 2006.231.07:34:38.32#ibcon#enter sib2, iclass 3, count 2 2006.231.07:34:38.32#ibcon#flushed, iclass 3, count 2 2006.231.07:34:38.32#ibcon#about to write, iclass 3, count 2 2006.231.07:34:38.32#ibcon#wrote, iclass 3, count 2 2006.231.07:34:38.32#ibcon#about to read 3, iclass 3, count 2 2006.231.07:34:38.35#ibcon#read 3, iclass 3, count 2 2006.231.07:34:38.35#ibcon#about to read 4, iclass 3, count 2 2006.231.07:34:38.35#ibcon#read 4, iclass 3, count 2 2006.231.07:34:38.35#ibcon#about to read 5, iclass 3, count 2 2006.231.07:34:38.35#ibcon#read 5, iclass 3, count 2 2006.231.07:34:38.35#ibcon#about to read 6, iclass 3, count 2 2006.231.07:34:38.35#ibcon#read 6, iclass 3, count 2 2006.231.07:34:38.35#ibcon#end of sib2, iclass 3, count 2 2006.231.07:34:38.35#ibcon#*after write, iclass 3, count 2 2006.231.07:34:38.35#ibcon#*before return 0, iclass 3, count 2 2006.231.07:34:38.35#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:34:38.35#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:34:38.35#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.231.07:34:38.35#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:38.35#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:34:38.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:34:38.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:34:38.48#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:34:38.48#ibcon#first serial, iclass 3, count 0 2006.231.07:34:38.48#ibcon#enter sib2, iclass 3, count 0 2006.231.07:34:38.48#ibcon#flushed, iclass 3, count 0 2006.231.07:34:38.48#ibcon#about to write, iclass 3, count 0 2006.231.07:34:38.48#ibcon#wrote, iclass 3, count 0 2006.231.07:34:38.48#ibcon#about to read 3, iclass 3, count 0 2006.231.07:34:38.49#ibcon#read 3, iclass 3, count 0 2006.231.07:34:38.49#ibcon#about to read 4, iclass 3, count 0 2006.231.07:34:38.49#ibcon#read 4, iclass 3, count 0 2006.231.07:34:38.49#ibcon#about to read 5, iclass 3, count 0 2006.231.07:34:38.49#ibcon#read 5, iclass 3, count 0 2006.231.07:34:38.49#ibcon#about to read 6, iclass 3, count 0 2006.231.07:34:38.49#ibcon#read 6, iclass 3, count 0 2006.231.07:34:38.49#ibcon#end of sib2, iclass 3, count 0 2006.231.07:34:38.49#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:34:38.49#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:34:38.49#ibcon#[25=USB\r\n] 2006.231.07:34:38.49#ibcon#*before write, iclass 3, count 0 2006.231.07:34:38.49#ibcon#enter sib2, iclass 3, count 0 2006.231.07:34:38.49#ibcon#flushed, iclass 3, count 0 2006.231.07:34:38.49#ibcon#about to write, iclass 3, count 0 2006.231.07:34:38.49#ibcon#wrote, iclass 3, count 0 2006.231.07:34:38.49#ibcon#about to read 3, iclass 3, count 0 2006.231.07:34:38.52#ibcon#read 3, iclass 3, count 0 2006.231.07:34:38.52#ibcon#about to read 4, iclass 3, count 0 2006.231.07:34:38.52#ibcon#read 4, iclass 3, count 0 2006.231.07:34:38.52#ibcon#about to read 5, iclass 3, count 0 2006.231.07:34:38.52#ibcon#read 5, iclass 3, count 0 2006.231.07:34:38.52#ibcon#about to read 6, iclass 3, count 0 2006.231.07:34:38.52#ibcon#read 6, iclass 3, count 0 2006.231.07:34:38.52#ibcon#end of sib2, iclass 3, count 0 2006.231.07:34:38.52#ibcon#*after write, iclass 3, count 0 2006.231.07:34:38.52#ibcon#*before return 0, iclass 3, count 0 2006.231.07:34:38.52#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:34:38.52#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:34:38.52#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:34:38.52#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:34:38.52$vc4f8/valo=3,672.99 2006.231.07:34:38.52#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.231.07:34:38.52#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.231.07:34:38.52#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:38.52#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:34:38.52#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:34:38.52#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:34:38.52#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:34:38.52#ibcon#first serial, iclass 5, count 0 2006.231.07:34:38.52#ibcon#enter sib2, iclass 5, count 0 2006.231.07:34:38.52#ibcon#flushed, iclass 5, count 0 2006.231.07:34:38.52#ibcon#about to write, iclass 5, count 0 2006.231.07:34:38.52#ibcon#wrote, iclass 5, count 0 2006.231.07:34:38.52#ibcon#about to read 3, iclass 5, count 0 2006.231.07:34:38.54#ibcon#read 3, iclass 5, count 0 2006.231.07:34:38.54#ibcon#about to read 4, iclass 5, count 0 2006.231.07:34:38.54#ibcon#read 4, iclass 5, count 0 2006.231.07:34:38.54#ibcon#about to read 5, iclass 5, count 0 2006.231.07:34:38.54#ibcon#read 5, iclass 5, count 0 2006.231.07:34:38.54#ibcon#about to read 6, iclass 5, count 0 2006.231.07:34:38.54#ibcon#read 6, iclass 5, count 0 2006.231.07:34:38.54#ibcon#end of sib2, iclass 5, count 0 2006.231.07:34:38.54#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:34:38.54#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:34:38.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:34:38.54#ibcon#*before write, iclass 5, count 0 2006.231.07:34:38.54#ibcon#enter sib2, iclass 5, count 0 2006.231.07:34:38.54#ibcon#flushed, iclass 5, count 0 2006.231.07:34:38.54#ibcon#about to write, iclass 5, count 0 2006.231.07:34:38.54#ibcon#wrote, iclass 5, count 0 2006.231.07:34:38.54#ibcon#about to read 3, iclass 5, count 0 2006.231.07:34:38.59#ibcon#read 3, iclass 5, count 0 2006.231.07:34:38.59#ibcon#about to read 4, iclass 5, count 0 2006.231.07:34:38.59#ibcon#read 4, iclass 5, count 0 2006.231.07:34:38.59#ibcon#about to read 5, iclass 5, count 0 2006.231.07:34:38.59#ibcon#read 5, iclass 5, count 0 2006.231.07:34:38.59#ibcon#about to read 6, iclass 5, count 0 2006.231.07:34:38.59#ibcon#read 6, iclass 5, count 0 2006.231.07:34:38.59#ibcon#end of sib2, iclass 5, count 0 2006.231.07:34:38.59#ibcon#*after write, iclass 5, count 0 2006.231.07:34:38.59#ibcon#*before return 0, iclass 5, count 0 2006.231.07:34:38.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:34:38.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:34:38.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:34:38.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:34:38.59$vc4f8/va=3,8 2006.231.07:34:38.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.231.07:34:38.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.231.07:34:38.59#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:38.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:34:38.63#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:34:38.63#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:34:38.63#ibcon#enter wrdev, iclass 7, count 2 2006.231.07:34:38.63#ibcon#first serial, iclass 7, count 2 2006.231.07:34:38.63#ibcon#enter sib2, iclass 7, count 2 2006.231.07:34:38.63#ibcon#flushed, iclass 7, count 2 2006.231.07:34:38.63#ibcon#about to write, iclass 7, count 2 2006.231.07:34:38.63#ibcon#wrote, iclass 7, count 2 2006.231.07:34:38.63#ibcon#about to read 3, iclass 7, count 2 2006.231.07:34:38.65#ibcon#read 3, iclass 7, count 2 2006.231.07:34:38.65#ibcon#about to read 4, iclass 7, count 2 2006.231.07:34:38.65#ibcon#read 4, iclass 7, count 2 2006.231.07:34:38.65#ibcon#about to read 5, iclass 7, count 2 2006.231.07:34:38.65#ibcon#read 5, iclass 7, count 2 2006.231.07:34:38.65#ibcon#about to read 6, iclass 7, count 2 2006.231.07:34:38.65#ibcon#read 6, iclass 7, count 2 2006.231.07:34:38.65#ibcon#end of sib2, iclass 7, count 2 2006.231.07:34:38.65#ibcon#*mode == 0, iclass 7, count 2 2006.231.07:34:38.65#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.231.07:34:38.65#ibcon#[25=AT03-08\r\n] 2006.231.07:34:38.65#ibcon#*before write, iclass 7, count 2 2006.231.07:34:38.65#ibcon#enter sib2, iclass 7, count 2 2006.231.07:34:38.65#ibcon#flushed, iclass 7, count 2 2006.231.07:34:38.65#ibcon#about to write, iclass 7, count 2 2006.231.07:34:38.65#ibcon#wrote, iclass 7, count 2 2006.231.07:34:38.65#ibcon#about to read 3, iclass 7, count 2 2006.231.07:34:38.68#ibcon#read 3, iclass 7, count 2 2006.231.07:34:38.68#ibcon#about to read 4, iclass 7, count 2 2006.231.07:34:38.68#ibcon#read 4, iclass 7, count 2 2006.231.07:34:38.68#ibcon#about to read 5, iclass 7, count 2 2006.231.07:34:38.68#ibcon#read 5, iclass 7, count 2 2006.231.07:34:38.68#ibcon#about to read 6, iclass 7, count 2 2006.231.07:34:38.68#ibcon#read 6, iclass 7, count 2 2006.231.07:34:38.68#ibcon#end of sib2, iclass 7, count 2 2006.231.07:34:38.68#ibcon#*after write, iclass 7, count 2 2006.231.07:34:38.68#ibcon#*before return 0, iclass 7, count 2 2006.231.07:34:38.68#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:34:38.68#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:34:38.68#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.231.07:34:38.68#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:38.68#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:34:38.80#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:34:38.80#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:34:38.80#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:34:38.80#ibcon#first serial, iclass 7, count 0 2006.231.07:34:38.80#ibcon#enter sib2, iclass 7, count 0 2006.231.07:34:38.80#ibcon#flushed, iclass 7, count 0 2006.231.07:34:38.80#ibcon#about to write, iclass 7, count 0 2006.231.07:34:38.80#ibcon#wrote, iclass 7, count 0 2006.231.07:34:38.80#ibcon#about to read 3, iclass 7, count 0 2006.231.07:34:38.82#ibcon#read 3, iclass 7, count 0 2006.231.07:34:38.82#ibcon#about to read 4, iclass 7, count 0 2006.231.07:34:38.82#ibcon#read 4, iclass 7, count 0 2006.231.07:34:38.82#ibcon#about to read 5, iclass 7, count 0 2006.231.07:34:38.82#ibcon#read 5, iclass 7, count 0 2006.231.07:34:38.82#ibcon#about to read 6, iclass 7, count 0 2006.231.07:34:38.82#ibcon#read 6, iclass 7, count 0 2006.231.07:34:38.82#ibcon#end of sib2, iclass 7, count 0 2006.231.07:34:38.82#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:34:38.82#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:34:38.82#ibcon#[25=USB\r\n] 2006.231.07:34:38.82#ibcon#*before write, iclass 7, count 0 2006.231.07:34:38.82#ibcon#enter sib2, iclass 7, count 0 2006.231.07:34:38.82#ibcon#flushed, iclass 7, count 0 2006.231.07:34:38.82#ibcon#about to write, iclass 7, count 0 2006.231.07:34:38.82#ibcon#wrote, iclass 7, count 0 2006.231.07:34:38.82#ibcon#about to read 3, iclass 7, count 0 2006.231.07:34:38.85#ibcon#read 3, iclass 7, count 0 2006.231.07:34:38.85#ibcon#about to read 4, iclass 7, count 0 2006.231.07:34:38.85#ibcon#read 4, iclass 7, count 0 2006.231.07:34:38.85#ibcon#about to read 5, iclass 7, count 0 2006.231.07:34:38.85#ibcon#read 5, iclass 7, count 0 2006.231.07:34:38.85#ibcon#about to read 6, iclass 7, count 0 2006.231.07:34:38.85#ibcon#read 6, iclass 7, count 0 2006.231.07:34:38.85#ibcon#end of sib2, iclass 7, count 0 2006.231.07:34:38.85#ibcon#*after write, iclass 7, count 0 2006.231.07:34:38.85#ibcon#*before return 0, iclass 7, count 0 2006.231.07:34:38.85#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:34:38.85#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:34:38.85#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:34:38.85#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:34:38.85$vc4f8/valo=4,832.99 2006.231.07:34:38.85#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.231.07:34:38.85#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.231.07:34:38.85#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:38.85#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:34:38.85#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:34:38.85#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:34:38.85#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:34:38.85#ibcon#first serial, iclass 11, count 0 2006.231.07:34:38.85#ibcon#enter sib2, iclass 11, count 0 2006.231.07:34:38.85#ibcon#flushed, iclass 11, count 0 2006.231.07:34:38.85#ibcon#about to write, iclass 11, count 0 2006.231.07:34:38.85#ibcon#wrote, iclass 11, count 0 2006.231.07:34:38.85#ibcon#about to read 3, iclass 11, count 0 2006.231.07:34:38.87#ibcon#read 3, iclass 11, count 0 2006.231.07:34:38.87#ibcon#about to read 4, iclass 11, count 0 2006.231.07:34:38.87#ibcon#read 4, iclass 11, count 0 2006.231.07:34:38.87#ibcon#about to read 5, iclass 11, count 0 2006.231.07:34:38.87#ibcon#read 5, iclass 11, count 0 2006.231.07:34:38.87#ibcon#about to read 6, iclass 11, count 0 2006.231.07:34:38.87#ibcon#read 6, iclass 11, count 0 2006.231.07:34:38.87#ibcon#end of sib2, iclass 11, count 0 2006.231.07:34:38.87#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:34:38.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:34:38.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:34:38.87#ibcon#*before write, iclass 11, count 0 2006.231.07:34:38.87#ibcon#enter sib2, iclass 11, count 0 2006.231.07:34:38.87#ibcon#flushed, iclass 11, count 0 2006.231.07:34:38.87#ibcon#about to write, iclass 11, count 0 2006.231.07:34:38.87#ibcon#wrote, iclass 11, count 0 2006.231.07:34:38.87#ibcon#about to read 3, iclass 11, count 0 2006.231.07:34:38.91#ibcon#read 3, iclass 11, count 0 2006.231.07:34:38.91#ibcon#about to read 4, iclass 11, count 0 2006.231.07:34:38.91#ibcon#read 4, iclass 11, count 0 2006.231.07:34:38.91#ibcon#about to read 5, iclass 11, count 0 2006.231.07:34:38.91#ibcon#read 5, iclass 11, count 0 2006.231.07:34:38.91#ibcon#about to read 6, iclass 11, count 0 2006.231.07:34:38.91#ibcon#read 6, iclass 11, count 0 2006.231.07:34:38.91#ibcon#end of sib2, iclass 11, count 0 2006.231.07:34:38.91#ibcon#*after write, iclass 11, count 0 2006.231.07:34:38.91#ibcon#*before return 0, iclass 11, count 0 2006.231.07:34:38.91#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:34:38.91#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:34:38.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:34:38.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:34:38.91$vc4f8/va=4,7 2006.231.07:34:38.91#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.231.07:34:38.91#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.231.07:34:38.91#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:38.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:34:38.97#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:34:38.97#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:34:38.97#ibcon#enter wrdev, iclass 13, count 2 2006.231.07:34:38.97#ibcon#first serial, iclass 13, count 2 2006.231.07:34:38.97#ibcon#enter sib2, iclass 13, count 2 2006.231.07:34:38.97#ibcon#flushed, iclass 13, count 2 2006.231.07:34:38.97#ibcon#about to write, iclass 13, count 2 2006.231.07:34:38.97#ibcon#wrote, iclass 13, count 2 2006.231.07:34:38.97#ibcon#about to read 3, iclass 13, count 2 2006.231.07:34:38.99#ibcon#read 3, iclass 13, count 2 2006.231.07:34:38.99#ibcon#about to read 4, iclass 13, count 2 2006.231.07:34:38.99#ibcon#read 4, iclass 13, count 2 2006.231.07:34:38.99#ibcon#about to read 5, iclass 13, count 2 2006.231.07:34:38.99#ibcon#read 5, iclass 13, count 2 2006.231.07:34:38.99#ibcon#about to read 6, iclass 13, count 2 2006.231.07:34:38.99#ibcon#read 6, iclass 13, count 2 2006.231.07:34:38.99#ibcon#end of sib2, iclass 13, count 2 2006.231.07:34:38.99#ibcon#*mode == 0, iclass 13, count 2 2006.231.07:34:38.99#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.231.07:34:38.99#ibcon#[25=AT04-07\r\n] 2006.231.07:34:38.99#ibcon#*before write, iclass 13, count 2 2006.231.07:34:38.99#ibcon#enter sib2, iclass 13, count 2 2006.231.07:34:38.99#ibcon#flushed, iclass 13, count 2 2006.231.07:34:38.99#ibcon#about to write, iclass 13, count 2 2006.231.07:34:38.99#ibcon#wrote, iclass 13, count 2 2006.231.07:34:38.99#ibcon#about to read 3, iclass 13, count 2 2006.231.07:34:39.02#ibcon#read 3, iclass 13, count 2 2006.231.07:34:39.02#ibcon#about to read 4, iclass 13, count 2 2006.231.07:34:39.02#ibcon#read 4, iclass 13, count 2 2006.231.07:34:39.02#ibcon#about to read 5, iclass 13, count 2 2006.231.07:34:39.02#ibcon#read 5, iclass 13, count 2 2006.231.07:34:39.02#ibcon#about to read 6, iclass 13, count 2 2006.231.07:34:39.02#ibcon#read 6, iclass 13, count 2 2006.231.07:34:39.02#ibcon#end of sib2, iclass 13, count 2 2006.231.07:34:39.02#ibcon#*after write, iclass 13, count 2 2006.231.07:34:39.02#ibcon#*before return 0, iclass 13, count 2 2006.231.07:34:39.02#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:34:39.02#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:34:39.02#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.231.07:34:39.02#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:39.02#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:34:39.14#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:34:39.14#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:34:39.14#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:34:39.14#ibcon#first serial, iclass 13, count 0 2006.231.07:34:39.14#ibcon#enter sib2, iclass 13, count 0 2006.231.07:34:39.14#ibcon#flushed, iclass 13, count 0 2006.231.07:34:39.14#ibcon#about to write, iclass 13, count 0 2006.231.07:34:39.14#ibcon#wrote, iclass 13, count 0 2006.231.07:34:39.14#ibcon#about to read 3, iclass 13, count 0 2006.231.07:34:39.16#ibcon#read 3, iclass 13, count 0 2006.231.07:34:39.16#ibcon#about to read 4, iclass 13, count 0 2006.231.07:34:39.16#ibcon#read 4, iclass 13, count 0 2006.231.07:34:39.16#ibcon#about to read 5, iclass 13, count 0 2006.231.07:34:39.16#ibcon#read 5, iclass 13, count 0 2006.231.07:34:39.16#ibcon#about to read 6, iclass 13, count 0 2006.231.07:34:39.16#ibcon#read 6, iclass 13, count 0 2006.231.07:34:39.16#ibcon#end of sib2, iclass 13, count 0 2006.231.07:34:39.16#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:34:39.16#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:34:39.16#ibcon#[25=USB\r\n] 2006.231.07:34:39.16#ibcon#*before write, iclass 13, count 0 2006.231.07:34:39.16#ibcon#enter sib2, iclass 13, count 0 2006.231.07:34:39.16#ibcon#flushed, iclass 13, count 0 2006.231.07:34:39.16#ibcon#about to write, iclass 13, count 0 2006.231.07:34:39.16#ibcon#wrote, iclass 13, count 0 2006.231.07:34:39.16#ibcon#about to read 3, iclass 13, count 0 2006.231.07:34:39.19#ibcon#read 3, iclass 13, count 0 2006.231.07:34:39.19#ibcon#about to read 4, iclass 13, count 0 2006.231.07:34:39.19#ibcon#read 4, iclass 13, count 0 2006.231.07:34:39.19#ibcon#about to read 5, iclass 13, count 0 2006.231.07:34:39.19#ibcon#read 5, iclass 13, count 0 2006.231.07:34:39.19#ibcon#about to read 6, iclass 13, count 0 2006.231.07:34:39.19#ibcon#read 6, iclass 13, count 0 2006.231.07:34:39.19#ibcon#end of sib2, iclass 13, count 0 2006.231.07:34:39.19#ibcon#*after write, iclass 13, count 0 2006.231.07:34:39.19#ibcon#*before return 0, iclass 13, count 0 2006.231.07:34:39.19#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:34:39.19#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:34:39.19#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:34:39.19#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:34:39.19$vc4f8/valo=5,652.99 2006.231.07:34:39.19#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.07:34:39.19#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.07:34:39.19#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:39.19#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:34:39.19#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:34:39.19#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:34:39.19#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:34:39.19#ibcon#first serial, iclass 15, count 0 2006.231.07:34:39.19#ibcon#enter sib2, iclass 15, count 0 2006.231.07:34:39.19#ibcon#flushed, iclass 15, count 0 2006.231.07:34:39.19#ibcon#about to write, iclass 15, count 0 2006.231.07:34:39.19#ibcon#wrote, iclass 15, count 0 2006.231.07:34:39.19#ibcon#about to read 3, iclass 15, count 0 2006.231.07:34:39.21#ibcon#read 3, iclass 15, count 0 2006.231.07:34:39.21#ibcon#about to read 4, iclass 15, count 0 2006.231.07:34:39.21#ibcon#read 4, iclass 15, count 0 2006.231.07:34:39.21#ibcon#about to read 5, iclass 15, count 0 2006.231.07:34:39.21#ibcon#read 5, iclass 15, count 0 2006.231.07:34:39.21#ibcon#about to read 6, iclass 15, count 0 2006.231.07:34:39.21#ibcon#read 6, iclass 15, count 0 2006.231.07:34:39.21#ibcon#end of sib2, iclass 15, count 0 2006.231.07:34:39.21#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:34:39.21#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:34:39.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:34:39.21#ibcon#*before write, iclass 15, count 0 2006.231.07:34:39.21#ibcon#enter sib2, iclass 15, count 0 2006.231.07:34:39.21#ibcon#flushed, iclass 15, count 0 2006.231.07:34:39.21#ibcon#about to write, iclass 15, count 0 2006.231.07:34:39.21#ibcon#wrote, iclass 15, count 0 2006.231.07:34:39.21#ibcon#about to read 3, iclass 15, count 0 2006.231.07:34:39.25#ibcon#read 3, iclass 15, count 0 2006.231.07:34:39.25#ibcon#about to read 4, iclass 15, count 0 2006.231.07:34:39.25#ibcon#read 4, iclass 15, count 0 2006.231.07:34:39.25#ibcon#about to read 5, iclass 15, count 0 2006.231.07:34:39.25#ibcon#read 5, iclass 15, count 0 2006.231.07:34:39.25#ibcon#about to read 6, iclass 15, count 0 2006.231.07:34:39.25#ibcon#read 6, iclass 15, count 0 2006.231.07:34:39.25#ibcon#end of sib2, iclass 15, count 0 2006.231.07:34:39.25#ibcon#*after write, iclass 15, count 0 2006.231.07:34:39.25#ibcon#*before return 0, iclass 15, count 0 2006.231.07:34:39.25#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:34:39.25#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:34:39.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:34:39.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:34:39.25$vc4f8/va=5,7 2006.231.07:34:39.25#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.07:34:39.25#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.07:34:39.25#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:39.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:34:39.31#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:34:39.31#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:34:39.31#ibcon#enter wrdev, iclass 17, count 2 2006.231.07:34:39.31#ibcon#first serial, iclass 17, count 2 2006.231.07:34:39.31#ibcon#enter sib2, iclass 17, count 2 2006.231.07:34:39.31#ibcon#flushed, iclass 17, count 2 2006.231.07:34:39.31#ibcon#about to write, iclass 17, count 2 2006.231.07:34:39.31#ibcon#wrote, iclass 17, count 2 2006.231.07:34:39.31#ibcon#about to read 3, iclass 17, count 2 2006.231.07:34:39.34#ibcon#read 3, iclass 17, count 2 2006.231.07:34:39.34#ibcon#about to read 4, iclass 17, count 2 2006.231.07:34:39.34#ibcon#read 4, iclass 17, count 2 2006.231.07:34:39.34#ibcon#about to read 5, iclass 17, count 2 2006.231.07:34:39.34#ibcon#read 5, iclass 17, count 2 2006.231.07:34:39.34#ibcon#about to read 6, iclass 17, count 2 2006.231.07:34:39.34#ibcon#read 6, iclass 17, count 2 2006.231.07:34:39.34#ibcon#end of sib2, iclass 17, count 2 2006.231.07:34:39.34#ibcon#*mode == 0, iclass 17, count 2 2006.231.07:34:39.34#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.07:34:39.34#ibcon#[25=AT05-07\r\n] 2006.231.07:34:39.34#ibcon#*before write, iclass 17, count 2 2006.231.07:34:39.34#ibcon#enter sib2, iclass 17, count 2 2006.231.07:34:39.34#ibcon#flushed, iclass 17, count 2 2006.231.07:34:39.34#ibcon#about to write, iclass 17, count 2 2006.231.07:34:39.34#ibcon#wrote, iclass 17, count 2 2006.231.07:34:39.34#ibcon#about to read 3, iclass 17, count 2 2006.231.07:34:39.37#ibcon#read 3, iclass 17, count 2 2006.231.07:34:39.37#ibcon#about to read 4, iclass 17, count 2 2006.231.07:34:39.37#ibcon#read 4, iclass 17, count 2 2006.231.07:34:39.37#ibcon#about to read 5, iclass 17, count 2 2006.231.07:34:39.37#ibcon#read 5, iclass 17, count 2 2006.231.07:34:39.37#ibcon#about to read 6, iclass 17, count 2 2006.231.07:34:39.37#ibcon#read 6, iclass 17, count 2 2006.231.07:34:39.37#ibcon#end of sib2, iclass 17, count 2 2006.231.07:34:39.37#ibcon#*after write, iclass 17, count 2 2006.231.07:34:39.37#ibcon#*before return 0, iclass 17, count 2 2006.231.07:34:39.37#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:34:39.37#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:34:39.37#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.07:34:39.37#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:39.37#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:34:39.49#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:34:39.49#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:34:39.49#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:34:39.49#ibcon#first serial, iclass 17, count 0 2006.231.07:34:39.49#ibcon#enter sib2, iclass 17, count 0 2006.231.07:34:39.49#ibcon#flushed, iclass 17, count 0 2006.231.07:34:39.49#ibcon#about to write, iclass 17, count 0 2006.231.07:34:39.49#ibcon#wrote, iclass 17, count 0 2006.231.07:34:39.49#ibcon#about to read 3, iclass 17, count 0 2006.231.07:34:39.51#ibcon#read 3, iclass 17, count 0 2006.231.07:34:39.51#ibcon#about to read 4, iclass 17, count 0 2006.231.07:34:39.51#ibcon#read 4, iclass 17, count 0 2006.231.07:34:39.51#ibcon#about to read 5, iclass 17, count 0 2006.231.07:34:39.51#ibcon#read 5, iclass 17, count 0 2006.231.07:34:39.51#ibcon#about to read 6, iclass 17, count 0 2006.231.07:34:39.51#ibcon#read 6, iclass 17, count 0 2006.231.07:34:39.51#ibcon#end of sib2, iclass 17, count 0 2006.231.07:34:39.51#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:34:39.51#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:34:39.51#ibcon#[25=USB\r\n] 2006.231.07:34:39.51#ibcon#*before write, iclass 17, count 0 2006.231.07:34:39.51#ibcon#enter sib2, iclass 17, count 0 2006.231.07:34:39.51#ibcon#flushed, iclass 17, count 0 2006.231.07:34:39.51#ibcon#about to write, iclass 17, count 0 2006.231.07:34:39.51#ibcon#wrote, iclass 17, count 0 2006.231.07:34:39.51#ibcon#about to read 3, iclass 17, count 0 2006.231.07:34:39.54#ibcon#read 3, iclass 17, count 0 2006.231.07:34:39.54#ibcon#about to read 4, iclass 17, count 0 2006.231.07:34:39.54#ibcon#read 4, iclass 17, count 0 2006.231.07:34:39.54#ibcon#about to read 5, iclass 17, count 0 2006.231.07:34:39.54#ibcon#read 5, iclass 17, count 0 2006.231.07:34:39.54#ibcon#about to read 6, iclass 17, count 0 2006.231.07:34:39.54#ibcon#read 6, iclass 17, count 0 2006.231.07:34:39.54#ibcon#end of sib2, iclass 17, count 0 2006.231.07:34:39.54#ibcon#*after write, iclass 17, count 0 2006.231.07:34:39.54#ibcon#*before return 0, iclass 17, count 0 2006.231.07:34:39.54#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:34:39.54#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:34:39.54#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:34:39.54#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:34:39.54$vc4f8/valo=6,772.99 2006.231.07:34:39.54#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.07:34:39.54#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.07:34:39.54#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:39.54#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:34:39.54#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:34:39.54#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:34:39.54#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:34:39.54#ibcon#first serial, iclass 19, count 0 2006.231.07:34:39.54#ibcon#enter sib2, iclass 19, count 0 2006.231.07:34:39.54#ibcon#flushed, iclass 19, count 0 2006.231.07:34:39.54#ibcon#about to write, iclass 19, count 0 2006.231.07:34:39.54#ibcon#wrote, iclass 19, count 0 2006.231.07:34:39.54#ibcon#about to read 3, iclass 19, count 0 2006.231.07:34:39.56#ibcon#read 3, iclass 19, count 0 2006.231.07:34:39.56#ibcon#about to read 4, iclass 19, count 0 2006.231.07:34:39.56#ibcon#read 4, iclass 19, count 0 2006.231.07:34:39.56#ibcon#about to read 5, iclass 19, count 0 2006.231.07:34:39.56#ibcon#read 5, iclass 19, count 0 2006.231.07:34:39.56#ibcon#about to read 6, iclass 19, count 0 2006.231.07:34:39.56#ibcon#read 6, iclass 19, count 0 2006.231.07:34:39.56#ibcon#end of sib2, iclass 19, count 0 2006.231.07:34:39.56#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:34:39.56#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:34:39.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:34:39.56#ibcon#*before write, iclass 19, count 0 2006.231.07:34:39.56#ibcon#enter sib2, iclass 19, count 0 2006.231.07:34:39.56#ibcon#flushed, iclass 19, count 0 2006.231.07:34:39.56#ibcon#about to write, iclass 19, count 0 2006.231.07:34:39.56#ibcon#wrote, iclass 19, count 0 2006.231.07:34:39.56#ibcon#about to read 3, iclass 19, count 0 2006.231.07:34:39.60#ibcon#read 3, iclass 19, count 0 2006.231.07:34:39.60#ibcon#about to read 4, iclass 19, count 0 2006.231.07:34:39.60#ibcon#read 4, iclass 19, count 0 2006.231.07:34:39.60#ibcon#about to read 5, iclass 19, count 0 2006.231.07:34:39.60#ibcon#read 5, iclass 19, count 0 2006.231.07:34:39.60#ibcon#about to read 6, iclass 19, count 0 2006.231.07:34:39.60#ibcon#read 6, iclass 19, count 0 2006.231.07:34:39.60#ibcon#end of sib2, iclass 19, count 0 2006.231.07:34:39.60#ibcon#*after write, iclass 19, count 0 2006.231.07:34:39.60#ibcon#*before return 0, iclass 19, count 0 2006.231.07:34:39.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:34:39.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:34:39.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:34:39.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:34:39.60$vc4f8/va=6,6 2006.231.07:34:39.60#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.231.07:34:39.60#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.231.07:34:39.60#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:39.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:34:39.66#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:34:39.66#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:34:39.66#ibcon#enter wrdev, iclass 21, count 2 2006.231.07:34:39.66#ibcon#first serial, iclass 21, count 2 2006.231.07:34:39.66#ibcon#enter sib2, iclass 21, count 2 2006.231.07:34:39.66#ibcon#flushed, iclass 21, count 2 2006.231.07:34:39.66#ibcon#about to write, iclass 21, count 2 2006.231.07:34:39.66#ibcon#wrote, iclass 21, count 2 2006.231.07:34:39.66#ibcon#about to read 3, iclass 21, count 2 2006.231.07:34:39.68#ibcon#read 3, iclass 21, count 2 2006.231.07:34:39.68#ibcon#about to read 4, iclass 21, count 2 2006.231.07:34:39.68#ibcon#read 4, iclass 21, count 2 2006.231.07:34:39.68#ibcon#about to read 5, iclass 21, count 2 2006.231.07:34:39.68#ibcon#read 5, iclass 21, count 2 2006.231.07:34:39.68#ibcon#about to read 6, iclass 21, count 2 2006.231.07:34:39.68#ibcon#read 6, iclass 21, count 2 2006.231.07:34:39.68#ibcon#end of sib2, iclass 21, count 2 2006.231.07:34:39.68#ibcon#*mode == 0, iclass 21, count 2 2006.231.07:34:39.68#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.231.07:34:39.68#ibcon#[25=AT06-06\r\n] 2006.231.07:34:39.68#ibcon#*before write, iclass 21, count 2 2006.231.07:34:39.68#ibcon#enter sib2, iclass 21, count 2 2006.231.07:34:39.68#ibcon#flushed, iclass 21, count 2 2006.231.07:34:39.68#ibcon#about to write, iclass 21, count 2 2006.231.07:34:39.68#ibcon#wrote, iclass 21, count 2 2006.231.07:34:39.68#ibcon#about to read 3, iclass 21, count 2 2006.231.07:34:39.71#ibcon#read 3, iclass 21, count 2 2006.231.07:34:39.71#ibcon#about to read 4, iclass 21, count 2 2006.231.07:34:39.71#ibcon#read 4, iclass 21, count 2 2006.231.07:34:39.71#ibcon#about to read 5, iclass 21, count 2 2006.231.07:34:39.71#ibcon#read 5, iclass 21, count 2 2006.231.07:34:39.71#ibcon#about to read 6, iclass 21, count 2 2006.231.07:34:39.71#ibcon#read 6, iclass 21, count 2 2006.231.07:34:39.71#ibcon#end of sib2, iclass 21, count 2 2006.231.07:34:39.71#ibcon#*after write, iclass 21, count 2 2006.231.07:34:39.71#ibcon#*before return 0, iclass 21, count 2 2006.231.07:34:39.71#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:34:39.71#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:34:39.71#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.231.07:34:39.71#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:39.71#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:34:39.83#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:34:39.83#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:34:39.83#ibcon#enter wrdev, iclass 21, count 0 2006.231.07:34:39.83#ibcon#first serial, iclass 21, count 0 2006.231.07:34:39.83#ibcon#enter sib2, iclass 21, count 0 2006.231.07:34:39.83#ibcon#flushed, iclass 21, count 0 2006.231.07:34:39.83#ibcon#about to write, iclass 21, count 0 2006.231.07:34:39.83#ibcon#wrote, iclass 21, count 0 2006.231.07:34:39.83#ibcon#about to read 3, iclass 21, count 0 2006.231.07:34:39.85#ibcon#read 3, iclass 21, count 0 2006.231.07:34:39.85#ibcon#about to read 4, iclass 21, count 0 2006.231.07:34:39.85#ibcon#read 4, iclass 21, count 0 2006.231.07:34:39.85#ibcon#about to read 5, iclass 21, count 0 2006.231.07:34:39.85#ibcon#read 5, iclass 21, count 0 2006.231.07:34:39.85#ibcon#about to read 6, iclass 21, count 0 2006.231.07:34:39.85#ibcon#read 6, iclass 21, count 0 2006.231.07:34:39.85#ibcon#end of sib2, iclass 21, count 0 2006.231.07:34:39.85#ibcon#*mode == 0, iclass 21, count 0 2006.231.07:34:39.85#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.07:34:39.85#ibcon#[25=USB\r\n] 2006.231.07:34:39.85#ibcon#*before write, iclass 21, count 0 2006.231.07:34:39.85#ibcon#enter sib2, iclass 21, count 0 2006.231.07:34:39.85#ibcon#flushed, iclass 21, count 0 2006.231.07:34:39.85#ibcon#about to write, iclass 21, count 0 2006.231.07:34:39.85#ibcon#wrote, iclass 21, count 0 2006.231.07:34:39.85#ibcon#about to read 3, iclass 21, count 0 2006.231.07:34:39.88#ibcon#read 3, iclass 21, count 0 2006.231.07:34:39.88#ibcon#about to read 4, iclass 21, count 0 2006.231.07:34:39.88#ibcon#read 4, iclass 21, count 0 2006.231.07:34:39.88#ibcon#about to read 5, iclass 21, count 0 2006.231.07:34:39.88#ibcon#read 5, iclass 21, count 0 2006.231.07:34:39.88#ibcon#about to read 6, iclass 21, count 0 2006.231.07:34:39.88#ibcon#read 6, iclass 21, count 0 2006.231.07:34:39.88#ibcon#end of sib2, iclass 21, count 0 2006.231.07:34:39.88#ibcon#*after write, iclass 21, count 0 2006.231.07:34:39.88#ibcon#*before return 0, iclass 21, count 0 2006.231.07:34:39.88#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:34:39.88#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:34:39.88#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.07:34:39.88#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.07:34:39.88$vc4f8/valo=7,832.99 2006.231.07:34:39.88#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.231.07:34:39.88#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.231.07:34:39.88#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:39.88#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:34:39.88#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:34:39.88#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:34:39.88#ibcon#enter wrdev, iclass 23, count 0 2006.231.07:34:39.88#ibcon#first serial, iclass 23, count 0 2006.231.07:34:39.88#ibcon#enter sib2, iclass 23, count 0 2006.231.07:34:39.88#ibcon#flushed, iclass 23, count 0 2006.231.07:34:39.88#ibcon#about to write, iclass 23, count 0 2006.231.07:34:39.88#ibcon#wrote, iclass 23, count 0 2006.231.07:34:39.88#ibcon#about to read 3, iclass 23, count 0 2006.231.07:34:39.90#ibcon#read 3, iclass 23, count 0 2006.231.07:34:39.90#ibcon#about to read 4, iclass 23, count 0 2006.231.07:34:39.90#ibcon#read 4, iclass 23, count 0 2006.231.07:34:39.90#ibcon#about to read 5, iclass 23, count 0 2006.231.07:34:39.90#ibcon#read 5, iclass 23, count 0 2006.231.07:34:39.90#ibcon#about to read 6, iclass 23, count 0 2006.231.07:34:39.90#ibcon#read 6, iclass 23, count 0 2006.231.07:34:39.90#ibcon#end of sib2, iclass 23, count 0 2006.231.07:34:39.90#ibcon#*mode == 0, iclass 23, count 0 2006.231.07:34:39.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.07:34:39.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:34:39.90#ibcon#*before write, iclass 23, count 0 2006.231.07:34:39.90#ibcon#enter sib2, iclass 23, count 0 2006.231.07:34:39.90#ibcon#flushed, iclass 23, count 0 2006.231.07:34:39.90#ibcon#about to write, iclass 23, count 0 2006.231.07:34:39.90#ibcon#wrote, iclass 23, count 0 2006.231.07:34:39.90#ibcon#about to read 3, iclass 23, count 0 2006.231.07:34:39.94#ibcon#read 3, iclass 23, count 0 2006.231.07:34:39.94#ibcon#about to read 4, iclass 23, count 0 2006.231.07:34:39.94#ibcon#read 4, iclass 23, count 0 2006.231.07:34:39.94#ibcon#about to read 5, iclass 23, count 0 2006.231.07:34:39.94#ibcon#read 5, iclass 23, count 0 2006.231.07:34:39.94#ibcon#about to read 6, iclass 23, count 0 2006.231.07:34:39.94#ibcon#read 6, iclass 23, count 0 2006.231.07:34:39.94#ibcon#end of sib2, iclass 23, count 0 2006.231.07:34:39.94#ibcon#*after write, iclass 23, count 0 2006.231.07:34:39.94#ibcon#*before return 0, iclass 23, count 0 2006.231.07:34:39.94#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:34:39.94#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:34:39.94#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.07:34:39.94#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.07:34:39.94$vc4f8/va=7,6 2006.231.07:34:39.94#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.231.07:34:39.94#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.231.07:34:39.94#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:39.94#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:34:40.00#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:34:40.00#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:34:40.00#ibcon#enter wrdev, iclass 25, count 2 2006.231.07:34:40.00#ibcon#first serial, iclass 25, count 2 2006.231.07:34:40.00#ibcon#enter sib2, iclass 25, count 2 2006.231.07:34:40.00#ibcon#flushed, iclass 25, count 2 2006.231.07:34:40.00#ibcon#about to write, iclass 25, count 2 2006.231.07:34:40.00#ibcon#wrote, iclass 25, count 2 2006.231.07:34:40.00#ibcon#about to read 3, iclass 25, count 2 2006.231.07:34:40.02#ibcon#read 3, iclass 25, count 2 2006.231.07:34:40.02#ibcon#about to read 4, iclass 25, count 2 2006.231.07:34:40.02#ibcon#read 4, iclass 25, count 2 2006.231.07:34:40.02#ibcon#about to read 5, iclass 25, count 2 2006.231.07:34:40.02#ibcon#read 5, iclass 25, count 2 2006.231.07:34:40.02#ibcon#about to read 6, iclass 25, count 2 2006.231.07:34:40.02#ibcon#read 6, iclass 25, count 2 2006.231.07:34:40.02#ibcon#end of sib2, iclass 25, count 2 2006.231.07:34:40.02#ibcon#*mode == 0, iclass 25, count 2 2006.231.07:34:40.02#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.231.07:34:40.02#ibcon#[25=AT07-06\r\n] 2006.231.07:34:40.02#ibcon#*before write, iclass 25, count 2 2006.231.07:34:40.02#ibcon#enter sib2, iclass 25, count 2 2006.231.07:34:40.02#ibcon#flushed, iclass 25, count 2 2006.231.07:34:40.02#ibcon#about to write, iclass 25, count 2 2006.231.07:34:40.02#ibcon#wrote, iclass 25, count 2 2006.231.07:34:40.02#ibcon#about to read 3, iclass 25, count 2 2006.231.07:34:40.05#ibcon#read 3, iclass 25, count 2 2006.231.07:34:40.05#ibcon#about to read 4, iclass 25, count 2 2006.231.07:34:40.05#ibcon#read 4, iclass 25, count 2 2006.231.07:34:40.05#ibcon#about to read 5, iclass 25, count 2 2006.231.07:34:40.05#ibcon#read 5, iclass 25, count 2 2006.231.07:34:40.05#ibcon#about to read 6, iclass 25, count 2 2006.231.07:34:40.05#ibcon#read 6, iclass 25, count 2 2006.231.07:34:40.05#ibcon#end of sib2, iclass 25, count 2 2006.231.07:34:40.05#ibcon#*after write, iclass 25, count 2 2006.231.07:34:40.05#ibcon#*before return 0, iclass 25, count 2 2006.231.07:34:40.05#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:34:40.05#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:34:40.05#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.231.07:34:40.05#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:40.05#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:34:40.17#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:34:40.17#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:34:40.17#ibcon#enter wrdev, iclass 25, count 0 2006.231.07:34:40.17#ibcon#first serial, iclass 25, count 0 2006.231.07:34:40.17#ibcon#enter sib2, iclass 25, count 0 2006.231.07:34:40.17#ibcon#flushed, iclass 25, count 0 2006.231.07:34:40.17#ibcon#about to write, iclass 25, count 0 2006.231.07:34:40.17#ibcon#wrote, iclass 25, count 0 2006.231.07:34:40.17#ibcon#about to read 3, iclass 25, count 0 2006.231.07:34:40.19#ibcon#read 3, iclass 25, count 0 2006.231.07:34:40.19#ibcon#about to read 4, iclass 25, count 0 2006.231.07:34:40.19#ibcon#read 4, iclass 25, count 0 2006.231.07:34:40.19#ibcon#about to read 5, iclass 25, count 0 2006.231.07:34:40.19#ibcon#read 5, iclass 25, count 0 2006.231.07:34:40.19#ibcon#about to read 6, iclass 25, count 0 2006.231.07:34:40.19#ibcon#read 6, iclass 25, count 0 2006.231.07:34:40.19#ibcon#end of sib2, iclass 25, count 0 2006.231.07:34:40.19#ibcon#*mode == 0, iclass 25, count 0 2006.231.07:34:40.19#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.07:34:40.19#ibcon#[25=USB\r\n] 2006.231.07:34:40.19#ibcon#*before write, iclass 25, count 0 2006.231.07:34:40.19#ibcon#enter sib2, iclass 25, count 0 2006.231.07:34:40.19#ibcon#flushed, iclass 25, count 0 2006.231.07:34:40.19#ibcon#about to write, iclass 25, count 0 2006.231.07:34:40.19#ibcon#wrote, iclass 25, count 0 2006.231.07:34:40.19#ibcon#about to read 3, iclass 25, count 0 2006.231.07:34:40.23#ibcon#read 3, iclass 25, count 0 2006.231.07:34:40.23#ibcon#about to read 4, iclass 25, count 0 2006.231.07:34:40.23#ibcon#read 4, iclass 25, count 0 2006.231.07:34:40.23#ibcon#about to read 5, iclass 25, count 0 2006.231.07:34:40.23#ibcon#read 5, iclass 25, count 0 2006.231.07:34:40.23#ibcon#about to read 6, iclass 25, count 0 2006.231.07:34:40.23#ibcon#read 6, iclass 25, count 0 2006.231.07:34:40.23#ibcon#end of sib2, iclass 25, count 0 2006.231.07:34:40.23#ibcon#*after write, iclass 25, count 0 2006.231.07:34:40.23#ibcon#*before return 0, iclass 25, count 0 2006.231.07:34:40.23#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:34:40.23#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:34:40.23#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.07:34:40.23#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.07:34:40.23$vc4f8/valo=8,852.99 2006.231.07:34:40.23#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.231.07:34:40.23#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.231.07:34:40.23#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:40.23#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:34:40.23#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:34:40.23#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:34:40.23#ibcon#enter wrdev, iclass 27, count 0 2006.231.07:34:40.23#ibcon#first serial, iclass 27, count 0 2006.231.07:34:40.23#ibcon#enter sib2, iclass 27, count 0 2006.231.07:34:40.23#ibcon#flushed, iclass 27, count 0 2006.231.07:34:40.23#ibcon#about to write, iclass 27, count 0 2006.231.07:34:40.23#ibcon#wrote, iclass 27, count 0 2006.231.07:34:40.23#ibcon#about to read 3, iclass 27, count 0 2006.231.07:34:40.24#ibcon#read 3, iclass 27, count 0 2006.231.07:34:40.24#ibcon#about to read 4, iclass 27, count 0 2006.231.07:34:40.24#ibcon#read 4, iclass 27, count 0 2006.231.07:34:40.24#ibcon#about to read 5, iclass 27, count 0 2006.231.07:34:40.24#ibcon#read 5, iclass 27, count 0 2006.231.07:34:40.24#ibcon#about to read 6, iclass 27, count 0 2006.231.07:34:40.24#ibcon#read 6, iclass 27, count 0 2006.231.07:34:40.24#ibcon#end of sib2, iclass 27, count 0 2006.231.07:34:40.24#ibcon#*mode == 0, iclass 27, count 0 2006.231.07:34:40.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.07:34:40.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:34:40.24#ibcon#*before write, iclass 27, count 0 2006.231.07:34:40.24#ibcon#enter sib2, iclass 27, count 0 2006.231.07:34:40.24#ibcon#flushed, iclass 27, count 0 2006.231.07:34:40.24#ibcon#about to write, iclass 27, count 0 2006.231.07:34:40.24#ibcon#wrote, iclass 27, count 0 2006.231.07:34:40.24#ibcon#about to read 3, iclass 27, count 0 2006.231.07:34:40.28#ibcon#read 3, iclass 27, count 0 2006.231.07:34:40.28#ibcon#about to read 4, iclass 27, count 0 2006.231.07:34:40.28#ibcon#read 4, iclass 27, count 0 2006.231.07:34:40.28#ibcon#about to read 5, iclass 27, count 0 2006.231.07:34:40.28#ibcon#read 5, iclass 27, count 0 2006.231.07:34:40.28#ibcon#about to read 6, iclass 27, count 0 2006.231.07:34:40.28#ibcon#read 6, iclass 27, count 0 2006.231.07:34:40.28#ibcon#end of sib2, iclass 27, count 0 2006.231.07:34:40.28#ibcon#*after write, iclass 27, count 0 2006.231.07:34:40.28#ibcon#*before return 0, iclass 27, count 0 2006.231.07:34:40.28#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:34:40.28#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:34:40.28#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.07:34:40.28#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.07:34:40.28$vc4f8/va=8,6 2006.231.07:34:40.28#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.231.07:34:40.28#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.231.07:34:40.28#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:40.28#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:34:40.35#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:34:40.35#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:34:40.35#ibcon#enter wrdev, iclass 29, count 2 2006.231.07:34:40.35#ibcon#first serial, iclass 29, count 2 2006.231.07:34:40.35#ibcon#enter sib2, iclass 29, count 2 2006.231.07:34:40.35#ibcon#flushed, iclass 29, count 2 2006.231.07:34:40.35#ibcon#about to write, iclass 29, count 2 2006.231.07:34:40.35#ibcon#wrote, iclass 29, count 2 2006.231.07:34:40.35#ibcon#about to read 3, iclass 29, count 2 2006.231.07:34:40.37#ibcon#read 3, iclass 29, count 2 2006.231.07:34:40.37#ibcon#about to read 4, iclass 29, count 2 2006.231.07:34:40.37#ibcon#read 4, iclass 29, count 2 2006.231.07:34:40.37#ibcon#about to read 5, iclass 29, count 2 2006.231.07:34:40.37#ibcon#read 5, iclass 29, count 2 2006.231.07:34:40.37#ibcon#about to read 6, iclass 29, count 2 2006.231.07:34:40.37#ibcon#read 6, iclass 29, count 2 2006.231.07:34:40.37#ibcon#end of sib2, iclass 29, count 2 2006.231.07:34:40.37#ibcon#*mode == 0, iclass 29, count 2 2006.231.07:34:40.37#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.231.07:34:40.37#ibcon#[25=AT08-06\r\n] 2006.231.07:34:40.37#ibcon#*before write, iclass 29, count 2 2006.231.07:34:40.37#ibcon#enter sib2, iclass 29, count 2 2006.231.07:34:40.37#ibcon#flushed, iclass 29, count 2 2006.231.07:34:40.37#ibcon#about to write, iclass 29, count 2 2006.231.07:34:40.37#ibcon#wrote, iclass 29, count 2 2006.231.07:34:40.37#ibcon#about to read 3, iclass 29, count 2 2006.231.07:34:40.40#ibcon#read 3, iclass 29, count 2 2006.231.07:34:40.40#ibcon#about to read 4, iclass 29, count 2 2006.231.07:34:40.40#ibcon#read 4, iclass 29, count 2 2006.231.07:34:40.40#ibcon#about to read 5, iclass 29, count 2 2006.231.07:34:40.40#ibcon#read 5, iclass 29, count 2 2006.231.07:34:40.40#ibcon#about to read 6, iclass 29, count 2 2006.231.07:34:40.40#ibcon#read 6, iclass 29, count 2 2006.231.07:34:40.40#ibcon#end of sib2, iclass 29, count 2 2006.231.07:34:40.40#ibcon#*after write, iclass 29, count 2 2006.231.07:34:40.40#ibcon#*before return 0, iclass 29, count 2 2006.231.07:34:40.40#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:34:40.40#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:34:40.40#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.231.07:34:40.40#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:40.40#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:34:40.52#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:34:40.52#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:34:40.52#ibcon#enter wrdev, iclass 29, count 0 2006.231.07:34:40.52#ibcon#first serial, iclass 29, count 0 2006.231.07:34:40.52#ibcon#enter sib2, iclass 29, count 0 2006.231.07:34:40.52#ibcon#flushed, iclass 29, count 0 2006.231.07:34:40.52#ibcon#about to write, iclass 29, count 0 2006.231.07:34:40.52#ibcon#wrote, iclass 29, count 0 2006.231.07:34:40.52#ibcon#about to read 3, iclass 29, count 0 2006.231.07:34:40.54#ibcon#read 3, iclass 29, count 0 2006.231.07:34:40.54#ibcon#about to read 4, iclass 29, count 0 2006.231.07:34:40.54#ibcon#read 4, iclass 29, count 0 2006.231.07:34:40.54#ibcon#about to read 5, iclass 29, count 0 2006.231.07:34:40.54#ibcon#read 5, iclass 29, count 0 2006.231.07:34:40.54#ibcon#about to read 6, iclass 29, count 0 2006.231.07:34:40.54#ibcon#read 6, iclass 29, count 0 2006.231.07:34:40.54#ibcon#end of sib2, iclass 29, count 0 2006.231.07:34:40.54#ibcon#*mode == 0, iclass 29, count 0 2006.231.07:34:40.54#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.07:34:40.54#ibcon#[25=USB\r\n] 2006.231.07:34:40.54#ibcon#*before write, iclass 29, count 0 2006.231.07:34:40.54#ibcon#enter sib2, iclass 29, count 0 2006.231.07:34:40.54#ibcon#flushed, iclass 29, count 0 2006.231.07:34:40.54#ibcon#about to write, iclass 29, count 0 2006.231.07:34:40.54#ibcon#wrote, iclass 29, count 0 2006.231.07:34:40.54#ibcon#about to read 3, iclass 29, count 0 2006.231.07:34:40.57#ibcon#read 3, iclass 29, count 0 2006.231.07:34:40.57#ibcon#about to read 4, iclass 29, count 0 2006.231.07:34:40.57#ibcon#read 4, iclass 29, count 0 2006.231.07:34:40.57#ibcon#about to read 5, iclass 29, count 0 2006.231.07:34:40.57#ibcon#read 5, iclass 29, count 0 2006.231.07:34:40.57#ibcon#about to read 6, iclass 29, count 0 2006.231.07:34:40.57#ibcon#read 6, iclass 29, count 0 2006.231.07:34:40.57#ibcon#end of sib2, iclass 29, count 0 2006.231.07:34:40.57#ibcon#*after write, iclass 29, count 0 2006.231.07:34:40.57#ibcon#*before return 0, iclass 29, count 0 2006.231.07:34:40.57#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:34:40.57#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:34:40.57#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.07:34:40.57#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.07:34:40.57$vc4f8/vblo=1,632.99 2006.231.07:34:40.57#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.231.07:34:40.57#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.231.07:34:40.57#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:40.57#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:34:40.57#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:34:40.57#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:34:40.57#ibcon#enter wrdev, iclass 31, count 0 2006.231.07:34:40.57#ibcon#first serial, iclass 31, count 0 2006.231.07:34:40.57#ibcon#enter sib2, iclass 31, count 0 2006.231.07:34:40.57#ibcon#flushed, iclass 31, count 0 2006.231.07:34:40.57#ibcon#about to write, iclass 31, count 0 2006.231.07:34:40.57#ibcon#wrote, iclass 31, count 0 2006.231.07:34:40.57#ibcon#about to read 3, iclass 31, count 0 2006.231.07:34:40.59#ibcon#read 3, iclass 31, count 0 2006.231.07:34:40.59#ibcon#about to read 4, iclass 31, count 0 2006.231.07:34:40.59#ibcon#read 4, iclass 31, count 0 2006.231.07:34:40.59#ibcon#about to read 5, iclass 31, count 0 2006.231.07:34:40.59#ibcon#read 5, iclass 31, count 0 2006.231.07:34:40.59#ibcon#about to read 6, iclass 31, count 0 2006.231.07:34:40.59#ibcon#read 6, iclass 31, count 0 2006.231.07:34:40.59#ibcon#end of sib2, iclass 31, count 0 2006.231.07:34:40.59#ibcon#*mode == 0, iclass 31, count 0 2006.231.07:34:40.59#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.07:34:40.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:34:40.59#ibcon#*before write, iclass 31, count 0 2006.231.07:34:40.59#ibcon#enter sib2, iclass 31, count 0 2006.231.07:34:40.59#ibcon#flushed, iclass 31, count 0 2006.231.07:34:40.59#ibcon#about to write, iclass 31, count 0 2006.231.07:34:40.59#ibcon#wrote, iclass 31, count 0 2006.231.07:34:40.59#ibcon#about to read 3, iclass 31, count 0 2006.231.07:34:40.63#ibcon#read 3, iclass 31, count 0 2006.231.07:34:40.63#ibcon#about to read 4, iclass 31, count 0 2006.231.07:34:40.63#ibcon#read 4, iclass 31, count 0 2006.231.07:34:40.63#ibcon#about to read 5, iclass 31, count 0 2006.231.07:34:40.63#ibcon#read 5, iclass 31, count 0 2006.231.07:34:40.63#ibcon#about to read 6, iclass 31, count 0 2006.231.07:34:40.63#ibcon#read 6, iclass 31, count 0 2006.231.07:34:40.63#ibcon#end of sib2, iclass 31, count 0 2006.231.07:34:40.63#ibcon#*after write, iclass 31, count 0 2006.231.07:34:40.63#ibcon#*before return 0, iclass 31, count 0 2006.231.07:34:40.63#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:34:40.63#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:34:40.63#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.07:34:40.63#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.07:34:40.63$vc4f8/vb=1,4 2006.231.07:34:40.63#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.231.07:34:40.63#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.231.07:34:40.63#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:40.63#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:34:40.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:34:40.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:34:40.63#ibcon#enter wrdev, iclass 33, count 2 2006.231.07:34:40.63#ibcon#first serial, iclass 33, count 2 2006.231.07:34:40.63#ibcon#enter sib2, iclass 33, count 2 2006.231.07:34:40.63#ibcon#flushed, iclass 33, count 2 2006.231.07:34:40.63#ibcon#about to write, iclass 33, count 2 2006.231.07:34:40.63#ibcon#wrote, iclass 33, count 2 2006.231.07:34:40.63#ibcon#about to read 3, iclass 33, count 2 2006.231.07:34:40.65#ibcon#read 3, iclass 33, count 2 2006.231.07:34:40.65#ibcon#about to read 4, iclass 33, count 2 2006.231.07:34:40.65#ibcon#read 4, iclass 33, count 2 2006.231.07:34:40.65#ibcon#about to read 5, iclass 33, count 2 2006.231.07:34:40.65#ibcon#read 5, iclass 33, count 2 2006.231.07:34:40.65#ibcon#about to read 6, iclass 33, count 2 2006.231.07:34:40.65#ibcon#read 6, iclass 33, count 2 2006.231.07:34:40.65#ibcon#end of sib2, iclass 33, count 2 2006.231.07:34:40.65#ibcon#*mode == 0, iclass 33, count 2 2006.231.07:34:40.65#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.231.07:34:40.65#ibcon#[27=AT01-04\r\n] 2006.231.07:34:40.65#ibcon#*before write, iclass 33, count 2 2006.231.07:34:40.65#ibcon#enter sib2, iclass 33, count 2 2006.231.07:34:40.65#ibcon#flushed, iclass 33, count 2 2006.231.07:34:40.65#ibcon#about to write, iclass 33, count 2 2006.231.07:34:40.65#ibcon#wrote, iclass 33, count 2 2006.231.07:34:40.65#ibcon#about to read 3, iclass 33, count 2 2006.231.07:34:40.68#ibcon#read 3, iclass 33, count 2 2006.231.07:34:40.68#ibcon#about to read 4, iclass 33, count 2 2006.231.07:34:40.68#ibcon#read 4, iclass 33, count 2 2006.231.07:34:40.68#ibcon#about to read 5, iclass 33, count 2 2006.231.07:34:40.68#ibcon#read 5, iclass 33, count 2 2006.231.07:34:40.68#ibcon#about to read 6, iclass 33, count 2 2006.231.07:34:40.68#ibcon#read 6, iclass 33, count 2 2006.231.07:34:40.68#ibcon#end of sib2, iclass 33, count 2 2006.231.07:34:40.68#ibcon#*after write, iclass 33, count 2 2006.231.07:34:40.68#ibcon#*before return 0, iclass 33, count 2 2006.231.07:34:40.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:34:40.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:34:40.68#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.231.07:34:40.68#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:40.68#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:34:40.80#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:34:40.80#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:34:40.80#ibcon#enter wrdev, iclass 33, count 0 2006.231.07:34:40.80#ibcon#first serial, iclass 33, count 0 2006.231.07:34:40.80#ibcon#enter sib2, iclass 33, count 0 2006.231.07:34:40.80#ibcon#flushed, iclass 33, count 0 2006.231.07:34:40.80#ibcon#about to write, iclass 33, count 0 2006.231.07:34:40.80#ibcon#wrote, iclass 33, count 0 2006.231.07:34:40.80#ibcon#about to read 3, iclass 33, count 0 2006.231.07:34:40.82#ibcon#read 3, iclass 33, count 0 2006.231.07:34:40.82#ibcon#about to read 4, iclass 33, count 0 2006.231.07:34:40.82#ibcon#read 4, iclass 33, count 0 2006.231.07:34:40.82#ibcon#about to read 5, iclass 33, count 0 2006.231.07:34:40.82#ibcon#read 5, iclass 33, count 0 2006.231.07:34:40.82#ibcon#about to read 6, iclass 33, count 0 2006.231.07:34:40.82#ibcon#read 6, iclass 33, count 0 2006.231.07:34:40.82#ibcon#end of sib2, iclass 33, count 0 2006.231.07:34:40.82#ibcon#*mode == 0, iclass 33, count 0 2006.231.07:34:40.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.07:34:40.82#ibcon#[27=USB\r\n] 2006.231.07:34:40.82#ibcon#*before write, iclass 33, count 0 2006.231.07:34:40.82#ibcon#enter sib2, iclass 33, count 0 2006.231.07:34:40.82#ibcon#flushed, iclass 33, count 0 2006.231.07:34:40.82#ibcon#about to write, iclass 33, count 0 2006.231.07:34:40.82#ibcon#wrote, iclass 33, count 0 2006.231.07:34:40.82#ibcon#about to read 3, iclass 33, count 0 2006.231.07:34:40.85#ibcon#read 3, iclass 33, count 0 2006.231.07:34:40.85#ibcon#about to read 4, iclass 33, count 0 2006.231.07:34:40.85#ibcon#read 4, iclass 33, count 0 2006.231.07:34:40.85#ibcon#about to read 5, iclass 33, count 0 2006.231.07:34:40.85#ibcon#read 5, iclass 33, count 0 2006.231.07:34:40.85#ibcon#about to read 6, iclass 33, count 0 2006.231.07:34:40.85#ibcon#read 6, iclass 33, count 0 2006.231.07:34:40.85#ibcon#end of sib2, iclass 33, count 0 2006.231.07:34:40.85#ibcon#*after write, iclass 33, count 0 2006.231.07:34:40.85#ibcon#*before return 0, iclass 33, count 0 2006.231.07:34:40.85#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:34:40.85#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:34:40.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.07:34:40.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.07:34:40.85$vc4f8/vblo=2,640.99 2006.231.07:34:40.85#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.231.07:34:40.85#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.231.07:34:40.85#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:40.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:34:40.85#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:34:40.85#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:34:40.85#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:34:40.85#ibcon#first serial, iclass 35, count 0 2006.231.07:34:40.85#ibcon#enter sib2, iclass 35, count 0 2006.231.07:34:40.85#ibcon#flushed, iclass 35, count 0 2006.231.07:34:40.85#ibcon#about to write, iclass 35, count 0 2006.231.07:34:40.85#ibcon#wrote, iclass 35, count 0 2006.231.07:34:40.85#ibcon#about to read 3, iclass 35, count 0 2006.231.07:34:40.87#ibcon#read 3, iclass 35, count 0 2006.231.07:34:40.87#ibcon#about to read 4, iclass 35, count 0 2006.231.07:34:40.87#ibcon#read 4, iclass 35, count 0 2006.231.07:34:40.87#ibcon#about to read 5, iclass 35, count 0 2006.231.07:34:40.87#ibcon#read 5, iclass 35, count 0 2006.231.07:34:40.87#ibcon#about to read 6, iclass 35, count 0 2006.231.07:34:40.87#ibcon#read 6, iclass 35, count 0 2006.231.07:34:40.87#ibcon#end of sib2, iclass 35, count 0 2006.231.07:34:40.87#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:34:40.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:34:40.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:34:40.87#ibcon#*before write, iclass 35, count 0 2006.231.07:34:40.87#ibcon#enter sib2, iclass 35, count 0 2006.231.07:34:40.87#ibcon#flushed, iclass 35, count 0 2006.231.07:34:40.87#ibcon#about to write, iclass 35, count 0 2006.231.07:34:40.87#ibcon#wrote, iclass 35, count 0 2006.231.07:34:40.87#ibcon#about to read 3, iclass 35, count 0 2006.231.07:34:40.91#ibcon#read 3, iclass 35, count 0 2006.231.07:34:40.91#ibcon#about to read 4, iclass 35, count 0 2006.231.07:34:40.91#ibcon#read 4, iclass 35, count 0 2006.231.07:34:40.91#ibcon#about to read 5, iclass 35, count 0 2006.231.07:34:40.91#ibcon#read 5, iclass 35, count 0 2006.231.07:34:40.91#ibcon#about to read 6, iclass 35, count 0 2006.231.07:34:40.91#ibcon#read 6, iclass 35, count 0 2006.231.07:34:40.91#ibcon#end of sib2, iclass 35, count 0 2006.231.07:34:40.91#ibcon#*after write, iclass 35, count 0 2006.231.07:34:40.91#ibcon#*before return 0, iclass 35, count 0 2006.231.07:34:40.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:34:40.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:34:40.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:34:40.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:34:40.91$vc4f8/vb=2,4 2006.231.07:34:40.91#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.231.07:34:40.91#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.231.07:34:40.91#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:40.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:34:40.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:34:40.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:34:40.97#ibcon#enter wrdev, iclass 37, count 2 2006.231.07:34:40.97#ibcon#first serial, iclass 37, count 2 2006.231.07:34:40.97#ibcon#enter sib2, iclass 37, count 2 2006.231.07:34:40.97#ibcon#flushed, iclass 37, count 2 2006.231.07:34:40.97#ibcon#about to write, iclass 37, count 2 2006.231.07:34:40.97#ibcon#wrote, iclass 37, count 2 2006.231.07:34:40.97#ibcon#about to read 3, iclass 37, count 2 2006.231.07:34:41.00#ibcon#read 3, iclass 37, count 2 2006.231.07:34:41.00#ibcon#about to read 4, iclass 37, count 2 2006.231.07:34:41.00#ibcon#read 4, iclass 37, count 2 2006.231.07:34:41.00#ibcon#about to read 5, iclass 37, count 2 2006.231.07:34:41.00#ibcon#read 5, iclass 37, count 2 2006.231.07:34:41.00#ibcon#about to read 6, iclass 37, count 2 2006.231.07:34:41.00#ibcon#read 6, iclass 37, count 2 2006.231.07:34:41.00#ibcon#end of sib2, iclass 37, count 2 2006.231.07:34:41.00#ibcon#*mode == 0, iclass 37, count 2 2006.231.07:34:41.00#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.231.07:34:41.00#ibcon#[27=AT02-04\r\n] 2006.231.07:34:41.00#ibcon#*before write, iclass 37, count 2 2006.231.07:34:41.00#ibcon#enter sib2, iclass 37, count 2 2006.231.07:34:41.00#ibcon#flushed, iclass 37, count 2 2006.231.07:34:41.00#ibcon#about to write, iclass 37, count 2 2006.231.07:34:41.00#ibcon#wrote, iclass 37, count 2 2006.231.07:34:41.00#ibcon#about to read 3, iclass 37, count 2 2006.231.07:34:41.03#ibcon#read 3, iclass 37, count 2 2006.231.07:34:41.03#ibcon#about to read 4, iclass 37, count 2 2006.231.07:34:41.03#ibcon#read 4, iclass 37, count 2 2006.231.07:34:41.03#ibcon#about to read 5, iclass 37, count 2 2006.231.07:34:41.03#ibcon#read 5, iclass 37, count 2 2006.231.07:34:41.03#ibcon#about to read 6, iclass 37, count 2 2006.231.07:34:41.03#ibcon#read 6, iclass 37, count 2 2006.231.07:34:41.03#ibcon#end of sib2, iclass 37, count 2 2006.231.07:34:41.03#ibcon#*after write, iclass 37, count 2 2006.231.07:34:41.03#ibcon#*before return 0, iclass 37, count 2 2006.231.07:34:41.03#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:34:41.03#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:34:41.03#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.231.07:34:41.03#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:41.03#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:34:41.15#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:34:41.15#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:34:41.15#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:34:41.15#ibcon#first serial, iclass 37, count 0 2006.231.07:34:41.15#ibcon#enter sib2, iclass 37, count 0 2006.231.07:34:41.15#ibcon#flushed, iclass 37, count 0 2006.231.07:34:41.15#ibcon#about to write, iclass 37, count 0 2006.231.07:34:41.15#ibcon#wrote, iclass 37, count 0 2006.231.07:34:41.15#ibcon#about to read 3, iclass 37, count 0 2006.231.07:34:41.17#ibcon#read 3, iclass 37, count 0 2006.231.07:34:41.17#ibcon#about to read 4, iclass 37, count 0 2006.231.07:34:41.17#ibcon#read 4, iclass 37, count 0 2006.231.07:34:41.17#ibcon#about to read 5, iclass 37, count 0 2006.231.07:34:41.17#ibcon#read 5, iclass 37, count 0 2006.231.07:34:41.17#ibcon#about to read 6, iclass 37, count 0 2006.231.07:34:41.17#ibcon#read 6, iclass 37, count 0 2006.231.07:34:41.17#ibcon#end of sib2, iclass 37, count 0 2006.231.07:34:41.17#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:34:41.17#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:34:41.17#ibcon#[27=USB\r\n] 2006.231.07:34:41.17#ibcon#*before write, iclass 37, count 0 2006.231.07:34:41.17#ibcon#enter sib2, iclass 37, count 0 2006.231.07:34:41.17#ibcon#flushed, iclass 37, count 0 2006.231.07:34:41.17#ibcon#about to write, iclass 37, count 0 2006.231.07:34:41.17#ibcon#wrote, iclass 37, count 0 2006.231.07:34:41.17#ibcon#about to read 3, iclass 37, count 0 2006.231.07:34:41.20#ibcon#read 3, iclass 37, count 0 2006.231.07:34:41.20#ibcon#about to read 4, iclass 37, count 0 2006.231.07:34:41.20#ibcon#read 4, iclass 37, count 0 2006.231.07:34:41.20#ibcon#about to read 5, iclass 37, count 0 2006.231.07:34:41.20#ibcon#read 5, iclass 37, count 0 2006.231.07:34:41.20#ibcon#about to read 6, iclass 37, count 0 2006.231.07:34:41.20#ibcon#read 6, iclass 37, count 0 2006.231.07:34:41.20#ibcon#end of sib2, iclass 37, count 0 2006.231.07:34:41.20#ibcon#*after write, iclass 37, count 0 2006.231.07:34:41.20#ibcon#*before return 0, iclass 37, count 0 2006.231.07:34:41.20#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:34:41.20#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:34:41.20#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:34:41.20#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:34:41.20$vc4f8/vblo=3,656.99 2006.231.07:34:41.20#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.07:34:41.20#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.07:34:41.20#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:41.20#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:34:41.20#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:34:41.20#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:34:41.20#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:34:41.20#ibcon#first serial, iclass 39, count 0 2006.231.07:34:41.20#ibcon#enter sib2, iclass 39, count 0 2006.231.07:34:41.20#ibcon#flushed, iclass 39, count 0 2006.231.07:34:41.20#ibcon#about to write, iclass 39, count 0 2006.231.07:34:41.20#ibcon#wrote, iclass 39, count 0 2006.231.07:34:41.20#ibcon#about to read 3, iclass 39, count 0 2006.231.07:34:41.22#ibcon#read 3, iclass 39, count 0 2006.231.07:34:41.22#ibcon#about to read 4, iclass 39, count 0 2006.231.07:34:41.22#ibcon#read 4, iclass 39, count 0 2006.231.07:34:41.22#ibcon#about to read 5, iclass 39, count 0 2006.231.07:34:41.22#ibcon#read 5, iclass 39, count 0 2006.231.07:34:41.22#ibcon#about to read 6, iclass 39, count 0 2006.231.07:34:41.22#ibcon#read 6, iclass 39, count 0 2006.231.07:34:41.22#ibcon#end of sib2, iclass 39, count 0 2006.231.07:34:41.22#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:34:41.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:34:41.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:34:41.22#ibcon#*before write, iclass 39, count 0 2006.231.07:34:41.22#ibcon#enter sib2, iclass 39, count 0 2006.231.07:34:41.22#ibcon#flushed, iclass 39, count 0 2006.231.07:34:41.22#ibcon#about to write, iclass 39, count 0 2006.231.07:34:41.22#ibcon#wrote, iclass 39, count 0 2006.231.07:34:41.22#ibcon#about to read 3, iclass 39, count 0 2006.231.07:34:41.26#ibcon#read 3, iclass 39, count 0 2006.231.07:34:41.26#ibcon#about to read 4, iclass 39, count 0 2006.231.07:34:41.26#ibcon#read 4, iclass 39, count 0 2006.231.07:34:41.26#ibcon#about to read 5, iclass 39, count 0 2006.231.07:34:41.26#ibcon#read 5, iclass 39, count 0 2006.231.07:34:41.26#ibcon#about to read 6, iclass 39, count 0 2006.231.07:34:41.26#ibcon#read 6, iclass 39, count 0 2006.231.07:34:41.26#ibcon#end of sib2, iclass 39, count 0 2006.231.07:34:41.26#ibcon#*after write, iclass 39, count 0 2006.231.07:34:41.26#ibcon#*before return 0, iclass 39, count 0 2006.231.07:34:41.26#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:34:41.26#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:34:41.26#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:34:41.26#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:34:41.26$vc4f8/vb=3,4 2006.231.07:34:41.26#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.231.07:34:41.26#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.231.07:34:41.26#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:41.26#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:34:41.32#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:34:41.32#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:34:41.32#ibcon#enter wrdev, iclass 3, count 2 2006.231.07:34:41.32#ibcon#first serial, iclass 3, count 2 2006.231.07:34:41.32#ibcon#enter sib2, iclass 3, count 2 2006.231.07:34:41.32#ibcon#flushed, iclass 3, count 2 2006.231.07:34:41.32#ibcon#about to write, iclass 3, count 2 2006.231.07:34:41.32#ibcon#wrote, iclass 3, count 2 2006.231.07:34:41.32#ibcon#about to read 3, iclass 3, count 2 2006.231.07:34:41.34#ibcon#read 3, iclass 3, count 2 2006.231.07:34:41.34#ibcon#about to read 4, iclass 3, count 2 2006.231.07:34:41.34#ibcon#read 4, iclass 3, count 2 2006.231.07:34:41.34#ibcon#about to read 5, iclass 3, count 2 2006.231.07:34:41.34#ibcon#read 5, iclass 3, count 2 2006.231.07:34:41.34#ibcon#about to read 6, iclass 3, count 2 2006.231.07:34:41.34#ibcon#read 6, iclass 3, count 2 2006.231.07:34:41.34#ibcon#end of sib2, iclass 3, count 2 2006.231.07:34:41.34#ibcon#*mode == 0, iclass 3, count 2 2006.231.07:34:41.34#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.231.07:34:41.34#ibcon#[27=AT03-04\r\n] 2006.231.07:34:41.34#ibcon#*before write, iclass 3, count 2 2006.231.07:34:41.34#ibcon#enter sib2, iclass 3, count 2 2006.231.07:34:41.34#ibcon#flushed, iclass 3, count 2 2006.231.07:34:41.34#ibcon#about to write, iclass 3, count 2 2006.231.07:34:41.34#ibcon#wrote, iclass 3, count 2 2006.231.07:34:41.34#ibcon#about to read 3, iclass 3, count 2 2006.231.07:34:41.37#ibcon#read 3, iclass 3, count 2 2006.231.07:34:41.37#ibcon#about to read 4, iclass 3, count 2 2006.231.07:34:41.37#ibcon#read 4, iclass 3, count 2 2006.231.07:34:41.37#ibcon#about to read 5, iclass 3, count 2 2006.231.07:34:41.37#ibcon#read 5, iclass 3, count 2 2006.231.07:34:41.37#ibcon#about to read 6, iclass 3, count 2 2006.231.07:34:41.37#ibcon#read 6, iclass 3, count 2 2006.231.07:34:41.37#ibcon#end of sib2, iclass 3, count 2 2006.231.07:34:41.37#ibcon#*after write, iclass 3, count 2 2006.231.07:34:41.37#ibcon#*before return 0, iclass 3, count 2 2006.231.07:34:41.37#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:34:41.37#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:34:41.37#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.231.07:34:41.37#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:41.37#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:34:41.49#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:34:41.49#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:34:41.49#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:34:41.49#ibcon#first serial, iclass 3, count 0 2006.231.07:34:41.49#ibcon#enter sib2, iclass 3, count 0 2006.231.07:34:41.49#ibcon#flushed, iclass 3, count 0 2006.231.07:34:41.49#ibcon#about to write, iclass 3, count 0 2006.231.07:34:41.49#ibcon#wrote, iclass 3, count 0 2006.231.07:34:41.49#ibcon#about to read 3, iclass 3, count 0 2006.231.07:34:41.51#ibcon#read 3, iclass 3, count 0 2006.231.07:34:41.51#ibcon#about to read 4, iclass 3, count 0 2006.231.07:34:41.51#ibcon#read 4, iclass 3, count 0 2006.231.07:34:41.51#ibcon#about to read 5, iclass 3, count 0 2006.231.07:34:41.51#ibcon#read 5, iclass 3, count 0 2006.231.07:34:41.51#ibcon#about to read 6, iclass 3, count 0 2006.231.07:34:41.51#ibcon#read 6, iclass 3, count 0 2006.231.07:34:41.51#ibcon#end of sib2, iclass 3, count 0 2006.231.07:34:41.51#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:34:41.51#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:34:41.51#ibcon#[27=USB\r\n] 2006.231.07:34:41.51#ibcon#*before write, iclass 3, count 0 2006.231.07:34:41.51#ibcon#enter sib2, iclass 3, count 0 2006.231.07:34:41.51#ibcon#flushed, iclass 3, count 0 2006.231.07:34:41.51#ibcon#about to write, iclass 3, count 0 2006.231.07:34:41.51#ibcon#wrote, iclass 3, count 0 2006.231.07:34:41.51#ibcon#about to read 3, iclass 3, count 0 2006.231.07:34:41.54#ibcon#read 3, iclass 3, count 0 2006.231.07:34:41.54#ibcon#about to read 4, iclass 3, count 0 2006.231.07:34:41.54#ibcon#read 4, iclass 3, count 0 2006.231.07:34:41.54#ibcon#about to read 5, iclass 3, count 0 2006.231.07:34:41.54#ibcon#read 5, iclass 3, count 0 2006.231.07:34:41.54#ibcon#about to read 6, iclass 3, count 0 2006.231.07:34:41.54#ibcon#read 6, iclass 3, count 0 2006.231.07:34:41.54#ibcon#end of sib2, iclass 3, count 0 2006.231.07:34:41.54#ibcon#*after write, iclass 3, count 0 2006.231.07:34:41.54#ibcon#*before return 0, iclass 3, count 0 2006.231.07:34:41.54#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:34:41.54#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:34:41.54#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:34:41.54#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:34:41.54$vc4f8/vblo=4,712.99 2006.231.07:34:41.54#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.231.07:34:41.54#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.231.07:34:41.54#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:41.54#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:34:41.54#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:34:41.54#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:34:41.54#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:34:41.54#ibcon#first serial, iclass 5, count 0 2006.231.07:34:41.54#ibcon#enter sib2, iclass 5, count 0 2006.231.07:34:41.54#ibcon#flushed, iclass 5, count 0 2006.231.07:34:41.54#ibcon#about to write, iclass 5, count 0 2006.231.07:34:41.54#ibcon#wrote, iclass 5, count 0 2006.231.07:34:41.54#ibcon#about to read 3, iclass 5, count 0 2006.231.07:34:41.56#ibcon#read 3, iclass 5, count 0 2006.231.07:34:41.56#ibcon#about to read 4, iclass 5, count 0 2006.231.07:34:41.56#ibcon#read 4, iclass 5, count 0 2006.231.07:34:41.56#ibcon#about to read 5, iclass 5, count 0 2006.231.07:34:41.56#ibcon#read 5, iclass 5, count 0 2006.231.07:34:41.56#ibcon#about to read 6, iclass 5, count 0 2006.231.07:34:41.56#ibcon#read 6, iclass 5, count 0 2006.231.07:34:41.56#ibcon#end of sib2, iclass 5, count 0 2006.231.07:34:41.56#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:34:41.56#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:34:41.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:34:41.56#ibcon#*before write, iclass 5, count 0 2006.231.07:34:41.56#ibcon#enter sib2, iclass 5, count 0 2006.231.07:34:41.56#ibcon#flushed, iclass 5, count 0 2006.231.07:34:41.56#ibcon#about to write, iclass 5, count 0 2006.231.07:34:41.56#ibcon#wrote, iclass 5, count 0 2006.231.07:34:41.56#ibcon#about to read 3, iclass 5, count 0 2006.231.07:34:41.60#ibcon#read 3, iclass 5, count 0 2006.231.07:34:41.60#ibcon#about to read 4, iclass 5, count 0 2006.231.07:34:41.60#ibcon#read 4, iclass 5, count 0 2006.231.07:34:41.60#ibcon#about to read 5, iclass 5, count 0 2006.231.07:34:41.60#ibcon#read 5, iclass 5, count 0 2006.231.07:34:41.60#ibcon#about to read 6, iclass 5, count 0 2006.231.07:34:41.60#ibcon#read 6, iclass 5, count 0 2006.231.07:34:41.60#ibcon#end of sib2, iclass 5, count 0 2006.231.07:34:41.60#ibcon#*after write, iclass 5, count 0 2006.231.07:34:41.60#ibcon#*before return 0, iclass 5, count 0 2006.231.07:34:41.60#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:34:41.60#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:34:41.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:34:41.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:34:41.60$vc4f8/vb=4,4 2006.231.07:34:41.60#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.231.07:34:41.60#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.231.07:34:41.60#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:41.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:34:41.66#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:34:41.66#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:34:41.66#ibcon#enter wrdev, iclass 7, count 2 2006.231.07:34:41.66#ibcon#first serial, iclass 7, count 2 2006.231.07:34:41.66#ibcon#enter sib2, iclass 7, count 2 2006.231.07:34:41.66#ibcon#flushed, iclass 7, count 2 2006.231.07:34:41.66#ibcon#about to write, iclass 7, count 2 2006.231.07:34:41.66#ibcon#wrote, iclass 7, count 2 2006.231.07:34:41.66#ibcon#about to read 3, iclass 7, count 2 2006.231.07:34:41.68#ibcon#read 3, iclass 7, count 2 2006.231.07:34:41.68#ibcon#about to read 4, iclass 7, count 2 2006.231.07:34:41.68#ibcon#read 4, iclass 7, count 2 2006.231.07:34:41.68#ibcon#about to read 5, iclass 7, count 2 2006.231.07:34:41.68#ibcon#read 5, iclass 7, count 2 2006.231.07:34:41.68#ibcon#about to read 6, iclass 7, count 2 2006.231.07:34:41.68#ibcon#read 6, iclass 7, count 2 2006.231.07:34:41.68#ibcon#end of sib2, iclass 7, count 2 2006.231.07:34:41.68#ibcon#*mode == 0, iclass 7, count 2 2006.231.07:34:41.68#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.231.07:34:41.68#ibcon#[27=AT04-04\r\n] 2006.231.07:34:41.68#ibcon#*before write, iclass 7, count 2 2006.231.07:34:41.68#ibcon#enter sib2, iclass 7, count 2 2006.231.07:34:41.68#ibcon#flushed, iclass 7, count 2 2006.231.07:34:41.68#ibcon#about to write, iclass 7, count 2 2006.231.07:34:41.68#ibcon#wrote, iclass 7, count 2 2006.231.07:34:41.68#ibcon#about to read 3, iclass 7, count 2 2006.231.07:34:41.71#ibcon#read 3, iclass 7, count 2 2006.231.07:34:41.71#ibcon#about to read 4, iclass 7, count 2 2006.231.07:34:41.71#ibcon#read 4, iclass 7, count 2 2006.231.07:34:41.71#ibcon#about to read 5, iclass 7, count 2 2006.231.07:34:41.71#ibcon#read 5, iclass 7, count 2 2006.231.07:34:41.71#ibcon#about to read 6, iclass 7, count 2 2006.231.07:34:41.71#ibcon#read 6, iclass 7, count 2 2006.231.07:34:41.71#ibcon#end of sib2, iclass 7, count 2 2006.231.07:34:41.71#ibcon#*after write, iclass 7, count 2 2006.231.07:34:41.71#ibcon#*before return 0, iclass 7, count 2 2006.231.07:34:41.71#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:34:41.71#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:34:41.71#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.231.07:34:41.71#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:41.71#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:34:41.83#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:34:41.83#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:34:41.83#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:34:41.83#ibcon#first serial, iclass 7, count 0 2006.231.07:34:41.83#ibcon#enter sib2, iclass 7, count 0 2006.231.07:34:41.83#ibcon#flushed, iclass 7, count 0 2006.231.07:34:41.83#ibcon#about to write, iclass 7, count 0 2006.231.07:34:41.83#ibcon#wrote, iclass 7, count 0 2006.231.07:34:41.83#ibcon#about to read 3, iclass 7, count 0 2006.231.07:34:41.85#ibcon#read 3, iclass 7, count 0 2006.231.07:34:41.85#ibcon#about to read 4, iclass 7, count 0 2006.231.07:34:41.85#ibcon#read 4, iclass 7, count 0 2006.231.07:34:41.85#ibcon#about to read 5, iclass 7, count 0 2006.231.07:34:41.85#ibcon#read 5, iclass 7, count 0 2006.231.07:34:41.85#ibcon#about to read 6, iclass 7, count 0 2006.231.07:34:41.85#ibcon#read 6, iclass 7, count 0 2006.231.07:34:41.85#ibcon#end of sib2, iclass 7, count 0 2006.231.07:34:41.85#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:34:41.85#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:34:41.85#ibcon#[27=USB\r\n] 2006.231.07:34:41.85#ibcon#*before write, iclass 7, count 0 2006.231.07:34:41.85#ibcon#enter sib2, iclass 7, count 0 2006.231.07:34:41.85#ibcon#flushed, iclass 7, count 0 2006.231.07:34:41.85#ibcon#about to write, iclass 7, count 0 2006.231.07:34:41.85#ibcon#wrote, iclass 7, count 0 2006.231.07:34:41.85#ibcon#about to read 3, iclass 7, count 0 2006.231.07:34:41.88#ibcon#read 3, iclass 7, count 0 2006.231.07:34:41.88#ibcon#about to read 4, iclass 7, count 0 2006.231.07:34:41.88#ibcon#read 4, iclass 7, count 0 2006.231.07:34:41.88#ibcon#about to read 5, iclass 7, count 0 2006.231.07:34:41.88#ibcon#read 5, iclass 7, count 0 2006.231.07:34:41.88#ibcon#about to read 6, iclass 7, count 0 2006.231.07:34:41.88#ibcon#read 6, iclass 7, count 0 2006.231.07:34:41.88#ibcon#end of sib2, iclass 7, count 0 2006.231.07:34:41.88#ibcon#*after write, iclass 7, count 0 2006.231.07:34:41.88#ibcon#*before return 0, iclass 7, count 0 2006.231.07:34:41.88#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:34:41.88#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:34:41.88#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:34:41.88#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:34:41.88$vc4f8/vblo=5,744.99 2006.231.07:34:41.88#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.231.07:34:41.88#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.231.07:34:41.88#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:41.88#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:34:41.88#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:34:41.88#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:34:41.88#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:34:41.88#ibcon#first serial, iclass 11, count 0 2006.231.07:34:41.88#ibcon#enter sib2, iclass 11, count 0 2006.231.07:34:41.88#ibcon#flushed, iclass 11, count 0 2006.231.07:34:41.88#ibcon#about to write, iclass 11, count 0 2006.231.07:34:41.88#ibcon#wrote, iclass 11, count 0 2006.231.07:34:41.88#ibcon#about to read 3, iclass 11, count 0 2006.231.07:34:41.90#ibcon#read 3, iclass 11, count 0 2006.231.07:34:41.90#ibcon#about to read 4, iclass 11, count 0 2006.231.07:34:41.90#ibcon#read 4, iclass 11, count 0 2006.231.07:34:41.90#ibcon#about to read 5, iclass 11, count 0 2006.231.07:34:41.90#ibcon#read 5, iclass 11, count 0 2006.231.07:34:41.90#ibcon#about to read 6, iclass 11, count 0 2006.231.07:34:41.90#ibcon#read 6, iclass 11, count 0 2006.231.07:34:41.90#ibcon#end of sib2, iclass 11, count 0 2006.231.07:34:41.90#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:34:41.90#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:34:41.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:34:41.90#ibcon#*before write, iclass 11, count 0 2006.231.07:34:41.90#ibcon#enter sib2, iclass 11, count 0 2006.231.07:34:41.90#ibcon#flushed, iclass 11, count 0 2006.231.07:34:41.90#ibcon#about to write, iclass 11, count 0 2006.231.07:34:41.90#ibcon#wrote, iclass 11, count 0 2006.231.07:34:41.90#ibcon#about to read 3, iclass 11, count 0 2006.231.07:34:41.94#ibcon#read 3, iclass 11, count 0 2006.231.07:34:41.94#ibcon#about to read 4, iclass 11, count 0 2006.231.07:34:41.94#ibcon#read 4, iclass 11, count 0 2006.231.07:34:41.94#ibcon#about to read 5, iclass 11, count 0 2006.231.07:34:41.94#ibcon#read 5, iclass 11, count 0 2006.231.07:34:41.94#ibcon#about to read 6, iclass 11, count 0 2006.231.07:34:41.94#ibcon#read 6, iclass 11, count 0 2006.231.07:34:41.94#ibcon#end of sib2, iclass 11, count 0 2006.231.07:34:41.94#ibcon#*after write, iclass 11, count 0 2006.231.07:34:41.94#ibcon#*before return 0, iclass 11, count 0 2006.231.07:34:41.94#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:34:41.94#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:34:41.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:34:41.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:34:41.95$vc4f8/vb=5,3 2006.231.07:34:41.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.231.07:34:41.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.231.07:34:41.95#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:41.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:34:41.99#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:34:41.99#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:34:41.99#ibcon#enter wrdev, iclass 13, count 2 2006.231.07:34:41.99#ibcon#first serial, iclass 13, count 2 2006.231.07:34:41.99#ibcon#enter sib2, iclass 13, count 2 2006.231.07:34:41.99#ibcon#flushed, iclass 13, count 2 2006.231.07:34:41.99#ibcon#about to write, iclass 13, count 2 2006.231.07:34:41.99#ibcon#wrote, iclass 13, count 2 2006.231.07:34:41.99#ibcon#about to read 3, iclass 13, count 2 2006.231.07:34:42.01#ibcon#read 3, iclass 13, count 2 2006.231.07:34:42.01#ibcon#about to read 4, iclass 13, count 2 2006.231.07:34:42.01#ibcon#read 4, iclass 13, count 2 2006.231.07:34:42.01#ibcon#about to read 5, iclass 13, count 2 2006.231.07:34:42.01#ibcon#read 5, iclass 13, count 2 2006.231.07:34:42.01#ibcon#about to read 6, iclass 13, count 2 2006.231.07:34:42.01#ibcon#read 6, iclass 13, count 2 2006.231.07:34:42.01#ibcon#end of sib2, iclass 13, count 2 2006.231.07:34:42.01#ibcon#*mode == 0, iclass 13, count 2 2006.231.07:34:42.01#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.231.07:34:42.01#ibcon#[27=AT05-03\r\n] 2006.231.07:34:42.01#ibcon#*before write, iclass 13, count 2 2006.231.07:34:42.01#ibcon#enter sib2, iclass 13, count 2 2006.231.07:34:42.01#ibcon#flushed, iclass 13, count 2 2006.231.07:34:42.01#ibcon#about to write, iclass 13, count 2 2006.231.07:34:42.01#ibcon#wrote, iclass 13, count 2 2006.231.07:34:42.01#ibcon#about to read 3, iclass 13, count 2 2006.231.07:34:42.04#ibcon#read 3, iclass 13, count 2 2006.231.07:34:42.04#ibcon#about to read 4, iclass 13, count 2 2006.231.07:34:42.04#ibcon#read 4, iclass 13, count 2 2006.231.07:34:42.04#ibcon#about to read 5, iclass 13, count 2 2006.231.07:34:42.04#ibcon#read 5, iclass 13, count 2 2006.231.07:34:42.04#ibcon#about to read 6, iclass 13, count 2 2006.231.07:34:42.04#ibcon#read 6, iclass 13, count 2 2006.231.07:34:42.04#ibcon#end of sib2, iclass 13, count 2 2006.231.07:34:42.04#ibcon#*after write, iclass 13, count 2 2006.231.07:34:42.04#ibcon#*before return 0, iclass 13, count 2 2006.231.07:34:42.04#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:34:42.04#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:34:42.04#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.231.07:34:42.04#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:42.04#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:34:42.16#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:34:42.16#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:34:42.16#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:34:42.16#ibcon#first serial, iclass 13, count 0 2006.231.07:34:42.16#ibcon#enter sib2, iclass 13, count 0 2006.231.07:34:42.16#ibcon#flushed, iclass 13, count 0 2006.231.07:34:42.16#ibcon#about to write, iclass 13, count 0 2006.231.07:34:42.16#ibcon#wrote, iclass 13, count 0 2006.231.07:34:42.16#ibcon#about to read 3, iclass 13, count 0 2006.231.07:34:42.18#ibcon#read 3, iclass 13, count 0 2006.231.07:34:42.18#ibcon#about to read 4, iclass 13, count 0 2006.231.07:34:42.18#ibcon#read 4, iclass 13, count 0 2006.231.07:34:42.18#ibcon#about to read 5, iclass 13, count 0 2006.231.07:34:42.18#ibcon#read 5, iclass 13, count 0 2006.231.07:34:42.18#ibcon#about to read 6, iclass 13, count 0 2006.231.07:34:42.18#ibcon#read 6, iclass 13, count 0 2006.231.07:34:42.18#ibcon#end of sib2, iclass 13, count 0 2006.231.07:34:42.18#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:34:42.18#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:34:42.18#ibcon#[27=USB\r\n] 2006.231.07:34:42.18#ibcon#*before write, iclass 13, count 0 2006.231.07:34:42.18#ibcon#enter sib2, iclass 13, count 0 2006.231.07:34:42.18#ibcon#flushed, iclass 13, count 0 2006.231.07:34:42.18#ibcon#about to write, iclass 13, count 0 2006.231.07:34:42.18#ibcon#wrote, iclass 13, count 0 2006.231.07:34:42.18#ibcon#about to read 3, iclass 13, count 0 2006.231.07:34:42.21#ibcon#read 3, iclass 13, count 0 2006.231.07:34:42.21#ibcon#about to read 4, iclass 13, count 0 2006.231.07:34:42.21#ibcon#read 4, iclass 13, count 0 2006.231.07:34:42.21#ibcon#about to read 5, iclass 13, count 0 2006.231.07:34:42.21#ibcon#read 5, iclass 13, count 0 2006.231.07:34:42.21#ibcon#about to read 6, iclass 13, count 0 2006.231.07:34:42.21#ibcon#read 6, iclass 13, count 0 2006.231.07:34:42.21#ibcon#end of sib2, iclass 13, count 0 2006.231.07:34:42.21#ibcon#*after write, iclass 13, count 0 2006.231.07:34:42.21#ibcon#*before return 0, iclass 13, count 0 2006.231.07:34:42.21#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:34:42.21#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:34:42.21#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:34:42.21#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:34:42.21$vc4f8/vblo=6,752.99 2006.231.07:34:42.21#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.07:34:42.21#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.07:34:42.21#ibcon#ireg 17 cls_cnt 0 2006.231.07:34:42.21#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:34:42.21#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:34:42.21#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:34:42.21#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:34:42.21#ibcon#first serial, iclass 15, count 0 2006.231.07:34:42.21#ibcon#enter sib2, iclass 15, count 0 2006.231.07:34:42.21#ibcon#flushed, iclass 15, count 0 2006.231.07:34:42.21#ibcon#about to write, iclass 15, count 0 2006.231.07:34:42.21#ibcon#wrote, iclass 15, count 0 2006.231.07:34:42.21#ibcon#about to read 3, iclass 15, count 0 2006.231.07:34:42.23#ibcon#read 3, iclass 15, count 0 2006.231.07:34:42.23#ibcon#about to read 4, iclass 15, count 0 2006.231.07:34:42.23#ibcon#read 4, iclass 15, count 0 2006.231.07:34:42.23#ibcon#about to read 5, iclass 15, count 0 2006.231.07:34:42.23#ibcon#read 5, iclass 15, count 0 2006.231.07:34:42.23#ibcon#about to read 6, iclass 15, count 0 2006.231.07:34:42.23#ibcon#read 6, iclass 15, count 0 2006.231.07:34:42.23#ibcon#end of sib2, iclass 15, count 0 2006.231.07:34:42.23#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:34:42.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:34:42.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:34:42.23#ibcon#*before write, iclass 15, count 0 2006.231.07:34:42.23#ibcon#enter sib2, iclass 15, count 0 2006.231.07:34:42.23#ibcon#flushed, iclass 15, count 0 2006.231.07:34:42.23#ibcon#about to write, iclass 15, count 0 2006.231.07:34:42.23#ibcon#wrote, iclass 15, count 0 2006.231.07:34:42.23#ibcon#about to read 3, iclass 15, count 0 2006.231.07:34:42.27#ibcon#read 3, iclass 15, count 0 2006.231.07:34:42.27#ibcon#about to read 4, iclass 15, count 0 2006.231.07:34:42.27#ibcon#read 4, iclass 15, count 0 2006.231.07:34:42.27#ibcon#about to read 5, iclass 15, count 0 2006.231.07:34:42.27#ibcon#read 5, iclass 15, count 0 2006.231.07:34:42.27#ibcon#about to read 6, iclass 15, count 0 2006.231.07:34:42.27#ibcon#read 6, iclass 15, count 0 2006.231.07:34:42.27#ibcon#end of sib2, iclass 15, count 0 2006.231.07:34:42.27#ibcon#*after write, iclass 15, count 0 2006.231.07:34:42.27#ibcon#*before return 0, iclass 15, count 0 2006.231.07:34:42.27#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:34:42.27#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:34:42.27#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:34:42.27#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:34:42.27$vc4f8/vb=6,4 2006.231.07:34:42.27#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.07:34:42.27#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.07:34:42.27#ibcon#ireg 11 cls_cnt 2 2006.231.07:34:42.27#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:34:42.33#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:34:42.33#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:34:42.33#ibcon#enter wrdev, iclass 17, count 2 2006.231.07:34:42.33#ibcon#first serial, iclass 17, count 2 2006.231.07:34:42.33#ibcon#enter sib2, iclass 17, count 2 2006.231.07:34:42.33#ibcon#flushed, iclass 17, count 2 2006.231.07:34:42.33#ibcon#about to write, iclass 17, count 2 2006.231.07:34:42.33#ibcon#wrote, iclass 17, count 2 2006.231.07:34:42.33#ibcon#about to read 3, iclass 17, count 2 2006.231.07:34:42.35#ibcon#read 3, iclass 17, count 2 2006.231.07:34:42.35#ibcon#about to read 4, iclass 17, count 2 2006.231.07:34:42.35#ibcon#read 4, iclass 17, count 2 2006.231.07:34:42.35#ibcon#about to read 5, iclass 17, count 2 2006.231.07:34:42.35#ibcon#read 5, iclass 17, count 2 2006.231.07:34:42.35#ibcon#about to read 6, iclass 17, count 2 2006.231.07:34:42.35#ibcon#read 6, iclass 17, count 2 2006.231.07:34:42.35#ibcon#end of sib2, iclass 17, count 2 2006.231.07:34:42.35#ibcon#*mode == 0, iclass 17, count 2 2006.231.07:34:42.35#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.07:34:42.35#ibcon#[27=AT06-04\r\n] 2006.231.07:34:42.35#ibcon#*before write, iclass 17, count 2 2006.231.07:34:42.35#ibcon#enter sib2, iclass 17, count 2 2006.231.07:34:42.35#ibcon#flushed, iclass 17, count 2 2006.231.07:34:42.35#ibcon#about to write, iclass 17, count 2 2006.231.07:34:42.35#ibcon#wrote, iclass 17, count 2 2006.231.07:34:42.35#ibcon#about to read 3, iclass 17, count 2 2006.231.07:34:42.38#ibcon#read 3, iclass 17, count 2 2006.231.07:34:42.38#ibcon#about to read 4, iclass 17, count 2 2006.231.07:34:42.38#ibcon#read 4, iclass 17, count 2 2006.231.07:34:42.38#ibcon#about to read 5, iclass 17, count 2 2006.231.07:34:42.38#ibcon#read 5, iclass 17, count 2 2006.231.07:34:42.38#ibcon#about to read 6, iclass 17, count 2 2006.231.07:34:42.38#ibcon#read 6, iclass 17, count 2 2006.231.07:34:42.38#ibcon#end of sib2, iclass 17, count 2 2006.231.07:34:42.38#ibcon#*after write, iclass 17, count 2 2006.231.07:34:42.38#ibcon#*before return 0, iclass 17, count 2 2006.231.07:34:42.38#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:34:42.38#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:34:42.38#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.07:34:42.38#ibcon#ireg 7 cls_cnt 0 2006.231.07:34:42.38#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:34:42.50#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:34:42.50#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:34:42.50#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:34:42.50#ibcon#first serial, iclass 17, count 0 2006.231.07:34:42.50#ibcon#enter sib2, iclass 17, count 0 2006.231.07:34:42.50#ibcon#flushed, iclass 17, count 0 2006.231.07:34:42.50#ibcon#about to write, iclass 17, count 0 2006.231.07:34:42.50#ibcon#wrote, iclass 17, count 0 2006.231.07:34:42.50#ibcon#about to read 3, iclass 17, count 0 2006.231.07:34:42.52#ibcon#read 3, iclass 17, count 0 2006.231.07:34:42.52#ibcon#about to read 4, iclass 17, count 0 2006.231.07:34:42.52#ibcon#read 4, iclass 17, count 0 2006.231.07:34:42.52#ibcon#about to read 5, iclass 17, count 0 2006.231.07:34:42.52#ibcon#read 5, iclass 17, count 0 2006.231.07:34:42.52#ibcon#about to read 6, iclass 17, count 0 2006.231.07:34:42.52#ibcon#read 6, iclass 17, count 0 2006.231.07:34:42.52#ibcon#end of sib2, iclass 17, count 0 2006.231.07:34:42.52#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:34:42.52#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:34:42.52#ibcon#[27=USB\r\n] 2006.231.07:34:42.52#ibcon#*before write, iclass 17, count 0 2006.231.07:34:42.52#ibcon#enter sib2, iclass 17, count 0 2006.231.07:34:42.52#ibcon#flushed, iclass 17, count 0 2006.231.07:34:42.52#ibcon#about to write, iclass 17, count 0 2006.231.07:34:42.52#ibcon#wrote, iclass 17, count 0 2006.231.07:34:42.52#ibcon#about to read 3, iclass 17, count 0 2006.231.07:34:42.55#ibcon#read 3, iclass 17, count 0 2006.231.07:34:42.55#ibcon#about to read 4, iclass 17, count 0 2006.231.07:34:42.55#ibcon#read 4, iclass 17, count 0 2006.231.07:34:42.55#ibcon#about to read 5, iclass 17, count 0 2006.231.07:34:42.55#ibcon#read 5, iclass 17, count 0 2006.231.07:34:42.55#ibcon#about to read 6, iclass 17, count 0 2006.231.07:34:42.55#ibcon#read 6, iclass 17, count 0 2006.231.07:34:42.55#ibcon#end of sib2, iclass 17, count 0 2006.231.07:34:42.55#ibcon#*after write, iclass 17, count 0 2006.231.07:34:42.55#ibcon#*before return 0, iclass 17, count 0 2006.231.07:34:42.55#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:34:42.55#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:34:42.55#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:34:42.55#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:34:42.55$vc4f8/vabw=wide 2006.231.07:34:42.55#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.07:34:42.55#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.07:34:42.55#ibcon#ireg 8 cls_cnt 0 2006.231.07:34:42.55#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:34:42.55#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:34:42.55#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:34:42.55#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:34:42.55#ibcon#first serial, iclass 19, count 0 2006.231.07:34:42.55#ibcon#enter sib2, iclass 19, count 0 2006.231.07:34:42.55#ibcon#flushed, iclass 19, count 0 2006.231.07:34:42.55#ibcon#about to write, iclass 19, count 0 2006.231.07:34:42.55#ibcon#wrote, iclass 19, count 0 2006.231.07:34:42.55#ibcon#about to read 3, iclass 19, count 0 2006.231.07:34:42.57#ibcon#read 3, iclass 19, count 0 2006.231.07:34:42.57#ibcon#about to read 4, iclass 19, count 0 2006.231.07:34:42.57#ibcon#read 4, iclass 19, count 0 2006.231.07:34:42.57#ibcon#about to read 5, iclass 19, count 0 2006.231.07:34:42.57#ibcon#read 5, iclass 19, count 0 2006.231.07:34:42.57#ibcon#about to read 6, iclass 19, count 0 2006.231.07:34:42.57#ibcon#read 6, iclass 19, count 0 2006.231.07:34:42.57#ibcon#end of sib2, iclass 19, count 0 2006.231.07:34:42.57#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:34:42.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:34:42.57#ibcon#[25=BW32\r\n] 2006.231.07:34:42.57#ibcon#*before write, iclass 19, count 0 2006.231.07:34:42.57#ibcon#enter sib2, iclass 19, count 0 2006.231.07:34:42.57#ibcon#flushed, iclass 19, count 0 2006.231.07:34:42.57#ibcon#about to write, iclass 19, count 0 2006.231.07:34:42.57#ibcon#wrote, iclass 19, count 0 2006.231.07:34:42.57#ibcon#about to read 3, iclass 19, count 0 2006.231.07:34:42.60#ibcon#read 3, iclass 19, count 0 2006.231.07:34:42.60#ibcon#about to read 4, iclass 19, count 0 2006.231.07:34:42.60#ibcon#read 4, iclass 19, count 0 2006.231.07:34:42.60#ibcon#about to read 5, iclass 19, count 0 2006.231.07:34:42.60#ibcon#read 5, iclass 19, count 0 2006.231.07:34:42.60#ibcon#about to read 6, iclass 19, count 0 2006.231.07:34:42.60#ibcon#read 6, iclass 19, count 0 2006.231.07:34:42.60#ibcon#end of sib2, iclass 19, count 0 2006.231.07:34:42.60#ibcon#*after write, iclass 19, count 0 2006.231.07:34:42.60#ibcon#*before return 0, iclass 19, count 0 2006.231.07:34:42.60#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:34:42.60#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:34:42.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:34:42.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:34:42.60$vc4f8/vbbw=wide 2006.231.07:34:42.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.07:34:42.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.07:34:42.60#ibcon#ireg 8 cls_cnt 0 2006.231.07:34:42.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:34:42.67#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:34:42.67#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:34:42.67#ibcon#enter wrdev, iclass 21, count 0 2006.231.07:34:42.67#ibcon#first serial, iclass 21, count 0 2006.231.07:34:42.67#ibcon#enter sib2, iclass 21, count 0 2006.231.07:34:42.67#ibcon#flushed, iclass 21, count 0 2006.231.07:34:42.67#ibcon#about to write, iclass 21, count 0 2006.231.07:34:42.67#ibcon#wrote, iclass 21, count 0 2006.231.07:34:42.67#ibcon#about to read 3, iclass 21, count 0 2006.231.07:34:42.70#ibcon#read 3, iclass 21, count 0 2006.231.07:34:42.70#ibcon#about to read 4, iclass 21, count 0 2006.231.07:34:42.70#ibcon#read 4, iclass 21, count 0 2006.231.07:34:42.70#ibcon#about to read 5, iclass 21, count 0 2006.231.07:34:42.70#ibcon#read 5, iclass 21, count 0 2006.231.07:34:42.70#ibcon#about to read 6, iclass 21, count 0 2006.231.07:34:42.70#ibcon#read 6, iclass 21, count 0 2006.231.07:34:42.70#ibcon#end of sib2, iclass 21, count 0 2006.231.07:34:42.70#ibcon#*mode == 0, iclass 21, count 0 2006.231.07:34:42.70#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.07:34:42.70#ibcon#[27=BW32\r\n] 2006.231.07:34:42.70#ibcon#*before write, iclass 21, count 0 2006.231.07:34:42.70#ibcon#enter sib2, iclass 21, count 0 2006.231.07:34:42.70#ibcon#flushed, iclass 21, count 0 2006.231.07:34:42.70#ibcon#about to write, iclass 21, count 0 2006.231.07:34:42.70#ibcon#wrote, iclass 21, count 0 2006.231.07:34:42.70#ibcon#about to read 3, iclass 21, count 0 2006.231.07:34:42.73#ibcon#read 3, iclass 21, count 0 2006.231.07:34:42.73#ibcon#about to read 4, iclass 21, count 0 2006.231.07:34:42.73#ibcon#read 4, iclass 21, count 0 2006.231.07:34:42.73#ibcon#about to read 5, iclass 21, count 0 2006.231.07:34:42.73#ibcon#read 5, iclass 21, count 0 2006.231.07:34:42.73#ibcon#about to read 6, iclass 21, count 0 2006.231.07:34:42.73#ibcon#read 6, iclass 21, count 0 2006.231.07:34:42.73#ibcon#end of sib2, iclass 21, count 0 2006.231.07:34:42.73#ibcon#*after write, iclass 21, count 0 2006.231.07:34:42.73#ibcon#*before return 0, iclass 21, count 0 2006.231.07:34:42.73#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:34:42.73#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:34:42.73#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.07:34:42.73#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.07:34:42.73$4f8m12a/ifd4f 2006.231.07:34:42.73$ifd4f/lo= 2006.231.07:34:42.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:34:42.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:34:42.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:34:42.73$ifd4f/patch= 2006.231.07:34:42.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:34:42.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:34:42.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:34:42.73$4f8m12a/"form=m,16.000,1:2 2006.231.07:34:42.73$4f8m12a/"tpicd 2006.231.07:34:42.73$4f8m12a/echo=off 2006.231.07:34:42.73$4f8m12a/xlog=off 2006.231.07:34:42.73:!2006.231.07:35:10 2006.231.07:34:55.13#trakl#Source acquired 2006.231.07:34:57.13#flagr#flagr/antenna,acquired 2006.231.07:35:10.01:preob 2006.231.07:35:11.13/onsource/TRACKING 2006.231.07:35:11.13:!2006.231.07:35:20 2006.231.07:35:20.00:data_valid=on 2006.231.07:35:20.00:midob 2006.231.07:35:20.13/onsource/TRACKING 2006.231.07:35:20.13/wx/30.75,1004.4,83 2006.231.07:35:20.26/cable/+6.3694E-03 2006.231.07:35:21.35/va/01,08,usb,yes,29,31 2006.231.07:35:21.35/va/02,07,usb,yes,29,31 2006.231.07:35:21.35/va/03,08,usb,yes,22,22 2006.231.07:35:21.35/va/04,07,usb,yes,31,33 2006.231.07:35:21.35/va/05,07,usb,yes,34,36 2006.231.07:35:21.35/va/06,06,usb,yes,33,33 2006.231.07:35:21.35/va/07,06,usb,yes,34,34 2006.231.07:35:21.35/va/08,06,usb,yes,36,36 2006.231.07:35:21.58/valo/01,532.99,yes,locked 2006.231.07:35:21.58/valo/02,572.99,yes,locked 2006.231.07:35:21.58/valo/03,672.99,yes,locked 2006.231.07:35:21.58/valo/04,832.99,yes,locked 2006.231.07:35:21.58/valo/05,652.99,yes,locked 2006.231.07:35:21.58/valo/06,772.99,yes,locked 2006.231.07:35:21.58/valo/07,832.99,yes,locked 2006.231.07:35:21.58/valo/08,852.99,yes,locked 2006.231.07:35:22.67/vb/01,04,usb,yes,30,29 2006.231.07:35:22.67/vb/02,04,usb,yes,32,34 2006.231.07:35:22.67/vb/03,04,usb,yes,29,32 2006.231.07:35:22.67/vb/04,04,usb,yes,29,30 2006.231.07:35:22.67/vb/05,03,usb,yes,35,39 2006.231.07:35:22.67/vb/06,04,usb,yes,29,32 2006.231.07:35:22.67/vb/07,04,usb,yes,31,31 2006.231.07:35:22.67/vb/08,04,usb,yes,28,32 2006.231.07:35:22.90/vblo/01,632.99,yes,locked 2006.231.07:35:22.90/vblo/02,640.99,yes,locked 2006.231.07:35:22.90/vblo/03,656.99,yes,locked 2006.231.07:35:22.90/vblo/04,712.99,yes,locked 2006.231.07:35:22.90/vblo/05,744.99,yes,locked 2006.231.07:35:22.90/vblo/06,752.99,yes,locked 2006.231.07:35:22.90/vblo/07,734.99,yes,locked 2006.231.07:35:22.90/vblo/08,744.99,yes,locked 2006.231.07:35:23.05/vabw/8 2006.231.07:35:23.20/vbbw/8 2006.231.07:35:23.29/xfe/off,on,12.5 2006.231.07:35:23.67/ifatt/23,28,28,28 2006.231.07:35:24.07/fmout-gps/S +4.38E-07 2006.231.07:35:24.11:!2006.231.07:36:20 2006.231.07:36:20.00:data_valid=off 2006.231.07:36:20.01:postob 2006.231.07:36:20.09/cable/+6.3728E-03 2006.231.07:36:20.09/wx/30.73,1004.4,83 2006.231.07:36:21.07/fmout-gps/S +4.37E-07 2006.231.07:36:21.08:scan_name=231-0737,k06231,60 2006.231.07:36:21.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.231.07:36:22.14#flagr#flagr/antenna,new-source 2006.231.07:36:22.15:checkk5 2006.231.07:36:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:36:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:36:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:36:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:36:24.01/chk_obsdata//k5ts1/T2310735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:36:24.38/chk_obsdata//k5ts2/T2310735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:36:24.75/chk_obsdata//k5ts3/T2310735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:36:25.11/chk_obsdata//k5ts4/T2310735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:36:25.80/k5log//k5ts1_log_newline 2006.231.07:36:26.49/k5log//k5ts2_log_newline 2006.231.07:36:27.18/k5log//k5ts3_log_newline 2006.231.07:36:27.86/k5log//k5ts4_log_newline 2006.231.07:36:27.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:36:27.89:4f8m12a=1 2006.231.07:36:27.89$4f8m12a/echo=on 2006.231.07:36:27.89$4f8m12a/pcalon 2006.231.07:36:27.89$pcalon/"no phase cal control is implemented here 2006.231.07:36:27.89$4f8m12a/"tpicd=stop 2006.231.07:36:27.89$4f8m12a/vc4f8 2006.231.07:36:27.89$vc4f8/valo=1,532.99 2006.231.07:36:27.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.07:36:27.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.07:36:27.89#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:27.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:36:27.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:36:27.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:36:27.89#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:36:27.89#ibcon#first serial, iclass 32, count 0 2006.231.07:36:27.89#ibcon#enter sib2, iclass 32, count 0 2006.231.07:36:27.89#ibcon#flushed, iclass 32, count 0 2006.231.07:36:27.89#ibcon#about to write, iclass 32, count 0 2006.231.07:36:27.89#ibcon#wrote, iclass 32, count 0 2006.231.07:36:27.89#ibcon#about to read 3, iclass 32, count 0 2006.231.07:36:27.93#ibcon#read 3, iclass 32, count 0 2006.231.07:36:27.93#ibcon#about to read 4, iclass 32, count 0 2006.231.07:36:27.93#ibcon#read 4, iclass 32, count 0 2006.231.07:36:27.93#ibcon#about to read 5, iclass 32, count 0 2006.231.07:36:27.93#ibcon#read 5, iclass 32, count 0 2006.231.07:36:27.93#ibcon#about to read 6, iclass 32, count 0 2006.231.07:36:27.93#ibcon#read 6, iclass 32, count 0 2006.231.07:36:27.93#ibcon#end of sib2, iclass 32, count 0 2006.231.07:36:27.93#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:36:27.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:36:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:36:27.93#ibcon#*before write, iclass 32, count 0 2006.231.07:36:27.93#ibcon#enter sib2, iclass 32, count 0 2006.231.07:36:27.93#ibcon#flushed, iclass 32, count 0 2006.231.07:36:27.93#ibcon#about to write, iclass 32, count 0 2006.231.07:36:27.93#ibcon#wrote, iclass 32, count 0 2006.231.07:36:27.93#ibcon#about to read 3, iclass 32, count 0 2006.231.07:36:27.98#ibcon#read 3, iclass 32, count 0 2006.231.07:36:27.98#ibcon#about to read 4, iclass 32, count 0 2006.231.07:36:27.98#ibcon#read 4, iclass 32, count 0 2006.231.07:36:27.98#ibcon#about to read 5, iclass 32, count 0 2006.231.07:36:27.98#ibcon#read 5, iclass 32, count 0 2006.231.07:36:27.98#ibcon#about to read 6, iclass 32, count 0 2006.231.07:36:27.98#ibcon#read 6, iclass 32, count 0 2006.231.07:36:27.98#ibcon#end of sib2, iclass 32, count 0 2006.231.07:36:27.98#ibcon#*after write, iclass 32, count 0 2006.231.07:36:27.98#ibcon#*before return 0, iclass 32, count 0 2006.231.07:36:27.98#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:36:27.98#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:36:27.98#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:36:27.98#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:36:27.98$vc4f8/va=1,8 2006.231.07:36:27.98#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.07:36:27.98#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.07:36:27.98#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:27.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:36:27.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:36:27.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:36:27.98#ibcon#enter wrdev, iclass 34, count 2 2006.231.07:36:27.98#ibcon#first serial, iclass 34, count 2 2006.231.07:36:27.98#ibcon#enter sib2, iclass 34, count 2 2006.231.07:36:27.98#ibcon#flushed, iclass 34, count 2 2006.231.07:36:27.98#ibcon#about to write, iclass 34, count 2 2006.231.07:36:27.98#ibcon#wrote, iclass 34, count 2 2006.231.07:36:27.98#ibcon#about to read 3, iclass 34, count 2 2006.231.07:36:28.00#ibcon#read 3, iclass 34, count 2 2006.231.07:36:28.00#ibcon#about to read 4, iclass 34, count 2 2006.231.07:36:28.00#ibcon#read 4, iclass 34, count 2 2006.231.07:36:28.00#ibcon#about to read 5, iclass 34, count 2 2006.231.07:36:28.00#ibcon#read 5, iclass 34, count 2 2006.231.07:36:28.00#ibcon#about to read 6, iclass 34, count 2 2006.231.07:36:28.00#ibcon#read 6, iclass 34, count 2 2006.231.07:36:28.00#ibcon#end of sib2, iclass 34, count 2 2006.231.07:36:28.00#ibcon#*mode == 0, iclass 34, count 2 2006.231.07:36:28.00#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.07:36:28.00#ibcon#[25=AT01-08\r\n] 2006.231.07:36:28.00#ibcon#*before write, iclass 34, count 2 2006.231.07:36:28.00#ibcon#enter sib2, iclass 34, count 2 2006.231.07:36:28.00#ibcon#flushed, iclass 34, count 2 2006.231.07:36:28.00#ibcon#about to write, iclass 34, count 2 2006.231.07:36:28.00#ibcon#wrote, iclass 34, count 2 2006.231.07:36:28.00#ibcon#about to read 3, iclass 34, count 2 2006.231.07:36:28.03#ibcon#read 3, iclass 34, count 2 2006.231.07:36:28.03#ibcon#about to read 4, iclass 34, count 2 2006.231.07:36:28.03#ibcon#read 4, iclass 34, count 2 2006.231.07:36:28.03#ibcon#about to read 5, iclass 34, count 2 2006.231.07:36:28.03#ibcon#read 5, iclass 34, count 2 2006.231.07:36:28.03#ibcon#about to read 6, iclass 34, count 2 2006.231.07:36:28.03#ibcon#read 6, iclass 34, count 2 2006.231.07:36:28.03#ibcon#end of sib2, iclass 34, count 2 2006.231.07:36:28.03#ibcon#*after write, iclass 34, count 2 2006.231.07:36:28.03#ibcon#*before return 0, iclass 34, count 2 2006.231.07:36:28.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:36:28.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:36:28.03#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.07:36:28.03#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:28.03#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:36:28.15#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:36:28.15#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:36:28.15#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:36:28.15#ibcon#first serial, iclass 34, count 0 2006.231.07:36:28.15#ibcon#enter sib2, iclass 34, count 0 2006.231.07:36:28.15#ibcon#flushed, iclass 34, count 0 2006.231.07:36:28.15#ibcon#about to write, iclass 34, count 0 2006.231.07:36:28.15#ibcon#wrote, iclass 34, count 0 2006.231.07:36:28.15#ibcon#about to read 3, iclass 34, count 0 2006.231.07:36:28.17#ibcon#read 3, iclass 34, count 0 2006.231.07:36:28.17#ibcon#about to read 4, iclass 34, count 0 2006.231.07:36:28.17#ibcon#read 4, iclass 34, count 0 2006.231.07:36:28.17#ibcon#about to read 5, iclass 34, count 0 2006.231.07:36:28.17#ibcon#read 5, iclass 34, count 0 2006.231.07:36:28.17#ibcon#about to read 6, iclass 34, count 0 2006.231.07:36:28.17#ibcon#read 6, iclass 34, count 0 2006.231.07:36:28.17#ibcon#end of sib2, iclass 34, count 0 2006.231.07:36:28.17#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:36:28.17#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:36:28.17#ibcon#[25=USB\r\n] 2006.231.07:36:28.17#ibcon#*before write, iclass 34, count 0 2006.231.07:36:28.17#ibcon#enter sib2, iclass 34, count 0 2006.231.07:36:28.17#ibcon#flushed, iclass 34, count 0 2006.231.07:36:28.17#ibcon#about to write, iclass 34, count 0 2006.231.07:36:28.17#ibcon#wrote, iclass 34, count 0 2006.231.07:36:28.17#ibcon#about to read 3, iclass 34, count 0 2006.231.07:36:28.20#ibcon#read 3, iclass 34, count 0 2006.231.07:36:28.20#ibcon#about to read 4, iclass 34, count 0 2006.231.07:36:28.20#ibcon#read 4, iclass 34, count 0 2006.231.07:36:28.20#ibcon#about to read 5, iclass 34, count 0 2006.231.07:36:28.20#ibcon#read 5, iclass 34, count 0 2006.231.07:36:28.20#ibcon#about to read 6, iclass 34, count 0 2006.231.07:36:28.20#ibcon#read 6, iclass 34, count 0 2006.231.07:36:28.20#ibcon#end of sib2, iclass 34, count 0 2006.231.07:36:28.20#ibcon#*after write, iclass 34, count 0 2006.231.07:36:28.20#ibcon#*before return 0, iclass 34, count 0 2006.231.07:36:28.20#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:36:28.20#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:36:28.20#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:36:28.20#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:36:28.20$vc4f8/valo=2,572.99 2006.231.07:36:28.20#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.07:36:28.20#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.07:36:28.20#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:28.20#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:36:28.20#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:36:28.20#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:36:28.20#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:36:28.20#ibcon#first serial, iclass 36, count 0 2006.231.07:36:28.20#ibcon#enter sib2, iclass 36, count 0 2006.231.07:36:28.20#ibcon#flushed, iclass 36, count 0 2006.231.07:36:28.20#ibcon#about to write, iclass 36, count 0 2006.231.07:36:28.20#ibcon#wrote, iclass 36, count 0 2006.231.07:36:28.20#ibcon#about to read 3, iclass 36, count 0 2006.231.07:36:28.22#ibcon#read 3, iclass 36, count 0 2006.231.07:36:28.22#ibcon#about to read 4, iclass 36, count 0 2006.231.07:36:28.22#ibcon#read 4, iclass 36, count 0 2006.231.07:36:28.22#ibcon#about to read 5, iclass 36, count 0 2006.231.07:36:28.22#ibcon#read 5, iclass 36, count 0 2006.231.07:36:28.22#ibcon#about to read 6, iclass 36, count 0 2006.231.07:36:28.22#ibcon#read 6, iclass 36, count 0 2006.231.07:36:28.22#ibcon#end of sib2, iclass 36, count 0 2006.231.07:36:28.22#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:36:28.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:36:28.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:36:28.22#ibcon#*before write, iclass 36, count 0 2006.231.07:36:28.22#ibcon#enter sib2, iclass 36, count 0 2006.231.07:36:28.22#ibcon#flushed, iclass 36, count 0 2006.231.07:36:28.22#ibcon#about to write, iclass 36, count 0 2006.231.07:36:28.22#ibcon#wrote, iclass 36, count 0 2006.231.07:36:28.22#ibcon#about to read 3, iclass 36, count 0 2006.231.07:36:28.26#ibcon#read 3, iclass 36, count 0 2006.231.07:36:28.26#ibcon#about to read 4, iclass 36, count 0 2006.231.07:36:28.26#ibcon#read 4, iclass 36, count 0 2006.231.07:36:28.26#ibcon#about to read 5, iclass 36, count 0 2006.231.07:36:28.26#ibcon#read 5, iclass 36, count 0 2006.231.07:36:28.26#ibcon#about to read 6, iclass 36, count 0 2006.231.07:36:28.26#ibcon#read 6, iclass 36, count 0 2006.231.07:36:28.26#ibcon#end of sib2, iclass 36, count 0 2006.231.07:36:28.26#ibcon#*after write, iclass 36, count 0 2006.231.07:36:28.26#ibcon#*before return 0, iclass 36, count 0 2006.231.07:36:28.26#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:36:28.26#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:36:28.26#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:36:28.26#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:36:28.26$vc4f8/va=2,7 2006.231.07:36:28.26#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.07:36:28.26#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.07:36:28.26#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:28.26#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:36:28.32#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:36:28.32#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:36:28.32#ibcon#enter wrdev, iclass 38, count 2 2006.231.07:36:28.32#ibcon#first serial, iclass 38, count 2 2006.231.07:36:28.32#ibcon#enter sib2, iclass 38, count 2 2006.231.07:36:28.32#ibcon#flushed, iclass 38, count 2 2006.231.07:36:28.32#ibcon#about to write, iclass 38, count 2 2006.231.07:36:28.32#ibcon#wrote, iclass 38, count 2 2006.231.07:36:28.32#ibcon#about to read 3, iclass 38, count 2 2006.231.07:36:28.34#ibcon#read 3, iclass 38, count 2 2006.231.07:36:28.34#ibcon#about to read 4, iclass 38, count 2 2006.231.07:36:28.34#ibcon#read 4, iclass 38, count 2 2006.231.07:36:28.34#ibcon#about to read 5, iclass 38, count 2 2006.231.07:36:28.34#ibcon#read 5, iclass 38, count 2 2006.231.07:36:28.34#ibcon#about to read 6, iclass 38, count 2 2006.231.07:36:28.34#ibcon#read 6, iclass 38, count 2 2006.231.07:36:28.34#ibcon#end of sib2, iclass 38, count 2 2006.231.07:36:28.34#ibcon#*mode == 0, iclass 38, count 2 2006.231.07:36:28.34#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.07:36:28.34#ibcon#[25=AT02-07\r\n] 2006.231.07:36:28.34#ibcon#*before write, iclass 38, count 2 2006.231.07:36:28.34#ibcon#enter sib2, iclass 38, count 2 2006.231.07:36:28.34#ibcon#flushed, iclass 38, count 2 2006.231.07:36:28.34#ibcon#about to write, iclass 38, count 2 2006.231.07:36:28.34#ibcon#wrote, iclass 38, count 2 2006.231.07:36:28.34#ibcon#about to read 3, iclass 38, count 2 2006.231.07:36:28.37#ibcon#read 3, iclass 38, count 2 2006.231.07:36:28.37#ibcon#about to read 4, iclass 38, count 2 2006.231.07:36:28.37#ibcon#read 4, iclass 38, count 2 2006.231.07:36:28.37#ibcon#about to read 5, iclass 38, count 2 2006.231.07:36:28.37#ibcon#read 5, iclass 38, count 2 2006.231.07:36:28.37#ibcon#about to read 6, iclass 38, count 2 2006.231.07:36:28.37#ibcon#read 6, iclass 38, count 2 2006.231.07:36:28.37#ibcon#end of sib2, iclass 38, count 2 2006.231.07:36:28.37#ibcon#*after write, iclass 38, count 2 2006.231.07:36:28.37#ibcon#*before return 0, iclass 38, count 2 2006.231.07:36:28.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:36:28.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:36:28.37#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.07:36:28.37#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:28.37#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:36:28.49#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:36:28.49#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:36:28.49#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:36:28.49#ibcon#first serial, iclass 38, count 0 2006.231.07:36:28.49#ibcon#enter sib2, iclass 38, count 0 2006.231.07:36:28.49#ibcon#flushed, iclass 38, count 0 2006.231.07:36:28.49#ibcon#about to write, iclass 38, count 0 2006.231.07:36:28.49#ibcon#wrote, iclass 38, count 0 2006.231.07:36:28.49#ibcon#about to read 3, iclass 38, count 0 2006.231.07:36:28.51#ibcon#read 3, iclass 38, count 0 2006.231.07:36:28.51#ibcon#about to read 4, iclass 38, count 0 2006.231.07:36:28.51#ibcon#read 4, iclass 38, count 0 2006.231.07:36:28.51#ibcon#about to read 5, iclass 38, count 0 2006.231.07:36:28.51#ibcon#read 5, iclass 38, count 0 2006.231.07:36:28.51#ibcon#about to read 6, iclass 38, count 0 2006.231.07:36:28.51#ibcon#read 6, iclass 38, count 0 2006.231.07:36:28.51#ibcon#end of sib2, iclass 38, count 0 2006.231.07:36:28.51#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:36:28.51#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:36:28.51#ibcon#[25=USB\r\n] 2006.231.07:36:28.51#ibcon#*before write, iclass 38, count 0 2006.231.07:36:28.51#ibcon#enter sib2, iclass 38, count 0 2006.231.07:36:28.51#ibcon#flushed, iclass 38, count 0 2006.231.07:36:28.51#ibcon#about to write, iclass 38, count 0 2006.231.07:36:28.51#ibcon#wrote, iclass 38, count 0 2006.231.07:36:28.51#ibcon#about to read 3, iclass 38, count 0 2006.231.07:36:28.54#ibcon#read 3, iclass 38, count 0 2006.231.07:36:28.54#ibcon#about to read 4, iclass 38, count 0 2006.231.07:36:28.54#ibcon#read 4, iclass 38, count 0 2006.231.07:36:28.54#ibcon#about to read 5, iclass 38, count 0 2006.231.07:36:28.54#ibcon#read 5, iclass 38, count 0 2006.231.07:36:28.54#ibcon#about to read 6, iclass 38, count 0 2006.231.07:36:28.54#ibcon#read 6, iclass 38, count 0 2006.231.07:36:28.54#ibcon#end of sib2, iclass 38, count 0 2006.231.07:36:28.54#ibcon#*after write, iclass 38, count 0 2006.231.07:36:28.54#ibcon#*before return 0, iclass 38, count 0 2006.231.07:36:28.54#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:36:28.54#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:36:28.54#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:36:28.54#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:36:28.54$vc4f8/valo=3,672.99 2006.231.07:36:28.54#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.07:36:28.54#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.07:36:28.54#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:28.54#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:36:28.54#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:36:28.54#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:36:28.54#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:36:28.54#ibcon#first serial, iclass 40, count 0 2006.231.07:36:28.54#ibcon#enter sib2, iclass 40, count 0 2006.231.07:36:28.54#ibcon#flushed, iclass 40, count 0 2006.231.07:36:28.54#ibcon#about to write, iclass 40, count 0 2006.231.07:36:28.54#ibcon#wrote, iclass 40, count 0 2006.231.07:36:28.54#ibcon#about to read 3, iclass 40, count 0 2006.231.07:36:28.56#ibcon#read 3, iclass 40, count 0 2006.231.07:36:28.56#ibcon#about to read 4, iclass 40, count 0 2006.231.07:36:28.56#ibcon#read 4, iclass 40, count 0 2006.231.07:36:28.56#ibcon#about to read 5, iclass 40, count 0 2006.231.07:36:28.56#ibcon#read 5, iclass 40, count 0 2006.231.07:36:28.56#ibcon#about to read 6, iclass 40, count 0 2006.231.07:36:28.56#ibcon#read 6, iclass 40, count 0 2006.231.07:36:28.56#ibcon#end of sib2, iclass 40, count 0 2006.231.07:36:28.56#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:36:28.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:36:28.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:36:28.56#ibcon#*before write, iclass 40, count 0 2006.231.07:36:28.56#ibcon#enter sib2, iclass 40, count 0 2006.231.07:36:28.56#ibcon#flushed, iclass 40, count 0 2006.231.07:36:28.56#ibcon#about to write, iclass 40, count 0 2006.231.07:36:28.56#ibcon#wrote, iclass 40, count 0 2006.231.07:36:28.56#ibcon#about to read 3, iclass 40, count 0 2006.231.07:36:28.60#ibcon#read 3, iclass 40, count 0 2006.231.07:36:28.60#ibcon#about to read 4, iclass 40, count 0 2006.231.07:36:28.60#ibcon#read 4, iclass 40, count 0 2006.231.07:36:28.60#ibcon#about to read 5, iclass 40, count 0 2006.231.07:36:28.60#ibcon#read 5, iclass 40, count 0 2006.231.07:36:28.60#ibcon#about to read 6, iclass 40, count 0 2006.231.07:36:28.60#ibcon#read 6, iclass 40, count 0 2006.231.07:36:28.60#ibcon#end of sib2, iclass 40, count 0 2006.231.07:36:28.60#ibcon#*after write, iclass 40, count 0 2006.231.07:36:28.60#ibcon#*before return 0, iclass 40, count 0 2006.231.07:36:28.60#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:36:28.60#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:36:28.60#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:36:28.60#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:36:28.60$vc4f8/va=3,8 2006.231.07:36:28.60#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.231.07:36:28.60#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.231.07:36:28.60#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:28.60#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:36:28.66#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:36:28.66#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:36:28.66#ibcon#enter wrdev, iclass 4, count 2 2006.231.07:36:28.66#ibcon#first serial, iclass 4, count 2 2006.231.07:36:28.66#ibcon#enter sib2, iclass 4, count 2 2006.231.07:36:28.66#ibcon#flushed, iclass 4, count 2 2006.231.07:36:28.66#ibcon#about to write, iclass 4, count 2 2006.231.07:36:28.66#ibcon#wrote, iclass 4, count 2 2006.231.07:36:28.66#ibcon#about to read 3, iclass 4, count 2 2006.231.07:36:28.68#ibcon#read 3, iclass 4, count 2 2006.231.07:36:28.68#ibcon#about to read 4, iclass 4, count 2 2006.231.07:36:28.68#ibcon#read 4, iclass 4, count 2 2006.231.07:36:28.68#ibcon#about to read 5, iclass 4, count 2 2006.231.07:36:28.68#ibcon#read 5, iclass 4, count 2 2006.231.07:36:28.68#ibcon#about to read 6, iclass 4, count 2 2006.231.07:36:28.68#ibcon#read 6, iclass 4, count 2 2006.231.07:36:28.68#ibcon#end of sib2, iclass 4, count 2 2006.231.07:36:28.68#ibcon#*mode == 0, iclass 4, count 2 2006.231.07:36:28.68#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.231.07:36:28.68#ibcon#[25=AT03-08\r\n] 2006.231.07:36:28.68#ibcon#*before write, iclass 4, count 2 2006.231.07:36:28.68#ibcon#enter sib2, iclass 4, count 2 2006.231.07:36:28.68#ibcon#flushed, iclass 4, count 2 2006.231.07:36:28.68#ibcon#about to write, iclass 4, count 2 2006.231.07:36:28.68#ibcon#wrote, iclass 4, count 2 2006.231.07:36:28.68#ibcon#about to read 3, iclass 4, count 2 2006.231.07:36:28.71#ibcon#read 3, iclass 4, count 2 2006.231.07:36:28.71#ibcon#about to read 4, iclass 4, count 2 2006.231.07:36:28.71#ibcon#read 4, iclass 4, count 2 2006.231.07:36:28.71#ibcon#about to read 5, iclass 4, count 2 2006.231.07:36:28.71#ibcon#read 5, iclass 4, count 2 2006.231.07:36:28.71#ibcon#about to read 6, iclass 4, count 2 2006.231.07:36:28.71#ibcon#read 6, iclass 4, count 2 2006.231.07:36:28.71#ibcon#end of sib2, iclass 4, count 2 2006.231.07:36:28.71#ibcon#*after write, iclass 4, count 2 2006.231.07:36:28.71#ibcon#*before return 0, iclass 4, count 2 2006.231.07:36:28.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:36:28.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:36:28.71#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.231.07:36:28.71#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:28.71#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:36:28.83#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:36:28.83#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:36:28.83#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:36:28.83#ibcon#first serial, iclass 4, count 0 2006.231.07:36:28.83#ibcon#enter sib2, iclass 4, count 0 2006.231.07:36:28.83#ibcon#flushed, iclass 4, count 0 2006.231.07:36:28.83#ibcon#about to write, iclass 4, count 0 2006.231.07:36:28.83#ibcon#wrote, iclass 4, count 0 2006.231.07:36:28.83#ibcon#about to read 3, iclass 4, count 0 2006.231.07:36:28.85#ibcon#read 3, iclass 4, count 0 2006.231.07:36:28.85#ibcon#about to read 4, iclass 4, count 0 2006.231.07:36:28.85#ibcon#read 4, iclass 4, count 0 2006.231.07:36:28.85#ibcon#about to read 5, iclass 4, count 0 2006.231.07:36:28.85#ibcon#read 5, iclass 4, count 0 2006.231.07:36:28.85#ibcon#about to read 6, iclass 4, count 0 2006.231.07:36:28.85#ibcon#read 6, iclass 4, count 0 2006.231.07:36:28.85#ibcon#end of sib2, iclass 4, count 0 2006.231.07:36:28.85#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:36:28.85#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:36:28.85#ibcon#[25=USB\r\n] 2006.231.07:36:28.85#ibcon#*before write, iclass 4, count 0 2006.231.07:36:28.85#ibcon#enter sib2, iclass 4, count 0 2006.231.07:36:28.85#ibcon#flushed, iclass 4, count 0 2006.231.07:36:28.85#ibcon#about to write, iclass 4, count 0 2006.231.07:36:28.85#ibcon#wrote, iclass 4, count 0 2006.231.07:36:28.85#ibcon#about to read 3, iclass 4, count 0 2006.231.07:36:28.90#ibcon#read 3, iclass 4, count 0 2006.231.07:36:28.90#ibcon#about to read 4, iclass 4, count 0 2006.231.07:36:28.90#ibcon#read 4, iclass 4, count 0 2006.231.07:36:28.90#ibcon#about to read 5, iclass 4, count 0 2006.231.07:36:28.90#ibcon#read 5, iclass 4, count 0 2006.231.07:36:28.90#ibcon#about to read 6, iclass 4, count 0 2006.231.07:36:28.90#ibcon#read 6, iclass 4, count 0 2006.231.07:36:28.90#ibcon#end of sib2, iclass 4, count 0 2006.231.07:36:28.90#ibcon#*after write, iclass 4, count 0 2006.231.07:36:28.90#ibcon#*before return 0, iclass 4, count 0 2006.231.07:36:28.90#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:36:28.90#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:36:28.90#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:36:28.90#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:36:28.90$vc4f8/valo=4,832.99 2006.231.07:36:28.90#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.231.07:36:28.90#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.231.07:36:28.90#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:28.90#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:36:28.90#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:36:28.90#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:36:28.90#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:36:28.90#ibcon#first serial, iclass 6, count 0 2006.231.07:36:28.90#ibcon#enter sib2, iclass 6, count 0 2006.231.07:36:28.90#ibcon#flushed, iclass 6, count 0 2006.231.07:36:28.90#ibcon#about to write, iclass 6, count 0 2006.231.07:36:28.90#ibcon#wrote, iclass 6, count 0 2006.231.07:36:28.90#ibcon#about to read 3, iclass 6, count 0 2006.231.07:36:28.91#ibcon#read 3, iclass 6, count 0 2006.231.07:36:28.91#ibcon#about to read 4, iclass 6, count 0 2006.231.07:36:28.91#ibcon#read 4, iclass 6, count 0 2006.231.07:36:28.91#ibcon#about to read 5, iclass 6, count 0 2006.231.07:36:28.91#ibcon#read 5, iclass 6, count 0 2006.231.07:36:28.91#ibcon#about to read 6, iclass 6, count 0 2006.231.07:36:28.91#ibcon#read 6, iclass 6, count 0 2006.231.07:36:28.91#ibcon#end of sib2, iclass 6, count 0 2006.231.07:36:28.91#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:36:28.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:36:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:36:28.91#ibcon#*before write, iclass 6, count 0 2006.231.07:36:28.91#ibcon#enter sib2, iclass 6, count 0 2006.231.07:36:28.91#ibcon#flushed, iclass 6, count 0 2006.231.07:36:28.91#ibcon#about to write, iclass 6, count 0 2006.231.07:36:28.91#ibcon#wrote, iclass 6, count 0 2006.231.07:36:28.91#ibcon#about to read 3, iclass 6, count 0 2006.231.07:36:28.95#ibcon#read 3, iclass 6, count 0 2006.231.07:36:28.95#ibcon#about to read 4, iclass 6, count 0 2006.231.07:36:28.95#ibcon#read 4, iclass 6, count 0 2006.231.07:36:28.95#ibcon#about to read 5, iclass 6, count 0 2006.231.07:36:28.95#ibcon#read 5, iclass 6, count 0 2006.231.07:36:28.95#ibcon#about to read 6, iclass 6, count 0 2006.231.07:36:28.95#ibcon#read 6, iclass 6, count 0 2006.231.07:36:28.95#ibcon#end of sib2, iclass 6, count 0 2006.231.07:36:28.95#ibcon#*after write, iclass 6, count 0 2006.231.07:36:28.95#ibcon#*before return 0, iclass 6, count 0 2006.231.07:36:28.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:36:28.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:36:28.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:36:28.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:36:28.95$vc4f8/va=4,7 2006.231.07:36:28.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.231.07:36:28.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.231.07:36:28.95#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:28.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:36:29.02#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:36:29.02#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:36:29.02#ibcon#enter wrdev, iclass 10, count 2 2006.231.07:36:29.02#ibcon#first serial, iclass 10, count 2 2006.231.07:36:29.02#ibcon#enter sib2, iclass 10, count 2 2006.231.07:36:29.02#ibcon#flushed, iclass 10, count 2 2006.231.07:36:29.02#ibcon#about to write, iclass 10, count 2 2006.231.07:36:29.02#ibcon#wrote, iclass 10, count 2 2006.231.07:36:29.02#ibcon#about to read 3, iclass 10, count 2 2006.231.07:36:29.04#ibcon#read 3, iclass 10, count 2 2006.231.07:36:29.04#ibcon#about to read 4, iclass 10, count 2 2006.231.07:36:29.04#ibcon#read 4, iclass 10, count 2 2006.231.07:36:29.04#ibcon#about to read 5, iclass 10, count 2 2006.231.07:36:29.04#ibcon#read 5, iclass 10, count 2 2006.231.07:36:29.04#ibcon#about to read 6, iclass 10, count 2 2006.231.07:36:29.04#ibcon#read 6, iclass 10, count 2 2006.231.07:36:29.04#ibcon#end of sib2, iclass 10, count 2 2006.231.07:36:29.04#ibcon#*mode == 0, iclass 10, count 2 2006.231.07:36:29.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.231.07:36:29.04#ibcon#[25=AT04-07\r\n] 2006.231.07:36:29.04#ibcon#*before write, iclass 10, count 2 2006.231.07:36:29.04#ibcon#enter sib2, iclass 10, count 2 2006.231.07:36:29.04#ibcon#flushed, iclass 10, count 2 2006.231.07:36:29.04#ibcon#about to write, iclass 10, count 2 2006.231.07:36:29.04#ibcon#wrote, iclass 10, count 2 2006.231.07:36:29.04#ibcon#about to read 3, iclass 10, count 2 2006.231.07:36:29.07#ibcon#read 3, iclass 10, count 2 2006.231.07:36:29.07#ibcon#about to read 4, iclass 10, count 2 2006.231.07:36:29.07#ibcon#read 4, iclass 10, count 2 2006.231.07:36:29.07#ibcon#about to read 5, iclass 10, count 2 2006.231.07:36:29.07#ibcon#read 5, iclass 10, count 2 2006.231.07:36:29.07#ibcon#about to read 6, iclass 10, count 2 2006.231.07:36:29.07#ibcon#read 6, iclass 10, count 2 2006.231.07:36:29.07#ibcon#end of sib2, iclass 10, count 2 2006.231.07:36:29.07#ibcon#*after write, iclass 10, count 2 2006.231.07:36:29.07#ibcon#*before return 0, iclass 10, count 2 2006.231.07:36:29.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:36:29.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:36:29.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.231.07:36:29.07#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:29.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:36:29.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:36:29.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:36:29.19#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:36:29.19#ibcon#first serial, iclass 10, count 0 2006.231.07:36:29.19#ibcon#enter sib2, iclass 10, count 0 2006.231.07:36:29.19#ibcon#flushed, iclass 10, count 0 2006.231.07:36:29.19#ibcon#about to write, iclass 10, count 0 2006.231.07:36:29.19#ibcon#wrote, iclass 10, count 0 2006.231.07:36:29.19#ibcon#about to read 3, iclass 10, count 0 2006.231.07:36:29.21#ibcon#read 3, iclass 10, count 0 2006.231.07:36:29.21#ibcon#about to read 4, iclass 10, count 0 2006.231.07:36:29.21#ibcon#read 4, iclass 10, count 0 2006.231.07:36:29.21#ibcon#about to read 5, iclass 10, count 0 2006.231.07:36:29.21#ibcon#read 5, iclass 10, count 0 2006.231.07:36:29.21#ibcon#about to read 6, iclass 10, count 0 2006.231.07:36:29.21#ibcon#read 6, iclass 10, count 0 2006.231.07:36:29.21#ibcon#end of sib2, iclass 10, count 0 2006.231.07:36:29.21#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:36:29.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:36:29.21#ibcon#[25=USB\r\n] 2006.231.07:36:29.21#ibcon#*before write, iclass 10, count 0 2006.231.07:36:29.21#ibcon#enter sib2, iclass 10, count 0 2006.231.07:36:29.21#ibcon#flushed, iclass 10, count 0 2006.231.07:36:29.21#ibcon#about to write, iclass 10, count 0 2006.231.07:36:29.21#ibcon#wrote, iclass 10, count 0 2006.231.07:36:29.21#ibcon#about to read 3, iclass 10, count 0 2006.231.07:36:29.24#ibcon#read 3, iclass 10, count 0 2006.231.07:36:29.24#ibcon#about to read 4, iclass 10, count 0 2006.231.07:36:29.24#ibcon#read 4, iclass 10, count 0 2006.231.07:36:29.24#ibcon#about to read 5, iclass 10, count 0 2006.231.07:36:29.24#ibcon#read 5, iclass 10, count 0 2006.231.07:36:29.24#ibcon#about to read 6, iclass 10, count 0 2006.231.07:36:29.24#ibcon#read 6, iclass 10, count 0 2006.231.07:36:29.24#ibcon#end of sib2, iclass 10, count 0 2006.231.07:36:29.24#ibcon#*after write, iclass 10, count 0 2006.231.07:36:29.24#ibcon#*before return 0, iclass 10, count 0 2006.231.07:36:29.24#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:36:29.24#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:36:29.24#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:36:29.24#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:36:29.24$vc4f8/valo=5,652.99 2006.231.07:36:29.24#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.07:36:29.24#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.07:36:29.24#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:29.24#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:36:29.24#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:36:29.24#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:36:29.24#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:36:29.24#ibcon#first serial, iclass 12, count 0 2006.231.07:36:29.24#ibcon#enter sib2, iclass 12, count 0 2006.231.07:36:29.24#ibcon#flushed, iclass 12, count 0 2006.231.07:36:29.24#ibcon#about to write, iclass 12, count 0 2006.231.07:36:29.24#ibcon#wrote, iclass 12, count 0 2006.231.07:36:29.24#ibcon#about to read 3, iclass 12, count 0 2006.231.07:36:29.26#ibcon#read 3, iclass 12, count 0 2006.231.07:36:29.26#ibcon#about to read 4, iclass 12, count 0 2006.231.07:36:29.26#ibcon#read 4, iclass 12, count 0 2006.231.07:36:29.26#ibcon#about to read 5, iclass 12, count 0 2006.231.07:36:29.26#ibcon#read 5, iclass 12, count 0 2006.231.07:36:29.26#ibcon#about to read 6, iclass 12, count 0 2006.231.07:36:29.26#ibcon#read 6, iclass 12, count 0 2006.231.07:36:29.26#ibcon#end of sib2, iclass 12, count 0 2006.231.07:36:29.26#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:36:29.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:36:29.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:36:29.26#ibcon#*before write, iclass 12, count 0 2006.231.07:36:29.26#ibcon#enter sib2, iclass 12, count 0 2006.231.07:36:29.26#ibcon#flushed, iclass 12, count 0 2006.231.07:36:29.26#ibcon#about to write, iclass 12, count 0 2006.231.07:36:29.26#ibcon#wrote, iclass 12, count 0 2006.231.07:36:29.26#ibcon#about to read 3, iclass 12, count 0 2006.231.07:36:29.30#ibcon#read 3, iclass 12, count 0 2006.231.07:36:29.30#ibcon#about to read 4, iclass 12, count 0 2006.231.07:36:29.30#ibcon#read 4, iclass 12, count 0 2006.231.07:36:29.30#ibcon#about to read 5, iclass 12, count 0 2006.231.07:36:29.30#ibcon#read 5, iclass 12, count 0 2006.231.07:36:29.30#ibcon#about to read 6, iclass 12, count 0 2006.231.07:36:29.30#ibcon#read 6, iclass 12, count 0 2006.231.07:36:29.30#ibcon#end of sib2, iclass 12, count 0 2006.231.07:36:29.30#ibcon#*after write, iclass 12, count 0 2006.231.07:36:29.30#ibcon#*before return 0, iclass 12, count 0 2006.231.07:36:29.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:36:29.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:36:29.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:36:29.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:36:29.30$vc4f8/va=5,7 2006.231.07:36:29.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.07:36:29.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.07:36:29.30#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:29.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:36:29.36#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:36:29.36#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:36:29.36#ibcon#enter wrdev, iclass 14, count 2 2006.231.07:36:29.36#ibcon#first serial, iclass 14, count 2 2006.231.07:36:29.36#ibcon#enter sib2, iclass 14, count 2 2006.231.07:36:29.36#ibcon#flushed, iclass 14, count 2 2006.231.07:36:29.36#ibcon#about to write, iclass 14, count 2 2006.231.07:36:29.36#ibcon#wrote, iclass 14, count 2 2006.231.07:36:29.36#ibcon#about to read 3, iclass 14, count 2 2006.231.07:36:29.38#ibcon#read 3, iclass 14, count 2 2006.231.07:36:29.38#ibcon#about to read 4, iclass 14, count 2 2006.231.07:36:29.38#ibcon#read 4, iclass 14, count 2 2006.231.07:36:29.38#ibcon#about to read 5, iclass 14, count 2 2006.231.07:36:29.38#ibcon#read 5, iclass 14, count 2 2006.231.07:36:29.38#ibcon#about to read 6, iclass 14, count 2 2006.231.07:36:29.38#ibcon#read 6, iclass 14, count 2 2006.231.07:36:29.38#ibcon#end of sib2, iclass 14, count 2 2006.231.07:36:29.38#ibcon#*mode == 0, iclass 14, count 2 2006.231.07:36:29.38#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.07:36:29.38#ibcon#[25=AT05-07\r\n] 2006.231.07:36:29.38#ibcon#*before write, iclass 14, count 2 2006.231.07:36:29.38#ibcon#enter sib2, iclass 14, count 2 2006.231.07:36:29.38#ibcon#flushed, iclass 14, count 2 2006.231.07:36:29.38#ibcon#about to write, iclass 14, count 2 2006.231.07:36:29.38#ibcon#wrote, iclass 14, count 2 2006.231.07:36:29.38#ibcon#about to read 3, iclass 14, count 2 2006.231.07:36:29.41#ibcon#read 3, iclass 14, count 2 2006.231.07:36:29.41#ibcon#about to read 4, iclass 14, count 2 2006.231.07:36:29.41#ibcon#read 4, iclass 14, count 2 2006.231.07:36:29.41#ibcon#about to read 5, iclass 14, count 2 2006.231.07:36:29.41#ibcon#read 5, iclass 14, count 2 2006.231.07:36:29.41#ibcon#about to read 6, iclass 14, count 2 2006.231.07:36:29.41#ibcon#read 6, iclass 14, count 2 2006.231.07:36:29.41#ibcon#end of sib2, iclass 14, count 2 2006.231.07:36:29.41#ibcon#*after write, iclass 14, count 2 2006.231.07:36:29.41#ibcon#*before return 0, iclass 14, count 2 2006.231.07:36:29.41#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:36:29.41#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:36:29.41#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.07:36:29.41#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:29.41#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:36:29.53#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:36:29.53#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:36:29.53#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:36:29.53#ibcon#first serial, iclass 14, count 0 2006.231.07:36:29.53#ibcon#enter sib2, iclass 14, count 0 2006.231.07:36:29.53#ibcon#flushed, iclass 14, count 0 2006.231.07:36:29.53#ibcon#about to write, iclass 14, count 0 2006.231.07:36:29.53#ibcon#wrote, iclass 14, count 0 2006.231.07:36:29.53#ibcon#about to read 3, iclass 14, count 0 2006.231.07:36:29.55#ibcon#read 3, iclass 14, count 0 2006.231.07:36:29.55#ibcon#about to read 4, iclass 14, count 0 2006.231.07:36:29.55#ibcon#read 4, iclass 14, count 0 2006.231.07:36:29.55#ibcon#about to read 5, iclass 14, count 0 2006.231.07:36:29.55#ibcon#read 5, iclass 14, count 0 2006.231.07:36:29.55#ibcon#about to read 6, iclass 14, count 0 2006.231.07:36:29.55#ibcon#read 6, iclass 14, count 0 2006.231.07:36:29.55#ibcon#end of sib2, iclass 14, count 0 2006.231.07:36:29.55#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:36:29.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:36:29.55#ibcon#[25=USB\r\n] 2006.231.07:36:29.55#ibcon#*before write, iclass 14, count 0 2006.231.07:36:29.55#ibcon#enter sib2, iclass 14, count 0 2006.231.07:36:29.55#ibcon#flushed, iclass 14, count 0 2006.231.07:36:29.55#ibcon#about to write, iclass 14, count 0 2006.231.07:36:29.55#ibcon#wrote, iclass 14, count 0 2006.231.07:36:29.55#ibcon#about to read 3, iclass 14, count 0 2006.231.07:36:29.58#ibcon#read 3, iclass 14, count 0 2006.231.07:36:29.58#ibcon#about to read 4, iclass 14, count 0 2006.231.07:36:29.58#ibcon#read 4, iclass 14, count 0 2006.231.07:36:29.58#ibcon#about to read 5, iclass 14, count 0 2006.231.07:36:29.58#ibcon#read 5, iclass 14, count 0 2006.231.07:36:29.58#ibcon#about to read 6, iclass 14, count 0 2006.231.07:36:29.58#ibcon#read 6, iclass 14, count 0 2006.231.07:36:29.58#ibcon#end of sib2, iclass 14, count 0 2006.231.07:36:29.58#ibcon#*after write, iclass 14, count 0 2006.231.07:36:29.58#ibcon#*before return 0, iclass 14, count 0 2006.231.07:36:29.58#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:36:29.58#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:36:29.58#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:36:29.58#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:36:29.58$vc4f8/valo=6,772.99 2006.231.07:36:29.58#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.07:36:29.58#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.07:36:29.58#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:29.58#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:36:29.58#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:36:29.58#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:36:29.58#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:36:29.58#ibcon#first serial, iclass 16, count 0 2006.231.07:36:29.58#ibcon#enter sib2, iclass 16, count 0 2006.231.07:36:29.58#ibcon#flushed, iclass 16, count 0 2006.231.07:36:29.58#ibcon#about to write, iclass 16, count 0 2006.231.07:36:29.58#ibcon#wrote, iclass 16, count 0 2006.231.07:36:29.58#ibcon#about to read 3, iclass 16, count 0 2006.231.07:36:29.60#ibcon#read 3, iclass 16, count 0 2006.231.07:36:29.60#ibcon#about to read 4, iclass 16, count 0 2006.231.07:36:29.60#ibcon#read 4, iclass 16, count 0 2006.231.07:36:29.60#ibcon#about to read 5, iclass 16, count 0 2006.231.07:36:29.60#ibcon#read 5, iclass 16, count 0 2006.231.07:36:29.60#ibcon#about to read 6, iclass 16, count 0 2006.231.07:36:29.60#ibcon#read 6, iclass 16, count 0 2006.231.07:36:29.60#ibcon#end of sib2, iclass 16, count 0 2006.231.07:36:29.60#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:36:29.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:36:29.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:36:29.60#ibcon#*before write, iclass 16, count 0 2006.231.07:36:29.60#ibcon#enter sib2, iclass 16, count 0 2006.231.07:36:29.60#ibcon#flushed, iclass 16, count 0 2006.231.07:36:29.60#ibcon#about to write, iclass 16, count 0 2006.231.07:36:29.60#ibcon#wrote, iclass 16, count 0 2006.231.07:36:29.60#ibcon#about to read 3, iclass 16, count 0 2006.231.07:36:29.64#ibcon#read 3, iclass 16, count 0 2006.231.07:36:29.64#ibcon#about to read 4, iclass 16, count 0 2006.231.07:36:29.64#ibcon#read 4, iclass 16, count 0 2006.231.07:36:29.64#ibcon#about to read 5, iclass 16, count 0 2006.231.07:36:29.64#ibcon#read 5, iclass 16, count 0 2006.231.07:36:29.64#ibcon#about to read 6, iclass 16, count 0 2006.231.07:36:29.64#ibcon#read 6, iclass 16, count 0 2006.231.07:36:29.64#ibcon#end of sib2, iclass 16, count 0 2006.231.07:36:29.64#ibcon#*after write, iclass 16, count 0 2006.231.07:36:29.64#ibcon#*before return 0, iclass 16, count 0 2006.231.07:36:29.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:36:29.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:36:29.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:36:29.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:36:29.64$vc4f8/va=6,6 2006.231.07:36:29.64#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.231.07:36:29.64#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.231.07:36:29.64#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:29.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:36:29.70#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:36:29.70#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:36:29.70#ibcon#enter wrdev, iclass 18, count 2 2006.231.07:36:29.70#ibcon#first serial, iclass 18, count 2 2006.231.07:36:29.70#ibcon#enter sib2, iclass 18, count 2 2006.231.07:36:29.70#ibcon#flushed, iclass 18, count 2 2006.231.07:36:29.70#ibcon#about to write, iclass 18, count 2 2006.231.07:36:29.70#ibcon#wrote, iclass 18, count 2 2006.231.07:36:29.70#ibcon#about to read 3, iclass 18, count 2 2006.231.07:36:29.72#ibcon#read 3, iclass 18, count 2 2006.231.07:36:29.72#ibcon#about to read 4, iclass 18, count 2 2006.231.07:36:29.72#ibcon#read 4, iclass 18, count 2 2006.231.07:36:29.72#ibcon#about to read 5, iclass 18, count 2 2006.231.07:36:29.72#ibcon#read 5, iclass 18, count 2 2006.231.07:36:29.72#ibcon#about to read 6, iclass 18, count 2 2006.231.07:36:29.72#ibcon#read 6, iclass 18, count 2 2006.231.07:36:29.72#ibcon#end of sib2, iclass 18, count 2 2006.231.07:36:29.72#ibcon#*mode == 0, iclass 18, count 2 2006.231.07:36:29.72#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.231.07:36:29.72#ibcon#[25=AT06-06\r\n] 2006.231.07:36:29.72#ibcon#*before write, iclass 18, count 2 2006.231.07:36:29.72#ibcon#enter sib2, iclass 18, count 2 2006.231.07:36:29.72#ibcon#flushed, iclass 18, count 2 2006.231.07:36:29.72#ibcon#about to write, iclass 18, count 2 2006.231.07:36:29.72#ibcon#wrote, iclass 18, count 2 2006.231.07:36:29.72#ibcon#about to read 3, iclass 18, count 2 2006.231.07:36:29.75#ibcon#read 3, iclass 18, count 2 2006.231.07:36:29.75#ibcon#about to read 4, iclass 18, count 2 2006.231.07:36:29.75#ibcon#read 4, iclass 18, count 2 2006.231.07:36:29.75#ibcon#about to read 5, iclass 18, count 2 2006.231.07:36:29.75#ibcon#read 5, iclass 18, count 2 2006.231.07:36:29.75#ibcon#about to read 6, iclass 18, count 2 2006.231.07:36:29.75#ibcon#read 6, iclass 18, count 2 2006.231.07:36:29.75#ibcon#end of sib2, iclass 18, count 2 2006.231.07:36:29.75#ibcon#*after write, iclass 18, count 2 2006.231.07:36:29.75#ibcon#*before return 0, iclass 18, count 2 2006.231.07:36:29.75#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:36:29.75#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:36:29.75#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.231.07:36:29.75#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:29.75#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:36:29.87#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:36:29.87#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:36:29.87#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:36:29.87#ibcon#first serial, iclass 18, count 0 2006.231.07:36:29.87#ibcon#enter sib2, iclass 18, count 0 2006.231.07:36:29.87#ibcon#flushed, iclass 18, count 0 2006.231.07:36:29.87#ibcon#about to write, iclass 18, count 0 2006.231.07:36:29.87#ibcon#wrote, iclass 18, count 0 2006.231.07:36:29.87#ibcon#about to read 3, iclass 18, count 0 2006.231.07:36:29.89#ibcon#read 3, iclass 18, count 0 2006.231.07:36:29.89#ibcon#about to read 4, iclass 18, count 0 2006.231.07:36:29.89#ibcon#read 4, iclass 18, count 0 2006.231.07:36:29.89#ibcon#about to read 5, iclass 18, count 0 2006.231.07:36:29.89#ibcon#read 5, iclass 18, count 0 2006.231.07:36:29.89#ibcon#about to read 6, iclass 18, count 0 2006.231.07:36:29.89#ibcon#read 6, iclass 18, count 0 2006.231.07:36:29.89#ibcon#end of sib2, iclass 18, count 0 2006.231.07:36:29.89#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:36:29.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:36:29.89#ibcon#[25=USB\r\n] 2006.231.07:36:29.89#ibcon#*before write, iclass 18, count 0 2006.231.07:36:29.89#ibcon#enter sib2, iclass 18, count 0 2006.231.07:36:29.89#ibcon#flushed, iclass 18, count 0 2006.231.07:36:29.89#ibcon#about to write, iclass 18, count 0 2006.231.07:36:29.89#ibcon#wrote, iclass 18, count 0 2006.231.07:36:29.89#ibcon#about to read 3, iclass 18, count 0 2006.231.07:36:29.92#ibcon#read 3, iclass 18, count 0 2006.231.07:36:29.92#ibcon#about to read 4, iclass 18, count 0 2006.231.07:36:29.92#ibcon#read 4, iclass 18, count 0 2006.231.07:36:29.92#ibcon#about to read 5, iclass 18, count 0 2006.231.07:36:29.92#ibcon#read 5, iclass 18, count 0 2006.231.07:36:29.92#ibcon#about to read 6, iclass 18, count 0 2006.231.07:36:29.92#ibcon#read 6, iclass 18, count 0 2006.231.07:36:29.92#ibcon#end of sib2, iclass 18, count 0 2006.231.07:36:29.92#ibcon#*after write, iclass 18, count 0 2006.231.07:36:29.92#ibcon#*before return 0, iclass 18, count 0 2006.231.07:36:29.92#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:36:29.92#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:36:29.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:36:29.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:36:29.92$vc4f8/valo=7,832.99 2006.231.07:36:29.92#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.231.07:36:29.92#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.231.07:36:29.92#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:29.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:36:29.92#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:36:29.92#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:36:29.92#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:36:29.92#ibcon#first serial, iclass 20, count 0 2006.231.07:36:29.92#ibcon#enter sib2, iclass 20, count 0 2006.231.07:36:29.92#ibcon#flushed, iclass 20, count 0 2006.231.07:36:29.92#ibcon#about to write, iclass 20, count 0 2006.231.07:36:29.92#ibcon#wrote, iclass 20, count 0 2006.231.07:36:29.92#ibcon#about to read 3, iclass 20, count 0 2006.231.07:36:29.94#ibcon#read 3, iclass 20, count 0 2006.231.07:36:29.94#ibcon#about to read 4, iclass 20, count 0 2006.231.07:36:29.94#ibcon#read 4, iclass 20, count 0 2006.231.07:36:29.94#ibcon#about to read 5, iclass 20, count 0 2006.231.07:36:29.94#ibcon#read 5, iclass 20, count 0 2006.231.07:36:29.94#ibcon#about to read 6, iclass 20, count 0 2006.231.07:36:29.94#ibcon#read 6, iclass 20, count 0 2006.231.07:36:29.94#ibcon#end of sib2, iclass 20, count 0 2006.231.07:36:29.94#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:36:29.94#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:36:29.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:36:29.94#ibcon#*before write, iclass 20, count 0 2006.231.07:36:29.94#ibcon#enter sib2, iclass 20, count 0 2006.231.07:36:29.94#ibcon#flushed, iclass 20, count 0 2006.231.07:36:29.94#ibcon#about to write, iclass 20, count 0 2006.231.07:36:29.94#ibcon#wrote, iclass 20, count 0 2006.231.07:36:29.94#ibcon#about to read 3, iclass 20, count 0 2006.231.07:36:29.98#ibcon#read 3, iclass 20, count 0 2006.231.07:36:29.98#ibcon#about to read 4, iclass 20, count 0 2006.231.07:36:29.98#ibcon#read 4, iclass 20, count 0 2006.231.07:36:29.98#ibcon#about to read 5, iclass 20, count 0 2006.231.07:36:29.98#ibcon#read 5, iclass 20, count 0 2006.231.07:36:29.98#ibcon#about to read 6, iclass 20, count 0 2006.231.07:36:29.98#ibcon#read 6, iclass 20, count 0 2006.231.07:36:29.98#ibcon#end of sib2, iclass 20, count 0 2006.231.07:36:29.98#ibcon#*after write, iclass 20, count 0 2006.231.07:36:29.98#ibcon#*before return 0, iclass 20, count 0 2006.231.07:36:29.98#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:36:29.98#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:36:29.98#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:36:29.98#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:36:29.98$vc4f8/va=7,6 2006.231.07:36:29.98#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.231.07:36:29.98#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.231.07:36:29.98#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:29.98#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:36:30.04#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:36:30.04#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:36:30.04#ibcon#enter wrdev, iclass 22, count 2 2006.231.07:36:30.04#ibcon#first serial, iclass 22, count 2 2006.231.07:36:30.04#ibcon#enter sib2, iclass 22, count 2 2006.231.07:36:30.04#ibcon#flushed, iclass 22, count 2 2006.231.07:36:30.04#ibcon#about to write, iclass 22, count 2 2006.231.07:36:30.04#ibcon#wrote, iclass 22, count 2 2006.231.07:36:30.04#ibcon#about to read 3, iclass 22, count 2 2006.231.07:36:30.06#ibcon#read 3, iclass 22, count 2 2006.231.07:36:30.06#ibcon#about to read 4, iclass 22, count 2 2006.231.07:36:30.06#ibcon#read 4, iclass 22, count 2 2006.231.07:36:30.06#ibcon#about to read 5, iclass 22, count 2 2006.231.07:36:30.06#ibcon#read 5, iclass 22, count 2 2006.231.07:36:30.06#ibcon#about to read 6, iclass 22, count 2 2006.231.07:36:30.06#ibcon#read 6, iclass 22, count 2 2006.231.07:36:30.06#ibcon#end of sib2, iclass 22, count 2 2006.231.07:36:30.06#ibcon#*mode == 0, iclass 22, count 2 2006.231.07:36:30.06#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.231.07:36:30.06#ibcon#[25=AT07-06\r\n] 2006.231.07:36:30.06#ibcon#*before write, iclass 22, count 2 2006.231.07:36:30.06#ibcon#enter sib2, iclass 22, count 2 2006.231.07:36:30.06#ibcon#flushed, iclass 22, count 2 2006.231.07:36:30.06#ibcon#about to write, iclass 22, count 2 2006.231.07:36:30.06#ibcon#wrote, iclass 22, count 2 2006.231.07:36:30.06#ibcon#about to read 3, iclass 22, count 2 2006.231.07:36:30.09#ibcon#read 3, iclass 22, count 2 2006.231.07:36:30.09#ibcon#about to read 4, iclass 22, count 2 2006.231.07:36:30.09#ibcon#read 4, iclass 22, count 2 2006.231.07:36:30.09#ibcon#about to read 5, iclass 22, count 2 2006.231.07:36:30.09#ibcon#read 5, iclass 22, count 2 2006.231.07:36:30.09#ibcon#about to read 6, iclass 22, count 2 2006.231.07:36:30.09#ibcon#read 6, iclass 22, count 2 2006.231.07:36:30.09#ibcon#end of sib2, iclass 22, count 2 2006.231.07:36:30.09#ibcon#*after write, iclass 22, count 2 2006.231.07:36:30.09#ibcon#*before return 0, iclass 22, count 2 2006.231.07:36:30.09#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:36:30.09#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:36:30.09#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.231.07:36:30.09#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:30.09#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:36:30.21#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:36:30.21#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:36:30.21#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:36:30.21#ibcon#first serial, iclass 22, count 0 2006.231.07:36:30.21#ibcon#enter sib2, iclass 22, count 0 2006.231.07:36:30.21#ibcon#flushed, iclass 22, count 0 2006.231.07:36:30.21#ibcon#about to write, iclass 22, count 0 2006.231.07:36:30.21#ibcon#wrote, iclass 22, count 0 2006.231.07:36:30.21#ibcon#about to read 3, iclass 22, count 0 2006.231.07:36:30.23#ibcon#read 3, iclass 22, count 0 2006.231.07:36:30.23#ibcon#about to read 4, iclass 22, count 0 2006.231.07:36:30.23#ibcon#read 4, iclass 22, count 0 2006.231.07:36:30.23#ibcon#about to read 5, iclass 22, count 0 2006.231.07:36:30.23#ibcon#read 5, iclass 22, count 0 2006.231.07:36:30.23#ibcon#about to read 6, iclass 22, count 0 2006.231.07:36:30.23#ibcon#read 6, iclass 22, count 0 2006.231.07:36:30.23#ibcon#end of sib2, iclass 22, count 0 2006.231.07:36:30.23#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:36:30.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:36:30.23#ibcon#[25=USB\r\n] 2006.231.07:36:30.23#ibcon#*before write, iclass 22, count 0 2006.231.07:36:30.23#ibcon#enter sib2, iclass 22, count 0 2006.231.07:36:30.23#ibcon#flushed, iclass 22, count 0 2006.231.07:36:30.23#ibcon#about to write, iclass 22, count 0 2006.231.07:36:30.23#ibcon#wrote, iclass 22, count 0 2006.231.07:36:30.23#ibcon#about to read 3, iclass 22, count 0 2006.231.07:36:30.26#ibcon#read 3, iclass 22, count 0 2006.231.07:36:30.26#ibcon#about to read 4, iclass 22, count 0 2006.231.07:36:30.26#ibcon#read 4, iclass 22, count 0 2006.231.07:36:30.26#ibcon#about to read 5, iclass 22, count 0 2006.231.07:36:30.26#ibcon#read 5, iclass 22, count 0 2006.231.07:36:30.26#ibcon#about to read 6, iclass 22, count 0 2006.231.07:36:30.26#ibcon#read 6, iclass 22, count 0 2006.231.07:36:30.26#ibcon#end of sib2, iclass 22, count 0 2006.231.07:36:30.26#ibcon#*after write, iclass 22, count 0 2006.231.07:36:30.26#ibcon#*before return 0, iclass 22, count 0 2006.231.07:36:30.26#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:36:30.26#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:36:30.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:36:30.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:36:30.26$vc4f8/valo=8,852.99 2006.231.07:36:30.26#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.231.07:36:30.26#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.231.07:36:30.26#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:30.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:36:30.26#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:36:30.26#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:36:30.26#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:36:30.26#ibcon#first serial, iclass 24, count 0 2006.231.07:36:30.26#ibcon#enter sib2, iclass 24, count 0 2006.231.07:36:30.26#ibcon#flushed, iclass 24, count 0 2006.231.07:36:30.26#ibcon#about to write, iclass 24, count 0 2006.231.07:36:30.26#ibcon#wrote, iclass 24, count 0 2006.231.07:36:30.26#ibcon#about to read 3, iclass 24, count 0 2006.231.07:36:30.28#ibcon#read 3, iclass 24, count 0 2006.231.07:36:30.28#ibcon#about to read 4, iclass 24, count 0 2006.231.07:36:30.28#ibcon#read 4, iclass 24, count 0 2006.231.07:36:30.28#ibcon#about to read 5, iclass 24, count 0 2006.231.07:36:30.28#ibcon#read 5, iclass 24, count 0 2006.231.07:36:30.28#ibcon#about to read 6, iclass 24, count 0 2006.231.07:36:30.28#ibcon#read 6, iclass 24, count 0 2006.231.07:36:30.28#ibcon#end of sib2, iclass 24, count 0 2006.231.07:36:30.28#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:36:30.28#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:36:30.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:36:30.28#ibcon#*before write, iclass 24, count 0 2006.231.07:36:30.28#ibcon#enter sib2, iclass 24, count 0 2006.231.07:36:30.28#ibcon#flushed, iclass 24, count 0 2006.231.07:36:30.28#ibcon#about to write, iclass 24, count 0 2006.231.07:36:30.28#ibcon#wrote, iclass 24, count 0 2006.231.07:36:30.28#ibcon#about to read 3, iclass 24, count 0 2006.231.07:36:30.32#ibcon#read 3, iclass 24, count 0 2006.231.07:36:30.32#ibcon#about to read 4, iclass 24, count 0 2006.231.07:36:30.32#ibcon#read 4, iclass 24, count 0 2006.231.07:36:30.32#ibcon#about to read 5, iclass 24, count 0 2006.231.07:36:30.32#ibcon#read 5, iclass 24, count 0 2006.231.07:36:30.32#ibcon#about to read 6, iclass 24, count 0 2006.231.07:36:30.32#ibcon#read 6, iclass 24, count 0 2006.231.07:36:30.32#ibcon#end of sib2, iclass 24, count 0 2006.231.07:36:30.32#ibcon#*after write, iclass 24, count 0 2006.231.07:36:30.32#ibcon#*before return 0, iclass 24, count 0 2006.231.07:36:30.32#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:36:30.32#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:36:30.32#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:36:30.32#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:36:30.32$vc4f8/va=8,6 2006.231.07:36:30.32#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.231.07:36:30.32#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.231.07:36:30.32#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:30.32#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:36:30.38#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:36:30.38#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:36:30.38#ibcon#enter wrdev, iclass 26, count 2 2006.231.07:36:30.38#ibcon#first serial, iclass 26, count 2 2006.231.07:36:30.38#ibcon#enter sib2, iclass 26, count 2 2006.231.07:36:30.38#ibcon#flushed, iclass 26, count 2 2006.231.07:36:30.38#ibcon#about to write, iclass 26, count 2 2006.231.07:36:30.38#ibcon#wrote, iclass 26, count 2 2006.231.07:36:30.38#ibcon#about to read 3, iclass 26, count 2 2006.231.07:36:30.41#ibcon#read 3, iclass 26, count 2 2006.231.07:36:30.41#ibcon#about to read 4, iclass 26, count 2 2006.231.07:36:30.41#ibcon#read 4, iclass 26, count 2 2006.231.07:36:30.41#ibcon#about to read 5, iclass 26, count 2 2006.231.07:36:30.41#ibcon#read 5, iclass 26, count 2 2006.231.07:36:30.41#ibcon#about to read 6, iclass 26, count 2 2006.231.07:36:30.41#ibcon#read 6, iclass 26, count 2 2006.231.07:36:30.41#ibcon#end of sib2, iclass 26, count 2 2006.231.07:36:30.41#ibcon#*mode == 0, iclass 26, count 2 2006.231.07:36:30.41#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.231.07:36:30.41#ibcon#[25=AT08-06\r\n] 2006.231.07:36:30.41#ibcon#*before write, iclass 26, count 2 2006.231.07:36:30.41#ibcon#enter sib2, iclass 26, count 2 2006.231.07:36:30.41#ibcon#flushed, iclass 26, count 2 2006.231.07:36:30.41#ibcon#about to write, iclass 26, count 2 2006.231.07:36:30.41#ibcon#wrote, iclass 26, count 2 2006.231.07:36:30.41#ibcon#about to read 3, iclass 26, count 2 2006.231.07:36:30.44#ibcon#read 3, iclass 26, count 2 2006.231.07:36:30.44#ibcon#about to read 4, iclass 26, count 2 2006.231.07:36:30.44#ibcon#read 4, iclass 26, count 2 2006.231.07:36:30.44#ibcon#about to read 5, iclass 26, count 2 2006.231.07:36:30.44#ibcon#read 5, iclass 26, count 2 2006.231.07:36:30.44#ibcon#about to read 6, iclass 26, count 2 2006.231.07:36:30.44#ibcon#read 6, iclass 26, count 2 2006.231.07:36:30.44#ibcon#end of sib2, iclass 26, count 2 2006.231.07:36:30.44#ibcon#*after write, iclass 26, count 2 2006.231.07:36:30.44#ibcon#*before return 0, iclass 26, count 2 2006.231.07:36:30.44#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:36:30.44#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:36:30.44#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.231.07:36:30.44#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:30.44#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:36:30.56#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:36:30.56#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:36:30.56#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:36:30.56#ibcon#first serial, iclass 26, count 0 2006.231.07:36:30.56#ibcon#enter sib2, iclass 26, count 0 2006.231.07:36:30.56#ibcon#flushed, iclass 26, count 0 2006.231.07:36:30.56#ibcon#about to write, iclass 26, count 0 2006.231.07:36:30.56#ibcon#wrote, iclass 26, count 0 2006.231.07:36:30.56#ibcon#about to read 3, iclass 26, count 0 2006.231.07:36:30.58#ibcon#read 3, iclass 26, count 0 2006.231.07:36:30.58#ibcon#about to read 4, iclass 26, count 0 2006.231.07:36:30.58#ibcon#read 4, iclass 26, count 0 2006.231.07:36:30.58#ibcon#about to read 5, iclass 26, count 0 2006.231.07:36:30.58#ibcon#read 5, iclass 26, count 0 2006.231.07:36:30.58#ibcon#about to read 6, iclass 26, count 0 2006.231.07:36:30.58#ibcon#read 6, iclass 26, count 0 2006.231.07:36:30.58#ibcon#end of sib2, iclass 26, count 0 2006.231.07:36:30.58#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:36:30.58#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:36:30.58#ibcon#[25=USB\r\n] 2006.231.07:36:30.58#ibcon#*before write, iclass 26, count 0 2006.231.07:36:30.58#ibcon#enter sib2, iclass 26, count 0 2006.231.07:36:30.58#ibcon#flushed, iclass 26, count 0 2006.231.07:36:30.58#ibcon#about to write, iclass 26, count 0 2006.231.07:36:30.58#ibcon#wrote, iclass 26, count 0 2006.231.07:36:30.58#ibcon#about to read 3, iclass 26, count 0 2006.231.07:36:30.61#ibcon#read 3, iclass 26, count 0 2006.231.07:36:30.61#ibcon#about to read 4, iclass 26, count 0 2006.231.07:36:30.61#ibcon#read 4, iclass 26, count 0 2006.231.07:36:30.61#ibcon#about to read 5, iclass 26, count 0 2006.231.07:36:30.61#ibcon#read 5, iclass 26, count 0 2006.231.07:36:30.61#ibcon#about to read 6, iclass 26, count 0 2006.231.07:36:30.61#ibcon#read 6, iclass 26, count 0 2006.231.07:36:30.61#ibcon#end of sib2, iclass 26, count 0 2006.231.07:36:30.61#ibcon#*after write, iclass 26, count 0 2006.231.07:36:30.61#ibcon#*before return 0, iclass 26, count 0 2006.231.07:36:30.61#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:36:30.61#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:36:30.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:36:30.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:36:30.61$vc4f8/vblo=1,632.99 2006.231.07:36:30.61#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.231.07:36:30.61#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.231.07:36:30.61#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:30.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:36:30.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:36:30.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:36:30.61#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:36:30.61#ibcon#first serial, iclass 28, count 0 2006.231.07:36:30.61#ibcon#enter sib2, iclass 28, count 0 2006.231.07:36:30.61#ibcon#flushed, iclass 28, count 0 2006.231.07:36:30.61#ibcon#about to write, iclass 28, count 0 2006.231.07:36:30.61#ibcon#wrote, iclass 28, count 0 2006.231.07:36:30.61#ibcon#about to read 3, iclass 28, count 0 2006.231.07:36:30.63#ibcon#read 3, iclass 28, count 0 2006.231.07:36:30.63#ibcon#about to read 4, iclass 28, count 0 2006.231.07:36:30.63#ibcon#read 4, iclass 28, count 0 2006.231.07:36:30.63#ibcon#about to read 5, iclass 28, count 0 2006.231.07:36:30.63#ibcon#read 5, iclass 28, count 0 2006.231.07:36:30.63#ibcon#about to read 6, iclass 28, count 0 2006.231.07:36:30.63#ibcon#read 6, iclass 28, count 0 2006.231.07:36:30.63#ibcon#end of sib2, iclass 28, count 0 2006.231.07:36:30.63#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:36:30.63#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:36:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:36:30.63#ibcon#*before write, iclass 28, count 0 2006.231.07:36:30.63#ibcon#enter sib2, iclass 28, count 0 2006.231.07:36:30.63#ibcon#flushed, iclass 28, count 0 2006.231.07:36:30.63#ibcon#about to write, iclass 28, count 0 2006.231.07:36:30.63#ibcon#wrote, iclass 28, count 0 2006.231.07:36:30.63#ibcon#about to read 3, iclass 28, count 0 2006.231.07:36:30.67#ibcon#read 3, iclass 28, count 0 2006.231.07:36:30.67#ibcon#about to read 4, iclass 28, count 0 2006.231.07:36:30.67#ibcon#read 4, iclass 28, count 0 2006.231.07:36:30.67#ibcon#about to read 5, iclass 28, count 0 2006.231.07:36:30.67#ibcon#read 5, iclass 28, count 0 2006.231.07:36:30.67#ibcon#about to read 6, iclass 28, count 0 2006.231.07:36:30.67#ibcon#read 6, iclass 28, count 0 2006.231.07:36:30.67#ibcon#end of sib2, iclass 28, count 0 2006.231.07:36:30.67#ibcon#*after write, iclass 28, count 0 2006.231.07:36:30.67#ibcon#*before return 0, iclass 28, count 0 2006.231.07:36:30.67#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:36:30.67#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:36:30.67#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:36:30.67#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:36:30.67$vc4f8/vb=1,4 2006.231.07:36:30.67#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.07:36:30.67#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.07:36:30.67#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:30.67#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:36:30.67#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:36:30.67#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:36:30.67#ibcon#enter wrdev, iclass 30, count 2 2006.231.07:36:30.67#ibcon#first serial, iclass 30, count 2 2006.231.07:36:30.67#ibcon#enter sib2, iclass 30, count 2 2006.231.07:36:30.67#ibcon#flushed, iclass 30, count 2 2006.231.07:36:30.67#ibcon#about to write, iclass 30, count 2 2006.231.07:36:30.67#ibcon#wrote, iclass 30, count 2 2006.231.07:36:30.67#ibcon#about to read 3, iclass 30, count 2 2006.231.07:36:30.69#ibcon#read 3, iclass 30, count 2 2006.231.07:36:30.69#ibcon#about to read 4, iclass 30, count 2 2006.231.07:36:30.69#ibcon#read 4, iclass 30, count 2 2006.231.07:36:30.69#ibcon#about to read 5, iclass 30, count 2 2006.231.07:36:30.69#ibcon#read 5, iclass 30, count 2 2006.231.07:36:30.69#ibcon#about to read 6, iclass 30, count 2 2006.231.07:36:30.69#ibcon#read 6, iclass 30, count 2 2006.231.07:36:30.69#ibcon#end of sib2, iclass 30, count 2 2006.231.07:36:30.69#ibcon#*mode == 0, iclass 30, count 2 2006.231.07:36:30.69#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.07:36:30.69#ibcon#[27=AT01-04\r\n] 2006.231.07:36:30.69#ibcon#*before write, iclass 30, count 2 2006.231.07:36:30.69#ibcon#enter sib2, iclass 30, count 2 2006.231.07:36:30.69#ibcon#flushed, iclass 30, count 2 2006.231.07:36:30.69#ibcon#about to write, iclass 30, count 2 2006.231.07:36:30.69#ibcon#wrote, iclass 30, count 2 2006.231.07:36:30.69#ibcon#about to read 3, iclass 30, count 2 2006.231.07:36:30.72#ibcon#read 3, iclass 30, count 2 2006.231.07:36:30.72#ibcon#about to read 4, iclass 30, count 2 2006.231.07:36:30.72#ibcon#read 4, iclass 30, count 2 2006.231.07:36:30.72#ibcon#about to read 5, iclass 30, count 2 2006.231.07:36:30.72#ibcon#read 5, iclass 30, count 2 2006.231.07:36:30.72#ibcon#about to read 6, iclass 30, count 2 2006.231.07:36:30.72#ibcon#read 6, iclass 30, count 2 2006.231.07:36:30.72#ibcon#end of sib2, iclass 30, count 2 2006.231.07:36:30.72#ibcon#*after write, iclass 30, count 2 2006.231.07:36:30.72#ibcon#*before return 0, iclass 30, count 2 2006.231.07:36:30.72#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:36:30.72#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:36:30.72#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.07:36:30.72#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:30.72#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:36:30.84#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:36:30.84#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:36:30.84#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:36:30.84#ibcon#first serial, iclass 30, count 0 2006.231.07:36:30.84#ibcon#enter sib2, iclass 30, count 0 2006.231.07:36:30.84#ibcon#flushed, iclass 30, count 0 2006.231.07:36:30.84#ibcon#about to write, iclass 30, count 0 2006.231.07:36:30.84#ibcon#wrote, iclass 30, count 0 2006.231.07:36:30.84#ibcon#about to read 3, iclass 30, count 0 2006.231.07:36:30.86#ibcon#read 3, iclass 30, count 0 2006.231.07:36:30.86#ibcon#about to read 4, iclass 30, count 0 2006.231.07:36:30.86#ibcon#read 4, iclass 30, count 0 2006.231.07:36:30.86#ibcon#about to read 5, iclass 30, count 0 2006.231.07:36:30.86#ibcon#read 5, iclass 30, count 0 2006.231.07:36:30.86#ibcon#about to read 6, iclass 30, count 0 2006.231.07:36:30.86#ibcon#read 6, iclass 30, count 0 2006.231.07:36:30.86#ibcon#end of sib2, iclass 30, count 0 2006.231.07:36:30.86#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:36:30.86#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:36:30.86#ibcon#[27=USB\r\n] 2006.231.07:36:30.86#ibcon#*before write, iclass 30, count 0 2006.231.07:36:30.86#ibcon#enter sib2, iclass 30, count 0 2006.231.07:36:30.86#ibcon#flushed, iclass 30, count 0 2006.231.07:36:30.86#ibcon#about to write, iclass 30, count 0 2006.231.07:36:30.86#ibcon#wrote, iclass 30, count 0 2006.231.07:36:30.86#ibcon#about to read 3, iclass 30, count 0 2006.231.07:36:30.89#ibcon#read 3, iclass 30, count 0 2006.231.07:36:30.89#ibcon#about to read 4, iclass 30, count 0 2006.231.07:36:30.89#ibcon#read 4, iclass 30, count 0 2006.231.07:36:30.89#ibcon#about to read 5, iclass 30, count 0 2006.231.07:36:30.89#ibcon#read 5, iclass 30, count 0 2006.231.07:36:30.89#ibcon#about to read 6, iclass 30, count 0 2006.231.07:36:30.89#ibcon#read 6, iclass 30, count 0 2006.231.07:36:30.89#ibcon#end of sib2, iclass 30, count 0 2006.231.07:36:30.89#ibcon#*after write, iclass 30, count 0 2006.231.07:36:30.89#ibcon#*before return 0, iclass 30, count 0 2006.231.07:36:30.89#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:36:30.89#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:36:30.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:36:30.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:36:30.89$vc4f8/vblo=2,640.99 2006.231.07:36:30.89#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.07:36:30.89#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.07:36:30.89#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:30.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:36:30.89#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:36:30.89#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:36:30.89#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:36:30.89#ibcon#first serial, iclass 32, count 0 2006.231.07:36:30.89#ibcon#enter sib2, iclass 32, count 0 2006.231.07:36:30.89#ibcon#flushed, iclass 32, count 0 2006.231.07:36:30.89#ibcon#about to write, iclass 32, count 0 2006.231.07:36:30.89#ibcon#wrote, iclass 32, count 0 2006.231.07:36:30.89#ibcon#about to read 3, iclass 32, count 0 2006.231.07:36:30.91#ibcon#read 3, iclass 32, count 0 2006.231.07:36:30.91#ibcon#about to read 4, iclass 32, count 0 2006.231.07:36:30.91#ibcon#read 4, iclass 32, count 0 2006.231.07:36:30.91#ibcon#about to read 5, iclass 32, count 0 2006.231.07:36:30.91#ibcon#read 5, iclass 32, count 0 2006.231.07:36:30.91#ibcon#about to read 6, iclass 32, count 0 2006.231.07:36:30.91#ibcon#read 6, iclass 32, count 0 2006.231.07:36:30.91#ibcon#end of sib2, iclass 32, count 0 2006.231.07:36:30.91#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:36:30.91#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:36:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:36:30.91#ibcon#*before write, iclass 32, count 0 2006.231.07:36:30.91#ibcon#enter sib2, iclass 32, count 0 2006.231.07:36:30.91#ibcon#flushed, iclass 32, count 0 2006.231.07:36:30.91#ibcon#about to write, iclass 32, count 0 2006.231.07:36:30.91#ibcon#wrote, iclass 32, count 0 2006.231.07:36:30.91#ibcon#about to read 3, iclass 32, count 0 2006.231.07:36:30.95#ibcon#read 3, iclass 32, count 0 2006.231.07:36:30.95#ibcon#about to read 4, iclass 32, count 0 2006.231.07:36:30.95#ibcon#read 4, iclass 32, count 0 2006.231.07:36:30.95#ibcon#about to read 5, iclass 32, count 0 2006.231.07:36:30.95#ibcon#read 5, iclass 32, count 0 2006.231.07:36:30.95#ibcon#about to read 6, iclass 32, count 0 2006.231.07:36:30.95#ibcon#read 6, iclass 32, count 0 2006.231.07:36:30.95#ibcon#end of sib2, iclass 32, count 0 2006.231.07:36:30.95#ibcon#*after write, iclass 32, count 0 2006.231.07:36:30.95#ibcon#*before return 0, iclass 32, count 0 2006.231.07:36:30.95#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:36:30.95#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:36:30.95#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:36:30.95#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:36:30.95$vc4f8/vb=2,4 2006.231.07:36:30.95#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.07:36:30.95#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.07:36:30.95#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:30.95#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:36:31.01#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:36:31.01#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:36:31.01#ibcon#enter wrdev, iclass 34, count 2 2006.231.07:36:31.01#ibcon#first serial, iclass 34, count 2 2006.231.07:36:31.01#ibcon#enter sib2, iclass 34, count 2 2006.231.07:36:31.01#ibcon#flushed, iclass 34, count 2 2006.231.07:36:31.01#ibcon#about to write, iclass 34, count 2 2006.231.07:36:31.01#ibcon#wrote, iclass 34, count 2 2006.231.07:36:31.01#ibcon#about to read 3, iclass 34, count 2 2006.231.07:36:31.03#ibcon#read 3, iclass 34, count 2 2006.231.07:36:31.03#ibcon#about to read 4, iclass 34, count 2 2006.231.07:36:31.03#ibcon#read 4, iclass 34, count 2 2006.231.07:36:31.03#ibcon#about to read 5, iclass 34, count 2 2006.231.07:36:31.03#ibcon#read 5, iclass 34, count 2 2006.231.07:36:31.03#ibcon#about to read 6, iclass 34, count 2 2006.231.07:36:31.03#ibcon#read 6, iclass 34, count 2 2006.231.07:36:31.03#ibcon#end of sib2, iclass 34, count 2 2006.231.07:36:31.03#ibcon#*mode == 0, iclass 34, count 2 2006.231.07:36:31.03#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.07:36:31.03#ibcon#[27=AT02-04\r\n] 2006.231.07:36:31.03#ibcon#*before write, iclass 34, count 2 2006.231.07:36:31.03#ibcon#enter sib2, iclass 34, count 2 2006.231.07:36:31.03#ibcon#flushed, iclass 34, count 2 2006.231.07:36:31.03#ibcon#about to write, iclass 34, count 2 2006.231.07:36:31.03#ibcon#wrote, iclass 34, count 2 2006.231.07:36:31.03#ibcon#about to read 3, iclass 34, count 2 2006.231.07:36:31.06#ibcon#read 3, iclass 34, count 2 2006.231.07:36:31.06#ibcon#about to read 4, iclass 34, count 2 2006.231.07:36:31.06#ibcon#read 4, iclass 34, count 2 2006.231.07:36:31.06#ibcon#about to read 5, iclass 34, count 2 2006.231.07:36:31.06#ibcon#read 5, iclass 34, count 2 2006.231.07:36:31.06#ibcon#about to read 6, iclass 34, count 2 2006.231.07:36:31.06#ibcon#read 6, iclass 34, count 2 2006.231.07:36:31.06#ibcon#end of sib2, iclass 34, count 2 2006.231.07:36:31.06#ibcon#*after write, iclass 34, count 2 2006.231.07:36:31.06#ibcon#*before return 0, iclass 34, count 2 2006.231.07:36:31.06#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:36:31.06#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:36:31.06#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.07:36:31.06#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:31.06#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:36:31.18#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:36:31.18#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:36:31.18#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:36:31.18#ibcon#first serial, iclass 34, count 0 2006.231.07:36:31.18#ibcon#enter sib2, iclass 34, count 0 2006.231.07:36:31.18#ibcon#flushed, iclass 34, count 0 2006.231.07:36:31.18#ibcon#about to write, iclass 34, count 0 2006.231.07:36:31.18#ibcon#wrote, iclass 34, count 0 2006.231.07:36:31.18#ibcon#about to read 3, iclass 34, count 0 2006.231.07:36:31.20#ibcon#read 3, iclass 34, count 0 2006.231.07:36:31.20#ibcon#about to read 4, iclass 34, count 0 2006.231.07:36:31.20#ibcon#read 4, iclass 34, count 0 2006.231.07:36:31.20#ibcon#about to read 5, iclass 34, count 0 2006.231.07:36:31.20#ibcon#read 5, iclass 34, count 0 2006.231.07:36:31.20#ibcon#about to read 6, iclass 34, count 0 2006.231.07:36:31.20#ibcon#read 6, iclass 34, count 0 2006.231.07:36:31.20#ibcon#end of sib2, iclass 34, count 0 2006.231.07:36:31.20#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:36:31.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:36:31.20#ibcon#[27=USB\r\n] 2006.231.07:36:31.20#ibcon#*before write, iclass 34, count 0 2006.231.07:36:31.20#ibcon#enter sib2, iclass 34, count 0 2006.231.07:36:31.20#ibcon#flushed, iclass 34, count 0 2006.231.07:36:31.20#ibcon#about to write, iclass 34, count 0 2006.231.07:36:31.20#ibcon#wrote, iclass 34, count 0 2006.231.07:36:31.20#ibcon#about to read 3, iclass 34, count 0 2006.231.07:36:31.23#ibcon#read 3, iclass 34, count 0 2006.231.07:36:31.23#ibcon#about to read 4, iclass 34, count 0 2006.231.07:36:31.23#ibcon#read 4, iclass 34, count 0 2006.231.07:36:31.23#ibcon#about to read 5, iclass 34, count 0 2006.231.07:36:31.23#ibcon#read 5, iclass 34, count 0 2006.231.07:36:31.23#ibcon#about to read 6, iclass 34, count 0 2006.231.07:36:31.23#ibcon#read 6, iclass 34, count 0 2006.231.07:36:31.23#ibcon#end of sib2, iclass 34, count 0 2006.231.07:36:31.23#ibcon#*after write, iclass 34, count 0 2006.231.07:36:31.23#ibcon#*before return 0, iclass 34, count 0 2006.231.07:36:31.23#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:36:31.23#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:36:31.23#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:36:31.23#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:36:31.23$vc4f8/vblo=3,656.99 2006.231.07:36:31.23#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.07:36:31.23#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.07:36:31.23#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:31.23#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:36:31.23#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:36:31.23#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:36:31.23#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:36:31.23#ibcon#first serial, iclass 36, count 0 2006.231.07:36:31.23#ibcon#enter sib2, iclass 36, count 0 2006.231.07:36:31.23#ibcon#flushed, iclass 36, count 0 2006.231.07:36:31.23#ibcon#about to write, iclass 36, count 0 2006.231.07:36:31.23#ibcon#wrote, iclass 36, count 0 2006.231.07:36:31.23#ibcon#about to read 3, iclass 36, count 0 2006.231.07:36:31.25#ibcon#read 3, iclass 36, count 0 2006.231.07:36:31.25#ibcon#about to read 4, iclass 36, count 0 2006.231.07:36:31.25#ibcon#read 4, iclass 36, count 0 2006.231.07:36:31.25#ibcon#about to read 5, iclass 36, count 0 2006.231.07:36:31.25#ibcon#read 5, iclass 36, count 0 2006.231.07:36:31.25#ibcon#about to read 6, iclass 36, count 0 2006.231.07:36:31.25#ibcon#read 6, iclass 36, count 0 2006.231.07:36:31.25#ibcon#end of sib2, iclass 36, count 0 2006.231.07:36:31.25#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:36:31.25#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:36:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:36:31.25#ibcon#*before write, iclass 36, count 0 2006.231.07:36:31.25#ibcon#enter sib2, iclass 36, count 0 2006.231.07:36:31.25#ibcon#flushed, iclass 36, count 0 2006.231.07:36:31.25#ibcon#about to write, iclass 36, count 0 2006.231.07:36:31.25#ibcon#wrote, iclass 36, count 0 2006.231.07:36:31.25#ibcon#about to read 3, iclass 36, count 0 2006.231.07:36:31.29#ibcon#read 3, iclass 36, count 0 2006.231.07:36:31.29#ibcon#about to read 4, iclass 36, count 0 2006.231.07:36:31.29#ibcon#read 4, iclass 36, count 0 2006.231.07:36:31.29#ibcon#about to read 5, iclass 36, count 0 2006.231.07:36:31.29#ibcon#read 5, iclass 36, count 0 2006.231.07:36:31.29#ibcon#about to read 6, iclass 36, count 0 2006.231.07:36:31.29#ibcon#read 6, iclass 36, count 0 2006.231.07:36:31.29#ibcon#end of sib2, iclass 36, count 0 2006.231.07:36:31.29#ibcon#*after write, iclass 36, count 0 2006.231.07:36:31.29#ibcon#*before return 0, iclass 36, count 0 2006.231.07:36:31.29#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:36:31.29#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:36:31.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:36:31.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:36:31.29$vc4f8/vb=3,4 2006.231.07:36:31.29#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.07:36:31.29#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.07:36:31.29#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:31.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:36:31.35#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:36:31.35#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:36:31.35#ibcon#enter wrdev, iclass 38, count 2 2006.231.07:36:31.35#ibcon#first serial, iclass 38, count 2 2006.231.07:36:31.35#ibcon#enter sib2, iclass 38, count 2 2006.231.07:36:31.35#ibcon#flushed, iclass 38, count 2 2006.231.07:36:31.35#ibcon#about to write, iclass 38, count 2 2006.231.07:36:31.35#ibcon#wrote, iclass 38, count 2 2006.231.07:36:31.35#ibcon#about to read 3, iclass 38, count 2 2006.231.07:36:31.37#ibcon#read 3, iclass 38, count 2 2006.231.07:36:31.37#ibcon#about to read 4, iclass 38, count 2 2006.231.07:36:31.37#ibcon#read 4, iclass 38, count 2 2006.231.07:36:31.37#ibcon#about to read 5, iclass 38, count 2 2006.231.07:36:31.37#ibcon#read 5, iclass 38, count 2 2006.231.07:36:31.37#ibcon#about to read 6, iclass 38, count 2 2006.231.07:36:31.37#ibcon#read 6, iclass 38, count 2 2006.231.07:36:31.37#ibcon#end of sib2, iclass 38, count 2 2006.231.07:36:31.37#ibcon#*mode == 0, iclass 38, count 2 2006.231.07:36:31.37#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.07:36:31.37#ibcon#[27=AT03-04\r\n] 2006.231.07:36:31.37#ibcon#*before write, iclass 38, count 2 2006.231.07:36:31.37#ibcon#enter sib2, iclass 38, count 2 2006.231.07:36:31.37#ibcon#flushed, iclass 38, count 2 2006.231.07:36:31.37#ibcon#about to write, iclass 38, count 2 2006.231.07:36:31.37#ibcon#wrote, iclass 38, count 2 2006.231.07:36:31.37#ibcon#about to read 3, iclass 38, count 2 2006.231.07:36:31.40#ibcon#read 3, iclass 38, count 2 2006.231.07:36:31.40#ibcon#about to read 4, iclass 38, count 2 2006.231.07:36:31.40#ibcon#read 4, iclass 38, count 2 2006.231.07:36:31.40#ibcon#about to read 5, iclass 38, count 2 2006.231.07:36:31.40#ibcon#read 5, iclass 38, count 2 2006.231.07:36:31.40#ibcon#about to read 6, iclass 38, count 2 2006.231.07:36:31.40#ibcon#read 6, iclass 38, count 2 2006.231.07:36:31.40#ibcon#end of sib2, iclass 38, count 2 2006.231.07:36:31.40#ibcon#*after write, iclass 38, count 2 2006.231.07:36:31.40#ibcon#*before return 0, iclass 38, count 2 2006.231.07:36:31.40#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:36:31.40#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:36:31.40#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.07:36:31.40#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:31.40#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:36:31.52#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:36:31.52#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:36:31.52#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:36:31.52#ibcon#first serial, iclass 38, count 0 2006.231.07:36:31.52#ibcon#enter sib2, iclass 38, count 0 2006.231.07:36:31.52#ibcon#flushed, iclass 38, count 0 2006.231.07:36:31.52#ibcon#about to write, iclass 38, count 0 2006.231.07:36:31.52#ibcon#wrote, iclass 38, count 0 2006.231.07:36:31.52#ibcon#about to read 3, iclass 38, count 0 2006.231.07:36:31.54#ibcon#read 3, iclass 38, count 0 2006.231.07:36:31.54#ibcon#about to read 4, iclass 38, count 0 2006.231.07:36:31.54#ibcon#read 4, iclass 38, count 0 2006.231.07:36:31.54#ibcon#about to read 5, iclass 38, count 0 2006.231.07:36:31.54#ibcon#read 5, iclass 38, count 0 2006.231.07:36:31.54#ibcon#about to read 6, iclass 38, count 0 2006.231.07:36:31.54#ibcon#read 6, iclass 38, count 0 2006.231.07:36:31.54#ibcon#end of sib2, iclass 38, count 0 2006.231.07:36:31.54#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:36:31.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:36:31.54#ibcon#[27=USB\r\n] 2006.231.07:36:31.54#ibcon#*before write, iclass 38, count 0 2006.231.07:36:31.54#ibcon#enter sib2, iclass 38, count 0 2006.231.07:36:31.54#ibcon#flushed, iclass 38, count 0 2006.231.07:36:31.54#ibcon#about to write, iclass 38, count 0 2006.231.07:36:31.54#ibcon#wrote, iclass 38, count 0 2006.231.07:36:31.54#ibcon#about to read 3, iclass 38, count 0 2006.231.07:36:31.57#ibcon#read 3, iclass 38, count 0 2006.231.07:36:31.57#ibcon#about to read 4, iclass 38, count 0 2006.231.07:36:31.57#ibcon#read 4, iclass 38, count 0 2006.231.07:36:31.57#ibcon#about to read 5, iclass 38, count 0 2006.231.07:36:31.57#ibcon#read 5, iclass 38, count 0 2006.231.07:36:31.57#ibcon#about to read 6, iclass 38, count 0 2006.231.07:36:31.57#ibcon#read 6, iclass 38, count 0 2006.231.07:36:31.57#ibcon#end of sib2, iclass 38, count 0 2006.231.07:36:31.57#ibcon#*after write, iclass 38, count 0 2006.231.07:36:31.57#ibcon#*before return 0, iclass 38, count 0 2006.231.07:36:31.57#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:36:31.57#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:36:31.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:36:31.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:36:31.57$vc4f8/vblo=4,712.99 2006.231.07:36:31.57#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.07:36:31.57#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.07:36:31.57#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:31.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:36:31.57#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:36:31.57#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:36:31.57#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:36:31.57#ibcon#first serial, iclass 40, count 0 2006.231.07:36:31.57#ibcon#enter sib2, iclass 40, count 0 2006.231.07:36:31.57#ibcon#flushed, iclass 40, count 0 2006.231.07:36:31.57#ibcon#about to write, iclass 40, count 0 2006.231.07:36:31.57#ibcon#wrote, iclass 40, count 0 2006.231.07:36:31.57#ibcon#about to read 3, iclass 40, count 0 2006.231.07:36:31.59#ibcon#read 3, iclass 40, count 0 2006.231.07:36:31.59#ibcon#about to read 4, iclass 40, count 0 2006.231.07:36:31.59#ibcon#read 4, iclass 40, count 0 2006.231.07:36:31.59#ibcon#about to read 5, iclass 40, count 0 2006.231.07:36:31.59#ibcon#read 5, iclass 40, count 0 2006.231.07:36:31.59#ibcon#about to read 6, iclass 40, count 0 2006.231.07:36:31.59#ibcon#read 6, iclass 40, count 0 2006.231.07:36:31.59#ibcon#end of sib2, iclass 40, count 0 2006.231.07:36:31.59#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:36:31.59#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:36:31.59#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:36:31.59#ibcon#*before write, iclass 40, count 0 2006.231.07:36:31.59#ibcon#enter sib2, iclass 40, count 0 2006.231.07:36:31.59#ibcon#flushed, iclass 40, count 0 2006.231.07:36:31.59#ibcon#about to write, iclass 40, count 0 2006.231.07:36:31.59#ibcon#wrote, iclass 40, count 0 2006.231.07:36:31.59#ibcon#about to read 3, iclass 40, count 0 2006.231.07:36:31.63#ibcon#read 3, iclass 40, count 0 2006.231.07:36:31.63#ibcon#about to read 4, iclass 40, count 0 2006.231.07:36:31.63#ibcon#read 4, iclass 40, count 0 2006.231.07:36:31.63#ibcon#about to read 5, iclass 40, count 0 2006.231.07:36:31.63#ibcon#read 5, iclass 40, count 0 2006.231.07:36:31.63#ibcon#about to read 6, iclass 40, count 0 2006.231.07:36:31.63#ibcon#read 6, iclass 40, count 0 2006.231.07:36:31.63#ibcon#end of sib2, iclass 40, count 0 2006.231.07:36:31.63#ibcon#*after write, iclass 40, count 0 2006.231.07:36:31.63#ibcon#*before return 0, iclass 40, count 0 2006.231.07:36:31.63#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:36:31.63#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:36:31.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:36:31.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:36:31.63$vc4f8/vb=4,4 2006.231.07:36:31.63#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.231.07:36:31.63#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.231.07:36:31.63#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:31.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:36:31.69#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:36:31.69#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:36:31.69#ibcon#enter wrdev, iclass 4, count 2 2006.231.07:36:31.69#ibcon#first serial, iclass 4, count 2 2006.231.07:36:31.69#ibcon#enter sib2, iclass 4, count 2 2006.231.07:36:31.69#ibcon#flushed, iclass 4, count 2 2006.231.07:36:31.69#ibcon#about to write, iclass 4, count 2 2006.231.07:36:31.69#ibcon#wrote, iclass 4, count 2 2006.231.07:36:31.69#ibcon#about to read 3, iclass 4, count 2 2006.231.07:36:31.71#ibcon#read 3, iclass 4, count 2 2006.231.07:36:31.71#ibcon#about to read 4, iclass 4, count 2 2006.231.07:36:31.71#ibcon#read 4, iclass 4, count 2 2006.231.07:36:31.71#ibcon#about to read 5, iclass 4, count 2 2006.231.07:36:31.71#ibcon#read 5, iclass 4, count 2 2006.231.07:36:31.71#ibcon#about to read 6, iclass 4, count 2 2006.231.07:36:31.71#ibcon#read 6, iclass 4, count 2 2006.231.07:36:31.71#ibcon#end of sib2, iclass 4, count 2 2006.231.07:36:31.71#ibcon#*mode == 0, iclass 4, count 2 2006.231.07:36:31.71#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.231.07:36:31.71#ibcon#[27=AT04-04\r\n] 2006.231.07:36:31.71#ibcon#*before write, iclass 4, count 2 2006.231.07:36:31.71#ibcon#enter sib2, iclass 4, count 2 2006.231.07:36:31.71#ibcon#flushed, iclass 4, count 2 2006.231.07:36:31.71#ibcon#about to write, iclass 4, count 2 2006.231.07:36:31.71#ibcon#wrote, iclass 4, count 2 2006.231.07:36:31.71#ibcon#about to read 3, iclass 4, count 2 2006.231.07:36:31.74#ibcon#read 3, iclass 4, count 2 2006.231.07:36:31.74#ibcon#about to read 4, iclass 4, count 2 2006.231.07:36:31.74#ibcon#read 4, iclass 4, count 2 2006.231.07:36:31.74#ibcon#about to read 5, iclass 4, count 2 2006.231.07:36:31.74#ibcon#read 5, iclass 4, count 2 2006.231.07:36:31.74#ibcon#about to read 6, iclass 4, count 2 2006.231.07:36:31.74#ibcon#read 6, iclass 4, count 2 2006.231.07:36:31.74#ibcon#end of sib2, iclass 4, count 2 2006.231.07:36:31.74#ibcon#*after write, iclass 4, count 2 2006.231.07:36:31.74#ibcon#*before return 0, iclass 4, count 2 2006.231.07:36:31.74#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:36:31.74#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:36:31.74#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.231.07:36:31.74#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:31.74#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:36:31.86#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:36:31.86#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:36:31.86#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:36:31.86#ibcon#first serial, iclass 4, count 0 2006.231.07:36:31.86#ibcon#enter sib2, iclass 4, count 0 2006.231.07:36:31.86#ibcon#flushed, iclass 4, count 0 2006.231.07:36:31.86#ibcon#about to write, iclass 4, count 0 2006.231.07:36:31.86#ibcon#wrote, iclass 4, count 0 2006.231.07:36:31.86#ibcon#about to read 3, iclass 4, count 0 2006.231.07:36:31.88#ibcon#read 3, iclass 4, count 0 2006.231.07:36:31.88#ibcon#about to read 4, iclass 4, count 0 2006.231.07:36:31.88#ibcon#read 4, iclass 4, count 0 2006.231.07:36:31.88#ibcon#about to read 5, iclass 4, count 0 2006.231.07:36:31.88#ibcon#read 5, iclass 4, count 0 2006.231.07:36:31.88#ibcon#about to read 6, iclass 4, count 0 2006.231.07:36:31.88#ibcon#read 6, iclass 4, count 0 2006.231.07:36:31.88#ibcon#end of sib2, iclass 4, count 0 2006.231.07:36:31.88#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:36:31.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:36:31.88#ibcon#[27=USB\r\n] 2006.231.07:36:31.88#ibcon#*before write, iclass 4, count 0 2006.231.07:36:31.88#ibcon#enter sib2, iclass 4, count 0 2006.231.07:36:31.88#ibcon#flushed, iclass 4, count 0 2006.231.07:36:31.88#ibcon#about to write, iclass 4, count 0 2006.231.07:36:31.88#ibcon#wrote, iclass 4, count 0 2006.231.07:36:31.88#ibcon#about to read 3, iclass 4, count 0 2006.231.07:36:31.91#ibcon#read 3, iclass 4, count 0 2006.231.07:36:31.91#ibcon#about to read 4, iclass 4, count 0 2006.231.07:36:31.91#ibcon#read 4, iclass 4, count 0 2006.231.07:36:31.91#ibcon#about to read 5, iclass 4, count 0 2006.231.07:36:31.91#ibcon#read 5, iclass 4, count 0 2006.231.07:36:31.91#ibcon#about to read 6, iclass 4, count 0 2006.231.07:36:31.91#ibcon#read 6, iclass 4, count 0 2006.231.07:36:31.91#ibcon#end of sib2, iclass 4, count 0 2006.231.07:36:31.91#ibcon#*after write, iclass 4, count 0 2006.231.07:36:31.91#ibcon#*before return 0, iclass 4, count 0 2006.231.07:36:31.91#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:36:31.91#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:36:31.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:36:31.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:36:31.91$vc4f8/vblo=5,744.99 2006.231.07:36:31.91#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.231.07:36:31.91#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.231.07:36:31.91#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:31.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:36:31.91#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:36:31.91#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:36:31.91#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:36:31.91#ibcon#first serial, iclass 6, count 0 2006.231.07:36:31.91#ibcon#enter sib2, iclass 6, count 0 2006.231.07:36:31.91#ibcon#flushed, iclass 6, count 0 2006.231.07:36:31.91#ibcon#about to write, iclass 6, count 0 2006.231.07:36:31.91#ibcon#wrote, iclass 6, count 0 2006.231.07:36:31.91#ibcon#about to read 3, iclass 6, count 0 2006.231.07:36:31.93#ibcon#read 3, iclass 6, count 0 2006.231.07:36:31.93#ibcon#about to read 4, iclass 6, count 0 2006.231.07:36:31.93#ibcon#read 4, iclass 6, count 0 2006.231.07:36:31.93#ibcon#about to read 5, iclass 6, count 0 2006.231.07:36:31.93#ibcon#read 5, iclass 6, count 0 2006.231.07:36:31.93#ibcon#about to read 6, iclass 6, count 0 2006.231.07:36:31.93#ibcon#read 6, iclass 6, count 0 2006.231.07:36:31.93#ibcon#end of sib2, iclass 6, count 0 2006.231.07:36:31.93#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:36:31.93#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:36:31.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:36:31.93#ibcon#*before write, iclass 6, count 0 2006.231.07:36:31.93#ibcon#enter sib2, iclass 6, count 0 2006.231.07:36:31.93#ibcon#flushed, iclass 6, count 0 2006.231.07:36:31.93#ibcon#about to write, iclass 6, count 0 2006.231.07:36:31.93#ibcon#wrote, iclass 6, count 0 2006.231.07:36:31.93#ibcon#about to read 3, iclass 6, count 0 2006.231.07:36:31.97#ibcon#read 3, iclass 6, count 0 2006.231.07:36:31.97#ibcon#about to read 4, iclass 6, count 0 2006.231.07:36:31.97#ibcon#read 4, iclass 6, count 0 2006.231.07:36:31.97#ibcon#about to read 5, iclass 6, count 0 2006.231.07:36:31.97#ibcon#read 5, iclass 6, count 0 2006.231.07:36:31.97#ibcon#about to read 6, iclass 6, count 0 2006.231.07:36:31.97#ibcon#read 6, iclass 6, count 0 2006.231.07:36:31.97#ibcon#end of sib2, iclass 6, count 0 2006.231.07:36:31.97#ibcon#*after write, iclass 6, count 0 2006.231.07:36:31.97#ibcon#*before return 0, iclass 6, count 0 2006.231.07:36:31.97#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:36:31.97#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:36:31.97#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:36:31.97#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:36:31.97$vc4f8/vb=5,3 2006.231.07:36:31.97#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.231.07:36:31.97#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.231.07:36:31.97#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:31.97#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:36:32.03#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:36:32.03#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:36:32.03#ibcon#enter wrdev, iclass 10, count 2 2006.231.07:36:32.03#ibcon#first serial, iclass 10, count 2 2006.231.07:36:32.03#ibcon#enter sib2, iclass 10, count 2 2006.231.07:36:32.03#ibcon#flushed, iclass 10, count 2 2006.231.07:36:32.03#ibcon#about to write, iclass 10, count 2 2006.231.07:36:32.03#ibcon#wrote, iclass 10, count 2 2006.231.07:36:32.03#ibcon#about to read 3, iclass 10, count 2 2006.231.07:36:32.05#ibcon#read 3, iclass 10, count 2 2006.231.07:36:32.05#ibcon#about to read 4, iclass 10, count 2 2006.231.07:36:32.05#ibcon#read 4, iclass 10, count 2 2006.231.07:36:32.05#ibcon#about to read 5, iclass 10, count 2 2006.231.07:36:32.05#ibcon#read 5, iclass 10, count 2 2006.231.07:36:32.05#ibcon#about to read 6, iclass 10, count 2 2006.231.07:36:32.05#ibcon#read 6, iclass 10, count 2 2006.231.07:36:32.05#ibcon#end of sib2, iclass 10, count 2 2006.231.07:36:32.05#ibcon#*mode == 0, iclass 10, count 2 2006.231.07:36:32.05#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.231.07:36:32.05#ibcon#[27=AT05-03\r\n] 2006.231.07:36:32.05#ibcon#*before write, iclass 10, count 2 2006.231.07:36:32.05#ibcon#enter sib2, iclass 10, count 2 2006.231.07:36:32.05#ibcon#flushed, iclass 10, count 2 2006.231.07:36:32.05#ibcon#about to write, iclass 10, count 2 2006.231.07:36:32.05#ibcon#wrote, iclass 10, count 2 2006.231.07:36:32.05#ibcon#about to read 3, iclass 10, count 2 2006.231.07:36:32.08#ibcon#read 3, iclass 10, count 2 2006.231.07:36:32.08#ibcon#about to read 4, iclass 10, count 2 2006.231.07:36:32.08#ibcon#read 4, iclass 10, count 2 2006.231.07:36:32.08#ibcon#about to read 5, iclass 10, count 2 2006.231.07:36:32.08#ibcon#read 5, iclass 10, count 2 2006.231.07:36:32.08#ibcon#about to read 6, iclass 10, count 2 2006.231.07:36:32.08#ibcon#read 6, iclass 10, count 2 2006.231.07:36:32.08#ibcon#end of sib2, iclass 10, count 2 2006.231.07:36:32.08#ibcon#*after write, iclass 10, count 2 2006.231.07:36:32.08#ibcon#*before return 0, iclass 10, count 2 2006.231.07:36:32.08#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:36:32.08#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:36:32.08#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.231.07:36:32.08#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:32.08#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:36:32.20#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:36:32.20#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:36:32.20#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:36:32.20#ibcon#first serial, iclass 10, count 0 2006.231.07:36:32.20#ibcon#enter sib2, iclass 10, count 0 2006.231.07:36:32.20#ibcon#flushed, iclass 10, count 0 2006.231.07:36:32.20#ibcon#about to write, iclass 10, count 0 2006.231.07:36:32.20#ibcon#wrote, iclass 10, count 0 2006.231.07:36:32.20#ibcon#about to read 3, iclass 10, count 0 2006.231.07:36:32.22#ibcon#read 3, iclass 10, count 0 2006.231.07:36:32.22#ibcon#about to read 4, iclass 10, count 0 2006.231.07:36:32.22#ibcon#read 4, iclass 10, count 0 2006.231.07:36:32.22#ibcon#about to read 5, iclass 10, count 0 2006.231.07:36:32.22#ibcon#read 5, iclass 10, count 0 2006.231.07:36:32.22#ibcon#about to read 6, iclass 10, count 0 2006.231.07:36:32.22#ibcon#read 6, iclass 10, count 0 2006.231.07:36:32.22#ibcon#end of sib2, iclass 10, count 0 2006.231.07:36:32.22#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:36:32.22#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:36:32.22#ibcon#[27=USB\r\n] 2006.231.07:36:32.22#ibcon#*before write, iclass 10, count 0 2006.231.07:36:32.22#ibcon#enter sib2, iclass 10, count 0 2006.231.07:36:32.22#ibcon#flushed, iclass 10, count 0 2006.231.07:36:32.22#ibcon#about to write, iclass 10, count 0 2006.231.07:36:32.22#ibcon#wrote, iclass 10, count 0 2006.231.07:36:32.22#ibcon#about to read 3, iclass 10, count 0 2006.231.07:36:32.25#ibcon#read 3, iclass 10, count 0 2006.231.07:36:32.25#ibcon#about to read 4, iclass 10, count 0 2006.231.07:36:32.25#ibcon#read 4, iclass 10, count 0 2006.231.07:36:32.25#ibcon#about to read 5, iclass 10, count 0 2006.231.07:36:32.25#ibcon#read 5, iclass 10, count 0 2006.231.07:36:32.25#ibcon#about to read 6, iclass 10, count 0 2006.231.07:36:32.25#ibcon#read 6, iclass 10, count 0 2006.231.07:36:32.25#ibcon#end of sib2, iclass 10, count 0 2006.231.07:36:32.25#ibcon#*after write, iclass 10, count 0 2006.231.07:36:32.25#ibcon#*before return 0, iclass 10, count 0 2006.231.07:36:32.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:36:32.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:36:32.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:36:32.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:36:32.25$vc4f8/vblo=6,752.99 2006.231.07:36:32.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.07:36:32.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.07:36:32.25#ibcon#ireg 17 cls_cnt 0 2006.231.07:36:32.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:36:32.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:36:32.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:36:32.25#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:36:32.25#ibcon#first serial, iclass 12, count 0 2006.231.07:36:32.25#ibcon#enter sib2, iclass 12, count 0 2006.231.07:36:32.25#ibcon#flushed, iclass 12, count 0 2006.231.07:36:32.25#ibcon#about to write, iclass 12, count 0 2006.231.07:36:32.25#ibcon#wrote, iclass 12, count 0 2006.231.07:36:32.25#ibcon#about to read 3, iclass 12, count 0 2006.231.07:36:32.27#ibcon#read 3, iclass 12, count 0 2006.231.07:36:32.27#ibcon#about to read 4, iclass 12, count 0 2006.231.07:36:32.27#ibcon#read 4, iclass 12, count 0 2006.231.07:36:32.27#ibcon#about to read 5, iclass 12, count 0 2006.231.07:36:32.27#ibcon#read 5, iclass 12, count 0 2006.231.07:36:32.27#ibcon#about to read 6, iclass 12, count 0 2006.231.07:36:32.27#ibcon#read 6, iclass 12, count 0 2006.231.07:36:32.27#ibcon#end of sib2, iclass 12, count 0 2006.231.07:36:32.27#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:36:32.27#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:36:32.27#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:36:32.27#ibcon#*before write, iclass 12, count 0 2006.231.07:36:32.27#ibcon#enter sib2, iclass 12, count 0 2006.231.07:36:32.27#ibcon#flushed, iclass 12, count 0 2006.231.07:36:32.27#ibcon#about to write, iclass 12, count 0 2006.231.07:36:32.27#ibcon#wrote, iclass 12, count 0 2006.231.07:36:32.27#ibcon#about to read 3, iclass 12, count 0 2006.231.07:36:32.31#ibcon#read 3, iclass 12, count 0 2006.231.07:36:32.31#ibcon#about to read 4, iclass 12, count 0 2006.231.07:36:32.31#ibcon#read 4, iclass 12, count 0 2006.231.07:36:32.31#ibcon#about to read 5, iclass 12, count 0 2006.231.07:36:32.31#ibcon#read 5, iclass 12, count 0 2006.231.07:36:32.31#ibcon#about to read 6, iclass 12, count 0 2006.231.07:36:32.31#ibcon#read 6, iclass 12, count 0 2006.231.07:36:32.31#ibcon#end of sib2, iclass 12, count 0 2006.231.07:36:32.31#ibcon#*after write, iclass 12, count 0 2006.231.07:36:32.31#ibcon#*before return 0, iclass 12, count 0 2006.231.07:36:32.31#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:36:32.31#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:36:32.31#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:36:32.31#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:36:32.31$vc4f8/vb=6,4 2006.231.07:36:32.31#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.07:36:32.31#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.07:36:32.31#ibcon#ireg 11 cls_cnt 2 2006.231.07:36:32.31#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:36:32.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:36:32.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:36:32.37#ibcon#enter wrdev, iclass 14, count 2 2006.231.07:36:32.37#ibcon#first serial, iclass 14, count 2 2006.231.07:36:32.37#ibcon#enter sib2, iclass 14, count 2 2006.231.07:36:32.37#ibcon#flushed, iclass 14, count 2 2006.231.07:36:32.37#ibcon#about to write, iclass 14, count 2 2006.231.07:36:32.37#ibcon#wrote, iclass 14, count 2 2006.231.07:36:32.37#ibcon#about to read 3, iclass 14, count 2 2006.231.07:36:32.39#ibcon#read 3, iclass 14, count 2 2006.231.07:36:32.39#ibcon#about to read 4, iclass 14, count 2 2006.231.07:36:32.39#ibcon#read 4, iclass 14, count 2 2006.231.07:36:32.39#ibcon#about to read 5, iclass 14, count 2 2006.231.07:36:32.39#ibcon#read 5, iclass 14, count 2 2006.231.07:36:32.39#ibcon#about to read 6, iclass 14, count 2 2006.231.07:36:32.39#ibcon#read 6, iclass 14, count 2 2006.231.07:36:32.39#ibcon#end of sib2, iclass 14, count 2 2006.231.07:36:32.39#ibcon#*mode == 0, iclass 14, count 2 2006.231.07:36:32.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.07:36:32.39#ibcon#[27=AT06-04\r\n] 2006.231.07:36:32.39#ibcon#*before write, iclass 14, count 2 2006.231.07:36:32.39#ibcon#enter sib2, iclass 14, count 2 2006.231.07:36:32.39#ibcon#flushed, iclass 14, count 2 2006.231.07:36:32.39#ibcon#about to write, iclass 14, count 2 2006.231.07:36:32.39#ibcon#wrote, iclass 14, count 2 2006.231.07:36:32.39#ibcon#about to read 3, iclass 14, count 2 2006.231.07:36:32.42#ibcon#read 3, iclass 14, count 2 2006.231.07:36:32.42#ibcon#about to read 4, iclass 14, count 2 2006.231.07:36:32.42#ibcon#read 4, iclass 14, count 2 2006.231.07:36:32.42#ibcon#about to read 5, iclass 14, count 2 2006.231.07:36:32.42#ibcon#read 5, iclass 14, count 2 2006.231.07:36:32.42#ibcon#about to read 6, iclass 14, count 2 2006.231.07:36:32.42#ibcon#read 6, iclass 14, count 2 2006.231.07:36:32.42#ibcon#end of sib2, iclass 14, count 2 2006.231.07:36:32.42#ibcon#*after write, iclass 14, count 2 2006.231.07:36:32.42#ibcon#*before return 0, iclass 14, count 2 2006.231.07:36:32.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:36:32.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:36:32.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.07:36:32.42#ibcon#ireg 7 cls_cnt 0 2006.231.07:36:32.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:36:32.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:36:32.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:36:32.54#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:36:32.54#ibcon#first serial, iclass 14, count 0 2006.231.07:36:32.54#ibcon#enter sib2, iclass 14, count 0 2006.231.07:36:32.54#ibcon#flushed, iclass 14, count 0 2006.231.07:36:32.54#ibcon#about to write, iclass 14, count 0 2006.231.07:36:32.54#ibcon#wrote, iclass 14, count 0 2006.231.07:36:32.54#ibcon#about to read 3, iclass 14, count 0 2006.231.07:36:32.56#ibcon#read 3, iclass 14, count 0 2006.231.07:36:32.56#ibcon#about to read 4, iclass 14, count 0 2006.231.07:36:32.56#ibcon#read 4, iclass 14, count 0 2006.231.07:36:32.56#ibcon#about to read 5, iclass 14, count 0 2006.231.07:36:32.56#ibcon#read 5, iclass 14, count 0 2006.231.07:36:32.56#ibcon#about to read 6, iclass 14, count 0 2006.231.07:36:32.56#ibcon#read 6, iclass 14, count 0 2006.231.07:36:32.56#ibcon#end of sib2, iclass 14, count 0 2006.231.07:36:32.56#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:36:32.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:36:32.56#ibcon#[27=USB\r\n] 2006.231.07:36:32.56#ibcon#*before write, iclass 14, count 0 2006.231.07:36:32.56#ibcon#enter sib2, iclass 14, count 0 2006.231.07:36:32.56#ibcon#flushed, iclass 14, count 0 2006.231.07:36:32.56#ibcon#about to write, iclass 14, count 0 2006.231.07:36:32.56#ibcon#wrote, iclass 14, count 0 2006.231.07:36:32.56#ibcon#about to read 3, iclass 14, count 0 2006.231.07:36:32.59#ibcon#read 3, iclass 14, count 0 2006.231.07:36:32.59#ibcon#about to read 4, iclass 14, count 0 2006.231.07:36:32.59#ibcon#read 4, iclass 14, count 0 2006.231.07:36:32.59#ibcon#about to read 5, iclass 14, count 0 2006.231.07:36:32.59#ibcon#read 5, iclass 14, count 0 2006.231.07:36:32.59#ibcon#about to read 6, iclass 14, count 0 2006.231.07:36:32.59#ibcon#read 6, iclass 14, count 0 2006.231.07:36:32.59#ibcon#end of sib2, iclass 14, count 0 2006.231.07:36:32.59#ibcon#*after write, iclass 14, count 0 2006.231.07:36:32.59#ibcon#*before return 0, iclass 14, count 0 2006.231.07:36:32.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:36:32.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:36:32.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:36:32.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:36:32.59$vc4f8/vabw=wide 2006.231.07:36:32.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.07:36:32.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.07:36:32.59#ibcon#ireg 8 cls_cnt 0 2006.231.07:36:32.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:36:32.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:36:32.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:36:32.59#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:36:32.59#ibcon#first serial, iclass 16, count 0 2006.231.07:36:32.59#ibcon#enter sib2, iclass 16, count 0 2006.231.07:36:32.59#ibcon#flushed, iclass 16, count 0 2006.231.07:36:32.59#ibcon#about to write, iclass 16, count 0 2006.231.07:36:32.59#ibcon#wrote, iclass 16, count 0 2006.231.07:36:32.59#ibcon#about to read 3, iclass 16, count 0 2006.231.07:36:32.61#ibcon#read 3, iclass 16, count 0 2006.231.07:36:32.61#ibcon#about to read 4, iclass 16, count 0 2006.231.07:36:32.61#ibcon#read 4, iclass 16, count 0 2006.231.07:36:32.61#ibcon#about to read 5, iclass 16, count 0 2006.231.07:36:32.61#ibcon#read 5, iclass 16, count 0 2006.231.07:36:32.61#ibcon#about to read 6, iclass 16, count 0 2006.231.07:36:32.61#ibcon#read 6, iclass 16, count 0 2006.231.07:36:32.61#ibcon#end of sib2, iclass 16, count 0 2006.231.07:36:32.61#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:36:32.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:36:32.61#ibcon#[25=BW32\r\n] 2006.231.07:36:32.61#ibcon#*before write, iclass 16, count 0 2006.231.07:36:32.61#ibcon#enter sib2, iclass 16, count 0 2006.231.07:36:32.61#ibcon#flushed, iclass 16, count 0 2006.231.07:36:32.61#ibcon#about to write, iclass 16, count 0 2006.231.07:36:32.61#ibcon#wrote, iclass 16, count 0 2006.231.07:36:32.61#ibcon#about to read 3, iclass 16, count 0 2006.231.07:36:32.64#ibcon#read 3, iclass 16, count 0 2006.231.07:36:32.64#ibcon#about to read 4, iclass 16, count 0 2006.231.07:36:32.64#ibcon#read 4, iclass 16, count 0 2006.231.07:36:32.64#ibcon#about to read 5, iclass 16, count 0 2006.231.07:36:32.64#ibcon#read 5, iclass 16, count 0 2006.231.07:36:32.64#ibcon#about to read 6, iclass 16, count 0 2006.231.07:36:32.64#ibcon#read 6, iclass 16, count 0 2006.231.07:36:32.64#ibcon#end of sib2, iclass 16, count 0 2006.231.07:36:32.64#ibcon#*after write, iclass 16, count 0 2006.231.07:36:32.64#ibcon#*before return 0, iclass 16, count 0 2006.231.07:36:32.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:36:32.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:36:32.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:36:32.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:36:32.64$vc4f8/vbbw=wide 2006.231.07:36:32.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.07:36:32.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.07:36:32.64#ibcon#ireg 8 cls_cnt 0 2006.231.07:36:32.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:36:32.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:36:32.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:36:32.71#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:36:32.71#ibcon#first serial, iclass 18, count 0 2006.231.07:36:32.71#ibcon#enter sib2, iclass 18, count 0 2006.231.07:36:32.71#ibcon#flushed, iclass 18, count 0 2006.231.07:36:32.71#ibcon#about to write, iclass 18, count 0 2006.231.07:36:32.71#ibcon#wrote, iclass 18, count 0 2006.231.07:36:32.71#ibcon#about to read 3, iclass 18, count 0 2006.231.07:36:32.74#ibcon#read 3, iclass 18, count 0 2006.231.07:36:32.74#ibcon#about to read 4, iclass 18, count 0 2006.231.07:36:32.74#ibcon#read 4, iclass 18, count 0 2006.231.07:36:32.74#ibcon#about to read 5, iclass 18, count 0 2006.231.07:36:32.74#ibcon#read 5, iclass 18, count 0 2006.231.07:36:32.74#ibcon#about to read 6, iclass 18, count 0 2006.231.07:36:32.74#ibcon#read 6, iclass 18, count 0 2006.231.07:36:32.74#ibcon#end of sib2, iclass 18, count 0 2006.231.07:36:32.74#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:36:32.74#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:36:32.74#ibcon#[27=BW32\r\n] 2006.231.07:36:32.74#ibcon#*before write, iclass 18, count 0 2006.231.07:36:32.74#ibcon#enter sib2, iclass 18, count 0 2006.231.07:36:32.74#ibcon#flushed, iclass 18, count 0 2006.231.07:36:32.74#ibcon#about to write, iclass 18, count 0 2006.231.07:36:32.74#ibcon#wrote, iclass 18, count 0 2006.231.07:36:32.74#ibcon#about to read 3, iclass 18, count 0 2006.231.07:36:32.76#ibcon#read 3, iclass 18, count 0 2006.231.07:36:32.76#ibcon#about to read 4, iclass 18, count 0 2006.231.07:36:32.76#ibcon#read 4, iclass 18, count 0 2006.231.07:36:32.76#ibcon#about to read 5, iclass 18, count 0 2006.231.07:36:32.76#ibcon#read 5, iclass 18, count 0 2006.231.07:36:32.76#ibcon#about to read 6, iclass 18, count 0 2006.231.07:36:32.76#ibcon#read 6, iclass 18, count 0 2006.231.07:36:32.76#ibcon#end of sib2, iclass 18, count 0 2006.231.07:36:32.76#ibcon#*after write, iclass 18, count 0 2006.231.07:36:32.76#ibcon#*before return 0, iclass 18, count 0 2006.231.07:36:32.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:36:32.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:36:32.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:36:32.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:36:32.76$4f8m12a/ifd4f 2006.231.07:36:32.76$ifd4f/lo= 2006.231.07:36:32.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:36:32.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:36:32.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:36:32.76$ifd4f/patch= 2006.231.07:36:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:36:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:36:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:36:32.76$4f8m12a/"form=m,16.000,1:2 2006.231.07:36:32.76$4f8m12a/"tpicd 2006.231.07:36:32.76$4f8m12a/echo=off 2006.231.07:36:32.76$4f8m12a/xlog=off 2006.231.07:36:32.76:!2006.231.07:37:00 2006.231.07:36:43.14#trakl#Source acquired 2006.231.07:36:44.14#flagr#flagr/antenna,acquired 2006.231.07:37:00.00:preob 2006.231.07:37:00.14/onsource/TRACKING 2006.231.07:37:00.14:!2006.231.07:37:10 2006.231.07:37:06.14#trakl#Off source 2006.231.07:37:06.14?ERROR st -7 Antenna off-source! 2006.231.07:37:06.14#trakl#az 294.223 el 84.097 azerr*cos(el) -0.0002 elerr -0.0173 2006.231.07:37:07.14#flagr#flagr/antenna,off-source 2006.231.07:37:10.00:data_valid=on 2006.231.07:37:10.00:midob 2006.231.07:37:11.14?ERROR an -103 Pointing computer tracking errors are too large. 2006.231.07:37:11.14?ERROR qo -301 WARNING: ONSOURCE status is SLEWING! 2006.231.07:37:11.14/onsource/SLEWING 2006.231.07:37:11.14/wx/30.71,1004.4,82 2006.231.07:37:11.29/cable/+6.3702E-03 2006.231.07:37:12.14#trakl#Source re-acquired 2006.231.07:37:12.14#flagr#flagr/antenna,re-acquired 2006.231.07:37:12.38/va/01,08,usb,yes,29,30 2006.231.07:37:12.38/va/02,07,usb,yes,29,30 2006.231.07:37:12.38/va/03,08,usb,yes,22,22 2006.231.07:37:12.38/va/04,07,usb,yes,30,33 2006.231.07:37:12.38/va/05,07,usb,yes,34,36 2006.231.07:37:12.38/va/06,06,usb,yes,33,33 2006.231.07:37:12.38/va/07,06,usb,yes,34,34 2006.231.07:37:12.38/va/08,06,usb,yes,36,35 2006.231.07:37:12.61/valo/01,532.99,yes,locked 2006.231.07:37:12.61/valo/02,572.99,yes,locked 2006.231.07:37:12.61/valo/03,672.99,yes,locked 2006.231.07:37:12.61/valo/04,832.99,yes,locked 2006.231.07:37:12.61/valo/05,652.99,yes,locked 2006.231.07:37:12.61/valo/06,772.99,yes,locked 2006.231.07:37:12.61/valo/07,832.99,yes,locked 2006.231.07:37:12.61/valo/08,852.99,yes,locked 2006.231.07:37:13.70/vb/01,04,usb,yes,30,29 2006.231.07:37:13.70/vb/02,04,usb,yes,32,34 2006.231.07:37:13.70/vb/03,04,usb,yes,29,32 2006.231.07:37:13.70/vb/04,04,usb,yes,29,30 2006.231.07:37:13.70/vb/05,03,usb,yes,35,39 2006.231.07:37:13.70/vb/06,04,usb,yes,29,32 2006.231.07:37:13.70/vb/07,04,usb,yes,31,31 2006.231.07:37:13.70/vb/08,04,usb,yes,28,32 2006.231.07:37:13.93/vblo/01,632.99,yes,locked 2006.231.07:37:13.93/vblo/02,640.99,yes,locked 2006.231.07:37:13.93/vblo/03,656.99,yes,locked 2006.231.07:37:13.93/vblo/04,712.99,yes,locked 2006.231.07:37:13.93/vblo/05,744.99,yes,locked 2006.231.07:37:13.93/vblo/06,752.99,yes,locked 2006.231.07:37:13.93/vblo/07,734.99,yes,locked 2006.231.07:37:13.93/vblo/08,744.99,yes,locked 2006.231.07:37:14.08/vabw/8 2006.231.07:37:14.23/vbbw/8 2006.231.07:37:14.32/xfe/off,on,12.5 2006.231.07:37:14.71/ifatt/23,28,28,28 2006.231.07:37:15.07/fmout-gps/S +4.38E-07 2006.231.07:37:15.11:!2006.231.07:38:10 2006.231.07:38:10.01:data_valid=off 2006.231.07:38:10.02:postob 2006.231.07:38:10.14/cable/+6.3705E-03 2006.231.07:38:10.15/wx/30.70,1004.4,83 2006.231.07:38:11.07/fmout-gps/S +4.38E-07 2006.231.07:38:11.08:scan_name=231-0739,k06231,60 2006.231.07:38:11.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.231.07:38:11.14#flagr#flagr/antenna,new-source 2006.231.07:38:12.14:checkk5 2006.231.07:38:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:38:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:38:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:38:13.64/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:38:14.01/chk_obsdata//k5ts1/T2310737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:38:14.38/chk_obsdata//k5ts2/T2310737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:38:14.75/chk_obsdata//k5ts3/T2310737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:38:15.12/chk_obsdata//k5ts4/T2310737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:38:15.80/k5log//k5ts1_log_newline 2006.231.07:38:16.49/k5log//k5ts2_log_newline 2006.231.07:38:17.18/k5log//k5ts3_log_newline 2006.231.07:38:17.87/k5log//k5ts4_log_newline 2006.231.07:38:17.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:38:17.90:4f8m12a=1 2006.231.07:38:17.90$4f8m12a/echo=on 2006.231.07:38:17.90$4f8m12a/pcalon 2006.231.07:38:17.90$pcalon/"no phase cal control is implemented here 2006.231.07:38:17.90$4f8m12a/"tpicd=stop 2006.231.07:38:17.90$4f8m12a/vc4f8 2006.231.07:38:17.90$vc4f8/valo=1,532.99 2006.231.07:38:17.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.231.07:38:17.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.231.07:38:17.90#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:17.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:38:17.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:38:17.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:38:17.90#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:38:17.90#ibcon#first serial, iclass 35, count 0 2006.231.07:38:17.90#ibcon#enter sib2, iclass 35, count 0 2006.231.07:38:17.90#ibcon#flushed, iclass 35, count 0 2006.231.07:38:17.90#ibcon#about to write, iclass 35, count 0 2006.231.07:38:17.90#ibcon#wrote, iclass 35, count 0 2006.231.07:38:17.90#ibcon#about to read 3, iclass 35, count 0 2006.231.07:38:17.94#ibcon#read 3, iclass 35, count 0 2006.231.07:38:17.94#ibcon#about to read 4, iclass 35, count 0 2006.231.07:38:17.94#ibcon#read 4, iclass 35, count 0 2006.231.07:38:17.94#ibcon#about to read 5, iclass 35, count 0 2006.231.07:38:17.94#ibcon#read 5, iclass 35, count 0 2006.231.07:38:17.94#ibcon#about to read 6, iclass 35, count 0 2006.231.07:38:17.94#ibcon#read 6, iclass 35, count 0 2006.231.07:38:17.94#ibcon#end of sib2, iclass 35, count 0 2006.231.07:38:17.94#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:38:17.94#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:38:17.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:38:17.94#ibcon#*before write, iclass 35, count 0 2006.231.07:38:17.94#ibcon#enter sib2, iclass 35, count 0 2006.231.07:38:17.94#ibcon#flushed, iclass 35, count 0 2006.231.07:38:17.94#ibcon#about to write, iclass 35, count 0 2006.231.07:38:17.94#ibcon#wrote, iclass 35, count 0 2006.231.07:38:17.94#ibcon#about to read 3, iclass 35, count 0 2006.231.07:38:17.99#ibcon#read 3, iclass 35, count 0 2006.231.07:38:17.99#ibcon#about to read 4, iclass 35, count 0 2006.231.07:38:17.99#ibcon#read 4, iclass 35, count 0 2006.231.07:38:17.99#ibcon#about to read 5, iclass 35, count 0 2006.231.07:38:17.99#ibcon#read 5, iclass 35, count 0 2006.231.07:38:17.99#ibcon#about to read 6, iclass 35, count 0 2006.231.07:38:17.99#ibcon#read 6, iclass 35, count 0 2006.231.07:38:17.99#ibcon#end of sib2, iclass 35, count 0 2006.231.07:38:17.99#ibcon#*after write, iclass 35, count 0 2006.231.07:38:17.99#ibcon#*before return 0, iclass 35, count 0 2006.231.07:38:17.99#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:38:17.99#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:38:17.99#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:38:17.99#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:38:17.99$vc4f8/va=1,8 2006.231.07:38:17.99#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.231.07:38:17.99#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.231.07:38:17.99#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:17.99#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:38:17.99#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:38:17.99#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:38:17.99#ibcon#enter wrdev, iclass 37, count 2 2006.231.07:38:17.99#ibcon#first serial, iclass 37, count 2 2006.231.07:38:17.99#ibcon#enter sib2, iclass 37, count 2 2006.231.07:38:17.99#ibcon#flushed, iclass 37, count 2 2006.231.07:38:17.99#ibcon#about to write, iclass 37, count 2 2006.231.07:38:17.99#ibcon#wrote, iclass 37, count 2 2006.231.07:38:17.99#ibcon#about to read 3, iclass 37, count 2 2006.231.07:38:18.02#ibcon#read 3, iclass 37, count 2 2006.231.07:38:18.02#ibcon#about to read 4, iclass 37, count 2 2006.231.07:38:18.02#ibcon#read 4, iclass 37, count 2 2006.231.07:38:18.02#ibcon#about to read 5, iclass 37, count 2 2006.231.07:38:18.02#ibcon#read 5, iclass 37, count 2 2006.231.07:38:18.02#ibcon#about to read 6, iclass 37, count 2 2006.231.07:38:18.02#ibcon#read 6, iclass 37, count 2 2006.231.07:38:18.02#ibcon#end of sib2, iclass 37, count 2 2006.231.07:38:18.02#ibcon#*mode == 0, iclass 37, count 2 2006.231.07:38:18.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.231.07:38:18.02#ibcon#[25=AT01-08\r\n] 2006.231.07:38:18.02#ibcon#*before write, iclass 37, count 2 2006.231.07:38:18.02#ibcon#enter sib2, iclass 37, count 2 2006.231.07:38:18.02#ibcon#flushed, iclass 37, count 2 2006.231.07:38:18.02#ibcon#about to write, iclass 37, count 2 2006.231.07:38:18.02#ibcon#wrote, iclass 37, count 2 2006.231.07:38:18.02#ibcon#about to read 3, iclass 37, count 2 2006.231.07:38:18.05#ibcon#read 3, iclass 37, count 2 2006.231.07:38:18.05#ibcon#about to read 4, iclass 37, count 2 2006.231.07:38:18.05#ibcon#read 4, iclass 37, count 2 2006.231.07:38:18.05#ibcon#about to read 5, iclass 37, count 2 2006.231.07:38:18.05#ibcon#read 5, iclass 37, count 2 2006.231.07:38:18.05#ibcon#about to read 6, iclass 37, count 2 2006.231.07:38:18.05#ibcon#read 6, iclass 37, count 2 2006.231.07:38:18.05#ibcon#end of sib2, iclass 37, count 2 2006.231.07:38:18.05#ibcon#*after write, iclass 37, count 2 2006.231.07:38:18.05#ibcon#*before return 0, iclass 37, count 2 2006.231.07:38:18.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:38:18.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:38:18.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.231.07:38:18.05#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:18.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:38:18.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:38:18.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:38:18.17#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:38:18.17#ibcon#first serial, iclass 37, count 0 2006.231.07:38:18.17#ibcon#enter sib2, iclass 37, count 0 2006.231.07:38:18.17#ibcon#flushed, iclass 37, count 0 2006.231.07:38:18.17#ibcon#about to write, iclass 37, count 0 2006.231.07:38:18.17#ibcon#wrote, iclass 37, count 0 2006.231.07:38:18.17#ibcon#about to read 3, iclass 37, count 0 2006.231.07:38:18.19#ibcon#read 3, iclass 37, count 0 2006.231.07:38:18.19#ibcon#about to read 4, iclass 37, count 0 2006.231.07:38:18.19#ibcon#read 4, iclass 37, count 0 2006.231.07:38:18.19#ibcon#about to read 5, iclass 37, count 0 2006.231.07:38:18.19#ibcon#read 5, iclass 37, count 0 2006.231.07:38:18.19#ibcon#about to read 6, iclass 37, count 0 2006.231.07:38:18.19#ibcon#read 6, iclass 37, count 0 2006.231.07:38:18.19#ibcon#end of sib2, iclass 37, count 0 2006.231.07:38:18.19#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:38:18.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:38:18.19#ibcon#[25=USB\r\n] 2006.231.07:38:18.19#ibcon#*before write, iclass 37, count 0 2006.231.07:38:18.19#ibcon#enter sib2, iclass 37, count 0 2006.231.07:38:18.19#ibcon#flushed, iclass 37, count 0 2006.231.07:38:18.19#ibcon#about to write, iclass 37, count 0 2006.231.07:38:18.19#ibcon#wrote, iclass 37, count 0 2006.231.07:38:18.19#ibcon#about to read 3, iclass 37, count 0 2006.231.07:38:18.22#ibcon#read 3, iclass 37, count 0 2006.231.07:38:18.22#ibcon#about to read 4, iclass 37, count 0 2006.231.07:38:18.22#ibcon#read 4, iclass 37, count 0 2006.231.07:38:18.22#ibcon#about to read 5, iclass 37, count 0 2006.231.07:38:18.22#ibcon#read 5, iclass 37, count 0 2006.231.07:38:18.22#ibcon#about to read 6, iclass 37, count 0 2006.231.07:38:18.22#ibcon#read 6, iclass 37, count 0 2006.231.07:38:18.22#ibcon#end of sib2, iclass 37, count 0 2006.231.07:38:18.22#ibcon#*after write, iclass 37, count 0 2006.231.07:38:18.22#ibcon#*before return 0, iclass 37, count 0 2006.231.07:38:18.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:38:18.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:38:18.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:38:18.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:38:18.22$vc4f8/valo=2,572.99 2006.231.07:38:18.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.07:38:18.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.07:38:18.22#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:18.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:38:18.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:38:18.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:38:18.22#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:38:18.22#ibcon#first serial, iclass 39, count 0 2006.231.07:38:18.22#ibcon#enter sib2, iclass 39, count 0 2006.231.07:38:18.22#ibcon#flushed, iclass 39, count 0 2006.231.07:38:18.22#ibcon#about to write, iclass 39, count 0 2006.231.07:38:18.22#ibcon#wrote, iclass 39, count 0 2006.231.07:38:18.22#ibcon#about to read 3, iclass 39, count 0 2006.231.07:38:18.25#ibcon#read 3, iclass 39, count 0 2006.231.07:38:18.25#ibcon#about to read 4, iclass 39, count 0 2006.231.07:38:18.25#ibcon#read 4, iclass 39, count 0 2006.231.07:38:18.25#ibcon#about to read 5, iclass 39, count 0 2006.231.07:38:18.25#ibcon#read 5, iclass 39, count 0 2006.231.07:38:18.25#ibcon#about to read 6, iclass 39, count 0 2006.231.07:38:18.25#ibcon#read 6, iclass 39, count 0 2006.231.07:38:18.25#ibcon#end of sib2, iclass 39, count 0 2006.231.07:38:18.25#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:38:18.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:38:18.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:38:18.25#ibcon#*before write, iclass 39, count 0 2006.231.07:38:18.25#ibcon#enter sib2, iclass 39, count 0 2006.231.07:38:18.25#ibcon#flushed, iclass 39, count 0 2006.231.07:38:18.25#ibcon#about to write, iclass 39, count 0 2006.231.07:38:18.25#ibcon#wrote, iclass 39, count 0 2006.231.07:38:18.25#ibcon#about to read 3, iclass 39, count 0 2006.231.07:38:18.28#ibcon#read 3, iclass 39, count 0 2006.231.07:38:18.28#ibcon#about to read 4, iclass 39, count 0 2006.231.07:38:18.28#ibcon#read 4, iclass 39, count 0 2006.231.07:38:18.28#ibcon#about to read 5, iclass 39, count 0 2006.231.07:38:18.28#ibcon#read 5, iclass 39, count 0 2006.231.07:38:18.28#ibcon#about to read 6, iclass 39, count 0 2006.231.07:38:18.28#ibcon#read 6, iclass 39, count 0 2006.231.07:38:18.28#ibcon#end of sib2, iclass 39, count 0 2006.231.07:38:18.28#ibcon#*after write, iclass 39, count 0 2006.231.07:38:18.28#ibcon#*before return 0, iclass 39, count 0 2006.231.07:38:18.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:38:18.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:38:18.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:38:18.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:38:18.28$vc4f8/va=2,7 2006.231.07:38:18.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.231.07:38:18.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.231.07:38:18.28#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:18.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:38:18.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:38:18.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:38:18.34#ibcon#enter wrdev, iclass 3, count 2 2006.231.07:38:18.34#ibcon#first serial, iclass 3, count 2 2006.231.07:38:18.34#ibcon#enter sib2, iclass 3, count 2 2006.231.07:38:18.34#ibcon#flushed, iclass 3, count 2 2006.231.07:38:18.34#ibcon#about to write, iclass 3, count 2 2006.231.07:38:18.34#ibcon#wrote, iclass 3, count 2 2006.231.07:38:18.34#ibcon#about to read 3, iclass 3, count 2 2006.231.07:38:18.36#ibcon#read 3, iclass 3, count 2 2006.231.07:38:18.36#ibcon#about to read 4, iclass 3, count 2 2006.231.07:38:18.36#ibcon#read 4, iclass 3, count 2 2006.231.07:38:18.36#ibcon#about to read 5, iclass 3, count 2 2006.231.07:38:18.36#ibcon#read 5, iclass 3, count 2 2006.231.07:38:18.36#ibcon#about to read 6, iclass 3, count 2 2006.231.07:38:18.36#ibcon#read 6, iclass 3, count 2 2006.231.07:38:18.36#ibcon#end of sib2, iclass 3, count 2 2006.231.07:38:18.36#ibcon#*mode == 0, iclass 3, count 2 2006.231.07:38:18.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.231.07:38:18.36#ibcon#[25=AT02-07\r\n] 2006.231.07:38:18.36#ibcon#*before write, iclass 3, count 2 2006.231.07:38:18.36#ibcon#enter sib2, iclass 3, count 2 2006.231.07:38:18.36#ibcon#flushed, iclass 3, count 2 2006.231.07:38:18.36#ibcon#about to write, iclass 3, count 2 2006.231.07:38:18.36#ibcon#wrote, iclass 3, count 2 2006.231.07:38:18.36#ibcon#about to read 3, iclass 3, count 2 2006.231.07:38:18.39#ibcon#read 3, iclass 3, count 2 2006.231.07:38:18.39#ibcon#about to read 4, iclass 3, count 2 2006.231.07:38:18.39#ibcon#read 4, iclass 3, count 2 2006.231.07:38:18.39#ibcon#about to read 5, iclass 3, count 2 2006.231.07:38:18.39#ibcon#read 5, iclass 3, count 2 2006.231.07:38:18.39#ibcon#about to read 6, iclass 3, count 2 2006.231.07:38:18.39#ibcon#read 6, iclass 3, count 2 2006.231.07:38:18.39#ibcon#end of sib2, iclass 3, count 2 2006.231.07:38:18.39#ibcon#*after write, iclass 3, count 2 2006.231.07:38:18.39#ibcon#*before return 0, iclass 3, count 2 2006.231.07:38:18.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:38:18.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:38:18.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.231.07:38:18.39#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:18.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:38:18.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:38:18.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:38:18.51#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:38:18.51#ibcon#first serial, iclass 3, count 0 2006.231.07:38:18.51#ibcon#enter sib2, iclass 3, count 0 2006.231.07:38:18.51#ibcon#flushed, iclass 3, count 0 2006.231.07:38:18.51#ibcon#about to write, iclass 3, count 0 2006.231.07:38:18.51#ibcon#wrote, iclass 3, count 0 2006.231.07:38:18.51#ibcon#about to read 3, iclass 3, count 0 2006.231.07:38:18.53#ibcon#read 3, iclass 3, count 0 2006.231.07:38:18.53#ibcon#about to read 4, iclass 3, count 0 2006.231.07:38:18.53#ibcon#read 4, iclass 3, count 0 2006.231.07:38:18.53#ibcon#about to read 5, iclass 3, count 0 2006.231.07:38:18.53#ibcon#read 5, iclass 3, count 0 2006.231.07:38:18.53#ibcon#about to read 6, iclass 3, count 0 2006.231.07:38:18.53#ibcon#read 6, iclass 3, count 0 2006.231.07:38:18.53#ibcon#end of sib2, iclass 3, count 0 2006.231.07:38:18.53#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:38:18.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:38:18.53#ibcon#[25=USB\r\n] 2006.231.07:38:18.53#ibcon#*before write, iclass 3, count 0 2006.231.07:38:18.53#ibcon#enter sib2, iclass 3, count 0 2006.231.07:38:18.53#ibcon#flushed, iclass 3, count 0 2006.231.07:38:18.53#ibcon#about to write, iclass 3, count 0 2006.231.07:38:18.53#ibcon#wrote, iclass 3, count 0 2006.231.07:38:18.53#ibcon#about to read 3, iclass 3, count 0 2006.231.07:38:18.56#ibcon#read 3, iclass 3, count 0 2006.231.07:38:18.56#ibcon#about to read 4, iclass 3, count 0 2006.231.07:38:18.56#ibcon#read 4, iclass 3, count 0 2006.231.07:38:18.56#ibcon#about to read 5, iclass 3, count 0 2006.231.07:38:18.56#ibcon#read 5, iclass 3, count 0 2006.231.07:38:18.56#ibcon#about to read 6, iclass 3, count 0 2006.231.07:38:18.56#ibcon#read 6, iclass 3, count 0 2006.231.07:38:18.56#ibcon#end of sib2, iclass 3, count 0 2006.231.07:38:18.56#ibcon#*after write, iclass 3, count 0 2006.231.07:38:18.56#ibcon#*before return 0, iclass 3, count 0 2006.231.07:38:18.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:38:18.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:38:18.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:38:18.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:38:18.56$vc4f8/valo=3,672.99 2006.231.07:38:18.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.231.07:38:18.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.231.07:38:18.56#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:18.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:38:18.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:38:18.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:38:18.56#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:38:18.56#ibcon#first serial, iclass 5, count 0 2006.231.07:38:18.56#ibcon#enter sib2, iclass 5, count 0 2006.231.07:38:18.56#ibcon#flushed, iclass 5, count 0 2006.231.07:38:18.56#ibcon#about to write, iclass 5, count 0 2006.231.07:38:18.56#ibcon#wrote, iclass 5, count 0 2006.231.07:38:18.56#ibcon#about to read 3, iclass 5, count 0 2006.231.07:38:18.58#ibcon#read 3, iclass 5, count 0 2006.231.07:38:18.58#ibcon#about to read 4, iclass 5, count 0 2006.231.07:38:18.58#ibcon#read 4, iclass 5, count 0 2006.231.07:38:18.58#ibcon#about to read 5, iclass 5, count 0 2006.231.07:38:18.58#ibcon#read 5, iclass 5, count 0 2006.231.07:38:18.58#ibcon#about to read 6, iclass 5, count 0 2006.231.07:38:18.58#ibcon#read 6, iclass 5, count 0 2006.231.07:38:18.58#ibcon#end of sib2, iclass 5, count 0 2006.231.07:38:18.58#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:38:18.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:38:18.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:38:18.58#ibcon#*before write, iclass 5, count 0 2006.231.07:38:18.58#ibcon#enter sib2, iclass 5, count 0 2006.231.07:38:18.58#ibcon#flushed, iclass 5, count 0 2006.231.07:38:18.58#ibcon#about to write, iclass 5, count 0 2006.231.07:38:18.58#ibcon#wrote, iclass 5, count 0 2006.231.07:38:18.58#ibcon#about to read 3, iclass 5, count 0 2006.231.07:38:18.62#ibcon#read 3, iclass 5, count 0 2006.231.07:38:18.62#ibcon#about to read 4, iclass 5, count 0 2006.231.07:38:18.62#ibcon#read 4, iclass 5, count 0 2006.231.07:38:18.62#ibcon#about to read 5, iclass 5, count 0 2006.231.07:38:18.62#ibcon#read 5, iclass 5, count 0 2006.231.07:38:18.62#ibcon#about to read 6, iclass 5, count 0 2006.231.07:38:18.62#ibcon#read 6, iclass 5, count 0 2006.231.07:38:18.62#ibcon#end of sib2, iclass 5, count 0 2006.231.07:38:18.62#ibcon#*after write, iclass 5, count 0 2006.231.07:38:18.62#ibcon#*before return 0, iclass 5, count 0 2006.231.07:38:18.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:38:18.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:38:18.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:38:18.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:38:18.62$vc4f8/va=3,8 2006.231.07:38:18.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.231.07:38:18.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.231.07:38:18.62#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:18.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:38:18.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:38:18.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:38:18.68#ibcon#enter wrdev, iclass 7, count 2 2006.231.07:38:18.68#ibcon#first serial, iclass 7, count 2 2006.231.07:38:18.68#ibcon#enter sib2, iclass 7, count 2 2006.231.07:38:18.68#ibcon#flushed, iclass 7, count 2 2006.231.07:38:18.68#ibcon#about to write, iclass 7, count 2 2006.231.07:38:18.68#ibcon#wrote, iclass 7, count 2 2006.231.07:38:18.68#ibcon#about to read 3, iclass 7, count 2 2006.231.07:38:18.70#ibcon#read 3, iclass 7, count 2 2006.231.07:38:18.70#ibcon#about to read 4, iclass 7, count 2 2006.231.07:38:18.70#ibcon#read 4, iclass 7, count 2 2006.231.07:38:18.70#ibcon#about to read 5, iclass 7, count 2 2006.231.07:38:18.70#ibcon#read 5, iclass 7, count 2 2006.231.07:38:18.70#ibcon#about to read 6, iclass 7, count 2 2006.231.07:38:18.70#ibcon#read 6, iclass 7, count 2 2006.231.07:38:18.70#ibcon#end of sib2, iclass 7, count 2 2006.231.07:38:18.70#ibcon#*mode == 0, iclass 7, count 2 2006.231.07:38:18.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.231.07:38:18.70#ibcon#[25=AT03-08\r\n] 2006.231.07:38:18.70#ibcon#*before write, iclass 7, count 2 2006.231.07:38:18.70#ibcon#enter sib2, iclass 7, count 2 2006.231.07:38:18.70#ibcon#flushed, iclass 7, count 2 2006.231.07:38:18.70#ibcon#about to write, iclass 7, count 2 2006.231.07:38:18.70#ibcon#wrote, iclass 7, count 2 2006.231.07:38:18.70#ibcon#about to read 3, iclass 7, count 2 2006.231.07:38:18.73#ibcon#read 3, iclass 7, count 2 2006.231.07:38:18.73#ibcon#about to read 4, iclass 7, count 2 2006.231.07:38:18.73#ibcon#read 4, iclass 7, count 2 2006.231.07:38:18.73#ibcon#about to read 5, iclass 7, count 2 2006.231.07:38:18.73#ibcon#read 5, iclass 7, count 2 2006.231.07:38:18.73#ibcon#about to read 6, iclass 7, count 2 2006.231.07:38:18.73#ibcon#read 6, iclass 7, count 2 2006.231.07:38:18.73#ibcon#end of sib2, iclass 7, count 2 2006.231.07:38:18.73#ibcon#*after write, iclass 7, count 2 2006.231.07:38:18.73#ibcon#*before return 0, iclass 7, count 2 2006.231.07:38:18.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:38:18.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:38:18.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.231.07:38:18.73#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:18.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:38:18.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:38:18.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:38:18.85#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:38:18.85#ibcon#first serial, iclass 7, count 0 2006.231.07:38:18.85#ibcon#enter sib2, iclass 7, count 0 2006.231.07:38:18.85#ibcon#flushed, iclass 7, count 0 2006.231.07:38:18.85#ibcon#about to write, iclass 7, count 0 2006.231.07:38:18.85#ibcon#wrote, iclass 7, count 0 2006.231.07:38:18.85#ibcon#about to read 3, iclass 7, count 0 2006.231.07:38:18.87#ibcon#read 3, iclass 7, count 0 2006.231.07:38:18.87#ibcon#about to read 4, iclass 7, count 0 2006.231.07:38:18.87#ibcon#read 4, iclass 7, count 0 2006.231.07:38:18.87#ibcon#about to read 5, iclass 7, count 0 2006.231.07:38:18.87#ibcon#read 5, iclass 7, count 0 2006.231.07:38:18.87#ibcon#about to read 6, iclass 7, count 0 2006.231.07:38:18.87#ibcon#read 6, iclass 7, count 0 2006.231.07:38:18.87#ibcon#end of sib2, iclass 7, count 0 2006.231.07:38:18.87#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:38:18.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:38:18.87#ibcon#[25=USB\r\n] 2006.231.07:38:18.87#ibcon#*before write, iclass 7, count 0 2006.231.07:38:18.87#ibcon#enter sib2, iclass 7, count 0 2006.231.07:38:18.87#ibcon#flushed, iclass 7, count 0 2006.231.07:38:18.87#ibcon#about to write, iclass 7, count 0 2006.231.07:38:18.87#ibcon#wrote, iclass 7, count 0 2006.231.07:38:18.87#ibcon#about to read 3, iclass 7, count 0 2006.231.07:38:18.90#ibcon#read 3, iclass 7, count 0 2006.231.07:38:18.90#ibcon#about to read 4, iclass 7, count 0 2006.231.07:38:18.90#ibcon#read 4, iclass 7, count 0 2006.231.07:38:18.90#ibcon#about to read 5, iclass 7, count 0 2006.231.07:38:18.90#ibcon#read 5, iclass 7, count 0 2006.231.07:38:18.90#ibcon#about to read 6, iclass 7, count 0 2006.231.07:38:18.90#ibcon#read 6, iclass 7, count 0 2006.231.07:38:18.90#ibcon#end of sib2, iclass 7, count 0 2006.231.07:38:18.90#ibcon#*after write, iclass 7, count 0 2006.231.07:38:18.90#ibcon#*before return 0, iclass 7, count 0 2006.231.07:38:18.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:38:18.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:38:18.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:38:18.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:38:18.90$vc4f8/valo=4,832.99 2006.231.07:38:18.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.231.07:38:18.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.231.07:38:18.90#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:18.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:38:18.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:38:18.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:38:18.90#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:38:18.90#ibcon#first serial, iclass 11, count 0 2006.231.07:38:18.90#ibcon#enter sib2, iclass 11, count 0 2006.231.07:38:18.90#ibcon#flushed, iclass 11, count 0 2006.231.07:38:18.90#ibcon#about to write, iclass 11, count 0 2006.231.07:38:18.90#ibcon#wrote, iclass 11, count 0 2006.231.07:38:18.90#ibcon#about to read 3, iclass 11, count 0 2006.231.07:38:18.93#ibcon#read 3, iclass 11, count 0 2006.231.07:38:18.93#ibcon#about to read 4, iclass 11, count 0 2006.231.07:38:18.93#ibcon#read 4, iclass 11, count 0 2006.231.07:38:18.93#ibcon#about to read 5, iclass 11, count 0 2006.231.07:38:18.93#ibcon#read 5, iclass 11, count 0 2006.231.07:38:18.93#ibcon#about to read 6, iclass 11, count 0 2006.231.07:38:18.93#ibcon#read 6, iclass 11, count 0 2006.231.07:38:18.93#ibcon#end of sib2, iclass 11, count 0 2006.231.07:38:18.93#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:38:18.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:38:18.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:38:18.93#ibcon#*before write, iclass 11, count 0 2006.231.07:38:18.93#ibcon#enter sib2, iclass 11, count 0 2006.231.07:38:18.93#ibcon#flushed, iclass 11, count 0 2006.231.07:38:18.93#ibcon#about to write, iclass 11, count 0 2006.231.07:38:18.93#ibcon#wrote, iclass 11, count 0 2006.231.07:38:18.93#ibcon#about to read 3, iclass 11, count 0 2006.231.07:38:18.97#ibcon#read 3, iclass 11, count 0 2006.231.07:38:18.97#ibcon#about to read 4, iclass 11, count 0 2006.231.07:38:18.97#ibcon#read 4, iclass 11, count 0 2006.231.07:38:18.97#ibcon#about to read 5, iclass 11, count 0 2006.231.07:38:18.97#ibcon#read 5, iclass 11, count 0 2006.231.07:38:18.97#ibcon#about to read 6, iclass 11, count 0 2006.231.07:38:18.97#ibcon#read 6, iclass 11, count 0 2006.231.07:38:18.97#ibcon#end of sib2, iclass 11, count 0 2006.231.07:38:18.97#ibcon#*after write, iclass 11, count 0 2006.231.07:38:18.97#ibcon#*before return 0, iclass 11, count 0 2006.231.07:38:18.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:38:18.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:38:18.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:38:18.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:38:18.97$vc4f8/va=4,7 2006.231.07:38:18.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.231.07:38:18.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.231.07:38:18.97#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:18.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:38:19.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:38:19.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:38:19.02#ibcon#enter wrdev, iclass 13, count 2 2006.231.07:38:19.02#ibcon#first serial, iclass 13, count 2 2006.231.07:38:19.02#ibcon#enter sib2, iclass 13, count 2 2006.231.07:38:19.02#ibcon#flushed, iclass 13, count 2 2006.231.07:38:19.02#ibcon#about to write, iclass 13, count 2 2006.231.07:38:19.02#ibcon#wrote, iclass 13, count 2 2006.231.07:38:19.02#ibcon#about to read 3, iclass 13, count 2 2006.231.07:38:19.04#ibcon#read 3, iclass 13, count 2 2006.231.07:38:19.04#ibcon#about to read 4, iclass 13, count 2 2006.231.07:38:19.04#ibcon#read 4, iclass 13, count 2 2006.231.07:38:19.04#ibcon#about to read 5, iclass 13, count 2 2006.231.07:38:19.04#ibcon#read 5, iclass 13, count 2 2006.231.07:38:19.04#ibcon#about to read 6, iclass 13, count 2 2006.231.07:38:19.04#ibcon#read 6, iclass 13, count 2 2006.231.07:38:19.04#ibcon#end of sib2, iclass 13, count 2 2006.231.07:38:19.04#ibcon#*mode == 0, iclass 13, count 2 2006.231.07:38:19.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.231.07:38:19.04#ibcon#[25=AT04-07\r\n] 2006.231.07:38:19.04#ibcon#*before write, iclass 13, count 2 2006.231.07:38:19.04#ibcon#enter sib2, iclass 13, count 2 2006.231.07:38:19.04#ibcon#flushed, iclass 13, count 2 2006.231.07:38:19.04#ibcon#about to write, iclass 13, count 2 2006.231.07:38:19.04#ibcon#wrote, iclass 13, count 2 2006.231.07:38:19.04#ibcon#about to read 3, iclass 13, count 2 2006.231.07:38:19.07#ibcon#read 3, iclass 13, count 2 2006.231.07:38:19.07#ibcon#about to read 4, iclass 13, count 2 2006.231.07:38:19.07#ibcon#read 4, iclass 13, count 2 2006.231.07:38:19.07#ibcon#about to read 5, iclass 13, count 2 2006.231.07:38:19.07#ibcon#read 5, iclass 13, count 2 2006.231.07:38:19.07#ibcon#about to read 6, iclass 13, count 2 2006.231.07:38:19.07#ibcon#read 6, iclass 13, count 2 2006.231.07:38:19.07#ibcon#end of sib2, iclass 13, count 2 2006.231.07:38:19.07#ibcon#*after write, iclass 13, count 2 2006.231.07:38:19.07#ibcon#*before return 0, iclass 13, count 2 2006.231.07:38:19.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:38:19.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:38:19.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.231.07:38:19.07#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:19.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:38:19.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:38:19.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:38:19.19#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:38:19.19#ibcon#first serial, iclass 13, count 0 2006.231.07:38:19.19#ibcon#enter sib2, iclass 13, count 0 2006.231.07:38:19.19#ibcon#flushed, iclass 13, count 0 2006.231.07:38:19.19#ibcon#about to write, iclass 13, count 0 2006.231.07:38:19.19#ibcon#wrote, iclass 13, count 0 2006.231.07:38:19.19#ibcon#about to read 3, iclass 13, count 0 2006.231.07:38:19.21#ibcon#read 3, iclass 13, count 0 2006.231.07:38:19.21#ibcon#about to read 4, iclass 13, count 0 2006.231.07:38:19.21#ibcon#read 4, iclass 13, count 0 2006.231.07:38:19.21#ibcon#about to read 5, iclass 13, count 0 2006.231.07:38:19.21#ibcon#read 5, iclass 13, count 0 2006.231.07:38:19.21#ibcon#about to read 6, iclass 13, count 0 2006.231.07:38:19.21#ibcon#read 6, iclass 13, count 0 2006.231.07:38:19.21#ibcon#end of sib2, iclass 13, count 0 2006.231.07:38:19.21#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:38:19.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:38:19.21#ibcon#[25=USB\r\n] 2006.231.07:38:19.21#ibcon#*before write, iclass 13, count 0 2006.231.07:38:19.21#ibcon#enter sib2, iclass 13, count 0 2006.231.07:38:19.21#ibcon#flushed, iclass 13, count 0 2006.231.07:38:19.21#ibcon#about to write, iclass 13, count 0 2006.231.07:38:19.21#ibcon#wrote, iclass 13, count 0 2006.231.07:38:19.21#ibcon#about to read 3, iclass 13, count 0 2006.231.07:38:19.24#ibcon#read 3, iclass 13, count 0 2006.231.07:38:19.24#ibcon#about to read 4, iclass 13, count 0 2006.231.07:38:19.24#ibcon#read 4, iclass 13, count 0 2006.231.07:38:19.24#ibcon#about to read 5, iclass 13, count 0 2006.231.07:38:19.24#ibcon#read 5, iclass 13, count 0 2006.231.07:38:19.24#ibcon#about to read 6, iclass 13, count 0 2006.231.07:38:19.24#ibcon#read 6, iclass 13, count 0 2006.231.07:38:19.24#ibcon#end of sib2, iclass 13, count 0 2006.231.07:38:19.24#ibcon#*after write, iclass 13, count 0 2006.231.07:38:19.24#ibcon#*before return 0, iclass 13, count 0 2006.231.07:38:19.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:38:19.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:38:19.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:38:19.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:38:19.24$vc4f8/valo=5,652.99 2006.231.07:38:19.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.07:38:19.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.07:38:19.24#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:19.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:38:19.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:38:19.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:38:19.24#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:38:19.24#ibcon#first serial, iclass 15, count 0 2006.231.07:38:19.24#ibcon#enter sib2, iclass 15, count 0 2006.231.07:38:19.24#ibcon#flushed, iclass 15, count 0 2006.231.07:38:19.24#ibcon#about to write, iclass 15, count 0 2006.231.07:38:19.24#ibcon#wrote, iclass 15, count 0 2006.231.07:38:19.24#ibcon#about to read 3, iclass 15, count 0 2006.231.07:38:19.26#ibcon#read 3, iclass 15, count 0 2006.231.07:38:19.26#ibcon#about to read 4, iclass 15, count 0 2006.231.07:38:19.26#ibcon#read 4, iclass 15, count 0 2006.231.07:38:19.26#ibcon#about to read 5, iclass 15, count 0 2006.231.07:38:19.26#ibcon#read 5, iclass 15, count 0 2006.231.07:38:19.26#ibcon#about to read 6, iclass 15, count 0 2006.231.07:38:19.26#ibcon#read 6, iclass 15, count 0 2006.231.07:38:19.26#ibcon#end of sib2, iclass 15, count 0 2006.231.07:38:19.26#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:38:19.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:38:19.26#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:38:19.26#ibcon#*before write, iclass 15, count 0 2006.231.07:38:19.26#ibcon#enter sib2, iclass 15, count 0 2006.231.07:38:19.26#ibcon#flushed, iclass 15, count 0 2006.231.07:38:19.26#ibcon#about to write, iclass 15, count 0 2006.231.07:38:19.26#ibcon#wrote, iclass 15, count 0 2006.231.07:38:19.26#ibcon#about to read 3, iclass 15, count 0 2006.231.07:38:19.30#ibcon#read 3, iclass 15, count 0 2006.231.07:38:19.30#ibcon#about to read 4, iclass 15, count 0 2006.231.07:38:19.30#ibcon#read 4, iclass 15, count 0 2006.231.07:38:19.30#ibcon#about to read 5, iclass 15, count 0 2006.231.07:38:19.30#ibcon#read 5, iclass 15, count 0 2006.231.07:38:19.30#ibcon#about to read 6, iclass 15, count 0 2006.231.07:38:19.30#ibcon#read 6, iclass 15, count 0 2006.231.07:38:19.30#ibcon#end of sib2, iclass 15, count 0 2006.231.07:38:19.30#ibcon#*after write, iclass 15, count 0 2006.231.07:38:19.30#ibcon#*before return 0, iclass 15, count 0 2006.231.07:38:19.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:38:19.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:38:19.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:38:19.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:38:19.30$vc4f8/va=5,7 2006.231.07:38:19.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.07:38:19.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.07:38:19.30#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:19.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:38:19.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:38:19.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:38:19.36#ibcon#enter wrdev, iclass 17, count 2 2006.231.07:38:19.36#ibcon#first serial, iclass 17, count 2 2006.231.07:38:19.36#ibcon#enter sib2, iclass 17, count 2 2006.231.07:38:19.36#ibcon#flushed, iclass 17, count 2 2006.231.07:38:19.36#ibcon#about to write, iclass 17, count 2 2006.231.07:38:19.36#ibcon#wrote, iclass 17, count 2 2006.231.07:38:19.36#ibcon#about to read 3, iclass 17, count 2 2006.231.07:38:19.38#ibcon#read 3, iclass 17, count 2 2006.231.07:38:19.38#ibcon#about to read 4, iclass 17, count 2 2006.231.07:38:19.38#ibcon#read 4, iclass 17, count 2 2006.231.07:38:19.38#ibcon#about to read 5, iclass 17, count 2 2006.231.07:38:19.38#ibcon#read 5, iclass 17, count 2 2006.231.07:38:19.38#ibcon#about to read 6, iclass 17, count 2 2006.231.07:38:19.38#ibcon#read 6, iclass 17, count 2 2006.231.07:38:19.38#ibcon#end of sib2, iclass 17, count 2 2006.231.07:38:19.38#ibcon#*mode == 0, iclass 17, count 2 2006.231.07:38:19.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.07:38:19.38#ibcon#[25=AT05-07\r\n] 2006.231.07:38:19.38#ibcon#*before write, iclass 17, count 2 2006.231.07:38:19.38#ibcon#enter sib2, iclass 17, count 2 2006.231.07:38:19.38#ibcon#flushed, iclass 17, count 2 2006.231.07:38:19.38#ibcon#about to write, iclass 17, count 2 2006.231.07:38:19.38#ibcon#wrote, iclass 17, count 2 2006.231.07:38:19.38#ibcon#about to read 3, iclass 17, count 2 2006.231.07:38:19.41#ibcon#read 3, iclass 17, count 2 2006.231.07:38:19.41#ibcon#about to read 4, iclass 17, count 2 2006.231.07:38:19.41#ibcon#read 4, iclass 17, count 2 2006.231.07:38:19.41#ibcon#about to read 5, iclass 17, count 2 2006.231.07:38:19.41#ibcon#read 5, iclass 17, count 2 2006.231.07:38:19.41#ibcon#about to read 6, iclass 17, count 2 2006.231.07:38:19.41#ibcon#read 6, iclass 17, count 2 2006.231.07:38:19.41#ibcon#end of sib2, iclass 17, count 2 2006.231.07:38:19.41#ibcon#*after write, iclass 17, count 2 2006.231.07:38:19.41#ibcon#*before return 0, iclass 17, count 2 2006.231.07:38:19.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:38:19.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:38:19.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.07:38:19.41#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:19.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:38:19.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:38:19.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:38:19.53#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:38:19.53#ibcon#first serial, iclass 17, count 0 2006.231.07:38:19.53#ibcon#enter sib2, iclass 17, count 0 2006.231.07:38:19.53#ibcon#flushed, iclass 17, count 0 2006.231.07:38:19.53#ibcon#about to write, iclass 17, count 0 2006.231.07:38:19.53#ibcon#wrote, iclass 17, count 0 2006.231.07:38:19.53#ibcon#about to read 3, iclass 17, count 0 2006.231.07:38:19.55#ibcon#read 3, iclass 17, count 0 2006.231.07:38:19.55#ibcon#about to read 4, iclass 17, count 0 2006.231.07:38:19.55#ibcon#read 4, iclass 17, count 0 2006.231.07:38:19.55#ibcon#about to read 5, iclass 17, count 0 2006.231.07:38:19.55#ibcon#read 5, iclass 17, count 0 2006.231.07:38:19.55#ibcon#about to read 6, iclass 17, count 0 2006.231.07:38:19.55#ibcon#read 6, iclass 17, count 0 2006.231.07:38:19.55#ibcon#end of sib2, iclass 17, count 0 2006.231.07:38:19.55#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:38:19.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:38:19.55#ibcon#[25=USB\r\n] 2006.231.07:38:19.55#ibcon#*before write, iclass 17, count 0 2006.231.07:38:19.55#ibcon#enter sib2, iclass 17, count 0 2006.231.07:38:19.55#ibcon#flushed, iclass 17, count 0 2006.231.07:38:19.55#ibcon#about to write, iclass 17, count 0 2006.231.07:38:19.55#ibcon#wrote, iclass 17, count 0 2006.231.07:38:19.55#ibcon#about to read 3, iclass 17, count 0 2006.231.07:38:19.58#ibcon#read 3, iclass 17, count 0 2006.231.07:38:19.58#ibcon#about to read 4, iclass 17, count 0 2006.231.07:38:19.58#ibcon#read 4, iclass 17, count 0 2006.231.07:38:19.58#ibcon#about to read 5, iclass 17, count 0 2006.231.07:38:19.58#ibcon#read 5, iclass 17, count 0 2006.231.07:38:19.58#ibcon#about to read 6, iclass 17, count 0 2006.231.07:38:19.58#ibcon#read 6, iclass 17, count 0 2006.231.07:38:19.58#ibcon#end of sib2, iclass 17, count 0 2006.231.07:38:19.58#ibcon#*after write, iclass 17, count 0 2006.231.07:38:19.58#ibcon#*before return 0, iclass 17, count 0 2006.231.07:38:19.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:38:19.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:38:19.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:38:19.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:38:19.58$vc4f8/valo=6,772.99 2006.231.07:38:19.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.07:38:19.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.07:38:19.58#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:19.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:38:19.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:38:19.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:38:19.58#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:38:19.58#ibcon#first serial, iclass 19, count 0 2006.231.07:38:19.58#ibcon#enter sib2, iclass 19, count 0 2006.231.07:38:19.58#ibcon#flushed, iclass 19, count 0 2006.231.07:38:19.58#ibcon#about to write, iclass 19, count 0 2006.231.07:38:19.58#ibcon#wrote, iclass 19, count 0 2006.231.07:38:19.58#ibcon#about to read 3, iclass 19, count 0 2006.231.07:38:19.60#ibcon#read 3, iclass 19, count 0 2006.231.07:38:19.60#ibcon#about to read 4, iclass 19, count 0 2006.231.07:38:19.60#ibcon#read 4, iclass 19, count 0 2006.231.07:38:19.60#ibcon#about to read 5, iclass 19, count 0 2006.231.07:38:19.60#ibcon#read 5, iclass 19, count 0 2006.231.07:38:19.60#ibcon#about to read 6, iclass 19, count 0 2006.231.07:38:19.60#ibcon#read 6, iclass 19, count 0 2006.231.07:38:19.60#ibcon#end of sib2, iclass 19, count 0 2006.231.07:38:19.60#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:38:19.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:38:19.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:38:19.60#ibcon#*before write, iclass 19, count 0 2006.231.07:38:19.60#ibcon#enter sib2, iclass 19, count 0 2006.231.07:38:19.60#ibcon#flushed, iclass 19, count 0 2006.231.07:38:19.60#ibcon#about to write, iclass 19, count 0 2006.231.07:38:19.60#ibcon#wrote, iclass 19, count 0 2006.231.07:38:19.60#ibcon#about to read 3, iclass 19, count 0 2006.231.07:38:19.64#ibcon#read 3, iclass 19, count 0 2006.231.07:38:19.64#ibcon#about to read 4, iclass 19, count 0 2006.231.07:38:19.64#ibcon#read 4, iclass 19, count 0 2006.231.07:38:19.64#ibcon#about to read 5, iclass 19, count 0 2006.231.07:38:19.64#ibcon#read 5, iclass 19, count 0 2006.231.07:38:19.64#ibcon#about to read 6, iclass 19, count 0 2006.231.07:38:19.64#ibcon#read 6, iclass 19, count 0 2006.231.07:38:19.64#ibcon#end of sib2, iclass 19, count 0 2006.231.07:38:19.64#ibcon#*after write, iclass 19, count 0 2006.231.07:38:19.64#ibcon#*before return 0, iclass 19, count 0 2006.231.07:38:19.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:38:19.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:38:19.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:38:19.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:38:19.64$vc4f8/va=6,6 2006.231.07:38:19.64#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.231.07:38:19.64#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.231.07:38:19.64#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:19.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:38:19.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:38:19.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:38:19.70#ibcon#enter wrdev, iclass 21, count 2 2006.231.07:38:19.70#ibcon#first serial, iclass 21, count 2 2006.231.07:38:19.70#ibcon#enter sib2, iclass 21, count 2 2006.231.07:38:19.70#ibcon#flushed, iclass 21, count 2 2006.231.07:38:19.70#ibcon#about to write, iclass 21, count 2 2006.231.07:38:19.70#ibcon#wrote, iclass 21, count 2 2006.231.07:38:19.70#ibcon#about to read 3, iclass 21, count 2 2006.231.07:38:19.72#ibcon#read 3, iclass 21, count 2 2006.231.07:38:19.72#ibcon#about to read 4, iclass 21, count 2 2006.231.07:38:19.72#ibcon#read 4, iclass 21, count 2 2006.231.07:38:19.72#ibcon#about to read 5, iclass 21, count 2 2006.231.07:38:19.72#ibcon#read 5, iclass 21, count 2 2006.231.07:38:19.72#ibcon#about to read 6, iclass 21, count 2 2006.231.07:38:19.72#ibcon#read 6, iclass 21, count 2 2006.231.07:38:19.72#ibcon#end of sib2, iclass 21, count 2 2006.231.07:38:19.72#ibcon#*mode == 0, iclass 21, count 2 2006.231.07:38:19.72#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.231.07:38:19.72#ibcon#[25=AT06-06\r\n] 2006.231.07:38:19.72#ibcon#*before write, iclass 21, count 2 2006.231.07:38:19.72#ibcon#enter sib2, iclass 21, count 2 2006.231.07:38:19.72#ibcon#flushed, iclass 21, count 2 2006.231.07:38:19.72#ibcon#about to write, iclass 21, count 2 2006.231.07:38:19.72#ibcon#wrote, iclass 21, count 2 2006.231.07:38:19.72#ibcon#about to read 3, iclass 21, count 2 2006.231.07:38:19.75#ibcon#read 3, iclass 21, count 2 2006.231.07:38:19.75#ibcon#about to read 4, iclass 21, count 2 2006.231.07:38:19.75#ibcon#read 4, iclass 21, count 2 2006.231.07:38:19.75#ibcon#about to read 5, iclass 21, count 2 2006.231.07:38:19.75#ibcon#read 5, iclass 21, count 2 2006.231.07:38:19.75#ibcon#about to read 6, iclass 21, count 2 2006.231.07:38:19.75#ibcon#read 6, iclass 21, count 2 2006.231.07:38:19.75#ibcon#end of sib2, iclass 21, count 2 2006.231.07:38:19.75#ibcon#*after write, iclass 21, count 2 2006.231.07:38:19.75#ibcon#*before return 0, iclass 21, count 2 2006.231.07:38:19.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:38:19.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:38:19.75#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.231.07:38:19.75#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:19.75#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:38:19.87#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:38:19.87#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:38:19.87#ibcon#enter wrdev, iclass 21, count 0 2006.231.07:38:19.87#ibcon#first serial, iclass 21, count 0 2006.231.07:38:19.87#ibcon#enter sib2, iclass 21, count 0 2006.231.07:38:19.87#ibcon#flushed, iclass 21, count 0 2006.231.07:38:19.87#ibcon#about to write, iclass 21, count 0 2006.231.07:38:19.87#ibcon#wrote, iclass 21, count 0 2006.231.07:38:19.87#ibcon#about to read 3, iclass 21, count 0 2006.231.07:38:19.89#ibcon#read 3, iclass 21, count 0 2006.231.07:38:19.89#ibcon#about to read 4, iclass 21, count 0 2006.231.07:38:19.89#ibcon#read 4, iclass 21, count 0 2006.231.07:38:19.89#ibcon#about to read 5, iclass 21, count 0 2006.231.07:38:19.89#ibcon#read 5, iclass 21, count 0 2006.231.07:38:19.89#ibcon#about to read 6, iclass 21, count 0 2006.231.07:38:19.89#ibcon#read 6, iclass 21, count 0 2006.231.07:38:19.89#ibcon#end of sib2, iclass 21, count 0 2006.231.07:38:19.89#ibcon#*mode == 0, iclass 21, count 0 2006.231.07:38:19.89#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.07:38:19.89#ibcon#[25=USB\r\n] 2006.231.07:38:19.89#ibcon#*before write, iclass 21, count 0 2006.231.07:38:19.89#ibcon#enter sib2, iclass 21, count 0 2006.231.07:38:19.89#ibcon#flushed, iclass 21, count 0 2006.231.07:38:19.89#ibcon#about to write, iclass 21, count 0 2006.231.07:38:19.89#ibcon#wrote, iclass 21, count 0 2006.231.07:38:19.89#ibcon#about to read 3, iclass 21, count 0 2006.231.07:38:19.92#ibcon#read 3, iclass 21, count 0 2006.231.07:38:19.92#ibcon#about to read 4, iclass 21, count 0 2006.231.07:38:19.92#ibcon#read 4, iclass 21, count 0 2006.231.07:38:19.92#ibcon#about to read 5, iclass 21, count 0 2006.231.07:38:19.92#ibcon#read 5, iclass 21, count 0 2006.231.07:38:19.92#ibcon#about to read 6, iclass 21, count 0 2006.231.07:38:19.92#ibcon#read 6, iclass 21, count 0 2006.231.07:38:19.92#ibcon#end of sib2, iclass 21, count 0 2006.231.07:38:19.92#ibcon#*after write, iclass 21, count 0 2006.231.07:38:19.92#ibcon#*before return 0, iclass 21, count 0 2006.231.07:38:19.92#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:38:19.92#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:38:19.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.07:38:19.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.07:38:19.92$vc4f8/valo=7,832.99 2006.231.07:38:19.92#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.231.07:38:19.92#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.231.07:38:19.92#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:19.92#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:38:19.92#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:38:19.92#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:38:19.92#ibcon#enter wrdev, iclass 23, count 0 2006.231.07:38:19.92#ibcon#first serial, iclass 23, count 0 2006.231.07:38:19.92#ibcon#enter sib2, iclass 23, count 0 2006.231.07:38:19.92#ibcon#flushed, iclass 23, count 0 2006.231.07:38:19.92#ibcon#about to write, iclass 23, count 0 2006.231.07:38:19.92#ibcon#wrote, iclass 23, count 0 2006.231.07:38:19.92#ibcon#about to read 3, iclass 23, count 0 2006.231.07:38:19.94#ibcon#read 3, iclass 23, count 0 2006.231.07:38:19.94#ibcon#about to read 4, iclass 23, count 0 2006.231.07:38:19.94#ibcon#read 4, iclass 23, count 0 2006.231.07:38:19.94#ibcon#about to read 5, iclass 23, count 0 2006.231.07:38:19.94#ibcon#read 5, iclass 23, count 0 2006.231.07:38:19.94#ibcon#about to read 6, iclass 23, count 0 2006.231.07:38:19.94#ibcon#read 6, iclass 23, count 0 2006.231.07:38:19.94#ibcon#end of sib2, iclass 23, count 0 2006.231.07:38:19.94#ibcon#*mode == 0, iclass 23, count 0 2006.231.07:38:19.94#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.07:38:19.94#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:38:19.94#ibcon#*before write, iclass 23, count 0 2006.231.07:38:19.94#ibcon#enter sib2, iclass 23, count 0 2006.231.07:38:19.94#ibcon#flushed, iclass 23, count 0 2006.231.07:38:19.94#ibcon#about to write, iclass 23, count 0 2006.231.07:38:19.94#ibcon#wrote, iclass 23, count 0 2006.231.07:38:19.94#ibcon#about to read 3, iclass 23, count 0 2006.231.07:38:19.98#ibcon#read 3, iclass 23, count 0 2006.231.07:38:19.98#ibcon#about to read 4, iclass 23, count 0 2006.231.07:38:19.98#ibcon#read 4, iclass 23, count 0 2006.231.07:38:19.98#ibcon#about to read 5, iclass 23, count 0 2006.231.07:38:19.98#ibcon#read 5, iclass 23, count 0 2006.231.07:38:19.98#ibcon#about to read 6, iclass 23, count 0 2006.231.07:38:19.98#ibcon#read 6, iclass 23, count 0 2006.231.07:38:19.98#ibcon#end of sib2, iclass 23, count 0 2006.231.07:38:19.98#ibcon#*after write, iclass 23, count 0 2006.231.07:38:19.98#ibcon#*before return 0, iclass 23, count 0 2006.231.07:38:19.98#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:38:19.98#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:38:19.98#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.07:38:19.98#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.07:38:19.98$vc4f8/va=7,6 2006.231.07:38:19.98#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.231.07:38:19.98#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.231.07:38:19.98#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:19.98#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:38:20.04#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:38:20.04#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:38:20.04#ibcon#enter wrdev, iclass 25, count 2 2006.231.07:38:20.04#ibcon#first serial, iclass 25, count 2 2006.231.07:38:20.04#ibcon#enter sib2, iclass 25, count 2 2006.231.07:38:20.04#ibcon#flushed, iclass 25, count 2 2006.231.07:38:20.04#ibcon#about to write, iclass 25, count 2 2006.231.07:38:20.04#ibcon#wrote, iclass 25, count 2 2006.231.07:38:20.04#ibcon#about to read 3, iclass 25, count 2 2006.231.07:38:20.06#ibcon#read 3, iclass 25, count 2 2006.231.07:38:20.06#ibcon#about to read 4, iclass 25, count 2 2006.231.07:38:20.06#ibcon#read 4, iclass 25, count 2 2006.231.07:38:20.06#ibcon#about to read 5, iclass 25, count 2 2006.231.07:38:20.06#ibcon#read 5, iclass 25, count 2 2006.231.07:38:20.06#ibcon#about to read 6, iclass 25, count 2 2006.231.07:38:20.06#ibcon#read 6, iclass 25, count 2 2006.231.07:38:20.06#ibcon#end of sib2, iclass 25, count 2 2006.231.07:38:20.06#ibcon#*mode == 0, iclass 25, count 2 2006.231.07:38:20.06#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.231.07:38:20.06#ibcon#[25=AT07-06\r\n] 2006.231.07:38:20.06#ibcon#*before write, iclass 25, count 2 2006.231.07:38:20.06#ibcon#enter sib2, iclass 25, count 2 2006.231.07:38:20.06#ibcon#flushed, iclass 25, count 2 2006.231.07:38:20.06#ibcon#about to write, iclass 25, count 2 2006.231.07:38:20.06#ibcon#wrote, iclass 25, count 2 2006.231.07:38:20.06#ibcon#about to read 3, iclass 25, count 2 2006.231.07:38:20.09#ibcon#read 3, iclass 25, count 2 2006.231.07:38:20.09#ibcon#about to read 4, iclass 25, count 2 2006.231.07:38:20.09#ibcon#read 4, iclass 25, count 2 2006.231.07:38:20.09#ibcon#about to read 5, iclass 25, count 2 2006.231.07:38:20.09#ibcon#read 5, iclass 25, count 2 2006.231.07:38:20.09#ibcon#about to read 6, iclass 25, count 2 2006.231.07:38:20.09#ibcon#read 6, iclass 25, count 2 2006.231.07:38:20.09#ibcon#end of sib2, iclass 25, count 2 2006.231.07:38:20.09#ibcon#*after write, iclass 25, count 2 2006.231.07:38:20.09#ibcon#*before return 0, iclass 25, count 2 2006.231.07:38:20.09#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:38:20.09#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:38:20.09#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.231.07:38:20.09#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:20.09#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:38:20.21#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:38:20.21#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:38:20.21#ibcon#enter wrdev, iclass 25, count 0 2006.231.07:38:20.21#ibcon#first serial, iclass 25, count 0 2006.231.07:38:20.21#ibcon#enter sib2, iclass 25, count 0 2006.231.07:38:20.21#ibcon#flushed, iclass 25, count 0 2006.231.07:38:20.21#ibcon#about to write, iclass 25, count 0 2006.231.07:38:20.21#ibcon#wrote, iclass 25, count 0 2006.231.07:38:20.21#ibcon#about to read 3, iclass 25, count 0 2006.231.07:38:20.23#ibcon#read 3, iclass 25, count 0 2006.231.07:38:20.23#ibcon#about to read 4, iclass 25, count 0 2006.231.07:38:20.23#ibcon#read 4, iclass 25, count 0 2006.231.07:38:20.23#ibcon#about to read 5, iclass 25, count 0 2006.231.07:38:20.23#ibcon#read 5, iclass 25, count 0 2006.231.07:38:20.23#ibcon#about to read 6, iclass 25, count 0 2006.231.07:38:20.23#ibcon#read 6, iclass 25, count 0 2006.231.07:38:20.23#ibcon#end of sib2, iclass 25, count 0 2006.231.07:38:20.23#ibcon#*mode == 0, iclass 25, count 0 2006.231.07:38:20.23#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.07:38:20.23#ibcon#[25=USB\r\n] 2006.231.07:38:20.23#ibcon#*before write, iclass 25, count 0 2006.231.07:38:20.23#ibcon#enter sib2, iclass 25, count 0 2006.231.07:38:20.23#ibcon#flushed, iclass 25, count 0 2006.231.07:38:20.23#ibcon#about to write, iclass 25, count 0 2006.231.07:38:20.23#ibcon#wrote, iclass 25, count 0 2006.231.07:38:20.23#ibcon#about to read 3, iclass 25, count 0 2006.231.07:38:20.26#ibcon#read 3, iclass 25, count 0 2006.231.07:38:20.26#ibcon#about to read 4, iclass 25, count 0 2006.231.07:38:20.26#ibcon#read 4, iclass 25, count 0 2006.231.07:38:20.26#ibcon#about to read 5, iclass 25, count 0 2006.231.07:38:20.26#ibcon#read 5, iclass 25, count 0 2006.231.07:38:20.26#ibcon#about to read 6, iclass 25, count 0 2006.231.07:38:20.26#ibcon#read 6, iclass 25, count 0 2006.231.07:38:20.26#ibcon#end of sib2, iclass 25, count 0 2006.231.07:38:20.26#ibcon#*after write, iclass 25, count 0 2006.231.07:38:20.26#ibcon#*before return 0, iclass 25, count 0 2006.231.07:38:20.26#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:38:20.26#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:38:20.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.07:38:20.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.07:38:20.26$vc4f8/valo=8,852.99 2006.231.07:38:20.26#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.231.07:38:20.26#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.231.07:38:20.26#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:20.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:38:20.26#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:38:20.26#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:38:20.26#ibcon#enter wrdev, iclass 27, count 0 2006.231.07:38:20.26#ibcon#first serial, iclass 27, count 0 2006.231.07:38:20.26#ibcon#enter sib2, iclass 27, count 0 2006.231.07:38:20.26#ibcon#flushed, iclass 27, count 0 2006.231.07:38:20.26#ibcon#about to write, iclass 27, count 0 2006.231.07:38:20.26#ibcon#wrote, iclass 27, count 0 2006.231.07:38:20.26#ibcon#about to read 3, iclass 27, count 0 2006.231.07:38:20.28#ibcon#read 3, iclass 27, count 0 2006.231.07:38:20.28#ibcon#about to read 4, iclass 27, count 0 2006.231.07:38:20.28#ibcon#read 4, iclass 27, count 0 2006.231.07:38:20.28#ibcon#about to read 5, iclass 27, count 0 2006.231.07:38:20.28#ibcon#read 5, iclass 27, count 0 2006.231.07:38:20.28#ibcon#about to read 6, iclass 27, count 0 2006.231.07:38:20.28#ibcon#read 6, iclass 27, count 0 2006.231.07:38:20.28#ibcon#end of sib2, iclass 27, count 0 2006.231.07:38:20.28#ibcon#*mode == 0, iclass 27, count 0 2006.231.07:38:20.28#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.07:38:20.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:38:20.28#ibcon#*before write, iclass 27, count 0 2006.231.07:38:20.28#ibcon#enter sib2, iclass 27, count 0 2006.231.07:38:20.28#ibcon#flushed, iclass 27, count 0 2006.231.07:38:20.28#ibcon#about to write, iclass 27, count 0 2006.231.07:38:20.28#ibcon#wrote, iclass 27, count 0 2006.231.07:38:20.28#ibcon#about to read 3, iclass 27, count 0 2006.231.07:38:20.32#ibcon#read 3, iclass 27, count 0 2006.231.07:38:20.32#ibcon#about to read 4, iclass 27, count 0 2006.231.07:38:20.32#ibcon#read 4, iclass 27, count 0 2006.231.07:38:20.32#ibcon#about to read 5, iclass 27, count 0 2006.231.07:38:20.32#ibcon#read 5, iclass 27, count 0 2006.231.07:38:20.32#ibcon#about to read 6, iclass 27, count 0 2006.231.07:38:20.32#ibcon#read 6, iclass 27, count 0 2006.231.07:38:20.32#ibcon#end of sib2, iclass 27, count 0 2006.231.07:38:20.32#ibcon#*after write, iclass 27, count 0 2006.231.07:38:20.32#ibcon#*before return 0, iclass 27, count 0 2006.231.07:38:20.32#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:38:20.32#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:38:20.32#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.07:38:20.32#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.07:38:20.32$vc4f8/va=8,6 2006.231.07:38:20.32#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.231.07:38:20.32#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.231.07:38:20.32#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:20.32#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:38:20.38#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:38:20.38#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:38:20.38#ibcon#enter wrdev, iclass 29, count 2 2006.231.07:38:20.38#ibcon#first serial, iclass 29, count 2 2006.231.07:38:20.38#ibcon#enter sib2, iclass 29, count 2 2006.231.07:38:20.38#ibcon#flushed, iclass 29, count 2 2006.231.07:38:20.38#ibcon#about to write, iclass 29, count 2 2006.231.07:38:20.38#ibcon#wrote, iclass 29, count 2 2006.231.07:38:20.38#ibcon#about to read 3, iclass 29, count 2 2006.231.07:38:20.40#ibcon#read 3, iclass 29, count 2 2006.231.07:38:20.40#ibcon#about to read 4, iclass 29, count 2 2006.231.07:38:20.40#ibcon#read 4, iclass 29, count 2 2006.231.07:38:20.40#ibcon#about to read 5, iclass 29, count 2 2006.231.07:38:20.40#ibcon#read 5, iclass 29, count 2 2006.231.07:38:20.40#ibcon#about to read 6, iclass 29, count 2 2006.231.07:38:20.40#ibcon#read 6, iclass 29, count 2 2006.231.07:38:20.40#ibcon#end of sib2, iclass 29, count 2 2006.231.07:38:20.40#ibcon#*mode == 0, iclass 29, count 2 2006.231.07:38:20.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.231.07:38:20.40#ibcon#[25=AT08-06\r\n] 2006.231.07:38:20.40#ibcon#*before write, iclass 29, count 2 2006.231.07:38:20.40#ibcon#enter sib2, iclass 29, count 2 2006.231.07:38:20.40#ibcon#flushed, iclass 29, count 2 2006.231.07:38:20.40#ibcon#about to write, iclass 29, count 2 2006.231.07:38:20.40#ibcon#wrote, iclass 29, count 2 2006.231.07:38:20.40#ibcon#about to read 3, iclass 29, count 2 2006.231.07:38:20.44#ibcon#read 3, iclass 29, count 2 2006.231.07:38:20.44#ibcon#about to read 4, iclass 29, count 2 2006.231.07:38:20.44#ibcon#read 4, iclass 29, count 2 2006.231.07:38:20.44#ibcon#about to read 5, iclass 29, count 2 2006.231.07:38:20.44#ibcon#read 5, iclass 29, count 2 2006.231.07:38:20.44#ibcon#about to read 6, iclass 29, count 2 2006.231.07:38:20.44#ibcon#read 6, iclass 29, count 2 2006.231.07:38:20.44#ibcon#end of sib2, iclass 29, count 2 2006.231.07:38:20.44#ibcon#*after write, iclass 29, count 2 2006.231.07:38:20.44#ibcon#*before return 0, iclass 29, count 2 2006.231.07:38:20.44#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:38:20.44#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:38:20.44#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.231.07:38:20.44#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:20.44#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:38:20.56#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:38:20.56#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:38:20.56#ibcon#enter wrdev, iclass 29, count 0 2006.231.07:38:20.56#ibcon#first serial, iclass 29, count 0 2006.231.07:38:20.56#ibcon#enter sib2, iclass 29, count 0 2006.231.07:38:20.56#ibcon#flushed, iclass 29, count 0 2006.231.07:38:20.56#ibcon#about to write, iclass 29, count 0 2006.231.07:38:20.56#ibcon#wrote, iclass 29, count 0 2006.231.07:38:20.56#ibcon#about to read 3, iclass 29, count 0 2006.231.07:38:20.57#ibcon#read 3, iclass 29, count 0 2006.231.07:38:20.57#ibcon#about to read 4, iclass 29, count 0 2006.231.07:38:20.57#ibcon#read 4, iclass 29, count 0 2006.231.07:38:20.57#ibcon#about to read 5, iclass 29, count 0 2006.231.07:38:20.57#ibcon#read 5, iclass 29, count 0 2006.231.07:38:20.57#ibcon#about to read 6, iclass 29, count 0 2006.231.07:38:20.57#ibcon#read 6, iclass 29, count 0 2006.231.07:38:20.57#ibcon#end of sib2, iclass 29, count 0 2006.231.07:38:20.57#ibcon#*mode == 0, iclass 29, count 0 2006.231.07:38:20.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.07:38:20.57#ibcon#[25=USB\r\n] 2006.231.07:38:20.57#ibcon#*before write, iclass 29, count 0 2006.231.07:38:20.57#ibcon#enter sib2, iclass 29, count 0 2006.231.07:38:20.57#ibcon#flushed, iclass 29, count 0 2006.231.07:38:20.57#ibcon#about to write, iclass 29, count 0 2006.231.07:38:20.57#ibcon#wrote, iclass 29, count 0 2006.231.07:38:20.57#ibcon#about to read 3, iclass 29, count 0 2006.231.07:38:20.60#ibcon#read 3, iclass 29, count 0 2006.231.07:38:20.60#ibcon#about to read 4, iclass 29, count 0 2006.231.07:38:20.60#ibcon#read 4, iclass 29, count 0 2006.231.07:38:20.60#ibcon#about to read 5, iclass 29, count 0 2006.231.07:38:20.60#ibcon#read 5, iclass 29, count 0 2006.231.07:38:20.60#ibcon#about to read 6, iclass 29, count 0 2006.231.07:38:20.60#ibcon#read 6, iclass 29, count 0 2006.231.07:38:20.60#ibcon#end of sib2, iclass 29, count 0 2006.231.07:38:20.60#ibcon#*after write, iclass 29, count 0 2006.231.07:38:20.60#ibcon#*before return 0, iclass 29, count 0 2006.231.07:38:20.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:38:20.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:38:20.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.07:38:20.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.07:38:20.60$vc4f8/vblo=1,632.99 2006.231.07:38:20.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.231.07:38:20.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.231.07:38:20.60#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:20.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:38:20.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:38:20.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:38:20.60#ibcon#enter wrdev, iclass 31, count 0 2006.231.07:38:20.60#ibcon#first serial, iclass 31, count 0 2006.231.07:38:20.60#ibcon#enter sib2, iclass 31, count 0 2006.231.07:38:20.60#ibcon#flushed, iclass 31, count 0 2006.231.07:38:20.60#ibcon#about to write, iclass 31, count 0 2006.231.07:38:20.60#ibcon#wrote, iclass 31, count 0 2006.231.07:38:20.60#ibcon#about to read 3, iclass 31, count 0 2006.231.07:38:20.62#ibcon#read 3, iclass 31, count 0 2006.231.07:38:20.62#ibcon#about to read 4, iclass 31, count 0 2006.231.07:38:20.62#ibcon#read 4, iclass 31, count 0 2006.231.07:38:20.62#ibcon#about to read 5, iclass 31, count 0 2006.231.07:38:20.62#ibcon#read 5, iclass 31, count 0 2006.231.07:38:20.62#ibcon#about to read 6, iclass 31, count 0 2006.231.07:38:20.62#ibcon#read 6, iclass 31, count 0 2006.231.07:38:20.62#ibcon#end of sib2, iclass 31, count 0 2006.231.07:38:20.62#ibcon#*mode == 0, iclass 31, count 0 2006.231.07:38:20.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.07:38:20.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:38:20.62#ibcon#*before write, iclass 31, count 0 2006.231.07:38:20.62#ibcon#enter sib2, iclass 31, count 0 2006.231.07:38:20.62#ibcon#flushed, iclass 31, count 0 2006.231.07:38:20.62#ibcon#about to write, iclass 31, count 0 2006.231.07:38:20.62#ibcon#wrote, iclass 31, count 0 2006.231.07:38:20.62#ibcon#about to read 3, iclass 31, count 0 2006.231.07:38:20.66#ibcon#read 3, iclass 31, count 0 2006.231.07:38:20.66#ibcon#about to read 4, iclass 31, count 0 2006.231.07:38:20.66#ibcon#read 4, iclass 31, count 0 2006.231.07:38:20.66#ibcon#about to read 5, iclass 31, count 0 2006.231.07:38:20.66#ibcon#read 5, iclass 31, count 0 2006.231.07:38:20.66#ibcon#about to read 6, iclass 31, count 0 2006.231.07:38:20.66#ibcon#read 6, iclass 31, count 0 2006.231.07:38:20.66#ibcon#end of sib2, iclass 31, count 0 2006.231.07:38:20.66#ibcon#*after write, iclass 31, count 0 2006.231.07:38:20.66#ibcon#*before return 0, iclass 31, count 0 2006.231.07:38:20.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:38:20.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:38:20.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.07:38:20.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.07:38:20.66$vc4f8/vb=1,4 2006.231.07:38:20.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.231.07:38:20.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.231.07:38:20.66#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:20.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:38:20.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:38:20.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:38:20.66#ibcon#enter wrdev, iclass 33, count 2 2006.231.07:38:20.66#ibcon#first serial, iclass 33, count 2 2006.231.07:38:20.66#ibcon#enter sib2, iclass 33, count 2 2006.231.07:38:20.66#ibcon#flushed, iclass 33, count 2 2006.231.07:38:20.66#ibcon#about to write, iclass 33, count 2 2006.231.07:38:20.66#ibcon#wrote, iclass 33, count 2 2006.231.07:38:20.66#ibcon#about to read 3, iclass 33, count 2 2006.231.07:38:20.68#ibcon#read 3, iclass 33, count 2 2006.231.07:38:20.68#ibcon#about to read 4, iclass 33, count 2 2006.231.07:38:20.68#ibcon#read 4, iclass 33, count 2 2006.231.07:38:20.68#ibcon#about to read 5, iclass 33, count 2 2006.231.07:38:20.68#ibcon#read 5, iclass 33, count 2 2006.231.07:38:20.68#ibcon#about to read 6, iclass 33, count 2 2006.231.07:38:20.68#ibcon#read 6, iclass 33, count 2 2006.231.07:38:20.68#ibcon#end of sib2, iclass 33, count 2 2006.231.07:38:20.68#ibcon#*mode == 0, iclass 33, count 2 2006.231.07:38:20.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.231.07:38:20.68#ibcon#[27=AT01-04\r\n] 2006.231.07:38:20.68#ibcon#*before write, iclass 33, count 2 2006.231.07:38:20.68#ibcon#enter sib2, iclass 33, count 2 2006.231.07:38:20.68#ibcon#flushed, iclass 33, count 2 2006.231.07:38:20.68#ibcon#about to write, iclass 33, count 2 2006.231.07:38:20.68#ibcon#wrote, iclass 33, count 2 2006.231.07:38:20.68#ibcon#about to read 3, iclass 33, count 2 2006.231.07:38:20.71#ibcon#read 3, iclass 33, count 2 2006.231.07:38:20.71#ibcon#about to read 4, iclass 33, count 2 2006.231.07:38:20.71#ibcon#read 4, iclass 33, count 2 2006.231.07:38:20.71#ibcon#about to read 5, iclass 33, count 2 2006.231.07:38:20.71#ibcon#read 5, iclass 33, count 2 2006.231.07:38:20.71#ibcon#about to read 6, iclass 33, count 2 2006.231.07:38:20.71#ibcon#read 6, iclass 33, count 2 2006.231.07:38:20.71#ibcon#end of sib2, iclass 33, count 2 2006.231.07:38:20.71#ibcon#*after write, iclass 33, count 2 2006.231.07:38:20.71#ibcon#*before return 0, iclass 33, count 2 2006.231.07:38:20.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:38:20.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:38:20.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.231.07:38:20.71#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:20.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:38:20.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:38:20.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:38:20.83#ibcon#enter wrdev, iclass 33, count 0 2006.231.07:38:20.83#ibcon#first serial, iclass 33, count 0 2006.231.07:38:20.83#ibcon#enter sib2, iclass 33, count 0 2006.231.07:38:20.83#ibcon#flushed, iclass 33, count 0 2006.231.07:38:20.83#ibcon#about to write, iclass 33, count 0 2006.231.07:38:20.83#ibcon#wrote, iclass 33, count 0 2006.231.07:38:20.83#ibcon#about to read 3, iclass 33, count 0 2006.231.07:38:20.85#ibcon#read 3, iclass 33, count 0 2006.231.07:38:20.85#ibcon#about to read 4, iclass 33, count 0 2006.231.07:38:20.85#ibcon#read 4, iclass 33, count 0 2006.231.07:38:20.85#ibcon#about to read 5, iclass 33, count 0 2006.231.07:38:20.85#ibcon#read 5, iclass 33, count 0 2006.231.07:38:20.85#ibcon#about to read 6, iclass 33, count 0 2006.231.07:38:20.85#ibcon#read 6, iclass 33, count 0 2006.231.07:38:20.85#ibcon#end of sib2, iclass 33, count 0 2006.231.07:38:20.85#ibcon#*mode == 0, iclass 33, count 0 2006.231.07:38:20.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.07:38:20.85#ibcon#[27=USB\r\n] 2006.231.07:38:20.85#ibcon#*before write, iclass 33, count 0 2006.231.07:38:20.85#ibcon#enter sib2, iclass 33, count 0 2006.231.07:38:20.85#ibcon#flushed, iclass 33, count 0 2006.231.07:38:20.85#ibcon#about to write, iclass 33, count 0 2006.231.07:38:20.85#ibcon#wrote, iclass 33, count 0 2006.231.07:38:20.85#ibcon#about to read 3, iclass 33, count 0 2006.231.07:38:20.88#ibcon#read 3, iclass 33, count 0 2006.231.07:38:20.88#ibcon#about to read 4, iclass 33, count 0 2006.231.07:38:20.88#ibcon#read 4, iclass 33, count 0 2006.231.07:38:20.88#ibcon#about to read 5, iclass 33, count 0 2006.231.07:38:20.88#ibcon#read 5, iclass 33, count 0 2006.231.07:38:20.88#ibcon#about to read 6, iclass 33, count 0 2006.231.07:38:20.88#ibcon#read 6, iclass 33, count 0 2006.231.07:38:20.88#ibcon#end of sib2, iclass 33, count 0 2006.231.07:38:20.88#ibcon#*after write, iclass 33, count 0 2006.231.07:38:20.88#ibcon#*before return 0, iclass 33, count 0 2006.231.07:38:20.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:38:20.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:38:20.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.07:38:20.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.07:38:20.88$vc4f8/vblo=2,640.99 2006.231.07:38:20.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.231.07:38:20.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.231.07:38:20.88#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:20.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:38:20.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:38:20.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:38:20.88#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:38:20.88#ibcon#first serial, iclass 35, count 0 2006.231.07:38:20.88#ibcon#enter sib2, iclass 35, count 0 2006.231.07:38:20.88#ibcon#flushed, iclass 35, count 0 2006.231.07:38:20.88#ibcon#about to write, iclass 35, count 0 2006.231.07:38:20.88#ibcon#wrote, iclass 35, count 0 2006.231.07:38:20.88#ibcon#about to read 3, iclass 35, count 0 2006.231.07:38:20.90#ibcon#read 3, iclass 35, count 0 2006.231.07:38:20.90#ibcon#about to read 4, iclass 35, count 0 2006.231.07:38:20.90#ibcon#read 4, iclass 35, count 0 2006.231.07:38:20.90#ibcon#about to read 5, iclass 35, count 0 2006.231.07:38:20.90#ibcon#read 5, iclass 35, count 0 2006.231.07:38:20.90#ibcon#about to read 6, iclass 35, count 0 2006.231.07:38:20.90#ibcon#read 6, iclass 35, count 0 2006.231.07:38:20.90#ibcon#end of sib2, iclass 35, count 0 2006.231.07:38:20.90#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:38:20.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:38:20.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:38:20.90#ibcon#*before write, iclass 35, count 0 2006.231.07:38:20.90#ibcon#enter sib2, iclass 35, count 0 2006.231.07:38:20.90#ibcon#flushed, iclass 35, count 0 2006.231.07:38:20.90#ibcon#about to write, iclass 35, count 0 2006.231.07:38:20.90#ibcon#wrote, iclass 35, count 0 2006.231.07:38:20.90#ibcon#about to read 3, iclass 35, count 0 2006.231.07:38:20.94#ibcon#read 3, iclass 35, count 0 2006.231.07:38:20.94#ibcon#about to read 4, iclass 35, count 0 2006.231.07:38:20.94#ibcon#read 4, iclass 35, count 0 2006.231.07:38:20.94#ibcon#about to read 5, iclass 35, count 0 2006.231.07:38:20.94#ibcon#read 5, iclass 35, count 0 2006.231.07:38:20.94#ibcon#about to read 6, iclass 35, count 0 2006.231.07:38:20.94#ibcon#read 6, iclass 35, count 0 2006.231.07:38:20.94#ibcon#end of sib2, iclass 35, count 0 2006.231.07:38:20.94#ibcon#*after write, iclass 35, count 0 2006.231.07:38:20.94#ibcon#*before return 0, iclass 35, count 0 2006.231.07:38:20.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:38:20.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:38:20.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:38:20.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:38:20.94$vc4f8/vb=2,4 2006.231.07:38:20.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.231.07:38:20.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.231.07:38:20.94#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:20.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:38:21.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:38:21.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:38:21.00#ibcon#enter wrdev, iclass 37, count 2 2006.231.07:38:21.00#ibcon#first serial, iclass 37, count 2 2006.231.07:38:21.00#ibcon#enter sib2, iclass 37, count 2 2006.231.07:38:21.00#ibcon#flushed, iclass 37, count 2 2006.231.07:38:21.00#ibcon#about to write, iclass 37, count 2 2006.231.07:38:21.00#ibcon#wrote, iclass 37, count 2 2006.231.07:38:21.00#ibcon#about to read 3, iclass 37, count 2 2006.231.07:38:21.02#ibcon#read 3, iclass 37, count 2 2006.231.07:38:21.02#ibcon#about to read 4, iclass 37, count 2 2006.231.07:38:21.02#ibcon#read 4, iclass 37, count 2 2006.231.07:38:21.02#ibcon#about to read 5, iclass 37, count 2 2006.231.07:38:21.02#ibcon#read 5, iclass 37, count 2 2006.231.07:38:21.02#ibcon#about to read 6, iclass 37, count 2 2006.231.07:38:21.02#ibcon#read 6, iclass 37, count 2 2006.231.07:38:21.02#ibcon#end of sib2, iclass 37, count 2 2006.231.07:38:21.02#ibcon#*mode == 0, iclass 37, count 2 2006.231.07:38:21.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.231.07:38:21.02#ibcon#[27=AT02-04\r\n] 2006.231.07:38:21.02#ibcon#*before write, iclass 37, count 2 2006.231.07:38:21.02#ibcon#enter sib2, iclass 37, count 2 2006.231.07:38:21.02#ibcon#flushed, iclass 37, count 2 2006.231.07:38:21.02#ibcon#about to write, iclass 37, count 2 2006.231.07:38:21.02#ibcon#wrote, iclass 37, count 2 2006.231.07:38:21.02#ibcon#about to read 3, iclass 37, count 2 2006.231.07:38:21.05#ibcon#read 3, iclass 37, count 2 2006.231.07:38:21.05#ibcon#about to read 4, iclass 37, count 2 2006.231.07:38:21.05#ibcon#read 4, iclass 37, count 2 2006.231.07:38:21.05#ibcon#about to read 5, iclass 37, count 2 2006.231.07:38:21.05#ibcon#read 5, iclass 37, count 2 2006.231.07:38:21.05#ibcon#about to read 6, iclass 37, count 2 2006.231.07:38:21.05#ibcon#read 6, iclass 37, count 2 2006.231.07:38:21.05#ibcon#end of sib2, iclass 37, count 2 2006.231.07:38:21.05#ibcon#*after write, iclass 37, count 2 2006.231.07:38:21.05#ibcon#*before return 0, iclass 37, count 2 2006.231.07:38:21.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:38:21.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:38:21.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.231.07:38:21.05#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:21.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:38:21.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:38:21.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:38:21.17#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:38:21.17#ibcon#first serial, iclass 37, count 0 2006.231.07:38:21.17#ibcon#enter sib2, iclass 37, count 0 2006.231.07:38:21.17#ibcon#flushed, iclass 37, count 0 2006.231.07:38:21.17#ibcon#about to write, iclass 37, count 0 2006.231.07:38:21.17#ibcon#wrote, iclass 37, count 0 2006.231.07:38:21.17#ibcon#about to read 3, iclass 37, count 0 2006.231.07:38:21.19#ibcon#read 3, iclass 37, count 0 2006.231.07:38:21.19#ibcon#about to read 4, iclass 37, count 0 2006.231.07:38:21.19#ibcon#read 4, iclass 37, count 0 2006.231.07:38:21.19#ibcon#about to read 5, iclass 37, count 0 2006.231.07:38:21.19#ibcon#read 5, iclass 37, count 0 2006.231.07:38:21.19#ibcon#about to read 6, iclass 37, count 0 2006.231.07:38:21.19#ibcon#read 6, iclass 37, count 0 2006.231.07:38:21.19#ibcon#end of sib2, iclass 37, count 0 2006.231.07:38:21.19#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:38:21.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:38:21.19#ibcon#[27=USB\r\n] 2006.231.07:38:21.19#ibcon#*before write, iclass 37, count 0 2006.231.07:38:21.19#ibcon#enter sib2, iclass 37, count 0 2006.231.07:38:21.19#ibcon#flushed, iclass 37, count 0 2006.231.07:38:21.19#ibcon#about to write, iclass 37, count 0 2006.231.07:38:21.19#ibcon#wrote, iclass 37, count 0 2006.231.07:38:21.19#ibcon#about to read 3, iclass 37, count 0 2006.231.07:38:21.22#ibcon#read 3, iclass 37, count 0 2006.231.07:38:21.22#ibcon#about to read 4, iclass 37, count 0 2006.231.07:38:21.22#ibcon#read 4, iclass 37, count 0 2006.231.07:38:21.22#ibcon#about to read 5, iclass 37, count 0 2006.231.07:38:21.22#ibcon#read 5, iclass 37, count 0 2006.231.07:38:21.22#ibcon#about to read 6, iclass 37, count 0 2006.231.07:38:21.22#ibcon#read 6, iclass 37, count 0 2006.231.07:38:21.22#ibcon#end of sib2, iclass 37, count 0 2006.231.07:38:21.22#ibcon#*after write, iclass 37, count 0 2006.231.07:38:21.22#ibcon#*before return 0, iclass 37, count 0 2006.231.07:38:21.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:38:21.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:38:21.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:38:21.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:38:21.23$vc4f8/vblo=3,656.99 2006.231.07:38:21.23#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.07:38:21.23#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.07:38:21.23#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:21.23#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:38:21.23#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:38:21.23#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:38:21.23#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:38:21.23#ibcon#first serial, iclass 39, count 0 2006.231.07:38:21.23#ibcon#enter sib2, iclass 39, count 0 2006.231.07:38:21.23#ibcon#flushed, iclass 39, count 0 2006.231.07:38:21.23#ibcon#about to write, iclass 39, count 0 2006.231.07:38:21.23#ibcon#wrote, iclass 39, count 0 2006.231.07:38:21.23#ibcon#about to read 3, iclass 39, count 0 2006.231.07:38:21.24#ibcon#read 3, iclass 39, count 0 2006.231.07:38:21.24#ibcon#about to read 4, iclass 39, count 0 2006.231.07:38:21.24#ibcon#read 4, iclass 39, count 0 2006.231.07:38:21.24#ibcon#about to read 5, iclass 39, count 0 2006.231.07:38:21.24#ibcon#read 5, iclass 39, count 0 2006.231.07:38:21.24#ibcon#about to read 6, iclass 39, count 0 2006.231.07:38:21.24#ibcon#read 6, iclass 39, count 0 2006.231.07:38:21.24#ibcon#end of sib2, iclass 39, count 0 2006.231.07:38:21.24#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:38:21.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:38:21.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:38:21.24#ibcon#*before write, iclass 39, count 0 2006.231.07:38:21.24#ibcon#enter sib2, iclass 39, count 0 2006.231.07:38:21.24#ibcon#flushed, iclass 39, count 0 2006.231.07:38:21.24#ibcon#about to write, iclass 39, count 0 2006.231.07:38:21.24#ibcon#wrote, iclass 39, count 0 2006.231.07:38:21.24#ibcon#about to read 3, iclass 39, count 0 2006.231.07:38:21.28#ibcon#read 3, iclass 39, count 0 2006.231.07:38:21.28#ibcon#about to read 4, iclass 39, count 0 2006.231.07:38:21.28#ibcon#read 4, iclass 39, count 0 2006.231.07:38:21.28#ibcon#about to read 5, iclass 39, count 0 2006.231.07:38:21.28#ibcon#read 5, iclass 39, count 0 2006.231.07:38:21.28#ibcon#about to read 6, iclass 39, count 0 2006.231.07:38:21.28#ibcon#read 6, iclass 39, count 0 2006.231.07:38:21.28#ibcon#end of sib2, iclass 39, count 0 2006.231.07:38:21.28#ibcon#*after write, iclass 39, count 0 2006.231.07:38:21.28#ibcon#*before return 0, iclass 39, count 0 2006.231.07:38:21.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:38:21.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:38:21.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:38:21.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:38:21.28$vc4f8/vb=3,4 2006.231.07:38:21.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.231.07:38:21.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.231.07:38:21.28#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:21.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:38:21.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:38:21.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:38:21.34#ibcon#enter wrdev, iclass 3, count 2 2006.231.07:38:21.34#ibcon#first serial, iclass 3, count 2 2006.231.07:38:21.34#ibcon#enter sib2, iclass 3, count 2 2006.231.07:38:21.34#ibcon#flushed, iclass 3, count 2 2006.231.07:38:21.34#ibcon#about to write, iclass 3, count 2 2006.231.07:38:21.34#ibcon#wrote, iclass 3, count 2 2006.231.07:38:21.34#ibcon#about to read 3, iclass 3, count 2 2006.231.07:38:21.36#ibcon#read 3, iclass 3, count 2 2006.231.07:38:21.36#ibcon#about to read 4, iclass 3, count 2 2006.231.07:38:21.36#ibcon#read 4, iclass 3, count 2 2006.231.07:38:21.36#ibcon#about to read 5, iclass 3, count 2 2006.231.07:38:21.36#ibcon#read 5, iclass 3, count 2 2006.231.07:38:21.36#ibcon#about to read 6, iclass 3, count 2 2006.231.07:38:21.36#ibcon#read 6, iclass 3, count 2 2006.231.07:38:21.36#ibcon#end of sib2, iclass 3, count 2 2006.231.07:38:21.36#ibcon#*mode == 0, iclass 3, count 2 2006.231.07:38:21.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.231.07:38:21.36#ibcon#[27=AT03-04\r\n] 2006.231.07:38:21.36#ibcon#*before write, iclass 3, count 2 2006.231.07:38:21.36#ibcon#enter sib2, iclass 3, count 2 2006.231.07:38:21.36#ibcon#flushed, iclass 3, count 2 2006.231.07:38:21.36#ibcon#about to write, iclass 3, count 2 2006.231.07:38:21.36#ibcon#wrote, iclass 3, count 2 2006.231.07:38:21.36#ibcon#about to read 3, iclass 3, count 2 2006.231.07:38:21.39#ibcon#read 3, iclass 3, count 2 2006.231.07:38:21.39#ibcon#about to read 4, iclass 3, count 2 2006.231.07:38:21.39#ibcon#read 4, iclass 3, count 2 2006.231.07:38:21.39#ibcon#about to read 5, iclass 3, count 2 2006.231.07:38:21.39#ibcon#read 5, iclass 3, count 2 2006.231.07:38:21.39#ibcon#about to read 6, iclass 3, count 2 2006.231.07:38:21.39#ibcon#read 6, iclass 3, count 2 2006.231.07:38:21.39#ibcon#end of sib2, iclass 3, count 2 2006.231.07:38:21.39#ibcon#*after write, iclass 3, count 2 2006.231.07:38:21.39#ibcon#*before return 0, iclass 3, count 2 2006.231.07:38:21.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:38:21.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:38:21.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.231.07:38:21.39#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:21.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:38:21.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:38:21.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:38:21.51#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:38:21.51#ibcon#first serial, iclass 3, count 0 2006.231.07:38:21.51#ibcon#enter sib2, iclass 3, count 0 2006.231.07:38:21.51#ibcon#flushed, iclass 3, count 0 2006.231.07:38:21.51#ibcon#about to write, iclass 3, count 0 2006.231.07:38:21.51#ibcon#wrote, iclass 3, count 0 2006.231.07:38:21.51#ibcon#about to read 3, iclass 3, count 0 2006.231.07:38:21.53#ibcon#read 3, iclass 3, count 0 2006.231.07:38:21.53#ibcon#about to read 4, iclass 3, count 0 2006.231.07:38:21.53#ibcon#read 4, iclass 3, count 0 2006.231.07:38:21.53#ibcon#about to read 5, iclass 3, count 0 2006.231.07:38:21.53#ibcon#read 5, iclass 3, count 0 2006.231.07:38:21.53#ibcon#about to read 6, iclass 3, count 0 2006.231.07:38:21.53#ibcon#read 6, iclass 3, count 0 2006.231.07:38:21.53#ibcon#end of sib2, iclass 3, count 0 2006.231.07:38:21.53#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:38:21.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:38:21.53#ibcon#[27=USB\r\n] 2006.231.07:38:21.53#ibcon#*before write, iclass 3, count 0 2006.231.07:38:21.53#ibcon#enter sib2, iclass 3, count 0 2006.231.07:38:21.53#ibcon#flushed, iclass 3, count 0 2006.231.07:38:21.53#ibcon#about to write, iclass 3, count 0 2006.231.07:38:21.53#ibcon#wrote, iclass 3, count 0 2006.231.07:38:21.53#ibcon#about to read 3, iclass 3, count 0 2006.231.07:38:21.56#ibcon#read 3, iclass 3, count 0 2006.231.07:38:21.56#ibcon#about to read 4, iclass 3, count 0 2006.231.07:38:21.56#ibcon#read 4, iclass 3, count 0 2006.231.07:38:21.56#ibcon#about to read 5, iclass 3, count 0 2006.231.07:38:21.56#ibcon#read 5, iclass 3, count 0 2006.231.07:38:21.56#ibcon#about to read 6, iclass 3, count 0 2006.231.07:38:21.56#ibcon#read 6, iclass 3, count 0 2006.231.07:38:21.56#ibcon#end of sib2, iclass 3, count 0 2006.231.07:38:21.56#ibcon#*after write, iclass 3, count 0 2006.231.07:38:21.56#ibcon#*before return 0, iclass 3, count 0 2006.231.07:38:21.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:38:21.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:38:21.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:38:21.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:38:21.56$vc4f8/vblo=4,712.99 2006.231.07:38:21.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.231.07:38:21.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.231.07:38:21.56#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:21.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:38:21.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:38:21.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:38:21.56#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:38:21.56#ibcon#first serial, iclass 5, count 0 2006.231.07:38:21.56#ibcon#enter sib2, iclass 5, count 0 2006.231.07:38:21.56#ibcon#flushed, iclass 5, count 0 2006.231.07:38:21.56#ibcon#about to write, iclass 5, count 0 2006.231.07:38:21.56#ibcon#wrote, iclass 5, count 0 2006.231.07:38:21.56#ibcon#about to read 3, iclass 5, count 0 2006.231.07:38:21.58#ibcon#read 3, iclass 5, count 0 2006.231.07:38:21.58#ibcon#about to read 4, iclass 5, count 0 2006.231.07:38:21.58#ibcon#read 4, iclass 5, count 0 2006.231.07:38:21.58#ibcon#about to read 5, iclass 5, count 0 2006.231.07:38:21.58#ibcon#read 5, iclass 5, count 0 2006.231.07:38:21.58#ibcon#about to read 6, iclass 5, count 0 2006.231.07:38:21.58#ibcon#read 6, iclass 5, count 0 2006.231.07:38:21.58#ibcon#end of sib2, iclass 5, count 0 2006.231.07:38:21.58#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:38:21.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:38:21.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:38:21.58#ibcon#*before write, iclass 5, count 0 2006.231.07:38:21.58#ibcon#enter sib2, iclass 5, count 0 2006.231.07:38:21.58#ibcon#flushed, iclass 5, count 0 2006.231.07:38:21.58#ibcon#about to write, iclass 5, count 0 2006.231.07:38:21.58#ibcon#wrote, iclass 5, count 0 2006.231.07:38:21.58#ibcon#about to read 3, iclass 5, count 0 2006.231.07:38:21.62#ibcon#read 3, iclass 5, count 0 2006.231.07:38:21.62#ibcon#about to read 4, iclass 5, count 0 2006.231.07:38:21.62#ibcon#read 4, iclass 5, count 0 2006.231.07:38:21.62#ibcon#about to read 5, iclass 5, count 0 2006.231.07:38:21.62#ibcon#read 5, iclass 5, count 0 2006.231.07:38:21.62#ibcon#about to read 6, iclass 5, count 0 2006.231.07:38:21.62#ibcon#read 6, iclass 5, count 0 2006.231.07:38:21.62#ibcon#end of sib2, iclass 5, count 0 2006.231.07:38:21.62#ibcon#*after write, iclass 5, count 0 2006.231.07:38:21.62#ibcon#*before return 0, iclass 5, count 0 2006.231.07:38:21.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:38:21.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:38:21.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:38:21.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:38:21.62$vc4f8/vb=4,4 2006.231.07:38:21.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.231.07:38:21.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.231.07:38:21.62#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:21.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:38:21.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:38:21.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:38:21.68#ibcon#enter wrdev, iclass 7, count 2 2006.231.07:38:21.68#ibcon#first serial, iclass 7, count 2 2006.231.07:38:21.68#ibcon#enter sib2, iclass 7, count 2 2006.231.07:38:21.68#ibcon#flushed, iclass 7, count 2 2006.231.07:38:21.68#ibcon#about to write, iclass 7, count 2 2006.231.07:38:21.68#ibcon#wrote, iclass 7, count 2 2006.231.07:38:21.68#ibcon#about to read 3, iclass 7, count 2 2006.231.07:38:21.70#ibcon#read 3, iclass 7, count 2 2006.231.07:38:21.70#ibcon#about to read 4, iclass 7, count 2 2006.231.07:38:21.70#ibcon#read 4, iclass 7, count 2 2006.231.07:38:21.70#ibcon#about to read 5, iclass 7, count 2 2006.231.07:38:21.70#ibcon#read 5, iclass 7, count 2 2006.231.07:38:21.70#ibcon#about to read 6, iclass 7, count 2 2006.231.07:38:21.70#ibcon#read 6, iclass 7, count 2 2006.231.07:38:21.70#ibcon#end of sib2, iclass 7, count 2 2006.231.07:38:21.70#ibcon#*mode == 0, iclass 7, count 2 2006.231.07:38:21.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.231.07:38:21.70#ibcon#[27=AT04-04\r\n] 2006.231.07:38:21.70#ibcon#*before write, iclass 7, count 2 2006.231.07:38:21.70#ibcon#enter sib2, iclass 7, count 2 2006.231.07:38:21.70#ibcon#flushed, iclass 7, count 2 2006.231.07:38:21.70#ibcon#about to write, iclass 7, count 2 2006.231.07:38:21.70#ibcon#wrote, iclass 7, count 2 2006.231.07:38:21.70#ibcon#about to read 3, iclass 7, count 2 2006.231.07:38:21.73#ibcon#read 3, iclass 7, count 2 2006.231.07:38:21.73#ibcon#about to read 4, iclass 7, count 2 2006.231.07:38:21.73#ibcon#read 4, iclass 7, count 2 2006.231.07:38:21.73#ibcon#about to read 5, iclass 7, count 2 2006.231.07:38:21.73#ibcon#read 5, iclass 7, count 2 2006.231.07:38:21.73#ibcon#about to read 6, iclass 7, count 2 2006.231.07:38:21.73#ibcon#read 6, iclass 7, count 2 2006.231.07:38:21.73#ibcon#end of sib2, iclass 7, count 2 2006.231.07:38:21.73#ibcon#*after write, iclass 7, count 2 2006.231.07:38:21.73#ibcon#*before return 0, iclass 7, count 2 2006.231.07:38:21.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:38:21.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:38:21.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.231.07:38:21.73#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:21.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:38:21.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:38:21.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:38:21.85#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:38:21.85#ibcon#first serial, iclass 7, count 0 2006.231.07:38:21.85#ibcon#enter sib2, iclass 7, count 0 2006.231.07:38:21.85#ibcon#flushed, iclass 7, count 0 2006.231.07:38:21.85#ibcon#about to write, iclass 7, count 0 2006.231.07:38:21.85#ibcon#wrote, iclass 7, count 0 2006.231.07:38:21.85#ibcon#about to read 3, iclass 7, count 0 2006.231.07:38:21.87#ibcon#read 3, iclass 7, count 0 2006.231.07:38:21.87#ibcon#about to read 4, iclass 7, count 0 2006.231.07:38:21.87#ibcon#read 4, iclass 7, count 0 2006.231.07:38:21.87#ibcon#about to read 5, iclass 7, count 0 2006.231.07:38:21.87#ibcon#read 5, iclass 7, count 0 2006.231.07:38:21.87#ibcon#about to read 6, iclass 7, count 0 2006.231.07:38:21.87#ibcon#read 6, iclass 7, count 0 2006.231.07:38:21.87#ibcon#end of sib2, iclass 7, count 0 2006.231.07:38:21.87#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:38:21.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:38:21.87#ibcon#[27=USB\r\n] 2006.231.07:38:21.87#ibcon#*before write, iclass 7, count 0 2006.231.07:38:21.87#ibcon#enter sib2, iclass 7, count 0 2006.231.07:38:21.87#ibcon#flushed, iclass 7, count 0 2006.231.07:38:21.87#ibcon#about to write, iclass 7, count 0 2006.231.07:38:21.87#ibcon#wrote, iclass 7, count 0 2006.231.07:38:21.87#ibcon#about to read 3, iclass 7, count 0 2006.231.07:38:21.90#ibcon#read 3, iclass 7, count 0 2006.231.07:38:21.90#ibcon#about to read 4, iclass 7, count 0 2006.231.07:38:21.90#ibcon#read 4, iclass 7, count 0 2006.231.07:38:21.90#ibcon#about to read 5, iclass 7, count 0 2006.231.07:38:21.90#ibcon#read 5, iclass 7, count 0 2006.231.07:38:21.90#ibcon#about to read 6, iclass 7, count 0 2006.231.07:38:21.90#ibcon#read 6, iclass 7, count 0 2006.231.07:38:21.90#ibcon#end of sib2, iclass 7, count 0 2006.231.07:38:21.90#ibcon#*after write, iclass 7, count 0 2006.231.07:38:21.90#ibcon#*before return 0, iclass 7, count 0 2006.231.07:38:21.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:38:21.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:38:21.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:38:21.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:38:21.90$vc4f8/vblo=5,744.99 2006.231.07:38:21.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.231.07:38:21.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.231.07:38:21.90#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:21.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:38:21.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:38:21.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:38:21.90#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:38:21.90#ibcon#first serial, iclass 11, count 0 2006.231.07:38:21.90#ibcon#enter sib2, iclass 11, count 0 2006.231.07:38:21.90#ibcon#flushed, iclass 11, count 0 2006.231.07:38:21.90#ibcon#about to write, iclass 11, count 0 2006.231.07:38:21.90#ibcon#wrote, iclass 11, count 0 2006.231.07:38:21.90#ibcon#about to read 3, iclass 11, count 0 2006.231.07:38:21.93#ibcon#read 3, iclass 11, count 0 2006.231.07:38:21.93#ibcon#about to read 4, iclass 11, count 0 2006.231.07:38:21.93#ibcon#read 4, iclass 11, count 0 2006.231.07:38:21.93#ibcon#about to read 5, iclass 11, count 0 2006.231.07:38:21.93#ibcon#read 5, iclass 11, count 0 2006.231.07:38:21.93#ibcon#about to read 6, iclass 11, count 0 2006.231.07:38:21.93#ibcon#read 6, iclass 11, count 0 2006.231.07:38:21.93#ibcon#end of sib2, iclass 11, count 0 2006.231.07:38:21.93#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:38:21.93#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:38:21.93#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:38:21.93#ibcon#*before write, iclass 11, count 0 2006.231.07:38:21.93#ibcon#enter sib2, iclass 11, count 0 2006.231.07:38:21.93#ibcon#flushed, iclass 11, count 0 2006.231.07:38:21.93#ibcon#about to write, iclass 11, count 0 2006.231.07:38:21.93#ibcon#wrote, iclass 11, count 0 2006.231.07:38:21.93#ibcon#about to read 3, iclass 11, count 0 2006.231.07:38:21.97#ibcon#read 3, iclass 11, count 0 2006.231.07:38:21.97#ibcon#about to read 4, iclass 11, count 0 2006.231.07:38:21.97#ibcon#read 4, iclass 11, count 0 2006.231.07:38:21.97#ibcon#about to read 5, iclass 11, count 0 2006.231.07:38:21.97#ibcon#read 5, iclass 11, count 0 2006.231.07:38:21.97#ibcon#about to read 6, iclass 11, count 0 2006.231.07:38:21.97#ibcon#read 6, iclass 11, count 0 2006.231.07:38:21.97#ibcon#end of sib2, iclass 11, count 0 2006.231.07:38:21.97#ibcon#*after write, iclass 11, count 0 2006.231.07:38:21.97#ibcon#*before return 0, iclass 11, count 0 2006.231.07:38:21.97#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:38:21.97#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:38:21.97#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:38:21.97#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:38:21.97$vc4f8/vb=5,3 2006.231.07:38:21.97#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.231.07:38:21.97#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.231.07:38:21.97#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:21.97#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:38:22.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:38:22.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:38:22.02#ibcon#enter wrdev, iclass 13, count 2 2006.231.07:38:22.02#ibcon#first serial, iclass 13, count 2 2006.231.07:38:22.02#ibcon#enter sib2, iclass 13, count 2 2006.231.07:38:22.02#ibcon#flushed, iclass 13, count 2 2006.231.07:38:22.02#ibcon#about to write, iclass 13, count 2 2006.231.07:38:22.02#ibcon#wrote, iclass 13, count 2 2006.231.07:38:22.02#ibcon#about to read 3, iclass 13, count 2 2006.231.07:38:22.04#ibcon#read 3, iclass 13, count 2 2006.231.07:38:22.04#ibcon#about to read 4, iclass 13, count 2 2006.231.07:38:22.04#ibcon#read 4, iclass 13, count 2 2006.231.07:38:22.04#ibcon#about to read 5, iclass 13, count 2 2006.231.07:38:22.04#ibcon#read 5, iclass 13, count 2 2006.231.07:38:22.04#ibcon#about to read 6, iclass 13, count 2 2006.231.07:38:22.04#ibcon#read 6, iclass 13, count 2 2006.231.07:38:22.04#ibcon#end of sib2, iclass 13, count 2 2006.231.07:38:22.04#ibcon#*mode == 0, iclass 13, count 2 2006.231.07:38:22.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.231.07:38:22.04#ibcon#[27=AT05-03\r\n] 2006.231.07:38:22.04#ibcon#*before write, iclass 13, count 2 2006.231.07:38:22.04#ibcon#enter sib2, iclass 13, count 2 2006.231.07:38:22.04#ibcon#flushed, iclass 13, count 2 2006.231.07:38:22.04#ibcon#about to write, iclass 13, count 2 2006.231.07:38:22.04#ibcon#wrote, iclass 13, count 2 2006.231.07:38:22.04#ibcon#about to read 3, iclass 13, count 2 2006.231.07:38:22.07#ibcon#read 3, iclass 13, count 2 2006.231.07:38:22.07#ibcon#about to read 4, iclass 13, count 2 2006.231.07:38:22.07#ibcon#read 4, iclass 13, count 2 2006.231.07:38:22.07#ibcon#about to read 5, iclass 13, count 2 2006.231.07:38:22.07#ibcon#read 5, iclass 13, count 2 2006.231.07:38:22.07#ibcon#about to read 6, iclass 13, count 2 2006.231.07:38:22.07#ibcon#read 6, iclass 13, count 2 2006.231.07:38:22.07#ibcon#end of sib2, iclass 13, count 2 2006.231.07:38:22.07#ibcon#*after write, iclass 13, count 2 2006.231.07:38:22.07#ibcon#*before return 0, iclass 13, count 2 2006.231.07:38:22.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:38:22.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:38:22.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.231.07:38:22.07#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:22.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:38:22.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:38:22.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:38:22.19#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:38:22.19#ibcon#first serial, iclass 13, count 0 2006.231.07:38:22.19#ibcon#enter sib2, iclass 13, count 0 2006.231.07:38:22.19#ibcon#flushed, iclass 13, count 0 2006.231.07:38:22.19#ibcon#about to write, iclass 13, count 0 2006.231.07:38:22.19#ibcon#wrote, iclass 13, count 0 2006.231.07:38:22.19#ibcon#about to read 3, iclass 13, count 0 2006.231.07:38:22.21#ibcon#read 3, iclass 13, count 0 2006.231.07:38:22.21#ibcon#about to read 4, iclass 13, count 0 2006.231.07:38:22.21#ibcon#read 4, iclass 13, count 0 2006.231.07:38:22.21#ibcon#about to read 5, iclass 13, count 0 2006.231.07:38:22.21#ibcon#read 5, iclass 13, count 0 2006.231.07:38:22.21#ibcon#about to read 6, iclass 13, count 0 2006.231.07:38:22.21#ibcon#read 6, iclass 13, count 0 2006.231.07:38:22.21#ibcon#end of sib2, iclass 13, count 0 2006.231.07:38:22.21#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:38:22.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:38:22.21#ibcon#[27=USB\r\n] 2006.231.07:38:22.21#ibcon#*before write, iclass 13, count 0 2006.231.07:38:22.21#ibcon#enter sib2, iclass 13, count 0 2006.231.07:38:22.21#ibcon#flushed, iclass 13, count 0 2006.231.07:38:22.21#ibcon#about to write, iclass 13, count 0 2006.231.07:38:22.21#ibcon#wrote, iclass 13, count 0 2006.231.07:38:22.21#ibcon#about to read 3, iclass 13, count 0 2006.231.07:38:22.24#ibcon#read 3, iclass 13, count 0 2006.231.07:38:22.24#ibcon#about to read 4, iclass 13, count 0 2006.231.07:38:22.24#ibcon#read 4, iclass 13, count 0 2006.231.07:38:22.24#ibcon#about to read 5, iclass 13, count 0 2006.231.07:38:22.24#ibcon#read 5, iclass 13, count 0 2006.231.07:38:22.24#ibcon#about to read 6, iclass 13, count 0 2006.231.07:38:22.24#ibcon#read 6, iclass 13, count 0 2006.231.07:38:22.24#ibcon#end of sib2, iclass 13, count 0 2006.231.07:38:22.24#ibcon#*after write, iclass 13, count 0 2006.231.07:38:22.24#ibcon#*before return 0, iclass 13, count 0 2006.231.07:38:22.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:38:22.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:38:22.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:38:22.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:38:22.24$vc4f8/vblo=6,752.99 2006.231.07:38:22.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.07:38:22.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.07:38:22.24#ibcon#ireg 17 cls_cnt 0 2006.231.07:38:22.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:38:22.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:38:22.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:38:22.24#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:38:22.24#ibcon#first serial, iclass 15, count 0 2006.231.07:38:22.24#ibcon#enter sib2, iclass 15, count 0 2006.231.07:38:22.24#ibcon#flushed, iclass 15, count 0 2006.231.07:38:22.24#ibcon#about to write, iclass 15, count 0 2006.231.07:38:22.24#ibcon#wrote, iclass 15, count 0 2006.231.07:38:22.24#ibcon#about to read 3, iclass 15, count 0 2006.231.07:38:22.26#ibcon#read 3, iclass 15, count 0 2006.231.07:38:22.26#ibcon#about to read 4, iclass 15, count 0 2006.231.07:38:22.26#ibcon#read 4, iclass 15, count 0 2006.231.07:38:22.26#ibcon#about to read 5, iclass 15, count 0 2006.231.07:38:22.26#ibcon#read 5, iclass 15, count 0 2006.231.07:38:22.26#ibcon#about to read 6, iclass 15, count 0 2006.231.07:38:22.26#ibcon#read 6, iclass 15, count 0 2006.231.07:38:22.26#ibcon#end of sib2, iclass 15, count 0 2006.231.07:38:22.26#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:38:22.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:38:22.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:38:22.26#ibcon#*before write, iclass 15, count 0 2006.231.07:38:22.26#ibcon#enter sib2, iclass 15, count 0 2006.231.07:38:22.26#ibcon#flushed, iclass 15, count 0 2006.231.07:38:22.26#ibcon#about to write, iclass 15, count 0 2006.231.07:38:22.26#ibcon#wrote, iclass 15, count 0 2006.231.07:38:22.26#ibcon#about to read 3, iclass 15, count 0 2006.231.07:38:22.30#ibcon#read 3, iclass 15, count 0 2006.231.07:38:22.30#ibcon#about to read 4, iclass 15, count 0 2006.231.07:38:22.30#ibcon#read 4, iclass 15, count 0 2006.231.07:38:22.30#ibcon#about to read 5, iclass 15, count 0 2006.231.07:38:22.30#ibcon#read 5, iclass 15, count 0 2006.231.07:38:22.30#ibcon#about to read 6, iclass 15, count 0 2006.231.07:38:22.30#ibcon#read 6, iclass 15, count 0 2006.231.07:38:22.30#ibcon#end of sib2, iclass 15, count 0 2006.231.07:38:22.30#ibcon#*after write, iclass 15, count 0 2006.231.07:38:22.30#ibcon#*before return 0, iclass 15, count 0 2006.231.07:38:22.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:38:22.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:38:22.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:38:22.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:38:22.30$vc4f8/vb=6,4 2006.231.07:38:22.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.07:38:22.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.07:38:22.30#ibcon#ireg 11 cls_cnt 2 2006.231.07:38:22.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:38:22.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:38:22.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:38:22.36#ibcon#enter wrdev, iclass 17, count 2 2006.231.07:38:22.36#ibcon#first serial, iclass 17, count 2 2006.231.07:38:22.36#ibcon#enter sib2, iclass 17, count 2 2006.231.07:38:22.36#ibcon#flushed, iclass 17, count 2 2006.231.07:38:22.36#ibcon#about to write, iclass 17, count 2 2006.231.07:38:22.36#ibcon#wrote, iclass 17, count 2 2006.231.07:38:22.36#ibcon#about to read 3, iclass 17, count 2 2006.231.07:38:22.38#ibcon#read 3, iclass 17, count 2 2006.231.07:38:22.38#ibcon#about to read 4, iclass 17, count 2 2006.231.07:38:22.38#ibcon#read 4, iclass 17, count 2 2006.231.07:38:22.38#ibcon#about to read 5, iclass 17, count 2 2006.231.07:38:22.38#ibcon#read 5, iclass 17, count 2 2006.231.07:38:22.38#ibcon#about to read 6, iclass 17, count 2 2006.231.07:38:22.38#ibcon#read 6, iclass 17, count 2 2006.231.07:38:22.38#ibcon#end of sib2, iclass 17, count 2 2006.231.07:38:22.38#ibcon#*mode == 0, iclass 17, count 2 2006.231.07:38:22.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.07:38:22.38#ibcon#[27=AT06-04\r\n] 2006.231.07:38:22.38#ibcon#*before write, iclass 17, count 2 2006.231.07:38:22.38#ibcon#enter sib2, iclass 17, count 2 2006.231.07:38:22.38#ibcon#flushed, iclass 17, count 2 2006.231.07:38:22.38#ibcon#about to write, iclass 17, count 2 2006.231.07:38:22.38#ibcon#wrote, iclass 17, count 2 2006.231.07:38:22.38#ibcon#about to read 3, iclass 17, count 2 2006.231.07:38:22.41#ibcon#read 3, iclass 17, count 2 2006.231.07:38:22.41#ibcon#about to read 4, iclass 17, count 2 2006.231.07:38:22.41#ibcon#read 4, iclass 17, count 2 2006.231.07:38:22.41#ibcon#about to read 5, iclass 17, count 2 2006.231.07:38:22.41#ibcon#read 5, iclass 17, count 2 2006.231.07:38:22.41#ibcon#about to read 6, iclass 17, count 2 2006.231.07:38:22.41#ibcon#read 6, iclass 17, count 2 2006.231.07:38:22.41#ibcon#end of sib2, iclass 17, count 2 2006.231.07:38:22.41#ibcon#*after write, iclass 17, count 2 2006.231.07:38:22.41#ibcon#*before return 0, iclass 17, count 2 2006.231.07:38:22.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:38:22.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:38:22.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.07:38:22.41#ibcon#ireg 7 cls_cnt 0 2006.231.07:38:22.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:38:22.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:38:22.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:38:22.53#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:38:22.53#ibcon#first serial, iclass 17, count 0 2006.231.07:38:22.53#ibcon#enter sib2, iclass 17, count 0 2006.231.07:38:22.53#ibcon#flushed, iclass 17, count 0 2006.231.07:38:22.53#ibcon#about to write, iclass 17, count 0 2006.231.07:38:22.53#ibcon#wrote, iclass 17, count 0 2006.231.07:38:22.53#ibcon#about to read 3, iclass 17, count 0 2006.231.07:38:22.55#ibcon#read 3, iclass 17, count 0 2006.231.07:38:22.55#ibcon#about to read 4, iclass 17, count 0 2006.231.07:38:22.55#ibcon#read 4, iclass 17, count 0 2006.231.07:38:22.55#ibcon#about to read 5, iclass 17, count 0 2006.231.07:38:22.55#ibcon#read 5, iclass 17, count 0 2006.231.07:38:22.55#ibcon#about to read 6, iclass 17, count 0 2006.231.07:38:22.55#ibcon#read 6, iclass 17, count 0 2006.231.07:38:22.55#ibcon#end of sib2, iclass 17, count 0 2006.231.07:38:22.55#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:38:22.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:38:22.55#ibcon#[27=USB\r\n] 2006.231.07:38:22.55#ibcon#*before write, iclass 17, count 0 2006.231.07:38:22.55#ibcon#enter sib2, iclass 17, count 0 2006.231.07:38:22.55#ibcon#flushed, iclass 17, count 0 2006.231.07:38:22.55#ibcon#about to write, iclass 17, count 0 2006.231.07:38:22.55#ibcon#wrote, iclass 17, count 0 2006.231.07:38:22.55#ibcon#about to read 3, iclass 17, count 0 2006.231.07:38:22.58#ibcon#read 3, iclass 17, count 0 2006.231.07:38:22.58#ibcon#about to read 4, iclass 17, count 0 2006.231.07:38:22.58#ibcon#read 4, iclass 17, count 0 2006.231.07:38:22.58#ibcon#about to read 5, iclass 17, count 0 2006.231.07:38:22.58#ibcon#read 5, iclass 17, count 0 2006.231.07:38:22.58#ibcon#about to read 6, iclass 17, count 0 2006.231.07:38:22.58#ibcon#read 6, iclass 17, count 0 2006.231.07:38:22.58#ibcon#end of sib2, iclass 17, count 0 2006.231.07:38:22.58#ibcon#*after write, iclass 17, count 0 2006.231.07:38:22.58#ibcon#*before return 0, iclass 17, count 0 2006.231.07:38:22.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:38:22.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:38:22.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:38:22.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:38:22.58$vc4f8/vabw=wide 2006.231.07:38:22.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.07:38:22.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.07:38:22.58#ibcon#ireg 8 cls_cnt 0 2006.231.07:38:22.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:38:22.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:38:22.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:38:22.58#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:38:22.58#ibcon#first serial, iclass 19, count 0 2006.231.07:38:22.58#ibcon#enter sib2, iclass 19, count 0 2006.231.07:38:22.58#ibcon#flushed, iclass 19, count 0 2006.231.07:38:22.58#ibcon#about to write, iclass 19, count 0 2006.231.07:38:22.58#ibcon#wrote, iclass 19, count 0 2006.231.07:38:22.58#ibcon#about to read 3, iclass 19, count 0 2006.231.07:38:22.60#ibcon#read 3, iclass 19, count 0 2006.231.07:38:22.60#ibcon#about to read 4, iclass 19, count 0 2006.231.07:38:22.60#ibcon#read 4, iclass 19, count 0 2006.231.07:38:22.60#ibcon#about to read 5, iclass 19, count 0 2006.231.07:38:22.60#ibcon#read 5, iclass 19, count 0 2006.231.07:38:22.60#ibcon#about to read 6, iclass 19, count 0 2006.231.07:38:22.60#ibcon#read 6, iclass 19, count 0 2006.231.07:38:22.60#ibcon#end of sib2, iclass 19, count 0 2006.231.07:38:22.60#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:38:22.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:38:22.60#ibcon#[25=BW32\r\n] 2006.231.07:38:22.60#ibcon#*before write, iclass 19, count 0 2006.231.07:38:22.60#ibcon#enter sib2, iclass 19, count 0 2006.231.07:38:22.60#ibcon#flushed, iclass 19, count 0 2006.231.07:38:22.60#ibcon#about to write, iclass 19, count 0 2006.231.07:38:22.60#ibcon#wrote, iclass 19, count 0 2006.231.07:38:22.60#ibcon#about to read 3, iclass 19, count 0 2006.231.07:38:22.63#ibcon#read 3, iclass 19, count 0 2006.231.07:38:22.63#ibcon#about to read 4, iclass 19, count 0 2006.231.07:38:22.63#ibcon#read 4, iclass 19, count 0 2006.231.07:38:22.63#ibcon#about to read 5, iclass 19, count 0 2006.231.07:38:22.63#ibcon#read 5, iclass 19, count 0 2006.231.07:38:22.63#ibcon#about to read 6, iclass 19, count 0 2006.231.07:38:22.63#ibcon#read 6, iclass 19, count 0 2006.231.07:38:22.63#ibcon#end of sib2, iclass 19, count 0 2006.231.07:38:22.63#ibcon#*after write, iclass 19, count 0 2006.231.07:38:22.63#ibcon#*before return 0, iclass 19, count 0 2006.231.07:38:22.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:38:22.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:38:22.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:38:22.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:38:22.63$vc4f8/vbbw=wide 2006.231.07:38:22.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.07:38:22.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.07:38:22.63#ibcon#ireg 8 cls_cnt 0 2006.231.07:38:22.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:38:22.71#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:38:22.71#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:38:22.71#ibcon#enter wrdev, iclass 21, count 0 2006.231.07:38:22.71#ibcon#first serial, iclass 21, count 0 2006.231.07:38:22.71#ibcon#enter sib2, iclass 21, count 0 2006.231.07:38:22.71#ibcon#flushed, iclass 21, count 0 2006.231.07:38:22.71#ibcon#about to write, iclass 21, count 0 2006.231.07:38:22.71#ibcon#wrote, iclass 21, count 0 2006.231.07:38:22.71#ibcon#about to read 3, iclass 21, count 0 2006.231.07:38:22.72#ibcon#read 3, iclass 21, count 0 2006.231.07:38:22.72#ibcon#about to read 4, iclass 21, count 0 2006.231.07:38:22.72#ibcon#read 4, iclass 21, count 0 2006.231.07:38:22.72#ibcon#about to read 5, iclass 21, count 0 2006.231.07:38:22.72#ibcon#read 5, iclass 21, count 0 2006.231.07:38:22.72#ibcon#about to read 6, iclass 21, count 0 2006.231.07:38:22.72#ibcon#read 6, iclass 21, count 0 2006.231.07:38:22.72#ibcon#end of sib2, iclass 21, count 0 2006.231.07:38:22.72#ibcon#*mode == 0, iclass 21, count 0 2006.231.07:38:22.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.07:38:22.72#ibcon#[27=BW32\r\n] 2006.231.07:38:22.72#ibcon#*before write, iclass 21, count 0 2006.231.07:38:22.72#ibcon#enter sib2, iclass 21, count 0 2006.231.07:38:22.72#ibcon#flushed, iclass 21, count 0 2006.231.07:38:22.72#ibcon#about to write, iclass 21, count 0 2006.231.07:38:22.72#ibcon#wrote, iclass 21, count 0 2006.231.07:38:22.72#ibcon#about to read 3, iclass 21, count 0 2006.231.07:38:22.75#ibcon#read 3, iclass 21, count 0 2006.231.07:38:22.75#ibcon#about to read 4, iclass 21, count 0 2006.231.07:38:22.75#ibcon#read 4, iclass 21, count 0 2006.231.07:38:22.75#ibcon#about to read 5, iclass 21, count 0 2006.231.07:38:22.75#ibcon#read 5, iclass 21, count 0 2006.231.07:38:22.75#ibcon#about to read 6, iclass 21, count 0 2006.231.07:38:22.75#ibcon#read 6, iclass 21, count 0 2006.231.07:38:22.75#ibcon#end of sib2, iclass 21, count 0 2006.231.07:38:22.75#ibcon#*after write, iclass 21, count 0 2006.231.07:38:22.75#ibcon#*before return 0, iclass 21, count 0 2006.231.07:38:22.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:38:22.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:38:22.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.07:38:22.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.07:38:22.75$4f8m12a/ifd4f 2006.231.07:38:22.75$ifd4f/lo= 2006.231.07:38:22.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:38:22.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:38:22.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:38:22.75$ifd4f/patch= 2006.231.07:38:22.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:38:22.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:38:22.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:38:22.75$4f8m12a/"form=m,16.000,1:2 2006.231.07:38:22.75$4f8m12a/"tpicd 2006.231.07:38:22.75$4f8m12a/echo=off 2006.231.07:38:22.75$4f8m12a/xlog=off 2006.231.07:38:22.75:!2006.231.07:38:50 2006.231.07:38:33.14#trakl#Source acquired 2006.231.07:38:35.14#flagr#flagr/antenna,acquired 2006.231.07:38:50.00:preob 2006.231.07:38:51.14/onsource/TRACKING 2006.231.07:38:51.14:!2006.231.07:39:00 2006.231.07:39:00.00:data_valid=on 2006.231.07:39:00.00:midob 2006.231.07:39:00.14/onsource/TRACKING 2006.231.07:39:00.14/wx/30.69,1004.4,83 2006.231.07:39:00.29/cable/+6.3707E-03 2006.231.07:39:01.38/va/01,08,usb,yes,29,31 2006.231.07:39:01.38/va/02,07,usb,yes,29,31 2006.231.07:39:01.38/va/03,08,usb,yes,22,22 2006.231.07:39:01.38/va/04,07,usb,yes,31,33 2006.231.07:39:01.38/va/05,07,usb,yes,34,36 2006.231.07:39:01.38/va/06,06,usb,yes,33,33 2006.231.07:39:01.38/va/07,06,usb,yes,34,34 2006.231.07:39:01.38/va/08,06,usb,yes,36,35 2006.231.07:39:01.61/valo/01,532.99,yes,locked 2006.231.07:39:01.61/valo/02,572.99,yes,locked 2006.231.07:39:01.61/valo/03,672.99,yes,locked 2006.231.07:39:01.61/valo/04,832.99,yes,locked 2006.231.07:39:01.61/valo/05,652.99,yes,locked 2006.231.07:39:01.61/valo/06,772.99,yes,locked 2006.231.07:39:01.61/valo/07,832.99,yes,locked 2006.231.07:39:01.61/valo/08,852.99,yes,locked 2006.231.07:39:02.70/vb/01,04,usb,yes,30,29 2006.231.07:39:02.70/vb/02,04,usb,yes,32,33 2006.231.07:39:02.70/vb/03,04,usb,yes,28,32 2006.231.07:39:02.70/vb/04,04,usb,yes,29,29 2006.231.07:39:02.70/vb/05,03,usb,yes,35,39 2006.231.07:39:02.70/vb/06,04,usb,yes,28,31 2006.231.07:39:02.70/vb/07,04,usb,yes,31,31 2006.231.07:39:02.70/vb/08,04,usb,yes,28,32 2006.231.07:39:02.93/vblo/01,632.99,yes,locked 2006.231.07:39:02.93/vblo/02,640.99,yes,locked 2006.231.07:39:02.93/vblo/03,656.99,yes,locked 2006.231.07:39:02.93/vblo/04,712.99,yes,locked 2006.231.07:39:02.93/vblo/05,744.99,yes,locked 2006.231.07:39:02.93/vblo/06,752.99,yes,locked 2006.231.07:39:02.93/vblo/07,734.99,yes,locked 2006.231.07:39:02.93/vblo/08,744.99,yes,locked 2006.231.07:39:03.08/vabw/8 2006.231.07:39:03.23/vbbw/8 2006.231.07:39:03.32/xfe/off,on,12.5 2006.231.07:39:03.69/ifatt/23,28,28,28 2006.231.07:39:04.07/fmout-gps/S +4.38E-07 2006.231.07:39:04.11:!2006.231.07:40:00 2006.231.07:40:00.00:data_valid=off 2006.231.07:40:00.00:postob 2006.231.07:40:00.06/cable/+6.3709E-03 2006.231.07:40:00.06/wx/30.67,1004.4,84 2006.231.07:40:01.07/fmout-gps/S +4.38E-07 2006.231.07:40:01.07:scan_name=231-0740,k06231,60 2006.231.07:40:01.07:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.231.07:40:01.14#flagr#flagr/antenna,new-source 2006.231.07:40:02.14:checkk5 2006.231.07:40:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:40:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:40:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:40:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:40:04.01/chk_obsdata//k5ts1/T2310739??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:40:04.38/chk_obsdata//k5ts2/T2310739??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:40:04.75/chk_obsdata//k5ts3/T2310739??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:40:05.12/chk_obsdata//k5ts4/T2310739??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:40:05.81/k5log//k5ts1_log_newline 2006.231.07:40:06.50/k5log//k5ts2_log_newline 2006.231.07:40:07.19/k5log//k5ts3_log_newline 2006.231.07:40:07.88/k5log//k5ts4_log_newline 2006.231.07:40:07.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:40:07.90:4f8m12a=1 2006.231.07:40:07.90$4f8m12a/echo=on 2006.231.07:40:07.90$4f8m12a/pcalon 2006.231.07:40:07.90$pcalon/"no phase cal control is implemented here 2006.231.07:40:07.90$4f8m12a/"tpicd=stop 2006.231.07:40:07.90$4f8m12a/vc4f8 2006.231.07:40:07.90$vc4f8/valo=1,532.99 2006.231.07:40:07.90#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.231.07:40:07.90#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.231.07:40:07.90#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:07.90#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:40:07.90#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:40:07.90#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:40:07.90#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:40:07.90#ibcon#first serial, iclass 28, count 0 2006.231.07:40:07.90#ibcon#enter sib2, iclass 28, count 0 2006.231.07:40:07.90#ibcon#flushed, iclass 28, count 0 2006.231.07:40:07.90#ibcon#about to write, iclass 28, count 0 2006.231.07:40:07.90#ibcon#wrote, iclass 28, count 0 2006.231.07:40:07.90#ibcon#about to read 3, iclass 28, count 0 2006.231.07:40:07.94#ibcon#read 3, iclass 28, count 0 2006.231.07:40:07.94#ibcon#about to read 4, iclass 28, count 0 2006.231.07:40:07.94#ibcon#read 4, iclass 28, count 0 2006.231.07:40:07.94#ibcon#about to read 5, iclass 28, count 0 2006.231.07:40:07.94#ibcon#read 5, iclass 28, count 0 2006.231.07:40:07.94#ibcon#about to read 6, iclass 28, count 0 2006.231.07:40:07.94#ibcon#read 6, iclass 28, count 0 2006.231.07:40:07.94#ibcon#end of sib2, iclass 28, count 0 2006.231.07:40:07.94#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:40:07.94#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:40:07.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:40:07.94#ibcon#*before write, iclass 28, count 0 2006.231.07:40:07.94#ibcon#enter sib2, iclass 28, count 0 2006.231.07:40:07.94#ibcon#flushed, iclass 28, count 0 2006.231.07:40:07.94#ibcon#about to write, iclass 28, count 0 2006.231.07:40:07.94#ibcon#wrote, iclass 28, count 0 2006.231.07:40:07.94#ibcon#about to read 3, iclass 28, count 0 2006.231.07:40:07.99#ibcon#read 3, iclass 28, count 0 2006.231.07:40:07.99#ibcon#about to read 4, iclass 28, count 0 2006.231.07:40:07.99#ibcon#read 4, iclass 28, count 0 2006.231.07:40:07.99#ibcon#about to read 5, iclass 28, count 0 2006.231.07:40:07.99#ibcon#read 5, iclass 28, count 0 2006.231.07:40:07.99#ibcon#about to read 6, iclass 28, count 0 2006.231.07:40:07.99#ibcon#read 6, iclass 28, count 0 2006.231.07:40:07.99#ibcon#end of sib2, iclass 28, count 0 2006.231.07:40:07.99#ibcon#*after write, iclass 28, count 0 2006.231.07:40:07.99#ibcon#*before return 0, iclass 28, count 0 2006.231.07:40:07.99#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:40:07.99#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:40:07.99#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:40:07.99#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:40:07.99$vc4f8/va=1,8 2006.231.07:40:07.99#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.07:40:07.99#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.07:40:07.99#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:07.99#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:40:07.99#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:40:07.99#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:40:07.99#ibcon#enter wrdev, iclass 30, count 2 2006.231.07:40:07.99#ibcon#first serial, iclass 30, count 2 2006.231.07:40:07.99#ibcon#enter sib2, iclass 30, count 2 2006.231.07:40:07.99#ibcon#flushed, iclass 30, count 2 2006.231.07:40:07.99#ibcon#about to write, iclass 30, count 2 2006.231.07:40:07.99#ibcon#wrote, iclass 30, count 2 2006.231.07:40:07.99#ibcon#about to read 3, iclass 30, count 2 2006.231.07:40:08.01#ibcon#read 3, iclass 30, count 2 2006.231.07:40:08.01#ibcon#about to read 4, iclass 30, count 2 2006.231.07:40:08.01#ibcon#read 4, iclass 30, count 2 2006.231.07:40:08.01#ibcon#about to read 5, iclass 30, count 2 2006.231.07:40:08.01#ibcon#read 5, iclass 30, count 2 2006.231.07:40:08.01#ibcon#about to read 6, iclass 30, count 2 2006.231.07:40:08.01#ibcon#read 6, iclass 30, count 2 2006.231.07:40:08.01#ibcon#end of sib2, iclass 30, count 2 2006.231.07:40:08.01#ibcon#*mode == 0, iclass 30, count 2 2006.231.07:40:08.01#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.07:40:08.01#ibcon#[25=AT01-08\r\n] 2006.231.07:40:08.01#ibcon#*before write, iclass 30, count 2 2006.231.07:40:08.01#ibcon#enter sib2, iclass 30, count 2 2006.231.07:40:08.01#ibcon#flushed, iclass 30, count 2 2006.231.07:40:08.01#ibcon#about to write, iclass 30, count 2 2006.231.07:40:08.01#ibcon#wrote, iclass 30, count 2 2006.231.07:40:08.01#ibcon#about to read 3, iclass 30, count 2 2006.231.07:40:08.04#ibcon#read 3, iclass 30, count 2 2006.231.07:40:08.04#ibcon#about to read 4, iclass 30, count 2 2006.231.07:40:08.04#ibcon#read 4, iclass 30, count 2 2006.231.07:40:08.04#ibcon#about to read 5, iclass 30, count 2 2006.231.07:40:08.04#ibcon#read 5, iclass 30, count 2 2006.231.07:40:08.04#ibcon#about to read 6, iclass 30, count 2 2006.231.07:40:08.04#ibcon#read 6, iclass 30, count 2 2006.231.07:40:08.04#ibcon#end of sib2, iclass 30, count 2 2006.231.07:40:08.04#ibcon#*after write, iclass 30, count 2 2006.231.07:40:08.04#ibcon#*before return 0, iclass 30, count 2 2006.231.07:40:08.04#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:40:08.04#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:40:08.04#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.07:40:08.04#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:08.04#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:40:08.16#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:40:08.16#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:40:08.16#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:40:08.16#ibcon#first serial, iclass 30, count 0 2006.231.07:40:08.16#ibcon#enter sib2, iclass 30, count 0 2006.231.07:40:08.16#ibcon#flushed, iclass 30, count 0 2006.231.07:40:08.16#ibcon#about to write, iclass 30, count 0 2006.231.07:40:08.16#ibcon#wrote, iclass 30, count 0 2006.231.07:40:08.16#ibcon#about to read 3, iclass 30, count 0 2006.231.07:40:08.18#ibcon#read 3, iclass 30, count 0 2006.231.07:40:08.18#ibcon#about to read 4, iclass 30, count 0 2006.231.07:40:08.18#ibcon#read 4, iclass 30, count 0 2006.231.07:40:08.18#ibcon#about to read 5, iclass 30, count 0 2006.231.07:40:08.18#ibcon#read 5, iclass 30, count 0 2006.231.07:40:08.18#ibcon#about to read 6, iclass 30, count 0 2006.231.07:40:08.18#ibcon#read 6, iclass 30, count 0 2006.231.07:40:08.18#ibcon#end of sib2, iclass 30, count 0 2006.231.07:40:08.18#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:40:08.18#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:40:08.18#ibcon#[25=USB\r\n] 2006.231.07:40:08.18#ibcon#*before write, iclass 30, count 0 2006.231.07:40:08.18#ibcon#enter sib2, iclass 30, count 0 2006.231.07:40:08.18#ibcon#flushed, iclass 30, count 0 2006.231.07:40:08.18#ibcon#about to write, iclass 30, count 0 2006.231.07:40:08.18#ibcon#wrote, iclass 30, count 0 2006.231.07:40:08.18#ibcon#about to read 3, iclass 30, count 0 2006.231.07:40:08.21#ibcon#read 3, iclass 30, count 0 2006.231.07:40:08.21#ibcon#about to read 4, iclass 30, count 0 2006.231.07:40:08.21#ibcon#read 4, iclass 30, count 0 2006.231.07:40:08.21#ibcon#about to read 5, iclass 30, count 0 2006.231.07:40:08.21#ibcon#read 5, iclass 30, count 0 2006.231.07:40:08.21#ibcon#about to read 6, iclass 30, count 0 2006.231.07:40:08.21#ibcon#read 6, iclass 30, count 0 2006.231.07:40:08.21#ibcon#end of sib2, iclass 30, count 0 2006.231.07:40:08.21#ibcon#*after write, iclass 30, count 0 2006.231.07:40:08.21#ibcon#*before return 0, iclass 30, count 0 2006.231.07:40:08.21#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:40:08.21#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:40:08.21#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:40:08.21#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:40:08.21$vc4f8/valo=2,572.99 2006.231.07:40:08.21#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.07:40:08.21#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.07:40:08.21#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:08.21#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:40:08.21#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:40:08.21#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:40:08.21#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:40:08.21#ibcon#first serial, iclass 32, count 0 2006.231.07:40:08.21#ibcon#enter sib2, iclass 32, count 0 2006.231.07:40:08.21#ibcon#flushed, iclass 32, count 0 2006.231.07:40:08.21#ibcon#about to write, iclass 32, count 0 2006.231.07:40:08.21#ibcon#wrote, iclass 32, count 0 2006.231.07:40:08.21#ibcon#about to read 3, iclass 32, count 0 2006.231.07:40:08.23#ibcon#read 3, iclass 32, count 0 2006.231.07:40:08.23#ibcon#about to read 4, iclass 32, count 0 2006.231.07:40:08.23#ibcon#read 4, iclass 32, count 0 2006.231.07:40:08.23#ibcon#about to read 5, iclass 32, count 0 2006.231.07:40:08.23#ibcon#read 5, iclass 32, count 0 2006.231.07:40:08.23#ibcon#about to read 6, iclass 32, count 0 2006.231.07:40:08.23#ibcon#read 6, iclass 32, count 0 2006.231.07:40:08.23#ibcon#end of sib2, iclass 32, count 0 2006.231.07:40:08.23#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:40:08.23#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:40:08.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:40:08.23#ibcon#*before write, iclass 32, count 0 2006.231.07:40:08.23#ibcon#enter sib2, iclass 32, count 0 2006.231.07:40:08.23#ibcon#flushed, iclass 32, count 0 2006.231.07:40:08.23#ibcon#about to write, iclass 32, count 0 2006.231.07:40:08.23#ibcon#wrote, iclass 32, count 0 2006.231.07:40:08.23#ibcon#about to read 3, iclass 32, count 0 2006.231.07:40:08.27#ibcon#read 3, iclass 32, count 0 2006.231.07:40:08.27#ibcon#about to read 4, iclass 32, count 0 2006.231.07:40:08.27#ibcon#read 4, iclass 32, count 0 2006.231.07:40:08.27#ibcon#about to read 5, iclass 32, count 0 2006.231.07:40:08.27#ibcon#read 5, iclass 32, count 0 2006.231.07:40:08.27#ibcon#about to read 6, iclass 32, count 0 2006.231.07:40:08.27#ibcon#read 6, iclass 32, count 0 2006.231.07:40:08.27#ibcon#end of sib2, iclass 32, count 0 2006.231.07:40:08.27#ibcon#*after write, iclass 32, count 0 2006.231.07:40:08.27#ibcon#*before return 0, iclass 32, count 0 2006.231.07:40:08.27#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:40:08.27#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:40:08.27#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:40:08.27#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:40:08.27$vc4f8/va=2,7 2006.231.07:40:08.27#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.07:40:08.27#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.07:40:08.27#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:08.27#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:40:08.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:40:08.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:40:08.34#ibcon#enter wrdev, iclass 34, count 2 2006.231.07:40:08.34#ibcon#first serial, iclass 34, count 2 2006.231.07:40:08.34#ibcon#enter sib2, iclass 34, count 2 2006.231.07:40:08.34#ibcon#flushed, iclass 34, count 2 2006.231.07:40:08.34#ibcon#about to write, iclass 34, count 2 2006.231.07:40:08.34#ibcon#wrote, iclass 34, count 2 2006.231.07:40:08.34#ibcon#about to read 3, iclass 34, count 2 2006.231.07:40:08.35#ibcon#read 3, iclass 34, count 2 2006.231.07:40:08.35#ibcon#about to read 4, iclass 34, count 2 2006.231.07:40:08.35#ibcon#read 4, iclass 34, count 2 2006.231.07:40:08.35#ibcon#about to read 5, iclass 34, count 2 2006.231.07:40:08.35#ibcon#read 5, iclass 34, count 2 2006.231.07:40:08.35#ibcon#about to read 6, iclass 34, count 2 2006.231.07:40:08.35#ibcon#read 6, iclass 34, count 2 2006.231.07:40:08.35#ibcon#end of sib2, iclass 34, count 2 2006.231.07:40:08.35#ibcon#*mode == 0, iclass 34, count 2 2006.231.07:40:08.35#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.07:40:08.35#ibcon#[25=AT02-07\r\n] 2006.231.07:40:08.35#ibcon#*before write, iclass 34, count 2 2006.231.07:40:08.35#ibcon#enter sib2, iclass 34, count 2 2006.231.07:40:08.35#ibcon#flushed, iclass 34, count 2 2006.231.07:40:08.35#ibcon#about to write, iclass 34, count 2 2006.231.07:40:08.35#ibcon#wrote, iclass 34, count 2 2006.231.07:40:08.35#ibcon#about to read 3, iclass 34, count 2 2006.231.07:40:08.38#ibcon#read 3, iclass 34, count 2 2006.231.07:40:08.38#ibcon#about to read 4, iclass 34, count 2 2006.231.07:40:08.38#ibcon#read 4, iclass 34, count 2 2006.231.07:40:08.38#ibcon#about to read 5, iclass 34, count 2 2006.231.07:40:08.38#ibcon#read 5, iclass 34, count 2 2006.231.07:40:08.38#ibcon#about to read 6, iclass 34, count 2 2006.231.07:40:08.38#ibcon#read 6, iclass 34, count 2 2006.231.07:40:08.38#ibcon#end of sib2, iclass 34, count 2 2006.231.07:40:08.38#ibcon#*after write, iclass 34, count 2 2006.231.07:40:08.38#ibcon#*before return 0, iclass 34, count 2 2006.231.07:40:08.38#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:40:08.38#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:40:08.38#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.07:40:08.38#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:08.38#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:40:08.50#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:40:08.50#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:40:08.50#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:40:08.50#ibcon#first serial, iclass 34, count 0 2006.231.07:40:08.50#ibcon#enter sib2, iclass 34, count 0 2006.231.07:40:08.50#ibcon#flushed, iclass 34, count 0 2006.231.07:40:08.50#ibcon#about to write, iclass 34, count 0 2006.231.07:40:08.50#ibcon#wrote, iclass 34, count 0 2006.231.07:40:08.50#ibcon#about to read 3, iclass 34, count 0 2006.231.07:40:08.52#ibcon#read 3, iclass 34, count 0 2006.231.07:40:08.52#ibcon#about to read 4, iclass 34, count 0 2006.231.07:40:08.52#ibcon#read 4, iclass 34, count 0 2006.231.07:40:08.52#ibcon#about to read 5, iclass 34, count 0 2006.231.07:40:08.52#ibcon#read 5, iclass 34, count 0 2006.231.07:40:08.52#ibcon#about to read 6, iclass 34, count 0 2006.231.07:40:08.52#ibcon#read 6, iclass 34, count 0 2006.231.07:40:08.52#ibcon#end of sib2, iclass 34, count 0 2006.231.07:40:08.52#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:40:08.52#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:40:08.52#ibcon#[25=USB\r\n] 2006.231.07:40:08.52#ibcon#*before write, iclass 34, count 0 2006.231.07:40:08.52#ibcon#enter sib2, iclass 34, count 0 2006.231.07:40:08.52#ibcon#flushed, iclass 34, count 0 2006.231.07:40:08.52#ibcon#about to write, iclass 34, count 0 2006.231.07:40:08.52#ibcon#wrote, iclass 34, count 0 2006.231.07:40:08.52#ibcon#about to read 3, iclass 34, count 0 2006.231.07:40:08.55#ibcon#read 3, iclass 34, count 0 2006.231.07:40:08.55#ibcon#about to read 4, iclass 34, count 0 2006.231.07:40:08.55#ibcon#read 4, iclass 34, count 0 2006.231.07:40:08.55#ibcon#about to read 5, iclass 34, count 0 2006.231.07:40:08.55#ibcon#read 5, iclass 34, count 0 2006.231.07:40:08.55#ibcon#about to read 6, iclass 34, count 0 2006.231.07:40:08.55#ibcon#read 6, iclass 34, count 0 2006.231.07:40:08.55#ibcon#end of sib2, iclass 34, count 0 2006.231.07:40:08.55#ibcon#*after write, iclass 34, count 0 2006.231.07:40:08.55#ibcon#*before return 0, iclass 34, count 0 2006.231.07:40:08.55#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:40:08.55#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:40:08.55#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:40:08.55#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:40:08.55$vc4f8/valo=3,672.99 2006.231.07:40:08.55#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.07:40:08.55#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.07:40:08.55#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:08.55#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:40:08.55#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:40:08.55#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:40:08.55#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:40:08.55#ibcon#first serial, iclass 36, count 0 2006.231.07:40:08.55#ibcon#enter sib2, iclass 36, count 0 2006.231.07:40:08.55#ibcon#flushed, iclass 36, count 0 2006.231.07:40:08.55#ibcon#about to write, iclass 36, count 0 2006.231.07:40:08.55#ibcon#wrote, iclass 36, count 0 2006.231.07:40:08.55#ibcon#about to read 3, iclass 36, count 0 2006.231.07:40:08.57#ibcon#read 3, iclass 36, count 0 2006.231.07:40:08.57#ibcon#about to read 4, iclass 36, count 0 2006.231.07:40:08.57#ibcon#read 4, iclass 36, count 0 2006.231.07:40:08.57#ibcon#about to read 5, iclass 36, count 0 2006.231.07:40:08.57#ibcon#read 5, iclass 36, count 0 2006.231.07:40:08.57#ibcon#about to read 6, iclass 36, count 0 2006.231.07:40:08.57#ibcon#read 6, iclass 36, count 0 2006.231.07:40:08.57#ibcon#end of sib2, iclass 36, count 0 2006.231.07:40:08.57#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:40:08.57#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:40:08.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:40:08.57#ibcon#*before write, iclass 36, count 0 2006.231.07:40:08.57#ibcon#enter sib2, iclass 36, count 0 2006.231.07:40:08.57#ibcon#flushed, iclass 36, count 0 2006.231.07:40:08.57#ibcon#about to write, iclass 36, count 0 2006.231.07:40:08.57#ibcon#wrote, iclass 36, count 0 2006.231.07:40:08.57#ibcon#about to read 3, iclass 36, count 0 2006.231.07:40:08.61#ibcon#read 3, iclass 36, count 0 2006.231.07:40:08.61#ibcon#about to read 4, iclass 36, count 0 2006.231.07:40:08.61#ibcon#read 4, iclass 36, count 0 2006.231.07:40:08.61#ibcon#about to read 5, iclass 36, count 0 2006.231.07:40:08.61#ibcon#read 5, iclass 36, count 0 2006.231.07:40:08.61#ibcon#about to read 6, iclass 36, count 0 2006.231.07:40:08.61#ibcon#read 6, iclass 36, count 0 2006.231.07:40:08.61#ibcon#end of sib2, iclass 36, count 0 2006.231.07:40:08.61#ibcon#*after write, iclass 36, count 0 2006.231.07:40:08.61#ibcon#*before return 0, iclass 36, count 0 2006.231.07:40:08.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:40:08.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:40:08.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:40:08.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:40:08.61$vc4f8/va=3,8 2006.231.07:40:08.61#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.07:40:08.61#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.07:40:08.61#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:08.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:40:08.67#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:40:08.67#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:40:08.67#ibcon#enter wrdev, iclass 38, count 2 2006.231.07:40:08.67#ibcon#first serial, iclass 38, count 2 2006.231.07:40:08.67#ibcon#enter sib2, iclass 38, count 2 2006.231.07:40:08.67#ibcon#flushed, iclass 38, count 2 2006.231.07:40:08.67#ibcon#about to write, iclass 38, count 2 2006.231.07:40:08.67#ibcon#wrote, iclass 38, count 2 2006.231.07:40:08.67#ibcon#about to read 3, iclass 38, count 2 2006.231.07:40:08.69#ibcon#read 3, iclass 38, count 2 2006.231.07:40:08.69#ibcon#about to read 4, iclass 38, count 2 2006.231.07:40:08.69#ibcon#read 4, iclass 38, count 2 2006.231.07:40:08.69#ibcon#about to read 5, iclass 38, count 2 2006.231.07:40:08.69#ibcon#read 5, iclass 38, count 2 2006.231.07:40:08.69#ibcon#about to read 6, iclass 38, count 2 2006.231.07:40:08.69#ibcon#read 6, iclass 38, count 2 2006.231.07:40:08.69#ibcon#end of sib2, iclass 38, count 2 2006.231.07:40:08.69#ibcon#*mode == 0, iclass 38, count 2 2006.231.07:40:08.69#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.07:40:08.69#ibcon#[25=AT03-08\r\n] 2006.231.07:40:08.69#ibcon#*before write, iclass 38, count 2 2006.231.07:40:08.69#ibcon#enter sib2, iclass 38, count 2 2006.231.07:40:08.69#ibcon#flushed, iclass 38, count 2 2006.231.07:40:08.69#ibcon#about to write, iclass 38, count 2 2006.231.07:40:08.69#ibcon#wrote, iclass 38, count 2 2006.231.07:40:08.69#ibcon#about to read 3, iclass 38, count 2 2006.231.07:40:08.72#ibcon#read 3, iclass 38, count 2 2006.231.07:40:08.72#ibcon#about to read 4, iclass 38, count 2 2006.231.07:40:08.72#ibcon#read 4, iclass 38, count 2 2006.231.07:40:08.72#ibcon#about to read 5, iclass 38, count 2 2006.231.07:40:08.72#ibcon#read 5, iclass 38, count 2 2006.231.07:40:08.72#ibcon#about to read 6, iclass 38, count 2 2006.231.07:40:08.72#ibcon#read 6, iclass 38, count 2 2006.231.07:40:08.72#ibcon#end of sib2, iclass 38, count 2 2006.231.07:40:08.72#ibcon#*after write, iclass 38, count 2 2006.231.07:40:08.72#ibcon#*before return 0, iclass 38, count 2 2006.231.07:40:08.72#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:40:08.72#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:40:08.72#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.07:40:08.72#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:08.72#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:40:08.84#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:40:08.84#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:40:08.84#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:40:08.84#ibcon#first serial, iclass 38, count 0 2006.231.07:40:08.84#ibcon#enter sib2, iclass 38, count 0 2006.231.07:40:08.84#ibcon#flushed, iclass 38, count 0 2006.231.07:40:08.84#ibcon#about to write, iclass 38, count 0 2006.231.07:40:08.84#ibcon#wrote, iclass 38, count 0 2006.231.07:40:08.84#ibcon#about to read 3, iclass 38, count 0 2006.231.07:40:08.86#ibcon#read 3, iclass 38, count 0 2006.231.07:40:08.86#ibcon#about to read 4, iclass 38, count 0 2006.231.07:40:08.86#ibcon#read 4, iclass 38, count 0 2006.231.07:40:08.86#ibcon#about to read 5, iclass 38, count 0 2006.231.07:40:08.86#ibcon#read 5, iclass 38, count 0 2006.231.07:40:08.86#ibcon#about to read 6, iclass 38, count 0 2006.231.07:40:08.86#ibcon#read 6, iclass 38, count 0 2006.231.07:40:08.86#ibcon#end of sib2, iclass 38, count 0 2006.231.07:40:08.86#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:40:08.86#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:40:08.86#ibcon#[25=USB\r\n] 2006.231.07:40:08.86#ibcon#*before write, iclass 38, count 0 2006.231.07:40:08.86#ibcon#enter sib2, iclass 38, count 0 2006.231.07:40:08.86#ibcon#flushed, iclass 38, count 0 2006.231.07:40:08.86#ibcon#about to write, iclass 38, count 0 2006.231.07:40:08.86#ibcon#wrote, iclass 38, count 0 2006.231.07:40:08.86#ibcon#about to read 3, iclass 38, count 0 2006.231.07:40:08.89#ibcon#read 3, iclass 38, count 0 2006.231.07:40:08.89#ibcon#about to read 4, iclass 38, count 0 2006.231.07:40:08.89#ibcon#read 4, iclass 38, count 0 2006.231.07:40:08.89#ibcon#about to read 5, iclass 38, count 0 2006.231.07:40:08.89#ibcon#read 5, iclass 38, count 0 2006.231.07:40:08.89#ibcon#about to read 6, iclass 38, count 0 2006.231.07:40:08.89#ibcon#read 6, iclass 38, count 0 2006.231.07:40:08.89#ibcon#end of sib2, iclass 38, count 0 2006.231.07:40:08.89#ibcon#*after write, iclass 38, count 0 2006.231.07:40:08.89#ibcon#*before return 0, iclass 38, count 0 2006.231.07:40:08.89#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:40:08.89#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:40:08.89#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:40:08.89#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:40:08.89$vc4f8/valo=4,832.99 2006.231.07:40:08.89#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.07:40:08.89#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.07:40:08.89#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:08.89#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:40:08.89#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:40:08.89#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:40:08.89#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:40:08.89#ibcon#first serial, iclass 40, count 0 2006.231.07:40:08.89#ibcon#enter sib2, iclass 40, count 0 2006.231.07:40:08.89#ibcon#flushed, iclass 40, count 0 2006.231.07:40:08.89#ibcon#about to write, iclass 40, count 0 2006.231.07:40:08.89#ibcon#wrote, iclass 40, count 0 2006.231.07:40:08.89#ibcon#about to read 3, iclass 40, count 0 2006.231.07:40:08.91#ibcon#read 3, iclass 40, count 0 2006.231.07:40:08.91#ibcon#about to read 4, iclass 40, count 0 2006.231.07:40:08.91#ibcon#read 4, iclass 40, count 0 2006.231.07:40:08.91#ibcon#about to read 5, iclass 40, count 0 2006.231.07:40:08.91#ibcon#read 5, iclass 40, count 0 2006.231.07:40:08.91#ibcon#about to read 6, iclass 40, count 0 2006.231.07:40:08.91#ibcon#read 6, iclass 40, count 0 2006.231.07:40:08.91#ibcon#end of sib2, iclass 40, count 0 2006.231.07:40:08.91#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:40:08.91#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:40:08.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:40:08.91#ibcon#*before write, iclass 40, count 0 2006.231.07:40:08.91#ibcon#enter sib2, iclass 40, count 0 2006.231.07:40:08.91#ibcon#flushed, iclass 40, count 0 2006.231.07:40:08.91#ibcon#about to write, iclass 40, count 0 2006.231.07:40:08.91#ibcon#wrote, iclass 40, count 0 2006.231.07:40:08.91#ibcon#about to read 3, iclass 40, count 0 2006.231.07:40:08.95#ibcon#read 3, iclass 40, count 0 2006.231.07:40:08.95#ibcon#about to read 4, iclass 40, count 0 2006.231.07:40:08.95#ibcon#read 4, iclass 40, count 0 2006.231.07:40:08.95#ibcon#about to read 5, iclass 40, count 0 2006.231.07:40:08.95#ibcon#read 5, iclass 40, count 0 2006.231.07:40:08.95#ibcon#about to read 6, iclass 40, count 0 2006.231.07:40:08.95#ibcon#read 6, iclass 40, count 0 2006.231.07:40:08.95#ibcon#end of sib2, iclass 40, count 0 2006.231.07:40:08.95#ibcon#*after write, iclass 40, count 0 2006.231.07:40:08.95#ibcon#*before return 0, iclass 40, count 0 2006.231.07:40:08.95#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:40:08.95#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:40:08.95#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:40:08.95#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:40:08.95$vc4f8/va=4,7 2006.231.07:40:08.95#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.231.07:40:08.95#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.231.07:40:08.95#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:08.95#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:40:09.01#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:40:09.01#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:40:09.01#ibcon#enter wrdev, iclass 4, count 2 2006.231.07:40:09.01#ibcon#first serial, iclass 4, count 2 2006.231.07:40:09.01#ibcon#enter sib2, iclass 4, count 2 2006.231.07:40:09.01#ibcon#flushed, iclass 4, count 2 2006.231.07:40:09.01#ibcon#about to write, iclass 4, count 2 2006.231.07:40:09.01#ibcon#wrote, iclass 4, count 2 2006.231.07:40:09.01#ibcon#about to read 3, iclass 4, count 2 2006.231.07:40:09.03#ibcon#read 3, iclass 4, count 2 2006.231.07:40:09.03#ibcon#about to read 4, iclass 4, count 2 2006.231.07:40:09.03#ibcon#read 4, iclass 4, count 2 2006.231.07:40:09.03#ibcon#about to read 5, iclass 4, count 2 2006.231.07:40:09.03#ibcon#read 5, iclass 4, count 2 2006.231.07:40:09.03#ibcon#about to read 6, iclass 4, count 2 2006.231.07:40:09.03#ibcon#read 6, iclass 4, count 2 2006.231.07:40:09.03#ibcon#end of sib2, iclass 4, count 2 2006.231.07:40:09.03#ibcon#*mode == 0, iclass 4, count 2 2006.231.07:40:09.03#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.231.07:40:09.03#ibcon#[25=AT04-07\r\n] 2006.231.07:40:09.03#ibcon#*before write, iclass 4, count 2 2006.231.07:40:09.03#ibcon#enter sib2, iclass 4, count 2 2006.231.07:40:09.03#ibcon#flushed, iclass 4, count 2 2006.231.07:40:09.03#ibcon#about to write, iclass 4, count 2 2006.231.07:40:09.03#ibcon#wrote, iclass 4, count 2 2006.231.07:40:09.03#ibcon#about to read 3, iclass 4, count 2 2006.231.07:40:09.03#abcon#<5=/07 3.0 7.2 30.67 841004.4\r\n> 2006.231.07:40:09.05#abcon#{5=INTERFACE CLEAR} 2006.231.07:40:09.06#ibcon#read 3, iclass 4, count 2 2006.231.07:40:09.06#ibcon#about to read 4, iclass 4, count 2 2006.231.07:40:09.06#ibcon#read 4, iclass 4, count 2 2006.231.07:40:09.06#ibcon#about to read 5, iclass 4, count 2 2006.231.07:40:09.06#ibcon#read 5, iclass 4, count 2 2006.231.07:40:09.06#ibcon#about to read 6, iclass 4, count 2 2006.231.07:40:09.06#ibcon#read 6, iclass 4, count 2 2006.231.07:40:09.06#ibcon#end of sib2, iclass 4, count 2 2006.231.07:40:09.06#ibcon#*after write, iclass 4, count 2 2006.231.07:40:09.06#ibcon#*before return 0, iclass 4, count 2 2006.231.07:40:09.06#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:40:09.06#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:40:09.06#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.231.07:40:09.06#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:09.06#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:40:09.11#abcon#[5=S1D000X0/0*\r\n] 2006.231.07:40:09.18#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:40:09.18#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:40:09.18#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:40:09.18#ibcon#first serial, iclass 4, count 0 2006.231.07:40:09.18#ibcon#enter sib2, iclass 4, count 0 2006.231.07:40:09.18#ibcon#flushed, iclass 4, count 0 2006.231.07:40:09.18#ibcon#about to write, iclass 4, count 0 2006.231.07:40:09.18#ibcon#wrote, iclass 4, count 0 2006.231.07:40:09.18#ibcon#about to read 3, iclass 4, count 0 2006.231.07:40:09.20#ibcon#read 3, iclass 4, count 0 2006.231.07:40:09.20#ibcon#about to read 4, iclass 4, count 0 2006.231.07:40:09.20#ibcon#read 4, iclass 4, count 0 2006.231.07:40:09.20#ibcon#about to read 5, iclass 4, count 0 2006.231.07:40:09.20#ibcon#read 5, iclass 4, count 0 2006.231.07:40:09.20#ibcon#about to read 6, iclass 4, count 0 2006.231.07:40:09.20#ibcon#read 6, iclass 4, count 0 2006.231.07:40:09.20#ibcon#end of sib2, iclass 4, count 0 2006.231.07:40:09.20#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:40:09.20#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:40:09.20#ibcon#[25=USB\r\n] 2006.231.07:40:09.20#ibcon#*before write, iclass 4, count 0 2006.231.07:40:09.20#ibcon#enter sib2, iclass 4, count 0 2006.231.07:40:09.20#ibcon#flushed, iclass 4, count 0 2006.231.07:40:09.20#ibcon#about to write, iclass 4, count 0 2006.231.07:40:09.20#ibcon#wrote, iclass 4, count 0 2006.231.07:40:09.20#ibcon#about to read 3, iclass 4, count 0 2006.231.07:40:09.23#ibcon#read 3, iclass 4, count 0 2006.231.07:40:09.23#ibcon#about to read 4, iclass 4, count 0 2006.231.07:40:09.23#ibcon#read 4, iclass 4, count 0 2006.231.07:40:09.23#ibcon#about to read 5, iclass 4, count 0 2006.231.07:40:09.23#ibcon#read 5, iclass 4, count 0 2006.231.07:40:09.23#ibcon#about to read 6, iclass 4, count 0 2006.231.07:40:09.23#ibcon#read 6, iclass 4, count 0 2006.231.07:40:09.23#ibcon#end of sib2, iclass 4, count 0 2006.231.07:40:09.23#ibcon#*after write, iclass 4, count 0 2006.231.07:40:09.23#ibcon#*before return 0, iclass 4, count 0 2006.231.07:40:09.23#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:40:09.23#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:40:09.23#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:40:09.23#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:40:09.23$vc4f8/valo=5,652.99 2006.231.07:40:09.23#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.07:40:09.23#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.07:40:09.23#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:09.23#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:40:09.23#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:40:09.23#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:40:09.23#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:40:09.23#ibcon#first serial, iclass 12, count 0 2006.231.07:40:09.23#ibcon#enter sib2, iclass 12, count 0 2006.231.07:40:09.23#ibcon#flushed, iclass 12, count 0 2006.231.07:40:09.23#ibcon#about to write, iclass 12, count 0 2006.231.07:40:09.23#ibcon#wrote, iclass 12, count 0 2006.231.07:40:09.23#ibcon#about to read 3, iclass 12, count 0 2006.231.07:40:09.25#ibcon#read 3, iclass 12, count 0 2006.231.07:40:09.25#ibcon#about to read 4, iclass 12, count 0 2006.231.07:40:09.25#ibcon#read 4, iclass 12, count 0 2006.231.07:40:09.25#ibcon#about to read 5, iclass 12, count 0 2006.231.07:40:09.25#ibcon#read 5, iclass 12, count 0 2006.231.07:40:09.25#ibcon#about to read 6, iclass 12, count 0 2006.231.07:40:09.25#ibcon#read 6, iclass 12, count 0 2006.231.07:40:09.25#ibcon#end of sib2, iclass 12, count 0 2006.231.07:40:09.25#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:40:09.25#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:40:09.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:40:09.25#ibcon#*before write, iclass 12, count 0 2006.231.07:40:09.25#ibcon#enter sib2, iclass 12, count 0 2006.231.07:40:09.25#ibcon#flushed, iclass 12, count 0 2006.231.07:40:09.25#ibcon#about to write, iclass 12, count 0 2006.231.07:40:09.25#ibcon#wrote, iclass 12, count 0 2006.231.07:40:09.25#ibcon#about to read 3, iclass 12, count 0 2006.231.07:40:09.29#ibcon#read 3, iclass 12, count 0 2006.231.07:40:09.29#ibcon#about to read 4, iclass 12, count 0 2006.231.07:40:09.29#ibcon#read 4, iclass 12, count 0 2006.231.07:40:09.29#ibcon#about to read 5, iclass 12, count 0 2006.231.07:40:09.29#ibcon#read 5, iclass 12, count 0 2006.231.07:40:09.29#ibcon#about to read 6, iclass 12, count 0 2006.231.07:40:09.29#ibcon#read 6, iclass 12, count 0 2006.231.07:40:09.29#ibcon#end of sib2, iclass 12, count 0 2006.231.07:40:09.29#ibcon#*after write, iclass 12, count 0 2006.231.07:40:09.29#ibcon#*before return 0, iclass 12, count 0 2006.231.07:40:09.29#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:40:09.29#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:40:09.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:40:09.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:40:09.29$vc4f8/va=5,7 2006.231.07:40:09.29#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.07:40:09.29#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.07:40:09.29#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:09.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:40:09.35#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:40:09.35#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:40:09.35#ibcon#enter wrdev, iclass 14, count 2 2006.231.07:40:09.35#ibcon#first serial, iclass 14, count 2 2006.231.07:40:09.35#ibcon#enter sib2, iclass 14, count 2 2006.231.07:40:09.35#ibcon#flushed, iclass 14, count 2 2006.231.07:40:09.35#ibcon#about to write, iclass 14, count 2 2006.231.07:40:09.35#ibcon#wrote, iclass 14, count 2 2006.231.07:40:09.35#ibcon#about to read 3, iclass 14, count 2 2006.231.07:40:09.37#ibcon#read 3, iclass 14, count 2 2006.231.07:40:09.37#ibcon#about to read 4, iclass 14, count 2 2006.231.07:40:09.37#ibcon#read 4, iclass 14, count 2 2006.231.07:40:09.37#ibcon#about to read 5, iclass 14, count 2 2006.231.07:40:09.37#ibcon#read 5, iclass 14, count 2 2006.231.07:40:09.37#ibcon#about to read 6, iclass 14, count 2 2006.231.07:40:09.37#ibcon#read 6, iclass 14, count 2 2006.231.07:40:09.37#ibcon#end of sib2, iclass 14, count 2 2006.231.07:40:09.37#ibcon#*mode == 0, iclass 14, count 2 2006.231.07:40:09.37#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.07:40:09.37#ibcon#[25=AT05-07\r\n] 2006.231.07:40:09.37#ibcon#*before write, iclass 14, count 2 2006.231.07:40:09.37#ibcon#enter sib2, iclass 14, count 2 2006.231.07:40:09.37#ibcon#flushed, iclass 14, count 2 2006.231.07:40:09.37#ibcon#about to write, iclass 14, count 2 2006.231.07:40:09.37#ibcon#wrote, iclass 14, count 2 2006.231.07:40:09.37#ibcon#about to read 3, iclass 14, count 2 2006.231.07:40:09.40#ibcon#read 3, iclass 14, count 2 2006.231.07:40:09.40#ibcon#about to read 4, iclass 14, count 2 2006.231.07:40:09.40#ibcon#read 4, iclass 14, count 2 2006.231.07:40:09.40#ibcon#about to read 5, iclass 14, count 2 2006.231.07:40:09.40#ibcon#read 5, iclass 14, count 2 2006.231.07:40:09.40#ibcon#about to read 6, iclass 14, count 2 2006.231.07:40:09.40#ibcon#read 6, iclass 14, count 2 2006.231.07:40:09.40#ibcon#end of sib2, iclass 14, count 2 2006.231.07:40:09.40#ibcon#*after write, iclass 14, count 2 2006.231.07:40:09.40#ibcon#*before return 0, iclass 14, count 2 2006.231.07:40:09.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:40:09.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:40:09.40#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.07:40:09.40#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:09.40#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:40:09.52#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:40:09.52#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:40:09.52#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:40:09.52#ibcon#first serial, iclass 14, count 0 2006.231.07:40:09.52#ibcon#enter sib2, iclass 14, count 0 2006.231.07:40:09.52#ibcon#flushed, iclass 14, count 0 2006.231.07:40:09.52#ibcon#about to write, iclass 14, count 0 2006.231.07:40:09.52#ibcon#wrote, iclass 14, count 0 2006.231.07:40:09.52#ibcon#about to read 3, iclass 14, count 0 2006.231.07:40:09.54#ibcon#read 3, iclass 14, count 0 2006.231.07:40:09.54#ibcon#about to read 4, iclass 14, count 0 2006.231.07:40:09.54#ibcon#read 4, iclass 14, count 0 2006.231.07:40:09.54#ibcon#about to read 5, iclass 14, count 0 2006.231.07:40:09.54#ibcon#read 5, iclass 14, count 0 2006.231.07:40:09.54#ibcon#about to read 6, iclass 14, count 0 2006.231.07:40:09.54#ibcon#read 6, iclass 14, count 0 2006.231.07:40:09.54#ibcon#end of sib2, iclass 14, count 0 2006.231.07:40:09.54#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:40:09.54#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:40:09.54#ibcon#[25=USB\r\n] 2006.231.07:40:09.54#ibcon#*before write, iclass 14, count 0 2006.231.07:40:09.54#ibcon#enter sib2, iclass 14, count 0 2006.231.07:40:09.54#ibcon#flushed, iclass 14, count 0 2006.231.07:40:09.54#ibcon#about to write, iclass 14, count 0 2006.231.07:40:09.54#ibcon#wrote, iclass 14, count 0 2006.231.07:40:09.54#ibcon#about to read 3, iclass 14, count 0 2006.231.07:40:09.57#ibcon#read 3, iclass 14, count 0 2006.231.07:40:09.57#ibcon#about to read 4, iclass 14, count 0 2006.231.07:40:09.57#ibcon#read 4, iclass 14, count 0 2006.231.07:40:09.57#ibcon#about to read 5, iclass 14, count 0 2006.231.07:40:09.57#ibcon#read 5, iclass 14, count 0 2006.231.07:40:09.57#ibcon#about to read 6, iclass 14, count 0 2006.231.07:40:09.57#ibcon#read 6, iclass 14, count 0 2006.231.07:40:09.57#ibcon#end of sib2, iclass 14, count 0 2006.231.07:40:09.57#ibcon#*after write, iclass 14, count 0 2006.231.07:40:09.57#ibcon#*before return 0, iclass 14, count 0 2006.231.07:40:09.57#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:40:09.57#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:40:09.57#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:40:09.57#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:40:09.57$vc4f8/valo=6,772.99 2006.231.07:40:09.57#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.07:40:09.57#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.07:40:09.57#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:09.57#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:40:09.57#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:40:09.57#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:40:09.57#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:40:09.57#ibcon#first serial, iclass 16, count 0 2006.231.07:40:09.57#ibcon#enter sib2, iclass 16, count 0 2006.231.07:40:09.57#ibcon#flushed, iclass 16, count 0 2006.231.07:40:09.57#ibcon#about to write, iclass 16, count 0 2006.231.07:40:09.57#ibcon#wrote, iclass 16, count 0 2006.231.07:40:09.57#ibcon#about to read 3, iclass 16, count 0 2006.231.07:40:09.59#ibcon#read 3, iclass 16, count 0 2006.231.07:40:09.59#ibcon#about to read 4, iclass 16, count 0 2006.231.07:40:09.59#ibcon#read 4, iclass 16, count 0 2006.231.07:40:09.59#ibcon#about to read 5, iclass 16, count 0 2006.231.07:40:09.59#ibcon#read 5, iclass 16, count 0 2006.231.07:40:09.59#ibcon#about to read 6, iclass 16, count 0 2006.231.07:40:09.59#ibcon#read 6, iclass 16, count 0 2006.231.07:40:09.59#ibcon#end of sib2, iclass 16, count 0 2006.231.07:40:09.59#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:40:09.59#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:40:09.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:40:09.59#ibcon#*before write, iclass 16, count 0 2006.231.07:40:09.59#ibcon#enter sib2, iclass 16, count 0 2006.231.07:40:09.59#ibcon#flushed, iclass 16, count 0 2006.231.07:40:09.59#ibcon#about to write, iclass 16, count 0 2006.231.07:40:09.59#ibcon#wrote, iclass 16, count 0 2006.231.07:40:09.59#ibcon#about to read 3, iclass 16, count 0 2006.231.07:40:09.63#ibcon#read 3, iclass 16, count 0 2006.231.07:40:09.63#ibcon#about to read 4, iclass 16, count 0 2006.231.07:40:09.63#ibcon#read 4, iclass 16, count 0 2006.231.07:40:09.63#ibcon#about to read 5, iclass 16, count 0 2006.231.07:40:09.63#ibcon#read 5, iclass 16, count 0 2006.231.07:40:09.63#ibcon#about to read 6, iclass 16, count 0 2006.231.07:40:09.63#ibcon#read 6, iclass 16, count 0 2006.231.07:40:09.63#ibcon#end of sib2, iclass 16, count 0 2006.231.07:40:09.63#ibcon#*after write, iclass 16, count 0 2006.231.07:40:09.63#ibcon#*before return 0, iclass 16, count 0 2006.231.07:40:09.63#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:40:09.63#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:40:09.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:40:09.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:40:09.63$vc4f8/va=6,6 2006.231.07:40:09.63#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.231.07:40:09.63#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.231.07:40:09.63#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:09.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:40:09.69#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:40:09.69#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:40:09.69#ibcon#enter wrdev, iclass 18, count 2 2006.231.07:40:09.69#ibcon#first serial, iclass 18, count 2 2006.231.07:40:09.69#ibcon#enter sib2, iclass 18, count 2 2006.231.07:40:09.69#ibcon#flushed, iclass 18, count 2 2006.231.07:40:09.69#ibcon#about to write, iclass 18, count 2 2006.231.07:40:09.69#ibcon#wrote, iclass 18, count 2 2006.231.07:40:09.69#ibcon#about to read 3, iclass 18, count 2 2006.231.07:40:09.71#ibcon#read 3, iclass 18, count 2 2006.231.07:40:09.71#ibcon#about to read 4, iclass 18, count 2 2006.231.07:40:09.71#ibcon#read 4, iclass 18, count 2 2006.231.07:40:09.71#ibcon#about to read 5, iclass 18, count 2 2006.231.07:40:09.71#ibcon#read 5, iclass 18, count 2 2006.231.07:40:09.71#ibcon#about to read 6, iclass 18, count 2 2006.231.07:40:09.71#ibcon#read 6, iclass 18, count 2 2006.231.07:40:09.71#ibcon#end of sib2, iclass 18, count 2 2006.231.07:40:09.71#ibcon#*mode == 0, iclass 18, count 2 2006.231.07:40:09.71#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.231.07:40:09.71#ibcon#[25=AT06-06\r\n] 2006.231.07:40:09.71#ibcon#*before write, iclass 18, count 2 2006.231.07:40:09.71#ibcon#enter sib2, iclass 18, count 2 2006.231.07:40:09.71#ibcon#flushed, iclass 18, count 2 2006.231.07:40:09.71#ibcon#about to write, iclass 18, count 2 2006.231.07:40:09.71#ibcon#wrote, iclass 18, count 2 2006.231.07:40:09.71#ibcon#about to read 3, iclass 18, count 2 2006.231.07:40:09.74#ibcon#read 3, iclass 18, count 2 2006.231.07:40:09.74#ibcon#about to read 4, iclass 18, count 2 2006.231.07:40:09.74#ibcon#read 4, iclass 18, count 2 2006.231.07:40:09.74#ibcon#about to read 5, iclass 18, count 2 2006.231.07:40:09.74#ibcon#read 5, iclass 18, count 2 2006.231.07:40:09.74#ibcon#about to read 6, iclass 18, count 2 2006.231.07:40:09.74#ibcon#read 6, iclass 18, count 2 2006.231.07:40:09.74#ibcon#end of sib2, iclass 18, count 2 2006.231.07:40:09.74#ibcon#*after write, iclass 18, count 2 2006.231.07:40:09.74#ibcon#*before return 0, iclass 18, count 2 2006.231.07:40:09.74#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:40:09.74#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:40:09.74#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.231.07:40:09.74#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:09.74#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:40:09.86#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:40:09.86#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:40:09.86#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:40:09.86#ibcon#first serial, iclass 18, count 0 2006.231.07:40:09.86#ibcon#enter sib2, iclass 18, count 0 2006.231.07:40:09.86#ibcon#flushed, iclass 18, count 0 2006.231.07:40:09.86#ibcon#about to write, iclass 18, count 0 2006.231.07:40:09.86#ibcon#wrote, iclass 18, count 0 2006.231.07:40:09.86#ibcon#about to read 3, iclass 18, count 0 2006.231.07:40:09.88#ibcon#read 3, iclass 18, count 0 2006.231.07:40:09.88#ibcon#about to read 4, iclass 18, count 0 2006.231.07:40:09.88#ibcon#read 4, iclass 18, count 0 2006.231.07:40:09.88#ibcon#about to read 5, iclass 18, count 0 2006.231.07:40:09.88#ibcon#read 5, iclass 18, count 0 2006.231.07:40:09.88#ibcon#about to read 6, iclass 18, count 0 2006.231.07:40:09.88#ibcon#read 6, iclass 18, count 0 2006.231.07:40:09.88#ibcon#end of sib2, iclass 18, count 0 2006.231.07:40:09.88#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:40:09.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:40:09.88#ibcon#[25=USB\r\n] 2006.231.07:40:09.88#ibcon#*before write, iclass 18, count 0 2006.231.07:40:09.88#ibcon#enter sib2, iclass 18, count 0 2006.231.07:40:09.88#ibcon#flushed, iclass 18, count 0 2006.231.07:40:09.88#ibcon#about to write, iclass 18, count 0 2006.231.07:40:09.88#ibcon#wrote, iclass 18, count 0 2006.231.07:40:09.88#ibcon#about to read 3, iclass 18, count 0 2006.231.07:40:09.91#ibcon#read 3, iclass 18, count 0 2006.231.07:40:09.91#ibcon#about to read 4, iclass 18, count 0 2006.231.07:40:09.91#ibcon#read 4, iclass 18, count 0 2006.231.07:40:09.91#ibcon#about to read 5, iclass 18, count 0 2006.231.07:40:09.91#ibcon#read 5, iclass 18, count 0 2006.231.07:40:09.91#ibcon#about to read 6, iclass 18, count 0 2006.231.07:40:09.91#ibcon#read 6, iclass 18, count 0 2006.231.07:40:09.91#ibcon#end of sib2, iclass 18, count 0 2006.231.07:40:09.91#ibcon#*after write, iclass 18, count 0 2006.231.07:40:09.91#ibcon#*before return 0, iclass 18, count 0 2006.231.07:40:09.91#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:40:09.91#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:40:09.91#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:40:09.91#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:40:09.91$vc4f8/valo=7,832.99 2006.231.07:40:09.91#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.231.07:40:09.91#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.231.07:40:09.91#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:09.91#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:40:09.91#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:40:09.91#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:40:09.91#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:40:09.91#ibcon#first serial, iclass 20, count 0 2006.231.07:40:09.91#ibcon#enter sib2, iclass 20, count 0 2006.231.07:40:09.91#ibcon#flushed, iclass 20, count 0 2006.231.07:40:09.91#ibcon#about to write, iclass 20, count 0 2006.231.07:40:09.91#ibcon#wrote, iclass 20, count 0 2006.231.07:40:09.91#ibcon#about to read 3, iclass 20, count 0 2006.231.07:40:09.93#ibcon#read 3, iclass 20, count 0 2006.231.07:40:09.93#ibcon#about to read 4, iclass 20, count 0 2006.231.07:40:09.93#ibcon#read 4, iclass 20, count 0 2006.231.07:40:09.93#ibcon#about to read 5, iclass 20, count 0 2006.231.07:40:09.93#ibcon#read 5, iclass 20, count 0 2006.231.07:40:09.93#ibcon#about to read 6, iclass 20, count 0 2006.231.07:40:09.93#ibcon#read 6, iclass 20, count 0 2006.231.07:40:09.93#ibcon#end of sib2, iclass 20, count 0 2006.231.07:40:09.93#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:40:09.93#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:40:09.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:40:09.93#ibcon#*before write, iclass 20, count 0 2006.231.07:40:09.93#ibcon#enter sib2, iclass 20, count 0 2006.231.07:40:09.93#ibcon#flushed, iclass 20, count 0 2006.231.07:40:09.93#ibcon#about to write, iclass 20, count 0 2006.231.07:40:09.93#ibcon#wrote, iclass 20, count 0 2006.231.07:40:09.93#ibcon#about to read 3, iclass 20, count 0 2006.231.07:40:09.97#ibcon#read 3, iclass 20, count 0 2006.231.07:40:09.97#ibcon#about to read 4, iclass 20, count 0 2006.231.07:40:09.97#ibcon#read 4, iclass 20, count 0 2006.231.07:40:09.97#ibcon#about to read 5, iclass 20, count 0 2006.231.07:40:09.97#ibcon#read 5, iclass 20, count 0 2006.231.07:40:09.97#ibcon#about to read 6, iclass 20, count 0 2006.231.07:40:09.97#ibcon#read 6, iclass 20, count 0 2006.231.07:40:09.97#ibcon#end of sib2, iclass 20, count 0 2006.231.07:40:09.97#ibcon#*after write, iclass 20, count 0 2006.231.07:40:09.97#ibcon#*before return 0, iclass 20, count 0 2006.231.07:40:09.97#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:40:09.97#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:40:09.97#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:40:09.97#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:40:09.97$vc4f8/va=7,6 2006.231.07:40:09.97#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.231.07:40:09.97#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.231.07:40:09.97#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:09.97#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:40:10.03#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:40:10.03#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:40:10.03#ibcon#enter wrdev, iclass 22, count 2 2006.231.07:40:10.03#ibcon#first serial, iclass 22, count 2 2006.231.07:40:10.03#ibcon#enter sib2, iclass 22, count 2 2006.231.07:40:10.03#ibcon#flushed, iclass 22, count 2 2006.231.07:40:10.03#ibcon#about to write, iclass 22, count 2 2006.231.07:40:10.03#ibcon#wrote, iclass 22, count 2 2006.231.07:40:10.03#ibcon#about to read 3, iclass 22, count 2 2006.231.07:40:10.05#ibcon#read 3, iclass 22, count 2 2006.231.07:40:10.05#ibcon#about to read 4, iclass 22, count 2 2006.231.07:40:10.05#ibcon#read 4, iclass 22, count 2 2006.231.07:40:10.05#ibcon#about to read 5, iclass 22, count 2 2006.231.07:40:10.05#ibcon#read 5, iclass 22, count 2 2006.231.07:40:10.05#ibcon#about to read 6, iclass 22, count 2 2006.231.07:40:10.05#ibcon#read 6, iclass 22, count 2 2006.231.07:40:10.05#ibcon#end of sib2, iclass 22, count 2 2006.231.07:40:10.05#ibcon#*mode == 0, iclass 22, count 2 2006.231.07:40:10.05#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.231.07:40:10.05#ibcon#[25=AT07-06\r\n] 2006.231.07:40:10.05#ibcon#*before write, iclass 22, count 2 2006.231.07:40:10.05#ibcon#enter sib2, iclass 22, count 2 2006.231.07:40:10.05#ibcon#flushed, iclass 22, count 2 2006.231.07:40:10.05#ibcon#about to write, iclass 22, count 2 2006.231.07:40:10.05#ibcon#wrote, iclass 22, count 2 2006.231.07:40:10.05#ibcon#about to read 3, iclass 22, count 2 2006.231.07:40:10.08#ibcon#read 3, iclass 22, count 2 2006.231.07:40:10.08#ibcon#about to read 4, iclass 22, count 2 2006.231.07:40:10.08#ibcon#read 4, iclass 22, count 2 2006.231.07:40:10.08#ibcon#about to read 5, iclass 22, count 2 2006.231.07:40:10.08#ibcon#read 5, iclass 22, count 2 2006.231.07:40:10.08#ibcon#about to read 6, iclass 22, count 2 2006.231.07:40:10.08#ibcon#read 6, iclass 22, count 2 2006.231.07:40:10.08#ibcon#end of sib2, iclass 22, count 2 2006.231.07:40:10.08#ibcon#*after write, iclass 22, count 2 2006.231.07:40:10.08#ibcon#*before return 0, iclass 22, count 2 2006.231.07:40:10.08#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:40:10.08#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:40:10.08#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.231.07:40:10.08#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:10.08#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:40:10.20#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:40:10.20#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:40:10.20#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:40:10.20#ibcon#first serial, iclass 22, count 0 2006.231.07:40:10.20#ibcon#enter sib2, iclass 22, count 0 2006.231.07:40:10.20#ibcon#flushed, iclass 22, count 0 2006.231.07:40:10.20#ibcon#about to write, iclass 22, count 0 2006.231.07:40:10.20#ibcon#wrote, iclass 22, count 0 2006.231.07:40:10.20#ibcon#about to read 3, iclass 22, count 0 2006.231.07:40:10.22#ibcon#read 3, iclass 22, count 0 2006.231.07:40:10.22#ibcon#about to read 4, iclass 22, count 0 2006.231.07:40:10.22#ibcon#read 4, iclass 22, count 0 2006.231.07:40:10.22#ibcon#about to read 5, iclass 22, count 0 2006.231.07:40:10.22#ibcon#read 5, iclass 22, count 0 2006.231.07:40:10.22#ibcon#about to read 6, iclass 22, count 0 2006.231.07:40:10.22#ibcon#read 6, iclass 22, count 0 2006.231.07:40:10.22#ibcon#end of sib2, iclass 22, count 0 2006.231.07:40:10.22#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:40:10.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:40:10.22#ibcon#[25=USB\r\n] 2006.231.07:40:10.22#ibcon#*before write, iclass 22, count 0 2006.231.07:40:10.22#ibcon#enter sib2, iclass 22, count 0 2006.231.07:40:10.22#ibcon#flushed, iclass 22, count 0 2006.231.07:40:10.22#ibcon#about to write, iclass 22, count 0 2006.231.07:40:10.22#ibcon#wrote, iclass 22, count 0 2006.231.07:40:10.22#ibcon#about to read 3, iclass 22, count 0 2006.231.07:40:10.25#ibcon#read 3, iclass 22, count 0 2006.231.07:40:10.25#ibcon#about to read 4, iclass 22, count 0 2006.231.07:40:10.25#ibcon#read 4, iclass 22, count 0 2006.231.07:40:10.25#ibcon#about to read 5, iclass 22, count 0 2006.231.07:40:10.25#ibcon#read 5, iclass 22, count 0 2006.231.07:40:10.25#ibcon#about to read 6, iclass 22, count 0 2006.231.07:40:10.25#ibcon#read 6, iclass 22, count 0 2006.231.07:40:10.25#ibcon#end of sib2, iclass 22, count 0 2006.231.07:40:10.25#ibcon#*after write, iclass 22, count 0 2006.231.07:40:10.25#ibcon#*before return 0, iclass 22, count 0 2006.231.07:40:10.25#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:40:10.25#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:40:10.25#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:40:10.25#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:40:10.25$vc4f8/valo=8,852.99 2006.231.07:40:10.25#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.231.07:40:10.25#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.231.07:40:10.25#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:10.25#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:40:10.25#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:40:10.25#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:40:10.25#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:40:10.25#ibcon#first serial, iclass 24, count 0 2006.231.07:40:10.25#ibcon#enter sib2, iclass 24, count 0 2006.231.07:40:10.25#ibcon#flushed, iclass 24, count 0 2006.231.07:40:10.25#ibcon#about to write, iclass 24, count 0 2006.231.07:40:10.25#ibcon#wrote, iclass 24, count 0 2006.231.07:40:10.25#ibcon#about to read 3, iclass 24, count 0 2006.231.07:40:10.27#ibcon#read 3, iclass 24, count 0 2006.231.07:40:10.27#ibcon#about to read 4, iclass 24, count 0 2006.231.07:40:10.27#ibcon#read 4, iclass 24, count 0 2006.231.07:40:10.27#ibcon#about to read 5, iclass 24, count 0 2006.231.07:40:10.27#ibcon#read 5, iclass 24, count 0 2006.231.07:40:10.27#ibcon#about to read 6, iclass 24, count 0 2006.231.07:40:10.27#ibcon#read 6, iclass 24, count 0 2006.231.07:40:10.27#ibcon#end of sib2, iclass 24, count 0 2006.231.07:40:10.27#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:40:10.27#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:40:10.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:40:10.27#ibcon#*before write, iclass 24, count 0 2006.231.07:40:10.27#ibcon#enter sib2, iclass 24, count 0 2006.231.07:40:10.27#ibcon#flushed, iclass 24, count 0 2006.231.07:40:10.27#ibcon#about to write, iclass 24, count 0 2006.231.07:40:10.27#ibcon#wrote, iclass 24, count 0 2006.231.07:40:10.27#ibcon#about to read 3, iclass 24, count 0 2006.231.07:40:10.31#ibcon#read 3, iclass 24, count 0 2006.231.07:40:10.31#ibcon#about to read 4, iclass 24, count 0 2006.231.07:40:10.31#ibcon#read 4, iclass 24, count 0 2006.231.07:40:10.31#ibcon#about to read 5, iclass 24, count 0 2006.231.07:40:10.31#ibcon#read 5, iclass 24, count 0 2006.231.07:40:10.31#ibcon#about to read 6, iclass 24, count 0 2006.231.07:40:10.31#ibcon#read 6, iclass 24, count 0 2006.231.07:40:10.31#ibcon#end of sib2, iclass 24, count 0 2006.231.07:40:10.31#ibcon#*after write, iclass 24, count 0 2006.231.07:40:10.31#ibcon#*before return 0, iclass 24, count 0 2006.231.07:40:10.31#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:40:10.31#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:40:10.31#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:40:10.31#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:40:10.31$vc4f8/va=8,6 2006.231.07:40:10.31#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.231.07:40:10.31#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.231.07:40:10.31#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:10.31#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:40:10.37#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:40:10.37#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:40:10.37#ibcon#enter wrdev, iclass 26, count 2 2006.231.07:40:10.37#ibcon#first serial, iclass 26, count 2 2006.231.07:40:10.37#ibcon#enter sib2, iclass 26, count 2 2006.231.07:40:10.37#ibcon#flushed, iclass 26, count 2 2006.231.07:40:10.37#ibcon#about to write, iclass 26, count 2 2006.231.07:40:10.37#ibcon#wrote, iclass 26, count 2 2006.231.07:40:10.37#ibcon#about to read 3, iclass 26, count 2 2006.231.07:40:10.39#ibcon#read 3, iclass 26, count 2 2006.231.07:40:10.39#ibcon#about to read 4, iclass 26, count 2 2006.231.07:40:10.39#ibcon#read 4, iclass 26, count 2 2006.231.07:40:10.39#ibcon#about to read 5, iclass 26, count 2 2006.231.07:40:10.39#ibcon#read 5, iclass 26, count 2 2006.231.07:40:10.39#ibcon#about to read 6, iclass 26, count 2 2006.231.07:40:10.39#ibcon#read 6, iclass 26, count 2 2006.231.07:40:10.39#ibcon#end of sib2, iclass 26, count 2 2006.231.07:40:10.39#ibcon#*mode == 0, iclass 26, count 2 2006.231.07:40:10.39#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.231.07:40:10.39#ibcon#[25=AT08-06\r\n] 2006.231.07:40:10.39#ibcon#*before write, iclass 26, count 2 2006.231.07:40:10.39#ibcon#enter sib2, iclass 26, count 2 2006.231.07:40:10.39#ibcon#flushed, iclass 26, count 2 2006.231.07:40:10.39#ibcon#about to write, iclass 26, count 2 2006.231.07:40:10.39#ibcon#wrote, iclass 26, count 2 2006.231.07:40:10.39#ibcon#about to read 3, iclass 26, count 2 2006.231.07:40:10.42#ibcon#read 3, iclass 26, count 2 2006.231.07:40:10.42#ibcon#about to read 4, iclass 26, count 2 2006.231.07:40:10.42#ibcon#read 4, iclass 26, count 2 2006.231.07:40:10.42#ibcon#about to read 5, iclass 26, count 2 2006.231.07:40:10.42#ibcon#read 5, iclass 26, count 2 2006.231.07:40:10.42#ibcon#about to read 6, iclass 26, count 2 2006.231.07:40:10.42#ibcon#read 6, iclass 26, count 2 2006.231.07:40:10.42#ibcon#end of sib2, iclass 26, count 2 2006.231.07:40:10.42#ibcon#*after write, iclass 26, count 2 2006.231.07:40:10.42#ibcon#*before return 0, iclass 26, count 2 2006.231.07:40:10.42#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:40:10.42#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:40:10.42#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.231.07:40:10.42#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:10.42#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:40:10.54#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:40:10.54#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:40:10.54#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:40:10.54#ibcon#first serial, iclass 26, count 0 2006.231.07:40:10.54#ibcon#enter sib2, iclass 26, count 0 2006.231.07:40:10.54#ibcon#flushed, iclass 26, count 0 2006.231.07:40:10.54#ibcon#about to write, iclass 26, count 0 2006.231.07:40:10.54#ibcon#wrote, iclass 26, count 0 2006.231.07:40:10.54#ibcon#about to read 3, iclass 26, count 0 2006.231.07:40:10.56#ibcon#read 3, iclass 26, count 0 2006.231.07:40:10.56#ibcon#about to read 4, iclass 26, count 0 2006.231.07:40:10.56#ibcon#read 4, iclass 26, count 0 2006.231.07:40:10.56#ibcon#about to read 5, iclass 26, count 0 2006.231.07:40:10.56#ibcon#read 5, iclass 26, count 0 2006.231.07:40:10.56#ibcon#about to read 6, iclass 26, count 0 2006.231.07:40:10.56#ibcon#read 6, iclass 26, count 0 2006.231.07:40:10.56#ibcon#end of sib2, iclass 26, count 0 2006.231.07:40:10.56#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:40:10.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:40:10.56#ibcon#[25=USB\r\n] 2006.231.07:40:10.56#ibcon#*before write, iclass 26, count 0 2006.231.07:40:10.56#ibcon#enter sib2, iclass 26, count 0 2006.231.07:40:10.56#ibcon#flushed, iclass 26, count 0 2006.231.07:40:10.56#ibcon#about to write, iclass 26, count 0 2006.231.07:40:10.56#ibcon#wrote, iclass 26, count 0 2006.231.07:40:10.56#ibcon#about to read 3, iclass 26, count 0 2006.231.07:40:10.59#ibcon#read 3, iclass 26, count 0 2006.231.07:40:10.59#ibcon#about to read 4, iclass 26, count 0 2006.231.07:40:10.59#ibcon#read 4, iclass 26, count 0 2006.231.07:40:10.59#ibcon#about to read 5, iclass 26, count 0 2006.231.07:40:10.59#ibcon#read 5, iclass 26, count 0 2006.231.07:40:10.59#ibcon#about to read 6, iclass 26, count 0 2006.231.07:40:10.59#ibcon#read 6, iclass 26, count 0 2006.231.07:40:10.59#ibcon#end of sib2, iclass 26, count 0 2006.231.07:40:10.59#ibcon#*after write, iclass 26, count 0 2006.231.07:40:10.59#ibcon#*before return 0, iclass 26, count 0 2006.231.07:40:10.59#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:40:10.59#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:40:10.59#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:40:10.59#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:40:10.59$vc4f8/vblo=1,632.99 2006.231.07:40:10.59#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.231.07:40:10.59#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.231.07:40:10.59#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:10.59#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:40:10.59#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:40:10.59#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:40:10.59#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:40:10.59#ibcon#first serial, iclass 28, count 0 2006.231.07:40:10.59#ibcon#enter sib2, iclass 28, count 0 2006.231.07:40:10.59#ibcon#flushed, iclass 28, count 0 2006.231.07:40:10.59#ibcon#about to write, iclass 28, count 0 2006.231.07:40:10.59#ibcon#wrote, iclass 28, count 0 2006.231.07:40:10.59#ibcon#about to read 3, iclass 28, count 0 2006.231.07:40:10.61#ibcon#read 3, iclass 28, count 0 2006.231.07:40:10.61#ibcon#about to read 4, iclass 28, count 0 2006.231.07:40:10.61#ibcon#read 4, iclass 28, count 0 2006.231.07:40:10.61#ibcon#about to read 5, iclass 28, count 0 2006.231.07:40:10.61#ibcon#read 5, iclass 28, count 0 2006.231.07:40:10.61#ibcon#about to read 6, iclass 28, count 0 2006.231.07:40:10.61#ibcon#read 6, iclass 28, count 0 2006.231.07:40:10.61#ibcon#end of sib2, iclass 28, count 0 2006.231.07:40:10.61#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:40:10.61#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:40:10.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:40:10.61#ibcon#*before write, iclass 28, count 0 2006.231.07:40:10.61#ibcon#enter sib2, iclass 28, count 0 2006.231.07:40:10.61#ibcon#flushed, iclass 28, count 0 2006.231.07:40:10.61#ibcon#about to write, iclass 28, count 0 2006.231.07:40:10.61#ibcon#wrote, iclass 28, count 0 2006.231.07:40:10.61#ibcon#about to read 3, iclass 28, count 0 2006.231.07:40:10.65#ibcon#read 3, iclass 28, count 0 2006.231.07:40:10.65#ibcon#about to read 4, iclass 28, count 0 2006.231.07:40:10.65#ibcon#read 4, iclass 28, count 0 2006.231.07:40:10.65#ibcon#about to read 5, iclass 28, count 0 2006.231.07:40:10.65#ibcon#read 5, iclass 28, count 0 2006.231.07:40:10.65#ibcon#about to read 6, iclass 28, count 0 2006.231.07:40:10.65#ibcon#read 6, iclass 28, count 0 2006.231.07:40:10.65#ibcon#end of sib2, iclass 28, count 0 2006.231.07:40:10.65#ibcon#*after write, iclass 28, count 0 2006.231.07:40:10.65#ibcon#*before return 0, iclass 28, count 0 2006.231.07:40:10.65#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:40:10.65#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:40:10.65#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:40:10.65#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:40:10.65$vc4f8/vb=1,4 2006.231.07:40:10.65#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.07:40:10.65#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.07:40:10.65#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:10.65#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:40:10.65#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:40:10.65#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:40:10.65#ibcon#enter wrdev, iclass 30, count 2 2006.231.07:40:10.65#ibcon#first serial, iclass 30, count 2 2006.231.07:40:10.65#ibcon#enter sib2, iclass 30, count 2 2006.231.07:40:10.65#ibcon#flushed, iclass 30, count 2 2006.231.07:40:10.65#ibcon#about to write, iclass 30, count 2 2006.231.07:40:10.65#ibcon#wrote, iclass 30, count 2 2006.231.07:40:10.65#ibcon#about to read 3, iclass 30, count 2 2006.231.07:40:10.67#ibcon#read 3, iclass 30, count 2 2006.231.07:40:10.67#ibcon#about to read 4, iclass 30, count 2 2006.231.07:40:10.67#ibcon#read 4, iclass 30, count 2 2006.231.07:40:10.67#ibcon#about to read 5, iclass 30, count 2 2006.231.07:40:10.67#ibcon#read 5, iclass 30, count 2 2006.231.07:40:10.67#ibcon#about to read 6, iclass 30, count 2 2006.231.07:40:10.67#ibcon#read 6, iclass 30, count 2 2006.231.07:40:10.67#ibcon#end of sib2, iclass 30, count 2 2006.231.07:40:10.67#ibcon#*mode == 0, iclass 30, count 2 2006.231.07:40:10.67#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.07:40:10.67#ibcon#[27=AT01-04\r\n] 2006.231.07:40:10.67#ibcon#*before write, iclass 30, count 2 2006.231.07:40:10.67#ibcon#enter sib2, iclass 30, count 2 2006.231.07:40:10.67#ibcon#flushed, iclass 30, count 2 2006.231.07:40:10.67#ibcon#about to write, iclass 30, count 2 2006.231.07:40:10.67#ibcon#wrote, iclass 30, count 2 2006.231.07:40:10.67#ibcon#about to read 3, iclass 30, count 2 2006.231.07:40:10.70#ibcon#read 3, iclass 30, count 2 2006.231.07:40:10.70#ibcon#about to read 4, iclass 30, count 2 2006.231.07:40:10.70#ibcon#read 4, iclass 30, count 2 2006.231.07:40:10.70#ibcon#about to read 5, iclass 30, count 2 2006.231.07:40:10.70#ibcon#read 5, iclass 30, count 2 2006.231.07:40:10.70#ibcon#about to read 6, iclass 30, count 2 2006.231.07:40:10.70#ibcon#read 6, iclass 30, count 2 2006.231.07:40:10.70#ibcon#end of sib2, iclass 30, count 2 2006.231.07:40:10.70#ibcon#*after write, iclass 30, count 2 2006.231.07:40:10.70#ibcon#*before return 0, iclass 30, count 2 2006.231.07:40:10.70#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:40:10.70#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:40:10.70#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.07:40:10.70#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:10.70#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:40:10.82#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:40:10.82#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:40:10.82#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:40:10.82#ibcon#first serial, iclass 30, count 0 2006.231.07:40:10.82#ibcon#enter sib2, iclass 30, count 0 2006.231.07:40:10.82#ibcon#flushed, iclass 30, count 0 2006.231.07:40:10.82#ibcon#about to write, iclass 30, count 0 2006.231.07:40:10.82#ibcon#wrote, iclass 30, count 0 2006.231.07:40:10.82#ibcon#about to read 3, iclass 30, count 0 2006.231.07:40:10.84#ibcon#read 3, iclass 30, count 0 2006.231.07:40:10.84#ibcon#about to read 4, iclass 30, count 0 2006.231.07:40:10.84#ibcon#read 4, iclass 30, count 0 2006.231.07:40:10.84#ibcon#about to read 5, iclass 30, count 0 2006.231.07:40:10.84#ibcon#read 5, iclass 30, count 0 2006.231.07:40:10.84#ibcon#about to read 6, iclass 30, count 0 2006.231.07:40:10.84#ibcon#read 6, iclass 30, count 0 2006.231.07:40:10.84#ibcon#end of sib2, iclass 30, count 0 2006.231.07:40:10.84#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:40:10.84#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:40:10.84#ibcon#[27=USB\r\n] 2006.231.07:40:10.84#ibcon#*before write, iclass 30, count 0 2006.231.07:40:10.84#ibcon#enter sib2, iclass 30, count 0 2006.231.07:40:10.84#ibcon#flushed, iclass 30, count 0 2006.231.07:40:10.84#ibcon#about to write, iclass 30, count 0 2006.231.07:40:10.84#ibcon#wrote, iclass 30, count 0 2006.231.07:40:10.84#ibcon#about to read 3, iclass 30, count 0 2006.231.07:40:10.87#ibcon#read 3, iclass 30, count 0 2006.231.07:40:10.87#ibcon#about to read 4, iclass 30, count 0 2006.231.07:40:10.87#ibcon#read 4, iclass 30, count 0 2006.231.07:40:10.87#ibcon#about to read 5, iclass 30, count 0 2006.231.07:40:10.87#ibcon#read 5, iclass 30, count 0 2006.231.07:40:10.87#ibcon#about to read 6, iclass 30, count 0 2006.231.07:40:10.87#ibcon#read 6, iclass 30, count 0 2006.231.07:40:10.87#ibcon#end of sib2, iclass 30, count 0 2006.231.07:40:10.87#ibcon#*after write, iclass 30, count 0 2006.231.07:40:10.87#ibcon#*before return 0, iclass 30, count 0 2006.231.07:40:10.87#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:40:10.87#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:40:10.87#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:40:10.87#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:40:10.87$vc4f8/vblo=2,640.99 2006.231.07:40:10.87#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.07:40:10.87#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.07:40:10.87#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:10.87#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:40:10.87#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:40:10.87#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:40:10.87#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:40:10.87#ibcon#first serial, iclass 32, count 0 2006.231.07:40:10.87#ibcon#enter sib2, iclass 32, count 0 2006.231.07:40:10.87#ibcon#flushed, iclass 32, count 0 2006.231.07:40:10.87#ibcon#about to write, iclass 32, count 0 2006.231.07:40:10.87#ibcon#wrote, iclass 32, count 0 2006.231.07:40:10.87#ibcon#about to read 3, iclass 32, count 0 2006.231.07:40:10.89#ibcon#read 3, iclass 32, count 0 2006.231.07:40:10.89#ibcon#about to read 4, iclass 32, count 0 2006.231.07:40:10.89#ibcon#read 4, iclass 32, count 0 2006.231.07:40:10.89#ibcon#about to read 5, iclass 32, count 0 2006.231.07:40:10.89#ibcon#read 5, iclass 32, count 0 2006.231.07:40:10.89#ibcon#about to read 6, iclass 32, count 0 2006.231.07:40:10.89#ibcon#read 6, iclass 32, count 0 2006.231.07:40:10.89#ibcon#end of sib2, iclass 32, count 0 2006.231.07:40:10.89#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:40:10.89#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:40:10.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:40:10.89#ibcon#*before write, iclass 32, count 0 2006.231.07:40:10.89#ibcon#enter sib2, iclass 32, count 0 2006.231.07:40:10.89#ibcon#flushed, iclass 32, count 0 2006.231.07:40:10.89#ibcon#about to write, iclass 32, count 0 2006.231.07:40:10.89#ibcon#wrote, iclass 32, count 0 2006.231.07:40:10.89#ibcon#about to read 3, iclass 32, count 0 2006.231.07:40:10.93#ibcon#read 3, iclass 32, count 0 2006.231.07:40:10.93#ibcon#about to read 4, iclass 32, count 0 2006.231.07:40:10.93#ibcon#read 4, iclass 32, count 0 2006.231.07:40:10.93#ibcon#about to read 5, iclass 32, count 0 2006.231.07:40:10.93#ibcon#read 5, iclass 32, count 0 2006.231.07:40:10.93#ibcon#about to read 6, iclass 32, count 0 2006.231.07:40:10.93#ibcon#read 6, iclass 32, count 0 2006.231.07:40:10.93#ibcon#end of sib2, iclass 32, count 0 2006.231.07:40:10.93#ibcon#*after write, iclass 32, count 0 2006.231.07:40:10.93#ibcon#*before return 0, iclass 32, count 0 2006.231.07:40:10.93#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:40:10.93#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:40:10.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:40:10.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:40:10.93$vc4f8/vb=2,4 2006.231.07:40:10.93#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.07:40:10.93#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.07:40:10.93#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:10.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:40:10.99#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:40:10.99#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:40:10.99#ibcon#enter wrdev, iclass 34, count 2 2006.231.07:40:10.99#ibcon#first serial, iclass 34, count 2 2006.231.07:40:10.99#ibcon#enter sib2, iclass 34, count 2 2006.231.07:40:10.99#ibcon#flushed, iclass 34, count 2 2006.231.07:40:10.99#ibcon#about to write, iclass 34, count 2 2006.231.07:40:10.99#ibcon#wrote, iclass 34, count 2 2006.231.07:40:10.99#ibcon#about to read 3, iclass 34, count 2 2006.231.07:40:11.01#ibcon#read 3, iclass 34, count 2 2006.231.07:40:11.01#ibcon#about to read 4, iclass 34, count 2 2006.231.07:40:11.01#ibcon#read 4, iclass 34, count 2 2006.231.07:40:11.01#ibcon#about to read 5, iclass 34, count 2 2006.231.07:40:11.01#ibcon#read 5, iclass 34, count 2 2006.231.07:40:11.01#ibcon#about to read 6, iclass 34, count 2 2006.231.07:40:11.01#ibcon#read 6, iclass 34, count 2 2006.231.07:40:11.01#ibcon#end of sib2, iclass 34, count 2 2006.231.07:40:11.01#ibcon#*mode == 0, iclass 34, count 2 2006.231.07:40:11.01#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.07:40:11.01#ibcon#[27=AT02-04\r\n] 2006.231.07:40:11.01#ibcon#*before write, iclass 34, count 2 2006.231.07:40:11.01#ibcon#enter sib2, iclass 34, count 2 2006.231.07:40:11.01#ibcon#flushed, iclass 34, count 2 2006.231.07:40:11.01#ibcon#about to write, iclass 34, count 2 2006.231.07:40:11.01#ibcon#wrote, iclass 34, count 2 2006.231.07:40:11.01#ibcon#about to read 3, iclass 34, count 2 2006.231.07:40:11.04#ibcon#read 3, iclass 34, count 2 2006.231.07:40:11.04#ibcon#about to read 4, iclass 34, count 2 2006.231.07:40:11.04#ibcon#read 4, iclass 34, count 2 2006.231.07:40:11.04#ibcon#about to read 5, iclass 34, count 2 2006.231.07:40:11.04#ibcon#read 5, iclass 34, count 2 2006.231.07:40:11.04#ibcon#about to read 6, iclass 34, count 2 2006.231.07:40:11.04#ibcon#read 6, iclass 34, count 2 2006.231.07:40:11.04#ibcon#end of sib2, iclass 34, count 2 2006.231.07:40:11.04#ibcon#*after write, iclass 34, count 2 2006.231.07:40:11.04#ibcon#*before return 0, iclass 34, count 2 2006.231.07:40:11.04#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:40:11.04#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:40:11.04#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.07:40:11.04#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:11.04#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:40:11.16#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:40:11.16#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:40:11.16#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:40:11.16#ibcon#first serial, iclass 34, count 0 2006.231.07:40:11.16#ibcon#enter sib2, iclass 34, count 0 2006.231.07:40:11.16#ibcon#flushed, iclass 34, count 0 2006.231.07:40:11.16#ibcon#about to write, iclass 34, count 0 2006.231.07:40:11.16#ibcon#wrote, iclass 34, count 0 2006.231.07:40:11.16#ibcon#about to read 3, iclass 34, count 0 2006.231.07:40:11.18#ibcon#read 3, iclass 34, count 0 2006.231.07:40:11.18#ibcon#about to read 4, iclass 34, count 0 2006.231.07:40:11.18#ibcon#read 4, iclass 34, count 0 2006.231.07:40:11.18#ibcon#about to read 5, iclass 34, count 0 2006.231.07:40:11.18#ibcon#read 5, iclass 34, count 0 2006.231.07:40:11.18#ibcon#about to read 6, iclass 34, count 0 2006.231.07:40:11.18#ibcon#read 6, iclass 34, count 0 2006.231.07:40:11.18#ibcon#end of sib2, iclass 34, count 0 2006.231.07:40:11.18#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:40:11.18#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:40:11.18#ibcon#[27=USB\r\n] 2006.231.07:40:11.18#ibcon#*before write, iclass 34, count 0 2006.231.07:40:11.18#ibcon#enter sib2, iclass 34, count 0 2006.231.07:40:11.18#ibcon#flushed, iclass 34, count 0 2006.231.07:40:11.18#ibcon#about to write, iclass 34, count 0 2006.231.07:40:11.18#ibcon#wrote, iclass 34, count 0 2006.231.07:40:11.18#ibcon#about to read 3, iclass 34, count 0 2006.231.07:40:11.21#ibcon#read 3, iclass 34, count 0 2006.231.07:40:11.21#ibcon#about to read 4, iclass 34, count 0 2006.231.07:40:11.21#ibcon#read 4, iclass 34, count 0 2006.231.07:40:11.21#ibcon#about to read 5, iclass 34, count 0 2006.231.07:40:11.21#ibcon#read 5, iclass 34, count 0 2006.231.07:40:11.21#ibcon#about to read 6, iclass 34, count 0 2006.231.07:40:11.21#ibcon#read 6, iclass 34, count 0 2006.231.07:40:11.21#ibcon#end of sib2, iclass 34, count 0 2006.231.07:40:11.21#ibcon#*after write, iclass 34, count 0 2006.231.07:40:11.21#ibcon#*before return 0, iclass 34, count 0 2006.231.07:40:11.21#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:40:11.21#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:40:11.21#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:40:11.21#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:40:11.21$vc4f8/vblo=3,656.99 2006.231.07:40:11.21#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.07:40:11.21#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.07:40:11.21#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:11.21#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:40:11.21#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:40:11.21#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:40:11.21#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:40:11.21#ibcon#first serial, iclass 36, count 0 2006.231.07:40:11.21#ibcon#enter sib2, iclass 36, count 0 2006.231.07:40:11.21#ibcon#flushed, iclass 36, count 0 2006.231.07:40:11.21#ibcon#about to write, iclass 36, count 0 2006.231.07:40:11.21#ibcon#wrote, iclass 36, count 0 2006.231.07:40:11.21#ibcon#about to read 3, iclass 36, count 0 2006.231.07:40:11.23#ibcon#read 3, iclass 36, count 0 2006.231.07:40:11.23#ibcon#about to read 4, iclass 36, count 0 2006.231.07:40:11.23#ibcon#read 4, iclass 36, count 0 2006.231.07:40:11.23#ibcon#about to read 5, iclass 36, count 0 2006.231.07:40:11.23#ibcon#read 5, iclass 36, count 0 2006.231.07:40:11.23#ibcon#about to read 6, iclass 36, count 0 2006.231.07:40:11.23#ibcon#read 6, iclass 36, count 0 2006.231.07:40:11.23#ibcon#end of sib2, iclass 36, count 0 2006.231.07:40:11.23#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:40:11.23#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:40:11.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:40:11.23#ibcon#*before write, iclass 36, count 0 2006.231.07:40:11.23#ibcon#enter sib2, iclass 36, count 0 2006.231.07:40:11.23#ibcon#flushed, iclass 36, count 0 2006.231.07:40:11.23#ibcon#about to write, iclass 36, count 0 2006.231.07:40:11.23#ibcon#wrote, iclass 36, count 0 2006.231.07:40:11.23#ibcon#about to read 3, iclass 36, count 0 2006.231.07:40:11.27#ibcon#read 3, iclass 36, count 0 2006.231.07:40:11.27#ibcon#about to read 4, iclass 36, count 0 2006.231.07:40:11.27#ibcon#read 4, iclass 36, count 0 2006.231.07:40:11.27#ibcon#about to read 5, iclass 36, count 0 2006.231.07:40:11.27#ibcon#read 5, iclass 36, count 0 2006.231.07:40:11.27#ibcon#about to read 6, iclass 36, count 0 2006.231.07:40:11.27#ibcon#read 6, iclass 36, count 0 2006.231.07:40:11.27#ibcon#end of sib2, iclass 36, count 0 2006.231.07:40:11.27#ibcon#*after write, iclass 36, count 0 2006.231.07:40:11.27#ibcon#*before return 0, iclass 36, count 0 2006.231.07:40:11.27#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:40:11.27#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:40:11.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:40:11.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:40:11.27$vc4f8/vb=3,4 2006.231.07:40:11.27#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.07:40:11.27#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.07:40:11.27#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:11.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:40:11.33#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:40:11.33#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:40:11.33#ibcon#enter wrdev, iclass 38, count 2 2006.231.07:40:11.33#ibcon#first serial, iclass 38, count 2 2006.231.07:40:11.33#ibcon#enter sib2, iclass 38, count 2 2006.231.07:40:11.33#ibcon#flushed, iclass 38, count 2 2006.231.07:40:11.33#ibcon#about to write, iclass 38, count 2 2006.231.07:40:11.33#ibcon#wrote, iclass 38, count 2 2006.231.07:40:11.33#ibcon#about to read 3, iclass 38, count 2 2006.231.07:40:11.35#ibcon#read 3, iclass 38, count 2 2006.231.07:40:11.35#ibcon#about to read 4, iclass 38, count 2 2006.231.07:40:11.35#ibcon#read 4, iclass 38, count 2 2006.231.07:40:11.35#ibcon#about to read 5, iclass 38, count 2 2006.231.07:40:11.35#ibcon#read 5, iclass 38, count 2 2006.231.07:40:11.35#ibcon#about to read 6, iclass 38, count 2 2006.231.07:40:11.35#ibcon#read 6, iclass 38, count 2 2006.231.07:40:11.35#ibcon#end of sib2, iclass 38, count 2 2006.231.07:40:11.35#ibcon#*mode == 0, iclass 38, count 2 2006.231.07:40:11.35#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.07:40:11.35#ibcon#[27=AT03-04\r\n] 2006.231.07:40:11.35#ibcon#*before write, iclass 38, count 2 2006.231.07:40:11.35#ibcon#enter sib2, iclass 38, count 2 2006.231.07:40:11.35#ibcon#flushed, iclass 38, count 2 2006.231.07:40:11.35#ibcon#about to write, iclass 38, count 2 2006.231.07:40:11.35#ibcon#wrote, iclass 38, count 2 2006.231.07:40:11.35#ibcon#about to read 3, iclass 38, count 2 2006.231.07:40:11.38#ibcon#read 3, iclass 38, count 2 2006.231.07:40:11.38#ibcon#about to read 4, iclass 38, count 2 2006.231.07:40:11.38#ibcon#read 4, iclass 38, count 2 2006.231.07:40:11.38#ibcon#about to read 5, iclass 38, count 2 2006.231.07:40:11.38#ibcon#read 5, iclass 38, count 2 2006.231.07:40:11.38#ibcon#about to read 6, iclass 38, count 2 2006.231.07:40:11.38#ibcon#read 6, iclass 38, count 2 2006.231.07:40:11.38#ibcon#end of sib2, iclass 38, count 2 2006.231.07:40:11.38#ibcon#*after write, iclass 38, count 2 2006.231.07:40:11.38#ibcon#*before return 0, iclass 38, count 2 2006.231.07:40:11.38#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:40:11.38#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:40:11.38#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.07:40:11.38#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:11.38#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:40:11.50#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:40:11.50#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:40:11.50#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:40:11.50#ibcon#first serial, iclass 38, count 0 2006.231.07:40:11.50#ibcon#enter sib2, iclass 38, count 0 2006.231.07:40:11.50#ibcon#flushed, iclass 38, count 0 2006.231.07:40:11.50#ibcon#about to write, iclass 38, count 0 2006.231.07:40:11.50#ibcon#wrote, iclass 38, count 0 2006.231.07:40:11.50#ibcon#about to read 3, iclass 38, count 0 2006.231.07:40:11.52#ibcon#read 3, iclass 38, count 0 2006.231.07:40:11.52#ibcon#about to read 4, iclass 38, count 0 2006.231.07:40:11.52#ibcon#read 4, iclass 38, count 0 2006.231.07:40:11.52#ibcon#about to read 5, iclass 38, count 0 2006.231.07:40:11.52#ibcon#read 5, iclass 38, count 0 2006.231.07:40:11.52#ibcon#about to read 6, iclass 38, count 0 2006.231.07:40:11.52#ibcon#read 6, iclass 38, count 0 2006.231.07:40:11.52#ibcon#end of sib2, iclass 38, count 0 2006.231.07:40:11.52#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:40:11.52#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:40:11.52#ibcon#[27=USB\r\n] 2006.231.07:40:11.52#ibcon#*before write, iclass 38, count 0 2006.231.07:40:11.52#ibcon#enter sib2, iclass 38, count 0 2006.231.07:40:11.52#ibcon#flushed, iclass 38, count 0 2006.231.07:40:11.52#ibcon#about to write, iclass 38, count 0 2006.231.07:40:11.52#ibcon#wrote, iclass 38, count 0 2006.231.07:40:11.52#ibcon#about to read 3, iclass 38, count 0 2006.231.07:40:11.55#ibcon#read 3, iclass 38, count 0 2006.231.07:40:11.55#ibcon#about to read 4, iclass 38, count 0 2006.231.07:40:11.55#ibcon#read 4, iclass 38, count 0 2006.231.07:40:11.55#ibcon#about to read 5, iclass 38, count 0 2006.231.07:40:11.55#ibcon#read 5, iclass 38, count 0 2006.231.07:40:11.55#ibcon#about to read 6, iclass 38, count 0 2006.231.07:40:11.55#ibcon#read 6, iclass 38, count 0 2006.231.07:40:11.55#ibcon#end of sib2, iclass 38, count 0 2006.231.07:40:11.55#ibcon#*after write, iclass 38, count 0 2006.231.07:40:11.55#ibcon#*before return 0, iclass 38, count 0 2006.231.07:40:11.55#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:40:11.55#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:40:11.55#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:40:11.55#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:40:11.55$vc4f8/vblo=4,712.99 2006.231.07:40:11.55#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.07:40:11.55#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.07:40:11.55#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:11.55#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:40:11.55#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:40:11.55#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:40:11.55#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:40:11.55#ibcon#first serial, iclass 40, count 0 2006.231.07:40:11.55#ibcon#enter sib2, iclass 40, count 0 2006.231.07:40:11.55#ibcon#flushed, iclass 40, count 0 2006.231.07:40:11.55#ibcon#about to write, iclass 40, count 0 2006.231.07:40:11.55#ibcon#wrote, iclass 40, count 0 2006.231.07:40:11.55#ibcon#about to read 3, iclass 40, count 0 2006.231.07:40:11.57#ibcon#read 3, iclass 40, count 0 2006.231.07:40:11.57#ibcon#about to read 4, iclass 40, count 0 2006.231.07:40:11.57#ibcon#read 4, iclass 40, count 0 2006.231.07:40:11.57#ibcon#about to read 5, iclass 40, count 0 2006.231.07:40:11.57#ibcon#read 5, iclass 40, count 0 2006.231.07:40:11.57#ibcon#about to read 6, iclass 40, count 0 2006.231.07:40:11.57#ibcon#read 6, iclass 40, count 0 2006.231.07:40:11.57#ibcon#end of sib2, iclass 40, count 0 2006.231.07:40:11.57#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:40:11.57#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:40:11.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:40:11.57#ibcon#*before write, iclass 40, count 0 2006.231.07:40:11.57#ibcon#enter sib2, iclass 40, count 0 2006.231.07:40:11.57#ibcon#flushed, iclass 40, count 0 2006.231.07:40:11.57#ibcon#about to write, iclass 40, count 0 2006.231.07:40:11.57#ibcon#wrote, iclass 40, count 0 2006.231.07:40:11.57#ibcon#about to read 3, iclass 40, count 0 2006.231.07:40:11.61#ibcon#read 3, iclass 40, count 0 2006.231.07:40:11.61#ibcon#about to read 4, iclass 40, count 0 2006.231.07:40:11.61#ibcon#read 4, iclass 40, count 0 2006.231.07:40:11.61#ibcon#about to read 5, iclass 40, count 0 2006.231.07:40:11.61#ibcon#read 5, iclass 40, count 0 2006.231.07:40:11.61#ibcon#about to read 6, iclass 40, count 0 2006.231.07:40:11.61#ibcon#read 6, iclass 40, count 0 2006.231.07:40:11.61#ibcon#end of sib2, iclass 40, count 0 2006.231.07:40:11.61#ibcon#*after write, iclass 40, count 0 2006.231.07:40:11.61#ibcon#*before return 0, iclass 40, count 0 2006.231.07:40:11.61#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:40:11.61#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:40:11.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:40:11.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:40:11.61$vc4f8/vb=4,4 2006.231.07:40:11.61#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.231.07:40:11.61#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.231.07:40:11.61#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:11.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:40:11.67#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:40:11.67#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:40:11.67#ibcon#enter wrdev, iclass 4, count 2 2006.231.07:40:11.67#ibcon#first serial, iclass 4, count 2 2006.231.07:40:11.67#ibcon#enter sib2, iclass 4, count 2 2006.231.07:40:11.67#ibcon#flushed, iclass 4, count 2 2006.231.07:40:11.67#ibcon#about to write, iclass 4, count 2 2006.231.07:40:11.67#ibcon#wrote, iclass 4, count 2 2006.231.07:40:11.67#ibcon#about to read 3, iclass 4, count 2 2006.231.07:40:11.69#ibcon#read 3, iclass 4, count 2 2006.231.07:40:11.69#ibcon#about to read 4, iclass 4, count 2 2006.231.07:40:11.69#ibcon#read 4, iclass 4, count 2 2006.231.07:40:11.69#ibcon#about to read 5, iclass 4, count 2 2006.231.07:40:11.69#ibcon#read 5, iclass 4, count 2 2006.231.07:40:11.69#ibcon#about to read 6, iclass 4, count 2 2006.231.07:40:11.69#ibcon#read 6, iclass 4, count 2 2006.231.07:40:11.69#ibcon#end of sib2, iclass 4, count 2 2006.231.07:40:11.69#ibcon#*mode == 0, iclass 4, count 2 2006.231.07:40:11.69#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.231.07:40:11.69#ibcon#[27=AT04-04\r\n] 2006.231.07:40:11.69#ibcon#*before write, iclass 4, count 2 2006.231.07:40:11.69#ibcon#enter sib2, iclass 4, count 2 2006.231.07:40:11.69#ibcon#flushed, iclass 4, count 2 2006.231.07:40:11.69#ibcon#about to write, iclass 4, count 2 2006.231.07:40:11.69#ibcon#wrote, iclass 4, count 2 2006.231.07:40:11.69#ibcon#about to read 3, iclass 4, count 2 2006.231.07:40:11.72#ibcon#read 3, iclass 4, count 2 2006.231.07:40:11.72#ibcon#about to read 4, iclass 4, count 2 2006.231.07:40:11.72#ibcon#read 4, iclass 4, count 2 2006.231.07:40:11.72#ibcon#about to read 5, iclass 4, count 2 2006.231.07:40:11.72#ibcon#read 5, iclass 4, count 2 2006.231.07:40:11.72#ibcon#about to read 6, iclass 4, count 2 2006.231.07:40:11.72#ibcon#read 6, iclass 4, count 2 2006.231.07:40:11.72#ibcon#end of sib2, iclass 4, count 2 2006.231.07:40:11.72#ibcon#*after write, iclass 4, count 2 2006.231.07:40:11.72#ibcon#*before return 0, iclass 4, count 2 2006.231.07:40:11.72#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:40:11.72#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:40:11.72#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.231.07:40:11.72#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:11.72#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:40:11.84#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:40:11.84#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:40:11.84#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:40:11.84#ibcon#first serial, iclass 4, count 0 2006.231.07:40:11.84#ibcon#enter sib2, iclass 4, count 0 2006.231.07:40:11.84#ibcon#flushed, iclass 4, count 0 2006.231.07:40:11.84#ibcon#about to write, iclass 4, count 0 2006.231.07:40:11.84#ibcon#wrote, iclass 4, count 0 2006.231.07:40:11.84#ibcon#about to read 3, iclass 4, count 0 2006.231.07:40:11.86#ibcon#read 3, iclass 4, count 0 2006.231.07:40:11.86#ibcon#about to read 4, iclass 4, count 0 2006.231.07:40:11.86#ibcon#read 4, iclass 4, count 0 2006.231.07:40:11.86#ibcon#about to read 5, iclass 4, count 0 2006.231.07:40:11.86#ibcon#read 5, iclass 4, count 0 2006.231.07:40:11.86#ibcon#about to read 6, iclass 4, count 0 2006.231.07:40:11.86#ibcon#read 6, iclass 4, count 0 2006.231.07:40:11.86#ibcon#end of sib2, iclass 4, count 0 2006.231.07:40:11.86#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:40:11.86#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:40:11.86#ibcon#[27=USB\r\n] 2006.231.07:40:11.86#ibcon#*before write, iclass 4, count 0 2006.231.07:40:11.86#ibcon#enter sib2, iclass 4, count 0 2006.231.07:40:11.86#ibcon#flushed, iclass 4, count 0 2006.231.07:40:11.86#ibcon#about to write, iclass 4, count 0 2006.231.07:40:11.86#ibcon#wrote, iclass 4, count 0 2006.231.07:40:11.86#ibcon#about to read 3, iclass 4, count 0 2006.231.07:40:11.89#ibcon#read 3, iclass 4, count 0 2006.231.07:40:11.89#ibcon#about to read 4, iclass 4, count 0 2006.231.07:40:11.89#ibcon#read 4, iclass 4, count 0 2006.231.07:40:11.89#ibcon#about to read 5, iclass 4, count 0 2006.231.07:40:11.89#ibcon#read 5, iclass 4, count 0 2006.231.07:40:11.89#ibcon#about to read 6, iclass 4, count 0 2006.231.07:40:11.89#ibcon#read 6, iclass 4, count 0 2006.231.07:40:11.89#ibcon#end of sib2, iclass 4, count 0 2006.231.07:40:11.89#ibcon#*after write, iclass 4, count 0 2006.231.07:40:11.89#ibcon#*before return 0, iclass 4, count 0 2006.231.07:40:11.89#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:40:11.89#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:40:11.89#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:40:11.89#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:40:11.89$vc4f8/vblo=5,744.99 2006.231.07:40:11.89#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.231.07:40:11.89#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.231.07:40:11.89#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:11.89#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:40:11.89#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:40:11.89#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:40:11.89#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:40:11.89#ibcon#first serial, iclass 6, count 0 2006.231.07:40:11.89#ibcon#enter sib2, iclass 6, count 0 2006.231.07:40:11.89#ibcon#flushed, iclass 6, count 0 2006.231.07:40:11.89#ibcon#about to write, iclass 6, count 0 2006.231.07:40:11.89#ibcon#wrote, iclass 6, count 0 2006.231.07:40:11.89#ibcon#about to read 3, iclass 6, count 0 2006.231.07:40:11.91#ibcon#read 3, iclass 6, count 0 2006.231.07:40:11.91#ibcon#about to read 4, iclass 6, count 0 2006.231.07:40:11.91#ibcon#read 4, iclass 6, count 0 2006.231.07:40:11.91#ibcon#about to read 5, iclass 6, count 0 2006.231.07:40:11.91#ibcon#read 5, iclass 6, count 0 2006.231.07:40:11.91#ibcon#about to read 6, iclass 6, count 0 2006.231.07:40:11.91#ibcon#read 6, iclass 6, count 0 2006.231.07:40:11.91#ibcon#end of sib2, iclass 6, count 0 2006.231.07:40:11.91#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:40:11.91#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:40:11.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:40:11.91#ibcon#*before write, iclass 6, count 0 2006.231.07:40:11.91#ibcon#enter sib2, iclass 6, count 0 2006.231.07:40:11.91#ibcon#flushed, iclass 6, count 0 2006.231.07:40:11.91#ibcon#about to write, iclass 6, count 0 2006.231.07:40:11.91#ibcon#wrote, iclass 6, count 0 2006.231.07:40:11.91#ibcon#about to read 3, iclass 6, count 0 2006.231.07:40:11.95#ibcon#read 3, iclass 6, count 0 2006.231.07:40:11.95#ibcon#about to read 4, iclass 6, count 0 2006.231.07:40:11.95#ibcon#read 4, iclass 6, count 0 2006.231.07:40:11.95#ibcon#about to read 5, iclass 6, count 0 2006.231.07:40:11.95#ibcon#read 5, iclass 6, count 0 2006.231.07:40:11.95#ibcon#about to read 6, iclass 6, count 0 2006.231.07:40:11.95#ibcon#read 6, iclass 6, count 0 2006.231.07:40:11.95#ibcon#end of sib2, iclass 6, count 0 2006.231.07:40:11.95#ibcon#*after write, iclass 6, count 0 2006.231.07:40:11.95#ibcon#*before return 0, iclass 6, count 0 2006.231.07:40:11.95#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:40:11.95#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:40:11.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:40:11.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:40:11.95$vc4f8/vb=5,3 2006.231.07:40:11.95#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.231.07:40:11.95#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.231.07:40:11.95#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:11.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:40:12.01#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:40:12.01#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:40:12.01#ibcon#enter wrdev, iclass 10, count 2 2006.231.07:40:12.01#ibcon#first serial, iclass 10, count 2 2006.231.07:40:12.01#ibcon#enter sib2, iclass 10, count 2 2006.231.07:40:12.01#ibcon#flushed, iclass 10, count 2 2006.231.07:40:12.01#ibcon#about to write, iclass 10, count 2 2006.231.07:40:12.01#ibcon#wrote, iclass 10, count 2 2006.231.07:40:12.01#ibcon#about to read 3, iclass 10, count 2 2006.231.07:40:12.04#ibcon#read 3, iclass 10, count 2 2006.231.07:40:12.04#ibcon#about to read 4, iclass 10, count 2 2006.231.07:40:12.04#ibcon#read 4, iclass 10, count 2 2006.231.07:40:12.04#ibcon#about to read 5, iclass 10, count 2 2006.231.07:40:12.04#ibcon#read 5, iclass 10, count 2 2006.231.07:40:12.04#ibcon#about to read 6, iclass 10, count 2 2006.231.07:40:12.04#ibcon#read 6, iclass 10, count 2 2006.231.07:40:12.04#ibcon#end of sib2, iclass 10, count 2 2006.231.07:40:12.04#ibcon#*mode == 0, iclass 10, count 2 2006.231.07:40:12.04#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.231.07:40:12.04#ibcon#[27=AT05-03\r\n] 2006.231.07:40:12.04#ibcon#*before write, iclass 10, count 2 2006.231.07:40:12.04#ibcon#enter sib2, iclass 10, count 2 2006.231.07:40:12.04#ibcon#flushed, iclass 10, count 2 2006.231.07:40:12.04#ibcon#about to write, iclass 10, count 2 2006.231.07:40:12.04#ibcon#wrote, iclass 10, count 2 2006.231.07:40:12.04#ibcon#about to read 3, iclass 10, count 2 2006.231.07:40:12.07#ibcon#read 3, iclass 10, count 2 2006.231.07:40:12.07#ibcon#about to read 4, iclass 10, count 2 2006.231.07:40:12.07#ibcon#read 4, iclass 10, count 2 2006.231.07:40:12.07#ibcon#about to read 5, iclass 10, count 2 2006.231.07:40:12.07#ibcon#read 5, iclass 10, count 2 2006.231.07:40:12.07#ibcon#about to read 6, iclass 10, count 2 2006.231.07:40:12.07#ibcon#read 6, iclass 10, count 2 2006.231.07:40:12.07#ibcon#end of sib2, iclass 10, count 2 2006.231.07:40:12.07#ibcon#*after write, iclass 10, count 2 2006.231.07:40:12.07#ibcon#*before return 0, iclass 10, count 2 2006.231.07:40:12.07#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:40:12.07#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:40:12.07#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.231.07:40:12.07#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:12.07#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:40:12.19#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:40:12.19#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:40:12.19#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:40:12.19#ibcon#first serial, iclass 10, count 0 2006.231.07:40:12.19#ibcon#enter sib2, iclass 10, count 0 2006.231.07:40:12.19#ibcon#flushed, iclass 10, count 0 2006.231.07:40:12.19#ibcon#about to write, iclass 10, count 0 2006.231.07:40:12.19#ibcon#wrote, iclass 10, count 0 2006.231.07:40:12.19#ibcon#about to read 3, iclass 10, count 0 2006.231.07:40:12.21#ibcon#read 3, iclass 10, count 0 2006.231.07:40:12.21#ibcon#about to read 4, iclass 10, count 0 2006.231.07:40:12.21#ibcon#read 4, iclass 10, count 0 2006.231.07:40:12.21#ibcon#about to read 5, iclass 10, count 0 2006.231.07:40:12.21#ibcon#read 5, iclass 10, count 0 2006.231.07:40:12.21#ibcon#about to read 6, iclass 10, count 0 2006.231.07:40:12.21#ibcon#read 6, iclass 10, count 0 2006.231.07:40:12.21#ibcon#end of sib2, iclass 10, count 0 2006.231.07:40:12.21#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:40:12.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:40:12.21#ibcon#[27=USB\r\n] 2006.231.07:40:12.21#ibcon#*before write, iclass 10, count 0 2006.231.07:40:12.21#ibcon#enter sib2, iclass 10, count 0 2006.231.07:40:12.21#ibcon#flushed, iclass 10, count 0 2006.231.07:40:12.21#ibcon#about to write, iclass 10, count 0 2006.231.07:40:12.21#ibcon#wrote, iclass 10, count 0 2006.231.07:40:12.21#ibcon#about to read 3, iclass 10, count 0 2006.231.07:40:12.25#ibcon#read 3, iclass 10, count 0 2006.231.07:40:12.25#ibcon#about to read 4, iclass 10, count 0 2006.231.07:40:12.25#ibcon#read 4, iclass 10, count 0 2006.231.07:40:12.25#ibcon#about to read 5, iclass 10, count 0 2006.231.07:40:12.25#ibcon#read 5, iclass 10, count 0 2006.231.07:40:12.25#ibcon#about to read 6, iclass 10, count 0 2006.231.07:40:12.25#ibcon#read 6, iclass 10, count 0 2006.231.07:40:12.25#ibcon#end of sib2, iclass 10, count 0 2006.231.07:40:12.25#ibcon#*after write, iclass 10, count 0 2006.231.07:40:12.25#ibcon#*before return 0, iclass 10, count 0 2006.231.07:40:12.25#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:40:12.25#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:40:12.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:40:12.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:40:12.25$vc4f8/vblo=6,752.99 2006.231.07:40:12.25#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.07:40:12.25#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.07:40:12.25#ibcon#ireg 17 cls_cnt 0 2006.231.07:40:12.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:40:12.25#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:40:12.25#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:40:12.25#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:40:12.25#ibcon#first serial, iclass 12, count 0 2006.231.07:40:12.25#ibcon#enter sib2, iclass 12, count 0 2006.231.07:40:12.25#ibcon#flushed, iclass 12, count 0 2006.231.07:40:12.25#ibcon#about to write, iclass 12, count 0 2006.231.07:40:12.25#ibcon#wrote, iclass 12, count 0 2006.231.07:40:12.25#ibcon#about to read 3, iclass 12, count 0 2006.231.07:40:12.26#ibcon#read 3, iclass 12, count 0 2006.231.07:40:12.26#ibcon#about to read 4, iclass 12, count 0 2006.231.07:40:12.26#ibcon#read 4, iclass 12, count 0 2006.231.07:40:12.26#ibcon#about to read 5, iclass 12, count 0 2006.231.07:40:12.26#ibcon#read 5, iclass 12, count 0 2006.231.07:40:12.26#ibcon#about to read 6, iclass 12, count 0 2006.231.07:40:12.26#ibcon#read 6, iclass 12, count 0 2006.231.07:40:12.26#ibcon#end of sib2, iclass 12, count 0 2006.231.07:40:12.26#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:40:12.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:40:12.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:40:12.26#ibcon#*before write, iclass 12, count 0 2006.231.07:40:12.26#ibcon#enter sib2, iclass 12, count 0 2006.231.07:40:12.26#ibcon#flushed, iclass 12, count 0 2006.231.07:40:12.26#ibcon#about to write, iclass 12, count 0 2006.231.07:40:12.26#ibcon#wrote, iclass 12, count 0 2006.231.07:40:12.26#ibcon#about to read 3, iclass 12, count 0 2006.231.07:40:12.30#ibcon#read 3, iclass 12, count 0 2006.231.07:40:12.30#ibcon#about to read 4, iclass 12, count 0 2006.231.07:40:12.30#ibcon#read 4, iclass 12, count 0 2006.231.07:40:12.30#ibcon#about to read 5, iclass 12, count 0 2006.231.07:40:12.30#ibcon#read 5, iclass 12, count 0 2006.231.07:40:12.30#ibcon#about to read 6, iclass 12, count 0 2006.231.07:40:12.30#ibcon#read 6, iclass 12, count 0 2006.231.07:40:12.30#ibcon#end of sib2, iclass 12, count 0 2006.231.07:40:12.30#ibcon#*after write, iclass 12, count 0 2006.231.07:40:12.30#ibcon#*before return 0, iclass 12, count 0 2006.231.07:40:12.30#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:40:12.30#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:40:12.30#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:40:12.30#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:40:12.30$vc4f8/vb=6,4 2006.231.07:40:12.30#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.07:40:12.30#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.07:40:12.30#ibcon#ireg 11 cls_cnt 2 2006.231.07:40:12.30#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:40:12.37#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:40:12.37#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:40:12.37#ibcon#enter wrdev, iclass 14, count 2 2006.231.07:40:12.37#ibcon#first serial, iclass 14, count 2 2006.231.07:40:12.37#ibcon#enter sib2, iclass 14, count 2 2006.231.07:40:12.37#ibcon#flushed, iclass 14, count 2 2006.231.07:40:12.37#ibcon#about to write, iclass 14, count 2 2006.231.07:40:12.37#ibcon#wrote, iclass 14, count 2 2006.231.07:40:12.37#ibcon#about to read 3, iclass 14, count 2 2006.231.07:40:12.39#ibcon#read 3, iclass 14, count 2 2006.231.07:40:12.39#ibcon#about to read 4, iclass 14, count 2 2006.231.07:40:12.39#ibcon#read 4, iclass 14, count 2 2006.231.07:40:12.39#ibcon#about to read 5, iclass 14, count 2 2006.231.07:40:12.39#ibcon#read 5, iclass 14, count 2 2006.231.07:40:12.39#ibcon#about to read 6, iclass 14, count 2 2006.231.07:40:12.39#ibcon#read 6, iclass 14, count 2 2006.231.07:40:12.39#ibcon#end of sib2, iclass 14, count 2 2006.231.07:40:12.39#ibcon#*mode == 0, iclass 14, count 2 2006.231.07:40:12.39#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.07:40:12.39#ibcon#[27=AT06-04\r\n] 2006.231.07:40:12.39#ibcon#*before write, iclass 14, count 2 2006.231.07:40:12.39#ibcon#enter sib2, iclass 14, count 2 2006.231.07:40:12.39#ibcon#flushed, iclass 14, count 2 2006.231.07:40:12.39#ibcon#about to write, iclass 14, count 2 2006.231.07:40:12.39#ibcon#wrote, iclass 14, count 2 2006.231.07:40:12.39#ibcon#about to read 3, iclass 14, count 2 2006.231.07:40:12.42#ibcon#read 3, iclass 14, count 2 2006.231.07:40:12.42#ibcon#about to read 4, iclass 14, count 2 2006.231.07:40:12.42#ibcon#read 4, iclass 14, count 2 2006.231.07:40:12.42#ibcon#about to read 5, iclass 14, count 2 2006.231.07:40:12.42#ibcon#read 5, iclass 14, count 2 2006.231.07:40:12.42#ibcon#about to read 6, iclass 14, count 2 2006.231.07:40:12.42#ibcon#read 6, iclass 14, count 2 2006.231.07:40:12.42#ibcon#end of sib2, iclass 14, count 2 2006.231.07:40:12.42#ibcon#*after write, iclass 14, count 2 2006.231.07:40:12.42#ibcon#*before return 0, iclass 14, count 2 2006.231.07:40:12.42#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:40:12.42#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:40:12.42#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.07:40:12.42#ibcon#ireg 7 cls_cnt 0 2006.231.07:40:12.42#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:40:12.54#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:40:12.54#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:40:12.54#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:40:12.54#ibcon#first serial, iclass 14, count 0 2006.231.07:40:12.54#ibcon#enter sib2, iclass 14, count 0 2006.231.07:40:12.54#ibcon#flushed, iclass 14, count 0 2006.231.07:40:12.54#ibcon#about to write, iclass 14, count 0 2006.231.07:40:12.54#ibcon#wrote, iclass 14, count 0 2006.231.07:40:12.54#ibcon#about to read 3, iclass 14, count 0 2006.231.07:40:12.56#ibcon#read 3, iclass 14, count 0 2006.231.07:40:12.56#ibcon#about to read 4, iclass 14, count 0 2006.231.07:40:12.56#ibcon#read 4, iclass 14, count 0 2006.231.07:40:12.56#ibcon#about to read 5, iclass 14, count 0 2006.231.07:40:12.56#ibcon#read 5, iclass 14, count 0 2006.231.07:40:12.56#ibcon#about to read 6, iclass 14, count 0 2006.231.07:40:12.56#ibcon#read 6, iclass 14, count 0 2006.231.07:40:12.56#ibcon#end of sib2, iclass 14, count 0 2006.231.07:40:12.56#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:40:12.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:40:12.56#ibcon#[27=USB\r\n] 2006.231.07:40:12.56#ibcon#*before write, iclass 14, count 0 2006.231.07:40:12.56#ibcon#enter sib2, iclass 14, count 0 2006.231.07:40:12.56#ibcon#flushed, iclass 14, count 0 2006.231.07:40:12.56#ibcon#about to write, iclass 14, count 0 2006.231.07:40:12.56#ibcon#wrote, iclass 14, count 0 2006.231.07:40:12.56#ibcon#about to read 3, iclass 14, count 0 2006.231.07:40:12.59#ibcon#read 3, iclass 14, count 0 2006.231.07:40:12.59#ibcon#about to read 4, iclass 14, count 0 2006.231.07:40:12.59#ibcon#read 4, iclass 14, count 0 2006.231.07:40:12.59#ibcon#about to read 5, iclass 14, count 0 2006.231.07:40:12.59#ibcon#read 5, iclass 14, count 0 2006.231.07:40:12.59#ibcon#about to read 6, iclass 14, count 0 2006.231.07:40:12.59#ibcon#read 6, iclass 14, count 0 2006.231.07:40:12.59#ibcon#end of sib2, iclass 14, count 0 2006.231.07:40:12.59#ibcon#*after write, iclass 14, count 0 2006.231.07:40:12.59#ibcon#*before return 0, iclass 14, count 0 2006.231.07:40:12.59#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:40:12.59#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:40:12.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:40:12.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:40:12.59$vc4f8/vabw=wide 2006.231.07:40:12.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.07:40:12.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.07:40:12.59#ibcon#ireg 8 cls_cnt 0 2006.231.07:40:12.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:40:12.59#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:40:12.59#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:40:12.59#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:40:12.59#ibcon#first serial, iclass 16, count 0 2006.231.07:40:12.59#ibcon#enter sib2, iclass 16, count 0 2006.231.07:40:12.59#ibcon#flushed, iclass 16, count 0 2006.231.07:40:12.59#ibcon#about to write, iclass 16, count 0 2006.231.07:40:12.59#ibcon#wrote, iclass 16, count 0 2006.231.07:40:12.59#ibcon#about to read 3, iclass 16, count 0 2006.231.07:40:12.61#ibcon#read 3, iclass 16, count 0 2006.231.07:40:12.61#ibcon#about to read 4, iclass 16, count 0 2006.231.07:40:12.61#ibcon#read 4, iclass 16, count 0 2006.231.07:40:12.61#ibcon#about to read 5, iclass 16, count 0 2006.231.07:40:12.61#ibcon#read 5, iclass 16, count 0 2006.231.07:40:12.61#ibcon#about to read 6, iclass 16, count 0 2006.231.07:40:12.61#ibcon#read 6, iclass 16, count 0 2006.231.07:40:12.61#ibcon#end of sib2, iclass 16, count 0 2006.231.07:40:12.61#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:40:12.61#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:40:12.61#ibcon#[25=BW32\r\n] 2006.231.07:40:12.61#ibcon#*before write, iclass 16, count 0 2006.231.07:40:12.61#ibcon#enter sib2, iclass 16, count 0 2006.231.07:40:12.61#ibcon#flushed, iclass 16, count 0 2006.231.07:40:12.61#ibcon#about to write, iclass 16, count 0 2006.231.07:40:12.61#ibcon#wrote, iclass 16, count 0 2006.231.07:40:12.61#ibcon#about to read 3, iclass 16, count 0 2006.231.07:40:12.64#ibcon#read 3, iclass 16, count 0 2006.231.07:40:12.64#ibcon#about to read 4, iclass 16, count 0 2006.231.07:40:12.64#ibcon#read 4, iclass 16, count 0 2006.231.07:40:12.64#ibcon#about to read 5, iclass 16, count 0 2006.231.07:40:12.64#ibcon#read 5, iclass 16, count 0 2006.231.07:40:12.64#ibcon#about to read 6, iclass 16, count 0 2006.231.07:40:12.64#ibcon#read 6, iclass 16, count 0 2006.231.07:40:12.64#ibcon#end of sib2, iclass 16, count 0 2006.231.07:40:12.64#ibcon#*after write, iclass 16, count 0 2006.231.07:40:12.64#ibcon#*before return 0, iclass 16, count 0 2006.231.07:40:12.64#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:40:12.64#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:40:12.64#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:40:12.64#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:40:12.64$vc4f8/vbbw=wide 2006.231.07:40:12.64#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.07:40:12.64#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.07:40:12.64#ibcon#ireg 8 cls_cnt 0 2006.231.07:40:12.64#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:40:12.71#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:40:12.71#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:40:12.71#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:40:12.71#ibcon#first serial, iclass 18, count 0 2006.231.07:40:12.71#ibcon#enter sib2, iclass 18, count 0 2006.231.07:40:12.71#ibcon#flushed, iclass 18, count 0 2006.231.07:40:12.71#ibcon#about to write, iclass 18, count 0 2006.231.07:40:12.71#ibcon#wrote, iclass 18, count 0 2006.231.07:40:12.71#ibcon#about to read 3, iclass 18, count 0 2006.231.07:40:12.73#ibcon#read 3, iclass 18, count 0 2006.231.07:40:12.73#ibcon#about to read 4, iclass 18, count 0 2006.231.07:40:12.73#ibcon#read 4, iclass 18, count 0 2006.231.07:40:12.73#ibcon#about to read 5, iclass 18, count 0 2006.231.07:40:12.73#ibcon#read 5, iclass 18, count 0 2006.231.07:40:12.73#ibcon#about to read 6, iclass 18, count 0 2006.231.07:40:12.73#ibcon#read 6, iclass 18, count 0 2006.231.07:40:12.73#ibcon#end of sib2, iclass 18, count 0 2006.231.07:40:12.73#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:40:12.73#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:40:12.73#ibcon#[27=BW32\r\n] 2006.231.07:40:12.73#ibcon#*before write, iclass 18, count 0 2006.231.07:40:12.73#ibcon#enter sib2, iclass 18, count 0 2006.231.07:40:12.73#ibcon#flushed, iclass 18, count 0 2006.231.07:40:12.73#ibcon#about to write, iclass 18, count 0 2006.231.07:40:12.73#ibcon#wrote, iclass 18, count 0 2006.231.07:40:12.73#ibcon#about to read 3, iclass 18, count 0 2006.231.07:40:12.76#ibcon#read 3, iclass 18, count 0 2006.231.07:40:12.76#ibcon#about to read 4, iclass 18, count 0 2006.231.07:40:12.76#ibcon#read 4, iclass 18, count 0 2006.231.07:40:12.76#ibcon#about to read 5, iclass 18, count 0 2006.231.07:40:12.76#ibcon#read 5, iclass 18, count 0 2006.231.07:40:12.76#ibcon#about to read 6, iclass 18, count 0 2006.231.07:40:12.76#ibcon#read 6, iclass 18, count 0 2006.231.07:40:12.76#ibcon#end of sib2, iclass 18, count 0 2006.231.07:40:12.76#ibcon#*after write, iclass 18, count 0 2006.231.07:40:12.76#ibcon#*before return 0, iclass 18, count 0 2006.231.07:40:12.76#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:40:12.76#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:40:12.76#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:40:12.76#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:40:12.76$4f8m12a/ifd4f 2006.231.07:40:12.76$ifd4f/lo= 2006.231.07:40:12.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:40:12.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:40:12.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:40:12.76$ifd4f/patch= 2006.231.07:40:12.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:40:12.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:40:12.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:40:12.76$4f8m12a/"form=m,16.000,1:2 2006.231.07:40:12.76$4f8m12a/"tpicd 2006.231.07:40:12.76$4f8m12a/echo=off 2006.231.07:40:12.76$4f8m12a/xlog=off 2006.231.07:40:12.76:!2006.231.07:40:40 2006.231.07:40:28.14#trakl#Source acquired 2006.231.07:40:28.14#flagr#flagr/antenna,acquired 2006.231.07:40:40.00:preob 2006.231.07:40:41.14/onsource/TRACKING 2006.231.07:40:41.14:!2006.231.07:40:50 2006.231.07:40:50.00:data_valid=on 2006.231.07:40:50.00:midob 2006.231.07:40:50.14/onsource/TRACKING 2006.231.07:40:50.14/wx/30.67,1004.4,84 2006.231.07:40:50.35/cable/+6.3716E-03 2006.231.07:40:51.44/va/01,08,usb,yes,31,33 2006.231.07:40:51.44/va/02,07,usb,yes,32,33 2006.231.07:40:51.44/va/03,08,usb,yes,24,24 2006.231.07:40:51.44/va/04,07,usb,yes,33,36 2006.231.07:40:51.44/va/05,07,usb,yes,37,39 2006.231.07:40:51.44/va/06,06,usb,yes,36,36 2006.231.07:40:51.44/va/07,06,usb,yes,37,37 2006.231.07:40:51.44/va/08,06,usb,yes,39,39 2006.231.07:40:51.67/valo/01,532.99,yes,locked 2006.231.07:40:51.67/valo/02,572.99,yes,locked 2006.231.07:40:51.67/valo/03,672.99,yes,locked 2006.231.07:40:51.67/valo/04,832.99,yes,locked 2006.231.07:40:51.67/valo/05,652.99,yes,locked 2006.231.07:40:51.67/valo/06,772.99,yes,locked 2006.231.07:40:51.67/valo/07,832.99,yes,locked 2006.231.07:40:51.67/valo/08,852.99,yes,locked 2006.231.07:40:52.76/vb/01,04,usb,yes,32,30 2006.231.07:40:52.76/vb/02,04,usb,yes,34,35 2006.231.07:40:52.76/vb/03,04,usb,yes,30,34 2006.231.07:40:52.76/vb/04,04,usb,yes,31,31 2006.231.07:40:52.76/vb/05,03,usb,yes,36,41 2006.231.07:40:52.76/vb/06,04,usb,yes,30,33 2006.231.07:40:52.76/vb/07,04,usb,yes,32,32 2006.231.07:40:52.76/vb/08,04,usb,yes,30,33 2006.231.07:40:52.99/vblo/01,632.99,yes,locked 2006.231.07:40:52.99/vblo/02,640.99,yes,locked 2006.231.07:40:52.99/vblo/03,656.99,yes,locked 2006.231.07:40:52.99/vblo/04,712.99,yes,locked 2006.231.07:40:52.99/vblo/05,744.99,yes,locked 2006.231.07:40:52.99/vblo/06,752.99,yes,locked 2006.231.07:40:52.99/vblo/07,734.99,yes,locked 2006.231.07:40:52.99/vblo/08,744.99,yes,locked 2006.231.07:40:53.14/vabw/8 2006.231.07:40:53.29/vbbw/8 2006.231.07:40:53.38/xfe/off,on,12.5 2006.231.07:40:53.77/ifatt/23,28,28,28 2006.231.07:40:54.07/fmout-gps/S +4.40E-07 2006.231.07:40:54.11:!2006.231.07:41:50 2006.231.07:41:50.00:data_valid=off 2006.231.07:41:50.00:postob 2006.231.07:41:50.10/cable/+6.3707E-03 2006.231.07:41:50.10/wx/30.65,1004.4,84 2006.231.07:41:51.07/fmout-gps/S +4.41E-07 2006.231.07:41:51.07:scan_name=231-0742,k06231,60 2006.231.07:41:51.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.231.07:41:51.14#flagr#flagr/antenna,new-source 2006.231.07:41:52.14:checkk5 2006.231.07:41:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:41:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:41:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:41:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:41:54.01/chk_obsdata//k5ts1/T2310740??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:41:54.37/chk_obsdata//k5ts2/T2310740??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:41:54.74/chk_obsdata//k5ts3/T2310740??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:41:55.11/chk_obsdata//k5ts4/T2310740??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:41:55.80/k5log//k5ts1_log_newline 2006.231.07:41:56.48/k5log//k5ts2_log_newline 2006.231.07:41:57.17/k5log//k5ts3_log_newline 2006.231.07:41:57.85/k5log//k5ts4_log_newline 2006.231.07:41:57.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:41:57.88:4f8m12a=1 2006.231.07:41:57.88$4f8m12a/echo=on 2006.231.07:41:57.88$4f8m12a/pcalon 2006.231.07:41:57.88$pcalon/"no phase cal control is implemented here 2006.231.07:41:57.88$4f8m12a/"tpicd=stop 2006.231.07:41:57.88$4f8m12a/vc4f8 2006.231.07:41:57.88$vc4f8/valo=1,532.99 2006.231.07:41:57.88#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.231.07:41:57.88#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.231.07:41:57.88#ibcon#ireg 17 cls_cnt 0 2006.231.07:41:57.88#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:41:57.88#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:41:57.88#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:41:57.88#ibcon#enter wrdev, iclass 25, count 0 2006.231.07:41:57.88#ibcon#first serial, iclass 25, count 0 2006.231.07:41:57.88#ibcon#enter sib2, iclass 25, count 0 2006.231.07:41:57.88#ibcon#flushed, iclass 25, count 0 2006.231.07:41:57.88#ibcon#about to write, iclass 25, count 0 2006.231.07:41:57.88#ibcon#wrote, iclass 25, count 0 2006.231.07:41:57.88#ibcon#about to read 3, iclass 25, count 0 2006.231.07:41:57.92#ibcon#read 3, iclass 25, count 0 2006.231.07:41:57.92#ibcon#about to read 4, iclass 25, count 0 2006.231.07:41:57.92#ibcon#read 4, iclass 25, count 0 2006.231.07:41:57.92#ibcon#about to read 5, iclass 25, count 0 2006.231.07:41:57.92#ibcon#read 5, iclass 25, count 0 2006.231.07:41:57.92#ibcon#about to read 6, iclass 25, count 0 2006.231.07:41:57.92#ibcon#read 6, iclass 25, count 0 2006.231.07:41:57.92#ibcon#end of sib2, iclass 25, count 0 2006.231.07:41:57.92#ibcon#*mode == 0, iclass 25, count 0 2006.231.07:41:57.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.07:41:57.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:41:57.92#ibcon#*before write, iclass 25, count 0 2006.231.07:41:57.92#ibcon#enter sib2, iclass 25, count 0 2006.231.07:41:57.92#ibcon#flushed, iclass 25, count 0 2006.231.07:41:57.92#ibcon#about to write, iclass 25, count 0 2006.231.07:41:57.92#ibcon#wrote, iclass 25, count 0 2006.231.07:41:57.92#ibcon#about to read 3, iclass 25, count 0 2006.231.07:41:57.97#ibcon#read 3, iclass 25, count 0 2006.231.07:41:57.97#ibcon#about to read 4, iclass 25, count 0 2006.231.07:41:57.97#ibcon#read 4, iclass 25, count 0 2006.231.07:41:57.97#ibcon#about to read 5, iclass 25, count 0 2006.231.07:41:57.97#ibcon#read 5, iclass 25, count 0 2006.231.07:41:57.97#ibcon#about to read 6, iclass 25, count 0 2006.231.07:41:57.97#ibcon#read 6, iclass 25, count 0 2006.231.07:41:57.97#ibcon#end of sib2, iclass 25, count 0 2006.231.07:41:57.97#ibcon#*after write, iclass 25, count 0 2006.231.07:41:57.97#ibcon#*before return 0, iclass 25, count 0 2006.231.07:41:57.97#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:41:57.97#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:41:57.97#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.07:41:57.97#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.07:41:57.97$vc4f8/va=1,8 2006.231.07:41:57.97#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.231.07:41:57.97#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.231.07:41:57.97#ibcon#ireg 11 cls_cnt 2 2006.231.07:41:57.97#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:41:57.97#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:41:57.97#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:41:57.97#ibcon#enter wrdev, iclass 27, count 2 2006.231.07:41:57.97#ibcon#first serial, iclass 27, count 2 2006.231.07:41:57.97#ibcon#enter sib2, iclass 27, count 2 2006.231.07:41:57.97#ibcon#flushed, iclass 27, count 2 2006.231.07:41:57.97#ibcon#about to write, iclass 27, count 2 2006.231.07:41:57.97#ibcon#wrote, iclass 27, count 2 2006.231.07:41:57.97#ibcon#about to read 3, iclass 27, count 2 2006.231.07:41:57.99#ibcon#read 3, iclass 27, count 2 2006.231.07:41:57.99#ibcon#about to read 4, iclass 27, count 2 2006.231.07:41:57.99#ibcon#read 4, iclass 27, count 2 2006.231.07:41:57.99#ibcon#about to read 5, iclass 27, count 2 2006.231.07:41:57.99#ibcon#read 5, iclass 27, count 2 2006.231.07:41:57.99#ibcon#about to read 6, iclass 27, count 2 2006.231.07:41:57.99#ibcon#read 6, iclass 27, count 2 2006.231.07:41:57.99#ibcon#end of sib2, iclass 27, count 2 2006.231.07:41:57.99#ibcon#*mode == 0, iclass 27, count 2 2006.231.07:41:57.99#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.231.07:41:57.99#ibcon#[25=AT01-08\r\n] 2006.231.07:41:57.99#ibcon#*before write, iclass 27, count 2 2006.231.07:41:57.99#ibcon#enter sib2, iclass 27, count 2 2006.231.07:41:57.99#ibcon#flushed, iclass 27, count 2 2006.231.07:41:57.99#ibcon#about to write, iclass 27, count 2 2006.231.07:41:57.99#ibcon#wrote, iclass 27, count 2 2006.231.07:41:57.99#ibcon#about to read 3, iclass 27, count 2 2006.231.07:41:58.02#ibcon#read 3, iclass 27, count 2 2006.231.07:41:58.02#ibcon#about to read 4, iclass 27, count 2 2006.231.07:41:58.02#ibcon#read 4, iclass 27, count 2 2006.231.07:41:58.02#ibcon#about to read 5, iclass 27, count 2 2006.231.07:41:58.02#ibcon#read 5, iclass 27, count 2 2006.231.07:41:58.02#ibcon#about to read 6, iclass 27, count 2 2006.231.07:41:58.02#ibcon#read 6, iclass 27, count 2 2006.231.07:41:58.02#ibcon#end of sib2, iclass 27, count 2 2006.231.07:41:58.02#ibcon#*after write, iclass 27, count 2 2006.231.07:41:58.02#ibcon#*before return 0, iclass 27, count 2 2006.231.07:41:58.02#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:41:58.02#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:41:58.02#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.231.07:41:58.02#ibcon#ireg 7 cls_cnt 0 2006.231.07:41:58.02#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:41:58.14#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:41:58.14#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:41:58.14#ibcon#enter wrdev, iclass 27, count 0 2006.231.07:41:58.14#ibcon#first serial, iclass 27, count 0 2006.231.07:41:58.14#ibcon#enter sib2, iclass 27, count 0 2006.231.07:41:58.14#ibcon#flushed, iclass 27, count 0 2006.231.07:41:58.14#ibcon#about to write, iclass 27, count 0 2006.231.07:41:58.14#ibcon#wrote, iclass 27, count 0 2006.231.07:41:58.14#ibcon#about to read 3, iclass 27, count 0 2006.231.07:41:58.16#ibcon#read 3, iclass 27, count 0 2006.231.07:41:58.16#ibcon#about to read 4, iclass 27, count 0 2006.231.07:41:58.16#ibcon#read 4, iclass 27, count 0 2006.231.07:41:58.16#ibcon#about to read 5, iclass 27, count 0 2006.231.07:41:58.16#ibcon#read 5, iclass 27, count 0 2006.231.07:41:58.16#ibcon#about to read 6, iclass 27, count 0 2006.231.07:41:58.16#ibcon#read 6, iclass 27, count 0 2006.231.07:41:58.16#ibcon#end of sib2, iclass 27, count 0 2006.231.07:41:58.16#ibcon#*mode == 0, iclass 27, count 0 2006.231.07:41:58.16#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.07:41:58.16#ibcon#[25=USB\r\n] 2006.231.07:41:58.16#ibcon#*before write, iclass 27, count 0 2006.231.07:41:58.16#ibcon#enter sib2, iclass 27, count 0 2006.231.07:41:58.16#ibcon#flushed, iclass 27, count 0 2006.231.07:41:58.16#ibcon#about to write, iclass 27, count 0 2006.231.07:41:58.16#ibcon#wrote, iclass 27, count 0 2006.231.07:41:58.16#ibcon#about to read 3, iclass 27, count 0 2006.231.07:41:58.19#ibcon#read 3, iclass 27, count 0 2006.231.07:41:58.19#ibcon#about to read 4, iclass 27, count 0 2006.231.07:41:58.19#ibcon#read 4, iclass 27, count 0 2006.231.07:41:58.19#ibcon#about to read 5, iclass 27, count 0 2006.231.07:41:58.19#ibcon#read 5, iclass 27, count 0 2006.231.07:41:58.19#ibcon#about to read 6, iclass 27, count 0 2006.231.07:41:58.19#ibcon#read 6, iclass 27, count 0 2006.231.07:41:58.19#ibcon#end of sib2, iclass 27, count 0 2006.231.07:41:58.19#ibcon#*after write, iclass 27, count 0 2006.231.07:41:58.19#ibcon#*before return 0, iclass 27, count 0 2006.231.07:41:58.19#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:41:58.19#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:41:58.19#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.07:41:58.19#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.07:41:58.19$vc4f8/valo=2,572.99 2006.231.07:41:58.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.231.07:41:58.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.231.07:41:58.19#ibcon#ireg 17 cls_cnt 0 2006.231.07:41:58.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:41:58.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:41:58.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:41:58.19#ibcon#enter wrdev, iclass 29, count 0 2006.231.07:41:58.19#ibcon#first serial, iclass 29, count 0 2006.231.07:41:58.19#ibcon#enter sib2, iclass 29, count 0 2006.231.07:41:58.19#ibcon#flushed, iclass 29, count 0 2006.231.07:41:58.19#ibcon#about to write, iclass 29, count 0 2006.231.07:41:58.19#ibcon#wrote, iclass 29, count 0 2006.231.07:41:58.19#ibcon#about to read 3, iclass 29, count 0 2006.231.07:41:58.21#ibcon#read 3, iclass 29, count 0 2006.231.07:41:58.21#ibcon#about to read 4, iclass 29, count 0 2006.231.07:41:58.21#ibcon#read 4, iclass 29, count 0 2006.231.07:41:58.21#ibcon#about to read 5, iclass 29, count 0 2006.231.07:41:58.21#ibcon#read 5, iclass 29, count 0 2006.231.07:41:58.21#ibcon#about to read 6, iclass 29, count 0 2006.231.07:41:58.21#ibcon#read 6, iclass 29, count 0 2006.231.07:41:58.21#ibcon#end of sib2, iclass 29, count 0 2006.231.07:41:58.21#ibcon#*mode == 0, iclass 29, count 0 2006.231.07:41:58.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.07:41:58.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:41:58.21#ibcon#*before write, iclass 29, count 0 2006.231.07:41:58.21#ibcon#enter sib2, iclass 29, count 0 2006.231.07:41:58.21#ibcon#flushed, iclass 29, count 0 2006.231.07:41:58.21#ibcon#about to write, iclass 29, count 0 2006.231.07:41:58.21#ibcon#wrote, iclass 29, count 0 2006.231.07:41:58.21#ibcon#about to read 3, iclass 29, count 0 2006.231.07:41:58.25#ibcon#read 3, iclass 29, count 0 2006.231.07:41:58.25#ibcon#about to read 4, iclass 29, count 0 2006.231.07:41:58.25#ibcon#read 4, iclass 29, count 0 2006.231.07:41:58.25#ibcon#about to read 5, iclass 29, count 0 2006.231.07:41:58.25#ibcon#read 5, iclass 29, count 0 2006.231.07:41:58.25#ibcon#about to read 6, iclass 29, count 0 2006.231.07:41:58.25#ibcon#read 6, iclass 29, count 0 2006.231.07:41:58.25#ibcon#end of sib2, iclass 29, count 0 2006.231.07:41:58.25#ibcon#*after write, iclass 29, count 0 2006.231.07:41:58.25#ibcon#*before return 0, iclass 29, count 0 2006.231.07:41:58.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:41:58.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:41:58.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.07:41:58.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.07:41:58.25$vc4f8/va=2,7 2006.231.07:41:58.25#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.231.07:41:58.25#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.231.07:41:58.25#ibcon#ireg 11 cls_cnt 2 2006.231.07:41:58.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:41:58.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:41:58.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:41:58.31#ibcon#enter wrdev, iclass 31, count 2 2006.231.07:41:58.31#ibcon#first serial, iclass 31, count 2 2006.231.07:41:58.31#ibcon#enter sib2, iclass 31, count 2 2006.231.07:41:58.31#ibcon#flushed, iclass 31, count 2 2006.231.07:41:58.31#ibcon#about to write, iclass 31, count 2 2006.231.07:41:58.31#ibcon#wrote, iclass 31, count 2 2006.231.07:41:58.31#ibcon#about to read 3, iclass 31, count 2 2006.231.07:41:58.33#ibcon#read 3, iclass 31, count 2 2006.231.07:41:58.33#ibcon#about to read 4, iclass 31, count 2 2006.231.07:41:58.33#ibcon#read 4, iclass 31, count 2 2006.231.07:41:58.33#ibcon#about to read 5, iclass 31, count 2 2006.231.07:41:58.33#ibcon#read 5, iclass 31, count 2 2006.231.07:41:58.33#ibcon#about to read 6, iclass 31, count 2 2006.231.07:41:58.33#ibcon#read 6, iclass 31, count 2 2006.231.07:41:58.33#ibcon#end of sib2, iclass 31, count 2 2006.231.07:41:58.33#ibcon#*mode == 0, iclass 31, count 2 2006.231.07:41:58.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.231.07:41:58.33#ibcon#[25=AT02-07\r\n] 2006.231.07:41:58.33#ibcon#*before write, iclass 31, count 2 2006.231.07:41:58.33#ibcon#enter sib2, iclass 31, count 2 2006.231.07:41:58.33#ibcon#flushed, iclass 31, count 2 2006.231.07:41:58.33#ibcon#about to write, iclass 31, count 2 2006.231.07:41:58.33#ibcon#wrote, iclass 31, count 2 2006.231.07:41:58.33#ibcon#about to read 3, iclass 31, count 2 2006.231.07:41:58.36#ibcon#read 3, iclass 31, count 2 2006.231.07:41:58.36#ibcon#about to read 4, iclass 31, count 2 2006.231.07:41:58.36#ibcon#read 4, iclass 31, count 2 2006.231.07:41:58.36#ibcon#about to read 5, iclass 31, count 2 2006.231.07:41:58.36#ibcon#read 5, iclass 31, count 2 2006.231.07:41:58.36#ibcon#about to read 6, iclass 31, count 2 2006.231.07:41:58.36#ibcon#read 6, iclass 31, count 2 2006.231.07:41:58.36#ibcon#end of sib2, iclass 31, count 2 2006.231.07:41:58.36#ibcon#*after write, iclass 31, count 2 2006.231.07:41:58.36#ibcon#*before return 0, iclass 31, count 2 2006.231.07:41:58.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:41:58.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:41:58.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.231.07:41:58.36#ibcon#ireg 7 cls_cnt 0 2006.231.07:41:58.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:41:58.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:41:58.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:41:58.48#ibcon#enter wrdev, iclass 31, count 0 2006.231.07:41:58.48#ibcon#first serial, iclass 31, count 0 2006.231.07:41:58.48#ibcon#enter sib2, iclass 31, count 0 2006.231.07:41:58.48#ibcon#flushed, iclass 31, count 0 2006.231.07:41:58.48#ibcon#about to write, iclass 31, count 0 2006.231.07:41:58.48#ibcon#wrote, iclass 31, count 0 2006.231.07:41:58.48#ibcon#about to read 3, iclass 31, count 0 2006.231.07:41:58.50#ibcon#read 3, iclass 31, count 0 2006.231.07:41:58.50#ibcon#about to read 4, iclass 31, count 0 2006.231.07:41:58.50#ibcon#read 4, iclass 31, count 0 2006.231.07:41:58.50#ibcon#about to read 5, iclass 31, count 0 2006.231.07:41:58.50#ibcon#read 5, iclass 31, count 0 2006.231.07:41:58.50#ibcon#about to read 6, iclass 31, count 0 2006.231.07:41:58.50#ibcon#read 6, iclass 31, count 0 2006.231.07:41:58.50#ibcon#end of sib2, iclass 31, count 0 2006.231.07:41:58.50#ibcon#*mode == 0, iclass 31, count 0 2006.231.07:41:58.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.07:41:58.50#ibcon#[25=USB\r\n] 2006.231.07:41:58.50#ibcon#*before write, iclass 31, count 0 2006.231.07:41:58.50#ibcon#enter sib2, iclass 31, count 0 2006.231.07:41:58.50#ibcon#flushed, iclass 31, count 0 2006.231.07:41:58.50#ibcon#about to write, iclass 31, count 0 2006.231.07:41:58.50#ibcon#wrote, iclass 31, count 0 2006.231.07:41:58.50#ibcon#about to read 3, iclass 31, count 0 2006.231.07:41:58.53#ibcon#read 3, iclass 31, count 0 2006.231.07:41:58.53#ibcon#about to read 4, iclass 31, count 0 2006.231.07:41:58.53#ibcon#read 4, iclass 31, count 0 2006.231.07:41:58.53#ibcon#about to read 5, iclass 31, count 0 2006.231.07:41:58.53#ibcon#read 5, iclass 31, count 0 2006.231.07:41:58.53#ibcon#about to read 6, iclass 31, count 0 2006.231.07:41:58.53#ibcon#read 6, iclass 31, count 0 2006.231.07:41:58.53#ibcon#end of sib2, iclass 31, count 0 2006.231.07:41:58.53#ibcon#*after write, iclass 31, count 0 2006.231.07:41:58.53#ibcon#*before return 0, iclass 31, count 0 2006.231.07:41:58.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:41:58.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:41:58.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.07:41:58.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.07:41:58.53$vc4f8/valo=3,672.99 2006.231.07:41:58.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.07:41:58.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.07:41:58.53#ibcon#ireg 17 cls_cnt 0 2006.231.07:41:58.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:41:58.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:41:58.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:41:58.53#ibcon#enter wrdev, iclass 33, count 0 2006.231.07:41:58.53#ibcon#first serial, iclass 33, count 0 2006.231.07:41:58.53#ibcon#enter sib2, iclass 33, count 0 2006.231.07:41:58.53#ibcon#flushed, iclass 33, count 0 2006.231.07:41:58.53#ibcon#about to write, iclass 33, count 0 2006.231.07:41:58.53#ibcon#wrote, iclass 33, count 0 2006.231.07:41:58.53#ibcon#about to read 3, iclass 33, count 0 2006.231.07:41:58.55#ibcon#read 3, iclass 33, count 0 2006.231.07:41:58.55#ibcon#about to read 4, iclass 33, count 0 2006.231.07:41:58.55#ibcon#read 4, iclass 33, count 0 2006.231.07:41:58.55#ibcon#about to read 5, iclass 33, count 0 2006.231.07:41:58.55#ibcon#read 5, iclass 33, count 0 2006.231.07:41:58.55#ibcon#about to read 6, iclass 33, count 0 2006.231.07:41:58.55#ibcon#read 6, iclass 33, count 0 2006.231.07:41:58.55#ibcon#end of sib2, iclass 33, count 0 2006.231.07:41:58.55#ibcon#*mode == 0, iclass 33, count 0 2006.231.07:41:58.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.07:41:58.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:41:58.55#ibcon#*before write, iclass 33, count 0 2006.231.07:41:58.55#ibcon#enter sib2, iclass 33, count 0 2006.231.07:41:58.55#ibcon#flushed, iclass 33, count 0 2006.231.07:41:58.55#ibcon#about to write, iclass 33, count 0 2006.231.07:41:58.55#ibcon#wrote, iclass 33, count 0 2006.231.07:41:58.55#ibcon#about to read 3, iclass 33, count 0 2006.231.07:41:58.59#ibcon#read 3, iclass 33, count 0 2006.231.07:41:58.59#ibcon#about to read 4, iclass 33, count 0 2006.231.07:41:58.59#ibcon#read 4, iclass 33, count 0 2006.231.07:41:58.59#ibcon#about to read 5, iclass 33, count 0 2006.231.07:41:58.59#ibcon#read 5, iclass 33, count 0 2006.231.07:41:58.59#ibcon#about to read 6, iclass 33, count 0 2006.231.07:41:58.59#ibcon#read 6, iclass 33, count 0 2006.231.07:41:58.59#ibcon#end of sib2, iclass 33, count 0 2006.231.07:41:58.59#ibcon#*after write, iclass 33, count 0 2006.231.07:41:58.59#ibcon#*before return 0, iclass 33, count 0 2006.231.07:41:58.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:41:58.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:41:58.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.07:41:58.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.07:41:58.59$vc4f8/va=3,8 2006.231.07:41:58.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.07:41:58.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.07:41:58.59#ibcon#ireg 11 cls_cnt 2 2006.231.07:41:58.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:41:58.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:41:58.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:41:58.65#ibcon#enter wrdev, iclass 35, count 2 2006.231.07:41:58.65#ibcon#first serial, iclass 35, count 2 2006.231.07:41:58.65#ibcon#enter sib2, iclass 35, count 2 2006.231.07:41:58.65#ibcon#flushed, iclass 35, count 2 2006.231.07:41:58.65#ibcon#about to write, iclass 35, count 2 2006.231.07:41:58.65#ibcon#wrote, iclass 35, count 2 2006.231.07:41:58.65#ibcon#about to read 3, iclass 35, count 2 2006.231.07:41:58.67#ibcon#read 3, iclass 35, count 2 2006.231.07:41:58.67#ibcon#about to read 4, iclass 35, count 2 2006.231.07:41:58.67#ibcon#read 4, iclass 35, count 2 2006.231.07:41:58.67#ibcon#about to read 5, iclass 35, count 2 2006.231.07:41:58.67#ibcon#read 5, iclass 35, count 2 2006.231.07:41:58.67#ibcon#about to read 6, iclass 35, count 2 2006.231.07:41:58.67#ibcon#read 6, iclass 35, count 2 2006.231.07:41:58.67#ibcon#end of sib2, iclass 35, count 2 2006.231.07:41:58.67#ibcon#*mode == 0, iclass 35, count 2 2006.231.07:41:58.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.07:41:58.67#ibcon#[25=AT03-08\r\n] 2006.231.07:41:58.67#ibcon#*before write, iclass 35, count 2 2006.231.07:41:58.67#ibcon#enter sib2, iclass 35, count 2 2006.231.07:41:58.67#ibcon#flushed, iclass 35, count 2 2006.231.07:41:58.67#ibcon#about to write, iclass 35, count 2 2006.231.07:41:58.67#ibcon#wrote, iclass 35, count 2 2006.231.07:41:58.67#ibcon#about to read 3, iclass 35, count 2 2006.231.07:41:58.70#ibcon#read 3, iclass 35, count 2 2006.231.07:41:58.70#ibcon#about to read 4, iclass 35, count 2 2006.231.07:41:58.70#ibcon#read 4, iclass 35, count 2 2006.231.07:41:58.70#ibcon#about to read 5, iclass 35, count 2 2006.231.07:41:58.70#ibcon#read 5, iclass 35, count 2 2006.231.07:41:58.70#ibcon#about to read 6, iclass 35, count 2 2006.231.07:41:58.70#ibcon#read 6, iclass 35, count 2 2006.231.07:41:58.70#ibcon#end of sib2, iclass 35, count 2 2006.231.07:41:58.70#ibcon#*after write, iclass 35, count 2 2006.231.07:41:58.70#ibcon#*before return 0, iclass 35, count 2 2006.231.07:41:58.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:41:58.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:41:58.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.07:41:58.70#ibcon#ireg 7 cls_cnt 0 2006.231.07:41:58.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:41:58.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:41:58.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:41:58.82#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:41:58.82#ibcon#first serial, iclass 35, count 0 2006.231.07:41:58.82#ibcon#enter sib2, iclass 35, count 0 2006.231.07:41:58.82#ibcon#flushed, iclass 35, count 0 2006.231.07:41:58.82#ibcon#about to write, iclass 35, count 0 2006.231.07:41:58.82#ibcon#wrote, iclass 35, count 0 2006.231.07:41:58.82#ibcon#about to read 3, iclass 35, count 0 2006.231.07:41:58.84#ibcon#read 3, iclass 35, count 0 2006.231.07:41:58.84#ibcon#about to read 4, iclass 35, count 0 2006.231.07:41:58.84#ibcon#read 4, iclass 35, count 0 2006.231.07:41:58.84#ibcon#about to read 5, iclass 35, count 0 2006.231.07:41:58.84#ibcon#read 5, iclass 35, count 0 2006.231.07:41:58.84#ibcon#about to read 6, iclass 35, count 0 2006.231.07:41:58.84#ibcon#read 6, iclass 35, count 0 2006.231.07:41:58.84#ibcon#end of sib2, iclass 35, count 0 2006.231.07:41:58.84#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:41:58.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:41:58.84#ibcon#[25=USB\r\n] 2006.231.07:41:58.84#ibcon#*before write, iclass 35, count 0 2006.231.07:41:58.84#ibcon#enter sib2, iclass 35, count 0 2006.231.07:41:58.84#ibcon#flushed, iclass 35, count 0 2006.231.07:41:58.84#ibcon#about to write, iclass 35, count 0 2006.231.07:41:58.84#ibcon#wrote, iclass 35, count 0 2006.231.07:41:58.84#ibcon#about to read 3, iclass 35, count 0 2006.231.07:41:58.87#ibcon#read 3, iclass 35, count 0 2006.231.07:41:58.87#ibcon#about to read 4, iclass 35, count 0 2006.231.07:41:58.87#ibcon#read 4, iclass 35, count 0 2006.231.07:41:58.87#ibcon#about to read 5, iclass 35, count 0 2006.231.07:41:58.87#ibcon#read 5, iclass 35, count 0 2006.231.07:41:58.87#ibcon#about to read 6, iclass 35, count 0 2006.231.07:41:58.87#ibcon#read 6, iclass 35, count 0 2006.231.07:41:58.87#ibcon#end of sib2, iclass 35, count 0 2006.231.07:41:58.87#ibcon#*after write, iclass 35, count 0 2006.231.07:41:58.87#ibcon#*before return 0, iclass 35, count 0 2006.231.07:41:58.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:41:58.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:41:58.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:41:58.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:41:58.87$vc4f8/valo=4,832.99 2006.231.07:41:58.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.07:41:58.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.07:41:58.87#ibcon#ireg 17 cls_cnt 0 2006.231.07:41:58.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:41:58.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:41:58.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:41:58.87#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:41:58.87#ibcon#first serial, iclass 37, count 0 2006.231.07:41:58.87#ibcon#enter sib2, iclass 37, count 0 2006.231.07:41:58.87#ibcon#flushed, iclass 37, count 0 2006.231.07:41:58.87#ibcon#about to write, iclass 37, count 0 2006.231.07:41:58.87#ibcon#wrote, iclass 37, count 0 2006.231.07:41:58.87#ibcon#about to read 3, iclass 37, count 0 2006.231.07:41:58.89#ibcon#read 3, iclass 37, count 0 2006.231.07:41:58.89#ibcon#about to read 4, iclass 37, count 0 2006.231.07:41:58.89#ibcon#read 4, iclass 37, count 0 2006.231.07:41:58.89#ibcon#about to read 5, iclass 37, count 0 2006.231.07:41:58.89#ibcon#read 5, iclass 37, count 0 2006.231.07:41:58.89#ibcon#about to read 6, iclass 37, count 0 2006.231.07:41:58.89#ibcon#read 6, iclass 37, count 0 2006.231.07:41:58.89#ibcon#end of sib2, iclass 37, count 0 2006.231.07:41:58.89#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:41:58.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:41:58.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:41:58.89#ibcon#*before write, iclass 37, count 0 2006.231.07:41:58.89#ibcon#enter sib2, iclass 37, count 0 2006.231.07:41:58.89#ibcon#flushed, iclass 37, count 0 2006.231.07:41:58.89#ibcon#about to write, iclass 37, count 0 2006.231.07:41:58.89#ibcon#wrote, iclass 37, count 0 2006.231.07:41:58.89#ibcon#about to read 3, iclass 37, count 0 2006.231.07:41:58.93#ibcon#read 3, iclass 37, count 0 2006.231.07:41:58.93#ibcon#about to read 4, iclass 37, count 0 2006.231.07:41:58.93#ibcon#read 4, iclass 37, count 0 2006.231.07:41:58.93#ibcon#about to read 5, iclass 37, count 0 2006.231.07:41:58.93#ibcon#read 5, iclass 37, count 0 2006.231.07:41:58.93#ibcon#about to read 6, iclass 37, count 0 2006.231.07:41:58.93#ibcon#read 6, iclass 37, count 0 2006.231.07:41:58.93#ibcon#end of sib2, iclass 37, count 0 2006.231.07:41:58.93#ibcon#*after write, iclass 37, count 0 2006.231.07:41:58.93#ibcon#*before return 0, iclass 37, count 0 2006.231.07:41:58.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:41:58.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:41:58.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:41:58.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:41:58.93$vc4f8/va=4,7 2006.231.07:41:58.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.07:41:58.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.07:41:58.93#ibcon#ireg 11 cls_cnt 2 2006.231.07:41:58.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:41:58.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:41:58.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:41:58.99#ibcon#enter wrdev, iclass 39, count 2 2006.231.07:41:58.99#ibcon#first serial, iclass 39, count 2 2006.231.07:41:58.99#ibcon#enter sib2, iclass 39, count 2 2006.231.07:41:58.99#ibcon#flushed, iclass 39, count 2 2006.231.07:41:58.99#ibcon#about to write, iclass 39, count 2 2006.231.07:41:58.99#ibcon#wrote, iclass 39, count 2 2006.231.07:41:58.99#ibcon#about to read 3, iclass 39, count 2 2006.231.07:41:59.01#ibcon#read 3, iclass 39, count 2 2006.231.07:41:59.01#ibcon#about to read 4, iclass 39, count 2 2006.231.07:41:59.01#ibcon#read 4, iclass 39, count 2 2006.231.07:41:59.01#ibcon#about to read 5, iclass 39, count 2 2006.231.07:41:59.01#ibcon#read 5, iclass 39, count 2 2006.231.07:41:59.01#ibcon#about to read 6, iclass 39, count 2 2006.231.07:41:59.01#ibcon#read 6, iclass 39, count 2 2006.231.07:41:59.01#ibcon#end of sib2, iclass 39, count 2 2006.231.07:41:59.01#ibcon#*mode == 0, iclass 39, count 2 2006.231.07:41:59.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.07:41:59.01#ibcon#[25=AT04-07\r\n] 2006.231.07:41:59.01#ibcon#*before write, iclass 39, count 2 2006.231.07:41:59.01#ibcon#enter sib2, iclass 39, count 2 2006.231.07:41:59.01#ibcon#flushed, iclass 39, count 2 2006.231.07:41:59.01#ibcon#about to write, iclass 39, count 2 2006.231.07:41:59.01#ibcon#wrote, iclass 39, count 2 2006.231.07:41:59.01#ibcon#about to read 3, iclass 39, count 2 2006.231.07:41:59.04#ibcon#read 3, iclass 39, count 2 2006.231.07:41:59.04#ibcon#about to read 4, iclass 39, count 2 2006.231.07:41:59.04#ibcon#read 4, iclass 39, count 2 2006.231.07:41:59.04#ibcon#about to read 5, iclass 39, count 2 2006.231.07:41:59.04#ibcon#read 5, iclass 39, count 2 2006.231.07:41:59.04#ibcon#about to read 6, iclass 39, count 2 2006.231.07:41:59.04#ibcon#read 6, iclass 39, count 2 2006.231.07:41:59.04#ibcon#end of sib2, iclass 39, count 2 2006.231.07:41:59.04#ibcon#*after write, iclass 39, count 2 2006.231.07:41:59.04#ibcon#*before return 0, iclass 39, count 2 2006.231.07:41:59.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:41:59.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:41:59.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.07:41:59.04#ibcon#ireg 7 cls_cnt 0 2006.231.07:41:59.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:41:59.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:41:59.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:41:59.16#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:41:59.16#ibcon#first serial, iclass 39, count 0 2006.231.07:41:59.16#ibcon#enter sib2, iclass 39, count 0 2006.231.07:41:59.16#ibcon#flushed, iclass 39, count 0 2006.231.07:41:59.16#ibcon#about to write, iclass 39, count 0 2006.231.07:41:59.16#ibcon#wrote, iclass 39, count 0 2006.231.07:41:59.16#ibcon#about to read 3, iclass 39, count 0 2006.231.07:41:59.18#ibcon#read 3, iclass 39, count 0 2006.231.07:41:59.18#ibcon#about to read 4, iclass 39, count 0 2006.231.07:41:59.18#ibcon#read 4, iclass 39, count 0 2006.231.07:41:59.18#ibcon#about to read 5, iclass 39, count 0 2006.231.07:41:59.18#ibcon#read 5, iclass 39, count 0 2006.231.07:41:59.18#ibcon#about to read 6, iclass 39, count 0 2006.231.07:41:59.18#ibcon#read 6, iclass 39, count 0 2006.231.07:41:59.18#ibcon#end of sib2, iclass 39, count 0 2006.231.07:41:59.18#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:41:59.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:41:59.18#ibcon#[25=USB\r\n] 2006.231.07:41:59.18#ibcon#*before write, iclass 39, count 0 2006.231.07:41:59.18#ibcon#enter sib2, iclass 39, count 0 2006.231.07:41:59.18#ibcon#flushed, iclass 39, count 0 2006.231.07:41:59.18#ibcon#about to write, iclass 39, count 0 2006.231.07:41:59.18#ibcon#wrote, iclass 39, count 0 2006.231.07:41:59.18#ibcon#about to read 3, iclass 39, count 0 2006.231.07:41:59.21#ibcon#read 3, iclass 39, count 0 2006.231.07:41:59.21#ibcon#about to read 4, iclass 39, count 0 2006.231.07:41:59.21#ibcon#read 4, iclass 39, count 0 2006.231.07:41:59.21#ibcon#about to read 5, iclass 39, count 0 2006.231.07:41:59.21#ibcon#read 5, iclass 39, count 0 2006.231.07:41:59.21#ibcon#about to read 6, iclass 39, count 0 2006.231.07:41:59.21#ibcon#read 6, iclass 39, count 0 2006.231.07:41:59.21#ibcon#end of sib2, iclass 39, count 0 2006.231.07:41:59.21#ibcon#*after write, iclass 39, count 0 2006.231.07:41:59.21#ibcon#*before return 0, iclass 39, count 0 2006.231.07:41:59.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:41:59.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:41:59.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:41:59.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:41:59.21$vc4f8/valo=5,652.99 2006.231.07:41:59.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.07:41:59.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.07:41:59.21#ibcon#ireg 17 cls_cnt 0 2006.231.07:41:59.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:41:59.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:41:59.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:41:59.21#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:41:59.21#ibcon#first serial, iclass 3, count 0 2006.231.07:41:59.21#ibcon#enter sib2, iclass 3, count 0 2006.231.07:41:59.21#ibcon#flushed, iclass 3, count 0 2006.231.07:41:59.21#ibcon#about to write, iclass 3, count 0 2006.231.07:41:59.21#ibcon#wrote, iclass 3, count 0 2006.231.07:41:59.21#ibcon#about to read 3, iclass 3, count 0 2006.231.07:41:59.23#ibcon#read 3, iclass 3, count 0 2006.231.07:41:59.23#ibcon#about to read 4, iclass 3, count 0 2006.231.07:41:59.23#ibcon#read 4, iclass 3, count 0 2006.231.07:41:59.23#ibcon#about to read 5, iclass 3, count 0 2006.231.07:41:59.23#ibcon#read 5, iclass 3, count 0 2006.231.07:41:59.23#ibcon#about to read 6, iclass 3, count 0 2006.231.07:41:59.23#ibcon#read 6, iclass 3, count 0 2006.231.07:41:59.23#ibcon#end of sib2, iclass 3, count 0 2006.231.07:41:59.23#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:41:59.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:41:59.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:41:59.23#ibcon#*before write, iclass 3, count 0 2006.231.07:41:59.23#ibcon#enter sib2, iclass 3, count 0 2006.231.07:41:59.23#ibcon#flushed, iclass 3, count 0 2006.231.07:41:59.23#ibcon#about to write, iclass 3, count 0 2006.231.07:41:59.23#ibcon#wrote, iclass 3, count 0 2006.231.07:41:59.23#ibcon#about to read 3, iclass 3, count 0 2006.231.07:41:59.27#ibcon#read 3, iclass 3, count 0 2006.231.07:41:59.27#ibcon#about to read 4, iclass 3, count 0 2006.231.07:41:59.27#ibcon#read 4, iclass 3, count 0 2006.231.07:41:59.27#ibcon#about to read 5, iclass 3, count 0 2006.231.07:41:59.27#ibcon#read 5, iclass 3, count 0 2006.231.07:41:59.27#ibcon#about to read 6, iclass 3, count 0 2006.231.07:41:59.27#ibcon#read 6, iclass 3, count 0 2006.231.07:41:59.27#ibcon#end of sib2, iclass 3, count 0 2006.231.07:41:59.27#ibcon#*after write, iclass 3, count 0 2006.231.07:41:59.27#ibcon#*before return 0, iclass 3, count 0 2006.231.07:41:59.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:41:59.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:41:59.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:41:59.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:41:59.27$vc4f8/va=5,7 2006.231.07:41:59.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.07:41:59.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.07:41:59.27#ibcon#ireg 11 cls_cnt 2 2006.231.07:41:59.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:41:59.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:41:59.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:41:59.33#ibcon#enter wrdev, iclass 5, count 2 2006.231.07:41:59.33#ibcon#first serial, iclass 5, count 2 2006.231.07:41:59.33#ibcon#enter sib2, iclass 5, count 2 2006.231.07:41:59.33#ibcon#flushed, iclass 5, count 2 2006.231.07:41:59.33#ibcon#about to write, iclass 5, count 2 2006.231.07:41:59.33#ibcon#wrote, iclass 5, count 2 2006.231.07:41:59.33#ibcon#about to read 3, iclass 5, count 2 2006.231.07:41:59.35#ibcon#read 3, iclass 5, count 2 2006.231.07:41:59.35#ibcon#about to read 4, iclass 5, count 2 2006.231.07:41:59.35#ibcon#read 4, iclass 5, count 2 2006.231.07:41:59.35#ibcon#about to read 5, iclass 5, count 2 2006.231.07:41:59.35#ibcon#read 5, iclass 5, count 2 2006.231.07:41:59.35#ibcon#about to read 6, iclass 5, count 2 2006.231.07:41:59.35#ibcon#read 6, iclass 5, count 2 2006.231.07:41:59.35#ibcon#end of sib2, iclass 5, count 2 2006.231.07:41:59.35#ibcon#*mode == 0, iclass 5, count 2 2006.231.07:41:59.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.07:41:59.35#ibcon#[25=AT05-07\r\n] 2006.231.07:41:59.35#ibcon#*before write, iclass 5, count 2 2006.231.07:41:59.35#ibcon#enter sib2, iclass 5, count 2 2006.231.07:41:59.35#ibcon#flushed, iclass 5, count 2 2006.231.07:41:59.35#ibcon#about to write, iclass 5, count 2 2006.231.07:41:59.35#ibcon#wrote, iclass 5, count 2 2006.231.07:41:59.35#ibcon#about to read 3, iclass 5, count 2 2006.231.07:41:59.38#ibcon#read 3, iclass 5, count 2 2006.231.07:41:59.38#ibcon#about to read 4, iclass 5, count 2 2006.231.07:41:59.38#ibcon#read 4, iclass 5, count 2 2006.231.07:41:59.38#ibcon#about to read 5, iclass 5, count 2 2006.231.07:41:59.38#ibcon#read 5, iclass 5, count 2 2006.231.07:41:59.38#ibcon#about to read 6, iclass 5, count 2 2006.231.07:41:59.38#ibcon#read 6, iclass 5, count 2 2006.231.07:41:59.38#ibcon#end of sib2, iclass 5, count 2 2006.231.07:41:59.38#ibcon#*after write, iclass 5, count 2 2006.231.07:41:59.38#ibcon#*before return 0, iclass 5, count 2 2006.231.07:41:59.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:41:59.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:41:59.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.07:41:59.38#ibcon#ireg 7 cls_cnt 0 2006.231.07:41:59.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:41:59.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:41:59.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:41:59.50#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:41:59.50#ibcon#first serial, iclass 5, count 0 2006.231.07:41:59.50#ibcon#enter sib2, iclass 5, count 0 2006.231.07:41:59.50#ibcon#flushed, iclass 5, count 0 2006.231.07:41:59.50#ibcon#about to write, iclass 5, count 0 2006.231.07:41:59.50#ibcon#wrote, iclass 5, count 0 2006.231.07:41:59.50#ibcon#about to read 3, iclass 5, count 0 2006.231.07:41:59.52#ibcon#read 3, iclass 5, count 0 2006.231.07:41:59.52#ibcon#about to read 4, iclass 5, count 0 2006.231.07:41:59.52#ibcon#read 4, iclass 5, count 0 2006.231.07:41:59.52#ibcon#about to read 5, iclass 5, count 0 2006.231.07:41:59.52#ibcon#read 5, iclass 5, count 0 2006.231.07:41:59.52#ibcon#about to read 6, iclass 5, count 0 2006.231.07:41:59.52#ibcon#read 6, iclass 5, count 0 2006.231.07:41:59.52#ibcon#end of sib2, iclass 5, count 0 2006.231.07:41:59.52#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:41:59.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:41:59.52#ibcon#[25=USB\r\n] 2006.231.07:41:59.52#ibcon#*before write, iclass 5, count 0 2006.231.07:41:59.52#ibcon#enter sib2, iclass 5, count 0 2006.231.07:41:59.52#ibcon#flushed, iclass 5, count 0 2006.231.07:41:59.52#ibcon#about to write, iclass 5, count 0 2006.231.07:41:59.52#ibcon#wrote, iclass 5, count 0 2006.231.07:41:59.52#ibcon#about to read 3, iclass 5, count 0 2006.231.07:41:59.55#ibcon#read 3, iclass 5, count 0 2006.231.07:41:59.55#ibcon#about to read 4, iclass 5, count 0 2006.231.07:41:59.55#ibcon#read 4, iclass 5, count 0 2006.231.07:41:59.55#ibcon#about to read 5, iclass 5, count 0 2006.231.07:41:59.55#ibcon#read 5, iclass 5, count 0 2006.231.07:41:59.55#ibcon#about to read 6, iclass 5, count 0 2006.231.07:41:59.55#ibcon#read 6, iclass 5, count 0 2006.231.07:41:59.55#ibcon#end of sib2, iclass 5, count 0 2006.231.07:41:59.55#ibcon#*after write, iclass 5, count 0 2006.231.07:41:59.55#ibcon#*before return 0, iclass 5, count 0 2006.231.07:41:59.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:41:59.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:41:59.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:41:59.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:41:59.55$vc4f8/valo=6,772.99 2006.231.07:41:59.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.07:41:59.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.07:41:59.55#ibcon#ireg 17 cls_cnt 0 2006.231.07:41:59.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:41:59.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:41:59.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:41:59.55#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:41:59.55#ibcon#first serial, iclass 7, count 0 2006.231.07:41:59.55#ibcon#enter sib2, iclass 7, count 0 2006.231.07:41:59.55#ibcon#flushed, iclass 7, count 0 2006.231.07:41:59.55#ibcon#about to write, iclass 7, count 0 2006.231.07:41:59.55#ibcon#wrote, iclass 7, count 0 2006.231.07:41:59.55#ibcon#about to read 3, iclass 7, count 0 2006.231.07:41:59.57#ibcon#read 3, iclass 7, count 0 2006.231.07:41:59.57#ibcon#about to read 4, iclass 7, count 0 2006.231.07:41:59.57#ibcon#read 4, iclass 7, count 0 2006.231.07:41:59.57#ibcon#about to read 5, iclass 7, count 0 2006.231.07:41:59.57#ibcon#read 5, iclass 7, count 0 2006.231.07:41:59.57#ibcon#about to read 6, iclass 7, count 0 2006.231.07:41:59.57#ibcon#read 6, iclass 7, count 0 2006.231.07:41:59.57#ibcon#end of sib2, iclass 7, count 0 2006.231.07:41:59.57#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:41:59.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:41:59.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:41:59.57#ibcon#*before write, iclass 7, count 0 2006.231.07:41:59.57#ibcon#enter sib2, iclass 7, count 0 2006.231.07:41:59.57#ibcon#flushed, iclass 7, count 0 2006.231.07:41:59.57#ibcon#about to write, iclass 7, count 0 2006.231.07:41:59.57#ibcon#wrote, iclass 7, count 0 2006.231.07:41:59.57#ibcon#about to read 3, iclass 7, count 0 2006.231.07:41:59.61#ibcon#read 3, iclass 7, count 0 2006.231.07:41:59.61#ibcon#about to read 4, iclass 7, count 0 2006.231.07:41:59.61#ibcon#read 4, iclass 7, count 0 2006.231.07:41:59.61#ibcon#about to read 5, iclass 7, count 0 2006.231.07:41:59.61#ibcon#read 5, iclass 7, count 0 2006.231.07:41:59.61#ibcon#about to read 6, iclass 7, count 0 2006.231.07:41:59.61#ibcon#read 6, iclass 7, count 0 2006.231.07:41:59.61#ibcon#end of sib2, iclass 7, count 0 2006.231.07:41:59.61#ibcon#*after write, iclass 7, count 0 2006.231.07:41:59.61#ibcon#*before return 0, iclass 7, count 0 2006.231.07:41:59.61#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:41:59.61#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:41:59.61#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:41:59.61#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:41:59.61$vc4f8/va=6,6 2006.231.07:41:59.61#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.07:41:59.61#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.07:41:59.61#ibcon#ireg 11 cls_cnt 2 2006.231.07:41:59.61#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:41:59.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:41:59.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:41:59.67#ibcon#enter wrdev, iclass 11, count 2 2006.231.07:41:59.67#ibcon#first serial, iclass 11, count 2 2006.231.07:41:59.67#ibcon#enter sib2, iclass 11, count 2 2006.231.07:41:59.67#ibcon#flushed, iclass 11, count 2 2006.231.07:41:59.67#ibcon#about to write, iclass 11, count 2 2006.231.07:41:59.67#ibcon#wrote, iclass 11, count 2 2006.231.07:41:59.67#ibcon#about to read 3, iclass 11, count 2 2006.231.07:41:59.69#ibcon#read 3, iclass 11, count 2 2006.231.07:41:59.69#ibcon#about to read 4, iclass 11, count 2 2006.231.07:41:59.69#ibcon#read 4, iclass 11, count 2 2006.231.07:41:59.69#ibcon#about to read 5, iclass 11, count 2 2006.231.07:41:59.69#ibcon#read 5, iclass 11, count 2 2006.231.07:41:59.69#ibcon#about to read 6, iclass 11, count 2 2006.231.07:41:59.69#ibcon#read 6, iclass 11, count 2 2006.231.07:41:59.69#ibcon#end of sib2, iclass 11, count 2 2006.231.07:41:59.69#ibcon#*mode == 0, iclass 11, count 2 2006.231.07:41:59.69#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.07:41:59.69#ibcon#[25=AT06-06\r\n] 2006.231.07:41:59.69#ibcon#*before write, iclass 11, count 2 2006.231.07:41:59.69#ibcon#enter sib2, iclass 11, count 2 2006.231.07:41:59.69#ibcon#flushed, iclass 11, count 2 2006.231.07:41:59.69#ibcon#about to write, iclass 11, count 2 2006.231.07:41:59.69#ibcon#wrote, iclass 11, count 2 2006.231.07:41:59.69#ibcon#about to read 3, iclass 11, count 2 2006.231.07:41:59.72#ibcon#read 3, iclass 11, count 2 2006.231.07:41:59.72#ibcon#about to read 4, iclass 11, count 2 2006.231.07:41:59.72#ibcon#read 4, iclass 11, count 2 2006.231.07:41:59.72#ibcon#about to read 5, iclass 11, count 2 2006.231.07:41:59.72#ibcon#read 5, iclass 11, count 2 2006.231.07:41:59.72#ibcon#about to read 6, iclass 11, count 2 2006.231.07:41:59.72#ibcon#read 6, iclass 11, count 2 2006.231.07:41:59.72#ibcon#end of sib2, iclass 11, count 2 2006.231.07:41:59.72#ibcon#*after write, iclass 11, count 2 2006.231.07:41:59.72#ibcon#*before return 0, iclass 11, count 2 2006.231.07:41:59.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:41:59.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:41:59.72#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.07:41:59.72#ibcon#ireg 7 cls_cnt 0 2006.231.07:41:59.72#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:41:59.84#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:41:59.84#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:41:59.84#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:41:59.84#ibcon#first serial, iclass 11, count 0 2006.231.07:41:59.84#ibcon#enter sib2, iclass 11, count 0 2006.231.07:41:59.84#ibcon#flushed, iclass 11, count 0 2006.231.07:41:59.84#ibcon#about to write, iclass 11, count 0 2006.231.07:41:59.84#ibcon#wrote, iclass 11, count 0 2006.231.07:41:59.84#ibcon#about to read 3, iclass 11, count 0 2006.231.07:41:59.86#ibcon#read 3, iclass 11, count 0 2006.231.07:41:59.86#ibcon#about to read 4, iclass 11, count 0 2006.231.07:41:59.86#ibcon#read 4, iclass 11, count 0 2006.231.07:41:59.86#ibcon#about to read 5, iclass 11, count 0 2006.231.07:41:59.86#ibcon#read 5, iclass 11, count 0 2006.231.07:41:59.86#ibcon#about to read 6, iclass 11, count 0 2006.231.07:41:59.86#ibcon#read 6, iclass 11, count 0 2006.231.07:41:59.86#ibcon#end of sib2, iclass 11, count 0 2006.231.07:41:59.86#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:41:59.86#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:41:59.86#ibcon#[25=USB\r\n] 2006.231.07:41:59.86#ibcon#*before write, iclass 11, count 0 2006.231.07:41:59.86#ibcon#enter sib2, iclass 11, count 0 2006.231.07:41:59.86#ibcon#flushed, iclass 11, count 0 2006.231.07:41:59.86#ibcon#about to write, iclass 11, count 0 2006.231.07:41:59.86#ibcon#wrote, iclass 11, count 0 2006.231.07:41:59.86#ibcon#about to read 3, iclass 11, count 0 2006.231.07:41:59.89#ibcon#read 3, iclass 11, count 0 2006.231.07:41:59.89#ibcon#about to read 4, iclass 11, count 0 2006.231.07:41:59.89#ibcon#read 4, iclass 11, count 0 2006.231.07:41:59.89#ibcon#about to read 5, iclass 11, count 0 2006.231.07:41:59.89#ibcon#read 5, iclass 11, count 0 2006.231.07:41:59.89#ibcon#about to read 6, iclass 11, count 0 2006.231.07:41:59.89#ibcon#read 6, iclass 11, count 0 2006.231.07:41:59.89#ibcon#end of sib2, iclass 11, count 0 2006.231.07:41:59.89#ibcon#*after write, iclass 11, count 0 2006.231.07:41:59.89#ibcon#*before return 0, iclass 11, count 0 2006.231.07:41:59.89#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:41:59.89#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:41:59.89#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:41:59.89#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:41:59.89$vc4f8/valo=7,832.99 2006.231.07:41:59.89#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.07:41:59.89#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.07:41:59.89#ibcon#ireg 17 cls_cnt 0 2006.231.07:41:59.89#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:41:59.89#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:41:59.89#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:41:59.89#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:41:59.89#ibcon#first serial, iclass 13, count 0 2006.231.07:41:59.89#ibcon#enter sib2, iclass 13, count 0 2006.231.07:41:59.89#ibcon#flushed, iclass 13, count 0 2006.231.07:41:59.89#ibcon#about to write, iclass 13, count 0 2006.231.07:41:59.89#ibcon#wrote, iclass 13, count 0 2006.231.07:41:59.89#ibcon#about to read 3, iclass 13, count 0 2006.231.07:41:59.91#ibcon#read 3, iclass 13, count 0 2006.231.07:41:59.91#ibcon#about to read 4, iclass 13, count 0 2006.231.07:41:59.91#ibcon#read 4, iclass 13, count 0 2006.231.07:41:59.91#ibcon#about to read 5, iclass 13, count 0 2006.231.07:41:59.91#ibcon#read 5, iclass 13, count 0 2006.231.07:41:59.91#ibcon#about to read 6, iclass 13, count 0 2006.231.07:41:59.91#ibcon#read 6, iclass 13, count 0 2006.231.07:41:59.91#ibcon#end of sib2, iclass 13, count 0 2006.231.07:41:59.91#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:41:59.91#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:41:59.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:41:59.91#ibcon#*before write, iclass 13, count 0 2006.231.07:41:59.91#ibcon#enter sib2, iclass 13, count 0 2006.231.07:41:59.91#ibcon#flushed, iclass 13, count 0 2006.231.07:41:59.91#ibcon#about to write, iclass 13, count 0 2006.231.07:41:59.91#ibcon#wrote, iclass 13, count 0 2006.231.07:41:59.91#ibcon#about to read 3, iclass 13, count 0 2006.231.07:41:59.95#ibcon#read 3, iclass 13, count 0 2006.231.07:41:59.95#ibcon#about to read 4, iclass 13, count 0 2006.231.07:41:59.95#ibcon#read 4, iclass 13, count 0 2006.231.07:41:59.95#ibcon#about to read 5, iclass 13, count 0 2006.231.07:41:59.95#ibcon#read 5, iclass 13, count 0 2006.231.07:41:59.95#ibcon#about to read 6, iclass 13, count 0 2006.231.07:41:59.95#ibcon#read 6, iclass 13, count 0 2006.231.07:41:59.95#ibcon#end of sib2, iclass 13, count 0 2006.231.07:41:59.95#ibcon#*after write, iclass 13, count 0 2006.231.07:41:59.95#ibcon#*before return 0, iclass 13, count 0 2006.231.07:41:59.95#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:41:59.95#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:41:59.95#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:41:59.95#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:41:59.95$vc4f8/va=7,6 2006.231.07:41:59.95#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.07:41:59.95#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.07:41:59.95#ibcon#ireg 11 cls_cnt 2 2006.231.07:41:59.95#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:42:00.01#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:42:00.01#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:42:00.01#ibcon#enter wrdev, iclass 15, count 2 2006.231.07:42:00.01#ibcon#first serial, iclass 15, count 2 2006.231.07:42:00.01#ibcon#enter sib2, iclass 15, count 2 2006.231.07:42:00.01#ibcon#flushed, iclass 15, count 2 2006.231.07:42:00.01#ibcon#about to write, iclass 15, count 2 2006.231.07:42:00.01#ibcon#wrote, iclass 15, count 2 2006.231.07:42:00.01#ibcon#about to read 3, iclass 15, count 2 2006.231.07:42:00.03#ibcon#read 3, iclass 15, count 2 2006.231.07:42:00.03#ibcon#about to read 4, iclass 15, count 2 2006.231.07:42:00.03#ibcon#read 4, iclass 15, count 2 2006.231.07:42:00.03#ibcon#about to read 5, iclass 15, count 2 2006.231.07:42:00.03#ibcon#read 5, iclass 15, count 2 2006.231.07:42:00.03#ibcon#about to read 6, iclass 15, count 2 2006.231.07:42:00.03#ibcon#read 6, iclass 15, count 2 2006.231.07:42:00.03#ibcon#end of sib2, iclass 15, count 2 2006.231.07:42:00.03#ibcon#*mode == 0, iclass 15, count 2 2006.231.07:42:00.03#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.07:42:00.03#ibcon#[25=AT07-06\r\n] 2006.231.07:42:00.03#ibcon#*before write, iclass 15, count 2 2006.231.07:42:00.03#ibcon#enter sib2, iclass 15, count 2 2006.231.07:42:00.03#ibcon#flushed, iclass 15, count 2 2006.231.07:42:00.03#ibcon#about to write, iclass 15, count 2 2006.231.07:42:00.03#ibcon#wrote, iclass 15, count 2 2006.231.07:42:00.03#ibcon#about to read 3, iclass 15, count 2 2006.231.07:42:00.06#ibcon#read 3, iclass 15, count 2 2006.231.07:42:00.06#ibcon#about to read 4, iclass 15, count 2 2006.231.07:42:00.06#ibcon#read 4, iclass 15, count 2 2006.231.07:42:00.06#ibcon#about to read 5, iclass 15, count 2 2006.231.07:42:00.06#ibcon#read 5, iclass 15, count 2 2006.231.07:42:00.06#ibcon#about to read 6, iclass 15, count 2 2006.231.07:42:00.06#ibcon#read 6, iclass 15, count 2 2006.231.07:42:00.06#ibcon#end of sib2, iclass 15, count 2 2006.231.07:42:00.06#ibcon#*after write, iclass 15, count 2 2006.231.07:42:00.06#ibcon#*before return 0, iclass 15, count 2 2006.231.07:42:00.06#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:42:00.06#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:42:00.06#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.07:42:00.06#ibcon#ireg 7 cls_cnt 0 2006.231.07:42:00.06#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:42:00.18#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:42:00.18#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:42:00.18#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:42:00.18#ibcon#first serial, iclass 15, count 0 2006.231.07:42:00.18#ibcon#enter sib2, iclass 15, count 0 2006.231.07:42:00.18#ibcon#flushed, iclass 15, count 0 2006.231.07:42:00.18#ibcon#about to write, iclass 15, count 0 2006.231.07:42:00.18#ibcon#wrote, iclass 15, count 0 2006.231.07:42:00.18#ibcon#about to read 3, iclass 15, count 0 2006.231.07:42:00.20#ibcon#read 3, iclass 15, count 0 2006.231.07:42:00.20#ibcon#about to read 4, iclass 15, count 0 2006.231.07:42:00.20#ibcon#read 4, iclass 15, count 0 2006.231.07:42:00.20#ibcon#about to read 5, iclass 15, count 0 2006.231.07:42:00.20#ibcon#read 5, iclass 15, count 0 2006.231.07:42:00.20#ibcon#about to read 6, iclass 15, count 0 2006.231.07:42:00.20#ibcon#read 6, iclass 15, count 0 2006.231.07:42:00.20#ibcon#end of sib2, iclass 15, count 0 2006.231.07:42:00.20#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:42:00.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:42:00.20#ibcon#[25=USB\r\n] 2006.231.07:42:00.20#ibcon#*before write, iclass 15, count 0 2006.231.07:42:00.20#ibcon#enter sib2, iclass 15, count 0 2006.231.07:42:00.20#ibcon#flushed, iclass 15, count 0 2006.231.07:42:00.20#ibcon#about to write, iclass 15, count 0 2006.231.07:42:00.20#ibcon#wrote, iclass 15, count 0 2006.231.07:42:00.20#ibcon#about to read 3, iclass 15, count 0 2006.231.07:42:00.23#ibcon#read 3, iclass 15, count 0 2006.231.07:42:00.23#ibcon#about to read 4, iclass 15, count 0 2006.231.07:42:00.23#ibcon#read 4, iclass 15, count 0 2006.231.07:42:00.23#ibcon#about to read 5, iclass 15, count 0 2006.231.07:42:00.23#ibcon#read 5, iclass 15, count 0 2006.231.07:42:00.23#ibcon#about to read 6, iclass 15, count 0 2006.231.07:42:00.23#ibcon#read 6, iclass 15, count 0 2006.231.07:42:00.23#ibcon#end of sib2, iclass 15, count 0 2006.231.07:42:00.23#ibcon#*after write, iclass 15, count 0 2006.231.07:42:00.23#ibcon#*before return 0, iclass 15, count 0 2006.231.07:42:00.23#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:42:00.23#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:42:00.23#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:42:00.23#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:42:00.23$vc4f8/valo=8,852.99 2006.231.07:42:00.23#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.07:42:00.23#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.07:42:00.23#ibcon#ireg 17 cls_cnt 0 2006.231.07:42:00.23#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:42:00.23#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:42:00.23#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:42:00.23#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:42:00.23#ibcon#first serial, iclass 17, count 0 2006.231.07:42:00.23#ibcon#enter sib2, iclass 17, count 0 2006.231.07:42:00.23#ibcon#flushed, iclass 17, count 0 2006.231.07:42:00.23#ibcon#about to write, iclass 17, count 0 2006.231.07:42:00.23#ibcon#wrote, iclass 17, count 0 2006.231.07:42:00.23#ibcon#about to read 3, iclass 17, count 0 2006.231.07:42:00.25#ibcon#read 3, iclass 17, count 0 2006.231.07:42:00.25#ibcon#about to read 4, iclass 17, count 0 2006.231.07:42:00.25#ibcon#read 4, iclass 17, count 0 2006.231.07:42:00.25#ibcon#about to read 5, iclass 17, count 0 2006.231.07:42:00.25#ibcon#read 5, iclass 17, count 0 2006.231.07:42:00.25#ibcon#about to read 6, iclass 17, count 0 2006.231.07:42:00.25#ibcon#read 6, iclass 17, count 0 2006.231.07:42:00.25#ibcon#end of sib2, iclass 17, count 0 2006.231.07:42:00.25#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:42:00.25#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:42:00.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:42:00.25#ibcon#*before write, iclass 17, count 0 2006.231.07:42:00.25#ibcon#enter sib2, iclass 17, count 0 2006.231.07:42:00.25#ibcon#flushed, iclass 17, count 0 2006.231.07:42:00.25#ibcon#about to write, iclass 17, count 0 2006.231.07:42:00.25#ibcon#wrote, iclass 17, count 0 2006.231.07:42:00.25#ibcon#about to read 3, iclass 17, count 0 2006.231.07:42:00.29#ibcon#read 3, iclass 17, count 0 2006.231.07:42:00.29#ibcon#about to read 4, iclass 17, count 0 2006.231.07:42:00.29#ibcon#read 4, iclass 17, count 0 2006.231.07:42:00.29#ibcon#about to read 5, iclass 17, count 0 2006.231.07:42:00.29#ibcon#read 5, iclass 17, count 0 2006.231.07:42:00.29#ibcon#about to read 6, iclass 17, count 0 2006.231.07:42:00.29#ibcon#read 6, iclass 17, count 0 2006.231.07:42:00.29#ibcon#end of sib2, iclass 17, count 0 2006.231.07:42:00.29#ibcon#*after write, iclass 17, count 0 2006.231.07:42:00.29#ibcon#*before return 0, iclass 17, count 0 2006.231.07:42:00.29#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:42:00.29#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:42:00.29#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:42:00.29#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:42:00.29$vc4f8/va=8,6 2006.231.07:42:00.29#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.231.07:42:00.29#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.231.07:42:00.29#ibcon#ireg 11 cls_cnt 2 2006.231.07:42:00.29#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:42:00.35#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:42:00.35#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:42:00.35#ibcon#enter wrdev, iclass 19, count 2 2006.231.07:42:00.35#ibcon#first serial, iclass 19, count 2 2006.231.07:42:00.35#ibcon#enter sib2, iclass 19, count 2 2006.231.07:42:00.35#ibcon#flushed, iclass 19, count 2 2006.231.07:42:00.35#ibcon#about to write, iclass 19, count 2 2006.231.07:42:00.35#ibcon#wrote, iclass 19, count 2 2006.231.07:42:00.35#ibcon#about to read 3, iclass 19, count 2 2006.231.07:42:00.37#ibcon#read 3, iclass 19, count 2 2006.231.07:42:00.37#ibcon#about to read 4, iclass 19, count 2 2006.231.07:42:00.37#ibcon#read 4, iclass 19, count 2 2006.231.07:42:00.37#ibcon#about to read 5, iclass 19, count 2 2006.231.07:42:00.37#ibcon#read 5, iclass 19, count 2 2006.231.07:42:00.37#ibcon#about to read 6, iclass 19, count 2 2006.231.07:42:00.37#ibcon#read 6, iclass 19, count 2 2006.231.07:42:00.37#ibcon#end of sib2, iclass 19, count 2 2006.231.07:42:00.37#ibcon#*mode == 0, iclass 19, count 2 2006.231.07:42:00.37#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.231.07:42:00.37#ibcon#[25=AT08-06\r\n] 2006.231.07:42:00.37#ibcon#*before write, iclass 19, count 2 2006.231.07:42:00.37#ibcon#enter sib2, iclass 19, count 2 2006.231.07:42:00.37#ibcon#flushed, iclass 19, count 2 2006.231.07:42:00.37#ibcon#about to write, iclass 19, count 2 2006.231.07:42:00.37#ibcon#wrote, iclass 19, count 2 2006.231.07:42:00.37#ibcon#about to read 3, iclass 19, count 2 2006.231.07:42:00.40#ibcon#read 3, iclass 19, count 2 2006.231.07:42:00.40#ibcon#about to read 4, iclass 19, count 2 2006.231.07:42:00.40#ibcon#read 4, iclass 19, count 2 2006.231.07:42:00.40#ibcon#about to read 5, iclass 19, count 2 2006.231.07:42:00.40#ibcon#read 5, iclass 19, count 2 2006.231.07:42:00.40#ibcon#about to read 6, iclass 19, count 2 2006.231.07:42:00.40#ibcon#read 6, iclass 19, count 2 2006.231.07:42:00.40#ibcon#end of sib2, iclass 19, count 2 2006.231.07:42:00.40#ibcon#*after write, iclass 19, count 2 2006.231.07:42:00.40#ibcon#*before return 0, iclass 19, count 2 2006.231.07:42:00.40#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:42:00.40#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:42:00.40#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.231.07:42:00.40#ibcon#ireg 7 cls_cnt 0 2006.231.07:42:00.40#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:42:00.52#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:42:00.52#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:42:00.52#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:42:00.52#ibcon#first serial, iclass 19, count 0 2006.231.07:42:00.52#ibcon#enter sib2, iclass 19, count 0 2006.231.07:42:00.52#ibcon#flushed, iclass 19, count 0 2006.231.07:42:00.52#ibcon#about to write, iclass 19, count 0 2006.231.07:42:00.52#ibcon#wrote, iclass 19, count 0 2006.231.07:42:00.52#ibcon#about to read 3, iclass 19, count 0 2006.231.07:42:00.54#ibcon#read 3, iclass 19, count 0 2006.231.07:42:00.54#ibcon#about to read 4, iclass 19, count 0 2006.231.07:42:00.54#ibcon#read 4, iclass 19, count 0 2006.231.07:42:00.54#ibcon#about to read 5, iclass 19, count 0 2006.231.07:42:00.54#ibcon#read 5, iclass 19, count 0 2006.231.07:42:00.54#ibcon#about to read 6, iclass 19, count 0 2006.231.07:42:00.54#ibcon#read 6, iclass 19, count 0 2006.231.07:42:00.54#ibcon#end of sib2, iclass 19, count 0 2006.231.07:42:00.54#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:42:00.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:42:00.54#ibcon#[25=USB\r\n] 2006.231.07:42:00.54#ibcon#*before write, iclass 19, count 0 2006.231.07:42:00.54#ibcon#enter sib2, iclass 19, count 0 2006.231.07:42:00.54#ibcon#flushed, iclass 19, count 0 2006.231.07:42:00.54#ibcon#about to write, iclass 19, count 0 2006.231.07:42:00.54#ibcon#wrote, iclass 19, count 0 2006.231.07:42:00.54#ibcon#about to read 3, iclass 19, count 0 2006.231.07:42:00.57#ibcon#read 3, iclass 19, count 0 2006.231.07:42:00.57#ibcon#about to read 4, iclass 19, count 0 2006.231.07:42:00.57#ibcon#read 4, iclass 19, count 0 2006.231.07:42:00.57#ibcon#about to read 5, iclass 19, count 0 2006.231.07:42:00.57#ibcon#read 5, iclass 19, count 0 2006.231.07:42:00.57#ibcon#about to read 6, iclass 19, count 0 2006.231.07:42:00.57#ibcon#read 6, iclass 19, count 0 2006.231.07:42:00.57#ibcon#end of sib2, iclass 19, count 0 2006.231.07:42:00.57#ibcon#*after write, iclass 19, count 0 2006.231.07:42:00.57#ibcon#*before return 0, iclass 19, count 0 2006.231.07:42:00.57#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:42:00.57#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:42:00.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:42:00.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:42:00.57$vc4f8/vblo=1,632.99 2006.231.07:42:00.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.07:42:00.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.07:42:00.57#ibcon#ireg 17 cls_cnt 0 2006.231.07:42:00.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:42:00.57#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:42:00.57#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:42:00.57#ibcon#enter wrdev, iclass 21, count 0 2006.231.07:42:00.57#ibcon#first serial, iclass 21, count 0 2006.231.07:42:00.57#ibcon#enter sib2, iclass 21, count 0 2006.231.07:42:00.57#ibcon#flushed, iclass 21, count 0 2006.231.07:42:00.57#ibcon#about to write, iclass 21, count 0 2006.231.07:42:00.57#ibcon#wrote, iclass 21, count 0 2006.231.07:42:00.57#ibcon#about to read 3, iclass 21, count 0 2006.231.07:42:00.59#ibcon#read 3, iclass 21, count 0 2006.231.07:42:00.59#ibcon#about to read 4, iclass 21, count 0 2006.231.07:42:00.59#ibcon#read 4, iclass 21, count 0 2006.231.07:42:00.59#ibcon#about to read 5, iclass 21, count 0 2006.231.07:42:00.59#ibcon#read 5, iclass 21, count 0 2006.231.07:42:00.59#ibcon#about to read 6, iclass 21, count 0 2006.231.07:42:00.59#ibcon#read 6, iclass 21, count 0 2006.231.07:42:00.59#ibcon#end of sib2, iclass 21, count 0 2006.231.07:42:00.59#ibcon#*mode == 0, iclass 21, count 0 2006.231.07:42:00.59#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.07:42:00.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:42:00.59#ibcon#*before write, iclass 21, count 0 2006.231.07:42:00.59#ibcon#enter sib2, iclass 21, count 0 2006.231.07:42:00.59#ibcon#flushed, iclass 21, count 0 2006.231.07:42:00.59#ibcon#about to write, iclass 21, count 0 2006.231.07:42:00.59#ibcon#wrote, iclass 21, count 0 2006.231.07:42:00.59#ibcon#about to read 3, iclass 21, count 0 2006.231.07:42:00.63#ibcon#read 3, iclass 21, count 0 2006.231.07:42:00.63#ibcon#about to read 4, iclass 21, count 0 2006.231.07:42:00.63#ibcon#read 4, iclass 21, count 0 2006.231.07:42:00.63#ibcon#about to read 5, iclass 21, count 0 2006.231.07:42:00.63#ibcon#read 5, iclass 21, count 0 2006.231.07:42:00.63#ibcon#about to read 6, iclass 21, count 0 2006.231.07:42:00.63#ibcon#read 6, iclass 21, count 0 2006.231.07:42:00.63#ibcon#end of sib2, iclass 21, count 0 2006.231.07:42:00.63#ibcon#*after write, iclass 21, count 0 2006.231.07:42:00.63#ibcon#*before return 0, iclass 21, count 0 2006.231.07:42:00.63#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:42:00.63#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:42:00.63#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.07:42:00.63#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.07:42:00.63$vc4f8/vb=1,4 2006.231.07:42:00.63#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.231.07:42:00.63#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.231.07:42:00.63#ibcon#ireg 11 cls_cnt 2 2006.231.07:42:00.63#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:42:00.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:42:00.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:42:00.63#ibcon#enter wrdev, iclass 23, count 2 2006.231.07:42:00.63#ibcon#first serial, iclass 23, count 2 2006.231.07:42:00.63#ibcon#enter sib2, iclass 23, count 2 2006.231.07:42:00.63#ibcon#flushed, iclass 23, count 2 2006.231.07:42:00.63#ibcon#about to write, iclass 23, count 2 2006.231.07:42:00.63#ibcon#wrote, iclass 23, count 2 2006.231.07:42:00.63#ibcon#about to read 3, iclass 23, count 2 2006.231.07:42:00.65#ibcon#read 3, iclass 23, count 2 2006.231.07:42:00.65#ibcon#about to read 4, iclass 23, count 2 2006.231.07:42:00.65#ibcon#read 4, iclass 23, count 2 2006.231.07:42:00.65#ibcon#about to read 5, iclass 23, count 2 2006.231.07:42:00.65#ibcon#read 5, iclass 23, count 2 2006.231.07:42:00.65#ibcon#about to read 6, iclass 23, count 2 2006.231.07:42:00.65#ibcon#read 6, iclass 23, count 2 2006.231.07:42:00.65#ibcon#end of sib2, iclass 23, count 2 2006.231.07:42:00.65#ibcon#*mode == 0, iclass 23, count 2 2006.231.07:42:00.65#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.231.07:42:00.65#ibcon#[27=AT01-04\r\n] 2006.231.07:42:00.65#ibcon#*before write, iclass 23, count 2 2006.231.07:42:00.65#ibcon#enter sib2, iclass 23, count 2 2006.231.07:42:00.65#ibcon#flushed, iclass 23, count 2 2006.231.07:42:00.65#ibcon#about to write, iclass 23, count 2 2006.231.07:42:00.65#ibcon#wrote, iclass 23, count 2 2006.231.07:42:00.65#ibcon#about to read 3, iclass 23, count 2 2006.231.07:42:00.68#ibcon#read 3, iclass 23, count 2 2006.231.07:42:00.68#ibcon#about to read 4, iclass 23, count 2 2006.231.07:42:00.68#ibcon#read 4, iclass 23, count 2 2006.231.07:42:00.68#ibcon#about to read 5, iclass 23, count 2 2006.231.07:42:00.68#ibcon#read 5, iclass 23, count 2 2006.231.07:42:00.68#ibcon#about to read 6, iclass 23, count 2 2006.231.07:42:00.68#ibcon#read 6, iclass 23, count 2 2006.231.07:42:00.68#ibcon#end of sib2, iclass 23, count 2 2006.231.07:42:00.68#ibcon#*after write, iclass 23, count 2 2006.231.07:42:00.68#ibcon#*before return 0, iclass 23, count 2 2006.231.07:42:00.68#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:42:00.68#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:42:00.68#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.231.07:42:00.68#ibcon#ireg 7 cls_cnt 0 2006.231.07:42:00.68#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:42:00.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:42:00.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:42:00.80#ibcon#enter wrdev, iclass 23, count 0 2006.231.07:42:00.80#ibcon#first serial, iclass 23, count 0 2006.231.07:42:00.80#ibcon#enter sib2, iclass 23, count 0 2006.231.07:42:00.80#ibcon#flushed, iclass 23, count 0 2006.231.07:42:00.80#ibcon#about to write, iclass 23, count 0 2006.231.07:42:00.80#ibcon#wrote, iclass 23, count 0 2006.231.07:42:00.80#ibcon#about to read 3, iclass 23, count 0 2006.231.07:42:00.82#ibcon#read 3, iclass 23, count 0 2006.231.07:42:00.82#ibcon#about to read 4, iclass 23, count 0 2006.231.07:42:00.82#ibcon#read 4, iclass 23, count 0 2006.231.07:42:00.82#ibcon#about to read 5, iclass 23, count 0 2006.231.07:42:00.82#ibcon#read 5, iclass 23, count 0 2006.231.07:42:00.82#ibcon#about to read 6, iclass 23, count 0 2006.231.07:42:00.82#ibcon#read 6, iclass 23, count 0 2006.231.07:42:00.82#ibcon#end of sib2, iclass 23, count 0 2006.231.07:42:00.82#ibcon#*mode == 0, iclass 23, count 0 2006.231.07:42:00.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.07:42:00.82#ibcon#[27=USB\r\n] 2006.231.07:42:00.82#ibcon#*before write, iclass 23, count 0 2006.231.07:42:00.82#ibcon#enter sib2, iclass 23, count 0 2006.231.07:42:00.82#ibcon#flushed, iclass 23, count 0 2006.231.07:42:00.82#ibcon#about to write, iclass 23, count 0 2006.231.07:42:00.82#ibcon#wrote, iclass 23, count 0 2006.231.07:42:00.82#ibcon#about to read 3, iclass 23, count 0 2006.231.07:42:00.85#ibcon#read 3, iclass 23, count 0 2006.231.07:42:00.85#ibcon#about to read 4, iclass 23, count 0 2006.231.07:42:00.85#ibcon#read 4, iclass 23, count 0 2006.231.07:42:00.85#ibcon#about to read 5, iclass 23, count 0 2006.231.07:42:00.85#ibcon#read 5, iclass 23, count 0 2006.231.07:42:00.85#ibcon#about to read 6, iclass 23, count 0 2006.231.07:42:00.85#ibcon#read 6, iclass 23, count 0 2006.231.07:42:00.85#ibcon#end of sib2, iclass 23, count 0 2006.231.07:42:00.85#ibcon#*after write, iclass 23, count 0 2006.231.07:42:00.85#ibcon#*before return 0, iclass 23, count 0 2006.231.07:42:00.85#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:42:00.85#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:42:00.85#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.07:42:00.85#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.07:42:00.85$vc4f8/vblo=2,640.99 2006.231.07:42:00.85#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.231.07:42:00.85#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.231.07:42:00.85#ibcon#ireg 17 cls_cnt 0 2006.231.07:42:00.85#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:42:00.85#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:42:00.85#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:42:00.85#ibcon#enter wrdev, iclass 25, count 0 2006.231.07:42:00.85#ibcon#first serial, iclass 25, count 0 2006.231.07:42:00.85#ibcon#enter sib2, iclass 25, count 0 2006.231.07:42:00.85#ibcon#flushed, iclass 25, count 0 2006.231.07:42:00.85#ibcon#about to write, iclass 25, count 0 2006.231.07:42:00.85#ibcon#wrote, iclass 25, count 0 2006.231.07:42:00.85#ibcon#about to read 3, iclass 25, count 0 2006.231.07:42:00.87#ibcon#read 3, iclass 25, count 0 2006.231.07:42:00.87#ibcon#about to read 4, iclass 25, count 0 2006.231.07:42:00.87#ibcon#read 4, iclass 25, count 0 2006.231.07:42:00.87#ibcon#about to read 5, iclass 25, count 0 2006.231.07:42:00.87#ibcon#read 5, iclass 25, count 0 2006.231.07:42:00.87#ibcon#about to read 6, iclass 25, count 0 2006.231.07:42:00.87#ibcon#read 6, iclass 25, count 0 2006.231.07:42:00.87#ibcon#end of sib2, iclass 25, count 0 2006.231.07:42:00.87#ibcon#*mode == 0, iclass 25, count 0 2006.231.07:42:00.87#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.07:42:00.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:42:00.87#ibcon#*before write, iclass 25, count 0 2006.231.07:42:00.87#ibcon#enter sib2, iclass 25, count 0 2006.231.07:42:00.87#ibcon#flushed, iclass 25, count 0 2006.231.07:42:00.87#ibcon#about to write, iclass 25, count 0 2006.231.07:42:00.87#ibcon#wrote, iclass 25, count 0 2006.231.07:42:00.87#ibcon#about to read 3, iclass 25, count 0 2006.231.07:42:00.90#abcon#<5=/07 2.8 7.2 30.65 831004.4\r\n> 2006.231.07:42:00.91#ibcon#read 3, iclass 25, count 0 2006.231.07:42:00.91#ibcon#about to read 4, iclass 25, count 0 2006.231.07:42:00.91#ibcon#read 4, iclass 25, count 0 2006.231.07:42:00.91#ibcon#about to read 5, iclass 25, count 0 2006.231.07:42:00.91#ibcon#read 5, iclass 25, count 0 2006.231.07:42:00.91#ibcon#about to read 6, iclass 25, count 0 2006.231.07:42:00.91#ibcon#read 6, iclass 25, count 0 2006.231.07:42:00.91#ibcon#end of sib2, iclass 25, count 0 2006.231.07:42:00.91#ibcon#*after write, iclass 25, count 0 2006.231.07:42:00.91#ibcon#*before return 0, iclass 25, count 0 2006.231.07:42:00.91#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:42:00.91#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:42:00.91#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.07:42:00.91#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.07:42:00.91$vc4f8/vb=2,4 2006.231.07:42:00.91#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.07:42:00.91#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.07:42:00.91#ibcon#ireg 11 cls_cnt 2 2006.231.07:42:00.91#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:42:00.92#abcon#{5=INTERFACE CLEAR} 2006.231.07:42:00.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:42:00.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:42:00.97#ibcon#enter wrdev, iclass 30, count 2 2006.231.07:42:00.97#ibcon#first serial, iclass 30, count 2 2006.231.07:42:00.97#ibcon#enter sib2, iclass 30, count 2 2006.231.07:42:00.97#ibcon#flushed, iclass 30, count 2 2006.231.07:42:00.97#ibcon#about to write, iclass 30, count 2 2006.231.07:42:00.97#ibcon#wrote, iclass 30, count 2 2006.231.07:42:00.97#ibcon#about to read 3, iclass 30, count 2 2006.231.07:42:00.98#abcon#[5=S1D000X0/0*\r\n] 2006.231.07:42:00.99#ibcon#read 3, iclass 30, count 2 2006.231.07:42:00.99#ibcon#about to read 4, iclass 30, count 2 2006.231.07:42:00.99#ibcon#read 4, iclass 30, count 2 2006.231.07:42:00.99#ibcon#about to read 5, iclass 30, count 2 2006.231.07:42:00.99#ibcon#read 5, iclass 30, count 2 2006.231.07:42:00.99#ibcon#about to read 6, iclass 30, count 2 2006.231.07:42:00.99#ibcon#read 6, iclass 30, count 2 2006.231.07:42:00.99#ibcon#end of sib2, iclass 30, count 2 2006.231.07:42:00.99#ibcon#*mode == 0, iclass 30, count 2 2006.231.07:42:00.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.07:42:00.99#ibcon#[27=AT02-04\r\n] 2006.231.07:42:00.99#ibcon#*before write, iclass 30, count 2 2006.231.07:42:00.99#ibcon#enter sib2, iclass 30, count 2 2006.231.07:42:00.99#ibcon#flushed, iclass 30, count 2 2006.231.07:42:00.99#ibcon#about to write, iclass 30, count 2 2006.231.07:42:00.99#ibcon#wrote, iclass 30, count 2 2006.231.07:42:00.99#ibcon#about to read 3, iclass 30, count 2 2006.231.07:42:01.02#ibcon#read 3, iclass 30, count 2 2006.231.07:42:01.02#ibcon#about to read 4, iclass 30, count 2 2006.231.07:42:01.02#ibcon#read 4, iclass 30, count 2 2006.231.07:42:01.02#ibcon#about to read 5, iclass 30, count 2 2006.231.07:42:01.02#ibcon#read 5, iclass 30, count 2 2006.231.07:42:01.02#ibcon#about to read 6, iclass 30, count 2 2006.231.07:42:01.02#ibcon#read 6, iclass 30, count 2 2006.231.07:42:01.02#ibcon#end of sib2, iclass 30, count 2 2006.231.07:42:01.02#ibcon#*after write, iclass 30, count 2 2006.231.07:42:01.02#ibcon#*before return 0, iclass 30, count 2 2006.231.07:42:01.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:42:01.02#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:42:01.02#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.07:42:01.02#ibcon#ireg 7 cls_cnt 0 2006.231.07:42:01.02#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:42:01.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:42:01.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:42:01.14#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:42:01.14#ibcon#first serial, iclass 30, count 0 2006.231.07:42:01.14#ibcon#enter sib2, iclass 30, count 0 2006.231.07:42:01.14#ibcon#flushed, iclass 30, count 0 2006.231.07:42:01.14#ibcon#about to write, iclass 30, count 0 2006.231.07:42:01.14#ibcon#wrote, iclass 30, count 0 2006.231.07:42:01.14#ibcon#about to read 3, iclass 30, count 0 2006.231.07:42:01.16#ibcon#read 3, iclass 30, count 0 2006.231.07:42:01.16#ibcon#about to read 4, iclass 30, count 0 2006.231.07:42:01.16#ibcon#read 4, iclass 30, count 0 2006.231.07:42:01.16#ibcon#about to read 5, iclass 30, count 0 2006.231.07:42:01.16#ibcon#read 5, iclass 30, count 0 2006.231.07:42:01.16#ibcon#about to read 6, iclass 30, count 0 2006.231.07:42:01.16#ibcon#read 6, iclass 30, count 0 2006.231.07:42:01.16#ibcon#end of sib2, iclass 30, count 0 2006.231.07:42:01.16#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:42:01.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:42:01.16#ibcon#[27=USB\r\n] 2006.231.07:42:01.16#ibcon#*before write, iclass 30, count 0 2006.231.07:42:01.16#ibcon#enter sib2, iclass 30, count 0 2006.231.07:42:01.16#ibcon#flushed, iclass 30, count 0 2006.231.07:42:01.16#ibcon#about to write, iclass 30, count 0 2006.231.07:42:01.16#ibcon#wrote, iclass 30, count 0 2006.231.07:42:01.16#ibcon#about to read 3, iclass 30, count 0 2006.231.07:42:01.19#ibcon#read 3, iclass 30, count 0 2006.231.07:42:01.19#ibcon#about to read 4, iclass 30, count 0 2006.231.07:42:01.19#ibcon#read 4, iclass 30, count 0 2006.231.07:42:01.19#ibcon#about to read 5, iclass 30, count 0 2006.231.07:42:01.19#ibcon#read 5, iclass 30, count 0 2006.231.07:42:01.19#ibcon#about to read 6, iclass 30, count 0 2006.231.07:42:01.19#ibcon#read 6, iclass 30, count 0 2006.231.07:42:01.19#ibcon#end of sib2, iclass 30, count 0 2006.231.07:42:01.19#ibcon#*after write, iclass 30, count 0 2006.231.07:42:01.19#ibcon#*before return 0, iclass 30, count 0 2006.231.07:42:01.19#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:42:01.19#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:42:01.19#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:42:01.19#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:42:01.19$vc4f8/vblo=3,656.99 2006.231.07:42:01.19#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.07:42:01.19#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.07:42:01.19#ibcon#ireg 17 cls_cnt 0 2006.231.07:42:01.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:42:01.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:42:01.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:42:01.19#ibcon#enter wrdev, iclass 33, count 0 2006.231.07:42:01.19#ibcon#first serial, iclass 33, count 0 2006.231.07:42:01.19#ibcon#enter sib2, iclass 33, count 0 2006.231.07:42:01.19#ibcon#flushed, iclass 33, count 0 2006.231.07:42:01.19#ibcon#about to write, iclass 33, count 0 2006.231.07:42:01.19#ibcon#wrote, iclass 33, count 0 2006.231.07:42:01.19#ibcon#about to read 3, iclass 33, count 0 2006.231.07:42:01.21#ibcon#read 3, iclass 33, count 0 2006.231.07:42:01.21#ibcon#about to read 4, iclass 33, count 0 2006.231.07:42:01.21#ibcon#read 4, iclass 33, count 0 2006.231.07:42:01.21#ibcon#about to read 5, iclass 33, count 0 2006.231.07:42:01.21#ibcon#read 5, iclass 33, count 0 2006.231.07:42:01.21#ibcon#about to read 6, iclass 33, count 0 2006.231.07:42:01.21#ibcon#read 6, iclass 33, count 0 2006.231.07:42:01.21#ibcon#end of sib2, iclass 33, count 0 2006.231.07:42:01.21#ibcon#*mode == 0, iclass 33, count 0 2006.231.07:42:01.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.07:42:01.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:42:01.21#ibcon#*before write, iclass 33, count 0 2006.231.07:42:01.21#ibcon#enter sib2, iclass 33, count 0 2006.231.07:42:01.21#ibcon#flushed, iclass 33, count 0 2006.231.07:42:01.21#ibcon#about to write, iclass 33, count 0 2006.231.07:42:01.21#ibcon#wrote, iclass 33, count 0 2006.231.07:42:01.21#ibcon#about to read 3, iclass 33, count 0 2006.231.07:42:01.25#ibcon#read 3, iclass 33, count 0 2006.231.07:42:01.25#ibcon#about to read 4, iclass 33, count 0 2006.231.07:42:01.25#ibcon#read 4, iclass 33, count 0 2006.231.07:42:01.25#ibcon#about to read 5, iclass 33, count 0 2006.231.07:42:01.25#ibcon#read 5, iclass 33, count 0 2006.231.07:42:01.25#ibcon#about to read 6, iclass 33, count 0 2006.231.07:42:01.25#ibcon#read 6, iclass 33, count 0 2006.231.07:42:01.25#ibcon#end of sib2, iclass 33, count 0 2006.231.07:42:01.25#ibcon#*after write, iclass 33, count 0 2006.231.07:42:01.25#ibcon#*before return 0, iclass 33, count 0 2006.231.07:42:01.25#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:42:01.25#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:42:01.25#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.07:42:01.25#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.07:42:01.25$vc4f8/vb=3,4 2006.231.07:42:01.25#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.07:42:01.25#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.07:42:01.25#ibcon#ireg 11 cls_cnt 2 2006.231.07:42:01.25#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:42:01.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:42:01.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:42:01.31#ibcon#enter wrdev, iclass 35, count 2 2006.231.07:42:01.31#ibcon#first serial, iclass 35, count 2 2006.231.07:42:01.31#ibcon#enter sib2, iclass 35, count 2 2006.231.07:42:01.31#ibcon#flushed, iclass 35, count 2 2006.231.07:42:01.31#ibcon#about to write, iclass 35, count 2 2006.231.07:42:01.31#ibcon#wrote, iclass 35, count 2 2006.231.07:42:01.31#ibcon#about to read 3, iclass 35, count 2 2006.231.07:42:01.34#ibcon#read 3, iclass 35, count 2 2006.231.07:42:01.34#ibcon#about to read 4, iclass 35, count 2 2006.231.07:42:01.34#ibcon#read 4, iclass 35, count 2 2006.231.07:42:01.34#ibcon#about to read 5, iclass 35, count 2 2006.231.07:42:01.34#ibcon#read 5, iclass 35, count 2 2006.231.07:42:01.34#ibcon#about to read 6, iclass 35, count 2 2006.231.07:42:01.34#ibcon#read 6, iclass 35, count 2 2006.231.07:42:01.34#ibcon#end of sib2, iclass 35, count 2 2006.231.07:42:01.34#ibcon#*mode == 0, iclass 35, count 2 2006.231.07:42:01.34#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.07:42:01.34#ibcon#[27=AT03-04\r\n] 2006.231.07:42:01.34#ibcon#*before write, iclass 35, count 2 2006.231.07:42:01.34#ibcon#enter sib2, iclass 35, count 2 2006.231.07:42:01.34#ibcon#flushed, iclass 35, count 2 2006.231.07:42:01.34#ibcon#about to write, iclass 35, count 2 2006.231.07:42:01.34#ibcon#wrote, iclass 35, count 2 2006.231.07:42:01.34#ibcon#about to read 3, iclass 35, count 2 2006.231.07:42:01.37#ibcon#read 3, iclass 35, count 2 2006.231.07:42:01.37#ibcon#about to read 4, iclass 35, count 2 2006.231.07:42:01.37#ibcon#read 4, iclass 35, count 2 2006.231.07:42:01.37#ibcon#about to read 5, iclass 35, count 2 2006.231.07:42:01.37#ibcon#read 5, iclass 35, count 2 2006.231.07:42:01.37#ibcon#about to read 6, iclass 35, count 2 2006.231.07:42:01.37#ibcon#read 6, iclass 35, count 2 2006.231.07:42:01.37#ibcon#end of sib2, iclass 35, count 2 2006.231.07:42:01.37#ibcon#*after write, iclass 35, count 2 2006.231.07:42:01.37#ibcon#*before return 0, iclass 35, count 2 2006.231.07:42:01.37#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:42:01.37#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:42:01.37#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.07:42:01.37#ibcon#ireg 7 cls_cnt 0 2006.231.07:42:01.37#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:42:01.49#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:42:01.49#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:42:01.49#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:42:01.49#ibcon#first serial, iclass 35, count 0 2006.231.07:42:01.49#ibcon#enter sib2, iclass 35, count 0 2006.231.07:42:01.49#ibcon#flushed, iclass 35, count 0 2006.231.07:42:01.49#ibcon#about to write, iclass 35, count 0 2006.231.07:42:01.49#ibcon#wrote, iclass 35, count 0 2006.231.07:42:01.49#ibcon#about to read 3, iclass 35, count 0 2006.231.07:42:01.51#ibcon#read 3, iclass 35, count 0 2006.231.07:42:01.51#ibcon#about to read 4, iclass 35, count 0 2006.231.07:42:01.51#ibcon#read 4, iclass 35, count 0 2006.231.07:42:01.51#ibcon#about to read 5, iclass 35, count 0 2006.231.07:42:01.51#ibcon#read 5, iclass 35, count 0 2006.231.07:42:01.51#ibcon#about to read 6, iclass 35, count 0 2006.231.07:42:01.51#ibcon#read 6, iclass 35, count 0 2006.231.07:42:01.51#ibcon#end of sib2, iclass 35, count 0 2006.231.07:42:01.51#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:42:01.51#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:42:01.51#ibcon#[27=USB\r\n] 2006.231.07:42:01.51#ibcon#*before write, iclass 35, count 0 2006.231.07:42:01.51#ibcon#enter sib2, iclass 35, count 0 2006.231.07:42:01.51#ibcon#flushed, iclass 35, count 0 2006.231.07:42:01.51#ibcon#about to write, iclass 35, count 0 2006.231.07:42:01.51#ibcon#wrote, iclass 35, count 0 2006.231.07:42:01.51#ibcon#about to read 3, iclass 35, count 0 2006.231.07:42:01.54#ibcon#read 3, iclass 35, count 0 2006.231.07:42:01.54#ibcon#about to read 4, iclass 35, count 0 2006.231.07:42:01.54#ibcon#read 4, iclass 35, count 0 2006.231.07:42:01.54#ibcon#about to read 5, iclass 35, count 0 2006.231.07:42:01.54#ibcon#read 5, iclass 35, count 0 2006.231.07:42:01.54#ibcon#about to read 6, iclass 35, count 0 2006.231.07:42:01.54#ibcon#read 6, iclass 35, count 0 2006.231.07:42:01.54#ibcon#end of sib2, iclass 35, count 0 2006.231.07:42:01.54#ibcon#*after write, iclass 35, count 0 2006.231.07:42:01.54#ibcon#*before return 0, iclass 35, count 0 2006.231.07:42:01.54#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:42:01.54#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:42:01.54#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:42:01.54#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:42:01.54$vc4f8/vblo=4,712.99 2006.231.07:42:01.54#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.07:42:01.54#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.07:42:01.54#ibcon#ireg 17 cls_cnt 0 2006.231.07:42:01.54#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:42:01.54#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:42:01.54#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:42:01.54#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:42:01.54#ibcon#first serial, iclass 37, count 0 2006.231.07:42:01.54#ibcon#enter sib2, iclass 37, count 0 2006.231.07:42:01.54#ibcon#flushed, iclass 37, count 0 2006.231.07:42:01.54#ibcon#about to write, iclass 37, count 0 2006.231.07:42:01.54#ibcon#wrote, iclass 37, count 0 2006.231.07:42:01.54#ibcon#about to read 3, iclass 37, count 0 2006.231.07:42:01.56#ibcon#read 3, iclass 37, count 0 2006.231.07:42:01.56#ibcon#about to read 4, iclass 37, count 0 2006.231.07:42:01.56#ibcon#read 4, iclass 37, count 0 2006.231.07:42:01.56#ibcon#about to read 5, iclass 37, count 0 2006.231.07:42:01.56#ibcon#read 5, iclass 37, count 0 2006.231.07:42:01.56#ibcon#about to read 6, iclass 37, count 0 2006.231.07:42:01.56#ibcon#read 6, iclass 37, count 0 2006.231.07:42:01.56#ibcon#end of sib2, iclass 37, count 0 2006.231.07:42:01.56#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:42:01.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:42:01.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:42:01.56#ibcon#*before write, iclass 37, count 0 2006.231.07:42:01.56#ibcon#enter sib2, iclass 37, count 0 2006.231.07:42:01.56#ibcon#flushed, iclass 37, count 0 2006.231.07:42:01.56#ibcon#about to write, iclass 37, count 0 2006.231.07:42:01.56#ibcon#wrote, iclass 37, count 0 2006.231.07:42:01.56#ibcon#about to read 3, iclass 37, count 0 2006.231.07:42:01.60#ibcon#read 3, iclass 37, count 0 2006.231.07:42:01.60#ibcon#about to read 4, iclass 37, count 0 2006.231.07:42:01.60#ibcon#read 4, iclass 37, count 0 2006.231.07:42:01.60#ibcon#about to read 5, iclass 37, count 0 2006.231.07:42:01.60#ibcon#read 5, iclass 37, count 0 2006.231.07:42:01.60#ibcon#about to read 6, iclass 37, count 0 2006.231.07:42:01.60#ibcon#read 6, iclass 37, count 0 2006.231.07:42:01.60#ibcon#end of sib2, iclass 37, count 0 2006.231.07:42:01.60#ibcon#*after write, iclass 37, count 0 2006.231.07:42:01.60#ibcon#*before return 0, iclass 37, count 0 2006.231.07:42:01.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:42:01.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:42:01.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:42:01.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:42:01.60$vc4f8/vb=4,4 2006.231.07:42:01.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.07:42:01.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.07:42:01.60#ibcon#ireg 11 cls_cnt 2 2006.231.07:42:01.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:42:01.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:42:01.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:42:01.66#ibcon#enter wrdev, iclass 39, count 2 2006.231.07:42:01.66#ibcon#first serial, iclass 39, count 2 2006.231.07:42:01.66#ibcon#enter sib2, iclass 39, count 2 2006.231.07:42:01.66#ibcon#flushed, iclass 39, count 2 2006.231.07:42:01.66#ibcon#about to write, iclass 39, count 2 2006.231.07:42:01.66#ibcon#wrote, iclass 39, count 2 2006.231.07:42:01.66#ibcon#about to read 3, iclass 39, count 2 2006.231.07:42:01.68#ibcon#read 3, iclass 39, count 2 2006.231.07:42:01.68#ibcon#about to read 4, iclass 39, count 2 2006.231.07:42:01.68#ibcon#read 4, iclass 39, count 2 2006.231.07:42:01.68#ibcon#about to read 5, iclass 39, count 2 2006.231.07:42:01.68#ibcon#read 5, iclass 39, count 2 2006.231.07:42:01.68#ibcon#about to read 6, iclass 39, count 2 2006.231.07:42:01.68#ibcon#read 6, iclass 39, count 2 2006.231.07:42:01.68#ibcon#end of sib2, iclass 39, count 2 2006.231.07:42:01.68#ibcon#*mode == 0, iclass 39, count 2 2006.231.07:42:01.68#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.07:42:01.68#ibcon#[27=AT04-04\r\n] 2006.231.07:42:01.68#ibcon#*before write, iclass 39, count 2 2006.231.07:42:01.68#ibcon#enter sib2, iclass 39, count 2 2006.231.07:42:01.68#ibcon#flushed, iclass 39, count 2 2006.231.07:42:01.68#ibcon#about to write, iclass 39, count 2 2006.231.07:42:01.68#ibcon#wrote, iclass 39, count 2 2006.231.07:42:01.68#ibcon#about to read 3, iclass 39, count 2 2006.231.07:42:01.71#ibcon#read 3, iclass 39, count 2 2006.231.07:42:01.71#ibcon#about to read 4, iclass 39, count 2 2006.231.07:42:01.71#ibcon#read 4, iclass 39, count 2 2006.231.07:42:01.71#ibcon#about to read 5, iclass 39, count 2 2006.231.07:42:01.71#ibcon#read 5, iclass 39, count 2 2006.231.07:42:01.71#ibcon#about to read 6, iclass 39, count 2 2006.231.07:42:01.71#ibcon#read 6, iclass 39, count 2 2006.231.07:42:01.71#ibcon#end of sib2, iclass 39, count 2 2006.231.07:42:01.71#ibcon#*after write, iclass 39, count 2 2006.231.07:42:01.71#ibcon#*before return 0, iclass 39, count 2 2006.231.07:42:01.71#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:42:01.71#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:42:01.71#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.07:42:01.71#ibcon#ireg 7 cls_cnt 0 2006.231.07:42:01.71#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:42:01.83#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:42:01.83#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:42:01.83#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:42:01.83#ibcon#first serial, iclass 39, count 0 2006.231.07:42:01.83#ibcon#enter sib2, iclass 39, count 0 2006.231.07:42:01.83#ibcon#flushed, iclass 39, count 0 2006.231.07:42:01.83#ibcon#about to write, iclass 39, count 0 2006.231.07:42:01.83#ibcon#wrote, iclass 39, count 0 2006.231.07:42:01.83#ibcon#about to read 3, iclass 39, count 0 2006.231.07:42:01.85#ibcon#read 3, iclass 39, count 0 2006.231.07:42:01.85#ibcon#about to read 4, iclass 39, count 0 2006.231.07:42:01.85#ibcon#read 4, iclass 39, count 0 2006.231.07:42:01.85#ibcon#about to read 5, iclass 39, count 0 2006.231.07:42:01.85#ibcon#read 5, iclass 39, count 0 2006.231.07:42:01.85#ibcon#about to read 6, iclass 39, count 0 2006.231.07:42:01.85#ibcon#read 6, iclass 39, count 0 2006.231.07:42:01.85#ibcon#end of sib2, iclass 39, count 0 2006.231.07:42:01.85#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:42:01.85#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:42:01.85#ibcon#[27=USB\r\n] 2006.231.07:42:01.85#ibcon#*before write, iclass 39, count 0 2006.231.07:42:01.85#ibcon#enter sib2, iclass 39, count 0 2006.231.07:42:01.85#ibcon#flushed, iclass 39, count 0 2006.231.07:42:01.85#ibcon#about to write, iclass 39, count 0 2006.231.07:42:01.85#ibcon#wrote, iclass 39, count 0 2006.231.07:42:01.85#ibcon#about to read 3, iclass 39, count 0 2006.231.07:42:01.88#ibcon#read 3, iclass 39, count 0 2006.231.07:42:01.88#ibcon#about to read 4, iclass 39, count 0 2006.231.07:42:01.88#ibcon#read 4, iclass 39, count 0 2006.231.07:42:01.88#ibcon#about to read 5, iclass 39, count 0 2006.231.07:42:01.88#ibcon#read 5, iclass 39, count 0 2006.231.07:42:01.88#ibcon#about to read 6, iclass 39, count 0 2006.231.07:42:01.88#ibcon#read 6, iclass 39, count 0 2006.231.07:42:01.88#ibcon#end of sib2, iclass 39, count 0 2006.231.07:42:01.88#ibcon#*after write, iclass 39, count 0 2006.231.07:42:01.88#ibcon#*before return 0, iclass 39, count 0 2006.231.07:42:01.88#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:42:01.88#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:42:01.88#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:42:01.88#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:42:01.88$vc4f8/vblo=5,744.99 2006.231.07:42:01.88#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.07:42:01.88#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.07:42:01.88#ibcon#ireg 17 cls_cnt 0 2006.231.07:42:01.88#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:42:01.88#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:42:01.88#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:42:01.88#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:42:01.88#ibcon#first serial, iclass 3, count 0 2006.231.07:42:01.88#ibcon#enter sib2, iclass 3, count 0 2006.231.07:42:01.88#ibcon#flushed, iclass 3, count 0 2006.231.07:42:01.88#ibcon#about to write, iclass 3, count 0 2006.231.07:42:01.88#ibcon#wrote, iclass 3, count 0 2006.231.07:42:01.88#ibcon#about to read 3, iclass 3, count 0 2006.231.07:42:01.91#ibcon#read 3, iclass 3, count 0 2006.231.07:42:01.91#ibcon#about to read 4, iclass 3, count 0 2006.231.07:42:01.91#ibcon#read 4, iclass 3, count 0 2006.231.07:42:01.91#ibcon#about to read 5, iclass 3, count 0 2006.231.07:42:01.91#ibcon#read 5, iclass 3, count 0 2006.231.07:42:01.91#ibcon#about to read 6, iclass 3, count 0 2006.231.07:42:01.91#ibcon#read 6, iclass 3, count 0 2006.231.07:42:01.91#ibcon#end of sib2, iclass 3, count 0 2006.231.07:42:01.91#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:42:01.91#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:42:01.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:42:01.91#ibcon#*before write, iclass 3, count 0 2006.231.07:42:01.91#ibcon#enter sib2, iclass 3, count 0 2006.231.07:42:01.91#ibcon#flushed, iclass 3, count 0 2006.231.07:42:01.91#ibcon#about to write, iclass 3, count 0 2006.231.07:42:01.91#ibcon#wrote, iclass 3, count 0 2006.231.07:42:01.91#ibcon#about to read 3, iclass 3, count 0 2006.231.07:42:01.95#ibcon#read 3, iclass 3, count 0 2006.231.07:42:01.95#ibcon#about to read 4, iclass 3, count 0 2006.231.07:42:01.95#ibcon#read 4, iclass 3, count 0 2006.231.07:42:01.95#ibcon#about to read 5, iclass 3, count 0 2006.231.07:42:01.95#ibcon#read 5, iclass 3, count 0 2006.231.07:42:01.95#ibcon#about to read 6, iclass 3, count 0 2006.231.07:42:01.95#ibcon#read 6, iclass 3, count 0 2006.231.07:42:01.95#ibcon#end of sib2, iclass 3, count 0 2006.231.07:42:01.95#ibcon#*after write, iclass 3, count 0 2006.231.07:42:01.95#ibcon#*before return 0, iclass 3, count 0 2006.231.07:42:01.95#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:42:01.95#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:42:01.95#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:42:01.95#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:42:01.95$vc4f8/vb=5,3 2006.231.07:42:01.95#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.07:42:01.95#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.07:42:01.95#ibcon#ireg 11 cls_cnt 2 2006.231.07:42:01.95#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:42:02.00#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:42:02.00#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:42:02.00#ibcon#enter wrdev, iclass 5, count 2 2006.231.07:42:02.00#ibcon#first serial, iclass 5, count 2 2006.231.07:42:02.00#ibcon#enter sib2, iclass 5, count 2 2006.231.07:42:02.00#ibcon#flushed, iclass 5, count 2 2006.231.07:42:02.00#ibcon#about to write, iclass 5, count 2 2006.231.07:42:02.00#ibcon#wrote, iclass 5, count 2 2006.231.07:42:02.00#ibcon#about to read 3, iclass 5, count 2 2006.231.07:42:02.02#ibcon#read 3, iclass 5, count 2 2006.231.07:42:02.02#ibcon#about to read 4, iclass 5, count 2 2006.231.07:42:02.02#ibcon#read 4, iclass 5, count 2 2006.231.07:42:02.02#ibcon#about to read 5, iclass 5, count 2 2006.231.07:42:02.02#ibcon#read 5, iclass 5, count 2 2006.231.07:42:02.02#ibcon#about to read 6, iclass 5, count 2 2006.231.07:42:02.02#ibcon#read 6, iclass 5, count 2 2006.231.07:42:02.02#ibcon#end of sib2, iclass 5, count 2 2006.231.07:42:02.02#ibcon#*mode == 0, iclass 5, count 2 2006.231.07:42:02.02#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.07:42:02.02#ibcon#[27=AT05-03\r\n] 2006.231.07:42:02.02#ibcon#*before write, iclass 5, count 2 2006.231.07:42:02.02#ibcon#enter sib2, iclass 5, count 2 2006.231.07:42:02.02#ibcon#flushed, iclass 5, count 2 2006.231.07:42:02.02#ibcon#about to write, iclass 5, count 2 2006.231.07:42:02.02#ibcon#wrote, iclass 5, count 2 2006.231.07:42:02.02#ibcon#about to read 3, iclass 5, count 2 2006.231.07:42:02.05#ibcon#read 3, iclass 5, count 2 2006.231.07:42:02.05#ibcon#about to read 4, iclass 5, count 2 2006.231.07:42:02.05#ibcon#read 4, iclass 5, count 2 2006.231.07:42:02.05#ibcon#about to read 5, iclass 5, count 2 2006.231.07:42:02.05#ibcon#read 5, iclass 5, count 2 2006.231.07:42:02.05#ibcon#about to read 6, iclass 5, count 2 2006.231.07:42:02.05#ibcon#read 6, iclass 5, count 2 2006.231.07:42:02.05#ibcon#end of sib2, iclass 5, count 2 2006.231.07:42:02.05#ibcon#*after write, iclass 5, count 2 2006.231.07:42:02.05#ibcon#*before return 0, iclass 5, count 2 2006.231.07:42:02.05#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:42:02.05#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:42:02.05#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.07:42:02.05#ibcon#ireg 7 cls_cnt 0 2006.231.07:42:02.05#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:42:02.17#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:42:02.17#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:42:02.17#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:42:02.17#ibcon#first serial, iclass 5, count 0 2006.231.07:42:02.17#ibcon#enter sib2, iclass 5, count 0 2006.231.07:42:02.17#ibcon#flushed, iclass 5, count 0 2006.231.07:42:02.17#ibcon#about to write, iclass 5, count 0 2006.231.07:42:02.17#ibcon#wrote, iclass 5, count 0 2006.231.07:42:02.17#ibcon#about to read 3, iclass 5, count 0 2006.231.07:42:02.19#ibcon#read 3, iclass 5, count 0 2006.231.07:42:02.19#ibcon#about to read 4, iclass 5, count 0 2006.231.07:42:02.19#ibcon#read 4, iclass 5, count 0 2006.231.07:42:02.19#ibcon#about to read 5, iclass 5, count 0 2006.231.07:42:02.19#ibcon#read 5, iclass 5, count 0 2006.231.07:42:02.19#ibcon#about to read 6, iclass 5, count 0 2006.231.07:42:02.19#ibcon#read 6, iclass 5, count 0 2006.231.07:42:02.19#ibcon#end of sib2, iclass 5, count 0 2006.231.07:42:02.19#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:42:02.19#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:42:02.19#ibcon#[27=USB\r\n] 2006.231.07:42:02.19#ibcon#*before write, iclass 5, count 0 2006.231.07:42:02.19#ibcon#enter sib2, iclass 5, count 0 2006.231.07:42:02.19#ibcon#flushed, iclass 5, count 0 2006.231.07:42:02.19#ibcon#about to write, iclass 5, count 0 2006.231.07:42:02.19#ibcon#wrote, iclass 5, count 0 2006.231.07:42:02.19#ibcon#about to read 3, iclass 5, count 0 2006.231.07:42:02.22#ibcon#read 3, iclass 5, count 0 2006.231.07:42:02.22#ibcon#about to read 4, iclass 5, count 0 2006.231.07:42:02.22#ibcon#read 4, iclass 5, count 0 2006.231.07:42:02.22#ibcon#about to read 5, iclass 5, count 0 2006.231.07:42:02.22#ibcon#read 5, iclass 5, count 0 2006.231.07:42:02.22#ibcon#about to read 6, iclass 5, count 0 2006.231.07:42:02.22#ibcon#read 6, iclass 5, count 0 2006.231.07:42:02.22#ibcon#end of sib2, iclass 5, count 0 2006.231.07:42:02.22#ibcon#*after write, iclass 5, count 0 2006.231.07:42:02.22#ibcon#*before return 0, iclass 5, count 0 2006.231.07:42:02.22#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:42:02.22#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:42:02.22#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:42:02.22#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:42:02.22$vc4f8/vblo=6,752.99 2006.231.07:42:02.22#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.07:42:02.22#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.07:42:02.22#ibcon#ireg 17 cls_cnt 0 2006.231.07:42:02.22#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:42:02.22#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:42:02.22#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:42:02.22#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:42:02.22#ibcon#first serial, iclass 7, count 0 2006.231.07:42:02.22#ibcon#enter sib2, iclass 7, count 0 2006.231.07:42:02.22#ibcon#flushed, iclass 7, count 0 2006.231.07:42:02.22#ibcon#about to write, iclass 7, count 0 2006.231.07:42:02.22#ibcon#wrote, iclass 7, count 0 2006.231.07:42:02.22#ibcon#about to read 3, iclass 7, count 0 2006.231.07:42:02.24#ibcon#read 3, iclass 7, count 0 2006.231.07:42:02.24#ibcon#about to read 4, iclass 7, count 0 2006.231.07:42:02.24#ibcon#read 4, iclass 7, count 0 2006.231.07:42:02.24#ibcon#about to read 5, iclass 7, count 0 2006.231.07:42:02.24#ibcon#read 5, iclass 7, count 0 2006.231.07:42:02.24#ibcon#about to read 6, iclass 7, count 0 2006.231.07:42:02.24#ibcon#read 6, iclass 7, count 0 2006.231.07:42:02.24#ibcon#end of sib2, iclass 7, count 0 2006.231.07:42:02.24#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:42:02.24#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:42:02.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:42:02.24#ibcon#*before write, iclass 7, count 0 2006.231.07:42:02.24#ibcon#enter sib2, iclass 7, count 0 2006.231.07:42:02.24#ibcon#flushed, iclass 7, count 0 2006.231.07:42:02.24#ibcon#about to write, iclass 7, count 0 2006.231.07:42:02.24#ibcon#wrote, iclass 7, count 0 2006.231.07:42:02.24#ibcon#about to read 3, iclass 7, count 0 2006.231.07:42:02.28#ibcon#read 3, iclass 7, count 0 2006.231.07:42:02.28#ibcon#about to read 4, iclass 7, count 0 2006.231.07:42:02.28#ibcon#read 4, iclass 7, count 0 2006.231.07:42:02.28#ibcon#about to read 5, iclass 7, count 0 2006.231.07:42:02.28#ibcon#read 5, iclass 7, count 0 2006.231.07:42:02.28#ibcon#about to read 6, iclass 7, count 0 2006.231.07:42:02.28#ibcon#read 6, iclass 7, count 0 2006.231.07:42:02.28#ibcon#end of sib2, iclass 7, count 0 2006.231.07:42:02.28#ibcon#*after write, iclass 7, count 0 2006.231.07:42:02.28#ibcon#*before return 0, iclass 7, count 0 2006.231.07:42:02.28#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:42:02.28#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:42:02.28#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:42:02.28#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:42:02.28$vc4f8/vb=6,4 2006.231.07:42:02.28#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.07:42:02.28#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.07:42:02.28#ibcon#ireg 11 cls_cnt 2 2006.231.07:42:02.28#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:42:02.34#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:42:02.34#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:42:02.34#ibcon#enter wrdev, iclass 11, count 2 2006.231.07:42:02.34#ibcon#first serial, iclass 11, count 2 2006.231.07:42:02.34#ibcon#enter sib2, iclass 11, count 2 2006.231.07:42:02.34#ibcon#flushed, iclass 11, count 2 2006.231.07:42:02.34#ibcon#about to write, iclass 11, count 2 2006.231.07:42:02.34#ibcon#wrote, iclass 11, count 2 2006.231.07:42:02.34#ibcon#about to read 3, iclass 11, count 2 2006.231.07:42:02.36#ibcon#read 3, iclass 11, count 2 2006.231.07:42:02.36#ibcon#about to read 4, iclass 11, count 2 2006.231.07:42:02.36#ibcon#read 4, iclass 11, count 2 2006.231.07:42:02.36#ibcon#about to read 5, iclass 11, count 2 2006.231.07:42:02.36#ibcon#read 5, iclass 11, count 2 2006.231.07:42:02.36#ibcon#about to read 6, iclass 11, count 2 2006.231.07:42:02.36#ibcon#read 6, iclass 11, count 2 2006.231.07:42:02.36#ibcon#end of sib2, iclass 11, count 2 2006.231.07:42:02.36#ibcon#*mode == 0, iclass 11, count 2 2006.231.07:42:02.36#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.07:42:02.36#ibcon#[27=AT06-04\r\n] 2006.231.07:42:02.36#ibcon#*before write, iclass 11, count 2 2006.231.07:42:02.36#ibcon#enter sib2, iclass 11, count 2 2006.231.07:42:02.36#ibcon#flushed, iclass 11, count 2 2006.231.07:42:02.36#ibcon#about to write, iclass 11, count 2 2006.231.07:42:02.36#ibcon#wrote, iclass 11, count 2 2006.231.07:42:02.36#ibcon#about to read 3, iclass 11, count 2 2006.231.07:42:02.39#ibcon#read 3, iclass 11, count 2 2006.231.07:42:02.39#ibcon#about to read 4, iclass 11, count 2 2006.231.07:42:02.39#ibcon#read 4, iclass 11, count 2 2006.231.07:42:02.39#ibcon#about to read 5, iclass 11, count 2 2006.231.07:42:02.39#ibcon#read 5, iclass 11, count 2 2006.231.07:42:02.39#ibcon#about to read 6, iclass 11, count 2 2006.231.07:42:02.39#ibcon#read 6, iclass 11, count 2 2006.231.07:42:02.39#ibcon#end of sib2, iclass 11, count 2 2006.231.07:42:02.39#ibcon#*after write, iclass 11, count 2 2006.231.07:42:02.39#ibcon#*before return 0, iclass 11, count 2 2006.231.07:42:02.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:42:02.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:42:02.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.07:42:02.39#ibcon#ireg 7 cls_cnt 0 2006.231.07:42:02.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:42:02.51#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:42:02.51#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:42:02.51#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:42:02.51#ibcon#first serial, iclass 11, count 0 2006.231.07:42:02.51#ibcon#enter sib2, iclass 11, count 0 2006.231.07:42:02.51#ibcon#flushed, iclass 11, count 0 2006.231.07:42:02.51#ibcon#about to write, iclass 11, count 0 2006.231.07:42:02.51#ibcon#wrote, iclass 11, count 0 2006.231.07:42:02.51#ibcon#about to read 3, iclass 11, count 0 2006.231.07:42:02.53#ibcon#read 3, iclass 11, count 0 2006.231.07:42:02.53#ibcon#about to read 4, iclass 11, count 0 2006.231.07:42:02.53#ibcon#read 4, iclass 11, count 0 2006.231.07:42:02.53#ibcon#about to read 5, iclass 11, count 0 2006.231.07:42:02.53#ibcon#read 5, iclass 11, count 0 2006.231.07:42:02.53#ibcon#about to read 6, iclass 11, count 0 2006.231.07:42:02.53#ibcon#read 6, iclass 11, count 0 2006.231.07:42:02.53#ibcon#end of sib2, iclass 11, count 0 2006.231.07:42:02.53#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:42:02.53#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:42:02.53#ibcon#[27=USB\r\n] 2006.231.07:42:02.53#ibcon#*before write, iclass 11, count 0 2006.231.07:42:02.53#ibcon#enter sib2, iclass 11, count 0 2006.231.07:42:02.53#ibcon#flushed, iclass 11, count 0 2006.231.07:42:02.53#ibcon#about to write, iclass 11, count 0 2006.231.07:42:02.53#ibcon#wrote, iclass 11, count 0 2006.231.07:42:02.53#ibcon#about to read 3, iclass 11, count 0 2006.231.07:42:02.56#ibcon#read 3, iclass 11, count 0 2006.231.07:42:02.56#ibcon#about to read 4, iclass 11, count 0 2006.231.07:42:02.56#ibcon#read 4, iclass 11, count 0 2006.231.07:42:02.56#ibcon#about to read 5, iclass 11, count 0 2006.231.07:42:02.56#ibcon#read 5, iclass 11, count 0 2006.231.07:42:02.56#ibcon#about to read 6, iclass 11, count 0 2006.231.07:42:02.56#ibcon#read 6, iclass 11, count 0 2006.231.07:42:02.56#ibcon#end of sib2, iclass 11, count 0 2006.231.07:42:02.56#ibcon#*after write, iclass 11, count 0 2006.231.07:42:02.56#ibcon#*before return 0, iclass 11, count 0 2006.231.07:42:02.56#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:42:02.56#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:42:02.56#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:42:02.56#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:42:02.56$vc4f8/vabw=wide 2006.231.07:42:02.56#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.07:42:02.56#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.07:42:02.56#ibcon#ireg 8 cls_cnt 0 2006.231.07:42:02.56#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:42:02.56#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:42:02.56#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:42:02.56#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:42:02.56#ibcon#first serial, iclass 13, count 0 2006.231.07:42:02.56#ibcon#enter sib2, iclass 13, count 0 2006.231.07:42:02.56#ibcon#flushed, iclass 13, count 0 2006.231.07:42:02.56#ibcon#about to write, iclass 13, count 0 2006.231.07:42:02.56#ibcon#wrote, iclass 13, count 0 2006.231.07:42:02.56#ibcon#about to read 3, iclass 13, count 0 2006.231.07:42:02.59#ibcon#read 3, iclass 13, count 0 2006.231.07:42:02.59#ibcon#about to read 4, iclass 13, count 0 2006.231.07:42:02.59#ibcon#read 4, iclass 13, count 0 2006.231.07:42:02.59#ibcon#about to read 5, iclass 13, count 0 2006.231.07:42:02.59#ibcon#read 5, iclass 13, count 0 2006.231.07:42:02.59#ibcon#about to read 6, iclass 13, count 0 2006.231.07:42:02.59#ibcon#read 6, iclass 13, count 0 2006.231.07:42:02.59#ibcon#end of sib2, iclass 13, count 0 2006.231.07:42:02.59#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:42:02.59#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:42:02.59#ibcon#[25=BW32\r\n] 2006.231.07:42:02.59#ibcon#*before write, iclass 13, count 0 2006.231.07:42:02.59#ibcon#enter sib2, iclass 13, count 0 2006.231.07:42:02.59#ibcon#flushed, iclass 13, count 0 2006.231.07:42:02.59#ibcon#about to write, iclass 13, count 0 2006.231.07:42:02.59#ibcon#wrote, iclass 13, count 0 2006.231.07:42:02.59#ibcon#about to read 3, iclass 13, count 0 2006.231.07:42:02.62#ibcon#read 3, iclass 13, count 0 2006.231.07:42:02.62#ibcon#about to read 4, iclass 13, count 0 2006.231.07:42:02.62#ibcon#read 4, iclass 13, count 0 2006.231.07:42:02.62#ibcon#about to read 5, iclass 13, count 0 2006.231.07:42:02.62#ibcon#read 5, iclass 13, count 0 2006.231.07:42:02.62#ibcon#about to read 6, iclass 13, count 0 2006.231.07:42:02.62#ibcon#read 6, iclass 13, count 0 2006.231.07:42:02.62#ibcon#end of sib2, iclass 13, count 0 2006.231.07:42:02.62#ibcon#*after write, iclass 13, count 0 2006.231.07:42:02.62#ibcon#*before return 0, iclass 13, count 0 2006.231.07:42:02.62#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:42:02.62#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:42:02.62#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:42:02.62#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:42:02.62$vc4f8/vbbw=wide 2006.231.07:42:02.62#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.07:42:02.62#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.07:42:02.62#ibcon#ireg 8 cls_cnt 0 2006.231.07:42:02.62#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:42:02.68#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:42:02.68#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:42:02.68#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:42:02.68#ibcon#first serial, iclass 15, count 0 2006.231.07:42:02.68#ibcon#enter sib2, iclass 15, count 0 2006.231.07:42:02.68#ibcon#flushed, iclass 15, count 0 2006.231.07:42:02.68#ibcon#about to write, iclass 15, count 0 2006.231.07:42:02.68#ibcon#wrote, iclass 15, count 0 2006.231.07:42:02.68#ibcon#about to read 3, iclass 15, count 0 2006.231.07:42:02.70#ibcon#read 3, iclass 15, count 0 2006.231.07:42:02.70#ibcon#about to read 4, iclass 15, count 0 2006.231.07:42:02.70#ibcon#read 4, iclass 15, count 0 2006.231.07:42:02.70#ibcon#about to read 5, iclass 15, count 0 2006.231.07:42:02.70#ibcon#read 5, iclass 15, count 0 2006.231.07:42:02.70#ibcon#about to read 6, iclass 15, count 0 2006.231.07:42:02.70#ibcon#read 6, iclass 15, count 0 2006.231.07:42:02.70#ibcon#end of sib2, iclass 15, count 0 2006.231.07:42:02.70#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:42:02.70#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:42:02.70#ibcon#[27=BW32\r\n] 2006.231.07:42:02.70#ibcon#*before write, iclass 15, count 0 2006.231.07:42:02.70#ibcon#enter sib2, iclass 15, count 0 2006.231.07:42:02.70#ibcon#flushed, iclass 15, count 0 2006.231.07:42:02.70#ibcon#about to write, iclass 15, count 0 2006.231.07:42:02.70#ibcon#wrote, iclass 15, count 0 2006.231.07:42:02.70#ibcon#about to read 3, iclass 15, count 0 2006.231.07:42:02.73#ibcon#read 3, iclass 15, count 0 2006.231.07:42:02.73#ibcon#about to read 4, iclass 15, count 0 2006.231.07:42:02.73#ibcon#read 4, iclass 15, count 0 2006.231.07:42:02.73#ibcon#about to read 5, iclass 15, count 0 2006.231.07:42:02.73#ibcon#read 5, iclass 15, count 0 2006.231.07:42:02.73#ibcon#about to read 6, iclass 15, count 0 2006.231.07:42:02.73#ibcon#read 6, iclass 15, count 0 2006.231.07:42:02.73#ibcon#end of sib2, iclass 15, count 0 2006.231.07:42:02.73#ibcon#*after write, iclass 15, count 0 2006.231.07:42:02.73#ibcon#*before return 0, iclass 15, count 0 2006.231.07:42:02.73#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:42:02.73#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:42:02.73#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:42:02.73#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:42:02.73$4f8m12a/ifd4f 2006.231.07:42:02.73$ifd4f/lo= 2006.231.07:42:02.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:42:02.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:42:02.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:42:02.73$ifd4f/patch= 2006.231.07:42:02.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:42:02.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:42:02.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:42:02.73$4f8m12a/"form=m,16.000,1:2 2006.231.07:42:02.73$4f8m12a/"tpicd 2006.231.07:42:02.73$4f8m12a/echo=off 2006.231.07:42:02.73$4f8m12a/xlog=off 2006.231.07:42:02.73:!2006.231.07:42:30 2006.231.07:42:10.14#trakl#Source acquired 2006.231.07:42:12.14#flagr#flagr/antenna,acquired 2006.231.07:42:30.00:preob 2006.231.07:42:31.14/onsource/TRACKING 2006.231.07:42:31.14:!2006.231.07:42:40 2006.231.07:42:40.00:data_valid=on 2006.231.07:42:40.00:midob 2006.231.07:42:40.13/onsource/TRACKING 2006.231.07:42:40.13/wx/30.64,1004.4,84 2006.231.07:42:40.34/cable/+6.3702E-03 2006.231.07:42:41.43/va/01,08,usb,yes,30,31 2006.231.07:42:41.43/va/02,07,usb,yes,30,31 2006.231.07:42:41.43/va/03,08,usb,yes,22,22 2006.231.07:42:41.43/va/04,07,usb,yes,31,34 2006.231.07:42:41.43/va/05,07,usb,yes,34,36 2006.231.07:42:41.43/va/06,06,usb,yes,33,33 2006.231.07:42:41.43/va/07,06,usb,yes,34,34 2006.231.07:42:41.43/va/08,06,usb,yes,36,36 2006.231.07:42:41.66/valo/01,532.99,yes,locked 2006.231.07:42:41.66/valo/02,572.99,yes,locked 2006.231.07:42:41.66/valo/03,672.99,yes,locked 2006.231.07:42:41.66/valo/04,832.99,yes,locked 2006.231.07:42:41.66/valo/05,652.99,yes,locked 2006.231.07:42:41.66/valo/06,772.99,yes,locked 2006.231.07:42:41.66/valo/07,832.99,yes,locked 2006.231.07:42:41.66/valo/08,852.99,yes,locked 2006.231.07:42:42.75/vb/01,04,usb,yes,31,29 2006.231.07:42:42.75/vb/02,04,usb,yes,32,34 2006.231.07:42:42.75/vb/03,04,usb,yes,29,32 2006.231.07:42:42.75/vb/04,04,usb,yes,30,30 2006.231.07:42:42.75/vb/05,03,usb,yes,35,40 2006.231.07:42:42.75/vb/06,04,usb,yes,29,32 2006.231.07:42:42.75/vb/07,04,usb,yes,31,31 2006.231.07:42:42.75/vb/08,04,usb,yes,29,32 2006.231.07:42:42.99/vblo/01,632.99,yes,locked 2006.231.07:42:42.99/vblo/02,640.99,yes,locked 2006.231.07:42:42.99/vblo/03,656.99,yes,locked 2006.231.07:42:42.99/vblo/04,712.99,yes,locked 2006.231.07:42:42.99/vblo/05,744.99,yes,locked 2006.231.07:42:42.99/vblo/06,752.99,yes,locked 2006.231.07:42:42.99/vblo/07,734.99,yes,locked 2006.231.07:42:42.99/vblo/08,744.99,yes,locked 2006.231.07:42:43.14/vabw/8 2006.231.07:42:43.29/vbbw/8 2006.231.07:42:43.44/xfe/off,on,12.2 2006.231.07:42:43.83/ifatt/23,28,28,28 2006.231.07:42:44.08/fmout-gps/S +4.42E-07 2006.231.07:42:44.12:!2006.231.07:43:40 2006.231.07:43:40.00:data_valid=off 2006.231.07:43:40.00:postob 2006.231.07:43:40.10/cable/+6.3691E-03 2006.231.07:43:40.10/wx/30.63,1004.4,84 2006.231.07:43:41.08/fmout-gps/S +4.41E-07 2006.231.07:43:41.08:scan_name=231-0744,k06231,70 2006.231.07:43:41.08:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.231.07:43:42.13#flagr#flagr/antenna,new-source 2006.231.07:43:42.13:checkk5 2006.231.07:43:42.48/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:43:42.85/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:43:43.23/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:43:43.62/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:43:43.98/chk_obsdata//k5ts1/T2310742??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:43:44.34/chk_obsdata//k5ts2/T2310742??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:43:44.71/chk_obsdata//k5ts3/T2310742??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:43:45.09/chk_obsdata//k5ts4/T2310742??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:43:45.79/k5log//k5ts1_log_newline 2006.231.07:43:46.48/k5log//k5ts2_log_newline 2006.231.07:43:47.18/k5log//k5ts3_log_newline 2006.231.07:43:47.87/k5log//k5ts4_log_newline 2006.231.07:43:47.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:43:47.89:4f8m12a=1 2006.231.07:43:47.89$4f8m12a/echo=on 2006.231.07:43:47.89$4f8m12a/pcalon 2006.231.07:43:47.89$pcalon/"no phase cal control is implemented here 2006.231.07:43:47.89$4f8m12a/"tpicd=stop 2006.231.07:43:47.89$4f8m12a/vc4f8 2006.231.07:43:47.89$vc4f8/valo=1,532.99 2006.231.07:43:47.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.07:43:47.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.07:43:47.90#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:47.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:43:47.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:43:47.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:43:47.90#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:43:47.90#ibcon#first serial, iclass 22, count 0 2006.231.07:43:47.90#ibcon#enter sib2, iclass 22, count 0 2006.231.07:43:47.90#ibcon#flushed, iclass 22, count 0 2006.231.07:43:47.90#ibcon#about to write, iclass 22, count 0 2006.231.07:43:47.90#ibcon#wrote, iclass 22, count 0 2006.231.07:43:47.90#ibcon#about to read 3, iclass 22, count 0 2006.231.07:43:47.93#ibcon#read 3, iclass 22, count 0 2006.231.07:43:47.93#ibcon#about to read 4, iclass 22, count 0 2006.231.07:43:47.93#ibcon#read 4, iclass 22, count 0 2006.231.07:43:47.93#ibcon#about to read 5, iclass 22, count 0 2006.231.07:43:47.93#ibcon#read 5, iclass 22, count 0 2006.231.07:43:47.94#ibcon#about to read 6, iclass 22, count 0 2006.231.07:43:47.94#ibcon#read 6, iclass 22, count 0 2006.231.07:43:47.94#ibcon#end of sib2, iclass 22, count 0 2006.231.07:43:47.94#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:43:47.94#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:43:47.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:43:47.94#ibcon#*before write, iclass 22, count 0 2006.231.07:43:47.94#ibcon#enter sib2, iclass 22, count 0 2006.231.07:43:47.94#ibcon#flushed, iclass 22, count 0 2006.231.07:43:47.94#ibcon#about to write, iclass 22, count 0 2006.231.07:43:47.94#ibcon#wrote, iclass 22, count 0 2006.231.07:43:47.94#ibcon#about to read 3, iclass 22, count 0 2006.231.07:43:47.98#ibcon#read 3, iclass 22, count 0 2006.231.07:43:47.98#ibcon#about to read 4, iclass 22, count 0 2006.231.07:43:47.98#ibcon#read 4, iclass 22, count 0 2006.231.07:43:47.98#ibcon#about to read 5, iclass 22, count 0 2006.231.07:43:47.98#ibcon#read 5, iclass 22, count 0 2006.231.07:43:47.98#ibcon#about to read 6, iclass 22, count 0 2006.231.07:43:47.98#ibcon#read 6, iclass 22, count 0 2006.231.07:43:47.98#ibcon#end of sib2, iclass 22, count 0 2006.231.07:43:47.98#ibcon#*after write, iclass 22, count 0 2006.231.07:43:47.98#ibcon#*before return 0, iclass 22, count 0 2006.231.07:43:47.98#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:43:47.98#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:43:47.98#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:43:47.98#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:43:47.98$vc4f8/va=1,8 2006.231.07:43:47.98#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.07:43:47.98#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.07:43:47.98#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:47.98#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:43:47.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:43:47.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:43:47.98#ibcon#enter wrdev, iclass 24, count 2 2006.231.07:43:47.98#ibcon#first serial, iclass 24, count 2 2006.231.07:43:47.98#ibcon#enter sib2, iclass 24, count 2 2006.231.07:43:47.98#ibcon#flushed, iclass 24, count 2 2006.231.07:43:47.98#ibcon#about to write, iclass 24, count 2 2006.231.07:43:47.98#ibcon#wrote, iclass 24, count 2 2006.231.07:43:47.98#ibcon#about to read 3, iclass 24, count 2 2006.231.07:43:48.00#ibcon#read 3, iclass 24, count 2 2006.231.07:43:48.00#ibcon#about to read 4, iclass 24, count 2 2006.231.07:43:48.00#ibcon#read 4, iclass 24, count 2 2006.231.07:43:48.00#ibcon#about to read 5, iclass 24, count 2 2006.231.07:43:48.00#ibcon#read 5, iclass 24, count 2 2006.231.07:43:48.00#ibcon#about to read 6, iclass 24, count 2 2006.231.07:43:48.00#ibcon#read 6, iclass 24, count 2 2006.231.07:43:48.00#ibcon#end of sib2, iclass 24, count 2 2006.231.07:43:48.00#ibcon#*mode == 0, iclass 24, count 2 2006.231.07:43:48.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.07:43:48.00#ibcon#[25=AT01-08\r\n] 2006.231.07:43:48.00#ibcon#*before write, iclass 24, count 2 2006.231.07:43:48.00#ibcon#enter sib2, iclass 24, count 2 2006.231.07:43:48.00#ibcon#flushed, iclass 24, count 2 2006.231.07:43:48.00#ibcon#about to write, iclass 24, count 2 2006.231.07:43:48.00#ibcon#wrote, iclass 24, count 2 2006.231.07:43:48.00#ibcon#about to read 3, iclass 24, count 2 2006.231.07:43:48.04#ibcon#read 3, iclass 24, count 2 2006.231.07:43:48.04#ibcon#about to read 4, iclass 24, count 2 2006.231.07:43:48.04#ibcon#read 4, iclass 24, count 2 2006.231.07:43:48.04#ibcon#about to read 5, iclass 24, count 2 2006.231.07:43:48.04#ibcon#read 5, iclass 24, count 2 2006.231.07:43:48.04#ibcon#about to read 6, iclass 24, count 2 2006.231.07:43:48.04#ibcon#read 6, iclass 24, count 2 2006.231.07:43:48.04#ibcon#end of sib2, iclass 24, count 2 2006.231.07:43:48.04#ibcon#*after write, iclass 24, count 2 2006.231.07:43:48.04#ibcon#*before return 0, iclass 24, count 2 2006.231.07:43:48.04#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:43:48.04#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:43:48.04#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.07:43:48.04#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:48.04#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:43:48.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:43:48.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:43:48.15#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:43:48.15#ibcon#first serial, iclass 24, count 0 2006.231.07:43:48.15#ibcon#enter sib2, iclass 24, count 0 2006.231.07:43:48.15#ibcon#flushed, iclass 24, count 0 2006.231.07:43:48.15#ibcon#about to write, iclass 24, count 0 2006.231.07:43:48.15#ibcon#wrote, iclass 24, count 0 2006.231.07:43:48.15#ibcon#about to read 3, iclass 24, count 0 2006.231.07:43:48.17#ibcon#read 3, iclass 24, count 0 2006.231.07:43:48.17#ibcon#about to read 4, iclass 24, count 0 2006.231.07:43:48.17#ibcon#read 4, iclass 24, count 0 2006.231.07:43:48.17#ibcon#about to read 5, iclass 24, count 0 2006.231.07:43:48.17#ibcon#read 5, iclass 24, count 0 2006.231.07:43:48.17#ibcon#about to read 6, iclass 24, count 0 2006.231.07:43:48.17#ibcon#read 6, iclass 24, count 0 2006.231.07:43:48.17#ibcon#end of sib2, iclass 24, count 0 2006.231.07:43:48.17#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:43:48.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:43:48.17#ibcon#[25=USB\r\n] 2006.231.07:43:48.17#ibcon#*before write, iclass 24, count 0 2006.231.07:43:48.17#ibcon#enter sib2, iclass 24, count 0 2006.231.07:43:48.17#ibcon#flushed, iclass 24, count 0 2006.231.07:43:48.17#ibcon#about to write, iclass 24, count 0 2006.231.07:43:48.17#ibcon#wrote, iclass 24, count 0 2006.231.07:43:48.17#ibcon#about to read 3, iclass 24, count 0 2006.231.07:43:48.20#ibcon#read 3, iclass 24, count 0 2006.231.07:43:48.20#ibcon#about to read 4, iclass 24, count 0 2006.231.07:43:48.20#ibcon#read 4, iclass 24, count 0 2006.231.07:43:48.20#ibcon#about to read 5, iclass 24, count 0 2006.231.07:43:48.20#ibcon#read 5, iclass 24, count 0 2006.231.07:43:48.20#ibcon#about to read 6, iclass 24, count 0 2006.231.07:43:48.20#ibcon#read 6, iclass 24, count 0 2006.231.07:43:48.20#ibcon#end of sib2, iclass 24, count 0 2006.231.07:43:48.20#ibcon#*after write, iclass 24, count 0 2006.231.07:43:48.20#ibcon#*before return 0, iclass 24, count 0 2006.231.07:43:48.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:43:48.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:43:48.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:43:48.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:43:48.20$vc4f8/valo=2,572.99 2006.231.07:43:48.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:43:48.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:43:48.20#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:48.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:43:48.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:43:48.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:43:48.20#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:43:48.20#ibcon#first serial, iclass 26, count 0 2006.231.07:43:48.20#ibcon#enter sib2, iclass 26, count 0 2006.231.07:43:48.20#ibcon#flushed, iclass 26, count 0 2006.231.07:43:48.20#ibcon#about to write, iclass 26, count 0 2006.231.07:43:48.20#ibcon#wrote, iclass 26, count 0 2006.231.07:43:48.20#ibcon#about to read 3, iclass 26, count 0 2006.231.07:43:48.22#ibcon#read 3, iclass 26, count 0 2006.231.07:43:48.22#ibcon#about to read 4, iclass 26, count 0 2006.231.07:43:48.22#ibcon#read 4, iclass 26, count 0 2006.231.07:43:48.22#ibcon#about to read 5, iclass 26, count 0 2006.231.07:43:48.22#ibcon#read 5, iclass 26, count 0 2006.231.07:43:48.22#ibcon#about to read 6, iclass 26, count 0 2006.231.07:43:48.22#ibcon#read 6, iclass 26, count 0 2006.231.07:43:48.22#ibcon#end of sib2, iclass 26, count 0 2006.231.07:43:48.22#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:43:48.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:43:48.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:43:48.22#ibcon#*before write, iclass 26, count 0 2006.231.07:43:48.22#ibcon#enter sib2, iclass 26, count 0 2006.231.07:43:48.22#ibcon#flushed, iclass 26, count 0 2006.231.07:43:48.22#ibcon#about to write, iclass 26, count 0 2006.231.07:43:48.22#ibcon#wrote, iclass 26, count 0 2006.231.07:43:48.22#ibcon#about to read 3, iclass 26, count 0 2006.231.07:43:48.26#ibcon#read 3, iclass 26, count 0 2006.231.07:43:48.26#ibcon#about to read 4, iclass 26, count 0 2006.231.07:43:48.26#ibcon#read 4, iclass 26, count 0 2006.231.07:43:48.26#ibcon#about to read 5, iclass 26, count 0 2006.231.07:43:48.26#ibcon#read 5, iclass 26, count 0 2006.231.07:43:48.26#ibcon#about to read 6, iclass 26, count 0 2006.231.07:43:48.26#ibcon#read 6, iclass 26, count 0 2006.231.07:43:48.26#ibcon#end of sib2, iclass 26, count 0 2006.231.07:43:48.26#ibcon#*after write, iclass 26, count 0 2006.231.07:43:48.26#ibcon#*before return 0, iclass 26, count 0 2006.231.07:43:48.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:43:48.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:43:48.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:43:48.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:43:48.26$vc4f8/va=2,7 2006.231.07:43:48.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.07:43:48.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.07:43:48.26#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:48.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:43:48.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:43:48.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:43:48.32#ibcon#enter wrdev, iclass 28, count 2 2006.231.07:43:48.32#ibcon#first serial, iclass 28, count 2 2006.231.07:43:48.32#ibcon#enter sib2, iclass 28, count 2 2006.231.07:43:48.32#ibcon#flushed, iclass 28, count 2 2006.231.07:43:48.32#ibcon#about to write, iclass 28, count 2 2006.231.07:43:48.32#ibcon#wrote, iclass 28, count 2 2006.231.07:43:48.32#ibcon#about to read 3, iclass 28, count 2 2006.231.07:43:48.34#ibcon#read 3, iclass 28, count 2 2006.231.07:43:48.34#ibcon#about to read 4, iclass 28, count 2 2006.231.07:43:48.34#ibcon#read 4, iclass 28, count 2 2006.231.07:43:48.34#ibcon#about to read 5, iclass 28, count 2 2006.231.07:43:48.34#ibcon#read 5, iclass 28, count 2 2006.231.07:43:48.34#ibcon#about to read 6, iclass 28, count 2 2006.231.07:43:48.34#ibcon#read 6, iclass 28, count 2 2006.231.07:43:48.34#ibcon#end of sib2, iclass 28, count 2 2006.231.07:43:48.34#ibcon#*mode == 0, iclass 28, count 2 2006.231.07:43:48.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.07:43:48.34#ibcon#[25=AT02-07\r\n] 2006.231.07:43:48.34#ibcon#*before write, iclass 28, count 2 2006.231.07:43:48.34#ibcon#enter sib2, iclass 28, count 2 2006.231.07:43:48.34#ibcon#flushed, iclass 28, count 2 2006.231.07:43:48.34#ibcon#about to write, iclass 28, count 2 2006.231.07:43:48.34#ibcon#wrote, iclass 28, count 2 2006.231.07:43:48.34#ibcon#about to read 3, iclass 28, count 2 2006.231.07:43:48.37#ibcon#read 3, iclass 28, count 2 2006.231.07:43:48.37#ibcon#about to read 4, iclass 28, count 2 2006.231.07:43:48.37#ibcon#read 4, iclass 28, count 2 2006.231.07:43:48.37#ibcon#about to read 5, iclass 28, count 2 2006.231.07:43:48.37#ibcon#read 5, iclass 28, count 2 2006.231.07:43:48.37#ibcon#about to read 6, iclass 28, count 2 2006.231.07:43:48.37#ibcon#read 6, iclass 28, count 2 2006.231.07:43:48.37#ibcon#end of sib2, iclass 28, count 2 2006.231.07:43:48.37#ibcon#*after write, iclass 28, count 2 2006.231.07:43:48.37#ibcon#*before return 0, iclass 28, count 2 2006.231.07:43:48.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:43:48.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:43:48.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.07:43:48.37#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:48.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:43:48.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:43:48.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:43:48.49#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:43:48.49#ibcon#first serial, iclass 28, count 0 2006.231.07:43:48.49#ibcon#enter sib2, iclass 28, count 0 2006.231.07:43:48.49#ibcon#flushed, iclass 28, count 0 2006.231.07:43:48.49#ibcon#about to write, iclass 28, count 0 2006.231.07:43:48.49#ibcon#wrote, iclass 28, count 0 2006.231.07:43:48.49#ibcon#about to read 3, iclass 28, count 0 2006.231.07:43:48.51#ibcon#read 3, iclass 28, count 0 2006.231.07:43:48.51#ibcon#about to read 4, iclass 28, count 0 2006.231.07:43:48.51#ibcon#read 4, iclass 28, count 0 2006.231.07:43:48.51#ibcon#about to read 5, iclass 28, count 0 2006.231.07:43:48.51#ibcon#read 5, iclass 28, count 0 2006.231.07:43:48.51#ibcon#about to read 6, iclass 28, count 0 2006.231.07:43:48.51#ibcon#read 6, iclass 28, count 0 2006.231.07:43:48.51#ibcon#end of sib2, iclass 28, count 0 2006.231.07:43:48.51#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:43:48.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:43:48.51#ibcon#[25=USB\r\n] 2006.231.07:43:48.51#ibcon#*before write, iclass 28, count 0 2006.231.07:43:48.51#ibcon#enter sib2, iclass 28, count 0 2006.231.07:43:48.51#ibcon#flushed, iclass 28, count 0 2006.231.07:43:48.51#ibcon#about to write, iclass 28, count 0 2006.231.07:43:48.51#ibcon#wrote, iclass 28, count 0 2006.231.07:43:48.51#ibcon#about to read 3, iclass 28, count 0 2006.231.07:43:48.54#ibcon#read 3, iclass 28, count 0 2006.231.07:43:48.54#ibcon#about to read 4, iclass 28, count 0 2006.231.07:43:48.54#ibcon#read 4, iclass 28, count 0 2006.231.07:43:48.54#ibcon#about to read 5, iclass 28, count 0 2006.231.07:43:48.54#ibcon#read 5, iclass 28, count 0 2006.231.07:43:48.54#ibcon#about to read 6, iclass 28, count 0 2006.231.07:43:48.54#ibcon#read 6, iclass 28, count 0 2006.231.07:43:48.54#ibcon#end of sib2, iclass 28, count 0 2006.231.07:43:48.54#ibcon#*after write, iclass 28, count 0 2006.231.07:43:48.54#ibcon#*before return 0, iclass 28, count 0 2006.231.07:43:48.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:43:48.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:43:48.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:43:48.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:43:48.54$vc4f8/valo=3,672.99 2006.231.07:43:48.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.07:43:48.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.07:43:48.54#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:48.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:43:48.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:43:48.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:43:48.54#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:43:48.54#ibcon#first serial, iclass 30, count 0 2006.231.07:43:48.54#ibcon#enter sib2, iclass 30, count 0 2006.231.07:43:48.54#ibcon#flushed, iclass 30, count 0 2006.231.07:43:48.54#ibcon#about to write, iclass 30, count 0 2006.231.07:43:48.54#ibcon#wrote, iclass 30, count 0 2006.231.07:43:48.54#ibcon#about to read 3, iclass 30, count 0 2006.231.07:43:48.56#ibcon#read 3, iclass 30, count 0 2006.231.07:43:48.56#ibcon#about to read 4, iclass 30, count 0 2006.231.07:43:48.56#ibcon#read 4, iclass 30, count 0 2006.231.07:43:48.56#ibcon#about to read 5, iclass 30, count 0 2006.231.07:43:48.56#ibcon#read 5, iclass 30, count 0 2006.231.07:43:48.56#ibcon#about to read 6, iclass 30, count 0 2006.231.07:43:48.56#ibcon#read 6, iclass 30, count 0 2006.231.07:43:48.56#ibcon#end of sib2, iclass 30, count 0 2006.231.07:43:48.56#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:43:48.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:43:48.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:43:48.56#ibcon#*before write, iclass 30, count 0 2006.231.07:43:48.56#ibcon#enter sib2, iclass 30, count 0 2006.231.07:43:48.56#ibcon#flushed, iclass 30, count 0 2006.231.07:43:48.56#ibcon#about to write, iclass 30, count 0 2006.231.07:43:48.56#ibcon#wrote, iclass 30, count 0 2006.231.07:43:48.56#ibcon#about to read 3, iclass 30, count 0 2006.231.07:43:48.60#ibcon#read 3, iclass 30, count 0 2006.231.07:43:48.60#ibcon#about to read 4, iclass 30, count 0 2006.231.07:43:48.60#ibcon#read 4, iclass 30, count 0 2006.231.07:43:48.60#ibcon#about to read 5, iclass 30, count 0 2006.231.07:43:48.60#ibcon#read 5, iclass 30, count 0 2006.231.07:43:48.60#ibcon#about to read 6, iclass 30, count 0 2006.231.07:43:48.60#ibcon#read 6, iclass 30, count 0 2006.231.07:43:48.60#ibcon#end of sib2, iclass 30, count 0 2006.231.07:43:48.60#ibcon#*after write, iclass 30, count 0 2006.231.07:43:48.60#ibcon#*before return 0, iclass 30, count 0 2006.231.07:43:48.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:43:48.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:43:48.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:43:48.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:43:48.60$vc4f8/va=3,8 2006.231.07:43:48.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.07:43:48.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.07:43:48.60#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:48.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:43:48.67#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:43:48.67#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:43:48.67#ibcon#enter wrdev, iclass 32, count 2 2006.231.07:43:48.67#ibcon#first serial, iclass 32, count 2 2006.231.07:43:48.67#ibcon#enter sib2, iclass 32, count 2 2006.231.07:43:48.67#ibcon#flushed, iclass 32, count 2 2006.231.07:43:48.67#ibcon#about to write, iclass 32, count 2 2006.231.07:43:48.67#ibcon#wrote, iclass 32, count 2 2006.231.07:43:48.67#ibcon#about to read 3, iclass 32, count 2 2006.231.07:43:48.69#ibcon#read 3, iclass 32, count 2 2006.231.07:43:48.69#ibcon#about to read 4, iclass 32, count 2 2006.231.07:43:48.69#ibcon#read 4, iclass 32, count 2 2006.231.07:43:48.69#ibcon#about to read 5, iclass 32, count 2 2006.231.07:43:48.69#ibcon#read 5, iclass 32, count 2 2006.231.07:43:48.69#ibcon#about to read 6, iclass 32, count 2 2006.231.07:43:48.69#ibcon#read 6, iclass 32, count 2 2006.231.07:43:48.69#ibcon#end of sib2, iclass 32, count 2 2006.231.07:43:48.69#ibcon#*mode == 0, iclass 32, count 2 2006.231.07:43:48.69#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.07:43:48.69#ibcon#[25=AT03-08\r\n] 2006.231.07:43:48.69#ibcon#*before write, iclass 32, count 2 2006.231.07:43:48.69#ibcon#enter sib2, iclass 32, count 2 2006.231.07:43:48.69#ibcon#flushed, iclass 32, count 2 2006.231.07:43:48.69#ibcon#about to write, iclass 32, count 2 2006.231.07:43:48.69#ibcon#wrote, iclass 32, count 2 2006.231.07:43:48.69#ibcon#about to read 3, iclass 32, count 2 2006.231.07:43:48.72#ibcon#read 3, iclass 32, count 2 2006.231.07:43:48.72#ibcon#about to read 4, iclass 32, count 2 2006.231.07:43:48.72#ibcon#read 4, iclass 32, count 2 2006.231.07:43:48.72#ibcon#about to read 5, iclass 32, count 2 2006.231.07:43:48.72#ibcon#read 5, iclass 32, count 2 2006.231.07:43:48.72#ibcon#about to read 6, iclass 32, count 2 2006.231.07:43:48.72#ibcon#read 6, iclass 32, count 2 2006.231.07:43:48.72#ibcon#end of sib2, iclass 32, count 2 2006.231.07:43:48.72#ibcon#*after write, iclass 32, count 2 2006.231.07:43:48.72#ibcon#*before return 0, iclass 32, count 2 2006.231.07:43:48.72#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:43:48.72#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:43:48.72#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.07:43:48.72#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:48.72#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:43:48.84#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:43:48.84#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:43:48.84#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:43:48.84#ibcon#first serial, iclass 32, count 0 2006.231.07:43:48.84#ibcon#enter sib2, iclass 32, count 0 2006.231.07:43:48.84#ibcon#flushed, iclass 32, count 0 2006.231.07:43:48.84#ibcon#about to write, iclass 32, count 0 2006.231.07:43:48.84#ibcon#wrote, iclass 32, count 0 2006.231.07:43:48.84#ibcon#about to read 3, iclass 32, count 0 2006.231.07:43:48.86#ibcon#read 3, iclass 32, count 0 2006.231.07:43:48.86#ibcon#about to read 4, iclass 32, count 0 2006.231.07:43:48.86#ibcon#read 4, iclass 32, count 0 2006.231.07:43:48.86#ibcon#about to read 5, iclass 32, count 0 2006.231.07:43:48.86#ibcon#read 5, iclass 32, count 0 2006.231.07:43:48.86#ibcon#about to read 6, iclass 32, count 0 2006.231.07:43:48.86#ibcon#read 6, iclass 32, count 0 2006.231.07:43:48.86#ibcon#end of sib2, iclass 32, count 0 2006.231.07:43:48.86#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:43:48.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:43:48.86#ibcon#[25=USB\r\n] 2006.231.07:43:48.86#ibcon#*before write, iclass 32, count 0 2006.231.07:43:48.86#ibcon#enter sib2, iclass 32, count 0 2006.231.07:43:48.86#ibcon#flushed, iclass 32, count 0 2006.231.07:43:48.86#ibcon#about to write, iclass 32, count 0 2006.231.07:43:48.86#ibcon#wrote, iclass 32, count 0 2006.231.07:43:48.86#ibcon#about to read 3, iclass 32, count 0 2006.231.07:43:48.89#ibcon#read 3, iclass 32, count 0 2006.231.07:43:48.89#ibcon#about to read 4, iclass 32, count 0 2006.231.07:43:48.89#ibcon#read 4, iclass 32, count 0 2006.231.07:43:48.89#ibcon#about to read 5, iclass 32, count 0 2006.231.07:43:48.89#ibcon#read 5, iclass 32, count 0 2006.231.07:43:48.89#ibcon#about to read 6, iclass 32, count 0 2006.231.07:43:48.89#ibcon#read 6, iclass 32, count 0 2006.231.07:43:48.89#ibcon#end of sib2, iclass 32, count 0 2006.231.07:43:48.89#ibcon#*after write, iclass 32, count 0 2006.231.07:43:48.89#ibcon#*before return 0, iclass 32, count 0 2006.231.07:43:48.89#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:43:48.89#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:43:48.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:43:48.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:43:48.89$vc4f8/valo=4,832.99 2006.231.07:43:48.89#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.07:43:48.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.07:43:48.89#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:48.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:43:48.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:43:48.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:43:48.89#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:43:48.89#ibcon#first serial, iclass 34, count 0 2006.231.07:43:48.89#ibcon#enter sib2, iclass 34, count 0 2006.231.07:43:48.89#ibcon#flushed, iclass 34, count 0 2006.231.07:43:48.89#ibcon#about to write, iclass 34, count 0 2006.231.07:43:48.89#ibcon#wrote, iclass 34, count 0 2006.231.07:43:48.89#ibcon#about to read 3, iclass 34, count 0 2006.231.07:43:48.91#ibcon#read 3, iclass 34, count 0 2006.231.07:43:48.91#ibcon#about to read 4, iclass 34, count 0 2006.231.07:43:48.91#ibcon#read 4, iclass 34, count 0 2006.231.07:43:48.91#ibcon#about to read 5, iclass 34, count 0 2006.231.07:43:48.91#ibcon#read 5, iclass 34, count 0 2006.231.07:43:48.91#ibcon#about to read 6, iclass 34, count 0 2006.231.07:43:48.91#ibcon#read 6, iclass 34, count 0 2006.231.07:43:48.91#ibcon#end of sib2, iclass 34, count 0 2006.231.07:43:48.91#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:43:48.91#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:43:48.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:43:48.91#ibcon#*before write, iclass 34, count 0 2006.231.07:43:48.91#ibcon#enter sib2, iclass 34, count 0 2006.231.07:43:48.91#ibcon#flushed, iclass 34, count 0 2006.231.07:43:48.91#ibcon#about to write, iclass 34, count 0 2006.231.07:43:48.91#ibcon#wrote, iclass 34, count 0 2006.231.07:43:48.91#ibcon#about to read 3, iclass 34, count 0 2006.231.07:43:48.95#ibcon#read 3, iclass 34, count 0 2006.231.07:43:48.95#ibcon#about to read 4, iclass 34, count 0 2006.231.07:43:48.95#ibcon#read 4, iclass 34, count 0 2006.231.07:43:48.95#ibcon#about to read 5, iclass 34, count 0 2006.231.07:43:48.95#ibcon#read 5, iclass 34, count 0 2006.231.07:43:48.95#ibcon#about to read 6, iclass 34, count 0 2006.231.07:43:48.95#ibcon#read 6, iclass 34, count 0 2006.231.07:43:48.95#ibcon#end of sib2, iclass 34, count 0 2006.231.07:43:48.95#ibcon#*after write, iclass 34, count 0 2006.231.07:43:48.95#ibcon#*before return 0, iclass 34, count 0 2006.231.07:43:48.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:43:48.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:43:48.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:43:48.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:43:48.95$vc4f8/va=4,7 2006.231.07:43:48.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.07:43:48.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.07:43:48.95#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:48.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:43:49.01#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:43:49.01#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:43:49.01#ibcon#enter wrdev, iclass 36, count 2 2006.231.07:43:49.01#ibcon#first serial, iclass 36, count 2 2006.231.07:43:49.01#ibcon#enter sib2, iclass 36, count 2 2006.231.07:43:49.01#ibcon#flushed, iclass 36, count 2 2006.231.07:43:49.01#ibcon#about to write, iclass 36, count 2 2006.231.07:43:49.01#ibcon#wrote, iclass 36, count 2 2006.231.07:43:49.01#ibcon#about to read 3, iclass 36, count 2 2006.231.07:43:49.03#ibcon#read 3, iclass 36, count 2 2006.231.07:43:49.03#ibcon#about to read 4, iclass 36, count 2 2006.231.07:43:49.03#ibcon#read 4, iclass 36, count 2 2006.231.07:43:49.03#ibcon#about to read 5, iclass 36, count 2 2006.231.07:43:49.03#ibcon#read 5, iclass 36, count 2 2006.231.07:43:49.03#ibcon#about to read 6, iclass 36, count 2 2006.231.07:43:49.03#ibcon#read 6, iclass 36, count 2 2006.231.07:43:49.03#ibcon#end of sib2, iclass 36, count 2 2006.231.07:43:49.03#ibcon#*mode == 0, iclass 36, count 2 2006.231.07:43:49.03#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.07:43:49.03#ibcon#[25=AT04-07\r\n] 2006.231.07:43:49.03#ibcon#*before write, iclass 36, count 2 2006.231.07:43:49.03#ibcon#enter sib2, iclass 36, count 2 2006.231.07:43:49.03#ibcon#flushed, iclass 36, count 2 2006.231.07:43:49.03#ibcon#about to write, iclass 36, count 2 2006.231.07:43:49.03#ibcon#wrote, iclass 36, count 2 2006.231.07:43:49.03#ibcon#about to read 3, iclass 36, count 2 2006.231.07:43:49.06#ibcon#read 3, iclass 36, count 2 2006.231.07:43:49.06#ibcon#about to read 4, iclass 36, count 2 2006.231.07:43:49.06#ibcon#read 4, iclass 36, count 2 2006.231.07:43:49.06#ibcon#about to read 5, iclass 36, count 2 2006.231.07:43:49.06#ibcon#read 5, iclass 36, count 2 2006.231.07:43:49.06#ibcon#about to read 6, iclass 36, count 2 2006.231.07:43:49.06#ibcon#read 6, iclass 36, count 2 2006.231.07:43:49.06#ibcon#end of sib2, iclass 36, count 2 2006.231.07:43:49.06#ibcon#*after write, iclass 36, count 2 2006.231.07:43:49.06#ibcon#*before return 0, iclass 36, count 2 2006.231.07:43:49.06#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:43:49.06#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:43:49.06#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.07:43:49.06#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:49.06#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:43:49.18#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:43:49.18#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:43:49.18#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:43:49.18#ibcon#first serial, iclass 36, count 0 2006.231.07:43:49.18#ibcon#enter sib2, iclass 36, count 0 2006.231.07:43:49.18#ibcon#flushed, iclass 36, count 0 2006.231.07:43:49.18#ibcon#about to write, iclass 36, count 0 2006.231.07:43:49.18#ibcon#wrote, iclass 36, count 0 2006.231.07:43:49.18#ibcon#about to read 3, iclass 36, count 0 2006.231.07:43:49.20#ibcon#read 3, iclass 36, count 0 2006.231.07:43:49.20#ibcon#about to read 4, iclass 36, count 0 2006.231.07:43:49.20#ibcon#read 4, iclass 36, count 0 2006.231.07:43:49.20#ibcon#about to read 5, iclass 36, count 0 2006.231.07:43:49.20#ibcon#read 5, iclass 36, count 0 2006.231.07:43:49.20#ibcon#about to read 6, iclass 36, count 0 2006.231.07:43:49.20#ibcon#read 6, iclass 36, count 0 2006.231.07:43:49.20#ibcon#end of sib2, iclass 36, count 0 2006.231.07:43:49.20#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:43:49.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:43:49.20#ibcon#[25=USB\r\n] 2006.231.07:43:49.20#ibcon#*before write, iclass 36, count 0 2006.231.07:43:49.20#ibcon#enter sib2, iclass 36, count 0 2006.231.07:43:49.20#ibcon#flushed, iclass 36, count 0 2006.231.07:43:49.20#ibcon#about to write, iclass 36, count 0 2006.231.07:43:49.20#ibcon#wrote, iclass 36, count 0 2006.231.07:43:49.20#ibcon#about to read 3, iclass 36, count 0 2006.231.07:43:49.23#ibcon#read 3, iclass 36, count 0 2006.231.07:43:49.23#ibcon#about to read 4, iclass 36, count 0 2006.231.07:43:49.23#ibcon#read 4, iclass 36, count 0 2006.231.07:43:49.23#ibcon#about to read 5, iclass 36, count 0 2006.231.07:43:49.23#ibcon#read 5, iclass 36, count 0 2006.231.07:43:49.23#ibcon#about to read 6, iclass 36, count 0 2006.231.07:43:49.23#ibcon#read 6, iclass 36, count 0 2006.231.07:43:49.23#ibcon#end of sib2, iclass 36, count 0 2006.231.07:43:49.23#ibcon#*after write, iclass 36, count 0 2006.231.07:43:49.23#ibcon#*before return 0, iclass 36, count 0 2006.231.07:43:49.23#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:43:49.23#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:43:49.23#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:43:49.23#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:43:49.23$vc4f8/valo=5,652.99 2006.231.07:43:49.23#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.07:43:49.23#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.07:43:49.23#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:49.23#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:43:49.23#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:43:49.23#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:43:49.23#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:43:49.23#ibcon#first serial, iclass 38, count 0 2006.231.07:43:49.23#ibcon#enter sib2, iclass 38, count 0 2006.231.07:43:49.23#ibcon#flushed, iclass 38, count 0 2006.231.07:43:49.23#ibcon#about to write, iclass 38, count 0 2006.231.07:43:49.23#ibcon#wrote, iclass 38, count 0 2006.231.07:43:49.23#ibcon#about to read 3, iclass 38, count 0 2006.231.07:43:49.25#ibcon#read 3, iclass 38, count 0 2006.231.07:43:49.25#ibcon#about to read 4, iclass 38, count 0 2006.231.07:43:49.25#ibcon#read 4, iclass 38, count 0 2006.231.07:43:49.25#ibcon#about to read 5, iclass 38, count 0 2006.231.07:43:49.25#ibcon#read 5, iclass 38, count 0 2006.231.07:43:49.25#ibcon#about to read 6, iclass 38, count 0 2006.231.07:43:49.25#ibcon#read 6, iclass 38, count 0 2006.231.07:43:49.25#ibcon#end of sib2, iclass 38, count 0 2006.231.07:43:49.25#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:43:49.25#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:43:49.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:43:49.25#ibcon#*before write, iclass 38, count 0 2006.231.07:43:49.25#ibcon#enter sib2, iclass 38, count 0 2006.231.07:43:49.25#ibcon#flushed, iclass 38, count 0 2006.231.07:43:49.25#ibcon#about to write, iclass 38, count 0 2006.231.07:43:49.25#ibcon#wrote, iclass 38, count 0 2006.231.07:43:49.25#ibcon#about to read 3, iclass 38, count 0 2006.231.07:43:49.29#ibcon#read 3, iclass 38, count 0 2006.231.07:43:49.29#ibcon#about to read 4, iclass 38, count 0 2006.231.07:43:49.29#ibcon#read 4, iclass 38, count 0 2006.231.07:43:49.29#ibcon#about to read 5, iclass 38, count 0 2006.231.07:43:49.29#ibcon#read 5, iclass 38, count 0 2006.231.07:43:49.29#ibcon#about to read 6, iclass 38, count 0 2006.231.07:43:49.29#ibcon#read 6, iclass 38, count 0 2006.231.07:43:49.29#ibcon#end of sib2, iclass 38, count 0 2006.231.07:43:49.29#ibcon#*after write, iclass 38, count 0 2006.231.07:43:49.29#ibcon#*before return 0, iclass 38, count 0 2006.231.07:43:49.29#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:43:49.29#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:43:49.29#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:43:49.29#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:43:49.29$vc4f8/va=5,7 2006.231.07:43:49.29#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.07:43:49.29#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.07:43:49.29#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:49.29#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:43:49.35#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:43:49.35#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:43:49.35#ibcon#enter wrdev, iclass 40, count 2 2006.231.07:43:49.35#ibcon#first serial, iclass 40, count 2 2006.231.07:43:49.35#ibcon#enter sib2, iclass 40, count 2 2006.231.07:43:49.35#ibcon#flushed, iclass 40, count 2 2006.231.07:43:49.35#ibcon#about to write, iclass 40, count 2 2006.231.07:43:49.35#ibcon#wrote, iclass 40, count 2 2006.231.07:43:49.35#ibcon#about to read 3, iclass 40, count 2 2006.231.07:43:49.37#ibcon#read 3, iclass 40, count 2 2006.231.07:43:49.37#ibcon#about to read 4, iclass 40, count 2 2006.231.07:43:49.37#ibcon#read 4, iclass 40, count 2 2006.231.07:43:49.37#ibcon#about to read 5, iclass 40, count 2 2006.231.07:43:49.37#ibcon#read 5, iclass 40, count 2 2006.231.07:43:49.37#ibcon#about to read 6, iclass 40, count 2 2006.231.07:43:49.37#ibcon#read 6, iclass 40, count 2 2006.231.07:43:49.37#ibcon#end of sib2, iclass 40, count 2 2006.231.07:43:49.37#ibcon#*mode == 0, iclass 40, count 2 2006.231.07:43:49.37#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.07:43:49.37#ibcon#[25=AT05-07\r\n] 2006.231.07:43:49.37#ibcon#*before write, iclass 40, count 2 2006.231.07:43:49.37#ibcon#enter sib2, iclass 40, count 2 2006.231.07:43:49.37#ibcon#flushed, iclass 40, count 2 2006.231.07:43:49.37#ibcon#about to write, iclass 40, count 2 2006.231.07:43:49.37#ibcon#wrote, iclass 40, count 2 2006.231.07:43:49.37#ibcon#about to read 3, iclass 40, count 2 2006.231.07:43:49.40#ibcon#read 3, iclass 40, count 2 2006.231.07:43:49.40#ibcon#about to read 4, iclass 40, count 2 2006.231.07:43:49.40#ibcon#read 4, iclass 40, count 2 2006.231.07:43:49.40#ibcon#about to read 5, iclass 40, count 2 2006.231.07:43:49.40#ibcon#read 5, iclass 40, count 2 2006.231.07:43:49.40#ibcon#about to read 6, iclass 40, count 2 2006.231.07:43:49.40#ibcon#read 6, iclass 40, count 2 2006.231.07:43:49.40#ibcon#end of sib2, iclass 40, count 2 2006.231.07:43:49.40#ibcon#*after write, iclass 40, count 2 2006.231.07:43:49.40#ibcon#*before return 0, iclass 40, count 2 2006.231.07:43:49.40#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:43:49.40#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:43:49.40#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.07:43:49.40#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:49.40#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:43:49.52#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:43:49.52#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:43:49.52#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:43:49.52#ibcon#first serial, iclass 40, count 0 2006.231.07:43:49.52#ibcon#enter sib2, iclass 40, count 0 2006.231.07:43:49.52#ibcon#flushed, iclass 40, count 0 2006.231.07:43:49.52#ibcon#about to write, iclass 40, count 0 2006.231.07:43:49.52#ibcon#wrote, iclass 40, count 0 2006.231.07:43:49.52#ibcon#about to read 3, iclass 40, count 0 2006.231.07:43:49.54#ibcon#read 3, iclass 40, count 0 2006.231.07:43:49.54#ibcon#about to read 4, iclass 40, count 0 2006.231.07:43:49.54#ibcon#read 4, iclass 40, count 0 2006.231.07:43:49.54#ibcon#about to read 5, iclass 40, count 0 2006.231.07:43:49.54#ibcon#read 5, iclass 40, count 0 2006.231.07:43:49.54#ibcon#about to read 6, iclass 40, count 0 2006.231.07:43:49.54#ibcon#read 6, iclass 40, count 0 2006.231.07:43:49.54#ibcon#end of sib2, iclass 40, count 0 2006.231.07:43:49.54#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:43:49.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:43:49.54#ibcon#[25=USB\r\n] 2006.231.07:43:49.54#ibcon#*before write, iclass 40, count 0 2006.231.07:43:49.54#ibcon#enter sib2, iclass 40, count 0 2006.231.07:43:49.54#ibcon#flushed, iclass 40, count 0 2006.231.07:43:49.54#ibcon#about to write, iclass 40, count 0 2006.231.07:43:49.54#ibcon#wrote, iclass 40, count 0 2006.231.07:43:49.54#ibcon#about to read 3, iclass 40, count 0 2006.231.07:43:49.57#ibcon#read 3, iclass 40, count 0 2006.231.07:43:49.57#ibcon#about to read 4, iclass 40, count 0 2006.231.07:43:49.57#ibcon#read 4, iclass 40, count 0 2006.231.07:43:49.57#ibcon#about to read 5, iclass 40, count 0 2006.231.07:43:49.57#ibcon#read 5, iclass 40, count 0 2006.231.07:43:49.57#ibcon#about to read 6, iclass 40, count 0 2006.231.07:43:49.57#ibcon#read 6, iclass 40, count 0 2006.231.07:43:49.57#ibcon#end of sib2, iclass 40, count 0 2006.231.07:43:49.57#ibcon#*after write, iclass 40, count 0 2006.231.07:43:49.57#ibcon#*before return 0, iclass 40, count 0 2006.231.07:43:49.57#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:43:49.57#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:43:49.57#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:43:49.57#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:43:49.57$vc4f8/valo=6,772.99 2006.231.07:43:49.57#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.07:43:49.57#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.07:43:49.57#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:49.57#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:43:49.57#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:43:49.57#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:43:49.57#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:43:49.57#ibcon#first serial, iclass 4, count 0 2006.231.07:43:49.57#ibcon#enter sib2, iclass 4, count 0 2006.231.07:43:49.57#ibcon#flushed, iclass 4, count 0 2006.231.07:43:49.57#ibcon#about to write, iclass 4, count 0 2006.231.07:43:49.57#ibcon#wrote, iclass 4, count 0 2006.231.07:43:49.57#ibcon#about to read 3, iclass 4, count 0 2006.231.07:43:49.59#ibcon#read 3, iclass 4, count 0 2006.231.07:43:49.59#ibcon#about to read 4, iclass 4, count 0 2006.231.07:43:49.59#ibcon#read 4, iclass 4, count 0 2006.231.07:43:49.59#ibcon#about to read 5, iclass 4, count 0 2006.231.07:43:49.59#ibcon#read 5, iclass 4, count 0 2006.231.07:43:49.59#ibcon#about to read 6, iclass 4, count 0 2006.231.07:43:49.59#ibcon#read 6, iclass 4, count 0 2006.231.07:43:49.59#ibcon#end of sib2, iclass 4, count 0 2006.231.07:43:49.59#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:43:49.59#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:43:49.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:43:49.59#ibcon#*before write, iclass 4, count 0 2006.231.07:43:49.59#ibcon#enter sib2, iclass 4, count 0 2006.231.07:43:49.59#ibcon#flushed, iclass 4, count 0 2006.231.07:43:49.59#ibcon#about to write, iclass 4, count 0 2006.231.07:43:49.59#ibcon#wrote, iclass 4, count 0 2006.231.07:43:49.59#ibcon#about to read 3, iclass 4, count 0 2006.231.07:43:49.63#ibcon#read 3, iclass 4, count 0 2006.231.07:43:49.63#ibcon#about to read 4, iclass 4, count 0 2006.231.07:43:49.63#ibcon#read 4, iclass 4, count 0 2006.231.07:43:49.63#ibcon#about to read 5, iclass 4, count 0 2006.231.07:43:49.63#ibcon#read 5, iclass 4, count 0 2006.231.07:43:49.63#ibcon#about to read 6, iclass 4, count 0 2006.231.07:43:49.63#ibcon#read 6, iclass 4, count 0 2006.231.07:43:49.63#ibcon#end of sib2, iclass 4, count 0 2006.231.07:43:49.63#ibcon#*after write, iclass 4, count 0 2006.231.07:43:49.63#ibcon#*before return 0, iclass 4, count 0 2006.231.07:43:49.63#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:43:49.63#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:43:49.63#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:43:49.63#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:43:49.63$vc4f8/va=6,6 2006.231.07:43:49.63#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.07:43:49.63#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.07:43:49.63#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:49.63#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:43:49.69#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:43:49.69#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:43:49.69#ibcon#enter wrdev, iclass 6, count 2 2006.231.07:43:49.69#ibcon#first serial, iclass 6, count 2 2006.231.07:43:49.69#ibcon#enter sib2, iclass 6, count 2 2006.231.07:43:49.69#ibcon#flushed, iclass 6, count 2 2006.231.07:43:49.69#ibcon#about to write, iclass 6, count 2 2006.231.07:43:49.69#ibcon#wrote, iclass 6, count 2 2006.231.07:43:49.69#ibcon#about to read 3, iclass 6, count 2 2006.231.07:43:49.71#ibcon#read 3, iclass 6, count 2 2006.231.07:43:49.71#ibcon#about to read 4, iclass 6, count 2 2006.231.07:43:49.71#ibcon#read 4, iclass 6, count 2 2006.231.07:43:49.71#ibcon#about to read 5, iclass 6, count 2 2006.231.07:43:49.71#ibcon#read 5, iclass 6, count 2 2006.231.07:43:49.71#ibcon#about to read 6, iclass 6, count 2 2006.231.07:43:49.71#ibcon#read 6, iclass 6, count 2 2006.231.07:43:49.71#ibcon#end of sib2, iclass 6, count 2 2006.231.07:43:49.71#ibcon#*mode == 0, iclass 6, count 2 2006.231.07:43:49.71#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.07:43:49.71#ibcon#[25=AT06-06\r\n] 2006.231.07:43:49.71#ibcon#*before write, iclass 6, count 2 2006.231.07:43:49.71#ibcon#enter sib2, iclass 6, count 2 2006.231.07:43:49.71#ibcon#flushed, iclass 6, count 2 2006.231.07:43:49.71#ibcon#about to write, iclass 6, count 2 2006.231.07:43:49.71#ibcon#wrote, iclass 6, count 2 2006.231.07:43:49.71#ibcon#about to read 3, iclass 6, count 2 2006.231.07:43:49.74#ibcon#read 3, iclass 6, count 2 2006.231.07:43:49.74#ibcon#about to read 4, iclass 6, count 2 2006.231.07:43:49.74#ibcon#read 4, iclass 6, count 2 2006.231.07:43:49.74#ibcon#about to read 5, iclass 6, count 2 2006.231.07:43:49.74#ibcon#read 5, iclass 6, count 2 2006.231.07:43:49.74#ibcon#about to read 6, iclass 6, count 2 2006.231.07:43:49.74#ibcon#read 6, iclass 6, count 2 2006.231.07:43:49.74#ibcon#end of sib2, iclass 6, count 2 2006.231.07:43:49.74#ibcon#*after write, iclass 6, count 2 2006.231.07:43:49.74#ibcon#*before return 0, iclass 6, count 2 2006.231.07:43:49.74#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:43:49.74#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:43:49.74#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.07:43:49.74#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:49.74#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:43:49.86#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:43:49.86#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:43:49.86#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:43:49.86#ibcon#first serial, iclass 6, count 0 2006.231.07:43:49.86#ibcon#enter sib2, iclass 6, count 0 2006.231.07:43:49.86#ibcon#flushed, iclass 6, count 0 2006.231.07:43:49.86#ibcon#about to write, iclass 6, count 0 2006.231.07:43:49.86#ibcon#wrote, iclass 6, count 0 2006.231.07:43:49.86#ibcon#about to read 3, iclass 6, count 0 2006.231.07:43:49.88#ibcon#read 3, iclass 6, count 0 2006.231.07:43:49.88#ibcon#about to read 4, iclass 6, count 0 2006.231.07:43:49.88#ibcon#read 4, iclass 6, count 0 2006.231.07:43:49.88#ibcon#about to read 5, iclass 6, count 0 2006.231.07:43:49.88#ibcon#read 5, iclass 6, count 0 2006.231.07:43:49.88#ibcon#about to read 6, iclass 6, count 0 2006.231.07:43:49.88#ibcon#read 6, iclass 6, count 0 2006.231.07:43:49.88#ibcon#end of sib2, iclass 6, count 0 2006.231.07:43:49.88#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:43:49.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:43:49.88#ibcon#[25=USB\r\n] 2006.231.07:43:49.88#ibcon#*before write, iclass 6, count 0 2006.231.07:43:49.88#ibcon#enter sib2, iclass 6, count 0 2006.231.07:43:49.88#ibcon#flushed, iclass 6, count 0 2006.231.07:43:49.88#ibcon#about to write, iclass 6, count 0 2006.231.07:43:49.88#ibcon#wrote, iclass 6, count 0 2006.231.07:43:49.88#ibcon#about to read 3, iclass 6, count 0 2006.231.07:43:49.91#ibcon#read 3, iclass 6, count 0 2006.231.07:43:49.91#ibcon#about to read 4, iclass 6, count 0 2006.231.07:43:49.91#ibcon#read 4, iclass 6, count 0 2006.231.07:43:49.91#ibcon#about to read 5, iclass 6, count 0 2006.231.07:43:49.91#ibcon#read 5, iclass 6, count 0 2006.231.07:43:49.91#ibcon#about to read 6, iclass 6, count 0 2006.231.07:43:49.91#ibcon#read 6, iclass 6, count 0 2006.231.07:43:49.91#ibcon#end of sib2, iclass 6, count 0 2006.231.07:43:49.91#ibcon#*after write, iclass 6, count 0 2006.231.07:43:49.91#ibcon#*before return 0, iclass 6, count 0 2006.231.07:43:49.91#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:43:49.91#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:43:49.91#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:43:49.91#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:43:49.91$vc4f8/valo=7,832.99 2006.231.07:43:49.91#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.07:43:49.91#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.07:43:49.91#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:49.91#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:43:49.91#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:43:49.91#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:43:49.91#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:43:49.91#ibcon#first serial, iclass 10, count 0 2006.231.07:43:49.91#ibcon#enter sib2, iclass 10, count 0 2006.231.07:43:49.91#ibcon#flushed, iclass 10, count 0 2006.231.07:43:49.91#ibcon#about to write, iclass 10, count 0 2006.231.07:43:49.91#ibcon#wrote, iclass 10, count 0 2006.231.07:43:49.91#ibcon#about to read 3, iclass 10, count 0 2006.231.07:43:49.93#ibcon#read 3, iclass 10, count 0 2006.231.07:43:49.93#ibcon#about to read 4, iclass 10, count 0 2006.231.07:43:49.93#ibcon#read 4, iclass 10, count 0 2006.231.07:43:49.93#ibcon#about to read 5, iclass 10, count 0 2006.231.07:43:49.93#ibcon#read 5, iclass 10, count 0 2006.231.07:43:49.93#ibcon#about to read 6, iclass 10, count 0 2006.231.07:43:49.93#ibcon#read 6, iclass 10, count 0 2006.231.07:43:49.93#ibcon#end of sib2, iclass 10, count 0 2006.231.07:43:49.93#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:43:49.93#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:43:49.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:43:49.93#ibcon#*before write, iclass 10, count 0 2006.231.07:43:49.93#ibcon#enter sib2, iclass 10, count 0 2006.231.07:43:49.93#ibcon#flushed, iclass 10, count 0 2006.231.07:43:49.93#ibcon#about to write, iclass 10, count 0 2006.231.07:43:49.93#ibcon#wrote, iclass 10, count 0 2006.231.07:43:49.93#ibcon#about to read 3, iclass 10, count 0 2006.231.07:43:49.97#ibcon#read 3, iclass 10, count 0 2006.231.07:43:49.97#ibcon#about to read 4, iclass 10, count 0 2006.231.07:43:49.97#ibcon#read 4, iclass 10, count 0 2006.231.07:43:49.97#ibcon#about to read 5, iclass 10, count 0 2006.231.07:43:49.97#ibcon#read 5, iclass 10, count 0 2006.231.07:43:49.97#ibcon#about to read 6, iclass 10, count 0 2006.231.07:43:49.97#ibcon#read 6, iclass 10, count 0 2006.231.07:43:49.97#ibcon#end of sib2, iclass 10, count 0 2006.231.07:43:49.97#ibcon#*after write, iclass 10, count 0 2006.231.07:43:49.97#ibcon#*before return 0, iclass 10, count 0 2006.231.07:43:49.97#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:43:49.97#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:43:49.97#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:43:49.97#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:43:49.97$vc4f8/va=7,6 2006.231.07:43:49.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.07:43:49.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.07:43:49.97#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:49.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:43:50.04#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:43:50.04#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:43:50.04#ibcon#enter wrdev, iclass 12, count 2 2006.231.07:43:50.04#ibcon#first serial, iclass 12, count 2 2006.231.07:43:50.04#ibcon#enter sib2, iclass 12, count 2 2006.231.07:43:50.04#ibcon#flushed, iclass 12, count 2 2006.231.07:43:50.04#ibcon#about to write, iclass 12, count 2 2006.231.07:43:50.04#ibcon#wrote, iclass 12, count 2 2006.231.07:43:50.04#ibcon#about to read 3, iclass 12, count 2 2006.231.07:43:50.05#ibcon#read 3, iclass 12, count 2 2006.231.07:43:50.05#ibcon#about to read 4, iclass 12, count 2 2006.231.07:43:50.05#ibcon#read 4, iclass 12, count 2 2006.231.07:43:50.05#ibcon#about to read 5, iclass 12, count 2 2006.231.07:43:50.05#ibcon#read 5, iclass 12, count 2 2006.231.07:43:50.05#ibcon#about to read 6, iclass 12, count 2 2006.231.07:43:50.05#ibcon#read 6, iclass 12, count 2 2006.231.07:43:50.05#ibcon#end of sib2, iclass 12, count 2 2006.231.07:43:50.05#ibcon#*mode == 0, iclass 12, count 2 2006.231.07:43:50.05#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.07:43:50.05#ibcon#[25=AT07-06\r\n] 2006.231.07:43:50.05#ibcon#*before write, iclass 12, count 2 2006.231.07:43:50.05#ibcon#enter sib2, iclass 12, count 2 2006.231.07:43:50.05#ibcon#flushed, iclass 12, count 2 2006.231.07:43:50.05#ibcon#about to write, iclass 12, count 2 2006.231.07:43:50.05#ibcon#wrote, iclass 12, count 2 2006.231.07:43:50.05#ibcon#about to read 3, iclass 12, count 2 2006.231.07:43:50.08#ibcon#read 3, iclass 12, count 2 2006.231.07:43:50.08#ibcon#about to read 4, iclass 12, count 2 2006.231.07:43:50.08#ibcon#read 4, iclass 12, count 2 2006.231.07:43:50.08#ibcon#about to read 5, iclass 12, count 2 2006.231.07:43:50.08#ibcon#read 5, iclass 12, count 2 2006.231.07:43:50.08#ibcon#about to read 6, iclass 12, count 2 2006.231.07:43:50.08#ibcon#read 6, iclass 12, count 2 2006.231.07:43:50.08#ibcon#end of sib2, iclass 12, count 2 2006.231.07:43:50.08#ibcon#*after write, iclass 12, count 2 2006.231.07:43:50.08#ibcon#*before return 0, iclass 12, count 2 2006.231.07:43:50.08#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:43:50.08#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:43:50.08#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.07:43:50.08#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:50.08#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:43:50.20#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:43:50.20#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:43:50.20#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:43:50.20#ibcon#first serial, iclass 12, count 0 2006.231.07:43:50.20#ibcon#enter sib2, iclass 12, count 0 2006.231.07:43:50.20#ibcon#flushed, iclass 12, count 0 2006.231.07:43:50.20#ibcon#about to write, iclass 12, count 0 2006.231.07:43:50.20#ibcon#wrote, iclass 12, count 0 2006.231.07:43:50.20#ibcon#about to read 3, iclass 12, count 0 2006.231.07:43:50.22#ibcon#read 3, iclass 12, count 0 2006.231.07:43:50.22#ibcon#about to read 4, iclass 12, count 0 2006.231.07:43:50.22#ibcon#read 4, iclass 12, count 0 2006.231.07:43:50.22#ibcon#about to read 5, iclass 12, count 0 2006.231.07:43:50.22#ibcon#read 5, iclass 12, count 0 2006.231.07:43:50.22#ibcon#about to read 6, iclass 12, count 0 2006.231.07:43:50.22#ibcon#read 6, iclass 12, count 0 2006.231.07:43:50.22#ibcon#end of sib2, iclass 12, count 0 2006.231.07:43:50.22#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:43:50.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:43:50.22#ibcon#[25=USB\r\n] 2006.231.07:43:50.22#ibcon#*before write, iclass 12, count 0 2006.231.07:43:50.22#ibcon#enter sib2, iclass 12, count 0 2006.231.07:43:50.22#ibcon#flushed, iclass 12, count 0 2006.231.07:43:50.22#ibcon#about to write, iclass 12, count 0 2006.231.07:43:50.22#ibcon#wrote, iclass 12, count 0 2006.231.07:43:50.22#ibcon#about to read 3, iclass 12, count 0 2006.231.07:43:50.25#ibcon#read 3, iclass 12, count 0 2006.231.07:43:50.25#ibcon#about to read 4, iclass 12, count 0 2006.231.07:43:50.25#ibcon#read 4, iclass 12, count 0 2006.231.07:43:50.25#ibcon#about to read 5, iclass 12, count 0 2006.231.07:43:50.25#ibcon#read 5, iclass 12, count 0 2006.231.07:43:50.25#ibcon#about to read 6, iclass 12, count 0 2006.231.07:43:50.25#ibcon#read 6, iclass 12, count 0 2006.231.07:43:50.25#ibcon#end of sib2, iclass 12, count 0 2006.231.07:43:50.25#ibcon#*after write, iclass 12, count 0 2006.231.07:43:50.25#ibcon#*before return 0, iclass 12, count 0 2006.231.07:43:50.25#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:43:50.25#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:43:50.25#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:43:50.25#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:43:50.25$vc4f8/valo=8,852.99 2006.231.07:43:50.25#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.07:43:50.25#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.07:43:50.25#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:50.25#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:43:50.25#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:43:50.25#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:43:50.25#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:43:50.25#ibcon#first serial, iclass 14, count 0 2006.231.07:43:50.25#ibcon#enter sib2, iclass 14, count 0 2006.231.07:43:50.25#ibcon#flushed, iclass 14, count 0 2006.231.07:43:50.25#ibcon#about to write, iclass 14, count 0 2006.231.07:43:50.25#ibcon#wrote, iclass 14, count 0 2006.231.07:43:50.25#ibcon#about to read 3, iclass 14, count 0 2006.231.07:43:50.27#ibcon#read 3, iclass 14, count 0 2006.231.07:43:50.27#ibcon#about to read 4, iclass 14, count 0 2006.231.07:43:50.27#ibcon#read 4, iclass 14, count 0 2006.231.07:43:50.27#ibcon#about to read 5, iclass 14, count 0 2006.231.07:43:50.27#ibcon#read 5, iclass 14, count 0 2006.231.07:43:50.27#ibcon#about to read 6, iclass 14, count 0 2006.231.07:43:50.27#ibcon#read 6, iclass 14, count 0 2006.231.07:43:50.27#ibcon#end of sib2, iclass 14, count 0 2006.231.07:43:50.27#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:43:50.27#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:43:50.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:43:50.27#ibcon#*before write, iclass 14, count 0 2006.231.07:43:50.27#ibcon#enter sib2, iclass 14, count 0 2006.231.07:43:50.27#ibcon#flushed, iclass 14, count 0 2006.231.07:43:50.27#ibcon#about to write, iclass 14, count 0 2006.231.07:43:50.27#ibcon#wrote, iclass 14, count 0 2006.231.07:43:50.27#ibcon#about to read 3, iclass 14, count 0 2006.231.07:43:50.31#ibcon#read 3, iclass 14, count 0 2006.231.07:43:50.31#ibcon#about to read 4, iclass 14, count 0 2006.231.07:43:50.31#ibcon#read 4, iclass 14, count 0 2006.231.07:43:50.31#ibcon#about to read 5, iclass 14, count 0 2006.231.07:43:50.31#ibcon#read 5, iclass 14, count 0 2006.231.07:43:50.31#ibcon#about to read 6, iclass 14, count 0 2006.231.07:43:50.31#ibcon#read 6, iclass 14, count 0 2006.231.07:43:50.31#ibcon#end of sib2, iclass 14, count 0 2006.231.07:43:50.31#ibcon#*after write, iclass 14, count 0 2006.231.07:43:50.31#ibcon#*before return 0, iclass 14, count 0 2006.231.07:43:50.31#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:43:50.31#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:43:50.31#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:43:50.31#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:43:50.31$vc4f8/va=8,6 2006.231.07:43:50.31#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.07:43:50.31#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.07:43:50.31#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:50.31#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:43:50.37#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:43:50.37#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:43:50.37#ibcon#enter wrdev, iclass 16, count 2 2006.231.07:43:50.37#ibcon#first serial, iclass 16, count 2 2006.231.07:43:50.37#ibcon#enter sib2, iclass 16, count 2 2006.231.07:43:50.37#ibcon#flushed, iclass 16, count 2 2006.231.07:43:50.37#ibcon#about to write, iclass 16, count 2 2006.231.07:43:50.37#ibcon#wrote, iclass 16, count 2 2006.231.07:43:50.37#ibcon#about to read 3, iclass 16, count 2 2006.231.07:43:50.39#ibcon#read 3, iclass 16, count 2 2006.231.07:43:50.39#ibcon#about to read 4, iclass 16, count 2 2006.231.07:43:50.39#ibcon#read 4, iclass 16, count 2 2006.231.07:43:50.39#ibcon#about to read 5, iclass 16, count 2 2006.231.07:43:50.39#ibcon#read 5, iclass 16, count 2 2006.231.07:43:50.39#ibcon#about to read 6, iclass 16, count 2 2006.231.07:43:50.39#ibcon#read 6, iclass 16, count 2 2006.231.07:43:50.39#ibcon#end of sib2, iclass 16, count 2 2006.231.07:43:50.39#ibcon#*mode == 0, iclass 16, count 2 2006.231.07:43:50.39#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.07:43:50.39#ibcon#[25=AT08-06\r\n] 2006.231.07:43:50.39#ibcon#*before write, iclass 16, count 2 2006.231.07:43:50.39#ibcon#enter sib2, iclass 16, count 2 2006.231.07:43:50.39#ibcon#flushed, iclass 16, count 2 2006.231.07:43:50.39#ibcon#about to write, iclass 16, count 2 2006.231.07:43:50.39#ibcon#wrote, iclass 16, count 2 2006.231.07:43:50.39#ibcon#about to read 3, iclass 16, count 2 2006.231.07:43:50.42#ibcon#read 3, iclass 16, count 2 2006.231.07:43:50.42#ibcon#about to read 4, iclass 16, count 2 2006.231.07:43:50.42#ibcon#read 4, iclass 16, count 2 2006.231.07:43:50.42#ibcon#about to read 5, iclass 16, count 2 2006.231.07:43:50.42#ibcon#read 5, iclass 16, count 2 2006.231.07:43:50.42#ibcon#about to read 6, iclass 16, count 2 2006.231.07:43:50.42#ibcon#read 6, iclass 16, count 2 2006.231.07:43:50.42#ibcon#end of sib2, iclass 16, count 2 2006.231.07:43:50.42#ibcon#*after write, iclass 16, count 2 2006.231.07:43:50.42#ibcon#*before return 0, iclass 16, count 2 2006.231.07:43:50.42#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:43:50.42#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:43:50.42#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.07:43:50.42#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:50.42#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:43:50.54#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:43:50.54#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:43:50.54#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:43:50.54#ibcon#first serial, iclass 16, count 0 2006.231.07:43:50.54#ibcon#enter sib2, iclass 16, count 0 2006.231.07:43:50.54#ibcon#flushed, iclass 16, count 0 2006.231.07:43:50.54#ibcon#about to write, iclass 16, count 0 2006.231.07:43:50.54#ibcon#wrote, iclass 16, count 0 2006.231.07:43:50.54#ibcon#about to read 3, iclass 16, count 0 2006.231.07:43:50.56#ibcon#read 3, iclass 16, count 0 2006.231.07:43:50.56#ibcon#about to read 4, iclass 16, count 0 2006.231.07:43:50.56#ibcon#read 4, iclass 16, count 0 2006.231.07:43:50.56#ibcon#about to read 5, iclass 16, count 0 2006.231.07:43:50.56#ibcon#read 5, iclass 16, count 0 2006.231.07:43:50.56#ibcon#about to read 6, iclass 16, count 0 2006.231.07:43:50.56#ibcon#read 6, iclass 16, count 0 2006.231.07:43:50.56#ibcon#end of sib2, iclass 16, count 0 2006.231.07:43:50.56#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:43:50.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:43:50.56#ibcon#[25=USB\r\n] 2006.231.07:43:50.56#ibcon#*before write, iclass 16, count 0 2006.231.07:43:50.56#ibcon#enter sib2, iclass 16, count 0 2006.231.07:43:50.56#ibcon#flushed, iclass 16, count 0 2006.231.07:43:50.56#ibcon#about to write, iclass 16, count 0 2006.231.07:43:50.56#ibcon#wrote, iclass 16, count 0 2006.231.07:43:50.56#ibcon#about to read 3, iclass 16, count 0 2006.231.07:43:50.59#ibcon#read 3, iclass 16, count 0 2006.231.07:43:50.59#ibcon#about to read 4, iclass 16, count 0 2006.231.07:43:50.59#ibcon#read 4, iclass 16, count 0 2006.231.07:43:50.59#ibcon#about to read 5, iclass 16, count 0 2006.231.07:43:50.59#ibcon#read 5, iclass 16, count 0 2006.231.07:43:50.59#ibcon#about to read 6, iclass 16, count 0 2006.231.07:43:50.59#ibcon#read 6, iclass 16, count 0 2006.231.07:43:50.59#ibcon#end of sib2, iclass 16, count 0 2006.231.07:43:50.59#ibcon#*after write, iclass 16, count 0 2006.231.07:43:50.59#ibcon#*before return 0, iclass 16, count 0 2006.231.07:43:50.59#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:43:50.59#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:43:50.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:43:50.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:43:50.59$vc4f8/vblo=1,632.99 2006.231.07:43:50.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.07:43:50.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.07:43:50.59#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:50.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:43:50.59#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:43:50.59#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:43:50.59#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:43:50.59#ibcon#first serial, iclass 18, count 0 2006.231.07:43:50.59#ibcon#enter sib2, iclass 18, count 0 2006.231.07:43:50.59#ibcon#flushed, iclass 18, count 0 2006.231.07:43:50.59#ibcon#about to write, iclass 18, count 0 2006.231.07:43:50.59#ibcon#wrote, iclass 18, count 0 2006.231.07:43:50.59#ibcon#about to read 3, iclass 18, count 0 2006.231.07:43:50.61#ibcon#read 3, iclass 18, count 0 2006.231.07:43:50.61#ibcon#about to read 4, iclass 18, count 0 2006.231.07:43:50.61#ibcon#read 4, iclass 18, count 0 2006.231.07:43:50.61#ibcon#about to read 5, iclass 18, count 0 2006.231.07:43:50.61#ibcon#read 5, iclass 18, count 0 2006.231.07:43:50.61#ibcon#about to read 6, iclass 18, count 0 2006.231.07:43:50.61#ibcon#read 6, iclass 18, count 0 2006.231.07:43:50.61#ibcon#end of sib2, iclass 18, count 0 2006.231.07:43:50.61#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:43:50.61#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:43:50.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:43:50.61#ibcon#*before write, iclass 18, count 0 2006.231.07:43:50.61#ibcon#enter sib2, iclass 18, count 0 2006.231.07:43:50.61#ibcon#flushed, iclass 18, count 0 2006.231.07:43:50.61#ibcon#about to write, iclass 18, count 0 2006.231.07:43:50.61#ibcon#wrote, iclass 18, count 0 2006.231.07:43:50.61#ibcon#about to read 3, iclass 18, count 0 2006.231.07:43:50.65#ibcon#read 3, iclass 18, count 0 2006.231.07:43:50.65#ibcon#about to read 4, iclass 18, count 0 2006.231.07:43:50.65#ibcon#read 4, iclass 18, count 0 2006.231.07:43:50.65#ibcon#about to read 5, iclass 18, count 0 2006.231.07:43:50.65#ibcon#read 5, iclass 18, count 0 2006.231.07:43:50.65#ibcon#about to read 6, iclass 18, count 0 2006.231.07:43:50.65#ibcon#read 6, iclass 18, count 0 2006.231.07:43:50.65#ibcon#end of sib2, iclass 18, count 0 2006.231.07:43:50.65#ibcon#*after write, iclass 18, count 0 2006.231.07:43:50.65#ibcon#*before return 0, iclass 18, count 0 2006.231.07:43:50.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:43:50.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:43:50.65#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:43:50.65#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:43:50.65$vc4f8/vb=1,4 2006.231.07:43:50.65#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.07:43:50.65#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.07:43:50.65#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:50.65#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:43:50.65#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:43:50.65#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:43:50.65#ibcon#enter wrdev, iclass 20, count 2 2006.231.07:43:50.65#ibcon#first serial, iclass 20, count 2 2006.231.07:43:50.65#ibcon#enter sib2, iclass 20, count 2 2006.231.07:43:50.65#ibcon#flushed, iclass 20, count 2 2006.231.07:43:50.65#ibcon#about to write, iclass 20, count 2 2006.231.07:43:50.65#ibcon#wrote, iclass 20, count 2 2006.231.07:43:50.65#ibcon#about to read 3, iclass 20, count 2 2006.231.07:43:50.67#ibcon#read 3, iclass 20, count 2 2006.231.07:43:50.67#ibcon#about to read 4, iclass 20, count 2 2006.231.07:43:50.67#ibcon#read 4, iclass 20, count 2 2006.231.07:43:50.67#ibcon#about to read 5, iclass 20, count 2 2006.231.07:43:50.67#ibcon#read 5, iclass 20, count 2 2006.231.07:43:50.67#ibcon#about to read 6, iclass 20, count 2 2006.231.07:43:50.67#ibcon#read 6, iclass 20, count 2 2006.231.07:43:50.67#ibcon#end of sib2, iclass 20, count 2 2006.231.07:43:50.67#ibcon#*mode == 0, iclass 20, count 2 2006.231.07:43:50.67#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.07:43:50.67#ibcon#[27=AT01-04\r\n] 2006.231.07:43:50.67#ibcon#*before write, iclass 20, count 2 2006.231.07:43:50.67#ibcon#enter sib2, iclass 20, count 2 2006.231.07:43:50.67#ibcon#flushed, iclass 20, count 2 2006.231.07:43:50.67#ibcon#about to write, iclass 20, count 2 2006.231.07:43:50.67#ibcon#wrote, iclass 20, count 2 2006.231.07:43:50.67#ibcon#about to read 3, iclass 20, count 2 2006.231.07:43:50.70#ibcon#read 3, iclass 20, count 2 2006.231.07:43:50.70#ibcon#about to read 4, iclass 20, count 2 2006.231.07:43:50.70#ibcon#read 4, iclass 20, count 2 2006.231.07:43:50.70#ibcon#about to read 5, iclass 20, count 2 2006.231.07:43:50.70#ibcon#read 5, iclass 20, count 2 2006.231.07:43:50.70#ibcon#about to read 6, iclass 20, count 2 2006.231.07:43:50.70#ibcon#read 6, iclass 20, count 2 2006.231.07:43:50.70#ibcon#end of sib2, iclass 20, count 2 2006.231.07:43:50.70#ibcon#*after write, iclass 20, count 2 2006.231.07:43:50.70#ibcon#*before return 0, iclass 20, count 2 2006.231.07:43:50.70#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:43:50.70#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:43:50.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.07:43:50.70#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:50.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:43:50.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:43:50.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:43:50.83#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:43:50.83#ibcon#first serial, iclass 20, count 0 2006.231.07:43:50.83#ibcon#enter sib2, iclass 20, count 0 2006.231.07:43:50.83#ibcon#flushed, iclass 20, count 0 2006.231.07:43:50.83#ibcon#about to write, iclass 20, count 0 2006.231.07:43:50.83#ibcon#wrote, iclass 20, count 0 2006.231.07:43:50.83#ibcon#about to read 3, iclass 20, count 0 2006.231.07:43:50.84#ibcon#read 3, iclass 20, count 0 2006.231.07:43:50.84#ibcon#about to read 4, iclass 20, count 0 2006.231.07:43:50.84#ibcon#read 4, iclass 20, count 0 2006.231.07:43:50.84#ibcon#about to read 5, iclass 20, count 0 2006.231.07:43:50.84#ibcon#read 5, iclass 20, count 0 2006.231.07:43:50.84#ibcon#about to read 6, iclass 20, count 0 2006.231.07:43:50.84#ibcon#read 6, iclass 20, count 0 2006.231.07:43:50.84#ibcon#end of sib2, iclass 20, count 0 2006.231.07:43:50.84#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:43:50.84#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:43:50.84#ibcon#[27=USB\r\n] 2006.231.07:43:50.84#ibcon#*before write, iclass 20, count 0 2006.231.07:43:50.84#ibcon#enter sib2, iclass 20, count 0 2006.231.07:43:50.84#ibcon#flushed, iclass 20, count 0 2006.231.07:43:50.84#ibcon#about to write, iclass 20, count 0 2006.231.07:43:50.84#ibcon#wrote, iclass 20, count 0 2006.231.07:43:50.84#ibcon#about to read 3, iclass 20, count 0 2006.231.07:43:50.87#ibcon#read 3, iclass 20, count 0 2006.231.07:43:50.87#ibcon#about to read 4, iclass 20, count 0 2006.231.07:43:50.87#ibcon#read 4, iclass 20, count 0 2006.231.07:43:50.87#ibcon#about to read 5, iclass 20, count 0 2006.231.07:43:50.87#ibcon#read 5, iclass 20, count 0 2006.231.07:43:50.87#ibcon#about to read 6, iclass 20, count 0 2006.231.07:43:50.87#ibcon#read 6, iclass 20, count 0 2006.231.07:43:50.87#ibcon#end of sib2, iclass 20, count 0 2006.231.07:43:50.87#ibcon#*after write, iclass 20, count 0 2006.231.07:43:50.87#ibcon#*before return 0, iclass 20, count 0 2006.231.07:43:50.87#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:43:50.87#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:43:50.87#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:43:50.87#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:43:50.87$vc4f8/vblo=2,640.99 2006.231.07:43:50.87#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.07:43:50.87#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.07:43:50.87#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:50.87#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:43:50.87#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:43:50.87#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:43:50.87#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:43:50.87#ibcon#first serial, iclass 22, count 0 2006.231.07:43:50.87#ibcon#enter sib2, iclass 22, count 0 2006.231.07:43:50.87#ibcon#flushed, iclass 22, count 0 2006.231.07:43:50.87#ibcon#about to write, iclass 22, count 0 2006.231.07:43:50.87#ibcon#wrote, iclass 22, count 0 2006.231.07:43:50.87#ibcon#about to read 3, iclass 22, count 0 2006.231.07:43:50.89#ibcon#read 3, iclass 22, count 0 2006.231.07:43:50.89#ibcon#about to read 4, iclass 22, count 0 2006.231.07:43:50.89#ibcon#read 4, iclass 22, count 0 2006.231.07:43:50.89#ibcon#about to read 5, iclass 22, count 0 2006.231.07:43:50.89#ibcon#read 5, iclass 22, count 0 2006.231.07:43:50.89#ibcon#about to read 6, iclass 22, count 0 2006.231.07:43:50.89#ibcon#read 6, iclass 22, count 0 2006.231.07:43:50.89#ibcon#end of sib2, iclass 22, count 0 2006.231.07:43:50.89#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:43:50.89#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:43:50.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:43:50.89#ibcon#*before write, iclass 22, count 0 2006.231.07:43:50.89#ibcon#enter sib2, iclass 22, count 0 2006.231.07:43:50.89#ibcon#flushed, iclass 22, count 0 2006.231.07:43:50.89#ibcon#about to write, iclass 22, count 0 2006.231.07:43:50.89#ibcon#wrote, iclass 22, count 0 2006.231.07:43:50.89#ibcon#about to read 3, iclass 22, count 0 2006.231.07:43:50.94#ibcon#read 3, iclass 22, count 0 2006.231.07:43:50.94#ibcon#about to read 4, iclass 22, count 0 2006.231.07:43:50.94#ibcon#read 4, iclass 22, count 0 2006.231.07:43:50.94#ibcon#about to read 5, iclass 22, count 0 2006.231.07:43:50.94#ibcon#read 5, iclass 22, count 0 2006.231.07:43:50.94#ibcon#about to read 6, iclass 22, count 0 2006.231.07:43:50.94#ibcon#read 6, iclass 22, count 0 2006.231.07:43:50.94#ibcon#end of sib2, iclass 22, count 0 2006.231.07:43:50.94#ibcon#*after write, iclass 22, count 0 2006.231.07:43:50.94#ibcon#*before return 0, iclass 22, count 0 2006.231.07:43:50.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:43:50.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:43:50.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:43:50.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:43:50.94$vc4f8/vb=2,4 2006.231.07:43:50.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.07:43:50.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.07:43:50.94#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:50.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:43:50.98#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:43:50.98#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:43:50.98#ibcon#enter wrdev, iclass 24, count 2 2006.231.07:43:50.98#ibcon#first serial, iclass 24, count 2 2006.231.07:43:50.98#ibcon#enter sib2, iclass 24, count 2 2006.231.07:43:50.98#ibcon#flushed, iclass 24, count 2 2006.231.07:43:50.98#ibcon#about to write, iclass 24, count 2 2006.231.07:43:50.98#ibcon#wrote, iclass 24, count 2 2006.231.07:43:50.98#ibcon#about to read 3, iclass 24, count 2 2006.231.07:43:51.00#ibcon#read 3, iclass 24, count 2 2006.231.07:43:51.00#ibcon#about to read 4, iclass 24, count 2 2006.231.07:43:51.00#ibcon#read 4, iclass 24, count 2 2006.231.07:43:51.00#ibcon#about to read 5, iclass 24, count 2 2006.231.07:43:51.00#ibcon#read 5, iclass 24, count 2 2006.231.07:43:51.00#ibcon#about to read 6, iclass 24, count 2 2006.231.07:43:51.00#ibcon#read 6, iclass 24, count 2 2006.231.07:43:51.00#ibcon#end of sib2, iclass 24, count 2 2006.231.07:43:51.00#ibcon#*mode == 0, iclass 24, count 2 2006.231.07:43:51.00#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.07:43:51.00#ibcon#[27=AT02-04\r\n] 2006.231.07:43:51.00#ibcon#*before write, iclass 24, count 2 2006.231.07:43:51.00#ibcon#enter sib2, iclass 24, count 2 2006.231.07:43:51.00#ibcon#flushed, iclass 24, count 2 2006.231.07:43:51.00#ibcon#about to write, iclass 24, count 2 2006.231.07:43:51.00#ibcon#wrote, iclass 24, count 2 2006.231.07:43:51.00#ibcon#about to read 3, iclass 24, count 2 2006.231.07:43:51.03#ibcon#read 3, iclass 24, count 2 2006.231.07:43:51.03#ibcon#about to read 4, iclass 24, count 2 2006.231.07:43:51.03#ibcon#read 4, iclass 24, count 2 2006.231.07:43:51.03#ibcon#about to read 5, iclass 24, count 2 2006.231.07:43:51.03#ibcon#read 5, iclass 24, count 2 2006.231.07:43:51.03#ibcon#about to read 6, iclass 24, count 2 2006.231.07:43:51.03#ibcon#read 6, iclass 24, count 2 2006.231.07:43:51.03#ibcon#end of sib2, iclass 24, count 2 2006.231.07:43:51.03#ibcon#*after write, iclass 24, count 2 2006.231.07:43:51.03#ibcon#*before return 0, iclass 24, count 2 2006.231.07:43:51.03#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:43:51.03#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:43:51.03#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.07:43:51.03#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:51.03#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:43:51.15#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:43:51.15#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:43:51.15#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:43:51.15#ibcon#first serial, iclass 24, count 0 2006.231.07:43:51.15#ibcon#enter sib2, iclass 24, count 0 2006.231.07:43:51.15#ibcon#flushed, iclass 24, count 0 2006.231.07:43:51.15#ibcon#about to write, iclass 24, count 0 2006.231.07:43:51.15#ibcon#wrote, iclass 24, count 0 2006.231.07:43:51.15#ibcon#about to read 3, iclass 24, count 0 2006.231.07:43:51.17#ibcon#read 3, iclass 24, count 0 2006.231.07:43:51.17#ibcon#about to read 4, iclass 24, count 0 2006.231.07:43:51.17#ibcon#read 4, iclass 24, count 0 2006.231.07:43:51.17#ibcon#about to read 5, iclass 24, count 0 2006.231.07:43:51.17#ibcon#read 5, iclass 24, count 0 2006.231.07:43:51.17#ibcon#about to read 6, iclass 24, count 0 2006.231.07:43:51.17#ibcon#read 6, iclass 24, count 0 2006.231.07:43:51.17#ibcon#end of sib2, iclass 24, count 0 2006.231.07:43:51.17#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:43:51.17#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:43:51.17#ibcon#[27=USB\r\n] 2006.231.07:43:51.17#ibcon#*before write, iclass 24, count 0 2006.231.07:43:51.17#ibcon#enter sib2, iclass 24, count 0 2006.231.07:43:51.17#ibcon#flushed, iclass 24, count 0 2006.231.07:43:51.17#ibcon#about to write, iclass 24, count 0 2006.231.07:43:51.17#ibcon#wrote, iclass 24, count 0 2006.231.07:43:51.17#ibcon#about to read 3, iclass 24, count 0 2006.231.07:43:51.20#ibcon#read 3, iclass 24, count 0 2006.231.07:43:51.20#ibcon#about to read 4, iclass 24, count 0 2006.231.07:43:51.20#ibcon#read 4, iclass 24, count 0 2006.231.07:43:51.20#ibcon#about to read 5, iclass 24, count 0 2006.231.07:43:51.20#ibcon#read 5, iclass 24, count 0 2006.231.07:43:51.20#ibcon#about to read 6, iclass 24, count 0 2006.231.07:43:51.20#ibcon#read 6, iclass 24, count 0 2006.231.07:43:51.20#ibcon#end of sib2, iclass 24, count 0 2006.231.07:43:51.20#ibcon#*after write, iclass 24, count 0 2006.231.07:43:51.20#ibcon#*before return 0, iclass 24, count 0 2006.231.07:43:51.20#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:43:51.20#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:43:51.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:43:51.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:43:51.20$vc4f8/vblo=3,656.99 2006.231.07:43:51.20#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:43:51.20#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:43:51.20#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:51.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:43:51.20#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:43:51.20#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:43:51.20#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:43:51.20#ibcon#first serial, iclass 26, count 0 2006.231.07:43:51.20#ibcon#enter sib2, iclass 26, count 0 2006.231.07:43:51.20#ibcon#flushed, iclass 26, count 0 2006.231.07:43:51.20#ibcon#about to write, iclass 26, count 0 2006.231.07:43:51.20#ibcon#wrote, iclass 26, count 0 2006.231.07:43:51.20#ibcon#about to read 3, iclass 26, count 0 2006.231.07:43:51.22#ibcon#read 3, iclass 26, count 0 2006.231.07:43:51.22#ibcon#about to read 4, iclass 26, count 0 2006.231.07:43:51.22#ibcon#read 4, iclass 26, count 0 2006.231.07:43:51.22#ibcon#about to read 5, iclass 26, count 0 2006.231.07:43:51.22#ibcon#read 5, iclass 26, count 0 2006.231.07:43:51.22#ibcon#about to read 6, iclass 26, count 0 2006.231.07:43:51.22#ibcon#read 6, iclass 26, count 0 2006.231.07:43:51.22#ibcon#end of sib2, iclass 26, count 0 2006.231.07:43:51.22#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:43:51.22#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:43:51.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:43:51.22#ibcon#*before write, iclass 26, count 0 2006.231.07:43:51.22#ibcon#enter sib2, iclass 26, count 0 2006.231.07:43:51.22#ibcon#flushed, iclass 26, count 0 2006.231.07:43:51.22#ibcon#about to write, iclass 26, count 0 2006.231.07:43:51.22#ibcon#wrote, iclass 26, count 0 2006.231.07:43:51.22#ibcon#about to read 3, iclass 26, count 0 2006.231.07:43:51.26#ibcon#read 3, iclass 26, count 0 2006.231.07:43:51.26#ibcon#about to read 4, iclass 26, count 0 2006.231.07:43:51.26#ibcon#read 4, iclass 26, count 0 2006.231.07:43:51.26#ibcon#about to read 5, iclass 26, count 0 2006.231.07:43:51.26#ibcon#read 5, iclass 26, count 0 2006.231.07:43:51.26#ibcon#about to read 6, iclass 26, count 0 2006.231.07:43:51.26#ibcon#read 6, iclass 26, count 0 2006.231.07:43:51.26#ibcon#end of sib2, iclass 26, count 0 2006.231.07:43:51.26#ibcon#*after write, iclass 26, count 0 2006.231.07:43:51.26#ibcon#*before return 0, iclass 26, count 0 2006.231.07:43:51.26#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:43:51.26#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:43:51.26#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:43:51.26#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:43:51.26$vc4f8/vb=3,4 2006.231.07:43:51.26#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.07:43:51.26#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.07:43:51.26#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:51.26#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:43:51.32#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:43:51.32#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:43:51.32#ibcon#enter wrdev, iclass 28, count 2 2006.231.07:43:51.32#ibcon#first serial, iclass 28, count 2 2006.231.07:43:51.32#ibcon#enter sib2, iclass 28, count 2 2006.231.07:43:51.32#ibcon#flushed, iclass 28, count 2 2006.231.07:43:51.32#ibcon#about to write, iclass 28, count 2 2006.231.07:43:51.32#ibcon#wrote, iclass 28, count 2 2006.231.07:43:51.32#ibcon#about to read 3, iclass 28, count 2 2006.231.07:43:51.34#ibcon#read 3, iclass 28, count 2 2006.231.07:43:51.34#ibcon#about to read 4, iclass 28, count 2 2006.231.07:43:51.34#ibcon#read 4, iclass 28, count 2 2006.231.07:43:51.34#ibcon#about to read 5, iclass 28, count 2 2006.231.07:43:51.34#ibcon#read 5, iclass 28, count 2 2006.231.07:43:51.34#ibcon#about to read 6, iclass 28, count 2 2006.231.07:43:51.34#ibcon#read 6, iclass 28, count 2 2006.231.07:43:51.34#ibcon#end of sib2, iclass 28, count 2 2006.231.07:43:51.34#ibcon#*mode == 0, iclass 28, count 2 2006.231.07:43:51.34#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.07:43:51.34#ibcon#[27=AT03-04\r\n] 2006.231.07:43:51.34#ibcon#*before write, iclass 28, count 2 2006.231.07:43:51.34#ibcon#enter sib2, iclass 28, count 2 2006.231.07:43:51.34#ibcon#flushed, iclass 28, count 2 2006.231.07:43:51.34#ibcon#about to write, iclass 28, count 2 2006.231.07:43:51.34#ibcon#wrote, iclass 28, count 2 2006.231.07:43:51.34#ibcon#about to read 3, iclass 28, count 2 2006.231.07:43:51.37#ibcon#read 3, iclass 28, count 2 2006.231.07:43:51.37#ibcon#about to read 4, iclass 28, count 2 2006.231.07:43:51.37#ibcon#read 4, iclass 28, count 2 2006.231.07:43:51.37#ibcon#about to read 5, iclass 28, count 2 2006.231.07:43:51.37#ibcon#read 5, iclass 28, count 2 2006.231.07:43:51.37#ibcon#about to read 6, iclass 28, count 2 2006.231.07:43:51.37#ibcon#read 6, iclass 28, count 2 2006.231.07:43:51.37#ibcon#end of sib2, iclass 28, count 2 2006.231.07:43:51.37#ibcon#*after write, iclass 28, count 2 2006.231.07:43:51.37#ibcon#*before return 0, iclass 28, count 2 2006.231.07:43:51.37#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:43:51.37#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:43:51.37#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.07:43:51.37#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:51.37#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:43:51.49#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:43:51.49#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:43:51.49#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:43:51.49#ibcon#first serial, iclass 28, count 0 2006.231.07:43:51.49#ibcon#enter sib2, iclass 28, count 0 2006.231.07:43:51.49#ibcon#flushed, iclass 28, count 0 2006.231.07:43:51.49#ibcon#about to write, iclass 28, count 0 2006.231.07:43:51.49#ibcon#wrote, iclass 28, count 0 2006.231.07:43:51.49#ibcon#about to read 3, iclass 28, count 0 2006.231.07:43:51.51#ibcon#read 3, iclass 28, count 0 2006.231.07:43:51.51#ibcon#about to read 4, iclass 28, count 0 2006.231.07:43:51.51#ibcon#read 4, iclass 28, count 0 2006.231.07:43:51.51#ibcon#about to read 5, iclass 28, count 0 2006.231.07:43:51.51#ibcon#read 5, iclass 28, count 0 2006.231.07:43:51.51#ibcon#about to read 6, iclass 28, count 0 2006.231.07:43:51.51#ibcon#read 6, iclass 28, count 0 2006.231.07:43:51.51#ibcon#end of sib2, iclass 28, count 0 2006.231.07:43:51.51#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:43:51.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:43:51.51#ibcon#[27=USB\r\n] 2006.231.07:43:51.51#ibcon#*before write, iclass 28, count 0 2006.231.07:43:51.51#ibcon#enter sib2, iclass 28, count 0 2006.231.07:43:51.51#ibcon#flushed, iclass 28, count 0 2006.231.07:43:51.51#ibcon#about to write, iclass 28, count 0 2006.231.07:43:51.51#ibcon#wrote, iclass 28, count 0 2006.231.07:43:51.51#ibcon#about to read 3, iclass 28, count 0 2006.231.07:43:51.54#ibcon#read 3, iclass 28, count 0 2006.231.07:43:51.54#ibcon#about to read 4, iclass 28, count 0 2006.231.07:43:51.54#ibcon#read 4, iclass 28, count 0 2006.231.07:43:51.54#ibcon#about to read 5, iclass 28, count 0 2006.231.07:43:51.54#ibcon#read 5, iclass 28, count 0 2006.231.07:43:51.54#ibcon#about to read 6, iclass 28, count 0 2006.231.07:43:51.54#ibcon#read 6, iclass 28, count 0 2006.231.07:43:51.54#ibcon#end of sib2, iclass 28, count 0 2006.231.07:43:51.54#ibcon#*after write, iclass 28, count 0 2006.231.07:43:51.54#ibcon#*before return 0, iclass 28, count 0 2006.231.07:43:51.54#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:43:51.54#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:43:51.54#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:43:51.54#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:43:51.54$vc4f8/vblo=4,712.99 2006.231.07:43:51.54#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.07:43:51.54#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.07:43:51.54#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:51.54#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:43:51.54#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:43:51.54#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:43:51.54#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:43:51.54#ibcon#first serial, iclass 30, count 0 2006.231.07:43:51.54#ibcon#enter sib2, iclass 30, count 0 2006.231.07:43:51.54#ibcon#flushed, iclass 30, count 0 2006.231.07:43:51.54#ibcon#about to write, iclass 30, count 0 2006.231.07:43:51.54#ibcon#wrote, iclass 30, count 0 2006.231.07:43:51.54#ibcon#about to read 3, iclass 30, count 0 2006.231.07:43:51.56#ibcon#read 3, iclass 30, count 0 2006.231.07:43:51.56#ibcon#about to read 4, iclass 30, count 0 2006.231.07:43:51.56#ibcon#read 4, iclass 30, count 0 2006.231.07:43:51.56#ibcon#about to read 5, iclass 30, count 0 2006.231.07:43:51.56#ibcon#read 5, iclass 30, count 0 2006.231.07:43:51.56#ibcon#about to read 6, iclass 30, count 0 2006.231.07:43:51.56#ibcon#read 6, iclass 30, count 0 2006.231.07:43:51.56#ibcon#end of sib2, iclass 30, count 0 2006.231.07:43:51.56#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:43:51.56#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:43:51.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:43:51.56#ibcon#*before write, iclass 30, count 0 2006.231.07:43:51.56#ibcon#enter sib2, iclass 30, count 0 2006.231.07:43:51.56#ibcon#flushed, iclass 30, count 0 2006.231.07:43:51.56#ibcon#about to write, iclass 30, count 0 2006.231.07:43:51.56#ibcon#wrote, iclass 30, count 0 2006.231.07:43:51.56#ibcon#about to read 3, iclass 30, count 0 2006.231.07:43:51.60#ibcon#read 3, iclass 30, count 0 2006.231.07:43:51.60#ibcon#about to read 4, iclass 30, count 0 2006.231.07:43:51.60#ibcon#read 4, iclass 30, count 0 2006.231.07:43:51.60#ibcon#about to read 5, iclass 30, count 0 2006.231.07:43:51.60#ibcon#read 5, iclass 30, count 0 2006.231.07:43:51.60#ibcon#about to read 6, iclass 30, count 0 2006.231.07:43:51.60#ibcon#read 6, iclass 30, count 0 2006.231.07:43:51.60#ibcon#end of sib2, iclass 30, count 0 2006.231.07:43:51.60#ibcon#*after write, iclass 30, count 0 2006.231.07:43:51.60#ibcon#*before return 0, iclass 30, count 0 2006.231.07:43:51.60#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:43:51.60#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:43:51.60#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:43:51.60#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:43:51.60$vc4f8/vb=4,4 2006.231.07:43:51.60#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.07:43:51.60#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.07:43:51.60#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:51.60#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:43:51.66#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:43:51.66#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:43:51.66#ibcon#enter wrdev, iclass 32, count 2 2006.231.07:43:51.66#ibcon#first serial, iclass 32, count 2 2006.231.07:43:51.66#ibcon#enter sib2, iclass 32, count 2 2006.231.07:43:51.66#ibcon#flushed, iclass 32, count 2 2006.231.07:43:51.66#ibcon#about to write, iclass 32, count 2 2006.231.07:43:51.66#ibcon#wrote, iclass 32, count 2 2006.231.07:43:51.66#ibcon#about to read 3, iclass 32, count 2 2006.231.07:43:51.68#ibcon#read 3, iclass 32, count 2 2006.231.07:43:51.68#ibcon#about to read 4, iclass 32, count 2 2006.231.07:43:51.68#ibcon#read 4, iclass 32, count 2 2006.231.07:43:51.68#ibcon#about to read 5, iclass 32, count 2 2006.231.07:43:51.68#ibcon#read 5, iclass 32, count 2 2006.231.07:43:51.68#ibcon#about to read 6, iclass 32, count 2 2006.231.07:43:51.68#ibcon#read 6, iclass 32, count 2 2006.231.07:43:51.68#ibcon#end of sib2, iclass 32, count 2 2006.231.07:43:51.68#ibcon#*mode == 0, iclass 32, count 2 2006.231.07:43:51.68#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.07:43:51.68#ibcon#[27=AT04-04\r\n] 2006.231.07:43:51.68#ibcon#*before write, iclass 32, count 2 2006.231.07:43:51.68#ibcon#enter sib2, iclass 32, count 2 2006.231.07:43:51.68#ibcon#flushed, iclass 32, count 2 2006.231.07:43:51.68#ibcon#about to write, iclass 32, count 2 2006.231.07:43:51.68#ibcon#wrote, iclass 32, count 2 2006.231.07:43:51.68#ibcon#about to read 3, iclass 32, count 2 2006.231.07:43:51.71#ibcon#read 3, iclass 32, count 2 2006.231.07:43:51.71#ibcon#about to read 4, iclass 32, count 2 2006.231.07:43:51.71#ibcon#read 4, iclass 32, count 2 2006.231.07:43:51.71#ibcon#about to read 5, iclass 32, count 2 2006.231.07:43:51.71#ibcon#read 5, iclass 32, count 2 2006.231.07:43:51.71#ibcon#about to read 6, iclass 32, count 2 2006.231.07:43:51.71#ibcon#read 6, iclass 32, count 2 2006.231.07:43:51.71#ibcon#end of sib2, iclass 32, count 2 2006.231.07:43:51.71#ibcon#*after write, iclass 32, count 2 2006.231.07:43:51.71#ibcon#*before return 0, iclass 32, count 2 2006.231.07:43:51.71#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:43:51.71#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:43:51.71#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.07:43:51.71#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:51.71#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:43:51.83#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:43:51.83#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:43:51.83#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:43:51.83#ibcon#first serial, iclass 32, count 0 2006.231.07:43:51.83#ibcon#enter sib2, iclass 32, count 0 2006.231.07:43:51.83#ibcon#flushed, iclass 32, count 0 2006.231.07:43:51.83#ibcon#about to write, iclass 32, count 0 2006.231.07:43:51.83#ibcon#wrote, iclass 32, count 0 2006.231.07:43:51.83#ibcon#about to read 3, iclass 32, count 0 2006.231.07:43:51.85#ibcon#read 3, iclass 32, count 0 2006.231.07:43:51.85#ibcon#about to read 4, iclass 32, count 0 2006.231.07:43:51.85#ibcon#read 4, iclass 32, count 0 2006.231.07:43:51.85#ibcon#about to read 5, iclass 32, count 0 2006.231.07:43:51.85#ibcon#read 5, iclass 32, count 0 2006.231.07:43:51.85#ibcon#about to read 6, iclass 32, count 0 2006.231.07:43:51.85#ibcon#read 6, iclass 32, count 0 2006.231.07:43:51.85#ibcon#end of sib2, iclass 32, count 0 2006.231.07:43:51.85#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:43:51.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:43:51.85#ibcon#[27=USB\r\n] 2006.231.07:43:51.85#ibcon#*before write, iclass 32, count 0 2006.231.07:43:51.85#ibcon#enter sib2, iclass 32, count 0 2006.231.07:43:51.85#ibcon#flushed, iclass 32, count 0 2006.231.07:43:51.85#ibcon#about to write, iclass 32, count 0 2006.231.07:43:51.85#ibcon#wrote, iclass 32, count 0 2006.231.07:43:51.85#ibcon#about to read 3, iclass 32, count 0 2006.231.07:43:51.88#ibcon#read 3, iclass 32, count 0 2006.231.07:43:51.88#ibcon#about to read 4, iclass 32, count 0 2006.231.07:43:51.88#ibcon#read 4, iclass 32, count 0 2006.231.07:43:51.88#ibcon#about to read 5, iclass 32, count 0 2006.231.07:43:51.88#ibcon#read 5, iclass 32, count 0 2006.231.07:43:51.88#ibcon#about to read 6, iclass 32, count 0 2006.231.07:43:51.88#ibcon#read 6, iclass 32, count 0 2006.231.07:43:51.88#ibcon#end of sib2, iclass 32, count 0 2006.231.07:43:51.88#ibcon#*after write, iclass 32, count 0 2006.231.07:43:51.88#ibcon#*before return 0, iclass 32, count 0 2006.231.07:43:51.88#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:43:51.88#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:43:51.88#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:43:51.88#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:43:51.88$vc4f8/vblo=5,744.99 2006.231.07:43:51.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.07:43:51.88#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.07:43:51.88#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:51.88#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:43:51.88#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:43:51.88#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:43:51.88#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:43:51.88#ibcon#first serial, iclass 34, count 0 2006.231.07:43:51.88#ibcon#enter sib2, iclass 34, count 0 2006.231.07:43:51.88#ibcon#flushed, iclass 34, count 0 2006.231.07:43:51.88#ibcon#about to write, iclass 34, count 0 2006.231.07:43:51.88#ibcon#wrote, iclass 34, count 0 2006.231.07:43:51.88#ibcon#about to read 3, iclass 34, count 0 2006.231.07:43:51.90#ibcon#read 3, iclass 34, count 0 2006.231.07:43:51.90#ibcon#about to read 4, iclass 34, count 0 2006.231.07:43:51.90#ibcon#read 4, iclass 34, count 0 2006.231.07:43:51.90#ibcon#about to read 5, iclass 34, count 0 2006.231.07:43:51.90#ibcon#read 5, iclass 34, count 0 2006.231.07:43:51.90#ibcon#about to read 6, iclass 34, count 0 2006.231.07:43:51.90#ibcon#read 6, iclass 34, count 0 2006.231.07:43:51.90#ibcon#end of sib2, iclass 34, count 0 2006.231.07:43:51.90#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:43:51.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:43:51.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:43:51.90#ibcon#*before write, iclass 34, count 0 2006.231.07:43:51.90#ibcon#enter sib2, iclass 34, count 0 2006.231.07:43:51.90#ibcon#flushed, iclass 34, count 0 2006.231.07:43:51.90#ibcon#about to write, iclass 34, count 0 2006.231.07:43:51.90#ibcon#wrote, iclass 34, count 0 2006.231.07:43:51.90#ibcon#about to read 3, iclass 34, count 0 2006.231.07:43:51.94#ibcon#read 3, iclass 34, count 0 2006.231.07:43:51.94#ibcon#about to read 4, iclass 34, count 0 2006.231.07:43:51.94#ibcon#read 4, iclass 34, count 0 2006.231.07:43:51.94#ibcon#about to read 5, iclass 34, count 0 2006.231.07:43:51.94#ibcon#read 5, iclass 34, count 0 2006.231.07:43:51.94#ibcon#about to read 6, iclass 34, count 0 2006.231.07:43:51.94#ibcon#read 6, iclass 34, count 0 2006.231.07:43:51.94#ibcon#end of sib2, iclass 34, count 0 2006.231.07:43:51.94#ibcon#*after write, iclass 34, count 0 2006.231.07:43:51.94#ibcon#*before return 0, iclass 34, count 0 2006.231.07:43:51.94#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:43:51.94#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:43:51.94#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:43:51.94#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:43:51.94$vc4f8/vb=5,3 2006.231.07:43:51.94#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.07:43:51.94#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.07:43:51.94#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:51.94#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:43:52.00#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:43:52.00#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:43:52.00#ibcon#enter wrdev, iclass 36, count 2 2006.231.07:43:52.00#ibcon#first serial, iclass 36, count 2 2006.231.07:43:52.00#ibcon#enter sib2, iclass 36, count 2 2006.231.07:43:52.00#ibcon#flushed, iclass 36, count 2 2006.231.07:43:52.00#ibcon#about to write, iclass 36, count 2 2006.231.07:43:52.00#ibcon#wrote, iclass 36, count 2 2006.231.07:43:52.00#ibcon#about to read 3, iclass 36, count 2 2006.231.07:43:52.02#ibcon#read 3, iclass 36, count 2 2006.231.07:43:52.02#ibcon#about to read 4, iclass 36, count 2 2006.231.07:43:52.02#ibcon#read 4, iclass 36, count 2 2006.231.07:43:52.02#ibcon#about to read 5, iclass 36, count 2 2006.231.07:43:52.02#ibcon#read 5, iclass 36, count 2 2006.231.07:43:52.02#ibcon#about to read 6, iclass 36, count 2 2006.231.07:43:52.02#ibcon#read 6, iclass 36, count 2 2006.231.07:43:52.02#ibcon#end of sib2, iclass 36, count 2 2006.231.07:43:52.02#ibcon#*mode == 0, iclass 36, count 2 2006.231.07:43:52.02#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.07:43:52.02#ibcon#[27=AT05-03\r\n] 2006.231.07:43:52.02#ibcon#*before write, iclass 36, count 2 2006.231.07:43:52.02#ibcon#enter sib2, iclass 36, count 2 2006.231.07:43:52.02#ibcon#flushed, iclass 36, count 2 2006.231.07:43:52.02#ibcon#about to write, iclass 36, count 2 2006.231.07:43:52.02#ibcon#wrote, iclass 36, count 2 2006.231.07:43:52.02#ibcon#about to read 3, iclass 36, count 2 2006.231.07:43:52.05#ibcon#read 3, iclass 36, count 2 2006.231.07:43:52.05#ibcon#about to read 4, iclass 36, count 2 2006.231.07:43:52.05#ibcon#read 4, iclass 36, count 2 2006.231.07:43:52.05#ibcon#about to read 5, iclass 36, count 2 2006.231.07:43:52.05#ibcon#read 5, iclass 36, count 2 2006.231.07:43:52.05#ibcon#about to read 6, iclass 36, count 2 2006.231.07:43:52.05#ibcon#read 6, iclass 36, count 2 2006.231.07:43:52.05#ibcon#end of sib2, iclass 36, count 2 2006.231.07:43:52.05#ibcon#*after write, iclass 36, count 2 2006.231.07:43:52.05#ibcon#*before return 0, iclass 36, count 2 2006.231.07:43:52.05#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:43:52.05#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:43:52.05#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.07:43:52.05#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:52.05#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:43:52.17#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:43:52.17#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:43:52.17#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:43:52.17#ibcon#first serial, iclass 36, count 0 2006.231.07:43:52.17#ibcon#enter sib2, iclass 36, count 0 2006.231.07:43:52.17#ibcon#flushed, iclass 36, count 0 2006.231.07:43:52.17#ibcon#about to write, iclass 36, count 0 2006.231.07:43:52.17#ibcon#wrote, iclass 36, count 0 2006.231.07:43:52.17#ibcon#about to read 3, iclass 36, count 0 2006.231.07:43:52.19#ibcon#read 3, iclass 36, count 0 2006.231.07:43:52.19#ibcon#about to read 4, iclass 36, count 0 2006.231.07:43:52.19#ibcon#read 4, iclass 36, count 0 2006.231.07:43:52.19#ibcon#about to read 5, iclass 36, count 0 2006.231.07:43:52.19#ibcon#read 5, iclass 36, count 0 2006.231.07:43:52.19#ibcon#about to read 6, iclass 36, count 0 2006.231.07:43:52.19#ibcon#read 6, iclass 36, count 0 2006.231.07:43:52.19#ibcon#end of sib2, iclass 36, count 0 2006.231.07:43:52.19#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:43:52.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:43:52.19#ibcon#[27=USB\r\n] 2006.231.07:43:52.19#ibcon#*before write, iclass 36, count 0 2006.231.07:43:52.19#ibcon#enter sib2, iclass 36, count 0 2006.231.07:43:52.19#ibcon#flushed, iclass 36, count 0 2006.231.07:43:52.19#ibcon#about to write, iclass 36, count 0 2006.231.07:43:52.19#ibcon#wrote, iclass 36, count 0 2006.231.07:43:52.19#ibcon#about to read 3, iclass 36, count 0 2006.231.07:43:52.22#ibcon#read 3, iclass 36, count 0 2006.231.07:43:52.22#ibcon#about to read 4, iclass 36, count 0 2006.231.07:43:52.22#ibcon#read 4, iclass 36, count 0 2006.231.07:43:52.22#ibcon#about to read 5, iclass 36, count 0 2006.231.07:43:52.22#ibcon#read 5, iclass 36, count 0 2006.231.07:43:52.22#ibcon#about to read 6, iclass 36, count 0 2006.231.07:43:52.22#ibcon#read 6, iclass 36, count 0 2006.231.07:43:52.22#ibcon#end of sib2, iclass 36, count 0 2006.231.07:43:52.22#ibcon#*after write, iclass 36, count 0 2006.231.07:43:52.22#ibcon#*before return 0, iclass 36, count 0 2006.231.07:43:52.22#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:43:52.22#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:43:52.22#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:43:52.22#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:43:52.22$vc4f8/vblo=6,752.99 2006.231.07:43:52.22#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.07:43:52.22#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.07:43:52.22#ibcon#ireg 17 cls_cnt 0 2006.231.07:43:52.22#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:43:52.22#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:43:52.22#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:43:52.22#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:43:52.22#ibcon#first serial, iclass 38, count 0 2006.231.07:43:52.22#ibcon#enter sib2, iclass 38, count 0 2006.231.07:43:52.22#ibcon#flushed, iclass 38, count 0 2006.231.07:43:52.22#ibcon#about to write, iclass 38, count 0 2006.231.07:43:52.22#ibcon#wrote, iclass 38, count 0 2006.231.07:43:52.22#ibcon#about to read 3, iclass 38, count 0 2006.231.07:43:52.24#ibcon#read 3, iclass 38, count 0 2006.231.07:43:52.24#ibcon#about to read 4, iclass 38, count 0 2006.231.07:43:52.24#ibcon#read 4, iclass 38, count 0 2006.231.07:43:52.24#ibcon#about to read 5, iclass 38, count 0 2006.231.07:43:52.24#ibcon#read 5, iclass 38, count 0 2006.231.07:43:52.24#ibcon#about to read 6, iclass 38, count 0 2006.231.07:43:52.24#ibcon#read 6, iclass 38, count 0 2006.231.07:43:52.24#ibcon#end of sib2, iclass 38, count 0 2006.231.07:43:52.24#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:43:52.24#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:43:52.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:43:52.24#ibcon#*before write, iclass 38, count 0 2006.231.07:43:52.24#ibcon#enter sib2, iclass 38, count 0 2006.231.07:43:52.24#ibcon#flushed, iclass 38, count 0 2006.231.07:43:52.24#ibcon#about to write, iclass 38, count 0 2006.231.07:43:52.24#ibcon#wrote, iclass 38, count 0 2006.231.07:43:52.24#ibcon#about to read 3, iclass 38, count 0 2006.231.07:43:52.28#ibcon#read 3, iclass 38, count 0 2006.231.07:43:52.28#ibcon#about to read 4, iclass 38, count 0 2006.231.07:43:52.28#ibcon#read 4, iclass 38, count 0 2006.231.07:43:52.28#ibcon#about to read 5, iclass 38, count 0 2006.231.07:43:52.28#ibcon#read 5, iclass 38, count 0 2006.231.07:43:52.28#ibcon#about to read 6, iclass 38, count 0 2006.231.07:43:52.28#ibcon#read 6, iclass 38, count 0 2006.231.07:43:52.28#ibcon#end of sib2, iclass 38, count 0 2006.231.07:43:52.28#ibcon#*after write, iclass 38, count 0 2006.231.07:43:52.28#ibcon#*before return 0, iclass 38, count 0 2006.231.07:43:52.28#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:43:52.28#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:43:52.28#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:43:52.28#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:43:52.28$vc4f8/vb=6,4 2006.231.07:43:52.28#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.07:43:52.28#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.07:43:52.28#ibcon#ireg 11 cls_cnt 2 2006.231.07:43:52.28#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:43:52.34#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:43:52.34#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:43:52.34#ibcon#enter wrdev, iclass 40, count 2 2006.231.07:43:52.34#ibcon#first serial, iclass 40, count 2 2006.231.07:43:52.34#ibcon#enter sib2, iclass 40, count 2 2006.231.07:43:52.34#ibcon#flushed, iclass 40, count 2 2006.231.07:43:52.34#ibcon#about to write, iclass 40, count 2 2006.231.07:43:52.34#ibcon#wrote, iclass 40, count 2 2006.231.07:43:52.34#ibcon#about to read 3, iclass 40, count 2 2006.231.07:43:52.36#ibcon#read 3, iclass 40, count 2 2006.231.07:43:52.36#ibcon#about to read 4, iclass 40, count 2 2006.231.07:43:52.36#ibcon#read 4, iclass 40, count 2 2006.231.07:43:52.36#ibcon#about to read 5, iclass 40, count 2 2006.231.07:43:52.36#ibcon#read 5, iclass 40, count 2 2006.231.07:43:52.36#ibcon#about to read 6, iclass 40, count 2 2006.231.07:43:52.36#ibcon#read 6, iclass 40, count 2 2006.231.07:43:52.36#ibcon#end of sib2, iclass 40, count 2 2006.231.07:43:52.36#ibcon#*mode == 0, iclass 40, count 2 2006.231.07:43:52.36#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.07:43:52.36#ibcon#[27=AT06-04\r\n] 2006.231.07:43:52.36#ibcon#*before write, iclass 40, count 2 2006.231.07:43:52.36#ibcon#enter sib2, iclass 40, count 2 2006.231.07:43:52.36#ibcon#flushed, iclass 40, count 2 2006.231.07:43:52.36#ibcon#about to write, iclass 40, count 2 2006.231.07:43:52.36#ibcon#wrote, iclass 40, count 2 2006.231.07:43:52.36#ibcon#about to read 3, iclass 40, count 2 2006.231.07:43:52.39#ibcon#read 3, iclass 40, count 2 2006.231.07:43:52.39#ibcon#about to read 4, iclass 40, count 2 2006.231.07:43:52.39#ibcon#read 4, iclass 40, count 2 2006.231.07:43:52.39#ibcon#about to read 5, iclass 40, count 2 2006.231.07:43:52.39#ibcon#read 5, iclass 40, count 2 2006.231.07:43:52.39#ibcon#about to read 6, iclass 40, count 2 2006.231.07:43:52.39#ibcon#read 6, iclass 40, count 2 2006.231.07:43:52.39#ibcon#end of sib2, iclass 40, count 2 2006.231.07:43:52.39#ibcon#*after write, iclass 40, count 2 2006.231.07:43:52.39#ibcon#*before return 0, iclass 40, count 2 2006.231.07:43:52.39#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:43:52.39#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:43:52.39#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.07:43:52.39#ibcon#ireg 7 cls_cnt 0 2006.231.07:43:52.39#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:43:52.51#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:43:52.51#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:43:52.51#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:43:52.51#ibcon#first serial, iclass 40, count 0 2006.231.07:43:52.51#ibcon#enter sib2, iclass 40, count 0 2006.231.07:43:52.51#ibcon#flushed, iclass 40, count 0 2006.231.07:43:52.51#ibcon#about to write, iclass 40, count 0 2006.231.07:43:52.51#ibcon#wrote, iclass 40, count 0 2006.231.07:43:52.51#ibcon#about to read 3, iclass 40, count 0 2006.231.07:43:52.53#ibcon#read 3, iclass 40, count 0 2006.231.07:43:52.53#ibcon#about to read 4, iclass 40, count 0 2006.231.07:43:52.53#ibcon#read 4, iclass 40, count 0 2006.231.07:43:52.53#ibcon#about to read 5, iclass 40, count 0 2006.231.07:43:52.53#ibcon#read 5, iclass 40, count 0 2006.231.07:43:52.53#ibcon#about to read 6, iclass 40, count 0 2006.231.07:43:52.53#ibcon#read 6, iclass 40, count 0 2006.231.07:43:52.53#ibcon#end of sib2, iclass 40, count 0 2006.231.07:43:52.53#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:43:52.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:43:52.53#ibcon#[27=USB\r\n] 2006.231.07:43:52.53#ibcon#*before write, iclass 40, count 0 2006.231.07:43:52.53#ibcon#enter sib2, iclass 40, count 0 2006.231.07:43:52.53#ibcon#flushed, iclass 40, count 0 2006.231.07:43:52.53#ibcon#about to write, iclass 40, count 0 2006.231.07:43:52.53#ibcon#wrote, iclass 40, count 0 2006.231.07:43:52.53#ibcon#about to read 3, iclass 40, count 0 2006.231.07:43:52.56#ibcon#read 3, iclass 40, count 0 2006.231.07:43:52.56#ibcon#about to read 4, iclass 40, count 0 2006.231.07:43:52.56#ibcon#read 4, iclass 40, count 0 2006.231.07:43:52.56#ibcon#about to read 5, iclass 40, count 0 2006.231.07:43:52.56#ibcon#read 5, iclass 40, count 0 2006.231.07:43:52.56#ibcon#about to read 6, iclass 40, count 0 2006.231.07:43:52.56#ibcon#read 6, iclass 40, count 0 2006.231.07:43:52.56#ibcon#end of sib2, iclass 40, count 0 2006.231.07:43:52.56#ibcon#*after write, iclass 40, count 0 2006.231.07:43:52.56#ibcon#*before return 0, iclass 40, count 0 2006.231.07:43:52.56#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:43:52.56#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:43:52.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:43:52.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:43:52.56$vc4f8/vabw=wide 2006.231.07:43:52.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.07:43:52.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.07:43:52.56#ibcon#ireg 8 cls_cnt 0 2006.231.07:43:52.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:43:52.56#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:43:52.56#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:43:52.56#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:43:52.56#ibcon#first serial, iclass 4, count 0 2006.231.07:43:52.56#ibcon#enter sib2, iclass 4, count 0 2006.231.07:43:52.56#ibcon#flushed, iclass 4, count 0 2006.231.07:43:52.56#ibcon#about to write, iclass 4, count 0 2006.231.07:43:52.56#ibcon#wrote, iclass 4, count 0 2006.231.07:43:52.56#ibcon#about to read 3, iclass 4, count 0 2006.231.07:43:52.58#ibcon#read 3, iclass 4, count 0 2006.231.07:43:52.58#ibcon#about to read 4, iclass 4, count 0 2006.231.07:43:52.58#ibcon#read 4, iclass 4, count 0 2006.231.07:43:52.58#ibcon#about to read 5, iclass 4, count 0 2006.231.07:43:52.58#ibcon#read 5, iclass 4, count 0 2006.231.07:43:52.58#ibcon#about to read 6, iclass 4, count 0 2006.231.07:43:52.58#ibcon#read 6, iclass 4, count 0 2006.231.07:43:52.58#ibcon#end of sib2, iclass 4, count 0 2006.231.07:43:52.58#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:43:52.58#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:43:52.58#ibcon#[25=BW32\r\n] 2006.231.07:43:52.58#ibcon#*before write, iclass 4, count 0 2006.231.07:43:52.58#ibcon#enter sib2, iclass 4, count 0 2006.231.07:43:52.58#ibcon#flushed, iclass 4, count 0 2006.231.07:43:52.58#ibcon#about to write, iclass 4, count 0 2006.231.07:43:52.58#ibcon#wrote, iclass 4, count 0 2006.231.07:43:52.58#ibcon#about to read 3, iclass 4, count 0 2006.231.07:43:52.61#ibcon#read 3, iclass 4, count 0 2006.231.07:43:52.61#ibcon#about to read 4, iclass 4, count 0 2006.231.07:43:52.61#ibcon#read 4, iclass 4, count 0 2006.231.07:43:52.61#ibcon#about to read 5, iclass 4, count 0 2006.231.07:43:52.61#ibcon#read 5, iclass 4, count 0 2006.231.07:43:52.61#ibcon#about to read 6, iclass 4, count 0 2006.231.07:43:52.61#ibcon#read 6, iclass 4, count 0 2006.231.07:43:52.61#ibcon#end of sib2, iclass 4, count 0 2006.231.07:43:52.61#ibcon#*after write, iclass 4, count 0 2006.231.07:43:52.61#ibcon#*before return 0, iclass 4, count 0 2006.231.07:43:52.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:43:52.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:43:52.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:43:52.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:43:52.61$vc4f8/vbbw=wide 2006.231.07:43:52.61#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.231.07:43:52.61#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.231.07:43:52.61#ibcon#ireg 8 cls_cnt 0 2006.231.07:43:52.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:43:52.68#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:43:52.68#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:43:52.68#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:43:52.68#ibcon#first serial, iclass 6, count 0 2006.231.07:43:52.68#ibcon#enter sib2, iclass 6, count 0 2006.231.07:43:52.68#ibcon#flushed, iclass 6, count 0 2006.231.07:43:52.68#ibcon#about to write, iclass 6, count 0 2006.231.07:43:52.68#ibcon#wrote, iclass 6, count 0 2006.231.07:43:52.68#ibcon#about to read 3, iclass 6, count 0 2006.231.07:43:52.70#ibcon#read 3, iclass 6, count 0 2006.231.07:43:52.70#ibcon#about to read 4, iclass 6, count 0 2006.231.07:43:52.70#ibcon#read 4, iclass 6, count 0 2006.231.07:43:52.70#ibcon#about to read 5, iclass 6, count 0 2006.231.07:43:52.70#ibcon#read 5, iclass 6, count 0 2006.231.07:43:52.70#ibcon#about to read 6, iclass 6, count 0 2006.231.07:43:52.70#ibcon#read 6, iclass 6, count 0 2006.231.07:43:52.70#ibcon#end of sib2, iclass 6, count 0 2006.231.07:43:52.70#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:43:52.70#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:43:52.70#ibcon#[27=BW32\r\n] 2006.231.07:43:52.70#ibcon#*before write, iclass 6, count 0 2006.231.07:43:52.70#ibcon#enter sib2, iclass 6, count 0 2006.231.07:43:52.70#ibcon#flushed, iclass 6, count 0 2006.231.07:43:52.70#ibcon#about to write, iclass 6, count 0 2006.231.07:43:52.70#ibcon#wrote, iclass 6, count 0 2006.231.07:43:52.70#ibcon#about to read 3, iclass 6, count 0 2006.231.07:43:52.73#ibcon#read 3, iclass 6, count 0 2006.231.07:43:52.73#ibcon#about to read 4, iclass 6, count 0 2006.231.07:43:52.73#ibcon#read 4, iclass 6, count 0 2006.231.07:43:52.73#ibcon#about to read 5, iclass 6, count 0 2006.231.07:43:52.73#ibcon#read 5, iclass 6, count 0 2006.231.07:43:52.73#ibcon#about to read 6, iclass 6, count 0 2006.231.07:43:52.73#ibcon#read 6, iclass 6, count 0 2006.231.07:43:52.73#ibcon#end of sib2, iclass 6, count 0 2006.231.07:43:52.73#ibcon#*after write, iclass 6, count 0 2006.231.07:43:52.73#ibcon#*before return 0, iclass 6, count 0 2006.231.07:43:52.73#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:43:52.73#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:43:52.73#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:43:52.73#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:43:52.73$4f8m12a/ifd4f 2006.231.07:43:52.73$ifd4f/lo= 2006.231.07:43:52.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:43:52.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:43:52.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:43:52.73$ifd4f/patch= 2006.231.07:43:52.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:43:52.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:43:52.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:43:52.73$4f8m12a/"form=m,16.000,1:2 2006.231.07:43:52.73$4f8m12a/"tpicd 2006.231.07:43:52.73$4f8m12a/echo=off 2006.231.07:43:52.73$4f8m12a/xlog=off 2006.231.07:43:52.73:!2006.231.07:44:40 2006.231.07:43:52.77#abcon#<5=/07 3.0 7.2 30.63 831004.4\r\n> 2006.231.07:44:16.13#trakl#Source acquired 2006.231.07:44:16.13#flagr#flagr/antenna,acquired 2006.231.07:44:40.00:preob 2006.231.07:44:41.13/onsource/TRACKING 2006.231.07:44:41.13:!2006.231.07:44:50 2006.231.07:44:50.00:data_valid=on 2006.231.07:44:50.00:midob 2006.231.07:44:50.14/onsource/TRACKING 2006.231.07:44:50.14/wx/30.62,1004.4,84 2006.231.07:44:50.21/cable/+6.3721E-03 2006.231.07:44:51.30/va/01,08,usb,yes,30,32 2006.231.07:44:51.30/va/02,07,usb,yes,30,32 2006.231.07:44:51.30/va/03,08,usb,yes,23,23 2006.231.07:44:51.30/va/04,07,usb,yes,31,34 2006.231.07:44:51.30/va/05,07,usb,yes,34,36 2006.231.07:44:51.30/va/06,06,usb,yes,33,33 2006.231.07:44:51.30/va/07,06,usb,yes,34,34 2006.231.07:44:51.30/va/08,06,usb,yes,36,36 2006.231.07:44:51.53/valo/01,532.99,yes,locked 2006.231.07:44:51.53/valo/02,572.99,yes,locked 2006.231.07:44:51.53/valo/03,672.99,yes,locked 2006.231.07:44:51.53/valo/04,832.99,yes,locked 2006.231.07:44:51.53/valo/05,652.99,yes,locked 2006.231.07:44:51.53/valo/06,772.99,yes,locked 2006.231.07:44:51.53/valo/07,832.99,yes,locked 2006.231.07:44:51.53/valo/08,852.99,yes,locked 2006.231.07:44:52.62/vb/01,04,usb,yes,31,29 2006.231.07:44:52.62/vb/02,04,usb,yes,32,34 2006.231.07:44:52.62/vb/03,04,usb,yes,29,33 2006.231.07:44:52.62/vb/04,04,usb,yes,30,30 2006.231.07:44:52.62/vb/05,03,usb,yes,35,40 2006.231.07:44:52.62/vb/06,04,usb,yes,29,32 2006.231.07:44:52.62/vb/07,04,usb,yes,31,31 2006.231.07:44:52.62/vb/08,04,usb,yes,29,32 2006.231.07:44:52.85/vblo/01,632.99,yes,locked 2006.231.07:44:52.85/vblo/02,640.99,yes,locked 2006.231.07:44:52.85/vblo/03,656.99,yes,locked 2006.231.07:44:52.85/vblo/04,712.99,yes,locked 2006.231.07:44:52.85/vblo/05,744.99,yes,locked 2006.231.07:44:52.85/vblo/06,752.99,yes,locked 2006.231.07:44:52.85/vblo/07,734.99,yes,locked 2006.231.07:44:52.85/vblo/08,744.99,yes,locked 2006.231.07:44:53.00/vabw/8 2006.231.07:44:53.15/vbbw/8 2006.231.07:44:53.27/xfe/off,on,12.5 2006.231.07:44:53.65/ifatt/23,28,28,28 2006.231.07:44:54.08/fmout-gps/S +4.41E-07 2006.231.07:44:54.12:!2006.231.07:46:00 2006.231.07:45:23.14#trakl#Off source 2006.231.07:45:23.14?ERROR st -7 Antenna off-source! 2006.231.07:45:23.14#trakl#az 258.445 el 36.143 azerr*cos(el) 0.0179 elerr -0.0057 2006.231.07:45:25.14#flagr#flagr/antenna,off-source 2006.231.07:45:29.14#trakl#Source re-acquired 2006.231.07:45:31.14#flagr#flagr/antenna,re-acquired 2006.231.07:46:00.00:data_valid=off 2006.231.07:46:00.00:postob 2006.231.07:46:00.13/cable/+6.3721E-03 2006.231.07:46:00.13/wx/30.61,1004.4,84 2006.231.07:46:01.08/fmout-gps/S +4.42E-07 2006.231.07:46:01.08:scan_name=231-0747,k06231,60 2006.231.07:46:01.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.231.07:46:02.14#flagr#flagr/antenna,new-source 2006.231.07:46:02.14:checkk5 2006.231.07:46:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:46:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:46:03.23/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:46:03.60/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:46:03.97/chk_obsdata//k5ts1/T2310744??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.231.07:46:04.33/chk_obsdata//k5ts2/T2310744??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.231.07:46:04.70/chk_obsdata//k5ts3/T2310744??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.231.07:46:05.07/chk_obsdata//k5ts4/T2310744??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.231.07:46:05.78/k5log//k5ts1_log_newline 2006.231.07:46:06.50/k5log//k5ts2_log_newline 2006.231.07:46:07.20/k5log//k5ts3_log_newline 2006.231.07:46:07.90/k5log//k5ts4_log_newline 2006.231.07:46:07.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:46:07.92:4f8m12a=1 2006.231.07:46:07.92$4f8m12a/echo=on 2006.231.07:46:07.92$4f8m12a/pcalon 2006.231.07:46:07.92$pcalon/"no phase cal control is implemented here 2006.231.07:46:07.92$4f8m12a/"tpicd=stop 2006.231.07:46:07.92$4f8m12a/vc4f8 2006.231.07:46:07.92$vc4f8/valo=1,532.99 2006.231.07:46:07.92#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.07:46:07.92#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.07:46:07.92#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:07.92#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:46:07.92#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:46:07.92#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:46:07.92#ibcon#enter wrdev, iclass 33, count 0 2006.231.07:46:07.92#ibcon#first serial, iclass 33, count 0 2006.231.07:46:07.92#ibcon#enter sib2, iclass 33, count 0 2006.231.07:46:07.92#ibcon#flushed, iclass 33, count 0 2006.231.07:46:07.92#ibcon#about to write, iclass 33, count 0 2006.231.07:46:07.92#ibcon#wrote, iclass 33, count 0 2006.231.07:46:07.92#ibcon#about to read 3, iclass 33, count 0 2006.231.07:46:07.96#ibcon#read 3, iclass 33, count 0 2006.231.07:46:07.96#ibcon#about to read 4, iclass 33, count 0 2006.231.07:46:07.96#ibcon#read 4, iclass 33, count 0 2006.231.07:46:07.96#ibcon#about to read 5, iclass 33, count 0 2006.231.07:46:07.96#ibcon#read 5, iclass 33, count 0 2006.231.07:46:07.96#ibcon#about to read 6, iclass 33, count 0 2006.231.07:46:07.96#ibcon#read 6, iclass 33, count 0 2006.231.07:46:07.96#ibcon#end of sib2, iclass 33, count 0 2006.231.07:46:07.96#ibcon#*mode == 0, iclass 33, count 0 2006.231.07:46:07.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.07:46:07.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:46:07.96#ibcon#*before write, iclass 33, count 0 2006.231.07:46:07.96#ibcon#enter sib2, iclass 33, count 0 2006.231.07:46:07.96#ibcon#flushed, iclass 33, count 0 2006.231.07:46:07.96#ibcon#about to write, iclass 33, count 0 2006.231.07:46:07.96#ibcon#wrote, iclass 33, count 0 2006.231.07:46:07.96#ibcon#about to read 3, iclass 33, count 0 2006.231.07:46:08.01#ibcon#read 3, iclass 33, count 0 2006.231.07:46:08.01#ibcon#about to read 4, iclass 33, count 0 2006.231.07:46:08.01#ibcon#read 4, iclass 33, count 0 2006.231.07:46:08.01#ibcon#about to read 5, iclass 33, count 0 2006.231.07:46:08.01#ibcon#read 5, iclass 33, count 0 2006.231.07:46:08.01#ibcon#about to read 6, iclass 33, count 0 2006.231.07:46:08.01#ibcon#read 6, iclass 33, count 0 2006.231.07:46:08.01#ibcon#end of sib2, iclass 33, count 0 2006.231.07:46:08.01#ibcon#*after write, iclass 33, count 0 2006.231.07:46:08.01#ibcon#*before return 0, iclass 33, count 0 2006.231.07:46:08.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:46:08.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:46:08.01#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.07:46:08.01#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.07:46:08.01$vc4f8/va=1,8 2006.231.07:46:08.01#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.07:46:08.01#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.07:46:08.01#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:08.01#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:46:08.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:46:08.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:46:08.01#ibcon#enter wrdev, iclass 35, count 2 2006.231.07:46:08.01#ibcon#first serial, iclass 35, count 2 2006.231.07:46:08.01#ibcon#enter sib2, iclass 35, count 2 2006.231.07:46:08.01#ibcon#flushed, iclass 35, count 2 2006.231.07:46:08.01#ibcon#about to write, iclass 35, count 2 2006.231.07:46:08.01#ibcon#wrote, iclass 35, count 2 2006.231.07:46:08.01#ibcon#about to read 3, iclass 35, count 2 2006.231.07:46:08.03#ibcon#read 3, iclass 35, count 2 2006.231.07:46:08.03#ibcon#about to read 4, iclass 35, count 2 2006.231.07:46:08.03#ibcon#read 4, iclass 35, count 2 2006.231.07:46:08.03#ibcon#about to read 5, iclass 35, count 2 2006.231.07:46:08.03#ibcon#read 5, iclass 35, count 2 2006.231.07:46:08.03#ibcon#about to read 6, iclass 35, count 2 2006.231.07:46:08.03#ibcon#read 6, iclass 35, count 2 2006.231.07:46:08.03#ibcon#end of sib2, iclass 35, count 2 2006.231.07:46:08.03#ibcon#*mode == 0, iclass 35, count 2 2006.231.07:46:08.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.07:46:08.03#ibcon#[25=AT01-08\r\n] 2006.231.07:46:08.03#ibcon#*before write, iclass 35, count 2 2006.231.07:46:08.03#ibcon#enter sib2, iclass 35, count 2 2006.231.07:46:08.03#ibcon#flushed, iclass 35, count 2 2006.231.07:46:08.03#ibcon#about to write, iclass 35, count 2 2006.231.07:46:08.03#ibcon#wrote, iclass 35, count 2 2006.231.07:46:08.03#ibcon#about to read 3, iclass 35, count 2 2006.231.07:46:08.06#ibcon#read 3, iclass 35, count 2 2006.231.07:46:08.06#ibcon#about to read 4, iclass 35, count 2 2006.231.07:46:08.06#ibcon#read 4, iclass 35, count 2 2006.231.07:46:08.06#ibcon#about to read 5, iclass 35, count 2 2006.231.07:46:08.06#ibcon#read 5, iclass 35, count 2 2006.231.07:46:08.06#ibcon#about to read 6, iclass 35, count 2 2006.231.07:46:08.06#ibcon#read 6, iclass 35, count 2 2006.231.07:46:08.06#ibcon#end of sib2, iclass 35, count 2 2006.231.07:46:08.06#ibcon#*after write, iclass 35, count 2 2006.231.07:46:08.06#ibcon#*before return 0, iclass 35, count 2 2006.231.07:46:08.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:46:08.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:46:08.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.07:46:08.06#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:08.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:46:08.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:46:08.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:46:08.18#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:46:08.18#ibcon#first serial, iclass 35, count 0 2006.231.07:46:08.18#ibcon#enter sib2, iclass 35, count 0 2006.231.07:46:08.18#ibcon#flushed, iclass 35, count 0 2006.231.07:46:08.18#ibcon#about to write, iclass 35, count 0 2006.231.07:46:08.18#ibcon#wrote, iclass 35, count 0 2006.231.07:46:08.18#ibcon#about to read 3, iclass 35, count 0 2006.231.07:46:08.20#ibcon#read 3, iclass 35, count 0 2006.231.07:46:08.20#ibcon#about to read 4, iclass 35, count 0 2006.231.07:46:08.20#ibcon#read 4, iclass 35, count 0 2006.231.07:46:08.20#ibcon#about to read 5, iclass 35, count 0 2006.231.07:46:08.20#ibcon#read 5, iclass 35, count 0 2006.231.07:46:08.20#ibcon#about to read 6, iclass 35, count 0 2006.231.07:46:08.20#ibcon#read 6, iclass 35, count 0 2006.231.07:46:08.20#ibcon#end of sib2, iclass 35, count 0 2006.231.07:46:08.20#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:46:08.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:46:08.20#ibcon#[25=USB\r\n] 2006.231.07:46:08.20#ibcon#*before write, iclass 35, count 0 2006.231.07:46:08.20#ibcon#enter sib2, iclass 35, count 0 2006.231.07:46:08.20#ibcon#flushed, iclass 35, count 0 2006.231.07:46:08.20#ibcon#about to write, iclass 35, count 0 2006.231.07:46:08.20#ibcon#wrote, iclass 35, count 0 2006.231.07:46:08.20#ibcon#about to read 3, iclass 35, count 0 2006.231.07:46:08.23#ibcon#read 3, iclass 35, count 0 2006.231.07:46:08.23#ibcon#about to read 4, iclass 35, count 0 2006.231.07:46:08.23#ibcon#read 4, iclass 35, count 0 2006.231.07:46:08.23#ibcon#about to read 5, iclass 35, count 0 2006.231.07:46:08.23#ibcon#read 5, iclass 35, count 0 2006.231.07:46:08.23#ibcon#about to read 6, iclass 35, count 0 2006.231.07:46:08.23#ibcon#read 6, iclass 35, count 0 2006.231.07:46:08.23#ibcon#end of sib2, iclass 35, count 0 2006.231.07:46:08.23#ibcon#*after write, iclass 35, count 0 2006.231.07:46:08.23#ibcon#*before return 0, iclass 35, count 0 2006.231.07:46:08.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:46:08.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:46:08.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:46:08.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:46:08.23$vc4f8/valo=2,572.99 2006.231.07:46:08.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.07:46:08.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.07:46:08.23#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:08.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:46:08.23#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:46:08.23#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:46:08.23#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:46:08.23#ibcon#first serial, iclass 37, count 0 2006.231.07:46:08.23#ibcon#enter sib2, iclass 37, count 0 2006.231.07:46:08.23#ibcon#flushed, iclass 37, count 0 2006.231.07:46:08.23#ibcon#about to write, iclass 37, count 0 2006.231.07:46:08.23#ibcon#wrote, iclass 37, count 0 2006.231.07:46:08.23#ibcon#about to read 3, iclass 37, count 0 2006.231.07:46:08.25#ibcon#read 3, iclass 37, count 0 2006.231.07:46:08.25#ibcon#about to read 4, iclass 37, count 0 2006.231.07:46:08.25#ibcon#read 4, iclass 37, count 0 2006.231.07:46:08.25#ibcon#about to read 5, iclass 37, count 0 2006.231.07:46:08.25#ibcon#read 5, iclass 37, count 0 2006.231.07:46:08.25#ibcon#about to read 6, iclass 37, count 0 2006.231.07:46:08.25#ibcon#read 6, iclass 37, count 0 2006.231.07:46:08.25#ibcon#end of sib2, iclass 37, count 0 2006.231.07:46:08.25#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:46:08.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:46:08.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:46:08.25#ibcon#*before write, iclass 37, count 0 2006.231.07:46:08.25#ibcon#enter sib2, iclass 37, count 0 2006.231.07:46:08.25#ibcon#flushed, iclass 37, count 0 2006.231.07:46:08.25#ibcon#about to write, iclass 37, count 0 2006.231.07:46:08.25#ibcon#wrote, iclass 37, count 0 2006.231.07:46:08.25#ibcon#about to read 3, iclass 37, count 0 2006.231.07:46:08.29#ibcon#read 3, iclass 37, count 0 2006.231.07:46:08.29#ibcon#about to read 4, iclass 37, count 0 2006.231.07:46:08.29#ibcon#read 4, iclass 37, count 0 2006.231.07:46:08.29#ibcon#about to read 5, iclass 37, count 0 2006.231.07:46:08.29#ibcon#read 5, iclass 37, count 0 2006.231.07:46:08.29#ibcon#about to read 6, iclass 37, count 0 2006.231.07:46:08.29#ibcon#read 6, iclass 37, count 0 2006.231.07:46:08.29#ibcon#end of sib2, iclass 37, count 0 2006.231.07:46:08.29#ibcon#*after write, iclass 37, count 0 2006.231.07:46:08.29#ibcon#*before return 0, iclass 37, count 0 2006.231.07:46:08.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:46:08.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:46:08.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:46:08.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:46:08.29$vc4f8/va=2,7 2006.231.07:46:08.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.07:46:08.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.07:46:08.29#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:08.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:46:08.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:46:08.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:46:08.35#ibcon#enter wrdev, iclass 39, count 2 2006.231.07:46:08.35#ibcon#first serial, iclass 39, count 2 2006.231.07:46:08.35#ibcon#enter sib2, iclass 39, count 2 2006.231.07:46:08.35#ibcon#flushed, iclass 39, count 2 2006.231.07:46:08.35#ibcon#about to write, iclass 39, count 2 2006.231.07:46:08.35#ibcon#wrote, iclass 39, count 2 2006.231.07:46:08.35#ibcon#about to read 3, iclass 39, count 2 2006.231.07:46:08.37#ibcon#read 3, iclass 39, count 2 2006.231.07:46:08.37#ibcon#about to read 4, iclass 39, count 2 2006.231.07:46:08.37#ibcon#read 4, iclass 39, count 2 2006.231.07:46:08.37#ibcon#about to read 5, iclass 39, count 2 2006.231.07:46:08.37#ibcon#read 5, iclass 39, count 2 2006.231.07:46:08.37#ibcon#about to read 6, iclass 39, count 2 2006.231.07:46:08.37#ibcon#read 6, iclass 39, count 2 2006.231.07:46:08.37#ibcon#end of sib2, iclass 39, count 2 2006.231.07:46:08.37#ibcon#*mode == 0, iclass 39, count 2 2006.231.07:46:08.37#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.07:46:08.37#ibcon#[25=AT02-07\r\n] 2006.231.07:46:08.37#ibcon#*before write, iclass 39, count 2 2006.231.07:46:08.37#ibcon#enter sib2, iclass 39, count 2 2006.231.07:46:08.37#ibcon#flushed, iclass 39, count 2 2006.231.07:46:08.37#ibcon#about to write, iclass 39, count 2 2006.231.07:46:08.37#ibcon#wrote, iclass 39, count 2 2006.231.07:46:08.37#ibcon#about to read 3, iclass 39, count 2 2006.231.07:46:08.40#ibcon#read 3, iclass 39, count 2 2006.231.07:46:08.40#ibcon#about to read 4, iclass 39, count 2 2006.231.07:46:08.40#ibcon#read 4, iclass 39, count 2 2006.231.07:46:08.40#ibcon#about to read 5, iclass 39, count 2 2006.231.07:46:08.40#ibcon#read 5, iclass 39, count 2 2006.231.07:46:08.40#ibcon#about to read 6, iclass 39, count 2 2006.231.07:46:08.40#ibcon#read 6, iclass 39, count 2 2006.231.07:46:08.40#ibcon#end of sib2, iclass 39, count 2 2006.231.07:46:08.40#ibcon#*after write, iclass 39, count 2 2006.231.07:46:08.40#ibcon#*before return 0, iclass 39, count 2 2006.231.07:46:08.40#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:46:08.40#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:46:08.40#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.07:46:08.40#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:08.40#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:46:08.52#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:46:08.52#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:46:08.52#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:46:08.52#ibcon#first serial, iclass 39, count 0 2006.231.07:46:08.52#ibcon#enter sib2, iclass 39, count 0 2006.231.07:46:08.52#ibcon#flushed, iclass 39, count 0 2006.231.07:46:08.52#ibcon#about to write, iclass 39, count 0 2006.231.07:46:08.52#ibcon#wrote, iclass 39, count 0 2006.231.07:46:08.52#ibcon#about to read 3, iclass 39, count 0 2006.231.07:46:08.54#ibcon#read 3, iclass 39, count 0 2006.231.07:46:08.54#ibcon#about to read 4, iclass 39, count 0 2006.231.07:46:08.54#ibcon#read 4, iclass 39, count 0 2006.231.07:46:08.54#ibcon#about to read 5, iclass 39, count 0 2006.231.07:46:08.54#ibcon#read 5, iclass 39, count 0 2006.231.07:46:08.54#ibcon#about to read 6, iclass 39, count 0 2006.231.07:46:08.54#ibcon#read 6, iclass 39, count 0 2006.231.07:46:08.54#ibcon#end of sib2, iclass 39, count 0 2006.231.07:46:08.54#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:46:08.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:46:08.54#ibcon#[25=USB\r\n] 2006.231.07:46:08.54#ibcon#*before write, iclass 39, count 0 2006.231.07:46:08.54#ibcon#enter sib2, iclass 39, count 0 2006.231.07:46:08.54#ibcon#flushed, iclass 39, count 0 2006.231.07:46:08.54#ibcon#about to write, iclass 39, count 0 2006.231.07:46:08.54#ibcon#wrote, iclass 39, count 0 2006.231.07:46:08.54#ibcon#about to read 3, iclass 39, count 0 2006.231.07:46:08.57#ibcon#read 3, iclass 39, count 0 2006.231.07:46:08.57#ibcon#about to read 4, iclass 39, count 0 2006.231.07:46:08.57#ibcon#read 4, iclass 39, count 0 2006.231.07:46:08.57#ibcon#about to read 5, iclass 39, count 0 2006.231.07:46:08.57#ibcon#read 5, iclass 39, count 0 2006.231.07:46:08.57#ibcon#about to read 6, iclass 39, count 0 2006.231.07:46:08.57#ibcon#read 6, iclass 39, count 0 2006.231.07:46:08.57#ibcon#end of sib2, iclass 39, count 0 2006.231.07:46:08.57#ibcon#*after write, iclass 39, count 0 2006.231.07:46:08.57#ibcon#*before return 0, iclass 39, count 0 2006.231.07:46:08.57#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:46:08.57#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:46:08.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:46:08.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:46:08.57$vc4f8/valo=3,672.99 2006.231.07:46:08.57#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.07:46:08.57#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.07:46:08.57#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:08.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:46:08.57#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:46:08.57#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:46:08.57#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:46:08.57#ibcon#first serial, iclass 3, count 0 2006.231.07:46:08.57#ibcon#enter sib2, iclass 3, count 0 2006.231.07:46:08.57#ibcon#flushed, iclass 3, count 0 2006.231.07:46:08.57#ibcon#about to write, iclass 3, count 0 2006.231.07:46:08.57#ibcon#wrote, iclass 3, count 0 2006.231.07:46:08.57#ibcon#about to read 3, iclass 3, count 0 2006.231.07:46:08.60#ibcon#read 3, iclass 3, count 0 2006.231.07:46:08.60#ibcon#about to read 4, iclass 3, count 0 2006.231.07:46:08.60#ibcon#read 4, iclass 3, count 0 2006.231.07:46:08.60#ibcon#about to read 5, iclass 3, count 0 2006.231.07:46:08.60#ibcon#read 5, iclass 3, count 0 2006.231.07:46:08.60#ibcon#about to read 6, iclass 3, count 0 2006.231.07:46:08.60#ibcon#read 6, iclass 3, count 0 2006.231.07:46:08.60#ibcon#end of sib2, iclass 3, count 0 2006.231.07:46:08.60#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:46:08.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:46:08.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:46:08.60#ibcon#*before write, iclass 3, count 0 2006.231.07:46:08.60#ibcon#enter sib2, iclass 3, count 0 2006.231.07:46:08.60#ibcon#flushed, iclass 3, count 0 2006.231.07:46:08.60#ibcon#about to write, iclass 3, count 0 2006.231.07:46:08.60#ibcon#wrote, iclass 3, count 0 2006.231.07:46:08.60#ibcon#about to read 3, iclass 3, count 0 2006.231.07:46:08.64#ibcon#read 3, iclass 3, count 0 2006.231.07:46:08.64#ibcon#about to read 4, iclass 3, count 0 2006.231.07:46:08.64#ibcon#read 4, iclass 3, count 0 2006.231.07:46:08.64#ibcon#about to read 5, iclass 3, count 0 2006.231.07:46:08.64#ibcon#read 5, iclass 3, count 0 2006.231.07:46:08.64#ibcon#about to read 6, iclass 3, count 0 2006.231.07:46:08.64#ibcon#read 6, iclass 3, count 0 2006.231.07:46:08.64#ibcon#end of sib2, iclass 3, count 0 2006.231.07:46:08.64#ibcon#*after write, iclass 3, count 0 2006.231.07:46:08.64#ibcon#*before return 0, iclass 3, count 0 2006.231.07:46:08.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:46:08.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:46:08.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:46:08.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:46:08.64$vc4f8/va=3,8 2006.231.07:46:08.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.07:46:08.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.07:46:08.64#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:08.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:46:08.69#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:46:08.69#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:46:08.69#ibcon#enter wrdev, iclass 5, count 2 2006.231.07:46:08.69#ibcon#first serial, iclass 5, count 2 2006.231.07:46:08.69#ibcon#enter sib2, iclass 5, count 2 2006.231.07:46:08.69#ibcon#flushed, iclass 5, count 2 2006.231.07:46:08.69#ibcon#about to write, iclass 5, count 2 2006.231.07:46:08.69#ibcon#wrote, iclass 5, count 2 2006.231.07:46:08.69#ibcon#about to read 3, iclass 5, count 2 2006.231.07:46:08.71#ibcon#read 3, iclass 5, count 2 2006.231.07:46:08.71#ibcon#about to read 4, iclass 5, count 2 2006.231.07:46:08.71#ibcon#read 4, iclass 5, count 2 2006.231.07:46:08.71#ibcon#about to read 5, iclass 5, count 2 2006.231.07:46:08.71#ibcon#read 5, iclass 5, count 2 2006.231.07:46:08.71#ibcon#about to read 6, iclass 5, count 2 2006.231.07:46:08.71#ibcon#read 6, iclass 5, count 2 2006.231.07:46:08.71#ibcon#end of sib2, iclass 5, count 2 2006.231.07:46:08.71#ibcon#*mode == 0, iclass 5, count 2 2006.231.07:46:08.71#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.07:46:08.71#ibcon#[25=AT03-08\r\n] 2006.231.07:46:08.71#ibcon#*before write, iclass 5, count 2 2006.231.07:46:08.71#ibcon#enter sib2, iclass 5, count 2 2006.231.07:46:08.71#ibcon#flushed, iclass 5, count 2 2006.231.07:46:08.71#ibcon#about to write, iclass 5, count 2 2006.231.07:46:08.71#ibcon#wrote, iclass 5, count 2 2006.231.07:46:08.71#ibcon#about to read 3, iclass 5, count 2 2006.231.07:46:08.74#ibcon#read 3, iclass 5, count 2 2006.231.07:46:08.74#ibcon#about to read 4, iclass 5, count 2 2006.231.07:46:08.74#ibcon#read 4, iclass 5, count 2 2006.231.07:46:08.74#ibcon#about to read 5, iclass 5, count 2 2006.231.07:46:08.74#ibcon#read 5, iclass 5, count 2 2006.231.07:46:08.74#ibcon#about to read 6, iclass 5, count 2 2006.231.07:46:08.74#ibcon#read 6, iclass 5, count 2 2006.231.07:46:08.74#ibcon#end of sib2, iclass 5, count 2 2006.231.07:46:08.74#ibcon#*after write, iclass 5, count 2 2006.231.07:46:08.74#ibcon#*before return 0, iclass 5, count 2 2006.231.07:46:08.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:46:08.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:46:08.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.07:46:08.74#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:08.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:46:08.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:46:08.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:46:08.86#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:46:08.86#ibcon#first serial, iclass 5, count 0 2006.231.07:46:08.86#ibcon#enter sib2, iclass 5, count 0 2006.231.07:46:08.86#ibcon#flushed, iclass 5, count 0 2006.231.07:46:08.86#ibcon#about to write, iclass 5, count 0 2006.231.07:46:08.86#ibcon#wrote, iclass 5, count 0 2006.231.07:46:08.86#ibcon#about to read 3, iclass 5, count 0 2006.231.07:46:08.88#ibcon#read 3, iclass 5, count 0 2006.231.07:46:08.88#ibcon#about to read 4, iclass 5, count 0 2006.231.07:46:08.88#ibcon#read 4, iclass 5, count 0 2006.231.07:46:08.88#ibcon#about to read 5, iclass 5, count 0 2006.231.07:46:08.88#ibcon#read 5, iclass 5, count 0 2006.231.07:46:08.88#ibcon#about to read 6, iclass 5, count 0 2006.231.07:46:08.88#ibcon#read 6, iclass 5, count 0 2006.231.07:46:08.88#ibcon#end of sib2, iclass 5, count 0 2006.231.07:46:08.88#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:46:08.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:46:08.88#ibcon#[25=USB\r\n] 2006.231.07:46:08.88#ibcon#*before write, iclass 5, count 0 2006.231.07:46:08.88#ibcon#enter sib2, iclass 5, count 0 2006.231.07:46:08.88#ibcon#flushed, iclass 5, count 0 2006.231.07:46:08.88#ibcon#about to write, iclass 5, count 0 2006.231.07:46:08.88#ibcon#wrote, iclass 5, count 0 2006.231.07:46:08.88#ibcon#about to read 3, iclass 5, count 0 2006.231.07:46:08.91#ibcon#read 3, iclass 5, count 0 2006.231.07:46:08.91#ibcon#about to read 4, iclass 5, count 0 2006.231.07:46:08.91#ibcon#read 4, iclass 5, count 0 2006.231.07:46:08.91#ibcon#about to read 5, iclass 5, count 0 2006.231.07:46:08.91#ibcon#read 5, iclass 5, count 0 2006.231.07:46:08.91#ibcon#about to read 6, iclass 5, count 0 2006.231.07:46:08.91#ibcon#read 6, iclass 5, count 0 2006.231.07:46:08.91#ibcon#end of sib2, iclass 5, count 0 2006.231.07:46:08.91#ibcon#*after write, iclass 5, count 0 2006.231.07:46:08.91#ibcon#*before return 0, iclass 5, count 0 2006.231.07:46:08.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:46:08.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:46:08.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:46:08.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:46:08.91$vc4f8/valo=4,832.99 2006.231.07:46:08.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.07:46:08.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.07:46:08.91#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:08.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:46:08.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:46:08.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:46:08.91#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:46:08.91#ibcon#first serial, iclass 7, count 0 2006.231.07:46:08.91#ibcon#enter sib2, iclass 7, count 0 2006.231.07:46:08.91#ibcon#flushed, iclass 7, count 0 2006.231.07:46:08.91#ibcon#about to write, iclass 7, count 0 2006.231.07:46:08.91#ibcon#wrote, iclass 7, count 0 2006.231.07:46:08.91#ibcon#about to read 3, iclass 7, count 0 2006.231.07:46:08.93#ibcon#read 3, iclass 7, count 0 2006.231.07:46:08.93#ibcon#about to read 4, iclass 7, count 0 2006.231.07:46:08.93#ibcon#read 4, iclass 7, count 0 2006.231.07:46:08.93#ibcon#about to read 5, iclass 7, count 0 2006.231.07:46:08.93#ibcon#read 5, iclass 7, count 0 2006.231.07:46:08.93#ibcon#about to read 6, iclass 7, count 0 2006.231.07:46:08.93#ibcon#read 6, iclass 7, count 0 2006.231.07:46:08.93#ibcon#end of sib2, iclass 7, count 0 2006.231.07:46:08.93#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:46:08.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:46:08.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:46:08.93#ibcon#*before write, iclass 7, count 0 2006.231.07:46:08.93#ibcon#enter sib2, iclass 7, count 0 2006.231.07:46:08.93#ibcon#flushed, iclass 7, count 0 2006.231.07:46:08.93#ibcon#about to write, iclass 7, count 0 2006.231.07:46:08.93#ibcon#wrote, iclass 7, count 0 2006.231.07:46:08.93#ibcon#about to read 3, iclass 7, count 0 2006.231.07:46:08.97#ibcon#read 3, iclass 7, count 0 2006.231.07:46:08.97#ibcon#about to read 4, iclass 7, count 0 2006.231.07:46:08.97#ibcon#read 4, iclass 7, count 0 2006.231.07:46:08.97#ibcon#about to read 5, iclass 7, count 0 2006.231.07:46:08.97#ibcon#read 5, iclass 7, count 0 2006.231.07:46:08.97#ibcon#about to read 6, iclass 7, count 0 2006.231.07:46:08.97#ibcon#read 6, iclass 7, count 0 2006.231.07:46:08.97#ibcon#end of sib2, iclass 7, count 0 2006.231.07:46:08.97#ibcon#*after write, iclass 7, count 0 2006.231.07:46:08.97#ibcon#*before return 0, iclass 7, count 0 2006.231.07:46:08.97#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:46:08.97#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:46:08.97#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:46:08.97#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:46:08.97$vc4f8/va=4,7 2006.231.07:46:08.97#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.07:46:08.97#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.07:46:08.97#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:08.97#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:46:09.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:46:09.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:46:09.03#ibcon#enter wrdev, iclass 11, count 2 2006.231.07:46:09.03#ibcon#first serial, iclass 11, count 2 2006.231.07:46:09.03#ibcon#enter sib2, iclass 11, count 2 2006.231.07:46:09.03#ibcon#flushed, iclass 11, count 2 2006.231.07:46:09.03#ibcon#about to write, iclass 11, count 2 2006.231.07:46:09.03#ibcon#wrote, iclass 11, count 2 2006.231.07:46:09.03#ibcon#about to read 3, iclass 11, count 2 2006.231.07:46:09.05#ibcon#read 3, iclass 11, count 2 2006.231.07:46:09.05#ibcon#about to read 4, iclass 11, count 2 2006.231.07:46:09.05#ibcon#read 4, iclass 11, count 2 2006.231.07:46:09.05#ibcon#about to read 5, iclass 11, count 2 2006.231.07:46:09.05#ibcon#read 5, iclass 11, count 2 2006.231.07:46:09.05#ibcon#about to read 6, iclass 11, count 2 2006.231.07:46:09.05#ibcon#read 6, iclass 11, count 2 2006.231.07:46:09.05#ibcon#end of sib2, iclass 11, count 2 2006.231.07:46:09.05#ibcon#*mode == 0, iclass 11, count 2 2006.231.07:46:09.05#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.07:46:09.05#ibcon#[25=AT04-07\r\n] 2006.231.07:46:09.05#ibcon#*before write, iclass 11, count 2 2006.231.07:46:09.05#ibcon#enter sib2, iclass 11, count 2 2006.231.07:46:09.05#ibcon#flushed, iclass 11, count 2 2006.231.07:46:09.05#ibcon#about to write, iclass 11, count 2 2006.231.07:46:09.05#ibcon#wrote, iclass 11, count 2 2006.231.07:46:09.05#ibcon#about to read 3, iclass 11, count 2 2006.231.07:46:09.08#ibcon#read 3, iclass 11, count 2 2006.231.07:46:09.08#ibcon#about to read 4, iclass 11, count 2 2006.231.07:46:09.08#ibcon#read 4, iclass 11, count 2 2006.231.07:46:09.08#ibcon#about to read 5, iclass 11, count 2 2006.231.07:46:09.08#ibcon#read 5, iclass 11, count 2 2006.231.07:46:09.08#ibcon#about to read 6, iclass 11, count 2 2006.231.07:46:09.08#ibcon#read 6, iclass 11, count 2 2006.231.07:46:09.08#ibcon#end of sib2, iclass 11, count 2 2006.231.07:46:09.08#ibcon#*after write, iclass 11, count 2 2006.231.07:46:09.08#ibcon#*before return 0, iclass 11, count 2 2006.231.07:46:09.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:46:09.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:46:09.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.07:46:09.08#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:09.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:46:09.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:46:09.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:46:09.20#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:46:09.20#ibcon#first serial, iclass 11, count 0 2006.231.07:46:09.20#ibcon#enter sib2, iclass 11, count 0 2006.231.07:46:09.20#ibcon#flushed, iclass 11, count 0 2006.231.07:46:09.20#ibcon#about to write, iclass 11, count 0 2006.231.07:46:09.20#ibcon#wrote, iclass 11, count 0 2006.231.07:46:09.20#ibcon#about to read 3, iclass 11, count 0 2006.231.07:46:09.22#ibcon#read 3, iclass 11, count 0 2006.231.07:46:09.22#ibcon#about to read 4, iclass 11, count 0 2006.231.07:46:09.22#ibcon#read 4, iclass 11, count 0 2006.231.07:46:09.22#ibcon#about to read 5, iclass 11, count 0 2006.231.07:46:09.22#ibcon#read 5, iclass 11, count 0 2006.231.07:46:09.22#ibcon#about to read 6, iclass 11, count 0 2006.231.07:46:09.22#ibcon#read 6, iclass 11, count 0 2006.231.07:46:09.22#ibcon#end of sib2, iclass 11, count 0 2006.231.07:46:09.22#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:46:09.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:46:09.22#ibcon#[25=USB\r\n] 2006.231.07:46:09.22#ibcon#*before write, iclass 11, count 0 2006.231.07:46:09.22#ibcon#enter sib2, iclass 11, count 0 2006.231.07:46:09.22#ibcon#flushed, iclass 11, count 0 2006.231.07:46:09.22#ibcon#about to write, iclass 11, count 0 2006.231.07:46:09.22#ibcon#wrote, iclass 11, count 0 2006.231.07:46:09.22#ibcon#about to read 3, iclass 11, count 0 2006.231.07:46:09.25#ibcon#read 3, iclass 11, count 0 2006.231.07:46:09.25#ibcon#about to read 4, iclass 11, count 0 2006.231.07:46:09.25#ibcon#read 4, iclass 11, count 0 2006.231.07:46:09.25#ibcon#about to read 5, iclass 11, count 0 2006.231.07:46:09.25#ibcon#read 5, iclass 11, count 0 2006.231.07:46:09.25#ibcon#about to read 6, iclass 11, count 0 2006.231.07:46:09.25#ibcon#read 6, iclass 11, count 0 2006.231.07:46:09.25#ibcon#end of sib2, iclass 11, count 0 2006.231.07:46:09.25#ibcon#*after write, iclass 11, count 0 2006.231.07:46:09.25#ibcon#*before return 0, iclass 11, count 0 2006.231.07:46:09.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:46:09.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:46:09.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:46:09.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:46:09.25$vc4f8/valo=5,652.99 2006.231.07:46:09.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.07:46:09.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.07:46:09.25#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:09.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:46:09.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:46:09.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:46:09.25#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:46:09.25#ibcon#first serial, iclass 13, count 0 2006.231.07:46:09.25#ibcon#enter sib2, iclass 13, count 0 2006.231.07:46:09.25#ibcon#flushed, iclass 13, count 0 2006.231.07:46:09.25#ibcon#about to write, iclass 13, count 0 2006.231.07:46:09.25#ibcon#wrote, iclass 13, count 0 2006.231.07:46:09.25#ibcon#about to read 3, iclass 13, count 0 2006.231.07:46:09.27#ibcon#read 3, iclass 13, count 0 2006.231.07:46:09.27#ibcon#about to read 4, iclass 13, count 0 2006.231.07:46:09.27#ibcon#read 4, iclass 13, count 0 2006.231.07:46:09.27#ibcon#about to read 5, iclass 13, count 0 2006.231.07:46:09.27#ibcon#read 5, iclass 13, count 0 2006.231.07:46:09.27#ibcon#about to read 6, iclass 13, count 0 2006.231.07:46:09.27#ibcon#read 6, iclass 13, count 0 2006.231.07:46:09.27#ibcon#end of sib2, iclass 13, count 0 2006.231.07:46:09.27#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:46:09.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:46:09.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:46:09.27#ibcon#*before write, iclass 13, count 0 2006.231.07:46:09.27#ibcon#enter sib2, iclass 13, count 0 2006.231.07:46:09.27#ibcon#flushed, iclass 13, count 0 2006.231.07:46:09.27#ibcon#about to write, iclass 13, count 0 2006.231.07:46:09.27#ibcon#wrote, iclass 13, count 0 2006.231.07:46:09.27#ibcon#about to read 3, iclass 13, count 0 2006.231.07:46:09.31#ibcon#read 3, iclass 13, count 0 2006.231.07:46:09.31#ibcon#about to read 4, iclass 13, count 0 2006.231.07:46:09.31#ibcon#read 4, iclass 13, count 0 2006.231.07:46:09.31#ibcon#about to read 5, iclass 13, count 0 2006.231.07:46:09.31#ibcon#read 5, iclass 13, count 0 2006.231.07:46:09.31#ibcon#about to read 6, iclass 13, count 0 2006.231.07:46:09.31#ibcon#read 6, iclass 13, count 0 2006.231.07:46:09.31#ibcon#end of sib2, iclass 13, count 0 2006.231.07:46:09.31#ibcon#*after write, iclass 13, count 0 2006.231.07:46:09.31#ibcon#*before return 0, iclass 13, count 0 2006.231.07:46:09.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:46:09.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:46:09.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:46:09.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:46:09.31$vc4f8/va=5,7 2006.231.07:46:09.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.07:46:09.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.07:46:09.31#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:09.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:46:09.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:46:09.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:46:09.38#ibcon#enter wrdev, iclass 15, count 2 2006.231.07:46:09.38#ibcon#first serial, iclass 15, count 2 2006.231.07:46:09.38#ibcon#enter sib2, iclass 15, count 2 2006.231.07:46:09.38#ibcon#flushed, iclass 15, count 2 2006.231.07:46:09.38#ibcon#about to write, iclass 15, count 2 2006.231.07:46:09.38#ibcon#wrote, iclass 15, count 2 2006.231.07:46:09.38#ibcon#about to read 3, iclass 15, count 2 2006.231.07:46:09.39#ibcon#read 3, iclass 15, count 2 2006.231.07:46:09.39#ibcon#about to read 4, iclass 15, count 2 2006.231.07:46:09.39#ibcon#read 4, iclass 15, count 2 2006.231.07:46:09.39#ibcon#about to read 5, iclass 15, count 2 2006.231.07:46:09.39#ibcon#read 5, iclass 15, count 2 2006.231.07:46:09.39#ibcon#about to read 6, iclass 15, count 2 2006.231.07:46:09.39#ibcon#read 6, iclass 15, count 2 2006.231.07:46:09.39#ibcon#end of sib2, iclass 15, count 2 2006.231.07:46:09.39#ibcon#*mode == 0, iclass 15, count 2 2006.231.07:46:09.39#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.07:46:09.39#ibcon#[25=AT05-07\r\n] 2006.231.07:46:09.39#ibcon#*before write, iclass 15, count 2 2006.231.07:46:09.39#ibcon#enter sib2, iclass 15, count 2 2006.231.07:46:09.39#ibcon#flushed, iclass 15, count 2 2006.231.07:46:09.39#ibcon#about to write, iclass 15, count 2 2006.231.07:46:09.39#ibcon#wrote, iclass 15, count 2 2006.231.07:46:09.39#ibcon#about to read 3, iclass 15, count 2 2006.231.07:46:09.42#ibcon#read 3, iclass 15, count 2 2006.231.07:46:09.42#ibcon#about to read 4, iclass 15, count 2 2006.231.07:46:09.42#ibcon#read 4, iclass 15, count 2 2006.231.07:46:09.42#ibcon#about to read 5, iclass 15, count 2 2006.231.07:46:09.42#ibcon#read 5, iclass 15, count 2 2006.231.07:46:09.42#ibcon#about to read 6, iclass 15, count 2 2006.231.07:46:09.42#ibcon#read 6, iclass 15, count 2 2006.231.07:46:09.42#ibcon#end of sib2, iclass 15, count 2 2006.231.07:46:09.42#ibcon#*after write, iclass 15, count 2 2006.231.07:46:09.42#ibcon#*before return 0, iclass 15, count 2 2006.231.07:46:09.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:46:09.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:46:09.42#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.07:46:09.42#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:09.42#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:46:09.54#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:46:09.54#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:46:09.54#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:46:09.54#ibcon#first serial, iclass 15, count 0 2006.231.07:46:09.54#ibcon#enter sib2, iclass 15, count 0 2006.231.07:46:09.54#ibcon#flushed, iclass 15, count 0 2006.231.07:46:09.54#ibcon#about to write, iclass 15, count 0 2006.231.07:46:09.54#ibcon#wrote, iclass 15, count 0 2006.231.07:46:09.54#ibcon#about to read 3, iclass 15, count 0 2006.231.07:46:09.56#ibcon#read 3, iclass 15, count 0 2006.231.07:46:09.56#ibcon#about to read 4, iclass 15, count 0 2006.231.07:46:09.56#ibcon#read 4, iclass 15, count 0 2006.231.07:46:09.56#ibcon#about to read 5, iclass 15, count 0 2006.231.07:46:09.56#ibcon#read 5, iclass 15, count 0 2006.231.07:46:09.56#ibcon#about to read 6, iclass 15, count 0 2006.231.07:46:09.56#ibcon#read 6, iclass 15, count 0 2006.231.07:46:09.56#ibcon#end of sib2, iclass 15, count 0 2006.231.07:46:09.56#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:46:09.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:46:09.56#ibcon#[25=USB\r\n] 2006.231.07:46:09.56#ibcon#*before write, iclass 15, count 0 2006.231.07:46:09.56#ibcon#enter sib2, iclass 15, count 0 2006.231.07:46:09.56#ibcon#flushed, iclass 15, count 0 2006.231.07:46:09.56#ibcon#about to write, iclass 15, count 0 2006.231.07:46:09.56#ibcon#wrote, iclass 15, count 0 2006.231.07:46:09.56#ibcon#about to read 3, iclass 15, count 0 2006.231.07:46:09.59#ibcon#read 3, iclass 15, count 0 2006.231.07:46:09.59#ibcon#about to read 4, iclass 15, count 0 2006.231.07:46:09.59#ibcon#read 4, iclass 15, count 0 2006.231.07:46:09.59#ibcon#about to read 5, iclass 15, count 0 2006.231.07:46:09.59#ibcon#read 5, iclass 15, count 0 2006.231.07:46:09.59#ibcon#about to read 6, iclass 15, count 0 2006.231.07:46:09.59#ibcon#read 6, iclass 15, count 0 2006.231.07:46:09.59#ibcon#end of sib2, iclass 15, count 0 2006.231.07:46:09.59#ibcon#*after write, iclass 15, count 0 2006.231.07:46:09.59#ibcon#*before return 0, iclass 15, count 0 2006.231.07:46:09.59#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:46:09.59#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:46:09.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:46:09.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:46:09.59$vc4f8/valo=6,772.99 2006.231.07:46:09.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.07:46:09.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.07:46:09.59#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:09.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:46:09.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:46:09.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:46:09.59#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:46:09.59#ibcon#first serial, iclass 17, count 0 2006.231.07:46:09.59#ibcon#enter sib2, iclass 17, count 0 2006.231.07:46:09.59#ibcon#flushed, iclass 17, count 0 2006.231.07:46:09.59#ibcon#about to write, iclass 17, count 0 2006.231.07:46:09.59#ibcon#wrote, iclass 17, count 0 2006.231.07:46:09.59#ibcon#about to read 3, iclass 17, count 0 2006.231.07:46:09.61#ibcon#read 3, iclass 17, count 0 2006.231.07:46:09.61#ibcon#about to read 4, iclass 17, count 0 2006.231.07:46:09.61#ibcon#read 4, iclass 17, count 0 2006.231.07:46:09.61#ibcon#about to read 5, iclass 17, count 0 2006.231.07:46:09.61#ibcon#read 5, iclass 17, count 0 2006.231.07:46:09.61#ibcon#about to read 6, iclass 17, count 0 2006.231.07:46:09.61#ibcon#read 6, iclass 17, count 0 2006.231.07:46:09.61#ibcon#end of sib2, iclass 17, count 0 2006.231.07:46:09.61#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:46:09.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:46:09.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:46:09.61#ibcon#*before write, iclass 17, count 0 2006.231.07:46:09.61#ibcon#enter sib2, iclass 17, count 0 2006.231.07:46:09.61#ibcon#flushed, iclass 17, count 0 2006.231.07:46:09.61#ibcon#about to write, iclass 17, count 0 2006.231.07:46:09.61#ibcon#wrote, iclass 17, count 0 2006.231.07:46:09.61#ibcon#about to read 3, iclass 17, count 0 2006.231.07:46:09.65#ibcon#read 3, iclass 17, count 0 2006.231.07:46:09.65#ibcon#about to read 4, iclass 17, count 0 2006.231.07:46:09.65#ibcon#read 4, iclass 17, count 0 2006.231.07:46:09.65#ibcon#about to read 5, iclass 17, count 0 2006.231.07:46:09.65#ibcon#read 5, iclass 17, count 0 2006.231.07:46:09.65#ibcon#about to read 6, iclass 17, count 0 2006.231.07:46:09.65#ibcon#read 6, iclass 17, count 0 2006.231.07:46:09.65#ibcon#end of sib2, iclass 17, count 0 2006.231.07:46:09.65#ibcon#*after write, iclass 17, count 0 2006.231.07:46:09.65#ibcon#*before return 0, iclass 17, count 0 2006.231.07:46:09.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:46:09.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:46:09.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:46:09.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:46:09.65$vc4f8/va=6,6 2006.231.07:46:09.65#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.231.07:46:09.65#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.231.07:46:09.65#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:09.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:46:09.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:46:09.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:46:09.71#ibcon#enter wrdev, iclass 19, count 2 2006.231.07:46:09.71#ibcon#first serial, iclass 19, count 2 2006.231.07:46:09.71#ibcon#enter sib2, iclass 19, count 2 2006.231.07:46:09.71#ibcon#flushed, iclass 19, count 2 2006.231.07:46:09.71#ibcon#about to write, iclass 19, count 2 2006.231.07:46:09.71#ibcon#wrote, iclass 19, count 2 2006.231.07:46:09.71#ibcon#about to read 3, iclass 19, count 2 2006.231.07:46:09.73#ibcon#read 3, iclass 19, count 2 2006.231.07:46:09.73#ibcon#about to read 4, iclass 19, count 2 2006.231.07:46:09.73#ibcon#read 4, iclass 19, count 2 2006.231.07:46:09.73#ibcon#about to read 5, iclass 19, count 2 2006.231.07:46:09.73#ibcon#read 5, iclass 19, count 2 2006.231.07:46:09.73#ibcon#about to read 6, iclass 19, count 2 2006.231.07:46:09.73#ibcon#read 6, iclass 19, count 2 2006.231.07:46:09.73#ibcon#end of sib2, iclass 19, count 2 2006.231.07:46:09.73#ibcon#*mode == 0, iclass 19, count 2 2006.231.07:46:09.73#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.231.07:46:09.73#ibcon#[25=AT06-06\r\n] 2006.231.07:46:09.73#ibcon#*before write, iclass 19, count 2 2006.231.07:46:09.73#ibcon#enter sib2, iclass 19, count 2 2006.231.07:46:09.73#ibcon#flushed, iclass 19, count 2 2006.231.07:46:09.73#ibcon#about to write, iclass 19, count 2 2006.231.07:46:09.73#ibcon#wrote, iclass 19, count 2 2006.231.07:46:09.73#ibcon#about to read 3, iclass 19, count 2 2006.231.07:46:09.76#ibcon#read 3, iclass 19, count 2 2006.231.07:46:09.76#ibcon#about to read 4, iclass 19, count 2 2006.231.07:46:09.76#ibcon#read 4, iclass 19, count 2 2006.231.07:46:09.76#ibcon#about to read 5, iclass 19, count 2 2006.231.07:46:09.76#ibcon#read 5, iclass 19, count 2 2006.231.07:46:09.76#ibcon#about to read 6, iclass 19, count 2 2006.231.07:46:09.76#ibcon#read 6, iclass 19, count 2 2006.231.07:46:09.76#ibcon#end of sib2, iclass 19, count 2 2006.231.07:46:09.76#ibcon#*after write, iclass 19, count 2 2006.231.07:46:09.76#ibcon#*before return 0, iclass 19, count 2 2006.231.07:46:09.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:46:09.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:46:09.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.231.07:46:09.76#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:09.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:46:09.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:46:09.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:46:09.88#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:46:09.88#ibcon#first serial, iclass 19, count 0 2006.231.07:46:09.88#ibcon#enter sib2, iclass 19, count 0 2006.231.07:46:09.88#ibcon#flushed, iclass 19, count 0 2006.231.07:46:09.88#ibcon#about to write, iclass 19, count 0 2006.231.07:46:09.88#ibcon#wrote, iclass 19, count 0 2006.231.07:46:09.88#ibcon#about to read 3, iclass 19, count 0 2006.231.07:46:09.90#ibcon#read 3, iclass 19, count 0 2006.231.07:46:09.90#ibcon#about to read 4, iclass 19, count 0 2006.231.07:46:09.90#ibcon#read 4, iclass 19, count 0 2006.231.07:46:09.90#ibcon#about to read 5, iclass 19, count 0 2006.231.07:46:09.90#ibcon#read 5, iclass 19, count 0 2006.231.07:46:09.90#ibcon#about to read 6, iclass 19, count 0 2006.231.07:46:09.90#ibcon#read 6, iclass 19, count 0 2006.231.07:46:09.90#ibcon#end of sib2, iclass 19, count 0 2006.231.07:46:09.90#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:46:09.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:46:09.90#ibcon#[25=USB\r\n] 2006.231.07:46:09.90#ibcon#*before write, iclass 19, count 0 2006.231.07:46:09.90#ibcon#enter sib2, iclass 19, count 0 2006.231.07:46:09.90#ibcon#flushed, iclass 19, count 0 2006.231.07:46:09.90#ibcon#about to write, iclass 19, count 0 2006.231.07:46:09.90#ibcon#wrote, iclass 19, count 0 2006.231.07:46:09.90#ibcon#about to read 3, iclass 19, count 0 2006.231.07:46:09.93#ibcon#read 3, iclass 19, count 0 2006.231.07:46:09.93#ibcon#about to read 4, iclass 19, count 0 2006.231.07:46:09.93#ibcon#read 4, iclass 19, count 0 2006.231.07:46:09.93#ibcon#about to read 5, iclass 19, count 0 2006.231.07:46:09.93#ibcon#read 5, iclass 19, count 0 2006.231.07:46:09.93#ibcon#about to read 6, iclass 19, count 0 2006.231.07:46:09.93#ibcon#read 6, iclass 19, count 0 2006.231.07:46:09.93#ibcon#end of sib2, iclass 19, count 0 2006.231.07:46:09.93#ibcon#*after write, iclass 19, count 0 2006.231.07:46:09.93#ibcon#*before return 0, iclass 19, count 0 2006.231.07:46:09.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:46:09.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:46:09.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:46:09.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:46:09.93$vc4f8/valo=7,832.99 2006.231.07:46:09.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.07:46:09.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.07:46:09.93#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:09.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:46:09.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:46:09.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:46:09.93#ibcon#enter wrdev, iclass 21, count 0 2006.231.07:46:09.93#ibcon#first serial, iclass 21, count 0 2006.231.07:46:09.93#ibcon#enter sib2, iclass 21, count 0 2006.231.07:46:09.93#ibcon#flushed, iclass 21, count 0 2006.231.07:46:09.93#ibcon#about to write, iclass 21, count 0 2006.231.07:46:09.93#ibcon#wrote, iclass 21, count 0 2006.231.07:46:09.93#ibcon#about to read 3, iclass 21, count 0 2006.231.07:46:09.95#ibcon#read 3, iclass 21, count 0 2006.231.07:46:09.95#ibcon#about to read 4, iclass 21, count 0 2006.231.07:46:09.95#ibcon#read 4, iclass 21, count 0 2006.231.07:46:09.95#ibcon#about to read 5, iclass 21, count 0 2006.231.07:46:09.95#ibcon#read 5, iclass 21, count 0 2006.231.07:46:09.95#ibcon#about to read 6, iclass 21, count 0 2006.231.07:46:09.95#ibcon#read 6, iclass 21, count 0 2006.231.07:46:09.95#ibcon#end of sib2, iclass 21, count 0 2006.231.07:46:09.95#ibcon#*mode == 0, iclass 21, count 0 2006.231.07:46:09.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.07:46:09.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:46:09.95#ibcon#*before write, iclass 21, count 0 2006.231.07:46:09.95#ibcon#enter sib2, iclass 21, count 0 2006.231.07:46:09.95#ibcon#flushed, iclass 21, count 0 2006.231.07:46:09.95#ibcon#about to write, iclass 21, count 0 2006.231.07:46:09.95#ibcon#wrote, iclass 21, count 0 2006.231.07:46:09.95#ibcon#about to read 3, iclass 21, count 0 2006.231.07:46:09.99#ibcon#read 3, iclass 21, count 0 2006.231.07:46:09.99#ibcon#about to read 4, iclass 21, count 0 2006.231.07:46:09.99#ibcon#read 4, iclass 21, count 0 2006.231.07:46:09.99#ibcon#about to read 5, iclass 21, count 0 2006.231.07:46:09.99#ibcon#read 5, iclass 21, count 0 2006.231.07:46:09.99#ibcon#about to read 6, iclass 21, count 0 2006.231.07:46:09.99#ibcon#read 6, iclass 21, count 0 2006.231.07:46:09.99#ibcon#end of sib2, iclass 21, count 0 2006.231.07:46:09.99#ibcon#*after write, iclass 21, count 0 2006.231.07:46:09.99#ibcon#*before return 0, iclass 21, count 0 2006.231.07:46:09.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:46:09.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:46:09.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.07:46:09.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.07:46:09.99$vc4f8/va=7,6 2006.231.07:46:09.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.231.07:46:09.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.231.07:46:09.99#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:09.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:46:10.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:46:10.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:46:10.05#ibcon#enter wrdev, iclass 23, count 2 2006.231.07:46:10.05#ibcon#first serial, iclass 23, count 2 2006.231.07:46:10.05#ibcon#enter sib2, iclass 23, count 2 2006.231.07:46:10.05#ibcon#flushed, iclass 23, count 2 2006.231.07:46:10.05#ibcon#about to write, iclass 23, count 2 2006.231.07:46:10.05#ibcon#wrote, iclass 23, count 2 2006.231.07:46:10.05#ibcon#about to read 3, iclass 23, count 2 2006.231.07:46:10.08#ibcon#read 3, iclass 23, count 2 2006.231.07:46:10.08#ibcon#about to read 4, iclass 23, count 2 2006.231.07:46:10.08#ibcon#read 4, iclass 23, count 2 2006.231.07:46:10.08#ibcon#about to read 5, iclass 23, count 2 2006.231.07:46:10.08#ibcon#read 5, iclass 23, count 2 2006.231.07:46:10.08#ibcon#about to read 6, iclass 23, count 2 2006.231.07:46:10.08#ibcon#read 6, iclass 23, count 2 2006.231.07:46:10.08#ibcon#end of sib2, iclass 23, count 2 2006.231.07:46:10.08#ibcon#*mode == 0, iclass 23, count 2 2006.231.07:46:10.08#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.231.07:46:10.08#ibcon#[25=AT07-06\r\n] 2006.231.07:46:10.08#ibcon#*before write, iclass 23, count 2 2006.231.07:46:10.08#ibcon#enter sib2, iclass 23, count 2 2006.231.07:46:10.08#ibcon#flushed, iclass 23, count 2 2006.231.07:46:10.08#ibcon#about to write, iclass 23, count 2 2006.231.07:46:10.08#ibcon#wrote, iclass 23, count 2 2006.231.07:46:10.08#ibcon#about to read 3, iclass 23, count 2 2006.231.07:46:10.11#ibcon#read 3, iclass 23, count 2 2006.231.07:46:10.11#ibcon#about to read 4, iclass 23, count 2 2006.231.07:46:10.11#ibcon#read 4, iclass 23, count 2 2006.231.07:46:10.11#ibcon#about to read 5, iclass 23, count 2 2006.231.07:46:10.11#ibcon#read 5, iclass 23, count 2 2006.231.07:46:10.11#ibcon#about to read 6, iclass 23, count 2 2006.231.07:46:10.11#ibcon#read 6, iclass 23, count 2 2006.231.07:46:10.11#ibcon#end of sib2, iclass 23, count 2 2006.231.07:46:10.11#ibcon#*after write, iclass 23, count 2 2006.231.07:46:10.11#ibcon#*before return 0, iclass 23, count 2 2006.231.07:46:10.11#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:46:10.11#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:46:10.11#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.231.07:46:10.11#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:10.11#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:46:10.23#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:46:10.23#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:46:10.23#ibcon#enter wrdev, iclass 23, count 0 2006.231.07:46:10.23#ibcon#first serial, iclass 23, count 0 2006.231.07:46:10.23#ibcon#enter sib2, iclass 23, count 0 2006.231.07:46:10.23#ibcon#flushed, iclass 23, count 0 2006.231.07:46:10.23#ibcon#about to write, iclass 23, count 0 2006.231.07:46:10.23#ibcon#wrote, iclass 23, count 0 2006.231.07:46:10.23#ibcon#about to read 3, iclass 23, count 0 2006.231.07:46:10.25#ibcon#read 3, iclass 23, count 0 2006.231.07:46:10.25#ibcon#about to read 4, iclass 23, count 0 2006.231.07:46:10.25#ibcon#read 4, iclass 23, count 0 2006.231.07:46:10.25#ibcon#about to read 5, iclass 23, count 0 2006.231.07:46:10.25#ibcon#read 5, iclass 23, count 0 2006.231.07:46:10.25#ibcon#about to read 6, iclass 23, count 0 2006.231.07:46:10.25#ibcon#read 6, iclass 23, count 0 2006.231.07:46:10.25#ibcon#end of sib2, iclass 23, count 0 2006.231.07:46:10.25#ibcon#*mode == 0, iclass 23, count 0 2006.231.07:46:10.25#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.07:46:10.25#ibcon#[25=USB\r\n] 2006.231.07:46:10.25#ibcon#*before write, iclass 23, count 0 2006.231.07:46:10.25#ibcon#enter sib2, iclass 23, count 0 2006.231.07:46:10.25#ibcon#flushed, iclass 23, count 0 2006.231.07:46:10.25#ibcon#about to write, iclass 23, count 0 2006.231.07:46:10.25#ibcon#wrote, iclass 23, count 0 2006.231.07:46:10.25#ibcon#about to read 3, iclass 23, count 0 2006.231.07:46:10.28#ibcon#read 3, iclass 23, count 0 2006.231.07:46:10.28#ibcon#about to read 4, iclass 23, count 0 2006.231.07:46:10.28#ibcon#read 4, iclass 23, count 0 2006.231.07:46:10.28#ibcon#about to read 5, iclass 23, count 0 2006.231.07:46:10.28#ibcon#read 5, iclass 23, count 0 2006.231.07:46:10.28#ibcon#about to read 6, iclass 23, count 0 2006.231.07:46:10.28#ibcon#read 6, iclass 23, count 0 2006.231.07:46:10.28#ibcon#end of sib2, iclass 23, count 0 2006.231.07:46:10.28#ibcon#*after write, iclass 23, count 0 2006.231.07:46:10.28#ibcon#*before return 0, iclass 23, count 0 2006.231.07:46:10.28#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:46:10.28#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:46:10.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.07:46:10.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.07:46:10.28$vc4f8/valo=8,852.99 2006.231.07:46:10.28#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.231.07:46:10.28#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.231.07:46:10.28#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:10.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:46:10.28#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:46:10.28#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:46:10.28#ibcon#enter wrdev, iclass 25, count 0 2006.231.07:46:10.28#ibcon#first serial, iclass 25, count 0 2006.231.07:46:10.28#ibcon#enter sib2, iclass 25, count 0 2006.231.07:46:10.28#ibcon#flushed, iclass 25, count 0 2006.231.07:46:10.28#ibcon#about to write, iclass 25, count 0 2006.231.07:46:10.28#ibcon#wrote, iclass 25, count 0 2006.231.07:46:10.28#ibcon#about to read 3, iclass 25, count 0 2006.231.07:46:10.30#ibcon#read 3, iclass 25, count 0 2006.231.07:46:10.30#ibcon#about to read 4, iclass 25, count 0 2006.231.07:46:10.30#ibcon#read 4, iclass 25, count 0 2006.231.07:46:10.30#ibcon#about to read 5, iclass 25, count 0 2006.231.07:46:10.30#ibcon#read 5, iclass 25, count 0 2006.231.07:46:10.30#ibcon#about to read 6, iclass 25, count 0 2006.231.07:46:10.30#ibcon#read 6, iclass 25, count 0 2006.231.07:46:10.30#ibcon#end of sib2, iclass 25, count 0 2006.231.07:46:10.30#ibcon#*mode == 0, iclass 25, count 0 2006.231.07:46:10.30#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.07:46:10.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:46:10.30#ibcon#*before write, iclass 25, count 0 2006.231.07:46:10.30#ibcon#enter sib2, iclass 25, count 0 2006.231.07:46:10.30#ibcon#flushed, iclass 25, count 0 2006.231.07:46:10.30#ibcon#about to write, iclass 25, count 0 2006.231.07:46:10.30#ibcon#wrote, iclass 25, count 0 2006.231.07:46:10.30#ibcon#about to read 3, iclass 25, count 0 2006.231.07:46:10.34#ibcon#read 3, iclass 25, count 0 2006.231.07:46:10.34#ibcon#about to read 4, iclass 25, count 0 2006.231.07:46:10.34#ibcon#read 4, iclass 25, count 0 2006.231.07:46:10.34#ibcon#about to read 5, iclass 25, count 0 2006.231.07:46:10.34#ibcon#read 5, iclass 25, count 0 2006.231.07:46:10.34#ibcon#about to read 6, iclass 25, count 0 2006.231.07:46:10.34#ibcon#read 6, iclass 25, count 0 2006.231.07:46:10.34#ibcon#end of sib2, iclass 25, count 0 2006.231.07:46:10.34#ibcon#*after write, iclass 25, count 0 2006.231.07:46:10.34#ibcon#*before return 0, iclass 25, count 0 2006.231.07:46:10.34#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:46:10.34#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:46:10.34#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.07:46:10.34#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.07:46:10.34$vc4f8/va=8,6 2006.231.07:46:10.34#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.231.07:46:10.34#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.231.07:46:10.34#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:10.34#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:46:10.40#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:46:10.40#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:46:10.40#ibcon#enter wrdev, iclass 27, count 2 2006.231.07:46:10.40#ibcon#first serial, iclass 27, count 2 2006.231.07:46:10.40#ibcon#enter sib2, iclass 27, count 2 2006.231.07:46:10.40#ibcon#flushed, iclass 27, count 2 2006.231.07:46:10.40#ibcon#about to write, iclass 27, count 2 2006.231.07:46:10.40#ibcon#wrote, iclass 27, count 2 2006.231.07:46:10.40#ibcon#about to read 3, iclass 27, count 2 2006.231.07:46:10.42#ibcon#read 3, iclass 27, count 2 2006.231.07:46:10.42#ibcon#about to read 4, iclass 27, count 2 2006.231.07:46:10.42#ibcon#read 4, iclass 27, count 2 2006.231.07:46:10.42#ibcon#about to read 5, iclass 27, count 2 2006.231.07:46:10.42#ibcon#read 5, iclass 27, count 2 2006.231.07:46:10.42#ibcon#about to read 6, iclass 27, count 2 2006.231.07:46:10.42#ibcon#read 6, iclass 27, count 2 2006.231.07:46:10.42#ibcon#end of sib2, iclass 27, count 2 2006.231.07:46:10.42#ibcon#*mode == 0, iclass 27, count 2 2006.231.07:46:10.42#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.231.07:46:10.42#ibcon#[25=AT08-06\r\n] 2006.231.07:46:10.42#ibcon#*before write, iclass 27, count 2 2006.231.07:46:10.42#ibcon#enter sib2, iclass 27, count 2 2006.231.07:46:10.42#ibcon#flushed, iclass 27, count 2 2006.231.07:46:10.42#ibcon#about to write, iclass 27, count 2 2006.231.07:46:10.42#ibcon#wrote, iclass 27, count 2 2006.231.07:46:10.42#ibcon#about to read 3, iclass 27, count 2 2006.231.07:46:10.45#ibcon#read 3, iclass 27, count 2 2006.231.07:46:10.45#ibcon#about to read 4, iclass 27, count 2 2006.231.07:46:10.45#ibcon#read 4, iclass 27, count 2 2006.231.07:46:10.45#ibcon#about to read 5, iclass 27, count 2 2006.231.07:46:10.45#ibcon#read 5, iclass 27, count 2 2006.231.07:46:10.45#ibcon#about to read 6, iclass 27, count 2 2006.231.07:46:10.45#ibcon#read 6, iclass 27, count 2 2006.231.07:46:10.45#ibcon#end of sib2, iclass 27, count 2 2006.231.07:46:10.45#ibcon#*after write, iclass 27, count 2 2006.231.07:46:10.45#ibcon#*before return 0, iclass 27, count 2 2006.231.07:46:10.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:46:10.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:46:10.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.231.07:46:10.45#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:10.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:46:10.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:46:10.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:46:10.57#ibcon#enter wrdev, iclass 27, count 0 2006.231.07:46:10.57#ibcon#first serial, iclass 27, count 0 2006.231.07:46:10.57#ibcon#enter sib2, iclass 27, count 0 2006.231.07:46:10.57#ibcon#flushed, iclass 27, count 0 2006.231.07:46:10.57#ibcon#about to write, iclass 27, count 0 2006.231.07:46:10.57#ibcon#wrote, iclass 27, count 0 2006.231.07:46:10.57#ibcon#about to read 3, iclass 27, count 0 2006.231.07:46:10.59#ibcon#read 3, iclass 27, count 0 2006.231.07:46:10.59#ibcon#about to read 4, iclass 27, count 0 2006.231.07:46:10.59#ibcon#read 4, iclass 27, count 0 2006.231.07:46:10.59#ibcon#about to read 5, iclass 27, count 0 2006.231.07:46:10.59#ibcon#read 5, iclass 27, count 0 2006.231.07:46:10.59#ibcon#about to read 6, iclass 27, count 0 2006.231.07:46:10.59#ibcon#read 6, iclass 27, count 0 2006.231.07:46:10.59#ibcon#end of sib2, iclass 27, count 0 2006.231.07:46:10.59#ibcon#*mode == 0, iclass 27, count 0 2006.231.07:46:10.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.07:46:10.59#ibcon#[25=USB\r\n] 2006.231.07:46:10.59#ibcon#*before write, iclass 27, count 0 2006.231.07:46:10.59#ibcon#enter sib2, iclass 27, count 0 2006.231.07:46:10.59#ibcon#flushed, iclass 27, count 0 2006.231.07:46:10.59#ibcon#about to write, iclass 27, count 0 2006.231.07:46:10.59#ibcon#wrote, iclass 27, count 0 2006.231.07:46:10.59#ibcon#about to read 3, iclass 27, count 0 2006.231.07:46:10.62#ibcon#read 3, iclass 27, count 0 2006.231.07:46:10.62#ibcon#about to read 4, iclass 27, count 0 2006.231.07:46:10.62#ibcon#read 4, iclass 27, count 0 2006.231.07:46:10.62#ibcon#about to read 5, iclass 27, count 0 2006.231.07:46:10.62#ibcon#read 5, iclass 27, count 0 2006.231.07:46:10.62#ibcon#about to read 6, iclass 27, count 0 2006.231.07:46:10.62#ibcon#read 6, iclass 27, count 0 2006.231.07:46:10.62#ibcon#end of sib2, iclass 27, count 0 2006.231.07:46:10.62#ibcon#*after write, iclass 27, count 0 2006.231.07:46:10.62#ibcon#*before return 0, iclass 27, count 0 2006.231.07:46:10.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:46:10.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:46:10.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.07:46:10.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.07:46:10.62$vc4f8/vblo=1,632.99 2006.231.07:46:10.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.231.07:46:10.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.231.07:46:10.62#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:10.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:46:10.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:46:10.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:46:10.62#ibcon#enter wrdev, iclass 29, count 0 2006.231.07:46:10.62#ibcon#first serial, iclass 29, count 0 2006.231.07:46:10.62#ibcon#enter sib2, iclass 29, count 0 2006.231.07:46:10.62#ibcon#flushed, iclass 29, count 0 2006.231.07:46:10.62#ibcon#about to write, iclass 29, count 0 2006.231.07:46:10.62#ibcon#wrote, iclass 29, count 0 2006.231.07:46:10.62#ibcon#about to read 3, iclass 29, count 0 2006.231.07:46:10.64#ibcon#read 3, iclass 29, count 0 2006.231.07:46:10.64#ibcon#about to read 4, iclass 29, count 0 2006.231.07:46:10.64#ibcon#read 4, iclass 29, count 0 2006.231.07:46:10.64#ibcon#about to read 5, iclass 29, count 0 2006.231.07:46:10.64#ibcon#read 5, iclass 29, count 0 2006.231.07:46:10.64#ibcon#about to read 6, iclass 29, count 0 2006.231.07:46:10.64#ibcon#read 6, iclass 29, count 0 2006.231.07:46:10.64#ibcon#end of sib2, iclass 29, count 0 2006.231.07:46:10.64#ibcon#*mode == 0, iclass 29, count 0 2006.231.07:46:10.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.07:46:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:46:10.64#ibcon#*before write, iclass 29, count 0 2006.231.07:46:10.64#ibcon#enter sib2, iclass 29, count 0 2006.231.07:46:10.64#ibcon#flushed, iclass 29, count 0 2006.231.07:46:10.64#ibcon#about to write, iclass 29, count 0 2006.231.07:46:10.64#ibcon#wrote, iclass 29, count 0 2006.231.07:46:10.64#ibcon#about to read 3, iclass 29, count 0 2006.231.07:46:10.68#ibcon#read 3, iclass 29, count 0 2006.231.07:46:10.68#ibcon#about to read 4, iclass 29, count 0 2006.231.07:46:10.68#ibcon#read 4, iclass 29, count 0 2006.231.07:46:10.68#ibcon#about to read 5, iclass 29, count 0 2006.231.07:46:10.68#ibcon#read 5, iclass 29, count 0 2006.231.07:46:10.68#ibcon#about to read 6, iclass 29, count 0 2006.231.07:46:10.68#ibcon#read 6, iclass 29, count 0 2006.231.07:46:10.68#ibcon#end of sib2, iclass 29, count 0 2006.231.07:46:10.68#ibcon#*after write, iclass 29, count 0 2006.231.07:46:10.68#ibcon#*before return 0, iclass 29, count 0 2006.231.07:46:10.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:46:10.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:46:10.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.07:46:10.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.07:46:10.68$vc4f8/vb=1,4 2006.231.07:46:10.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.231.07:46:10.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.231.07:46:10.68#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:10.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:46:10.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:46:10.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:46:10.68#ibcon#enter wrdev, iclass 31, count 2 2006.231.07:46:10.68#ibcon#first serial, iclass 31, count 2 2006.231.07:46:10.68#ibcon#enter sib2, iclass 31, count 2 2006.231.07:46:10.68#ibcon#flushed, iclass 31, count 2 2006.231.07:46:10.68#ibcon#about to write, iclass 31, count 2 2006.231.07:46:10.68#ibcon#wrote, iclass 31, count 2 2006.231.07:46:10.68#ibcon#about to read 3, iclass 31, count 2 2006.231.07:46:10.70#ibcon#read 3, iclass 31, count 2 2006.231.07:46:10.70#ibcon#about to read 4, iclass 31, count 2 2006.231.07:46:10.70#ibcon#read 4, iclass 31, count 2 2006.231.07:46:10.70#ibcon#about to read 5, iclass 31, count 2 2006.231.07:46:10.70#ibcon#read 5, iclass 31, count 2 2006.231.07:46:10.70#ibcon#about to read 6, iclass 31, count 2 2006.231.07:46:10.70#ibcon#read 6, iclass 31, count 2 2006.231.07:46:10.70#ibcon#end of sib2, iclass 31, count 2 2006.231.07:46:10.70#ibcon#*mode == 0, iclass 31, count 2 2006.231.07:46:10.70#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.231.07:46:10.70#ibcon#[27=AT01-04\r\n] 2006.231.07:46:10.70#ibcon#*before write, iclass 31, count 2 2006.231.07:46:10.70#ibcon#enter sib2, iclass 31, count 2 2006.231.07:46:10.70#ibcon#flushed, iclass 31, count 2 2006.231.07:46:10.70#ibcon#about to write, iclass 31, count 2 2006.231.07:46:10.70#ibcon#wrote, iclass 31, count 2 2006.231.07:46:10.70#ibcon#about to read 3, iclass 31, count 2 2006.231.07:46:10.73#ibcon#read 3, iclass 31, count 2 2006.231.07:46:10.73#ibcon#about to read 4, iclass 31, count 2 2006.231.07:46:10.73#ibcon#read 4, iclass 31, count 2 2006.231.07:46:10.73#ibcon#about to read 5, iclass 31, count 2 2006.231.07:46:10.73#ibcon#read 5, iclass 31, count 2 2006.231.07:46:10.73#ibcon#about to read 6, iclass 31, count 2 2006.231.07:46:10.73#ibcon#read 6, iclass 31, count 2 2006.231.07:46:10.73#ibcon#end of sib2, iclass 31, count 2 2006.231.07:46:10.73#ibcon#*after write, iclass 31, count 2 2006.231.07:46:10.73#ibcon#*before return 0, iclass 31, count 2 2006.231.07:46:10.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:46:10.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:46:10.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.231.07:46:10.73#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:10.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:46:10.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:46:10.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:46:10.85#ibcon#enter wrdev, iclass 31, count 0 2006.231.07:46:10.85#ibcon#first serial, iclass 31, count 0 2006.231.07:46:10.85#ibcon#enter sib2, iclass 31, count 0 2006.231.07:46:10.85#ibcon#flushed, iclass 31, count 0 2006.231.07:46:10.85#ibcon#about to write, iclass 31, count 0 2006.231.07:46:10.85#ibcon#wrote, iclass 31, count 0 2006.231.07:46:10.85#ibcon#about to read 3, iclass 31, count 0 2006.231.07:46:10.87#ibcon#read 3, iclass 31, count 0 2006.231.07:46:10.87#ibcon#about to read 4, iclass 31, count 0 2006.231.07:46:10.87#ibcon#read 4, iclass 31, count 0 2006.231.07:46:10.87#ibcon#about to read 5, iclass 31, count 0 2006.231.07:46:10.87#ibcon#read 5, iclass 31, count 0 2006.231.07:46:10.87#ibcon#about to read 6, iclass 31, count 0 2006.231.07:46:10.87#ibcon#read 6, iclass 31, count 0 2006.231.07:46:10.87#ibcon#end of sib2, iclass 31, count 0 2006.231.07:46:10.87#ibcon#*mode == 0, iclass 31, count 0 2006.231.07:46:10.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.07:46:10.87#ibcon#[27=USB\r\n] 2006.231.07:46:10.87#ibcon#*before write, iclass 31, count 0 2006.231.07:46:10.87#ibcon#enter sib2, iclass 31, count 0 2006.231.07:46:10.87#ibcon#flushed, iclass 31, count 0 2006.231.07:46:10.87#ibcon#about to write, iclass 31, count 0 2006.231.07:46:10.87#ibcon#wrote, iclass 31, count 0 2006.231.07:46:10.87#ibcon#about to read 3, iclass 31, count 0 2006.231.07:46:10.90#ibcon#read 3, iclass 31, count 0 2006.231.07:46:10.90#ibcon#about to read 4, iclass 31, count 0 2006.231.07:46:10.90#ibcon#read 4, iclass 31, count 0 2006.231.07:46:10.90#ibcon#about to read 5, iclass 31, count 0 2006.231.07:46:10.90#ibcon#read 5, iclass 31, count 0 2006.231.07:46:10.90#ibcon#about to read 6, iclass 31, count 0 2006.231.07:46:10.90#ibcon#read 6, iclass 31, count 0 2006.231.07:46:10.90#ibcon#end of sib2, iclass 31, count 0 2006.231.07:46:10.90#ibcon#*after write, iclass 31, count 0 2006.231.07:46:10.90#ibcon#*before return 0, iclass 31, count 0 2006.231.07:46:10.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:46:10.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:46:10.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.07:46:10.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.07:46:10.90$vc4f8/vblo=2,640.99 2006.231.07:46:10.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.07:46:10.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.07:46:10.90#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:10.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:46:10.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:46:10.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:46:10.90#ibcon#enter wrdev, iclass 33, count 0 2006.231.07:46:10.90#ibcon#first serial, iclass 33, count 0 2006.231.07:46:10.90#ibcon#enter sib2, iclass 33, count 0 2006.231.07:46:10.90#ibcon#flushed, iclass 33, count 0 2006.231.07:46:10.90#ibcon#about to write, iclass 33, count 0 2006.231.07:46:10.90#ibcon#wrote, iclass 33, count 0 2006.231.07:46:10.90#ibcon#about to read 3, iclass 33, count 0 2006.231.07:46:10.93#ibcon#read 3, iclass 33, count 0 2006.231.07:46:10.93#ibcon#about to read 4, iclass 33, count 0 2006.231.07:46:10.93#ibcon#read 4, iclass 33, count 0 2006.231.07:46:10.93#ibcon#about to read 5, iclass 33, count 0 2006.231.07:46:10.93#ibcon#read 5, iclass 33, count 0 2006.231.07:46:10.93#ibcon#about to read 6, iclass 33, count 0 2006.231.07:46:10.93#ibcon#read 6, iclass 33, count 0 2006.231.07:46:10.93#ibcon#end of sib2, iclass 33, count 0 2006.231.07:46:10.93#ibcon#*mode == 0, iclass 33, count 0 2006.231.07:46:10.93#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.07:46:10.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:46:10.93#ibcon#*before write, iclass 33, count 0 2006.231.07:46:10.93#ibcon#enter sib2, iclass 33, count 0 2006.231.07:46:10.93#ibcon#flushed, iclass 33, count 0 2006.231.07:46:10.93#ibcon#about to write, iclass 33, count 0 2006.231.07:46:10.93#ibcon#wrote, iclass 33, count 0 2006.231.07:46:10.93#ibcon#about to read 3, iclass 33, count 0 2006.231.07:46:10.97#ibcon#read 3, iclass 33, count 0 2006.231.07:46:10.97#ibcon#about to read 4, iclass 33, count 0 2006.231.07:46:10.97#ibcon#read 4, iclass 33, count 0 2006.231.07:46:10.97#ibcon#about to read 5, iclass 33, count 0 2006.231.07:46:10.97#ibcon#read 5, iclass 33, count 0 2006.231.07:46:10.97#ibcon#about to read 6, iclass 33, count 0 2006.231.07:46:10.97#ibcon#read 6, iclass 33, count 0 2006.231.07:46:10.97#ibcon#end of sib2, iclass 33, count 0 2006.231.07:46:10.97#ibcon#*after write, iclass 33, count 0 2006.231.07:46:10.97#ibcon#*before return 0, iclass 33, count 0 2006.231.07:46:10.97#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:46:10.97#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:46:10.97#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.07:46:10.97#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.07:46:10.97$vc4f8/vb=2,4 2006.231.07:46:10.97#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.07:46:10.97#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.07:46:10.97#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:10.97#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:46:11.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:46:11.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:46:11.02#ibcon#enter wrdev, iclass 35, count 2 2006.231.07:46:11.02#ibcon#first serial, iclass 35, count 2 2006.231.07:46:11.02#ibcon#enter sib2, iclass 35, count 2 2006.231.07:46:11.02#ibcon#flushed, iclass 35, count 2 2006.231.07:46:11.02#ibcon#about to write, iclass 35, count 2 2006.231.07:46:11.02#ibcon#wrote, iclass 35, count 2 2006.231.07:46:11.02#ibcon#about to read 3, iclass 35, count 2 2006.231.07:46:11.04#ibcon#read 3, iclass 35, count 2 2006.231.07:46:11.04#ibcon#about to read 4, iclass 35, count 2 2006.231.07:46:11.04#ibcon#read 4, iclass 35, count 2 2006.231.07:46:11.04#ibcon#about to read 5, iclass 35, count 2 2006.231.07:46:11.04#ibcon#read 5, iclass 35, count 2 2006.231.07:46:11.04#ibcon#about to read 6, iclass 35, count 2 2006.231.07:46:11.04#ibcon#read 6, iclass 35, count 2 2006.231.07:46:11.04#ibcon#end of sib2, iclass 35, count 2 2006.231.07:46:11.04#ibcon#*mode == 0, iclass 35, count 2 2006.231.07:46:11.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.07:46:11.04#ibcon#[27=AT02-04\r\n] 2006.231.07:46:11.04#ibcon#*before write, iclass 35, count 2 2006.231.07:46:11.04#ibcon#enter sib2, iclass 35, count 2 2006.231.07:46:11.04#ibcon#flushed, iclass 35, count 2 2006.231.07:46:11.04#ibcon#about to write, iclass 35, count 2 2006.231.07:46:11.04#ibcon#wrote, iclass 35, count 2 2006.231.07:46:11.04#ibcon#about to read 3, iclass 35, count 2 2006.231.07:46:11.07#ibcon#read 3, iclass 35, count 2 2006.231.07:46:11.07#ibcon#about to read 4, iclass 35, count 2 2006.231.07:46:11.07#ibcon#read 4, iclass 35, count 2 2006.231.07:46:11.07#ibcon#about to read 5, iclass 35, count 2 2006.231.07:46:11.07#ibcon#read 5, iclass 35, count 2 2006.231.07:46:11.07#ibcon#about to read 6, iclass 35, count 2 2006.231.07:46:11.07#ibcon#read 6, iclass 35, count 2 2006.231.07:46:11.07#ibcon#end of sib2, iclass 35, count 2 2006.231.07:46:11.07#ibcon#*after write, iclass 35, count 2 2006.231.07:46:11.07#ibcon#*before return 0, iclass 35, count 2 2006.231.07:46:11.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:46:11.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:46:11.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.07:46:11.07#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:11.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:46:11.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:46:11.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:46:11.19#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:46:11.19#ibcon#first serial, iclass 35, count 0 2006.231.07:46:11.19#ibcon#enter sib2, iclass 35, count 0 2006.231.07:46:11.19#ibcon#flushed, iclass 35, count 0 2006.231.07:46:11.19#ibcon#about to write, iclass 35, count 0 2006.231.07:46:11.19#ibcon#wrote, iclass 35, count 0 2006.231.07:46:11.19#ibcon#about to read 3, iclass 35, count 0 2006.231.07:46:11.21#ibcon#read 3, iclass 35, count 0 2006.231.07:46:11.21#ibcon#about to read 4, iclass 35, count 0 2006.231.07:46:11.21#ibcon#read 4, iclass 35, count 0 2006.231.07:46:11.21#ibcon#about to read 5, iclass 35, count 0 2006.231.07:46:11.21#ibcon#read 5, iclass 35, count 0 2006.231.07:46:11.21#ibcon#about to read 6, iclass 35, count 0 2006.231.07:46:11.21#ibcon#read 6, iclass 35, count 0 2006.231.07:46:11.21#ibcon#end of sib2, iclass 35, count 0 2006.231.07:46:11.21#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:46:11.21#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:46:11.21#ibcon#[27=USB\r\n] 2006.231.07:46:11.21#ibcon#*before write, iclass 35, count 0 2006.231.07:46:11.21#ibcon#enter sib2, iclass 35, count 0 2006.231.07:46:11.21#ibcon#flushed, iclass 35, count 0 2006.231.07:46:11.21#ibcon#about to write, iclass 35, count 0 2006.231.07:46:11.21#ibcon#wrote, iclass 35, count 0 2006.231.07:46:11.21#ibcon#about to read 3, iclass 35, count 0 2006.231.07:46:11.24#ibcon#read 3, iclass 35, count 0 2006.231.07:46:11.24#ibcon#about to read 4, iclass 35, count 0 2006.231.07:46:11.24#ibcon#read 4, iclass 35, count 0 2006.231.07:46:11.24#ibcon#about to read 5, iclass 35, count 0 2006.231.07:46:11.24#ibcon#read 5, iclass 35, count 0 2006.231.07:46:11.24#ibcon#about to read 6, iclass 35, count 0 2006.231.07:46:11.24#ibcon#read 6, iclass 35, count 0 2006.231.07:46:11.24#ibcon#end of sib2, iclass 35, count 0 2006.231.07:46:11.24#ibcon#*after write, iclass 35, count 0 2006.231.07:46:11.24#ibcon#*before return 0, iclass 35, count 0 2006.231.07:46:11.24#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:46:11.24#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:46:11.24#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:46:11.24#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:46:11.24$vc4f8/vblo=3,656.99 2006.231.07:46:11.24#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.07:46:11.24#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.07:46:11.24#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:11.24#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:46:11.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:46:11.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:46:11.24#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:46:11.24#ibcon#first serial, iclass 37, count 0 2006.231.07:46:11.24#ibcon#enter sib2, iclass 37, count 0 2006.231.07:46:11.24#ibcon#flushed, iclass 37, count 0 2006.231.07:46:11.24#ibcon#about to write, iclass 37, count 0 2006.231.07:46:11.24#ibcon#wrote, iclass 37, count 0 2006.231.07:46:11.24#ibcon#about to read 3, iclass 37, count 0 2006.231.07:46:11.26#ibcon#read 3, iclass 37, count 0 2006.231.07:46:11.26#ibcon#about to read 4, iclass 37, count 0 2006.231.07:46:11.26#ibcon#read 4, iclass 37, count 0 2006.231.07:46:11.26#ibcon#about to read 5, iclass 37, count 0 2006.231.07:46:11.26#ibcon#read 5, iclass 37, count 0 2006.231.07:46:11.26#ibcon#about to read 6, iclass 37, count 0 2006.231.07:46:11.26#ibcon#read 6, iclass 37, count 0 2006.231.07:46:11.26#ibcon#end of sib2, iclass 37, count 0 2006.231.07:46:11.26#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:46:11.26#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:46:11.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:46:11.26#ibcon#*before write, iclass 37, count 0 2006.231.07:46:11.26#ibcon#enter sib2, iclass 37, count 0 2006.231.07:46:11.26#ibcon#flushed, iclass 37, count 0 2006.231.07:46:11.26#ibcon#about to write, iclass 37, count 0 2006.231.07:46:11.26#ibcon#wrote, iclass 37, count 0 2006.231.07:46:11.26#ibcon#about to read 3, iclass 37, count 0 2006.231.07:46:11.30#ibcon#read 3, iclass 37, count 0 2006.231.07:46:11.30#ibcon#about to read 4, iclass 37, count 0 2006.231.07:46:11.30#ibcon#read 4, iclass 37, count 0 2006.231.07:46:11.30#ibcon#about to read 5, iclass 37, count 0 2006.231.07:46:11.30#ibcon#read 5, iclass 37, count 0 2006.231.07:46:11.30#ibcon#about to read 6, iclass 37, count 0 2006.231.07:46:11.30#ibcon#read 6, iclass 37, count 0 2006.231.07:46:11.30#ibcon#end of sib2, iclass 37, count 0 2006.231.07:46:11.30#ibcon#*after write, iclass 37, count 0 2006.231.07:46:11.30#ibcon#*before return 0, iclass 37, count 0 2006.231.07:46:11.30#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:46:11.30#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:46:11.30#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:46:11.30#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:46:11.30$vc4f8/vb=3,4 2006.231.07:46:11.30#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.07:46:11.30#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.07:46:11.30#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:11.30#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:46:11.36#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:46:11.36#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:46:11.36#ibcon#enter wrdev, iclass 39, count 2 2006.231.07:46:11.36#ibcon#first serial, iclass 39, count 2 2006.231.07:46:11.36#ibcon#enter sib2, iclass 39, count 2 2006.231.07:46:11.36#ibcon#flushed, iclass 39, count 2 2006.231.07:46:11.36#ibcon#about to write, iclass 39, count 2 2006.231.07:46:11.36#ibcon#wrote, iclass 39, count 2 2006.231.07:46:11.36#ibcon#about to read 3, iclass 39, count 2 2006.231.07:46:11.38#ibcon#read 3, iclass 39, count 2 2006.231.07:46:11.38#ibcon#about to read 4, iclass 39, count 2 2006.231.07:46:11.38#ibcon#read 4, iclass 39, count 2 2006.231.07:46:11.38#ibcon#about to read 5, iclass 39, count 2 2006.231.07:46:11.38#ibcon#read 5, iclass 39, count 2 2006.231.07:46:11.38#ibcon#about to read 6, iclass 39, count 2 2006.231.07:46:11.38#ibcon#read 6, iclass 39, count 2 2006.231.07:46:11.38#ibcon#end of sib2, iclass 39, count 2 2006.231.07:46:11.38#ibcon#*mode == 0, iclass 39, count 2 2006.231.07:46:11.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.07:46:11.38#ibcon#[27=AT03-04\r\n] 2006.231.07:46:11.38#ibcon#*before write, iclass 39, count 2 2006.231.07:46:11.38#ibcon#enter sib2, iclass 39, count 2 2006.231.07:46:11.38#ibcon#flushed, iclass 39, count 2 2006.231.07:46:11.38#ibcon#about to write, iclass 39, count 2 2006.231.07:46:11.38#ibcon#wrote, iclass 39, count 2 2006.231.07:46:11.38#ibcon#about to read 3, iclass 39, count 2 2006.231.07:46:11.41#ibcon#read 3, iclass 39, count 2 2006.231.07:46:11.41#ibcon#about to read 4, iclass 39, count 2 2006.231.07:46:11.41#ibcon#read 4, iclass 39, count 2 2006.231.07:46:11.41#ibcon#about to read 5, iclass 39, count 2 2006.231.07:46:11.41#ibcon#read 5, iclass 39, count 2 2006.231.07:46:11.41#ibcon#about to read 6, iclass 39, count 2 2006.231.07:46:11.41#ibcon#read 6, iclass 39, count 2 2006.231.07:46:11.41#ibcon#end of sib2, iclass 39, count 2 2006.231.07:46:11.41#ibcon#*after write, iclass 39, count 2 2006.231.07:46:11.41#ibcon#*before return 0, iclass 39, count 2 2006.231.07:46:11.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:46:11.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:46:11.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.07:46:11.41#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:11.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:46:11.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:46:11.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:46:11.53#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:46:11.53#ibcon#first serial, iclass 39, count 0 2006.231.07:46:11.53#ibcon#enter sib2, iclass 39, count 0 2006.231.07:46:11.53#ibcon#flushed, iclass 39, count 0 2006.231.07:46:11.53#ibcon#about to write, iclass 39, count 0 2006.231.07:46:11.53#ibcon#wrote, iclass 39, count 0 2006.231.07:46:11.53#ibcon#about to read 3, iclass 39, count 0 2006.231.07:46:11.55#ibcon#read 3, iclass 39, count 0 2006.231.07:46:11.55#ibcon#about to read 4, iclass 39, count 0 2006.231.07:46:11.55#ibcon#read 4, iclass 39, count 0 2006.231.07:46:11.55#ibcon#about to read 5, iclass 39, count 0 2006.231.07:46:11.55#ibcon#read 5, iclass 39, count 0 2006.231.07:46:11.55#ibcon#about to read 6, iclass 39, count 0 2006.231.07:46:11.55#ibcon#read 6, iclass 39, count 0 2006.231.07:46:11.55#ibcon#end of sib2, iclass 39, count 0 2006.231.07:46:11.55#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:46:11.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:46:11.55#ibcon#[27=USB\r\n] 2006.231.07:46:11.55#ibcon#*before write, iclass 39, count 0 2006.231.07:46:11.55#ibcon#enter sib2, iclass 39, count 0 2006.231.07:46:11.55#ibcon#flushed, iclass 39, count 0 2006.231.07:46:11.55#ibcon#about to write, iclass 39, count 0 2006.231.07:46:11.55#ibcon#wrote, iclass 39, count 0 2006.231.07:46:11.55#ibcon#about to read 3, iclass 39, count 0 2006.231.07:46:11.58#ibcon#read 3, iclass 39, count 0 2006.231.07:46:11.58#ibcon#about to read 4, iclass 39, count 0 2006.231.07:46:11.58#ibcon#read 4, iclass 39, count 0 2006.231.07:46:11.58#ibcon#about to read 5, iclass 39, count 0 2006.231.07:46:11.58#ibcon#read 5, iclass 39, count 0 2006.231.07:46:11.58#ibcon#about to read 6, iclass 39, count 0 2006.231.07:46:11.58#ibcon#read 6, iclass 39, count 0 2006.231.07:46:11.58#ibcon#end of sib2, iclass 39, count 0 2006.231.07:46:11.58#ibcon#*after write, iclass 39, count 0 2006.231.07:46:11.58#ibcon#*before return 0, iclass 39, count 0 2006.231.07:46:11.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:46:11.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:46:11.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:46:11.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:46:11.58$vc4f8/vblo=4,712.99 2006.231.07:46:11.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.07:46:11.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.07:46:11.58#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:11.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:46:11.58#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:46:11.58#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:46:11.58#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:46:11.58#ibcon#first serial, iclass 3, count 0 2006.231.07:46:11.58#ibcon#enter sib2, iclass 3, count 0 2006.231.07:46:11.58#ibcon#flushed, iclass 3, count 0 2006.231.07:46:11.58#ibcon#about to write, iclass 3, count 0 2006.231.07:46:11.58#ibcon#wrote, iclass 3, count 0 2006.231.07:46:11.58#ibcon#about to read 3, iclass 3, count 0 2006.231.07:46:11.60#ibcon#read 3, iclass 3, count 0 2006.231.07:46:11.60#ibcon#about to read 4, iclass 3, count 0 2006.231.07:46:11.60#ibcon#read 4, iclass 3, count 0 2006.231.07:46:11.60#ibcon#about to read 5, iclass 3, count 0 2006.231.07:46:11.60#ibcon#read 5, iclass 3, count 0 2006.231.07:46:11.60#ibcon#about to read 6, iclass 3, count 0 2006.231.07:46:11.60#ibcon#read 6, iclass 3, count 0 2006.231.07:46:11.60#ibcon#end of sib2, iclass 3, count 0 2006.231.07:46:11.60#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:46:11.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:46:11.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:46:11.60#ibcon#*before write, iclass 3, count 0 2006.231.07:46:11.60#ibcon#enter sib2, iclass 3, count 0 2006.231.07:46:11.60#ibcon#flushed, iclass 3, count 0 2006.231.07:46:11.60#ibcon#about to write, iclass 3, count 0 2006.231.07:46:11.60#ibcon#wrote, iclass 3, count 0 2006.231.07:46:11.60#ibcon#about to read 3, iclass 3, count 0 2006.231.07:46:11.64#ibcon#read 3, iclass 3, count 0 2006.231.07:46:11.64#ibcon#about to read 4, iclass 3, count 0 2006.231.07:46:11.64#ibcon#read 4, iclass 3, count 0 2006.231.07:46:11.64#ibcon#about to read 5, iclass 3, count 0 2006.231.07:46:11.64#ibcon#read 5, iclass 3, count 0 2006.231.07:46:11.64#ibcon#about to read 6, iclass 3, count 0 2006.231.07:46:11.64#ibcon#read 6, iclass 3, count 0 2006.231.07:46:11.64#ibcon#end of sib2, iclass 3, count 0 2006.231.07:46:11.64#ibcon#*after write, iclass 3, count 0 2006.231.07:46:11.64#ibcon#*before return 0, iclass 3, count 0 2006.231.07:46:11.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:46:11.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:46:11.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:46:11.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:46:11.64$vc4f8/vb=4,4 2006.231.07:46:11.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.07:46:11.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.07:46:11.64#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:11.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:46:11.70#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:46:11.70#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:46:11.70#ibcon#enter wrdev, iclass 5, count 2 2006.231.07:46:11.70#ibcon#first serial, iclass 5, count 2 2006.231.07:46:11.70#ibcon#enter sib2, iclass 5, count 2 2006.231.07:46:11.70#ibcon#flushed, iclass 5, count 2 2006.231.07:46:11.70#ibcon#about to write, iclass 5, count 2 2006.231.07:46:11.70#ibcon#wrote, iclass 5, count 2 2006.231.07:46:11.70#ibcon#about to read 3, iclass 5, count 2 2006.231.07:46:11.72#ibcon#read 3, iclass 5, count 2 2006.231.07:46:11.72#ibcon#about to read 4, iclass 5, count 2 2006.231.07:46:11.72#ibcon#read 4, iclass 5, count 2 2006.231.07:46:11.72#ibcon#about to read 5, iclass 5, count 2 2006.231.07:46:11.72#ibcon#read 5, iclass 5, count 2 2006.231.07:46:11.72#ibcon#about to read 6, iclass 5, count 2 2006.231.07:46:11.72#ibcon#read 6, iclass 5, count 2 2006.231.07:46:11.72#ibcon#end of sib2, iclass 5, count 2 2006.231.07:46:11.72#ibcon#*mode == 0, iclass 5, count 2 2006.231.07:46:11.72#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.07:46:11.72#ibcon#[27=AT04-04\r\n] 2006.231.07:46:11.72#ibcon#*before write, iclass 5, count 2 2006.231.07:46:11.72#ibcon#enter sib2, iclass 5, count 2 2006.231.07:46:11.72#ibcon#flushed, iclass 5, count 2 2006.231.07:46:11.72#ibcon#about to write, iclass 5, count 2 2006.231.07:46:11.72#ibcon#wrote, iclass 5, count 2 2006.231.07:46:11.72#ibcon#about to read 3, iclass 5, count 2 2006.231.07:46:11.75#ibcon#read 3, iclass 5, count 2 2006.231.07:46:11.75#ibcon#about to read 4, iclass 5, count 2 2006.231.07:46:11.75#ibcon#read 4, iclass 5, count 2 2006.231.07:46:11.75#ibcon#about to read 5, iclass 5, count 2 2006.231.07:46:11.75#ibcon#read 5, iclass 5, count 2 2006.231.07:46:11.75#ibcon#about to read 6, iclass 5, count 2 2006.231.07:46:11.75#ibcon#read 6, iclass 5, count 2 2006.231.07:46:11.75#ibcon#end of sib2, iclass 5, count 2 2006.231.07:46:11.75#ibcon#*after write, iclass 5, count 2 2006.231.07:46:11.75#ibcon#*before return 0, iclass 5, count 2 2006.231.07:46:11.75#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:46:11.75#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:46:11.75#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.07:46:11.75#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:11.75#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:46:11.87#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:46:11.87#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:46:11.87#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:46:11.87#ibcon#first serial, iclass 5, count 0 2006.231.07:46:11.87#ibcon#enter sib2, iclass 5, count 0 2006.231.07:46:11.87#ibcon#flushed, iclass 5, count 0 2006.231.07:46:11.87#ibcon#about to write, iclass 5, count 0 2006.231.07:46:11.87#ibcon#wrote, iclass 5, count 0 2006.231.07:46:11.87#ibcon#about to read 3, iclass 5, count 0 2006.231.07:46:11.89#ibcon#read 3, iclass 5, count 0 2006.231.07:46:11.89#ibcon#about to read 4, iclass 5, count 0 2006.231.07:46:11.89#ibcon#read 4, iclass 5, count 0 2006.231.07:46:11.89#ibcon#about to read 5, iclass 5, count 0 2006.231.07:46:11.89#ibcon#read 5, iclass 5, count 0 2006.231.07:46:11.89#ibcon#about to read 6, iclass 5, count 0 2006.231.07:46:11.89#ibcon#read 6, iclass 5, count 0 2006.231.07:46:11.89#ibcon#end of sib2, iclass 5, count 0 2006.231.07:46:11.89#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:46:11.89#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:46:11.89#ibcon#[27=USB\r\n] 2006.231.07:46:11.89#ibcon#*before write, iclass 5, count 0 2006.231.07:46:11.89#ibcon#enter sib2, iclass 5, count 0 2006.231.07:46:11.89#ibcon#flushed, iclass 5, count 0 2006.231.07:46:11.89#ibcon#about to write, iclass 5, count 0 2006.231.07:46:11.89#ibcon#wrote, iclass 5, count 0 2006.231.07:46:11.89#ibcon#about to read 3, iclass 5, count 0 2006.231.07:46:11.92#ibcon#read 3, iclass 5, count 0 2006.231.07:46:11.92#ibcon#about to read 4, iclass 5, count 0 2006.231.07:46:11.92#ibcon#read 4, iclass 5, count 0 2006.231.07:46:11.92#ibcon#about to read 5, iclass 5, count 0 2006.231.07:46:11.92#ibcon#read 5, iclass 5, count 0 2006.231.07:46:11.92#ibcon#about to read 6, iclass 5, count 0 2006.231.07:46:11.92#ibcon#read 6, iclass 5, count 0 2006.231.07:46:11.92#ibcon#end of sib2, iclass 5, count 0 2006.231.07:46:11.92#ibcon#*after write, iclass 5, count 0 2006.231.07:46:11.92#ibcon#*before return 0, iclass 5, count 0 2006.231.07:46:11.92#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:46:11.92#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:46:11.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:46:11.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:46:11.92$vc4f8/vblo=5,744.99 2006.231.07:46:11.92#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.07:46:11.92#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.07:46:11.92#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:11.92#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:46:11.92#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:46:11.92#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:46:11.92#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:46:11.92#ibcon#first serial, iclass 7, count 0 2006.231.07:46:11.92#ibcon#enter sib2, iclass 7, count 0 2006.231.07:46:11.92#ibcon#flushed, iclass 7, count 0 2006.231.07:46:11.92#ibcon#about to write, iclass 7, count 0 2006.231.07:46:11.92#ibcon#wrote, iclass 7, count 0 2006.231.07:46:11.92#ibcon#about to read 3, iclass 7, count 0 2006.231.07:46:11.94#ibcon#read 3, iclass 7, count 0 2006.231.07:46:11.94#ibcon#about to read 4, iclass 7, count 0 2006.231.07:46:11.94#ibcon#read 4, iclass 7, count 0 2006.231.07:46:11.94#ibcon#about to read 5, iclass 7, count 0 2006.231.07:46:11.94#ibcon#read 5, iclass 7, count 0 2006.231.07:46:11.94#ibcon#about to read 6, iclass 7, count 0 2006.231.07:46:11.94#ibcon#read 6, iclass 7, count 0 2006.231.07:46:11.94#ibcon#end of sib2, iclass 7, count 0 2006.231.07:46:11.94#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:46:11.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:46:11.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:46:11.94#ibcon#*before write, iclass 7, count 0 2006.231.07:46:11.94#ibcon#enter sib2, iclass 7, count 0 2006.231.07:46:11.94#ibcon#flushed, iclass 7, count 0 2006.231.07:46:11.94#ibcon#about to write, iclass 7, count 0 2006.231.07:46:11.94#ibcon#wrote, iclass 7, count 0 2006.231.07:46:11.94#ibcon#about to read 3, iclass 7, count 0 2006.231.07:46:11.98#ibcon#read 3, iclass 7, count 0 2006.231.07:46:11.98#ibcon#about to read 4, iclass 7, count 0 2006.231.07:46:11.98#ibcon#read 4, iclass 7, count 0 2006.231.07:46:11.98#ibcon#about to read 5, iclass 7, count 0 2006.231.07:46:11.98#ibcon#read 5, iclass 7, count 0 2006.231.07:46:11.98#ibcon#about to read 6, iclass 7, count 0 2006.231.07:46:11.98#ibcon#read 6, iclass 7, count 0 2006.231.07:46:11.98#ibcon#end of sib2, iclass 7, count 0 2006.231.07:46:11.98#ibcon#*after write, iclass 7, count 0 2006.231.07:46:11.98#ibcon#*before return 0, iclass 7, count 0 2006.231.07:46:11.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:46:11.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:46:11.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:46:11.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:46:11.98$vc4f8/vb=5,3 2006.231.07:46:11.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.07:46:11.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.07:46:11.98#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:11.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:46:12.04#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:46:12.04#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:46:12.04#ibcon#enter wrdev, iclass 11, count 2 2006.231.07:46:12.04#ibcon#first serial, iclass 11, count 2 2006.231.07:46:12.04#ibcon#enter sib2, iclass 11, count 2 2006.231.07:46:12.04#ibcon#flushed, iclass 11, count 2 2006.231.07:46:12.04#ibcon#about to write, iclass 11, count 2 2006.231.07:46:12.04#ibcon#wrote, iclass 11, count 2 2006.231.07:46:12.04#ibcon#about to read 3, iclass 11, count 2 2006.231.07:46:12.06#ibcon#read 3, iclass 11, count 2 2006.231.07:46:12.06#ibcon#about to read 4, iclass 11, count 2 2006.231.07:46:12.06#ibcon#read 4, iclass 11, count 2 2006.231.07:46:12.06#ibcon#about to read 5, iclass 11, count 2 2006.231.07:46:12.06#ibcon#read 5, iclass 11, count 2 2006.231.07:46:12.06#ibcon#about to read 6, iclass 11, count 2 2006.231.07:46:12.06#ibcon#read 6, iclass 11, count 2 2006.231.07:46:12.06#ibcon#end of sib2, iclass 11, count 2 2006.231.07:46:12.06#ibcon#*mode == 0, iclass 11, count 2 2006.231.07:46:12.06#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.07:46:12.06#ibcon#[27=AT05-03\r\n] 2006.231.07:46:12.06#ibcon#*before write, iclass 11, count 2 2006.231.07:46:12.06#ibcon#enter sib2, iclass 11, count 2 2006.231.07:46:12.06#ibcon#flushed, iclass 11, count 2 2006.231.07:46:12.06#ibcon#about to write, iclass 11, count 2 2006.231.07:46:12.06#ibcon#wrote, iclass 11, count 2 2006.231.07:46:12.06#ibcon#about to read 3, iclass 11, count 2 2006.231.07:46:12.09#ibcon#read 3, iclass 11, count 2 2006.231.07:46:12.09#ibcon#about to read 4, iclass 11, count 2 2006.231.07:46:12.09#ibcon#read 4, iclass 11, count 2 2006.231.07:46:12.09#ibcon#about to read 5, iclass 11, count 2 2006.231.07:46:12.09#ibcon#read 5, iclass 11, count 2 2006.231.07:46:12.09#ibcon#about to read 6, iclass 11, count 2 2006.231.07:46:12.09#ibcon#read 6, iclass 11, count 2 2006.231.07:46:12.09#ibcon#end of sib2, iclass 11, count 2 2006.231.07:46:12.09#ibcon#*after write, iclass 11, count 2 2006.231.07:46:12.09#ibcon#*before return 0, iclass 11, count 2 2006.231.07:46:12.09#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:46:12.09#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:46:12.09#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.07:46:12.09#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:12.09#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:46:12.21#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:46:12.21#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:46:12.21#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:46:12.21#ibcon#first serial, iclass 11, count 0 2006.231.07:46:12.21#ibcon#enter sib2, iclass 11, count 0 2006.231.07:46:12.21#ibcon#flushed, iclass 11, count 0 2006.231.07:46:12.21#ibcon#about to write, iclass 11, count 0 2006.231.07:46:12.21#ibcon#wrote, iclass 11, count 0 2006.231.07:46:12.21#ibcon#about to read 3, iclass 11, count 0 2006.231.07:46:12.23#ibcon#read 3, iclass 11, count 0 2006.231.07:46:12.23#ibcon#about to read 4, iclass 11, count 0 2006.231.07:46:12.23#ibcon#read 4, iclass 11, count 0 2006.231.07:46:12.23#ibcon#about to read 5, iclass 11, count 0 2006.231.07:46:12.23#ibcon#read 5, iclass 11, count 0 2006.231.07:46:12.23#ibcon#about to read 6, iclass 11, count 0 2006.231.07:46:12.23#ibcon#read 6, iclass 11, count 0 2006.231.07:46:12.23#ibcon#end of sib2, iclass 11, count 0 2006.231.07:46:12.23#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:46:12.23#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:46:12.23#ibcon#[27=USB\r\n] 2006.231.07:46:12.23#ibcon#*before write, iclass 11, count 0 2006.231.07:46:12.23#ibcon#enter sib2, iclass 11, count 0 2006.231.07:46:12.23#ibcon#flushed, iclass 11, count 0 2006.231.07:46:12.23#ibcon#about to write, iclass 11, count 0 2006.231.07:46:12.23#ibcon#wrote, iclass 11, count 0 2006.231.07:46:12.23#ibcon#about to read 3, iclass 11, count 0 2006.231.07:46:12.26#ibcon#read 3, iclass 11, count 0 2006.231.07:46:12.26#ibcon#about to read 4, iclass 11, count 0 2006.231.07:46:12.26#ibcon#read 4, iclass 11, count 0 2006.231.07:46:12.26#ibcon#about to read 5, iclass 11, count 0 2006.231.07:46:12.26#ibcon#read 5, iclass 11, count 0 2006.231.07:46:12.26#ibcon#about to read 6, iclass 11, count 0 2006.231.07:46:12.26#ibcon#read 6, iclass 11, count 0 2006.231.07:46:12.26#ibcon#end of sib2, iclass 11, count 0 2006.231.07:46:12.26#ibcon#*after write, iclass 11, count 0 2006.231.07:46:12.26#ibcon#*before return 0, iclass 11, count 0 2006.231.07:46:12.26#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:46:12.26#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:46:12.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:46:12.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:46:12.26$vc4f8/vblo=6,752.99 2006.231.07:46:12.26#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.07:46:12.26#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.07:46:12.26#ibcon#ireg 17 cls_cnt 0 2006.231.07:46:12.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:46:12.26#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:46:12.26#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:46:12.26#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:46:12.26#ibcon#first serial, iclass 13, count 0 2006.231.07:46:12.26#ibcon#enter sib2, iclass 13, count 0 2006.231.07:46:12.26#ibcon#flushed, iclass 13, count 0 2006.231.07:46:12.26#ibcon#about to write, iclass 13, count 0 2006.231.07:46:12.26#ibcon#wrote, iclass 13, count 0 2006.231.07:46:12.26#ibcon#about to read 3, iclass 13, count 0 2006.231.07:46:12.28#ibcon#read 3, iclass 13, count 0 2006.231.07:46:12.28#ibcon#about to read 4, iclass 13, count 0 2006.231.07:46:12.28#ibcon#read 4, iclass 13, count 0 2006.231.07:46:12.28#ibcon#about to read 5, iclass 13, count 0 2006.231.07:46:12.28#ibcon#read 5, iclass 13, count 0 2006.231.07:46:12.28#ibcon#about to read 6, iclass 13, count 0 2006.231.07:46:12.28#ibcon#read 6, iclass 13, count 0 2006.231.07:46:12.28#ibcon#end of sib2, iclass 13, count 0 2006.231.07:46:12.28#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:46:12.28#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:46:12.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:46:12.28#ibcon#*before write, iclass 13, count 0 2006.231.07:46:12.28#ibcon#enter sib2, iclass 13, count 0 2006.231.07:46:12.28#ibcon#flushed, iclass 13, count 0 2006.231.07:46:12.28#ibcon#about to write, iclass 13, count 0 2006.231.07:46:12.28#ibcon#wrote, iclass 13, count 0 2006.231.07:46:12.28#ibcon#about to read 3, iclass 13, count 0 2006.231.07:46:12.32#ibcon#read 3, iclass 13, count 0 2006.231.07:46:12.32#ibcon#about to read 4, iclass 13, count 0 2006.231.07:46:12.32#ibcon#read 4, iclass 13, count 0 2006.231.07:46:12.32#ibcon#about to read 5, iclass 13, count 0 2006.231.07:46:12.32#ibcon#read 5, iclass 13, count 0 2006.231.07:46:12.32#ibcon#about to read 6, iclass 13, count 0 2006.231.07:46:12.32#ibcon#read 6, iclass 13, count 0 2006.231.07:46:12.32#ibcon#end of sib2, iclass 13, count 0 2006.231.07:46:12.32#ibcon#*after write, iclass 13, count 0 2006.231.07:46:12.32#ibcon#*before return 0, iclass 13, count 0 2006.231.07:46:12.32#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:46:12.32#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:46:12.32#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:46:12.32#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:46:12.32$vc4f8/vb=6,4 2006.231.07:46:12.32#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.07:46:12.32#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.07:46:12.32#ibcon#ireg 11 cls_cnt 2 2006.231.07:46:12.32#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:46:12.38#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:46:12.38#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:46:12.38#ibcon#enter wrdev, iclass 15, count 2 2006.231.07:46:12.38#ibcon#first serial, iclass 15, count 2 2006.231.07:46:12.38#ibcon#enter sib2, iclass 15, count 2 2006.231.07:46:12.38#ibcon#flushed, iclass 15, count 2 2006.231.07:46:12.38#ibcon#about to write, iclass 15, count 2 2006.231.07:46:12.38#ibcon#wrote, iclass 15, count 2 2006.231.07:46:12.38#ibcon#about to read 3, iclass 15, count 2 2006.231.07:46:12.40#ibcon#read 3, iclass 15, count 2 2006.231.07:46:12.40#ibcon#about to read 4, iclass 15, count 2 2006.231.07:46:12.40#ibcon#read 4, iclass 15, count 2 2006.231.07:46:12.40#ibcon#about to read 5, iclass 15, count 2 2006.231.07:46:12.40#ibcon#read 5, iclass 15, count 2 2006.231.07:46:12.40#ibcon#about to read 6, iclass 15, count 2 2006.231.07:46:12.40#ibcon#read 6, iclass 15, count 2 2006.231.07:46:12.40#ibcon#end of sib2, iclass 15, count 2 2006.231.07:46:12.40#ibcon#*mode == 0, iclass 15, count 2 2006.231.07:46:12.40#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.07:46:12.40#ibcon#[27=AT06-04\r\n] 2006.231.07:46:12.40#ibcon#*before write, iclass 15, count 2 2006.231.07:46:12.40#ibcon#enter sib2, iclass 15, count 2 2006.231.07:46:12.40#ibcon#flushed, iclass 15, count 2 2006.231.07:46:12.40#ibcon#about to write, iclass 15, count 2 2006.231.07:46:12.40#ibcon#wrote, iclass 15, count 2 2006.231.07:46:12.40#ibcon#about to read 3, iclass 15, count 2 2006.231.07:46:12.43#ibcon#read 3, iclass 15, count 2 2006.231.07:46:12.43#ibcon#about to read 4, iclass 15, count 2 2006.231.07:46:12.43#ibcon#read 4, iclass 15, count 2 2006.231.07:46:12.43#ibcon#about to read 5, iclass 15, count 2 2006.231.07:46:12.43#ibcon#read 5, iclass 15, count 2 2006.231.07:46:12.43#ibcon#about to read 6, iclass 15, count 2 2006.231.07:46:12.43#ibcon#read 6, iclass 15, count 2 2006.231.07:46:12.43#ibcon#end of sib2, iclass 15, count 2 2006.231.07:46:12.43#ibcon#*after write, iclass 15, count 2 2006.231.07:46:12.43#ibcon#*before return 0, iclass 15, count 2 2006.231.07:46:12.43#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:46:12.43#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:46:12.43#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.07:46:12.43#ibcon#ireg 7 cls_cnt 0 2006.231.07:46:12.43#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:46:12.55#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:46:12.55#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:46:12.55#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:46:12.55#ibcon#first serial, iclass 15, count 0 2006.231.07:46:12.55#ibcon#enter sib2, iclass 15, count 0 2006.231.07:46:12.55#ibcon#flushed, iclass 15, count 0 2006.231.07:46:12.55#ibcon#about to write, iclass 15, count 0 2006.231.07:46:12.55#ibcon#wrote, iclass 15, count 0 2006.231.07:46:12.55#ibcon#about to read 3, iclass 15, count 0 2006.231.07:46:12.57#ibcon#read 3, iclass 15, count 0 2006.231.07:46:12.57#ibcon#about to read 4, iclass 15, count 0 2006.231.07:46:12.57#ibcon#read 4, iclass 15, count 0 2006.231.07:46:12.57#ibcon#about to read 5, iclass 15, count 0 2006.231.07:46:12.57#ibcon#read 5, iclass 15, count 0 2006.231.07:46:12.57#ibcon#about to read 6, iclass 15, count 0 2006.231.07:46:12.57#ibcon#read 6, iclass 15, count 0 2006.231.07:46:12.57#ibcon#end of sib2, iclass 15, count 0 2006.231.07:46:12.57#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:46:12.57#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:46:12.57#ibcon#[27=USB\r\n] 2006.231.07:46:12.57#ibcon#*before write, iclass 15, count 0 2006.231.07:46:12.57#ibcon#enter sib2, iclass 15, count 0 2006.231.07:46:12.57#ibcon#flushed, iclass 15, count 0 2006.231.07:46:12.57#ibcon#about to write, iclass 15, count 0 2006.231.07:46:12.57#ibcon#wrote, iclass 15, count 0 2006.231.07:46:12.57#ibcon#about to read 3, iclass 15, count 0 2006.231.07:46:12.60#ibcon#read 3, iclass 15, count 0 2006.231.07:46:12.60#ibcon#about to read 4, iclass 15, count 0 2006.231.07:46:12.60#ibcon#read 4, iclass 15, count 0 2006.231.07:46:12.60#ibcon#about to read 5, iclass 15, count 0 2006.231.07:46:12.60#ibcon#read 5, iclass 15, count 0 2006.231.07:46:12.60#ibcon#about to read 6, iclass 15, count 0 2006.231.07:46:12.60#ibcon#read 6, iclass 15, count 0 2006.231.07:46:12.60#ibcon#end of sib2, iclass 15, count 0 2006.231.07:46:12.60#ibcon#*after write, iclass 15, count 0 2006.231.07:46:12.60#ibcon#*before return 0, iclass 15, count 0 2006.231.07:46:12.60#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:46:12.60#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:46:12.60#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:46:12.60#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:46:12.60$vc4f8/vabw=wide 2006.231.07:46:12.60#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.07:46:12.60#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.07:46:12.60#ibcon#ireg 8 cls_cnt 0 2006.231.07:46:12.60#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:46:12.60#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:46:12.60#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:46:12.60#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:46:12.60#ibcon#first serial, iclass 17, count 0 2006.231.07:46:12.60#ibcon#enter sib2, iclass 17, count 0 2006.231.07:46:12.60#ibcon#flushed, iclass 17, count 0 2006.231.07:46:12.60#ibcon#about to write, iclass 17, count 0 2006.231.07:46:12.60#ibcon#wrote, iclass 17, count 0 2006.231.07:46:12.60#ibcon#about to read 3, iclass 17, count 0 2006.231.07:46:12.62#ibcon#read 3, iclass 17, count 0 2006.231.07:46:12.62#ibcon#about to read 4, iclass 17, count 0 2006.231.07:46:12.62#ibcon#read 4, iclass 17, count 0 2006.231.07:46:12.62#ibcon#about to read 5, iclass 17, count 0 2006.231.07:46:12.62#ibcon#read 5, iclass 17, count 0 2006.231.07:46:12.62#ibcon#about to read 6, iclass 17, count 0 2006.231.07:46:12.62#ibcon#read 6, iclass 17, count 0 2006.231.07:46:12.62#ibcon#end of sib2, iclass 17, count 0 2006.231.07:46:12.62#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:46:12.62#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:46:12.62#ibcon#[25=BW32\r\n] 2006.231.07:46:12.62#ibcon#*before write, iclass 17, count 0 2006.231.07:46:12.62#ibcon#enter sib2, iclass 17, count 0 2006.231.07:46:12.62#ibcon#flushed, iclass 17, count 0 2006.231.07:46:12.62#ibcon#about to write, iclass 17, count 0 2006.231.07:46:12.62#ibcon#wrote, iclass 17, count 0 2006.231.07:46:12.62#ibcon#about to read 3, iclass 17, count 0 2006.231.07:46:12.65#ibcon#read 3, iclass 17, count 0 2006.231.07:46:12.65#ibcon#about to read 4, iclass 17, count 0 2006.231.07:46:12.65#ibcon#read 4, iclass 17, count 0 2006.231.07:46:12.65#ibcon#about to read 5, iclass 17, count 0 2006.231.07:46:12.65#ibcon#read 5, iclass 17, count 0 2006.231.07:46:12.65#ibcon#about to read 6, iclass 17, count 0 2006.231.07:46:12.65#ibcon#read 6, iclass 17, count 0 2006.231.07:46:12.65#ibcon#end of sib2, iclass 17, count 0 2006.231.07:46:12.65#ibcon#*after write, iclass 17, count 0 2006.231.07:46:12.65#ibcon#*before return 0, iclass 17, count 0 2006.231.07:46:12.65#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:46:12.65#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:46:12.65#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:46:12.65#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:46:12.65$vc4f8/vbbw=wide 2006.231.07:46:12.65#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.07:46:12.65#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.07:46:12.65#ibcon#ireg 8 cls_cnt 0 2006.231.07:46:12.65#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:46:12.72#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:46:12.72#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:46:12.72#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:46:12.72#ibcon#first serial, iclass 19, count 0 2006.231.07:46:12.72#ibcon#enter sib2, iclass 19, count 0 2006.231.07:46:12.72#ibcon#flushed, iclass 19, count 0 2006.231.07:46:12.72#ibcon#about to write, iclass 19, count 0 2006.231.07:46:12.72#ibcon#wrote, iclass 19, count 0 2006.231.07:46:12.72#ibcon#about to read 3, iclass 19, count 0 2006.231.07:46:12.74#ibcon#read 3, iclass 19, count 0 2006.231.07:46:12.74#ibcon#about to read 4, iclass 19, count 0 2006.231.07:46:12.74#ibcon#read 4, iclass 19, count 0 2006.231.07:46:12.74#ibcon#about to read 5, iclass 19, count 0 2006.231.07:46:12.74#ibcon#read 5, iclass 19, count 0 2006.231.07:46:12.74#ibcon#about to read 6, iclass 19, count 0 2006.231.07:46:12.75#ibcon#read 6, iclass 19, count 0 2006.231.07:46:12.75#ibcon#end of sib2, iclass 19, count 0 2006.231.07:46:12.75#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:46:12.75#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:46:12.75#ibcon#[27=BW32\r\n] 2006.231.07:46:12.75#ibcon#*before write, iclass 19, count 0 2006.231.07:46:12.75#ibcon#enter sib2, iclass 19, count 0 2006.231.07:46:12.75#ibcon#flushed, iclass 19, count 0 2006.231.07:46:12.75#ibcon#about to write, iclass 19, count 0 2006.231.07:46:12.75#ibcon#wrote, iclass 19, count 0 2006.231.07:46:12.75#ibcon#about to read 3, iclass 19, count 0 2006.231.07:46:12.77#ibcon#read 3, iclass 19, count 0 2006.231.07:46:12.77#ibcon#about to read 4, iclass 19, count 0 2006.231.07:46:12.77#ibcon#read 4, iclass 19, count 0 2006.231.07:46:12.77#ibcon#about to read 5, iclass 19, count 0 2006.231.07:46:12.77#ibcon#read 5, iclass 19, count 0 2006.231.07:46:12.77#ibcon#about to read 6, iclass 19, count 0 2006.231.07:46:12.77#ibcon#read 6, iclass 19, count 0 2006.231.07:46:12.77#ibcon#end of sib2, iclass 19, count 0 2006.231.07:46:12.77#ibcon#*after write, iclass 19, count 0 2006.231.07:46:12.77#ibcon#*before return 0, iclass 19, count 0 2006.231.07:46:12.77#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:46:12.77#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:46:12.77#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:46:12.77#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:46:12.77$4f8m12a/ifd4f 2006.231.07:46:12.77$ifd4f/lo= 2006.231.07:46:12.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:46:12.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:46:12.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:46:12.77$ifd4f/patch= 2006.231.07:46:12.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:46:12.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:46:12.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:46:12.77$4f8m12a/"form=m,16.000,1:2 2006.231.07:46:12.77$4f8m12a/"tpicd 2006.231.07:46:12.77$4f8m12a/echo=off 2006.231.07:46:12.77$4f8m12a/xlog=off 2006.231.07:46:12.77:!2006.231.07:47:20 2006.231.07:46:57.14#trakl#Source acquired 2006.231.07:46:57.14#flagr#flagr/antenna,acquired 2006.231.07:47:20.00:preob 2006.231.07:47:20.14/onsource/TRACKING 2006.231.07:47:20.14:!2006.231.07:47:30 2006.231.07:47:30.00:data_valid=on 2006.231.07:47:30.00:midob 2006.231.07:47:30.14/onsource/TRACKING 2006.231.07:47:30.14/wx/30.60,1004.4,84 2006.231.07:47:30.34/cable/+6.3717E-03 2006.231.07:47:31.43/va/01,08,usb,yes,29,31 2006.231.07:47:31.43/va/02,07,usb,yes,29,31 2006.231.07:47:31.43/va/03,08,usb,yes,22,22 2006.231.07:47:31.43/va/04,07,usb,yes,31,33 2006.231.07:47:31.43/va/05,07,usb,yes,34,36 2006.231.07:47:31.43/va/06,06,usb,yes,33,33 2006.231.07:47:31.43/va/07,06,usb,yes,34,34 2006.231.07:47:31.43/va/08,06,usb,yes,36,36 2006.231.07:47:31.66/valo/01,532.99,yes,locked 2006.231.07:47:31.66/valo/02,572.99,yes,locked 2006.231.07:47:31.66/valo/03,672.99,yes,locked 2006.231.07:47:31.66/valo/04,832.99,yes,locked 2006.231.07:47:31.66/valo/05,652.99,yes,locked 2006.231.07:47:31.66/valo/06,772.99,yes,locked 2006.231.07:47:31.66/valo/07,832.99,yes,locked 2006.231.07:47:31.66/valo/08,852.99,yes,locked 2006.231.07:47:32.75/vb/01,04,usb,yes,30,29 2006.231.07:47:32.75/vb/02,04,usb,yes,32,34 2006.231.07:47:32.75/vb/03,04,usb,yes,29,32 2006.231.07:47:32.75/vb/04,04,usb,yes,29,30 2006.231.07:47:32.75/vb/05,03,usb,yes,35,39 2006.231.07:47:32.75/vb/06,04,usb,yes,29,32 2006.231.07:47:32.75/vb/07,04,usb,yes,31,31 2006.231.07:47:32.75/vb/08,04,usb,yes,28,32 2006.231.07:47:32.99/vblo/01,632.99,yes,locked 2006.231.07:47:32.99/vblo/02,640.99,yes,locked 2006.231.07:47:32.99/vblo/03,656.99,yes,locked 2006.231.07:47:32.99/vblo/04,712.99,yes,locked 2006.231.07:47:32.99/vblo/05,744.99,yes,locked 2006.231.07:47:32.99/vblo/06,752.99,yes,locked 2006.231.07:47:32.99/vblo/07,734.99,yes,locked 2006.231.07:47:32.99/vblo/08,744.99,yes,locked 2006.231.07:47:33.14/vabw/8 2006.231.07:47:33.29/vbbw/8 2006.231.07:47:33.38/xfe/off,on,12.5 2006.231.07:47:33.76/ifatt/23,28,28,28 2006.231.07:47:34.08/fmout-gps/S +4.43E-07 2006.231.07:47:34.12:!2006.231.07:48:30 2006.231.07:48:30.00:data_valid=off 2006.231.07:48:30.00:postob 2006.231.07:48:30.14/cable/+6.3716E-03 2006.231.07:48:30.14/wx/30.59,1004.4,84 2006.231.07:48:31.08/fmout-gps/S +4.44E-07 2006.231.07:48:31.08:scan_name=231-0749,k06231,60 2006.231.07:48:31.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.231.07:48:31.14#flagr#flagr/antenna,new-source 2006.231.07:48:32.14:checkk5 2006.231.07:48:32.48/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:48:32.86/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:48:33.24/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:48:33.61/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:48:33.97/chk_obsdata//k5ts1/T2310747??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:48:34.34/chk_obsdata//k5ts2/T2310747??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:48:34.71/chk_obsdata//k5ts3/T2310747??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:48:35.08/chk_obsdata//k5ts4/T2310747??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:48:35.76/k5log//k5ts1_log_newline 2006.231.07:48:36.45/k5log//k5ts2_log_newline 2006.231.07:48:37.14/k5log//k5ts3_log_newline 2006.231.07:48:37.83/k5log//k5ts4_log_newline 2006.231.07:48:37.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:48:37.85:4f8m12a=1 2006.231.07:48:37.85$4f8m12a/echo=on 2006.231.07:48:37.85$4f8m12a/pcalon 2006.231.07:48:37.85$pcalon/"no phase cal control is implemented here 2006.231.07:48:37.85$4f8m12a/"tpicd=stop 2006.231.07:48:37.85$4f8m12a/vc4f8 2006.231.07:48:37.85$vc4f8/valo=1,532.99 2006.231.07:48:37.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.07:48:37.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.07:48:37.85#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:37.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:48:37.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:48:37.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:48:37.85#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:48:37.85#ibcon#first serial, iclass 10, count 0 2006.231.07:48:37.85#ibcon#enter sib2, iclass 10, count 0 2006.231.07:48:37.85#ibcon#flushed, iclass 10, count 0 2006.231.07:48:37.85#ibcon#about to write, iclass 10, count 0 2006.231.07:48:37.85#ibcon#wrote, iclass 10, count 0 2006.231.07:48:37.85#ibcon#about to read 3, iclass 10, count 0 2006.231.07:48:37.87#ibcon#read 3, iclass 10, count 0 2006.231.07:48:37.87#ibcon#about to read 4, iclass 10, count 0 2006.231.07:48:37.87#ibcon#read 4, iclass 10, count 0 2006.231.07:48:37.87#ibcon#about to read 5, iclass 10, count 0 2006.231.07:48:37.87#ibcon#read 5, iclass 10, count 0 2006.231.07:48:37.87#ibcon#about to read 6, iclass 10, count 0 2006.231.07:48:37.87#ibcon#read 6, iclass 10, count 0 2006.231.07:48:37.87#ibcon#end of sib2, iclass 10, count 0 2006.231.07:48:37.87#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:48:37.87#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:48:37.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:48:37.87#ibcon#*before write, iclass 10, count 0 2006.231.07:48:37.87#ibcon#enter sib2, iclass 10, count 0 2006.231.07:48:37.87#ibcon#flushed, iclass 10, count 0 2006.231.07:48:37.87#ibcon#about to write, iclass 10, count 0 2006.231.07:48:37.87#ibcon#wrote, iclass 10, count 0 2006.231.07:48:37.87#ibcon#about to read 3, iclass 10, count 0 2006.231.07:48:37.92#ibcon#read 3, iclass 10, count 0 2006.231.07:48:37.92#ibcon#about to read 4, iclass 10, count 0 2006.231.07:48:37.92#ibcon#read 4, iclass 10, count 0 2006.231.07:48:37.92#ibcon#about to read 5, iclass 10, count 0 2006.231.07:48:37.92#ibcon#read 5, iclass 10, count 0 2006.231.07:48:37.92#ibcon#about to read 6, iclass 10, count 0 2006.231.07:48:37.92#ibcon#read 6, iclass 10, count 0 2006.231.07:48:37.92#ibcon#end of sib2, iclass 10, count 0 2006.231.07:48:37.92#ibcon#*after write, iclass 10, count 0 2006.231.07:48:37.92#ibcon#*before return 0, iclass 10, count 0 2006.231.07:48:37.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:48:37.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:48:37.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:48:37.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:48:37.92$vc4f8/va=1,8 2006.231.07:48:37.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.07:48:37.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.07:48:37.92#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:37.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:48:37.92#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:48:37.92#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:48:37.92#ibcon#enter wrdev, iclass 12, count 2 2006.231.07:48:37.92#ibcon#first serial, iclass 12, count 2 2006.231.07:48:37.92#ibcon#enter sib2, iclass 12, count 2 2006.231.07:48:37.92#ibcon#flushed, iclass 12, count 2 2006.231.07:48:37.92#ibcon#about to write, iclass 12, count 2 2006.231.07:48:37.92#ibcon#wrote, iclass 12, count 2 2006.231.07:48:37.92#ibcon#about to read 3, iclass 12, count 2 2006.231.07:48:37.94#ibcon#read 3, iclass 12, count 2 2006.231.07:48:37.94#ibcon#about to read 4, iclass 12, count 2 2006.231.07:48:37.94#ibcon#read 4, iclass 12, count 2 2006.231.07:48:37.94#ibcon#about to read 5, iclass 12, count 2 2006.231.07:48:37.94#ibcon#read 5, iclass 12, count 2 2006.231.07:48:37.94#ibcon#about to read 6, iclass 12, count 2 2006.231.07:48:37.94#ibcon#read 6, iclass 12, count 2 2006.231.07:48:37.94#ibcon#end of sib2, iclass 12, count 2 2006.231.07:48:37.94#ibcon#*mode == 0, iclass 12, count 2 2006.231.07:48:37.94#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.07:48:37.94#ibcon#[25=AT01-08\r\n] 2006.231.07:48:37.94#ibcon#*before write, iclass 12, count 2 2006.231.07:48:37.94#ibcon#enter sib2, iclass 12, count 2 2006.231.07:48:37.94#ibcon#flushed, iclass 12, count 2 2006.231.07:48:37.94#ibcon#about to write, iclass 12, count 2 2006.231.07:48:37.94#ibcon#wrote, iclass 12, count 2 2006.231.07:48:37.94#ibcon#about to read 3, iclass 12, count 2 2006.231.07:48:37.97#ibcon#read 3, iclass 12, count 2 2006.231.07:48:37.97#ibcon#about to read 4, iclass 12, count 2 2006.231.07:48:37.97#ibcon#read 4, iclass 12, count 2 2006.231.07:48:37.97#ibcon#about to read 5, iclass 12, count 2 2006.231.07:48:37.97#ibcon#read 5, iclass 12, count 2 2006.231.07:48:37.97#ibcon#about to read 6, iclass 12, count 2 2006.231.07:48:37.97#ibcon#read 6, iclass 12, count 2 2006.231.07:48:37.97#ibcon#end of sib2, iclass 12, count 2 2006.231.07:48:37.97#ibcon#*after write, iclass 12, count 2 2006.231.07:48:37.97#ibcon#*before return 0, iclass 12, count 2 2006.231.07:48:37.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:48:37.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:48:37.97#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.07:48:37.97#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:37.97#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:48:38.09#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:48:38.09#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:48:38.09#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:48:38.09#ibcon#first serial, iclass 12, count 0 2006.231.07:48:38.09#ibcon#enter sib2, iclass 12, count 0 2006.231.07:48:38.09#ibcon#flushed, iclass 12, count 0 2006.231.07:48:38.09#ibcon#about to write, iclass 12, count 0 2006.231.07:48:38.09#ibcon#wrote, iclass 12, count 0 2006.231.07:48:38.09#ibcon#about to read 3, iclass 12, count 0 2006.231.07:48:38.11#ibcon#read 3, iclass 12, count 0 2006.231.07:48:38.11#ibcon#about to read 4, iclass 12, count 0 2006.231.07:48:38.11#ibcon#read 4, iclass 12, count 0 2006.231.07:48:38.11#ibcon#about to read 5, iclass 12, count 0 2006.231.07:48:38.11#ibcon#read 5, iclass 12, count 0 2006.231.07:48:38.11#ibcon#about to read 6, iclass 12, count 0 2006.231.07:48:38.11#ibcon#read 6, iclass 12, count 0 2006.231.07:48:38.11#ibcon#end of sib2, iclass 12, count 0 2006.231.07:48:38.11#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:48:38.11#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:48:38.11#ibcon#[25=USB\r\n] 2006.231.07:48:38.11#ibcon#*before write, iclass 12, count 0 2006.231.07:48:38.11#ibcon#enter sib2, iclass 12, count 0 2006.231.07:48:38.11#ibcon#flushed, iclass 12, count 0 2006.231.07:48:38.11#ibcon#about to write, iclass 12, count 0 2006.231.07:48:38.11#ibcon#wrote, iclass 12, count 0 2006.231.07:48:38.11#ibcon#about to read 3, iclass 12, count 0 2006.231.07:48:38.14#ibcon#read 3, iclass 12, count 0 2006.231.07:48:38.14#ibcon#about to read 4, iclass 12, count 0 2006.231.07:48:38.14#ibcon#read 4, iclass 12, count 0 2006.231.07:48:38.14#ibcon#about to read 5, iclass 12, count 0 2006.231.07:48:38.14#ibcon#read 5, iclass 12, count 0 2006.231.07:48:38.14#ibcon#about to read 6, iclass 12, count 0 2006.231.07:48:38.14#ibcon#read 6, iclass 12, count 0 2006.231.07:48:38.14#ibcon#end of sib2, iclass 12, count 0 2006.231.07:48:38.14#ibcon#*after write, iclass 12, count 0 2006.231.07:48:38.14#ibcon#*before return 0, iclass 12, count 0 2006.231.07:48:38.14#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:48:38.14#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:48:38.14#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:48:38.14#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:48:38.14$vc4f8/valo=2,572.99 2006.231.07:48:38.14#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.07:48:38.14#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.07:48:38.14#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:38.14#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:48:38.14#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:48:38.14#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:48:38.14#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:48:38.14#ibcon#first serial, iclass 14, count 0 2006.231.07:48:38.14#ibcon#enter sib2, iclass 14, count 0 2006.231.07:48:38.14#ibcon#flushed, iclass 14, count 0 2006.231.07:48:38.14#ibcon#about to write, iclass 14, count 0 2006.231.07:48:38.14#ibcon#wrote, iclass 14, count 0 2006.231.07:48:38.14#ibcon#about to read 3, iclass 14, count 0 2006.231.07:48:38.17#ibcon#read 3, iclass 14, count 0 2006.231.07:48:38.17#ibcon#about to read 4, iclass 14, count 0 2006.231.07:48:38.17#ibcon#read 4, iclass 14, count 0 2006.231.07:48:38.17#ibcon#about to read 5, iclass 14, count 0 2006.231.07:48:38.17#ibcon#read 5, iclass 14, count 0 2006.231.07:48:38.17#ibcon#about to read 6, iclass 14, count 0 2006.231.07:48:38.17#ibcon#read 6, iclass 14, count 0 2006.231.07:48:38.17#ibcon#end of sib2, iclass 14, count 0 2006.231.07:48:38.17#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:48:38.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:48:38.17#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:48:38.17#ibcon#*before write, iclass 14, count 0 2006.231.07:48:38.17#ibcon#enter sib2, iclass 14, count 0 2006.231.07:48:38.17#ibcon#flushed, iclass 14, count 0 2006.231.07:48:38.17#ibcon#about to write, iclass 14, count 0 2006.231.07:48:38.17#ibcon#wrote, iclass 14, count 0 2006.231.07:48:38.17#ibcon#about to read 3, iclass 14, count 0 2006.231.07:48:38.21#ibcon#read 3, iclass 14, count 0 2006.231.07:48:38.21#ibcon#about to read 4, iclass 14, count 0 2006.231.07:48:38.21#ibcon#read 4, iclass 14, count 0 2006.231.07:48:38.21#ibcon#about to read 5, iclass 14, count 0 2006.231.07:48:38.21#ibcon#read 5, iclass 14, count 0 2006.231.07:48:38.21#ibcon#about to read 6, iclass 14, count 0 2006.231.07:48:38.21#ibcon#read 6, iclass 14, count 0 2006.231.07:48:38.21#ibcon#end of sib2, iclass 14, count 0 2006.231.07:48:38.21#ibcon#*after write, iclass 14, count 0 2006.231.07:48:38.21#ibcon#*before return 0, iclass 14, count 0 2006.231.07:48:38.21#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:48:38.21#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:48:38.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:48:38.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:48:38.21$vc4f8/va=2,7 2006.231.07:48:38.21#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.07:48:38.21#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.07:48:38.21#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:38.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:48:38.26#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:48:38.26#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:48:38.26#ibcon#enter wrdev, iclass 16, count 2 2006.231.07:48:38.26#ibcon#first serial, iclass 16, count 2 2006.231.07:48:38.26#ibcon#enter sib2, iclass 16, count 2 2006.231.07:48:38.26#ibcon#flushed, iclass 16, count 2 2006.231.07:48:38.26#ibcon#about to write, iclass 16, count 2 2006.231.07:48:38.26#ibcon#wrote, iclass 16, count 2 2006.231.07:48:38.26#ibcon#about to read 3, iclass 16, count 2 2006.231.07:48:38.28#ibcon#read 3, iclass 16, count 2 2006.231.07:48:38.28#ibcon#about to read 4, iclass 16, count 2 2006.231.07:48:38.28#ibcon#read 4, iclass 16, count 2 2006.231.07:48:38.28#ibcon#about to read 5, iclass 16, count 2 2006.231.07:48:38.28#ibcon#read 5, iclass 16, count 2 2006.231.07:48:38.28#ibcon#about to read 6, iclass 16, count 2 2006.231.07:48:38.28#ibcon#read 6, iclass 16, count 2 2006.231.07:48:38.28#ibcon#end of sib2, iclass 16, count 2 2006.231.07:48:38.28#ibcon#*mode == 0, iclass 16, count 2 2006.231.07:48:38.28#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.07:48:38.28#ibcon#[25=AT02-07\r\n] 2006.231.07:48:38.28#ibcon#*before write, iclass 16, count 2 2006.231.07:48:38.28#ibcon#enter sib2, iclass 16, count 2 2006.231.07:48:38.28#ibcon#flushed, iclass 16, count 2 2006.231.07:48:38.28#ibcon#about to write, iclass 16, count 2 2006.231.07:48:38.28#ibcon#wrote, iclass 16, count 2 2006.231.07:48:38.28#ibcon#about to read 3, iclass 16, count 2 2006.231.07:48:38.31#ibcon#read 3, iclass 16, count 2 2006.231.07:48:38.31#ibcon#about to read 4, iclass 16, count 2 2006.231.07:48:38.31#ibcon#read 4, iclass 16, count 2 2006.231.07:48:38.31#ibcon#about to read 5, iclass 16, count 2 2006.231.07:48:38.31#ibcon#read 5, iclass 16, count 2 2006.231.07:48:38.31#ibcon#about to read 6, iclass 16, count 2 2006.231.07:48:38.31#ibcon#read 6, iclass 16, count 2 2006.231.07:48:38.31#ibcon#end of sib2, iclass 16, count 2 2006.231.07:48:38.31#ibcon#*after write, iclass 16, count 2 2006.231.07:48:38.31#ibcon#*before return 0, iclass 16, count 2 2006.231.07:48:38.31#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:48:38.31#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:48:38.31#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.07:48:38.31#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:38.31#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:48:38.43#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:48:38.43#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:48:38.43#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:48:38.43#ibcon#first serial, iclass 16, count 0 2006.231.07:48:38.43#ibcon#enter sib2, iclass 16, count 0 2006.231.07:48:38.43#ibcon#flushed, iclass 16, count 0 2006.231.07:48:38.43#ibcon#about to write, iclass 16, count 0 2006.231.07:48:38.43#ibcon#wrote, iclass 16, count 0 2006.231.07:48:38.43#ibcon#about to read 3, iclass 16, count 0 2006.231.07:48:38.45#ibcon#read 3, iclass 16, count 0 2006.231.07:48:38.45#ibcon#about to read 4, iclass 16, count 0 2006.231.07:48:38.45#ibcon#read 4, iclass 16, count 0 2006.231.07:48:38.45#ibcon#about to read 5, iclass 16, count 0 2006.231.07:48:38.45#ibcon#read 5, iclass 16, count 0 2006.231.07:48:38.45#ibcon#about to read 6, iclass 16, count 0 2006.231.07:48:38.45#ibcon#read 6, iclass 16, count 0 2006.231.07:48:38.45#ibcon#end of sib2, iclass 16, count 0 2006.231.07:48:38.45#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:48:38.45#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:48:38.45#ibcon#[25=USB\r\n] 2006.231.07:48:38.45#ibcon#*before write, iclass 16, count 0 2006.231.07:48:38.45#ibcon#enter sib2, iclass 16, count 0 2006.231.07:48:38.45#ibcon#flushed, iclass 16, count 0 2006.231.07:48:38.45#ibcon#about to write, iclass 16, count 0 2006.231.07:48:38.45#ibcon#wrote, iclass 16, count 0 2006.231.07:48:38.45#ibcon#about to read 3, iclass 16, count 0 2006.231.07:48:38.48#ibcon#read 3, iclass 16, count 0 2006.231.07:48:38.48#ibcon#about to read 4, iclass 16, count 0 2006.231.07:48:38.48#ibcon#read 4, iclass 16, count 0 2006.231.07:48:38.48#ibcon#about to read 5, iclass 16, count 0 2006.231.07:48:38.48#ibcon#read 5, iclass 16, count 0 2006.231.07:48:38.48#ibcon#about to read 6, iclass 16, count 0 2006.231.07:48:38.48#ibcon#read 6, iclass 16, count 0 2006.231.07:48:38.48#ibcon#end of sib2, iclass 16, count 0 2006.231.07:48:38.48#ibcon#*after write, iclass 16, count 0 2006.231.07:48:38.48#ibcon#*before return 0, iclass 16, count 0 2006.231.07:48:38.48#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:48:38.48#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:48:38.48#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:48:38.48#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:48:38.48$vc4f8/valo=3,672.99 2006.231.07:48:38.48#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.07:48:38.48#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.07:48:38.48#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:38.48#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:48:38.48#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:48:38.48#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:48:38.48#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:48:38.48#ibcon#first serial, iclass 18, count 0 2006.231.07:48:38.48#ibcon#enter sib2, iclass 18, count 0 2006.231.07:48:38.48#ibcon#flushed, iclass 18, count 0 2006.231.07:48:38.48#ibcon#about to write, iclass 18, count 0 2006.231.07:48:38.48#ibcon#wrote, iclass 18, count 0 2006.231.07:48:38.48#ibcon#about to read 3, iclass 18, count 0 2006.231.07:48:38.50#ibcon#read 3, iclass 18, count 0 2006.231.07:48:38.50#ibcon#about to read 4, iclass 18, count 0 2006.231.07:48:38.50#ibcon#read 4, iclass 18, count 0 2006.231.07:48:38.50#ibcon#about to read 5, iclass 18, count 0 2006.231.07:48:38.50#ibcon#read 5, iclass 18, count 0 2006.231.07:48:38.50#ibcon#about to read 6, iclass 18, count 0 2006.231.07:48:38.50#ibcon#read 6, iclass 18, count 0 2006.231.07:48:38.50#ibcon#end of sib2, iclass 18, count 0 2006.231.07:48:38.50#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:48:38.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:48:38.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:48:38.50#ibcon#*before write, iclass 18, count 0 2006.231.07:48:38.50#ibcon#enter sib2, iclass 18, count 0 2006.231.07:48:38.50#ibcon#flushed, iclass 18, count 0 2006.231.07:48:38.50#ibcon#about to write, iclass 18, count 0 2006.231.07:48:38.50#ibcon#wrote, iclass 18, count 0 2006.231.07:48:38.50#ibcon#about to read 3, iclass 18, count 0 2006.231.07:48:38.54#ibcon#read 3, iclass 18, count 0 2006.231.07:48:38.54#ibcon#about to read 4, iclass 18, count 0 2006.231.07:48:38.54#ibcon#read 4, iclass 18, count 0 2006.231.07:48:38.54#ibcon#about to read 5, iclass 18, count 0 2006.231.07:48:38.54#ibcon#read 5, iclass 18, count 0 2006.231.07:48:38.54#ibcon#about to read 6, iclass 18, count 0 2006.231.07:48:38.54#ibcon#read 6, iclass 18, count 0 2006.231.07:48:38.54#ibcon#end of sib2, iclass 18, count 0 2006.231.07:48:38.54#ibcon#*after write, iclass 18, count 0 2006.231.07:48:38.54#ibcon#*before return 0, iclass 18, count 0 2006.231.07:48:38.54#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:48:38.54#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:48:38.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:48:38.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:48:38.54$vc4f8/va=3,8 2006.231.07:48:38.54#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.07:48:38.54#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.07:48:38.54#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:38.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:48:38.60#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:48:38.60#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:48:38.60#ibcon#enter wrdev, iclass 20, count 2 2006.231.07:48:38.60#ibcon#first serial, iclass 20, count 2 2006.231.07:48:38.60#ibcon#enter sib2, iclass 20, count 2 2006.231.07:48:38.60#ibcon#flushed, iclass 20, count 2 2006.231.07:48:38.60#ibcon#about to write, iclass 20, count 2 2006.231.07:48:38.60#ibcon#wrote, iclass 20, count 2 2006.231.07:48:38.60#ibcon#about to read 3, iclass 20, count 2 2006.231.07:48:38.62#ibcon#read 3, iclass 20, count 2 2006.231.07:48:38.62#ibcon#about to read 4, iclass 20, count 2 2006.231.07:48:38.62#ibcon#read 4, iclass 20, count 2 2006.231.07:48:38.62#ibcon#about to read 5, iclass 20, count 2 2006.231.07:48:38.62#ibcon#read 5, iclass 20, count 2 2006.231.07:48:38.62#ibcon#about to read 6, iclass 20, count 2 2006.231.07:48:38.62#ibcon#read 6, iclass 20, count 2 2006.231.07:48:38.62#ibcon#end of sib2, iclass 20, count 2 2006.231.07:48:38.62#ibcon#*mode == 0, iclass 20, count 2 2006.231.07:48:38.62#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.07:48:38.62#ibcon#[25=AT03-08\r\n] 2006.231.07:48:38.62#ibcon#*before write, iclass 20, count 2 2006.231.07:48:38.62#ibcon#enter sib2, iclass 20, count 2 2006.231.07:48:38.62#ibcon#flushed, iclass 20, count 2 2006.231.07:48:38.62#ibcon#about to write, iclass 20, count 2 2006.231.07:48:38.62#ibcon#wrote, iclass 20, count 2 2006.231.07:48:38.62#ibcon#about to read 3, iclass 20, count 2 2006.231.07:48:38.65#ibcon#read 3, iclass 20, count 2 2006.231.07:48:38.65#ibcon#about to read 4, iclass 20, count 2 2006.231.07:48:38.65#ibcon#read 4, iclass 20, count 2 2006.231.07:48:38.65#ibcon#about to read 5, iclass 20, count 2 2006.231.07:48:38.65#ibcon#read 5, iclass 20, count 2 2006.231.07:48:38.65#ibcon#about to read 6, iclass 20, count 2 2006.231.07:48:38.65#ibcon#read 6, iclass 20, count 2 2006.231.07:48:38.65#ibcon#end of sib2, iclass 20, count 2 2006.231.07:48:38.65#ibcon#*after write, iclass 20, count 2 2006.231.07:48:38.65#ibcon#*before return 0, iclass 20, count 2 2006.231.07:48:38.65#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:48:38.65#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:48:38.65#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.07:48:38.65#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:38.65#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:48:38.77#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:48:38.77#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:48:38.77#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:48:38.77#ibcon#first serial, iclass 20, count 0 2006.231.07:48:38.77#ibcon#enter sib2, iclass 20, count 0 2006.231.07:48:38.77#ibcon#flushed, iclass 20, count 0 2006.231.07:48:38.77#ibcon#about to write, iclass 20, count 0 2006.231.07:48:38.77#ibcon#wrote, iclass 20, count 0 2006.231.07:48:38.77#ibcon#about to read 3, iclass 20, count 0 2006.231.07:48:38.79#ibcon#read 3, iclass 20, count 0 2006.231.07:48:38.79#ibcon#about to read 4, iclass 20, count 0 2006.231.07:48:38.79#ibcon#read 4, iclass 20, count 0 2006.231.07:48:38.79#ibcon#about to read 5, iclass 20, count 0 2006.231.07:48:38.79#ibcon#read 5, iclass 20, count 0 2006.231.07:48:38.79#ibcon#about to read 6, iclass 20, count 0 2006.231.07:48:38.79#ibcon#read 6, iclass 20, count 0 2006.231.07:48:38.79#ibcon#end of sib2, iclass 20, count 0 2006.231.07:48:38.79#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:48:38.79#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:48:38.79#ibcon#[25=USB\r\n] 2006.231.07:48:38.79#ibcon#*before write, iclass 20, count 0 2006.231.07:48:38.79#ibcon#enter sib2, iclass 20, count 0 2006.231.07:48:38.79#ibcon#flushed, iclass 20, count 0 2006.231.07:48:38.79#ibcon#about to write, iclass 20, count 0 2006.231.07:48:38.79#ibcon#wrote, iclass 20, count 0 2006.231.07:48:38.79#ibcon#about to read 3, iclass 20, count 0 2006.231.07:48:38.82#ibcon#read 3, iclass 20, count 0 2006.231.07:48:38.82#ibcon#about to read 4, iclass 20, count 0 2006.231.07:48:38.82#ibcon#read 4, iclass 20, count 0 2006.231.07:48:38.82#ibcon#about to read 5, iclass 20, count 0 2006.231.07:48:38.82#ibcon#read 5, iclass 20, count 0 2006.231.07:48:38.82#ibcon#about to read 6, iclass 20, count 0 2006.231.07:48:38.82#ibcon#read 6, iclass 20, count 0 2006.231.07:48:38.82#ibcon#end of sib2, iclass 20, count 0 2006.231.07:48:38.82#ibcon#*after write, iclass 20, count 0 2006.231.07:48:38.82#ibcon#*before return 0, iclass 20, count 0 2006.231.07:48:38.82#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:48:38.82#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:48:38.82#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:48:38.82#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:48:38.82$vc4f8/valo=4,832.99 2006.231.07:48:38.82#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.07:48:38.82#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.07:48:38.82#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:38.82#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:48:38.82#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:48:38.82#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:48:38.82#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:48:38.82#ibcon#first serial, iclass 22, count 0 2006.231.07:48:38.82#ibcon#enter sib2, iclass 22, count 0 2006.231.07:48:38.82#ibcon#flushed, iclass 22, count 0 2006.231.07:48:38.82#ibcon#about to write, iclass 22, count 0 2006.231.07:48:38.82#ibcon#wrote, iclass 22, count 0 2006.231.07:48:38.82#ibcon#about to read 3, iclass 22, count 0 2006.231.07:48:38.84#ibcon#read 3, iclass 22, count 0 2006.231.07:48:38.84#ibcon#about to read 4, iclass 22, count 0 2006.231.07:48:38.84#ibcon#read 4, iclass 22, count 0 2006.231.07:48:38.84#ibcon#about to read 5, iclass 22, count 0 2006.231.07:48:38.84#ibcon#read 5, iclass 22, count 0 2006.231.07:48:38.84#ibcon#about to read 6, iclass 22, count 0 2006.231.07:48:38.84#ibcon#read 6, iclass 22, count 0 2006.231.07:48:38.84#ibcon#end of sib2, iclass 22, count 0 2006.231.07:48:38.84#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:48:38.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:48:38.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:48:38.84#ibcon#*before write, iclass 22, count 0 2006.231.07:48:38.84#ibcon#enter sib2, iclass 22, count 0 2006.231.07:48:38.84#ibcon#flushed, iclass 22, count 0 2006.231.07:48:38.84#ibcon#about to write, iclass 22, count 0 2006.231.07:48:38.84#ibcon#wrote, iclass 22, count 0 2006.231.07:48:38.84#ibcon#about to read 3, iclass 22, count 0 2006.231.07:48:38.88#ibcon#read 3, iclass 22, count 0 2006.231.07:48:38.88#ibcon#about to read 4, iclass 22, count 0 2006.231.07:48:38.88#ibcon#read 4, iclass 22, count 0 2006.231.07:48:38.88#ibcon#about to read 5, iclass 22, count 0 2006.231.07:48:38.88#ibcon#read 5, iclass 22, count 0 2006.231.07:48:38.88#ibcon#about to read 6, iclass 22, count 0 2006.231.07:48:38.88#ibcon#read 6, iclass 22, count 0 2006.231.07:48:38.88#ibcon#end of sib2, iclass 22, count 0 2006.231.07:48:38.88#ibcon#*after write, iclass 22, count 0 2006.231.07:48:38.88#ibcon#*before return 0, iclass 22, count 0 2006.231.07:48:38.88#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:48:38.88#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:48:38.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:48:38.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:48:38.88$vc4f8/va=4,7 2006.231.07:48:38.88#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.07:48:38.88#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.07:48:38.88#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:38.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:48:38.94#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:48:38.94#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:48:38.94#ibcon#enter wrdev, iclass 24, count 2 2006.231.07:48:38.94#ibcon#first serial, iclass 24, count 2 2006.231.07:48:38.94#ibcon#enter sib2, iclass 24, count 2 2006.231.07:48:38.94#ibcon#flushed, iclass 24, count 2 2006.231.07:48:38.94#ibcon#about to write, iclass 24, count 2 2006.231.07:48:38.94#ibcon#wrote, iclass 24, count 2 2006.231.07:48:38.94#ibcon#about to read 3, iclass 24, count 2 2006.231.07:48:38.96#ibcon#read 3, iclass 24, count 2 2006.231.07:48:38.96#ibcon#about to read 4, iclass 24, count 2 2006.231.07:48:38.96#ibcon#read 4, iclass 24, count 2 2006.231.07:48:38.96#ibcon#about to read 5, iclass 24, count 2 2006.231.07:48:38.96#ibcon#read 5, iclass 24, count 2 2006.231.07:48:38.96#ibcon#about to read 6, iclass 24, count 2 2006.231.07:48:38.96#ibcon#read 6, iclass 24, count 2 2006.231.07:48:38.96#ibcon#end of sib2, iclass 24, count 2 2006.231.07:48:38.96#ibcon#*mode == 0, iclass 24, count 2 2006.231.07:48:38.96#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.07:48:38.96#ibcon#[25=AT04-07\r\n] 2006.231.07:48:38.96#ibcon#*before write, iclass 24, count 2 2006.231.07:48:38.96#ibcon#enter sib2, iclass 24, count 2 2006.231.07:48:38.96#ibcon#flushed, iclass 24, count 2 2006.231.07:48:38.96#ibcon#about to write, iclass 24, count 2 2006.231.07:48:38.96#ibcon#wrote, iclass 24, count 2 2006.231.07:48:38.96#ibcon#about to read 3, iclass 24, count 2 2006.231.07:48:38.99#ibcon#read 3, iclass 24, count 2 2006.231.07:48:38.99#ibcon#about to read 4, iclass 24, count 2 2006.231.07:48:38.99#ibcon#read 4, iclass 24, count 2 2006.231.07:48:38.99#ibcon#about to read 5, iclass 24, count 2 2006.231.07:48:38.99#ibcon#read 5, iclass 24, count 2 2006.231.07:48:38.99#ibcon#about to read 6, iclass 24, count 2 2006.231.07:48:38.99#ibcon#read 6, iclass 24, count 2 2006.231.07:48:38.99#ibcon#end of sib2, iclass 24, count 2 2006.231.07:48:38.99#ibcon#*after write, iclass 24, count 2 2006.231.07:48:38.99#ibcon#*before return 0, iclass 24, count 2 2006.231.07:48:38.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:48:38.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:48:38.99#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.07:48:38.99#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:38.99#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:48:39.11#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:48:39.11#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:48:39.11#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:48:39.11#ibcon#first serial, iclass 24, count 0 2006.231.07:48:39.11#ibcon#enter sib2, iclass 24, count 0 2006.231.07:48:39.11#ibcon#flushed, iclass 24, count 0 2006.231.07:48:39.11#ibcon#about to write, iclass 24, count 0 2006.231.07:48:39.11#ibcon#wrote, iclass 24, count 0 2006.231.07:48:39.11#ibcon#about to read 3, iclass 24, count 0 2006.231.07:48:39.13#ibcon#read 3, iclass 24, count 0 2006.231.07:48:39.13#ibcon#about to read 4, iclass 24, count 0 2006.231.07:48:39.13#ibcon#read 4, iclass 24, count 0 2006.231.07:48:39.13#ibcon#about to read 5, iclass 24, count 0 2006.231.07:48:39.13#ibcon#read 5, iclass 24, count 0 2006.231.07:48:39.13#ibcon#about to read 6, iclass 24, count 0 2006.231.07:48:39.13#ibcon#read 6, iclass 24, count 0 2006.231.07:48:39.13#ibcon#end of sib2, iclass 24, count 0 2006.231.07:48:39.13#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:48:39.13#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:48:39.13#ibcon#[25=USB\r\n] 2006.231.07:48:39.13#ibcon#*before write, iclass 24, count 0 2006.231.07:48:39.13#ibcon#enter sib2, iclass 24, count 0 2006.231.07:48:39.13#ibcon#flushed, iclass 24, count 0 2006.231.07:48:39.13#ibcon#about to write, iclass 24, count 0 2006.231.07:48:39.13#ibcon#wrote, iclass 24, count 0 2006.231.07:48:39.13#ibcon#about to read 3, iclass 24, count 0 2006.231.07:48:39.16#ibcon#read 3, iclass 24, count 0 2006.231.07:48:39.16#ibcon#about to read 4, iclass 24, count 0 2006.231.07:48:39.16#ibcon#read 4, iclass 24, count 0 2006.231.07:48:39.16#ibcon#about to read 5, iclass 24, count 0 2006.231.07:48:39.16#ibcon#read 5, iclass 24, count 0 2006.231.07:48:39.16#ibcon#about to read 6, iclass 24, count 0 2006.231.07:48:39.16#ibcon#read 6, iclass 24, count 0 2006.231.07:48:39.16#ibcon#end of sib2, iclass 24, count 0 2006.231.07:48:39.16#ibcon#*after write, iclass 24, count 0 2006.231.07:48:39.16#ibcon#*before return 0, iclass 24, count 0 2006.231.07:48:39.16#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:48:39.16#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:48:39.16#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:48:39.16#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:48:39.16$vc4f8/valo=5,652.99 2006.231.07:48:39.16#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:48:39.16#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:48:39.16#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:39.16#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:48:39.16#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:48:39.16#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:48:39.16#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:48:39.16#ibcon#first serial, iclass 26, count 0 2006.231.07:48:39.16#ibcon#enter sib2, iclass 26, count 0 2006.231.07:48:39.16#ibcon#flushed, iclass 26, count 0 2006.231.07:48:39.16#ibcon#about to write, iclass 26, count 0 2006.231.07:48:39.16#ibcon#wrote, iclass 26, count 0 2006.231.07:48:39.16#ibcon#about to read 3, iclass 26, count 0 2006.231.07:48:39.19#ibcon#read 3, iclass 26, count 0 2006.231.07:48:39.19#ibcon#about to read 4, iclass 26, count 0 2006.231.07:48:39.19#ibcon#read 4, iclass 26, count 0 2006.231.07:48:39.19#ibcon#about to read 5, iclass 26, count 0 2006.231.07:48:39.19#ibcon#read 5, iclass 26, count 0 2006.231.07:48:39.19#ibcon#about to read 6, iclass 26, count 0 2006.231.07:48:39.19#ibcon#read 6, iclass 26, count 0 2006.231.07:48:39.19#ibcon#end of sib2, iclass 26, count 0 2006.231.07:48:39.19#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:48:39.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:48:39.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:48:39.19#ibcon#*before write, iclass 26, count 0 2006.231.07:48:39.19#ibcon#enter sib2, iclass 26, count 0 2006.231.07:48:39.19#ibcon#flushed, iclass 26, count 0 2006.231.07:48:39.19#ibcon#about to write, iclass 26, count 0 2006.231.07:48:39.19#ibcon#wrote, iclass 26, count 0 2006.231.07:48:39.19#ibcon#about to read 3, iclass 26, count 0 2006.231.07:48:39.23#ibcon#read 3, iclass 26, count 0 2006.231.07:48:39.23#ibcon#about to read 4, iclass 26, count 0 2006.231.07:48:39.23#ibcon#read 4, iclass 26, count 0 2006.231.07:48:39.23#ibcon#about to read 5, iclass 26, count 0 2006.231.07:48:39.23#ibcon#read 5, iclass 26, count 0 2006.231.07:48:39.23#ibcon#about to read 6, iclass 26, count 0 2006.231.07:48:39.23#ibcon#read 6, iclass 26, count 0 2006.231.07:48:39.23#ibcon#end of sib2, iclass 26, count 0 2006.231.07:48:39.23#ibcon#*after write, iclass 26, count 0 2006.231.07:48:39.23#ibcon#*before return 0, iclass 26, count 0 2006.231.07:48:39.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:48:39.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:48:39.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:48:39.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:48:39.23$vc4f8/va=5,7 2006.231.07:48:39.23#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.07:48:39.23#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.07:48:39.23#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:39.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:48:39.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:48:39.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:48:39.28#ibcon#enter wrdev, iclass 28, count 2 2006.231.07:48:39.28#ibcon#first serial, iclass 28, count 2 2006.231.07:48:39.28#ibcon#enter sib2, iclass 28, count 2 2006.231.07:48:39.28#ibcon#flushed, iclass 28, count 2 2006.231.07:48:39.28#ibcon#about to write, iclass 28, count 2 2006.231.07:48:39.28#ibcon#wrote, iclass 28, count 2 2006.231.07:48:39.28#ibcon#about to read 3, iclass 28, count 2 2006.231.07:48:39.30#ibcon#read 3, iclass 28, count 2 2006.231.07:48:39.30#ibcon#about to read 4, iclass 28, count 2 2006.231.07:48:39.30#ibcon#read 4, iclass 28, count 2 2006.231.07:48:39.30#ibcon#about to read 5, iclass 28, count 2 2006.231.07:48:39.30#ibcon#read 5, iclass 28, count 2 2006.231.07:48:39.30#ibcon#about to read 6, iclass 28, count 2 2006.231.07:48:39.30#ibcon#read 6, iclass 28, count 2 2006.231.07:48:39.30#ibcon#end of sib2, iclass 28, count 2 2006.231.07:48:39.30#ibcon#*mode == 0, iclass 28, count 2 2006.231.07:48:39.30#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.07:48:39.30#ibcon#[25=AT05-07\r\n] 2006.231.07:48:39.30#ibcon#*before write, iclass 28, count 2 2006.231.07:48:39.30#ibcon#enter sib2, iclass 28, count 2 2006.231.07:48:39.30#ibcon#flushed, iclass 28, count 2 2006.231.07:48:39.30#ibcon#about to write, iclass 28, count 2 2006.231.07:48:39.30#ibcon#wrote, iclass 28, count 2 2006.231.07:48:39.30#ibcon#about to read 3, iclass 28, count 2 2006.231.07:48:39.33#ibcon#read 3, iclass 28, count 2 2006.231.07:48:39.33#ibcon#about to read 4, iclass 28, count 2 2006.231.07:48:39.33#ibcon#read 4, iclass 28, count 2 2006.231.07:48:39.33#ibcon#about to read 5, iclass 28, count 2 2006.231.07:48:39.33#ibcon#read 5, iclass 28, count 2 2006.231.07:48:39.33#ibcon#about to read 6, iclass 28, count 2 2006.231.07:48:39.33#ibcon#read 6, iclass 28, count 2 2006.231.07:48:39.33#ibcon#end of sib2, iclass 28, count 2 2006.231.07:48:39.33#ibcon#*after write, iclass 28, count 2 2006.231.07:48:39.33#ibcon#*before return 0, iclass 28, count 2 2006.231.07:48:39.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:48:39.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:48:39.33#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.07:48:39.33#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:39.33#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:48:39.45#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:48:39.45#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:48:39.45#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:48:39.45#ibcon#first serial, iclass 28, count 0 2006.231.07:48:39.45#ibcon#enter sib2, iclass 28, count 0 2006.231.07:48:39.45#ibcon#flushed, iclass 28, count 0 2006.231.07:48:39.45#ibcon#about to write, iclass 28, count 0 2006.231.07:48:39.45#ibcon#wrote, iclass 28, count 0 2006.231.07:48:39.45#ibcon#about to read 3, iclass 28, count 0 2006.231.07:48:39.47#ibcon#read 3, iclass 28, count 0 2006.231.07:48:39.47#ibcon#about to read 4, iclass 28, count 0 2006.231.07:48:39.47#ibcon#read 4, iclass 28, count 0 2006.231.07:48:39.47#ibcon#about to read 5, iclass 28, count 0 2006.231.07:48:39.47#ibcon#read 5, iclass 28, count 0 2006.231.07:48:39.47#ibcon#about to read 6, iclass 28, count 0 2006.231.07:48:39.47#ibcon#read 6, iclass 28, count 0 2006.231.07:48:39.47#ibcon#end of sib2, iclass 28, count 0 2006.231.07:48:39.47#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:48:39.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:48:39.47#ibcon#[25=USB\r\n] 2006.231.07:48:39.47#ibcon#*before write, iclass 28, count 0 2006.231.07:48:39.47#ibcon#enter sib2, iclass 28, count 0 2006.231.07:48:39.47#ibcon#flushed, iclass 28, count 0 2006.231.07:48:39.47#ibcon#about to write, iclass 28, count 0 2006.231.07:48:39.47#ibcon#wrote, iclass 28, count 0 2006.231.07:48:39.47#ibcon#about to read 3, iclass 28, count 0 2006.231.07:48:39.50#ibcon#read 3, iclass 28, count 0 2006.231.07:48:39.50#ibcon#about to read 4, iclass 28, count 0 2006.231.07:48:39.50#ibcon#read 4, iclass 28, count 0 2006.231.07:48:39.50#ibcon#about to read 5, iclass 28, count 0 2006.231.07:48:39.50#ibcon#read 5, iclass 28, count 0 2006.231.07:48:39.50#ibcon#about to read 6, iclass 28, count 0 2006.231.07:48:39.50#ibcon#read 6, iclass 28, count 0 2006.231.07:48:39.50#ibcon#end of sib2, iclass 28, count 0 2006.231.07:48:39.50#ibcon#*after write, iclass 28, count 0 2006.231.07:48:39.50#ibcon#*before return 0, iclass 28, count 0 2006.231.07:48:39.50#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:48:39.50#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:48:39.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:48:39.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:48:39.50$vc4f8/valo=6,772.99 2006.231.07:48:39.50#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.07:48:39.50#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.07:48:39.50#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:39.50#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:48:39.50#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:48:39.50#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:48:39.50#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:48:39.50#ibcon#first serial, iclass 30, count 0 2006.231.07:48:39.50#ibcon#enter sib2, iclass 30, count 0 2006.231.07:48:39.50#ibcon#flushed, iclass 30, count 0 2006.231.07:48:39.50#ibcon#about to write, iclass 30, count 0 2006.231.07:48:39.50#ibcon#wrote, iclass 30, count 0 2006.231.07:48:39.50#ibcon#about to read 3, iclass 30, count 0 2006.231.07:48:39.53#ibcon#read 3, iclass 30, count 0 2006.231.07:48:39.53#ibcon#about to read 4, iclass 30, count 0 2006.231.07:48:39.53#ibcon#read 4, iclass 30, count 0 2006.231.07:48:39.53#ibcon#about to read 5, iclass 30, count 0 2006.231.07:48:39.53#ibcon#read 5, iclass 30, count 0 2006.231.07:48:39.53#ibcon#about to read 6, iclass 30, count 0 2006.231.07:48:39.53#ibcon#read 6, iclass 30, count 0 2006.231.07:48:39.53#ibcon#end of sib2, iclass 30, count 0 2006.231.07:48:39.53#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:48:39.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:48:39.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:48:39.53#ibcon#*before write, iclass 30, count 0 2006.231.07:48:39.53#ibcon#enter sib2, iclass 30, count 0 2006.231.07:48:39.53#ibcon#flushed, iclass 30, count 0 2006.231.07:48:39.53#ibcon#about to write, iclass 30, count 0 2006.231.07:48:39.53#ibcon#wrote, iclass 30, count 0 2006.231.07:48:39.53#ibcon#about to read 3, iclass 30, count 0 2006.231.07:48:39.57#ibcon#read 3, iclass 30, count 0 2006.231.07:48:39.57#ibcon#about to read 4, iclass 30, count 0 2006.231.07:48:39.57#ibcon#read 4, iclass 30, count 0 2006.231.07:48:39.57#ibcon#about to read 5, iclass 30, count 0 2006.231.07:48:39.57#ibcon#read 5, iclass 30, count 0 2006.231.07:48:39.57#ibcon#about to read 6, iclass 30, count 0 2006.231.07:48:39.57#ibcon#read 6, iclass 30, count 0 2006.231.07:48:39.57#ibcon#end of sib2, iclass 30, count 0 2006.231.07:48:39.57#ibcon#*after write, iclass 30, count 0 2006.231.07:48:39.57#ibcon#*before return 0, iclass 30, count 0 2006.231.07:48:39.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:48:39.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:48:39.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:48:39.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:48:39.57$vc4f8/va=6,6 2006.231.07:48:39.57#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.07:48:39.57#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.07:48:39.57#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:39.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:48:39.62#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:48:39.62#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:48:39.62#ibcon#enter wrdev, iclass 32, count 2 2006.231.07:48:39.62#ibcon#first serial, iclass 32, count 2 2006.231.07:48:39.62#ibcon#enter sib2, iclass 32, count 2 2006.231.07:48:39.62#ibcon#flushed, iclass 32, count 2 2006.231.07:48:39.62#ibcon#about to write, iclass 32, count 2 2006.231.07:48:39.62#ibcon#wrote, iclass 32, count 2 2006.231.07:48:39.62#ibcon#about to read 3, iclass 32, count 2 2006.231.07:48:39.64#ibcon#read 3, iclass 32, count 2 2006.231.07:48:39.64#ibcon#about to read 4, iclass 32, count 2 2006.231.07:48:39.64#ibcon#read 4, iclass 32, count 2 2006.231.07:48:39.64#ibcon#about to read 5, iclass 32, count 2 2006.231.07:48:39.64#ibcon#read 5, iclass 32, count 2 2006.231.07:48:39.64#ibcon#about to read 6, iclass 32, count 2 2006.231.07:48:39.64#ibcon#read 6, iclass 32, count 2 2006.231.07:48:39.64#ibcon#end of sib2, iclass 32, count 2 2006.231.07:48:39.64#ibcon#*mode == 0, iclass 32, count 2 2006.231.07:48:39.64#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.07:48:39.64#ibcon#[25=AT06-06\r\n] 2006.231.07:48:39.64#ibcon#*before write, iclass 32, count 2 2006.231.07:48:39.64#ibcon#enter sib2, iclass 32, count 2 2006.231.07:48:39.64#ibcon#flushed, iclass 32, count 2 2006.231.07:48:39.64#ibcon#about to write, iclass 32, count 2 2006.231.07:48:39.64#ibcon#wrote, iclass 32, count 2 2006.231.07:48:39.64#ibcon#about to read 3, iclass 32, count 2 2006.231.07:48:39.67#ibcon#read 3, iclass 32, count 2 2006.231.07:48:39.67#ibcon#about to read 4, iclass 32, count 2 2006.231.07:48:39.67#ibcon#read 4, iclass 32, count 2 2006.231.07:48:39.67#ibcon#about to read 5, iclass 32, count 2 2006.231.07:48:39.67#ibcon#read 5, iclass 32, count 2 2006.231.07:48:39.67#ibcon#about to read 6, iclass 32, count 2 2006.231.07:48:39.67#ibcon#read 6, iclass 32, count 2 2006.231.07:48:39.67#ibcon#end of sib2, iclass 32, count 2 2006.231.07:48:39.67#ibcon#*after write, iclass 32, count 2 2006.231.07:48:39.67#ibcon#*before return 0, iclass 32, count 2 2006.231.07:48:39.67#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:48:39.67#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:48:39.67#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.07:48:39.67#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:39.67#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:48:39.79#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:48:39.79#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:48:39.79#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:48:39.79#ibcon#first serial, iclass 32, count 0 2006.231.07:48:39.79#ibcon#enter sib2, iclass 32, count 0 2006.231.07:48:39.79#ibcon#flushed, iclass 32, count 0 2006.231.07:48:39.79#ibcon#about to write, iclass 32, count 0 2006.231.07:48:39.79#ibcon#wrote, iclass 32, count 0 2006.231.07:48:39.79#ibcon#about to read 3, iclass 32, count 0 2006.231.07:48:39.81#ibcon#read 3, iclass 32, count 0 2006.231.07:48:39.81#ibcon#about to read 4, iclass 32, count 0 2006.231.07:48:39.81#ibcon#read 4, iclass 32, count 0 2006.231.07:48:39.81#ibcon#about to read 5, iclass 32, count 0 2006.231.07:48:39.81#ibcon#read 5, iclass 32, count 0 2006.231.07:48:39.81#ibcon#about to read 6, iclass 32, count 0 2006.231.07:48:39.81#ibcon#read 6, iclass 32, count 0 2006.231.07:48:39.81#ibcon#end of sib2, iclass 32, count 0 2006.231.07:48:39.81#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:48:39.81#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:48:39.81#ibcon#[25=USB\r\n] 2006.231.07:48:39.81#ibcon#*before write, iclass 32, count 0 2006.231.07:48:39.81#ibcon#enter sib2, iclass 32, count 0 2006.231.07:48:39.81#ibcon#flushed, iclass 32, count 0 2006.231.07:48:39.81#ibcon#about to write, iclass 32, count 0 2006.231.07:48:39.81#ibcon#wrote, iclass 32, count 0 2006.231.07:48:39.81#ibcon#about to read 3, iclass 32, count 0 2006.231.07:48:39.84#ibcon#read 3, iclass 32, count 0 2006.231.07:48:39.84#ibcon#about to read 4, iclass 32, count 0 2006.231.07:48:39.84#ibcon#read 4, iclass 32, count 0 2006.231.07:48:39.84#ibcon#about to read 5, iclass 32, count 0 2006.231.07:48:39.84#ibcon#read 5, iclass 32, count 0 2006.231.07:48:39.84#ibcon#about to read 6, iclass 32, count 0 2006.231.07:48:39.84#ibcon#read 6, iclass 32, count 0 2006.231.07:48:39.84#ibcon#end of sib2, iclass 32, count 0 2006.231.07:48:39.84#ibcon#*after write, iclass 32, count 0 2006.231.07:48:39.84#ibcon#*before return 0, iclass 32, count 0 2006.231.07:48:39.84#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:48:39.84#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:48:39.84#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:48:39.84#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:48:39.84$vc4f8/valo=7,832.99 2006.231.07:48:39.84#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.07:48:39.84#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.07:48:39.84#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:39.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:48:39.84#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:48:39.84#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:48:39.84#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:48:39.84#ibcon#first serial, iclass 34, count 0 2006.231.07:48:39.84#ibcon#enter sib2, iclass 34, count 0 2006.231.07:48:39.84#ibcon#flushed, iclass 34, count 0 2006.231.07:48:39.84#ibcon#about to write, iclass 34, count 0 2006.231.07:48:39.84#ibcon#wrote, iclass 34, count 0 2006.231.07:48:39.84#ibcon#about to read 3, iclass 34, count 0 2006.231.07:48:39.86#ibcon#read 3, iclass 34, count 0 2006.231.07:48:39.86#ibcon#about to read 4, iclass 34, count 0 2006.231.07:48:39.86#ibcon#read 4, iclass 34, count 0 2006.231.07:48:39.86#ibcon#about to read 5, iclass 34, count 0 2006.231.07:48:39.86#ibcon#read 5, iclass 34, count 0 2006.231.07:48:39.86#ibcon#about to read 6, iclass 34, count 0 2006.231.07:48:39.86#ibcon#read 6, iclass 34, count 0 2006.231.07:48:39.86#ibcon#end of sib2, iclass 34, count 0 2006.231.07:48:39.86#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:48:39.86#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:48:39.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:48:39.86#ibcon#*before write, iclass 34, count 0 2006.231.07:48:39.86#ibcon#enter sib2, iclass 34, count 0 2006.231.07:48:39.86#ibcon#flushed, iclass 34, count 0 2006.231.07:48:39.86#ibcon#about to write, iclass 34, count 0 2006.231.07:48:39.86#ibcon#wrote, iclass 34, count 0 2006.231.07:48:39.86#ibcon#about to read 3, iclass 34, count 0 2006.231.07:48:39.90#ibcon#read 3, iclass 34, count 0 2006.231.07:48:39.90#ibcon#about to read 4, iclass 34, count 0 2006.231.07:48:39.90#ibcon#read 4, iclass 34, count 0 2006.231.07:48:39.90#ibcon#about to read 5, iclass 34, count 0 2006.231.07:48:39.90#ibcon#read 5, iclass 34, count 0 2006.231.07:48:39.90#ibcon#about to read 6, iclass 34, count 0 2006.231.07:48:39.90#ibcon#read 6, iclass 34, count 0 2006.231.07:48:39.90#ibcon#end of sib2, iclass 34, count 0 2006.231.07:48:39.90#ibcon#*after write, iclass 34, count 0 2006.231.07:48:39.90#ibcon#*before return 0, iclass 34, count 0 2006.231.07:48:39.90#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:48:39.90#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:48:39.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:48:39.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:48:39.90$vc4f8/va=7,6 2006.231.07:48:39.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.07:48:39.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.07:48:39.90#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:39.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:48:39.96#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:48:39.96#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:48:39.96#ibcon#enter wrdev, iclass 36, count 2 2006.231.07:48:39.96#ibcon#first serial, iclass 36, count 2 2006.231.07:48:39.96#ibcon#enter sib2, iclass 36, count 2 2006.231.07:48:39.96#ibcon#flushed, iclass 36, count 2 2006.231.07:48:39.96#ibcon#about to write, iclass 36, count 2 2006.231.07:48:39.96#ibcon#wrote, iclass 36, count 2 2006.231.07:48:39.96#ibcon#about to read 3, iclass 36, count 2 2006.231.07:48:39.98#ibcon#read 3, iclass 36, count 2 2006.231.07:48:39.98#ibcon#about to read 4, iclass 36, count 2 2006.231.07:48:39.98#ibcon#read 4, iclass 36, count 2 2006.231.07:48:39.98#ibcon#about to read 5, iclass 36, count 2 2006.231.07:48:39.98#ibcon#read 5, iclass 36, count 2 2006.231.07:48:39.98#ibcon#about to read 6, iclass 36, count 2 2006.231.07:48:39.98#ibcon#read 6, iclass 36, count 2 2006.231.07:48:39.98#ibcon#end of sib2, iclass 36, count 2 2006.231.07:48:39.98#ibcon#*mode == 0, iclass 36, count 2 2006.231.07:48:39.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.07:48:39.98#ibcon#[25=AT07-06\r\n] 2006.231.07:48:39.98#ibcon#*before write, iclass 36, count 2 2006.231.07:48:39.98#ibcon#enter sib2, iclass 36, count 2 2006.231.07:48:39.98#ibcon#flushed, iclass 36, count 2 2006.231.07:48:39.98#ibcon#about to write, iclass 36, count 2 2006.231.07:48:39.98#ibcon#wrote, iclass 36, count 2 2006.231.07:48:39.98#ibcon#about to read 3, iclass 36, count 2 2006.231.07:48:40.01#ibcon#read 3, iclass 36, count 2 2006.231.07:48:40.01#ibcon#about to read 4, iclass 36, count 2 2006.231.07:48:40.01#ibcon#read 4, iclass 36, count 2 2006.231.07:48:40.01#ibcon#about to read 5, iclass 36, count 2 2006.231.07:48:40.01#ibcon#read 5, iclass 36, count 2 2006.231.07:48:40.01#ibcon#about to read 6, iclass 36, count 2 2006.231.07:48:40.01#ibcon#read 6, iclass 36, count 2 2006.231.07:48:40.01#ibcon#end of sib2, iclass 36, count 2 2006.231.07:48:40.01#ibcon#*after write, iclass 36, count 2 2006.231.07:48:40.01#ibcon#*before return 0, iclass 36, count 2 2006.231.07:48:40.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:48:40.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:48:40.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.07:48:40.01#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:40.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:48:40.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:48:40.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:48:40.13#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:48:40.13#ibcon#first serial, iclass 36, count 0 2006.231.07:48:40.13#ibcon#enter sib2, iclass 36, count 0 2006.231.07:48:40.13#ibcon#flushed, iclass 36, count 0 2006.231.07:48:40.13#ibcon#about to write, iclass 36, count 0 2006.231.07:48:40.13#ibcon#wrote, iclass 36, count 0 2006.231.07:48:40.13#ibcon#about to read 3, iclass 36, count 0 2006.231.07:48:40.15#ibcon#read 3, iclass 36, count 0 2006.231.07:48:40.15#ibcon#about to read 4, iclass 36, count 0 2006.231.07:48:40.15#ibcon#read 4, iclass 36, count 0 2006.231.07:48:40.15#ibcon#about to read 5, iclass 36, count 0 2006.231.07:48:40.15#ibcon#read 5, iclass 36, count 0 2006.231.07:48:40.15#ibcon#about to read 6, iclass 36, count 0 2006.231.07:48:40.15#ibcon#read 6, iclass 36, count 0 2006.231.07:48:40.15#ibcon#end of sib2, iclass 36, count 0 2006.231.07:48:40.15#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:48:40.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:48:40.15#ibcon#[25=USB\r\n] 2006.231.07:48:40.15#ibcon#*before write, iclass 36, count 0 2006.231.07:48:40.15#ibcon#enter sib2, iclass 36, count 0 2006.231.07:48:40.15#ibcon#flushed, iclass 36, count 0 2006.231.07:48:40.15#ibcon#about to write, iclass 36, count 0 2006.231.07:48:40.15#ibcon#wrote, iclass 36, count 0 2006.231.07:48:40.15#ibcon#about to read 3, iclass 36, count 0 2006.231.07:48:40.18#ibcon#read 3, iclass 36, count 0 2006.231.07:48:40.18#ibcon#about to read 4, iclass 36, count 0 2006.231.07:48:40.18#ibcon#read 4, iclass 36, count 0 2006.231.07:48:40.18#ibcon#about to read 5, iclass 36, count 0 2006.231.07:48:40.18#ibcon#read 5, iclass 36, count 0 2006.231.07:48:40.18#ibcon#about to read 6, iclass 36, count 0 2006.231.07:48:40.18#ibcon#read 6, iclass 36, count 0 2006.231.07:48:40.18#ibcon#end of sib2, iclass 36, count 0 2006.231.07:48:40.18#ibcon#*after write, iclass 36, count 0 2006.231.07:48:40.18#ibcon#*before return 0, iclass 36, count 0 2006.231.07:48:40.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:48:40.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:48:40.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:48:40.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:48:40.18$vc4f8/valo=8,852.99 2006.231.07:48:40.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.07:48:40.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.07:48:40.18#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:40.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:48:40.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:48:40.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:48:40.18#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:48:40.18#ibcon#first serial, iclass 38, count 0 2006.231.07:48:40.18#ibcon#enter sib2, iclass 38, count 0 2006.231.07:48:40.18#ibcon#flushed, iclass 38, count 0 2006.231.07:48:40.18#ibcon#about to write, iclass 38, count 0 2006.231.07:48:40.18#ibcon#wrote, iclass 38, count 0 2006.231.07:48:40.18#ibcon#about to read 3, iclass 38, count 0 2006.231.07:48:40.20#ibcon#read 3, iclass 38, count 0 2006.231.07:48:40.20#ibcon#about to read 4, iclass 38, count 0 2006.231.07:48:40.20#ibcon#read 4, iclass 38, count 0 2006.231.07:48:40.20#ibcon#about to read 5, iclass 38, count 0 2006.231.07:48:40.20#ibcon#read 5, iclass 38, count 0 2006.231.07:48:40.20#ibcon#about to read 6, iclass 38, count 0 2006.231.07:48:40.20#ibcon#read 6, iclass 38, count 0 2006.231.07:48:40.20#ibcon#end of sib2, iclass 38, count 0 2006.231.07:48:40.20#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:48:40.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:48:40.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:48:40.20#ibcon#*before write, iclass 38, count 0 2006.231.07:48:40.20#ibcon#enter sib2, iclass 38, count 0 2006.231.07:48:40.20#ibcon#flushed, iclass 38, count 0 2006.231.07:48:40.20#ibcon#about to write, iclass 38, count 0 2006.231.07:48:40.20#ibcon#wrote, iclass 38, count 0 2006.231.07:48:40.20#ibcon#about to read 3, iclass 38, count 0 2006.231.07:48:40.24#ibcon#read 3, iclass 38, count 0 2006.231.07:48:40.24#ibcon#about to read 4, iclass 38, count 0 2006.231.07:48:40.24#ibcon#read 4, iclass 38, count 0 2006.231.07:48:40.24#ibcon#about to read 5, iclass 38, count 0 2006.231.07:48:40.24#ibcon#read 5, iclass 38, count 0 2006.231.07:48:40.24#ibcon#about to read 6, iclass 38, count 0 2006.231.07:48:40.24#ibcon#read 6, iclass 38, count 0 2006.231.07:48:40.24#ibcon#end of sib2, iclass 38, count 0 2006.231.07:48:40.24#ibcon#*after write, iclass 38, count 0 2006.231.07:48:40.24#ibcon#*before return 0, iclass 38, count 0 2006.231.07:48:40.24#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:48:40.24#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:48:40.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:48:40.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:48:40.24$vc4f8/va=8,6 2006.231.07:48:40.24#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.07:48:40.24#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.07:48:40.24#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:40.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:48:40.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:48:40.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:48:40.30#ibcon#enter wrdev, iclass 40, count 2 2006.231.07:48:40.30#ibcon#first serial, iclass 40, count 2 2006.231.07:48:40.30#ibcon#enter sib2, iclass 40, count 2 2006.231.07:48:40.30#ibcon#flushed, iclass 40, count 2 2006.231.07:48:40.30#ibcon#about to write, iclass 40, count 2 2006.231.07:48:40.30#ibcon#wrote, iclass 40, count 2 2006.231.07:48:40.30#ibcon#about to read 3, iclass 40, count 2 2006.231.07:48:40.32#ibcon#read 3, iclass 40, count 2 2006.231.07:48:40.32#ibcon#about to read 4, iclass 40, count 2 2006.231.07:48:40.32#ibcon#read 4, iclass 40, count 2 2006.231.07:48:40.32#ibcon#about to read 5, iclass 40, count 2 2006.231.07:48:40.32#ibcon#read 5, iclass 40, count 2 2006.231.07:48:40.32#ibcon#about to read 6, iclass 40, count 2 2006.231.07:48:40.32#ibcon#read 6, iclass 40, count 2 2006.231.07:48:40.32#ibcon#end of sib2, iclass 40, count 2 2006.231.07:48:40.32#ibcon#*mode == 0, iclass 40, count 2 2006.231.07:48:40.32#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.07:48:40.32#ibcon#[25=AT08-06\r\n] 2006.231.07:48:40.32#ibcon#*before write, iclass 40, count 2 2006.231.07:48:40.32#ibcon#enter sib2, iclass 40, count 2 2006.231.07:48:40.32#ibcon#flushed, iclass 40, count 2 2006.231.07:48:40.32#ibcon#about to write, iclass 40, count 2 2006.231.07:48:40.32#ibcon#wrote, iclass 40, count 2 2006.231.07:48:40.32#ibcon#about to read 3, iclass 40, count 2 2006.231.07:48:40.35#ibcon#read 3, iclass 40, count 2 2006.231.07:48:40.35#ibcon#about to read 4, iclass 40, count 2 2006.231.07:48:40.35#ibcon#read 4, iclass 40, count 2 2006.231.07:48:40.35#ibcon#about to read 5, iclass 40, count 2 2006.231.07:48:40.35#ibcon#read 5, iclass 40, count 2 2006.231.07:48:40.35#ibcon#about to read 6, iclass 40, count 2 2006.231.07:48:40.35#ibcon#read 6, iclass 40, count 2 2006.231.07:48:40.35#ibcon#end of sib2, iclass 40, count 2 2006.231.07:48:40.35#ibcon#*after write, iclass 40, count 2 2006.231.07:48:40.35#ibcon#*before return 0, iclass 40, count 2 2006.231.07:48:40.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:48:40.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:48:40.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.07:48:40.35#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:40.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:48:40.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:48:40.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:48:40.47#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:48:40.47#ibcon#first serial, iclass 40, count 0 2006.231.07:48:40.47#ibcon#enter sib2, iclass 40, count 0 2006.231.07:48:40.47#ibcon#flushed, iclass 40, count 0 2006.231.07:48:40.47#ibcon#about to write, iclass 40, count 0 2006.231.07:48:40.47#ibcon#wrote, iclass 40, count 0 2006.231.07:48:40.47#ibcon#about to read 3, iclass 40, count 0 2006.231.07:48:40.49#ibcon#read 3, iclass 40, count 0 2006.231.07:48:40.49#ibcon#about to read 4, iclass 40, count 0 2006.231.07:48:40.49#ibcon#read 4, iclass 40, count 0 2006.231.07:48:40.49#ibcon#about to read 5, iclass 40, count 0 2006.231.07:48:40.49#ibcon#read 5, iclass 40, count 0 2006.231.07:48:40.49#ibcon#about to read 6, iclass 40, count 0 2006.231.07:48:40.49#ibcon#read 6, iclass 40, count 0 2006.231.07:48:40.49#ibcon#end of sib2, iclass 40, count 0 2006.231.07:48:40.49#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:48:40.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:48:40.49#ibcon#[25=USB\r\n] 2006.231.07:48:40.49#ibcon#*before write, iclass 40, count 0 2006.231.07:48:40.49#ibcon#enter sib2, iclass 40, count 0 2006.231.07:48:40.49#ibcon#flushed, iclass 40, count 0 2006.231.07:48:40.49#ibcon#about to write, iclass 40, count 0 2006.231.07:48:40.49#ibcon#wrote, iclass 40, count 0 2006.231.07:48:40.49#ibcon#about to read 3, iclass 40, count 0 2006.231.07:48:40.52#ibcon#read 3, iclass 40, count 0 2006.231.07:48:40.52#ibcon#about to read 4, iclass 40, count 0 2006.231.07:48:40.52#ibcon#read 4, iclass 40, count 0 2006.231.07:48:40.52#ibcon#about to read 5, iclass 40, count 0 2006.231.07:48:40.52#ibcon#read 5, iclass 40, count 0 2006.231.07:48:40.52#ibcon#about to read 6, iclass 40, count 0 2006.231.07:48:40.52#ibcon#read 6, iclass 40, count 0 2006.231.07:48:40.52#ibcon#end of sib2, iclass 40, count 0 2006.231.07:48:40.52#ibcon#*after write, iclass 40, count 0 2006.231.07:48:40.52#ibcon#*before return 0, iclass 40, count 0 2006.231.07:48:40.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:48:40.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:48:40.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:48:40.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:48:40.52$vc4f8/vblo=1,632.99 2006.231.07:48:40.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.07:48:40.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.07:48:40.52#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:40.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:48:40.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:48:40.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:48:40.52#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:48:40.52#ibcon#first serial, iclass 4, count 0 2006.231.07:48:40.52#ibcon#enter sib2, iclass 4, count 0 2006.231.07:48:40.52#ibcon#flushed, iclass 4, count 0 2006.231.07:48:40.52#ibcon#about to write, iclass 4, count 0 2006.231.07:48:40.52#ibcon#wrote, iclass 4, count 0 2006.231.07:48:40.52#ibcon#about to read 3, iclass 4, count 0 2006.231.07:48:40.54#ibcon#read 3, iclass 4, count 0 2006.231.07:48:40.54#ibcon#about to read 4, iclass 4, count 0 2006.231.07:48:40.54#ibcon#read 4, iclass 4, count 0 2006.231.07:48:40.54#ibcon#about to read 5, iclass 4, count 0 2006.231.07:48:40.54#ibcon#read 5, iclass 4, count 0 2006.231.07:48:40.54#ibcon#about to read 6, iclass 4, count 0 2006.231.07:48:40.54#ibcon#read 6, iclass 4, count 0 2006.231.07:48:40.54#ibcon#end of sib2, iclass 4, count 0 2006.231.07:48:40.54#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:48:40.54#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:48:40.54#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:48:40.54#ibcon#*before write, iclass 4, count 0 2006.231.07:48:40.54#ibcon#enter sib2, iclass 4, count 0 2006.231.07:48:40.54#ibcon#flushed, iclass 4, count 0 2006.231.07:48:40.54#ibcon#about to write, iclass 4, count 0 2006.231.07:48:40.54#ibcon#wrote, iclass 4, count 0 2006.231.07:48:40.54#ibcon#about to read 3, iclass 4, count 0 2006.231.07:48:40.58#ibcon#read 3, iclass 4, count 0 2006.231.07:48:40.58#ibcon#about to read 4, iclass 4, count 0 2006.231.07:48:40.58#ibcon#read 4, iclass 4, count 0 2006.231.07:48:40.58#ibcon#about to read 5, iclass 4, count 0 2006.231.07:48:40.58#ibcon#read 5, iclass 4, count 0 2006.231.07:48:40.58#ibcon#about to read 6, iclass 4, count 0 2006.231.07:48:40.58#ibcon#read 6, iclass 4, count 0 2006.231.07:48:40.58#ibcon#end of sib2, iclass 4, count 0 2006.231.07:48:40.58#ibcon#*after write, iclass 4, count 0 2006.231.07:48:40.58#ibcon#*before return 0, iclass 4, count 0 2006.231.07:48:40.58#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:48:40.58#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:48:40.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:48:40.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:48:40.58$vc4f8/vb=1,4 2006.231.07:48:40.58#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.07:48:40.58#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.07:48:40.58#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:40.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:48:40.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:48:40.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:48:40.58#ibcon#enter wrdev, iclass 6, count 2 2006.231.07:48:40.58#ibcon#first serial, iclass 6, count 2 2006.231.07:48:40.58#ibcon#enter sib2, iclass 6, count 2 2006.231.07:48:40.58#ibcon#flushed, iclass 6, count 2 2006.231.07:48:40.58#ibcon#about to write, iclass 6, count 2 2006.231.07:48:40.58#ibcon#wrote, iclass 6, count 2 2006.231.07:48:40.58#ibcon#about to read 3, iclass 6, count 2 2006.231.07:48:40.60#ibcon#read 3, iclass 6, count 2 2006.231.07:48:40.60#ibcon#about to read 4, iclass 6, count 2 2006.231.07:48:40.60#ibcon#read 4, iclass 6, count 2 2006.231.07:48:40.60#ibcon#about to read 5, iclass 6, count 2 2006.231.07:48:40.60#ibcon#read 5, iclass 6, count 2 2006.231.07:48:40.60#ibcon#about to read 6, iclass 6, count 2 2006.231.07:48:40.60#ibcon#read 6, iclass 6, count 2 2006.231.07:48:40.60#ibcon#end of sib2, iclass 6, count 2 2006.231.07:48:40.60#ibcon#*mode == 0, iclass 6, count 2 2006.231.07:48:40.60#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.07:48:40.60#ibcon#[27=AT01-04\r\n] 2006.231.07:48:40.60#ibcon#*before write, iclass 6, count 2 2006.231.07:48:40.60#ibcon#enter sib2, iclass 6, count 2 2006.231.07:48:40.60#ibcon#flushed, iclass 6, count 2 2006.231.07:48:40.60#ibcon#about to write, iclass 6, count 2 2006.231.07:48:40.60#ibcon#wrote, iclass 6, count 2 2006.231.07:48:40.60#ibcon#about to read 3, iclass 6, count 2 2006.231.07:48:40.63#ibcon#read 3, iclass 6, count 2 2006.231.07:48:40.63#ibcon#about to read 4, iclass 6, count 2 2006.231.07:48:40.63#ibcon#read 4, iclass 6, count 2 2006.231.07:48:40.63#ibcon#about to read 5, iclass 6, count 2 2006.231.07:48:40.63#ibcon#read 5, iclass 6, count 2 2006.231.07:48:40.63#ibcon#about to read 6, iclass 6, count 2 2006.231.07:48:40.63#ibcon#read 6, iclass 6, count 2 2006.231.07:48:40.63#ibcon#end of sib2, iclass 6, count 2 2006.231.07:48:40.63#ibcon#*after write, iclass 6, count 2 2006.231.07:48:40.63#ibcon#*before return 0, iclass 6, count 2 2006.231.07:48:40.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:48:40.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:48:40.63#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.07:48:40.63#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:40.63#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:48:40.75#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:48:40.75#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:48:40.75#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:48:40.75#ibcon#first serial, iclass 6, count 0 2006.231.07:48:40.75#ibcon#enter sib2, iclass 6, count 0 2006.231.07:48:40.75#ibcon#flushed, iclass 6, count 0 2006.231.07:48:40.75#ibcon#about to write, iclass 6, count 0 2006.231.07:48:40.75#ibcon#wrote, iclass 6, count 0 2006.231.07:48:40.75#ibcon#about to read 3, iclass 6, count 0 2006.231.07:48:40.77#ibcon#read 3, iclass 6, count 0 2006.231.07:48:40.77#ibcon#about to read 4, iclass 6, count 0 2006.231.07:48:40.77#ibcon#read 4, iclass 6, count 0 2006.231.07:48:40.77#ibcon#about to read 5, iclass 6, count 0 2006.231.07:48:40.77#ibcon#read 5, iclass 6, count 0 2006.231.07:48:40.77#ibcon#about to read 6, iclass 6, count 0 2006.231.07:48:40.77#ibcon#read 6, iclass 6, count 0 2006.231.07:48:40.77#ibcon#end of sib2, iclass 6, count 0 2006.231.07:48:40.77#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:48:40.77#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:48:40.77#ibcon#[27=USB\r\n] 2006.231.07:48:40.77#ibcon#*before write, iclass 6, count 0 2006.231.07:48:40.77#ibcon#enter sib2, iclass 6, count 0 2006.231.07:48:40.77#ibcon#flushed, iclass 6, count 0 2006.231.07:48:40.77#ibcon#about to write, iclass 6, count 0 2006.231.07:48:40.77#ibcon#wrote, iclass 6, count 0 2006.231.07:48:40.77#ibcon#about to read 3, iclass 6, count 0 2006.231.07:48:40.82#ibcon#read 3, iclass 6, count 0 2006.231.07:48:40.82#ibcon#about to read 4, iclass 6, count 0 2006.231.07:48:40.82#ibcon#read 4, iclass 6, count 0 2006.231.07:48:40.82#ibcon#about to read 5, iclass 6, count 0 2006.231.07:48:40.82#ibcon#read 5, iclass 6, count 0 2006.231.07:48:40.82#ibcon#about to read 6, iclass 6, count 0 2006.231.07:48:40.82#ibcon#read 6, iclass 6, count 0 2006.231.07:48:40.82#ibcon#end of sib2, iclass 6, count 0 2006.231.07:48:40.82#ibcon#*after write, iclass 6, count 0 2006.231.07:48:40.82#ibcon#*before return 0, iclass 6, count 0 2006.231.07:48:40.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:48:40.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:48:40.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:48:40.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:48:40.82$vc4f8/vblo=2,640.99 2006.231.07:48:40.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.07:48:40.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.07:48:40.82#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:40.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:48:40.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:48:40.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:48:40.82#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:48:40.82#ibcon#first serial, iclass 10, count 0 2006.231.07:48:40.82#ibcon#enter sib2, iclass 10, count 0 2006.231.07:48:40.82#ibcon#flushed, iclass 10, count 0 2006.231.07:48:40.82#ibcon#about to write, iclass 10, count 0 2006.231.07:48:40.82#ibcon#wrote, iclass 10, count 0 2006.231.07:48:40.82#ibcon#about to read 3, iclass 10, count 0 2006.231.07:48:40.84#ibcon#read 3, iclass 10, count 0 2006.231.07:48:40.84#ibcon#about to read 4, iclass 10, count 0 2006.231.07:48:40.84#ibcon#read 4, iclass 10, count 0 2006.231.07:48:40.84#ibcon#about to read 5, iclass 10, count 0 2006.231.07:48:40.84#ibcon#read 5, iclass 10, count 0 2006.231.07:48:40.84#ibcon#about to read 6, iclass 10, count 0 2006.231.07:48:40.84#ibcon#read 6, iclass 10, count 0 2006.231.07:48:40.84#ibcon#end of sib2, iclass 10, count 0 2006.231.07:48:40.84#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:48:40.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:48:40.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:48:40.84#ibcon#*before write, iclass 10, count 0 2006.231.07:48:40.84#ibcon#enter sib2, iclass 10, count 0 2006.231.07:48:40.84#ibcon#flushed, iclass 10, count 0 2006.231.07:48:40.84#ibcon#about to write, iclass 10, count 0 2006.231.07:48:40.84#ibcon#wrote, iclass 10, count 0 2006.231.07:48:40.84#ibcon#about to read 3, iclass 10, count 0 2006.231.07:48:40.88#ibcon#read 3, iclass 10, count 0 2006.231.07:48:40.88#ibcon#about to read 4, iclass 10, count 0 2006.231.07:48:40.88#ibcon#read 4, iclass 10, count 0 2006.231.07:48:40.88#ibcon#about to read 5, iclass 10, count 0 2006.231.07:48:40.88#ibcon#read 5, iclass 10, count 0 2006.231.07:48:40.88#ibcon#about to read 6, iclass 10, count 0 2006.231.07:48:40.88#ibcon#read 6, iclass 10, count 0 2006.231.07:48:40.88#ibcon#end of sib2, iclass 10, count 0 2006.231.07:48:40.88#ibcon#*after write, iclass 10, count 0 2006.231.07:48:40.88#ibcon#*before return 0, iclass 10, count 0 2006.231.07:48:40.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:48:40.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:48:40.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:48:40.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:48:40.88$vc4f8/vb=2,4 2006.231.07:48:40.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.07:48:40.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.07:48:40.88#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:40.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:48:40.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:48:40.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:48:40.94#ibcon#enter wrdev, iclass 12, count 2 2006.231.07:48:40.94#ibcon#first serial, iclass 12, count 2 2006.231.07:48:40.94#ibcon#enter sib2, iclass 12, count 2 2006.231.07:48:40.94#ibcon#flushed, iclass 12, count 2 2006.231.07:48:40.94#ibcon#about to write, iclass 12, count 2 2006.231.07:48:40.94#ibcon#wrote, iclass 12, count 2 2006.231.07:48:40.94#ibcon#about to read 3, iclass 12, count 2 2006.231.07:48:40.96#ibcon#read 3, iclass 12, count 2 2006.231.07:48:40.96#ibcon#about to read 4, iclass 12, count 2 2006.231.07:48:40.96#ibcon#read 4, iclass 12, count 2 2006.231.07:48:40.96#ibcon#about to read 5, iclass 12, count 2 2006.231.07:48:40.96#ibcon#read 5, iclass 12, count 2 2006.231.07:48:40.96#ibcon#about to read 6, iclass 12, count 2 2006.231.07:48:40.96#ibcon#read 6, iclass 12, count 2 2006.231.07:48:40.96#ibcon#end of sib2, iclass 12, count 2 2006.231.07:48:40.96#ibcon#*mode == 0, iclass 12, count 2 2006.231.07:48:40.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.07:48:40.96#ibcon#[27=AT02-04\r\n] 2006.231.07:48:40.96#ibcon#*before write, iclass 12, count 2 2006.231.07:48:40.96#ibcon#enter sib2, iclass 12, count 2 2006.231.07:48:40.96#ibcon#flushed, iclass 12, count 2 2006.231.07:48:40.96#ibcon#about to write, iclass 12, count 2 2006.231.07:48:40.96#ibcon#wrote, iclass 12, count 2 2006.231.07:48:40.96#ibcon#about to read 3, iclass 12, count 2 2006.231.07:48:40.99#ibcon#read 3, iclass 12, count 2 2006.231.07:48:40.99#ibcon#about to read 4, iclass 12, count 2 2006.231.07:48:40.99#ibcon#read 4, iclass 12, count 2 2006.231.07:48:40.99#ibcon#about to read 5, iclass 12, count 2 2006.231.07:48:40.99#ibcon#read 5, iclass 12, count 2 2006.231.07:48:40.99#ibcon#about to read 6, iclass 12, count 2 2006.231.07:48:40.99#ibcon#read 6, iclass 12, count 2 2006.231.07:48:40.99#ibcon#end of sib2, iclass 12, count 2 2006.231.07:48:40.99#ibcon#*after write, iclass 12, count 2 2006.231.07:48:40.99#ibcon#*before return 0, iclass 12, count 2 2006.231.07:48:40.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:48:40.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:48:40.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.07:48:40.99#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:40.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:48:41.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:48:41.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:48:41.11#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:48:41.11#ibcon#first serial, iclass 12, count 0 2006.231.07:48:41.11#ibcon#enter sib2, iclass 12, count 0 2006.231.07:48:41.11#ibcon#flushed, iclass 12, count 0 2006.231.07:48:41.11#ibcon#about to write, iclass 12, count 0 2006.231.07:48:41.11#ibcon#wrote, iclass 12, count 0 2006.231.07:48:41.11#ibcon#about to read 3, iclass 12, count 0 2006.231.07:48:41.13#ibcon#read 3, iclass 12, count 0 2006.231.07:48:41.13#ibcon#about to read 4, iclass 12, count 0 2006.231.07:48:41.13#ibcon#read 4, iclass 12, count 0 2006.231.07:48:41.13#ibcon#about to read 5, iclass 12, count 0 2006.231.07:48:41.13#ibcon#read 5, iclass 12, count 0 2006.231.07:48:41.13#ibcon#about to read 6, iclass 12, count 0 2006.231.07:48:41.13#ibcon#read 6, iclass 12, count 0 2006.231.07:48:41.13#ibcon#end of sib2, iclass 12, count 0 2006.231.07:48:41.13#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:48:41.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:48:41.13#ibcon#[27=USB\r\n] 2006.231.07:48:41.13#ibcon#*before write, iclass 12, count 0 2006.231.07:48:41.13#ibcon#enter sib2, iclass 12, count 0 2006.231.07:48:41.13#ibcon#flushed, iclass 12, count 0 2006.231.07:48:41.13#ibcon#about to write, iclass 12, count 0 2006.231.07:48:41.13#ibcon#wrote, iclass 12, count 0 2006.231.07:48:41.13#ibcon#about to read 3, iclass 12, count 0 2006.231.07:48:41.16#ibcon#read 3, iclass 12, count 0 2006.231.07:48:41.16#ibcon#about to read 4, iclass 12, count 0 2006.231.07:48:41.16#ibcon#read 4, iclass 12, count 0 2006.231.07:48:41.16#ibcon#about to read 5, iclass 12, count 0 2006.231.07:48:41.16#ibcon#read 5, iclass 12, count 0 2006.231.07:48:41.16#ibcon#about to read 6, iclass 12, count 0 2006.231.07:48:41.16#ibcon#read 6, iclass 12, count 0 2006.231.07:48:41.16#ibcon#end of sib2, iclass 12, count 0 2006.231.07:48:41.16#ibcon#*after write, iclass 12, count 0 2006.231.07:48:41.16#ibcon#*before return 0, iclass 12, count 0 2006.231.07:48:41.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:48:41.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:48:41.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:48:41.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:48:41.16$vc4f8/vblo=3,656.99 2006.231.07:48:41.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.07:48:41.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.07:48:41.16#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:41.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:48:41.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:48:41.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:48:41.16#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:48:41.16#ibcon#first serial, iclass 14, count 0 2006.231.07:48:41.16#ibcon#enter sib2, iclass 14, count 0 2006.231.07:48:41.16#ibcon#flushed, iclass 14, count 0 2006.231.07:48:41.16#ibcon#about to write, iclass 14, count 0 2006.231.07:48:41.16#ibcon#wrote, iclass 14, count 0 2006.231.07:48:41.16#ibcon#about to read 3, iclass 14, count 0 2006.231.07:48:41.18#ibcon#read 3, iclass 14, count 0 2006.231.07:48:41.18#ibcon#about to read 4, iclass 14, count 0 2006.231.07:48:41.18#ibcon#read 4, iclass 14, count 0 2006.231.07:48:41.18#ibcon#about to read 5, iclass 14, count 0 2006.231.07:48:41.18#ibcon#read 5, iclass 14, count 0 2006.231.07:48:41.18#ibcon#about to read 6, iclass 14, count 0 2006.231.07:48:41.18#ibcon#read 6, iclass 14, count 0 2006.231.07:48:41.18#ibcon#end of sib2, iclass 14, count 0 2006.231.07:48:41.18#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:48:41.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:48:41.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:48:41.18#ibcon#*before write, iclass 14, count 0 2006.231.07:48:41.18#ibcon#enter sib2, iclass 14, count 0 2006.231.07:48:41.18#ibcon#flushed, iclass 14, count 0 2006.231.07:48:41.18#ibcon#about to write, iclass 14, count 0 2006.231.07:48:41.18#ibcon#wrote, iclass 14, count 0 2006.231.07:48:41.18#ibcon#about to read 3, iclass 14, count 0 2006.231.07:48:41.22#ibcon#read 3, iclass 14, count 0 2006.231.07:48:41.22#ibcon#about to read 4, iclass 14, count 0 2006.231.07:48:41.22#ibcon#read 4, iclass 14, count 0 2006.231.07:48:41.22#ibcon#about to read 5, iclass 14, count 0 2006.231.07:48:41.22#ibcon#read 5, iclass 14, count 0 2006.231.07:48:41.22#ibcon#about to read 6, iclass 14, count 0 2006.231.07:48:41.22#ibcon#read 6, iclass 14, count 0 2006.231.07:48:41.22#ibcon#end of sib2, iclass 14, count 0 2006.231.07:48:41.22#ibcon#*after write, iclass 14, count 0 2006.231.07:48:41.22#ibcon#*before return 0, iclass 14, count 0 2006.231.07:48:41.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:48:41.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:48:41.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:48:41.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:48:41.22$vc4f8/vb=3,4 2006.231.07:48:41.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.07:48:41.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.07:48:41.22#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:41.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:48:41.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:48:41.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:48:41.28#ibcon#enter wrdev, iclass 16, count 2 2006.231.07:48:41.28#ibcon#first serial, iclass 16, count 2 2006.231.07:48:41.28#ibcon#enter sib2, iclass 16, count 2 2006.231.07:48:41.28#ibcon#flushed, iclass 16, count 2 2006.231.07:48:41.28#ibcon#about to write, iclass 16, count 2 2006.231.07:48:41.28#ibcon#wrote, iclass 16, count 2 2006.231.07:48:41.28#ibcon#about to read 3, iclass 16, count 2 2006.231.07:48:41.30#ibcon#read 3, iclass 16, count 2 2006.231.07:48:41.30#ibcon#about to read 4, iclass 16, count 2 2006.231.07:48:41.30#ibcon#read 4, iclass 16, count 2 2006.231.07:48:41.30#ibcon#about to read 5, iclass 16, count 2 2006.231.07:48:41.30#ibcon#read 5, iclass 16, count 2 2006.231.07:48:41.30#ibcon#about to read 6, iclass 16, count 2 2006.231.07:48:41.30#ibcon#read 6, iclass 16, count 2 2006.231.07:48:41.30#ibcon#end of sib2, iclass 16, count 2 2006.231.07:48:41.30#ibcon#*mode == 0, iclass 16, count 2 2006.231.07:48:41.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.07:48:41.30#ibcon#[27=AT03-04\r\n] 2006.231.07:48:41.30#ibcon#*before write, iclass 16, count 2 2006.231.07:48:41.30#ibcon#enter sib2, iclass 16, count 2 2006.231.07:48:41.30#ibcon#flushed, iclass 16, count 2 2006.231.07:48:41.30#ibcon#about to write, iclass 16, count 2 2006.231.07:48:41.30#ibcon#wrote, iclass 16, count 2 2006.231.07:48:41.30#ibcon#about to read 3, iclass 16, count 2 2006.231.07:48:41.33#ibcon#read 3, iclass 16, count 2 2006.231.07:48:41.33#ibcon#about to read 4, iclass 16, count 2 2006.231.07:48:41.33#ibcon#read 4, iclass 16, count 2 2006.231.07:48:41.33#ibcon#about to read 5, iclass 16, count 2 2006.231.07:48:41.33#ibcon#read 5, iclass 16, count 2 2006.231.07:48:41.33#ibcon#about to read 6, iclass 16, count 2 2006.231.07:48:41.33#ibcon#read 6, iclass 16, count 2 2006.231.07:48:41.33#ibcon#end of sib2, iclass 16, count 2 2006.231.07:48:41.33#ibcon#*after write, iclass 16, count 2 2006.231.07:48:41.33#ibcon#*before return 0, iclass 16, count 2 2006.231.07:48:41.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:48:41.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:48:41.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.07:48:41.33#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:41.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:48:41.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:48:41.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:48:41.45#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:48:41.45#ibcon#first serial, iclass 16, count 0 2006.231.07:48:41.45#ibcon#enter sib2, iclass 16, count 0 2006.231.07:48:41.45#ibcon#flushed, iclass 16, count 0 2006.231.07:48:41.45#ibcon#about to write, iclass 16, count 0 2006.231.07:48:41.45#ibcon#wrote, iclass 16, count 0 2006.231.07:48:41.45#ibcon#about to read 3, iclass 16, count 0 2006.231.07:48:41.47#ibcon#read 3, iclass 16, count 0 2006.231.07:48:41.47#ibcon#about to read 4, iclass 16, count 0 2006.231.07:48:41.47#ibcon#read 4, iclass 16, count 0 2006.231.07:48:41.47#ibcon#about to read 5, iclass 16, count 0 2006.231.07:48:41.47#ibcon#read 5, iclass 16, count 0 2006.231.07:48:41.47#ibcon#about to read 6, iclass 16, count 0 2006.231.07:48:41.47#ibcon#read 6, iclass 16, count 0 2006.231.07:48:41.47#ibcon#end of sib2, iclass 16, count 0 2006.231.07:48:41.47#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:48:41.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:48:41.47#ibcon#[27=USB\r\n] 2006.231.07:48:41.47#ibcon#*before write, iclass 16, count 0 2006.231.07:48:41.47#ibcon#enter sib2, iclass 16, count 0 2006.231.07:48:41.47#ibcon#flushed, iclass 16, count 0 2006.231.07:48:41.47#ibcon#about to write, iclass 16, count 0 2006.231.07:48:41.47#ibcon#wrote, iclass 16, count 0 2006.231.07:48:41.47#ibcon#about to read 3, iclass 16, count 0 2006.231.07:48:41.50#ibcon#read 3, iclass 16, count 0 2006.231.07:48:41.50#ibcon#about to read 4, iclass 16, count 0 2006.231.07:48:41.50#ibcon#read 4, iclass 16, count 0 2006.231.07:48:41.50#ibcon#about to read 5, iclass 16, count 0 2006.231.07:48:41.50#ibcon#read 5, iclass 16, count 0 2006.231.07:48:41.50#ibcon#about to read 6, iclass 16, count 0 2006.231.07:48:41.50#ibcon#read 6, iclass 16, count 0 2006.231.07:48:41.50#ibcon#end of sib2, iclass 16, count 0 2006.231.07:48:41.50#ibcon#*after write, iclass 16, count 0 2006.231.07:48:41.50#ibcon#*before return 0, iclass 16, count 0 2006.231.07:48:41.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:48:41.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:48:41.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:48:41.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:48:41.50$vc4f8/vblo=4,712.99 2006.231.07:48:41.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.07:48:41.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.07:48:41.50#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:41.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:48:41.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:48:41.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:48:41.50#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:48:41.50#ibcon#first serial, iclass 18, count 0 2006.231.07:48:41.50#ibcon#enter sib2, iclass 18, count 0 2006.231.07:48:41.50#ibcon#flushed, iclass 18, count 0 2006.231.07:48:41.50#ibcon#about to write, iclass 18, count 0 2006.231.07:48:41.50#ibcon#wrote, iclass 18, count 0 2006.231.07:48:41.50#ibcon#about to read 3, iclass 18, count 0 2006.231.07:48:41.52#ibcon#read 3, iclass 18, count 0 2006.231.07:48:41.52#ibcon#about to read 4, iclass 18, count 0 2006.231.07:48:41.52#ibcon#read 4, iclass 18, count 0 2006.231.07:48:41.52#ibcon#about to read 5, iclass 18, count 0 2006.231.07:48:41.52#ibcon#read 5, iclass 18, count 0 2006.231.07:48:41.52#ibcon#about to read 6, iclass 18, count 0 2006.231.07:48:41.52#ibcon#read 6, iclass 18, count 0 2006.231.07:48:41.52#ibcon#end of sib2, iclass 18, count 0 2006.231.07:48:41.52#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:48:41.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:48:41.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:48:41.52#ibcon#*before write, iclass 18, count 0 2006.231.07:48:41.52#ibcon#enter sib2, iclass 18, count 0 2006.231.07:48:41.52#ibcon#flushed, iclass 18, count 0 2006.231.07:48:41.52#ibcon#about to write, iclass 18, count 0 2006.231.07:48:41.52#ibcon#wrote, iclass 18, count 0 2006.231.07:48:41.52#ibcon#about to read 3, iclass 18, count 0 2006.231.07:48:41.56#ibcon#read 3, iclass 18, count 0 2006.231.07:48:41.56#ibcon#about to read 4, iclass 18, count 0 2006.231.07:48:41.56#ibcon#read 4, iclass 18, count 0 2006.231.07:48:41.56#ibcon#about to read 5, iclass 18, count 0 2006.231.07:48:41.56#ibcon#read 5, iclass 18, count 0 2006.231.07:48:41.56#ibcon#about to read 6, iclass 18, count 0 2006.231.07:48:41.56#ibcon#read 6, iclass 18, count 0 2006.231.07:48:41.56#ibcon#end of sib2, iclass 18, count 0 2006.231.07:48:41.56#ibcon#*after write, iclass 18, count 0 2006.231.07:48:41.56#ibcon#*before return 0, iclass 18, count 0 2006.231.07:48:41.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:48:41.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:48:41.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:48:41.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:48:41.56$vc4f8/vb=4,4 2006.231.07:48:41.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.07:48:41.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.07:48:41.56#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:41.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:48:41.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:48:41.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:48:41.62#ibcon#enter wrdev, iclass 20, count 2 2006.231.07:48:41.62#ibcon#first serial, iclass 20, count 2 2006.231.07:48:41.62#ibcon#enter sib2, iclass 20, count 2 2006.231.07:48:41.62#ibcon#flushed, iclass 20, count 2 2006.231.07:48:41.62#ibcon#about to write, iclass 20, count 2 2006.231.07:48:41.62#ibcon#wrote, iclass 20, count 2 2006.231.07:48:41.62#ibcon#about to read 3, iclass 20, count 2 2006.231.07:48:41.64#ibcon#read 3, iclass 20, count 2 2006.231.07:48:41.64#ibcon#about to read 4, iclass 20, count 2 2006.231.07:48:41.64#ibcon#read 4, iclass 20, count 2 2006.231.07:48:41.64#ibcon#about to read 5, iclass 20, count 2 2006.231.07:48:41.64#ibcon#read 5, iclass 20, count 2 2006.231.07:48:41.64#ibcon#about to read 6, iclass 20, count 2 2006.231.07:48:41.64#ibcon#read 6, iclass 20, count 2 2006.231.07:48:41.64#ibcon#end of sib2, iclass 20, count 2 2006.231.07:48:41.64#ibcon#*mode == 0, iclass 20, count 2 2006.231.07:48:41.64#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.07:48:41.64#ibcon#[27=AT04-04\r\n] 2006.231.07:48:41.64#ibcon#*before write, iclass 20, count 2 2006.231.07:48:41.64#ibcon#enter sib2, iclass 20, count 2 2006.231.07:48:41.64#ibcon#flushed, iclass 20, count 2 2006.231.07:48:41.64#ibcon#about to write, iclass 20, count 2 2006.231.07:48:41.64#ibcon#wrote, iclass 20, count 2 2006.231.07:48:41.64#ibcon#about to read 3, iclass 20, count 2 2006.231.07:48:41.67#ibcon#read 3, iclass 20, count 2 2006.231.07:48:41.67#ibcon#about to read 4, iclass 20, count 2 2006.231.07:48:41.67#ibcon#read 4, iclass 20, count 2 2006.231.07:48:41.67#ibcon#about to read 5, iclass 20, count 2 2006.231.07:48:41.67#ibcon#read 5, iclass 20, count 2 2006.231.07:48:41.67#ibcon#about to read 6, iclass 20, count 2 2006.231.07:48:41.67#ibcon#read 6, iclass 20, count 2 2006.231.07:48:41.67#ibcon#end of sib2, iclass 20, count 2 2006.231.07:48:41.67#ibcon#*after write, iclass 20, count 2 2006.231.07:48:41.67#ibcon#*before return 0, iclass 20, count 2 2006.231.07:48:41.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:48:41.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:48:41.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.07:48:41.67#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:41.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:48:41.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:48:41.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:48:41.79#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:48:41.79#ibcon#first serial, iclass 20, count 0 2006.231.07:48:41.79#ibcon#enter sib2, iclass 20, count 0 2006.231.07:48:41.79#ibcon#flushed, iclass 20, count 0 2006.231.07:48:41.79#ibcon#about to write, iclass 20, count 0 2006.231.07:48:41.79#ibcon#wrote, iclass 20, count 0 2006.231.07:48:41.79#ibcon#about to read 3, iclass 20, count 0 2006.231.07:48:41.81#ibcon#read 3, iclass 20, count 0 2006.231.07:48:41.81#ibcon#about to read 4, iclass 20, count 0 2006.231.07:48:41.81#ibcon#read 4, iclass 20, count 0 2006.231.07:48:41.81#ibcon#about to read 5, iclass 20, count 0 2006.231.07:48:41.81#ibcon#read 5, iclass 20, count 0 2006.231.07:48:41.81#ibcon#about to read 6, iclass 20, count 0 2006.231.07:48:41.81#ibcon#read 6, iclass 20, count 0 2006.231.07:48:41.81#ibcon#end of sib2, iclass 20, count 0 2006.231.07:48:41.81#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:48:41.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:48:41.81#ibcon#[27=USB\r\n] 2006.231.07:48:41.81#ibcon#*before write, iclass 20, count 0 2006.231.07:48:41.81#ibcon#enter sib2, iclass 20, count 0 2006.231.07:48:41.81#ibcon#flushed, iclass 20, count 0 2006.231.07:48:41.81#ibcon#about to write, iclass 20, count 0 2006.231.07:48:41.81#ibcon#wrote, iclass 20, count 0 2006.231.07:48:41.81#ibcon#about to read 3, iclass 20, count 0 2006.231.07:48:41.84#ibcon#read 3, iclass 20, count 0 2006.231.07:48:41.84#ibcon#about to read 4, iclass 20, count 0 2006.231.07:48:41.84#ibcon#read 4, iclass 20, count 0 2006.231.07:48:41.84#ibcon#about to read 5, iclass 20, count 0 2006.231.07:48:41.84#ibcon#read 5, iclass 20, count 0 2006.231.07:48:41.84#ibcon#about to read 6, iclass 20, count 0 2006.231.07:48:41.84#ibcon#read 6, iclass 20, count 0 2006.231.07:48:41.84#ibcon#end of sib2, iclass 20, count 0 2006.231.07:48:41.84#ibcon#*after write, iclass 20, count 0 2006.231.07:48:41.84#ibcon#*before return 0, iclass 20, count 0 2006.231.07:48:41.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:48:41.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:48:41.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:48:41.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:48:41.84$vc4f8/vblo=5,744.99 2006.231.07:48:41.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.07:48:41.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.07:48:41.84#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:41.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:48:41.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:48:41.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:48:41.84#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:48:41.84#ibcon#first serial, iclass 22, count 0 2006.231.07:48:41.84#ibcon#enter sib2, iclass 22, count 0 2006.231.07:48:41.84#ibcon#flushed, iclass 22, count 0 2006.231.07:48:41.84#ibcon#about to write, iclass 22, count 0 2006.231.07:48:41.84#ibcon#wrote, iclass 22, count 0 2006.231.07:48:41.84#ibcon#about to read 3, iclass 22, count 0 2006.231.07:48:41.86#ibcon#read 3, iclass 22, count 0 2006.231.07:48:41.86#ibcon#about to read 4, iclass 22, count 0 2006.231.07:48:41.86#ibcon#read 4, iclass 22, count 0 2006.231.07:48:41.86#ibcon#about to read 5, iclass 22, count 0 2006.231.07:48:41.86#ibcon#read 5, iclass 22, count 0 2006.231.07:48:41.86#ibcon#about to read 6, iclass 22, count 0 2006.231.07:48:41.86#ibcon#read 6, iclass 22, count 0 2006.231.07:48:41.86#ibcon#end of sib2, iclass 22, count 0 2006.231.07:48:41.86#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:48:41.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:48:41.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:48:41.86#ibcon#*before write, iclass 22, count 0 2006.231.07:48:41.86#ibcon#enter sib2, iclass 22, count 0 2006.231.07:48:41.86#ibcon#flushed, iclass 22, count 0 2006.231.07:48:41.86#ibcon#about to write, iclass 22, count 0 2006.231.07:48:41.86#ibcon#wrote, iclass 22, count 0 2006.231.07:48:41.86#ibcon#about to read 3, iclass 22, count 0 2006.231.07:48:41.90#ibcon#read 3, iclass 22, count 0 2006.231.07:48:41.90#ibcon#about to read 4, iclass 22, count 0 2006.231.07:48:41.90#ibcon#read 4, iclass 22, count 0 2006.231.07:48:41.90#ibcon#about to read 5, iclass 22, count 0 2006.231.07:48:41.90#ibcon#read 5, iclass 22, count 0 2006.231.07:48:41.90#ibcon#about to read 6, iclass 22, count 0 2006.231.07:48:41.90#ibcon#read 6, iclass 22, count 0 2006.231.07:48:41.90#ibcon#end of sib2, iclass 22, count 0 2006.231.07:48:41.90#ibcon#*after write, iclass 22, count 0 2006.231.07:48:41.90#ibcon#*before return 0, iclass 22, count 0 2006.231.07:48:41.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:48:41.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:48:41.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:48:41.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:48:41.90$vc4f8/vb=5,3 2006.231.07:48:41.90#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.07:48:41.90#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.07:48:41.90#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:41.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:48:41.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:48:41.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:48:41.96#ibcon#enter wrdev, iclass 24, count 2 2006.231.07:48:41.96#ibcon#first serial, iclass 24, count 2 2006.231.07:48:41.96#ibcon#enter sib2, iclass 24, count 2 2006.231.07:48:41.96#ibcon#flushed, iclass 24, count 2 2006.231.07:48:41.96#ibcon#about to write, iclass 24, count 2 2006.231.07:48:41.96#ibcon#wrote, iclass 24, count 2 2006.231.07:48:41.96#ibcon#about to read 3, iclass 24, count 2 2006.231.07:48:41.98#ibcon#read 3, iclass 24, count 2 2006.231.07:48:41.98#ibcon#about to read 4, iclass 24, count 2 2006.231.07:48:41.98#ibcon#read 4, iclass 24, count 2 2006.231.07:48:41.98#ibcon#about to read 5, iclass 24, count 2 2006.231.07:48:41.98#ibcon#read 5, iclass 24, count 2 2006.231.07:48:41.98#ibcon#about to read 6, iclass 24, count 2 2006.231.07:48:41.98#ibcon#read 6, iclass 24, count 2 2006.231.07:48:41.98#ibcon#end of sib2, iclass 24, count 2 2006.231.07:48:41.98#ibcon#*mode == 0, iclass 24, count 2 2006.231.07:48:41.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.07:48:41.98#ibcon#[27=AT05-03\r\n] 2006.231.07:48:41.98#ibcon#*before write, iclass 24, count 2 2006.231.07:48:41.98#ibcon#enter sib2, iclass 24, count 2 2006.231.07:48:41.98#ibcon#flushed, iclass 24, count 2 2006.231.07:48:41.98#ibcon#about to write, iclass 24, count 2 2006.231.07:48:41.98#ibcon#wrote, iclass 24, count 2 2006.231.07:48:41.98#ibcon#about to read 3, iclass 24, count 2 2006.231.07:48:42.01#ibcon#read 3, iclass 24, count 2 2006.231.07:48:42.01#ibcon#about to read 4, iclass 24, count 2 2006.231.07:48:42.01#ibcon#read 4, iclass 24, count 2 2006.231.07:48:42.01#ibcon#about to read 5, iclass 24, count 2 2006.231.07:48:42.01#ibcon#read 5, iclass 24, count 2 2006.231.07:48:42.01#ibcon#about to read 6, iclass 24, count 2 2006.231.07:48:42.01#ibcon#read 6, iclass 24, count 2 2006.231.07:48:42.01#ibcon#end of sib2, iclass 24, count 2 2006.231.07:48:42.01#ibcon#*after write, iclass 24, count 2 2006.231.07:48:42.01#ibcon#*before return 0, iclass 24, count 2 2006.231.07:48:42.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:48:42.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:48:42.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.07:48:42.01#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:42.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:48:42.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:48:42.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:48:42.13#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:48:42.13#ibcon#first serial, iclass 24, count 0 2006.231.07:48:42.13#ibcon#enter sib2, iclass 24, count 0 2006.231.07:48:42.13#ibcon#flushed, iclass 24, count 0 2006.231.07:48:42.13#ibcon#about to write, iclass 24, count 0 2006.231.07:48:42.13#ibcon#wrote, iclass 24, count 0 2006.231.07:48:42.13#ibcon#about to read 3, iclass 24, count 0 2006.231.07:48:42.15#ibcon#read 3, iclass 24, count 0 2006.231.07:48:42.15#ibcon#about to read 4, iclass 24, count 0 2006.231.07:48:42.15#ibcon#read 4, iclass 24, count 0 2006.231.07:48:42.15#ibcon#about to read 5, iclass 24, count 0 2006.231.07:48:42.15#ibcon#read 5, iclass 24, count 0 2006.231.07:48:42.15#ibcon#about to read 6, iclass 24, count 0 2006.231.07:48:42.15#ibcon#read 6, iclass 24, count 0 2006.231.07:48:42.15#ibcon#end of sib2, iclass 24, count 0 2006.231.07:48:42.15#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:48:42.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:48:42.15#ibcon#[27=USB\r\n] 2006.231.07:48:42.15#ibcon#*before write, iclass 24, count 0 2006.231.07:48:42.15#ibcon#enter sib2, iclass 24, count 0 2006.231.07:48:42.15#ibcon#flushed, iclass 24, count 0 2006.231.07:48:42.15#ibcon#about to write, iclass 24, count 0 2006.231.07:48:42.15#ibcon#wrote, iclass 24, count 0 2006.231.07:48:42.15#ibcon#about to read 3, iclass 24, count 0 2006.231.07:48:42.18#ibcon#read 3, iclass 24, count 0 2006.231.07:48:42.18#ibcon#about to read 4, iclass 24, count 0 2006.231.07:48:42.18#ibcon#read 4, iclass 24, count 0 2006.231.07:48:42.18#ibcon#about to read 5, iclass 24, count 0 2006.231.07:48:42.18#ibcon#read 5, iclass 24, count 0 2006.231.07:48:42.18#ibcon#about to read 6, iclass 24, count 0 2006.231.07:48:42.18#ibcon#read 6, iclass 24, count 0 2006.231.07:48:42.18#ibcon#end of sib2, iclass 24, count 0 2006.231.07:48:42.18#ibcon#*after write, iclass 24, count 0 2006.231.07:48:42.18#ibcon#*before return 0, iclass 24, count 0 2006.231.07:48:42.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:48:42.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:48:42.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:48:42.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:48:42.18$vc4f8/vblo=6,752.99 2006.231.07:48:42.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:48:42.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:48:42.18#ibcon#ireg 17 cls_cnt 0 2006.231.07:48:42.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:48:42.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:48:42.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:48:42.18#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:48:42.18#ibcon#first serial, iclass 26, count 0 2006.231.07:48:42.18#ibcon#enter sib2, iclass 26, count 0 2006.231.07:48:42.18#ibcon#flushed, iclass 26, count 0 2006.231.07:48:42.18#ibcon#about to write, iclass 26, count 0 2006.231.07:48:42.18#ibcon#wrote, iclass 26, count 0 2006.231.07:48:42.18#ibcon#about to read 3, iclass 26, count 0 2006.231.07:48:42.20#ibcon#read 3, iclass 26, count 0 2006.231.07:48:42.20#ibcon#about to read 4, iclass 26, count 0 2006.231.07:48:42.20#ibcon#read 4, iclass 26, count 0 2006.231.07:48:42.20#ibcon#about to read 5, iclass 26, count 0 2006.231.07:48:42.20#ibcon#read 5, iclass 26, count 0 2006.231.07:48:42.20#ibcon#about to read 6, iclass 26, count 0 2006.231.07:48:42.20#ibcon#read 6, iclass 26, count 0 2006.231.07:48:42.20#ibcon#end of sib2, iclass 26, count 0 2006.231.07:48:42.20#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:48:42.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:48:42.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:48:42.20#ibcon#*before write, iclass 26, count 0 2006.231.07:48:42.20#ibcon#enter sib2, iclass 26, count 0 2006.231.07:48:42.20#ibcon#flushed, iclass 26, count 0 2006.231.07:48:42.20#ibcon#about to write, iclass 26, count 0 2006.231.07:48:42.20#ibcon#wrote, iclass 26, count 0 2006.231.07:48:42.20#ibcon#about to read 3, iclass 26, count 0 2006.231.07:48:42.24#ibcon#read 3, iclass 26, count 0 2006.231.07:48:42.24#ibcon#about to read 4, iclass 26, count 0 2006.231.07:48:42.24#ibcon#read 4, iclass 26, count 0 2006.231.07:48:42.24#ibcon#about to read 5, iclass 26, count 0 2006.231.07:48:42.24#ibcon#read 5, iclass 26, count 0 2006.231.07:48:42.24#ibcon#about to read 6, iclass 26, count 0 2006.231.07:48:42.24#ibcon#read 6, iclass 26, count 0 2006.231.07:48:42.24#ibcon#end of sib2, iclass 26, count 0 2006.231.07:48:42.24#ibcon#*after write, iclass 26, count 0 2006.231.07:48:42.24#ibcon#*before return 0, iclass 26, count 0 2006.231.07:48:42.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:48:42.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:48:42.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:48:42.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:48:42.24$vc4f8/vb=6,4 2006.231.07:48:42.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.07:48:42.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.07:48:42.24#ibcon#ireg 11 cls_cnt 2 2006.231.07:48:42.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:48:42.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:48:42.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:48:42.30#ibcon#enter wrdev, iclass 28, count 2 2006.231.07:48:42.30#ibcon#first serial, iclass 28, count 2 2006.231.07:48:42.30#ibcon#enter sib2, iclass 28, count 2 2006.231.07:48:42.30#ibcon#flushed, iclass 28, count 2 2006.231.07:48:42.30#ibcon#about to write, iclass 28, count 2 2006.231.07:48:42.30#ibcon#wrote, iclass 28, count 2 2006.231.07:48:42.30#ibcon#about to read 3, iclass 28, count 2 2006.231.07:48:42.32#ibcon#read 3, iclass 28, count 2 2006.231.07:48:42.32#ibcon#about to read 4, iclass 28, count 2 2006.231.07:48:42.32#ibcon#read 4, iclass 28, count 2 2006.231.07:48:42.32#ibcon#about to read 5, iclass 28, count 2 2006.231.07:48:42.32#ibcon#read 5, iclass 28, count 2 2006.231.07:48:42.32#ibcon#about to read 6, iclass 28, count 2 2006.231.07:48:42.32#ibcon#read 6, iclass 28, count 2 2006.231.07:48:42.32#ibcon#end of sib2, iclass 28, count 2 2006.231.07:48:42.32#ibcon#*mode == 0, iclass 28, count 2 2006.231.07:48:42.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.07:48:42.32#ibcon#[27=AT06-04\r\n] 2006.231.07:48:42.32#ibcon#*before write, iclass 28, count 2 2006.231.07:48:42.32#ibcon#enter sib2, iclass 28, count 2 2006.231.07:48:42.32#ibcon#flushed, iclass 28, count 2 2006.231.07:48:42.32#ibcon#about to write, iclass 28, count 2 2006.231.07:48:42.32#ibcon#wrote, iclass 28, count 2 2006.231.07:48:42.32#ibcon#about to read 3, iclass 28, count 2 2006.231.07:48:42.35#ibcon#read 3, iclass 28, count 2 2006.231.07:48:42.35#ibcon#about to read 4, iclass 28, count 2 2006.231.07:48:42.35#ibcon#read 4, iclass 28, count 2 2006.231.07:48:42.35#ibcon#about to read 5, iclass 28, count 2 2006.231.07:48:42.35#ibcon#read 5, iclass 28, count 2 2006.231.07:48:42.35#ibcon#about to read 6, iclass 28, count 2 2006.231.07:48:42.35#ibcon#read 6, iclass 28, count 2 2006.231.07:48:42.35#ibcon#end of sib2, iclass 28, count 2 2006.231.07:48:42.35#ibcon#*after write, iclass 28, count 2 2006.231.07:48:42.35#ibcon#*before return 0, iclass 28, count 2 2006.231.07:48:42.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:48:42.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:48:42.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.07:48:42.35#ibcon#ireg 7 cls_cnt 0 2006.231.07:48:42.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:48:42.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:48:42.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:48:42.47#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:48:42.47#ibcon#first serial, iclass 28, count 0 2006.231.07:48:42.47#ibcon#enter sib2, iclass 28, count 0 2006.231.07:48:42.47#ibcon#flushed, iclass 28, count 0 2006.231.07:48:42.47#ibcon#about to write, iclass 28, count 0 2006.231.07:48:42.47#ibcon#wrote, iclass 28, count 0 2006.231.07:48:42.47#ibcon#about to read 3, iclass 28, count 0 2006.231.07:48:42.49#ibcon#read 3, iclass 28, count 0 2006.231.07:48:42.49#ibcon#about to read 4, iclass 28, count 0 2006.231.07:48:42.49#ibcon#read 4, iclass 28, count 0 2006.231.07:48:42.49#ibcon#about to read 5, iclass 28, count 0 2006.231.07:48:42.49#ibcon#read 5, iclass 28, count 0 2006.231.07:48:42.49#ibcon#about to read 6, iclass 28, count 0 2006.231.07:48:42.49#ibcon#read 6, iclass 28, count 0 2006.231.07:48:42.49#ibcon#end of sib2, iclass 28, count 0 2006.231.07:48:42.49#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:48:42.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:48:42.49#ibcon#[27=USB\r\n] 2006.231.07:48:42.49#ibcon#*before write, iclass 28, count 0 2006.231.07:48:42.49#ibcon#enter sib2, iclass 28, count 0 2006.231.07:48:42.49#ibcon#flushed, iclass 28, count 0 2006.231.07:48:42.49#ibcon#about to write, iclass 28, count 0 2006.231.07:48:42.49#ibcon#wrote, iclass 28, count 0 2006.231.07:48:42.49#ibcon#about to read 3, iclass 28, count 0 2006.231.07:48:42.52#ibcon#read 3, iclass 28, count 0 2006.231.07:48:42.52#ibcon#about to read 4, iclass 28, count 0 2006.231.07:48:42.52#ibcon#read 4, iclass 28, count 0 2006.231.07:48:42.52#ibcon#about to read 5, iclass 28, count 0 2006.231.07:48:42.52#ibcon#read 5, iclass 28, count 0 2006.231.07:48:42.52#ibcon#about to read 6, iclass 28, count 0 2006.231.07:48:42.52#ibcon#read 6, iclass 28, count 0 2006.231.07:48:42.52#ibcon#end of sib2, iclass 28, count 0 2006.231.07:48:42.52#ibcon#*after write, iclass 28, count 0 2006.231.07:48:42.52#ibcon#*before return 0, iclass 28, count 0 2006.231.07:48:42.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:48:42.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:48:42.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:48:42.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:48:42.52$vc4f8/vabw=wide 2006.231.07:48:42.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.07:48:42.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.07:48:42.52#ibcon#ireg 8 cls_cnt 0 2006.231.07:48:42.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:48:42.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:48:42.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:48:42.52#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:48:42.52#ibcon#first serial, iclass 30, count 0 2006.231.07:48:42.52#ibcon#enter sib2, iclass 30, count 0 2006.231.07:48:42.52#ibcon#flushed, iclass 30, count 0 2006.231.07:48:42.52#ibcon#about to write, iclass 30, count 0 2006.231.07:48:42.52#ibcon#wrote, iclass 30, count 0 2006.231.07:48:42.52#ibcon#about to read 3, iclass 30, count 0 2006.231.07:48:42.54#ibcon#read 3, iclass 30, count 0 2006.231.07:48:42.54#ibcon#about to read 4, iclass 30, count 0 2006.231.07:48:42.54#ibcon#read 4, iclass 30, count 0 2006.231.07:48:42.54#ibcon#about to read 5, iclass 30, count 0 2006.231.07:48:42.54#ibcon#read 5, iclass 30, count 0 2006.231.07:48:42.54#ibcon#about to read 6, iclass 30, count 0 2006.231.07:48:42.54#ibcon#read 6, iclass 30, count 0 2006.231.07:48:42.54#ibcon#end of sib2, iclass 30, count 0 2006.231.07:48:42.54#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:48:42.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:48:42.54#ibcon#[25=BW32\r\n] 2006.231.07:48:42.54#ibcon#*before write, iclass 30, count 0 2006.231.07:48:42.54#ibcon#enter sib2, iclass 30, count 0 2006.231.07:48:42.54#ibcon#flushed, iclass 30, count 0 2006.231.07:48:42.54#ibcon#about to write, iclass 30, count 0 2006.231.07:48:42.54#ibcon#wrote, iclass 30, count 0 2006.231.07:48:42.54#ibcon#about to read 3, iclass 30, count 0 2006.231.07:48:42.57#ibcon#read 3, iclass 30, count 0 2006.231.07:48:42.57#ibcon#about to read 4, iclass 30, count 0 2006.231.07:48:42.57#ibcon#read 4, iclass 30, count 0 2006.231.07:48:42.57#ibcon#about to read 5, iclass 30, count 0 2006.231.07:48:42.57#ibcon#read 5, iclass 30, count 0 2006.231.07:48:42.57#ibcon#about to read 6, iclass 30, count 0 2006.231.07:48:42.57#ibcon#read 6, iclass 30, count 0 2006.231.07:48:42.57#ibcon#end of sib2, iclass 30, count 0 2006.231.07:48:42.57#ibcon#*after write, iclass 30, count 0 2006.231.07:48:42.57#ibcon#*before return 0, iclass 30, count 0 2006.231.07:48:42.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:48:42.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:48:42.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:48:42.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:48:42.57$vc4f8/vbbw=wide 2006.231.07:48:42.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.07:48:42.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.07:48:42.57#ibcon#ireg 8 cls_cnt 0 2006.231.07:48:42.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:48:42.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:48:42.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:48:42.64#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:48:42.64#ibcon#first serial, iclass 32, count 0 2006.231.07:48:42.64#ibcon#enter sib2, iclass 32, count 0 2006.231.07:48:42.64#ibcon#flushed, iclass 32, count 0 2006.231.07:48:42.64#ibcon#about to write, iclass 32, count 0 2006.231.07:48:42.64#ibcon#wrote, iclass 32, count 0 2006.231.07:48:42.64#ibcon#about to read 3, iclass 32, count 0 2006.231.07:48:42.66#ibcon#read 3, iclass 32, count 0 2006.231.07:48:42.66#ibcon#about to read 4, iclass 32, count 0 2006.231.07:48:42.66#ibcon#read 4, iclass 32, count 0 2006.231.07:48:42.66#ibcon#about to read 5, iclass 32, count 0 2006.231.07:48:42.66#ibcon#read 5, iclass 32, count 0 2006.231.07:48:42.66#ibcon#about to read 6, iclass 32, count 0 2006.231.07:48:42.66#ibcon#read 6, iclass 32, count 0 2006.231.07:48:42.66#ibcon#end of sib2, iclass 32, count 0 2006.231.07:48:42.66#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:48:42.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:48:42.66#ibcon#[27=BW32\r\n] 2006.231.07:48:42.66#ibcon#*before write, iclass 32, count 0 2006.231.07:48:42.66#ibcon#enter sib2, iclass 32, count 0 2006.231.07:48:42.66#ibcon#flushed, iclass 32, count 0 2006.231.07:48:42.66#ibcon#about to write, iclass 32, count 0 2006.231.07:48:42.66#ibcon#wrote, iclass 32, count 0 2006.231.07:48:42.66#ibcon#about to read 3, iclass 32, count 0 2006.231.07:48:42.69#ibcon#read 3, iclass 32, count 0 2006.231.07:48:42.69#ibcon#about to read 4, iclass 32, count 0 2006.231.07:48:42.69#ibcon#read 4, iclass 32, count 0 2006.231.07:48:42.69#ibcon#about to read 5, iclass 32, count 0 2006.231.07:48:42.69#ibcon#read 5, iclass 32, count 0 2006.231.07:48:42.69#ibcon#about to read 6, iclass 32, count 0 2006.231.07:48:42.69#ibcon#read 6, iclass 32, count 0 2006.231.07:48:42.69#ibcon#end of sib2, iclass 32, count 0 2006.231.07:48:42.69#ibcon#*after write, iclass 32, count 0 2006.231.07:48:42.69#ibcon#*before return 0, iclass 32, count 0 2006.231.07:48:42.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:48:42.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:48:42.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:48:42.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:48:42.69$4f8m12a/ifd4f 2006.231.07:48:42.69$ifd4f/lo= 2006.231.07:48:42.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:48:42.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:48:42.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:48:42.69$ifd4f/patch= 2006.231.07:48:42.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:48:42.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:48:42.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:48:42.69$4f8m12a/"form=m,16.000,1:2 2006.231.07:48:42.69$4f8m12a/"tpicd 2006.231.07:48:42.69$4f8m12a/echo=off 2006.231.07:48:42.69$4f8m12a/xlog=off 2006.231.07:48:42.69:!2006.231.07:49:10 2006.231.07:48:50.14#trakl#Source acquired 2006.231.07:48:52.14#flagr#flagr/antenna,acquired 2006.231.07:49:10.00:preob 2006.231.07:49:11.14/onsource/TRACKING 2006.231.07:49:11.14:!2006.231.07:49:20 2006.231.07:49:20.00:data_valid=on 2006.231.07:49:20.00:midob 2006.231.07:49:20.14/onsource/TRACKING 2006.231.07:49:20.14/wx/30.58,1004.4,85 2006.231.07:49:20.21/cable/+6.3709E-03 2006.231.07:49:21.30/va/01,08,usb,yes,29,31 2006.231.07:49:21.30/va/02,07,usb,yes,29,31 2006.231.07:49:21.30/va/03,08,usb,yes,22,22 2006.231.07:49:21.30/va/04,07,usb,yes,31,33 2006.231.07:49:21.30/va/05,07,usb,yes,34,36 2006.231.07:49:21.30/va/06,06,usb,yes,33,33 2006.231.07:49:21.30/va/07,06,usb,yes,34,34 2006.231.07:49:21.30/va/08,06,usb,yes,36,36 2006.231.07:49:21.53/valo/01,532.99,yes,locked 2006.231.07:49:21.53/valo/02,572.99,yes,locked 2006.231.07:49:21.53/valo/03,672.99,yes,locked 2006.231.07:49:21.53/valo/04,832.99,yes,locked 2006.231.07:49:21.53/valo/05,652.99,yes,locked 2006.231.07:49:21.53/valo/06,772.99,yes,locked 2006.231.07:49:21.53/valo/07,832.99,yes,locked 2006.231.07:49:21.53/valo/08,852.99,yes,locked 2006.231.07:49:22.62/vb/01,04,usb,yes,31,29 2006.231.07:49:22.62/vb/02,04,usb,yes,32,34 2006.231.07:49:22.62/vb/03,04,usb,yes,29,33 2006.231.07:49:22.62/vb/04,04,usb,yes,30,30 2006.231.07:49:22.62/vb/05,03,usb,yes,35,40 2006.231.07:49:22.62/vb/06,04,usb,yes,29,32 2006.231.07:49:22.62/vb/07,04,usb,yes,31,31 2006.231.07:49:22.62/vb/08,04,usb,yes,29,32 2006.231.07:49:22.86/vblo/01,632.99,yes,locked 2006.231.07:49:22.86/vblo/02,640.99,yes,locked 2006.231.07:49:22.86/vblo/03,656.99,yes,locked 2006.231.07:49:22.86/vblo/04,712.99,yes,locked 2006.231.07:49:22.86/vblo/05,744.99,yes,locked 2006.231.07:49:22.86/vblo/06,752.99,yes,locked 2006.231.07:49:22.86/vblo/07,734.99,yes,locked 2006.231.07:49:22.86/vblo/08,744.99,yes,locked 2006.231.07:49:23.01/vabw/8 2006.231.07:49:23.16/vbbw/8 2006.231.07:49:23.25/xfe/off,on,12.5 2006.231.07:49:23.62/ifatt/23,28,28,28 2006.231.07:49:24.08/fmout-gps/S +4.44E-07 2006.231.07:49:24.12:!2006.231.07:50:20 2006.231.07:50:20.00:data_valid=off 2006.231.07:50:20.00:postob 2006.231.07:50:20.10/cable/+6.3711E-03 2006.231.07:50:20.10/wx/30.58,1004.4,85 2006.231.07:50:21.08/fmout-gps/S +4.44E-07 2006.231.07:50:21.08:scan_name=231-0751,k06231,60 2006.231.07:50:21.08:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.231.07:50:21.14#flagr#flagr/antenna,new-source 2006.231.07:50:22.14:checkk5 2006.231.07:50:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:50:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:50:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:50:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:50:24.00/chk_obsdata//k5ts1/T2310749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:50:24.37/chk_obsdata//k5ts2/T2310749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:50:24.74/chk_obsdata//k5ts3/T2310749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:50:25.11/chk_obsdata//k5ts4/T2310749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:50:25.80/k5log//k5ts1_log_newline 2006.231.07:50:26.49/k5log//k5ts2_log_newline 2006.231.07:50:27.18/k5log//k5ts3_log_newline 2006.231.07:50:27.87/k5log//k5ts4_log_newline 2006.231.07:50:27.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:50:27.89:4f8m12a=1 2006.231.07:50:27.89$4f8m12a/echo=on 2006.231.07:50:27.89$4f8m12a/pcalon 2006.231.07:50:27.89$pcalon/"no phase cal control is implemented here 2006.231.07:50:27.89$4f8m12a/"tpicd=stop 2006.231.07:50:27.89$4f8m12a/vc4f8 2006.231.07:50:27.89$vc4f8/valo=1,532.99 2006.231.07:50:27.89#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.07:50:27.89#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.07:50:27.89#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:27.89#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:50:27.89#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:50:27.89#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:50:27.89#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:50:27.89#ibcon#first serial, iclass 39, count 0 2006.231.07:50:27.89#ibcon#enter sib2, iclass 39, count 0 2006.231.07:50:27.89#ibcon#flushed, iclass 39, count 0 2006.231.07:50:27.89#ibcon#about to write, iclass 39, count 0 2006.231.07:50:27.89#ibcon#wrote, iclass 39, count 0 2006.231.07:50:27.89#ibcon#about to read 3, iclass 39, count 0 2006.231.07:50:27.93#ibcon#read 3, iclass 39, count 0 2006.231.07:50:27.93#ibcon#about to read 4, iclass 39, count 0 2006.231.07:50:27.93#ibcon#read 4, iclass 39, count 0 2006.231.07:50:27.93#ibcon#about to read 5, iclass 39, count 0 2006.231.07:50:27.93#ibcon#read 5, iclass 39, count 0 2006.231.07:50:27.93#ibcon#about to read 6, iclass 39, count 0 2006.231.07:50:27.93#ibcon#read 6, iclass 39, count 0 2006.231.07:50:27.93#ibcon#end of sib2, iclass 39, count 0 2006.231.07:50:27.93#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:50:27.93#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:50:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:50:27.93#ibcon#*before write, iclass 39, count 0 2006.231.07:50:27.93#ibcon#enter sib2, iclass 39, count 0 2006.231.07:50:27.93#ibcon#flushed, iclass 39, count 0 2006.231.07:50:27.93#ibcon#about to write, iclass 39, count 0 2006.231.07:50:27.93#ibcon#wrote, iclass 39, count 0 2006.231.07:50:27.93#ibcon#about to read 3, iclass 39, count 0 2006.231.07:50:27.98#ibcon#read 3, iclass 39, count 0 2006.231.07:50:27.98#ibcon#about to read 4, iclass 39, count 0 2006.231.07:50:27.98#ibcon#read 4, iclass 39, count 0 2006.231.07:50:27.98#ibcon#about to read 5, iclass 39, count 0 2006.231.07:50:27.98#ibcon#read 5, iclass 39, count 0 2006.231.07:50:27.98#ibcon#about to read 6, iclass 39, count 0 2006.231.07:50:27.98#ibcon#read 6, iclass 39, count 0 2006.231.07:50:27.98#ibcon#end of sib2, iclass 39, count 0 2006.231.07:50:27.98#ibcon#*after write, iclass 39, count 0 2006.231.07:50:27.98#ibcon#*before return 0, iclass 39, count 0 2006.231.07:50:27.98#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:50:27.98#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:50:27.98#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:50:27.98#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:50:27.98$vc4f8/va=1,8 2006.231.07:50:27.98#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.231.07:50:27.98#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.231.07:50:27.98#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:27.98#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:50:27.98#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:50:27.98#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:50:27.98#ibcon#enter wrdev, iclass 3, count 2 2006.231.07:50:27.98#ibcon#first serial, iclass 3, count 2 2006.231.07:50:27.98#ibcon#enter sib2, iclass 3, count 2 2006.231.07:50:27.98#ibcon#flushed, iclass 3, count 2 2006.231.07:50:27.98#ibcon#about to write, iclass 3, count 2 2006.231.07:50:27.98#ibcon#wrote, iclass 3, count 2 2006.231.07:50:27.98#ibcon#about to read 3, iclass 3, count 2 2006.231.07:50:28.00#ibcon#read 3, iclass 3, count 2 2006.231.07:50:28.00#ibcon#about to read 4, iclass 3, count 2 2006.231.07:50:28.00#ibcon#read 4, iclass 3, count 2 2006.231.07:50:28.00#ibcon#about to read 5, iclass 3, count 2 2006.231.07:50:28.00#ibcon#read 5, iclass 3, count 2 2006.231.07:50:28.00#ibcon#about to read 6, iclass 3, count 2 2006.231.07:50:28.00#ibcon#read 6, iclass 3, count 2 2006.231.07:50:28.00#ibcon#end of sib2, iclass 3, count 2 2006.231.07:50:28.00#ibcon#*mode == 0, iclass 3, count 2 2006.231.07:50:28.00#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.231.07:50:28.00#ibcon#[25=AT01-08\r\n] 2006.231.07:50:28.00#ibcon#*before write, iclass 3, count 2 2006.231.07:50:28.00#ibcon#enter sib2, iclass 3, count 2 2006.231.07:50:28.00#ibcon#flushed, iclass 3, count 2 2006.231.07:50:28.00#ibcon#about to write, iclass 3, count 2 2006.231.07:50:28.00#ibcon#wrote, iclass 3, count 2 2006.231.07:50:28.00#ibcon#about to read 3, iclass 3, count 2 2006.231.07:50:28.03#ibcon#read 3, iclass 3, count 2 2006.231.07:50:28.03#ibcon#about to read 4, iclass 3, count 2 2006.231.07:50:28.03#ibcon#read 4, iclass 3, count 2 2006.231.07:50:28.03#ibcon#about to read 5, iclass 3, count 2 2006.231.07:50:28.03#ibcon#read 5, iclass 3, count 2 2006.231.07:50:28.03#ibcon#about to read 6, iclass 3, count 2 2006.231.07:50:28.03#ibcon#read 6, iclass 3, count 2 2006.231.07:50:28.03#ibcon#end of sib2, iclass 3, count 2 2006.231.07:50:28.03#ibcon#*after write, iclass 3, count 2 2006.231.07:50:28.03#ibcon#*before return 0, iclass 3, count 2 2006.231.07:50:28.03#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:50:28.03#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:50:28.03#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.231.07:50:28.03#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:28.03#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:50:28.15#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:50:28.15#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:50:28.15#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:50:28.15#ibcon#first serial, iclass 3, count 0 2006.231.07:50:28.15#ibcon#enter sib2, iclass 3, count 0 2006.231.07:50:28.15#ibcon#flushed, iclass 3, count 0 2006.231.07:50:28.15#ibcon#about to write, iclass 3, count 0 2006.231.07:50:28.15#ibcon#wrote, iclass 3, count 0 2006.231.07:50:28.15#ibcon#about to read 3, iclass 3, count 0 2006.231.07:50:28.17#ibcon#read 3, iclass 3, count 0 2006.231.07:50:28.17#ibcon#about to read 4, iclass 3, count 0 2006.231.07:50:28.17#ibcon#read 4, iclass 3, count 0 2006.231.07:50:28.17#ibcon#about to read 5, iclass 3, count 0 2006.231.07:50:28.17#ibcon#read 5, iclass 3, count 0 2006.231.07:50:28.17#ibcon#about to read 6, iclass 3, count 0 2006.231.07:50:28.17#ibcon#read 6, iclass 3, count 0 2006.231.07:50:28.17#ibcon#end of sib2, iclass 3, count 0 2006.231.07:50:28.17#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:50:28.17#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:50:28.17#ibcon#[25=USB\r\n] 2006.231.07:50:28.17#ibcon#*before write, iclass 3, count 0 2006.231.07:50:28.17#ibcon#enter sib2, iclass 3, count 0 2006.231.07:50:28.17#ibcon#flushed, iclass 3, count 0 2006.231.07:50:28.17#ibcon#about to write, iclass 3, count 0 2006.231.07:50:28.17#ibcon#wrote, iclass 3, count 0 2006.231.07:50:28.17#ibcon#about to read 3, iclass 3, count 0 2006.231.07:50:28.20#ibcon#read 3, iclass 3, count 0 2006.231.07:50:28.20#ibcon#about to read 4, iclass 3, count 0 2006.231.07:50:28.20#ibcon#read 4, iclass 3, count 0 2006.231.07:50:28.20#ibcon#about to read 5, iclass 3, count 0 2006.231.07:50:28.20#ibcon#read 5, iclass 3, count 0 2006.231.07:50:28.20#ibcon#about to read 6, iclass 3, count 0 2006.231.07:50:28.20#ibcon#read 6, iclass 3, count 0 2006.231.07:50:28.20#ibcon#end of sib2, iclass 3, count 0 2006.231.07:50:28.20#ibcon#*after write, iclass 3, count 0 2006.231.07:50:28.20#ibcon#*before return 0, iclass 3, count 0 2006.231.07:50:28.20#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:50:28.20#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:50:28.20#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:50:28.20#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:50:28.20$vc4f8/valo=2,572.99 2006.231.07:50:28.20#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.231.07:50:28.20#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.231.07:50:28.20#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:28.20#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:50:28.20#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:50:28.20#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:50:28.20#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:50:28.20#ibcon#first serial, iclass 5, count 0 2006.231.07:50:28.20#ibcon#enter sib2, iclass 5, count 0 2006.231.07:50:28.20#ibcon#flushed, iclass 5, count 0 2006.231.07:50:28.20#ibcon#about to write, iclass 5, count 0 2006.231.07:50:28.20#ibcon#wrote, iclass 5, count 0 2006.231.07:50:28.20#ibcon#about to read 3, iclass 5, count 0 2006.231.07:50:28.22#ibcon#read 3, iclass 5, count 0 2006.231.07:50:28.22#ibcon#about to read 4, iclass 5, count 0 2006.231.07:50:28.22#ibcon#read 4, iclass 5, count 0 2006.231.07:50:28.22#ibcon#about to read 5, iclass 5, count 0 2006.231.07:50:28.22#ibcon#read 5, iclass 5, count 0 2006.231.07:50:28.22#ibcon#about to read 6, iclass 5, count 0 2006.231.07:50:28.22#ibcon#read 6, iclass 5, count 0 2006.231.07:50:28.22#ibcon#end of sib2, iclass 5, count 0 2006.231.07:50:28.22#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:50:28.22#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:50:28.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:50:28.22#ibcon#*before write, iclass 5, count 0 2006.231.07:50:28.22#ibcon#enter sib2, iclass 5, count 0 2006.231.07:50:28.22#ibcon#flushed, iclass 5, count 0 2006.231.07:50:28.22#ibcon#about to write, iclass 5, count 0 2006.231.07:50:28.22#ibcon#wrote, iclass 5, count 0 2006.231.07:50:28.22#ibcon#about to read 3, iclass 5, count 0 2006.231.07:50:28.26#ibcon#read 3, iclass 5, count 0 2006.231.07:50:28.26#ibcon#about to read 4, iclass 5, count 0 2006.231.07:50:28.26#ibcon#read 4, iclass 5, count 0 2006.231.07:50:28.26#ibcon#about to read 5, iclass 5, count 0 2006.231.07:50:28.26#ibcon#read 5, iclass 5, count 0 2006.231.07:50:28.26#ibcon#about to read 6, iclass 5, count 0 2006.231.07:50:28.26#ibcon#read 6, iclass 5, count 0 2006.231.07:50:28.26#ibcon#end of sib2, iclass 5, count 0 2006.231.07:50:28.26#ibcon#*after write, iclass 5, count 0 2006.231.07:50:28.26#ibcon#*before return 0, iclass 5, count 0 2006.231.07:50:28.26#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:50:28.26#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:50:28.26#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:50:28.26#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:50:28.26$vc4f8/va=2,7 2006.231.07:50:28.26#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.231.07:50:28.26#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.231.07:50:28.26#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:28.26#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:50:28.32#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:50:28.32#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:50:28.32#ibcon#enter wrdev, iclass 7, count 2 2006.231.07:50:28.32#ibcon#first serial, iclass 7, count 2 2006.231.07:50:28.32#ibcon#enter sib2, iclass 7, count 2 2006.231.07:50:28.32#ibcon#flushed, iclass 7, count 2 2006.231.07:50:28.32#ibcon#about to write, iclass 7, count 2 2006.231.07:50:28.32#ibcon#wrote, iclass 7, count 2 2006.231.07:50:28.32#ibcon#about to read 3, iclass 7, count 2 2006.231.07:50:28.34#ibcon#read 3, iclass 7, count 2 2006.231.07:50:28.34#ibcon#about to read 4, iclass 7, count 2 2006.231.07:50:28.34#ibcon#read 4, iclass 7, count 2 2006.231.07:50:28.34#ibcon#about to read 5, iclass 7, count 2 2006.231.07:50:28.34#ibcon#read 5, iclass 7, count 2 2006.231.07:50:28.34#ibcon#about to read 6, iclass 7, count 2 2006.231.07:50:28.34#ibcon#read 6, iclass 7, count 2 2006.231.07:50:28.34#ibcon#end of sib2, iclass 7, count 2 2006.231.07:50:28.34#ibcon#*mode == 0, iclass 7, count 2 2006.231.07:50:28.34#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.231.07:50:28.34#ibcon#[25=AT02-07\r\n] 2006.231.07:50:28.34#ibcon#*before write, iclass 7, count 2 2006.231.07:50:28.34#ibcon#enter sib2, iclass 7, count 2 2006.231.07:50:28.34#ibcon#flushed, iclass 7, count 2 2006.231.07:50:28.34#ibcon#about to write, iclass 7, count 2 2006.231.07:50:28.34#ibcon#wrote, iclass 7, count 2 2006.231.07:50:28.34#ibcon#about to read 3, iclass 7, count 2 2006.231.07:50:28.37#ibcon#read 3, iclass 7, count 2 2006.231.07:50:28.37#ibcon#about to read 4, iclass 7, count 2 2006.231.07:50:28.37#ibcon#read 4, iclass 7, count 2 2006.231.07:50:28.37#ibcon#about to read 5, iclass 7, count 2 2006.231.07:50:28.37#ibcon#read 5, iclass 7, count 2 2006.231.07:50:28.37#ibcon#about to read 6, iclass 7, count 2 2006.231.07:50:28.37#ibcon#read 6, iclass 7, count 2 2006.231.07:50:28.37#ibcon#end of sib2, iclass 7, count 2 2006.231.07:50:28.37#ibcon#*after write, iclass 7, count 2 2006.231.07:50:28.37#ibcon#*before return 0, iclass 7, count 2 2006.231.07:50:28.37#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:50:28.37#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:50:28.37#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.231.07:50:28.37#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:28.37#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:50:28.49#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:50:28.49#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:50:28.49#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:50:28.49#ibcon#first serial, iclass 7, count 0 2006.231.07:50:28.49#ibcon#enter sib2, iclass 7, count 0 2006.231.07:50:28.49#ibcon#flushed, iclass 7, count 0 2006.231.07:50:28.49#ibcon#about to write, iclass 7, count 0 2006.231.07:50:28.49#ibcon#wrote, iclass 7, count 0 2006.231.07:50:28.49#ibcon#about to read 3, iclass 7, count 0 2006.231.07:50:28.52#ibcon#read 3, iclass 7, count 0 2006.231.07:50:28.52#ibcon#about to read 4, iclass 7, count 0 2006.231.07:50:28.52#ibcon#read 4, iclass 7, count 0 2006.231.07:50:28.52#ibcon#about to read 5, iclass 7, count 0 2006.231.07:50:28.52#ibcon#read 5, iclass 7, count 0 2006.231.07:50:28.52#ibcon#about to read 6, iclass 7, count 0 2006.231.07:50:28.52#ibcon#read 6, iclass 7, count 0 2006.231.07:50:28.52#ibcon#end of sib2, iclass 7, count 0 2006.231.07:50:28.52#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:50:28.52#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:50:28.52#ibcon#[25=USB\r\n] 2006.231.07:50:28.52#ibcon#*before write, iclass 7, count 0 2006.231.07:50:28.52#ibcon#enter sib2, iclass 7, count 0 2006.231.07:50:28.52#ibcon#flushed, iclass 7, count 0 2006.231.07:50:28.52#ibcon#about to write, iclass 7, count 0 2006.231.07:50:28.52#ibcon#wrote, iclass 7, count 0 2006.231.07:50:28.52#ibcon#about to read 3, iclass 7, count 0 2006.231.07:50:28.55#ibcon#read 3, iclass 7, count 0 2006.231.07:50:28.55#ibcon#about to read 4, iclass 7, count 0 2006.231.07:50:28.55#ibcon#read 4, iclass 7, count 0 2006.231.07:50:28.55#ibcon#about to read 5, iclass 7, count 0 2006.231.07:50:28.55#ibcon#read 5, iclass 7, count 0 2006.231.07:50:28.55#ibcon#about to read 6, iclass 7, count 0 2006.231.07:50:28.55#ibcon#read 6, iclass 7, count 0 2006.231.07:50:28.55#ibcon#end of sib2, iclass 7, count 0 2006.231.07:50:28.55#ibcon#*after write, iclass 7, count 0 2006.231.07:50:28.55#ibcon#*before return 0, iclass 7, count 0 2006.231.07:50:28.55#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:50:28.55#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:50:28.55#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:50:28.55#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:50:28.55$vc4f8/valo=3,672.99 2006.231.07:50:28.55#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.231.07:50:28.55#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.231.07:50:28.55#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:28.55#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:50:28.55#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:50:28.55#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:50:28.55#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:50:28.55#ibcon#first serial, iclass 11, count 0 2006.231.07:50:28.55#ibcon#enter sib2, iclass 11, count 0 2006.231.07:50:28.55#ibcon#flushed, iclass 11, count 0 2006.231.07:50:28.55#ibcon#about to write, iclass 11, count 0 2006.231.07:50:28.55#ibcon#wrote, iclass 11, count 0 2006.231.07:50:28.55#ibcon#about to read 3, iclass 11, count 0 2006.231.07:50:28.57#ibcon#read 3, iclass 11, count 0 2006.231.07:50:28.57#ibcon#about to read 4, iclass 11, count 0 2006.231.07:50:28.57#ibcon#read 4, iclass 11, count 0 2006.231.07:50:28.57#ibcon#about to read 5, iclass 11, count 0 2006.231.07:50:28.57#ibcon#read 5, iclass 11, count 0 2006.231.07:50:28.57#ibcon#about to read 6, iclass 11, count 0 2006.231.07:50:28.57#ibcon#read 6, iclass 11, count 0 2006.231.07:50:28.57#ibcon#end of sib2, iclass 11, count 0 2006.231.07:50:28.57#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:50:28.57#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:50:28.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:50:28.57#ibcon#*before write, iclass 11, count 0 2006.231.07:50:28.57#ibcon#enter sib2, iclass 11, count 0 2006.231.07:50:28.57#ibcon#flushed, iclass 11, count 0 2006.231.07:50:28.57#ibcon#about to write, iclass 11, count 0 2006.231.07:50:28.57#ibcon#wrote, iclass 11, count 0 2006.231.07:50:28.57#ibcon#about to read 3, iclass 11, count 0 2006.231.07:50:28.61#ibcon#read 3, iclass 11, count 0 2006.231.07:50:28.61#ibcon#about to read 4, iclass 11, count 0 2006.231.07:50:28.61#ibcon#read 4, iclass 11, count 0 2006.231.07:50:28.61#ibcon#about to read 5, iclass 11, count 0 2006.231.07:50:28.61#ibcon#read 5, iclass 11, count 0 2006.231.07:50:28.61#ibcon#about to read 6, iclass 11, count 0 2006.231.07:50:28.61#ibcon#read 6, iclass 11, count 0 2006.231.07:50:28.61#ibcon#end of sib2, iclass 11, count 0 2006.231.07:50:28.61#ibcon#*after write, iclass 11, count 0 2006.231.07:50:28.61#ibcon#*before return 0, iclass 11, count 0 2006.231.07:50:28.61#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:50:28.61#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:50:28.61#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:50:28.61#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:50:28.61$vc4f8/va=3,8 2006.231.07:50:28.61#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.231.07:50:28.61#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.231.07:50:28.61#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:28.61#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:50:28.67#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:50:28.67#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:50:28.67#ibcon#enter wrdev, iclass 13, count 2 2006.231.07:50:28.67#ibcon#first serial, iclass 13, count 2 2006.231.07:50:28.67#ibcon#enter sib2, iclass 13, count 2 2006.231.07:50:28.67#ibcon#flushed, iclass 13, count 2 2006.231.07:50:28.67#ibcon#about to write, iclass 13, count 2 2006.231.07:50:28.67#ibcon#wrote, iclass 13, count 2 2006.231.07:50:28.67#ibcon#about to read 3, iclass 13, count 2 2006.231.07:50:28.69#ibcon#read 3, iclass 13, count 2 2006.231.07:50:28.69#ibcon#about to read 4, iclass 13, count 2 2006.231.07:50:28.69#ibcon#read 4, iclass 13, count 2 2006.231.07:50:28.69#ibcon#about to read 5, iclass 13, count 2 2006.231.07:50:28.69#ibcon#read 5, iclass 13, count 2 2006.231.07:50:28.69#ibcon#about to read 6, iclass 13, count 2 2006.231.07:50:28.69#ibcon#read 6, iclass 13, count 2 2006.231.07:50:28.69#ibcon#end of sib2, iclass 13, count 2 2006.231.07:50:28.69#ibcon#*mode == 0, iclass 13, count 2 2006.231.07:50:28.69#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.231.07:50:28.69#ibcon#[25=AT03-08\r\n] 2006.231.07:50:28.69#ibcon#*before write, iclass 13, count 2 2006.231.07:50:28.69#ibcon#enter sib2, iclass 13, count 2 2006.231.07:50:28.69#ibcon#flushed, iclass 13, count 2 2006.231.07:50:28.69#ibcon#about to write, iclass 13, count 2 2006.231.07:50:28.69#ibcon#wrote, iclass 13, count 2 2006.231.07:50:28.69#ibcon#about to read 3, iclass 13, count 2 2006.231.07:50:28.73#ibcon#read 3, iclass 13, count 2 2006.231.07:50:28.73#ibcon#about to read 4, iclass 13, count 2 2006.231.07:50:28.73#ibcon#read 4, iclass 13, count 2 2006.231.07:50:28.73#ibcon#about to read 5, iclass 13, count 2 2006.231.07:50:28.73#ibcon#read 5, iclass 13, count 2 2006.231.07:50:28.73#ibcon#about to read 6, iclass 13, count 2 2006.231.07:50:28.73#ibcon#read 6, iclass 13, count 2 2006.231.07:50:28.73#ibcon#end of sib2, iclass 13, count 2 2006.231.07:50:28.73#ibcon#*after write, iclass 13, count 2 2006.231.07:50:28.73#ibcon#*before return 0, iclass 13, count 2 2006.231.07:50:28.73#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:50:28.73#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:50:28.73#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.231.07:50:28.73#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:28.73#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:50:28.84#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:50:28.84#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:50:28.84#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:50:28.84#ibcon#first serial, iclass 13, count 0 2006.231.07:50:28.84#ibcon#enter sib2, iclass 13, count 0 2006.231.07:50:28.84#ibcon#flushed, iclass 13, count 0 2006.231.07:50:28.84#ibcon#about to write, iclass 13, count 0 2006.231.07:50:28.84#ibcon#wrote, iclass 13, count 0 2006.231.07:50:28.84#ibcon#about to read 3, iclass 13, count 0 2006.231.07:50:28.86#ibcon#read 3, iclass 13, count 0 2006.231.07:50:28.86#ibcon#about to read 4, iclass 13, count 0 2006.231.07:50:28.86#ibcon#read 4, iclass 13, count 0 2006.231.07:50:28.86#ibcon#about to read 5, iclass 13, count 0 2006.231.07:50:28.86#ibcon#read 5, iclass 13, count 0 2006.231.07:50:28.86#ibcon#about to read 6, iclass 13, count 0 2006.231.07:50:28.86#ibcon#read 6, iclass 13, count 0 2006.231.07:50:28.86#ibcon#end of sib2, iclass 13, count 0 2006.231.07:50:28.86#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:50:28.86#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:50:28.86#ibcon#[25=USB\r\n] 2006.231.07:50:28.86#ibcon#*before write, iclass 13, count 0 2006.231.07:50:28.86#ibcon#enter sib2, iclass 13, count 0 2006.231.07:50:28.86#ibcon#flushed, iclass 13, count 0 2006.231.07:50:28.86#ibcon#about to write, iclass 13, count 0 2006.231.07:50:28.86#ibcon#wrote, iclass 13, count 0 2006.231.07:50:28.86#ibcon#about to read 3, iclass 13, count 0 2006.231.07:50:28.89#ibcon#read 3, iclass 13, count 0 2006.231.07:50:28.89#ibcon#about to read 4, iclass 13, count 0 2006.231.07:50:28.89#ibcon#read 4, iclass 13, count 0 2006.231.07:50:28.89#ibcon#about to read 5, iclass 13, count 0 2006.231.07:50:28.89#ibcon#read 5, iclass 13, count 0 2006.231.07:50:28.89#ibcon#about to read 6, iclass 13, count 0 2006.231.07:50:28.89#ibcon#read 6, iclass 13, count 0 2006.231.07:50:28.89#ibcon#end of sib2, iclass 13, count 0 2006.231.07:50:28.89#ibcon#*after write, iclass 13, count 0 2006.231.07:50:28.89#ibcon#*before return 0, iclass 13, count 0 2006.231.07:50:28.89#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:50:28.89#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:50:28.89#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:50:28.89#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:50:28.89$vc4f8/valo=4,832.99 2006.231.07:50:28.89#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.07:50:28.89#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.07:50:28.89#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:28.89#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:50:28.89#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:50:28.89#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:50:28.89#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:50:28.89#ibcon#first serial, iclass 15, count 0 2006.231.07:50:28.89#ibcon#enter sib2, iclass 15, count 0 2006.231.07:50:28.89#ibcon#flushed, iclass 15, count 0 2006.231.07:50:28.89#ibcon#about to write, iclass 15, count 0 2006.231.07:50:28.89#ibcon#wrote, iclass 15, count 0 2006.231.07:50:28.89#ibcon#about to read 3, iclass 15, count 0 2006.231.07:50:28.91#ibcon#read 3, iclass 15, count 0 2006.231.07:50:28.91#ibcon#about to read 4, iclass 15, count 0 2006.231.07:50:28.91#ibcon#read 4, iclass 15, count 0 2006.231.07:50:28.91#ibcon#about to read 5, iclass 15, count 0 2006.231.07:50:28.91#ibcon#read 5, iclass 15, count 0 2006.231.07:50:28.91#ibcon#about to read 6, iclass 15, count 0 2006.231.07:50:28.91#ibcon#read 6, iclass 15, count 0 2006.231.07:50:28.91#ibcon#end of sib2, iclass 15, count 0 2006.231.07:50:28.91#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:50:28.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:50:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:50:28.91#ibcon#*before write, iclass 15, count 0 2006.231.07:50:28.91#ibcon#enter sib2, iclass 15, count 0 2006.231.07:50:28.91#ibcon#flushed, iclass 15, count 0 2006.231.07:50:28.91#ibcon#about to write, iclass 15, count 0 2006.231.07:50:28.91#ibcon#wrote, iclass 15, count 0 2006.231.07:50:28.91#ibcon#about to read 3, iclass 15, count 0 2006.231.07:50:28.95#ibcon#read 3, iclass 15, count 0 2006.231.07:50:28.95#ibcon#about to read 4, iclass 15, count 0 2006.231.07:50:28.95#ibcon#read 4, iclass 15, count 0 2006.231.07:50:28.95#ibcon#about to read 5, iclass 15, count 0 2006.231.07:50:28.95#ibcon#read 5, iclass 15, count 0 2006.231.07:50:28.95#ibcon#about to read 6, iclass 15, count 0 2006.231.07:50:28.95#ibcon#read 6, iclass 15, count 0 2006.231.07:50:28.95#ibcon#end of sib2, iclass 15, count 0 2006.231.07:50:28.95#ibcon#*after write, iclass 15, count 0 2006.231.07:50:28.95#ibcon#*before return 0, iclass 15, count 0 2006.231.07:50:28.95#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:50:28.95#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:50:28.95#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:50:28.95#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:50:28.95$vc4f8/va=4,7 2006.231.07:50:28.95#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.07:50:28.95#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.07:50:28.95#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:28.95#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:50:29.01#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:50:29.01#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:50:29.01#ibcon#enter wrdev, iclass 17, count 2 2006.231.07:50:29.01#ibcon#first serial, iclass 17, count 2 2006.231.07:50:29.01#ibcon#enter sib2, iclass 17, count 2 2006.231.07:50:29.01#ibcon#flushed, iclass 17, count 2 2006.231.07:50:29.01#ibcon#about to write, iclass 17, count 2 2006.231.07:50:29.01#ibcon#wrote, iclass 17, count 2 2006.231.07:50:29.01#ibcon#about to read 3, iclass 17, count 2 2006.231.07:50:29.03#ibcon#read 3, iclass 17, count 2 2006.231.07:50:29.03#ibcon#about to read 4, iclass 17, count 2 2006.231.07:50:29.03#ibcon#read 4, iclass 17, count 2 2006.231.07:50:29.03#ibcon#about to read 5, iclass 17, count 2 2006.231.07:50:29.03#ibcon#read 5, iclass 17, count 2 2006.231.07:50:29.03#ibcon#about to read 6, iclass 17, count 2 2006.231.07:50:29.03#ibcon#read 6, iclass 17, count 2 2006.231.07:50:29.03#ibcon#end of sib2, iclass 17, count 2 2006.231.07:50:29.03#ibcon#*mode == 0, iclass 17, count 2 2006.231.07:50:29.03#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.07:50:29.03#ibcon#[25=AT04-07\r\n] 2006.231.07:50:29.03#ibcon#*before write, iclass 17, count 2 2006.231.07:50:29.03#ibcon#enter sib2, iclass 17, count 2 2006.231.07:50:29.03#ibcon#flushed, iclass 17, count 2 2006.231.07:50:29.03#ibcon#about to write, iclass 17, count 2 2006.231.07:50:29.03#ibcon#wrote, iclass 17, count 2 2006.231.07:50:29.03#ibcon#about to read 3, iclass 17, count 2 2006.231.07:50:29.06#ibcon#read 3, iclass 17, count 2 2006.231.07:50:29.06#ibcon#about to read 4, iclass 17, count 2 2006.231.07:50:29.06#ibcon#read 4, iclass 17, count 2 2006.231.07:50:29.06#ibcon#about to read 5, iclass 17, count 2 2006.231.07:50:29.06#ibcon#read 5, iclass 17, count 2 2006.231.07:50:29.06#ibcon#about to read 6, iclass 17, count 2 2006.231.07:50:29.06#ibcon#read 6, iclass 17, count 2 2006.231.07:50:29.06#ibcon#end of sib2, iclass 17, count 2 2006.231.07:50:29.06#ibcon#*after write, iclass 17, count 2 2006.231.07:50:29.06#ibcon#*before return 0, iclass 17, count 2 2006.231.07:50:29.06#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:50:29.06#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:50:29.06#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.07:50:29.06#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:29.06#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:50:29.18#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:50:29.18#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:50:29.18#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:50:29.18#ibcon#first serial, iclass 17, count 0 2006.231.07:50:29.18#ibcon#enter sib2, iclass 17, count 0 2006.231.07:50:29.18#ibcon#flushed, iclass 17, count 0 2006.231.07:50:29.18#ibcon#about to write, iclass 17, count 0 2006.231.07:50:29.18#ibcon#wrote, iclass 17, count 0 2006.231.07:50:29.18#ibcon#about to read 3, iclass 17, count 0 2006.231.07:50:29.20#ibcon#read 3, iclass 17, count 0 2006.231.07:50:29.20#ibcon#about to read 4, iclass 17, count 0 2006.231.07:50:29.20#ibcon#read 4, iclass 17, count 0 2006.231.07:50:29.20#ibcon#about to read 5, iclass 17, count 0 2006.231.07:50:29.20#ibcon#read 5, iclass 17, count 0 2006.231.07:50:29.20#ibcon#about to read 6, iclass 17, count 0 2006.231.07:50:29.20#ibcon#read 6, iclass 17, count 0 2006.231.07:50:29.20#ibcon#end of sib2, iclass 17, count 0 2006.231.07:50:29.20#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:50:29.20#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:50:29.20#ibcon#[25=USB\r\n] 2006.231.07:50:29.20#ibcon#*before write, iclass 17, count 0 2006.231.07:50:29.20#ibcon#enter sib2, iclass 17, count 0 2006.231.07:50:29.20#ibcon#flushed, iclass 17, count 0 2006.231.07:50:29.20#ibcon#about to write, iclass 17, count 0 2006.231.07:50:29.20#ibcon#wrote, iclass 17, count 0 2006.231.07:50:29.20#ibcon#about to read 3, iclass 17, count 0 2006.231.07:50:29.23#ibcon#read 3, iclass 17, count 0 2006.231.07:50:29.23#ibcon#about to read 4, iclass 17, count 0 2006.231.07:50:29.23#ibcon#read 4, iclass 17, count 0 2006.231.07:50:29.23#ibcon#about to read 5, iclass 17, count 0 2006.231.07:50:29.23#ibcon#read 5, iclass 17, count 0 2006.231.07:50:29.23#ibcon#about to read 6, iclass 17, count 0 2006.231.07:50:29.23#ibcon#read 6, iclass 17, count 0 2006.231.07:50:29.23#ibcon#end of sib2, iclass 17, count 0 2006.231.07:50:29.23#ibcon#*after write, iclass 17, count 0 2006.231.07:50:29.23#ibcon#*before return 0, iclass 17, count 0 2006.231.07:50:29.23#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:50:29.23#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:50:29.23#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:50:29.23#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:50:29.23$vc4f8/valo=5,652.99 2006.231.07:50:29.23#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.07:50:29.23#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.07:50:29.23#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:29.23#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:50:29.23#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:50:29.23#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:50:29.23#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:50:29.23#ibcon#first serial, iclass 19, count 0 2006.231.07:50:29.23#ibcon#enter sib2, iclass 19, count 0 2006.231.07:50:29.23#ibcon#flushed, iclass 19, count 0 2006.231.07:50:29.23#ibcon#about to write, iclass 19, count 0 2006.231.07:50:29.23#ibcon#wrote, iclass 19, count 0 2006.231.07:50:29.23#ibcon#about to read 3, iclass 19, count 0 2006.231.07:50:29.25#ibcon#read 3, iclass 19, count 0 2006.231.07:50:29.25#ibcon#about to read 4, iclass 19, count 0 2006.231.07:50:29.25#ibcon#read 4, iclass 19, count 0 2006.231.07:50:29.25#ibcon#about to read 5, iclass 19, count 0 2006.231.07:50:29.25#ibcon#read 5, iclass 19, count 0 2006.231.07:50:29.25#ibcon#about to read 6, iclass 19, count 0 2006.231.07:50:29.25#ibcon#read 6, iclass 19, count 0 2006.231.07:50:29.25#ibcon#end of sib2, iclass 19, count 0 2006.231.07:50:29.25#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:50:29.25#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:50:29.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:50:29.25#ibcon#*before write, iclass 19, count 0 2006.231.07:50:29.25#ibcon#enter sib2, iclass 19, count 0 2006.231.07:50:29.25#ibcon#flushed, iclass 19, count 0 2006.231.07:50:29.25#ibcon#about to write, iclass 19, count 0 2006.231.07:50:29.25#ibcon#wrote, iclass 19, count 0 2006.231.07:50:29.25#ibcon#about to read 3, iclass 19, count 0 2006.231.07:50:29.29#ibcon#read 3, iclass 19, count 0 2006.231.07:50:29.29#ibcon#about to read 4, iclass 19, count 0 2006.231.07:50:29.29#ibcon#read 4, iclass 19, count 0 2006.231.07:50:29.29#ibcon#about to read 5, iclass 19, count 0 2006.231.07:50:29.29#ibcon#read 5, iclass 19, count 0 2006.231.07:50:29.29#ibcon#about to read 6, iclass 19, count 0 2006.231.07:50:29.29#ibcon#read 6, iclass 19, count 0 2006.231.07:50:29.29#ibcon#end of sib2, iclass 19, count 0 2006.231.07:50:29.29#ibcon#*after write, iclass 19, count 0 2006.231.07:50:29.29#ibcon#*before return 0, iclass 19, count 0 2006.231.07:50:29.29#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:50:29.29#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:50:29.29#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:50:29.29#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:50:29.29$vc4f8/va=5,7 2006.231.07:50:29.29#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.231.07:50:29.29#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.231.07:50:29.29#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:29.29#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:50:29.35#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:50:29.35#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:50:29.35#ibcon#enter wrdev, iclass 21, count 2 2006.231.07:50:29.35#ibcon#first serial, iclass 21, count 2 2006.231.07:50:29.35#ibcon#enter sib2, iclass 21, count 2 2006.231.07:50:29.35#ibcon#flushed, iclass 21, count 2 2006.231.07:50:29.35#ibcon#about to write, iclass 21, count 2 2006.231.07:50:29.35#ibcon#wrote, iclass 21, count 2 2006.231.07:50:29.35#ibcon#about to read 3, iclass 21, count 2 2006.231.07:50:29.37#ibcon#read 3, iclass 21, count 2 2006.231.07:50:29.37#ibcon#about to read 4, iclass 21, count 2 2006.231.07:50:29.37#ibcon#read 4, iclass 21, count 2 2006.231.07:50:29.37#ibcon#about to read 5, iclass 21, count 2 2006.231.07:50:29.37#ibcon#read 5, iclass 21, count 2 2006.231.07:50:29.37#ibcon#about to read 6, iclass 21, count 2 2006.231.07:50:29.37#ibcon#read 6, iclass 21, count 2 2006.231.07:50:29.37#ibcon#end of sib2, iclass 21, count 2 2006.231.07:50:29.37#ibcon#*mode == 0, iclass 21, count 2 2006.231.07:50:29.37#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.231.07:50:29.37#ibcon#[25=AT05-07\r\n] 2006.231.07:50:29.37#ibcon#*before write, iclass 21, count 2 2006.231.07:50:29.37#ibcon#enter sib2, iclass 21, count 2 2006.231.07:50:29.37#ibcon#flushed, iclass 21, count 2 2006.231.07:50:29.37#ibcon#about to write, iclass 21, count 2 2006.231.07:50:29.37#ibcon#wrote, iclass 21, count 2 2006.231.07:50:29.37#ibcon#about to read 3, iclass 21, count 2 2006.231.07:50:29.40#ibcon#read 3, iclass 21, count 2 2006.231.07:50:29.40#ibcon#about to read 4, iclass 21, count 2 2006.231.07:50:29.40#ibcon#read 4, iclass 21, count 2 2006.231.07:50:29.40#ibcon#about to read 5, iclass 21, count 2 2006.231.07:50:29.40#ibcon#read 5, iclass 21, count 2 2006.231.07:50:29.40#ibcon#about to read 6, iclass 21, count 2 2006.231.07:50:29.40#ibcon#read 6, iclass 21, count 2 2006.231.07:50:29.40#ibcon#end of sib2, iclass 21, count 2 2006.231.07:50:29.40#ibcon#*after write, iclass 21, count 2 2006.231.07:50:29.40#ibcon#*before return 0, iclass 21, count 2 2006.231.07:50:29.40#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:50:29.40#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:50:29.40#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.231.07:50:29.40#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:29.40#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:50:29.52#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:50:29.52#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:50:29.52#ibcon#enter wrdev, iclass 21, count 0 2006.231.07:50:29.52#ibcon#first serial, iclass 21, count 0 2006.231.07:50:29.52#ibcon#enter sib2, iclass 21, count 0 2006.231.07:50:29.52#ibcon#flushed, iclass 21, count 0 2006.231.07:50:29.52#ibcon#about to write, iclass 21, count 0 2006.231.07:50:29.52#ibcon#wrote, iclass 21, count 0 2006.231.07:50:29.52#ibcon#about to read 3, iclass 21, count 0 2006.231.07:50:29.54#ibcon#read 3, iclass 21, count 0 2006.231.07:50:29.54#ibcon#about to read 4, iclass 21, count 0 2006.231.07:50:29.54#ibcon#read 4, iclass 21, count 0 2006.231.07:50:29.54#ibcon#about to read 5, iclass 21, count 0 2006.231.07:50:29.54#ibcon#read 5, iclass 21, count 0 2006.231.07:50:29.54#ibcon#about to read 6, iclass 21, count 0 2006.231.07:50:29.54#ibcon#read 6, iclass 21, count 0 2006.231.07:50:29.54#ibcon#end of sib2, iclass 21, count 0 2006.231.07:50:29.54#ibcon#*mode == 0, iclass 21, count 0 2006.231.07:50:29.54#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.07:50:29.54#ibcon#[25=USB\r\n] 2006.231.07:50:29.54#ibcon#*before write, iclass 21, count 0 2006.231.07:50:29.54#ibcon#enter sib2, iclass 21, count 0 2006.231.07:50:29.54#ibcon#flushed, iclass 21, count 0 2006.231.07:50:29.54#ibcon#about to write, iclass 21, count 0 2006.231.07:50:29.54#ibcon#wrote, iclass 21, count 0 2006.231.07:50:29.54#ibcon#about to read 3, iclass 21, count 0 2006.231.07:50:29.56#abcon#<5=/07 3.6 7.2 30.58 851004.4\r\n> 2006.231.07:50:29.57#ibcon#read 3, iclass 21, count 0 2006.231.07:50:29.57#ibcon#about to read 4, iclass 21, count 0 2006.231.07:50:29.57#ibcon#read 4, iclass 21, count 0 2006.231.07:50:29.57#ibcon#about to read 5, iclass 21, count 0 2006.231.07:50:29.57#ibcon#read 5, iclass 21, count 0 2006.231.07:50:29.57#ibcon#about to read 6, iclass 21, count 0 2006.231.07:50:29.57#ibcon#read 6, iclass 21, count 0 2006.231.07:50:29.57#ibcon#end of sib2, iclass 21, count 0 2006.231.07:50:29.57#ibcon#*after write, iclass 21, count 0 2006.231.07:50:29.57#ibcon#*before return 0, iclass 21, count 0 2006.231.07:50:29.57#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:50:29.57#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:50:29.57#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.07:50:29.57#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.07:50:29.57$vc4f8/valo=6,772.99 2006.231.07:50:29.57#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:50:29.57#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:50:29.57#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:29.57#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:50:29.57#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:50:29.57#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:50:29.57#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:50:29.57#ibcon#first serial, iclass 26, count 0 2006.231.07:50:29.57#ibcon#enter sib2, iclass 26, count 0 2006.231.07:50:29.57#ibcon#flushed, iclass 26, count 0 2006.231.07:50:29.57#ibcon#about to write, iclass 26, count 0 2006.231.07:50:29.57#ibcon#wrote, iclass 26, count 0 2006.231.07:50:29.57#ibcon#about to read 3, iclass 26, count 0 2006.231.07:50:29.58#abcon#{5=INTERFACE CLEAR} 2006.231.07:50:29.59#ibcon#read 3, iclass 26, count 0 2006.231.07:50:29.59#ibcon#about to read 4, iclass 26, count 0 2006.231.07:50:29.59#ibcon#read 4, iclass 26, count 0 2006.231.07:50:29.59#ibcon#about to read 5, iclass 26, count 0 2006.231.07:50:29.59#ibcon#read 5, iclass 26, count 0 2006.231.07:50:29.59#ibcon#about to read 6, iclass 26, count 0 2006.231.07:50:29.59#ibcon#read 6, iclass 26, count 0 2006.231.07:50:29.59#ibcon#end of sib2, iclass 26, count 0 2006.231.07:50:29.59#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:50:29.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:50:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:50:29.59#ibcon#*before write, iclass 26, count 0 2006.231.07:50:29.59#ibcon#enter sib2, iclass 26, count 0 2006.231.07:50:29.59#ibcon#flushed, iclass 26, count 0 2006.231.07:50:29.59#ibcon#about to write, iclass 26, count 0 2006.231.07:50:29.59#ibcon#wrote, iclass 26, count 0 2006.231.07:50:29.59#ibcon#about to read 3, iclass 26, count 0 2006.231.07:50:29.63#ibcon#read 3, iclass 26, count 0 2006.231.07:50:29.63#ibcon#about to read 4, iclass 26, count 0 2006.231.07:50:29.63#ibcon#read 4, iclass 26, count 0 2006.231.07:50:29.63#ibcon#about to read 5, iclass 26, count 0 2006.231.07:50:29.63#ibcon#read 5, iclass 26, count 0 2006.231.07:50:29.63#ibcon#about to read 6, iclass 26, count 0 2006.231.07:50:29.63#ibcon#read 6, iclass 26, count 0 2006.231.07:50:29.63#ibcon#end of sib2, iclass 26, count 0 2006.231.07:50:29.63#ibcon#*after write, iclass 26, count 0 2006.231.07:50:29.63#ibcon#*before return 0, iclass 26, count 0 2006.231.07:50:29.63#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:50:29.63#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:50:29.63#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:50:29.63#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:50:29.63$vc4f8/va=6,6 2006.231.07:50:29.63#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.231.07:50:29.63#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.231.07:50:29.63#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:29.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:50:29.64#abcon#[5=S1D000X0/0*\r\n] 2006.231.07:50:29.69#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:50:29.69#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:50:29.69#ibcon#enter wrdev, iclass 29, count 2 2006.231.07:50:29.69#ibcon#first serial, iclass 29, count 2 2006.231.07:50:29.69#ibcon#enter sib2, iclass 29, count 2 2006.231.07:50:29.69#ibcon#flushed, iclass 29, count 2 2006.231.07:50:29.69#ibcon#about to write, iclass 29, count 2 2006.231.07:50:29.69#ibcon#wrote, iclass 29, count 2 2006.231.07:50:29.69#ibcon#about to read 3, iclass 29, count 2 2006.231.07:50:29.71#ibcon#read 3, iclass 29, count 2 2006.231.07:50:29.71#ibcon#about to read 4, iclass 29, count 2 2006.231.07:50:29.71#ibcon#read 4, iclass 29, count 2 2006.231.07:50:29.71#ibcon#about to read 5, iclass 29, count 2 2006.231.07:50:29.71#ibcon#read 5, iclass 29, count 2 2006.231.07:50:29.71#ibcon#about to read 6, iclass 29, count 2 2006.231.07:50:29.71#ibcon#read 6, iclass 29, count 2 2006.231.07:50:29.71#ibcon#end of sib2, iclass 29, count 2 2006.231.07:50:29.71#ibcon#*mode == 0, iclass 29, count 2 2006.231.07:50:29.71#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.231.07:50:29.71#ibcon#[25=AT06-06\r\n] 2006.231.07:50:29.71#ibcon#*before write, iclass 29, count 2 2006.231.07:50:29.71#ibcon#enter sib2, iclass 29, count 2 2006.231.07:50:29.71#ibcon#flushed, iclass 29, count 2 2006.231.07:50:29.71#ibcon#about to write, iclass 29, count 2 2006.231.07:50:29.71#ibcon#wrote, iclass 29, count 2 2006.231.07:50:29.71#ibcon#about to read 3, iclass 29, count 2 2006.231.07:50:29.74#ibcon#read 3, iclass 29, count 2 2006.231.07:50:29.74#ibcon#about to read 4, iclass 29, count 2 2006.231.07:50:29.74#ibcon#read 4, iclass 29, count 2 2006.231.07:50:29.74#ibcon#about to read 5, iclass 29, count 2 2006.231.07:50:29.74#ibcon#read 5, iclass 29, count 2 2006.231.07:50:29.74#ibcon#about to read 6, iclass 29, count 2 2006.231.07:50:29.74#ibcon#read 6, iclass 29, count 2 2006.231.07:50:29.74#ibcon#end of sib2, iclass 29, count 2 2006.231.07:50:29.74#ibcon#*after write, iclass 29, count 2 2006.231.07:50:29.74#ibcon#*before return 0, iclass 29, count 2 2006.231.07:50:29.74#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:50:29.74#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.231.07:50:29.74#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.231.07:50:29.74#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:29.74#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:50:29.86#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:50:29.86#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:50:29.86#ibcon#enter wrdev, iclass 29, count 0 2006.231.07:50:29.86#ibcon#first serial, iclass 29, count 0 2006.231.07:50:29.86#ibcon#enter sib2, iclass 29, count 0 2006.231.07:50:29.86#ibcon#flushed, iclass 29, count 0 2006.231.07:50:29.86#ibcon#about to write, iclass 29, count 0 2006.231.07:50:29.86#ibcon#wrote, iclass 29, count 0 2006.231.07:50:29.86#ibcon#about to read 3, iclass 29, count 0 2006.231.07:50:29.88#ibcon#read 3, iclass 29, count 0 2006.231.07:50:29.88#ibcon#about to read 4, iclass 29, count 0 2006.231.07:50:29.88#ibcon#read 4, iclass 29, count 0 2006.231.07:50:29.88#ibcon#about to read 5, iclass 29, count 0 2006.231.07:50:29.88#ibcon#read 5, iclass 29, count 0 2006.231.07:50:29.88#ibcon#about to read 6, iclass 29, count 0 2006.231.07:50:29.88#ibcon#read 6, iclass 29, count 0 2006.231.07:50:29.88#ibcon#end of sib2, iclass 29, count 0 2006.231.07:50:29.88#ibcon#*mode == 0, iclass 29, count 0 2006.231.07:50:29.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.07:50:29.88#ibcon#[25=USB\r\n] 2006.231.07:50:29.88#ibcon#*before write, iclass 29, count 0 2006.231.07:50:29.88#ibcon#enter sib2, iclass 29, count 0 2006.231.07:50:29.88#ibcon#flushed, iclass 29, count 0 2006.231.07:50:29.88#ibcon#about to write, iclass 29, count 0 2006.231.07:50:29.88#ibcon#wrote, iclass 29, count 0 2006.231.07:50:29.88#ibcon#about to read 3, iclass 29, count 0 2006.231.07:50:29.91#ibcon#read 3, iclass 29, count 0 2006.231.07:50:29.91#ibcon#about to read 4, iclass 29, count 0 2006.231.07:50:29.91#ibcon#read 4, iclass 29, count 0 2006.231.07:50:29.91#ibcon#about to read 5, iclass 29, count 0 2006.231.07:50:29.91#ibcon#read 5, iclass 29, count 0 2006.231.07:50:29.91#ibcon#about to read 6, iclass 29, count 0 2006.231.07:50:29.91#ibcon#read 6, iclass 29, count 0 2006.231.07:50:29.91#ibcon#end of sib2, iclass 29, count 0 2006.231.07:50:29.91#ibcon#*after write, iclass 29, count 0 2006.231.07:50:29.91#ibcon#*before return 0, iclass 29, count 0 2006.231.07:50:29.91#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:50:29.91#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.231.07:50:29.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.07:50:29.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.07:50:29.91$vc4f8/valo=7,832.99 2006.231.07:50:29.91#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.231.07:50:29.91#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.231.07:50:29.91#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:29.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:50:29.91#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:50:29.91#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:50:29.91#ibcon#enter wrdev, iclass 31, count 0 2006.231.07:50:29.91#ibcon#first serial, iclass 31, count 0 2006.231.07:50:29.91#ibcon#enter sib2, iclass 31, count 0 2006.231.07:50:29.91#ibcon#flushed, iclass 31, count 0 2006.231.07:50:29.91#ibcon#about to write, iclass 31, count 0 2006.231.07:50:29.91#ibcon#wrote, iclass 31, count 0 2006.231.07:50:29.91#ibcon#about to read 3, iclass 31, count 0 2006.231.07:50:29.93#ibcon#read 3, iclass 31, count 0 2006.231.07:50:29.93#ibcon#about to read 4, iclass 31, count 0 2006.231.07:50:29.93#ibcon#read 4, iclass 31, count 0 2006.231.07:50:29.93#ibcon#about to read 5, iclass 31, count 0 2006.231.07:50:29.93#ibcon#read 5, iclass 31, count 0 2006.231.07:50:29.93#ibcon#about to read 6, iclass 31, count 0 2006.231.07:50:29.93#ibcon#read 6, iclass 31, count 0 2006.231.07:50:29.93#ibcon#end of sib2, iclass 31, count 0 2006.231.07:50:29.93#ibcon#*mode == 0, iclass 31, count 0 2006.231.07:50:29.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.07:50:29.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:50:29.93#ibcon#*before write, iclass 31, count 0 2006.231.07:50:29.93#ibcon#enter sib2, iclass 31, count 0 2006.231.07:50:29.93#ibcon#flushed, iclass 31, count 0 2006.231.07:50:29.93#ibcon#about to write, iclass 31, count 0 2006.231.07:50:29.93#ibcon#wrote, iclass 31, count 0 2006.231.07:50:29.93#ibcon#about to read 3, iclass 31, count 0 2006.231.07:50:29.97#ibcon#read 3, iclass 31, count 0 2006.231.07:50:29.97#ibcon#about to read 4, iclass 31, count 0 2006.231.07:50:29.97#ibcon#read 4, iclass 31, count 0 2006.231.07:50:29.97#ibcon#about to read 5, iclass 31, count 0 2006.231.07:50:29.97#ibcon#read 5, iclass 31, count 0 2006.231.07:50:29.97#ibcon#about to read 6, iclass 31, count 0 2006.231.07:50:29.97#ibcon#read 6, iclass 31, count 0 2006.231.07:50:29.97#ibcon#end of sib2, iclass 31, count 0 2006.231.07:50:29.97#ibcon#*after write, iclass 31, count 0 2006.231.07:50:29.97#ibcon#*before return 0, iclass 31, count 0 2006.231.07:50:29.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:50:29.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.231.07:50:29.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.07:50:29.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.07:50:29.97$vc4f8/va=7,6 2006.231.07:50:29.97#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.231.07:50:29.97#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.231.07:50:29.97#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:29.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:50:30.03#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:50:30.03#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:50:30.03#ibcon#enter wrdev, iclass 33, count 2 2006.231.07:50:30.03#ibcon#first serial, iclass 33, count 2 2006.231.07:50:30.03#ibcon#enter sib2, iclass 33, count 2 2006.231.07:50:30.03#ibcon#flushed, iclass 33, count 2 2006.231.07:50:30.03#ibcon#about to write, iclass 33, count 2 2006.231.07:50:30.03#ibcon#wrote, iclass 33, count 2 2006.231.07:50:30.03#ibcon#about to read 3, iclass 33, count 2 2006.231.07:50:30.05#ibcon#read 3, iclass 33, count 2 2006.231.07:50:30.05#ibcon#about to read 4, iclass 33, count 2 2006.231.07:50:30.05#ibcon#read 4, iclass 33, count 2 2006.231.07:50:30.05#ibcon#about to read 5, iclass 33, count 2 2006.231.07:50:30.05#ibcon#read 5, iclass 33, count 2 2006.231.07:50:30.05#ibcon#about to read 6, iclass 33, count 2 2006.231.07:50:30.05#ibcon#read 6, iclass 33, count 2 2006.231.07:50:30.05#ibcon#end of sib2, iclass 33, count 2 2006.231.07:50:30.05#ibcon#*mode == 0, iclass 33, count 2 2006.231.07:50:30.05#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.231.07:50:30.05#ibcon#[25=AT07-06\r\n] 2006.231.07:50:30.05#ibcon#*before write, iclass 33, count 2 2006.231.07:50:30.05#ibcon#enter sib2, iclass 33, count 2 2006.231.07:50:30.05#ibcon#flushed, iclass 33, count 2 2006.231.07:50:30.05#ibcon#about to write, iclass 33, count 2 2006.231.07:50:30.05#ibcon#wrote, iclass 33, count 2 2006.231.07:50:30.05#ibcon#about to read 3, iclass 33, count 2 2006.231.07:50:30.09#ibcon#read 3, iclass 33, count 2 2006.231.07:50:30.09#ibcon#about to read 4, iclass 33, count 2 2006.231.07:50:30.09#ibcon#read 4, iclass 33, count 2 2006.231.07:50:30.09#ibcon#about to read 5, iclass 33, count 2 2006.231.07:50:30.09#ibcon#read 5, iclass 33, count 2 2006.231.07:50:30.09#ibcon#about to read 6, iclass 33, count 2 2006.231.07:50:30.09#ibcon#read 6, iclass 33, count 2 2006.231.07:50:30.09#ibcon#end of sib2, iclass 33, count 2 2006.231.07:50:30.09#ibcon#*after write, iclass 33, count 2 2006.231.07:50:30.09#ibcon#*before return 0, iclass 33, count 2 2006.231.07:50:30.09#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:50:30.09#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.231.07:50:30.09#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.231.07:50:30.09#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:30.09#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:50:30.21#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:50:30.21#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:50:30.21#ibcon#enter wrdev, iclass 33, count 0 2006.231.07:50:30.21#ibcon#first serial, iclass 33, count 0 2006.231.07:50:30.21#ibcon#enter sib2, iclass 33, count 0 2006.231.07:50:30.21#ibcon#flushed, iclass 33, count 0 2006.231.07:50:30.21#ibcon#about to write, iclass 33, count 0 2006.231.07:50:30.21#ibcon#wrote, iclass 33, count 0 2006.231.07:50:30.21#ibcon#about to read 3, iclass 33, count 0 2006.231.07:50:30.23#ibcon#read 3, iclass 33, count 0 2006.231.07:50:30.23#ibcon#about to read 4, iclass 33, count 0 2006.231.07:50:30.23#ibcon#read 4, iclass 33, count 0 2006.231.07:50:30.23#ibcon#about to read 5, iclass 33, count 0 2006.231.07:50:30.23#ibcon#read 5, iclass 33, count 0 2006.231.07:50:30.23#ibcon#about to read 6, iclass 33, count 0 2006.231.07:50:30.23#ibcon#read 6, iclass 33, count 0 2006.231.07:50:30.23#ibcon#end of sib2, iclass 33, count 0 2006.231.07:50:30.23#ibcon#*mode == 0, iclass 33, count 0 2006.231.07:50:30.23#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.07:50:30.23#ibcon#[25=USB\r\n] 2006.231.07:50:30.23#ibcon#*before write, iclass 33, count 0 2006.231.07:50:30.23#ibcon#enter sib2, iclass 33, count 0 2006.231.07:50:30.23#ibcon#flushed, iclass 33, count 0 2006.231.07:50:30.23#ibcon#about to write, iclass 33, count 0 2006.231.07:50:30.23#ibcon#wrote, iclass 33, count 0 2006.231.07:50:30.23#ibcon#about to read 3, iclass 33, count 0 2006.231.07:50:30.26#ibcon#read 3, iclass 33, count 0 2006.231.07:50:30.26#ibcon#about to read 4, iclass 33, count 0 2006.231.07:50:30.26#ibcon#read 4, iclass 33, count 0 2006.231.07:50:30.26#ibcon#about to read 5, iclass 33, count 0 2006.231.07:50:30.26#ibcon#read 5, iclass 33, count 0 2006.231.07:50:30.26#ibcon#about to read 6, iclass 33, count 0 2006.231.07:50:30.26#ibcon#read 6, iclass 33, count 0 2006.231.07:50:30.26#ibcon#end of sib2, iclass 33, count 0 2006.231.07:50:30.26#ibcon#*after write, iclass 33, count 0 2006.231.07:50:30.26#ibcon#*before return 0, iclass 33, count 0 2006.231.07:50:30.26#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:50:30.26#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.231.07:50:30.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.07:50:30.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.07:50:30.26$vc4f8/valo=8,852.99 2006.231.07:50:30.26#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.231.07:50:30.26#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.231.07:50:30.26#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:30.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:50:30.26#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:50:30.26#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:50:30.26#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:50:30.26#ibcon#first serial, iclass 35, count 0 2006.231.07:50:30.26#ibcon#enter sib2, iclass 35, count 0 2006.231.07:50:30.26#ibcon#flushed, iclass 35, count 0 2006.231.07:50:30.26#ibcon#about to write, iclass 35, count 0 2006.231.07:50:30.26#ibcon#wrote, iclass 35, count 0 2006.231.07:50:30.26#ibcon#about to read 3, iclass 35, count 0 2006.231.07:50:30.28#ibcon#read 3, iclass 35, count 0 2006.231.07:50:30.28#ibcon#about to read 4, iclass 35, count 0 2006.231.07:50:30.28#ibcon#read 4, iclass 35, count 0 2006.231.07:50:30.28#ibcon#about to read 5, iclass 35, count 0 2006.231.07:50:30.28#ibcon#read 5, iclass 35, count 0 2006.231.07:50:30.28#ibcon#about to read 6, iclass 35, count 0 2006.231.07:50:30.28#ibcon#read 6, iclass 35, count 0 2006.231.07:50:30.28#ibcon#end of sib2, iclass 35, count 0 2006.231.07:50:30.28#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:50:30.28#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:50:30.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:50:30.28#ibcon#*before write, iclass 35, count 0 2006.231.07:50:30.28#ibcon#enter sib2, iclass 35, count 0 2006.231.07:50:30.28#ibcon#flushed, iclass 35, count 0 2006.231.07:50:30.28#ibcon#about to write, iclass 35, count 0 2006.231.07:50:30.28#ibcon#wrote, iclass 35, count 0 2006.231.07:50:30.28#ibcon#about to read 3, iclass 35, count 0 2006.231.07:50:30.32#ibcon#read 3, iclass 35, count 0 2006.231.07:50:30.32#ibcon#about to read 4, iclass 35, count 0 2006.231.07:50:30.32#ibcon#read 4, iclass 35, count 0 2006.231.07:50:30.32#ibcon#about to read 5, iclass 35, count 0 2006.231.07:50:30.32#ibcon#read 5, iclass 35, count 0 2006.231.07:50:30.32#ibcon#about to read 6, iclass 35, count 0 2006.231.07:50:30.32#ibcon#read 6, iclass 35, count 0 2006.231.07:50:30.32#ibcon#end of sib2, iclass 35, count 0 2006.231.07:50:30.32#ibcon#*after write, iclass 35, count 0 2006.231.07:50:30.32#ibcon#*before return 0, iclass 35, count 0 2006.231.07:50:30.32#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:50:30.32#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.231.07:50:30.32#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:50:30.32#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:50:30.32$vc4f8/va=8,6 2006.231.07:50:30.32#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.231.07:50:30.32#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.231.07:50:30.32#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:30.32#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:50:30.38#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:50:30.38#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:50:30.38#ibcon#enter wrdev, iclass 37, count 2 2006.231.07:50:30.38#ibcon#first serial, iclass 37, count 2 2006.231.07:50:30.38#ibcon#enter sib2, iclass 37, count 2 2006.231.07:50:30.38#ibcon#flushed, iclass 37, count 2 2006.231.07:50:30.38#ibcon#about to write, iclass 37, count 2 2006.231.07:50:30.38#ibcon#wrote, iclass 37, count 2 2006.231.07:50:30.38#ibcon#about to read 3, iclass 37, count 2 2006.231.07:50:30.40#ibcon#read 3, iclass 37, count 2 2006.231.07:50:30.40#ibcon#about to read 4, iclass 37, count 2 2006.231.07:50:30.40#ibcon#read 4, iclass 37, count 2 2006.231.07:50:30.40#ibcon#about to read 5, iclass 37, count 2 2006.231.07:50:30.40#ibcon#read 5, iclass 37, count 2 2006.231.07:50:30.40#ibcon#about to read 6, iclass 37, count 2 2006.231.07:50:30.40#ibcon#read 6, iclass 37, count 2 2006.231.07:50:30.40#ibcon#end of sib2, iclass 37, count 2 2006.231.07:50:30.40#ibcon#*mode == 0, iclass 37, count 2 2006.231.07:50:30.40#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.231.07:50:30.40#ibcon#[25=AT08-06\r\n] 2006.231.07:50:30.40#ibcon#*before write, iclass 37, count 2 2006.231.07:50:30.40#ibcon#enter sib2, iclass 37, count 2 2006.231.07:50:30.40#ibcon#flushed, iclass 37, count 2 2006.231.07:50:30.40#ibcon#about to write, iclass 37, count 2 2006.231.07:50:30.40#ibcon#wrote, iclass 37, count 2 2006.231.07:50:30.40#ibcon#about to read 3, iclass 37, count 2 2006.231.07:50:30.43#ibcon#read 3, iclass 37, count 2 2006.231.07:50:30.43#ibcon#about to read 4, iclass 37, count 2 2006.231.07:50:30.43#ibcon#read 4, iclass 37, count 2 2006.231.07:50:30.43#ibcon#about to read 5, iclass 37, count 2 2006.231.07:50:30.43#ibcon#read 5, iclass 37, count 2 2006.231.07:50:30.43#ibcon#about to read 6, iclass 37, count 2 2006.231.07:50:30.43#ibcon#read 6, iclass 37, count 2 2006.231.07:50:30.43#ibcon#end of sib2, iclass 37, count 2 2006.231.07:50:30.43#ibcon#*after write, iclass 37, count 2 2006.231.07:50:30.43#ibcon#*before return 0, iclass 37, count 2 2006.231.07:50:30.43#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:50:30.43#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.231.07:50:30.43#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.231.07:50:30.43#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:30.43#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:50:30.55#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:50:30.55#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:50:30.55#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:50:30.55#ibcon#first serial, iclass 37, count 0 2006.231.07:50:30.55#ibcon#enter sib2, iclass 37, count 0 2006.231.07:50:30.55#ibcon#flushed, iclass 37, count 0 2006.231.07:50:30.55#ibcon#about to write, iclass 37, count 0 2006.231.07:50:30.55#ibcon#wrote, iclass 37, count 0 2006.231.07:50:30.55#ibcon#about to read 3, iclass 37, count 0 2006.231.07:50:30.57#ibcon#read 3, iclass 37, count 0 2006.231.07:50:30.57#ibcon#about to read 4, iclass 37, count 0 2006.231.07:50:30.57#ibcon#read 4, iclass 37, count 0 2006.231.07:50:30.57#ibcon#about to read 5, iclass 37, count 0 2006.231.07:50:30.57#ibcon#read 5, iclass 37, count 0 2006.231.07:50:30.57#ibcon#about to read 6, iclass 37, count 0 2006.231.07:50:30.57#ibcon#read 6, iclass 37, count 0 2006.231.07:50:30.57#ibcon#end of sib2, iclass 37, count 0 2006.231.07:50:30.57#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:50:30.57#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:50:30.57#ibcon#[25=USB\r\n] 2006.231.07:50:30.57#ibcon#*before write, iclass 37, count 0 2006.231.07:50:30.57#ibcon#enter sib2, iclass 37, count 0 2006.231.07:50:30.57#ibcon#flushed, iclass 37, count 0 2006.231.07:50:30.57#ibcon#about to write, iclass 37, count 0 2006.231.07:50:30.57#ibcon#wrote, iclass 37, count 0 2006.231.07:50:30.57#ibcon#about to read 3, iclass 37, count 0 2006.231.07:50:30.60#ibcon#read 3, iclass 37, count 0 2006.231.07:50:30.60#ibcon#about to read 4, iclass 37, count 0 2006.231.07:50:30.60#ibcon#read 4, iclass 37, count 0 2006.231.07:50:30.60#ibcon#about to read 5, iclass 37, count 0 2006.231.07:50:30.60#ibcon#read 5, iclass 37, count 0 2006.231.07:50:30.60#ibcon#about to read 6, iclass 37, count 0 2006.231.07:50:30.60#ibcon#read 6, iclass 37, count 0 2006.231.07:50:30.60#ibcon#end of sib2, iclass 37, count 0 2006.231.07:50:30.60#ibcon#*after write, iclass 37, count 0 2006.231.07:50:30.60#ibcon#*before return 0, iclass 37, count 0 2006.231.07:50:30.60#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:50:30.60#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.231.07:50:30.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:50:30.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:50:30.60$vc4f8/vblo=1,632.99 2006.231.07:50:30.60#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.07:50:30.60#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.07:50:30.60#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:30.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:50:30.60#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:50:30.60#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:50:30.60#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:50:30.60#ibcon#first serial, iclass 39, count 0 2006.231.07:50:30.60#ibcon#enter sib2, iclass 39, count 0 2006.231.07:50:30.60#ibcon#flushed, iclass 39, count 0 2006.231.07:50:30.60#ibcon#about to write, iclass 39, count 0 2006.231.07:50:30.60#ibcon#wrote, iclass 39, count 0 2006.231.07:50:30.60#ibcon#about to read 3, iclass 39, count 0 2006.231.07:50:30.62#ibcon#read 3, iclass 39, count 0 2006.231.07:50:30.62#ibcon#about to read 4, iclass 39, count 0 2006.231.07:50:30.62#ibcon#read 4, iclass 39, count 0 2006.231.07:50:30.62#ibcon#about to read 5, iclass 39, count 0 2006.231.07:50:30.62#ibcon#read 5, iclass 39, count 0 2006.231.07:50:30.62#ibcon#about to read 6, iclass 39, count 0 2006.231.07:50:30.62#ibcon#read 6, iclass 39, count 0 2006.231.07:50:30.62#ibcon#end of sib2, iclass 39, count 0 2006.231.07:50:30.62#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:50:30.62#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:50:30.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:50:30.62#ibcon#*before write, iclass 39, count 0 2006.231.07:50:30.62#ibcon#enter sib2, iclass 39, count 0 2006.231.07:50:30.62#ibcon#flushed, iclass 39, count 0 2006.231.07:50:30.62#ibcon#about to write, iclass 39, count 0 2006.231.07:50:30.62#ibcon#wrote, iclass 39, count 0 2006.231.07:50:30.62#ibcon#about to read 3, iclass 39, count 0 2006.231.07:50:30.66#ibcon#read 3, iclass 39, count 0 2006.231.07:50:30.66#ibcon#about to read 4, iclass 39, count 0 2006.231.07:50:30.66#ibcon#read 4, iclass 39, count 0 2006.231.07:50:30.66#ibcon#about to read 5, iclass 39, count 0 2006.231.07:50:30.66#ibcon#read 5, iclass 39, count 0 2006.231.07:50:30.66#ibcon#about to read 6, iclass 39, count 0 2006.231.07:50:30.66#ibcon#read 6, iclass 39, count 0 2006.231.07:50:30.66#ibcon#end of sib2, iclass 39, count 0 2006.231.07:50:30.66#ibcon#*after write, iclass 39, count 0 2006.231.07:50:30.66#ibcon#*before return 0, iclass 39, count 0 2006.231.07:50:30.66#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:50:30.66#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.07:50:30.66#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:50:30.66#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:50:30.66$vc4f8/vb=1,4 2006.231.07:50:30.66#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.231.07:50:30.66#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.231.07:50:30.66#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:30.66#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:50:30.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:50:30.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:50:30.66#ibcon#enter wrdev, iclass 3, count 2 2006.231.07:50:30.66#ibcon#first serial, iclass 3, count 2 2006.231.07:50:30.66#ibcon#enter sib2, iclass 3, count 2 2006.231.07:50:30.66#ibcon#flushed, iclass 3, count 2 2006.231.07:50:30.66#ibcon#about to write, iclass 3, count 2 2006.231.07:50:30.66#ibcon#wrote, iclass 3, count 2 2006.231.07:50:30.66#ibcon#about to read 3, iclass 3, count 2 2006.231.07:50:30.68#ibcon#read 3, iclass 3, count 2 2006.231.07:50:30.68#ibcon#about to read 4, iclass 3, count 2 2006.231.07:50:30.68#ibcon#read 4, iclass 3, count 2 2006.231.07:50:30.68#ibcon#about to read 5, iclass 3, count 2 2006.231.07:50:30.68#ibcon#read 5, iclass 3, count 2 2006.231.07:50:30.68#ibcon#about to read 6, iclass 3, count 2 2006.231.07:50:30.68#ibcon#read 6, iclass 3, count 2 2006.231.07:50:30.68#ibcon#end of sib2, iclass 3, count 2 2006.231.07:50:30.68#ibcon#*mode == 0, iclass 3, count 2 2006.231.07:50:30.68#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.231.07:50:30.68#ibcon#[27=AT01-04\r\n] 2006.231.07:50:30.68#ibcon#*before write, iclass 3, count 2 2006.231.07:50:30.68#ibcon#enter sib2, iclass 3, count 2 2006.231.07:50:30.68#ibcon#flushed, iclass 3, count 2 2006.231.07:50:30.68#ibcon#about to write, iclass 3, count 2 2006.231.07:50:30.68#ibcon#wrote, iclass 3, count 2 2006.231.07:50:30.68#ibcon#about to read 3, iclass 3, count 2 2006.231.07:50:30.71#ibcon#read 3, iclass 3, count 2 2006.231.07:50:30.71#ibcon#about to read 4, iclass 3, count 2 2006.231.07:50:30.71#ibcon#read 4, iclass 3, count 2 2006.231.07:50:30.71#ibcon#about to read 5, iclass 3, count 2 2006.231.07:50:30.71#ibcon#read 5, iclass 3, count 2 2006.231.07:50:30.71#ibcon#about to read 6, iclass 3, count 2 2006.231.07:50:30.71#ibcon#read 6, iclass 3, count 2 2006.231.07:50:30.71#ibcon#end of sib2, iclass 3, count 2 2006.231.07:50:30.71#ibcon#*after write, iclass 3, count 2 2006.231.07:50:30.71#ibcon#*before return 0, iclass 3, count 2 2006.231.07:50:30.71#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:50:30.71#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.231.07:50:30.71#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.231.07:50:30.71#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:30.71#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:50:30.83#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:50:30.83#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:50:30.83#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:50:30.83#ibcon#first serial, iclass 3, count 0 2006.231.07:50:30.83#ibcon#enter sib2, iclass 3, count 0 2006.231.07:50:30.83#ibcon#flushed, iclass 3, count 0 2006.231.07:50:30.83#ibcon#about to write, iclass 3, count 0 2006.231.07:50:30.83#ibcon#wrote, iclass 3, count 0 2006.231.07:50:30.83#ibcon#about to read 3, iclass 3, count 0 2006.231.07:50:30.85#ibcon#read 3, iclass 3, count 0 2006.231.07:50:30.85#ibcon#about to read 4, iclass 3, count 0 2006.231.07:50:30.85#ibcon#read 4, iclass 3, count 0 2006.231.07:50:30.85#ibcon#about to read 5, iclass 3, count 0 2006.231.07:50:30.85#ibcon#read 5, iclass 3, count 0 2006.231.07:50:30.85#ibcon#about to read 6, iclass 3, count 0 2006.231.07:50:30.85#ibcon#read 6, iclass 3, count 0 2006.231.07:50:30.85#ibcon#end of sib2, iclass 3, count 0 2006.231.07:50:30.85#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:50:30.85#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:50:30.85#ibcon#[27=USB\r\n] 2006.231.07:50:30.85#ibcon#*before write, iclass 3, count 0 2006.231.07:50:30.85#ibcon#enter sib2, iclass 3, count 0 2006.231.07:50:30.85#ibcon#flushed, iclass 3, count 0 2006.231.07:50:30.85#ibcon#about to write, iclass 3, count 0 2006.231.07:50:30.85#ibcon#wrote, iclass 3, count 0 2006.231.07:50:30.85#ibcon#about to read 3, iclass 3, count 0 2006.231.07:50:30.88#ibcon#read 3, iclass 3, count 0 2006.231.07:50:30.88#ibcon#about to read 4, iclass 3, count 0 2006.231.07:50:30.88#ibcon#read 4, iclass 3, count 0 2006.231.07:50:30.88#ibcon#about to read 5, iclass 3, count 0 2006.231.07:50:30.88#ibcon#read 5, iclass 3, count 0 2006.231.07:50:30.88#ibcon#about to read 6, iclass 3, count 0 2006.231.07:50:30.88#ibcon#read 6, iclass 3, count 0 2006.231.07:50:30.88#ibcon#end of sib2, iclass 3, count 0 2006.231.07:50:30.88#ibcon#*after write, iclass 3, count 0 2006.231.07:50:30.88#ibcon#*before return 0, iclass 3, count 0 2006.231.07:50:30.88#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:50:30.88#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.231.07:50:30.88#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:50:30.88#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:50:30.88$vc4f8/vblo=2,640.99 2006.231.07:50:30.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.231.07:50:30.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.231.07:50:30.88#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:30.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:50:30.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:50:30.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:50:30.88#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:50:30.88#ibcon#first serial, iclass 5, count 0 2006.231.07:50:30.88#ibcon#enter sib2, iclass 5, count 0 2006.231.07:50:30.88#ibcon#flushed, iclass 5, count 0 2006.231.07:50:30.88#ibcon#about to write, iclass 5, count 0 2006.231.07:50:30.88#ibcon#wrote, iclass 5, count 0 2006.231.07:50:30.88#ibcon#about to read 3, iclass 5, count 0 2006.231.07:50:30.90#ibcon#read 3, iclass 5, count 0 2006.231.07:50:30.90#ibcon#about to read 4, iclass 5, count 0 2006.231.07:50:30.90#ibcon#read 4, iclass 5, count 0 2006.231.07:50:30.90#ibcon#about to read 5, iclass 5, count 0 2006.231.07:50:30.90#ibcon#read 5, iclass 5, count 0 2006.231.07:50:30.90#ibcon#about to read 6, iclass 5, count 0 2006.231.07:50:30.90#ibcon#read 6, iclass 5, count 0 2006.231.07:50:30.90#ibcon#end of sib2, iclass 5, count 0 2006.231.07:50:30.90#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:50:30.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:50:30.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:50:30.90#ibcon#*before write, iclass 5, count 0 2006.231.07:50:30.90#ibcon#enter sib2, iclass 5, count 0 2006.231.07:50:30.90#ibcon#flushed, iclass 5, count 0 2006.231.07:50:30.90#ibcon#about to write, iclass 5, count 0 2006.231.07:50:30.90#ibcon#wrote, iclass 5, count 0 2006.231.07:50:30.90#ibcon#about to read 3, iclass 5, count 0 2006.231.07:50:30.94#ibcon#read 3, iclass 5, count 0 2006.231.07:50:30.94#ibcon#about to read 4, iclass 5, count 0 2006.231.07:50:30.94#ibcon#read 4, iclass 5, count 0 2006.231.07:50:30.94#ibcon#about to read 5, iclass 5, count 0 2006.231.07:50:30.94#ibcon#read 5, iclass 5, count 0 2006.231.07:50:30.94#ibcon#about to read 6, iclass 5, count 0 2006.231.07:50:30.94#ibcon#read 6, iclass 5, count 0 2006.231.07:50:30.94#ibcon#end of sib2, iclass 5, count 0 2006.231.07:50:30.94#ibcon#*after write, iclass 5, count 0 2006.231.07:50:30.94#ibcon#*before return 0, iclass 5, count 0 2006.231.07:50:30.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:50:30.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.231.07:50:30.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:50:30.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:50:30.94$vc4f8/vb=2,4 2006.231.07:50:30.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.231.07:50:30.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.231.07:50:30.94#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:30.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:50:31.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:50:31.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:50:31.00#ibcon#enter wrdev, iclass 7, count 2 2006.231.07:50:31.00#ibcon#first serial, iclass 7, count 2 2006.231.07:50:31.00#ibcon#enter sib2, iclass 7, count 2 2006.231.07:50:31.00#ibcon#flushed, iclass 7, count 2 2006.231.07:50:31.00#ibcon#about to write, iclass 7, count 2 2006.231.07:50:31.00#ibcon#wrote, iclass 7, count 2 2006.231.07:50:31.00#ibcon#about to read 3, iclass 7, count 2 2006.231.07:50:31.02#ibcon#read 3, iclass 7, count 2 2006.231.07:50:31.02#ibcon#about to read 4, iclass 7, count 2 2006.231.07:50:31.02#ibcon#read 4, iclass 7, count 2 2006.231.07:50:31.02#ibcon#about to read 5, iclass 7, count 2 2006.231.07:50:31.02#ibcon#read 5, iclass 7, count 2 2006.231.07:50:31.02#ibcon#about to read 6, iclass 7, count 2 2006.231.07:50:31.02#ibcon#read 6, iclass 7, count 2 2006.231.07:50:31.02#ibcon#end of sib2, iclass 7, count 2 2006.231.07:50:31.02#ibcon#*mode == 0, iclass 7, count 2 2006.231.07:50:31.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.231.07:50:31.02#ibcon#[27=AT02-04\r\n] 2006.231.07:50:31.02#ibcon#*before write, iclass 7, count 2 2006.231.07:50:31.02#ibcon#enter sib2, iclass 7, count 2 2006.231.07:50:31.02#ibcon#flushed, iclass 7, count 2 2006.231.07:50:31.02#ibcon#about to write, iclass 7, count 2 2006.231.07:50:31.02#ibcon#wrote, iclass 7, count 2 2006.231.07:50:31.02#ibcon#about to read 3, iclass 7, count 2 2006.231.07:50:31.05#ibcon#read 3, iclass 7, count 2 2006.231.07:50:31.05#ibcon#about to read 4, iclass 7, count 2 2006.231.07:50:31.05#ibcon#read 4, iclass 7, count 2 2006.231.07:50:31.05#ibcon#about to read 5, iclass 7, count 2 2006.231.07:50:31.05#ibcon#read 5, iclass 7, count 2 2006.231.07:50:31.05#ibcon#about to read 6, iclass 7, count 2 2006.231.07:50:31.05#ibcon#read 6, iclass 7, count 2 2006.231.07:50:31.05#ibcon#end of sib2, iclass 7, count 2 2006.231.07:50:31.05#ibcon#*after write, iclass 7, count 2 2006.231.07:50:31.05#ibcon#*before return 0, iclass 7, count 2 2006.231.07:50:31.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:50:31.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.231.07:50:31.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.231.07:50:31.05#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:31.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:50:31.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:50:31.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:50:31.17#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:50:31.17#ibcon#first serial, iclass 7, count 0 2006.231.07:50:31.17#ibcon#enter sib2, iclass 7, count 0 2006.231.07:50:31.17#ibcon#flushed, iclass 7, count 0 2006.231.07:50:31.17#ibcon#about to write, iclass 7, count 0 2006.231.07:50:31.17#ibcon#wrote, iclass 7, count 0 2006.231.07:50:31.17#ibcon#about to read 3, iclass 7, count 0 2006.231.07:50:31.19#ibcon#read 3, iclass 7, count 0 2006.231.07:50:31.19#ibcon#about to read 4, iclass 7, count 0 2006.231.07:50:31.19#ibcon#read 4, iclass 7, count 0 2006.231.07:50:31.19#ibcon#about to read 5, iclass 7, count 0 2006.231.07:50:31.19#ibcon#read 5, iclass 7, count 0 2006.231.07:50:31.19#ibcon#about to read 6, iclass 7, count 0 2006.231.07:50:31.19#ibcon#read 6, iclass 7, count 0 2006.231.07:50:31.19#ibcon#end of sib2, iclass 7, count 0 2006.231.07:50:31.19#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:50:31.19#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:50:31.19#ibcon#[27=USB\r\n] 2006.231.07:50:31.19#ibcon#*before write, iclass 7, count 0 2006.231.07:50:31.19#ibcon#enter sib2, iclass 7, count 0 2006.231.07:50:31.19#ibcon#flushed, iclass 7, count 0 2006.231.07:50:31.19#ibcon#about to write, iclass 7, count 0 2006.231.07:50:31.19#ibcon#wrote, iclass 7, count 0 2006.231.07:50:31.19#ibcon#about to read 3, iclass 7, count 0 2006.231.07:50:31.22#ibcon#read 3, iclass 7, count 0 2006.231.07:50:31.22#ibcon#about to read 4, iclass 7, count 0 2006.231.07:50:31.22#ibcon#read 4, iclass 7, count 0 2006.231.07:50:31.22#ibcon#about to read 5, iclass 7, count 0 2006.231.07:50:31.22#ibcon#read 5, iclass 7, count 0 2006.231.07:50:31.22#ibcon#about to read 6, iclass 7, count 0 2006.231.07:50:31.22#ibcon#read 6, iclass 7, count 0 2006.231.07:50:31.22#ibcon#end of sib2, iclass 7, count 0 2006.231.07:50:31.22#ibcon#*after write, iclass 7, count 0 2006.231.07:50:31.22#ibcon#*before return 0, iclass 7, count 0 2006.231.07:50:31.22#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:50:31.22#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.231.07:50:31.22#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:50:31.22#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:50:31.22$vc4f8/vblo=3,656.99 2006.231.07:50:31.22#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.231.07:50:31.22#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.231.07:50:31.22#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:31.22#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:50:31.22#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:50:31.22#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:50:31.22#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:50:31.22#ibcon#first serial, iclass 11, count 0 2006.231.07:50:31.22#ibcon#enter sib2, iclass 11, count 0 2006.231.07:50:31.22#ibcon#flushed, iclass 11, count 0 2006.231.07:50:31.22#ibcon#about to write, iclass 11, count 0 2006.231.07:50:31.22#ibcon#wrote, iclass 11, count 0 2006.231.07:50:31.22#ibcon#about to read 3, iclass 11, count 0 2006.231.07:50:31.24#ibcon#read 3, iclass 11, count 0 2006.231.07:50:31.24#ibcon#about to read 4, iclass 11, count 0 2006.231.07:50:31.24#ibcon#read 4, iclass 11, count 0 2006.231.07:50:31.24#ibcon#about to read 5, iclass 11, count 0 2006.231.07:50:31.24#ibcon#read 5, iclass 11, count 0 2006.231.07:50:31.24#ibcon#about to read 6, iclass 11, count 0 2006.231.07:50:31.24#ibcon#read 6, iclass 11, count 0 2006.231.07:50:31.24#ibcon#end of sib2, iclass 11, count 0 2006.231.07:50:31.24#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:50:31.24#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:50:31.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:50:31.24#ibcon#*before write, iclass 11, count 0 2006.231.07:50:31.24#ibcon#enter sib2, iclass 11, count 0 2006.231.07:50:31.24#ibcon#flushed, iclass 11, count 0 2006.231.07:50:31.24#ibcon#about to write, iclass 11, count 0 2006.231.07:50:31.24#ibcon#wrote, iclass 11, count 0 2006.231.07:50:31.24#ibcon#about to read 3, iclass 11, count 0 2006.231.07:50:31.28#ibcon#read 3, iclass 11, count 0 2006.231.07:50:31.28#ibcon#about to read 4, iclass 11, count 0 2006.231.07:50:31.28#ibcon#read 4, iclass 11, count 0 2006.231.07:50:31.28#ibcon#about to read 5, iclass 11, count 0 2006.231.07:50:31.28#ibcon#read 5, iclass 11, count 0 2006.231.07:50:31.28#ibcon#about to read 6, iclass 11, count 0 2006.231.07:50:31.28#ibcon#read 6, iclass 11, count 0 2006.231.07:50:31.28#ibcon#end of sib2, iclass 11, count 0 2006.231.07:50:31.28#ibcon#*after write, iclass 11, count 0 2006.231.07:50:31.28#ibcon#*before return 0, iclass 11, count 0 2006.231.07:50:31.28#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:50:31.28#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.231.07:50:31.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:50:31.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:50:31.28$vc4f8/vb=3,4 2006.231.07:50:31.28#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.231.07:50:31.28#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.231.07:50:31.28#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:31.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:50:31.34#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:50:31.34#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:50:31.34#ibcon#enter wrdev, iclass 13, count 2 2006.231.07:50:31.34#ibcon#first serial, iclass 13, count 2 2006.231.07:50:31.34#ibcon#enter sib2, iclass 13, count 2 2006.231.07:50:31.34#ibcon#flushed, iclass 13, count 2 2006.231.07:50:31.34#ibcon#about to write, iclass 13, count 2 2006.231.07:50:31.34#ibcon#wrote, iclass 13, count 2 2006.231.07:50:31.34#ibcon#about to read 3, iclass 13, count 2 2006.231.07:50:31.36#ibcon#read 3, iclass 13, count 2 2006.231.07:50:31.36#ibcon#about to read 4, iclass 13, count 2 2006.231.07:50:31.36#ibcon#read 4, iclass 13, count 2 2006.231.07:50:31.36#ibcon#about to read 5, iclass 13, count 2 2006.231.07:50:31.36#ibcon#read 5, iclass 13, count 2 2006.231.07:50:31.36#ibcon#about to read 6, iclass 13, count 2 2006.231.07:50:31.36#ibcon#read 6, iclass 13, count 2 2006.231.07:50:31.36#ibcon#end of sib2, iclass 13, count 2 2006.231.07:50:31.36#ibcon#*mode == 0, iclass 13, count 2 2006.231.07:50:31.36#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.231.07:50:31.36#ibcon#[27=AT03-04\r\n] 2006.231.07:50:31.36#ibcon#*before write, iclass 13, count 2 2006.231.07:50:31.36#ibcon#enter sib2, iclass 13, count 2 2006.231.07:50:31.36#ibcon#flushed, iclass 13, count 2 2006.231.07:50:31.36#ibcon#about to write, iclass 13, count 2 2006.231.07:50:31.36#ibcon#wrote, iclass 13, count 2 2006.231.07:50:31.36#ibcon#about to read 3, iclass 13, count 2 2006.231.07:50:31.39#ibcon#read 3, iclass 13, count 2 2006.231.07:50:31.39#ibcon#about to read 4, iclass 13, count 2 2006.231.07:50:31.39#ibcon#read 4, iclass 13, count 2 2006.231.07:50:31.39#ibcon#about to read 5, iclass 13, count 2 2006.231.07:50:31.39#ibcon#read 5, iclass 13, count 2 2006.231.07:50:31.39#ibcon#about to read 6, iclass 13, count 2 2006.231.07:50:31.39#ibcon#read 6, iclass 13, count 2 2006.231.07:50:31.39#ibcon#end of sib2, iclass 13, count 2 2006.231.07:50:31.39#ibcon#*after write, iclass 13, count 2 2006.231.07:50:31.39#ibcon#*before return 0, iclass 13, count 2 2006.231.07:50:31.39#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:50:31.39#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.231.07:50:31.39#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.231.07:50:31.39#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:31.39#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:50:31.51#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:50:31.51#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:50:31.51#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:50:31.51#ibcon#first serial, iclass 13, count 0 2006.231.07:50:31.51#ibcon#enter sib2, iclass 13, count 0 2006.231.07:50:31.51#ibcon#flushed, iclass 13, count 0 2006.231.07:50:31.51#ibcon#about to write, iclass 13, count 0 2006.231.07:50:31.51#ibcon#wrote, iclass 13, count 0 2006.231.07:50:31.51#ibcon#about to read 3, iclass 13, count 0 2006.231.07:50:31.53#ibcon#read 3, iclass 13, count 0 2006.231.07:50:31.53#ibcon#about to read 4, iclass 13, count 0 2006.231.07:50:31.53#ibcon#read 4, iclass 13, count 0 2006.231.07:50:31.53#ibcon#about to read 5, iclass 13, count 0 2006.231.07:50:31.53#ibcon#read 5, iclass 13, count 0 2006.231.07:50:31.53#ibcon#about to read 6, iclass 13, count 0 2006.231.07:50:31.53#ibcon#read 6, iclass 13, count 0 2006.231.07:50:31.53#ibcon#end of sib2, iclass 13, count 0 2006.231.07:50:31.53#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:50:31.53#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:50:31.53#ibcon#[27=USB\r\n] 2006.231.07:50:31.53#ibcon#*before write, iclass 13, count 0 2006.231.07:50:31.53#ibcon#enter sib2, iclass 13, count 0 2006.231.07:50:31.53#ibcon#flushed, iclass 13, count 0 2006.231.07:50:31.53#ibcon#about to write, iclass 13, count 0 2006.231.07:50:31.53#ibcon#wrote, iclass 13, count 0 2006.231.07:50:31.53#ibcon#about to read 3, iclass 13, count 0 2006.231.07:50:31.56#ibcon#read 3, iclass 13, count 0 2006.231.07:50:31.56#ibcon#about to read 4, iclass 13, count 0 2006.231.07:50:31.56#ibcon#read 4, iclass 13, count 0 2006.231.07:50:31.56#ibcon#about to read 5, iclass 13, count 0 2006.231.07:50:31.56#ibcon#read 5, iclass 13, count 0 2006.231.07:50:31.56#ibcon#about to read 6, iclass 13, count 0 2006.231.07:50:31.56#ibcon#read 6, iclass 13, count 0 2006.231.07:50:31.56#ibcon#end of sib2, iclass 13, count 0 2006.231.07:50:31.56#ibcon#*after write, iclass 13, count 0 2006.231.07:50:31.56#ibcon#*before return 0, iclass 13, count 0 2006.231.07:50:31.56#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:50:31.56#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.231.07:50:31.56#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:50:31.56#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:50:31.56$vc4f8/vblo=4,712.99 2006.231.07:50:31.56#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.07:50:31.56#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.07:50:31.56#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:31.56#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:50:31.56#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:50:31.56#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:50:31.56#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:50:31.56#ibcon#first serial, iclass 15, count 0 2006.231.07:50:31.56#ibcon#enter sib2, iclass 15, count 0 2006.231.07:50:31.56#ibcon#flushed, iclass 15, count 0 2006.231.07:50:31.56#ibcon#about to write, iclass 15, count 0 2006.231.07:50:31.56#ibcon#wrote, iclass 15, count 0 2006.231.07:50:31.56#ibcon#about to read 3, iclass 15, count 0 2006.231.07:50:31.58#ibcon#read 3, iclass 15, count 0 2006.231.07:50:31.58#ibcon#about to read 4, iclass 15, count 0 2006.231.07:50:31.58#ibcon#read 4, iclass 15, count 0 2006.231.07:50:31.58#ibcon#about to read 5, iclass 15, count 0 2006.231.07:50:31.58#ibcon#read 5, iclass 15, count 0 2006.231.07:50:31.58#ibcon#about to read 6, iclass 15, count 0 2006.231.07:50:31.58#ibcon#read 6, iclass 15, count 0 2006.231.07:50:31.58#ibcon#end of sib2, iclass 15, count 0 2006.231.07:50:31.58#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:50:31.58#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:50:31.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:50:31.58#ibcon#*before write, iclass 15, count 0 2006.231.07:50:31.58#ibcon#enter sib2, iclass 15, count 0 2006.231.07:50:31.58#ibcon#flushed, iclass 15, count 0 2006.231.07:50:31.58#ibcon#about to write, iclass 15, count 0 2006.231.07:50:31.58#ibcon#wrote, iclass 15, count 0 2006.231.07:50:31.58#ibcon#about to read 3, iclass 15, count 0 2006.231.07:50:31.62#ibcon#read 3, iclass 15, count 0 2006.231.07:50:31.62#ibcon#about to read 4, iclass 15, count 0 2006.231.07:50:31.62#ibcon#read 4, iclass 15, count 0 2006.231.07:50:31.62#ibcon#about to read 5, iclass 15, count 0 2006.231.07:50:31.62#ibcon#read 5, iclass 15, count 0 2006.231.07:50:31.62#ibcon#about to read 6, iclass 15, count 0 2006.231.07:50:31.62#ibcon#read 6, iclass 15, count 0 2006.231.07:50:31.62#ibcon#end of sib2, iclass 15, count 0 2006.231.07:50:31.62#ibcon#*after write, iclass 15, count 0 2006.231.07:50:31.62#ibcon#*before return 0, iclass 15, count 0 2006.231.07:50:31.62#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:50:31.62#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.07:50:31.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:50:31.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:50:31.62$vc4f8/vb=4,4 2006.231.07:50:31.62#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.07:50:31.62#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.07:50:31.62#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:31.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:50:31.68#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:50:31.68#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:50:31.68#ibcon#enter wrdev, iclass 17, count 2 2006.231.07:50:31.68#ibcon#first serial, iclass 17, count 2 2006.231.07:50:31.68#ibcon#enter sib2, iclass 17, count 2 2006.231.07:50:31.68#ibcon#flushed, iclass 17, count 2 2006.231.07:50:31.68#ibcon#about to write, iclass 17, count 2 2006.231.07:50:31.68#ibcon#wrote, iclass 17, count 2 2006.231.07:50:31.68#ibcon#about to read 3, iclass 17, count 2 2006.231.07:50:31.70#ibcon#read 3, iclass 17, count 2 2006.231.07:50:31.70#ibcon#about to read 4, iclass 17, count 2 2006.231.07:50:31.70#ibcon#read 4, iclass 17, count 2 2006.231.07:50:31.70#ibcon#about to read 5, iclass 17, count 2 2006.231.07:50:31.70#ibcon#read 5, iclass 17, count 2 2006.231.07:50:31.70#ibcon#about to read 6, iclass 17, count 2 2006.231.07:50:31.70#ibcon#read 6, iclass 17, count 2 2006.231.07:50:31.70#ibcon#end of sib2, iclass 17, count 2 2006.231.07:50:31.70#ibcon#*mode == 0, iclass 17, count 2 2006.231.07:50:31.70#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.07:50:31.70#ibcon#[27=AT04-04\r\n] 2006.231.07:50:31.70#ibcon#*before write, iclass 17, count 2 2006.231.07:50:31.70#ibcon#enter sib2, iclass 17, count 2 2006.231.07:50:31.70#ibcon#flushed, iclass 17, count 2 2006.231.07:50:31.70#ibcon#about to write, iclass 17, count 2 2006.231.07:50:31.70#ibcon#wrote, iclass 17, count 2 2006.231.07:50:31.70#ibcon#about to read 3, iclass 17, count 2 2006.231.07:50:31.73#ibcon#read 3, iclass 17, count 2 2006.231.07:50:31.73#ibcon#about to read 4, iclass 17, count 2 2006.231.07:50:31.73#ibcon#read 4, iclass 17, count 2 2006.231.07:50:31.73#ibcon#about to read 5, iclass 17, count 2 2006.231.07:50:31.73#ibcon#read 5, iclass 17, count 2 2006.231.07:50:31.73#ibcon#about to read 6, iclass 17, count 2 2006.231.07:50:31.73#ibcon#read 6, iclass 17, count 2 2006.231.07:50:31.73#ibcon#end of sib2, iclass 17, count 2 2006.231.07:50:31.73#ibcon#*after write, iclass 17, count 2 2006.231.07:50:31.73#ibcon#*before return 0, iclass 17, count 2 2006.231.07:50:31.73#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:50:31.73#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.07:50:31.73#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.07:50:31.73#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:31.73#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:50:31.85#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:50:31.85#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:50:31.85#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:50:31.85#ibcon#first serial, iclass 17, count 0 2006.231.07:50:31.85#ibcon#enter sib2, iclass 17, count 0 2006.231.07:50:31.85#ibcon#flushed, iclass 17, count 0 2006.231.07:50:31.85#ibcon#about to write, iclass 17, count 0 2006.231.07:50:31.85#ibcon#wrote, iclass 17, count 0 2006.231.07:50:31.85#ibcon#about to read 3, iclass 17, count 0 2006.231.07:50:31.87#ibcon#read 3, iclass 17, count 0 2006.231.07:50:31.87#ibcon#about to read 4, iclass 17, count 0 2006.231.07:50:31.87#ibcon#read 4, iclass 17, count 0 2006.231.07:50:31.87#ibcon#about to read 5, iclass 17, count 0 2006.231.07:50:31.87#ibcon#read 5, iclass 17, count 0 2006.231.07:50:31.87#ibcon#about to read 6, iclass 17, count 0 2006.231.07:50:31.87#ibcon#read 6, iclass 17, count 0 2006.231.07:50:31.87#ibcon#end of sib2, iclass 17, count 0 2006.231.07:50:31.87#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:50:31.87#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:50:31.87#ibcon#[27=USB\r\n] 2006.231.07:50:31.87#ibcon#*before write, iclass 17, count 0 2006.231.07:50:31.87#ibcon#enter sib2, iclass 17, count 0 2006.231.07:50:31.87#ibcon#flushed, iclass 17, count 0 2006.231.07:50:31.87#ibcon#about to write, iclass 17, count 0 2006.231.07:50:31.87#ibcon#wrote, iclass 17, count 0 2006.231.07:50:31.87#ibcon#about to read 3, iclass 17, count 0 2006.231.07:50:31.90#ibcon#read 3, iclass 17, count 0 2006.231.07:50:31.90#ibcon#about to read 4, iclass 17, count 0 2006.231.07:50:31.90#ibcon#read 4, iclass 17, count 0 2006.231.07:50:31.90#ibcon#about to read 5, iclass 17, count 0 2006.231.07:50:31.90#ibcon#read 5, iclass 17, count 0 2006.231.07:50:31.90#ibcon#about to read 6, iclass 17, count 0 2006.231.07:50:31.90#ibcon#read 6, iclass 17, count 0 2006.231.07:50:31.90#ibcon#end of sib2, iclass 17, count 0 2006.231.07:50:31.90#ibcon#*after write, iclass 17, count 0 2006.231.07:50:31.90#ibcon#*before return 0, iclass 17, count 0 2006.231.07:50:31.90#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:50:31.90#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.07:50:31.90#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:50:31.90#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:50:31.90$vc4f8/vblo=5,744.99 2006.231.07:50:31.90#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.07:50:31.90#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.07:50:31.90#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:31.90#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:50:31.90#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:50:31.90#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:50:31.90#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:50:31.90#ibcon#first serial, iclass 19, count 0 2006.231.07:50:31.90#ibcon#enter sib2, iclass 19, count 0 2006.231.07:50:31.90#ibcon#flushed, iclass 19, count 0 2006.231.07:50:31.90#ibcon#about to write, iclass 19, count 0 2006.231.07:50:31.90#ibcon#wrote, iclass 19, count 0 2006.231.07:50:31.90#ibcon#about to read 3, iclass 19, count 0 2006.231.07:50:31.92#ibcon#read 3, iclass 19, count 0 2006.231.07:50:31.92#ibcon#about to read 4, iclass 19, count 0 2006.231.07:50:31.92#ibcon#read 4, iclass 19, count 0 2006.231.07:50:31.92#ibcon#about to read 5, iclass 19, count 0 2006.231.07:50:31.92#ibcon#read 5, iclass 19, count 0 2006.231.07:50:31.92#ibcon#about to read 6, iclass 19, count 0 2006.231.07:50:31.92#ibcon#read 6, iclass 19, count 0 2006.231.07:50:31.92#ibcon#end of sib2, iclass 19, count 0 2006.231.07:50:31.92#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:50:31.92#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:50:31.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:50:31.92#ibcon#*before write, iclass 19, count 0 2006.231.07:50:31.92#ibcon#enter sib2, iclass 19, count 0 2006.231.07:50:31.92#ibcon#flushed, iclass 19, count 0 2006.231.07:50:31.92#ibcon#about to write, iclass 19, count 0 2006.231.07:50:31.92#ibcon#wrote, iclass 19, count 0 2006.231.07:50:31.92#ibcon#about to read 3, iclass 19, count 0 2006.231.07:50:31.96#ibcon#read 3, iclass 19, count 0 2006.231.07:50:31.96#ibcon#about to read 4, iclass 19, count 0 2006.231.07:50:31.96#ibcon#read 4, iclass 19, count 0 2006.231.07:50:31.96#ibcon#about to read 5, iclass 19, count 0 2006.231.07:50:31.96#ibcon#read 5, iclass 19, count 0 2006.231.07:50:31.96#ibcon#about to read 6, iclass 19, count 0 2006.231.07:50:31.96#ibcon#read 6, iclass 19, count 0 2006.231.07:50:31.96#ibcon#end of sib2, iclass 19, count 0 2006.231.07:50:31.96#ibcon#*after write, iclass 19, count 0 2006.231.07:50:31.96#ibcon#*before return 0, iclass 19, count 0 2006.231.07:50:31.96#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:50:31.96#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:50:31.96#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:50:31.96#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:50:31.96$vc4f8/vb=5,3 2006.231.07:50:31.96#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.231.07:50:31.96#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.231.07:50:31.96#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:31.96#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:50:32.02#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:50:32.02#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:50:32.02#ibcon#enter wrdev, iclass 21, count 2 2006.231.07:50:32.02#ibcon#first serial, iclass 21, count 2 2006.231.07:50:32.02#ibcon#enter sib2, iclass 21, count 2 2006.231.07:50:32.02#ibcon#flushed, iclass 21, count 2 2006.231.07:50:32.02#ibcon#about to write, iclass 21, count 2 2006.231.07:50:32.02#ibcon#wrote, iclass 21, count 2 2006.231.07:50:32.02#ibcon#about to read 3, iclass 21, count 2 2006.231.07:50:32.04#ibcon#read 3, iclass 21, count 2 2006.231.07:50:32.04#ibcon#about to read 4, iclass 21, count 2 2006.231.07:50:32.04#ibcon#read 4, iclass 21, count 2 2006.231.07:50:32.04#ibcon#about to read 5, iclass 21, count 2 2006.231.07:50:32.04#ibcon#read 5, iclass 21, count 2 2006.231.07:50:32.04#ibcon#about to read 6, iclass 21, count 2 2006.231.07:50:32.04#ibcon#read 6, iclass 21, count 2 2006.231.07:50:32.04#ibcon#end of sib2, iclass 21, count 2 2006.231.07:50:32.04#ibcon#*mode == 0, iclass 21, count 2 2006.231.07:50:32.04#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.231.07:50:32.04#ibcon#[27=AT05-03\r\n] 2006.231.07:50:32.04#ibcon#*before write, iclass 21, count 2 2006.231.07:50:32.04#ibcon#enter sib2, iclass 21, count 2 2006.231.07:50:32.04#ibcon#flushed, iclass 21, count 2 2006.231.07:50:32.04#ibcon#about to write, iclass 21, count 2 2006.231.07:50:32.04#ibcon#wrote, iclass 21, count 2 2006.231.07:50:32.04#ibcon#about to read 3, iclass 21, count 2 2006.231.07:50:32.07#ibcon#read 3, iclass 21, count 2 2006.231.07:50:32.07#ibcon#about to read 4, iclass 21, count 2 2006.231.07:50:32.07#ibcon#read 4, iclass 21, count 2 2006.231.07:50:32.07#ibcon#about to read 5, iclass 21, count 2 2006.231.07:50:32.07#ibcon#read 5, iclass 21, count 2 2006.231.07:50:32.07#ibcon#about to read 6, iclass 21, count 2 2006.231.07:50:32.07#ibcon#read 6, iclass 21, count 2 2006.231.07:50:32.07#ibcon#end of sib2, iclass 21, count 2 2006.231.07:50:32.07#ibcon#*after write, iclass 21, count 2 2006.231.07:50:32.07#ibcon#*before return 0, iclass 21, count 2 2006.231.07:50:32.07#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:50:32.07#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.231.07:50:32.07#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.231.07:50:32.07#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:32.07#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:50:32.19#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:50:32.19#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:50:32.19#ibcon#enter wrdev, iclass 21, count 0 2006.231.07:50:32.19#ibcon#first serial, iclass 21, count 0 2006.231.07:50:32.19#ibcon#enter sib2, iclass 21, count 0 2006.231.07:50:32.19#ibcon#flushed, iclass 21, count 0 2006.231.07:50:32.19#ibcon#about to write, iclass 21, count 0 2006.231.07:50:32.19#ibcon#wrote, iclass 21, count 0 2006.231.07:50:32.19#ibcon#about to read 3, iclass 21, count 0 2006.231.07:50:32.21#ibcon#read 3, iclass 21, count 0 2006.231.07:50:32.21#ibcon#about to read 4, iclass 21, count 0 2006.231.07:50:32.21#ibcon#read 4, iclass 21, count 0 2006.231.07:50:32.21#ibcon#about to read 5, iclass 21, count 0 2006.231.07:50:32.21#ibcon#read 5, iclass 21, count 0 2006.231.07:50:32.21#ibcon#about to read 6, iclass 21, count 0 2006.231.07:50:32.21#ibcon#read 6, iclass 21, count 0 2006.231.07:50:32.21#ibcon#end of sib2, iclass 21, count 0 2006.231.07:50:32.21#ibcon#*mode == 0, iclass 21, count 0 2006.231.07:50:32.21#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.07:50:32.21#ibcon#[27=USB\r\n] 2006.231.07:50:32.21#ibcon#*before write, iclass 21, count 0 2006.231.07:50:32.21#ibcon#enter sib2, iclass 21, count 0 2006.231.07:50:32.21#ibcon#flushed, iclass 21, count 0 2006.231.07:50:32.21#ibcon#about to write, iclass 21, count 0 2006.231.07:50:32.21#ibcon#wrote, iclass 21, count 0 2006.231.07:50:32.21#ibcon#about to read 3, iclass 21, count 0 2006.231.07:50:32.24#ibcon#read 3, iclass 21, count 0 2006.231.07:50:32.24#ibcon#about to read 4, iclass 21, count 0 2006.231.07:50:32.24#ibcon#read 4, iclass 21, count 0 2006.231.07:50:32.24#ibcon#about to read 5, iclass 21, count 0 2006.231.07:50:32.24#ibcon#read 5, iclass 21, count 0 2006.231.07:50:32.24#ibcon#about to read 6, iclass 21, count 0 2006.231.07:50:32.24#ibcon#read 6, iclass 21, count 0 2006.231.07:50:32.24#ibcon#end of sib2, iclass 21, count 0 2006.231.07:50:32.24#ibcon#*after write, iclass 21, count 0 2006.231.07:50:32.24#ibcon#*before return 0, iclass 21, count 0 2006.231.07:50:32.24#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:50:32.24#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.231.07:50:32.24#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.07:50:32.24#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.07:50:32.24$vc4f8/vblo=6,752.99 2006.231.07:50:32.24#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.231.07:50:32.24#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.231.07:50:32.24#ibcon#ireg 17 cls_cnt 0 2006.231.07:50:32.24#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:50:32.24#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:50:32.24#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:50:32.24#ibcon#enter wrdev, iclass 23, count 0 2006.231.07:50:32.24#ibcon#first serial, iclass 23, count 0 2006.231.07:50:32.24#ibcon#enter sib2, iclass 23, count 0 2006.231.07:50:32.24#ibcon#flushed, iclass 23, count 0 2006.231.07:50:32.24#ibcon#about to write, iclass 23, count 0 2006.231.07:50:32.24#ibcon#wrote, iclass 23, count 0 2006.231.07:50:32.24#ibcon#about to read 3, iclass 23, count 0 2006.231.07:50:32.26#ibcon#read 3, iclass 23, count 0 2006.231.07:50:32.26#ibcon#about to read 4, iclass 23, count 0 2006.231.07:50:32.26#ibcon#read 4, iclass 23, count 0 2006.231.07:50:32.26#ibcon#about to read 5, iclass 23, count 0 2006.231.07:50:32.26#ibcon#read 5, iclass 23, count 0 2006.231.07:50:32.26#ibcon#about to read 6, iclass 23, count 0 2006.231.07:50:32.26#ibcon#read 6, iclass 23, count 0 2006.231.07:50:32.26#ibcon#end of sib2, iclass 23, count 0 2006.231.07:50:32.26#ibcon#*mode == 0, iclass 23, count 0 2006.231.07:50:32.26#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.07:50:32.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:50:32.26#ibcon#*before write, iclass 23, count 0 2006.231.07:50:32.26#ibcon#enter sib2, iclass 23, count 0 2006.231.07:50:32.26#ibcon#flushed, iclass 23, count 0 2006.231.07:50:32.26#ibcon#about to write, iclass 23, count 0 2006.231.07:50:32.26#ibcon#wrote, iclass 23, count 0 2006.231.07:50:32.26#ibcon#about to read 3, iclass 23, count 0 2006.231.07:50:32.30#ibcon#read 3, iclass 23, count 0 2006.231.07:50:32.30#ibcon#about to read 4, iclass 23, count 0 2006.231.07:50:32.30#ibcon#read 4, iclass 23, count 0 2006.231.07:50:32.30#ibcon#about to read 5, iclass 23, count 0 2006.231.07:50:32.30#ibcon#read 5, iclass 23, count 0 2006.231.07:50:32.30#ibcon#about to read 6, iclass 23, count 0 2006.231.07:50:32.30#ibcon#read 6, iclass 23, count 0 2006.231.07:50:32.30#ibcon#end of sib2, iclass 23, count 0 2006.231.07:50:32.30#ibcon#*after write, iclass 23, count 0 2006.231.07:50:32.30#ibcon#*before return 0, iclass 23, count 0 2006.231.07:50:32.30#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:50:32.30#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.231.07:50:32.30#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.07:50:32.30#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.07:50:32.30$vc4f8/vb=6,4 2006.231.07:50:32.30#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.231.07:50:32.30#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.231.07:50:32.30#ibcon#ireg 11 cls_cnt 2 2006.231.07:50:32.30#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:50:32.36#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:50:32.36#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:50:32.36#ibcon#enter wrdev, iclass 25, count 2 2006.231.07:50:32.36#ibcon#first serial, iclass 25, count 2 2006.231.07:50:32.36#ibcon#enter sib2, iclass 25, count 2 2006.231.07:50:32.36#ibcon#flushed, iclass 25, count 2 2006.231.07:50:32.36#ibcon#about to write, iclass 25, count 2 2006.231.07:50:32.36#ibcon#wrote, iclass 25, count 2 2006.231.07:50:32.36#ibcon#about to read 3, iclass 25, count 2 2006.231.07:50:32.38#ibcon#read 3, iclass 25, count 2 2006.231.07:50:32.38#ibcon#about to read 4, iclass 25, count 2 2006.231.07:50:32.38#ibcon#read 4, iclass 25, count 2 2006.231.07:50:32.38#ibcon#about to read 5, iclass 25, count 2 2006.231.07:50:32.38#ibcon#read 5, iclass 25, count 2 2006.231.07:50:32.38#ibcon#about to read 6, iclass 25, count 2 2006.231.07:50:32.38#ibcon#read 6, iclass 25, count 2 2006.231.07:50:32.38#ibcon#end of sib2, iclass 25, count 2 2006.231.07:50:32.38#ibcon#*mode == 0, iclass 25, count 2 2006.231.07:50:32.38#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.231.07:50:32.38#ibcon#[27=AT06-04\r\n] 2006.231.07:50:32.38#ibcon#*before write, iclass 25, count 2 2006.231.07:50:32.38#ibcon#enter sib2, iclass 25, count 2 2006.231.07:50:32.38#ibcon#flushed, iclass 25, count 2 2006.231.07:50:32.38#ibcon#about to write, iclass 25, count 2 2006.231.07:50:32.38#ibcon#wrote, iclass 25, count 2 2006.231.07:50:32.38#ibcon#about to read 3, iclass 25, count 2 2006.231.07:50:32.41#ibcon#read 3, iclass 25, count 2 2006.231.07:50:32.41#ibcon#about to read 4, iclass 25, count 2 2006.231.07:50:32.41#ibcon#read 4, iclass 25, count 2 2006.231.07:50:32.41#ibcon#about to read 5, iclass 25, count 2 2006.231.07:50:32.41#ibcon#read 5, iclass 25, count 2 2006.231.07:50:32.41#ibcon#about to read 6, iclass 25, count 2 2006.231.07:50:32.41#ibcon#read 6, iclass 25, count 2 2006.231.07:50:32.41#ibcon#end of sib2, iclass 25, count 2 2006.231.07:50:32.41#ibcon#*after write, iclass 25, count 2 2006.231.07:50:32.41#ibcon#*before return 0, iclass 25, count 2 2006.231.07:50:32.41#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:50:32.41#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.231.07:50:32.41#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.231.07:50:32.41#ibcon#ireg 7 cls_cnt 0 2006.231.07:50:32.41#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:50:32.53#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:50:32.53#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:50:32.53#ibcon#enter wrdev, iclass 25, count 0 2006.231.07:50:32.53#ibcon#first serial, iclass 25, count 0 2006.231.07:50:32.53#ibcon#enter sib2, iclass 25, count 0 2006.231.07:50:32.53#ibcon#flushed, iclass 25, count 0 2006.231.07:50:32.53#ibcon#about to write, iclass 25, count 0 2006.231.07:50:32.53#ibcon#wrote, iclass 25, count 0 2006.231.07:50:32.53#ibcon#about to read 3, iclass 25, count 0 2006.231.07:50:32.55#ibcon#read 3, iclass 25, count 0 2006.231.07:50:32.55#ibcon#about to read 4, iclass 25, count 0 2006.231.07:50:32.55#ibcon#read 4, iclass 25, count 0 2006.231.07:50:32.55#ibcon#about to read 5, iclass 25, count 0 2006.231.07:50:32.55#ibcon#read 5, iclass 25, count 0 2006.231.07:50:32.55#ibcon#about to read 6, iclass 25, count 0 2006.231.07:50:32.55#ibcon#read 6, iclass 25, count 0 2006.231.07:50:32.55#ibcon#end of sib2, iclass 25, count 0 2006.231.07:50:32.55#ibcon#*mode == 0, iclass 25, count 0 2006.231.07:50:32.55#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.07:50:32.55#ibcon#[27=USB\r\n] 2006.231.07:50:32.55#ibcon#*before write, iclass 25, count 0 2006.231.07:50:32.55#ibcon#enter sib2, iclass 25, count 0 2006.231.07:50:32.55#ibcon#flushed, iclass 25, count 0 2006.231.07:50:32.55#ibcon#about to write, iclass 25, count 0 2006.231.07:50:32.55#ibcon#wrote, iclass 25, count 0 2006.231.07:50:32.55#ibcon#about to read 3, iclass 25, count 0 2006.231.07:50:32.58#ibcon#read 3, iclass 25, count 0 2006.231.07:50:32.58#ibcon#about to read 4, iclass 25, count 0 2006.231.07:50:32.58#ibcon#read 4, iclass 25, count 0 2006.231.07:50:32.58#ibcon#about to read 5, iclass 25, count 0 2006.231.07:50:32.58#ibcon#read 5, iclass 25, count 0 2006.231.07:50:32.58#ibcon#about to read 6, iclass 25, count 0 2006.231.07:50:32.58#ibcon#read 6, iclass 25, count 0 2006.231.07:50:32.58#ibcon#end of sib2, iclass 25, count 0 2006.231.07:50:32.58#ibcon#*after write, iclass 25, count 0 2006.231.07:50:32.58#ibcon#*before return 0, iclass 25, count 0 2006.231.07:50:32.58#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:50:32.58#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.231.07:50:32.58#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.07:50:32.58#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.07:50:32.58$vc4f8/vabw=wide 2006.231.07:50:32.58#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.231.07:50:32.58#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.231.07:50:32.58#ibcon#ireg 8 cls_cnt 0 2006.231.07:50:32.58#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:50:32.58#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:50:32.58#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:50:32.58#ibcon#enter wrdev, iclass 27, count 0 2006.231.07:50:32.58#ibcon#first serial, iclass 27, count 0 2006.231.07:50:32.58#ibcon#enter sib2, iclass 27, count 0 2006.231.07:50:32.58#ibcon#flushed, iclass 27, count 0 2006.231.07:50:32.58#ibcon#about to write, iclass 27, count 0 2006.231.07:50:32.58#ibcon#wrote, iclass 27, count 0 2006.231.07:50:32.58#ibcon#about to read 3, iclass 27, count 0 2006.231.07:50:32.60#ibcon#read 3, iclass 27, count 0 2006.231.07:50:32.60#ibcon#about to read 4, iclass 27, count 0 2006.231.07:50:32.60#ibcon#read 4, iclass 27, count 0 2006.231.07:50:32.60#ibcon#about to read 5, iclass 27, count 0 2006.231.07:50:32.60#ibcon#read 5, iclass 27, count 0 2006.231.07:50:32.60#ibcon#about to read 6, iclass 27, count 0 2006.231.07:50:32.60#ibcon#read 6, iclass 27, count 0 2006.231.07:50:32.60#ibcon#end of sib2, iclass 27, count 0 2006.231.07:50:32.60#ibcon#*mode == 0, iclass 27, count 0 2006.231.07:50:32.60#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.07:50:32.60#ibcon#[25=BW32\r\n] 2006.231.07:50:32.60#ibcon#*before write, iclass 27, count 0 2006.231.07:50:32.60#ibcon#enter sib2, iclass 27, count 0 2006.231.07:50:32.60#ibcon#flushed, iclass 27, count 0 2006.231.07:50:32.60#ibcon#about to write, iclass 27, count 0 2006.231.07:50:32.60#ibcon#wrote, iclass 27, count 0 2006.231.07:50:32.60#ibcon#about to read 3, iclass 27, count 0 2006.231.07:50:32.63#ibcon#read 3, iclass 27, count 0 2006.231.07:50:32.63#ibcon#about to read 4, iclass 27, count 0 2006.231.07:50:32.63#ibcon#read 4, iclass 27, count 0 2006.231.07:50:32.63#ibcon#about to read 5, iclass 27, count 0 2006.231.07:50:32.63#ibcon#read 5, iclass 27, count 0 2006.231.07:50:32.63#ibcon#about to read 6, iclass 27, count 0 2006.231.07:50:32.63#ibcon#read 6, iclass 27, count 0 2006.231.07:50:32.63#ibcon#end of sib2, iclass 27, count 0 2006.231.07:50:32.63#ibcon#*after write, iclass 27, count 0 2006.231.07:50:32.63#ibcon#*before return 0, iclass 27, count 0 2006.231.07:50:32.63#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:50:32.63#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.231.07:50:32.63#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.07:50:32.63#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.07:50:32.63$vc4f8/vbbw=wide 2006.231.07:50:32.63#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.231.07:50:32.63#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.231.07:50:32.63#ibcon#ireg 8 cls_cnt 0 2006.231.07:50:32.63#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:50:32.70#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:50:32.70#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:50:32.70#ibcon#enter wrdev, iclass 29, count 0 2006.231.07:50:32.70#ibcon#first serial, iclass 29, count 0 2006.231.07:50:32.70#ibcon#enter sib2, iclass 29, count 0 2006.231.07:50:32.70#ibcon#flushed, iclass 29, count 0 2006.231.07:50:32.70#ibcon#about to write, iclass 29, count 0 2006.231.07:50:32.70#ibcon#wrote, iclass 29, count 0 2006.231.07:50:32.70#ibcon#about to read 3, iclass 29, count 0 2006.231.07:50:32.72#ibcon#read 3, iclass 29, count 0 2006.231.07:50:32.72#ibcon#about to read 4, iclass 29, count 0 2006.231.07:50:32.72#ibcon#read 4, iclass 29, count 0 2006.231.07:50:32.72#ibcon#about to read 5, iclass 29, count 0 2006.231.07:50:32.72#ibcon#read 5, iclass 29, count 0 2006.231.07:50:32.72#ibcon#about to read 6, iclass 29, count 0 2006.231.07:50:32.72#ibcon#read 6, iclass 29, count 0 2006.231.07:50:32.72#ibcon#end of sib2, iclass 29, count 0 2006.231.07:50:32.72#ibcon#*mode == 0, iclass 29, count 0 2006.231.07:50:32.72#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.07:50:32.72#ibcon#[27=BW32\r\n] 2006.231.07:50:32.72#ibcon#*before write, iclass 29, count 0 2006.231.07:50:32.72#ibcon#enter sib2, iclass 29, count 0 2006.231.07:50:32.72#ibcon#flushed, iclass 29, count 0 2006.231.07:50:32.72#ibcon#about to write, iclass 29, count 0 2006.231.07:50:32.72#ibcon#wrote, iclass 29, count 0 2006.231.07:50:32.72#ibcon#about to read 3, iclass 29, count 0 2006.231.07:50:32.75#ibcon#read 3, iclass 29, count 0 2006.231.07:50:32.75#ibcon#about to read 4, iclass 29, count 0 2006.231.07:50:32.75#ibcon#read 4, iclass 29, count 0 2006.231.07:50:32.75#ibcon#about to read 5, iclass 29, count 0 2006.231.07:50:32.75#ibcon#read 5, iclass 29, count 0 2006.231.07:50:32.75#ibcon#about to read 6, iclass 29, count 0 2006.231.07:50:32.75#ibcon#read 6, iclass 29, count 0 2006.231.07:50:32.75#ibcon#end of sib2, iclass 29, count 0 2006.231.07:50:32.75#ibcon#*after write, iclass 29, count 0 2006.231.07:50:32.75#ibcon#*before return 0, iclass 29, count 0 2006.231.07:50:32.75#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:50:32.75#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:50:32.75#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.07:50:32.75#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.07:50:32.75$4f8m12a/ifd4f 2006.231.07:50:32.75$ifd4f/lo= 2006.231.07:50:32.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:50:32.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:50:32.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:50:32.75$ifd4f/patch= 2006.231.07:50:32.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:50:32.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:50:32.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:50:32.75$4f8m12a/"form=m,16.000,1:2 2006.231.07:50:32.75$4f8m12a/"tpicd 2006.231.07:50:32.75$4f8m12a/echo=off 2006.231.07:50:32.75$4f8m12a/xlog=off 2006.231.07:50:32.75:!2006.231.07:51:00 2006.231.07:50:40.14#trakl#Source acquired 2006.231.07:50:42.14#flagr#flagr/antenna,acquired 2006.231.07:51:00.00:preob 2006.231.07:51:01.14/onsource/TRACKING 2006.231.07:51:01.14:!2006.231.07:51:10 2006.231.07:51:10.00:data_valid=on 2006.231.07:51:10.00:midob 2006.231.07:51:10.13/onsource/TRACKING 2006.231.07:51:10.13/wx/30.57,1004.4,85 2006.231.07:51:10.26/cable/+6.3713E-03 2006.231.07:51:11.35/va/01,08,usb,yes,30,31 2006.231.07:51:11.35/va/02,07,usb,yes,29,31 2006.231.07:51:11.35/va/03,08,usb,yes,22,22 2006.231.07:51:11.35/va/04,07,usb,yes,31,33 2006.231.07:51:11.35/va/05,07,usb,yes,34,35 2006.231.07:51:11.35/va/06,06,usb,yes,33,33 2006.231.07:51:11.35/va/07,06,usb,yes,34,33 2006.231.07:51:11.35/va/08,06,usb,yes,36,35 2006.231.07:51:11.58/valo/01,532.99,yes,locked 2006.231.07:51:11.58/valo/02,572.99,yes,locked 2006.231.07:51:11.58/valo/03,672.99,yes,locked 2006.231.07:51:11.58/valo/04,832.99,yes,locked 2006.231.07:51:11.58/valo/05,652.99,yes,locked 2006.231.07:51:11.58/valo/06,772.99,yes,locked 2006.231.07:51:11.58/valo/07,832.99,yes,locked 2006.231.07:51:11.58/valo/08,852.99,yes,locked 2006.231.07:51:12.67/vb/01,04,usb,yes,30,29 2006.231.07:51:12.67/vb/02,04,usb,yes,32,33 2006.231.07:51:12.67/vb/03,04,usb,yes,28,32 2006.231.07:51:12.67/vb/04,04,usb,yes,29,29 2006.231.07:51:12.67/vb/05,03,usb,yes,35,39 2006.231.07:51:12.67/vb/06,04,usb,yes,29,32 2006.231.07:51:12.67/vb/07,04,usb,yes,31,31 2006.231.07:51:12.67/vb/08,04,usb,yes,28,32 2006.231.07:51:12.90/vblo/01,632.99,yes,locked 2006.231.07:51:12.90/vblo/02,640.99,yes,locked 2006.231.07:51:12.90/vblo/03,656.99,yes,locked 2006.231.07:51:12.90/vblo/04,712.99,yes,locked 2006.231.07:51:12.90/vblo/05,744.99,yes,locked 2006.231.07:51:12.90/vblo/06,752.99,yes,locked 2006.231.07:51:12.90/vblo/07,734.99,yes,locked 2006.231.07:51:12.90/vblo/08,744.99,yes,locked 2006.231.07:51:13.05/vabw/8 2006.231.07:51:13.20/vbbw/8 2006.231.07:51:13.29/xfe/off,on,12.5 2006.231.07:51:13.66/ifatt/23,28,28,28 2006.231.07:51:14.08/fmout-gps/S +4.44E-07 2006.231.07:51:14.12:!2006.231.07:52:10 2006.231.07:52:10.00:data_valid=off 2006.231.07:52:10.00:postob 2006.231.07:52:10.06/cable/+6.3698E-03 2006.231.07:52:10.06/wx/30.56,1004.4,85 2006.231.07:52:11.08/fmout-gps/S +4.45E-07 2006.231.07:52:11.08:scan_name=231-0753,k06231,60 2006.231.07:52:11.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.231.07:52:11.13#flagr#flagr/antenna,new-source 2006.231.07:52:12.13:checkk5 2006.231.07:52:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:52:12.87/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:52:13.24/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:52:13.61/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:52:13.98/chk_obsdata//k5ts1/T2310751??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:52:14.35/chk_obsdata//k5ts2/T2310751??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:52:14.72/chk_obsdata//k5ts3/T2310751??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:52:15.09/chk_obsdata//k5ts4/T2310751??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:52:15.78/k5log//k5ts1_log_newline 2006.231.07:52:16.47/k5log//k5ts2_log_newline 2006.231.07:52:17.15/k5log//k5ts3_log_newline 2006.231.07:52:17.84/k5log//k5ts4_log_newline 2006.231.07:52:17.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:52:17.86:4f8m12a=1 2006.231.07:52:17.86$4f8m12a/echo=on 2006.231.07:52:17.86$4f8m12a/pcalon 2006.231.07:52:17.86$pcalon/"no phase cal control is implemented here 2006.231.07:52:17.86$4f8m12a/"tpicd=stop 2006.231.07:52:17.86$4f8m12a/vc4f8 2006.231.07:52:17.86$vc4f8/valo=1,532.99 2006.231.07:52:17.87#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.07:52:17.87#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.07:52:17.87#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:17.87#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:52:17.87#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:52:17.87#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:52:17.87#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:52:17.87#ibcon#first serial, iclass 36, count 0 2006.231.07:52:17.87#ibcon#enter sib2, iclass 36, count 0 2006.231.07:52:17.87#ibcon#flushed, iclass 36, count 0 2006.231.07:52:17.87#ibcon#about to write, iclass 36, count 0 2006.231.07:52:17.87#ibcon#wrote, iclass 36, count 0 2006.231.07:52:17.87#ibcon#about to read 3, iclass 36, count 0 2006.231.07:52:17.90#ibcon#read 3, iclass 36, count 0 2006.231.07:52:17.90#ibcon#about to read 4, iclass 36, count 0 2006.231.07:52:17.90#ibcon#read 4, iclass 36, count 0 2006.231.07:52:17.90#ibcon#about to read 5, iclass 36, count 0 2006.231.07:52:17.90#ibcon#read 5, iclass 36, count 0 2006.231.07:52:17.90#ibcon#about to read 6, iclass 36, count 0 2006.231.07:52:17.90#ibcon#read 6, iclass 36, count 0 2006.231.07:52:17.90#ibcon#end of sib2, iclass 36, count 0 2006.231.07:52:17.90#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:52:17.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:52:17.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:52:17.90#ibcon#*before write, iclass 36, count 0 2006.231.07:52:17.90#ibcon#enter sib2, iclass 36, count 0 2006.231.07:52:17.90#ibcon#flushed, iclass 36, count 0 2006.231.07:52:17.90#ibcon#about to write, iclass 36, count 0 2006.231.07:52:17.90#ibcon#wrote, iclass 36, count 0 2006.231.07:52:17.90#ibcon#about to read 3, iclass 36, count 0 2006.231.07:52:17.95#ibcon#read 3, iclass 36, count 0 2006.231.07:52:17.95#ibcon#about to read 4, iclass 36, count 0 2006.231.07:52:17.95#ibcon#read 4, iclass 36, count 0 2006.231.07:52:17.95#ibcon#about to read 5, iclass 36, count 0 2006.231.07:52:17.95#ibcon#read 5, iclass 36, count 0 2006.231.07:52:17.95#ibcon#about to read 6, iclass 36, count 0 2006.231.07:52:17.95#ibcon#read 6, iclass 36, count 0 2006.231.07:52:17.95#ibcon#end of sib2, iclass 36, count 0 2006.231.07:52:17.95#ibcon#*after write, iclass 36, count 0 2006.231.07:52:17.95#ibcon#*before return 0, iclass 36, count 0 2006.231.07:52:17.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:52:17.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:52:17.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:52:17.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:52:17.95$vc4f8/va=1,8 2006.231.07:52:17.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.07:52:17.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.07:52:17.95#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:17.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:52:17.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:52:17.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:52:17.95#ibcon#enter wrdev, iclass 38, count 2 2006.231.07:52:17.95#ibcon#first serial, iclass 38, count 2 2006.231.07:52:17.95#ibcon#enter sib2, iclass 38, count 2 2006.231.07:52:17.95#ibcon#flushed, iclass 38, count 2 2006.231.07:52:17.95#ibcon#about to write, iclass 38, count 2 2006.231.07:52:17.95#ibcon#wrote, iclass 38, count 2 2006.231.07:52:17.95#ibcon#about to read 3, iclass 38, count 2 2006.231.07:52:17.97#ibcon#read 3, iclass 38, count 2 2006.231.07:52:17.97#ibcon#about to read 4, iclass 38, count 2 2006.231.07:52:17.97#ibcon#read 4, iclass 38, count 2 2006.231.07:52:17.97#ibcon#about to read 5, iclass 38, count 2 2006.231.07:52:17.97#ibcon#read 5, iclass 38, count 2 2006.231.07:52:17.97#ibcon#about to read 6, iclass 38, count 2 2006.231.07:52:17.97#ibcon#read 6, iclass 38, count 2 2006.231.07:52:17.97#ibcon#end of sib2, iclass 38, count 2 2006.231.07:52:17.97#ibcon#*mode == 0, iclass 38, count 2 2006.231.07:52:17.97#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.07:52:17.97#ibcon#[25=AT01-08\r\n] 2006.231.07:52:17.97#ibcon#*before write, iclass 38, count 2 2006.231.07:52:17.97#ibcon#enter sib2, iclass 38, count 2 2006.231.07:52:17.97#ibcon#flushed, iclass 38, count 2 2006.231.07:52:17.97#ibcon#about to write, iclass 38, count 2 2006.231.07:52:17.97#ibcon#wrote, iclass 38, count 2 2006.231.07:52:17.97#ibcon#about to read 3, iclass 38, count 2 2006.231.07:52:18.00#ibcon#read 3, iclass 38, count 2 2006.231.07:52:18.00#ibcon#about to read 4, iclass 38, count 2 2006.231.07:52:18.00#ibcon#read 4, iclass 38, count 2 2006.231.07:52:18.00#ibcon#about to read 5, iclass 38, count 2 2006.231.07:52:18.00#ibcon#read 5, iclass 38, count 2 2006.231.07:52:18.00#ibcon#about to read 6, iclass 38, count 2 2006.231.07:52:18.00#ibcon#read 6, iclass 38, count 2 2006.231.07:52:18.00#ibcon#end of sib2, iclass 38, count 2 2006.231.07:52:18.00#ibcon#*after write, iclass 38, count 2 2006.231.07:52:18.00#ibcon#*before return 0, iclass 38, count 2 2006.231.07:52:18.00#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:52:18.00#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:52:18.00#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.07:52:18.00#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:18.00#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:52:18.12#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:52:18.12#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:52:18.12#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:52:18.12#ibcon#first serial, iclass 38, count 0 2006.231.07:52:18.12#ibcon#enter sib2, iclass 38, count 0 2006.231.07:52:18.12#ibcon#flushed, iclass 38, count 0 2006.231.07:52:18.12#ibcon#about to write, iclass 38, count 0 2006.231.07:52:18.12#ibcon#wrote, iclass 38, count 0 2006.231.07:52:18.12#ibcon#about to read 3, iclass 38, count 0 2006.231.07:52:18.14#ibcon#read 3, iclass 38, count 0 2006.231.07:52:18.14#ibcon#about to read 4, iclass 38, count 0 2006.231.07:52:18.14#ibcon#read 4, iclass 38, count 0 2006.231.07:52:18.14#ibcon#about to read 5, iclass 38, count 0 2006.231.07:52:18.14#ibcon#read 5, iclass 38, count 0 2006.231.07:52:18.14#ibcon#about to read 6, iclass 38, count 0 2006.231.07:52:18.14#ibcon#read 6, iclass 38, count 0 2006.231.07:52:18.14#ibcon#end of sib2, iclass 38, count 0 2006.231.07:52:18.14#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:52:18.14#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:52:18.14#ibcon#[25=USB\r\n] 2006.231.07:52:18.14#ibcon#*before write, iclass 38, count 0 2006.231.07:52:18.14#ibcon#enter sib2, iclass 38, count 0 2006.231.07:52:18.14#ibcon#flushed, iclass 38, count 0 2006.231.07:52:18.14#ibcon#about to write, iclass 38, count 0 2006.231.07:52:18.14#ibcon#wrote, iclass 38, count 0 2006.231.07:52:18.14#ibcon#about to read 3, iclass 38, count 0 2006.231.07:52:18.17#ibcon#read 3, iclass 38, count 0 2006.231.07:52:18.17#ibcon#about to read 4, iclass 38, count 0 2006.231.07:52:18.17#ibcon#read 4, iclass 38, count 0 2006.231.07:52:18.17#ibcon#about to read 5, iclass 38, count 0 2006.231.07:52:18.17#ibcon#read 5, iclass 38, count 0 2006.231.07:52:18.17#ibcon#about to read 6, iclass 38, count 0 2006.231.07:52:18.17#ibcon#read 6, iclass 38, count 0 2006.231.07:52:18.17#ibcon#end of sib2, iclass 38, count 0 2006.231.07:52:18.17#ibcon#*after write, iclass 38, count 0 2006.231.07:52:18.17#ibcon#*before return 0, iclass 38, count 0 2006.231.07:52:18.17#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:52:18.17#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:52:18.17#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:52:18.17#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:52:18.17$vc4f8/valo=2,572.99 2006.231.07:52:18.17#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.07:52:18.17#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.07:52:18.17#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:18.17#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:52:18.17#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:52:18.17#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:52:18.17#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:52:18.17#ibcon#first serial, iclass 40, count 0 2006.231.07:52:18.17#ibcon#enter sib2, iclass 40, count 0 2006.231.07:52:18.17#ibcon#flushed, iclass 40, count 0 2006.231.07:52:18.17#ibcon#about to write, iclass 40, count 0 2006.231.07:52:18.17#ibcon#wrote, iclass 40, count 0 2006.231.07:52:18.17#ibcon#about to read 3, iclass 40, count 0 2006.231.07:52:18.19#ibcon#read 3, iclass 40, count 0 2006.231.07:52:18.19#ibcon#about to read 4, iclass 40, count 0 2006.231.07:52:18.19#ibcon#read 4, iclass 40, count 0 2006.231.07:52:18.19#ibcon#about to read 5, iclass 40, count 0 2006.231.07:52:18.19#ibcon#read 5, iclass 40, count 0 2006.231.07:52:18.19#ibcon#about to read 6, iclass 40, count 0 2006.231.07:52:18.19#ibcon#read 6, iclass 40, count 0 2006.231.07:52:18.19#ibcon#end of sib2, iclass 40, count 0 2006.231.07:52:18.19#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:52:18.19#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:52:18.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:52:18.19#ibcon#*before write, iclass 40, count 0 2006.231.07:52:18.19#ibcon#enter sib2, iclass 40, count 0 2006.231.07:52:18.19#ibcon#flushed, iclass 40, count 0 2006.231.07:52:18.19#ibcon#about to write, iclass 40, count 0 2006.231.07:52:18.19#ibcon#wrote, iclass 40, count 0 2006.231.07:52:18.19#ibcon#about to read 3, iclass 40, count 0 2006.231.07:52:18.23#ibcon#read 3, iclass 40, count 0 2006.231.07:52:18.23#ibcon#about to read 4, iclass 40, count 0 2006.231.07:52:18.23#ibcon#read 4, iclass 40, count 0 2006.231.07:52:18.23#ibcon#about to read 5, iclass 40, count 0 2006.231.07:52:18.23#ibcon#read 5, iclass 40, count 0 2006.231.07:52:18.23#ibcon#about to read 6, iclass 40, count 0 2006.231.07:52:18.23#ibcon#read 6, iclass 40, count 0 2006.231.07:52:18.23#ibcon#end of sib2, iclass 40, count 0 2006.231.07:52:18.23#ibcon#*after write, iclass 40, count 0 2006.231.07:52:18.23#ibcon#*before return 0, iclass 40, count 0 2006.231.07:52:18.23#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:52:18.23#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:52:18.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:52:18.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:52:18.23$vc4f8/va=2,7 2006.231.07:52:18.23#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.231.07:52:18.23#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.231.07:52:18.23#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:18.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:52:18.29#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:52:18.29#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:52:18.29#ibcon#enter wrdev, iclass 4, count 2 2006.231.07:52:18.29#ibcon#first serial, iclass 4, count 2 2006.231.07:52:18.29#ibcon#enter sib2, iclass 4, count 2 2006.231.07:52:18.29#ibcon#flushed, iclass 4, count 2 2006.231.07:52:18.29#ibcon#about to write, iclass 4, count 2 2006.231.07:52:18.29#ibcon#wrote, iclass 4, count 2 2006.231.07:52:18.29#ibcon#about to read 3, iclass 4, count 2 2006.231.07:52:18.31#ibcon#read 3, iclass 4, count 2 2006.231.07:52:18.31#ibcon#about to read 4, iclass 4, count 2 2006.231.07:52:18.31#ibcon#read 4, iclass 4, count 2 2006.231.07:52:18.31#ibcon#about to read 5, iclass 4, count 2 2006.231.07:52:18.31#ibcon#read 5, iclass 4, count 2 2006.231.07:52:18.31#ibcon#about to read 6, iclass 4, count 2 2006.231.07:52:18.31#ibcon#read 6, iclass 4, count 2 2006.231.07:52:18.31#ibcon#end of sib2, iclass 4, count 2 2006.231.07:52:18.31#ibcon#*mode == 0, iclass 4, count 2 2006.231.07:52:18.31#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.231.07:52:18.31#ibcon#[25=AT02-07\r\n] 2006.231.07:52:18.31#ibcon#*before write, iclass 4, count 2 2006.231.07:52:18.31#ibcon#enter sib2, iclass 4, count 2 2006.231.07:52:18.31#ibcon#flushed, iclass 4, count 2 2006.231.07:52:18.31#ibcon#about to write, iclass 4, count 2 2006.231.07:52:18.31#ibcon#wrote, iclass 4, count 2 2006.231.07:52:18.31#ibcon#about to read 3, iclass 4, count 2 2006.231.07:52:18.34#ibcon#read 3, iclass 4, count 2 2006.231.07:52:18.34#ibcon#about to read 4, iclass 4, count 2 2006.231.07:52:18.34#ibcon#read 4, iclass 4, count 2 2006.231.07:52:18.34#ibcon#about to read 5, iclass 4, count 2 2006.231.07:52:18.34#ibcon#read 5, iclass 4, count 2 2006.231.07:52:18.34#ibcon#about to read 6, iclass 4, count 2 2006.231.07:52:18.34#ibcon#read 6, iclass 4, count 2 2006.231.07:52:18.34#ibcon#end of sib2, iclass 4, count 2 2006.231.07:52:18.34#ibcon#*after write, iclass 4, count 2 2006.231.07:52:18.34#ibcon#*before return 0, iclass 4, count 2 2006.231.07:52:18.34#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:52:18.34#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:52:18.34#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.231.07:52:18.34#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:18.34#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:52:18.46#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:52:18.46#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:52:18.46#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:52:18.46#ibcon#first serial, iclass 4, count 0 2006.231.07:52:18.46#ibcon#enter sib2, iclass 4, count 0 2006.231.07:52:18.46#ibcon#flushed, iclass 4, count 0 2006.231.07:52:18.46#ibcon#about to write, iclass 4, count 0 2006.231.07:52:18.46#ibcon#wrote, iclass 4, count 0 2006.231.07:52:18.46#ibcon#about to read 3, iclass 4, count 0 2006.231.07:52:18.48#ibcon#read 3, iclass 4, count 0 2006.231.07:52:18.48#ibcon#about to read 4, iclass 4, count 0 2006.231.07:52:18.48#ibcon#read 4, iclass 4, count 0 2006.231.07:52:18.48#ibcon#about to read 5, iclass 4, count 0 2006.231.07:52:18.48#ibcon#read 5, iclass 4, count 0 2006.231.07:52:18.48#ibcon#about to read 6, iclass 4, count 0 2006.231.07:52:18.48#ibcon#read 6, iclass 4, count 0 2006.231.07:52:18.48#ibcon#end of sib2, iclass 4, count 0 2006.231.07:52:18.48#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:52:18.48#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:52:18.48#ibcon#[25=USB\r\n] 2006.231.07:52:18.48#ibcon#*before write, iclass 4, count 0 2006.231.07:52:18.48#ibcon#enter sib2, iclass 4, count 0 2006.231.07:52:18.48#ibcon#flushed, iclass 4, count 0 2006.231.07:52:18.48#ibcon#about to write, iclass 4, count 0 2006.231.07:52:18.48#ibcon#wrote, iclass 4, count 0 2006.231.07:52:18.48#ibcon#about to read 3, iclass 4, count 0 2006.231.07:52:18.51#ibcon#read 3, iclass 4, count 0 2006.231.07:52:18.51#ibcon#about to read 4, iclass 4, count 0 2006.231.07:52:18.51#ibcon#read 4, iclass 4, count 0 2006.231.07:52:18.51#ibcon#about to read 5, iclass 4, count 0 2006.231.07:52:18.51#ibcon#read 5, iclass 4, count 0 2006.231.07:52:18.51#ibcon#about to read 6, iclass 4, count 0 2006.231.07:52:18.51#ibcon#read 6, iclass 4, count 0 2006.231.07:52:18.51#ibcon#end of sib2, iclass 4, count 0 2006.231.07:52:18.51#ibcon#*after write, iclass 4, count 0 2006.231.07:52:18.51#ibcon#*before return 0, iclass 4, count 0 2006.231.07:52:18.51#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:52:18.51#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:52:18.51#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:52:18.51#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:52:18.51$vc4f8/valo=3,672.99 2006.231.07:52:18.51#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.231.07:52:18.51#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.231.07:52:18.51#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:18.51#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:52:18.51#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:52:18.51#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:52:18.51#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:52:18.51#ibcon#first serial, iclass 6, count 0 2006.231.07:52:18.51#ibcon#enter sib2, iclass 6, count 0 2006.231.07:52:18.51#ibcon#flushed, iclass 6, count 0 2006.231.07:52:18.51#ibcon#about to write, iclass 6, count 0 2006.231.07:52:18.51#ibcon#wrote, iclass 6, count 0 2006.231.07:52:18.51#ibcon#about to read 3, iclass 6, count 0 2006.231.07:52:18.53#ibcon#read 3, iclass 6, count 0 2006.231.07:52:18.53#ibcon#about to read 4, iclass 6, count 0 2006.231.07:52:18.53#ibcon#read 4, iclass 6, count 0 2006.231.07:52:18.53#ibcon#about to read 5, iclass 6, count 0 2006.231.07:52:18.53#ibcon#read 5, iclass 6, count 0 2006.231.07:52:18.53#ibcon#about to read 6, iclass 6, count 0 2006.231.07:52:18.53#ibcon#read 6, iclass 6, count 0 2006.231.07:52:18.53#ibcon#end of sib2, iclass 6, count 0 2006.231.07:52:18.53#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:52:18.53#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:52:18.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:52:18.53#ibcon#*before write, iclass 6, count 0 2006.231.07:52:18.53#ibcon#enter sib2, iclass 6, count 0 2006.231.07:52:18.53#ibcon#flushed, iclass 6, count 0 2006.231.07:52:18.53#ibcon#about to write, iclass 6, count 0 2006.231.07:52:18.53#ibcon#wrote, iclass 6, count 0 2006.231.07:52:18.53#ibcon#about to read 3, iclass 6, count 0 2006.231.07:52:18.57#ibcon#read 3, iclass 6, count 0 2006.231.07:52:18.57#ibcon#about to read 4, iclass 6, count 0 2006.231.07:52:18.57#ibcon#read 4, iclass 6, count 0 2006.231.07:52:18.57#ibcon#about to read 5, iclass 6, count 0 2006.231.07:52:18.57#ibcon#read 5, iclass 6, count 0 2006.231.07:52:18.57#ibcon#about to read 6, iclass 6, count 0 2006.231.07:52:18.57#ibcon#read 6, iclass 6, count 0 2006.231.07:52:18.57#ibcon#end of sib2, iclass 6, count 0 2006.231.07:52:18.57#ibcon#*after write, iclass 6, count 0 2006.231.07:52:18.57#ibcon#*before return 0, iclass 6, count 0 2006.231.07:52:18.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:52:18.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.231.07:52:18.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:52:18.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:52:18.57$vc4f8/va=3,8 2006.231.07:52:18.57#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.231.07:52:18.57#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.231.07:52:18.57#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:18.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:52:18.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:52:18.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:52:18.63#ibcon#enter wrdev, iclass 10, count 2 2006.231.07:52:18.63#ibcon#first serial, iclass 10, count 2 2006.231.07:52:18.63#ibcon#enter sib2, iclass 10, count 2 2006.231.07:52:18.63#ibcon#flushed, iclass 10, count 2 2006.231.07:52:18.63#ibcon#about to write, iclass 10, count 2 2006.231.07:52:18.63#ibcon#wrote, iclass 10, count 2 2006.231.07:52:18.63#ibcon#about to read 3, iclass 10, count 2 2006.231.07:52:18.65#ibcon#read 3, iclass 10, count 2 2006.231.07:52:18.65#ibcon#about to read 4, iclass 10, count 2 2006.231.07:52:18.65#ibcon#read 4, iclass 10, count 2 2006.231.07:52:18.65#ibcon#about to read 5, iclass 10, count 2 2006.231.07:52:18.65#ibcon#read 5, iclass 10, count 2 2006.231.07:52:18.65#ibcon#about to read 6, iclass 10, count 2 2006.231.07:52:18.65#ibcon#read 6, iclass 10, count 2 2006.231.07:52:18.65#ibcon#end of sib2, iclass 10, count 2 2006.231.07:52:18.65#ibcon#*mode == 0, iclass 10, count 2 2006.231.07:52:18.65#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.231.07:52:18.65#ibcon#[25=AT03-08\r\n] 2006.231.07:52:18.65#ibcon#*before write, iclass 10, count 2 2006.231.07:52:18.65#ibcon#enter sib2, iclass 10, count 2 2006.231.07:52:18.65#ibcon#flushed, iclass 10, count 2 2006.231.07:52:18.65#ibcon#about to write, iclass 10, count 2 2006.231.07:52:18.65#ibcon#wrote, iclass 10, count 2 2006.231.07:52:18.65#ibcon#about to read 3, iclass 10, count 2 2006.231.07:52:18.68#ibcon#read 3, iclass 10, count 2 2006.231.07:52:18.68#ibcon#about to read 4, iclass 10, count 2 2006.231.07:52:18.68#ibcon#read 4, iclass 10, count 2 2006.231.07:52:18.68#ibcon#about to read 5, iclass 10, count 2 2006.231.07:52:18.68#ibcon#read 5, iclass 10, count 2 2006.231.07:52:18.68#ibcon#about to read 6, iclass 10, count 2 2006.231.07:52:18.68#ibcon#read 6, iclass 10, count 2 2006.231.07:52:18.68#ibcon#end of sib2, iclass 10, count 2 2006.231.07:52:18.68#ibcon#*after write, iclass 10, count 2 2006.231.07:52:18.68#ibcon#*before return 0, iclass 10, count 2 2006.231.07:52:18.68#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:52:18.68#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.231.07:52:18.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.231.07:52:18.68#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:18.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:52:18.80#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:52:18.80#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:52:18.80#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:52:18.80#ibcon#first serial, iclass 10, count 0 2006.231.07:52:18.80#ibcon#enter sib2, iclass 10, count 0 2006.231.07:52:18.80#ibcon#flushed, iclass 10, count 0 2006.231.07:52:18.80#ibcon#about to write, iclass 10, count 0 2006.231.07:52:18.80#ibcon#wrote, iclass 10, count 0 2006.231.07:52:18.80#ibcon#about to read 3, iclass 10, count 0 2006.231.07:52:18.82#ibcon#read 3, iclass 10, count 0 2006.231.07:52:18.82#ibcon#about to read 4, iclass 10, count 0 2006.231.07:52:18.82#ibcon#read 4, iclass 10, count 0 2006.231.07:52:18.82#ibcon#about to read 5, iclass 10, count 0 2006.231.07:52:18.82#ibcon#read 5, iclass 10, count 0 2006.231.07:52:18.82#ibcon#about to read 6, iclass 10, count 0 2006.231.07:52:18.82#ibcon#read 6, iclass 10, count 0 2006.231.07:52:18.82#ibcon#end of sib2, iclass 10, count 0 2006.231.07:52:18.82#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:52:18.82#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:52:18.82#ibcon#[25=USB\r\n] 2006.231.07:52:18.82#ibcon#*before write, iclass 10, count 0 2006.231.07:52:18.82#ibcon#enter sib2, iclass 10, count 0 2006.231.07:52:18.82#ibcon#flushed, iclass 10, count 0 2006.231.07:52:18.82#ibcon#about to write, iclass 10, count 0 2006.231.07:52:18.82#ibcon#wrote, iclass 10, count 0 2006.231.07:52:18.82#ibcon#about to read 3, iclass 10, count 0 2006.231.07:52:18.85#ibcon#read 3, iclass 10, count 0 2006.231.07:52:18.85#ibcon#about to read 4, iclass 10, count 0 2006.231.07:52:18.85#ibcon#read 4, iclass 10, count 0 2006.231.07:52:18.85#ibcon#about to read 5, iclass 10, count 0 2006.231.07:52:18.85#ibcon#read 5, iclass 10, count 0 2006.231.07:52:18.85#ibcon#about to read 6, iclass 10, count 0 2006.231.07:52:18.85#ibcon#read 6, iclass 10, count 0 2006.231.07:52:18.85#ibcon#end of sib2, iclass 10, count 0 2006.231.07:52:18.85#ibcon#*after write, iclass 10, count 0 2006.231.07:52:18.85#ibcon#*before return 0, iclass 10, count 0 2006.231.07:52:18.85#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:52:18.85#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.231.07:52:18.85#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:52:18.85#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:52:18.85$vc4f8/valo=4,832.99 2006.231.07:52:18.85#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.07:52:18.85#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.07:52:18.85#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:18.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:52:18.85#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:52:18.85#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:52:18.85#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:52:18.85#ibcon#first serial, iclass 12, count 0 2006.231.07:52:18.85#ibcon#enter sib2, iclass 12, count 0 2006.231.07:52:18.85#ibcon#flushed, iclass 12, count 0 2006.231.07:52:18.85#ibcon#about to write, iclass 12, count 0 2006.231.07:52:18.85#ibcon#wrote, iclass 12, count 0 2006.231.07:52:18.85#ibcon#about to read 3, iclass 12, count 0 2006.231.07:52:18.87#ibcon#read 3, iclass 12, count 0 2006.231.07:52:18.87#ibcon#about to read 4, iclass 12, count 0 2006.231.07:52:18.87#ibcon#read 4, iclass 12, count 0 2006.231.07:52:18.87#ibcon#about to read 5, iclass 12, count 0 2006.231.07:52:18.87#ibcon#read 5, iclass 12, count 0 2006.231.07:52:18.87#ibcon#about to read 6, iclass 12, count 0 2006.231.07:52:18.87#ibcon#read 6, iclass 12, count 0 2006.231.07:52:18.87#ibcon#end of sib2, iclass 12, count 0 2006.231.07:52:18.87#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:52:18.87#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:52:18.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:52:18.87#ibcon#*before write, iclass 12, count 0 2006.231.07:52:18.87#ibcon#enter sib2, iclass 12, count 0 2006.231.07:52:18.87#ibcon#flushed, iclass 12, count 0 2006.231.07:52:18.87#ibcon#about to write, iclass 12, count 0 2006.231.07:52:18.87#ibcon#wrote, iclass 12, count 0 2006.231.07:52:18.87#ibcon#about to read 3, iclass 12, count 0 2006.231.07:52:18.91#ibcon#read 3, iclass 12, count 0 2006.231.07:52:18.91#ibcon#about to read 4, iclass 12, count 0 2006.231.07:52:18.91#ibcon#read 4, iclass 12, count 0 2006.231.07:52:18.91#ibcon#about to read 5, iclass 12, count 0 2006.231.07:52:18.91#ibcon#read 5, iclass 12, count 0 2006.231.07:52:18.91#ibcon#about to read 6, iclass 12, count 0 2006.231.07:52:18.91#ibcon#read 6, iclass 12, count 0 2006.231.07:52:18.91#ibcon#end of sib2, iclass 12, count 0 2006.231.07:52:18.91#ibcon#*after write, iclass 12, count 0 2006.231.07:52:18.91#ibcon#*before return 0, iclass 12, count 0 2006.231.07:52:18.91#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:52:18.91#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:52:18.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:52:18.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:52:18.91$vc4f8/va=4,7 2006.231.07:52:18.91#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.07:52:18.91#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.07:52:18.91#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:18.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:52:18.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:52:18.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:52:18.97#ibcon#enter wrdev, iclass 14, count 2 2006.231.07:52:18.97#ibcon#first serial, iclass 14, count 2 2006.231.07:52:18.97#ibcon#enter sib2, iclass 14, count 2 2006.231.07:52:18.97#ibcon#flushed, iclass 14, count 2 2006.231.07:52:18.97#ibcon#about to write, iclass 14, count 2 2006.231.07:52:18.97#ibcon#wrote, iclass 14, count 2 2006.231.07:52:18.97#ibcon#about to read 3, iclass 14, count 2 2006.231.07:52:18.99#ibcon#read 3, iclass 14, count 2 2006.231.07:52:18.99#ibcon#about to read 4, iclass 14, count 2 2006.231.07:52:18.99#ibcon#read 4, iclass 14, count 2 2006.231.07:52:18.99#ibcon#about to read 5, iclass 14, count 2 2006.231.07:52:18.99#ibcon#read 5, iclass 14, count 2 2006.231.07:52:18.99#ibcon#about to read 6, iclass 14, count 2 2006.231.07:52:18.99#ibcon#read 6, iclass 14, count 2 2006.231.07:52:18.99#ibcon#end of sib2, iclass 14, count 2 2006.231.07:52:18.99#ibcon#*mode == 0, iclass 14, count 2 2006.231.07:52:18.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.07:52:18.99#ibcon#[25=AT04-07\r\n] 2006.231.07:52:18.99#ibcon#*before write, iclass 14, count 2 2006.231.07:52:18.99#ibcon#enter sib2, iclass 14, count 2 2006.231.07:52:18.99#ibcon#flushed, iclass 14, count 2 2006.231.07:52:18.99#ibcon#about to write, iclass 14, count 2 2006.231.07:52:18.99#ibcon#wrote, iclass 14, count 2 2006.231.07:52:18.99#ibcon#about to read 3, iclass 14, count 2 2006.231.07:52:19.02#ibcon#read 3, iclass 14, count 2 2006.231.07:52:19.02#ibcon#about to read 4, iclass 14, count 2 2006.231.07:52:19.02#ibcon#read 4, iclass 14, count 2 2006.231.07:52:19.02#ibcon#about to read 5, iclass 14, count 2 2006.231.07:52:19.02#ibcon#read 5, iclass 14, count 2 2006.231.07:52:19.02#ibcon#about to read 6, iclass 14, count 2 2006.231.07:52:19.02#ibcon#read 6, iclass 14, count 2 2006.231.07:52:19.02#ibcon#end of sib2, iclass 14, count 2 2006.231.07:52:19.02#ibcon#*after write, iclass 14, count 2 2006.231.07:52:19.02#ibcon#*before return 0, iclass 14, count 2 2006.231.07:52:19.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:52:19.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:52:19.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.07:52:19.02#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:19.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:52:19.14#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:52:19.14#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:52:19.14#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:52:19.14#ibcon#first serial, iclass 14, count 0 2006.231.07:52:19.14#ibcon#enter sib2, iclass 14, count 0 2006.231.07:52:19.14#ibcon#flushed, iclass 14, count 0 2006.231.07:52:19.14#ibcon#about to write, iclass 14, count 0 2006.231.07:52:19.14#ibcon#wrote, iclass 14, count 0 2006.231.07:52:19.14#ibcon#about to read 3, iclass 14, count 0 2006.231.07:52:19.16#ibcon#read 3, iclass 14, count 0 2006.231.07:52:19.16#ibcon#about to read 4, iclass 14, count 0 2006.231.07:52:19.16#ibcon#read 4, iclass 14, count 0 2006.231.07:52:19.16#ibcon#about to read 5, iclass 14, count 0 2006.231.07:52:19.16#ibcon#read 5, iclass 14, count 0 2006.231.07:52:19.16#ibcon#about to read 6, iclass 14, count 0 2006.231.07:52:19.16#ibcon#read 6, iclass 14, count 0 2006.231.07:52:19.16#ibcon#end of sib2, iclass 14, count 0 2006.231.07:52:19.16#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:52:19.16#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:52:19.16#ibcon#[25=USB\r\n] 2006.231.07:52:19.16#ibcon#*before write, iclass 14, count 0 2006.231.07:52:19.16#ibcon#enter sib2, iclass 14, count 0 2006.231.07:52:19.16#ibcon#flushed, iclass 14, count 0 2006.231.07:52:19.16#ibcon#about to write, iclass 14, count 0 2006.231.07:52:19.16#ibcon#wrote, iclass 14, count 0 2006.231.07:52:19.16#ibcon#about to read 3, iclass 14, count 0 2006.231.07:52:19.19#ibcon#read 3, iclass 14, count 0 2006.231.07:52:19.19#ibcon#about to read 4, iclass 14, count 0 2006.231.07:52:19.19#ibcon#read 4, iclass 14, count 0 2006.231.07:52:19.19#ibcon#about to read 5, iclass 14, count 0 2006.231.07:52:19.19#ibcon#read 5, iclass 14, count 0 2006.231.07:52:19.19#ibcon#about to read 6, iclass 14, count 0 2006.231.07:52:19.19#ibcon#read 6, iclass 14, count 0 2006.231.07:52:19.19#ibcon#end of sib2, iclass 14, count 0 2006.231.07:52:19.19#ibcon#*after write, iclass 14, count 0 2006.231.07:52:19.19#ibcon#*before return 0, iclass 14, count 0 2006.231.07:52:19.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:52:19.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:52:19.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:52:19.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:52:19.19$vc4f8/valo=5,652.99 2006.231.07:52:19.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.07:52:19.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.07:52:19.19#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:19.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:52:19.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:52:19.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:52:19.19#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:52:19.19#ibcon#first serial, iclass 16, count 0 2006.231.07:52:19.19#ibcon#enter sib2, iclass 16, count 0 2006.231.07:52:19.19#ibcon#flushed, iclass 16, count 0 2006.231.07:52:19.19#ibcon#about to write, iclass 16, count 0 2006.231.07:52:19.19#ibcon#wrote, iclass 16, count 0 2006.231.07:52:19.19#ibcon#about to read 3, iclass 16, count 0 2006.231.07:52:19.21#ibcon#read 3, iclass 16, count 0 2006.231.07:52:19.21#ibcon#about to read 4, iclass 16, count 0 2006.231.07:52:19.21#ibcon#read 4, iclass 16, count 0 2006.231.07:52:19.21#ibcon#about to read 5, iclass 16, count 0 2006.231.07:52:19.21#ibcon#read 5, iclass 16, count 0 2006.231.07:52:19.21#ibcon#about to read 6, iclass 16, count 0 2006.231.07:52:19.21#ibcon#read 6, iclass 16, count 0 2006.231.07:52:19.21#ibcon#end of sib2, iclass 16, count 0 2006.231.07:52:19.21#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:52:19.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:52:19.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:52:19.21#ibcon#*before write, iclass 16, count 0 2006.231.07:52:19.21#ibcon#enter sib2, iclass 16, count 0 2006.231.07:52:19.21#ibcon#flushed, iclass 16, count 0 2006.231.07:52:19.21#ibcon#about to write, iclass 16, count 0 2006.231.07:52:19.21#ibcon#wrote, iclass 16, count 0 2006.231.07:52:19.21#ibcon#about to read 3, iclass 16, count 0 2006.231.07:52:19.25#ibcon#read 3, iclass 16, count 0 2006.231.07:52:19.25#ibcon#about to read 4, iclass 16, count 0 2006.231.07:52:19.25#ibcon#read 4, iclass 16, count 0 2006.231.07:52:19.25#ibcon#about to read 5, iclass 16, count 0 2006.231.07:52:19.25#ibcon#read 5, iclass 16, count 0 2006.231.07:52:19.25#ibcon#about to read 6, iclass 16, count 0 2006.231.07:52:19.25#ibcon#read 6, iclass 16, count 0 2006.231.07:52:19.25#ibcon#end of sib2, iclass 16, count 0 2006.231.07:52:19.25#ibcon#*after write, iclass 16, count 0 2006.231.07:52:19.25#ibcon#*before return 0, iclass 16, count 0 2006.231.07:52:19.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:52:19.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:52:19.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:52:19.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:52:19.25$vc4f8/va=5,7 2006.231.07:52:19.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.231.07:52:19.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.231.07:52:19.25#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:19.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:52:19.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:52:19.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:52:19.31#ibcon#enter wrdev, iclass 18, count 2 2006.231.07:52:19.31#ibcon#first serial, iclass 18, count 2 2006.231.07:52:19.31#ibcon#enter sib2, iclass 18, count 2 2006.231.07:52:19.31#ibcon#flushed, iclass 18, count 2 2006.231.07:52:19.31#ibcon#about to write, iclass 18, count 2 2006.231.07:52:19.31#ibcon#wrote, iclass 18, count 2 2006.231.07:52:19.31#ibcon#about to read 3, iclass 18, count 2 2006.231.07:52:19.33#ibcon#read 3, iclass 18, count 2 2006.231.07:52:19.33#ibcon#about to read 4, iclass 18, count 2 2006.231.07:52:19.33#ibcon#read 4, iclass 18, count 2 2006.231.07:52:19.33#ibcon#about to read 5, iclass 18, count 2 2006.231.07:52:19.33#ibcon#read 5, iclass 18, count 2 2006.231.07:52:19.33#ibcon#about to read 6, iclass 18, count 2 2006.231.07:52:19.33#ibcon#read 6, iclass 18, count 2 2006.231.07:52:19.33#ibcon#end of sib2, iclass 18, count 2 2006.231.07:52:19.33#ibcon#*mode == 0, iclass 18, count 2 2006.231.07:52:19.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.231.07:52:19.33#ibcon#[25=AT05-07\r\n] 2006.231.07:52:19.33#ibcon#*before write, iclass 18, count 2 2006.231.07:52:19.33#ibcon#enter sib2, iclass 18, count 2 2006.231.07:52:19.33#ibcon#flushed, iclass 18, count 2 2006.231.07:52:19.33#ibcon#about to write, iclass 18, count 2 2006.231.07:52:19.33#ibcon#wrote, iclass 18, count 2 2006.231.07:52:19.33#ibcon#about to read 3, iclass 18, count 2 2006.231.07:52:19.36#ibcon#read 3, iclass 18, count 2 2006.231.07:52:19.36#ibcon#about to read 4, iclass 18, count 2 2006.231.07:52:19.36#ibcon#read 4, iclass 18, count 2 2006.231.07:52:19.36#ibcon#about to read 5, iclass 18, count 2 2006.231.07:52:19.36#ibcon#read 5, iclass 18, count 2 2006.231.07:52:19.36#ibcon#about to read 6, iclass 18, count 2 2006.231.07:52:19.36#ibcon#read 6, iclass 18, count 2 2006.231.07:52:19.36#ibcon#end of sib2, iclass 18, count 2 2006.231.07:52:19.36#ibcon#*after write, iclass 18, count 2 2006.231.07:52:19.36#ibcon#*before return 0, iclass 18, count 2 2006.231.07:52:19.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:52:19.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:52:19.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.231.07:52:19.36#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:19.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:52:19.48#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:52:19.48#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:52:19.48#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:52:19.48#ibcon#first serial, iclass 18, count 0 2006.231.07:52:19.48#ibcon#enter sib2, iclass 18, count 0 2006.231.07:52:19.48#ibcon#flushed, iclass 18, count 0 2006.231.07:52:19.48#ibcon#about to write, iclass 18, count 0 2006.231.07:52:19.48#ibcon#wrote, iclass 18, count 0 2006.231.07:52:19.48#ibcon#about to read 3, iclass 18, count 0 2006.231.07:52:19.50#ibcon#read 3, iclass 18, count 0 2006.231.07:52:19.50#ibcon#about to read 4, iclass 18, count 0 2006.231.07:52:19.50#ibcon#read 4, iclass 18, count 0 2006.231.07:52:19.50#ibcon#about to read 5, iclass 18, count 0 2006.231.07:52:19.50#ibcon#read 5, iclass 18, count 0 2006.231.07:52:19.50#ibcon#about to read 6, iclass 18, count 0 2006.231.07:52:19.50#ibcon#read 6, iclass 18, count 0 2006.231.07:52:19.50#ibcon#end of sib2, iclass 18, count 0 2006.231.07:52:19.50#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:52:19.50#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:52:19.50#ibcon#[25=USB\r\n] 2006.231.07:52:19.50#ibcon#*before write, iclass 18, count 0 2006.231.07:52:19.50#ibcon#enter sib2, iclass 18, count 0 2006.231.07:52:19.50#ibcon#flushed, iclass 18, count 0 2006.231.07:52:19.50#ibcon#about to write, iclass 18, count 0 2006.231.07:52:19.50#ibcon#wrote, iclass 18, count 0 2006.231.07:52:19.50#ibcon#about to read 3, iclass 18, count 0 2006.231.07:52:19.53#ibcon#read 3, iclass 18, count 0 2006.231.07:52:19.53#ibcon#about to read 4, iclass 18, count 0 2006.231.07:52:19.53#ibcon#read 4, iclass 18, count 0 2006.231.07:52:19.53#ibcon#about to read 5, iclass 18, count 0 2006.231.07:52:19.53#ibcon#read 5, iclass 18, count 0 2006.231.07:52:19.53#ibcon#about to read 6, iclass 18, count 0 2006.231.07:52:19.53#ibcon#read 6, iclass 18, count 0 2006.231.07:52:19.53#ibcon#end of sib2, iclass 18, count 0 2006.231.07:52:19.53#ibcon#*after write, iclass 18, count 0 2006.231.07:52:19.53#ibcon#*before return 0, iclass 18, count 0 2006.231.07:52:19.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:52:19.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:52:19.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:52:19.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:52:19.53$vc4f8/valo=6,772.99 2006.231.07:52:19.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.231.07:52:19.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.231.07:52:19.53#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:19.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:52:19.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:52:19.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:52:19.53#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:52:19.53#ibcon#first serial, iclass 20, count 0 2006.231.07:52:19.53#ibcon#enter sib2, iclass 20, count 0 2006.231.07:52:19.53#ibcon#flushed, iclass 20, count 0 2006.231.07:52:19.53#ibcon#about to write, iclass 20, count 0 2006.231.07:52:19.53#ibcon#wrote, iclass 20, count 0 2006.231.07:52:19.53#ibcon#about to read 3, iclass 20, count 0 2006.231.07:52:19.55#ibcon#read 3, iclass 20, count 0 2006.231.07:52:19.55#ibcon#about to read 4, iclass 20, count 0 2006.231.07:52:19.55#ibcon#read 4, iclass 20, count 0 2006.231.07:52:19.55#ibcon#about to read 5, iclass 20, count 0 2006.231.07:52:19.55#ibcon#read 5, iclass 20, count 0 2006.231.07:52:19.55#ibcon#about to read 6, iclass 20, count 0 2006.231.07:52:19.55#ibcon#read 6, iclass 20, count 0 2006.231.07:52:19.55#ibcon#end of sib2, iclass 20, count 0 2006.231.07:52:19.55#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:52:19.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:52:19.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:52:19.55#ibcon#*before write, iclass 20, count 0 2006.231.07:52:19.55#ibcon#enter sib2, iclass 20, count 0 2006.231.07:52:19.55#ibcon#flushed, iclass 20, count 0 2006.231.07:52:19.55#ibcon#about to write, iclass 20, count 0 2006.231.07:52:19.55#ibcon#wrote, iclass 20, count 0 2006.231.07:52:19.55#ibcon#about to read 3, iclass 20, count 0 2006.231.07:52:19.59#ibcon#read 3, iclass 20, count 0 2006.231.07:52:19.59#ibcon#about to read 4, iclass 20, count 0 2006.231.07:52:19.59#ibcon#read 4, iclass 20, count 0 2006.231.07:52:19.59#ibcon#about to read 5, iclass 20, count 0 2006.231.07:52:19.59#ibcon#read 5, iclass 20, count 0 2006.231.07:52:19.59#ibcon#about to read 6, iclass 20, count 0 2006.231.07:52:19.59#ibcon#read 6, iclass 20, count 0 2006.231.07:52:19.59#ibcon#end of sib2, iclass 20, count 0 2006.231.07:52:19.59#ibcon#*after write, iclass 20, count 0 2006.231.07:52:19.59#ibcon#*before return 0, iclass 20, count 0 2006.231.07:52:19.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:52:19.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:52:19.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:52:19.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:52:19.59$vc4f8/va=6,6 2006.231.07:52:19.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.231.07:52:19.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.231.07:52:19.59#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:19.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:52:19.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:52:19.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:52:19.65#ibcon#enter wrdev, iclass 22, count 2 2006.231.07:52:19.65#ibcon#first serial, iclass 22, count 2 2006.231.07:52:19.65#ibcon#enter sib2, iclass 22, count 2 2006.231.07:52:19.65#ibcon#flushed, iclass 22, count 2 2006.231.07:52:19.65#ibcon#about to write, iclass 22, count 2 2006.231.07:52:19.65#ibcon#wrote, iclass 22, count 2 2006.231.07:52:19.65#ibcon#about to read 3, iclass 22, count 2 2006.231.07:52:19.67#ibcon#read 3, iclass 22, count 2 2006.231.07:52:19.67#ibcon#about to read 4, iclass 22, count 2 2006.231.07:52:19.67#ibcon#read 4, iclass 22, count 2 2006.231.07:52:19.67#ibcon#about to read 5, iclass 22, count 2 2006.231.07:52:19.67#ibcon#read 5, iclass 22, count 2 2006.231.07:52:19.67#ibcon#about to read 6, iclass 22, count 2 2006.231.07:52:19.67#ibcon#read 6, iclass 22, count 2 2006.231.07:52:19.67#ibcon#end of sib2, iclass 22, count 2 2006.231.07:52:19.67#ibcon#*mode == 0, iclass 22, count 2 2006.231.07:52:19.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.231.07:52:19.67#ibcon#[25=AT06-06\r\n] 2006.231.07:52:19.67#ibcon#*before write, iclass 22, count 2 2006.231.07:52:19.67#ibcon#enter sib2, iclass 22, count 2 2006.231.07:52:19.67#ibcon#flushed, iclass 22, count 2 2006.231.07:52:19.67#ibcon#about to write, iclass 22, count 2 2006.231.07:52:19.67#ibcon#wrote, iclass 22, count 2 2006.231.07:52:19.67#ibcon#about to read 3, iclass 22, count 2 2006.231.07:52:19.70#ibcon#read 3, iclass 22, count 2 2006.231.07:52:19.70#ibcon#about to read 4, iclass 22, count 2 2006.231.07:52:19.70#ibcon#read 4, iclass 22, count 2 2006.231.07:52:19.70#ibcon#about to read 5, iclass 22, count 2 2006.231.07:52:19.70#ibcon#read 5, iclass 22, count 2 2006.231.07:52:19.70#ibcon#about to read 6, iclass 22, count 2 2006.231.07:52:19.70#ibcon#read 6, iclass 22, count 2 2006.231.07:52:19.70#ibcon#end of sib2, iclass 22, count 2 2006.231.07:52:19.70#ibcon#*after write, iclass 22, count 2 2006.231.07:52:19.70#ibcon#*before return 0, iclass 22, count 2 2006.231.07:52:19.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:52:19.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:52:19.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.231.07:52:19.70#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:19.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:52:19.82#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:52:19.82#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:52:19.82#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:52:19.82#ibcon#first serial, iclass 22, count 0 2006.231.07:52:19.82#ibcon#enter sib2, iclass 22, count 0 2006.231.07:52:19.82#ibcon#flushed, iclass 22, count 0 2006.231.07:52:19.82#ibcon#about to write, iclass 22, count 0 2006.231.07:52:19.82#ibcon#wrote, iclass 22, count 0 2006.231.07:52:19.82#ibcon#about to read 3, iclass 22, count 0 2006.231.07:52:19.84#ibcon#read 3, iclass 22, count 0 2006.231.07:52:19.84#ibcon#about to read 4, iclass 22, count 0 2006.231.07:52:19.84#ibcon#read 4, iclass 22, count 0 2006.231.07:52:19.84#ibcon#about to read 5, iclass 22, count 0 2006.231.07:52:19.84#ibcon#read 5, iclass 22, count 0 2006.231.07:52:19.84#ibcon#about to read 6, iclass 22, count 0 2006.231.07:52:19.84#ibcon#read 6, iclass 22, count 0 2006.231.07:52:19.84#ibcon#end of sib2, iclass 22, count 0 2006.231.07:52:19.84#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:52:19.84#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:52:19.84#ibcon#[25=USB\r\n] 2006.231.07:52:19.84#ibcon#*before write, iclass 22, count 0 2006.231.07:52:19.84#ibcon#enter sib2, iclass 22, count 0 2006.231.07:52:19.84#ibcon#flushed, iclass 22, count 0 2006.231.07:52:19.84#ibcon#about to write, iclass 22, count 0 2006.231.07:52:19.84#ibcon#wrote, iclass 22, count 0 2006.231.07:52:19.84#ibcon#about to read 3, iclass 22, count 0 2006.231.07:52:19.87#ibcon#read 3, iclass 22, count 0 2006.231.07:52:19.87#ibcon#about to read 4, iclass 22, count 0 2006.231.07:52:19.87#ibcon#read 4, iclass 22, count 0 2006.231.07:52:19.87#ibcon#about to read 5, iclass 22, count 0 2006.231.07:52:19.87#ibcon#read 5, iclass 22, count 0 2006.231.07:52:19.87#ibcon#about to read 6, iclass 22, count 0 2006.231.07:52:19.87#ibcon#read 6, iclass 22, count 0 2006.231.07:52:19.87#ibcon#end of sib2, iclass 22, count 0 2006.231.07:52:19.87#ibcon#*after write, iclass 22, count 0 2006.231.07:52:19.87#ibcon#*before return 0, iclass 22, count 0 2006.231.07:52:19.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:52:19.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:52:19.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:52:19.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:52:19.87$vc4f8/valo=7,832.99 2006.231.07:52:19.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.231.07:52:19.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.231.07:52:19.87#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:19.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:52:19.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:52:19.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:52:19.87#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:52:19.87#ibcon#first serial, iclass 24, count 0 2006.231.07:52:19.87#ibcon#enter sib2, iclass 24, count 0 2006.231.07:52:19.87#ibcon#flushed, iclass 24, count 0 2006.231.07:52:19.87#ibcon#about to write, iclass 24, count 0 2006.231.07:52:19.87#ibcon#wrote, iclass 24, count 0 2006.231.07:52:19.87#ibcon#about to read 3, iclass 24, count 0 2006.231.07:52:19.89#ibcon#read 3, iclass 24, count 0 2006.231.07:52:19.89#ibcon#about to read 4, iclass 24, count 0 2006.231.07:52:19.89#ibcon#read 4, iclass 24, count 0 2006.231.07:52:19.89#ibcon#about to read 5, iclass 24, count 0 2006.231.07:52:19.89#ibcon#read 5, iclass 24, count 0 2006.231.07:52:19.89#ibcon#about to read 6, iclass 24, count 0 2006.231.07:52:19.89#ibcon#read 6, iclass 24, count 0 2006.231.07:52:19.89#ibcon#end of sib2, iclass 24, count 0 2006.231.07:52:19.89#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:52:19.89#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:52:19.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:52:19.89#ibcon#*before write, iclass 24, count 0 2006.231.07:52:19.89#ibcon#enter sib2, iclass 24, count 0 2006.231.07:52:19.89#ibcon#flushed, iclass 24, count 0 2006.231.07:52:19.89#ibcon#about to write, iclass 24, count 0 2006.231.07:52:19.89#ibcon#wrote, iclass 24, count 0 2006.231.07:52:19.89#ibcon#about to read 3, iclass 24, count 0 2006.231.07:52:19.93#ibcon#read 3, iclass 24, count 0 2006.231.07:52:19.93#ibcon#about to read 4, iclass 24, count 0 2006.231.07:52:19.93#ibcon#read 4, iclass 24, count 0 2006.231.07:52:19.93#ibcon#about to read 5, iclass 24, count 0 2006.231.07:52:19.93#ibcon#read 5, iclass 24, count 0 2006.231.07:52:19.93#ibcon#about to read 6, iclass 24, count 0 2006.231.07:52:19.93#ibcon#read 6, iclass 24, count 0 2006.231.07:52:19.93#ibcon#end of sib2, iclass 24, count 0 2006.231.07:52:19.93#ibcon#*after write, iclass 24, count 0 2006.231.07:52:19.93#ibcon#*before return 0, iclass 24, count 0 2006.231.07:52:19.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:52:19.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:52:19.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:52:19.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:52:19.93$vc4f8/va=7,6 2006.231.07:52:19.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.231.07:52:19.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.231.07:52:19.93#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:19.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:52:19.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:52:19.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:52:19.99#ibcon#enter wrdev, iclass 26, count 2 2006.231.07:52:19.99#ibcon#first serial, iclass 26, count 2 2006.231.07:52:19.99#ibcon#enter sib2, iclass 26, count 2 2006.231.07:52:19.99#ibcon#flushed, iclass 26, count 2 2006.231.07:52:19.99#ibcon#about to write, iclass 26, count 2 2006.231.07:52:19.99#ibcon#wrote, iclass 26, count 2 2006.231.07:52:19.99#ibcon#about to read 3, iclass 26, count 2 2006.231.07:52:20.01#ibcon#read 3, iclass 26, count 2 2006.231.07:52:20.01#ibcon#about to read 4, iclass 26, count 2 2006.231.07:52:20.01#ibcon#read 4, iclass 26, count 2 2006.231.07:52:20.01#ibcon#about to read 5, iclass 26, count 2 2006.231.07:52:20.01#ibcon#read 5, iclass 26, count 2 2006.231.07:52:20.01#ibcon#about to read 6, iclass 26, count 2 2006.231.07:52:20.01#ibcon#read 6, iclass 26, count 2 2006.231.07:52:20.01#ibcon#end of sib2, iclass 26, count 2 2006.231.07:52:20.01#ibcon#*mode == 0, iclass 26, count 2 2006.231.07:52:20.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.231.07:52:20.01#ibcon#[25=AT07-06\r\n] 2006.231.07:52:20.01#ibcon#*before write, iclass 26, count 2 2006.231.07:52:20.01#ibcon#enter sib2, iclass 26, count 2 2006.231.07:52:20.01#ibcon#flushed, iclass 26, count 2 2006.231.07:52:20.01#ibcon#about to write, iclass 26, count 2 2006.231.07:52:20.01#ibcon#wrote, iclass 26, count 2 2006.231.07:52:20.01#ibcon#about to read 3, iclass 26, count 2 2006.231.07:52:20.04#ibcon#read 3, iclass 26, count 2 2006.231.07:52:20.04#ibcon#about to read 4, iclass 26, count 2 2006.231.07:52:20.04#ibcon#read 4, iclass 26, count 2 2006.231.07:52:20.04#ibcon#about to read 5, iclass 26, count 2 2006.231.07:52:20.04#ibcon#read 5, iclass 26, count 2 2006.231.07:52:20.04#ibcon#about to read 6, iclass 26, count 2 2006.231.07:52:20.04#ibcon#read 6, iclass 26, count 2 2006.231.07:52:20.04#ibcon#end of sib2, iclass 26, count 2 2006.231.07:52:20.04#ibcon#*after write, iclass 26, count 2 2006.231.07:52:20.04#ibcon#*before return 0, iclass 26, count 2 2006.231.07:52:20.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:52:20.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.231.07:52:20.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.231.07:52:20.04#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:20.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:52:20.16#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:52:20.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:52:20.16#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:52:20.16#ibcon#first serial, iclass 26, count 0 2006.231.07:52:20.16#ibcon#enter sib2, iclass 26, count 0 2006.231.07:52:20.16#ibcon#flushed, iclass 26, count 0 2006.231.07:52:20.16#ibcon#about to write, iclass 26, count 0 2006.231.07:52:20.16#ibcon#wrote, iclass 26, count 0 2006.231.07:52:20.16#ibcon#about to read 3, iclass 26, count 0 2006.231.07:52:20.18#ibcon#read 3, iclass 26, count 0 2006.231.07:52:20.18#ibcon#about to read 4, iclass 26, count 0 2006.231.07:52:20.18#ibcon#read 4, iclass 26, count 0 2006.231.07:52:20.18#ibcon#about to read 5, iclass 26, count 0 2006.231.07:52:20.18#ibcon#read 5, iclass 26, count 0 2006.231.07:52:20.18#ibcon#about to read 6, iclass 26, count 0 2006.231.07:52:20.18#ibcon#read 6, iclass 26, count 0 2006.231.07:52:20.18#ibcon#end of sib2, iclass 26, count 0 2006.231.07:52:20.18#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:52:20.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:52:20.18#ibcon#[25=USB\r\n] 2006.231.07:52:20.18#ibcon#*before write, iclass 26, count 0 2006.231.07:52:20.18#ibcon#enter sib2, iclass 26, count 0 2006.231.07:52:20.18#ibcon#flushed, iclass 26, count 0 2006.231.07:52:20.18#ibcon#about to write, iclass 26, count 0 2006.231.07:52:20.18#ibcon#wrote, iclass 26, count 0 2006.231.07:52:20.18#ibcon#about to read 3, iclass 26, count 0 2006.231.07:52:20.21#ibcon#read 3, iclass 26, count 0 2006.231.07:52:20.21#ibcon#about to read 4, iclass 26, count 0 2006.231.07:52:20.21#ibcon#read 4, iclass 26, count 0 2006.231.07:52:20.21#ibcon#about to read 5, iclass 26, count 0 2006.231.07:52:20.21#ibcon#read 5, iclass 26, count 0 2006.231.07:52:20.21#ibcon#about to read 6, iclass 26, count 0 2006.231.07:52:20.21#ibcon#read 6, iclass 26, count 0 2006.231.07:52:20.21#ibcon#end of sib2, iclass 26, count 0 2006.231.07:52:20.21#ibcon#*after write, iclass 26, count 0 2006.231.07:52:20.21#ibcon#*before return 0, iclass 26, count 0 2006.231.07:52:20.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:52:20.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.231.07:52:20.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:52:20.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:52:20.21$vc4f8/valo=8,852.99 2006.231.07:52:20.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.231.07:52:20.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.231.07:52:20.21#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:20.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:52:20.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:52:20.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:52:20.21#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:52:20.21#ibcon#first serial, iclass 28, count 0 2006.231.07:52:20.21#ibcon#enter sib2, iclass 28, count 0 2006.231.07:52:20.21#ibcon#flushed, iclass 28, count 0 2006.231.07:52:20.21#ibcon#about to write, iclass 28, count 0 2006.231.07:52:20.21#ibcon#wrote, iclass 28, count 0 2006.231.07:52:20.21#ibcon#about to read 3, iclass 28, count 0 2006.231.07:52:20.23#ibcon#read 3, iclass 28, count 0 2006.231.07:52:20.23#ibcon#about to read 4, iclass 28, count 0 2006.231.07:52:20.23#ibcon#read 4, iclass 28, count 0 2006.231.07:52:20.23#ibcon#about to read 5, iclass 28, count 0 2006.231.07:52:20.23#ibcon#read 5, iclass 28, count 0 2006.231.07:52:20.23#ibcon#about to read 6, iclass 28, count 0 2006.231.07:52:20.23#ibcon#read 6, iclass 28, count 0 2006.231.07:52:20.23#ibcon#end of sib2, iclass 28, count 0 2006.231.07:52:20.23#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:52:20.23#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:52:20.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:52:20.23#ibcon#*before write, iclass 28, count 0 2006.231.07:52:20.23#ibcon#enter sib2, iclass 28, count 0 2006.231.07:52:20.23#ibcon#flushed, iclass 28, count 0 2006.231.07:52:20.23#ibcon#about to write, iclass 28, count 0 2006.231.07:52:20.23#ibcon#wrote, iclass 28, count 0 2006.231.07:52:20.23#ibcon#about to read 3, iclass 28, count 0 2006.231.07:52:20.27#ibcon#read 3, iclass 28, count 0 2006.231.07:52:20.27#ibcon#about to read 4, iclass 28, count 0 2006.231.07:52:20.27#ibcon#read 4, iclass 28, count 0 2006.231.07:52:20.27#ibcon#about to read 5, iclass 28, count 0 2006.231.07:52:20.27#ibcon#read 5, iclass 28, count 0 2006.231.07:52:20.27#ibcon#about to read 6, iclass 28, count 0 2006.231.07:52:20.27#ibcon#read 6, iclass 28, count 0 2006.231.07:52:20.27#ibcon#end of sib2, iclass 28, count 0 2006.231.07:52:20.27#ibcon#*after write, iclass 28, count 0 2006.231.07:52:20.27#ibcon#*before return 0, iclass 28, count 0 2006.231.07:52:20.27#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:52:20.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.231.07:52:20.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:52:20.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:52:20.27$vc4f8/va=8,6 2006.231.07:52:20.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.07:52:20.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.07:52:20.27#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:20.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:52:20.33#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:52:20.33#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:52:20.33#ibcon#enter wrdev, iclass 30, count 2 2006.231.07:52:20.33#ibcon#first serial, iclass 30, count 2 2006.231.07:52:20.33#ibcon#enter sib2, iclass 30, count 2 2006.231.07:52:20.33#ibcon#flushed, iclass 30, count 2 2006.231.07:52:20.33#ibcon#about to write, iclass 30, count 2 2006.231.07:52:20.33#ibcon#wrote, iclass 30, count 2 2006.231.07:52:20.33#ibcon#about to read 3, iclass 30, count 2 2006.231.07:52:20.35#ibcon#read 3, iclass 30, count 2 2006.231.07:52:20.35#ibcon#about to read 4, iclass 30, count 2 2006.231.07:52:20.35#ibcon#read 4, iclass 30, count 2 2006.231.07:52:20.35#ibcon#about to read 5, iclass 30, count 2 2006.231.07:52:20.35#ibcon#read 5, iclass 30, count 2 2006.231.07:52:20.35#ibcon#about to read 6, iclass 30, count 2 2006.231.07:52:20.35#ibcon#read 6, iclass 30, count 2 2006.231.07:52:20.35#ibcon#end of sib2, iclass 30, count 2 2006.231.07:52:20.35#ibcon#*mode == 0, iclass 30, count 2 2006.231.07:52:20.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.07:52:20.35#ibcon#[25=AT08-06\r\n] 2006.231.07:52:20.35#ibcon#*before write, iclass 30, count 2 2006.231.07:52:20.35#ibcon#enter sib2, iclass 30, count 2 2006.231.07:52:20.35#ibcon#flushed, iclass 30, count 2 2006.231.07:52:20.35#ibcon#about to write, iclass 30, count 2 2006.231.07:52:20.35#ibcon#wrote, iclass 30, count 2 2006.231.07:52:20.35#ibcon#about to read 3, iclass 30, count 2 2006.231.07:52:20.38#ibcon#read 3, iclass 30, count 2 2006.231.07:52:20.38#ibcon#about to read 4, iclass 30, count 2 2006.231.07:52:20.38#ibcon#read 4, iclass 30, count 2 2006.231.07:52:20.38#ibcon#about to read 5, iclass 30, count 2 2006.231.07:52:20.38#ibcon#read 5, iclass 30, count 2 2006.231.07:52:20.38#ibcon#about to read 6, iclass 30, count 2 2006.231.07:52:20.38#ibcon#read 6, iclass 30, count 2 2006.231.07:52:20.38#ibcon#end of sib2, iclass 30, count 2 2006.231.07:52:20.38#ibcon#*after write, iclass 30, count 2 2006.231.07:52:20.38#ibcon#*before return 0, iclass 30, count 2 2006.231.07:52:20.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:52:20.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.07:52:20.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.07:52:20.38#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:20.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:52:20.50#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:52:20.50#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:52:20.50#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:52:20.50#ibcon#first serial, iclass 30, count 0 2006.231.07:52:20.50#ibcon#enter sib2, iclass 30, count 0 2006.231.07:52:20.50#ibcon#flushed, iclass 30, count 0 2006.231.07:52:20.50#ibcon#about to write, iclass 30, count 0 2006.231.07:52:20.50#ibcon#wrote, iclass 30, count 0 2006.231.07:52:20.50#ibcon#about to read 3, iclass 30, count 0 2006.231.07:52:20.52#ibcon#read 3, iclass 30, count 0 2006.231.07:52:20.52#ibcon#about to read 4, iclass 30, count 0 2006.231.07:52:20.52#ibcon#read 4, iclass 30, count 0 2006.231.07:52:20.52#ibcon#about to read 5, iclass 30, count 0 2006.231.07:52:20.52#ibcon#read 5, iclass 30, count 0 2006.231.07:52:20.52#ibcon#about to read 6, iclass 30, count 0 2006.231.07:52:20.52#ibcon#read 6, iclass 30, count 0 2006.231.07:52:20.52#ibcon#end of sib2, iclass 30, count 0 2006.231.07:52:20.52#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:52:20.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:52:20.52#ibcon#[25=USB\r\n] 2006.231.07:52:20.52#ibcon#*before write, iclass 30, count 0 2006.231.07:52:20.52#ibcon#enter sib2, iclass 30, count 0 2006.231.07:52:20.52#ibcon#flushed, iclass 30, count 0 2006.231.07:52:20.52#ibcon#about to write, iclass 30, count 0 2006.231.07:52:20.52#ibcon#wrote, iclass 30, count 0 2006.231.07:52:20.52#ibcon#about to read 3, iclass 30, count 0 2006.231.07:52:20.55#ibcon#read 3, iclass 30, count 0 2006.231.07:52:20.55#ibcon#about to read 4, iclass 30, count 0 2006.231.07:52:20.55#ibcon#read 4, iclass 30, count 0 2006.231.07:52:20.55#ibcon#about to read 5, iclass 30, count 0 2006.231.07:52:20.55#ibcon#read 5, iclass 30, count 0 2006.231.07:52:20.55#ibcon#about to read 6, iclass 30, count 0 2006.231.07:52:20.55#ibcon#read 6, iclass 30, count 0 2006.231.07:52:20.55#ibcon#end of sib2, iclass 30, count 0 2006.231.07:52:20.55#ibcon#*after write, iclass 30, count 0 2006.231.07:52:20.55#ibcon#*before return 0, iclass 30, count 0 2006.231.07:52:20.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:52:20.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.07:52:20.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:52:20.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:52:20.55$vc4f8/vblo=1,632.99 2006.231.07:52:20.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.07:52:20.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.07:52:20.55#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:20.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:52:20.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:52:20.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:52:20.55#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:52:20.55#ibcon#first serial, iclass 32, count 0 2006.231.07:52:20.55#ibcon#enter sib2, iclass 32, count 0 2006.231.07:52:20.55#ibcon#flushed, iclass 32, count 0 2006.231.07:52:20.55#ibcon#about to write, iclass 32, count 0 2006.231.07:52:20.55#ibcon#wrote, iclass 32, count 0 2006.231.07:52:20.55#ibcon#about to read 3, iclass 32, count 0 2006.231.07:52:20.57#ibcon#read 3, iclass 32, count 0 2006.231.07:52:20.57#ibcon#about to read 4, iclass 32, count 0 2006.231.07:52:20.57#ibcon#read 4, iclass 32, count 0 2006.231.07:52:20.57#ibcon#about to read 5, iclass 32, count 0 2006.231.07:52:20.57#ibcon#read 5, iclass 32, count 0 2006.231.07:52:20.57#ibcon#about to read 6, iclass 32, count 0 2006.231.07:52:20.57#ibcon#read 6, iclass 32, count 0 2006.231.07:52:20.57#ibcon#end of sib2, iclass 32, count 0 2006.231.07:52:20.57#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:52:20.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:52:20.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:52:20.57#ibcon#*before write, iclass 32, count 0 2006.231.07:52:20.57#ibcon#enter sib2, iclass 32, count 0 2006.231.07:52:20.57#ibcon#flushed, iclass 32, count 0 2006.231.07:52:20.57#ibcon#about to write, iclass 32, count 0 2006.231.07:52:20.57#ibcon#wrote, iclass 32, count 0 2006.231.07:52:20.57#ibcon#about to read 3, iclass 32, count 0 2006.231.07:52:20.61#ibcon#read 3, iclass 32, count 0 2006.231.07:52:20.61#ibcon#about to read 4, iclass 32, count 0 2006.231.07:52:20.61#ibcon#read 4, iclass 32, count 0 2006.231.07:52:20.61#ibcon#about to read 5, iclass 32, count 0 2006.231.07:52:20.61#ibcon#read 5, iclass 32, count 0 2006.231.07:52:20.61#ibcon#about to read 6, iclass 32, count 0 2006.231.07:52:20.61#ibcon#read 6, iclass 32, count 0 2006.231.07:52:20.61#ibcon#end of sib2, iclass 32, count 0 2006.231.07:52:20.61#ibcon#*after write, iclass 32, count 0 2006.231.07:52:20.61#ibcon#*before return 0, iclass 32, count 0 2006.231.07:52:20.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:52:20.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.07:52:20.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:52:20.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:52:20.61$vc4f8/vb=1,4 2006.231.07:52:20.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.07:52:20.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.07:52:20.61#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:20.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:52:20.61#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:52:20.61#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:52:20.61#ibcon#enter wrdev, iclass 34, count 2 2006.231.07:52:20.61#ibcon#first serial, iclass 34, count 2 2006.231.07:52:20.61#ibcon#enter sib2, iclass 34, count 2 2006.231.07:52:20.61#ibcon#flushed, iclass 34, count 2 2006.231.07:52:20.61#ibcon#about to write, iclass 34, count 2 2006.231.07:52:20.61#ibcon#wrote, iclass 34, count 2 2006.231.07:52:20.61#ibcon#about to read 3, iclass 34, count 2 2006.231.07:52:20.63#ibcon#read 3, iclass 34, count 2 2006.231.07:52:20.63#ibcon#about to read 4, iclass 34, count 2 2006.231.07:52:20.63#ibcon#read 4, iclass 34, count 2 2006.231.07:52:20.63#ibcon#about to read 5, iclass 34, count 2 2006.231.07:52:20.63#ibcon#read 5, iclass 34, count 2 2006.231.07:52:20.63#ibcon#about to read 6, iclass 34, count 2 2006.231.07:52:20.63#ibcon#read 6, iclass 34, count 2 2006.231.07:52:20.63#ibcon#end of sib2, iclass 34, count 2 2006.231.07:52:20.63#ibcon#*mode == 0, iclass 34, count 2 2006.231.07:52:20.63#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.07:52:20.63#ibcon#[27=AT01-04\r\n] 2006.231.07:52:20.63#ibcon#*before write, iclass 34, count 2 2006.231.07:52:20.63#ibcon#enter sib2, iclass 34, count 2 2006.231.07:52:20.63#ibcon#flushed, iclass 34, count 2 2006.231.07:52:20.63#ibcon#about to write, iclass 34, count 2 2006.231.07:52:20.63#ibcon#wrote, iclass 34, count 2 2006.231.07:52:20.63#ibcon#about to read 3, iclass 34, count 2 2006.231.07:52:20.66#ibcon#read 3, iclass 34, count 2 2006.231.07:52:20.66#ibcon#about to read 4, iclass 34, count 2 2006.231.07:52:20.66#ibcon#read 4, iclass 34, count 2 2006.231.07:52:20.66#ibcon#about to read 5, iclass 34, count 2 2006.231.07:52:20.66#ibcon#read 5, iclass 34, count 2 2006.231.07:52:20.66#ibcon#about to read 6, iclass 34, count 2 2006.231.07:52:20.66#ibcon#read 6, iclass 34, count 2 2006.231.07:52:20.66#ibcon#end of sib2, iclass 34, count 2 2006.231.07:52:20.66#ibcon#*after write, iclass 34, count 2 2006.231.07:52:20.66#ibcon#*before return 0, iclass 34, count 2 2006.231.07:52:20.66#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:52:20.66#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.07:52:20.66#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.07:52:20.66#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:20.66#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:52:20.78#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:52:20.78#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:52:20.78#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:52:20.78#ibcon#first serial, iclass 34, count 0 2006.231.07:52:20.78#ibcon#enter sib2, iclass 34, count 0 2006.231.07:52:20.78#ibcon#flushed, iclass 34, count 0 2006.231.07:52:20.78#ibcon#about to write, iclass 34, count 0 2006.231.07:52:20.78#ibcon#wrote, iclass 34, count 0 2006.231.07:52:20.78#ibcon#about to read 3, iclass 34, count 0 2006.231.07:52:20.80#ibcon#read 3, iclass 34, count 0 2006.231.07:52:20.80#ibcon#about to read 4, iclass 34, count 0 2006.231.07:52:20.80#ibcon#read 4, iclass 34, count 0 2006.231.07:52:20.80#ibcon#about to read 5, iclass 34, count 0 2006.231.07:52:20.80#ibcon#read 5, iclass 34, count 0 2006.231.07:52:20.80#ibcon#about to read 6, iclass 34, count 0 2006.231.07:52:20.80#ibcon#read 6, iclass 34, count 0 2006.231.07:52:20.80#ibcon#end of sib2, iclass 34, count 0 2006.231.07:52:20.80#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:52:20.80#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:52:20.80#ibcon#[27=USB\r\n] 2006.231.07:52:20.80#ibcon#*before write, iclass 34, count 0 2006.231.07:52:20.80#ibcon#enter sib2, iclass 34, count 0 2006.231.07:52:20.80#ibcon#flushed, iclass 34, count 0 2006.231.07:52:20.80#ibcon#about to write, iclass 34, count 0 2006.231.07:52:20.80#ibcon#wrote, iclass 34, count 0 2006.231.07:52:20.80#ibcon#about to read 3, iclass 34, count 0 2006.231.07:52:20.83#ibcon#read 3, iclass 34, count 0 2006.231.07:52:20.83#ibcon#about to read 4, iclass 34, count 0 2006.231.07:52:20.83#ibcon#read 4, iclass 34, count 0 2006.231.07:52:20.83#ibcon#about to read 5, iclass 34, count 0 2006.231.07:52:20.83#ibcon#read 5, iclass 34, count 0 2006.231.07:52:20.83#ibcon#about to read 6, iclass 34, count 0 2006.231.07:52:20.83#ibcon#read 6, iclass 34, count 0 2006.231.07:52:20.83#ibcon#end of sib2, iclass 34, count 0 2006.231.07:52:20.83#ibcon#*after write, iclass 34, count 0 2006.231.07:52:20.83#ibcon#*before return 0, iclass 34, count 0 2006.231.07:52:20.83#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:52:20.83#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.07:52:20.83#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:52:20.83#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:52:20.83$vc4f8/vblo=2,640.99 2006.231.07:52:20.83#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.07:52:20.83#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.07:52:20.83#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:20.83#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:52:20.83#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:52:20.83#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:52:20.83#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:52:20.83#ibcon#first serial, iclass 36, count 0 2006.231.07:52:20.83#ibcon#enter sib2, iclass 36, count 0 2006.231.07:52:20.83#ibcon#flushed, iclass 36, count 0 2006.231.07:52:20.83#ibcon#about to write, iclass 36, count 0 2006.231.07:52:20.83#ibcon#wrote, iclass 36, count 0 2006.231.07:52:20.83#ibcon#about to read 3, iclass 36, count 0 2006.231.07:52:20.85#ibcon#read 3, iclass 36, count 0 2006.231.07:52:20.85#ibcon#about to read 4, iclass 36, count 0 2006.231.07:52:20.85#ibcon#read 4, iclass 36, count 0 2006.231.07:52:20.85#ibcon#about to read 5, iclass 36, count 0 2006.231.07:52:20.85#ibcon#read 5, iclass 36, count 0 2006.231.07:52:20.85#ibcon#about to read 6, iclass 36, count 0 2006.231.07:52:20.85#ibcon#read 6, iclass 36, count 0 2006.231.07:52:20.85#ibcon#end of sib2, iclass 36, count 0 2006.231.07:52:20.85#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:52:20.85#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:52:20.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:52:20.85#ibcon#*before write, iclass 36, count 0 2006.231.07:52:20.85#ibcon#enter sib2, iclass 36, count 0 2006.231.07:52:20.85#ibcon#flushed, iclass 36, count 0 2006.231.07:52:20.85#ibcon#about to write, iclass 36, count 0 2006.231.07:52:20.85#ibcon#wrote, iclass 36, count 0 2006.231.07:52:20.85#ibcon#about to read 3, iclass 36, count 0 2006.231.07:52:20.89#ibcon#read 3, iclass 36, count 0 2006.231.07:52:20.89#ibcon#about to read 4, iclass 36, count 0 2006.231.07:52:20.89#ibcon#read 4, iclass 36, count 0 2006.231.07:52:20.89#ibcon#about to read 5, iclass 36, count 0 2006.231.07:52:20.89#ibcon#read 5, iclass 36, count 0 2006.231.07:52:20.89#ibcon#about to read 6, iclass 36, count 0 2006.231.07:52:20.89#ibcon#read 6, iclass 36, count 0 2006.231.07:52:20.89#ibcon#end of sib2, iclass 36, count 0 2006.231.07:52:20.89#ibcon#*after write, iclass 36, count 0 2006.231.07:52:20.89#ibcon#*before return 0, iclass 36, count 0 2006.231.07:52:20.89#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:52:20.89#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.07:52:20.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:52:20.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:52:20.89$vc4f8/vb=2,4 2006.231.07:52:20.89#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.07:52:20.89#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.07:52:20.89#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:20.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:52:20.95#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:52:20.95#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:52:20.95#ibcon#enter wrdev, iclass 38, count 2 2006.231.07:52:20.95#ibcon#first serial, iclass 38, count 2 2006.231.07:52:20.95#ibcon#enter sib2, iclass 38, count 2 2006.231.07:52:20.95#ibcon#flushed, iclass 38, count 2 2006.231.07:52:20.95#ibcon#about to write, iclass 38, count 2 2006.231.07:52:20.95#ibcon#wrote, iclass 38, count 2 2006.231.07:52:20.95#ibcon#about to read 3, iclass 38, count 2 2006.231.07:52:20.98#ibcon#read 3, iclass 38, count 2 2006.231.07:52:20.98#ibcon#about to read 4, iclass 38, count 2 2006.231.07:52:20.98#ibcon#read 4, iclass 38, count 2 2006.231.07:52:20.98#ibcon#about to read 5, iclass 38, count 2 2006.231.07:52:20.98#ibcon#read 5, iclass 38, count 2 2006.231.07:52:20.98#ibcon#about to read 6, iclass 38, count 2 2006.231.07:52:20.98#ibcon#read 6, iclass 38, count 2 2006.231.07:52:20.98#ibcon#end of sib2, iclass 38, count 2 2006.231.07:52:20.98#ibcon#*mode == 0, iclass 38, count 2 2006.231.07:52:20.98#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.07:52:20.98#ibcon#[27=AT02-04\r\n] 2006.231.07:52:20.98#ibcon#*before write, iclass 38, count 2 2006.231.07:52:20.98#ibcon#enter sib2, iclass 38, count 2 2006.231.07:52:20.98#ibcon#flushed, iclass 38, count 2 2006.231.07:52:20.98#ibcon#about to write, iclass 38, count 2 2006.231.07:52:20.98#ibcon#wrote, iclass 38, count 2 2006.231.07:52:20.98#ibcon#about to read 3, iclass 38, count 2 2006.231.07:52:21.01#ibcon#read 3, iclass 38, count 2 2006.231.07:52:21.01#ibcon#about to read 4, iclass 38, count 2 2006.231.07:52:21.01#ibcon#read 4, iclass 38, count 2 2006.231.07:52:21.01#ibcon#about to read 5, iclass 38, count 2 2006.231.07:52:21.01#ibcon#read 5, iclass 38, count 2 2006.231.07:52:21.01#ibcon#about to read 6, iclass 38, count 2 2006.231.07:52:21.01#ibcon#read 6, iclass 38, count 2 2006.231.07:52:21.01#ibcon#end of sib2, iclass 38, count 2 2006.231.07:52:21.01#ibcon#*after write, iclass 38, count 2 2006.231.07:52:21.01#ibcon#*before return 0, iclass 38, count 2 2006.231.07:52:21.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:52:21.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.07:52:21.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.07:52:21.01#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:21.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:52:21.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:52:21.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:52:21.13#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:52:21.13#ibcon#first serial, iclass 38, count 0 2006.231.07:52:21.13#ibcon#enter sib2, iclass 38, count 0 2006.231.07:52:21.13#ibcon#flushed, iclass 38, count 0 2006.231.07:52:21.13#ibcon#about to write, iclass 38, count 0 2006.231.07:52:21.13#ibcon#wrote, iclass 38, count 0 2006.231.07:52:21.13#ibcon#about to read 3, iclass 38, count 0 2006.231.07:52:21.15#ibcon#read 3, iclass 38, count 0 2006.231.07:52:21.15#ibcon#about to read 4, iclass 38, count 0 2006.231.07:52:21.15#ibcon#read 4, iclass 38, count 0 2006.231.07:52:21.15#ibcon#about to read 5, iclass 38, count 0 2006.231.07:52:21.15#ibcon#read 5, iclass 38, count 0 2006.231.07:52:21.15#ibcon#about to read 6, iclass 38, count 0 2006.231.07:52:21.15#ibcon#read 6, iclass 38, count 0 2006.231.07:52:21.15#ibcon#end of sib2, iclass 38, count 0 2006.231.07:52:21.15#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:52:21.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:52:21.15#ibcon#[27=USB\r\n] 2006.231.07:52:21.15#ibcon#*before write, iclass 38, count 0 2006.231.07:52:21.15#ibcon#enter sib2, iclass 38, count 0 2006.231.07:52:21.15#ibcon#flushed, iclass 38, count 0 2006.231.07:52:21.15#ibcon#about to write, iclass 38, count 0 2006.231.07:52:21.15#ibcon#wrote, iclass 38, count 0 2006.231.07:52:21.15#ibcon#about to read 3, iclass 38, count 0 2006.231.07:52:21.18#ibcon#read 3, iclass 38, count 0 2006.231.07:52:21.18#ibcon#about to read 4, iclass 38, count 0 2006.231.07:52:21.18#ibcon#read 4, iclass 38, count 0 2006.231.07:52:21.18#ibcon#about to read 5, iclass 38, count 0 2006.231.07:52:21.18#ibcon#read 5, iclass 38, count 0 2006.231.07:52:21.18#ibcon#about to read 6, iclass 38, count 0 2006.231.07:52:21.18#ibcon#read 6, iclass 38, count 0 2006.231.07:52:21.18#ibcon#end of sib2, iclass 38, count 0 2006.231.07:52:21.18#ibcon#*after write, iclass 38, count 0 2006.231.07:52:21.18#ibcon#*before return 0, iclass 38, count 0 2006.231.07:52:21.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:52:21.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.07:52:21.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:52:21.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:52:21.18$vc4f8/vblo=3,656.99 2006.231.07:52:21.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.07:52:21.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.07:52:21.18#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:21.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:52:21.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:52:21.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:52:21.18#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:52:21.18#ibcon#first serial, iclass 40, count 0 2006.231.07:52:21.18#ibcon#enter sib2, iclass 40, count 0 2006.231.07:52:21.18#ibcon#flushed, iclass 40, count 0 2006.231.07:52:21.18#ibcon#about to write, iclass 40, count 0 2006.231.07:52:21.18#ibcon#wrote, iclass 40, count 0 2006.231.07:52:21.18#ibcon#about to read 3, iclass 40, count 0 2006.231.07:52:21.20#ibcon#read 3, iclass 40, count 0 2006.231.07:52:21.20#ibcon#about to read 4, iclass 40, count 0 2006.231.07:52:21.20#ibcon#read 4, iclass 40, count 0 2006.231.07:52:21.20#ibcon#about to read 5, iclass 40, count 0 2006.231.07:52:21.20#ibcon#read 5, iclass 40, count 0 2006.231.07:52:21.20#ibcon#about to read 6, iclass 40, count 0 2006.231.07:52:21.20#ibcon#read 6, iclass 40, count 0 2006.231.07:52:21.20#ibcon#end of sib2, iclass 40, count 0 2006.231.07:52:21.20#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:52:21.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:52:21.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:52:21.20#ibcon#*before write, iclass 40, count 0 2006.231.07:52:21.20#ibcon#enter sib2, iclass 40, count 0 2006.231.07:52:21.20#ibcon#flushed, iclass 40, count 0 2006.231.07:52:21.20#ibcon#about to write, iclass 40, count 0 2006.231.07:52:21.20#ibcon#wrote, iclass 40, count 0 2006.231.07:52:21.20#ibcon#about to read 3, iclass 40, count 0 2006.231.07:52:21.24#ibcon#read 3, iclass 40, count 0 2006.231.07:52:21.24#ibcon#about to read 4, iclass 40, count 0 2006.231.07:52:21.24#ibcon#read 4, iclass 40, count 0 2006.231.07:52:21.24#ibcon#about to read 5, iclass 40, count 0 2006.231.07:52:21.24#ibcon#read 5, iclass 40, count 0 2006.231.07:52:21.24#ibcon#about to read 6, iclass 40, count 0 2006.231.07:52:21.24#ibcon#read 6, iclass 40, count 0 2006.231.07:52:21.24#ibcon#end of sib2, iclass 40, count 0 2006.231.07:52:21.24#ibcon#*after write, iclass 40, count 0 2006.231.07:52:21.24#ibcon#*before return 0, iclass 40, count 0 2006.231.07:52:21.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:52:21.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:52:21.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:52:21.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:52:21.24$vc4f8/vb=3,4 2006.231.07:52:21.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.231.07:52:21.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.231.07:52:21.24#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:21.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:52:21.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:52:21.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:52:21.30#ibcon#enter wrdev, iclass 4, count 2 2006.231.07:52:21.30#ibcon#first serial, iclass 4, count 2 2006.231.07:52:21.30#ibcon#enter sib2, iclass 4, count 2 2006.231.07:52:21.30#ibcon#flushed, iclass 4, count 2 2006.231.07:52:21.30#ibcon#about to write, iclass 4, count 2 2006.231.07:52:21.30#ibcon#wrote, iclass 4, count 2 2006.231.07:52:21.30#ibcon#about to read 3, iclass 4, count 2 2006.231.07:52:21.32#ibcon#read 3, iclass 4, count 2 2006.231.07:52:21.32#ibcon#about to read 4, iclass 4, count 2 2006.231.07:52:21.32#ibcon#read 4, iclass 4, count 2 2006.231.07:52:21.32#ibcon#about to read 5, iclass 4, count 2 2006.231.07:52:21.32#ibcon#read 5, iclass 4, count 2 2006.231.07:52:21.32#ibcon#about to read 6, iclass 4, count 2 2006.231.07:52:21.32#ibcon#read 6, iclass 4, count 2 2006.231.07:52:21.32#ibcon#end of sib2, iclass 4, count 2 2006.231.07:52:21.32#ibcon#*mode == 0, iclass 4, count 2 2006.231.07:52:21.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.231.07:52:21.32#ibcon#[27=AT03-04\r\n] 2006.231.07:52:21.32#ibcon#*before write, iclass 4, count 2 2006.231.07:52:21.32#ibcon#enter sib2, iclass 4, count 2 2006.231.07:52:21.32#ibcon#flushed, iclass 4, count 2 2006.231.07:52:21.32#ibcon#about to write, iclass 4, count 2 2006.231.07:52:21.32#ibcon#wrote, iclass 4, count 2 2006.231.07:52:21.32#ibcon#about to read 3, iclass 4, count 2 2006.231.07:52:21.35#ibcon#read 3, iclass 4, count 2 2006.231.07:52:21.35#ibcon#about to read 4, iclass 4, count 2 2006.231.07:52:21.35#ibcon#read 4, iclass 4, count 2 2006.231.07:52:21.35#ibcon#about to read 5, iclass 4, count 2 2006.231.07:52:21.35#ibcon#read 5, iclass 4, count 2 2006.231.07:52:21.35#ibcon#about to read 6, iclass 4, count 2 2006.231.07:52:21.35#ibcon#read 6, iclass 4, count 2 2006.231.07:52:21.35#ibcon#end of sib2, iclass 4, count 2 2006.231.07:52:21.35#ibcon#*after write, iclass 4, count 2 2006.231.07:52:21.35#ibcon#*before return 0, iclass 4, count 2 2006.231.07:52:21.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:52:21.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.231.07:52:21.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.231.07:52:21.35#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:21.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:52:21.43#abcon#<5=/06 3.9 7.3 30.56 861004.4\r\n> 2006.231.07:52:21.45#abcon#{5=INTERFACE CLEAR} 2006.231.07:52:21.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:52:21.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:52:21.47#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:52:21.47#ibcon#first serial, iclass 4, count 0 2006.231.07:52:21.47#ibcon#enter sib2, iclass 4, count 0 2006.231.07:52:21.47#ibcon#flushed, iclass 4, count 0 2006.231.07:52:21.47#ibcon#about to write, iclass 4, count 0 2006.231.07:52:21.47#ibcon#wrote, iclass 4, count 0 2006.231.07:52:21.47#ibcon#about to read 3, iclass 4, count 0 2006.231.07:52:21.49#ibcon#read 3, iclass 4, count 0 2006.231.07:52:21.49#ibcon#about to read 4, iclass 4, count 0 2006.231.07:52:21.49#ibcon#read 4, iclass 4, count 0 2006.231.07:52:21.49#ibcon#about to read 5, iclass 4, count 0 2006.231.07:52:21.49#ibcon#read 5, iclass 4, count 0 2006.231.07:52:21.49#ibcon#about to read 6, iclass 4, count 0 2006.231.07:52:21.49#ibcon#read 6, iclass 4, count 0 2006.231.07:52:21.49#ibcon#end of sib2, iclass 4, count 0 2006.231.07:52:21.49#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:52:21.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:52:21.49#ibcon#[27=USB\r\n] 2006.231.07:52:21.49#ibcon#*before write, iclass 4, count 0 2006.231.07:52:21.49#ibcon#enter sib2, iclass 4, count 0 2006.231.07:52:21.49#ibcon#flushed, iclass 4, count 0 2006.231.07:52:21.49#ibcon#about to write, iclass 4, count 0 2006.231.07:52:21.49#ibcon#wrote, iclass 4, count 0 2006.231.07:52:21.49#ibcon#about to read 3, iclass 4, count 0 2006.231.07:52:21.51#abcon#[5=S1D000X0/0*\r\n] 2006.231.07:52:21.52#ibcon#read 3, iclass 4, count 0 2006.231.07:52:21.52#ibcon#about to read 4, iclass 4, count 0 2006.231.07:52:21.52#ibcon#read 4, iclass 4, count 0 2006.231.07:52:21.52#ibcon#about to read 5, iclass 4, count 0 2006.231.07:52:21.52#ibcon#read 5, iclass 4, count 0 2006.231.07:52:21.52#ibcon#about to read 6, iclass 4, count 0 2006.231.07:52:21.52#ibcon#read 6, iclass 4, count 0 2006.231.07:52:21.52#ibcon#end of sib2, iclass 4, count 0 2006.231.07:52:21.52#ibcon#*after write, iclass 4, count 0 2006.231.07:52:21.52#ibcon#*before return 0, iclass 4, count 0 2006.231.07:52:21.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:52:21.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.231.07:52:21.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:52:21.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:52:21.52$vc4f8/vblo=4,712.99 2006.231.07:52:21.52#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.07:52:21.52#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.07:52:21.52#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:21.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:52:21.52#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:52:21.52#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:52:21.52#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:52:21.52#ibcon#first serial, iclass 12, count 0 2006.231.07:52:21.52#ibcon#enter sib2, iclass 12, count 0 2006.231.07:52:21.52#ibcon#flushed, iclass 12, count 0 2006.231.07:52:21.52#ibcon#about to write, iclass 12, count 0 2006.231.07:52:21.52#ibcon#wrote, iclass 12, count 0 2006.231.07:52:21.52#ibcon#about to read 3, iclass 12, count 0 2006.231.07:52:21.54#ibcon#read 3, iclass 12, count 0 2006.231.07:52:21.54#ibcon#about to read 4, iclass 12, count 0 2006.231.07:52:21.54#ibcon#read 4, iclass 12, count 0 2006.231.07:52:21.54#ibcon#about to read 5, iclass 12, count 0 2006.231.07:52:21.54#ibcon#read 5, iclass 12, count 0 2006.231.07:52:21.54#ibcon#about to read 6, iclass 12, count 0 2006.231.07:52:21.54#ibcon#read 6, iclass 12, count 0 2006.231.07:52:21.54#ibcon#end of sib2, iclass 12, count 0 2006.231.07:52:21.54#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:52:21.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:52:21.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:52:21.54#ibcon#*before write, iclass 12, count 0 2006.231.07:52:21.54#ibcon#enter sib2, iclass 12, count 0 2006.231.07:52:21.54#ibcon#flushed, iclass 12, count 0 2006.231.07:52:21.54#ibcon#about to write, iclass 12, count 0 2006.231.07:52:21.54#ibcon#wrote, iclass 12, count 0 2006.231.07:52:21.54#ibcon#about to read 3, iclass 12, count 0 2006.231.07:52:21.58#ibcon#read 3, iclass 12, count 0 2006.231.07:52:21.58#ibcon#about to read 4, iclass 12, count 0 2006.231.07:52:21.58#ibcon#read 4, iclass 12, count 0 2006.231.07:52:21.58#ibcon#about to read 5, iclass 12, count 0 2006.231.07:52:21.58#ibcon#read 5, iclass 12, count 0 2006.231.07:52:21.58#ibcon#about to read 6, iclass 12, count 0 2006.231.07:52:21.58#ibcon#read 6, iclass 12, count 0 2006.231.07:52:21.58#ibcon#end of sib2, iclass 12, count 0 2006.231.07:52:21.58#ibcon#*after write, iclass 12, count 0 2006.231.07:52:21.58#ibcon#*before return 0, iclass 12, count 0 2006.231.07:52:21.58#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:52:21.58#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.07:52:21.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:52:21.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:52:21.58$vc4f8/vb=4,4 2006.231.07:52:21.58#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.07:52:21.58#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.07:52:21.58#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:21.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:52:21.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:52:21.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:52:21.64#ibcon#enter wrdev, iclass 14, count 2 2006.231.07:52:21.64#ibcon#first serial, iclass 14, count 2 2006.231.07:52:21.64#ibcon#enter sib2, iclass 14, count 2 2006.231.07:52:21.64#ibcon#flushed, iclass 14, count 2 2006.231.07:52:21.64#ibcon#about to write, iclass 14, count 2 2006.231.07:52:21.64#ibcon#wrote, iclass 14, count 2 2006.231.07:52:21.64#ibcon#about to read 3, iclass 14, count 2 2006.231.07:52:21.66#ibcon#read 3, iclass 14, count 2 2006.231.07:52:21.66#ibcon#about to read 4, iclass 14, count 2 2006.231.07:52:21.66#ibcon#read 4, iclass 14, count 2 2006.231.07:52:21.66#ibcon#about to read 5, iclass 14, count 2 2006.231.07:52:21.66#ibcon#read 5, iclass 14, count 2 2006.231.07:52:21.66#ibcon#about to read 6, iclass 14, count 2 2006.231.07:52:21.66#ibcon#read 6, iclass 14, count 2 2006.231.07:52:21.66#ibcon#end of sib2, iclass 14, count 2 2006.231.07:52:21.66#ibcon#*mode == 0, iclass 14, count 2 2006.231.07:52:21.66#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.07:52:21.66#ibcon#[27=AT04-04\r\n] 2006.231.07:52:21.66#ibcon#*before write, iclass 14, count 2 2006.231.07:52:21.66#ibcon#enter sib2, iclass 14, count 2 2006.231.07:52:21.66#ibcon#flushed, iclass 14, count 2 2006.231.07:52:21.66#ibcon#about to write, iclass 14, count 2 2006.231.07:52:21.66#ibcon#wrote, iclass 14, count 2 2006.231.07:52:21.66#ibcon#about to read 3, iclass 14, count 2 2006.231.07:52:21.69#ibcon#read 3, iclass 14, count 2 2006.231.07:52:21.69#ibcon#about to read 4, iclass 14, count 2 2006.231.07:52:21.69#ibcon#read 4, iclass 14, count 2 2006.231.07:52:21.69#ibcon#about to read 5, iclass 14, count 2 2006.231.07:52:21.69#ibcon#read 5, iclass 14, count 2 2006.231.07:52:21.69#ibcon#about to read 6, iclass 14, count 2 2006.231.07:52:21.69#ibcon#read 6, iclass 14, count 2 2006.231.07:52:21.69#ibcon#end of sib2, iclass 14, count 2 2006.231.07:52:21.69#ibcon#*after write, iclass 14, count 2 2006.231.07:52:21.69#ibcon#*before return 0, iclass 14, count 2 2006.231.07:52:21.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:52:21.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.07:52:21.69#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.07:52:21.69#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:21.69#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:52:21.81#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:52:21.81#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:52:21.81#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:52:21.81#ibcon#first serial, iclass 14, count 0 2006.231.07:52:21.81#ibcon#enter sib2, iclass 14, count 0 2006.231.07:52:21.81#ibcon#flushed, iclass 14, count 0 2006.231.07:52:21.81#ibcon#about to write, iclass 14, count 0 2006.231.07:52:21.81#ibcon#wrote, iclass 14, count 0 2006.231.07:52:21.81#ibcon#about to read 3, iclass 14, count 0 2006.231.07:52:21.83#ibcon#read 3, iclass 14, count 0 2006.231.07:52:21.83#ibcon#about to read 4, iclass 14, count 0 2006.231.07:52:21.83#ibcon#read 4, iclass 14, count 0 2006.231.07:52:21.83#ibcon#about to read 5, iclass 14, count 0 2006.231.07:52:21.83#ibcon#read 5, iclass 14, count 0 2006.231.07:52:21.83#ibcon#about to read 6, iclass 14, count 0 2006.231.07:52:21.83#ibcon#read 6, iclass 14, count 0 2006.231.07:52:21.83#ibcon#end of sib2, iclass 14, count 0 2006.231.07:52:21.83#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:52:21.83#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:52:21.83#ibcon#[27=USB\r\n] 2006.231.07:52:21.83#ibcon#*before write, iclass 14, count 0 2006.231.07:52:21.83#ibcon#enter sib2, iclass 14, count 0 2006.231.07:52:21.83#ibcon#flushed, iclass 14, count 0 2006.231.07:52:21.83#ibcon#about to write, iclass 14, count 0 2006.231.07:52:21.83#ibcon#wrote, iclass 14, count 0 2006.231.07:52:21.83#ibcon#about to read 3, iclass 14, count 0 2006.231.07:52:21.86#ibcon#read 3, iclass 14, count 0 2006.231.07:52:21.86#ibcon#about to read 4, iclass 14, count 0 2006.231.07:52:21.86#ibcon#read 4, iclass 14, count 0 2006.231.07:52:21.86#ibcon#about to read 5, iclass 14, count 0 2006.231.07:52:21.86#ibcon#read 5, iclass 14, count 0 2006.231.07:52:21.86#ibcon#about to read 6, iclass 14, count 0 2006.231.07:52:21.86#ibcon#read 6, iclass 14, count 0 2006.231.07:52:21.86#ibcon#end of sib2, iclass 14, count 0 2006.231.07:52:21.86#ibcon#*after write, iclass 14, count 0 2006.231.07:52:21.86#ibcon#*before return 0, iclass 14, count 0 2006.231.07:52:21.86#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:52:21.86#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.07:52:21.86#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:52:21.86#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:52:21.86$vc4f8/vblo=5,744.99 2006.231.07:52:21.86#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.07:52:21.86#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.07:52:21.86#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:21.86#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:52:21.86#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:52:21.86#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:52:21.86#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:52:21.86#ibcon#first serial, iclass 16, count 0 2006.231.07:52:21.86#ibcon#enter sib2, iclass 16, count 0 2006.231.07:52:21.86#ibcon#flushed, iclass 16, count 0 2006.231.07:52:21.86#ibcon#about to write, iclass 16, count 0 2006.231.07:52:21.86#ibcon#wrote, iclass 16, count 0 2006.231.07:52:21.86#ibcon#about to read 3, iclass 16, count 0 2006.231.07:52:21.88#ibcon#read 3, iclass 16, count 0 2006.231.07:52:21.88#ibcon#about to read 4, iclass 16, count 0 2006.231.07:52:21.88#ibcon#read 4, iclass 16, count 0 2006.231.07:52:21.88#ibcon#about to read 5, iclass 16, count 0 2006.231.07:52:21.88#ibcon#read 5, iclass 16, count 0 2006.231.07:52:21.88#ibcon#about to read 6, iclass 16, count 0 2006.231.07:52:21.88#ibcon#read 6, iclass 16, count 0 2006.231.07:52:21.88#ibcon#end of sib2, iclass 16, count 0 2006.231.07:52:21.88#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:52:21.88#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:52:21.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:52:21.88#ibcon#*before write, iclass 16, count 0 2006.231.07:52:21.88#ibcon#enter sib2, iclass 16, count 0 2006.231.07:52:21.88#ibcon#flushed, iclass 16, count 0 2006.231.07:52:21.88#ibcon#about to write, iclass 16, count 0 2006.231.07:52:21.88#ibcon#wrote, iclass 16, count 0 2006.231.07:52:21.88#ibcon#about to read 3, iclass 16, count 0 2006.231.07:52:21.92#ibcon#read 3, iclass 16, count 0 2006.231.07:52:21.92#ibcon#about to read 4, iclass 16, count 0 2006.231.07:52:21.92#ibcon#read 4, iclass 16, count 0 2006.231.07:52:21.92#ibcon#about to read 5, iclass 16, count 0 2006.231.07:52:21.92#ibcon#read 5, iclass 16, count 0 2006.231.07:52:21.92#ibcon#about to read 6, iclass 16, count 0 2006.231.07:52:21.92#ibcon#read 6, iclass 16, count 0 2006.231.07:52:21.92#ibcon#end of sib2, iclass 16, count 0 2006.231.07:52:21.92#ibcon#*after write, iclass 16, count 0 2006.231.07:52:21.92#ibcon#*before return 0, iclass 16, count 0 2006.231.07:52:21.92#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:52:21.92#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.07:52:21.92#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:52:21.92#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:52:21.92$vc4f8/vb=5,3 2006.231.07:52:21.92#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.231.07:52:21.92#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.231.07:52:21.92#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:21.92#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:52:21.98#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:52:21.98#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:52:21.98#ibcon#enter wrdev, iclass 18, count 2 2006.231.07:52:21.98#ibcon#first serial, iclass 18, count 2 2006.231.07:52:21.98#ibcon#enter sib2, iclass 18, count 2 2006.231.07:52:21.98#ibcon#flushed, iclass 18, count 2 2006.231.07:52:21.98#ibcon#about to write, iclass 18, count 2 2006.231.07:52:21.98#ibcon#wrote, iclass 18, count 2 2006.231.07:52:21.98#ibcon#about to read 3, iclass 18, count 2 2006.231.07:52:22.00#ibcon#read 3, iclass 18, count 2 2006.231.07:52:22.00#ibcon#about to read 4, iclass 18, count 2 2006.231.07:52:22.00#ibcon#read 4, iclass 18, count 2 2006.231.07:52:22.00#ibcon#about to read 5, iclass 18, count 2 2006.231.07:52:22.00#ibcon#read 5, iclass 18, count 2 2006.231.07:52:22.00#ibcon#about to read 6, iclass 18, count 2 2006.231.07:52:22.00#ibcon#read 6, iclass 18, count 2 2006.231.07:52:22.00#ibcon#end of sib2, iclass 18, count 2 2006.231.07:52:22.00#ibcon#*mode == 0, iclass 18, count 2 2006.231.07:52:22.00#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.231.07:52:22.00#ibcon#[27=AT05-03\r\n] 2006.231.07:52:22.00#ibcon#*before write, iclass 18, count 2 2006.231.07:52:22.00#ibcon#enter sib2, iclass 18, count 2 2006.231.07:52:22.00#ibcon#flushed, iclass 18, count 2 2006.231.07:52:22.00#ibcon#about to write, iclass 18, count 2 2006.231.07:52:22.00#ibcon#wrote, iclass 18, count 2 2006.231.07:52:22.00#ibcon#about to read 3, iclass 18, count 2 2006.231.07:52:22.03#ibcon#read 3, iclass 18, count 2 2006.231.07:52:22.03#ibcon#about to read 4, iclass 18, count 2 2006.231.07:52:22.03#ibcon#read 4, iclass 18, count 2 2006.231.07:52:22.03#ibcon#about to read 5, iclass 18, count 2 2006.231.07:52:22.03#ibcon#read 5, iclass 18, count 2 2006.231.07:52:22.03#ibcon#about to read 6, iclass 18, count 2 2006.231.07:52:22.03#ibcon#read 6, iclass 18, count 2 2006.231.07:52:22.03#ibcon#end of sib2, iclass 18, count 2 2006.231.07:52:22.03#ibcon#*after write, iclass 18, count 2 2006.231.07:52:22.03#ibcon#*before return 0, iclass 18, count 2 2006.231.07:52:22.03#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:52:22.03#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.231.07:52:22.03#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.231.07:52:22.03#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:22.03#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:52:22.15#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:52:22.15#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:52:22.15#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:52:22.15#ibcon#first serial, iclass 18, count 0 2006.231.07:52:22.15#ibcon#enter sib2, iclass 18, count 0 2006.231.07:52:22.15#ibcon#flushed, iclass 18, count 0 2006.231.07:52:22.15#ibcon#about to write, iclass 18, count 0 2006.231.07:52:22.15#ibcon#wrote, iclass 18, count 0 2006.231.07:52:22.15#ibcon#about to read 3, iclass 18, count 0 2006.231.07:52:22.17#ibcon#read 3, iclass 18, count 0 2006.231.07:52:22.17#ibcon#about to read 4, iclass 18, count 0 2006.231.07:52:22.17#ibcon#read 4, iclass 18, count 0 2006.231.07:52:22.17#ibcon#about to read 5, iclass 18, count 0 2006.231.07:52:22.17#ibcon#read 5, iclass 18, count 0 2006.231.07:52:22.17#ibcon#about to read 6, iclass 18, count 0 2006.231.07:52:22.17#ibcon#read 6, iclass 18, count 0 2006.231.07:52:22.17#ibcon#end of sib2, iclass 18, count 0 2006.231.07:52:22.17#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:52:22.17#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:52:22.17#ibcon#[27=USB\r\n] 2006.231.07:52:22.17#ibcon#*before write, iclass 18, count 0 2006.231.07:52:22.17#ibcon#enter sib2, iclass 18, count 0 2006.231.07:52:22.17#ibcon#flushed, iclass 18, count 0 2006.231.07:52:22.17#ibcon#about to write, iclass 18, count 0 2006.231.07:52:22.17#ibcon#wrote, iclass 18, count 0 2006.231.07:52:22.17#ibcon#about to read 3, iclass 18, count 0 2006.231.07:52:22.20#ibcon#read 3, iclass 18, count 0 2006.231.07:52:22.20#ibcon#about to read 4, iclass 18, count 0 2006.231.07:52:22.20#ibcon#read 4, iclass 18, count 0 2006.231.07:52:22.20#ibcon#about to read 5, iclass 18, count 0 2006.231.07:52:22.20#ibcon#read 5, iclass 18, count 0 2006.231.07:52:22.20#ibcon#about to read 6, iclass 18, count 0 2006.231.07:52:22.20#ibcon#read 6, iclass 18, count 0 2006.231.07:52:22.20#ibcon#end of sib2, iclass 18, count 0 2006.231.07:52:22.20#ibcon#*after write, iclass 18, count 0 2006.231.07:52:22.20#ibcon#*before return 0, iclass 18, count 0 2006.231.07:52:22.20#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:52:22.20#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.231.07:52:22.20#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:52:22.20#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:52:22.20$vc4f8/vblo=6,752.99 2006.231.07:52:22.20#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.231.07:52:22.20#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.231.07:52:22.20#ibcon#ireg 17 cls_cnt 0 2006.231.07:52:22.20#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:52:22.20#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:52:22.20#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:52:22.20#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:52:22.20#ibcon#first serial, iclass 20, count 0 2006.231.07:52:22.20#ibcon#enter sib2, iclass 20, count 0 2006.231.07:52:22.20#ibcon#flushed, iclass 20, count 0 2006.231.07:52:22.20#ibcon#about to write, iclass 20, count 0 2006.231.07:52:22.20#ibcon#wrote, iclass 20, count 0 2006.231.07:52:22.20#ibcon#about to read 3, iclass 20, count 0 2006.231.07:52:22.22#ibcon#read 3, iclass 20, count 0 2006.231.07:52:22.22#ibcon#about to read 4, iclass 20, count 0 2006.231.07:52:22.22#ibcon#read 4, iclass 20, count 0 2006.231.07:52:22.22#ibcon#about to read 5, iclass 20, count 0 2006.231.07:52:22.22#ibcon#read 5, iclass 20, count 0 2006.231.07:52:22.22#ibcon#about to read 6, iclass 20, count 0 2006.231.07:52:22.22#ibcon#read 6, iclass 20, count 0 2006.231.07:52:22.22#ibcon#end of sib2, iclass 20, count 0 2006.231.07:52:22.22#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:52:22.22#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:52:22.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:52:22.22#ibcon#*before write, iclass 20, count 0 2006.231.07:52:22.22#ibcon#enter sib2, iclass 20, count 0 2006.231.07:52:22.22#ibcon#flushed, iclass 20, count 0 2006.231.07:52:22.22#ibcon#about to write, iclass 20, count 0 2006.231.07:52:22.22#ibcon#wrote, iclass 20, count 0 2006.231.07:52:22.22#ibcon#about to read 3, iclass 20, count 0 2006.231.07:52:22.26#ibcon#read 3, iclass 20, count 0 2006.231.07:52:22.26#ibcon#about to read 4, iclass 20, count 0 2006.231.07:52:22.26#ibcon#read 4, iclass 20, count 0 2006.231.07:52:22.26#ibcon#about to read 5, iclass 20, count 0 2006.231.07:52:22.26#ibcon#read 5, iclass 20, count 0 2006.231.07:52:22.26#ibcon#about to read 6, iclass 20, count 0 2006.231.07:52:22.26#ibcon#read 6, iclass 20, count 0 2006.231.07:52:22.26#ibcon#end of sib2, iclass 20, count 0 2006.231.07:52:22.26#ibcon#*after write, iclass 20, count 0 2006.231.07:52:22.26#ibcon#*before return 0, iclass 20, count 0 2006.231.07:52:22.26#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:52:22.26#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.231.07:52:22.26#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:52:22.26#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:52:22.26$vc4f8/vb=6,4 2006.231.07:52:22.26#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.231.07:52:22.26#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.231.07:52:22.26#ibcon#ireg 11 cls_cnt 2 2006.231.07:52:22.26#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:52:22.32#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:52:22.32#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:52:22.32#ibcon#enter wrdev, iclass 22, count 2 2006.231.07:52:22.32#ibcon#first serial, iclass 22, count 2 2006.231.07:52:22.32#ibcon#enter sib2, iclass 22, count 2 2006.231.07:52:22.32#ibcon#flushed, iclass 22, count 2 2006.231.07:52:22.32#ibcon#about to write, iclass 22, count 2 2006.231.07:52:22.32#ibcon#wrote, iclass 22, count 2 2006.231.07:52:22.32#ibcon#about to read 3, iclass 22, count 2 2006.231.07:52:22.34#ibcon#read 3, iclass 22, count 2 2006.231.07:52:22.34#ibcon#about to read 4, iclass 22, count 2 2006.231.07:52:22.34#ibcon#read 4, iclass 22, count 2 2006.231.07:52:22.34#ibcon#about to read 5, iclass 22, count 2 2006.231.07:52:22.34#ibcon#read 5, iclass 22, count 2 2006.231.07:52:22.34#ibcon#about to read 6, iclass 22, count 2 2006.231.07:52:22.34#ibcon#read 6, iclass 22, count 2 2006.231.07:52:22.34#ibcon#end of sib2, iclass 22, count 2 2006.231.07:52:22.34#ibcon#*mode == 0, iclass 22, count 2 2006.231.07:52:22.34#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.231.07:52:22.34#ibcon#[27=AT06-04\r\n] 2006.231.07:52:22.34#ibcon#*before write, iclass 22, count 2 2006.231.07:52:22.34#ibcon#enter sib2, iclass 22, count 2 2006.231.07:52:22.34#ibcon#flushed, iclass 22, count 2 2006.231.07:52:22.34#ibcon#about to write, iclass 22, count 2 2006.231.07:52:22.34#ibcon#wrote, iclass 22, count 2 2006.231.07:52:22.34#ibcon#about to read 3, iclass 22, count 2 2006.231.07:52:22.37#ibcon#read 3, iclass 22, count 2 2006.231.07:52:22.37#ibcon#about to read 4, iclass 22, count 2 2006.231.07:52:22.37#ibcon#read 4, iclass 22, count 2 2006.231.07:52:22.37#ibcon#about to read 5, iclass 22, count 2 2006.231.07:52:22.37#ibcon#read 5, iclass 22, count 2 2006.231.07:52:22.37#ibcon#about to read 6, iclass 22, count 2 2006.231.07:52:22.37#ibcon#read 6, iclass 22, count 2 2006.231.07:52:22.37#ibcon#end of sib2, iclass 22, count 2 2006.231.07:52:22.37#ibcon#*after write, iclass 22, count 2 2006.231.07:52:22.37#ibcon#*before return 0, iclass 22, count 2 2006.231.07:52:22.37#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:52:22.37#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.231.07:52:22.37#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.231.07:52:22.37#ibcon#ireg 7 cls_cnt 0 2006.231.07:52:22.37#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:52:22.49#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:52:22.49#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:52:22.49#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:52:22.49#ibcon#first serial, iclass 22, count 0 2006.231.07:52:22.49#ibcon#enter sib2, iclass 22, count 0 2006.231.07:52:22.49#ibcon#flushed, iclass 22, count 0 2006.231.07:52:22.49#ibcon#about to write, iclass 22, count 0 2006.231.07:52:22.49#ibcon#wrote, iclass 22, count 0 2006.231.07:52:22.49#ibcon#about to read 3, iclass 22, count 0 2006.231.07:52:22.51#ibcon#read 3, iclass 22, count 0 2006.231.07:52:22.51#ibcon#about to read 4, iclass 22, count 0 2006.231.07:52:22.51#ibcon#read 4, iclass 22, count 0 2006.231.07:52:22.51#ibcon#about to read 5, iclass 22, count 0 2006.231.07:52:22.51#ibcon#read 5, iclass 22, count 0 2006.231.07:52:22.51#ibcon#about to read 6, iclass 22, count 0 2006.231.07:52:22.51#ibcon#read 6, iclass 22, count 0 2006.231.07:52:22.51#ibcon#end of sib2, iclass 22, count 0 2006.231.07:52:22.51#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:52:22.51#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:52:22.51#ibcon#[27=USB\r\n] 2006.231.07:52:22.51#ibcon#*before write, iclass 22, count 0 2006.231.07:52:22.51#ibcon#enter sib2, iclass 22, count 0 2006.231.07:52:22.51#ibcon#flushed, iclass 22, count 0 2006.231.07:52:22.51#ibcon#about to write, iclass 22, count 0 2006.231.07:52:22.51#ibcon#wrote, iclass 22, count 0 2006.231.07:52:22.51#ibcon#about to read 3, iclass 22, count 0 2006.231.07:52:22.54#ibcon#read 3, iclass 22, count 0 2006.231.07:52:22.54#ibcon#about to read 4, iclass 22, count 0 2006.231.07:52:22.54#ibcon#read 4, iclass 22, count 0 2006.231.07:52:22.54#ibcon#about to read 5, iclass 22, count 0 2006.231.07:52:22.54#ibcon#read 5, iclass 22, count 0 2006.231.07:52:22.54#ibcon#about to read 6, iclass 22, count 0 2006.231.07:52:22.54#ibcon#read 6, iclass 22, count 0 2006.231.07:52:22.54#ibcon#end of sib2, iclass 22, count 0 2006.231.07:52:22.54#ibcon#*after write, iclass 22, count 0 2006.231.07:52:22.54#ibcon#*before return 0, iclass 22, count 0 2006.231.07:52:22.54#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:52:22.54#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.231.07:52:22.54#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:52:22.54#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:52:22.54$vc4f8/vabw=wide 2006.231.07:52:22.54#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.231.07:52:22.54#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.231.07:52:22.54#ibcon#ireg 8 cls_cnt 0 2006.231.07:52:22.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:52:22.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:52:22.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:52:22.54#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:52:22.54#ibcon#first serial, iclass 24, count 0 2006.231.07:52:22.54#ibcon#enter sib2, iclass 24, count 0 2006.231.07:52:22.54#ibcon#flushed, iclass 24, count 0 2006.231.07:52:22.54#ibcon#about to write, iclass 24, count 0 2006.231.07:52:22.54#ibcon#wrote, iclass 24, count 0 2006.231.07:52:22.54#ibcon#about to read 3, iclass 24, count 0 2006.231.07:52:22.56#ibcon#read 3, iclass 24, count 0 2006.231.07:52:22.56#ibcon#about to read 4, iclass 24, count 0 2006.231.07:52:22.56#ibcon#read 4, iclass 24, count 0 2006.231.07:52:22.56#ibcon#about to read 5, iclass 24, count 0 2006.231.07:52:22.56#ibcon#read 5, iclass 24, count 0 2006.231.07:52:22.56#ibcon#about to read 6, iclass 24, count 0 2006.231.07:52:22.56#ibcon#read 6, iclass 24, count 0 2006.231.07:52:22.56#ibcon#end of sib2, iclass 24, count 0 2006.231.07:52:22.56#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:52:22.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:52:22.56#ibcon#[25=BW32\r\n] 2006.231.07:52:22.56#ibcon#*before write, iclass 24, count 0 2006.231.07:52:22.56#ibcon#enter sib2, iclass 24, count 0 2006.231.07:52:22.56#ibcon#flushed, iclass 24, count 0 2006.231.07:52:22.56#ibcon#about to write, iclass 24, count 0 2006.231.07:52:22.56#ibcon#wrote, iclass 24, count 0 2006.231.07:52:22.56#ibcon#about to read 3, iclass 24, count 0 2006.231.07:52:22.59#ibcon#read 3, iclass 24, count 0 2006.231.07:52:22.59#ibcon#about to read 4, iclass 24, count 0 2006.231.07:52:22.59#ibcon#read 4, iclass 24, count 0 2006.231.07:52:22.59#ibcon#about to read 5, iclass 24, count 0 2006.231.07:52:22.59#ibcon#read 5, iclass 24, count 0 2006.231.07:52:22.59#ibcon#about to read 6, iclass 24, count 0 2006.231.07:52:22.59#ibcon#read 6, iclass 24, count 0 2006.231.07:52:22.59#ibcon#end of sib2, iclass 24, count 0 2006.231.07:52:22.59#ibcon#*after write, iclass 24, count 0 2006.231.07:52:22.59#ibcon#*before return 0, iclass 24, count 0 2006.231.07:52:22.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:52:22.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.231.07:52:22.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:52:22.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:52:22.59$vc4f8/vbbw=wide 2006.231.07:52:22.59#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:52:22.59#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:52:22.59#ibcon#ireg 8 cls_cnt 0 2006.231.07:52:22.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:52:22.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:52:22.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:52:22.66#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:52:22.66#ibcon#first serial, iclass 26, count 0 2006.231.07:52:22.66#ibcon#enter sib2, iclass 26, count 0 2006.231.07:52:22.66#ibcon#flushed, iclass 26, count 0 2006.231.07:52:22.66#ibcon#about to write, iclass 26, count 0 2006.231.07:52:22.66#ibcon#wrote, iclass 26, count 0 2006.231.07:52:22.66#ibcon#about to read 3, iclass 26, count 0 2006.231.07:52:22.68#ibcon#read 3, iclass 26, count 0 2006.231.07:52:22.68#ibcon#about to read 4, iclass 26, count 0 2006.231.07:52:22.68#ibcon#read 4, iclass 26, count 0 2006.231.07:52:22.68#ibcon#about to read 5, iclass 26, count 0 2006.231.07:52:22.68#ibcon#read 5, iclass 26, count 0 2006.231.07:52:22.68#ibcon#about to read 6, iclass 26, count 0 2006.231.07:52:22.68#ibcon#read 6, iclass 26, count 0 2006.231.07:52:22.68#ibcon#end of sib2, iclass 26, count 0 2006.231.07:52:22.68#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:52:22.68#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:52:22.68#ibcon#[27=BW32\r\n] 2006.231.07:52:22.68#ibcon#*before write, iclass 26, count 0 2006.231.07:52:22.68#ibcon#enter sib2, iclass 26, count 0 2006.231.07:52:22.68#ibcon#flushed, iclass 26, count 0 2006.231.07:52:22.68#ibcon#about to write, iclass 26, count 0 2006.231.07:52:22.68#ibcon#wrote, iclass 26, count 0 2006.231.07:52:22.68#ibcon#about to read 3, iclass 26, count 0 2006.231.07:52:22.71#ibcon#read 3, iclass 26, count 0 2006.231.07:52:22.71#ibcon#about to read 4, iclass 26, count 0 2006.231.07:52:22.71#ibcon#read 4, iclass 26, count 0 2006.231.07:52:22.71#ibcon#about to read 5, iclass 26, count 0 2006.231.07:52:22.71#ibcon#read 5, iclass 26, count 0 2006.231.07:52:22.71#ibcon#about to read 6, iclass 26, count 0 2006.231.07:52:22.71#ibcon#read 6, iclass 26, count 0 2006.231.07:52:22.71#ibcon#end of sib2, iclass 26, count 0 2006.231.07:52:22.71#ibcon#*after write, iclass 26, count 0 2006.231.07:52:22.71#ibcon#*before return 0, iclass 26, count 0 2006.231.07:52:22.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:52:22.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:52:22.71#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:52:22.71#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:52:22.71$4f8m12a/ifd4f 2006.231.07:52:22.71$ifd4f/lo= 2006.231.07:52:22.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:52:22.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:52:22.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:52:22.71$ifd4f/patch= 2006.231.07:52:22.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:52:22.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:52:22.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:52:22.71$4f8m12a/"form=m,16.000,1:2 2006.231.07:52:22.71$4f8m12a/"tpicd 2006.231.07:52:22.71$4f8m12a/echo=off 2006.231.07:52:22.71$4f8m12a/xlog=off 2006.231.07:52:22.71:!2006.231.07:52:50 2006.231.07:52:30.13#trakl#Source acquired 2006.231.07:52:32.13#flagr#flagr/antenna,acquired 2006.231.07:52:50.00:preob 2006.231.07:52:51.13/onsource/TRACKING 2006.231.07:52:51.13:!2006.231.07:53:00 2006.231.07:53:00.00:data_valid=on 2006.231.07:53:00.00:midob 2006.231.07:53:00.13/onsource/TRACKING 2006.231.07:53:00.13/wx/30.56,1004.4,85 2006.231.07:53:00.34/cable/+6.3709E-03 2006.231.07:53:01.43/va/01,08,usb,yes,29,31 2006.231.07:53:01.43/va/02,07,usb,yes,29,31 2006.231.07:53:01.43/va/03,08,usb,yes,22,22 2006.231.07:53:01.43/va/04,07,usb,yes,31,33 2006.231.07:53:01.43/va/05,07,usb,yes,34,35 2006.231.07:53:01.43/va/06,06,usb,yes,33,33 2006.231.07:53:01.43/va/07,06,usb,yes,34,33 2006.231.07:53:01.43/va/08,06,usb,yes,36,35 2006.231.07:53:01.66/valo/01,532.99,yes,locked 2006.231.07:53:01.66/valo/02,572.99,yes,locked 2006.231.07:53:01.66/valo/03,672.99,yes,locked 2006.231.07:53:01.66/valo/04,832.99,yes,locked 2006.231.07:53:01.66/valo/05,652.99,yes,locked 2006.231.07:53:01.66/valo/06,772.99,yes,locked 2006.231.07:53:01.66/valo/07,832.99,yes,locked 2006.231.07:53:01.66/valo/08,852.99,yes,locked 2006.231.07:53:02.75/vb/01,04,usb,yes,30,29 2006.231.07:53:02.75/vb/02,04,usb,yes,32,33 2006.231.07:53:02.75/vb/03,04,usb,yes,28,32 2006.231.07:53:02.75/vb/04,04,usb,yes,29,29 2006.231.07:53:02.75/vb/05,03,usb,yes,35,39 2006.231.07:53:02.75/vb/06,04,usb,yes,28,31 2006.231.07:53:02.75/vb/07,04,usb,yes,31,31 2006.231.07:53:02.75/vb/08,04,usb,yes,28,32 2006.231.07:53:02.98/vblo/01,632.99,yes,locked 2006.231.07:53:02.98/vblo/02,640.99,yes,locked 2006.231.07:53:02.98/vblo/03,656.99,yes,locked 2006.231.07:53:02.98/vblo/04,712.99,yes,locked 2006.231.07:53:02.98/vblo/05,744.99,yes,locked 2006.231.07:53:02.98/vblo/06,752.99,yes,locked 2006.231.07:53:02.98/vblo/07,734.99,yes,locked 2006.231.07:53:02.98/vblo/08,744.99,yes,locked 2006.231.07:53:03.13/vabw/8 2006.231.07:53:03.28/vbbw/8 2006.231.07:53:03.39/xfe/off,on,12.5 2006.231.07:53:03.76/ifatt/23,28,28,28 2006.231.07:53:04.08/fmout-gps/S +4.46E-07 2006.231.07:53:04.12:!2006.231.07:54:00 2006.231.07:54:00.00:data_valid=off 2006.231.07:54:00.00:postob 2006.231.07:54:00.18/cable/+6.3709E-03 2006.231.07:54:00.18/wx/30.56,1004.4,86 2006.231.07:54:01.08/fmout-gps/S +4.47E-07 2006.231.07:54:01.08:scan_name=231-0755,k06231,60 2006.231.07:54:01.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.231.07:54:01.14#flagr#flagr/antenna,new-source 2006.231.07:54:02.14:checkk5 2006.231.07:54:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:54:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:54:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:54:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:54:04.01/chk_obsdata//k5ts1/T2310753??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:54:04.38/chk_obsdata//k5ts2/T2310753??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:54:04.75/chk_obsdata//k5ts3/T2310753??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:54:05.12/chk_obsdata//k5ts4/T2310753??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:54:05.81/k5log//k5ts1_log_newline 2006.231.07:54:06.50/k5log//k5ts2_log_newline 2006.231.07:54:07.18/k5log//k5ts3_log_newline 2006.231.07:54:07.87/k5log//k5ts4_log_newline 2006.231.07:54:07.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:54:07.89:4f8m12a=2 2006.231.07:54:07.89$4f8m12a/echo=on 2006.231.07:54:07.89$4f8m12a/pcalon 2006.231.07:54:07.89$pcalon/"no phase cal control is implemented here 2006.231.07:54:07.89$4f8m12a/"tpicd=stop 2006.231.07:54:07.89$4f8m12a/vc4f8 2006.231.07:54:07.89$vc4f8/valo=1,532.99 2006.231.07:54:07.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.07:54:07.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.07:54:07.90#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:07.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:54:07.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:54:07.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:54:07.90#ibcon#enter wrdev, iclass 33, count 0 2006.231.07:54:07.90#ibcon#first serial, iclass 33, count 0 2006.231.07:54:07.90#ibcon#enter sib2, iclass 33, count 0 2006.231.07:54:07.90#ibcon#flushed, iclass 33, count 0 2006.231.07:54:07.90#ibcon#about to write, iclass 33, count 0 2006.231.07:54:07.90#ibcon#wrote, iclass 33, count 0 2006.231.07:54:07.90#ibcon#about to read 3, iclass 33, count 0 2006.231.07:54:07.94#ibcon#read 3, iclass 33, count 0 2006.231.07:54:07.94#ibcon#about to read 4, iclass 33, count 0 2006.231.07:54:07.94#ibcon#read 4, iclass 33, count 0 2006.231.07:54:07.94#ibcon#about to read 5, iclass 33, count 0 2006.231.07:54:07.94#ibcon#read 5, iclass 33, count 0 2006.231.07:54:07.94#ibcon#about to read 6, iclass 33, count 0 2006.231.07:54:07.94#ibcon#read 6, iclass 33, count 0 2006.231.07:54:07.94#ibcon#end of sib2, iclass 33, count 0 2006.231.07:54:07.94#ibcon#*mode == 0, iclass 33, count 0 2006.231.07:54:07.94#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.07:54:07.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:54:07.94#ibcon#*before write, iclass 33, count 0 2006.231.07:54:07.94#ibcon#enter sib2, iclass 33, count 0 2006.231.07:54:07.94#ibcon#flushed, iclass 33, count 0 2006.231.07:54:07.94#ibcon#about to write, iclass 33, count 0 2006.231.07:54:07.94#ibcon#wrote, iclass 33, count 0 2006.231.07:54:07.94#ibcon#about to read 3, iclass 33, count 0 2006.231.07:54:07.99#ibcon#read 3, iclass 33, count 0 2006.231.07:54:07.99#ibcon#about to read 4, iclass 33, count 0 2006.231.07:54:07.99#ibcon#read 4, iclass 33, count 0 2006.231.07:54:07.99#ibcon#about to read 5, iclass 33, count 0 2006.231.07:54:07.99#ibcon#read 5, iclass 33, count 0 2006.231.07:54:07.99#ibcon#about to read 6, iclass 33, count 0 2006.231.07:54:07.99#ibcon#read 6, iclass 33, count 0 2006.231.07:54:07.99#ibcon#end of sib2, iclass 33, count 0 2006.231.07:54:07.99#ibcon#*after write, iclass 33, count 0 2006.231.07:54:07.99#ibcon#*before return 0, iclass 33, count 0 2006.231.07:54:07.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:54:07.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:54:07.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.07:54:07.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.07:54:07.99$vc4f8/va=1,8 2006.231.07:54:07.99#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.07:54:07.99#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.07:54:07.99#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:07.99#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:54:07.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:54:07.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:54:07.99#ibcon#enter wrdev, iclass 35, count 2 2006.231.07:54:07.99#ibcon#first serial, iclass 35, count 2 2006.231.07:54:07.99#ibcon#enter sib2, iclass 35, count 2 2006.231.07:54:07.99#ibcon#flushed, iclass 35, count 2 2006.231.07:54:07.99#ibcon#about to write, iclass 35, count 2 2006.231.07:54:07.99#ibcon#wrote, iclass 35, count 2 2006.231.07:54:07.99#ibcon#about to read 3, iclass 35, count 2 2006.231.07:54:08.02#ibcon#read 3, iclass 35, count 2 2006.231.07:54:08.02#ibcon#about to read 4, iclass 35, count 2 2006.231.07:54:08.02#ibcon#read 4, iclass 35, count 2 2006.231.07:54:08.02#ibcon#about to read 5, iclass 35, count 2 2006.231.07:54:08.02#ibcon#read 5, iclass 35, count 2 2006.231.07:54:08.02#ibcon#about to read 6, iclass 35, count 2 2006.231.07:54:08.02#ibcon#read 6, iclass 35, count 2 2006.231.07:54:08.02#ibcon#end of sib2, iclass 35, count 2 2006.231.07:54:08.02#ibcon#*mode == 0, iclass 35, count 2 2006.231.07:54:08.02#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.07:54:08.02#ibcon#[25=AT01-08\r\n] 2006.231.07:54:08.02#ibcon#*before write, iclass 35, count 2 2006.231.07:54:08.02#ibcon#enter sib2, iclass 35, count 2 2006.231.07:54:08.02#ibcon#flushed, iclass 35, count 2 2006.231.07:54:08.02#ibcon#about to write, iclass 35, count 2 2006.231.07:54:08.02#ibcon#wrote, iclass 35, count 2 2006.231.07:54:08.02#ibcon#about to read 3, iclass 35, count 2 2006.231.07:54:08.05#ibcon#read 3, iclass 35, count 2 2006.231.07:54:08.05#ibcon#about to read 4, iclass 35, count 2 2006.231.07:54:08.05#ibcon#read 4, iclass 35, count 2 2006.231.07:54:08.05#ibcon#about to read 5, iclass 35, count 2 2006.231.07:54:08.05#ibcon#read 5, iclass 35, count 2 2006.231.07:54:08.05#ibcon#about to read 6, iclass 35, count 2 2006.231.07:54:08.05#ibcon#read 6, iclass 35, count 2 2006.231.07:54:08.05#ibcon#end of sib2, iclass 35, count 2 2006.231.07:54:08.05#ibcon#*after write, iclass 35, count 2 2006.231.07:54:08.05#ibcon#*before return 0, iclass 35, count 2 2006.231.07:54:08.05#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:54:08.05#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:54:08.05#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.07:54:08.05#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:08.05#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:54:08.17#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:54:08.17#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:54:08.17#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:54:08.17#ibcon#first serial, iclass 35, count 0 2006.231.07:54:08.17#ibcon#enter sib2, iclass 35, count 0 2006.231.07:54:08.17#ibcon#flushed, iclass 35, count 0 2006.231.07:54:08.17#ibcon#about to write, iclass 35, count 0 2006.231.07:54:08.17#ibcon#wrote, iclass 35, count 0 2006.231.07:54:08.17#ibcon#about to read 3, iclass 35, count 0 2006.231.07:54:08.19#ibcon#read 3, iclass 35, count 0 2006.231.07:54:08.19#ibcon#about to read 4, iclass 35, count 0 2006.231.07:54:08.19#ibcon#read 4, iclass 35, count 0 2006.231.07:54:08.19#ibcon#about to read 5, iclass 35, count 0 2006.231.07:54:08.19#ibcon#read 5, iclass 35, count 0 2006.231.07:54:08.19#ibcon#about to read 6, iclass 35, count 0 2006.231.07:54:08.19#ibcon#read 6, iclass 35, count 0 2006.231.07:54:08.19#ibcon#end of sib2, iclass 35, count 0 2006.231.07:54:08.19#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:54:08.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:54:08.19#ibcon#[25=USB\r\n] 2006.231.07:54:08.19#ibcon#*before write, iclass 35, count 0 2006.231.07:54:08.19#ibcon#enter sib2, iclass 35, count 0 2006.231.07:54:08.19#ibcon#flushed, iclass 35, count 0 2006.231.07:54:08.19#ibcon#about to write, iclass 35, count 0 2006.231.07:54:08.19#ibcon#wrote, iclass 35, count 0 2006.231.07:54:08.19#ibcon#about to read 3, iclass 35, count 0 2006.231.07:54:08.22#ibcon#read 3, iclass 35, count 0 2006.231.07:54:08.22#ibcon#about to read 4, iclass 35, count 0 2006.231.07:54:08.22#ibcon#read 4, iclass 35, count 0 2006.231.07:54:08.22#ibcon#about to read 5, iclass 35, count 0 2006.231.07:54:08.22#ibcon#read 5, iclass 35, count 0 2006.231.07:54:08.22#ibcon#about to read 6, iclass 35, count 0 2006.231.07:54:08.22#ibcon#read 6, iclass 35, count 0 2006.231.07:54:08.22#ibcon#end of sib2, iclass 35, count 0 2006.231.07:54:08.22#ibcon#*after write, iclass 35, count 0 2006.231.07:54:08.22#ibcon#*before return 0, iclass 35, count 0 2006.231.07:54:08.22#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:54:08.22#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:54:08.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:54:08.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:54:08.22$vc4f8/valo=2,572.99 2006.231.07:54:08.22#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.07:54:08.22#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.07:54:08.22#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:08.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:54:08.22#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:54:08.22#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:54:08.22#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:54:08.22#ibcon#first serial, iclass 37, count 0 2006.231.07:54:08.22#ibcon#enter sib2, iclass 37, count 0 2006.231.07:54:08.22#ibcon#flushed, iclass 37, count 0 2006.231.07:54:08.22#ibcon#about to write, iclass 37, count 0 2006.231.07:54:08.22#ibcon#wrote, iclass 37, count 0 2006.231.07:54:08.22#ibcon#about to read 3, iclass 37, count 0 2006.231.07:54:08.24#ibcon#read 3, iclass 37, count 0 2006.231.07:54:08.24#ibcon#about to read 4, iclass 37, count 0 2006.231.07:54:08.24#ibcon#read 4, iclass 37, count 0 2006.231.07:54:08.24#ibcon#about to read 5, iclass 37, count 0 2006.231.07:54:08.24#ibcon#read 5, iclass 37, count 0 2006.231.07:54:08.24#ibcon#about to read 6, iclass 37, count 0 2006.231.07:54:08.24#ibcon#read 6, iclass 37, count 0 2006.231.07:54:08.24#ibcon#end of sib2, iclass 37, count 0 2006.231.07:54:08.24#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:54:08.24#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:54:08.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:54:08.24#ibcon#*before write, iclass 37, count 0 2006.231.07:54:08.24#ibcon#enter sib2, iclass 37, count 0 2006.231.07:54:08.24#ibcon#flushed, iclass 37, count 0 2006.231.07:54:08.24#ibcon#about to write, iclass 37, count 0 2006.231.07:54:08.24#ibcon#wrote, iclass 37, count 0 2006.231.07:54:08.24#ibcon#about to read 3, iclass 37, count 0 2006.231.07:54:08.28#ibcon#read 3, iclass 37, count 0 2006.231.07:54:08.28#ibcon#about to read 4, iclass 37, count 0 2006.231.07:54:08.28#ibcon#read 4, iclass 37, count 0 2006.231.07:54:08.28#ibcon#about to read 5, iclass 37, count 0 2006.231.07:54:08.28#ibcon#read 5, iclass 37, count 0 2006.231.07:54:08.28#ibcon#about to read 6, iclass 37, count 0 2006.231.07:54:08.28#ibcon#read 6, iclass 37, count 0 2006.231.07:54:08.28#ibcon#end of sib2, iclass 37, count 0 2006.231.07:54:08.28#ibcon#*after write, iclass 37, count 0 2006.231.07:54:08.28#ibcon#*before return 0, iclass 37, count 0 2006.231.07:54:08.28#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:54:08.28#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:54:08.28#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:54:08.28#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:54:08.28$vc4f8/va=2,7 2006.231.07:54:08.28#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.07:54:08.28#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.07:54:08.28#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:08.28#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:54:08.34#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:54:08.34#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:54:08.34#ibcon#enter wrdev, iclass 39, count 2 2006.231.07:54:08.34#ibcon#first serial, iclass 39, count 2 2006.231.07:54:08.34#ibcon#enter sib2, iclass 39, count 2 2006.231.07:54:08.34#ibcon#flushed, iclass 39, count 2 2006.231.07:54:08.34#ibcon#about to write, iclass 39, count 2 2006.231.07:54:08.34#ibcon#wrote, iclass 39, count 2 2006.231.07:54:08.34#ibcon#about to read 3, iclass 39, count 2 2006.231.07:54:08.36#ibcon#read 3, iclass 39, count 2 2006.231.07:54:08.36#ibcon#about to read 4, iclass 39, count 2 2006.231.07:54:08.36#ibcon#read 4, iclass 39, count 2 2006.231.07:54:08.36#ibcon#about to read 5, iclass 39, count 2 2006.231.07:54:08.36#ibcon#read 5, iclass 39, count 2 2006.231.07:54:08.36#ibcon#about to read 6, iclass 39, count 2 2006.231.07:54:08.36#ibcon#read 6, iclass 39, count 2 2006.231.07:54:08.36#ibcon#end of sib2, iclass 39, count 2 2006.231.07:54:08.36#ibcon#*mode == 0, iclass 39, count 2 2006.231.07:54:08.36#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.07:54:08.36#ibcon#[25=AT02-07\r\n] 2006.231.07:54:08.36#ibcon#*before write, iclass 39, count 2 2006.231.07:54:08.36#ibcon#enter sib2, iclass 39, count 2 2006.231.07:54:08.36#ibcon#flushed, iclass 39, count 2 2006.231.07:54:08.36#ibcon#about to write, iclass 39, count 2 2006.231.07:54:08.36#ibcon#wrote, iclass 39, count 2 2006.231.07:54:08.36#ibcon#about to read 3, iclass 39, count 2 2006.231.07:54:08.39#ibcon#read 3, iclass 39, count 2 2006.231.07:54:08.39#ibcon#about to read 4, iclass 39, count 2 2006.231.07:54:08.39#ibcon#read 4, iclass 39, count 2 2006.231.07:54:08.39#ibcon#about to read 5, iclass 39, count 2 2006.231.07:54:08.39#ibcon#read 5, iclass 39, count 2 2006.231.07:54:08.39#ibcon#about to read 6, iclass 39, count 2 2006.231.07:54:08.39#ibcon#read 6, iclass 39, count 2 2006.231.07:54:08.39#ibcon#end of sib2, iclass 39, count 2 2006.231.07:54:08.39#ibcon#*after write, iclass 39, count 2 2006.231.07:54:08.39#ibcon#*before return 0, iclass 39, count 2 2006.231.07:54:08.39#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:54:08.39#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:54:08.39#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.07:54:08.39#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:08.39#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:54:08.51#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:54:08.51#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:54:08.51#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:54:08.51#ibcon#first serial, iclass 39, count 0 2006.231.07:54:08.51#ibcon#enter sib2, iclass 39, count 0 2006.231.07:54:08.51#ibcon#flushed, iclass 39, count 0 2006.231.07:54:08.51#ibcon#about to write, iclass 39, count 0 2006.231.07:54:08.51#ibcon#wrote, iclass 39, count 0 2006.231.07:54:08.51#ibcon#about to read 3, iclass 39, count 0 2006.231.07:54:08.53#ibcon#read 3, iclass 39, count 0 2006.231.07:54:08.53#ibcon#about to read 4, iclass 39, count 0 2006.231.07:54:08.53#ibcon#read 4, iclass 39, count 0 2006.231.07:54:08.53#ibcon#about to read 5, iclass 39, count 0 2006.231.07:54:08.53#ibcon#read 5, iclass 39, count 0 2006.231.07:54:08.53#ibcon#about to read 6, iclass 39, count 0 2006.231.07:54:08.53#ibcon#read 6, iclass 39, count 0 2006.231.07:54:08.53#ibcon#end of sib2, iclass 39, count 0 2006.231.07:54:08.53#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:54:08.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:54:08.53#ibcon#[25=USB\r\n] 2006.231.07:54:08.53#ibcon#*before write, iclass 39, count 0 2006.231.07:54:08.53#ibcon#enter sib2, iclass 39, count 0 2006.231.07:54:08.53#ibcon#flushed, iclass 39, count 0 2006.231.07:54:08.53#ibcon#about to write, iclass 39, count 0 2006.231.07:54:08.53#ibcon#wrote, iclass 39, count 0 2006.231.07:54:08.53#ibcon#about to read 3, iclass 39, count 0 2006.231.07:54:08.56#ibcon#read 3, iclass 39, count 0 2006.231.07:54:08.56#ibcon#about to read 4, iclass 39, count 0 2006.231.07:54:08.56#ibcon#read 4, iclass 39, count 0 2006.231.07:54:08.56#ibcon#about to read 5, iclass 39, count 0 2006.231.07:54:08.56#ibcon#read 5, iclass 39, count 0 2006.231.07:54:08.56#ibcon#about to read 6, iclass 39, count 0 2006.231.07:54:08.56#ibcon#read 6, iclass 39, count 0 2006.231.07:54:08.56#ibcon#end of sib2, iclass 39, count 0 2006.231.07:54:08.56#ibcon#*after write, iclass 39, count 0 2006.231.07:54:08.56#ibcon#*before return 0, iclass 39, count 0 2006.231.07:54:08.56#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:54:08.56#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:54:08.56#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:54:08.56#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:54:08.56$vc4f8/valo=3,672.99 2006.231.07:54:08.56#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.07:54:08.56#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.07:54:08.56#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:08.56#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:54:08.56#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:54:08.56#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:54:08.56#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:54:08.56#ibcon#first serial, iclass 3, count 0 2006.231.07:54:08.56#ibcon#enter sib2, iclass 3, count 0 2006.231.07:54:08.56#ibcon#flushed, iclass 3, count 0 2006.231.07:54:08.56#ibcon#about to write, iclass 3, count 0 2006.231.07:54:08.56#ibcon#wrote, iclass 3, count 0 2006.231.07:54:08.56#ibcon#about to read 3, iclass 3, count 0 2006.231.07:54:08.58#ibcon#read 3, iclass 3, count 0 2006.231.07:54:08.58#ibcon#about to read 4, iclass 3, count 0 2006.231.07:54:08.58#ibcon#read 4, iclass 3, count 0 2006.231.07:54:08.58#ibcon#about to read 5, iclass 3, count 0 2006.231.07:54:08.58#ibcon#read 5, iclass 3, count 0 2006.231.07:54:08.58#ibcon#about to read 6, iclass 3, count 0 2006.231.07:54:08.58#ibcon#read 6, iclass 3, count 0 2006.231.07:54:08.58#ibcon#end of sib2, iclass 3, count 0 2006.231.07:54:08.58#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:54:08.58#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:54:08.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:54:08.58#ibcon#*before write, iclass 3, count 0 2006.231.07:54:08.58#ibcon#enter sib2, iclass 3, count 0 2006.231.07:54:08.58#ibcon#flushed, iclass 3, count 0 2006.231.07:54:08.58#ibcon#about to write, iclass 3, count 0 2006.231.07:54:08.58#ibcon#wrote, iclass 3, count 0 2006.231.07:54:08.58#ibcon#about to read 3, iclass 3, count 0 2006.231.07:54:08.63#ibcon#read 3, iclass 3, count 0 2006.231.07:54:08.63#ibcon#about to read 4, iclass 3, count 0 2006.231.07:54:08.63#ibcon#read 4, iclass 3, count 0 2006.231.07:54:08.63#ibcon#about to read 5, iclass 3, count 0 2006.231.07:54:08.63#ibcon#read 5, iclass 3, count 0 2006.231.07:54:08.63#ibcon#about to read 6, iclass 3, count 0 2006.231.07:54:08.63#ibcon#read 6, iclass 3, count 0 2006.231.07:54:08.63#ibcon#end of sib2, iclass 3, count 0 2006.231.07:54:08.63#ibcon#*after write, iclass 3, count 0 2006.231.07:54:08.63#ibcon#*before return 0, iclass 3, count 0 2006.231.07:54:08.63#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:54:08.63#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:54:08.63#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:54:08.63#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:54:08.63$vc4f8/va=3,8 2006.231.07:54:08.63#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.07:54:08.63#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.07:54:08.63#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:08.63#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:54:08.68#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:54:08.68#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:54:08.68#ibcon#enter wrdev, iclass 5, count 2 2006.231.07:54:08.68#ibcon#first serial, iclass 5, count 2 2006.231.07:54:08.68#ibcon#enter sib2, iclass 5, count 2 2006.231.07:54:08.68#ibcon#flushed, iclass 5, count 2 2006.231.07:54:08.68#ibcon#about to write, iclass 5, count 2 2006.231.07:54:08.68#ibcon#wrote, iclass 5, count 2 2006.231.07:54:08.68#ibcon#about to read 3, iclass 5, count 2 2006.231.07:54:08.70#ibcon#read 3, iclass 5, count 2 2006.231.07:54:08.70#ibcon#about to read 4, iclass 5, count 2 2006.231.07:54:08.70#ibcon#read 4, iclass 5, count 2 2006.231.07:54:08.70#ibcon#about to read 5, iclass 5, count 2 2006.231.07:54:08.70#ibcon#read 5, iclass 5, count 2 2006.231.07:54:08.70#ibcon#about to read 6, iclass 5, count 2 2006.231.07:54:08.70#ibcon#read 6, iclass 5, count 2 2006.231.07:54:08.70#ibcon#end of sib2, iclass 5, count 2 2006.231.07:54:08.70#ibcon#*mode == 0, iclass 5, count 2 2006.231.07:54:08.70#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.07:54:08.70#ibcon#[25=AT03-08\r\n] 2006.231.07:54:08.70#ibcon#*before write, iclass 5, count 2 2006.231.07:54:08.70#ibcon#enter sib2, iclass 5, count 2 2006.231.07:54:08.70#ibcon#flushed, iclass 5, count 2 2006.231.07:54:08.70#ibcon#about to write, iclass 5, count 2 2006.231.07:54:08.70#ibcon#wrote, iclass 5, count 2 2006.231.07:54:08.70#ibcon#about to read 3, iclass 5, count 2 2006.231.07:54:08.74#ibcon#read 3, iclass 5, count 2 2006.231.07:54:08.74#ibcon#about to read 4, iclass 5, count 2 2006.231.07:54:08.74#ibcon#read 4, iclass 5, count 2 2006.231.07:54:08.74#ibcon#about to read 5, iclass 5, count 2 2006.231.07:54:08.74#ibcon#read 5, iclass 5, count 2 2006.231.07:54:08.74#ibcon#about to read 6, iclass 5, count 2 2006.231.07:54:08.74#ibcon#read 6, iclass 5, count 2 2006.231.07:54:08.74#ibcon#end of sib2, iclass 5, count 2 2006.231.07:54:08.74#ibcon#*after write, iclass 5, count 2 2006.231.07:54:08.74#ibcon#*before return 0, iclass 5, count 2 2006.231.07:54:08.74#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:54:08.74#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:54:08.74#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.07:54:08.74#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:08.74#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:54:08.86#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:54:08.86#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:54:08.86#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:54:08.86#ibcon#first serial, iclass 5, count 0 2006.231.07:54:08.86#ibcon#enter sib2, iclass 5, count 0 2006.231.07:54:08.86#ibcon#flushed, iclass 5, count 0 2006.231.07:54:08.86#ibcon#about to write, iclass 5, count 0 2006.231.07:54:08.86#ibcon#wrote, iclass 5, count 0 2006.231.07:54:08.86#ibcon#about to read 3, iclass 5, count 0 2006.231.07:54:08.88#ibcon#read 3, iclass 5, count 0 2006.231.07:54:08.88#ibcon#about to read 4, iclass 5, count 0 2006.231.07:54:08.88#ibcon#read 4, iclass 5, count 0 2006.231.07:54:08.88#ibcon#about to read 5, iclass 5, count 0 2006.231.07:54:08.88#ibcon#read 5, iclass 5, count 0 2006.231.07:54:08.88#ibcon#about to read 6, iclass 5, count 0 2006.231.07:54:08.88#ibcon#read 6, iclass 5, count 0 2006.231.07:54:08.88#ibcon#end of sib2, iclass 5, count 0 2006.231.07:54:08.88#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:54:08.88#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:54:08.88#ibcon#[25=USB\r\n] 2006.231.07:54:08.88#ibcon#*before write, iclass 5, count 0 2006.231.07:54:08.88#ibcon#enter sib2, iclass 5, count 0 2006.231.07:54:08.88#ibcon#flushed, iclass 5, count 0 2006.231.07:54:08.88#ibcon#about to write, iclass 5, count 0 2006.231.07:54:08.88#ibcon#wrote, iclass 5, count 0 2006.231.07:54:08.88#ibcon#about to read 3, iclass 5, count 0 2006.231.07:54:08.91#ibcon#read 3, iclass 5, count 0 2006.231.07:54:08.91#ibcon#about to read 4, iclass 5, count 0 2006.231.07:54:08.91#ibcon#read 4, iclass 5, count 0 2006.231.07:54:08.91#ibcon#about to read 5, iclass 5, count 0 2006.231.07:54:08.91#ibcon#read 5, iclass 5, count 0 2006.231.07:54:08.91#ibcon#about to read 6, iclass 5, count 0 2006.231.07:54:08.91#ibcon#read 6, iclass 5, count 0 2006.231.07:54:08.91#ibcon#end of sib2, iclass 5, count 0 2006.231.07:54:08.91#ibcon#*after write, iclass 5, count 0 2006.231.07:54:08.91#ibcon#*before return 0, iclass 5, count 0 2006.231.07:54:08.91#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:54:08.91#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:54:08.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:54:08.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:54:08.91$vc4f8/valo=4,832.99 2006.231.07:54:08.91#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.07:54:08.91#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.07:54:08.91#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:08.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:54:08.91#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:54:08.91#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:54:08.91#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:54:08.91#ibcon#first serial, iclass 7, count 0 2006.231.07:54:08.91#ibcon#enter sib2, iclass 7, count 0 2006.231.07:54:08.91#ibcon#flushed, iclass 7, count 0 2006.231.07:54:08.91#ibcon#about to write, iclass 7, count 0 2006.231.07:54:08.91#ibcon#wrote, iclass 7, count 0 2006.231.07:54:08.91#ibcon#about to read 3, iclass 7, count 0 2006.231.07:54:08.93#ibcon#read 3, iclass 7, count 0 2006.231.07:54:08.93#ibcon#about to read 4, iclass 7, count 0 2006.231.07:54:08.93#ibcon#read 4, iclass 7, count 0 2006.231.07:54:08.93#ibcon#about to read 5, iclass 7, count 0 2006.231.07:54:08.93#ibcon#read 5, iclass 7, count 0 2006.231.07:54:08.93#ibcon#about to read 6, iclass 7, count 0 2006.231.07:54:08.93#ibcon#read 6, iclass 7, count 0 2006.231.07:54:08.93#ibcon#end of sib2, iclass 7, count 0 2006.231.07:54:08.93#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:54:08.93#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:54:08.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:54:08.93#ibcon#*before write, iclass 7, count 0 2006.231.07:54:08.93#ibcon#enter sib2, iclass 7, count 0 2006.231.07:54:08.93#ibcon#flushed, iclass 7, count 0 2006.231.07:54:08.93#ibcon#about to write, iclass 7, count 0 2006.231.07:54:08.93#ibcon#wrote, iclass 7, count 0 2006.231.07:54:08.93#ibcon#about to read 3, iclass 7, count 0 2006.231.07:54:08.98#ibcon#read 3, iclass 7, count 0 2006.231.07:54:08.98#ibcon#about to read 4, iclass 7, count 0 2006.231.07:54:08.98#ibcon#read 4, iclass 7, count 0 2006.231.07:54:08.98#ibcon#about to read 5, iclass 7, count 0 2006.231.07:54:08.98#ibcon#read 5, iclass 7, count 0 2006.231.07:54:08.98#ibcon#about to read 6, iclass 7, count 0 2006.231.07:54:08.98#ibcon#read 6, iclass 7, count 0 2006.231.07:54:08.98#ibcon#end of sib2, iclass 7, count 0 2006.231.07:54:08.98#ibcon#*after write, iclass 7, count 0 2006.231.07:54:08.98#ibcon#*before return 0, iclass 7, count 0 2006.231.07:54:08.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:54:08.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:54:08.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:54:08.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:54:08.98$vc4f8/va=4,7 2006.231.07:54:08.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.07:54:08.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.07:54:08.98#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:08.98#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:54:09.03#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:54:09.03#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:54:09.03#ibcon#enter wrdev, iclass 11, count 2 2006.231.07:54:09.03#ibcon#first serial, iclass 11, count 2 2006.231.07:54:09.03#ibcon#enter sib2, iclass 11, count 2 2006.231.07:54:09.03#ibcon#flushed, iclass 11, count 2 2006.231.07:54:09.03#ibcon#about to write, iclass 11, count 2 2006.231.07:54:09.03#ibcon#wrote, iclass 11, count 2 2006.231.07:54:09.03#ibcon#about to read 3, iclass 11, count 2 2006.231.07:54:09.05#ibcon#read 3, iclass 11, count 2 2006.231.07:54:09.05#ibcon#about to read 4, iclass 11, count 2 2006.231.07:54:09.05#ibcon#read 4, iclass 11, count 2 2006.231.07:54:09.05#ibcon#about to read 5, iclass 11, count 2 2006.231.07:54:09.05#ibcon#read 5, iclass 11, count 2 2006.231.07:54:09.05#ibcon#about to read 6, iclass 11, count 2 2006.231.07:54:09.05#ibcon#read 6, iclass 11, count 2 2006.231.07:54:09.05#ibcon#end of sib2, iclass 11, count 2 2006.231.07:54:09.05#ibcon#*mode == 0, iclass 11, count 2 2006.231.07:54:09.05#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.07:54:09.05#ibcon#[25=AT04-07\r\n] 2006.231.07:54:09.05#ibcon#*before write, iclass 11, count 2 2006.231.07:54:09.05#ibcon#enter sib2, iclass 11, count 2 2006.231.07:54:09.05#ibcon#flushed, iclass 11, count 2 2006.231.07:54:09.05#ibcon#about to write, iclass 11, count 2 2006.231.07:54:09.05#ibcon#wrote, iclass 11, count 2 2006.231.07:54:09.05#ibcon#about to read 3, iclass 11, count 2 2006.231.07:54:09.08#ibcon#read 3, iclass 11, count 2 2006.231.07:54:09.08#ibcon#about to read 4, iclass 11, count 2 2006.231.07:54:09.08#ibcon#read 4, iclass 11, count 2 2006.231.07:54:09.08#ibcon#about to read 5, iclass 11, count 2 2006.231.07:54:09.08#ibcon#read 5, iclass 11, count 2 2006.231.07:54:09.08#ibcon#about to read 6, iclass 11, count 2 2006.231.07:54:09.08#ibcon#read 6, iclass 11, count 2 2006.231.07:54:09.08#ibcon#end of sib2, iclass 11, count 2 2006.231.07:54:09.08#ibcon#*after write, iclass 11, count 2 2006.231.07:54:09.08#ibcon#*before return 0, iclass 11, count 2 2006.231.07:54:09.08#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:54:09.08#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:54:09.08#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.07:54:09.08#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:09.08#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:54:09.20#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:54:09.20#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:54:09.20#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:54:09.20#ibcon#first serial, iclass 11, count 0 2006.231.07:54:09.20#ibcon#enter sib2, iclass 11, count 0 2006.231.07:54:09.20#ibcon#flushed, iclass 11, count 0 2006.231.07:54:09.20#ibcon#about to write, iclass 11, count 0 2006.231.07:54:09.20#ibcon#wrote, iclass 11, count 0 2006.231.07:54:09.20#ibcon#about to read 3, iclass 11, count 0 2006.231.07:54:09.22#ibcon#read 3, iclass 11, count 0 2006.231.07:54:09.22#ibcon#about to read 4, iclass 11, count 0 2006.231.07:54:09.22#ibcon#read 4, iclass 11, count 0 2006.231.07:54:09.22#ibcon#about to read 5, iclass 11, count 0 2006.231.07:54:09.22#ibcon#read 5, iclass 11, count 0 2006.231.07:54:09.22#ibcon#about to read 6, iclass 11, count 0 2006.231.07:54:09.22#ibcon#read 6, iclass 11, count 0 2006.231.07:54:09.22#ibcon#end of sib2, iclass 11, count 0 2006.231.07:54:09.22#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:54:09.22#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:54:09.22#ibcon#[25=USB\r\n] 2006.231.07:54:09.22#ibcon#*before write, iclass 11, count 0 2006.231.07:54:09.22#ibcon#enter sib2, iclass 11, count 0 2006.231.07:54:09.22#ibcon#flushed, iclass 11, count 0 2006.231.07:54:09.22#ibcon#about to write, iclass 11, count 0 2006.231.07:54:09.22#ibcon#wrote, iclass 11, count 0 2006.231.07:54:09.22#ibcon#about to read 3, iclass 11, count 0 2006.231.07:54:09.25#ibcon#read 3, iclass 11, count 0 2006.231.07:54:09.25#ibcon#about to read 4, iclass 11, count 0 2006.231.07:54:09.25#ibcon#read 4, iclass 11, count 0 2006.231.07:54:09.25#ibcon#about to read 5, iclass 11, count 0 2006.231.07:54:09.25#ibcon#read 5, iclass 11, count 0 2006.231.07:54:09.25#ibcon#about to read 6, iclass 11, count 0 2006.231.07:54:09.25#ibcon#read 6, iclass 11, count 0 2006.231.07:54:09.25#ibcon#end of sib2, iclass 11, count 0 2006.231.07:54:09.25#ibcon#*after write, iclass 11, count 0 2006.231.07:54:09.25#ibcon#*before return 0, iclass 11, count 0 2006.231.07:54:09.25#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:54:09.25#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:54:09.25#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:54:09.25#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:54:09.25$vc4f8/valo=5,652.99 2006.231.07:54:09.25#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.07:54:09.25#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.07:54:09.25#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:09.25#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:54:09.25#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:54:09.25#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:54:09.25#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:54:09.25#ibcon#first serial, iclass 13, count 0 2006.231.07:54:09.25#ibcon#enter sib2, iclass 13, count 0 2006.231.07:54:09.25#ibcon#flushed, iclass 13, count 0 2006.231.07:54:09.25#ibcon#about to write, iclass 13, count 0 2006.231.07:54:09.25#ibcon#wrote, iclass 13, count 0 2006.231.07:54:09.25#ibcon#about to read 3, iclass 13, count 0 2006.231.07:54:09.27#ibcon#read 3, iclass 13, count 0 2006.231.07:54:09.27#ibcon#about to read 4, iclass 13, count 0 2006.231.07:54:09.27#ibcon#read 4, iclass 13, count 0 2006.231.07:54:09.27#ibcon#about to read 5, iclass 13, count 0 2006.231.07:54:09.27#ibcon#read 5, iclass 13, count 0 2006.231.07:54:09.27#ibcon#about to read 6, iclass 13, count 0 2006.231.07:54:09.27#ibcon#read 6, iclass 13, count 0 2006.231.07:54:09.27#ibcon#end of sib2, iclass 13, count 0 2006.231.07:54:09.27#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:54:09.27#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:54:09.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:54:09.27#ibcon#*before write, iclass 13, count 0 2006.231.07:54:09.27#ibcon#enter sib2, iclass 13, count 0 2006.231.07:54:09.27#ibcon#flushed, iclass 13, count 0 2006.231.07:54:09.27#ibcon#about to write, iclass 13, count 0 2006.231.07:54:09.27#ibcon#wrote, iclass 13, count 0 2006.231.07:54:09.27#ibcon#about to read 3, iclass 13, count 0 2006.231.07:54:09.31#ibcon#read 3, iclass 13, count 0 2006.231.07:54:09.31#ibcon#about to read 4, iclass 13, count 0 2006.231.07:54:09.31#ibcon#read 4, iclass 13, count 0 2006.231.07:54:09.31#ibcon#about to read 5, iclass 13, count 0 2006.231.07:54:09.31#ibcon#read 5, iclass 13, count 0 2006.231.07:54:09.31#ibcon#about to read 6, iclass 13, count 0 2006.231.07:54:09.31#ibcon#read 6, iclass 13, count 0 2006.231.07:54:09.31#ibcon#end of sib2, iclass 13, count 0 2006.231.07:54:09.31#ibcon#*after write, iclass 13, count 0 2006.231.07:54:09.31#ibcon#*before return 0, iclass 13, count 0 2006.231.07:54:09.31#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:54:09.31#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:54:09.31#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:54:09.31#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:54:09.31$vc4f8/va=5,7 2006.231.07:54:09.31#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.07:54:09.31#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.07:54:09.31#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:09.31#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:54:09.37#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:54:09.37#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:54:09.37#ibcon#enter wrdev, iclass 15, count 2 2006.231.07:54:09.37#ibcon#first serial, iclass 15, count 2 2006.231.07:54:09.37#ibcon#enter sib2, iclass 15, count 2 2006.231.07:54:09.37#ibcon#flushed, iclass 15, count 2 2006.231.07:54:09.37#ibcon#about to write, iclass 15, count 2 2006.231.07:54:09.37#ibcon#wrote, iclass 15, count 2 2006.231.07:54:09.37#ibcon#about to read 3, iclass 15, count 2 2006.231.07:54:09.39#ibcon#read 3, iclass 15, count 2 2006.231.07:54:09.39#ibcon#about to read 4, iclass 15, count 2 2006.231.07:54:09.39#ibcon#read 4, iclass 15, count 2 2006.231.07:54:09.39#ibcon#about to read 5, iclass 15, count 2 2006.231.07:54:09.39#ibcon#read 5, iclass 15, count 2 2006.231.07:54:09.39#ibcon#about to read 6, iclass 15, count 2 2006.231.07:54:09.39#ibcon#read 6, iclass 15, count 2 2006.231.07:54:09.39#ibcon#end of sib2, iclass 15, count 2 2006.231.07:54:09.39#ibcon#*mode == 0, iclass 15, count 2 2006.231.07:54:09.39#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.07:54:09.39#ibcon#[25=AT05-07\r\n] 2006.231.07:54:09.39#ibcon#*before write, iclass 15, count 2 2006.231.07:54:09.39#ibcon#enter sib2, iclass 15, count 2 2006.231.07:54:09.39#ibcon#flushed, iclass 15, count 2 2006.231.07:54:09.39#ibcon#about to write, iclass 15, count 2 2006.231.07:54:09.39#ibcon#wrote, iclass 15, count 2 2006.231.07:54:09.39#ibcon#about to read 3, iclass 15, count 2 2006.231.07:54:09.42#ibcon#read 3, iclass 15, count 2 2006.231.07:54:09.42#ibcon#about to read 4, iclass 15, count 2 2006.231.07:54:09.42#ibcon#read 4, iclass 15, count 2 2006.231.07:54:09.42#ibcon#about to read 5, iclass 15, count 2 2006.231.07:54:09.42#ibcon#read 5, iclass 15, count 2 2006.231.07:54:09.42#ibcon#about to read 6, iclass 15, count 2 2006.231.07:54:09.42#ibcon#read 6, iclass 15, count 2 2006.231.07:54:09.42#ibcon#end of sib2, iclass 15, count 2 2006.231.07:54:09.42#ibcon#*after write, iclass 15, count 2 2006.231.07:54:09.42#ibcon#*before return 0, iclass 15, count 2 2006.231.07:54:09.42#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:54:09.42#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:54:09.42#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.07:54:09.42#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:09.42#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:54:09.54#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:54:09.54#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:54:09.54#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:54:09.54#ibcon#first serial, iclass 15, count 0 2006.231.07:54:09.54#ibcon#enter sib2, iclass 15, count 0 2006.231.07:54:09.54#ibcon#flushed, iclass 15, count 0 2006.231.07:54:09.54#ibcon#about to write, iclass 15, count 0 2006.231.07:54:09.54#ibcon#wrote, iclass 15, count 0 2006.231.07:54:09.54#ibcon#about to read 3, iclass 15, count 0 2006.231.07:54:09.56#ibcon#read 3, iclass 15, count 0 2006.231.07:54:09.56#ibcon#about to read 4, iclass 15, count 0 2006.231.07:54:09.56#ibcon#read 4, iclass 15, count 0 2006.231.07:54:09.56#ibcon#about to read 5, iclass 15, count 0 2006.231.07:54:09.56#ibcon#read 5, iclass 15, count 0 2006.231.07:54:09.56#ibcon#about to read 6, iclass 15, count 0 2006.231.07:54:09.56#ibcon#read 6, iclass 15, count 0 2006.231.07:54:09.56#ibcon#end of sib2, iclass 15, count 0 2006.231.07:54:09.56#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:54:09.56#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:54:09.56#ibcon#[25=USB\r\n] 2006.231.07:54:09.56#ibcon#*before write, iclass 15, count 0 2006.231.07:54:09.56#ibcon#enter sib2, iclass 15, count 0 2006.231.07:54:09.56#ibcon#flushed, iclass 15, count 0 2006.231.07:54:09.56#ibcon#about to write, iclass 15, count 0 2006.231.07:54:09.56#ibcon#wrote, iclass 15, count 0 2006.231.07:54:09.56#ibcon#about to read 3, iclass 15, count 0 2006.231.07:54:09.59#ibcon#read 3, iclass 15, count 0 2006.231.07:54:09.59#ibcon#about to read 4, iclass 15, count 0 2006.231.07:54:09.59#ibcon#read 4, iclass 15, count 0 2006.231.07:54:09.59#ibcon#about to read 5, iclass 15, count 0 2006.231.07:54:09.59#ibcon#read 5, iclass 15, count 0 2006.231.07:54:09.59#ibcon#about to read 6, iclass 15, count 0 2006.231.07:54:09.59#ibcon#read 6, iclass 15, count 0 2006.231.07:54:09.59#ibcon#end of sib2, iclass 15, count 0 2006.231.07:54:09.59#ibcon#*after write, iclass 15, count 0 2006.231.07:54:09.59#ibcon#*before return 0, iclass 15, count 0 2006.231.07:54:09.59#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:54:09.59#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:54:09.59#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:54:09.59#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:54:09.59$vc4f8/valo=6,772.99 2006.231.07:54:09.59#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.07:54:09.59#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.07:54:09.59#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:09.59#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:54:09.59#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:54:09.59#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:54:09.59#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:54:09.59#ibcon#first serial, iclass 17, count 0 2006.231.07:54:09.59#ibcon#enter sib2, iclass 17, count 0 2006.231.07:54:09.59#ibcon#flushed, iclass 17, count 0 2006.231.07:54:09.59#ibcon#about to write, iclass 17, count 0 2006.231.07:54:09.59#ibcon#wrote, iclass 17, count 0 2006.231.07:54:09.59#ibcon#about to read 3, iclass 17, count 0 2006.231.07:54:09.61#ibcon#read 3, iclass 17, count 0 2006.231.07:54:09.61#ibcon#about to read 4, iclass 17, count 0 2006.231.07:54:09.61#ibcon#read 4, iclass 17, count 0 2006.231.07:54:09.61#ibcon#about to read 5, iclass 17, count 0 2006.231.07:54:09.61#ibcon#read 5, iclass 17, count 0 2006.231.07:54:09.61#ibcon#about to read 6, iclass 17, count 0 2006.231.07:54:09.61#ibcon#read 6, iclass 17, count 0 2006.231.07:54:09.61#ibcon#end of sib2, iclass 17, count 0 2006.231.07:54:09.61#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:54:09.61#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:54:09.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:54:09.61#ibcon#*before write, iclass 17, count 0 2006.231.07:54:09.61#ibcon#enter sib2, iclass 17, count 0 2006.231.07:54:09.61#ibcon#flushed, iclass 17, count 0 2006.231.07:54:09.61#ibcon#about to write, iclass 17, count 0 2006.231.07:54:09.61#ibcon#wrote, iclass 17, count 0 2006.231.07:54:09.61#ibcon#about to read 3, iclass 17, count 0 2006.231.07:54:09.66#ibcon#read 3, iclass 17, count 0 2006.231.07:54:09.66#ibcon#about to read 4, iclass 17, count 0 2006.231.07:54:09.66#ibcon#read 4, iclass 17, count 0 2006.231.07:54:09.66#ibcon#about to read 5, iclass 17, count 0 2006.231.07:54:09.66#ibcon#read 5, iclass 17, count 0 2006.231.07:54:09.66#ibcon#about to read 6, iclass 17, count 0 2006.231.07:54:09.66#ibcon#read 6, iclass 17, count 0 2006.231.07:54:09.66#ibcon#end of sib2, iclass 17, count 0 2006.231.07:54:09.66#ibcon#*after write, iclass 17, count 0 2006.231.07:54:09.66#ibcon#*before return 0, iclass 17, count 0 2006.231.07:54:09.66#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:54:09.66#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:54:09.66#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:54:09.66#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:54:09.66$vc4f8/va=6,6 2006.231.07:54:09.66#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.231.07:54:09.66#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.231.07:54:09.66#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:09.66#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:54:09.71#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:54:09.71#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:54:09.71#ibcon#enter wrdev, iclass 19, count 2 2006.231.07:54:09.71#ibcon#first serial, iclass 19, count 2 2006.231.07:54:09.71#ibcon#enter sib2, iclass 19, count 2 2006.231.07:54:09.71#ibcon#flushed, iclass 19, count 2 2006.231.07:54:09.71#ibcon#about to write, iclass 19, count 2 2006.231.07:54:09.71#ibcon#wrote, iclass 19, count 2 2006.231.07:54:09.71#ibcon#about to read 3, iclass 19, count 2 2006.231.07:54:09.73#ibcon#read 3, iclass 19, count 2 2006.231.07:54:09.73#ibcon#about to read 4, iclass 19, count 2 2006.231.07:54:09.73#ibcon#read 4, iclass 19, count 2 2006.231.07:54:09.73#ibcon#about to read 5, iclass 19, count 2 2006.231.07:54:09.73#ibcon#read 5, iclass 19, count 2 2006.231.07:54:09.73#ibcon#about to read 6, iclass 19, count 2 2006.231.07:54:09.73#ibcon#read 6, iclass 19, count 2 2006.231.07:54:09.73#ibcon#end of sib2, iclass 19, count 2 2006.231.07:54:09.73#ibcon#*mode == 0, iclass 19, count 2 2006.231.07:54:09.73#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.231.07:54:09.73#ibcon#[25=AT06-06\r\n] 2006.231.07:54:09.73#ibcon#*before write, iclass 19, count 2 2006.231.07:54:09.73#ibcon#enter sib2, iclass 19, count 2 2006.231.07:54:09.73#ibcon#flushed, iclass 19, count 2 2006.231.07:54:09.73#ibcon#about to write, iclass 19, count 2 2006.231.07:54:09.73#ibcon#wrote, iclass 19, count 2 2006.231.07:54:09.73#ibcon#about to read 3, iclass 19, count 2 2006.231.07:54:09.76#ibcon#read 3, iclass 19, count 2 2006.231.07:54:09.76#ibcon#about to read 4, iclass 19, count 2 2006.231.07:54:09.76#ibcon#read 4, iclass 19, count 2 2006.231.07:54:09.76#ibcon#about to read 5, iclass 19, count 2 2006.231.07:54:09.76#ibcon#read 5, iclass 19, count 2 2006.231.07:54:09.76#ibcon#about to read 6, iclass 19, count 2 2006.231.07:54:09.76#ibcon#read 6, iclass 19, count 2 2006.231.07:54:09.76#ibcon#end of sib2, iclass 19, count 2 2006.231.07:54:09.76#ibcon#*after write, iclass 19, count 2 2006.231.07:54:09.76#ibcon#*before return 0, iclass 19, count 2 2006.231.07:54:09.76#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:54:09.76#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.231.07:54:09.76#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.231.07:54:09.76#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:09.76#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:54:09.88#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:54:09.88#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:54:09.88#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:54:09.88#ibcon#first serial, iclass 19, count 0 2006.231.07:54:09.88#ibcon#enter sib2, iclass 19, count 0 2006.231.07:54:09.88#ibcon#flushed, iclass 19, count 0 2006.231.07:54:09.88#ibcon#about to write, iclass 19, count 0 2006.231.07:54:09.88#ibcon#wrote, iclass 19, count 0 2006.231.07:54:09.88#ibcon#about to read 3, iclass 19, count 0 2006.231.07:54:09.90#ibcon#read 3, iclass 19, count 0 2006.231.07:54:09.90#ibcon#about to read 4, iclass 19, count 0 2006.231.07:54:09.90#ibcon#read 4, iclass 19, count 0 2006.231.07:54:09.90#ibcon#about to read 5, iclass 19, count 0 2006.231.07:54:09.90#ibcon#read 5, iclass 19, count 0 2006.231.07:54:09.90#ibcon#about to read 6, iclass 19, count 0 2006.231.07:54:09.90#ibcon#read 6, iclass 19, count 0 2006.231.07:54:09.90#ibcon#end of sib2, iclass 19, count 0 2006.231.07:54:09.90#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:54:09.90#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:54:09.90#ibcon#[25=USB\r\n] 2006.231.07:54:09.90#ibcon#*before write, iclass 19, count 0 2006.231.07:54:09.90#ibcon#enter sib2, iclass 19, count 0 2006.231.07:54:09.90#ibcon#flushed, iclass 19, count 0 2006.231.07:54:09.90#ibcon#about to write, iclass 19, count 0 2006.231.07:54:09.90#ibcon#wrote, iclass 19, count 0 2006.231.07:54:09.90#ibcon#about to read 3, iclass 19, count 0 2006.231.07:54:09.93#ibcon#read 3, iclass 19, count 0 2006.231.07:54:09.93#ibcon#about to read 4, iclass 19, count 0 2006.231.07:54:09.93#ibcon#read 4, iclass 19, count 0 2006.231.07:54:09.93#ibcon#about to read 5, iclass 19, count 0 2006.231.07:54:09.93#ibcon#read 5, iclass 19, count 0 2006.231.07:54:09.93#ibcon#about to read 6, iclass 19, count 0 2006.231.07:54:09.93#ibcon#read 6, iclass 19, count 0 2006.231.07:54:09.93#ibcon#end of sib2, iclass 19, count 0 2006.231.07:54:09.93#ibcon#*after write, iclass 19, count 0 2006.231.07:54:09.93#ibcon#*before return 0, iclass 19, count 0 2006.231.07:54:09.93#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:54:09.93#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.231.07:54:09.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:54:09.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:54:09.93$vc4f8/valo=7,832.99 2006.231.07:54:09.93#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.07:54:09.93#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.07:54:09.93#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:09.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:54:09.93#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:54:09.93#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:54:09.93#ibcon#enter wrdev, iclass 21, count 0 2006.231.07:54:09.93#ibcon#first serial, iclass 21, count 0 2006.231.07:54:09.93#ibcon#enter sib2, iclass 21, count 0 2006.231.07:54:09.93#ibcon#flushed, iclass 21, count 0 2006.231.07:54:09.93#ibcon#about to write, iclass 21, count 0 2006.231.07:54:09.93#ibcon#wrote, iclass 21, count 0 2006.231.07:54:09.93#ibcon#about to read 3, iclass 21, count 0 2006.231.07:54:09.95#ibcon#read 3, iclass 21, count 0 2006.231.07:54:09.95#ibcon#about to read 4, iclass 21, count 0 2006.231.07:54:09.95#ibcon#read 4, iclass 21, count 0 2006.231.07:54:09.95#ibcon#about to read 5, iclass 21, count 0 2006.231.07:54:09.95#ibcon#read 5, iclass 21, count 0 2006.231.07:54:09.95#ibcon#about to read 6, iclass 21, count 0 2006.231.07:54:09.95#ibcon#read 6, iclass 21, count 0 2006.231.07:54:09.95#ibcon#end of sib2, iclass 21, count 0 2006.231.07:54:09.95#ibcon#*mode == 0, iclass 21, count 0 2006.231.07:54:09.95#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.07:54:09.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:54:09.95#ibcon#*before write, iclass 21, count 0 2006.231.07:54:09.95#ibcon#enter sib2, iclass 21, count 0 2006.231.07:54:09.95#ibcon#flushed, iclass 21, count 0 2006.231.07:54:09.95#ibcon#about to write, iclass 21, count 0 2006.231.07:54:09.95#ibcon#wrote, iclass 21, count 0 2006.231.07:54:09.95#ibcon#about to read 3, iclass 21, count 0 2006.231.07:54:09.99#ibcon#read 3, iclass 21, count 0 2006.231.07:54:09.99#ibcon#about to read 4, iclass 21, count 0 2006.231.07:54:09.99#ibcon#read 4, iclass 21, count 0 2006.231.07:54:09.99#ibcon#about to read 5, iclass 21, count 0 2006.231.07:54:09.99#ibcon#read 5, iclass 21, count 0 2006.231.07:54:09.99#ibcon#about to read 6, iclass 21, count 0 2006.231.07:54:09.99#ibcon#read 6, iclass 21, count 0 2006.231.07:54:09.99#ibcon#end of sib2, iclass 21, count 0 2006.231.07:54:09.99#ibcon#*after write, iclass 21, count 0 2006.231.07:54:09.99#ibcon#*before return 0, iclass 21, count 0 2006.231.07:54:09.99#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:54:09.99#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.07:54:09.99#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.07:54:09.99#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.07:54:09.99$vc4f8/va=7,6 2006.231.07:54:09.99#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.231.07:54:09.99#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.231.07:54:09.99#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:09.99#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:54:10.05#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:54:10.05#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:54:10.05#ibcon#enter wrdev, iclass 23, count 2 2006.231.07:54:10.05#ibcon#first serial, iclass 23, count 2 2006.231.07:54:10.05#ibcon#enter sib2, iclass 23, count 2 2006.231.07:54:10.05#ibcon#flushed, iclass 23, count 2 2006.231.07:54:10.05#ibcon#about to write, iclass 23, count 2 2006.231.07:54:10.05#ibcon#wrote, iclass 23, count 2 2006.231.07:54:10.05#ibcon#about to read 3, iclass 23, count 2 2006.231.07:54:10.07#ibcon#read 3, iclass 23, count 2 2006.231.07:54:10.07#ibcon#about to read 4, iclass 23, count 2 2006.231.07:54:10.07#ibcon#read 4, iclass 23, count 2 2006.231.07:54:10.07#ibcon#about to read 5, iclass 23, count 2 2006.231.07:54:10.07#ibcon#read 5, iclass 23, count 2 2006.231.07:54:10.07#ibcon#about to read 6, iclass 23, count 2 2006.231.07:54:10.07#ibcon#read 6, iclass 23, count 2 2006.231.07:54:10.07#ibcon#end of sib2, iclass 23, count 2 2006.231.07:54:10.07#ibcon#*mode == 0, iclass 23, count 2 2006.231.07:54:10.07#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.231.07:54:10.07#ibcon#[25=AT07-06\r\n] 2006.231.07:54:10.07#ibcon#*before write, iclass 23, count 2 2006.231.07:54:10.07#ibcon#enter sib2, iclass 23, count 2 2006.231.07:54:10.07#ibcon#flushed, iclass 23, count 2 2006.231.07:54:10.07#ibcon#about to write, iclass 23, count 2 2006.231.07:54:10.07#ibcon#wrote, iclass 23, count 2 2006.231.07:54:10.07#ibcon#about to read 3, iclass 23, count 2 2006.231.07:54:10.10#ibcon#read 3, iclass 23, count 2 2006.231.07:54:10.10#ibcon#about to read 4, iclass 23, count 2 2006.231.07:54:10.10#ibcon#read 4, iclass 23, count 2 2006.231.07:54:10.10#ibcon#about to read 5, iclass 23, count 2 2006.231.07:54:10.10#ibcon#read 5, iclass 23, count 2 2006.231.07:54:10.10#ibcon#about to read 6, iclass 23, count 2 2006.231.07:54:10.10#ibcon#read 6, iclass 23, count 2 2006.231.07:54:10.10#ibcon#end of sib2, iclass 23, count 2 2006.231.07:54:10.10#ibcon#*after write, iclass 23, count 2 2006.231.07:54:10.10#ibcon#*before return 0, iclass 23, count 2 2006.231.07:54:10.10#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:54:10.10#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.231.07:54:10.10#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.231.07:54:10.10#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:10.10#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:54:10.22#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:54:10.22#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:54:10.22#ibcon#enter wrdev, iclass 23, count 0 2006.231.07:54:10.22#ibcon#first serial, iclass 23, count 0 2006.231.07:54:10.22#ibcon#enter sib2, iclass 23, count 0 2006.231.07:54:10.22#ibcon#flushed, iclass 23, count 0 2006.231.07:54:10.22#ibcon#about to write, iclass 23, count 0 2006.231.07:54:10.22#ibcon#wrote, iclass 23, count 0 2006.231.07:54:10.22#ibcon#about to read 3, iclass 23, count 0 2006.231.07:54:10.24#ibcon#read 3, iclass 23, count 0 2006.231.07:54:10.24#ibcon#about to read 4, iclass 23, count 0 2006.231.07:54:10.24#ibcon#read 4, iclass 23, count 0 2006.231.07:54:10.24#ibcon#about to read 5, iclass 23, count 0 2006.231.07:54:10.24#ibcon#read 5, iclass 23, count 0 2006.231.07:54:10.24#ibcon#about to read 6, iclass 23, count 0 2006.231.07:54:10.24#ibcon#read 6, iclass 23, count 0 2006.231.07:54:10.24#ibcon#end of sib2, iclass 23, count 0 2006.231.07:54:10.24#ibcon#*mode == 0, iclass 23, count 0 2006.231.07:54:10.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.07:54:10.24#ibcon#[25=USB\r\n] 2006.231.07:54:10.24#ibcon#*before write, iclass 23, count 0 2006.231.07:54:10.24#ibcon#enter sib2, iclass 23, count 0 2006.231.07:54:10.24#ibcon#flushed, iclass 23, count 0 2006.231.07:54:10.24#ibcon#about to write, iclass 23, count 0 2006.231.07:54:10.24#ibcon#wrote, iclass 23, count 0 2006.231.07:54:10.24#ibcon#about to read 3, iclass 23, count 0 2006.231.07:54:10.27#ibcon#read 3, iclass 23, count 0 2006.231.07:54:10.27#ibcon#about to read 4, iclass 23, count 0 2006.231.07:54:10.27#ibcon#read 4, iclass 23, count 0 2006.231.07:54:10.27#ibcon#about to read 5, iclass 23, count 0 2006.231.07:54:10.27#ibcon#read 5, iclass 23, count 0 2006.231.07:54:10.27#ibcon#about to read 6, iclass 23, count 0 2006.231.07:54:10.27#ibcon#read 6, iclass 23, count 0 2006.231.07:54:10.27#ibcon#end of sib2, iclass 23, count 0 2006.231.07:54:10.27#ibcon#*after write, iclass 23, count 0 2006.231.07:54:10.27#ibcon#*before return 0, iclass 23, count 0 2006.231.07:54:10.27#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:54:10.27#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.231.07:54:10.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.07:54:10.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.07:54:10.27$vc4f8/valo=8,852.99 2006.231.07:54:10.27#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.231.07:54:10.27#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.231.07:54:10.27#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:10.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:54:10.27#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:54:10.27#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:54:10.27#ibcon#enter wrdev, iclass 25, count 0 2006.231.07:54:10.27#ibcon#first serial, iclass 25, count 0 2006.231.07:54:10.27#ibcon#enter sib2, iclass 25, count 0 2006.231.07:54:10.27#ibcon#flushed, iclass 25, count 0 2006.231.07:54:10.27#ibcon#about to write, iclass 25, count 0 2006.231.07:54:10.27#ibcon#wrote, iclass 25, count 0 2006.231.07:54:10.27#ibcon#about to read 3, iclass 25, count 0 2006.231.07:54:10.29#ibcon#read 3, iclass 25, count 0 2006.231.07:54:10.29#ibcon#about to read 4, iclass 25, count 0 2006.231.07:54:10.29#ibcon#read 4, iclass 25, count 0 2006.231.07:54:10.29#ibcon#about to read 5, iclass 25, count 0 2006.231.07:54:10.29#ibcon#read 5, iclass 25, count 0 2006.231.07:54:10.29#ibcon#about to read 6, iclass 25, count 0 2006.231.07:54:10.29#ibcon#read 6, iclass 25, count 0 2006.231.07:54:10.29#ibcon#end of sib2, iclass 25, count 0 2006.231.07:54:10.29#ibcon#*mode == 0, iclass 25, count 0 2006.231.07:54:10.29#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.07:54:10.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:54:10.29#ibcon#*before write, iclass 25, count 0 2006.231.07:54:10.29#ibcon#enter sib2, iclass 25, count 0 2006.231.07:54:10.29#ibcon#flushed, iclass 25, count 0 2006.231.07:54:10.29#ibcon#about to write, iclass 25, count 0 2006.231.07:54:10.29#ibcon#wrote, iclass 25, count 0 2006.231.07:54:10.29#ibcon#about to read 3, iclass 25, count 0 2006.231.07:54:10.33#ibcon#read 3, iclass 25, count 0 2006.231.07:54:10.33#ibcon#about to read 4, iclass 25, count 0 2006.231.07:54:10.33#ibcon#read 4, iclass 25, count 0 2006.231.07:54:10.33#ibcon#about to read 5, iclass 25, count 0 2006.231.07:54:10.33#ibcon#read 5, iclass 25, count 0 2006.231.07:54:10.33#ibcon#about to read 6, iclass 25, count 0 2006.231.07:54:10.33#ibcon#read 6, iclass 25, count 0 2006.231.07:54:10.33#ibcon#end of sib2, iclass 25, count 0 2006.231.07:54:10.33#ibcon#*after write, iclass 25, count 0 2006.231.07:54:10.33#ibcon#*before return 0, iclass 25, count 0 2006.231.07:54:10.33#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:54:10.33#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.231.07:54:10.33#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.07:54:10.33#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.07:54:10.33$vc4f8/va=8,6 2006.231.07:54:10.33#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.231.07:54:10.33#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.231.07:54:10.33#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:10.33#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:54:10.39#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:54:10.39#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:54:10.39#ibcon#enter wrdev, iclass 27, count 2 2006.231.07:54:10.39#ibcon#first serial, iclass 27, count 2 2006.231.07:54:10.39#ibcon#enter sib2, iclass 27, count 2 2006.231.07:54:10.39#ibcon#flushed, iclass 27, count 2 2006.231.07:54:10.39#ibcon#about to write, iclass 27, count 2 2006.231.07:54:10.39#ibcon#wrote, iclass 27, count 2 2006.231.07:54:10.39#ibcon#about to read 3, iclass 27, count 2 2006.231.07:54:10.42#ibcon#read 3, iclass 27, count 2 2006.231.07:54:10.42#ibcon#about to read 4, iclass 27, count 2 2006.231.07:54:10.42#ibcon#read 4, iclass 27, count 2 2006.231.07:54:10.42#ibcon#about to read 5, iclass 27, count 2 2006.231.07:54:10.42#ibcon#read 5, iclass 27, count 2 2006.231.07:54:10.42#ibcon#about to read 6, iclass 27, count 2 2006.231.07:54:10.42#ibcon#read 6, iclass 27, count 2 2006.231.07:54:10.42#ibcon#end of sib2, iclass 27, count 2 2006.231.07:54:10.42#ibcon#*mode == 0, iclass 27, count 2 2006.231.07:54:10.42#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.231.07:54:10.42#ibcon#[25=AT08-06\r\n] 2006.231.07:54:10.42#ibcon#*before write, iclass 27, count 2 2006.231.07:54:10.42#ibcon#enter sib2, iclass 27, count 2 2006.231.07:54:10.42#ibcon#flushed, iclass 27, count 2 2006.231.07:54:10.42#ibcon#about to write, iclass 27, count 2 2006.231.07:54:10.42#ibcon#wrote, iclass 27, count 2 2006.231.07:54:10.42#ibcon#about to read 3, iclass 27, count 2 2006.231.07:54:10.45#ibcon#read 3, iclass 27, count 2 2006.231.07:54:10.45#ibcon#about to read 4, iclass 27, count 2 2006.231.07:54:10.45#ibcon#read 4, iclass 27, count 2 2006.231.07:54:10.45#ibcon#about to read 5, iclass 27, count 2 2006.231.07:54:10.45#ibcon#read 5, iclass 27, count 2 2006.231.07:54:10.45#ibcon#about to read 6, iclass 27, count 2 2006.231.07:54:10.45#ibcon#read 6, iclass 27, count 2 2006.231.07:54:10.45#ibcon#end of sib2, iclass 27, count 2 2006.231.07:54:10.45#ibcon#*after write, iclass 27, count 2 2006.231.07:54:10.45#ibcon#*before return 0, iclass 27, count 2 2006.231.07:54:10.45#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:54:10.45#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.231.07:54:10.45#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.231.07:54:10.45#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:10.45#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:54:10.57#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:54:10.57#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:54:10.57#ibcon#enter wrdev, iclass 27, count 0 2006.231.07:54:10.57#ibcon#first serial, iclass 27, count 0 2006.231.07:54:10.57#ibcon#enter sib2, iclass 27, count 0 2006.231.07:54:10.57#ibcon#flushed, iclass 27, count 0 2006.231.07:54:10.57#ibcon#about to write, iclass 27, count 0 2006.231.07:54:10.57#ibcon#wrote, iclass 27, count 0 2006.231.07:54:10.57#ibcon#about to read 3, iclass 27, count 0 2006.231.07:54:10.59#ibcon#read 3, iclass 27, count 0 2006.231.07:54:10.59#ibcon#about to read 4, iclass 27, count 0 2006.231.07:54:10.59#ibcon#read 4, iclass 27, count 0 2006.231.07:54:10.59#ibcon#about to read 5, iclass 27, count 0 2006.231.07:54:10.59#ibcon#read 5, iclass 27, count 0 2006.231.07:54:10.59#ibcon#about to read 6, iclass 27, count 0 2006.231.07:54:10.59#ibcon#read 6, iclass 27, count 0 2006.231.07:54:10.59#ibcon#end of sib2, iclass 27, count 0 2006.231.07:54:10.59#ibcon#*mode == 0, iclass 27, count 0 2006.231.07:54:10.59#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.07:54:10.59#ibcon#[25=USB\r\n] 2006.231.07:54:10.59#ibcon#*before write, iclass 27, count 0 2006.231.07:54:10.59#ibcon#enter sib2, iclass 27, count 0 2006.231.07:54:10.59#ibcon#flushed, iclass 27, count 0 2006.231.07:54:10.59#ibcon#about to write, iclass 27, count 0 2006.231.07:54:10.59#ibcon#wrote, iclass 27, count 0 2006.231.07:54:10.59#ibcon#about to read 3, iclass 27, count 0 2006.231.07:54:10.62#ibcon#read 3, iclass 27, count 0 2006.231.07:54:10.62#ibcon#about to read 4, iclass 27, count 0 2006.231.07:54:10.62#ibcon#read 4, iclass 27, count 0 2006.231.07:54:10.62#ibcon#about to read 5, iclass 27, count 0 2006.231.07:54:10.62#ibcon#read 5, iclass 27, count 0 2006.231.07:54:10.62#ibcon#about to read 6, iclass 27, count 0 2006.231.07:54:10.62#ibcon#read 6, iclass 27, count 0 2006.231.07:54:10.62#ibcon#end of sib2, iclass 27, count 0 2006.231.07:54:10.62#ibcon#*after write, iclass 27, count 0 2006.231.07:54:10.62#ibcon#*before return 0, iclass 27, count 0 2006.231.07:54:10.62#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:54:10.62#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.231.07:54:10.62#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.07:54:10.62#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.07:54:10.62$vc4f8/vblo=1,632.99 2006.231.07:54:10.62#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.231.07:54:10.62#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.231.07:54:10.62#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:10.62#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:54:10.62#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:54:10.62#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:54:10.62#ibcon#enter wrdev, iclass 29, count 0 2006.231.07:54:10.62#ibcon#first serial, iclass 29, count 0 2006.231.07:54:10.62#ibcon#enter sib2, iclass 29, count 0 2006.231.07:54:10.62#ibcon#flushed, iclass 29, count 0 2006.231.07:54:10.62#ibcon#about to write, iclass 29, count 0 2006.231.07:54:10.62#ibcon#wrote, iclass 29, count 0 2006.231.07:54:10.62#ibcon#about to read 3, iclass 29, count 0 2006.231.07:54:10.64#ibcon#read 3, iclass 29, count 0 2006.231.07:54:10.64#ibcon#about to read 4, iclass 29, count 0 2006.231.07:54:10.64#ibcon#read 4, iclass 29, count 0 2006.231.07:54:10.64#ibcon#about to read 5, iclass 29, count 0 2006.231.07:54:10.64#ibcon#read 5, iclass 29, count 0 2006.231.07:54:10.64#ibcon#about to read 6, iclass 29, count 0 2006.231.07:54:10.64#ibcon#read 6, iclass 29, count 0 2006.231.07:54:10.64#ibcon#end of sib2, iclass 29, count 0 2006.231.07:54:10.64#ibcon#*mode == 0, iclass 29, count 0 2006.231.07:54:10.64#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.07:54:10.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:54:10.64#ibcon#*before write, iclass 29, count 0 2006.231.07:54:10.64#ibcon#enter sib2, iclass 29, count 0 2006.231.07:54:10.64#ibcon#flushed, iclass 29, count 0 2006.231.07:54:10.64#ibcon#about to write, iclass 29, count 0 2006.231.07:54:10.64#ibcon#wrote, iclass 29, count 0 2006.231.07:54:10.64#ibcon#about to read 3, iclass 29, count 0 2006.231.07:54:10.68#ibcon#read 3, iclass 29, count 0 2006.231.07:54:10.68#ibcon#about to read 4, iclass 29, count 0 2006.231.07:54:10.68#ibcon#read 4, iclass 29, count 0 2006.231.07:54:10.68#ibcon#about to read 5, iclass 29, count 0 2006.231.07:54:10.68#ibcon#read 5, iclass 29, count 0 2006.231.07:54:10.68#ibcon#about to read 6, iclass 29, count 0 2006.231.07:54:10.68#ibcon#read 6, iclass 29, count 0 2006.231.07:54:10.68#ibcon#end of sib2, iclass 29, count 0 2006.231.07:54:10.68#ibcon#*after write, iclass 29, count 0 2006.231.07:54:10.68#ibcon#*before return 0, iclass 29, count 0 2006.231.07:54:10.68#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:54:10.68#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.231.07:54:10.68#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.07:54:10.68#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.07:54:10.68$vc4f8/vb=1,4 2006.231.07:54:10.68#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.231.07:54:10.68#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.231.07:54:10.68#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:10.68#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:54:10.68#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:54:10.68#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:54:10.68#ibcon#enter wrdev, iclass 31, count 2 2006.231.07:54:10.68#ibcon#first serial, iclass 31, count 2 2006.231.07:54:10.68#ibcon#enter sib2, iclass 31, count 2 2006.231.07:54:10.68#ibcon#flushed, iclass 31, count 2 2006.231.07:54:10.68#ibcon#about to write, iclass 31, count 2 2006.231.07:54:10.68#ibcon#wrote, iclass 31, count 2 2006.231.07:54:10.68#ibcon#about to read 3, iclass 31, count 2 2006.231.07:54:10.70#ibcon#read 3, iclass 31, count 2 2006.231.07:54:10.70#ibcon#about to read 4, iclass 31, count 2 2006.231.07:54:10.70#ibcon#read 4, iclass 31, count 2 2006.231.07:54:10.70#ibcon#about to read 5, iclass 31, count 2 2006.231.07:54:10.70#ibcon#read 5, iclass 31, count 2 2006.231.07:54:10.70#ibcon#about to read 6, iclass 31, count 2 2006.231.07:54:10.70#ibcon#read 6, iclass 31, count 2 2006.231.07:54:10.70#ibcon#end of sib2, iclass 31, count 2 2006.231.07:54:10.70#ibcon#*mode == 0, iclass 31, count 2 2006.231.07:54:10.70#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.231.07:54:10.70#ibcon#[27=AT01-04\r\n] 2006.231.07:54:10.70#ibcon#*before write, iclass 31, count 2 2006.231.07:54:10.70#ibcon#enter sib2, iclass 31, count 2 2006.231.07:54:10.70#ibcon#flushed, iclass 31, count 2 2006.231.07:54:10.70#ibcon#about to write, iclass 31, count 2 2006.231.07:54:10.70#ibcon#wrote, iclass 31, count 2 2006.231.07:54:10.70#ibcon#about to read 3, iclass 31, count 2 2006.231.07:54:10.73#ibcon#read 3, iclass 31, count 2 2006.231.07:54:10.73#ibcon#about to read 4, iclass 31, count 2 2006.231.07:54:10.73#ibcon#read 4, iclass 31, count 2 2006.231.07:54:10.73#ibcon#about to read 5, iclass 31, count 2 2006.231.07:54:10.73#ibcon#read 5, iclass 31, count 2 2006.231.07:54:10.73#ibcon#about to read 6, iclass 31, count 2 2006.231.07:54:10.73#ibcon#read 6, iclass 31, count 2 2006.231.07:54:10.73#ibcon#end of sib2, iclass 31, count 2 2006.231.07:54:10.73#ibcon#*after write, iclass 31, count 2 2006.231.07:54:10.73#ibcon#*before return 0, iclass 31, count 2 2006.231.07:54:10.73#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:54:10.73#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.231.07:54:10.73#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.231.07:54:10.73#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:10.73#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:54:10.85#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:54:10.85#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:54:10.85#ibcon#enter wrdev, iclass 31, count 0 2006.231.07:54:10.85#ibcon#first serial, iclass 31, count 0 2006.231.07:54:10.85#ibcon#enter sib2, iclass 31, count 0 2006.231.07:54:10.85#ibcon#flushed, iclass 31, count 0 2006.231.07:54:10.85#ibcon#about to write, iclass 31, count 0 2006.231.07:54:10.85#ibcon#wrote, iclass 31, count 0 2006.231.07:54:10.85#ibcon#about to read 3, iclass 31, count 0 2006.231.07:54:10.87#ibcon#read 3, iclass 31, count 0 2006.231.07:54:10.87#ibcon#about to read 4, iclass 31, count 0 2006.231.07:54:10.87#ibcon#read 4, iclass 31, count 0 2006.231.07:54:10.87#ibcon#about to read 5, iclass 31, count 0 2006.231.07:54:10.87#ibcon#read 5, iclass 31, count 0 2006.231.07:54:10.87#ibcon#about to read 6, iclass 31, count 0 2006.231.07:54:10.87#ibcon#read 6, iclass 31, count 0 2006.231.07:54:10.87#ibcon#end of sib2, iclass 31, count 0 2006.231.07:54:10.87#ibcon#*mode == 0, iclass 31, count 0 2006.231.07:54:10.87#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.07:54:10.87#ibcon#[27=USB\r\n] 2006.231.07:54:10.87#ibcon#*before write, iclass 31, count 0 2006.231.07:54:10.87#ibcon#enter sib2, iclass 31, count 0 2006.231.07:54:10.87#ibcon#flushed, iclass 31, count 0 2006.231.07:54:10.87#ibcon#about to write, iclass 31, count 0 2006.231.07:54:10.87#ibcon#wrote, iclass 31, count 0 2006.231.07:54:10.87#ibcon#about to read 3, iclass 31, count 0 2006.231.07:54:10.90#ibcon#read 3, iclass 31, count 0 2006.231.07:54:10.90#ibcon#about to read 4, iclass 31, count 0 2006.231.07:54:10.90#ibcon#read 4, iclass 31, count 0 2006.231.07:54:10.90#ibcon#about to read 5, iclass 31, count 0 2006.231.07:54:10.90#ibcon#read 5, iclass 31, count 0 2006.231.07:54:10.90#ibcon#about to read 6, iclass 31, count 0 2006.231.07:54:10.90#ibcon#read 6, iclass 31, count 0 2006.231.07:54:10.90#ibcon#end of sib2, iclass 31, count 0 2006.231.07:54:10.90#ibcon#*after write, iclass 31, count 0 2006.231.07:54:10.90#ibcon#*before return 0, iclass 31, count 0 2006.231.07:54:10.90#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:54:10.90#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.231.07:54:10.90#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.07:54:10.90#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.07:54:10.90$vc4f8/vblo=2,640.99 2006.231.07:54:10.90#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.07:54:10.90#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.07:54:10.90#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:10.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:54:10.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:54:10.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:54:10.90#ibcon#enter wrdev, iclass 33, count 0 2006.231.07:54:10.90#ibcon#first serial, iclass 33, count 0 2006.231.07:54:10.90#ibcon#enter sib2, iclass 33, count 0 2006.231.07:54:10.90#ibcon#flushed, iclass 33, count 0 2006.231.07:54:10.90#ibcon#about to write, iclass 33, count 0 2006.231.07:54:10.90#ibcon#wrote, iclass 33, count 0 2006.231.07:54:10.90#ibcon#about to read 3, iclass 33, count 0 2006.231.07:54:10.92#ibcon#read 3, iclass 33, count 0 2006.231.07:54:10.92#ibcon#about to read 4, iclass 33, count 0 2006.231.07:54:10.92#ibcon#read 4, iclass 33, count 0 2006.231.07:54:10.92#ibcon#about to read 5, iclass 33, count 0 2006.231.07:54:10.92#ibcon#read 5, iclass 33, count 0 2006.231.07:54:10.92#ibcon#about to read 6, iclass 33, count 0 2006.231.07:54:10.92#ibcon#read 6, iclass 33, count 0 2006.231.07:54:10.92#ibcon#end of sib2, iclass 33, count 0 2006.231.07:54:10.92#ibcon#*mode == 0, iclass 33, count 0 2006.231.07:54:10.92#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.07:54:10.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:54:10.92#ibcon#*before write, iclass 33, count 0 2006.231.07:54:10.92#ibcon#enter sib2, iclass 33, count 0 2006.231.07:54:10.92#ibcon#flushed, iclass 33, count 0 2006.231.07:54:10.92#ibcon#about to write, iclass 33, count 0 2006.231.07:54:10.92#ibcon#wrote, iclass 33, count 0 2006.231.07:54:10.92#ibcon#about to read 3, iclass 33, count 0 2006.231.07:54:10.96#ibcon#read 3, iclass 33, count 0 2006.231.07:54:10.96#ibcon#about to read 4, iclass 33, count 0 2006.231.07:54:10.96#ibcon#read 4, iclass 33, count 0 2006.231.07:54:10.96#ibcon#about to read 5, iclass 33, count 0 2006.231.07:54:10.96#ibcon#read 5, iclass 33, count 0 2006.231.07:54:10.96#ibcon#about to read 6, iclass 33, count 0 2006.231.07:54:10.96#ibcon#read 6, iclass 33, count 0 2006.231.07:54:10.96#ibcon#end of sib2, iclass 33, count 0 2006.231.07:54:10.96#ibcon#*after write, iclass 33, count 0 2006.231.07:54:10.96#ibcon#*before return 0, iclass 33, count 0 2006.231.07:54:10.96#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:54:10.96#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.07:54:10.96#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.07:54:10.96#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.07:54:10.96$vc4f8/vb=2,4 2006.231.07:54:10.96#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.07:54:10.96#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.07:54:10.96#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:10.96#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:54:11.02#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:54:11.02#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:54:11.02#ibcon#enter wrdev, iclass 35, count 2 2006.231.07:54:11.02#ibcon#first serial, iclass 35, count 2 2006.231.07:54:11.02#ibcon#enter sib2, iclass 35, count 2 2006.231.07:54:11.02#ibcon#flushed, iclass 35, count 2 2006.231.07:54:11.02#ibcon#about to write, iclass 35, count 2 2006.231.07:54:11.02#ibcon#wrote, iclass 35, count 2 2006.231.07:54:11.02#ibcon#about to read 3, iclass 35, count 2 2006.231.07:54:11.04#ibcon#read 3, iclass 35, count 2 2006.231.07:54:11.04#ibcon#about to read 4, iclass 35, count 2 2006.231.07:54:11.04#ibcon#read 4, iclass 35, count 2 2006.231.07:54:11.04#ibcon#about to read 5, iclass 35, count 2 2006.231.07:54:11.04#ibcon#read 5, iclass 35, count 2 2006.231.07:54:11.04#ibcon#about to read 6, iclass 35, count 2 2006.231.07:54:11.04#ibcon#read 6, iclass 35, count 2 2006.231.07:54:11.04#ibcon#end of sib2, iclass 35, count 2 2006.231.07:54:11.04#ibcon#*mode == 0, iclass 35, count 2 2006.231.07:54:11.04#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.07:54:11.04#ibcon#[27=AT02-04\r\n] 2006.231.07:54:11.04#ibcon#*before write, iclass 35, count 2 2006.231.07:54:11.04#ibcon#enter sib2, iclass 35, count 2 2006.231.07:54:11.04#ibcon#flushed, iclass 35, count 2 2006.231.07:54:11.04#ibcon#about to write, iclass 35, count 2 2006.231.07:54:11.04#ibcon#wrote, iclass 35, count 2 2006.231.07:54:11.04#ibcon#about to read 3, iclass 35, count 2 2006.231.07:54:11.07#ibcon#read 3, iclass 35, count 2 2006.231.07:54:11.07#ibcon#about to read 4, iclass 35, count 2 2006.231.07:54:11.07#ibcon#read 4, iclass 35, count 2 2006.231.07:54:11.07#ibcon#about to read 5, iclass 35, count 2 2006.231.07:54:11.07#ibcon#read 5, iclass 35, count 2 2006.231.07:54:11.07#ibcon#about to read 6, iclass 35, count 2 2006.231.07:54:11.07#ibcon#read 6, iclass 35, count 2 2006.231.07:54:11.07#ibcon#end of sib2, iclass 35, count 2 2006.231.07:54:11.07#ibcon#*after write, iclass 35, count 2 2006.231.07:54:11.07#ibcon#*before return 0, iclass 35, count 2 2006.231.07:54:11.07#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:54:11.07#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.07:54:11.07#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.07:54:11.07#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:11.07#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:54:11.19#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:54:11.19#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:54:11.19#ibcon#enter wrdev, iclass 35, count 0 2006.231.07:54:11.19#ibcon#first serial, iclass 35, count 0 2006.231.07:54:11.19#ibcon#enter sib2, iclass 35, count 0 2006.231.07:54:11.19#ibcon#flushed, iclass 35, count 0 2006.231.07:54:11.19#ibcon#about to write, iclass 35, count 0 2006.231.07:54:11.19#ibcon#wrote, iclass 35, count 0 2006.231.07:54:11.19#ibcon#about to read 3, iclass 35, count 0 2006.231.07:54:11.22#ibcon#read 3, iclass 35, count 0 2006.231.07:54:11.22#ibcon#about to read 4, iclass 35, count 0 2006.231.07:54:11.22#ibcon#read 4, iclass 35, count 0 2006.231.07:54:11.22#ibcon#about to read 5, iclass 35, count 0 2006.231.07:54:11.22#ibcon#read 5, iclass 35, count 0 2006.231.07:54:11.22#ibcon#about to read 6, iclass 35, count 0 2006.231.07:54:11.22#ibcon#read 6, iclass 35, count 0 2006.231.07:54:11.22#ibcon#end of sib2, iclass 35, count 0 2006.231.07:54:11.22#ibcon#*mode == 0, iclass 35, count 0 2006.231.07:54:11.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.07:54:11.22#ibcon#[27=USB\r\n] 2006.231.07:54:11.22#ibcon#*before write, iclass 35, count 0 2006.231.07:54:11.22#ibcon#enter sib2, iclass 35, count 0 2006.231.07:54:11.22#ibcon#flushed, iclass 35, count 0 2006.231.07:54:11.22#ibcon#about to write, iclass 35, count 0 2006.231.07:54:11.22#ibcon#wrote, iclass 35, count 0 2006.231.07:54:11.22#ibcon#about to read 3, iclass 35, count 0 2006.231.07:54:11.25#ibcon#read 3, iclass 35, count 0 2006.231.07:54:11.25#ibcon#about to read 4, iclass 35, count 0 2006.231.07:54:11.25#ibcon#read 4, iclass 35, count 0 2006.231.07:54:11.25#ibcon#about to read 5, iclass 35, count 0 2006.231.07:54:11.25#ibcon#read 5, iclass 35, count 0 2006.231.07:54:11.25#ibcon#about to read 6, iclass 35, count 0 2006.231.07:54:11.25#ibcon#read 6, iclass 35, count 0 2006.231.07:54:11.25#ibcon#end of sib2, iclass 35, count 0 2006.231.07:54:11.25#ibcon#*after write, iclass 35, count 0 2006.231.07:54:11.25#ibcon#*before return 0, iclass 35, count 0 2006.231.07:54:11.25#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:54:11.25#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.07:54:11.25#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.07:54:11.25#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.07:54:11.25$vc4f8/vblo=3,656.99 2006.231.07:54:11.25#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.07:54:11.25#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.07:54:11.25#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:11.25#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:54:11.25#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:54:11.25#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:54:11.25#ibcon#enter wrdev, iclass 37, count 0 2006.231.07:54:11.25#ibcon#first serial, iclass 37, count 0 2006.231.07:54:11.25#ibcon#enter sib2, iclass 37, count 0 2006.231.07:54:11.25#ibcon#flushed, iclass 37, count 0 2006.231.07:54:11.25#ibcon#about to write, iclass 37, count 0 2006.231.07:54:11.25#ibcon#wrote, iclass 37, count 0 2006.231.07:54:11.25#ibcon#about to read 3, iclass 37, count 0 2006.231.07:54:11.27#ibcon#read 3, iclass 37, count 0 2006.231.07:54:11.27#ibcon#about to read 4, iclass 37, count 0 2006.231.07:54:11.27#ibcon#read 4, iclass 37, count 0 2006.231.07:54:11.27#ibcon#about to read 5, iclass 37, count 0 2006.231.07:54:11.27#ibcon#read 5, iclass 37, count 0 2006.231.07:54:11.27#ibcon#about to read 6, iclass 37, count 0 2006.231.07:54:11.27#ibcon#read 6, iclass 37, count 0 2006.231.07:54:11.27#ibcon#end of sib2, iclass 37, count 0 2006.231.07:54:11.27#ibcon#*mode == 0, iclass 37, count 0 2006.231.07:54:11.27#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.07:54:11.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:54:11.27#ibcon#*before write, iclass 37, count 0 2006.231.07:54:11.27#ibcon#enter sib2, iclass 37, count 0 2006.231.07:54:11.27#ibcon#flushed, iclass 37, count 0 2006.231.07:54:11.27#ibcon#about to write, iclass 37, count 0 2006.231.07:54:11.27#ibcon#wrote, iclass 37, count 0 2006.231.07:54:11.27#ibcon#about to read 3, iclass 37, count 0 2006.231.07:54:11.31#ibcon#read 3, iclass 37, count 0 2006.231.07:54:11.31#ibcon#about to read 4, iclass 37, count 0 2006.231.07:54:11.31#ibcon#read 4, iclass 37, count 0 2006.231.07:54:11.31#ibcon#about to read 5, iclass 37, count 0 2006.231.07:54:11.31#ibcon#read 5, iclass 37, count 0 2006.231.07:54:11.31#ibcon#about to read 6, iclass 37, count 0 2006.231.07:54:11.31#ibcon#read 6, iclass 37, count 0 2006.231.07:54:11.31#ibcon#end of sib2, iclass 37, count 0 2006.231.07:54:11.31#ibcon#*after write, iclass 37, count 0 2006.231.07:54:11.31#ibcon#*before return 0, iclass 37, count 0 2006.231.07:54:11.31#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:54:11.31#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.07:54:11.31#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.07:54:11.31#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.07:54:11.31$vc4f8/vb=3,4 2006.231.07:54:11.31#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.07:54:11.31#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.07:54:11.31#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:11.31#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:54:11.37#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:54:11.37#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:54:11.37#ibcon#enter wrdev, iclass 39, count 2 2006.231.07:54:11.37#ibcon#first serial, iclass 39, count 2 2006.231.07:54:11.37#ibcon#enter sib2, iclass 39, count 2 2006.231.07:54:11.37#ibcon#flushed, iclass 39, count 2 2006.231.07:54:11.37#ibcon#about to write, iclass 39, count 2 2006.231.07:54:11.37#ibcon#wrote, iclass 39, count 2 2006.231.07:54:11.37#ibcon#about to read 3, iclass 39, count 2 2006.231.07:54:11.39#ibcon#read 3, iclass 39, count 2 2006.231.07:54:11.39#ibcon#about to read 4, iclass 39, count 2 2006.231.07:54:11.39#ibcon#read 4, iclass 39, count 2 2006.231.07:54:11.39#ibcon#about to read 5, iclass 39, count 2 2006.231.07:54:11.39#ibcon#read 5, iclass 39, count 2 2006.231.07:54:11.39#ibcon#about to read 6, iclass 39, count 2 2006.231.07:54:11.39#ibcon#read 6, iclass 39, count 2 2006.231.07:54:11.39#ibcon#end of sib2, iclass 39, count 2 2006.231.07:54:11.39#ibcon#*mode == 0, iclass 39, count 2 2006.231.07:54:11.39#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.07:54:11.39#ibcon#[27=AT03-04\r\n] 2006.231.07:54:11.39#ibcon#*before write, iclass 39, count 2 2006.231.07:54:11.39#ibcon#enter sib2, iclass 39, count 2 2006.231.07:54:11.39#ibcon#flushed, iclass 39, count 2 2006.231.07:54:11.39#ibcon#about to write, iclass 39, count 2 2006.231.07:54:11.39#ibcon#wrote, iclass 39, count 2 2006.231.07:54:11.39#ibcon#about to read 3, iclass 39, count 2 2006.231.07:54:11.42#ibcon#read 3, iclass 39, count 2 2006.231.07:54:11.42#ibcon#about to read 4, iclass 39, count 2 2006.231.07:54:11.42#ibcon#read 4, iclass 39, count 2 2006.231.07:54:11.42#ibcon#about to read 5, iclass 39, count 2 2006.231.07:54:11.42#ibcon#read 5, iclass 39, count 2 2006.231.07:54:11.42#ibcon#about to read 6, iclass 39, count 2 2006.231.07:54:11.42#ibcon#read 6, iclass 39, count 2 2006.231.07:54:11.42#ibcon#end of sib2, iclass 39, count 2 2006.231.07:54:11.42#ibcon#*after write, iclass 39, count 2 2006.231.07:54:11.42#ibcon#*before return 0, iclass 39, count 2 2006.231.07:54:11.42#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:54:11.42#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.07:54:11.42#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.07:54:11.42#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:11.42#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:54:11.54#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:54:11.54#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:54:11.54#ibcon#enter wrdev, iclass 39, count 0 2006.231.07:54:11.54#ibcon#first serial, iclass 39, count 0 2006.231.07:54:11.54#ibcon#enter sib2, iclass 39, count 0 2006.231.07:54:11.54#ibcon#flushed, iclass 39, count 0 2006.231.07:54:11.54#ibcon#about to write, iclass 39, count 0 2006.231.07:54:11.54#ibcon#wrote, iclass 39, count 0 2006.231.07:54:11.54#ibcon#about to read 3, iclass 39, count 0 2006.231.07:54:11.56#ibcon#read 3, iclass 39, count 0 2006.231.07:54:11.56#ibcon#about to read 4, iclass 39, count 0 2006.231.07:54:11.56#ibcon#read 4, iclass 39, count 0 2006.231.07:54:11.56#ibcon#about to read 5, iclass 39, count 0 2006.231.07:54:11.56#ibcon#read 5, iclass 39, count 0 2006.231.07:54:11.56#ibcon#about to read 6, iclass 39, count 0 2006.231.07:54:11.56#ibcon#read 6, iclass 39, count 0 2006.231.07:54:11.56#ibcon#end of sib2, iclass 39, count 0 2006.231.07:54:11.56#ibcon#*mode == 0, iclass 39, count 0 2006.231.07:54:11.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.07:54:11.56#ibcon#[27=USB\r\n] 2006.231.07:54:11.56#ibcon#*before write, iclass 39, count 0 2006.231.07:54:11.56#ibcon#enter sib2, iclass 39, count 0 2006.231.07:54:11.56#ibcon#flushed, iclass 39, count 0 2006.231.07:54:11.56#ibcon#about to write, iclass 39, count 0 2006.231.07:54:11.56#ibcon#wrote, iclass 39, count 0 2006.231.07:54:11.56#ibcon#about to read 3, iclass 39, count 0 2006.231.07:54:11.59#ibcon#read 3, iclass 39, count 0 2006.231.07:54:11.59#ibcon#about to read 4, iclass 39, count 0 2006.231.07:54:11.59#ibcon#read 4, iclass 39, count 0 2006.231.07:54:11.59#ibcon#about to read 5, iclass 39, count 0 2006.231.07:54:11.59#ibcon#read 5, iclass 39, count 0 2006.231.07:54:11.59#ibcon#about to read 6, iclass 39, count 0 2006.231.07:54:11.59#ibcon#read 6, iclass 39, count 0 2006.231.07:54:11.59#ibcon#end of sib2, iclass 39, count 0 2006.231.07:54:11.59#ibcon#*after write, iclass 39, count 0 2006.231.07:54:11.59#ibcon#*before return 0, iclass 39, count 0 2006.231.07:54:11.59#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:54:11.59#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.07:54:11.59#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.07:54:11.59#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.07:54:11.59$vc4f8/vblo=4,712.99 2006.231.07:54:11.59#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.07:54:11.59#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.07:54:11.59#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:11.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:54:11.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:54:11.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:54:11.59#ibcon#enter wrdev, iclass 3, count 0 2006.231.07:54:11.59#ibcon#first serial, iclass 3, count 0 2006.231.07:54:11.59#ibcon#enter sib2, iclass 3, count 0 2006.231.07:54:11.59#ibcon#flushed, iclass 3, count 0 2006.231.07:54:11.59#ibcon#about to write, iclass 3, count 0 2006.231.07:54:11.59#ibcon#wrote, iclass 3, count 0 2006.231.07:54:11.59#ibcon#about to read 3, iclass 3, count 0 2006.231.07:54:11.61#ibcon#read 3, iclass 3, count 0 2006.231.07:54:11.61#ibcon#about to read 4, iclass 3, count 0 2006.231.07:54:11.61#ibcon#read 4, iclass 3, count 0 2006.231.07:54:11.61#ibcon#about to read 5, iclass 3, count 0 2006.231.07:54:11.61#ibcon#read 5, iclass 3, count 0 2006.231.07:54:11.61#ibcon#about to read 6, iclass 3, count 0 2006.231.07:54:11.61#ibcon#read 6, iclass 3, count 0 2006.231.07:54:11.61#ibcon#end of sib2, iclass 3, count 0 2006.231.07:54:11.61#ibcon#*mode == 0, iclass 3, count 0 2006.231.07:54:11.61#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.07:54:11.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:54:11.61#ibcon#*before write, iclass 3, count 0 2006.231.07:54:11.61#ibcon#enter sib2, iclass 3, count 0 2006.231.07:54:11.61#ibcon#flushed, iclass 3, count 0 2006.231.07:54:11.61#ibcon#about to write, iclass 3, count 0 2006.231.07:54:11.61#ibcon#wrote, iclass 3, count 0 2006.231.07:54:11.61#ibcon#about to read 3, iclass 3, count 0 2006.231.07:54:11.65#ibcon#read 3, iclass 3, count 0 2006.231.07:54:11.65#ibcon#about to read 4, iclass 3, count 0 2006.231.07:54:11.65#ibcon#read 4, iclass 3, count 0 2006.231.07:54:11.65#ibcon#about to read 5, iclass 3, count 0 2006.231.07:54:11.65#ibcon#read 5, iclass 3, count 0 2006.231.07:54:11.65#ibcon#about to read 6, iclass 3, count 0 2006.231.07:54:11.65#ibcon#read 6, iclass 3, count 0 2006.231.07:54:11.65#ibcon#end of sib2, iclass 3, count 0 2006.231.07:54:11.65#ibcon#*after write, iclass 3, count 0 2006.231.07:54:11.65#ibcon#*before return 0, iclass 3, count 0 2006.231.07:54:11.65#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:54:11.65#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.07:54:11.65#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.07:54:11.65#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.07:54:11.65$vc4f8/vb=4,4 2006.231.07:54:11.65#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.07:54:11.65#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.07:54:11.65#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:11.65#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:54:11.71#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:54:11.71#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:54:11.71#ibcon#enter wrdev, iclass 5, count 2 2006.231.07:54:11.71#ibcon#first serial, iclass 5, count 2 2006.231.07:54:11.71#ibcon#enter sib2, iclass 5, count 2 2006.231.07:54:11.71#ibcon#flushed, iclass 5, count 2 2006.231.07:54:11.71#ibcon#about to write, iclass 5, count 2 2006.231.07:54:11.71#ibcon#wrote, iclass 5, count 2 2006.231.07:54:11.71#ibcon#about to read 3, iclass 5, count 2 2006.231.07:54:11.73#ibcon#read 3, iclass 5, count 2 2006.231.07:54:11.73#ibcon#about to read 4, iclass 5, count 2 2006.231.07:54:11.73#ibcon#read 4, iclass 5, count 2 2006.231.07:54:11.73#ibcon#about to read 5, iclass 5, count 2 2006.231.07:54:11.73#ibcon#read 5, iclass 5, count 2 2006.231.07:54:11.73#ibcon#about to read 6, iclass 5, count 2 2006.231.07:54:11.73#ibcon#read 6, iclass 5, count 2 2006.231.07:54:11.73#ibcon#end of sib2, iclass 5, count 2 2006.231.07:54:11.73#ibcon#*mode == 0, iclass 5, count 2 2006.231.07:54:11.73#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.07:54:11.73#ibcon#[27=AT04-04\r\n] 2006.231.07:54:11.73#ibcon#*before write, iclass 5, count 2 2006.231.07:54:11.73#ibcon#enter sib2, iclass 5, count 2 2006.231.07:54:11.73#ibcon#flushed, iclass 5, count 2 2006.231.07:54:11.73#ibcon#about to write, iclass 5, count 2 2006.231.07:54:11.73#ibcon#wrote, iclass 5, count 2 2006.231.07:54:11.73#ibcon#about to read 3, iclass 5, count 2 2006.231.07:54:11.76#ibcon#read 3, iclass 5, count 2 2006.231.07:54:11.76#ibcon#about to read 4, iclass 5, count 2 2006.231.07:54:11.76#ibcon#read 4, iclass 5, count 2 2006.231.07:54:11.76#ibcon#about to read 5, iclass 5, count 2 2006.231.07:54:11.76#ibcon#read 5, iclass 5, count 2 2006.231.07:54:11.76#ibcon#about to read 6, iclass 5, count 2 2006.231.07:54:11.76#ibcon#read 6, iclass 5, count 2 2006.231.07:54:11.76#ibcon#end of sib2, iclass 5, count 2 2006.231.07:54:11.76#ibcon#*after write, iclass 5, count 2 2006.231.07:54:11.76#ibcon#*before return 0, iclass 5, count 2 2006.231.07:54:11.76#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:54:11.76#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.07:54:11.76#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.07:54:11.76#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:11.76#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:54:11.88#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:54:11.88#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:54:11.88#ibcon#enter wrdev, iclass 5, count 0 2006.231.07:54:11.88#ibcon#first serial, iclass 5, count 0 2006.231.07:54:11.88#ibcon#enter sib2, iclass 5, count 0 2006.231.07:54:11.88#ibcon#flushed, iclass 5, count 0 2006.231.07:54:11.88#ibcon#about to write, iclass 5, count 0 2006.231.07:54:11.88#ibcon#wrote, iclass 5, count 0 2006.231.07:54:11.88#ibcon#about to read 3, iclass 5, count 0 2006.231.07:54:11.90#ibcon#read 3, iclass 5, count 0 2006.231.07:54:11.90#ibcon#about to read 4, iclass 5, count 0 2006.231.07:54:11.90#ibcon#read 4, iclass 5, count 0 2006.231.07:54:11.90#ibcon#about to read 5, iclass 5, count 0 2006.231.07:54:11.90#ibcon#read 5, iclass 5, count 0 2006.231.07:54:11.90#ibcon#about to read 6, iclass 5, count 0 2006.231.07:54:11.90#ibcon#read 6, iclass 5, count 0 2006.231.07:54:11.90#ibcon#end of sib2, iclass 5, count 0 2006.231.07:54:11.90#ibcon#*mode == 0, iclass 5, count 0 2006.231.07:54:11.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.07:54:11.90#ibcon#[27=USB\r\n] 2006.231.07:54:11.90#ibcon#*before write, iclass 5, count 0 2006.231.07:54:11.90#ibcon#enter sib2, iclass 5, count 0 2006.231.07:54:11.90#ibcon#flushed, iclass 5, count 0 2006.231.07:54:11.90#ibcon#about to write, iclass 5, count 0 2006.231.07:54:11.90#ibcon#wrote, iclass 5, count 0 2006.231.07:54:11.90#ibcon#about to read 3, iclass 5, count 0 2006.231.07:54:11.93#ibcon#read 3, iclass 5, count 0 2006.231.07:54:11.93#ibcon#about to read 4, iclass 5, count 0 2006.231.07:54:11.93#ibcon#read 4, iclass 5, count 0 2006.231.07:54:11.93#ibcon#about to read 5, iclass 5, count 0 2006.231.07:54:11.93#ibcon#read 5, iclass 5, count 0 2006.231.07:54:11.93#ibcon#about to read 6, iclass 5, count 0 2006.231.07:54:11.93#ibcon#read 6, iclass 5, count 0 2006.231.07:54:11.93#ibcon#end of sib2, iclass 5, count 0 2006.231.07:54:11.93#ibcon#*after write, iclass 5, count 0 2006.231.07:54:11.93#ibcon#*before return 0, iclass 5, count 0 2006.231.07:54:11.93#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:54:11.93#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.07:54:11.93#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.07:54:11.93#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.07:54:11.93$vc4f8/vblo=5,744.99 2006.231.07:54:11.93#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.07:54:11.93#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.07:54:11.93#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:11.93#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:54:11.93#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:54:11.93#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:54:11.93#ibcon#enter wrdev, iclass 7, count 0 2006.231.07:54:11.93#ibcon#first serial, iclass 7, count 0 2006.231.07:54:11.93#ibcon#enter sib2, iclass 7, count 0 2006.231.07:54:11.93#ibcon#flushed, iclass 7, count 0 2006.231.07:54:11.93#ibcon#about to write, iclass 7, count 0 2006.231.07:54:11.93#ibcon#wrote, iclass 7, count 0 2006.231.07:54:11.93#ibcon#about to read 3, iclass 7, count 0 2006.231.07:54:11.95#ibcon#read 3, iclass 7, count 0 2006.231.07:54:11.95#ibcon#about to read 4, iclass 7, count 0 2006.231.07:54:11.95#ibcon#read 4, iclass 7, count 0 2006.231.07:54:11.95#ibcon#about to read 5, iclass 7, count 0 2006.231.07:54:11.95#ibcon#read 5, iclass 7, count 0 2006.231.07:54:11.95#ibcon#about to read 6, iclass 7, count 0 2006.231.07:54:11.95#ibcon#read 6, iclass 7, count 0 2006.231.07:54:11.95#ibcon#end of sib2, iclass 7, count 0 2006.231.07:54:11.95#ibcon#*mode == 0, iclass 7, count 0 2006.231.07:54:11.95#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.07:54:11.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:54:11.95#ibcon#*before write, iclass 7, count 0 2006.231.07:54:11.95#ibcon#enter sib2, iclass 7, count 0 2006.231.07:54:11.95#ibcon#flushed, iclass 7, count 0 2006.231.07:54:11.95#ibcon#about to write, iclass 7, count 0 2006.231.07:54:11.95#ibcon#wrote, iclass 7, count 0 2006.231.07:54:11.95#ibcon#about to read 3, iclass 7, count 0 2006.231.07:54:11.99#ibcon#read 3, iclass 7, count 0 2006.231.07:54:11.99#ibcon#about to read 4, iclass 7, count 0 2006.231.07:54:11.99#ibcon#read 4, iclass 7, count 0 2006.231.07:54:11.99#ibcon#about to read 5, iclass 7, count 0 2006.231.07:54:11.99#ibcon#read 5, iclass 7, count 0 2006.231.07:54:11.99#ibcon#about to read 6, iclass 7, count 0 2006.231.07:54:11.99#ibcon#read 6, iclass 7, count 0 2006.231.07:54:11.99#ibcon#end of sib2, iclass 7, count 0 2006.231.07:54:11.99#ibcon#*after write, iclass 7, count 0 2006.231.07:54:11.99#ibcon#*before return 0, iclass 7, count 0 2006.231.07:54:11.99#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:54:11.99#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.07:54:11.99#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.07:54:11.99#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.07:54:11.99$vc4f8/vb=5,3 2006.231.07:54:11.99#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.07:54:11.99#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.07:54:11.99#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:11.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:54:12.05#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:54:12.05#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:54:12.05#ibcon#enter wrdev, iclass 11, count 2 2006.231.07:54:12.05#ibcon#first serial, iclass 11, count 2 2006.231.07:54:12.05#ibcon#enter sib2, iclass 11, count 2 2006.231.07:54:12.05#ibcon#flushed, iclass 11, count 2 2006.231.07:54:12.05#ibcon#about to write, iclass 11, count 2 2006.231.07:54:12.05#ibcon#wrote, iclass 11, count 2 2006.231.07:54:12.05#ibcon#about to read 3, iclass 11, count 2 2006.231.07:54:12.07#ibcon#read 3, iclass 11, count 2 2006.231.07:54:12.07#ibcon#about to read 4, iclass 11, count 2 2006.231.07:54:12.07#ibcon#read 4, iclass 11, count 2 2006.231.07:54:12.07#ibcon#about to read 5, iclass 11, count 2 2006.231.07:54:12.07#ibcon#read 5, iclass 11, count 2 2006.231.07:54:12.07#ibcon#about to read 6, iclass 11, count 2 2006.231.07:54:12.07#ibcon#read 6, iclass 11, count 2 2006.231.07:54:12.07#ibcon#end of sib2, iclass 11, count 2 2006.231.07:54:12.07#ibcon#*mode == 0, iclass 11, count 2 2006.231.07:54:12.07#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.07:54:12.07#ibcon#[27=AT05-03\r\n] 2006.231.07:54:12.07#ibcon#*before write, iclass 11, count 2 2006.231.07:54:12.07#ibcon#enter sib2, iclass 11, count 2 2006.231.07:54:12.07#ibcon#flushed, iclass 11, count 2 2006.231.07:54:12.07#ibcon#about to write, iclass 11, count 2 2006.231.07:54:12.07#ibcon#wrote, iclass 11, count 2 2006.231.07:54:12.07#ibcon#about to read 3, iclass 11, count 2 2006.231.07:54:12.11#ibcon#read 3, iclass 11, count 2 2006.231.07:54:12.11#ibcon#about to read 4, iclass 11, count 2 2006.231.07:54:12.11#ibcon#read 4, iclass 11, count 2 2006.231.07:54:12.11#ibcon#about to read 5, iclass 11, count 2 2006.231.07:54:12.11#ibcon#read 5, iclass 11, count 2 2006.231.07:54:12.11#ibcon#about to read 6, iclass 11, count 2 2006.231.07:54:12.11#ibcon#read 6, iclass 11, count 2 2006.231.07:54:12.11#ibcon#end of sib2, iclass 11, count 2 2006.231.07:54:12.11#ibcon#*after write, iclass 11, count 2 2006.231.07:54:12.11#ibcon#*before return 0, iclass 11, count 2 2006.231.07:54:12.11#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:54:12.11#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.07:54:12.11#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.07:54:12.11#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:12.11#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:54:12.23#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:54:12.23#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:54:12.23#ibcon#enter wrdev, iclass 11, count 0 2006.231.07:54:12.23#ibcon#first serial, iclass 11, count 0 2006.231.07:54:12.23#ibcon#enter sib2, iclass 11, count 0 2006.231.07:54:12.23#ibcon#flushed, iclass 11, count 0 2006.231.07:54:12.23#ibcon#about to write, iclass 11, count 0 2006.231.07:54:12.23#ibcon#wrote, iclass 11, count 0 2006.231.07:54:12.23#ibcon#about to read 3, iclass 11, count 0 2006.231.07:54:12.25#ibcon#read 3, iclass 11, count 0 2006.231.07:54:12.25#ibcon#about to read 4, iclass 11, count 0 2006.231.07:54:12.25#ibcon#read 4, iclass 11, count 0 2006.231.07:54:12.25#ibcon#about to read 5, iclass 11, count 0 2006.231.07:54:12.25#ibcon#read 5, iclass 11, count 0 2006.231.07:54:12.25#ibcon#about to read 6, iclass 11, count 0 2006.231.07:54:12.25#ibcon#read 6, iclass 11, count 0 2006.231.07:54:12.25#ibcon#end of sib2, iclass 11, count 0 2006.231.07:54:12.25#ibcon#*mode == 0, iclass 11, count 0 2006.231.07:54:12.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.07:54:12.25#ibcon#[27=USB\r\n] 2006.231.07:54:12.25#ibcon#*before write, iclass 11, count 0 2006.231.07:54:12.25#ibcon#enter sib2, iclass 11, count 0 2006.231.07:54:12.25#ibcon#flushed, iclass 11, count 0 2006.231.07:54:12.25#ibcon#about to write, iclass 11, count 0 2006.231.07:54:12.25#ibcon#wrote, iclass 11, count 0 2006.231.07:54:12.25#ibcon#about to read 3, iclass 11, count 0 2006.231.07:54:12.28#ibcon#read 3, iclass 11, count 0 2006.231.07:54:12.28#ibcon#about to read 4, iclass 11, count 0 2006.231.07:54:12.28#ibcon#read 4, iclass 11, count 0 2006.231.07:54:12.28#ibcon#about to read 5, iclass 11, count 0 2006.231.07:54:12.28#ibcon#read 5, iclass 11, count 0 2006.231.07:54:12.28#ibcon#about to read 6, iclass 11, count 0 2006.231.07:54:12.28#ibcon#read 6, iclass 11, count 0 2006.231.07:54:12.28#ibcon#end of sib2, iclass 11, count 0 2006.231.07:54:12.28#ibcon#*after write, iclass 11, count 0 2006.231.07:54:12.28#ibcon#*before return 0, iclass 11, count 0 2006.231.07:54:12.28#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:54:12.28#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.07:54:12.28#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.07:54:12.28#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.07:54:12.28$vc4f8/vblo=6,752.99 2006.231.07:54:12.28#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.07:54:12.28#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.07:54:12.28#ibcon#ireg 17 cls_cnt 0 2006.231.07:54:12.28#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:54:12.28#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:54:12.28#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:54:12.28#ibcon#enter wrdev, iclass 13, count 0 2006.231.07:54:12.28#ibcon#first serial, iclass 13, count 0 2006.231.07:54:12.28#ibcon#enter sib2, iclass 13, count 0 2006.231.07:54:12.28#ibcon#flushed, iclass 13, count 0 2006.231.07:54:12.28#ibcon#about to write, iclass 13, count 0 2006.231.07:54:12.28#ibcon#wrote, iclass 13, count 0 2006.231.07:54:12.28#ibcon#about to read 3, iclass 13, count 0 2006.231.07:54:12.30#ibcon#read 3, iclass 13, count 0 2006.231.07:54:12.30#ibcon#about to read 4, iclass 13, count 0 2006.231.07:54:12.30#ibcon#read 4, iclass 13, count 0 2006.231.07:54:12.30#ibcon#about to read 5, iclass 13, count 0 2006.231.07:54:12.30#ibcon#read 5, iclass 13, count 0 2006.231.07:54:12.30#ibcon#about to read 6, iclass 13, count 0 2006.231.07:54:12.30#ibcon#read 6, iclass 13, count 0 2006.231.07:54:12.30#ibcon#end of sib2, iclass 13, count 0 2006.231.07:54:12.30#ibcon#*mode == 0, iclass 13, count 0 2006.231.07:54:12.30#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.07:54:12.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:54:12.30#ibcon#*before write, iclass 13, count 0 2006.231.07:54:12.30#ibcon#enter sib2, iclass 13, count 0 2006.231.07:54:12.30#ibcon#flushed, iclass 13, count 0 2006.231.07:54:12.30#ibcon#about to write, iclass 13, count 0 2006.231.07:54:12.30#ibcon#wrote, iclass 13, count 0 2006.231.07:54:12.30#ibcon#about to read 3, iclass 13, count 0 2006.231.07:54:12.34#ibcon#read 3, iclass 13, count 0 2006.231.07:54:12.34#ibcon#about to read 4, iclass 13, count 0 2006.231.07:54:12.34#ibcon#read 4, iclass 13, count 0 2006.231.07:54:12.34#ibcon#about to read 5, iclass 13, count 0 2006.231.07:54:12.34#ibcon#read 5, iclass 13, count 0 2006.231.07:54:12.34#ibcon#about to read 6, iclass 13, count 0 2006.231.07:54:12.34#ibcon#read 6, iclass 13, count 0 2006.231.07:54:12.34#ibcon#end of sib2, iclass 13, count 0 2006.231.07:54:12.34#ibcon#*after write, iclass 13, count 0 2006.231.07:54:12.34#ibcon#*before return 0, iclass 13, count 0 2006.231.07:54:12.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:54:12.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.07:54:12.34#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.07:54:12.34#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.07:54:12.34$vc4f8/vb=6,4 2006.231.07:54:12.34#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.07:54:12.34#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.07:54:12.34#ibcon#ireg 11 cls_cnt 2 2006.231.07:54:12.34#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:54:12.40#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:54:12.40#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:54:12.40#ibcon#enter wrdev, iclass 15, count 2 2006.231.07:54:12.40#ibcon#first serial, iclass 15, count 2 2006.231.07:54:12.40#ibcon#enter sib2, iclass 15, count 2 2006.231.07:54:12.40#ibcon#flushed, iclass 15, count 2 2006.231.07:54:12.40#ibcon#about to write, iclass 15, count 2 2006.231.07:54:12.40#ibcon#wrote, iclass 15, count 2 2006.231.07:54:12.40#ibcon#about to read 3, iclass 15, count 2 2006.231.07:54:12.42#ibcon#read 3, iclass 15, count 2 2006.231.07:54:12.42#ibcon#about to read 4, iclass 15, count 2 2006.231.07:54:12.42#ibcon#read 4, iclass 15, count 2 2006.231.07:54:12.42#ibcon#about to read 5, iclass 15, count 2 2006.231.07:54:12.42#ibcon#read 5, iclass 15, count 2 2006.231.07:54:12.42#ibcon#about to read 6, iclass 15, count 2 2006.231.07:54:12.42#ibcon#read 6, iclass 15, count 2 2006.231.07:54:12.42#ibcon#end of sib2, iclass 15, count 2 2006.231.07:54:12.42#ibcon#*mode == 0, iclass 15, count 2 2006.231.07:54:12.42#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.07:54:12.42#ibcon#[27=AT06-04\r\n] 2006.231.07:54:12.42#ibcon#*before write, iclass 15, count 2 2006.231.07:54:12.42#ibcon#enter sib2, iclass 15, count 2 2006.231.07:54:12.42#ibcon#flushed, iclass 15, count 2 2006.231.07:54:12.42#ibcon#about to write, iclass 15, count 2 2006.231.07:54:12.42#ibcon#wrote, iclass 15, count 2 2006.231.07:54:12.42#ibcon#about to read 3, iclass 15, count 2 2006.231.07:54:12.45#ibcon#read 3, iclass 15, count 2 2006.231.07:54:12.45#ibcon#about to read 4, iclass 15, count 2 2006.231.07:54:12.45#ibcon#read 4, iclass 15, count 2 2006.231.07:54:12.45#ibcon#about to read 5, iclass 15, count 2 2006.231.07:54:12.45#ibcon#read 5, iclass 15, count 2 2006.231.07:54:12.45#ibcon#about to read 6, iclass 15, count 2 2006.231.07:54:12.45#ibcon#read 6, iclass 15, count 2 2006.231.07:54:12.45#ibcon#end of sib2, iclass 15, count 2 2006.231.07:54:12.45#ibcon#*after write, iclass 15, count 2 2006.231.07:54:12.45#ibcon#*before return 0, iclass 15, count 2 2006.231.07:54:12.45#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:54:12.45#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.07:54:12.45#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.07:54:12.45#ibcon#ireg 7 cls_cnt 0 2006.231.07:54:12.45#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:54:12.57#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:54:12.57#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:54:12.57#ibcon#enter wrdev, iclass 15, count 0 2006.231.07:54:12.57#ibcon#first serial, iclass 15, count 0 2006.231.07:54:12.57#ibcon#enter sib2, iclass 15, count 0 2006.231.07:54:12.57#ibcon#flushed, iclass 15, count 0 2006.231.07:54:12.57#ibcon#about to write, iclass 15, count 0 2006.231.07:54:12.57#ibcon#wrote, iclass 15, count 0 2006.231.07:54:12.57#ibcon#about to read 3, iclass 15, count 0 2006.231.07:54:12.59#ibcon#read 3, iclass 15, count 0 2006.231.07:54:12.59#ibcon#about to read 4, iclass 15, count 0 2006.231.07:54:12.59#ibcon#read 4, iclass 15, count 0 2006.231.07:54:12.59#ibcon#about to read 5, iclass 15, count 0 2006.231.07:54:12.59#ibcon#read 5, iclass 15, count 0 2006.231.07:54:12.59#ibcon#about to read 6, iclass 15, count 0 2006.231.07:54:12.59#ibcon#read 6, iclass 15, count 0 2006.231.07:54:12.59#ibcon#end of sib2, iclass 15, count 0 2006.231.07:54:12.59#ibcon#*mode == 0, iclass 15, count 0 2006.231.07:54:12.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.07:54:12.59#ibcon#[27=USB\r\n] 2006.231.07:54:12.59#ibcon#*before write, iclass 15, count 0 2006.231.07:54:12.59#ibcon#enter sib2, iclass 15, count 0 2006.231.07:54:12.59#ibcon#flushed, iclass 15, count 0 2006.231.07:54:12.59#ibcon#about to write, iclass 15, count 0 2006.231.07:54:12.59#ibcon#wrote, iclass 15, count 0 2006.231.07:54:12.59#ibcon#about to read 3, iclass 15, count 0 2006.231.07:54:12.62#ibcon#read 3, iclass 15, count 0 2006.231.07:54:12.62#ibcon#about to read 4, iclass 15, count 0 2006.231.07:54:12.62#ibcon#read 4, iclass 15, count 0 2006.231.07:54:12.62#ibcon#about to read 5, iclass 15, count 0 2006.231.07:54:12.62#ibcon#read 5, iclass 15, count 0 2006.231.07:54:12.62#ibcon#about to read 6, iclass 15, count 0 2006.231.07:54:12.62#ibcon#read 6, iclass 15, count 0 2006.231.07:54:12.62#ibcon#end of sib2, iclass 15, count 0 2006.231.07:54:12.62#ibcon#*after write, iclass 15, count 0 2006.231.07:54:12.62#ibcon#*before return 0, iclass 15, count 0 2006.231.07:54:12.62#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:54:12.62#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.07:54:12.62#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.07:54:12.62#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.07:54:12.62$vc4f8/vabw=wide 2006.231.07:54:12.62#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.07:54:12.62#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.07:54:12.62#ibcon#ireg 8 cls_cnt 0 2006.231.07:54:12.62#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:54:12.62#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:54:12.62#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:54:12.62#ibcon#enter wrdev, iclass 17, count 0 2006.231.07:54:12.62#ibcon#first serial, iclass 17, count 0 2006.231.07:54:12.62#ibcon#enter sib2, iclass 17, count 0 2006.231.07:54:12.62#ibcon#flushed, iclass 17, count 0 2006.231.07:54:12.62#ibcon#about to write, iclass 17, count 0 2006.231.07:54:12.62#ibcon#wrote, iclass 17, count 0 2006.231.07:54:12.62#ibcon#about to read 3, iclass 17, count 0 2006.231.07:54:12.64#ibcon#read 3, iclass 17, count 0 2006.231.07:54:12.64#ibcon#about to read 4, iclass 17, count 0 2006.231.07:54:12.64#ibcon#read 4, iclass 17, count 0 2006.231.07:54:12.64#ibcon#about to read 5, iclass 17, count 0 2006.231.07:54:12.64#ibcon#read 5, iclass 17, count 0 2006.231.07:54:12.64#ibcon#about to read 6, iclass 17, count 0 2006.231.07:54:12.64#ibcon#read 6, iclass 17, count 0 2006.231.07:54:12.64#ibcon#end of sib2, iclass 17, count 0 2006.231.07:54:12.64#ibcon#*mode == 0, iclass 17, count 0 2006.231.07:54:12.64#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.07:54:12.64#ibcon#[25=BW32\r\n] 2006.231.07:54:12.64#ibcon#*before write, iclass 17, count 0 2006.231.07:54:12.64#ibcon#enter sib2, iclass 17, count 0 2006.231.07:54:12.64#ibcon#flushed, iclass 17, count 0 2006.231.07:54:12.64#ibcon#about to write, iclass 17, count 0 2006.231.07:54:12.64#ibcon#wrote, iclass 17, count 0 2006.231.07:54:12.64#ibcon#about to read 3, iclass 17, count 0 2006.231.07:54:12.67#ibcon#read 3, iclass 17, count 0 2006.231.07:54:12.67#ibcon#about to read 4, iclass 17, count 0 2006.231.07:54:12.67#ibcon#read 4, iclass 17, count 0 2006.231.07:54:12.67#ibcon#about to read 5, iclass 17, count 0 2006.231.07:54:12.67#ibcon#read 5, iclass 17, count 0 2006.231.07:54:12.67#ibcon#about to read 6, iclass 17, count 0 2006.231.07:54:12.67#ibcon#read 6, iclass 17, count 0 2006.231.07:54:12.67#ibcon#end of sib2, iclass 17, count 0 2006.231.07:54:12.67#ibcon#*after write, iclass 17, count 0 2006.231.07:54:12.67#ibcon#*before return 0, iclass 17, count 0 2006.231.07:54:12.67#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:54:12.67#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.07:54:12.67#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.07:54:12.67#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.07:54:12.67$vc4f8/vbbw=wide 2006.231.07:54:12.67#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.07:54:12.67#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.07:54:12.67#ibcon#ireg 8 cls_cnt 0 2006.231.07:54:12.67#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:54:12.74#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:54:12.74#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:54:12.74#ibcon#enter wrdev, iclass 19, count 0 2006.231.07:54:12.74#ibcon#first serial, iclass 19, count 0 2006.231.07:54:12.74#ibcon#enter sib2, iclass 19, count 0 2006.231.07:54:12.74#ibcon#flushed, iclass 19, count 0 2006.231.07:54:12.74#ibcon#about to write, iclass 19, count 0 2006.231.07:54:12.74#ibcon#wrote, iclass 19, count 0 2006.231.07:54:12.74#ibcon#about to read 3, iclass 19, count 0 2006.231.07:54:12.76#ibcon#read 3, iclass 19, count 0 2006.231.07:54:12.76#ibcon#about to read 4, iclass 19, count 0 2006.231.07:54:12.76#ibcon#read 4, iclass 19, count 0 2006.231.07:54:12.76#ibcon#about to read 5, iclass 19, count 0 2006.231.07:54:12.76#ibcon#read 5, iclass 19, count 0 2006.231.07:54:12.76#ibcon#about to read 6, iclass 19, count 0 2006.231.07:54:12.76#ibcon#read 6, iclass 19, count 0 2006.231.07:54:12.76#ibcon#end of sib2, iclass 19, count 0 2006.231.07:54:12.76#ibcon#*mode == 0, iclass 19, count 0 2006.231.07:54:12.76#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.07:54:12.76#ibcon#[27=BW32\r\n] 2006.231.07:54:12.76#ibcon#*before write, iclass 19, count 0 2006.231.07:54:12.76#ibcon#enter sib2, iclass 19, count 0 2006.231.07:54:12.76#ibcon#flushed, iclass 19, count 0 2006.231.07:54:12.76#ibcon#about to write, iclass 19, count 0 2006.231.07:54:12.76#ibcon#wrote, iclass 19, count 0 2006.231.07:54:12.76#ibcon#about to read 3, iclass 19, count 0 2006.231.07:54:12.79#ibcon#read 3, iclass 19, count 0 2006.231.07:54:12.79#ibcon#about to read 4, iclass 19, count 0 2006.231.07:54:12.79#ibcon#read 4, iclass 19, count 0 2006.231.07:54:12.79#ibcon#about to read 5, iclass 19, count 0 2006.231.07:54:12.79#ibcon#read 5, iclass 19, count 0 2006.231.07:54:12.79#ibcon#about to read 6, iclass 19, count 0 2006.231.07:54:12.79#ibcon#read 6, iclass 19, count 0 2006.231.07:54:12.79#ibcon#end of sib2, iclass 19, count 0 2006.231.07:54:12.79#ibcon#*after write, iclass 19, count 0 2006.231.07:54:12.79#ibcon#*before return 0, iclass 19, count 0 2006.231.07:54:12.79#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:54:12.79#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.07:54:12.79#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.07:54:12.79#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.07:54:12.79$4f8m12a/ifd4f 2006.231.07:54:12.79$ifd4f/lo= 2006.231.07:54:12.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:54:12.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:54:12.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:54:12.79$ifd4f/patch= 2006.231.07:54:12.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:54:12.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:54:12.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:54:12.79$4f8m12a/"form=m,16.000,1:2 2006.231.07:54:12.79$4f8m12a/"tpicd 2006.231.07:54:12.79$4f8m12a/echo=off 2006.231.07:54:12.79$4f8m12a/xlog=off 2006.231.07:54:12.79:!2006.231.07:55:40 2006.231.07:54:23.14#trakl#Source acquired 2006.231.07:54:25.14#flagr#flagr/antenna,acquired 2006.231.07:55:40.00:preob 2006.231.07:55:41.14/onsource/TRACKING 2006.231.07:55:41.14:!2006.231.07:55:50 2006.231.07:55:50.00:data_valid=on 2006.231.07:55:50.00:midob 2006.231.07:55:50.14/onsource/TRACKING 2006.231.07:55:50.14/wx/30.55,1004.4,85 2006.231.07:55:50.30/cable/+6.3708E-03 2006.231.07:55:51.39/va/01,08,usb,yes,29,31 2006.231.07:55:51.39/va/02,07,usb,yes,29,31 2006.231.07:55:51.39/va/03,08,usb,yes,22,22 2006.231.07:55:51.39/va/04,07,usb,yes,31,33 2006.231.07:55:51.39/va/05,07,usb,yes,34,36 2006.231.07:55:51.39/va/06,06,usb,yes,33,33 2006.231.07:55:51.39/va/07,06,usb,yes,34,34 2006.231.07:55:51.39/va/08,06,usb,yes,36,36 2006.231.07:55:51.62/valo/01,532.99,yes,locked 2006.231.07:55:51.62/valo/02,572.99,yes,locked 2006.231.07:55:51.62/valo/03,672.99,yes,locked 2006.231.07:55:51.62/valo/04,832.99,yes,locked 2006.231.07:55:51.62/valo/05,652.99,yes,locked 2006.231.07:55:51.62/valo/06,772.99,yes,locked 2006.231.07:55:51.62/valo/07,832.99,yes,locked 2006.231.07:55:51.62/valo/08,852.99,yes,locked 2006.231.07:55:52.71/vb/01,04,usb,yes,31,29 2006.231.07:55:52.71/vb/02,04,usb,yes,32,34 2006.231.07:55:52.71/vb/03,04,usb,yes,29,33 2006.231.07:55:52.71/vb/04,04,usb,yes,29,30 2006.231.07:55:52.71/vb/05,03,usb,yes,35,39 2006.231.07:55:52.71/vb/06,04,usb,yes,29,32 2006.231.07:55:52.71/vb/07,04,usb,yes,31,31 2006.231.07:55:52.71/vb/08,04,usb,yes,29,32 2006.231.07:55:52.94/vblo/01,632.99,yes,locked 2006.231.07:55:52.94/vblo/02,640.99,yes,locked 2006.231.07:55:52.94/vblo/03,656.99,yes,locked 2006.231.07:55:52.94/vblo/04,712.99,yes,locked 2006.231.07:55:52.94/vblo/05,744.99,yes,locked 2006.231.07:55:52.94/vblo/06,752.99,yes,locked 2006.231.07:55:52.94/vblo/07,734.99,yes,locked 2006.231.07:55:52.94/vblo/08,744.99,yes,locked 2006.231.07:55:53.09/vabw/8 2006.231.07:55:53.24/vbbw/8 2006.231.07:55:53.33/xfe/off,on,12.5 2006.231.07:55:53.71/ifatt/23,28,28,28 2006.231.07:55:54.08/fmout-gps/S +4.47E-07 2006.231.07:55:54.12:!2006.231.07:56:50 2006.231.07:56:50.01:data_valid=off 2006.231.07:56:50.01:postob 2006.231.07:56:50.19/cable/+6.3704E-03 2006.231.07:56:50.19/wx/30.55,1004.4,86 2006.231.07:56:51.08/fmout-gps/S +4.47E-07 2006.231.07:56:51.08:scan_name=231-0759,k06231,60 2006.231.07:56:51.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.231.07:56:51.14#flagr#flagr/antenna,new-source 2006.231.07:56:52.14:checkk5 2006.231.07:56:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.231.07:56:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.231.07:56:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.231.07:56:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.231.07:56:54.01/chk_obsdata//k5ts1/T2310755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:56:54.37/chk_obsdata//k5ts2/T2310755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:56:54.73/chk_obsdata//k5ts3/T2310755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:56:55.10/chk_obsdata//k5ts4/T2310755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.07:56:55.79/k5log//k5ts1_log_newline 2006.231.07:56:56.47/k5log//k5ts2_log_newline 2006.231.07:56:57.15/k5log//k5ts3_log_newline 2006.231.07:56:57.84/k5log//k5ts4_log_newline 2006.231.07:56:57.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.07:56:57.86:4f8m12a=2 2006.231.07:56:57.86$4f8m12a/echo=on 2006.231.07:56:57.86$4f8m12a/pcalon 2006.231.07:56:57.86$pcalon/"no phase cal control is implemented here 2006.231.07:56:57.86$4f8m12a/"tpicd=stop 2006.231.07:56:57.86$4f8m12a/vc4f8 2006.231.07:56:57.86$vc4f8/valo=1,532.99 2006.231.07:56:57.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.07:56:57.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.07:56:57.87#ibcon#ireg 17 cls_cnt 0 2006.231.07:56:57.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:56:57.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:56:57.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:56:57.87#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:56:57.87#ibcon#first serial, iclass 18, count 0 2006.231.07:56:57.87#ibcon#enter sib2, iclass 18, count 0 2006.231.07:56:57.87#ibcon#flushed, iclass 18, count 0 2006.231.07:56:57.87#ibcon#about to write, iclass 18, count 0 2006.231.07:56:57.87#ibcon#wrote, iclass 18, count 0 2006.231.07:56:57.87#ibcon#about to read 3, iclass 18, count 0 2006.231.07:56:57.91#ibcon#read 3, iclass 18, count 0 2006.231.07:56:57.91#ibcon#about to read 4, iclass 18, count 0 2006.231.07:56:57.91#ibcon#read 4, iclass 18, count 0 2006.231.07:56:57.91#ibcon#about to read 5, iclass 18, count 0 2006.231.07:56:57.91#ibcon#read 5, iclass 18, count 0 2006.231.07:56:57.91#ibcon#about to read 6, iclass 18, count 0 2006.231.07:56:57.91#ibcon#read 6, iclass 18, count 0 2006.231.07:56:57.91#ibcon#end of sib2, iclass 18, count 0 2006.231.07:56:57.91#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:56:57.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:56:57.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.07:56:57.91#ibcon#*before write, iclass 18, count 0 2006.231.07:56:57.91#ibcon#enter sib2, iclass 18, count 0 2006.231.07:56:57.91#ibcon#flushed, iclass 18, count 0 2006.231.07:56:57.91#ibcon#about to write, iclass 18, count 0 2006.231.07:56:57.91#ibcon#wrote, iclass 18, count 0 2006.231.07:56:57.91#ibcon#about to read 3, iclass 18, count 0 2006.231.07:56:57.96#ibcon#read 3, iclass 18, count 0 2006.231.07:56:57.96#ibcon#about to read 4, iclass 18, count 0 2006.231.07:56:57.96#ibcon#read 4, iclass 18, count 0 2006.231.07:56:57.96#ibcon#about to read 5, iclass 18, count 0 2006.231.07:56:57.96#ibcon#read 5, iclass 18, count 0 2006.231.07:56:57.96#ibcon#about to read 6, iclass 18, count 0 2006.231.07:56:57.96#ibcon#read 6, iclass 18, count 0 2006.231.07:56:57.96#ibcon#end of sib2, iclass 18, count 0 2006.231.07:56:57.96#ibcon#*after write, iclass 18, count 0 2006.231.07:56:57.96#ibcon#*before return 0, iclass 18, count 0 2006.231.07:56:57.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:56:57.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:56:57.96#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:56:57.96#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:56:57.96$vc4f8/va=1,8 2006.231.07:56:57.96#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.07:56:57.96#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.07:56:57.96#ibcon#ireg 11 cls_cnt 2 2006.231.07:56:57.96#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:56:57.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:56:57.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:56:57.96#ibcon#enter wrdev, iclass 20, count 2 2006.231.07:56:57.96#ibcon#first serial, iclass 20, count 2 2006.231.07:56:57.96#ibcon#enter sib2, iclass 20, count 2 2006.231.07:56:57.96#ibcon#flushed, iclass 20, count 2 2006.231.07:56:57.96#ibcon#about to write, iclass 20, count 2 2006.231.07:56:57.96#ibcon#wrote, iclass 20, count 2 2006.231.07:56:57.96#ibcon#about to read 3, iclass 20, count 2 2006.231.07:56:57.98#ibcon#read 3, iclass 20, count 2 2006.231.07:56:57.98#ibcon#about to read 4, iclass 20, count 2 2006.231.07:56:57.98#ibcon#read 4, iclass 20, count 2 2006.231.07:56:57.98#ibcon#about to read 5, iclass 20, count 2 2006.231.07:56:57.98#ibcon#read 5, iclass 20, count 2 2006.231.07:56:57.98#ibcon#about to read 6, iclass 20, count 2 2006.231.07:56:57.98#ibcon#read 6, iclass 20, count 2 2006.231.07:56:57.98#ibcon#end of sib2, iclass 20, count 2 2006.231.07:56:57.98#ibcon#*mode == 0, iclass 20, count 2 2006.231.07:56:57.98#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.07:56:57.98#ibcon#[25=AT01-08\r\n] 2006.231.07:56:57.98#ibcon#*before write, iclass 20, count 2 2006.231.07:56:57.98#ibcon#enter sib2, iclass 20, count 2 2006.231.07:56:57.98#ibcon#flushed, iclass 20, count 2 2006.231.07:56:57.98#ibcon#about to write, iclass 20, count 2 2006.231.07:56:57.98#ibcon#wrote, iclass 20, count 2 2006.231.07:56:57.98#ibcon#about to read 3, iclass 20, count 2 2006.231.07:56:58.01#ibcon#read 3, iclass 20, count 2 2006.231.07:56:58.01#ibcon#about to read 4, iclass 20, count 2 2006.231.07:56:58.01#ibcon#read 4, iclass 20, count 2 2006.231.07:56:58.01#ibcon#about to read 5, iclass 20, count 2 2006.231.07:56:58.01#ibcon#read 5, iclass 20, count 2 2006.231.07:56:58.01#ibcon#about to read 6, iclass 20, count 2 2006.231.07:56:58.01#ibcon#read 6, iclass 20, count 2 2006.231.07:56:58.01#ibcon#end of sib2, iclass 20, count 2 2006.231.07:56:58.01#ibcon#*after write, iclass 20, count 2 2006.231.07:56:58.01#ibcon#*before return 0, iclass 20, count 2 2006.231.07:56:58.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:56:58.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:56:58.01#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.07:56:58.01#ibcon#ireg 7 cls_cnt 0 2006.231.07:56:58.01#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:56:58.13#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:56:58.13#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:56:58.13#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:56:58.13#ibcon#first serial, iclass 20, count 0 2006.231.07:56:58.13#ibcon#enter sib2, iclass 20, count 0 2006.231.07:56:58.13#ibcon#flushed, iclass 20, count 0 2006.231.07:56:58.13#ibcon#about to write, iclass 20, count 0 2006.231.07:56:58.13#ibcon#wrote, iclass 20, count 0 2006.231.07:56:58.13#ibcon#about to read 3, iclass 20, count 0 2006.231.07:56:58.15#ibcon#read 3, iclass 20, count 0 2006.231.07:56:58.15#ibcon#about to read 4, iclass 20, count 0 2006.231.07:56:58.15#ibcon#read 4, iclass 20, count 0 2006.231.07:56:58.15#ibcon#about to read 5, iclass 20, count 0 2006.231.07:56:58.15#ibcon#read 5, iclass 20, count 0 2006.231.07:56:58.15#ibcon#about to read 6, iclass 20, count 0 2006.231.07:56:58.15#ibcon#read 6, iclass 20, count 0 2006.231.07:56:58.15#ibcon#end of sib2, iclass 20, count 0 2006.231.07:56:58.15#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:56:58.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:56:58.15#ibcon#[25=USB\r\n] 2006.231.07:56:58.15#ibcon#*before write, iclass 20, count 0 2006.231.07:56:58.15#ibcon#enter sib2, iclass 20, count 0 2006.231.07:56:58.15#ibcon#flushed, iclass 20, count 0 2006.231.07:56:58.15#ibcon#about to write, iclass 20, count 0 2006.231.07:56:58.15#ibcon#wrote, iclass 20, count 0 2006.231.07:56:58.15#ibcon#about to read 3, iclass 20, count 0 2006.231.07:56:58.18#ibcon#read 3, iclass 20, count 0 2006.231.07:56:58.18#ibcon#about to read 4, iclass 20, count 0 2006.231.07:56:58.18#ibcon#read 4, iclass 20, count 0 2006.231.07:56:58.18#ibcon#about to read 5, iclass 20, count 0 2006.231.07:56:58.18#ibcon#read 5, iclass 20, count 0 2006.231.07:56:58.18#ibcon#about to read 6, iclass 20, count 0 2006.231.07:56:58.18#ibcon#read 6, iclass 20, count 0 2006.231.07:56:58.18#ibcon#end of sib2, iclass 20, count 0 2006.231.07:56:58.18#ibcon#*after write, iclass 20, count 0 2006.231.07:56:58.18#ibcon#*before return 0, iclass 20, count 0 2006.231.07:56:58.18#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:56:58.18#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:56:58.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:56:58.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:56:58.18$vc4f8/valo=2,572.99 2006.231.07:56:58.18#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.07:56:58.18#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.07:56:58.18#ibcon#ireg 17 cls_cnt 0 2006.231.07:56:58.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:56:58.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:56:58.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:56:58.18#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:56:58.18#ibcon#first serial, iclass 22, count 0 2006.231.07:56:58.18#ibcon#enter sib2, iclass 22, count 0 2006.231.07:56:58.18#ibcon#flushed, iclass 22, count 0 2006.231.07:56:58.18#ibcon#about to write, iclass 22, count 0 2006.231.07:56:58.18#ibcon#wrote, iclass 22, count 0 2006.231.07:56:58.18#ibcon#about to read 3, iclass 22, count 0 2006.231.07:56:58.20#ibcon#read 3, iclass 22, count 0 2006.231.07:56:58.20#ibcon#about to read 4, iclass 22, count 0 2006.231.07:56:58.20#ibcon#read 4, iclass 22, count 0 2006.231.07:56:58.20#ibcon#about to read 5, iclass 22, count 0 2006.231.07:56:58.20#ibcon#read 5, iclass 22, count 0 2006.231.07:56:58.20#ibcon#about to read 6, iclass 22, count 0 2006.231.07:56:58.20#ibcon#read 6, iclass 22, count 0 2006.231.07:56:58.20#ibcon#end of sib2, iclass 22, count 0 2006.231.07:56:58.20#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:56:58.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:56:58.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.07:56:58.20#ibcon#*before write, iclass 22, count 0 2006.231.07:56:58.20#ibcon#enter sib2, iclass 22, count 0 2006.231.07:56:58.20#ibcon#flushed, iclass 22, count 0 2006.231.07:56:58.20#ibcon#about to write, iclass 22, count 0 2006.231.07:56:58.20#ibcon#wrote, iclass 22, count 0 2006.231.07:56:58.20#ibcon#about to read 3, iclass 22, count 0 2006.231.07:56:58.24#ibcon#read 3, iclass 22, count 0 2006.231.07:56:58.24#ibcon#about to read 4, iclass 22, count 0 2006.231.07:56:58.24#ibcon#read 4, iclass 22, count 0 2006.231.07:56:58.24#ibcon#about to read 5, iclass 22, count 0 2006.231.07:56:58.24#ibcon#read 5, iclass 22, count 0 2006.231.07:56:58.24#ibcon#about to read 6, iclass 22, count 0 2006.231.07:56:58.24#ibcon#read 6, iclass 22, count 0 2006.231.07:56:58.24#ibcon#end of sib2, iclass 22, count 0 2006.231.07:56:58.24#ibcon#*after write, iclass 22, count 0 2006.231.07:56:58.24#ibcon#*before return 0, iclass 22, count 0 2006.231.07:56:58.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:56:58.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:56:58.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:56:58.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:56:58.24$vc4f8/va=2,7 2006.231.07:56:58.24#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.07:56:58.24#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.07:56:58.24#ibcon#ireg 11 cls_cnt 2 2006.231.07:56:58.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:56:58.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:56:58.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:56:58.30#ibcon#enter wrdev, iclass 24, count 2 2006.231.07:56:58.30#ibcon#first serial, iclass 24, count 2 2006.231.07:56:58.30#ibcon#enter sib2, iclass 24, count 2 2006.231.07:56:58.30#ibcon#flushed, iclass 24, count 2 2006.231.07:56:58.30#ibcon#about to write, iclass 24, count 2 2006.231.07:56:58.30#ibcon#wrote, iclass 24, count 2 2006.231.07:56:58.30#ibcon#about to read 3, iclass 24, count 2 2006.231.07:56:58.32#ibcon#read 3, iclass 24, count 2 2006.231.07:56:58.32#ibcon#about to read 4, iclass 24, count 2 2006.231.07:56:58.32#ibcon#read 4, iclass 24, count 2 2006.231.07:56:58.32#ibcon#about to read 5, iclass 24, count 2 2006.231.07:56:58.32#ibcon#read 5, iclass 24, count 2 2006.231.07:56:58.32#ibcon#about to read 6, iclass 24, count 2 2006.231.07:56:58.32#ibcon#read 6, iclass 24, count 2 2006.231.07:56:58.32#ibcon#end of sib2, iclass 24, count 2 2006.231.07:56:58.32#ibcon#*mode == 0, iclass 24, count 2 2006.231.07:56:58.32#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.07:56:58.32#ibcon#[25=AT02-07\r\n] 2006.231.07:56:58.32#ibcon#*before write, iclass 24, count 2 2006.231.07:56:58.32#ibcon#enter sib2, iclass 24, count 2 2006.231.07:56:58.32#ibcon#flushed, iclass 24, count 2 2006.231.07:56:58.32#ibcon#about to write, iclass 24, count 2 2006.231.07:56:58.32#ibcon#wrote, iclass 24, count 2 2006.231.07:56:58.32#ibcon#about to read 3, iclass 24, count 2 2006.231.07:56:58.35#ibcon#read 3, iclass 24, count 2 2006.231.07:56:58.35#ibcon#about to read 4, iclass 24, count 2 2006.231.07:56:58.35#ibcon#read 4, iclass 24, count 2 2006.231.07:56:58.35#ibcon#about to read 5, iclass 24, count 2 2006.231.07:56:58.35#ibcon#read 5, iclass 24, count 2 2006.231.07:56:58.35#ibcon#about to read 6, iclass 24, count 2 2006.231.07:56:58.35#ibcon#read 6, iclass 24, count 2 2006.231.07:56:58.35#ibcon#end of sib2, iclass 24, count 2 2006.231.07:56:58.35#ibcon#*after write, iclass 24, count 2 2006.231.07:56:58.35#ibcon#*before return 0, iclass 24, count 2 2006.231.07:56:58.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:56:58.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:56:58.35#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.07:56:58.35#ibcon#ireg 7 cls_cnt 0 2006.231.07:56:58.35#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:56:58.47#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:56:58.47#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:56:58.47#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:56:58.47#ibcon#first serial, iclass 24, count 0 2006.231.07:56:58.47#ibcon#enter sib2, iclass 24, count 0 2006.231.07:56:58.47#ibcon#flushed, iclass 24, count 0 2006.231.07:56:58.47#ibcon#about to write, iclass 24, count 0 2006.231.07:56:58.47#ibcon#wrote, iclass 24, count 0 2006.231.07:56:58.47#ibcon#about to read 3, iclass 24, count 0 2006.231.07:56:58.49#ibcon#read 3, iclass 24, count 0 2006.231.07:56:58.49#ibcon#about to read 4, iclass 24, count 0 2006.231.07:56:58.49#ibcon#read 4, iclass 24, count 0 2006.231.07:56:58.49#ibcon#about to read 5, iclass 24, count 0 2006.231.07:56:58.49#ibcon#read 5, iclass 24, count 0 2006.231.07:56:58.49#ibcon#about to read 6, iclass 24, count 0 2006.231.07:56:58.49#ibcon#read 6, iclass 24, count 0 2006.231.07:56:58.49#ibcon#end of sib2, iclass 24, count 0 2006.231.07:56:58.49#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:56:58.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:56:58.49#ibcon#[25=USB\r\n] 2006.231.07:56:58.49#ibcon#*before write, iclass 24, count 0 2006.231.07:56:58.49#ibcon#enter sib2, iclass 24, count 0 2006.231.07:56:58.49#ibcon#flushed, iclass 24, count 0 2006.231.07:56:58.49#ibcon#about to write, iclass 24, count 0 2006.231.07:56:58.49#ibcon#wrote, iclass 24, count 0 2006.231.07:56:58.49#ibcon#about to read 3, iclass 24, count 0 2006.231.07:56:58.52#ibcon#read 3, iclass 24, count 0 2006.231.07:56:58.52#ibcon#about to read 4, iclass 24, count 0 2006.231.07:56:58.52#ibcon#read 4, iclass 24, count 0 2006.231.07:56:58.52#ibcon#about to read 5, iclass 24, count 0 2006.231.07:56:58.52#ibcon#read 5, iclass 24, count 0 2006.231.07:56:58.52#ibcon#about to read 6, iclass 24, count 0 2006.231.07:56:58.52#ibcon#read 6, iclass 24, count 0 2006.231.07:56:58.52#ibcon#end of sib2, iclass 24, count 0 2006.231.07:56:58.52#ibcon#*after write, iclass 24, count 0 2006.231.07:56:58.52#ibcon#*before return 0, iclass 24, count 0 2006.231.07:56:58.52#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:56:58.52#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:56:58.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:56:58.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:56:58.52$vc4f8/valo=3,672.99 2006.231.07:56:58.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:56:58.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:56:58.52#ibcon#ireg 17 cls_cnt 0 2006.231.07:56:58.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:56:58.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:56:58.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:56:58.52#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:56:58.52#ibcon#first serial, iclass 26, count 0 2006.231.07:56:58.52#ibcon#enter sib2, iclass 26, count 0 2006.231.07:56:58.52#ibcon#flushed, iclass 26, count 0 2006.231.07:56:58.52#ibcon#about to write, iclass 26, count 0 2006.231.07:56:58.52#ibcon#wrote, iclass 26, count 0 2006.231.07:56:58.52#ibcon#about to read 3, iclass 26, count 0 2006.231.07:56:58.54#ibcon#read 3, iclass 26, count 0 2006.231.07:56:58.54#ibcon#about to read 4, iclass 26, count 0 2006.231.07:56:58.54#ibcon#read 4, iclass 26, count 0 2006.231.07:56:58.54#ibcon#about to read 5, iclass 26, count 0 2006.231.07:56:58.54#ibcon#read 5, iclass 26, count 0 2006.231.07:56:58.54#ibcon#about to read 6, iclass 26, count 0 2006.231.07:56:58.54#ibcon#read 6, iclass 26, count 0 2006.231.07:56:58.54#ibcon#end of sib2, iclass 26, count 0 2006.231.07:56:58.54#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:56:58.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:56:58.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.07:56:58.54#ibcon#*before write, iclass 26, count 0 2006.231.07:56:58.54#ibcon#enter sib2, iclass 26, count 0 2006.231.07:56:58.54#ibcon#flushed, iclass 26, count 0 2006.231.07:56:58.54#ibcon#about to write, iclass 26, count 0 2006.231.07:56:58.54#ibcon#wrote, iclass 26, count 0 2006.231.07:56:58.54#ibcon#about to read 3, iclass 26, count 0 2006.231.07:56:58.58#ibcon#read 3, iclass 26, count 0 2006.231.07:56:58.58#ibcon#about to read 4, iclass 26, count 0 2006.231.07:56:58.58#ibcon#read 4, iclass 26, count 0 2006.231.07:56:58.58#ibcon#about to read 5, iclass 26, count 0 2006.231.07:56:58.58#ibcon#read 5, iclass 26, count 0 2006.231.07:56:58.58#ibcon#about to read 6, iclass 26, count 0 2006.231.07:56:58.58#ibcon#read 6, iclass 26, count 0 2006.231.07:56:58.58#ibcon#end of sib2, iclass 26, count 0 2006.231.07:56:58.58#ibcon#*after write, iclass 26, count 0 2006.231.07:56:58.58#ibcon#*before return 0, iclass 26, count 0 2006.231.07:56:58.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:56:58.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:56:58.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:56:58.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:56:58.58$vc4f8/va=3,8 2006.231.07:56:58.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.07:56:58.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.07:56:58.58#ibcon#ireg 11 cls_cnt 2 2006.231.07:56:58.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:56:58.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:56:58.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:56:58.64#ibcon#enter wrdev, iclass 28, count 2 2006.231.07:56:58.64#ibcon#first serial, iclass 28, count 2 2006.231.07:56:58.64#ibcon#enter sib2, iclass 28, count 2 2006.231.07:56:58.64#ibcon#flushed, iclass 28, count 2 2006.231.07:56:58.64#ibcon#about to write, iclass 28, count 2 2006.231.07:56:58.64#ibcon#wrote, iclass 28, count 2 2006.231.07:56:58.64#ibcon#about to read 3, iclass 28, count 2 2006.231.07:56:58.66#ibcon#read 3, iclass 28, count 2 2006.231.07:56:58.66#ibcon#about to read 4, iclass 28, count 2 2006.231.07:56:58.66#ibcon#read 4, iclass 28, count 2 2006.231.07:56:58.66#ibcon#about to read 5, iclass 28, count 2 2006.231.07:56:58.66#ibcon#read 5, iclass 28, count 2 2006.231.07:56:58.66#ibcon#about to read 6, iclass 28, count 2 2006.231.07:56:58.66#ibcon#read 6, iclass 28, count 2 2006.231.07:56:58.66#ibcon#end of sib2, iclass 28, count 2 2006.231.07:56:58.66#ibcon#*mode == 0, iclass 28, count 2 2006.231.07:56:58.66#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.07:56:58.66#ibcon#[25=AT03-08\r\n] 2006.231.07:56:58.66#ibcon#*before write, iclass 28, count 2 2006.231.07:56:58.66#ibcon#enter sib2, iclass 28, count 2 2006.231.07:56:58.66#ibcon#flushed, iclass 28, count 2 2006.231.07:56:58.66#ibcon#about to write, iclass 28, count 2 2006.231.07:56:58.66#ibcon#wrote, iclass 28, count 2 2006.231.07:56:58.66#ibcon#about to read 3, iclass 28, count 2 2006.231.07:56:58.69#ibcon#read 3, iclass 28, count 2 2006.231.07:56:58.69#ibcon#about to read 4, iclass 28, count 2 2006.231.07:56:58.69#ibcon#read 4, iclass 28, count 2 2006.231.07:56:58.69#ibcon#about to read 5, iclass 28, count 2 2006.231.07:56:58.69#ibcon#read 5, iclass 28, count 2 2006.231.07:56:58.69#ibcon#about to read 6, iclass 28, count 2 2006.231.07:56:58.69#ibcon#read 6, iclass 28, count 2 2006.231.07:56:58.69#ibcon#end of sib2, iclass 28, count 2 2006.231.07:56:58.69#ibcon#*after write, iclass 28, count 2 2006.231.07:56:58.69#ibcon#*before return 0, iclass 28, count 2 2006.231.07:56:58.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:56:58.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:56:58.69#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.07:56:58.69#ibcon#ireg 7 cls_cnt 0 2006.231.07:56:58.69#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:56:58.81#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:56:58.81#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:56:58.81#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:56:58.81#ibcon#first serial, iclass 28, count 0 2006.231.07:56:58.81#ibcon#enter sib2, iclass 28, count 0 2006.231.07:56:58.81#ibcon#flushed, iclass 28, count 0 2006.231.07:56:58.81#ibcon#about to write, iclass 28, count 0 2006.231.07:56:58.81#ibcon#wrote, iclass 28, count 0 2006.231.07:56:58.81#ibcon#about to read 3, iclass 28, count 0 2006.231.07:56:58.83#ibcon#read 3, iclass 28, count 0 2006.231.07:56:58.83#ibcon#about to read 4, iclass 28, count 0 2006.231.07:56:58.83#ibcon#read 4, iclass 28, count 0 2006.231.07:56:58.83#ibcon#about to read 5, iclass 28, count 0 2006.231.07:56:58.83#ibcon#read 5, iclass 28, count 0 2006.231.07:56:58.83#ibcon#about to read 6, iclass 28, count 0 2006.231.07:56:58.83#ibcon#read 6, iclass 28, count 0 2006.231.07:56:58.83#ibcon#end of sib2, iclass 28, count 0 2006.231.07:56:58.83#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:56:58.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:56:58.83#ibcon#[25=USB\r\n] 2006.231.07:56:58.83#ibcon#*before write, iclass 28, count 0 2006.231.07:56:58.83#ibcon#enter sib2, iclass 28, count 0 2006.231.07:56:58.83#ibcon#flushed, iclass 28, count 0 2006.231.07:56:58.83#ibcon#about to write, iclass 28, count 0 2006.231.07:56:58.83#ibcon#wrote, iclass 28, count 0 2006.231.07:56:58.83#ibcon#about to read 3, iclass 28, count 0 2006.231.07:56:58.86#ibcon#read 3, iclass 28, count 0 2006.231.07:56:58.86#ibcon#about to read 4, iclass 28, count 0 2006.231.07:56:58.86#ibcon#read 4, iclass 28, count 0 2006.231.07:56:58.86#ibcon#about to read 5, iclass 28, count 0 2006.231.07:56:58.86#ibcon#read 5, iclass 28, count 0 2006.231.07:56:58.86#ibcon#about to read 6, iclass 28, count 0 2006.231.07:56:58.86#ibcon#read 6, iclass 28, count 0 2006.231.07:56:58.86#ibcon#end of sib2, iclass 28, count 0 2006.231.07:56:58.86#ibcon#*after write, iclass 28, count 0 2006.231.07:56:58.86#ibcon#*before return 0, iclass 28, count 0 2006.231.07:56:58.86#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:56:58.86#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:56:58.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:56:58.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:56:58.86$vc4f8/valo=4,832.99 2006.231.07:56:58.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.07:56:58.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.07:56:58.86#ibcon#ireg 17 cls_cnt 0 2006.231.07:56:58.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:56:58.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:56:58.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:56:58.86#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:56:58.86#ibcon#first serial, iclass 30, count 0 2006.231.07:56:58.86#ibcon#enter sib2, iclass 30, count 0 2006.231.07:56:58.86#ibcon#flushed, iclass 30, count 0 2006.231.07:56:58.86#ibcon#about to write, iclass 30, count 0 2006.231.07:56:58.86#ibcon#wrote, iclass 30, count 0 2006.231.07:56:58.86#ibcon#about to read 3, iclass 30, count 0 2006.231.07:56:58.88#ibcon#read 3, iclass 30, count 0 2006.231.07:56:58.88#ibcon#about to read 4, iclass 30, count 0 2006.231.07:56:58.88#ibcon#read 4, iclass 30, count 0 2006.231.07:56:58.88#ibcon#about to read 5, iclass 30, count 0 2006.231.07:56:58.88#ibcon#read 5, iclass 30, count 0 2006.231.07:56:58.88#ibcon#about to read 6, iclass 30, count 0 2006.231.07:56:58.88#ibcon#read 6, iclass 30, count 0 2006.231.07:56:58.88#ibcon#end of sib2, iclass 30, count 0 2006.231.07:56:58.88#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:56:58.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:56:58.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.07:56:58.88#ibcon#*before write, iclass 30, count 0 2006.231.07:56:58.88#ibcon#enter sib2, iclass 30, count 0 2006.231.07:56:58.88#ibcon#flushed, iclass 30, count 0 2006.231.07:56:58.88#ibcon#about to write, iclass 30, count 0 2006.231.07:56:58.88#ibcon#wrote, iclass 30, count 0 2006.231.07:56:58.88#ibcon#about to read 3, iclass 30, count 0 2006.231.07:56:58.92#ibcon#read 3, iclass 30, count 0 2006.231.07:56:58.92#ibcon#about to read 4, iclass 30, count 0 2006.231.07:56:58.92#ibcon#read 4, iclass 30, count 0 2006.231.07:56:58.92#ibcon#about to read 5, iclass 30, count 0 2006.231.07:56:58.92#ibcon#read 5, iclass 30, count 0 2006.231.07:56:58.92#ibcon#about to read 6, iclass 30, count 0 2006.231.07:56:58.92#ibcon#read 6, iclass 30, count 0 2006.231.07:56:58.92#ibcon#end of sib2, iclass 30, count 0 2006.231.07:56:58.92#ibcon#*after write, iclass 30, count 0 2006.231.07:56:58.92#ibcon#*before return 0, iclass 30, count 0 2006.231.07:56:58.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:56:58.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:56:58.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:56:58.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:56:58.92$vc4f8/va=4,7 2006.231.07:56:58.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.07:56:58.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.07:56:58.92#ibcon#ireg 11 cls_cnt 2 2006.231.07:56:58.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:56:58.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:56:58.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:56:58.98#ibcon#enter wrdev, iclass 32, count 2 2006.231.07:56:58.98#ibcon#first serial, iclass 32, count 2 2006.231.07:56:58.98#ibcon#enter sib2, iclass 32, count 2 2006.231.07:56:58.98#ibcon#flushed, iclass 32, count 2 2006.231.07:56:58.98#ibcon#about to write, iclass 32, count 2 2006.231.07:56:58.98#ibcon#wrote, iclass 32, count 2 2006.231.07:56:58.98#ibcon#about to read 3, iclass 32, count 2 2006.231.07:56:59.00#ibcon#read 3, iclass 32, count 2 2006.231.07:56:59.00#ibcon#about to read 4, iclass 32, count 2 2006.231.07:56:59.00#ibcon#read 4, iclass 32, count 2 2006.231.07:56:59.00#ibcon#about to read 5, iclass 32, count 2 2006.231.07:56:59.00#ibcon#read 5, iclass 32, count 2 2006.231.07:56:59.00#ibcon#about to read 6, iclass 32, count 2 2006.231.07:56:59.00#ibcon#read 6, iclass 32, count 2 2006.231.07:56:59.00#ibcon#end of sib2, iclass 32, count 2 2006.231.07:56:59.00#ibcon#*mode == 0, iclass 32, count 2 2006.231.07:56:59.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.07:56:59.00#ibcon#[25=AT04-07\r\n] 2006.231.07:56:59.00#ibcon#*before write, iclass 32, count 2 2006.231.07:56:59.00#ibcon#enter sib2, iclass 32, count 2 2006.231.07:56:59.00#ibcon#flushed, iclass 32, count 2 2006.231.07:56:59.00#ibcon#about to write, iclass 32, count 2 2006.231.07:56:59.00#ibcon#wrote, iclass 32, count 2 2006.231.07:56:59.00#ibcon#about to read 3, iclass 32, count 2 2006.231.07:56:59.03#ibcon#read 3, iclass 32, count 2 2006.231.07:56:59.03#ibcon#about to read 4, iclass 32, count 2 2006.231.07:56:59.03#ibcon#read 4, iclass 32, count 2 2006.231.07:56:59.03#ibcon#about to read 5, iclass 32, count 2 2006.231.07:56:59.03#ibcon#read 5, iclass 32, count 2 2006.231.07:56:59.03#ibcon#about to read 6, iclass 32, count 2 2006.231.07:56:59.03#ibcon#read 6, iclass 32, count 2 2006.231.07:56:59.03#ibcon#end of sib2, iclass 32, count 2 2006.231.07:56:59.03#ibcon#*after write, iclass 32, count 2 2006.231.07:56:59.03#ibcon#*before return 0, iclass 32, count 2 2006.231.07:56:59.03#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:56:59.03#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:56:59.03#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.07:56:59.03#ibcon#ireg 7 cls_cnt 0 2006.231.07:56:59.03#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:56:59.15#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:56:59.15#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:56:59.15#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:56:59.15#ibcon#first serial, iclass 32, count 0 2006.231.07:56:59.15#ibcon#enter sib2, iclass 32, count 0 2006.231.07:56:59.15#ibcon#flushed, iclass 32, count 0 2006.231.07:56:59.15#ibcon#about to write, iclass 32, count 0 2006.231.07:56:59.15#ibcon#wrote, iclass 32, count 0 2006.231.07:56:59.15#ibcon#about to read 3, iclass 32, count 0 2006.231.07:56:59.17#ibcon#read 3, iclass 32, count 0 2006.231.07:56:59.17#ibcon#about to read 4, iclass 32, count 0 2006.231.07:56:59.17#ibcon#read 4, iclass 32, count 0 2006.231.07:56:59.17#ibcon#about to read 5, iclass 32, count 0 2006.231.07:56:59.17#ibcon#read 5, iclass 32, count 0 2006.231.07:56:59.17#ibcon#about to read 6, iclass 32, count 0 2006.231.07:56:59.17#ibcon#read 6, iclass 32, count 0 2006.231.07:56:59.17#ibcon#end of sib2, iclass 32, count 0 2006.231.07:56:59.17#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:56:59.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:56:59.17#ibcon#[25=USB\r\n] 2006.231.07:56:59.17#ibcon#*before write, iclass 32, count 0 2006.231.07:56:59.17#ibcon#enter sib2, iclass 32, count 0 2006.231.07:56:59.17#ibcon#flushed, iclass 32, count 0 2006.231.07:56:59.17#ibcon#about to write, iclass 32, count 0 2006.231.07:56:59.17#ibcon#wrote, iclass 32, count 0 2006.231.07:56:59.17#ibcon#about to read 3, iclass 32, count 0 2006.231.07:56:59.20#ibcon#read 3, iclass 32, count 0 2006.231.07:56:59.20#ibcon#about to read 4, iclass 32, count 0 2006.231.07:56:59.20#ibcon#read 4, iclass 32, count 0 2006.231.07:56:59.20#ibcon#about to read 5, iclass 32, count 0 2006.231.07:56:59.20#ibcon#read 5, iclass 32, count 0 2006.231.07:56:59.20#ibcon#about to read 6, iclass 32, count 0 2006.231.07:56:59.20#ibcon#read 6, iclass 32, count 0 2006.231.07:56:59.20#ibcon#end of sib2, iclass 32, count 0 2006.231.07:56:59.20#ibcon#*after write, iclass 32, count 0 2006.231.07:56:59.20#ibcon#*before return 0, iclass 32, count 0 2006.231.07:56:59.20#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:56:59.20#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:56:59.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:56:59.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:56:59.20$vc4f8/valo=5,652.99 2006.231.07:56:59.20#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.07:56:59.20#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.07:56:59.20#ibcon#ireg 17 cls_cnt 0 2006.231.07:56:59.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:56:59.20#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:56:59.20#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:56:59.20#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:56:59.20#ibcon#first serial, iclass 34, count 0 2006.231.07:56:59.20#ibcon#enter sib2, iclass 34, count 0 2006.231.07:56:59.20#ibcon#flushed, iclass 34, count 0 2006.231.07:56:59.20#ibcon#about to write, iclass 34, count 0 2006.231.07:56:59.20#ibcon#wrote, iclass 34, count 0 2006.231.07:56:59.20#ibcon#about to read 3, iclass 34, count 0 2006.231.07:56:59.22#ibcon#read 3, iclass 34, count 0 2006.231.07:56:59.22#ibcon#about to read 4, iclass 34, count 0 2006.231.07:56:59.22#ibcon#read 4, iclass 34, count 0 2006.231.07:56:59.22#ibcon#about to read 5, iclass 34, count 0 2006.231.07:56:59.22#ibcon#read 5, iclass 34, count 0 2006.231.07:56:59.22#ibcon#about to read 6, iclass 34, count 0 2006.231.07:56:59.22#ibcon#read 6, iclass 34, count 0 2006.231.07:56:59.22#ibcon#end of sib2, iclass 34, count 0 2006.231.07:56:59.22#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:56:59.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:56:59.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.07:56:59.22#ibcon#*before write, iclass 34, count 0 2006.231.07:56:59.22#ibcon#enter sib2, iclass 34, count 0 2006.231.07:56:59.22#ibcon#flushed, iclass 34, count 0 2006.231.07:56:59.22#ibcon#about to write, iclass 34, count 0 2006.231.07:56:59.22#ibcon#wrote, iclass 34, count 0 2006.231.07:56:59.22#ibcon#about to read 3, iclass 34, count 0 2006.231.07:56:59.26#ibcon#read 3, iclass 34, count 0 2006.231.07:56:59.26#ibcon#about to read 4, iclass 34, count 0 2006.231.07:56:59.26#ibcon#read 4, iclass 34, count 0 2006.231.07:56:59.26#ibcon#about to read 5, iclass 34, count 0 2006.231.07:56:59.26#ibcon#read 5, iclass 34, count 0 2006.231.07:56:59.26#ibcon#about to read 6, iclass 34, count 0 2006.231.07:56:59.26#ibcon#read 6, iclass 34, count 0 2006.231.07:56:59.26#ibcon#end of sib2, iclass 34, count 0 2006.231.07:56:59.26#ibcon#*after write, iclass 34, count 0 2006.231.07:56:59.26#ibcon#*before return 0, iclass 34, count 0 2006.231.07:56:59.26#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:56:59.26#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:56:59.26#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:56:59.26#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:56:59.26$vc4f8/va=5,7 2006.231.07:56:59.26#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.07:56:59.26#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.07:56:59.26#ibcon#ireg 11 cls_cnt 2 2006.231.07:56:59.26#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:56:59.32#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:56:59.32#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:56:59.32#ibcon#enter wrdev, iclass 36, count 2 2006.231.07:56:59.32#ibcon#first serial, iclass 36, count 2 2006.231.07:56:59.32#ibcon#enter sib2, iclass 36, count 2 2006.231.07:56:59.32#ibcon#flushed, iclass 36, count 2 2006.231.07:56:59.32#ibcon#about to write, iclass 36, count 2 2006.231.07:56:59.32#ibcon#wrote, iclass 36, count 2 2006.231.07:56:59.32#ibcon#about to read 3, iclass 36, count 2 2006.231.07:56:59.34#ibcon#read 3, iclass 36, count 2 2006.231.07:56:59.34#ibcon#about to read 4, iclass 36, count 2 2006.231.07:56:59.34#ibcon#read 4, iclass 36, count 2 2006.231.07:56:59.34#ibcon#about to read 5, iclass 36, count 2 2006.231.07:56:59.34#ibcon#read 5, iclass 36, count 2 2006.231.07:56:59.34#ibcon#about to read 6, iclass 36, count 2 2006.231.07:56:59.34#ibcon#read 6, iclass 36, count 2 2006.231.07:56:59.34#ibcon#end of sib2, iclass 36, count 2 2006.231.07:56:59.34#ibcon#*mode == 0, iclass 36, count 2 2006.231.07:56:59.34#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.07:56:59.34#ibcon#[25=AT05-07\r\n] 2006.231.07:56:59.34#ibcon#*before write, iclass 36, count 2 2006.231.07:56:59.34#ibcon#enter sib2, iclass 36, count 2 2006.231.07:56:59.34#ibcon#flushed, iclass 36, count 2 2006.231.07:56:59.34#ibcon#about to write, iclass 36, count 2 2006.231.07:56:59.34#ibcon#wrote, iclass 36, count 2 2006.231.07:56:59.34#ibcon#about to read 3, iclass 36, count 2 2006.231.07:56:59.37#ibcon#read 3, iclass 36, count 2 2006.231.07:56:59.37#ibcon#about to read 4, iclass 36, count 2 2006.231.07:56:59.37#ibcon#read 4, iclass 36, count 2 2006.231.07:56:59.37#ibcon#about to read 5, iclass 36, count 2 2006.231.07:56:59.37#ibcon#read 5, iclass 36, count 2 2006.231.07:56:59.37#ibcon#about to read 6, iclass 36, count 2 2006.231.07:56:59.37#ibcon#read 6, iclass 36, count 2 2006.231.07:56:59.37#ibcon#end of sib2, iclass 36, count 2 2006.231.07:56:59.37#ibcon#*after write, iclass 36, count 2 2006.231.07:56:59.37#ibcon#*before return 0, iclass 36, count 2 2006.231.07:56:59.37#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:56:59.37#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:56:59.37#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.07:56:59.37#ibcon#ireg 7 cls_cnt 0 2006.231.07:56:59.37#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:56:59.49#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:56:59.49#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:56:59.49#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:56:59.49#ibcon#first serial, iclass 36, count 0 2006.231.07:56:59.49#ibcon#enter sib2, iclass 36, count 0 2006.231.07:56:59.49#ibcon#flushed, iclass 36, count 0 2006.231.07:56:59.49#ibcon#about to write, iclass 36, count 0 2006.231.07:56:59.49#ibcon#wrote, iclass 36, count 0 2006.231.07:56:59.49#ibcon#about to read 3, iclass 36, count 0 2006.231.07:56:59.51#ibcon#read 3, iclass 36, count 0 2006.231.07:56:59.51#ibcon#about to read 4, iclass 36, count 0 2006.231.07:56:59.51#ibcon#read 4, iclass 36, count 0 2006.231.07:56:59.51#ibcon#about to read 5, iclass 36, count 0 2006.231.07:56:59.51#ibcon#read 5, iclass 36, count 0 2006.231.07:56:59.51#ibcon#about to read 6, iclass 36, count 0 2006.231.07:56:59.51#ibcon#read 6, iclass 36, count 0 2006.231.07:56:59.51#ibcon#end of sib2, iclass 36, count 0 2006.231.07:56:59.51#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:56:59.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:56:59.51#ibcon#[25=USB\r\n] 2006.231.07:56:59.51#ibcon#*before write, iclass 36, count 0 2006.231.07:56:59.51#ibcon#enter sib2, iclass 36, count 0 2006.231.07:56:59.51#ibcon#flushed, iclass 36, count 0 2006.231.07:56:59.51#ibcon#about to write, iclass 36, count 0 2006.231.07:56:59.51#ibcon#wrote, iclass 36, count 0 2006.231.07:56:59.51#ibcon#about to read 3, iclass 36, count 0 2006.231.07:56:59.54#ibcon#read 3, iclass 36, count 0 2006.231.07:56:59.54#ibcon#about to read 4, iclass 36, count 0 2006.231.07:56:59.54#ibcon#read 4, iclass 36, count 0 2006.231.07:56:59.54#ibcon#about to read 5, iclass 36, count 0 2006.231.07:56:59.54#ibcon#read 5, iclass 36, count 0 2006.231.07:56:59.54#ibcon#about to read 6, iclass 36, count 0 2006.231.07:56:59.54#ibcon#read 6, iclass 36, count 0 2006.231.07:56:59.54#ibcon#end of sib2, iclass 36, count 0 2006.231.07:56:59.54#ibcon#*after write, iclass 36, count 0 2006.231.07:56:59.54#ibcon#*before return 0, iclass 36, count 0 2006.231.07:56:59.54#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:56:59.54#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:56:59.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:56:59.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:56:59.54$vc4f8/valo=6,772.99 2006.231.07:56:59.54#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.07:56:59.54#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.07:56:59.54#ibcon#ireg 17 cls_cnt 0 2006.231.07:56:59.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:56:59.54#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:56:59.54#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:56:59.54#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:56:59.54#ibcon#first serial, iclass 38, count 0 2006.231.07:56:59.54#ibcon#enter sib2, iclass 38, count 0 2006.231.07:56:59.54#ibcon#flushed, iclass 38, count 0 2006.231.07:56:59.54#ibcon#about to write, iclass 38, count 0 2006.231.07:56:59.54#ibcon#wrote, iclass 38, count 0 2006.231.07:56:59.54#ibcon#about to read 3, iclass 38, count 0 2006.231.07:56:59.56#ibcon#read 3, iclass 38, count 0 2006.231.07:56:59.56#ibcon#about to read 4, iclass 38, count 0 2006.231.07:56:59.56#ibcon#read 4, iclass 38, count 0 2006.231.07:56:59.56#ibcon#about to read 5, iclass 38, count 0 2006.231.07:56:59.56#ibcon#read 5, iclass 38, count 0 2006.231.07:56:59.56#ibcon#about to read 6, iclass 38, count 0 2006.231.07:56:59.56#ibcon#read 6, iclass 38, count 0 2006.231.07:56:59.56#ibcon#end of sib2, iclass 38, count 0 2006.231.07:56:59.56#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:56:59.56#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:56:59.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.07:56:59.56#ibcon#*before write, iclass 38, count 0 2006.231.07:56:59.56#ibcon#enter sib2, iclass 38, count 0 2006.231.07:56:59.56#ibcon#flushed, iclass 38, count 0 2006.231.07:56:59.56#ibcon#about to write, iclass 38, count 0 2006.231.07:56:59.56#ibcon#wrote, iclass 38, count 0 2006.231.07:56:59.56#ibcon#about to read 3, iclass 38, count 0 2006.231.07:56:59.60#ibcon#read 3, iclass 38, count 0 2006.231.07:56:59.60#ibcon#about to read 4, iclass 38, count 0 2006.231.07:56:59.60#ibcon#read 4, iclass 38, count 0 2006.231.07:56:59.60#ibcon#about to read 5, iclass 38, count 0 2006.231.07:56:59.60#ibcon#read 5, iclass 38, count 0 2006.231.07:56:59.60#ibcon#about to read 6, iclass 38, count 0 2006.231.07:56:59.60#ibcon#read 6, iclass 38, count 0 2006.231.07:56:59.60#ibcon#end of sib2, iclass 38, count 0 2006.231.07:56:59.60#ibcon#*after write, iclass 38, count 0 2006.231.07:56:59.60#ibcon#*before return 0, iclass 38, count 0 2006.231.07:56:59.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:56:59.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:56:59.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:56:59.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:56:59.60$vc4f8/va=6,6 2006.231.07:56:59.60#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.07:56:59.60#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.07:56:59.60#ibcon#ireg 11 cls_cnt 2 2006.231.07:56:59.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:56:59.66#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:56:59.66#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:56:59.66#ibcon#enter wrdev, iclass 40, count 2 2006.231.07:56:59.66#ibcon#first serial, iclass 40, count 2 2006.231.07:56:59.66#ibcon#enter sib2, iclass 40, count 2 2006.231.07:56:59.66#ibcon#flushed, iclass 40, count 2 2006.231.07:56:59.66#ibcon#about to write, iclass 40, count 2 2006.231.07:56:59.66#ibcon#wrote, iclass 40, count 2 2006.231.07:56:59.66#ibcon#about to read 3, iclass 40, count 2 2006.231.07:56:59.68#ibcon#read 3, iclass 40, count 2 2006.231.07:56:59.68#ibcon#about to read 4, iclass 40, count 2 2006.231.07:56:59.68#ibcon#read 4, iclass 40, count 2 2006.231.07:56:59.68#ibcon#about to read 5, iclass 40, count 2 2006.231.07:56:59.68#ibcon#read 5, iclass 40, count 2 2006.231.07:56:59.68#ibcon#about to read 6, iclass 40, count 2 2006.231.07:56:59.68#ibcon#read 6, iclass 40, count 2 2006.231.07:56:59.68#ibcon#end of sib2, iclass 40, count 2 2006.231.07:56:59.68#ibcon#*mode == 0, iclass 40, count 2 2006.231.07:56:59.68#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.07:56:59.68#ibcon#[25=AT06-06\r\n] 2006.231.07:56:59.68#ibcon#*before write, iclass 40, count 2 2006.231.07:56:59.68#ibcon#enter sib2, iclass 40, count 2 2006.231.07:56:59.68#ibcon#flushed, iclass 40, count 2 2006.231.07:56:59.68#ibcon#about to write, iclass 40, count 2 2006.231.07:56:59.68#ibcon#wrote, iclass 40, count 2 2006.231.07:56:59.68#ibcon#about to read 3, iclass 40, count 2 2006.231.07:56:59.71#ibcon#read 3, iclass 40, count 2 2006.231.07:56:59.71#ibcon#about to read 4, iclass 40, count 2 2006.231.07:56:59.71#ibcon#read 4, iclass 40, count 2 2006.231.07:56:59.71#ibcon#about to read 5, iclass 40, count 2 2006.231.07:56:59.71#ibcon#read 5, iclass 40, count 2 2006.231.07:56:59.71#ibcon#about to read 6, iclass 40, count 2 2006.231.07:56:59.71#ibcon#read 6, iclass 40, count 2 2006.231.07:56:59.71#ibcon#end of sib2, iclass 40, count 2 2006.231.07:56:59.71#ibcon#*after write, iclass 40, count 2 2006.231.07:56:59.71#ibcon#*before return 0, iclass 40, count 2 2006.231.07:56:59.71#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:56:59.71#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.07:56:59.71#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.07:56:59.71#ibcon#ireg 7 cls_cnt 0 2006.231.07:56:59.71#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:56:59.83#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:56:59.83#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:56:59.83#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:56:59.83#ibcon#first serial, iclass 40, count 0 2006.231.07:56:59.83#ibcon#enter sib2, iclass 40, count 0 2006.231.07:56:59.83#ibcon#flushed, iclass 40, count 0 2006.231.07:56:59.83#ibcon#about to write, iclass 40, count 0 2006.231.07:56:59.83#ibcon#wrote, iclass 40, count 0 2006.231.07:56:59.83#ibcon#about to read 3, iclass 40, count 0 2006.231.07:56:59.85#ibcon#read 3, iclass 40, count 0 2006.231.07:56:59.85#ibcon#about to read 4, iclass 40, count 0 2006.231.07:56:59.85#ibcon#read 4, iclass 40, count 0 2006.231.07:56:59.85#ibcon#about to read 5, iclass 40, count 0 2006.231.07:56:59.85#ibcon#read 5, iclass 40, count 0 2006.231.07:56:59.85#ibcon#about to read 6, iclass 40, count 0 2006.231.07:56:59.85#ibcon#read 6, iclass 40, count 0 2006.231.07:56:59.85#ibcon#end of sib2, iclass 40, count 0 2006.231.07:56:59.85#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:56:59.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:56:59.85#ibcon#[25=USB\r\n] 2006.231.07:56:59.85#ibcon#*before write, iclass 40, count 0 2006.231.07:56:59.85#ibcon#enter sib2, iclass 40, count 0 2006.231.07:56:59.85#ibcon#flushed, iclass 40, count 0 2006.231.07:56:59.85#ibcon#about to write, iclass 40, count 0 2006.231.07:56:59.85#ibcon#wrote, iclass 40, count 0 2006.231.07:56:59.85#ibcon#about to read 3, iclass 40, count 0 2006.231.07:56:59.88#ibcon#read 3, iclass 40, count 0 2006.231.07:56:59.88#ibcon#about to read 4, iclass 40, count 0 2006.231.07:56:59.88#ibcon#read 4, iclass 40, count 0 2006.231.07:56:59.88#ibcon#about to read 5, iclass 40, count 0 2006.231.07:56:59.88#ibcon#read 5, iclass 40, count 0 2006.231.07:56:59.88#ibcon#about to read 6, iclass 40, count 0 2006.231.07:56:59.88#ibcon#read 6, iclass 40, count 0 2006.231.07:56:59.88#ibcon#end of sib2, iclass 40, count 0 2006.231.07:56:59.88#ibcon#*after write, iclass 40, count 0 2006.231.07:56:59.88#ibcon#*before return 0, iclass 40, count 0 2006.231.07:56:59.88#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:56:59.88#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.07:56:59.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:56:59.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:56:59.88$vc4f8/valo=7,832.99 2006.231.07:56:59.88#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.07:56:59.88#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.07:56:59.88#ibcon#ireg 17 cls_cnt 0 2006.231.07:56:59.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:56:59.88#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:56:59.88#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:56:59.88#ibcon#enter wrdev, iclass 4, count 0 2006.231.07:56:59.88#ibcon#first serial, iclass 4, count 0 2006.231.07:56:59.88#ibcon#enter sib2, iclass 4, count 0 2006.231.07:56:59.88#ibcon#flushed, iclass 4, count 0 2006.231.07:56:59.88#ibcon#about to write, iclass 4, count 0 2006.231.07:56:59.88#ibcon#wrote, iclass 4, count 0 2006.231.07:56:59.88#ibcon#about to read 3, iclass 4, count 0 2006.231.07:56:59.90#ibcon#read 3, iclass 4, count 0 2006.231.07:56:59.90#ibcon#about to read 4, iclass 4, count 0 2006.231.07:56:59.90#ibcon#read 4, iclass 4, count 0 2006.231.07:56:59.90#ibcon#about to read 5, iclass 4, count 0 2006.231.07:56:59.90#ibcon#read 5, iclass 4, count 0 2006.231.07:56:59.90#ibcon#about to read 6, iclass 4, count 0 2006.231.07:56:59.90#ibcon#read 6, iclass 4, count 0 2006.231.07:56:59.90#ibcon#end of sib2, iclass 4, count 0 2006.231.07:56:59.90#ibcon#*mode == 0, iclass 4, count 0 2006.231.07:56:59.90#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.07:56:59.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.07:56:59.90#ibcon#*before write, iclass 4, count 0 2006.231.07:56:59.90#ibcon#enter sib2, iclass 4, count 0 2006.231.07:56:59.90#ibcon#flushed, iclass 4, count 0 2006.231.07:56:59.90#ibcon#about to write, iclass 4, count 0 2006.231.07:56:59.90#ibcon#wrote, iclass 4, count 0 2006.231.07:56:59.90#ibcon#about to read 3, iclass 4, count 0 2006.231.07:56:59.94#ibcon#read 3, iclass 4, count 0 2006.231.07:56:59.94#ibcon#about to read 4, iclass 4, count 0 2006.231.07:56:59.94#ibcon#read 4, iclass 4, count 0 2006.231.07:56:59.94#ibcon#about to read 5, iclass 4, count 0 2006.231.07:56:59.94#ibcon#read 5, iclass 4, count 0 2006.231.07:56:59.94#ibcon#about to read 6, iclass 4, count 0 2006.231.07:56:59.94#ibcon#read 6, iclass 4, count 0 2006.231.07:56:59.94#ibcon#end of sib2, iclass 4, count 0 2006.231.07:56:59.94#ibcon#*after write, iclass 4, count 0 2006.231.07:56:59.94#ibcon#*before return 0, iclass 4, count 0 2006.231.07:56:59.94#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:56:59.94#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.07:56:59.94#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.07:56:59.94#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.07:56:59.94$vc4f8/va=7,6 2006.231.07:56:59.94#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.07:56:59.94#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.07:56:59.94#ibcon#ireg 11 cls_cnt 2 2006.231.07:56:59.94#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:57:00.00#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:57:00.00#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:57:00.00#ibcon#enter wrdev, iclass 6, count 2 2006.231.07:57:00.00#ibcon#first serial, iclass 6, count 2 2006.231.07:57:00.00#ibcon#enter sib2, iclass 6, count 2 2006.231.07:57:00.00#ibcon#flushed, iclass 6, count 2 2006.231.07:57:00.00#ibcon#about to write, iclass 6, count 2 2006.231.07:57:00.00#ibcon#wrote, iclass 6, count 2 2006.231.07:57:00.00#ibcon#about to read 3, iclass 6, count 2 2006.231.07:57:00.02#ibcon#read 3, iclass 6, count 2 2006.231.07:57:00.02#ibcon#about to read 4, iclass 6, count 2 2006.231.07:57:00.02#ibcon#read 4, iclass 6, count 2 2006.231.07:57:00.02#ibcon#about to read 5, iclass 6, count 2 2006.231.07:57:00.02#ibcon#read 5, iclass 6, count 2 2006.231.07:57:00.02#ibcon#about to read 6, iclass 6, count 2 2006.231.07:57:00.02#ibcon#read 6, iclass 6, count 2 2006.231.07:57:00.02#ibcon#end of sib2, iclass 6, count 2 2006.231.07:57:00.02#ibcon#*mode == 0, iclass 6, count 2 2006.231.07:57:00.02#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.07:57:00.02#ibcon#[25=AT07-06\r\n] 2006.231.07:57:00.02#ibcon#*before write, iclass 6, count 2 2006.231.07:57:00.02#ibcon#enter sib2, iclass 6, count 2 2006.231.07:57:00.02#ibcon#flushed, iclass 6, count 2 2006.231.07:57:00.02#ibcon#about to write, iclass 6, count 2 2006.231.07:57:00.02#ibcon#wrote, iclass 6, count 2 2006.231.07:57:00.02#ibcon#about to read 3, iclass 6, count 2 2006.231.07:57:00.05#ibcon#read 3, iclass 6, count 2 2006.231.07:57:00.05#ibcon#about to read 4, iclass 6, count 2 2006.231.07:57:00.05#ibcon#read 4, iclass 6, count 2 2006.231.07:57:00.05#ibcon#about to read 5, iclass 6, count 2 2006.231.07:57:00.05#ibcon#read 5, iclass 6, count 2 2006.231.07:57:00.05#ibcon#about to read 6, iclass 6, count 2 2006.231.07:57:00.05#ibcon#read 6, iclass 6, count 2 2006.231.07:57:00.05#ibcon#end of sib2, iclass 6, count 2 2006.231.07:57:00.05#ibcon#*after write, iclass 6, count 2 2006.231.07:57:00.05#ibcon#*before return 0, iclass 6, count 2 2006.231.07:57:00.05#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:57:00.05#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.07:57:00.05#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.07:57:00.05#ibcon#ireg 7 cls_cnt 0 2006.231.07:57:00.05#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:57:00.17#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:57:00.17#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:57:00.17#ibcon#enter wrdev, iclass 6, count 0 2006.231.07:57:00.17#ibcon#first serial, iclass 6, count 0 2006.231.07:57:00.17#ibcon#enter sib2, iclass 6, count 0 2006.231.07:57:00.17#ibcon#flushed, iclass 6, count 0 2006.231.07:57:00.17#ibcon#about to write, iclass 6, count 0 2006.231.07:57:00.17#ibcon#wrote, iclass 6, count 0 2006.231.07:57:00.17#ibcon#about to read 3, iclass 6, count 0 2006.231.07:57:00.19#ibcon#read 3, iclass 6, count 0 2006.231.07:57:00.19#ibcon#about to read 4, iclass 6, count 0 2006.231.07:57:00.19#ibcon#read 4, iclass 6, count 0 2006.231.07:57:00.19#ibcon#about to read 5, iclass 6, count 0 2006.231.07:57:00.19#ibcon#read 5, iclass 6, count 0 2006.231.07:57:00.19#ibcon#about to read 6, iclass 6, count 0 2006.231.07:57:00.19#ibcon#read 6, iclass 6, count 0 2006.231.07:57:00.19#ibcon#end of sib2, iclass 6, count 0 2006.231.07:57:00.19#ibcon#*mode == 0, iclass 6, count 0 2006.231.07:57:00.19#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.07:57:00.19#ibcon#[25=USB\r\n] 2006.231.07:57:00.19#ibcon#*before write, iclass 6, count 0 2006.231.07:57:00.19#ibcon#enter sib2, iclass 6, count 0 2006.231.07:57:00.19#ibcon#flushed, iclass 6, count 0 2006.231.07:57:00.19#ibcon#about to write, iclass 6, count 0 2006.231.07:57:00.19#ibcon#wrote, iclass 6, count 0 2006.231.07:57:00.19#ibcon#about to read 3, iclass 6, count 0 2006.231.07:57:00.22#ibcon#read 3, iclass 6, count 0 2006.231.07:57:00.22#ibcon#about to read 4, iclass 6, count 0 2006.231.07:57:00.22#ibcon#read 4, iclass 6, count 0 2006.231.07:57:00.22#ibcon#about to read 5, iclass 6, count 0 2006.231.07:57:00.22#ibcon#read 5, iclass 6, count 0 2006.231.07:57:00.22#ibcon#about to read 6, iclass 6, count 0 2006.231.07:57:00.22#ibcon#read 6, iclass 6, count 0 2006.231.07:57:00.22#ibcon#end of sib2, iclass 6, count 0 2006.231.07:57:00.22#ibcon#*after write, iclass 6, count 0 2006.231.07:57:00.22#ibcon#*before return 0, iclass 6, count 0 2006.231.07:57:00.22#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:57:00.22#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.07:57:00.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.07:57:00.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.07:57:00.22$vc4f8/valo=8,852.99 2006.231.07:57:00.22#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.07:57:00.22#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.07:57:00.22#ibcon#ireg 17 cls_cnt 0 2006.231.07:57:00.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:57:00.22#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:57:00.22#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:57:00.22#ibcon#enter wrdev, iclass 10, count 0 2006.231.07:57:00.22#ibcon#first serial, iclass 10, count 0 2006.231.07:57:00.22#ibcon#enter sib2, iclass 10, count 0 2006.231.07:57:00.22#ibcon#flushed, iclass 10, count 0 2006.231.07:57:00.22#ibcon#about to write, iclass 10, count 0 2006.231.07:57:00.22#ibcon#wrote, iclass 10, count 0 2006.231.07:57:00.22#ibcon#about to read 3, iclass 10, count 0 2006.231.07:57:00.24#ibcon#read 3, iclass 10, count 0 2006.231.07:57:00.24#ibcon#about to read 4, iclass 10, count 0 2006.231.07:57:00.24#ibcon#read 4, iclass 10, count 0 2006.231.07:57:00.24#ibcon#about to read 5, iclass 10, count 0 2006.231.07:57:00.24#ibcon#read 5, iclass 10, count 0 2006.231.07:57:00.24#ibcon#about to read 6, iclass 10, count 0 2006.231.07:57:00.24#ibcon#read 6, iclass 10, count 0 2006.231.07:57:00.24#ibcon#end of sib2, iclass 10, count 0 2006.231.07:57:00.24#ibcon#*mode == 0, iclass 10, count 0 2006.231.07:57:00.24#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.07:57:00.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.07:57:00.24#ibcon#*before write, iclass 10, count 0 2006.231.07:57:00.24#ibcon#enter sib2, iclass 10, count 0 2006.231.07:57:00.24#ibcon#flushed, iclass 10, count 0 2006.231.07:57:00.24#ibcon#about to write, iclass 10, count 0 2006.231.07:57:00.24#ibcon#wrote, iclass 10, count 0 2006.231.07:57:00.24#ibcon#about to read 3, iclass 10, count 0 2006.231.07:57:00.28#ibcon#read 3, iclass 10, count 0 2006.231.07:57:00.28#ibcon#about to read 4, iclass 10, count 0 2006.231.07:57:00.28#ibcon#read 4, iclass 10, count 0 2006.231.07:57:00.28#ibcon#about to read 5, iclass 10, count 0 2006.231.07:57:00.28#ibcon#read 5, iclass 10, count 0 2006.231.07:57:00.28#ibcon#about to read 6, iclass 10, count 0 2006.231.07:57:00.28#ibcon#read 6, iclass 10, count 0 2006.231.07:57:00.28#ibcon#end of sib2, iclass 10, count 0 2006.231.07:57:00.28#ibcon#*after write, iclass 10, count 0 2006.231.07:57:00.28#ibcon#*before return 0, iclass 10, count 0 2006.231.07:57:00.28#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:57:00.28#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.07:57:00.28#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.07:57:00.28#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.07:57:00.28$vc4f8/va=8,6 2006.231.07:57:00.28#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.07:57:00.28#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.07:57:00.28#ibcon#ireg 11 cls_cnt 2 2006.231.07:57:00.28#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:57:00.34#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:57:00.34#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:57:00.34#ibcon#enter wrdev, iclass 12, count 2 2006.231.07:57:00.34#ibcon#first serial, iclass 12, count 2 2006.231.07:57:00.34#ibcon#enter sib2, iclass 12, count 2 2006.231.07:57:00.34#ibcon#flushed, iclass 12, count 2 2006.231.07:57:00.34#ibcon#about to write, iclass 12, count 2 2006.231.07:57:00.34#ibcon#wrote, iclass 12, count 2 2006.231.07:57:00.34#ibcon#about to read 3, iclass 12, count 2 2006.231.07:57:00.36#ibcon#read 3, iclass 12, count 2 2006.231.07:57:00.36#ibcon#about to read 4, iclass 12, count 2 2006.231.07:57:00.36#ibcon#read 4, iclass 12, count 2 2006.231.07:57:00.36#ibcon#about to read 5, iclass 12, count 2 2006.231.07:57:00.36#ibcon#read 5, iclass 12, count 2 2006.231.07:57:00.36#ibcon#about to read 6, iclass 12, count 2 2006.231.07:57:00.36#ibcon#read 6, iclass 12, count 2 2006.231.07:57:00.36#ibcon#end of sib2, iclass 12, count 2 2006.231.07:57:00.36#ibcon#*mode == 0, iclass 12, count 2 2006.231.07:57:00.36#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.07:57:00.36#ibcon#[25=AT08-06\r\n] 2006.231.07:57:00.36#ibcon#*before write, iclass 12, count 2 2006.231.07:57:00.36#ibcon#enter sib2, iclass 12, count 2 2006.231.07:57:00.36#ibcon#flushed, iclass 12, count 2 2006.231.07:57:00.36#ibcon#about to write, iclass 12, count 2 2006.231.07:57:00.36#ibcon#wrote, iclass 12, count 2 2006.231.07:57:00.36#ibcon#about to read 3, iclass 12, count 2 2006.231.07:57:00.39#ibcon#read 3, iclass 12, count 2 2006.231.07:57:00.39#ibcon#about to read 4, iclass 12, count 2 2006.231.07:57:00.39#ibcon#read 4, iclass 12, count 2 2006.231.07:57:00.39#ibcon#about to read 5, iclass 12, count 2 2006.231.07:57:00.39#ibcon#read 5, iclass 12, count 2 2006.231.07:57:00.39#ibcon#about to read 6, iclass 12, count 2 2006.231.07:57:00.39#ibcon#read 6, iclass 12, count 2 2006.231.07:57:00.39#ibcon#end of sib2, iclass 12, count 2 2006.231.07:57:00.39#ibcon#*after write, iclass 12, count 2 2006.231.07:57:00.39#ibcon#*before return 0, iclass 12, count 2 2006.231.07:57:00.39#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:57:00.39#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.07:57:00.39#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.07:57:00.39#ibcon#ireg 7 cls_cnt 0 2006.231.07:57:00.39#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:57:00.51#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:57:00.51#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:57:00.51#ibcon#enter wrdev, iclass 12, count 0 2006.231.07:57:00.51#ibcon#first serial, iclass 12, count 0 2006.231.07:57:00.51#ibcon#enter sib2, iclass 12, count 0 2006.231.07:57:00.51#ibcon#flushed, iclass 12, count 0 2006.231.07:57:00.51#ibcon#about to write, iclass 12, count 0 2006.231.07:57:00.51#ibcon#wrote, iclass 12, count 0 2006.231.07:57:00.51#ibcon#about to read 3, iclass 12, count 0 2006.231.07:57:00.53#ibcon#read 3, iclass 12, count 0 2006.231.07:57:00.53#ibcon#about to read 4, iclass 12, count 0 2006.231.07:57:00.53#ibcon#read 4, iclass 12, count 0 2006.231.07:57:00.53#ibcon#about to read 5, iclass 12, count 0 2006.231.07:57:00.53#ibcon#read 5, iclass 12, count 0 2006.231.07:57:00.53#ibcon#about to read 6, iclass 12, count 0 2006.231.07:57:00.53#ibcon#read 6, iclass 12, count 0 2006.231.07:57:00.53#ibcon#end of sib2, iclass 12, count 0 2006.231.07:57:00.53#ibcon#*mode == 0, iclass 12, count 0 2006.231.07:57:00.53#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.07:57:00.53#ibcon#[25=USB\r\n] 2006.231.07:57:00.53#ibcon#*before write, iclass 12, count 0 2006.231.07:57:00.53#ibcon#enter sib2, iclass 12, count 0 2006.231.07:57:00.53#ibcon#flushed, iclass 12, count 0 2006.231.07:57:00.53#ibcon#about to write, iclass 12, count 0 2006.231.07:57:00.53#ibcon#wrote, iclass 12, count 0 2006.231.07:57:00.53#ibcon#about to read 3, iclass 12, count 0 2006.231.07:57:00.56#ibcon#read 3, iclass 12, count 0 2006.231.07:57:00.56#ibcon#about to read 4, iclass 12, count 0 2006.231.07:57:00.56#ibcon#read 4, iclass 12, count 0 2006.231.07:57:00.56#ibcon#about to read 5, iclass 12, count 0 2006.231.07:57:00.56#ibcon#read 5, iclass 12, count 0 2006.231.07:57:00.56#ibcon#about to read 6, iclass 12, count 0 2006.231.07:57:00.56#ibcon#read 6, iclass 12, count 0 2006.231.07:57:00.56#ibcon#end of sib2, iclass 12, count 0 2006.231.07:57:00.56#ibcon#*after write, iclass 12, count 0 2006.231.07:57:00.56#ibcon#*before return 0, iclass 12, count 0 2006.231.07:57:00.56#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:57:00.56#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.07:57:00.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.07:57:00.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.07:57:00.56$vc4f8/vblo=1,632.99 2006.231.07:57:00.56#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.07:57:00.56#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.07:57:00.56#ibcon#ireg 17 cls_cnt 0 2006.231.07:57:00.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:57:00.56#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:57:00.56#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:57:00.56#ibcon#enter wrdev, iclass 14, count 0 2006.231.07:57:00.56#ibcon#first serial, iclass 14, count 0 2006.231.07:57:00.56#ibcon#enter sib2, iclass 14, count 0 2006.231.07:57:00.56#ibcon#flushed, iclass 14, count 0 2006.231.07:57:00.56#ibcon#about to write, iclass 14, count 0 2006.231.07:57:00.56#ibcon#wrote, iclass 14, count 0 2006.231.07:57:00.56#ibcon#about to read 3, iclass 14, count 0 2006.231.07:57:00.58#ibcon#read 3, iclass 14, count 0 2006.231.07:57:00.58#ibcon#about to read 4, iclass 14, count 0 2006.231.07:57:00.58#ibcon#read 4, iclass 14, count 0 2006.231.07:57:00.58#ibcon#about to read 5, iclass 14, count 0 2006.231.07:57:00.58#ibcon#read 5, iclass 14, count 0 2006.231.07:57:00.58#ibcon#about to read 6, iclass 14, count 0 2006.231.07:57:00.58#ibcon#read 6, iclass 14, count 0 2006.231.07:57:00.58#ibcon#end of sib2, iclass 14, count 0 2006.231.07:57:00.58#ibcon#*mode == 0, iclass 14, count 0 2006.231.07:57:00.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.07:57:00.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.07:57:00.58#ibcon#*before write, iclass 14, count 0 2006.231.07:57:00.58#ibcon#enter sib2, iclass 14, count 0 2006.231.07:57:00.58#ibcon#flushed, iclass 14, count 0 2006.231.07:57:00.58#ibcon#about to write, iclass 14, count 0 2006.231.07:57:00.58#ibcon#wrote, iclass 14, count 0 2006.231.07:57:00.58#ibcon#about to read 3, iclass 14, count 0 2006.231.07:57:00.62#ibcon#read 3, iclass 14, count 0 2006.231.07:57:00.62#ibcon#about to read 4, iclass 14, count 0 2006.231.07:57:00.62#ibcon#read 4, iclass 14, count 0 2006.231.07:57:00.62#ibcon#about to read 5, iclass 14, count 0 2006.231.07:57:00.62#ibcon#read 5, iclass 14, count 0 2006.231.07:57:00.62#ibcon#about to read 6, iclass 14, count 0 2006.231.07:57:00.62#ibcon#read 6, iclass 14, count 0 2006.231.07:57:00.62#ibcon#end of sib2, iclass 14, count 0 2006.231.07:57:00.62#ibcon#*after write, iclass 14, count 0 2006.231.07:57:00.62#ibcon#*before return 0, iclass 14, count 0 2006.231.07:57:00.62#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:57:00.62#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.07:57:00.62#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.07:57:00.62#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.07:57:00.62$vc4f8/vb=1,4 2006.231.07:57:00.62#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.07:57:00.62#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.07:57:00.62#ibcon#ireg 11 cls_cnt 2 2006.231.07:57:00.62#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:57:00.62#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:57:00.62#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:57:00.62#ibcon#enter wrdev, iclass 16, count 2 2006.231.07:57:00.62#ibcon#first serial, iclass 16, count 2 2006.231.07:57:00.62#ibcon#enter sib2, iclass 16, count 2 2006.231.07:57:00.62#ibcon#flushed, iclass 16, count 2 2006.231.07:57:00.62#ibcon#about to write, iclass 16, count 2 2006.231.07:57:00.62#ibcon#wrote, iclass 16, count 2 2006.231.07:57:00.62#ibcon#about to read 3, iclass 16, count 2 2006.231.07:57:00.64#ibcon#read 3, iclass 16, count 2 2006.231.07:57:00.64#ibcon#about to read 4, iclass 16, count 2 2006.231.07:57:00.64#ibcon#read 4, iclass 16, count 2 2006.231.07:57:00.64#ibcon#about to read 5, iclass 16, count 2 2006.231.07:57:00.64#ibcon#read 5, iclass 16, count 2 2006.231.07:57:00.64#ibcon#about to read 6, iclass 16, count 2 2006.231.07:57:00.64#ibcon#read 6, iclass 16, count 2 2006.231.07:57:00.64#ibcon#end of sib2, iclass 16, count 2 2006.231.07:57:00.64#ibcon#*mode == 0, iclass 16, count 2 2006.231.07:57:00.64#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.07:57:00.64#ibcon#[27=AT01-04\r\n] 2006.231.07:57:00.64#ibcon#*before write, iclass 16, count 2 2006.231.07:57:00.64#ibcon#enter sib2, iclass 16, count 2 2006.231.07:57:00.64#ibcon#flushed, iclass 16, count 2 2006.231.07:57:00.64#ibcon#about to write, iclass 16, count 2 2006.231.07:57:00.64#ibcon#wrote, iclass 16, count 2 2006.231.07:57:00.64#ibcon#about to read 3, iclass 16, count 2 2006.231.07:57:00.67#ibcon#read 3, iclass 16, count 2 2006.231.07:57:00.67#ibcon#about to read 4, iclass 16, count 2 2006.231.07:57:00.67#ibcon#read 4, iclass 16, count 2 2006.231.07:57:00.67#ibcon#about to read 5, iclass 16, count 2 2006.231.07:57:00.67#ibcon#read 5, iclass 16, count 2 2006.231.07:57:00.67#ibcon#about to read 6, iclass 16, count 2 2006.231.07:57:00.67#ibcon#read 6, iclass 16, count 2 2006.231.07:57:00.67#ibcon#end of sib2, iclass 16, count 2 2006.231.07:57:00.67#ibcon#*after write, iclass 16, count 2 2006.231.07:57:00.67#ibcon#*before return 0, iclass 16, count 2 2006.231.07:57:00.67#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:57:00.67#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.07:57:00.67#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.07:57:00.67#ibcon#ireg 7 cls_cnt 0 2006.231.07:57:00.67#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:57:00.79#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:57:00.79#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:57:00.79#ibcon#enter wrdev, iclass 16, count 0 2006.231.07:57:00.79#ibcon#first serial, iclass 16, count 0 2006.231.07:57:00.79#ibcon#enter sib2, iclass 16, count 0 2006.231.07:57:00.79#ibcon#flushed, iclass 16, count 0 2006.231.07:57:00.79#ibcon#about to write, iclass 16, count 0 2006.231.07:57:00.79#ibcon#wrote, iclass 16, count 0 2006.231.07:57:00.79#ibcon#about to read 3, iclass 16, count 0 2006.231.07:57:00.81#ibcon#read 3, iclass 16, count 0 2006.231.07:57:00.81#ibcon#about to read 4, iclass 16, count 0 2006.231.07:57:00.81#ibcon#read 4, iclass 16, count 0 2006.231.07:57:00.81#ibcon#about to read 5, iclass 16, count 0 2006.231.07:57:00.81#ibcon#read 5, iclass 16, count 0 2006.231.07:57:00.81#ibcon#about to read 6, iclass 16, count 0 2006.231.07:57:00.81#ibcon#read 6, iclass 16, count 0 2006.231.07:57:00.81#ibcon#end of sib2, iclass 16, count 0 2006.231.07:57:00.81#ibcon#*mode == 0, iclass 16, count 0 2006.231.07:57:00.81#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.07:57:00.81#ibcon#[27=USB\r\n] 2006.231.07:57:00.81#ibcon#*before write, iclass 16, count 0 2006.231.07:57:00.81#ibcon#enter sib2, iclass 16, count 0 2006.231.07:57:00.81#ibcon#flushed, iclass 16, count 0 2006.231.07:57:00.81#ibcon#about to write, iclass 16, count 0 2006.231.07:57:00.81#ibcon#wrote, iclass 16, count 0 2006.231.07:57:00.81#ibcon#about to read 3, iclass 16, count 0 2006.231.07:57:00.84#ibcon#read 3, iclass 16, count 0 2006.231.07:57:00.84#ibcon#about to read 4, iclass 16, count 0 2006.231.07:57:00.84#ibcon#read 4, iclass 16, count 0 2006.231.07:57:00.84#ibcon#about to read 5, iclass 16, count 0 2006.231.07:57:00.84#ibcon#read 5, iclass 16, count 0 2006.231.07:57:00.84#ibcon#about to read 6, iclass 16, count 0 2006.231.07:57:00.84#ibcon#read 6, iclass 16, count 0 2006.231.07:57:00.84#ibcon#end of sib2, iclass 16, count 0 2006.231.07:57:00.84#ibcon#*after write, iclass 16, count 0 2006.231.07:57:00.84#ibcon#*before return 0, iclass 16, count 0 2006.231.07:57:00.84#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:57:00.84#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.07:57:00.84#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.07:57:00.84#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.07:57:00.84$vc4f8/vblo=2,640.99 2006.231.07:57:00.84#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.07:57:00.84#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.07:57:00.84#ibcon#ireg 17 cls_cnt 0 2006.231.07:57:00.84#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:57:00.84#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:57:00.84#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:57:00.84#ibcon#enter wrdev, iclass 18, count 0 2006.231.07:57:00.84#ibcon#first serial, iclass 18, count 0 2006.231.07:57:00.84#ibcon#enter sib2, iclass 18, count 0 2006.231.07:57:00.84#ibcon#flushed, iclass 18, count 0 2006.231.07:57:00.84#ibcon#about to write, iclass 18, count 0 2006.231.07:57:00.84#ibcon#wrote, iclass 18, count 0 2006.231.07:57:00.84#ibcon#about to read 3, iclass 18, count 0 2006.231.07:57:00.86#ibcon#read 3, iclass 18, count 0 2006.231.07:57:00.86#ibcon#about to read 4, iclass 18, count 0 2006.231.07:57:00.86#ibcon#read 4, iclass 18, count 0 2006.231.07:57:00.86#ibcon#about to read 5, iclass 18, count 0 2006.231.07:57:00.86#ibcon#read 5, iclass 18, count 0 2006.231.07:57:00.86#ibcon#about to read 6, iclass 18, count 0 2006.231.07:57:00.86#ibcon#read 6, iclass 18, count 0 2006.231.07:57:00.86#ibcon#end of sib2, iclass 18, count 0 2006.231.07:57:00.86#ibcon#*mode == 0, iclass 18, count 0 2006.231.07:57:00.86#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.07:57:00.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.07:57:00.86#ibcon#*before write, iclass 18, count 0 2006.231.07:57:00.86#ibcon#enter sib2, iclass 18, count 0 2006.231.07:57:00.86#ibcon#flushed, iclass 18, count 0 2006.231.07:57:00.86#ibcon#about to write, iclass 18, count 0 2006.231.07:57:00.86#ibcon#wrote, iclass 18, count 0 2006.231.07:57:00.86#ibcon#about to read 3, iclass 18, count 0 2006.231.07:57:00.90#ibcon#read 3, iclass 18, count 0 2006.231.07:57:00.90#ibcon#about to read 4, iclass 18, count 0 2006.231.07:57:00.90#ibcon#read 4, iclass 18, count 0 2006.231.07:57:00.90#ibcon#about to read 5, iclass 18, count 0 2006.231.07:57:00.90#ibcon#read 5, iclass 18, count 0 2006.231.07:57:00.90#ibcon#about to read 6, iclass 18, count 0 2006.231.07:57:00.90#ibcon#read 6, iclass 18, count 0 2006.231.07:57:00.90#ibcon#end of sib2, iclass 18, count 0 2006.231.07:57:00.90#ibcon#*after write, iclass 18, count 0 2006.231.07:57:00.90#ibcon#*before return 0, iclass 18, count 0 2006.231.07:57:00.90#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:57:00.90#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.07:57:00.90#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.07:57:00.90#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.07:57:00.90$vc4f8/vb=2,4 2006.231.07:57:00.90#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.07:57:00.90#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.07:57:00.90#ibcon#ireg 11 cls_cnt 2 2006.231.07:57:00.90#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:57:00.96#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:57:00.96#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:57:00.96#ibcon#enter wrdev, iclass 20, count 2 2006.231.07:57:00.96#ibcon#first serial, iclass 20, count 2 2006.231.07:57:00.96#ibcon#enter sib2, iclass 20, count 2 2006.231.07:57:00.96#ibcon#flushed, iclass 20, count 2 2006.231.07:57:00.96#ibcon#about to write, iclass 20, count 2 2006.231.07:57:00.96#ibcon#wrote, iclass 20, count 2 2006.231.07:57:00.96#ibcon#about to read 3, iclass 20, count 2 2006.231.07:57:00.98#ibcon#read 3, iclass 20, count 2 2006.231.07:57:00.98#ibcon#about to read 4, iclass 20, count 2 2006.231.07:57:00.98#ibcon#read 4, iclass 20, count 2 2006.231.07:57:00.98#ibcon#about to read 5, iclass 20, count 2 2006.231.07:57:00.98#ibcon#read 5, iclass 20, count 2 2006.231.07:57:00.98#ibcon#about to read 6, iclass 20, count 2 2006.231.07:57:00.98#ibcon#read 6, iclass 20, count 2 2006.231.07:57:00.98#ibcon#end of sib2, iclass 20, count 2 2006.231.07:57:00.98#ibcon#*mode == 0, iclass 20, count 2 2006.231.07:57:00.98#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.07:57:00.98#ibcon#[27=AT02-04\r\n] 2006.231.07:57:00.98#ibcon#*before write, iclass 20, count 2 2006.231.07:57:00.98#ibcon#enter sib2, iclass 20, count 2 2006.231.07:57:00.98#ibcon#flushed, iclass 20, count 2 2006.231.07:57:00.98#ibcon#about to write, iclass 20, count 2 2006.231.07:57:00.98#ibcon#wrote, iclass 20, count 2 2006.231.07:57:00.98#ibcon#about to read 3, iclass 20, count 2 2006.231.07:57:01.01#ibcon#read 3, iclass 20, count 2 2006.231.07:57:01.01#ibcon#about to read 4, iclass 20, count 2 2006.231.07:57:01.01#ibcon#read 4, iclass 20, count 2 2006.231.07:57:01.01#ibcon#about to read 5, iclass 20, count 2 2006.231.07:57:01.01#ibcon#read 5, iclass 20, count 2 2006.231.07:57:01.01#ibcon#about to read 6, iclass 20, count 2 2006.231.07:57:01.01#ibcon#read 6, iclass 20, count 2 2006.231.07:57:01.01#ibcon#end of sib2, iclass 20, count 2 2006.231.07:57:01.01#ibcon#*after write, iclass 20, count 2 2006.231.07:57:01.01#ibcon#*before return 0, iclass 20, count 2 2006.231.07:57:01.01#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:57:01.01#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.07:57:01.01#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.07:57:01.01#ibcon#ireg 7 cls_cnt 0 2006.231.07:57:01.01#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:57:01.13#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:57:01.13#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:57:01.13#ibcon#enter wrdev, iclass 20, count 0 2006.231.07:57:01.13#ibcon#first serial, iclass 20, count 0 2006.231.07:57:01.13#ibcon#enter sib2, iclass 20, count 0 2006.231.07:57:01.13#ibcon#flushed, iclass 20, count 0 2006.231.07:57:01.13#ibcon#about to write, iclass 20, count 0 2006.231.07:57:01.13#ibcon#wrote, iclass 20, count 0 2006.231.07:57:01.13#ibcon#about to read 3, iclass 20, count 0 2006.231.07:57:01.15#ibcon#read 3, iclass 20, count 0 2006.231.07:57:01.15#ibcon#about to read 4, iclass 20, count 0 2006.231.07:57:01.15#ibcon#read 4, iclass 20, count 0 2006.231.07:57:01.15#ibcon#about to read 5, iclass 20, count 0 2006.231.07:57:01.15#ibcon#read 5, iclass 20, count 0 2006.231.07:57:01.15#ibcon#about to read 6, iclass 20, count 0 2006.231.07:57:01.15#ibcon#read 6, iclass 20, count 0 2006.231.07:57:01.15#ibcon#end of sib2, iclass 20, count 0 2006.231.07:57:01.15#ibcon#*mode == 0, iclass 20, count 0 2006.231.07:57:01.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.07:57:01.15#ibcon#[27=USB\r\n] 2006.231.07:57:01.15#ibcon#*before write, iclass 20, count 0 2006.231.07:57:01.15#ibcon#enter sib2, iclass 20, count 0 2006.231.07:57:01.15#ibcon#flushed, iclass 20, count 0 2006.231.07:57:01.15#ibcon#about to write, iclass 20, count 0 2006.231.07:57:01.15#ibcon#wrote, iclass 20, count 0 2006.231.07:57:01.15#ibcon#about to read 3, iclass 20, count 0 2006.231.07:57:01.18#ibcon#read 3, iclass 20, count 0 2006.231.07:57:01.18#ibcon#about to read 4, iclass 20, count 0 2006.231.07:57:01.18#ibcon#read 4, iclass 20, count 0 2006.231.07:57:01.18#ibcon#about to read 5, iclass 20, count 0 2006.231.07:57:01.18#ibcon#read 5, iclass 20, count 0 2006.231.07:57:01.18#ibcon#about to read 6, iclass 20, count 0 2006.231.07:57:01.18#ibcon#read 6, iclass 20, count 0 2006.231.07:57:01.18#ibcon#end of sib2, iclass 20, count 0 2006.231.07:57:01.18#ibcon#*after write, iclass 20, count 0 2006.231.07:57:01.18#ibcon#*before return 0, iclass 20, count 0 2006.231.07:57:01.18#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:57:01.18#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.07:57:01.18#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.07:57:01.18#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.07:57:01.18$vc4f8/vblo=3,656.99 2006.231.07:57:01.18#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.07:57:01.18#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.07:57:01.18#ibcon#ireg 17 cls_cnt 0 2006.231.07:57:01.18#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:57:01.18#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:57:01.18#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:57:01.18#ibcon#enter wrdev, iclass 22, count 0 2006.231.07:57:01.18#ibcon#first serial, iclass 22, count 0 2006.231.07:57:01.18#ibcon#enter sib2, iclass 22, count 0 2006.231.07:57:01.18#ibcon#flushed, iclass 22, count 0 2006.231.07:57:01.18#ibcon#about to write, iclass 22, count 0 2006.231.07:57:01.18#ibcon#wrote, iclass 22, count 0 2006.231.07:57:01.18#ibcon#about to read 3, iclass 22, count 0 2006.231.07:57:01.20#ibcon#read 3, iclass 22, count 0 2006.231.07:57:01.20#ibcon#about to read 4, iclass 22, count 0 2006.231.07:57:01.20#ibcon#read 4, iclass 22, count 0 2006.231.07:57:01.20#ibcon#about to read 5, iclass 22, count 0 2006.231.07:57:01.20#ibcon#read 5, iclass 22, count 0 2006.231.07:57:01.20#ibcon#about to read 6, iclass 22, count 0 2006.231.07:57:01.20#ibcon#read 6, iclass 22, count 0 2006.231.07:57:01.20#ibcon#end of sib2, iclass 22, count 0 2006.231.07:57:01.20#ibcon#*mode == 0, iclass 22, count 0 2006.231.07:57:01.20#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.07:57:01.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.07:57:01.20#ibcon#*before write, iclass 22, count 0 2006.231.07:57:01.20#ibcon#enter sib2, iclass 22, count 0 2006.231.07:57:01.20#ibcon#flushed, iclass 22, count 0 2006.231.07:57:01.20#ibcon#about to write, iclass 22, count 0 2006.231.07:57:01.20#ibcon#wrote, iclass 22, count 0 2006.231.07:57:01.20#ibcon#about to read 3, iclass 22, count 0 2006.231.07:57:01.24#ibcon#read 3, iclass 22, count 0 2006.231.07:57:01.24#ibcon#about to read 4, iclass 22, count 0 2006.231.07:57:01.24#ibcon#read 4, iclass 22, count 0 2006.231.07:57:01.24#ibcon#about to read 5, iclass 22, count 0 2006.231.07:57:01.24#ibcon#read 5, iclass 22, count 0 2006.231.07:57:01.24#ibcon#about to read 6, iclass 22, count 0 2006.231.07:57:01.24#ibcon#read 6, iclass 22, count 0 2006.231.07:57:01.24#ibcon#end of sib2, iclass 22, count 0 2006.231.07:57:01.24#ibcon#*after write, iclass 22, count 0 2006.231.07:57:01.24#ibcon#*before return 0, iclass 22, count 0 2006.231.07:57:01.24#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:57:01.24#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.07:57:01.24#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.07:57:01.24#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.07:57:01.24$vc4f8/vb=3,4 2006.231.07:57:01.24#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.07:57:01.24#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.07:57:01.24#ibcon#ireg 11 cls_cnt 2 2006.231.07:57:01.24#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:57:01.30#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:57:01.30#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:57:01.30#ibcon#enter wrdev, iclass 24, count 2 2006.231.07:57:01.30#ibcon#first serial, iclass 24, count 2 2006.231.07:57:01.30#ibcon#enter sib2, iclass 24, count 2 2006.231.07:57:01.30#ibcon#flushed, iclass 24, count 2 2006.231.07:57:01.30#ibcon#about to write, iclass 24, count 2 2006.231.07:57:01.30#ibcon#wrote, iclass 24, count 2 2006.231.07:57:01.30#ibcon#about to read 3, iclass 24, count 2 2006.231.07:57:01.32#ibcon#read 3, iclass 24, count 2 2006.231.07:57:01.32#ibcon#about to read 4, iclass 24, count 2 2006.231.07:57:01.32#ibcon#read 4, iclass 24, count 2 2006.231.07:57:01.32#ibcon#about to read 5, iclass 24, count 2 2006.231.07:57:01.32#ibcon#read 5, iclass 24, count 2 2006.231.07:57:01.32#ibcon#about to read 6, iclass 24, count 2 2006.231.07:57:01.32#ibcon#read 6, iclass 24, count 2 2006.231.07:57:01.32#ibcon#end of sib2, iclass 24, count 2 2006.231.07:57:01.32#ibcon#*mode == 0, iclass 24, count 2 2006.231.07:57:01.32#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.07:57:01.32#ibcon#[27=AT03-04\r\n] 2006.231.07:57:01.32#ibcon#*before write, iclass 24, count 2 2006.231.07:57:01.32#ibcon#enter sib2, iclass 24, count 2 2006.231.07:57:01.32#ibcon#flushed, iclass 24, count 2 2006.231.07:57:01.32#ibcon#about to write, iclass 24, count 2 2006.231.07:57:01.32#ibcon#wrote, iclass 24, count 2 2006.231.07:57:01.32#ibcon#about to read 3, iclass 24, count 2 2006.231.07:57:01.35#ibcon#read 3, iclass 24, count 2 2006.231.07:57:01.35#ibcon#about to read 4, iclass 24, count 2 2006.231.07:57:01.35#ibcon#read 4, iclass 24, count 2 2006.231.07:57:01.35#ibcon#about to read 5, iclass 24, count 2 2006.231.07:57:01.35#ibcon#read 5, iclass 24, count 2 2006.231.07:57:01.35#ibcon#about to read 6, iclass 24, count 2 2006.231.07:57:01.35#ibcon#read 6, iclass 24, count 2 2006.231.07:57:01.35#ibcon#end of sib2, iclass 24, count 2 2006.231.07:57:01.35#ibcon#*after write, iclass 24, count 2 2006.231.07:57:01.35#ibcon#*before return 0, iclass 24, count 2 2006.231.07:57:01.35#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:57:01.35#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.07:57:01.35#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.07:57:01.35#ibcon#ireg 7 cls_cnt 0 2006.231.07:57:01.35#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:57:01.47#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:57:01.47#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:57:01.47#ibcon#enter wrdev, iclass 24, count 0 2006.231.07:57:01.47#ibcon#first serial, iclass 24, count 0 2006.231.07:57:01.47#ibcon#enter sib2, iclass 24, count 0 2006.231.07:57:01.47#ibcon#flushed, iclass 24, count 0 2006.231.07:57:01.47#ibcon#about to write, iclass 24, count 0 2006.231.07:57:01.47#ibcon#wrote, iclass 24, count 0 2006.231.07:57:01.47#ibcon#about to read 3, iclass 24, count 0 2006.231.07:57:01.49#ibcon#read 3, iclass 24, count 0 2006.231.07:57:01.49#ibcon#about to read 4, iclass 24, count 0 2006.231.07:57:01.49#ibcon#read 4, iclass 24, count 0 2006.231.07:57:01.49#ibcon#about to read 5, iclass 24, count 0 2006.231.07:57:01.49#ibcon#read 5, iclass 24, count 0 2006.231.07:57:01.49#ibcon#about to read 6, iclass 24, count 0 2006.231.07:57:01.49#ibcon#read 6, iclass 24, count 0 2006.231.07:57:01.49#ibcon#end of sib2, iclass 24, count 0 2006.231.07:57:01.49#ibcon#*mode == 0, iclass 24, count 0 2006.231.07:57:01.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.07:57:01.49#ibcon#[27=USB\r\n] 2006.231.07:57:01.49#ibcon#*before write, iclass 24, count 0 2006.231.07:57:01.49#ibcon#enter sib2, iclass 24, count 0 2006.231.07:57:01.49#ibcon#flushed, iclass 24, count 0 2006.231.07:57:01.49#ibcon#about to write, iclass 24, count 0 2006.231.07:57:01.49#ibcon#wrote, iclass 24, count 0 2006.231.07:57:01.49#ibcon#about to read 3, iclass 24, count 0 2006.231.07:57:01.52#ibcon#read 3, iclass 24, count 0 2006.231.07:57:01.52#ibcon#about to read 4, iclass 24, count 0 2006.231.07:57:01.52#ibcon#read 4, iclass 24, count 0 2006.231.07:57:01.52#ibcon#about to read 5, iclass 24, count 0 2006.231.07:57:01.52#ibcon#read 5, iclass 24, count 0 2006.231.07:57:01.52#ibcon#about to read 6, iclass 24, count 0 2006.231.07:57:01.52#ibcon#read 6, iclass 24, count 0 2006.231.07:57:01.52#ibcon#end of sib2, iclass 24, count 0 2006.231.07:57:01.52#ibcon#*after write, iclass 24, count 0 2006.231.07:57:01.52#ibcon#*before return 0, iclass 24, count 0 2006.231.07:57:01.52#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:57:01.52#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.07:57:01.52#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.07:57:01.52#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.07:57:01.52$vc4f8/vblo=4,712.99 2006.231.07:57:01.52#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.07:57:01.52#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.07:57:01.52#ibcon#ireg 17 cls_cnt 0 2006.231.07:57:01.52#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:57:01.52#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:57:01.52#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:57:01.52#ibcon#enter wrdev, iclass 26, count 0 2006.231.07:57:01.52#ibcon#first serial, iclass 26, count 0 2006.231.07:57:01.52#ibcon#enter sib2, iclass 26, count 0 2006.231.07:57:01.52#ibcon#flushed, iclass 26, count 0 2006.231.07:57:01.52#ibcon#about to write, iclass 26, count 0 2006.231.07:57:01.52#ibcon#wrote, iclass 26, count 0 2006.231.07:57:01.52#ibcon#about to read 3, iclass 26, count 0 2006.231.07:57:01.54#ibcon#read 3, iclass 26, count 0 2006.231.07:57:01.54#ibcon#about to read 4, iclass 26, count 0 2006.231.07:57:01.54#ibcon#read 4, iclass 26, count 0 2006.231.07:57:01.54#ibcon#about to read 5, iclass 26, count 0 2006.231.07:57:01.54#ibcon#read 5, iclass 26, count 0 2006.231.07:57:01.54#ibcon#about to read 6, iclass 26, count 0 2006.231.07:57:01.54#ibcon#read 6, iclass 26, count 0 2006.231.07:57:01.54#ibcon#end of sib2, iclass 26, count 0 2006.231.07:57:01.54#ibcon#*mode == 0, iclass 26, count 0 2006.231.07:57:01.54#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.07:57:01.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.07:57:01.54#ibcon#*before write, iclass 26, count 0 2006.231.07:57:01.54#ibcon#enter sib2, iclass 26, count 0 2006.231.07:57:01.54#ibcon#flushed, iclass 26, count 0 2006.231.07:57:01.54#ibcon#about to write, iclass 26, count 0 2006.231.07:57:01.54#ibcon#wrote, iclass 26, count 0 2006.231.07:57:01.54#ibcon#about to read 3, iclass 26, count 0 2006.231.07:57:01.58#ibcon#read 3, iclass 26, count 0 2006.231.07:57:01.58#ibcon#about to read 4, iclass 26, count 0 2006.231.07:57:01.58#ibcon#read 4, iclass 26, count 0 2006.231.07:57:01.58#ibcon#about to read 5, iclass 26, count 0 2006.231.07:57:01.58#ibcon#read 5, iclass 26, count 0 2006.231.07:57:01.58#ibcon#about to read 6, iclass 26, count 0 2006.231.07:57:01.58#ibcon#read 6, iclass 26, count 0 2006.231.07:57:01.58#ibcon#end of sib2, iclass 26, count 0 2006.231.07:57:01.58#ibcon#*after write, iclass 26, count 0 2006.231.07:57:01.58#ibcon#*before return 0, iclass 26, count 0 2006.231.07:57:01.58#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:57:01.58#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.07:57:01.58#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.07:57:01.58#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.07:57:01.58$vc4f8/vb=4,4 2006.231.07:57:01.58#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.07:57:01.58#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.07:57:01.58#ibcon#ireg 11 cls_cnt 2 2006.231.07:57:01.58#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:57:01.64#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:57:01.64#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:57:01.64#ibcon#enter wrdev, iclass 28, count 2 2006.231.07:57:01.64#ibcon#first serial, iclass 28, count 2 2006.231.07:57:01.64#ibcon#enter sib2, iclass 28, count 2 2006.231.07:57:01.64#ibcon#flushed, iclass 28, count 2 2006.231.07:57:01.64#ibcon#about to write, iclass 28, count 2 2006.231.07:57:01.64#ibcon#wrote, iclass 28, count 2 2006.231.07:57:01.64#ibcon#about to read 3, iclass 28, count 2 2006.231.07:57:01.66#ibcon#read 3, iclass 28, count 2 2006.231.07:57:01.66#ibcon#about to read 4, iclass 28, count 2 2006.231.07:57:01.66#ibcon#read 4, iclass 28, count 2 2006.231.07:57:01.66#ibcon#about to read 5, iclass 28, count 2 2006.231.07:57:01.66#ibcon#read 5, iclass 28, count 2 2006.231.07:57:01.66#ibcon#about to read 6, iclass 28, count 2 2006.231.07:57:01.66#ibcon#read 6, iclass 28, count 2 2006.231.07:57:01.66#ibcon#end of sib2, iclass 28, count 2 2006.231.07:57:01.66#ibcon#*mode == 0, iclass 28, count 2 2006.231.07:57:01.66#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.07:57:01.66#ibcon#[27=AT04-04\r\n] 2006.231.07:57:01.66#ibcon#*before write, iclass 28, count 2 2006.231.07:57:01.66#ibcon#enter sib2, iclass 28, count 2 2006.231.07:57:01.66#ibcon#flushed, iclass 28, count 2 2006.231.07:57:01.66#ibcon#about to write, iclass 28, count 2 2006.231.07:57:01.66#ibcon#wrote, iclass 28, count 2 2006.231.07:57:01.66#ibcon#about to read 3, iclass 28, count 2 2006.231.07:57:01.69#ibcon#read 3, iclass 28, count 2 2006.231.07:57:01.69#ibcon#about to read 4, iclass 28, count 2 2006.231.07:57:01.69#ibcon#read 4, iclass 28, count 2 2006.231.07:57:01.69#ibcon#about to read 5, iclass 28, count 2 2006.231.07:57:01.69#ibcon#read 5, iclass 28, count 2 2006.231.07:57:01.69#ibcon#about to read 6, iclass 28, count 2 2006.231.07:57:01.69#ibcon#read 6, iclass 28, count 2 2006.231.07:57:01.69#ibcon#end of sib2, iclass 28, count 2 2006.231.07:57:01.69#ibcon#*after write, iclass 28, count 2 2006.231.07:57:01.69#ibcon#*before return 0, iclass 28, count 2 2006.231.07:57:01.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:57:01.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.07:57:01.69#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.07:57:01.69#ibcon#ireg 7 cls_cnt 0 2006.231.07:57:01.69#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:57:01.81#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:57:01.81#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:57:01.81#ibcon#enter wrdev, iclass 28, count 0 2006.231.07:57:01.81#ibcon#first serial, iclass 28, count 0 2006.231.07:57:01.81#ibcon#enter sib2, iclass 28, count 0 2006.231.07:57:01.81#ibcon#flushed, iclass 28, count 0 2006.231.07:57:01.81#ibcon#about to write, iclass 28, count 0 2006.231.07:57:01.81#ibcon#wrote, iclass 28, count 0 2006.231.07:57:01.81#ibcon#about to read 3, iclass 28, count 0 2006.231.07:57:01.83#ibcon#read 3, iclass 28, count 0 2006.231.07:57:01.83#ibcon#about to read 4, iclass 28, count 0 2006.231.07:57:01.83#ibcon#read 4, iclass 28, count 0 2006.231.07:57:01.83#ibcon#about to read 5, iclass 28, count 0 2006.231.07:57:01.83#ibcon#read 5, iclass 28, count 0 2006.231.07:57:01.83#ibcon#about to read 6, iclass 28, count 0 2006.231.07:57:01.83#ibcon#read 6, iclass 28, count 0 2006.231.07:57:01.83#ibcon#end of sib2, iclass 28, count 0 2006.231.07:57:01.83#ibcon#*mode == 0, iclass 28, count 0 2006.231.07:57:01.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.07:57:01.83#ibcon#[27=USB\r\n] 2006.231.07:57:01.83#ibcon#*before write, iclass 28, count 0 2006.231.07:57:01.83#ibcon#enter sib2, iclass 28, count 0 2006.231.07:57:01.83#ibcon#flushed, iclass 28, count 0 2006.231.07:57:01.83#ibcon#about to write, iclass 28, count 0 2006.231.07:57:01.83#ibcon#wrote, iclass 28, count 0 2006.231.07:57:01.83#ibcon#about to read 3, iclass 28, count 0 2006.231.07:57:01.86#ibcon#read 3, iclass 28, count 0 2006.231.07:57:01.86#ibcon#about to read 4, iclass 28, count 0 2006.231.07:57:01.86#ibcon#read 4, iclass 28, count 0 2006.231.07:57:01.86#ibcon#about to read 5, iclass 28, count 0 2006.231.07:57:01.86#ibcon#read 5, iclass 28, count 0 2006.231.07:57:01.86#ibcon#about to read 6, iclass 28, count 0 2006.231.07:57:01.86#ibcon#read 6, iclass 28, count 0 2006.231.07:57:01.86#ibcon#end of sib2, iclass 28, count 0 2006.231.07:57:01.86#ibcon#*after write, iclass 28, count 0 2006.231.07:57:01.86#ibcon#*before return 0, iclass 28, count 0 2006.231.07:57:01.86#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:57:01.86#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.07:57:01.86#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.07:57:01.86#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.07:57:01.86$vc4f8/vblo=5,744.99 2006.231.07:57:01.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.07:57:01.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.07:57:01.86#ibcon#ireg 17 cls_cnt 0 2006.231.07:57:01.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:57:01.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:57:01.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:57:01.86#ibcon#enter wrdev, iclass 30, count 0 2006.231.07:57:01.86#ibcon#first serial, iclass 30, count 0 2006.231.07:57:01.86#ibcon#enter sib2, iclass 30, count 0 2006.231.07:57:01.86#ibcon#flushed, iclass 30, count 0 2006.231.07:57:01.86#ibcon#about to write, iclass 30, count 0 2006.231.07:57:01.86#ibcon#wrote, iclass 30, count 0 2006.231.07:57:01.86#ibcon#about to read 3, iclass 30, count 0 2006.231.07:57:01.88#ibcon#read 3, iclass 30, count 0 2006.231.07:57:01.88#ibcon#about to read 4, iclass 30, count 0 2006.231.07:57:01.88#ibcon#read 4, iclass 30, count 0 2006.231.07:57:01.88#ibcon#about to read 5, iclass 30, count 0 2006.231.07:57:01.88#ibcon#read 5, iclass 30, count 0 2006.231.07:57:01.88#ibcon#about to read 6, iclass 30, count 0 2006.231.07:57:01.88#ibcon#read 6, iclass 30, count 0 2006.231.07:57:01.88#ibcon#end of sib2, iclass 30, count 0 2006.231.07:57:01.88#ibcon#*mode == 0, iclass 30, count 0 2006.231.07:57:01.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.07:57:01.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.07:57:01.88#ibcon#*before write, iclass 30, count 0 2006.231.07:57:01.88#ibcon#enter sib2, iclass 30, count 0 2006.231.07:57:01.88#ibcon#flushed, iclass 30, count 0 2006.231.07:57:01.88#ibcon#about to write, iclass 30, count 0 2006.231.07:57:01.88#ibcon#wrote, iclass 30, count 0 2006.231.07:57:01.88#ibcon#about to read 3, iclass 30, count 0 2006.231.07:57:01.92#ibcon#read 3, iclass 30, count 0 2006.231.07:57:01.92#ibcon#about to read 4, iclass 30, count 0 2006.231.07:57:01.92#ibcon#read 4, iclass 30, count 0 2006.231.07:57:01.92#ibcon#about to read 5, iclass 30, count 0 2006.231.07:57:01.92#ibcon#read 5, iclass 30, count 0 2006.231.07:57:01.92#ibcon#about to read 6, iclass 30, count 0 2006.231.07:57:01.92#ibcon#read 6, iclass 30, count 0 2006.231.07:57:01.92#ibcon#end of sib2, iclass 30, count 0 2006.231.07:57:01.92#ibcon#*after write, iclass 30, count 0 2006.231.07:57:01.92#ibcon#*before return 0, iclass 30, count 0 2006.231.07:57:01.92#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:57:01.92#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.07:57:01.92#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.07:57:01.92#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.07:57:01.92$vc4f8/vb=5,3 2006.231.07:57:01.92#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.07:57:01.92#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.07:57:01.92#ibcon#ireg 11 cls_cnt 2 2006.231.07:57:01.92#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:57:01.98#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:57:01.98#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:57:01.98#ibcon#enter wrdev, iclass 32, count 2 2006.231.07:57:01.98#ibcon#first serial, iclass 32, count 2 2006.231.07:57:01.98#ibcon#enter sib2, iclass 32, count 2 2006.231.07:57:01.98#ibcon#flushed, iclass 32, count 2 2006.231.07:57:01.98#ibcon#about to write, iclass 32, count 2 2006.231.07:57:01.98#ibcon#wrote, iclass 32, count 2 2006.231.07:57:01.98#ibcon#about to read 3, iclass 32, count 2 2006.231.07:57:02.00#ibcon#read 3, iclass 32, count 2 2006.231.07:57:02.00#ibcon#about to read 4, iclass 32, count 2 2006.231.07:57:02.00#ibcon#read 4, iclass 32, count 2 2006.231.07:57:02.00#ibcon#about to read 5, iclass 32, count 2 2006.231.07:57:02.00#ibcon#read 5, iclass 32, count 2 2006.231.07:57:02.00#ibcon#about to read 6, iclass 32, count 2 2006.231.07:57:02.00#ibcon#read 6, iclass 32, count 2 2006.231.07:57:02.00#ibcon#end of sib2, iclass 32, count 2 2006.231.07:57:02.00#ibcon#*mode == 0, iclass 32, count 2 2006.231.07:57:02.00#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.07:57:02.00#ibcon#[27=AT05-03\r\n] 2006.231.07:57:02.00#ibcon#*before write, iclass 32, count 2 2006.231.07:57:02.00#ibcon#enter sib2, iclass 32, count 2 2006.231.07:57:02.00#ibcon#flushed, iclass 32, count 2 2006.231.07:57:02.00#ibcon#about to write, iclass 32, count 2 2006.231.07:57:02.00#ibcon#wrote, iclass 32, count 2 2006.231.07:57:02.00#ibcon#about to read 3, iclass 32, count 2 2006.231.07:57:02.04#ibcon#read 3, iclass 32, count 2 2006.231.07:57:02.04#ibcon#about to read 4, iclass 32, count 2 2006.231.07:57:02.04#ibcon#read 4, iclass 32, count 2 2006.231.07:57:02.04#ibcon#about to read 5, iclass 32, count 2 2006.231.07:57:02.04#ibcon#read 5, iclass 32, count 2 2006.231.07:57:02.04#ibcon#about to read 6, iclass 32, count 2 2006.231.07:57:02.04#ibcon#read 6, iclass 32, count 2 2006.231.07:57:02.04#ibcon#end of sib2, iclass 32, count 2 2006.231.07:57:02.04#ibcon#*after write, iclass 32, count 2 2006.231.07:57:02.04#ibcon#*before return 0, iclass 32, count 2 2006.231.07:57:02.04#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:57:02.04#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.07:57:02.04#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.07:57:02.04#ibcon#ireg 7 cls_cnt 0 2006.231.07:57:02.04#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:57:02.16#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:57:02.16#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:57:02.16#ibcon#enter wrdev, iclass 32, count 0 2006.231.07:57:02.16#ibcon#first serial, iclass 32, count 0 2006.231.07:57:02.16#ibcon#enter sib2, iclass 32, count 0 2006.231.07:57:02.16#ibcon#flushed, iclass 32, count 0 2006.231.07:57:02.16#ibcon#about to write, iclass 32, count 0 2006.231.07:57:02.16#ibcon#wrote, iclass 32, count 0 2006.231.07:57:02.16#ibcon#about to read 3, iclass 32, count 0 2006.231.07:57:02.18#ibcon#read 3, iclass 32, count 0 2006.231.07:57:02.18#ibcon#about to read 4, iclass 32, count 0 2006.231.07:57:02.18#ibcon#read 4, iclass 32, count 0 2006.231.07:57:02.18#ibcon#about to read 5, iclass 32, count 0 2006.231.07:57:02.18#ibcon#read 5, iclass 32, count 0 2006.231.07:57:02.18#ibcon#about to read 6, iclass 32, count 0 2006.231.07:57:02.18#ibcon#read 6, iclass 32, count 0 2006.231.07:57:02.18#ibcon#end of sib2, iclass 32, count 0 2006.231.07:57:02.18#ibcon#*mode == 0, iclass 32, count 0 2006.231.07:57:02.18#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.07:57:02.18#ibcon#[27=USB\r\n] 2006.231.07:57:02.18#ibcon#*before write, iclass 32, count 0 2006.231.07:57:02.18#ibcon#enter sib2, iclass 32, count 0 2006.231.07:57:02.18#ibcon#flushed, iclass 32, count 0 2006.231.07:57:02.18#ibcon#about to write, iclass 32, count 0 2006.231.07:57:02.18#ibcon#wrote, iclass 32, count 0 2006.231.07:57:02.18#ibcon#about to read 3, iclass 32, count 0 2006.231.07:57:02.21#ibcon#read 3, iclass 32, count 0 2006.231.07:57:02.21#ibcon#about to read 4, iclass 32, count 0 2006.231.07:57:02.21#ibcon#read 4, iclass 32, count 0 2006.231.07:57:02.21#ibcon#about to read 5, iclass 32, count 0 2006.231.07:57:02.21#ibcon#read 5, iclass 32, count 0 2006.231.07:57:02.21#ibcon#about to read 6, iclass 32, count 0 2006.231.07:57:02.21#ibcon#read 6, iclass 32, count 0 2006.231.07:57:02.21#ibcon#end of sib2, iclass 32, count 0 2006.231.07:57:02.21#ibcon#*after write, iclass 32, count 0 2006.231.07:57:02.21#ibcon#*before return 0, iclass 32, count 0 2006.231.07:57:02.21#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:57:02.21#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.07:57:02.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.07:57:02.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.07:57:02.21$vc4f8/vblo=6,752.99 2006.231.07:57:02.21#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.07:57:02.21#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.07:57:02.21#ibcon#ireg 17 cls_cnt 0 2006.231.07:57:02.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:57:02.21#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:57:02.21#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:57:02.21#ibcon#enter wrdev, iclass 34, count 0 2006.231.07:57:02.21#ibcon#first serial, iclass 34, count 0 2006.231.07:57:02.21#ibcon#enter sib2, iclass 34, count 0 2006.231.07:57:02.21#ibcon#flushed, iclass 34, count 0 2006.231.07:57:02.21#ibcon#about to write, iclass 34, count 0 2006.231.07:57:02.21#ibcon#wrote, iclass 34, count 0 2006.231.07:57:02.21#ibcon#about to read 3, iclass 34, count 0 2006.231.07:57:02.23#ibcon#read 3, iclass 34, count 0 2006.231.07:57:02.23#ibcon#about to read 4, iclass 34, count 0 2006.231.07:57:02.23#ibcon#read 4, iclass 34, count 0 2006.231.07:57:02.23#ibcon#about to read 5, iclass 34, count 0 2006.231.07:57:02.23#ibcon#read 5, iclass 34, count 0 2006.231.07:57:02.23#ibcon#about to read 6, iclass 34, count 0 2006.231.07:57:02.23#ibcon#read 6, iclass 34, count 0 2006.231.07:57:02.23#ibcon#end of sib2, iclass 34, count 0 2006.231.07:57:02.23#ibcon#*mode == 0, iclass 34, count 0 2006.231.07:57:02.23#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.07:57:02.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.07:57:02.23#ibcon#*before write, iclass 34, count 0 2006.231.07:57:02.23#ibcon#enter sib2, iclass 34, count 0 2006.231.07:57:02.23#ibcon#flushed, iclass 34, count 0 2006.231.07:57:02.23#ibcon#about to write, iclass 34, count 0 2006.231.07:57:02.23#ibcon#wrote, iclass 34, count 0 2006.231.07:57:02.23#ibcon#about to read 3, iclass 34, count 0 2006.231.07:57:02.27#ibcon#read 3, iclass 34, count 0 2006.231.07:57:02.27#ibcon#about to read 4, iclass 34, count 0 2006.231.07:57:02.27#ibcon#read 4, iclass 34, count 0 2006.231.07:57:02.27#ibcon#about to read 5, iclass 34, count 0 2006.231.07:57:02.27#ibcon#read 5, iclass 34, count 0 2006.231.07:57:02.27#ibcon#about to read 6, iclass 34, count 0 2006.231.07:57:02.27#ibcon#read 6, iclass 34, count 0 2006.231.07:57:02.27#ibcon#end of sib2, iclass 34, count 0 2006.231.07:57:02.27#ibcon#*after write, iclass 34, count 0 2006.231.07:57:02.27#ibcon#*before return 0, iclass 34, count 0 2006.231.07:57:02.27#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:57:02.27#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.07:57:02.27#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.07:57:02.27#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.07:57:02.27$vc4f8/vb=6,4 2006.231.07:57:02.27#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.07:57:02.27#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.07:57:02.27#ibcon#ireg 11 cls_cnt 2 2006.231.07:57:02.27#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:57:02.33#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:57:02.33#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:57:02.33#ibcon#enter wrdev, iclass 36, count 2 2006.231.07:57:02.33#ibcon#first serial, iclass 36, count 2 2006.231.07:57:02.33#ibcon#enter sib2, iclass 36, count 2 2006.231.07:57:02.33#ibcon#flushed, iclass 36, count 2 2006.231.07:57:02.33#ibcon#about to write, iclass 36, count 2 2006.231.07:57:02.33#ibcon#wrote, iclass 36, count 2 2006.231.07:57:02.33#ibcon#about to read 3, iclass 36, count 2 2006.231.07:57:02.35#ibcon#read 3, iclass 36, count 2 2006.231.07:57:02.35#ibcon#about to read 4, iclass 36, count 2 2006.231.07:57:02.35#ibcon#read 4, iclass 36, count 2 2006.231.07:57:02.35#ibcon#about to read 5, iclass 36, count 2 2006.231.07:57:02.35#ibcon#read 5, iclass 36, count 2 2006.231.07:57:02.35#ibcon#about to read 6, iclass 36, count 2 2006.231.07:57:02.35#ibcon#read 6, iclass 36, count 2 2006.231.07:57:02.35#ibcon#end of sib2, iclass 36, count 2 2006.231.07:57:02.35#ibcon#*mode == 0, iclass 36, count 2 2006.231.07:57:02.35#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.07:57:02.35#ibcon#[27=AT06-04\r\n] 2006.231.07:57:02.35#ibcon#*before write, iclass 36, count 2 2006.231.07:57:02.35#ibcon#enter sib2, iclass 36, count 2 2006.231.07:57:02.35#ibcon#flushed, iclass 36, count 2 2006.231.07:57:02.35#ibcon#about to write, iclass 36, count 2 2006.231.07:57:02.35#ibcon#wrote, iclass 36, count 2 2006.231.07:57:02.35#ibcon#about to read 3, iclass 36, count 2 2006.231.07:57:02.38#ibcon#read 3, iclass 36, count 2 2006.231.07:57:02.38#ibcon#about to read 4, iclass 36, count 2 2006.231.07:57:02.38#ibcon#read 4, iclass 36, count 2 2006.231.07:57:02.38#ibcon#about to read 5, iclass 36, count 2 2006.231.07:57:02.38#ibcon#read 5, iclass 36, count 2 2006.231.07:57:02.38#ibcon#about to read 6, iclass 36, count 2 2006.231.07:57:02.38#ibcon#read 6, iclass 36, count 2 2006.231.07:57:02.38#ibcon#end of sib2, iclass 36, count 2 2006.231.07:57:02.38#ibcon#*after write, iclass 36, count 2 2006.231.07:57:02.38#ibcon#*before return 0, iclass 36, count 2 2006.231.07:57:02.38#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:57:02.38#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.07:57:02.38#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.07:57:02.38#ibcon#ireg 7 cls_cnt 0 2006.231.07:57:02.38#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:57:02.50#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:57:02.50#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:57:02.50#ibcon#enter wrdev, iclass 36, count 0 2006.231.07:57:02.50#ibcon#first serial, iclass 36, count 0 2006.231.07:57:02.50#ibcon#enter sib2, iclass 36, count 0 2006.231.07:57:02.50#ibcon#flushed, iclass 36, count 0 2006.231.07:57:02.50#ibcon#about to write, iclass 36, count 0 2006.231.07:57:02.50#ibcon#wrote, iclass 36, count 0 2006.231.07:57:02.50#ibcon#about to read 3, iclass 36, count 0 2006.231.07:57:02.52#ibcon#read 3, iclass 36, count 0 2006.231.07:57:02.52#ibcon#about to read 4, iclass 36, count 0 2006.231.07:57:02.52#ibcon#read 4, iclass 36, count 0 2006.231.07:57:02.52#ibcon#about to read 5, iclass 36, count 0 2006.231.07:57:02.52#ibcon#read 5, iclass 36, count 0 2006.231.07:57:02.52#ibcon#about to read 6, iclass 36, count 0 2006.231.07:57:02.52#ibcon#read 6, iclass 36, count 0 2006.231.07:57:02.52#ibcon#end of sib2, iclass 36, count 0 2006.231.07:57:02.52#ibcon#*mode == 0, iclass 36, count 0 2006.231.07:57:02.52#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.07:57:02.52#ibcon#[27=USB\r\n] 2006.231.07:57:02.52#ibcon#*before write, iclass 36, count 0 2006.231.07:57:02.52#ibcon#enter sib2, iclass 36, count 0 2006.231.07:57:02.52#ibcon#flushed, iclass 36, count 0 2006.231.07:57:02.52#ibcon#about to write, iclass 36, count 0 2006.231.07:57:02.52#ibcon#wrote, iclass 36, count 0 2006.231.07:57:02.52#ibcon#about to read 3, iclass 36, count 0 2006.231.07:57:02.55#ibcon#read 3, iclass 36, count 0 2006.231.07:57:02.55#ibcon#about to read 4, iclass 36, count 0 2006.231.07:57:02.55#ibcon#read 4, iclass 36, count 0 2006.231.07:57:02.55#ibcon#about to read 5, iclass 36, count 0 2006.231.07:57:02.55#ibcon#read 5, iclass 36, count 0 2006.231.07:57:02.55#ibcon#about to read 6, iclass 36, count 0 2006.231.07:57:02.55#ibcon#read 6, iclass 36, count 0 2006.231.07:57:02.55#ibcon#end of sib2, iclass 36, count 0 2006.231.07:57:02.55#ibcon#*after write, iclass 36, count 0 2006.231.07:57:02.55#ibcon#*before return 0, iclass 36, count 0 2006.231.07:57:02.55#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:57:02.55#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.07:57:02.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.07:57:02.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.07:57:02.55$vc4f8/vabw=wide 2006.231.07:57:02.55#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.07:57:02.55#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.07:57:02.55#ibcon#ireg 8 cls_cnt 0 2006.231.07:57:02.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:57:02.55#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:57:02.55#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:57:02.55#ibcon#enter wrdev, iclass 38, count 0 2006.231.07:57:02.55#ibcon#first serial, iclass 38, count 0 2006.231.07:57:02.55#ibcon#enter sib2, iclass 38, count 0 2006.231.07:57:02.55#ibcon#flushed, iclass 38, count 0 2006.231.07:57:02.55#ibcon#about to write, iclass 38, count 0 2006.231.07:57:02.55#ibcon#wrote, iclass 38, count 0 2006.231.07:57:02.55#ibcon#about to read 3, iclass 38, count 0 2006.231.07:57:02.57#ibcon#read 3, iclass 38, count 0 2006.231.07:57:02.57#ibcon#about to read 4, iclass 38, count 0 2006.231.07:57:02.57#ibcon#read 4, iclass 38, count 0 2006.231.07:57:02.57#ibcon#about to read 5, iclass 38, count 0 2006.231.07:57:02.57#ibcon#read 5, iclass 38, count 0 2006.231.07:57:02.57#ibcon#about to read 6, iclass 38, count 0 2006.231.07:57:02.57#ibcon#read 6, iclass 38, count 0 2006.231.07:57:02.57#ibcon#end of sib2, iclass 38, count 0 2006.231.07:57:02.57#ibcon#*mode == 0, iclass 38, count 0 2006.231.07:57:02.57#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.07:57:02.57#ibcon#[25=BW32\r\n] 2006.231.07:57:02.57#ibcon#*before write, iclass 38, count 0 2006.231.07:57:02.57#ibcon#enter sib2, iclass 38, count 0 2006.231.07:57:02.57#ibcon#flushed, iclass 38, count 0 2006.231.07:57:02.57#ibcon#about to write, iclass 38, count 0 2006.231.07:57:02.57#ibcon#wrote, iclass 38, count 0 2006.231.07:57:02.57#ibcon#about to read 3, iclass 38, count 0 2006.231.07:57:02.60#ibcon#read 3, iclass 38, count 0 2006.231.07:57:02.60#ibcon#about to read 4, iclass 38, count 0 2006.231.07:57:02.60#ibcon#read 4, iclass 38, count 0 2006.231.07:57:02.60#ibcon#about to read 5, iclass 38, count 0 2006.231.07:57:02.60#ibcon#read 5, iclass 38, count 0 2006.231.07:57:02.60#ibcon#about to read 6, iclass 38, count 0 2006.231.07:57:02.60#ibcon#read 6, iclass 38, count 0 2006.231.07:57:02.60#ibcon#end of sib2, iclass 38, count 0 2006.231.07:57:02.60#ibcon#*after write, iclass 38, count 0 2006.231.07:57:02.60#ibcon#*before return 0, iclass 38, count 0 2006.231.07:57:02.60#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:57:02.60#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.07:57:02.60#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.07:57:02.60#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.07:57:02.60$vc4f8/vbbw=wide 2006.231.07:57:02.60#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.07:57:02.60#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.07:57:02.60#ibcon#ireg 8 cls_cnt 0 2006.231.07:57:02.60#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:57:02.67#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:57:02.67#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:57:02.67#ibcon#enter wrdev, iclass 40, count 0 2006.231.07:57:02.67#ibcon#first serial, iclass 40, count 0 2006.231.07:57:02.67#ibcon#enter sib2, iclass 40, count 0 2006.231.07:57:02.67#ibcon#flushed, iclass 40, count 0 2006.231.07:57:02.67#ibcon#about to write, iclass 40, count 0 2006.231.07:57:02.67#ibcon#wrote, iclass 40, count 0 2006.231.07:57:02.67#ibcon#about to read 3, iclass 40, count 0 2006.231.07:57:02.69#ibcon#read 3, iclass 40, count 0 2006.231.07:57:02.69#ibcon#about to read 4, iclass 40, count 0 2006.231.07:57:02.69#ibcon#read 4, iclass 40, count 0 2006.231.07:57:02.69#ibcon#about to read 5, iclass 40, count 0 2006.231.07:57:02.69#ibcon#read 5, iclass 40, count 0 2006.231.07:57:02.69#ibcon#about to read 6, iclass 40, count 0 2006.231.07:57:02.69#ibcon#read 6, iclass 40, count 0 2006.231.07:57:02.69#ibcon#end of sib2, iclass 40, count 0 2006.231.07:57:02.69#ibcon#*mode == 0, iclass 40, count 0 2006.231.07:57:02.69#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.07:57:02.69#ibcon#[27=BW32\r\n] 2006.231.07:57:02.69#ibcon#*before write, iclass 40, count 0 2006.231.07:57:02.69#ibcon#enter sib2, iclass 40, count 0 2006.231.07:57:02.69#ibcon#flushed, iclass 40, count 0 2006.231.07:57:02.69#ibcon#about to write, iclass 40, count 0 2006.231.07:57:02.69#ibcon#wrote, iclass 40, count 0 2006.231.07:57:02.69#ibcon#about to read 3, iclass 40, count 0 2006.231.07:57:02.72#ibcon#read 3, iclass 40, count 0 2006.231.07:57:02.72#ibcon#about to read 4, iclass 40, count 0 2006.231.07:57:02.72#ibcon#read 4, iclass 40, count 0 2006.231.07:57:02.72#ibcon#about to read 5, iclass 40, count 0 2006.231.07:57:02.72#ibcon#read 5, iclass 40, count 0 2006.231.07:57:02.72#ibcon#about to read 6, iclass 40, count 0 2006.231.07:57:02.72#ibcon#read 6, iclass 40, count 0 2006.231.07:57:02.72#ibcon#end of sib2, iclass 40, count 0 2006.231.07:57:02.72#ibcon#*after write, iclass 40, count 0 2006.231.07:57:02.72#ibcon#*before return 0, iclass 40, count 0 2006.231.07:57:02.72#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:57:02.72#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.07:57:02.72#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.07:57:02.72#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.07:57:02.72$4f8m12a/ifd4f 2006.231.07:57:02.72$ifd4f/lo= 2006.231.07:57:02.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.07:57:02.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.07:57:02.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.07:57:02.72$ifd4f/patch= 2006.231.07:57:02.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.07:57:02.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.07:57:02.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.07:57:02.72$4f8m12a/"form=m,16.000,1:2 2006.231.07:57:02.72$4f8m12a/"tpicd 2006.231.07:57:02.72$4f8m12a/echo=off 2006.231.07:57:02.72$4f8m12a/xlog=off 2006.231.07:57:02.72:!2006.231.07:59:10 2006.231.07:57:38.14#trakl#Source acquired 2006.231.07:57:39.14#flagr#flagr/antenna,acquired 2006.231.07:59:10.00:preob 2006.231.07:59:10.14/onsource/TRACKING 2006.231.07:59:10.14:!2006.231.07:59:20 2006.231.07:59:20.00:data_valid=on 2006.231.07:59:20.00:midob 2006.231.07:59:21.14/onsource/TRACKING 2006.231.07:59:21.14/wx/30.54,1004.4,85 2006.231.07:59:21.26/cable/+6.3711E-03 2006.231.07:59:22.35/va/01,08,usb,yes,30,32 2006.231.07:59:22.35/va/02,07,usb,yes,30,32 2006.231.07:59:22.35/va/03,08,usb,yes,23,23 2006.231.07:59:22.35/va/04,07,usb,yes,32,34 2006.231.07:59:22.35/va/05,07,usb,yes,35,37 2006.231.07:59:22.35/va/06,06,usb,yes,34,34 2006.231.07:59:22.35/va/07,06,usb,yes,35,35 2006.231.07:59:22.35/va/08,06,usb,yes,37,37 2006.231.07:59:22.58/valo/01,532.99,yes,locked 2006.231.07:59:22.58/valo/02,572.99,yes,locked 2006.231.07:59:22.58/valo/03,672.99,yes,locked 2006.231.07:59:22.58/valo/04,832.99,yes,locked 2006.231.07:59:22.58/valo/05,652.99,yes,locked 2006.231.07:59:22.58/valo/06,772.99,yes,locked 2006.231.07:59:22.58/valo/07,832.99,yes,locked 2006.231.07:59:22.58/valo/08,852.99,yes,locked 2006.231.07:59:23.67/vb/01,04,usb,yes,31,30 2006.231.07:59:23.67/vb/02,04,usb,yes,33,35 2006.231.07:59:23.67/vb/03,04,usb,yes,30,33 2006.231.07:59:23.67/vb/04,04,usb,yes,30,31 2006.231.07:59:23.67/vb/05,03,usb,yes,36,41 2006.231.07:59:23.67/vb/06,04,usb,yes,30,33 2006.231.07:59:23.67/vb/07,04,usb,yes,32,32 2006.231.07:59:23.67/vb/08,04,usb,yes,29,33 2006.231.07:59:23.91/vblo/01,632.99,yes,locked 2006.231.07:59:23.91/vblo/02,640.99,yes,locked 2006.231.07:59:23.91/vblo/03,656.99,yes,locked 2006.231.07:59:23.91/vblo/04,712.99,yes,locked 2006.231.07:59:23.91/vblo/05,744.99,yes,locked 2006.231.07:59:23.91/vblo/06,752.99,yes,locked 2006.231.07:59:23.91/vblo/07,734.99,yes,locked 2006.231.07:59:23.91/vblo/08,744.99,yes,locked 2006.231.07:59:24.06/vabw/8 2006.231.07:59:24.21/vbbw/8 2006.231.07:59:24.30/xfe/off,on,12.5 2006.231.07:59:24.69/ifatt/23,28,28,28 2006.231.07:59:25.08/fmout-gps/S +4.47E-07 2006.231.07:59:25.12:!2006.231.08:00:20 2006.231.08:00:20.00:data_valid=off 2006.231.08:00:20.00:postob 2006.231.08:00:20.07/cable/+6.3697E-03 2006.231.08:00:20.07/wx/30.53,1004.4,86 2006.231.08:00:21.08/fmout-gps/S +4.48E-07 2006.231.08:00:21.08:scan_name=231-0801,k06231,60 2006.231.08:00:21.08:source=0059+581,010245.76,582411.1,2000.0,cw 2006.231.08:00:21.13#flagr#flagr/antenna,new-source 2006.231.08:00:22.13:checkk5 2006.231.08:00:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:00:22.87/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:00:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:00:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:00:24.00/chk_obsdata//k5ts1/T2310759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:00:24.36/chk_obsdata//k5ts2/T2310759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:00:24.72/chk_obsdata//k5ts3/T2310759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:00:25.09/chk_obsdata//k5ts4/T2310759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:00:25.78/k5log//k5ts1_log_newline 2006.231.08:00:26.47/k5log//k5ts2_log_newline 2006.231.08:00:27.16/k5log//k5ts3_log_newline 2006.231.08:00:27.84/k5log//k5ts4_log_newline 2006.231.08:00:27.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:00:27.86:4f8m12a=2 2006.231.08:00:27.86$4f8m12a/echo=on 2006.231.08:00:27.86$4f8m12a/pcalon 2006.231.08:00:27.86$pcalon/"no phase cal control is implemented here 2006.231.08:00:27.86$4f8m12a/"tpicd=stop 2006.231.08:00:27.86$4f8m12a/vc4f8 2006.231.08:00:27.86$vc4f8/valo=1,532.99 2006.231.08:00:27.87#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.08:00:27.87#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.08:00:27.87#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:27.87#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:00:27.87#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:00:27.87#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:00:27.87#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:00:27.87#ibcon#first serial, iclass 15, count 0 2006.231.08:00:27.87#ibcon#enter sib2, iclass 15, count 0 2006.231.08:00:27.87#ibcon#flushed, iclass 15, count 0 2006.231.08:00:27.87#ibcon#about to write, iclass 15, count 0 2006.231.08:00:27.87#ibcon#wrote, iclass 15, count 0 2006.231.08:00:27.87#ibcon#about to read 3, iclass 15, count 0 2006.231.08:00:27.91#ibcon#read 3, iclass 15, count 0 2006.231.08:00:27.91#ibcon#about to read 4, iclass 15, count 0 2006.231.08:00:27.91#ibcon#read 4, iclass 15, count 0 2006.231.08:00:27.91#ibcon#about to read 5, iclass 15, count 0 2006.231.08:00:27.91#ibcon#read 5, iclass 15, count 0 2006.231.08:00:27.91#ibcon#about to read 6, iclass 15, count 0 2006.231.08:00:27.91#ibcon#read 6, iclass 15, count 0 2006.231.08:00:27.91#ibcon#end of sib2, iclass 15, count 0 2006.231.08:00:27.91#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:00:27.91#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:00:27.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:00:27.91#ibcon#*before write, iclass 15, count 0 2006.231.08:00:27.91#ibcon#enter sib2, iclass 15, count 0 2006.231.08:00:27.91#ibcon#flushed, iclass 15, count 0 2006.231.08:00:27.91#ibcon#about to write, iclass 15, count 0 2006.231.08:00:27.91#ibcon#wrote, iclass 15, count 0 2006.231.08:00:27.91#ibcon#about to read 3, iclass 15, count 0 2006.231.08:00:27.96#ibcon#read 3, iclass 15, count 0 2006.231.08:00:27.96#ibcon#about to read 4, iclass 15, count 0 2006.231.08:00:27.96#ibcon#read 4, iclass 15, count 0 2006.231.08:00:27.96#ibcon#about to read 5, iclass 15, count 0 2006.231.08:00:27.96#ibcon#read 5, iclass 15, count 0 2006.231.08:00:27.96#ibcon#about to read 6, iclass 15, count 0 2006.231.08:00:27.96#ibcon#read 6, iclass 15, count 0 2006.231.08:00:27.96#ibcon#end of sib2, iclass 15, count 0 2006.231.08:00:27.96#ibcon#*after write, iclass 15, count 0 2006.231.08:00:27.96#ibcon#*before return 0, iclass 15, count 0 2006.231.08:00:27.96#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:00:27.96#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:00:27.96#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:00:27.96#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:00:27.96$vc4f8/va=1,8 2006.231.08:00:27.96#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.08:00:27.96#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.08:00:27.96#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:27.96#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:00:27.96#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:00:27.96#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:00:27.96#ibcon#enter wrdev, iclass 17, count 2 2006.231.08:00:27.96#ibcon#first serial, iclass 17, count 2 2006.231.08:00:27.96#ibcon#enter sib2, iclass 17, count 2 2006.231.08:00:27.96#ibcon#flushed, iclass 17, count 2 2006.231.08:00:27.96#ibcon#about to write, iclass 17, count 2 2006.231.08:00:27.96#ibcon#wrote, iclass 17, count 2 2006.231.08:00:27.96#ibcon#about to read 3, iclass 17, count 2 2006.231.08:00:27.98#ibcon#read 3, iclass 17, count 2 2006.231.08:00:27.98#ibcon#about to read 4, iclass 17, count 2 2006.231.08:00:27.98#ibcon#read 4, iclass 17, count 2 2006.231.08:00:27.98#ibcon#about to read 5, iclass 17, count 2 2006.231.08:00:27.98#ibcon#read 5, iclass 17, count 2 2006.231.08:00:27.98#ibcon#about to read 6, iclass 17, count 2 2006.231.08:00:27.98#ibcon#read 6, iclass 17, count 2 2006.231.08:00:27.98#ibcon#end of sib2, iclass 17, count 2 2006.231.08:00:27.98#ibcon#*mode == 0, iclass 17, count 2 2006.231.08:00:27.98#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.08:00:27.98#ibcon#[25=AT01-08\r\n] 2006.231.08:00:27.98#ibcon#*before write, iclass 17, count 2 2006.231.08:00:27.98#ibcon#enter sib2, iclass 17, count 2 2006.231.08:00:27.98#ibcon#flushed, iclass 17, count 2 2006.231.08:00:27.98#ibcon#about to write, iclass 17, count 2 2006.231.08:00:27.98#ibcon#wrote, iclass 17, count 2 2006.231.08:00:27.98#ibcon#about to read 3, iclass 17, count 2 2006.231.08:00:28.01#ibcon#read 3, iclass 17, count 2 2006.231.08:00:28.01#ibcon#about to read 4, iclass 17, count 2 2006.231.08:00:28.01#ibcon#read 4, iclass 17, count 2 2006.231.08:00:28.01#ibcon#about to read 5, iclass 17, count 2 2006.231.08:00:28.01#ibcon#read 5, iclass 17, count 2 2006.231.08:00:28.01#ibcon#about to read 6, iclass 17, count 2 2006.231.08:00:28.01#ibcon#read 6, iclass 17, count 2 2006.231.08:00:28.01#ibcon#end of sib2, iclass 17, count 2 2006.231.08:00:28.01#ibcon#*after write, iclass 17, count 2 2006.231.08:00:28.01#ibcon#*before return 0, iclass 17, count 2 2006.231.08:00:28.01#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:00:28.01#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:00:28.01#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.08:00:28.01#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:28.01#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:00:28.13#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:00:28.13#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:00:28.13#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:00:28.13#ibcon#first serial, iclass 17, count 0 2006.231.08:00:28.13#ibcon#enter sib2, iclass 17, count 0 2006.231.08:00:28.13#ibcon#flushed, iclass 17, count 0 2006.231.08:00:28.13#ibcon#about to write, iclass 17, count 0 2006.231.08:00:28.13#ibcon#wrote, iclass 17, count 0 2006.231.08:00:28.13#ibcon#about to read 3, iclass 17, count 0 2006.231.08:00:28.15#ibcon#read 3, iclass 17, count 0 2006.231.08:00:28.15#ibcon#about to read 4, iclass 17, count 0 2006.231.08:00:28.15#ibcon#read 4, iclass 17, count 0 2006.231.08:00:28.15#ibcon#about to read 5, iclass 17, count 0 2006.231.08:00:28.15#ibcon#read 5, iclass 17, count 0 2006.231.08:00:28.15#ibcon#about to read 6, iclass 17, count 0 2006.231.08:00:28.15#ibcon#read 6, iclass 17, count 0 2006.231.08:00:28.15#ibcon#end of sib2, iclass 17, count 0 2006.231.08:00:28.15#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:00:28.15#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:00:28.15#ibcon#[25=USB\r\n] 2006.231.08:00:28.15#ibcon#*before write, iclass 17, count 0 2006.231.08:00:28.15#ibcon#enter sib2, iclass 17, count 0 2006.231.08:00:28.15#ibcon#flushed, iclass 17, count 0 2006.231.08:00:28.15#ibcon#about to write, iclass 17, count 0 2006.231.08:00:28.15#ibcon#wrote, iclass 17, count 0 2006.231.08:00:28.15#ibcon#about to read 3, iclass 17, count 0 2006.231.08:00:28.18#ibcon#read 3, iclass 17, count 0 2006.231.08:00:28.18#ibcon#about to read 4, iclass 17, count 0 2006.231.08:00:28.18#ibcon#read 4, iclass 17, count 0 2006.231.08:00:28.18#ibcon#about to read 5, iclass 17, count 0 2006.231.08:00:28.18#ibcon#read 5, iclass 17, count 0 2006.231.08:00:28.18#ibcon#about to read 6, iclass 17, count 0 2006.231.08:00:28.18#ibcon#read 6, iclass 17, count 0 2006.231.08:00:28.18#ibcon#end of sib2, iclass 17, count 0 2006.231.08:00:28.18#ibcon#*after write, iclass 17, count 0 2006.231.08:00:28.18#ibcon#*before return 0, iclass 17, count 0 2006.231.08:00:28.18#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:00:28.18#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:00:28.18#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:00:28.18#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:00:28.18$vc4f8/valo=2,572.99 2006.231.08:00:28.18#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.08:00:28.18#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.08:00:28.18#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:28.18#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:00:28.18#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:00:28.18#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:00:28.18#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:00:28.18#ibcon#first serial, iclass 19, count 0 2006.231.08:00:28.18#ibcon#enter sib2, iclass 19, count 0 2006.231.08:00:28.18#ibcon#flushed, iclass 19, count 0 2006.231.08:00:28.18#ibcon#about to write, iclass 19, count 0 2006.231.08:00:28.18#ibcon#wrote, iclass 19, count 0 2006.231.08:00:28.18#ibcon#about to read 3, iclass 19, count 0 2006.231.08:00:28.20#ibcon#read 3, iclass 19, count 0 2006.231.08:00:28.20#ibcon#about to read 4, iclass 19, count 0 2006.231.08:00:28.20#ibcon#read 4, iclass 19, count 0 2006.231.08:00:28.20#ibcon#about to read 5, iclass 19, count 0 2006.231.08:00:28.20#ibcon#read 5, iclass 19, count 0 2006.231.08:00:28.20#ibcon#about to read 6, iclass 19, count 0 2006.231.08:00:28.20#ibcon#read 6, iclass 19, count 0 2006.231.08:00:28.20#ibcon#end of sib2, iclass 19, count 0 2006.231.08:00:28.20#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:00:28.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:00:28.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:00:28.20#ibcon#*before write, iclass 19, count 0 2006.231.08:00:28.20#ibcon#enter sib2, iclass 19, count 0 2006.231.08:00:28.20#ibcon#flushed, iclass 19, count 0 2006.231.08:00:28.20#ibcon#about to write, iclass 19, count 0 2006.231.08:00:28.20#ibcon#wrote, iclass 19, count 0 2006.231.08:00:28.20#ibcon#about to read 3, iclass 19, count 0 2006.231.08:00:28.24#ibcon#read 3, iclass 19, count 0 2006.231.08:00:28.24#ibcon#about to read 4, iclass 19, count 0 2006.231.08:00:28.24#ibcon#read 4, iclass 19, count 0 2006.231.08:00:28.24#ibcon#about to read 5, iclass 19, count 0 2006.231.08:00:28.24#ibcon#read 5, iclass 19, count 0 2006.231.08:00:28.24#ibcon#about to read 6, iclass 19, count 0 2006.231.08:00:28.24#ibcon#read 6, iclass 19, count 0 2006.231.08:00:28.24#ibcon#end of sib2, iclass 19, count 0 2006.231.08:00:28.24#ibcon#*after write, iclass 19, count 0 2006.231.08:00:28.24#ibcon#*before return 0, iclass 19, count 0 2006.231.08:00:28.24#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:00:28.24#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:00:28.24#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:00:28.24#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:00:28.24$vc4f8/va=2,7 2006.231.08:00:28.24#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.231.08:00:28.24#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.231.08:00:28.24#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:28.24#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:00:28.30#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:00:28.30#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:00:28.30#ibcon#enter wrdev, iclass 21, count 2 2006.231.08:00:28.30#ibcon#first serial, iclass 21, count 2 2006.231.08:00:28.30#ibcon#enter sib2, iclass 21, count 2 2006.231.08:00:28.30#ibcon#flushed, iclass 21, count 2 2006.231.08:00:28.30#ibcon#about to write, iclass 21, count 2 2006.231.08:00:28.30#ibcon#wrote, iclass 21, count 2 2006.231.08:00:28.30#ibcon#about to read 3, iclass 21, count 2 2006.231.08:00:28.32#ibcon#read 3, iclass 21, count 2 2006.231.08:00:28.32#ibcon#about to read 4, iclass 21, count 2 2006.231.08:00:28.32#ibcon#read 4, iclass 21, count 2 2006.231.08:00:28.32#ibcon#about to read 5, iclass 21, count 2 2006.231.08:00:28.32#ibcon#read 5, iclass 21, count 2 2006.231.08:00:28.32#ibcon#about to read 6, iclass 21, count 2 2006.231.08:00:28.32#ibcon#read 6, iclass 21, count 2 2006.231.08:00:28.32#ibcon#end of sib2, iclass 21, count 2 2006.231.08:00:28.32#ibcon#*mode == 0, iclass 21, count 2 2006.231.08:00:28.32#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.231.08:00:28.32#ibcon#[25=AT02-07\r\n] 2006.231.08:00:28.32#ibcon#*before write, iclass 21, count 2 2006.231.08:00:28.32#ibcon#enter sib2, iclass 21, count 2 2006.231.08:00:28.32#ibcon#flushed, iclass 21, count 2 2006.231.08:00:28.32#ibcon#about to write, iclass 21, count 2 2006.231.08:00:28.32#ibcon#wrote, iclass 21, count 2 2006.231.08:00:28.32#ibcon#about to read 3, iclass 21, count 2 2006.231.08:00:28.35#ibcon#read 3, iclass 21, count 2 2006.231.08:00:28.35#ibcon#about to read 4, iclass 21, count 2 2006.231.08:00:28.35#ibcon#read 4, iclass 21, count 2 2006.231.08:00:28.35#ibcon#about to read 5, iclass 21, count 2 2006.231.08:00:28.35#ibcon#read 5, iclass 21, count 2 2006.231.08:00:28.35#ibcon#about to read 6, iclass 21, count 2 2006.231.08:00:28.35#ibcon#read 6, iclass 21, count 2 2006.231.08:00:28.35#ibcon#end of sib2, iclass 21, count 2 2006.231.08:00:28.35#ibcon#*after write, iclass 21, count 2 2006.231.08:00:28.35#ibcon#*before return 0, iclass 21, count 2 2006.231.08:00:28.35#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:00:28.35#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:00:28.35#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.231.08:00:28.35#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:28.35#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:00:28.47#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:00:28.47#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:00:28.47#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:00:28.47#ibcon#first serial, iclass 21, count 0 2006.231.08:00:28.47#ibcon#enter sib2, iclass 21, count 0 2006.231.08:00:28.47#ibcon#flushed, iclass 21, count 0 2006.231.08:00:28.47#ibcon#about to write, iclass 21, count 0 2006.231.08:00:28.47#ibcon#wrote, iclass 21, count 0 2006.231.08:00:28.47#ibcon#about to read 3, iclass 21, count 0 2006.231.08:00:28.49#ibcon#read 3, iclass 21, count 0 2006.231.08:00:28.49#ibcon#about to read 4, iclass 21, count 0 2006.231.08:00:28.49#ibcon#read 4, iclass 21, count 0 2006.231.08:00:28.49#ibcon#about to read 5, iclass 21, count 0 2006.231.08:00:28.49#ibcon#read 5, iclass 21, count 0 2006.231.08:00:28.49#ibcon#about to read 6, iclass 21, count 0 2006.231.08:00:28.49#ibcon#read 6, iclass 21, count 0 2006.231.08:00:28.49#ibcon#end of sib2, iclass 21, count 0 2006.231.08:00:28.49#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:00:28.49#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:00:28.49#ibcon#[25=USB\r\n] 2006.231.08:00:28.49#ibcon#*before write, iclass 21, count 0 2006.231.08:00:28.49#ibcon#enter sib2, iclass 21, count 0 2006.231.08:00:28.49#ibcon#flushed, iclass 21, count 0 2006.231.08:00:28.49#ibcon#about to write, iclass 21, count 0 2006.231.08:00:28.49#ibcon#wrote, iclass 21, count 0 2006.231.08:00:28.49#ibcon#about to read 3, iclass 21, count 0 2006.231.08:00:28.52#ibcon#read 3, iclass 21, count 0 2006.231.08:00:28.52#ibcon#about to read 4, iclass 21, count 0 2006.231.08:00:28.52#ibcon#read 4, iclass 21, count 0 2006.231.08:00:28.52#ibcon#about to read 5, iclass 21, count 0 2006.231.08:00:28.52#ibcon#read 5, iclass 21, count 0 2006.231.08:00:28.52#ibcon#about to read 6, iclass 21, count 0 2006.231.08:00:28.52#ibcon#read 6, iclass 21, count 0 2006.231.08:00:28.52#ibcon#end of sib2, iclass 21, count 0 2006.231.08:00:28.52#ibcon#*after write, iclass 21, count 0 2006.231.08:00:28.52#ibcon#*before return 0, iclass 21, count 0 2006.231.08:00:28.52#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:00:28.52#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:00:28.52#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:00:28.52#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:00:28.52$vc4f8/valo=3,672.99 2006.231.08:00:28.52#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.231.08:00:28.52#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.231.08:00:28.52#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:28.52#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:00:28.52#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:00:28.52#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:00:28.52#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:00:28.52#ibcon#first serial, iclass 23, count 0 2006.231.08:00:28.52#ibcon#enter sib2, iclass 23, count 0 2006.231.08:00:28.52#ibcon#flushed, iclass 23, count 0 2006.231.08:00:28.52#ibcon#about to write, iclass 23, count 0 2006.231.08:00:28.52#ibcon#wrote, iclass 23, count 0 2006.231.08:00:28.52#ibcon#about to read 3, iclass 23, count 0 2006.231.08:00:28.54#ibcon#read 3, iclass 23, count 0 2006.231.08:00:28.54#ibcon#about to read 4, iclass 23, count 0 2006.231.08:00:28.54#ibcon#read 4, iclass 23, count 0 2006.231.08:00:28.54#ibcon#about to read 5, iclass 23, count 0 2006.231.08:00:28.54#ibcon#read 5, iclass 23, count 0 2006.231.08:00:28.54#ibcon#about to read 6, iclass 23, count 0 2006.231.08:00:28.54#ibcon#read 6, iclass 23, count 0 2006.231.08:00:28.54#ibcon#end of sib2, iclass 23, count 0 2006.231.08:00:28.54#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:00:28.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:00:28.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:00:28.54#ibcon#*before write, iclass 23, count 0 2006.231.08:00:28.54#ibcon#enter sib2, iclass 23, count 0 2006.231.08:00:28.54#ibcon#flushed, iclass 23, count 0 2006.231.08:00:28.54#ibcon#about to write, iclass 23, count 0 2006.231.08:00:28.54#ibcon#wrote, iclass 23, count 0 2006.231.08:00:28.54#ibcon#about to read 3, iclass 23, count 0 2006.231.08:00:28.58#ibcon#read 3, iclass 23, count 0 2006.231.08:00:28.58#ibcon#about to read 4, iclass 23, count 0 2006.231.08:00:28.58#ibcon#read 4, iclass 23, count 0 2006.231.08:00:28.58#ibcon#about to read 5, iclass 23, count 0 2006.231.08:00:28.58#ibcon#read 5, iclass 23, count 0 2006.231.08:00:28.58#ibcon#about to read 6, iclass 23, count 0 2006.231.08:00:28.58#ibcon#read 6, iclass 23, count 0 2006.231.08:00:28.58#ibcon#end of sib2, iclass 23, count 0 2006.231.08:00:28.58#ibcon#*after write, iclass 23, count 0 2006.231.08:00:28.58#ibcon#*before return 0, iclass 23, count 0 2006.231.08:00:28.58#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:00:28.58#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:00:28.58#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:00:28.58#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:00:28.58$vc4f8/va=3,8 2006.231.08:00:28.58#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.231.08:00:28.58#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.231.08:00:28.58#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:28.58#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:00:28.64#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:00:28.64#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:00:28.64#ibcon#enter wrdev, iclass 25, count 2 2006.231.08:00:28.64#ibcon#first serial, iclass 25, count 2 2006.231.08:00:28.64#ibcon#enter sib2, iclass 25, count 2 2006.231.08:00:28.64#ibcon#flushed, iclass 25, count 2 2006.231.08:00:28.64#ibcon#about to write, iclass 25, count 2 2006.231.08:00:28.64#ibcon#wrote, iclass 25, count 2 2006.231.08:00:28.64#ibcon#about to read 3, iclass 25, count 2 2006.231.08:00:28.66#ibcon#read 3, iclass 25, count 2 2006.231.08:00:28.66#ibcon#about to read 4, iclass 25, count 2 2006.231.08:00:28.66#ibcon#read 4, iclass 25, count 2 2006.231.08:00:28.66#ibcon#about to read 5, iclass 25, count 2 2006.231.08:00:28.66#ibcon#read 5, iclass 25, count 2 2006.231.08:00:28.66#ibcon#about to read 6, iclass 25, count 2 2006.231.08:00:28.66#ibcon#read 6, iclass 25, count 2 2006.231.08:00:28.66#ibcon#end of sib2, iclass 25, count 2 2006.231.08:00:28.66#ibcon#*mode == 0, iclass 25, count 2 2006.231.08:00:28.66#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.231.08:00:28.66#ibcon#[25=AT03-08\r\n] 2006.231.08:00:28.66#ibcon#*before write, iclass 25, count 2 2006.231.08:00:28.66#ibcon#enter sib2, iclass 25, count 2 2006.231.08:00:28.66#ibcon#flushed, iclass 25, count 2 2006.231.08:00:28.66#ibcon#about to write, iclass 25, count 2 2006.231.08:00:28.66#ibcon#wrote, iclass 25, count 2 2006.231.08:00:28.66#ibcon#about to read 3, iclass 25, count 2 2006.231.08:00:28.69#ibcon#read 3, iclass 25, count 2 2006.231.08:00:28.69#ibcon#about to read 4, iclass 25, count 2 2006.231.08:00:28.69#ibcon#read 4, iclass 25, count 2 2006.231.08:00:28.69#ibcon#about to read 5, iclass 25, count 2 2006.231.08:00:28.69#ibcon#read 5, iclass 25, count 2 2006.231.08:00:28.69#ibcon#about to read 6, iclass 25, count 2 2006.231.08:00:28.69#ibcon#read 6, iclass 25, count 2 2006.231.08:00:28.69#ibcon#end of sib2, iclass 25, count 2 2006.231.08:00:28.69#ibcon#*after write, iclass 25, count 2 2006.231.08:00:28.69#ibcon#*before return 0, iclass 25, count 2 2006.231.08:00:28.69#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:00:28.69#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:00:28.69#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.231.08:00:28.69#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:28.69#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:00:28.81#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:00:28.81#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:00:28.81#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:00:28.81#ibcon#first serial, iclass 25, count 0 2006.231.08:00:28.81#ibcon#enter sib2, iclass 25, count 0 2006.231.08:00:28.81#ibcon#flushed, iclass 25, count 0 2006.231.08:00:28.81#ibcon#about to write, iclass 25, count 0 2006.231.08:00:28.81#ibcon#wrote, iclass 25, count 0 2006.231.08:00:28.81#ibcon#about to read 3, iclass 25, count 0 2006.231.08:00:28.83#ibcon#read 3, iclass 25, count 0 2006.231.08:00:28.83#ibcon#about to read 4, iclass 25, count 0 2006.231.08:00:28.83#ibcon#read 4, iclass 25, count 0 2006.231.08:00:28.83#ibcon#about to read 5, iclass 25, count 0 2006.231.08:00:28.83#ibcon#read 5, iclass 25, count 0 2006.231.08:00:28.83#ibcon#about to read 6, iclass 25, count 0 2006.231.08:00:28.83#ibcon#read 6, iclass 25, count 0 2006.231.08:00:28.83#ibcon#end of sib2, iclass 25, count 0 2006.231.08:00:28.83#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:00:28.83#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:00:28.83#ibcon#[25=USB\r\n] 2006.231.08:00:28.83#ibcon#*before write, iclass 25, count 0 2006.231.08:00:28.83#ibcon#enter sib2, iclass 25, count 0 2006.231.08:00:28.83#ibcon#flushed, iclass 25, count 0 2006.231.08:00:28.83#ibcon#about to write, iclass 25, count 0 2006.231.08:00:28.83#ibcon#wrote, iclass 25, count 0 2006.231.08:00:28.83#ibcon#about to read 3, iclass 25, count 0 2006.231.08:00:28.86#ibcon#read 3, iclass 25, count 0 2006.231.08:00:28.86#ibcon#about to read 4, iclass 25, count 0 2006.231.08:00:28.86#ibcon#read 4, iclass 25, count 0 2006.231.08:00:28.86#ibcon#about to read 5, iclass 25, count 0 2006.231.08:00:28.86#ibcon#read 5, iclass 25, count 0 2006.231.08:00:28.86#ibcon#about to read 6, iclass 25, count 0 2006.231.08:00:28.86#ibcon#read 6, iclass 25, count 0 2006.231.08:00:28.86#ibcon#end of sib2, iclass 25, count 0 2006.231.08:00:28.86#ibcon#*after write, iclass 25, count 0 2006.231.08:00:28.86#ibcon#*before return 0, iclass 25, count 0 2006.231.08:00:28.86#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:00:28.86#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:00:28.86#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:00:28.86#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:00:28.86$vc4f8/valo=4,832.99 2006.231.08:00:28.86#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.231.08:00:28.86#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.231.08:00:28.86#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:28.86#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:00:28.86#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:00:28.86#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:00:28.86#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:00:28.86#ibcon#first serial, iclass 27, count 0 2006.231.08:00:28.86#ibcon#enter sib2, iclass 27, count 0 2006.231.08:00:28.86#ibcon#flushed, iclass 27, count 0 2006.231.08:00:28.86#ibcon#about to write, iclass 27, count 0 2006.231.08:00:28.86#ibcon#wrote, iclass 27, count 0 2006.231.08:00:28.86#ibcon#about to read 3, iclass 27, count 0 2006.231.08:00:28.88#ibcon#read 3, iclass 27, count 0 2006.231.08:00:28.88#ibcon#about to read 4, iclass 27, count 0 2006.231.08:00:28.88#ibcon#read 4, iclass 27, count 0 2006.231.08:00:28.88#ibcon#about to read 5, iclass 27, count 0 2006.231.08:00:28.88#ibcon#read 5, iclass 27, count 0 2006.231.08:00:28.88#ibcon#about to read 6, iclass 27, count 0 2006.231.08:00:28.88#ibcon#read 6, iclass 27, count 0 2006.231.08:00:28.88#ibcon#end of sib2, iclass 27, count 0 2006.231.08:00:28.88#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:00:28.88#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:00:28.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:00:28.88#ibcon#*before write, iclass 27, count 0 2006.231.08:00:28.88#ibcon#enter sib2, iclass 27, count 0 2006.231.08:00:28.88#ibcon#flushed, iclass 27, count 0 2006.231.08:00:28.88#ibcon#about to write, iclass 27, count 0 2006.231.08:00:28.88#ibcon#wrote, iclass 27, count 0 2006.231.08:00:28.88#ibcon#about to read 3, iclass 27, count 0 2006.231.08:00:28.92#ibcon#read 3, iclass 27, count 0 2006.231.08:00:28.92#ibcon#about to read 4, iclass 27, count 0 2006.231.08:00:28.92#ibcon#read 4, iclass 27, count 0 2006.231.08:00:28.92#ibcon#about to read 5, iclass 27, count 0 2006.231.08:00:28.92#ibcon#read 5, iclass 27, count 0 2006.231.08:00:28.92#ibcon#about to read 6, iclass 27, count 0 2006.231.08:00:28.92#ibcon#read 6, iclass 27, count 0 2006.231.08:00:28.92#ibcon#end of sib2, iclass 27, count 0 2006.231.08:00:28.92#ibcon#*after write, iclass 27, count 0 2006.231.08:00:28.92#ibcon#*before return 0, iclass 27, count 0 2006.231.08:00:28.92#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:00:28.92#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:00:28.92#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:00:28.92#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:00:28.92$vc4f8/va=4,7 2006.231.08:00:28.92#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.231.08:00:28.92#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.231.08:00:28.92#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:28.92#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:00:28.98#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:00:28.98#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:00:28.98#ibcon#enter wrdev, iclass 29, count 2 2006.231.08:00:28.98#ibcon#first serial, iclass 29, count 2 2006.231.08:00:28.98#ibcon#enter sib2, iclass 29, count 2 2006.231.08:00:28.98#ibcon#flushed, iclass 29, count 2 2006.231.08:00:28.98#ibcon#about to write, iclass 29, count 2 2006.231.08:00:28.98#ibcon#wrote, iclass 29, count 2 2006.231.08:00:28.98#ibcon#about to read 3, iclass 29, count 2 2006.231.08:00:29.00#ibcon#read 3, iclass 29, count 2 2006.231.08:00:29.00#ibcon#about to read 4, iclass 29, count 2 2006.231.08:00:29.00#ibcon#read 4, iclass 29, count 2 2006.231.08:00:29.00#ibcon#about to read 5, iclass 29, count 2 2006.231.08:00:29.00#ibcon#read 5, iclass 29, count 2 2006.231.08:00:29.00#ibcon#about to read 6, iclass 29, count 2 2006.231.08:00:29.00#ibcon#read 6, iclass 29, count 2 2006.231.08:00:29.00#ibcon#end of sib2, iclass 29, count 2 2006.231.08:00:29.00#ibcon#*mode == 0, iclass 29, count 2 2006.231.08:00:29.00#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.231.08:00:29.00#ibcon#[25=AT04-07\r\n] 2006.231.08:00:29.00#ibcon#*before write, iclass 29, count 2 2006.231.08:00:29.00#ibcon#enter sib2, iclass 29, count 2 2006.231.08:00:29.00#ibcon#flushed, iclass 29, count 2 2006.231.08:00:29.00#ibcon#about to write, iclass 29, count 2 2006.231.08:00:29.00#ibcon#wrote, iclass 29, count 2 2006.231.08:00:29.00#ibcon#about to read 3, iclass 29, count 2 2006.231.08:00:29.03#ibcon#read 3, iclass 29, count 2 2006.231.08:00:29.03#ibcon#about to read 4, iclass 29, count 2 2006.231.08:00:29.03#ibcon#read 4, iclass 29, count 2 2006.231.08:00:29.03#ibcon#about to read 5, iclass 29, count 2 2006.231.08:00:29.03#ibcon#read 5, iclass 29, count 2 2006.231.08:00:29.03#ibcon#about to read 6, iclass 29, count 2 2006.231.08:00:29.03#ibcon#read 6, iclass 29, count 2 2006.231.08:00:29.03#ibcon#end of sib2, iclass 29, count 2 2006.231.08:00:29.03#ibcon#*after write, iclass 29, count 2 2006.231.08:00:29.03#ibcon#*before return 0, iclass 29, count 2 2006.231.08:00:29.03#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:00:29.03#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:00:29.03#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.231.08:00:29.03#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:29.03#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:00:29.15#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:00:29.15#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:00:29.15#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:00:29.15#ibcon#first serial, iclass 29, count 0 2006.231.08:00:29.15#ibcon#enter sib2, iclass 29, count 0 2006.231.08:00:29.15#ibcon#flushed, iclass 29, count 0 2006.231.08:00:29.15#ibcon#about to write, iclass 29, count 0 2006.231.08:00:29.15#ibcon#wrote, iclass 29, count 0 2006.231.08:00:29.15#ibcon#about to read 3, iclass 29, count 0 2006.231.08:00:29.17#ibcon#read 3, iclass 29, count 0 2006.231.08:00:29.17#ibcon#about to read 4, iclass 29, count 0 2006.231.08:00:29.17#ibcon#read 4, iclass 29, count 0 2006.231.08:00:29.17#ibcon#about to read 5, iclass 29, count 0 2006.231.08:00:29.17#ibcon#read 5, iclass 29, count 0 2006.231.08:00:29.17#ibcon#about to read 6, iclass 29, count 0 2006.231.08:00:29.17#ibcon#read 6, iclass 29, count 0 2006.231.08:00:29.17#ibcon#end of sib2, iclass 29, count 0 2006.231.08:00:29.17#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:00:29.17#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:00:29.17#ibcon#[25=USB\r\n] 2006.231.08:00:29.17#ibcon#*before write, iclass 29, count 0 2006.231.08:00:29.17#ibcon#enter sib2, iclass 29, count 0 2006.231.08:00:29.17#ibcon#flushed, iclass 29, count 0 2006.231.08:00:29.17#ibcon#about to write, iclass 29, count 0 2006.231.08:00:29.17#ibcon#wrote, iclass 29, count 0 2006.231.08:00:29.17#ibcon#about to read 3, iclass 29, count 0 2006.231.08:00:29.20#ibcon#read 3, iclass 29, count 0 2006.231.08:00:29.20#ibcon#about to read 4, iclass 29, count 0 2006.231.08:00:29.20#ibcon#read 4, iclass 29, count 0 2006.231.08:00:29.20#ibcon#about to read 5, iclass 29, count 0 2006.231.08:00:29.20#ibcon#read 5, iclass 29, count 0 2006.231.08:00:29.20#ibcon#about to read 6, iclass 29, count 0 2006.231.08:00:29.20#ibcon#read 6, iclass 29, count 0 2006.231.08:00:29.20#ibcon#end of sib2, iclass 29, count 0 2006.231.08:00:29.20#ibcon#*after write, iclass 29, count 0 2006.231.08:00:29.20#ibcon#*before return 0, iclass 29, count 0 2006.231.08:00:29.20#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:00:29.20#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:00:29.20#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:00:29.20#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:00:29.20$vc4f8/valo=5,652.99 2006.231.08:00:29.20#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.231.08:00:29.20#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.231.08:00:29.20#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:29.20#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:00:29.20#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:00:29.20#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:00:29.20#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:00:29.20#ibcon#first serial, iclass 31, count 0 2006.231.08:00:29.20#ibcon#enter sib2, iclass 31, count 0 2006.231.08:00:29.20#ibcon#flushed, iclass 31, count 0 2006.231.08:00:29.20#ibcon#about to write, iclass 31, count 0 2006.231.08:00:29.20#ibcon#wrote, iclass 31, count 0 2006.231.08:00:29.20#ibcon#about to read 3, iclass 31, count 0 2006.231.08:00:29.22#ibcon#read 3, iclass 31, count 0 2006.231.08:00:29.22#ibcon#about to read 4, iclass 31, count 0 2006.231.08:00:29.22#ibcon#read 4, iclass 31, count 0 2006.231.08:00:29.22#ibcon#about to read 5, iclass 31, count 0 2006.231.08:00:29.22#ibcon#read 5, iclass 31, count 0 2006.231.08:00:29.22#ibcon#about to read 6, iclass 31, count 0 2006.231.08:00:29.22#ibcon#read 6, iclass 31, count 0 2006.231.08:00:29.22#ibcon#end of sib2, iclass 31, count 0 2006.231.08:00:29.22#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:00:29.22#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:00:29.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:00:29.22#ibcon#*before write, iclass 31, count 0 2006.231.08:00:29.22#ibcon#enter sib2, iclass 31, count 0 2006.231.08:00:29.22#ibcon#flushed, iclass 31, count 0 2006.231.08:00:29.22#ibcon#about to write, iclass 31, count 0 2006.231.08:00:29.22#ibcon#wrote, iclass 31, count 0 2006.231.08:00:29.22#ibcon#about to read 3, iclass 31, count 0 2006.231.08:00:29.26#ibcon#read 3, iclass 31, count 0 2006.231.08:00:29.26#ibcon#about to read 4, iclass 31, count 0 2006.231.08:00:29.26#ibcon#read 4, iclass 31, count 0 2006.231.08:00:29.26#ibcon#about to read 5, iclass 31, count 0 2006.231.08:00:29.26#ibcon#read 5, iclass 31, count 0 2006.231.08:00:29.26#ibcon#about to read 6, iclass 31, count 0 2006.231.08:00:29.26#ibcon#read 6, iclass 31, count 0 2006.231.08:00:29.26#ibcon#end of sib2, iclass 31, count 0 2006.231.08:00:29.26#ibcon#*after write, iclass 31, count 0 2006.231.08:00:29.26#ibcon#*before return 0, iclass 31, count 0 2006.231.08:00:29.26#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:00:29.26#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:00:29.26#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:00:29.26#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:00:29.26$vc4f8/va=5,7 2006.231.08:00:29.26#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.231.08:00:29.26#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.231.08:00:29.26#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:29.26#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:00:29.32#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:00:29.32#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:00:29.32#ibcon#enter wrdev, iclass 33, count 2 2006.231.08:00:29.32#ibcon#first serial, iclass 33, count 2 2006.231.08:00:29.32#ibcon#enter sib2, iclass 33, count 2 2006.231.08:00:29.32#ibcon#flushed, iclass 33, count 2 2006.231.08:00:29.32#ibcon#about to write, iclass 33, count 2 2006.231.08:00:29.32#ibcon#wrote, iclass 33, count 2 2006.231.08:00:29.32#ibcon#about to read 3, iclass 33, count 2 2006.231.08:00:29.34#ibcon#read 3, iclass 33, count 2 2006.231.08:00:29.34#ibcon#about to read 4, iclass 33, count 2 2006.231.08:00:29.34#ibcon#read 4, iclass 33, count 2 2006.231.08:00:29.34#ibcon#about to read 5, iclass 33, count 2 2006.231.08:00:29.34#ibcon#read 5, iclass 33, count 2 2006.231.08:00:29.34#ibcon#about to read 6, iclass 33, count 2 2006.231.08:00:29.34#ibcon#read 6, iclass 33, count 2 2006.231.08:00:29.34#ibcon#end of sib2, iclass 33, count 2 2006.231.08:00:29.34#ibcon#*mode == 0, iclass 33, count 2 2006.231.08:00:29.34#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.231.08:00:29.34#ibcon#[25=AT05-07\r\n] 2006.231.08:00:29.34#ibcon#*before write, iclass 33, count 2 2006.231.08:00:29.34#ibcon#enter sib2, iclass 33, count 2 2006.231.08:00:29.34#ibcon#flushed, iclass 33, count 2 2006.231.08:00:29.34#ibcon#about to write, iclass 33, count 2 2006.231.08:00:29.34#ibcon#wrote, iclass 33, count 2 2006.231.08:00:29.34#ibcon#about to read 3, iclass 33, count 2 2006.231.08:00:29.37#ibcon#read 3, iclass 33, count 2 2006.231.08:00:29.37#ibcon#about to read 4, iclass 33, count 2 2006.231.08:00:29.37#ibcon#read 4, iclass 33, count 2 2006.231.08:00:29.37#ibcon#about to read 5, iclass 33, count 2 2006.231.08:00:29.37#ibcon#read 5, iclass 33, count 2 2006.231.08:00:29.37#ibcon#about to read 6, iclass 33, count 2 2006.231.08:00:29.37#ibcon#read 6, iclass 33, count 2 2006.231.08:00:29.37#ibcon#end of sib2, iclass 33, count 2 2006.231.08:00:29.37#ibcon#*after write, iclass 33, count 2 2006.231.08:00:29.37#ibcon#*before return 0, iclass 33, count 2 2006.231.08:00:29.37#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:00:29.37#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:00:29.37#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.231.08:00:29.37#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:29.37#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:00:29.49#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:00:29.49#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:00:29.49#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:00:29.49#ibcon#first serial, iclass 33, count 0 2006.231.08:00:29.49#ibcon#enter sib2, iclass 33, count 0 2006.231.08:00:29.49#ibcon#flushed, iclass 33, count 0 2006.231.08:00:29.49#ibcon#about to write, iclass 33, count 0 2006.231.08:00:29.49#ibcon#wrote, iclass 33, count 0 2006.231.08:00:29.49#ibcon#about to read 3, iclass 33, count 0 2006.231.08:00:29.51#ibcon#read 3, iclass 33, count 0 2006.231.08:00:29.51#ibcon#about to read 4, iclass 33, count 0 2006.231.08:00:29.51#ibcon#read 4, iclass 33, count 0 2006.231.08:00:29.51#ibcon#about to read 5, iclass 33, count 0 2006.231.08:00:29.51#ibcon#read 5, iclass 33, count 0 2006.231.08:00:29.51#ibcon#about to read 6, iclass 33, count 0 2006.231.08:00:29.51#ibcon#read 6, iclass 33, count 0 2006.231.08:00:29.51#ibcon#end of sib2, iclass 33, count 0 2006.231.08:00:29.51#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:00:29.51#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:00:29.51#ibcon#[25=USB\r\n] 2006.231.08:00:29.51#ibcon#*before write, iclass 33, count 0 2006.231.08:00:29.51#ibcon#enter sib2, iclass 33, count 0 2006.231.08:00:29.51#ibcon#flushed, iclass 33, count 0 2006.231.08:00:29.51#ibcon#about to write, iclass 33, count 0 2006.231.08:00:29.51#ibcon#wrote, iclass 33, count 0 2006.231.08:00:29.51#ibcon#about to read 3, iclass 33, count 0 2006.231.08:00:29.54#ibcon#read 3, iclass 33, count 0 2006.231.08:00:29.54#ibcon#about to read 4, iclass 33, count 0 2006.231.08:00:29.54#ibcon#read 4, iclass 33, count 0 2006.231.08:00:29.54#ibcon#about to read 5, iclass 33, count 0 2006.231.08:00:29.54#ibcon#read 5, iclass 33, count 0 2006.231.08:00:29.54#ibcon#about to read 6, iclass 33, count 0 2006.231.08:00:29.54#ibcon#read 6, iclass 33, count 0 2006.231.08:00:29.54#ibcon#end of sib2, iclass 33, count 0 2006.231.08:00:29.54#ibcon#*after write, iclass 33, count 0 2006.231.08:00:29.54#ibcon#*before return 0, iclass 33, count 0 2006.231.08:00:29.54#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:00:29.54#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:00:29.54#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:00:29.54#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:00:29.54$vc4f8/valo=6,772.99 2006.231.08:00:29.54#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.231.08:00:29.54#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.231.08:00:29.54#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:29.54#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:00:29.54#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:00:29.54#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:00:29.54#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:00:29.54#ibcon#first serial, iclass 35, count 0 2006.231.08:00:29.54#ibcon#enter sib2, iclass 35, count 0 2006.231.08:00:29.54#ibcon#flushed, iclass 35, count 0 2006.231.08:00:29.54#ibcon#about to write, iclass 35, count 0 2006.231.08:00:29.54#ibcon#wrote, iclass 35, count 0 2006.231.08:00:29.54#ibcon#about to read 3, iclass 35, count 0 2006.231.08:00:29.56#ibcon#read 3, iclass 35, count 0 2006.231.08:00:29.56#ibcon#about to read 4, iclass 35, count 0 2006.231.08:00:29.56#ibcon#read 4, iclass 35, count 0 2006.231.08:00:29.56#ibcon#about to read 5, iclass 35, count 0 2006.231.08:00:29.56#ibcon#read 5, iclass 35, count 0 2006.231.08:00:29.56#ibcon#about to read 6, iclass 35, count 0 2006.231.08:00:29.56#ibcon#read 6, iclass 35, count 0 2006.231.08:00:29.56#ibcon#end of sib2, iclass 35, count 0 2006.231.08:00:29.56#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:00:29.56#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:00:29.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:00:29.56#ibcon#*before write, iclass 35, count 0 2006.231.08:00:29.56#ibcon#enter sib2, iclass 35, count 0 2006.231.08:00:29.56#ibcon#flushed, iclass 35, count 0 2006.231.08:00:29.56#ibcon#about to write, iclass 35, count 0 2006.231.08:00:29.56#ibcon#wrote, iclass 35, count 0 2006.231.08:00:29.56#ibcon#about to read 3, iclass 35, count 0 2006.231.08:00:29.60#ibcon#read 3, iclass 35, count 0 2006.231.08:00:29.60#ibcon#about to read 4, iclass 35, count 0 2006.231.08:00:29.60#ibcon#read 4, iclass 35, count 0 2006.231.08:00:29.60#ibcon#about to read 5, iclass 35, count 0 2006.231.08:00:29.60#ibcon#read 5, iclass 35, count 0 2006.231.08:00:29.60#ibcon#about to read 6, iclass 35, count 0 2006.231.08:00:29.60#ibcon#read 6, iclass 35, count 0 2006.231.08:00:29.60#ibcon#end of sib2, iclass 35, count 0 2006.231.08:00:29.60#ibcon#*after write, iclass 35, count 0 2006.231.08:00:29.60#ibcon#*before return 0, iclass 35, count 0 2006.231.08:00:29.60#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:00:29.60#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:00:29.60#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:00:29.60#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:00:29.60$vc4f8/va=6,6 2006.231.08:00:29.60#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.231.08:00:29.60#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.231.08:00:29.60#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:29.60#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:00:29.66#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:00:29.66#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:00:29.66#ibcon#enter wrdev, iclass 37, count 2 2006.231.08:00:29.66#ibcon#first serial, iclass 37, count 2 2006.231.08:00:29.66#ibcon#enter sib2, iclass 37, count 2 2006.231.08:00:29.66#ibcon#flushed, iclass 37, count 2 2006.231.08:00:29.66#ibcon#about to write, iclass 37, count 2 2006.231.08:00:29.66#ibcon#wrote, iclass 37, count 2 2006.231.08:00:29.66#ibcon#about to read 3, iclass 37, count 2 2006.231.08:00:29.68#ibcon#read 3, iclass 37, count 2 2006.231.08:00:29.68#ibcon#about to read 4, iclass 37, count 2 2006.231.08:00:29.68#ibcon#read 4, iclass 37, count 2 2006.231.08:00:29.68#ibcon#about to read 5, iclass 37, count 2 2006.231.08:00:29.68#ibcon#read 5, iclass 37, count 2 2006.231.08:00:29.68#ibcon#about to read 6, iclass 37, count 2 2006.231.08:00:29.68#ibcon#read 6, iclass 37, count 2 2006.231.08:00:29.68#ibcon#end of sib2, iclass 37, count 2 2006.231.08:00:29.68#ibcon#*mode == 0, iclass 37, count 2 2006.231.08:00:29.68#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.231.08:00:29.68#ibcon#[25=AT06-06\r\n] 2006.231.08:00:29.68#ibcon#*before write, iclass 37, count 2 2006.231.08:00:29.68#ibcon#enter sib2, iclass 37, count 2 2006.231.08:00:29.68#ibcon#flushed, iclass 37, count 2 2006.231.08:00:29.68#ibcon#about to write, iclass 37, count 2 2006.231.08:00:29.68#ibcon#wrote, iclass 37, count 2 2006.231.08:00:29.68#ibcon#about to read 3, iclass 37, count 2 2006.231.08:00:29.71#ibcon#read 3, iclass 37, count 2 2006.231.08:00:29.71#ibcon#about to read 4, iclass 37, count 2 2006.231.08:00:29.71#ibcon#read 4, iclass 37, count 2 2006.231.08:00:29.71#ibcon#about to read 5, iclass 37, count 2 2006.231.08:00:29.71#ibcon#read 5, iclass 37, count 2 2006.231.08:00:29.71#ibcon#about to read 6, iclass 37, count 2 2006.231.08:00:29.71#ibcon#read 6, iclass 37, count 2 2006.231.08:00:29.71#ibcon#end of sib2, iclass 37, count 2 2006.231.08:00:29.71#ibcon#*after write, iclass 37, count 2 2006.231.08:00:29.71#ibcon#*before return 0, iclass 37, count 2 2006.231.08:00:29.71#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:00:29.71#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:00:29.71#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.231.08:00:29.71#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:29.71#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:00:29.72#abcon#<5=/06 4.1 7.3 30.53 861004.5\r\n> 2006.231.08:00:29.74#abcon#{5=INTERFACE CLEAR} 2006.231.08:00:29.80#abcon#[5=S1D000X0/0*\r\n] 2006.231.08:00:29.83#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:00:29.83#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:00:29.83#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:00:29.83#ibcon#first serial, iclass 37, count 0 2006.231.08:00:29.83#ibcon#enter sib2, iclass 37, count 0 2006.231.08:00:29.83#ibcon#flushed, iclass 37, count 0 2006.231.08:00:29.83#ibcon#about to write, iclass 37, count 0 2006.231.08:00:29.83#ibcon#wrote, iclass 37, count 0 2006.231.08:00:29.83#ibcon#about to read 3, iclass 37, count 0 2006.231.08:00:29.85#ibcon#read 3, iclass 37, count 0 2006.231.08:00:29.85#ibcon#about to read 4, iclass 37, count 0 2006.231.08:00:29.85#ibcon#read 4, iclass 37, count 0 2006.231.08:00:29.85#ibcon#about to read 5, iclass 37, count 0 2006.231.08:00:29.85#ibcon#read 5, iclass 37, count 0 2006.231.08:00:29.85#ibcon#about to read 6, iclass 37, count 0 2006.231.08:00:29.85#ibcon#read 6, iclass 37, count 0 2006.231.08:00:29.85#ibcon#end of sib2, iclass 37, count 0 2006.231.08:00:29.85#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:00:29.85#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:00:29.85#ibcon#[25=USB\r\n] 2006.231.08:00:29.85#ibcon#*before write, iclass 37, count 0 2006.231.08:00:29.85#ibcon#enter sib2, iclass 37, count 0 2006.231.08:00:29.85#ibcon#flushed, iclass 37, count 0 2006.231.08:00:29.85#ibcon#about to write, iclass 37, count 0 2006.231.08:00:29.85#ibcon#wrote, iclass 37, count 0 2006.231.08:00:29.85#ibcon#about to read 3, iclass 37, count 0 2006.231.08:00:29.88#ibcon#read 3, iclass 37, count 0 2006.231.08:00:29.88#ibcon#about to read 4, iclass 37, count 0 2006.231.08:00:29.88#ibcon#read 4, iclass 37, count 0 2006.231.08:00:29.88#ibcon#about to read 5, iclass 37, count 0 2006.231.08:00:29.88#ibcon#read 5, iclass 37, count 0 2006.231.08:00:29.88#ibcon#about to read 6, iclass 37, count 0 2006.231.08:00:29.88#ibcon#read 6, iclass 37, count 0 2006.231.08:00:29.88#ibcon#end of sib2, iclass 37, count 0 2006.231.08:00:29.88#ibcon#*after write, iclass 37, count 0 2006.231.08:00:29.88#ibcon#*before return 0, iclass 37, count 0 2006.231.08:00:29.88#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:00:29.88#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:00:29.88#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:00:29.88#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:00:29.88$vc4f8/valo=7,832.99 2006.231.08:00:29.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.231.08:00:29.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.231.08:00:29.88#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:29.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:00:29.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:00:29.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:00:29.88#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:00:29.88#ibcon#first serial, iclass 5, count 0 2006.231.08:00:29.88#ibcon#enter sib2, iclass 5, count 0 2006.231.08:00:29.88#ibcon#flushed, iclass 5, count 0 2006.231.08:00:29.88#ibcon#about to write, iclass 5, count 0 2006.231.08:00:29.88#ibcon#wrote, iclass 5, count 0 2006.231.08:00:29.88#ibcon#about to read 3, iclass 5, count 0 2006.231.08:00:29.90#ibcon#read 3, iclass 5, count 0 2006.231.08:00:29.90#ibcon#about to read 4, iclass 5, count 0 2006.231.08:00:29.90#ibcon#read 4, iclass 5, count 0 2006.231.08:00:29.90#ibcon#about to read 5, iclass 5, count 0 2006.231.08:00:29.90#ibcon#read 5, iclass 5, count 0 2006.231.08:00:29.90#ibcon#about to read 6, iclass 5, count 0 2006.231.08:00:29.90#ibcon#read 6, iclass 5, count 0 2006.231.08:00:29.90#ibcon#end of sib2, iclass 5, count 0 2006.231.08:00:29.90#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:00:29.90#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:00:29.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:00:29.90#ibcon#*before write, iclass 5, count 0 2006.231.08:00:29.90#ibcon#enter sib2, iclass 5, count 0 2006.231.08:00:29.90#ibcon#flushed, iclass 5, count 0 2006.231.08:00:29.90#ibcon#about to write, iclass 5, count 0 2006.231.08:00:29.90#ibcon#wrote, iclass 5, count 0 2006.231.08:00:29.90#ibcon#about to read 3, iclass 5, count 0 2006.231.08:00:29.94#ibcon#read 3, iclass 5, count 0 2006.231.08:00:29.94#ibcon#about to read 4, iclass 5, count 0 2006.231.08:00:29.94#ibcon#read 4, iclass 5, count 0 2006.231.08:00:29.94#ibcon#about to read 5, iclass 5, count 0 2006.231.08:00:29.94#ibcon#read 5, iclass 5, count 0 2006.231.08:00:29.94#ibcon#about to read 6, iclass 5, count 0 2006.231.08:00:29.94#ibcon#read 6, iclass 5, count 0 2006.231.08:00:29.94#ibcon#end of sib2, iclass 5, count 0 2006.231.08:00:29.94#ibcon#*after write, iclass 5, count 0 2006.231.08:00:29.94#ibcon#*before return 0, iclass 5, count 0 2006.231.08:00:29.94#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:00:29.94#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:00:29.94#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:00:29.94#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:00:29.94$vc4f8/va=7,6 2006.231.08:00:29.94#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.231.08:00:29.94#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.231.08:00:29.94#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:29.94#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:00:30.00#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:00:30.00#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:00:30.00#ibcon#enter wrdev, iclass 7, count 2 2006.231.08:00:30.00#ibcon#first serial, iclass 7, count 2 2006.231.08:00:30.00#ibcon#enter sib2, iclass 7, count 2 2006.231.08:00:30.00#ibcon#flushed, iclass 7, count 2 2006.231.08:00:30.00#ibcon#about to write, iclass 7, count 2 2006.231.08:00:30.00#ibcon#wrote, iclass 7, count 2 2006.231.08:00:30.00#ibcon#about to read 3, iclass 7, count 2 2006.231.08:00:30.02#ibcon#read 3, iclass 7, count 2 2006.231.08:00:30.02#ibcon#about to read 4, iclass 7, count 2 2006.231.08:00:30.02#ibcon#read 4, iclass 7, count 2 2006.231.08:00:30.02#ibcon#about to read 5, iclass 7, count 2 2006.231.08:00:30.02#ibcon#read 5, iclass 7, count 2 2006.231.08:00:30.02#ibcon#about to read 6, iclass 7, count 2 2006.231.08:00:30.02#ibcon#read 6, iclass 7, count 2 2006.231.08:00:30.02#ibcon#end of sib2, iclass 7, count 2 2006.231.08:00:30.02#ibcon#*mode == 0, iclass 7, count 2 2006.231.08:00:30.02#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.231.08:00:30.02#ibcon#[25=AT07-06\r\n] 2006.231.08:00:30.02#ibcon#*before write, iclass 7, count 2 2006.231.08:00:30.02#ibcon#enter sib2, iclass 7, count 2 2006.231.08:00:30.02#ibcon#flushed, iclass 7, count 2 2006.231.08:00:30.02#ibcon#about to write, iclass 7, count 2 2006.231.08:00:30.02#ibcon#wrote, iclass 7, count 2 2006.231.08:00:30.02#ibcon#about to read 3, iclass 7, count 2 2006.231.08:00:30.05#ibcon#read 3, iclass 7, count 2 2006.231.08:00:30.05#ibcon#about to read 4, iclass 7, count 2 2006.231.08:00:30.05#ibcon#read 4, iclass 7, count 2 2006.231.08:00:30.05#ibcon#about to read 5, iclass 7, count 2 2006.231.08:00:30.05#ibcon#read 5, iclass 7, count 2 2006.231.08:00:30.05#ibcon#about to read 6, iclass 7, count 2 2006.231.08:00:30.05#ibcon#read 6, iclass 7, count 2 2006.231.08:00:30.05#ibcon#end of sib2, iclass 7, count 2 2006.231.08:00:30.05#ibcon#*after write, iclass 7, count 2 2006.231.08:00:30.05#ibcon#*before return 0, iclass 7, count 2 2006.231.08:00:30.05#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:00:30.05#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:00:30.05#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.231.08:00:30.05#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:30.05#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:00:30.17#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:00:30.17#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:00:30.17#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:00:30.17#ibcon#first serial, iclass 7, count 0 2006.231.08:00:30.17#ibcon#enter sib2, iclass 7, count 0 2006.231.08:00:30.17#ibcon#flushed, iclass 7, count 0 2006.231.08:00:30.17#ibcon#about to write, iclass 7, count 0 2006.231.08:00:30.17#ibcon#wrote, iclass 7, count 0 2006.231.08:00:30.17#ibcon#about to read 3, iclass 7, count 0 2006.231.08:00:30.20#ibcon#read 3, iclass 7, count 0 2006.231.08:00:30.20#ibcon#about to read 4, iclass 7, count 0 2006.231.08:00:30.20#ibcon#read 4, iclass 7, count 0 2006.231.08:00:30.20#ibcon#about to read 5, iclass 7, count 0 2006.231.08:00:30.20#ibcon#read 5, iclass 7, count 0 2006.231.08:00:30.20#ibcon#about to read 6, iclass 7, count 0 2006.231.08:00:30.20#ibcon#read 6, iclass 7, count 0 2006.231.08:00:30.20#ibcon#end of sib2, iclass 7, count 0 2006.231.08:00:30.20#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:00:30.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:00:30.20#ibcon#[25=USB\r\n] 2006.231.08:00:30.20#ibcon#*before write, iclass 7, count 0 2006.231.08:00:30.20#ibcon#enter sib2, iclass 7, count 0 2006.231.08:00:30.20#ibcon#flushed, iclass 7, count 0 2006.231.08:00:30.20#ibcon#about to write, iclass 7, count 0 2006.231.08:00:30.20#ibcon#wrote, iclass 7, count 0 2006.231.08:00:30.20#ibcon#about to read 3, iclass 7, count 0 2006.231.08:00:30.23#ibcon#read 3, iclass 7, count 0 2006.231.08:00:30.23#ibcon#about to read 4, iclass 7, count 0 2006.231.08:00:30.23#ibcon#read 4, iclass 7, count 0 2006.231.08:00:30.23#ibcon#about to read 5, iclass 7, count 0 2006.231.08:00:30.23#ibcon#read 5, iclass 7, count 0 2006.231.08:00:30.23#ibcon#about to read 6, iclass 7, count 0 2006.231.08:00:30.23#ibcon#read 6, iclass 7, count 0 2006.231.08:00:30.23#ibcon#end of sib2, iclass 7, count 0 2006.231.08:00:30.23#ibcon#*after write, iclass 7, count 0 2006.231.08:00:30.23#ibcon#*before return 0, iclass 7, count 0 2006.231.08:00:30.23#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:00:30.23#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:00:30.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:00:30.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:00:30.23$vc4f8/valo=8,852.99 2006.231.08:00:30.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.231.08:00:30.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.231.08:00:30.23#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:30.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:00:30.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:00:30.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:00:30.23#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:00:30.23#ibcon#first serial, iclass 11, count 0 2006.231.08:00:30.23#ibcon#enter sib2, iclass 11, count 0 2006.231.08:00:30.23#ibcon#flushed, iclass 11, count 0 2006.231.08:00:30.23#ibcon#about to write, iclass 11, count 0 2006.231.08:00:30.23#ibcon#wrote, iclass 11, count 0 2006.231.08:00:30.23#ibcon#about to read 3, iclass 11, count 0 2006.231.08:00:30.25#ibcon#read 3, iclass 11, count 0 2006.231.08:00:30.25#ibcon#about to read 4, iclass 11, count 0 2006.231.08:00:30.25#ibcon#read 4, iclass 11, count 0 2006.231.08:00:30.25#ibcon#about to read 5, iclass 11, count 0 2006.231.08:00:30.25#ibcon#read 5, iclass 11, count 0 2006.231.08:00:30.25#ibcon#about to read 6, iclass 11, count 0 2006.231.08:00:30.25#ibcon#read 6, iclass 11, count 0 2006.231.08:00:30.25#ibcon#end of sib2, iclass 11, count 0 2006.231.08:00:30.25#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:00:30.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:00:30.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:00:30.25#ibcon#*before write, iclass 11, count 0 2006.231.08:00:30.25#ibcon#enter sib2, iclass 11, count 0 2006.231.08:00:30.25#ibcon#flushed, iclass 11, count 0 2006.231.08:00:30.25#ibcon#about to write, iclass 11, count 0 2006.231.08:00:30.25#ibcon#wrote, iclass 11, count 0 2006.231.08:00:30.25#ibcon#about to read 3, iclass 11, count 0 2006.231.08:00:30.29#ibcon#read 3, iclass 11, count 0 2006.231.08:00:30.29#ibcon#about to read 4, iclass 11, count 0 2006.231.08:00:30.29#ibcon#read 4, iclass 11, count 0 2006.231.08:00:30.29#ibcon#about to read 5, iclass 11, count 0 2006.231.08:00:30.29#ibcon#read 5, iclass 11, count 0 2006.231.08:00:30.29#ibcon#about to read 6, iclass 11, count 0 2006.231.08:00:30.29#ibcon#read 6, iclass 11, count 0 2006.231.08:00:30.29#ibcon#end of sib2, iclass 11, count 0 2006.231.08:00:30.29#ibcon#*after write, iclass 11, count 0 2006.231.08:00:30.29#ibcon#*before return 0, iclass 11, count 0 2006.231.08:00:30.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:00:30.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:00:30.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:00:30.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:00:30.29$vc4f8/va=8,6 2006.231.08:00:30.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.231.08:00:30.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.231.08:00:30.29#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:30.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:00:30.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:00:30.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:00:30.35#ibcon#enter wrdev, iclass 13, count 2 2006.231.08:00:30.35#ibcon#first serial, iclass 13, count 2 2006.231.08:00:30.35#ibcon#enter sib2, iclass 13, count 2 2006.231.08:00:30.35#ibcon#flushed, iclass 13, count 2 2006.231.08:00:30.35#ibcon#about to write, iclass 13, count 2 2006.231.08:00:30.35#ibcon#wrote, iclass 13, count 2 2006.231.08:00:30.35#ibcon#about to read 3, iclass 13, count 2 2006.231.08:00:30.37#ibcon#read 3, iclass 13, count 2 2006.231.08:00:30.37#ibcon#about to read 4, iclass 13, count 2 2006.231.08:00:30.37#ibcon#read 4, iclass 13, count 2 2006.231.08:00:30.37#ibcon#about to read 5, iclass 13, count 2 2006.231.08:00:30.37#ibcon#read 5, iclass 13, count 2 2006.231.08:00:30.37#ibcon#about to read 6, iclass 13, count 2 2006.231.08:00:30.37#ibcon#read 6, iclass 13, count 2 2006.231.08:00:30.37#ibcon#end of sib2, iclass 13, count 2 2006.231.08:00:30.37#ibcon#*mode == 0, iclass 13, count 2 2006.231.08:00:30.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.231.08:00:30.37#ibcon#[25=AT08-06\r\n] 2006.231.08:00:30.37#ibcon#*before write, iclass 13, count 2 2006.231.08:00:30.37#ibcon#enter sib2, iclass 13, count 2 2006.231.08:00:30.37#ibcon#flushed, iclass 13, count 2 2006.231.08:00:30.37#ibcon#about to write, iclass 13, count 2 2006.231.08:00:30.37#ibcon#wrote, iclass 13, count 2 2006.231.08:00:30.37#ibcon#about to read 3, iclass 13, count 2 2006.231.08:00:30.40#ibcon#read 3, iclass 13, count 2 2006.231.08:00:30.40#ibcon#about to read 4, iclass 13, count 2 2006.231.08:00:30.40#ibcon#read 4, iclass 13, count 2 2006.231.08:00:30.40#ibcon#about to read 5, iclass 13, count 2 2006.231.08:00:30.40#ibcon#read 5, iclass 13, count 2 2006.231.08:00:30.40#ibcon#about to read 6, iclass 13, count 2 2006.231.08:00:30.40#ibcon#read 6, iclass 13, count 2 2006.231.08:00:30.40#ibcon#end of sib2, iclass 13, count 2 2006.231.08:00:30.40#ibcon#*after write, iclass 13, count 2 2006.231.08:00:30.40#ibcon#*before return 0, iclass 13, count 2 2006.231.08:00:30.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:00:30.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:00:30.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.231.08:00:30.40#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:30.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:00:30.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:00:30.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:00:30.52#ibcon#enter wrdev, iclass 13, count 0 2006.231.08:00:30.52#ibcon#first serial, iclass 13, count 0 2006.231.08:00:30.52#ibcon#enter sib2, iclass 13, count 0 2006.231.08:00:30.52#ibcon#flushed, iclass 13, count 0 2006.231.08:00:30.52#ibcon#about to write, iclass 13, count 0 2006.231.08:00:30.52#ibcon#wrote, iclass 13, count 0 2006.231.08:00:30.52#ibcon#about to read 3, iclass 13, count 0 2006.231.08:00:30.54#ibcon#read 3, iclass 13, count 0 2006.231.08:00:30.54#ibcon#about to read 4, iclass 13, count 0 2006.231.08:00:30.54#ibcon#read 4, iclass 13, count 0 2006.231.08:00:30.54#ibcon#about to read 5, iclass 13, count 0 2006.231.08:00:30.54#ibcon#read 5, iclass 13, count 0 2006.231.08:00:30.54#ibcon#about to read 6, iclass 13, count 0 2006.231.08:00:30.54#ibcon#read 6, iclass 13, count 0 2006.231.08:00:30.54#ibcon#end of sib2, iclass 13, count 0 2006.231.08:00:30.54#ibcon#*mode == 0, iclass 13, count 0 2006.231.08:00:30.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.08:00:30.54#ibcon#[25=USB\r\n] 2006.231.08:00:30.54#ibcon#*before write, iclass 13, count 0 2006.231.08:00:30.54#ibcon#enter sib2, iclass 13, count 0 2006.231.08:00:30.54#ibcon#flushed, iclass 13, count 0 2006.231.08:00:30.54#ibcon#about to write, iclass 13, count 0 2006.231.08:00:30.54#ibcon#wrote, iclass 13, count 0 2006.231.08:00:30.54#ibcon#about to read 3, iclass 13, count 0 2006.231.08:00:30.57#ibcon#read 3, iclass 13, count 0 2006.231.08:00:30.57#ibcon#about to read 4, iclass 13, count 0 2006.231.08:00:30.57#ibcon#read 4, iclass 13, count 0 2006.231.08:00:30.57#ibcon#about to read 5, iclass 13, count 0 2006.231.08:00:30.57#ibcon#read 5, iclass 13, count 0 2006.231.08:00:30.57#ibcon#about to read 6, iclass 13, count 0 2006.231.08:00:30.57#ibcon#read 6, iclass 13, count 0 2006.231.08:00:30.57#ibcon#end of sib2, iclass 13, count 0 2006.231.08:00:30.57#ibcon#*after write, iclass 13, count 0 2006.231.08:00:30.57#ibcon#*before return 0, iclass 13, count 0 2006.231.08:00:30.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:00:30.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:00:30.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.08:00:30.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.08:00:30.57$vc4f8/vblo=1,632.99 2006.231.08:00:30.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.08:00:30.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.08:00:30.57#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:30.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:00:30.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:00:30.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:00:30.57#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:00:30.57#ibcon#first serial, iclass 15, count 0 2006.231.08:00:30.57#ibcon#enter sib2, iclass 15, count 0 2006.231.08:00:30.57#ibcon#flushed, iclass 15, count 0 2006.231.08:00:30.57#ibcon#about to write, iclass 15, count 0 2006.231.08:00:30.57#ibcon#wrote, iclass 15, count 0 2006.231.08:00:30.57#ibcon#about to read 3, iclass 15, count 0 2006.231.08:00:30.59#ibcon#read 3, iclass 15, count 0 2006.231.08:00:30.59#ibcon#about to read 4, iclass 15, count 0 2006.231.08:00:30.59#ibcon#read 4, iclass 15, count 0 2006.231.08:00:30.59#ibcon#about to read 5, iclass 15, count 0 2006.231.08:00:30.59#ibcon#read 5, iclass 15, count 0 2006.231.08:00:30.59#ibcon#about to read 6, iclass 15, count 0 2006.231.08:00:30.59#ibcon#read 6, iclass 15, count 0 2006.231.08:00:30.59#ibcon#end of sib2, iclass 15, count 0 2006.231.08:00:30.59#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:00:30.59#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:00:30.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:00:30.59#ibcon#*before write, iclass 15, count 0 2006.231.08:00:30.59#ibcon#enter sib2, iclass 15, count 0 2006.231.08:00:30.59#ibcon#flushed, iclass 15, count 0 2006.231.08:00:30.59#ibcon#about to write, iclass 15, count 0 2006.231.08:00:30.59#ibcon#wrote, iclass 15, count 0 2006.231.08:00:30.59#ibcon#about to read 3, iclass 15, count 0 2006.231.08:00:30.63#ibcon#read 3, iclass 15, count 0 2006.231.08:00:30.63#ibcon#about to read 4, iclass 15, count 0 2006.231.08:00:30.63#ibcon#read 4, iclass 15, count 0 2006.231.08:00:30.63#ibcon#about to read 5, iclass 15, count 0 2006.231.08:00:30.63#ibcon#read 5, iclass 15, count 0 2006.231.08:00:30.63#ibcon#about to read 6, iclass 15, count 0 2006.231.08:00:30.63#ibcon#read 6, iclass 15, count 0 2006.231.08:00:30.63#ibcon#end of sib2, iclass 15, count 0 2006.231.08:00:30.63#ibcon#*after write, iclass 15, count 0 2006.231.08:00:30.63#ibcon#*before return 0, iclass 15, count 0 2006.231.08:00:30.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:00:30.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:00:30.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:00:30.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:00:30.63$vc4f8/vb=1,4 2006.231.08:00:30.63#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.08:00:30.63#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.08:00:30.63#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:30.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:00:30.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:00:30.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:00:30.63#ibcon#enter wrdev, iclass 17, count 2 2006.231.08:00:30.63#ibcon#first serial, iclass 17, count 2 2006.231.08:00:30.63#ibcon#enter sib2, iclass 17, count 2 2006.231.08:00:30.63#ibcon#flushed, iclass 17, count 2 2006.231.08:00:30.63#ibcon#about to write, iclass 17, count 2 2006.231.08:00:30.63#ibcon#wrote, iclass 17, count 2 2006.231.08:00:30.63#ibcon#about to read 3, iclass 17, count 2 2006.231.08:00:30.65#ibcon#read 3, iclass 17, count 2 2006.231.08:00:30.65#ibcon#about to read 4, iclass 17, count 2 2006.231.08:00:30.65#ibcon#read 4, iclass 17, count 2 2006.231.08:00:30.65#ibcon#about to read 5, iclass 17, count 2 2006.231.08:00:30.65#ibcon#read 5, iclass 17, count 2 2006.231.08:00:30.65#ibcon#about to read 6, iclass 17, count 2 2006.231.08:00:30.65#ibcon#read 6, iclass 17, count 2 2006.231.08:00:30.65#ibcon#end of sib2, iclass 17, count 2 2006.231.08:00:30.65#ibcon#*mode == 0, iclass 17, count 2 2006.231.08:00:30.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.08:00:30.65#ibcon#[27=AT01-04\r\n] 2006.231.08:00:30.65#ibcon#*before write, iclass 17, count 2 2006.231.08:00:30.65#ibcon#enter sib2, iclass 17, count 2 2006.231.08:00:30.65#ibcon#flushed, iclass 17, count 2 2006.231.08:00:30.65#ibcon#about to write, iclass 17, count 2 2006.231.08:00:30.65#ibcon#wrote, iclass 17, count 2 2006.231.08:00:30.65#ibcon#about to read 3, iclass 17, count 2 2006.231.08:00:30.68#ibcon#read 3, iclass 17, count 2 2006.231.08:00:30.68#ibcon#about to read 4, iclass 17, count 2 2006.231.08:00:30.68#ibcon#read 4, iclass 17, count 2 2006.231.08:00:30.68#ibcon#about to read 5, iclass 17, count 2 2006.231.08:00:30.68#ibcon#read 5, iclass 17, count 2 2006.231.08:00:30.68#ibcon#about to read 6, iclass 17, count 2 2006.231.08:00:30.68#ibcon#read 6, iclass 17, count 2 2006.231.08:00:30.68#ibcon#end of sib2, iclass 17, count 2 2006.231.08:00:30.68#ibcon#*after write, iclass 17, count 2 2006.231.08:00:30.68#ibcon#*before return 0, iclass 17, count 2 2006.231.08:00:30.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:00:30.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:00:30.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.08:00:30.68#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:30.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:00:30.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:00:30.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:00:30.80#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:00:30.80#ibcon#first serial, iclass 17, count 0 2006.231.08:00:30.80#ibcon#enter sib2, iclass 17, count 0 2006.231.08:00:30.80#ibcon#flushed, iclass 17, count 0 2006.231.08:00:30.80#ibcon#about to write, iclass 17, count 0 2006.231.08:00:30.80#ibcon#wrote, iclass 17, count 0 2006.231.08:00:30.80#ibcon#about to read 3, iclass 17, count 0 2006.231.08:00:30.82#ibcon#read 3, iclass 17, count 0 2006.231.08:00:30.82#ibcon#about to read 4, iclass 17, count 0 2006.231.08:00:30.82#ibcon#read 4, iclass 17, count 0 2006.231.08:00:30.82#ibcon#about to read 5, iclass 17, count 0 2006.231.08:00:30.82#ibcon#read 5, iclass 17, count 0 2006.231.08:00:30.82#ibcon#about to read 6, iclass 17, count 0 2006.231.08:00:30.82#ibcon#read 6, iclass 17, count 0 2006.231.08:00:30.82#ibcon#end of sib2, iclass 17, count 0 2006.231.08:00:30.82#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:00:30.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:00:30.82#ibcon#[27=USB\r\n] 2006.231.08:00:30.82#ibcon#*before write, iclass 17, count 0 2006.231.08:00:30.82#ibcon#enter sib2, iclass 17, count 0 2006.231.08:00:30.82#ibcon#flushed, iclass 17, count 0 2006.231.08:00:30.82#ibcon#about to write, iclass 17, count 0 2006.231.08:00:30.82#ibcon#wrote, iclass 17, count 0 2006.231.08:00:30.82#ibcon#about to read 3, iclass 17, count 0 2006.231.08:00:30.85#ibcon#read 3, iclass 17, count 0 2006.231.08:00:30.85#ibcon#about to read 4, iclass 17, count 0 2006.231.08:00:30.85#ibcon#read 4, iclass 17, count 0 2006.231.08:00:30.85#ibcon#about to read 5, iclass 17, count 0 2006.231.08:00:30.85#ibcon#read 5, iclass 17, count 0 2006.231.08:00:30.85#ibcon#about to read 6, iclass 17, count 0 2006.231.08:00:30.85#ibcon#read 6, iclass 17, count 0 2006.231.08:00:30.85#ibcon#end of sib2, iclass 17, count 0 2006.231.08:00:30.85#ibcon#*after write, iclass 17, count 0 2006.231.08:00:30.85#ibcon#*before return 0, iclass 17, count 0 2006.231.08:00:30.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:00:30.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:00:30.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:00:30.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:00:30.85$vc4f8/vblo=2,640.99 2006.231.08:00:30.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.08:00:30.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.08:00:30.85#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:30.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:00:30.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:00:30.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:00:30.85#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:00:30.85#ibcon#first serial, iclass 19, count 0 2006.231.08:00:30.85#ibcon#enter sib2, iclass 19, count 0 2006.231.08:00:30.85#ibcon#flushed, iclass 19, count 0 2006.231.08:00:30.85#ibcon#about to write, iclass 19, count 0 2006.231.08:00:30.85#ibcon#wrote, iclass 19, count 0 2006.231.08:00:30.85#ibcon#about to read 3, iclass 19, count 0 2006.231.08:00:30.87#ibcon#read 3, iclass 19, count 0 2006.231.08:00:30.87#ibcon#about to read 4, iclass 19, count 0 2006.231.08:00:30.87#ibcon#read 4, iclass 19, count 0 2006.231.08:00:30.87#ibcon#about to read 5, iclass 19, count 0 2006.231.08:00:30.87#ibcon#read 5, iclass 19, count 0 2006.231.08:00:30.87#ibcon#about to read 6, iclass 19, count 0 2006.231.08:00:30.87#ibcon#read 6, iclass 19, count 0 2006.231.08:00:30.87#ibcon#end of sib2, iclass 19, count 0 2006.231.08:00:30.87#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:00:30.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:00:30.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:00:30.87#ibcon#*before write, iclass 19, count 0 2006.231.08:00:30.87#ibcon#enter sib2, iclass 19, count 0 2006.231.08:00:30.87#ibcon#flushed, iclass 19, count 0 2006.231.08:00:30.87#ibcon#about to write, iclass 19, count 0 2006.231.08:00:30.87#ibcon#wrote, iclass 19, count 0 2006.231.08:00:30.87#ibcon#about to read 3, iclass 19, count 0 2006.231.08:00:30.91#ibcon#read 3, iclass 19, count 0 2006.231.08:00:30.91#ibcon#about to read 4, iclass 19, count 0 2006.231.08:00:30.91#ibcon#read 4, iclass 19, count 0 2006.231.08:00:30.91#ibcon#about to read 5, iclass 19, count 0 2006.231.08:00:30.91#ibcon#read 5, iclass 19, count 0 2006.231.08:00:30.91#ibcon#about to read 6, iclass 19, count 0 2006.231.08:00:30.91#ibcon#read 6, iclass 19, count 0 2006.231.08:00:30.91#ibcon#end of sib2, iclass 19, count 0 2006.231.08:00:30.91#ibcon#*after write, iclass 19, count 0 2006.231.08:00:30.91#ibcon#*before return 0, iclass 19, count 0 2006.231.08:00:30.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:00:30.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:00:30.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:00:30.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:00:30.91$vc4f8/vb=2,4 2006.231.08:00:30.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.231.08:00:30.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.231.08:00:30.91#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:30.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:00:30.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:00:30.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:00:30.97#ibcon#enter wrdev, iclass 21, count 2 2006.231.08:00:30.97#ibcon#first serial, iclass 21, count 2 2006.231.08:00:30.97#ibcon#enter sib2, iclass 21, count 2 2006.231.08:00:30.97#ibcon#flushed, iclass 21, count 2 2006.231.08:00:30.97#ibcon#about to write, iclass 21, count 2 2006.231.08:00:30.97#ibcon#wrote, iclass 21, count 2 2006.231.08:00:30.97#ibcon#about to read 3, iclass 21, count 2 2006.231.08:00:30.99#ibcon#read 3, iclass 21, count 2 2006.231.08:00:30.99#ibcon#about to read 4, iclass 21, count 2 2006.231.08:00:30.99#ibcon#read 4, iclass 21, count 2 2006.231.08:00:30.99#ibcon#about to read 5, iclass 21, count 2 2006.231.08:00:30.99#ibcon#read 5, iclass 21, count 2 2006.231.08:00:30.99#ibcon#about to read 6, iclass 21, count 2 2006.231.08:00:30.99#ibcon#read 6, iclass 21, count 2 2006.231.08:00:30.99#ibcon#end of sib2, iclass 21, count 2 2006.231.08:00:30.99#ibcon#*mode == 0, iclass 21, count 2 2006.231.08:00:30.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.231.08:00:30.99#ibcon#[27=AT02-04\r\n] 2006.231.08:00:30.99#ibcon#*before write, iclass 21, count 2 2006.231.08:00:30.99#ibcon#enter sib2, iclass 21, count 2 2006.231.08:00:30.99#ibcon#flushed, iclass 21, count 2 2006.231.08:00:30.99#ibcon#about to write, iclass 21, count 2 2006.231.08:00:30.99#ibcon#wrote, iclass 21, count 2 2006.231.08:00:30.99#ibcon#about to read 3, iclass 21, count 2 2006.231.08:00:31.02#ibcon#read 3, iclass 21, count 2 2006.231.08:00:31.02#ibcon#about to read 4, iclass 21, count 2 2006.231.08:00:31.02#ibcon#read 4, iclass 21, count 2 2006.231.08:00:31.02#ibcon#about to read 5, iclass 21, count 2 2006.231.08:00:31.02#ibcon#read 5, iclass 21, count 2 2006.231.08:00:31.02#ibcon#about to read 6, iclass 21, count 2 2006.231.08:00:31.02#ibcon#read 6, iclass 21, count 2 2006.231.08:00:31.02#ibcon#end of sib2, iclass 21, count 2 2006.231.08:00:31.02#ibcon#*after write, iclass 21, count 2 2006.231.08:00:31.02#ibcon#*before return 0, iclass 21, count 2 2006.231.08:00:31.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:00:31.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:00:31.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.231.08:00:31.02#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:31.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:00:31.14#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:00:31.14#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:00:31.14#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:00:31.14#ibcon#first serial, iclass 21, count 0 2006.231.08:00:31.14#ibcon#enter sib2, iclass 21, count 0 2006.231.08:00:31.14#ibcon#flushed, iclass 21, count 0 2006.231.08:00:31.14#ibcon#about to write, iclass 21, count 0 2006.231.08:00:31.14#ibcon#wrote, iclass 21, count 0 2006.231.08:00:31.14#ibcon#about to read 3, iclass 21, count 0 2006.231.08:00:31.16#ibcon#read 3, iclass 21, count 0 2006.231.08:00:31.16#ibcon#about to read 4, iclass 21, count 0 2006.231.08:00:31.16#ibcon#read 4, iclass 21, count 0 2006.231.08:00:31.16#ibcon#about to read 5, iclass 21, count 0 2006.231.08:00:31.16#ibcon#read 5, iclass 21, count 0 2006.231.08:00:31.16#ibcon#about to read 6, iclass 21, count 0 2006.231.08:00:31.16#ibcon#read 6, iclass 21, count 0 2006.231.08:00:31.16#ibcon#end of sib2, iclass 21, count 0 2006.231.08:00:31.16#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:00:31.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:00:31.16#ibcon#[27=USB\r\n] 2006.231.08:00:31.16#ibcon#*before write, iclass 21, count 0 2006.231.08:00:31.16#ibcon#enter sib2, iclass 21, count 0 2006.231.08:00:31.16#ibcon#flushed, iclass 21, count 0 2006.231.08:00:31.16#ibcon#about to write, iclass 21, count 0 2006.231.08:00:31.16#ibcon#wrote, iclass 21, count 0 2006.231.08:00:31.16#ibcon#about to read 3, iclass 21, count 0 2006.231.08:00:31.19#ibcon#read 3, iclass 21, count 0 2006.231.08:00:31.19#ibcon#about to read 4, iclass 21, count 0 2006.231.08:00:31.19#ibcon#read 4, iclass 21, count 0 2006.231.08:00:31.19#ibcon#about to read 5, iclass 21, count 0 2006.231.08:00:31.19#ibcon#read 5, iclass 21, count 0 2006.231.08:00:31.19#ibcon#about to read 6, iclass 21, count 0 2006.231.08:00:31.19#ibcon#read 6, iclass 21, count 0 2006.231.08:00:31.19#ibcon#end of sib2, iclass 21, count 0 2006.231.08:00:31.19#ibcon#*after write, iclass 21, count 0 2006.231.08:00:31.19#ibcon#*before return 0, iclass 21, count 0 2006.231.08:00:31.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:00:31.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:00:31.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:00:31.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:00:31.19$vc4f8/vblo=3,656.99 2006.231.08:00:31.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.231.08:00:31.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.231.08:00:31.19#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:31.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:00:31.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:00:31.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:00:31.19#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:00:31.19#ibcon#first serial, iclass 23, count 0 2006.231.08:00:31.19#ibcon#enter sib2, iclass 23, count 0 2006.231.08:00:31.19#ibcon#flushed, iclass 23, count 0 2006.231.08:00:31.19#ibcon#about to write, iclass 23, count 0 2006.231.08:00:31.19#ibcon#wrote, iclass 23, count 0 2006.231.08:00:31.19#ibcon#about to read 3, iclass 23, count 0 2006.231.08:00:31.21#ibcon#read 3, iclass 23, count 0 2006.231.08:00:31.21#ibcon#about to read 4, iclass 23, count 0 2006.231.08:00:31.21#ibcon#read 4, iclass 23, count 0 2006.231.08:00:31.21#ibcon#about to read 5, iclass 23, count 0 2006.231.08:00:31.21#ibcon#read 5, iclass 23, count 0 2006.231.08:00:31.21#ibcon#about to read 6, iclass 23, count 0 2006.231.08:00:31.21#ibcon#read 6, iclass 23, count 0 2006.231.08:00:31.21#ibcon#end of sib2, iclass 23, count 0 2006.231.08:00:31.21#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:00:31.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:00:31.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:00:31.21#ibcon#*before write, iclass 23, count 0 2006.231.08:00:31.21#ibcon#enter sib2, iclass 23, count 0 2006.231.08:00:31.21#ibcon#flushed, iclass 23, count 0 2006.231.08:00:31.21#ibcon#about to write, iclass 23, count 0 2006.231.08:00:31.21#ibcon#wrote, iclass 23, count 0 2006.231.08:00:31.21#ibcon#about to read 3, iclass 23, count 0 2006.231.08:00:31.25#ibcon#read 3, iclass 23, count 0 2006.231.08:00:31.25#ibcon#about to read 4, iclass 23, count 0 2006.231.08:00:31.25#ibcon#read 4, iclass 23, count 0 2006.231.08:00:31.25#ibcon#about to read 5, iclass 23, count 0 2006.231.08:00:31.25#ibcon#read 5, iclass 23, count 0 2006.231.08:00:31.25#ibcon#about to read 6, iclass 23, count 0 2006.231.08:00:31.25#ibcon#read 6, iclass 23, count 0 2006.231.08:00:31.25#ibcon#end of sib2, iclass 23, count 0 2006.231.08:00:31.25#ibcon#*after write, iclass 23, count 0 2006.231.08:00:31.25#ibcon#*before return 0, iclass 23, count 0 2006.231.08:00:31.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:00:31.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:00:31.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:00:31.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:00:31.25$vc4f8/vb=3,4 2006.231.08:00:31.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.231.08:00:31.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.231.08:00:31.25#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:31.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:00:31.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:00:31.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:00:31.31#ibcon#enter wrdev, iclass 25, count 2 2006.231.08:00:31.31#ibcon#first serial, iclass 25, count 2 2006.231.08:00:31.31#ibcon#enter sib2, iclass 25, count 2 2006.231.08:00:31.31#ibcon#flushed, iclass 25, count 2 2006.231.08:00:31.31#ibcon#about to write, iclass 25, count 2 2006.231.08:00:31.31#ibcon#wrote, iclass 25, count 2 2006.231.08:00:31.31#ibcon#about to read 3, iclass 25, count 2 2006.231.08:00:31.33#ibcon#read 3, iclass 25, count 2 2006.231.08:00:31.33#ibcon#about to read 4, iclass 25, count 2 2006.231.08:00:31.33#ibcon#read 4, iclass 25, count 2 2006.231.08:00:31.33#ibcon#about to read 5, iclass 25, count 2 2006.231.08:00:31.33#ibcon#read 5, iclass 25, count 2 2006.231.08:00:31.33#ibcon#about to read 6, iclass 25, count 2 2006.231.08:00:31.33#ibcon#read 6, iclass 25, count 2 2006.231.08:00:31.33#ibcon#end of sib2, iclass 25, count 2 2006.231.08:00:31.33#ibcon#*mode == 0, iclass 25, count 2 2006.231.08:00:31.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.231.08:00:31.33#ibcon#[27=AT03-04\r\n] 2006.231.08:00:31.33#ibcon#*before write, iclass 25, count 2 2006.231.08:00:31.33#ibcon#enter sib2, iclass 25, count 2 2006.231.08:00:31.33#ibcon#flushed, iclass 25, count 2 2006.231.08:00:31.33#ibcon#about to write, iclass 25, count 2 2006.231.08:00:31.33#ibcon#wrote, iclass 25, count 2 2006.231.08:00:31.33#ibcon#about to read 3, iclass 25, count 2 2006.231.08:00:31.36#ibcon#read 3, iclass 25, count 2 2006.231.08:00:31.36#ibcon#about to read 4, iclass 25, count 2 2006.231.08:00:31.36#ibcon#read 4, iclass 25, count 2 2006.231.08:00:31.36#ibcon#about to read 5, iclass 25, count 2 2006.231.08:00:31.36#ibcon#read 5, iclass 25, count 2 2006.231.08:00:31.36#ibcon#about to read 6, iclass 25, count 2 2006.231.08:00:31.36#ibcon#read 6, iclass 25, count 2 2006.231.08:00:31.36#ibcon#end of sib2, iclass 25, count 2 2006.231.08:00:31.36#ibcon#*after write, iclass 25, count 2 2006.231.08:00:31.36#ibcon#*before return 0, iclass 25, count 2 2006.231.08:00:31.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:00:31.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:00:31.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.231.08:00:31.36#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:31.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:00:31.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:00:31.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:00:31.48#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:00:31.48#ibcon#first serial, iclass 25, count 0 2006.231.08:00:31.48#ibcon#enter sib2, iclass 25, count 0 2006.231.08:00:31.48#ibcon#flushed, iclass 25, count 0 2006.231.08:00:31.48#ibcon#about to write, iclass 25, count 0 2006.231.08:00:31.48#ibcon#wrote, iclass 25, count 0 2006.231.08:00:31.48#ibcon#about to read 3, iclass 25, count 0 2006.231.08:00:31.50#ibcon#read 3, iclass 25, count 0 2006.231.08:00:31.50#ibcon#about to read 4, iclass 25, count 0 2006.231.08:00:31.50#ibcon#read 4, iclass 25, count 0 2006.231.08:00:31.50#ibcon#about to read 5, iclass 25, count 0 2006.231.08:00:31.50#ibcon#read 5, iclass 25, count 0 2006.231.08:00:31.50#ibcon#about to read 6, iclass 25, count 0 2006.231.08:00:31.50#ibcon#read 6, iclass 25, count 0 2006.231.08:00:31.50#ibcon#end of sib2, iclass 25, count 0 2006.231.08:00:31.50#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:00:31.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:00:31.50#ibcon#[27=USB\r\n] 2006.231.08:00:31.50#ibcon#*before write, iclass 25, count 0 2006.231.08:00:31.50#ibcon#enter sib2, iclass 25, count 0 2006.231.08:00:31.50#ibcon#flushed, iclass 25, count 0 2006.231.08:00:31.50#ibcon#about to write, iclass 25, count 0 2006.231.08:00:31.50#ibcon#wrote, iclass 25, count 0 2006.231.08:00:31.50#ibcon#about to read 3, iclass 25, count 0 2006.231.08:00:31.53#ibcon#read 3, iclass 25, count 0 2006.231.08:00:31.53#ibcon#about to read 4, iclass 25, count 0 2006.231.08:00:31.53#ibcon#read 4, iclass 25, count 0 2006.231.08:00:31.53#ibcon#about to read 5, iclass 25, count 0 2006.231.08:00:31.53#ibcon#read 5, iclass 25, count 0 2006.231.08:00:31.53#ibcon#about to read 6, iclass 25, count 0 2006.231.08:00:31.53#ibcon#read 6, iclass 25, count 0 2006.231.08:00:31.53#ibcon#end of sib2, iclass 25, count 0 2006.231.08:00:31.53#ibcon#*after write, iclass 25, count 0 2006.231.08:00:31.53#ibcon#*before return 0, iclass 25, count 0 2006.231.08:00:31.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:00:31.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:00:31.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:00:31.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:00:31.53$vc4f8/vblo=4,712.99 2006.231.08:00:31.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.231.08:00:31.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.231.08:00:31.53#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:31.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:00:31.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:00:31.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:00:31.53#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:00:31.53#ibcon#first serial, iclass 27, count 0 2006.231.08:00:31.53#ibcon#enter sib2, iclass 27, count 0 2006.231.08:00:31.53#ibcon#flushed, iclass 27, count 0 2006.231.08:00:31.53#ibcon#about to write, iclass 27, count 0 2006.231.08:00:31.53#ibcon#wrote, iclass 27, count 0 2006.231.08:00:31.53#ibcon#about to read 3, iclass 27, count 0 2006.231.08:00:31.55#ibcon#read 3, iclass 27, count 0 2006.231.08:00:31.55#ibcon#about to read 4, iclass 27, count 0 2006.231.08:00:31.55#ibcon#read 4, iclass 27, count 0 2006.231.08:00:31.55#ibcon#about to read 5, iclass 27, count 0 2006.231.08:00:31.55#ibcon#read 5, iclass 27, count 0 2006.231.08:00:31.55#ibcon#about to read 6, iclass 27, count 0 2006.231.08:00:31.55#ibcon#read 6, iclass 27, count 0 2006.231.08:00:31.55#ibcon#end of sib2, iclass 27, count 0 2006.231.08:00:31.55#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:00:31.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:00:31.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:00:31.55#ibcon#*before write, iclass 27, count 0 2006.231.08:00:31.55#ibcon#enter sib2, iclass 27, count 0 2006.231.08:00:31.55#ibcon#flushed, iclass 27, count 0 2006.231.08:00:31.55#ibcon#about to write, iclass 27, count 0 2006.231.08:00:31.55#ibcon#wrote, iclass 27, count 0 2006.231.08:00:31.55#ibcon#about to read 3, iclass 27, count 0 2006.231.08:00:31.59#ibcon#read 3, iclass 27, count 0 2006.231.08:00:31.59#ibcon#about to read 4, iclass 27, count 0 2006.231.08:00:31.59#ibcon#read 4, iclass 27, count 0 2006.231.08:00:31.59#ibcon#about to read 5, iclass 27, count 0 2006.231.08:00:31.59#ibcon#read 5, iclass 27, count 0 2006.231.08:00:31.59#ibcon#about to read 6, iclass 27, count 0 2006.231.08:00:31.59#ibcon#read 6, iclass 27, count 0 2006.231.08:00:31.59#ibcon#end of sib2, iclass 27, count 0 2006.231.08:00:31.59#ibcon#*after write, iclass 27, count 0 2006.231.08:00:31.59#ibcon#*before return 0, iclass 27, count 0 2006.231.08:00:31.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:00:31.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:00:31.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:00:31.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:00:31.59$vc4f8/vb=4,4 2006.231.08:00:31.59#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.231.08:00:31.59#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.231.08:00:31.59#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:31.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:00:31.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:00:31.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:00:31.65#ibcon#enter wrdev, iclass 29, count 2 2006.231.08:00:31.65#ibcon#first serial, iclass 29, count 2 2006.231.08:00:31.65#ibcon#enter sib2, iclass 29, count 2 2006.231.08:00:31.65#ibcon#flushed, iclass 29, count 2 2006.231.08:00:31.65#ibcon#about to write, iclass 29, count 2 2006.231.08:00:31.65#ibcon#wrote, iclass 29, count 2 2006.231.08:00:31.65#ibcon#about to read 3, iclass 29, count 2 2006.231.08:00:31.67#ibcon#read 3, iclass 29, count 2 2006.231.08:00:31.67#ibcon#about to read 4, iclass 29, count 2 2006.231.08:00:31.67#ibcon#read 4, iclass 29, count 2 2006.231.08:00:31.67#ibcon#about to read 5, iclass 29, count 2 2006.231.08:00:31.67#ibcon#read 5, iclass 29, count 2 2006.231.08:00:31.67#ibcon#about to read 6, iclass 29, count 2 2006.231.08:00:31.67#ibcon#read 6, iclass 29, count 2 2006.231.08:00:31.67#ibcon#end of sib2, iclass 29, count 2 2006.231.08:00:31.67#ibcon#*mode == 0, iclass 29, count 2 2006.231.08:00:31.67#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.231.08:00:31.67#ibcon#[27=AT04-04\r\n] 2006.231.08:00:31.67#ibcon#*before write, iclass 29, count 2 2006.231.08:00:31.67#ibcon#enter sib2, iclass 29, count 2 2006.231.08:00:31.67#ibcon#flushed, iclass 29, count 2 2006.231.08:00:31.67#ibcon#about to write, iclass 29, count 2 2006.231.08:00:31.67#ibcon#wrote, iclass 29, count 2 2006.231.08:00:31.67#ibcon#about to read 3, iclass 29, count 2 2006.231.08:00:31.70#ibcon#read 3, iclass 29, count 2 2006.231.08:00:31.70#ibcon#about to read 4, iclass 29, count 2 2006.231.08:00:31.70#ibcon#read 4, iclass 29, count 2 2006.231.08:00:31.70#ibcon#about to read 5, iclass 29, count 2 2006.231.08:00:31.70#ibcon#read 5, iclass 29, count 2 2006.231.08:00:31.70#ibcon#about to read 6, iclass 29, count 2 2006.231.08:00:31.70#ibcon#read 6, iclass 29, count 2 2006.231.08:00:31.70#ibcon#end of sib2, iclass 29, count 2 2006.231.08:00:31.70#ibcon#*after write, iclass 29, count 2 2006.231.08:00:31.70#ibcon#*before return 0, iclass 29, count 2 2006.231.08:00:31.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:00:31.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:00:31.70#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.231.08:00:31.70#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:31.70#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:00:31.82#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:00:31.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:00:31.82#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:00:31.82#ibcon#first serial, iclass 29, count 0 2006.231.08:00:31.82#ibcon#enter sib2, iclass 29, count 0 2006.231.08:00:31.82#ibcon#flushed, iclass 29, count 0 2006.231.08:00:31.82#ibcon#about to write, iclass 29, count 0 2006.231.08:00:31.82#ibcon#wrote, iclass 29, count 0 2006.231.08:00:31.82#ibcon#about to read 3, iclass 29, count 0 2006.231.08:00:31.84#ibcon#read 3, iclass 29, count 0 2006.231.08:00:31.84#ibcon#about to read 4, iclass 29, count 0 2006.231.08:00:31.84#ibcon#read 4, iclass 29, count 0 2006.231.08:00:31.84#ibcon#about to read 5, iclass 29, count 0 2006.231.08:00:31.84#ibcon#read 5, iclass 29, count 0 2006.231.08:00:31.84#ibcon#about to read 6, iclass 29, count 0 2006.231.08:00:31.84#ibcon#read 6, iclass 29, count 0 2006.231.08:00:31.84#ibcon#end of sib2, iclass 29, count 0 2006.231.08:00:31.84#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:00:31.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:00:31.84#ibcon#[27=USB\r\n] 2006.231.08:00:31.84#ibcon#*before write, iclass 29, count 0 2006.231.08:00:31.84#ibcon#enter sib2, iclass 29, count 0 2006.231.08:00:31.84#ibcon#flushed, iclass 29, count 0 2006.231.08:00:31.84#ibcon#about to write, iclass 29, count 0 2006.231.08:00:31.84#ibcon#wrote, iclass 29, count 0 2006.231.08:00:31.84#ibcon#about to read 3, iclass 29, count 0 2006.231.08:00:31.87#ibcon#read 3, iclass 29, count 0 2006.231.08:00:31.87#ibcon#about to read 4, iclass 29, count 0 2006.231.08:00:31.87#ibcon#read 4, iclass 29, count 0 2006.231.08:00:31.87#ibcon#about to read 5, iclass 29, count 0 2006.231.08:00:31.87#ibcon#read 5, iclass 29, count 0 2006.231.08:00:31.87#ibcon#about to read 6, iclass 29, count 0 2006.231.08:00:31.87#ibcon#read 6, iclass 29, count 0 2006.231.08:00:31.87#ibcon#end of sib2, iclass 29, count 0 2006.231.08:00:31.87#ibcon#*after write, iclass 29, count 0 2006.231.08:00:31.87#ibcon#*before return 0, iclass 29, count 0 2006.231.08:00:31.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:00:31.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:00:31.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:00:31.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:00:31.87$vc4f8/vblo=5,744.99 2006.231.08:00:31.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.231.08:00:31.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.231.08:00:31.87#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:31.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:00:31.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:00:31.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:00:31.87#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:00:31.87#ibcon#first serial, iclass 31, count 0 2006.231.08:00:31.87#ibcon#enter sib2, iclass 31, count 0 2006.231.08:00:31.87#ibcon#flushed, iclass 31, count 0 2006.231.08:00:31.87#ibcon#about to write, iclass 31, count 0 2006.231.08:00:31.87#ibcon#wrote, iclass 31, count 0 2006.231.08:00:31.87#ibcon#about to read 3, iclass 31, count 0 2006.231.08:00:31.89#ibcon#read 3, iclass 31, count 0 2006.231.08:00:31.89#ibcon#about to read 4, iclass 31, count 0 2006.231.08:00:31.89#ibcon#read 4, iclass 31, count 0 2006.231.08:00:31.89#ibcon#about to read 5, iclass 31, count 0 2006.231.08:00:31.89#ibcon#read 5, iclass 31, count 0 2006.231.08:00:31.89#ibcon#about to read 6, iclass 31, count 0 2006.231.08:00:31.89#ibcon#read 6, iclass 31, count 0 2006.231.08:00:31.89#ibcon#end of sib2, iclass 31, count 0 2006.231.08:00:31.89#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:00:31.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:00:31.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:00:31.89#ibcon#*before write, iclass 31, count 0 2006.231.08:00:31.89#ibcon#enter sib2, iclass 31, count 0 2006.231.08:00:31.89#ibcon#flushed, iclass 31, count 0 2006.231.08:00:31.89#ibcon#about to write, iclass 31, count 0 2006.231.08:00:31.89#ibcon#wrote, iclass 31, count 0 2006.231.08:00:31.89#ibcon#about to read 3, iclass 31, count 0 2006.231.08:00:31.93#ibcon#read 3, iclass 31, count 0 2006.231.08:00:31.93#ibcon#about to read 4, iclass 31, count 0 2006.231.08:00:31.93#ibcon#read 4, iclass 31, count 0 2006.231.08:00:31.93#ibcon#about to read 5, iclass 31, count 0 2006.231.08:00:31.93#ibcon#read 5, iclass 31, count 0 2006.231.08:00:31.93#ibcon#about to read 6, iclass 31, count 0 2006.231.08:00:31.93#ibcon#read 6, iclass 31, count 0 2006.231.08:00:31.93#ibcon#end of sib2, iclass 31, count 0 2006.231.08:00:31.93#ibcon#*after write, iclass 31, count 0 2006.231.08:00:31.93#ibcon#*before return 0, iclass 31, count 0 2006.231.08:00:31.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:00:31.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:00:31.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:00:31.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:00:31.93$vc4f8/vb=5,3 2006.231.08:00:31.93#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.231.08:00:31.93#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.231.08:00:31.93#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:31.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:00:31.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:00:31.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:00:31.99#ibcon#enter wrdev, iclass 33, count 2 2006.231.08:00:31.99#ibcon#first serial, iclass 33, count 2 2006.231.08:00:31.99#ibcon#enter sib2, iclass 33, count 2 2006.231.08:00:31.99#ibcon#flushed, iclass 33, count 2 2006.231.08:00:31.99#ibcon#about to write, iclass 33, count 2 2006.231.08:00:31.99#ibcon#wrote, iclass 33, count 2 2006.231.08:00:31.99#ibcon#about to read 3, iclass 33, count 2 2006.231.08:00:32.01#ibcon#read 3, iclass 33, count 2 2006.231.08:00:32.01#ibcon#about to read 4, iclass 33, count 2 2006.231.08:00:32.01#ibcon#read 4, iclass 33, count 2 2006.231.08:00:32.01#ibcon#about to read 5, iclass 33, count 2 2006.231.08:00:32.01#ibcon#read 5, iclass 33, count 2 2006.231.08:00:32.01#ibcon#about to read 6, iclass 33, count 2 2006.231.08:00:32.01#ibcon#read 6, iclass 33, count 2 2006.231.08:00:32.01#ibcon#end of sib2, iclass 33, count 2 2006.231.08:00:32.01#ibcon#*mode == 0, iclass 33, count 2 2006.231.08:00:32.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.231.08:00:32.01#ibcon#[27=AT05-03\r\n] 2006.231.08:00:32.01#ibcon#*before write, iclass 33, count 2 2006.231.08:00:32.01#ibcon#enter sib2, iclass 33, count 2 2006.231.08:00:32.01#ibcon#flushed, iclass 33, count 2 2006.231.08:00:32.01#ibcon#about to write, iclass 33, count 2 2006.231.08:00:32.01#ibcon#wrote, iclass 33, count 2 2006.231.08:00:32.01#ibcon#about to read 3, iclass 33, count 2 2006.231.08:00:32.04#ibcon#read 3, iclass 33, count 2 2006.231.08:00:32.04#ibcon#about to read 4, iclass 33, count 2 2006.231.08:00:32.04#ibcon#read 4, iclass 33, count 2 2006.231.08:00:32.04#ibcon#about to read 5, iclass 33, count 2 2006.231.08:00:32.04#ibcon#read 5, iclass 33, count 2 2006.231.08:00:32.04#ibcon#about to read 6, iclass 33, count 2 2006.231.08:00:32.04#ibcon#read 6, iclass 33, count 2 2006.231.08:00:32.04#ibcon#end of sib2, iclass 33, count 2 2006.231.08:00:32.04#ibcon#*after write, iclass 33, count 2 2006.231.08:00:32.04#ibcon#*before return 0, iclass 33, count 2 2006.231.08:00:32.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:00:32.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:00:32.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.231.08:00:32.04#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:32.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:00:32.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:00:32.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:00:32.16#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:00:32.16#ibcon#first serial, iclass 33, count 0 2006.231.08:00:32.16#ibcon#enter sib2, iclass 33, count 0 2006.231.08:00:32.16#ibcon#flushed, iclass 33, count 0 2006.231.08:00:32.16#ibcon#about to write, iclass 33, count 0 2006.231.08:00:32.16#ibcon#wrote, iclass 33, count 0 2006.231.08:00:32.16#ibcon#about to read 3, iclass 33, count 0 2006.231.08:00:32.18#ibcon#read 3, iclass 33, count 0 2006.231.08:00:32.18#ibcon#about to read 4, iclass 33, count 0 2006.231.08:00:32.18#ibcon#read 4, iclass 33, count 0 2006.231.08:00:32.18#ibcon#about to read 5, iclass 33, count 0 2006.231.08:00:32.18#ibcon#read 5, iclass 33, count 0 2006.231.08:00:32.18#ibcon#about to read 6, iclass 33, count 0 2006.231.08:00:32.18#ibcon#read 6, iclass 33, count 0 2006.231.08:00:32.18#ibcon#end of sib2, iclass 33, count 0 2006.231.08:00:32.18#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:00:32.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:00:32.18#ibcon#[27=USB\r\n] 2006.231.08:00:32.18#ibcon#*before write, iclass 33, count 0 2006.231.08:00:32.18#ibcon#enter sib2, iclass 33, count 0 2006.231.08:00:32.18#ibcon#flushed, iclass 33, count 0 2006.231.08:00:32.18#ibcon#about to write, iclass 33, count 0 2006.231.08:00:32.18#ibcon#wrote, iclass 33, count 0 2006.231.08:00:32.18#ibcon#about to read 3, iclass 33, count 0 2006.231.08:00:32.21#ibcon#read 3, iclass 33, count 0 2006.231.08:00:32.21#ibcon#about to read 4, iclass 33, count 0 2006.231.08:00:32.21#ibcon#read 4, iclass 33, count 0 2006.231.08:00:32.21#ibcon#about to read 5, iclass 33, count 0 2006.231.08:00:32.21#ibcon#read 5, iclass 33, count 0 2006.231.08:00:32.21#ibcon#about to read 6, iclass 33, count 0 2006.231.08:00:32.21#ibcon#read 6, iclass 33, count 0 2006.231.08:00:32.21#ibcon#end of sib2, iclass 33, count 0 2006.231.08:00:32.21#ibcon#*after write, iclass 33, count 0 2006.231.08:00:32.21#ibcon#*before return 0, iclass 33, count 0 2006.231.08:00:32.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:00:32.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:00:32.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:00:32.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:00:32.21$vc4f8/vblo=6,752.99 2006.231.08:00:32.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.231.08:00:32.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.231.08:00:32.21#ibcon#ireg 17 cls_cnt 0 2006.231.08:00:32.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:00:32.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:00:32.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:00:32.21#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:00:32.21#ibcon#first serial, iclass 35, count 0 2006.231.08:00:32.21#ibcon#enter sib2, iclass 35, count 0 2006.231.08:00:32.21#ibcon#flushed, iclass 35, count 0 2006.231.08:00:32.21#ibcon#about to write, iclass 35, count 0 2006.231.08:00:32.21#ibcon#wrote, iclass 35, count 0 2006.231.08:00:32.21#ibcon#about to read 3, iclass 35, count 0 2006.231.08:00:32.23#ibcon#read 3, iclass 35, count 0 2006.231.08:00:32.23#ibcon#about to read 4, iclass 35, count 0 2006.231.08:00:32.23#ibcon#read 4, iclass 35, count 0 2006.231.08:00:32.23#ibcon#about to read 5, iclass 35, count 0 2006.231.08:00:32.23#ibcon#read 5, iclass 35, count 0 2006.231.08:00:32.23#ibcon#about to read 6, iclass 35, count 0 2006.231.08:00:32.23#ibcon#read 6, iclass 35, count 0 2006.231.08:00:32.23#ibcon#end of sib2, iclass 35, count 0 2006.231.08:00:32.23#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:00:32.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:00:32.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:00:32.23#ibcon#*before write, iclass 35, count 0 2006.231.08:00:32.23#ibcon#enter sib2, iclass 35, count 0 2006.231.08:00:32.23#ibcon#flushed, iclass 35, count 0 2006.231.08:00:32.23#ibcon#about to write, iclass 35, count 0 2006.231.08:00:32.23#ibcon#wrote, iclass 35, count 0 2006.231.08:00:32.23#ibcon#about to read 3, iclass 35, count 0 2006.231.08:00:32.27#ibcon#read 3, iclass 35, count 0 2006.231.08:00:32.27#ibcon#about to read 4, iclass 35, count 0 2006.231.08:00:32.27#ibcon#read 4, iclass 35, count 0 2006.231.08:00:32.27#ibcon#about to read 5, iclass 35, count 0 2006.231.08:00:32.27#ibcon#read 5, iclass 35, count 0 2006.231.08:00:32.27#ibcon#about to read 6, iclass 35, count 0 2006.231.08:00:32.27#ibcon#read 6, iclass 35, count 0 2006.231.08:00:32.27#ibcon#end of sib2, iclass 35, count 0 2006.231.08:00:32.27#ibcon#*after write, iclass 35, count 0 2006.231.08:00:32.27#ibcon#*before return 0, iclass 35, count 0 2006.231.08:00:32.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:00:32.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:00:32.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:00:32.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:00:32.27$vc4f8/vb=6,4 2006.231.08:00:32.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.231.08:00:32.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.231.08:00:32.27#ibcon#ireg 11 cls_cnt 2 2006.231.08:00:32.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:00:32.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:00:32.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:00:32.33#ibcon#enter wrdev, iclass 37, count 2 2006.231.08:00:32.33#ibcon#first serial, iclass 37, count 2 2006.231.08:00:32.33#ibcon#enter sib2, iclass 37, count 2 2006.231.08:00:32.33#ibcon#flushed, iclass 37, count 2 2006.231.08:00:32.33#ibcon#about to write, iclass 37, count 2 2006.231.08:00:32.33#ibcon#wrote, iclass 37, count 2 2006.231.08:00:32.33#ibcon#about to read 3, iclass 37, count 2 2006.231.08:00:32.35#ibcon#read 3, iclass 37, count 2 2006.231.08:00:32.35#ibcon#about to read 4, iclass 37, count 2 2006.231.08:00:32.35#ibcon#read 4, iclass 37, count 2 2006.231.08:00:32.35#ibcon#about to read 5, iclass 37, count 2 2006.231.08:00:32.35#ibcon#read 5, iclass 37, count 2 2006.231.08:00:32.35#ibcon#about to read 6, iclass 37, count 2 2006.231.08:00:32.35#ibcon#read 6, iclass 37, count 2 2006.231.08:00:32.35#ibcon#end of sib2, iclass 37, count 2 2006.231.08:00:32.35#ibcon#*mode == 0, iclass 37, count 2 2006.231.08:00:32.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.231.08:00:32.35#ibcon#[27=AT06-04\r\n] 2006.231.08:00:32.35#ibcon#*before write, iclass 37, count 2 2006.231.08:00:32.35#ibcon#enter sib2, iclass 37, count 2 2006.231.08:00:32.35#ibcon#flushed, iclass 37, count 2 2006.231.08:00:32.35#ibcon#about to write, iclass 37, count 2 2006.231.08:00:32.35#ibcon#wrote, iclass 37, count 2 2006.231.08:00:32.35#ibcon#about to read 3, iclass 37, count 2 2006.231.08:00:32.38#ibcon#read 3, iclass 37, count 2 2006.231.08:00:32.38#ibcon#about to read 4, iclass 37, count 2 2006.231.08:00:32.38#ibcon#read 4, iclass 37, count 2 2006.231.08:00:32.38#ibcon#about to read 5, iclass 37, count 2 2006.231.08:00:32.38#ibcon#read 5, iclass 37, count 2 2006.231.08:00:32.38#ibcon#about to read 6, iclass 37, count 2 2006.231.08:00:32.38#ibcon#read 6, iclass 37, count 2 2006.231.08:00:32.38#ibcon#end of sib2, iclass 37, count 2 2006.231.08:00:32.38#ibcon#*after write, iclass 37, count 2 2006.231.08:00:32.38#ibcon#*before return 0, iclass 37, count 2 2006.231.08:00:32.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:00:32.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:00:32.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.231.08:00:32.38#ibcon#ireg 7 cls_cnt 0 2006.231.08:00:32.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:00:32.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:00:32.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:00:32.50#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:00:32.50#ibcon#first serial, iclass 37, count 0 2006.231.08:00:32.50#ibcon#enter sib2, iclass 37, count 0 2006.231.08:00:32.50#ibcon#flushed, iclass 37, count 0 2006.231.08:00:32.50#ibcon#about to write, iclass 37, count 0 2006.231.08:00:32.50#ibcon#wrote, iclass 37, count 0 2006.231.08:00:32.50#ibcon#about to read 3, iclass 37, count 0 2006.231.08:00:32.52#ibcon#read 3, iclass 37, count 0 2006.231.08:00:32.52#ibcon#about to read 4, iclass 37, count 0 2006.231.08:00:32.52#ibcon#read 4, iclass 37, count 0 2006.231.08:00:32.52#ibcon#about to read 5, iclass 37, count 0 2006.231.08:00:32.52#ibcon#read 5, iclass 37, count 0 2006.231.08:00:32.52#ibcon#about to read 6, iclass 37, count 0 2006.231.08:00:32.52#ibcon#read 6, iclass 37, count 0 2006.231.08:00:32.52#ibcon#end of sib2, iclass 37, count 0 2006.231.08:00:32.52#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:00:32.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:00:32.52#ibcon#[27=USB\r\n] 2006.231.08:00:32.52#ibcon#*before write, iclass 37, count 0 2006.231.08:00:32.52#ibcon#enter sib2, iclass 37, count 0 2006.231.08:00:32.52#ibcon#flushed, iclass 37, count 0 2006.231.08:00:32.52#ibcon#about to write, iclass 37, count 0 2006.231.08:00:32.52#ibcon#wrote, iclass 37, count 0 2006.231.08:00:32.52#ibcon#about to read 3, iclass 37, count 0 2006.231.08:00:32.55#ibcon#read 3, iclass 37, count 0 2006.231.08:00:32.55#ibcon#about to read 4, iclass 37, count 0 2006.231.08:00:32.55#ibcon#read 4, iclass 37, count 0 2006.231.08:00:32.55#ibcon#about to read 5, iclass 37, count 0 2006.231.08:00:32.55#ibcon#read 5, iclass 37, count 0 2006.231.08:00:32.55#ibcon#about to read 6, iclass 37, count 0 2006.231.08:00:32.55#ibcon#read 6, iclass 37, count 0 2006.231.08:00:32.55#ibcon#end of sib2, iclass 37, count 0 2006.231.08:00:32.55#ibcon#*after write, iclass 37, count 0 2006.231.08:00:32.55#ibcon#*before return 0, iclass 37, count 0 2006.231.08:00:32.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:00:32.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:00:32.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:00:32.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:00:32.55$vc4f8/vabw=wide 2006.231.08:00:32.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.08:00:32.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.08:00:32.55#ibcon#ireg 8 cls_cnt 0 2006.231.08:00:32.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:00:32.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:00:32.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:00:32.55#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:00:32.55#ibcon#first serial, iclass 39, count 0 2006.231.08:00:32.55#ibcon#enter sib2, iclass 39, count 0 2006.231.08:00:32.55#ibcon#flushed, iclass 39, count 0 2006.231.08:00:32.55#ibcon#about to write, iclass 39, count 0 2006.231.08:00:32.55#ibcon#wrote, iclass 39, count 0 2006.231.08:00:32.55#ibcon#about to read 3, iclass 39, count 0 2006.231.08:00:32.57#ibcon#read 3, iclass 39, count 0 2006.231.08:00:32.57#ibcon#about to read 4, iclass 39, count 0 2006.231.08:00:32.57#ibcon#read 4, iclass 39, count 0 2006.231.08:00:32.57#ibcon#about to read 5, iclass 39, count 0 2006.231.08:00:32.57#ibcon#read 5, iclass 39, count 0 2006.231.08:00:32.57#ibcon#about to read 6, iclass 39, count 0 2006.231.08:00:32.57#ibcon#read 6, iclass 39, count 0 2006.231.08:00:32.57#ibcon#end of sib2, iclass 39, count 0 2006.231.08:00:32.57#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:00:32.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:00:32.57#ibcon#[25=BW32\r\n] 2006.231.08:00:32.57#ibcon#*before write, iclass 39, count 0 2006.231.08:00:32.57#ibcon#enter sib2, iclass 39, count 0 2006.231.08:00:32.57#ibcon#flushed, iclass 39, count 0 2006.231.08:00:32.57#ibcon#about to write, iclass 39, count 0 2006.231.08:00:32.57#ibcon#wrote, iclass 39, count 0 2006.231.08:00:32.57#ibcon#about to read 3, iclass 39, count 0 2006.231.08:00:32.60#ibcon#read 3, iclass 39, count 0 2006.231.08:00:32.60#ibcon#about to read 4, iclass 39, count 0 2006.231.08:00:32.60#ibcon#read 4, iclass 39, count 0 2006.231.08:00:32.60#ibcon#about to read 5, iclass 39, count 0 2006.231.08:00:32.60#ibcon#read 5, iclass 39, count 0 2006.231.08:00:32.60#ibcon#about to read 6, iclass 39, count 0 2006.231.08:00:32.60#ibcon#read 6, iclass 39, count 0 2006.231.08:00:32.60#ibcon#end of sib2, iclass 39, count 0 2006.231.08:00:32.60#ibcon#*after write, iclass 39, count 0 2006.231.08:00:32.60#ibcon#*before return 0, iclass 39, count 0 2006.231.08:00:32.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:00:32.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:00:32.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:00:32.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:00:32.60$vc4f8/vbbw=wide 2006.231.08:00:32.60#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.08:00:32.60#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.08:00:32.60#ibcon#ireg 8 cls_cnt 0 2006.231.08:00:32.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:00:32.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:00:32.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:00:32.67#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:00:32.67#ibcon#first serial, iclass 3, count 0 2006.231.08:00:32.67#ibcon#enter sib2, iclass 3, count 0 2006.231.08:00:32.67#ibcon#flushed, iclass 3, count 0 2006.231.08:00:32.67#ibcon#about to write, iclass 3, count 0 2006.231.08:00:32.67#ibcon#wrote, iclass 3, count 0 2006.231.08:00:32.67#ibcon#about to read 3, iclass 3, count 0 2006.231.08:00:32.69#ibcon#read 3, iclass 3, count 0 2006.231.08:00:32.69#ibcon#about to read 4, iclass 3, count 0 2006.231.08:00:32.69#ibcon#read 4, iclass 3, count 0 2006.231.08:00:32.69#ibcon#about to read 5, iclass 3, count 0 2006.231.08:00:32.69#ibcon#read 5, iclass 3, count 0 2006.231.08:00:32.69#ibcon#about to read 6, iclass 3, count 0 2006.231.08:00:32.69#ibcon#read 6, iclass 3, count 0 2006.231.08:00:32.69#ibcon#end of sib2, iclass 3, count 0 2006.231.08:00:32.69#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:00:32.69#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:00:32.69#ibcon#[27=BW32\r\n] 2006.231.08:00:32.69#ibcon#*before write, iclass 3, count 0 2006.231.08:00:32.69#ibcon#enter sib2, iclass 3, count 0 2006.231.08:00:32.69#ibcon#flushed, iclass 3, count 0 2006.231.08:00:32.69#ibcon#about to write, iclass 3, count 0 2006.231.08:00:32.69#ibcon#wrote, iclass 3, count 0 2006.231.08:00:32.69#ibcon#about to read 3, iclass 3, count 0 2006.231.08:00:32.72#ibcon#read 3, iclass 3, count 0 2006.231.08:00:32.72#ibcon#about to read 4, iclass 3, count 0 2006.231.08:00:32.72#ibcon#read 4, iclass 3, count 0 2006.231.08:00:32.72#ibcon#about to read 5, iclass 3, count 0 2006.231.08:00:32.72#ibcon#read 5, iclass 3, count 0 2006.231.08:00:32.72#ibcon#about to read 6, iclass 3, count 0 2006.231.08:00:32.72#ibcon#read 6, iclass 3, count 0 2006.231.08:00:32.72#ibcon#end of sib2, iclass 3, count 0 2006.231.08:00:32.72#ibcon#*after write, iclass 3, count 0 2006.231.08:00:32.72#ibcon#*before return 0, iclass 3, count 0 2006.231.08:00:32.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:00:32.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:00:32.72#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:00:32.72#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:00:32.72$4f8m12a/ifd4f 2006.231.08:00:32.72$ifd4f/lo= 2006.231.08:00:32.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:00:32.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:00:32.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:00:32.72$ifd4f/patch= 2006.231.08:00:32.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:00:32.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:00:32.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:00:32.72$4f8m12a/"form=m,16.000,1:2 2006.231.08:00:32.72$4f8m12a/"tpicd 2006.231.08:00:32.72$4f8m12a/echo=off 2006.231.08:00:32.72$4f8m12a/xlog=off 2006.231.08:00:32.72:!2006.231.08:01:00 2006.231.08:00:43.13#trakl#Source acquired 2006.231.08:00:45.13#flagr#flagr/antenna,acquired 2006.231.08:01:00.00:preob 2006.231.08:01:01.13/onsource/TRACKING 2006.231.08:01:01.13:!2006.231.08:01:10 2006.231.08:01:10.00:data_valid=on 2006.231.08:01:10.00:midob 2006.231.08:01:10.13/onsource/TRACKING 2006.231.08:01:10.13/wx/30.53,1004.5,86 2006.231.08:01:10.34/cable/+6.3719E-03 2006.231.08:01:11.43/va/01,08,usb,yes,37,39 2006.231.08:01:11.43/va/02,07,usb,yes,37,39 2006.231.08:01:11.43/va/03,08,usb,yes,28,28 2006.231.08:01:11.43/va/04,07,usb,yes,39,42 2006.231.08:01:11.43/va/05,07,usb,yes,43,45 2006.231.08:01:11.43/va/06,06,usb,yes,42,42 2006.231.08:01:11.43/va/07,06,usb,yes,43,43 2006.231.08:01:11.43/va/08,06,usb,yes,45,45 2006.231.08:01:11.66/valo/01,532.99,yes,locked 2006.231.08:01:11.66/valo/02,572.99,yes,locked 2006.231.08:01:11.66/valo/03,672.99,yes,locked 2006.231.08:01:11.66/valo/04,832.99,yes,locked 2006.231.08:01:11.66/valo/05,652.99,yes,locked 2006.231.08:01:11.66/valo/06,772.99,yes,locked 2006.231.08:01:11.66/valo/07,832.99,yes,locked 2006.231.08:01:11.66/valo/08,852.99,yes,locked 2006.231.08:01:12.75/vb/01,04,usb,yes,40,97 2006.231.08:01:12.75/vb/02,04,usb,yes,34,93 2006.231.08:01:12.75/vb/03,04,usb,yes,31,52 2006.231.08:01:12.75/vb/04,04,usb,yes,32,32 2006.231.08:01:12.75/vb/05,03,usb,yes,39,44 2006.231.08:01:12.75/vb/06,04,usb,yes,32,35 2006.231.08:01:12.75/vb/07,04,usb,yes,34,34 2006.231.08:01:12.75/vb/08,04,usb,yes,31,35 2006.231.08:01:12.98/vblo/01,632.99,yes,locked 2006.231.08:01:12.98/vblo/02,640.99,yes,locked 2006.231.08:01:12.98/vblo/03,656.99,yes,locked 2006.231.08:01:12.98/vblo/04,712.99,yes,locked 2006.231.08:01:12.98/vblo/05,744.99,yes,locked 2006.231.08:01:12.98/vblo/06,752.99,yes,locked 2006.231.08:01:12.98/vblo/07,734.99,yes,locked 2006.231.08:01:12.98/vblo/08,744.99,yes,locked 2006.231.08:01:13.13/vabw/8 2006.231.08:01:13.28/vbbw/8 2006.231.08:01:13.37/xfe/off,on,12.5 2006.231.08:01:13.75/ifatt/23,28,28,28 2006.231.08:01:14.08/fmout-gps/S +4.47E-07 2006.231.08:01:14.12:!2006.231.08:02:10 2006.231.08:02:10.02:data_valid=off 2006.231.08:02:10.02:postob 2006.231.08:02:10.15/cable/+6.3709E-03 2006.231.08:02:10.15/wx/30.53,1004.5,85 2006.231.08:02:11.08/fmout-gps/S +4.45E-07 2006.231.08:02:11.08:scan_name=231-0803,k06231,60 2006.231.08:02:11.08:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.231.08:02:11.13#flagr#flagr/antenna,new-source 2006.231.08:02:12.15:checkk5 2006.231.08:02:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:02:12.89/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:02:13.27/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:02:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:02:14.00/chk_obsdata//k5ts1/T2310801??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:02:14.37/chk_obsdata//k5ts2/T2310801??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:02:14.74/chk_obsdata//k5ts3/T2310801??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:02:15.10/chk_obsdata//k5ts4/T2310801??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:02:15.79/k5log//k5ts1_log_newline 2006.231.08:02:16.48/k5log//k5ts2_log_newline 2006.231.08:02:17.17/k5log//k5ts3_log_newline 2006.231.08:02:17.85/k5log//k5ts4_log_newline 2006.231.08:02:17.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:02:17.87:4f8m12a=2 2006.231.08:02:17.87$4f8m12a/echo=on 2006.231.08:02:17.87$4f8m12a/pcalon 2006.231.08:02:17.87$pcalon/"no phase cal control is implemented here 2006.231.08:02:17.87$4f8m12a/"tpicd=stop 2006.231.08:02:17.87$4f8m12a/vc4f8 2006.231.08:02:17.87$vc4f8/valo=1,532.99 2006.231.08:02:17.88#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.08:02:17.88#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.08:02:17.88#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:17.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:02:17.88#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:02:17.88#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:02:17.88#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:02:17.88#ibcon#first serial, iclass 12, count 0 2006.231.08:02:17.88#ibcon#enter sib2, iclass 12, count 0 2006.231.08:02:17.88#ibcon#flushed, iclass 12, count 0 2006.231.08:02:17.88#ibcon#about to write, iclass 12, count 0 2006.231.08:02:17.88#ibcon#wrote, iclass 12, count 0 2006.231.08:02:17.88#ibcon#about to read 3, iclass 12, count 0 2006.231.08:02:17.92#ibcon#read 3, iclass 12, count 0 2006.231.08:02:17.92#ibcon#about to read 4, iclass 12, count 0 2006.231.08:02:17.92#ibcon#read 4, iclass 12, count 0 2006.231.08:02:17.92#ibcon#about to read 5, iclass 12, count 0 2006.231.08:02:17.92#ibcon#read 5, iclass 12, count 0 2006.231.08:02:17.92#ibcon#about to read 6, iclass 12, count 0 2006.231.08:02:17.92#ibcon#read 6, iclass 12, count 0 2006.231.08:02:17.92#ibcon#end of sib2, iclass 12, count 0 2006.231.08:02:17.92#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:02:17.92#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:02:17.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:02:17.92#ibcon#*before write, iclass 12, count 0 2006.231.08:02:17.92#ibcon#enter sib2, iclass 12, count 0 2006.231.08:02:17.92#ibcon#flushed, iclass 12, count 0 2006.231.08:02:17.92#ibcon#about to write, iclass 12, count 0 2006.231.08:02:17.92#ibcon#wrote, iclass 12, count 0 2006.231.08:02:17.92#ibcon#about to read 3, iclass 12, count 0 2006.231.08:02:17.96#ibcon#read 3, iclass 12, count 0 2006.231.08:02:17.96#ibcon#about to read 4, iclass 12, count 0 2006.231.08:02:17.96#ibcon#read 4, iclass 12, count 0 2006.231.08:02:17.96#ibcon#about to read 5, iclass 12, count 0 2006.231.08:02:17.96#ibcon#read 5, iclass 12, count 0 2006.231.08:02:17.96#ibcon#about to read 6, iclass 12, count 0 2006.231.08:02:17.96#ibcon#read 6, iclass 12, count 0 2006.231.08:02:17.96#ibcon#end of sib2, iclass 12, count 0 2006.231.08:02:17.97#ibcon#*after write, iclass 12, count 0 2006.231.08:02:17.97#ibcon#*before return 0, iclass 12, count 0 2006.231.08:02:17.97#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:02:17.97#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:02:17.97#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:02:17.97#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:02:17.97$vc4f8/va=1,8 2006.231.08:02:17.97#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.08:02:17.97#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.08:02:17.97#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:17.97#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:02:17.97#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:02:17.97#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:02:17.97#ibcon#enter wrdev, iclass 14, count 2 2006.231.08:02:17.97#ibcon#first serial, iclass 14, count 2 2006.231.08:02:17.97#ibcon#enter sib2, iclass 14, count 2 2006.231.08:02:17.97#ibcon#flushed, iclass 14, count 2 2006.231.08:02:17.97#ibcon#about to write, iclass 14, count 2 2006.231.08:02:17.97#ibcon#wrote, iclass 14, count 2 2006.231.08:02:17.97#ibcon#about to read 3, iclass 14, count 2 2006.231.08:02:17.98#ibcon#read 3, iclass 14, count 2 2006.231.08:02:17.98#ibcon#about to read 4, iclass 14, count 2 2006.231.08:02:17.98#ibcon#read 4, iclass 14, count 2 2006.231.08:02:17.98#ibcon#about to read 5, iclass 14, count 2 2006.231.08:02:17.98#ibcon#read 5, iclass 14, count 2 2006.231.08:02:17.98#ibcon#about to read 6, iclass 14, count 2 2006.231.08:02:17.98#ibcon#read 6, iclass 14, count 2 2006.231.08:02:17.98#ibcon#end of sib2, iclass 14, count 2 2006.231.08:02:17.99#ibcon#*mode == 0, iclass 14, count 2 2006.231.08:02:17.99#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.08:02:17.99#ibcon#[25=AT01-08\r\n] 2006.231.08:02:17.99#ibcon#*before write, iclass 14, count 2 2006.231.08:02:17.99#ibcon#enter sib2, iclass 14, count 2 2006.231.08:02:17.99#ibcon#flushed, iclass 14, count 2 2006.231.08:02:17.99#ibcon#about to write, iclass 14, count 2 2006.231.08:02:17.99#ibcon#wrote, iclass 14, count 2 2006.231.08:02:17.99#ibcon#about to read 3, iclass 14, count 2 2006.231.08:02:18.02#ibcon#read 3, iclass 14, count 2 2006.231.08:02:18.02#ibcon#about to read 4, iclass 14, count 2 2006.231.08:02:18.02#ibcon#read 4, iclass 14, count 2 2006.231.08:02:18.02#ibcon#about to read 5, iclass 14, count 2 2006.231.08:02:18.02#ibcon#read 5, iclass 14, count 2 2006.231.08:02:18.02#ibcon#about to read 6, iclass 14, count 2 2006.231.08:02:18.02#ibcon#read 6, iclass 14, count 2 2006.231.08:02:18.02#ibcon#end of sib2, iclass 14, count 2 2006.231.08:02:18.02#ibcon#*after write, iclass 14, count 2 2006.231.08:02:18.02#ibcon#*before return 0, iclass 14, count 2 2006.231.08:02:18.02#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:02:18.02#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:02:18.02#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.08:02:18.02#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:18.02#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:02:18.13#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:02:18.13#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:02:18.13#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:02:18.13#ibcon#first serial, iclass 14, count 0 2006.231.08:02:18.13#ibcon#enter sib2, iclass 14, count 0 2006.231.08:02:18.13#ibcon#flushed, iclass 14, count 0 2006.231.08:02:18.13#ibcon#about to write, iclass 14, count 0 2006.231.08:02:18.13#ibcon#wrote, iclass 14, count 0 2006.231.08:02:18.13#ibcon#about to read 3, iclass 14, count 0 2006.231.08:02:18.15#ibcon#read 3, iclass 14, count 0 2006.231.08:02:18.15#ibcon#about to read 4, iclass 14, count 0 2006.231.08:02:18.15#ibcon#read 4, iclass 14, count 0 2006.231.08:02:18.15#ibcon#about to read 5, iclass 14, count 0 2006.231.08:02:18.15#ibcon#read 5, iclass 14, count 0 2006.231.08:02:18.15#ibcon#about to read 6, iclass 14, count 0 2006.231.08:02:18.15#ibcon#read 6, iclass 14, count 0 2006.231.08:02:18.15#ibcon#end of sib2, iclass 14, count 0 2006.231.08:02:18.15#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:02:18.15#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:02:18.16#ibcon#[25=USB\r\n] 2006.231.08:02:18.16#ibcon#*before write, iclass 14, count 0 2006.231.08:02:18.16#ibcon#enter sib2, iclass 14, count 0 2006.231.08:02:18.16#ibcon#flushed, iclass 14, count 0 2006.231.08:02:18.16#ibcon#about to write, iclass 14, count 0 2006.231.08:02:18.16#ibcon#wrote, iclass 14, count 0 2006.231.08:02:18.16#ibcon#about to read 3, iclass 14, count 0 2006.231.08:02:18.19#ibcon#read 3, iclass 14, count 0 2006.231.08:02:18.19#ibcon#about to read 4, iclass 14, count 0 2006.231.08:02:18.19#ibcon#read 4, iclass 14, count 0 2006.231.08:02:18.19#ibcon#about to read 5, iclass 14, count 0 2006.231.08:02:18.19#ibcon#read 5, iclass 14, count 0 2006.231.08:02:18.19#ibcon#about to read 6, iclass 14, count 0 2006.231.08:02:18.19#ibcon#read 6, iclass 14, count 0 2006.231.08:02:18.19#ibcon#end of sib2, iclass 14, count 0 2006.231.08:02:18.19#ibcon#*after write, iclass 14, count 0 2006.231.08:02:18.19#ibcon#*before return 0, iclass 14, count 0 2006.231.08:02:18.19#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:02:18.19#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:02:18.19#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:02:18.19#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:02:18.19$vc4f8/valo=2,572.99 2006.231.08:02:18.19#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.08:02:18.19#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.08:02:18.19#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:18.19#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:02:18.19#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:02:18.19#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:02:18.19#ibcon#enter wrdev, iclass 16, count 0 2006.231.08:02:18.19#ibcon#first serial, iclass 16, count 0 2006.231.08:02:18.19#ibcon#enter sib2, iclass 16, count 0 2006.231.08:02:18.19#ibcon#flushed, iclass 16, count 0 2006.231.08:02:18.19#ibcon#about to write, iclass 16, count 0 2006.231.08:02:18.19#ibcon#wrote, iclass 16, count 0 2006.231.08:02:18.19#ibcon#about to read 3, iclass 16, count 0 2006.231.08:02:18.21#ibcon#read 3, iclass 16, count 0 2006.231.08:02:18.21#ibcon#about to read 4, iclass 16, count 0 2006.231.08:02:18.21#ibcon#read 4, iclass 16, count 0 2006.231.08:02:18.21#ibcon#about to read 5, iclass 16, count 0 2006.231.08:02:18.21#ibcon#read 5, iclass 16, count 0 2006.231.08:02:18.21#ibcon#about to read 6, iclass 16, count 0 2006.231.08:02:18.21#ibcon#read 6, iclass 16, count 0 2006.231.08:02:18.21#ibcon#end of sib2, iclass 16, count 0 2006.231.08:02:18.21#ibcon#*mode == 0, iclass 16, count 0 2006.231.08:02:18.21#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.08:02:18.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:02:18.21#ibcon#*before write, iclass 16, count 0 2006.231.08:02:18.21#ibcon#enter sib2, iclass 16, count 0 2006.231.08:02:18.21#ibcon#flushed, iclass 16, count 0 2006.231.08:02:18.21#ibcon#about to write, iclass 16, count 0 2006.231.08:02:18.21#ibcon#wrote, iclass 16, count 0 2006.231.08:02:18.21#ibcon#about to read 3, iclass 16, count 0 2006.231.08:02:18.24#ibcon#read 3, iclass 16, count 0 2006.231.08:02:18.24#ibcon#about to read 4, iclass 16, count 0 2006.231.08:02:18.24#ibcon#read 4, iclass 16, count 0 2006.231.08:02:18.24#ibcon#about to read 5, iclass 16, count 0 2006.231.08:02:18.24#ibcon#read 5, iclass 16, count 0 2006.231.08:02:18.24#ibcon#about to read 6, iclass 16, count 0 2006.231.08:02:18.24#ibcon#read 6, iclass 16, count 0 2006.231.08:02:18.24#ibcon#end of sib2, iclass 16, count 0 2006.231.08:02:18.24#ibcon#*after write, iclass 16, count 0 2006.231.08:02:18.25#ibcon#*before return 0, iclass 16, count 0 2006.231.08:02:18.25#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:02:18.25#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:02:18.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.08:02:18.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.08:02:18.25$vc4f8/va=2,7 2006.231.08:02:18.25#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.231.08:02:18.25#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.231.08:02:18.25#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:18.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:02:18.31#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:02:18.31#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:02:18.31#ibcon#enter wrdev, iclass 18, count 2 2006.231.08:02:18.31#ibcon#first serial, iclass 18, count 2 2006.231.08:02:18.31#ibcon#enter sib2, iclass 18, count 2 2006.231.08:02:18.31#ibcon#flushed, iclass 18, count 2 2006.231.08:02:18.31#ibcon#about to write, iclass 18, count 2 2006.231.08:02:18.31#ibcon#wrote, iclass 18, count 2 2006.231.08:02:18.31#ibcon#about to read 3, iclass 18, count 2 2006.231.08:02:18.32#ibcon#read 3, iclass 18, count 2 2006.231.08:02:18.32#ibcon#about to read 4, iclass 18, count 2 2006.231.08:02:18.32#ibcon#read 4, iclass 18, count 2 2006.231.08:02:18.32#ibcon#about to read 5, iclass 18, count 2 2006.231.08:02:18.32#ibcon#read 5, iclass 18, count 2 2006.231.08:02:18.32#ibcon#about to read 6, iclass 18, count 2 2006.231.08:02:18.32#ibcon#read 6, iclass 18, count 2 2006.231.08:02:18.33#ibcon#end of sib2, iclass 18, count 2 2006.231.08:02:18.33#ibcon#*mode == 0, iclass 18, count 2 2006.231.08:02:18.33#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.231.08:02:18.33#ibcon#[25=AT02-07\r\n] 2006.231.08:02:18.33#ibcon#*before write, iclass 18, count 2 2006.231.08:02:18.33#ibcon#enter sib2, iclass 18, count 2 2006.231.08:02:18.33#ibcon#flushed, iclass 18, count 2 2006.231.08:02:18.33#ibcon#about to write, iclass 18, count 2 2006.231.08:02:18.33#ibcon#wrote, iclass 18, count 2 2006.231.08:02:18.33#ibcon#about to read 3, iclass 18, count 2 2006.231.08:02:18.35#ibcon#read 3, iclass 18, count 2 2006.231.08:02:18.35#ibcon#about to read 4, iclass 18, count 2 2006.231.08:02:18.35#ibcon#read 4, iclass 18, count 2 2006.231.08:02:18.35#ibcon#about to read 5, iclass 18, count 2 2006.231.08:02:18.35#ibcon#read 5, iclass 18, count 2 2006.231.08:02:18.35#ibcon#about to read 6, iclass 18, count 2 2006.231.08:02:18.35#ibcon#read 6, iclass 18, count 2 2006.231.08:02:18.36#ibcon#end of sib2, iclass 18, count 2 2006.231.08:02:18.36#ibcon#*after write, iclass 18, count 2 2006.231.08:02:18.36#ibcon#*before return 0, iclass 18, count 2 2006.231.08:02:18.36#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:02:18.36#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:02:18.36#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.231.08:02:18.36#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:18.36#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:02:18.47#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:02:18.47#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:02:18.47#ibcon#enter wrdev, iclass 18, count 0 2006.231.08:02:18.47#ibcon#first serial, iclass 18, count 0 2006.231.08:02:18.47#ibcon#enter sib2, iclass 18, count 0 2006.231.08:02:18.47#ibcon#flushed, iclass 18, count 0 2006.231.08:02:18.47#ibcon#about to write, iclass 18, count 0 2006.231.08:02:18.47#ibcon#wrote, iclass 18, count 0 2006.231.08:02:18.47#ibcon#about to read 3, iclass 18, count 0 2006.231.08:02:18.49#ibcon#read 3, iclass 18, count 0 2006.231.08:02:18.49#ibcon#about to read 4, iclass 18, count 0 2006.231.08:02:18.49#ibcon#read 4, iclass 18, count 0 2006.231.08:02:18.49#ibcon#about to read 5, iclass 18, count 0 2006.231.08:02:18.49#ibcon#read 5, iclass 18, count 0 2006.231.08:02:18.49#ibcon#about to read 6, iclass 18, count 0 2006.231.08:02:18.49#ibcon#read 6, iclass 18, count 0 2006.231.08:02:18.49#ibcon#end of sib2, iclass 18, count 0 2006.231.08:02:18.49#ibcon#*mode == 0, iclass 18, count 0 2006.231.08:02:18.49#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.08:02:18.50#ibcon#[25=USB\r\n] 2006.231.08:02:18.50#ibcon#*before write, iclass 18, count 0 2006.231.08:02:18.50#ibcon#enter sib2, iclass 18, count 0 2006.231.08:02:18.50#ibcon#flushed, iclass 18, count 0 2006.231.08:02:18.50#ibcon#about to write, iclass 18, count 0 2006.231.08:02:18.50#ibcon#wrote, iclass 18, count 0 2006.231.08:02:18.50#ibcon#about to read 3, iclass 18, count 0 2006.231.08:02:18.53#ibcon#read 3, iclass 18, count 0 2006.231.08:02:18.53#ibcon#about to read 4, iclass 18, count 0 2006.231.08:02:18.53#ibcon#read 4, iclass 18, count 0 2006.231.08:02:18.53#ibcon#about to read 5, iclass 18, count 0 2006.231.08:02:18.53#ibcon#read 5, iclass 18, count 0 2006.231.08:02:18.53#ibcon#about to read 6, iclass 18, count 0 2006.231.08:02:18.53#ibcon#read 6, iclass 18, count 0 2006.231.08:02:18.53#ibcon#end of sib2, iclass 18, count 0 2006.231.08:02:18.53#ibcon#*after write, iclass 18, count 0 2006.231.08:02:18.53#ibcon#*before return 0, iclass 18, count 0 2006.231.08:02:18.53#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:02:18.53#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:02:18.53#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.08:02:18.53#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.08:02:18.53$vc4f8/valo=3,672.99 2006.231.08:02:18.53#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.231.08:02:18.53#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.231.08:02:18.53#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:18.53#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:02:18.53#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:02:18.53#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:02:18.53#ibcon#enter wrdev, iclass 20, count 0 2006.231.08:02:18.53#ibcon#first serial, iclass 20, count 0 2006.231.08:02:18.53#ibcon#enter sib2, iclass 20, count 0 2006.231.08:02:18.53#ibcon#flushed, iclass 20, count 0 2006.231.08:02:18.53#ibcon#about to write, iclass 20, count 0 2006.231.08:02:18.53#ibcon#wrote, iclass 20, count 0 2006.231.08:02:18.53#ibcon#about to read 3, iclass 20, count 0 2006.231.08:02:18.55#ibcon#read 3, iclass 20, count 0 2006.231.08:02:18.55#ibcon#about to read 4, iclass 20, count 0 2006.231.08:02:18.55#ibcon#read 4, iclass 20, count 0 2006.231.08:02:18.55#ibcon#about to read 5, iclass 20, count 0 2006.231.08:02:18.55#ibcon#read 5, iclass 20, count 0 2006.231.08:02:18.55#ibcon#about to read 6, iclass 20, count 0 2006.231.08:02:18.55#ibcon#read 6, iclass 20, count 0 2006.231.08:02:18.55#ibcon#end of sib2, iclass 20, count 0 2006.231.08:02:18.55#ibcon#*mode == 0, iclass 20, count 0 2006.231.08:02:18.55#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.08:02:18.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:02:18.55#ibcon#*before write, iclass 20, count 0 2006.231.08:02:18.55#ibcon#enter sib2, iclass 20, count 0 2006.231.08:02:18.55#ibcon#flushed, iclass 20, count 0 2006.231.08:02:18.55#ibcon#about to write, iclass 20, count 0 2006.231.08:02:18.55#ibcon#wrote, iclass 20, count 0 2006.231.08:02:18.55#ibcon#about to read 3, iclass 20, count 0 2006.231.08:02:18.58#ibcon#read 3, iclass 20, count 0 2006.231.08:02:18.58#ibcon#about to read 4, iclass 20, count 0 2006.231.08:02:18.58#ibcon#read 4, iclass 20, count 0 2006.231.08:02:18.58#ibcon#about to read 5, iclass 20, count 0 2006.231.08:02:18.59#ibcon#read 5, iclass 20, count 0 2006.231.08:02:18.59#ibcon#about to read 6, iclass 20, count 0 2006.231.08:02:18.59#ibcon#read 6, iclass 20, count 0 2006.231.08:02:18.59#ibcon#end of sib2, iclass 20, count 0 2006.231.08:02:18.59#ibcon#*after write, iclass 20, count 0 2006.231.08:02:18.59#ibcon#*before return 0, iclass 20, count 0 2006.231.08:02:18.59#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:02:18.59#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:02:18.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.08:02:18.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.08:02:18.59$vc4f8/va=3,8 2006.231.08:02:18.59#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.231.08:02:18.59#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.231.08:02:18.59#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:18.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:02:18.65#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:02:18.65#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:02:18.65#ibcon#enter wrdev, iclass 22, count 2 2006.231.08:02:18.65#ibcon#first serial, iclass 22, count 2 2006.231.08:02:18.65#ibcon#enter sib2, iclass 22, count 2 2006.231.08:02:18.65#ibcon#flushed, iclass 22, count 2 2006.231.08:02:18.65#ibcon#about to write, iclass 22, count 2 2006.231.08:02:18.65#ibcon#wrote, iclass 22, count 2 2006.231.08:02:18.65#ibcon#about to read 3, iclass 22, count 2 2006.231.08:02:18.67#ibcon#read 3, iclass 22, count 2 2006.231.08:02:18.67#ibcon#about to read 4, iclass 22, count 2 2006.231.08:02:18.67#ibcon#read 4, iclass 22, count 2 2006.231.08:02:18.67#ibcon#about to read 5, iclass 22, count 2 2006.231.08:02:18.67#ibcon#read 5, iclass 22, count 2 2006.231.08:02:18.67#ibcon#about to read 6, iclass 22, count 2 2006.231.08:02:18.67#ibcon#read 6, iclass 22, count 2 2006.231.08:02:18.67#ibcon#end of sib2, iclass 22, count 2 2006.231.08:02:18.67#ibcon#*mode == 0, iclass 22, count 2 2006.231.08:02:18.67#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.231.08:02:18.67#ibcon#[25=AT03-08\r\n] 2006.231.08:02:18.67#ibcon#*before write, iclass 22, count 2 2006.231.08:02:18.67#ibcon#enter sib2, iclass 22, count 2 2006.231.08:02:18.67#ibcon#flushed, iclass 22, count 2 2006.231.08:02:18.67#ibcon#about to write, iclass 22, count 2 2006.231.08:02:18.67#ibcon#wrote, iclass 22, count 2 2006.231.08:02:18.67#ibcon#about to read 3, iclass 22, count 2 2006.231.08:02:18.69#ibcon#read 3, iclass 22, count 2 2006.231.08:02:18.69#ibcon#about to read 4, iclass 22, count 2 2006.231.08:02:18.69#ibcon#read 4, iclass 22, count 2 2006.231.08:02:18.69#ibcon#about to read 5, iclass 22, count 2 2006.231.08:02:18.69#ibcon#read 5, iclass 22, count 2 2006.231.08:02:18.69#ibcon#about to read 6, iclass 22, count 2 2006.231.08:02:18.69#ibcon#read 6, iclass 22, count 2 2006.231.08:02:18.69#ibcon#end of sib2, iclass 22, count 2 2006.231.08:02:18.69#ibcon#*after write, iclass 22, count 2 2006.231.08:02:18.69#ibcon#*before return 0, iclass 22, count 2 2006.231.08:02:18.70#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:02:18.70#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:02:18.70#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.231.08:02:18.70#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:18.70#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:02:18.81#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:02:18.81#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:02:18.81#ibcon#enter wrdev, iclass 22, count 0 2006.231.08:02:18.81#ibcon#first serial, iclass 22, count 0 2006.231.08:02:18.81#ibcon#enter sib2, iclass 22, count 0 2006.231.08:02:18.81#ibcon#flushed, iclass 22, count 0 2006.231.08:02:18.81#ibcon#about to write, iclass 22, count 0 2006.231.08:02:18.81#ibcon#wrote, iclass 22, count 0 2006.231.08:02:18.81#ibcon#about to read 3, iclass 22, count 0 2006.231.08:02:18.83#ibcon#read 3, iclass 22, count 0 2006.231.08:02:18.83#ibcon#about to read 4, iclass 22, count 0 2006.231.08:02:18.83#ibcon#read 4, iclass 22, count 0 2006.231.08:02:18.83#ibcon#about to read 5, iclass 22, count 0 2006.231.08:02:18.83#ibcon#read 5, iclass 22, count 0 2006.231.08:02:18.83#ibcon#about to read 6, iclass 22, count 0 2006.231.08:02:18.83#ibcon#read 6, iclass 22, count 0 2006.231.08:02:18.83#ibcon#end of sib2, iclass 22, count 0 2006.231.08:02:18.83#ibcon#*mode == 0, iclass 22, count 0 2006.231.08:02:18.83#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.08:02:18.84#ibcon#[25=USB\r\n] 2006.231.08:02:18.84#ibcon#*before write, iclass 22, count 0 2006.231.08:02:18.84#ibcon#enter sib2, iclass 22, count 0 2006.231.08:02:18.84#ibcon#flushed, iclass 22, count 0 2006.231.08:02:18.84#ibcon#about to write, iclass 22, count 0 2006.231.08:02:18.84#ibcon#wrote, iclass 22, count 0 2006.231.08:02:18.84#ibcon#about to read 3, iclass 22, count 0 2006.231.08:02:18.86#ibcon#read 3, iclass 22, count 0 2006.231.08:02:18.86#ibcon#about to read 4, iclass 22, count 0 2006.231.08:02:18.86#ibcon#read 4, iclass 22, count 0 2006.231.08:02:18.86#ibcon#about to read 5, iclass 22, count 0 2006.231.08:02:18.86#ibcon#read 5, iclass 22, count 0 2006.231.08:02:18.86#ibcon#about to read 6, iclass 22, count 0 2006.231.08:02:18.86#ibcon#read 6, iclass 22, count 0 2006.231.08:02:18.86#ibcon#end of sib2, iclass 22, count 0 2006.231.08:02:18.86#ibcon#*after write, iclass 22, count 0 2006.231.08:02:18.86#ibcon#*before return 0, iclass 22, count 0 2006.231.08:02:18.87#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:02:18.87#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:02:18.87#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.08:02:18.87#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.08:02:18.87$vc4f8/valo=4,832.99 2006.231.08:02:18.87#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.231.08:02:18.87#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.231.08:02:18.87#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:18.87#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:02:18.87#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:02:18.87#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:02:18.87#ibcon#enter wrdev, iclass 24, count 0 2006.231.08:02:18.87#ibcon#first serial, iclass 24, count 0 2006.231.08:02:18.87#ibcon#enter sib2, iclass 24, count 0 2006.231.08:02:18.87#ibcon#flushed, iclass 24, count 0 2006.231.08:02:18.87#ibcon#about to write, iclass 24, count 0 2006.231.08:02:18.87#ibcon#wrote, iclass 24, count 0 2006.231.08:02:18.87#ibcon#about to read 3, iclass 24, count 0 2006.231.08:02:18.88#ibcon#read 3, iclass 24, count 0 2006.231.08:02:18.88#ibcon#about to read 4, iclass 24, count 0 2006.231.08:02:18.88#ibcon#read 4, iclass 24, count 0 2006.231.08:02:18.88#ibcon#about to read 5, iclass 24, count 0 2006.231.08:02:18.88#ibcon#read 5, iclass 24, count 0 2006.231.08:02:18.88#ibcon#about to read 6, iclass 24, count 0 2006.231.08:02:18.88#ibcon#read 6, iclass 24, count 0 2006.231.08:02:18.88#ibcon#end of sib2, iclass 24, count 0 2006.231.08:02:18.88#ibcon#*mode == 0, iclass 24, count 0 2006.231.08:02:18.88#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.08:02:18.89#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:02:18.89#ibcon#*before write, iclass 24, count 0 2006.231.08:02:18.89#ibcon#enter sib2, iclass 24, count 0 2006.231.08:02:18.89#ibcon#flushed, iclass 24, count 0 2006.231.08:02:18.89#ibcon#about to write, iclass 24, count 0 2006.231.08:02:18.89#ibcon#wrote, iclass 24, count 0 2006.231.08:02:18.89#ibcon#about to read 3, iclass 24, count 0 2006.231.08:02:18.92#ibcon#read 3, iclass 24, count 0 2006.231.08:02:18.92#ibcon#about to read 4, iclass 24, count 0 2006.231.08:02:18.92#ibcon#read 4, iclass 24, count 0 2006.231.08:02:18.92#ibcon#about to read 5, iclass 24, count 0 2006.231.08:02:18.92#ibcon#read 5, iclass 24, count 0 2006.231.08:02:18.92#ibcon#about to read 6, iclass 24, count 0 2006.231.08:02:18.92#ibcon#read 6, iclass 24, count 0 2006.231.08:02:18.92#ibcon#end of sib2, iclass 24, count 0 2006.231.08:02:18.92#ibcon#*after write, iclass 24, count 0 2006.231.08:02:18.92#ibcon#*before return 0, iclass 24, count 0 2006.231.08:02:18.92#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:02:18.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:02:18.93#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.08:02:18.93#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.08:02:18.93$vc4f8/va=4,7 2006.231.08:02:18.93#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.231.08:02:18.93#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.231.08:02:18.93#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:18.93#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:02:18.98#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:02:18.98#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:02:18.98#ibcon#enter wrdev, iclass 26, count 2 2006.231.08:02:18.98#ibcon#first serial, iclass 26, count 2 2006.231.08:02:18.98#ibcon#enter sib2, iclass 26, count 2 2006.231.08:02:18.98#ibcon#flushed, iclass 26, count 2 2006.231.08:02:18.98#ibcon#about to write, iclass 26, count 2 2006.231.08:02:18.98#ibcon#wrote, iclass 26, count 2 2006.231.08:02:18.98#ibcon#about to read 3, iclass 26, count 2 2006.231.08:02:19.00#ibcon#read 3, iclass 26, count 2 2006.231.08:02:19.00#ibcon#about to read 4, iclass 26, count 2 2006.231.08:02:19.00#ibcon#read 4, iclass 26, count 2 2006.231.08:02:19.00#ibcon#about to read 5, iclass 26, count 2 2006.231.08:02:19.00#ibcon#read 5, iclass 26, count 2 2006.231.08:02:19.00#ibcon#about to read 6, iclass 26, count 2 2006.231.08:02:19.01#ibcon#read 6, iclass 26, count 2 2006.231.08:02:19.01#ibcon#end of sib2, iclass 26, count 2 2006.231.08:02:19.01#ibcon#*mode == 0, iclass 26, count 2 2006.231.08:02:19.01#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.231.08:02:19.01#ibcon#[25=AT04-07\r\n] 2006.231.08:02:19.01#ibcon#*before write, iclass 26, count 2 2006.231.08:02:19.01#ibcon#enter sib2, iclass 26, count 2 2006.231.08:02:19.01#ibcon#flushed, iclass 26, count 2 2006.231.08:02:19.01#ibcon#about to write, iclass 26, count 2 2006.231.08:02:19.01#ibcon#wrote, iclass 26, count 2 2006.231.08:02:19.01#ibcon#about to read 3, iclass 26, count 2 2006.231.08:02:19.03#ibcon#read 3, iclass 26, count 2 2006.231.08:02:19.03#ibcon#about to read 4, iclass 26, count 2 2006.231.08:02:19.03#ibcon#read 4, iclass 26, count 2 2006.231.08:02:19.03#ibcon#about to read 5, iclass 26, count 2 2006.231.08:02:19.03#ibcon#read 5, iclass 26, count 2 2006.231.08:02:19.03#ibcon#about to read 6, iclass 26, count 2 2006.231.08:02:19.03#ibcon#read 6, iclass 26, count 2 2006.231.08:02:19.03#ibcon#end of sib2, iclass 26, count 2 2006.231.08:02:19.03#ibcon#*after write, iclass 26, count 2 2006.231.08:02:19.03#ibcon#*before return 0, iclass 26, count 2 2006.231.08:02:19.04#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:02:19.04#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:02:19.04#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.231.08:02:19.04#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:19.04#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:02:19.15#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:02:19.16#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:02:19.16#ibcon#enter wrdev, iclass 26, count 0 2006.231.08:02:19.16#ibcon#first serial, iclass 26, count 0 2006.231.08:02:19.16#ibcon#enter sib2, iclass 26, count 0 2006.231.08:02:19.16#ibcon#flushed, iclass 26, count 0 2006.231.08:02:19.16#ibcon#about to write, iclass 26, count 0 2006.231.08:02:19.16#ibcon#wrote, iclass 26, count 0 2006.231.08:02:19.16#ibcon#about to read 3, iclass 26, count 0 2006.231.08:02:19.17#ibcon#read 3, iclass 26, count 0 2006.231.08:02:19.17#ibcon#about to read 4, iclass 26, count 0 2006.231.08:02:19.17#ibcon#read 4, iclass 26, count 0 2006.231.08:02:19.17#ibcon#about to read 5, iclass 26, count 0 2006.231.08:02:19.17#ibcon#read 5, iclass 26, count 0 2006.231.08:02:19.17#ibcon#about to read 6, iclass 26, count 0 2006.231.08:02:19.17#ibcon#read 6, iclass 26, count 0 2006.231.08:02:19.17#ibcon#end of sib2, iclass 26, count 0 2006.231.08:02:19.18#ibcon#*mode == 0, iclass 26, count 0 2006.231.08:02:19.18#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.08:02:19.18#ibcon#[25=USB\r\n] 2006.231.08:02:19.18#ibcon#*before write, iclass 26, count 0 2006.231.08:02:19.18#ibcon#enter sib2, iclass 26, count 0 2006.231.08:02:19.18#ibcon#flushed, iclass 26, count 0 2006.231.08:02:19.18#ibcon#about to write, iclass 26, count 0 2006.231.08:02:19.18#ibcon#wrote, iclass 26, count 0 2006.231.08:02:19.18#ibcon#about to read 3, iclass 26, count 0 2006.231.08:02:19.20#ibcon#read 3, iclass 26, count 0 2006.231.08:02:19.20#ibcon#about to read 4, iclass 26, count 0 2006.231.08:02:19.20#ibcon#read 4, iclass 26, count 0 2006.231.08:02:19.20#ibcon#about to read 5, iclass 26, count 0 2006.231.08:02:19.20#ibcon#read 5, iclass 26, count 0 2006.231.08:02:19.20#ibcon#about to read 6, iclass 26, count 0 2006.231.08:02:19.20#ibcon#read 6, iclass 26, count 0 2006.231.08:02:19.20#ibcon#end of sib2, iclass 26, count 0 2006.231.08:02:19.20#ibcon#*after write, iclass 26, count 0 2006.231.08:02:19.20#ibcon#*before return 0, iclass 26, count 0 2006.231.08:02:19.21#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:02:19.21#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:02:19.21#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.08:02:19.21#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.08:02:19.21$vc4f8/valo=5,652.99 2006.231.08:02:19.21#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.231.08:02:19.21#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.231.08:02:19.21#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:19.21#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:02:19.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:02:19.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:02:19.21#ibcon#enter wrdev, iclass 28, count 0 2006.231.08:02:19.21#ibcon#first serial, iclass 28, count 0 2006.231.08:02:19.21#ibcon#enter sib2, iclass 28, count 0 2006.231.08:02:19.21#ibcon#flushed, iclass 28, count 0 2006.231.08:02:19.21#ibcon#about to write, iclass 28, count 0 2006.231.08:02:19.21#ibcon#wrote, iclass 28, count 0 2006.231.08:02:19.21#ibcon#about to read 3, iclass 28, count 0 2006.231.08:02:19.22#ibcon#read 3, iclass 28, count 0 2006.231.08:02:19.22#ibcon#about to read 4, iclass 28, count 0 2006.231.08:02:19.22#ibcon#read 4, iclass 28, count 0 2006.231.08:02:19.22#ibcon#about to read 5, iclass 28, count 0 2006.231.08:02:19.22#ibcon#read 5, iclass 28, count 0 2006.231.08:02:19.22#ibcon#about to read 6, iclass 28, count 0 2006.231.08:02:19.22#ibcon#read 6, iclass 28, count 0 2006.231.08:02:19.22#ibcon#end of sib2, iclass 28, count 0 2006.231.08:02:19.22#ibcon#*mode == 0, iclass 28, count 0 2006.231.08:02:19.22#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.08:02:19.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:02:19.23#ibcon#*before write, iclass 28, count 0 2006.231.08:02:19.23#ibcon#enter sib2, iclass 28, count 0 2006.231.08:02:19.23#ibcon#flushed, iclass 28, count 0 2006.231.08:02:19.23#ibcon#about to write, iclass 28, count 0 2006.231.08:02:19.23#ibcon#wrote, iclass 28, count 0 2006.231.08:02:19.23#ibcon#about to read 3, iclass 28, count 0 2006.231.08:02:19.26#ibcon#read 3, iclass 28, count 0 2006.231.08:02:19.26#ibcon#about to read 4, iclass 28, count 0 2006.231.08:02:19.26#ibcon#read 4, iclass 28, count 0 2006.231.08:02:19.26#ibcon#about to read 5, iclass 28, count 0 2006.231.08:02:19.26#ibcon#read 5, iclass 28, count 0 2006.231.08:02:19.26#ibcon#about to read 6, iclass 28, count 0 2006.231.08:02:19.26#ibcon#read 6, iclass 28, count 0 2006.231.08:02:19.26#ibcon#end of sib2, iclass 28, count 0 2006.231.08:02:19.26#ibcon#*after write, iclass 28, count 0 2006.231.08:02:19.26#ibcon#*before return 0, iclass 28, count 0 2006.231.08:02:19.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:02:19.27#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:02:19.27#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.08:02:19.27#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.08:02:19.27$vc4f8/va=5,7 2006.231.08:02:19.27#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.08:02:19.27#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.08:02:19.27#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:19.27#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:02:19.32#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:02:19.32#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:02:19.32#ibcon#enter wrdev, iclass 30, count 2 2006.231.08:02:19.32#ibcon#first serial, iclass 30, count 2 2006.231.08:02:19.32#ibcon#enter sib2, iclass 30, count 2 2006.231.08:02:19.32#ibcon#flushed, iclass 30, count 2 2006.231.08:02:19.32#ibcon#about to write, iclass 30, count 2 2006.231.08:02:19.33#ibcon#wrote, iclass 30, count 2 2006.231.08:02:19.33#ibcon#about to read 3, iclass 30, count 2 2006.231.08:02:19.34#ibcon#read 3, iclass 30, count 2 2006.231.08:02:19.34#ibcon#about to read 4, iclass 30, count 2 2006.231.08:02:19.34#ibcon#read 4, iclass 30, count 2 2006.231.08:02:19.34#ibcon#about to read 5, iclass 30, count 2 2006.231.08:02:19.34#ibcon#read 5, iclass 30, count 2 2006.231.08:02:19.34#ibcon#about to read 6, iclass 30, count 2 2006.231.08:02:19.35#ibcon#read 6, iclass 30, count 2 2006.231.08:02:19.35#ibcon#end of sib2, iclass 30, count 2 2006.231.08:02:19.35#ibcon#*mode == 0, iclass 30, count 2 2006.231.08:02:19.35#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.08:02:19.35#ibcon#[25=AT05-07\r\n] 2006.231.08:02:19.35#ibcon#*before write, iclass 30, count 2 2006.231.08:02:19.35#ibcon#enter sib2, iclass 30, count 2 2006.231.08:02:19.35#ibcon#flushed, iclass 30, count 2 2006.231.08:02:19.35#ibcon#about to write, iclass 30, count 2 2006.231.08:02:19.35#ibcon#wrote, iclass 30, count 2 2006.231.08:02:19.35#ibcon#about to read 3, iclass 30, count 2 2006.231.08:02:19.37#ibcon#read 3, iclass 30, count 2 2006.231.08:02:19.37#ibcon#about to read 4, iclass 30, count 2 2006.231.08:02:19.37#ibcon#read 4, iclass 30, count 2 2006.231.08:02:19.37#ibcon#about to read 5, iclass 30, count 2 2006.231.08:02:19.37#ibcon#read 5, iclass 30, count 2 2006.231.08:02:19.37#ibcon#about to read 6, iclass 30, count 2 2006.231.08:02:19.37#ibcon#read 6, iclass 30, count 2 2006.231.08:02:19.37#ibcon#end of sib2, iclass 30, count 2 2006.231.08:02:19.37#ibcon#*after write, iclass 30, count 2 2006.231.08:02:19.37#ibcon#*before return 0, iclass 30, count 2 2006.231.08:02:19.38#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:02:19.38#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:02:19.38#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.08:02:19.38#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:19.38#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:02:19.49#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:02:19.49#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:02:19.49#ibcon#enter wrdev, iclass 30, count 0 2006.231.08:02:19.49#ibcon#first serial, iclass 30, count 0 2006.231.08:02:19.49#ibcon#enter sib2, iclass 30, count 0 2006.231.08:02:19.49#ibcon#flushed, iclass 30, count 0 2006.231.08:02:19.49#ibcon#about to write, iclass 30, count 0 2006.231.08:02:19.49#ibcon#wrote, iclass 30, count 0 2006.231.08:02:19.49#ibcon#about to read 3, iclass 30, count 0 2006.231.08:02:19.52#ibcon#read 3, iclass 30, count 0 2006.231.08:02:19.52#ibcon#about to read 4, iclass 30, count 0 2006.231.08:02:19.52#ibcon#read 4, iclass 30, count 0 2006.231.08:02:19.52#ibcon#about to read 5, iclass 30, count 0 2006.231.08:02:19.52#ibcon#read 5, iclass 30, count 0 2006.231.08:02:19.52#ibcon#about to read 6, iclass 30, count 0 2006.231.08:02:19.52#ibcon#read 6, iclass 30, count 0 2006.231.08:02:19.52#ibcon#end of sib2, iclass 30, count 0 2006.231.08:02:19.52#ibcon#*mode == 0, iclass 30, count 0 2006.231.08:02:19.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.08:02:19.52#ibcon#[25=USB\r\n] 2006.231.08:02:19.52#ibcon#*before write, iclass 30, count 0 2006.231.08:02:19.52#ibcon#enter sib2, iclass 30, count 0 2006.231.08:02:19.52#ibcon#flushed, iclass 30, count 0 2006.231.08:02:19.52#ibcon#about to write, iclass 30, count 0 2006.231.08:02:19.52#ibcon#wrote, iclass 30, count 0 2006.231.08:02:19.52#ibcon#about to read 3, iclass 30, count 0 2006.231.08:02:19.54#ibcon#read 3, iclass 30, count 0 2006.231.08:02:19.54#ibcon#about to read 4, iclass 30, count 0 2006.231.08:02:19.54#ibcon#read 4, iclass 30, count 0 2006.231.08:02:19.54#ibcon#about to read 5, iclass 30, count 0 2006.231.08:02:19.54#ibcon#read 5, iclass 30, count 0 2006.231.08:02:19.54#ibcon#about to read 6, iclass 30, count 0 2006.231.08:02:19.54#ibcon#read 6, iclass 30, count 0 2006.231.08:02:19.54#ibcon#end of sib2, iclass 30, count 0 2006.231.08:02:19.54#ibcon#*after write, iclass 30, count 0 2006.231.08:02:19.55#ibcon#*before return 0, iclass 30, count 0 2006.231.08:02:19.55#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:02:19.55#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:02:19.55#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.08:02:19.55#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.08:02:19.55$vc4f8/valo=6,772.99 2006.231.08:02:19.55#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.08:02:19.55#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.08:02:19.55#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:19.55#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:02:19.55#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:02:19.55#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:02:19.55#ibcon#enter wrdev, iclass 32, count 0 2006.231.08:02:19.55#ibcon#first serial, iclass 32, count 0 2006.231.08:02:19.55#ibcon#enter sib2, iclass 32, count 0 2006.231.08:02:19.55#ibcon#flushed, iclass 32, count 0 2006.231.08:02:19.55#ibcon#about to write, iclass 32, count 0 2006.231.08:02:19.55#ibcon#wrote, iclass 32, count 0 2006.231.08:02:19.55#ibcon#about to read 3, iclass 32, count 0 2006.231.08:02:19.56#ibcon#read 3, iclass 32, count 0 2006.231.08:02:19.56#ibcon#about to read 4, iclass 32, count 0 2006.231.08:02:19.56#ibcon#read 4, iclass 32, count 0 2006.231.08:02:19.56#ibcon#about to read 5, iclass 32, count 0 2006.231.08:02:19.56#ibcon#read 5, iclass 32, count 0 2006.231.08:02:19.56#ibcon#about to read 6, iclass 32, count 0 2006.231.08:02:19.56#ibcon#read 6, iclass 32, count 0 2006.231.08:02:19.57#ibcon#end of sib2, iclass 32, count 0 2006.231.08:02:19.57#ibcon#*mode == 0, iclass 32, count 0 2006.231.08:02:19.57#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.08:02:19.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:02:19.57#ibcon#*before write, iclass 32, count 0 2006.231.08:02:19.57#ibcon#enter sib2, iclass 32, count 0 2006.231.08:02:19.57#ibcon#flushed, iclass 32, count 0 2006.231.08:02:19.57#ibcon#about to write, iclass 32, count 0 2006.231.08:02:19.57#ibcon#wrote, iclass 32, count 0 2006.231.08:02:19.57#ibcon#about to read 3, iclass 32, count 0 2006.231.08:02:19.60#ibcon#read 3, iclass 32, count 0 2006.231.08:02:19.60#ibcon#about to read 4, iclass 32, count 0 2006.231.08:02:19.60#ibcon#read 4, iclass 32, count 0 2006.231.08:02:19.60#ibcon#about to read 5, iclass 32, count 0 2006.231.08:02:19.60#ibcon#read 5, iclass 32, count 0 2006.231.08:02:19.60#ibcon#about to read 6, iclass 32, count 0 2006.231.08:02:19.60#ibcon#read 6, iclass 32, count 0 2006.231.08:02:19.60#ibcon#end of sib2, iclass 32, count 0 2006.231.08:02:19.60#ibcon#*after write, iclass 32, count 0 2006.231.08:02:19.61#ibcon#*before return 0, iclass 32, count 0 2006.231.08:02:19.61#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:02:19.61#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:02:19.61#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.08:02:19.61#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.08:02:19.61$vc4f8/va=6,6 2006.231.08:02:19.61#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.08:02:19.61#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.08:02:19.61#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:19.61#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:02:19.66#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:02:19.66#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:02:19.66#ibcon#enter wrdev, iclass 34, count 2 2006.231.08:02:19.66#ibcon#first serial, iclass 34, count 2 2006.231.08:02:19.66#ibcon#enter sib2, iclass 34, count 2 2006.231.08:02:19.66#ibcon#flushed, iclass 34, count 2 2006.231.08:02:19.66#ibcon#about to write, iclass 34, count 2 2006.231.08:02:19.66#ibcon#wrote, iclass 34, count 2 2006.231.08:02:19.66#ibcon#about to read 3, iclass 34, count 2 2006.231.08:02:19.68#ibcon#read 3, iclass 34, count 2 2006.231.08:02:19.68#ibcon#about to read 4, iclass 34, count 2 2006.231.08:02:19.68#ibcon#read 4, iclass 34, count 2 2006.231.08:02:19.68#ibcon#about to read 5, iclass 34, count 2 2006.231.08:02:19.68#ibcon#read 5, iclass 34, count 2 2006.231.08:02:19.68#ibcon#about to read 6, iclass 34, count 2 2006.231.08:02:19.68#ibcon#read 6, iclass 34, count 2 2006.231.08:02:19.68#ibcon#end of sib2, iclass 34, count 2 2006.231.08:02:19.68#ibcon#*mode == 0, iclass 34, count 2 2006.231.08:02:19.69#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.08:02:19.69#ibcon#[25=AT06-06\r\n] 2006.231.08:02:19.69#ibcon#*before write, iclass 34, count 2 2006.231.08:02:19.69#ibcon#enter sib2, iclass 34, count 2 2006.231.08:02:19.69#ibcon#flushed, iclass 34, count 2 2006.231.08:02:19.69#ibcon#about to write, iclass 34, count 2 2006.231.08:02:19.69#ibcon#wrote, iclass 34, count 2 2006.231.08:02:19.69#ibcon#about to read 3, iclass 34, count 2 2006.231.08:02:19.71#ibcon#read 3, iclass 34, count 2 2006.231.08:02:19.71#ibcon#about to read 4, iclass 34, count 2 2006.231.08:02:19.71#ibcon#read 4, iclass 34, count 2 2006.231.08:02:19.71#ibcon#about to read 5, iclass 34, count 2 2006.231.08:02:19.71#ibcon#read 5, iclass 34, count 2 2006.231.08:02:19.71#ibcon#about to read 6, iclass 34, count 2 2006.231.08:02:19.71#ibcon#read 6, iclass 34, count 2 2006.231.08:02:19.71#ibcon#end of sib2, iclass 34, count 2 2006.231.08:02:19.71#ibcon#*after write, iclass 34, count 2 2006.231.08:02:19.71#ibcon#*before return 0, iclass 34, count 2 2006.231.08:02:19.72#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:02:19.72#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:02:19.72#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.08:02:19.72#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:19.72#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:02:19.83#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:02:19.83#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:02:19.83#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:02:19.83#ibcon#first serial, iclass 34, count 0 2006.231.08:02:19.83#ibcon#enter sib2, iclass 34, count 0 2006.231.08:02:19.83#ibcon#flushed, iclass 34, count 0 2006.231.08:02:19.83#ibcon#about to write, iclass 34, count 0 2006.231.08:02:19.83#ibcon#wrote, iclass 34, count 0 2006.231.08:02:19.83#ibcon#about to read 3, iclass 34, count 0 2006.231.08:02:19.85#ibcon#read 3, iclass 34, count 0 2006.231.08:02:19.85#ibcon#about to read 4, iclass 34, count 0 2006.231.08:02:19.85#ibcon#read 4, iclass 34, count 0 2006.231.08:02:19.85#ibcon#about to read 5, iclass 34, count 0 2006.231.08:02:19.85#ibcon#read 5, iclass 34, count 0 2006.231.08:02:19.85#ibcon#about to read 6, iclass 34, count 0 2006.231.08:02:19.85#ibcon#read 6, iclass 34, count 0 2006.231.08:02:19.85#ibcon#end of sib2, iclass 34, count 0 2006.231.08:02:19.85#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:02:19.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:02:19.86#ibcon#[25=USB\r\n] 2006.231.08:02:19.86#ibcon#*before write, iclass 34, count 0 2006.231.08:02:19.86#ibcon#enter sib2, iclass 34, count 0 2006.231.08:02:19.86#ibcon#flushed, iclass 34, count 0 2006.231.08:02:19.86#ibcon#about to write, iclass 34, count 0 2006.231.08:02:19.86#ibcon#wrote, iclass 34, count 0 2006.231.08:02:19.86#ibcon#about to read 3, iclass 34, count 0 2006.231.08:02:19.88#ibcon#read 3, iclass 34, count 0 2006.231.08:02:19.88#ibcon#about to read 4, iclass 34, count 0 2006.231.08:02:19.88#ibcon#read 4, iclass 34, count 0 2006.231.08:02:19.88#ibcon#about to read 5, iclass 34, count 0 2006.231.08:02:19.88#ibcon#read 5, iclass 34, count 0 2006.231.08:02:19.88#ibcon#about to read 6, iclass 34, count 0 2006.231.08:02:19.88#ibcon#read 6, iclass 34, count 0 2006.231.08:02:19.88#ibcon#end of sib2, iclass 34, count 0 2006.231.08:02:19.88#ibcon#*after write, iclass 34, count 0 2006.231.08:02:19.88#ibcon#*before return 0, iclass 34, count 0 2006.231.08:02:19.88#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:02:19.89#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:02:19.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:02:19.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:02:19.89$vc4f8/valo=7,832.99 2006.231.08:02:19.89#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.08:02:19.89#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.08:02:19.89#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:19.89#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:02:19.89#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:02:19.89#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:02:19.89#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:02:19.89#ibcon#first serial, iclass 36, count 0 2006.231.08:02:19.89#ibcon#enter sib2, iclass 36, count 0 2006.231.08:02:19.89#ibcon#flushed, iclass 36, count 0 2006.231.08:02:19.89#ibcon#about to write, iclass 36, count 0 2006.231.08:02:19.89#ibcon#wrote, iclass 36, count 0 2006.231.08:02:19.89#ibcon#about to read 3, iclass 36, count 0 2006.231.08:02:19.90#ibcon#read 3, iclass 36, count 0 2006.231.08:02:19.90#ibcon#about to read 4, iclass 36, count 0 2006.231.08:02:19.90#ibcon#read 4, iclass 36, count 0 2006.231.08:02:19.90#ibcon#about to read 5, iclass 36, count 0 2006.231.08:02:19.90#ibcon#read 5, iclass 36, count 0 2006.231.08:02:19.90#ibcon#about to read 6, iclass 36, count 0 2006.231.08:02:19.90#ibcon#read 6, iclass 36, count 0 2006.231.08:02:19.90#ibcon#end of sib2, iclass 36, count 0 2006.231.08:02:19.90#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:02:19.90#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:02:19.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:02:19.91#ibcon#*before write, iclass 36, count 0 2006.231.08:02:19.91#ibcon#enter sib2, iclass 36, count 0 2006.231.08:02:19.91#ibcon#flushed, iclass 36, count 0 2006.231.08:02:19.91#ibcon#about to write, iclass 36, count 0 2006.231.08:02:19.91#ibcon#wrote, iclass 36, count 0 2006.231.08:02:19.91#ibcon#about to read 3, iclass 36, count 0 2006.231.08:02:19.94#ibcon#read 3, iclass 36, count 0 2006.231.08:02:19.94#ibcon#about to read 4, iclass 36, count 0 2006.231.08:02:19.94#ibcon#read 4, iclass 36, count 0 2006.231.08:02:19.94#ibcon#about to read 5, iclass 36, count 0 2006.231.08:02:19.94#ibcon#read 5, iclass 36, count 0 2006.231.08:02:19.94#ibcon#about to read 6, iclass 36, count 0 2006.231.08:02:19.94#ibcon#read 6, iclass 36, count 0 2006.231.08:02:19.94#ibcon#end of sib2, iclass 36, count 0 2006.231.08:02:19.94#ibcon#*after write, iclass 36, count 0 2006.231.08:02:19.94#ibcon#*before return 0, iclass 36, count 0 2006.231.08:02:19.95#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:02:19.95#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:02:19.95#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:02:19.95#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:02:19.95$vc4f8/va=7,6 2006.231.08:02:19.95#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.08:02:19.95#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.08:02:19.95#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:19.95#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:02:20.01#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:02:20.01#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:02:20.01#ibcon#enter wrdev, iclass 38, count 2 2006.231.08:02:20.01#ibcon#first serial, iclass 38, count 2 2006.231.08:02:20.01#ibcon#enter sib2, iclass 38, count 2 2006.231.08:02:20.01#ibcon#flushed, iclass 38, count 2 2006.231.08:02:20.01#ibcon#about to write, iclass 38, count 2 2006.231.08:02:20.01#ibcon#wrote, iclass 38, count 2 2006.231.08:02:20.01#ibcon#about to read 3, iclass 38, count 2 2006.231.08:02:20.02#ibcon#read 3, iclass 38, count 2 2006.231.08:02:20.02#ibcon#about to read 4, iclass 38, count 2 2006.231.08:02:20.02#ibcon#read 4, iclass 38, count 2 2006.231.08:02:20.02#ibcon#about to read 5, iclass 38, count 2 2006.231.08:02:20.02#ibcon#read 5, iclass 38, count 2 2006.231.08:02:20.02#ibcon#about to read 6, iclass 38, count 2 2006.231.08:02:20.02#ibcon#read 6, iclass 38, count 2 2006.231.08:02:20.02#ibcon#end of sib2, iclass 38, count 2 2006.231.08:02:20.02#ibcon#*mode == 0, iclass 38, count 2 2006.231.08:02:20.02#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.08:02:20.03#ibcon#[25=AT07-06\r\n] 2006.231.08:02:20.03#ibcon#*before write, iclass 38, count 2 2006.231.08:02:20.03#ibcon#enter sib2, iclass 38, count 2 2006.231.08:02:20.03#ibcon#flushed, iclass 38, count 2 2006.231.08:02:20.03#ibcon#about to write, iclass 38, count 2 2006.231.08:02:20.03#ibcon#wrote, iclass 38, count 2 2006.231.08:02:20.03#ibcon#about to read 3, iclass 38, count 2 2006.231.08:02:20.05#ibcon#read 3, iclass 38, count 2 2006.231.08:02:20.05#ibcon#about to read 4, iclass 38, count 2 2006.231.08:02:20.05#ibcon#read 4, iclass 38, count 2 2006.231.08:02:20.05#ibcon#about to read 5, iclass 38, count 2 2006.231.08:02:20.05#ibcon#read 5, iclass 38, count 2 2006.231.08:02:20.05#ibcon#about to read 6, iclass 38, count 2 2006.231.08:02:20.05#ibcon#read 6, iclass 38, count 2 2006.231.08:02:20.05#ibcon#end of sib2, iclass 38, count 2 2006.231.08:02:20.05#ibcon#*after write, iclass 38, count 2 2006.231.08:02:20.05#ibcon#*before return 0, iclass 38, count 2 2006.231.08:02:20.06#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:02:20.06#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:02:20.06#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.08:02:20.06#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:20.06#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:02:20.17#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:02:20.17#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:02:20.17#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:02:20.17#ibcon#first serial, iclass 38, count 0 2006.231.08:02:20.17#ibcon#enter sib2, iclass 38, count 0 2006.231.08:02:20.17#ibcon#flushed, iclass 38, count 0 2006.231.08:02:20.17#ibcon#about to write, iclass 38, count 0 2006.231.08:02:20.17#ibcon#wrote, iclass 38, count 0 2006.231.08:02:20.17#ibcon#about to read 3, iclass 38, count 0 2006.231.08:02:20.20#ibcon#read 3, iclass 38, count 0 2006.231.08:02:20.20#ibcon#about to read 4, iclass 38, count 0 2006.231.08:02:20.20#ibcon#read 4, iclass 38, count 0 2006.231.08:02:20.20#ibcon#about to read 5, iclass 38, count 0 2006.231.08:02:20.20#ibcon#read 5, iclass 38, count 0 2006.231.08:02:20.20#ibcon#about to read 6, iclass 38, count 0 2006.231.08:02:20.20#ibcon#read 6, iclass 38, count 0 2006.231.08:02:20.20#ibcon#end of sib2, iclass 38, count 0 2006.231.08:02:20.20#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:02:20.20#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:02:20.20#ibcon#[25=USB\r\n] 2006.231.08:02:20.20#ibcon#*before write, iclass 38, count 0 2006.231.08:02:20.20#ibcon#enter sib2, iclass 38, count 0 2006.231.08:02:20.20#ibcon#flushed, iclass 38, count 0 2006.231.08:02:20.20#ibcon#about to write, iclass 38, count 0 2006.231.08:02:20.20#ibcon#wrote, iclass 38, count 0 2006.231.08:02:20.20#ibcon#about to read 3, iclass 38, count 0 2006.231.08:02:20.22#ibcon#read 3, iclass 38, count 0 2006.231.08:02:20.22#ibcon#about to read 4, iclass 38, count 0 2006.231.08:02:20.22#ibcon#read 4, iclass 38, count 0 2006.231.08:02:20.22#ibcon#about to read 5, iclass 38, count 0 2006.231.08:02:20.22#ibcon#read 5, iclass 38, count 0 2006.231.08:02:20.22#ibcon#about to read 6, iclass 38, count 0 2006.231.08:02:20.22#ibcon#read 6, iclass 38, count 0 2006.231.08:02:20.22#ibcon#end of sib2, iclass 38, count 0 2006.231.08:02:20.22#ibcon#*after write, iclass 38, count 0 2006.231.08:02:20.22#ibcon#*before return 0, iclass 38, count 0 2006.231.08:02:20.23#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:02:20.23#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:02:20.23#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:02:20.23#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:02:20.23$vc4f8/valo=8,852.99 2006.231.08:02:20.23#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.08:02:20.23#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.08:02:20.23#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:20.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:02:20.23#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:02:20.23#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:02:20.23#ibcon#enter wrdev, iclass 40, count 0 2006.231.08:02:20.23#ibcon#first serial, iclass 40, count 0 2006.231.08:02:20.23#ibcon#enter sib2, iclass 40, count 0 2006.231.08:02:20.23#ibcon#flushed, iclass 40, count 0 2006.231.08:02:20.23#ibcon#about to write, iclass 40, count 0 2006.231.08:02:20.23#ibcon#wrote, iclass 40, count 0 2006.231.08:02:20.23#ibcon#about to read 3, iclass 40, count 0 2006.231.08:02:20.24#ibcon#read 3, iclass 40, count 0 2006.231.08:02:20.24#ibcon#about to read 4, iclass 40, count 0 2006.231.08:02:20.24#ibcon#read 4, iclass 40, count 0 2006.231.08:02:20.24#ibcon#about to read 5, iclass 40, count 0 2006.231.08:02:20.24#ibcon#read 5, iclass 40, count 0 2006.231.08:02:20.24#ibcon#about to read 6, iclass 40, count 0 2006.231.08:02:20.24#ibcon#read 6, iclass 40, count 0 2006.231.08:02:20.24#ibcon#end of sib2, iclass 40, count 0 2006.231.08:02:20.24#ibcon#*mode == 0, iclass 40, count 0 2006.231.08:02:20.25#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.08:02:20.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:02:20.25#ibcon#*before write, iclass 40, count 0 2006.231.08:02:20.25#ibcon#enter sib2, iclass 40, count 0 2006.231.08:02:20.25#ibcon#flushed, iclass 40, count 0 2006.231.08:02:20.25#ibcon#about to write, iclass 40, count 0 2006.231.08:02:20.25#ibcon#wrote, iclass 40, count 0 2006.231.08:02:20.25#ibcon#about to read 3, iclass 40, count 0 2006.231.08:02:20.28#ibcon#read 3, iclass 40, count 0 2006.231.08:02:20.28#ibcon#about to read 4, iclass 40, count 0 2006.231.08:02:20.28#ibcon#read 4, iclass 40, count 0 2006.231.08:02:20.28#ibcon#about to read 5, iclass 40, count 0 2006.231.08:02:20.28#ibcon#read 5, iclass 40, count 0 2006.231.08:02:20.28#ibcon#about to read 6, iclass 40, count 0 2006.231.08:02:20.28#ibcon#read 6, iclass 40, count 0 2006.231.08:02:20.28#ibcon#end of sib2, iclass 40, count 0 2006.231.08:02:20.28#ibcon#*after write, iclass 40, count 0 2006.231.08:02:20.28#ibcon#*before return 0, iclass 40, count 0 2006.231.08:02:20.29#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:02:20.29#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:02:20.29#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.08:02:20.29#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.08:02:20.29$vc4f8/va=8,6 2006.231.08:02:20.29#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.231.08:02:20.29#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.231.08:02:20.29#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:20.29#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:02:20.34#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:02:20.34#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:02:20.34#ibcon#enter wrdev, iclass 4, count 2 2006.231.08:02:20.34#ibcon#first serial, iclass 4, count 2 2006.231.08:02:20.34#ibcon#enter sib2, iclass 4, count 2 2006.231.08:02:20.34#ibcon#flushed, iclass 4, count 2 2006.231.08:02:20.34#ibcon#about to write, iclass 4, count 2 2006.231.08:02:20.35#ibcon#wrote, iclass 4, count 2 2006.231.08:02:20.35#ibcon#about to read 3, iclass 4, count 2 2006.231.08:02:20.36#ibcon#read 3, iclass 4, count 2 2006.231.08:02:20.36#ibcon#about to read 4, iclass 4, count 2 2006.231.08:02:20.36#ibcon#read 4, iclass 4, count 2 2006.231.08:02:20.36#ibcon#about to read 5, iclass 4, count 2 2006.231.08:02:20.36#ibcon#read 5, iclass 4, count 2 2006.231.08:02:20.36#ibcon#about to read 6, iclass 4, count 2 2006.231.08:02:20.36#ibcon#read 6, iclass 4, count 2 2006.231.08:02:20.36#ibcon#end of sib2, iclass 4, count 2 2006.231.08:02:20.36#ibcon#*mode == 0, iclass 4, count 2 2006.231.08:02:20.36#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.231.08:02:20.37#ibcon#[25=AT08-06\r\n] 2006.231.08:02:20.37#ibcon#*before write, iclass 4, count 2 2006.231.08:02:20.37#ibcon#enter sib2, iclass 4, count 2 2006.231.08:02:20.37#ibcon#flushed, iclass 4, count 2 2006.231.08:02:20.37#ibcon#about to write, iclass 4, count 2 2006.231.08:02:20.37#ibcon#wrote, iclass 4, count 2 2006.231.08:02:20.37#ibcon#about to read 3, iclass 4, count 2 2006.231.08:02:20.39#ibcon#read 3, iclass 4, count 2 2006.231.08:02:20.39#ibcon#about to read 4, iclass 4, count 2 2006.231.08:02:20.39#ibcon#read 4, iclass 4, count 2 2006.231.08:02:20.39#ibcon#about to read 5, iclass 4, count 2 2006.231.08:02:20.39#ibcon#read 5, iclass 4, count 2 2006.231.08:02:20.39#ibcon#about to read 6, iclass 4, count 2 2006.231.08:02:20.39#ibcon#read 6, iclass 4, count 2 2006.231.08:02:20.39#ibcon#end of sib2, iclass 4, count 2 2006.231.08:02:20.40#ibcon#*after write, iclass 4, count 2 2006.231.08:02:20.40#ibcon#*before return 0, iclass 4, count 2 2006.231.08:02:20.40#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:02:20.40#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:02:20.40#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.231.08:02:20.40#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:20.40#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:02:20.51#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:02:20.51#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:02:20.51#ibcon#enter wrdev, iclass 4, count 0 2006.231.08:02:20.51#ibcon#first serial, iclass 4, count 0 2006.231.08:02:20.51#ibcon#enter sib2, iclass 4, count 0 2006.231.08:02:20.51#ibcon#flushed, iclass 4, count 0 2006.231.08:02:20.51#ibcon#about to write, iclass 4, count 0 2006.231.08:02:20.51#ibcon#wrote, iclass 4, count 0 2006.231.08:02:20.52#ibcon#about to read 3, iclass 4, count 0 2006.231.08:02:20.53#ibcon#read 3, iclass 4, count 0 2006.231.08:02:20.53#ibcon#about to read 4, iclass 4, count 0 2006.231.08:02:20.53#ibcon#read 4, iclass 4, count 0 2006.231.08:02:20.53#ibcon#about to read 5, iclass 4, count 0 2006.231.08:02:20.53#ibcon#read 5, iclass 4, count 0 2006.231.08:02:20.53#ibcon#about to read 6, iclass 4, count 0 2006.231.08:02:20.53#ibcon#read 6, iclass 4, count 0 2006.231.08:02:20.53#ibcon#end of sib2, iclass 4, count 0 2006.231.08:02:20.53#ibcon#*mode == 0, iclass 4, count 0 2006.231.08:02:20.53#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.08:02:20.54#ibcon#[25=USB\r\n] 2006.231.08:02:20.54#ibcon#*before write, iclass 4, count 0 2006.231.08:02:20.54#ibcon#enter sib2, iclass 4, count 0 2006.231.08:02:20.54#ibcon#flushed, iclass 4, count 0 2006.231.08:02:20.54#ibcon#about to write, iclass 4, count 0 2006.231.08:02:20.54#ibcon#wrote, iclass 4, count 0 2006.231.08:02:20.54#ibcon#about to read 3, iclass 4, count 0 2006.231.08:02:20.56#ibcon#read 3, iclass 4, count 0 2006.231.08:02:20.56#ibcon#about to read 4, iclass 4, count 0 2006.231.08:02:20.56#ibcon#read 4, iclass 4, count 0 2006.231.08:02:20.56#ibcon#about to read 5, iclass 4, count 0 2006.231.08:02:20.56#ibcon#read 5, iclass 4, count 0 2006.231.08:02:20.56#ibcon#about to read 6, iclass 4, count 0 2006.231.08:02:20.56#ibcon#read 6, iclass 4, count 0 2006.231.08:02:20.56#ibcon#end of sib2, iclass 4, count 0 2006.231.08:02:20.57#ibcon#*after write, iclass 4, count 0 2006.231.08:02:20.57#ibcon#*before return 0, iclass 4, count 0 2006.231.08:02:20.57#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:02:20.57#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:02:20.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.08:02:20.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.08:02:20.57$vc4f8/vblo=1,632.99 2006.231.08:02:20.57#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.231.08:02:20.57#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.231.08:02:20.57#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:20.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:02:20.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:02:20.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:02:20.57#ibcon#enter wrdev, iclass 6, count 0 2006.231.08:02:20.57#ibcon#first serial, iclass 6, count 0 2006.231.08:02:20.57#ibcon#enter sib2, iclass 6, count 0 2006.231.08:02:20.57#ibcon#flushed, iclass 6, count 0 2006.231.08:02:20.57#ibcon#about to write, iclass 6, count 0 2006.231.08:02:20.57#ibcon#wrote, iclass 6, count 0 2006.231.08:02:20.57#ibcon#about to read 3, iclass 6, count 0 2006.231.08:02:20.58#ibcon#read 3, iclass 6, count 0 2006.231.08:02:20.58#ibcon#about to read 4, iclass 6, count 0 2006.231.08:02:20.58#ibcon#read 4, iclass 6, count 0 2006.231.08:02:20.58#ibcon#about to read 5, iclass 6, count 0 2006.231.08:02:20.58#ibcon#read 5, iclass 6, count 0 2006.231.08:02:20.58#ibcon#about to read 6, iclass 6, count 0 2006.231.08:02:20.58#ibcon#read 6, iclass 6, count 0 2006.231.08:02:20.58#ibcon#end of sib2, iclass 6, count 0 2006.231.08:02:20.58#ibcon#*mode == 0, iclass 6, count 0 2006.231.08:02:20.58#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.08:02:20.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:02:20.59#ibcon#*before write, iclass 6, count 0 2006.231.08:02:20.59#ibcon#enter sib2, iclass 6, count 0 2006.231.08:02:20.59#ibcon#flushed, iclass 6, count 0 2006.231.08:02:20.59#ibcon#about to write, iclass 6, count 0 2006.231.08:02:20.59#ibcon#wrote, iclass 6, count 0 2006.231.08:02:20.59#ibcon#about to read 3, iclass 6, count 0 2006.231.08:02:20.62#ibcon#read 3, iclass 6, count 0 2006.231.08:02:20.62#ibcon#about to read 4, iclass 6, count 0 2006.231.08:02:20.62#ibcon#read 4, iclass 6, count 0 2006.231.08:02:20.62#ibcon#about to read 5, iclass 6, count 0 2006.231.08:02:20.62#ibcon#read 5, iclass 6, count 0 2006.231.08:02:20.62#ibcon#about to read 6, iclass 6, count 0 2006.231.08:02:20.62#ibcon#read 6, iclass 6, count 0 2006.231.08:02:20.62#ibcon#end of sib2, iclass 6, count 0 2006.231.08:02:20.62#ibcon#*after write, iclass 6, count 0 2006.231.08:02:20.62#ibcon#*before return 0, iclass 6, count 0 2006.231.08:02:20.63#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:02:20.63#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:02:20.63#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.08:02:20.63#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.08:02:20.63$vc4f8/vb=1,4 2006.231.08:02:20.63#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.231.08:02:20.63#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.231.08:02:20.63#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:20.63#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:02:20.63#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:02:20.63#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:02:20.63#ibcon#enter wrdev, iclass 10, count 2 2006.231.08:02:20.63#ibcon#first serial, iclass 10, count 2 2006.231.08:02:20.63#ibcon#enter sib2, iclass 10, count 2 2006.231.08:02:20.63#ibcon#flushed, iclass 10, count 2 2006.231.08:02:20.63#ibcon#about to write, iclass 10, count 2 2006.231.08:02:20.63#ibcon#wrote, iclass 10, count 2 2006.231.08:02:20.63#ibcon#about to read 3, iclass 10, count 2 2006.231.08:02:20.64#ibcon#read 3, iclass 10, count 2 2006.231.08:02:20.64#ibcon#about to read 4, iclass 10, count 2 2006.231.08:02:20.64#ibcon#read 4, iclass 10, count 2 2006.231.08:02:20.64#ibcon#about to read 5, iclass 10, count 2 2006.231.08:02:20.64#ibcon#read 5, iclass 10, count 2 2006.231.08:02:20.64#ibcon#about to read 6, iclass 10, count 2 2006.231.08:02:20.64#ibcon#read 6, iclass 10, count 2 2006.231.08:02:20.64#ibcon#end of sib2, iclass 10, count 2 2006.231.08:02:20.64#ibcon#*mode == 0, iclass 10, count 2 2006.231.08:02:20.64#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.231.08:02:20.64#ibcon#[27=AT01-04\r\n] 2006.231.08:02:20.65#ibcon#*before write, iclass 10, count 2 2006.231.08:02:20.65#ibcon#enter sib2, iclass 10, count 2 2006.231.08:02:20.65#ibcon#flushed, iclass 10, count 2 2006.231.08:02:20.65#ibcon#about to write, iclass 10, count 2 2006.231.08:02:20.65#ibcon#wrote, iclass 10, count 2 2006.231.08:02:20.65#ibcon#about to read 3, iclass 10, count 2 2006.231.08:02:20.67#ibcon#read 3, iclass 10, count 2 2006.231.08:02:20.67#ibcon#about to read 4, iclass 10, count 2 2006.231.08:02:20.67#ibcon#read 4, iclass 10, count 2 2006.231.08:02:20.67#ibcon#about to read 5, iclass 10, count 2 2006.231.08:02:20.67#ibcon#read 5, iclass 10, count 2 2006.231.08:02:20.67#ibcon#about to read 6, iclass 10, count 2 2006.231.08:02:20.67#ibcon#read 6, iclass 10, count 2 2006.231.08:02:20.67#ibcon#end of sib2, iclass 10, count 2 2006.231.08:02:20.67#ibcon#*after write, iclass 10, count 2 2006.231.08:02:20.67#ibcon#*before return 0, iclass 10, count 2 2006.231.08:02:20.67#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:02:20.67#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:02:20.68#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.231.08:02:20.68#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:20.68#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:02:20.78#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:02:20.78#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:02:20.78#ibcon#enter wrdev, iclass 10, count 0 2006.231.08:02:20.78#ibcon#first serial, iclass 10, count 0 2006.231.08:02:20.78#ibcon#enter sib2, iclass 10, count 0 2006.231.08:02:20.78#ibcon#flushed, iclass 10, count 0 2006.231.08:02:20.78#ibcon#about to write, iclass 10, count 0 2006.231.08:02:20.78#ibcon#wrote, iclass 10, count 0 2006.231.08:02:20.79#ibcon#about to read 3, iclass 10, count 0 2006.231.08:02:20.80#ibcon#read 3, iclass 10, count 0 2006.231.08:02:20.80#ibcon#about to read 4, iclass 10, count 0 2006.231.08:02:20.80#ibcon#read 4, iclass 10, count 0 2006.231.08:02:20.80#ibcon#about to read 5, iclass 10, count 0 2006.231.08:02:20.80#ibcon#read 5, iclass 10, count 0 2006.231.08:02:20.80#ibcon#about to read 6, iclass 10, count 0 2006.231.08:02:20.80#ibcon#read 6, iclass 10, count 0 2006.231.08:02:20.80#ibcon#end of sib2, iclass 10, count 0 2006.231.08:02:20.80#ibcon#*mode == 0, iclass 10, count 0 2006.231.08:02:20.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.08:02:20.80#ibcon#[27=USB\r\n] 2006.231.08:02:20.81#ibcon#*before write, iclass 10, count 0 2006.231.08:02:20.81#ibcon#enter sib2, iclass 10, count 0 2006.231.08:02:20.81#ibcon#flushed, iclass 10, count 0 2006.231.08:02:20.81#ibcon#about to write, iclass 10, count 0 2006.231.08:02:20.81#ibcon#wrote, iclass 10, count 0 2006.231.08:02:20.81#ibcon#about to read 3, iclass 10, count 0 2006.231.08:02:20.83#ibcon#read 3, iclass 10, count 0 2006.231.08:02:20.83#ibcon#about to read 4, iclass 10, count 0 2006.231.08:02:20.83#ibcon#read 4, iclass 10, count 0 2006.231.08:02:20.83#ibcon#about to read 5, iclass 10, count 0 2006.231.08:02:20.83#ibcon#read 5, iclass 10, count 0 2006.231.08:02:20.83#ibcon#about to read 6, iclass 10, count 0 2006.231.08:02:20.83#ibcon#read 6, iclass 10, count 0 2006.231.08:02:20.83#ibcon#end of sib2, iclass 10, count 0 2006.231.08:02:20.83#ibcon#*after write, iclass 10, count 0 2006.231.08:02:20.83#ibcon#*before return 0, iclass 10, count 0 2006.231.08:02:20.83#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:02:20.84#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:02:20.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.08:02:20.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.08:02:20.84$vc4f8/vblo=2,640.99 2006.231.08:02:20.84#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.08:02:20.84#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.08:02:20.84#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:20.84#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:02:20.84#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:02:20.84#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:02:20.84#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:02:20.84#ibcon#first serial, iclass 12, count 0 2006.231.08:02:20.84#ibcon#enter sib2, iclass 12, count 0 2006.231.08:02:20.84#ibcon#flushed, iclass 12, count 0 2006.231.08:02:20.84#ibcon#about to write, iclass 12, count 0 2006.231.08:02:20.84#ibcon#wrote, iclass 12, count 0 2006.231.08:02:20.84#ibcon#about to read 3, iclass 12, count 0 2006.231.08:02:20.86#ibcon#read 3, iclass 12, count 0 2006.231.08:02:20.86#ibcon#about to read 4, iclass 12, count 0 2006.231.08:02:20.86#ibcon#read 4, iclass 12, count 0 2006.231.08:02:20.86#ibcon#about to read 5, iclass 12, count 0 2006.231.08:02:20.86#ibcon#read 5, iclass 12, count 0 2006.231.08:02:20.86#ibcon#about to read 6, iclass 12, count 0 2006.231.08:02:20.86#ibcon#read 6, iclass 12, count 0 2006.231.08:02:20.86#ibcon#end of sib2, iclass 12, count 0 2006.231.08:02:20.86#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:02:20.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:02:20.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:02:20.86#ibcon#*before write, iclass 12, count 0 2006.231.08:02:20.86#ibcon#enter sib2, iclass 12, count 0 2006.231.08:02:20.86#ibcon#flushed, iclass 12, count 0 2006.231.08:02:20.86#ibcon#about to write, iclass 12, count 0 2006.231.08:02:20.86#ibcon#wrote, iclass 12, count 0 2006.231.08:02:20.86#ibcon#about to read 3, iclass 12, count 0 2006.231.08:02:20.89#ibcon#read 3, iclass 12, count 0 2006.231.08:02:20.89#ibcon#about to read 4, iclass 12, count 0 2006.231.08:02:20.89#ibcon#read 4, iclass 12, count 0 2006.231.08:02:20.89#ibcon#about to read 5, iclass 12, count 0 2006.231.08:02:20.89#ibcon#read 5, iclass 12, count 0 2006.231.08:02:20.89#ibcon#about to read 6, iclass 12, count 0 2006.231.08:02:20.89#ibcon#read 6, iclass 12, count 0 2006.231.08:02:20.90#ibcon#end of sib2, iclass 12, count 0 2006.231.08:02:20.90#ibcon#*after write, iclass 12, count 0 2006.231.08:02:20.90#ibcon#*before return 0, iclass 12, count 0 2006.231.08:02:20.90#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:02:20.90#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:02:20.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:02:20.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:02:20.90$vc4f8/vb=2,4 2006.231.08:02:20.90#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.08:02:20.90#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.08:02:20.90#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:20.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:02:20.95#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:02:20.95#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:02:20.95#ibcon#enter wrdev, iclass 14, count 2 2006.231.08:02:20.95#ibcon#first serial, iclass 14, count 2 2006.231.08:02:20.95#ibcon#enter sib2, iclass 14, count 2 2006.231.08:02:20.95#ibcon#flushed, iclass 14, count 2 2006.231.08:02:20.95#ibcon#about to write, iclass 14, count 2 2006.231.08:02:20.95#ibcon#wrote, iclass 14, count 2 2006.231.08:02:20.95#ibcon#about to read 3, iclass 14, count 2 2006.231.08:02:20.97#ibcon#read 3, iclass 14, count 2 2006.231.08:02:20.97#ibcon#about to read 4, iclass 14, count 2 2006.231.08:02:20.97#ibcon#read 4, iclass 14, count 2 2006.231.08:02:20.97#ibcon#about to read 5, iclass 14, count 2 2006.231.08:02:20.97#ibcon#read 5, iclass 14, count 2 2006.231.08:02:20.97#ibcon#about to read 6, iclass 14, count 2 2006.231.08:02:20.97#ibcon#read 6, iclass 14, count 2 2006.231.08:02:20.97#ibcon#end of sib2, iclass 14, count 2 2006.231.08:02:20.97#ibcon#*mode == 0, iclass 14, count 2 2006.231.08:02:20.97#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.08:02:20.97#ibcon#[27=AT02-04\r\n] 2006.231.08:02:20.97#ibcon#*before write, iclass 14, count 2 2006.231.08:02:20.97#ibcon#enter sib2, iclass 14, count 2 2006.231.08:02:20.97#ibcon#flushed, iclass 14, count 2 2006.231.08:02:20.97#ibcon#about to write, iclass 14, count 2 2006.231.08:02:20.98#ibcon#wrote, iclass 14, count 2 2006.231.08:02:20.98#ibcon#about to read 3, iclass 14, count 2 2006.231.08:02:21.00#ibcon#read 3, iclass 14, count 2 2006.231.08:02:21.00#ibcon#about to read 4, iclass 14, count 2 2006.231.08:02:21.00#ibcon#read 4, iclass 14, count 2 2006.231.08:02:21.00#ibcon#about to read 5, iclass 14, count 2 2006.231.08:02:21.00#ibcon#read 5, iclass 14, count 2 2006.231.08:02:21.00#ibcon#about to read 6, iclass 14, count 2 2006.231.08:02:21.00#ibcon#read 6, iclass 14, count 2 2006.231.08:02:21.00#ibcon#end of sib2, iclass 14, count 2 2006.231.08:02:21.00#ibcon#*after write, iclass 14, count 2 2006.231.08:02:21.00#ibcon#*before return 0, iclass 14, count 2 2006.231.08:02:21.00#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:02:21.01#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:02:21.01#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.08:02:21.01#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:21.01#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:02:21.12#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:02:21.12#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:02:21.12#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:02:21.12#ibcon#first serial, iclass 14, count 0 2006.231.08:02:21.12#ibcon#enter sib2, iclass 14, count 0 2006.231.08:02:21.12#ibcon#flushed, iclass 14, count 0 2006.231.08:02:21.12#ibcon#about to write, iclass 14, count 0 2006.231.08:02:21.12#ibcon#wrote, iclass 14, count 0 2006.231.08:02:21.12#ibcon#about to read 3, iclass 14, count 0 2006.231.08:02:21.14#ibcon#read 3, iclass 14, count 0 2006.231.08:02:21.14#ibcon#about to read 4, iclass 14, count 0 2006.231.08:02:21.14#ibcon#read 4, iclass 14, count 0 2006.231.08:02:21.14#ibcon#about to read 5, iclass 14, count 0 2006.231.08:02:21.14#ibcon#read 5, iclass 14, count 0 2006.231.08:02:21.14#ibcon#about to read 6, iclass 14, count 0 2006.231.08:02:21.14#ibcon#read 6, iclass 14, count 0 2006.231.08:02:21.14#ibcon#end of sib2, iclass 14, count 0 2006.231.08:02:21.14#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:02:21.14#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:02:21.14#ibcon#[27=USB\r\n] 2006.231.08:02:21.15#ibcon#*before write, iclass 14, count 0 2006.231.08:02:21.15#ibcon#enter sib2, iclass 14, count 0 2006.231.08:02:21.15#ibcon#flushed, iclass 14, count 0 2006.231.08:02:21.15#ibcon#about to write, iclass 14, count 0 2006.231.08:02:21.15#ibcon#wrote, iclass 14, count 0 2006.231.08:02:21.15#ibcon#about to read 3, iclass 14, count 0 2006.231.08:02:21.17#ibcon#read 3, iclass 14, count 0 2006.231.08:02:21.17#ibcon#about to read 4, iclass 14, count 0 2006.231.08:02:21.17#ibcon#read 4, iclass 14, count 0 2006.231.08:02:21.17#ibcon#about to read 5, iclass 14, count 0 2006.231.08:02:21.17#ibcon#read 5, iclass 14, count 0 2006.231.08:02:21.17#ibcon#about to read 6, iclass 14, count 0 2006.231.08:02:21.17#ibcon#read 6, iclass 14, count 0 2006.231.08:02:21.17#ibcon#end of sib2, iclass 14, count 0 2006.231.08:02:21.17#ibcon#*after write, iclass 14, count 0 2006.231.08:02:21.17#ibcon#*before return 0, iclass 14, count 0 2006.231.08:02:21.18#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:02:21.18#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:02:21.18#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:02:21.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:02:21.18$vc4f8/vblo=3,656.99 2006.231.08:02:21.18#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.08:02:21.18#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.08:02:21.18#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:21.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:02:21.18#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:02:21.18#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:02:21.18#ibcon#enter wrdev, iclass 16, count 0 2006.231.08:02:21.18#ibcon#first serial, iclass 16, count 0 2006.231.08:02:21.18#ibcon#enter sib2, iclass 16, count 0 2006.231.08:02:21.18#ibcon#flushed, iclass 16, count 0 2006.231.08:02:21.18#ibcon#about to write, iclass 16, count 0 2006.231.08:02:21.18#ibcon#wrote, iclass 16, count 0 2006.231.08:02:21.18#ibcon#about to read 3, iclass 16, count 0 2006.231.08:02:21.19#ibcon#read 3, iclass 16, count 0 2006.231.08:02:21.19#ibcon#about to read 4, iclass 16, count 0 2006.231.08:02:21.19#ibcon#read 4, iclass 16, count 0 2006.231.08:02:21.19#ibcon#about to read 5, iclass 16, count 0 2006.231.08:02:21.19#ibcon#read 5, iclass 16, count 0 2006.231.08:02:21.19#ibcon#about to read 6, iclass 16, count 0 2006.231.08:02:21.19#ibcon#read 6, iclass 16, count 0 2006.231.08:02:21.19#ibcon#end of sib2, iclass 16, count 0 2006.231.08:02:21.19#ibcon#*mode == 0, iclass 16, count 0 2006.231.08:02:21.19#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.08:02:21.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:02:21.20#ibcon#*before write, iclass 16, count 0 2006.231.08:02:21.20#ibcon#enter sib2, iclass 16, count 0 2006.231.08:02:21.20#ibcon#flushed, iclass 16, count 0 2006.231.08:02:21.20#ibcon#about to write, iclass 16, count 0 2006.231.08:02:21.20#ibcon#wrote, iclass 16, count 0 2006.231.08:02:21.20#ibcon#about to read 3, iclass 16, count 0 2006.231.08:02:21.23#ibcon#read 3, iclass 16, count 0 2006.231.08:02:21.23#ibcon#about to read 4, iclass 16, count 0 2006.231.08:02:21.23#ibcon#read 4, iclass 16, count 0 2006.231.08:02:21.23#ibcon#about to read 5, iclass 16, count 0 2006.231.08:02:21.23#ibcon#read 5, iclass 16, count 0 2006.231.08:02:21.23#ibcon#about to read 6, iclass 16, count 0 2006.231.08:02:21.23#ibcon#read 6, iclass 16, count 0 2006.231.08:02:21.23#ibcon#end of sib2, iclass 16, count 0 2006.231.08:02:21.23#ibcon#*after write, iclass 16, count 0 2006.231.08:02:21.23#ibcon#*before return 0, iclass 16, count 0 2006.231.08:02:21.24#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:02:21.24#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:02:21.24#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.08:02:21.24#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.08:02:21.24$vc4f8/vb=3,4 2006.231.08:02:21.24#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.231.08:02:21.24#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.231.08:02:21.24#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:21.24#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:02:21.29#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:02:21.29#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:02:21.29#ibcon#enter wrdev, iclass 18, count 2 2006.231.08:02:21.29#ibcon#first serial, iclass 18, count 2 2006.231.08:02:21.29#ibcon#enter sib2, iclass 18, count 2 2006.231.08:02:21.29#ibcon#flushed, iclass 18, count 2 2006.231.08:02:21.29#ibcon#about to write, iclass 18, count 2 2006.231.08:02:21.29#ibcon#wrote, iclass 18, count 2 2006.231.08:02:21.29#ibcon#about to read 3, iclass 18, count 2 2006.231.08:02:21.31#ibcon#read 3, iclass 18, count 2 2006.231.08:02:21.31#ibcon#about to read 4, iclass 18, count 2 2006.231.08:02:21.31#ibcon#read 4, iclass 18, count 2 2006.231.08:02:21.31#ibcon#about to read 5, iclass 18, count 2 2006.231.08:02:21.31#ibcon#read 5, iclass 18, count 2 2006.231.08:02:21.31#ibcon#about to read 6, iclass 18, count 2 2006.231.08:02:21.31#ibcon#read 6, iclass 18, count 2 2006.231.08:02:21.31#ibcon#end of sib2, iclass 18, count 2 2006.231.08:02:21.31#ibcon#*mode == 0, iclass 18, count 2 2006.231.08:02:21.31#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.231.08:02:21.31#ibcon#[27=AT03-04\r\n] 2006.231.08:02:21.32#ibcon#*before write, iclass 18, count 2 2006.231.08:02:21.32#ibcon#enter sib2, iclass 18, count 2 2006.231.08:02:21.32#ibcon#flushed, iclass 18, count 2 2006.231.08:02:21.32#ibcon#about to write, iclass 18, count 2 2006.231.08:02:21.32#ibcon#wrote, iclass 18, count 2 2006.231.08:02:21.32#ibcon#about to read 3, iclass 18, count 2 2006.231.08:02:21.34#ibcon#read 3, iclass 18, count 2 2006.231.08:02:21.34#ibcon#about to read 4, iclass 18, count 2 2006.231.08:02:21.34#ibcon#read 4, iclass 18, count 2 2006.231.08:02:21.34#ibcon#about to read 5, iclass 18, count 2 2006.231.08:02:21.34#ibcon#read 5, iclass 18, count 2 2006.231.08:02:21.34#ibcon#about to read 6, iclass 18, count 2 2006.231.08:02:21.34#ibcon#read 6, iclass 18, count 2 2006.231.08:02:21.34#ibcon#end of sib2, iclass 18, count 2 2006.231.08:02:21.34#ibcon#*after write, iclass 18, count 2 2006.231.08:02:21.34#ibcon#*before return 0, iclass 18, count 2 2006.231.08:02:21.35#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:02:21.35#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:02:21.35#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.231.08:02:21.35#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:21.35#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:02:21.46#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:02:21.46#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:02:21.46#ibcon#enter wrdev, iclass 18, count 0 2006.231.08:02:21.46#ibcon#first serial, iclass 18, count 0 2006.231.08:02:21.46#ibcon#enter sib2, iclass 18, count 0 2006.231.08:02:21.47#ibcon#flushed, iclass 18, count 0 2006.231.08:02:21.47#ibcon#about to write, iclass 18, count 0 2006.231.08:02:21.47#ibcon#wrote, iclass 18, count 0 2006.231.08:02:21.47#ibcon#about to read 3, iclass 18, count 0 2006.231.08:02:21.48#ibcon#read 3, iclass 18, count 0 2006.231.08:02:21.48#ibcon#about to read 4, iclass 18, count 0 2006.231.08:02:21.48#ibcon#read 4, iclass 18, count 0 2006.231.08:02:21.48#ibcon#about to read 5, iclass 18, count 0 2006.231.08:02:21.48#ibcon#read 5, iclass 18, count 0 2006.231.08:02:21.48#ibcon#about to read 6, iclass 18, count 0 2006.231.08:02:21.48#ibcon#read 6, iclass 18, count 0 2006.231.08:02:21.48#ibcon#end of sib2, iclass 18, count 0 2006.231.08:02:21.48#ibcon#*mode == 0, iclass 18, count 0 2006.231.08:02:21.48#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.08:02:21.49#ibcon#[27=USB\r\n] 2006.231.08:02:21.49#ibcon#*before write, iclass 18, count 0 2006.231.08:02:21.49#ibcon#enter sib2, iclass 18, count 0 2006.231.08:02:21.49#ibcon#flushed, iclass 18, count 0 2006.231.08:02:21.49#ibcon#about to write, iclass 18, count 0 2006.231.08:02:21.49#ibcon#wrote, iclass 18, count 0 2006.231.08:02:21.49#ibcon#about to read 3, iclass 18, count 0 2006.231.08:02:21.51#ibcon#read 3, iclass 18, count 0 2006.231.08:02:21.51#ibcon#about to read 4, iclass 18, count 0 2006.231.08:02:21.51#ibcon#read 4, iclass 18, count 0 2006.231.08:02:21.51#ibcon#about to read 5, iclass 18, count 0 2006.231.08:02:21.51#ibcon#read 5, iclass 18, count 0 2006.231.08:02:21.51#ibcon#about to read 6, iclass 18, count 0 2006.231.08:02:21.51#ibcon#read 6, iclass 18, count 0 2006.231.08:02:21.51#ibcon#end of sib2, iclass 18, count 0 2006.231.08:02:21.51#ibcon#*after write, iclass 18, count 0 2006.231.08:02:21.51#ibcon#*before return 0, iclass 18, count 0 2006.231.08:02:21.52#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:02:21.52#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:02:21.52#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.08:02:21.52#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.08:02:21.52$vc4f8/vblo=4,712.99 2006.231.08:02:21.52#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.231.08:02:21.52#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.231.08:02:21.52#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:21.52#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:02:21.52#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:02:21.52#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:02:21.52#ibcon#enter wrdev, iclass 20, count 0 2006.231.08:02:21.52#ibcon#first serial, iclass 20, count 0 2006.231.08:02:21.52#ibcon#enter sib2, iclass 20, count 0 2006.231.08:02:21.52#ibcon#flushed, iclass 20, count 0 2006.231.08:02:21.52#ibcon#about to write, iclass 20, count 0 2006.231.08:02:21.52#ibcon#wrote, iclass 20, count 0 2006.231.08:02:21.52#ibcon#about to read 3, iclass 20, count 0 2006.231.08:02:21.53#ibcon#read 3, iclass 20, count 0 2006.231.08:02:21.53#ibcon#about to read 4, iclass 20, count 0 2006.231.08:02:21.53#ibcon#read 4, iclass 20, count 0 2006.231.08:02:21.53#ibcon#about to read 5, iclass 20, count 0 2006.231.08:02:21.53#ibcon#read 5, iclass 20, count 0 2006.231.08:02:21.53#ibcon#about to read 6, iclass 20, count 0 2006.231.08:02:21.53#ibcon#read 6, iclass 20, count 0 2006.231.08:02:21.53#ibcon#end of sib2, iclass 20, count 0 2006.231.08:02:21.53#ibcon#*mode == 0, iclass 20, count 0 2006.231.08:02:21.53#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.08:02:21.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:02:21.53#ibcon#*before write, iclass 20, count 0 2006.231.08:02:21.54#ibcon#enter sib2, iclass 20, count 0 2006.231.08:02:21.54#ibcon#flushed, iclass 20, count 0 2006.231.08:02:21.54#ibcon#about to write, iclass 20, count 0 2006.231.08:02:21.54#ibcon#wrote, iclass 20, count 0 2006.231.08:02:21.54#ibcon#about to read 3, iclass 20, count 0 2006.231.08:02:21.57#ibcon#read 3, iclass 20, count 0 2006.231.08:02:21.57#ibcon#about to read 4, iclass 20, count 0 2006.231.08:02:21.57#ibcon#read 4, iclass 20, count 0 2006.231.08:02:21.57#ibcon#about to read 5, iclass 20, count 0 2006.231.08:02:21.57#ibcon#read 5, iclass 20, count 0 2006.231.08:02:21.57#ibcon#about to read 6, iclass 20, count 0 2006.231.08:02:21.57#ibcon#read 6, iclass 20, count 0 2006.231.08:02:21.57#ibcon#end of sib2, iclass 20, count 0 2006.231.08:02:21.57#ibcon#*after write, iclass 20, count 0 2006.231.08:02:21.57#ibcon#*before return 0, iclass 20, count 0 2006.231.08:02:21.58#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:02:21.58#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:02:21.58#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.08:02:21.58#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.08:02:21.58$vc4f8/vb=4,4 2006.231.08:02:21.58#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.231.08:02:21.58#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.231.08:02:21.58#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:21.58#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:02:21.58#abcon#<5=/06 3.8 6.8 30.53 861004.5\r\n> 2006.231.08:02:21.60#abcon#{5=INTERFACE CLEAR} 2006.231.08:02:21.63#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:02:21.63#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:02:21.63#ibcon#enter wrdev, iclass 23, count 2 2006.231.08:02:21.63#ibcon#first serial, iclass 23, count 2 2006.231.08:02:21.63#ibcon#enter sib2, iclass 23, count 2 2006.231.08:02:21.63#ibcon#flushed, iclass 23, count 2 2006.231.08:02:21.63#ibcon#about to write, iclass 23, count 2 2006.231.08:02:21.63#ibcon#wrote, iclass 23, count 2 2006.231.08:02:21.63#ibcon#about to read 3, iclass 23, count 2 2006.231.08:02:21.65#ibcon#read 3, iclass 23, count 2 2006.231.08:02:21.65#ibcon#about to read 4, iclass 23, count 2 2006.231.08:02:21.65#ibcon#read 4, iclass 23, count 2 2006.231.08:02:21.65#ibcon#about to read 5, iclass 23, count 2 2006.231.08:02:21.65#ibcon#read 5, iclass 23, count 2 2006.231.08:02:21.65#ibcon#about to read 6, iclass 23, count 2 2006.231.08:02:21.65#ibcon#read 6, iclass 23, count 2 2006.231.08:02:21.65#ibcon#end of sib2, iclass 23, count 2 2006.231.08:02:21.65#ibcon#*mode == 0, iclass 23, count 2 2006.231.08:02:21.65#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.231.08:02:21.65#ibcon#[27=AT04-04\r\n] 2006.231.08:02:21.66#ibcon#*before write, iclass 23, count 2 2006.231.08:02:21.66#ibcon#enter sib2, iclass 23, count 2 2006.231.08:02:21.66#ibcon#flushed, iclass 23, count 2 2006.231.08:02:21.66#ibcon#about to write, iclass 23, count 2 2006.231.08:02:21.66#ibcon#wrote, iclass 23, count 2 2006.231.08:02:21.66#ibcon#about to read 3, iclass 23, count 2 2006.231.08:02:21.66#abcon#[5=S1D000X0/0*\r\n] 2006.231.08:02:21.68#ibcon#read 3, iclass 23, count 2 2006.231.08:02:21.68#ibcon#about to read 4, iclass 23, count 2 2006.231.08:02:21.68#ibcon#read 4, iclass 23, count 2 2006.231.08:02:21.68#ibcon#about to read 5, iclass 23, count 2 2006.231.08:02:21.68#ibcon#read 5, iclass 23, count 2 2006.231.08:02:21.68#ibcon#about to read 6, iclass 23, count 2 2006.231.08:02:21.68#ibcon#read 6, iclass 23, count 2 2006.231.08:02:21.68#ibcon#end of sib2, iclass 23, count 2 2006.231.08:02:21.68#ibcon#*after write, iclass 23, count 2 2006.231.08:02:21.68#ibcon#*before return 0, iclass 23, count 2 2006.231.08:02:21.69#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:02:21.69#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:02:21.69#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.231.08:02:21.69#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:21.69#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:02:21.80#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:02:21.80#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:02:21.80#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:02:21.80#ibcon#first serial, iclass 23, count 0 2006.231.08:02:21.80#ibcon#enter sib2, iclass 23, count 0 2006.231.08:02:21.80#ibcon#flushed, iclass 23, count 0 2006.231.08:02:21.80#ibcon#about to write, iclass 23, count 0 2006.231.08:02:21.80#ibcon#wrote, iclass 23, count 0 2006.231.08:02:21.80#ibcon#about to read 3, iclass 23, count 0 2006.231.08:02:21.82#ibcon#read 3, iclass 23, count 0 2006.231.08:02:21.82#ibcon#about to read 4, iclass 23, count 0 2006.231.08:02:21.82#ibcon#read 4, iclass 23, count 0 2006.231.08:02:21.82#ibcon#about to read 5, iclass 23, count 0 2006.231.08:02:21.82#ibcon#read 5, iclass 23, count 0 2006.231.08:02:21.82#ibcon#about to read 6, iclass 23, count 0 2006.231.08:02:21.82#ibcon#read 6, iclass 23, count 0 2006.231.08:02:21.82#ibcon#end of sib2, iclass 23, count 0 2006.231.08:02:21.82#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:02:21.82#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:02:21.82#ibcon#[27=USB\r\n] 2006.231.08:02:21.82#ibcon#*before write, iclass 23, count 0 2006.231.08:02:21.83#ibcon#enter sib2, iclass 23, count 0 2006.231.08:02:21.83#ibcon#flushed, iclass 23, count 0 2006.231.08:02:21.83#ibcon#about to write, iclass 23, count 0 2006.231.08:02:21.83#ibcon#wrote, iclass 23, count 0 2006.231.08:02:21.83#ibcon#about to read 3, iclass 23, count 0 2006.231.08:02:21.85#ibcon#read 3, iclass 23, count 0 2006.231.08:02:21.85#ibcon#about to read 4, iclass 23, count 0 2006.231.08:02:21.85#ibcon#read 4, iclass 23, count 0 2006.231.08:02:21.85#ibcon#about to read 5, iclass 23, count 0 2006.231.08:02:21.85#ibcon#read 5, iclass 23, count 0 2006.231.08:02:21.85#ibcon#about to read 6, iclass 23, count 0 2006.231.08:02:21.85#ibcon#read 6, iclass 23, count 0 2006.231.08:02:21.85#ibcon#end of sib2, iclass 23, count 0 2006.231.08:02:21.85#ibcon#*after write, iclass 23, count 0 2006.231.08:02:21.85#ibcon#*before return 0, iclass 23, count 0 2006.231.08:02:21.86#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:02:21.86#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:02:21.86#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:02:21.86#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:02:21.86$vc4f8/vblo=5,744.99 2006.231.08:02:21.86#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.231.08:02:21.86#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.231.08:02:21.86#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:21.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:02:21.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:02:21.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:02:21.86#ibcon#enter wrdev, iclass 28, count 0 2006.231.08:02:21.86#ibcon#first serial, iclass 28, count 0 2006.231.08:02:21.86#ibcon#enter sib2, iclass 28, count 0 2006.231.08:02:21.86#ibcon#flushed, iclass 28, count 0 2006.231.08:02:21.86#ibcon#about to write, iclass 28, count 0 2006.231.08:02:21.86#ibcon#wrote, iclass 28, count 0 2006.231.08:02:21.86#ibcon#about to read 3, iclass 28, count 0 2006.231.08:02:21.87#ibcon#read 3, iclass 28, count 0 2006.231.08:02:21.87#ibcon#about to read 4, iclass 28, count 0 2006.231.08:02:21.87#ibcon#read 4, iclass 28, count 0 2006.231.08:02:21.87#ibcon#about to read 5, iclass 28, count 0 2006.231.08:02:21.87#ibcon#read 5, iclass 28, count 0 2006.231.08:02:21.87#ibcon#about to read 6, iclass 28, count 0 2006.231.08:02:21.87#ibcon#read 6, iclass 28, count 0 2006.231.08:02:21.87#ibcon#end of sib2, iclass 28, count 0 2006.231.08:02:21.87#ibcon#*mode == 0, iclass 28, count 0 2006.231.08:02:21.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.08:02:21.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:02:21.88#ibcon#*before write, iclass 28, count 0 2006.231.08:02:21.88#ibcon#enter sib2, iclass 28, count 0 2006.231.08:02:21.88#ibcon#flushed, iclass 28, count 0 2006.231.08:02:21.88#ibcon#about to write, iclass 28, count 0 2006.231.08:02:21.88#ibcon#wrote, iclass 28, count 0 2006.231.08:02:21.88#ibcon#about to read 3, iclass 28, count 0 2006.231.08:02:21.91#ibcon#read 3, iclass 28, count 0 2006.231.08:02:21.91#ibcon#about to read 4, iclass 28, count 0 2006.231.08:02:21.92#ibcon#read 4, iclass 28, count 0 2006.231.08:02:21.92#ibcon#about to read 5, iclass 28, count 0 2006.231.08:02:21.92#ibcon#read 5, iclass 28, count 0 2006.231.08:02:21.92#ibcon#about to read 6, iclass 28, count 0 2006.231.08:02:21.92#ibcon#read 6, iclass 28, count 0 2006.231.08:02:21.92#ibcon#end of sib2, iclass 28, count 0 2006.231.08:02:21.92#ibcon#*after write, iclass 28, count 0 2006.231.08:02:21.92#ibcon#*before return 0, iclass 28, count 0 2006.231.08:02:21.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:02:21.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:02:21.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.08:02:21.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.08:02:21.92$vc4f8/vb=5,3 2006.231.08:02:21.92#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.08:02:21.92#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.08:02:21.92#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:21.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:02:21.97#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:02:21.97#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:02:21.97#ibcon#enter wrdev, iclass 30, count 2 2006.231.08:02:21.97#ibcon#first serial, iclass 30, count 2 2006.231.08:02:21.97#ibcon#enter sib2, iclass 30, count 2 2006.231.08:02:21.97#ibcon#flushed, iclass 30, count 2 2006.231.08:02:21.97#ibcon#about to write, iclass 30, count 2 2006.231.08:02:21.97#ibcon#wrote, iclass 30, count 2 2006.231.08:02:21.97#ibcon#about to read 3, iclass 30, count 2 2006.231.08:02:21.99#ibcon#read 3, iclass 30, count 2 2006.231.08:02:21.99#ibcon#about to read 4, iclass 30, count 2 2006.231.08:02:21.99#ibcon#read 4, iclass 30, count 2 2006.231.08:02:21.99#ibcon#about to read 5, iclass 30, count 2 2006.231.08:02:21.99#ibcon#read 5, iclass 30, count 2 2006.231.08:02:21.99#ibcon#about to read 6, iclass 30, count 2 2006.231.08:02:21.99#ibcon#read 6, iclass 30, count 2 2006.231.08:02:21.99#ibcon#end of sib2, iclass 30, count 2 2006.231.08:02:21.99#ibcon#*mode == 0, iclass 30, count 2 2006.231.08:02:21.99#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.08:02:21.99#ibcon#[27=AT05-03\r\n] 2006.231.08:02:22.00#ibcon#*before write, iclass 30, count 2 2006.231.08:02:22.00#ibcon#enter sib2, iclass 30, count 2 2006.231.08:02:22.00#ibcon#flushed, iclass 30, count 2 2006.231.08:02:22.00#ibcon#about to write, iclass 30, count 2 2006.231.08:02:22.00#ibcon#wrote, iclass 30, count 2 2006.231.08:02:22.00#ibcon#about to read 3, iclass 30, count 2 2006.231.08:02:22.02#ibcon#read 3, iclass 30, count 2 2006.231.08:02:22.02#ibcon#about to read 4, iclass 30, count 2 2006.231.08:02:22.02#ibcon#read 4, iclass 30, count 2 2006.231.08:02:22.02#ibcon#about to read 5, iclass 30, count 2 2006.231.08:02:22.02#ibcon#read 5, iclass 30, count 2 2006.231.08:02:22.02#ibcon#about to read 6, iclass 30, count 2 2006.231.08:02:22.02#ibcon#read 6, iclass 30, count 2 2006.231.08:02:22.02#ibcon#end of sib2, iclass 30, count 2 2006.231.08:02:22.02#ibcon#*after write, iclass 30, count 2 2006.231.08:02:22.02#ibcon#*before return 0, iclass 30, count 2 2006.231.08:02:22.02#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:02:22.03#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:02:22.03#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.08:02:22.03#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:22.03#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:02:22.14#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:02:22.14#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:02:22.15#ibcon#enter wrdev, iclass 30, count 0 2006.231.08:02:22.15#ibcon#first serial, iclass 30, count 0 2006.231.08:02:22.15#ibcon#enter sib2, iclass 30, count 0 2006.231.08:02:22.15#ibcon#flushed, iclass 30, count 0 2006.231.08:02:22.15#ibcon#about to write, iclass 30, count 0 2006.231.08:02:22.15#ibcon#wrote, iclass 30, count 0 2006.231.08:02:22.15#ibcon#about to read 3, iclass 30, count 0 2006.231.08:02:22.16#ibcon#read 3, iclass 30, count 0 2006.231.08:02:22.16#ibcon#about to read 4, iclass 30, count 0 2006.231.08:02:22.16#ibcon#read 4, iclass 30, count 0 2006.231.08:02:22.16#ibcon#about to read 5, iclass 30, count 0 2006.231.08:02:22.16#ibcon#read 5, iclass 30, count 0 2006.231.08:02:22.16#ibcon#about to read 6, iclass 30, count 0 2006.231.08:02:22.16#ibcon#read 6, iclass 30, count 0 2006.231.08:02:22.16#ibcon#end of sib2, iclass 30, count 0 2006.231.08:02:22.16#ibcon#*mode == 0, iclass 30, count 0 2006.231.08:02:22.16#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.08:02:22.16#ibcon#[27=USB\r\n] 2006.231.08:02:22.16#ibcon#*before write, iclass 30, count 0 2006.231.08:02:22.16#ibcon#enter sib2, iclass 30, count 0 2006.231.08:02:22.17#ibcon#flushed, iclass 30, count 0 2006.231.08:02:22.17#ibcon#about to write, iclass 30, count 0 2006.231.08:02:22.17#ibcon#wrote, iclass 30, count 0 2006.231.08:02:22.17#ibcon#about to read 3, iclass 30, count 0 2006.231.08:02:22.19#ibcon#read 3, iclass 30, count 0 2006.231.08:02:22.19#ibcon#about to read 4, iclass 30, count 0 2006.231.08:02:22.19#ibcon#read 4, iclass 30, count 0 2006.231.08:02:22.19#ibcon#about to read 5, iclass 30, count 0 2006.231.08:02:22.19#ibcon#read 5, iclass 30, count 0 2006.231.08:02:22.19#ibcon#about to read 6, iclass 30, count 0 2006.231.08:02:22.19#ibcon#read 6, iclass 30, count 0 2006.231.08:02:22.19#ibcon#end of sib2, iclass 30, count 0 2006.231.08:02:22.19#ibcon#*after write, iclass 30, count 0 2006.231.08:02:22.19#ibcon#*before return 0, iclass 30, count 0 2006.231.08:02:22.20#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:02:22.20#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:02:22.20#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.08:02:22.20#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.08:02:22.20$vc4f8/vblo=6,752.99 2006.231.08:02:22.20#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.08:02:22.20#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.08:02:22.20#ibcon#ireg 17 cls_cnt 0 2006.231.08:02:22.20#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:02:22.20#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:02:22.20#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:02:22.20#ibcon#enter wrdev, iclass 32, count 0 2006.231.08:02:22.20#ibcon#first serial, iclass 32, count 0 2006.231.08:02:22.20#ibcon#enter sib2, iclass 32, count 0 2006.231.08:02:22.20#ibcon#flushed, iclass 32, count 0 2006.231.08:02:22.20#ibcon#about to write, iclass 32, count 0 2006.231.08:02:22.20#ibcon#wrote, iclass 32, count 0 2006.231.08:02:22.20#ibcon#about to read 3, iclass 32, count 0 2006.231.08:02:22.21#ibcon#read 3, iclass 32, count 0 2006.231.08:02:22.21#ibcon#about to read 4, iclass 32, count 0 2006.231.08:02:22.21#ibcon#read 4, iclass 32, count 0 2006.231.08:02:22.21#ibcon#about to read 5, iclass 32, count 0 2006.231.08:02:22.21#ibcon#read 5, iclass 32, count 0 2006.231.08:02:22.21#ibcon#about to read 6, iclass 32, count 0 2006.231.08:02:22.21#ibcon#read 6, iclass 32, count 0 2006.231.08:02:22.21#ibcon#end of sib2, iclass 32, count 0 2006.231.08:02:22.21#ibcon#*mode == 0, iclass 32, count 0 2006.231.08:02:22.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.08:02:22.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:02:22.22#ibcon#*before write, iclass 32, count 0 2006.231.08:02:22.22#ibcon#enter sib2, iclass 32, count 0 2006.231.08:02:22.22#ibcon#flushed, iclass 32, count 0 2006.231.08:02:22.22#ibcon#about to write, iclass 32, count 0 2006.231.08:02:22.22#ibcon#wrote, iclass 32, count 0 2006.231.08:02:22.22#ibcon#about to read 3, iclass 32, count 0 2006.231.08:02:22.25#ibcon#read 3, iclass 32, count 0 2006.231.08:02:22.25#ibcon#about to read 4, iclass 32, count 0 2006.231.08:02:22.25#ibcon#read 4, iclass 32, count 0 2006.231.08:02:22.25#ibcon#about to read 5, iclass 32, count 0 2006.231.08:02:22.25#ibcon#read 5, iclass 32, count 0 2006.231.08:02:22.25#ibcon#about to read 6, iclass 32, count 0 2006.231.08:02:22.25#ibcon#read 6, iclass 32, count 0 2006.231.08:02:22.25#ibcon#end of sib2, iclass 32, count 0 2006.231.08:02:22.25#ibcon#*after write, iclass 32, count 0 2006.231.08:02:22.25#ibcon#*before return 0, iclass 32, count 0 2006.231.08:02:22.26#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:02:22.26#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:02:22.26#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.08:02:22.26#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.08:02:22.26$vc4f8/vb=6,4 2006.231.08:02:22.26#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.08:02:22.26#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.08:02:22.26#ibcon#ireg 11 cls_cnt 2 2006.231.08:02:22.26#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:02:22.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:02:22.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:02:22.31#ibcon#enter wrdev, iclass 34, count 2 2006.231.08:02:22.31#ibcon#first serial, iclass 34, count 2 2006.231.08:02:22.31#ibcon#enter sib2, iclass 34, count 2 2006.231.08:02:22.31#ibcon#flushed, iclass 34, count 2 2006.231.08:02:22.31#ibcon#about to write, iclass 34, count 2 2006.231.08:02:22.31#ibcon#wrote, iclass 34, count 2 2006.231.08:02:22.31#ibcon#about to read 3, iclass 34, count 2 2006.231.08:02:22.33#ibcon#read 3, iclass 34, count 2 2006.231.08:02:22.33#ibcon#about to read 4, iclass 34, count 2 2006.231.08:02:22.33#ibcon#read 4, iclass 34, count 2 2006.231.08:02:22.33#ibcon#about to read 5, iclass 34, count 2 2006.231.08:02:22.33#ibcon#read 5, iclass 34, count 2 2006.231.08:02:22.33#ibcon#about to read 6, iclass 34, count 2 2006.231.08:02:22.33#ibcon#read 6, iclass 34, count 2 2006.231.08:02:22.33#ibcon#end of sib2, iclass 34, count 2 2006.231.08:02:22.33#ibcon#*mode == 0, iclass 34, count 2 2006.231.08:02:22.33#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.08:02:22.33#ibcon#[27=AT06-04\r\n] 2006.231.08:02:22.34#ibcon#*before write, iclass 34, count 2 2006.231.08:02:22.34#ibcon#enter sib2, iclass 34, count 2 2006.231.08:02:22.34#ibcon#flushed, iclass 34, count 2 2006.231.08:02:22.34#ibcon#about to write, iclass 34, count 2 2006.231.08:02:22.34#ibcon#wrote, iclass 34, count 2 2006.231.08:02:22.34#ibcon#about to read 3, iclass 34, count 2 2006.231.08:02:22.36#ibcon#read 3, iclass 34, count 2 2006.231.08:02:22.36#ibcon#about to read 4, iclass 34, count 2 2006.231.08:02:22.36#ibcon#read 4, iclass 34, count 2 2006.231.08:02:22.36#ibcon#about to read 5, iclass 34, count 2 2006.231.08:02:22.36#ibcon#read 5, iclass 34, count 2 2006.231.08:02:22.36#ibcon#about to read 6, iclass 34, count 2 2006.231.08:02:22.36#ibcon#read 6, iclass 34, count 2 2006.231.08:02:22.36#ibcon#end of sib2, iclass 34, count 2 2006.231.08:02:22.36#ibcon#*after write, iclass 34, count 2 2006.231.08:02:22.36#ibcon#*before return 0, iclass 34, count 2 2006.231.08:02:22.37#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:02:22.37#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:02:22.37#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.08:02:22.37#ibcon#ireg 7 cls_cnt 0 2006.231.08:02:22.37#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:02:22.48#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:02:22.48#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:02:22.48#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:02:22.48#ibcon#first serial, iclass 34, count 0 2006.231.08:02:22.48#ibcon#enter sib2, iclass 34, count 0 2006.231.08:02:22.48#ibcon#flushed, iclass 34, count 0 2006.231.08:02:22.48#ibcon#about to write, iclass 34, count 0 2006.231.08:02:22.48#ibcon#wrote, iclass 34, count 0 2006.231.08:02:22.48#ibcon#about to read 3, iclass 34, count 0 2006.231.08:02:22.50#ibcon#read 3, iclass 34, count 0 2006.231.08:02:22.50#ibcon#about to read 4, iclass 34, count 0 2006.231.08:02:22.50#ibcon#read 4, iclass 34, count 0 2006.231.08:02:22.50#ibcon#about to read 5, iclass 34, count 0 2006.231.08:02:22.50#ibcon#read 5, iclass 34, count 0 2006.231.08:02:22.50#ibcon#about to read 6, iclass 34, count 0 2006.231.08:02:22.50#ibcon#read 6, iclass 34, count 0 2006.231.08:02:22.50#ibcon#end of sib2, iclass 34, count 0 2006.231.08:02:22.50#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:02:22.50#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:02:22.51#ibcon#[27=USB\r\n] 2006.231.08:02:22.51#ibcon#*before write, iclass 34, count 0 2006.231.08:02:22.51#ibcon#enter sib2, iclass 34, count 0 2006.231.08:02:22.51#ibcon#flushed, iclass 34, count 0 2006.231.08:02:22.51#ibcon#about to write, iclass 34, count 0 2006.231.08:02:22.51#ibcon#wrote, iclass 34, count 0 2006.231.08:02:22.51#ibcon#about to read 3, iclass 34, count 0 2006.231.08:02:22.53#ibcon#read 3, iclass 34, count 0 2006.231.08:02:22.53#ibcon#about to read 4, iclass 34, count 0 2006.231.08:02:22.53#ibcon#read 4, iclass 34, count 0 2006.231.08:02:22.53#ibcon#about to read 5, iclass 34, count 0 2006.231.08:02:22.53#ibcon#read 5, iclass 34, count 0 2006.231.08:02:22.53#ibcon#about to read 6, iclass 34, count 0 2006.231.08:02:22.53#ibcon#read 6, iclass 34, count 0 2006.231.08:02:22.53#ibcon#end of sib2, iclass 34, count 0 2006.231.08:02:22.53#ibcon#*after write, iclass 34, count 0 2006.231.08:02:22.53#ibcon#*before return 0, iclass 34, count 0 2006.231.08:02:22.54#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:02:22.54#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:02:22.54#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:02:22.54#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:02:22.54$vc4f8/vabw=wide 2006.231.08:02:22.54#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.08:02:22.54#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.08:02:22.54#ibcon#ireg 8 cls_cnt 0 2006.231.08:02:22.54#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:02:22.54#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:02:22.54#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:02:22.54#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:02:22.54#ibcon#first serial, iclass 36, count 0 2006.231.08:02:22.54#ibcon#enter sib2, iclass 36, count 0 2006.231.08:02:22.54#ibcon#flushed, iclass 36, count 0 2006.231.08:02:22.54#ibcon#about to write, iclass 36, count 0 2006.231.08:02:22.54#ibcon#wrote, iclass 36, count 0 2006.231.08:02:22.54#ibcon#about to read 3, iclass 36, count 0 2006.231.08:02:22.55#ibcon#read 3, iclass 36, count 0 2006.231.08:02:22.55#ibcon#about to read 4, iclass 36, count 0 2006.231.08:02:22.55#ibcon#read 4, iclass 36, count 0 2006.231.08:02:22.55#ibcon#about to read 5, iclass 36, count 0 2006.231.08:02:22.55#ibcon#read 5, iclass 36, count 0 2006.231.08:02:22.55#ibcon#about to read 6, iclass 36, count 0 2006.231.08:02:22.55#ibcon#read 6, iclass 36, count 0 2006.231.08:02:22.55#ibcon#end of sib2, iclass 36, count 0 2006.231.08:02:22.55#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:02:22.55#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:02:22.55#ibcon#[25=BW32\r\n] 2006.231.08:02:22.55#ibcon#*before write, iclass 36, count 0 2006.231.08:02:22.56#ibcon#enter sib2, iclass 36, count 0 2006.231.08:02:22.56#ibcon#flushed, iclass 36, count 0 2006.231.08:02:22.56#ibcon#about to write, iclass 36, count 0 2006.231.08:02:22.56#ibcon#wrote, iclass 36, count 0 2006.231.08:02:22.56#ibcon#about to read 3, iclass 36, count 0 2006.231.08:02:22.58#ibcon#read 3, iclass 36, count 0 2006.231.08:02:22.58#ibcon#about to read 4, iclass 36, count 0 2006.231.08:02:22.58#ibcon#read 4, iclass 36, count 0 2006.231.08:02:22.58#ibcon#about to read 5, iclass 36, count 0 2006.231.08:02:22.58#ibcon#read 5, iclass 36, count 0 2006.231.08:02:22.58#ibcon#about to read 6, iclass 36, count 0 2006.231.08:02:22.58#ibcon#read 6, iclass 36, count 0 2006.231.08:02:22.58#ibcon#end of sib2, iclass 36, count 0 2006.231.08:02:22.58#ibcon#*after write, iclass 36, count 0 2006.231.08:02:22.58#ibcon#*before return 0, iclass 36, count 0 2006.231.08:02:22.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:02:22.59#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:02:22.59#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:02:22.59#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:02:22.59$vc4f8/vbbw=wide 2006.231.08:02:22.59#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.08:02:22.59#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.08:02:22.59#ibcon#ireg 8 cls_cnt 0 2006.231.08:02:22.59#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:02:22.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:02:22.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:02:22.65#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:02:22.65#ibcon#first serial, iclass 38, count 0 2006.231.08:02:22.65#ibcon#enter sib2, iclass 38, count 0 2006.231.08:02:22.65#ibcon#flushed, iclass 38, count 0 2006.231.08:02:22.65#ibcon#about to write, iclass 38, count 0 2006.231.08:02:22.65#ibcon#wrote, iclass 38, count 0 2006.231.08:02:22.65#ibcon#about to read 3, iclass 38, count 0 2006.231.08:02:22.67#ibcon#read 3, iclass 38, count 0 2006.231.08:02:22.67#ibcon#about to read 4, iclass 38, count 0 2006.231.08:02:22.67#ibcon#read 4, iclass 38, count 0 2006.231.08:02:22.67#ibcon#about to read 5, iclass 38, count 0 2006.231.08:02:22.67#ibcon#read 5, iclass 38, count 0 2006.231.08:02:22.67#ibcon#about to read 6, iclass 38, count 0 2006.231.08:02:22.67#ibcon#read 6, iclass 38, count 0 2006.231.08:02:22.67#ibcon#end of sib2, iclass 38, count 0 2006.231.08:02:22.67#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:02:22.67#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:02:22.67#ibcon#[27=BW32\r\n] 2006.231.08:02:22.68#ibcon#*before write, iclass 38, count 0 2006.231.08:02:22.68#ibcon#enter sib2, iclass 38, count 0 2006.231.08:02:22.68#ibcon#flushed, iclass 38, count 0 2006.231.08:02:22.68#ibcon#about to write, iclass 38, count 0 2006.231.08:02:22.68#ibcon#wrote, iclass 38, count 0 2006.231.08:02:22.68#ibcon#about to read 3, iclass 38, count 0 2006.231.08:02:22.70#ibcon#read 3, iclass 38, count 0 2006.231.08:02:22.70#ibcon#about to read 4, iclass 38, count 0 2006.231.08:02:22.70#ibcon#read 4, iclass 38, count 0 2006.231.08:02:22.70#ibcon#about to read 5, iclass 38, count 0 2006.231.08:02:22.70#ibcon#read 5, iclass 38, count 0 2006.231.08:02:22.70#ibcon#about to read 6, iclass 38, count 0 2006.231.08:02:22.70#ibcon#read 6, iclass 38, count 0 2006.231.08:02:22.70#ibcon#end of sib2, iclass 38, count 0 2006.231.08:02:22.70#ibcon#*after write, iclass 38, count 0 2006.231.08:02:22.70#ibcon#*before return 0, iclass 38, count 0 2006.231.08:02:22.70#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:02:22.71#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:02:22.71#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:02:22.71#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:02:22.71$4f8m12a/ifd4f 2006.231.08:02:22.71$ifd4f/lo= 2006.231.08:02:22.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:02:22.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:02:22.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:02:22.71$ifd4f/patch= 2006.231.08:02:22.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:02:22.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:02:22.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:02:22.71$4f8m12a/"form=m,16.000,1:2 2006.231.08:02:22.71$4f8m12a/"tpicd 2006.231.08:02:22.71$4f8m12a/echo=off 2006.231.08:02:22.71$4f8m12a/xlog=off 2006.231.08:02:22.71:!2006.231.08:02:50 2006.231.08:02:34.14#trakl#Source acquired 2006.231.08:02:35.15#flagr#flagr/antenna,acquired 2006.231.08:02:50.02:preob 2006.231.08:02:51.15/onsource/TRACKING 2006.231.08:02:51.15:!2006.231.08:03:00 2006.231.08:03:00.02:data_valid=on 2006.231.08:03:00.02:midob 2006.231.08:03:01.15/onsource/TRACKING 2006.231.08:03:01.15/wx/30.53,1004.5,86 2006.231.08:03:01.30/cable/+6.3738E-03 2006.231.08:03:02.39/va/01,08,usb,yes,30,31 2006.231.08:03:02.39/va/02,07,usb,yes,30,31 2006.231.08:03:02.39/va/03,08,usb,yes,22,23 2006.231.08:03:02.39/va/04,07,usb,yes,31,34 2006.231.08:03:02.39/va/05,07,usb,yes,34,36 2006.231.08:03:02.39/va/06,06,usb,yes,33,33 2006.231.08:03:02.39/va/07,06,usb,yes,34,34 2006.231.08:03:02.39/va/08,06,usb,yes,36,36 2006.231.08:03:02.62/valo/01,532.99,yes,locked 2006.231.08:03:02.62/valo/02,572.99,yes,locked 2006.231.08:03:02.62/valo/03,672.99,yes,locked 2006.231.08:03:02.62/valo/04,832.99,yes,locked 2006.231.08:03:02.62/valo/05,652.99,yes,locked 2006.231.08:03:02.62/valo/06,772.99,yes,locked 2006.231.08:03:02.62/valo/07,832.99,yes,locked 2006.231.08:03:02.62/valo/08,852.99,yes,locked 2006.231.08:03:03.71/vb/01,04,usb,yes,31,29 2006.231.08:03:03.71/vb/02,04,usb,yes,32,34 2006.231.08:03:03.71/vb/03,04,usb,yes,29,33 2006.231.08:03:03.71/vb/04,04,usb,yes,30,30 2006.231.08:03:03.71/vb/05,03,usb,yes,35,40 2006.231.08:03:03.71/vb/06,04,usb,yes,29,32 2006.231.08:03:03.71/vb/07,04,usb,yes,31,31 2006.231.08:03:03.71/vb/08,04,usb,yes,29,32 2006.231.08:03:03.95/vblo/01,632.99,yes,locked 2006.231.08:03:03.95/vblo/02,640.99,yes,locked 2006.231.08:03:03.95/vblo/03,656.99,yes,locked 2006.231.08:03:03.95/vblo/04,712.99,yes,locked 2006.231.08:03:03.95/vblo/05,744.99,yes,locked 2006.231.08:03:03.95/vblo/06,752.99,yes,locked 2006.231.08:03:03.95/vblo/07,734.99,yes,locked 2006.231.08:03:03.95/vblo/08,744.99,yes,locked 2006.231.08:03:04.10/vabw/8 2006.231.08:03:04.25/vbbw/8 2006.231.08:03:04.34/xfe/off,on,12.5 2006.231.08:03:04.72/ifatt/23,28,28,28 2006.231.08:03:05.07/fmout-gps/S +4.45E-07 2006.231.08:03:05.12:!2006.231.08:04:00 2006.231.08:04:00.00:data_valid=off 2006.231.08:04:00.01:postob 2006.231.08:04:00.15/cable/+6.3720E-03 2006.231.08:04:00.15/wx/30.53,1004.5,85 2006.231.08:04:01.07/fmout-gps/S +4.46E-07 2006.231.08:04:01.08:scan_name=231-0804,k06231,60 2006.231.08:04:01.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.231.08:04:02.15#flagr#flagr/antenna,new-source 2006.231.08:04:02.15:checkk5 2006.231.08:04:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:04:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:04:03.27/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:04:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:04:04.01/chk_obsdata//k5ts1/T2310803??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:04:04.38/chk_obsdata//k5ts2/T2310803??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:04:04.76/chk_obsdata//k5ts3/T2310803??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:04:05.12/chk_obsdata//k5ts4/T2310803??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:04:05.81/k5log//k5ts1_log_newline 2006.231.08:04:06.49/k5log//k5ts2_log_newline 2006.231.08:04:07.18/k5log//k5ts3_log_newline 2006.231.08:04:07.87/k5log//k5ts4_log_newline 2006.231.08:04:07.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:04:07.89:4f8m12a=2 2006.231.08:04:07.89$4f8m12a/echo=on 2006.231.08:04:07.89$4f8m12a/pcalon 2006.231.08:04:07.89$pcalon/"no phase cal control is implemented here 2006.231.08:04:07.89$4f8m12a/"tpicd=stop 2006.231.08:04:07.89$4f8m12a/vc4f8 2006.231.08:04:07.89$vc4f8/valo=1,532.99 2006.231.08:04:07.90#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.08:04:07.90#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.08:04:07.90#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:07.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:04:07.90#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:04:07.90#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:04:07.90#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:04:07.90#ibcon#first serial, iclass 7, count 0 2006.231.08:04:07.90#ibcon#enter sib2, iclass 7, count 0 2006.231.08:04:07.90#ibcon#flushed, iclass 7, count 0 2006.231.08:04:07.90#ibcon#about to write, iclass 7, count 0 2006.231.08:04:07.90#ibcon#wrote, iclass 7, count 0 2006.231.08:04:07.90#ibcon#about to read 3, iclass 7, count 0 2006.231.08:04:07.94#ibcon#read 3, iclass 7, count 0 2006.231.08:04:07.94#ibcon#about to read 4, iclass 7, count 0 2006.231.08:04:07.94#ibcon#read 4, iclass 7, count 0 2006.231.08:04:07.94#ibcon#about to read 5, iclass 7, count 0 2006.231.08:04:07.94#ibcon#read 5, iclass 7, count 0 2006.231.08:04:07.94#ibcon#about to read 6, iclass 7, count 0 2006.231.08:04:07.94#ibcon#read 6, iclass 7, count 0 2006.231.08:04:07.94#ibcon#end of sib2, iclass 7, count 0 2006.231.08:04:07.94#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:04:07.94#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:04:07.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:04:07.94#ibcon#*before write, iclass 7, count 0 2006.231.08:04:07.94#ibcon#enter sib2, iclass 7, count 0 2006.231.08:04:07.94#ibcon#flushed, iclass 7, count 0 2006.231.08:04:07.94#ibcon#about to write, iclass 7, count 0 2006.231.08:04:07.94#ibcon#wrote, iclass 7, count 0 2006.231.08:04:07.94#ibcon#about to read 3, iclass 7, count 0 2006.231.08:04:07.98#ibcon#read 3, iclass 7, count 0 2006.231.08:04:07.98#ibcon#about to read 4, iclass 7, count 0 2006.231.08:04:07.98#ibcon#read 4, iclass 7, count 0 2006.231.08:04:07.98#ibcon#about to read 5, iclass 7, count 0 2006.231.08:04:07.98#ibcon#read 5, iclass 7, count 0 2006.231.08:04:07.98#ibcon#about to read 6, iclass 7, count 0 2006.231.08:04:07.98#ibcon#read 6, iclass 7, count 0 2006.231.08:04:07.98#ibcon#end of sib2, iclass 7, count 0 2006.231.08:04:07.98#ibcon#*after write, iclass 7, count 0 2006.231.08:04:07.98#ibcon#*before return 0, iclass 7, count 0 2006.231.08:04:07.98#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:04:07.98#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:04:07.98#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:04:07.98#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:04:07.98$vc4f8/va=1,8 2006.231.08:04:07.98#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.08:04:07.98#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.08:04:07.98#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:07.99#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:04:07.99#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:04:07.99#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:04:07.99#ibcon#enter wrdev, iclass 11, count 2 2006.231.08:04:07.99#ibcon#first serial, iclass 11, count 2 2006.231.08:04:07.99#ibcon#enter sib2, iclass 11, count 2 2006.231.08:04:07.99#ibcon#flushed, iclass 11, count 2 2006.231.08:04:07.99#ibcon#about to write, iclass 11, count 2 2006.231.08:04:07.99#ibcon#wrote, iclass 11, count 2 2006.231.08:04:07.99#ibcon#about to read 3, iclass 11, count 2 2006.231.08:04:08.00#ibcon#read 3, iclass 11, count 2 2006.231.08:04:08.00#ibcon#about to read 4, iclass 11, count 2 2006.231.08:04:08.00#ibcon#read 4, iclass 11, count 2 2006.231.08:04:08.00#ibcon#about to read 5, iclass 11, count 2 2006.231.08:04:08.00#ibcon#read 5, iclass 11, count 2 2006.231.08:04:08.00#ibcon#about to read 6, iclass 11, count 2 2006.231.08:04:08.00#ibcon#read 6, iclass 11, count 2 2006.231.08:04:08.00#ibcon#end of sib2, iclass 11, count 2 2006.231.08:04:08.00#ibcon#*mode == 0, iclass 11, count 2 2006.231.08:04:08.00#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.08:04:08.00#ibcon#[25=AT01-08\r\n] 2006.231.08:04:08.00#ibcon#*before write, iclass 11, count 2 2006.231.08:04:08.00#ibcon#enter sib2, iclass 11, count 2 2006.231.08:04:08.00#ibcon#flushed, iclass 11, count 2 2006.231.08:04:08.00#ibcon#about to write, iclass 11, count 2 2006.231.08:04:08.00#ibcon#wrote, iclass 11, count 2 2006.231.08:04:08.00#ibcon#about to read 3, iclass 11, count 2 2006.231.08:04:08.04#ibcon#read 3, iclass 11, count 2 2006.231.08:04:08.04#ibcon#about to read 4, iclass 11, count 2 2006.231.08:04:08.04#ibcon#read 4, iclass 11, count 2 2006.231.08:04:08.04#ibcon#about to read 5, iclass 11, count 2 2006.231.08:04:08.04#ibcon#read 5, iclass 11, count 2 2006.231.08:04:08.04#ibcon#about to read 6, iclass 11, count 2 2006.231.08:04:08.04#ibcon#read 6, iclass 11, count 2 2006.231.08:04:08.04#ibcon#end of sib2, iclass 11, count 2 2006.231.08:04:08.04#ibcon#*after write, iclass 11, count 2 2006.231.08:04:08.04#ibcon#*before return 0, iclass 11, count 2 2006.231.08:04:08.04#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:04:08.04#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:04:08.04#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.08:04:08.04#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:08.04#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:04:08.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:04:08.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:04:08.15#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:04:08.15#ibcon#first serial, iclass 11, count 0 2006.231.08:04:08.15#ibcon#enter sib2, iclass 11, count 0 2006.231.08:04:08.15#ibcon#flushed, iclass 11, count 0 2006.231.08:04:08.15#ibcon#about to write, iclass 11, count 0 2006.231.08:04:08.15#ibcon#wrote, iclass 11, count 0 2006.231.08:04:08.15#ibcon#about to read 3, iclass 11, count 0 2006.231.08:04:08.17#ibcon#read 3, iclass 11, count 0 2006.231.08:04:08.17#ibcon#about to read 4, iclass 11, count 0 2006.231.08:04:08.17#ibcon#read 4, iclass 11, count 0 2006.231.08:04:08.17#ibcon#about to read 5, iclass 11, count 0 2006.231.08:04:08.17#ibcon#read 5, iclass 11, count 0 2006.231.08:04:08.17#ibcon#about to read 6, iclass 11, count 0 2006.231.08:04:08.17#ibcon#read 6, iclass 11, count 0 2006.231.08:04:08.17#ibcon#end of sib2, iclass 11, count 0 2006.231.08:04:08.17#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:04:08.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:04:08.17#ibcon#[25=USB\r\n] 2006.231.08:04:08.17#ibcon#*before write, iclass 11, count 0 2006.231.08:04:08.17#ibcon#enter sib2, iclass 11, count 0 2006.231.08:04:08.17#ibcon#flushed, iclass 11, count 0 2006.231.08:04:08.17#ibcon#about to write, iclass 11, count 0 2006.231.08:04:08.17#ibcon#wrote, iclass 11, count 0 2006.231.08:04:08.17#ibcon#about to read 3, iclass 11, count 0 2006.231.08:04:08.21#ibcon#read 3, iclass 11, count 0 2006.231.08:04:08.21#ibcon#about to read 4, iclass 11, count 0 2006.231.08:04:08.21#ibcon#read 4, iclass 11, count 0 2006.231.08:04:08.21#ibcon#about to read 5, iclass 11, count 0 2006.231.08:04:08.21#ibcon#read 5, iclass 11, count 0 2006.231.08:04:08.21#ibcon#about to read 6, iclass 11, count 0 2006.231.08:04:08.21#ibcon#read 6, iclass 11, count 0 2006.231.08:04:08.21#ibcon#end of sib2, iclass 11, count 0 2006.231.08:04:08.21#ibcon#*after write, iclass 11, count 0 2006.231.08:04:08.21#ibcon#*before return 0, iclass 11, count 0 2006.231.08:04:08.21#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:04:08.21#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:04:08.21#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:04:08.21#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:04:08.21$vc4f8/valo=2,572.99 2006.231.08:04:08.21#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.08:04:08.21#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.08:04:08.21#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:08.21#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:04:08.21#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:04:08.21#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:04:08.21#ibcon#enter wrdev, iclass 13, count 0 2006.231.08:04:08.21#ibcon#first serial, iclass 13, count 0 2006.231.08:04:08.21#ibcon#enter sib2, iclass 13, count 0 2006.231.08:04:08.21#ibcon#flushed, iclass 13, count 0 2006.231.08:04:08.21#ibcon#about to write, iclass 13, count 0 2006.231.08:04:08.21#ibcon#wrote, iclass 13, count 0 2006.231.08:04:08.21#ibcon#about to read 3, iclass 13, count 0 2006.231.08:04:08.23#ibcon#read 3, iclass 13, count 0 2006.231.08:04:08.23#ibcon#about to read 4, iclass 13, count 0 2006.231.08:04:08.23#ibcon#read 4, iclass 13, count 0 2006.231.08:04:08.23#ibcon#about to read 5, iclass 13, count 0 2006.231.08:04:08.23#ibcon#read 5, iclass 13, count 0 2006.231.08:04:08.23#ibcon#about to read 6, iclass 13, count 0 2006.231.08:04:08.23#ibcon#read 6, iclass 13, count 0 2006.231.08:04:08.23#ibcon#end of sib2, iclass 13, count 0 2006.231.08:04:08.23#ibcon#*mode == 0, iclass 13, count 0 2006.231.08:04:08.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.08:04:08.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:04:08.23#ibcon#*before write, iclass 13, count 0 2006.231.08:04:08.23#ibcon#enter sib2, iclass 13, count 0 2006.231.08:04:08.23#ibcon#flushed, iclass 13, count 0 2006.231.08:04:08.23#ibcon#about to write, iclass 13, count 0 2006.231.08:04:08.23#ibcon#wrote, iclass 13, count 0 2006.231.08:04:08.23#ibcon#about to read 3, iclass 13, count 0 2006.231.08:04:08.26#ibcon#read 3, iclass 13, count 0 2006.231.08:04:08.26#ibcon#about to read 4, iclass 13, count 0 2006.231.08:04:08.26#ibcon#read 4, iclass 13, count 0 2006.231.08:04:08.26#ibcon#about to read 5, iclass 13, count 0 2006.231.08:04:08.26#ibcon#read 5, iclass 13, count 0 2006.231.08:04:08.26#ibcon#about to read 6, iclass 13, count 0 2006.231.08:04:08.26#ibcon#read 6, iclass 13, count 0 2006.231.08:04:08.26#ibcon#end of sib2, iclass 13, count 0 2006.231.08:04:08.26#ibcon#*after write, iclass 13, count 0 2006.231.08:04:08.26#ibcon#*before return 0, iclass 13, count 0 2006.231.08:04:08.26#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:04:08.26#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:04:08.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.08:04:08.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.08:04:08.26$vc4f8/va=2,7 2006.231.08:04:08.26#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.08:04:08.26#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.08:04:08.26#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:08.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:04:08.33#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:04:08.33#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:04:08.33#ibcon#enter wrdev, iclass 15, count 2 2006.231.08:04:08.33#ibcon#first serial, iclass 15, count 2 2006.231.08:04:08.33#ibcon#enter sib2, iclass 15, count 2 2006.231.08:04:08.33#ibcon#flushed, iclass 15, count 2 2006.231.08:04:08.33#ibcon#about to write, iclass 15, count 2 2006.231.08:04:08.33#ibcon#wrote, iclass 15, count 2 2006.231.08:04:08.33#ibcon#about to read 3, iclass 15, count 2 2006.231.08:04:08.35#ibcon#read 3, iclass 15, count 2 2006.231.08:04:08.35#ibcon#about to read 4, iclass 15, count 2 2006.231.08:04:08.35#ibcon#read 4, iclass 15, count 2 2006.231.08:04:08.35#ibcon#about to read 5, iclass 15, count 2 2006.231.08:04:08.35#ibcon#read 5, iclass 15, count 2 2006.231.08:04:08.35#ibcon#about to read 6, iclass 15, count 2 2006.231.08:04:08.35#ibcon#read 6, iclass 15, count 2 2006.231.08:04:08.35#ibcon#end of sib2, iclass 15, count 2 2006.231.08:04:08.35#ibcon#*mode == 0, iclass 15, count 2 2006.231.08:04:08.35#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.08:04:08.35#ibcon#[25=AT02-07\r\n] 2006.231.08:04:08.35#ibcon#*before write, iclass 15, count 2 2006.231.08:04:08.35#ibcon#enter sib2, iclass 15, count 2 2006.231.08:04:08.35#ibcon#flushed, iclass 15, count 2 2006.231.08:04:08.35#ibcon#about to write, iclass 15, count 2 2006.231.08:04:08.35#ibcon#wrote, iclass 15, count 2 2006.231.08:04:08.35#ibcon#about to read 3, iclass 15, count 2 2006.231.08:04:08.38#ibcon#read 3, iclass 15, count 2 2006.231.08:04:08.38#ibcon#about to read 4, iclass 15, count 2 2006.231.08:04:08.38#ibcon#read 4, iclass 15, count 2 2006.231.08:04:08.38#ibcon#about to read 5, iclass 15, count 2 2006.231.08:04:08.38#ibcon#read 5, iclass 15, count 2 2006.231.08:04:08.38#ibcon#about to read 6, iclass 15, count 2 2006.231.08:04:08.38#ibcon#read 6, iclass 15, count 2 2006.231.08:04:08.38#ibcon#end of sib2, iclass 15, count 2 2006.231.08:04:08.38#ibcon#*after write, iclass 15, count 2 2006.231.08:04:08.38#ibcon#*before return 0, iclass 15, count 2 2006.231.08:04:08.38#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:04:08.38#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:04:08.38#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.08:04:08.38#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:08.38#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:04:08.51#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:04:08.51#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:04:08.51#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:04:08.51#ibcon#first serial, iclass 15, count 0 2006.231.08:04:08.51#ibcon#enter sib2, iclass 15, count 0 2006.231.08:04:08.51#ibcon#flushed, iclass 15, count 0 2006.231.08:04:08.51#ibcon#about to write, iclass 15, count 0 2006.231.08:04:08.51#ibcon#wrote, iclass 15, count 0 2006.231.08:04:08.51#ibcon#about to read 3, iclass 15, count 0 2006.231.08:04:08.53#ibcon#read 3, iclass 15, count 0 2006.231.08:04:08.53#ibcon#about to read 4, iclass 15, count 0 2006.231.08:04:08.53#ibcon#read 4, iclass 15, count 0 2006.231.08:04:08.53#ibcon#about to read 5, iclass 15, count 0 2006.231.08:04:08.53#ibcon#read 5, iclass 15, count 0 2006.231.08:04:08.53#ibcon#about to read 6, iclass 15, count 0 2006.231.08:04:08.53#ibcon#read 6, iclass 15, count 0 2006.231.08:04:08.53#ibcon#end of sib2, iclass 15, count 0 2006.231.08:04:08.53#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:04:08.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:04:08.53#ibcon#[25=USB\r\n] 2006.231.08:04:08.53#ibcon#*before write, iclass 15, count 0 2006.231.08:04:08.53#ibcon#enter sib2, iclass 15, count 0 2006.231.08:04:08.53#ibcon#flushed, iclass 15, count 0 2006.231.08:04:08.53#ibcon#about to write, iclass 15, count 0 2006.231.08:04:08.53#ibcon#wrote, iclass 15, count 0 2006.231.08:04:08.53#ibcon#about to read 3, iclass 15, count 0 2006.231.08:04:08.55#ibcon#read 3, iclass 15, count 0 2006.231.08:04:08.55#ibcon#about to read 4, iclass 15, count 0 2006.231.08:04:08.55#ibcon#read 4, iclass 15, count 0 2006.231.08:04:08.55#ibcon#about to read 5, iclass 15, count 0 2006.231.08:04:08.55#ibcon#read 5, iclass 15, count 0 2006.231.08:04:08.55#ibcon#about to read 6, iclass 15, count 0 2006.231.08:04:08.55#ibcon#read 6, iclass 15, count 0 2006.231.08:04:08.55#ibcon#end of sib2, iclass 15, count 0 2006.231.08:04:08.55#ibcon#*after write, iclass 15, count 0 2006.231.08:04:08.55#ibcon#*before return 0, iclass 15, count 0 2006.231.08:04:08.55#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:04:08.55#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:04:08.55#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:04:08.55#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:04:08.55$vc4f8/valo=3,672.99 2006.231.08:04:08.56#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.08:04:08.56#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.08:04:08.56#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:08.56#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:04:08.56#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:04:08.56#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:04:08.56#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:04:08.56#ibcon#first serial, iclass 17, count 0 2006.231.08:04:08.56#ibcon#enter sib2, iclass 17, count 0 2006.231.08:04:08.56#ibcon#flushed, iclass 17, count 0 2006.231.08:04:08.56#ibcon#about to write, iclass 17, count 0 2006.231.08:04:08.56#ibcon#wrote, iclass 17, count 0 2006.231.08:04:08.56#ibcon#about to read 3, iclass 17, count 0 2006.231.08:04:08.57#ibcon#read 3, iclass 17, count 0 2006.231.08:04:08.57#ibcon#about to read 4, iclass 17, count 0 2006.231.08:04:08.57#ibcon#read 4, iclass 17, count 0 2006.231.08:04:08.57#ibcon#about to read 5, iclass 17, count 0 2006.231.08:04:08.57#ibcon#read 5, iclass 17, count 0 2006.231.08:04:08.57#ibcon#about to read 6, iclass 17, count 0 2006.231.08:04:08.57#ibcon#read 6, iclass 17, count 0 2006.231.08:04:08.57#ibcon#end of sib2, iclass 17, count 0 2006.231.08:04:08.57#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:04:08.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:04:08.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:04:08.57#ibcon#*before write, iclass 17, count 0 2006.231.08:04:08.57#ibcon#enter sib2, iclass 17, count 0 2006.231.08:04:08.57#ibcon#flushed, iclass 17, count 0 2006.231.08:04:08.57#ibcon#about to write, iclass 17, count 0 2006.231.08:04:08.57#ibcon#wrote, iclass 17, count 0 2006.231.08:04:08.57#ibcon#about to read 3, iclass 17, count 0 2006.231.08:04:08.62#ibcon#read 3, iclass 17, count 0 2006.231.08:04:08.62#ibcon#about to read 4, iclass 17, count 0 2006.231.08:04:08.62#ibcon#read 4, iclass 17, count 0 2006.231.08:04:08.62#ibcon#about to read 5, iclass 17, count 0 2006.231.08:04:08.62#ibcon#read 5, iclass 17, count 0 2006.231.08:04:08.62#ibcon#about to read 6, iclass 17, count 0 2006.231.08:04:08.62#ibcon#read 6, iclass 17, count 0 2006.231.08:04:08.62#ibcon#end of sib2, iclass 17, count 0 2006.231.08:04:08.62#ibcon#*after write, iclass 17, count 0 2006.231.08:04:08.62#ibcon#*before return 0, iclass 17, count 0 2006.231.08:04:08.62#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:04:08.62#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:04:08.62#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:04:08.62#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:04:08.62$vc4f8/va=3,8 2006.231.08:04:08.62#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.231.08:04:08.62#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.231.08:04:08.62#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:08.62#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:04:08.66#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:04:08.66#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:04:08.66#ibcon#enter wrdev, iclass 19, count 2 2006.231.08:04:08.66#ibcon#first serial, iclass 19, count 2 2006.231.08:04:08.66#ibcon#enter sib2, iclass 19, count 2 2006.231.08:04:08.66#ibcon#flushed, iclass 19, count 2 2006.231.08:04:08.66#ibcon#about to write, iclass 19, count 2 2006.231.08:04:08.66#ibcon#wrote, iclass 19, count 2 2006.231.08:04:08.66#ibcon#about to read 3, iclass 19, count 2 2006.231.08:04:08.68#ibcon#read 3, iclass 19, count 2 2006.231.08:04:08.68#ibcon#about to read 4, iclass 19, count 2 2006.231.08:04:08.68#ibcon#read 4, iclass 19, count 2 2006.231.08:04:08.68#ibcon#about to read 5, iclass 19, count 2 2006.231.08:04:08.68#ibcon#read 5, iclass 19, count 2 2006.231.08:04:08.68#ibcon#about to read 6, iclass 19, count 2 2006.231.08:04:08.68#ibcon#read 6, iclass 19, count 2 2006.231.08:04:08.68#ibcon#end of sib2, iclass 19, count 2 2006.231.08:04:08.68#ibcon#*mode == 0, iclass 19, count 2 2006.231.08:04:08.68#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.231.08:04:08.68#ibcon#[25=AT03-08\r\n] 2006.231.08:04:08.68#ibcon#*before write, iclass 19, count 2 2006.231.08:04:08.68#ibcon#enter sib2, iclass 19, count 2 2006.231.08:04:08.68#ibcon#flushed, iclass 19, count 2 2006.231.08:04:08.68#ibcon#about to write, iclass 19, count 2 2006.231.08:04:08.68#ibcon#wrote, iclass 19, count 2 2006.231.08:04:08.68#ibcon#about to read 3, iclass 19, count 2 2006.231.08:04:08.71#ibcon#read 3, iclass 19, count 2 2006.231.08:04:08.71#ibcon#about to read 4, iclass 19, count 2 2006.231.08:04:08.71#ibcon#read 4, iclass 19, count 2 2006.231.08:04:08.71#ibcon#about to read 5, iclass 19, count 2 2006.231.08:04:08.71#ibcon#read 5, iclass 19, count 2 2006.231.08:04:08.71#ibcon#about to read 6, iclass 19, count 2 2006.231.08:04:08.71#ibcon#read 6, iclass 19, count 2 2006.231.08:04:08.71#ibcon#end of sib2, iclass 19, count 2 2006.231.08:04:08.71#ibcon#*after write, iclass 19, count 2 2006.231.08:04:08.71#ibcon#*before return 0, iclass 19, count 2 2006.231.08:04:08.71#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:04:08.71#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:04:08.71#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.231.08:04:08.71#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:08.71#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:04:08.83#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:04:08.83#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:04:08.83#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:04:08.83#ibcon#first serial, iclass 19, count 0 2006.231.08:04:08.83#ibcon#enter sib2, iclass 19, count 0 2006.231.08:04:08.83#ibcon#flushed, iclass 19, count 0 2006.231.08:04:08.83#ibcon#about to write, iclass 19, count 0 2006.231.08:04:08.83#ibcon#wrote, iclass 19, count 0 2006.231.08:04:08.83#ibcon#about to read 3, iclass 19, count 0 2006.231.08:04:08.85#ibcon#read 3, iclass 19, count 0 2006.231.08:04:08.85#ibcon#about to read 4, iclass 19, count 0 2006.231.08:04:08.85#ibcon#read 4, iclass 19, count 0 2006.231.08:04:08.85#ibcon#about to read 5, iclass 19, count 0 2006.231.08:04:08.85#ibcon#read 5, iclass 19, count 0 2006.231.08:04:08.85#ibcon#about to read 6, iclass 19, count 0 2006.231.08:04:08.85#ibcon#read 6, iclass 19, count 0 2006.231.08:04:08.85#ibcon#end of sib2, iclass 19, count 0 2006.231.08:04:08.85#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:04:08.85#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:04:08.85#ibcon#[25=USB\r\n] 2006.231.08:04:08.85#ibcon#*before write, iclass 19, count 0 2006.231.08:04:08.85#ibcon#enter sib2, iclass 19, count 0 2006.231.08:04:08.85#ibcon#flushed, iclass 19, count 0 2006.231.08:04:08.85#ibcon#about to write, iclass 19, count 0 2006.231.08:04:08.85#ibcon#wrote, iclass 19, count 0 2006.231.08:04:08.85#ibcon#about to read 3, iclass 19, count 0 2006.231.08:04:08.88#ibcon#read 3, iclass 19, count 0 2006.231.08:04:08.88#ibcon#about to read 4, iclass 19, count 0 2006.231.08:04:08.88#ibcon#read 4, iclass 19, count 0 2006.231.08:04:08.88#ibcon#about to read 5, iclass 19, count 0 2006.231.08:04:08.88#ibcon#read 5, iclass 19, count 0 2006.231.08:04:08.88#ibcon#about to read 6, iclass 19, count 0 2006.231.08:04:08.88#ibcon#read 6, iclass 19, count 0 2006.231.08:04:08.88#ibcon#end of sib2, iclass 19, count 0 2006.231.08:04:08.88#ibcon#*after write, iclass 19, count 0 2006.231.08:04:08.88#ibcon#*before return 0, iclass 19, count 0 2006.231.08:04:08.88#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:04:08.88#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:04:08.88#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:04:08.88#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:04:08.88$vc4f8/valo=4,832.99 2006.231.08:04:08.88#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.08:04:08.88#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.08:04:08.88#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:08.89#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:04:08.89#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:04:08.89#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:04:08.89#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:04:08.89#ibcon#first serial, iclass 21, count 0 2006.231.08:04:08.89#ibcon#enter sib2, iclass 21, count 0 2006.231.08:04:08.89#ibcon#flushed, iclass 21, count 0 2006.231.08:04:08.89#ibcon#about to write, iclass 21, count 0 2006.231.08:04:08.89#ibcon#wrote, iclass 21, count 0 2006.231.08:04:08.89#ibcon#about to read 3, iclass 21, count 0 2006.231.08:04:08.90#ibcon#read 3, iclass 21, count 0 2006.231.08:04:08.90#ibcon#about to read 4, iclass 21, count 0 2006.231.08:04:08.90#ibcon#read 4, iclass 21, count 0 2006.231.08:04:08.90#ibcon#about to read 5, iclass 21, count 0 2006.231.08:04:08.90#ibcon#read 5, iclass 21, count 0 2006.231.08:04:08.90#ibcon#about to read 6, iclass 21, count 0 2006.231.08:04:08.90#ibcon#read 6, iclass 21, count 0 2006.231.08:04:08.90#ibcon#end of sib2, iclass 21, count 0 2006.231.08:04:08.90#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:04:08.90#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:04:08.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:04:08.90#ibcon#*before write, iclass 21, count 0 2006.231.08:04:08.90#ibcon#enter sib2, iclass 21, count 0 2006.231.08:04:08.90#ibcon#flushed, iclass 21, count 0 2006.231.08:04:08.90#ibcon#about to write, iclass 21, count 0 2006.231.08:04:08.90#ibcon#wrote, iclass 21, count 0 2006.231.08:04:08.90#ibcon#about to read 3, iclass 21, count 0 2006.231.08:04:08.94#ibcon#read 3, iclass 21, count 0 2006.231.08:04:08.94#ibcon#about to read 4, iclass 21, count 0 2006.231.08:04:08.94#ibcon#read 4, iclass 21, count 0 2006.231.08:04:08.94#ibcon#about to read 5, iclass 21, count 0 2006.231.08:04:08.94#ibcon#read 5, iclass 21, count 0 2006.231.08:04:08.94#ibcon#about to read 6, iclass 21, count 0 2006.231.08:04:08.94#ibcon#read 6, iclass 21, count 0 2006.231.08:04:08.94#ibcon#end of sib2, iclass 21, count 0 2006.231.08:04:08.94#ibcon#*after write, iclass 21, count 0 2006.231.08:04:08.94#ibcon#*before return 0, iclass 21, count 0 2006.231.08:04:08.94#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:04:08.94#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:04:08.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:04:08.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:04:08.94$vc4f8/va=4,7 2006.231.08:04:08.94#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.231.08:04:08.94#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.231.08:04:08.94#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:08.95#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:04:09.00#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:04:09.00#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:04:09.00#ibcon#enter wrdev, iclass 23, count 2 2006.231.08:04:09.00#ibcon#first serial, iclass 23, count 2 2006.231.08:04:09.00#ibcon#enter sib2, iclass 23, count 2 2006.231.08:04:09.00#ibcon#flushed, iclass 23, count 2 2006.231.08:04:09.00#ibcon#about to write, iclass 23, count 2 2006.231.08:04:09.01#ibcon#wrote, iclass 23, count 2 2006.231.08:04:09.01#ibcon#about to read 3, iclass 23, count 2 2006.231.08:04:09.02#ibcon#read 3, iclass 23, count 2 2006.231.08:04:09.02#ibcon#about to read 4, iclass 23, count 2 2006.231.08:04:09.02#ibcon#read 4, iclass 23, count 2 2006.231.08:04:09.02#ibcon#about to read 5, iclass 23, count 2 2006.231.08:04:09.02#ibcon#read 5, iclass 23, count 2 2006.231.08:04:09.02#ibcon#about to read 6, iclass 23, count 2 2006.231.08:04:09.02#ibcon#read 6, iclass 23, count 2 2006.231.08:04:09.02#ibcon#end of sib2, iclass 23, count 2 2006.231.08:04:09.02#ibcon#*mode == 0, iclass 23, count 2 2006.231.08:04:09.02#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.231.08:04:09.02#ibcon#[25=AT04-07\r\n] 2006.231.08:04:09.02#ibcon#*before write, iclass 23, count 2 2006.231.08:04:09.02#ibcon#enter sib2, iclass 23, count 2 2006.231.08:04:09.02#ibcon#flushed, iclass 23, count 2 2006.231.08:04:09.02#ibcon#about to write, iclass 23, count 2 2006.231.08:04:09.02#ibcon#wrote, iclass 23, count 2 2006.231.08:04:09.02#ibcon#about to read 3, iclass 23, count 2 2006.231.08:04:09.05#ibcon#read 3, iclass 23, count 2 2006.231.08:04:09.05#ibcon#about to read 4, iclass 23, count 2 2006.231.08:04:09.05#ibcon#read 4, iclass 23, count 2 2006.231.08:04:09.05#ibcon#about to read 5, iclass 23, count 2 2006.231.08:04:09.05#ibcon#read 5, iclass 23, count 2 2006.231.08:04:09.05#ibcon#about to read 6, iclass 23, count 2 2006.231.08:04:09.05#ibcon#read 6, iclass 23, count 2 2006.231.08:04:09.05#ibcon#end of sib2, iclass 23, count 2 2006.231.08:04:09.05#ibcon#*after write, iclass 23, count 2 2006.231.08:04:09.05#ibcon#*before return 0, iclass 23, count 2 2006.231.08:04:09.05#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:04:09.05#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:04:09.05#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.231.08:04:09.05#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:09.05#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:04:09.17#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:04:09.17#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:04:09.17#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:04:09.17#ibcon#first serial, iclass 23, count 0 2006.231.08:04:09.17#ibcon#enter sib2, iclass 23, count 0 2006.231.08:04:09.17#ibcon#flushed, iclass 23, count 0 2006.231.08:04:09.17#ibcon#about to write, iclass 23, count 0 2006.231.08:04:09.17#ibcon#wrote, iclass 23, count 0 2006.231.08:04:09.17#ibcon#about to read 3, iclass 23, count 0 2006.231.08:04:09.19#ibcon#read 3, iclass 23, count 0 2006.231.08:04:09.19#ibcon#about to read 4, iclass 23, count 0 2006.231.08:04:09.19#ibcon#read 4, iclass 23, count 0 2006.231.08:04:09.19#ibcon#about to read 5, iclass 23, count 0 2006.231.08:04:09.19#ibcon#read 5, iclass 23, count 0 2006.231.08:04:09.19#ibcon#about to read 6, iclass 23, count 0 2006.231.08:04:09.19#ibcon#read 6, iclass 23, count 0 2006.231.08:04:09.19#ibcon#end of sib2, iclass 23, count 0 2006.231.08:04:09.19#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:04:09.19#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:04:09.19#ibcon#[25=USB\r\n] 2006.231.08:04:09.19#ibcon#*before write, iclass 23, count 0 2006.231.08:04:09.19#ibcon#enter sib2, iclass 23, count 0 2006.231.08:04:09.19#ibcon#flushed, iclass 23, count 0 2006.231.08:04:09.19#ibcon#about to write, iclass 23, count 0 2006.231.08:04:09.19#ibcon#wrote, iclass 23, count 0 2006.231.08:04:09.19#ibcon#about to read 3, iclass 23, count 0 2006.231.08:04:09.22#ibcon#read 3, iclass 23, count 0 2006.231.08:04:09.22#ibcon#about to read 4, iclass 23, count 0 2006.231.08:04:09.22#ibcon#read 4, iclass 23, count 0 2006.231.08:04:09.22#ibcon#about to read 5, iclass 23, count 0 2006.231.08:04:09.22#ibcon#read 5, iclass 23, count 0 2006.231.08:04:09.22#ibcon#about to read 6, iclass 23, count 0 2006.231.08:04:09.22#ibcon#read 6, iclass 23, count 0 2006.231.08:04:09.22#ibcon#end of sib2, iclass 23, count 0 2006.231.08:04:09.22#ibcon#*after write, iclass 23, count 0 2006.231.08:04:09.22#ibcon#*before return 0, iclass 23, count 0 2006.231.08:04:09.22#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:04:09.22#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:04:09.22#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:04:09.22#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:04:09.22$vc4f8/valo=5,652.99 2006.231.08:04:09.22#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.231.08:04:09.22#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.231.08:04:09.23#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:09.23#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:04:09.23#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:04:09.23#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:04:09.23#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:04:09.23#ibcon#first serial, iclass 25, count 0 2006.231.08:04:09.23#ibcon#enter sib2, iclass 25, count 0 2006.231.08:04:09.23#ibcon#flushed, iclass 25, count 0 2006.231.08:04:09.23#ibcon#about to write, iclass 25, count 0 2006.231.08:04:09.23#ibcon#wrote, iclass 25, count 0 2006.231.08:04:09.23#ibcon#about to read 3, iclass 25, count 0 2006.231.08:04:09.24#ibcon#read 3, iclass 25, count 0 2006.231.08:04:09.24#ibcon#about to read 4, iclass 25, count 0 2006.231.08:04:09.24#ibcon#read 4, iclass 25, count 0 2006.231.08:04:09.24#ibcon#about to read 5, iclass 25, count 0 2006.231.08:04:09.24#ibcon#read 5, iclass 25, count 0 2006.231.08:04:09.24#ibcon#about to read 6, iclass 25, count 0 2006.231.08:04:09.24#ibcon#read 6, iclass 25, count 0 2006.231.08:04:09.24#ibcon#end of sib2, iclass 25, count 0 2006.231.08:04:09.24#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:04:09.24#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:04:09.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:04:09.24#ibcon#*before write, iclass 25, count 0 2006.231.08:04:09.24#ibcon#enter sib2, iclass 25, count 0 2006.231.08:04:09.24#ibcon#flushed, iclass 25, count 0 2006.231.08:04:09.24#ibcon#about to write, iclass 25, count 0 2006.231.08:04:09.24#ibcon#wrote, iclass 25, count 0 2006.231.08:04:09.24#ibcon#about to read 3, iclass 25, count 0 2006.231.08:04:09.28#ibcon#read 3, iclass 25, count 0 2006.231.08:04:09.28#ibcon#about to read 4, iclass 25, count 0 2006.231.08:04:09.28#ibcon#read 4, iclass 25, count 0 2006.231.08:04:09.28#ibcon#about to read 5, iclass 25, count 0 2006.231.08:04:09.28#ibcon#read 5, iclass 25, count 0 2006.231.08:04:09.28#ibcon#about to read 6, iclass 25, count 0 2006.231.08:04:09.28#ibcon#read 6, iclass 25, count 0 2006.231.08:04:09.28#ibcon#end of sib2, iclass 25, count 0 2006.231.08:04:09.28#ibcon#*after write, iclass 25, count 0 2006.231.08:04:09.28#ibcon#*before return 0, iclass 25, count 0 2006.231.08:04:09.28#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:04:09.28#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:04:09.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:04:09.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:04:09.28$vc4f8/va=5,7 2006.231.08:04:09.28#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.231.08:04:09.28#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.231.08:04:09.28#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:09.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:04:09.34#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:04:09.34#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:04:09.34#ibcon#enter wrdev, iclass 27, count 2 2006.231.08:04:09.34#ibcon#first serial, iclass 27, count 2 2006.231.08:04:09.34#ibcon#enter sib2, iclass 27, count 2 2006.231.08:04:09.34#ibcon#flushed, iclass 27, count 2 2006.231.08:04:09.34#ibcon#about to write, iclass 27, count 2 2006.231.08:04:09.34#ibcon#wrote, iclass 27, count 2 2006.231.08:04:09.34#ibcon#about to read 3, iclass 27, count 2 2006.231.08:04:09.36#ibcon#read 3, iclass 27, count 2 2006.231.08:04:09.36#ibcon#about to read 4, iclass 27, count 2 2006.231.08:04:09.36#ibcon#read 4, iclass 27, count 2 2006.231.08:04:09.36#ibcon#about to read 5, iclass 27, count 2 2006.231.08:04:09.36#ibcon#read 5, iclass 27, count 2 2006.231.08:04:09.36#ibcon#about to read 6, iclass 27, count 2 2006.231.08:04:09.36#ibcon#read 6, iclass 27, count 2 2006.231.08:04:09.36#ibcon#end of sib2, iclass 27, count 2 2006.231.08:04:09.36#ibcon#*mode == 0, iclass 27, count 2 2006.231.08:04:09.36#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.231.08:04:09.36#ibcon#[25=AT05-07\r\n] 2006.231.08:04:09.36#ibcon#*before write, iclass 27, count 2 2006.231.08:04:09.36#ibcon#enter sib2, iclass 27, count 2 2006.231.08:04:09.36#ibcon#flushed, iclass 27, count 2 2006.231.08:04:09.36#ibcon#about to write, iclass 27, count 2 2006.231.08:04:09.36#ibcon#wrote, iclass 27, count 2 2006.231.08:04:09.36#ibcon#about to read 3, iclass 27, count 2 2006.231.08:04:09.39#ibcon#read 3, iclass 27, count 2 2006.231.08:04:09.39#ibcon#about to read 4, iclass 27, count 2 2006.231.08:04:09.39#ibcon#read 4, iclass 27, count 2 2006.231.08:04:09.39#ibcon#about to read 5, iclass 27, count 2 2006.231.08:04:09.39#ibcon#read 5, iclass 27, count 2 2006.231.08:04:09.39#ibcon#about to read 6, iclass 27, count 2 2006.231.08:04:09.39#ibcon#read 6, iclass 27, count 2 2006.231.08:04:09.39#ibcon#end of sib2, iclass 27, count 2 2006.231.08:04:09.39#ibcon#*after write, iclass 27, count 2 2006.231.08:04:09.39#ibcon#*before return 0, iclass 27, count 2 2006.231.08:04:09.39#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:04:09.39#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:04:09.39#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.231.08:04:09.39#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:09.39#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:04:09.51#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:04:09.51#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:04:09.51#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:04:09.51#ibcon#first serial, iclass 27, count 0 2006.231.08:04:09.51#ibcon#enter sib2, iclass 27, count 0 2006.231.08:04:09.51#ibcon#flushed, iclass 27, count 0 2006.231.08:04:09.51#ibcon#about to write, iclass 27, count 0 2006.231.08:04:09.51#ibcon#wrote, iclass 27, count 0 2006.231.08:04:09.51#ibcon#about to read 3, iclass 27, count 0 2006.231.08:04:09.53#ibcon#read 3, iclass 27, count 0 2006.231.08:04:09.53#ibcon#about to read 4, iclass 27, count 0 2006.231.08:04:09.53#ibcon#read 4, iclass 27, count 0 2006.231.08:04:09.53#ibcon#about to read 5, iclass 27, count 0 2006.231.08:04:09.53#ibcon#read 5, iclass 27, count 0 2006.231.08:04:09.53#ibcon#about to read 6, iclass 27, count 0 2006.231.08:04:09.53#ibcon#read 6, iclass 27, count 0 2006.231.08:04:09.53#ibcon#end of sib2, iclass 27, count 0 2006.231.08:04:09.53#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:04:09.53#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:04:09.53#ibcon#[25=USB\r\n] 2006.231.08:04:09.53#ibcon#*before write, iclass 27, count 0 2006.231.08:04:09.53#ibcon#enter sib2, iclass 27, count 0 2006.231.08:04:09.53#ibcon#flushed, iclass 27, count 0 2006.231.08:04:09.53#ibcon#about to write, iclass 27, count 0 2006.231.08:04:09.53#ibcon#wrote, iclass 27, count 0 2006.231.08:04:09.53#ibcon#about to read 3, iclass 27, count 0 2006.231.08:04:09.56#ibcon#read 3, iclass 27, count 0 2006.231.08:04:09.56#ibcon#about to read 4, iclass 27, count 0 2006.231.08:04:09.56#ibcon#read 4, iclass 27, count 0 2006.231.08:04:09.56#ibcon#about to read 5, iclass 27, count 0 2006.231.08:04:09.56#ibcon#read 5, iclass 27, count 0 2006.231.08:04:09.56#ibcon#about to read 6, iclass 27, count 0 2006.231.08:04:09.56#ibcon#read 6, iclass 27, count 0 2006.231.08:04:09.56#ibcon#end of sib2, iclass 27, count 0 2006.231.08:04:09.56#ibcon#*after write, iclass 27, count 0 2006.231.08:04:09.56#ibcon#*before return 0, iclass 27, count 0 2006.231.08:04:09.56#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:04:09.56#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:04:09.56#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:04:09.56#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:04:09.56$vc4f8/valo=6,772.99 2006.231.08:04:09.56#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.231.08:04:09.56#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.231.08:04:09.57#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:09.57#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:04:09.57#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:04:09.57#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:04:09.57#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:04:09.57#ibcon#first serial, iclass 29, count 0 2006.231.08:04:09.57#ibcon#enter sib2, iclass 29, count 0 2006.231.08:04:09.57#ibcon#flushed, iclass 29, count 0 2006.231.08:04:09.57#ibcon#about to write, iclass 29, count 0 2006.231.08:04:09.57#ibcon#wrote, iclass 29, count 0 2006.231.08:04:09.57#ibcon#about to read 3, iclass 29, count 0 2006.231.08:04:09.58#ibcon#read 3, iclass 29, count 0 2006.231.08:04:09.58#ibcon#about to read 4, iclass 29, count 0 2006.231.08:04:09.58#ibcon#read 4, iclass 29, count 0 2006.231.08:04:09.58#ibcon#about to read 5, iclass 29, count 0 2006.231.08:04:09.58#ibcon#read 5, iclass 29, count 0 2006.231.08:04:09.58#ibcon#about to read 6, iclass 29, count 0 2006.231.08:04:09.58#ibcon#read 6, iclass 29, count 0 2006.231.08:04:09.58#ibcon#end of sib2, iclass 29, count 0 2006.231.08:04:09.58#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:04:09.58#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:04:09.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:04:09.58#ibcon#*before write, iclass 29, count 0 2006.231.08:04:09.58#ibcon#enter sib2, iclass 29, count 0 2006.231.08:04:09.58#ibcon#flushed, iclass 29, count 0 2006.231.08:04:09.58#ibcon#about to write, iclass 29, count 0 2006.231.08:04:09.58#ibcon#wrote, iclass 29, count 0 2006.231.08:04:09.58#ibcon#about to read 3, iclass 29, count 0 2006.231.08:04:09.62#ibcon#read 3, iclass 29, count 0 2006.231.08:04:09.62#ibcon#about to read 4, iclass 29, count 0 2006.231.08:04:09.62#ibcon#read 4, iclass 29, count 0 2006.231.08:04:09.62#ibcon#about to read 5, iclass 29, count 0 2006.231.08:04:09.62#ibcon#read 5, iclass 29, count 0 2006.231.08:04:09.62#ibcon#about to read 6, iclass 29, count 0 2006.231.08:04:09.62#ibcon#read 6, iclass 29, count 0 2006.231.08:04:09.62#ibcon#end of sib2, iclass 29, count 0 2006.231.08:04:09.62#ibcon#*after write, iclass 29, count 0 2006.231.08:04:09.62#ibcon#*before return 0, iclass 29, count 0 2006.231.08:04:09.62#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:04:09.62#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:04:09.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:04:09.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:04:09.62$vc4f8/va=6,6 2006.231.08:04:09.62#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.231.08:04:09.62#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.231.08:04:09.63#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:09.63#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:04:09.67#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:04:09.67#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:04:09.67#ibcon#enter wrdev, iclass 31, count 2 2006.231.08:04:09.67#ibcon#first serial, iclass 31, count 2 2006.231.08:04:09.67#ibcon#enter sib2, iclass 31, count 2 2006.231.08:04:09.67#ibcon#flushed, iclass 31, count 2 2006.231.08:04:09.67#ibcon#about to write, iclass 31, count 2 2006.231.08:04:09.67#ibcon#wrote, iclass 31, count 2 2006.231.08:04:09.67#ibcon#about to read 3, iclass 31, count 2 2006.231.08:04:09.69#ibcon#read 3, iclass 31, count 2 2006.231.08:04:09.69#ibcon#about to read 4, iclass 31, count 2 2006.231.08:04:09.69#ibcon#read 4, iclass 31, count 2 2006.231.08:04:09.69#ibcon#about to read 5, iclass 31, count 2 2006.231.08:04:09.69#ibcon#read 5, iclass 31, count 2 2006.231.08:04:09.69#ibcon#about to read 6, iclass 31, count 2 2006.231.08:04:09.69#ibcon#read 6, iclass 31, count 2 2006.231.08:04:09.69#ibcon#end of sib2, iclass 31, count 2 2006.231.08:04:09.69#ibcon#*mode == 0, iclass 31, count 2 2006.231.08:04:09.69#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.231.08:04:09.69#ibcon#[25=AT06-06\r\n] 2006.231.08:04:09.69#ibcon#*before write, iclass 31, count 2 2006.231.08:04:09.69#ibcon#enter sib2, iclass 31, count 2 2006.231.08:04:09.69#ibcon#flushed, iclass 31, count 2 2006.231.08:04:09.69#ibcon#about to write, iclass 31, count 2 2006.231.08:04:09.69#ibcon#wrote, iclass 31, count 2 2006.231.08:04:09.69#ibcon#about to read 3, iclass 31, count 2 2006.231.08:04:09.72#ibcon#read 3, iclass 31, count 2 2006.231.08:04:09.72#ibcon#about to read 4, iclass 31, count 2 2006.231.08:04:09.72#ibcon#read 4, iclass 31, count 2 2006.231.08:04:09.72#ibcon#about to read 5, iclass 31, count 2 2006.231.08:04:09.72#ibcon#read 5, iclass 31, count 2 2006.231.08:04:09.72#ibcon#about to read 6, iclass 31, count 2 2006.231.08:04:09.72#ibcon#read 6, iclass 31, count 2 2006.231.08:04:09.72#ibcon#end of sib2, iclass 31, count 2 2006.231.08:04:09.72#ibcon#*after write, iclass 31, count 2 2006.231.08:04:09.72#ibcon#*before return 0, iclass 31, count 2 2006.231.08:04:09.72#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:04:09.72#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:04:09.72#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.231.08:04:09.72#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:09.72#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:04:09.84#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:04:09.84#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:04:09.84#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:04:09.84#ibcon#first serial, iclass 31, count 0 2006.231.08:04:09.84#ibcon#enter sib2, iclass 31, count 0 2006.231.08:04:09.84#ibcon#flushed, iclass 31, count 0 2006.231.08:04:09.84#ibcon#about to write, iclass 31, count 0 2006.231.08:04:09.84#ibcon#wrote, iclass 31, count 0 2006.231.08:04:09.84#ibcon#about to read 3, iclass 31, count 0 2006.231.08:04:09.86#ibcon#read 3, iclass 31, count 0 2006.231.08:04:09.86#ibcon#about to read 4, iclass 31, count 0 2006.231.08:04:09.86#ibcon#read 4, iclass 31, count 0 2006.231.08:04:09.86#ibcon#about to read 5, iclass 31, count 0 2006.231.08:04:09.86#ibcon#read 5, iclass 31, count 0 2006.231.08:04:09.86#ibcon#about to read 6, iclass 31, count 0 2006.231.08:04:09.86#ibcon#read 6, iclass 31, count 0 2006.231.08:04:09.86#ibcon#end of sib2, iclass 31, count 0 2006.231.08:04:09.86#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:04:09.86#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:04:09.86#ibcon#[25=USB\r\n] 2006.231.08:04:09.86#ibcon#*before write, iclass 31, count 0 2006.231.08:04:09.86#ibcon#enter sib2, iclass 31, count 0 2006.231.08:04:09.86#ibcon#flushed, iclass 31, count 0 2006.231.08:04:09.86#ibcon#about to write, iclass 31, count 0 2006.231.08:04:09.86#ibcon#wrote, iclass 31, count 0 2006.231.08:04:09.86#ibcon#about to read 3, iclass 31, count 0 2006.231.08:04:09.89#ibcon#read 3, iclass 31, count 0 2006.231.08:04:09.89#ibcon#about to read 4, iclass 31, count 0 2006.231.08:04:09.89#ibcon#read 4, iclass 31, count 0 2006.231.08:04:09.89#ibcon#about to read 5, iclass 31, count 0 2006.231.08:04:09.89#ibcon#read 5, iclass 31, count 0 2006.231.08:04:09.89#ibcon#about to read 6, iclass 31, count 0 2006.231.08:04:09.89#ibcon#read 6, iclass 31, count 0 2006.231.08:04:09.89#ibcon#end of sib2, iclass 31, count 0 2006.231.08:04:09.89#ibcon#*after write, iclass 31, count 0 2006.231.08:04:09.89#ibcon#*before return 0, iclass 31, count 0 2006.231.08:04:09.89#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:04:09.89#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:04:09.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:04:09.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:04:09.89$vc4f8/valo=7,832.99 2006.231.08:04:09.89#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.08:04:09.89#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.08:04:09.89#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:09.90#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:04:09.90#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:04:09.90#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:04:09.90#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:04:09.90#ibcon#first serial, iclass 33, count 0 2006.231.08:04:09.90#ibcon#enter sib2, iclass 33, count 0 2006.231.08:04:09.90#ibcon#flushed, iclass 33, count 0 2006.231.08:04:09.90#ibcon#about to write, iclass 33, count 0 2006.231.08:04:09.90#ibcon#wrote, iclass 33, count 0 2006.231.08:04:09.90#ibcon#about to read 3, iclass 33, count 0 2006.231.08:04:09.91#ibcon#read 3, iclass 33, count 0 2006.231.08:04:09.91#ibcon#about to read 4, iclass 33, count 0 2006.231.08:04:09.91#ibcon#read 4, iclass 33, count 0 2006.231.08:04:09.91#ibcon#about to read 5, iclass 33, count 0 2006.231.08:04:09.91#ibcon#read 5, iclass 33, count 0 2006.231.08:04:09.91#ibcon#about to read 6, iclass 33, count 0 2006.231.08:04:09.91#ibcon#read 6, iclass 33, count 0 2006.231.08:04:09.91#ibcon#end of sib2, iclass 33, count 0 2006.231.08:04:09.91#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:04:09.91#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:04:09.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:04:09.91#ibcon#*before write, iclass 33, count 0 2006.231.08:04:09.91#ibcon#enter sib2, iclass 33, count 0 2006.231.08:04:09.91#ibcon#flushed, iclass 33, count 0 2006.231.08:04:09.91#ibcon#about to write, iclass 33, count 0 2006.231.08:04:09.91#ibcon#wrote, iclass 33, count 0 2006.231.08:04:09.91#ibcon#about to read 3, iclass 33, count 0 2006.231.08:04:09.95#ibcon#read 3, iclass 33, count 0 2006.231.08:04:09.95#ibcon#about to read 4, iclass 33, count 0 2006.231.08:04:09.95#ibcon#read 4, iclass 33, count 0 2006.231.08:04:09.95#ibcon#about to read 5, iclass 33, count 0 2006.231.08:04:09.95#ibcon#read 5, iclass 33, count 0 2006.231.08:04:09.95#ibcon#about to read 6, iclass 33, count 0 2006.231.08:04:09.95#ibcon#read 6, iclass 33, count 0 2006.231.08:04:09.95#ibcon#end of sib2, iclass 33, count 0 2006.231.08:04:09.95#ibcon#*after write, iclass 33, count 0 2006.231.08:04:09.95#ibcon#*before return 0, iclass 33, count 0 2006.231.08:04:09.95#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:04:09.95#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:04:09.95#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:04:09.95#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:04:09.95$vc4f8/va=7,6 2006.231.08:04:09.95#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.08:04:09.95#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.08:04:09.95#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:09.95#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:04:10.01#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:04:10.01#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:04:10.01#ibcon#enter wrdev, iclass 35, count 2 2006.231.08:04:10.01#ibcon#first serial, iclass 35, count 2 2006.231.08:04:10.02#ibcon#enter sib2, iclass 35, count 2 2006.231.08:04:10.02#ibcon#flushed, iclass 35, count 2 2006.231.08:04:10.02#ibcon#about to write, iclass 35, count 2 2006.231.08:04:10.02#ibcon#wrote, iclass 35, count 2 2006.231.08:04:10.02#ibcon#about to read 3, iclass 35, count 2 2006.231.08:04:10.03#ibcon#read 3, iclass 35, count 2 2006.231.08:04:10.03#ibcon#about to read 4, iclass 35, count 2 2006.231.08:04:10.03#ibcon#read 4, iclass 35, count 2 2006.231.08:04:10.03#ibcon#about to read 5, iclass 35, count 2 2006.231.08:04:10.03#ibcon#read 5, iclass 35, count 2 2006.231.08:04:10.03#ibcon#about to read 6, iclass 35, count 2 2006.231.08:04:10.03#ibcon#read 6, iclass 35, count 2 2006.231.08:04:10.03#ibcon#end of sib2, iclass 35, count 2 2006.231.08:04:10.03#ibcon#*mode == 0, iclass 35, count 2 2006.231.08:04:10.03#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.08:04:10.03#ibcon#[25=AT07-06\r\n] 2006.231.08:04:10.03#ibcon#*before write, iclass 35, count 2 2006.231.08:04:10.03#ibcon#enter sib2, iclass 35, count 2 2006.231.08:04:10.03#ibcon#flushed, iclass 35, count 2 2006.231.08:04:10.03#ibcon#about to write, iclass 35, count 2 2006.231.08:04:10.03#ibcon#wrote, iclass 35, count 2 2006.231.08:04:10.03#ibcon#about to read 3, iclass 35, count 2 2006.231.08:04:10.06#ibcon#read 3, iclass 35, count 2 2006.231.08:04:10.06#ibcon#about to read 4, iclass 35, count 2 2006.231.08:04:10.06#ibcon#read 4, iclass 35, count 2 2006.231.08:04:10.06#ibcon#about to read 5, iclass 35, count 2 2006.231.08:04:10.06#ibcon#read 5, iclass 35, count 2 2006.231.08:04:10.06#ibcon#about to read 6, iclass 35, count 2 2006.231.08:04:10.06#ibcon#read 6, iclass 35, count 2 2006.231.08:04:10.06#ibcon#end of sib2, iclass 35, count 2 2006.231.08:04:10.06#ibcon#*after write, iclass 35, count 2 2006.231.08:04:10.06#ibcon#*before return 0, iclass 35, count 2 2006.231.08:04:10.06#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:04:10.06#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:04:10.06#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.08:04:10.06#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:10.06#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:04:10.18#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:04:10.18#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:04:10.18#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:04:10.18#ibcon#first serial, iclass 35, count 0 2006.231.08:04:10.18#ibcon#enter sib2, iclass 35, count 0 2006.231.08:04:10.18#ibcon#flushed, iclass 35, count 0 2006.231.08:04:10.18#ibcon#about to write, iclass 35, count 0 2006.231.08:04:10.18#ibcon#wrote, iclass 35, count 0 2006.231.08:04:10.18#ibcon#about to read 3, iclass 35, count 0 2006.231.08:04:10.20#ibcon#read 3, iclass 35, count 0 2006.231.08:04:10.20#ibcon#about to read 4, iclass 35, count 0 2006.231.08:04:10.20#ibcon#read 4, iclass 35, count 0 2006.231.08:04:10.20#ibcon#about to read 5, iclass 35, count 0 2006.231.08:04:10.20#ibcon#read 5, iclass 35, count 0 2006.231.08:04:10.20#ibcon#about to read 6, iclass 35, count 0 2006.231.08:04:10.20#ibcon#read 6, iclass 35, count 0 2006.231.08:04:10.20#ibcon#end of sib2, iclass 35, count 0 2006.231.08:04:10.20#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:04:10.20#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:04:10.20#ibcon#[25=USB\r\n] 2006.231.08:04:10.20#ibcon#*before write, iclass 35, count 0 2006.231.08:04:10.20#ibcon#enter sib2, iclass 35, count 0 2006.231.08:04:10.20#ibcon#flushed, iclass 35, count 0 2006.231.08:04:10.20#ibcon#about to write, iclass 35, count 0 2006.231.08:04:10.20#ibcon#wrote, iclass 35, count 0 2006.231.08:04:10.20#ibcon#about to read 3, iclass 35, count 0 2006.231.08:04:10.23#ibcon#read 3, iclass 35, count 0 2006.231.08:04:10.23#ibcon#about to read 4, iclass 35, count 0 2006.231.08:04:10.23#ibcon#read 4, iclass 35, count 0 2006.231.08:04:10.23#ibcon#about to read 5, iclass 35, count 0 2006.231.08:04:10.23#ibcon#read 5, iclass 35, count 0 2006.231.08:04:10.23#ibcon#about to read 6, iclass 35, count 0 2006.231.08:04:10.23#ibcon#read 6, iclass 35, count 0 2006.231.08:04:10.23#ibcon#end of sib2, iclass 35, count 0 2006.231.08:04:10.23#ibcon#*after write, iclass 35, count 0 2006.231.08:04:10.23#ibcon#*before return 0, iclass 35, count 0 2006.231.08:04:10.23#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:04:10.23#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:04:10.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:04:10.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:04:10.23$vc4f8/valo=8,852.99 2006.231.08:04:10.23#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.08:04:10.23#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.08:04:10.23#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:10.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:04:10.24#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:04:10.24#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:04:10.24#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:04:10.24#ibcon#first serial, iclass 37, count 0 2006.231.08:04:10.24#ibcon#enter sib2, iclass 37, count 0 2006.231.08:04:10.24#ibcon#flushed, iclass 37, count 0 2006.231.08:04:10.24#ibcon#about to write, iclass 37, count 0 2006.231.08:04:10.24#ibcon#wrote, iclass 37, count 0 2006.231.08:04:10.24#ibcon#about to read 3, iclass 37, count 0 2006.231.08:04:10.25#ibcon#read 3, iclass 37, count 0 2006.231.08:04:10.25#ibcon#about to read 4, iclass 37, count 0 2006.231.08:04:10.25#ibcon#read 4, iclass 37, count 0 2006.231.08:04:10.25#ibcon#about to read 5, iclass 37, count 0 2006.231.08:04:10.25#ibcon#read 5, iclass 37, count 0 2006.231.08:04:10.25#ibcon#about to read 6, iclass 37, count 0 2006.231.08:04:10.25#ibcon#read 6, iclass 37, count 0 2006.231.08:04:10.25#ibcon#end of sib2, iclass 37, count 0 2006.231.08:04:10.25#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:04:10.25#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:04:10.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:04:10.25#ibcon#*before write, iclass 37, count 0 2006.231.08:04:10.25#ibcon#enter sib2, iclass 37, count 0 2006.231.08:04:10.25#ibcon#flushed, iclass 37, count 0 2006.231.08:04:10.25#ibcon#about to write, iclass 37, count 0 2006.231.08:04:10.25#ibcon#wrote, iclass 37, count 0 2006.231.08:04:10.25#ibcon#about to read 3, iclass 37, count 0 2006.231.08:04:10.29#ibcon#read 3, iclass 37, count 0 2006.231.08:04:10.29#ibcon#about to read 4, iclass 37, count 0 2006.231.08:04:10.29#ibcon#read 4, iclass 37, count 0 2006.231.08:04:10.29#ibcon#about to read 5, iclass 37, count 0 2006.231.08:04:10.29#ibcon#read 5, iclass 37, count 0 2006.231.08:04:10.29#ibcon#about to read 6, iclass 37, count 0 2006.231.08:04:10.29#ibcon#read 6, iclass 37, count 0 2006.231.08:04:10.29#ibcon#end of sib2, iclass 37, count 0 2006.231.08:04:10.29#ibcon#*after write, iclass 37, count 0 2006.231.08:04:10.29#ibcon#*before return 0, iclass 37, count 0 2006.231.08:04:10.29#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:04:10.29#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:04:10.29#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:04:10.29#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:04:10.29$vc4f8/va=8,6 2006.231.08:04:10.29#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.08:04:10.29#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.08:04:10.29#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:10.29#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:04:10.35#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:04:10.35#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:04:10.35#ibcon#enter wrdev, iclass 39, count 2 2006.231.08:04:10.35#ibcon#first serial, iclass 39, count 2 2006.231.08:04:10.35#ibcon#enter sib2, iclass 39, count 2 2006.231.08:04:10.35#ibcon#flushed, iclass 39, count 2 2006.231.08:04:10.35#ibcon#about to write, iclass 39, count 2 2006.231.08:04:10.35#ibcon#wrote, iclass 39, count 2 2006.231.08:04:10.35#ibcon#about to read 3, iclass 39, count 2 2006.231.08:04:10.38#ibcon#read 3, iclass 39, count 2 2006.231.08:04:10.38#ibcon#about to read 4, iclass 39, count 2 2006.231.08:04:10.38#ibcon#read 4, iclass 39, count 2 2006.231.08:04:10.38#ibcon#about to read 5, iclass 39, count 2 2006.231.08:04:10.38#ibcon#read 5, iclass 39, count 2 2006.231.08:04:10.38#ibcon#about to read 6, iclass 39, count 2 2006.231.08:04:10.38#ibcon#read 6, iclass 39, count 2 2006.231.08:04:10.38#ibcon#end of sib2, iclass 39, count 2 2006.231.08:04:10.38#ibcon#*mode == 0, iclass 39, count 2 2006.231.08:04:10.38#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.08:04:10.38#ibcon#[25=AT08-06\r\n] 2006.231.08:04:10.38#ibcon#*before write, iclass 39, count 2 2006.231.08:04:10.38#ibcon#enter sib2, iclass 39, count 2 2006.231.08:04:10.38#ibcon#flushed, iclass 39, count 2 2006.231.08:04:10.38#ibcon#about to write, iclass 39, count 2 2006.231.08:04:10.38#ibcon#wrote, iclass 39, count 2 2006.231.08:04:10.38#ibcon#about to read 3, iclass 39, count 2 2006.231.08:04:10.41#ibcon#read 3, iclass 39, count 2 2006.231.08:04:10.41#ibcon#about to read 4, iclass 39, count 2 2006.231.08:04:10.41#ibcon#read 4, iclass 39, count 2 2006.231.08:04:10.41#ibcon#about to read 5, iclass 39, count 2 2006.231.08:04:10.41#ibcon#read 5, iclass 39, count 2 2006.231.08:04:10.41#ibcon#about to read 6, iclass 39, count 2 2006.231.08:04:10.41#ibcon#read 6, iclass 39, count 2 2006.231.08:04:10.41#ibcon#end of sib2, iclass 39, count 2 2006.231.08:04:10.41#ibcon#*after write, iclass 39, count 2 2006.231.08:04:10.41#ibcon#*before return 0, iclass 39, count 2 2006.231.08:04:10.41#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:04:10.41#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:04:10.41#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.08:04:10.41#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:10.41#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:04:10.53#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:04:10.53#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:04:10.53#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:04:10.53#ibcon#first serial, iclass 39, count 0 2006.231.08:04:10.53#ibcon#enter sib2, iclass 39, count 0 2006.231.08:04:10.53#ibcon#flushed, iclass 39, count 0 2006.231.08:04:10.53#ibcon#about to write, iclass 39, count 0 2006.231.08:04:10.53#ibcon#wrote, iclass 39, count 0 2006.231.08:04:10.53#ibcon#about to read 3, iclass 39, count 0 2006.231.08:04:10.55#ibcon#read 3, iclass 39, count 0 2006.231.08:04:10.55#ibcon#about to read 4, iclass 39, count 0 2006.231.08:04:10.55#ibcon#read 4, iclass 39, count 0 2006.231.08:04:10.55#ibcon#about to read 5, iclass 39, count 0 2006.231.08:04:10.55#ibcon#read 5, iclass 39, count 0 2006.231.08:04:10.55#ibcon#about to read 6, iclass 39, count 0 2006.231.08:04:10.55#ibcon#read 6, iclass 39, count 0 2006.231.08:04:10.55#ibcon#end of sib2, iclass 39, count 0 2006.231.08:04:10.55#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:04:10.55#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:04:10.55#ibcon#[25=USB\r\n] 2006.231.08:04:10.55#ibcon#*before write, iclass 39, count 0 2006.231.08:04:10.55#ibcon#enter sib2, iclass 39, count 0 2006.231.08:04:10.55#ibcon#flushed, iclass 39, count 0 2006.231.08:04:10.55#ibcon#about to write, iclass 39, count 0 2006.231.08:04:10.55#ibcon#wrote, iclass 39, count 0 2006.231.08:04:10.55#ibcon#about to read 3, iclass 39, count 0 2006.231.08:04:10.58#ibcon#read 3, iclass 39, count 0 2006.231.08:04:10.58#ibcon#about to read 4, iclass 39, count 0 2006.231.08:04:10.58#ibcon#read 4, iclass 39, count 0 2006.231.08:04:10.58#ibcon#about to read 5, iclass 39, count 0 2006.231.08:04:10.58#ibcon#read 5, iclass 39, count 0 2006.231.08:04:10.58#ibcon#about to read 6, iclass 39, count 0 2006.231.08:04:10.58#ibcon#read 6, iclass 39, count 0 2006.231.08:04:10.58#ibcon#end of sib2, iclass 39, count 0 2006.231.08:04:10.58#ibcon#*after write, iclass 39, count 0 2006.231.08:04:10.58#ibcon#*before return 0, iclass 39, count 0 2006.231.08:04:10.58#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:04:10.58#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:04:10.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:04:10.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:04:10.58$vc4f8/vblo=1,632.99 2006.231.08:04:10.58#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.08:04:10.58#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.08:04:10.59#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:10.59#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:04:10.59#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:04:10.59#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:04:10.59#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:04:10.59#ibcon#first serial, iclass 3, count 0 2006.231.08:04:10.59#ibcon#enter sib2, iclass 3, count 0 2006.231.08:04:10.59#ibcon#flushed, iclass 3, count 0 2006.231.08:04:10.59#ibcon#about to write, iclass 3, count 0 2006.231.08:04:10.59#ibcon#wrote, iclass 3, count 0 2006.231.08:04:10.59#ibcon#about to read 3, iclass 3, count 0 2006.231.08:04:10.60#ibcon#read 3, iclass 3, count 0 2006.231.08:04:10.60#ibcon#about to read 4, iclass 3, count 0 2006.231.08:04:10.60#ibcon#read 4, iclass 3, count 0 2006.231.08:04:10.60#ibcon#about to read 5, iclass 3, count 0 2006.231.08:04:10.60#ibcon#read 5, iclass 3, count 0 2006.231.08:04:10.60#ibcon#about to read 6, iclass 3, count 0 2006.231.08:04:10.60#ibcon#read 6, iclass 3, count 0 2006.231.08:04:10.60#ibcon#end of sib2, iclass 3, count 0 2006.231.08:04:10.60#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:04:10.60#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:04:10.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:04:10.60#ibcon#*before write, iclass 3, count 0 2006.231.08:04:10.60#ibcon#enter sib2, iclass 3, count 0 2006.231.08:04:10.60#ibcon#flushed, iclass 3, count 0 2006.231.08:04:10.60#ibcon#about to write, iclass 3, count 0 2006.231.08:04:10.60#ibcon#wrote, iclass 3, count 0 2006.231.08:04:10.60#ibcon#about to read 3, iclass 3, count 0 2006.231.08:04:10.64#ibcon#read 3, iclass 3, count 0 2006.231.08:04:10.64#ibcon#about to read 4, iclass 3, count 0 2006.231.08:04:10.64#ibcon#read 4, iclass 3, count 0 2006.231.08:04:10.64#ibcon#about to read 5, iclass 3, count 0 2006.231.08:04:10.64#ibcon#read 5, iclass 3, count 0 2006.231.08:04:10.64#ibcon#about to read 6, iclass 3, count 0 2006.231.08:04:10.64#ibcon#read 6, iclass 3, count 0 2006.231.08:04:10.64#ibcon#end of sib2, iclass 3, count 0 2006.231.08:04:10.64#ibcon#*after write, iclass 3, count 0 2006.231.08:04:10.64#ibcon#*before return 0, iclass 3, count 0 2006.231.08:04:10.64#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:04:10.64#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:04:10.64#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:04:10.64#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:04:10.64$vc4f8/vb=1,4 2006.231.08:04:10.64#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.08:04:10.64#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.08:04:10.64#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:10.64#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:04:10.64#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:04:10.64#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:04:10.64#ibcon#enter wrdev, iclass 5, count 2 2006.231.08:04:10.64#ibcon#first serial, iclass 5, count 2 2006.231.08:04:10.65#ibcon#enter sib2, iclass 5, count 2 2006.231.08:04:10.65#ibcon#flushed, iclass 5, count 2 2006.231.08:04:10.65#ibcon#about to write, iclass 5, count 2 2006.231.08:04:10.65#ibcon#wrote, iclass 5, count 2 2006.231.08:04:10.65#ibcon#about to read 3, iclass 5, count 2 2006.231.08:04:10.66#ibcon#read 3, iclass 5, count 2 2006.231.08:04:10.66#ibcon#about to read 4, iclass 5, count 2 2006.231.08:04:10.66#ibcon#read 4, iclass 5, count 2 2006.231.08:04:10.66#ibcon#about to read 5, iclass 5, count 2 2006.231.08:04:10.66#ibcon#read 5, iclass 5, count 2 2006.231.08:04:10.66#ibcon#about to read 6, iclass 5, count 2 2006.231.08:04:10.66#ibcon#read 6, iclass 5, count 2 2006.231.08:04:10.66#ibcon#end of sib2, iclass 5, count 2 2006.231.08:04:10.66#ibcon#*mode == 0, iclass 5, count 2 2006.231.08:04:10.66#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.08:04:10.66#ibcon#[27=AT01-04\r\n] 2006.231.08:04:10.66#ibcon#*before write, iclass 5, count 2 2006.231.08:04:10.66#ibcon#enter sib2, iclass 5, count 2 2006.231.08:04:10.66#ibcon#flushed, iclass 5, count 2 2006.231.08:04:10.66#ibcon#about to write, iclass 5, count 2 2006.231.08:04:10.66#ibcon#wrote, iclass 5, count 2 2006.231.08:04:10.66#ibcon#about to read 3, iclass 5, count 2 2006.231.08:04:10.69#ibcon#read 3, iclass 5, count 2 2006.231.08:04:10.69#ibcon#about to read 4, iclass 5, count 2 2006.231.08:04:10.69#ibcon#read 4, iclass 5, count 2 2006.231.08:04:10.69#ibcon#about to read 5, iclass 5, count 2 2006.231.08:04:10.69#ibcon#read 5, iclass 5, count 2 2006.231.08:04:10.69#ibcon#about to read 6, iclass 5, count 2 2006.231.08:04:10.69#ibcon#read 6, iclass 5, count 2 2006.231.08:04:10.69#ibcon#end of sib2, iclass 5, count 2 2006.231.08:04:10.69#ibcon#*after write, iclass 5, count 2 2006.231.08:04:10.69#ibcon#*before return 0, iclass 5, count 2 2006.231.08:04:10.69#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:04:10.69#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:04:10.69#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.08:04:10.69#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:10.69#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:04:10.81#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:04:10.81#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:04:10.81#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:04:10.81#ibcon#first serial, iclass 5, count 0 2006.231.08:04:10.81#ibcon#enter sib2, iclass 5, count 0 2006.231.08:04:10.81#ibcon#flushed, iclass 5, count 0 2006.231.08:04:10.81#ibcon#about to write, iclass 5, count 0 2006.231.08:04:10.81#ibcon#wrote, iclass 5, count 0 2006.231.08:04:10.81#ibcon#about to read 3, iclass 5, count 0 2006.231.08:04:10.83#ibcon#read 3, iclass 5, count 0 2006.231.08:04:10.83#ibcon#about to read 4, iclass 5, count 0 2006.231.08:04:10.83#ibcon#read 4, iclass 5, count 0 2006.231.08:04:10.83#ibcon#about to read 5, iclass 5, count 0 2006.231.08:04:10.83#ibcon#read 5, iclass 5, count 0 2006.231.08:04:10.83#ibcon#about to read 6, iclass 5, count 0 2006.231.08:04:10.83#ibcon#read 6, iclass 5, count 0 2006.231.08:04:10.83#ibcon#end of sib2, iclass 5, count 0 2006.231.08:04:10.83#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:04:10.83#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:04:10.83#ibcon#[27=USB\r\n] 2006.231.08:04:10.83#ibcon#*before write, iclass 5, count 0 2006.231.08:04:10.83#ibcon#enter sib2, iclass 5, count 0 2006.231.08:04:10.83#ibcon#flushed, iclass 5, count 0 2006.231.08:04:10.83#ibcon#about to write, iclass 5, count 0 2006.231.08:04:10.83#ibcon#wrote, iclass 5, count 0 2006.231.08:04:10.83#ibcon#about to read 3, iclass 5, count 0 2006.231.08:04:10.86#ibcon#read 3, iclass 5, count 0 2006.231.08:04:10.86#ibcon#about to read 4, iclass 5, count 0 2006.231.08:04:10.86#ibcon#read 4, iclass 5, count 0 2006.231.08:04:10.86#ibcon#about to read 5, iclass 5, count 0 2006.231.08:04:10.86#ibcon#read 5, iclass 5, count 0 2006.231.08:04:10.86#ibcon#about to read 6, iclass 5, count 0 2006.231.08:04:10.86#ibcon#read 6, iclass 5, count 0 2006.231.08:04:10.86#ibcon#end of sib2, iclass 5, count 0 2006.231.08:04:10.86#ibcon#*after write, iclass 5, count 0 2006.231.08:04:10.86#ibcon#*before return 0, iclass 5, count 0 2006.231.08:04:10.86#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:04:10.86#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:04:10.86#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:04:10.86#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:04:10.86$vc4f8/vblo=2,640.99 2006.231.08:04:10.86#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.08:04:10.86#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.08:04:10.86#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:10.86#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:04:10.86#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:04:10.87#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:04:10.87#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:04:10.87#ibcon#first serial, iclass 7, count 0 2006.231.08:04:10.87#ibcon#enter sib2, iclass 7, count 0 2006.231.08:04:10.87#ibcon#flushed, iclass 7, count 0 2006.231.08:04:10.87#ibcon#about to write, iclass 7, count 0 2006.231.08:04:10.87#ibcon#wrote, iclass 7, count 0 2006.231.08:04:10.87#ibcon#about to read 3, iclass 7, count 0 2006.231.08:04:10.88#ibcon#read 3, iclass 7, count 0 2006.231.08:04:10.88#ibcon#about to read 4, iclass 7, count 0 2006.231.08:04:10.88#ibcon#read 4, iclass 7, count 0 2006.231.08:04:10.88#ibcon#about to read 5, iclass 7, count 0 2006.231.08:04:10.88#ibcon#read 5, iclass 7, count 0 2006.231.08:04:10.88#ibcon#about to read 6, iclass 7, count 0 2006.231.08:04:10.88#ibcon#read 6, iclass 7, count 0 2006.231.08:04:10.88#ibcon#end of sib2, iclass 7, count 0 2006.231.08:04:10.88#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:04:10.88#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:04:10.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:04:10.88#ibcon#*before write, iclass 7, count 0 2006.231.08:04:10.88#ibcon#enter sib2, iclass 7, count 0 2006.231.08:04:10.88#ibcon#flushed, iclass 7, count 0 2006.231.08:04:10.88#ibcon#about to write, iclass 7, count 0 2006.231.08:04:10.88#ibcon#wrote, iclass 7, count 0 2006.231.08:04:10.88#ibcon#about to read 3, iclass 7, count 0 2006.231.08:04:10.92#ibcon#read 3, iclass 7, count 0 2006.231.08:04:10.92#ibcon#about to read 4, iclass 7, count 0 2006.231.08:04:10.92#ibcon#read 4, iclass 7, count 0 2006.231.08:04:10.92#ibcon#about to read 5, iclass 7, count 0 2006.231.08:04:10.92#ibcon#read 5, iclass 7, count 0 2006.231.08:04:10.92#ibcon#about to read 6, iclass 7, count 0 2006.231.08:04:10.92#ibcon#read 6, iclass 7, count 0 2006.231.08:04:10.92#ibcon#end of sib2, iclass 7, count 0 2006.231.08:04:10.92#ibcon#*after write, iclass 7, count 0 2006.231.08:04:10.92#ibcon#*before return 0, iclass 7, count 0 2006.231.08:04:10.92#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:04:10.92#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:04:10.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:04:10.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:04:10.92$vc4f8/vb=2,4 2006.231.08:04:10.92#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.08:04:10.92#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.08:04:10.93#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:10.93#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:04:10.97#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:04:10.97#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:04:10.97#ibcon#enter wrdev, iclass 11, count 2 2006.231.08:04:10.97#ibcon#first serial, iclass 11, count 2 2006.231.08:04:10.97#ibcon#enter sib2, iclass 11, count 2 2006.231.08:04:10.97#ibcon#flushed, iclass 11, count 2 2006.231.08:04:10.97#ibcon#about to write, iclass 11, count 2 2006.231.08:04:10.97#ibcon#wrote, iclass 11, count 2 2006.231.08:04:10.97#ibcon#about to read 3, iclass 11, count 2 2006.231.08:04:10.99#ibcon#read 3, iclass 11, count 2 2006.231.08:04:10.99#ibcon#about to read 4, iclass 11, count 2 2006.231.08:04:10.99#ibcon#read 4, iclass 11, count 2 2006.231.08:04:10.99#ibcon#about to read 5, iclass 11, count 2 2006.231.08:04:10.99#ibcon#read 5, iclass 11, count 2 2006.231.08:04:10.99#ibcon#about to read 6, iclass 11, count 2 2006.231.08:04:10.99#ibcon#read 6, iclass 11, count 2 2006.231.08:04:10.99#ibcon#end of sib2, iclass 11, count 2 2006.231.08:04:10.99#ibcon#*mode == 0, iclass 11, count 2 2006.231.08:04:10.99#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.08:04:10.99#ibcon#[27=AT02-04\r\n] 2006.231.08:04:10.99#ibcon#*before write, iclass 11, count 2 2006.231.08:04:10.99#ibcon#enter sib2, iclass 11, count 2 2006.231.08:04:10.99#ibcon#flushed, iclass 11, count 2 2006.231.08:04:10.99#ibcon#about to write, iclass 11, count 2 2006.231.08:04:10.99#ibcon#wrote, iclass 11, count 2 2006.231.08:04:10.99#ibcon#about to read 3, iclass 11, count 2 2006.231.08:04:11.02#ibcon#read 3, iclass 11, count 2 2006.231.08:04:11.02#ibcon#about to read 4, iclass 11, count 2 2006.231.08:04:11.02#ibcon#read 4, iclass 11, count 2 2006.231.08:04:11.02#ibcon#about to read 5, iclass 11, count 2 2006.231.08:04:11.02#ibcon#read 5, iclass 11, count 2 2006.231.08:04:11.02#ibcon#about to read 6, iclass 11, count 2 2006.231.08:04:11.02#ibcon#read 6, iclass 11, count 2 2006.231.08:04:11.02#ibcon#end of sib2, iclass 11, count 2 2006.231.08:04:11.02#ibcon#*after write, iclass 11, count 2 2006.231.08:04:11.02#ibcon#*before return 0, iclass 11, count 2 2006.231.08:04:11.02#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:04:11.02#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:04:11.02#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.08:04:11.02#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:11.02#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:04:11.15#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:04:11.15#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:04:11.15#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:04:11.15#ibcon#first serial, iclass 11, count 0 2006.231.08:04:11.15#ibcon#enter sib2, iclass 11, count 0 2006.231.08:04:11.15#ibcon#flushed, iclass 11, count 0 2006.231.08:04:11.15#ibcon#about to write, iclass 11, count 0 2006.231.08:04:11.15#ibcon#wrote, iclass 11, count 0 2006.231.08:04:11.15#ibcon#about to read 3, iclass 11, count 0 2006.231.08:04:11.17#ibcon#read 3, iclass 11, count 0 2006.231.08:04:11.17#ibcon#about to read 4, iclass 11, count 0 2006.231.08:04:11.17#ibcon#read 4, iclass 11, count 0 2006.231.08:04:11.17#ibcon#about to read 5, iclass 11, count 0 2006.231.08:04:11.17#ibcon#read 5, iclass 11, count 0 2006.231.08:04:11.17#ibcon#about to read 6, iclass 11, count 0 2006.231.08:04:11.17#ibcon#read 6, iclass 11, count 0 2006.231.08:04:11.17#ibcon#end of sib2, iclass 11, count 0 2006.231.08:04:11.17#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:04:11.17#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:04:11.17#ibcon#[27=USB\r\n] 2006.231.08:04:11.17#ibcon#*before write, iclass 11, count 0 2006.231.08:04:11.17#ibcon#enter sib2, iclass 11, count 0 2006.231.08:04:11.17#ibcon#flushed, iclass 11, count 0 2006.231.08:04:11.17#ibcon#about to write, iclass 11, count 0 2006.231.08:04:11.17#ibcon#wrote, iclass 11, count 0 2006.231.08:04:11.17#ibcon#about to read 3, iclass 11, count 0 2006.231.08:04:11.19#ibcon#read 3, iclass 11, count 0 2006.231.08:04:11.19#ibcon#about to read 4, iclass 11, count 0 2006.231.08:04:11.19#ibcon#read 4, iclass 11, count 0 2006.231.08:04:11.19#ibcon#about to read 5, iclass 11, count 0 2006.231.08:04:11.19#ibcon#read 5, iclass 11, count 0 2006.231.08:04:11.19#ibcon#about to read 6, iclass 11, count 0 2006.231.08:04:11.19#ibcon#read 6, iclass 11, count 0 2006.231.08:04:11.19#ibcon#end of sib2, iclass 11, count 0 2006.231.08:04:11.19#ibcon#*after write, iclass 11, count 0 2006.231.08:04:11.19#ibcon#*before return 0, iclass 11, count 0 2006.231.08:04:11.19#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:04:11.19#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:04:11.19#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:04:11.19#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:04:11.19$vc4f8/vblo=3,656.99 2006.231.08:04:11.19#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.08:04:11.19#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.08:04:11.20#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:11.20#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:04:11.20#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:04:11.20#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:04:11.20#ibcon#enter wrdev, iclass 13, count 0 2006.231.08:04:11.20#ibcon#first serial, iclass 13, count 0 2006.231.08:04:11.20#ibcon#enter sib2, iclass 13, count 0 2006.231.08:04:11.20#ibcon#flushed, iclass 13, count 0 2006.231.08:04:11.20#ibcon#about to write, iclass 13, count 0 2006.231.08:04:11.20#ibcon#wrote, iclass 13, count 0 2006.231.08:04:11.20#ibcon#about to read 3, iclass 13, count 0 2006.231.08:04:11.21#ibcon#read 3, iclass 13, count 0 2006.231.08:04:11.21#ibcon#about to read 4, iclass 13, count 0 2006.231.08:04:11.21#ibcon#read 4, iclass 13, count 0 2006.231.08:04:11.21#ibcon#about to read 5, iclass 13, count 0 2006.231.08:04:11.21#ibcon#read 5, iclass 13, count 0 2006.231.08:04:11.21#ibcon#about to read 6, iclass 13, count 0 2006.231.08:04:11.21#ibcon#read 6, iclass 13, count 0 2006.231.08:04:11.21#ibcon#end of sib2, iclass 13, count 0 2006.231.08:04:11.21#ibcon#*mode == 0, iclass 13, count 0 2006.231.08:04:11.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.08:04:11.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:04:11.21#ibcon#*before write, iclass 13, count 0 2006.231.08:04:11.21#ibcon#enter sib2, iclass 13, count 0 2006.231.08:04:11.21#ibcon#flushed, iclass 13, count 0 2006.231.08:04:11.21#ibcon#about to write, iclass 13, count 0 2006.231.08:04:11.21#ibcon#wrote, iclass 13, count 0 2006.231.08:04:11.21#ibcon#about to read 3, iclass 13, count 0 2006.231.08:04:11.25#ibcon#read 3, iclass 13, count 0 2006.231.08:04:11.25#ibcon#about to read 4, iclass 13, count 0 2006.231.08:04:11.25#ibcon#read 4, iclass 13, count 0 2006.231.08:04:11.25#ibcon#about to read 5, iclass 13, count 0 2006.231.08:04:11.25#ibcon#read 5, iclass 13, count 0 2006.231.08:04:11.25#ibcon#about to read 6, iclass 13, count 0 2006.231.08:04:11.25#ibcon#read 6, iclass 13, count 0 2006.231.08:04:11.25#ibcon#end of sib2, iclass 13, count 0 2006.231.08:04:11.25#ibcon#*after write, iclass 13, count 0 2006.231.08:04:11.25#ibcon#*before return 0, iclass 13, count 0 2006.231.08:04:11.25#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:04:11.25#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:04:11.25#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.08:04:11.25#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.08:04:11.25$vc4f8/vb=3,4 2006.231.08:04:11.25#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.08:04:11.25#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.08:04:11.25#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:11.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:04:11.30#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:04:11.30#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:04:11.30#ibcon#enter wrdev, iclass 15, count 2 2006.231.08:04:11.30#ibcon#first serial, iclass 15, count 2 2006.231.08:04:11.30#ibcon#enter sib2, iclass 15, count 2 2006.231.08:04:11.30#ibcon#flushed, iclass 15, count 2 2006.231.08:04:11.30#ibcon#about to write, iclass 15, count 2 2006.231.08:04:11.30#ibcon#wrote, iclass 15, count 2 2006.231.08:04:11.30#ibcon#about to read 3, iclass 15, count 2 2006.231.08:04:11.32#ibcon#read 3, iclass 15, count 2 2006.231.08:04:11.32#ibcon#about to read 4, iclass 15, count 2 2006.231.08:04:11.32#ibcon#read 4, iclass 15, count 2 2006.231.08:04:11.32#ibcon#about to read 5, iclass 15, count 2 2006.231.08:04:11.32#ibcon#read 5, iclass 15, count 2 2006.231.08:04:11.32#ibcon#about to read 6, iclass 15, count 2 2006.231.08:04:11.32#ibcon#read 6, iclass 15, count 2 2006.231.08:04:11.32#ibcon#end of sib2, iclass 15, count 2 2006.231.08:04:11.32#ibcon#*mode == 0, iclass 15, count 2 2006.231.08:04:11.32#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.08:04:11.32#ibcon#[27=AT03-04\r\n] 2006.231.08:04:11.32#ibcon#*before write, iclass 15, count 2 2006.231.08:04:11.32#ibcon#enter sib2, iclass 15, count 2 2006.231.08:04:11.32#ibcon#flushed, iclass 15, count 2 2006.231.08:04:11.32#ibcon#about to write, iclass 15, count 2 2006.231.08:04:11.32#ibcon#wrote, iclass 15, count 2 2006.231.08:04:11.32#ibcon#about to read 3, iclass 15, count 2 2006.231.08:04:11.35#ibcon#read 3, iclass 15, count 2 2006.231.08:04:11.35#ibcon#about to read 4, iclass 15, count 2 2006.231.08:04:11.35#ibcon#read 4, iclass 15, count 2 2006.231.08:04:11.35#ibcon#about to read 5, iclass 15, count 2 2006.231.08:04:11.35#ibcon#read 5, iclass 15, count 2 2006.231.08:04:11.35#ibcon#about to read 6, iclass 15, count 2 2006.231.08:04:11.35#ibcon#read 6, iclass 15, count 2 2006.231.08:04:11.35#ibcon#end of sib2, iclass 15, count 2 2006.231.08:04:11.35#ibcon#*after write, iclass 15, count 2 2006.231.08:04:11.35#ibcon#*before return 0, iclass 15, count 2 2006.231.08:04:11.35#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:04:11.35#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:04:11.35#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.08:04:11.35#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:11.35#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:04:11.47#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:04:11.47#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:04:11.47#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:04:11.47#ibcon#first serial, iclass 15, count 0 2006.231.08:04:11.47#ibcon#enter sib2, iclass 15, count 0 2006.231.08:04:11.47#ibcon#flushed, iclass 15, count 0 2006.231.08:04:11.47#ibcon#about to write, iclass 15, count 0 2006.231.08:04:11.47#ibcon#wrote, iclass 15, count 0 2006.231.08:04:11.47#ibcon#about to read 3, iclass 15, count 0 2006.231.08:04:11.49#ibcon#read 3, iclass 15, count 0 2006.231.08:04:11.49#ibcon#about to read 4, iclass 15, count 0 2006.231.08:04:11.49#ibcon#read 4, iclass 15, count 0 2006.231.08:04:11.49#ibcon#about to read 5, iclass 15, count 0 2006.231.08:04:11.49#ibcon#read 5, iclass 15, count 0 2006.231.08:04:11.49#ibcon#about to read 6, iclass 15, count 0 2006.231.08:04:11.49#ibcon#read 6, iclass 15, count 0 2006.231.08:04:11.49#ibcon#end of sib2, iclass 15, count 0 2006.231.08:04:11.49#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:04:11.49#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:04:11.49#ibcon#[27=USB\r\n] 2006.231.08:04:11.49#ibcon#*before write, iclass 15, count 0 2006.231.08:04:11.49#ibcon#enter sib2, iclass 15, count 0 2006.231.08:04:11.49#ibcon#flushed, iclass 15, count 0 2006.231.08:04:11.49#ibcon#about to write, iclass 15, count 0 2006.231.08:04:11.49#ibcon#wrote, iclass 15, count 0 2006.231.08:04:11.49#ibcon#about to read 3, iclass 15, count 0 2006.231.08:04:11.52#ibcon#read 3, iclass 15, count 0 2006.231.08:04:11.52#ibcon#about to read 4, iclass 15, count 0 2006.231.08:04:11.52#ibcon#read 4, iclass 15, count 0 2006.231.08:04:11.52#ibcon#about to read 5, iclass 15, count 0 2006.231.08:04:11.52#ibcon#read 5, iclass 15, count 0 2006.231.08:04:11.52#ibcon#about to read 6, iclass 15, count 0 2006.231.08:04:11.52#ibcon#read 6, iclass 15, count 0 2006.231.08:04:11.52#ibcon#end of sib2, iclass 15, count 0 2006.231.08:04:11.52#ibcon#*after write, iclass 15, count 0 2006.231.08:04:11.52#ibcon#*before return 0, iclass 15, count 0 2006.231.08:04:11.52#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:04:11.52#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:04:11.52#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:04:11.52#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:04:11.52$vc4f8/vblo=4,712.99 2006.231.08:04:11.52#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.08:04:11.53#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.08:04:11.53#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:11.53#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:04:11.53#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:04:11.53#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:04:11.53#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:04:11.53#ibcon#first serial, iclass 17, count 0 2006.231.08:04:11.53#ibcon#enter sib2, iclass 17, count 0 2006.231.08:04:11.53#ibcon#flushed, iclass 17, count 0 2006.231.08:04:11.53#ibcon#about to write, iclass 17, count 0 2006.231.08:04:11.53#ibcon#wrote, iclass 17, count 0 2006.231.08:04:11.53#ibcon#about to read 3, iclass 17, count 0 2006.231.08:04:11.54#ibcon#read 3, iclass 17, count 0 2006.231.08:04:11.54#ibcon#about to read 4, iclass 17, count 0 2006.231.08:04:11.54#ibcon#read 4, iclass 17, count 0 2006.231.08:04:11.54#ibcon#about to read 5, iclass 17, count 0 2006.231.08:04:11.54#ibcon#read 5, iclass 17, count 0 2006.231.08:04:11.54#ibcon#about to read 6, iclass 17, count 0 2006.231.08:04:11.54#ibcon#read 6, iclass 17, count 0 2006.231.08:04:11.54#ibcon#end of sib2, iclass 17, count 0 2006.231.08:04:11.54#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:04:11.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:04:11.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:04:11.54#ibcon#*before write, iclass 17, count 0 2006.231.08:04:11.54#ibcon#enter sib2, iclass 17, count 0 2006.231.08:04:11.54#ibcon#flushed, iclass 17, count 0 2006.231.08:04:11.54#ibcon#about to write, iclass 17, count 0 2006.231.08:04:11.54#ibcon#wrote, iclass 17, count 0 2006.231.08:04:11.54#ibcon#about to read 3, iclass 17, count 0 2006.231.08:04:11.58#ibcon#read 3, iclass 17, count 0 2006.231.08:04:11.58#ibcon#about to read 4, iclass 17, count 0 2006.231.08:04:11.58#ibcon#read 4, iclass 17, count 0 2006.231.08:04:11.58#ibcon#about to read 5, iclass 17, count 0 2006.231.08:04:11.58#ibcon#read 5, iclass 17, count 0 2006.231.08:04:11.58#ibcon#about to read 6, iclass 17, count 0 2006.231.08:04:11.58#ibcon#read 6, iclass 17, count 0 2006.231.08:04:11.58#ibcon#end of sib2, iclass 17, count 0 2006.231.08:04:11.58#ibcon#*after write, iclass 17, count 0 2006.231.08:04:11.58#ibcon#*before return 0, iclass 17, count 0 2006.231.08:04:11.58#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:04:11.58#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:04:11.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:04:11.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:04:11.58$vc4f8/vb=4,4 2006.231.08:04:11.58#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.231.08:04:11.58#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.231.08:04:11.58#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:11.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:04:11.64#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:04:11.64#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:04:11.64#ibcon#enter wrdev, iclass 19, count 2 2006.231.08:04:11.64#ibcon#first serial, iclass 19, count 2 2006.231.08:04:11.64#ibcon#enter sib2, iclass 19, count 2 2006.231.08:04:11.64#ibcon#flushed, iclass 19, count 2 2006.231.08:04:11.64#ibcon#about to write, iclass 19, count 2 2006.231.08:04:11.64#ibcon#wrote, iclass 19, count 2 2006.231.08:04:11.64#ibcon#about to read 3, iclass 19, count 2 2006.231.08:04:11.66#ibcon#read 3, iclass 19, count 2 2006.231.08:04:11.66#ibcon#about to read 4, iclass 19, count 2 2006.231.08:04:11.66#ibcon#read 4, iclass 19, count 2 2006.231.08:04:11.66#ibcon#about to read 5, iclass 19, count 2 2006.231.08:04:11.66#ibcon#read 5, iclass 19, count 2 2006.231.08:04:11.66#ibcon#about to read 6, iclass 19, count 2 2006.231.08:04:11.66#ibcon#read 6, iclass 19, count 2 2006.231.08:04:11.66#ibcon#end of sib2, iclass 19, count 2 2006.231.08:04:11.66#ibcon#*mode == 0, iclass 19, count 2 2006.231.08:04:11.66#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.231.08:04:11.66#ibcon#[27=AT04-04\r\n] 2006.231.08:04:11.66#ibcon#*before write, iclass 19, count 2 2006.231.08:04:11.66#ibcon#enter sib2, iclass 19, count 2 2006.231.08:04:11.66#ibcon#flushed, iclass 19, count 2 2006.231.08:04:11.66#ibcon#about to write, iclass 19, count 2 2006.231.08:04:11.66#ibcon#wrote, iclass 19, count 2 2006.231.08:04:11.66#ibcon#about to read 3, iclass 19, count 2 2006.231.08:04:11.69#ibcon#read 3, iclass 19, count 2 2006.231.08:04:11.69#ibcon#about to read 4, iclass 19, count 2 2006.231.08:04:11.69#ibcon#read 4, iclass 19, count 2 2006.231.08:04:11.69#ibcon#about to read 5, iclass 19, count 2 2006.231.08:04:11.69#ibcon#read 5, iclass 19, count 2 2006.231.08:04:11.69#ibcon#about to read 6, iclass 19, count 2 2006.231.08:04:11.69#ibcon#read 6, iclass 19, count 2 2006.231.08:04:11.69#ibcon#end of sib2, iclass 19, count 2 2006.231.08:04:11.69#ibcon#*after write, iclass 19, count 2 2006.231.08:04:11.69#ibcon#*before return 0, iclass 19, count 2 2006.231.08:04:11.69#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:04:11.69#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:04:11.69#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.231.08:04:11.69#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:11.69#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:04:11.81#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:04:11.81#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:04:11.81#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:04:11.81#ibcon#first serial, iclass 19, count 0 2006.231.08:04:11.81#ibcon#enter sib2, iclass 19, count 0 2006.231.08:04:11.81#ibcon#flushed, iclass 19, count 0 2006.231.08:04:11.81#ibcon#about to write, iclass 19, count 0 2006.231.08:04:11.81#ibcon#wrote, iclass 19, count 0 2006.231.08:04:11.81#ibcon#about to read 3, iclass 19, count 0 2006.231.08:04:11.84#ibcon#read 3, iclass 19, count 0 2006.231.08:04:11.84#ibcon#about to read 4, iclass 19, count 0 2006.231.08:04:11.84#ibcon#read 4, iclass 19, count 0 2006.231.08:04:11.84#ibcon#about to read 5, iclass 19, count 0 2006.231.08:04:11.84#ibcon#read 5, iclass 19, count 0 2006.231.08:04:11.84#ibcon#about to read 6, iclass 19, count 0 2006.231.08:04:11.84#ibcon#read 6, iclass 19, count 0 2006.231.08:04:11.84#ibcon#end of sib2, iclass 19, count 0 2006.231.08:04:11.84#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:04:11.84#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:04:11.84#ibcon#[27=USB\r\n] 2006.231.08:04:11.84#ibcon#*before write, iclass 19, count 0 2006.231.08:04:11.84#ibcon#enter sib2, iclass 19, count 0 2006.231.08:04:11.84#ibcon#flushed, iclass 19, count 0 2006.231.08:04:11.84#ibcon#about to write, iclass 19, count 0 2006.231.08:04:11.84#ibcon#wrote, iclass 19, count 0 2006.231.08:04:11.84#ibcon#about to read 3, iclass 19, count 0 2006.231.08:04:11.86#ibcon#read 3, iclass 19, count 0 2006.231.08:04:11.86#ibcon#about to read 4, iclass 19, count 0 2006.231.08:04:11.86#ibcon#read 4, iclass 19, count 0 2006.231.08:04:11.86#ibcon#about to read 5, iclass 19, count 0 2006.231.08:04:11.86#ibcon#read 5, iclass 19, count 0 2006.231.08:04:11.86#ibcon#about to read 6, iclass 19, count 0 2006.231.08:04:11.86#ibcon#read 6, iclass 19, count 0 2006.231.08:04:11.86#ibcon#end of sib2, iclass 19, count 0 2006.231.08:04:11.86#ibcon#*after write, iclass 19, count 0 2006.231.08:04:11.86#ibcon#*before return 0, iclass 19, count 0 2006.231.08:04:11.86#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:04:11.86#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:04:11.86#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:04:11.86#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:04:11.86$vc4f8/vblo=5,744.99 2006.231.08:04:11.86#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.08:04:11.86#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.08:04:11.86#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:11.86#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:04:11.86#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:04:11.86#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:04:11.86#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:04:11.86#ibcon#first serial, iclass 21, count 0 2006.231.08:04:11.87#ibcon#enter sib2, iclass 21, count 0 2006.231.08:04:11.87#ibcon#flushed, iclass 21, count 0 2006.231.08:04:11.87#ibcon#about to write, iclass 21, count 0 2006.231.08:04:11.87#ibcon#wrote, iclass 21, count 0 2006.231.08:04:11.87#ibcon#about to read 3, iclass 21, count 0 2006.231.08:04:11.88#ibcon#read 3, iclass 21, count 0 2006.231.08:04:11.88#ibcon#about to read 4, iclass 21, count 0 2006.231.08:04:11.88#ibcon#read 4, iclass 21, count 0 2006.231.08:04:11.88#ibcon#about to read 5, iclass 21, count 0 2006.231.08:04:11.88#ibcon#read 5, iclass 21, count 0 2006.231.08:04:11.88#ibcon#about to read 6, iclass 21, count 0 2006.231.08:04:11.88#ibcon#read 6, iclass 21, count 0 2006.231.08:04:11.88#ibcon#end of sib2, iclass 21, count 0 2006.231.08:04:11.88#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:04:11.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:04:11.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:04:11.88#ibcon#*before write, iclass 21, count 0 2006.231.08:04:11.88#ibcon#enter sib2, iclass 21, count 0 2006.231.08:04:11.88#ibcon#flushed, iclass 21, count 0 2006.231.08:04:11.88#ibcon#about to write, iclass 21, count 0 2006.231.08:04:11.88#ibcon#wrote, iclass 21, count 0 2006.231.08:04:11.88#ibcon#about to read 3, iclass 21, count 0 2006.231.08:04:11.92#ibcon#read 3, iclass 21, count 0 2006.231.08:04:11.92#ibcon#about to read 4, iclass 21, count 0 2006.231.08:04:11.92#ibcon#read 4, iclass 21, count 0 2006.231.08:04:11.92#ibcon#about to read 5, iclass 21, count 0 2006.231.08:04:11.92#ibcon#read 5, iclass 21, count 0 2006.231.08:04:11.92#ibcon#about to read 6, iclass 21, count 0 2006.231.08:04:11.92#ibcon#read 6, iclass 21, count 0 2006.231.08:04:11.92#ibcon#end of sib2, iclass 21, count 0 2006.231.08:04:11.92#ibcon#*after write, iclass 21, count 0 2006.231.08:04:11.92#ibcon#*before return 0, iclass 21, count 0 2006.231.08:04:11.92#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:04:11.92#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:04:11.92#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:04:11.92#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:04:11.92$vc4f8/vb=5,3 2006.231.08:04:11.92#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.231.08:04:11.92#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.231.08:04:11.92#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:11.93#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:04:11.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:04:11.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:04:11.97#ibcon#enter wrdev, iclass 23, count 2 2006.231.08:04:11.97#ibcon#first serial, iclass 23, count 2 2006.231.08:04:11.97#ibcon#enter sib2, iclass 23, count 2 2006.231.08:04:11.97#ibcon#flushed, iclass 23, count 2 2006.231.08:04:11.97#ibcon#about to write, iclass 23, count 2 2006.231.08:04:11.97#ibcon#wrote, iclass 23, count 2 2006.231.08:04:11.97#ibcon#about to read 3, iclass 23, count 2 2006.231.08:04:11.99#ibcon#read 3, iclass 23, count 2 2006.231.08:04:11.99#ibcon#about to read 4, iclass 23, count 2 2006.231.08:04:11.99#ibcon#read 4, iclass 23, count 2 2006.231.08:04:11.99#ibcon#about to read 5, iclass 23, count 2 2006.231.08:04:11.99#ibcon#read 5, iclass 23, count 2 2006.231.08:04:11.99#ibcon#about to read 6, iclass 23, count 2 2006.231.08:04:11.99#ibcon#read 6, iclass 23, count 2 2006.231.08:04:11.99#ibcon#end of sib2, iclass 23, count 2 2006.231.08:04:11.99#ibcon#*mode == 0, iclass 23, count 2 2006.231.08:04:11.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.231.08:04:11.99#ibcon#[27=AT05-03\r\n] 2006.231.08:04:11.99#ibcon#*before write, iclass 23, count 2 2006.231.08:04:11.99#ibcon#enter sib2, iclass 23, count 2 2006.231.08:04:11.99#ibcon#flushed, iclass 23, count 2 2006.231.08:04:11.99#ibcon#about to write, iclass 23, count 2 2006.231.08:04:11.99#ibcon#wrote, iclass 23, count 2 2006.231.08:04:11.99#ibcon#about to read 3, iclass 23, count 2 2006.231.08:04:12.02#ibcon#read 3, iclass 23, count 2 2006.231.08:04:12.02#ibcon#about to read 4, iclass 23, count 2 2006.231.08:04:12.02#ibcon#read 4, iclass 23, count 2 2006.231.08:04:12.02#ibcon#about to read 5, iclass 23, count 2 2006.231.08:04:12.02#ibcon#read 5, iclass 23, count 2 2006.231.08:04:12.02#ibcon#about to read 6, iclass 23, count 2 2006.231.08:04:12.02#ibcon#read 6, iclass 23, count 2 2006.231.08:04:12.02#ibcon#end of sib2, iclass 23, count 2 2006.231.08:04:12.02#ibcon#*after write, iclass 23, count 2 2006.231.08:04:12.02#ibcon#*before return 0, iclass 23, count 2 2006.231.08:04:12.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:04:12.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:04:12.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.231.08:04:12.02#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:12.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:04:12.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:04:12.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:04:12.14#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:04:12.14#ibcon#first serial, iclass 23, count 0 2006.231.08:04:12.14#ibcon#enter sib2, iclass 23, count 0 2006.231.08:04:12.14#ibcon#flushed, iclass 23, count 0 2006.231.08:04:12.14#ibcon#about to write, iclass 23, count 0 2006.231.08:04:12.14#ibcon#wrote, iclass 23, count 0 2006.231.08:04:12.14#ibcon#about to read 3, iclass 23, count 0 2006.231.08:04:12.16#ibcon#read 3, iclass 23, count 0 2006.231.08:04:12.16#ibcon#about to read 4, iclass 23, count 0 2006.231.08:04:12.16#ibcon#read 4, iclass 23, count 0 2006.231.08:04:12.16#ibcon#about to read 5, iclass 23, count 0 2006.231.08:04:12.16#ibcon#read 5, iclass 23, count 0 2006.231.08:04:12.16#ibcon#about to read 6, iclass 23, count 0 2006.231.08:04:12.16#ibcon#read 6, iclass 23, count 0 2006.231.08:04:12.16#ibcon#end of sib2, iclass 23, count 0 2006.231.08:04:12.16#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:04:12.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:04:12.16#ibcon#[27=USB\r\n] 2006.231.08:04:12.16#ibcon#*before write, iclass 23, count 0 2006.231.08:04:12.16#ibcon#enter sib2, iclass 23, count 0 2006.231.08:04:12.16#ibcon#flushed, iclass 23, count 0 2006.231.08:04:12.16#ibcon#about to write, iclass 23, count 0 2006.231.08:04:12.16#ibcon#wrote, iclass 23, count 0 2006.231.08:04:12.16#ibcon#about to read 3, iclass 23, count 0 2006.231.08:04:12.19#ibcon#read 3, iclass 23, count 0 2006.231.08:04:12.19#ibcon#about to read 4, iclass 23, count 0 2006.231.08:04:12.19#ibcon#read 4, iclass 23, count 0 2006.231.08:04:12.19#ibcon#about to read 5, iclass 23, count 0 2006.231.08:04:12.19#ibcon#read 5, iclass 23, count 0 2006.231.08:04:12.19#ibcon#about to read 6, iclass 23, count 0 2006.231.08:04:12.19#ibcon#read 6, iclass 23, count 0 2006.231.08:04:12.19#ibcon#end of sib2, iclass 23, count 0 2006.231.08:04:12.19#ibcon#*after write, iclass 23, count 0 2006.231.08:04:12.19#ibcon#*before return 0, iclass 23, count 0 2006.231.08:04:12.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:04:12.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:04:12.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:04:12.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:04:12.19$vc4f8/vblo=6,752.99 2006.231.08:04:12.20#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.231.08:04:12.20#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.231.08:04:12.20#ibcon#ireg 17 cls_cnt 0 2006.231.08:04:12.20#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:04:12.20#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:04:12.20#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:04:12.20#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:04:12.20#ibcon#first serial, iclass 25, count 0 2006.231.08:04:12.20#ibcon#enter sib2, iclass 25, count 0 2006.231.08:04:12.20#ibcon#flushed, iclass 25, count 0 2006.231.08:04:12.20#ibcon#about to write, iclass 25, count 0 2006.231.08:04:12.20#ibcon#wrote, iclass 25, count 0 2006.231.08:04:12.20#ibcon#about to read 3, iclass 25, count 0 2006.231.08:04:12.21#ibcon#read 3, iclass 25, count 0 2006.231.08:04:12.21#ibcon#about to read 4, iclass 25, count 0 2006.231.08:04:12.21#ibcon#read 4, iclass 25, count 0 2006.231.08:04:12.21#ibcon#about to read 5, iclass 25, count 0 2006.231.08:04:12.21#ibcon#read 5, iclass 25, count 0 2006.231.08:04:12.21#ibcon#about to read 6, iclass 25, count 0 2006.231.08:04:12.21#ibcon#read 6, iclass 25, count 0 2006.231.08:04:12.21#ibcon#end of sib2, iclass 25, count 0 2006.231.08:04:12.21#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:04:12.21#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:04:12.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:04:12.21#ibcon#*before write, iclass 25, count 0 2006.231.08:04:12.21#ibcon#enter sib2, iclass 25, count 0 2006.231.08:04:12.21#ibcon#flushed, iclass 25, count 0 2006.231.08:04:12.21#ibcon#about to write, iclass 25, count 0 2006.231.08:04:12.21#ibcon#wrote, iclass 25, count 0 2006.231.08:04:12.21#ibcon#about to read 3, iclass 25, count 0 2006.231.08:04:12.25#ibcon#read 3, iclass 25, count 0 2006.231.08:04:12.25#ibcon#about to read 4, iclass 25, count 0 2006.231.08:04:12.25#ibcon#read 4, iclass 25, count 0 2006.231.08:04:12.25#ibcon#about to read 5, iclass 25, count 0 2006.231.08:04:12.25#ibcon#read 5, iclass 25, count 0 2006.231.08:04:12.25#ibcon#about to read 6, iclass 25, count 0 2006.231.08:04:12.25#ibcon#read 6, iclass 25, count 0 2006.231.08:04:12.25#ibcon#end of sib2, iclass 25, count 0 2006.231.08:04:12.25#ibcon#*after write, iclass 25, count 0 2006.231.08:04:12.25#ibcon#*before return 0, iclass 25, count 0 2006.231.08:04:12.25#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:04:12.25#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:04:12.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:04:12.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:04:12.25$vc4f8/vb=6,4 2006.231.08:04:12.25#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.231.08:04:12.25#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.231.08:04:12.25#ibcon#ireg 11 cls_cnt 2 2006.231.08:04:12.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:04:12.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:04:12.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:04:12.31#ibcon#enter wrdev, iclass 27, count 2 2006.231.08:04:12.31#ibcon#first serial, iclass 27, count 2 2006.231.08:04:12.31#ibcon#enter sib2, iclass 27, count 2 2006.231.08:04:12.31#ibcon#flushed, iclass 27, count 2 2006.231.08:04:12.31#ibcon#about to write, iclass 27, count 2 2006.231.08:04:12.31#ibcon#wrote, iclass 27, count 2 2006.231.08:04:12.31#ibcon#about to read 3, iclass 27, count 2 2006.231.08:04:12.33#ibcon#read 3, iclass 27, count 2 2006.231.08:04:12.33#ibcon#about to read 4, iclass 27, count 2 2006.231.08:04:12.33#ibcon#read 4, iclass 27, count 2 2006.231.08:04:12.33#ibcon#about to read 5, iclass 27, count 2 2006.231.08:04:12.33#ibcon#read 5, iclass 27, count 2 2006.231.08:04:12.33#ibcon#about to read 6, iclass 27, count 2 2006.231.08:04:12.33#ibcon#read 6, iclass 27, count 2 2006.231.08:04:12.33#ibcon#end of sib2, iclass 27, count 2 2006.231.08:04:12.33#ibcon#*mode == 0, iclass 27, count 2 2006.231.08:04:12.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.231.08:04:12.33#ibcon#[27=AT06-04\r\n] 2006.231.08:04:12.33#ibcon#*before write, iclass 27, count 2 2006.231.08:04:12.33#ibcon#enter sib2, iclass 27, count 2 2006.231.08:04:12.33#ibcon#flushed, iclass 27, count 2 2006.231.08:04:12.33#ibcon#about to write, iclass 27, count 2 2006.231.08:04:12.33#ibcon#wrote, iclass 27, count 2 2006.231.08:04:12.33#ibcon#about to read 3, iclass 27, count 2 2006.231.08:04:12.36#ibcon#read 3, iclass 27, count 2 2006.231.08:04:12.36#ibcon#about to read 4, iclass 27, count 2 2006.231.08:04:12.36#ibcon#read 4, iclass 27, count 2 2006.231.08:04:12.36#ibcon#about to read 5, iclass 27, count 2 2006.231.08:04:12.36#ibcon#read 5, iclass 27, count 2 2006.231.08:04:12.36#ibcon#about to read 6, iclass 27, count 2 2006.231.08:04:12.36#ibcon#read 6, iclass 27, count 2 2006.231.08:04:12.36#ibcon#end of sib2, iclass 27, count 2 2006.231.08:04:12.36#ibcon#*after write, iclass 27, count 2 2006.231.08:04:12.36#ibcon#*before return 0, iclass 27, count 2 2006.231.08:04:12.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:04:12.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:04:12.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.231.08:04:12.36#ibcon#ireg 7 cls_cnt 0 2006.231.08:04:12.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:04:12.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:04:12.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:04:12.48#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:04:12.48#ibcon#first serial, iclass 27, count 0 2006.231.08:04:12.48#ibcon#enter sib2, iclass 27, count 0 2006.231.08:04:12.48#ibcon#flushed, iclass 27, count 0 2006.231.08:04:12.48#ibcon#about to write, iclass 27, count 0 2006.231.08:04:12.48#ibcon#wrote, iclass 27, count 0 2006.231.08:04:12.48#ibcon#about to read 3, iclass 27, count 0 2006.231.08:04:12.50#ibcon#read 3, iclass 27, count 0 2006.231.08:04:12.50#ibcon#about to read 4, iclass 27, count 0 2006.231.08:04:12.50#ibcon#read 4, iclass 27, count 0 2006.231.08:04:12.50#ibcon#about to read 5, iclass 27, count 0 2006.231.08:04:12.50#ibcon#read 5, iclass 27, count 0 2006.231.08:04:12.50#ibcon#about to read 6, iclass 27, count 0 2006.231.08:04:12.50#ibcon#read 6, iclass 27, count 0 2006.231.08:04:12.50#ibcon#end of sib2, iclass 27, count 0 2006.231.08:04:12.50#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:04:12.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:04:12.50#ibcon#[27=USB\r\n] 2006.231.08:04:12.50#ibcon#*before write, iclass 27, count 0 2006.231.08:04:12.50#ibcon#enter sib2, iclass 27, count 0 2006.231.08:04:12.50#ibcon#flushed, iclass 27, count 0 2006.231.08:04:12.50#ibcon#about to write, iclass 27, count 0 2006.231.08:04:12.50#ibcon#wrote, iclass 27, count 0 2006.231.08:04:12.50#ibcon#about to read 3, iclass 27, count 0 2006.231.08:04:12.53#ibcon#read 3, iclass 27, count 0 2006.231.08:04:12.53#ibcon#about to read 4, iclass 27, count 0 2006.231.08:04:12.53#ibcon#read 4, iclass 27, count 0 2006.231.08:04:12.53#ibcon#about to read 5, iclass 27, count 0 2006.231.08:04:12.53#ibcon#read 5, iclass 27, count 0 2006.231.08:04:12.53#ibcon#about to read 6, iclass 27, count 0 2006.231.08:04:12.53#ibcon#read 6, iclass 27, count 0 2006.231.08:04:12.53#ibcon#end of sib2, iclass 27, count 0 2006.231.08:04:12.53#ibcon#*after write, iclass 27, count 0 2006.231.08:04:12.53#ibcon#*before return 0, iclass 27, count 0 2006.231.08:04:12.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:04:12.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:04:12.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:04:12.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:04:12.53$vc4f8/vabw=wide 2006.231.08:04:12.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.231.08:04:12.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.231.08:04:12.54#ibcon#ireg 8 cls_cnt 0 2006.231.08:04:12.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:04:12.54#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:04:12.54#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:04:12.54#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:04:12.54#ibcon#first serial, iclass 29, count 0 2006.231.08:04:12.54#ibcon#enter sib2, iclass 29, count 0 2006.231.08:04:12.54#ibcon#flushed, iclass 29, count 0 2006.231.08:04:12.54#ibcon#about to write, iclass 29, count 0 2006.231.08:04:12.54#ibcon#wrote, iclass 29, count 0 2006.231.08:04:12.54#ibcon#about to read 3, iclass 29, count 0 2006.231.08:04:12.55#ibcon#read 3, iclass 29, count 0 2006.231.08:04:12.55#ibcon#about to read 4, iclass 29, count 0 2006.231.08:04:12.55#ibcon#read 4, iclass 29, count 0 2006.231.08:04:12.55#ibcon#about to read 5, iclass 29, count 0 2006.231.08:04:12.55#ibcon#read 5, iclass 29, count 0 2006.231.08:04:12.55#ibcon#about to read 6, iclass 29, count 0 2006.231.08:04:12.55#ibcon#read 6, iclass 29, count 0 2006.231.08:04:12.55#ibcon#end of sib2, iclass 29, count 0 2006.231.08:04:12.55#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:04:12.55#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:04:12.55#ibcon#[25=BW32\r\n] 2006.231.08:04:12.55#ibcon#*before write, iclass 29, count 0 2006.231.08:04:12.55#ibcon#enter sib2, iclass 29, count 0 2006.231.08:04:12.55#ibcon#flushed, iclass 29, count 0 2006.231.08:04:12.55#ibcon#about to write, iclass 29, count 0 2006.231.08:04:12.55#ibcon#wrote, iclass 29, count 0 2006.231.08:04:12.55#ibcon#about to read 3, iclass 29, count 0 2006.231.08:04:12.58#ibcon#read 3, iclass 29, count 0 2006.231.08:04:12.58#ibcon#about to read 4, iclass 29, count 0 2006.231.08:04:12.58#ibcon#read 4, iclass 29, count 0 2006.231.08:04:12.58#ibcon#about to read 5, iclass 29, count 0 2006.231.08:04:12.58#ibcon#read 5, iclass 29, count 0 2006.231.08:04:12.58#ibcon#about to read 6, iclass 29, count 0 2006.231.08:04:12.58#ibcon#read 6, iclass 29, count 0 2006.231.08:04:12.58#ibcon#end of sib2, iclass 29, count 0 2006.231.08:04:12.58#ibcon#*after write, iclass 29, count 0 2006.231.08:04:12.58#ibcon#*before return 0, iclass 29, count 0 2006.231.08:04:12.58#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:04:12.58#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:04:12.58#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:04:12.58#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:04:12.58$vc4f8/vbbw=wide 2006.231.08:04:12.58#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.231.08:04:12.58#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.231.08:04:12.58#ibcon#ireg 8 cls_cnt 0 2006.231.08:04:12.58#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:04:12.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:04:12.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:04:12.65#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:04:12.65#ibcon#first serial, iclass 31, count 0 2006.231.08:04:12.65#ibcon#enter sib2, iclass 31, count 0 2006.231.08:04:12.65#ibcon#flushed, iclass 31, count 0 2006.231.08:04:12.65#ibcon#about to write, iclass 31, count 0 2006.231.08:04:12.65#ibcon#wrote, iclass 31, count 0 2006.231.08:04:12.65#ibcon#about to read 3, iclass 31, count 0 2006.231.08:04:12.67#ibcon#read 3, iclass 31, count 0 2006.231.08:04:12.67#ibcon#about to read 4, iclass 31, count 0 2006.231.08:04:12.67#ibcon#read 4, iclass 31, count 0 2006.231.08:04:12.67#ibcon#about to read 5, iclass 31, count 0 2006.231.08:04:12.67#ibcon#read 5, iclass 31, count 0 2006.231.08:04:12.67#ibcon#about to read 6, iclass 31, count 0 2006.231.08:04:12.67#ibcon#read 6, iclass 31, count 0 2006.231.08:04:12.67#ibcon#end of sib2, iclass 31, count 0 2006.231.08:04:12.67#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:04:12.67#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:04:12.67#ibcon#[27=BW32\r\n] 2006.231.08:04:12.67#ibcon#*before write, iclass 31, count 0 2006.231.08:04:12.67#ibcon#enter sib2, iclass 31, count 0 2006.231.08:04:12.67#ibcon#flushed, iclass 31, count 0 2006.231.08:04:12.67#ibcon#about to write, iclass 31, count 0 2006.231.08:04:12.67#ibcon#wrote, iclass 31, count 0 2006.231.08:04:12.67#ibcon#about to read 3, iclass 31, count 0 2006.231.08:04:12.70#ibcon#read 3, iclass 31, count 0 2006.231.08:04:12.70#ibcon#about to read 4, iclass 31, count 0 2006.231.08:04:12.70#ibcon#read 4, iclass 31, count 0 2006.231.08:04:12.70#ibcon#about to read 5, iclass 31, count 0 2006.231.08:04:12.70#ibcon#read 5, iclass 31, count 0 2006.231.08:04:12.70#ibcon#about to read 6, iclass 31, count 0 2006.231.08:04:12.70#ibcon#read 6, iclass 31, count 0 2006.231.08:04:12.70#ibcon#end of sib2, iclass 31, count 0 2006.231.08:04:12.70#ibcon#*after write, iclass 31, count 0 2006.231.08:04:12.70#ibcon#*before return 0, iclass 31, count 0 2006.231.08:04:12.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:04:12.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:04:12.70#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:04:12.70#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:04:12.70$4f8m12a/ifd4f 2006.231.08:04:12.71$ifd4f/lo= 2006.231.08:04:12.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:04:12.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:04:12.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:04:12.71$ifd4f/patch= 2006.231.08:04:12.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:04:12.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:04:12.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:04:12.71$4f8m12a/"form=m,16.000,1:2 2006.231.08:04:12.71$4f8m12a/"tpicd 2006.231.08:04:12.71$4f8m12a/echo=off 2006.231.08:04:12.71$4f8m12a/xlog=off 2006.231.08:04:12.71:!2006.231.08:04:40 2006.231.08:04:23.14#trakl#Source acquired 2006.231.08:04:25.14#flagr#flagr/antenna,acquired 2006.231.08:04:40.01:preob 2006.231.08:04:41.14/onsource/TRACKING 2006.231.08:04:41.15:!2006.231.08:04:50 2006.231.08:04:50.01:data_valid=on 2006.231.08:04:50.02:midob 2006.231.08:04:51.14/onsource/TRACKING 2006.231.08:04:51.15/wx/30.52,1004.5,85 2006.231.08:04:51.30/cable/+6.3717E-03 2006.231.08:04:52.39/va/01,08,usb,yes,32,33 2006.231.08:04:52.39/va/02,07,usb,yes,32,33 2006.231.08:04:52.39/va/03,08,usb,yes,24,24 2006.231.08:04:52.39/va/04,07,usb,yes,33,36 2006.231.08:04:52.39/va/05,07,usb,yes,36,38 2006.231.08:04:52.39/va/06,06,usb,yes,36,35 2006.231.08:04:52.39/va/07,06,usb,yes,36,36 2006.231.08:04:52.39/va/08,06,usb,yes,39,38 2006.231.08:04:52.62/valo/01,532.99,yes,locked 2006.231.08:04:52.62/valo/02,572.99,yes,locked 2006.231.08:04:52.62/valo/03,672.99,yes,locked 2006.231.08:04:52.62/valo/04,832.99,yes,locked 2006.231.08:04:52.62/valo/05,652.99,yes,locked 2006.231.08:04:52.62/valo/06,772.99,yes,locked 2006.231.08:04:52.62/valo/07,832.99,yes,locked 2006.231.08:04:52.62/valo/08,852.99,yes,locked 2006.231.08:04:53.71/vb/01,04,usb,yes,32,32 2006.231.08:04:53.71/vb/02,04,usb,yes,34,37 2006.231.08:04:53.71/vb/03,04,usb,yes,30,34 2006.231.08:04:53.71/vb/04,04,usb,yes,31,31 2006.231.08:04:53.71/vb/05,03,usb,yes,36,41 2006.231.08:04:53.71/vb/06,04,usb,yes,30,33 2006.231.08:04:53.71/vb/07,04,usb,yes,32,32 2006.231.08:04:53.71/vb/08,04,usb,yes,30,33 2006.231.08:04:53.95/vblo/01,632.99,yes,locked 2006.231.08:04:53.95/vblo/02,640.99,yes,locked 2006.231.08:04:53.95/vblo/03,656.99,yes,locked 2006.231.08:04:53.95/vblo/04,712.99,yes,locked 2006.231.08:04:53.95/vblo/05,744.99,yes,locked 2006.231.08:04:53.95/vblo/06,752.99,yes,locked 2006.231.08:04:53.95/vblo/07,734.99,yes,locked 2006.231.08:04:53.95/vblo/08,744.99,yes,locked 2006.231.08:04:54.10/vabw/8 2006.231.08:04:54.25/vbbw/8 2006.231.08:04:54.34/xfe/off,on,12.2 2006.231.08:04:54.71/ifatt/23,28,28,28 2006.231.08:04:55.07/fmout-gps/S +4.45E-07 2006.231.08:04:55.12:!2006.231.08:05:50 2006.231.08:05:50.00:data_valid=off 2006.231.08:05:50.01:postob 2006.231.08:05:50.17/cable/+6.3736E-03 2006.231.08:05:50.18/wx/30.51,1004.4,85 2006.231.08:05:51.07/fmout-gps/S +4.45E-07 2006.231.08:05:51.08:scan_name=231-0806,k06231,70 2006.231.08:05:51.08:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.231.08:05:52.13#flagr#flagr/antenna,new-source 2006.231.08:05:52.14:checkk5 2006.231.08:05:52.52/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:05:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:05:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:05:53.67/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:05:54.03/chk_obsdata//k5ts1/T2310804??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:05:54.40/chk_obsdata//k5ts2/T2310804??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:05:54.77/chk_obsdata//k5ts3/T2310804??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:05:55.13/chk_obsdata//k5ts4/T2310804??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:05:55.82/k5log//k5ts1_log_newline 2006.231.08:05:56.50/k5log//k5ts2_log_newline 2006.231.08:05:57.19/k5log//k5ts3_log_newline 2006.231.08:05:57.88/k5log//k5ts4_log_newline 2006.231.08:05:57.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:05:57.90:4f8m12a=2 2006.231.08:05:57.90$4f8m12a/echo=on 2006.231.08:05:57.90$4f8m12a/pcalon 2006.231.08:05:57.90$pcalon/"no phase cal control is implemented here 2006.231.08:05:57.90$4f8m12a/"tpicd=stop 2006.231.08:05:57.90$4f8m12a/vc4f8 2006.231.08:05:57.90$vc4f8/valo=1,532.99 2006.231.08:05:57.91#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.08:05:57.91#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.08:05:57.91#ibcon#ireg 17 cls_cnt 0 2006.231.08:05:57.91#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:05:57.91#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:05:57.91#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:05:57.91#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:05:57.91#ibcon#first serial, iclass 33, count 0 2006.231.08:05:57.91#ibcon#enter sib2, iclass 33, count 0 2006.231.08:05:57.91#ibcon#flushed, iclass 33, count 0 2006.231.08:05:57.91#ibcon#about to write, iclass 33, count 0 2006.231.08:05:57.91#ibcon#wrote, iclass 33, count 0 2006.231.08:05:57.91#ibcon#about to read 3, iclass 33, count 0 2006.231.08:05:57.95#ibcon#read 3, iclass 33, count 0 2006.231.08:05:57.95#ibcon#about to read 4, iclass 33, count 0 2006.231.08:05:57.95#ibcon#read 4, iclass 33, count 0 2006.231.08:05:57.95#ibcon#about to read 5, iclass 33, count 0 2006.231.08:05:57.95#ibcon#read 5, iclass 33, count 0 2006.231.08:05:57.95#ibcon#about to read 6, iclass 33, count 0 2006.231.08:05:57.95#ibcon#read 6, iclass 33, count 0 2006.231.08:05:57.95#ibcon#end of sib2, iclass 33, count 0 2006.231.08:05:57.95#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:05:57.95#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:05:57.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:05:57.95#ibcon#*before write, iclass 33, count 0 2006.231.08:05:57.95#ibcon#enter sib2, iclass 33, count 0 2006.231.08:05:57.95#ibcon#flushed, iclass 33, count 0 2006.231.08:05:57.95#ibcon#about to write, iclass 33, count 0 2006.231.08:05:57.95#ibcon#wrote, iclass 33, count 0 2006.231.08:05:57.95#ibcon#about to read 3, iclass 33, count 0 2006.231.08:05:57.99#abcon#<5=/07 3.1 6.8 30.51 851004.4\r\n> 2006.231.08:05:57.99#ibcon#read 3, iclass 33, count 0 2006.231.08:05:57.99#ibcon#about to read 4, iclass 33, count 0 2006.231.08:05:57.99#ibcon#read 4, iclass 33, count 0 2006.231.08:05:57.99#ibcon#about to read 5, iclass 33, count 0 2006.231.08:05:57.99#ibcon#read 5, iclass 33, count 0 2006.231.08:05:57.99#ibcon#about to read 6, iclass 33, count 0 2006.231.08:05:57.99#ibcon#read 6, iclass 33, count 0 2006.231.08:05:57.99#ibcon#end of sib2, iclass 33, count 0 2006.231.08:05:57.99#ibcon#*after write, iclass 33, count 0 2006.231.08:05:57.99#ibcon#*before return 0, iclass 33, count 0 2006.231.08:05:57.99#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:05:57.99#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:05:57.99#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:05:57.99#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:05:57.99$vc4f8/va=1,8 2006.231.08:05:58.00#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.08:05:58.00#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.08:05:58.00#ibcon#ireg 11 cls_cnt 2 2006.231.08:05:58.00#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:05:58.00#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:05:58.00#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:05:58.00#ibcon#enter wrdev, iclass 38, count 2 2006.231.08:05:58.00#ibcon#first serial, iclass 38, count 2 2006.231.08:05:58.00#ibcon#enter sib2, iclass 38, count 2 2006.231.08:05:58.00#ibcon#flushed, iclass 38, count 2 2006.231.08:05:58.00#ibcon#about to write, iclass 38, count 2 2006.231.08:05:58.00#ibcon#wrote, iclass 38, count 2 2006.231.08:05:58.00#ibcon#about to read 3, iclass 38, count 2 2006.231.08:05:58.01#abcon#{5=INTERFACE CLEAR} 2006.231.08:05:58.01#ibcon#read 3, iclass 38, count 2 2006.231.08:05:58.01#ibcon#about to read 4, iclass 38, count 2 2006.231.08:05:58.01#ibcon#read 4, iclass 38, count 2 2006.231.08:05:58.01#ibcon#about to read 5, iclass 38, count 2 2006.231.08:05:58.01#ibcon#read 5, iclass 38, count 2 2006.231.08:05:58.01#ibcon#about to read 6, iclass 38, count 2 2006.231.08:05:58.01#ibcon#read 6, iclass 38, count 2 2006.231.08:05:58.01#ibcon#end of sib2, iclass 38, count 2 2006.231.08:05:58.01#ibcon#*mode == 0, iclass 38, count 2 2006.231.08:05:58.01#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.08:05:58.01#ibcon#[25=AT01-08\r\n] 2006.231.08:05:58.01#ibcon#*before write, iclass 38, count 2 2006.231.08:05:58.01#ibcon#enter sib2, iclass 38, count 2 2006.231.08:05:58.01#ibcon#flushed, iclass 38, count 2 2006.231.08:05:58.01#ibcon#about to write, iclass 38, count 2 2006.231.08:05:58.01#ibcon#wrote, iclass 38, count 2 2006.231.08:05:58.01#ibcon#about to read 3, iclass 38, count 2 2006.231.08:05:58.04#ibcon#read 3, iclass 38, count 2 2006.231.08:05:58.04#ibcon#about to read 4, iclass 38, count 2 2006.231.08:05:58.04#ibcon#read 4, iclass 38, count 2 2006.231.08:05:58.04#ibcon#about to read 5, iclass 38, count 2 2006.231.08:05:58.04#ibcon#read 5, iclass 38, count 2 2006.231.08:05:58.04#ibcon#about to read 6, iclass 38, count 2 2006.231.08:05:58.04#ibcon#read 6, iclass 38, count 2 2006.231.08:05:58.04#ibcon#end of sib2, iclass 38, count 2 2006.231.08:05:58.04#ibcon#*after write, iclass 38, count 2 2006.231.08:05:58.04#ibcon#*before return 0, iclass 38, count 2 2006.231.08:05:58.04#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:05:58.04#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:05:58.04#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.08:05:58.04#ibcon#ireg 7 cls_cnt 0 2006.231.08:05:58.04#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:05:58.07#abcon#[5=S1D000X0/0*\r\n] 2006.231.08:05:58.16#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:05:58.16#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:05:58.16#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:05:58.16#ibcon#first serial, iclass 38, count 0 2006.231.08:05:58.16#ibcon#enter sib2, iclass 38, count 0 2006.231.08:05:58.16#ibcon#flushed, iclass 38, count 0 2006.231.08:05:58.16#ibcon#about to write, iclass 38, count 0 2006.231.08:05:58.16#ibcon#wrote, iclass 38, count 0 2006.231.08:05:58.16#ibcon#about to read 3, iclass 38, count 0 2006.231.08:05:58.18#ibcon#read 3, iclass 38, count 0 2006.231.08:05:58.18#ibcon#about to read 4, iclass 38, count 0 2006.231.08:05:58.18#ibcon#read 4, iclass 38, count 0 2006.231.08:05:58.18#ibcon#about to read 5, iclass 38, count 0 2006.231.08:05:58.18#ibcon#read 5, iclass 38, count 0 2006.231.08:05:58.18#ibcon#about to read 6, iclass 38, count 0 2006.231.08:05:58.18#ibcon#read 6, iclass 38, count 0 2006.231.08:05:58.18#ibcon#end of sib2, iclass 38, count 0 2006.231.08:05:58.18#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:05:58.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:05:58.18#ibcon#[25=USB\r\n] 2006.231.08:05:58.18#ibcon#*before write, iclass 38, count 0 2006.231.08:05:58.18#ibcon#enter sib2, iclass 38, count 0 2006.231.08:05:58.18#ibcon#flushed, iclass 38, count 0 2006.231.08:05:58.18#ibcon#about to write, iclass 38, count 0 2006.231.08:05:58.18#ibcon#wrote, iclass 38, count 0 2006.231.08:05:58.18#ibcon#about to read 3, iclass 38, count 0 2006.231.08:05:58.21#ibcon#read 3, iclass 38, count 0 2006.231.08:05:58.21#ibcon#about to read 4, iclass 38, count 0 2006.231.08:05:58.21#ibcon#read 4, iclass 38, count 0 2006.231.08:05:58.21#ibcon#about to read 5, iclass 38, count 0 2006.231.08:05:58.21#ibcon#read 5, iclass 38, count 0 2006.231.08:05:58.21#ibcon#about to read 6, iclass 38, count 0 2006.231.08:05:58.21#ibcon#read 6, iclass 38, count 0 2006.231.08:05:58.21#ibcon#end of sib2, iclass 38, count 0 2006.231.08:05:58.21#ibcon#*after write, iclass 38, count 0 2006.231.08:05:58.21#ibcon#*before return 0, iclass 38, count 0 2006.231.08:05:58.21#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:05:58.21#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:05:58.21#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:05:58.21#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:05:58.21$vc4f8/valo=2,572.99 2006.231.08:05:58.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.08:05:58.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.08:05:58.21#ibcon#ireg 17 cls_cnt 0 2006.231.08:05:58.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:05:58.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:05:58.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:05:58.21#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:05:58.21#ibcon#first serial, iclass 3, count 0 2006.231.08:05:58.21#ibcon#enter sib2, iclass 3, count 0 2006.231.08:05:58.21#ibcon#flushed, iclass 3, count 0 2006.231.08:05:58.21#ibcon#about to write, iclass 3, count 0 2006.231.08:05:58.21#ibcon#wrote, iclass 3, count 0 2006.231.08:05:58.21#ibcon#about to read 3, iclass 3, count 0 2006.231.08:05:58.23#ibcon#read 3, iclass 3, count 0 2006.231.08:05:58.23#ibcon#about to read 4, iclass 3, count 0 2006.231.08:05:58.23#ibcon#read 4, iclass 3, count 0 2006.231.08:05:58.23#ibcon#about to read 5, iclass 3, count 0 2006.231.08:05:58.23#ibcon#read 5, iclass 3, count 0 2006.231.08:05:58.23#ibcon#about to read 6, iclass 3, count 0 2006.231.08:05:58.23#ibcon#read 6, iclass 3, count 0 2006.231.08:05:58.23#ibcon#end of sib2, iclass 3, count 0 2006.231.08:05:58.23#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:05:58.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:05:58.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:05:58.23#ibcon#*before write, iclass 3, count 0 2006.231.08:05:58.23#ibcon#enter sib2, iclass 3, count 0 2006.231.08:05:58.23#ibcon#flushed, iclass 3, count 0 2006.231.08:05:58.23#ibcon#about to write, iclass 3, count 0 2006.231.08:05:58.23#ibcon#wrote, iclass 3, count 0 2006.231.08:05:58.23#ibcon#about to read 3, iclass 3, count 0 2006.231.08:05:58.27#ibcon#read 3, iclass 3, count 0 2006.231.08:05:58.27#ibcon#about to read 4, iclass 3, count 0 2006.231.08:05:58.27#ibcon#read 4, iclass 3, count 0 2006.231.08:05:58.27#ibcon#about to read 5, iclass 3, count 0 2006.231.08:05:58.27#ibcon#read 5, iclass 3, count 0 2006.231.08:05:58.27#ibcon#about to read 6, iclass 3, count 0 2006.231.08:05:58.27#ibcon#read 6, iclass 3, count 0 2006.231.08:05:58.27#ibcon#end of sib2, iclass 3, count 0 2006.231.08:05:58.27#ibcon#*after write, iclass 3, count 0 2006.231.08:05:58.27#ibcon#*before return 0, iclass 3, count 0 2006.231.08:05:58.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:05:58.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:05:58.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:05:58.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:05:58.27$vc4f8/va=2,7 2006.231.08:05:58.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.08:05:58.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.08:05:58.27#ibcon#ireg 11 cls_cnt 2 2006.231.08:05:58.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:05:58.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:05:58.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:05:58.33#ibcon#enter wrdev, iclass 5, count 2 2006.231.08:05:58.33#ibcon#first serial, iclass 5, count 2 2006.231.08:05:58.33#ibcon#enter sib2, iclass 5, count 2 2006.231.08:05:58.33#ibcon#flushed, iclass 5, count 2 2006.231.08:05:58.33#ibcon#about to write, iclass 5, count 2 2006.231.08:05:58.33#ibcon#wrote, iclass 5, count 2 2006.231.08:05:58.33#ibcon#about to read 3, iclass 5, count 2 2006.231.08:05:58.36#ibcon#read 3, iclass 5, count 2 2006.231.08:05:58.36#ibcon#about to read 4, iclass 5, count 2 2006.231.08:05:58.36#ibcon#read 4, iclass 5, count 2 2006.231.08:05:58.36#ibcon#about to read 5, iclass 5, count 2 2006.231.08:05:58.36#ibcon#read 5, iclass 5, count 2 2006.231.08:05:58.36#ibcon#about to read 6, iclass 5, count 2 2006.231.08:05:58.36#ibcon#read 6, iclass 5, count 2 2006.231.08:05:58.36#ibcon#end of sib2, iclass 5, count 2 2006.231.08:05:58.36#ibcon#*mode == 0, iclass 5, count 2 2006.231.08:05:58.36#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.08:05:58.36#ibcon#[25=AT02-07\r\n] 2006.231.08:05:58.36#ibcon#*before write, iclass 5, count 2 2006.231.08:05:58.36#ibcon#enter sib2, iclass 5, count 2 2006.231.08:05:58.36#ibcon#flushed, iclass 5, count 2 2006.231.08:05:58.36#ibcon#about to write, iclass 5, count 2 2006.231.08:05:58.36#ibcon#wrote, iclass 5, count 2 2006.231.08:05:58.36#ibcon#about to read 3, iclass 5, count 2 2006.231.08:05:58.39#ibcon#read 3, iclass 5, count 2 2006.231.08:05:58.39#ibcon#about to read 4, iclass 5, count 2 2006.231.08:05:58.39#ibcon#read 4, iclass 5, count 2 2006.231.08:05:58.39#ibcon#about to read 5, iclass 5, count 2 2006.231.08:05:58.39#ibcon#read 5, iclass 5, count 2 2006.231.08:05:58.39#ibcon#about to read 6, iclass 5, count 2 2006.231.08:05:58.39#ibcon#read 6, iclass 5, count 2 2006.231.08:05:58.39#ibcon#end of sib2, iclass 5, count 2 2006.231.08:05:58.39#ibcon#*after write, iclass 5, count 2 2006.231.08:05:58.39#ibcon#*before return 0, iclass 5, count 2 2006.231.08:05:58.39#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:05:58.39#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:05:58.39#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.08:05:58.39#ibcon#ireg 7 cls_cnt 0 2006.231.08:05:58.39#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:05:58.51#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:05:58.51#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:05:58.51#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:05:58.51#ibcon#first serial, iclass 5, count 0 2006.231.08:05:58.51#ibcon#enter sib2, iclass 5, count 0 2006.231.08:05:58.51#ibcon#flushed, iclass 5, count 0 2006.231.08:05:58.51#ibcon#about to write, iclass 5, count 0 2006.231.08:05:58.51#ibcon#wrote, iclass 5, count 0 2006.231.08:05:58.51#ibcon#about to read 3, iclass 5, count 0 2006.231.08:05:58.53#ibcon#read 3, iclass 5, count 0 2006.231.08:05:58.53#ibcon#about to read 4, iclass 5, count 0 2006.231.08:05:58.53#ibcon#read 4, iclass 5, count 0 2006.231.08:05:58.53#ibcon#about to read 5, iclass 5, count 0 2006.231.08:05:58.53#ibcon#read 5, iclass 5, count 0 2006.231.08:05:58.53#ibcon#about to read 6, iclass 5, count 0 2006.231.08:05:58.53#ibcon#read 6, iclass 5, count 0 2006.231.08:05:58.53#ibcon#end of sib2, iclass 5, count 0 2006.231.08:05:58.53#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:05:58.53#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:05:58.53#ibcon#[25=USB\r\n] 2006.231.08:05:58.53#ibcon#*before write, iclass 5, count 0 2006.231.08:05:58.53#ibcon#enter sib2, iclass 5, count 0 2006.231.08:05:58.53#ibcon#flushed, iclass 5, count 0 2006.231.08:05:58.53#ibcon#about to write, iclass 5, count 0 2006.231.08:05:58.53#ibcon#wrote, iclass 5, count 0 2006.231.08:05:58.53#ibcon#about to read 3, iclass 5, count 0 2006.231.08:05:58.56#ibcon#read 3, iclass 5, count 0 2006.231.08:05:58.56#ibcon#about to read 4, iclass 5, count 0 2006.231.08:05:58.56#ibcon#read 4, iclass 5, count 0 2006.231.08:05:58.56#ibcon#about to read 5, iclass 5, count 0 2006.231.08:05:58.56#ibcon#read 5, iclass 5, count 0 2006.231.08:05:58.56#ibcon#about to read 6, iclass 5, count 0 2006.231.08:05:58.56#ibcon#read 6, iclass 5, count 0 2006.231.08:05:58.56#ibcon#end of sib2, iclass 5, count 0 2006.231.08:05:58.56#ibcon#*after write, iclass 5, count 0 2006.231.08:05:58.56#ibcon#*before return 0, iclass 5, count 0 2006.231.08:05:58.56#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:05:58.56#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:05:58.56#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:05:58.56#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:05:58.56$vc4f8/valo=3,672.99 2006.231.08:05:58.56#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.08:05:58.56#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.08:05:58.56#ibcon#ireg 17 cls_cnt 0 2006.231.08:05:58.56#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:05:58.56#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:05:58.56#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:05:58.56#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:05:58.56#ibcon#first serial, iclass 7, count 0 2006.231.08:05:58.56#ibcon#enter sib2, iclass 7, count 0 2006.231.08:05:58.56#ibcon#flushed, iclass 7, count 0 2006.231.08:05:58.56#ibcon#about to write, iclass 7, count 0 2006.231.08:05:58.56#ibcon#wrote, iclass 7, count 0 2006.231.08:05:58.56#ibcon#about to read 3, iclass 7, count 0 2006.231.08:05:58.59#ibcon#read 3, iclass 7, count 0 2006.231.08:05:58.59#ibcon#about to read 4, iclass 7, count 0 2006.231.08:05:58.59#ibcon#read 4, iclass 7, count 0 2006.231.08:05:58.59#ibcon#about to read 5, iclass 7, count 0 2006.231.08:05:58.59#ibcon#read 5, iclass 7, count 0 2006.231.08:05:58.59#ibcon#about to read 6, iclass 7, count 0 2006.231.08:05:58.59#ibcon#read 6, iclass 7, count 0 2006.231.08:05:58.59#ibcon#end of sib2, iclass 7, count 0 2006.231.08:05:58.59#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:05:58.59#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:05:58.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:05:58.59#ibcon#*before write, iclass 7, count 0 2006.231.08:05:58.59#ibcon#enter sib2, iclass 7, count 0 2006.231.08:05:58.59#ibcon#flushed, iclass 7, count 0 2006.231.08:05:58.59#ibcon#about to write, iclass 7, count 0 2006.231.08:05:58.59#ibcon#wrote, iclass 7, count 0 2006.231.08:05:58.59#ibcon#about to read 3, iclass 7, count 0 2006.231.08:05:58.63#ibcon#read 3, iclass 7, count 0 2006.231.08:05:58.63#ibcon#about to read 4, iclass 7, count 0 2006.231.08:05:58.63#ibcon#read 4, iclass 7, count 0 2006.231.08:05:58.63#ibcon#about to read 5, iclass 7, count 0 2006.231.08:05:58.63#ibcon#read 5, iclass 7, count 0 2006.231.08:05:58.63#ibcon#about to read 6, iclass 7, count 0 2006.231.08:05:58.63#ibcon#read 6, iclass 7, count 0 2006.231.08:05:58.63#ibcon#end of sib2, iclass 7, count 0 2006.231.08:05:58.63#ibcon#*after write, iclass 7, count 0 2006.231.08:05:58.63#ibcon#*before return 0, iclass 7, count 0 2006.231.08:05:58.63#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:05:58.63#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:05:58.63#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:05:58.63#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:05:58.63$vc4f8/va=3,8 2006.231.08:05:58.63#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.08:05:58.63#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.08:05:58.63#ibcon#ireg 11 cls_cnt 2 2006.231.08:05:58.63#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:05:58.69#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:05:58.69#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:05:58.69#ibcon#enter wrdev, iclass 11, count 2 2006.231.08:05:58.69#ibcon#first serial, iclass 11, count 2 2006.231.08:05:58.69#ibcon#enter sib2, iclass 11, count 2 2006.231.08:05:58.69#ibcon#flushed, iclass 11, count 2 2006.231.08:05:58.69#ibcon#about to write, iclass 11, count 2 2006.231.08:05:58.69#ibcon#wrote, iclass 11, count 2 2006.231.08:05:58.69#ibcon#about to read 3, iclass 11, count 2 2006.231.08:05:58.70#ibcon#read 3, iclass 11, count 2 2006.231.08:05:58.70#ibcon#about to read 4, iclass 11, count 2 2006.231.08:05:58.70#ibcon#read 4, iclass 11, count 2 2006.231.08:05:58.70#ibcon#about to read 5, iclass 11, count 2 2006.231.08:05:58.70#ibcon#read 5, iclass 11, count 2 2006.231.08:05:58.70#ibcon#about to read 6, iclass 11, count 2 2006.231.08:05:58.70#ibcon#read 6, iclass 11, count 2 2006.231.08:05:58.70#ibcon#end of sib2, iclass 11, count 2 2006.231.08:05:58.70#ibcon#*mode == 0, iclass 11, count 2 2006.231.08:05:58.70#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.08:05:58.70#ibcon#[25=AT03-08\r\n] 2006.231.08:05:58.70#ibcon#*before write, iclass 11, count 2 2006.231.08:05:58.70#ibcon#enter sib2, iclass 11, count 2 2006.231.08:05:58.70#ibcon#flushed, iclass 11, count 2 2006.231.08:05:58.70#ibcon#about to write, iclass 11, count 2 2006.231.08:05:58.70#ibcon#wrote, iclass 11, count 2 2006.231.08:05:58.70#ibcon#about to read 3, iclass 11, count 2 2006.231.08:05:58.73#ibcon#read 3, iclass 11, count 2 2006.231.08:05:58.73#ibcon#about to read 4, iclass 11, count 2 2006.231.08:05:58.73#ibcon#read 4, iclass 11, count 2 2006.231.08:05:58.73#ibcon#about to read 5, iclass 11, count 2 2006.231.08:05:58.73#ibcon#read 5, iclass 11, count 2 2006.231.08:05:58.73#ibcon#about to read 6, iclass 11, count 2 2006.231.08:05:58.73#ibcon#read 6, iclass 11, count 2 2006.231.08:05:58.73#ibcon#end of sib2, iclass 11, count 2 2006.231.08:05:58.73#ibcon#*after write, iclass 11, count 2 2006.231.08:05:58.73#ibcon#*before return 0, iclass 11, count 2 2006.231.08:05:58.73#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:05:58.73#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:05:58.73#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.08:05:58.73#ibcon#ireg 7 cls_cnt 0 2006.231.08:05:58.73#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:05:58.85#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:05:58.85#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:05:58.85#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:05:58.85#ibcon#first serial, iclass 11, count 0 2006.231.08:05:58.85#ibcon#enter sib2, iclass 11, count 0 2006.231.08:05:58.85#ibcon#flushed, iclass 11, count 0 2006.231.08:05:58.85#ibcon#about to write, iclass 11, count 0 2006.231.08:05:58.85#ibcon#wrote, iclass 11, count 0 2006.231.08:05:58.85#ibcon#about to read 3, iclass 11, count 0 2006.231.08:05:58.87#ibcon#read 3, iclass 11, count 0 2006.231.08:05:58.87#ibcon#about to read 4, iclass 11, count 0 2006.231.08:05:58.87#ibcon#read 4, iclass 11, count 0 2006.231.08:05:58.87#ibcon#about to read 5, iclass 11, count 0 2006.231.08:05:58.87#ibcon#read 5, iclass 11, count 0 2006.231.08:05:58.87#ibcon#about to read 6, iclass 11, count 0 2006.231.08:05:58.87#ibcon#read 6, iclass 11, count 0 2006.231.08:05:58.87#ibcon#end of sib2, iclass 11, count 0 2006.231.08:05:58.87#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:05:58.87#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:05:58.87#ibcon#[25=USB\r\n] 2006.231.08:05:58.87#ibcon#*before write, iclass 11, count 0 2006.231.08:05:58.87#ibcon#enter sib2, iclass 11, count 0 2006.231.08:05:58.87#ibcon#flushed, iclass 11, count 0 2006.231.08:05:58.87#ibcon#about to write, iclass 11, count 0 2006.231.08:05:58.87#ibcon#wrote, iclass 11, count 0 2006.231.08:05:58.87#ibcon#about to read 3, iclass 11, count 0 2006.231.08:05:58.91#ibcon#read 3, iclass 11, count 0 2006.231.08:05:58.91#ibcon#about to read 4, iclass 11, count 0 2006.231.08:05:58.91#ibcon#read 4, iclass 11, count 0 2006.231.08:05:58.91#ibcon#about to read 5, iclass 11, count 0 2006.231.08:05:58.91#ibcon#read 5, iclass 11, count 0 2006.231.08:05:58.91#ibcon#about to read 6, iclass 11, count 0 2006.231.08:05:58.91#ibcon#read 6, iclass 11, count 0 2006.231.08:05:58.91#ibcon#end of sib2, iclass 11, count 0 2006.231.08:05:58.91#ibcon#*after write, iclass 11, count 0 2006.231.08:05:58.91#ibcon#*before return 0, iclass 11, count 0 2006.231.08:05:58.91#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:05:58.91#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:05:58.91#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:05:58.91#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:05:58.91$vc4f8/valo=4,832.99 2006.231.08:05:58.91#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.08:05:58.91#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.08:05:58.91#ibcon#ireg 17 cls_cnt 0 2006.231.08:05:58.91#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:05:58.91#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:05:58.91#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:05:58.91#ibcon#enter wrdev, iclass 13, count 0 2006.231.08:05:58.91#ibcon#first serial, iclass 13, count 0 2006.231.08:05:58.91#ibcon#enter sib2, iclass 13, count 0 2006.231.08:05:58.91#ibcon#flushed, iclass 13, count 0 2006.231.08:05:58.91#ibcon#about to write, iclass 13, count 0 2006.231.08:05:58.91#ibcon#wrote, iclass 13, count 0 2006.231.08:05:58.91#ibcon#about to read 3, iclass 13, count 0 2006.231.08:05:58.93#ibcon#read 3, iclass 13, count 0 2006.231.08:05:58.93#ibcon#about to read 4, iclass 13, count 0 2006.231.08:05:58.93#ibcon#read 4, iclass 13, count 0 2006.231.08:05:58.93#ibcon#about to read 5, iclass 13, count 0 2006.231.08:05:58.93#ibcon#read 5, iclass 13, count 0 2006.231.08:05:58.93#ibcon#about to read 6, iclass 13, count 0 2006.231.08:05:58.93#ibcon#read 6, iclass 13, count 0 2006.231.08:05:58.93#ibcon#end of sib2, iclass 13, count 0 2006.231.08:05:58.93#ibcon#*mode == 0, iclass 13, count 0 2006.231.08:05:58.93#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.08:05:58.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:05:58.93#ibcon#*before write, iclass 13, count 0 2006.231.08:05:58.93#ibcon#enter sib2, iclass 13, count 0 2006.231.08:05:58.93#ibcon#flushed, iclass 13, count 0 2006.231.08:05:58.93#ibcon#about to write, iclass 13, count 0 2006.231.08:05:58.93#ibcon#wrote, iclass 13, count 0 2006.231.08:05:58.93#ibcon#about to read 3, iclass 13, count 0 2006.231.08:05:58.96#ibcon#read 3, iclass 13, count 0 2006.231.08:05:58.96#ibcon#about to read 4, iclass 13, count 0 2006.231.08:05:58.96#ibcon#read 4, iclass 13, count 0 2006.231.08:05:58.96#ibcon#about to read 5, iclass 13, count 0 2006.231.08:05:58.96#ibcon#read 5, iclass 13, count 0 2006.231.08:05:58.96#ibcon#about to read 6, iclass 13, count 0 2006.231.08:05:58.96#ibcon#read 6, iclass 13, count 0 2006.231.08:05:58.96#ibcon#end of sib2, iclass 13, count 0 2006.231.08:05:58.96#ibcon#*after write, iclass 13, count 0 2006.231.08:05:58.96#ibcon#*before return 0, iclass 13, count 0 2006.231.08:05:58.96#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:05:58.96#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:05:58.96#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.08:05:58.96#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.08:05:58.96$vc4f8/va=4,7 2006.231.08:05:58.96#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.08:05:58.96#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.08:05:58.96#ibcon#ireg 11 cls_cnt 2 2006.231.08:05:58.96#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:05:59.03#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:05:59.03#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:05:59.03#ibcon#enter wrdev, iclass 15, count 2 2006.231.08:05:59.03#ibcon#first serial, iclass 15, count 2 2006.231.08:05:59.03#ibcon#enter sib2, iclass 15, count 2 2006.231.08:05:59.03#ibcon#flushed, iclass 15, count 2 2006.231.08:05:59.03#ibcon#about to write, iclass 15, count 2 2006.231.08:05:59.03#ibcon#wrote, iclass 15, count 2 2006.231.08:05:59.03#ibcon#about to read 3, iclass 15, count 2 2006.231.08:05:59.05#ibcon#read 3, iclass 15, count 2 2006.231.08:05:59.05#ibcon#about to read 4, iclass 15, count 2 2006.231.08:05:59.05#ibcon#read 4, iclass 15, count 2 2006.231.08:05:59.05#ibcon#about to read 5, iclass 15, count 2 2006.231.08:05:59.05#ibcon#read 5, iclass 15, count 2 2006.231.08:05:59.05#ibcon#about to read 6, iclass 15, count 2 2006.231.08:05:59.05#ibcon#read 6, iclass 15, count 2 2006.231.08:05:59.05#ibcon#end of sib2, iclass 15, count 2 2006.231.08:05:59.05#ibcon#*mode == 0, iclass 15, count 2 2006.231.08:05:59.05#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.08:05:59.05#ibcon#[25=AT04-07\r\n] 2006.231.08:05:59.05#ibcon#*before write, iclass 15, count 2 2006.231.08:05:59.05#ibcon#enter sib2, iclass 15, count 2 2006.231.08:05:59.05#ibcon#flushed, iclass 15, count 2 2006.231.08:05:59.05#ibcon#about to write, iclass 15, count 2 2006.231.08:05:59.05#ibcon#wrote, iclass 15, count 2 2006.231.08:05:59.05#ibcon#about to read 3, iclass 15, count 2 2006.231.08:05:59.08#ibcon#read 3, iclass 15, count 2 2006.231.08:05:59.08#ibcon#about to read 4, iclass 15, count 2 2006.231.08:05:59.08#ibcon#read 4, iclass 15, count 2 2006.231.08:05:59.08#ibcon#about to read 5, iclass 15, count 2 2006.231.08:05:59.08#ibcon#read 5, iclass 15, count 2 2006.231.08:05:59.08#ibcon#about to read 6, iclass 15, count 2 2006.231.08:05:59.08#ibcon#read 6, iclass 15, count 2 2006.231.08:05:59.08#ibcon#end of sib2, iclass 15, count 2 2006.231.08:05:59.08#ibcon#*after write, iclass 15, count 2 2006.231.08:05:59.08#ibcon#*before return 0, iclass 15, count 2 2006.231.08:05:59.08#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:05:59.08#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:05:59.08#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.08:05:59.08#ibcon#ireg 7 cls_cnt 0 2006.231.08:05:59.08#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:05:59.20#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:05:59.20#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:05:59.20#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:05:59.20#ibcon#first serial, iclass 15, count 0 2006.231.08:05:59.20#ibcon#enter sib2, iclass 15, count 0 2006.231.08:05:59.20#ibcon#flushed, iclass 15, count 0 2006.231.08:05:59.20#ibcon#about to write, iclass 15, count 0 2006.231.08:05:59.20#ibcon#wrote, iclass 15, count 0 2006.231.08:05:59.20#ibcon#about to read 3, iclass 15, count 0 2006.231.08:05:59.22#ibcon#read 3, iclass 15, count 0 2006.231.08:05:59.22#ibcon#about to read 4, iclass 15, count 0 2006.231.08:05:59.22#ibcon#read 4, iclass 15, count 0 2006.231.08:05:59.22#ibcon#about to read 5, iclass 15, count 0 2006.231.08:05:59.22#ibcon#read 5, iclass 15, count 0 2006.231.08:05:59.22#ibcon#about to read 6, iclass 15, count 0 2006.231.08:05:59.22#ibcon#read 6, iclass 15, count 0 2006.231.08:05:59.22#ibcon#end of sib2, iclass 15, count 0 2006.231.08:05:59.22#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:05:59.22#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:05:59.22#ibcon#[25=USB\r\n] 2006.231.08:05:59.22#ibcon#*before write, iclass 15, count 0 2006.231.08:05:59.22#ibcon#enter sib2, iclass 15, count 0 2006.231.08:05:59.22#ibcon#flushed, iclass 15, count 0 2006.231.08:05:59.22#ibcon#about to write, iclass 15, count 0 2006.231.08:05:59.22#ibcon#wrote, iclass 15, count 0 2006.231.08:05:59.22#ibcon#about to read 3, iclass 15, count 0 2006.231.08:05:59.25#ibcon#read 3, iclass 15, count 0 2006.231.08:05:59.25#ibcon#about to read 4, iclass 15, count 0 2006.231.08:05:59.25#ibcon#read 4, iclass 15, count 0 2006.231.08:05:59.25#ibcon#about to read 5, iclass 15, count 0 2006.231.08:05:59.25#ibcon#read 5, iclass 15, count 0 2006.231.08:05:59.25#ibcon#about to read 6, iclass 15, count 0 2006.231.08:05:59.25#ibcon#read 6, iclass 15, count 0 2006.231.08:05:59.25#ibcon#end of sib2, iclass 15, count 0 2006.231.08:05:59.25#ibcon#*after write, iclass 15, count 0 2006.231.08:05:59.25#ibcon#*before return 0, iclass 15, count 0 2006.231.08:05:59.25#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:05:59.25#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:05:59.25#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:05:59.25#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:05:59.25$vc4f8/valo=5,652.99 2006.231.08:05:59.25#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.08:05:59.25#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.08:05:59.25#ibcon#ireg 17 cls_cnt 0 2006.231.08:05:59.25#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:05:59.25#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:05:59.25#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:05:59.25#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:05:59.25#ibcon#first serial, iclass 17, count 0 2006.231.08:05:59.25#ibcon#enter sib2, iclass 17, count 0 2006.231.08:05:59.25#ibcon#flushed, iclass 17, count 0 2006.231.08:05:59.25#ibcon#about to write, iclass 17, count 0 2006.231.08:05:59.25#ibcon#wrote, iclass 17, count 0 2006.231.08:05:59.25#ibcon#about to read 3, iclass 17, count 0 2006.231.08:05:59.27#ibcon#read 3, iclass 17, count 0 2006.231.08:05:59.27#ibcon#about to read 4, iclass 17, count 0 2006.231.08:05:59.27#ibcon#read 4, iclass 17, count 0 2006.231.08:05:59.27#ibcon#about to read 5, iclass 17, count 0 2006.231.08:05:59.27#ibcon#read 5, iclass 17, count 0 2006.231.08:05:59.27#ibcon#about to read 6, iclass 17, count 0 2006.231.08:05:59.27#ibcon#read 6, iclass 17, count 0 2006.231.08:05:59.27#ibcon#end of sib2, iclass 17, count 0 2006.231.08:05:59.27#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:05:59.27#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:05:59.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:05:59.27#ibcon#*before write, iclass 17, count 0 2006.231.08:05:59.27#ibcon#enter sib2, iclass 17, count 0 2006.231.08:05:59.27#ibcon#flushed, iclass 17, count 0 2006.231.08:05:59.27#ibcon#about to write, iclass 17, count 0 2006.231.08:05:59.27#ibcon#wrote, iclass 17, count 0 2006.231.08:05:59.27#ibcon#about to read 3, iclass 17, count 0 2006.231.08:05:59.31#ibcon#read 3, iclass 17, count 0 2006.231.08:05:59.31#ibcon#about to read 4, iclass 17, count 0 2006.231.08:05:59.31#ibcon#read 4, iclass 17, count 0 2006.231.08:05:59.31#ibcon#about to read 5, iclass 17, count 0 2006.231.08:05:59.31#ibcon#read 5, iclass 17, count 0 2006.231.08:05:59.31#ibcon#about to read 6, iclass 17, count 0 2006.231.08:05:59.31#ibcon#read 6, iclass 17, count 0 2006.231.08:05:59.31#ibcon#end of sib2, iclass 17, count 0 2006.231.08:05:59.31#ibcon#*after write, iclass 17, count 0 2006.231.08:05:59.31#ibcon#*before return 0, iclass 17, count 0 2006.231.08:05:59.31#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:05:59.31#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:05:59.31#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:05:59.31#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:05:59.31$vc4f8/va=5,7 2006.231.08:05:59.31#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.231.08:05:59.31#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.231.08:05:59.31#ibcon#ireg 11 cls_cnt 2 2006.231.08:05:59.31#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:05:59.37#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:05:59.37#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:05:59.37#ibcon#enter wrdev, iclass 19, count 2 2006.231.08:05:59.37#ibcon#first serial, iclass 19, count 2 2006.231.08:05:59.37#ibcon#enter sib2, iclass 19, count 2 2006.231.08:05:59.37#ibcon#flushed, iclass 19, count 2 2006.231.08:05:59.37#ibcon#about to write, iclass 19, count 2 2006.231.08:05:59.37#ibcon#wrote, iclass 19, count 2 2006.231.08:05:59.37#ibcon#about to read 3, iclass 19, count 2 2006.231.08:05:59.39#ibcon#read 3, iclass 19, count 2 2006.231.08:05:59.39#ibcon#about to read 4, iclass 19, count 2 2006.231.08:05:59.39#ibcon#read 4, iclass 19, count 2 2006.231.08:05:59.39#ibcon#about to read 5, iclass 19, count 2 2006.231.08:05:59.39#ibcon#read 5, iclass 19, count 2 2006.231.08:05:59.39#ibcon#about to read 6, iclass 19, count 2 2006.231.08:05:59.39#ibcon#read 6, iclass 19, count 2 2006.231.08:05:59.39#ibcon#end of sib2, iclass 19, count 2 2006.231.08:05:59.39#ibcon#*mode == 0, iclass 19, count 2 2006.231.08:05:59.39#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.231.08:05:59.39#ibcon#[25=AT05-07\r\n] 2006.231.08:05:59.39#ibcon#*before write, iclass 19, count 2 2006.231.08:05:59.39#ibcon#enter sib2, iclass 19, count 2 2006.231.08:05:59.39#ibcon#flushed, iclass 19, count 2 2006.231.08:05:59.39#ibcon#about to write, iclass 19, count 2 2006.231.08:05:59.39#ibcon#wrote, iclass 19, count 2 2006.231.08:05:59.39#ibcon#about to read 3, iclass 19, count 2 2006.231.08:05:59.42#ibcon#read 3, iclass 19, count 2 2006.231.08:05:59.42#ibcon#about to read 4, iclass 19, count 2 2006.231.08:05:59.42#ibcon#read 4, iclass 19, count 2 2006.231.08:05:59.42#ibcon#about to read 5, iclass 19, count 2 2006.231.08:05:59.42#ibcon#read 5, iclass 19, count 2 2006.231.08:05:59.42#ibcon#about to read 6, iclass 19, count 2 2006.231.08:05:59.42#ibcon#read 6, iclass 19, count 2 2006.231.08:05:59.42#ibcon#end of sib2, iclass 19, count 2 2006.231.08:05:59.42#ibcon#*after write, iclass 19, count 2 2006.231.08:05:59.42#ibcon#*before return 0, iclass 19, count 2 2006.231.08:05:59.42#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:05:59.42#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:05:59.42#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.231.08:05:59.42#ibcon#ireg 7 cls_cnt 0 2006.231.08:05:59.42#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:05:59.54#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:05:59.54#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:05:59.54#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:05:59.54#ibcon#first serial, iclass 19, count 0 2006.231.08:05:59.54#ibcon#enter sib2, iclass 19, count 0 2006.231.08:05:59.54#ibcon#flushed, iclass 19, count 0 2006.231.08:05:59.54#ibcon#about to write, iclass 19, count 0 2006.231.08:05:59.54#ibcon#wrote, iclass 19, count 0 2006.231.08:05:59.54#ibcon#about to read 3, iclass 19, count 0 2006.231.08:05:59.56#ibcon#read 3, iclass 19, count 0 2006.231.08:05:59.56#ibcon#about to read 4, iclass 19, count 0 2006.231.08:05:59.56#ibcon#read 4, iclass 19, count 0 2006.231.08:05:59.56#ibcon#about to read 5, iclass 19, count 0 2006.231.08:05:59.56#ibcon#read 5, iclass 19, count 0 2006.231.08:05:59.56#ibcon#about to read 6, iclass 19, count 0 2006.231.08:05:59.57#ibcon#read 6, iclass 19, count 0 2006.231.08:05:59.57#ibcon#end of sib2, iclass 19, count 0 2006.231.08:05:59.57#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:05:59.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:05:59.57#ibcon#[25=USB\r\n] 2006.231.08:05:59.57#ibcon#*before write, iclass 19, count 0 2006.231.08:05:59.57#ibcon#enter sib2, iclass 19, count 0 2006.231.08:05:59.57#ibcon#flushed, iclass 19, count 0 2006.231.08:05:59.57#ibcon#about to write, iclass 19, count 0 2006.231.08:05:59.57#ibcon#wrote, iclass 19, count 0 2006.231.08:05:59.57#ibcon#about to read 3, iclass 19, count 0 2006.231.08:05:59.59#ibcon#read 3, iclass 19, count 0 2006.231.08:05:59.59#ibcon#about to read 4, iclass 19, count 0 2006.231.08:05:59.59#ibcon#read 4, iclass 19, count 0 2006.231.08:05:59.59#ibcon#about to read 5, iclass 19, count 0 2006.231.08:05:59.59#ibcon#read 5, iclass 19, count 0 2006.231.08:05:59.59#ibcon#about to read 6, iclass 19, count 0 2006.231.08:05:59.59#ibcon#read 6, iclass 19, count 0 2006.231.08:05:59.59#ibcon#end of sib2, iclass 19, count 0 2006.231.08:05:59.59#ibcon#*after write, iclass 19, count 0 2006.231.08:05:59.59#ibcon#*before return 0, iclass 19, count 0 2006.231.08:05:59.59#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:05:59.59#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:05:59.59#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:05:59.59#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:05:59.59$vc4f8/valo=6,772.99 2006.231.08:05:59.59#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.08:05:59.59#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.08:05:59.59#ibcon#ireg 17 cls_cnt 0 2006.231.08:05:59.59#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:05:59.59#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:05:59.59#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:05:59.59#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:05:59.59#ibcon#first serial, iclass 21, count 0 2006.231.08:05:59.59#ibcon#enter sib2, iclass 21, count 0 2006.231.08:05:59.59#ibcon#flushed, iclass 21, count 0 2006.231.08:05:59.59#ibcon#about to write, iclass 21, count 0 2006.231.08:05:59.59#ibcon#wrote, iclass 21, count 0 2006.231.08:05:59.59#ibcon#about to read 3, iclass 21, count 0 2006.231.08:05:59.61#ibcon#read 3, iclass 21, count 0 2006.231.08:05:59.61#ibcon#about to read 4, iclass 21, count 0 2006.231.08:05:59.61#ibcon#read 4, iclass 21, count 0 2006.231.08:05:59.61#ibcon#about to read 5, iclass 21, count 0 2006.231.08:05:59.61#ibcon#read 5, iclass 21, count 0 2006.231.08:05:59.61#ibcon#about to read 6, iclass 21, count 0 2006.231.08:05:59.61#ibcon#read 6, iclass 21, count 0 2006.231.08:05:59.61#ibcon#end of sib2, iclass 21, count 0 2006.231.08:05:59.61#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:05:59.61#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:05:59.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:05:59.61#ibcon#*before write, iclass 21, count 0 2006.231.08:05:59.61#ibcon#enter sib2, iclass 21, count 0 2006.231.08:05:59.61#ibcon#flushed, iclass 21, count 0 2006.231.08:05:59.61#ibcon#about to write, iclass 21, count 0 2006.231.08:05:59.61#ibcon#wrote, iclass 21, count 0 2006.231.08:05:59.61#ibcon#about to read 3, iclass 21, count 0 2006.231.08:05:59.65#ibcon#read 3, iclass 21, count 0 2006.231.08:05:59.65#ibcon#about to read 4, iclass 21, count 0 2006.231.08:05:59.65#ibcon#read 4, iclass 21, count 0 2006.231.08:05:59.65#ibcon#about to read 5, iclass 21, count 0 2006.231.08:05:59.65#ibcon#read 5, iclass 21, count 0 2006.231.08:05:59.65#ibcon#about to read 6, iclass 21, count 0 2006.231.08:05:59.65#ibcon#read 6, iclass 21, count 0 2006.231.08:05:59.65#ibcon#end of sib2, iclass 21, count 0 2006.231.08:05:59.65#ibcon#*after write, iclass 21, count 0 2006.231.08:05:59.65#ibcon#*before return 0, iclass 21, count 0 2006.231.08:05:59.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:05:59.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:05:59.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:05:59.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:05:59.65$vc4f8/va=6,6 2006.231.08:05:59.65#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.231.08:05:59.65#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.231.08:05:59.65#ibcon#ireg 11 cls_cnt 2 2006.231.08:05:59.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:05:59.71#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:05:59.71#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:05:59.71#ibcon#enter wrdev, iclass 23, count 2 2006.231.08:05:59.71#ibcon#first serial, iclass 23, count 2 2006.231.08:05:59.71#ibcon#enter sib2, iclass 23, count 2 2006.231.08:05:59.71#ibcon#flushed, iclass 23, count 2 2006.231.08:05:59.71#ibcon#about to write, iclass 23, count 2 2006.231.08:05:59.71#ibcon#wrote, iclass 23, count 2 2006.231.08:05:59.71#ibcon#about to read 3, iclass 23, count 2 2006.231.08:05:59.73#ibcon#read 3, iclass 23, count 2 2006.231.08:05:59.73#ibcon#about to read 4, iclass 23, count 2 2006.231.08:05:59.73#ibcon#read 4, iclass 23, count 2 2006.231.08:05:59.73#ibcon#about to read 5, iclass 23, count 2 2006.231.08:05:59.73#ibcon#read 5, iclass 23, count 2 2006.231.08:05:59.73#ibcon#about to read 6, iclass 23, count 2 2006.231.08:05:59.73#ibcon#read 6, iclass 23, count 2 2006.231.08:05:59.73#ibcon#end of sib2, iclass 23, count 2 2006.231.08:05:59.73#ibcon#*mode == 0, iclass 23, count 2 2006.231.08:05:59.73#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.231.08:05:59.73#ibcon#[25=AT06-06\r\n] 2006.231.08:05:59.73#ibcon#*before write, iclass 23, count 2 2006.231.08:05:59.73#ibcon#enter sib2, iclass 23, count 2 2006.231.08:05:59.73#ibcon#flushed, iclass 23, count 2 2006.231.08:05:59.73#ibcon#about to write, iclass 23, count 2 2006.231.08:05:59.73#ibcon#wrote, iclass 23, count 2 2006.231.08:05:59.73#ibcon#about to read 3, iclass 23, count 2 2006.231.08:05:59.76#ibcon#read 3, iclass 23, count 2 2006.231.08:05:59.76#ibcon#about to read 4, iclass 23, count 2 2006.231.08:05:59.76#ibcon#read 4, iclass 23, count 2 2006.231.08:05:59.76#ibcon#about to read 5, iclass 23, count 2 2006.231.08:05:59.76#ibcon#read 5, iclass 23, count 2 2006.231.08:05:59.76#ibcon#about to read 6, iclass 23, count 2 2006.231.08:05:59.76#ibcon#read 6, iclass 23, count 2 2006.231.08:05:59.76#ibcon#end of sib2, iclass 23, count 2 2006.231.08:05:59.76#ibcon#*after write, iclass 23, count 2 2006.231.08:05:59.76#ibcon#*before return 0, iclass 23, count 2 2006.231.08:05:59.76#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:05:59.76#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:05:59.76#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.231.08:05:59.76#ibcon#ireg 7 cls_cnt 0 2006.231.08:05:59.76#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:05:59.88#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:05:59.88#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:05:59.88#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:05:59.88#ibcon#first serial, iclass 23, count 0 2006.231.08:05:59.88#ibcon#enter sib2, iclass 23, count 0 2006.231.08:05:59.88#ibcon#flushed, iclass 23, count 0 2006.231.08:05:59.88#ibcon#about to write, iclass 23, count 0 2006.231.08:05:59.88#ibcon#wrote, iclass 23, count 0 2006.231.08:05:59.88#ibcon#about to read 3, iclass 23, count 0 2006.231.08:05:59.90#ibcon#read 3, iclass 23, count 0 2006.231.08:05:59.90#ibcon#about to read 4, iclass 23, count 0 2006.231.08:05:59.90#ibcon#read 4, iclass 23, count 0 2006.231.08:05:59.90#ibcon#about to read 5, iclass 23, count 0 2006.231.08:05:59.90#ibcon#read 5, iclass 23, count 0 2006.231.08:05:59.90#ibcon#about to read 6, iclass 23, count 0 2006.231.08:05:59.90#ibcon#read 6, iclass 23, count 0 2006.231.08:05:59.90#ibcon#end of sib2, iclass 23, count 0 2006.231.08:05:59.90#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:05:59.90#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:05:59.90#ibcon#[25=USB\r\n] 2006.231.08:05:59.90#ibcon#*before write, iclass 23, count 0 2006.231.08:05:59.90#ibcon#enter sib2, iclass 23, count 0 2006.231.08:05:59.90#ibcon#flushed, iclass 23, count 0 2006.231.08:05:59.90#ibcon#about to write, iclass 23, count 0 2006.231.08:05:59.90#ibcon#wrote, iclass 23, count 0 2006.231.08:05:59.90#ibcon#about to read 3, iclass 23, count 0 2006.231.08:05:59.93#ibcon#read 3, iclass 23, count 0 2006.231.08:05:59.93#ibcon#about to read 4, iclass 23, count 0 2006.231.08:05:59.93#ibcon#read 4, iclass 23, count 0 2006.231.08:05:59.93#ibcon#about to read 5, iclass 23, count 0 2006.231.08:05:59.93#ibcon#read 5, iclass 23, count 0 2006.231.08:05:59.93#ibcon#about to read 6, iclass 23, count 0 2006.231.08:05:59.93#ibcon#read 6, iclass 23, count 0 2006.231.08:05:59.93#ibcon#end of sib2, iclass 23, count 0 2006.231.08:05:59.93#ibcon#*after write, iclass 23, count 0 2006.231.08:05:59.93#ibcon#*before return 0, iclass 23, count 0 2006.231.08:05:59.93#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:05:59.93#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:05:59.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:05:59.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:05:59.93$vc4f8/valo=7,832.99 2006.231.08:05:59.93#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.231.08:05:59.93#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.231.08:05:59.93#ibcon#ireg 17 cls_cnt 0 2006.231.08:05:59.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:05:59.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:05:59.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:05:59.93#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:05:59.93#ibcon#first serial, iclass 25, count 0 2006.231.08:05:59.93#ibcon#enter sib2, iclass 25, count 0 2006.231.08:05:59.93#ibcon#flushed, iclass 25, count 0 2006.231.08:05:59.93#ibcon#about to write, iclass 25, count 0 2006.231.08:05:59.93#ibcon#wrote, iclass 25, count 0 2006.231.08:05:59.93#ibcon#about to read 3, iclass 25, count 0 2006.231.08:05:59.95#ibcon#read 3, iclass 25, count 0 2006.231.08:05:59.95#ibcon#about to read 4, iclass 25, count 0 2006.231.08:05:59.95#ibcon#read 4, iclass 25, count 0 2006.231.08:05:59.95#ibcon#about to read 5, iclass 25, count 0 2006.231.08:05:59.95#ibcon#read 5, iclass 25, count 0 2006.231.08:05:59.95#ibcon#about to read 6, iclass 25, count 0 2006.231.08:05:59.95#ibcon#read 6, iclass 25, count 0 2006.231.08:05:59.95#ibcon#end of sib2, iclass 25, count 0 2006.231.08:05:59.95#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:05:59.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:05:59.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:05:59.95#ibcon#*before write, iclass 25, count 0 2006.231.08:05:59.95#ibcon#enter sib2, iclass 25, count 0 2006.231.08:05:59.95#ibcon#flushed, iclass 25, count 0 2006.231.08:05:59.95#ibcon#about to write, iclass 25, count 0 2006.231.08:05:59.95#ibcon#wrote, iclass 25, count 0 2006.231.08:05:59.95#ibcon#about to read 3, iclass 25, count 0 2006.231.08:05:59.99#ibcon#read 3, iclass 25, count 0 2006.231.08:05:59.99#ibcon#about to read 4, iclass 25, count 0 2006.231.08:05:59.99#ibcon#read 4, iclass 25, count 0 2006.231.08:05:59.99#ibcon#about to read 5, iclass 25, count 0 2006.231.08:05:59.99#ibcon#read 5, iclass 25, count 0 2006.231.08:05:59.99#ibcon#about to read 6, iclass 25, count 0 2006.231.08:05:59.99#ibcon#read 6, iclass 25, count 0 2006.231.08:05:59.99#ibcon#end of sib2, iclass 25, count 0 2006.231.08:05:59.99#ibcon#*after write, iclass 25, count 0 2006.231.08:05:59.99#ibcon#*before return 0, iclass 25, count 0 2006.231.08:05:59.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:05:59.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:05:59.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:05:59.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:05:59.99$vc4f8/va=7,6 2006.231.08:05:59.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.231.08:05:59.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.231.08:05:59.99#ibcon#ireg 11 cls_cnt 2 2006.231.08:05:59.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:06:00.05#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:06:00.05#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:06:00.05#ibcon#enter wrdev, iclass 27, count 2 2006.231.08:06:00.05#ibcon#first serial, iclass 27, count 2 2006.231.08:06:00.05#ibcon#enter sib2, iclass 27, count 2 2006.231.08:06:00.05#ibcon#flushed, iclass 27, count 2 2006.231.08:06:00.05#ibcon#about to write, iclass 27, count 2 2006.231.08:06:00.05#ibcon#wrote, iclass 27, count 2 2006.231.08:06:00.05#ibcon#about to read 3, iclass 27, count 2 2006.231.08:06:00.07#ibcon#read 3, iclass 27, count 2 2006.231.08:06:00.07#ibcon#about to read 4, iclass 27, count 2 2006.231.08:06:00.07#ibcon#read 4, iclass 27, count 2 2006.231.08:06:00.07#ibcon#about to read 5, iclass 27, count 2 2006.231.08:06:00.07#ibcon#read 5, iclass 27, count 2 2006.231.08:06:00.07#ibcon#about to read 6, iclass 27, count 2 2006.231.08:06:00.07#ibcon#read 6, iclass 27, count 2 2006.231.08:06:00.07#ibcon#end of sib2, iclass 27, count 2 2006.231.08:06:00.07#ibcon#*mode == 0, iclass 27, count 2 2006.231.08:06:00.07#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.231.08:06:00.07#ibcon#[25=AT07-06\r\n] 2006.231.08:06:00.07#ibcon#*before write, iclass 27, count 2 2006.231.08:06:00.07#ibcon#enter sib2, iclass 27, count 2 2006.231.08:06:00.07#ibcon#flushed, iclass 27, count 2 2006.231.08:06:00.07#ibcon#about to write, iclass 27, count 2 2006.231.08:06:00.07#ibcon#wrote, iclass 27, count 2 2006.231.08:06:00.07#ibcon#about to read 3, iclass 27, count 2 2006.231.08:06:00.10#ibcon#read 3, iclass 27, count 2 2006.231.08:06:00.10#ibcon#about to read 4, iclass 27, count 2 2006.231.08:06:00.10#ibcon#read 4, iclass 27, count 2 2006.231.08:06:00.10#ibcon#about to read 5, iclass 27, count 2 2006.231.08:06:00.10#ibcon#read 5, iclass 27, count 2 2006.231.08:06:00.10#ibcon#about to read 6, iclass 27, count 2 2006.231.08:06:00.10#ibcon#read 6, iclass 27, count 2 2006.231.08:06:00.10#ibcon#end of sib2, iclass 27, count 2 2006.231.08:06:00.10#ibcon#*after write, iclass 27, count 2 2006.231.08:06:00.10#ibcon#*before return 0, iclass 27, count 2 2006.231.08:06:00.10#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:06:00.10#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:06:00.10#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.231.08:06:00.10#ibcon#ireg 7 cls_cnt 0 2006.231.08:06:00.10#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:06:00.22#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:06:00.22#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:06:00.22#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:06:00.22#ibcon#first serial, iclass 27, count 0 2006.231.08:06:00.22#ibcon#enter sib2, iclass 27, count 0 2006.231.08:06:00.22#ibcon#flushed, iclass 27, count 0 2006.231.08:06:00.22#ibcon#about to write, iclass 27, count 0 2006.231.08:06:00.22#ibcon#wrote, iclass 27, count 0 2006.231.08:06:00.22#ibcon#about to read 3, iclass 27, count 0 2006.231.08:06:00.24#ibcon#read 3, iclass 27, count 0 2006.231.08:06:00.24#ibcon#about to read 4, iclass 27, count 0 2006.231.08:06:00.24#ibcon#read 4, iclass 27, count 0 2006.231.08:06:00.24#ibcon#about to read 5, iclass 27, count 0 2006.231.08:06:00.24#ibcon#read 5, iclass 27, count 0 2006.231.08:06:00.24#ibcon#about to read 6, iclass 27, count 0 2006.231.08:06:00.24#ibcon#read 6, iclass 27, count 0 2006.231.08:06:00.24#ibcon#end of sib2, iclass 27, count 0 2006.231.08:06:00.24#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:06:00.24#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:06:00.24#ibcon#[25=USB\r\n] 2006.231.08:06:00.24#ibcon#*before write, iclass 27, count 0 2006.231.08:06:00.24#ibcon#enter sib2, iclass 27, count 0 2006.231.08:06:00.24#ibcon#flushed, iclass 27, count 0 2006.231.08:06:00.24#ibcon#about to write, iclass 27, count 0 2006.231.08:06:00.24#ibcon#wrote, iclass 27, count 0 2006.231.08:06:00.24#ibcon#about to read 3, iclass 27, count 0 2006.231.08:06:00.27#ibcon#read 3, iclass 27, count 0 2006.231.08:06:00.27#ibcon#about to read 4, iclass 27, count 0 2006.231.08:06:00.27#ibcon#read 4, iclass 27, count 0 2006.231.08:06:00.27#ibcon#about to read 5, iclass 27, count 0 2006.231.08:06:00.27#ibcon#read 5, iclass 27, count 0 2006.231.08:06:00.27#ibcon#about to read 6, iclass 27, count 0 2006.231.08:06:00.27#ibcon#read 6, iclass 27, count 0 2006.231.08:06:00.27#ibcon#end of sib2, iclass 27, count 0 2006.231.08:06:00.27#ibcon#*after write, iclass 27, count 0 2006.231.08:06:00.27#ibcon#*before return 0, iclass 27, count 0 2006.231.08:06:00.27#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:06:00.27#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:06:00.27#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:06:00.27#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:06:00.27$vc4f8/valo=8,852.99 2006.231.08:06:00.27#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.231.08:06:00.27#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.231.08:06:00.27#ibcon#ireg 17 cls_cnt 0 2006.231.08:06:00.27#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:06:00.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:06:00.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:06:00.27#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:06:00.27#ibcon#first serial, iclass 29, count 0 2006.231.08:06:00.27#ibcon#enter sib2, iclass 29, count 0 2006.231.08:06:00.27#ibcon#flushed, iclass 29, count 0 2006.231.08:06:00.27#ibcon#about to write, iclass 29, count 0 2006.231.08:06:00.27#ibcon#wrote, iclass 29, count 0 2006.231.08:06:00.27#ibcon#about to read 3, iclass 29, count 0 2006.231.08:06:00.29#ibcon#read 3, iclass 29, count 0 2006.231.08:06:00.29#ibcon#about to read 4, iclass 29, count 0 2006.231.08:06:00.29#ibcon#read 4, iclass 29, count 0 2006.231.08:06:00.29#ibcon#about to read 5, iclass 29, count 0 2006.231.08:06:00.29#ibcon#read 5, iclass 29, count 0 2006.231.08:06:00.29#ibcon#about to read 6, iclass 29, count 0 2006.231.08:06:00.29#ibcon#read 6, iclass 29, count 0 2006.231.08:06:00.29#ibcon#end of sib2, iclass 29, count 0 2006.231.08:06:00.29#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:06:00.29#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:06:00.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:06:00.29#ibcon#*before write, iclass 29, count 0 2006.231.08:06:00.29#ibcon#enter sib2, iclass 29, count 0 2006.231.08:06:00.29#ibcon#flushed, iclass 29, count 0 2006.231.08:06:00.29#ibcon#about to write, iclass 29, count 0 2006.231.08:06:00.29#ibcon#wrote, iclass 29, count 0 2006.231.08:06:00.29#ibcon#about to read 3, iclass 29, count 0 2006.231.08:06:00.33#ibcon#read 3, iclass 29, count 0 2006.231.08:06:00.33#ibcon#about to read 4, iclass 29, count 0 2006.231.08:06:00.33#ibcon#read 4, iclass 29, count 0 2006.231.08:06:00.33#ibcon#about to read 5, iclass 29, count 0 2006.231.08:06:00.33#ibcon#read 5, iclass 29, count 0 2006.231.08:06:00.33#ibcon#about to read 6, iclass 29, count 0 2006.231.08:06:00.33#ibcon#read 6, iclass 29, count 0 2006.231.08:06:00.33#ibcon#end of sib2, iclass 29, count 0 2006.231.08:06:00.33#ibcon#*after write, iclass 29, count 0 2006.231.08:06:00.33#ibcon#*before return 0, iclass 29, count 0 2006.231.08:06:00.33#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:06:00.33#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:06:00.33#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:06:00.33#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:06:00.33$vc4f8/va=8,6 2006.231.08:06:00.33#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.231.08:06:00.33#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.231.08:06:00.33#ibcon#ireg 11 cls_cnt 2 2006.231.08:06:00.33#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:06:00.39#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:06:00.39#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:06:00.39#ibcon#enter wrdev, iclass 31, count 2 2006.231.08:06:00.39#ibcon#first serial, iclass 31, count 2 2006.231.08:06:00.39#ibcon#enter sib2, iclass 31, count 2 2006.231.08:06:00.39#ibcon#flushed, iclass 31, count 2 2006.231.08:06:00.39#ibcon#about to write, iclass 31, count 2 2006.231.08:06:00.39#ibcon#wrote, iclass 31, count 2 2006.231.08:06:00.39#ibcon#about to read 3, iclass 31, count 2 2006.231.08:06:00.41#ibcon#read 3, iclass 31, count 2 2006.231.08:06:00.41#ibcon#about to read 4, iclass 31, count 2 2006.231.08:06:00.41#ibcon#read 4, iclass 31, count 2 2006.231.08:06:00.41#ibcon#about to read 5, iclass 31, count 2 2006.231.08:06:00.41#ibcon#read 5, iclass 31, count 2 2006.231.08:06:00.41#ibcon#about to read 6, iclass 31, count 2 2006.231.08:06:00.41#ibcon#read 6, iclass 31, count 2 2006.231.08:06:00.41#ibcon#end of sib2, iclass 31, count 2 2006.231.08:06:00.41#ibcon#*mode == 0, iclass 31, count 2 2006.231.08:06:00.41#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.231.08:06:00.41#ibcon#[25=AT08-06\r\n] 2006.231.08:06:00.41#ibcon#*before write, iclass 31, count 2 2006.231.08:06:00.41#ibcon#enter sib2, iclass 31, count 2 2006.231.08:06:00.41#ibcon#flushed, iclass 31, count 2 2006.231.08:06:00.41#ibcon#about to write, iclass 31, count 2 2006.231.08:06:00.41#ibcon#wrote, iclass 31, count 2 2006.231.08:06:00.41#ibcon#about to read 3, iclass 31, count 2 2006.231.08:06:00.44#ibcon#read 3, iclass 31, count 2 2006.231.08:06:00.44#ibcon#about to read 4, iclass 31, count 2 2006.231.08:06:00.44#ibcon#read 4, iclass 31, count 2 2006.231.08:06:00.44#ibcon#about to read 5, iclass 31, count 2 2006.231.08:06:00.44#ibcon#read 5, iclass 31, count 2 2006.231.08:06:00.44#ibcon#about to read 6, iclass 31, count 2 2006.231.08:06:00.44#ibcon#read 6, iclass 31, count 2 2006.231.08:06:00.44#ibcon#end of sib2, iclass 31, count 2 2006.231.08:06:00.44#ibcon#*after write, iclass 31, count 2 2006.231.08:06:00.44#ibcon#*before return 0, iclass 31, count 2 2006.231.08:06:00.44#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:06:00.44#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:06:00.44#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.231.08:06:00.44#ibcon#ireg 7 cls_cnt 0 2006.231.08:06:00.44#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:06:00.56#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:06:00.56#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:06:00.56#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:06:00.56#ibcon#first serial, iclass 31, count 0 2006.231.08:06:00.56#ibcon#enter sib2, iclass 31, count 0 2006.231.08:06:00.56#ibcon#flushed, iclass 31, count 0 2006.231.08:06:00.56#ibcon#about to write, iclass 31, count 0 2006.231.08:06:00.56#ibcon#wrote, iclass 31, count 0 2006.231.08:06:00.56#ibcon#about to read 3, iclass 31, count 0 2006.231.08:06:00.58#ibcon#read 3, iclass 31, count 0 2006.231.08:06:00.58#ibcon#about to read 4, iclass 31, count 0 2006.231.08:06:00.58#ibcon#read 4, iclass 31, count 0 2006.231.08:06:00.58#ibcon#about to read 5, iclass 31, count 0 2006.231.08:06:00.58#ibcon#read 5, iclass 31, count 0 2006.231.08:06:00.58#ibcon#about to read 6, iclass 31, count 0 2006.231.08:06:00.58#ibcon#read 6, iclass 31, count 0 2006.231.08:06:00.58#ibcon#end of sib2, iclass 31, count 0 2006.231.08:06:00.58#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:06:00.58#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:06:00.58#ibcon#[25=USB\r\n] 2006.231.08:06:00.58#ibcon#*before write, iclass 31, count 0 2006.231.08:06:00.58#ibcon#enter sib2, iclass 31, count 0 2006.231.08:06:00.58#ibcon#flushed, iclass 31, count 0 2006.231.08:06:00.58#ibcon#about to write, iclass 31, count 0 2006.231.08:06:00.58#ibcon#wrote, iclass 31, count 0 2006.231.08:06:00.58#ibcon#about to read 3, iclass 31, count 0 2006.231.08:06:00.61#ibcon#read 3, iclass 31, count 0 2006.231.08:06:00.61#ibcon#about to read 4, iclass 31, count 0 2006.231.08:06:00.61#ibcon#read 4, iclass 31, count 0 2006.231.08:06:00.61#ibcon#about to read 5, iclass 31, count 0 2006.231.08:06:00.61#ibcon#read 5, iclass 31, count 0 2006.231.08:06:00.61#ibcon#about to read 6, iclass 31, count 0 2006.231.08:06:00.61#ibcon#read 6, iclass 31, count 0 2006.231.08:06:00.61#ibcon#end of sib2, iclass 31, count 0 2006.231.08:06:00.61#ibcon#*after write, iclass 31, count 0 2006.231.08:06:00.61#ibcon#*before return 0, iclass 31, count 0 2006.231.08:06:00.61#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:06:00.61#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:06:00.61#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:06:00.61#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:06:00.61$vc4f8/vblo=1,632.99 2006.231.08:06:00.61#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.08:06:00.61#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.08:06:00.61#ibcon#ireg 17 cls_cnt 0 2006.231.08:06:00.61#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:06:00.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:06:00.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:06:00.61#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:06:00.61#ibcon#first serial, iclass 33, count 0 2006.231.08:06:00.61#ibcon#enter sib2, iclass 33, count 0 2006.231.08:06:00.61#ibcon#flushed, iclass 33, count 0 2006.231.08:06:00.61#ibcon#about to write, iclass 33, count 0 2006.231.08:06:00.61#ibcon#wrote, iclass 33, count 0 2006.231.08:06:00.61#ibcon#about to read 3, iclass 33, count 0 2006.231.08:06:00.63#ibcon#read 3, iclass 33, count 0 2006.231.08:06:00.63#ibcon#about to read 4, iclass 33, count 0 2006.231.08:06:00.63#ibcon#read 4, iclass 33, count 0 2006.231.08:06:00.63#ibcon#about to read 5, iclass 33, count 0 2006.231.08:06:00.63#ibcon#read 5, iclass 33, count 0 2006.231.08:06:00.63#ibcon#about to read 6, iclass 33, count 0 2006.231.08:06:00.63#ibcon#read 6, iclass 33, count 0 2006.231.08:06:00.63#ibcon#end of sib2, iclass 33, count 0 2006.231.08:06:00.63#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:06:00.63#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:06:00.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:06:00.63#ibcon#*before write, iclass 33, count 0 2006.231.08:06:00.63#ibcon#enter sib2, iclass 33, count 0 2006.231.08:06:00.63#ibcon#flushed, iclass 33, count 0 2006.231.08:06:00.63#ibcon#about to write, iclass 33, count 0 2006.231.08:06:00.63#ibcon#wrote, iclass 33, count 0 2006.231.08:06:00.63#ibcon#about to read 3, iclass 33, count 0 2006.231.08:06:00.67#ibcon#read 3, iclass 33, count 0 2006.231.08:06:00.67#ibcon#about to read 4, iclass 33, count 0 2006.231.08:06:00.67#ibcon#read 4, iclass 33, count 0 2006.231.08:06:00.67#ibcon#about to read 5, iclass 33, count 0 2006.231.08:06:00.67#ibcon#read 5, iclass 33, count 0 2006.231.08:06:00.67#ibcon#about to read 6, iclass 33, count 0 2006.231.08:06:00.67#ibcon#read 6, iclass 33, count 0 2006.231.08:06:00.67#ibcon#end of sib2, iclass 33, count 0 2006.231.08:06:00.67#ibcon#*after write, iclass 33, count 0 2006.231.08:06:00.67#ibcon#*before return 0, iclass 33, count 0 2006.231.08:06:00.67#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:06:00.67#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:06:00.67#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:06:00.67#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:06:00.67$vc4f8/vb=1,4 2006.231.08:06:00.67#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.08:06:00.67#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.08:06:00.67#ibcon#ireg 11 cls_cnt 2 2006.231.08:06:00.67#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:06:00.67#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:06:00.67#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:06:00.67#ibcon#enter wrdev, iclass 35, count 2 2006.231.08:06:00.67#ibcon#first serial, iclass 35, count 2 2006.231.08:06:00.67#ibcon#enter sib2, iclass 35, count 2 2006.231.08:06:00.67#ibcon#flushed, iclass 35, count 2 2006.231.08:06:00.67#ibcon#about to write, iclass 35, count 2 2006.231.08:06:00.67#ibcon#wrote, iclass 35, count 2 2006.231.08:06:00.67#ibcon#about to read 3, iclass 35, count 2 2006.231.08:06:00.69#ibcon#read 3, iclass 35, count 2 2006.231.08:06:00.69#ibcon#about to read 4, iclass 35, count 2 2006.231.08:06:00.69#ibcon#read 4, iclass 35, count 2 2006.231.08:06:00.69#ibcon#about to read 5, iclass 35, count 2 2006.231.08:06:00.69#ibcon#read 5, iclass 35, count 2 2006.231.08:06:00.69#ibcon#about to read 6, iclass 35, count 2 2006.231.08:06:00.69#ibcon#read 6, iclass 35, count 2 2006.231.08:06:00.69#ibcon#end of sib2, iclass 35, count 2 2006.231.08:06:00.69#ibcon#*mode == 0, iclass 35, count 2 2006.231.08:06:00.69#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.08:06:00.69#ibcon#[27=AT01-04\r\n] 2006.231.08:06:00.69#ibcon#*before write, iclass 35, count 2 2006.231.08:06:00.69#ibcon#enter sib2, iclass 35, count 2 2006.231.08:06:00.69#ibcon#flushed, iclass 35, count 2 2006.231.08:06:00.69#ibcon#about to write, iclass 35, count 2 2006.231.08:06:00.69#ibcon#wrote, iclass 35, count 2 2006.231.08:06:00.69#ibcon#about to read 3, iclass 35, count 2 2006.231.08:06:00.72#ibcon#read 3, iclass 35, count 2 2006.231.08:06:00.72#ibcon#about to read 4, iclass 35, count 2 2006.231.08:06:00.72#ibcon#read 4, iclass 35, count 2 2006.231.08:06:00.72#ibcon#about to read 5, iclass 35, count 2 2006.231.08:06:00.72#ibcon#read 5, iclass 35, count 2 2006.231.08:06:00.72#ibcon#about to read 6, iclass 35, count 2 2006.231.08:06:00.72#ibcon#read 6, iclass 35, count 2 2006.231.08:06:00.72#ibcon#end of sib2, iclass 35, count 2 2006.231.08:06:00.72#ibcon#*after write, iclass 35, count 2 2006.231.08:06:00.72#ibcon#*before return 0, iclass 35, count 2 2006.231.08:06:00.72#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:06:00.72#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:06:00.72#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.08:06:00.72#ibcon#ireg 7 cls_cnt 0 2006.231.08:06:00.72#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:06:00.84#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:06:00.84#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:06:00.84#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:06:00.84#ibcon#first serial, iclass 35, count 0 2006.231.08:06:00.84#ibcon#enter sib2, iclass 35, count 0 2006.231.08:06:00.84#ibcon#flushed, iclass 35, count 0 2006.231.08:06:00.84#ibcon#about to write, iclass 35, count 0 2006.231.08:06:00.84#ibcon#wrote, iclass 35, count 0 2006.231.08:06:00.84#ibcon#about to read 3, iclass 35, count 0 2006.231.08:06:00.86#ibcon#read 3, iclass 35, count 0 2006.231.08:06:00.86#ibcon#about to read 4, iclass 35, count 0 2006.231.08:06:00.86#ibcon#read 4, iclass 35, count 0 2006.231.08:06:00.86#ibcon#about to read 5, iclass 35, count 0 2006.231.08:06:00.86#ibcon#read 5, iclass 35, count 0 2006.231.08:06:00.86#ibcon#about to read 6, iclass 35, count 0 2006.231.08:06:00.86#ibcon#read 6, iclass 35, count 0 2006.231.08:06:00.86#ibcon#end of sib2, iclass 35, count 0 2006.231.08:06:00.86#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:06:00.86#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:06:00.86#ibcon#[27=USB\r\n] 2006.231.08:06:00.86#ibcon#*before write, iclass 35, count 0 2006.231.08:06:00.86#ibcon#enter sib2, iclass 35, count 0 2006.231.08:06:00.86#ibcon#flushed, iclass 35, count 0 2006.231.08:06:00.86#ibcon#about to write, iclass 35, count 0 2006.231.08:06:00.86#ibcon#wrote, iclass 35, count 0 2006.231.08:06:00.86#ibcon#about to read 3, iclass 35, count 0 2006.231.08:06:00.90#ibcon#read 3, iclass 35, count 0 2006.231.08:06:00.90#ibcon#about to read 4, iclass 35, count 0 2006.231.08:06:00.90#ibcon#read 4, iclass 35, count 0 2006.231.08:06:00.90#ibcon#about to read 5, iclass 35, count 0 2006.231.08:06:00.90#ibcon#read 5, iclass 35, count 0 2006.231.08:06:00.90#ibcon#about to read 6, iclass 35, count 0 2006.231.08:06:00.90#ibcon#read 6, iclass 35, count 0 2006.231.08:06:00.90#ibcon#end of sib2, iclass 35, count 0 2006.231.08:06:00.90#ibcon#*after write, iclass 35, count 0 2006.231.08:06:00.90#ibcon#*before return 0, iclass 35, count 0 2006.231.08:06:00.90#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:06:00.90#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:06:00.90#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:06:00.90#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:06:00.90$vc4f8/vblo=2,640.99 2006.231.08:06:00.90#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.08:06:00.90#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.08:06:00.90#ibcon#ireg 17 cls_cnt 0 2006.231.08:06:00.90#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:06:00.90#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:06:00.90#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:06:00.90#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:06:00.90#ibcon#first serial, iclass 37, count 0 2006.231.08:06:00.90#ibcon#enter sib2, iclass 37, count 0 2006.231.08:06:00.90#ibcon#flushed, iclass 37, count 0 2006.231.08:06:00.90#ibcon#about to write, iclass 37, count 0 2006.231.08:06:00.90#ibcon#wrote, iclass 37, count 0 2006.231.08:06:00.90#ibcon#about to read 3, iclass 37, count 0 2006.231.08:06:00.92#ibcon#read 3, iclass 37, count 0 2006.231.08:06:00.92#ibcon#about to read 4, iclass 37, count 0 2006.231.08:06:00.92#ibcon#read 4, iclass 37, count 0 2006.231.08:06:00.92#ibcon#about to read 5, iclass 37, count 0 2006.231.08:06:00.92#ibcon#read 5, iclass 37, count 0 2006.231.08:06:00.92#ibcon#about to read 6, iclass 37, count 0 2006.231.08:06:00.92#ibcon#read 6, iclass 37, count 0 2006.231.08:06:00.92#ibcon#end of sib2, iclass 37, count 0 2006.231.08:06:00.92#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:06:00.92#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:06:00.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:06:00.92#ibcon#*before write, iclass 37, count 0 2006.231.08:06:00.92#ibcon#enter sib2, iclass 37, count 0 2006.231.08:06:00.92#ibcon#flushed, iclass 37, count 0 2006.231.08:06:00.92#ibcon#about to write, iclass 37, count 0 2006.231.08:06:00.92#ibcon#wrote, iclass 37, count 0 2006.231.08:06:00.92#ibcon#about to read 3, iclass 37, count 0 2006.231.08:06:00.96#ibcon#read 3, iclass 37, count 0 2006.231.08:06:00.96#ibcon#about to read 4, iclass 37, count 0 2006.231.08:06:00.96#ibcon#read 4, iclass 37, count 0 2006.231.08:06:00.96#ibcon#about to read 5, iclass 37, count 0 2006.231.08:06:00.96#ibcon#read 5, iclass 37, count 0 2006.231.08:06:00.96#ibcon#about to read 6, iclass 37, count 0 2006.231.08:06:00.96#ibcon#read 6, iclass 37, count 0 2006.231.08:06:00.96#ibcon#end of sib2, iclass 37, count 0 2006.231.08:06:00.96#ibcon#*after write, iclass 37, count 0 2006.231.08:06:00.96#ibcon#*before return 0, iclass 37, count 0 2006.231.08:06:00.96#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:06:00.96#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:06:00.96#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:06:00.96#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:06:00.96$vc4f8/vb=2,4 2006.231.08:06:00.96#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.08:06:00.96#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.08:06:00.96#ibcon#ireg 11 cls_cnt 2 2006.231.08:06:00.96#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:06:01.02#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:06:01.02#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:06:01.02#ibcon#enter wrdev, iclass 39, count 2 2006.231.08:06:01.02#ibcon#first serial, iclass 39, count 2 2006.231.08:06:01.02#ibcon#enter sib2, iclass 39, count 2 2006.231.08:06:01.02#ibcon#flushed, iclass 39, count 2 2006.231.08:06:01.02#ibcon#about to write, iclass 39, count 2 2006.231.08:06:01.02#ibcon#wrote, iclass 39, count 2 2006.231.08:06:01.02#ibcon#about to read 3, iclass 39, count 2 2006.231.08:06:01.04#ibcon#read 3, iclass 39, count 2 2006.231.08:06:01.04#ibcon#about to read 4, iclass 39, count 2 2006.231.08:06:01.04#ibcon#read 4, iclass 39, count 2 2006.231.08:06:01.04#ibcon#about to read 5, iclass 39, count 2 2006.231.08:06:01.04#ibcon#read 5, iclass 39, count 2 2006.231.08:06:01.04#ibcon#about to read 6, iclass 39, count 2 2006.231.08:06:01.04#ibcon#read 6, iclass 39, count 2 2006.231.08:06:01.04#ibcon#end of sib2, iclass 39, count 2 2006.231.08:06:01.04#ibcon#*mode == 0, iclass 39, count 2 2006.231.08:06:01.04#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.08:06:01.04#ibcon#[27=AT02-04\r\n] 2006.231.08:06:01.04#ibcon#*before write, iclass 39, count 2 2006.231.08:06:01.04#ibcon#enter sib2, iclass 39, count 2 2006.231.08:06:01.04#ibcon#flushed, iclass 39, count 2 2006.231.08:06:01.04#ibcon#about to write, iclass 39, count 2 2006.231.08:06:01.04#ibcon#wrote, iclass 39, count 2 2006.231.08:06:01.04#ibcon#about to read 3, iclass 39, count 2 2006.231.08:06:01.07#ibcon#read 3, iclass 39, count 2 2006.231.08:06:01.07#ibcon#about to read 4, iclass 39, count 2 2006.231.08:06:01.07#ibcon#read 4, iclass 39, count 2 2006.231.08:06:01.07#ibcon#about to read 5, iclass 39, count 2 2006.231.08:06:01.07#ibcon#read 5, iclass 39, count 2 2006.231.08:06:01.07#ibcon#about to read 6, iclass 39, count 2 2006.231.08:06:01.07#ibcon#read 6, iclass 39, count 2 2006.231.08:06:01.07#ibcon#end of sib2, iclass 39, count 2 2006.231.08:06:01.07#ibcon#*after write, iclass 39, count 2 2006.231.08:06:01.07#ibcon#*before return 0, iclass 39, count 2 2006.231.08:06:01.07#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:06:01.07#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:06:01.07#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.08:06:01.07#ibcon#ireg 7 cls_cnt 0 2006.231.08:06:01.07#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:06:01.19#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:06:01.19#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:06:01.19#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:06:01.19#ibcon#first serial, iclass 39, count 0 2006.231.08:06:01.19#ibcon#enter sib2, iclass 39, count 0 2006.231.08:06:01.19#ibcon#flushed, iclass 39, count 0 2006.231.08:06:01.19#ibcon#about to write, iclass 39, count 0 2006.231.08:06:01.19#ibcon#wrote, iclass 39, count 0 2006.231.08:06:01.19#ibcon#about to read 3, iclass 39, count 0 2006.231.08:06:01.21#ibcon#read 3, iclass 39, count 0 2006.231.08:06:01.21#ibcon#about to read 4, iclass 39, count 0 2006.231.08:06:01.21#ibcon#read 4, iclass 39, count 0 2006.231.08:06:01.21#ibcon#about to read 5, iclass 39, count 0 2006.231.08:06:01.21#ibcon#read 5, iclass 39, count 0 2006.231.08:06:01.21#ibcon#about to read 6, iclass 39, count 0 2006.231.08:06:01.21#ibcon#read 6, iclass 39, count 0 2006.231.08:06:01.21#ibcon#end of sib2, iclass 39, count 0 2006.231.08:06:01.21#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:06:01.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:06:01.21#ibcon#[27=USB\r\n] 2006.231.08:06:01.21#ibcon#*before write, iclass 39, count 0 2006.231.08:06:01.21#ibcon#enter sib2, iclass 39, count 0 2006.231.08:06:01.21#ibcon#flushed, iclass 39, count 0 2006.231.08:06:01.21#ibcon#about to write, iclass 39, count 0 2006.231.08:06:01.21#ibcon#wrote, iclass 39, count 0 2006.231.08:06:01.21#ibcon#about to read 3, iclass 39, count 0 2006.231.08:06:01.24#ibcon#read 3, iclass 39, count 0 2006.231.08:06:01.24#ibcon#about to read 4, iclass 39, count 0 2006.231.08:06:01.24#ibcon#read 4, iclass 39, count 0 2006.231.08:06:01.24#ibcon#about to read 5, iclass 39, count 0 2006.231.08:06:01.24#ibcon#read 5, iclass 39, count 0 2006.231.08:06:01.24#ibcon#about to read 6, iclass 39, count 0 2006.231.08:06:01.24#ibcon#read 6, iclass 39, count 0 2006.231.08:06:01.24#ibcon#end of sib2, iclass 39, count 0 2006.231.08:06:01.24#ibcon#*after write, iclass 39, count 0 2006.231.08:06:01.24#ibcon#*before return 0, iclass 39, count 0 2006.231.08:06:01.24#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:06:01.24#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:06:01.24#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:06:01.24#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:06:01.24$vc4f8/vblo=3,656.99 2006.231.08:06:01.24#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.08:06:01.24#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.08:06:01.24#ibcon#ireg 17 cls_cnt 0 2006.231.08:06:01.24#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:06:01.24#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:06:01.24#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:06:01.24#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:06:01.24#ibcon#first serial, iclass 3, count 0 2006.231.08:06:01.24#ibcon#enter sib2, iclass 3, count 0 2006.231.08:06:01.24#ibcon#flushed, iclass 3, count 0 2006.231.08:06:01.24#ibcon#about to write, iclass 3, count 0 2006.231.08:06:01.24#ibcon#wrote, iclass 3, count 0 2006.231.08:06:01.24#ibcon#about to read 3, iclass 3, count 0 2006.231.08:06:01.26#ibcon#read 3, iclass 3, count 0 2006.231.08:06:01.26#ibcon#about to read 4, iclass 3, count 0 2006.231.08:06:01.26#ibcon#read 4, iclass 3, count 0 2006.231.08:06:01.26#ibcon#about to read 5, iclass 3, count 0 2006.231.08:06:01.26#ibcon#read 5, iclass 3, count 0 2006.231.08:06:01.26#ibcon#about to read 6, iclass 3, count 0 2006.231.08:06:01.26#ibcon#read 6, iclass 3, count 0 2006.231.08:06:01.26#ibcon#end of sib2, iclass 3, count 0 2006.231.08:06:01.26#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:06:01.26#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:06:01.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:06:01.26#ibcon#*before write, iclass 3, count 0 2006.231.08:06:01.26#ibcon#enter sib2, iclass 3, count 0 2006.231.08:06:01.26#ibcon#flushed, iclass 3, count 0 2006.231.08:06:01.26#ibcon#about to write, iclass 3, count 0 2006.231.08:06:01.26#ibcon#wrote, iclass 3, count 0 2006.231.08:06:01.26#ibcon#about to read 3, iclass 3, count 0 2006.231.08:06:01.30#ibcon#read 3, iclass 3, count 0 2006.231.08:06:01.30#ibcon#about to read 4, iclass 3, count 0 2006.231.08:06:01.30#ibcon#read 4, iclass 3, count 0 2006.231.08:06:01.30#ibcon#about to read 5, iclass 3, count 0 2006.231.08:06:01.30#ibcon#read 5, iclass 3, count 0 2006.231.08:06:01.30#ibcon#about to read 6, iclass 3, count 0 2006.231.08:06:01.30#ibcon#read 6, iclass 3, count 0 2006.231.08:06:01.30#ibcon#end of sib2, iclass 3, count 0 2006.231.08:06:01.30#ibcon#*after write, iclass 3, count 0 2006.231.08:06:01.30#ibcon#*before return 0, iclass 3, count 0 2006.231.08:06:01.30#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:06:01.30#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:06:01.30#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:06:01.30#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:06:01.30$vc4f8/vb=3,4 2006.231.08:06:01.30#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.08:06:01.30#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.08:06:01.30#ibcon#ireg 11 cls_cnt 2 2006.231.08:06:01.30#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:06:01.36#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:06:01.36#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:06:01.36#ibcon#enter wrdev, iclass 5, count 2 2006.231.08:06:01.36#ibcon#first serial, iclass 5, count 2 2006.231.08:06:01.36#ibcon#enter sib2, iclass 5, count 2 2006.231.08:06:01.36#ibcon#flushed, iclass 5, count 2 2006.231.08:06:01.36#ibcon#about to write, iclass 5, count 2 2006.231.08:06:01.36#ibcon#wrote, iclass 5, count 2 2006.231.08:06:01.36#ibcon#about to read 3, iclass 5, count 2 2006.231.08:06:01.38#ibcon#read 3, iclass 5, count 2 2006.231.08:06:01.38#ibcon#about to read 4, iclass 5, count 2 2006.231.08:06:01.38#ibcon#read 4, iclass 5, count 2 2006.231.08:06:01.38#ibcon#about to read 5, iclass 5, count 2 2006.231.08:06:01.38#ibcon#read 5, iclass 5, count 2 2006.231.08:06:01.38#ibcon#about to read 6, iclass 5, count 2 2006.231.08:06:01.38#ibcon#read 6, iclass 5, count 2 2006.231.08:06:01.38#ibcon#end of sib2, iclass 5, count 2 2006.231.08:06:01.38#ibcon#*mode == 0, iclass 5, count 2 2006.231.08:06:01.38#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.08:06:01.38#ibcon#[27=AT03-04\r\n] 2006.231.08:06:01.38#ibcon#*before write, iclass 5, count 2 2006.231.08:06:01.38#ibcon#enter sib2, iclass 5, count 2 2006.231.08:06:01.38#ibcon#flushed, iclass 5, count 2 2006.231.08:06:01.38#ibcon#about to write, iclass 5, count 2 2006.231.08:06:01.38#ibcon#wrote, iclass 5, count 2 2006.231.08:06:01.38#ibcon#about to read 3, iclass 5, count 2 2006.231.08:06:01.41#ibcon#read 3, iclass 5, count 2 2006.231.08:06:01.41#ibcon#about to read 4, iclass 5, count 2 2006.231.08:06:01.41#ibcon#read 4, iclass 5, count 2 2006.231.08:06:01.41#ibcon#about to read 5, iclass 5, count 2 2006.231.08:06:01.41#ibcon#read 5, iclass 5, count 2 2006.231.08:06:01.41#ibcon#about to read 6, iclass 5, count 2 2006.231.08:06:01.41#ibcon#read 6, iclass 5, count 2 2006.231.08:06:01.41#ibcon#end of sib2, iclass 5, count 2 2006.231.08:06:01.41#ibcon#*after write, iclass 5, count 2 2006.231.08:06:01.41#ibcon#*before return 0, iclass 5, count 2 2006.231.08:06:01.41#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:06:01.41#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:06:01.41#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.08:06:01.41#ibcon#ireg 7 cls_cnt 0 2006.231.08:06:01.41#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:06:01.53#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:06:01.53#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:06:01.53#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:06:01.53#ibcon#first serial, iclass 5, count 0 2006.231.08:06:01.53#ibcon#enter sib2, iclass 5, count 0 2006.231.08:06:01.53#ibcon#flushed, iclass 5, count 0 2006.231.08:06:01.53#ibcon#about to write, iclass 5, count 0 2006.231.08:06:01.53#ibcon#wrote, iclass 5, count 0 2006.231.08:06:01.53#ibcon#about to read 3, iclass 5, count 0 2006.231.08:06:01.55#ibcon#read 3, iclass 5, count 0 2006.231.08:06:01.55#ibcon#about to read 4, iclass 5, count 0 2006.231.08:06:01.55#ibcon#read 4, iclass 5, count 0 2006.231.08:06:01.55#ibcon#about to read 5, iclass 5, count 0 2006.231.08:06:01.55#ibcon#read 5, iclass 5, count 0 2006.231.08:06:01.55#ibcon#about to read 6, iclass 5, count 0 2006.231.08:06:01.55#ibcon#read 6, iclass 5, count 0 2006.231.08:06:01.55#ibcon#end of sib2, iclass 5, count 0 2006.231.08:06:01.55#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:06:01.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:06:01.55#ibcon#[27=USB\r\n] 2006.231.08:06:01.55#ibcon#*before write, iclass 5, count 0 2006.231.08:06:01.55#ibcon#enter sib2, iclass 5, count 0 2006.231.08:06:01.55#ibcon#flushed, iclass 5, count 0 2006.231.08:06:01.55#ibcon#about to write, iclass 5, count 0 2006.231.08:06:01.55#ibcon#wrote, iclass 5, count 0 2006.231.08:06:01.55#ibcon#about to read 3, iclass 5, count 0 2006.231.08:06:01.58#ibcon#read 3, iclass 5, count 0 2006.231.08:06:01.58#ibcon#about to read 4, iclass 5, count 0 2006.231.08:06:01.58#ibcon#read 4, iclass 5, count 0 2006.231.08:06:01.58#ibcon#about to read 5, iclass 5, count 0 2006.231.08:06:01.58#ibcon#read 5, iclass 5, count 0 2006.231.08:06:01.58#ibcon#about to read 6, iclass 5, count 0 2006.231.08:06:01.58#ibcon#read 6, iclass 5, count 0 2006.231.08:06:01.58#ibcon#end of sib2, iclass 5, count 0 2006.231.08:06:01.58#ibcon#*after write, iclass 5, count 0 2006.231.08:06:01.58#ibcon#*before return 0, iclass 5, count 0 2006.231.08:06:01.58#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:06:01.58#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:06:01.58#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:06:01.58#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:06:01.58$vc4f8/vblo=4,712.99 2006.231.08:06:01.58#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.08:06:01.58#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.08:06:01.58#ibcon#ireg 17 cls_cnt 0 2006.231.08:06:01.58#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:06:01.58#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:06:01.58#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:06:01.58#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:06:01.58#ibcon#first serial, iclass 7, count 0 2006.231.08:06:01.58#ibcon#enter sib2, iclass 7, count 0 2006.231.08:06:01.58#ibcon#flushed, iclass 7, count 0 2006.231.08:06:01.58#ibcon#about to write, iclass 7, count 0 2006.231.08:06:01.58#ibcon#wrote, iclass 7, count 0 2006.231.08:06:01.58#ibcon#about to read 3, iclass 7, count 0 2006.231.08:06:01.60#ibcon#read 3, iclass 7, count 0 2006.231.08:06:01.60#ibcon#about to read 4, iclass 7, count 0 2006.231.08:06:01.60#ibcon#read 4, iclass 7, count 0 2006.231.08:06:01.60#ibcon#about to read 5, iclass 7, count 0 2006.231.08:06:01.60#ibcon#read 5, iclass 7, count 0 2006.231.08:06:01.60#ibcon#about to read 6, iclass 7, count 0 2006.231.08:06:01.60#ibcon#read 6, iclass 7, count 0 2006.231.08:06:01.60#ibcon#end of sib2, iclass 7, count 0 2006.231.08:06:01.60#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:06:01.60#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:06:01.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:06:01.60#ibcon#*before write, iclass 7, count 0 2006.231.08:06:01.60#ibcon#enter sib2, iclass 7, count 0 2006.231.08:06:01.60#ibcon#flushed, iclass 7, count 0 2006.231.08:06:01.60#ibcon#about to write, iclass 7, count 0 2006.231.08:06:01.60#ibcon#wrote, iclass 7, count 0 2006.231.08:06:01.60#ibcon#about to read 3, iclass 7, count 0 2006.231.08:06:01.64#ibcon#read 3, iclass 7, count 0 2006.231.08:06:01.64#ibcon#about to read 4, iclass 7, count 0 2006.231.08:06:01.64#ibcon#read 4, iclass 7, count 0 2006.231.08:06:01.64#ibcon#about to read 5, iclass 7, count 0 2006.231.08:06:01.64#ibcon#read 5, iclass 7, count 0 2006.231.08:06:01.64#ibcon#about to read 6, iclass 7, count 0 2006.231.08:06:01.64#ibcon#read 6, iclass 7, count 0 2006.231.08:06:01.64#ibcon#end of sib2, iclass 7, count 0 2006.231.08:06:01.64#ibcon#*after write, iclass 7, count 0 2006.231.08:06:01.64#ibcon#*before return 0, iclass 7, count 0 2006.231.08:06:01.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:06:01.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:06:01.64#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:06:01.64#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:06:01.64$vc4f8/vb=4,4 2006.231.08:06:01.64#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.08:06:01.64#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.08:06:01.64#ibcon#ireg 11 cls_cnt 2 2006.231.08:06:01.64#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:06:01.70#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:06:01.70#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:06:01.70#ibcon#enter wrdev, iclass 11, count 2 2006.231.08:06:01.70#ibcon#first serial, iclass 11, count 2 2006.231.08:06:01.70#ibcon#enter sib2, iclass 11, count 2 2006.231.08:06:01.70#ibcon#flushed, iclass 11, count 2 2006.231.08:06:01.70#ibcon#about to write, iclass 11, count 2 2006.231.08:06:01.70#ibcon#wrote, iclass 11, count 2 2006.231.08:06:01.70#ibcon#about to read 3, iclass 11, count 2 2006.231.08:06:01.72#ibcon#read 3, iclass 11, count 2 2006.231.08:06:01.72#ibcon#about to read 4, iclass 11, count 2 2006.231.08:06:01.72#ibcon#read 4, iclass 11, count 2 2006.231.08:06:01.72#ibcon#about to read 5, iclass 11, count 2 2006.231.08:06:01.72#ibcon#read 5, iclass 11, count 2 2006.231.08:06:01.72#ibcon#about to read 6, iclass 11, count 2 2006.231.08:06:01.72#ibcon#read 6, iclass 11, count 2 2006.231.08:06:01.72#ibcon#end of sib2, iclass 11, count 2 2006.231.08:06:01.72#ibcon#*mode == 0, iclass 11, count 2 2006.231.08:06:01.72#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.08:06:01.72#ibcon#[27=AT04-04\r\n] 2006.231.08:06:01.72#ibcon#*before write, iclass 11, count 2 2006.231.08:06:01.72#ibcon#enter sib2, iclass 11, count 2 2006.231.08:06:01.72#ibcon#flushed, iclass 11, count 2 2006.231.08:06:01.72#ibcon#about to write, iclass 11, count 2 2006.231.08:06:01.72#ibcon#wrote, iclass 11, count 2 2006.231.08:06:01.72#ibcon#about to read 3, iclass 11, count 2 2006.231.08:06:01.75#ibcon#read 3, iclass 11, count 2 2006.231.08:06:01.75#ibcon#about to read 4, iclass 11, count 2 2006.231.08:06:01.75#ibcon#read 4, iclass 11, count 2 2006.231.08:06:01.75#ibcon#about to read 5, iclass 11, count 2 2006.231.08:06:01.75#ibcon#read 5, iclass 11, count 2 2006.231.08:06:01.75#ibcon#about to read 6, iclass 11, count 2 2006.231.08:06:01.75#ibcon#read 6, iclass 11, count 2 2006.231.08:06:01.75#ibcon#end of sib2, iclass 11, count 2 2006.231.08:06:01.75#ibcon#*after write, iclass 11, count 2 2006.231.08:06:01.75#ibcon#*before return 0, iclass 11, count 2 2006.231.08:06:01.75#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:06:01.75#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:06:01.75#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.08:06:01.75#ibcon#ireg 7 cls_cnt 0 2006.231.08:06:01.75#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:06:01.87#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:06:01.87#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:06:01.87#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:06:01.87#ibcon#first serial, iclass 11, count 0 2006.231.08:06:01.87#ibcon#enter sib2, iclass 11, count 0 2006.231.08:06:01.87#ibcon#flushed, iclass 11, count 0 2006.231.08:06:01.87#ibcon#about to write, iclass 11, count 0 2006.231.08:06:01.87#ibcon#wrote, iclass 11, count 0 2006.231.08:06:01.87#ibcon#about to read 3, iclass 11, count 0 2006.231.08:06:01.89#ibcon#read 3, iclass 11, count 0 2006.231.08:06:01.89#ibcon#about to read 4, iclass 11, count 0 2006.231.08:06:01.89#ibcon#read 4, iclass 11, count 0 2006.231.08:06:01.89#ibcon#about to read 5, iclass 11, count 0 2006.231.08:06:01.89#ibcon#read 5, iclass 11, count 0 2006.231.08:06:01.89#ibcon#about to read 6, iclass 11, count 0 2006.231.08:06:01.89#ibcon#read 6, iclass 11, count 0 2006.231.08:06:01.89#ibcon#end of sib2, iclass 11, count 0 2006.231.08:06:01.89#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:06:01.89#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:06:01.89#ibcon#[27=USB\r\n] 2006.231.08:06:01.89#ibcon#*before write, iclass 11, count 0 2006.231.08:06:01.89#ibcon#enter sib2, iclass 11, count 0 2006.231.08:06:01.89#ibcon#flushed, iclass 11, count 0 2006.231.08:06:01.89#ibcon#about to write, iclass 11, count 0 2006.231.08:06:01.89#ibcon#wrote, iclass 11, count 0 2006.231.08:06:01.89#ibcon#about to read 3, iclass 11, count 0 2006.231.08:06:01.92#ibcon#read 3, iclass 11, count 0 2006.231.08:06:01.92#ibcon#about to read 4, iclass 11, count 0 2006.231.08:06:01.92#ibcon#read 4, iclass 11, count 0 2006.231.08:06:01.92#ibcon#about to read 5, iclass 11, count 0 2006.231.08:06:01.92#ibcon#read 5, iclass 11, count 0 2006.231.08:06:01.92#ibcon#about to read 6, iclass 11, count 0 2006.231.08:06:01.92#ibcon#read 6, iclass 11, count 0 2006.231.08:06:01.92#ibcon#end of sib2, iclass 11, count 0 2006.231.08:06:01.92#ibcon#*after write, iclass 11, count 0 2006.231.08:06:01.92#ibcon#*before return 0, iclass 11, count 0 2006.231.08:06:01.92#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:06:01.92#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:06:01.92#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:06:01.92#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:06:01.92$vc4f8/vblo=5,744.99 2006.231.08:06:01.92#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.08:06:01.92#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.08:06:01.92#ibcon#ireg 17 cls_cnt 0 2006.231.08:06:01.92#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:06:01.92#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:06:01.92#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:06:01.92#ibcon#enter wrdev, iclass 13, count 0 2006.231.08:06:01.92#ibcon#first serial, iclass 13, count 0 2006.231.08:06:01.92#ibcon#enter sib2, iclass 13, count 0 2006.231.08:06:01.92#ibcon#flushed, iclass 13, count 0 2006.231.08:06:01.92#ibcon#about to write, iclass 13, count 0 2006.231.08:06:01.92#ibcon#wrote, iclass 13, count 0 2006.231.08:06:01.92#ibcon#about to read 3, iclass 13, count 0 2006.231.08:06:01.94#ibcon#read 3, iclass 13, count 0 2006.231.08:06:01.94#ibcon#about to read 4, iclass 13, count 0 2006.231.08:06:01.94#ibcon#read 4, iclass 13, count 0 2006.231.08:06:01.94#ibcon#about to read 5, iclass 13, count 0 2006.231.08:06:01.94#ibcon#read 5, iclass 13, count 0 2006.231.08:06:01.94#ibcon#about to read 6, iclass 13, count 0 2006.231.08:06:01.94#ibcon#read 6, iclass 13, count 0 2006.231.08:06:01.94#ibcon#end of sib2, iclass 13, count 0 2006.231.08:06:01.94#ibcon#*mode == 0, iclass 13, count 0 2006.231.08:06:01.94#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.08:06:01.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:06:01.94#ibcon#*before write, iclass 13, count 0 2006.231.08:06:01.94#ibcon#enter sib2, iclass 13, count 0 2006.231.08:06:01.94#ibcon#flushed, iclass 13, count 0 2006.231.08:06:01.94#ibcon#about to write, iclass 13, count 0 2006.231.08:06:01.94#ibcon#wrote, iclass 13, count 0 2006.231.08:06:01.94#ibcon#about to read 3, iclass 13, count 0 2006.231.08:06:01.98#ibcon#read 3, iclass 13, count 0 2006.231.08:06:01.98#ibcon#about to read 4, iclass 13, count 0 2006.231.08:06:01.98#ibcon#read 4, iclass 13, count 0 2006.231.08:06:01.98#ibcon#about to read 5, iclass 13, count 0 2006.231.08:06:01.98#ibcon#read 5, iclass 13, count 0 2006.231.08:06:01.98#ibcon#about to read 6, iclass 13, count 0 2006.231.08:06:01.98#ibcon#read 6, iclass 13, count 0 2006.231.08:06:01.98#ibcon#end of sib2, iclass 13, count 0 2006.231.08:06:01.98#ibcon#*after write, iclass 13, count 0 2006.231.08:06:01.98#ibcon#*before return 0, iclass 13, count 0 2006.231.08:06:01.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:06:01.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:06:01.98#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.08:06:01.98#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.08:06:01.98$vc4f8/vb=5,3 2006.231.08:06:01.98#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.08:06:01.98#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.08:06:01.98#ibcon#ireg 11 cls_cnt 2 2006.231.08:06:01.98#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:06:02.04#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:06:02.04#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:06:02.04#ibcon#enter wrdev, iclass 15, count 2 2006.231.08:06:02.04#ibcon#first serial, iclass 15, count 2 2006.231.08:06:02.04#ibcon#enter sib2, iclass 15, count 2 2006.231.08:06:02.04#ibcon#flushed, iclass 15, count 2 2006.231.08:06:02.04#ibcon#about to write, iclass 15, count 2 2006.231.08:06:02.04#ibcon#wrote, iclass 15, count 2 2006.231.08:06:02.04#ibcon#about to read 3, iclass 15, count 2 2006.231.08:06:02.06#ibcon#read 3, iclass 15, count 2 2006.231.08:06:02.06#ibcon#about to read 4, iclass 15, count 2 2006.231.08:06:02.06#ibcon#read 4, iclass 15, count 2 2006.231.08:06:02.06#ibcon#about to read 5, iclass 15, count 2 2006.231.08:06:02.06#ibcon#read 5, iclass 15, count 2 2006.231.08:06:02.06#ibcon#about to read 6, iclass 15, count 2 2006.231.08:06:02.06#ibcon#read 6, iclass 15, count 2 2006.231.08:06:02.06#ibcon#end of sib2, iclass 15, count 2 2006.231.08:06:02.06#ibcon#*mode == 0, iclass 15, count 2 2006.231.08:06:02.06#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.08:06:02.06#ibcon#[27=AT05-03\r\n] 2006.231.08:06:02.06#ibcon#*before write, iclass 15, count 2 2006.231.08:06:02.06#ibcon#enter sib2, iclass 15, count 2 2006.231.08:06:02.06#ibcon#flushed, iclass 15, count 2 2006.231.08:06:02.06#ibcon#about to write, iclass 15, count 2 2006.231.08:06:02.06#ibcon#wrote, iclass 15, count 2 2006.231.08:06:02.06#ibcon#about to read 3, iclass 15, count 2 2006.231.08:06:02.09#ibcon#read 3, iclass 15, count 2 2006.231.08:06:02.09#ibcon#about to read 4, iclass 15, count 2 2006.231.08:06:02.09#ibcon#read 4, iclass 15, count 2 2006.231.08:06:02.09#ibcon#about to read 5, iclass 15, count 2 2006.231.08:06:02.09#ibcon#read 5, iclass 15, count 2 2006.231.08:06:02.09#ibcon#about to read 6, iclass 15, count 2 2006.231.08:06:02.09#ibcon#read 6, iclass 15, count 2 2006.231.08:06:02.09#ibcon#end of sib2, iclass 15, count 2 2006.231.08:06:02.09#ibcon#*after write, iclass 15, count 2 2006.231.08:06:02.09#ibcon#*before return 0, iclass 15, count 2 2006.231.08:06:02.09#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:06:02.09#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:06:02.09#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.08:06:02.09#ibcon#ireg 7 cls_cnt 0 2006.231.08:06:02.09#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:06:02.21#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:06:02.21#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:06:02.21#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:06:02.21#ibcon#first serial, iclass 15, count 0 2006.231.08:06:02.21#ibcon#enter sib2, iclass 15, count 0 2006.231.08:06:02.21#ibcon#flushed, iclass 15, count 0 2006.231.08:06:02.21#ibcon#about to write, iclass 15, count 0 2006.231.08:06:02.21#ibcon#wrote, iclass 15, count 0 2006.231.08:06:02.21#ibcon#about to read 3, iclass 15, count 0 2006.231.08:06:02.23#ibcon#read 3, iclass 15, count 0 2006.231.08:06:02.23#ibcon#about to read 4, iclass 15, count 0 2006.231.08:06:02.23#ibcon#read 4, iclass 15, count 0 2006.231.08:06:02.23#ibcon#about to read 5, iclass 15, count 0 2006.231.08:06:02.23#ibcon#read 5, iclass 15, count 0 2006.231.08:06:02.23#ibcon#about to read 6, iclass 15, count 0 2006.231.08:06:02.23#ibcon#read 6, iclass 15, count 0 2006.231.08:06:02.23#ibcon#end of sib2, iclass 15, count 0 2006.231.08:06:02.23#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:06:02.23#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:06:02.23#ibcon#[27=USB\r\n] 2006.231.08:06:02.23#ibcon#*before write, iclass 15, count 0 2006.231.08:06:02.23#ibcon#enter sib2, iclass 15, count 0 2006.231.08:06:02.23#ibcon#flushed, iclass 15, count 0 2006.231.08:06:02.23#ibcon#about to write, iclass 15, count 0 2006.231.08:06:02.23#ibcon#wrote, iclass 15, count 0 2006.231.08:06:02.23#ibcon#about to read 3, iclass 15, count 0 2006.231.08:06:02.26#ibcon#read 3, iclass 15, count 0 2006.231.08:06:02.26#ibcon#about to read 4, iclass 15, count 0 2006.231.08:06:02.26#ibcon#read 4, iclass 15, count 0 2006.231.08:06:02.26#ibcon#about to read 5, iclass 15, count 0 2006.231.08:06:02.26#ibcon#read 5, iclass 15, count 0 2006.231.08:06:02.26#ibcon#about to read 6, iclass 15, count 0 2006.231.08:06:02.26#ibcon#read 6, iclass 15, count 0 2006.231.08:06:02.26#ibcon#end of sib2, iclass 15, count 0 2006.231.08:06:02.26#ibcon#*after write, iclass 15, count 0 2006.231.08:06:02.26#ibcon#*before return 0, iclass 15, count 0 2006.231.08:06:02.26#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:06:02.26#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:06:02.26#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:06:02.26#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:06:02.26$vc4f8/vblo=6,752.99 2006.231.08:06:02.26#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.08:06:02.26#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.08:06:02.26#ibcon#ireg 17 cls_cnt 0 2006.231.08:06:02.26#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:06:02.26#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:06:02.26#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:06:02.26#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:06:02.26#ibcon#first serial, iclass 17, count 0 2006.231.08:06:02.26#ibcon#enter sib2, iclass 17, count 0 2006.231.08:06:02.26#ibcon#flushed, iclass 17, count 0 2006.231.08:06:02.26#ibcon#about to write, iclass 17, count 0 2006.231.08:06:02.26#ibcon#wrote, iclass 17, count 0 2006.231.08:06:02.26#ibcon#about to read 3, iclass 17, count 0 2006.231.08:06:02.28#ibcon#read 3, iclass 17, count 0 2006.231.08:06:02.28#ibcon#about to read 4, iclass 17, count 0 2006.231.08:06:02.28#ibcon#read 4, iclass 17, count 0 2006.231.08:06:02.28#ibcon#about to read 5, iclass 17, count 0 2006.231.08:06:02.28#ibcon#read 5, iclass 17, count 0 2006.231.08:06:02.28#ibcon#about to read 6, iclass 17, count 0 2006.231.08:06:02.28#ibcon#read 6, iclass 17, count 0 2006.231.08:06:02.28#ibcon#end of sib2, iclass 17, count 0 2006.231.08:06:02.28#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:06:02.28#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:06:02.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:06:02.28#ibcon#*before write, iclass 17, count 0 2006.231.08:06:02.28#ibcon#enter sib2, iclass 17, count 0 2006.231.08:06:02.28#ibcon#flushed, iclass 17, count 0 2006.231.08:06:02.28#ibcon#about to write, iclass 17, count 0 2006.231.08:06:02.28#ibcon#wrote, iclass 17, count 0 2006.231.08:06:02.28#ibcon#about to read 3, iclass 17, count 0 2006.231.08:06:02.32#ibcon#read 3, iclass 17, count 0 2006.231.08:06:02.32#ibcon#about to read 4, iclass 17, count 0 2006.231.08:06:02.32#ibcon#read 4, iclass 17, count 0 2006.231.08:06:02.32#ibcon#about to read 5, iclass 17, count 0 2006.231.08:06:02.32#ibcon#read 5, iclass 17, count 0 2006.231.08:06:02.32#ibcon#about to read 6, iclass 17, count 0 2006.231.08:06:02.32#ibcon#read 6, iclass 17, count 0 2006.231.08:06:02.32#ibcon#end of sib2, iclass 17, count 0 2006.231.08:06:02.32#ibcon#*after write, iclass 17, count 0 2006.231.08:06:02.32#ibcon#*before return 0, iclass 17, count 0 2006.231.08:06:02.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:06:02.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:06:02.32#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:06:02.32#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:06:02.32$vc4f8/vb=6,4 2006.231.08:06:02.32#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.231.08:06:02.32#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.231.08:06:02.32#ibcon#ireg 11 cls_cnt 2 2006.231.08:06:02.32#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:06:02.38#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:06:02.38#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:06:02.38#ibcon#enter wrdev, iclass 19, count 2 2006.231.08:06:02.38#ibcon#first serial, iclass 19, count 2 2006.231.08:06:02.38#ibcon#enter sib2, iclass 19, count 2 2006.231.08:06:02.38#ibcon#flushed, iclass 19, count 2 2006.231.08:06:02.38#ibcon#about to write, iclass 19, count 2 2006.231.08:06:02.38#ibcon#wrote, iclass 19, count 2 2006.231.08:06:02.38#ibcon#about to read 3, iclass 19, count 2 2006.231.08:06:02.40#ibcon#read 3, iclass 19, count 2 2006.231.08:06:02.40#ibcon#about to read 4, iclass 19, count 2 2006.231.08:06:02.40#ibcon#read 4, iclass 19, count 2 2006.231.08:06:02.40#ibcon#about to read 5, iclass 19, count 2 2006.231.08:06:02.40#ibcon#read 5, iclass 19, count 2 2006.231.08:06:02.40#ibcon#about to read 6, iclass 19, count 2 2006.231.08:06:02.40#ibcon#read 6, iclass 19, count 2 2006.231.08:06:02.40#ibcon#end of sib2, iclass 19, count 2 2006.231.08:06:02.40#ibcon#*mode == 0, iclass 19, count 2 2006.231.08:06:02.40#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.231.08:06:02.40#ibcon#[27=AT06-04\r\n] 2006.231.08:06:02.40#ibcon#*before write, iclass 19, count 2 2006.231.08:06:02.40#ibcon#enter sib2, iclass 19, count 2 2006.231.08:06:02.40#ibcon#flushed, iclass 19, count 2 2006.231.08:06:02.40#ibcon#about to write, iclass 19, count 2 2006.231.08:06:02.40#ibcon#wrote, iclass 19, count 2 2006.231.08:06:02.40#ibcon#about to read 3, iclass 19, count 2 2006.231.08:06:02.43#ibcon#read 3, iclass 19, count 2 2006.231.08:06:02.43#ibcon#about to read 4, iclass 19, count 2 2006.231.08:06:02.43#ibcon#read 4, iclass 19, count 2 2006.231.08:06:02.43#ibcon#about to read 5, iclass 19, count 2 2006.231.08:06:02.43#ibcon#read 5, iclass 19, count 2 2006.231.08:06:02.43#ibcon#about to read 6, iclass 19, count 2 2006.231.08:06:02.43#ibcon#read 6, iclass 19, count 2 2006.231.08:06:02.43#ibcon#end of sib2, iclass 19, count 2 2006.231.08:06:02.43#ibcon#*after write, iclass 19, count 2 2006.231.08:06:02.43#ibcon#*before return 0, iclass 19, count 2 2006.231.08:06:02.43#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:06:02.43#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:06:02.43#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.231.08:06:02.43#ibcon#ireg 7 cls_cnt 0 2006.231.08:06:02.43#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:06:02.55#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:06:02.55#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:06:02.55#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:06:02.55#ibcon#first serial, iclass 19, count 0 2006.231.08:06:02.55#ibcon#enter sib2, iclass 19, count 0 2006.231.08:06:02.55#ibcon#flushed, iclass 19, count 0 2006.231.08:06:02.55#ibcon#about to write, iclass 19, count 0 2006.231.08:06:02.55#ibcon#wrote, iclass 19, count 0 2006.231.08:06:02.55#ibcon#about to read 3, iclass 19, count 0 2006.231.08:06:02.57#ibcon#read 3, iclass 19, count 0 2006.231.08:06:02.57#ibcon#about to read 4, iclass 19, count 0 2006.231.08:06:02.57#ibcon#read 4, iclass 19, count 0 2006.231.08:06:02.57#ibcon#about to read 5, iclass 19, count 0 2006.231.08:06:02.57#ibcon#read 5, iclass 19, count 0 2006.231.08:06:02.57#ibcon#about to read 6, iclass 19, count 0 2006.231.08:06:02.57#ibcon#read 6, iclass 19, count 0 2006.231.08:06:02.57#ibcon#end of sib2, iclass 19, count 0 2006.231.08:06:02.57#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:06:02.57#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:06:02.57#ibcon#[27=USB\r\n] 2006.231.08:06:02.57#ibcon#*before write, iclass 19, count 0 2006.231.08:06:02.57#ibcon#enter sib2, iclass 19, count 0 2006.231.08:06:02.57#ibcon#flushed, iclass 19, count 0 2006.231.08:06:02.57#ibcon#about to write, iclass 19, count 0 2006.231.08:06:02.57#ibcon#wrote, iclass 19, count 0 2006.231.08:06:02.57#ibcon#about to read 3, iclass 19, count 0 2006.231.08:06:02.60#ibcon#read 3, iclass 19, count 0 2006.231.08:06:02.60#ibcon#about to read 4, iclass 19, count 0 2006.231.08:06:02.60#ibcon#read 4, iclass 19, count 0 2006.231.08:06:02.60#ibcon#about to read 5, iclass 19, count 0 2006.231.08:06:02.60#ibcon#read 5, iclass 19, count 0 2006.231.08:06:02.60#ibcon#about to read 6, iclass 19, count 0 2006.231.08:06:02.60#ibcon#read 6, iclass 19, count 0 2006.231.08:06:02.60#ibcon#end of sib2, iclass 19, count 0 2006.231.08:06:02.60#ibcon#*after write, iclass 19, count 0 2006.231.08:06:02.60#ibcon#*before return 0, iclass 19, count 0 2006.231.08:06:02.60#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:06:02.60#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:06:02.60#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:06:02.60#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:06:02.60$vc4f8/vabw=wide 2006.231.08:06:02.60#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.08:06:02.60#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.08:06:02.60#ibcon#ireg 8 cls_cnt 0 2006.231.08:06:02.60#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:06:02.60#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:06:02.60#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:06:02.60#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:06:02.60#ibcon#first serial, iclass 21, count 0 2006.231.08:06:02.60#ibcon#enter sib2, iclass 21, count 0 2006.231.08:06:02.60#ibcon#flushed, iclass 21, count 0 2006.231.08:06:02.60#ibcon#about to write, iclass 21, count 0 2006.231.08:06:02.60#ibcon#wrote, iclass 21, count 0 2006.231.08:06:02.60#ibcon#about to read 3, iclass 21, count 0 2006.231.08:06:02.62#ibcon#read 3, iclass 21, count 0 2006.231.08:06:02.62#ibcon#about to read 4, iclass 21, count 0 2006.231.08:06:02.62#ibcon#read 4, iclass 21, count 0 2006.231.08:06:02.62#ibcon#about to read 5, iclass 21, count 0 2006.231.08:06:02.62#ibcon#read 5, iclass 21, count 0 2006.231.08:06:02.62#ibcon#about to read 6, iclass 21, count 0 2006.231.08:06:02.62#ibcon#read 6, iclass 21, count 0 2006.231.08:06:02.62#ibcon#end of sib2, iclass 21, count 0 2006.231.08:06:02.62#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:06:02.62#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:06:02.62#ibcon#[25=BW32\r\n] 2006.231.08:06:02.62#ibcon#*before write, iclass 21, count 0 2006.231.08:06:02.62#ibcon#enter sib2, iclass 21, count 0 2006.231.08:06:02.62#ibcon#flushed, iclass 21, count 0 2006.231.08:06:02.62#ibcon#about to write, iclass 21, count 0 2006.231.08:06:02.62#ibcon#wrote, iclass 21, count 0 2006.231.08:06:02.62#ibcon#about to read 3, iclass 21, count 0 2006.231.08:06:02.65#ibcon#read 3, iclass 21, count 0 2006.231.08:06:02.65#ibcon#about to read 4, iclass 21, count 0 2006.231.08:06:02.65#ibcon#read 4, iclass 21, count 0 2006.231.08:06:02.65#ibcon#about to read 5, iclass 21, count 0 2006.231.08:06:02.65#ibcon#read 5, iclass 21, count 0 2006.231.08:06:02.65#ibcon#about to read 6, iclass 21, count 0 2006.231.08:06:02.65#ibcon#read 6, iclass 21, count 0 2006.231.08:06:02.65#ibcon#end of sib2, iclass 21, count 0 2006.231.08:06:02.65#ibcon#*after write, iclass 21, count 0 2006.231.08:06:02.65#ibcon#*before return 0, iclass 21, count 0 2006.231.08:06:02.65#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:06:02.65#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:06:02.65#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:06:02.65#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:06:02.65$vc4f8/vbbw=wide 2006.231.08:06:02.65#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.231.08:06:02.65#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.231.08:06:02.65#ibcon#ireg 8 cls_cnt 0 2006.231.08:06:02.65#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:06:02.72#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:06:02.72#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:06:02.72#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:06:02.72#ibcon#first serial, iclass 23, count 0 2006.231.08:06:02.72#ibcon#enter sib2, iclass 23, count 0 2006.231.08:06:02.72#ibcon#flushed, iclass 23, count 0 2006.231.08:06:02.72#ibcon#about to write, iclass 23, count 0 2006.231.08:06:02.72#ibcon#wrote, iclass 23, count 0 2006.231.08:06:02.72#ibcon#about to read 3, iclass 23, count 0 2006.231.08:06:02.74#ibcon#read 3, iclass 23, count 0 2006.231.08:06:02.74#ibcon#about to read 4, iclass 23, count 0 2006.231.08:06:02.74#ibcon#read 4, iclass 23, count 0 2006.231.08:06:02.74#ibcon#about to read 5, iclass 23, count 0 2006.231.08:06:02.74#ibcon#read 5, iclass 23, count 0 2006.231.08:06:02.74#ibcon#about to read 6, iclass 23, count 0 2006.231.08:06:02.74#ibcon#read 6, iclass 23, count 0 2006.231.08:06:02.74#ibcon#end of sib2, iclass 23, count 0 2006.231.08:06:02.74#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:06:02.74#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:06:02.74#ibcon#[27=BW32\r\n] 2006.231.08:06:02.74#ibcon#*before write, iclass 23, count 0 2006.231.08:06:02.74#ibcon#enter sib2, iclass 23, count 0 2006.231.08:06:02.74#ibcon#flushed, iclass 23, count 0 2006.231.08:06:02.74#ibcon#about to write, iclass 23, count 0 2006.231.08:06:02.74#ibcon#wrote, iclass 23, count 0 2006.231.08:06:02.74#ibcon#about to read 3, iclass 23, count 0 2006.231.08:06:02.77#ibcon#read 3, iclass 23, count 0 2006.231.08:06:02.77#ibcon#about to read 4, iclass 23, count 0 2006.231.08:06:02.77#ibcon#read 4, iclass 23, count 0 2006.231.08:06:02.77#ibcon#about to read 5, iclass 23, count 0 2006.231.08:06:02.77#ibcon#read 5, iclass 23, count 0 2006.231.08:06:02.77#ibcon#about to read 6, iclass 23, count 0 2006.231.08:06:02.77#ibcon#read 6, iclass 23, count 0 2006.231.08:06:02.77#ibcon#end of sib2, iclass 23, count 0 2006.231.08:06:02.77#ibcon#*after write, iclass 23, count 0 2006.231.08:06:02.77#ibcon#*before return 0, iclass 23, count 0 2006.231.08:06:02.77#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:06:02.77#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:06:02.77#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:06:02.77#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:06:02.77$4f8m12a/ifd4f 2006.231.08:06:02.77$ifd4f/lo= 2006.231.08:06:02.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:06:02.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:06:02.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:06:02.78$ifd4f/patch= 2006.231.08:06:02.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:06:02.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:06:02.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:06:02.78$4f8m12a/"form=m,16.000,1:2 2006.231.08:06:02.78$4f8m12a/"tpicd 2006.231.08:06:02.78$4f8m12a/echo=off 2006.231.08:06:02.78$4f8m12a/xlog=off 2006.231.08:06:02.78:!2006.231.08:06:30 2006.231.08:06:14.14#trakl#Source acquired 2006.231.08:06:14.14#flagr#flagr/antenna,acquired 2006.231.08:06:30.01:preob 2006.231.08:06:31.14/onsource/TRACKING 2006.231.08:06:31.14:!2006.231.08:06:40 2006.231.08:06:40.00:data_valid=on 2006.231.08:06:40.00:midob 2006.231.08:06:40.14/onsource/TRACKING 2006.231.08:06:40.14/wx/30.50,1004.4,86 2006.231.08:06:40.21/cable/+6.3736E-03 2006.231.08:06:41.30/va/01,08,usb,yes,30,32 2006.231.08:06:41.30/va/02,07,usb,yes,30,32 2006.231.08:06:41.30/va/03,08,usb,yes,23,23 2006.231.08:06:41.30/va/04,07,usb,yes,32,34 2006.231.08:06:41.30/va/05,07,usb,yes,34,36 2006.231.08:06:41.30/va/06,06,usb,yes,33,33 2006.231.08:06:41.30/va/07,06,usb,yes,34,34 2006.231.08:06:41.30/va/08,06,usb,yes,36,36 2006.231.08:06:41.53/valo/01,532.99,yes,locked 2006.231.08:06:41.53/valo/02,572.99,yes,locked 2006.231.08:06:41.53/valo/03,672.99,yes,locked 2006.231.08:06:41.53/valo/04,832.99,yes,locked 2006.231.08:06:41.53/valo/05,652.99,yes,locked 2006.231.08:06:41.53/valo/06,772.99,yes,locked 2006.231.08:06:41.53/valo/07,832.99,yes,locked 2006.231.08:06:41.53/valo/08,852.99,yes,locked 2006.231.08:06:42.62/vb/01,04,usb,yes,31,30 2006.231.08:06:42.62/vb/02,04,usb,yes,33,34 2006.231.08:06:42.62/vb/03,04,usb,yes,29,33 2006.231.08:06:42.62/vb/04,04,usb,yes,30,30 2006.231.08:06:42.62/vb/05,03,usb,yes,35,40 2006.231.08:06:42.62/vb/06,04,usb,yes,29,32 2006.231.08:06:42.62/vb/07,04,usb,yes,31,31 2006.231.08:06:42.62/vb/08,04,usb,yes,29,32 2006.231.08:06:42.86/vblo/01,632.99,yes,locked 2006.231.08:06:42.86/vblo/02,640.99,yes,locked 2006.231.08:06:42.86/vblo/03,656.99,yes,locked 2006.231.08:06:42.86/vblo/04,712.99,yes,locked 2006.231.08:06:42.86/vblo/05,744.99,yes,locked 2006.231.08:06:42.86/vblo/06,752.99,yes,locked 2006.231.08:06:42.86/vblo/07,734.99,yes,locked 2006.231.08:06:42.86/vblo/08,744.99,yes,locked 2006.231.08:06:43.01/vabw/8 2006.231.08:06:43.16/vbbw/8 2006.231.08:06:43.25/xfe/off,on,12.2 2006.231.08:06:43.62/ifatt/23,28,28,28 2006.231.08:06:44.07/fmout-gps/S +4.45E-07 2006.231.08:06:44.12:!2006.231.08:07:50 2006.231.08:07:50.01:data_valid=off 2006.231.08:07:50.01:postob 2006.231.08:07:50.21/cable/+6.3719E-03 2006.231.08:07:50.21/wx/30.49,1004.4,86 2006.231.08:07:51.07/fmout-gps/S +4.44E-07 2006.231.08:07:51.07:scan_name=231-0808,k06231,60 2006.231.08:07:51.07:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.231.08:07:52.14#flagr#flagr/antenna,new-source 2006.231.08:07:52.14:checkk5 2006.231.08:07:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:07:52.90/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:07:53.28/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:07:53.66/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:07:54.02/chk_obsdata//k5ts1/T2310806??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.231.08:07:54.38/chk_obsdata//k5ts2/T2310806??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.231.08:07:54.75/chk_obsdata//k5ts3/T2310806??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.231.08:07:55.11/chk_obsdata//k5ts4/T2310806??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.231.08:07:55.80/k5log//k5ts1_log_newline 2006.231.08:07:56.48/k5log//k5ts2_log_newline 2006.231.08:07:57.17/k5log//k5ts3_log_newline 2006.231.08:07:57.86/k5log//k5ts4_log_newline 2006.231.08:07:57.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:07:57.88:4f8m12a=2 2006.231.08:07:57.88$4f8m12a/echo=on 2006.231.08:07:57.88$4f8m12a/pcalon 2006.231.08:07:57.88$pcalon/"no phase cal control is implemented here 2006.231.08:07:57.88$4f8m12a/"tpicd=stop 2006.231.08:07:57.88$4f8m12a/vc4f8 2006.231.08:07:57.88$vc4f8/valo=1,532.99 2006.231.08:07:57.88#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.08:07:57.89#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.08:07:57.89#ibcon#ireg 17 cls_cnt 0 2006.231.08:07:57.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:07:57.89#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:07:57.89#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:07:57.89#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:07:57.89#ibcon#first serial, iclass 34, count 0 2006.231.08:07:57.89#ibcon#enter sib2, iclass 34, count 0 2006.231.08:07:57.89#ibcon#flushed, iclass 34, count 0 2006.231.08:07:57.89#ibcon#about to write, iclass 34, count 0 2006.231.08:07:57.89#ibcon#wrote, iclass 34, count 0 2006.231.08:07:57.89#ibcon#about to read 3, iclass 34, count 0 2006.231.08:07:57.93#ibcon#read 3, iclass 34, count 0 2006.231.08:07:57.93#ibcon#about to read 4, iclass 34, count 0 2006.231.08:07:57.93#ibcon#read 4, iclass 34, count 0 2006.231.08:07:57.93#ibcon#about to read 5, iclass 34, count 0 2006.231.08:07:57.93#ibcon#read 5, iclass 34, count 0 2006.231.08:07:57.93#ibcon#about to read 6, iclass 34, count 0 2006.231.08:07:57.93#ibcon#read 6, iclass 34, count 0 2006.231.08:07:57.93#ibcon#end of sib2, iclass 34, count 0 2006.231.08:07:57.93#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:07:57.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:07:57.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:07:57.93#ibcon#*before write, iclass 34, count 0 2006.231.08:07:57.93#ibcon#enter sib2, iclass 34, count 0 2006.231.08:07:57.93#ibcon#flushed, iclass 34, count 0 2006.231.08:07:57.93#ibcon#about to write, iclass 34, count 0 2006.231.08:07:57.93#ibcon#wrote, iclass 34, count 0 2006.231.08:07:57.93#ibcon#about to read 3, iclass 34, count 0 2006.231.08:07:57.97#ibcon#read 3, iclass 34, count 0 2006.231.08:07:57.97#ibcon#about to read 4, iclass 34, count 0 2006.231.08:07:57.97#ibcon#read 4, iclass 34, count 0 2006.231.08:07:57.97#ibcon#about to read 5, iclass 34, count 0 2006.231.08:07:57.97#ibcon#read 5, iclass 34, count 0 2006.231.08:07:57.97#ibcon#about to read 6, iclass 34, count 0 2006.231.08:07:57.97#ibcon#read 6, iclass 34, count 0 2006.231.08:07:57.97#ibcon#end of sib2, iclass 34, count 0 2006.231.08:07:57.97#ibcon#*after write, iclass 34, count 0 2006.231.08:07:57.97#ibcon#*before return 0, iclass 34, count 0 2006.231.08:07:57.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:07:57.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:07:57.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:07:57.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:07:57.97$vc4f8/va=1,8 2006.231.08:07:57.97#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.08:07:57.97#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.08:07:57.97#ibcon#ireg 11 cls_cnt 2 2006.231.08:07:57.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:07:57.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:07:57.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:07:57.97#ibcon#enter wrdev, iclass 36, count 2 2006.231.08:07:57.97#ibcon#first serial, iclass 36, count 2 2006.231.08:07:57.97#ibcon#enter sib2, iclass 36, count 2 2006.231.08:07:57.97#ibcon#flushed, iclass 36, count 2 2006.231.08:07:57.97#ibcon#about to write, iclass 36, count 2 2006.231.08:07:57.97#ibcon#wrote, iclass 36, count 2 2006.231.08:07:57.97#ibcon#about to read 3, iclass 36, count 2 2006.231.08:07:58.00#ibcon#read 3, iclass 36, count 2 2006.231.08:07:58.00#ibcon#about to read 4, iclass 36, count 2 2006.231.08:07:58.00#ibcon#read 4, iclass 36, count 2 2006.231.08:07:58.00#ibcon#about to read 5, iclass 36, count 2 2006.231.08:07:58.00#ibcon#read 5, iclass 36, count 2 2006.231.08:07:58.00#ibcon#about to read 6, iclass 36, count 2 2006.231.08:07:58.00#ibcon#read 6, iclass 36, count 2 2006.231.08:07:58.00#ibcon#end of sib2, iclass 36, count 2 2006.231.08:07:58.00#ibcon#*mode == 0, iclass 36, count 2 2006.231.08:07:58.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.08:07:58.00#ibcon#[25=AT01-08\r\n] 2006.231.08:07:58.00#ibcon#*before write, iclass 36, count 2 2006.231.08:07:58.00#ibcon#enter sib2, iclass 36, count 2 2006.231.08:07:58.00#ibcon#flushed, iclass 36, count 2 2006.231.08:07:58.00#ibcon#about to write, iclass 36, count 2 2006.231.08:07:58.00#ibcon#wrote, iclass 36, count 2 2006.231.08:07:58.00#ibcon#about to read 3, iclass 36, count 2 2006.231.08:07:58.03#ibcon#read 3, iclass 36, count 2 2006.231.08:07:58.03#ibcon#about to read 4, iclass 36, count 2 2006.231.08:07:58.03#ibcon#read 4, iclass 36, count 2 2006.231.08:07:58.03#ibcon#about to read 5, iclass 36, count 2 2006.231.08:07:58.03#ibcon#read 5, iclass 36, count 2 2006.231.08:07:58.03#ibcon#about to read 6, iclass 36, count 2 2006.231.08:07:58.03#ibcon#read 6, iclass 36, count 2 2006.231.08:07:58.03#ibcon#end of sib2, iclass 36, count 2 2006.231.08:07:58.03#ibcon#*after write, iclass 36, count 2 2006.231.08:07:58.03#ibcon#*before return 0, iclass 36, count 2 2006.231.08:07:58.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:07:58.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:07:58.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.08:07:58.03#ibcon#ireg 7 cls_cnt 0 2006.231.08:07:58.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:07:58.14#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:07:58.14#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:07:58.14#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:07:58.14#ibcon#first serial, iclass 36, count 0 2006.231.08:07:58.14#ibcon#enter sib2, iclass 36, count 0 2006.231.08:07:58.14#ibcon#flushed, iclass 36, count 0 2006.231.08:07:58.14#ibcon#about to write, iclass 36, count 0 2006.231.08:07:58.14#ibcon#wrote, iclass 36, count 0 2006.231.08:07:58.14#ibcon#about to read 3, iclass 36, count 0 2006.231.08:07:58.16#ibcon#read 3, iclass 36, count 0 2006.231.08:07:58.16#ibcon#about to read 4, iclass 36, count 0 2006.231.08:07:58.16#ibcon#read 4, iclass 36, count 0 2006.231.08:07:58.16#ibcon#about to read 5, iclass 36, count 0 2006.231.08:07:58.16#ibcon#read 5, iclass 36, count 0 2006.231.08:07:58.16#ibcon#about to read 6, iclass 36, count 0 2006.231.08:07:58.16#ibcon#read 6, iclass 36, count 0 2006.231.08:07:58.16#ibcon#end of sib2, iclass 36, count 0 2006.231.08:07:58.16#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:07:58.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:07:58.16#ibcon#[25=USB\r\n] 2006.231.08:07:58.16#ibcon#*before write, iclass 36, count 0 2006.231.08:07:58.16#ibcon#enter sib2, iclass 36, count 0 2006.231.08:07:58.16#ibcon#flushed, iclass 36, count 0 2006.231.08:07:58.16#ibcon#about to write, iclass 36, count 0 2006.231.08:07:58.16#ibcon#wrote, iclass 36, count 0 2006.231.08:07:58.16#ibcon#about to read 3, iclass 36, count 0 2006.231.08:07:58.19#ibcon#read 3, iclass 36, count 0 2006.231.08:07:58.19#ibcon#about to read 4, iclass 36, count 0 2006.231.08:07:58.19#ibcon#read 4, iclass 36, count 0 2006.231.08:07:58.19#ibcon#about to read 5, iclass 36, count 0 2006.231.08:07:58.19#ibcon#read 5, iclass 36, count 0 2006.231.08:07:58.19#ibcon#about to read 6, iclass 36, count 0 2006.231.08:07:58.19#ibcon#read 6, iclass 36, count 0 2006.231.08:07:58.19#ibcon#end of sib2, iclass 36, count 0 2006.231.08:07:58.19#ibcon#*after write, iclass 36, count 0 2006.231.08:07:58.19#ibcon#*before return 0, iclass 36, count 0 2006.231.08:07:58.19#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:07:58.19#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:07:58.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:07:58.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:07:58.19$vc4f8/valo=2,572.99 2006.231.08:07:58.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.08:07:58.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.08:07:58.19#ibcon#ireg 17 cls_cnt 0 2006.231.08:07:58.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:07:58.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:07:58.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:07:58.19#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:07:58.19#ibcon#first serial, iclass 38, count 0 2006.231.08:07:58.19#ibcon#enter sib2, iclass 38, count 0 2006.231.08:07:58.19#ibcon#flushed, iclass 38, count 0 2006.231.08:07:58.19#ibcon#about to write, iclass 38, count 0 2006.231.08:07:58.19#ibcon#wrote, iclass 38, count 0 2006.231.08:07:58.19#ibcon#about to read 3, iclass 38, count 0 2006.231.08:07:58.22#ibcon#read 3, iclass 38, count 0 2006.231.08:07:58.22#ibcon#about to read 4, iclass 38, count 0 2006.231.08:07:58.22#ibcon#read 4, iclass 38, count 0 2006.231.08:07:58.22#ibcon#about to read 5, iclass 38, count 0 2006.231.08:07:58.22#ibcon#read 5, iclass 38, count 0 2006.231.08:07:58.22#ibcon#about to read 6, iclass 38, count 0 2006.231.08:07:58.22#ibcon#read 6, iclass 38, count 0 2006.231.08:07:58.22#ibcon#end of sib2, iclass 38, count 0 2006.231.08:07:58.22#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:07:58.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:07:58.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:07:58.22#ibcon#*before write, iclass 38, count 0 2006.231.08:07:58.22#ibcon#enter sib2, iclass 38, count 0 2006.231.08:07:58.22#ibcon#flushed, iclass 38, count 0 2006.231.08:07:58.22#ibcon#about to write, iclass 38, count 0 2006.231.08:07:58.22#ibcon#wrote, iclass 38, count 0 2006.231.08:07:58.22#ibcon#about to read 3, iclass 38, count 0 2006.231.08:07:58.25#ibcon#read 3, iclass 38, count 0 2006.231.08:07:58.25#ibcon#about to read 4, iclass 38, count 0 2006.231.08:07:58.25#ibcon#read 4, iclass 38, count 0 2006.231.08:07:58.25#ibcon#about to read 5, iclass 38, count 0 2006.231.08:07:58.25#ibcon#read 5, iclass 38, count 0 2006.231.08:07:58.25#ibcon#about to read 6, iclass 38, count 0 2006.231.08:07:58.25#ibcon#read 6, iclass 38, count 0 2006.231.08:07:58.25#ibcon#end of sib2, iclass 38, count 0 2006.231.08:07:58.25#ibcon#*after write, iclass 38, count 0 2006.231.08:07:58.25#ibcon#*before return 0, iclass 38, count 0 2006.231.08:07:58.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:07:58.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:07:58.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:07:58.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:07:58.25$vc4f8/va=2,7 2006.231.08:07:58.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.08:07:58.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.08:07:58.25#ibcon#ireg 11 cls_cnt 2 2006.231.08:07:58.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:07:58.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:07:58.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:07:58.32#ibcon#enter wrdev, iclass 40, count 2 2006.231.08:07:58.32#ibcon#first serial, iclass 40, count 2 2006.231.08:07:58.32#ibcon#enter sib2, iclass 40, count 2 2006.231.08:07:58.32#ibcon#flushed, iclass 40, count 2 2006.231.08:07:58.32#ibcon#about to write, iclass 40, count 2 2006.231.08:07:58.32#ibcon#wrote, iclass 40, count 2 2006.231.08:07:58.32#ibcon#about to read 3, iclass 40, count 2 2006.231.08:07:58.33#ibcon#read 3, iclass 40, count 2 2006.231.08:07:58.33#ibcon#about to read 4, iclass 40, count 2 2006.231.08:07:58.33#ibcon#read 4, iclass 40, count 2 2006.231.08:07:58.33#ibcon#about to read 5, iclass 40, count 2 2006.231.08:07:58.33#ibcon#read 5, iclass 40, count 2 2006.231.08:07:58.33#ibcon#about to read 6, iclass 40, count 2 2006.231.08:07:58.33#ibcon#read 6, iclass 40, count 2 2006.231.08:07:58.33#ibcon#end of sib2, iclass 40, count 2 2006.231.08:07:58.33#ibcon#*mode == 0, iclass 40, count 2 2006.231.08:07:58.33#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.08:07:58.33#ibcon#[25=AT02-07\r\n] 2006.231.08:07:58.33#ibcon#*before write, iclass 40, count 2 2006.231.08:07:58.33#ibcon#enter sib2, iclass 40, count 2 2006.231.08:07:58.33#ibcon#flushed, iclass 40, count 2 2006.231.08:07:58.33#ibcon#about to write, iclass 40, count 2 2006.231.08:07:58.33#ibcon#wrote, iclass 40, count 2 2006.231.08:07:58.33#ibcon#about to read 3, iclass 40, count 2 2006.231.08:07:58.36#ibcon#read 3, iclass 40, count 2 2006.231.08:07:58.36#ibcon#about to read 4, iclass 40, count 2 2006.231.08:07:58.36#ibcon#read 4, iclass 40, count 2 2006.231.08:07:58.36#ibcon#about to read 5, iclass 40, count 2 2006.231.08:07:58.36#ibcon#read 5, iclass 40, count 2 2006.231.08:07:58.36#ibcon#about to read 6, iclass 40, count 2 2006.231.08:07:58.36#ibcon#read 6, iclass 40, count 2 2006.231.08:07:58.36#ibcon#end of sib2, iclass 40, count 2 2006.231.08:07:58.36#ibcon#*after write, iclass 40, count 2 2006.231.08:07:58.36#ibcon#*before return 0, iclass 40, count 2 2006.231.08:07:58.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:07:58.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:07:58.36#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.08:07:58.36#ibcon#ireg 7 cls_cnt 0 2006.231.08:07:58.36#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:07:58.48#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:07:58.48#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:07:58.48#ibcon#enter wrdev, iclass 40, count 0 2006.231.08:07:58.48#ibcon#first serial, iclass 40, count 0 2006.231.08:07:58.48#ibcon#enter sib2, iclass 40, count 0 2006.231.08:07:58.48#ibcon#flushed, iclass 40, count 0 2006.231.08:07:58.48#ibcon#about to write, iclass 40, count 0 2006.231.08:07:58.48#ibcon#wrote, iclass 40, count 0 2006.231.08:07:58.48#ibcon#about to read 3, iclass 40, count 0 2006.231.08:07:58.50#ibcon#read 3, iclass 40, count 0 2006.231.08:07:58.50#ibcon#about to read 4, iclass 40, count 0 2006.231.08:07:58.50#ibcon#read 4, iclass 40, count 0 2006.231.08:07:58.50#ibcon#about to read 5, iclass 40, count 0 2006.231.08:07:58.50#ibcon#read 5, iclass 40, count 0 2006.231.08:07:58.50#ibcon#about to read 6, iclass 40, count 0 2006.231.08:07:58.50#ibcon#read 6, iclass 40, count 0 2006.231.08:07:58.50#ibcon#end of sib2, iclass 40, count 0 2006.231.08:07:58.50#ibcon#*mode == 0, iclass 40, count 0 2006.231.08:07:58.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.08:07:58.50#ibcon#[25=USB\r\n] 2006.231.08:07:58.50#ibcon#*before write, iclass 40, count 0 2006.231.08:07:58.50#ibcon#enter sib2, iclass 40, count 0 2006.231.08:07:58.50#ibcon#flushed, iclass 40, count 0 2006.231.08:07:58.50#ibcon#about to write, iclass 40, count 0 2006.231.08:07:58.50#ibcon#wrote, iclass 40, count 0 2006.231.08:07:58.50#ibcon#about to read 3, iclass 40, count 0 2006.231.08:07:58.53#ibcon#read 3, iclass 40, count 0 2006.231.08:07:58.53#ibcon#about to read 4, iclass 40, count 0 2006.231.08:07:58.54#ibcon#read 4, iclass 40, count 0 2006.231.08:07:58.54#ibcon#about to read 5, iclass 40, count 0 2006.231.08:07:58.54#ibcon#read 5, iclass 40, count 0 2006.231.08:07:58.54#ibcon#about to read 6, iclass 40, count 0 2006.231.08:07:58.54#ibcon#read 6, iclass 40, count 0 2006.231.08:07:58.54#ibcon#end of sib2, iclass 40, count 0 2006.231.08:07:58.54#ibcon#*after write, iclass 40, count 0 2006.231.08:07:58.54#ibcon#*before return 0, iclass 40, count 0 2006.231.08:07:58.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:07:58.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:07:58.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.08:07:58.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.08:07:58.54$vc4f8/valo=3,672.99 2006.231.08:07:58.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.08:07:58.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.08:07:58.54#ibcon#ireg 17 cls_cnt 0 2006.231.08:07:58.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:07:58.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:07:58.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:07:58.54#ibcon#enter wrdev, iclass 4, count 0 2006.231.08:07:58.54#ibcon#first serial, iclass 4, count 0 2006.231.08:07:58.54#ibcon#enter sib2, iclass 4, count 0 2006.231.08:07:58.54#ibcon#flushed, iclass 4, count 0 2006.231.08:07:58.54#ibcon#about to write, iclass 4, count 0 2006.231.08:07:58.54#ibcon#wrote, iclass 4, count 0 2006.231.08:07:58.54#ibcon#about to read 3, iclass 4, count 0 2006.231.08:07:58.55#ibcon#read 3, iclass 4, count 0 2006.231.08:07:58.55#ibcon#about to read 4, iclass 4, count 0 2006.231.08:07:58.55#ibcon#read 4, iclass 4, count 0 2006.231.08:07:58.55#ibcon#about to read 5, iclass 4, count 0 2006.231.08:07:58.55#ibcon#read 5, iclass 4, count 0 2006.231.08:07:58.55#ibcon#about to read 6, iclass 4, count 0 2006.231.08:07:58.55#ibcon#read 6, iclass 4, count 0 2006.231.08:07:58.55#ibcon#end of sib2, iclass 4, count 0 2006.231.08:07:58.55#ibcon#*mode == 0, iclass 4, count 0 2006.231.08:07:58.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.08:07:58.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:07:58.55#ibcon#*before write, iclass 4, count 0 2006.231.08:07:58.55#ibcon#enter sib2, iclass 4, count 0 2006.231.08:07:58.55#ibcon#flushed, iclass 4, count 0 2006.231.08:07:58.55#ibcon#about to write, iclass 4, count 0 2006.231.08:07:58.55#ibcon#wrote, iclass 4, count 0 2006.231.08:07:58.55#ibcon#about to read 3, iclass 4, count 0 2006.231.08:07:58.59#ibcon#read 3, iclass 4, count 0 2006.231.08:07:58.59#ibcon#about to read 4, iclass 4, count 0 2006.231.08:07:58.59#ibcon#read 4, iclass 4, count 0 2006.231.08:07:58.59#ibcon#about to read 5, iclass 4, count 0 2006.231.08:07:58.59#ibcon#read 5, iclass 4, count 0 2006.231.08:07:58.59#ibcon#about to read 6, iclass 4, count 0 2006.231.08:07:58.59#ibcon#read 6, iclass 4, count 0 2006.231.08:07:58.59#ibcon#end of sib2, iclass 4, count 0 2006.231.08:07:58.59#ibcon#*after write, iclass 4, count 0 2006.231.08:07:58.59#ibcon#*before return 0, iclass 4, count 0 2006.231.08:07:58.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:07:58.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:07:58.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.08:07:58.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.08:07:58.59$vc4f8/va=3,8 2006.231.08:07:58.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.08:07:58.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.08:07:58.59#ibcon#ireg 11 cls_cnt 2 2006.231.08:07:58.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:07:58.66#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:07:58.66#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:07:58.66#ibcon#enter wrdev, iclass 6, count 2 2006.231.08:07:58.66#ibcon#first serial, iclass 6, count 2 2006.231.08:07:58.66#ibcon#enter sib2, iclass 6, count 2 2006.231.08:07:58.66#ibcon#flushed, iclass 6, count 2 2006.231.08:07:58.66#ibcon#about to write, iclass 6, count 2 2006.231.08:07:58.66#ibcon#wrote, iclass 6, count 2 2006.231.08:07:58.66#ibcon#about to read 3, iclass 6, count 2 2006.231.08:07:58.68#ibcon#read 3, iclass 6, count 2 2006.231.08:07:58.68#ibcon#about to read 4, iclass 6, count 2 2006.231.08:07:58.68#ibcon#read 4, iclass 6, count 2 2006.231.08:07:58.68#ibcon#about to read 5, iclass 6, count 2 2006.231.08:07:58.68#ibcon#read 5, iclass 6, count 2 2006.231.08:07:58.68#ibcon#about to read 6, iclass 6, count 2 2006.231.08:07:58.68#ibcon#read 6, iclass 6, count 2 2006.231.08:07:58.68#ibcon#end of sib2, iclass 6, count 2 2006.231.08:07:58.68#ibcon#*mode == 0, iclass 6, count 2 2006.231.08:07:58.68#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.08:07:58.68#ibcon#[25=AT03-08\r\n] 2006.231.08:07:58.68#ibcon#*before write, iclass 6, count 2 2006.231.08:07:58.68#ibcon#enter sib2, iclass 6, count 2 2006.231.08:07:58.68#ibcon#flushed, iclass 6, count 2 2006.231.08:07:58.68#ibcon#about to write, iclass 6, count 2 2006.231.08:07:58.68#ibcon#wrote, iclass 6, count 2 2006.231.08:07:58.68#ibcon#about to read 3, iclass 6, count 2 2006.231.08:07:58.71#ibcon#read 3, iclass 6, count 2 2006.231.08:07:58.71#ibcon#about to read 4, iclass 6, count 2 2006.231.08:07:58.71#ibcon#read 4, iclass 6, count 2 2006.231.08:07:58.71#ibcon#about to read 5, iclass 6, count 2 2006.231.08:07:58.71#ibcon#read 5, iclass 6, count 2 2006.231.08:07:58.71#ibcon#about to read 6, iclass 6, count 2 2006.231.08:07:58.71#ibcon#read 6, iclass 6, count 2 2006.231.08:07:58.71#ibcon#end of sib2, iclass 6, count 2 2006.231.08:07:58.71#ibcon#*after write, iclass 6, count 2 2006.231.08:07:58.71#ibcon#*before return 0, iclass 6, count 2 2006.231.08:07:58.71#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:07:58.71#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:07:58.71#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.08:07:58.71#ibcon#ireg 7 cls_cnt 0 2006.231.08:07:58.71#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:07:58.83#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:07:58.83#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:07:58.83#ibcon#enter wrdev, iclass 6, count 0 2006.231.08:07:58.83#ibcon#first serial, iclass 6, count 0 2006.231.08:07:58.83#ibcon#enter sib2, iclass 6, count 0 2006.231.08:07:58.83#ibcon#flushed, iclass 6, count 0 2006.231.08:07:58.83#ibcon#about to write, iclass 6, count 0 2006.231.08:07:58.83#ibcon#wrote, iclass 6, count 0 2006.231.08:07:58.83#ibcon#about to read 3, iclass 6, count 0 2006.231.08:07:58.85#ibcon#read 3, iclass 6, count 0 2006.231.08:07:58.85#ibcon#about to read 4, iclass 6, count 0 2006.231.08:07:58.85#ibcon#read 4, iclass 6, count 0 2006.231.08:07:58.85#ibcon#about to read 5, iclass 6, count 0 2006.231.08:07:58.85#ibcon#read 5, iclass 6, count 0 2006.231.08:07:58.85#ibcon#about to read 6, iclass 6, count 0 2006.231.08:07:58.85#ibcon#read 6, iclass 6, count 0 2006.231.08:07:58.85#ibcon#end of sib2, iclass 6, count 0 2006.231.08:07:58.85#ibcon#*mode == 0, iclass 6, count 0 2006.231.08:07:58.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.08:07:58.85#ibcon#[25=USB\r\n] 2006.231.08:07:58.85#ibcon#*before write, iclass 6, count 0 2006.231.08:07:58.85#ibcon#enter sib2, iclass 6, count 0 2006.231.08:07:58.85#ibcon#flushed, iclass 6, count 0 2006.231.08:07:58.85#ibcon#about to write, iclass 6, count 0 2006.231.08:07:58.85#ibcon#wrote, iclass 6, count 0 2006.231.08:07:58.85#ibcon#about to read 3, iclass 6, count 0 2006.231.08:07:58.88#ibcon#read 3, iclass 6, count 0 2006.231.08:07:58.88#ibcon#about to read 4, iclass 6, count 0 2006.231.08:07:58.88#ibcon#read 4, iclass 6, count 0 2006.231.08:07:58.88#ibcon#about to read 5, iclass 6, count 0 2006.231.08:07:58.88#ibcon#read 5, iclass 6, count 0 2006.231.08:07:58.88#ibcon#about to read 6, iclass 6, count 0 2006.231.08:07:58.88#ibcon#read 6, iclass 6, count 0 2006.231.08:07:58.88#ibcon#end of sib2, iclass 6, count 0 2006.231.08:07:58.88#ibcon#*after write, iclass 6, count 0 2006.231.08:07:58.88#ibcon#*before return 0, iclass 6, count 0 2006.231.08:07:58.88#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:07:58.88#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:07:58.88#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.08:07:58.88#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.08:07:58.88$vc4f8/valo=4,832.99 2006.231.08:07:58.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.08:07:58.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.08:07:58.88#ibcon#ireg 17 cls_cnt 0 2006.231.08:07:58.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:07:58.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:07:58.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:07:58.88#ibcon#enter wrdev, iclass 10, count 0 2006.231.08:07:58.88#ibcon#first serial, iclass 10, count 0 2006.231.08:07:58.88#ibcon#enter sib2, iclass 10, count 0 2006.231.08:07:58.88#ibcon#flushed, iclass 10, count 0 2006.231.08:07:58.88#ibcon#about to write, iclass 10, count 0 2006.231.08:07:58.88#ibcon#wrote, iclass 10, count 0 2006.231.08:07:58.88#ibcon#about to read 3, iclass 10, count 0 2006.231.08:07:58.90#ibcon#read 3, iclass 10, count 0 2006.231.08:07:58.90#ibcon#about to read 4, iclass 10, count 0 2006.231.08:07:58.90#ibcon#read 4, iclass 10, count 0 2006.231.08:07:58.90#ibcon#about to read 5, iclass 10, count 0 2006.231.08:07:58.90#ibcon#read 5, iclass 10, count 0 2006.231.08:07:58.90#ibcon#about to read 6, iclass 10, count 0 2006.231.08:07:58.90#ibcon#read 6, iclass 10, count 0 2006.231.08:07:58.90#ibcon#end of sib2, iclass 10, count 0 2006.231.08:07:58.90#ibcon#*mode == 0, iclass 10, count 0 2006.231.08:07:58.90#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.08:07:58.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:07:58.90#ibcon#*before write, iclass 10, count 0 2006.231.08:07:58.90#ibcon#enter sib2, iclass 10, count 0 2006.231.08:07:58.90#ibcon#flushed, iclass 10, count 0 2006.231.08:07:58.90#ibcon#about to write, iclass 10, count 0 2006.231.08:07:58.90#ibcon#wrote, iclass 10, count 0 2006.231.08:07:58.90#ibcon#about to read 3, iclass 10, count 0 2006.231.08:07:58.94#ibcon#read 3, iclass 10, count 0 2006.231.08:07:58.94#ibcon#about to read 4, iclass 10, count 0 2006.231.08:07:58.94#ibcon#read 4, iclass 10, count 0 2006.231.08:07:58.94#ibcon#about to read 5, iclass 10, count 0 2006.231.08:07:58.94#ibcon#read 5, iclass 10, count 0 2006.231.08:07:58.94#ibcon#about to read 6, iclass 10, count 0 2006.231.08:07:58.94#ibcon#read 6, iclass 10, count 0 2006.231.08:07:58.94#ibcon#end of sib2, iclass 10, count 0 2006.231.08:07:58.94#ibcon#*after write, iclass 10, count 0 2006.231.08:07:58.94#ibcon#*before return 0, iclass 10, count 0 2006.231.08:07:58.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:07:58.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:07:58.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.08:07:58.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.08:07:58.94$vc4f8/va=4,7 2006.231.08:07:58.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.08:07:58.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.08:07:58.94#ibcon#ireg 11 cls_cnt 2 2006.231.08:07:58.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:07:59.00#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:07:59.00#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:07:59.00#ibcon#enter wrdev, iclass 12, count 2 2006.231.08:07:59.00#ibcon#first serial, iclass 12, count 2 2006.231.08:07:59.00#ibcon#enter sib2, iclass 12, count 2 2006.231.08:07:59.00#ibcon#flushed, iclass 12, count 2 2006.231.08:07:59.00#ibcon#about to write, iclass 12, count 2 2006.231.08:07:59.00#ibcon#wrote, iclass 12, count 2 2006.231.08:07:59.00#ibcon#about to read 3, iclass 12, count 2 2006.231.08:07:59.02#ibcon#read 3, iclass 12, count 2 2006.231.08:07:59.02#ibcon#about to read 4, iclass 12, count 2 2006.231.08:07:59.02#ibcon#read 4, iclass 12, count 2 2006.231.08:07:59.02#ibcon#about to read 5, iclass 12, count 2 2006.231.08:07:59.02#ibcon#read 5, iclass 12, count 2 2006.231.08:07:59.02#ibcon#about to read 6, iclass 12, count 2 2006.231.08:07:59.02#ibcon#read 6, iclass 12, count 2 2006.231.08:07:59.02#ibcon#end of sib2, iclass 12, count 2 2006.231.08:07:59.02#ibcon#*mode == 0, iclass 12, count 2 2006.231.08:07:59.02#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.08:07:59.02#ibcon#[25=AT04-07\r\n] 2006.231.08:07:59.02#ibcon#*before write, iclass 12, count 2 2006.231.08:07:59.02#ibcon#enter sib2, iclass 12, count 2 2006.231.08:07:59.02#ibcon#flushed, iclass 12, count 2 2006.231.08:07:59.02#ibcon#about to write, iclass 12, count 2 2006.231.08:07:59.02#ibcon#wrote, iclass 12, count 2 2006.231.08:07:59.02#ibcon#about to read 3, iclass 12, count 2 2006.231.08:07:59.05#ibcon#read 3, iclass 12, count 2 2006.231.08:07:59.05#ibcon#about to read 4, iclass 12, count 2 2006.231.08:07:59.05#ibcon#read 4, iclass 12, count 2 2006.231.08:07:59.05#ibcon#about to read 5, iclass 12, count 2 2006.231.08:07:59.05#ibcon#read 5, iclass 12, count 2 2006.231.08:07:59.05#ibcon#about to read 6, iclass 12, count 2 2006.231.08:07:59.05#ibcon#read 6, iclass 12, count 2 2006.231.08:07:59.05#ibcon#end of sib2, iclass 12, count 2 2006.231.08:07:59.05#ibcon#*after write, iclass 12, count 2 2006.231.08:07:59.05#ibcon#*before return 0, iclass 12, count 2 2006.231.08:07:59.05#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:07:59.05#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:07:59.05#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.08:07:59.05#ibcon#ireg 7 cls_cnt 0 2006.231.08:07:59.05#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:07:59.17#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:07:59.17#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:07:59.17#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:07:59.17#ibcon#first serial, iclass 12, count 0 2006.231.08:07:59.17#ibcon#enter sib2, iclass 12, count 0 2006.231.08:07:59.17#ibcon#flushed, iclass 12, count 0 2006.231.08:07:59.17#ibcon#about to write, iclass 12, count 0 2006.231.08:07:59.17#ibcon#wrote, iclass 12, count 0 2006.231.08:07:59.17#ibcon#about to read 3, iclass 12, count 0 2006.231.08:07:59.19#ibcon#read 3, iclass 12, count 0 2006.231.08:07:59.19#ibcon#about to read 4, iclass 12, count 0 2006.231.08:07:59.19#ibcon#read 4, iclass 12, count 0 2006.231.08:07:59.19#ibcon#about to read 5, iclass 12, count 0 2006.231.08:07:59.19#ibcon#read 5, iclass 12, count 0 2006.231.08:07:59.19#ibcon#about to read 6, iclass 12, count 0 2006.231.08:07:59.19#ibcon#read 6, iclass 12, count 0 2006.231.08:07:59.19#ibcon#end of sib2, iclass 12, count 0 2006.231.08:07:59.19#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:07:59.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:07:59.19#ibcon#[25=USB\r\n] 2006.231.08:07:59.19#ibcon#*before write, iclass 12, count 0 2006.231.08:07:59.19#ibcon#enter sib2, iclass 12, count 0 2006.231.08:07:59.19#ibcon#flushed, iclass 12, count 0 2006.231.08:07:59.19#ibcon#about to write, iclass 12, count 0 2006.231.08:07:59.19#ibcon#wrote, iclass 12, count 0 2006.231.08:07:59.19#ibcon#about to read 3, iclass 12, count 0 2006.231.08:07:59.22#ibcon#read 3, iclass 12, count 0 2006.231.08:07:59.22#ibcon#about to read 4, iclass 12, count 0 2006.231.08:07:59.22#ibcon#read 4, iclass 12, count 0 2006.231.08:07:59.22#ibcon#about to read 5, iclass 12, count 0 2006.231.08:07:59.22#ibcon#read 5, iclass 12, count 0 2006.231.08:07:59.22#ibcon#about to read 6, iclass 12, count 0 2006.231.08:07:59.22#ibcon#read 6, iclass 12, count 0 2006.231.08:07:59.22#ibcon#end of sib2, iclass 12, count 0 2006.231.08:07:59.22#ibcon#*after write, iclass 12, count 0 2006.231.08:07:59.22#ibcon#*before return 0, iclass 12, count 0 2006.231.08:07:59.22#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:07:59.22#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:07:59.22#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:07:59.22#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:07:59.22$vc4f8/valo=5,652.99 2006.231.08:07:59.22#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.08:07:59.22#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.08:07:59.22#ibcon#ireg 17 cls_cnt 0 2006.231.08:07:59.22#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:07:59.22#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:07:59.22#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:07:59.22#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:07:59.22#ibcon#first serial, iclass 14, count 0 2006.231.08:07:59.22#ibcon#enter sib2, iclass 14, count 0 2006.231.08:07:59.22#ibcon#flushed, iclass 14, count 0 2006.231.08:07:59.22#ibcon#about to write, iclass 14, count 0 2006.231.08:07:59.22#ibcon#wrote, iclass 14, count 0 2006.231.08:07:59.22#ibcon#about to read 3, iclass 14, count 0 2006.231.08:07:59.24#ibcon#read 3, iclass 14, count 0 2006.231.08:07:59.24#ibcon#about to read 4, iclass 14, count 0 2006.231.08:07:59.24#ibcon#read 4, iclass 14, count 0 2006.231.08:07:59.24#ibcon#about to read 5, iclass 14, count 0 2006.231.08:07:59.24#ibcon#read 5, iclass 14, count 0 2006.231.08:07:59.24#ibcon#about to read 6, iclass 14, count 0 2006.231.08:07:59.24#ibcon#read 6, iclass 14, count 0 2006.231.08:07:59.24#ibcon#end of sib2, iclass 14, count 0 2006.231.08:07:59.24#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:07:59.24#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:07:59.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:07:59.24#ibcon#*before write, iclass 14, count 0 2006.231.08:07:59.24#ibcon#enter sib2, iclass 14, count 0 2006.231.08:07:59.24#ibcon#flushed, iclass 14, count 0 2006.231.08:07:59.24#ibcon#about to write, iclass 14, count 0 2006.231.08:07:59.24#ibcon#wrote, iclass 14, count 0 2006.231.08:07:59.24#ibcon#about to read 3, iclass 14, count 0 2006.231.08:07:59.28#ibcon#read 3, iclass 14, count 0 2006.231.08:07:59.28#ibcon#about to read 4, iclass 14, count 0 2006.231.08:07:59.28#ibcon#read 4, iclass 14, count 0 2006.231.08:07:59.28#ibcon#about to read 5, iclass 14, count 0 2006.231.08:07:59.28#ibcon#read 5, iclass 14, count 0 2006.231.08:07:59.28#ibcon#about to read 6, iclass 14, count 0 2006.231.08:07:59.28#ibcon#read 6, iclass 14, count 0 2006.231.08:07:59.28#ibcon#end of sib2, iclass 14, count 0 2006.231.08:07:59.28#ibcon#*after write, iclass 14, count 0 2006.231.08:07:59.28#ibcon#*before return 0, iclass 14, count 0 2006.231.08:07:59.28#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:07:59.28#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:07:59.28#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:07:59.28#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:07:59.28$vc4f8/va=5,7 2006.231.08:07:59.28#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.08:07:59.28#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.08:07:59.28#ibcon#ireg 11 cls_cnt 2 2006.231.08:07:59.28#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:07:59.34#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:07:59.34#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:07:59.34#ibcon#enter wrdev, iclass 16, count 2 2006.231.08:07:59.34#ibcon#first serial, iclass 16, count 2 2006.231.08:07:59.34#ibcon#enter sib2, iclass 16, count 2 2006.231.08:07:59.34#ibcon#flushed, iclass 16, count 2 2006.231.08:07:59.34#ibcon#about to write, iclass 16, count 2 2006.231.08:07:59.34#ibcon#wrote, iclass 16, count 2 2006.231.08:07:59.34#ibcon#about to read 3, iclass 16, count 2 2006.231.08:07:59.36#ibcon#read 3, iclass 16, count 2 2006.231.08:07:59.36#ibcon#about to read 4, iclass 16, count 2 2006.231.08:07:59.36#ibcon#read 4, iclass 16, count 2 2006.231.08:07:59.36#ibcon#about to read 5, iclass 16, count 2 2006.231.08:07:59.36#ibcon#read 5, iclass 16, count 2 2006.231.08:07:59.36#ibcon#about to read 6, iclass 16, count 2 2006.231.08:07:59.36#ibcon#read 6, iclass 16, count 2 2006.231.08:07:59.36#ibcon#end of sib2, iclass 16, count 2 2006.231.08:07:59.36#ibcon#*mode == 0, iclass 16, count 2 2006.231.08:07:59.36#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.08:07:59.36#ibcon#[25=AT05-07\r\n] 2006.231.08:07:59.36#ibcon#*before write, iclass 16, count 2 2006.231.08:07:59.36#ibcon#enter sib2, iclass 16, count 2 2006.231.08:07:59.36#ibcon#flushed, iclass 16, count 2 2006.231.08:07:59.36#ibcon#about to write, iclass 16, count 2 2006.231.08:07:59.36#ibcon#wrote, iclass 16, count 2 2006.231.08:07:59.36#ibcon#about to read 3, iclass 16, count 2 2006.231.08:07:59.40#ibcon#read 3, iclass 16, count 2 2006.231.08:07:59.40#ibcon#about to read 4, iclass 16, count 2 2006.231.08:07:59.40#ibcon#read 4, iclass 16, count 2 2006.231.08:07:59.40#ibcon#about to read 5, iclass 16, count 2 2006.231.08:07:59.40#ibcon#read 5, iclass 16, count 2 2006.231.08:07:59.40#ibcon#about to read 6, iclass 16, count 2 2006.231.08:07:59.40#ibcon#read 6, iclass 16, count 2 2006.231.08:07:59.40#ibcon#end of sib2, iclass 16, count 2 2006.231.08:07:59.40#ibcon#*after write, iclass 16, count 2 2006.231.08:07:59.40#ibcon#*before return 0, iclass 16, count 2 2006.231.08:07:59.40#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:07:59.40#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:07:59.40#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.08:07:59.40#ibcon#ireg 7 cls_cnt 0 2006.231.08:07:59.40#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:07:59.51#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:07:59.51#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:07:59.51#ibcon#enter wrdev, iclass 16, count 0 2006.231.08:07:59.51#ibcon#first serial, iclass 16, count 0 2006.231.08:07:59.51#ibcon#enter sib2, iclass 16, count 0 2006.231.08:07:59.51#ibcon#flushed, iclass 16, count 0 2006.231.08:07:59.51#ibcon#about to write, iclass 16, count 0 2006.231.08:07:59.51#ibcon#wrote, iclass 16, count 0 2006.231.08:07:59.51#ibcon#about to read 3, iclass 16, count 0 2006.231.08:07:59.53#ibcon#read 3, iclass 16, count 0 2006.231.08:07:59.53#ibcon#about to read 4, iclass 16, count 0 2006.231.08:07:59.53#ibcon#read 4, iclass 16, count 0 2006.231.08:07:59.53#ibcon#about to read 5, iclass 16, count 0 2006.231.08:07:59.53#ibcon#read 5, iclass 16, count 0 2006.231.08:07:59.53#ibcon#about to read 6, iclass 16, count 0 2006.231.08:07:59.53#ibcon#read 6, iclass 16, count 0 2006.231.08:07:59.53#ibcon#end of sib2, iclass 16, count 0 2006.231.08:07:59.53#ibcon#*mode == 0, iclass 16, count 0 2006.231.08:07:59.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.08:07:59.53#ibcon#[25=USB\r\n] 2006.231.08:07:59.53#ibcon#*before write, iclass 16, count 0 2006.231.08:07:59.53#ibcon#enter sib2, iclass 16, count 0 2006.231.08:07:59.53#ibcon#flushed, iclass 16, count 0 2006.231.08:07:59.53#ibcon#about to write, iclass 16, count 0 2006.231.08:07:59.53#ibcon#wrote, iclass 16, count 0 2006.231.08:07:59.53#ibcon#about to read 3, iclass 16, count 0 2006.231.08:07:59.56#ibcon#read 3, iclass 16, count 0 2006.231.08:07:59.56#ibcon#about to read 4, iclass 16, count 0 2006.231.08:07:59.56#ibcon#read 4, iclass 16, count 0 2006.231.08:07:59.56#ibcon#about to read 5, iclass 16, count 0 2006.231.08:07:59.56#ibcon#read 5, iclass 16, count 0 2006.231.08:07:59.56#ibcon#about to read 6, iclass 16, count 0 2006.231.08:07:59.56#ibcon#read 6, iclass 16, count 0 2006.231.08:07:59.56#ibcon#end of sib2, iclass 16, count 0 2006.231.08:07:59.56#ibcon#*after write, iclass 16, count 0 2006.231.08:07:59.56#ibcon#*before return 0, iclass 16, count 0 2006.231.08:07:59.56#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:07:59.56#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:07:59.56#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.08:07:59.56#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.08:07:59.56$vc4f8/valo=6,772.99 2006.231.08:07:59.56#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.08:07:59.56#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.08:07:59.56#ibcon#ireg 17 cls_cnt 0 2006.231.08:07:59.56#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:07:59.56#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:07:59.56#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:07:59.56#ibcon#enter wrdev, iclass 18, count 0 2006.231.08:07:59.56#ibcon#first serial, iclass 18, count 0 2006.231.08:07:59.56#ibcon#enter sib2, iclass 18, count 0 2006.231.08:07:59.56#ibcon#flushed, iclass 18, count 0 2006.231.08:07:59.56#ibcon#about to write, iclass 18, count 0 2006.231.08:07:59.56#ibcon#wrote, iclass 18, count 0 2006.231.08:07:59.56#ibcon#about to read 3, iclass 18, count 0 2006.231.08:07:59.58#ibcon#read 3, iclass 18, count 0 2006.231.08:07:59.58#ibcon#about to read 4, iclass 18, count 0 2006.231.08:07:59.58#ibcon#read 4, iclass 18, count 0 2006.231.08:07:59.58#ibcon#about to read 5, iclass 18, count 0 2006.231.08:07:59.58#ibcon#read 5, iclass 18, count 0 2006.231.08:07:59.58#ibcon#about to read 6, iclass 18, count 0 2006.231.08:07:59.58#ibcon#read 6, iclass 18, count 0 2006.231.08:07:59.58#ibcon#end of sib2, iclass 18, count 0 2006.231.08:07:59.58#ibcon#*mode == 0, iclass 18, count 0 2006.231.08:07:59.58#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.08:07:59.58#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:07:59.58#ibcon#*before write, iclass 18, count 0 2006.231.08:07:59.58#ibcon#enter sib2, iclass 18, count 0 2006.231.08:07:59.58#ibcon#flushed, iclass 18, count 0 2006.231.08:07:59.58#ibcon#about to write, iclass 18, count 0 2006.231.08:07:59.58#ibcon#wrote, iclass 18, count 0 2006.231.08:07:59.58#ibcon#about to read 3, iclass 18, count 0 2006.231.08:07:59.62#ibcon#read 3, iclass 18, count 0 2006.231.08:07:59.62#ibcon#about to read 4, iclass 18, count 0 2006.231.08:07:59.62#ibcon#read 4, iclass 18, count 0 2006.231.08:07:59.62#ibcon#about to read 5, iclass 18, count 0 2006.231.08:07:59.62#ibcon#read 5, iclass 18, count 0 2006.231.08:07:59.62#ibcon#about to read 6, iclass 18, count 0 2006.231.08:07:59.62#ibcon#read 6, iclass 18, count 0 2006.231.08:07:59.62#ibcon#end of sib2, iclass 18, count 0 2006.231.08:07:59.62#ibcon#*after write, iclass 18, count 0 2006.231.08:07:59.62#ibcon#*before return 0, iclass 18, count 0 2006.231.08:07:59.62#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:07:59.62#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:07:59.62#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.08:07:59.62#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.08:07:59.62$vc4f8/va=6,6 2006.231.08:07:59.62#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.08:07:59.62#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.08:07:59.62#ibcon#ireg 11 cls_cnt 2 2006.231.08:07:59.62#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:07:59.68#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:07:59.68#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:07:59.68#ibcon#enter wrdev, iclass 20, count 2 2006.231.08:07:59.68#ibcon#first serial, iclass 20, count 2 2006.231.08:07:59.68#ibcon#enter sib2, iclass 20, count 2 2006.231.08:07:59.68#ibcon#flushed, iclass 20, count 2 2006.231.08:07:59.68#ibcon#about to write, iclass 20, count 2 2006.231.08:07:59.68#ibcon#wrote, iclass 20, count 2 2006.231.08:07:59.68#ibcon#about to read 3, iclass 20, count 2 2006.231.08:07:59.70#ibcon#read 3, iclass 20, count 2 2006.231.08:07:59.70#ibcon#about to read 4, iclass 20, count 2 2006.231.08:07:59.70#ibcon#read 4, iclass 20, count 2 2006.231.08:07:59.70#ibcon#about to read 5, iclass 20, count 2 2006.231.08:07:59.70#ibcon#read 5, iclass 20, count 2 2006.231.08:07:59.70#ibcon#about to read 6, iclass 20, count 2 2006.231.08:07:59.70#ibcon#read 6, iclass 20, count 2 2006.231.08:07:59.70#ibcon#end of sib2, iclass 20, count 2 2006.231.08:07:59.70#ibcon#*mode == 0, iclass 20, count 2 2006.231.08:07:59.70#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.08:07:59.70#ibcon#[25=AT06-06\r\n] 2006.231.08:07:59.70#ibcon#*before write, iclass 20, count 2 2006.231.08:07:59.70#ibcon#enter sib2, iclass 20, count 2 2006.231.08:07:59.70#ibcon#flushed, iclass 20, count 2 2006.231.08:07:59.70#ibcon#about to write, iclass 20, count 2 2006.231.08:07:59.70#ibcon#wrote, iclass 20, count 2 2006.231.08:07:59.70#ibcon#about to read 3, iclass 20, count 2 2006.231.08:07:59.73#ibcon#read 3, iclass 20, count 2 2006.231.08:07:59.73#ibcon#about to read 4, iclass 20, count 2 2006.231.08:07:59.73#ibcon#read 4, iclass 20, count 2 2006.231.08:07:59.73#ibcon#about to read 5, iclass 20, count 2 2006.231.08:07:59.73#ibcon#read 5, iclass 20, count 2 2006.231.08:07:59.73#ibcon#about to read 6, iclass 20, count 2 2006.231.08:07:59.73#ibcon#read 6, iclass 20, count 2 2006.231.08:07:59.73#ibcon#end of sib2, iclass 20, count 2 2006.231.08:07:59.73#ibcon#*after write, iclass 20, count 2 2006.231.08:07:59.73#ibcon#*before return 0, iclass 20, count 2 2006.231.08:07:59.73#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:07:59.73#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:07:59.73#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.08:07:59.73#ibcon#ireg 7 cls_cnt 0 2006.231.08:07:59.73#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:07:59.85#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:07:59.85#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:07:59.85#ibcon#enter wrdev, iclass 20, count 0 2006.231.08:07:59.85#ibcon#first serial, iclass 20, count 0 2006.231.08:07:59.85#ibcon#enter sib2, iclass 20, count 0 2006.231.08:07:59.85#ibcon#flushed, iclass 20, count 0 2006.231.08:07:59.85#ibcon#about to write, iclass 20, count 0 2006.231.08:07:59.85#ibcon#wrote, iclass 20, count 0 2006.231.08:07:59.85#ibcon#about to read 3, iclass 20, count 0 2006.231.08:07:59.87#ibcon#read 3, iclass 20, count 0 2006.231.08:07:59.87#ibcon#about to read 4, iclass 20, count 0 2006.231.08:07:59.87#ibcon#read 4, iclass 20, count 0 2006.231.08:07:59.87#ibcon#about to read 5, iclass 20, count 0 2006.231.08:07:59.87#ibcon#read 5, iclass 20, count 0 2006.231.08:07:59.87#ibcon#about to read 6, iclass 20, count 0 2006.231.08:07:59.87#ibcon#read 6, iclass 20, count 0 2006.231.08:07:59.87#ibcon#end of sib2, iclass 20, count 0 2006.231.08:07:59.87#ibcon#*mode == 0, iclass 20, count 0 2006.231.08:07:59.87#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.08:07:59.87#ibcon#[25=USB\r\n] 2006.231.08:07:59.87#ibcon#*before write, iclass 20, count 0 2006.231.08:07:59.87#ibcon#enter sib2, iclass 20, count 0 2006.231.08:07:59.87#ibcon#flushed, iclass 20, count 0 2006.231.08:07:59.87#ibcon#about to write, iclass 20, count 0 2006.231.08:07:59.87#ibcon#wrote, iclass 20, count 0 2006.231.08:07:59.87#ibcon#about to read 3, iclass 20, count 0 2006.231.08:07:59.90#ibcon#read 3, iclass 20, count 0 2006.231.08:07:59.90#ibcon#about to read 4, iclass 20, count 0 2006.231.08:07:59.90#ibcon#read 4, iclass 20, count 0 2006.231.08:07:59.90#ibcon#about to read 5, iclass 20, count 0 2006.231.08:07:59.90#ibcon#read 5, iclass 20, count 0 2006.231.08:07:59.90#ibcon#about to read 6, iclass 20, count 0 2006.231.08:07:59.90#ibcon#read 6, iclass 20, count 0 2006.231.08:07:59.90#ibcon#end of sib2, iclass 20, count 0 2006.231.08:07:59.90#ibcon#*after write, iclass 20, count 0 2006.231.08:07:59.90#ibcon#*before return 0, iclass 20, count 0 2006.231.08:07:59.90#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:07:59.90#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:07:59.90#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.08:07:59.90#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.08:07:59.90$vc4f8/valo=7,832.99 2006.231.08:07:59.90#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.08:07:59.90#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.08:07:59.90#ibcon#ireg 17 cls_cnt 0 2006.231.08:07:59.90#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:07:59.90#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:07:59.90#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:07:59.90#ibcon#enter wrdev, iclass 22, count 0 2006.231.08:07:59.90#ibcon#first serial, iclass 22, count 0 2006.231.08:07:59.90#ibcon#enter sib2, iclass 22, count 0 2006.231.08:07:59.90#ibcon#flushed, iclass 22, count 0 2006.231.08:07:59.90#ibcon#about to write, iclass 22, count 0 2006.231.08:07:59.90#ibcon#wrote, iclass 22, count 0 2006.231.08:07:59.90#ibcon#about to read 3, iclass 22, count 0 2006.231.08:07:59.92#ibcon#read 3, iclass 22, count 0 2006.231.08:07:59.92#ibcon#about to read 4, iclass 22, count 0 2006.231.08:07:59.92#ibcon#read 4, iclass 22, count 0 2006.231.08:07:59.92#ibcon#about to read 5, iclass 22, count 0 2006.231.08:07:59.92#ibcon#read 5, iclass 22, count 0 2006.231.08:07:59.92#ibcon#about to read 6, iclass 22, count 0 2006.231.08:07:59.92#ibcon#read 6, iclass 22, count 0 2006.231.08:07:59.92#ibcon#end of sib2, iclass 22, count 0 2006.231.08:07:59.92#ibcon#*mode == 0, iclass 22, count 0 2006.231.08:07:59.92#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.08:07:59.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:07:59.92#ibcon#*before write, iclass 22, count 0 2006.231.08:07:59.92#ibcon#enter sib2, iclass 22, count 0 2006.231.08:07:59.92#ibcon#flushed, iclass 22, count 0 2006.231.08:07:59.92#ibcon#about to write, iclass 22, count 0 2006.231.08:07:59.92#ibcon#wrote, iclass 22, count 0 2006.231.08:07:59.92#ibcon#about to read 3, iclass 22, count 0 2006.231.08:07:59.96#ibcon#read 3, iclass 22, count 0 2006.231.08:07:59.96#ibcon#about to read 4, iclass 22, count 0 2006.231.08:07:59.96#ibcon#read 4, iclass 22, count 0 2006.231.08:07:59.96#ibcon#about to read 5, iclass 22, count 0 2006.231.08:07:59.96#ibcon#read 5, iclass 22, count 0 2006.231.08:07:59.96#ibcon#about to read 6, iclass 22, count 0 2006.231.08:07:59.96#ibcon#read 6, iclass 22, count 0 2006.231.08:07:59.96#ibcon#end of sib2, iclass 22, count 0 2006.231.08:07:59.96#ibcon#*after write, iclass 22, count 0 2006.231.08:07:59.96#ibcon#*before return 0, iclass 22, count 0 2006.231.08:07:59.96#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:07:59.96#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:07:59.96#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.08:07:59.96#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.08:07:59.96$vc4f8/va=7,6 2006.231.08:07:59.96#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.08:07:59.96#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.08:07:59.96#ibcon#ireg 11 cls_cnt 2 2006.231.08:07:59.96#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:08:00.02#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:08:00.02#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:08:00.02#ibcon#enter wrdev, iclass 24, count 2 2006.231.08:08:00.02#ibcon#first serial, iclass 24, count 2 2006.231.08:08:00.02#ibcon#enter sib2, iclass 24, count 2 2006.231.08:08:00.02#ibcon#flushed, iclass 24, count 2 2006.231.08:08:00.02#ibcon#about to write, iclass 24, count 2 2006.231.08:08:00.02#ibcon#wrote, iclass 24, count 2 2006.231.08:08:00.02#ibcon#about to read 3, iclass 24, count 2 2006.231.08:08:00.03#abcon#<5=/06 3.1 6.8 30.49 851004.5\r\n> 2006.231.08:08:00.04#ibcon#read 3, iclass 24, count 2 2006.231.08:08:00.04#ibcon#about to read 4, iclass 24, count 2 2006.231.08:08:00.04#ibcon#read 4, iclass 24, count 2 2006.231.08:08:00.04#ibcon#about to read 5, iclass 24, count 2 2006.231.08:08:00.04#ibcon#read 5, iclass 24, count 2 2006.231.08:08:00.04#ibcon#about to read 6, iclass 24, count 2 2006.231.08:08:00.04#ibcon#read 6, iclass 24, count 2 2006.231.08:08:00.04#ibcon#end of sib2, iclass 24, count 2 2006.231.08:08:00.04#ibcon#*mode == 0, iclass 24, count 2 2006.231.08:08:00.04#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.08:08:00.04#ibcon#[25=AT07-06\r\n] 2006.231.08:08:00.04#ibcon#*before write, iclass 24, count 2 2006.231.08:08:00.04#ibcon#enter sib2, iclass 24, count 2 2006.231.08:08:00.04#ibcon#flushed, iclass 24, count 2 2006.231.08:08:00.04#ibcon#about to write, iclass 24, count 2 2006.231.08:08:00.04#ibcon#wrote, iclass 24, count 2 2006.231.08:08:00.04#ibcon#about to read 3, iclass 24, count 2 2006.231.08:08:00.05#abcon#{5=INTERFACE CLEAR} 2006.231.08:08:00.07#ibcon#read 3, iclass 24, count 2 2006.231.08:08:00.07#ibcon#about to read 4, iclass 24, count 2 2006.231.08:08:00.07#ibcon#read 4, iclass 24, count 2 2006.231.08:08:00.07#ibcon#about to read 5, iclass 24, count 2 2006.231.08:08:00.07#ibcon#read 5, iclass 24, count 2 2006.231.08:08:00.07#ibcon#about to read 6, iclass 24, count 2 2006.231.08:08:00.07#ibcon#read 6, iclass 24, count 2 2006.231.08:08:00.07#ibcon#end of sib2, iclass 24, count 2 2006.231.08:08:00.07#ibcon#*after write, iclass 24, count 2 2006.231.08:08:00.07#ibcon#*before return 0, iclass 24, count 2 2006.231.08:08:00.07#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:08:00.07#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:08:00.07#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.08:08:00.07#ibcon#ireg 7 cls_cnt 0 2006.231.08:08:00.07#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:08:00.11#abcon#[5=S1D000X0/0*\r\n] 2006.231.08:08:00.19#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:08:00.19#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:08:00.19#ibcon#enter wrdev, iclass 24, count 0 2006.231.08:08:00.19#ibcon#first serial, iclass 24, count 0 2006.231.08:08:00.19#ibcon#enter sib2, iclass 24, count 0 2006.231.08:08:00.19#ibcon#flushed, iclass 24, count 0 2006.231.08:08:00.19#ibcon#about to write, iclass 24, count 0 2006.231.08:08:00.19#ibcon#wrote, iclass 24, count 0 2006.231.08:08:00.19#ibcon#about to read 3, iclass 24, count 0 2006.231.08:08:00.21#ibcon#read 3, iclass 24, count 0 2006.231.08:08:00.21#ibcon#about to read 4, iclass 24, count 0 2006.231.08:08:00.21#ibcon#read 4, iclass 24, count 0 2006.231.08:08:00.21#ibcon#about to read 5, iclass 24, count 0 2006.231.08:08:00.21#ibcon#read 5, iclass 24, count 0 2006.231.08:08:00.21#ibcon#about to read 6, iclass 24, count 0 2006.231.08:08:00.21#ibcon#read 6, iclass 24, count 0 2006.231.08:08:00.21#ibcon#end of sib2, iclass 24, count 0 2006.231.08:08:00.21#ibcon#*mode == 0, iclass 24, count 0 2006.231.08:08:00.21#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.08:08:00.21#ibcon#[25=USB\r\n] 2006.231.08:08:00.21#ibcon#*before write, iclass 24, count 0 2006.231.08:08:00.21#ibcon#enter sib2, iclass 24, count 0 2006.231.08:08:00.21#ibcon#flushed, iclass 24, count 0 2006.231.08:08:00.21#ibcon#about to write, iclass 24, count 0 2006.231.08:08:00.21#ibcon#wrote, iclass 24, count 0 2006.231.08:08:00.21#ibcon#about to read 3, iclass 24, count 0 2006.231.08:08:00.24#ibcon#read 3, iclass 24, count 0 2006.231.08:08:00.24#ibcon#about to read 4, iclass 24, count 0 2006.231.08:08:00.24#ibcon#read 4, iclass 24, count 0 2006.231.08:08:00.24#ibcon#about to read 5, iclass 24, count 0 2006.231.08:08:00.24#ibcon#read 5, iclass 24, count 0 2006.231.08:08:00.24#ibcon#about to read 6, iclass 24, count 0 2006.231.08:08:00.24#ibcon#read 6, iclass 24, count 0 2006.231.08:08:00.24#ibcon#end of sib2, iclass 24, count 0 2006.231.08:08:00.24#ibcon#*after write, iclass 24, count 0 2006.231.08:08:00.24#ibcon#*before return 0, iclass 24, count 0 2006.231.08:08:00.24#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:08:00.24#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:08:00.24#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.08:08:00.24#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.08:08:00.24$vc4f8/valo=8,852.99 2006.231.08:08:00.24#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.08:08:00.24#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.08:08:00.24#ibcon#ireg 17 cls_cnt 0 2006.231.08:08:00.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:08:00.24#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:08:00.24#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:08:00.24#ibcon#enter wrdev, iclass 30, count 0 2006.231.08:08:00.24#ibcon#first serial, iclass 30, count 0 2006.231.08:08:00.24#ibcon#enter sib2, iclass 30, count 0 2006.231.08:08:00.24#ibcon#flushed, iclass 30, count 0 2006.231.08:08:00.24#ibcon#about to write, iclass 30, count 0 2006.231.08:08:00.24#ibcon#wrote, iclass 30, count 0 2006.231.08:08:00.24#ibcon#about to read 3, iclass 30, count 0 2006.231.08:08:00.26#ibcon#read 3, iclass 30, count 0 2006.231.08:08:00.26#ibcon#about to read 4, iclass 30, count 0 2006.231.08:08:00.26#ibcon#read 4, iclass 30, count 0 2006.231.08:08:00.26#ibcon#about to read 5, iclass 30, count 0 2006.231.08:08:00.26#ibcon#read 5, iclass 30, count 0 2006.231.08:08:00.26#ibcon#about to read 6, iclass 30, count 0 2006.231.08:08:00.26#ibcon#read 6, iclass 30, count 0 2006.231.08:08:00.26#ibcon#end of sib2, iclass 30, count 0 2006.231.08:08:00.26#ibcon#*mode == 0, iclass 30, count 0 2006.231.08:08:00.26#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.08:08:00.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:08:00.26#ibcon#*before write, iclass 30, count 0 2006.231.08:08:00.26#ibcon#enter sib2, iclass 30, count 0 2006.231.08:08:00.26#ibcon#flushed, iclass 30, count 0 2006.231.08:08:00.26#ibcon#about to write, iclass 30, count 0 2006.231.08:08:00.26#ibcon#wrote, iclass 30, count 0 2006.231.08:08:00.26#ibcon#about to read 3, iclass 30, count 0 2006.231.08:08:00.30#ibcon#read 3, iclass 30, count 0 2006.231.08:08:00.30#ibcon#about to read 4, iclass 30, count 0 2006.231.08:08:00.30#ibcon#read 4, iclass 30, count 0 2006.231.08:08:00.30#ibcon#about to read 5, iclass 30, count 0 2006.231.08:08:00.30#ibcon#read 5, iclass 30, count 0 2006.231.08:08:00.30#ibcon#about to read 6, iclass 30, count 0 2006.231.08:08:00.30#ibcon#read 6, iclass 30, count 0 2006.231.08:08:00.30#ibcon#end of sib2, iclass 30, count 0 2006.231.08:08:00.30#ibcon#*after write, iclass 30, count 0 2006.231.08:08:00.30#ibcon#*before return 0, iclass 30, count 0 2006.231.08:08:00.30#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:08:00.30#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:08:00.30#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.08:08:00.30#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.08:08:00.30$vc4f8/va=8,6 2006.231.08:08:00.30#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.08:08:00.30#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.08:08:00.30#ibcon#ireg 11 cls_cnt 2 2006.231.08:08:00.30#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:08:00.36#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:08:00.36#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:08:00.36#ibcon#enter wrdev, iclass 32, count 2 2006.231.08:08:00.36#ibcon#first serial, iclass 32, count 2 2006.231.08:08:00.36#ibcon#enter sib2, iclass 32, count 2 2006.231.08:08:00.36#ibcon#flushed, iclass 32, count 2 2006.231.08:08:00.36#ibcon#about to write, iclass 32, count 2 2006.231.08:08:00.36#ibcon#wrote, iclass 32, count 2 2006.231.08:08:00.36#ibcon#about to read 3, iclass 32, count 2 2006.231.08:08:00.38#ibcon#read 3, iclass 32, count 2 2006.231.08:08:00.38#ibcon#about to read 4, iclass 32, count 2 2006.231.08:08:00.38#ibcon#read 4, iclass 32, count 2 2006.231.08:08:00.38#ibcon#about to read 5, iclass 32, count 2 2006.231.08:08:00.38#ibcon#read 5, iclass 32, count 2 2006.231.08:08:00.38#ibcon#about to read 6, iclass 32, count 2 2006.231.08:08:00.38#ibcon#read 6, iclass 32, count 2 2006.231.08:08:00.38#ibcon#end of sib2, iclass 32, count 2 2006.231.08:08:00.38#ibcon#*mode == 0, iclass 32, count 2 2006.231.08:08:00.38#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.08:08:00.38#ibcon#[25=AT08-06\r\n] 2006.231.08:08:00.38#ibcon#*before write, iclass 32, count 2 2006.231.08:08:00.38#ibcon#enter sib2, iclass 32, count 2 2006.231.08:08:00.38#ibcon#flushed, iclass 32, count 2 2006.231.08:08:00.38#ibcon#about to write, iclass 32, count 2 2006.231.08:08:00.38#ibcon#wrote, iclass 32, count 2 2006.231.08:08:00.38#ibcon#about to read 3, iclass 32, count 2 2006.231.08:08:00.41#ibcon#read 3, iclass 32, count 2 2006.231.08:08:00.41#ibcon#about to read 4, iclass 32, count 2 2006.231.08:08:00.41#ibcon#read 4, iclass 32, count 2 2006.231.08:08:00.41#ibcon#about to read 5, iclass 32, count 2 2006.231.08:08:00.41#ibcon#read 5, iclass 32, count 2 2006.231.08:08:00.41#ibcon#about to read 6, iclass 32, count 2 2006.231.08:08:00.41#ibcon#read 6, iclass 32, count 2 2006.231.08:08:00.41#ibcon#end of sib2, iclass 32, count 2 2006.231.08:08:00.41#ibcon#*after write, iclass 32, count 2 2006.231.08:08:00.41#ibcon#*before return 0, iclass 32, count 2 2006.231.08:08:00.41#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:08:00.41#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:08:00.41#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.08:08:00.41#ibcon#ireg 7 cls_cnt 0 2006.231.08:08:00.41#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:08:00.53#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:08:00.53#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:08:00.53#ibcon#enter wrdev, iclass 32, count 0 2006.231.08:08:00.53#ibcon#first serial, iclass 32, count 0 2006.231.08:08:00.53#ibcon#enter sib2, iclass 32, count 0 2006.231.08:08:00.53#ibcon#flushed, iclass 32, count 0 2006.231.08:08:00.53#ibcon#about to write, iclass 32, count 0 2006.231.08:08:00.53#ibcon#wrote, iclass 32, count 0 2006.231.08:08:00.53#ibcon#about to read 3, iclass 32, count 0 2006.231.08:08:00.55#ibcon#read 3, iclass 32, count 0 2006.231.08:08:00.55#ibcon#about to read 4, iclass 32, count 0 2006.231.08:08:00.55#ibcon#read 4, iclass 32, count 0 2006.231.08:08:00.55#ibcon#about to read 5, iclass 32, count 0 2006.231.08:08:00.55#ibcon#read 5, iclass 32, count 0 2006.231.08:08:00.55#ibcon#about to read 6, iclass 32, count 0 2006.231.08:08:00.55#ibcon#read 6, iclass 32, count 0 2006.231.08:08:00.55#ibcon#end of sib2, iclass 32, count 0 2006.231.08:08:00.55#ibcon#*mode == 0, iclass 32, count 0 2006.231.08:08:00.55#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.08:08:00.55#ibcon#[25=USB\r\n] 2006.231.08:08:00.55#ibcon#*before write, iclass 32, count 0 2006.231.08:08:00.55#ibcon#enter sib2, iclass 32, count 0 2006.231.08:08:00.55#ibcon#flushed, iclass 32, count 0 2006.231.08:08:00.55#ibcon#about to write, iclass 32, count 0 2006.231.08:08:00.55#ibcon#wrote, iclass 32, count 0 2006.231.08:08:00.55#ibcon#about to read 3, iclass 32, count 0 2006.231.08:08:00.58#ibcon#read 3, iclass 32, count 0 2006.231.08:08:00.58#ibcon#about to read 4, iclass 32, count 0 2006.231.08:08:00.58#ibcon#read 4, iclass 32, count 0 2006.231.08:08:00.58#ibcon#about to read 5, iclass 32, count 0 2006.231.08:08:00.58#ibcon#read 5, iclass 32, count 0 2006.231.08:08:00.58#ibcon#about to read 6, iclass 32, count 0 2006.231.08:08:00.58#ibcon#read 6, iclass 32, count 0 2006.231.08:08:00.58#ibcon#end of sib2, iclass 32, count 0 2006.231.08:08:00.58#ibcon#*after write, iclass 32, count 0 2006.231.08:08:00.58#ibcon#*before return 0, iclass 32, count 0 2006.231.08:08:00.58#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:08:00.58#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:08:00.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.08:08:00.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.08:08:00.58$vc4f8/vblo=1,632.99 2006.231.08:08:00.58#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.08:08:00.58#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.08:08:00.58#ibcon#ireg 17 cls_cnt 0 2006.231.08:08:00.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:08:00.58#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:08:00.58#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:08:00.58#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:08:00.58#ibcon#first serial, iclass 34, count 0 2006.231.08:08:00.58#ibcon#enter sib2, iclass 34, count 0 2006.231.08:08:00.58#ibcon#flushed, iclass 34, count 0 2006.231.08:08:00.58#ibcon#about to write, iclass 34, count 0 2006.231.08:08:00.58#ibcon#wrote, iclass 34, count 0 2006.231.08:08:00.58#ibcon#about to read 3, iclass 34, count 0 2006.231.08:08:00.60#ibcon#read 3, iclass 34, count 0 2006.231.08:08:00.60#ibcon#about to read 4, iclass 34, count 0 2006.231.08:08:00.60#ibcon#read 4, iclass 34, count 0 2006.231.08:08:00.60#ibcon#about to read 5, iclass 34, count 0 2006.231.08:08:00.60#ibcon#read 5, iclass 34, count 0 2006.231.08:08:00.60#ibcon#about to read 6, iclass 34, count 0 2006.231.08:08:00.60#ibcon#read 6, iclass 34, count 0 2006.231.08:08:00.60#ibcon#end of sib2, iclass 34, count 0 2006.231.08:08:00.60#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:08:00.60#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:08:00.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:08:00.60#ibcon#*before write, iclass 34, count 0 2006.231.08:08:00.60#ibcon#enter sib2, iclass 34, count 0 2006.231.08:08:00.60#ibcon#flushed, iclass 34, count 0 2006.231.08:08:00.60#ibcon#about to write, iclass 34, count 0 2006.231.08:08:00.60#ibcon#wrote, iclass 34, count 0 2006.231.08:08:00.60#ibcon#about to read 3, iclass 34, count 0 2006.231.08:08:00.64#ibcon#read 3, iclass 34, count 0 2006.231.08:08:00.64#ibcon#about to read 4, iclass 34, count 0 2006.231.08:08:00.64#ibcon#read 4, iclass 34, count 0 2006.231.08:08:00.64#ibcon#about to read 5, iclass 34, count 0 2006.231.08:08:00.64#ibcon#read 5, iclass 34, count 0 2006.231.08:08:00.64#ibcon#about to read 6, iclass 34, count 0 2006.231.08:08:00.64#ibcon#read 6, iclass 34, count 0 2006.231.08:08:00.64#ibcon#end of sib2, iclass 34, count 0 2006.231.08:08:00.64#ibcon#*after write, iclass 34, count 0 2006.231.08:08:00.64#ibcon#*before return 0, iclass 34, count 0 2006.231.08:08:00.64#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:08:00.64#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:08:00.64#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:08:00.64#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:08:00.64$vc4f8/vb=1,4 2006.231.08:08:00.64#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.08:08:00.64#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.08:08:00.64#ibcon#ireg 11 cls_cnt 2 2006.231.08:08:00.64#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:08:00.64#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:08:00.64#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:08:00.64#ibcon#enter wrdev, iclass 36, count 2 2006.231.08:08:00.64#ibcon#first serial, iclass 36, count 2 2006.231.08:08:00.64#ibcon#enter sib2, iclass 36, count 2 2006.231.08:08:00.64#ibcon#flushed, iclass 36, count 2 2006.231.08:08:00.64#ibcon#about to write, iclass 36, count 2 2006.231.08:08:00.64#ibcon#wrote, iclass 36, count 2 2006.231.08:08:00.64#ibcon#about to read 3, iclass 36, count 2 2006.231.08:08:00.66#ibcon#read 3, iclass 36, count 2 2006.231.08:08:00.66#ibcon#about to read 4, iclass 36, count 2 2006.231.08:08:00.66#ibcon#read 4, iclass 36, count 2 2006.231.08:08:00.66#ibcon#about to read 5, iclass 36, count 2 2006.231.08:08:00.66#ibcon#read 5, iclass 36, count 2 2006.231.08:08:00.66#ibcon#about to read 6, iclass 36, count 2 2006.231.08:08:00.66#ibcon#read 6, iclass 36, count 2 2006.231.08:08:00.66#ibcon#end of sib2, iclass 36, count 2 2006.231.08:08:00.66#ibcon#*mode == 0, iclass 36, count 2 2006.231.08:08:00.66#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.08:08:00.66#ibcon#[27=AT01-04\r\n] 2006.231.08:08:00.66#ibcon#*before write, iclass 36, count 2 2006.231.08:08:00.66#ibcon#enter sib2, iclass 36, count 2 2006.231.08:08:00.66#ibcon#flushed, iclass 36, count 2 2006.231.08:08:00.66#ibcon#about to write, iclass 36, count 2 2006.231.08:08:00.66#ibcon#wrote, iclass 36, count 2 2006.231.08:08:00.66#ibcon#about to read 3, iclass 36, count 2 2006.231.08:08:00.69#ibcon#read 3, iclass 36, count 2 2006.231.08:08:00.69#ibcon#about to read 4, iclass 36, count 2 2006.231.08:08:00.69#ibcon#read 4, iclass 36, count 2 2006.231.08:08:00.69#ibcon#about to read 5, iclass 36, count 2 2006.231.08:08:00.69#ibcon#read 5, iclass 36, count 2 2006.231.08:08:00.69#ibcon#about to read 6, iclass 36, count 2 2006.231.08:08:00.69#ibcon#read 6, iclass 36, count 2 2006.231.08:08:00.69#ibcon#end of sib2, iclass 36, count 2 2006.231.08:08:00.69#ibcon#*after write, iclass 36, count 2 2006.231.08:08:00.69#ibcon#*before return 0, iclass 36, count 2 2006.231.08:08:00.69#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:08:00.69#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:08:00.69#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.08:08:00.69#ibcon#ireg 7 cls_cnt 0 2006.231.08:08:00.69#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:08:00.81#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:08:00.81#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:08:00.81#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:08:00.81#ibcon#first serial, iclass 36, count 0 2006.231.08:08:00.81#ibcon#enter sib2, iclass 36, count 0 2006.231.08:08:00.81#ibcon#flushed, iclass 36, count 0 2006.231.08:08:00.81#ibcon#about to write, iclass 36, count 0 2006.231.08:08:00.81#ibcon#wrote, iclass 36, count 0 2006.231.08:08:00.81#ibcon#about to read 3, iclass 36, count 0 2006.231.08:08:00.83#ibcon#read 3, iclass 36, count 0 2006.231.08:08:00.83#ibcon#about to read 4, iclass 36, count 0 2006.231.08:08:00.83#ibcon#read 4, iclass 36, count 0 2006.231.08:08:00.83#ibcon#about to read 5, iclass 36, count 0 2006.231.08:08:00.83#ibcon#read 5, iclass 36, count 0 2006.231.08:08:00.83#ibcon#about to read 6, iclass 36, count 0 2006.231.08:08:00.83#ibcon#read 6, iclass 36, count 0 2006.231.08:08:00.83#ibcon#end of sib2, iclass 36, count 0 2006.231.08:08:00.83#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:08:00.83#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:08:00.83#ibcon#[27=USB\r\n] 2006.231.08:08:00.83#ibcon#*before write, iclass 36, count 0 2006.231.08:08:00.83#ibcon#enter sib2, iclass 36, count 0 2006.231.08:08:00.83#ibcon#flushed, iclass 36, count 0 2006.231.08:08:00.83#ibcon#about to write, iclass 36, count 0 2006.231.08:08:00.83#ibcon#wrote, iclass 36, count 0 2006.231.08:08:00.83#ibcon#about to read 3, iclass 36, count 0 2006.231.08:08:00.86#ibcon#read 3, iclass 36, count 0 2006.231.08:08:00.86#ibcon#about to read 4, iclass 36, count 0 2006.231.08:08:00.86#ibcon#read 4, iclass 36, count 0 2006.231.08:08:00.86#ibcon#about to read 5, iclass 36, count 0 2006.231.08:08:00.86#ibcon#read 5, iclass 36, count 0 2006.231.08:08:00.86#ibcon#about to read 6, iclass 36, count 0 2006.231.08:08:00.86#ibcon#read 6, iclass 36, count 0 2006.231.08:08:00.86#ibcon#end of sib2, iclass 36, count 0 2006.231.08:08:00.86#ibcon#*after write, iclass 36, count 0 2006.231.08:08:00.86#ibcon#*before return 0, iclass 36, count 0 2006.231.08:08:00.86#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:08:00.86#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:08:00.86#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:08:00.86#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:08:00.86$vc4f8/vblo=2,640.99 2006.231.08:08:00.86#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.08:08:00.86#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.08:08:00.86#ibcon#ireg 17 cls_cnt 0 2006.231.08:08:00.86#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:08:00.86#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:08:00.86#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:08:00.86#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:08:00.86#ibcon#first serial, iclass 38, count 0 2006.231.08:08:00.86#ibcon#enter sib2, iclass 38, count 0 2006.231.08:08:00.86#ibcon#flushed, iclass 38, count 0 2006.231.08:08:00.86#ibcon#about to write, iclass 38, count 0 2006.231.08:08:00.86#ibcon#wrote, iclass 38, count 0 2006.231.08:08:00.86#ibcon#about to read 3, iclass 38, count 0 2006.231.08:08:00.88#ibcon#read 3, iclass 38, count 0 2006.231.08:08:00.88#ibcon#about to read 4, iclass 38, count 0 2006.231.08:08:00.88#ibcon#read 4, iclass 38, count 0 2006.231.08:08:00.88#ibcon#about to read 5, iclass 38, count 0 2006.231.08:08:00.88#ibcon#read 5, iclass 38, count 0 2006.231.08:08:00.88#ibcon#about to read 6, iclass 38, count 0 2006.231.08:08:00.88#ibcon#read 6, iclass 38, count 0 2006.231.08:08:00.88#ibcon#end of sib2, iclass 38, count 0 2006.231.08:08:00.88#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:08:00.88#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:08:00.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:08:00.88#ibcon#*before write, iclass 38, count 0 2006.231.08:08:00.88#ibcon#enter sib2, iclass 38, count 0 2006.231.08:08:00.88#ibcon#flushed, iclass 38, count 0 2006.231.08:08:00.88#ibcon#about to write, iclass 38, count 0 2006.231.08:08:00.88#ibcon#wrote, iclass 38, count 0 2006.231.08:08:00.88#ibcon#about to read 3, iclass 38, count 0 2006.231.08:08:00.92#ibcon#read 3, iclass 38, count 0 2006.231.08:08:00.92#ibcon#about to read 4, iclass 38, count 0 2006.231.08:08:00.92#ibcon#read 4, iclass 38, count 0 2006.231.08:08:00.92#ibcon#about to read 5, iclass 38, count 0 2006.231.08:08:00.92#ibcon#read 5, iclass 38, count 0 2006.231.08:08:00.92#ibcon#about to read 6, iclass 38, count 0 2006.231.08:08:00.92#ibcon#read 6, iclass 38, count 0 2006.231.08:08:00.92#ibcon#end of sib2, iclass 38, count 0 2006.231.08:08:00.92#ibcon#*after write, iclass 38, count 0 2006.231.08:08:00.92#ibcon#*before return 0, iclass 38, count 0 2006.231.08:08:00.92#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:08:00.92#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:08:00.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:08:00.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:08:00.92$vc4f8/vb=2,4 2006.231.08:08:00.92#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.08:08:00.92#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.08:08:00.92#ibcon#ireg 11 cls_cnt 2 2006.231.08:08:00.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:08:00.98#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:08:00.98#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:08:00.98#ibcon#enter wrdev, iclass 40, count 2 2006.231.08:08:00.98#ibcon#first serial, iclass 40, count 2 2006.231.08:08:00.98#ibcon#enter sib2, iclass 40, count 2 2006.231.08:08:00.98#ibcon#flushed, iclass 40, count 2 2006.231.08:08:00.98#ibcon#about to write, iclass 40, count 2 2006.231.08:08:00.98#ibcon#wrote, iclass 40, count 2 2006.231.08:08:00.98#ibcon#about to read 3, iclass 40, count 2 2006.231.08:08:01.00#ibcon#read 3, iclass 40, count 2 2006.231.08:08:01.00#ibcon#about to read 4, iclass 40, count 2 2006.231.08:08:01.00#ibcon#read 4, iclass 40, count 2 2006.231.08:08:01.00#ibcon#about to read 5, iclass 40, count 2 2006.231.08:08:01.00#ibcon#read 5, iclass 40, count 2 2006.231.08:08:01.00#ibcon#about to read 6, iclass 40, count 2 2006.231.08:08:01.00#ibcon#read 6, iclass 40, count 2 2006.231.08:08:01.00#ibcon#end of sib2, iclass 40, count 2 2006.231.08:08:01.00#ibcon#*mode == 0, iclass 40, count 2 2006.231.08:08:01.00#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.08:08:01.00#ibcon#[27=AT02-04\r\n] 2006.231.08:08:01.00#ibcon#*before write, iclass 40, count 2 2006.231.08:08:01.00#ibcon#enter sib2, iclass 40, count 2 2006.231.08:08:01.00#ibcon#flushed, iclass 40, count 2 2006.231.08:08:01.00#ibcon#about to write, iclass 40, count 2 2006.231.08:08:01.00#ibcon#wrote, iclass 40, count 2 2006.231.08:08:01.00#ibcon#about to read 3, iclass 40, count 2 2006.231.08:08:01.03#ibcon#read 3, iclass 40, count 2 2006.231.08:08:01.03#ibcon#about to read 4, iclass 40, count 2 2006.231.08:08:01.03#ibcon#read 4, iclass 40, count 2 2006.231.08:08:01.03#ibcon#about to read 5, iclass 40, count 2 2006.231.08:08:01.03#ibcon#read 5, iclass 40, count 2 2006.231.08:08:01.03#ibcon#about to read 6, iclass 40, count 2 2006.231.08:08:01.03#ibcon#read 6, iclass 40, count 2 2006.231.08:08:01.03#ibcon#end of sib2, iclass 40, count 2 2006.231.08:08:01.03#ibcon#*after write, iclass 40, count 2 2006.231.08:08:01.03#ibcon#*before return 0, iclass 40, count 2 2006.231.08:08:01.03#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:08:01.03#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:08:01.03#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.08:08:01.03#ibcon#ireg 7 cls_cnt 0 2006.231.08:08:01.03#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:08:01.15#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:08:01.15#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:08:01.15#ibcon#enter wrdev, iclass 40, count 0 2006.231.08:08:01.15#ibcon#first serial, iclass 40, count 0 2006.231.08:08:01.15#ibcon#enter sib2, iclass 40, count 0 2006.231.08:08:01.15#ibcon#flushed, iclass 40, count 0 2006.231.08:08:01.15#ibcon#about to write, iclass 40, count 0 2006.231.08:08:01.15#ibcon#wrote, iclass 40, count 0 2006.231.08:08:01.15#ibcon#about to read 3, iclass 40, count 0 2006.231.08:08:01.17#ibcon#read 3, iclass 40, count 0 2006.231.08:08:01.17#ibcon#about to read 4, iclass 40, count 0 2006.231.08:08:01.17#ibcon#read 4, iclass 40, count 0 2006.231.08:08:01.17#ibcon#about to read 5, iclass 40, count 0 2006.231.08:08:01.17#ibcon#read 5, iclass 40, count 0 2006.231.08:08:01.17#ibcon#about to read 6, iclass 40, count 0 2006.231.08:08:01.17#ibcon#read 6, iclass 40, count 0 2006.231.08:08:01.17#ibcon#end of sib2, iclass 40, count 0 2006.231.08:08:01.17#ibcon#*mode == 0, iclass 40, count 0 2006.231.08:08:01.17#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.08:08:01.17#ibcon#[27=USB\r\n] 2006.231.08:08:01.17#ibcon#*before write, iclass 40, count 0 2006.231.08:08:01.17#ibcon#enter sib2, iclass 40, count 0 2006.231.08:08:01.17#ibcon#flushed, iclass 40, count 0 2006.231.08:08:01.17#ibcon#about to write, iclass 40, count 0 2006.231.08:08:01.17#ibcon#wrote, iclass 40, count 0 2006.231.08:08:01.17#ibcon#about to read 3, iclass 40, count 0 2006.231.08:08:01.21#ibcon#read 3, iclass 40, count 0 2006.231.08:08:01.21#ibcon#about to read 4, iclass 40, count 0 2006.231.08:08:01.21#ibcon#read 4, iclass 40, count 0 2006.231.08:08:01.21#ibcon#about to read 5, iclass 40, count 0 2006.231.08:08:01.21#ibcon#read 5, iclass 40, count 0 2006.231.08:08:01.21#ibcon#about to read 6, iclass 40, count 0 2006.231.08:08:01.21#ibcon#read 6, iclass 40, count 0 2006.231.08:08:01.21#ibcon#end of sib2, iclass 40, count 0 2006.231.08:08:01.21#ibcon#*after write, iclass 40, count 0 2006.231.08:08:01.21#ibcon#*before return 0, iclass 40, count 0 2006.231.08:08:01.21#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:08:01.21#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:08:01.21#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.08:08:01.21#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.08:08:01.21$vc4f8/vblo=3,656.99 2006.231.08:08:01.21#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.08:08:01.21#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.08:08:01.21#ibcon#ireg 17 cls_cnt 0 2006.231.08:08:01.21#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:08:01.21#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:08:01.21#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:08:01.21#ibcon#enter wrdev, iclass 4, count 0 2006.231.08:08:01.21#ibcon#first serial, iclass 4, count 0 2006.231.08:08:01.21#ibcon#enter sib2, iclass 4, count 0 2006.231.08:08:01.21#ibcon#flushed, iclass 4, count 0 2006.231.08:08:01.21#ibcon#about to write, iclass 4, count 0 2006.231.08:08:01.21#ibcon#wrote, iclass 4, count 0 2006.231.08:08:01.21#ibcon#about to read 3, iclass 4, count 0 2006.231.08:08:01.22#ibcon#read 3, iclass 4, count 0 2006.231.08:08:01.22#ibcon#about to read 4, iclass 4, count 0 2006.231.08:08:01.22#ibcon#read 4, iclass 4, count 0 2006.231.08:08:01.22#ibcon#about to read 5, iclass 4, count 0 2006.231.08:08:01.22#ibcon#read 5, iclass 4, count 0 2006.231.08:08:01.22#ibcon#about to read 6, iclass 4, count 0 2006.231.08:08:01.22#ibcon#read 6, iclass 4, count 0 2006.231.08:08:01.22#ibcon#end of sib2, iclass 4, count 0 2006.231.08:08:01.22#ibcon#*mode == 0, iclass 4, count 0 2006.231.08:08:01.22#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.08:08:01.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:08:01.22#ibcon#*before write, iclass 4, count 0 2006.231.08:08:01.22#ibcon#enter sib2, iclass 4, count 0 2006.231.08:08:01.22#ibcon#flushed, iclass 4, count 0 2006.231.08:08:01.22#ibcon#about to write, iclass 4, count 0 2006.231.08:08:01.22#ibcon#wrote, iclass 4, count 0 2006.231.08:08:01.22#ibcon#about to read 3, iclass 4, count 0 2006.231.08:08:01.26#ibcon#read 3, iclass 4, count 0 2006.231.08:08:01.26#ibcon#about to read 4, iclass 4, count 0 2006.231.08:08:01.26#ibcon#read 4, iclass 4, count 0 2006.231.08:08:01.26#ibcon#about to read 5, iclass 4, count 0 2006.231.08:08:01.26#ibcon#read 5, iclass 4, count 0 2006.231.08:08:01.26#ibcon#about to read 6, iclass 4, count 0 2006.231.08:08:01.26#ibcon#read 6, iclass 4, count 0 2006.231.08:08:01.26#ibcon#end of sib2, iclass 4, count 0 2006.231.08:08:01.26#ibcon#*after write, iclass 4, count 0 2006.231.08:08:01.26#ibcon#*before return 0, iclass 4, count 0 2006.231.08:08:01.26#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:08:01.26#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:08:01.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.08:08:01.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.08:08:01.26$vc4f8/vb=3,4 2006.231.08:08:01.26#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.08:08:01.26#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.08:08:01.26#ibcon#ireg 11 cls_cnt 2 2006.231.08:08:01.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:08:01.33#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:08:01.33#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:08:01.33#ibcon#enter wrdev, iclass 6, count 2 2006.231.08:08:01.33#ibcon#first serial, iclass 6, count 2 2006.231.08:08:01.33#ibcon#enter sib2, iclass 6, count 2 2006.231.08:08:01.33#ibcon#flushed, iclass 6, count 2 2006.231.08:08:01.33#ibcon#about to write, iclass 6, count 2 2006.231.08:08:01.33#ibcon#wrote, iclass 6, count 2 2006.231.08:08:01.33#ibcon#about to read 3, iclass 6, count 2 2006.231.08:08:01.35#ibcon#read 3, iclass 6, count 2 2006.231.08:08:01.35#ibcon#about to read 4, iclass 6, count 2 2006.231.08:08:01.35#ibcon#read 4, iclass 6, count 2 2006.231.08:08:01.35#ibcon#about to read 5, iclass 6, count 2 2006.231.08:08:01.35#ibcon#read 5, iclass 6, count 2 2006.231.08:08:01.35#ibcon#about to read 6, iclass 6, count 2 2006.231.08:08:01.35#ibcon#read 6, iclass 6, count 2 2006.231.08:08:01.35#ibcon#end of sib2, iclass 6, count 2 2006.231.08:08:01.35#ibcon#*mode == 0, iclass 6, count 2 2006.231.08:08:01.35#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.08:08:01.35#ibcon#[27=AT03-04\r\n] 2006.231.08:08:01.35#ibcon#*before write, iclass 6, count 2 2006.231.08:08:01.35#ibcon#enter sib2, iclass 6, count 2 2006.231.08:08:01.35#ibcon#flushed, iclass 6, count 2 2006.231.08:08:01.35#ibcon#about to write, iclass 6, count 2 2006.231.08:08:01.35#ibcon#wrote, iclass 6, count 2 2006.231.08:08:01.35#ibcon#about to read 3, iclass 6, count 2 2006.231.08:08:01.38#ibcon#read 3, iclass 6, count 2 2006.231.08:08:01.38#ibcon#about to read 4, iclass 6, count 2 2006.231.08:08:01.38#ibcon#read 4, iclass 6, count 2 2006.231.08:08:01.38#ibcon#about to read 5, iclass 6, count 2 2006.231.08:08:01.38#ibcon#read 5, iclass 6, count 2 2006.231.08:08:01.38#ibcon#about to read 6, iclass 6, count 2 2006.231.08:08:01.38#ibcon#read 6, iclass 6, count 2 2006.231.08:08:01.38#ibcon#end of sib2, iclass 6, count 2 2006.231.08:08:01.38#ibcon#*after write, iclass 6, count 2 2006.231.08:08:01.38#ibcon#*before return 0, iclass 6, count 2 2006.231.08:08:01.38#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:08:01.38#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:08:01.38#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.08:08:01.38#ibcon#ireg 7 cls_cnt 0 2006.231.08:08:01.38#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:08:01.50#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:08:01.50#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:08:01.50#ibcon#enter wrdev, iclass 6, count 0 2006.231.08:08:01.50#ibcon#first serial, iclass 6, count 0 2006.231.08:08:01.50#ibcon#enter sib2, iclass 6, count 0 2006.231.08:08:01.50#ibcon#flushed, iclass 6, count 0 2006.231.08:08:01.50#ibcon#about to write, iclass 6, count 0 2006.231.08:08:01.50#ibcon#wrote, iclass 6, count 0 2006.231.08:08:01.50#ibcon#about to read 3, iclass 6, count 0 2006.231.08:08:01.52#ibcon#read 3, iclass 6, count 0 2006.231.08:08:01.52#ibcon#about to read 4, iclass 6, count 0 2006.231.08:08:01.52#ibcon#read 4, iclass 6, count 0 2006.231.08:08:01.52#ibcon#about to read 5, iclass 6, count 0 2006.231.08:08:01.52#ibcon#read 5, iclass 6, count 0 2006.231.08:08:01.52#ibcon#about to read 6, iclass 6, count 0 2006.231.08:08:01.52#ibcon#read 6, iclass 6, count 0 2006.231.08:08:01.52#ibcon#end of sib2, iclass 6, count 0 2006.231.08:08:01.52#ibcon#*mode == 0, iclass 6, count 0 2006.231.08:08:01.52#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.08:08:01.52#ibcon#[27=USB\r\n] 2006.231.08:08:01.52#ibcon#*before write, iclass 6, count 0 2006.231.08:08:01.52#ibcon#enter sib2, iclass 6, count 0 2006.231.08:08:01.52#ibcon#flushed, iclass 6, count 0 2006.231.08:08:01.52#ibcon#about to write, iclass 6, count 0 2006.231.08:08:01.52#ibcon#wrote, iclass 6, count 0 2006.231.08:08:01.52#ibcon#about to read 3, iclass 6, count 0 2006.231.08:08:01.55#ibcon#read 3, iclass 6, count 0 2006.231.08:08:01.55#ibcon#about to read 4, iclass 6, count 0 2006.231.08:08:01.55#ibcon#read 4, iclass 6, count 0 2006.231.08:08:01.55#ibcon#about to read 5, iclass 6, count 0 2006.231.08:08:01.55#ibcon#read 5, iclass 6, count 0 2006.231.08:08:01.55#ibcon#about to read 6, iclass 6, count 0 2006.231.08:08:01.55#ibcon#read 6, iclass 6, count 0 2006.231.08:08:01.55#ibcon#end of sib2, iclass 6, count 0 2006.231.08:08:01.55#ibcon#*after write, iclass 6, count 0 2006.231.08:08:01.55#ibcon#*before return 0, iclass 6, count 0 2006.231.08:08:01.55#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:08:01.55#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:08:01.55#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.08:08:01.55#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.08:08:01.55$vc4f8/vblo=4,712.99 2006.231.08:08:01.55#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.08:08:01.55#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.08:08:01.55#ibcon#ireg 17 cls_cnt 0 2006.231.08:08:01.55#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:08:01.55#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:08:01.55#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:08:01.55#ibcon#enter wrdev, iclass 10, count 0 2006.231.08:08:01.55#ibcon#first serial, iclass 10, count 0 2006.231.08:08:01.55#ibcon#enter sib2, iclass 10, count 0 2006.231.08:08:01.55#ibcon#flushed, iclass 10, count 0 2006.231.08:08:01.55#ibcon#about to write, iclass 10, count 0 2006.231.08:08:01.55#ibcon#wrote, iclass 10, count 0 2006.231.08:08:01.55#ibcon#about to read 3, iclass 10, count 0 2006.231.08:08:01.57#ibcon#read 3, iclass 10, count 0 2006.231.08:08:01.57#ibcon#about to read 4, iclass 10, count 0 2006.231.08:08:01.57#ibcon#read 4, iclass 10, count 0 2006.231.08:08:01.57#ibcon#about to read 5, iclass 10, count 0 2006.231.08:08:01.57#ibcon#read 5, iclass 10, count 0 2006.231.08:08:01.57#ibcon#about to read 6, iclass 10, count 0 2006.231.08:08:01.57#ibcon#read 6, iclass 10, count 0 2006.231.08:08:01.57#ibcon#end of sib2, iclass 10, count 0 2006.231.08:08:01.57#ibcon#*mode == 0, iclass 10, count 0 2006.231.08:08:01.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.08:08:01.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:08:01.57#ibcon#*before write, iclass 10, count 0 2006.231.08:08:01.57#ibcon#enter sib2, iclass 10, count 0 2006.231.08:08:01.57#ibcon#flushed, iclass 10, count 0 2006.231.08:08:01.57#ibcon#about to write, iclass 10, count 0 2006.231.08:08:01.57#ibcon#wrote, iclass 10, count 0 2006.231.08:08:01.57#ibcon#about to read 3, iclass 10, count 0 2006.231.08:08:01.61#ibcon#read 3, iclass 10, count 0 2006.231.08:08:01.61#ibcon#about to read 4, iclass 10, count 0 2006.231.08:08:01.61#ibcon#read 4, iclass 10, count 0 2006.231.08:08:01.61#ibcon#about to read 5, iclass 10, count 0 2006.231.08:08:01.61#ibcon#read 5, iclass 10, count 0 2006.231.08:08:01.61#ibcon#about to read 6, iclass 10, count 0 2006.231.08:08:01.61#ibcon#read 6, iclass 10, count 0 2006.231.08:08:01.61#ibcon#end of sib2, iclass 10, count 0 2006.231.08:08:01.61#ibcon#*after write, iclass 10, count 0 2006.231.08:08:01.61#ibcon#*before return 0, iclass 10, count 0 2006.231.08:08:01.61#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:08:01.61#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:08:01.61#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.08:08:01.61#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.08:08:01.61$vc4f8/vb=4,4 2006.231.08:08:01.61#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.08:08:01.61#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.08:08:01.61#ibcon#ireg 11 cls_cnt 2 2006.231.08:08:01.61#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:08:01.67#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:08:01.67#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:08:01.67#ibcon#enter wrdev, iclass 12, count 2 2006.231.08:08:01.67#ibcon#first serial, iclass 12, count 2 2006.231.08:08:01.67#ibcon#enter sib2, iclass 12, count 2 2006.231.08:08:01.67#ibcon#flushed, iclass 12, count 2 2006.231.08:08:01.67#ibcon#about to write, iclass 12, count 2 2006.231.08:08:01.67#ibcon#wrote, iclass 12, count 2 2006.231.08:08:01.67#ibcon#about to read 3, iclass 12, count 2 2006.231.08:08:01.69#ibcon#read 3, iclass 12, count 2 2006.231.08:08:01.69#ibcon#about to read 4, iclass 12, count 2 2006.231.08:08:01.69#ibcon#read 4, iclass 12, count 2 2006.231.08:08:01.69#ibcon#about to read 5, iclass 12, count 2 2006.231.08:08:01.69#ibcon#read 5, iclass 12, count 2 2006.231.08:08:01.69#ibcon#about to read 6, iclass 12, count 2 2006.231.08:08:01.69#ibcon#read 6, iclass 12, count 2 2006.231.08:08:01.69#ibcon#end of sib2, iclass 12, count 2 2006.231.08:08:01.69#ibcon#*mode == 0, iclass 12, count 2 2006.231.08:08:01.69#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.08:08:01.69#ibcon#[27=AT04-04\r\n] 2006.231.08:08:01.69#ibcon#*before write, iclass 12, count 2 2006.231.08:08:01.69#ibcon#enter sib2, iclass 12, count 2 2006.231.08:08:01.69#ibcon#flushed, iclass 12, count 2 2006.231.08:08:01.69#ibcon#about to write, iclass 12, count 2 2006.231.08:08:01.69#ibcon#wrote, iclass 12, count 2 2006.231.08:08:01.69#ibcon#about to read 3, iclass 12, count 2 2006.231.08:08:01.72#ibcon#read 3, iclass 12, count 2 2006.231.08:08:01.72#ibcon#about to read 4, iclass 12, count 2 2006.231.08:08:01.72#ibcon#read 4, iclass 12, count 2 2006.231.08:08:01.72#ibcon#about to read 5, iclass 12, count 2 2006.231.08:08:01.72#ibcon#read 5, iclass 12, count 2 2006.231.08:08:01.72#ibcon#about to read 6, iclass 12, count 2 2006.231.08:08:01.72#ibcon#read 6, iclass 12, count 2 2006.231.08:08:01.72#ibcon#end of sib2, iclass 12, count 2 2006.231.08:08:01.72#ibcon#*after write, iclass 12, count 2 2006.231.08:08:01.72#ibcon#*before return 0, iclass 12, count 2 2006.231.08:08:01.72#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:08:01.72#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:08:01.72#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.08:08:01.72#ibcon#ireg 7 cls_cnt 0 2006.231.08:08:01.72#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:08:01.84#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:08:01.84#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:08:01.84#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:08:01.84#ibcon#first serial, iclass 12, count 0 2006.231.08:08:01.84#ibcon#enter sib2, iclass 12, count 0 2006.231.08:08:01.84#ibcon#flushed, iclass 12, count 0 2006.231.08:08:01.84#ibcon#about to write, iclass 12, count 0 2006.231.08:08:01.84#ibcon#wrote, iclass 12, count 0 2006.231.08:08:01.84#ibcon#about to read 3, iclass 12, count 0 2006.231.08:08:01.86#ibcon#read 3, iclass 12, count 0 2006.231.08:08:01.86#ibcon#about to read 4, iclass 12, count 0 2006.231.08:08:01.86#ibcon#read 4, iclass 12, count 0 2006.231.08:08:01.86#ibcon#about to read 5, iclass 12, count 0 2006.231.08:08:01.86#ibcon#read 5, iclass 12, count 0 2006.231.08:08:01.86#ibcon#about to read 6, iclass 12, count 0 2006.231.08:08:01.86#ibcon#read 6, iclass 12, count 0 2006.231.08:08:01.86#ibcon#end of sib2, iclass 12, count 0 2006.231.08:08:01.86#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:08:01.86#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:08:01.86#ibcon#[27=USB\r\n] 2006.231.08:08:01.86#ibcon#*before write, iclass 12, count 0 2006.231.08:08:01.86#ibcon#enter sib2, iclass 12, count 0 2006.231.08:08:01.86#ibcon#flushed, iclass 12, count 0 2006.231.08:08:01.86#ibcon#about to write, iclass 12, count 0 2006.231.08:08:01.86#ibcon#wrote, iclass 12, count 0 2006.231.08:08:01.86#ibcon#about to read 3, iclass 12, count 0 2006.231.08:08:01.90#ibcon#read 3, iclass 12, count 0 2006.231.08:08:01.90#ibcon#about to read 4, iclass 12, count 0 2006.231.08:08:01.90#ibcon#read 4, iclass 12, count 0 2006.231.08:08:01.90#ibcon#about to read 5, iclass 12, count 0 2006.231.08:08:01.90#ibcon#read 5, iclass 12, count 0 2006.231.08:08:01.90#ibcon#about to read 6, iclass 12, count 0 2006.231.08:08:01.90#ibcon#read 6, iclass 12, count 0 2006.231.08:08:01.90#ibcon#end of sib2, iclass 12, count 0 2006.231.08:08:01.90#ibcon#*after write, iclass 12, count 0 2006.231.08:08:01.90#ibcon#*before return 0, iclass 12, count 0 2006.231.08:08:01.90#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:08:01.90#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:08:01.90#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:08:01.90#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:08:01.90$vc4f8/vblo=5,744.99 2006.231.08:08:01.90#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.08:08:01.90#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.08:08:01.90#ibcon#ireg 17 cls_cnt 0 2006.231.08:08:01.90#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:08:01.90#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:08:01.90#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:08:01.90#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:08:01.90#ibcon#first serial, iclass 14, count 0 2006.231.08:08:01.90#ibcon#enter sib2, iclass 14, count 0 2006.231.08:08:01.90#ibcon#flushed, iclass 14, count 0 2006.231.08:08:01.90#ibcon#about to write, iclass 14, count 0 2006.231.08:08:01.90#ibcon#wrote, iclass 14, count 0 2006.231.08:08:01.90#ibcon#about to read 3, iclass 14, count 0 2006.231.08:08:01.91#ibcon#read 3, iclass 14, count 0 2006.231.08:08:01.91#ibcon#about to read 4, iclass 14, count 0 2006.231.08:08:01.91#ibcon#read 4, iclass 14, count 0 2006.231.08:08:01.91#ibcon#about to read 5, iclass 14, count 0 2006.231.08:08:01.91#ibcon#read 5, iclass 14, count 0 2006.231.08:08:01.91#ibcon#about to read 6, iclass 14, count 0 2006.231.08:08:01.91#ibcon#read 6, iclass 14, count 0 2006.231.08:08:01.91#ibcon#end of sib2, iclass 14, count 0 2006.231.08:08:01.91#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:08:01.91#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:08:01.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:08:01.91#ibcon#*before write, iclass 14, count 0 2006.231.08:08:01.91#ibcon#enter sib2, iclass 14, count 0 2006.231.08:08:01.91#ibcon#flushed, iclass 14, count 0 2006.231.08:08:01.91#ibcon#about to write, iclass 14, count 0 2006.231.08:08:01.91#ibcon#wrote, iclass 14, count 0 2006.231.08:08:01.91#ibcon#about to read 3, iclass 14, count 0 2006.231.08:08:01.95#ibcon#read 3, iclass 14, count 0 2006.231.08:08:01.95#ibcon#about to read 4, iclass 14, count 0 2006.231.08:08:01.95#ibcon#read 4, iclass 14, count 0 2006.231.08:08:01.95#ibcon#about to read 5, iclass 14, count 0 2006.231.08:08:01.95#ibcon#read 5, iclass 14, count 0 2006.231.08:08:01.95#ibcon#about to read 6, iclass 14, count 0 2006.231.08:08:01.95#ibcon#read 6, iclass 14, count 0 2006.231.08:08:01.95#ibcon#end of sib2, iclass 14, count 0 2006.231.08:08:01.95#ibcon#*after write, iclass 14, count 0 2006.231.08:08:01.95#ibcon#*before return 0, iclass 14, count 0 2006.231.08:08:01.95#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:08:01.95#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:08:01.95#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:08:01.95#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:08:01.95$vc4f8/vb=5,3 2006.231.08:08:01.95#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.08:08:01.95#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.08:08:01.95#ibcon#ireg 11 cls_cnt 2 2006.231.08:08:01.95#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:08:02.02#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:08:02.02#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:08:02.02#ibcon#enter wrdev, iclass 16, count 2 2006.231.08:08:02.02#ibcon#first serial, iclass 16, count 2 2006.231.08:08:02.02#ibcon#enter sib2, iclass 16, count 2 2006.231.08:08:02.02#ibcon#flushed, iclass 16, count 2 2006.231.08:08:02.02#ibcon#about to write, iclass 16, count 2 2006.231.08:08:02.02#ibcon#wrote, iclass 16, count 2 2006.231.08:08:02.02#ibcon#about to read 3, iclass 16, count 2 2006.231.08:08:02.05#ibcon#read 3, iclass 16, count 2 2006.231.08:08:02.05#ibcon#about to read 4, iclass 16, count 2 2006.231.08:08:02.05#ibcon#read 4, iclass 16, count 2 2006.231.08:08:02.05#ibcon#about to read 5, iclass 16, count 2 2006.231.08:08:02.05#ibcon#read 5, iclass 16, count 2 2006.231.08:08:02.05#ibcon#about to read 6, iclass 16, count 2 2006.231.08:08:02.05#ibcon#read 6, iclass 16, count 2 2006.231.08:08:02.05#ibcon#end of sib2, iclass 16, count 2 2006.231.08:08:02.05#ibcon#*mode == 0, iclass 16, count 2 2006.231.08:08:02.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.08:08:02.05#ibcon#[27=AT05-03\r\n] 2006.231.08:08:02.05#ibcon#*before write, iclass 16, count 2 2006.231.08:08:02.05#ibcon#enter sib2, iclass 16, count 2 2006.231.08:08:02.05#ibcon#flushed, iclass 16, count 2 2006.231.08:08:02.05#ibcon#about to write, iclass 16, count 2 2006.231.08:08:02.05#ibcon#wrote, iclass 16, count 2 2006.231.08:08:02.05#ibcon#about to read 3, iclass 16, count 2 2006.231.08:08:02.08#ibcon#read 3, iclass 16, count 2 2006.231.08:08:02.08#ibcon#about to read 4, iclass 16, count 2 2006.231.08:08:02.08#ibcon#read 4, iclass 16, count 2 2006.231.08:08:02.08#ibcon#about to read 5, iclass 16, count 2 2006.231.08:08:02.08#ibcon#read 5, iclass 16, count 2 2006.231.08:08:02.08#ibcon#about to read 6, iclass 16, count 2 2006.231.08:08:02.08#ibcon#read 6, iclass 16, count 2 2006.231.08:08:02.08#ibcon#end of sib2, iclass 16, count 2 2006.231.08:08:02.08#ibcon#*after write, iclass 16, count 2 2006.231.08:08:02.08#ibcon#*before return 0, iclass 16, count 2 2006.231.08:08:02.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:08:02.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:08:02.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.08:08:02.08#ibcon#ireg 7 cls_cnt 0 2006.231.08:08:02.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:08:02.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:08:02.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:08:02.20#ibcon#enter wrdev, iclass 16, count 0 2006.231.08:08:02.20#ibcon#first serial, iclass 16, count 0 2006.231.08:08:02.20#ibcon#enter sib2, iclass 16, count 0 2006.231.08:08:02.20#ibcon#flushed, iclass 16, count 0 2006.231.08:08:02.20#ibcon#about to write, iclass 16, count 0 2006.231.08:08:02.20#ibcon#wrote, iclass 16, count 0 2006.231.08:08:02.20#ibcon#about to read 3, iclass 16, count 0 2006.231.08:08:02.22#ibcon#read 3, iclass 16, count 0 2006.231.08:08:02.22#ibcon#about to read 4, iclass 16, count 0 2006.231.08:08:02.22#ibcon#read 4, iclass 16, count 0 2006.231.08:08:02.22#ibcon#about to read 5, iclass 16, count 0 2006.231.08:08:02.22#ibcon#read 5, iclass 16, count 0 2006.231.08:08:02.22#ibcon#about to read 6, iclass 16, count 0 2006.231.08:08:02.22#ibcon#read 6, iclass 16, count 0 2006.231.08:08:02.22#ibcon#end of sib2, iclass 16, count 0 2006.231.08:08:02.22#ibcon#*mode == 0, iclass 16, count 0 2006.231.08:08:02.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.08:08:02.22#ibcon#[27=USB\r\n] 2006.231.08:08:02.22#ibcon#*before write, iclass 16, count 0 2006.231.08:08:02.22#ibcon#enter sib2, iclass 16, count 0 2006.231.08:08:02.22#ibcon#flushed, iclass 16, count 0 2006.231.08:08:02.22#ibcon#about to write, iclass 16, count 0 2006.231.08:08:02.22#ibcon#wrote, iclass 16, count 0 2006.231.08:08:02.22#ibcon#about to read 3, iclass 16, count 0 2006.231.08:08:02.25#ibcon#read 3, iclass 16, count 0 2006.231.08:08:02.25#ibcon#about to read 4, iclass 16, count 0 2006.231.08:08:02.25#ibcon#read 4, iclass 16, count 0 2006.231.08:08:02.25#ibcon#about to read 5, iclass 16, count 0 2006.231.08:08:02.25#ibcon#read 5, iclass 16, count 0 2006.231.08:08:02.25#ibcon#about to read 6, iclass 16, count 0 2006.231.08:08:02.25#ibcon#read 6, iclass 16, count 0 2006.231.08:08:02.25#ibcon#end of sib2, iclass 16, count 0 2006.231.08:08:02.25#ibcon#*after write, iclass 16, count 0 2006.231.08:08:02.25#ibcon#*before return 0, iclass 16, count 0 2006.231.08:08:02.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:08:02.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:08:02.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.08:08:02.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.08:08:02.25$vc4f8/vblo=6,752.99 2006.231.08:08:02.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.08:08:02.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.08:08:02.25#ibcon#ireg 17 cls_cnt 0 2006.231.08:08:02.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:08:02.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:08:02.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:08:02.25#ibcon#enter wrdev, iclass 18, count 0 2006.231.08:08:02.25#ibcon#first serial, iclass 18, count 0 2006.231.08:08:02.25#ibcon#enter sib2, iclass 18, count 0 2006.231.08:08:02.25#ibcon#flushed, iclass 18, count 0 2006.231.08:08:02.25#ibcon#about to write, iclass 18, count 0 2006.231.08:08:02.25#ibcon#wrote, iclass 18, count 0 2006.231.08:08:02.25#ibcon#about to read 3, iclass 18, count 0 2006.231.08:08:02.28#ibcon#read 3, iclass 18, count 0 2006.231.08:08:02.28#ibcon#about to read 4, iclass 18, count 0 2006.231.08:08:02.28#ibcon#read 4, iclass 18, count 0 2006.231.08:08:02.28#ibcon#about to read 5, iclass 18, count 0 2006.231.08:08:02.28#ibcon#read 5, iclass 18, count 0 2006.231.08:08:02.28#ibcon#about to read 6, iclass 18, count 0 2006.231.08:08:02.28#ibcon#read 6, iclass 18, count 0 2006.231.08:08:02.28#ibcon#end of sib2, iclass 18, count 0 2006.231.08:08:02.28#ibcon#*mode == 0, iclass 18, count 0 2006.231.08:08:02.28#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.08:08:02.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:08:02.28#ibcon#*before write, iclass 18, count 0 2006.231.08:08:02.28#ibcon#enter sib2, iclass 18, count 0 2006.231.08:08:02.28#ibcon#flushed, iclass 18, count 0 2006.231.08:08:02.28#ibcon#about to write, iclass 18, count 0 2006.231.08:08:02.28#ibcon#wrote, iclass 18, count 0 2006.231.08:08:02.28#ibcon#about to read 3, iclass 18, count 0 2006.231.08:08:02.32#ibcon#read 3, iclass 18, count 0 2006.231.08:08:02.32#ibcon#about to read 4, iclass 18, count 0 2006.231.08:08:02.32#ibcon#read 4, iclass 18, count 0 2006.231.08:08:02.32#ibcon#about to read 5, iclass 18, count 0 2006.231.08:08:02.32#ibcon#read 5, iclass 18, count 0 2006.231.08:08:02.32#ibcon#about to read 6, iclass 18, count 0 2006.231.08:08:02.32#ibcon#read 6, iclass 18, count 0 2006.231.08:08:02.32#ibcon#end of sib2, iclass 18, count 0 2006.231.08:08:02.32#ibcon#*after write, iclass 18, count 0 2006.231.08:08:02.32#ibcon#*before return 0, iclass 18, count 0 2006.231.08:08:02.32#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:08:02.32#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:08:02.32#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.08:08:02.32#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.08:08:02.32$vc4f8/vb=6,4 2006.231.08:08:02.32#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.08:08:02.32#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.08:08:02.32#ibcon#ireg 11 cls_cnt 2 2006.231.08:08:02.32#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:08:02.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:08:02.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:08:02.37#ibcon#enter wrdev, iclass 20, count 2 2006.231.08:08:02.37#ibcon#first serial, iclass 20, count 2 2006.231.08:08:02.37#ibcon#enter sib2, iclass 20, count 2 2006.231.08:08:02.37#ibcon#flushed, iclass 20, count 2 2006.231.08:08:02.37#ibcon#about to write, iclass 20, count 2 2006.231.08:08:02.37#ibcon#wrote, iclass 20, count 2 2006.231.08:08:02.37#ibcon#about to read 3, iclass 20, count 2 2006.231.08:08:02.39#ibcon#read 3, iclass 20, count 2 2006.231.08:08:02.39#ibcon#about to read 4, iclass 20, count 2 2006.231.08:08:02.39#ibcon#read 4, iclass 20, count 2 2006.231.08:08:02.39#ibcon#about to read 5, iclass 20, count 2 2006.231.08:08:02.39#ibcon#read 5, iclass 20, count 2 2006.231.08:08:02.39#ibcon#about to read 6, iclass 20, count 2 2006.231.08:08:02.39#ibcon#read 6, iclass 20, count 2 2006.231.08:08:02.39#ibcon#end of sib2, iclass 20, count 2 2006.231.08:08:02.39#ibcon#*mode == 0, iclass 20, count 2 2006.231.08:08:02.39#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.08:08:02.39#ibcon#[27=AT06-04\r\n] 2006.231.08:08:02.39#ibcon#*before write, iclass 20, count 2 2006.231.08:08:02.39#ibcon#enter sib2, iclass 20, count 2 2006.231.08:08:02.39#ibcon#flushed, iclass 20, count 2 2006.231.08:08:02.39#ibcon#about to write, iclass 20, count 2 2006.231.08:08:02.39#ibcon#wrote, iclass 20, count 2 2006.231.08:08:02.39#ibcon#about to read 3, iclass 20, count 2 2006.231.08:08:02.42#ibcon#read 3, iclass 20, count 2 2006.231.08:08:02.42#ibcon#about to read 4, iclass 20, count 2 2006.231.08:08:02.42#ibcon#read 4, iclass 20, count 2 2006.231.08:08:02.42#ibcon#about to read 5, iclass 20, count 2 2006.231.08:08:02.42#ibcon#read 5, iclass 20, count 2 2006.231.08:08:02.42#ibcon#about to read 6, iclass 20, count 2 2006.231.08:08:02.42#ibcon#read 6, iclass 20, count 2 2006.231.08:08:02.42#ibcon#end of sib2, iclass 20, count 2 2006.231.08:08:02.42#ibcon#*after write, iclass 20, count 2 2006.231.08:08:02.42#ibcon#*before return 0, iclass 20, count 2 2006.231.08:08:02.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:08:02.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:08:02.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.08:08:02.42#ibcon#ireg 7 cls_cnt 0 2006.231.08:08:02.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:08:02.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:08:02.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:08:02.54#ibcon#enter wrdev, iclass 20, count 0 2006.231.08:08:02.54#ibcon#first serial, iclass 20, count 0 2006.231.08:08:02.54#ibcon#enter sib2, iclass 20, count 0 2006.231.08:08:02.54#ibcon#flushed, iclass 20, count 0 2006.231.08:08:02.54#ibcon#about to write, iclass 20, count 0 2006.231.08:08:02.54#ibcon#wrote, iclass 20, count 0 2006.231.08:08:02.54#ibcon#about to read 3, iclass 20, count 0 2006.231.08:08:02.56#ibcon#read 3, iclass 20, count 0 2006.231.08:08:02.56#ibcon#about to read 4, iclass 20, count 0 2006.231.08:08:02.56#ibcon#read 4, iclass 20, count 0 2006.231.08:08:02.56#ibcon#about to read 5, iclass 20, count 0 2006.231.08:08:02.56#ibcon#read 5, iclass 20, count 0 2006.231.08:08:02.56#ibcon#about to read 6, iclass 20, count 0 2006.231.08:08:02.56#ibcon#read 6, iclass 20, count 0 2006.231.08:08:02.56#ibcon#end of sib2, iclass 20, count 0 2006.231.08:08:02.56#ibcon#*mode == 0, iclass 20, count 0 2006.231.08:08:02.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.08:08:02.56#ibcon#[27=USB\r\n] 2006.231.08:08:02.56#ibcon#*before write, iclass 20, count 0 2006.231.08:08:02.56#ibcon#enter sib2, iclass 20, count 0 2006.231.08:08:02.56#ibcon#flushed, iclass 20, count 0 2006.231.08:08:02.56#ibcon#about to write, iclass 20, count 0 2006.231.08:08:02.56#ibcon#wrote, iclass 20, count 0 2006.231.08:08:02.56#ibcon#about to read 3, iclass 20, count 0 2006.231.08:08:02.59#ibcon#read 3, iclass 20, count 0 2006.231.08:08:02.59#ibcon#about to read 4, iclass 20, count 0 2006.231.08:08:02.59#ibcon#read 4, iclass 20, count 0 2006.231.08:08:02.59#ibcon#about to read 5, iclass 20, count 0 2006.231.08:08:02.59#ibcon#read 5, iclass 20, count 0 2006.231.08:08:02.59#ibcon#about to read 6, iclass 20, count 0 2006.231.08:08:02.59#ibcon#read 6, iclass 20, count 0 2006.231.08:08:02.59#ibcon#end of sib2, iclass 20, count 0 2006.231.08:08:02.59#ibcon#*after write, iclass 20, count 0 2006.231.08:08:02.59#ibcon#*before return 0, iclass 20, count 0 2006.231.08:08:02.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:08:02.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:08:02.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.08:08:02.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.08:08:02.59$vc4f8/vabw=wide 2006.231.08:08:02.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.08:08:02.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.08:08:02.59#ibcon#ireg 8 cls_cnt 0 2006.231.08:08:02.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:08:02.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:08:02.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:08:02.59#ibcon#enter wrdev, iclass 22, count 0 2006.231.08:08:02.59#ibcon#first serial, iclass 22, count 0 2006.231.08:08:02.59#ibcon#enter sib2, iclass 22, count 0 2006.231.08:08:02.59#ibcon#flushed, iclass 22, count 0 2006.231.08:08:02.59#ibcon#about to write, iclass 22, count 0 2006.231.08:08:02.59#ibcon#wrote, iclass 22, count 0 2006.231.08:08:02.59#ibcon#about to read 3, iclass 22, count 0 2006.231.08:08:02.61#ibcon#read 3, iclass 22, count 0 2006.231.08:08:02.61#ibcon#about to read 4, iclass 22, count 0 2006.231.08:08:02.61#ibcon#read 4, iclass 22, count 0 2006.231.08:08:02.61#ibcon#about to read 5, iclass 22, count 0 2006.231.08:08:02.61#ibcon#read 5, iclass 22, count 0 2006.231.08:08:02.61#ibcon#about to read 6, iclass 22, count 0 2006.231.08:08:02.61#ibcon#read 6, iclass 22, count 0 2006.231.08:08:02.61#ibcon#end of sib2, iclass 22, count 0 2006.231.08:08:02.61#ibcon#*mode == 0, iclass 22, count 0 2006.231.08:08:02.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.08:08:02.61#ibcon#[25=BW32\r\n] 2006.231.08:08:02.61#ibcon#*before write, iclass 22, count 0 2006.231.08:08:02.61#ibcon#enter sib2, iclass 22, count 0 2006.231.08:08:02.61#ibcon#flushed, iclass 22, count 0 2006.231.08:08:02.61#ibcon#about to write, iclass 22, count 0 2006.231.08:08:02.61#ibcon#wrote, iclass 22, count 0 2006.231.08:08:02.61#ibcon#about to read 3, iclass 22, count 0 2006.231.08:08:02.65#ibcon#read 3, iclass 22, count 0 2006.231.08:08:02.65#ibcon#about to read 4, iclass 22, count 0 2006.231.08:08:02.65#ibcon#read 4, iclass 22, count 0 2006.231.08:08:02.65#ibcon#about to read 5, iclass 22, count 0 2006.231.08:08:02.65#ibcon#read 5, iclass 22, count 0 2006.231.08:08:02.65#ibcon#about to read 6, iclass 22, count 0 2006.231.08:08:02.65#ibcon#read 6, iclass 22, count 0 2006.231.08:08:02.65#ibcon#end of sib2, iclass 22, count 0 2006.231.08:08:02.65#ibcon#*after write, iclass 22, count 0 2006.231.08:08:02.65#ibcon#*before return 0, iclass 22, count 0 2006.231.08:08:02.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:08:02.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:08:02.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.08:08:02.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.08:08:02.65$vc4f8/vbbw=wide 2006.231.08:08:02.65#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.231.08:08:02.65#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.231.08:08:02.65#ibcon#ireg 8 cls_cnt 0 2006.231.08:08:02.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:08:02.70#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:08:02.70#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:08:02.70#ibcon#enter wrdev, iclass 24, count 0 2006.231.08:08:02.70#ibcon#first serial, iclass 24, count 0 2006.231.08:08:02.70#ibcon#enter sib2, iclass 24, count 0 2006.231.08:08:02.70#ibcon#flushed, iclass 24, count 0 2006.231.08:08:02.70#ibcon#about to write, iclass 24, count 0 2006.231.08:08:02.70#ibcon#wrote, iclass 24, count 0 2006.231.08:08:02.70#ibcon#about to read 3, iclass 24, count 0 2006.231.08:08:02.72#ibcon#read 3, iclass 24, count 0 2006.231.08:08:02.72#ibcon#about to read 4, iclass 24, count 0 2006.231.08:08:02.72#ibcon#read 4, iclass 24, count 0 2006.231.08:08:02.72#ibcon#about to read 5, iclass 24, count 0 2006.231.08:08:02.72#ibcon#read 5, iclass 24, count 0 2006.231.08:08:02.72#ibcon#about to read 6, iclass 24, count 0 2006.231.08:08:02.72#ibcon#read 6, iclass 24, count 0 2006.231.08:08:02.72#ibcon#end of sib2, iclass 24, count 0 2006.231.08:08:02.72#ibcon#*mode == 0, iclass 24, count 0 2006.231.08:08:02.72#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.08:08:02.72#ibcon#[27=BW32\r\n] 2006.231.08:08:02.72#ibcon#*before write, iclass 24, count 0 2006.231.08:08:02.72#ibcon#enter sib2, iclass 24, count 0 2006.231.08:08:02.72#ibcon#flushed, iclass 24, count 0 2006.231.08:08:02.72#ibcon#about to write, iclass 24, count 0 2006.231.08:08:02.72#ibcon#wrote, iclass 24, count 0 2006.231.08:08:02.72#ibcon#about to read 3, iclass 24, count 0 2006.231.08:08:02.75#ibcon#read 3, iclass 24, count 0 2006.231.08:08:02.75#ibcon#about to read 4, iclass 24, count 0 2006.231.08:08:02.75#ibcon#read 4, iclass 24, count 0 2006.231.08:08:02.75#ibcon#about to read 5, iclass 24, count 0 2006.231.08:08:02.75#ibcon#read 5, iclass 24, count 0 2006.231.08:08:02.75#ibcon#about to read 6, iclass 24, count 0 2006.231.08:08:02.75#ibcon#read 6, iclass 24, count 0 2006.231.08:08:02.75#ibcon#end of sib2, iclass 24, count 0 2006.231.08:08:02.75#ibcon#*after write, iclass 24, count 0 2006.231.08:08:02.75#ibcon#*before return 0, iclass 24, count 0 2006.231.08:08:02.75#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:08:02.75#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:08:02.75#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.08:08:02.75#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.08:08:02.75$4f8m12a/ifd4f 2006.231.08:08:02.75$ifd4f/lo= 2006.231.08:08:02.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:08:02.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:08:02.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:08:02.75$ifd4f/patch= 2006.231.08:08:02.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:08:02.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:08:02.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:08:02.76$4f8m12a/"form=m,16.000,1:2 2006.231.08:08:02.76$4f8m12a/"tpicd 2006.231.08:08:02.76$4f8m12a/echo=off 2006.231.08:08:02.76$4f8m12a/xlog=off 2006.231.08:08:02.76:!2006.231.08:08:30 2006.231.08:08:10.13#trakl#Source acquired 2006.231.08:08:12.13#flagr#flagr/antenna,acquired 2006.231.08:08:30.01:preob 2006.231.08:08:31.13/onsource/TRACKING 2006.231.08:08:31.13:!2006.231.08:08:40 2006.231.08:08:40.00:data_valid=on 2006.231.08:08:40.00:midob 2006.231.08:08:40.13/onsource/TRACKING 2006.231.08:08:40.13/wx/30.49,1004.5,86 2006.231.08:08:40.29/cable/+6.3712E-03 2006.231.08:08:41.38/va/01,08,usb,yes,29,31 2006.231.08:08:41.38/va/02,07,usb,yes,29,31 2006.231.08:08:41.38/va/03,08,usb,yes,22,22 2006.231.08:08:41.38/va/04,07,usb,yes,31,33 2006.231.08:08:41.38/va/05,07,usb,yes,34,36 2006.231.08:08:41.38/va/06,06,usb,yes,33,33 2006.231.08:08:41.38/va/07,06,usb,yes,34,34 2006.231.08:08:41.38/va/08,06,usb,yes,36,35 2006.231.08:08:41.61/valo/01,532.99,yes,locked 2006.231.08:08:41.61/valo/02,572.99,yes,locked 2006.231.08:08:41.61/valo/03,672.99,yes,locked 2006.231.08:08:41.61/valo/04,832.99,yes,locked 2006.231.08:08:41.61/valo/05,652.99,yes,locked 2006.231.08:08:41.61/valo/06,772.99,yes,locked 2006.231.08:08:41.61/valo/07,832.99,yes,locked 2006.231.08:08:41.61/valo/08,852.99,yes,locked 2006.231.08:08:42.70/vb/01,04,usb,yes,30,29 2006.231.08:08:42.70/vb/02,04,usb,yes,32,34 2006.231.08:08:42.70/vb/03,04,usb,yes,29,32 2006.231.08:08:42.70/vb/04,04,usb,yes,29,30 2006.231.08:08:42.70/vb/05,03,usb,yes,35,39 2006.231.08:08:42.70/vb/06,04,usb,yes,29,32 2006.231.08:08:42.70/vb/07,04,usb,yes,31,31 2006.231.08:08:42.70/vb/08,04,usb,yes,28,32 2006.231.08:08:42.93/vblo/01,632.99,yes,locked 2006.231.08:08:42.93/vblo/02,640.99,yes,locked 2006.231.08:08:42.93/vblo/03,656.99,yes,locked 2006.231.08:08:42.93/vblo/04,712.99,yes,locked 2006.231.08:08:42.93/vblo/05,744.99,yes,locked 2006.231.08:08:42.93/vblo/06,752.99,yes,locked 2006.231.08:08:42.93/vblo/07,734.99,yes,locked 2006.231.08:08:42.93/vblo/08,744.99,yes,locked 2006.231.08:08:43.08/vabw/8 2006.231.08:08:43.23/vbbw/8 2006.231.08:08:43.32/xfe/off,on,12.2 2006.231.08:08:43.70/ifatt/23,28,28,28 2006.231.08:08:44.07/fmout-gps/S +4.43E-07 2006.231.08:08:44.11:!2006.231.08:09:40 2006.231.08:09:40.00:data_valid=off 2006.231.08:09:40.00:postob 2006.231.08:09:40.10/cable/+6.3717E-03 2006.231.08:09:40.10/wx/30.48,1004.5,86 2006.231.08:09:41.07/fmout-gps/S +4.44E-07 2006.231.08:09:41.07:scan_name=231-0810,k06231,60 2006.231.08:09:41.07:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.231.08:09:41.13#flagr#flagr/antenna,new-source 2006.231.08:09:42.13:checkk5 2006.231.08:09:42.50/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:09:42.87/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:09:43.25/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:09:43.62/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:09:43.99/chk_obsdata//k5ts1/T2310808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:09:44.36/chk_obsdata//k5ts2/T2310808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:09:44.72/chk_obsdata//k5ts3/T2310808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:09:45.09/chk_obsdata//k5ts4/T2310808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:09:45.78/k5log//k5ts1_log_newline 2006.231.08:09:46.47/k5log//k5ts2_log_newline 2006.231.08:09:47.16/k5log//k5ts3_log_newline 2006.231.08:09:47.85/k5log//k5ts4_log_newline 2006.231.08:09:47.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:09:47.87:4f8m12a=2 2006.231.08:09:47.87$4f8m12a/echo=on 2006.231.08:09:47.87$4f8m12a/pcalon 2006.231.08:09:47.87$pcalon/"no phase cal control is implemented here 2006.231.08:09:47.87$4f8m12a/"tpicd=stop 2006.231.08:09:47.87$4f8m12a/vc4f8 2006.231.08:09:47.87$vc4f8/valo=1,532.99 2006.231.08:09:47.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.231.08:09:47.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.231.08:09:47.88#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:47.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:09:47.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:09:47.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:09:47.88#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:09:47.88#ibcon#first serial, iclass 31, count 0 2006.231.08:09:47.88#ibcon#enter sib2, iclass 31, count 0 2006.231.08:09:47.88#ibcon#flushed, iclass 31, count 0 2006.231.08:09:47.88#ibcon#about to write, iclass 31, count 0 2006.231.08:09:47.88#ibcon#wrote, iclass 31, count 0 2006.231.08:09:47.88#ibcon#about to read 3, iclass 31, count 0 2006.231.08:09:47.89#ibcon#read 3, iclass 31, count 0 2006.231.08:09:47.89#ibcon#about to read 4, iclass 31, count 0 2006.231.08:09:47.89#ibcon#read 4, iclass 31, count 0 2006.231.08:09:47.89#ibcon#about to read 5, iclass 31, count 0 2006.231.08:09:47.89#ibcon#read 5, iclass 31, count 0 2006.231.08:09:47.89#ibcon#about to read 6, iclass 31, count 0 2006.231.08:09:47.89#ibcon#read 6, iclass 31, count 0 2006.231.08:09:47.89#ibcon#end of sib2, iclass 31, count 0 2006.231.08:09:47.89#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:09:47.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:09:47.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:09:47.89#ibcon#*before write, iclass 31, count 0 2006.231.08:09:47.89#ibcon#enter sib2, iclass 31, count 0 2006.231.08:09:47.89#ibcon#flushed, iclass 31, count 0 2006.231.08:09:47.89#ibcon#about to write, iclass 31, count 0 2006.231.08:09:47.89#ibcon#wrote, iclass 31, count 0 2006.231.08:09:47.89#ibcon#about to read 3, iclass 31, count 0 2006.231.08:09:47.94#ibcon#read 3, iclass 31, count 0 2006.231.08:09:47.94#ibcon#about to read 4, iclass 31, count 0 2006.231.08:09:47.94#ibcon#read 4, iclass 31, count 0 2006.231.08:09:47.94#ibcon#about to read 5, iclass 31, count 0 2006.231.08:09:47.94#ibcon#read 5, iclass 31, count 0 2006.231.08:09:47.94#ibcon#about to read 6, iclass 31, count 0 2006.231.08:09:47.94#ibcon#read 6, iclass 31, count 0 2006.231.08:09:47.94#ibcon#end of sib2, iclass 31, count 0 2006.231.08:09:47.94#ibcon#*after write, iclass 31, count 0 2006.231.08:09:47.94#ibcon#*before return 0, iclass 31, count 0 2006.231.08:09:47.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:09:47.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:09:47.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:09:47.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:09:47.94$vc4f8/va=1,8 2006.231.08:09:47.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.231.08:09:47.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.231.08:09:47.94#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:47.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:09:47.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:09:47.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:09:47.94#ibcon#enter wrdev, iclass 33, count 2 2006.231.08:09:47.94#ibcon#first serial, iclass 33, count 2 2006.231.08:09:47.94#ibcon#enter sib2, iclass 33, count 2 2006.231.08:09:47.94#ibcon#flushed, iclass 33, count 2 2006.231.08:09:47.94#ibcon#about to write, iclass 33, count 2 2006.231.08:09:47.94#ibcon#wrote, iclass 33, count 2 2006.231.08:09:47.94#ibcon#about to read 3, iclass 33, count 2 2006.231.08:09:47.96#ibcon#read 3, iclass 33, count 2 2006.231.08:09:47.96#ibcon#about to read 4, iclass 33, count 2 2006.231.08:09:47.96#ibcon#read 4, iclass 33, count 2 2006.231.08:09:47.96#ibcon#about to read 5, iclass 33, count 2 2006.231.08:09:47.96#ibcon#read 5, iclass 33, count 2 2006.231.08:09:47.96#ibcon#about to read 6, iclass 33, count 2 2006.231.08:09:47.96#ibcon#read 6, iclass 33, count 2 2006.231.08:09:47.96#ibcon#end of sib2, iclass 33, count 2 2006.231.08:09:47.96#ibcon#*mode == 0, iclass 33, count 2 2006.231.08:09:47.96#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.231.08:09:47.96#ibcon#[25=AT01-08\r\n] 2006.231.08:09:47.96#ibcon#*before write, iclass 33, count 2 2006.231.08:09:47.96#ibcon#enter sib2, iclass 33, count 2 2006.231.08:09:47.96#ibcon#flushed, iclass 33, count 2 2006.231.08:09:47.96#ibcon#about to write, iclass 33, count 2 2006.231.08:09:47.96#ibcon#wrote, iclass 33, count 2 2006.231.08:09:47.96#ibcon#about to read 3, iclass 33, count 2 2006.231.08:09:48.00#ibcon#read 3, iclass 33, count 2 2006.231.08:09:48.00#ibcon#about to read 4, iclass 33, count 2 2006.231.08:09:48.00#ibcon#read 4, iclass 33, count 2 2006.231.08:09:48.00#ibcon#about to read 5, iclass 33, count 2 2006.231.08:09:48.00#ibcon#read 5, iclass 33, count 2 2006.231.08:09:48.00#ibcon#about to read 6, iclass 33, count 2 2006.231.08:09:48.00#ibcon#read 6, iclass 33, count 2 2006.231.08:09:48.00#ibcon#end of sib2, iclass 33, count 2 2006.231.08:09:48.00#ibcon#*after write, iclass 33, count 2 2006.231.08:09:48.00#ibcon#*before return 0, iclass 33, count 2 2006.231.08:09:48.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:09:48.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:09:48.00#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.231.08:09:48.00#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:48.00#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:09:48.11#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:09:48.11#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:09:48.11#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:09:48.11#ibcon#first serial, iclass 33, count 0 2006.231.08:09:48.11#ibcon#enter sib2, iclass 33, count 0 2006.231.08:09:48.11#ibcon#flushed, iclass 33, count 0 2006.231.08:09:48.11#ibcon#about to write, iclass 33, count 0 2006.231.08:09:48.11#ibcon#wrote, iclass 33, count 0 2006.231.08:09:48.11#ibcon#about to read 3, iclass 33, count 0 2006.231.08:09:48.13#ibcon#read 3, iclass 33, count 0 2006.231.08:09:48.13#ibcon#about to read 4, iclass 33, count 0 2006.231.08:09:48.13#ibcon#read 4, iclass 33, count 0 2006.231.08:09:48.13#ibcon#about to read 5, iclass 33, count 0 2006.231.08:09:48.13#ibcon#read 5, iclass 33, count 0 2006.231.08:09:48.13#ibcon#about to read 6, iclass 33, count 0 2006.231.08:09:48.13#ibcon#read 6, iclass 33, count 0 2006.231.08:09:48.13#ibcon#end of sib2, iclass 33, count 0 2006.231.08:09:48.13#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:09:48.13#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:09:48.13#ibcon#[25=USB\r\n] 2006.231.08:09:48.13#ibcon#*before write, iclass 33, count 0 2006.231.08:09:48.13#ibcon#enter sib2, iclass 33, count 0 2006.231.08:09:48.13#ibcon#flushed, iclass 33, count 0 2006.231.08:09:48.13#ibcon#about to write, iclass 33, count 0 2006.231.08:09:48.13#ibcon#wrote, iclass 33, count 0 2006.231.08:09:48.13#ibcon#about to read 3, iclass 33, count 0 2006.231.08:09:48.16#ibcon#read 3, iclass 33, count 0 2006.231.08:09:48.16#ibcon#about to read 4, iclass 33, count 0 2006.231.08:09:48.16#ibcon#read 4, iclass 33, count 0 2006.231.08:09:48.16#ibcon#about to read 5, iclass 33, count 0 2006.231.08:09:48.16#ibcon#read 5, iclass 33, count 0 2006.231.08:09:48.16#ibcon#about to read 6, iclass 33, count 0 2006.231.08:09:48.16#ibcon#read 6, iclass 33, count 0 2006.231.08:09:48.16#ibcon#end of sib2, iclass 33, count 0 2006.231.08:09:48.16#ibcon#*after write, iclass 33, count 0 2006.231.08:09:48.16#ibcon#*before return 0, iclass 33, count 0 2006.231.08:09:48.16#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:09:48.16#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:09:48.16#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:09:48.16#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:09:48.16$vc4f8/valo=2,572.99 2006.231.08:09:48.16#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.231.08:09:48.16#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.231.08:09:48.16#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:48.16#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:09:48.16#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:09:48.16#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:09:48.16#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:09:48.16#ibcon#first serial, iclass 35, count 0 2006.231.08:09:48.16#ibcon#enter sib2, iclass 35, count 0 2006.231.08:09:48.16#ibcon#flushed, iclass 35, count 0 2006.231.08:09:48.16#ibcon#about to write, iclass 35, count 0 2006.231.08:09:48.16#ibcon#wrote, iclass 35, count 0 2006.231.08:09:48.16#ibcon#about to read 3, iclass 35, count 0 2006.231.08:09:48.18#ibcon#read 3, iclass 35, count 0 2006.231.08:09:48.18#ibcon#about to read 4, iclass 35, count 0 2006.231.08:09:48.18#ibcon#read 4, iclass 35, count 0 2006.231.08:09:48.18#ibcon#about to read 5, iclass 35, count 0 2006.231.08:09:48.18#ibcon#read 5, iclass 35, count 0 2006.231.08:09:48.18#ibcon#about to read 6, iclass 35, count 0 2006.231.08:09:48.18#ibcon#read 6, iclass 35, count 0 2006.231.08:09:48.18#ibcon#end of sib2, iclass 35, count 0 2006.231.08:09:48.18#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:09:48.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:09:48.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:09:48.18#ibcon#*before write, iclass 35, count 0 2006.231.08:09:48.18#ibcon#enter sib2, iclass 35, count 0 2006.231.08:09:48.18#ibcon#flushed, iclass 35, count 0 2006.231.08:09:48.18#ibcon#about to write, iclass 35, count 0 2006.231.08:09:48.18#ibcon#wrote, iclass 35, count 0 2006.231.08:09:48.18#ibcon#about to read 3, iclass 35, count 0 2006.231.08:09:48.22#ibcon#read 3, iclass 35, count 0 2006.231.08:09:48.22#ibcon#about to read 4, iclass 35, count 0 2006.231.08:09:48.22#ibcon#read 4, iclass 35, count 0 2006.231.08:09:48.22#ibcon#about to read 5, iclass 35, count 0 2006.231.08:09:48.22#ibcon#read 5, iclass 35, count 0 2006.231.08:09:48.22#ibcon#about to read 6, iclass 35, count 0 2006.231.08:09:48.22#ibcon#read 6, iclass 35, count 0 2006.231.08:09:48.22#ibcon#end of sib2, iclass 35, count 0 2006.231.08:09:48.22#ibcon#*after write, iclass 35, count 0 2006.231.08:09:48.22#ibcon#*before return 0, iclass 35, count 0 2006.231.08:09:48.22#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:09:48.22#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:09:48.22#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:09:48.22#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:09:48.22$vc4f8/va=2,7 2006.231.08:09:48.22#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.231.08:09:48.22#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.231.08:09:48.22#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:48.22#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:09:48.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:09:48.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:09:48.28#ibcon#enter wrdev, iclass 37, count 2 2006.231.08:09:48.28#ibcon#first serial, iclass 37, count 2 2006.231.08:09:48.28#ibcon#enter sib2, iclass 37, count 2 2006.231.08:09:48.28#ibcon#flushed, iclass 37, count 2 2006.231.08:09:48.28#ibcon#about to write, iclass 37, count 2 2006.231.08:09:48.28#ibcon#wrote, iclass 37, count 2 2006.231.08:09:48.28#ibcon#about to read 3, iclass 37, count 2 2006.231.08:09:48.31#ibcon#read 3, iclass 37, count 2 2006.231.08:09:48.31#ibcon#about to read 4, iclass 37, count 2 2006.231.08:09:48.31#ibcon#read 4, iclass 37, count 2 2006.231.08:09:48.31#ibcon#about to read 5, iclass 37, count 2 2006.231.08:09:48.31#ibcon#read 5, iclass 37, count 2 2006.231.08:09:48.31#ibcon#about to read 6, iclass 37, count 2 2006.231.08:09:48.31#ibcon#read 6, iclass 37, count 2 2006.231.08:09:48.31#ibcon#end of sib2, iclass 37, count 2 2006.231.08:09:48.31#ibcon#*mode == 0, iclass 37, count 2 2006.231.08:09:48.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.231.08:09:48.31#ibcon#[25=AT02-07\r\n] 2006.231.08:09:48.31#ibcon#*before write, iclass 37, count 2 2006.231.08:09:48.31#ibcon#enter sib2, iclass 37, count 2 2006.231.08:09:48.31#ibcon#flushed, iclass 37, count 2 2006.231.08:09:48.31#ibcon#about to write, iclass 37, count 2 2006.231.08:09:48.31#ibcon#wrote, iclass 37, count 2 2006.231.08:09:48.31#ibcon#about to read 3, iclass 37, count 2 2006.231.08:09:48.34#ibcon#read 3, iclass 37, count 2 2006.231.08:09:48.34#ibcon#about to read 4, iclass 37, count 2 2006.231.08:09:48.34#ibcon#read 4, iclass 37, count 2 2006.231.08:09:48.34#ibcon#about to read 5, iclass 37, count 2 2006.231.08:09:48.34#ibcon#read 5, iclass 37, count 2 2006.231.08:09:48.34#ibcon#about to read 6, iclass 37, count 2 2006.231.08:09:48.34#ibcon#read 6, iclass 37, count 2 2006.231.08:09:48.34#ibcon#end of sib2, iclass 37, count 2 2006.231.08:09:48.34#ibcon#*after write, iclass 37, count 2 2006.231.08:09:48.34#ibcon#*before return 0, iclass 37, count 2 2006.231.08:09:48.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:09:48.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:09:48.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.231.08:09:48.34#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:48.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:09:48.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:09:48.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:09:48.46#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:09:48.46#ibcon#first serial, iclass 37, count 0 2006.231.08:09:48.46#ibcon#enter sib2, iclass 37, count 0 2006.231.08:09:48.46#ibcon#flushed, iclass 37, count 0 2006.231.08:09:48.46#ibcon#about to write, iclass 37, count 0 2006.231.08:09:48.46#ibcon#wrote, iclass 37, count 0 2006.231.08:09:48.46#ibcon#about to read 3, iclass 37, count 0 2006.231.08:09:48.48#ibcon#read 3, iclass 37, count 0 2006.231.08:09:48.48#ibcon#about to read 4, iclass 37, count 0 2006.231.08:09:48.48#ibcon#read 4, iclass 37, count 0 2006.231.08:09:48.48#ibcon#about to read 5, iclass 37, count 0 2006.231.08:09:48.48#ibcon#read 5, iclass 37, count 0 2006.231.08:09:48.48#ibcon#about to read 6, iclass 37, count 0 2006.231.08:09:48.48#ibcon#read 6, iclass 37, count 0 2006.231.08:09:48.48#ibcon#end of sib2, iclass 37, count 0 2006.231.08:09:48.48#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:09:48.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:09:48.48#ibcon#[25=USB\r\n] 2006.231.08:09:48.48#ibcon#*before write, iclass 37, count 0 2006.231.08:09:48.48#ibcon#enter sib2, iclass 37, count 0 2006.231.08:09:48.48#ibcon#flushed, iclass 37, count 0 2006.231.08:09:48.48#ibcon#about to write, iclass 37, count 0 2006.231.08:09:48.48#ibcon#wrote, iclass 37, count 0 2006.231.08:09:48.48#ibcon#about to read 3, iclass 37, count 0 2006.231.08:09:48.51#ibcon#read 3, iclass 37, count 0 2006.231.08:09:48.51#ibcon#about to read 4, iclass 37, count 0 2006.231.08:09:48.51#ibcon#read 4, iclass 37, count 0 2006.231.08:09:48.51#ibcon#about to read 5, iclass 37, count 0 2006.231.08:09:48.51#ibcon#read 5, iclass 37, count 0 2006.231.08:09:48.51#ibcon#about to read 6, iclass 37, count 0 2006.231.08:09:48.51#ibcon#read 6, iclass 37, count 0 2006.231.08:09:48.51#ibcon#end of sib2, iclass 37, count 0 2006.231.08:09:48.51#ibcon#*after write, iclass 37, count 0 2006.231.08:09:48.51#ibcon#*before return 0, iclass 37, count 0 2006.231.08:09:48.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:09:48.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:09:48.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:09:48.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:09:48.51$vc4f8/valo=3,672.99 2006.231.08:09:48.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.08:09:48.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.08:09:48.51#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:48.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:09:48.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:09:48.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:09:48.51#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:09:48.51#ibcon#first serial, iclass 39, count 0 2006.231.08:09:48.51#ibcon#enter sib2, iclass 39, count 0 2006.231.08:09:48.51#ibcon#flushed, iclass 39, count 0 2006.231.08:09:48.51#ibcon#about to write, iclass 39, count 0 2006.231.08:09:48.51#ibcon#wrote, iclass 39, count 0 2006.231.08:09:48.51#ibcon#about to read 3, iclass 39, count 0 2006.231.08:09:48.54#ibcon#read 3, iclass 39, count 0 2006.231.08:09:48.54#ibcon#about to read 4, iclass 39, count 0 2006.231.08:09:48.54#ibcon#read 4, iclass 39, count 0 2006.231.08:09:48.54#ibcon#about to read 5, iclass 39, count 0 2006.231.08:09:48.54#ibcon#read 5, iclass 39, count 0 2006.231.08:09:48.54#ibcon#about to read 6, iclass 39, count 0 2006.231.08:09:48.54#ibcon#read 6, iclass 39, count 0 2006.231.08:09:48.54#ibcon#end of sib2, iclass 39, count 0 2006.231.08:09:48.54#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:09:48.54#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:09:48.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:09:48.54#ibcon#*before write, iclass 39, count 0 2006.231.08:09:48.54#ibcon#enter sib2, iclass 39, count 0 2006.231.08:09:48.54#ibcon#flushed, iclass 39, count 0 2006.231.08:09:48.54#ibcon#about to write, iclass 39, count 0 2006.231.08:09:48.54#ibcon#wrote, iclass 39, count 0 2006.231.08:09:48.54#ibcon#about to read 3, iclass 39, count 0 2006.231.08:09:48.58#ibcon#read 3, iclass 39, count 0 2006.231.08:09:48.58#ibcon#about to read 4, iclass 39, count 0 2006.231.08:09:48.58#ibcon#read 4, iclass 39, count 0 2006.231.08:09:48.58#ibcon#about to read 5, iclass 39, count 0 2006.231.08:09:48.58#ibcon#read 5, iclass 39, count 0 2006.231.08:09:48.58#ibcon#about to read 6, iclass 39, count 0 2006.231.08:09:48.58#ibcon#read 6, iclass 39, count 0 2006.231.08:09:48.58#ibcon#end of sib2, iclass 39, count 0 2006.231.08:09:48.58#ibcon#*after write, iclass 39, count 0 2006.231.08:09:48.58#ibcon#*before return 0, iclass 39, count 0 2006.231.08:09:48.58#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:09:48.58#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:09:48.58#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:09:48.58#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:09:48.58$vc4f8/va=3,8 2006.231.08:09:48.58#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.231.08:09:48.58#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.231.08:09:48.58#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:48.58#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:09:48.64#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:09:48.64#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:09:48.64#ibcon#enter wrdev, iclass 3, count 2 2006.231.08:09:48.64#ibcon#first serial, iclass 3, count 2 2006.231.08:09:48.64#ibcon#enter sib2, iclass 3, count 2 2006.231.08:09:48.64#ibcon#flushed, iclass 3, count 2 2006.231.08:09:48.64#ibcon#about to write, iclass 3, count 2 2006.231.08:09:48.64#ibcon#wrote, iclass 3, count 2 2006.231.08:09:48.64#ibcon#about to read 3, iclass 3, count 2 2006.231.08:09:48.65#ibcon#read 3, iclass 3, count 2 2006.231.08:09:48.65#ibcon#about to read 4, iclass 3, count 2 2006.231.08:09:48.65#ibcon#read 4, iclass 3, count 2 2006.231.08:09:48.65#ibcon#about to read 5, iclass 3, count 2 2006.231.08:09:48.65#ibcon#read 5, iclass 3, count 2 2006.231.08:09:48.65#ibcon#about to read 6, iclass 3, count 2 2006.231.08:09:48.65#ibcon#read 6, iclass 3, count 2 2006.231.08:09:48.65#ibcon#end of sib2, iclass 3, count 2 2006.231.08:09:48.65#ibcon#*mode == 0, iclass 3, count 2 2006.231.08:09:48.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.231.08:09:48.65#ibcon#[25=AT03-08\r\n] 2006.231.08:09:48.65#ibcon#*before write, iclass 3, count 2 2006.231.08:09:48.65#ibcon#enter sib2, iclass 3, count 2 2006.231.08:09:48.65#ibcon#flushed, iclass 3, count 2 2006.231.08:09:48.65#ibcon#about to write, iclass 3, count 2 2006.231.08:09:48.65#ibcon#wrote, iclass 3, count 2 2006.231.08:09:48.65#ibcon#about to read 3, iclass 3, count 2 2006.231.08:09:48.68#ibcon#read 3, iclass 3, count 2 2006.231.08:09:48.68#ibcon#about to read 4, iclass 3, count 2 2006.231.08:09:48.68#ibcon#read 4, iclass 3, count 2 2006.231.08:09:48.68#ibcon#about to read 5, iclass 3, count 2 2006.231.08:09:48.68#ibcon#read 5, iclass 3, count 2 2006.231.08:09:48.68#ibcon#about to read 6, iclass 3, count 2 2006.231.08:09:48.68#ibcon#read 6, iclass 3, count 2 2006.231.08:09:48.68#ibcon#end of sib2, iclass 3, count 2 2006.231.08:09:48.68#ibcon#*after write, iclass 3, count 2 2006.231.08:09:48.68#ibcon#*before return 0, iclass 3, count 2 2006.231.08:09:48.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:09:48.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:09:48.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.231.08:09:48.68#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:48.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:09:48.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:09:48.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:09:48.80#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:09:48.80#ibcon#first serial, iclass 3, count 0 2006.231.08:09:48.80#ibcon#enter sib2, iclass 3, count 0 2006.231.08:09:48.80#ibcon#flushed, iclass 3, count 0 2006.231.08:09:48.80#ibcon#about to write, iclass 3, count 0 2006.231.08:09:48.80#ibcon#wrote, iclass 3, count 0 2006.231.08:09:48.80#ibcon#about to read 3, iclass 3, count 0 2006.231.08:09:48.82#ibcon#read 3, iclass 3, count 0 2006.231.08:09:48.82#ibcon#about to read 4, iclass 3, count 0 2006.231.08:09:48.82#ibcon#read 4, iclass 3, count 0 2006.231.08:09:48.82#ibcon#about to read 5, iclass 3, count 0 2006.231.08:09:48.82#ibcon#read 5, iclass 3, count 0 2006.231.08:09:48.82#ibcon#about to read 6, iclass 3, count 0 2006.231.08:09:48.82#ibcon#read 6, iclass 3, count 0 2006.231.08:09:48.82#ibcon#end of sib2, iclass 3, count 0 2006.231.08:09:48.82#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:09:48.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:09:48.82#ibcon#[25=USB\r\n] 2006.231.08:09:48.82#ibcon#*before write, iclass 3, count 0 2006.231.08:09:48.82#ibcon#enter sib2, iclass 3, count 0 2006.231.08:09:48.82#ibcon#flushed, iclass 3, count 0 2006.231.08:09:48.82#ibcon#about to write, iclass 3, count 0 2006.231.08:09:48.82#ibcon#wrote, iclass 3, count 0 2006.231.08:09:48.82#ibcon#about to read 3, iclass 3, count 0 2006.231.08:09:48.85#ibcon#read 3, iclass 3, count 0 2006.231.08:09:48.85#ibcon#about to read 4, iclass 3, count 0 2006.231.08:09:48.85#ibcon#read 4, iclass 3, count 0 2006.231.08:09:48.85#ibcon#about to read 5, iclass 3, count 0 2006.231.08:09:48.85#ibcon#read 5, iclass 3, count 0 2006.231.08:09:48.85#ibcon#about to read 6, iclass 3, count 0 2006.231.08:09:48.85#ibcon#read 6, iclass 3, count 0 2006.231.08:09:48.85#ibcon#end of sib2, iclass 3, count 0 2006.231.08:09:48.85#ibcon#*after write, iclass 3, count 0 2006.231.08:09:48.85#ibcon#*before return 0, iclass 3, count 0 2006.231.08:09:48.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:09:48.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:09:48.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:09:48.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:09:48.85$vc4f8/valo=4,832.99 2006.231.08:09:48.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.231.08:09:48.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.231.08:09:48.85#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:48.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:09:48.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:09:48.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:09:48.85#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:09:48.85#ibcon#first serial, iclass 5, count 0 2006.231.08:09:48.85#ibcon#enter sib2, iclass 5, count 0 2006.231.08:09:48.85#ibcon#flushed, iclass 5, count 0 2006.231.08:09:48.85#ibcon#about to write, iclass 5, count 0 2006.231.08:09:48.85#ibcon#wrote, iclass 5, count 0 2006.231.08:09:48.85#ibcon#about to read 3, iclass 5, count 0 2006.231.08:09:48.87#ibcon#read 3, iclass 5, count 0 2006.231.08:09:48.87#ibcon#about to read 4, iclass 5, count 0 2006.231.08:09:48.87#ibcon#read 4, iclass 5, count 0 2006.231.08:09:48.87#ibcon#about to read 5, iclass 5, count 0 2006.231.08:09:48.87#ibcon#read 5, iclass 5, count 0 2006.231.08:09:48.87#ibcon#about to read 6, iclass 5, count 0 2006.231.08:09:48.87#ibcon#read 6, iclass 5, count 0 2006.231.08:09:48.87#ibcon#end of sib2, iclass 5, count 0 2006.231.08:09:48.87#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:09:48.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:09:48.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:09:48.87#ibcon#*before write, iclass 5, count 0 2006.231.08:09:48.87#ibcon#enter sib2, iclass 5, count 0 2006.231.08:09:48.87#ibcon#flushed, iclass 5, count 0 2006.231.08:09:48.87#ibcon#about to write, iclass 5, count 0 2006.231.08:09:48.87#ibcon#wrote, iclass 5, count 0 2006.231.08:09:48.87#ibcon#about to read 3, iclass 5, count 0 2006.231.08:09:48.91#ibcon#read 3, iclass 5, count 0 2006.231.08:09:48.91#ibcon#about to read 4, iclass 5, count 0 2006.231.08:09:48.91#ibcon#read 4, iclass 5, count 0 2006.231.08:09:48.91#ibcon#about to read 5, iclass 5, count 0 2006.231.08:09:48.91#ibcon#read 5, iclass 5, count 0 2006.231.08:09:48.91#ibcon#about to read 6, iclass 5, count 0 2006.231.08:09:48.91#ibcon#read 6, iclass 5, count 0 2006.231.08:09:48.91#ibcon#end of sib2, iclass 5, count 0 2006.231.08:09:48.91#ibcon#*after write, iclass 5, count 0 2006.231.08:09:48.91#ibcon#*before return 0, iclass 5, count 0 2006.231.08:09:48.91#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:09:48.91#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:09:48.91#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:09:48.91#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:09:48.91$vc4f8/va=4,7 2006.231.08:09:48.91#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.231.08:09:48.91#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.231.08:09:48.91#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:48.91#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:09:48.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:09:48.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:09:48.97#ibcon#enter wrdev, iclass 7, count 2 2006.231.08:09:48.97#ibcon#first serial, iclass 7, count 2 2006.231.08:09:48.97#ibcon#enter sib2, iclass 7, count 2 2006.231.08:09:48.97#ibcon#flushed, iclass 7, count 2 2006.231.08:09:48.97#ibcon#about to write, iclass 7, count 2 2006.231.08:09:48.97#ibcon#wrote, iclass 7, count 2 2006.231.08:09:48.97#ibcon#about to read 3, iclass 7, count 2 2006.231.08:09:48.99#ibcon#read 3, iclass 7, count 2 2006.231.08:09:48.99#ibcon#about to read 4, iclass 7, count 2 2006.231.08:09:48.99#ibcon#read 4, iclass 7, count 2 2006.231.08:09:48.99#ibcon#about to read 5, iclass 7, count 2 2006.231.08:09:48.99#ibcon#read 5, iclass 7, count 2 2006.231.08:09:48.99#ibcon#about to read 6, iclass 7, count 2 2006.231.08:09:48.99#ibcon#read 6, iclass 7, count 2 2006.231.08:09:48.99#ibcon#end of sib2, iclass 7, count 2 2006.231.08:09:48.99#ibcon#*mode == 0, iclass 7, count 2 2006.231.08:09:48.99#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.231.08:09:48.99#ibcon#[25=AT04-07\r\n] 2006.231.08:09:48.99#ibcon#*before write, iclass 7, count 2 2006.231.08:09:48.99#ibcon#enter sib2, iclass 7, count 2 2006.231.08:09:48.99#ibcon#flushed, iclass 7, count 2 2006.231.08:09:48.99#ibcon#about to write, iclass 7, count 2 2006.231.08:09:48.99#ibcon#wrote, iclass 7, count 2 2006.231.08:09:48.99#ibcon#about to read 3, iclass 7, count 2 2006.231.08:09:49.03#ibcon#read 3, iclass 7, count 2 2006.231.08:09:49.03#ibcon#about to read 4, iclass 7, count 2 2006.231.08:09:49.03#ibcon#read 4, iclass 7, count 2 2006.231.08:09:49.03#ibcon#about to read 5, iclass 7, count 2 2006.231.08:09:49.03#ibcon#read 5, iclass 7, count 2 2006.231.08:09:49.03#ibcon#about to read 6, iclass 7, count 2 2006.231.08:09:49.03#ibcon#read 6, iclass 7, count 2 2006.231.08:09:49.03#ibcon#end of sib2, iclass 7, count 2 2006.231.08:09:49.03#ibcon#*after write, iclass 7, count 2 2006.231.08:09:49.03#ibcon#*before return 0, iclass 7, count 2 2006.231.08:09:49.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:09:49.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:09:49.03#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.231.08:09:49.03#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:49.03#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:09:49.14#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:09:49.14#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:09:49.14#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:09:49.14#ibcon#first serial, iclass 7, count 0 2006.231.08:09:49.14#ibcon#enter sib2, iclass 7, count 0 2006.231.08:09:49.14#ibcon#flushed, iclass 7, count 0 2006.231.08:09:49.14#ibcon#about to write, iclass 7, count 0 2006.231.08:09:49.14#ibcon#wrote, iclass 7, count 0 2006.231.08:09:49.14#ibcon#about to read 3, iclass 7, count 0 2006.231.08:09:49.16#ibcon#read 3, iclass 7, count 0 2006.231.08:09:49.16#ibcon#about to read 4, iclass 7, count 0 2006.231.08:09:49.16#ibcon#read 4, iclass 7, count 0 2006.231.08:09:49.16#ibcon#about to read 5, iclass 7, count 0 2006.231.08:09:49.16#ibcon#read 5, iclass 7, count 0 2006.231.08:09:49.16#ibcon#about to read 6, iclass 7, count 0 2006.231.08:09:49.16#ibcon#read 6, iclass 7, count 0 2006.231.08:09:49.16#ibcon#end of sib2, iclass 7, count 0 2006.231.08:09:49.16#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:09:49.16#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:09:49.16#ibcon#[25=USB\r\n] 2006.231.08:09:49.16#ibcon#*before write, iclass 7, count 0 2006.231.08:09:49.16#ibcon#enter sib2, iclass 7, count 0 2006.231.08:09:49.16#ibcon#flushed, iclass 7, count 0 2006.231.08:09:49.16#ibcon#about to write, iclass 7, count 0 2006.231.08:09:49.16#ibcon#wrote, iclass 7, count 0 2006.231.08:09:49.16#ibcon#about to read 3, iclass 7, count 0 2006.231.08:09:49.19#ibcon#read 3, iclass 7, count 0 2006.231.08:09:49.19#ibcon#about to read 4, iclass 7, count 0 2006.231.08:09:49.19#ibcon#read 4, iclass 7, count 0 2006.231.08:09:49.19#ibcon#about to read 5, iclass 7, count 0 2006.231.08:09:49.19#ibcon#read 5, iclass 7, count 0 2006.231.08:09:49.19#ibcon#about to read 6, iclass 7, count 0 2006.231.08:09:49.19#ibcon#read 6, iclass 7, count 0 2006.231.08:09:49.19#ibcon#end of sib2, iclass 7, count 0 2006.231.08:09:49.19#ibcon#*after write, iclass 7, count 0 2006.231.08:09:49.19#ibcon#*before return 0, iclass 7, count 0 2006.231.08:09:49.19#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:09:49.19#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:09:49.19#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:09:49.19#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:09:49.19$vc4f8/valo=5,652.99 2006.231.08:09:49.19#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.231.08:09:49.19#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.231.08:09:49.19#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:49.19#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:09:49.19#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:09:49.19#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:09:49.19#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:09:49.19#ibcon#first serial, iclass 11, count 0 2006.231.08:09:49.19#ibcon#enter sib2, iclass 11, count 0 2006.231.08:09:49.19#ibcon#flushed, iclass 11, count 0 2006.231.08:09:49.19#ibcon#about to write, iclass 11, count 0 2006.231.08:09:49.19#ibcon#wrote, iclass 11, count 0 2006.231.08:09:49.19#ibcon#about to read 3, iclass 11, count 0 2006.231.08:09:49.21#ibcon#read 3, iclass 11, count 0 2006.231.08:09:49.21#ibcon#about to read 4, iclass 11, count 0 2006.231.08:09:49.21#ibcon#read 4, iclass 11, count 0 2006.231.08:09:49.21#ibcon#about to read 5, iclass 11, count 0 2006.231.08:09:49.21#ibcon#read 5, iclass 11, count 0 2006.231.08:09:49.21#ibcon#about to read 6, iclass 11, count 0 2006.231.08:09:49.21#ibcon#read 6, iclass 11, count 0 2006.231.08:09:49.21#ibcon#end of sib2, iclass 11, count 0 2006.231.08:09:49.21#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:09:49.21#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:09:49.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:09:49.21#ibcon#*before write, iclass 11, count 0 2006.231.08:09:49.21#ibcon#enter sib2, iclass 11, count 0 2006.231.08:09:49.21#ibcon#flushed, iclass 11, count 0 2006.231.08:09:49.21#ibcon#about to write, iclass 11, count 0 2006.231.08:09:49.21#ibcon#wrote, iclass 11, count 0 2006.231.08:09:49.21#ibcon#about to read 3, iclass 11, count 0 2006.231.08:09:49.26#ibcon#read 3, iclass 11, count 0 2006.231.08:09:49.26#ibcon#about to read 4, iclass 11, count 0 2006.231.08:09:49.26#ibcon#read 4, iclass 11, count 0 2006.231.08:09:49.26#ibcon#about to read 5, iclass 11, count 0 2006.231.08:09:49.26#ibcon#read 5, iclass 11, count 0 2006.231.08:09:49.26#ibcon#about to read 6, iclass 11, count 0 2006.231.08:09:49.26#ibcon#read 6, iclass 11, count 0 2006.231.08:09:49.26#ibcon#end of sib2, iclass 11, count 0 2006.231.08:09:49.26#ibcon#*after write, iclass 11, count 0 2006.231.08:09:49.26#ibcon#*before return 0, iclass 11, count 0 2006.231.08:09:49.26#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:09:49.26#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:09:49.26#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:09:49.26#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:09:49.26$vc4f8/va=5,7 2006.231.08:09:49.26#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.231.08:09:49.26#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.231.08:09:49.26#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:49.26#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:09:49.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:09:49.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:09:49.30#ibcon#enter wrdev, iclass 13, count 2 2006.231.08:09:49.30#ibcon#first serial, iclass 13, count 2 2006.231.08:09:49.30#ibcon#enter sib2, iclass 13, count 2 2006.231.08:09:49.30#ibcon#flushed, iclass 13, count 2 2006.231.08:09:49.30#ibcon#about to write, iclass 13, count 2 2006.231.08:09:49.30#ibcon#wrote, iclass 13, count 2 2006.231.08:09:49.30#ibcon#about to read 3, iclass 13, count 2 2006.231.08:09:49.32#ibcon#read 3, iclass 13, count 2 2006.231.08:09:49.32#ibcon#about to read 4, iclass 13, count 2 2006.231.08:09:49.32#ibcon#read 4, iclass 13, count 2 2006.231.08:09:49.32#ibcon#about to read 5, iclass 13, count 2 2006.231.08:09:49.32#ibcon#read 5, iclass 13, count 2 2006.231.08:09:49.32#ibcon#about to read 6, iclass 13, count 2 2006.231.08:09:49.32#ibcon#read 6, iclass 13, count 2 2006.231.08:09:49.32#ibcon#end of sib2, iclass 13, count 2 2006.231.08:09:49.32#ibcon#*mode == 0, iclass 13, count 2 2006.231.08:09:49.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.231.08:09:49.32#ibcon#[25=AT05-07\r\n] 2006.231.08:09:49.32#ibcon#*before write, iclass 13, count 2 2006.231.08:09:49.32#ibcon#enter sib2, iclass 13, count 2 2006.231.08:09:49.32#ibcon#flushed, iclass 13, count 2 2006.231.08:09:49.32#ibcon#about to write, iclass 13, count 2 2006.231.08:09:49.32#ibcon#wrote, iclass 13, count 2 2006.231.08:09:49.32#ibcon#about to read 3, iclass 13, count 2 2006.231.08:09:49.35#ibcon#read 3, iclass 13, count 2 2006.231.08:09:49.35#ibcon#about to read 4, iclass 13, count 2 2006.231.08:09:49.35#ibcon#read 4, iclass 13, count 2 2006.231.08:09:49.35#ibcon#about to read 5, iclass 13, count 2 2006.231.08:09:49.35#ibcon#read 5, iclass 13, count 2 2006.231.08:09:49.35#ibcon#about to read 6, iclass 13, count 2 2006.231.08:09:49.35#ibcon#read 6, iclass 13, count 2 2006.231.08:09:49.35#ibcon#end of sib2, iclass 13, count 2 2006.231.08:09:49.35#ibcon#*after write, iclass 13, count 2 2006.231.08:09:49.35#ibcon#*before return 0, iclass 13, count 2 2006.231.08:09:49.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:09:49.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:09:49.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.231.08:09:49.35#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:49.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:09:49.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:09:49.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:09:49.47#ibcon#enter wrdev, iclass 13, count 0 2006.231.08:09:49.47#ibcon#first serial, iclass 13, count 0 2006.231.08:09:49.47#ibcon#enter sib2, iclass 13, count 0 2006.231.08:09:49.47#ibcon#flushed, iclass 13, count 0 2006.231.08:09:49.47#ibcon#about to write, iclass 13, count 0 2006.231.08:09:49.47#ibcon#wrote, iclass 13, count 0 2006.231.08:09:49.47#ibcon#about to read 3, iclass 13, count 0 2006.231.08:09:49.50#ibcon#read 3, iclass 13, count 0 2006.231.08:09:49.50#ibcon#about to read 4, iclass 13, count 0 2006.231.08:09:49.50#ibcon#read 4, iclass 13, count 0 2006.231.08:09:49.50#ibcon#about to read 5, iclass 13, count 0 2006.231.08:09:49.50#ibcon#read 5, iclass 13, count 0 2006.231.08:09:49.50#ibcon#about to read 6, iclass 13, count 0 2006.231.08:09:49.50#ibcon#read 6, iclass 13, count 0 2006.231.08:09:49.50#ibcon#end of sib2, iclass 13, count 0 2006.231.08:09:49.50#ibcon#*mode == 0, iclass 13, count 0 2006.231.08:09:49.50#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.08:09:49.50#ibcon#[25=USB\r\n] 2006.231.08:09:49.50#ibcon#*before write, iclass 13, count 0 2006.231.08:09:49.50#ibcon#enter sib2, iclass 13, count 0 2006.231.08:09:49.50#ibcon#flushed, iclass 13, count 0 2006.231.08:09:49.50#ibcon#about to write, iclass 13, count 0 2006.231.08:09:49.50#ibcon#wrote, iclass 13, count 0 2006.231.08:09:49.50#ibcon#about to read 3, iclass 13, count 0 2006.231.08:09:49.52#ibcon#read 3, iclass 13, count 0 2006.231.08:09:49.52#ibcon#about to read 4, iclass 13, count 0 2006.231.08:09:49.52#ibcon#read 4, iclass 13, count 0 2006.231.08:09:49.52#ibcon#about to read 5, iclass 13, count 0 2006.231.08:09:49.52#ibcon#read 5, iclass 13, count 0 2006.231.08:09:49.52#ibcon#about to read 6, iclass 13, count 0 2006.231.08:09:49.52#ibcon#read 6, iclass 13, count 0 2006.231.08:09:49.52#ibcon#end of sib2, iclass 13, count 0 2006.231.08:09:49.52#ibcon#*after write, iclass 13, count 0 2006.231.08:09:49.52#ibcon#*before return 0, iclass 13, count 0 2006.231.08:09:49.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:09:49.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:09:49.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.08:09:49.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.08:09:49.52$vc4f8/valo=6,772.99 2006.231.08:09:49.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.08:09:49.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.08:09:49.52#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:49.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:09:49.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:09:49.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:09:49.52#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:09:49.52#ibcon#first serial, iclass 15, count 0 2006.231.08:09:49.52#ibcon#enter sib2, iclass 15, count 0 2006.231.08:09:49.52#ibcon#flushed, iclass 15, count 0 2006.231.08:09:49.52#ibcon#about to write, iclass 15, count 0 2006.231.08:09:49.52#ibcon#wrote, iclass 15, count 0 2006.231.08:09:49.52#ibcon#about to read 3, iclass 15, count 0 2006.231.08:09:49.54#ibcon#read 3, iclass 15, count 0 2006.231.08:09:49.54#ibcon#about to read 4, iclass 15, count 0 2006.231.08:09:49.54#ibcon#read 4, iclass 15, count 0 2006.231.08:09:49.54#ibcon#about to read 5, iclass 15, count 0 2006.231.08:09:49.54#ibcon#read 5, iclass 15, count 0 2006.231.08:09:49.54#ibcon#about to read 6, iclass 15, count 0 2006.231.08:09:49.54#ibcon#read 6, iclass 15, count 0 2006.231.08:09:49.54#ibcon#end of sib2, iclass 15, count 0 2006.231.08:09:49.54#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:09:49.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:09:49.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:09:49.54#ibcon#*before write, iclass 15, count 0 2006.231.08:09:49.54#ibcon#enter sib2, iclass 15, count 0 2006.231.08:09:49.54#ibcon#flushed, iclass 15, count 0 2006.231.08:09:49.54#ibcon#about to write, iclass 15, count 0 2006.231.08:09:49.54#ibcon#wrote, iclass 15, count 0 2006.231.08:09:49.54#ibcon#about to read 3, iclass 15, count 0 2006.231.08:09:49.58#ibcon#read 3, iclass 15, count 0 2006.231.08:09:49.58#ibcon#about to read 4, iclass 15, count 0 2006.231.08:09:49.58#ibcon#read 4, iclass 15, count 0 2006.231.08:09:49.58#ibcon#about to read 5, iclass 15, count 0 2006.231.08:09:49.58#ibcon#read 5, iclass 15, count 0 2006.231.08:09:49.58#ibcon#about to read 6, iclass 15, count 0 2006.231.08:09:49.58#ibcon#read 6, iclass 15, count 0 2006.231.08:09:49.58#ibcon#end of sib2, iclass 15, count 0 2006.231.08:09:49.58#ibcon#*after write, iclass 15, count 0 2006.231.08:09:49.58#ibcon#*before return 0, iclass 15, count 0 2006.231.08:09:49.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:09:49.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:09:49.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:09:49.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:09:49.58$vc4f8/va=6,6 2006.231.08:09:49.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.08:09:49.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.08:09:49.58#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:49.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:09:49.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:09:49.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:09:49.64#ibcon#enter wrdev, iclass 17, count 2 2006.231.08:09:49.64#ibcon#first serial, iclass 17, count 2 2006.231.08:09:49.64#ibcon#enter sib2, iclass 17, count 2 2006.231.08:09:49.64#ibcon#flushed, iclass 17, count 2 2006.231.08:09:49.64#ibcon#about to write, iclass 17, count 2 2006.231.08:09:49.64#ibcon#wrote, iclass 17, count 2 2006.231.08:09:49.64#ibcon#about to read 3, iclass 17, count 2 2006.231.08:09:49.66#ibcon#read 3, iclass 17, count 2 2006.231.08:09:49.66#ibcon#about to read 4, iclass 17, count 2 2006.231.08:09:49.66#ibcon#read 4, iclass 17, count 2 2006.231.08:09:49.66#ibcon#about to read 5, iclass 17, count 2 2006.231.08:09:49.66#ibcon#read 5, iclass 17, count 2 2006.231.08:09:49.66#ibcon#about to read 6, iclass 17, count 2 2006.231.08:09:49.66#ibcon#read 6, iclass 17, count 2 2006.231.08:09:49.66#ibcon#end of sib2, iclass 17, count 2 2006.231.08:09:49.66#ibcon#*mode == 0, iclass 17, count 2 2006.231.08:09:49.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.08:09:49.66#ibcon#[25=AT06-06\r\n] 2006.231.08:09:49.66#ibcon#*before write, iclass 17, count 2 2006.231.08:09:49.66#ibcon#enter sib2, iclass 17, count 2 2006.231.08:09:49.66#ibcon#flushed, iclass 17, count 2 2006.231.08:09:49.66#ibcon#about to write, iclass 17, count 2 2006.231.08:09:49.66#ibcon#wrote, iclass 17, count 2 2006.231.08:09:49.66#ibcon#about to read 3, iclass 17, count 2 2006.231.08:09:49.69#ibcon#read 3, iclass 17, count 2 2006.231.08:09:49.69#ibcon#about to read 4, iclass 17, count 2 2006.231.08:09:49.69#ibcon#read 4, iclass 17, count 2 2006.231.08:09:49.69#ibcon#about to read 5, iclass 17, count 2 2006.231.08:09:49.69#ibcon#read 5, iclass 17, count 2 2006.231.08:09:49.69#ibcon#about to read 6, iclass 17, count 2 2006.231.08:09:49.69#ibcon#read 6, iclass 17, count 2 2006.231.08:09:49.69#ibcon#end of sib2, iclass 17, count 2 2006.231.08:09:49.69#ibcon#*after write, iclass 17, count 2 2006.231.08:09:49.69#ibcon#*before return 0, iclass 17, count 2 2006.231.08:09:49.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:09:49.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:09:49.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.08:09:49.69#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:49.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:09:49.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:09:49.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:09:49.81#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:09:49.81#ibcon#first serial, iclass 17, count 0 2006.231.08:09:49.81#ibcon#enter sib2, iclass 17, count 0 2006.231.08:09:49.81#ibcon#flushed, iclass 17, count 0 2006.231.08:09:49.81#ibcon#about to write, iclass 17, count 0 2006.231.08:09:49.81#ibcon#wrote, iclass 17, count 0 2006.231.08:09:49.81#ibcon#about to read 3, iclass 17, count 0 2006.231.08:09:49.83#ibcon#read 3, iclass 17, count 0 2006.231.08:09:49.83#ibcon#about to read 4, iclass 17, count 0 2006.231.08:09:49.83#ibcon#read 4, iclass 17, count 0 2006.231.08:09:49.83#ibcon#about to read 5, iclass 17, count 0 2006.231.08:09:49.83#ibcon#read 5, iclass 17, count 0 2006.231.08:09:49.83#ibcon#about to read 6, iclass 17, count 0 2006.231.08:09:49.83#ibcon#read 6, iclass 17, count 0 2006.231.08:09:49.83#ibcon#end of sib2, iclass 17, count 0 2006.231.08:09:49.83#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:09:49.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:09:49.83#ibcon#[25=USB\r\n] 2006.231.08:09:49.83#ibcon#*before write, iclass 17, count 0 2006.231.08:09:49.83#ibcon#enter sib2, iclass 17, count 0 2006.231.08:09:49.83#ibcon#flushed, iclass 17, count 0 2006.231.08:09:49.83#ibcon#about to write, iclass 17, count 0 2006.231.08:09:49.83#ibcon#wrote, iclass 17, count 0 2006.231.08:09:49.83#ibcon#about to read 3, iclass 17, count 0 2006.231.08:09:49.86#ibcon#read 3, iclass 17, count 0 2006.231.08:09:49.86#ibcon#about to read 4, iclass 17, count 0 2006.231.08:09:49.86#ibcon#read 4, iclass 17, count 0 2006.231.08:09:49.86#ibcon#about to read 5, iclass 17, count 0 2006.231.08:09:49.86#ibcon#read 5, iclass 17, count 0 2006.231.08:09:49.86#ibcon#about to read 6, iclass 17, count 0 2006.231.08:09:49.86#ibcon#read 6, iclass 17, count 0 2006.231.08:09:49.86#ibcon#end of sib2, iclass 17, count 0 2006.231.08:09:49.86#ibcon#*after write, iclass 17, count 0 2006.231.08:09:49.86#ibcon#*before return 0, iclass 17, count 0 2006.231.08:09:49.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:09:49.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:09:49.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:09:49.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:09:49.86$vc4f8/valo=7,832.99 2006.231.08:09:49.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.08:09:49.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.08:09:49.86#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:49.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:09:49.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:09:49.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:09:49.86#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:09:49.86#ibcon#first serial, iclass 19, count 0 2006.231.08:09:49.86#ibcon#enter sib2, iclass 19, count 0 2006.231.08:09:49.86#ibcon#flushed, iclass 19, count 0 2006.231.08:09:49.86#ibcon#about to write, iclass 19, count 0 2006.231.08:09:49.86#ibcon#wrote, iclass 19, count 0 2006.231.08:09:49.86#ibcon#about to read 3, iclass 19, count 0 2006.231.08:09:49.88#ibcon#read 3, iclass 19, count 0 2006.231.08:09:49.88#ibcon#about to read 4, iclass 19, count 0 2006.231.08:09:49.88#ibcon#read 4, iclass 19, count 0 2006.231.08:09:49.88#ibcon#about to read 5, iclass 19, count 0 2006.231.08:09:49.88#ibcon#read 5, iclass 19, count 0 2006.231.08:09:49.88#ibcon#about to read 6, iclass 19, count 0 2006.231.08:09:49.88#ibcon#read 6, iclass 19, count 0 2006.231.08:09:49.88#ibcon#end of sib2, iclass 19, count 0 2006.231.08:09:49.88#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:09:49.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:09:49.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:09:49.88#ibcon#*before write, iclass 19, count 0 2006.231.08:09:49.88#ibcon#enter sib2, iclass 19, count 0 2006.231.08:09:49.88#ibcon#flushed, iclass 19, count 0 2006.231.08:09:49.88#ibcon#about to write, iclass 19, count 0 2006.231.08:09:49.88#ibcon#wrote, iclass 19, count 0 2006.231.08:09:49.88#ibcon#about to read 3, iclass 19, count 0 2006.231.08:09:49.92#ibcon#read 3, iclass 19, count 0 2006.231.08:09:49.92#ibcon#about to read 4, iclass 19, count 0 2006.231.08:09:49.92#ibcon#read 4, iclass 19, count 0 2006.231.08:09:49.92#ibcon#about to read 5, iclass 19, count 0 2006.231.08:09:49.92#ibcon#read 5, iclass 19, count 0 2006.231.08:09:49.92#ibcon#about to read 6, iclass 19, count 0 2006.231.08:09:49.92#ibcon#read 6, iclass 19, count 0 2006.231.08:09:49.92#ibcon#end of sib2, iclass 19, count 0 2006.231.08:09:49.92#ibcon#*after write, iclass 19, count 0 2006.231.08:09:49.92#ibcon#*before return 0, iclass 19, count 0 2006.231.08:09:49.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:09:49.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:09:49.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:09:49.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:09:49.92$vc4f8/va=7,6 2006.231.08:09:49.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.231.08:09:49.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.231.08:09:49.92#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:49.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:09:49.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:09:49.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:09:49.98#ibcon#enter wrdev, iclass 21, count 2 2006.231.08:09:49.98#ibcon#first serial, iclass 21, count 2 2006.231.08:09:49.98#ibcon#enter sib2, iclass 21, count 2 2006.231.08:09:49.98#ibcon#flushed, iclass 21, count 2 2006.231.08:09:49.98#ibcon#about to write, iclass 21, count 2 2006.231.08:09:49.98#ibcon#wrote, iclass 21, count 2 2006.231.08:09:49.98#ibcon#about to read 3, iclass 21, count 2 2006.231.08:09:50.01#ibcon#read 3, iclass 21, count 2 2006.231.08:09:50.01#ibcon#about to read 4, iclass 21, count 2 2006.231.08:09:50.01#ibcon#read 4, iclass 21, count 2 2006.231.08:09:50.01#ibcon#about to read 5, iclass 21, count 2 2006.231.08:09:50.01#ibcon#read 5, iclass 21, count 2 2006.231.08:09:50.01#ibcon#about to read 6, iclass 21, count 2 2006.231.08:09:50.01#ibcon#read 6, iclass 21, count 2 2006.231.08:09:50.01#ibcon#end of sib2, iclass 21, count 2 2006.231.08:09:50.01#ibcon#*mode == 0, iclass 21, count 2 2006.231.08:09:50.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.231.08:09:50.01#ibcon#[25=AT07-06\r\n] 2006.231.08:09:50.01#ibcon#*before write, iclass 21, count 2 2006.231.08:09:50.01#ibcon#enter sib2, iclass 21, count 2 2006.231.08:09:50.01#ibcon#flushed, iclass 21, count 2 2006.231.08:09:50.01#ibcon#about to write, iclass 21, count 2 2006.231.08:09:50.01#ibcon#wrote, iclass 21, count 2 2006.231.08:09:50.01#ibcon#about to read 3, iclass 21, count 2 2006.231.08:09:50.04#ibcon#read 3, iclass 21, count 2 2006.231.08:09:50.04#ibcon#about to read 4, iclass 21, count 2 2006.231.08:09:50.04#ibcon#read 4, iclass 21, count 2 2006.231.08:09:50.04#ibcon#about to read 5, iclass 21, count 2 2006.231.08:09:50.04#ibcon#read 5, iclass 21, count 2 2006.231.08:09:50.04#ibcon#about to read 6, iclass 21, count 2 2006.231.08:09:50.04#ibcon#read 6, iclass 21, count 2 2006.231.08:09:50.04#ibcon#end of sib2, iclass 21, count 2 2006.231.08:09:50.04#ibcon#*after write, iclass 21, count 2 2006.231.08:09:50.04#ibcon#*before return 0, iclass 21, count 2 2006.231.08:09:50.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:09:50.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:09:50.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.231.08:09:50.04#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:50.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:09:50.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:09:50.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:09:50.16#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:09:50.16#ibcon#first serial, iclass 21, count 0 2006.231.08:09:50.16#ibcon#enter sib2, iclass 21, count 0 2006.231.08:09:50.16#ibcon#flushed, iclass 21, count 0 2006.231.08:09:50.16#ibcon#about to write, iclass 21, count 0 2006.231.08:09:50.16#ibcon#wrote, iclass 21, count 0 2006.231.08:09:50.16#ibcon#about to read 3, iclass 21, count 0 2006.231.08:09:50.18#ibcon#read 3, iclass 21, count 0 2006.231.08:09:50.18#ibcon#about to read 4, iclass 21, count 0 2006.231.08:09:50.18#ibcon#read 4, iclass 21, count 0 2006.231.08:09:50.18#ibcon#about to read 5, iclass 21, count 0 2006.231.08:09:50.18#ibcon#read 5, iclass 21, count 0 2006.231.08:09:50.18#ibcon#about to read 6, iclass 21, count 0 2006.231.08:09:50.18#ibcon#read 6, iclass 21, count 0 2006.231.08:09:50.18#ibcon#end of sib2, iclass 21, count 0 2006.231.08:09:50.18#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:09:50.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:09:50.18#ibcon#[25=USB\r\n] 2006.231.08:09:50.18#ibcon#*before write, iclass 21, count 0 2006.231.08:09:50.18#ibcon#enter sib2, iclass 21, count 0 2006.231.08:09:50.18#ibcon#flushed, iclass 21, count 0 2006.231.08:09:50.18#ibcon#about to write, iclass 21, count 0 2006.231.08:09:50.18#ibcon#wrote, iclass 21, count 0 2006.231.08:09:50.18#ibcon#about to read 3, iclass 21, count 0 2006.231.08:09:50.21#ibcon#read 3, iclass 21, count 0 2006.231.08:09:50.21#ibcon#about to read 4, iclass 21, count 0 2006.231.08:09:50.21#ibcon#read 4, iclass 21, count 0 2006.231.08:09:50.21#ibcon#about to read 5, iclass 21, count 0 2006.231.08:09:50.21#ibcon#read 5, iclass 21, count 0 2006.231.08:09:50.21#ibcon#about to read 6, iclass 21, count 0 2006.231.08:09:50.21#ibcon#read 6, iclass 21, count 0 2006.231.08:09:50.21#ibcon#end of sib2, iclass 21, count 0 2006.231.08:09:50.21#ibcon#*after write, iclass 21, count 0 2006.231.08:09:50.21#ibcon#*before return 0, iclass 21, count 0 2006.231.08:09:50.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:09:50.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:09:50.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:09:50.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:09:50.21$vc4f8/valo=8,852.99 2006.231.08:09:50.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.231.08:09:50.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.231.08:09:50.21#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:50.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:09:50.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:09:50.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:09:50.21#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:09:50.21#ibcon#first serial, iclass 23, count 0 2006.231.08:09:50.21#ibcon#enter sib2, iclass 23, count 0 2006.231.08:09:50.21#ibcon#flushed, iclass 23, count 0 2006.231.08:09:50.21#ibcon#about to write, iclass 23, count 0 2006.231.08:09:50.21#ibcon#wrote, iclass 23, count 0 2006.231.08:09:50.21#ibcon#about to read 3, iclass 23, count 0 2006.231.08:09:50.24#ibcon#read 3, iclass 23, count 0 2006.231.08:09:50.24#ibcon#about to read 4, iclass 23, count 0 2006.231.08:09:50.24#ibcon#read 4, iclass 23, count 0 2006.231.08:09:50.24#ibcon#about to read 5, iclass 23, count 0 2006.231.08:09:50.24#ibcon#read 5, iclass 23, count 0 2006.231.08:09:50.24#ibcon#about to read 6, iclass 23, count 0 2006.231.08:09:50.24#ibcon#read 6, iclass 23, count 0 2006.231.08:09:50.24#ibcon#end of sib2, iclass 23, count 0 2006.231.08:09:50.24#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:09:50.24#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:09:50.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:09:50.24#ibcon#*before write, iclass 23, count 0 2006.231.08:09:50.24#ibcon#enter sib2, iclass 23, count 0 2006.231.08:09:50.24#ibcon#flushed, iclass 23, count 0 2006.231.08:09:50.24#ibcon#about to write, iclass 23, count 0 2006.231.08:09:50.24#ibcon#wrote, iclass 23, count 0 2006.231.08:09:50.24#ibcon#about to read 3, iclass 23, count 0 2006.231.08:09:50.28#ibcon#read 3, iclass 23, count 0 2006.231.08:09:50.28#ibcon#about to read 4, iclass 23, count 0 2006.231.08:09:50.28#ibcon#read 4, iclass 23, count 0 2006.231.08:09:50.28#ibcon#about to read 5, iclass 23, count 0 2006.231.08:09:50.28#ibcon#read 5, iclass 23, count 0 2006.231.08:09:50.28#ibcon#about to read 6, iclass 23, count 0 2006.231.08:09:50.28#ibcon#read 6, iclass 23, count 0 2006.231.08:09:50.28#ibcon#end of sib2, iclass 23, count 0 2006.231.08:09:50.28#ibcon#*after write, iclass 23, count 0 2006.231.08:09:50.28#ibcon#*before return 0, iclass 23, count 0 2006.231.08:09:50.28#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:09:50.28#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:09:50.28#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:09:50.28#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:09:50.28$vc4f8/va=8,6 2006.231.08:09:50.28#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.231.08:09:50.28#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.231.08:09:50.28#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:50.28#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:09:50.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:09:50.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:09:50.33#ibcon#enter wrdev, iclass 25, count 2 2006.231.08:09:50.33#ibcon#first serial, iclass 25, count 2 2006.231.08:09:50.33#ibcon#enter sib2, iclass 25, count 2 2006.231.08:09:50.33#ibcon#flushed, iclass 25, count 2 2006.231.08:09:50.33#ibcon#about to write, iclass 25, count 2 2006.231.08:09:50.33#ibcon#wrote, iclass 25, count 2 2006.231.08:09:50.33#ibcon#about to read 3, iclass 25, count 2 2006.231.08:09:50.35#ibcon#read 3, iclass 25, count 2 2006.231.08:09:50.35#ibcon#about to read 4, iclass 25, count 2 2006.231.08:09:50.35#ibcon#read 4, iclass 25, count 2 2006.231.08:09:50.35#ibcon#about to read 5, iclass 25, count 2 2006.231.08:09:50.35#ibcon#read 5, iclass 25, count 2 2006.231.08:09:50.35#ibcon#about to read 6, iclass 25, count 2 2006.231.08:09:50.35#ibcon#read 6, iclass 25, count 2 2006.231.08:09:50.35#ibcon#end of sib2, iclass 25, count 2 2006.231.08:09:50.35#ibcon#*mode == 0, iclass 25, count 2 2006.231.08:09:50.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.231.08:09:50.35#ibcon#[25=AT08-06\r\n] 2006.231.08:09:50.35#ibcon#*before write, iclass 25, count 2 2006.231.08:09:50.35#ibcon#enter sib2, iclass 25, count 2 2006.231.08:09:50.35#ibcon#flushed, iclass 25, count 2 2006.231.08:09:50.35#ibcon#about to write, iclass 25, count 2 2006.231.08:09:50.35#ibcon#wrote, iclass 25, count 2 2006.231.08:09:50.35#ibcon#about to read 3, iclass 25, count 2 2006.231.08:09:50.38#ibcon#read 3, iclass 25, count 2 2006.231.08:09:50.38#ibcon#about to read 4, iclass 25, count 2 2006.231.08:09:50.38#ibcon#read 4, iclass 25, count 2 2006.231.08:09:50.38#ibcon#about to read 5, iclass 25, count 2 2006.231.08:09:50.38#ibcon#read 5, iclass 25, count 2 2006.231.08:09:50.38#ibcon#about to read 6, iclass 25, count 2 2006.231.08:09:50.38#ibcon#read 6, iclass 25, count 2 2006.231.08:09:50.38#ibcon#end of sib2, iclass 25, count 2 2006.231.08:09:50.38#ibcon#*after write, iclass 25, count 2 2006.231.08:09:50.38#ibcon#*before return 0, iclass 25, count 2 2006.231.08:09:50.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:09:50.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:09:50.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.231.08:09:50.38#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:50.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:09:50.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:09:50.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:09:50.50#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:09:50.50#ibcon#first serial, iclass 25, count 0 2006.231.08:09:50.50#ibcon#enter sib2, iclass 25, count 0 2006.231.08:09:50.50#ibcon#flushed, iclass 25, count 0 2006.231.08:09:50.50#ibcon#about to write, iclass 25, count 0 2006.231.08:09:50.50#ibcon#wrote, iclass 25, count 0 2006.231.08:09:50.50#ibcon#about to read 3, iclass 25, count 0 2006.231.08:09:50.52#ibcon#read 3, iclass 25, count 0 2006.231.08:09:50.52#ibcon#about to read 4, iclass 25, count 0 2006.231.08:09:50.52#ibcon#read 4, iclass 25, count 0 2006.231.08:09:50.52#ibcon#about to read 5, iclass 25, count 0 2006.231.08:09:50.52#ibcon#read 5, iclass 25, count 0 2006.231.08:09:50.52#ibcon#about to read 6, iclass 25, count 0 2006.231.08:09:50.52#ibcon#read 6, iclass 25, count 0 2006.231.08:09:50.52#ibcon#end of sib2, iclass 25, count 0 2006.231.08:09:50.52#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:09:50.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:09:50.52#ibcon#[25=USB\r\n] 2006.231.08:09:50.52#ibcon#*before write, iclass 25, count 0 2006.231.08:09:50.52#ibcon#enter sib2, iclass 25, count 0 2006.231.08:09:50.52#ibcon#flushed, iclass 25, count 0 2006.231.08:09:50.52#ibcon#about to write, iclass 25, count 0 2006.231.08:09:50.52#ibcon#wrote, iclass 25, count 0 2006.231.08:09:50.52#ibcon#about to read 3, iclass 25, count 0 2006.231.08:09:50.55#ibcon#read 3, iclass 25, count 0 2006.231.08:09:50.55#ibcon#about to read 4, iclass 25, count 0 2006.231.08:09:50.55#ibcon#read 4, iclass 25, count 0 2006.231.08:09:50.55#ibcon#about to read 5, iclass 25, count 0 2006.231.08:09:50.55#ibcon#read 5, iclass 25, count 0 2006.231.08:09:50.55#ibcon#about to read 6, iclass 25, count 0 2006.231.08:09:50.55#ibcon#read 6, iclass 25, count 0 2006.231.08:09:50.55#ibcon#end of sib2, iclass 25, count 0 2006.231.08:09:50.55#ibcon#*after write, iclass 25, count 0 2006.231.08:09:50.55#ibcon#*before return 0, iclass 25, count 0 2006.231.08:09:50.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:09:50.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:09:50.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:09:50.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:09:50.55$vc4f8/vblo=1,632.99 2006.231.08:09:50.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.231.08:09:50.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.231.08:09:50.55#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:50.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:09:50.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:09:50.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:09:50.55#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:09:50.55#ibcon#first serial, iclass 27, count 0 2006.231.08:09:50.55#ibcon#enter sib2, iclass 27, count 0 2006.231.08:09:50.55#ibcon#flushed, iclass 27, count 0 2006.231.08:09:50.55#ibcon#about to write, iclass 27, count 0 2006.231.08:09:50.55#ibcon#wrote, iclass 27, count 0 2006.231.08:09:50.55#ibcon#about to read 3, iclass 27, count 0 2006.231.08:09:50.57#ibcon#read 3, iclass 27, count 0 2006.231.08:09:50.57#ibcon#about to read 4, iclass 27, count 0 2006.231.08:09:50.57#ibcon#read 4, iclass 27, count 0 2006.231.08:09:50.57#ibcon#about to read 5, iclass 27, count 0 2006.231.08:09:50.57#ibcon#read 5, iclass 27, count 0 2006.231.08:09:50.57#ibcon#about to read 6, iclass 27, count 0 2006.231.08:09:50.57#ibcon#read 6, iclass 27, count 0 2006.231.08:09:50.57#ibcon#end of sib2, iclass 27, count 0 2006.231.08:09:50.57#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:09:50.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:09:50.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:09:50.57#ibcon#*before write, iclass 27, count 0 2006.231.08:09:50.57#ibcon#enter sib2, iclass 27, count 0 2006.231.08:09:50.57#ibcon#flushed, iclass 27, count 0 2006.231.08:09:50.57#ibcon#about to write, iclass 27, count 0 2006.231.08:09:50.57#ibcon#wrote, iclass 27, count 0 2006.231.08:09:50.57#ibcon#about to read 3, iclass 27, count 0 2006.231.08:09:50.61#ibcon#read 3, iclass 27, count 0 2006.231.08:09:50.61#ibcon#about to read 4, iclass 27, count 0 2006.231.08:09:50.61#ibcon#read 4, iclass 27, count 0 2006.231.08:09:50.61#ibcon#about to read 5, iclass 27, count 0 2006.231.08:09:50.61#ibcon#read 5, iclass 27, count 0 2006.231.08:09:50.61#ibcon#about to read 6, iclass 27, count 0 2006.231.08:09:50.61#ibcon#read 6, iclass 27, count 0 2006.231.08:09:50.61#ibcon#end of sib2, iclass 27, count 0 2006.231.08:09:50.61#ibcon#*after write, iclass 27, count 0 2006.231.08:09:50.61#ibcon#*before return 0, iclass 27, count 0 2006.231.08:09:50.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:09:50.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:09:50.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:09:50.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:09:50.61$vc4f8/vb=1,4 2006.231.08:09:50.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.231.08:09:50.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.231.08:09:50.61#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:50.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:09:50.61#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:09:50.61#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:09:50.61#ibcon#enter wrdev, iclass 29, count 2 2006.231.08:09:50.61#ibcon#first serial, iclass 29, count 2 2006.231.08:09:50.61#ibcon#enter sib2, iclass 29, count 2 2006.231.08:09:50.61#ibcon#flushed, iclass 29, count 2 2006.231.08:09:50.61#ibcon#about to write, iclass 29, count 2 2006.231.08:09:50.61#ibcon#wrote, iclass 29, count 2 2006.231.08:09:50.61#ibcon#about to read 3, iclass 29, count 2 2006.231.08:09:50.63#ibcon#read 3, iclass 29, count 2 2006.231.08:09:50.63#ibcon#about to read 4, iclass 29, count 2 2006.231.08:09:50.63#ibcon#read 4, iclass 29, count 2 2006.231.08:09:50.63#ibcon#about to read 5, iclass 29, count 2 2006.231.08:09:50.63#ibcon#read 5, iclass 29, count 2 2006.231.08:09:50.63#ibcon#about to read 6, iclass 29, count 2 2006.231.08:09:50.63#ibcon#read 6, iclass 29, count 2 2006.231.08:09:50.63#ibcon#end of sib2, iclass 29, count 2 2006.231.08:09:50.63#ibcon#*mode == 0, iclass 29, count 2 2006.231.08:09:50.63#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.231.08:09:50.63#ibcon#[27=AT01-04\r\n] 2006.231.08:09:50.63#ibcon#*before write, iclass 29, count 2 2006.231.08:09:50.63#ibcon#enter sib2, iclass 29, count 2 2006.231.08:09:50.63#ibcon#flushed, iclass 29, count 2 2006.231.08:09:50.63#ibcon#about to write, iclass 29, count 2 2006.231.08:09:50.63#ibcon#wrote, iclass 29, count 2 2006.231.08:09:50.63#ibcon#about to read 3, iclass 29, count 2 2006.231.08:09:50.66#ibcon#read 3, iclass 29, count 2 2006.231.08:09:50.66#ibcon#about to read 4, iclass 29, count 2 2006.231.08:09:50.66#ibcon#read 4, iclass 29, count 2 2006.231.08:09:50.66#ibcon#about to read 5, iclass 29, count 2 2006.231.08:09:50.66#ibcon#read 5, iclass 29, count 2 2006.231.08:09:50.66#ibcon#about to read 6, iclass 29, count 2 2006.231.08:09:50.66#ibcon#read 6, iclass 29, count 2 2006.231.08:09:50.66#ibcon#end of sib2, iclass 29, count 2 2006.231.08:09:50.66#ibcon#*after write, iclass 29, count 2 2006.231.08:09:50.66#ibcon#*before return 0, iclass 29, count 2 2006.231.08:09:50.66#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:09:50.66#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:09:50.66#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.231.08:09:50.66#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:50.66#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:09:50.78#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:09:50.78#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:09:50.78#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:09:50.78#ibcon#first serial, iclass 29, count 0 2006.231.08:09:50.78#ibcon#enter sib2, iclass 29, count 0 2006.231.08:09:50.78#ibcon#flushed, iclass 29, count 0 2006.231.08:09:50.78#ibcon#about to write, iclass 29, count 0 2006.231.08:09:50.78#ibcon#wrote, iclass 29, count 0 2006.231.08:09:50.78#ibcon#about to read 3, iclass 29, count 0 2006.231.08:09:50.80#ibcon#read 3, iclass 29, count 0 2006.231.08:09:50.80#ibcon#about to read 4, iclass 29, count 0 2006.231.08:09:50.80#ibcon#read 4, iclass 29, count 0 2006.231.08:09:50.80#ibcon#about to read 5, iclass 29, count 0 2006.231.08:09:50.80#ibcon#read 5, iclass 29, count 0 2006.231.08:09:50.80#ibcon#about to read 6, iclass 29, count 0 2006.231.08:09:50.80#ibcon#read 6, iclass 29, count 0 2006.231.08:09:50.80#ibcon#end of sib2, iclass 29, count 0 2006.231.08:09:50.80#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:09:50.80#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:09:50.80#ibcon#[27=USB\r\n] 2006.231.08:09:50.80#ibcon#*before write, iclass 29, count 0 2006.231.08:09:50.80#ibcon#enter sib2, iclass 29, count 0 2006.231.08:09:50.80#ibcon#flushed, iclass 29, count 0 2006.231.08:09:50.80#ibcon#about to write, iclass 29, count 0 2006.231.08:09:50.80#ibcon#wrote, iclass 29, count 0 2006.231.08:09:50.80#ibcon#about to read 3, iclass 29, count 0 2006.231.08:09:50.83#ibcon#read 3, iclass 29, count 0 2006.231.08:09:50.83#ibcon#about to read 4, iclass 29, count 0 2006.231.08:09:50.83#ibcon#read 4, iclass 29, count 0 2006.231.08:09:50.83#ibcon#about to read 5, iclass 29, count 0 2006.231.08:09:50.83#ibcon#read 5, iclass 29, count 0 2006.231.08:09:50.83#ibcon#about to read 6, iclass 29, count 0 2006.231.08:09:50.83#ibcon#read 6, iclass 29, count 0 2006.231.08:09:50.83#ibcon#end of sib2, iclass 29, count 0 2006.231.08:09:50.83#ibcon#*after write, iclass 29, count 0 2006.231.08:09:50.83#ibcon#*before return 0, iclass 29, count 0 2006.231.08:09:50.83#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:09:50.83#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:09:50.83#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:09:50.83#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:09:50.83$vc4f8/vblo=2,640.99 2006.231.08:09:50.83#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.231.08:09:50.83#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.231.08:09:50.83#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:50.83#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:09:50.83#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:09:50.83#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:09:50.83#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:09:50.83#ibcon#first serial, iclass 31, count 0 2006.231.08:09:50.83#ibcon#enter sib2, iclass 31, count 0 2006.231.08:09:50.83#ibcon#flushed, iclass 31, count 0 2006.231.08:09:50.83#ibcon#about to write, iclass 31, count 0 2006.231.08:09:50.83#ibcon#wrote, iclass 31, count 0 2006.231.08:09:50.83#ibcon#about to read 3, iclass 31, count 0 2006.231.08:09:50.85#ibcon#read 3, iclass 31, count 0 2006.231.08:09:50.85#ibcon#about to read 4, iclass 31, count 0 2006.231.08:09:50.85#ibcon#read 4, iclass 31, count 0 2006.231.08:09:50.85#ibcon#about to read 5, iclass 31, count 0 2006.231.08:09:50.85#ibcon#read 5, iclass 31, count 0 2006.231.08:09:50.85#ibcon#about to read 6, iclass 31, count 0 2006.231.08:09:50.85#ibcon#read 6, iclass 31, count 0 2006.231.08:09:50.85#ibcon#end of sib2, iclass 31, count 0 2006.231.08:09:50.85#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:09:50.85#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:09:50.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:09:50.85#ibcon#*before write, iclass 31, count 0 2006.231.08:09:50.85#ibcon#enter sib2, iclass 31, count 0 2006.231.08:09:50.85#ibcon#flushed, iclass 31, count 0 2006.231.08:09:50.85#ibcon#about to write, iclass 31, count 0 2006.231.08:09:50.85#ibcon#wrote, iclass 31, count 0 2006.231.08:09:50.85#ibcon#about to read 3, iclass 31, count 0 2006.231.08:09:50.89#ibcon#read 3, iclass 31, count 0 2006.231.08:09:50.89#ibcon#about to read 4, iclass 31, count 0 2006.231.08:09:50.89#ibcon#read 4, iclass 31, count 0 2006.231.08:09:50.89#ibcon#about to read 5, iclass 31, count 0 2006.231.08:09:50.89#ibcon#read 5, iclass 31, count 0 2006.231.08:09:50.89#ibcon#about to read 6, iclass 31, count 0 2006.231.08:09:50.89#ibcon#read 6, iclass 31, count 0 2006.231.08:09:50.89#ibcon#end of sib2, iclass 31, count 0 2006.231.08:09:50.89#ibcon#*after write, iclass 31, count 0 2006.231.08:09:50.89#ibcon#*before return 0, iclass 31, count 0 2006.231.08:09:50.89#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:09:50.89#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:09:50.89#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:09:50.89#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:09:50.89$vc4f8/vb=2,4 2006.231.08:09:50.89#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.231.08:09:50.89#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.231.08:09:50.89#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:50.89#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:09:50.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:09:50.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:09:50.95#ibcon#enter wrdev, iclass 33, count 2 2006.231.08:09:50.95#ibcon#first serial, iclass 33, count 2 2006.231.08:09:50.95#ibcon#enter sib2, iclass 33, count 2 2006.231.08:09:50.95#ibcon#flushed, iclass 33, count 2 2006.231.08:09:50.95#ibcon#about to write, iclass 33, count 2 2006.231.08:09:50.95#ibcon#wrote, iclass 33, count 2 2006.231.08:09:50.95#ibcon#about to read 3, iclass 33, count 2 2006.231.08:09:50.97#ibcon#read 3, iclass 33, count 2 2006.231.08:09:50.97#ibcon#about to read 4, iclass 33, count 2 2006.231.08:09:50.97#ibcon#read 4, iclass 33, count 2 2006.231.08:09:50.97#ibcon#about to read 5, iclass 33, count 2 2006.231.08:09:50.97#ibcon#read 5, iclass 33, count 2 2006.231.08:09:50.97#ibcon#about to read 6, iclass 33, count 2 2006.231.08:09:50.97#ibcon#read 6, iclass 33, count 2 2006.231.08:09:50.97#ibcon#end of sib2, iclass 33, count 2 2006.231.08:09:50.97#ibcon#*mode == 0, iclass 33, count 2 2006.231.08:09:50.97#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.231.08:09:50.97#ibcon#[27=AT02-04\r\n] 2006.231.08:09:50.97#ibcon#*before write, iclass 33, count 2 2006.231.08:09:50.97#ibcon#enter sib2, iclass 33, count 2 2006.231.08:09:50.97#ibcon#flushed, iclass 33, count 2 2006.231.08:09:50.97#ibcon#about to write, iclass 33, count 2 2006.231.08:09:50.97#ibcon#wrote, iclass 33, count 2 2006.231.08:09:50.97#ibcon#about to read 3, iclass 33, count 2 2006.231.08:09:51.01#ibcon#read 3, iclass 33, count 2 2006.231.08:09:51.01#ibcon#about to read 4, iclass 33, count 2 2006.231.08:09:51.01#ibcon#read 4, iclass 33, count 2 2006.231.08:09:51.01#ibcon#about to read 5, iclass 33, count 2 2006.231.08:09:51.01#ibcon#read 5, iclass 33, count 2 2006.231.08:09:51.01#ibcon#about to read 6, iclass 33, count 2 2006.231.08:09:51.01#ibcon#read 6, iclass 33, count 2 2006.231.08:09:51.01#ibcon#end of sib2, iclass 33, count 2 2006.231.08:09:51.01#ibcon#*after write, iclass 33, count 2 2006.231.08:09:51.01#ibcon#*before return 0, iclass 33, count 2 2006.231.08:09:51.01#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:09:51.01#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:09:51.01#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.231.08:09:51.01#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:51.01#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:09:51.12#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:09:51.12#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:09:51.12#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:09:51.12#ibcon#first serial, iclass 33, count 0 2006.231.08:09:51.12#ibcon#enter sib2, iclass 33, count 0 2006.231.08:09:51.12#ibcon#flushed, iclass 33, count 0 2006.231.08:09:51.12#ibcon#about to write, iclass 33, count 0 2006.231.08:09:51.12#ibcon#wrote, iclass 33, count 0 2006.231.08:09:51.12#ibcon#about to read 3, iclass 33, count 0 2006.231.08:09:51.14#ibcon#read 3, iclass 33, count 0 2006.231.08:09:51.14#ibcon#about to read 4, iclass 33, count 0 2006.231.08:09:51.14#ibcon#read 4, iclass 33, count 0 2006.231.08:09:51.14#ibcon#about to read 5, iclass 33, count 0 2006.231.08:09:51.14#ibcon#read 5, iclass 33, count 0 2006.231.08:09:51.14#ibcon#about to read 6, iclass 33, count 0 2006.231.08:09:51.14#ibcon#read 6, iclass 33, count 0 2006.231.08:09:51.14#ibcon#end of sib2, iclass 33, count 0 2006.231.08:09:51.14#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:09:51.14#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:09:51.14#ibcon#[27=USB\r\n] 2006.231.08:09:51.14#ibcon#*before write, iclass 33, count 0 2006.231.08:09:51.14#ibcon#enter sib2, iclass 33, count 0 2006.231.08:09:51.14#ibcon#flushed, iclass 33, count 0 2006.231.08:09:51.14#ibcon#about to write, iclass 33, count 0 2006.231.08:09:51.14#ibcon#wrote, iclass 33, count 0 2006.231.08:09:51.14#ibcon#about to read 3, iclass 33, count 0 2006.231.08:09:51.17#ibcon#read 3, iclass 33, count 0 2006.231.08:09:51.17#ibcon#about to read 4, iclass 33, count 0 2006.231.08:09:51.17#ibcon#read 4, iclass 33, count 0 2006.231.08:09:51.17#ibcon#about to read 5, iclass 33, count 0 2006.231.08:09:51.17#ibcon#read 5, iclass 33, count 0 2006.231.08:09:51.17#ibcon#about to read 6, iclass 33, count 0 2006.231.08:09:51.17#ibcon#read 6, iclass 33, count 0 2006.231.08:09:51.17#ibcon#end of sib2, iclass 33, count 0 2006.231.08:09:51.17#ibcon#*after write, iclass 33, count 0 2006.231.08:09:51.17#ibcon#*before return 0, iclass 33, count 0 2006.231.08:09:51.17#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:09:51.17#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:09:51.17#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:09:51.17#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:09:51.17$vc4f8/vblo=3,656.99 2006.231.08:09:51.17#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.231.08:09:51.17#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.231.08:09:51.17#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:51.17#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:09:51.17#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:09:51.17#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:09:51.17#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:09:51.17#ibcon#first serial, iclass 35, count 0 2006.231.08:09:51.17#ibcon#enter sib2, iclass 35, count 0 2006.231.08:09:51.17#ibcon#flushed, iclass 35, count 0 2006.231.08:09:51.17#ibcon#about to write, iclass 35, count 0 2006.231.08:09:51.17#ibcon#wrote, iclass 35, count 0 2006.231.08:09:51.17#ibcon#about to read 3, iclass 35, count 0 2006.231.08:09:51.19#ibcon#read 3, iclass 35, count 0 2006.231.08:09:51.19#ibcon#about to read 4, iclass 35, count 0 2006.231.08:09:51.19#ibcon#read 4, iclass 35, count 0 2006.231.08:09:51.19#ibcon#about to read 5, iclass 35, count 0 2006.231.08:09:51.19#ibcon#read 5, iclass 35, count 0 2006.231.08:09:51.19#ibcon#about to read 6, iclass 35, count 0 2006.231.08:09:51.19#ibcon#read 6, iclass 35, count 0 2006.231.08:09:51.19#ibcon#end of sib2, iclass 35, count 0 2006.231.08:09:51.19#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:09:51.19#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:09:51.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:09:51.19#ibcon#*before write, iclass 35, count 0 2006.231.08:09:51.19#ibcon#enter sib2, iclass 35, count 0 2006.231.08:09:51.19#ibcon#flushed, iclass 35, count 0 2006.231.08:09:51.19#ibcon#about to write, iclass 35, count 0 2006.231.08:09:51.19#ibcon#wrote, iclass 35, count 0 2006.231.08:09:51.19#ibcon#about to read 3, iclass 35, count 0 2006.231.08:09:51.23#ibcon#read 3, iclass 35, count 0 2006.231.08:09:51.23#ibcon#about to read 4, iclass 35, count 0 2006.231.08:09:51.23#ibcon#read 4, iclass 35, count 0 2006.231.08:09:51.23#ibcon#about to read 5, iclass 35, count 0 2006.231.08:09:51.23#ibcon#read 5, iclass 35, count 0 2006.231.08:09:51.23#ibcon#about to read 6, iclass 35, count 0 2006.231.08:09:51.23#ibcon#read 6, iclass 35, count 0 2006.231.08:09:51.23#ibcon#end of sib2, iclass 35, count 0 2006.231.08:09:51.23#ibcon#*after write, iclass 35, count 0 2006.231.08:09:51.23#ibcon#*before return 0, iclass 35, count 0 2006.231.08:09:51.23#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:09:51.23#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:09:51.23#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:09:51.23#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:09:51.23$vc4f8/vb=3,4 2006.231.08:09:51.23#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.231.08:09:51.23#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.231.08:09:51.23#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:51.23#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:09:51.29#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:09:51.29#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:09:51.29#ibcon#enter wrdev, iclass 37, count 2 2006.231.08:09:51.29#ibcon#first serial, iclass 37, count 2 2006.231.08:09:51.29#ibcon#enter sib2, iclass 37, count 2 2006.231.08:09:51.29#ibcon#flushed, iclass 37, count 2 2006.231.08:09:51.29#ibcon#about to write, iclass 37, count 2 2006.231.08:09:51.29#ibcon#wrote, iclass 37, count 2 2006.231.08:09:51.29#ibcon#about to read 3, iclass 37, count 2 2006.231.08:09:51.31#ibcon#read 3, iclass 37, count 2 2006.231.08:09:51.31#ibcon#about to read 4, iclass 37, count 2 2006.231.08:09:51.31#ibcon#read 4, iclass 37, count 2 2006.231.08:09:51.31#ibcon#about to read 5, iclass 37, count 2 2006.231.08:09:51.31#ibcon#read 5, iclass 37, count 2 2006.231.08:09:51.31#ibcon#about to read 6, iclass 37, count 2 2006.231.08:09:51.31#ibcon#read 6, iclass 37, count 2 2006.231.08:09:51.31#ibcon#end of sib2, iclass 37, count 2 2006.231.08:09:51.31#ibcon#*mode == 0, iclass 37, count 2 2006.231.08:09:51.31#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.231.08:09:51.31#ibcon#[27=AT03-04\r\n] 2006.231.08:09:51.31#ibcon#*before write, iclass 37, count 2 2006.231.08:09:51.31#ibcon#enter sib2, iclass 37, count 2 2006.231.08:09:51.31#ibcon#flushed, iclass 37, count 2 2006.231.08:09:51.31#ibcon#about to write, iclass 37, count 2 2006.231.08:09:51.31#ibcon#wrote, iclass 37, count 2 2006.231.08:09:51.31#ibcon#about to read 3, iclass 37, count 2 2006.231.08:09:51.34#ibcon#read 3, iclass 37, count 2 2006.231.08:09:51.34#ibcon#about to read 4, iclass 37, count 2 2006.231.08:09:51.34#ibcon#read 4, iclass 37, count 2 2006.231.08:09:51.34#ibcon#about to read 5, iclass 37, count 2 2006.231.08:09:51.34#ibcon#read 5, iclass 37, count 2 2006.231.08:09:51.34#ibcon#about to read 6, iclass 37, count 2 2006.231.08:09:51.34#ibcon#read 6, iclass 37, count 2 2006.231.08:09:51.34#ibcon#end of sib2, iclass 37, count 2 2006.231.08:09:51.34#ibcon#*after write, iclass 37, count 2 2006.231.08:09:51.34#ibcon#*before return 0, iclass 37, count 2 2006.231.08:09:51.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:09:51.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:09:51.34#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.231.08:09:51.34#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:51.34#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:09:51.46#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:09:51.46#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:09:51.46#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:09:51.46#ibcon#first serial, iclass 37, count 0 2006.231.08:09:51.46#ibcon#enter sib2, iclass 37, count 0 2006.231.08:09:51.46#ibcon#flushed, iclass 37, count 0 2006.231.08:09:51.46#ibcon#about to write, iclass 37, count 0 2006.231.08:09:51.46#ibcon#wrote, iclass 37, count 0 2006.231.08:09:51.46#ibcon#about to read 3, iclass 37, count 0 2006.231.08:09:51.48#ibcon#read 3, iclass 37, count 0 2006.231.08:09:51.48#ibcon#about to read 4, iclass 37, count 0 2006.231.08:09:51.48#ibcon#read 4, iclass 37, count 0 2006.231.08:09:51.48#ibcon#about to read 5, iclass 37, count 0 2006.231.08:09:51.48#ibcon#read 5, iclass 37, count 0 2006.231.08:09:51.48#ibcon#about to read 6, iclass 37, count 0 2006.231.08:09:51.48#ibcon#read 6, iclass 37, count 0 2006.231.08:09:51.48#ibcon#end of sib2, iclass 37, count 0 2006.231.08:09:51.48#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:09:51.48#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:09:51.48#ibcon#[27=USB\r\n] 2006.231.08:09:51.48#ibcon#*before write, iclass 37, count 0 2006.231.08:09:51.48#ibcon#enter sib2, iclass 37, count 0 2006.231.08:09:51.48#ibcon#flushed, iclass 37, count 0 2006.231.08:09:51.48#ibcon#about to write, iclass 37, count 0 2006.231.08:09:51.48#ibcon#wrote, iclass 37, count 0 2006.231.08:09:51.48#ibcon#about to read 3, iclass 37, count 0 2006.231.08:09:51.51#ibcon#read 3, iclass 37, count 0 2006.231.08:09:51.51#ibcon#about to read 4, iclass 37, count 0 2006.231.08:09:51.51#ibcon#read 4, iclass 37, count 0 2006.231.08:09:51.51#ibcon#about to read 5, iclass 37, count 0 2006.231.08:09:51.51#ibcon#read 5, iclass 37, count 0 2006.231.08:09:51.51#ibcon#about to read 6, iclass 37, count 0 2006.231.08:09:51.51#ibcon#read 6, iclass 37, count 0 2006.231.08:09:51.51#ibcon#end of sib2, iclass 37, count 0 2006.231.08:09:51.51#ibcon#*after write, iclass 37, count 0 2006.231.08:09:51.51#ibcon#*before return 0, iclass 37, count 0 2006.231.08:09:51.51#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:09:51.51#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:09:51.51#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:09:51.51#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:09:51.51$vc4f8/vblo=4,712.99 2006.231.08:09:51.51#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.08:09:51.51#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.08:09:51.51#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:51.51#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:09:51.51#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:09:51.51#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:09:51.51#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:09:51.51#ibcon#first serial, iclass 39, count 0 2006.231.08:09:51.51#ibcon#enter sib2, iclass 39, count 0 2006.231.08:09:51.51#ibcon#flushed, iclass 39, count 0 2006.231.08:09:51.51#ibcon#about to write, iclass 39, count 0 2006.231.08:09:51.51#ibcon#wrote, iclass 39, count 0 2006.231.08:09:51.51#ibcon#about to read 3, iclass 39, count 0 2006.231.08:09:51.53#ibcon#read 3, iclass 39, count 0 2006.231.08:09:51.53#ibcon#about to read 4, iclass 39, count 0 2006.231.08:09:51.53#ibcon#read 4, iclass 39, count 0 2006.231.08:09:51.53#ibcon#about to read 5, iclass 39, count 0 2006.231.08:09:51.53#ibcon#read 5, iclass 39, count 0 2006.231.08:09:51.53#ibcon#about to read 6, iclass 39, count 0 2006.231.08:09:51.53#ibcon#read 6, iclass 39, count 0 2006.231.08:09:51.53#ibcon#end of sib2, iclass 39, count 0 2006.231.08:09:51.53#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:09:51.53#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:09:51.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:09:51.53#ibcon#*before write, iclass 39, count 0 2006.231.08:09:51.53#ibcon#enter sib2, iclass 39, count 0 2006.231.08:09:51.53#ibcon#flushed, iclass 39, count 0 2006.231.08:09:51.53#ibcon#about to write, iclass 39, count 0 2006.231.08:09:51.53#ibcon#wrote, iclass 39, count 0 2006.231.08:09:51.53#ibcon#about to read 3, iclass 39, count 0 2006.231.08:09:51.57#ibcon#read 3, iclass 39, count 0 2006.231.08:09:51.57#ibcon#about to read 4, iclass 39, count 0 2006.231.08:09:51.57#ibcon#read 4, iclass 39, count 0 2006.231.08:09:51.57#ibcon#about to read 5, iclass 39, count 0 2006.231.08:09:51.57#ibcon#read 5, iclass 39, count 0 2006.231.08:09:51.57#ibcon#about to read 6, iclass 39, count 0 2006.231.08:09:51.57#ibcon#read 6, iclass 39, count 0 2006.231.08:09:51.57#ibcon#end of sib2, iclass 39, count 0 2006.231.08:09:51.57#ibcon#*after write, iclass 39, count 0 2006.231.08:09:51.57#ibcon#*before return 0, iclass 39, count 0 2006.231.08:09:51.57#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:09:51.57#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:09:51.57#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:09:51.57#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:09:51.57$vc4f8/vb=4,4 2006.231.08:09:51.57#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.231.08:09:51.57#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.231.08:09:51.57#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:51.57#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:09:51.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:09:51.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:09:51.63#ibcon#enter wrdev, iclass 3, count 2 2006.231.08:09:51.63#ibcon#first serial, iclass 3, count 2 2006.231.08:09:51.63#ibcon#enter sib2, iclass 3, count 2 2006.231.08:09:51.63#ibcon#flushed, iclass 3, count 2 2006.231.08:09:51.63#ibcon#about to write, iclass 3, count 2 2006.231.08:09:51.63#ibcon#wrote, iclass 3, count 2 2006.231.08:09:51.63#ibcon#about to read 3, iclass 3, count 2 2006.231.08:09:51.65#ibcon#read 3, iclass 3, count 2 2006.231.08:09:51.65#ibcon#about to read 4, iclass 3, count 2 2006.231.08:09:51.65#ibcon#read 4, iclass 3, count 2 2006.231.08:09:51.65#ibcon#about to read 5, iclass 3, count 2 2006.231.08:09:51.65#ibcon#read 5, iclass 3, count 2 2006.231.08:09:51.65#ibcon#about to read 6, iclass 3, count 2 2006.231.08:09:51.65#ibcon#read 6, iclass 3, count 2 2006.231.08:09:51.65#ibcon#end of sib2, iclass 3, count 2 2006.231.08:09:51.65#ibcon#*mode == 0, iclass 3, count 2 2006.231.08:09:51.65#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.231.08:09:51.65#ibcon#[27=AT04-04\r\n] 2006.231.08:09:51.65#ibcon#*before write, iclass 3, count 2 2006.231.08:09:51.65#ibcon#enter sib2, iclass 3, count 2 2006.231.08:09:51.65#ibcon#flushed, iclass 3, count 2 2006.231.08:09:51.65#ibcon#about to write, iclass 3, count 2 2006.231.08:09:51.65#ibcon#wrote, iclass 3, count 2 2006.231.08:09:51.65#ibcon#about to read 3, iclass 3, count 2 2006.231.08:09:51.68#ibcon#read 3, iclass 3, count 2 2006.231.08:09:51.68#ibcon#about to read 4, iclass 3, count 2 2006.231.08:09:51.68#ibcon#read 4, iclass 3, count 2 2006.231.08:09:51.68#ibcon#about to read 5, iclass 3, count 2 2006.231.08:09:51.68#ibcon#read 5, iclass 3, count 2 2006.231.08:09:51.68#ibcon#about to read 6, iclass 3, count 2 2006.231.08:09:51.68#ibcon#read 6, iclass 3, count 2 2006.231.08:09:51.68#ibcon#end of sib2, iclass 3, count 2 2006.231.08:09:51.68#ibcon#*after write, iclass 3, count 2 2006.231.08:09:51.68#ibcon#*before return 0, iclass 3, count 2 2006.231.08:09:51.68#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:09:51.68#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:09:51.68#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.231.08:09:51.68#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:51.68#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:09:51.80#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:09:51.80#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:09:51.80#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:09:51.80#ibcon#first serial, iclass 3, count 0 2006.231.08:09:51.80#ibcon#enter sib2, iclass 3, count 0 2006.231.08:09:51.80#ibcon#flushed, iclass 3, count 0 2006.231.08:09:51.80#ibcon#about to write, iclass 3, count 0 2006.231.08:09:51.80#ibcon#wrote, iclass 3, count 0 2006.231.08:09:51.80#ibcon#about to read 3, iclass 3, count 0 2006.231.08:09:51.82#ibcon#read 3, iclass 3, count 0 2006.231.08:09:51.82#ibcon#about to read 4, iclass 3, count 0 2006.231.08:09:51.82#ibcon#read 4, iclass 3, count 0 2006.231.08:09:51.82#ibcon#about to read 5, iclass 3, count 0 2006.231.08:09:51.82#ibcon#read 5, iclass 3, count 0 2006.231.08:09:51.82#ibcon#about to read 6, iclass 3, count 0 2006.231.08:09:51.82#ibcon#read 6, iclass 3, count 0 2006.231.08:09:51.82#ibcon#end of sib2, iclass 3, count 0 2006.231.08:09:51.82#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:09:51.82#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:09:51.82#ibcon#[27=USB\r\n] 2006.231.08:09:51.82#ibcon#*before write, iclass 3, count 0 2006.231.08:09:51.82#ibcon#enter sib2, iclass 3, count 0 2006.231.08:09:51.82#ibcon#flushed, iclass 3, count 0 2006.231.08:09:51.82#ibcon#about to write, iclass 3, count 0 2006.231.08:09:51.82#ibcon#wrote, iclass 3, count 0 2006.231.08:09:51.82#ibcon#about to read 3, iclass 3, count 0 2006.231.08:09:51.85#ibcon#read 3, iclass 3, count 0 2006.231.08:09:51.85#ibcon#about to read 4, iclass 3, count 0 2006.231.08:09:51.85#ibcon#read 4, iclass 3, count 0 2006.231.08:09:51.85#ibcon#about to read 5, iclass 3, count 0 2006.231.08:09:51.85#ibcon#read 5, iclass 3, count 0 2006.231.08:09:51.85#ibcon#about to read 6, iclass 3, count 0 2006.231.08:09:51.85#ibcon#read 6, iclass 3, count 0 2006.231.08:09:51.85#ibcon#end of sib2, iclass 3, count 0 2006.231.08:09:51.85#ibcon#*after write, iclass 3, count 0 2006.231.08:09:51.85#ibcon#*before return 0, iclass 3, count 0 2006.231.08:09:51.85#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:09:51.85#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:09:51.85#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:09:51.85#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:09:51.85$vc4f8/vblo=5,744.99 2006.231.08:09:51.85#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.231.08:09:51.85#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.231.08:09:51.85#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:51.85#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:09:51.85#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:09:51.85#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:09:51.85#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:09:51.85#ibcon#first serial, iclass 5, count 0 2006.231.08:09:51.85#ibcon#enter sib2, iclass 5, count 0 2006.231.08:09:51.85#ibcon#flushed, iclass 5, count 0 2006.231.08:09:51.85#ibcon#about to write, iclass 5, count 0 2006.231.08:09:51.85#ibcon#wrote, iclass 5, count 0 2006.231.08:09:51.85#ibcon#about to read 3, iclass 5, count 0 2006.231.08:09:51.87#ibcon#read 3, iclass 5, count 0 2006.231.08:09:51.87#ibcon#about to read 4, iclass 5, count 0 2006.231.08:09:51.87#ibcon#read 4, iclass 5, count 0 2006.231.08:09:51.87#ibcon#about to read 5, iclass 5, count 0 2006.231.08:09:51.87#ibcon#read 5, iclass 5, count 0 2006.231.08:09:51.87#ibcon#about to read 6, iclass 5, count 0 2006.231.08:09:51.87#ibcon#read 6, iclass 5, count 0 2006.231.08:09:51.87#ibcon#end of sib2, iclass 5, count 0 2006.231.08:09:51.87#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:09:51.87#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:09:51.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:09:51.87#ibcon#*before write, iclass 5, count 0 2006.231.08:09:51.87#ibcon#enter sib2, iclass 5, count 0 2006.231.08:09:51.87#ibcon#flushed, iclass 5, count 0 2006.231.08:09:51.87#ibcon#about to write, iclass 5, count 0 2006.231.08:09:51.87#ibcon#wrote, iclass 5, count 0 2006.231.08:09:51.87#ibcon#about to read 3, iclass 5, count 0 2006.231.08:09:51.90#abcon#<5=/06 3.1 6.8 30.48 861004.5\r\n> 2006.231.08:09:51.92#ibcon#read 3, iclass 5, count 0 2006.231.08:09:51.92#ibcon#about to read 4, iclass 5, count 0 2006.231.08:09:51.92#ibcon#read 4, iclass 5, count 0 2006.231.08:09:51.92#ibcon#about to read 5, iclass 5, count 0 2006.231.08:09:51.92#ibcon#read 5, iclass 5, count 0 2006.231.08:09:51.92#ibcon#about to read 6, iclass 5, count 0 2006.231.08:09:51.92#ibcon#read 6, iclass 5, count 0 2006.231.08:09:51.92#ibcon#end of sib2, iclass 5, count 0 2006.231.08:09:51.92#ibcon#*after write, iclass 5, count 0 2006.231.08:09:51.92#ibcon#*before return 0, iclass 5, count 0 2006.231.08:09:51.92#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:09:51.92#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:09:51.92#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:09:51.92#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:09:51.92$vc4f8/vb=5,3 2006.231.08:09:51.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.08:09:51.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.08:09:51.92#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:51.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:09:51.92#abcon#{5=INTERFACE CLEAR} 2006.231.08:09:51.96#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:09:51.96#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:09:51.96#ibcon#enter wrdev, iclass 12, count 2 2006.231.08:09:51.96#ibcon#first serial, iclass 12, count 2 2006.231.08:09:51.96#ibcon#enter sib2, iclass 12, count 2 2006.231.08:09:51.96#ibcon#flushed, iclass 12, count 2 2006.231.08:09:51.96#ibcon#about to write, iclass 12, count 2 2006.231.08:09:51.96#ibcon#wrote, iclass 12, count 2 2006.231.08:09:51.96#ibcon#about to read 3, iclass 12, count 2 2006.231.08:09:51.98#ibcon#read 3, iclass 12, count 2 2006.231.08:09:51.98#ibcon#about to read 4, iclass 12, count 2 2006.231.08:09:51.98#ibcon#read 4, iclass 12, count 2 2006.231.08:09:51.98#ibcon#about to read 5, iclass 12, count 2 2006.231.08:09:51.98#ibcon#read 5, iclass 12, count 2 2006.231.08:09:51.98#ibcon#about to read 6, iclass 12, count 2 2006.231.08:09:51.98#ibcon#read 6, iclass 12, count 2 2006.231.08:09:51.98#ibcon#end of sib2, iclass 12, count 2 2006.231.08:09:51.98#ibcon#*mode == 0, iclass 12, count 2 2006.231.08:09:51.98#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.08:09:51.98#ibcon#[27=AT05-03\r\n] 2006.231.08:09:51.98#ibcon#*before write, iclass 12, count 2 2006.231.08:09:51.98#ibcon#enter sib2, iclass 12, count 2 2006.231.08:09:51.98#ibcon#flushed, iclass 12, count 2 2006.231.08:09:51.98#ibcon#about to write, iclass 12, count 2 2006.231.08:09:51.98#ibcon#wrote, iclass 12, count 2 2006.231.08:09:51.98#ibcon#about to read 3, iclass 12, count 2 2006.231.08:09:51.98#abcon#[5=S1D000X0/0*\r\n] 2006.231.08:09:52.01#ibcon#read 3, iclass 12, count 2 2006.231.08:09:52.01#ibcon#about to read 4, iclass 12, count 2 2006.231.08:09:52.01#ibcon#read 4, iclass 12, count 2 2006.231.08:09:52.01#ibcon#about to read 5, iclass 12, count 2 2006.231.08:09:52.01#ibcon#read 5, iclass 12, count 2 2006.231.08:09:52.01#ibcon#about to read 6, iclass 12, count 2 2006.231.08:09:52.01#ibcon#read 6, iclass 12, count 2 2006.231.08:09:52.01#ibcon#end of sib2, iclass 12, count 2 2006.231.08:09:52.01#ibcon#*after write, iclass 12, count 2 2006.231.08:09:52.01#ibcon#*before return 0, iclass 12, count 2 2006.231.08:09:52.01#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:09:52.01#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:09:52.01#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.08:09:52.01#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:52.01#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:09:52.13#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:09:52.13#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:09:52.13#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:09:52.13#ibcon#first serial, iclass 12, count 0 2006.231.08:09:52.13#ibcon#enter sib2, iclass 12, count 0 2006.231.08:09:52.13#ibcon#flushed, iclass 12, count 0 2006.231.08:09:52.13#ibcon#about to write, iclass 12, count 0 2006.231.08:09:52.13#ibcon#wrote, iclass 12, count 0 2006.231.08:09:52.13#ibcon#about to read 3, iclass 12, count 0 2006.231.08:09:52.15#ibcon#read 3, iclass 12, count 0 2006.231.08:09:52.15#ibcon#about to read 4, iclass 12, count 0 2006.231.08:09:52.15#ibcon#read 4, iclass 12, count 0 2006.231.08:09:52.15#ibcon#about to read 5, iclass 12, count 0 2006.231.08:09:52.15#ibcon#read 5, iclass 12, count 0 2006.231.08:09:52.15#ibcon#about to read 6, iclass 12, count 0 2006.231.08:09:52.15#ibcon#read 6, iclass 12, count 0 2006.231.08:09:52.15#ibcon#end of sib2, iclass 12, count 0 2006.231.08:09:52.15#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:09:52.15#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:09:52.15#ibcon#[27=USB\r\n] 2006.231.08:09:52.15#ibcon#*before write, iclass 12, count 0 2006.231.08:09:52.15#ibcon#enter sib2, iclass 12, count 0 2006.231.08:09:52.15#ibcon#flushed, iclass 12, count 0 2006.231.08:09:52.15#ibcon#about to write, iclass 12, count 0 2006.231.08:09:52.15#ibcon#wrote, iclass 12, count 0 2006.231.08:09:52.15#ibcon#about to read 3, iclass 12, count 0 2006.231.08:09:52.18#ibcon#read 3, iclass 12, count 0 2006.231.08:09:52.18#ibcon#about to read 4, iclass 12, count 0 2006.231.08:09:52.18#ibcon#read 4, iclass 12, count 0 2006.231.08:09:52.18#ibcon#about to read 5, iclass 12, count 0 2006.231.08:09:52.18#ibcon#read 5, iclass 12, count 0 2006.231.08:09:52.18#ibcon#about to read 6, iclass 12, count 0 2006.231.08:09:52.18#ibcon#read 6, iclass 12, count 0 2006.231.08:09:52.18#ibcon#end of sib2, iclass 12, count 0 2006.231.08:09:52.18#ibcon#*after write, iclass 12, count 0 2006.231.08:09:52.18#ibcon#*before return 0, iclass 12, count 0 2006.231.08:09:52.18#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:09:52.18#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:09:52.18#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:09:52.18#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:09:52.18$vc4f8/vblo=6,752.99 2006.231.08:09:52.18#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.08:09:52.18#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.08:09:52.18#ibcon#ireg 17 cls_cnt 0 2006.231.08:09:52.18#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:09:52.18#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:09:52.18#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:09:52.18#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:09:52.18#ibcon#first serial, iclass 15, count 0 2006.231.08:09:52.18#ibcon#enter sib2, iclass 15, count 0 2006.231.08:09:52.18#ibcon#flushed, iclass 15, count 0 2006.231.08:09:52.18#ibcon#about to write, iclass 15, count 0 2006.231.08:09:52.18#ibcon#wrote, iclass 15, count 0 2006.231.08:09:52.18#ibcon#about to read 3, iclass 15, count 0 2006.231.08:09:52.20#ibcon#read 3, iclass 15, count 0 2006.231.08:09:52.20#ibcon#about to read 4, iclass 15, count 0 2006.231.08:09:52.20#ibcon#read 4, iclass 15, count 0 2006.231.08:09:52.20#ibcon#about to read 5, iclass 15, count 0 2006.231.08:09:52.20#ibcon#read 5, iclass 15, count 0 2006.231.08:09:52.20#ibcon#about to read 6, iclass 15, count 0 2006.231.08:09:52.20#ibcon#read 6, iclass 15, count 0 2006.231.08:09:52.20#ibcon#end of sib2, iclass 15, count 0 2006.231.08:09:52.20#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:09:52.20#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:09:52.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:09:52.20#ibcon#*before write, iclass 15, count 0 2006.231.08:09:52.20#ibcon#enter sib2, iclass 15, count 0 2006.231.08:09:52.20#ibcon#flushed, iclass 15, count 0 2006.231.08:09:52.20#ibcon#about to write, iclass 15, count 0 2006.231.08:09:52.20#ibcon#wrote, iclass 15, count 0 2006.231.08:09:52.20#ibcon#about to read 3, iclass 15, count 0 2006.231.08:09:52.24#ibcon#read 3, iclass 15, count 0 2006.231.08:09:52.24#ibcon#about to read 4, iclass 15, count 0 2006.231.08:09:52.24#ibcon#read 4, iclass 15, count 0 2006.231.08:09:52.24#ibcon#about to read 5, iclass 15, count 0 2006.231.08:09:52.24#ibcon#read 5, iclass 15, count 0 2006.231.08:09:52.24#ibcon#about to read 6, iclass 15, count 0 2006.231.08:09:52.24#ibcon#read 6, iclass 15, count 0 2006.231.08:09:52.24#ibcon#end of sib2, iclass 15, count 0 2006.231.08:09:52.24#ibcon#*after write, iclass 15, count 0 2006.231.08:09:52.24#ibcon#*before return 0, iclass 15, count 0 2006.231.08:09:52.24#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:09:52.24#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:09:52.24#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:09:52.24#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:09:52.24$vc4f8/vb=6,4 2006.231.08:09:52.24#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.08:09:52.24#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.08:09:52.24#ibcon#ireg 11 cls_cnt 2 2006.231.08:09:52.24#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:09:52.30#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:09:52.30#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:09:52.30#ibcon#enter wrdev, iclass 17, count 2 2006.231.08:09:52.30#ibcon#first serial, iclass 17, count 2 2006.231.08:09:52.30#ibcon#enter sib2, iclass 17, count 2 2006.231.08:09:52.30#ibcon#flushed, iclass 17, count 2 2006.231.08:09:52.30#ibcon#about to write, iclass 17, count 2 2006.231.08:09:52.30#ibcon#wrote, iclass 17, count 2 2006.231.08:09:52.30#ibcon#about to read 3, iclass 17, count 2 2006.231.08:09:52.32#ibcon#read 3, iclass 17, count 2 2006.231.08:09:52.32#ibcon#about to read 4, iclass 17, count 2 2006.231.08:09:52.32#ibcon#read 4, iclass 17, count 2 2006.231.08:09:52.32#ibcon#about to read 5, iclass 17, count 2 2006.231.08:09:52.32#ibcon#read 5, iclass 17, count 2 2006.231.08:09:52.32#ibcon#about to read 6, iclass 17, count 2 2006.231.08:09:52.32#ibcon#read 6, iclass 17, count 2 2006.231.08:09:52.32#ibcon#end of sib2, iclass 17, count 2 2006.231.08:09:52.32#ibcon#*mode == 0, iclass 17, count 2 2006.231.08:09:52.32#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.08:09:52.32#ibcon#[27=AT06-04\r\n] 2006.231.08:09:52.32#ibcon#*before write, iclass 17, count 2 2006.231.08:09:52.32#ibcon#enter sib2, iclass 17, count 2 2006.231.08:09:52.32#ibcon#flushed, iclass 17, count 2 2006.231.08:09:52.32#ibcon#about to write, iclass 17, count 2 2006.231.08:09:52.32#ibcon#wrote, iclass 17, count 2 2006.231.08:09:52.32#ibcon#about to read 3, iclass 17, count 2 2006.231.08:09:52.35#ibcon#read 3, iclass 17, count 2 2006.231.08:09:52.35#ibcon#about to read 4, iclass 17, count 2 2006.231.08:09:52.35#ibcon#read 4, iclass 17, count 2 2006.231.08:09:52.35#ibcon#about to read 5, iclass 17, count 2 2006.231.08:09:52.35#ibcon#read 5, iclass 17, count 2 2006.231.08:09:52.35#ibcon#about to read 6, iclass 17, count 2 2006.231.08:09:52.35#ibcon#read 6, iclass 17, count 2 2006.231.08:09:52.35#ibcon#end of sib2, iclass 17, count 2 2006.231.08:09:52.35#ibcon#*after write, iclass 17, count 2 2006.231.08:09:52.35#ibcon#*before return 0, iclass 17, count 2 2006.231.08:09:52.35#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:09:52.35#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:09:52.35#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.08:09:52.35#ibcon#ireg 7 cls_cnt 0 2006.231.08:09:52.35#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:09:52.47#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:09:52.47#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:09:52.47#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:09:52.47#ibcon#first serial, iclass 17, count 0 2006.231.08:09:52.47#ibcon#enter sib2, iclass 17, count 0 2006.231.08:09:52.47#ibcon#flushed, iclass 17, count 0 2006.231.08:09:52.47#ibcon#about to write, iclass 17, count 0 2006.231.08:09:52.47#ibcon#wrote, iclass 17, count 0 2006.231.08:09:52.47#ibcon#about to read 3, iclass 17, count 0 2006.231.08:09:52.49#ibcon#read 3, iclass 17, count 0 2006.231.08:09:52.49#ibcon#about to read 4, iclass 17, count 0 2006.231.08:09:52.49#ibcon#read 4, iclass 17, count 0 2006.231.08:09:52.49#ibcon#about to read 5, iclass 17, count 0 2006.231.08:09:52.49#ibcon#read 5, iclass 17, count 0 2006.231.08:09:52.49#ibcon#about to read 6, iclass 17, count 0 2006.231.08:09:52.49#ibcon#read 6, iclass 17, count 0 2006.231.08:09:52.49#ibcon#end of sib2, iclass 17, count 0 2006.231.08:09:52.49#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:09:52.49#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:09:52.49#ibcon#[27=USB\r\n] 2006.231.08:09:52.49#ibcon#*before write, iclass 17, count 0 2006.231.08:09:52.49#ibcon#enter sib2, iclass 17, count 0 2006.231.08:09:52.49#ibcon#flushed, iclass 17, count 0 2006.231.08:09:52.49#ibcon#about to write, iclass 17, count 0 2006.231.08:09:52.49#ibcon#wrote, iclass 17, count 0 2006.231.08:09:52.49#ibcon#about to read 3, iclass 17, count 0 2006.231.08:09:52.52#ibcon#read 3, iclass 17, count 0 2006.231.08:09:52.52#ibcon#about to read 4, iclass 17, count 0 2006.231.08:09:52.52#ibcon#read 4, iclass 17, count 0 2006.231.08:09:52.52#ibcon#about to read 5, iclass 17, count 0 2006.231.08:09:52.52#ibcon#read 5, iclass 17, count 0 2006.231.08:09:52.52#ibcon#about to read 6, iclass 17, count 0 2006.231.08:09:52.52#ibcon#read 6, iclass 17, count 0 2006.231.08:09:52.52#ibcon#end of sib2, iclass 17, count 0 2006.231.08:09:52.52#ibcon#*after write, iclass 17, count 0 2006.231.08:09:52.52#ibcon#*before return 0, iclass 17, count 0 2006.231.08:09:52.52#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:09:52.52#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:09:52.52#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:09:52.52#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:09:52.52$vc4f8/vabw=wide 2006.231.08:09:52.52#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.08:09:52.52#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.08:09:52.52#ibcon#ireg 8 cls_cnt 0 2006.231.08:09:52.52#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:09:52.52#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:09:52.52#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:09:52.52#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:09:52.52#ibcon#first serial, iclass 19, count 0 2006.231.08:09:52.52#ibcon#enter sib2, iclass 19, count 0 2006.231.08:09:52.52#ibcon#flushed, iclass 19, count 0 2006.231.08:09:52.52#ibcon#about to write, iclass 19, count 0 2006.231.08:09:52.52#ibcon#wrote, iclass 19, count 0 2006.231.08:09:52.52#ibcon#about to read 3, iclass 19, count 0 2006.231.08:09:52.54#ibcon#read 3, iclass 19, count 0 2006.231.08:09:52.54#ibcon#about to read 4, iclass 19, count 0 2006.231.08:09:52.54#ibcon#read 4, iclass 19, count 0 2006.231.08:09:52.54#ibcon#about to read 5, iclass 19, count 0 2006.231.08:09:52.54#ibcon#read 5, iclass 19, count 0 2006.231.08:09:52.54#ibcon#about to read 6, iclass 19, count 0 2006.231.08:09:52.54#ibcon#read 6, iclass 19, count 0 2006.231.08:09:52.54#ibcon#end of sib2, iclass 19, count 0 2006.231.08:09:52.54#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:09:52.54#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:09:52.54#ibcon#[25=BW32\r\n] 2006.231.08:09:52.54#ibcon#*before write, iclass 19, count 0 2006.231.08:09:52.54#ibcon#enter sib2, iclass 19, count 0 2006.231.08:09:52.54#ibcon#flushed, iclass 19, count 0 2006.231.08:09:52.54#ibcon#about to write, iclass 19, count 0 2006.231.08:09:52.54#ibcon#wrote, iclass 19, count 0 2006.231.08:09:52.54#ibcon#about to read 3, iclass 19, count 0 2006.231.08:09:52.57#ibcon#read 3, iclass 19, count 0 2006.231.08:09:52.57#ibcon#about to read 4, iclass 19, count 0 2006.231.08:09:52.57#ibcon#read 4, iclass 19, count 0 2006.231.08:09:52.57#ibcon#about to read 5, iclass 19, count 0 2006.231.08:09:52.57#ibcon#read 5, iclass 19, count 0 2006.231.08:09:52.57#ibcon#about to read 6, iclass 19, count 0 2006.231.08:09:52.57#ibcon#read 6, iclass 19, count 0 2006.231.08:09:52.57#ibcon#end of sib2, iclass 19, count 0 2006.231.08:09:52.57#ibcon#*after write, iclass 19, count 0 2006.231.08:09:52.57#ibcon#*before return 0, iclass 19, count 0 2006.231.08:09:52.57#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:09:52.57#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:09:52.57#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:09:52.57#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:09:52.57$vc4f8/vbbw=wide 2006.231.08:09:52.57#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.08:09:52.57#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.08:09:52.57#ibcon#ireg 8 cls_cnt 0 2006.231.08:09:52.57#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:09:52.64#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:09:52.64#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:09:52.64#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:09:52.64#ibcon#first serial, iclass 21, count 0 2006.231.08:09:52.64#ibcon#enter sib2, iclass 21, count 0 2006.231.08:09:52.64#ibcon#flushed, iclass 21, count 0 2006.231.08:09:52.65#ibcon#about to write, iclass 21, count 0 2006.231.08:09:52.65#ibcon#wrote, iclass 21, count 0 2006.231.08:09:52.65#ibcon#about to read 3, iclass 21, count 0 2006.231.08:09:52.66#ibcon#read 3, iclass 21, count 0 2006.231.08:09:52.66#ibcon#about to read 4, iclass 21, count 0 2006.231.08:09:52.66#ibcon#read 4, iclass 21, count 0 2006.231.08:09:52.66#ibcon#about to read 5, iclass 21, count 0 2006.231.08:09:52.66#ibcon#read 5, iclass 21, count 0 2006.231.08:09:52.66#ibcon#about to read 6, iclass 21, count 0 2006.231.08:09:52.66#ibcon#read 6, iclass 21, count 0 2006.231.08:09:52.66#ibcon#end of sib2, iclass 21, count 0 2006.231.08:09:52.66#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:09:52.66#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:09:52.66#ibcon#[27=BW32\r\n] 2006.231.08:09:52.66#ibcon#*before write, iclass 21, count 0 2006.231.08:09:52.66#ibcon#enter sib2, iclass 21, count 0 2006.231.08:09:52.66#ibcon#flushed, iclass 21, count 0 2006.231.08:09:52.66#ibcon#about to write, iclass 21, count 0 2006.231.08:09:52.66#ibcon#wrote, iclass 21, count 0 2006.231.08:09:52.66#ibcon#about to read 3, iclass 21, count 0 2006.231.08:09:52.69#ibcon#read 3, iclass 21, count 0 2006.231.08:09:52.69#ibcon#about to read 4, iclass 21, count 0 2006.231.08:09:52.69#ibcon#read 4, iclass 21, count 0 2006.231.08:09:52.69#ibcon#about to read 5, iclass 21, count 0 2006.231.08:09:52.69#ibcon#read 5, iclass 21, count 0 2006.231.08:09:52.69#ibcon#about to read 6, iclass 21, count 0 2006.231.08:09:52.69#ibcon#read 6, iclass 21, count 0 2006.231.08:09:52.69#ibcon#end of sib2, iclass 21, count 0 2006.231.08:09:52.69#ibcon#*after write, iclass 21, count 0 2006.231.08:09:52.69#ibcon#*before return 0, iclass 21, count 0 2006.231.08:09:52.69#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:09:52.69#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:09:52.69#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:09:52.69#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:09:52.69$4f8m12a/ifd4f 2006.231.08:09:52.69$ifd4f/lo= 2006.231.08:09:52.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:09:52.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:09:52.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:09:52.69$ifd4f/patch= 2006.231.08:09:52.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:09:52.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:09:52.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:09:52.69$4f8m12a/"form=m,16.000,1:2 2006.231.08:09:52.69$4f8m12a/"tpicd 2006.231.08:09:52.70$4f8m12a/echo=off 2006.231.08:09:52.70$4f8m12a/xlog=off 2006.231.08:09:52.70:!2006.231.08:10:20 2006.231.08:10:02.13#trakl#Source acquired 2006.231.08:10:02.13#flagr#flagr/antenna,acquired 2006.231.08:10:20.01:preob 2006.231.08:10:21.14/onsource/TRACKING 2006.231.08:10:21.14:!2006.231.08:10:30 2006.231.08:10:30.00:data_valid=on 2006.231.08:10:30.00:midob 2006.231.08:10:30.14/onsource/TRACKING 2006.231.08:10:30.14/wx/30.47,1004.5,85 2006.231.08:10:30.26/cable/+6.3743E-03 2006.231.08:10:31.35/va/01,08,usb,yes,29,31 2006.231.08:10:31.35/va/02,07,usb,yes,29,31 2006.231.08:10:31.35/va/03,08,usb,yes,22,22 2006.231.08:10:31.35/va/04,07,usb,yes,31,33 2006.231.08:10:31.35/va/05,07,usb,yes,34,35 2006.231.08:10:31.35/va/06,06,usb,yes,33,33 2006.231.08:10:31.35/va/07,06,usb,yes,33,33 2006.231.08:10:31.35/va/08,06,usb,yes,36,35 2006.231.08:10:31.58/valo/01,532.99,yes,locked 2006.231.08:10:31.58/valo/02,572.99,yes,locked 2006.231.08:10:31.58/valo/03,672.99,yes,locked 2006.231.08:10:31.58/valo/04,832.99,yes,locked 2006.231.08:10:31.58/valo/05,652.99,yes,locked 2006.231.08:10:31.58/valo/06,772.99,yes,locked 2006.231.08:10:31.58/valo/07,832.99,yes,locked 2006.231.08:10:31.58/valo/08,852.99,yes,locked 2006.231.08:10:32.67/vb/01,04,usb,yes,30,29 2006.231.08:10:32.67/vb/02,04,usb,yes,32,33 2006.231.08:10:32.67/vb/03,04,usb,yes,28,32 2006.231.08:10:32.67/vb/04,04,usb,yes,29,29 2006.231.08:10:32.67/vb/05,03,usb,yes,35,39 2006.231.08:10:32.67/vb/06,04,usb,yes,28,31 2006.231.08:10:32.67/vb/07,04,usb,yes,31,31 2006.231.08:10:32.67/vb/08,04,usb,yes,28,32 2006.231.08:10:32.91/vblo/01,632.99,yes,locked 2006.231.08:10:32.91/vblo/02,640.99,yes,locked 2006.231.08:10:32.91/vblo/03,656.99,yes,locked 2006.231.08:10:32.91/vblo/04,712.99,yes,locked 2006.231.08:10:32.91/vblo/05,744.99,yes,locked 2006.231.08:10:32.91/vblo/06,752.99,yes,locked 2006.231.08:10:32.91/vblo/07,734.99,yes,locked 2006.231.08:10:32.91/vblo/08,744.99,yes,locked 2006.231.08:10:33.06/vabw/8 2006.231.08:10:33.21/vbbw/8 2006.231.08:10:33.36/xfe/off,on,12.2 2006.231.08:10:33.73/ifatt/23,28,28,28 2006.231.08:10:34.07/fmout-gps/S +4.44E-07 2006.231.08:10:34.11:!2006.231.08:11:30 2006.231.08:11:30.00:data_valid=off 2006.231.08:11:30.01:postob 2006.231.08:11:30.08/cable/+6.3732E-03 2006.231.08:11:30.08/wx/30.46,1004.5,86 2006.231.08:11:31.07/fmout-gps/S +4.44E-07 2006.231.08:11:31.07:scan_name=231-0812,k06231,60 2006.231.08:11:31.07:source=1357+769,135755.37,764321.1,2000.0,neutral 2006.231.08:11:31.14#flagr#flagr/antenna,new-source 2006.231.08:11:32.14:checkk5 2006.231.08:11:32.48/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:11:32.85/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:11:33.23/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:11:33.60/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:11:33.96/chk_obsdata//k5ts1/T2310810??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:11:34.33/chk_obsdata//k5ts2/T2310810??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:11:34.70/chk_obsdata//k5ts3/T2310810??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:11:35.07/chk_obsdata//k5ts4/T2310810??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:11:35.75/k5log//k5ts1_log_newline 2006.231.08:11:36.45/k5log//k5ts2_log_newline 2006.231.08:11:37.14/k5log//k5ts3_log_newline 2006.231.08:11:37.83/k5log//k5ts4_log_newline 2006.231.08:11:37.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:11:37.85:4f8m12a=2 2006.231.08:11:37.85$4f8m12a/echo=on 2006.231.08:11:37.85$4f8m12a/pcalon 2006.231.08:11:37.85$pcalon/"no phase cal control is implemented here 2006.231.08:11:37.85$4f8m12a/"tpicd=stop 2006.231.08:11:37.85$4f8m12a/vc4f8 2006.231.08:11:37.85$vc4f8/valo=1,532.99 2006.231.08:11:37.86#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.231.08:11:37.86#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.231.08:11:37.86#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:37.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:11:37.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:11:37.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:11:37.86#ibcon#enter wrdev, iclass 28, count 0 2006.231.08:11:37.86#ibcon#first serial, iclass 28, count 0 2006.231.08:11:37.86#ibcon#enter sib2, iclass 28, count 0 2006.231.08:11:37.86#ibcon#flushed, iclass 28, count 0 2006.231.08:11:37.86#ibcon#about to write, iclass 28, count 0 2006.231.08:11:37.86#ibcon#wrote, iclass 28, count 0 2006.231.08:11:37.86#ibcon#about to read 3, iclass 28, count 0 2006.231.08:11:37.87#ibcon#read 3, iclass 28, count 0 2006.231.08:11:37.87#ibcon#about to read 4, iclass 28, count 0 2006.231.08:11:37.87#ibcon#read 4, iclass 28, count 0 2006.231.08:11:37.87#ibcon#about to read 5, iclass 28, count 0 2006.231.08:11:37.87#ibcon#read 5, iclass 28, count 0 2006.231.08:11:37.87#ibcon#about to read 6, iclass 28, count 0 2006.231.08:11:37.87#ibcon#read 6, iclass 28, count 0 2006.231.08:11:37.87#ibcon#end of sib2, iclass 28, count 0 2006.231.08:11:37.87#ibcon#*mode == 0, iclass 28, count 0 2006.231.08:11:37.87#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.08:11:37.87#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:11:37.87#ibcon#*before write, iclass 28, count 0 2006.231.08:11:37.87#ibcon#enter sib2, iclass 28, count 0 2006.231.08:11:37.87#ibcon#flushed, iclass 28, count 0 2006.231.08:11:37.87#ibcon#about to write, iclass 28, count 0 2006.231.08:11:37.87#ibcon#wrote, iclass 28, count 0 2006.231.08:11:37.87#ibcon#about to read 3, iclass 28, count 0 2006.231.08:11:37.92#ibcon#read 3, iclass 28, count 0 2006.231.08:11:37.92#ibcon#about to read 4, iclass 28, count 0 2006.231.08:11:37.92#ibcon#read 4, iclass 28, count 0 2006.231.08:11:37.92#ibcon#about to read 5, iclass 28, count 0 2006.231.08:11:37.92#ibcon#read 5, iclass 28, count 0 2006.231.08:11:37.92#ibcon#about to read 6, iclass 28, count 0 2006.231.08:11:37.92#ibcon#read 6, iclass 28, count 0 2006.231.08:11:37.92#ibcon#end of sib2, iclass 28, count 0 2006.231.08:11:37.92#ibcon#*after write, iclass 28, count 0 2006.231.08:11:37.92#ibcon#*before return 0, iclass 28, count 0 2006.231.08:11:37.92#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:11:37.92#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:11:37.92#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.08:11:37.92#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.08:11:37.92$vc4f8/va=1,8 2006.231.08:11:37.92#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.08:11:37.92#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.08:11:37.92#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:37.92#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:11:37.92#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:11:37.92#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:11:37.92#ibcon#enter wrdev, iclass 30, count 2 2006.231.08:11:37.92#ibcon#first serial, iclass 30, count 2 2006.231.08:11:37.92#ibcon#enter sib2, iclass 30, count 2 2006.231.08:11:37.92#ibcon#flushed, iclass 30, count 2 2006.231.08:11:37.92#ibcon#about to write, iclass 30, count 2 2006.231.08:11:37.92#ibcon#wrote, iclass 30, count 2 2006.231.08:11:37.92#ibcon#about to read 3, iclass 30, count 2 2006.231.08:11:37.94#ibcon#read 3, iclass 30, count 2 2006.231.08:11:37.94#ibcon#about to read 4, iclass 30, count 2 2006.231.08:11:37.94#ibcon#read 4, iclass 30, count 2 2006.231.08:11:37.94#ibcon#about to read 5, iclass 30, count 2 2006.231.08:11:37.94#ibcon#read 5, iclass 30, count 2 2006.231.08:11:37.94#ibcon#about to read 6, iclass 30, count 2 2006.231.08:11:37.94#ibcon#read 6, iclass 30, count 2 2006.231.08:11:37.94#ibcon#end of sib2, iclass 30, count 2 2006.231.08:11:37.94#ibcon#*mode == 0, iclass 30, count 2 2006.231.08:11:37.94#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.08:11:37.94#ibcon#[25=AT01-08\r\n] 2006.231.08:11:37.94#ibcon#*before write, iclass 30, count 2 2006.231.08:11:37.94#ibcon#enter sib2, iclass 30, count 2 2006.231.08:11:37.94#ibcon#flushed, iclass 30, count 2 2006.231.08:11:37.94#ibcon#about to write, iclass 30, count 2 2006.231.08:11:37.94#ibcon#wrote, iclass 30, count 2 2006.231.08:11:37.94#ibcon#about to read 3, iclass 30, count 2 2006.231.08:11:37.97#ibcon#read 3, iclass 30, count 2 2006.231.08:11:37.97#ibcon#about to read 4, iclass 30, count 2 2006.231.08:11:37.97#ibcon#read 4, iclass 30, count 2 2006.231.08:11:37.97#ibcon#about to read 5, iclass 30, count 2 2006.231.08:11:37.97#ibcon#read 5, iclass 30, count 2 2006.231.08:11:37.97#ibcon#about to read 6, iclass 30, count 2 2006.231.08:11:37.97#ibcon#read 6, iclass 30, count 2 2006.231.08:11:37.97#ibcon#end of sib2, iclass 30, count 2 2006.231.08:11:37.97#ibcon#*after write, iclass 30, count 2 2006.231.08:11:37.97#ibcon#*before return 0, iclass 30, count 2 2006.231.08:11:37.97#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:11:37.97#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:11:37.97#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.08:11:37.97#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:37.97#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:11:38.09#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:11:38.09#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:11:38.09#ibcon#enter wrdev, iclass 30, count 0 2006.231.08:11:38.09#ibcon#first serial, iclass 30, count 0 2006.231.08:11:38.09#ibcon#enter sib2, iclass 30, count 0 2006.231.08:11:38.09#ibcon#flushed, iclass 30, count 0 2006.231.08:11:38.09#ibcon#about to write, iclass 30, count 0 2006.231.08:11:38.09#ibcon#wrote, iclass 30, count 0 2006.231.08:11:38.09#ibcon#about to read 3, iclass 30, count 0 2006.231.08:11:38.11#ibcon#read 3, iclass 30, count 0 2006.231.08:11:38.11#ibcon#about to read 4, iclass 30, count 0 2006.231.08:11:38.11#ibcon#read 4, iclass 30, count 0 2006.231.08:11:38.11#ibcon#about to read 5, iclass 30, count 0 2006.231.08:11:38.11#ibcon#read 5, iclass 30, count 0 2006.231.08:11:38.11#ibcon#about to read 6, iclass 30, count 0 2006.231.08:11:38.11#ibcon#read 6, iclass 30, count 0 2006.231.08:11:38.11#ibcon#end of sib2, iclass 30, count 0 2006.231.08:11:38.11#ibcon#*mode == 0, iclass 30, count 0 2006.231.08:11:38.11#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.08:11:38.11#ibcon#[25=USB\r\n] 2006.231.08:11:38.11#ibcon#*before write, iclass 30, count 0 2006.231.08:11:38.11#ibcon#enter sib2, iclass 30, count 0 2006.231.08:11:38.11#ibcon#flushed, iclass 30, count 0 2006.231.08:11:38.11#ibcon#about to write, iclass 30, count 0 2006.231.08:11:38.11#ibcon#wrote, iclass 30, count 0 2006.231.08:11:38.11#ibcon#about to read 3, iclass 30, count 0 2006.231.08:11:38.14#ibcon#read 3, iclass 30, count 0 2006.231.08:11:38.14#ibcon#about to read 4, iclass 30, count 0 2006.231.08:11:38.14#ibcon#read 4, iclass 30, count 0 2006.231.08:11:38.14#ibcon#about to read 5, iclass 30, count 0 2006.231.08:11:38.14#ibcon#read 5, iclass 30, count 0 2006.231.08:11:38.14#ibcon#about to read 6, iclass 30, count 0 2006.231.08:11:38.14#ibcon#read 6, iclass 30, count 0 2006.231.08:11:38.14#ibcon#end of sib2, iclass 30, count 0 2006.231.08:11:38.14#ibcon#*after write, iclass 30, count 0 2006.231.08:11:38.14#ibcon#*before return 0, iclass 30, count 0 2006.231.08:11:38.14#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:11:38.14#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:11:38.14#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.08:11:38.14#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.08:11:38.14$vc4f8/valo=2,572.99 2006.231.08:11:38.14#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.08:11:38.14#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.08:11:38.14#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:38.14#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:11:38.14#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:11:38.14#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:11:38.14#ibcon#enter wrdev, iclass 32, count 0 2006.231.08:11:38.14#ibcon#first serial, iclass 32, count 0 2006.231.08:11:38.14#ibcon#enter sib2, iclass 32, count 0 2006.231.08:11:38.14#ibcon#flushed, iclass 32, count 0 2006.231.08:11:38.14#ibcon#about to write, iclass 32, count 0 2006.231.08:11:38.14#ibcon#wrote, iclass 32, count 0 2006.231.08:11:38.14#ibcon#about to read 3, iclass 32, count 0 2006.231.08:11:38.16#ibcon#read 3, iclass 32, count 0 2006.231.08:11:38.16#ibcon#about to read 4, iclass 32, count 0 2006.231.08:11:38.16#ibcon#read 4, iclass 32, count 0 2006.231.08:11:38.16#ibcon#about to read 5, iclass 32, count 0 2006.231.08:11:38.16#ibcon#read 5, iclass 32, count 0 2006.231.08:11:38.16#ibcon#about to read 6, iclass 32, count 0 2006.231.08:11:38.16#ibcon#read 6, iclass 32, count 0 2006.231.08:11:38.16#ibcon#end of sib2, iclass 32, count 0 2006.231.08:11:38.16#ibcon#*mode == 0, iclass 32, count 0 2006.231.08:11:38.16#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.08:11:38.16#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:11:38.16#ibcon#*before write, iclass 32, count 0 2006.231.08:11:38.16#ibcon#enter sib2, iclass 32, count 0 2006.231.08:11:38.16#ibcon#flushed, iclass 32, count 0 2006.231.08:11:38.16#ibcon#about to write, iclass 32, count 0 2006.231.08:11:38.16#ibcon#wrote, iclass 32, count 0 2006.231.08:11:38.16#ibcon#about to read 3, iclass 32, count 0 2006.231.08:11:38.20#ibcon#read 3, iclass 32, count 0 2006.231.08:11:38.20#ibcon#about to read 4, iclass 32, count 0 2006.231.08:11:38.20#ibcon#read 4, iclass 32, count 0 2006.231.08:11:38.20#ibcon#about to read 5, iclass 32, count 0 2006.231.08:11:38.20#ibcon#read 5, iclass 32, count 0 2006.231.08:11:38.20#ibcon#about to read 6, iclass 32, count 0 2006.231.08:11:38.20#ibcon#read 6, iclass 32, count 0 2006.231.08:11:38.20#ibcon#end of sib2, iclass 32, count 0 2006.231.08:11:38.20#ibcon#*after write, iclass 32, count 0 2006.231.08:11:38.20#ibcon#*before return 0, iclass 32, count 0 2006.231.08:11:38.20#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:11:38.20#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:11:38.20#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.08:11:38.20#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.08:11:38.20$vc4f8/va=2,7 2006.231.08:11:38.20#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.08:11:38.20#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.08:11:38.20#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:38.20#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:11:38.26#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:11:38.26#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:11:38.26#ibcon#enter wrdev, iclass 34, count 2 2006.231.08:11:38.26#ibcon#first serial, iclass 34, count 2 2006.231.08:11:38.26#ibcon#enter sib2, iclass 34, count 2 2006.231.08:11:38.26#ibcon#flushed, iclass 34, count 2 2006.231.08:11:38.26#ibcon#about to write, iclass 34, count 2 2006.231.08:11:38.26#ibcon#wrote, iclass 34, count 2 2006.231.08:11:38.26#ibcon#about to read 3, iclass 34, count 2 2006.231.08:11:38.28#ibcon#read 3, iclass 34, count 2 2006.231.08:11:38.28#ibcon#about to read 4, iclass 34, count 2 2006.231.08:11:38.28#ibcon#read 4, iclass 34, count 2 2006.231.08:11:38.28#ibcon#about to read 5, iclass 34, count 2 2006.231.08:11:38.28#ibcon#read 5, iclass 34, count 2 2006.231.08:11:38.28#ibcon#about to read 6, iclass 34, count 2 2006.231.08:11:38.28#ibcon#read 6, iclass 34, count 2 2006.231.08:11:38.28#ibcon#end of sib2, iclass 34, count 2 2006.231.08:11:38.28#ibcon#*mode == 0, iclass 34, count 2 2006.231.08:11:38.28#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.08:11:38.28#ibcon#[25=AT02-07\r\n] 2006.231.08:11:38.28#ibcon#*before write, iclass 34, count 2 2006.231.08:11:38.28#ibcon#enter sib2, iclass 34, count 2 2006.231.08:11:38.28#ibcon#flushed, iclass 34, count 2 2006.231.08:11:38.28#ibcon#about to write, iclass 34, count 2 2006.231.08:11:38.28#ibcon#wrote, iclass 34, count 2 2006.231.08:11:38.28#ibcon#about to read 3, iclass 34, count 2 2006.231.08:11:38.31#ibcon#read 3, iclass 34, count 2 2006.231.08:11:38.31#ibcon#about to read 4, iclass 34, count 2 2006.231.08:11:38.31#ibcon#read 4, iclass 34, count 2 2006.231.08:11:38.31#ibcon#about to read 5, iclass 34, count 2 2006.231.08:11:38.31#ibcon#read 5, iclass 34, count 2 2006.231.08:11:38.31#ibcon#about to read 6, iclass 34, count 2 2006.231.08:11:38.31#ibcon#read 6, iclass 34, count 2 2006.231.08:11:38.31#ibcon#end of sib2, iclass 34, count 2 2006.231.08:11:38.31#ibcon#*after write, iclass 34, count 2 2006.231.08:11:38.31#ibcon#*before return 0, iclass 34, count 2 2006.231.08:11:38.31#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:11:38.31#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:11:38.31#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.08:11:38.31#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:38.31#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:11:38.43#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:11:38.43#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:11:38.43#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:11:38.43#ibcon#first serial, iclass 34, count 0 2006.231.08:11:38.43#ibcon#enter sib2, iclass 34, count 0 2006.231.08:11:38.43#ibcon#flushed, iclass 34, count 0 2006.231.08:11:38.43#ibcon#about to write, iclass 34, count 0 2006.231.08:11:38.43#ibcon#wrote, iclass 34, count 0 2006.231.08:11:38.43#ibcon#about to read 3, iclass 34, count 0 2006.231.08:11:38.45#ibcon#read 3, iclass 34, count 0 2006.231.08:11:38.45#ibcon#about to read 4, iclass 34, count 0 2006.231.08:11:38.45#ibcon#read 4, iclass 34, count 0 2006.231.08:11:38.45#ibcon#about to read 5, iclass 34, count 0 2006.231.08:11:38.45#ibcon#read 5, iclass 34, count 0 2006.231.08:11:38.45#ibcon#about to read 6, iclass 34, count 0 2006.231.08:11:38.45#ibcon#read 6, iclass 34, count 0 2006.231.08:11:38.46#ibcon#end of sib2, iclass 34, count 0 2006.231.08:11:38.46#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:11:38.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:11:38.46#ibcon#[25=USB\r\n] 2006.231.08:11:38.46#ibcon#*before write, iclass 34, count 0 2006.231.08:11:38.46#ibcon#enter sib2, iclass 34, count 0 2006.231.08:11:38.46#ibcon#flushed, iclass 34, count 0 2006.231.08:11:38.46#ibcon#about to write, iclass 34, count 0 2006.231.08:11:38.46#ibcon#wrote, iclass 34, count 0 2006.231.08:11:38.46#ibcon#about to read 3, iclass 34, count 0 2006.231.08:11:38.48#ibcon#read 3, iclass 34, count 0 2006.231.08:11:38.48#ibcon#about to read 4, iclass 34, count 0 2006.231.08:11:38.48#ibcon#read 4, iclass 34, count 0 2006.231.08:11:38.48#ibcon#about to read 5, iclass 34, count 0 2006.231.08:11:38.48#ibcon#read 5, iclass 34, count 0 2006.231.08:11:38.48#ibcon#about to read 6, iclass 34, count 0 2006.231.08:11:38.48#ibcon#read 6, iclass 34, count 0 2006.231.08:11:38.48#ibcon#end of sib2, iclass 34, count 0 2006.231.08:11:38.48#ibcon#*after write, iclass 34, count 0 2006.231.08:11:38.48#ibcon#*before return 0, iclass 34, count 0 2006.231.08:11:38.48#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:11:38.48#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:11:38.48#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:11:38.48#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:11:38.48$vc4f8/valo=3,672.99 2006.231.08:11:38.48#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.08:11:38.48#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.08:11:38.48#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:38.48#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:11:38.48#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:11:38.48#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:11:38.48#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:11:38.48#ibcon#first serial, iclass 36, count 0 2006.231.08:11:38.48#ibcon#enter sib2, iclass 36, count 0 2006.231.08:11:38.48#ibcon#flushed, iclass 36, count 0 2006.231.08:11:38.48#ibcon#about to write, iclass 36, count 0 2006.231.08:11:38.48#ibcon#wrote, iclass 36, count 0 2006.231.08:11:38.48#ibcon#about to read 3, iclass 36, count 0 2006.231.08:11:38.50#ibcon#read 3, iclass 36, count 0 2006.231.08:11:38.50#ibcon#about to read 4, iclass 36, count 0 2006.231.08:11:38.50#ibcon#read 4, iclass 36, count 0 2006.231.08:11:38.50#ibcon#about to read 5, iclass 36, count 0 2006.231.08:11:38.50#ibcon#read 5, iclass 36, count 0 2006.231.08:11:38.50#ibcon#about to read 6, iclass 36, count 0 2006.231.08:11:38.50#ibcon#read 6, iclass 36, count 0 2006.231.08:11:38.50#ibcon#end of sib2, iclass 36, count 0 2006.231.08:11:38.50#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:11:38.50#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:11:38.50#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:11:38.50#ibcon#*before write, iclass 36, count 0 2006.231.08:11:38.50#ibcon#enter sib2, iclass 36, count 0 2006.231.08:11:38.50#ibcon#flushed, iclass 36, count 0 2006.231.08:11:38.50#ibcon#about to write, iclass 36, count 0 2006.231.08:11:38.50#ibcon#wrote, iclass 36, count 0 2006.231.08:11:38.50#ibcon#about to read 3, iclass 36, count 0 2006.231.08:11:38.54#ibcon#read 3, iclass 36, count 0 2006.231.08:11:38.54#ibcon#about to read 4, iclass 36, count 0 2006.231.08:11:38.54#ibcon#read 4, iclass 36, count 0 2006.231.08:11:38.54#ibcon#about to read 5, iclass 36, count 0 2006.231.08:11:38.54#ibcon#read 5, iclass 36, count 0 2006.231.08:11:38.54#ibcon#about to read 6, iclass 36, count 0 2006.231.08:11:38.54#ibcon#read 6, iclass 36, count 0 2006.231.08:11:38.54#ibcon#end of sib2, iclass 36, count 0 2006.231.08:11:38.54#ibcon#*after write, iclass 36, count 0 2006.231.08:11:38.54#ibcon#*before return 0, iclass 36, count 0 2006.231.08:11:38.54#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:11:38.54#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:11:38.54#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:11:38.54#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:11:38.54$vc4f8/va=3,8 2006.231.08:11:38.54#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.08:11:38.54#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.08:11:38.54#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:38.54#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:11:38.60#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:11:38.60#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:11:38.60#ibcon#enter wrdev, iclass 38, count 2 2006.231.08:11:38.60#ibcon#first serial, iclass 38, count 2 2006.231.08:11:38.60#ibcon#enter sib2, iclass 38, count 2 2006.231.08:11:38.60#ibcon#flushed, iclass 38, count 2 2006.231.08:11:38.60#ibcon#about to write, iclass 38, count 2 2006.231.08:11:38.60#ibcon#wrote, iclass 38, count 2 2006.231.08:11:38.60#ibcon#about to read 3, iclass 38, count 2 2006.231.08:11:38.62#ibcon#read 3, iclass 38, count 2 2006.231.08:11:38.62#ibcon#about to read 4, iclass 38, count 2 2006.231.08:11:38.62#ibcon#read 4, iclass 38, count 2 2006.231.08:11:38.62#ibcon#about to read 5, iclass 38, count 2 2006.231.08:11:38.62#ibcon#read 5, iclass 38, count 2 2006.231.08:11:38.62#ibcon#about to read 6, iclass 38, count 2 2006.231.08:11:38.62#ibcon#read 6, iclass 38, count 2 2006.231.08:11:38.62#ibcon#end of sib2, iclass 38, count 2 2006.231.08:11:38.62#ibcon#*mode == 0, iclass 38, count 2 2006.231.08:11:38.62#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.08:11:38.62#ibcon#[25=AT03-08\r\n] 2006.231.08:11:38.62#ibcon#*before write, iclass 38, count 2 2006.231.08:11:38.62#ibcon#enter sib2, iclass 38, count 2 2006.231.08:11:38.62#ibcon#flushed, iclass 38, count 2 2006.231.08:11:38.62#ibcon#about to write, iclass 38, count 2 2006.231.08:11:38.62#ibcon#wrote, iclass 38, count 2 2006.231.08:11:38.62#ibcon#about to read 3, iclass 38, count 2 2006.231.08:11:38.66#ibcon#read 3, iclass 38, count 2 2006.231.08:11:38.66#ibcon#about to read 4, iclass 38, count 2 2006.231.08:11:38.66#ibcon#read 4, iclass 38, count 2 2006.231.08:11:38.66#ibcon#about to read 5, iclass 38, count 2 2006.231.08:11:38.66#ibcon#read 5, iclass 38, count 2 2006.231.08:11:38.66#ibcon#about to read 6, iclass 38, count 2 2006.231.08:11:38.66#ibcon#read 6, iclass 38, count 2 2006.231.08:11:38.66#ibcon#end of sib2, iclass 38, count 2 2006.231.08:11:38.66#ibcon#*after write, iclass 38, count 2 2006.231.08:11:38.66#ibcon#*before return 0, iclass 38, count 2 2006.231.08:11:38.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:11:38.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:11:38.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.08:11:38.66#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:38.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:11:38.77#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:11:38.77#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:11:38.77#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:11:38.77#ibcon#first serial, iclass 38, count 0 2006.231.08:11:38.77#ibcon#enter sib2, iclass 38, count 0 2006.231.08:11:38.77#ibcon#flushed, iclass 38, count 0 2006.231.08:11:38.77#ibcon#about to write, iclass 38, count 0 2006.231.08:11:38.77#ibcon#wrote, iclass 38, count 0 2006.231.08:11:38.77#ibcon#about to read 3, iclass 38, count 0 2006.231.08:11:38.79#ibcon#read 3, iclass 38, count 0 2006.231.08:11:38.79#ibcon#about to read 4, iclass 38, count 0 2006.231.08:11:38.79#ibcon#read 4, iclass 38, count 0 2006.231.08:11:38.79#ibcon#about to read 5, iclass 38, count 0 2006.231.08:11:38.79#ibcon#read 5, iclass 38, count 0 2006.231.08:11:38.79#ibcon#about to read 6, iclass 38, count 0 2006.231.08:11:38.79#ibcon#read 6, iclass 38, count 0 2006.231.08:11:38.79#ibcon#end of sib2, iclass 38, count 0 2006.231.08:11:38.79#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:11:38.79#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:11:38.79#ibcon#[25=USB\r\n] 2006.231.08:11:38.79#ibcon#*before write, iclass 38, count 0 2006.231.08:11:38.79#ibcon#enter sib2, iclass 38, count 0 2006.231.08:11:38.79#ibcon#flushed, iclass 38, count 0 2006.231.08:11:38.79#ibcon#about to write, iclass 38, count 0 2006.231.08:11:38.79#ibcon#wrote, iclass 38, count 0 2006.231.08:11:38.79#ibcon#about to read 3, iclass 38, count 0 2006.231.08:11:38.82#ibcon#read 3, iclass 38, count 0 2006.231.08:11:38.82#ibcon#about to read 4, iclass 38, count 0 2006.231.08:11:38.82#ibcon#read 4, iclass 38, count 0 2006.231.08:11:38.82#ibcon#about to read 5, iclass 38, count 0 2006.231.08:11:38.82#ibcon#read 5, iclass 38, count 0 2006.231.08:11:38.82#ibcon#about to read 6, iclass 38, count 0 2006.231.08:11:38.82#ibcon#read 6, iclass 38, count 0 2006.231.08:11:38.82#ibcon#end of sib2, iclass 38, count 0 2006.231.08:11:38.82#ibcon#*after write, iclass 38, count 0 2006.231.08:11:38.82#ibcon#*before return 0, iclass 38, count 0 2006.231.08:11:38.82#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:11:38.82#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:11:38.82#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:11:38.82#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:11:38.82$vc4f8/valo=4,832.99 2006.231.08:11:38.82#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.08:11:38.82#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.08:11:38.82#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:38.82#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:11:38.82#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:11:38.82#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:11:38.82#ibcon#enter wrdev, iclass 40, count 0 2006.231.08:11:38.82#ibcon#first serial, iclass 40, count 0 2006.231.08:11:38.82#ibcon#enter sib2, iclass 40, count 0 2006.231.08:11:38.82#ibcon#flushed, iclass 40, count 0 2006.231.08:11:38.82#ibcon#about to write, iclass 40, count 0 2006.231.08:11:38.82#ibcon#wrote, iclass 40, count 0 2006.231.08:11:38.82#ibcon#about to read 3, iclass 40, count 0 2006.231.08:11:38.84#ibcon#read 3, iclass 40, count 0 2006.231.08:11:38.84#ibcon#about to read 4, iclass 40, count 0 2006.231.08:11:38.84#ibcon#read 4, iclass 40, count 0 2006.231.08:11:38.84#ibcon#about to read 5, iclass 40, count 0 2006.231.08:11:38.84#ibcon#read 5, iclass 40, count 0 2006.231.08:11:38.84#ibcon#about to read 6, iclass 40, count 0 2006.231.08:11:38.84#ibcon#read 6, iclass 40, count 0 2006.231.08:11:38.84#ibcon#end of sib2, iclass 40, count 0 2006.231.08:11:38.84#ibcon#*mode == 0, iclass 40, count 0 2006.231.08:11:38.84#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.08:11:38.84#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:11:38.84#ibcon#*before write, iclass 40, count 0 2006.231.08:11:38.84#ibcon#enter sib2, iclass 40, count 0 2006.231.08:11:38.84#ibcon#flushed, iclass 40, count 0 2006.231.08:11:38.84#ibcon#about to write, iclass 40, count 0 2006.231.08:11:38.84#ibcon#wrote, iclass 40, count 0 2006.231.08:11:38.84#ibcon#about to read 3, iclass 40, count 0 2006.231.08:11:38.88#ibcon#read 3, iclass 40, count 0 2006.231.08:11:38.88#ibcon#about to read 4, iclass 40, count 0 2006.231.08:11:38.88#ibcon#read 4, iclass 40, count 0 2006.231.08:11:38.88#ibcon#about to read 5, iclass 40, count 0 2006.231.08:11:38.88#ibcon#read 5, iclass 40, count 0 2006.231.08:11:38.88#ibcon#about to read 6, iclass 40, count 0 2006.231.08:11:38.88#ibcon#read 6, iclass 40, count 0 2006.231.08:11:38.88#ibcon#end of sib2, iclass 40, count 0 2006.231.08:11:38.88#ibcon#*after write, iclass 40, count 0 2006.231.08:11:38.88#ibcon#*before return 0, iclass 40, count 0 2006.231.08:11:38.88#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:11:38.88#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:11:38.88#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.08:11:38.88#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.08:11:38.88$vc4f8/va=4,7 2006.231.08:11:38.88#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.231.08:11:38.88#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.231.08:11:38.88#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:38.88#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:11:38.94#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:11:38.94#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:11:38.94#ibcon#enter wrdev, iclass 4, count 2 2006.231.08:11:38.94#ibcon#first serial, iclass 4, count 2 2006.231.08:11:38.94#ibcon#enter sib2, iclass 4, count 2 2006.231.08:11:38.94#ibcon#flushed, iclass 4, count 2 2006.231.08:11:38.94#ibcon#about to write, iclass 4, count 2 2006.231.08:11:38.94#ibcon#wrote, iclass 4, count 2 2006.231.08:11:38.94#ibcon#about to read 3, iclass 4, count 2 2006.231.08:11:38.96#ibcon#read 3, iclass 4, count 2 2006.231.08:11:38.96#ibcon#about to read 4, iclass 4, count 2 2006.231.08:11:38.96#ibcon#read 4, iclass 4, count 2 2006.231.08:11:38.96#ibcon#about to read 5, iclass 4, count 2 2006.231.08:11:38.96#ibcon#read 5, iclass 4, count 2 2006.231.08:11:38.96#ibcon#about to read 6, iclass 4, count 2 2006.231.08:11:38.96#ibcon#read 6, iclass 4, count 2 2006.231.08:11:38.96#ibcon#end of sib2, iclass 4, count 2 2006.231.08:11:38.96#ibcon#*mode == 0, iclass 4, count 2 2006.231.08:11:38.96#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.231.08:11:38.96#ibcon#[25=AT04-07\r\n] 2006.231.08:11:38.96#ibcon#*before write, iclass 4, count 2 2006.231.08:11:38.96#ibcon#enter sib2, iclass 4, count 2 2006.231.08:11:38.96#ibcon#flushed, iclass 4, count 2 2006.231.08:11:38.96#ibcon#about to write, iclass 4, count 2 2006.231.08:11:38.96#ibcon#wrote, iclass 4, count 2 2006.231.08:11:38.96#ibcon#about to read 3, iclass 4, count 2 2006.231.08:11:38.99#ibcon#read 3, iclass 4, count 2 2006.231.08:11:38.99#ibcon#about to read 4, iclass 4, count 2 2006.231.08:11:38.99#ibcon#read 4, iclass 4, count 2 2006.231.08:11:38.99#ibcon#about to read 5, iclass 4, count 2 2006.231.08:11:38.99#ibcon#read 5, iclass 4, count 2 2006.231.08:11:38.99#ibcon#about to read 6, iclass 4, count 2 2006.231.08:11:38.99#ibcon#read 6, iclass 4, count 2 2006.231.08:11:38.99#ibcon#end of sib2, iclass 4, count 2 2006.231.08:11:38.99#ibcon#*after write, iclass 4, count 2 2006.231.08:11:38.99#ibcon#*before return 0, iclass 4, count 2 2006.231.08:11:38.99#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:11:38.99#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:11:38.99#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.231.08:11:38.99#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:38.99#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:11:39.11#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:11:39.11#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:11:39.11#ibcon#enter wrdev, iclass 4, count 0 2006.231.08:11:39.11#ibcon#first serial, iclass 4, count 0 2006.231.08:11:39.11#ibcon#enter sib2, iclass 4, count 0 2006.231.08:11:39.11#ibcon#flushed, iclass 4, count 0 2006.231.08:11:39.11#ibcon#about to write, iclass 4, count 0 2006.231.08:11:39.11#ibcon#wrote, iclass 4, count 0 2006.231.08:11:39.11#ibcon#about to read 3, iclass 4, count 0 2006.231.08:11:39.13#ibcon#read 3, iclass 4, count 0 2006.231.08:11:39.13#ibcon#about to read 4, iclass 4, count 0 2006.231.08:11:39.13#ibcon#read 4, iclass 4, count 0 2006.231.08:11:39.13#ibcon#about to read 5, iclass 4, count 0 2006.231.08:11:39.13#ibcon#read 5, iclass 4, count 0 2006.231.08:11:39.13#ibcon#about to read 6, iclass 4, count 0 2006.231.08:11:39.13#ibcon#read 6, iclass 4, count 0 2006.231.08:11:39.13#ibcon#end of sib2, iclass 4, count 0 2006.231.08:11:39.13#ibcon#*mode == 0, iclass 4, count 0 2006.231.08:11:39.13#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.08:11:39.13#ibcon#[25=USB\r\n] 2006.231.08:11:39.13#ibcon#*before write, iclass 4, count 0 2006.231.08:11:39.13#ibcon#enter sib2, iclass 4, count 0 2006.231.08:11:39.13#ibcon#flushed, iclass 4, count 0 2006.231.08:11:39.13#ibcon#about to write, iclass 4, count 0 2006.231.08:11:39.13#ibcon#wrote, iclass 4, count 0 2006.231.08:11:39.13#ibcon#about to read 3, iclass 4, count 0 2006.231.08:11:39.16#ibcon#read 3, iclass 4, count 0 2006.231.08:11:39.16#ibcon#about to read 4, iclass 4, count 0 2006.231.08:11:39.16#ibcon#read 4, iclass 4, count 0 2006.231.08:11:39.16#ibcon#about to read 5, iclass 4, count 0 2006.231.08:11:39.16#ibcon#read 5, iclass 4, count 0 2006.231.08:11:39.16#ibcon#about to read 6, iclass 4, count 0 2006.231.08:11:39.16#ibcon#read 6, iclass 4, count 0 2006.231.08:11:39.16#ibcon#end of sib2, iclass 4, count 0 2006.231.08:11:39.16#ibcon#*after write, iclass 4, count 0 2006.231.08:11:39.16#ibcon#*before return 0, iclass 4, count 0 2006.231.08:11:39.16#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:11:39.16#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:11:39.16#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.08:11:39.16#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.08:11:39.16$vc4f8/valo=5,652.99 2006.231.08:11:39.16#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.231.08:11:39.16#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.231.08:11:39.16#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:39.16#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:11:39.16#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:11:39.16#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:11:39.16#ibcon#enter wrdev, iclass 6, count 0 2006.231.08:11:39.16#ibcon#first serial, iclass 6, count 0 2006.231.08:11:39.16#ibcon#enter sib2, iclass 6, count 0 2006.231.08:11:39.16#ibcon#flushed, iclass 6, count 0 2006.231.08:11:39.16#ibcon#about to write, iclass 6, count 0 2006.231.08:11:39.16#ibcon#wrote, iclass 6, count 0 2006.231.08:11:39.16#ibcon#about to read 3, iclass 6, count 0 2006.231.08:11:39.18#ibcon#read 3, iclass 6, count 0 2006.231.08:11:39.18#ibcon#about to read 4, iclass 6, count 0 2006.231.08:11:39.18#ibcon#read 4, iclass 6, count 0 2006.231.08:11:39.18#ibcon#about to read 5, iclass 6, count 0 2006.231.08:11:39.18#ibcon#read 5, iclass 6, count 0 2006.231.08:11:39.18#ibcon#about to read 6, iclass 6, count 0 2006.231.08:11:39.18#ibcon#read 6, iclass 6, count 0 2006.231.08:11:39.18#ibcon#end of sib2, iclass 6, count 0 2006.231.08:11:39.18#ibcon#*mode == 0, iclass 6, count 0 2006.231.08:11:39.18#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.08:11:39.18#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:11:39.18#ibcon#*before write, iclass 6, count 0 2006.231.08:11:39.18#ibcon#enter sib2, iclass 6, count 0 2006.231.08:11:39.18#ibcon#flushed, iclass 6, count 0 2006.231.08:11:39.18#ibcon#about to write, iclass 6, count 0 2006.231.08:11:39.18#ibcon#wrote, iclass 6, count 0 2006.231.08:11:39.18#ibcon#about to read 3, iclass 6, count 0 2006.231.08:11:39.22#ibcon#read 3, iclass 6, count 0 2006.231.08:11:39.22#ibcon#about to read 4, iclass 6, count 0 2006.231.08:11:39.22#ibcon#read 4, iclass 6, count 0 2006.231.08:11:39.22#ibcon#about to read 5, iclass 6, count 0 2006.231.08:11:39.22#ibcon#read 5, iclass 6, count 0 2006.231.08:11:39.22#ibcon#about to read 6, iclass 6, count 0 2006.231.08:11:39.22#ibcon#read 6, iclass 6, count 0 2006.231.08:11:39.22#ibcon#end of sib2, iclass 6, count 0 2006.231.08:11:39.22#ibcon#*after write, iclass 6, count 0 2006.231.08:11:39.22#ibcon#*before return 0, iclass 6, count 0 2006.231.08:11:39.22#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:11:39.22#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:11:39.22#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.08:11:39.22#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.08:11:39.22$vc4f8/va=5,7 2006.231.08:11:39.22#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.231.08:11:39.22#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.231.08:11:39.22#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:39.22#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:11:39.28#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:11:39.28#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:11:39.28#ibcon#enter wrdev, iclass 10, count 2 2006.231.08:11:39.28#ibcon#first serial, iclass 10, count 2 2006.231.08:11:39.28#ibcon#enter sib2, iclass 10, count 2 2006.231.08:11:39.28#ibcon#flushed, iclass 10, count 2 2006.231.08:11:39.28#ibcon#about to write, iclass 10, count 2 2006.231.08:11:39.28#ibcon#wrote, iclass 10, count 2 2006.231.08:11:39.28#ibcon#about to read 3, iclass 10, count 2 2006.231.08:11:39.30#ibcon#read 3, iclass 10, count 2 2006.231.08:11:39.30#ibcon#about to read 4, iclass 10, count 2 2006.231.08:11:39.30#ibcon#read 4, iclass 10, count 2 2006.231.08:11:39.30#ibcon#about to read 5, iclass 10, count 2 2006.231.08:11:39.30#ibcon#read 5, iclass 10, count 2 2006.231.08:11:39.30#ibcon#about to read 6, iclass 10, count 2 2006.231.08:11:39.30#ibcon#read 6, iclass 10, count 2 2006.231.08:11:39.30#ibcon#end of sib2, iclass 10, count 2 2006.231.08:11:39.30#ibcon#*mode == 0, iclass 10, count 2 2006.231.08:11:39.30#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.231.08:11:39.30#ibcon#[25=AT05-07\r\n] 2006.231.08:11:39.30#ibcon#*before write, iclass 10, count 2 2006.231.08:11:39.30#ibcon#enter sib2, iclass 10, count 2 2006.231.08:11:39.30#ibcon#flushed, iclass 10, count 2 2006.231.08:11:39.30#ibcon#about to write, iclass 10, count 2 2006.231.08:11:39.30#ibcon#wrote, iclass 10, count 2 2006.231.08:11:39.30#ibcon#about to read 3, iclass 10, count 2 2006.231.08:11:39.33#ibcon#read 3, iclass 10, count 2 2006.231.08:11:39.33#ibcon#about to read 4, iclass 10, count 2 2006.231.08:11:39.33#ibcon#read 4, iclass 10, count 2 2006.231.08:11:39.33#ibcon#about to read 5, iclass 10, count 2 2006.231.08:11:39.33#ibcon#read 5, iclass 10, count 2 2006.231.08:11:39.33#ibcon#about to read 6, iclass 10, count 2 2006.231.08:11:39.33#ibcon#read 6, iclass 10, count 2 2006.231.08:11:39.33#ibcon#end of sib2, iclass 10, count 2 2006.231.08:11:39.33#ibcon#*after write, iclass 10, count 2 2006.231.08:11:39.33#ibcon#*before return 0, iclass 10, count 2 2006.231.08:11:39.33#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:11:39.33#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:11:39.33#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.231.08:11:39.33#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:39.33#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:11:39.45#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:11:39.45#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:11:39.45#ibcon#enter wrdev, iclass 10, count 0 2006.231.08:11:39.45#ibcon#first serial, iclass 10, count 0 2006.231.08:11:39.45#ibcon#enter sib2, iclass 10, count 0 2006.231.08:11:39.45#ibcon#flushed, iclass 10, count 0 2006.231.08:11:39.45#ibcon#about to write, iclass 10, count 0 2006.231.08:11:39.45#ibcon#wrote, iclass 10, count 0 2006.231.08:11:39.45#ibcon#about to read 3, iclass 10, count 0 2006.231.08:11:39.47#ibcon#read 3, iclass 10, count 0 2006.231.08:11:39.47#ibcon#about to read 4, iclass 10, count 0 2006.231.08:11:39.47#ibcon#read 4, iclass 10, count 0 2006.231.08:11:39.47#ibcon#about to read 5, iclass 10, count 0 2006.231.08:11:39.47#ibcon#read 5, iclass 10, count 0 2006.231.08:11:39.47#ibcon#about to read 6, iclass 10, count 0 2006.231.08:11:39.47#ibcon#read 6, iclass 10, count 0 2006.231.08:11:39.47#ibcon#end of sib2, iclass 10, count 0 2006.231.08:11:39.47#ibcon#*mode == 0, iclass 10, count 0 2006.231.08:11:39.47#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.08:11:39.47#ibcon#[25=USB\r\n] 2006.231.08:11:39.47#ibcon#*before write, iclass 10, count 0 2006.231.08:11:39.47#ibcon#enter sib2, iclass 10, count 0 2006.231.08:11:39.47#ibcon#flushed, iclass 10, count 0 2006.231.08:11:39.47#ibcon#about to write, iclass 10, count 0 2006.231.08:11:39.48#ibcon#wrote, iclass 10, count 0 2006.231.08:11:39.48#ibcon#about to read 3, iclass 10, count 0 2006.231.08:11:39.50#ibcon#read 3, iclass 10, count 0 2006.231.08:11:39.50#ibcon#about to read 4, iclass 10, count 0 2006.231.08:11:39.50#ibcon#read 4, iclass 10, count 0 2006.231.08:11:39.50#ibcon#about to read 5, iclass 10, count 0 2006.231.08:11:39.50#ibcon#read 5, iclass 10, count 0 2006.231.08:11:39.50#ibcon#about to read 6, iclass 10, count 0 2006.231.08:11:39.50#ibcon#read 6, iclass 10, count 0 2006.231.08:11:39.50#ibcon#end of sib2, iclass 10, count 0 2006.231.08:11:39.50#ibcon#*after write, iclass 10, count 0 2006.231.08:11:39.50#ibcon#*before return 0, iclass 10, count 0 2006.231.08:11:39.50#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:11:39.50#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:11:39.50#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.08:11:39.50#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.08:11:39.50$vc4f8/valo=6,772.99 2006.231.08:11:39.50#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.08:11:39.50#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.08:11:39.50#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:39.50#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:11:39.50#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:11:39.50#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:11:39.50#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:11:39.50#ibcon#first serial, iclass 12, count 0 2006.231.08:11:39.50#ibcon#enter sib2, iclass 12, count 0 2006.231.08:11:39.50#ibcon#flushed, iclass 12, count 0 2006.231.08:11:39.50#ibcon#about to write, iclass 12, count 0 2006.231.08:11:39.50#ibcon#wrote, iclass 12, count 0 2006.231.08:11:39.50#ibcon#about to read 3, iclass 12, count 0 2006.231.08:11:39.52#ibcon#read 3, iclass 12, count 0 2006.231.08:11:39.52#ibcon#about to read 4, iclass 12, count 0 2006.231.08:11:39.52#ibcon#read 4, iclass 12, count 0 2006.231.08:11:39.52#ibcon#about to read 5, iclass 12, count 0 2006.231.08:11:39.52#ibcon#read 5, iclass 12, count 0 2006.231.08:11:39.52#ibcon#about to read 6, iclass 12, count 0 2006.231.08:11:39.52#ibcon#read 6, iclass 12, count 0 2006.231.08:11:39.52#ibcon#end of sib2, iclass 12, count 0 2006.231.08:11:39.52#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:11:39.52#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:11:39.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:11:39.52#ibcon#*before write, iclass 12, count 0 2006.231.08:11:39.52#ibcon#enter sib2, iclass 12, count 0 2006.231.08:11:39.52#ibcon#flushed, iclass 12, count 0 2006.231.08:11:39.52#ibcon#about to write, iclass 12, count 0 2006.231.08:11:39.52#ibcon#wrote, iclass 12, count 0 2006.231.08:11:39.52#ibcon#about to read 3, iclass 12, count 0 2006.231.08:11:39.56#ibcon#read 3, iclass 12, count 0 2006.231.08:11:39.56#ibcon#about to read 4, iclass 12, count 0 2006.231.08:11:39.56#ibcon#read 4, iclass 12, count 0 2006.231.08:11:39.56#ibcon#about to read 5, iclass 12, count 0 2006.231.08:11:39.56#ibcon#read 5, iclass 12, count 0 2006.231.08:11:39.56#ibcon#about to read 6, iclass 12, count 0 2006.231.08:11:39.56#ibcon#read 6, iclass 12, count 0 2006.231.08:11:39.56#ibcon#end of sib2, iclass 12, count 0 2006.231.08:11:39.56#ibcon#*after write, iclass 12, count 0 2006.231.08:11:39.56#ibcon#*before return 0, iclass 12, count 0 2006.231.08:11:39.56#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:11:39.56#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:11:39.56#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:11:39.56#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:11:39.56$vc4f8/va=6,6 2006.231.08:11:39.56#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.08:11:39.56#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.08:11:39.56#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:39.56#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:11:39.62#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:11:39.62#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:11:39.62#ibcon#enter wrdev, iclass 14, count 2 2006.231.08:11:39.62#ibcon#first serial, iclass 14, count 2 2006.231.08:11:39.62#ibcon#enter sib2, iclass 14, count 2 2006.231.08:11:39.62#ibcon#flushed, iclass 14, count 2 2006.231.08:11:39.62#ibcon#about to write, iclass 14, count 2 2006.231.08:11:39.62#ibcon#wrote, iclass 14, count 2 2006.231.08:11:39.62#ibcon#about to read 3, iclass 14, count 2 2006.231.08:11:39.64#ibcon#read 3, iclass 14, count 2 2006.231.08:11:39.64#ibcon#about to read 4, iclass 14, count 2 2006.231.08:11:39.64#ibcon#read 4, iclass 14, count 2 2006.231.08:11:39.64#ibcon#about to read 5, iclass 14, count 2 2006.231.08:11:39.64#ibcon#read 5, iclass 14, count 2 2006.231.08:11:39.64#ibcon#about to read 6, iclass 14, count 2 2006.231.08:11:39.64#ibcon#read 6, iclass 14, count 2 2006.231.08:11:39.64#ibcon#end of sib2, iclass 14, count 2 2006.231.08:11:39.64#ibcon#*mode == 0, iclass 14, count 2 2006.231.08:11:39.64#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.08:11:39.64#ibcon#[25=AT06-06\r\n] 2006.231.08:11:39.64#ibcon#*before write, iclass 14, count 2 2006.231.08:11:39.64#ibcon#enter sib2, iclass 14, count 2 2006.231.08:11:39.64#ibcon#flushed, iclass 14, count 2 2006.231.08:11:39.64#ibcon#about to write, iclass 14, count 2 2006.231.08:11:39.64#ibcon#wrote, iclass 14, count 2 2006.231.08:11:39.64#ibcon#about to read 3, iclass 14, count 2 2006.231.08:11:39.67#ibcon#read 3, iclass 14, count 2 2006.231.08:11:39.67#ibcon#about to read 4, iclass 14, count 2 2006.231.08:11:39.67#ibcon#read 4, iclass 14, count 2 2006.231.08:11:39.67#ibcon#about to read 5, iclass 14, count 2 2006.231.08:11:39.67#ibcon#read 5, iclass 14, count 2 2006.231.08:11:39.67#ibcon#about to read 6, iclass 14, count 2 2006.231.08:11:39.67#ibcon#read 6, iclass 14, count 2 2006.231.08:11:39.67#ibcon#end of sib2, iclass 14, count 2 2006.231.08:11:39.67#ibcon#*after write, iclass 14, count 2 2006.231.08:11:39.67#ibcon#*before return 0, iclass 14, count 2 2006.231.08:11:39.67#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:11:39.67#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:11:39.67#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.08:11:39.67#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:39.67#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:11:39.79#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:11:39.79#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:11:39.79#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:11:39.79#ibcon#first serial, iclass 14, count 0 2006.231.08:11:39.79#ibcon#enter sib2, iclass 14, count 0 2006.231.08:11:39.79#ibcon#flushed, iclass 14, count 0 2006.231.08:11:39.79#ibcon#about to write, iclass 14, count 0 2006.231.08:11:39.79#ibcon#wrote, iclass 14, count 0 2006.231.08:11:39.79#ibcon#about to read 3, iclass 14, count 0 2006.231.08:11:39.81#ibcon#read 3, iclass 14, count 0 2006.231.08:11:39.81#ibcon#about to read 4, iclass 14, count 0 2006.231.08:11:39.81#ibcon#read 4, iclass 14, count 0 2006.231.08:11:39.81#ibcon#about to read 5, iclass 14, count 0 2006.231.08:11:39.81#ibcon#read 5, iclass 14, count 0 2006.231.08:11:39.81#ibcon#about to read 6, iclass 14, count 0 2006.231.08:11:39.81#ibcon#read 6, iclass 14, count 0 2006.231.08:11:39.81#ibcon#end of sib2, iclass 14, count 0 2006.231.08:11:39.81#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:11:39.81#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:11:39.81#ibcon#[25=USB\r\n] 2006.231.08:11:39.81#ibcon#*before write, iclass 14, count 0 2006.231.08:11:39.81#ibcon#enter sib2, iclass 14, count 0 2006.231.08:11:39.81#ibcon#flushed, iclass 14, count 0 2006.231.08:11:39.81#ibcon#about to write, iclass 14, count 0 2006.231.08:11:39.81#ibcon#wrote, iclass 14, count 0 2006.231.08:11:39.81#ibcon#about to read 3, iclass 14, count 0 2006.231.08:11:39.84#ibcon#read 3, iclass 14, count 0 2006.231.08:11:39.84#ibcon#about to read 4, iclass 14, count 0 2006.231.08:11:39.84#ibcon#read 4, iclass 14, count 0 2006.231.08:11:39.84#ibcon#about to read 5, iclass 14, count 0 2006.231.08:11:39.84#ibcon#read 5, iclass 14, count 0 2006.231.08:11:39.84#ibcon#about to read 6, iclass 14, count 0 2006.231.08:11:39.84#ibcon#read 6, iclass 14, count 0 2006.231.08:11:39.84#ibcon#end of sib2, iclass 14, count 0 2006.231.08:11:39.84#ibcon#*after write, iclass 14, count 0 2006.231.08:11:39.84#ibcon#*before return 0, iclass 14, count 0 2006.231.08:11:39.84#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:11:39.84#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:11:39.84#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:11:39.84#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:11:39.84$vc4f8/valo=7,832.99 2006.231.08:11:39.84#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.08:11:39.84#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.08:11:39.84#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:39.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:11:39.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:11:39.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:11:39.84#ibcon#enter wrdev, iclass 16, count 0 2006.231.08:11:39.84#ibcon#first serial, iclass 16, count 0 2006.231.08:11:39.84#ibcon#enter sib2, iclass 16, count 0 2006.231.08:11:39.84#ibcon#flushed, iclass 16, count 0 2006.231.08:11:39.84#ibcon#about to write, iclass 16, count 0 2006.231.08:11:39.84#ibcon#wrote, iclass 16, count 0 2006.231.08:11:39.84#ibcon#about to read 3, iclass 16, count 0 2006.231.08:11:39.86#ibcon#read 3, iclass 16, count 0 2006.231.08:11:39.86#ibcon#about to read 4, iclass 16, count 0 2006.231.08:11:39.86#ibcon#read 4, iclass 16, count 0 2006.231.08:11:39.86#ibcon#about to read 5, iclass 16, count 0 2006.231.08:11:39.86#ibcon#read 5, iclass 16, count 0 2006.231.08:11:39.86#ibcon#about to read 6, iclass 16, count 0 2006.231.08:11:39.86#ibcon#read 6, iclass 16, count 0 2006.231.08:11:39.86#ibcon#end of sib2, iclass 16, count 0 2006.231.08:11:39.86#ibcon#*mode == 0, iclass 16, count 0 2006.231.08:11:39.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.08:11:39.86#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:11:39.86#ibcon#*before write, iclass 16, count 0 2006.231.08:11:39.86#ibcon#enter sib2, iclass 16, count 0 2006.231.08:11:39.86#ibcon#flushed, iclass 16, count 0 2006.231.08:11:39.86#ibcon#about to write, iclass 16, count 0 2006.231.08:11:39.86#ibcon#wrote, iclass 16, count 0 2006.231.08:11:39.86#ibcon#about to read 3, iclass 16, count 0 2006.231.08:11:39.90#ibcon#read 3, iclass 16, count 0 2006.231.08:11:39.90#ibcon#about to read 4, iclass 16, count 0 2006.231.08:11:39.90#ibcon#read 4, iclass 16, count 0 2006.231.08:11:39.90#ibcon#about to read 5, iclass 16, count 0 2006.231.08:11:39.90#ibcon#read 5, iclass 16, count 0 2006.231.08:11:39.90#ibcon#about to read 6, iclass 16, count 0 2006.231.08:11:39.90#ibcon#read 6, iclass 16, count 0 2006.231.08:11:39.90#ibcon#end of sib2, iclass 16, count 0 2006.231.08:11:39.90#ibcon#*after write, iclass 16, count 0 2006.231.08:11:39.90#ibcon#*before return 0, iclass 16, count 0 2006.231.08:11:39.90#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:11:39.90#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:11:39.90#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.08:11:39.90#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.08:11:39.90$vc4f8/va=7,6 2006.231.08:11:39.90#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.231.08:11:39.90#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.231.08:11:39.90#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:39.90#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:11:39.96#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:11:39.96#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:11:39.96#ibcon#enter wrdev, iclass 18, count 2 2006.231.08:11:39.96#ibcon#first serial, iclass 18, count 2 2006.231.08:11:39.96#ibcon#enter sib2, iclass 18, count 2 2006.231.08:11:39.96#ibcon#flushed, iclass 18, count 2 2006.231.08:11:39.96#ibcon#about to write, iclass 18, count 2 2006.231.08:11:39.96#ibcon#wrote, iclass 18, count 2 2006.231.08:11:39.96#ibcon#about to read 3, iclass 18, count 2 2006.231.08:11:39.98#ibcon#read 3, iclass 18, count 2 2006.231.08:11:39.98#ibcon#about to read 4, iclass 18, count 2 2006.231.08:11:39.98#ibcon#read 4, iclass 18, count 2 2006.231.08:11:39.98#ibcon#about to read 5, iclass 18, count 2 2006.231.08:11:39.98#ibcon#read 5, iclass 18, count 2 2006.231.08:11:39.98#ibcon#about to read 6, iclass 18, count 2 2006.231.08:11:39.98#ibcon#read 6, iclass 18, count 2 2006.231.08:11:39.98#ibcon#end of sib2, iclass 18, count 2 2006.231.08:11:39.98#ibcon#*mode == 0, iclass 18, count 2 2006.231.08:11:39.98#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.231.08:11:39.98#ibcon#[25=AT07-06\r\n] 2006.231.08:11:39.98#ibcon#*before write, iclass 18, count 2 2006.231.08:11:39.98#ibcon#enter sib2, iclass 18, count 2 2006.231.08:11:39.98#ibcon#flushed, iclass 18, count 2 2006.231.08:11:39.98#ibcon#about to write, iclass 18, count 2 2006.231.08:11:39.98#ibcon#wrote, iclass 18, count 2 2006.231.08:11:39.98#ibcon#about to read 3, iclass 18, count 2 2006.231.08:11:40.01#ibcon#read 3, iclass 18, count 2 2006.231.08:11:40.01#ibcon#about to read 4, iclass 18, count 2 2006.231.08:11:40.01#ibcon#read 4, iclass 18, count 2 2006.231.08:11:40.01#ibcon#about to read 5, iclass 18, count 2 2006.231.08:11:40.01#ibcon#read 5, iclass 18, count 2 2006.231.08:11:40.01#ibcon#about to read 6, iclass 18, count 2 2006.231.08:11:40.01#ibcon#read 6, iclass 18, count 2 2006.231.08:11:40.01#ibcon#end of sib2, iclass 18, count 2 2006.231.08:11:40.01#ibcon#*after write, iclass 18, count 2 2006.231.08:11:40.01#ibcon#*before return 0, iclass 18, count 2 2006.231.08:11:40.01#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:11:40.01#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:11:40.01#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.231.08:11:40.01#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:40.01#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:11:40.13#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:11:40.13#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:11:40.13#ibcon#enter wrdev, iclass 18, count 0 2006.231.08:11:40.13#ibcon#first serial, iclass 18, count 0 2006.231.08:11:40.13#ibcon#enter sib2, iclass 18, count 0 2006.231.08:11:40.13#ibcon#flushed, iclass 18, count 0 2006.231.08:11:40.13#ibcon#about to write, iclass 18, count 0 2006.231.08:11:40.13#ibcon#wrote, iclass 18, count 0 2006.231.08:11:40.13#ibcon#about to read 3, iclass 18, count 0 2006.231.08:11:40.15#ibcon#read 3, iclass 18, count 0 2006.231.08:11:40.15#ibcon#about to read 4, iclass 18, count 0 2006.231.08:11:40.15#ibcon#read 4, iclass 18, count 0 2006.231.08:11:40.15#ibcon#about to read 5, iclass 18, count 0 2006.231.08:11:40.15#ibcon#read 5, iclass 18, count 0 2006.231.08:11:40.15#ibcon#about to read 6, iclass 18, count 0 2006.231.08:11:40.15#ibcon#read 6, iclass 18, count 0 2006.231.08:11:40.15#ibcon#end of sib2, iclass 18, count 0 2006.231.08:11:40.15#ibcon#*mode == 0, iclass 18, count 0 2006.231.08:11:40.15#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.08:11:40.15#ibcon#[25=USB\r\n] 2006.231.08:11:40.15#ibcon#*before write, iclass 18, count 0 2006.231.08:11:40.15#ibcon#enter sib2, iclass 18, count 0 2006.231.08:11:40.15#ibcon#flushed, iclass 18, count 0 2006.231.08:11:40.15#ibcon#about to write, iclass 18, count 0 2006.231.08:11:40.15#ibcon#wrote, iclass 18, count 0 2006.231.08:11:40.15#ibcon#about to read 3, iclass 18, count 0 2006.231.08:11:40.18#ibcon#read 3, iclass 18, count 0 2006.231.08:11:40.18#ibcon#about to read 4, iclass 18, count 0 2006.231.08:11:40.18#ibcon#read 4, iclass 18, count 0 2006.231.08:11:40.18#ibcon#about to read 5, iclass 18, count 0 2006.231.08:11:40.18#ibcon#read 5, iclass 18, count 0 2006.231.08:11:40.18#ibcon#about to read 6, iclass 18, count 0 2006.231.08:11:40.18#ibcon#read 6, iclass 18, count 0 2006.231.08:11:40.18#ibcon#end of sib2, iclass 18, count 0 2006.231.08:11:40.18#ibcon#*after write, iclass 18, count 0 2006.231.08:11:40.18#ibcon#*before return 0, iclass 18, count 0 2006.231.08:11:40.18#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:11:40.18#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:11:40.18#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.08:11:40.18#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.08:11:40.18$vc4f8/valo=8,852.99 2006.231.08:11:40.18#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.231.08:11:40.18#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.231.08:11:40.18#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:40.18#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:11:40.18#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:11:40.18#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:11:40.18#ibcon#enter wrdev, iclass 20, count 0 2006.231.08:11:40.18#ibcon#first serial, iclass 20, count 0 2006.231.08:11:40.18#ibcon#enter sib2, iclass 20, count 0 2006.231.08:11:40.18#ibcon#flushed, iclass 20, count 0 2006.231.08:11:40.18#ibcon#about to write, iclass 20, count 0 2006.231.08:11:40.18#ibcon#wrote, iclass 20, count 0 2006.231.08:11:40.18#ibcon#about to read 3, iclass 20, count 0 2006.231.08:11:40.20#ibcon#read 3, iclass 20, count 0 2006.231.08:11:40.20#ibcon#about to read 4, iclass 20, count 0 2006.231.08:11:40.20#ibcon#read 4, iclass 20, count 0 2006.231.08:11:40.20#ibcon#about to read 5, iclass 20, count 0 2006.231.08:11:40.20#ibcon#read 5, iclass 20, count 0 2006.231.08:11:40.20#ibcon#about to read 6, iclass 20, count 0 2006.231.08:11:40.20#ibcon#read 6, iclass 20, count 0 2006.231.08:11:40.20#ibcon#end of sib2, iclass 20, count 0 2006.231.08:11:40.20#ibcon#*mode == 0, iclass 20, count 0 2006.231.08:11:40.20#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.08:11:40.20#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:11:40.20#ibcon#*before write, iclass 20, count 0 2006.231.08:11:40.20#ibcon#enter sib2, iclass 20, count 0 2006.231.08:11:40.20#ibcon#flushed, iclass 20, count 0 2006.231.08:11:40.20#ibcon#about to write, iclass 20, count 0 2006.231.08:11:40.20#ibcon#wrote, iclass 20, count 0 2006.231.08:11:40.20#ibcon#about to read 3, iclass 20, count 0 2006.231.08:11:40.24#ibcon#read 3, iclass 20, count 0 2006.231.08:11:40.24#ibcon#about to read 4, iclass 20, count 0 2006.231.08:11:40.24#ibcon#read 4, iclass 20, count 0 2006.231.08:11:40.24#ibcon#about to read 5, iclass 20, count 0 2006.231.08:11:40.24#ibcon#read 5, iclass 20, count 0 2006.231.08:11:40.24#ibcon#about to read 6, iclass 20, count 0 2006.231.08:11:40.24#ibcon#read 6, iclass 20, count 0 2006.231.08:11:40.24#ibcon#end of sib2, iclass 20, count 0 2006.231.08:11:40.24#ibcon#*after write, iclass 20, count 0 2006.231.08:11:40.24#ibcon#*before return 0, iclass 20, count 0 2006.231.08:11:40.24#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:11:40.24#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:11:40.24#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.08:11:40.24#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.08:11:40.24$vc4f8/va=8,6 2006.231.08:11:40.24#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.231.08:11:40.24#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.231.08:11:40.24#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:40.24#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:11:40.30#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:11:40.30#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:11:40.30#ibcon#enter wrdev, iclass 22, count 2 2006.231.08:11:40.30#ibcon#first serial, iclass 22, count 2 2006.231.08:11:40.30#ibcon#enter sib2, iclass 22, count 2 2006.231.08:11:40.30#ibcon#flushed, iclass 22, count 2 2006.231.08:11:40.30#ibcon#about to write, iclass 22, count 2 2006.231.08:11:40.30#ibcon#wrote, iclass 22, count 2 2006.231.08:11:40.30#ibcon#about to read 3, iclass 22, count 2 2006.231.08:11:40.33#ibcon#read 3, iclass 22, count 2 2006.231.08:11:40.33#ibcon#about to read 4, iclass 22, count 2 2006.231.08:11:40.33#ibcon#read 4, iclass 22, count 2 2006.231.08:11:40.33#ibcon#about to read 5, iclass 22, count 2 2006.231.08:11:40.33#ibcon#read 5, iclass 22, count 2 2006.231.08:11:40.33#ibcon#about to read 6, iclass 22, count 2 2006.231.08:11:40.33#ibcon#read 6, iclass 22, count 2 2006.231.08:11:40.33#ibcon#end of sib2, iclass 22, count 2 2006.231.08:11:40.33#ibcon#*mode == 0, iclass 22, count 2 2006.231.08:11:40.33#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.231.08:11:40.33#ibcon#[25=AT08-06\r\n] 2006.231.08:11:40.33#ibcon#*before write, iclass 22, count 2 2006.231.08:11:40.33#ibcon#enter sib2, iclass 22, count 2 2006.231.08:11:40.33#ibcon#flushed, iclass 22, count 2 2006.231.08:11:40.33#ibcon#about to write, iclass 22, count 2 2006.231.08:11:40.33#ibcon#wrote, iclass 22, count 2 2006.231.08:11:40.33#ibcon#about to read 3, iclass 22, count 2 2006.231.08:11:40.36#ibcon#read 3, iclass 22, count 2 2006.231.08:11:40.36#ibcon#about to read 4, iclass 22, count 2 2006.231.08:11:40.36#ibcon#read 4, iclass 22, count 2 2006.231.08:11:40.36#ibcon#about to read 5, iclass 22, count 2 2006.231.08:11:40.36#ibcon#read 5, iclass 22, count 2 2006.231.08:11:40.36#ibcon#about to read 6, iclass 22, count 2 2006.231.08:11:40.36#ibcon#read 6, iclass 22, count 2 2006.231.08:11:40.36#ibcon#end of sib2, iclass 22, count 2 2006.231.08:11:40.36#ibcon#*after write, iclass 22, count 2 2006.231.08:11:40.36#ibcon#*before return 0, iclass 22, count 2 2006.231.08:11:40.36#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:11:40.36#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:11:40.36#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.231.08:11:40.36#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:40.36#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:11:40.48#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:11:40.48#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:11:40.48#ibcon#enter wrdev, iclass 22, count 0 2006.231.08:11:40.48#ibcon#first serial, iclass 22, count 0 2006.231.08:11:40.48#ibcon#enter sib2, iclass 22, count 0 2006.231.08:11:40.48#ibcon#flushed, iclass 22, count 0 2006.231.08:11:40.48#ibcon#about to write, iclass 22, count 0 2006.231.08:11:40.48#ibcon#wrote, iclass 22, count 0 2006.231.08:11:40.48#ibcon#about to read 3, iclass 22, count 0 2006.231.08:11:40.50#ibcon#read 3, iclass 22, count 0 2006.231.08:11:40.50#ibcon#about to read 4, iclass 22, count 0 2006.231.08:11:40.50#ibcon#read 4, iclass 22, count 0 2006.231.08:11:40.50#ibcon#about to read 5, iclass 22, count 0 2006.231.08:11:40.50#ibcon#read 5, iclass 22, count 0 2006.231.08:11:40.50#ibcon#about to read 6, iclass 22, count 0 2006.231.08:11:40.50#ibcon#read 6, iclass 22, count 0 2006.231.08:11:40.50#ibcon#end of sib2, iclass 22, count 0 2006.231.08:11:40.50#ibcon#*mode == 0, iclass 22, count 0 2006.231.08:11:40.50#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.08:11:40.50#ibcon#[25=USB\r\n] 2006.231.08:11:40.50#ibcon#*before write, iclass 22, count 0 2006.231.08:11:40.50#ibcon#enter sib2, iclass 22, count 0 2006.231.08:11:40.50#ibcon#flushed, iclass 22, count 0 2006.231.08:11:40.50#ibcon#about to write, iclass 22, count 0 2006.231.08:11:40.50#ibcon#wrote, iclass 22, count 0 2006.231.08:11:40.50#ibcon#about to read 3, iclass 22, count 0 2006.231.08:11:40.53#ibcon#read 3, iclass 22, count 0 2006.231.08:11:40.53#ibcon#about to read 4, iclass 22, count 0 2006.231.08:11:40.53#ibcon#read 4, iclass 22, count 0 2006.231.08:11:40.53#ibcon#about to read 5, iclass 22, count 0 2006.231.08:11:40.53#ibcon#read 5, iclass 22, count 0 2006.231.08:11:40.53#ibcon#about to read 6, iclass 22, count 0 2006.231.08:11:40.53#ibcon#read 6, iclass 22, count 0 2006.231.08:11:40.53#ibcon#end of sib2, iclass 22, count 0 2006.231.08:11:40.53#ibcon#*after write, iclass 22, count 0 2006.231.08:11:40.53#ibcon#*before return 0, iclass 22, count 0 2006.231.08:11:40.53#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:11:40.53#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:11:40.53#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.08:11:40.53#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.08:11:40.53$vc4f8/vblo=1,632.99 2006.231.08:11:40.53#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.231.08:11:40.53#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.231.08:11:40.53#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:40.53#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:11:40.53#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:11:40.53#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:11:40.53#ibcon#enter wrdev, iclass 24, count 0 2006.231.08:11:40.53#ibcon#first serial, iclass 24, count 0 2006.231.08:11:40.53#ibcon#enter sib2, iclass 24, count 0 2006.231.08:11:40.53#ibcon#flushed, iclass 24, count 0 2006.231.08:11:40.53#ibcon#about to write, iclass 24, count 0 2006.231.08:11:40.53#ibcon#wrote, iclass 24, count 0 2006.231.08:11:40.53#ibcon#about to read 3, iclass 24, count 0 2006.231.08:11:40.55#ibcon#read 3, iclass 24, count 0 2006.231.08:11:40.55#ibcon#about to read 4, iclass 24, count 0 2006.231.08:11:40.55#ibcon#read 4, iclass 24, count 0 2006.231.08:11:40.55#ibcon#about to read 5, iclass 24, count 0 2006.231.08:11:40.55#ibcon#read 5, iclass 24, count 0 2006.231.08:11:40.55#ibcon#about to read 6, iclass 24, count 0 2006.231.08:11:40.55#ibcon#read 6, iclass 24, count 0 2006.231.08:11:40.55#ibcon#end of sib2, iclass 24, count 0 2006.231.08:11:40.55#ibcon#*mode == 0, iclass 24, count 0 2006.231.08:11:40.55#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.08:11:40.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:11:40.55#ibcon#*before write, iclass 24, count 0 2006.231.08:11:40.55#ibcon#enter sib2, iclass 24, count 0 2006.231.08:11:40.55#ibcon#flushed, iclass 24, count 0 2006.231.08:11:40.55#ibcon#about to write, iclass 24, count 0 2006.231.08:11:40.55#ibcon#wrote, iclass 24, count 0 2006.231.08:11:40.55#ibcon#about to read 3, iclass 24, count 0 2006.231.08:11:40.59#ibcon#read 3, iclass 24, count 0 2006.231.08:11:40.59#ibcon#about to read 4, iclass 24, count 0 2006.231.08:11:40.59#ibcon#read 4, iclass 24, count 0 2006.231.08:11:40.59#ibcon#about to read 5, iclass 24, count 0 2006.231.08:11:40.59#ibcon#read 5, iclass 24, count 0 2006.231.08:11:40.59#ibcon#about to read 6, iclass 24, count 0 2006.231.08:11:40.59#ibcon#read 6, iclass 24, count 0 2006.231.08:11:40.59#ibcon#end of sib2, iclass 24, count 0 2006.231.08:11:40.59#ibcon#*after write, iclass 24, count 0 2006.231.08:11:40.59#ibcon#*before return 0, iclass 24, count 0 2006.231.08:11:40.59#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:11:40.59#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:11:40.59#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.08:11:40.59#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.08:11:40.59$vc4f8/vb=1,4 2006.231.08:11:40.59#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.231.08:11:40.59#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.231.08:11:40.59#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:40.59#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:11:40.59#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:11:40.59#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:11:40.59#ibcon#enter wrdev, iclass 26, count 2 2006.231.08:11:40.59#ibcon#first serial, iclass 26, count 2 2006.231.08:11:40.59#ibcon#enter sib2, iclass 26, count 2 2006.231.08:11:40.59#ibcon#flushed, iclass 26, count 2 2006.231.08:11:40.59#ibcon#about to write, iclass 26, count 2 2006.231.08:11:40.59#ibcon#wrote, iclass 26, count 2 2006.231.08:11:40.59#ibcon#about to read 3, iclass 26, count 2 2006.231.08:11:40.61#ibcon#read 3, iclass 26, count 2 2006.231.08:11:40.61#ibcon#about to read 4, iclass 26, count 2 2006.231.08:11:40.61#ibcon#read 4, iclass 26, count 2 2006.231.08:11:40.61#ibcon#about to read 5, iclass 26, count 2 2006.231.08:11:40.61#ibcon#read 5, iclass 26, count 2 2006.231.08:11:40.61#ibcon#about to read 6, iclass 26, count 2 2006.231.08:11:40.61#ibcon#read 6, iclass 26, count 2 2006.231.08:11:40.61#ibcon#end of sib2, iclass 26, count 2 2006.231.08:11:40.61#ibcon#*mode == 0, iclass 26, count 2 2006.231.08:11:40.61#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.231.08:11:40.61#ibcon#[27=AT01-04\r\n] 2006.231.08:11:40.61#ibcon#*before write, iclass 26, count 2 2006.231.08:11:40.61#ibcon#enter sib2, iclass 26, count 2 2006.231.08:11:40.61#ibcon#flushed, iclass 26, count 2 2006.231.08:11:40.61#ibcon#about to write, iclass 26, count 2 2006.231.08:11:40.61#ibcon#wrote, iclass 26, count 2 2006.231.08:11:40.61#ibcon#about to read 3, iclass 26, count 2 2006.231.08:11:40.64#ibcon#read 3, iclass 26, count 2 2006.231.08:11:40.64#ibcon#about to read 4, iclass 26, count 2 2006.231.08:11:40.64#ibcon#read 4, iclass 26, count 2 2006.231.08:11:40.64#ibcon#about to read 5, iclass 26, count 2 2006.231.08:11:40.64#ibcon#read 5, iclass 26, count 2 2006.231.08:11:40.64#ibcon#about to read 6, iclass 26, count 2 2006.231.08:11:40.64#ibcon#read 6, iclass 26, count 2 2006.231.08:11:40.64#ibcon#end of sib2, iclass 26, count 2 2006.231.08:11:40.64#ibcon#*after write, iclass 26, count 2 2006.231.08:11:40.64#ibcon#*before return 0, iclass 26, count 2 2006.231.08:11:40.64#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:11:40.64#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:11:40.64#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.231.08:11:40.64#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:40.64#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:11:40.76#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:11:40.76#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:11:40.76#ibcon#enter wrdev, iclass 26, count 0 2006.231.08:11:40.76#ibcon#first serial, iclass 26, count 0 2006.231.08:11:40.76#ibcon#enter sib2, iclass 26, count 0 2006.231.08:11:40.76#ibcon#flushed, iclass 26, count 0 2006.231.08:11:40.76#ibcon#about to write, iclass 26, count 0 2006.231.08:11:40.76#ibcon#wrote, iclass 26, count 0 2006.231.08:11:40.76#ibcon#about to read 3, iclass 26, count 0 2006.231.08:11:40.78#ibcon#read 3, iclass 26, count 0 2006.231.08:11:40.78#ibcon#about to read 4, iclass 26, count 0 2006.231.08:11:40.78#ibcon#read 4, iclass 26, count 0 2006.231.08:11:40.78#ibcon#about to read 5, iclass 26, count 0 2006.231.08:11:40.78#ibcon#read 5, iclass 26, count 0 2006.231.08:11:40.78#ibcon#about to read 6, iclass 26, count 0 2006.231.08:11:40.78#ibcon#read 6, iclass 26, count 0 2006.231.08:11:40.78#ibcon#end of sib2, iclass 26, count 0 2006.231.08:11:40.78#ibcon#*mode == 0, iclass 26, count 0 2006.231.08:11:40.78#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.08:11:40.78#ibcon#[27=USB\r\n] 2006.231.08:11:40.78#ibcon#*before write, iclass 26, count 0 2006.231.08:11:40.78#ibcon#enter sib2, iclass 26, count 0 2006.231.08:11:40.78#ibcon#flushed, iclass 26, count 0 2006.231.08:11:40.78#ibcon#about to write, iclass 26, count 0 2006.231.08:11:40.78#ibcon#wrote, iclass 26, count 0 2006.231.08:11:40.78#ibcon#about to read 3, iclass 26, count 0 2006.231.08:11:40.81#ibcon#read 3, iclass 26, count 0 2006.231.08:11:40.81#ibcon#about to read 4, iclass 26, count 0 2006.231.08:11:40.81#ibcon#read 4, iclass 26, count 0 2006.231.08:11:40.81#ibcon#about to read 5, iclass 26, count 0 2006.231.08:11:40.81#ibcon#read 5, iclass 26, count 0 2006.231.08:11:40.81#ibcon#about to read 6, iclass 26, count 0 2006.231.08:11:40.81#ibcon#read 6, iclass 26, count 0 2006.231.08:11:40.81#ibcon#end of sib2, iclass 26, count 0 2006.231.08:11:40.81#ibcon#*after write, iclass 26, count 0 2006.231.08:11:40.81#ibcon#*before return 0, iclass 26, count 0 2006.231.08:11:40.81#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:11:40.81#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:11:40.81#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.08:11:40.81#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.08:11:40.81$vc4f8/vblo=2,640.99 2006.231.08:11:40.81#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.231.08:11:40.81#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.231.08:11:40.81#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:40.81#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:11:40.81#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:11:40.81#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:11:40.81#ibcon#enter wrdev, iclass 28, count 0 2006.231.08:11:40.81#ibcon#first serial, iclass 28, count 0 2006.231.08:11:40.81#ibcon#enter sib2, iclass 28, count 0 2006.231.08:11:40.81#ibcon#flushed, iclass 28, count 0 2006.231.08:11:40.81#ibcon#about to write, iclass 28, count 0 2006.231.08:11:40.81#ibcon#wrote, iclass 28, count 0 2006.231.08:11:40.81#ibcon#about to read 3, iclass 28, count 0 2006.231.08:11:40.83#ibcon#read 3, iclass 28, count 0 2006.231.08:11:40.83#ibcon#about to read 4, iclass 28, count 0 2006.231.08:11:40.83#ibcon#read 4, iclass 28, count 0 2006.231.08:11:40.83#ibcon#about to read 5, iclass 28, count 0 2006.231.08:11:40.83#ibcon#read 5, iclass 28, count 0 2006.231.08:11:40.83#ibcon#about to read 6, iclass 28, count 0 2006.231.08:11:40.83#ibcon#read 6, iclass 28, count 0 2006.231.08:11:40.83#ibcon#end of sib2, iclass 28, count 0 2006.231.08:11:40.83#ibcon#*mode == 0, iclass 28, count 0 2006.231.08:11:40.83#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.08:11:40.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:11:40.83#ibcon#*before write, iclass 28, count 0 2006.231.08:11:40.83#ibcon#enter sib2, iclass 28, count 0 2006.231.08:11:40.83#ibcon#flushed, iclass 28, count 0 2006.231.08:11:40.83#ibcon#about to write, iclass 28, count 0 2006.231.08:11:40.83#ibcon#wrote, iclass 28, count 0 2006.231.08:11:40.83#ibcon#about to read 3, iclass 28, count 0 2006.231.08:11:40.87#ibcon#read 3, iclass 28, count 0 2006.231.08:11:40.87#ibcon#about to read 4, iclass 28, count 0 2006.231.08:11:40.87#ibcon#read 4, iclass 28, count 0 2006.231.08:11:40.87#ibcon#about to read 5, iclass 28, count 0 2006.231.08:11:40.87#ibcon#read 5, iclass 28, count 0 2006.231.08:11:40.87#ibcon#about to read 6, iclass 28, count 0 2006.231.08:11:40.87#ibcon#read 6, iclass 28, count 0 2006.231.08:11:40.87#ibcon#end of sib2, iclass 28, count 0 2006.231.08:11:40.87#ibcon#*after write, iclass 28, count 0 2006.231.08:11:40.87#ibcon#*before return 0, iclass 28, count 0 2006.231.08:11:40.87#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:11:40.87#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:11:40.87#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.08:11:40.87#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.08:11:40.87$vc4f8/vb=2,4 2006.231.08:11:40.87#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.08:11:40.87#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.08:11:40.87#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:40.87#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:11:40.93#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:11:40.93#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:11:40.93#ibcon#enter wrdev, iclass 30, count 2 2006.231.08:11:40.93#ibcon#first serial, iclass 30, count 2 2006.231.08:11:40.93#ibcon#enter sib2, iclass 30, count 2 2006.231.08:11:40.93#ibcon#flushed, iclass 30, count 2 2006.231.08:11:40.93#ibcon#about to write, iclass 30, count 2 2006.231.08:11:40.93#ibcon#wrote, iclass 30, count 2 2006.231.08:11:40.93#ibcon#about to read 3, iclass 30, count 2 2006.231.08:11:40.95#ibcon#read 3, iclass 30, count 2 2006.231.08:11:40.95#ibcon#about to read 4, iclass 30, count 2 2006.231.08:11:40.95#ibcon#read 4, iclass 30, count 2 2006.231.08:11:40.95#ibcon#about to read 5, iclass 30, count 2 2006.231.08:11:40.95#ibcon#read 5, iclass 30, count 2 2006.231.08:11:40.95#ibcon#about to read 6, iclass 30, count 2 2006.231.08:11:40.95#ibcon#read 6, iclass 30, count 2 2006.231.08:11:40.95#ibcon#end of sib2, iclass 30, count 2 2006.231.08:11:40.95#ibcon#*mode == 0, iclass 30, count 2 2006.231.08:11:40.95#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.08:11:40.95#ibcon#[27=AT02-04\r\n] 2006.231.08:11:40.95#ibcon#*before write, iclass 30, count 2 2006.231.08:11:40.95#ibcon#enter sib2, iclass 30, count 2 2006.231.08:11:40.95#ibcon#flushed, iclass 30, count 2 2006.231.08:11:40.95#ibcon#about to write, iclass 30, count 2 2006.231.08:11:40.95#ibcon#wrote, iclass 30, count 2 2006.231.08:11:40.95#ibcon#about to read 3, iclass 30, count 2 2006.231.08:11:40.98#ibcon#read 3, iclass 30, count 2 2006.231.08:11:40.98#ibcon#about to read 4, iclass 30, count 2 2006.231.08:11:40.98#ibcon#read 4, iclass 30, count 2 2006.231.08:11:40.98#ibcon#about to read 5, iclass 30, count 2 2006.231.08:11:40.98#ibcon#read 5, iclass 30, count 2 2006.231.08:11:40.98#ibcon#about to read 6, iclass 30, count 2 2006.231.08:11:40.98#ibcon#read 6, iclass 30, count 2 2006.231.08:11:40.98#ibcon#end of sib2, iclass 30, count 2 2006.231.08:11:40.98#ibcon#*after write, iclass 30, count 2 2006.231.08:11:40.98#ibcon#*before return 0, iclass 30, count 2 2006.231.08:11:40.98#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:11:40.98#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:11:40.98#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.08:11:40.98#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:40.98#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:11:41.10#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:11:41.10#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:11:41.10#ibcon#enter wrdev, iclass 30, count 0 2006.231.08:11:41.10#ibcon#first serial, iclass 30, count 0 2006.231.08:11:41.10#ibcon#enter sib2, iclass 30, count 0 2006.231.08:11:41.10#ibcon#flushed, iclass 30, count 0 2006.231.08:11:41.10#ibcon#about to write, iclass 30, count 0 2006.231.08:11:41.10#ibcon#wrote, iclass 30, count 0 2006.231.08:11:41.10#ibcon#about to read 3, iclass 30, count 0 2006.231.08:11:41.12#ibcon#read 3, iclass 30, count 0 2006.231.08:11:41.12#ibcon#about to read 4, iclass 30, count 0 2006.231.08:11:41.12#ibcon#read 4, iclass 30, count 0 2006.231.08:11:41.12#ibcon#about to read 5, iclass 30, count 0 2006.231.08:11:41.12#ibcon#read 5, iclass 30, count 0 2006.231.08:11:41.12#ibcon#about to read 6, iclass 30, count 0 2006.231.08:11:41.12#ibcon#read 6, iclass 30, count 0 2006.231.08:11:41.12#ibcon#end of sib2, iclass 30, count 0 2006.231.08:11:41.12#ibcon#*mode == 0, iclass 30, count 0 2006.231.08:11:41.12#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.08:11:41.12#ibcon#[27=USB\r\n] 2006.231.08:11:41.12#ibcon#*before write, iclass 30, count 0 2006.231.08:11:41.12#ibcon#enter sib2, iclass 30, count 0 2006.231.08:11:41.12#ibcon#flushed, iclass 30, count 0 2006.231.08:11:41.12#ibcon#about to write, iclass 30, count 0 2006.231.08:11:41.12#ibcon#wrote, iclass 30, count 0 2006.231.08:11:41.12#ibcon#about to read 3, iclass 30, count 0 2006.231.08:11:41.15#ibcon#read 3, iclass 30, count 0 2006.231.08:11:41.15#ibcon#about to read 4, iclass 30, count 0 2006.231.08:11:41.15#ibcon#read 4, iclass 30, count 0 2006.231.08:11:41.15#ibcon#about to read 5, iclass 30, count 0 2006.231.08:11:41.15#ibcon#read 5, iclass 30, count 0 2006.231.08:11:41.15#ibcon#about to read 6, iclass 30, count 0 2006.231.08:11:41.15#ibcon#read 6, iclass 30, count 0 2006.231.08:11:41.15#ibcon#end of sib2, iclass 30, count 0 2006.231.08:11:41.15#ibcon#*after write, iclass 30, count 0 2006.231.08:11:41.15#ibcon#*before return 0, iclass 30, count 0 2006.231.08:11:41.15#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:11:41.15#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:11:41.15#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.08:11:41.15#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.08:11:41.15$vc4f8/vblo=3,656.99 2006.231.08:11:41.15#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.08:11:41.15#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.08:11:41.15#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:41.15#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:11:41.15#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:11:41.15#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:11:41.15#ibcon#enter wrdev, iclass 32, count 0 2006.231.08:11:41.15#ibcon#first serial, iclass 32, count 0 2006.231.08:11:41.15#ibcon#enter sib2, iclass 32, count 0 2006.231.08:11:41.15#ibcon#flushed, iclass 32, count 0 2006.231.08:11:41.15#ibcon#about to write, iclass 32, count 0 2006.231.08:11:41.15#ibcon#wrote, iclass 32, count 0 2006.231.08:11:41.15#ibcon#about to read 3, iclass 32, count 0 2006.231.08:11:41.17#ibcon#read 3, iclass 32, count 0 2006.231.08:11:41.17#ibcon#about to read 4, iclass 32, count 0 2006.231.08:11:41.17#ibcon#read 4, iclass 32, count 0 2006.231.08:11:41.17#ibcon#about to read 5, iclass 32, count 0 2006.231.08:11:41.17#ibcon#read 5, iclass 32, count 0 2006.231.08:11:41.17#ibcon#about to read 6, iclass 32, count 0 2006.231.08:11:41.17#ibcon#read 6, iclass 32, count 0 2006.231.08:11:41.17#ibcon#end of sib2, iclass 32, count 0 2006.231.08:11:41.17#ibcon#*mode == 0, iclass 32, count 0 2006.231.08:11:41.17#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.08:11:41.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:11:41.17#ibcon#*before write, iclass 32, count 0 2006.231.08:11:41.17#ibcon#enter sib2, iclass 32, count 0 2006.231.08:11:41.17#ibcon#flushed, iclass 32, count 0 2006.231.08:11:41.17#ibcon#about to write, iclass 32, count 0 2006.231.08:11:41.17#ibcon#wrote, iclass 32, count 0 2006.231.08:11:41.17#ibcon#about to read 3, iclass 32, count 0 2006.231.08:11:41.21#ibcon#read 3, iclass 32, count 0 2006.231.08:11:41.21#ibcon#about to read 4, iclass 32, count 0 2006.231.08:11:41.21#ibcon#read 4, iclass 32, count 0 2006.231.08:11:41.21#ibcon#about to read 5, iclass 32, count 0 2006.231.08:11:41.21#ibcon#read 5, iclass 32, count 0 2006.231.08:11:41.21#ibcon#about to read 6, iclass 32, count 0 2006.231.08:11:41.21#ibcon#read 6, iclass 32, count 0 2006.231.08:11:41.21#ibcon#end of sib2, iclass 32, count 0 2006.231.08:11:41.21#ibcon#*after write, iclass 32, count 0 2006.231.08:11:41.21#ibcon#*before return 0, iclass 32, count 0 2006.231.08:11:41.21#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:11:41.21#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:11:41.21#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.08:11:41.21#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.08:11:41.21$vc4f8/vb=3,4 2006.231.08:11:41.21#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.08:11:41.21#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.08:11:41.21#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:41.21#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:11:41.27#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:11:41.27#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:11:41.27#ibcon#enter wrdev, iclass 34, count 2 2006.231.08:11:41.27#ibcon#first serial, iclass 34, count 2 2006.231.08:11:41.27#ibcon#enter sib2, iclass 34, count 2 2006.231.08:11:41.27#ibcon#flushed, iclass 34, count 2 2006.231.08:11:41.27#ibcon#about to write, iclass 34, count 2 2006.231.08:11:41.27#ibcon#wrote, iclass 34, count 2 2006.231.08:11:41.27#ibcon#about to read 3, iclass 34, count 2 2006.231.08:11:41.29#ibcon#read 3, iclass 34, count 2 2006.231.08:11:41.29#ibcon#about to read 4, iclass 34, count 2 2006.231.08:11:41.29#ibcon#read 4, iclass 34, count 2 2006.231.08:11:41.29#ibcon#about to read 5, iclass 34, count 2 2006.231.08:11:41.29#ibcon#read 5, iclass 34, count 2 2006.231.08:11:41.29#ibcon#about to read 6, iclass 34, count 2 2006.231.08:11:41.29#ibcon#read 6, iclass 34, count 2 2006.231.08:11:41.29#ibcon#end of sib2, iclass 34, count 2 2006.231.08:11:41.29#ibcon#*mode == 0, iclass 34, count 2 2006.231.08:11:41.29#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.08:11:41.29#ibcon#[27=AT03-04\r\n] 2006.231.08:11:41.29#ibcon#*before write, iclass 34, count 2 2006.231.08:11:41.29#ibcon#enter sib2, iclass 34, count 2 2006.231.08:11:41.29#ibcon#flushed, iclass 34, count 2 2006.231.08:11:41.29#ibcon#about to write, iclass 34, count 2 2006.231.08:11:41.29#ibcon#wrote, iclass 34, count 2 2006.231.08:11:41.29#ibcon#about to read 3, iclass 34, count 2 2006.231.08:11:41.32#ibcon#read 3, iclass 34, count 2 2006.231.08:11:41.32#ibcon#about to read 4, iclass 34, count 2 2006.231.08:11:41.32#ibcon#read 4, iclass 34, count 2 2006.231.08:11:41.32#ibcon#about to read 5, iclass 34, count 2 2006.231.08:11:41.32#ibcon#read 5, iclass 34, count 2 2006.231.08:11:41.32#ibcon#about to read 6, iclass 34, count 2 2006.231.08:11:41.32#ibcon#read 6, iclass 34, count 2 2006.231.08:11:41.32#ibcon#end of sib2, iclass 34, count 2 2006.231.08:11:41.32#ibcon#*after write, iclass 34, count 2 2006.231.08:11:41.32#ibcon#*before return 0, iclass 34, count 2 2006.231.08:11:41.32#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:11:41.32#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:11:41.32#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.08:11:41.32#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:41.32#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:11:41.44#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:11:41.44#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:11:41.44#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:11:41.44#ibcon#first serial, iclass 34, count 0 2006.231.08:11:41.44#ibcon#enter sib2, iclass 34, count 0 2006.231.08:11:41.44#ibcon#flushed, iclass 34, count 0 2006.231.08:11:41.44#ibcon#about to write, iclass 34, count 0 2006.231.08:11:41.44#ibcon#wrote, iclass 34, count 0 2006.231.08:11:41.44#ibcon#about to read 3, iclass 34, count 0 2006.231.08:11:41.46#ibcon#read 3, iclass 34, count 0 2006.231.08:11:41.46#ibcon#about to read 4, iclass 34, count 0 2006.231.08:11:41.46#ibcon#read 4, iclass 34, count 0 2006.231.08:11:41.46#ibcon#about to read 5, iclass 34, count 0 2006.231.08:11:41.46#ibcon#read 5, iclass 34, count 0 2006.231.08:11:41.46#ibcon#about to read 6, iclass 34, count 0 2006.231.08:11:41.46#ibcon#read 6, iclass 34, count 0 2006.231.08:11:41.46#ibcon#end of sib2, iclass 34, count 0 2006.231.08:11:41.46#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:11:41.46#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:11:41.46#ibcon#[27=USB\r\n] 2006.231.08:11:41.46#ibcon#*before write, iclass 34, count 0 2006.231.08:11:41.46#ibcon#enter sib2, iclass 34, count 0 2006.231.08:11:41.46#ibcon#flushed, iclass 34, count 0 2006.231.08:11:41.46#ibcon#about to write, iclass 34, count 0 2006.231.08:11:41.46#ibcon#wrote, iclass 34, count 0 2006.231.08:11:41.46#ibcon#about to read 3, iclass 34, count 0 2006.231.08:11:41.49#ibcon#read 3, iclass 34, count 0 2006.231.08:11:41.49#ibcon#about to read 4, iclass 34, count 0 2006.231.08:11:41.49#ibcon#read 4, iclass 34, count 0 2006.231.08:11:41.49#ibcon#about to read 5, iclass 34, count 0 2006.231.08:11:41.49#ibcon#read 5, iclass 34, count 0 2006.231.08:11:41.49#ibcon#about to read 6, iclass 34, count 0 2006.231.08:11:41.49#ibcon#read 6, iclass 34, count 0 2006.231.08:11:41.49#ibcon#end of sib2, iclass 34, count 0 2006.231.08:11:41.49#ibcon#*after write, iclass 34, count 0 2006.231.08:11:41.49#ibcon#*before return 0, iclass 34, count 0 2006.231.08:11:41.49#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:11:41.49#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:11:41.49#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:11:41.49#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:11:41.49$vc4f8/vblo=4,712.99 2006.231.08:11:41.49#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.08:11:41.49#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.08:11:41.49#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:41.49#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:11:41.49#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:11:41.49#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:11:41.49#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:11:41.49#ibcon#first serial, iclass 36, count 0 2006.231.08:11:41.49#ibcon#enter sib2, iclass 36, count 0 2006.231.08:11:41.49#ibcon#flushed, iclass 36, count 0 2006.231.08:11:41.49#ibcon#about to write, iclass 36, count 0 2006.231.08:11:41.49#ibcon#wrote, iclass 36, count 0 2006.231.08:11:41.49#ibcon#about to read 3, iclass 36, count 0 2006.231.08:11:41.51#ibcon#read 3, iclass 36, count 0 2006.231.08:11:41.51#ibcon#about to read 4, iclass 36, count 0 2006.231.08:11:41.51#ibcon#read 4, iclass 36, count 0 2006.231.08:11:41.51#ibcon#about to read 5, iclass 36, count 0 2006.231.08:11:41.51#ibcon#read 5, iclass 36, count 0 2006.231.08:11:41.51#ibcon#about to read 6, iclass 36, count 0 2006.231.08:11:41.51#ibcon#read 6, iclass 36, count 0 2006.231.08:11:41.51#ibcon#end of sib2, iclass 36, count 0 2006.231.08:11:41.51#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:11:41.51#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:11:41.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:11:41.51#ibcon#*before write, iclass 36, count 0 2006.231.08:11:41.51#ibcon#enter sib2, iclass 36, count 0 2006.231.08:11:41.51#ibcon#flushed, iclass 36, count 0 2006.231.08:11:41.51#ibcon#about to write, iclass 36, count 0 2006.231.08:11:41.51#ibcon#wrote, iclass 36, count 0 2006.231.08:11:41.51#ibcon#about to read 3, iclass 36, count 0 2006.231.08:11:41.55#ibcon#read 3, iclass 36, count 0 2006.231.08:11:41.55#ibcon#about to read 4, iclass 36, count 0 2006.231.08:11:41.55#ibcon#read 4, iclass 36, count 0 2006.231.08:11:41.55#ibcon#about to read 5, iclass 36, count 0 2006.231.08:11:41.55#ibcon#read 5, iclass 36, count 0 2006.231.08:11:41.55#ibcon#about to read 6, iclass 36, count 0 2006.231.08:11:41.55#ibcon#read 6, iclass 36, count 0 2006.231.08:11:41.55#ibcon#end of sib2, iclass 36, count 0 2006.231.08:11:41.55#ibcon#*after write, iclass 36, count 0 2006.231.08:11:41.55#ibcon#*before return 0, iclass 36, count 0 2006.231.08:11:41.55#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:11:41.55#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:11:41.55#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:11:41.55#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:11:41.55$vc4f8/vb=4,4 2006.231.08:11:41.55#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.08:11:41.55#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.08:11:41.55#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:41.55#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:11:41.61#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:11:41.61#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:11:41.61#ibcon#enter wrdev, iclass 38, count 2 2006.231.08:11:41.61#ibcon#first serial, iclass 38, count 2 2006.231.08:11:41.61#ibcon#enter sib2, iclass 38, count 2 2006.231.08:11:41.61#ibcon#flushed, iclass 38, count 2 2006.231.08:11:41.61#ibcon#about to write, iclass 38, count 2 2006.231.08:11:41.61#ibcon#wrote, iclass 38, count 2 2006.231.08:11:41.61#ibcon#about to read 3, iclass 38, count 2 2006.231.08:11:41.63#ibcon#read 3, iclass 38, count 2 2006.231.08:11:41.63#ibcon#about to read 4, iclass 38, count 2 2006.231.08:11:41.63#ibcon#read 4, iclass 38, count 2 2006.231.08:11:41.63#ibcon#about to read 5, iclass 38, count 2 2006.231.08:11:41.63#ibcon#read 5, iclass 38, count 2 2006.231.08:11:41.63#ibcon#about to read 6, iclass 38, count 2 2006.231.08:11:41.63#ibcon#read 6, iclass 38, count 2 2006.231.08:11:41.63#ibcon#end of sib2, iclass 38, count 2 2006.231.08:11:41.63#ibcon#*mode == 0, iclass 38, count 2 2006.231.08:11:41.63#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.08:11:41.63#ibcon#[27=AT04-04\r\n] 2006.231.08:11:41.63#ibcon#*before write, iclass 38, count 2 2006.231.08:11:41.63#ibcon#enter sib2, iclass 38, count 2 2006.231.08:11:41.63#ibcon#flushed, iclass 38, count 2 2006.231.08:11:41.63#ibcon#about to write, iclass 38, count 2 2006.231.08:11:41.63#ibcon#wrote, iclass 38, count 2 2006.231.08:11:41.63#ibcon#about to read 3, iclass 38, count 2 2006.231.08:11:41.66#ibcon#read 3, iclass 38, count 2 2006.231.08:11:41.66#ibcon#about to read 4, iclass 38, count 2 2006.231.08:11:41.66#ibcon#read 4, iclass 38, count 2 2006.231.08:11:41.66#ibcon#about to read 5, iclass 38, count 2 2006.231.08:11:41.66#ibcon#read 5, iclass 38, count 2 2006.231.08:11:41.66#ibcon#about to read 6, iclass 38, count 2 2006.231.08:11:41.66#ibcon#read 6, iclass 38, count 2 2006.231.08:11:41.66#ibcon#end of sib2, iclass 38, count 2 2006.231.08:11:41.66#ibcon#*after write, iclass 38, count 2 2006.231.08:11:41.66#ibcon#*before return 0, iclass 38, count 2 2006.231.08:11:41.66#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:11:41.66#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:11:41.66#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.08:11:41.66#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:41.66#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:11:41.78#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:11:41.78#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:11:41.78#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:11:41.78#ibcon#first serial, iclass 38, count 0 2006.231.08:11:41.78#ibcon#enter sib2, iclass 38, count 0 2006.231.08:11:41.78#ibcon#flushed, iclass 38, count 0 2006.231.08:11:41.78#ibcon#about to write, iclass 38, count 0 2006.231.08:11:41.78#ibcon#wrote, iclass 38, count 0 2006.231.08:11:41.78#ibcon#about to read 3, iclass 38, count 0 2006.231.08:11:41.80#ibcon#read 3, iclass 38, count 0 2006.231.08:11:41.80#ibcon#about to read 4, iclass 38, count 0 2006.231.08:11:41.80#ibcon#read 4, iclass 38, count 0 2006.231.08:11:41.80#ibcon#about to read 5, iclass 38, count 0 2006.231.08:11:41.80#ibcon#read 5, iclass 38, count 0 2006.231.08:11:41.80#ibcon#about to read 6, iclass 38, count 0 2006.231.08:11:41.80#ibcon#read 6, iclass 38, count 0 2006.231.08:11:41.80#ibcon#end of sib2, iclass 38, count 0 2006.231.08:11:41.80#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:11:41.80#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:11:41.80#ibcon#[27=USB\r\n] 2006.231.08:11:41.80#ibcon#*before write, iclass 38, count 0 2006.231.08:11:41.80#ibcon#enter sib2, iclass 38, count 0 2006.231.08:11:41.80#ibcon#flushed, iclass 38, count 0 2006.231.08:11:41.80#ibcon#about to write, iclass 38, count 0 2006.231.08:11:41.80#ibcon#wrote, iclass 38, count 0 2006.231.08:11:41.80#ibcon#about to read 3, iclass 38, count 0 2006.231.08:11:41.83#ibcon#read 3, iclass 38, count 0 2006.231.08:11:41.83#ibcon#about to read 4, iclass 38, count 0 2006.231.08:11:41.83#ibcon#read 4, iclass 38, count 0 2006.231.08:11:41.83#ibcon#about to read 5, iclass 38, count 0 2006.231.08:11:41.83#ibcon#read 5, iclass 38, count 0 2006.231.08:11:41.83#ibcon#about to read 6, iclass 38, count 0 2006.231.08:11:41.83#ibcon#read 6, iclass 38, count 0 2006.231.08:11:41.83#ibcon#end of sib2, iclass 38, count 0 2006.231.08:11:41.83#ibcon#*after write, iclass 38, count 0 2006.231.08:11:41.83#ibcon#*before return 0, iclass 38, count 0 2006.231.08:11:41.83#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:11:41.83#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:11:41.83#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:11:41.83#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:11:41.83$vc4f8/vblo=5,744.99 2006.231.08:11:41.83#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.08:11:41.83#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.08:11:41.83#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:41.83#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:11:41.83#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:11:41.83#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:11:41.83#ibcon#enter wrdev, iclass 40, count 0 2006.231.08:11:41.83#ibcon#first serial, iclass 40, count 0 2006.231.08:11:41.83#ibcon#enter sib2, iclass 40, count 0 2006.231.08:11:41.83#ibcon#flushed, iclass 40, count 0 2006.231.08:11:41.83#ibcon#about to write, iclass 40, count 0 2006.231.08:11:41.83#ibcon#wrote, iclass 40, count 0 2006.231.08:11:41.83#ibcon#about to read 3, iclass 40, count 0 2006.231.08:11:41.85#ibcon#read 3, iclass 40, count 0 2006.231.08:11:41.85#ibcon#about to read 4, iclass 40, count 0 2006.231.08:11:41.85#ibcon#read 4, iclass 40, count 0 2006.231.08:11:41.85#ibcon#about to read 5, iclass 40, count 0 2006.231.08:11:41.85#ibcon#read 5, iclass 40, count 0 2006.231.08:11:41.85#ibcon#about to read 6, iclass 40, count 0 2006.231.08:11:41.85#ibcon#read 6, iclass 40, count 0 2006.231.08:11:41.85#ibcon#end of sib2, iclass 40, count 0 2006.231.08:11:41.85#ibcon#*mode == 0, iclass 40, count 0 2006.231.08:11:41.85#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.08:11:41.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:11:41.85#ibcon#*before write, iclass 40, count 0 2006.231.08:11:41.85#ibcon#enter sib2, iclass 40, count 0 2006.231.08:11:41.85#ibcon#flushed, iclass 40, count 0 2006.231.08:11:41.85#ibcon#about to write, iclass 40, count 0 2006.231.08:11:41.85#ibcon#wrote, iclass 40, count 0 2006.231.08:11:41.85#ibcon#about to read 3, iclass 40, count 0 2006.231.08:11:41.89#ibcon#read 3, iclass 40, count 0 2006.231.08:11:41.89#ibcon#about to read 4, iclass 40, count 0 2006.231.08:11:41.89#ibcon#read 4, iclass 40, count 0 2006.231.08:11:41.89#ibcon#about to read 5, iclass 40, count 0 2006.231.08:11:41.89#ibcon#read 5, iclass 40, count 0 2006.231.08:11:41.89#ibcon#about to read 6, iclass 40, count 0 2006.231.08:11:41.89#ibcon#read 6, iclass 40, count 0 2006.231.08:11:41.89#ibcon#end of sib2, iclass 40, count 0 2006.231.08:11:41.89#ibcon#*after write, iclass 40, count 0 2006.231.08:11:41.89#ibcon#*before return 0, iclass 40, count 0 2006.231.08:11:41.89#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:11:41.89#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:11:41.89#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.08:11:41.89#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.08:11:41.89$vc4f8/vb=5,3 2006.231.08:11:41.89#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.231.08:11:41.89#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.231.08:11:41.89#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:41.89#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:11:41.95#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:11:41.95#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:11:41.95#ibcon#enter wrdev, iclass 4, count 2 2006.231.08:11:41.95#ibcon#first serial, iclass 4, count 2 2006.231.08:11:41.95#ibcon#enter sib2, iclass 4, count 2 2006.231.08:11:41.95#ibcon#flushed, iclass 4, count 2 2006.231.08:11:41.95#ibcon#about to write, iclass 4, count 2 2006.231.08:11:41.95#ibcon#wrote, iclass 4, count 2 2006.231.08:11:41.95#ibcon#about to read 3, iclass 4, count 2 2006.231.08:11:41.98#ibcon#read 3, iclass 4, count 2 2006.231.08:11:41.98#ibcon#about to read 4, iclass 4, count 2 2006.231.08:11:41.98#ibcon#read 4, iclass 4, count 2 2006.231.08:11:41.98#ibcon#about to read 5, iclass 4, count 2 2006.231.08:11:41.98#ibcon#read 5, iclass 4, count 2 2006.231.08:11:41.98#ibcon#about to read 6, iclass 4, count 2 2006.231.08:11:41.98#ibcon#read 6, iclass 4, count 2 2006.231.08:11:41.98#ibcon#end of sib2, iclass 4, count 2 2006.231.08:11:41.98#ibcon#*mode == 0, iclass 4, count 2 2006.231.08:11:41.98#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.231.08:11:41.98#ibcon#[27=AT05-03\r\n] 2006.231.08:11:41.98#ibcon#*before write, iclass 4, count 2 2006.231.08:11:41.98#ibcon#enter sib2, iclass 4, count 2 2006.231.08:11:41.98#ibcon#flushed, iclass 4, count 2 2006.231.08:11:41.98#ibcon#about to write, iclass 4, count 2 2006.231.08:11:41.98#ibcon#wrote, iclass 4, count 2 2006.231.08:11:41.98#ibcon#about to read 3, iclass 4, count 2 2006.231.08:11:42.01#ibcon#read 3, iclass 4, count 2 2006.231.08:11:42.01#ibcon#about to read 4, iclass 4, count 2 2006.231.08:11:42.01#ibcon#read 4, iclass 4, count 2 2006.231.08:11:42.01#ibcon#about to read 5, iclass 4, count 2 2006.231.08:11:42.01#ibcon#read 5, iclass 4, count 2 2006.231.08:11:42.01#ibcon#about to read 6, iclass 4, count 2 2006.231.08:11:42.01#ibcon#read 6, iclass 4, count 2 2006.231.08:11:42.01#ibcon#end of sib2, iclass 4, count 2 2006.231.08:11:42.01#ibcon#*after write, iclass 4, count 2 2006.231.08:11:42.01#ibcon#*before return 0, iclass 4, count 2 2006.231.08:11:42.01#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:11:42.01#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:11:42.01#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.231.08:11:42.01#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:42.01#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:11:42.13#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:11:42.13#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:11:42.13#ibcon#enter wrdev, iclass 4, count 0 2006.231.08:11:42.13#ibcon#first serial, iclass 4, count 0 2006.231.08:11:42.13#ibcon#enter sib2, iclass 4, count 0 2006.231.08:11:42.13#ibcon#flushed, iclass 4, count 0 2006.231.08:11:42.13#ibcon#about to write, iclass 4, count 0 2006.231.08:11:42.13#ibcon#wrote, iclass 4, count 0 2006.231.08:11:42.13#ibcon#about to read 3, iclass 4, count 0 2006.231.08:11:42.15#ibcon#read 3, iclass 4, count 0 2006.231.08:11:42.15#ibcon#about to read 4, iclass 4, count 0 2006.231.08:11:42.15#ibcon#read 4, iclass 4, count 0 2006.231.08:11:42.15#ibcon#about to read 5, iclass 4, count 0 2006.231.08:11:42.15#ibcon#read 5, iclass 4, count 0 2006.231.08:11:42.15#ibcon#about to read 6, iclass 4, count 0 2006.231.08:11:42.15#ibcon#read 6, iclass 4, count 0 2006.231.08:11:42.15#ibcon#end of sib2, iclass 4, count 0 2006.231.08:11:42.15#ibcon#*mode == 0, iclass 4, count 0 2006.231.08:11:42.15#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.08:11:42.15#ibcon#[27=USB\r\n] 2006.231.08:11:42.15#ibcon#*before write, iclass 4, count 0 2006.231.08:11:42.15#ibcon#enter sib2, iclass 4, count 0 2006.231.08:11:42.15#ibcon#flushed, iclass 4, count 0 2006.231.08:11:42.15#ibcon#about to write, iclass 4, count 0 2006.231.08:11:42.15#ibcon#wrote, iclass 4, count 0 2006.231.08:11:42.15#ibcon#about to read 3, iclass 4, count 0 2006.231.08:11:42.18#ibcon#read 3, iclass 4, count 0 2006.231.08:11:42.18#ibcon#about to read 4, iclass 4, count 0 2006.231.08:11:42.18#ibcon#read 4, iclass 4, count 0 2006.231.08:11:42.18#ibcon#about to read 5, iclass 4, count 0 2006.231.08:11:42.18#ibcon#read 5, iclass 4, count 0 2006.231.08:11:42.18#ibcon#about to read 6, iclass 4, count 0 2006.231.08:11:42.18#ibcon#read 6, iclass 4, count 0 2006.231.08:11:42.18#ibcon#end of sib2, iclass 4, count 0 2006.231.08:11:42.18#ibcon#*after write, iclass 4, count 0 2006.231.08:11:42.18#ibcon#*before return 0, iclass 4, count 0 2006.231.08:11:42.18#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:11:42.18#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:11:42.18#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.08:11:42.18#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.08:11:42.18$vc4f8/vblo=6,752.99 2006.231.08:11:42.18#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.231.08:11:42.18#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.231.08:11:42.18#ibcon#ireg 17 cls_cnt 0 2006.231.08:11:42.18#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:11:42.18#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:11:42.18#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:11:42.18#ibcon#enter wrdev, iclass 6, count 0 2006.231.08:11:42.18#ibcon#first serial, iclass 6, count 0 2006.231.08:11:42.18#ibcon#enter sib2, iclass 6, count 0 2006.231.08:11:42.18#ibcon#flushed, iclass 6, count 0 2006.231.08:11:42.18#ibcon#about to write, iclass 6, count 0 2006.231.08:11:42.18#ibcon#wrote, iclass 6, count 0 2006.231.08:11:42.18#ibcon#about to read 3, iclass 6, count 0 2006.231.08:11:42.20#ibcon#read 3, iclass 6, count 0 2006.231.08:11:42.20#ibcon#about to read 4, iclass 6, count 0 2006.231.08:11:42.20#ibcon#read 4, iclass 6, count 0 2006.231.08:11:42.20#ibcon#about to read 5, iclass 6, count 0 2006.231.08:11:42.20#ibcon#read 5, iclass 6, count 0 2006.231.08:11:42.20#ibcon#about to read 6, iclass 6, count 0 2006.231.08:11:42.20#ibcon#read 6, iclass 6, count 0 2006.231.08:11:42.20#ibcon#end of sib2, iclass 6, count 0 2006.231.08:11:42.20#ibcon#*mode == 0, iclass 6, count 0 2006.231.08:11:42.20#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.08:11:42.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:11:42.20#ibcon#*before write, iclass 6, count 0 2006.231.08:11:42.20#ibcon#enter sib2, iclass 6, count 0 2006.231.08:11:42.20#ibcon#flushed, iclass 6, count 0 2006.231.08:11:42.20#ibcon#about to write, iclass 6, count 0 2006.231.08:11:42.20#ibcon#wrote, iclass 6, count 0 2006.231.08:11:42.20#ibcon#about to read 3, iclass 6, count 0 2006.231.08:11:42.24#ibcon#read 3, iclass 6, count 0 2006.231.08:11:42.24#ibcon#about to read 4, iclass 6, count 0 2006.231.08:11:42.24#ibcon#read 4, iclass 6, count 0 2006.231.08:11:42.24#ibcon#about to read 5, iclass 6, count 0 2006.231.08:11:42.24#ibcon#read 5, iclass 6, count 0 2006.231.08:11:42.24#ibcon#about to read 6, iclass 6, count 0 2006.231.08:11:42.24#ibcon#read 6, iclass 6, count 0 2006.231.08:11:42.24#ibcon#end of sib2, iclass 6, count 0 2006.231.08:11:42.24#ibcon#*after write, iclass 6, count 0 2006.231.08:11:42.24#ibcon#*before return 0, iclass 6, count 0 2006.231.08:11:42.24#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:11:42.24#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:11:42.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.08:11:42.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.08:11:42.24$vc4f8/vb=6,4 2006.231.08:11:42.24#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.231.08:11:42.24#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.231.08:11:42.24#ibcon#ireg 11 cls_cnt 2 2006.231.08:11:42.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:11:42.30#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:11:42.30#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:11:42.30#ibcon#enter wrdev, iclass 10, count 2 2006.231.08:11:42.30#ibcon#first serial, iclass 10, count 2 2006.231.08:11:42.30#ibcon#enter sib2, iclass 10, count 2 2006.231.08:11:42.30#ibcon#flushed, iclass 10, count 2 2006.231.08:11:42.30#ibcon#about to write, iclass 10, count 2 2006.231.08:11:42.30#ibcon#wrote, iclass 10, count 2 2006.231.08:11:42.30#ibcon#about to read 3, iclass 10, count 2 2006.231.08:11:42.32#ibcon#read 3, iclass 10, count 2 2006.231.08:11:42.32#ibcon#about to read 4, iclass 10, count 2 2006.231.08:11:42.32#ibcon#read 4, iclass 10, count 2 2006.231.08:11:42.32#ibcon#about to read 5, iclass 10, count 2 2006.231.08:11:42.32#ibcon#read 5, iclass 10, count 2 2006.231.08:11:42.32#ibcon#about to read 6, iclass 10, count 2 2006.231.08:11:42.32#ibcon#read 6, iclass 10, count 2 2006.231.08:11:42.32#ibcon#end of sib2, iclass 10, count 2 2006.231.08:11:42.32#ibcon#*mode == 0, iclass 10, count 2 2006.231.08:11:42.32#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.231.08:11:42.32#ibcon#[27=AT06-04\r\n] 2006.231.08:11:42.32#ibcon#*before write, iclass 10, count 2 2006.231.08:11:42.32#ibcon#enter sib2, iclass 10, count 2 2006.231.08:11:42.32#ibcon#flushed, iclass 10, count 2 2006.231.08:11:42.32#ibcon#about to write, iclass 10, count 2 2006.231.08:11:42.32#ibcon#wrote, iclass 10, count 2 2006.231.08:11:42.32#ibcon#about to read 3, iclass 10, count 2 2006.231.08:11:42.35#ibcon#read 3, iclass 10, count 2 2006.231.08:11:42.35#ibcon#about to read 4, iclass 10, count 2 2006.231.08:11:42.35#ibcon#read 4, iclass 10, count 2 2006.231.08:11:42.35#ibcon#about to read 5, iclass 10, count 2 2006.231.08:11:42.35#ibcon#read 5, iclass 10, count 2 2006.231.08:11:42.35#ibcon#about to read 6, iclass 10, count 2 2006.231.08:11:42.35#ibcon#read 6, iclass 10, count 2 2006.231.08:11:42.35#ibcon#end of sib2, iclass 10, count 2 2006.231.08:11:42.35#ibcon#*after write, iclass 10, count 2 2006.231.08:11:42.35#ibcon#*before return 0, iclass 10, count 2 2006.231.08:11:42.35#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:11:42.35#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:11:42.35#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.231.08:11:42.35#ibcon#ireg 7 cls_cnt 0 2006.231.08:11:42.35#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:11:42.47#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:11:42.47#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:11:42.47#ibcon#enter wrdev, iclass 10, count 0 2006.231.08:11:42.47#ibcon#first serial, iclass 10, count 0 2006.231.08:11:42.47#ibcon#enter sib2, iclass 10, count 0 2006.231.08:11:42.47#ibcon#flushed, iclass 10, count 0 2006.231.08:11:42.47#ibcon#about to write, iclass 10, count 0 2006.231.08:11:42.47#ibcon#wrote, iclass 10, count 0 2006.231.08:11:42.47#ibcon#about to read 3, iclass 10, count 0 2006.231.08:11:42.49#ibcon#read 3, iclass 10, count 0 2006.231.08:11:42.49#ibcon#about to read 4, iclass 10, count 0 2006.231.08:11:42.49#ibcon#read 4, iclass 10, count 0 2006.231.08:11:42.49#ibcon#about to read 5, iclass 10, count 0 2006.231.08:11:42.49#ibcon#read 5, iclass 10, count 0 2006.231.08:11:42.49#ibcon#about to read 6, iclass 10, count 0 2006.231.08:11:42.49#ibcon#read 6, iclass 10, count 0 2006.231.08:11:42.49#ibcon#end of sib2, iclass 10, count 0 2006.231.08:11:42.49#ibcon#*mode == 0, iclass 10, count 0 2006.231.08:11:42.49#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.08:11:42.49#ibcon#[27=USB\r\n] 2006.231.08:11:42.49#ibcon#*before write, iclass 10, count 0 2006.231.08:11:42.49#ibcon#enter sib2, iclass 10, count 0 2006.231.08:11:42.49#ibcon#flushed, iclass 10, count 0 2006.231.08:11:42.49#ibcon#about to write, iclass 10, count 0 2006.231.08:11:42.49#ibcon#wrote, iclass 10, count 0 2006.231.08:11:42.49#ibcon#about to read 3, iclass 10, count 0 2006.231.08:11:42.52#ibcon#read 3, iclass 10, count 0 2006.231.08:11:42.52#ibcon#about to read 4, iclass 10, count 0 2006.231.08:11:42.52#ibcon#read 4, iclass 10, count 0 2006.231.08:11:42.52#ibcon#about to read 5, iclass 10, count 0 2006.231.08:11:42.52#ibcon#read 5, iclass 10, count 0 2006.231.08:11:42.52#ibcon#about to read 6, iclass 10, count 0 2006.231.08:11:42.52#ibcon#read 6, iclass 10, count 0 2006.231.08:11:42.52#ibcon#end of sib2, iclass 10, count 0 2006.231.08:11:42.52#ibcon#*after write, iclass 10, count 0 2006.231.08:11:42.52#ibcon#*before return 0, iclass 10, count 0 2006.231.08:11:42.52#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:11:42.52#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:11:42.52#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.08:11:42.52#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.08:11:42.52$vc4f8/vabw=wide 2006.231.08:11:42.52#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.08:11:42.52#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.08:11:42.52#ibcon#ireg 8 cls_cnt 0 2006.231.08:11:42.52#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:11:42.52#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:11:42.52#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:11:42.52#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:11:42.52#ibcon#first serial, iclass 12, count 0 2006.231.08:11:42.52#ibcon#enter sib2, iclass 12, count 0 2006.231.08:11:42.52#ibcon#flushed, iclass 12, count 0 2006.231.08:11:42.52#ibcon#about to write, iclass 12, count 0 2006.231.08:11:42.52#ibcon#wrote, iclass 12, count 0 2006.231.08:11:42.52#ibcon#about to read 3, iclass 12, count 0 2006.231.08:11:42.54#ibcon#read 3, iclass 12, count 0 2006.231.08:11:42.54#ibcon#about to read 4, iclass 12, count 0 2006.231.08:11:42.54#ibcon#read 4, iclass 12, count 0 2006.231.08:11:42.54#ibcon#about to read 5, iclass 12, count 0 2006.231.08:11:42.54#ibcon#read 5, iclass 12, count 0 2006.231.08:11:42.54#ibcon#about to read 6, iclass 12, count 0 2006.231.08:11:42.54#ibcon#read 6, iclass 12, count 0 2006.231.08:11:42.54#ibcon#end of sib2, iclass 12, count 0 2006.231.08:11:42.54#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:11:42.54#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:11:42.54#ibcon#[25=BW32\r\n] 2006.231.08:11:42.54#ibcon#*before write, iclass 12, count 0 2006.231.08:11:42.54#ibcon#enter sib2, iclass 12, count 0 2006.231.08:11:42.54#ibcon#flushed, iclass 12, count 0 2006.231.08:11:42.54#ibcon#about to write, iclass 12, count 0 2006.231.08:11:42.54#ibcon#wrote, iclass 12, count 0 2006.231.08:11:42.54#ibcon#about to read 3, iclass 12, count 0 2006.231.08:11:42.57#ibcon#read 3, iclass 12, count 0 2006.231.08:11:42.57#ibcon#about to read 4, iclass 12, count 0 2006.231.08:11:42.57#ibcon#read 4, iclass 12, count 0 2006.231.08:11:42.57#ibcon#about to read 5, iclass 12, count 0 2006.231.08:11:42.57#ibcon#read 5, iclass 12, count 0 2006.231.08:11:42.57#ibcon#about to read 6, iclass 12, count 0 2006.231.08:11:42.57#ibcon#read 6, iclass 12, count 0 2006.231.08:11:42.57#ibcon#end of sib2, iclass 12, count 0 2006.231.08:11:42.57#ibcon#*after write, iclass 12, count 0 2006.231.08:11:42.57#ibcon#*before return 0, iclass 12, count 0 2006.231.08:11:42.57#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:11:42.57#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:11:42.57#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:11:42.57#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:11:42.57$vc4f8/vbbw=wide 2006.231.08:11:42.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.08:11:42.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.08:11:42.57#ibcon#ireg 8 cls_cnt 0 2006.231.08:11:42.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:11:42.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:11:42.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:11:42.64#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:11:42.64#ibcon#first serial, iclass 14, count 0 2006.231.08:11:42.64#ibcon#enter sib2, iclass 14, count 0 2006.231.08:11:42.64#ibcon#flushed, iclass 14, count 0 2006.231.08:11:42.64#ibcon#about to write, iclass 14, count 0 2006.231.08:11:42.64#ibcon#wrote, iclass 14, count 0 2006.231.08:11:42.64#ibcon#about to read 3, iclass 14, count 0 2006.231.08:11:42.66#ibcon#read 3, iclass 14, count 0 2006.231.08:11:42.66#ibcon#about to read 4, iclass 14, count 0 2006.231.08:11:42.66#ibcon#read 4, iclass 14, count 0 2006.231.08:11:42.66#ibcon#about to read 5, iclass 14, count 0 2006.231.08:11:42.66#ibcon#read 5, iclass 14, count 0 2006.231.08:11:42.66#ibcon#about to read 6, iclass 14, count 0 2006.231.08:11:42.66#ibcon#read 6, iclass 14, count 0 2006.231.08:11:42.66#ibcon#end of sib2, iclass 14, count 0 2006.231.08:11:42.66#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:11:42.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:11:42.66#ibcon#[27=BW32\r\n] 2006.231.08:11:42.66#ibcon#*before write, iclass 14, count 0 2006.231.08:11:42.66#ibcon#enter sib2, iclass 14, count 0 2006.231.08:11:42.66#ibcon#flushed, iclass 14, count 0 2006.231.08:11:42.66#ibcon#about to write, iclass 14, count 0 2006.231.08:11:42.66#ibcon#wrote, iclass 14, count 0 2006.231.08:11:42.66#ibcon#about to read 3, iclass 14, count 0 2006.231.08:11:42.69#ibcon#read 3, iclass 14, count 0 2006.231.08:11:42.69#ibcon#about to read 4, iclass 14, count 0 2006.231.08:11:42.69#ibcon#read 4, iclass 14, count 0 2006.231.08:11:42.69#ibcon#about to read 5, iclass 14, count 0 2006.231.08:11:42.69#ibcon#read 5, iclass 14, count 0 2006.231.08:11:42.69#ibcon#about to read 6, iclass 14, count 0 2006.231.08:11:42.69#ibcon#read 6, iclass 14, count 0 2006.231.08:11:42.69#ibcon#end of sib2, iclass 14, count 0 2006.231.08:11:42.69#ibcon#*after write, iclass 14, count 0 2006.231.08:11:42.69#ibcon#*before return 0, iclass 14, count 0 2006.231.08:11:42.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:11:42.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:11:42.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:11:42.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:11:42.69$4f8m12a/ifd4f 2006.231.08:11:42.69$ifd4f/lo= 2006.231.08:11:42.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:11:42.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:11:42.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:11:42.69$ifd4f/patch= 2006.231.08:11:42.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:11:42.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:11:42.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:11:42.69$4f8m12a/"form=m,16.000,1:2 2006.231.08:11:42.69$4f8m12a/"tpicd 2006.231.08:11:42.69$4f8m12a/echo=off 2006.231.08:11:42.69$4f8m12a/xlog=off 2006.231.08:11:42.69:!2006.231.08:12:10 2006.231.08:11:50.14#trakl#Source acquired 2006.231.08:11:52.14#flagr#flagr/antenna,acquired 2006.231.08:12:10.00:preob 2006.231.08:12:11.14/onsource/TRACKING 2006.231.08:12:11.14:!2006.231.08:12:20 2006.231.08:12:20.00:data_valid=on 2006.231.08:12:20.00:midob 2006.231.08:12:20.14/onsource/TRACKING 2006.231.08:12:20.14/wx/30.45,1004.5,86 2006.231.08:12:20.30/cable/+6.3719E-03 2006.231.08:12:21.39/va/01,08,usb,yes,29,31 2006.231.08:12:21.39/va/02,07,usb,yes,29,31 2006.231.08:12:21.39/va/03,08,usb,yes,22,22 2006.231.08:12:21.39/va/04,07,usb,yes,31,33 2006.231.08:12:21.39/va/05,07,usb,yes,33,35 2006.231.08:12:21.39/va/06,06,usb,yes,33,32 2006.231.08:12:21.39/va/07,06,usb,yes,33,33 2006.231.08:12:21.39/va/08,06,usb,yes,36,35 2006.231.08:12:21.62/valo/01,532.99,yes,locked 2006.231.08:12:21.62/valo/02,572.99,yes,locked 2006.231.08:12:21.62/valo/03,672.99,yes,locked 2006.231.08:12:21.62/valo/04,832.99,yes,locked 2006.231.08:12:21.62/valo/05,652.99,yes,locked 2006.231.08:12:21.62/valo/06,772.99,yes,locked 2006.231.08:12:21.62/valo/07,832.99,yes,locked 2006.231.08:12:21.62/valo/08,852.99,yes,locked 2006.231.08:12:22.71/vb/01,04,usb,yes,30,29 2006.231.08:12:22.71/vb/02,04,usb,yes,32,33 2006.231.08:12:22.71/vb/03,04,usb,yes,28,32 2006.231.08:12:22.71/vb/04,04,usb,yes,29,29 2006.231.08:12:22.71/vb/05,03,usb,yes,35,39 2006.231.08:12:22.71/vb/06,04,usb,yes,29,32 2006.231.08:12:22.71/vb/07,04,usb,yes,31,31 2006.231.08:12:22.71/vb/08,04,usb,yes,28,32 2006.231.08:12:22.94/vblo/01,632.99,yes,locked 2006.231.08:12:22.94/vblo/02,640.99,yes,locked 2006.231.08:12:22.94/vblo/03,656.99,yes,locked 2006.231.08:12:22.94/vblo/04,712.99,yes,locked 2006.231.08:12:22.94/vblo/05,744.99,yes,locked 2006.231.08:12:22.94/vblo/06,752.99,yes,locked 2006.231.08:12:22.94/vblo/07,734.99,yes,locked 2006.231.08:12:22.94/vblo/08,744.99,yes,locked 2006.231.08:12:23.09/vabw/8 2006.231.08:12:23.24/vbbw/8 2006.231.08:12:23.33/xfe/off,on,12.2 2006.231.08:12:23.72/ifatt/23,28,28,28 2006.231.08:12:24.07/fmout-gps/S +4.44E-07 2006.231.08:12:24.15:!2006.231.08:13:20 2006.231.08:13:20.01:data_valid=off 2006.231.08:13:20.02:postob 2006.231.08:13:20.10/cable/+6.3728E-03 2006.231.08:13:20.10/wx/30.45,1004.5,86 2006.231.08:13:21.07/fmout-gps/S +4.43E-07 2006.231.08:13:21.08:scan_name=231-0814,k06231,60 2006.231.08:13:21.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.231.08:13:21.14#flagr#flagr/antenna,new-source 2006.231.08:13:22.14:checkk5 2006.231.08:13:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:13:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:13:23.28/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:13:23.67/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:13:24.03/chk_obsdata//k5ts1/T2310812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:13:24.40/chk_obsdata//k5ts2/T2310812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:13:24.76/chk_obsdata//k5ts3/T2310812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:13:25.13/chk_obsdata//k5ts4/T2310812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:13:25.82/k5log//k5ts1_log_newline 2006.231.08:13:26.50/k5log//k5ts2_log_newline 2006.231.08:13:27.19/k5log//k5ts3_log_newline 2006.231.08:13:27.88/k5log//k5ts4_log_newline 2006.231.08:13:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:13:27.90:4f8m12a=2 2006.231.08:13:27.90$4f8m12a/echo=on 2006.231.08:13:27.90$4f8m12a/pcalon 2006.231.08:13:27.90$pcalon/"no phase cal control is implemented here 2006.231.08:13:27.90$4f8m12a/"tpicd=stop 2006.231.08:13:27.91$4f8m12a/vc4f8 2006.231.08:13:27.91$vc4f8/valo=1,532.99 2006.231.08:13:27.91#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.231.08:13:27.91#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.231.08:13:27.91#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:27.91#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:13:27.91#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:13:27.91#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:13:27.91#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:13:27.91#ibcon#first serial, iclass 25, count 0 2006.231.08:13:27.91#ibcon#enter sib2, iclass 25, count 0 2006.231.08:13:27.91#ibcon#flushed, iclass 25, count 0 2006.231.08:13:27.91#ibcon#about to write, iclass 25, count 0 2006.231.08:13:27.91#ibcon#wrote, iclass 25, count 0 2006.231.08:13:27.91#ibcon#about to read 3, iclass 25, count 0 2006.231.08:13:27.95#ibcon#read 3, iclass 25, count 0 2006.231.08:13:27.95#ibcon#about to read 4, iclass 25, count 0 2006.231.08:13:27.95#ibcon#read 4, iclass 25, count 0 2006.231.08:13:27.95#ibcon#about to read 5, iclass 25, count 0 2006.231.08:13:27.95#ibcon#read 5, iclass 25, count 0 2006.231.08:13:27.95#ibcon#about to read 6, iclass 25, count 0 2006.231.08:13:27.95#ibcon#read 6, iclass 25, count 0 2006.231.08:13:27.95#ibcon#end of sib2, iclass 25, count 0 2006.231.08:13:27.95#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:13:27.95#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:13:27.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:13:27.95#ibcon#*before write, iclass 25, count 0 2006.231.08:13:27.95#ibcon#enter sib2, iclass 25, count 0 2006.231.08:13:27.95#ibcon#flushed, iclass 25, count 0 2006.231.08:13:27.95#ibcon#about to write, iclass 25, count 0 2006.231.08:13:27.95#ibcon#wrote, iclass 25, count 0 2006.231.08:13:27.95#ibcon#about to read 3, iclass 25, count 0 2006.231.08:13:27.99#ibcon#read 3, iclass 25, count 0 2006.231.08:13:27.99#ibcon#about to read 4, iclass 25, count 0 2006.231.08:13:27.99#ibcon#read 4, iclass 25, count 0 2006.231.08:13:27.99#ibcon#about to read 5, iclass 25, count 0 2006.231.08:13:27.99#ibcon#read 5, iclass 25, count 0 2006.231.08:13:27.99#ibcon#about to read 6, iclass 25, count 0 2006.231.08:13:27.99#ibcon#read 6, iclass 25, count 0 2006.231.08:13:27.99#ibcon#end of sib2, iclass 25, count 0 2006.231.08:13:27.99#ibcon#*after write, iclass 25, count 0 2006.231.08:13:27.99#ibcon#*before return 0, iclass 25, count 0 2006.231.08:13:27.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:13:27.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:13:27.99#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:13:27.99#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:13:27.99$vc4f8/va=1,8 2006.231.08:13:27.99#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.231.08:13:27.99#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.231.08:13:27.99#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:27.99#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:13:27.99#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:13:27.99#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:13:27.99#ibcon#enter wrdev, iclass 27, count 2 2006.231.08:13:27.99#ibcon#first serial, iclass 27, count 2 2006.231.08:13:27.99#ibcon#enter sib2, iclass 27, count 2 2006.231.08:13:27.99#ibcon#flushed, iclass 27, count 2 2006.231.08:13:27.99#ibcon#about to write, iclass 27, count 2 2006.231.08:13:27.99#ibcon#wrote, iclass 27, count 2 2006.231.08:13:27.99#ibcon#about to read 3, iclass 27, count 2 2006.231.08:13:28.01#ibcon#read 3, iclass 27, count 2 2006.231.08:13:28.01#ibcon#about to read 4, iclass 27, count 2 2006.231.08:13:28.01#ibcon#read 4, iclass 27, count 2 2006.231.08:13:28.01#ibcon#about to read 5, iclass 27, count 2 2006.231.08:13:28.01#ibcon#read 5, iclass 27, count 2 2006.231.08:13:28.01#ibcon#about to read 6, iclass 27, count 2 2006.231.08:13:28.01#ibcon#read 6, iclass 27, count 2 2006.231.08:13:28.01#ibcon#end of sib2, iclass 27, count 2 2006.231.08:13:28.01#ibcon#*mode == 0, iclass 27, count 2 2006.231.08:13:28.01#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.231.08:13:28.01#ibcon#[25=AT01-08\r\n] 2006.231.08:13:28.01#ibcon#*before write, iclass 27, count 2 2006.231.08:13:28.01#ibcon#enter sib2, iclass 27, count 2 2006.231.08:13:28.01#ibcon#flushed, iclass 27, count 2 2006.231.08:13:28.01#ibcon#about to write, iclass 27, count 2 2006.231.08:13:28.01#ibcon#wrote, iclass 27, count 2 2006.231.08:13:28.01#ibcon#about to read 3, iclass 27, count 2 2006.231.08:13:28.04#ibcon#read 3, iclass 27, count 2 2006.231.08:13:28.04#ibcon#about to read 4, iclass 27, count 2 2006.231.08:13:28.04#ibcon#read 4, iclass 27, count 2 2006.231.08:13:28.04#ibcon#about to read 5, iclass 27, count 2 2006.231.08:13:28.04#ibcon#read 5, iclass 27, count 2 2006.231.08:13:28.04#ibcon#about to read 6, iclass 27, count 2 2006.231.08:13:28.04#ibcon#read 6, iclass 27, count 2 2006.231.08:13:28.04#ibcon#end of sib2, iclass 27, count 2 2006.231.08:13:28.04#ibcon#*after write, iclass 27, count 2 2006.231.08:13:28.04#ibcon#*before return 0, iclass 27, count 2 2006.231.08:13:28.04#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:13:28.04#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:13:28.04#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.231.08:13:28.04#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:28.04#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:13:28.16#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:13:28.16#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:13:28.16#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:13:28.16#ibcon#first serial, iclass 27, count 0 2006.231.08:13:28.16#ibcon#enter sib2, iclass 27, count 0 2006.231.08:13:28.16#ibcon#flushed, iclass 27, count 0 2006.231.08:13:28.16#ibcon#about to write, iclass 27, count 0 2006.231.08:13:28.16#ibcon#wrote, iclass 27, count 0 2006.231.08:13:28.16#ibcon#about to read 3, iclass 27, count 0 2006.231.08:13:28.18#ibcon#read 3, iclass 27, count 0 2006.231.08:13:28.18#ibcon#about to read 4, iclass 27, count 0 2006.231.08:13:28.18#ibcon#read 4, iclass 27, count 0 2006.231.08:13:28.18#ibcon#about to read 5, iclass 27, count 0 2006.231.08:13:28.18#ibcon#read 5, iclass 27, count 0 2006.231.08:13:28.18#ibcon#about to read 6, iclass 27, count 0 2006.231.08:13:28.18#ibcon#read 6, iclass 27, count 0 2006.231.08:13:28.18#ibcon#end of sib2, iclass 27, count 0 2006.231.08:13:28.18#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:13:28.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:13:28.18#ibcon#[25=USB\r\n] 2006.231.08:13:28.18#ibcon#*before write, iclass 27, count 0 2006.231.08:13:28.18#ibcon#enter sib2, iclass 27, count 0 2006.231.08:13:28.18#ibcon#flushed, iclass 27, count 0 2006.231.08:13:28.18#ibcon#about to write, iclass 27, count 0 2006.231.08:13:28.18#ibcon#wrote, iclass 27, count 0 2006.231.08:13:28.18#ibcon#about to read 3, iclass 27, count 0 2006.231.08:13:28.22#ibcon#read 3, iclass 27, count 0 2006.231.08:13:28.22#ibcon#about to read 4, iclass 27, count 0 2006.231.08:13:28.22#ibcon#read 4, iclass 27, count 0 2006.231.08:13:28.22#ibcon#about to read 5, iclass 27, count 0 2006.231.08:13:28.22#ibcon#read 5, iclass 27, count 0 2006.231.08:13:28.22#ibcon#about to read 6, iclass 27, count 0 2006.231.08:13:28.22#ibcon#read 6, iclass 27, count 0 2006.231.08:13:28.22#ibcon#end of sib2, iclass 27, count 0 2006.231.08:13:28.22#ibcon#*after write, iclass 27, count 0 2006.231.08:13:28.22#ibcon#*before return 0, iclass 27, count 0 2006.231.08:13:28.22#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:13:28.22#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:13:28.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:13:28.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:13:28.22$vc4f8/valo=2,572.99 2006.231.08:13:28.22#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.231.08:13:28.22#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.231.08:13:28.22#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:28.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:13:28.22#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:13:28.22#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:13:28.22#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:13:28.22#ibcon#first serial, iclass 29, count 0 2006.231.08:13:28.22#ibcon#enter sib2, iclass 29, count 0 2006.231.08:13:28.22#ibcon#flushed, iclass 29, count 0 2006.231.08:13:28.22#ibcon#about to write, iclass 29, count 0 2006.231.08:13:28.22#ibcon#wrote, iclass 29, count 0 2006.231.08:13:28.22#ibcon#about to read 3, iclass 29, count 0 2006.231.08:13:28.23#ibcon#read 3, iclass 29, count 0 2006.231.08:13:28.23#ibcon#about to read 4, iclass 29, count 0 2006.231.08:13:28.23#ibcon#read 4, iclass 29, count 0 2006.231.08:13:28.23#ibcon#about to read 5, iclass 29, count 0 2006.231.08:13:28.23#ibcon#read 5, iclass 29, count 0 2006.231.08:13:28.23#ibcon#about to read 6, iclass 29, count 0 2006.231.08:13:28.23#ibcon#read 6, iclass 29, count 0 2006.231.08:13:28.23#ibcon#end of sib2, iclass 29, count 0 2006.231.08:13:28.23#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:13:28.23#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:13:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:13:28.23#ibcon#*before write, iclass 29, count 0 2006.231.08:13:28.23#ibcon#enter sib2, iclass 29, count 0 2006.231.08:13:28.23#ibcon#flushed, iclass 29, count 0 2006.231.08:13:28.23#ibcon#about to write, iclass 29, count 0 2006.231.08:13:28.23#ibcon#wrote, iclass 29, count 0 2006.231.08:13:28.23#ibcon#about to read 3, iclass 29, count 0 2006.231.08:13:28.27#ibcon#read 3, iclass 29, count 0 2006.231.08:13:28.27#ibcon#about to read 4, iclass 29, count 0 2006.231.08:13:28.27#ibcon#read 4, iclass 29, count 0 2006.231.08:13:28.27#ibcon#about to read 5, iclass 29, count 0 2006.231.08:13:28.27#ibcon#read 5, iclass 29, count 0 2006.231.08:13:28.27#ibcon#about to read 6, iclass 29, count 0 2006.231.08:13:28.27#ibcon#read 6, iclass 29, count 0 2006.231.08:13:28.27#ibcon#end of sib2, iclass 29, count 0 2006.231.08:13:28.27#ibcon#*after write, iclass 29, count 0 2006.231.08:13:28.27#ibcon#*before return 0, iclass 29, count 0 2006.231.08:13:28.27#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:13:28.27#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:13:28.27#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:13:28.27#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:13:28.27$vc4f8/va=2,7 2006.231.08:13:28.27#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.231.08:13:28.27#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.231.08:13:28.27#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:28.27#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:13:28.34#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:13:28.34#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:13:28.34#ibcon#enter wrdev, iclass 31, count 2 2006.231.08:13:28.34#ibcon#first serial, iclass 31, count 2 2006.231.08:13:28.34#ibcon#enter sib2, iclass 31, count 2 2006.231.08:13:28.34#ibcon#flushed, iclass 31, count 2 2006.231.08:13:28.34#ibcon#about to write, iclass 31, count 2 2006.231.08:13:28.34#ibcon#wrote, iclass 31, count 2 2006.231.08:13:28.34#ibcon#about to read 3, iclass 31, count 2 2006.231.08:13:28.36#ibcon#read 3, iclass 31, count 2 2006.231.08:13:28.36#ibcon#about to read 4, iclass 31, count 2 2006.231.08:13:28.36#ibcon#read 4, iclass 31, count 2 2006.231.08:13:28.36#ibcon#about to read 5, iclass 31, count 2 2006.231.08:13:28.36#ibcon#read 5, iclass 31, count 2 2006.231.08:13:28.36#ibcon#about to read 6, iclass 31, count 2 2006.231.08:13:28.36#ibcon#read 6, iclass 31, count 2 2006.231.08:13:28.36#ibcon#end of sib2, iclass 31, count 2 2006.231.08:13:28.36#ibcon#*mode == 0, iclass 31, count 2 2006.231.08:13:28.36#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.231.08:13:28.36#ibcon#[25=AT02-07\r\n] 2006.231.08:13:28.36#ibcon#*before write, iclass 31, count 2 2006.231.08:13:28.36#ibcon#enter sib2, iclass 31, count 2 2006.231.08:13:28.36#ibcon#flushed, iclass 31, count 2 2006.231.08:13:28.36#ibcon#about to write, iclass 31, count 2 2006.231.08:13:28.36#ibcon#wrote, iclass 31, count 2 2006.231.08:13:28.36#ibcon#about to read 3, iclass 31, count 2 2006.231.08:13:28.39#ibcon#read 3, iclass 31, count 2 2006.231.08:13:28.39#ibcon#about to read 4, iclass 31, count 2 2006.231.08:13:28.39#ibcon#read 4, iclass 31, count 2 2006.231.08:13:28.39#ibcon#about to read 5, iclass 31, count 2 2006.231.08:13:28.39#ibcon#read 5, iclass 31, count 2 2006.231.08:13:28.39#ibcon#about to read 6, iclass 31, count 2 2006.231.08:13:28.39#ibcon#read 6, iclass 31, count 2 2006.231.08:13:28.39#ibcon#end of sib2, iclass 31, count 2 2006.231.08:13:28.39#ibcon#*after write, iclass 31, count 2 2006.231.08:13:28.39#ibcon#*before return 0, iclass 31, count 2 2006.231.08:13:28.39#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:13:28.39#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:13:28.39#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.231.08:13:28.39#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:28.39#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:13:28.51#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:13:28.51#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:13:28.51#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:13:28.51#ibcon#first serial, iclass 31, count 0 2006.231.08:13:28.51#ibcon#enter sib2, iclass 31, count 0 2006.231.08:13:28.51#ibcon#flushed, iclass 31, count 0 2006.231.08:13:28.51#ibcon#about to write, iclass 31, count 0 2006.231.08:13:28.51#ibcon#wrote, iclass 31, count 0 2006.231.08:13:28.51#ibcon#about to read 3, iclass 31, count 0 2006.231.08:13:28.54#ibcon#read 3, iclass 31, count 0 2006.231.08:13:28.54#ibcon#about to read 4, iclass 31, count 0 2006.231.08:13:28.54#ibcon#read 4, iclass 31, count 0 2006.231.08:13:28.54#ibcon#about to read 5, iclass 31, count 0 2006.231.08:13:28.54#ibcon#read 5, iclass 31, count 0 2006.231.08:13:28.54#ibcon#about to read 6, iclass 31, count 0 2006.231.08:13:28.54#ibcon#read 6, iclass 31, count 0 2006.231.08:13:28.54#ibcon#end of sib2, iclass 31, count 0 2006.231.08:13:28.54#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:13:28.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:13:28.54#ibcon#[25=USB\r\n] 2006.231.08:13:28.54#ibcon#*before write, iclass 31, count 0 2006.231.08:13:28.54#ibcon#enter sib2, iclass 31, count 0 2006.231.08:13:28.54#ibcon#flushed, iclass 31, count 0 2006.231.08:13:28.54#ibcon#about to write, iclass 31, count 0 2006.231.08:13:28.54#ibcon#wrote, iclass 31, count 0 2006.231.08:13:28.54#ibcon#about to read 3, iclass 31, count 0 2006.231.08:13:28.57#ibcon#read 3, iclass 31, count 0 2006.231.08:13:28.57#ibcon#about to read 4, iclass 31, count 0 2006.231.08:13:28.57#ibcon#read 4, iclass 31, count 0 2006.231.08:13:28.57#ibcon#about to read 5, iclass 31, count 0 2006.231.08:13:28.57#ibcon#read 5, iclass 31, count 0 2006.231.08:13:28.57#ibcon#about to read 6, iclass 31, count 0 2006.231.08:13:28.57#ibcon#read 6, iclass 31, count 0 2006.231.08:13:28.57#ibcon#end of sib2, iclass 31, count 0 2006.231.08:13:28.57#ibcon#*after write, iclass 31, count 0 2006.231.08:13:28.57#ibcon#*before return 0, iclass 31, count 0 2006.231.08:13:28.57#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:13:28.57#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:13:28.57#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:13:28.57#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:13:28.57$vc4f8/valo=3,672.99 2006.231.08:13:28.57#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.08:13:28.57#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.08:13:28.57#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:28.57#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:13:28.57#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:13:28.57#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:13:28.57#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:13:28.57#ibcon#first serial, iclass 33, count 0 2006.231.08:13:28.57#ibcon#enter sib2, iclass 33, count 0 2006.231.08:13:28.57#ibcon#flushed, iclass 33, count 0 2006.231.08:13:28.57#ibcon#about to write, iclass 33, count 0 2006.231.08:13:28.57#ibcon#wrote, iclass 33, count 0 2006.231.08:13:28.57#ibcon#about to read 3, iclass 33, count 0 2006.231.08:13:28.59#ibcon#read 3, iclass 33, count 0 2006.231.08:13:28.59#ibcon#about to read 4, iclass 33, count 0 2006.231.08:13:28.59#ibcon#read 4, iclass 33, count 0 2006.231.08:13:28.59#ibcon#about to read 5, iclass 33, count 0 2006.231.08:13:28.59#ibcon#read 5, iclass 33, count 0 2006.231.08:13:28.59#ibcon#about to read 6, iclass 33, count 0 2006.231.08:13:28.59#ibcon#read 6, iclass 33, count 0 2006.231.08:13:28.59#ibcon#end of sib2, iclass 33, count 0 2006.231.08:13:28.59#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:13:28.59#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:13:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:13:28.59#ibcon#*before write, iclass 33, count 0 2006.231.08:13:28.59#ibcon#enter sib2, iclass 33, count 0 2006.231.08:13:28.59#ibcon#flushed, iclass 33, count 0 2006.231.08:13:28.59#ibcon#about to write, iclass 33, count 0 2006.231.08:13:28.59#ibcon#wrote, iclass 33, count 0 2006.231.08:13:28.59#ibcon#about to read 3, iclass 33, count 0 2006.231.08:13:28.63#ibcon#read 3, iclass 33, count 0 2006.231.08:13:28.63#ibcon#about to read 4, iclass 33, count 0 2006.231.08:13:28.63#ibcon#read 4, iclass 33, count 0 2006.231.08:13:28.63#ibcon#about to read 5, iclass 33, count 0 2006.231.08:13:28.63#ibcon#read 5, iclass 33, count 0 2006.231.08:13:28.63#ibcon#about to read 6, iclass 33, count 0 2006.231.08:13:28.63#ibcon#read 6, iclass 33, count 0 2006.231.08:13:28.63#ibcon#end of sib2, iclass 33, count 0 2006.231.08:13:28.63#ibcon#*after write, iclass 33, count 0 2006.231.08:13:28.63#ibcon#*before return 0, iclass 33, count 0 2006.231.08:13:28.63#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:13:28.63#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:13:28.63#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:13:28.63#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:13:28.63$vc4f8/va=3,8 2006.231.08:13:28.63#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.08:13:28.63#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.08:13:28.63#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:28.63#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:13:28.69#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:13:28.69#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:13:28.69#ibcon#enter wrdev, iclass 35, count 2 2006.231.08:13:28.69#ibcon#first serial, iclass 35, count 2 2006.231.08:13:28.69#ibcon#enter sib2, iclass 35, count 2 2006.231.08:13:28.69#ibcon#flushed, iclass 35, count 2 2006.231.08:13:28.69#ibcon#about to write, iclass 35, count 2 2006.231.08:13:28.69#ibcon#wrote, iclass 35, count 2 2006.231.08:13:28.69#ibcon#about to read 3, iclass 35, count 2 2006.231.08:13:28.71#ibcon#read 3, iclass 35, count 2 2006.231.08:13:28.71#ibcon#about to read 4, iclass 35, count 2 2006.231.08:13:28.71#ibcon#read 4, iclass 35, count 2 2006.231.08:13:28.71#ibcon#about to read 5, iclass 35, count 2 2006.231.08:13:28.71#ibcon#read 5, iclass 35, count 2 2006.231.08:13:28.71#ibcon#about to read 6, iclass 35, count 2 2006.231.08:13:28.71#ibcon#read 6, iclass 35, count 2 2006.231.08:13:28.71#ibcon#end of sib2, iclass 35, count 2 2006.231.08:13:28.71#ibcon#*mode == 0, iclass 35, count 2 2006.231.08:13:28.71#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.08:13:28.71#ibcon#[25=AT03-08\r\n] 2006.231.08:13:28.71#ibcon#*before write, iclass 35, count 2 2006.231.08:13:28.71#ibcon#enter sib2, iclass 35, count 2 2006.231.08:13:28.71#ibcon#flushed, iclass 35, count 2 2006.231.08:13:28.71#ibcon#about to write, iclass 35, count 2 2006.231.08:13:28.71#ibcon#wrote, iclass 35, count 2 2006.231.08:13:28.71#ibcon#about to read 3, iclass 35, count 2 2006.231.08:13:28.74#ibcon#read 3, iclass 35, count 2 2006.231.08:13:28.74#ibcon#about to read 4, iclass 35, count 2 2006.231.08:13:28.74#ibcon#read 4, iclass 35, count 2 2006.231.08:13:28.74#ibcon#about to read 5, iclass 35, count 2 2006.231.08:13:28.74#ibcon#read 5, iclass 35, count 2 2006.231.08:13:28.74#ibcon#about to read 6, iclass 35, count 2 2006.231.08:13:28.74#ibcon#read 6, iclass 35, count 2 2006.231.08:13:28.74#ibcon#end of sib2, iclass 35, count 2 2006.231.08:13:28.74#ibcon#*after write, iclass 35, count 2 2006.231.08:13:28.74#ibcon#*before return 0, iclass 35, count 2 2006.231.08:13:28.74#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:13:28.74#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:13:28.74#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.08:13:28.74#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:28.74#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:13:28.86#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:13:28.86#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:13:28.86#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:13:28.86#ibcon#first serial, iclass 35, count 0 2006.231.08:13:28.86#ibcon#enter sib2, iclass 35, count 0 2006.231.08:13:28.86#ibcon#flushed, iclass 35, count 0 2006.231.08:13:28.86#ibcon#about to write, iclass 35, count 0 2006.231.08:13:28.86#ibcon#wrote, iclass 35, count 0 2006.231.08:13:28.86#ibcon#about to read 3, iclass 35, count 0 2006.231.08:13:28.88#ibcon#read 3, iclass 35, count 0 2006.231.08:13:28.88#ibcon#about to read 4, iclass 35, count 0 2006.231.08:13:28.88#ibcon#read 4, iclass 35, count 0 2006.231.08:13:28.88#ibcon#about to read 5, iclass 35, count 0 2006.231.08:13:28.88#ibcon#read 5, iclass 35, count 0 2006.231.08:13:28.88#ibcon#about to read 6, iclass 35, count 0 2006.231.08:13:28.88#ibcon#read 6, iclass 35, count 0 2006.231.08:13:28.88#ibcon#end of sib2, iclass 35, count 0 2006.231.08:13:28.88#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:13:28.88#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:13:28.88#ibcon#[25=USB\r\n] 2006.231.08:13:28.88#ibcon#*before write, iclass 35, count 0 2006.231.08:13:28.88#ibcon#enter sib2, iclass 35, count 0 2006.231.08:13:28.88#ibcon#flushed, iclass 35, count 0 2006.231.08:13:28.88#ibcon#about to write, iclass 35, count 0 2006.231.08:13:28.88#ibcon#wrote, iclass 35, count 0 2006.231.08:13:28.88#ibcon#about to read 3, iclass 35, count 0 2006.231.08:13:28.91#ibcon#read 3, iclass 35, count 0 2006.231.08:13:28.91#ibcon#about to read 4, iclass 35, count 0 2006.231.08:13:28.91#ibcon#read 4, iclass 35, count 0 2006.231.08:13:28.91#ibcon#about to read 5, iclass 35, count 0 2006.231.08:13:28.91#ibcon#read 5, iclass 35, count 0 2006.231.08:13:28.91#ibcon#about to read 6, iclass 35, count 0 2006.231.08:13:28.91#ibcon#read 6, iclass 35, count 0 2006.231.08:13:28.91#ibcon#end of sib2, iclass 35, count 0 2006.231.08:13:28.91#ibcon#*after write, iclass 35, count 0 2006.231.08:13:28.91#ibcon#*before return 0, iclass 35, count 0 2006.231.08:13:28.91#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:13:28.91#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:13:28.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:13:28.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:13:28.91$vc4f8/valo=4,832.99 2006.231.08:13:28.91#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.08:13:28.91#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.08:13:28.91#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:28.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:13:28.91#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:13:28.91#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:13:28.91#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:13:28.91#ibcon#first serial, iclass 37, count 0 2006.231.08:13:28.91#ibcon#enter sib2, iclass 37, count 0 2006.231.08:13:28.91#ibcon#flushed, iclass 37, count 0 2006.231.08:13:28.91#ibcon#about to write, iclass 37, count 0 2006.231.08:13:28.91#ibcon#wrote, iclass 37, count 0 2006.231.08:13:28.91#ibcon#about to read 3, iclass 37, count 0 2006.231.08:13:28.93#ibcon#read 3, iclass 37, count 0 2006.231.08:13:28.93#ibcon#about to read 4, iclass 37, count 0 2006.231.08:13:28.93#ibcon#read 4, iclass 37, count 0 2006.231.08:13:28.93#ibcon#about to read 5, iclass 37, count 0 2006.231.08:13:28.93#ibcon#read 5, iclass 37, count 0 2006.231.08:13:28.93#ibcon#about to read 6, iclass 37, count 0 2006.231.08:13:28.93#ibcon#read 6, iclass 37, count 0 2006.231.08:13:28.93#ibcon#end of sib2, iclass 37, count 0 2006.231.08:13:28.93#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:13:28.93#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:13:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:13:28.93#ibcon#*before write, iclass 37, count 0 2006.231.08:13:28.93#ibcon#enter sib2, iclass 37, count 0 2006.231.08:13:28.93#ibcon#flushed, iclass 37, count 0 2006.231.08:13:28.93#ibcon#about to write, iclass 37, count 0 2006.231.08:13:28.93#ibcon#wrote, iclass 37, count 0 2006.231.08:13:28.93#ibcon#about to read 3, iclass 37, count 0 2006.231.08:13:28.97#ibcon#read 3, iclass 37, count 0 2006.231.08:13:28.97#ibcon#about to read 4, iclass 37, count 0 2006.231.08:13:28.97#ibcon#read 4, iclass 37, count 0 2006.231.08:13:28.97#ibcon#about to read 5, iclass 37, count 0 2006.231.08:13:28.97#ibcon#read 5, iclass 37, count 0 2006.231.08:13:28.97#ibcon#about to read 6, iclass 37, count 0 2006.231.08:13:28.97#ibcon#read 6, iclass 37, count 0 2006.231.08:13:28.97#ibcon#end of sib2, iclass 37, count 0 2006.231.08:13:28.97#ibcon#*after write, iclass 37, count 0 2006.231.08:13:28.97#ibcon#*before return 0, iclass 37, count 0 2006.231.08:13:28.97#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:13:28.97#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:13:28.97#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:13:28.97#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:13:28.97$vc4f8/va=4,7 2006.231.08:13:28.97#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.08:13:28.97#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.08:13:28.97#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:28.97#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:13:29.03#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:13:29.03#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:13:29.03#ibcon#enter wrdev, iclass 39, count 2 2006.231.08:13:29.03#ibcon#first serial, iclass 39, count 2 2006.231.08:13:29.03#ibcon#enter sib2, iclass 39, count 2 2006.231.08:13:29.03#ibcon#flushed, iclass 39, count 2 2006.231.08:13:29.03#ibcon#about to write, iclass 39, count 2 2006.231.08:13:29.03#ibcon#wrote, iclass 39, count 2 2006.231.08:13:29.03#ibcon#about to read 3, iclass 39, count 2 2006.231.08:13:29.05#ibcon#read 3, iclass 39, count 2 2006.231.08:13:29.05#ibcon#about to read 4, iclass 39, count 2 2006.231.08:13:29.05#ibcon#read 4, iclass 39, count 2 2006.231.08:13:29.05#ibcon#about to read 5, iclass 39, count 2 2006.231.08:13:29.05#ibcon#read 5, iclass 39, count 2 2006.231.08:13:29.05#ibcon#about to read 6, iclass 39, count 2 2006.231.08:13:29.05#ibcon#read 6, iclass 39, count 2 2006.231.08:13:29.05#ibcon#end of sib2, iclass 39, count 2 2006.231.08:13:29.05#ibcon#*mode == 0, iclass 39, count 2 2006.231.08:13:29.05#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.08:13:29.05#ibcon#[25=AT04-07\r\n] 2006.231.08:13:29.05#ibcon#*before write, iclass 39, count 2 2006.231.08:13:29.05#ibcon#enter sib2, iclass 39, count 2 2006.231.08:13:29.05#ibcon#flushed, iclass 39, count 2 2006.231.08:13:29.05#ibcon#about to write, iclass 39, count 2 2006.231.08:13:29.05#ibcon#wrote, iclass 39, count 2 2006.231.08:13:29.05#ibcon#about to read 3, iclass 39, count 2 2006.231.08:13:29.08#ibcon#read 3, iclass 39, count 2 2006.231.08:13:29.08#ibcon#about to read 4, iclass 39, count 2 2006.231.08:13:29.08#ibcon#read 4, iclass 39, count 2 2006.231.08:13:29.08#ibcon#about to read 5, iclass 39, count 2 2006.231.08:13:29.08#ibcon#read 5, iclass 39, count 2 2006.231.08:13:29.08#ibcon#about to read 6, iclass 39, count 2 2006.231.08:13:29.08#ibcon#read 6, iclass 39, count 2 2006.231.08:13:29.08#ibcon#end of sib2, iclass 39, count 2 2006.231.08:13:29.08#ibcon#*after write, iclass 39, count 2 2006.231.08:13:29.08#ibcon#*before return 0, iclass 39, count 2 2006.231.08:13:29.08#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:13:29.08#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:13:29.08#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.08:13:29.08#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:29.08#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:13:29.20#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:13:29.20#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:13:29.20#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:13:29.20#ibcon#first serial, iclass 39, count 0 2006.231.08:13:29.20#ibcon#enter sib2, iclass 39, count 0 2006.231.08:13:29.20#ibcon#flushed, iclass 39, count 0 2006.231.08:13:29.20#ibcon#about to write, iclass 39, count 0 2006.231.08:13:29.20#ibcon#wrote, iclass 39, count 0 2006.231.08:13:29.20#ibcon#about to read 3, iclass 39, count 0 2006.231.08:13:29.22#ibcon#read 3, iclass 39, count 0 2006.231.08:13:29.22#ibcon#about to read 4, iclass 39, count 0 2006.231.08:13:29.22#ibcon#read 4, iclass 39, count 0 2006.231.08:13:29.22#ibcon#about to read 5, iclass 39, count 0 2006.231.08:13:29.22#ibcon#read 5, iclass 39, count 0 2006.231.08:13:29.22#ibcon#about to read 6, iclass 39, count 0 2006.231.08:13:29.22#ibcon#read 6, iclass 39, count 0 2006.231.08:13:29.22#ibcon#end of sib2, iclass 39, count 0 2006.231.08:13:29.22#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:13:29.22#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:13:29.22#ibcon#[25=USB\r\n] 2006.231.08:13:29.22#ibcon#*before write, iclass 39, count 0 2006.231.08:13:29.22#ibcon#enter sib2, iclass 39, count 0 2006.231.08:13:29.22#ibcon#flushed, iclass 39, count 0 2006.231.08:13:29.22#ibcon#about to write, iclass 39, count 0 2006.231.08:13:29.22#ibcon#wrote, iclass 39, count 0 2006.231.08:13:29.22#ibcon#about to read 3, iclass 39, count 0 2006.231.08:13:29.25#ibcon#read 3, iclass 39, count 0 2006.231.08:13:29.25#ibcon#about to read 4, iclass 39, count 0 2006.231.08:13:29.25#ibcon#read 4, iclass 39, count 0 2006.231.08:13:29.25#ibcon#about to read 5, iclass 39, count 0 2006.231.08:13:29.25#ibcon#read 5, iclass 39, count 0 2006.231.08:13:29.25#ibcon#about to read 6, iclass 39, count 0 2006.231.08:13:29.25#ibcon#read 6, iclass 39, count 0 2006.231.08:13:29.25#ibcon#end of sib2, iclass 39, count 0 2006.231.08:13:29.25#ibcon#*after write, iclass 39, count 0 2006.231.08:13:29.25#ibcon#*before return 0, iclass 39, count 0 2006.231.08:13:29.25#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:13:29.25#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:13:29.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:13:29.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:13:29.25$vc4f8/valo=5,652.99 2006.231.08:13:29.25#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.08:13:29.25#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.08:13:29.25#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:29.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:13:29.25#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:13:29.25#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:13:29.25#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:13:29.25#ibcon#first serial, iclass 3, count 0 2006.231.08:13:29.25#ibcon#enter sib2, iclass 3, count 0 2006.231.08:13:29.25#ibcon#flushed, iclass 3, count 0 2006.231.08:13:29.25#ibcon#about to write, iclass 3, count 0 2006.231.08:13:29.25#ibcon#wrote, iclass 3, count 0 2006.231.08:13:29.25#ibcon#about to read 3, iclass 3, count 0 2006.231.08:13:29.27#ibcon#read 3, iclass 3, count 0 2006.231.08:13:29.27#ibcon#about to read 4, iclass 3, count 0 2006.231.08:13:29.27#ibcon#read 4, iclass 3, count 0 2006.231.08:13:29.27#ibcon#about to read 5, iclass 3, count 0 2006.231.08:13:29.27#ibcon#read 5, iclass 3, count 0 2006.231.08:13:29.27#ibcon#about to read 6, iclass 3, count 0 2006.231.08:13:29.27#ibcon#read 6, iclass 3, count 0 2006.231.08:13:29.27#ibcon#end of sib2, iclass 3, count 0 2006.231.08:13:29.27#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:13:29.27#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:13:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:13:29.27#ibcon#*before write, iclass 3, count 0 2006.231.08:13:29.27#ibcon#enter sib2, iclass 3, count 0 2006.231.08:13:29.27#ibcon#flushed, iclass 3, count 0 2006.231.08:13:29.27#ibcon#about to write, iclass 3, count 0 2006.231.08:13:29.27#ibcon#wrote, iclass 3, count 0 2006.231.08:13:29.27#ibcon#about to read 3, iclass 3, count 0 2006.231.08:13:29.31#ibcon#read 3, iclass 3, count 0 2006.231.08:13:29.31#ibcon#about to read 4, iclass 3, count 0 2006.231.08:13:29.31#ibcon#read 4, iclass 3, count 0 2006.231.08:13:29.31#ibcon#about to read 5, iclass 3, count 0 2006.231.08:13:29.31#ibcon#read 5, iclass 3, count 0 2006.231.08:13:29.31#ibcon#about to read 6, iclass 3, count 0 2006.231.08:13:29.31#ibcon#read 6, iclass 3, count 0 2006.231.08:13:29.31#ibcon#end of sib2, iclass 3, count 0 2006.231.08:13:29.31#ibcon#*after write, iclass 3, count 0 2006.231.08:13:29.31#ibcon#*before return 0, iclass 3, count 0 2006.231.08:13:29.31#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:13:29.31#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:13:29.31#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:13:29.31#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:13:29.31$vc4f8/va=5,7 2006.231.08:13:29.31#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.08:13:29.31#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.08:13:29.31#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:29.31#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:13:29.37#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:13:29.37#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:13:29.37#ibcon#enter wrdev, iclass 5, count 2 2006.231.08:13:29.37#ibcon#first serial, iclass 5, count 2 2006.231.08:13:29.37#ibcon#enter sib2, iclass 5, count 2 2006.231.08:13:29.37#ibcon#flushed, iclass 5, count 2 2006.231.08:13:29.37#ibcon#about to write, iclass 5, count 2 2006.231.08:13:29.37#ibcon#wrote, iclass 5, count 2 2006.231.08:13:29.37#ibcon#about to read 3, iclass 5, count 2 2006.231.08:13:29.40#ibcon#read 3, iclass 5, count 2 2006.231.08:13:29.40#ibcon#about to read 4, iclass 5, count 2 2006.231.08:13:29.40#ibcon#read 4, iclass 5, count 2 2006.231.08:13:29.40#ibcon#about to read 5, iclass 5, count 2 2006.231.08:13:29.40#ibcon#read 5, iclass 5, count 2 2006.231.08:13:29.40#ibcon#about to read 6, iclass 5, count 2 2006.231.08:13:29.40#ibcon#read 6, iclass 5, count 2 2006.231.08:13:29.40#ibcon#end of sib2, iclass 5, count 2 2006.231.08:13:29.40#ibcon#*mode == 0, iclass 5, count 2 2006.231.08:13:29.40#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.08:13:29.40#ibcon#[25=AT05-07\r\n] 2006.231.08:13:29.40#ibcon#*before write, iclass 5, count 2 2006.231.08:13:29.40#ibcon#enter sib2, iclass 5, count 2 2006.231.08:13:29.40#ibcon#flushed, iclass 5, count 2 2006.231.08:13:29.40#ibcon#about to write, iclass 5, count 2 2006.231.08:13:29.40#ibcon#wrote, iclass 5, count 2 2006.231.08:13:29.40#ibcon#about to read 3, iclass 5, count 2 2006.231.08:13:29.43#ibcon#read 3, iclass 5, count 2 2006.231.08:13:29.43#ibcon#about to read 4, iclass 5, count 2 2006.231.08:13:29.43#ibcon#read 4, iclass 5, count 2 2006.231.08:13:29.43#ibcon#about to read 5, iclass 5, count 2 2006.231.08:13:29.43#ibcon#read 5, iclass 5, count 2 2006.231.08:13:29.43#ibcon#about to read 6, iclass 5, count 2 2006.231.08:13:29.43#ibcon#read 6, iclass 5, count 2 2006.231.08:13:29.43#ibcon#end of sib2, iclass 5, count 2 2006.231.08:13:29.43#ibcon#*after write, iclass 5, count 2 2006.231.08:13:29.43#ibcon#*before return 0, iclass 5, count 2 2006.231.08:13:29.43#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:13:29.43#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:13:29.43#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.08:13:29.43#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:29.43#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:13:29.55#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:13:29.55#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:13:29.55#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:13:29.55#ibcon#first serial, iclass 5, count 0 2006.231.08:13:29.55#ibcon#enter sib2, iclass 5, count 0 2006.231.08:13:29.55#ibcon#flushed, iclass 5, count 0 2006.231.08:13:29.55#ibcon#about to write, iclass 5, count 0 2006.231.08:13:29.55#ibcon#wrote, iclass 5, count 0 2006.231.08:13:29.55#ibcon#about to read 3, iclass 5, count 0 2006.231.08:13:29.57#ibcon#read 3, iclass 5, count 0 2006.231.08:13:29.57#ibcon#about to read 4, iclass 5, count 0 2006.231.08:13:29.57#ibcon#read 4, iclass 5, count 0 2006.231.08:13:29.57#ibcon#about to read 5, iclass 5, count 0 2006.231.08:13:29.57#ibcon#read 5, iclass 5, count 0 2006.231.08:13:29.57#ibcon#about to read 6, iclass 5, count 0 2006.231.08:13:29.57#ibcon#read 6, iclass 5, count 0 2006.231.08:13:29.57#ibcon#end of sib2, iclass 5, count 0 2006.231.08:13:29.57#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:13:29.57#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:13:29.57#ibcon#[25=USB\r\n] 2006.231.08:13:29.57#ibcon#*before write, iclass 5, count 0 2006.231.08:13:29.57#ibcon#enter sib2, iclass 5, count 0 2006.231.08:13:29.57#ibcon#flushed, iclass 5, count 0 2006.231.08:13:29.57#ibcon#about to write, iclass 5, count 0 2006.231.08:13:29.57#ibcon#wrote, iclass 5, count 0 2006.231.08:13:29.57#ibcon#about to read 3, iclass 5, count 0 2006.231.08:13:29.60#ibcon#read 3, iclass 5, count 0 2006.231.08:13:29.60#ibcon#about to read 4, iclass 5, count 0 2006.231.08:13:29.60#ibcon#read 4, iclass 5, count 0 2006.231.08:13:29.60#ibcon#about to read 5, iclass 5, count 0 2006.231.08:13:29.60#ibcon#read 5, iclass 5, count 0 2006.231.08:13:29.60#ibcon#about to read 6, iclass 5, count 0 2006.231.08:13:29.60#ibcon#read 6, iclass 5, count 0 2006.231.08:13:29.60#ibcon#end of sib2, iclass 5, count 0 2006.231.08:13:29.60#ibcon#*after write, iclass 5, count 0 2006.231.08:13:29.60#ibcon#*before return 0, iclass 5, count 0 2006.231.08:13:29.60#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:13:29.60#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:13:29.60#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:13:29.60#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:13:29.60$vc4f8/valo=6,772.99 2006.231.08:13:29.60#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.08:13:29.60#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.08:13:29.60#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:29.60#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:13:29.60#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:13:29.60#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:13:29.60#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:13:29.60#ibcon#first serial, iclass 7, count 0 2006.231.08:13:29.60#ibcon#enter sib2, iclass 7, count 0 2006.231.08:13:29.60#ibcon#flushed, iclass 7, count 0 2006.231.08:13:29.60#ibcon#about to write, iclass 7, count 0 2006.231.08:13:29.60#ibcon#wrote, iclass 7, count 0 2006.231.08:13:29.60#ibcon#about to read 3, iclass 7, count 0 2006.231.08:13:29.62#ibcon#read 3, iclass 7, count 0 2006.231.08:13:29.62#ibcon#about to read 4, iclass 7, count 0 2006.231.08:13:29.62#ibcon#read 4, iclass 7, count 0 2006.231.08:13:29.62#ibcon#about to read 5, iclass 7, count 0 2006.231.08:13:29.62#ibcon#read 5, iclass 7, count 0 2006.231.08:13:29.62#ibcon#about to read 6, iclass 7, count 0 2006.231.08:13:29.62#ibcon#read 6, iclass 7, count 0 2006.231.08:13:29.62#ibcon#end of sib2, iclass 7, count 0 2006.231.08:13:29.62#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:13:29.62#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:13:29.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:13:29.62#ibcon#*before write, iclass 7, count 0 2006.231.08:13:29.62#ibcon#enter sib2, iclass 7, count 0 2006.231.08:13:29.62#ibcon#flushed, iclass 7, count 0 2006.231.08:13:29.62#ibcon#about to write, iclass 7, count 0 2006.231.08:13:29.62#ibcon#wrote, iclass 7, count 0 2006.231.08:13:29.62#ibcon#about to read 3, iclass 7, count 0 2006.231.08:13:29.66#ibcon#read 3, iclass 7, count 0 2006.231.08:13:29.66#ibcon#about to read 4, iclass 7, count 0 2006.231.08:13:29.66#ibcon#read 4, iclass 7, count 0 2006.231.08:13:29.66#ibcon#about to read 5, iclass 7, count 0 2006.231.08:13:29.66#ibcon#read 5, iclass 7, count 0 2006.231.08:13:29.66#ibcon#about to read 6, iclass 7, count 0 2006.231.08:13:29.66#ibcon#read 6, iclass 7, count 0 2006.231.08:13:29.66#ibcon#end of sib2, iclass 7, count 0 2006.231.08:13:29.66#ibcon#*after write, iclass 7, count 0 2006.231.08:13:29.66#ibcon#*before return 0, iclass 7, count 0 2006.231.08:13:29.66#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:13:29.66#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:13:29.66#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:13:29.66#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:13:29.66$vc4f8/va=6,6 2006.231.08:13:29.66#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.08:13:29.66#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.08:13:29.66#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:29.66#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:13:29.72#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:13:29.72#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:13:29.72#ibcon#enter wrdev, iclass 11, count 2 2006.231.08:13:29.72#ibcon#first serial, iclass 11, count 2 2006.231.08:13:29.72#ibcon#enter sib2, iclass 11, count 2 2006.231.08:13:29.72#ibcon#flushed, iclass 11, count 2 2006.231.08:13:29.72#ibcon#about to write, iclass 11, count 2 2006.231.08:13:29.72#ibcon#wrote, iclass 11, count 2 2006.231.08:13:29.72#ibcon#about to read 3, iclass 11, count 2 2006.231.08:13:29.74#ibcon#read 3, iclass 11, count 2 2006.231.08:13:29.74#ibcon#about to read 4, iclass 11, count 2 2006.231.08:13:29.74#ibcon#read 4, iclass 11, count 2 2006.231.08:13:29.74#ibcon#about to read 5, iclass 11, count 2 2006.231.08:13:29.74#ibcon#read 5, iclass 11, count 2 2006.231.08:13:29.74#ibcon#about to read 6, iclass 11, count 2 2006.231.08:13:29.74#ibcon#read 6, iclass 11, count 2 2006.231.08:13:29.74#ibcon#end of sib2, iclass 11, count 2 2006.231.08:13:29.74#ibcon#*mode == 0, iclass 11, count 2 2006.231.08:13:29.74#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.08:13:29.74#ibcon#[25=AT06-06\r\n] 2006.231.08:13:29.74#ibcon#*before write, iclass 11, count 2 2006.231.08:13:29.74#ibcon#enter sib2, iclass 11, count 2 2006.231.08:13:29.74#ibcon#flushed, iclass 11, count 2 2006.231.08:13:29.74#ibcon#about to write, iclass 11, count 2 2006.231.08:13:29.74#ibcon#wrote, iclass 11, count 2 2006.231.08:13:29.74#ibcon#about to read 3, iclass 11, count 2 2006.231.08:13:29.77#ibcon#read 3, iclass 11, count 2 2006.231.08:13:29.77#ibcon#about to read 4, iclass 11, count 2 2006.231.08:13:29.77#ibcon#read 4, iclass 11, count 2 2006.231.08:13:29.77#ibcon#about to read 5, iclass 11, count 2 2006.231.08:13:29.77#ibcon#read 5, iclass 11, count 2 2006.231.08:13:29.77#ibcon#about to read 6, iclass 11, count 2 2006.231.08:13:29.77#ibcon#read 6, iclass 11, count 2 2006.231.08:13:29.77#ibcon#end of sib2, iclass 11, count 2 2006.231.08:13:29.77#ibcon#*after write, iclass 11, count 2 2006.231.08:13:29.77#ibcon#*before return 0, iclass 11, count 2 2006.231.08:13:29.77#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:13:29.77#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:13:29.77#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.08:13:29.77#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:29.77#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:13:29.89#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:13:29.89#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:13:29.89#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:13:29.89#ibcon#first serial, iclass 11, count 0 2006.231.08:13:29.89#ibcon#enter sib2, iclass 11, count 0 2006.231.08:13:29.89#ibcon#flushed, iclass 11, count 0 2006.231.08:13:29.89#ibcon#about to write, iclass 11, count 0 2006.231.08:13:29.89#ibcon#wrote, iclass 11, count 0 2006.231.08:13:29.89#ibcon#about to read 3, iclass 11, count 0 2006.231.08:13:29.91#ibcon#read 3, iclass 11, count 0 2006.231.08:13:29.91#ibcon#about to read 4, iclass 11, count 0 2006.231.08:13:29.91#ibcon#read 4, iclass 11, count 0 2006.231.08:13:29.91#ibcon#about to read 5, iclass 11, count 0 2006.231.08:13:29.91#ibcon#read 5, iclass 11, count 0 2006.231.08:13:29.91#ibcon#about to read 6, iclass 11, count 0 2006.231.08:13:29.91#ibcon#read 6, iclass 11, count 0 2006.231.08:13:29.91#ibcon#end of sib2, iclass 11, count 0 2006.231.08:13:29.91#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:13:29.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:13:29.91#ibcon#[25=USB\r\n] 2006.231.08:13:29.91#ibcon#*before write, iclass 11, count 0 2006.231.08:13:29.91#ibcon#enter sib2, iclass 11, count 0 2006.231.08:13:29.91#ibcon#flushed, iclass 11, count 0 2006.231.08:13:29.91#ibcon#about to write, iclass 11, count 0 2006.231.08:13:29.91#ibcon#wrote, iclass 11, count 0 2006.231.08:13:29.91#ibcon#about to read 3, iclass 11, count 0 2006.231.08:13:29.94#ibcon#read 3, iclass 11, count 0 2006.231.08:13:29.94#ibcon#about to read 4, iclass 11, count 0 2006.231.08:13:29.94#ibcon#read 4, iclass 11, count 0 2006.231.08:13:29.94#ibcon#about to read 5, iclass 11, count 0 2006.231.08:13:29.94#ibcon#read 5, iclass 11, count 0 2006.231.08:13:29.94#ibcon#about to read 6, iclass 11, count 0 2006.231.08:13:29.94#ibcon#read 6, iclass 11, count 0 2006.231.08:13:29.94#ibcon#end of sib2, iclass 11, count 0 2006.231.08:13:29.94#ibcon#*after write, iclass 11, count 0 2006.231.08:13:29.94#ibcon#*before return 0, iclass 11, count 0 2006.231.08:13:29.94#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:13:29.94#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:13:29.94#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:13:29.94#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:13:29.94$vc4f8/valo=7,832.99 2006.231.08:13:29.94#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.08:13:29.94#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.08:13:29.94#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:29.94#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:13:29.94#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:13:29.94#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:13:29.94#ibcon#enter wrdev, iclass 13, count 0 2006.231.08:13:29.94#ibcon#first serial, iclass 13, count 0 2006.231.08:13:29.94#ibcon#enter sib2, iclass 13, count 0 2006.231.08:13:29.94#ibcon#flushed, iclass 13, count 0 2006.231.08:13:29.94#ibcon#about to write, iclass 13, count 0 2006.231.08:13:29.94#ibcon#wrote, iclass 13, count 0 2006.231.08:13:29.94#ibcon#about to read 3, iclass 13, count 0 2006.231.08:13:29.96#ibcon#read 3, iclass 13, count 0 2006.231.08:13:29.96#ibcon#about to read 4, iclass 13, count 0 2006.231.08:13:29.96#ibcon#read 4, iclass 13, count 0 2006.231.08:13:29.96#ibcon#about to read 5, iclass 13, count 0 2006.231.08:13:29.96#ibcon#read 5, iclass 13, count 0 2006.231.08:13:29.96#ibcon#about to read 6, iclass 13, count 0 2006.231.08:13:29.96#ibcon#read 6, iclass 13, count 0 2006.231.08:13:29.96#ibcon#end of sib2, iclass 13, count 0 2006.231.08:13:29.96#ibcon#*mode == 0, iclass 13, count 0 2006.231.08:13:29.96#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.08:13:29.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:13:29.96#ibcon#*before write, iclass 13, count 0 2006.231.08:13:29.96#ibcon#enter sib2, iclass 13, count 0 2006.231.08:13:29.96#ibcon#flushed, iclass 13, count 0 2006.231.08:13:29.96#ibcon#about to write, iclass 13, count 0 2006.231.08:13:29.96#ibcon#wrote, iclass 13, count 0 2006.231.08:13:29.96#ibcon#about to read 3, iclass 13, count 0 2006.231.08:13:30.00#ibcon#read 3, iclass 13, count 0 2006.231.08:13:30.00#ibcon#about to read 4, iclass 13, count 0 2006.231.08:13:30.00#ibcon#read 4, iclass 13, count 0 2006.231.08:13:30.00#ibcon#about to read 5, iclass 13, count 0 2006.231.08:13:30.00#ibcon#read 5, iclass 13, count 0 2006.231.08:13:30.00#ibcon#about to read 6, iclass 13, count 0 2006.231.08:13:30.00#ibcon#read 6, iclass 13, count 0 2006.231.08:13:30.00#ibcon#end of sib2, iclass 13, count 0 2006.231.08:13:30.00#ibcon#*after write, iclass 13, count 0 2006.231.08:13:30.00#ibcon#*before return 0, iclass 13, count 0 2006.231.08:13:30.00#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:13:30.00#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:13:30.00#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.08:13:30.00#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.08:13:30.00$vc4f8/va=7,6 2006.231.08:13:30.00#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.08:13:30.00#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.08:13:30.00#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:30.00#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:13:30.06#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:13:30.06#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:13:30.06#ibcon#enter wrdev, iclass 15, count 2 2006.231.08:13:30.06#ibcon#first serial, iclass 15, count 2 2006.231.08:13:30.06#ibcon#enter sib2, iclass 15, count 2 2006.231.08:13:30.06#ibcon#flushed, iclass 15, count 2 2006.231.08:13:30.06#ibcon#about to write, iclass 15, count 2 2006.231.08:13:30.06#ibcon#wrote, iclass 15, count 2 2006.231.08:13:30.06#ibcon#about to read 3, iclass 15, count 2 2006.231.08:13:30.08#ibcon#read 3, iclass 15, count 2 2006.231.08:13:30.08#ibcon#about to read 4, iclass 15, count 2 2006.231.08:13:30.08#ibcon#read 4, iclass 15, count 2 2006.231.08:13:30.08#ibcon#about to read 5, iclass 15, count 2 2006.231.08:13:30.08#ibcon#read 5, iclass 15, count 2 2006.231.08:13:30.08#ibcon#about to read 6, iclass 15, count 2 2006.231.08:13:30.08#ibcon#read 6, iclass 15, count 2 2006.231.08:13:30.08#ibcon#end of sib2, iclass 15, count 2 2006.231.08:13:30.08#ibcon#*mode == 0, iclass 15, count 2 2006.231.08:13:30.08#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.08:13:30.08#ibcon#[25=AT07-06\r\n] 2006.231.08:13:30.08#ibcon#*before write, iclass 15, count 2 2006.231.08:13:30.08#ibcon#enter sib2, iclass 15, count 2 2006.231.08:13:30.08#ibcon#flushed, iclass 15, count 2 2006.231.08:13:30.08#ibcon#about to write, iclass 15, count 2 2006.231.08:13:30.08#ibcon#wrote, iclass 15, count 2 2006.231.08:13:30.08#ibcon#about to read 3, iclass 15, count 2 2006.231.08:13:30.11#ibcon#read 3, iclass 15, count 2 2006.231.08:13:30.11#ibcon#about to read 4, iclass 15, count 2 2006.231.08:13:30.11#ibcon#read 4, iclass 15, count 2 2006.231.08:13:30.11#ibcon#about to read 5, iclass 15, count 2 2006.231.08:13:30.11#ibcon#read 5, iclass 15, count 2 2006.231.08:13:30.11#ibcon#about to read 6, iclass 15, count 2 2006.231.08:13:30.11#ibcon#read 6, iclass 15, count 2 2006.231.08:13:30.11#ibcon#end of sib2, iclass 15, count 2 2006.231.08:13:30.11#ibcon#*after write, iclass 15, count 2 2006.231.08:13:30.11#ibcon#*before return 0, iclass 15, count 2 2006.231.08:13:30.11#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:13:30.11#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:13:30.11#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.08:13:30.11#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:30.11#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:13:30.23#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:13:30.23#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:13:30.23#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:13:30.23#ibcon#first serial, iclass 15, count 0 2006.231.08:13:30.23#ibcon#enter sib2, iclass 15, count 0 2006.231.08:13:30.23#ibcon#flushed, iclass 15, count 0 2006.231.08:13:30.23#ibcon#about to write, iclass 15, count 0 2006.231.08:13:30.23#ibcon#wrote, iclass 15, count 0 2006.231.08:13:30.23#ibcon#about to read 3, iclass 15, count 0 2006.231.08:13:30.25#ibcon#read 3, iclass 15, count 0 2006.231.08:13:30.25#ibcon#about to read 4, iclass 15, count 0 2006.231.08:13:30.25#ibcon#read 4, iclass 15, count 0 2006.231.08:13:30.25#ibcon#about to read 5, iclass 15, count 0 2006.231.08:13:30.25#ibcon#read 5, iclass 15, count 0 2006.231.08:13:30.25#ibcon#about to read 6, iclass 15, count 0 2006.231.08:13:30.25#ibcon#read 6, iclass 15, count 0 2006.231.08:13:30.25#ibcon#end of sib2, iclass 15, count 0 2006.231.08:13:30.25#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:13:30.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:13:30.25#ibcon#[25=USB\r\n] 2006.231.08:13:30.25#ibcon#*before write, iclass 15, count 0 2006.231.08:13:30.25#ibcon#enter sib2, iclass 15, count 0 2006.231.08:13:30.25#ibcon#flushed, iclass 15, count 0 2006.231.08:13:30.25#ibcon#about to write, iclass 15, count 0 2006.231.08:13:30.25#ibcon#wrote, iclass 15, count 0 2006.231.08:13:30.25#ibcon#about to read 3, iclass 15, count 0 2006.231.08:13:30.28#ibcon#read 3, iclass 15, count 0 2006.231.08:13:30.28#ibcon#about to read 4, iclass 15, count 0 2006.231.08:13:30.28#ibcon#read 4, iclass 15, count 0 2006.231.08:13:30.28#ibcon#about to read 5, iclass 15, count 0 2006.231.08:13:30.28#ibcon#read 5, iclass 15, count 0 2006.231.08:13:30.28#ibcon#about to read 6, iclass 15, count 0 2006.231.08:13:30.28#ibcon#read 6, iclass 15, count 0 2006.231.08:13:30.28#ibcon#end of sib2, iclass 15, count 0 2006.231.08:13:30.28#ibcon#*after write, iclass 15, count 0 2006.231.08:13:30.28#ibcon#*before return 0, iclass 15, count 0 2006.231.08:13:30.28#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:13:30.28#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:13:30.28#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:13:30.28#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:13:30.28$vc4f8/valo=8,852.99 2006.231.08:13:30.28#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.08:13:30.28#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.08:13:30.28#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:30.28#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:13:30.28#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:13:30.28#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:13:30.28#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:13:30.28#ibcon#first serial, iclass 17, count 0 2006.231.08:13:30.28#ibcon#enter sib2, iclass 17, count 0 2006.231.08:13:30.28#ibcon#flushed, iclass 17, count 0 2006.231.08:13:30.28#ibcon#about to write, iclass 17, count 0 2006.231.08:13:30.28#ibcon#wrote, iclass 17, count 0 2006.231.08:13:30.28#ibcon#about to read 3, iclass 17, count 0 2006.231.08:13:30.31#ibcon#read 3, iclass 17, count 0 2006.231.08:13:30.31#ibcon#about to read 4, iclass 17, count 0 2006.231.08:13:30.31#ibcon#read 4, iclass 17, count 0 2006.231.08:13:30.31#ibcon#about to read 5, iclass 17, count 0 2006.231.08:13:30.31#ibcon#read 5, iclass 17, count 0 2006.231.08:13:30.31#ibcon#about to read 6, iclass 17, count 0 2006.231.08:13:30.31#ibcon#read 6, iclass 17, count 0 2006.231.08:13:30.31#ibcon#end of sib2, iclass 17, count 0 2006.231.08:13:30.31#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:13:30.31#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:13:30.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:13:30.31#ibcon#*before write, iclass 17, count 0 2006.231.08:13:30.31#ibcon#enter sib2, iclass 17, count 0 2006.231.08:13:30.31#ibcon#flushed, iclass 17, count 0 2006.231.08:13:30.31#ibcon#about to write, iclass 17, count 0 2006.231.08:13:30.31#ibcon#wrote, iclass 17, count 0 2006.231.08:13:30.31#ibcon#about to read 3, iclass 17, count 0 2006.231.08:13:30.34#ibcon#read 3, iclass 17, count 0 2006.231.08:13:30.34#ibcon#about to read 4, iclass 17, count 0 2006.231.08:13:30.34#ibcon#read 4, iclass 17, count 0 2006.231.08:13:30.34#ibcon#about to read 5, iclass 17, count 0 2006.231.08:13:30.34#ibcon#read 5, iclass 17, count 0 2006.231.08:13:30.34#ibcon#about to read 6, iclass 17, count 0 2006.231.08:13:30.34#ibcon#read 6, iclass 17, count 0 2006.231.08:13:30.34#ibcon#end of sib2, iclass 17, count 0 2006.231.08:13:30.34#ibcon#*after write, iclass 17, count 0 2006.231.08:13:30.34#ibcon#*before return 0, iclass 17, count 0 2006.231.08:13:30.34#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:13:30.34#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:13:30.34#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:13:30.34#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:13:30.34$vc4f8/va=8,6 2006.231.08:13:30.34#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.231.08:13:30.34#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.231.08:13:30.34#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:30.34#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:13:30.40#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:13:30.40#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:13:30.40#ibcon#enter wrdev, iclass 19, count 2 2006.231.08:13:30.40#ibcon#first serial, iclass 19, count 2 2006.231.08:13:30.40#ibcon#enter sib2, iclass 19, count 2 2006.231.08:13:30.40#ibcon#flushed, iclass 19, count 2 2006.231.08:13:30.40#ibcon#about to write, iclass 19, count 2 2006.231.08:13:30.40#ibcon#wrote, iclass 19, count 2 2006.231.08:13:30.40#ibcon#about to read 3, iclass 19, count 2 2006.231.08:13:30.42#ibcon#read 3, iclass 19, count 2 2006.231.08:13:30.42#ibcon#about to read 4, iclass 19, count 2 2006.231.08:13:30.42#ibcon#read 4, iclass 19, count 2 2006.231.08:13:30.42#ibcon#about to read 5, iclass 19, count 2 2006.231.08:13:30.42#ibcon#read 5, iclass 19, count 2 2006.231.08:13:30.42#ibcon#about to read 6, iclass 19, count 2 2006.231.08:13:30.42#ibcon#read 6, iclass 19, count 2 2006.231.08:13:30.42#ibcon#end of sib2, iclass 19, count 2 2006.231.08:13:30.42#ibcon#*mode == 0, iclass 19, count 2 2006.231.08:13:30.42#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.231.08:13:30.42#ibcon#[25=AT08-06\r\n] 2006.231.08:13:30.42#ibcon#*before write, iclass 19, count 2 2006.231.08:13:30.42#ibcon#enter sib2, iclass 19, count 2 2006.231.08:13:30.42#ibcon#flushed, iclass 19, count 2 2006.231.08:13:30.42#ibcon#about to write, iclass 19, count 2 2006.231.08:13:30.42#ibcon#wrote, iclass 19, count 2 2006.231.08:13:30.42#ibcon#about to read 3, iclass 19, count 2 2006.231.08:13:30.45#ibcon#read 3, iclass 19, count 2 2006.231.08:13:30.45#ibcon#about to read 4, iclass 19, count 2 2006.231.08:13:30.45#ibcon#read 4, iclass 19, count 2 2006.231.08:13:30.45#ibcon#about to read 5, iclass 19, count 2 2006.231.08:13:30.45#ibcon#read 5, iclass 19, count 2 2006.231.08:13:30.45#ibcon#about to read 6, iclass 19, count 2 2006.231.08:13:30.45#ibcon#read 6, iclass 19, count 2 2006.231.08:13:30.45#ibcon#end of sib2, iclass 19, count 2 2006.231.08:13:30.45#ibcon#*after write, iclass 19, count 2 2006.231.08:13:30.45#ibcon#*before return 0, iclass 19, count 2 2006.231.08:13:30.45#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:13:30.45#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:13:30.45#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.231.08:13:30.45#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:30.45#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:13:30.57#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:13:30.57#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:13:30.57#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:13:30.57#ibcon#first serial, iclass 19, count 0 2006.231.08:13:30.57#ibcon#enter sib2, iclass 19, count 0 2006.231.08:13:30.57#ibcon#flushed, iclass 19, count 0 2006.231.08:13:30.57#ibcon#about to write, iclass 19, count 0 2006.231.08:13:30.57#ibcon#wrote, iclass 19, count 0 2006.231.08:13:30.57#ibcon#about to read 3, iclass 19, count 0 2006.231.08:13:30.59#ibcon#read 3, iclass 19, count 0 2006.231.08:13:30.59#ibcon#about to read 4, iclass 19, count 0 2006.231.08:13:30.59#ibcon#read 4, iclass 19, count 0 2006.231.08:13:30.59#ibcon#about to read 5, iclass 19, count 0 2006.231.08:13:30.59#ibcon#read 5, iclass 19, count 0 2006.231.08:13:30.59#ibcon#about to read 6, iclass 19, count 0 2006.231.08:13:30.59#ibcon#read 6, iclass 19, count 0 2006.231.08:13:30.59#ibcon#end of sib2, iclass 19, count 0 2006.231.08:13:30.59#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:13:30.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:13:30.59#ibcon#[25=USB\r\n] 2006.231.08:13:30.59#ibcon#*before write, iclass 19, count 0 2006.231.08:13:30.59#ibcon#enter sib2, iclass 19, count 0 2006.231.08:13:30.59#ibcon#flushed, iclass 19, count 0 2006.231.08:13:30.59#ibcon#about to write, iclass 19, count 0 2006.231.08:13:30.59#ibcon#wrote, iclass 19, count 0 2006.231.08:13:30.59#ibcon#about to read 3, iclass 19, count 0 2006.231.08:13:30.62#ibcon#read 3, iclass 19, count 0 2006.231.08:13:30.62#ibcon#about to read 4, iclass 19, count 0 2006.231.08:13:30.62#ibcon#read 4, iclass 19, count 0 2006.231.08:13:30.62#ibcon#about to read 5, iclass 19, count 0 2006.231.08:13:30.62#ibcon#read 5, iclass 19, count 0 2006.231.08:13:30.62#ibcon#about to read 6, iclass 19, count 0 2006.231.08:13:30.62#ibcon#read 6, iclass 19, count 0 2006.231.08:13:30.62#ibcon#end of sib2, iclass 19, count 0 2006.231.08:13:30.62#ibcon#*after write, iclass 19, count 0 2006.231.08:13:30.62#ibcon#*before return 0, iclass 19, count 0 2006.231.08:13:30.62#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:13:30.62#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:13:30.62#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:13:30.62#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:13:30.62$vc4f8/vblo=1,632.99 2006.231.08:13:30.62#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.08:13:30.62#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.08:13:30.62#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:30.62#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:13:30.62#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:13:30.62#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:13:30.62#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:13:30.62#ibcon#first serial, iclass 21, count 0 2006.231.08:13:30.62#ibcon#enter sib2, iclass 21, count 0 2006.231.08:13:30.62#ibcon#flushed, iclass 21, count 0 2006.231.08:13:30.62#ibcon#about to write, iclass 21, count 0 2006.231.08:13:30.62#ibcon#wrote, iclass 21, count 0 2006.231.08:13:30.62#ibcon#about to read 3, iclass 21, count 0 2006.231.08:13:30.64#ibcon#read 3, iclass 21, count 0 2006.231.08:13:30.64#ibcon#about to read 4, iclass 21, count 0 2006.231.08:13:30.64#ibcon#read 4, iclass 21, count 0 2006.231.08:13:30.64#ibcon#about to read 5, iclass 21, count 0 2006.231.08:13:30.64#ibcon#read 5, iclass 21, count 0 2006.231.08:13:30.64#ibcon#about to read 6, iclass 21, count 0 2006.231.08:13:30.64#ibcon#read 6, iclass 21, count 0 2006.231.08:13:30.64#ibcon#end of sib2, iclass 21, count 0 2006.231.08:13:30.64#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:13:30.64#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:13:30.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:13:30.64#ibcon#*before write, iclass 21, count 0 2006.231.08:13:30.64#ibcon#enter sib2, iclass 21, count 0 2006.231.08:13:30.64#ibcon#flushed, iclass 21, count 0 2006.231.08:13:30.64#ibcon#about to write, iclass 21, count 0 2006.231.08:13:30.64#ibcon#wrote, iclass 21, count 0 2006.231.08:13:30.64#ibcon#about to read 3, iclass 21, count 0 2006.231.08:13:30.68#ibcon#read 3, iclass 21, count 0 2006.231.08:13:30.68#ibcon#about to read 4, iclass 21, count 0 2006.231.08:13:30.68#ibcon#read 4, iclass 21, count 0 2006.231.08:13:30.68#ibcon#about to read 5, iclass 21, count 0 2006.231.08:13:30.68#ibcon#read 5, iclass 21, count 0 2006.231.08:13:30.68#ibcon#about to read 6, iclass 21, count 0 2006.231.08:13:30.68#ibcon#read 6, iclass 21, count 0 2006.231.08:13:30.68#ibcon#end of sib2, iclass 21, count 0 2006.231.08:13:30.68#ibcon#*after write, iclass 21, count 0 2006.231.08:13:30.68#ibcon#*before return 0, iclass 21, count 0 2006.231.08:13:30.68#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:13:30.68#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:13:30.68#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:13:30.68#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:13:30.68$vc4f8/vb=1,4 2006.231.08:13:30.68#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.231.08:13:30.68#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.231.08:13:30.68#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:30.68#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:13:30.68#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:13:30.68#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:13:30.68#ibcon#enter wrdev, iclass 23, count 2 2006.231.08:13:30.68#ibcon#first serial, iclass 23, count 2 2006.231.08:13:30.68#ibcon#enter sib2, iclass 23, count 2 2006.231.08:13:30.68#ibcon#flushed, iclass 23, count 2 2006.231.08:13:30.68#ibcon#about to write, iclass 23, count 2 2006.231.08:13:30.68#ibcon#wrote, iclass 23, count 2 2006.231.08:13:30.68#ibcon#about to read 3, iclass 23, count 2 2006.231.08:13:30.70#ibcon#read 3, iclass 23, count 2 2006.231.08:13:30.70#ibcon#about to read 4, iclass 23, count 2 2006.231.08:13:30.70#ibcon#read 4, iclass 23, count 2 2006.231.08:13:30.70#ibcon#about to read 5, iclass 23, count 2 2006.231.08:13:30.70#ibcon#read 5, iclass 23, count 2 2006.231.08:13:30.70#ibcon#about to read 6, iclass 23, count 2 2006.231.08:13:30.70#ibcon#read 6, iclass 23, count 2 2006.231.08:13:30.70#ibcon#end of sib2, iclass 23, count 2 2006.231.08:13:30.70#ibcon#*mode == 0, iclass 23, count 2 2006.231.08:13:30.70#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.231.08:13:30.70#ibcon#[27=AT01-04\r\n] 2006.231.08:13:30.70#ibcon#*before write, iclass 23, count 2 2006.231.08:13:30.70#ibcon#enter sib2, iclass 23, count 2 2006.231.08:13:30.70#ibcon#flushed, iclass 23, count 2 2006.231.08:13:30.70#ibcon#about to write, iclass 23, count 2 2006.231.08:13:30.70#ibcon#wrote, iclass 23, count 2 2006.231.08:13:30.70#ibcon#about to read 3, iclass 23, count 2 2006.231.08:13:30.73#ibcon#read 3, iclass 23, count 2 2006.231.08:13:30.73#ibcon#about to read 4, iclass 23, count 2 2006.231.08:13:30.73#ibcon#read 4, iclass 23, count 2 2006.231.08:13:30.73#ibcon#about to read 5, iclass 23, count 2 2006.231.08:13:30.73#ibcon#read 5, iclass 23, count 2 2006.231.08:13:30.73#ibcon#about to read 6, iclass 23, count 2 2006.231.08:13:30.73#ibcon#read 6, iclass 23, count 2 2006.231.08:13:30.73#ibcon#end of sib2, iclass 23, count 2 2006.231.08:13:30.73#ibcon#*after write, iclass 23, count 2 2006.231.08:13:30.73#ibcon#*before return 0, iclass 23, count 2 2006.231.08:13:30.73#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:13:30.73#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:13:30.73#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.231.08:13:30.73#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:30.73#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:13:30.85#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:13:30.85#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:13:30.85#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:13:30.85#ibcon#first serial, iclass 23, count 0 2006.231.08:13:30.85#ibcon#enter sib2, iclass 23, count 0 2006.231.08:13:30.85#ibcon#flushed, iclass 23, count 0 2006.231.08:13:30.85#ibcon#about to write, iclass 23, count 0 2006.231.08:13:30.85#ibcon#wrote, iclass 23, count 0 2006.231.08:13:30.85#ibcon#about to read 3, iclass 23, count 0 2006.231.08:13:30.87#ibcon#read 3, iclass 23, count 0 2006.231.08:13:30.87#ibcon#about to read 4, iclass 23, count 0 2006.231.08:13:30.87#ibcon#read 4, iclass 23, count 0 2006.231.08:13:30.87#ibcon#about to read 5, iclass 23, count 0 2006.231.08:13:30.87#ibcon#read 5, iclass 23, count 0 2006.231.08:13:30.87#ibcon#about to read 6, iclass 23, count 0 2006.231.08:13:30.87#ibcon#read 6, iclass 23, count 0 2006.231.08:13:30.87#ibcon#end of sib2, iclass 23, count 0 2006.231.08:13:30.87#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:13:30.87#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:13:30.87#ibcon#[27=USB\r\n] 2006.231.08:13:30.87#ibcon#*before write, iclass 23, count 0 2006.231.08:13:30.87#ibcon#enter sib2, iclass 23, count 0 2006.231.08:13:30.87#ibcon#flushed, iclass 23, count 0 2006.231.08:13:30.87#ibcon#about to write, iclass 23, count 0 2006.231.08:13:30.87#ibcon#wrote, iclass 23, count 0 2006.231.08:13:30.87#ibcon#about to read 3, iclass 23, count 0 2006.231.08:13:30.90#ibcon#read 3, iclass 23, count 0 2006.231.08:13:30.90#ibcon#about to read 4, iclass 23, count 0 2006.231.08:13:30.90#ibcon#read 4, iclass 23, count 0 2006.231.08:13:30.90#ibcon#about to read 5, iclass 23, count 0 2006.231.08:13:30.90#ibcon#read 5, iclass 23, count 0 2006.231.08:13:30.90#ibcon#about to read 6, iclass 23, count 0 2006.231.08:13:30.90#ibcon#read 6, iclass 23, count 0 2006.231.08:13:30.90#ibcon#end of sib2, iclass 23, count 0 2006.231.08:13:30.90#ibcon#*after write, iclass 23, count 0 2006.231.08:13:30.90#ibcon#*before return 0, iclass 23, count 0 2006.231.08:13:30.90#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:13:30.90#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:13:30.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:13:30.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:13:30.90$vc4f8/vblo=2,640.99 2006.231.08:13:30.90#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.231.08:13:30.90#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.231.08:13:30.90#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:30.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:13:30.90#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:13:30.90#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:13:30.90#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:13:30.90#ibcon#first serial, iclass 25, count 0 2006.231.08:13:30.90#ibcon#enter sib2, iclass 25, count 0 2006.231.08:13:30.90#ibcon#flushed, iclass 25, count 0 2006.231.08:13:30.90#ibcon#about to write, iclass 25, count 0 2006.231.08:13:30.90#ibcon#wrote, iclass 25, count 0 2006.231.08:13:30.90#ibcon#about to read 3, iclass 25, count 0 2006.231.08:13:30.92#ibcon#read 3, iclass 25, count 0 2006.231.08:13:30.92#ibcon#about to read 4, iclass 25, count 0 2006.231.08:13:30.92#ibcon#read 4, iclass 25, count 0 2006.231.08:13:30.92#ibcon#about to read 5, iclass 25, count 0 2006.231.08:13:30.92#ibcon#read 5, iclass 25, count 0 2006.231.08:13:30.92#ibcon#about to read 6, iclass 25, count 0 2006.231.08:13:30.92#ibcon#read 6, iclass 25, count 0 2006.231.08:13:30.92#ibcon#end of sib2, iclass 25, count 0 2006.231.08:13:30.92#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:13:30.92#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:13:30.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:13:30.92#ibcon#*before write, iclass 25, count 0 2006.231.08:13:30.92#ibcon#enter sib2, iclass 25, count 0 2006.231.08:13:30.92#ibcon#flushed, iclass 25, count 0 2006.231.08:13:30.92#ibcon#about to write, iclass 25, count 0 2006.231.08:13:30.92#ibcon#wrote, iclass 25, count 0 2006.231.08:13:30.92#ibcon#about to read 3, iclass 25, count 0 2006.231.08:13:30.96#ibcon#read 3, iclass 25, count 0 2006.231.08:13:30.96#ibcon#about to read 4, iclass 25, count 0 2006.231.08:13:30.96#ibcon#read 4, iclass 25, count 0 2006.231.08:13:30.96#ibcon#about to read 5, iclass 25, count 0 2006.231.08:13:30.96#ibcon#read 5, iclass 25, count 0 2006.231.08:13:30.96#ibcon#about to read 6, iclass 25, count 0 2006.231.08:13:30.96#ibcon#read 6, iclass 25, count 0 2006.231.08:13:30.96#ibcon#end of sib2, iclass 25, count 0 2006.231.08:13:30.96#ibcon#*after write, iclass 25, count 0 2006.231.08:13:30.96#ibcon#*before return 0, iclass 25, count 0 2006.231.08:13:30.96#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:13:30.96#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:13:30.96#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:13:30.96#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:13:30.96$vc4f8/vb=2,4 2006.231.08:13:30.96#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.231.08:13:30.96#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.231.08:13:30.96#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:30.96#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:13:31.02#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:13:31.02#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:13:31.02#ibcon#enter wrdev, iclass 27, count 2 2006.231.08:13:31.02#ibcon#first serial, iclass 27, count 2 2006.231.08:13:31.02#ibcon#enter sib2, iclass 27, count 2 2006.231.08:13:31.02#ibcon#flushed, iclass 27, count 2 2006.231.08:13:31.02#ibcon#about to write, iclass 27, count 2 2006.231.08:13:31.02#ibcon#wrote, iclass 27, count 2 2006.231.08:13:31.02#ibcon#about to read 3, iclass 27, count 2 2006.231.08:13:31.04#ibcon#read 3, iclass 27, count 2 2006.231.08:13:31.04#ibcon#about to read 4, iclass 27, count 2 2006.231.08:13:31.04#ibcon#read 4, iclass 27, count 2 2006.231.08:13:31.04#ibcon#about to read 5, iclass 27, count 2 2006.231.08:13:31.04#ibcon#read 5, iclass 27, count 2 2006.231.08:13:31.04#ibcon#about to read 6, iclass 27, count 2 2006.231.08:13:31.04#ibcon#read 6, iclass 27, count 2 2006.231.08:13:31.04#ibcon#end of sib2, iclass 27, count 2 2006.231.08:13:31.04#ibcon#*mode == 0, iclass 27, count 2 2006.231.08:13:31.04#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.231.08:13:31.04#ibcon#[27=AT02-04\r\n] 2006.231.08:13:31.04#ibcon#*before write, iclass 27, count 2 2006.231.08:13:31.04#ibcon#enter sib2, iclass 27, count 2 2006.231.08:13:31.04#ibcon#flushed, iclass 27, count 2 2006.231.08:13:31.04#ibcon#about to write, iclass 27, count 2 2006.231.08:13:31.04#ibcon#wrote, iclass 27, count 2 2006.231.08:13:31.04#ibcon#about to read 3, iclass 27, count 2 2006.231.08:13:31.09#ibcon#read 3, iclass 27, count 2 2006.231.08:13:31.09#ibcon#about to read 4, iclass 27, count 2 2006.231.08:13:31.09#ibcon#read 4, iclass 27, count 2 2006.231.08:13:31.09#ibcon#about to read 5, iclass 27, count 2 2006.231.08:13:31.09#ibcon#read 5, iclass 27, count 2 2006.231.08:13:31.09#ibcon#about to read 6, iclass 27, count 2 2006.231.08:13:31.09#ibcon#read 6, iclass 27, count 2 2006.231.08:13:31.09#ibcon#end of sib2, iclass 27, count 2 2006.231.08:13:31.09#ibcon#*after write, iclass 27, count 2 2006.231.08:13:31.09#ibcon#*before return 0, iclass 27, count 2 2006.231.08:13:31.09#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:13:31.09#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:13:31.09#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.231.08:13:31.09#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:31.09#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:13:31.21#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:13:31.21#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:13:31.21#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:13:31.21#ibcon#first serial, iclass 27, count 0 2006.231.08:13:31.21#ibcon#enter sib2, iclass 27, count 0 2006.231.08:13:31.21#ibcon#flushed, iclass 27, count 0 2006.231.08:13:31.21#ibcon#about to write, iclass 27, count 0 2006.231.08:13:31.21#ibcon#wrote, iclass 27, count 0 2006.231.08:13:31.21#ibcon#about to read 3, iclass 27, count 0 2006.231.08:13:31.23#ibcon#read 3, iclass 27, count 0 2006.231.08:13:31.23#ibcon#about to read 4, iclass 27, count 0 2006.231.08:13:31.23#ibcon#read 4, iclass 27, count 0 2006.231.08:13:31.23#ibcon#about to read 5, iclass 27, count 0 2006.231.08:13:31.23#ibcon#read 5, iclass 27, count 0 2006.231.08:13:31.23#ibcon#about to read 6, iclass 27, count 0 2006.231.08:13:31.23#ibcon#read 6, iclass 27, count 0 2006.231.08:13:31.23#ibcon#end of sib2, iclass 27, count 0 2006.231.08:13:31.23#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:13:31.23#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:13:31.23#ibcon#[27=USB\r\n] 2006.231.08:13:31.23#ibcon#*before write, iclass 27, count 0 2006.231.08:13:31.23#ibcon#enter sib2, iclass 27, count 0 2006.231.08:13:31.23#ibcon#flushed, iclass 27, count 0 2006.231.08:13:31.23#ibcon#about to write, iclass 27, count 0 2006.231.08:13:31.23#ibcon#wrote, iclass 27, count 0 2006.231.08:13:31.23#ibcon#about to read 3, iclass 27, count 0 2006.231.08:13:31.26#ibcon#read 3, iclass 27, count 0 2006.231.08:13:31.26#ibcon#about to read 4, iclass 27, count 0 2006.231.08:13:31.26#ibcon#read 4, iclass 27, count 0 2006.231.08:13:31.26#ibcon#about to read 5, iclass 27, count 0 2006.231.08:13:31.26#ibcon#read 5, iclass 27, count 0 2006.231.08:13:31.26#ibcon#about to read 6, iclass 27, count 0 2006.231.08:13:31.26#ibcon#read 6, iclass 27, count 0 2006.231.08:13:31.26#ibcon#end of sib2, iclass 27, count 0 2006.231.08:13:31.26#ibcon#*after write, iclass 27, count 0 2006.231.08:13:31.26#ibcon#*before return 0, iclass 27, count 0 2006.231.08:13:31.26#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:13:31.26#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:13:31.26#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:13:31.26#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:13:31.26$vc4f8/vblo=3,656.99 2006.231.08:13:31.26#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.231.08:13:31.26#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.231.08:13:31.26#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:31.26#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:13:31.26#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:13:31.26#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:13:31.26#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:13:31.26#ibcon#first serial, iclass 29, count 0 2006.231.08:13:31.26#ibcon#enter sib2, iclass 29, count 0 2006.231.08:13:31.26#ibcon#flushed, iclass 29, count 0 2006.231.08:13:31.26#ibcon#about to write, iclass 29, count 0 2006.231.08:13:31.26#ibcon#wrote, iclass 29, count 0 2006.231.08:13:31.26#ibcon#about to read 3, iclass 29, count 0 2006.231.08:13:31.28#ibcon#read 3, iclass 29, count 0 2006.231.08:13:31.28#ibcon#about to read 4, iclass 29, count 0 2006.231.08:13:31.28#ibcon#read 4, iclass 29, count 0 2006.231.08:13:31.28#ibcon#about to read 5, iclass 29, count 0 2006.231.08:13:31.28#ibcon#read 5, iclass 29, count 0 2006.231.08:13:31.28#ibcon#about to read 6, iclass 29, count 0 2006.231.08:13:31.28#ibcon#read 6, iclass 29, count 0 2006.231.08:13:31.28#ibcon#end of sib2, iclass 29, count 0 2006.231.08:13:31.28#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:13:31.28#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:13:31.28#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:13:31.28#ibcon#*before write, iclass 29, count 0 2006.231.08:13:31.28#ibcon#enter sib2, iclass 29, count 0 2006.231.08:13:31.28#ibcon#flushed, iclass 29, count 0 2006.231.08:13:31.28#ibcon#about to write, iclass 29, count 0 2006.231.08:13:31.28#ibcon#wrote, iclass 29, count 0 2006.231.08:13:31.28#ibcon#about to read 3, iclass 29, count 0 2006.231.08:13:31.32#ibcon#read 3, iclass 29, count 0 2006.231.08:13:31.32#ibcon#about to read 4, iclass 29, count 0 2006.231.08:13:31.32#ibcon#read 4, iclass 29, count 0 2006.231.08:13:31.32#ibcon#about to read 5, iclass 29, count 0 2006.231.08:13:31.32#ibcon#read 5, iclass 29, count 0 2006.231.08:13:31.32#ibcon#about to read 6, iclass 29, count 0 2006.231.08:13:31.32#ibcon#read 6, iclass 29, count 0 2006.231.08:13:31.32#ibcon#end of sib2, iclass 29, count 0 2006.231.08:13:31.32#ibcon#*after write, iclass 29, count 0 2006.231.08:13:31.32#ibcon#*before return 0, iclass 29, count 0 2006.231.08:13:31.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:13:31.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:13:31.32#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:13:31.32#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:13:31.32$vc4f8/vb=3,4 2006.231.08:13:31.32#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.231.08:13:31.32#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.231.08:13:31.32#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:31.32#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:13:31.38#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:13:31.38#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:13:31.38#ibcon#enter wrdev, iclass 31, count 2 2006.231.08:13:31.38#ibcon#first serial, iclass 31, count 2 2006.231.08:13:31.38#ibcon#enter sib2, iclass 31, count 2 2006.231.08:13:31.38#ibcon#flushed, iclass 31, count 2 2006.231.08:13:31.38#ibcon#about to write, iclass 31, count 2 2006.231.08:13:31.38#ibcon#wrote, iclass 31, count 2 2006.231.08:13:31.38#ibcon#about to read 3, iclass 31, count 2 2006.231.08:13:31.40#ibcon#read 3, iclass 31, count 2 2006.231.08:13:31.40#ibcon#about to read 4, iclass 31, count 2 2006.231.08:13:31.40#ibcon#read 4, iclass 31, count 2 2006.231.08:13:31.40#ibcon#about to read 5, iclass 31, count 2 2006.231.08:13:31.40#ibcon#read 5, iclass 31, count 2 2006.231.08:13:31.40#ibcon#about to read 6, iclass 31, count 2 2006.231.08:13:31.40#ibcon#read 6, iclass 31, count 2 2006.231.08:13:31.40#ibcon#end of sib2, iclass 31, count 2 2006.231.08:13:31.40#ibcon#*mode == 0, iclass 31, count 2 2006.231.08:13:31.40#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.231.08:13:31.40#ibcon#[27=AT03-04\r\n] 2006.231.08:13:31.40#ibcon#*before write, iclass 31, count 2 2006.231.08:13:31.40#ibcon#enter sib2, iclass 31, count 2 2006.231.08:13:31.40#ibcon#flushed, iclass 31, count 2 2006.231.08:13:31.40#ibcon#about to write, iclass 31, count 2 2006.231.08:13:31.40#ibcon#wrote, iclass 31, count 2 2006.231.08:13:31.40#ibcon#about to read 3, iclass 31, count 2 2006.231.08:13:31.43#ibcon#read 3, iclass 31, count 2 2006.231.08:13:31.43#ibcon#about to read 4, iclass 31, count 2 2006.231.08:13:31.43#ibcon#read 4, iclass 31, count 2 2006.231.08:13:31.43#ibcon#about to read 5, iclass 31, count 2 2006.231.08:13:31.43#ibcon#read 5, iclass 31, count 2 2006.231.08:13:31.43#ibcon#about to read 6, iclass 31, count 2 2006.231.08:13:31.43#ibcon#read 6, iclass 31, count 2 2006.231.08:13:31.43#ibcon#end of sib2, iclass 31, count 2 2006.231.08:13:31.43#ibcon#*after write, iclass 31, count 2 2006.231.08:13:31.43#ibcon#*before return 0, iclass 31, count 2 2006.231.08:13:31.43#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:13:31.43#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:13:31.43#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.231.08:13:31.43#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:31.43#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:13:31.55#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:13:31.55#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:13:31.55#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:13:31.55#ibcon#first serial, iclass 31, count 0 2006.231.08:13:31.55#ibcon#enter sib2, iclass 31, count 0 2006.231.08:13:31.55#ibcon#flushed, iclass 31, count 0 2006.231.08:13:31.55#ibcon#about to write, iclass 31, count 0 2006.231.08:13:31.55#ibcon#wrote, iclass 31, count 0 2006.231.08:13:31.55#ibcon#about to read 3, iclass 31, count 0 2006.231.08:13:31.57#ibcon#read 3, iclass 31, count 0 2006.231.08:13:31.57#ibcon#about to read 4, iclass 31, count 0 2006.231.08:13:31.57#ibcon#read 4, iclass 31, count 0 2006.231.08:13:31.57#ibcon#about to read 5, iclass 31, count 0 2006.231.08:13:31.57#ibcon#read 5, iclass 31, count 0 2006.231.08:13:31.57#ibcon#about to read 6, iclass 31, count 0 2006.231.08:13:31.57#ibcon#read 6, iclass 31, count 0 2006.231.08:13:31.57#ibcon#end of sib2, iclass 31, count 0 2006.231.08:13:31.57#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:13:31.57#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:13:31.57#ibcon#[27=USB\r\n] 2006.231.08:13:31.57#ibcon#*before write, iclass 31, count 0 2006.231.08:13:31.57#ibcon#enter sib2, iclass 31, count 0 2006.231.08:13:31.57#ibcon#flushed, iclass 31, count 0 2006.231.08:13:31.57#ibcon#about to write, iclass 31, count 0 2006.231.08:13:31.57#ibcon#wrote, iclass 31, count 0 2006.231.08:13:31.57#ibcon#about to read 3, iclass 31, count 0 2006.231.08:13:31.60#ibcon#read 3, iclass 31, count 0 2006.231.08:13:31.60#ibcon#about to read 4, iclass 31, count 0 2006.231.08:13:31.60#ibcon#read 4, iclass 31, count 0 2006.231.08:13:31.60#ibcon#about to read 5, iclass 31, count 0 2006.231.08:13:31.60#ibcon#read 5, iclass 31, count 0 2006.231.08:13:31.60#ibcon#about to read 6, iclass 31, count 0 2006.231.08:13:31.60#ibcon#read 6, iclass 31, count 0 2006.231.08:13:31.60#ibcon#end of sib2, iclass 31, count 0 2006.231.08:13:31.60#ibcon#*after write, iclass 31, count 0 2006.231.08:13:31.60#ibcon#*before return 0, iclass 31, count 0 2006.231.08:13:31.60#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:13:31.60#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:13:31.60#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:13:31.60#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:13:31.60$vc4f8/vblo=4,712.99 2006.231.08:13:31.60#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.08:13:31.60#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.08:13:31.60#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:31.60#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:13:31.60#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:13:31.60#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:13:31.60#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:13:31.60#ibcon#first serial, iclass 33, count 0 2006.231.08:13:31.60#ibcon#enter sib2, iclass 33, count 0 2006.231.08:13:31.60#ibcon#flushed, iclass 33, count 0 2006.231.08:13:31.60#ibcon#about to write, iclass 33, count 0 2006.231.08:13:31.60#ibcon#wrote, iclass 33, count 0 2006.231.08:13:31.60#ibcon#about to read 3, iclass 33, count 0 2006.231.08:13:31.62#ibcon#read 3, iclass 33, count 0 2006.231.08:13:31.62#ibcon#about to read 4, iclass 33, count 0 2006.231.08:13:31.62#ibcon#read 4, iclass 33, count 0 2006.231.08:13:31.62#ibcon#about to read 5, iclass 33, count 0 2006.231.08:13:31.62#ibcon#read 5, iclass 33, count 0 2006.231.08:13:31.62#ibcon#about to read 6, iclass 33, count 0 2006.231.08:13:31.62#ibcon#read 6, iclass 33, count 0 2006.231.08:13:31.62#ibcon#end of sib2, iclass 33, count 0 2006.231.08:13:31.62#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:13:31.62#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:13:31.62#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:13:31.62#ibcon#*before write, iclass 33, count 0 2006.231.08:13:31.62#ibcon#enter sib2, iclass 33, count 0 2006.231.08:13:31.62#ibcon#flushed, iclass 33, count 0 2006.231.08:13:31.62#ibcon#about to write, iclass 33, count 0 2006.231.08:13:31.62#ibcon#wrote, iclass 33, count 0 2006.231.08:13:31.62#ibcon#about to read 3, iclass 33, count 0 2006.231.08:13:31.66#ibcon#read 3, iclass 33, count 0 2006.231.08:13:31.66#ibcon#about to read 4, iclass 33, count 0 2006.231.08:13:31.66#ibcon#read 4, iclass 33, count 0 2006.231.08:13:31.66#ibcon#about to read 5, iclass 33, count 0 2006.231.08:13:31.66#ibcon#read 5, iclass 33, count 0 2006.231.08:13:31.66#ibcon#about to read 6, iclass 33, count 0 2006.231.08:13:31.66#ibcon#read 6, iclass 33, count 0 2006.231.08:13:31.66#ibcon#end of sib2, iclass 33, count 0 2006.231.08:13:31.66#ibcon#*after write, iclass 33, count 0 2006.231.08:13:31.66#ibcon#*before return 0, iclass 33, count 0 2006.231.08:13:31.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:13:31.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:13:31.66#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:13:31.66#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:13:31.66$vc4f8/vb=4,4 2006.231.08:13:31.66#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.08:13:31.66#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.08:13:31.66#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:31.66#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:13:31.72#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:13:31.72#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:13:31.72#ibcon#enter wrdev, iclass 35, count 2 2006.231.08:13:31.72#ibcon#first serial, iclass 35, count 2 2006.231.08:13:31.72#ibcon#enter sib2, iclass 35, count 2 2006.231.08:13:31.72#ibcon#flushed, iclass 35, count 2 2006.231.08:13:31.72#ibcon#about to write, iclass 35, count 2 2006.231.08:13:31.72#ibcon#wrote, iclass 35, count 2 2006.231.08:13:31.72#ibcon#about to read 3, iclass 35, count 2 2006.231.08:13:31.74#ibcon#read 3, iclass 35, count 2 2006.231.08:13:31.74#ibcon#about to read 4, iclass 35, count 2 2006.231.08:13:31.74#ibcon#read 4, iclass 35, count 2 2006.231.08:13:31.74#ibcon#about to read 5, iclass 35, count 2 2006.231.08:13:31.74#ibcon#read 5, iclass 35, count 2 2006.231.08:13:31.74#ibcon#about to read 6, iclass 35, count 2 2006.231.08:13:31.74#ibcon#read 6, iclass 35, count 2 2006.231.08:13:31.74#ibcon#end of sib2, iclass 35, count 2 2006.231.08:13:31.74#ibcon#*mode == 0, iclass 35, count 2 2006.231.08:13:31.74#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.08:13:31.74#ibcon#[27=AT04-04\r\n] 2006.231.08:13:31.74#ibcon#*before write, iclass 35, count 2 2006.231.08:13:31.74#ibcon#enter sib2, iclass 35, count 2 2006.231.08:13:31.74#ibcon#flushed, iclass 35, count 2 2006.231.08:13:31.74#ibcon#about to write, iclass 35, count 2 2006.231.08:13:31.74#ibcon#wrote, iclass 35, count 2 2006.231.08:13:31.74#ibcon#about to read 3, iclass 35, count 2 2006.231.08:13:31.77#ibcon#read 3, iclass 35, count 2 2006.231.08:13:31.77#ibcon#about to read 4, iclass 35, count 2 2006.231.08:13:31.77#ibcon#read 4, iclass 35, count 2 2006.231.08:13:31.77#ibcon#about to read 5, iclass 35, count 2 2006.231.08:13:31.77#ibcon#read 5, iclass 35, count 2 2006.231.08:13:31.77#ibcon#about to read 6, iclass 35, count 2 2006.231.08:13:31.77#ibcon#read 6, iclass 35, count 2 2006.231.08:13:31.77#ibcon#end of sib2, iclass 35, count 2 2006.231.08:13:31.77#ibcon#*after write, iclass 35, count 2 2006.231.08:13:31.77#ibcon#*before return 0, iclass 35, count 2 2006.231.08:13:31.77#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:13:31.77#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:13:31.77#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.08:13:31.77#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:31.77#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:13:31.89#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:13:31.89#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:13:31.89#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:13:31.89#ibcon#first serial, iclass 35, count 0 2006.231.08:13:31.89#ibcon#enter sib2, iclass 35, count 0 2006.231.08:13:31.89#ibcon#flushed, iclass 35, count 0 2006.231.08:13:31.89#ibcon#about to write, iclass 35, count 0 2006.231.08:13:31.89#ibcon#wrote, iclass 35, count 0 2006.231.08:13:31.89#ibcon#about to read 3, iclass 35, count 0 2006.231.08:13:31.91#ibcon#read 3, iclass 35, count 0 2006.231.08:13:31.91#ibcon#about to read 4, iclass 35, count 0 2006.231.08:13:31.91#ibcon#read 4, iclass 35, count 0 2006.231.08:13:31.91#ibcon#about to read 5, iclass 35, count 0 2006.231.08:13:31.91#ibcon#read 5, iclass 35, count 0 2006.231.08:13:31.91#ibcon#about to read 6, iclass 35, count 0 2006.231.08:13:31.91#ibcon#read 6, iclass 35, count 0 2006.231.08:13:31.91#ibcon#end of sib2, iclass 35, count 0 2006.231.08:13:31.91#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:13:31.91#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:13:31.91#ibcon#[27=USB\r\n] 2006.231.08:13:31.91#ibcon#*before write, iclass 35, count 0 2006.231.08:13:31.91#ibcon#enter sib2, iclass 35, count 0 2006.231.08:13:31.91#ibcon#flushed, iclass 35, count 0 2006.231.08:13:31.91#ibcon#about to write, iclass 35, count 0 2006.231.08:13:31.91#ibcon#wrote, iclass 35, count 0 2006.231.08:13:31.91#ibcon#about to read 3, iclass 35, count 0 2006.231.08:13:31.94#ibcon#read 3, iclass 35, count 0 2006.231.08:13:31.94#ibcon#about to read 4, iclass 35, count 0 2006.231.08:13:31.94#ibcon#read 4, iclass 35, count 0 2006.231.08:13:31.94#ibcon#about to read 5, iclass 35, count 0 2006.231.08:13:31.94#ibcon#read 5, iclass 35, count 0 2006.231.08:13:31.94#ibcon#about to read 6, iclass 35, count 0 2006.231.08:13:31.94#ibcon#read 6, iclass 35, count 0 2006.231.08:13:31.94#ibcon#end of sib2, iclass 35, count 0 2006.231.08:13:31.94#ibcon#*after write, iclass 35, count 0 2006.231.08:13:31.94#ibcon#*before return 0, iclass 35, count 0 2006.231.08:13:31.94#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:13:31.94#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:13:31.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:13:31.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:13:31.94$vc4f8/vblo=5,744.99 2006.231.08:13:31.94#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.08:13:31.94#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.08:13:31.94#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:31.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:13:31.94#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:13:31.94#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:13:31.94#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:13:31.94#ibcon#first serial, iclass 37, count 0 2006.231.08:13:31.94#ibcon#enter sib2, iclass 37, count 0 2006.231.08:13:31.94#ibcon#flushed, iclass 37, count 0 2006.231.08:13:31.94#ibcon#about to write, iclass 37, count 0 2006.231.08:13:31.94#ibcon#wrote, iclass 37, count 0 2006.231.08:13:31.94#ibcon#about to read 3, iclass 37, count 0 2006.231.08:13:31.96#ibcon#read 3, iclass 37, count 0 2006.231.08:13:31.96#ibcon#about to read 4, iclass 37, count 0 2006.231.08:13:31.96#ibcon#read 4, iclass 37, count 0 2006.231.08:13:31.96#ibcon#about to read 5, iclass 37, count 0 2006.231.08:13:31.96#ibcon#read 5, iclass 37, count 0 2006.231.08:13:31.96#ibcon#about to read 6, iclass 37, count 0 2006.231.08:13:31.96#ibcon#read 6, iclass 37, count 0 2006.231.08:13:31.96#ibcon#end of sib2, iclass 37, count 0 2006.231.08:13:31.96#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:13:31.96#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:13:31.96#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:13:31.96#ibcon#*before write, iclass 37, count 0 2006.231.08:13:31.96#ibcon#enter sib2, iclass 37, count 0 2006.231.08:13:31.96#ibcon#flushed, iclass 37, count 0 2006.231.08:13:31.96#ibcon#about to write, iclass 37, count 0 2006.231.08:13:31.96#ibcon#wrote, iclass 37, count 0 2006.231.08:13:31.96#ibcon#about to read 3, iclass 37, count 0 2006.231.08:13:32.00#ibcon#read 3, iclass 37, count 0 2006.231.08:13:32.00#ibcon#about to read 4, iclass 37, count 0 2006.231.08:13:32.00#ibcon#read 4, iclass 37, count 0 2006.231.08:13:32.00#ibcon#about to read 5, iclass 37, count 0 2006.231.08:13:32.00#ibcon#read 5, iclass 37, count 0 2006.231.08:13:32.00#ibcon#about to read 6, iclass 37, count 0 2006.231.08:13:32.00#ibcon#read 6, iclass 37, count 0 2006.231.08:13:32.00#ibcon#end of sib2, iclass 37, count 0 2006.231.08:13:32.00#ibcon#*after write, iclass 37, count 0 2006.231.08:13:32.00#ibcon#*before return 0, iclass 37, count 0 2006.231.08:13:32.00#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:13:32.00#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:13:32.00#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:13:32.00#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:13:32.00$vc4f8/vb=5,3 2006.231.08:13:32.00#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.08:13:32.00#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.08:13:32.00#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:32.00#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:13:32.06#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:13:32.06#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:13:32.06#ibcon#enter wrdev, iclass 39, count 2 2006.231.08:13:32.06#ibcon#first serial, iclass 39, count 2 2006.231.08:13:32.06#ibcon#enter sib2, iclass 39, count 2 2006.231.08:13:32.06#ibcon#flushed, iclass 39, count 2 2006.231.08:13:32.06#ibcon#about to write, iclass 39, count 2 2006.231.08:13:32.06#ibcon#wrote, iclass 39, count 2 2006.231.08:13:32.06#ibcon#about to read 3, iclass 39, count 2 2006.231.08:13:32.08#ibcon#read 3, iclass 39, count 2 2006.231.08:13:32.08#ibcon#about to read 4, iclass 39, count 2 2006.231.08:13:32.08#ibcon#read 4, iclass 39, count 2 2006.231.08:13:32.08#ibcon#about to read 5, iclass 39, count 2 2006.231.08:13:32.08#ibcon#read 5, iclass 39, count 2 2006.231.08:13:32.08#ibcon#about to read 6, iclass 39, count 2 2006.231.08:13:32.08#ibcon#read 6, iclass 39, count 2 2006.231.08:13:32.08#ibcon#end of sib2, iclass 39, count 2 2006.231.08:13:32.08#ibcon#*mode == 0, iclass 39, count 2 2006.231.08:13:32.08#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.08:13:32.08#ibcon#[27=AT05-03\r\n] 2006.231.08:13:32.08#ibcon#*before write, iclass 39, count 2 2006.231.08:13:32.08#ibcon#enter sib2, iclass 39, count 2 2006.231.08:13:32.08#ibcon#flushed, iclass 39, count 2 2006.231.08:13:32.08#ibcon#about to write, iclass 39, count 2 2006.231.08:13:32.08#ibcon#wrote, iclass 39, count 2 2006.231.08:13:32.08#ibcon#about to read 3, iclass 39, count 2 2006.231.08:13:32.11#ibcon#read 3, iclass 39, count 2 2006.231.08:13:32.11#ibcon#about to read 4, iclass 39, count 2 2006.231.08:13:32.11#ibcon#read 4, iclass 39, count 2 2006.231.08:13:32.11#ibcon#about to read 5, iclass 39, count 2 2006.231.08:13:32.11#ibcon#read 5, iclass 39, count 2 2006.231.08:13:32.11#ibcon#about to read 6, iclass 39, count 2 2006.231.08:13:32.11#ibcon#read 6, iclass 39, count 2 2006.231.08:13:32.11#ibcon#end of sib2, iclass 39, count 2 2006.231.08:13:32.11#ibcon#*after write, iclass 39, count 2 2006.231.08:13:32.11#ibcon#*before return 0, iclass 39, count 2 2006.231.08:13:32.11#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:13:32.11#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:13:32.11#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.08:13:32.11#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:32.11#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:13:32.23#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:13:32.23#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:13:32.23#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:13:32.23#ibcon#first serial, iclass 39, count 0 2006.231.08:13:32.23#ibcon#enter sib2, iclass 39, count 0 2006.231.08:13:32.23#ibcon#flushed, iclass 39, count 0 2006.231.08:13:32.23#ibcon#about to write, iclass 39, count 0 2006.231.08:13:32.23#ibcon#wrote, iclass 39, count 0 2006.231.08:13:32.23#ibcon#about to read 3, iclass 39, count 0 2006.231.08:13:32.25#ibcon#read 3, iclass 39, count 0 2006.231.08:13:32.25#ibcon#about to read 4, iclass 39, count 0 2006.231.08:13:32.25#ibcon#read 4, iclass 39, count 0 2006.231.08:13:32.25#ibcon#about to read 5, iclass 39, count 0 2006.231.08:13:32.25#ibcon#read 5, iclass 39, count 0 2006.231.08:13:32.25#ibcon#about to read 6, iclass 39, count 0 2006.231.08:13:32.25#ibcon#read 6, iclass 39, count 0 2006.231.08:13:32.25#ibcon#end of sib2, iclass 39, count 0 2006.231.08:13:32.25#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:13:32.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:13:32.25#ibcon#[27=USB\r\n] 2006.231.08:13:32.25#ibcon#*before write, iclass 39, count 0 2006.231.08:13:32.25#ibcon#enter sib2, iclass 39, count 0 2006.231.08:13:32.25#ibcon#flushed, iclass 39, count 0 2006.231.08:13:32.25#ibcon#about to write, iclass 39, count 0 2006.231.08:13:32.25#ibcon#wrote, iclass 39, count 0 2006.231.08:13:32.25#ibcon#about to read 3, iclass 39, count 0 2006.231.08:13:32.28#ibcon#read 3, iclass 39, count 0 2006.231.08:13:32.28#ibcon#about to read 4, iclass 39, count 0 2006.231.08:13:32.28#ibcon#read 4, iclass 39, count 0 2006.231.08:13:32.28#ibcon#about to read 5, iclass 39, count 0 2006.231.08:13:32.28#ibcon#read 5, iclass 39, count 0 2006.231.08:13:32.28#ibcon#about to read 6, iclass 39, count 0 2006.231.08:13:32.28#ibcon#read 6, iclass 39, count 0 2006.231.08:13:32.28#ibcon#end of sib2, iclass 39, count 0 2006.231.08:13:32.28#ibcon#*after write, iclass 39, count 0 2006.231.08:13:32.28#ibcon#*before return 0, iclass 39, count 0 2006.231.08:13:32.28#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:13:32.28#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:13:32.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:13:32.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:13:32.28$vc4f8/vblo=6,752.99 2006.231.08:13:32.28#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.08:13:32.28#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.08:13:32.28#ibcon#ireg 17 cls_cnt 0 2006.231.08:13:32.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:13:32.28#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:13:32.28#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:13:32.28#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:13:32.28#ibcon#first serial, iclass 3, count 0 2006.231.08:13:32.28#ibcon#enter sib2, iclass 3, count 0 2006.231.08:13:32.28#ibcon#flushed, iclass 3, count 0 2006.231.08:13:32.28#ibcon#about to write, iclass 3, count 0 2006.231.08:13:32.28#ibcon#wrote, iclass 3, count 0 2006.231.08:13:32.28#ibcon#about to read 3, iclass 3, count 0 2006.231.08:13:32.30#ibcon#read 3, iclass 3, count 0 2006.231.08:13:32.30#ibcon#about to read 4, iclass 3, count 0 2006.231.08:13:32.30#ibcon#read 4, iclass 3, count 0 2006.231.08:13:32.30#ibcon#about to read 5, iclass 3, count 0 2006.231.08:13:32.30#ibcon#read 5, iclass 3, count 0 2006.231.08:13:32.30#ibcon#about to read 6, iclass 3, count 0 2006.231.08:13:32.30#ibcon#read 6, iclass 3, count 0 2006.231.08:13:32.30#ibcon#end of sib2, iclass 3, count 0 2006.231.08:13:32.30#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:13:32.30#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:13:32.30#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:13:32.30#ibcon#*before write, iclass 3, count 0 2006.231.08:13:32.30#ibcon#enter sib2, iclass 3, count 0 2006.231.08:13:32.30#ibcon#flushed, iclass 3, count 0 2006.231.08:13:32.30#ibcon#about to write, iclass 3, count 0 2006.231.08:13:32.30#ibcon#wrote, iclass 3, count 0 2006.231.08:13:32.30#ibcon#about to read 3, iclass 3, count 0 2006.231.08:13:32.34#ibcon#read 3, iclass 3, count 0 2006.231.08:13:32.34#ibcon#about to read 4, iclass 3, count 0 2006.231.08:13:32.34#ibcon#read 4, iclass 3, count 0 2006.231.08:13:32.34#ibcon#about to read 5, iclass 3, count 0 2006.231.08:13:32.34#ibcon#read 5, iclass 3, count 0 2006.231.08:13:32.34#ibcon#about to read 6, iclass 3, count 0 2006.231.08:13:32.34#ibcon#read 6, iclass 3, count 0 2006.231.08:13:32.34#ibcon#end of sib2, iclass 3, count 0 2006.231.08:13:32.34#ibcon#*after write, iclass 3, count 0 2006.231.08:13:32.34#ibcon#*before return 0, iclass 3, count 0 2006.231.08:13:32.34#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:13:32.34#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:13:32.34#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:13:32.34#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:13:32.34$vc4f8/vb=6,4 2006.231.08:13:32.34#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.08:13:32.34#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.08:13:32.34#ibcon#ireg 11 cls_cnt 2 2006.231.08:13:32.34#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:13:32.40#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:13:32.40#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:13:32.40#ibcon#enter wrdev, iclass 5, count 2 2006.231.08:13:32.40#ibcon#first serial, iclass 5, count 2 2006.231.08:13:32.40#ibcon#enter sib2, iclass 5, count 2 2006.231.08:13:32.40#ibcon#flushed, iclass 5, count 2 2006.231.08:13:32.40#ibcon#about to write, iclass 5, count 2 2006.231.08:13:32.40#ibcon#wrote, iclass 5, count 2 2006.231.08:13:32.40#ibcon#about to read 3, iclass 5, count 2 2006.231.08:13:32.42#ibcon#read 3, iclass 5, count 2 2006.231.08:13:32.42#ibcon#about to read 4, iclass 5, count 2 2006.231.08:13:32.42#ibcon#read 4, iclass 5, count 2 2006.231.08:13:32.42#ibcon#about to read 5, iclass 5, count 2 2006.231.08:13:32.42#ibcon#read 5, iclass 5, count 2 2006.231.08:13:32.42#ibcon#about to read 6, iclass 5, count 2 2006.231.08:13:32.42#ibcon#read 6, iclass 5, count 2 2006.231.08:13:32.42#ibcon#end of sib2, iclass 5, count 2 2006.231.08:13:32.42#ibcon#*mode == 0, iclass 5, count 2 2006.231.08:13:32.42#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.08:13:32.42#ibcon#[27=AT06-04\r\n] 2006.231.08:13:32.42#ibcon#*before write, iclass 5, count 2 2006.231.08:13:32.42#ibcon#enter sib2, iclass 5, count 2 2006.231.08:13:32.42#ibcon#flushed, iclass 5, count 2 2006.231.08:13:32.42#ibcon#about to write, iclass 5, count 2 2006.231.08:13:32.42#ibcon#wrote, iclass 5, count 2 2006.231.08:13:32.42#ibcon#about to read 3, iclass 5, count 2 2006.231.08:13:32.45#ibcon#read 3, iclass 5, count 2 2006.231.08:13:32.45#ibcon#about to read 4, iclass 5, count 2 2006.231.08:13:32.45#ibcon#read 4, iclass 5, count 2 2006.231.08:13:32.45#ibcon#about to read 5, iclass 5, count 2 2006.231.08:13:32.45#ibcon#read 5, iclass 5, count 2 2006.231.08:13:32.45#ibcon#about to read 6, iclass 5, count 2 2006.231.08:13:32.45#ibcon#read 6, iclass 5, count 2 2006.231.08:13:32.45#ibcon#end of sib2, iclass 5, count 2 2006.231.08:13:32.45#ibcon#*after write, iclass 5, count 2 2006.231.08:13:32.45#ibcon#*before return 0, iclass 5, count 2 2006.231.08:13:32.45#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:13:32.45#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:13:32.45#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.08:13:32.45#ibcon#ireg 7 cls_cnt 0 2006.231.08:13:32.45#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:13:32.57#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:13:32.57#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:13:32.57#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:13:32.57#ibcon#first serial, iclass 5, count 0 2006.231.08:13:32.57#ibcon#enter sib2, iclass 5, count 0 2006.231.08:13:32.57#ibcon#flushed, iclass 5, count 0 2006.231.08:13:32.57#ibcon#about to write, iclass 5, count 0 2006.231.08:13:32.57#ibcon#wrote, iclass 5, count 0 2006.231.08:13:32.57#ibcon#about to read 3, iclass 5, count 0 2006.231.08:13:32.59#ibcon#read 3, iclass 5, count 0 2006.231.08:13:32.59#ibcon#about to read 4, iclass 5, count 0 2006.231.08:13:32.59#ibcon#read 4, iclass 5, count 0 2006.231.08:13:32.59#ibcon#about to read 5, iclass 5, count 0 2006.231.08:13:32.59#ibcon#read 5, iclass 5, count 0 2006.231.08:13:32.59#ibcon#about to read 6, iclass 5, count 0 2006.231.08:13:32.59#ibcon#read 6, iclass 5, count 0 2006.231.08:13:32.59#ibcon#end of sib2, iclass 5, count 0 2006.231.08:13:32.59#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:13:32.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:13:32.59#ibcon#[27=USB\r\n] 2006.231.08:13:32.59#ibcon#*before write, iclass 5, count 0 2006.231.08:13:32.59#ibcon#enter sib2, iclass 5, count 0 2006.231.08:13:32.59#ibcon#flushed, iclass 5, count 0 2006.231.08:13:32.59#ibcon#about to write, iclass 5, count 0 2006.231.08:13:32.59#ibcon#wrote, iclass 5, count 0 2006.231.08:13:32.59#ibcon#about to read 3, iclass 5, count 0 2006.231.08:13:32.62#ibcon#read 3, iclass 5, count 0 2006.231.08:13:32.62#ibcon#about to read 4, iclass 5, count 0 2006.231.08:13:32.62#ibcon#read 4, iclass 5, count 0 2006.231.08:13:32.62#ibcon#about to read 5, iclass 5, count 0 2006.231.08:13:32.62#ibcon#read 5, iclass 5, count 0 2006.231.08:13:32.62#ibcon#about to read 6, iclass 5, count 0 2006.231.08:13:32.62#ibcon#read 6, iclass 5, count 0 2006.231.08:13:32.62#ibcon#end of sib2, iclass 5, count 0 2006.231.08:13:32.62#ibcon#*after write, iclass 5, count 0 2006.231.08:13:32.62#ibcon#*before return 0, iclass 5, count 0 2006.231.08:13:32.62#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:13:32.62#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:13:32.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:13:32.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:13:32.62$vc4f8/vabw=wide 2006.231.08:13:32.62#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.08:13:32.62#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.08:13:32.62#ibcon#ireg 8 cls_cnt 0 2006.231.08:13:32.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:13:32.62#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:13:32.62#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:13:32.62#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:13:32.62#ibcon#first serial, iclass 7, count 0 2006.231.08:13:32.62#ibcon#enter sib2, iclass 7, count 0 2006.231.08:13:32.62#ibcon#flushed, iclass 7, count 0 2006.231.08:13:32.62#ibcon#about to write, iclass 7, count 0 2006.231.08:13:32.62#ibcon#wrote, iclass 7, count 0 2006.231.08:13:32.62#ibcon#about to read 3, iclass 7, count 0 2006.231.08:13:32.64#ibcon#read 3, iclass 7, count 0 2006.231.08:13:32.64#ibcon#about to read 4, iclass 7, count 0 2006.231.08:13:32.64#ibcon#read 4, iclass 7, count 0 2006.231.08:13:32.64#ibcon#about to read 5, iclass 7, count 0 2006.231.08:13:32.64#ibcon#read 5, iclass 7, count 0 2006.231.08:13:32.64#ibcon#about to read 6, iclass 7, count 0 2006.231.08:13:32.64#ibcon#read 6, iclass 7, count 0 2006.231.08:13:32.64#ibcon#end of sib2, iclass 7, count 0 2006.231.08:13:32.64#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:13:32.64#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:13:32.64#ibcon#[25=BW32\r\n] 2006.231.08:13:32.64#ibcon#*before write, iclass 7, count 0 2006.231.08:13:32.64#ibcon#enter sib2, iclass 7, count 0 2006.231.08:13:32.64#ibcon#flushed, iclass 7, count 0 2006.231.08:13:32.64#ibcon#about to write, iclass 7, count 0 2006.231.08:13:32.64#ibcon#wrote, iclass 7, count 0 2006.231.08:13:32.64#ibcon#about to read 3, iclass 7, count 0 2006.231.08:13:32.67#ibcon#read 3, iclass 7, count 0 2006.231.08:13:32.67#ibcon#about to read 4, iclass 7, count 0 2006.231.08:13:32.67#ibcon#read 4, iclass 7, count 0 2006.231.08:13:32.67#ibcon#about to read 5, iclass 7, count 0 2006.231.08:13:32.67#ibcon#read 5, iclass 7, count 0 2006.231.08:13:32.67#ibcon#about to read 6, iclass 7, count 0 2006.231.08:13:32.67#ibcon#read 6, iclass 7, count 0 2006.231.08:13:32.67#ibcon#end of sib2, iclass 7, count 0 2006.231.08:13:32.67#ibcon#*after write, iclass 7, count 0 2006.231.08:13:32.67#ibcon#*before return 0, iclass 7, count 0 2006.231.08:13:32.67#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:13:32.67#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:13:32.67#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:13:32.67#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:13:32.67$vc4f8/vbbw=wide 2006.231.08:13:32.67#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.231.08:13:32.67#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.231.08:13:32.67#ibcon#ireg 8 cls_cnt 0 2006.231.08:13:32.67#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:13:32.74#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:13:32.74#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:13:32.74#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:13:32.74#ibcon#first serial, iclass 11, count 0 2006.231.08:13:32.74#ibcon#enter sib2, iclass 11, count 0 2006.231.08:13:32.74#ibcon#flushed, iclass 11, count 0 2006.231.08:13:32.74#ibcon#about to write, iclass 11, count 0 2006.231.08:13:32.74#ibcon#wrote, iclass 11, count 0 2006.231.08:13:32.74#ibcon#about to read 3, iclass 11, count 0 2006.231.08:13:32.76#ibcon#read 3, iclass 11, count 0 2006.231.08:13:32.76#ibcon#about to read 4, iclass 11, count 0 2006.231.08:13:32.76#ibcon#read 4, iclass 11, count 0 2006.231.08:13:32.76#ibcon#about to read 5, iclass 11, count 0 2006.231.08:13:32.76#ibcon#read 5, iclass 11, count 0 2006.231.08:13:32.76#ibcon#about to read 6, iclass 11, count 0 2006.231.08:13:32.76#ibcon#read 6, iclass 11, count 0 2006.231.08:13:32.76#ibcon#end of sib2, iclass 11, count 0 2006.231.08:13:32.76#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:13:32.76#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:13:32.76#ibcon#[27=BW32\r\n] 2006.231.08:13:32.76#ibcon#*before write, iclass 11, count 0 2006.231.08:13:32.76#ibcon#enter sib2, iclass 11, count 0 2006.231.08:13:32.76#ibcon#flushed, iclass 11, count 0 2006.231.08:13:32.76#ibcon#about to write, iclass 11, count 0 2006.231.08:13:32.76#ibcon#wrote, iclass 11, count 0 2006.231.08:13:32.76#ibcon#about to read 3, iclass 11, count 0 2006.231.08:13:32.79#ibcon#read 3, iclass 11, count 0 2006.231.08:13:32.79#ibcon#about to read 4, iclass 11, count 0 2006.231.08:13:32.79#ibcon#read 4, iclass 11, count 0 2006.231.08:13:32.79#ibcon#about to read 5, iclass 11, count 0 2006.231.08:13:32.79#ibcon#read 5, iclass 11, count 0 2006.231.08:13:32.79#ibcon#about to read 6, iclass 11, count 0 2006.231.08:13:32.79#ibcon#read 6, iclass 11, count 0 2006.231.08:13:32.79#ibcon#end of sib2, iclass 11, count 0 2006.231.08:13:32.79#ibcon#*after write, iclass 11, count 0 2006.231.08:13:32.79#ibcon#*before return 0, iclass 11, count 0 2006.231.08:13:32.79#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:13:32.79#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:13:32.79#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:13:32.79#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:13:32.79$4f8m12a/ifd4f 2006.231.08:13:32.79$ifd4f/lo= 2006.231.08:13:32.79$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:13:32.79$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:13:32.79$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:13:32.79$ifd4f/patch= 2006.231.08:13:32.79$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:13:32.79$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:13:32.79$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:13:32.79$4f8m12a/"form=m,16.000,1:2 2006.231.08:13:32.79$4f8m12a/"tpicd 2006.231.08:13:32.79$4f8m12a/echo=off 2006.231.08:13:32.79$4f8m12a/xlog=off 2006.231.08:13:32.79:!2006.231.08:14:00 2006.231.08:13:37.14#trakl#Source acquired 2006.231.08:13:39.14#flagr#flagr/antenna,acquired 2006.231.08:14:00.00:preob 2006.231.08:14:01.14/onsource/TRACKING 2006.231.08:14:01.14:!2006.231.08:14:10 2006.231.08:14:10.00:data_valid=on 2006.231.08:14:10.00:midob 2006.231.08:14:10.14/onsource/TRACKING 2006.231.08:14:10.14/wx/30.45,1004.5,86 2006.231.08:14:10.30/cable/+6.3713E-03 2006.231.08:14:11.39/va/01,08,usb,yes,30,31 2006.231.08:14:11.39/va/02,07,usb,yes,30,31 2006.231.08:14:11.39/va/03,08,usb,yes,22,22 2006.231.08:14:11.39/va/04,07,usb,yes,31,34 2006.231.08:14:11.39/va/05,07,usb,yes,34,36 2006.231.08:14:11.39/va/06,06,usb,yes,33,33 2006.231.08:14:11.39/va/07,06,usb,yes,34,34 2006.231.08:14:11.39/va/08,06,usb,yes,36,35 2006.231.08:14:11.62/valo/01,532.99,yes,locked 2006.231.08:14:11.62/valo/02,572.99,yes,locked 2006.231.08:14:11.62/valo/03,672.99,yes,locked 2006.231.08:14:11.62/valo/04,832.99,yes,locked 2006.231.08:14:11.62/valo/05,652.99,yes,locked 2006.231.08:14:11.62/valo/06,772.99,yes,locked 2006.231.08:14:11.62/valo/07,832.99,yes,locked 2006.231.08:14:11.62/valo/08,852.99,yes,locked 2006.231.08:14:12.71/vb/01,04,usb,yes,31,29 2006.231.08:14:12.71/vb/02,04,usb,yes,32,34 2006.231.08:14:12.71/vb/03,04,usb,yes,29,33 2006.231.08:14:12.71/vb/04,04,usb,yes,30,30 2006.231.08:14:12.71/vb/05,03,usb,yes,35,40 2006.231.08:14:12.71/vb/06,04,usb,yes,29,32 2006.231.08:14:12.71/vb/07,04,usb,yes,31,31 2006.231.08:14:12.71/vb/08,04,usb,yes,29,32 2006.231.08:14:12.94/vblo/01,632.99,yes,locked 2006.231.08:14:12.94/vblo/02,640.99,yes,locked 2006.231.08:14:12.94/vblo/03,656.99,yes,locked 2006.231.08:14:12.94/vblo/04,712.99,yes,locked 2006.231.08:14:12.94/vblo/05,744.99,yes,locked 2006.231.08:14:12.94/vblo/06,752.99,yes,locked 2006.231.08:14:12.94/vblo/07,734.99,yes,locked 2006.231.08:14:12.94/vblo/08,744.99,yes,locked 2006.231.08:14:13.09/vabw/8 2006.231.08:14:13.24/vbbw/8 2006.231.08:14:13.33/xfe/off,on,12.2 2006.231.08:14:13.73/ifatt/23,28,28,28 2006.231.08:14:14.07/fmout-gps/S +4.43E-07 2006.231.08:14:14.11:!2006.231.08:15:10 2006.231.08:15:10.00:data_valid=off 2006.231.08:15:10.01:postob 2006.231.08:15:10.11/cable/+6.3719E-03 2006.231.08:15:10.12/wx/30.44,1004.5,85 2006.231.08:15:11.07/fmout-gps/S +4.43E-07 2006.231.08:15:11.08:scan_name=231-0816,k06231,60 2006.231.08:15:11.08:source=3c371,180650.68,694928.1,2000.0,cw 2006.231.08:15:11.14#flagr#flagr/antenna,new-source 2006.231.08:15:12.14:checkk5 2006.231.08:15:12.52/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:15:12.90/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:15:13.28/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:15:13.65/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:15:14.01/chk_obsdata//k5ts1/T2310814??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:15:14.38/chk_obsdata//k5ts2/T2310814??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:15:14.74/chk_obsdata//k5ts3/T2310814??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:15:15.11/chk_obsdata//k5ts4/T2310814??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:15:15.80/k5log//k5ts1_log_newline 2006.231.08:15:16.50/k5log//k5ts2_log_newline 2006.231.08:15:17.20/k5log//k5ts3_log_newline 2006.231.08:15:17.89/k5log//k5ts4_log_newline 2006.231.08:15:17.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:15:17.92:4f8m12a=2 2006.231.08:15:17.92$4f8m12a/echo=on 2006.231.08:15:17.92$4f8m12a/pcalon 2006.231.08:15:17.92$pcalon/"no phase cal control is implemented here 2006.231.08:15:17.92$4f8m12a/"tpicd=stop 2006.231.08:15:17.92$4f8m12a/vc4f8 2006.231.08:15:17.92$vc4f8/valo=1,532.99 2006.231.08:15:17.92#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.08:15:17.92#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.08:15:17.92#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:17.92#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:15:17.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:15:17.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:15:17.92#ibcon#enter wrdev, iclass 22, count 0 2006.231.08:15:17.92#ibcon#first serial, iclass 22, count 0 2006.231.08:15:17.92#ibcon#enter sib2, iclass 22, count 0 2006.231.08:15:17.92#ibcon#flushed, iclass 22, count 0 2006.231.08:15:17.92#ibcon#about to write, iclass 22, count 0 2006.231.08:15:17.92#ibcon#wrote, iclass 22, count 0 2006.231.08:15:17.92#ibcon#about to read 3, iclass 22, count 0 2006.231.08:15:17.96#ibcon#read 3, iclass 22, count 0 2006.231.08:15:17.96#ibcon#about to read 4, iclass 22, count 0 2006.231.08:15:17.96#ibcon#read 4, iclass 22, count 0 2006.231.08:15:17.96#ibcon#about to read 5, iclass 22, count 0 2006.231.08:15:17.96#ibcon#read 5, iclass 22, count 0 2006.231.08:15:17.96#ibcon#about to read 6, iclass 22, count 0 2006.231.08:15:17.96#ibcon#read 6, iclass 22, count 0 2006.231.08:15:17.96#ibcon#end of sib2, iclass 22, count 0 2006.231.08:15:17.96#ibcon#*mode == 0, iclass 22, count 0 2006.231.08:15:17.96#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.08:15:17.96#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:15:17.96#ibcon#*before write, iclass 22, count 0 2006.231.08:15:17.96#ibcon#enter sib2, iclass 22, count 0 2006.231.08:15:17.96#ibcon#flushed, iclass 22, count 0 2006.231.08:15:17.96#ibcon#about to write, iclass 22, count 0 2006.231.08:15:17.96#ibcon#wrote, iclass 22, count 0 2006.231.08:15:17.96#ibcon#about to read 3, iclass 22, count 0 2006.231.08:15:18.00#ibcon#read 3, iclass 22, count 0 2006.231.08:15:18.00#ibcon#about to read 4, iclass 22, count 0 2006.231.08:15:18.00#ibcon#read 4, iclass 22, count 0 2006.231.08:15:18.00#ibcon#about to read 5, iclass 22, count 0 2006.231.08:15:18.00#ibcon#read 5, iclass 22, count 0 2006.231.08:15:18.00#ibcon#about to read 6, iclass 22, count 0 2006.231.08:15:18.00#ibcon#read 6, iclass 22, count 0 2006.231.08:15:18.00#ibcon#end of sib2, iclass 22, count 0 2006.231.08:15:18.00#ibcon#*after write, iclass 22, count 0 2006.231.08:15:18.00#ibcon#*before return 0, iclass 22, count 0 2006.231.08:15:18.00#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:15:18.00#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:15:18.00#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.08:15:18.00#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.08:15:18.00$vc4f8/va=1,8 2006.231.08:15:18.00#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.08:15:18.00#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.08:15:18.00#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:18.00#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:15:18.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:15:18.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:15:18.00#ibcon#enter wrdev, iclass 24, count 2 2006.231.08:15:18.00#ibcon#first serial, iclass 24, count 2 2006.231.08:15:18.00#ibcon#enter sib2, iclass 24, count 2 2006.231.08:15:18.00#ibcon#flushed, iclass 24, count 2 2006.231.08:15:18.00#ibcon#about to write, iclass 24, count 2 2006.231.08:15:18.00#ibcon#wrote, iclass 24, count 2 2006.231.08:15:18.00#ibcon#about to read 3, iclass 24, count 2 2006.231.08:15:18.02#ibcon#read 3, iclass 24, count 2 2006.231.08:15:18.02#ibcon#about to read 4, iclass 24, count 2 2006.231.08:15:18.02#ibcon#read 4, iclass 24, count 2 2006.231.08:15:18.02#ibcon#about to read 5, iclass 24, count 2 2006.231.08:15:18.02#ibcon#read 5, iclass 24, count 2 2006.231.08:15:18.02#ibcon#about to read 6, iclass 24, count 2 2006.231.08:15:18.02#ibcon#read 6, iclass 24, count 2 2006.231.08:15:18.02#ibcon#end of sib2, iclass 24, count 2 2006.231.08:15:18.02#ibcon#*mode == 0, iclass 24, count 2 2006.231.08:15:18.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.08:15:18.02#ibcon#[25=AT01-08\r\n] 2006.231.08:15:18.02#ibcon#*before write, iclass 24, count 2 2006.231.08:15:18.02#ibcon#enter sib2, iclass 24, count 2 2006.231.08:15:18.02#ibcon#flushed, iclass 24, count 2 2006.231.08:15:18.02#ibcon#about to write, iclass 24, count 2 2006.231.08:15:18.02#ibcon#wrote, iclass 24, count 2 2006.231.08:15:18.02#ibcon#about to read 3, iclass 24, count 2 2006.231.08:15:18.05#ibcon#read 3, iclass 24, count 2 2006.231.08:15:18.05#ibcon#about to read 4, iclass 24, count 2 2006.231.08:15:18.05#ibcon#read 4, iclass 24, count 2 2006.231.08:15:18.05#ibcon#about to read 5, iclass 24, count 2 2006.231.08:15:18.05#ibcon#read 5, iclass 24, count 2 2006.231.08:15:18.05#ibcon#about to read 6, iclass 24, count 2 2006.231.08:15:18.05#ibcon#read 6, iclass 24, count 2 2006.231.08:15:18.05#ibcon#end of sib2, iclass 24, count 2 2006.231.08:15:18.05#ibcon#*after write, iclass 24, count 2 2006.231.08:15:18.05#ibcon#*before return 0, iclass 24, count 2 2006.231.08:15:18.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:15:18.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:15:18.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.08:15:18.05#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:18.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:15:18.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:15:18.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:15:18.17#ibcon#enter wrdev, iclass 24, count 0 2006.231.08:15:18.17#ibcon#first serial, iclass 24, count 0 2006.231.08:15:18.17#ibcon#enter sib2, iclass 24, count 0 2006.231.08:15:18.17#ibcon#flushed, iclass 24, count 0 2006.231.08:15:18.17#ibcon#about to write, iclass 24, count 0 2006.231.08:15:18.17#ibcon#wrote, iclass 24, count 0 2006.231.08:15:18.17#ibcon#about to read 3, iclass 24, count 0 2006.231.08:15:18.19#ibcon#read 3, iclass 24, count 0 2006.231.08:15:18.19#ibcon#about to read 4, iclass 24, count 0 2006.231.08:15:18.19#ibcon#read 4, iclass 24, count 0 2006.231.08:15:18.19#ibcon#about to read 5, iclass 24, count 0 2006.231.08:15:18.19#ibcon#read 5, iclass 24, count 0 2006.231.08:15:18.19#ibcon#about to read 6, iclass 24, count 0 2006.231.08:15:18.19#ibcon#read 6, iclass 24, count 0 2006.231.08:15:18.19#ibcon#end of sib2, iclass 24, count 0 2006.231.08:15:18.19#ibcon#*mode == 0, iclass 24, count 0 2006.231.08:15:18.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.08:15:18.19#ibcon#[25=USB\r\n] 2006.231.08:15:18.19#ibcon#*before write, iclass 24, count 0 2006.231.08:15:18.19#ibcon#enter sib2, iclass 24, count 0 2006.231.08:15:18.19#ibcon#flushed, iclass 24, count 0 2006.231.08:15:18.19#ibcon#about to write, iclass 24, count 0 2006.231.08:15:18.19#ibcon#wrote, iclass 24, count 0 2006.231.08:15:18.19#ibcon#about to read 3, iclass 24, count 0 2006.231.08:15:18.22#ibcon#read 3, iclass 24, count 0 2006.231.08:15:18.22#ibcon#about to read 4, iclass 24, count 0 2006.231.08:15:18.22#ibcon#read 4, iclass 24, count 0 2006.231.08:15:18.23#ibcon#about to read 5, iclass 24, count 0 2006.231.08:15:18.23#ibcon#read 5, iclass 24, count 0 2006.231.08:15:18.23#ibcon#about to read 6, iclass 24, count 0 2006.231.08:15:18.23#ibcon#read 6, iclass 24, count 0 2006.231.08:15:18.23#ibcon#end of sib2, iclass 24, count 0 2006.231.08:15:18.23#ibcon#*after write, iclass 24, count 0 2006.231.08:15:18.23#ibcon#*before return 0, iclass 24, count 0 2006.231.08:15:18.23#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:15:18.23#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:15:18.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.08:15:18.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.08:15:18.23$vc4f8/valo=2,572.99 2006.231.08:15:18.23#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.08:15:18.23#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.08:15:18.23#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:18.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:15:18.23#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:15:18.23#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:15:18.23#ibcon#enter wrdev, iclass 26, count 0 2006.231.08:15:18.23#ibcon#first serial, iclass 26, count 0 2006.231.08:15:18.23#ibcon#enter sib2, iclass 26, count 0 2006.231.08:15:18.23#ibcon#flushed, iclass 26, count 0 2006.231.08:15:18.23#ibcon#about to write, iclass 26, count 0 2006.231.08:15:18.23#ibcon#wrote, iclass 26, count 0 2006.231.08:15:18.23#ibcon#about to read 3, iclass 26, count 0 2006.231.08:15:18.24#ibcon#read 3, iclass 26, count 0 2006.231.08:15:18.24#ibcon#about to read 4, iclass 26, count 0 2006.231.08:15:18.24#ibcon#read 4, iclass 26, count 0 2006.231.08:15:18.24#ibcon#about to read 5, iclass 26, count 0 2006.231.08:15:18.24#ibcon#read 5, iclass 26, count 0 2006.231.08:15:18.24#ibcon#about to read 6, iclass 26, count 0 2006.231.08:15:18.24#ibcon#read 6, iclass 26, count 0 2006.231.08:15:18.24#ibcon#end of sib2, iclass 26, count 0 2006.231.08:15:18.24#ibcon#*mode == 0, iclass 26, count 0 2006.231.08:15:18.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.08:15:18.24#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:15:18.24#ibcon#*before write, iclass 26, count 0 2006.231.08:15:18.24#ibcon#enter sib2, iclass 26, count 0 2006.231.08:15:18.24#ibcon#flushed, iclass 26, count 0 2006.231.08:15:18.24#ibcon#about to write, iclass 26, count 0 2006.231.08:15:18.24#ibcon#wrote, iclass 26, count 0 2006.231.08:15:18.24#ibcon#about to read 3, iclass 26, count 0 2006.231.08:15:18.28#ibcon#read 3, iclass 26, count 0 2006.231.08:15:18.28#ibcon#about to read 4, iclass 26, count 0 2006.231.08:15:18.28#ibcon#read 4, iclass 26, count 0 2006.231.08:15:18.28#ibcon#about to read 5, iclass 26, count 0 2006.231.08:15:18.28#ibcon#read 5, iclass 26, count 0 2006.231.08:15:18.28#ibcon#about to read 6, iclass 26, count 0 2006.231.08:15:18.28#ibcon#read 6, iclass 26, count 0 2006.231.08:15:18.28#ibcon#end of sib2, iclass 26, count 0 2006.231.08:15:18.28#ibcon#*after write, iclass 26, count 0 2006.231.08:15:18.28#ibcon#*before return 0, iclass 26, count 0 2006.231.08:15:18.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:15:18.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:15:18.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.08:15:18.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.08:15:18.28$vc4f8/va=2,7 2006.231.08:15:18.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.08:15:18.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.08:15:18.28#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:18.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:15:18.35#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:15:18.35#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:15:18.35#ibcon#enter wrdev, iclass 28, count 2 2006.231.08:15:18.35#ibcon#first serial, iclass 28, count 2 2006.231.08:15:18.35#ibcon#enter sib2, iclass 28, count 2 2006.231.08:15:18.35#ibcon#flushed, iclass 28, count 2 2006.231.08:15:18.35#ibcon#about to write, iclass 28, count 2 2006.231.08:15:18.35#ibcon#wrote, iclass 28, count 2 2006.231.08:15:18.35#ibcon#about to read 3, iclass 28, count 2 2006.231.08:15:18.37#ibcon#read 3, iclass 28, count 2 2006.231.08:15:18.37#ibcon#about to read 4, iclass 28, count 2 2006.231.08:15:18.37#ibcon#read 4, iclass 28, count 2 2006.231.08:15:18.37#ibcon#about to read 5, iclass 28, count 2 2006.231.08:15:18.37#ibcon#read 5, iclass 28, count 2 2006.231.08:15:18.37#ibcon#about to read 6, iclass 28, count 2 2006.231.08:15:18.37#ibcon#read 6, iclass 28, count 2 2006.231.08:15:18.37#ibcon#end of sib2, iclass 28, count 2 2006.231.08:15:18.37#ibcon#*mode == 0, iclass 28, count 2 2006.231.08:15:18.37#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.08:15:18.37#ibcon#[25=AT02-07\r\n] 2006.231.08:15:18.37#ibcon#*before write, iclass 28, count 2 2006.231.08:15:18.37#ibcon#enter sib2, iclass 28, count 2 2006.231.08:15:18.37#ibcon#flushed, iclass 28, count 2 2006.231.08:15:18.37#ibcon#about to write, iclass 28, count 2 2006.231.08:15:18.37#ibcon#wrote, iclass 28, count 2 2006.231.08:15:18.37#ibcon#about to read 3, iclass 28, count 2 2006.231.08:15:18.40#ibcon#read 3, iclass 28, count 2 2006.231.08:15:18.40#ibcon#about to read 4, iclass 28, count 2 2006.231.08:15:18.40#ibcon#read 4, iclass 28, count 2 2006.231.08:15:18.40#ibcon#about to read 5, iclass 28, count 2 2006.231.08:15:18.40#ibcon#read 5, iclass 28, count 2 2006.231.08:15:18.40#ibcon#about to read 6, iclass 28, count 2 2006.231.08:15:18.40#ibcon#read 6, iclass 28, count 2 2006.231.08:15:18.40#ibcon#end of sib2, iclass 28, count 2 2006.231.08:15:18.40#ibcon#*after write, iclass 28, count 2 2006.231.08:15:18.40#ibcon#*before return 0, iclass 28, count 2 2006.231.08:15:18.40#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:15:18.40#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:15:18.40#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.08:15:18.40#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:18.40#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:15:18.52#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:15:18.52#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:15:18.52#ibcon#enter wrdev, iclass 28, count 0 2006.231.08:15:18.52#ibcon#first serial, iclass 28, count 0 2006.231.08:15:18.52#ibcon#enter sib2, iclass 28, count 0 2006.231.08:15:18.52#ibcon#flushed, iclass 28, count 0 2006.231.08:15:18.52#ibcon#about to write, iclass 28, count 0 2006.231.08:15:18.52#ibcon#wrote, iclass 28, count 0 2006.231.08:15:18.52#ibcon#about to read 3, iclass 28, count 0 2006.231.08:15:18.54#ibcon#read 3, iclass 28, count 0 2006.231.08:15:18.54#ibcon#about to read 4, iclass 28, count 0 2006.231.08:15:18.54#ibcon#read 4, iclass 28, count 0 2006.231.08:15:18.54#ibcon#about to read 5, iclass 28, count 0 2006.231.08:15:18.54#ibcon#read 5, iclass 28, count 0 2006.231.08:15:18.54#ibcon#about to read 6, iclass 28, count 0 2006.231.08:15:18.54#ibcon#read 6, iclass 28, count 0 2006.231.08:15:18.54#ibcon#end of sib2, iclass 28, count 0 2006.231.08:15:18.54#ibcon#*mode == 0, iclass 28, count 0 2006.231.08:15:18.54#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.08:15:18.54#ibcon#[25=USB\r\n] 2006.231.08:15:18.54#ibcon#*before write, iclass 28, count 0 2006.231.08:15:18.54#ibcon#enter sib2, iclass 28, count 0 2006.231.08:15:18.54#ibcon#flushed, iclass 28, count 0 2006.231.08:15:18.54#ibcon#about to write, iclass 28, count 0 2006.231.08:15:18.54#ibcon#wrote, iclass 28, count 0 2006.231.08:15:18.54#ibcon#about to read 3, iclass 28, count 0 2006.231.08:15:18.57#ibcon#read 3, iclass 28, count 0 2006.231.08:15:18.57#ibcon#about to read 4, iclass 28, count 0 2006.231.08:15:18.57#ibcon#read 4, iclass 28, count 0 2006.231.08:15:18.57#ibcon#about to read 5, iclass 28, count 0 2006.231.08:15:18.57#ibcon#read 5, iclass 28, count 0 2006.231.08:15:18.57#ibcon#about to read 6, iclass 28, count 0 2006.231.08:15:18.57#ibcon#read 6, iclass 28, count 0 2006.231.08:15:18.57#ibcon#end of sib2, iclass 28, count 0 2006.231.08:15:18.57#ibcon#*after write, iclass 28, count 0 2006.231.08:15:18.57#ibcon#*before return 0, iclass 28, count 0 2006.231.08:15:18.57#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:15:18.57#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:15:18.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.08:15:18.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.08:15:18.57$vc4f8/valo=3,672.99 2006.231.08:15:18.57#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.08:15:18.57#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.08:15:18.57#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:18.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:15:18.57#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:15:18.57#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:15:18.57#ibcon#enter wrdev, iclass 30, count 0 2006.231.08:15:18.57#ibcon#first serial, iclass 30, count 0 2006.231.08:15:18.57#ibcon#enter sib2, iclass 30, count 0 2006.231.08:15:18.57#ibcon#flushed, iclass 30, count 0 2006.231.08:15:18.57#ibcon#about to write, iclass 30, count 0 2006.231.08:15:18.57#ibcon#wrote, iclass 30, count 0 2006.231.08:15:18.57#ibcon#about to read 3, iclass 30, count 0 2006.231.08:15:18.59#ibcon#read 3, iclass 30, count 0 2006.231.08:15:18.59#ibcon#about to read 4, iclass 30, count 0 2006.231.08:15:18.59#ibcon#read 4, iclass 30, count 0 2006.231.08:15:18.59#ibcon#about to read 5, iclass 30, count 0 2006.231.08:15:18.59#ibcon#read 5, iclass 30, count 0 2006.231.08:15:18.59#ibcon#about to read 6, iclass 30, count 0 2006.231.08:15:18.59#ibcon#read 6, iclass 30, count 0 2006.231.08:15:18.59#ibcon#end of sib2, iclass 30, count 0 2006.231.08:15:18.59#ibcon#*mode == 0, iclass 30, count 0 2006.231.08:15:18.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.08:15:18.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:15:18.59#ibcon#*before write, iclass 30, count 0 2006.231.08:15:18.59#ibcon#enter sib2, iclass 30, count 0 2006.231.08:15:18.59#ibcon#flushed, iclass 30, count 0 2006.231.08:15:18.59#ibcon#about to write, iclass 30, count 0 2006.231.08:15:18.59#ibcon#wrote, iclass 30, count 0 2006.231.08:15:18.59#ibcon#about to read 3, iclass 30, count 0 2006.231.08:15:18.63#ibcon#read 3, iclass 30, count 0 2006.231.08:15:18.63#ibcon#about to read 4, iclass 30, count 0 2006.231.08:15:18.63#ibcon#read 4, iclass 30, count 0 2006.231.08:15:18.63#ibcon#about to read 5, iclass 30, count 0 2006.231.08:15:18.63#ibcon#read 5, iclass 30, count 0 2006.231.08:15:18.63#ibcon#about to read 6, iclass 30, count 0 2006.231.08:15:18.63#ibcon#read 6, iclass 30, count 0 2006.231.08:15:18.63#ibcon#end of sib2, iclass 30, count 0 2006.231.08:15:18.63#ibcon#*after write, iclass 30, count 0 2006.231.08:15:18.63#ibcon#*before return 0, iclass 30, count 0 2006.231.08:15:18.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:15:18.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:15:18.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.08:15:18.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.08:15:18.63$vc4f8/va=3,8 2006.231.08:15:18.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.08:15:18.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.08:15:18.63#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:18.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:15:18.70#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:15:18.70#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:15:18.70#ibcon#enter wrdev, iclass 32, count 2 2006.231.08:15:18.70#ibcon#first serial, iclass 32, count 2 2006.231.08:15:18.70#ibcon#enter sib2, iclass 32, count 2 2006.231.08:15:18.70#ibcon#flushed, iclass 32, count 2 2006.231.08:15:18.70#ibcon#about to write, iclass 32, count 2 2006.231.08:15:18.70#ibcon#wrote, iclass 32, count 2 2006.231.08:15:18.70#ibcon#about to read 3, iclass 32, count 2 2006.231.08:15:18.71#ibcon#read 3, iclass 32, count 2 2006.231.08:15:18.71#ibcon#about to read 4, iclass 32, count 2 2006.231.08:15:18.71#ibcon#read 4, iclass 32, count 2 2006.231.08:15:18.71#ibcon#about to read 5, iclass 32, count 2 2006.231.08:15:18.71#ibcon#read 5, iclass 32, count 2 2006.231.08:15:18.71#ibcon#about to read 6, iclass 32, count 2 2006.231.08:15:18.71#ibcon#read 6, iclass 32, count 2 2006.231.08:15:18.71#ibcon#end of sib2, iclass 32, count 2 2006.231.08:15:18.71#ibcon#*mode == 0, iclass 32, count 2 2006.231.08:15:18.71#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.08:15:18.71#ibcon#[25=AT03-08\r\n] 2006.231.08:15:18.71#ibcon#*before write, iclass 32, count 2 2006.231.08:15:18.71#ibcon#enter sib2, iclass 32, count 2 2006.231.08:15:18.71#ibcon#flushed, iclass 32, count 2 2006.231.08:15:18.71#ibcon#about to write, iclass 32, count 2 2006.231.08:15:18.71#ibcon#wrote, iclass 32, count 2 2006.231.08:15:18.71#ibcon#about to read 3, iclass 32, count 2 2006.231.08:15:18.74#ibcon#read 3, iclass 32, count 2 2006.231.08:15:18.74#ibcon#about to read 4, iclass 32, count 2 2006.231.08:15:18.74#ibcon#read 4, iclass 32, count 2 2006.231.08:15:18.74#ibcon#about to read 5, iclass 32, count 2 2006.231.08:15:18.74#ibcon#read 5, iclass 32, count 2 2006.231.08:15:18.74#ibcon#about to read 6, iclass 32, count 2 2006.231.08:15:18.74#ibcon#read 6, iclass 32, count 2 2006.231.08:15:18.74#ibcon#end of sib2, iclass 32, count 2 2006.231.08:15:18.74#ibcon#*after write, iclass 32, count 2 2006.231.08:15:18.74#ibcon#*before return 0, iclass 32, count 2 2006.231.08:15:18.74#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:15:18.74#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:15:18.74#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.08:15:18.74#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:18.74#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:15:18.86#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:15:18.86#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:15:18.86#ibcon#enter wrdev, iclass 32, count 0 2006.231.08:15:18.86#ibcon#first serial, iclass 32, count 0 2006.231.08:15:18.86#ibcon#enter sib2, iclass 32, count 0 2006.231.08:15:18.86#ibcon#flushed, iclass 32, count 0 2006.231.08:15:18.86#ibcon#about to write, iclass 32, count 0 2006.231.08:15:18.86#ibcon#wrote, iclass 32, count 0 2006.231.08:15:18.86#ibcon#about to read 3, iclass 32, count 0 2006.231.08:15:18.88#ibcon#read 3, iclass 32, count 0 2006.231.08:15:18.88#ibcon#about to read 4, iclass 32, count 0 2006.231.08:15:18.88#ibcon#read 4, iclass 32, count 0 2006.231.08:15:18.88#ibcon#about to read 5, iclass 32, count 0 2006.231.08:15:18.88#ibcon#read 5, iclass 32, count 0 2006.231.08:15:18.88#ibcon#about to read 6, iclass 32, count 0 2006.231.08:15:18.88#ibcon#read 6, iclass 32, count 0 2006.231.08:15:18.88#ibcon#end of sib2, iclass 32, count 0 2006.231.08:15:18.88#ibcon#*mode == 0, iclass 32, count 0 2006.231.08:15:18.88#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.08:15:18.88#ibcon#[25=USB\r\n] 2006.231.08:15:18.88#ibcon#*before write, iclass 32, count 0 2006.231.08:15:18.88#ibcon#enter sib2, iclass 32, count 0 2006.231.08:15:18.88#ibcon#flushed, iclass 32, count 0 2006.231.08:15:18.88#ibcon#about to write, iclass 32, count 0 2006.231.08:15:18.88#ibcon#wrote, iclass 32, count 0 2006.231.08:15:18.88#ibcon#about to read 3, iclass 32, count 0 2006.231.08:15:18.91#ibcon#read 3, iclass 32, count 0 2006.231.08:15:18.91#ibcon#about to read 4, iclass 32, count 0 2006.231.08:15:18.91#ibcon#read 4, iclass 32, count 0 2006.231.08:15:18.91#ibcon#about to read 5, iclass 32, count 0 2006.231.08:15:18.91#ibcon#read 5, iclass 32, count 0 2006.231.08:15:18.91#ibcon#about to read 6, iclass 32, count 0 2006.231.08:15:18.91#ibcon#read 6, iclass 32, count 0 2006.231.08:15:18.91#ibcon#end of sib2, iclass 32, count 0 2006.231.08:15:18.91#ibcon#*after write, iclass 32, count 0 2006.231.08:15:18.91#ibcon#*before return 0, iclass 32, count 0 2006.231.08:15:18.91#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:15:18.91#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:15:18.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.08:15:18.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.08:15:18.91$vc4f8/valo=4,832.99 2006.231.08:15:18.91#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.08:15:18.91#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.08:15:18.91#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:18.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:15:18.91#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:15:18.91#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:15:18.91#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:15:18.91#ibcon#first serial, iclass 34, count 0 2006.231.08:15:18.91#ibcon#enter sib2, iclass 34, count 0 2006.231.08:15:18.91#ibcon#flushed, iclass 34, count 0 2006.231.08:15:18.91#ibcon#about to write, iclass 34, count 0 2006.231.08:15:18.91#ibcon#wrote, iclass 34, count 0 2006.231.08:15:18.91#ibcon#about to read 3, iclass 34, count 0 2006.231.08:15:18.93#ibcon#read 3, iclass 34, count 0 2006.231.08:15:18.93#ibcon#about to read 4, iclass 34, count 0 2006.231.08:15:18.93#ibcon#read 4, iclass 34, count 0 2006.231.08:15:18.93#ibcon#about to read 5, iclass 34, count 0 2006.231.08:15:18.93#ibcon#read 5, iclass 34, count 0 2006.231.08:15:18.93#ibcon#about to read 6, iclass 34, count 0 2006.231.08:15:18.93#ibcon#read 6, iclass 34, count 0 2006.231.08:15:18.93#ibcon#end of sib2, iclass 34, count 0 2006.231.08:15:18.93#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:15:18.93#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:15:18.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:15:18.93#ibcon#*before write, iclass 34, count 0 2006.231.08:15:18.93#ibcon#enter sib2, iclass 34, count 0 2006.231.08:15:18.93#ibcon#flushed, iclass 34, count 0 2006.231.08:15:18.93#ibcon#about to write, iclass 34, count 0 2006.231.08:15:18.93#ibcon#wrote, iclass 34, count 0 2006.231.08:15:18.93#ibcon#about to read 3, iclass 34, count 0 2006.231.08:15:18.97#ibcon#read 3, iclass 34, count 0 2006.231.08:15:18.97#ibcon#about to read 4, iclass 34, count 0 2006.231.08:15:18.97#ibcon#read 4, iclass 34, count 0 2006.231.08:15:18.97#ibcon#about to read 5, iclass 34, count 0 2006.231.08:15:18.97#ibcon#read 5, iclass 34, count 0 2006.231.08:15:18.97#ibcon#about to read 6, iclass 34, count 0 2006.231.08:15:18.97#ibcon#read 6, iclass 34, count 0 2006.231.08:15:18.97#ibcon#end of sib2, iclass 34, count 0 2006.231.08:15:18.97#ibcon#*after write, iclass 34, count 0 2006.231.08:15:18.97#ibcon#*before return 0, iclass 34, count 0 2006.231.08:15:18.97#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:15:18.97#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:15:18.97#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:15:18.97#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:15:18.97$vc4f8/va=4,7 2006.231.08:15:18.97#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.08:15:18.97#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.08:15:18.97#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:18.97#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:15:19.03#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:15:19.03#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:15:19.03#ibcon#enter wrdev, iclass 36, count 2 2006.231.08:15:19.03#ibcon#first serial, iclass 36, count 2 2006.231.08:15:19.03#ibcon#enter sib2, iclass 36, count 2 2006.231.08:15:19.03#ibcon#flushed, iclass 36, count 2 2006.231.08:15:19.03#ibcon#about to write, iclass 36, count 2 2006.231.08:15:19.03#ibcon#wrote, iclass 36, count 2 2006.231.08:15:19.03#ibcon#about to read 3, iclass 36, count 2 2006.231.08:15:19.05#ibcon#read 3, iclass 36, count 2 2006.231.08:15:19.05#ibcon#about to read 4, iclass 36, count 2 2006.231.08:15:19.05#ibcon#read 4, iclass 36, count 2 2006.231.08:15:19.05#ibcon#about to read 5, iclass 36, count 2 2006.231.08:15:19.05#ibcon#read 5, iclass 36, count 2 2006.231.08:15:19.05#ibcon#about to read 6, iclass 36, count 2 2006.231.08:15:19.05#ibcon#read 6, iclass 36, count 2 2006.231.08:15:19.05#ibcon#end of sib2, iclass 36, count 2 2006.231.08:15:19.05#ibcon#*mode == 0, iclass 36, count 2 2006.231.08:15:19.05#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.08:15:19.05#ibcon#[25=AT04-07\r\n] 2006.231.08:15:19.05#ibcon#*before write, iclass 36, count 2 2006.231.08:15:19.05#ibcon#enter sib2, iclass 36, count 2 2006.231.08:15:19.05#ibcon#flushed, iclass 36, count 2 2006.231.08:15:19.05#ibcon#about to write, iclass 36, count 2 2006.231.08:15:19.05#ibcon#wrote, iclass 36, count 2 2006.231.08:15:19.05#ibcon#about to read 3, iclass 36, count 2 2006.231.08:15:19.08#ibcon#read 3, iclass 36, count 2 2006.231.08:15:19.08#ibcon#about to read 4, iclass 36, count 2 2006.231.08:15:19.08#ibcon#read 4, iclass 36, count 2 2006.231.08:15:19.08#ibcon#about to read 5, iclass 36, count 2 2006.231.08:15:19.08#ibcon#read 5, iclass 36, count 2 2006.231.08:15:19.08#ibcon#about to read 6, iclass 36, count 2 2006.231.08:15:19.08#ibcon#read 6, iclass 36, count 2 2006.231.08:15:19.08#ibcon#end of sib2, iclass 36, count 2 2006.231.08:15:19.08#ibcon#*after write, iclass 36, count 2 2006.231.08:15:19.08#ibcon#*before return 0, iclass 36, count 2 2006.231.08:15:19.08#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:15:19.08#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:15:19.08#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.08:15:19.08#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:19.08#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:15:19.20#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:15:19.20#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:15:19.20#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:15:19.20#ibcon#first serial, iclass 36, count 0 2006.231.08:15:19.20#ibcon#enter sib2, iclass 36, count 0 2006.231.08:15:19.20#ibcon#flushed, iclass 36, count 0 2006.231.08:15:19.20#ibcon#about to write, iclass 36, count 0 2006.231.08:15:19.20#ibcon#wrote, iclass 36, count 0 2006.231.08:15:19.20#ibcon#about to read 3, iclass 36, count 0 2006.231.08:15:19.22#ibcon#read 3, iclass 36, count 0 2006.231.08:15:19.22#ibcon#about to read 4, iclass 36, count 0 2006.231.08:15:19.22#ibcon#read 4, iclass 36, count 0 2006.231.08:15:19.22#ibcon#about to read 5, iclass 36, count 0 2006.231.08:15:19.22#ibcon#read 5, iclass 36, count 0 2006.231.08:15:19.22#ibcon#about to read 6, iclass 36, count 0 2006.231.08:15:19.22#ibcon#read 6, iclass 36, count 0 2006.231.08:15:19.22#ibcon#end of sib2, iclass 36, count 0 2006.231.08:15:19.22#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:15:19.22#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:15:19.22#ibcon#[25=USB\r\n] 2006.231.08:15:19.22#ibcon#*before write, iclass 36, count 0 2006.231.08:15:19.22#ibcon#enter sib2, iclass 36, count 0 2006.231.08:15:19.22#ibcon#flushed, iclass 36, count 0 2006.231.08:15:19.22#ibcon#about to write, iclass 36, count 0 2006.231.08:15:19.22#ibcon#wrote, iclass 36, count 0 2006.231.08:15:19.22#ibcon#about to read 3, iclass 36, count 0 2006.231.08:15:19.25#ibcon#read 3, iclass 36, count 0 2006.231.08:15:19.25#ibcon#about to read 4, iclass 36, count 0 2006.231.08:15:19.25#ibcon#read 4, iclass 36, count 0 2006.231.08:15:19.25#ibcon#about to read 5, iclass 36, count 0 2006.231.08:15:19.25#ibcon#read 5, iclass 36, count 0 2006.231.08:15:19.25#ibcon#about to read 6, iclass 36, count 0 2006.231.08:15:19.25#ibcon#read 6, iclass 36, count 0 2006.231.08:15:19.25#ibcon#end of sib2, iclass 36, count 0 2006.231.08:15:19.25#ibcon#*after write, iclass 36, count 0 2006.231.08:15:19.25#ibcon#*before return 0, iclass 36, count 0 2006.231.08:15:19.25#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:15:19.25#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:15:19.25#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:15:19.25#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:15:19.25$vc4f8/valo=5,652.99 2006.231.08:15:19.25#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.08:15:19.25#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.08:15:19.25#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:19.25#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:15:19.25#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:15:19.25#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:15:19.25#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:15:19.25#ibcon#first serial, iclass 38, count 0 2006.231.08:15:19.25#ibcon#enter sib2, iclass 38, count 0 2006.231.08:15:19.25#ibcon#flushed, iclass 38, count 0 2006.231.08:15:19.25#ibcon#about to write, iclass 38, count 0 2006.231.08:15:19.25#ibcon#wrote, iclass 38, count 0 2006.231.08:15:19.25#ibcon#about to read 3, iclass 38, count 0 2006.231.08:15:19.27#ibcon#read 3, iclass 38, count 0 2006.231.08:15:19.27#ibcon#about to read 4, iclass 38, count 0 2006.231.08:15:19.27#ibcon#read 4, iclass 38, count 0 2006.231.08:15:19.27#ibcon#about to read 5, iclass 38, count 0 2006.231.08:15:19.27#ibcon#read 5, iclass 38, count 0 2006.231.08:15:19.27#ibcon#about to read 6, iclass 38, count 0 2006.231.08:15:19.27#ibcon#read 6, iclass 38, count 0 2006.231.08:15:19.27#ibcon#end of sib2, iclass 38, count 0 2006.231.08:15:19.27#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:15:19.27#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:15:19.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:15:19.27#ibcon#*before write, iclass 38, count 0 2006.231.08:15:19.27#ibcon#enter sib2, iclass 38, count 0 2006.231.08:15:19.27#ibcon#flushed, iclass 38, count 0 2006.231.08:15:19.27#ibcon#about to write, iclass 38, count 0 2006.231.08:15:19.27#ibcon#wrote, iclass 38, count 0 2006.231.08:15:19.27#ibcon#about to read 3, iclass 38, count 0 2006.231.08:15:19.31#ibcon#read 3, iclass 38, count 0 2006.231.08:15:19.31#ibcon#about to read 4, iclass 38, count 0 2006.231.08:15:19.31#ibcon#read 4, iclass 38, count 0 2006.231.08:15:19.31#ibcon#about to read 5, iclass 38, count 0 2006.231.08:15:19.31#ibcon#read 5, iclass 38, count 0 2006.231.08:15:19.31#ibcon#about to read 6, iclass 38, count 0 2006.231.08:15:19.31#ibcon#read 6, iclass 38, count 0 2006.231.08:15:19.31#ibcon#end of sib2, iclass 38, count 0 2006.231.08:15:19.31#ibcon#*after write, iclass 38, count 0 2006.231.08:15:19.31#ibcon#*before return 0, iclass 38, count 0 2006.231.08:15:19.31#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:15:19.31#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:15:19.31#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:15:19.31#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:15:19.31$vc4f8/va=5,7 2006.231.08:15:19.31#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.08:15:19.31#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.08:15:19.31#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:19.31#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:15:19.37#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:15:19.37#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:15:19.37#ibcon#enter wrdev, iclass 40, count 2 2006.231.08:15:19.37#ibcon#first serial, iclass 40, count 2 2006.231.08:15:19.37#ibcon#enter sib2, iclass 40, count 2 2006.231.08:15:19.37#ibcon#flushed, iclass 40, count 2 2006.231.08:15:19.37#ibcon#about to write, iclass 40, count 2 2006.231.08:15:19.37#ibcon#wrote, iclass 40, count 2 2006.231.08:15:19.37#ibcon#about to read 3, iclass 40, count 2 2006.231.08:15:19.39#ibcon#read 3, iclass 40, count 2 2006.231.08:15:19.39#ibcon#about to read 4, iclass 40, count 2 2006.231.08:15:19.39#ibcon#read 4, iclass 40, count 2 2006.231.08:15:19.39#ibcon#about to read 5, iclass 40, count 2 2006.231.08:15:19.39#ibcon#read 5, iclass 40, count 2 2006.231.08:15:19.39#ibcon#about to read 6, iclass 40, count 2 2006.231.08:15:19.39#ibcon#read 6, iclass 40, count 2 2006.231.08:15:19.39#ibcon#end of sib2, iclass 40, count 2 2006.231.08:15:19.39#ibcon#*mode == 0, iclass 40, count 2 2006.231.08:15:19.39#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.08:15:19.39#ibcon#[25=AT05-07\r\n] 2006.231.08:15:19.39#ibcon#*before write, iclass 40, count 2 2006.231.08:15:19.39#ibcon#enter sib2, iclass 40, count 2 2006.231.08:15:19.39#ibcon#flushed, iclass 40, count 2 2006.231.08:15:19.39#ibcon#about to write, iclass 40, count 2 2006.231.08:15:19.39#ibcon#wrote, iclass 40, count 2 2006.231.08:15:19.39#ibcon#about to read 3, iclass 40, count 2 2006.231.08:15:19.42#ibcon#read 3, iclass 40, count 2 2006.231.08:15:19.42#ibcon#about to read 4, iclass 40, count 2 2006.231.08:15:19.42#ibcon#read 4, iclass 40, count 2 2006.231.08:15:19.42#ibcon#about to read 5, iclass 40, count 2 2006.231.08:15:19.42#ibcon#read 5, iclass 40, count 2 2006.231.08:15:19.42#ibcon#about to read 6, iclass 40, count 2 2006.231.08:15:19.42#ibcon#read 6, iclass 40, count 2 2006.231.08:15:19.42#ibcon#end of sib2, iclass 40, count 2 2006.231.08:15:19.42#ibcon#*after write, iclass 40, count 2 2006.231.08:15:19.42#ibcon#*before return 0, iclass 40, count 2 2006.231.08:15:19.42#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:15:19.42#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:15:19.42#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.08:15:19.42#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:19.42#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:15:19.54#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:15:19.54#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:15:19.54#ibcon#enter wrdev, iclass 40, count 0 2006.231.08:15:19.54#ibcon#first serial, iclass 40, count 0 2006.231.08:15:19.54#ibcon#enter sib2, iclass 40, count 0 2006.231.08:15:19.54#ibcon#flushed, iclass 40, count 0 2006.231.08:15:19.54#ibcon#about to write, iclass 40, count 0 2006.231.08:15:19.54#ibcon#wrote, iclass 40, count 0 2006.231.08:15:19.54#ibcon#about to read 3, iclass 40, count 0 2006.231.08:15:19.56#ibcon#read 3, iclass 40, count 0 2006.231.08:15:19.56#ibcon#about to read 4, iclass 40, count 0 2006.231.08:15:19.56#ibcon#read 4, iclass 40, count 0 2006.231.08:15:19.56#ibcon#about to read 5, iclass 40, count 0 2006.231.08:15:19.56#ibcon#read 5, iclass 40, count 0 2006.231.08:15:19.56#ibcon#about to read 6, iclass 40, count 0 2006.231.08:15:19.56#ibcon#read 6, iclass 40, count 0 2006.231.08:15:19.56#ibcon#end of sib2, iclass 40, count 0 2006.231.08:15:19.56#ibcon#*mode == 0, iclass 40, count 0 2006.231.08:15:19.56#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.08:15:19.56#ibcon#[25=USB\r\n] 2006.231.08:15:19.56#ibcon#*before write, iclass 40, count 0 2006.231.08:15:19.56#ibcon#enter sib2, iclass 40, count 0 2006.231.08:15:19.56#ibcon#flushed, iclass 40, count 0 2006.231.08:15:19.56#ibcon#about to write, iclass 40, count 0 2006.231.08:15:19.56#ibcon#wrote, iclass 40, count 0 2006.231.08:15:19.56#ibcon#about to read 3, iclass 40, count 0 2006.231.08:15:19.61#ibcon#read 3, iclass 40, count 0 2006.231.08:15:19.61#ibcon#about to read 4, iclass 40, count 0 2006.231.08:15:19.61#ibcon#read 4, iclass 40, count 0 2006.231.08:15:19.61#ibcon#about to read 5, iclass 40, count 0 2006.231.08:15:19.61#ibcon#read 5, iclass 40, count 0 2006.231.08:15:19.61#ibcon#about to read 6, iclass 40, count 0 2006.231.08:15:19.61#ibcon#read 6, iclass 40, count 0 2006.231.08:15:19.61#ibcon#end of sib2, iclass 40, count 0 2006.231.08:15:19.61#ibcon#*after write, iclass 40, count 0 2006.231.08:15:19.61#ibcon#*before return 0, iclass 40, count 0 2006.231.08:15:19.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:15:19.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:15:19.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.08:15:19.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.08:15:19.61$vc4f8/valo=6,772.99 2006.231.08:15:19.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.08:15:19.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.08:15:19.61#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:19.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:15:19.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:15:19.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:15:19.61#ibcon#enter wrdev, iclass 4, count 0 2006.231.08:15:19.61#ibcon#first serial, iclass 4, count 0 2006.231.08:15:19.61#ibcon#enter sib2, iclass 4, count 0 2006.231.08:15:19.61#ibcon#flushed, iclass 4, count 0 2006.231.08:15:19.61#ibcon#about to write, iclass 4, count 0 2006.231.08:15:19.61#ibcon#wrote, iclass 4, count 0 2006.231.08:15:19.61#ibcon#about to read 3, iclass 4, count 0 2006.231.08:15:19.62#ibcon#read 3, iclass 4, count 0 2006.231.08:15:19.63#ibcon#about to read 4, iclass 4, count 0 2006.231.08:15:19.63#ibcon#read 4, iclass 4, count 0 2006.231.08:15:19.63#ibcon#about to read 5, iclass 4, count 0 2006.231.08:15:19.63#ibcon#read 5, iclass 4, count 0 2006.231.08:15:19.63#ibcon#about to read 6, iclass 4, count 0 2006.231.08:15:19.63#ibcon#read 6, iclass 4, count 0 2006.231.08:15:19.63#ibcon#end of sib2, iclass 4, count 0 2006.231.08:15:19.63#ibcon#*mode == 0, iclass 4, count 0 2006.231.08:15:19.63#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.08:15:19.63#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:15:19.63#ibcon#*before write, iclass 4, count 0 2006.231.08:15:19.63#ibcon#enter sib2, iclass 4, count 0 2006.231.08:15:19.63#ibcon#flushed, iclass 4, count 0 2006.231.08:15:19.63#ibcon#about to write, iclass 4, count 0 2006.231.08:15:19.63#ibcon#wrote, iclass 4, count 0 2006.231.08:15:19.63#ibcon#about to read 3, iclass 4, count 0 2006.231.08:15:19.66#ibcon#read 3, iclass 4, count 0 2006.231.08:15:19.66#ibcon#about to read 4, iclass 4, count 0 2006.231.08:15:19.66#ibcon#read 4, iclass 4, count 0 2006.231.08:15:19.66#ibcon#about to read 5, iclass 4, count 0 2006.231.08:15:19.66#ibcon#read 5, iclass 4, count 0 2006.231.08:15:19.66#ibcon#about to read 6, iclass 4, count 0 2006.231.08:15:19.66#ibcon#read 6, iclass 4, count 0 2006.231.08:15:19.66#ibcon#end of sib2, iclass 4, count 0 2006.231.08:15:19.66#ibcon#*after write, iclass 4, count 0 2006.231.08:15:19.66#ibcon#*before return 0, iclass 4, count 0 2006.231.08:15:19.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:15:19.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:15:19.66#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.08:15:19.66#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.08:15:19.66$vc4f8/va=6,6 2006.231.08:15:19.66#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.08:15:19.66#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.08:15:19.66#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:19.66#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:15:19.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:15:19.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:15:19.73#ibcon#enter wrdev, iclass 6, count 2 2006.231.08:15:19.73#ibcon#first serial, iclass 6, count 2 2006.231.08:15:19.73#ibcon#enter sib2, iclass 6, count 2 2006.231.08:15:19.73#ibcon#flushed, iclass 6, count 2 2006.231.08:15:19.73#ibcon#about to write, iclass 6, count 2 2006.231.08:15:19.73#ibcon#wrote, iclass 6, count 2 2006.231.08:15:19.73#ibcon#about to read 3, iclass 6, count 2 2006.231.08:15:19.75#ibcon#read 3, iclass 6, count 2 2006.231.08:15:19.75#ibcon#about to read 4, iclass 6, count 2 2006.231.08:15:19.75#ibcon#read 4, iclass 6, count 2 2006.231.08:15:19.75#ibcon#about to read 5, iclass 6, count 2 2006.231.08:15:19.75#ibcon#read 5, iclass 6, count 2 2006.231.08:15:19.75#ibcon#about to read 6, iclass 6, count 2 2006.231.08:15:19.75#ibcon#read 6, iclass 6, count 2 2006.231.08:15:19.75#ibcon#end of sib2, iclass 6, count 2 2006.231.08:15:19.75#ibcon#*mode == 0, iclass 6, count 2 2006.231.08:15:19.75#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.08:15:19.75#ibcon#[25=AT06-06\r\n] 2006.231.08:15:19.75#ibcon#*before write, iclass 6, count 2 2006.231.08:15:19.75#ibcon#enter sib2, iclass 6, count 2 2006.231.08:15:19.75#ibcon#flushed, iclass 6, count 2 2006.231.08:15:19.75#ibcon#about to write, iclass 6, count 2 2006.231.08:15:19.75#ibcon#wrote, iclass 6, count 2 2006.231.08:15:19.75#ibcon#about to read 3, iclass 6, count 2 2006.231.08:15:19.78#ibcon#read 3, iclass 6, count 2 2006.231.08:15:19.78#ibcon#about to read 4, iclass 6, count 2 2006.231.08:15:19.78#ibcon#read 4, iclass 6, count 2 2006.231.08:15:19.78#ibcon#about to read 5, iclass 6, count 2 2006.231.08:15:19.78#ibcon#read 5, iclass 6, count 2 2006.231.08:15:19.78#ibcon#about to read 6, iclass 6, count 2 2006.231.08:15:19.78#ibcon#read 6, iclass 6, count 2 2006.231.08:15:19.78#ibcon#end of sib2, iclass 6, count 2 2006.231.08:15:19.78#ibcon#*after write, iclass 6, count 2 2006.231.08:15:19.78#ibcon#*before return 0, iclass 6, count 2 2006.231.08:15:19.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:15:19.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:15:19.78#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.08:15:19.78#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:19.78#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:15:19.90#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:15:19.90#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:15:19.90#ibcon#enter wrdev, iclass 6, count 0 2006.231.08:15:19.90#ibcon#first serial, iclass 6, count 0 2006.231.08:15:19.90#ibcon#enter sib2, iclass 6, count 0 2006.231.08:15:19.90#ibcon#flushed, iclass 6, count 0 2006.231.08:15:19.90#ibcon#about to write, iclass 6, count 0 2006.231.08:15:19.90#ibcon#wrote, iclass 6, count 0 2006.231.08:15:19.90#ibcon#about to read 3, iclass 6, count 0 2006.231.08:15:19.92#ibcon#read 3, iclass 6, count 0 2006.231.08:15:19.92#ibcon#about to read 4, iclass 6, count 0 2006.231.08:15:19.92#ibcon#read 4, iclass 6, count 0 2006.231.08:15:19.92#ibcon#about to read 5, iclass 6, count 0 2006.231.08:15:19.92#ibcon#read 5, iclass 6, count 0 2006.231.08:15:19.92#ibcon#about to read 6, iclass 6, count 0 2006.231.08:15:19.92#ibcon#read 6, iclass 6, count 0 2006.231.08:15:19.92#ibcon#end of sib2, iclass 6, count 0 2006.231.08:15:19.92#ibcon#*mode == 0, iclass 6, count 0 2006.231.08:15:19.92#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.08:15:19.92#ibcon#[25=USB\r\n] 2006.231.08:15:19.92#ibcon#*before write, iclass 6, count 0 2006.231.08:15:19.92#ibcon#enter sib2, iclass 6, count 0 2006.231.08:15:19.92#ibcon#flushed, iclass 6, count 0 2006.231.08:15:19.92#ibcon#about to write, iclass 6, count 0 2006.231.08:15:19.92#ibcon#wrote, iclass 6, count 0 2006.231.08:15:19.92#ibcon#about to read 3, iclass 6, count 0 2006.231.08:15:19.95#ibcon#read 3, iclass 6, count 0 2006.231.08:15:19.95#ibcon#about to read 4, iclass 6, count 0 2006.231.08:15:19.95#ibcon#read 4, iclass 6, count 0 2006.231.08:15:19.95#ibcon#about to read 5, iclass 6, count 0 2006.231.08:15:19.95#ibcon#read 5, iclass 6, count 0 2006.231.08:15:19.95#ibcon#about to read 6, iclass 6, count 0 2006.231.08:15:19.95#ibcon#read 6, iclass 6, count 0 2006.231.08:15:19.95#ibcon#end of sib2, iclass 6, count 0 2006.231.08:15:19.95#ibcon#*after write, iclass 6, count 0 2006.231.08:15:19.95#ibcon#*before return 0, iclass 6, count 0 2006.231.08:15:19.95#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:15:19.95#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:15:19.95#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.08:15:19.95#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.08:15:19.95$vc4f8/valo=7,832.99 2006.231.08:15:19.95#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.08:15:19.95#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.08:15:19.95#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:19.95#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:15:19.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:15:19.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:15:19.95#ibcon#enter wrdev, iclass 10, count 0 2006.231.08:15:19.95#ibcon#first serial, iclass 10, count 0 2006.231.08:15:19.95#ibcon#enter sib2, iclass 10, count 0 2006.231.08:15:19.95#ibcon#flushed, iclass 10, count 0 2006.231.08:15:19.95#ibcon#about to write, iclass 10, count 0 2006.231.08:15:19.95#ibcon#wrote, iclass 10, count 0 2006.231.08:15:19.95#ibcon#about to read 3, iclass 10, count 0 2006.231.08:15:19.97#ibcon#read 3, iclass 10, count 0 2006.231.08:15:19.97#ibcon#about to read 4, iclass 10, count 0 2006.231.08:15:19.97#ibcon#read 4, iclass 10, count 0 2006.231.08:15:19.97#ibcon#about to read 5, iclass 10, count 0 2006.231.08:15:19.97#ibcon#read 5, iclass 10, count 0 2006.231.08:15:19.97#ibcon#about to read 6, iclass 10, count 0 2006.231.08:15:19.97#ibcon#read 6, iclass 10, count 0 2006.231.08:15:19.97#ibcon#end of sib2, iclass 10, count 0 2006.231.08:15:19.97#ibcon#*mode == 0, iclass 10, count 0 2006.231.08:15:19.97#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.08:15:19.97#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:15:19.97#ibcon#*before write, iclass 10, count 0 2006.231.08:15:19.97#ibcon#enter sib2, iclass 10, count 0 2006.231.08:15:19.97#ibcon#flushed, iclass 10, count 0 2006.231.08:15:19.97#ibcon#about to write, iclass 10, count 0 2006.231.08:15:19.97#ibcon#wrote, iclass 10, count 0 2006.231.08:15:19.97#ibcon#about to read 3, iclass 10, count 0 2006.231.08:15:20.01#ibcon#read 3, iclass 10, count 0 2006.231.08:15:20.01#ibcon#about to read 4, iclass 10, count 0 2006.231.08:15:20.01#ibcon#read 4, iclass 10, count 0 2006.231.08:15:20.01#ibcon#about to read 5, iclass 10, count 0 2006.231.08:15:20.01#ibcon#read 5, iclass 10, count 0 2006.231.08:15:20.01#ibcon#about to read 6, iclass 10, count 0 2006.231.08:15:20.01#ibcon#read 6, iclass 10, count 0 2006.231.08:15:20.01#ibcon#end of sib2, iclass 10, count 0 2006.231.08:15:20.01#ibcon#*after write, iclass 10, count 0 2006.231.08:15:20.01#ibcon#*before return 0, iclass 10, count 0 2006.231.08:15:20.01#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:15:20.01#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:15:20.01#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.08:15:20.01#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.08:15:20.01$vc4f8/va=7,6 2006.231.08:15:20.01#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.08:15:20.01#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.08:15:20.01#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:20.01#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:15:20.07#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:15:20.07#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:15:20.07#ibcon#enter wrdev, iclass 12, count 2 2006.231.08:15:20.07#ibcon#first serial, iclass 12, count 2 2006.231.08:15:20.07#ibcon#enter sib2, iclass 12, count 2 2006.231.08:15:20.07#ibcon#flushed, iclass 12, count 2 2006.231.08:15:20.07#ibcon#about to write, iclass 12, count 2 2006.231.08:15:20.07#ibcon#wrote, iclass 12, count 2 2006.231.08:15:20.07#ibcon#about to read 3, iclass 12, count 2 2006.231.08:15:20.09#ibcon#read 3, iclass 12, count 2 2006.231.08:15:20.09#ibcon#about to read 4, iclass 12, count 2 2006.231.08:15:20.09#ibcon#read 4, iclass 12, count 2 2006.231.08:15:20.09#ibcon#about to read 5, iclass 12, count 2 2006.231.08:15:20.09#ibcon#read 5, iclass 12, count 2 2006.231.08:15:20.09#ibcon#about to read 6, iclass 12, count 2 2006.231.08:15:20.09#ibcon#read 6, iclass 12, count 2 2006.231.08:15:20.09#ibcon#end of sib2, iclass 12, count 2 2006.231.08:15:20.09#ibcon#*mode == 0, iclass 12, count 2 2006.231.08:15:20.09#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.08:15:20.09#ibcon#[25=AT07-06\r\n] 2006.231.08:15:20.09#ibcon#*before write, iclass 12, count 2 2006.231.08:15:20.09#ibcon#enter sib2, iclass 12, count 2 2006.231.08:15:20.09#ibcon#flushed, iclass 12, count 2 2006.231.08:15:20.09#ibcon#about to write, iclass 12, count 2 2006.231.08:15:20.09#ibcon#wrote, iclass 12, count 2 2006.231.08:15:20.09#ibcon#about to read 3, iclass 12, count 2 2006.231.08:15:20.12#ibcon#read 3, iclass 12, count 2 2006.231.08:15:20.12#ibcon#about to read 4, iclass 12, count 2 2006.231.08:15:20.12#ibcon#read 4, iclass 12, count 2 2006.231.08:15:20.12#ibcon#about to read 5, iclass 12, count 2 2006.231.08:15:20.12#ibcon#read 5, iclass 12, count 2 2006.231.08:15:20.12#ibcon#about to read 6, iclass 12, count 2 2006.231.08:15:20.12#ibcon#read 6, iclass 12, count 2 2006.231.08:15:20.12#ibcon#end of sib2, iclass 12, count 2 2006.231.08:15:20.12#ibcon#*after write, iclass 12, count 2 2006.231.08:15:20.12#ibcon#*before return 0, iclass 12, count 2 2006.231.08:15:20.12#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:15:20.12#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:15:20.12#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.08:15:20.12#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:20.12#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:15:20.24#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:15:20.24#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:15:20.24#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:15:20.24#ibcon#first serial, iclass 12, count 0 2006.231.08:15:20.24#ibcon#enter sib2, iclass 12, count 0 2006.231.08:15:20.24#ibcon#flushed, iclass 12, count 0 2006.231.08:15:20.24#ibcon#about to write, iclass 12, count 0 2006.231.08:15:20.24#ibcon#wrote, iclass 12, count 0 2006.231.08:15:20.24#ibcon#about to read 3, iclass 12, count 0 2006.231.08:15:20.26#ibcon#read 3, iclass 12, count 0 2006.231.08:15:20.26#ibcon#about to read 4, iclass 12, count 0 2006.231.08:15:20.26#ibcon#read 4, iclass 12, count 0 2006.231.08:15:20.26#ibcon#about to read 5, iclass 12, count 0 2006.231.08:15:20.26#ibcon#read 5, iclass 12, count 0 2006.231.08:15:20.26#ibcon#about to read 6, iclass 12, count 0 2006.231.08:15:20.26#ibcon#read 6, iclass 12, count 0 2006.231.08:15:20.26#ibcon#end of sib2, iclass 12, count 0 2006.231.08:15:20.26#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:15:20.26#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:15:20.26#ibcon#[25=USB\r\n] 2006.231.08:15:20.26#ibcon#*before write, iclass 12, count 0 2006.231.08:15:20.26#ibcon#enter sib2, iclass 12, count 0 2006.231.08:15:20.26#ibcon#flushed, iclass 12, count 0 2006.231.08:15:20.26#ibcon#about to write, iclass 12, count 0 2006.231.08:15:20.26#ibcon#wrote, iclass 12, count 0 2006.231.08:15:20.26#ibcon#about to read 3, iclass 12, count 0 2006.231.08:15:20.29#ibcon#read 3, iclass 12, count 0 2006.231.08:15:20.29#ibcon#about to read 4, iclass 12, count 0 2006.231.08:15:20.29#ibcon#read 4, iclass 12, count 0 2006.231.08:15:20.29#ibcon#about to read 5, iclass 12, count 0 2006.231.08:15:20.29#ibcon#read 5, iclass 12, count 0 2006.231.08:15:20.29#ibcon#about to read 6, iclass 12, count 0 2006.231.08:15:20.29#ibcon#read 6, iclass 12, count 0 2006.231.08:15:20.29#ibcon#end of sib2, iclass 12, count 0 2006.231.08:15:20.29#ibcon#*after write, iclass 12, count 0 2006.231.08:15:20.29#ibcon#*before return 0, iclass 12, count 0 2006.231.08:15:20.29#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:15:20.29#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:15:20.29#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:15:20.29#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:15:20.29$vc4f8/valo=8,852.99 2006.231.08:15:20.29#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.08:15:20.29#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.08:15:20.29#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:20.29#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:15:20.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:15:20.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:15:20.29#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:15:20.29#ibcon#first serial, iclass 14, count 0 2006.231.08:15:20.29#ibcon#enter sib2, iclass 14, count 0 2006.231.08:15:20.29#ibcon#flushed, iclass 14, count 0 2006.231.08:15:20.29#ibcon#about to write, iclass 14, count 0 2006.231.08:15:20.29#ibcon#wrote, iclass 14, count 0 2006.231.08:15:20.29#ibcon#about to read 3, iclass 14, count 0 2006.231.08:15:20.31#ibcon#read 3, iclass 14, count 0 2006.231.08:15:20.31#ibcon#about to read 4, iclass 14, count 0 2006.231.08:15:20.31#ibcon#read 4, iclass 14, count 0 2006.231.08:15:20.31#ibcon#about to read 5, iclass 14, count 0 2006.231.08:15:20.31#ibcon#read 5, iclass 14, count 0 2006.231.08:15:20.31#ibcon#about to read 6, iclass 14, count 0 2006.231.08:15:20.31#ibcon#read 6, iclass 14, count 0 2006.231.08:15:20.31#ibcon#end of sib2, iclass 14, count 0 2006.231.08:15:20.31#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:15:20.31#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:15:20.31#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:15:20.31#ibcon#*before write, iclass 14, count 0 2006.231.08:15:20.31#ibcon#enter sib2, iclass 14, count 0 2006.231.08:15:20.31#ibcon#flushed, iclass 14, count 0 2006.231.08:15:20.31#ibcon#about to write, iclass 14, count 0 2006.231.08:15:20.31#ibcon#wrote, iclass 14, count 0 2006.231.08:15:20.31#ibcon#about to read 3, iclass 14, count 0 2006.231.08:15:20.35#ibcon#read 3, iclass 14, count 0 2006.231.08:15:20.35#ibcon#about to read 4, iclass 14, count 0 2006.231.08:15:20.35#ibcon#read 4, iclass 14, count 0 2006.231.08:15:20.35#ibcon#about to read 5, iclass 14, count 0 2006.231.08:15:20.35#ibcon#read 5, iclass 14, count 0 2006.231.08:15:20.35#ibcon#about to read 6, iclass 14, count 0 2006.231.08:15:20.35#ibcon#read 6, iclass 14, count 0 2006.231.08:15:20.35#ibcon#end of sib2, iclass 14, count 0 2006.231.08:15:20.35#ibcon#*after write, iclass 14, count 0 2006.231.08:15:20.35#ibcon#*before return 0, iclass 14, count 0 2006.231.08:15:20.35#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:15:20.35#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:15:20.35#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:15:20.35#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:15:20.35$vc4f8/va=8,6 2006.231.08:15:20.35#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.08:15:20.35#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.08:15:20.35#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:20.35#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:15:20.41#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:15:20.41#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:15:20.41#ibcon#enter wrdev, iclass 16, count 2 2006.231.08:15:20.41#ibcon#first serial, iclass 16, count 2 2006.231.08:15:20.41#ibcon#enter sib2, iclass 16, count 2 2006.231.08:15:20.41#ibcon#flushed, iclass 16, count 2 2006.231.08:15:20.41#ibcon#about to write, iclass 16, count 2 2006.231.08:15:20.41#ibcon#wrote, iclass 16, count 2 2006.231.08:15:20.41#ibcon#about to read 3, iclass 16, count 2 2006.231.08:15:20.43#ibcon#read 3, iclass 16, count 2 2006.231.08:15:20.43#ibcon#about to read 4, iclass 16, count 2 2006.231.08:15:20.43#ibcon#read 4, iclass 16, count 2 2006.231.08:15:20.43#ibcon#about to read 5, iclass 16, count 2 2006.231.08:15:20.43#ibcon#read 5, iclass 16, count 2 2006.231.08:15:20.43#ibcon#about to read 6, iclass 16, count 2 2006.231.08:15:20.43#ibcon#read 6, iclass 16, count 2 2006.231.08:15:20.43#ibcon#end of sib2, iclass 16, count 2 2006.231.08:15:20.43#ibcon#*mode == 0, iclass 16, count 2 2006.231.08:15:20.43#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.08:15:20.43#ibcon#[25=AT08-06\r\n] 2006.231.08:15:20.43#ibcon#*before write, iclass 16, count 2 2006.231.08:15:20.43#ibcon#enter sib2, iclass 16, count 2 2006.231.08:15:20.43#ibcon#flushed, iclass 16, count 2 2006.231.08:15:20.43#ibcon#about to write, iclass 16, count 2 2006.231.08:15:20.43#ibcon#wrote, iclass 16, count 2 2006.231.08:15:20.43#ibcon#about to read 3, iclass 16, count 2 2006.231.08:15:20.46#ibcon#read 3, iclass 16, count 2 2006.231.08:15:20.46#ibcon#about to read 4, iclass 16, count 2 2006.231.08:15:20.46#ibcon#read 4, iclass 16, count 2 2006.231.08:15:20.46#ibcon#about to read 5, iclass 16, count 2 2006.231.08:15:20.46#ibcon#read 5, iclass 16, count 2 2006.231.08:15:20.46#ibcon#about to read 6, iclass 16, count 2 2006.231.08:15:20.46#ibcon#read 6, iclass 16, count 2 2006.231.08:15:20.46#ibcon#end of sib2, iclass 16, count 2 2006.231.08:15:20.46#ibcon#*after write, iclass 16, count 2 2006.231.08:15:20.46#ibcon#*before return 0, iclass 16, count 2 2006.231.08:15:20.46#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:15:20.46#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:15:20.46#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.08:15:20.46#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:20.46#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:15:20.58#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:15:20.58#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:15:20.58#ibcon#enter wrdev, iclass 16, count 0 2006.231.08:15:20.58#ibcon#first serial, iclass 16, count 0 2006.231.08:15:20.58#ibcon#enter sib2, iclass 16, count 0 2006.231.08:15:20.58#ibcon#flushed, iclass 16, count 0 2006.231.08:15:20.58#ibcon#about to write, iclass 16, count 0 2006.231.08:15:20.58#ibcon#wrote, iclass 16, count 0 2006.231.08:15:20.58#ibcon#about to read 3, iclass 16, count 0 2006.231.08:15:20.60#ibcon#read 3, iclass 16, count 0 2006.231.08:15:20.60#ibcon#about to read 4, iclass 16, count 0 2006.231.08:15:20.60#ibcon#read 4, iclass 16, count 0 2006.231.08:15:20.60#ibcon#about to read 5, iclass 16, count 0 2006.231.08:15:20.60#ibcon#read 5, iclass 16, count 0 2006.231.08:15:20.60#ibcon#about to read 6, iclass 16, count 0 2006.231.08:15:20.60#ibcon#read 6, iclass 16, count 0 2006.231.08:15:20.60#ibcon#end of sib2, iclass 16, count 0 2006.231.08:15:20.60#ibcon#*mode == 0, iclass 16, count 0 2006.231.08:15:20.60#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.08:15:20.60#ibcon#[25=USB\r\n] 2006.231.08:15:20.60#ibcon#*before write, iclass 16, count 0 2006.231.08:15:20.60#ibcon#enter sib2, iclass 16, count 0 2006.231.08:15:20.60#ibcon#flushed, iclass 16, count 0 2006.231.08:15:20.60#ibcon#about to write, iclass 16, count 0 2006.231.08:15:20.60#ibcon#wrote, iclass 16, count 0 2006.231.08:15:20.60#ibcon#about to read 3, iclass 16, count 0 2006.231.08:15:20.63#ibcon#read 3, iclass 16, count 0 2006.231.08:15:20.63#ibcon#about to read 4, iclass 16, count 0 2006.231.08:15:20.63#ibcon#read 4, iclass 16, count 0 2006.231.08:15:20.63#ibcon#about to read 5, iclass 16, count 0 2006.231.08:15:20.63#ibcon#read 5, iclass 16, count 0 2006.231.08:15:20.63#ibcon#about to read 6, iclass 16, count 0 2006.231.08:15:20.63#ibcon#read 6, iclass 16, count 0 2006.231.08:15:20.63#ibcon#end of sib2, iclass 16, count 0 2006.231.08:15:20.63#ibcon#*after write, iclass 16, count 0 2006.231.08:15:20.63#ibcon#*before return 0, iclass 16, count 0 2006.231.08:15:20.63#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:15:20.63#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:15:20.63#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.08:15:20.63#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.08:15:20.63$vc4f8/vblo=1,632.99 2006.231.08:15:20.63#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.08:15:20.63#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.08:15:20.63#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:20.63#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:15:20.63#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:15:20.63#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:15:20.63#ibcon#enter wrdev, iclass 18, count 0 2006.231.08:15:20.63#ibcon#first serial, iclass 18, count 0 2006.231.08:15:20.63#ibcon#enter sib2, iclass 18, count 0 2006.231.08:15:20.63#ibcon#flushed, iclass 18, count 0 2006.231.08:15:20.63#ibcon#about to write, iclass 18, count 0 2006.231.08:15:20.63#ibcon#wrote, iclass 18, count 0 2006.231.08:15:20.63#ibcon#about to read 3, iclass 18, count 0 2006.231.08:15:20.65#ibcon#read 3, iclass 18, count 0 2006.231.08:15:20.65#ibcon#about to read 4, iclass 18, count 0 2006.231.08:15:20.65#ibcon#read 4, iclass 18, count 0 2006.231.08:15:20.65#ibcon#about to read 5, iclass 18, count 0 2006.231.08:15:20.65#ibcon#read 5, iclass 18, count 0 2006.231.08:15:20.65#ibcon#about to read 6, iclass 18, count 0 2006.231.08:15:20.65#ibcon#read 6, iclass 18, count 0 2006.231.08:15:20.65#ibcon#end of sib2, iclass 18, count 0 2006.231.08:15:20.65#ibcon#*mode == 0, iclass 18, count 0 2006.231.08:15:20.65#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.08:15:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:15:20.65#ibcon#*before write, iclass 18, count 0 2006.231.08:15:20.65#ibcon#enter sib2, iclass 18, count 0 2006.231.08:15:20.65#ibcon#flushed, iclass 18, count 0 2006.231.08:15:20.65#ibcon#about to write, iclass 18, count 0 2006.231.08:15:20.65#ibcon#wrote, iclass 18, count 0 2006.231.08:15:20.65#ibcon#about to read 3, iclass 18, count 0 2006.231.08:15:20.69#ibcon#read 3, iclass 18, count 0 2006.231.08:15:20.69#ibcon#about to read 4, iclass 18, count 0 2006.231.08:15:20.69#ibcon#read 4, iclass 18, count 0 2006.231.08:15:20.69#ibcon#about to read 5, iclass 18, count 0 2006.231.08:15:20.69#ibcon#read 5, iclass 18, count 0 2006.231.08:15:20.69#ibcon#about to read 6, iclass 18, count 0 2006.231.08:15:20.69#ibcon#read 6, iclass 18, count 0 2006.231.08:15:20.69#ibcon#end of sib2, iclass 18, count 0 2006.231.08:15:20.69#ibcon#*after write, iclass 18, count 0 2006.231.08:15:20.69#ibcon#*before return 0, iclass 18, count 0 2006.231.08:15:20.69#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:15:20.69#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:15:20.69#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.08:15:20.69#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.08:15:20.69$vc4f8/vb=1,4 2006.231.08:15:20.69#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.08:15:20.69#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.08:15:20.69#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:20.69#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:15:20.69#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:15:20.69#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:15:20.69#ibcon#enter wrdev, iclass 20, count 2 2006.231.08:15:20.69#ibcon#first serial, iclass 20, count 2 2006.231.08:15:20.69#ibcon#enter sib2, iclass 20, count 2 2006.231.08:15:20.69#ibcon#flushed, iclass 20, count 2 2006.231.08:15:20.69#ibcon#about to write, iclass 20, count 2 2006.231.08:15:20.69#ibcon#wrote, iclass 20, count 2 2006.231.08:15:20.69#ibcon#about to read 3, iclass 20, count 2 2006.231.08:15:20.71#ibcon#read 3, iclass 20, count 2 2006.231.08:15:20.71#ibcon#about to read 4, iclass 20, count 2 2006.231.08:15:20.71#ibcon#read 4, iclass 20, count 2 2006.231.08:15:20.71#ibcon#about to read 5, iclass 20, count 2 2006.231.08:15:20.71#ibcon#read 5, iclass 20, count 2 2006.231.08:15:20.71#ibcon#about to read 6, iclass 20, count 2 2006.231.08:15:20.71#ibcon#read 6, iclass 20, count 2 2006.231.08:15:20.71#ibcon#end of sib2, iclass 20, count 2 2006.231.08:15:20.71#ibcon#*mode == 0, iclass 20, count 2 2006.231.08:15:20.71#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.08:15:20.71#ibcon#[27=AT01-04\r\n] 2006.231.08:15:20.71#ibcon#*before write, iclass 20, count 2 2006.231.08:15:20.71#ibcon#enter sib2, iclass 20, count 2 2006.231.08:15:20.71#ibcon#flushed, iclass 20, count 2 2006.231.08:15:20.71#ibcon#about to write, iclass 20, count 2 2006.231.08:15:20.71#ibcon#wrote, iclass 20, count 2 2006.231.08:15:20.71#ibcon#about to read 3, iclass 20, count 2 2006.231.08:15:20.74#ibcon#read 3, iclass 20, count 2 2006.231.08:15:20.74#ibcon#about to read 4, iclass 20, count 2 2006.231.08:15:20.74#ibcon#read 4, iclass 20, count 2 2006.231.08:15:20.74#ibcon#about to read 5, iclass 20, count 2 2006.231.08:15:20.74#ibcon#read 5, iclass 20, count 2 2006.231.08:15:20.74#ibcon#about to read 6, iclass 20, count 2 2006.231.08:15:20.74#ibcon#read 6, iclass 20, count 2 2006.231.08:15:20.74#ibcon#end of sib2, iclass 20, count 2 2006.231.08:15:20.74#ibcon#*after write, iclass 20, count 2 2006.231.08:15:20.74#ibcon#*before return 0, iclass 20, count 2 2006.231.08:15:20.74#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:15:20.74#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:15:20.74#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.08:15:20.74#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:20.74#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:15:20.86#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:15:20.86#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:15:20.86#ibcon#enter wrdev, iclass 20, count 0 2006.231.08:15:20.86#ibcon#first serial, iclass 20, count 0 2006.231.08:15:20.86#ibcon#enter sib2, iclass 20, count 0 2006.231.08:15:20.86#ibcon#flushed, iclass 20, count 0 2006.231.08:15:20.86#ibcon#about to write, iclass 20, count 0 2006.231.08:15:20.86#ibcon#wrote, iclass 20, count 0 2006.231.08:15:20.86#ibcon#about to read 3, iclass 20, count 0 2006.231.08:15:20.88#ibcon#read 3, iclass 20, count 0 2006.231.08:15:20.88#ibcon#about to read 4, iclass 20, count 0 2006.231.08:15:20.88#ibcon#read 4, iclass 20, count 0 2006.231.08:15:20.88#ibcon#about to read 5, iclass 20, count 0 2006.231.08:15:20.88#ibcon#read 5, iclass 20, count 0 2006.231.08:15:20.88#ibcon#about to read 6, iclass 20, count 0 2006.231.08:15:20.88#ibcon#read 6, iclass 20, count 0 2006.231.08:15:20.88#ibcon#end of sib2, iclass 20, count 0 2006.231.08:15:20.88#ibcon#*mode == 0, iclass 20, count 0 2006.231.08:15:20.88#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.08:15:20.88#ibcon#[27=USB\r\n] 2006.231.08:15:20.88#ibcon#*before write, iclass 20, count 0 2006.231.08:15:20.88#ibcon#enter sib2, iclass 20, count 0 2006.231.08:15:20.88#ibcon#flushed, iclass 20, count 0 2006.231.08:15:20.88#ibcon#about to write, iclass 20, count 0 2006.231.08:15:20.88#ibcon#wrote, iclass 20, count 0 2006.231.08:15:20.88#ibcon#about to read 3, iclass 20, count 0 2006.231.08:15:20.91#ibcon#read 3, iclass 20, count 0 2006.231.08:15:20.91#ibcon#about to read 4, iclass 20, count 0 2006.231.08:15:20.91#ibcon#read 4, iclass 20, count 0 2006.231.08:15:20.91#ibcon#about to read 5, iclass 20, count 0 2006.231.08:15:20.91#ibcon#read 5, iclass 20, count 0 2006.231.08:15:20.91#ibcon#about to read 6, iclass 20, count 0 2006.231.08:15:20.91#ibcon#read 6, iclass 20, count 0 2006.231.08:15:20.91#ibcon#end of sib2, iclass 20, count 0 2006.231.08:15:20.91#ibcon#*after write, iclass 20, count 0 2006.231.08:15:20.91#ibcon#*before return 0, iclass 20, count 0 2006.231.08:15:20.91#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:15:20.91#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:15:20.91#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.08:15:20.91#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.08:15:20.91$vc4f8/vblo=2,640.99 2006.231.08:15:20.91#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.08:15:20.91#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.08:15:20.91#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:20.91#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:15:20.91#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:15:20.91#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:15:20.91#ibcon#enter wrdev, iclass 22, count 0 2006.231.08:15:20.91#ibcon#first serial, iclass 22, count 0 2006.231.08:15:20.91#ibcon#enter sib2, iclass 22, count 0 2006.231.08:15:20.91#ibcon#flushed, iclass 22, count 0 2006.231.08:15:20.91#ibcon#about to write, iclass 22, count 0 2006.231.08:15:20.91#ibcon#wrote, iclass 22, count 0 2006.231.08:15:20.91#ibcon#about to read 3, iclass 22, count 0 2006.231.08:15:20.93#ibcon#read 3, iclass 22, count 0 2006.231.08:15:20.93#ibcon#about to read 4, iclass 22, count 0 2006.231.08:15:20.93#ibcon#read 4, iclass 22, count 0 2006.231.08:15:20.93#ibcon#about to read 5, iclass 22, count 0 2006.231.08:15:20.93#ibcon#read 5, iclass 22, count 0 2006.231.08:15:20.93#ibcon#about to read 6, iclass 22, count 0 2006.231.08:15:20.93#ibcon#read 6, iclass 22, count 0 2006.231.08:15:20.93#ibcon#end of sib2, iclass 22, count 0 2006.231.08:15:20.93#ibcon#*mode == 0, iclass 22, count 0 2006.231.08:15:20.93#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.08:15:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:15:20.93#ibcon#*before write, iclass 22, count 0 2006.231.08:15:20.93#ibcon#enter sib2, iclass 22, count 0 2006.231.08:15:20.93#ibcon#flushed, iclass 22, count 0 2006.231.08:15:20.93#ibcon#about to write, iclass 22, count 0 2006.231.08:15:20.93#ibcon#wrote, iclass 22, count 0 2006.231.08:15:20.93#ibcon#about to read 3, iclass 22, count 0 2006.231.08:15:20.97#ibcon#read 3, iclass 22, count 0 2006.231.08:15:20.97#ibcon#about to read 4, iclass 22, count 0 2006.231.08:15:20.97#ibcon#read 4, iclass 22, count 0 2006.231.08:15:20.97#ibcon#about to read 5, iclass 22, count 0 2006.231.08:15:20.97#ibcon#read 5, iclass 22, count 0 2006.231.08:15:20.97#ibcon#about to read 6, iclass 22, count 0 2006.231.08:15:20.97#ibcon#read 6, iclass 22, count 0 2006.231.08:15:20.97#ibcon#end of sib2, iclass 22, count 0 2006.231.08:15:20.97#ibcon#*after write, iclass 22, count 0 2006.231.08:15:20.97#ibcon#*before return 0, iclass 22, count 0 2006.231.08:15:20.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:15:20.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:15:20.97#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.08:15:20.97#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.08:15:20.97$vc4f8/vb=2,4 2006.231.08:15:20.97#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.08:15:20.97#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.08:15:20.97#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:20.97#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:15:21.03#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:15:21.03#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:15:21.03#ibcon#enter wrdev, iclass 24, count 2 2006.231.08:15:21.03#ibcon#first serial, iclass 24, count 2 2006.231.08:15:21.03#ibcon#enter sib2, iclass 24, count 2 2006.231.08:15:21.03#ibcon#flushed, iclass 24, count 2 2006.231.08:15:21.03#ibcon#about to write, iclass 24, count 2 2006.231.08:15:21.03#ibcon#wrote, iclass 24, count 2 2006.231.08:15:21.03#ibcon#about to read 3, iclass 24, count 2 2006.231.08:15:21.05#ibcon#read 3, iclass 24, count 2 2006.231.08:15:21.05#ibcon#about to read 4, iclass 24, count 2 2006.231.08:15:21.05#ibcon#read 4, iclass 24, count 2 2006.231.08:15:21.05#ibcon#about to read 5, iclass 24, count 2 2006.231.08:15:21.05#ibcon#read 5, iclass 24, count 2 2006.231.08:15:21.05#ibcon#about to read 6, iclass 24, count 2 2006.231.08:15:21.05#ibcon#read 6, iclass 24, count 2 2006.231.08:15:21.05#ibcon#end of sib2, iclass 24, count 2 2006.231.08:15:21.05#ibcon#*mode == 0, iclass 24, count 2 2006.231.08:15:21.05#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.08:15:21.05#ibcon#[27=AT02-04\r\n] 2006.231.08:15:21.05#ibcon#*before write, iclass 24, count 2 2006.231.08:15:21.05#ibcon#enter sib2, iclass 24, count 2 2006.231.08:15:21.05#ibcon#flushed, iclass 24, count 2 2006.231.08:15:21.05#ibcon#about to write, iclass 24, count 2 2006.231.08:15:21.05#ibcon#wrote, iclass 24, count 2 2006.231.08:15:21.05#ibcon#about to read 3, iclass 24, count 2 2006.231.08:15:21.08#ibcon#read 3, iclass 24, count 2 2006.231.08:15:21.08#ibcon#about to read 4, iclass 24, count 2 2006.231.08:15:21.08#ibcon#read 4, iclass 24, count 2 2006.231.08:15:21.08#ibcon#about to read 5, iclass 24, count 2 2006.231.08:15:21.08#ibcon#read 5, iclass 24, count 2 2006.231.08:15:21.08#ibcon#about to read 6, iclass 24, count 2 2006.231.08:15:21.08#ibcon#read 6, iclass 24, count 2 2006.231.08:15:21.08#ibcon#end of sib2, iclass 24, count 2 2006.231.08:15:21.08#ibcon#*after write, iclass 24, count 2 2006.231.08:15:21.08#ibcon#*before return 0, iclass 24, count 2 2006.231.08:15:21.08#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:15:21.08#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:15:21.08#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.08:15:21.08#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:21.08#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:15:21.20#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:15:21.20#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:15:21.20#ibcon#enter wrdev, iclass 24, count 0 2006.231.08:15:21.20#ibcon#first serial, iclass 24, count 0 2006.231.08:15:21.20#ibcon#enter sib2, iclass 24, count 0 2006.231.08:15:21.20#ibcon#flushed, iclass 24, count 0 2006.231.08:15:21.20#ibcon#about to write, iclass 24, count 0 2006.231.08:15:21.20#ibcon#wrote, iclass 24, count 0 2006.231.08:15:21.20#ibcon#about to read 3, iclass 24, count 0 2006.231.08:15:21.22#ibcon#read 3, iclass 24, count 0 2006.231.08:15:21.22#ibcon#about to read 4, iclass 24, count 0 2006.231.08:15:21.22#ibcon#read 4, iclass 24, count 0 2006.231.08:15:21.22#ibcon#about to read 5, iclass 24, count 0 2006.231.08:15:21.22#ibcon#read 5, iclass 24, count 0 2006.231.08:15:21.22#ibcon#about to read 6, iclass 24, count 0 2006.231.08:15:21.22#ibcon#read 6, iclass 24, count 0 2006.231.08:15:21.22#ibcon#end of sib2, iclass 24, count 0 2006.231.08:15:21.22#ibcon#*mode == 0, iclass 24, count 0 2006.231.08:15:21.22#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.08:15:21.22#ibcon#[27=USB\r\n] 2006.231.08:15:21.22#ibcon#*before write, iclass 24, count 0 2006.231.08:15:21.22#ibcon#enter sib2, iclass 24, count 0 2006.231.08:15:21.22#ibcon#flushed, iclass 24, count 0 2006.231.08:15:21.22#ibcon#about to write, iclass 24, count 0 2006.231.08:15:21.22#ibcon#wrote, iclass 24, count 0 2006.231.08:15:21.22#ibcon#about to read 3, iclass 24, count 0 2006.231.08:15:21.25#ibcon#read 3, iclass 24, count 0 2006.231.08:15:21.25#ibcon#about to read 4, iclass 24, count 0 2006.231.08:15:21.25#ibcon#read 4, iclass 24, count 0 2006.231.08:15:21.25#ibcon#about to read 5, iclass 24, count 0 2006.231.08:15:21.25#ibcon#read 5, iclass 24, count 0 2006.231.08:15:21.25#ibcon#about to read 6, iclass 24, count 0 2006.231.08:15:21.25#ibcon#read 6, iclass 24, count 0 2006.231.08:15:21.25#ibcon#end of sib2, iclass 24, count 0 2006.231.08:15:21.25#ibcon#*after write, iclass 24, count 0 2006.231.08:15:21.25#ibcon#*before return 0, iclass 24, count 0 2006.231.08:15:21.25#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:15:21.25#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:15:21.25#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.08:15:21.25#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.08:15:21.25$vc4f8/vblo=3,656.99 2006.231.08:15:21.25#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.08:15:21.25#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.08:15:21.25#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:21.25#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:15:21.25#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:15:21.25#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:15:21.25#ibcon#enter wrdev, iclass 26, count 0 2006.231.08:15:21.25#ibcon#first serial, iclass 26, count 0 2006.231.08:15:21.25#ibcon#enter sib2, iclass 26, count 0 2006.231.08:15:21.25#ibcon#flushed, iclass 26, count 0 2006.231.08:15:21.25#ibcon#about to write, iclass 26, count 0 2006.231.08:15:21.25#ibcon#wrote, iclass 26, count 0 2006.231.08:15:21.25#ibcon#about to read 3, iclass 26, count 0 2006.231.08:15:21.27#ibcon#read 3, iclass 26, count 0 2006.231.08:15:21.27#ibcon#about to read 4, iclass 26, count 0 2006.231.08:15:21.27#ibcon#read 4, iclass 26, count 0 2006.231.08:15:21.27#ibcon#about to read 5, iclass 26, count 0 2006.231.08:15:21.27#ibcon#read 5, iclass 26, count 0 2006.231.08:15:21.27#ibcon#about to read 6, iclass 26, count 0 2006.231.08:15:21.27#ibcon#read 6, iclass 26, count 0 2006.231.08:15:21.27#ibcon#end of sib2, iclass 26, count 0 2006.231.08:15:21.27#ibcon#*mode == 0, iclass 26, count 0 2006.231.08:15:21.27#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.08:15:21.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:15:21.27#ibcon#*before write, iclass 26, count 0 2006.231.08:15:21.27#ibcon#enter sib2, iclass 26, count 0 2006.231.08:15:21.27#ibcon#flushed, iclass 26, count 0 2006.231.08:15:21.27#ibcon#about to write, iclass 26, count 0 2006.231.08:15:21.27#ibcon#wrote, iclass 26, count 0 2006.231.08:15:21.27#ibcon#about to read 3, iclass 26, count 0 2006.231.08:15:21.31#ibcon#read 3, iclass 26, count 0 2006.231.08:15:21.31#ibcon#about to read 4, iclass 26, count 0 2006.231.08:15:21.31#ibcon#read 4, iclass 26, count 0 2006.231.08:15:21.31#ibcon#about to read 5, iclass 26, count 0 2006.231.08:15:21.31#ibcon#read 5, iclass 26, count 0 2006.231.08:15:21.31#ibcon#about to read 6, iclass 26, count 0 2006.231.08:15:21.31#ibcon#read 6, iclass 26, count 0 2006.231.08:15:21.31#ibcon#end of sib2, iclass 26, count 0 2006.231.08:15:21.31#ibcon#*after write, iclass 26, count 0 2006.231.08:15:21.31#ibcon#*before return 0, iclass 26, count 0 2006.231.08:15:21.31#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:15:21.31#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:15:21.31#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.08:15:21.31#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.08:15:21.31$vc4f8/vb=3,4 2006.231.08:15:21.31#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.08:15:21.31#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.08:15:21.31#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:21.31#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:15:21.37#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:15:21.37#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:15:21.37#ibcon#enter wrdev, iclass 28, count 2 2006.231.08:15:21.37#ibcon#first serial, iclass 28, count 2 2006.231.08:15:21.37#ibcon#enter sib2, iclass 28, count 2 2006.231.08:15:21.37#ibcon#flushed, iclass 28, count 2 2006.231.08:15:21.37#ibcon#about to write, iclass 28, count 2 2006.231.08:15:21.37#ibcon#wrote, iclass 28, count 2 2006.231.08:15:21.37#ibcon#about to read 3, iclass 28, count 2 2006.231.08:15:21.39#ibcon#read 3, iclass 28, count 2 2006.231.08:15:21.39#ibcon#about to read 4, iclass 28, count 2 2006.231.08:15:21.39#ibcon#read 4, iclass 28, count 2 2006.231.08:15:21.39#ibcon#about to read 5, iclass 28, count 2 2006.231.08:15:21.39#ibcon#read 5, iclass 28, count 2 2006.231.08:15:21.39#ibcon#about to read 6, iclass 28, count 2 2006.231.08:15:21.39#ibcon#read 6, iclass 28, count 2 2006.231.08:15:21.39#ibcon#end of sib2, iclass 28, count 2 2006.231.08:15:21.39#ibcon#*mode == 0, iclass 28, count 2 2006.231.08:15:21.39#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.08:15:21.39#ibcon#[27=AT03-04\r\n] 2006.231.08:15:21.39#ibcon#*before write, iclass 28, count 2 2006.231.08:15:21.39#ibcon#enter sib2, iclass 28, count 2 2006.231.08:15:21.39#ibcon#flushed, iclass 28, count 2 2006.231.08:15:21.39#ibcon#about to write, iclass 28, count 2 2006.231.08:15:21.39#ibcon#wrote, iclass 28, count 2 2006.231.08:15:21.39#ibcon#about to read 3, iclass 28, count 2 2006.231.08:15:21.42#ibcon#read 3, iclass 28, count 2 2006.231.08:15:21.42#ibcon#about to read 4, iclass 28, count 2 2006.231.08:15:21.42#ibcon#read 4, iclass 28, count 2 2006.231.08:15:21.42#ibcon#about to read 5, iclass 28, count 2 2006.231.08:15:21.42#ibcon#read 5, iclass 28, count 2 2006.231.08:15:21.42#ibcon#about to read 6, iclass 28, count 2 2006.231.08:15:21.42#ibcon#read 6, iclass 28, count 2 2006.231.08:15:21.42#ibcon#end of sib2, iclass 28, count 2 2006.231.08:15:21.42#ibcon#*after write, iclass 28, count 2 2006.231.08:15:21.42#ibcon#*before return 0, iclass 28, count 2 2006.231.08:15:21.42#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:15:21.42#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:15:21.42#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.08:15:21.42#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:21.42#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:15:21.54#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:15:21.54#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:15:21.54#ibcon#enter wrdev, iclass 28, count 0 2006.231.08:15:21.54#ibcon#first serial, iclass 28, count 0 2006.231.08:15:21.54#ibcon#enter sib2, iclass 28, count 0 2006.231.08:15:21.54#ibcon#flushed, iclass 28, count 0 2006.231.08:15:21.54#ibcon#about to write, iclass 28, count 0 2006.231.08:15:21.54#ibcon#wrote, iclass 28, count 0 2006.231.08:15:21.54#ibcon#about to read 3, iclass 28, count 0 2006.231.08:15:21.56#ibcon#read 3, iclass 28, count 0 2006.231.08:15:21.56#ibcon#about to read 4, iclass 28, count 0 2006.231.08:15:21.56#ibcon#read 4, iclass 28, count 0 2006.231.08:15:21.56#ibcon#about to read 5, iclass 28, count 0 2006.231.08:15:21.56#ibcon#read 5, iclass 28, count 0 2006.231.08:15:21.56#ibcon#about to read 6, iclass 28, count 0 2006.231.08:15:21.56#ibcon#read 6, iclass 28, count 0 2006.231.08:15:21.56#ibcon#end of sib2, iclass 28, count 0 2006.231.08:15:21.56#ibcon#*mode == 0, iclass 28, count 0 2006.231.08:15:21.56#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.08:15:21.56#ibcon#[27=USB\r\n] 2006.231.08:15:21.56#ibcon#*before write, iclass 28, count 0 2006.231.08:15:21.56#ibcon#enter sib2, iclass 28, count 0 2006.231.08:15:21.56#ibcon#flushed, iclass 28, count 0 2006.231.08:15:21.56#ibcon#about to write, iclass 28, count 0 2006.231.08:15:21.56#ibcon#wrote, iclass 28, count 0 2006.231.08:15:21.56#ibcon#about to read 3, iclass 28, count 0 2006.231.08:15:21.59#ibcon#read 3, iclass 28, count 0 2006.231.08:15:21.59#ibcon#about to read 4, iclass 28, count 0 2006.231.08:15:21.59#ibcon#read 4, iclass 28, count 0 2006.231.08:15:21.59#ibcon#about to read 5, iclass 28, count 0 2006.231.08:15:21.59#ibcon#read 5, iclass 28, count 0 2006.231.08:15:21.59#ibcon#about to read 6, iclass 28, count 0 2006.231.08:15:21.59#ibcon#read 6, iclass 28, count 0 2006.231.08:15:21.59#ibcon#end of sib2, iclass 28, count 0 2006.231.08:15:21.59#ibcon#*after write, iclass 28, count 0 2006.231.08:15:21.59#ibcon#*before return 0, iclass 28, count 0 2006.231.08:15:21.59#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:15:21.59#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:15:21.59#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.08:15:21.59#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.08:15:21.59$vc4f8/vblo=4,712.99 2006.231.08:15:21.59#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.08:15:21.59#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.08:15:21.59#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:21.59#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:15:21.59#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:15:21.59#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:15:21.59#ibcon#enter wrdev, iclass 30, count 0 2006.231.08:15:21.59#ibcon#first serial, iclass 30, count 0 2006.231.08:15:21.59#ibcon#enter sib2, iclass 30, count 0 2006.231.08:15:21.59#ibcon#flushed, iclass 30, count 0 2006.231.08:15:21.59#ibcon#about to write, iclass 30, count 0 2006.231.08:15:21.59#ibcon#wrote, iclass 30, count 0 2006.231.08:15:21.59#ibcon#about to read 3, iclass 30, count 0 2006.231.08:15:21.61#ibcon#read 3, iclass 30, count 0 2006.231.08:15:21.61#ibcon#about to read 4, iclass 30, count 0 2006.231.08:15:21.61#ibcon#read 4, iclass 30, count 0 2006.231.08:15:21.61#ibcon#about to read 5, iclass 30, count 0 2006.231.08:15:21.61#ibcon#read 5, iclass 30, count 0 2006.231.08:15:21.61#ibcon#about to read 6, iclass 30, count 0 2006.231.08:15:21.61#ibcon#read 6, iclass 30, count 0 2006.231.08:15:21.61#ibcon#end of sib2, iclass 30, count 0 2006.231.08:15:21.61#ibcon#*mode == 0, iclass 30, count 0 2006.231.08:15:21.61#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.08:15:21.61#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:15:21.61#ibcon#*before write, iclass 30, count 0 2006.231.08:15:21.61#ibcon#enter sib2, iclass 30, count 0 2006.231.08:15:21.61#ibcon#flushed, iclass 30, count 0 2006.231.08:15:21.61#ibcon#about to write, iclass 30, count 0 2006.231.08:15:21.61#ibcon#wrote, iclass 30, count 0 2006.231.08:15:21.61#ibcon#about to read 3, iclass 30, count 0 2006.231.08:15:21.65#ibcon#read 3, iclass 30, count 0 2006.231.08:15:21.65#ibcon#about to read 4, iclass 30, count 0 2006.231.08:15:21.65#ibcon#read 4, iclass 30, count 0 2006.231.08:15:21.65#ibcon#about to read 5, iclass 30, count 0 2006.231.08:15:21.65#ibcon#read 5, iclass 30, count 0 2006.231.08:15:21.65#ibcon#about to read 6, iclass 30, count 0 2006.231.08:15:21.65#ibcon#read 6, iclass 30, count 0 2006.231.08:15:21.65#ibcon#end of sib2, iclass 30, count 0 2006.231.08:15:21.65#ibcon#*after write, iclass 30, count 0 2006.231.08:15:21.65#ibcon#*before return 0, iclass 30, count 0 2006.231.08:15:21.65#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:15:21.65#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:15:21.65#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.08:15:21.65#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.08:15:21.65$vc4f8/vb=4,4 2006.231.08:15:21.65#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.08:15:21.65#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.08:15:21.65#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:21.65#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:15:21.71#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:15:21.71#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:15:21.71#ibcon#enter wrdev, iclass 32, count 2 2006.231.08:15:21.71#ibcon#first serial, iclass 32, count 2 2006.231.08:15:21.71#ibcon#enter sib2, iclass 32, count 2 2006.231.08:15:21.71#ibcon#flushed, iclass 32, count 2 2006.231.08:15:21.71#ibcon#about to write, iclass 32, count 2 2006.231.08:15:21.71#ibcon#wrote, iclass 32, count 2 2006.231.08:15:21.71#ibcon#about to read 3, iclass 32, count 2 2006.231.08:15:21.73#ibcon#read 3, iclass 32, count 2 2006.231.08:15:21.73#ibcon#about to read 4, iclass 32, count 2 2006.231.08:15:21.73#ibcon#read 4, iclass 32, count 2 2006.231.08:15:21.73#ibcon#about to read 5, iclass 32, count 2 2006.231.08:15:21.73#ibcon#read 5, iclass 32, count 2 2006.231.08:15:21.73#ibcon#about to read 6, iclass 32, count 2 2006.231.08:15:21.73#ibcon#read 6, iclass 32, count 2 2006.231.08:15:21.73#ibcon#end of sib2, iclass 32, count 2 2006.231.08:15:21.73#ibcon#*mode == 0, iclass 32, count 2 2006.231.08:15:21.73#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.08:15:21.73#ibcon#[27=AT04-04\r\n] 2006.231.08:15:21.73#ibcon#*before write, iclass 32, count 2 2006.231.08:15:21.73#ibcon#enter sib2, iclass 32, count 2 2006.231.08:15:21.73#ibcon#flushed, iclass 32, count 2 2006.231.08:15:21.73#ibcon#about to write, iclass 32, count 2 2006.231.08:15:21.73#ibcon#wrote, iclass 32, count 2 2006.231.08:15:21.73#ibcon#about to read 3, iclass 32, count 2 2006.231.08:15:21.76#ibcon#read 3, iclass 32, count 2 2006.231.08:15:21.76#ibcon#about to read 4, iclass 32, count 2 2006.231.08:15:21.76#ibcon#read 4, iclass 32, count 2 2006.231.08:15:21.76#ibcon#about to read 5, iclass 32, count 2 2006.231.08:15:21.76#ibcon#read 5, iclass 32, count 2 2006.231.08:15:21.76#ibcon#about to read 6, iclass 32, count 2 2006.231.08:15:21.76#ibcon#read 6, iclass 32, count 2 2006.231.08:15:21.76#ibcon#end of sib2, iclass 32, count 2 2006.231.08:15:21.76#ibcon#*after write, iclass 32, count 2 2006.231.08:15:21.76#ibcon#*before return 0, iclass 32, count 2 2006.231.08:15:21.76#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:15:21.76#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:15:21.76#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.08:15:21.76#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:21.76#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:15:21.88#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:15:21.88#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:15:21.88#ibcon#enter wrdev, iclass 32, count 0 2006.231.08:15:21.88#ibcon#first serial, iclass 32, count 0 2006.231.08:15:21.88#ibcon#enter sib2, iclass 32, count 0 2006.231.08:15:21.88#ibcon#flushed, iclass 32, count 0 2006.231.08:15:21.88#ibcon#about to write, iclass 32, count 0 2006.231.08:15:21.88#ibcon#wrote, iclass 32, count 0 2006.231.08:15:21.88#ibcon#about to read 3, iclass 32, count 0 2006.231.08:15:21.90#ibcon#read 3, iclass 32, count 0 2006.231.08:15:21.90#ibcon#about to read 4, iclass 32, count 0 2006.231.08:15:21.90#ibcon#read 4, iclass 32, count 0 2006.231.08:15:21.90#ibcon#about to read 5, iclass 32, count 0 2006.231.08:15:21.90#ibcon#read 5, iclass 32, count 0 2006.231.08:15:21.90#ibcon#about to read 6, iclass 32, count 0 2006.231.08:15:21.90#ibcon#read 6, iclass 32, count 0 2006.231.08:15:21.90#ibcon#end of sib2, iclass 32, count 0 2006.231.08:15:21.90#ibcon#*mode == 0, iclass 32, count 0 2006.231.08:15:21.90#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.08:15:21.90#ibcon#[27=USB\r\n] 2006.231.08:15:21.90#ibcon#*before write, iclass 32, count 0 2006.231.08:15:21.90#ibcon#enter sib2, iclass 32, count 0 2006.231.08:15:21.90#ibcon#flushed, iclass 32, count 0 2006.231.08:15:21.90#ibcon#about to write, iclass 32, count 0 2006.231.08:15:21.90#ibcon#wrote, iclass 32, count 0 2006.231.08:15:21.90#ibcon#about to read 3, iclass 32, count 0 2006.231.08:15:21.93#ibcon#read 3, iclass 32, count 0 2006.231.08:15:21.93#ibcon#about to read 4, iclass 32, count 0 2006.231.08:15:21.93#ibcon#read 4, iclass 32, count 0 2006.231.08:15:21.93#ibcon#about to read 5, iclass 32, count 0 2006.231.08:15:21.93#ibcon#read 5, iclass 32, count 0 2006.231.08:15:21.93#ibcon#about to read 6, iclass 32, count 0 2006.231.08:15:21.93#ibcon#read 6, iclass 32, count 0 2006.231.08:15:21.93#ibcon#end of sib2, iclass 32, count 0 2006.231.08:15:21.93#ibcon#*after write, iclass 32, count 0 2006.231.08:15:21.93#ibcon#*before return 0, iclass 32, count 0 2006.231.08:15:21.93#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:15:21.93#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:15:21.93#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.08:15:21.93#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.08:15:21.93$vc4f8/vblo=5,744.99 2006.231.08:15:21.93#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.08:15:21.93#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.08:15:21.93#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:21.93#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:15:21.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:15:21.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:15:21.93#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:15:21.93#ibcon#first serial, iclass 34, count 0 2006.231.08:15:21.93#ibcon#enter sib2, iclass 34, count 0 2006.231.08:15:21.93#ibcon#flushed, iclass 34, count 0 2006.231.08:15:21.93#ibcon#about to write, iclass 34, count 0 2006.231.08:15:21.93#ibcon#wrote, iclass 34, count 0 2006.231.08:15:21.93#ibcon#about to read 3, iclass 34, count 0 2006.231.08:15:21.95#ibcon#read 3, iclass 34, count 0 2006.231.08:15:21.95#ibcon#about to read 4, iclass 34, count 0 2006.231.08:15:21.95#ibcon#read 4, iclass 34, count 0 2006.231.08:15:21.95#ibcon#about to read 5, iclass 34, count 0 2006.231.08:15:21.95#ibcon#read 5, iclass 34, count 0 2006.231.08:15:21.95#ibcon#about to read 6, iclass 34, count 0 2006.231.08:15:21.95#ibcon#read 6, iclass 34, count 0 2006.231.08:15:21.95#ibcon#end of sib2, iclass 34, count 0 2006.231.08:15:21.95#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:15:21.95#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:15:21.95#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:15:21.95#ibcon#*before write, iclass 34, count 0 2006.231.08:15:21.95#ibcon#enter sib2, iclass 34, count 0 2006.231.08:15:21.95#ibcon#flushed, iclass 34, count 0 2006.231.08:15:21.95#ibcon#about to write, iclass 34, count 0 2006.231.08:15:21.95#ibcon#wrote, iclass 34, count 0 2006.231.08:15:21.95#ibcon#about to read 3, iclass 34, count 0 2006.231.08:15:21.99#ibcon#read 3, iclass 34, count 0 2006.231.08:15:21.99#ibcon#about to read 4, iclass 34, count 0 2006.231.08:15:21.99#ibcon#read 4, iclass 34, count 0 2006.231.08:15:21.99#ibcon#about to read 5, iclass 34, count 0 2006.231.08:15:21.99#ibcon#read 5, iclass 34, count 0 2006.231.08:15:21.99#ibcon#about to read 6, iclass 34, count 0 2006.231.08:15:21.99#ibcon#read 6, iclass 34, count 0 2006.231.08:15:21.99#ibcon#end of sib2, iclass 34, count 0 2006.231.08:15:21.99#ibcon#*after write, iclass 34, count 0 2006.231.08:15:21.99#ibcon#*before return 0, iclass 34, count 0 2006.231.08:15:21.99#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:15:21.99#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:15:21.99#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:15:21.99#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:15:21.99$vc4f8/vb=5,3 2006.231.08:15:21.99#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.08:15:21.99#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.08:15:21.99#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:21.99#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:15:22.05#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:15:22.05#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:15:22.05#ibcon#enter wrdev, iclass 36, count 2 2006.231.08:15:22.05#ibcon#first serial, iclass 36, count 2 2006.231.08:15:22.05#ibcon#enter sib2, iclass 36, count 2 2006.231.08:15:22.05#ibcon#flushed, iclass 36, count 2 2006.231.08:15:22.05#ibcon#about to write, iclass 36, count 2 2006.231.08:15:22.05#ibcon#wrote, iclass 36, count 2 2006.231.08:15:22.05#ibcon#about to read 3, iclass 36, count 2 2006.231.08:15:22.07#ibcon#read 3, iclass 36, count 2 2006.231.08:15:22.07#ibcon#about to read 4, iclass 36, count 2 2006.231.08:15:22.07#ibcon#read 4, iclass 36, count 2 2006.231.08:15:22.07#ibcon#about to read 5, iclass 36, count 2 2006.231.08:15:22.07#ibcon#read 5, iclass 36, count 2 2006.231.08:15:22.07#ibcon#about to read 6, iclass 36, count 2 2006.231.08:15:22.07#ibcon#read 6, iclass 36, count 2 2006.231.08:15:22.07#ibcon#end of sib2, iclass 36, count 2 2006.231.08:15:22.07#ibcon#*mode == 0, iclass 36, count 2 2006.231.08:15:22.07#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.08:15:22.07#ibcon#[27=AT05-03\r\n] 2006.231.08:15:22.07#ibcon#*before write, iclass 36, count 2 2006.231.08:15:22.07#ibcon#enter sib2, iclass 36, count 2 2006.231.08:15:22.07#ibcon#flushed, iclass 36, count 2 2006.231.08:15:22.07#ibcon#about to write, iclass 36, count 2 2006.231.08:15:22.07#ibcon#wrote, iclass 36, count 2 2006.231.08:15:22.07#ibcon#about to read 3, iclass 36, count 2 2006.231.08:15:22.10#ibcon#read 3, iclass 36, count 2 2006.231.08:15:22.10#ibcon#about to read 4, iclass 36, count 2 2006.231.08:15:22.10#ibcon#read 4, iclass 36, count 2 2006.231.08:15:22.10#ibcon#about to read 5, iclass 36, count 2 2006.231.08:15:22.10#ibcon#read 5, iclass 36, count 2 2006.231.08:15:22.10#ibcon#about to read 6, iclass 36, count 2 2006.231.08:15:22.10#ibcon#read 6, iclass 36, count 2 2006.231.08:15:22.10#ibcon#end of sib2, iclass 36, count 2 2006.231.08:15:22.10#ibcon#*after write, iclass 36, count 2 2006.231.08:15:22.10#ibcon#*before return 0, iclass 36, count 2 2006.231.08:15:22.10#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:15:22.10#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:15:22.10#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.08:15:22.10#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:22.10#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:15:22.22#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:15:22.22#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:15:22.22#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:15:22.22#ibcon#first serial, iclass 36, count 0 2006.231.08:15:22.22#ibcon#enter sib2, iclass 36, count 0 2006.231.08:15:22.22#ibcon#flushed, iclass 36, count 0 2006.231.08:15:22.22#ibcon#about to write, iclass 36, count 0 2006.231.08:15:22.22#ibcon#wrote, iclass 36, count 0 2006.231.08:15:22.22#ibcon#about to read 3, iclass 36, count 0 2006.231.08:15:22.24#ibcon#read 3, iclass 36, count 0 2006.231.08:15:22.24#ibcon#about to read 4, iclass 36, count 0 2006.231.08:15:22.24#ibcon#read 4, iclass 36, count 0 2006.231.08:15:22.24#ibcon#about to read 5, iclass 36, count 0 2006.231.08:15:22.24#ibcon#read 5, iclass 36, count 0 2006.231.08:15:22.24#ibcon#about to read 6, iclass 36, count 0 2006.231.08:15:22.24#ibcon#read 6, iclass 36, count 0 2006.231.08:15:22.24#ibcon#end of sib2, iclass 36, count 0 2006.231.08:15:22.24#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:15:22.24#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:15:22.24#ibcon#[27=USB\r\n] 2006.231.08:15:22.24#ibcon#*before write, iclass 36, count 0 2006.231.08:15:22.24#ibcon#enter sib2, iclass 36, count 0 2006.231.08:15:22.24#ibcon#flushed, iclass 36, count 0 2006.231.08:15:22.24#ibcon#about to write, iclass 36, count 0 2006.231.08:15:22.24#ibcon#wrote, iclass 36, count 0 2006.231.08:15:22.24#ibcon#about to read 3, iclass 36, count 0 2006.231.08:15:22.27#ibcon#read 3, iclass 36, count 0 2006.231.08:15:22.27#ibcon#about to read 4, iclass 36, count 0 2006.231.08:15:22.27#ibcon#read 4, iclass 36, count 0 2006.231.08:15:22.27#ibcon#about to read 5, iclass 36, count 0 2006.231.08:15:22.27#ibcon#read 5, iclass 36, count 0 2006.231.08:15:22.27#ibcon#about to read 6, iclass 36, count 0 2006.231.08:15:22.27#ibcon#read 6, iclass 36, count 0 2006.231.08:15:22.27#ibcon#end of sib2, iclass 36, count 0 2006.231.08:15:22.27#ibcon#*after write, iclass 36, count 0 2006.231.08:15:22.27#ibcon#*before return 0, iclass 36, count 0 2006.231.08:15:22.27#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:15:22.27#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:15:22.27#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:15:22.27#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:15:22.27$vc4f8/vblo=6,752.99 2006.231.08:15:22.27#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.08:15:22.27#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.08:15:22.27#ibcon#ireg 17 cls_cnt 0 2006.231.08:15:22.27#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:15:22.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:15:22.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:15:22.27#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:15:22.27#ibcon#first serial, iclass 38, count 0 2006.231.08:15:22.27#ibcon#enter sib2, iclass 38, count 0 2006.231.08:15:22.27#ibcon#flushed, iclass 38, count 0 2006.231.08:15:22.27#ibcon#about to write, iclass 38, count 0 2006.231.08:15:22.27#ibcon#wrote, iclass 38, count 0 2006.231.08:15:22.27#ibcon#about to read 3, iclass 38, count 0 2006.231.08:15:22.29#ibcon#read 3, iclass 38, count 0 2006.231.08:15:22.29#ibcon#about to read 4, iclass 38, count 0 2006.231.08:15:22.29#ibcon#read 4, iclass 38, count 0 2006.231.08:15:22.29#ibcon#about to read 5, iclass 38, count 0 2006.231.08:15:22.29#ibcon#read 5, iclass 38, count 0 2006.231.08:15:22.29#ibcon#about to read 6, iclass 38, count 0 2006.231.08:15:22.29#ibcon#read 6, iclass 38, count 0 2006.231.08:15:22.29#ibcon#end of sib2, iclass 38, count 0 2006.231.08:15:22.29#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:15:22.29#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:15:22.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:15:22.29#ibcon#*before write, iclass 38, count 0 2006.231.08:15:22.29#ibcon#enter sib2, iclass 38, count 0 2006.231.08:15:22.29#ibcon#flushed, iclass 38, count 0 2006.231.08:15:22.29#ibcon#about to write, iclass 38, count 0 2006.231.08:15:22.29#ibcon#wrote, iclass 38, count 0 2006.231.08:15:22.29#ibcon#about to read 3, iclass 38, count 0 2006.231.08:15:22.33#ibcon#read 3, iclass 38, count 0 2006.231.08:15:22.33#ibcon#about to read 4, iclass 38, count 0 2006.231.08:15:22.33#ibcon#read 4, iclass 38, count 0 2006.231.08:15:22.33#ibcon#about to read 5, iclass 38, count 0 2006.231.08:15:22.33#ibcon#read 5, iclass 38, count 0 2006.231.08:15:22.33#ibcon#about to read 6, iclass 38, count 0 2006.231.08:15:22.33#ibcon#read 6, iclass 38, count 0 2006.231.08:15:22.33#ibcon#end of sib2, iclass 38, count 0 2006.231.08:15:22.33#ibcon#*after write, iclass 38, count 0 2006.231.08:15:22.33#ibcon#*before return 0, iclass 38, count 0 2006.231.08:15:22.33#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:15:22.33#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:15:22.33#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:15:22.33#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:15:22.33$vc4f8/vb=6,4 2006.231.08:15:22.33#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.08:15:22.33#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.08:15:22.33#ibcon#ireg 11 cls_cnt 2 2006.231.08:15:22.33#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:15:22.39#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:15:22.39#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:15:22.39#ibcon#enter wrdev, iclass 40, count 2 2006.231.08:15:22.39#ibcon#first serial, iclass 40, count 2 2006.231.08:15:22.39#ibcon#enter sib2, iclass 40, count 2 2006.231.08:15:22.39#ibcon#flushed, iclass 40, count 2 2006.231.08:15:22.39#ibcon#about to write, iclass 40, count 2 2006.231.08:15:22.39#ibcon#wrote, iclass 40, count 2 2006.231.08:15:22.39#ibcon#about to read 3, iclass 40, count 2 2006.231.08:15:22.41#ibcon#read 3, iclass 40, count 2 2006.231.08:15:22.41#ibcon#about to read 4, iclass 40, count 2 2006.231.08:15:22.41#ibcon#read 4, iclass 40, count 2 2006.231.08:15:22.41#ibcon#about to read 5, iclass 40, count 2 2006.231.08:15:22.41#ibcon#read 5, iclass 40, count 2 2006.231.08:15:22.41#ibcon#about to read 6, iclass 40, count 2 2006.231.08:15:22.41#ibcon#read 6, iclass 40, count 2 2006.231.08:15:22.41#ibcon#end of sib2, iclass 40, count 2 2006.231.08:15:22.41#ibcon#*mode == 0, iclass 40, count 2 2006.231.08:15:22.41#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.08:15:22.41#ibcon#[27=AT06-04\r\n] 2006.231.08:15:22.41#ibcon#*before write, iclass 40, count 2 2006.231.08:15:22.41#ibcon#enter sib2, iclass 40, count 2 2006.231.08:15:22.41#ibcon#flushed, iclass 40, count 2 2006.231.08:15:22.41#ibcon#about to write, iclass 40, count 2 2006.231.08:15:22.41#ibcon#wrote, iclass 40, count 2 2006.231.08:15:22.41#ibcon#about to read 3, iclass 40, count 2 2006.231.08:15:22.44#ibcon#read 3, iclass 40, count 2 2006.231.08:15:22.44#ibcon#about to read 4, iclass 40, count 2 2006.231.08:15:22.44#ibcon#read 4, iclass 40, count 2 2006.231.08:15:22.44#ibcon#about to read 5, iclass 40, count 2 2006.231.08:15:22.44#ibcon#read 5, iclass 40, count 2 2006.231.08:15:22.44#ibcon#about to read 6, iclass 40, count 2 2006.231.08:15:22.44#ibcon#read 6, iclass 40, count 2 2006.231.08:15:22.44#ibcon#end of sib2, iclass 40, count 2 2006.231.08:15:22.44#ibcon#*after write, iclass 40, count 2 2006.231.08:15:22.44#ibcon#*before return 0, iclass 40, count 2 2006.231.08:15:22.44#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:15:22.44#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:15:22.44#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.08:15:22.44#ibcon#ireg 7 cls_cnt 0 2006.231.08:15:22.44#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:15:22.56#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:15:22.56#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:15:22.56#ibcon#enter wrdev, iclass 40, count 0 2006.231.08:15:22.56#ibcon#first serial, iclass 40, count 0 2006.231.08:15:22.56#ibcon#enter sib2, iclass 40, count 0 2006.231.08:15:22.56#ibcon#flushed, iclass 40, count 0 2006.231.08:15:22.56#ibcon#about to write, iclass 40, count 0 2006.231.08:15:22.56#ibcon#wrote, iclass 40, count 0 2006.231.08:15:22.56#ibcon#about to read 3, iclass 40, count 0 2006.231.08:15:22.58#ibcon#read 3, iclass 40, count 0 2006.231.08:15:22.58#ibcon#about to read 4, iclass 40, count 0 2006.231.08:15:22.58#ibcon#read 4, iclass 40, count 0 2006.231.08:15:22.58#ibcon#about to read 5, iclass 40, count 0 2006.231.08:15:22.58#ibcon#read 5, iclass 40, count 0 2006.231.08:15:22.58#ibcon#about to read 6, iclass 40, count 0 2006.231.08:15:22.58#ibcon#read 6, iclass 40, count 0 2006.231.08:15:22.58#ibcon#end of sib2, iclass 40, count 0 2006.231.08:15:22.58#ibcon#*mode == 0, iclass 40, count 0 2006.231.08:15:22.58#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.08:15:22.58#ibcon#[27=USB\r\n] 2006.231.08:15:22.58#ibcon#*before write, iclass 40, count 0 2006.231.08:15:22.58#ibcon#enter sib2, iclass 40, count 0 2006.231.08:15:22.58#ibcon#flushed, iclass 40, count 0 2006.231.08:15:22.58#ibcon#about to write, iclass 40, count 0 2006.231.08:15:22.58#ibcon#wrote, iclass 40, count 0 2006.231.08:15:22.58#ibcon#about to read 3, iclass 40, count 0 2006.231.08:15:22.61#ibcon#read 3, iclass 40, count 0 2006.231.08:15:22.61#ibcon#about to read 4, iclass 40, count 0 2006.231.08:15:22.61#ibcon#read 4, iclass 40, count 0 2006.231.08:15:22.61#ibcon#about to read 5, iclass 40, count 0 2006.231.08:15:22.61#ibcon#read 5, iclass 40, count 0 2006.231.08:15:22.61#ibcon#about to read 6, iclass 40, count 0 2006.231.08:15:22.61#ibcon#read 6, iclass 40, count 0 2006.231.08:15:22.61#ibcon#end of sib2, iclass 40, count 0 2006.231.08:15:22.61#ibcon#*after write, iclass 40, count 0 2006.231.08:15:22.61#ibcon#*before return 0, iclass 40, count 0 2006.231.08:15:22.61#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:15:22.61#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:15:22.61#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.08:15:22.61#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.08:15:22.61$vc4f8/vabw=wide 2006.231.08:15:22.61#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.08:15:22.61#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.08:15:22.61#ibcon#ireg 8 cls_cnt 0 2006.231.08:15:22.61#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:15:22.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:15:22.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:15:22.61#ibcon#enter wrdev, iclass 4, count 0 2006.231.08:15:22.61#ibcon#first serial, iclass 4, count 0 2006.231.08:15:22.61#ibcon#enter sib2, iclass 4, count 0 2006.231.08:15:22.61#ibcon#flushed, iclass 4, count 0 2006.231.08:15:22.61#ibcon#about to write, iclass 4, count 0 2006.231.08:15:22.61#ibcon#wrote, iclass 4, count 0 2006.231.08:15:22.61#ibcon#about to read 3, iclass 4, count 0 2006.231.08:15:22.64#ibcon#read 3, iclass 4, count 0 2006.231.08:15:22.64#ibcon#about to read 4, iclass 4, count 0 2006.231.08:15:22.64#ibcon#read 4, iclass 4, count 0 2006.231.08:15:22.64#ibcon#about to read 5, iclass 4, count 0 2006.231.08:15:22.64#ibcon#read 5, iclass 4, count 0 2006.231.08:15:22.64#ibcon#about to read 6, iclass 4, count 0 2006.231.08:15:22.64#ibcon#read 6, iclass 4, count 0 2006.231.08:15:22.64#ibcon#end of sib2, iclass 4, count 0 2006.231.08:15:22.64#ibcon#*mode == 0, iclass 4, count 0 2006.231.08:15:22.64#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.08:15:22.64#ibcon#[25=BW32\r\n] 2006.231.08:15:22.64#ibcon#*before write, iclass 4, count 0 2006.231.08:15:22.64#ibcon#enter sib2, iclass 4, count 0 2006.231.08:15:22.64#ibcon#flushed, iclass 4, count 0 2006.231.08:15:22.64#ibcon#about to write, iclass 4, count 0 2006.231.08:15:22.64#ibcon#wrote, iclass 4, count 0 2006.231.08:15:22.64#ibcon#about to read 3, iclass 4, count 0 2006.231.08:15:22.67#ibcon#read 3, iclass 4, count 0 2006.231.08:15:22.67#ibcon#about to read 4, iclass 4, count 0 2006.231.08:15:22.67#ibcon#read 4, iclass 4, count 0 2006.231.08:15:22.67#ibcon#about to read 5, iclass 4, count 0 2006.231.08:15:22.67#ibcon#read 5, iclass 4, count 0 2006.231.08:15:22.67#ibcon#about to read 6, iclass 4, count 0 2006.231.08:15:22.67#ibcon#read 6, iclass 4, count 0 2006.231.08:15:22.67#ibcon#end of sib2, iclass 4, count 0 2006.231.08:15:22.67#ibcon#*after write, iclass 4, count 0 2006.231.08:15:22.67#ibcon#*before return 0, iclass 4, count 0 2006.231.08:15:22.67#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:15:22.67#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:15:22.67#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.08:15:22.67#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.08:15:22.67$vc4f8/vbbw=wide 2006.231.08:15:22.67#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.231.08:15:22.67#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.231.08:15:22.67#ibcon#ireg 8 cls_cnt 0 2006.231.08:15:22.67#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:15:22.73#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:15:22.73#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:15:22.73#ibcon#enter wrdev, iclass 6, count 0 2006.231.08:15:22.73#ibcon#first serial, iclass 6, count 0 2006.231.08:15:22.73#ibcon#enter sib2, iclass 6, count 0 2006.231.08:15:22.73#ibcon#flushed, iclass 6, count 0 2006.231.08:15:22.73#ibcon#about to write, iclass 6, count 0 2006.231.08:15:22.73#ibcon#wrote, iclass 6, count 0 2006.231.08:15:22.73#ibcon#about to read 3, iclass 6, count 0 2006.231.08:15:22.75#ibcon#read 3, iclass 6, count 0 2006.231.08:15:22.75#ibcon#about to read 4, iclass 6, count 0 2006.231.08:15:22.75#ibcon#read 4, iclass 6, count 0 2006.231.08:15:22.75#ibcon#about to read 5, iclass 6, count 0 2006.231.08:15:22.75#ibcon#read 5, iclass 6, count 0 2006.231.08:15:22.75#ibcon#about to read 6, iclass 6, count 0 2006.231.08:15:22.75#ibcon#read 6, iclass 6, count 0 2006.231.08:15:22.75#ibcon#end of sib2, iclass 6, count 0 2006.231.08:15:22.75#ibcon#*mode == 0, iclass 6, count 0 2006.231.08:15:22.75#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.08:15:22.75#ibcon#[27=BW32\r\n] 2006.231.08:15:22.75#ibcon#*before write, iclass 6, count 0 2006.231.08:15:22.75#ibcon#enter sib2, iclass 6, count 0 2006.231.08:15:22.75#ibcon#flushed, iclass 6, count 0 2006.231.08:15:22.75#ibcon#about to write, iclass 6, count 0 2006.231.08:15:22.75#ibcon#wrote, iclass 6, count 0 2006.231.08:15:22.75#ibcon#about to read 3, iclass 6, count 0 2006.231.08:15:22.78#ibcon#read 3, iclass 6, count 0 2006.231.08:15:22.78#ibcon#about to read 4, iclass 6, count 0 2006.231.08:15:22.78#ibcon#read 4, iclass 6, count 0 2006.231.08:15:22.78#ibcon#about to read 5, iclass 6, count 0 2006.231.08:15:22.78#ibcon#read 5, iclass 6, count 0 2006.231.08:15:22.78#ibcon#about to read 6, iclass 6, count 0 2006.231.08:15:22.78#ibcon#read 6, iclass 6, count 0 2006.231.08:15:22.78#ibcon#end of sib2, iclass 6, count 0 2006.231.08:15:22.78#ibcon#*after write, iclass 6, count 0 2006.231.08:15:22.78#ibcon#*before return 0, iclass 6, count 0 2006.231.08:15:22.78#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:15:22.78#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:15:22.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.08:15:22.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.08:15:22.78$4f8m12a/ifd4f 2006.231.08:15:22.78$ifd4f/lo= 2006.231.08:15:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:15:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:15:22.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:15:22.78$ifd4f/patch= 2006.231.08:15:22.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:15:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:15:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:15:22.78$4f8m12a/"form=m,16.000,1:2 2006.231.08:15:22.78$4f8m12a/"tpicd 2006.231.08:15:22.78$4f8m12a/echo=off 2006.231.08:15:22.78$4f8m12a/xlog=off 2006.231.08:15:22.78:!2006.231.08:15:50 2006.231.08:15:25.14#trakl#Source acquired 2006.231.08:15:26.14#flagr#flagr/antenna,acquired 2006.231.08:15:50.00:preob 2006.231.08:15:51.14/onsource/TRACKING 2006.231.08:15:51.14:!2006.231.08:16:00 2006.231.08:16:00.00:data_valid=on 2006.231.08:16:00.00:midob 2006.231.08:16:00.14/onsource/TRACKING 2006.231.08:16:00.14/wx/30.43,1004.5,83 2006.231.08:16:00.29/cable/+6.3709E-03 2006.231.08:16:01.38/va/01,08,usb,yes,29,31 2006.231.08:16:01.38/va/02,07,usb,yes,29,31 2006.231.08:16:01.38/va/03,08,usb,yes,22,22 2006.231.08:16:01.38/va/04,07,usb,yes,31,33 2006.231.08:16:01.38/va/05,07,usb,yes,34,35 2006.231.08:16:01.38/va/06,06,usb,yes,33,33 2006.231.08:16:01.38/va/07,06,usb,yes,34,33 2006.231.08:16:01.38/va/08,06,usb,yes,36,35 2006.231.08:16:01.61/valo/01,532.99,yes,locked 2006.231.08:16:01.61/valo/02,572.99,yes,locked 2006.231.08:16:01.61/valo/03,672.99,yes,locked 2006.231.08:16:01.61/valo/04,832.99,yes,locked 2006.231.08:16:01.61/valo/05,652.99,yes,locked 2006.231.08:16:01.61/valo/06,772.99,yes,locked 2006.231.08:16:01.61/valo/07,832.99,yes,locked 2006.231.08:16:01.61/valo/08,852.99,yes,locked 2006.231.08:16:02.70/vb/01,04,usb,yes,30,29 2006.231.08:16:02.70/vb/02,04,usb,yes,32,34 2006.231.08:16:02.70/vb/03,04,usb,yes,29,32 2006.231.08:16:02.70/vb/04,04,usb,yes,29,30 2006.231.08:16:02.70/vb/05,03,usb,yes,35,39 2006.231.08:16:02.70/vb/06,04,usb,yes,29,32 2006.231.08:16:02.70/vb/07,04,usb,yes,31,31 2006.231.08:16:02.70/vb/08,04,usb,yes,28,32 2006.231.08:16:02.94/vblo/01,632.99,yes,locked 2006.231.08:16:02.94/vblo/02,640.99,yes,locked 2006.231.08:16:02.94/vblo/03,656.99,yes,locked 2006.231.08:16:02.94/vblo/04,712.99,yes,locked 2006.231.08:16:02.94/vblo/05,744.99,yes,locked 2006.231.08:16:02.94/vblo/06,752.99,yes,locked 2006.231.08:16:02.94/vblo/07,734.99,yes,locked 2006.231.08:16:02.94/vblo/08,744.99,yes,locked 2006.231.08:16:03.09/vabw/8 2006.231.08:16:03.24/vbbw/8 2006.231.08:16:03.34/xfe/off,on,12.5 2006.231.08:16:03.73/ifatt/23,28,28,28 2006.231.08:16:04.07/fmout-gps/S +4.44E-07 2006.231.08:16:04.11:!2006.231.08:17:00 2006.231.08:17:00.01:data_valid=off 2006.231.08:17:00.02:postob 2006.231.08:17:00.22/cable/+6.3726E-03 2006.231.08:17:00.22/wx/30.40,1004.5,83 2006.231.08:17:01.07/fmout-gps/S +4.44E-07 2006.231.08:17:01.07:scan_name=231-0817,k06231,60 2006.231.08:17:01.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.231.08:17:01.15#flagr#flagr/antenna,new-source 2006.231.08:17:02.12:checkk5 2006.231.08:17:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:17:02.87/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:17:03.24/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:17:03.62/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:17:03.98/chk_obsdata//k5ts1/T2310816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:17:04.35/chk_obsdata//k5ts2/T2310816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:17:04.71/chk_obsdata//k5ts3/T2310816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:17:05.08/chk_obsdata//k5ts4/T2310816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.231.08:17:05.77/k5log//k5ts1_log_newline 2006.231.08:17:06.49/k5log//k5ts2_log_newline 2006.231.08:17:07.19/k5log//k5ts3_log_newline 2006.231.08:17:07.88/k5log//k5ts4_log_newline 2006.231.08:17:07.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:17:07.90:4f8m12a=2 2006.231.08:17:07.90$4f8m12a/echo=on 2006.231.08:17:07.90$4f8m12a/pcalon 2006.231.08:17:07.90$pcalon/"no phase cal control is implemented here 2006.231.08:17:07.90$4f8m12a/"tpicd=stop 2006.231.08:17:07.90$4f8m12a/vc4f8 2006.231.08:17:07.90$vc4f8/valo=1,532.99 2006.231.08:17:07.90#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.08:17:07.90#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.08:17:07.90#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:07.90#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:17:07.90#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:17:07.90#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:17:07.90#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:17:07.90#ibcon#first serial, iclass 15, count 0 2006.231.08:17:07.90#ibcon#enter sib2, iclass 15, count 0 2006.231.08:17:07.90#ibcon#flushed, iclass 15, count 0 2006.231.08:17:07.90#ibcon#about to write, iclass 15, count 0 2006.231.08:17:07.91#ibcon#wrote, iclass 15, count 0 2006.231.08:17:07.91#ibcon#about to read 3, iclass 15, count 0 2006.231.08:17:07.95#ibcon#read 3, iclass 15, count 0 2006.231.08:17:07.95#ibcon#about to read 4, iclass 15, count 0 2006.231.08:17:07.95#ibcon#read 4, iclass 15, count 0 2006.231.08:17:07.95#ibcon#about to read 5, iclass 15, count 0 2006.231.08:17:07.95#ibcon#read 5, iclass 15, count 0 2006.231.08:17:07.95#ibcon#about to read 6, iclass 15, count 0 2006.231.08:17:07.95#ibcon#read 6, iclass 15, count 0 2006.231.08:17:07.95#ibcon#end of sib2, iclass 15, count 0 2006.231.08:17:07.95#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:17:07.95#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:17:07.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:17:07.95#ibcon#*before write, iclass 15, count 0 2006.231.08:17:07.95#ibcon#enter sib2, iclass 15, count 0 2006.231.08:17:07.95#ibcon#flushed, iclass 15, count 0 2006.231.08:17:07.95#ibcon#about to write, iclass 15, count 0 2006.231.08:17:07.95#ibcon#wrote, iclass 15, count 0 2006.231.08:17:07.95#ibcon#about to read 3, iclass 15, count 0 2006.231.08:17:07.99#ibcon#read 3, iclass 15, count 0 2006.231.08:17:07.99#ibcon#about to read 4, iclass 15, count 0 2006.231.08:17:07.99#ibcon#read 4, iclass 15, count 0 2006.231.08:17:07.99#ibcon#about to read 5, iclass 15, count 0 2006.231.08:17:07.99#ibcon#read 5, iclass 15, count 0 2006.231.08:17:07.99#ibcon#about to read 6, iclass 15, count 0 2006.231.08:17:07.99#ibcon#read 6, iclass 15, count 0 2006.231.08:17:07.99#ibcon#end of sib2, iclass 15, count 0 2006.231.08:17:07.99#ibcon#*after write, iclass 15, count 0 2006.231.08:17:07.99#ibcon#*before return 0, iclass 15, count 0 2006.231.08:17:07.99#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:17:07.99#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:17:07.99#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:17:07.99#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:17:07.99$vc4f8/va=1,8 2006.231.08:17:07.99#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.08:17:07.99#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.08:17:07.99#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:07.99#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:17:07.99#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:17:07.99#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:17:07.99#ibcon#enter wrdev, iclass 17, count 2 2006.231.08:17:07.99#ibcon#first serial, iclass 17, count 2 2006.231.08:17:07.99#ibcon#enter sib2, iclass 17, count 2 2006.231.08:17:07.99#ibcon#flushed, iclass 17, count 2 2006.231.08:17:07.99#ibcon#about to write, iclass 17, count 2 2006.231.08:17:07.99#ibcon#wrote, iclass 17, count 2 2006.231.08:17:07.99#ibcon#about to read 3, iclass 17, count 2 2006.231.08:17:08.01#ibcon#read 3, iclass 17, count 2 2006.231.08:17:08.01#ibcon#about to read 4, iclass 17, count 2 2006.231.08:17:08.01#ibcon#read 4, iclass 17, count 2 2006.231.08:17:08.01#ibcon#about to read 5, iclass 17, count 2 2006.231.08:17:08.01#ibcon#read 5, iclass 17, count 2 2006.231.08:17:08.01#ibcon#about to read 6, iclass 17, count 2 2006.231.08:17:08.01#ibcon#read 6, iclass 17, count 2 2006.231.08:17:08.01#ibcon#end of sib2, iclass 17, count 2 2006.231.08:17:08.01#ibcon#*mode == 0, iclass 17, count 2 2006.231.08:17:08.01#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.08:17:08.01#ibcon#[25=AT01-08\r\n] 2006.231.08:17:08.01#ibcon#*before write, iclass 17, count 2 2006.231.08:17:08.01#ibcon#enter sib2, iclass 17, count 2 2006.231.08:17:08.01#ibcon#flushed, iclass 17, count 2 2006.231.08:17:08.01#ibcon#about to write, iclass 17, count 2 2006.231.08:17:08.01#ibcon#wrote, iclass 17, count 2 2006.231.08:17:08.01#ibcon#about to read 3, iclass 17, count 2 2006.231.08:17:08.04#ibcon#read 3, iclass 17, count 2 2006.231.08:17:08.04#ibcon#about to read 4, iclass 17, count 2 2006.231.08:17:08.04#ibcon#read 4, iclass 17, count 2 2006.231.08:17:08.04#ibcon#about to read 5, iclass 17, count 2 2006.231.08:17:08.04#ibcon#read 5, iclass 17, count 2 2006.231.08:17:08.04#ibcon#about to read 6, iclass 17, count 2 2006.231.08:17:08.04#ibcon#read 6, iclass 17, count 2 2006.231.08:17:08.04#ibcon#end of sib2, iclass 17, count 2 2006.231.08:17:08.04#ibcon#*after write, iclass 17, count 2 2006.231.08:17:08.04#ibcon#*before return 0, iclass 17, count 2 2006.231.08:17:08.04#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:17:08.04#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:17:08.04#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.08:17:08.04#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:08.04#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:17:08.16#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:17:08.16#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:17:08.16#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:17:08.16#ibcon#first serial, iclass 17, count 0 2006.231.08:17:08.16#ibcon#enter sib2, iclass 17, count 0 2006.231.08:17:08.16#ibcon#flushed, iclass 17, count 0 2006.231.08:17:08.16#ibcon#about to write, iclass 17, count 0 2006.231.08:17:08.16#ibcon#wrote, iclass 17, count 0 2006.231.08:17:08.16#ibcon#about to read 3, iclass 17, count 0 2006.231.08:17:08.18#ibcon#read 3, iclass 17, count 0 2006.231.08:17:08.18#ibcon#about to read 4, iclass 17, count 0 2006.231.08:17:08.18#ibcon#read 4, iclass 17, count 0 2006.231.08:17:08.18#ibcon#about to read 5, iclass 17, count 0 2006.231.08:17:08.18#ibcon#read 5, iclass 17, count 0 2006.231.08:17:08.18#ibcon#about to read 6, iclass 17, count 0 2006.231.08:17:08.18#ibcon#read 6, iclass 17, count 0 2006.231.08:17:08.18#ibcon#end of sib2, iclass 17, count 0 2006.231.08:17:08.18#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:17:08.18#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:17:08.18#ibcon#[25=USB\r\n] 2006.231.08:17:08.18#ibcon#*before write, iclass 17, count 0 2006.231.08:17:08.18#ibcon#enter sib2, iclass 17, count 0 2006.231.08:17:08.18#ibcon#flushed, iclass 17, count 0 2006.231.08:17:08.18#ibcon#about to write, iclass 17, count 0 2006.231.08:17:08.18#ibcon#wrote, iclass 17, count 0 2006.231.08:17:08.18#ibcon#about to read 3, iclass 17, count 0 2006.231.08:17:08.21#ibcon#read 3, iclass 17, count 0 2006.231.08:17:08.21#ibcon#about to read 4, iclass 17, count 0 2006.231.08:17:08.21#ibcon#read 4, iclass 17, count 0 2006.231.08:17:08.21#ibcon#about to read 5, iclass 17, count 0 2006.231.08:17:08.21#ibcon#read 5, iclass 17, count 0 2006.231.08:17:08.21#ibcon#about to read 6, iclass 17, count 0 2006.231.08:17:08.21#ibcon#read 6, iclass 17, count 0 2006.231.08:17:08.21#ibcon#end of sib2, iclass 17, count 0 2006.231.08:17:08.21#ibcon#*after write, iclass 17, count 0 2006.231.08:17:08.21#ibcon#*before return 0, iclass 17, count 0 2006.231.08:17:08.21#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:17:08.21#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:17:08.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:17:08.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:17:08.21$vc4f8/valo=2,572.99 2006.231.08:17:08.22#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.08:17:08.22#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.08:17:08.22#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:08.22#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:17:08.22#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:17:08.22#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:17:08.22#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:17:08.22#ibcon#first serial, iclass 19, count 0 2006.231.08:17:08.22#ibcon#enter sib2, iclass 19, count 0 2006.231.08:17:08.22#ibcon#flushed, iclass 19, count 0 2006.231.08:17:08.22#ibcon#about to write, iclass 19, count 0 2006.231.08:17:08.22#ibcon#wrote, iclass 19, count 0 2006.231.08:17:08.22#ibcon#about to read 3, iclass 19, count 0 2006.231.08:17:08.23#ibcon#read 3, iclass 19, count 0 2006.231.08:17:08.23#ibcon#about to read 4, iclass 19, count 0 2006.231.08:17:08.23#ibcon#read 4, iclass 19, count 0 2006.231.08:17:08.23#ibcon#about to read 5, iclass 19, count 0 2006.231.08:17:08.23#ibcon#read 5, iclass 19, count 0 2006.231.08:17:08.23#ibcon#about to read 6, iclass 19, count 0 2006.231.08:17:08.23#ibcon#read 6, iclass 19, count 0 2006.231.08:17:08.23#ibcon#end of sib2, iclass 19, count 0 2006.231.08:17:08.23#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:17:08.23#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:17:08.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:17:08.23#ibcon#*before write, iclass 19, count 0 2006.231.08:17:08.23#ibcon#enter sib2, iclass 19, count 0 2006.231.08:17:08.23#ibcon#flushed, iclass 19, count 0 2006.231.08:17:08.23#ibcon#about to write, iclass 19, count 0 2006.231.08:17:08.23#ibcon#wrote, iclass 19, count 0 2006.231.08:17:08.23#ibcon#about to read 3, iclass 19, count 0 2006.231.08:17:08.27#ibcon#read 3, iclass 19, count 0 2006.231.08:17:08.27#ibcon#about to read 4, iclass 19, count 0 2006.231.08:17:08.27#ibcon#read 4, iclass 19, count 0 2006.231.08:17:08.27#ibcon#about to read 5, iclass 19, count 0 2006.231.08:17:08.27#ibcon#read 5, iclass 19, count 0 2006.231.08:17:08.27#ibcon#about to read 6, iclass 19, count 0 2006.231.08:17:08.27#ibcon#read 6, iclass 19, count 0 2006.231.08:17:08.27#ibcon#end of sib2, iclass 19, count 0 2006.231.08:17:08.27#ibcon#*after write, iclass 19, count 0 2006.231.08:17:08.27#ibcon#*before return 0, iclass 19, count 0 2006.231.08:17:08.27#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:17:08.27#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:17:08.27#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:17:08.27#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:17:08.27$vc4f8/va=2,7 2006.231.08:17:08.27#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.231.08:17:08.27#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.231.08:17:08.27#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:08.27#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:17:08.33#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:17:08.33#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:17:08.33#ibcon#enter wrdev, iclass 21, count 2 2006.231.08:17:08.33#ibcon#first serial, iclass 21, count 2 2006.231.08:17:08.33#ibcon#enter sib2, iclass 21, count 2 2006.231.08:17:08.33#ibcon#flushed, iclass 21, count 2 2006.231.08:17:08.33#ibcon#about to write, iclass 21, count 2 2006.231.08:17:08.33#ibcon#wrote, iclass 21, count 2 2006.231.08:17:08.33#ibcon#about to read 3, iclass 21, count 2 2006.231.08:17:08.35#ibcon#read 3, iclass 21, count 2 2006.231.08:17:08.35#ibcon#about to read 4, iclass 21, count 2 2006.231.08:17:08.35#ibcon#read 4, iclass 21, count 2 2006.231.08:17:08.35#ibcon#about to read 5, iclass 21, count 2 2006.231.08:17:08.35#ibcon#read 5, iclass 21, count 2 2006.231.08:17:08.35#ibcon#about to read 6, iclass 21, count 2 2006.231.08:17:08.35#ibcon#read 6, iclass 21, count 2 2006.231.08:17:08.35#ibcon#end of sib2, iclass 21, count 2 2006.231.08:17:08.35#ibcon#*mode == 0, iclass 21, count 2 2006.231.08:17:08.35#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.231.08:17:08.35#ibcon#[25=AT02-07\r\n] 2006.231.08:17:08.35#ibcon#*before write, iclass 21, count 2 2006.231.08:17:08.35#ibcon#enter sib2, iclass 21, count 2 2006.231.08:17:08.35#ibcon#flushed, iclass 21, count 2 2006.231.08:17:08.35#ibcon#about to write, iclass 21, count 2 2006.231.08:17:08.35#ibcon#wrote, iclass 21, count 2 2006.231.08:17:08.35#ibcon#about to read 3, iclass 21, count 2 2006.231.08:17:08.38#ibcon#read 3, iclass 21, count 2 2006.231.08:17:08.38#ibcon#about to read 4, iclass 21, count 2 2006.231.08:17:08.38#ibcon#read 4, iclass 21, count 2 2006.231.08:17:08.38#ibcon#about to read 5, iclass 21, count 2 2006.231.08:17:08.38#ibcon#read 5, iclass 21, count 2 2006.231.08:17:08.38#ibcon#about to read 6, iclass 21, count 2 2006.231.08:17:08.38#ibcon#read 6, iclass 21, count 2 2006.231.08:17:08.38#ibcon#end of sib2, iclass 21, count 2 2006.231.08:17:08.38#ibcon#*after write, iclass 21, count 2 2006.231.08:17:08.38#ibcon#*before return 0, iclass 21, count 2 2006.231.08:17:08.38#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:17:08.38#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:17:08.38#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.231.08:17:08.38#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:08.38#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:17:08.50#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:17:08.50#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:17:08.50#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:17:08.50#ibcon#first serial, iclass 21, count 0 2006.231.08:17:08.50#ibcon#enter sib2, iclass 21, count 0 2006.231.08:17:08.50#ibcon#flushed, iclass 21, count 0 2006.231.08:17:08.50#ibcon#about to write, iclass 21, count 0 2006.231.08:17:08.50#ibcon#wrote, iclass 21, count 0 2006.231.08:17:08.50#ibcon#about to read 3, iclass 21, count 0 2006.231.08:17:08.52#ibcon#read 3, iclass 21, count 0 2006.231.08:17:08.52#ibcon#about to read 4, iclass 21, count 0 2006.231.08:17:08.52#ibcon#read 4, iclass 21, count 0 2006.231.08:17:08.52#ibcon#about to read 5, iclass 21, count 0 2006.231.08:17:08.52#ibcon#read 5, iclass 21, count 0 2006.231.08:17:08.52#ibcon#about to read 6, iclass 21, count 0 2006.231.08:17:08.52#ibcon#read 6, iclass 21, count 0 2006.231.08:17:08.52#ibcon#end of sib2, iclass 21, count 0 2006.231.08:17:08.52#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:17:08.52#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:17:08.52#ibcon#[25=USB\r\n] 2006.231.08:17:08.52#ibcon#*before write, iclass 21, count 0 2006.231.08:17:08.52#ibcon#enter sib2, iclass 21, count 0 2006.231.08:17:08.52#ibcon#flushed, iclass 21, count 0 2006.231.08:17:08.52#ibcon#about to write, iclass 21, count 0 2006.231.08:17:08.52#ibcon#wrote, iclass 21, count 0 2006.231.08:17:08.52#ibcon#about to read 3, iclass 21, count 0 2006.231.08:17:08.55#ibcon#read 3, iclass 21, count 0 2006.231.08:17:08.55#ibcon#about to read 4, iclass 21, count 0 2006.231.08:17:08.55#ibcon#read 4, iclass 21, count 0 2006.231.08:17:08.55#ibcon#about to read 5, iclass 21, count 0 2006.231.08:17:08.55#ibcon#read 5, iclass 21, count 0 2006.231.08:17:08.55#ibcon#about to read 6, iclass 21, count 0 2006.231.08:17:08.55#ibcon#read 6, iclass 21, count 0 2006.231.08:17:08.55#ibcon#end of sib2, iclass 21, count 0 2006.231.08:17:08.55#ibcon#*after write, iclass 21, count 0 2006.231.08:17:08.55#ibcon#*before return 0, iclass 21, count 0 2006.231.08:17:08.55#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:17:08.55#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:17:08.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:17:08.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:17:08.55$vc4f8/valo=3,672.99 2006.231.08:17:08.55#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.231.08:17:08.55#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.231.08:17:08.55#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:08.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:17:08.55#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:17:08.55#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:17:08.55#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:17:08.55#ibcon#first serial, iclass 23, count 0 2006.231.08:17:08.55#ibcon#enter sib2, iclass 23, count 0 2006.231.08:17:08.55#ibcon#flushed, iclass 23, count 0 2006.231.08:17:08.55#ibcon#about to write, iclass 23, count 0 2006.231.08:17:08.55#ibcon#wrote, iclass 23, count 0 2006.231.08:17:08.55#ibcon#about to read 3, iclass 23, count 0 2006.231.08:17:08.57#ibcon#read 3, iclass 23, count 0 2006.231.08:17:08.57#ibcon#about to read 4, iclass 23, count 0 2006.231.08:17:08.57#ibcon#read 4, iclass 23, count 0 2006.231.08:17:08.57#ibcon#about to read 5, iclass 23, count 0 2006.231.08:17:08.57#ibcon#read 5, iclass 23, count 0 2006.231.08:17:08.57#ibcon#about to read 6, iclass 23, count 0 2006.231.08:17:08.57#ibcon#read 6, iclass 23, count 0 2006.231.08:17:08.57#ibcon#end of sib2, iclass 23, count 0 2006.231.08:17:08.57#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:17:08.57#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:17:08.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:17:08.57#ibcon#*before write, iclass 23, count 0 2006.231.08:17:08.57#ibcon#enter sib2, iclass 23, count 0 2006.231.08:17:08.57#ibcon#flushed, iclass 23, count 0 2006.231.08:17:08.57#ibcon#about to write, iclass 23, count 0 2006.231.08:17:08.57#ibcon#wrote, iclass 23, count 0 2006.231.08:17:08.57#ibcon#about to read 3, iclass 23, count 0 2006.231.08:17:08.61#ibcon#read 3, iclass 23, count 0 2006.231.08:17:08.61#ibcon#about to read 4, iclass 23, count 0 2006.231.08:17:08.61#ibcon#read 4, iclass 23, count 0 2006.231.08:17:08.61#ibcon#about to read 5, iclass 23, count 0 2006.231.08:17:08.61#ibcon#read 5, iclass 23, count 0 2006.231.08:17:08.61#ibcon#about to read 6, iclass 23, count 0 2006.231.08:17:08.61#ibcon#read 6, iclass 23, count 0 2006.231.08:17:08.61#ibcon#end of sib2, iclass 23, count 0 2006.231.08:17:08.61#ibcon#*after write, iclass 23, count 0 2006.231.08:17:08.61#ibcon#*before return 0, iclass 23, count 0 2006.231.08:17:08.61#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:17:08.61#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:17:08.61#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:17:08.61#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:17:08.61$vc4f8/va=3,8 2006.231.08:17:08.61#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.231.08:17:08.61#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.231.08:17:08.61#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:08.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:17:08.67#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:17:08.67#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:17:08.67#ibcon#enter wrdev, iclass 25, count 2 2006.231.08:17:08.67#ibcon#first serial, iclass 25, count 2 2006.231.08:17:08.67#ibcon#enter sib2, iclass 25, count 2 2006.231.08:17:08.67#ibcon#flushed, iclass 25, count 2 2006.231.08:17:08.67#ibcon#about to write, iclass 25, count 2 2006.231.08:17:08.67#ibcon#wrote, iclass 25, count 2 2006.231.08:17:08.67#ibcon#about to read 3, iclass 25, count 2 2006.231.08:17:08.69#ibcon#read 3, iclass 25, count 2 2006.231.08:17:08.69#ibcon#about to read 4, iclass 25, count 2 2006.231.08:17:08.69#ibcon#read 4, iclass 25, count 2 2006.231.08:17:08.69#ibcon#about to read 5, iclass 25, count 2 2006.231.08:17:08.69#ibcon#read 5, iclass 25, count 2 2006.231.08:17:08.69#ibcon#about to read 6, iclass 25, count 2 2006.231.08:17:08.69#ibcon#read 6, iclass 25, count 2 2006.231.08:17:08.69#ibcon#end of sib2, iclass 25, count 2 2006.231.08:17:08.69#ibcon#*mode == 0, iclass 25, count 2 2006.231.08:17:08.69#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.231.08:17:08.69#ibcon#[25=AT03-08\r\n] 2006.231.08:17:08.69#ibcon#*before write, iclass 25, count 2 2006.231.08:17:08.69#ibcon#enter sib2, iclass 25, count 2 2006.231.08:17:08.69#ibcon#flushed, iclass 25, count 2 2006.231.08:17:08.69#ibcon#about to write, iclass 25, count 2 2006.231.08:17:08.69#ibcon#wrote, iclass 25, count 2 2006.231.08:17:08.69#ibcon#about to read 3, iclass 25, count 2 2006.231.08:17:08.72#ibcon#read 3, iclass 25, count 2 2006.231.08:17:08.72#ibcon#about to read 4, iclass 25, count 2 2006.231.08:17:08.72#ibcon#read 4, iclass 25, count 2 2006.231.08:17:08.72#ibcon#about to read 5, iclass 25, count 2 2006.231.08:17:08.72#ibcon#read 5, iclass 25, count 2 2006.231.08:17:08.72#ibcon#about to read 6, iclass 25, count 2 2006.231.08:17:08.72#ibcon#read 6, iclass 25, count 2 2006.231.08:17:08.72#ibcon#end of sib2, iclass 25, count 2 2006.231.08:17:08.72#ibcon#*after write, iclass 25, count 2 2006.231.08:17:08.72#ibcon#*before return 0, iclass 25, count 2 2006.231.08:17:08.72#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:17:08.72#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:17:08.72#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.231.08:17:08.72#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:08.72#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:17:08.84#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:17:08.84#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:17:08.84#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:17:08.84#ibcon#first serial, iclass 25, count 0 2006.231.08:17:08.84#ibcon#enter sib2, iclass 25, count 0 2006.231.08:17:08.84#ibcon#flushed, iclass 25, count 0 2006.231.08:17:08.84#ibcon#about to write, iclass 25, count 0 2006.231.08:17:08.84#ibcon#wrote, iclass 25, count 0 2006.231.08:17:08.84#ibcon#about to read 3, iclass 25, count 0 2006.231.08:17:08.86#ibcon#read 3, iclass 25, count 0 2006.231.08:17:08.86#ibcon#about to read 4, iclass 25, count 0 2006.231.08:17:08.86#ibcon#read 4, iclass 25, count 0 2006.231.08:17:08.86#ibcon#about to read 5, iclass 25, count 0 2006.231.08:17:08.86#ibcon#read 5, iclass 25, count 0 2006.231.08:17:08.86#ibcon#about to read 6, iclass 25, count 0 2006.231.08:17:08.86#ibcon#read 6, iclass 25, count 0 2006.231.08:17:08.86#ibcon#end of sib2, iclass 25, count 0 2006.231.08:17:08.86#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:17:08.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:17:08.86#ibcon#[25=USB\r\n] 2006.231.08:17:08.86#ibcon#*before write, iclass 25, count 0 2006.231.08:17:08.86#ibcon#enter sib2, iclass 25, count 0 2006.231.08:17:08.86#ibcon#flushed, iclass 25, count 0 2006.231.08:17:08.86#ibcon#about to write, iclass 25, count 0 2006.231.08:17:08.86#ibcon#wrote, iclass 25, count 0 2006.231.08:17:08.86#ibcon#about to read 3, iclass 25, count 0 2006.231.08:17:08.89#ibcon#read 3, iclass 25, count 0 2006.231.08:17:08.89#ibcon#about to read 4, iclass 25, count 0 2006.231.08:17:08.89#ibcon#read 4, iclass 25, count 0 2006.231.08:17:08.89#ibcon#about to read 5, iclass 25, count 0 2006.231.08:17:08.89#ibcon#read 5, iclass 25, count 0 2006.231.08:17:08.89#ibcon#about to read 6, iclass 25, count 0 2006.231.08:17:08.89#ibcon#read 6, iclass 25, count 0 2006.231.08:17:08.89#ibcon#end of sib2, iclass 25, count 0 2006.231.08:17:08.89#ibcon#*after write, iclass 25, count 0 2006.231.08:17:08.89#ibcon#*before return 0, iclass 25, count 0 2006.231.08:17:08.89#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:17:08.89#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:17:08.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:17:08.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:17:08.89$vc4f8/valo=4,832.99 2006.231.08:17:08.89#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.231.08:17:08.89#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.231.08:17:08.89#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:08.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:17:08.89#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:17:08.89#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:17:08.89#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:17:08.89#ibcon#first serial, iclass 27, count 0 2006.231.08:17:08.89#ibcon#enter sib2, iclass 27, count 0 2006.231.08:17:08.89#ibcon#flushed, iclass 27, count 0 2006.231.08:17:08.89#ibcon#about to write, iclass 27, count 0 2006.231.08:17:08.89#ibcon#wrote, iclass 27, count 0 2006.231.08:17:08.89#ibcon#about to read 3, iclass 27, count 0 2006.231.08:17:08.91#ibcon#read 3, iclass 27, count 0 2006.231.08:17:08.91#ibcon#about to read 4, iclass 27, count 0 2006.231.08:17:08.91#ibcon#read 4, iclass 27, count 0 2006.231.08:17:08.91#ibcon#about to read 5, iclass 27, count 0 2006.231.08:17:08.91#ibcon#read 5, iclass 27, count 0 2006.231.08:17:08.91#ibcon#about to read 6, iclass 27, count 0 2006.231.08:17:08.91#ibcon#read 6, iclass 27, count 0 2006.231.08:17:08.91#ibcon#end of sib2, iclass 27, count 0 2006.231.08:17:08.91#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:17:08.91#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:17:08.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:17:08.91#ibcon#*before write, iclass 27, count 0 2006.231.08:17:08.91#ibcon#enter sib2, iclass 27, count 0 2006.231.08:17:08.91#ibcon#flushed, iclass 27, count 0 2006.231.08:17:08.91#ibcon#about to write, iclass 27, count 0 2006.231.08:17:08.91#ibcon#wrote, iclass 27, count 0 2006.231.08:17:08.91#ibcon#about to read 3, iclass 27, count 0 2006.231.08:17:08.95#ibcon#read 3, iclass 27, count 0 2006.231.08:17:08.95#ibcon#about to read 4, iclass 27, count 0 2006.231.08:17:08.95#ibcon#read 4, iclass 27, count 0 2006.231.08:17:08.95#ibcon#about to read 5, iclass 27, count 0 2006.231.08:17:08.95#ibcon#read 5, iclass 27, count 0 2006.231.08:17:08.95#ibcon#about to read 6, iclass 27, count 0 2006.231.08:17:08.95#ibcon#read 6, iclass 27, count 0 2006.231.08:17:08.95#ibcon#end of sib2, iclass 27, count 0 2006.231.08:17:08.95#ibcon#*after write, iclass 27, count 0 2006.231.08:17:08.95#ibcon#*before return 0, iclass 27, count 0 2006.231.08:17:08.95#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:17:08.95#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:17:08.95#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:17:08.95#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:17:08.95$vc4f8/va=4,7 2006.231.08:17:08.95#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.231.08:17:08.95#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.231.08:17:08.95#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:08.95#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:17:09.01#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:17:09.01#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:17:09.01#ibcon#enter wrdev, iclass 29, count 2 2006.231.08:17:09.01#ibcon#first serial, iclass 29, count 2 2006.231.08:17:09.01#ibcon#enter sib2, iclass 29, count 2 2006.231.08:17:09.01#ibcon#flushed, iclass 29, count 2 2006.231.08:17:09.01#ibcon#about to write, iclass 29, count 2 2006.231.08:17:09.01#ibcon#wrote, iclass 29, count 2 2006.231.08:17:09.01#ibcon#about to read 3, iclass 29, count 2 2006.231.08:17:09.03#ibcon#read 3, iclass 29, count 2 2006.231.08:17:09.03#ibcon#about to read 4, iclass 29, count 2 2006.231.08:17:09.03#ibcon#read 4, iclass 29, count 2 2006.231.08:17:09.03#ibcon#about to read 5, iclass 29, count 2 2006.231.08:17:09.03#ibcon#read 5, iclass 29, count 2 2006.231.08:17:09.03#ibcon#about to read 6, iclass 29, count 2 2006.231.08:17:09.03#ibcon#read 6, iclass 29, count 2 2006.231.08:17:09.03#ibcon#end of sib2, iclass 29, count 2 2006.231.08:17:09.03#ibcon#*mode == 0, iclass 29, count 2 2006.231.08:17:09.03#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.231.08:17:09.03#ibcon#[25=AT04-07\r\n] 2006.231.08:17:09.03#ibcon#*before write, iclass 29, count 2 2006.231.08:17:09.03#ibcon#enter sib2, iclass 29, count 2 2006.231.08:17:09.03#ibcon#flushed, iclass 29, count 2 2006.231.08:17:09.03#ibcon#about to write, iclass 29, count 2 2006.231.08:17:09.03#ibcon#wrote, iclass 29, count 2 2006.231.08:17:09.03#ibcon#about to read 3, iclass 29, count 2 2006.231.08:17:09.06#ibcon#read 3, iclass 29, count 2 2006.231.08:17:09.06#ibcon#about to read 4, iclass 29, count 2 2006.231.08:17:09.06#ibcon#read 4, iclass 29, count 2 2006.231.08:17:09.06#ibcon#about to read 5, iclass 29, count 2 2006.231.08:17:09.06#ibcon#read 5, iclass 29, count 2 2006.231.08:17:09.06#ibcon#about to read 6, iclass 29, count 2 2006.231.08:17:09.06#ibcon#read 6, iclass 29, count 2 2006.231.08:17:09.06#ibcon#end of sib2, iclass 29, count 2 2006.231.08:17:09.06#ibcon#*after write, iclass 29, count 2 2006.231.08:17:09.06#ibcon#*before return 0, iclass 29, count 2 2006.231.08:17:09.06#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:17:09.06#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:17:09.06#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.231.08:17:09.06#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:09.06#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:17:09.18#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:17:09.18#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:17:09.18#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:17:09.18#ibcon#first serial, iclass 29, count 0 2006.231.08:17:09.18#ibcon#enter sib2, iclass 29, count 0 2006.231.08:17:09.18#ibcon#flushed, iclass 29, count 0 2006.231.08:17:09.18#ibcon#about to write, iclass 29, count 0 2006.231.08:17:09.18#ibcon#wrote, iclass 29, count 0 2006.231.08:17:09.18#ibcon#about to read 3, iclass 29, count 0 2006.231.08:17:09.20#ibcon#read 3, iclass 29, count 0 2006.231.08:17:09.20#ibcon#about to read 4, iclass 29, count 0 2006.231.08:17:09.20#ibcon#read 4, iclass 29, count 0 2006.231.08:17:09.20#ibcon#about to read 5, iclass 29, count 0 2006.231.08:17:09.20#ibcon#read 5, iclass 29, count 0 2006.231.08:17:09.20#ibcon#about to read 6, iclass 29, count 0 2006.231.08:17:09.20#ibcon#read 6, iclass 29, count 0 2006.231.08:17:09.20#ibcon#end of sib2, iclass 29, count 0 2006.231.08:17:09.20#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:17:09.20#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:17:09.20#ibcon#[25=USB\r\n] 2006.231.08:17:09.20#ibcon#*before write, iclass 29, count 0 2006.231.08:17:09.20#ibcon#enter sib2, iclass 29, count 0 2006.231.08:17:09.20#ibcon#flushed, iclass 29, count 0 2006.231.08:17:09.20#ibcon#about to write, iclass 29, count 0 2006.231.08:17:09.20#ibcon#wrote, iclass 29, count 0 2006.231.08:17:09.20#ibcon#about to read 3, iclass 29, count 0 2006.231.08:17:09.23#ibcon#read 3, iclass 29, count 0 2006.231.08:17:09.23#ibcon#about to read 4, iclass 29, count 0 2006.231.08:17:09.23#ibcon#read 4, iclass 29, count 0 2006.231.08:17:09.23#ibcon#about to read 5, iclass 29, count 0 2006.231.08:17:09.23#ibcon#read 5, iclass 29, count 0 2006.231.08:17:09.23#ibcon#about to read 6, iclass 29, count 0 2006.231.08:17:09.23#ibcon#read 6, iclass 29, count 0 2006.231.08:17:09.23#ibcon#end of sib2, iclass 29, count 0 2006.231.08:17:09.23#ibcon#*after write, iclass 29, count 0 2006.231.08:17:09.23#ibcon#*before return 0, iclass 29, count 0 2006.231.08:17:09.23#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:17:09.23#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:17:09.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:17:09.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:17:09.23$vc4f8/valo=5,652.99 2006.231.08:17:09.23#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.231.08:17:09.23#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.231.08:17:09.23#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:09.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:17:09.23#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:17:09.23#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:17:09.23#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:17:09.23#ibcon#first serial, iclass 31, count 0 2006.231.08:17:09.23#ibcon#enter sib2, iclass 31, count 0 2006.231.08:17:09.23#ibcon#flushed, iclass 31, count 0 2006.231.08:17:09.23#ibcon#about to write, iclass 31, count 0 2006.231.08:17:09.23#ibcon#wrote, iclass 31, count 0 2006.231.08:17:09.23#ibcon#about to read 3, iclass 31, count 0 2006.231.08:17:09.25#ibcon#read 3, iclass 31, count 0 2006.231.08:17:09.25#ibcon#about to read 4, iclass 31, count 0 2006.231.08:17:09.25#ibcon#read 4, iclass 31, count 0 2006.231.08:17:09.25#ibcon#about to read 5, iclass 31, count 0 2006.231.08:17:09.25#ibcon#read 5, iclass 31, count 0 2006.231.08:17:09.25#ibcon#about to read 6, iclass 31, count 0 2006.231.08:17:09.25#ibcon#read 6, iclass 31, count 0 2006.231.08:17:09.25#ibcon#end of sib2, iclass 31, count 0 2006.231.08:17:09.25#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:17:09.25#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:17:09.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:17:09.25#ibcon#*before write, iclass 31, count 0 2006.231.08:17:09.25#ibcon#enter sib2, iclass 31, count 0 2006.231.08:17:09.25#ibcon#flushed, iclass 31, count 0 2006.231.08:17:09.25#ibcon#about to write, iclass 31, count 0 2006.231.08:17:09.25#ibcon#wrote, iclass 31, count 0 2006.231.08:17:09.25#ibcon#about to read 3, iclass 31, count 0 2006.231.08:17:09.29#ibcon#read 3, iclass 31, count 0 2006.231.08:17:09.29#ibcon#about to read 4, iclass 31, count 0 2006.231.08:17:09.29#ibcon#read 4, iclass 31, count 0 2006.231.08:17:09.29#ibcon#about to read 5, iclass 31, count 0 2006.231.08:17:09.29#ibcon#read 5, iclass 31, count 0 2006.231.08:17:09.29#ibcon#about to read 6, iclass 31, count 0 2006.231.08:17:09.29#ibcon#read 6, iclass 31, count 0 2006.231.08:17:09.29#ibcon#end of sib2, iclass 31, count 0 2006.231.08:17:09.29#ibcon#*after write, iclass 31, count 0 2006.231.08:17:09.29#ibcon#*before return 0, iclass 31, count 0 2006.231.08:17:09.29#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:17:09.29#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:17:09.29#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:17:09.29#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:17:09.29$vc4f8/va=5,7 2006.231.08:17:09.29#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.231.08:17:09.29#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.231.08:17:09.29#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:09.29#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:17:09.36#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:17:09.36#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:17:09.36#ibcon#enter wrdev, iclass 33, count 2 2006.231.08:17:09.36#ibcon#first serial, iclass 33, count 2 2006.231.08:17:09.36#ibcon#enter sib2, iclass 33, count 2 2006.231.08:17:09.36#ibcon#flushed, iclass 33, count 2 2006.231.08:17:09.36#ibcon#about to write, iclass 33, count 2 2006.231.08:17:09.36#ibcon#wrote, iclass 33, count 2 2006.231.08:17:09.36#ibcon#about to read 3, iclass 33, count 2 2006.231.08:17:09.37#ibcon#read 3, iclass 33, count 2 2006.231.08:17:09.37#ibcon#about to read 4, iclass 33, count 2 2006.231.08:17:09.37#ibcon#read 4, iclass 33, count 2 2006.231.08:17:09.37#ibcon#about to read 5, iclass 33, count 2 2006.231.08:17:09.37#ibcon#read 5, iclass 33, count 2 2006.231.08:17:09.37#ibcon#about to read 6, iclass 33, count 2 2006.231.08:17:09.37#ibcon#read 6, iclass 33, count 2 2006.231.08:17:09.37#ibcon#end of sib2, iclass 33, count 2 2006.231.08:17:09.37#ibcon#*mode == 0, iclass 33, count 2 2006.231.08:17:09.37#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.231.08:17:09.37#ibcon#[25=AT05-07\r\n] 2006.231.08:17:09.37#ibcon#*before write, iclass 33, count 2 2006.231.08:17:09.37#ibcon#enter sib2, iclass 33, count 2 2006.231.08:17:09.37#ibcon#flushed, iclass 33, count 2 2006.231.08:17:09.37#ibcon#about to write, iclass 33, count 2 2006.231.08:17:09.37#ibcon#wrote, iclass 33, count 2 2006.231.08:17:09.37#ibcon#about to read 3, iclass 33, count 2 2006.231.08:17:09.38#abcon#<5=/06 3.8 7.2 30.40 831004.5\r\n> 2006.231.08:17:09.40#abcon#{5=INTERFACE CLEAR} 2006.231.08:17:09.40#ibcon#read 3, iclass 33, count 2 2006.231.08:17:09.40#ibcon#about to read 4, iclass 33, count 2 2006.231.08:17:09.40#ibcon#read 4, iclass 33, count 2 2006.231.08:17:09.40#ibcon#about to read 5, iclass 33, count 2 2006.231.08:17:09.40#ibcon#read 5, iclass 33, count 2 2006.231.08:17:09.40#ibcon#about to read 6, iclass 33, count 2 2006.231.08:17:09.40#ibcon#read 6, iclass 33, count 2 2006.231.08:17:09.40#ibcon#end of sib2, iclass 33, count 2 2006.231.08:17:09.40#ibcon#*after write, iclass 33, count 2 2006.231.08:17:09.40#ibcon#*before return 0, iclass 33, count 2 2006.231.08:17:09.40#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:17:09.40#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:17:09.40#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.231.08:17:09.40#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:09.40#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:17:09.46#abcon#[5=S1D000X0/0*\r\n] 2006.231.08:17:09.52#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:17:09.52#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:17:09.52#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:17:09.52#ibcon#first serial, iclass 33, count 0 2006.231.08:17:09.52#ibcon#enter sib2, iclass 33, count 0 2006.231.08:17:09.52#ibcon#flushed, iclass 33, count 0 2006.231.08:17:09.52#ibcon#about to write, iclass 33, count 0 2006.231.08:17:09.52#ibcon#wrote, iclass 33, count 0 2006.231.08:17:09.52#ibcon#about to read 3, iclass 33, count 0 2006.231.08:17:09.54#ibcon#read 3, iclass 33, count 0 2006.231.08:17:09.54#ibcon#about to read 4, iclass 33, count 0 2006.231.08:17:09.54#ibcon#read 4, iclass 33, count 0 2006.231.08:17:09.54#ibcon#about to read 5, iclass 33, count 0 2006.231.08:17:09.54#ibcon#read 5, iclass 33, count 0 2006.231.08:17:09.54#ibcon#about to read 6, iclass 33, count 0 2006.231.08:17:09.54#ibcon#read 6, iclass 33, count 0 2006.231.08:17:09.54#ibcon#end of sib2, iclass 33, count 0 2006.231.08:17:09.54#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:17:09.54#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:17:09.54#ibcon#[25=USB\r\n] 2006.231.08:17:09.54#ibcon#*before write, iclass 33, count 0 2006.231.08:17:09.54#ibcon#enter sib2, iclass 33, count 0 2006.231.08:17:09.54#ibcon#flushed, iclass 33, count 0 2006.231.08:17:09.54#ibcon#about to write, iclass 33, count 0 2006.231.08:17:09.54#ibcon#wrote, iclass 33, count 0 2006.231.08:17:09.54#ibcon#about to read 3, iclass 33, count 0 2006.231.08:17:09.57#ibcon#read 3, iclass 33, count 0 2006.231.08:17:09.57#ibcon#about to read 4, iclass 33, count 0 2006.231.08:17:09.57#ibcon#read 4, iclass 33, count 0 2006.231.08:17:09.57#ibcon#about to read 5, iclass 33, count 0 2006.231.08:17:09.57#ibcon#read 5, iclass 33, count 0 2006.231.08:17:09.57#ibcon#about to read 6, iclass 33, count 0 2006.231.08:17:09.57#ibcon#read 6, iclass 33, count 0 2006.231.08:17:09.57#ibcon#end of sib2, iclass 33, count 0 2006.231.08:17:09.57#ibcon#*after write, iclass 33, count 0 2006.231.08:17:09.57#ibcon#*before return 0, iclass 33, count 0 2006.231.08:17:09.57#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:17:09.57#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:17:09.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:17:09.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:17:09.57$vc4f8/valo=6,772.99 2006.231.08:17:09.57#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.08:17:09.57#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.08:17:09.57#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:09.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:17:09.57#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:17:09.57#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:17:09.57#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:17:09.57#ibcon#first serial, iclass 39, count 0 2006.231.08:17:09.57#ibcon#enter sib2, iclass 39, count 0 2006.231.08:17:09.57#ibcon#flushed, iclass 39, count 0 2006.231.08:17:09.57#ibcon#about to write, iclass 39, count 0 2006.231.08:17:09.57#ibcon#wrote, iclass 39, count 0 2006.231.08:17:09.57#ibcon#about to read 3, iclass 39, count 0 2006.231.08:17:09.59#ibcon#read 3, iclass 39, count 0 2006.231.08:17:09.59#ibcon#about to read 4, iclass 39, count 0 2006.231.08:17:09.59#ibcon#read 4, iclass 39, count 0 2006.231.08:17:09.59#ibcon#about to read 5, iclass 39, count 0 2006.231.08:17:09.59#ibcon#read 5, iclass 39, count 0 2006.231.08:17:09.59#ibcon#about to read 6, iclass 39, count 0 2006.231.08:17:09.59#ibcon#read 6, iclass 39, count 0 2006.231.08:17:09.59#ibcon#end of sib2, iclass 39, count 0 2006.231.08:17:09.59#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:17:09.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:17:09.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:17:09.59#ibcon#*before write, iclass 39, count 0 2006.231.08:17:09.59#ibcon#enter sib2, iclass 39, count 0 2006.231.08:17:09.59#ibcon#flushed, iclass 39, count 0 2006.231.08:17:09.59#ibcon#about to write, iclass 39, count 0 2006.231.08:17:09.59#ibcon#wrote, iclass 39, count 0 2006.231.08:17:09.59#ibcon#about to read 3, iclass 39, count 0 2006.231.08:17:09.63#ibcon#read 3, iclass 39, count 0 2006.231.08:17:09.63#ibcon#about to read 4, iclass 39, count 0 2006.231.08:17:09.63#ibcon#read 4, iclass 39, count 0 2006.231.08:17:09.63#ibcon#about to read 5, iclass 39, count 0 2006.231.08:17:09.63#ibcon#read 5, iclass 39, count 0 2006.231.08:17:09.63#ibcon#about to read 6, iclass 39, count 0 2006.231.08:17:09.63#ibcon#read 6, iclass 39, count 0 2006.231.08:17:09.63#ibcon#end of sib2, iclass 39, count 0 2006.231.08:17:09.63#ibcon#*after write, iclass 39, count 0 2006.231.08:17:09.63#ibcon#*before return 0, iclass 39, count 0 2006.231.08:17:09.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:17:09.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:17:09.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:17:09.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:17:09.63$vc4f8/va=6,6 2006.231.08:17:09.63#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.231.08:17:09.63#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.231.08:17:09.63#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:09.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:17:09.69#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:17:09.69#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:17:09.69#ibcon#enter wrdev, iclass 3, count 2 2006.231.08:17:09.69#ibcon#first serial, iclass 3, count 2 2006.231.08:17:09.69#ibcon#enter sib2, iclass 3, count 2 2006.231.08:17:09.69#ibcon#flushed, iclass 3, count 2 2006.231.08:17:09.69#ibcon#about to write, iclass 3, count 2 2006.231.08:17:09.69#ibcon#wrote, iclass 3, count 2 2006.231.08:17:09.69#ibcon#about to read 3, iclass 3, count 2 2006.231.08:17:09.71#ibcon#read 3, iclass 3, count 2 2006.231.08:17:09.71#ibcon#about to read 4, iclass 3, count 2 2006.231.08:17:09.71#ibcon#read 4, iclass 3, count 2 2006.231.08:17:09.71#ibcon#about to read 5, iclass 3, count 2 2006.231.08:17:09.71#ibcon#read 5, iclass 3, count 2 2006.231.08:17:09.71#ibcon#about to read 6, iclass 3, count 2 2006.231.08:17:09.71#ibcon#read 6, iclass 3, count 2 2006.231.08:17:09.71#ibcon#end of sib2, iclass 3, count 2 2006.231.08:17:09.71#ibcon#*mode == 0, iclass 3, count 2 2006.231.08:17:09.71#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.231.08:17:09.71#ibcon#[25=AT06-06\r\n] 2006.231.08:17:09.71#ibcon#*before write, iclass 3, count 2 2006.231.08:17:09.71#ibcon#enter sib2, iclass 3, count 2 2006.231.08:17:09.71#ibcon#flushed, iclass 3, count 2 2006.231.08:17:09.71#ibcon#about to write, iclass 3, count 2 2006.231.08:17:09.71#ibcon#wrote, iclass 3, count 2 2006.231.08:17:09.71#ibcon#about to read 3, iclass 3, count 2 2006.231.08:17:09.74#ibcon#read 3, iclass 3, count 2 2006.231.08:17:09.74#ibcon#about to read 4, iclass 3, count 2 2006.231.08:17:09.74#ibcon#read 4, iclass 3, count 2 2006.231.08:17:09.74#ibcon#about to read 5, iclass 3, count 2 2006.231.08:17:09.74#ibcon#read 5, iclass 3, count 2 2006.231.08:17:09.74#ibcon#about to read 6, iclass 3, count 2 2006.231.08:17:09.74#ibcon#read 6, iclass 3, count 2 2006.231.08:17:09.74#ibcon#end of sib2, iclass 3, count 2 2006.231.08:17:09.74#ibcon#*after write, iclass 3, count 2 2006.231.08:17:09.74#ibcon#*before return 0, iclass 3, count 2 2006.231.08:17:09.74#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:17:09.74#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.231.08:17:09.74#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.231.08:17:09.74#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:09.74#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:17:09.86#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:17:09.86#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:17:09.86#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:17:09.86#ibcon#first serial, iclass 3, count 0 2006.231.08:17:09.86#ibcon#enter sib2, iclass 3, count 0 2006.231.08:17:09.86#ibcon#flushed, iclass 3, count 0 2006.231.08:17:09.86#ibcon#about to write, iclass 3, count 0 2006.231.08:17:09.86#ibcon#wrote, iclass 3, count 0 2006.231.08:17:09.86#ibcon#about to read 3, iclass 3, count 0 2006.231.08:17:09.88#ibcon#read 3, iclass 3, count 0 2006.231.08:17:09.88#ibcon#about to read 4, iclass 3, count 0 2006.231.08:17:09.88#ibcon#read 4, iclass 3, count 0 2006.231.08:17:09.88#ibcon#about to read 5, iclass 3, count 0 2006.231.08:17:09.88#ibcon#read 5, iclass 3, count 0 2006.231.08:17:09.88#ibcon#about to read 6, iclass 3, count 0 2006.231.08:17:09.88#ibcon#read 6, iclass 3, count 0 2006.231.08:17:09.88#ibcon#end of sib2, iclass 3, count 0 2006.231.08:17:09.88#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:17:09.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:17:09.88#ibcon#[25=USB\r\n] 2006.231.08:17:09.88#ibcon#*before write, iclass 3, count 0 2006.231.08:17:09.88#ibcon#enter sib2, iclass 3, count 0 2006.231.08:17:09.88#ibcon#flushed, iclass 3, count 0 2006.231.08:17:09.88#ibcon#about to write, iclass 3, count 0 2006.231.08:17:09.88#ibcon#wrote, iclass 3, count 0 2006.231.08:17:09.88#ibcon#about to read 3, iclass 3, count 0 2006.231.08:17:09.91#ibcon#read 3, iclass 3, count 0 2006.231.08:17:09.91#ibcon#about to read 4, iclass 3, count 0 2006.231.08:17:09.91#ibcon#read 4, iclass 3, count 0 2006.231.08:17:09.91#ibcon#about to read 5, iclass 3, count 0 2006.231.08:17:09.91#ibcon#read 5, iclass 3, count 0 2006.231.08:17:09.91#ibcon#about to read 6, iclass 3, count 0 2006.231.08:17:09.91#ibcon#read 6, iclass 3, count 0 2006.231.08:17:09.91#ibcon#end of sib2, iclass 3, count 0 2006.231.08:17:09.91#ibcon#*after write, iclass 3, count 0 2006.231.08:17:09.91#ibcon#*before return 0, iclass 3, count 0 2006.231.08:17:09.91#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:17:09.91#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.231.08:17:09.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:17:09.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:17:09.91$vc4f8/valo=7,832.99 2006.231.08:17:09.91#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.231.08:17:09.91#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.231.08:17:09.91#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:09.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:17:09.91#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:17:09.91#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:17:09.91#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:17:09.91#ibcon#first serial, iclass 5, count 0 2006.231.08:17:09.91#ibcon#enter sib2, iclass 5, count 0 2006.231.08:17:09.91#ibcon#flushed, iclass 5, count 0 2006.231.08:17:09.91#ibcon#about to write, iclass 5, count 0 2006.231.08:17:09.91#ibcon#wrote, iclass 5, count 0 2006.231.08:17:09.91#ibcon#about to read 3, iclass 5, count 0 2006.231.08:17:09.93#ibcon#read 3, iclass 5, count 0 2006.231.08:17:09.93#ibcon#about to read 4, iclass 5, count 0 2006.231.08:17:09.93#ibcon#read 4, iclass 5, count 0 2006.231.08:17:09.93#ibcon#about to read 5, iclass 5, count 0 2006.231.08:17:09.93#ibcon#read 5, iclass 5, count 0 2006.231.08:17:09.93#ibcon#about to read 6, iclass 5, count 0 2006.231.08:17:09.93#ibcon#read 6, iclass 5, count 0 2006.231.08:17:09.93#ibcon#end of sib2, iclass 5, count 0 2006.231.08:17:09.93#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:17:09.93#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:17:09.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:17:09.93#ibcon#*before write, iclass 5, count 0 2006.231.08:17:09.93#ibcon#enter sib2, iclass 5, count 0 2006.231.08:17:09.93#ibcon#flushed, iclass 5, count 0 2006.231.08:17:09.93#ibcon#about to write, iclass 5, count 0 2006.231.08:17:09.93#ibcon#wrote, iclass 5, count 0 2006.231.08:17:09.93#ibcon#about to read 3, iclass 5, count 0 2006.231.08:17:09.97#ibcon#read 3, iclass 5, count 0 2006.231.08:17:09.97#ibcon#about to read 4, iclass 5, count 0 2006.231.08:17:09.97#ibcon#read 4, iclass 5, count 0 2006.231.08:17:09.97#ibcon#about to read 5, iclass 5, count 0 2006.231.08:17:09.97#ibcon#read 5, iclass 5, count 0 2006.231.08:17:09.97#ibcon#about to read 6, iclass 5, count 0 2006.231.08:17:09.97#ibcon#read 6, iclass 5, count 0 2006.231.08:17:09.97#ibcon#end of sib2, iclass 5, count 0 2006.231.08:17:09.97#ibcon#*after write, iclass 5, count 0 2006.231.08:17:09.97#ibcon#*before return 0, iclass 5, count 0 2006.231.08:17:09.97#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:17:09.97#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.231.08:17:09.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:17:09.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:17:09.97$vc4f8/va=7,6 2006.231.08:17:09.97#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.231.08:17:09.97#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.231.08:17:09.97#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:09.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:17:10.03#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:17:10.03#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:17:10.03#ibcon#enter wrdev, iclass 7, count 2 2006.231.08:17:10.03#ibcon#first serial, iclass 7, count 2 2006.231.08:17:10.03#ibcon#enter sib2, iclass 7, count 2 2006.231.08:17:10.03#ibcon#flushed, iclass 7, count 2 2006.231.08:17:10.03#ibcon#about to write, iclass 7, count 2 2006.231.08:17:10.03#ibcon#wrote, iclass 7, count 2 2006.231.08:17:10.03#ibcon#about to read 3, iclass 7, count 2 2006.231.08:17:10.05#ibcon#read 3, iclass 7, count 2 2006.231.08:17:10.05#ibcon#about to read 4, iclass 7, count 2 2006.231.08:17:10.05#ibcon#read 4, iclass 7, count 2 2006.231.08:17:10.05#ibcon#about to read 5, iclass 7, count 2 2006.231.08:17:10.05#ibcon#read 5, iclass 7, count 2 2006.231.08:17:10.05#ibcon#about to read 6, iclass 7, count 2 2006.231.08:17:10.05#ibcon#read 6, iclass 7, count 2 2006.231.08:17:10.05#ibcon#end of sib2, iclass 7, count 2 2006.231.08:17:10.05#ibcon#*mode == 0, iclass 7, count 2 2006.231.08:17:10.05#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.231.08:17:10.05#ibcon#[25=AT07-06\r\n] 2006.231.08:17:10.05#ibcon#*before write, iclass 7, count 2 2006.231.08:17:10.05#ibcon#enter sib2, iclass 7, count 2 2006.231.08:17:10.05#ibcon#flushed, iclass 7, count 2 2006.231.08:17:10.05#ibcon#about to write, iclass 7, count 2 2006.231.08:17:10.05#ibcon#wrote, iclass 7, count 2 2006.231.08:17:10.05#ibcon#about to read 3, iclass 7, count 2 2006.231.08:17:10.08#ibcon#read 3, iclass 7, count 2 2006.231.08:17:10.08#ibcon#about to read 4, iclass 7, count 2 2006.231.08:17:10.08#ibcon#read 4, iclass 7, count 2 2006.231.08:17:10.08#ibcon#about to read 5, iclass 7, count 2 2006.231.08:17:10.08#ibcon#read 5, iclass 7, count 2 2006.231.08:17:10.08#ibcon#about to read 6, iclass 7, count 2 2006.231.08:17:10.08#ibcon#read 6, iclass 7, count 2 2006.231.08:17:10.08#ibcon#end of sib2, iclass 7, count 2 2006.231.08:17:10.08#ibcon#*after write, iclass 7, count 2 2006.231.08:17:10.08#ibcon#*before return 0, iclass 7, count 2 2006.231.08:17:10.08#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:17:10.08#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.231.08:17:10.08#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.231.08:17:10.08#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:10.08#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:17:10.20#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:17:10.20#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:17:10.20#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:17:10.20#ibcon#first serial, iclass 7, count 0 2006.231.08:17:10.20#ibcon#enter sib2, iclass 7, count 0 2006.231.08:17:10.20#ibcon#flushed, iclass 7, count 0 2006.231.08:17:10.20#ibcon#about to write, iclass 7, count 0 2006.231.08:17:10.20#ibcon#wrote, iclass 7, count 0 2006.231.08:17:10.20#ibcon#about to read 3, iclass 7, count 0 2006.231.08:17:10.22#ibcon#read 3, iclass 7, count 0 2006.231.08:17:10.22#ibcon#about to read 4, iclass 7, count 0 2006.231.08:17:10.22#ibcon#read 4, iclass 7, count 0 2006.231.08:17:10.22#ibcon#about to read 5, iclass 7, count 0 2006.231.08:17:10.22#ibcon#read 5, iclass 7, count 0 2006.231.08:17:10.22#ibcon#about to read 6, iclass 7, count 0 2006.231.08:17:10.22#ibcon#read 6, iclass 7, count 0 2006.231.08:17:10.22#ibcon#end of sib2, iclass 7, count 0 2006.231.08:17:10.22#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:17:10.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:17:10.22#ibcon#[25=USB\r\n] 2006.231.08:17:10.22#ibcon#*before write, iclass 7, count 0 2006.231.08:17:10.22#ibcon#enter sib2, iclass 7, count 0 2006.231.08:17:10.22#ibcon#flushed, iclass 7, count 0 2006.231.08:17:10.22#ibcon#about to write, iclass 7, count 0 2006.231.08:17:10.22#ibcon#wrote, iclass 7, count 0 2006.231.08:17:10.22#ibcon#about to read 3, iclass 7, count 0 2006.231.08:17:10.25#ibcon#read 3, iclass 7, count 0 2006.231.08:17:10.25#ibcon#about to read 4, iclass 7, count 0 2006.231.08:17:10.25#ibcon#read 4, iclass 7, count 0 2006.231.08:17:10.25#ibcon#about to read 5, iclass 7, count 0 2006.231.08:17:10.25#ibcon#read 5, iclass 7, count 0 2006.231.08:17:10.25#ibcon#about to read 6, iclass 7, count 0 2006.231.08:17:10.25#ibcon#read 6, iclass 7, count 0 2006.231.08:17:10.25#ibcon#end of sib2, iclass 7, count 0 2006.231.08:17:10.25#ibcon#*after write, iclass 7, count 0 2006.231.08:17:10.25#ibcon#*before return 0, iclass 7, count 0 2006.231.08:17:10.25#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:17:10.25#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.231.08:17:10.25#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:17:10.25#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:17:10.25$vc4f8/valo=8,852.99 2006.231.08:17:10.25#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.231.08:17:10.25#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.231.08:17:10.25#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:10.25#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:17:10.25#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:17:10.25#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:17:10.25#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:17:10.25#ibcon#first serial, iclass 11, count 0 2006.231.08:17:10.25#ibcon#enter sib2, iclass 11, count 0 2006.231.08:17:10.25#ibcon#flushed, iclass 11, count 0 2006.231.08:17:10.25#ibcon#about to write, iclass 11, count 0 2006.231.08:17:10.25#ibcon#wrote, iclass 11, count 0 2006.231.08:17:10.25#ibcon#about to read 3, iclass 11, count 0 2006.231.08:17:10.28#ibcon#read 3, iclass 11, count 0 2006.231.08:17:10.28#ibcon#about to read 4, iclass 11, count 0 2006.231.08:17:10.28#ibcon#read 4, iclass 11, count 0 2006.231.08:17:10.28#ibcon#about to read 5, iclass 11, count 0 2006.231.08:17:10.28#ibcon#read 5, iclass 11, count 0 2006.231.08:17:10.28#ibcon#about to read 6, iclass 11, count 0 2006.231.08:17:10.28#ibcon#read 6, iclass 11, count 0 2006.231.08:17:10.28#ibcon#end of sib2, iclass 11, count 0 2006.231.08:17:10.28#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:17:10.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:17:10.28#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:17:10.28#ibcon#*before write, iclass 11, count 0 2006.231.08:17:10.28#ibcon#enter sib2, iclass 11, count 0 2006.231.08:17:10.28#ibcon#flushed, iclass 11, count 0 2006.231.08:17:10.28#ibcon#about to write, iclass 11, count 0 2006.231.08:17:10.28#ibcon#wrote, iclass 11, count 0 2006.231.08:17:10.28#ibcon#about to read 3, iclass 11, count 0 2006.231.08:17:10.32#ibcon#read 3, iclass 11, count 0 2006.231.08:17:10.32#ibcon#about to read 4, iclass 11, count 0 2006.231.08:17:10.32#ibcon#read 4, iclass 11, count 0 2006.231.08:17:10.32#ibcon#about to read 5, iclass 11, count 0 2006.231.08:17:10.32#ibcon#read 5, iclass 11, count 0 2006.231.08:17:10.32#ibcon#about to read 6, iclass 11, count 0 2006.231.08:17:10.32#ibcon#read 6, iclass 11, count 0 2006.231.08:17:10.32#ibcon#end of sib2, iclass 11, count 0 2006.231.08:17:10.32#ibcon#*after write, iclass 11, count 0 2006.231.08:17:10.32#ibcon#*before return 0, iclass 11, count 0 2006.231.08:17:10.32#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:17:10.32#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.231.08:17:10.32#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:17:10.32#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:17:10.32$vc4f8/va=8,6 2006.231.08:17:10.32#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.231.08:17:10.32#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.231.08:17:10.32#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:10.32#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:17:10.37#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:17:10.37#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:17:10.37#ibcon#enter wrdev, iclass 13, count 2 2006.231.08:17:10.37#ibcon#first serial, iclass 13, count 2 2006.231.08:17:10.37#ibcon#enter sib2, iclass 13, count 2 2006.231.08:17:10.37#ibcon#flushed, iclass 13, count 2 2006.231.08:17:10.37#ibcon#about to write, iclass 13, count 2 2006.231.08:17:10.37#ibcon#wrote, iclass 13, count 2 2006.231.08:17:10.37#ibcon#about to read 3, iclass 13, count 2 2006.231.08:17:10.39#ibcon#read 3, iclass 13, count 2 2006.231.08:17:10.39#ibcon#about to read 4, iclass 13, count 2 2006.231.08:17:10.39#ibcon#read 4, iclass 13, count 2 2006.231.08:17:10.39#ibcon#about to read 5, iclass 13, count 2 2006.231.08:17:10.39#ibcon#read 5, iclass 13, count 2 2006.231.08:17:10.39#ibcon#about to read 6, iclass 13, count 2 2006.231.08:17:10.39#ibcon#read 6, iclass 13, count 2 2006.231.08:17:10.39#ibcon#end of sib2, iclass 13, count 2 2006.231.08:17:10.39#ibcon#*mode == 0, iclass 13, count 2 2006.231.08:17:10.39#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.231.08:17:10.39#ibcon#[25=AT08-06\r\n] 2006.231.08:17:10.39#ibcon#*before write, iclass 13, count 2 2006.231.08:17:10.39#ibcon#enter sib2, iclass 13, count 2 2006.231.08:17:10.39#ibcon#flushed, iclass 13, count 2 2006.231.08:17:10.39#ibcon#about to write, iclass 13, count 2 2006.231.08:17:10.39#ibcon#wrote, iclass 13, count 2 2006.231.08:17:10.39#ibcon#about to read 3, iclass 13, count 2 2006.231.08:17:10.42#ibcon#read 3, iclass 13, count 2 2006.231.08:17:10.42#ibcon#about to read 4, iclass 13, count 2 2006.231.08:17:10.42#ibcon#read 4, iclass 13, count 2 2006.231.08:17:10.42#ibcon#about to read 5, iclass 13, count 2 2006.231.08:17:10.42#ibcon#read 5, iclass 13, count 2 2006.231.08:17:10.42#ibcon#about to read 6, iclass 13, count 2 2006.231.08:17:10.42#ibcon#read 6, iclass 13, count 2 2006.231.08:17:10.42#ibcon#end of sib2, iclass 13, count 2 2006.231.08:17:10.42#ibcon#*after write, iclass 13, count 2 2006.231.08:17:10.42#ibcon#*before return 0, iclass 13, count 2 2006.231.08:17:10.42#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:17:10.42#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.231.08:17:10.42#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.231.08:17:10.42#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:10.42#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:17:10.54#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:17:10.54#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:17:10.54#ibcon#enter wrdev, iclass 13, count 0 2006.231.08:17:10.54#ibcon#first serial, iclass 13, count 0 2006.231.08:17:10.54#ibcon#enter sib2, iclass 13, count 0 2006.231.08:17:10.54#ibcon#flushed, iclass 13, count 0 2006.231.08:17:10.54#ibcon#about to write, iclass 13, count 0 2006.231.08:17:10.54#ibcon#wrote, iclass 13, count 0 2006.231.08:17:10.54#ibcon#about to read 3, iclass 13, count 0 2006.231.08:17:10.56#ibcon#read 3, iclass 13, count 0 2006.231.08:17:10.56#ibcon#about to read 4, iclass 13, count 0 2006.231.08:17:10.56#ibcon#read 4, iclass 13, count 0 2006.231.08:17:10.56#ibcon#about to read 5, iclass 13, count 0 2006.231.08:17:10.56#ibcon#read 5, iclass 13, count 0 2006.231.08:17:10.56#ibcon#about to read 6, iclass 13, count 0 2006.231.08:17:10.56#ibcon#read 6, iclass 13, count 0 2006.231.08:17:10.56#ibcon#end of sib2, iclass 13, count 0 2006.231.08:17:10.56#ibcon#*mode == 0, iclass 13, count 0 2006.231.08:17:10.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.08:17:10.56#ibcon#[25=USB\r\n] 2006.231.08:17:10.56#ibcon#*before write, iclass 13, count 0 2006.231.08:17:10.56#ibcon#enter sib2, iclass 13, count 0 2006.231.08:17:10.56#ibcon#flushed, iclass 13, count 0 2006.231.08:17:10.56#ibcon#about to write, iclass 13, count 0 2006.231.08:17:10.56#ibcon#wrote, iclass 13, count 0 2006.231.08:17:10.56#ibcon#about to read 3, iclass 13, count 0 2006.231.08:17:10.59#ibcon#read 3, iclass 13, count 0 2006.231.08:17:10.59#ibcon#about to read 4, iclass 13, count 0 2006.231.08:17:10.59#ibcon#read 4, iclass 13, count 0 2006.231.08:17:10.59#ibcon#about to read 5, iclass 13, count 0 2006.231.08:17:10.59#ibcon#read 5, iclass 13, count 0 2006.231.08:17:10.59#ibcon#about to read 6, iclass 13, count 0 2006.231.08:17:10.59#ibcon#read 6, iclass 13, count 0 2006.231.08:17:10.59#ibcon#end of sib2, iclass 13, count 0 2006.231.08:17:10.59#ibcon#*after write, iclass 13, count 0 2006.231.08:17:10.59#ibcon#*before return 0, iclass 13, count 0 2006.231.08:17:10.59#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:17:10.59#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.231.08:17:10.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.08:17:10.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.08:17:10.59$vc4f8/vblo=1,632.99 2006.231.08:17:10.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.231.08:17:10.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.231.08:17:10.59#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:10.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:17:10.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:17:10.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:17:10.59#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:17:10.59#ibcon#first serial, iclass 15, count 0 2006.231.08:17:10.59#ibcon#enter sib2, iclass 15, count 0 2006.231.08:17:10.59#ibcon#flushed, iclass 15, count 0 2006.231.08:17:10.59#ibcon#about to write, iclass 15, count 0 2006.231.08:17:10.59#ibcon#wrote, iclass 15, count 0 2006.231.08:17:10.59#ibcon#about to read 3, iclass 15, count 0 2006.231.08:17:10.61#ibcon#read 3, iclass 15, count 0 2006.231.08:17:10.61#ibcon#about to read 4, iclass 15, count 0 2006.231.08:17:10.61#ibcon#read 4, iclass 15, count 0 2006.231.08:17:10.61#ibcon#about to read 5, iclass 15, count 0 2006.231.08:17:10.61#ibcon#read 5, iclass 15, count 0 2006.231.08:17:10.61#ibcon#about to read 6, iclass 15, count 0 2006.231.08:17:10.61#ibcon#read 6, iclass 15, count 0 2006.231.08:17:10.61#ibcon#end of sib2, iclass 15, count 0 2006.231.08:17:10.61#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:17:10.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:17:10.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:17:10.61#ibcon#*before write, iclass 15, count 0 2006.231.08:17:10.61#ibcon#enter sib2, iclass 15, count 0 2006.231.08:17:10.61#ibcon#flushed, iclass 15, count 0 2006.231.08:17:10.61#ibcon#about to write, iclass 15, count 0 2006.231.08:17:10.61#ibcon#wrote, iclass 15, count 0 2006.231.08:17:10.61#ibcon#about to read 3, iclass 15, count 0 2006.231.08:17:10.65#ibcon#read 3, iclass 15, count 0 2006.231.08:17:10.65#ibcon#about to read 4, iclass 15, count 0 2006.231.08:17:10.65#ibcon#read 4, iclass 15, count 0 2006.231.08:17:10.65#ibcon#about to read 5, iclass 15, count 0 2006.231.08:17:10.65#ibcon#read 5, iclass 15, count 0 2006.231.08:17:10.65#ibcon#about to read 6, iclass 15, count 0 2006.231.08:17:10.65#ibcon#read 6, iclass 15, count 0 2006.231.08:17:10.65#ibcon#end of sib2, iclass 15, count 0 2006.231.08:17:10.65#ibcon#*after write, iclass 15, count 0 2006.231.08:17:10.65#ibcon#*before return 0, iclass 15, count 0 2006.231.08:17:10.65#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:17:10.65#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.231.08:17:10.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:17:10.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:17:10.65$vc4f8/vb=1,4 2006.231.08:17:10.65#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.231.08:17:10.65#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.231.08:17:10.65#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:10.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:17:10.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:17:10.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:17:10.65#ibcon#enter wrdev, iclass 17, count 2 2006.231.08:17:10.65#ibcon#first serial, iclass 17, count 2 2006.231.08:17:10.65#ibcon#enter sib2, iclass 17, count 2 2006.231.08:17:10.65#ibcon#flushed, iclass 17, count 2 2006.231.08:17:10.65#ibcon#about to write, iclass 17, count 2 2006.231.08:17:10.65#ibcon#wrote, iclass 17, count 2 2006.231.08:17:10.65#ibcon#about to read 3, iclass 17, count 2 2006.231.08:17:10.67#ibcon#read 3, iclass 17, count 2 2006.231.08:17:10.67#ibcon#about to read 4, iclass 17, count 2 2006.231.08:17:10.67#ibcon#read 4, iclass 17, count 2 2006.231.08:17:10.67#ibcon#about to read 5, iclass 17, count 2 2006.231.08:17:10.67#ibcon#read 5, iclass 17, count 2 2006.231.08:17:10.67#ibcon#about to read 6, iclass 17, count 2 2006.231.08:17:10.67#ibcon#read 6, iclass 17, count 2 2006.231.08:17:10.67#ibcon#end of sib2, iclass 17, count 2 2006.231.08:17:10.67#ibcon#*mode == 0, iclass 17, count 2 2006.231.08:17:10.67#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.231.08:17:10.67#ibcon#[27=AT01-04\r\n] 2006.231.08:17:10.67#ibcon#*before write, iclass 17, count 2 2006.231.08:17:10.67#ibcon#enter sib2, iclass 17, count 2 2006.231.08:17:10.67#ibcon#flushed, iclass 17, count 2 2006.231.08:17:10.67#ibcon#about to write, iclass 17, count 2 2006.231.08:17:10.67#ibcon#wrote, iclass 17, count 2 2006.231.08:17:10.67#ibcon#about to read 3, iclass 17, count 2 2006.231.08:17:10.70#ibcon#read 3, iclass 17, count 2 2006.231.08:17:10.70#ibcon#about to read 4, iclass 17, count 2 2006.231.08:17:10.70#ibcon#read 4, iclass 17, count 2 2006.231.08:17:10.70#ibcon#about to read 5, iclass 17, count 2 2006.231.08:17:10.70#ibcon#read 5, iclass 17, count 2 2006.231.08:17:10.70#ibcon#about to read 6, iclass 17, count 2 2006.231.08:17:10.70#ibcon#read 6, iclass 17, count 2 2006.231.08:17:10.70#ibcon#end of sib2, iclass 17, count 2 2006.231.08:17:10.70#ibcon#*after write, iclass 17, count 2 2006.231.08:17:10.70#ibcon#*before return 0, iclass 17, count 2 2006.231.08:17:10.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:17:10.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.231.08:17:10.70#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.231.08:17:10.70#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:10.70#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:17:10.82#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:17:10.82#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:17:10.82#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:17:10.82#ibcon#first serial, iclass 17, count 0 2006.231.08:17:10.82#ibcon#enter sib2, iclass 17, count 0 2006.231.08:17:10.82#ibcon#flushed, iclass 17, count 0 2006.231.08:17:10.82#ibcon#about to write, iclass 17, count 0 2006.231.08:17:10.82#ibcon#wrote, iclass 17, count 0 2006.231.08:17:10.82#ibcon#about to read 3, iclass 17, count 0 2006.231.08:17:10.84#ibcon#read 3, iclass 17, count 0 2006.231.08:17:10.84#ibcon#about to read 4, iclass 17, count 0 2006.231.08:17:10.84#ibcon#read 4, iclass 17, count 0 2006.231.08:17:10.84#ibcon#about to read 5, iclass 17, count 0 2006.231.08:17:10.84#ibcon#read 5, iclass 17, count 0 2006.231.08:17:10.84#ibcon#about to read 6, iclass 17, count 0 2006.231.08:17:10.84#ibcon#read 6, iclass 17, count 0 2006.231.08:17:10.84#ibcon#end of sib2, iclass 17, count 0 2006.231.08:17:10.84#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:17:10.84#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:17:10.84#ibcon#[27=USB\r\n] 2006.231.08:17:10.84#ibcon#*before write, iclass 17, count 0 2006.231.08:17:10.84#ibcon#enter sib2, iclass 17, count 0 2006.231.08:17:10.84#ibcon#flushed, iclass 17, count 0 2006.231.08:17:10.84#ibcon#about to write, iclass 17, count 0 2006.231.08:17:10.84#ibcon#wrote, iclass 17, count 0 2006.231.08:17:10.84#ibcon#about to read 3, iclass 17, count 0 2006.231.08:17:10.87#ibcon#read 3, iclass 17, count 0 2006.231.08:17:10.87#ibcon#about to read 4, iclass 17, count 0 2006.231.08:17:10.87#ibcon#read 4, iclass 17, count 0 2006.231.08:17:10.87#ibcon#about to read 5, iclass 17, count 0 2006.231.08:17:10.87#ibcon#read 5, iclass 17, count 0 2006.231.08:17:10.87#ibcon#about to read 6, iclass 17, count 0 2006.231.08:17:10.87#ibcon#read 6, iclass 17, count 0 2006.231.08:17:10.87#ibcon#end of sib2, iclass 17, count 0 2006.231.08:17:10.87#ibcon#*after write, iclass 17, count 0 2006.231.08:17:10.87#ibcon#*before return 0, iclass 17, count 0 2006.231.08:17:10.87#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:17:10.87#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.231.08:17:10.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:17:10.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:17:10.87$vc4f8/vblo=2,640.99 2006.231.08:17:10.87#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.08:17:10.87#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.08:17:10.87#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:10.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:17:10.87#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:17:10.87#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:17:10.87#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:17:10.87#ibcon#first serial, iclass 19, count 0 2006.231.08:17:10.87#ibcon#enter sib2, iclass 19, count 0 2006.231.08:17:10.87#ibcon#flushed, iclass 19, count 0 2006.231.08:17:10.87#ibcon#about to write, iclass 19, count 0 2006.231.08:17:10.87#ibcon#wrote, iclass 19, count 0 2006.231.08:17:10.87#ibcon#about to read 3, iclass 19, count 0 2006.231.08:17:10.89#ibcon#read 3, iclass 19, count 0 2006.231.08:17:10.89#ibcon#about to read 4, iclass 19, count 0 2006.231.08:17:10.89#ibcon#read 4, iclass 19, count 0 2006.231.08:17:10.89#ibcon#about to read 5, iclass 19, count 0 2006.231.08:17:10.89#ibcon#read 5, iclass 19, count 0 2006.231.08:17:10.89#ibcon#about to read 6, iclass 19, count 0 2006.231.08:17:10.89#ibcon#read 6, iclass 19, count 0 2006.231.08:17:10.89#ibcon#end of sib2, iclass 19, count 0 2006.231.08:17:10.89#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:17:10.89#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:17:10.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:17:10.89#ibcon#*before write, iclass 19, count 0 2006.231.08:17:10.89#ibcon#enter sib2, iclass 19, count 0 2006.231.08:17:10.89#ibcon#flushed, iclass 19, count 0 2006.231.08:17:10.89#ibcon#about to write, iclass 19, count 0 2006.231.08:17:10.89#ibcon#wrote, iclass 19, count 0 2006.231.08:17:10.89#ibcon#about to read 3, iclass 19, count 0 2006.231.08:17:10.93#ibcon#read 3, iclass 19, count 0 2006.231.08:17:10.93#ibcon#about to read 4, iclass 19, count 0 2006.231.08:17:10.93#ibcon#read 4, iclass 19, count 0 2006.231.08:17:10.93#ibcon#about to read 5, iclass 19, count 0 2006.231.08:17:10.93#ibcon#read 5, iclass 19, count 0 2006.231.08:17:10.93#ibcon#about to read 6, iclass 19, count 0 2006.231.08:17:10.93#ibcon#read 6, iclass 19, count 0 2006.231.08:17:10.93#ibcon#end of sib2, iclass 19, count 0 2006.231.08:17:10.93#ibcon#*after write, iclass 19, count 0 2006.231.08:17:10.93#ibcon#*before return 0, iclass 19, count 0 2006.231.08:17:10.93#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:17:10.93#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:17:10.93#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:17:10.93#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:17:10.93$vc4f8/vb=2,4 2006.231.08:17:10.93#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.231.08:17:10.93#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.231.08:17:10.93#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:10.93#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:17:10.99#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:17:10.99#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:17:10.99#ibcon#enter wrdev, iclass 21, count 2 2006.231.08:17:10.99#ibcon#first serial, iclass 21, count 2 2006.231.08:17:10.99#ibcon#enter sib2, iclass 21, count 2 2006.231.08:17:10.99#ibcon#flushed, iclass 21, count 2 2006.231.08:17:10.99#ibcon#about to write, iclass 21, count 2 2006.231.08:17:10.99#ibcon#wrote, iclass 21, count 2 2006.231.08:17:10.99#ibcon#about to read 3, iclass 21, count 2 2006.231.08:17:11.01#ibcon#read 3, iclass 21, count 2 2006.231.08:17:11.01#ibcon#about to read 4, iclass 21, count 2 2006.231.08:17:11.01#ibcon#read 4, iclass 21, count 2 2006.231.08:17:11.01#ibcon#about to read 5, iclass 21, count 2 2006.231.08:17:11.01#ibcon#read 5, iclass 21, count 2 2006.231.08:17:11.01#ibcon#about to read 6, iclass 21, count 2 2006.231.08:17:11.01#ibcon#read 6, iclass 21, count 2 2006.231.08:17:11.01#ibcon#end of sib2, iclass 21, count 2 2006.231.08:17:11.01#ibcon#*mode == 0, iclass 21, count 2 2006.231.08:17:11.01#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.231.08:17:11.01#ibcon#[27=AT02-04\r\n] 2006.231.08:17:11.01#ibcon#*before write, iclass 21, count 2 2006.231.08:17:11.01#ibcon#enter sib2, iclass 21, count 2 2006.231.08:17:11.01#ibcon#flushed, iclass 21, count 2 2006.231.08:17:11.01#ibcon#about to write, iclass 21, count 2 2006.231.08:17:11.01#ibcon#wrote, iclass 21, count 2 2006.231.08:17:11.01#ibcon#about to read 3, iclass 21, count 2 2006.231.08:17:11.04#ibcon#read 3, iclass 21, count 2 2006.231.08:17:11.04#ibcon#about to read 4, iclass 21, count 2 2006.231.08:17:11.04#ibcon#read 4, iclass 21, count 2 2006.231.08:17:11.04#ibcon#about to read 5, iclass 21, count 2 2006.231.08:17:11.04#ibcon#read 5, iclass 21, count 2 2006.231.08:17:11.04#ibcon#about to read 6, iclass 21, count 2 2006.231.08:17:11.04#ibcon#read 6, iclass 21, count 2 2006.231.08:17:11.04#ibcon#end of sib2, iclass 21, count 2 2006.231.08:17:11.04#ibcon#*after write, iclass 21, count 2 2006.231.08:17:11.04#ibcon#*before return 0, iclass 21, count 2 2006.231.08:17:11.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:17:11.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:17:11.04#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.231.08:17:11.04#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:11.04#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:17:11.16#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:17:11.16#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:17:11.16#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:17:11.16#ibcon#first serial, iclass 21, count 0 2006.231.08:17:11.16#ibcon#enter sib2, iclass 21, count 0 2006.231.08:17:11.16#ibcon#flushed, iclass 21, count 0 2006.231.08:17:11.16#ibcon#about to write, iclass 21, count 0 2006.231.08:17:11.16#ibcon#wrote, iclass 21, count 0 2006.231.08:17:11.16#ibcon#about to read 3, iclass 21, count 0 2006.231.08:17:11.18#ibcon#read 3, iclass 21, count 0 2006.231.08:17:11.18#ibcon#about to read 4, iclass 21, count 0 2006.231.08:17:11.18#ibcon#read 4, iclass 21, count 0 2006.231.08:17:11.18#ibcon#about to read 5, iclass 21, count 0 2006.231.08:17:11.18#ibcon#read 5, iclass 21, count 0 2006.231.08:17:11.18#ibcon#about to read 6, iclass 21, count 0 2006.231.08:17:11.18#ibcon#read 6, iclass 21, count 0 2006.231.08:17:11.18#ibcon#end of sib2, iclass 21, count 0 2006.231.08:17:11.18#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:17:11.18#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:17:11.18#ibcon#[27=USB\r\n] 2006.231.08:17:11.18#ibcon#*before write, iclass 21, count 0 2006.231.08:17:11.18#ibcon#enter sib2, iclass 21, count 0 2006.231.08:17:11.18#ibcon#flushed, iclass 21, count 0 2006.231.08:17:11.18#ibcon#about to write, iclass 21, count 0 2006.231.08:17:11.18#ibcon#wrote, iclass 21, count 0 2006.231.08:17:11.18#ibcon#about to read 3, iclass 21, count 0 2006.231.08:17:11.21#ibcon#read 3, iclass 21, count 0 2006.231.08:17:11.21#ibcon#about to read 4, iclass 21, count 0 2006.231.08:17:11.21#ibcon#read 4, iclass 21, count 0 2006.231.08:17:11.21#ibcon#about to read 5, iclass 21, count 0 2006.231.08:17:11.21#ibcon#read 5, iclass 21, count 0 2006.231.08:17:11.21#ibcon#about to read 6, iclass 21, count 0 2006.231.08:17:11.21#ibcon#read 6, iclass 21, count 0 2006.231.08:17:11.21#ibcon#end of sib2, iclass 21, count 0 2006.231.08:17:11.21#ibcon#*after write, iclass 21, count 0 2006.231.08:17:11.21#ibcon#*before return 0, iclass 21, count 0 2006.231.08:17:11.21#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:17:11.21#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:17:11.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:17:11.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:17:11.21$vc4f8/vblo=3,656.99 2006.231.08:17:11.21#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.231.08:17:11.21#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.231.08:17:11.21#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:11.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:17:11.21#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:17:11.21#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:17:11.21#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:17:11.21#ibcon#first serial, iclass 23, count 0 2006.231.08:17:11.21#ibcon#enter sib2, iclass 23, count 0 2006.231.08:17:11.21#ibcon#flushed, iclass 23, count 0 2006.231.08:17:11.21#ibcon#about to write, iclass 23, count 0 2006.231.08:17:11.21#ibcon#wrote, iclass 23, count 0 2006.231.08:17:11.21#ibcon#about to read 3, iclass 23, count 0 2006.231.08:17:11.23#ibcon#read 3, iclass 23, count 0 2006.231.08:17:11.23#ibcon#about to read 4, iclass 23, count 0 2006.231.08:17:11.23#ibcon#read 4, iclass 23, count 0 2006.231.08:17:11.23#ibcon#about to read 5, iclass 23, count 0 2006.231.08:17:11.23#ibcon#read 5, iclass 23, count 0 2006.231.08:17:11.23#ibcon#about to read 6, iclass 23, count 0 2006.231.08:17:11.23#ibcon#read 6, iclass 23, count 0 2006.231.08:17:11.23#ibcon#end of sib2, iclass 23, count 0 2006.231.08:17:11.23#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:17:11.23#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:17:11.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:17:11.23#ibcon#*before write, iclass 23, count 0 2006.231.08:17:11.23#ibcon#enter sib2, iclass 23, count 0 2006.231.08:17:11.23#ibcon#flushed, iclass 23, count 0 2006.231.08:17:11.23#ibcon#about to write, iclass 23, count 0 2006.231.08:17:11.23#ibcon#wrote, iclass 23, count 0 2006.231.08:17:11.23#ibcon#about to read 3, iclass 23, count 0 2006.231.08:17:11.27#ibcon#read 3, iclass 23, count 0 2006.231.08:17:11.27#ibcon#about to read 4, iclass 23, count 0 2006.231.08:17:11.27#ibcon#read 4, iclass 23, count 0 2006.231.08:17:11.27#ibcon#about to read 5, iclass 23, count 0 2006.231.08:17:11.27#ibcon#read 5, iclass 23, count 0 2006.231.08:17:11.27#ibcon#about to read 6, iclass 23, count 0 2006.231.08:17:11.27#ibcon#read 6, iclass 23, count 0 2006.231.08:17:11.27#ibcon#end of sib2, iclass 23, count 0 2006.231.08:17:11.27#ibcon#*after write, iclass 23, count 0 2006.231.08:17:11.27#ibcon#*before return 0, iclass 23, count 0 2006.231.08:17:11.27#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:17:11.27#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.231.08:17:11.27#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:17:11.27#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:17:11.27$vc4f8/vb=3,4 2006.231.08:17:11.27#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.231.08:17:11.27#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.231.08:17:11.27#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:11.27#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:17:11.33#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:17:11.33#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:17:11.33#ibcon#enter wrdev, iclass 25, count 2 2006.231.08:17:11.33#ibcon#first serial, iclass 25, count 2 2006.231.08:17:11.33#ibcon#enter sib2, iclass 25, count 2 2006.231.08:17:11.33#ibcon#flushed, iclass 25, count 2 2006.231.08:17:11.33#ibcon#about to write, iclass 25, count 2 2006.231.08:17:11.33#ibcon#wrote, iclass 25, count 2 2006.231.08:17:11.33#ibcon#about to read 3, iclass 25, count 2 2006.231.08:17:11.35#ibcon#read 3, iclass 25, count 2 2006.231.08:17:11.35#ibcon#about to read 4, iclass 25, count 2 2006.231.08:17:11.35#ibcon#read 4, iclass 25, count 2 2006.231.08:17:11.35#ibcon#about to read 5, iclass 25, count 2 2006.231.08:17:11.35#ibcon#read 5, iclass 25, count 2 2006.231.08:17:11.35#ibcon#about to read 6, iclass 25, count 2 2006.231.08:17:11.35#ibcon#read 6, iclass 25, count 2 2006.231.08:17:11.35#ibcon#end of sib2, iclass 25, count 2 2006.231.08:17:11.35#ibcon#*mode == 0, iclass 25, count 2 2006.231.08:17:11.35#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.231.08:17:11.35#ibcon#[27=AT03-04\r\n] 2006.231.08:17:11.35#ibcon#*before write, iclass 25, count 2 2006.231.08:17:11.35#ibcon#enter sib2, iclass 25, count 2 2006.231.08:17:11.35#ibcon#flushed, iclass 25, count 2 2006.231.08:17:11.35#ibcon#about to write, iclass 25, count 2 2006.231.08:17:11.35#ibcon#wrote, iclass 25, count 2 2006.231.08:17:11.35#ibcon#about to read 3, iclass 25, count 2 2006.231.08:17:11.38#ibcon#read 3, iclass 25, count 2 2006.231.08:17:11.38#ibcon#about to read 4, iclass 25, count 2 2006.231.08:17:11.38#ibcon#read 4, iclass 25, count 2 2006.231.08:17:11.38#ibcon#about to read 5, iclass 25, count 2 2006.231.08:17:11.38#ibcon#read 5, iclass 25, count 2 2006.231.08:17:11.38#ibcon#about to read 6, iclass 25, count 2 2006.231.08:17:11.38#ibcon#read 6, iclass 25, count 2 2006.231.08:17:11.38#ibcon#end of sib2, iclass 25, count 2 2006.231.08:17:11.38#ibcon#*after write, iclass 25, count 2 2006.231.08:17:11.38#ibcon#*before return 0, iclass 25, count 2 2006.231.08:17:11.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:17:11.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.231.08:17:11.38#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.231.08:17:11.38#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:11.38#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:17:11.50#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:17:11.50#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:17:11.50#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:17:11.50#ibcon#first serial, iclass 25, count 0 2006.231.08:17:11.50#ibcon#enter sib2, iclass 25, count 0 2006.231.08:17:11.50#ibcon#flushed, iclass 25, count 0 2006.231.08:17:11.50#ibcon#about to write, iclass 25, count 0 2006.231.08:17:11.50#ibcon#wrote, iclass 25, count 0 2006.231.08:17:11.50#ibcon#about to read 3, iclass 25, count 0 2006.231.08:17:11.52#ibcon#read 3, iclass 25, count 0 2006.231.08:17:11.52#ibcon#about to read 4, iclass 25, count 0 2006.231.08:17:11.52#ibcon#read 4, iclass 25, count 0 2006.231.08:17:11.52#ibcon#about to read 5, iclass 25, count 0 2006.231.08:17:11.52#ibcon#read 5, iclass 25, count 0 2006.231.08:17:11.52#ibcon#about to read 6, iclass 25, count 0 2006.231.08:17:11.52#ibcon#read 6, iclass 25, count 0 2006.231.08:17:11.52#ibcon#end of sib2, iclass 25, count 0 2006.231.08:17:11.52#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:17:11.52#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:17:11.52#ibcon#[27=USB\r\n] 2006.231.08:17:11.52#ibcon#*before write, iclass 25, count 0 2006.231.08:17:11.52#ibcon#enter sib2, iclass 25, count 0 2006.231.08:17:11.52#ibcon#flushed, iclass 25, count 0 2006.231.08:17:11.52#ibcon#about to write, iclass 25, count 0 2006.231.08:17:11.52#ibcon#wrote, iclass 25, count 0 2006.231.08:17:11.52#ibcon#about to read 3, iclass 25, count 0 2006.231.08:17:11.55#ibcon#read 3, iclass 25, count 0 2006.231.08:17:11.55#ibcon#about to read 4, iclass 25, count 0 2006.231.08:17:11.55#ibcon#read 4, iclass 25, count 0 2006.231.08:17:11.55#ibcon#about to read 5, iclass 25, count 0 2006.231.08:17:11.55#ibcon#read 5, iclass 25, count 0 2006.231.08:17:11.55#ibcon#about to read 6, iclass 25, count 0 2006.231.08:17:11.55#ibcon#read 6, iclass 25, count 0 2006.231.08:17:11.55#ibcon#end of sib2, iclass 25, count 0 2006.231.08:17:11.55#ibcon#*after write, iclass 25, count 0 2006.231.08:17:11.55#ibcon#*before return 0, iclass 25, count 0 2006.231.08:17:11.55#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:17:11.55#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.231.08:17:11.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:17:11.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:17:11.55$vc4f8/vblo=4,712.99 2006.231.08:17:11.55#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.231.08:17:11.55#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.231.08:17:11.55#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:11.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:17:11.55#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:17:11.55#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:17:11.55#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:17:11.55#ibcon#first serial, iclass 27, count 0 2006.231.08:17:11.55#ibcon#enter sib2, iclass 27, count 0 2006.231.08:17:11.55#ibcon#flushed, iclass 27, count 0 2006.231.08:17:11.55#ibcon#about to write, iclass 27, count 0 2006.231.08:17:11.55#ibcon#wrote, iclass 27, count 0 2006.231.08:17:11.55#ibcon#about to read 3, iclass 27, count 0 2006.231.08:17:11.57#ibcon#read 3, iclass 27, count 0 2006.231.08:17:11.57#ibcon#about to read 4, iclass 27, count 0 2006.231.08:17:11.57#ibcon#read 4, iclass 27, count 0 2006.231.08:17:11.57#ibcon#about to read 5, iclass 27, count 0 2006.231.08:17:11.57#ibcon#read 5, iclass 27, count 0 2006.231.08:17:11.57#ibcon#about to read 6, iclass 27, count 0 2006.231.08:17:11.57#ibcon#read 6, iclass 27, count 0 2006.231.08:17:11.57#ibcon#end of sib2, iclass 27, count 0 2006.231.08:17:11.57#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:17:11.57#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:17:11.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:17:11.57#ibcon#*before write, iclass 27, count 0 2006.231.08:17:11.57#ibcon#enter sib2, iclass 27, count 0 2006.231.08:17:11.57#ibcon#flushed, iclass 27, count 0 2006.231.08:17:11.57#ibcon#about to write, iclass 27, count 0 2006.231.08:17:11.57#ibcon#wrote, iclass 27, count 0 2006.231.08:17:11.57#ibcon#about to read 3, iclass 27, count 0 2006.231.08:17:11.61#ibcon#read 3, iclass 27, count 0 2006.231.08:17:11.61#ibcon#about to read 4, iclass 27, count 0 2006.231.08:17:11.61#ibcon#read 4, iclass 27, count 0 2006.231.08:17:11.61#ibcon#about to read 5, iclass 27, count 0 2006.231.08:17:11.61#ibcon#read 5, iclass 27, count 0 2006.231.08:17:11.61#ibcon#about to read 6, iclass 27, count 0 2006.231.08:17:11.61#ibcon#read 6, iclass 27, count 0 2006.231.08:17:11.61#ibcon#end of sib2, iclass 27, count 0 2006.231.08:17:11.61#ibcon#*after write, iclass 27, count 0 2006.231.08:17:11.61#ibcon#*before return 0, iclass 27, count 0 2006.231.08:17:11.61#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:17:11.61#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.231.08:17:11.61#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:17:11.61#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:17:11.61$vc4f8/vb=4,4 2006.231.08:17:11.61#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.231.08:17:11.61#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.231.08:17:11.61#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:11.61#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:17:11.67#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:17:11.67#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:17:11.67#ibcon#enter wrdev, iclass 29, count 2 2006.231.08:17:11.67#ibcon#first serial, iclass 29, count 2 2006.231.08:17:11.67#ibcon#enter sib2, iclass 29, count 2 2006.231.08:17:11.67#ibcon#flushed, iclass 29, count 2 2006.231.08:17:11.67#ibcon#about to write, iclass 29, count 2 2006.231.08:17:11.67#ibcon#wrote, iclass 29, count 2 2006.231.08:17:11.67#ibcon#about to read 3, iclass 29, count 2 2006.231.08:17:11.69#ibcon#read 3, iclass 29, count 2 2006.231.08:17:11.69#ibcon#about to read 4, iclass 29, count 2 2006.231.08:17:11.69#ibcon#read 4, iclass 29, count 2 2006.231.08:17:11.69#ibcon#about to read 5, iclass 29, count 2 2006.231.08:17:11.69#ibcon#read 5, iclass 29, count 2 2006.231.08:17:11.69#ibcon#about to read 6, iclass 29, count 2 2006.231.08:17:11.69#ibcon#read 6, iclass 29, count 2 2006.231.08:17:11.69#ibcon#end of sib2, iclass 29, count 2 2006.231.08:17:11.69#ibcon#*mode == 0, iclass 29, count 2 2006.231.08:17:11.69#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.231.08:17:11.69#ibcon#[27=AT04-04\r\n] 2006.231.08:17:11.69#ibcon#*before write, iclass 29, count 2 2006.231.08:17:11.69#ibcon#enter sib2, iclass 29, count 2 2006.231.08:17:11.69#ibcon#flushed, iclass 29, count 2 2006.231.08:17:11.69#ibcon#about to write, iclass 29, count 2 2006.231.08:17:11.69#ibcon#wrote, iclass 29, count 2 2006.231.08:17:11.69#ibcon#about to read 3, iclass 29, count 2 2006.231.08:17:11.72#ibcon#read 3, iclass 29, count 2 2006.231.08:17:11.72#ibcon#about to read 4, iclass 29, count 2 2006.231.08:17:11.72#ibcon#read 4, iclass 29, count 2 2006.231.08:17:11.72#ibcon#about to read 5, iclass 29, count 2 2006.231.08:17:11.72#ibcon#read 5, iclass 29, count 2 2006.231.08:17:11.72#ibcon#about to read 6, iclass 29, count 2 2006.231.08:17:11.72#ibcon#read 6, iclass 29, count 2 2006.231.08:17:11.72#ibcon#end of sib2, iclass 29, count 2 2006.231.08:17:11.72#ibcon#*after write, iclass 29, count 2 2006.231.08:17:11.72#ibcon#*before return 0, iclass 29, count 2 2006.231.08:17:11.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:17:11.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.231.08:17:11.72#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.231.08:17:11.72#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:11.72#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:17:11.84#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:17:11.84#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:17:11.84#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:17:11.84#ibcon#first serial, iclass 29, count 0 2006.231.08:17:11.84#ibcon#enter sib2, iclass 29, count 0 2006.231.08:17:11.84#ibcon#flushed, iclass 29, count 0 2006.231.08:17:11.84#ibcon#about to write, iclass 29, count 0 2006.231.08:17:11.84#ibcon#wrote, iclass 29, count 0 2006.231.08:17:11.84#ibcon#about to read 3, iclass 29, count 0 2006.231.08:17:11.86#ibcon#read 3, iclass 29, count 0 2006.231.08:17:11.86#ibcon#about to read 4, iclass 29, count 0 2006.231.08:17:11.86#ibcon#read 4, iclass 29, count 0 2006.231.08:17:11.86#ibcon#about to read 5, iclass 29, count 0 2006.231.08:17:11.86#ibcon#read 5, iclass 29, count 0 2006.231.08:17:11.86#ibcon#about to read 6, iclass 29, count 0 2006.231.08:17:11.86#ibcon#read 6, iclass 29, count 0 2006.231.08:17:11.86#ibcon#end of sib2, iclass 29, count 0 2006.231.08:17:11.86#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:17:11.86#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:17:11.86#ibcon#[27=USB\r\n] 2006.231.08:17:11.86#ibcon#*before write, iclass 29, count 0 2006.231.08:17:11.86#ibcon#enter sib2, iclass 29, count 0 2006.231.08:17:11.86#ibcon#flushed, iclass 29, count 0 2006.231.08:17:11.86#ibcon#about to write, iclass 29, count 0 2006.231.08:17:11.86#ibcon#wrote, iclass 29, count 0 2006.231.08:17:11.86#ibcon#about to read 3, iclass 29, count 0 2006.231.08:17:11.89#ibcon#read 3, iclass 29, count 0 2006.231.08:17:11.89#ibcon#about to read 4, iclass 29, count 0 2006.231.08:17:11.89#ibcon#read 4, iclass 29, count 0 2006.231.08:17:11.89#ibcon#about to read 5, iclass 29, count 0 2006.231.08:17:11.89#ibcon#read 5, iclass 29, count 0 2006.231.08:17:11.89#ibcon#about to read 6, iclass 29, count 0 2006.231.08:17:11.89#ibcon#read 6, iclass 29, count 0 2006.231.08:17:11.89#ibcon#end of sib2, iclass 29, count 0 2006.231.08:17:11.89#ibcon#*after write, iclass 29, count 0 2006.231.08:17:11.89#ibcon#*before return 0, iclass 29, count 0 2006.231.08:17:11.89#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:17:11.89#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.231.08:17:11.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:17:11.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:17:11.89$vc4f8/vblo=5,744.99 2006.231.08:17:11.89#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.231.08:17:11.89#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.231.08:17:11.89#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:11.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:17:11.89#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:17:11.89#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:17:11.89#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:17:11.89#ibcon#first serial, iclass 31, count 0 2006.231.08:17:11.89#ibcon#enter sib2, iclass 31, count 0 2006.231.08:17:11.89#ibcon#flushed, iclass 31, count 0 2006.231.08:17:11.89#ibcon#about to write, iclass 31, count 0 2006.231.08:17:11.89#ibcon#wrote, iclass 31, count 0 2006.231.08:17:11.89#ibcon#about to read 3, iclass 31, count 0 2006.231.08:17:11.91#ibcon#read 3, iclass 31, count 0 2006.231.08:17:11.91#ibcon#about to read 4, iclass 31, count 0 2006.231.08:17:11.91#ibcon#read 4, iclass 31, count 0 2006.231.08:17:11.91#ibcon#about to read 5, iclass 31, count 0 2006.231.08:17:11.91#ibcon#read 5, iclass 31, count 0 2006.231.08:17:11.91#ibcon#about to read 6, iclass 31, count 0 2006.231.08:17:11.91#ibcon#read 6, iclass 31, count 0 2006.231.08:17:11.91#ibcon#end of sib2, iclass 31, count 0 2006.231.08:17:11.91#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:17:11.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:17:11.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:17:11.91#ibcon#*before write, iclass 31, count 0 2006.231.08:17:11.91#ibcon#enter sib2, iclass 31, count 0 2006.231.08:17:11.91#ibcon#flushed, iclass 31, count 0 2006.231.08:17:11.91#ibcon#about to write, iclass 31, count 0 2006.231.08:17:11.91#ibcon#wrote, iclass 31, count 0 2006.231.08:17:11.91#ibcon#about to read 3, iclass 31, count 0 2006.231.08:17:11.95#ibcon#read 3, iclass 31, count 0 2006.231.08:17:11.95#ibcon#about to read 4, iclass 31, count 0 2006.231.08:17:11.95#ibcon#read 4, iclass 31, count 0 2006.231.08:17:11.95#ibcon#about to read 5, iclass 31, count 0 2006.231.08:17:11.95#ibcon#read 5, iclass 31, count 0 2006.231.08:17:11.95#ibcon#about to read 6, iclass 31, count 0 2006.231.08:17:11.95#ibcon#read 6, iclass 31, count 0 2006.231.08:17:11.95#ibcon#end of sib2, iclass 31, count 0 2006.231.08:17:11.95#ibcon#*after write, iclass 31, count 0 2006.231.08:17:11.95#ibcon#*before return 0, iclass 31, count 0 2006.231.08:17:11.95#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:17:11.95#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.231.08:17:11.95#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:17:11.95#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:17:11.95$vc4f8/vb=5,3 2006.231.08:17:11.95#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.231.08:17:11.95#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.231.08:17:11.95#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:11.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:17:12.01#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:17:12.01#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:17:12.01#ibcon#enter wrdev, iclass 33, count 2 2006.231.08:17:12.01#ibcon#first serial, iclass 33, count 2 2006.231.08:17:12.01#ibcon#enter sib2, iclass 33, count 2 2006.231.08:17:12.01#ibcon#flushed, iclass 33, count 2 2006.231.08:17:12.01#ibcon#about to write, iclass 33, count 2 2006.231.08:17:12.01#ibcon#wrote, iclass 33, count 2 2006.231.08:17:12.01#ibcon#about to read 3, iclass 33, count 2 2006.231.08:17:12.03#ibcon#read 3, iclass 33, count 2 2006.231.08:17:12.03#ibcon#about to read 4, iclass 33, count 2 2006.231.08:17:12.03#ibcon#read 4, iclass 33, count 2 2006.231.08:17:12.03#ibcon#about to read 5, iclass 33, count 2 2006.231.08:17:12.03#ibcon#read 5, iclass 33, count 2 2006.231.08:17:12.03#ibcon#about to read 6, iclass 33, count 2 2006.231.08:17:12.03#ibcon#read 6, iclass 33, count 2 2006.231.08:17:12.03#ibcon#end of sib2, iclass 33, count 2 2006.231.08:17:12.03#ibcon#*mode == 0, iclass 33, count 2 2006.231.08:17:12.03#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.231.08:17:12.03#ibcon#[27=AT05-03\r\n] 2006.231.08:17:12.03#ibcon#*before write, iclass 33, count 2 2006.231.08:17:12.03#ibcon#enter sib2, iclass 33, count 2 2006.231.08:17:12.03#ibcon#flushed, iclass 33, count 2 2006.231.08:17:12.03#ibcon#about to write, iclass 33, count 2 2006.231.08:17:12.03#ibcon#wrote, iclass 33, count 2 2006.231.08:17:12.03#ibcon#about to read 3, iclass 33, count 2 2006.231.08:17:12.06#ibcon#read 3, iclass 33, count 2 2006.231.08:17:12.06#ibcon#about to read 4, iclass 33, count 2 2006.231.08:17:12.06#ibcon#read 4, iclass 33, count 2 2006.231.08:17:12.06#ibcon#about to read 5, iclass 33, count 2 2006.231.08:17:12.06#ibcon#read 5, iclass 33, count 2 2006.231.08:17:12.06#ibcon#about to read 6, iclass 33, count 2 2006.231.08:17:12.06#ibcon#read 6, iclass 33, count 2 2006.231.08:17:12.06#ibcon#end of sib2, iclass 33, count 2 2006.231.08:17:12.06#ibcon#*after write, iclass 33, count 2 2006.231.08:17:12.06#ibcon#*before return 0, iclass 33, count 2 2006.231.08:17:12.06#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:17:12.06#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.231.08:17:12.06#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.231.08:17:12.06#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:12.06#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:17:12.18#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:17:12.18#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:17:12.18#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:17:12.18#ibcon#first serial, iclass 33, count 0 2006.231.08:17:12.18#ibcon#enter sib2, iclass 33, count 0 2006.231.08:17:12.18#ibcon#flushed, iclass 33, count 0 2006.231.08:17:12.18#ibcon#about to write, iclass 33, count 0 2006.231.08:17:12.18#ibcon#wrote, iclass 33, count 0 2006.231.08:17:12.18#ibcon#about to read 3, iclass 33, count 0 2006.231.08:17:12.20#ibcon#read 3, iclass 33, count 0 2006.231.08:17:12.20#ibcon#about to read 4, iclass 33, count 0 2006.231.08:17:12.20#ibcon#read 4, iclass 33, count 0 2006.231.08:17:12.20#ibcon#about to read 5, iclass 33, count 0 2006.231.08:17:12.20#ibcon#read 5, iclass 33, count 0 2006.231.08:17:12.20#ibcon#about to read 6, iclass 33, count 0 2006.231.08:17:12.20#ibcon#read 6, iclass 33, count 0 2006.231.08:17:12.20#ibcon#end of sib2, iclass 33, count 0 2006.231.08:17:12.20#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:17:12.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:17:12.20#ibcon#[27=USB\r\n] 2006.231.08:17:12.20#ibcon#*before write, iclass 33, count 0 2006.231.08:17:12.20#ibcon#enter sib2, iclass 33, count 0 2006.231.08:17:12.20#ibcon#flushed, iclass 33, count 0 2006.231.08:17:12.20#ibcon#about to write, iclass 33, count 0 2006.231.08:17:12.20#ibcon#wrote, iclass 33, count 0 2006.231.08:17:12.20#ibcon#about to read 3, iclass 33, count 0 2006.231.08:17:12.23#ibcon#read 3, iclass 33, count 0 2006.231.08:17:12.23#ibcon#about to read 4, iclass 33, count 0 2006.231.08:17:12.23#ibcon#read 4, iclass 33, count 0 2006.231.08:17:12.23#ibcon#about to read 5, iclass 33, count 0 2006.231.08:17:12.23#ibcon#read 5, iclass 33, count 0 2006.231.08:17:12.23#ibcon#about to read 6, iclass 33, count 0 2006.231.08:17:12.23#ibcon#read 6, iclass 33, count 0 2006.231.08:17:12.23#ibcon#end of sib2, iclass 33, count 0 2006.231.08:17:12.23#ibcon#*after write, iclass 33, count 0 2006.231.08:17:12.23#ibcon#*before return 0, iclass 33, count 0 2006.231.08:17:12.23#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:17:12.23#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.231.08:17:12.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:17:12.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:17:12.23$vc4f8/vblo=6,752.99 2006.231.08:17:12.23#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.231.08:17:12.23#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.231.08:17:12.23#ibcon#ireg 17 cls_cnt 0 2006.231.08:17:12.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:17:12.23#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:17:12.23#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:17:12.23#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:17:12.23#ibcon#first serial, iclass 35, count 0 2006.231.08:17:12.23#ibcon#enter sib2, iclass 35, count 0 2006.231.08:17:12.23#ibcon#flushed, iclass 35, count 0 2006.231.08:17:12.23#ibcon#about to write, iclass 35, count 0 2006.231.08:17:12.23#ibcon#wrote, iclass 35, count 0 2006.231.08:17:12.23#ibcon#about to read 3, iclass 35, count 0 2006.231.08:17:12.25#ibcon#read 3, iclass 35, count 0 2006.231.08:17:12.25#ibcon#about to read 4, iclass 35, count 0 2006.231.08:17:12.25#ibcon#read 4, iclass 35, count 0 2006.231.08:17:12.25#ibcon#about to read 5, iclass 35, count 0 2006.231.08:17:12.25#ibcon#read 5, iclass 35, count 0 2006.231.08:17:12.25#ibcon#about to read 6, iclass 35, count 0 2006.231.08:17:12.25#ibcon#read 6, iclass 35, count 0 2006.231.08:17:12.25#ibcon#end of sib2, iclass 35, count 0 2006.231.08:17:12.25#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:17:12.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:17:12.25#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:17:12.25#ibcon#*before write, iclass 35, count 0 2006.231.08:17:12.25#ibcon#enter sib2, iclass 35, count 0 2006.231.08:17:12.25#ibcon#flushed, iclass 35, count 0 2006.231.08:17:12.25#ibcon#about to write, iclass 35, count 0 2006.231.08:17:12.25#ibcon#wrote, iclass 35, count 0 2006.231.08:17:12.25#ibcon#about to read 3, iclass 35, count 0 2006.231.08:17:12.29#ibcon#read 3, iclass 35, count 0 2006.231.08:17:12.29#ibcon#about to read 4, iclass 35, count 0 2006.231.08:17:12.29#ibcon#read 4, iclass 35, count 0 2006.231.08:17:12.29#ibcon#about to read 5, iclass 35, count 0 2006.231.08:17:12.29#ibcon#read 5, iclass 35, count 0 2006.231.08:17:12.29#ibcon#about to read 6, iclass 35, count 0 2006.231.08:17:12.29#ibcon#read 6, iclass 35, count 0 2006.231.08:17:12.29#ibcon#end of sib2, iclass 35, count 0 2006.231.08:17:12.29#ibcon#*after write, iclass 35, count 0 2006.231.08:17:12.29#ibcon#*before return 0, iclass 35, count 0 2006.231.08:17:12.29#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:17:12.29#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.231.08:17:12.29#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:17:12.29#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:17:12.29$vc4f8/vb=6,4 2006.231.08:17:12.29#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.231.08:17:12.29#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.231.08:17:12.29#ibcon#ireg 11 cls_cnt 2 2006.231.08:17:12.29#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:17:12.35#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:17:12.35#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:17:12.35#ibcon#enter wrdev, iclass 37, count 2 2006.231.08:17:12.35#ibcon#first serial, iclass 37, count 2 2006.231.08:17:12.35#ibcon#enter sib2, iclass 37, count 2 2006.231.08:17:12.35#ibcon#flushed, iclass 37, count 2 2006.231.08:17:12.35#ibcon#about to write, iclass 37, count 2 2006.231.08:17:12.35#ibcon#wrote, iclass 37, count 2 2006.231.08:17:12.35#ibcon#about to read 3, iclass 37, count 2 2006.231.08:17:12.37#ibcon#read 3, iclass 37, count 2 2006.231.08:17:12.37#ibcon#about to read 4, iclass 37, count 2 2006.231.08:17:12.37#ibcon#read 4, iclass 37, count 2 2006.231.08:17:12.37#ibcon#about to read 5, iclass 37, count 2 2006.231.08:17:12.37#ibcon#read 5, iclass 37, count 2 2006.231.08:17:12.37#ibcon#about to read 6, iclass 37, count 2 2006.231.08:17:12.37#ibcon#read 6, iclass 37, count 2 2006.231.08:17:12.37#ibcon#end of sib2, iclass 37, count 2 2006.231.08:17:12.37#ibcon#*mode == 0, iclass 37, count 2 2006.231.08:17:12.37#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.231.08:17:12.37#ibcon#[27=AT06-04\r\n] 2006.231.08:17:12.37#ibcon#*before write, iclass 37, count 2 2006.231.08:17:12.37#ibcon#enter sib2, iclass 37, count 2 2006.231.08:17:12.37#ibcon#flushed, iclass 37, count 2 2006.231.08:17:12.37#ibcon#about to write, iclass 37, count 2 2006.231.08:17:12.37#ibcon#wrote, iclass 37, count 2 2006.231.08:17:12.37#ibcon#about to read 3, iclass 37, count 2 2006.231.08:17:12.40#ibcon#read 3, iclass 37, count 2 2006.231.08:17:12.40#ibcon#about to read 4, iclass 37, count 2 2006.231.08:17:12.40#ibcon#read 4, iclass 37, count 2 2006.231.08:17:12.40#ibcon#about to read 5, iclass 37, count 2 2006.231.08:17:12.40#ibcon#read 5, iclass 37, count 2 2006.231.08:17:12.40#ibcon#about to read 6, iclass 37, count 2 2006.231.08:17:12.40#ibcon#read 6, iclass 37, count 2 2006.231.08:17:12.40#ibcon#end of sib2, iclass 37, count 2 2006.231.08:17:12.40#ibcon#*after write, iclass 37, count 2 2006.231.08:17:12.40#ibcon#*before return 0, iclass 37, count 2 2006.231.08:17:12.40#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:17:12.40#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.231.08:17:12.40#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.231.08:17:12.40#ibcon#ireg 7 cls_cnt 0 2006.231.08:17:12.40#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:17:12.52#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:17:12.52#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:17:12.52#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:17:12.52#ibcon#first serial, iclass 37, count 0 2006.231.08:17:12.52#ibcon#enter sib2, iclass 37, count 0 2006.231.08:17:12.52#ibcon#flushed, iclass 37, count 0 2006.231.08:17:12.52#ibcon#about to write, iclass 37, count 0 2006.231.08:17:12.52#ibcon#wrote, iclass 37, count 0 2006.231.08:17:12.52#ibcon#about to read 3, iclass 37, count 0 2006.231.08:17:12.54#ibcon#read 3, iclass 37, count 0 2006.231.08:17:12.54#ibcon#about to read 4, iclass 37, count 0 2006.231.08:17:12.54#ibcon#read 4, iclass 37, count 0 2006.231.08:17:12.54#ibcon#about to read 5, iclass 37, count 0 2006.231.08:17:12.54#ibcon#read 5, iclass 37, count 0 2006.231.08:17:12.54#ibcon#about to read 6, iclass 37, count 0 2006.231.08:17:12.54#ibcon#read 6, iclass 37, count 0 2006.231.08:17:12.54#ibcon#end of sib2, iclass 37, count 0 2006.231.08:17:12.54#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:17:12.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:17:12.54#ibcon#[27=USB\r\n] 2006.231.08:17:12.54#ibcon#*before write, iclass 37, count 0 2006.231.08:17:12.54#ibcon#enter sib2, iclass 37, count 0 2006.231.08:17:12.54#ibcon#flushed, iclass 37, count 0 2006.231.08:17:12.54#ibcon#about to write, iclass 37, count 0 2006.231.08:17:12.54#ibcon#wrote, iclass 37, count 0 2006.231.08:17:12.54#ibcon#about to read 3, iclass 37, count 0 2006.231.08:17:12.59#ibcon#read 3, iclass 37, count 0 2006.231.08:17:12.59#ibcon#about to read 4, iclass 37, count 0 2006.231.08:17:12.59#ibcon#read 4, iclass 37, count 0 2006.231.08:17:12.59#ibcon#about to read 5, iclass 37, count 0 2006.231.08:17:12.59#ibcon#read 5, iclass 37, count 0 2006.231.08:17:12.59#ibcon#about to read 6, iclass 37, count 0 2006.231.08:17:12.59#ibcon#read 6, iclass 37, count 0 2006.231.08:17:12.59#ibcon#end of sib2, iclass 37, count 0 2006.231.08:17:12.59#ibcon#*after write, iclass 37, count 0 2006.231.08:17:12.59#ibcon#*before return 0, iclass 37, count 0 2006.231.08:17:12.59#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:17:12.59#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.231.08:17:12.59#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:17:12.59#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:17:12.59$vc4f8/vabw=wide 2006.231.08:17:12.59#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.231.08:17:12.59#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.231.08:17:12.59#ibcon#ireg 8 cls_cnt 0 2006.231.08:17:12.59#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:17:12.59#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:17:12.59#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:17:12.59#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:17:12.59#ibcon#first serial, iclass 39, count 0 2006.231.08:17:12.59#ibcon#enter sib2, iclass 39, count 0 2006.231.08:17:12.59#ibcon#flushed, iclass 39, count 0 2006.231.08:17:12.59#ibcon#about to write, iclass 39, count 0 2006.231.08:17:12.59#ibcon#wrote, iclass 39, count 0 2006.231.08:17:12.59#ibcon#about to read 3, iclass 39, count 0 2006.231.08:17:12.60#ibcon#read 3, iclass 39, count 0 2006.231.08:17:12.61#ibcon#about to read 4, iclass 39, count 0 2006.231.08:17:12.61#ibcon#read 4, iclass 39, count 0 2006.231.08:17:12.61#ibcon#about to read 5, iclass 39, count 0 2006.231.08:17:12.61#ibcon#read 5, iclass 39, count 0 2006.231.08:17:12.61#ibcon#about to read 6, iclass 39, count 0 2006.231.08:17:12.61#ibcon#read 6, iclass 39, count 0 2006.231.08:17:12.61#ibcon#end of sib2, iclass 39, count 0 2006.231.08:17:12.61#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:17:12.61#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:17:12.61#ibcon#[25=BW32\r\n] 2006.231.08:17:12.61#ibcon#*before write, iclass 39, count 0 2006.231.08:17:12.61#ibcon#enter sib2, iclass 39, count 0 2006.231.08:17:12.61#ibcon#flushed, iclass 39, count 0 2006.231.08:17:12.61#ibcon#about to write, iclass 39, count 0 2006.231.08:17:12.61#ibcon#wrote, iclass 39, count 0 2006.231.08:17:12.61#ibcon#about to read 3, iclass 39, count 0 2006.231.08:17:12.63#ibcon#read 3, iclass 39, count 0 2006.231.08:17:12.63#ibcon#about to read 4, iclass 39, count 0 2006.231.08:17:12.63#ibcon#read 4, iclass 39, count 0 2006.231.08:17:12.63#ibcon#about to read 5, iclass 39, count 0 2006.231.08:17:12.63#ibcon#read 5, iclass 39, count 0 2006.231.08:17:12.63#ibcon#about to read 6, iclass 39, count 0 2006.231.08:17:12.63#ibcon#read 6, iclass 39, count 0 2006.231.08:17:12.63#ibcon#end of sib2, iclass 39, count 0 2006.231.08:17:12.63#ibcon#*after write, iclass 39, count 0 2006.231.08:17:12.63#ibcon#*before return 0, iclass 39, count 0 2006.231.08:17:12.63#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:17:12.63#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.231.08:17:12.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:17:12.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:17:12.63$vc4f8/vbbw=wide 2006.231.08:17:12.63#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.08:17:12.63#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.08:17:12.63#ibcon#ireg 8 cls_cnt 0 2006.231.08:17:12.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:17:12.71#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:17:12.71#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:17:12.71#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:17:12.71#ibcon#first serial, iclass 3, count 0 2006.231.08:17:12.71#ibcon#enter sib2, iclass 3, count 0 2006.231.08:17:12.71#ibcon#flushed, iclass 3, count 0 2006.231.08:17:12.71#ibcon#about to write, iclass 3, count 0 2006.231.08:17:12.71#ibcon#wrote, iclass 3, count 0 2006.231.08:17:12.71#ibcon#about to read 3, iclass 3, count 0 2006.231.08:17:12.73#ibcon#read 3, iclass 3, count 0 2006.231.08:17:12.73#ibcon#about to read 4, iclass 3, count 0 2006.231.08:17:12.73#ibcon#read 4, iclass 3, count 0 2006.231.08:17:12.73#ibcon#about to read 5, iclass 3, count 0 2006.231.08:17:12.73#ibcon#read 5, iclass 3, count 0 2006.231.08:17:12.73#ibcon#about to read 6, iclass 3, count 0 2006.231.08:17:12.73#ibcon#read 6, iclass 3, count 0 2006.231.08:17:12.73#ibcon#end of sib2, iclass 3, count 0 2006.231.08:17:12.73#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:17:12.73#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:17:12.73#ibcon#[27=BW32\r\n] 2006.231.08:17:12.73#ibcon#*before write, iclass 3, count 0 2006.231.08:17:12.73#ibcon#enter sib2, iclass 3, count 0 2006.231.08:17:12.73#ibcon#flushed, iclass 3, count 0 2006.231.08:17:12.73#ibcon#about to write, iclass 3, count 0 2006.231.08:17:12.73#ibcon#wrote, iclass 3, count 0 2006.231.08:17:12.73#ibcon#about to read 3, iclass 3, count 0 2006.231.08:17:12.77#ibcon#read 3, iclass 3, count 0 2006.231.08:17:12.77#ibcon#about to read 4, iclass 3, count 0 2006.231.08:17:12.77#ibcon#read 4, iclass 3, count 0 2006.231.08:17:12.77#ibcon#about to read 5, iclass 3, count 0 2006.231.08:17:12.77#ibcon#read 5, iclass 3, count 0 2006.231.08:17:12.77#ibcon#about to read 6, iclass 3, count 0 2006.231.08:17:12.77#ibcon#read 6, iclass 3, count 0 2006.231.08:17:12.77#ibcon#end of sib2, iclass 3, count 0 2006.231.08:17:12.77#ibcon#*after write, iclass 3, count 0 2006.231.08:17:12.77#ibcon#*before return 0, iclass 3, count 0 2006.231.08:17:12.77#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:17:12.77#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:17:12.77#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:17:12.77#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:17:12.77$4f8m12a/ifd4f 2006.231.08:17:12.77$ifd4f/lo= 2006.231.08:17:12.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:17:12.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:17:12.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:17:12.77$ifd4f/patch= 2006.231.08:17:12.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:17:12.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:17:12.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:17:12.77$4f8m12a/"form=m,16.000,1:2 2006.231.08:17:12.77$4f8m12a/"tpicd 2006.231.08:17:12.77$4f8m12a/echo=off 2006.231.08:17:12.77$4f8m12a/xlog=off 2006.231.08:17:12.77:!2006.231.08:17:40 2006.231.08:17:19.13#trakl#Source acquired 2006.231.08:17:19.13#flagr#flagr/antenna,acquired 2006.231.08:17:40.01:preob 2006.231.08:17:41.13/onsource/TRACKING 2006.231.08:17:41.13:!2006.231.08:17:50 2006.231.08:17:50.00:data_valid=on 2006.231.08:17:50.00:midob 2006.231.08:17:50.13/onsource/TRACKING 2006.231.08:17:50.13/wx/30.38,1004.5,83 2006.231.08:17:50.22/cable/+6.3718E-03 2006.231.08:17:51.31/va/01,08,usb,yes,29,31 2006.231.08:17:51.31/va/02,07,usb,yes,29,31 2006.231.08:17:51.31/va/03,08,usb,yes,22,22 2006.231.08:17:51.31/va/04,07,usb,yes,30,33 2006.231.08:17:51.31/va/05,07,usb,yes,34,36 2006.231.08:17:51.31/va/06,06,usb,yes,33,33 2006.231.08:17:51.31/va/07,06,usb,yes,34,34 2006.231.08:17:51.31/va/08,06,usb,yes,36,35 2006.231.08:17:51.54/valo/01,532.99,yes,locked 2006.231.08:17:51.54/valo/02,572.99,yes,locked 2006.231.08:17:51.54/valo/03,672.99,yes,locked 2006.231.08:17:51.54/valo/04,832.99,yes,locked 2006.231.08:17:51.54/valo/05,652.99,yes,locked 2006.231.08:17:51.54/valo/06,772.99,yes,locked 2006.231.08:17:51.54/valo/07,832.99,yes,locked 2006.231.08:17:51.54/valo/08,852.99,yes,locked 2006.231.08:17:52.63/vb/01,04,usb,yes,30,29 2006.231.08:17:52.63/vb/02,04,usb,yes,32,34 2006.231.08:17:52.63/vb/03,04,usb,yes,29,32 2006.231.08:17:52.63/vb/04,04,usb,yes,29,30 2006.231.08:17:52.63/vb/05,03,usb,yes,35,39 2006.231.08:17:52.63/vb/06,04,usb,yes,29,32 2006.231.08:17:52.63/vb/07,04,usb,yes,31,31 2006.231.08:17:52.63/vb/08,04,usb,yes,28,32 2006.231.08:17:52.87/vblo/01,632.99,yes,locked 2006.231.08:17:52.87/vblo/02,640.99,yes,locked 2006.231.08:17:52.87/vblo/03,656.99,yes,locked 2006.231.08:17:52.87/vblo/04,712.99,yes,locked 2006.231.08:17:52.87/vblo/05,744.99,yes,locked 2006.231.08:17:52.87/vblo/06,752.99,yes,locked 2006.231.08:17:52.87/vblo/07,734.99,yes,locked 2006.231.08:17:52.87/vblo/08,744.99,yes,locked 2006.231.08:17:53.02/vabw/8 2006.231.08:17:53.17/vbbw/8 2006.231.08:17:53.26/xfe/off,on,12.2 2006.231.08:17:53.63/ifatt/23,28,28,28 2006.231.08:17:54.07/fmout-gps/S +4.45E-07 2006.231.08:17:54.11:!2006.231.08:18:50 2006.231.08:18:50.00:data_valid=off 2006.231.08:18:50.00:postob 2006.231.08:18:50.14/cable/+6.3714E-03 2006.231.08:18:50.15/wx/30.35,1004.5,83 2006.231.08:18:51.08/fmout-gps/S +4.45E-07 2006.231.08:18:51.08:scan_name=231-0820,k06231,60 2006.231.08:18:51.09:source=oq208,140700.39,282714.7,2000.0,ccw 2006.231.08:18:51.14#flagr#flagr/antenna,new-source 2006.231.08:18:52.14:checkk5 2006.231.08:18:52.53/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:18:52.92/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:18:53.27/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:18:53.65/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:18:54.01/chk_obsdata//k5ts1/T2310817??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:18:54.38/chk_obsdata//k5ts2/T2310817??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:18:54.74/chk_obsdata//k5ts3/T2310817??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:18:55.11/chk_obsdata//k5ts4/T2310817??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:18:55.80/k5log//k5ts1_log_newline 2006.231.08:18:56.49/k5log//k5ts2_log_newline 2006.231.08:18:57.18/k5log//k5ts3_log_newline 2006.231.08:18:57.86/k5log//k5ts4_log_newline 2006.231.08:18:57.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:18:57.89:4f8m12a=3 2006.231.08:18:57.89$4f8m12a/echo=on 2006.231.08:18:57.89$4f8m12a/pcalon 2006.231.08:18:57.89$pcalon/"no phase cal control is implemented here 2006.231.08:18:57.89$4f8m12a/"tpicd=stop 2006.231.08:18:57.89$4f8m12a/vc4f8 2006.231.08:18:57.89$vc4f8/valo=1,532.99 2006.231.08:18:57.89#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.08:18:57.89#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.08:18:57.89#ibcon#ireg 17 cls_cnt 0 2006.231.08:18:57.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:18:57.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:18:57.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:18:57.89#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:18:57.89#ibcon#first serial, iclass 12, count 0 2006.231.08:18:57.89#ibcon#enter sib2, iclass 12, count 0 2006.231.08:18:57.89#ibcon#flushed, iclass 12, count 0 2006.231.08:18:57.89#ibcon#about to write, iclass 12, count 0 2006.231.08:18:57.89#ibcon#wrote, iclass 12, count 0 2006.231.08:18:57.89#ibcon#about to read 3, iclass 12, count 0 2006.231.08:18:57.93#ibcon#read 3, iclass 12, count 0 2006.231.08:18:57.93#ibcon#about to read 4, iclass 12, count 0 2006.231.08:18:57.93#ibcon#read 4, iclass 12, count 0 2006.231.08:18:57.93#ibcon#about to read 5, iclass 12, count 0 2006.231.08:18:57.93#ibcon#read 5, iclass 12, count 0 2006.231.08:18:57.93#ibcon#about to read 6, iclass 12, count 0 2006.231.08:18:57.93#ibcon#read 6, iclass 12, count 0 2006.231.08:18:57.93#ibcon#end of sib2, iclass 12, count 0 2006.231.08:18:57.93#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:18:57.93#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:18:57.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:18:57.93#ibcon#*before write, iclass 12, count 0 2006.231.08:18:57.93#ibcon#enter sib2, iclass 12, count 0 2006.231.08:18:57.93#ibcon#flushed, iclass 12, count 0 2006.231.08:18:57.93#ibcon#about to write, iclass 12, count 0 2006.231.08:18:57.93#ibcon#wrote, iclass 12, count 0 2006.231.08:18:57.93#ibcon#about to read 3, iclass 12, count 0 2006.231.08:18:57.98#ibcon#read 3, iclass 12, count 0 2006.231.08:18:57.98#ibcon#about to read 4, iclass 12, count 0 2006.231.08:18:57.98#ibcon#read 4, iclass 12, count 0 2006.231.08:18:57.98#ibcon#about to read 5, iclass 12, count 0 2006.231.08:18:57.98#ibcon#read 5, iclass 12, count 0 2006.231.08:18:57.98#ibcon#about to read 6, iclass 12, count 0 2006.231.08:18:57.98#ibcon#read 6, iclass 12, count 0 2006.231.08:18:57.98#ibcon#end of sib2, iclass 12, count 0 2006.231.08:18:57.98#ibcon#*after write, iclass 12, count 0 2006.231.08:18:57.98#ibcon#*before return 0, iclass 12, count 0 2006.231.08:18:57.98#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:18:57.98#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:18:57.98#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:18:57.98#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:18:57.98$vc4f8/va=1,8 2006.231.08:18:57.98#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.08:18:57.98#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.08:18:57.98#ibcon#ireg 11 cls_cnt 2 2006.231.08:18:57.98#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:18:57.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:18:57.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:18:57.98#ibcon#enter wrdev, iclass 14, count 2 2006.231.08:18:57.98#ibcon#first serial, iclass 14, count 2 2006.231.08:18:57.98#ibcon#enter sib2, iclass 14, count 2 2006.231.08:18:57.98#ibcon#flushed, iclass 14, count 2 2006.231.08:18:57.98#ibcon#about to write, iclass 14, count 2 2006.231.08:18:57.98#ibcon#wrote, iclass 14, count 2 2006.231.08:18:57.98#ibcon#about to read 3, iclass 14, count 2 2006.231.08:18:58.00#ibcon#read 3, iclass 14, count 2 2006.231.08:18:58.00#ibcon#about to read 4, iclass 14, count 2 2006.231.08:18:58.00#ibcon#read 4, iclass 14, count 2 2006.231.08:18:58.00#ibcon#about to read 5, iclass 14, count 2 2006.231.08:18:58.00#ibcon#read 5, iclass 14, count 2 2006.231.08:18:58.00#ibcon#about to read 6, iclass 14, count 2 2006.231.08:18:58.00#ibcon#read 6, iclass 14, count 2 2006.231.08:18:58.00#ibcon#end of sib2, iclass 14, count 2 2006.231.08:18:58.00#ibcon#*mode == 0, iclass 14, count 2 2006.231.08:18:58.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.08:18:58.00#ibcon#[25=AT01-08\r\n] 2006.231.08:18:58.00#ibcon#*before write, iclass 14, count 2 2006.231.08:18:58.00#ibcon#enter sib2, iclass 14, count 2 2006.231.08:18:58.00#ibcon#flushed, iclass 14, count 2 2006.231.08:18:58.00#ibcon#about to write, iclass 14, count 2 2006.231.08:18:58.00#ibcon#wrote, iclass 14, count 2 2006.231.08:18:58.00#ibcon#about to read 3, iclass 14, count 2 2006.231.08:18:58.03#ibcon#read 3, iclass 14, count 2 2006.231.08:18:58.03#ibcon#about to read 4, iclass 14, count 2 2006.231.08:18:58.03#ibcon#read 4, iclass 14, count 2 2006.231.08:18:58.03#ibcon#about to read 5, iclass 14, count 2 2006.231.08:18:58.03#ibcon#read 5, iclass 14, count 2 2006.231.08:18:58.03#ibcon#about to read 6, iclass 14, count 2 2006.231.08:18:58.03#ibcon#read 6, iclass 14, count 2 2006.231.08:18:58.03#ibcon#end of sib2, iclass 14, count 2 2006.231.08:18:58.03#ibcon#*after write, iclass 14, count 2 2006.231.08:18:58.03#ibcon#*before return 0, iclass 14, count 2 2006.231.08:18:58.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:18:58.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:18:58.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.08:18:58.03#ibcon#ireg 7 cls_cnt 0 2006.231.08:18:58.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:18:58.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:18:58.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:18:58.15#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:18:58.15#ibcon#first serial, iclass 14, count 0 2006.231.08:18:58.15#ibcon#enter sib2, iclass 14, count 0 2006.231.08:18:58.15#ibcon#flushed, iclass 14, count 0 2006.231.08:18:58.15#ibcon#about to write, iclass 14, count 0 2006.231.08:18:58.15#ibcon#wrote, iclass 14, count 0 2006.231.08:18:58.15#ibcon#about to read 3, iclass 14, count 0 2006.231.08:18:58.17#ibcon#read 3, iclass 14, count 0 2006.231.08:18:58.17#ibcon#about to read 4, iclass 14, count 0 2006.231.08:18:58.17#ibcon#read 4, iclass 14, count 0 2006.231.08:18:58.17#ibcon#about to read 5, iclass 14, count 0 2006.231.08:18:58.17#ibcon#read 5, iclass 14, count 0 2006.231.08:18:58.17#ibcon#about to read 6, iclass 14, count 0 2006.231.08:18:58.17#ibcon#read 6, iclass 14, count 0 2006.231.08:18:58.17#ibcon#end of sib2, iclass 14, count 0 2006.231.08:18:58.17#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:18:58.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:18:58.17#ibcon#[25=USB\r\n] 2006.231.08:18:58.17#ibcon#*before write, iclass 14, count 0 2006.231.08:18:58.17#ibcon#enter sib2, iclass 14, count 0 2006.231.08:18:58.17#ibcon#flushed, iclass 14, count 0 2006.231.08:18:58.17#ibcon#about to write, iclass 14, count 0 2006.231.08:18:58.17#ibcon#wrote, iclass 14, count 0 2006.231.08:18:58.17#ibcon#about to read 3, iclass 14, count 0 2006.231.08:18:58.20#ibcon#read 3, iclass 14, count 0 2006.231.08:18:58.20#ibcon#about to read 4, iclass 14, count 0 2006.231.08:18:58.20#ibcon#read 4, iclass 14, count 0 2006.231.08:18:58.20#ibcon#about to read 5, iclass 14, count 0 2006.231.08:18:58.20#ibcon#read 5, iclass 14, count 0 2006.231.08:18:58.20#ibcon#about to read 6, iclass 14, count 0 2006.231.08:18:58.20#ibcon#read 6, iclass 14, count 0 2006.231.08:18:58.20#ibcon#end of sib2, iclass 14, count 0 2006.231.08:18:58.20#ibcon#*after write, iclass 14, count 0 2006.231.08:18:58.20#ibcon#*before return 0, iclass 14, count 0 2006.231.08:18:58.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:18:58.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:18:58.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:18:58.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:18:58.20$vc4f8/valo=2,572.99 2006.231.08:18:58.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.08:18:58.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.08:18:58.20#ibcon#ireg 17 cls_cnt 0 2006.231.08:18:58.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:18:58.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:18:58.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:18:58.20#ibcon#enter wrdev, iclass 16, count 0 2006.231.08:18:58.20#ibcon#first serial, iclass 16, count 0 2006.231.08:18:58.20#ibcon#enter sib2, iclass 16, count 0 2006.231.08:18:58.20#ibcon#flushed, iclass 16, count 0 2006.231.08:18:58.20#ibcon#about to write, iclass 16, count 0 2006.231.08:18:58.20#ibcon#wrote, iclass 16, count 0 2006.231.08:18:58.20#ibcon#about to read 3, iclass 16, count 0 2006.231.08:18:58.22#ibcon#read 3, iclass 16, count 0 2006.231.08:18:58.22#ibcon#about to read 4, iclass 16, count 0 2006.231.08:18:58.22#ibcon#read 4, iclass 16, count 0 2006.231.08:18:58.22#ibcon#about to read 5, iclass 16, count 0 2006.231.08:18:58.22#ibcon#read 5, iclass 16, count 0 2006.231.08:18:58.22#ibcon#about to read 6, iclass 16, count 0 2006.231.08:18:58.22#ibcon#read 6, iclass 16, count 0 2006.231.08:18:58.22#ibcon#end of sib2, iclass 16, count 0 2006.231.08:18:58.22#ibcon#*mode == 0, iclass 16, count 0 2006.231.08:18:58.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.08:18:58.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:18:58.22#ibcon#*before write, iclass 16, count 0 2006.231.08:18:58.22#ibcon#enter sib2, iclass 16, count 0 2006.231.08:18:58.22#ibcon#flushed, iclass 16, count 0 2006.231.08:18:58.22#ibcon#about to write, iclass 16, count 0 2006.231.08:18:58.22#ibcon#wrote, iclass 16, count 0 2006.231.08:18:58.22#ibcon#about to read 3, iclass 16, count 0 2006.231.08:18:58.26#ibcon#read 3, iclass 16, count 0 2006.231.08:18:58.26#ibcon#about to read 4, iclass 16, count 0 2006.231.08:18:58.26#ibcon#read 4, iclass 16, count 0 2006.231.08:18:58.26#ibcon#about to read 5, iclass 16, count 0 2006.231.08:18:58.26#ibcon#read 5, iclass 16, count 0 2006.231.08:18:58.26#ibcon#about to read 6, iclass 16, count 0 2006.231.08:18:58.26#ibcon#read 6, iclass 16, count 0 2006.231.08:18:58.26#ibcon#end of sib2, iclass 16, count 0 2006.231.08:18:58.26#ibcon#*after write, iclass 16, count 0 2006.231.08:18:58.26#ibcon#*before return 0, iclass 16, count 0 2006.231.08:18:58.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:18:58.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:18:58.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.08:18:58.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.08:18:58.26$vc4f8/va=2,7 2006.231.08:18:58.26#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.231.08:18:58.26#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.231.08:18:58.26#ibcon#ireg 11 cls_cnt 2 2006.231.08:18:58.26#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:18:58.32#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:18:58.32#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:18:58.32#ibcon#enter wrdev, iclass 18, count 2 2006.231.08:18:58.32#ibcon#first serial, iclass 18, count 2 2006.231.08:18:58.32#ibcon#enter sib2, iclass 18, count 2 2006.231.08:18:58.32#ibcon#flushed, iclass 18, count 2 2006.231.08:18:58.32#ibcon#about to write, iclass 18, count 2 2006.231.08:18:58.32#ibcon#wrote, iclass 18, count 2 2006.231.08:18:58.32#ibcon#about to read 3, iclass 18, count 2 2006.231.08:18:58.34#ibcon#read 3, iclass 18, count 2 2006.231.08:18:58.34#ibcon#about to read 4, iclass 18, count 2 2006.231.08:18:58.34#ibcon#read 4, iclass 18, count 2 2006.231.08:18:58.34#ibcon#about to read 5, iclass 18, count 2 2006.231.08:18:58.34#ibcon#read 5, iclass 18, count 2 2006.231.08:18:58.34#ibcon#about to read 6, iclass 18, count 2 2006.231.08:18:58.34#ibcon#read 6, iclass 18, count 2 2006.231.08:18:58.34#ibcon#end of sib2, iclass 18, count 2 2006.231.08:18:58.34#ibcon#*mode == 0, iclass 18, count 2 2006.231.08:18:58.34#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.231.08:18:58.34#ibcon#[25=AT02-07\r\n] 2006.231.08:18:58.34#ibcon#*before write, iclass 18, count 2 2006.231.08:18:58.34#ibcon#enter sib2, iclass 18, count 2 2006.231.08:18:58.34#ibcon#flushed, iclass 18, count 2 2006.231.08:18:58.34#ibcon#about to write, iclass 18, count 2 2006.231.08:18:58.34#ibcon#wrote, iclass 18, count 2 2006.231.08:18:58.34#ibcon#about to read 3, iclass 18, count 2 2006.231.08:18:58.37#ibcon#read 3, iclass 18, count 2 2006.231.08:18:58.37#ibcon#about to read 4, iclass 18, count 2 2006.231.08:18:58.37#ibcon#read 4, iclass 18, count 2 2006.231.08:18:58.37#ibcon#about to read 5, iclass 18, count 2 2006.231.08:18:58.37#ibcon#read 5, iclass 18, count 2 2006.231.08:18:58.37#ibcon#about to read 6, iclass 18, count 2 2006.231.08:18:58.37#ibcon#read 6, iclass 18, count 2 2006.231.08:18:58.37#ibcon#end of sib2, iclass 18, count 2 2006.231.08:18:58.37#ibcon#*after write, iclass 18, count 2 2006.231.08:18:58.37#ibcon#*before return 0, iclass 18, count 2 2006.231.08:18:58.37#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:18:58.37#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.231.08:18:58.37#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.231.08:18:58.37#ibcon#ireg 7 cls_cnt 0 2006.231.08:18:58.37#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:18:58.49#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:18:58.49#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:18:58.49#ibcon#enter wrdev, iclass 18, count 0 2006.231.08:18:58.49#ibcon#first serial, iclass 18, count 0 2006.231.08:18:58.49#ibcon#enter sib2, iclass 18, count 0 2006.231.08:18:58.49#ibcon#flushed, iclass 18, count 0 2006.231.08:18:58.49#ibcon#about to write, iclass 18, count 0 2006.231.08:18:58.49#ibcon#wrote, iclass 18, count 0 2006.231.08:18:58.49#ibcon#about to read 3, iclass 18, count 0 2006.231.08:18:58.51#ibcon#read 3, iclass 18, count 0 2006.231.08:18:58.51#ibcon#about to read 4, iclass 18, count 0 2006.231.08:18:58.51#ibcon#read 4, iclass 18, count 0 2006.231.08:18:58.51#ibcon#about to read 5, iclass 18, count 0 2006.231.08:18:58.51#ibcon#read 5, iclass 18, count 0 2006.231.08:18:58.51#ibcon#about to read 6, iclass 18, count 0 2006.231.08:18:58.51#ibcon#read 6, iclass 18, count 0 2006.231.08:18:58.51#ibcon#end of sib2, iclass 18, count 0 2006.231.08:18:58.51#ibcon#*mode == 0, iclass 18, count 0 2006.231.08:18:58.51#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.08:18:58.51#ibcon#[25=USB\r\n] 2006.231.08:18:58.51#ibcon#*before write, iclass 18, count 0 2006.231.08:18:58.51#ibcon#enter sib2, iclass 18, count 0 2006.231.08:18:58.51#ibcon#flushed, iclass 18, count 0 2006.231.08:18:58.51#ibcon#about to write, iclass 18, count 0 2006.231.08:18:58.51#ibcon#wrote, iclass 18, count 0 2006.231.08:18:58.51#ibcon#about to read 3, iclass 18, count 0 2006.231.08:18:58.54#ibcon#read 3, iclass 18, count 0 2006.231.08:18:58.54#ibcon#about to read 4, iclass 18, count 0 2006.231.08:18:58.54#ibcon#read 4, iclass 18, count 0 2006.231.08:18:58.54#ibcon#about to read 5, iclass 18, count 0 2006.231.08:18:58.54#ibcon#read 5, iclass 18, count 0 2006.231.08:18:58.54#ibcon#about to read 6, iclass 18, count 0 2006.231.08:18:58.54#ibcon#read 6, iclass 18, count 0 2006.231.08:18:58.54#ibcon#end of sib2, iclass 18, count 0 2006.231.08:18:58.54#ibcon#*after write, iclass 18, count 0 2006.231.08:18:58.54#ibcon#*before return 0, iclass 18, count 0 2006.231.08:18:58.54#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:18:58.54#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.231.08:18:58.54#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.08:18:58.54#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.08:18:58.54$vc4f8/valo=3,672.99 2006.231.08:18:58.54#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.231.08:18:58.54#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.231.08:18:58.54#ibcon#ireg 17 cls_cnt 0 2006.231.08:18:58.54#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:18:58.54#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:18:58.54#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:18:58.54#ibcon#enter wrdev, iclass 20, count 0 2006.231.08:18:58.54#ibcon#first serial, iclass 20, count 0 2006.231.08:18:58.54#ibcon#enter sib2, iclass 20, count 0 2006.231.08:18:58.54#ibcon#flushed, iclass 20, count 0 2006.231.08:18:58.54#ibcon#about to write, iclass 20, count 0 2006.231.08:18:58.54#ibcon#wrote, iclass 20, count 0 2006.231.08:18:58.54#ibcon#about to read 3, iclass 20, count 0 2006.231.08:18:58.56#ibcon#read 3, iclass 20, count 0 2006.231.08:18:58.56#ibcon#about to read 4, iclass 20, count 0 2006.231.08:18:58.56#ibcon#read 4, iclass 20, count 0 2006.231.08:18:58.56#ibcon#about to read 5, iclass 20, count 0 2006.231.08:18:58.56#ibcon#read 5, iclass 20, count 0 2006.231.08:18:58.56#ibcon#about to read 6, iclass 20, count 0 2006.231.08:18:58.56#ibcon#read 6, iclass 20, count 0 2006.231.08:18:58.56#ibcon#end of sib2, iclass 20, count 0 2006.231.08:18:58.56#ibcon#*mode == 0, iclass 20, count 0 2006.231.08:18:58.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.08:18:58.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:18:58.56#ibcon#*before write, iclass 20, count 0 2006.231.08:18:58.56#ibcon#enter sib2, iclass 20, count 0 2006.231.08:18:58.56#ibcon#flushed, iclass 20, count 0 2006.231.08:18:58.56#ibcon#about to write, iclass 20, count 0 2006.231.08:18:58.56#ibcon#wrote, iclass 20, count 0 2006.231.08:18:58.56#ibcon#about to read 3, iclass 20, count 0 2006.231.08:18:58.60#ibcon#read 3, iclass 20, count 0 2006.231.08:18:58.60#ibcon#about to read 4, iclass 20, count 0 2006.231.08:18:58.60#ibcon#read 4, iclass 20, count 0 2006.231.08:18:58.60#ibcon#about to read 5, iclass 20, count 0 2006.231.08:18:58.60#ibcon#read 5, iclass 20, count 0 2006.231.08:18:58.60#ibcon#about to read 6, iclass 20, count 0 2006.231.08:18:58.60#ibcon#read 6, iclass 20, count 0 2006.231.08:18:58.60#ibcon#end of sib2, iclass 20, count 0 2006.231.08:18:58.60#ibcon#*after write, iclass 20, count 0 2006.231.08:18:58.60#ibcon#*before return 0, iclass 20, count 0 2006.231.08:18:58.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:18:58.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:18:58.60#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.08:18:58.60#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.08:18:58.60$vc4f8/va=3,8 2006.231.08:18:58.60#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.231.08:18:58.60#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.231.08:18:58.60#ibcon#ireg 11 cls_cnt 2 2006.231.08:18:58.60#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:18:58.67#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:18:58.67#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:18:58.67#ibcon#enter wrdev, iclass 22, count 2 2006.231.08:18:58.67#ibcon#first serial, iclass 22, count 2 2006.231.08:18:58.67#ibcon#enter sib2, iclass 22, count 2 2006.231.08:18:58.67#ibcon#flushed, iclass 22, count 2 2006.231.08:18:58.67#ibcon#about to write, iclass 22, count 2 2006.231.08:18:58.67#ibcon#wrote, iclass 22, count 2 2006.231.08:18:58.67#ibcon#about to read 3, iclass 22, count 2 2006.231.08:18:58.68#ibcon#read 3, iclass 22, count 2 2006.231.08:18:58.68#ibcon#about to read 4, iclass 22, count 2 2006.231.08:18:58.68#ibcon#read 4, iclass 22, count 2 2006.231.08:18:58.68#ibcon#about to read 5, iclass 22, count 2 2006.231.08:18:58.68#ibcon#read 5, iclass 22, count 2 2006.231.08:18:58.68#ibcon#about to read 6, iclass 22, count 2 2006.231.08:18:58.68#ibcon#read 6, iclass 22, count 2 2006.231.08:18:58.68#ibcon#end of sib2, iclass 22, count 2 2006.231.08:18:58.68#ibcon#*mode == 0, iclass 22, count 2 2006.231.08:18:58.68#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.231.08:18:58.68#ibcon#[25=AT03-08\r\n] 2006.231.08:18:58.68#ibcon#*before write, iclass 22, count 2 2006.231.08:18:58.68#ibcon#enter sib2, iclass 22, count 2 2006.231.08:18:58.68#ibcon#flushed, iclass 22, count 2 2006.231.08:18:58.68#ibcon#about to write, iclass 22, count 2 2006.231.08:18:58.68#ibcon#wrote, iclass 22, count 2 2006.231.08:18:58.68#ibcon#about to read 3, iclass 22, count 2 2006.231.08:18:58.71#ibcon#read 3, iclass 22, count 2 2006.231.08:18:58.71#ibcon#about to read 4, iclass 22, count 2 2006.231.08:18:58.71#ibcon#read 4, iclass 22, count 2 2006.231.08:18:58.71#ibcon#about to read 5, iclass 22, count 2 2006.231.08:18:58.71#ibcon#read 5, iclass 22, count 2 2006.231.08:18:58.71#ibcon#about to read 6, iclass 22, count 2 2006.231.08:18:58.71#ibcon#read 6, iclass 22, count 2 2006.231.08:18:58.71#ibcon#end of sib2, iclass 22, count 2 2006.231.08:18:58.71#ibcon#*after write, iclass 22, count 2 2006.231.08:18:58.71#ibcon#*before return 0, iclass 22, count 2 2006.231.08:18:58.71#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:18:58.71#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.231.08:18:58.71#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.231.08:18:58.71#ibcon#ireg 7 cls_cnt 0 2006.231.08:18:58.71#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:18:58.83#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:18:58.83#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:18:58.83#ibcon#enter wrdev, iclass 22, count 0 2006.231.08:18:58.83#ibcon#first serial, iclass 22, count 0 2006.231.08:18:58.83#ibcon#enter sib2, iclass 22, count 0 2006.231.08:18:58.83#ibcon#flushed, iclass 22, count 0 2006.231.08:18:58.83#ibcon#about to write, iclass 22, count 0 2006.231.08:18:58.83#ibcon#wrote, iclass 22, count 0 2006.231.08:18:58.83#ibcon#about to read 3, iclass 22, count 0 2006.231.08:18:58.85#ibcon#read 3, iclass 22, count 0 2006.231.08:18:58.85#ibcon#about to read 4, iclass 22, count 0 2006.231.08:18:58.85#ibcon#read 4, iclass 22, count 0 2006.231.08:18:58.85#ibcon#about to read 5, iclass 22, count 0 2006.231.08:18:58.85#ibcon#read 5, iclass 22, count 0 2006.231.08:18:58.85#ibcon#about to read 6, iclass 22, count 0 2006.231.08:18:58.85#ibcon#read 6, iclass 22, count 0 2006.231.08:18:58.85#ibcon#end of sib2, iclass 22, count 0 2006.231.08:18:58.85#ibcon#*mode == 0, iclass 22, count 0 2006.231.08:18:58.85#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.08:18:58.85#ibcon#[25=USB\r\n] 2006.231.08:18:58.85#ibcon#*before write, iclass 22, count 0 2006.231.08:18:58.85#ibcon#enter sib2, iclass 22, count 0 2006.231.08:18:58.85#ibcon#flushed, iclass 22, count 0 2006.231.08:18:58.85#ibcon#about to write, iclass 22, count 0 2006.231.08:18:58.85#ibcon#wrote, iclass 22, count 0 2006.231.08:18:58.85#ibcon#about to read 3, iclass 22, count 0 2006.231.08:18:58.88#ibcon#read 3, iclass 22, count 0 2006.231.08:18:58.88#ibcon#about to read 4, iclass 22, count 0 2006.231.08:18:58.88#ibcon#read 4, iclass 22, count 0 2006.231.08:18:58.88#ibcon#about to read 5, iclass 22, count 0 2006.231.08:18:58.88#ibcon#read 5, iclass 22, count 0 2006.231.08:18:58.88#ibcon#about to read 6, iclass 22, count 0 2006.231.08:18:58.88#ibcon#read 6, iclass 22, count 0 2006.231.08:18:58.88#ibcon#end of sib2, iclass 22, count 0 2006.231.08:18:58.88#ibcon#*after write, iclass 22, count 0 2006.231.08:18:58.88#ibcon#*before return 0, iclass 22, count 0 2006.231.08:18:58.88#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:18:58.88#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.231.08:18:58.88#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.08:18:58.88#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.08:18:58.88$vc4f8/valo=4,832.99 2006.231.08:18:58.88#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.231.08:18:58.88#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.231.08:18:58.88#ibcon#ireg 17 cls_cnt 0 2006.231.08:18:58.88#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:18:58.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:18:58.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:18:58.88#ibcon#enter wrdev, iclass 24, count 0 2006.231.08:18:58.88#ibcon#first serial, iclass 24, count 0 2006.231.08:18:58.88#ibcon#enter sib2, iclass 24, count 0 2006.231.08:18:58.88#ibcon#flushed, iclass 24, count 0 2006.231.08:18:58.88#ibcon#about to write, iclass 24, count 0 2006.231.08:18:58.88#ibcon#wrote, iclass 24, count 0 2006.231.08:18:58.88#ibcon#about to read 3, iclass 24, count 0 2006.231.08:18:58.91#ibcon#read 3, iclass 24, count 0 2006.231.08:18:58.91#ibcon#about to read 4, iclass 24, count 0 2006.231.08:18:58.91#ibcon#read 4, iclass 24, count 0 2006.231.08:18:58.91#ibcon#about to read 5, iclass 24, count 0 2006.231.08:18:58.91#ibcon#read 5, iclass 24, count 0 2006.231.08:18:58.91#ibcon#about to read 6, iclass 24, count 0 2006.231.08:18:58.91#ibcon#read 6, iclass 24, count 0 2006.231.08:18:58.91#ibcon#end of sib2, iclass 24, count 0 2006.231.08:18:58.91#ibcon#*mode == 0, iclass 24, count 0 2006.231.08:18:58.91#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.08:18:58.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:18:58.91#ibcon#*before write, iclass 24, count 0 2006.231.08:18:58.91#ibcon#enter sib2, iclass 24, count 0 2006.231.08:18:58.91#ibcon#flushed, iclass 24, count 0 2006.231.08:18:58.91#ibcon#about to write, iclass 24, count 0 2006.231.08:18:58.91#ibcon#wrote, iclass 24, count 0 2006.231.08:18:58.91#ibcon#about to read 3, iclass 24, count 0 2006.231.08:18:58.95#ibcon#read 3, iclass 24, count 0 2006.231.08:18:58.95#ibcon#about to read 4, iclass 24, count 0 2006.231.08:18:58.95#ibcon#read 4, iclass 24, count 0 2006.231.08:18:58.95#ibcon#about to read 5, iclass 24, count 0 2006.231.08:18:58.95#ibcon#read 5, iclass 24, count 0 2006.231.08:18:58.95#ibcon#about to read 6, iclass 24, count 0 2006.231.08:18:58.95#ibcon#read 6, iclass 24, count 0 2006.231.08:18:58.95#ibcon#end of sib2, iclass 24, count 0 2006.231.08:18:58.95#ibcon#*after write, iclass 24, count 0 2006.231.08:18:58.95#ibcon#*before return 0, iclass 24, count 0 2006.231.08:18:58.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:18:58.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:18:58.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.08:18:58.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.08:18:58.95$vc4f8/va=4,7 2006.231.08:18:58.95#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.231.08:18:58.95#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.231.08:18:58.95#ibcon#ireg 11 cls_cnt 2 2006.231.08:18:58.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:18:59.00#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:18:59.00#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:18:59.00#ibcon#enter wrdev, iclass 26, count 2 2006.231.08:18:59.00#ibcon#first serial, iclass 26, count 2 2006.231.08:18:59.00#ibcon#enter sib2, iclass 26, count 2 2006.231.08:18:59.00#ibcon#flushed, iclass 26, count 2 2006.231.08:18:59.00#ibcon#about to write, iclass 26, count 2 2006.231.08:18:59.00#ibcon#wrote, iclass 26, count 2 2006.231.08:18:59.00#ibcon#about to read 3, iclass 26, count 2 2006.231.08:18:59.02#ibcon#read 3, iclass 26, count 2 2006.231.08:18:59.02#ibcon#about to read 4, iclass 26, count 2 2006.231.08:18:59.02#ibcon#read 4, iclass 26, count 2 2006.231.08:18:59.02#ibcon#about to read 5, iclass 26, count 2 2006.231.08:18:59.02#ibcon#read 5, iclass 26, count 2 2006.231.08:18:59.02#ibcon#about to read 6, iclass 26, count 2 2006.231.08:18:59.02#ibcon#read 6, iclass 26, count 2 2006.231.08:18:59.02#ibcon#end of sib2, iclass 26, count 2 2006.231.08:18:59.02#ibcon#*mode == 0, iclass 26, count 2 2006.231.08:18:59.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.231.08:18:59.02#ibcon#[25=AT04-07\r\n] 2006.231.08:18:59.02#ibcon#*before write, iclass 26, count 2 2006.231.08:18:59.02#ibcon#enter sib2, iclass 26, count 2 2006.231.08:18:59.02#ibcon#flushed, iclass 26, count 2 2006.231.08:18:59.02#ibcon#about to write, iclass 26, count 2 2006.231.08:18:59.02#ibcon#wrote, iclass 26, count 2 2006.231.08:18:59.02#ibcon#about to read 3, iclass 26, count 2 2006.231.08:18:59.05#ibcon#read 3, iclass 26, count 2 2006.231.08:18:59.05#ibcon#about to read 4, iclass 26, count 2 2006.231.08:18:59.05#ibcon#read 4, iclass 26, count 2 2006.231.08:18:59.05#ibcon#about to read 5, iclass 26, count 2 2006.231.08:18:59.05#ibcon#read 5, iclass 26, count 2 2006.231.08:18:59.05#ibcon#about to read 6, iclass 26, count 2 2006.231.08:18:59.05#ibcon#read 6, iclass 26, count 2 2006.231.08:18:59.05#ibcon#end of sib2, iclass 26, count 2 2006.231.08:18:59.05#ibcon#*after write, iclass 26, count 2 2006.231.08:18:59.05#ibcon#*before return 0, iclass 26, count 2 2006.231.08:18:59.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:18:59.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:18:59.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.231.08:18:59.05#ibcon#ireg 7 cls_cnt 0 2006.231.08:18:59.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:18:59.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:18:59.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:18:59.17#ibcon#enter wrdev, iclass 26, count 0 2006.231.08:18:59.17#ibcon#first serial, iclass 26, count 0 2006.231.08:18:59.17#ibcon#enter sib2, iclass 26, count 0 2006.231.08:18:59.17#ibcon#flushed, iclass 26, count 0 2006.231.08:18:59.17#ibcon#about to write, iclass 26, count 0 2006.231.08:18:59.17#ibcon#wrote, iclass 26, count 0 2006.231.08:18:59.17#ibcon#about to read 3, iclass 26, count 0 2006.231.08:18:59.19#ibcon#read 3, iclass 26, count 0 2006.231.08:18:59.19#ibcon#about to read 4, iclass 26, count 0 2006.231.08:18:59.19#ibcon#read 4, iclass 26, count 0 2006.231.08:18:59.19#ibcon#about to read 5, iclass 26, count 0 2006.231.08:18:59.19#ibcon#read 5, iclass 26, count 0 2006.231.08:18:59.19#ibcon#about to read 6, iclass 26, count 0 2006.231.08:18:59.19#ibcon#read 6, iclass 26, count 0 2006.231.08:18:59.19#ibcon#end of sib2, iclass 26, count 0 2006.231.08:18:59.19#ibcon#*mode == 0, iclass 26, count 0 2006.231.08:18:59.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.08:18:59.19#ibcon#[25=USB\r\n] 2006.231.08:18:59.19#ibcon#*before write, iclass 26, count 0 2006.231.08:18:59.19#ibcon#enter sib2, iclass 26, count 0 2006.231.08:18:59.19#ibcon#flushed, iclass 26, count 0 2006.231.08:18:59.19#ibcon#about to write, iclass 26, count 0 2006.231.08:18:59.19#ibcon#wrote, iclass 26, count 0 2006.231.08:18:59.19#ibcon#about to read 3, iclass 26, count 0 2006.231.08:18:59.22#ibcon#read 3, iclass 26, count 0 2006.231.08:18:59.22#ibcon#about to read 4, iclass 26, count 0 2006.231.08:18:59.22#ibcon#read 4, iclass 26, count 0 2006.231.08:18:59.22#ibcon#about to read 5, iclass 26, count 0 2006.231.08:18:59.22#ibcon#read 5, iclass 26, count 0 2006.231.08:18:59.22#ibcon#about to read 6, iclass 26, count 0 2006.231.08:18:59.22#ibcon#read 6, iclass 26, count 0 2006.231.08:18:59.22#ibcon#end of sib2, iclass 26, count 0 2006.231.08:18:59.22#ibcon#*after write, iclass 26, count 0 2006.231.08:18:59.22#ibcon#*before return 0, iclass 26, count 0 2006.231.08:18:59.22#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:18:59.22#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:18:59.22#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.08:18:59.22#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.08:18:59.22$vc4f8/valo=5,652.99 2006.231.08:18:59.22#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.231.08:18:59.22#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.231.08:18:59.22#ibcon#ireg 17 cls_cnt 0 2006.231.08:18:59.22#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:18:59.22#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:18:59.22#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:18:59.22#ibcon#enter wrdev, iclass 28, count 0 2006.231.08:18:59.22#ibcon#first serial, iclass 28, count 0 2006.231.08:18:59.22#ibcon#enter sib2, iclass 28, count 0 2006.231.08:18:59.22#ibcon#flushed, iclass 28, count 0 2006.231.08:18:59.22#ibcon#about to write, iclass 28, count 0 2006.231.08:18:59.22#ibcon#wrote, iclass 28, count 0 2006.231.08:18:59.22#ibcon#about to read 3, iclass 28, count 0 2006.231.08:18:59.24#ibcon#read 3, iclass 28, count 0 2006.231.08:18:59.24#ibcon#about to read 4, iclass 28, count 0 2006.231.08:18:59.24#ibcon#read 4, iclass 28, count 0 2006.231.08:18:59.24#ibcon#about to read 5, iclass 28, count 0 2006.231.08:18:59.24#ibcon#read 5, iclass 28, count 0 2006.231.08:18:59.24#ibcon#about to read 6, iclass 28, count 0 2006.231.08:18:59.24#ibcon#read 6, iclass 28, count 0 2006.231.08:18:59.24#ibcon#end of sib2, iclass 28, count 0 2006.231.08:18:59.24#ibcon#*mode == 0, iclass 28, count 0 2006.231.08:18:59.24#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.08:18:59.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:18:59.24#ibcon#*before write, iclass 28, count 0 2006.231.08:18:59.24#ibcon#enter sib2, iclass 28, count 0 2006.231.08:18:59.24#ibcon#flushed, iclass 28, count 0 2006.231.08:18:59.24#ibcon#about to write, iclass 28, count 0 2006.231.08:18:59.24#ibcon#wrote, iclass 28, count 0 2006.231.08:18:59.24#ibcon#about to read 3, iclass 28, count 0 2006.231.08:18:59.28#ibcon#read 3, iclass 28, count 0 2006.231.08:18:59.28#ibcon#about to read 4, iclass 28, count 0 2006.231.08:18:59.28#ibcon#read 4, iclass 28, count 0 2006.231.08:18:59.28#ibcon#about to read 5, iclass 28, count 0 2006.231.08:18:59.28#ibcon#read 5, iclass 28, count 0 2006.231.08:18:59.28#ibcon#about to read 6, iclass 28, count 0 2006.231.08:18:59.28#ibcon#read 6, iclass 28, count 0 2006.231.08:18:59.28#ibcon#end of sib2, iclass 28, count 0 2006.231.08:18:59.28#ibcon#*after write, iclass 28, count 0 2006.231.08:18:59.28#ibcon#*before return 0, iclass 28, count 0 2006.231.08:18:59.28#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:18:59.28#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:18:59.28#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.08:18:59.28#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.08:18:59.28$vc4f8/va=5,7 2006.231.08:18:59.28#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.08:18:59.28#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.08:18:59.28#ibcon#ireg 11 cls_cnt 2 2006.231.08:18:59.28#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:18:59.34#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:18:59.34#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:18:59.34#ibcon#enter wrdev, iclass 30, count 2 2006.231.08:18:59.34#ibcon#first serial, iclass 30, count 2 2006.231.08:18:59.34#ibcon#enter sib2, iclass 30, count 2 2006.231.08:18:59.34#ibcon#flushed, iclass 30, count 2 2006.231.08:18:59.34#ibcon#about to write, iclass 30, count 2 2006.231.08:18:59.34#ibcon#wrote, iclass 30, count 2 2006.231.08:18:59.34#ibcon#about to read 3, iclass 30, count 2 2006.231.08:18:59.36#ibcon#read 3, iclass 30, count 2 2006.231.08:18:59.36#ibcon#about to read 4, iclass 30, count 2 2006.231.08:18:59.36#ibcon#read 4, iclass 30, count 2 2006.231.08:18:59.36#ibcon#about to read 5, iclass 30, count 2 2006.231.08:18:59.36#ibcon#read 5, iclass 30, count 2 2006.231.08:18:59.36#ibcon#about to read 6, iclass 30, count 2 2006.231.08:18:59.36#ibcon#read 6, iclass 30, count 2 2006.231.08:18:59.36#ibcon#end of sib2, iclass 30, count 2 2006.231.08:18:59.36#ibcon#*mode == 0, iclass 30, count 2 2006.231.08:18:59.36#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.08:18:59.36#ibcon#[25=AT05-07\r\n] 2006.231.08:18:59.36#ibcon#*before write, iclass 30, count 2 2006.231.08:18:59.36#ibcon#enter sib2, iclass 30, count 2 2006.231.08:18:59.36#ibcon#flushed, iclass 30, count 2 2006.231.08:18:59.36#ibcon#about to write, iclass 30, count 2 2006.231.08:18:59.36#ibcon#wrote, iclass 30, count 2 2006.231.08:18:59.36#ibcon#about to read 3, iclass 30, count 2 2006.231.08:18:59.39#ibcon#read 3, iclass 30, count 2 2006.231.08:18:59.39#ibcon#about to read 4, iclass 30, count 2 2006.231.08:18:59.39#ibcon#read 4, iclass 30, count 2 2006.231.08:18:59.39#ibcon#about to read 5, iclass 30, count 2 2006.231.08:18:59.39#ibcon#read 5, iclass 30, count 2 2006.231.08:18:59.39#ibcon#about to read 6, iclass 30, count 2 2006.231.08:18:59.39#ibcon#read 6, iclass 30, count 2 2006.231.08:18:59.39#ibcon#end of sib2, iclass 30, count 2 2006.231.08:18:59.39#ibcon#*after write, iclass 30, count 2 2006.231.08:18:59.39#ibcon#*before return 0, iclass 30, count 2 2006.231.08:18:59.39#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:18:59.39#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:18:59.39#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.08:18:59.39#ibcon#ireg 7 cls_cnt 0 2006.231.08:18:59.39#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:18:59.51#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:18:59.51#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:18:59.51#ibcon#enter wrdev, iclass 30, count 0 2006.231.08:18:59.51#ibcon#first serial, iclass 30, count 0 2006.231.08:18:59.51#ibcon#enter sib2, iclass 30, count 0 2006.231.08:18:59.51#ibcon#flushed, iclass 30, count 0 2006.231.08:18:59.51#ibcon#about to write, iclass 30, count 0 2006.231.08:18:59.51#ibcon#wrote, iclass 30, count 0 2006.231.08:18:59.51#ibcon#about to read 3, iclass 30, count 0 2006.231.08:18:59.53#ibcon#read 3, iclass 30, count 0 2006.231.08:18:59.53#ibcon#about to read 4, iclass 30, count 0 2006.231.08:18:59.53#ibcon#read 4, iclass 30, count 0 2006.231.08:18:59.53#ibcon#about to read 5, iclass 30, count 0 2006.231.08:18:59.53#ibcon#read 5, iclass 30, count 0 2006.231.08:18:59.53#ibcon#about to read 6, iclass 30, count 0 2006.231.08:18:59.53#ibcon#read 6, iclass 30, count 0 2006.231.08:18:59.53#ibcon#end of sib2, iclass 30, count 0 2006.231.08:18:59.53#ibcon#*mode == 0, iclass 30, count 0 2006.231.08:18:59.53#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.08:18:59.53#ibcon#[25=USB\r\n] 2006.231.08:18:59.53#ibcon#*before write, iclass 30, count 0 2006.231.08:18:59.53#ibcon#enter sib2, iclass 30, count 0 2006.231.08:18:59.53#ibcon#flushed, iclass 30, count 0 2006.231.08:18:59.53#ibcon#about to write, iclass 30, count 0 2006.231.08:18:59.53#ibcon#wrote, iclass 30, count 0 2006.231.08:18:59.53#ibcon#about to read 3, iclass 30, count 0 2006.231.08:18:59.56#ibcon#read 3, iclass 30, count 0 2006.231.08:18:59.56#ibcon#about to read 4, iclass 30, count 0 2006.231.08:18:59.56#ibcon#read 4, iclass 30, count 0 2006.231.08:18:59.56#ibcon#about to read 5, iclass 30, count 0 2006.231.08:18:59.56#ibcon#read 5, iclass 30, count 0 2006.231.08:18:59.56#ibcon#about to read 6, iclass 30, count 0 2006.231.08:18:59.56#ibcon#read 6, iclass 30, count 0 2006.231.08:18:59.56#ibcon#end of sib2, iclass 30, count 0 2006.231.08:18:59.56#ibcon#*after write, iclass 30, count 0 2006.231.08:18:59.56#ibcon#*before return 0, iclass 30, count 0 2006.231.08:18:59.56#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:18:59.56#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:18:59.56#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.08:18:59.56#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.08:18:59.56$vc4f8/valo=6,772.99 2006.231.08:18:59.56#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.08:18:59.56#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.08:18:59.56#ibcon#ireg 17 cls_cnt 0 2006.231.08:18:59.56#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:18:59.56#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:18:59.56#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:18:59.56#ibcon#enter wrdev, iclass 32, count 0 2006.231.08:18:59.56#ibcon#first serial, iclass 32, count 0 2006.231.08:18:59.56#ibcon#enter sib2, iclass 32, count 0 2006.231.08:18:59.56#ibcon#flushed, iclass 32, count 0 2006.231.08:18:59.56#ibcon#about to write, iclass 32, count 0 2006.231.08:18:59.56#ibcon#wrote, iclass 32, count 0 2006.231.08:18:59.56#ibcon#about to read 3, iclass 32, count 0 2006.231.08:18:59.59#ibcon#read 3, iclass 32, count 0 2006.231.08:18:59.59#ibcon#about to read 4, iclass 32, count 0 2006.231.08:18:59.59#ibcon#read 4, iclass 32, count 0 2006.231.08:18:59.59#ibcon#about to read 5, iclass 32, count 0 2006.231.08:18:59.59#ibcon#read 5, iclass 32, count 0 2006.231.08:18:59.59#ibcon#about to read 6, iclass 32, count 0 2006.231.08:18:59.59#ibcon#read 6, iclass 32, count 0 2006.231.08:18:59.59#ibcon#end of sib2, iclass 32, count 0 2006.231.08:18:59.59#ibcon#*mode == 0, iclass 32, count 0 2006.231.08:18:59.59#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.08:18:59.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:18:59.59#ibcon#*before write, iclass 32, count 0 2006.231.08:18:59.59#ibcon#enter sib2, iclass 32, count 0 2006.231.08:18:59.59#ibcon#flushed, iclass 32, count 0 2006.231.08:18:59.59#ibcon#about to write, iclass 32, count 0 2006.231.08:18:59.59#ibcon#wrote, iclass 32, count 0 2006.231.08:18:59.59#ibcon#about to read 3, iclass 32, count 0 2006.231.08:18:59.63#ibcon#read 3, iclass 32, count 0 2006.231.08:18:59.63#ibcon#about to read 4, iclass 32, count 0 2006.231.08:18:59.63#ibcon#read 4, iclass 32, count 0 2006.231.08:18:59.63#ibcon#about to read 5, iclass 32, count 0 2006.231.08:18:59.63#ibcon#read 5, iclass 32, count 0 2006.231.08:18:59.63#ibcon#about to read 6, iclass 32, count 0 2006.231.08:18:59.63#ibcon#read 6, iclass 32, count 0 2006.231.08:18:59.63#ibcon#end of sib2, iclass 32, count 0 2006.231.08:18:59.63#ibcon#*after write, iclass 32, count 0 2006.231.08:18:59.63#ibcon#*before return 0, iclass 32, count 0 2006.231.08:18:59.63#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:18:59.63#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:18:59.63#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.08:18:59.63#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.08:18:59.63$vc4f8/va=6,6 2006.231.08:18:59.63#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.08:18:59.63#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.08:18:59.63#ibcon#ireg 11 cls_cnt 2 2006.231.08:18:59.63#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:18:59.68#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:18:59.68#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:18:59.68#ibcon#enter wrdev, iclass 34, count 2 2006.231.08:18:59.68#ibcon#first serial, iclass 34, count 2 2006.231.08:18:59.68#ibcon#enter sib2, iclass 34, count 2 2006.231.08:18:59.68#ibcon#flushed, iclass 34, count 2 2006.231.08:18:59.68#ibcon#about to write, iclass 34, count 2 2006.231.08:18:59.68#ibcon#wrote, iclass 34, count 2 2006.231.08:18:59.68#ibcon#about to read 3, iclass 34, count 2 2006.231.08:18:59.70#ibcon#read 3, iclass 34, count 2 2006.231.08:18:59.70#ibcon#about to read 4, iclass 34, count 2 2006.231.08:18:59.70#ibcon#read 4, iclass 34, count 2 2006.231.08:18:59.70#ibcon#about to read 5, iclass 34, count 2 2006.231.08:18:59.70#ibcon#read 5, iclass 34, count 2 2006.231.08:18:59.70#ibcon#about to read 6, iclass 34, count 2 2006.231.08:18:59.70#ibcon#read 6, iclass 34, count 2 2006.231.08:18:59.70#ibcon#end of sib2, iclass 34, count 2 2006.231.08:18:59.70#ibcon#*mode == 0, iclass 34, count 2 2006.231.08:18:59.70#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.08:18:59.70#ibcon#[25=AT06-06\r\n] 2006.231.08:18:59.70#ibcon#*before write, iclass 34, count 2 2006.231.08:18:59.70#ibcon#enter sib2, iclass 34, count 2 2006.231.08:18:59.70#ibcon#flushed, iclass 34, count 2 2006.231.08:18:59.70#ibcon#about to write, iclass 34, count 2 2006.231.08:18:59.70#ibcon#wrote, iclass 34, count 2 2006.231.08:18:59.70#ibcon#about to read 3, iclass 34, count 2 2006.231.08:18:59.73#ibcon#read 3, iclass 34, count 2 2006.231.08:18:59.73#ibcon#about to read 4, iclass 34, count 2 2006.231.08:18:59.73#ibcon#read 4, iclass 34, count 2 2006.231.08:18:59.73#ibcon#about to read 5, iclass 34, count 2 2006.231.08:18:59.73#ibcon#read 5, iclass 34, count 2 2006.231.08:18:59.73#ibcon#about to read 6, iclass 34, count 2 2006.231.08:18:59.73#ibcon#read 6, iclass 34, count 2 2006.231.08:18:59.73#ibcon#end of sib2, iclass 34, count 2 2006.231.08:18:59.73#ibcon#*after write, iclass 34, count 2 2006.231.08:18:59.73#ibcon#*before return 0, iclass 34, count 2 2006.231.08:18:59.73#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:18:59.73#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:18:59.73#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.08:18:59.73#ibcon#ireg 7 cls_cnt 0 2006.231.08:18:59.73#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:18:59.85#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:18:59.85#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:18:59.85#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:18:59.85#ibcon#first serial, iclass 34, count 0 2006.231.08:18:59.85#ibcon#enter sib2, iclass 34, count 0 2006.231.08:18:59.85#ibcon#flushed, iclass 34, count 0 2006.231.08:18:59.85#ibcon#about to write, iclass 34, count 0 2006.231.08:18:59.85#ibcon#wrote, iclass 34, count 0 2006.231.08:18:59.85#ibcon#about to read 3, iclass 34, count 0 2006.231.08:18:59.87#ibcon#read 3, iclass 34, count 0 2006.231.08:18:59.87#ibcon#about to read 4, iclass 34, count 0 2006.231.08:18:59.87#ibcon#read 4, iclass 34, count 0 2006.231.08:18:59.87#ibcon#about to read 5, iclass 34, count 0 2006.231.08:18:59.87#ibcon#read 5, iclass 34, count 0 2006.231.08:18:59.87#ibcon#about to read 6, iclass 34, count 0 2006.231.08:18:59.87#ibcon#read 6, iclass 34, count 0 2006.231.08:18:59.87#ibcon#end of sib2, iclass 34, count 0 2006.231.08:18:59.87#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:18:59.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:18:59.87#ibcon#[25=USB\r\n] 2006.231.08:18:59.87#ibcon#*before write, iclass 34, count 0 2006.231.08:18:59.87#ibcon#enter sib2, iclass 34, count 0 2006.231.08:18:59.87#ibcon#flushed, iclass 34, count 0 2006.231.08:18:59.87#ibcon#about to write, iclass 34, count 0 2006.231.08:18:59.87#ibcon#wrote, iclass 34, count 0 2006.231.08:18:59.87#ibcon#about to read 3, iclass 34, count 0 2006.231.08:18:59.90#ibcon#read 3, iclass 34, count 0 2006.231.08:18:59.90#ibcon#about to read 4, iclass 34, count 0 2006.231.08:18:59.90#ibcon#read 4, iclass 34, count 0 2006.231.08:18:59.90#ibcon#about to read 5, iclass 34, count 0 2006.231.08:18:59.90#ibcon#read 5, iclass 34, count 0 2006.231.08:18:59.90#ibcon#about to read 6, iclass 34, count 0 2006.231.08:18:59.90#ibcon#read 6, iclass 34, count 0 2006.231.08:18:59.90#ibcon#end of sib2, iclass 34, count 0 2006.231.08:18:59.90#ibcon#*after write, iclass 34, count 0 2006.231.08:18:59.90#ibcon#*before return 0, iclass 34, count 0 2006.231.08:18:59.90#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:18:59.90#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:18:59.90#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:18:59.90#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:18:59.90$vc4f8/valo=7,832.99 2006.231.08:18:59.90#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.08:18:59.90#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.08:18:59.90#ibcon#ireg 17 cls_cnt 0 2006.231.08:18:59.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:18:59.90#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:18:59.90#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:18:59.90#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:18:59.90#ibcon#first serial, iclass 36, count 0 2006.231.08:18:59.90#ibcon#enter sib2, iclass 36, count 0 2006.231.08:18:59.90#ibcon#flushed, iclass 36, count 0 2006.231.08:18:59.90#ibcon#about to write, iclass 36, count 0 2006.231.08:18:59.90#ibcon#wrote, iclass 36, count 0 2006.231.08:18:59.90#ibcon#about to read 3, iclass 36, count 0 2006.231.08:18:59.92#ibcon#read 3, iclass 36, count 0 2006.231.08:18:59.92#ibcon#about to read 4, iclass 36, count 0 2006.231.08:18:59.92#ibcon#read 4, iclass 36, count 0 2006.231.08:18:59.92#ibcon#about to read 5, iclass 36, count 0 2006.231.08:18:59.92#ibcon#read 5, iclass 36, count 0 2006.231.08:18:59.92#ibcon#about to read 6, iclass 36, count 0 2006.231.08:18:59.92#ibcon#read 6, iclass 36, count 0 2006.231.08:18:59.92#ibcon#end of sib2, iclass 36, count 0 2006.231.08:18:59.92#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:18:59.92#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:18:59.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:18:59.92#ibcon#*before write, iclass 36, count 0 2006.231.08:18:59.92#ibcon#enter sib2, iclass 36, count 0 2006.231.08:18:59.92#ibcon#flushed, iclass 36, count 0 2006.231.08:18:59.92#ibcon#about to write, iclass 36, count 0 2006.231.08:18:59.92#ibcon#wrote, iclass 36, count 0 2006.231.08:18:59.92#ibcon#about to read 3, iclass 36, count 0 2006.231.08:18:59.96#ibcon#read 3, iclass 36, count 0 2006.231.08:18:59.96#ibcon#about to read 4, iclass 36, count 0 2006.231.08:18:59.96#ibcon#read 4, iclass 36, count 0 2006.231.08:18:59.96#ibcon#about to read 5, iclass 36, count 0 2006.231.08:18:59.96#ibcon#read 5, iclass 36, count 0 2006.231.08:18:59.96#ibcon#about to read 6, iclass 36, count 0 2006.231.08:18:59.96#ibcon#read 6, iclass 36, count 0 2006.231.08:18:59.96#ibcon#end of sib2, iclass 36, count 0 2006.231.08:18:59.96#ibcon#*after write, iclass 36, count 0 2006.231.08:18:59.96#ibcon#*before return 0, iclass 36, count 0 2006.231.08:18:59.96#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:18:59.96#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:18:59.96#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:18:59.96#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:18:59.96$vc4f8/va=7,6 2006.231.08:18:59.96#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.231.08:18:59.96#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.231.08:18:59.96#ibcon#ireg 11 cls_cnt 2 2006.231.08:18:59.96#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:19:00.02#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:19:00.02#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:19:00.02#ibcon#enter wrdev, iclass 38, count 2 2006.231.08:19:00.02#ibcon#first serial, iclass 38, count 2 2006.231.08:19:00.02#ibcon#enter sib2, iclass 38, count 2 2006.231.08:19:00.02#ibcon#flushed, iclass 38, count 2 2006.231.08:19:00.02#ibcon#about to write, iclass 38, count 2 2006.231.08:19:00.02#ibcon#wrote, iclass 38, count 2 2006.231.08:19:00.02#ibcon#about to read 3, iclass 38, count 2 2006.231.08:19:00.04#ibcon#read 3, iclass 38, count 2 2006.231.08:19:00.04#ibcon#about to read 4, iclass 38, count 2 2006.231.08:19:00.04#ibcon#read 4, iclass 38, count 2 2006.231.08:19:00.04#ibcon#about to read 5, iclass 38, count 2 2006.231.08:19:00.04#ibcon#read 5, iclass 38, count 2 2006.231.08:19:00.04#ibcon#about to read 6, iclass 38, count 2 2006.231.08:19:00.04#ibcon#read 6, iclass 38, count 2 2006.231.08:19:00.04#ibcon#end of sib2, iclass 38, count 2 2006.231.08:19:00.04#ibcon#*mode == 0, iclass 38, count 2 2006.231.08:19:00.04#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.231.08:19:00.04#ibcon#[25=AT07-06\r\n] 2006.231.08:19:00.04#ibcon#*before write, iclass 38, count 2 2006.231.08:19:00.04#ibcon#enter sib2, iclass 38, count 2 2006.231.08:19:00.04#ibcon#flushed, iclass 38, count 2 2006.231.08:19:00.04#ibcon#about to write, iclass 38, count 2 2006.231.08:19:00.04#ibcon#wrote, iclass 38, count 2 2006.231.08:19:00.04#ibcon#about to read 3, iclass 38, count 2 2006.231.08:19:00.07#ibcon#read 3, iclass 38, count 2 2006.231.08:19:00.07#ibcon#about to read 4, iclass 38, count 2 2006.231.08:19:00.07#ibcon#read 4, iclass 38, count 2 2006.231.08:19:00.07#ibcon#about to read 5, iclass 38, count 2 2006.231.08:19:00.07#ibcon#read 5, iclass 38, count 2 2006.231.08:19:00.07#ibcon#about to read 6, iclass 38, count 2 2006.231.08:19:00.07#ibcon#read 6, iclass 38, count 2 2006.231.08:19:00.07#ibcon#end of sib2, iclass 38, count 2 2006.231.08:19:00.07#ibcon#*after write, iclass 38, count 2 2006.231.08:19:00.07#ibcon#*before return 0, iclass 38, count 2 2006.231.08:19:00.07#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:19:00.07#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.231.08:19:00.07#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.231.08:19:00.07#ibcon#ireg 7 cls_cnt 0 2006.231.08:19:00.07#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:19:00.19#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:19:00.19#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:19:00.19#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:19:00.19#ibcon#first serial, iclass 38, count 0 2006.231.08:19:00.19#ibcon#enter sib2, iclass 38, count 0 2006.231.08:19:00.19#ibcon#flushed, iclass 38, count 0 2006.231.08:19:00.19#ibcon#about to write, iclass 38, count 0 2006.231.08:19:00.19#ibcon#wrote, iclass 38, count 0 2006.231.08:19:00.19#ibcon#about to read 3, iclass 38, count 0 2006.231.08:19:00.21#ibcon#read 3, iclass 38, count 0 2006.231.08:19:00.21#ibcon#about to read 4, iclass 38, count 0 2006.231.08:19:00.21#ibcon#read 4, iclass 38, count 0 2006.231.08:19:00.21#ibcon#about to read 5, iclass 38, count 0 2006.231.08:19:00.21#ibcon#read 5, iclass 38, count 0 2006.231.08:19:00.21#ibcon#about to read 6, iclass 38, count 0 2006.231.08:19:00.21#ibcon#read 6, iclass 38, count 0 2006.231.08:19:00.21#ibcon#end of sib2, iclass 38, count 0 2006.231.08:19:00.21#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:19:00.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:19:00.21#ibcon#[25=USB\r\n] 2006.231.08:19:00.21#ibcon#*before write, iclass 38, count 0 2006.231.08:19:00.21#ibcon#enter sib2, iclass 38, count 0 2006.231.08:19:00.21#ibcon#flushed, iclass 38, count 0 2006.231.08:19:00.21#ibcon#about to write, iclass 38, count 0 2006.231.08:19:00.21#ibcon#wrote, iclass 38, count 0 2006.231.08:19:00.21#ibcon#about to read 3, iclass 38, count 0 2006.231.08:19:00.24#ibcon#read 3, iclass 38, count 0 2006.231.08:19:00.24#ibcon#about to read 4, iclass 38, count 0 2006.231.08:19:00.24#ibcon#read 4, iclass 38, count 0 2006.231.08:19:00.24#ibcon#about to read 5, iclass 38, count 0 2006.231.08:19:00.24#ibcon#read 5, iclass 38, count 0 2006.231.08:19:00.24#ibcon#about to read 6, iclass 38, count 0 2006.231.08:19:00.24#ibcon#read 6, iclass 38, count 0 2006.231.08:19:00.24#ibcon#end of sib2, iclass 38, count 0 2006.231.08:19:00.24#ibcon#*after write, iclass 38, count 0 2006.231.08:19:00.24#ibcon#*before return 0, iclass 38, count 0 2006.231.08:19:00.24#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:19:00.24#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.231.08:19:00.24#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:19:00.24#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:19:00.24$vc4f8/valo=8,852.99 2006.231.08:19:00.24#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.231.08:19:00.24#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.231.08:19:00.24#ibcon#ireg 17 cls_cnt 0 2006.231.08:19:00.24#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:19:00.24#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:19:00.24#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:19:00.24#ibcon#enter wrdev, iclass 40, count 0 2006.231.08:19:00.24#ibcon#first serial, iclass 40, count 0 2006.231.08:19:00.24#ibcon#enter sib2, iclass 40, count 0 2006.231.08:19:00.24#ibcon#flushed, iclass 40, count 0 2006.231.08:19:00.24#ibcon#about to write, iclass 40, count 0 2006.231.08:19:00.24#ibcon#wrote, iclass 40, count 0 2006.231.08:19:00.24#ibcon#about to read 3, iclass 40, count 0 2006.231.08:19:00.26#ibcon#read 3, iclass 40, count 0 2006.231.08:19:00.26#ibcon#about to read 4, iclass 40, count 0 2006.231.08:19:00.26#ibcon#read 4, iclass 40, count 0 2006.231.08:19:00.26#ibcon#about to read 5, iclass 40, count 0 2006.231.08:19:00.26#ibcon#read 5, iclass 40, count 0 2006.231.08:19:00.26#ibcon#about to read 6, iclass 40, count 0 2006.231.08:19:00.26#ibcon#read 6, iclass 40, count 0 2006.231.08:19:00.26#ibcon#end of sib2, iclass 40, count 0 2006.231.08:19:00.26#ibcon#*mode == 0, iclass 40, count 0 2006.231.08:19:00.26#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.08:19:00.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:19:00.26#ibcon#*before write, iclass 40, count 0 2006.231.08:19:00.26#ibcon#enter sib2, iclass 40, count 0 2006.231.08:19:00.26#ibcon#flushed, iclass 40, count 0 2006.231.08:19:00.26#ibcon#about to write, iclass 40, count 0 2006.231.08:19:00.26#ibcon#wrote, iclass 40, count 0 2006.231.08:19:00.26#ibcon#about to read 3, iclass 40, count 0 2006.231.08:19:00.30#ibcon#read 3, iclass 40, count 0 2006.231.08:19:00.30#ibcon#about to read 4, iclass 40, count 0 2006.231.08:19:00.30#ibcon#read 4, iclass 40, count 0 2006.231.08:19:00.30#ibcon#about to read 5, iclass 40, count 0 2006.231.08:19:00.30#ibcon#read 5, iclass 40, count 0 2006.231.08:19:00.30#ibcon#about to read 6, iclass 40, count 0 2006.231.08:19:00.30#ibcon#read 6, iclass 40, count 0 2006.231.08:19:00.30#ibcon#end of sib2, iclass 40, count 0 2006.231.08:19:00.30#ibcon#*after write, iclass 40, count 0 2006.231.08:19:00.30#ibcon#*before return 0, iclass 40, count 0 2006.231.08:19:00.30#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:19:00.30#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.231.08:19:00.30#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.08:19:00.30#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.08:19:00.30$vc4f8/va=8,6 2006.231.08:19:00.30#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.231.08:19:00.30#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.231.08:19:00.30#ibcon#ireg 11 cls_cnt 2 2006.231.08:19:00.30#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:19:00.36#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:19:00.36#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:19:00.36#ibcon#enter wrdev, iclass 4, count 2 2006.231.08:19:00.36#ibcon#first serial, iclass 4, count 2 2006.231.08:19:00.36#ibcon#enter sib2, iclass 4, count 2 2006.231.08:19:00.36#ibcon#flushed, iclass 4, count 2 2006.231.08:19:00.36#ibcon#about to write, iclass 4, count 2 2006.231.08:19:00.36#ibcon#wrote, iclass 4, count 2 2006.231.08:19:00.36#ibcon#about to read 3, iclass 4, count 2 2006.231.08:19:00.38#ibcon#read 3, iclass 4, count 2 2006.231.08:19:00.38#ibcon#about to read 4, iclass 4, count 2 2006.231.08:19:00.38#ibcon#read 4, iclass 4, count 2 2006.231.08:19:00.38#ibcon#about to read 5, iclass 4, count 2 2006.231.08:19:00.38#ibcon#read 5, iclass 4, count 2 2006.231.08:19:00.38#ibcon#about to read 6, iclass 4, count 2 2006.231.08:19:00.38#ibcon#read 6, iclass 4, count 2 2006.231.08:19:00.38#ibcon#end of sib2, iclass 4, count 2 2006.231.08:19:00.38#ibcon#*mode == 0, iclass 4, count 2 2006.231.08:19:00.38#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.231.08:19:00.38#ibcon#[25=AT08-06\r\n] 2006.231.08:19:00.38#ibcon#*before write, iclass 4, count 2 2006.231.08:19:00.38#ibcon#enter sib2, iclass 4, count 2 2006.231.08:19:00.38#ibcon#flushed, iclass 4, count 2 2006.231.08:19:00.38#ibcon#about to write, iclass 4, count 2 2006.231.08:19:00.38#ibcon#wrote, iclass 4, count 2 2006.231.08:19:00.38#ibcon#about to read 3, iclass 4, count 2 2006.231.08:19:00.41#ibcon#read 3, iclass 4, count 2 2006.231.08:19:00.41#ibcon#about to read 4, iclass 4, count 2 2006.231.08:19:00.41#ibcon#read 4, iclass 4, count 2 2006.231.08:19:00.41#ibcon#about to read 5, iclass 4, count 2 2006.231.08:19:00.41#ibcon#read 5, iclass 4, count 2 2006.231.08:19:00.41#ibcon#about to read 6, iclass 4, count 2 2006.231.08:19:00.41#ibcon#read 6, iclass 4, count 2 2006.231.08:19:00.41#ibcon#end of sib2, iclass 4, count 2 2006.231.08:19:00.41#ibcon#*after write, iclass 4, count 2 2006.231.08:19:00.41#ibcon#*before return 0, iclass 4, count 2 2006.231.08:19:00.41#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:19:00.41#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.231.08:19:00.41#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.231.08:19:00.41#ibcon#ireg 7 cls_cnt 0 2006.231.08:19:00.41#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:19:00.53#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:19:00.53#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:19:00.53#ibcon#enter wrdev, iclass 4, count 0 2006.231.08:19:00.53#ibcon#first serial, iclass 4, count 0 2006.231.08:19:00.53#ibcon#enter sib2, iclass 4, count 0 2006.231.08:19:00.53#ibcon#flushed, iclass 4, count 0 2006.231.08:19:00.53#ibcon#about to write, iclass 4, count 0 2006.231.08:19:00.53#ibcon#wrote, iclass 4, count 0 2006.231.08:19:00.53#ibcon#about to read 3, iclass 4, count 0 2006.231.08:19:00.55#ibcon#read 3, iclass 4, count 0 2006.231.08:19:00.55#ibcon#about to read 4, iclass 4, count 0 2006.231.08:19:00.55#ibcon#read 4, iclass 4, count 0 2006.231.08:19:00.55#ibcon#about to read 5, iclass 4, count 0 2006.231.08:19:00.55#ibcon#read 5, iclass 4, count 0 2006.231.08:19:00.55#ibcon#about to read 6, iclass 4, count 0 2006.231.08:19:00.55#ibcon#read 6, iclass 4, count 0 2006.231.08:19:00.55#ibcon#end of sib2, iclass 4, count 0 2006.231.08:19:00.55#ibcon#*mode == 0, iclass 4, count 0 2006.231.08:19:00.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.08:19:00.55#ibcon#[25=USB\r\n] 2006.231.08:19:00.55#ibcon#*before write, iclass 4, count 0 2006.231.08:19:00.55#ibcon#enter sib2, iclass 4, count 0 2006.231.08:19:00.55#ibcon#flushed, iclass 4, count 0 2006.231.08:19:00.55#ibcon#about to write, iclass 4, count 0 2006.231.08:19:00.55#ibcon#wrote, iclass 4, count 0 2006.231.08:19:00.55#ibcon#about to read 3, iclass 4, count 0 2006.231.08:19:00.58#ibcon#read 3, iclass 4, count 0 2006.231.08:19:00.58#ibcon#about to read 4, iclass 4, count 0 2006.231.08:19:00.58#ibcon#read 4, iclass 4, count 0 2006.231.08:19:00.58#ibcon#about to read 5, iclass 4, count 0 2006.231.08:19:00.58#ibcon#read 5, iclass 4, count 0 2006.231.08:19:00.58#ibcon#about to read 6, iclass 4, count 0 2006.231.08:19:00.58#ibcon#read 6, iclass 4, count 0 2006.231.08:19:00.58#ibcon#end of sib2, iclass 4, count 0 2006.231.08:19:00.58#ibcon#*after write, iclass 4, count 0 2006.231.08:19:00.58#ibcon#*before return 0, iclass 4, count 0 2006.231.08:19:00.58#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:19:00.58#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.231.08:19:00.58#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.08:19:00.58#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.08:19:00.58$vc4f8/vblo=1,632.99 2006.231.08:19:00.58#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.231.08:19:00.58#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.231.08:19:00.58#ibcon#ireg 17 cls_cnt 0 2006.231.08:19:00.58#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:19:00.58#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:19:00.58#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:19:00.58#ibcon#enter wrdev, iclass 6, count 0 2006.231.08:19:00.58#ibcon#first serial, iclass 6, count 0 2006.231.08:19:00.58#ibcon#enter sib2, iclass 6, count 0 2006.231.08:19:00.58#ibcon#flushed, iclass 6, count 0 2006.231.08:19:00.58#ibcon#about to write, iclass 6, count 0 2006.231.08:19:00.58#ibcon#wrote, iclass 6, count 0 2006.231.08:19:00.58#ibcon#about to read 3, iclass 6, count 0 2006.231.08:19:00.60#ibcon#read 3, iclass 6, count 0 2006.231.08:19:00.60#ibcon#about to read 4, iclass 6, count 0 2006.231.08:19:00.60#ibcon#read 4, iclass 6, count 0 2006.231.08:19:00.60#ibcon#about to read 5, iclass 6, count 0 2006.231.08:19:00.60#ibcon#read 5, iclass 6, count 0 2006.231.08:19:00.60#ibcon#about to read 6, iclass 6, count 0 2006.231.08:19:00.60#ibcon#read 6, iclass 6, count 0 2006.231.08:19:00.60#ibcon#end of sib2, iclass 6, count 0 2006.231.08:19:00.60#ibcon#*mode == 0, iclass 6, count 0 2006.231.08:19:00.60#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.08:19:00.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:19:00.60#ibcon#*before write, iclass 6, count 0 2006.231.08:19:00.60#ibcon#enter sib2, iclass 6, count 0 2006.231.08:19:00.60#ibcon#flushed, iclass 6, count 0 2006.231.08:19:00.60#ibcon#about to write, iclass 6, count 0 2006.231.08:19:00.60#ibcon#wrote, iclass 6, count 0 2006.231.08:19:00.60#ibcon#about to read 3, iclass 6, count 0 2006.231.08:19:00.64#ibcon#read 3, iclass 6, count 0 2006.231.08:19:00.64#ibcon#about to read 4, iclass 6, count 0 2006.231.08:19:00.64#ibcon#read 4, iclass 6, count 0 2006.231.08:19:00.64#ibcon#about to read 5, iclass 6, count 0 2006.231.08:19:00.64#ibcon#read 5, iclass 6, count 0 2006.231.08:19:00.64#ibcon#about to read 6, iclass 6, count 0 2006.231.08:19:00.64#ibcon#read 6, iclass 6, count 0 2006.231.08:19:00.64#ibcon#end of sib2, iclass 6, count 0 2006.231.08:19:00.64#ibcon#*after write, iclass 6, count 0 2006.231.08:19:00.64#ibcon#*before return 0, iclass 6, count 0 2006.231.08:19:00.64#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:19:00.64#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.231.08:19:00.64#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.08:19:00.64#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.08:19:00.64$vc4f8/vb=1,4 2006.231.08:19:00.64#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.231.08:19:00.64#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.231.08:19:00.64#ibcon#ireg 11 cls_cnt 2 2006.231.08:19:00.64#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:19:00.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:19:00.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:19:00.64#ibcon#enter wrdev, iclass 10, count 2 2006.231.08:19:00.64#ibcon#first serial, iclass 10, count 2 2006.231.08:19:00.64#ibcon#enter sib2, iclass 10, count 2 2006.231.08:19:00.64#ibcon#flushed, iclass 10, count 2 2006.231.08:19:00.64#ibcon#about to write, iclass 10, count 2 2006.231.08:19:00.64#ibcon#wrote, iclass 10, count 2 2006.231.08:19:00.64#ibcon#about to read 3, iclass 10, count 2 2006.231.08:19:00.66#ibcon#read 3, iclass 10, count 2 2006.231.08:19:00.66#ibcon#about to read 4, iclass 10, count 2 2006.231.08:19:00.66#ibcon#read 4, iclass 10, count 2 2006.231.08:19:00.66#ibcon#about to read 5, iclass 10, count 2 2006.231.08:19:00.66#ibcon#read 5, iclass 10, count 2 2006.231.08:19:00.66#ibcon#about to read 6, iclass 10, count 2 2006.231.08:19:00.66#ibcon#read 6, iclass 10, count 2 2006.231.08:19:00.66#ibcon#end of sib2, iclass 10, count 2 2006.231.08:19:00.66#ibcon#*mode == 0, iclass 10, count 2 2006.231.08:19:00.66#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.231.08:19:00.66#ibcon#[27=AT01-04\r\n] 2006.231.08:19:00.66#ibcon#*before write, iclass 10, count 2 2006.231.08:19:00.66#ibcon#enter sib2, iclass 10, count 2 2006.231.08:19:00.66#ibcon#flushed, iclass 10, count 2 2006.231.08:19:00.66#ibcon#about to write, iclass 10, count 2 2006.231.08:19:00.66#ibcon#wrote, iclass 10, count 2 2006.231.08:19:00.66#ibcon#about to read 3, iclass 10, count 2 2006.231.08:19:00.69#ibcon#read 3, iclass 10, count 2 2006.231.08:19:00.69#ibcon#about to read 4, iclass 10, count 2 2006.231.08:19:00.69#ibcon#read 4, iclass 10, count 2 2006.231.08:19:00.69#ibcon#about to read 5, iclass 10, count 2 2006.231.08:19:00.69#ibcon#read 5, iclass 10, count 2 2006.231.08:19:00.69#ibcon#about to read 6, iclass 10, count 2 2006.231.08:19:00.69#ibcon#read 6, iclass 10, count 2 2006.231.08:19:00.69#ibcon#end of sib2, iclass 10, count 2 2006.231.08:19:00.69#ibcon#*after write, iclass 10, count 2 2006.231.08:19:00.69#ibcon#*before return 0, iclass 10, count 2 2006.231.08:19:00.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:19:00.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.231.08:19:00.69#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.231.08:19:00.69#ibcon#ireg 7 cls_cnt 0 2006.231.08:19:00.69#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:19:00.81#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:19:00.81#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:19:00.81#ibcon#enter wrdev, iclass 10, count 0 2006.231.08:19:00.81#ibcon#first serial, iclass 10, count 0 2006.231.08:19:00.81#ibcon#enter sib2, iclass 10, count 0 2006.231.08:19:00.81#ibcon#flushed, iclass 10, count 0 2006.231.08:19:00.81#ibcon#about to write, iclass 10, count 0 2006.231.08:19:00.81#ibcon#wrote, iclass 10, count 0 2006.231.08:19:00.81#ibcon#about to read 3, iclass 10, count 0 2006.231.08:19:00.83#ibcon#read 3, iclass 10, count 0 2006.231.08:19:00.83#ibcon#about to read 4, iclass 10, count 0 2006.231.08:19:00.83#ibcon#read 4, iclass 10, count 0 2006.231.08:19:00.83#ibcon#about to read 5, iclass 10, count 0 2006.231.08:19:00.83#ibcon#read 5, iclass 10, count 0 2006.231.08:19:00.83#ibcon#about to read 6, iclass 10, count 0 2006.231.08:19:00.83#ibcon#read 6, iclass 10, count 0 2006.231.08:19:00.83#ibcon#end of sib2, iclass 10, count 0 2006.231.08:19:00.83#ibcon#*mode == 0, iclass 10, count 0 2006.231.08:19:00.83#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.08:19:00.83#ibcon#[27=USB\r\n] 2006.231.08:19:00.83#ibcon#*before write, iclass 10, count 0 2006.231.08:19:00.83#ibcon#enter sib2, iclass 10, count 0 2006.231.08:19:00.83#ibcon#flushed, iclass 10, count 0 2006.231.08:19:00.83#ibcon#about to write, iclass 10, count 0 2006.231.08:19:00.83#ibcon#wrote, iclass 10, count 0 2006.231.08:19:00.83#ibcon#about to read 3, iclass 10, count 0 2006.231.08:19:00.86#ibcon#read 3, iclass 10, count 0 2006.231.08:19:00.86#ibcon#about to read 4, iclass 10, count 0 2006.231.08:19:00.86#ibcon#read 4, iclass 10, count 0 2006.231.08:19:00.86#ibcon#about to read 5, iclass 10, count 0 2006.231.08:19:00.86#ibcon#read 5, iclass 10, count 0 2006.231.08:19:00.86#ibcon#about to read 6, iclass 10, count 0 2006.231.08:19:00.86#ibcon#read 6, iclass 10, count 0 2006.231.08:19:00.86#ibcon#end of sib2, iclass 10, count 0 2006.231.08:19:00.86#ibcon#*after write, iclass 10, count 0 2006.231.08:19:00.86#ibcon#*before return 0, iclass 10, count 0 2006.231.08:19:00.86#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:19:00.86#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.231.08:19:00.86#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.08:19:00.86#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.08:19:00.86$vc4f8/vblo=2,640.99 2006.231.08:19:00.86#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.231.08:19:00.86#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.231.08:19:00.86#ibcon#ireg 17 cls_cnt 0 2006.231.08:19:00.86#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:19:00.86#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:19:00.86#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:19:00.86#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:19:00.86#ibcon#first serial, iclass 12, count 0 2006.231.08:19:00.86#ibcon#enter sib2, iclass 12, count 0 2006.231.08:19:00.86#ibcon#flushed, iclass 12, count 0 2006.231.08:19:00.86#ibcon#about to write, iclass 12, count 0 2006.231.08:19:00.86#ibcon#wrote, iclass 12, count 0 2006.231.08:19:00.86#ibcon#about to read 3, iclass 12, count 0 2006.231.08:19:00.88#ibcon#read 3, iclass 12, count 0 2006.231.08:19:00.88#ibcon#about to read 4, iclass 12, count 0 2006.231.08:19:00.88#ibcon#read 4, iclass 12, count 0 2006.231.08:19:00.88#ibcon#about to read 5, iclass 12, count 0 2006.231.08:19:00.88#ibcon#read 5, iclass 12, count 0 2006.231.08:19:00.88#ibcon#about to read 6, iclass 12, count 0 2006.231.08:19:00.88#ibcon#read 6, iclass 12, count 0 2006.231.08:19:00.88#ibcon#end of sib2, iclass 12, count 0 2006.231.08:19:00.88#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:19:00.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:19:00.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:19:00.88#ibcon#*before write, iclass 12, count 0 2006.231.08:19:00.88#ibcon#enter sib2, iclass 12, count 0 2006.231.08:19:00.88#ibcon#flushed, iclass 12, count 0 2006.231.08:19:00.88#ibcon#about to write, iclass 12, count 0 2006.231.08:19:00.88#ibcon#wrote, iclass 12, count 0 2006.231.08:19:00.88#ibcon#about to read 3, iclass 12, count 0 2006.231.08:19:00.92#ibcon#read 3, iclass 12, count 0 2006.231.08:19:00.92#ibcon#about to read 4, iclass 12, count 0 2006.231.08:19:00.92#ibcon#read 4, iclass 12, count 0 2006.231.08:19:00.92#ibcon#about to read 5, iclass 12, count 0 2006.231.08:19:00.92#ibcon#read 5, iclass 12, count 0 2006.231.08:19:00.92#ibcon#about to read 6, iclass 12, count 0 2006.231.08:19:00.92#ibcon#read 6, iclass 12, count 0 2006.231.08:19:00.92#ibcon#end of sib2, iclass 12, count 0 2006.231.08:19:00.92#ibcon#*after write, iclass 12, count 0 2006.231.08:19:00.92#ibcon#*before return 0, iclass 12, count 0 2006.231.08:19:00.92#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:19:00.92#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.231.08:19:00.92#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:19:00.92#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:19:00.92$vc4f8/vb=2,4 2006.231.08:19:00.92#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.231.08:19:00.92#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.231.08:19:00.92#ibcon#ireg 11 cls_cnt 2 2006.231.08:19:00.92#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:19:00.98#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:19:00.98#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:19:00.98#ibcon#enter wrdev, iclass 14, count 2 2006.231.08:19:00.98#ibcon#first serial, iclass 14, count 2 2006.231.08:19:00.98#ibcon#enter sib2, iclass 14, count 2 2006.231.08:19:00.98#ibcon#flushed, iclass 14, count 2 2006.231.08:19:00.98#ibcon#about to write, iclass 14, count 2 2006.231.08:19:00.98#ibcon#wrote, iclass 14, count 2 2006.231.08:19:00.98#ibcon#about to read 3, iclass 14, count 2 2006.231.08:19:01.00#ibcon#read 3, iclass 14, count 2 2006.231.08:19:01.00#ibcon#about to read 4, iclass 14, count 2 2006.231.08:19:01.00#ibcon#read 4, iclass 14, count 2 2006.231.08:19:01.00#ibcon#about to read 5, iclass 14, count 2 2006.231.08:19:01.00#ibcon#read 5, iclass 14, count 2 2006.231.08:19:01.00#ibcon#about to read 6, iclass 14, count 2 2006.231.08:19:01.00#ibcon#read 6, iclass 14, count 2 2006.231.08:19:01.00#ibcon#end of sib2, iclass 14, count 2 2006.231.08:19:01.00#ibcon#*mode == 0, iclass 14, count 2 2006.231.08:19:01.00#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.231.08:19:01.00#ibcon#[27=AT02-04\r\n] 2006.231.08:19:01.00#ibcon#*before write, iclass 14, count 2 2006.231.08:19:01.00#ibcon#enter sib2, iclass 14, count 2 2006.231.08:19:01.00#ibcon#flushed, iclass 14, count 2 2006.231.08:19:01.00#ibcon#about to write, iclass 14, count 2 2006.231.08:19:01.00#ibcon#wrote, iclass 14, count 2 2006.231.08:19:01.00#ibcon#about to read 3, iclass 14, count 2 2006.231.08:19:01.03#ibcon#read 3, iclass 14, count 2 2006.231.08:19:01.03#ibcon#about to read 4, iclass 14, count 2 2006.231.08:19:01.03#ibcon#read 4, iclass 14, count 2 2006.231.08:19:01.03#ibcon#about to read 5, iclass 14, count 2 2006.231.08:19:01.03#ibcon#read 5, iclass 14, count 2 2006.231.08:19:01.03#ibcon#about to read 6, iclass 14, count 2 2006.231.08:19:01.03#ibcon#read 6, iclass 14, count 2 2006.231.08:19:01.03#ibcon#end of sib2, iclass 14, count 2 2006.231.08:19:01.03#ibcon#*after write, iclass 14, count 2 2006.231.08:19:01.03#ibcon#*before return 0, iclass 14, count 2 2006.231.08:19:01.03#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:19:01.03#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.231.08:19:01.03#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.231.08:19:01.03#ibcon#ireg 7 cls_cnt 0 2006.231.08:19:01.03#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:19:01.15#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:19:01.15#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:19:01.15#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:19:01.15#ibcon#first serial, iclass 14, count 0 2006.231.08:19:01.15#ibcon#enter sib2, iclass 14, count 0 2006.231.08:19:01.15#ibcon#flushed, iclass 14, count 0 2006.231.08:19:01.15#ibcon#about to write, iclass 14, count 0 2006.231.08:19:01.15#ibcon#wrote, iclass 14, count 0 2006.231.08:19:01.15#ibcon#about to read 3, iclass 14, count 0 2006.231.08:19:01.17#ibcon#read 3, iclass 14, count 0 2006.231.08:19:01.17#ibcon#about to read 4, iclass 14, count 0 2006.231.08:19:01.17#ibcon#read 4, iclass 14, count 0 2006.231.08:19:01.17#ibcon#about to read 5, iclass 14, count 0 2006.231.08:19:01.17#ibcon#read 5, iclass 14, count 0 2006.231.08:19:01.17#ibcon#about to read 6, iclass 14, count 0 2006.231.08:19:01.17#ibcon#read 6, iclass 14, count 0 2006.231.08:19:01.17#ibcon#end of sib2, iclass 14, count 0 2006.231.08:19:01.17#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:19:01.17#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:19:01.17#ibcon#[27=USB\r\n] 2006.231.08:19:01.17#ibcon#*before write, iclass 14, count 0 2006.231.08:19:01.17#ibcon#enter sib2, iclass 14, count 0 2006.231.08:19:01.17#ibcon#flushed, iclass 14, count 0 2006.231.08:19:01.17#ibcon#about to write, iclass 14, count 0 2006.231.08:19:01.17#ibcon#wrote, iclass 14, count 0 2006.231.08:19:01.17#ibcon#about to read 3, iclass 14, count 0 2006.231.08:19:01.20#ibcon#read 3, iclass 14, count 0 2006.231.08:19:01.20#ibcon#about to read 4, iclass 14, count 0 2006.231.08:19:01.20#ibcon#read 4, iclass 14, count 0 2006.231.08:19:01.20#ibcon#about to read 5, iclass 14, count 0 2006.231.08:19:01.20#ibcon#read 5, iclass 14, count 0 2006.231.08:19:01.20#ibcon#about to read 6, iclass 14, count 0 2006.231.08:19:01.20#ibcon#read 6, iclass 14, count 0 2006.231.08:19:01.20#ibcon#end of sib2, iclass 14, count 0 2006.231.08:19:01.20#ibcon#*after write, iclass 14, count 0 2006.231.08:19:01.20#ibcon#*before return 0, iclass 14, count 0 2006.231.08:19:01.20#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:19:01.20#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.231.08:19:01.20#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:19:01.20#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:19:01.20$vc4f8/vblo=3,656.99 2006.231.08:19:01.20#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.231.08:19:01.20#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.231.08:19:01.20#ibcon#ireg 17 cls_cnt 0 2006.231.08:19:01.20#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:19:01.20#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:19:01.20#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:19:01.20#ibcon#enter wrdev, iclass 16, count 0 2006.231.08:19:01.20#ibcon#first serial, iclass 16, count 0 2006.231.08:19:01.20#ibcon#enter sib2, iclass 16, count 0 2006.231.08:19:01.20#ibcon#flushed, iclass 16, count 0 2006.231.08:19:01.20#ibcon#about to write, iclass 16, count 0 2006.231.08:19:01.20#ibcon#wrote, iclass 16, count 0 2006.231.08:19:01.20#ibcon#about to read 3, iclass 16, count 0 2006.231.08:19:01.22#ibcon#read 3, iclass 16, count 0 2006.231.08:19:01.22#ibcon#about to read 4, iclass 16, count 0 2006.231.08:19:01.22#ibcon#read 4, iclass 16, count 0 2006.231.08:19:01.22#ibcon#about to read 5, iclass 16, count 0 2006.231.08:19:01.22#ibcon#read 5, iclass 16, count 0 2006.231.08:19:01.22#ibcon#about to read 6, iclass 16, count 0 2006.231.08:19:01.22#ibcon#read 6, iclass 16, count 0 2006.231.08:19:01.22#ibcon#end of sib2, iclass 16, count 0 2006.231.08:19:01.22#ibcon#*mode == 0, iclass 16, count 0 2006.231.08:19:01.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.08:19:01.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:19:01.22#ibcon#*before write, iclass 16, count 0 2006.231.08:19:01.22#ibcon#enter sib2, iclass 16, count 0 2006.231.08:19:01.22#ibcon#flushed, iclass 16, count 0 2006.231.08:19:01.22#ibcon#about to write, iclass 16, count 0 2006.231.08:19:01.22#ibcon#wrote, iclass 16, count 0 2006.231.08:19:01.22#ibcon#about to read 3, iclass 16, count 0 2006.231.08:19:01.25#abcon#<5=/06 4.1 7.6 30.34 831004.5\r\n> 2006.231.08:19:01.26#ibcon#read 3, iclass 16, count 0 2006.231.08:19:01.26#ibcon#about to read 4, iclass 16, count 0 2006.231.08:19:01.26#ibcon#read 4, iclass 16, count 0 2006.231.08:19:01.26#ibcon#about to read 5, iclass 16, count 0 2006.231.08:19:01.26#ibcon#read 5, iclass 16, count 0 2006.231.08:19:01.26#ibcon#about to read 6, iclass 16, count 0 2006.231.08:19:01.26#ibcon#read 6, iclass 16, count 0 2006.231.08:19:01.26#ibcon#end of sib2, iclass 16, count 0 2006.231.08:19:01.26#ibcon#*after write, iclass 16, count 0 2006.231.08:19:01.26#ibcon#*before return 0, iclass 16, count 0 2006.231.08:19:01.26#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:19:01.26#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.231.08:19:01.26#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.08:19:01.26#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.08:19:01.26$vc4f8/vb=3,4 2006.231.08:19:01.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.231.08:19:01.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.231.08:19:01.26#ibcon#ireg 11 cls_cnt 2 2006.231.08:19:01.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:19:01.28#abcon#{5=INTERFACE CLEAR} 2006.231.08:19:01.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:19:01.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:19:01.32#ibcon#enter wrdev, iclass 21, count 2 2006.231.08:19:01.32#ibcon#first serial, iclass 21, count 2 2006.231.08:19:01.32#ibcon#enter sib2, iclass 21, count 2 2006.231.08:19:01.32#ibcon#flushed, iclass 21, count 2 2006.231.08:19:01.32#ibcon#about to write, iclass 21, count 2 2006.231.08:19:01.32#ibcon#wrote, iclass 21, count 2 2006.231.08:19:01.32#ibcon#about to read 3, iclass 21, count 2 2006.231.08:19:01.33#abcon#[5=S1D000X0/0*\r\n] 2006.231.08:19:01.34#ibcon#read 3, iclass 21, count 2 2006.231.08:19:01.34#ibcon#about to read 4, iclass 21, count 2 2006.231.08:19:01.34#ibcon#read 4, iclass 21, count 2 2006.231.08:19:01.34#ibcon#about to read 5, iclass 21, count 2 2006.231.08:19:01.34#ibcon#read 5, iclass 21, count 2 2006.231.08:19:01.34#ibcon#about to read 6, iclass 21, count 2 2006.231.08:19:01.34#ibcon#read 6, iclass 21, count 2 2006.231.08:19:01.34#ibcon#end of sib2, iclass 21, count 2 2006.231.08:19:01.34#ibcon#*mode == 0, iclass 21, count 2 2006.231.08:19:01.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.231.08:19:01.34#ibcon#[27=AT03-04\r\n] 2006.231.08:19:01.34#ibcon#*before write, iclass 21, count 2 2006.231.08:19:01.34#ibcon#enter sib2, iclass 21, count 2 2006.231.08:19:01.34#ibcon#flushed, iclass 21, count 2 2006.231.08:19:01.34#ibcon#about to write, iclass 21, count 2 2006.231.08:19:01.34#ibcon#wrote, iclass 21, count 2 2006.231.08:19:01.34#ibcon#about to read 3, iclass 21, count 2 2006.231.08:19:01.37#ibcon#read 3, iclass 21, count 2 2006.231.08:19:01.37#ibcon#about to read 4, iclass 21, count 2 2006.231.08:19:01.37#ibcon#read 4, iclass 21, count 2 2006.231.08:19:01.37#ibcon#about to read 5, iclass 21, count 2 2006.231.08:19:01.37#ibcon#read 5, iclass 21, count 2 2006.231.08:19:01.37#ibcon#about to read 6, iclass 21, count 2 2006.231.08:19:01.37#ibcon#read 6, iclass 21, count 2 2006.231.08:19:01.37#ibcon#end of sib2, iclass 21, count 2 2006.231.08:19:01.37#ibcon#*after write, iclass 21, count 2 2006.231.08:19:01.37#ibcon#*before return 0, iclass 21, count 2 2006.231.08:19:01.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:19:01.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.231.08:19:01.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.231.08:19:01.37#ibcon#ireg 7 cls_cnt 0 2006.231.08:19:01.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:19:01.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:19:01.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:19:01.49#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:19:01.49#ibcon#first serial, iclass 21, count 0 2006.231.08:19:01.49#ibcon#enter sib2, iclass 21, count 0 2006.231.08:19:01.49#ibcon#flushed, iclass 21, count 0 2006.231.08:19:01.49#ibcon#about to write, iclass 21, count 0 2006.231.08:19:01.49#ibcon#wrote, iclass 21, count 0 2006.231.08:19:01.49#ibcon#about to read 3, iclass 21, count 0 2006.231.08:19:01.51#ibcon#read 3, iclass 21, count 0 2006.231.08:19:01.51#ibcon#about to read 4, iclass 21, count 0 2006.231.08:19:01.51#ibcon#read 4, iclass 21, count 0 2006.231.08:19:01.51#ibcon#about to read 5, iclass 21, count 0 2006.231.08:19:01.51#ibcon#read 5, iclass 21, count 0 2006.231.08:19:01.51#ibcon#about to read 6, iclass 21, count 0 2006.231.08:19:01.51#ibcon#read 6, iclass 21, count 0 2006.231.08:19:01.51#ibcon#end of sib2, iclass 21, count 0 2006.231.08:19:01.51#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:19:01.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:19:01.51#ibcon#[27=USB\r\n] 2006.231.08:19:01.51#ibcon#*before write, iclass 21, count 0 2006.231.08:19:01.51#ibcon#enter sib2, iclass 21, count 0 2006.231.08:19:01.51#ibcon#flushed, iclass 21, count 0 2006.231.08:19:01.51#ibcon#about to write, iclass 21, count 0 2006.231.08:19:01.51#ibcon#wrote, iclass 21, count 0 2006.231.08:19:01.51#ibcon#about to read 3, iclass 21, count 0 2006.231.08:19:01.54#ibcon#read 3, iclass 21, count 0 2006.231.08:19:01.54#ibcon#about to read 4, iclass 21, count 0 2006.231.08:19:01.54#ibcon#read 4, iclass 21, count 0 2006.231.08:19:01.54#ibcon#about to read 5, iclass 21, count 0 2006.231.08:19:01.54#ibcon#read 5, iclass 21, count 0 2006.231.08:19:01.54#ibcon#about to read 6, iclass 21, count 0 2006.231.08:19:01.54#ibcon#read 6, iclass 21, count 0 2006.231.08:19:01.54#ibcon#end of sib2, iclass 21, count 0 2006.231.08:19:01.54#ibcon#*after write, iclass 21, count 0 2006.231.08:19:01.54#ibcon#*before return 0, iclass 21, count 0 2006.231.08:19:01.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:19:01.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.231.08:19:01.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:19:01.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:19:01.54$vc4f8/vblo=4,712.99 2006.231.08:19:01.54#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.231.08:19:01.54#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.231.08:19:01.54#ibcon#ireg 17 cls_cnt 0 2006.231.08:19:01.54#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:19:01.54#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:19:01.54#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:19:01.54#ibcon#enter wrdev, iclass 24, count 0 2006.231.08:19:01.54#ibcon#first serial, iclass 24, count 0 2006.231.08:19:01.54#ibcon#enter sib2, iclass 24, count 0 2006.231.08:19:01.54#ibcon#flushed, iclass 24, count 0 2006.231.08:19:01.54#ibcon#about to write, iclass 24, count 0 2006.231.08:19:01.54#ibcon#wrote, iclass 24, count 0 2006.231.08:19:01.54#ibcon#about to read 3, iclass 24, count 0 2006.231.08:19:01.56#ibcon#read 3, iclass 24, count 0 2006.231.08:19:01.56#ibcon#about to read 4, iclass 24, count 0 2006.231.08:19:01.56#ibcon#read 4, iclass 24, count 0 2006.231.08:19:01.56#ibcon#about to read 5, iclass 24, count 0 2006.231.08:19:01.56#ibcon#read 5, iclass 24, count 0 2006.231.08:19:01.56#ibcon#about to read 6, iclass 24, count 0 2006.231.08:19:01.56#ibcon#read 6, iclass 24, count 0 2006.231.08:19:01.56#ibcon#end of sib2, iclass 24, count 0 2006.231.08:19:01.56#ibcon#*mode == 0, iclass 24, count 0 2006.231.08:19:01.56#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.08:19:01.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:19:01.56#ibcon#*before write, iclass 24, count 0 2006.231.08:19:01.56#ibcon#enter sib2, iclass 24, count 0 2006.231.08:19:01.56#ibcon#flushed, iclass 24, count 0 2006.231.08:19:01.56#ibcon#about to write, iclass 24, count 0 2006.231.08:19:01.56#ibcon#wrote, iclass 24, count 0 2006.231.08:19:01.56#ibcon#about to read 3, iclass 24, count 0 2006.231.08:19:01.60#ibcon#read 3, iclass 24, count 0 2006.231.08:19:01.60#ibcon#about to read 4, iclass 24, count 0 2006.231.08:19:01.60#ibcon#read 4, iclass 24, count 0 2006.231.08:19:01.60#ibcon#about to read 5, iclass 24, count 0 2006.231.08:19:01.60#ibcon#read 5, iclass 24, count 0 2006.231.08:19:01.60#ibcon#about to read 6, iclass 24, count 0 2006.231.08:19:01.60#ibcon#read 6, iclass 24, count 0 2006.231.08:19:01.60#ibcon#end of sib2, iclass 24, count 0 2006.231.08:19:01.60#ibcon#*after write, iclass 24, count 0 2006.231.08:19:01.60#ibcon#*before return 0, iclass 24, count 0 2006.231.08:19:01.60#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:19:01.60#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.231.08:19:01.60#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.08:19:01.60#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.08:19:01.60$vc4f8/vb=4,4 2006.231.08:19:01.60#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.231.08:19:01.60#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.231.08:19:01.60#ibcon#ireg 11 cls_cnt 2 2006.231.08:19:01.60#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:19:01.66#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:19:01.66#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:19:01.66#ibcon#enter wrdev, iclass 26, count 2 2006.231.08:19:01.66#ibcon#first serial, iclass 26, count 2 2006.231.08:19:01.66#ibcon#enter sib2, iclass 26, count 2 2006.231.08:19:01.66#ibcon#flushed, iclass 26, count 2 2006.231.08:19:01.66#ibcon#about to write, iclass 26, count 2 2006.231.08:19:01.66#ibcon#wrote, iclass 26, count 2 2006.231.08:19:01.66#ibcon#about to read 3, iclass 26, count 2 2006.231.08:19:01.68#ibcon#read 3, iclass 26, count 2 2006.231.08:19:01.68#ibcon#about to read 4, iclass 26, count 2 2006.231.08:19:01.68#ibcon#read 4, iclass 26, count 2 2006.231.08:19:01.68#ibcon#about to read 5, iclass 26, count 2 2006.231.08:19:01.68#ibcon#read 5, iclass 26, count 2 2006.231.08:19:01.68#ibcon#about to read 6, iclass 26, count 2 2006.231.08:19:01.68#ibcon#read 6, iclass 26, count 2 2006.231.08:19:01.68#ibcon#end of sib2, iclass 26, count 2 2006.231.08:19:01.68#ibcon#*mode == 0, iclass 26, count 2 2006.231.08:19:01.68#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.231.08:19:01.68#ibcon#[27=AT04-04\r\n] 2006.231.08:19:01.68#ibcon#*before write, iclass 26, count 2 2006.231.08:19:01.68#ibcon#enter sib2, iclass 26, count 2 2006.231.08:19:01.68#ibcon#flushed, iclass 26, count 2 2006.231.08:19:01.68#ibcon#about to write, iclass 26, count 2 2006.231.08:19:01.68#ibcon#wrote, iclass 26, count 2 2006.231.08:19:01.68#ibcon#about to read 3, iclass 26, count 2 2006.231.08:19:01.71#ibcon#read 3, iclass 26, count 2 2006.231.08:19:01.71#ibcon#about to read 4, iclass 26, count 2 2006.231.08:19:01.71#ibcon#read 4, iclass 26, count 2 2006.231.08:19:01.71#ibcon#about to read 5, iclass 26, count 2 2006.231.08:19:01.71#ibcon#read 5, iclass 26, count 2 2006.231.08:19:01.71#ibcon#about to read 6, iclass 26, count 2 2006.231.08:19:01.71#ibcon#read 6, iclass 26, count 2 2006.231.08:19:01.71#ibcon#end of sib2, iclass 26, count 2 2006.231.08:19:01.71#ibcon#*after write, iclass 26, count 2 2006.231.08:19:01.71#ibcon#*before return 0, iclass 26, count 2 2006.231.08:19:01.71#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:19:01.71#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.231.08:19:01.71#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.231.08:19:01.71#ibcon#ireg 7 cls_cnt 0 2006.231.08:19:01.71#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:19:01.83#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:19:01.83#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:19:01.83#ibcon#enter wrdev, iclass 26, count 0 2006.231.08:19:01.83#ibcon#first serial, iclass 26, count 0 2006.231.08:19:01.83#ibcon#enter sib2, iclass 26, count 0 2006.231.08:19:01.83#ibcon#flushed, iclass 26, count 0 2006.231.08:19:01.83#ibcon#about to write, iclass 26, count 0 2006.231.08:19:01.83#ibcon#wrote, iclass 26, count 0 2006.231.08:19:01.83#ibcon#about to read 3, iclass 26, count 0 2006.231.08:19:01.85#ibcon#read 3, iclass 26, count 0 2006.231.08:19:01.85#ibcon#about to read 4, iclass 26, count 0 2006.231.08:19:01.85#ibcon#read 4, iclass 26, count 0 2006.231.08:19:01.85#ibcon#about to read 5, iclass 26, count 0 2006.231.08:19:01.85#ibcon#read 5, iclass 26, count 0 2006.231.08:19:01.85#ibcon#about to read 6, iclass 26, count 0 2006.231.08:19:01.85#ibcon#read 6, iclass 26, count 0 2006.231.08:19:01.85#ibcon#end of sib2, iclass 26, count 0 2006.231.08:19:01.85#ibcon#*mode == 0, iclass 26, count 0 2006.231.08:19:01.85#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.08:19:01.85#ibcon#[27=USB\r\n] 2006.231.08:19:01.85#ibcon#*before write, iclass 26, count 0 2006.231.08:19:01.85#ibcon#enter sib2, iclass 26, count 0 2006.231.08:19:01.85#ibcon#flushed, iclass 26, count 0 2006.231.08:19:01.85#ibcon#about to write, iclass 26, count 0 2006.231.08:19:01.85#ibcon#wrote, iclass 26, count 0 2006.231.08:19:01.85#ibcon#about to read 3, iclass 26, count 0 2006.231.08:19:01.88#ibcon#read 3, iclass 26, count 0 2006.231.08:19:01.88#ibcon#about to read 4, iclass 26, count 0 2006.231.08:19:01.88#ibcon#read 4, iclass 26, count 0 2006.231.08:19:01.88#ibcon#about to read 5, iclass 26, count 0 2006.231.08:19:01.88#ibcon#read 5, iclass 26, count 0 2006.231.08:19:01.88#ibcon#about to read 6, iclass 26, count 0 2006.231.08:19:01.88#ibcon#read 6, iclass 26, count 0 2006.231.08:19:01.88#ibcon#end of sib2, iclass 26, count 0 2006.231.08:19:01.88#ibcon#*after write, iclass 26, count 0 2006.231.08:19:01.88#ibcon#*before return 0, iclass 26, count 0 2006.231.08:19:01.88#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:19:01.88#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.231.08:19:01.88#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.08:19:01.88#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.08:19:01.88$vc4f8/vblo=5,744.99 2006.231.08:19:01.88#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.231.08:19:01.88#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.231.08:19:01.88#ibcon#ireg 17 cls_cnt 0 2006.231.08:19:01.88#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:19:01.88#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:19:01.88#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:19:01.88#ibcon#enter wrdev, iclass 28, count 0 2006.231.08:19:01.88#ibcon#first serial, iclass 28, count 0 2006.231.08:19:01.88#ibcon#enter sib2, iclass 28, count 0 2006.231.08:19:01.88#ibcon#flushed, iclass 28, count 0 2006.231.08:19:01.88#ibcon#about to write, iclass 28, count 0 2006.231.08:19:01.88#ibcon#wrote, iclass 28, count 0 2006.231.08:19:01.88#ibcon#about to read 3, iclass 28, count 0 2006.231.08:19:01.90#ibcon#read 3, iclass 28, count 0 2006.231.08:19:01.90#ibcon#about to read 4, iclass 28, count 0 2006.231.08:19:01.90#ibcon#read 4, iclass 28, count 0 2006.231.08:19:01.90#ibcon#about to read 5, iclass 28, count 0 2006.231.08:19:01.90#ibcon#read 5, iclass 28, count 0 2006.231.08:19:01.90#ibcon#about to read 6, iclass 28, count 0 2006.231.08:19:01.90#ibcon#read 6, iclass 28, count 0 2006.231.08:19:01.90#ibcon#end of sib2, iclass 28, count 0 2006.231.08:19:01.90#ibcon#*mode == 0, iclass 28, count 0 2006.231.08:19:01.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.08:19:01.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:19:01.90#ibcon#*before write, iclass 28, count 0 2006.231.08:19:01.90#ibcon#enter sib2, iclass 28, count 0 2006.231.08:19:01.90#ibcon#flushed, iclass 28, count 0 2006.231.08:19:01.90#ibcon#about to write, iclass 28, count 0 2006.231.08:19:01.90#ibcon#wrote, iclass 28, count 0 2006.231.08:19:01.90#ibcon#about to read 3, iclass 28, count 0 2006.231.08:19:01.94#ibcon#read 3, iclass 28, count 0 2006.231.08:19:01.94#ibcon#about to read 4, iclass 28, count 0 2006.231.08:19:01.94#ibcon#read 4, iclass 28, count 0 2006.231.08:19:01.94#ibcon#about to read 5, iclass 28, count 0 2006.231.08:19:01.94#ibcon#read 5, iclass 28, count 0 2006.231.08:19:01.94#ibcon#about to read 6, iclass 28, count 0 2006.231.08:19:01.94#ibcon#read 6, iclass 28, count 0 2006.231.08:19:01.94#ibcon#end of sib2, iclass 28, count 0 2006.231.08:19:01.94#ibcon#*after write, iclass 28, count 0 2006.231.08:19:01.94#ibcon#*before return 0, iclass 28, count 0 2006.231.08:19:01.94#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:19:01.94#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.231.08:19:01.94#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.08:19:01.94#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.08:19:01.94$vc4f8/vb=5,3 2006.231.08:19:01.94#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.231.08:19:01.94#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.231.08:19:01.94#ibcon#ireg 11 cls_cnt 2 2006.231.08:19:01.94#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:19:02.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:19:02.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:19:02.00#ibcon#enter wrdev, iclass 30, count 2 2006.231.08:19:02.00#ibcon#first serial, iclass 30, count 2 2006.231.08:19:02.00#ibcon#enter sib2, iclass 30, count 2 2006.231.08:19:02.00#ibcon#flushed, iclass 30, count 2 2006.231.08:19:02.00#ibcon#about to write, iclass 30, count 2 2006.231.08:19:02.00#ibcon#wrote, iclass 30, count 2 2006.231.08:19:02.00#ibcon#about to read 3, iclass 30, count 2 2006.231.08:19:02.02#ibcon#read 3, iclass 30, count 2 2006.231.08:19:02.02#ibcon#about to read 4, iclass 30, count 2 2006.231.08:19:02.02#ibcon#read 4, iclass 30, count 2 2006.231.08:19:02.02#ibcon#about to read 5, iclass 30, count 2 2006.231.08:19:02.02#ibcon#read 5, iclass 30, count 2 2006.231.08:19:02.02#ibcon#about to read 6, iclass 30, count 2 2006.231.08:19:02.02#ibcon#read 6, iclass 30, count 2 2006.231.08:19:02.02#ibcon#end of sib2, iclass 30, count 2 2006.231.08:19:02.02#ibcon#*mode == 0, iclass 30, count 2 2006.231.08:19:02.02#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.231.08:19:02.02#ibcon#[27=AT05-03\r\n] 2006.231.08:19:02.02#ibcon#*before write, iclass 30, count 2 2006.231.08:19:02.02#ibcon#enter sib2, iclass 30, count 2 2006.231.08:19:02.02#ibcon#flushed, iclass 30, count 2 2006.231.08:19:02.02#ibcon#about to write, iclass 30, count 2 2006.231.08:19:02.02#ibcon#wrote, iclass 30, count 2 2006.231.08:19:02.02#ibcon#about to read 3, iclass 30, count 2 2006.231.08:19:02.05#ibcon#read 3, iclass 30, count 2 2006.231.08:19:02.05#ibcon#about to read 4, iclass 30, count 2 2006.231.08:19:02.05#ibcon#read 4, iclass 30, count 2 2006.231.08:19:02.05#ibcon#about to read 5, iclass 30, count 2 2006.231.08:19:02.05#ibcon#read 5, iclass 30, count 2 2006.231.08:19:02.05#ibcon#about to read 6, iclass 30, count 2 2006.231.08:19:02.05#ibcon#read 6, iclass 30, count 2 2006.231.08:19:02.05#ibcon#end of sib2, iclass 30, count 2 2006.231.08:19:02.05#ibcon#*after write, iclass 30, count 2 2006.231.08:19:02.05#ibcon#*before return 0, iclass 30, count 2 2006.231.08:19:02.05#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:19:02.05#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.231.08:19:02.05#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.231.08:19:02.05#ibcon#ireg 7 cls_cnt 0 2006.231.08:19:02.05#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:19:02.17#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:19:02.17#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:19:02.17#ibcon#enter wrdev, iclass 30, count 0 2006.231.08:19:02.17#ibcon#first serial, iclass 30, count 0 2006.231.08:19:02.17#ibcon#enter sib2, iclass 30, count 0 2006.231.08:19:02.17#ibcon#flushed, iclass 30, count 0 2006.231.08:19:02.17#ibcon#about to write, iclass 30, count 0 2006.231.08:19:02.17#ibcon#wrote, iclass 30, count 0 2006.231.08:19:02.17#ibcon#about to read 3, iclass 30, count 0 2006.231.08:19:02.19#ibcon#read 3, iclass 30, count 0 2006.231.08:19:02.19#ibcon#about to read 4, iclass 30, count 0 2006.231.08:19:02.19#ibcon#read 4, iclass 30, count 0 2006.231.08:19:02.19#ibcon#about to read 5, iclass 30, count 0 2006.231.08:19:02.19#ibcon#read 5, iclass 30, count 0 2006.231.08:19:02.19#ibcon#about to read 6, iclass 30, count 0 2006.231.08:19:02.19#ibcon#read 6, iclass 30, count 0 2006.231.08:19:02.19#ibcon#end of sib2, iclass 30, count 0 2006.231.08:19:02.19#ibcon#*mode == 0, iclass 30, count 0 2006.231.08:19:02.19#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.08:19:02.19#ibcon#[27=USB\r\n] 2006.231.08:19:02.19#ibcon#*before write, iclass 30, count 0 2006.231.08:19:02.19#ibcon#enter sib2, iclass 30, count 0 2006.231.08:19:02.19#ibcon#flushed, iclass 30, count 0 2006.231.08:19:02.19#ibcon#about to write, iclass 30, count 0 2006.231.08:19:02.19#ibcon#wrote, iclass 30, count 0 2006.231.08:19:02.19#ibcon#about to read 3, iclass 30, count 0 2006.231.08:19:02.22#ibcon#read 3, iclass 30, count 0 2006.231.08:19:02.22#ibcon#about to read 4, iclass 30, count 0 2006.231.08:19:02.22#ibcon#read 4, iclass 30, count 0 2006.231.08:19:02.22#ibcon#about to read 5, iclass 30, count 0 2006.231.08:19:02.22#ibcon#read 5, iclass 30, count 0 2006.231.08:19:02.22#ibcon#about to read 6, iclass 30, count 0 2006.231.08:19:02.22#ibcon#read 6, iclass 30, count 0 2006.231.08:19:02.22#ibcon#end of sib2, iclass 30, count 0 2006.231.08:19:02.22#ibcon#*after write, iclass 30, count 0 2006.231.08:19:02.22#ibcon#*before return 0, iclass 30, count 0 2006.231.08:19:02.22#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:19:02.22#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.231.08:19:02.22#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.08:19:02.22#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.08:19:02.22$vc4f8/vblo=6,752.99 2006.231.08:19:02.22#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.231.08:19:02.22#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.231.08:19:02.22#ibcon#ireg 17 cls_cnt 0 2006.231.08:19:02.22#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:19:02.22#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:19:02.22#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:19:02.22#ibcon#enter wrdev, iclass 32, count 0 2006.231.08:19:02.22#ibcon#first serial, iclass 32, count 0 2006.231.08:19:02.22#ibcon#enter sib2, iclass 32, count 0 2006.231.08:19:02.22#ibcon#flushed, iclass 32, count 0 2006.231.08:19:02.22#ibcon#about to write, iclass 32, count 0 2006.231.08:19:02.22#ibcon#wrote, iclass 32, count 0 2006.231.08:19:02.22#ibcon#about to read 3, iclass 32, count 0 2006.231.08:19:02.24#ibcon#read 3, iclass 32, count 0 2006.231.08:19:02.24#ibcon#about to read 4, iclass 32, count 0 2006.231.08:19:02.24#ibcon#read 4, iclass 32, count 0 2006.231.08:19:02.24#ibcon#about to read 5, iclass 32, count 0 2006.231.08:19:02.24#ibcon#read 5, iclass 32, count 0 2006.231.08:19:02.24#ibcon#about to read 6, iclass 32, count 0 2006.231.08:19:02.24#ibcon#read 6, iclass 32, count 0 2006.231.08:19:02.24#ibcon#end of sib2, iclass 32, count 0 2006.231.08:19:02.24#ibcon#*mode == 0, iclass 32, count 0 2006.231.08:19:02.24#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.08:19:02.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:19:02.24#ibcon#*before write, iclass 32, count 0 2006.231.08:19:02.24#ibcon#enter sib2, iclass 32, count 0 2006.231.08:19:02.24#ibcon#flushed, iclass 32, count 0 2006.231.08:19:02.24#ibcon#about to write, iclass 32, count 0 2006.231.08:19:02.24#ibcon#wrote, iclass 32, count 0 2006.231.08:19:02.24#ibcon#about to read 3, iclass 32, count 0 2006.231.08:19:02.28#ibcon#read 3, iclass 32, count 0 2006.231.08:19:02.28#ibcon#about to read 4, iclass 32, count 0 2006.231.08:19:02.28#ibcon#read 4, iclass 32, count 0 2006.231.08:19:02.28#ibcon#about to read 5, iclass 32, count 0 2006.231.08:19:02.28#ibcon#read 5, iclass 32, count 0 2006.231.08:19:02.28#ibcon#about to read 6, iclass 32, count 0 2006.231.08:19:02.28#ibcon#read 6, iclass 32, count 0 2006.231.08:19:02.28#ibcon#end of sib2, iclass 32, count 0 2006.231.08:19:02.28#ibcon#*after write, iclass 32, count 0 2006.231.08:19:02.28#ibcon#*before return 0, iclass 32, count 0 2006.231.08:19:02.28#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:19:02.28#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.231.08:19:02.28#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.08:19:02.28#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.08:19:02.28$vc4f8/vb=6,4 2006.231.08:19:02.28#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.231.08:19:02.28#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.231.08:19:02.28#ibcon#ireg 11 cls_cnt 2 2006.231.08:19:02.28#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:19:02.34#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:19:02.34#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:19:02.34#ibcon#enter wrdev, iclass 34, count 2 2006.231.08:19:02.34#ibcon#first serial, iclass 34, count 2 2006.231.08:19:02.34#ibcon#enter sib2, iclass 34, count 2 2006.231.08:19:02.34#ibcon#flushed, iclass 34, count 2 2006.231.08:19:02.34#ibcon#about to write, iclass 34, count 2 2006.231.08:19:02.34#ibcon#wrote, iclass 34, count 2 2006.231.08:19:02.34#ibcon#about to read 3, iclass 34, count 2 2006.231.08:19:02.36#ibcon#read 3, iclass 34, count 2 2006.231.08:19:02.36#ibcon#about to read 4, iclass 34, count 2 2006.231.08:19:02.36#ibcon#read 4, iclass 34, count 2 2006.231.08:19:02.36#ibcon#about to read 5, iclass 34, count 2 2006.231.08:19:02.36#ibcon#read 5, iclass 34, count 2 2006.231.08:19:02.36#ibcon#about to read 6, iclass 34, count 2 2006.231.08:19:02.36#ibcon#read 6, iclass 34, count 2 2006.231.08:19:02.36#ibcon#end of sib2, iclass 34, count 2 2006.231.08:19:02.36#ibcon#*mode == 0, iclass 34, count 2 2006.231.08:19:02.36#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.231.08:19:02.36#ibcon#[27=AT06-04\r\n] 2006.231.08:19:02.36#ibcon#*before write, iclass 34, count 2 2006.231.08:19:02.36#ibcon#enter sib2, iclass 34, count 2 2006.231.08:19:02.36#ibcon#flushed, iclass 34, count 2 2006.231.08:19:02.36#ibcon#about to write, iclass 34, count 2 2006.231.08:19:02.36#ibcon#wrote, iclass 34, count 2 2006.231.08:19:02.36#ibcon#about to read 3, iclass 34, count 2 2006.231.08:19:02.39#ibcon#read 3, iclass 34, count 2 2006.231.08:19:02.39#ibcon#about to read 4, iclass 34, count 2 2006.231.08:19:02.39#ibcon#read 4, iclass 34, count 2 2006.231.08:19:02.39#ibcon#about to read 5, iclass 34, count 2 2006.231.08:19:02.39#ibcon#read 5, iclass 34, count 2 2006.231.08:19:02.39#ibcon#about to read 6, iclass 34, count 2 2006.231.08:19:02.39#ibcon#read 6, iclass 34, count 2 2006.231.08:19:02.39#ibcon#end of sib2, iclass 34, count 2 2006.231.08:19:02.39#ibcon#*after write, iclass 34, count 2 2006.231.08:19:02.39#ibcon#*before return 0, iclass 34, count 2 2006.231.08:19:02.39#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:19:02.39#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.231.08:19:02.39#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.231.08:19:02.39#ibcon#ireg 7 cls_cnt 0 2006.231.08:19:02.39#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:19:02.51#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:19:02.51#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:19:02.51#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:19:02.51#ibcon#first serial, iclass 34, count 0 2006.231.08:19:02.51#ibcon#enter sib2, iclass 34, count 0 2006.231.08:19:02.51#ibcon#flushed, iclass 34, count 0 2006.231.08:19:02.51#ibcon#about to write, iclass 34, count 0 2006.231.08:19:02.51#ibcon#wrote, iclass 34, count 0 2006.231.08:19:02.51#ibcon#about to read 3, iclass 34, count 0 2006.231.08:19:02.53#ibcon#read 3, iclass 34, count 0 2006.231.08:19:02.53#ibcon#about to read 4, iclass 34, count 0 2006.231.08:19:02.53#ibcon#read 4, iclass 34, count 0 2006.231.08:19:02.53#ibcon#about to read 5, iclass 34, count 0 2006.231.08:19:02.53#ibcon#read 5, iclass 34, count 0 2006.231.08:19:02.53#ibcon#about to read 6, iclass 34, count 0 2006.231.08:19:02.53#ibcon#read 6, iclass 34, count 0 2006.231.08:19:02.53#ibcon#end of sib2, iclass 34, count 0 2006.231.08:19:02.53#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:19:02.53#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:19:02.53#ibcon#[27=USB\r\n] 2006.231.08:19:02.53#ibcon#*before write, iclass 34, count 0 2006.231.08:19:02.53#ibcon#enter sib2, iclass 34, count 0 2006.231.08:19:02.53#ibcon#flushed, iclass 34, count 0 2006.231.08:19:02.53#ibcon#about to write, iclass 34, count 0 2006.231.08:19:02.53#ibcon#wrote, iclass 34, count 0 2006.231.08:19:02.53#ibcon#about to read 3, iclass 34, count 0 2006.231.08:19:02.56#ibcon#read 3, iclass 34, count 0 2006.231.08:19:02.56#ibcon#about to read 4, iclass 34, count 0 2006.231.08:19:02.56#ibcon#read 4, iclass 34, count 0 2006.231.08:19:02.56#ibcon#about to read 5, iclass 34, count 0 2006.231.08:19:02.56#ibcon#read 5, iclass 34, count 0 2006.231.08:19:02.56#ibcon#about to read 6, iclass 34, count 0 2006.231.08:19:02.56#ibcon#read 6, iclass 34, count 0 2006.231.08:19:02.56#ibcon#end of sib2, iclass 34, count 0 2006.231.08:19:02.56#ibcon#*after write, iclass 34, count 0 2006.231.08:19:02.56#ibcon#*before return 0, iclass 34, count 0 2006.231.08:19:02.56#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:19:02.56#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.231.08:19:02.56#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:19:02.56#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:19:02.56$vc4f8/vabw=wide 2006.231.08:19:02.56#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.231.08:19:02.56#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.231.08:19:02.56#ibcon#ireg 8 cls_cnt 0 2006.231.08:19:02.56#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:19:02.56#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:19:02.56#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:19:02.56#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:19:02.56#ibcon#first serial, iclass 36, count 0 2006.231.08:19:02.56#ibcon#enter sib2, iclass 36, count 0 2006.231.08:19:02.56#ibcon#flushed, iclass 36, count 0 2006.231.08:19:02.56#ibcon#about to write, iclass 36, count 0 2006.231.08:19:02.56#ibcon#wrote, iclass 36, count 0 2006.231.08:19:02.56#ibcon#about to read 3, iclass 36, count 0 2006.231.08:19:02.58#ibcon#read 3, iclass 36, count 0 2006.231.08:19:02.58#ibcon#about to read 4, iclass 36, count 0 2006.231.08:19:02.58#ibcon#read 4, iclass 36, count 0 2006.231.08:19:02.58#ibcon#about to read 5, iclass 36, count 0 2006.231.08:19:02.58#ibcon#read 5, iclass 36, count 0 2006.231.08:19:02.58#ibcon#about to read 6, iclass 36, count 0 2006.231.08:19:02.58#ibcon#read 6, iclass 36, count 0 2006.231.08:19:02.58#ibcon#end of sib2, iclass 36, count 0 2006.231.08:19:02.58#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:19:02.58#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:19:02.58#ibcon#[25=BW32\r\n] 2006.231.08:19:02.58#ibcon#*before write, iclass 36, count 0 2006.231.08:19:02.58#ibcon#enter sib2, iclass 36, count 0 2006.231.08:19:02.58#ibcon#flushed, iclass 36, count 0 2006.231.08:19:02.58#ibcon#about to write, iclass 36, count 0 2006.231.08:19:02.58#ibcon#wrote, iclass 36, count 0 2006.231.08:19:02.58#ibcon#about to read 3, iclass 36, count 0 2006.231.08:19:02.61#ibcon#read 3, iclass 36, count 0 2006.231.08:19:02.61#ibcon#about to read 4, iclass 36, count 0 2006.231.08:19:02.61#ibcon#read 4, iclass 36, count 0 2006.231.08:19:02.61#ibcon#about to read 5, iclass 36, count 0 2006.231.08:19:02.61#ibcon#read 5, iclass 36, count 0 2006.231.08:19:02.61#ibcon#about to read 6, iclass 36, count 0 2006.231.08:19:02.61#ibcon#read 6, iclass 36, count 0 2006.231.08:19:02.61#ibcon#end of sib2, iclass 36, count 0 2006.231.08:19:02.61#ibcon#*after write, iclass 36, count 0 2006.231.08:19:02.61#ibcon#*before return 0, iclass 36, count 0 2006.231.08:19:02.61#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:19:02.61#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.231.08:19:02.61#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:19:02.61#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:19:02.61$vc4f8/vbbw=wide 2006.231.08:19:02.61#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.08:19:02.61#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.08:19:02.61#ibcon#ireg 8 cls_cnt 0 2006.231.08:19:02.61#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:19:02.68#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:19:02.68#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:19:02.68#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:19:02.68#ibcon#first serial, iclass 38, count 0 2006.231.08:19:02.68#ibcon#enter sib2, iclass 38, count 0 2006.231.08:19:02.68#ibcon#flushed, iclass 38, count 0 2006.231.08:19:02.68#ibcon#about to write, iclass 38, count 0 2006.231.08:19:02.68#ibcon#wrote, iclass 38, count 0 2006.231.08:19:02.68#ibcon#about to read 3, iclass 38, count 0 2006.231.08:19:02.70#ibcon#read 3, iclass 38, count 0 2006.231.08:19:02.70#ibcon#about to read 4, iclass 38, count 0 2006.231.08:19:02.70#ibcon#read 4, iclass 38, count 0 2006.231.08:19:02.70#ibcon#about to read 5, iclass 38, count 0 2006.231.08:19:02.70#ibcon#read 5, iclass 38, count 0 2006.231.08:19:02.70#ibcon#about to read 6, iclass 38, count 0 2006.231.08:19:02.70#ibcon#read 6, iclass 38, count 0 2006.231.08:19:02.70#ibcon#end of sib2, iclass 38, count 0 2006.231.08:19:02.70#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:19:02.70#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:19:02.70#ibcon#[27=BW32\r\n] 2006.231.08:19:02.70#ibcon#*before write, iclass 38, count 0 2006.231.08:19:02.70#ibcon#enter sib2, iclass 38, count 0 2006.231.08:19:02.70#ibcon#flushed, iclass 38, count 0 2006.231.08:19:02.70#ibcon#about to write, iclass 38, count 0 2006.231.08:19:02.70#ibcon#wrote, iclass 38, count 0 2006.231.08:19:02.70#ibcon#about to read 3, iclass 38, count 0 2006.231.08:19:02.73#ibcon#read 3, iclass 38, count 0 2006.231.08:19:02.73#ibcon#about to read 4, iclass 38, count 0 2006.231.08:19:02.73#ibcon#read 4, iclass 38, count 0 2006.231.08:19:02.73#ibcon#about to read 5, iclass 38, count 0 2006.231.08:19:02.73#ibcon#read 5, iclass 38, count 0 2006.231.08:19:02.73#ibcon#about to read 6, iclass 38, count 0 2006.231.08:19:02.73#ibcon#read 6, iclass 38, count 0 2006.231.08:19:02.73#ibcon#end of sib2, iclass 38, count 0 2006.231.08:19:02.73#ibcon#*after write, iclass 38, count 0 2006.231.08:19:02.73#ibcon#*before return 0, iclass 38, count 0 2006.231.08:19:02.73#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:19:02.73#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:19:02.73#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:19:02.73#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:19:02.73$4f8m12a/ifd4f 2006.231.08:19:02.73$ifd4f/lo= 2006.231.08:19:02.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:19:02.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:19:02.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:19:02.73$ifd4f/patch= 2006.231.08:19:02.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:19:02.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:19:02.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:19:02.73$4f8m12a/"form=m,16.000,1:2 2006.231.08:19:02.73$4f8m12a/"tpicd 2006.231.08:19:02.73$4f8m12a/echo=off 2006.231.08:19:02.73$4f8m12a/xlog=off 2006.231.08:19:02.73:!2006.231.08:20:30 2006.231.08:19:48.14#trakl#Source acquired 2006.231.08:19:48.14#flagr#flagr/antenna,acquired 2006.231.08:20:30.00:preob 2006.231.08:20:31.14/onsource/TRACKING 2006.231.08:20:31.14:!2006.231.08:20:40 2006.231.08:20:40.00:data_valid=on 2006.231.08:20:40.00:midob 2006.231.08:20:40.14/onsource/TRACKING 2006.231.08:20:40.14/wx/30.30,1004.6,84 2006.231.08:20:40.34/cable/+6.3719E-03 2006.231.08:20:41.43/va/01,08,usb,yes,29,31 2006.231.08:20:41.43/va/02,07,usb,yes,29,31 2006.231.08:20:41.43/va/03,08,usb,yes,22,22 2006.231.08:20:41.43/va/04,07,usb,yes,30,33 2006.231.08:20:41.43/va/05,07,usb,yes,33,35 2006.231.08:20:41.43/va/06,06,usb,yes,32,32 2006.231.08:20:41.43/va/07,06,usb,yes,33,33 2006.231.08:20:41.43/va/08,06,usb,yes,35,35 2006.231.08:20:41.66/valo/01,532.99,yes,locked 2006.231.08:20:41.66/valo/02,572.99,yes,locked 2006.231.08:20:41.66/valo/03,672.99,yes,locked 2006.231.08:20:41.66/valo/04,832.99,yes,locked 2006.231.08:20:41.66/valo/05,652.99,yes,locked 2006.231.08:20:41.66/valo/06,772.99,yes,locked 2006.231.08:20:41.66/valo/07,832.99,yes,locked 2006.231.08:20:41.66/valo/08,852.99,yes,locked 2006.231.08:20:42.75/vb/01,04,usb,yes,30,29 2006.231.08:20:42.75/vb/02,04,usb,yes,32,33 2006.231.08:20:42.75/vb/03,04,usb,yes,28,32 2006.231.08:20:42.75/vb/04,04,usb,yes,29,29 2006.231.08:20:42.75/vb/05,03,usb,yes,34,39 2006.231.08:20:42.75/vb/06,04,usb,yes,28,31 2006.231.08:20:42.75/vb/07,04,usb,yes,31,30 2006.231.08:20:42.75/vb/08,04,usb,yes,28,32 2006.231.08:20:42.98/vblo/01,632.99,yes,locked 2006.231.08:20:42.98/vblo/02,640.99,yes,locked 2006.231.08:20:42.98/vblo/03,656.99,yes,locked 2006.231.08:20:42.98/vblo/04,712.99,yes,locked 2006.231.08:20:42.98/vblo/05,744.99,yes,locked 2006.231.08:20:42.98/vblo/06,752.99,yes,locked 2006.231.08:20:42.98/vblo/07,734.99,yes,locked 2006.231.08:20:42.98/vblo/08,744.99,yes,locked 2006.231.08:20:43.13/vabw/8 2006.231.08:20:43.28/vbbw/8 2006.231.08:20:43.38/xfe/off,on,12.2 2006.231.08:20:43.75/ifatt/23,28,28,28 2006.231.08:20:44.08/fmout-gps/S +4.47E-07 2006.231.08:20:44.12:!2006.231.08:21:40 2006.231.08:21:40.00:data_valid=off 2006.231.08:21:40.00:postob 2006.231.08:21:40.17/cable/+6.3726E-03 2006.231.08:21:40.17/wx/30.27,1004.5,84 2006.231.08:21:41.08/fmout-gps/S +4.47E-07 2006.231.08:21:41.08:scan_name=231-0824,k06231,60 2006.231.08:21:41.09:source=0059+581,010245.76,582411.1,2000.0,cw 2006.231.08:21:41.14#flagr#flagr/antenna,new-source 2006.231.08:21:42.14:checkk5 2006.231.08:21:42.54/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:21:42.94/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:21:43.32/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:21:43.69/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:21:44.06/chk_obsdata//k5ts1/T2310820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:21:44.43/chk_obsdata//k5ts2/T2310820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:21:44.80/chk_obsdata//k5ts3/T2310820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:21:45.17/chk_obsdata//k5ts4/T2310820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:21:45.85/k5log//k5ts1_log_newline 2006.231.08:21:46.55/k5log//k5ts2_log_newline 2006.231.08:21:47.24/k5log//k5ts3_log_newline 2006.231.08:21:47.92/k5log//k5ts4_log_newline 2006.231.08:21:47.94/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:21:47.94:4f8m12a=3 2006.231.08:21:47.95$4f8m12a/echo=on 2006.231.08:21:47.95$4f8m12a/pcalon 2006.231.08:21:47.95$pcalon/"no phase cal control is implemented here 2006.231.08:21:47.95$4f8m12a/"tpicd=stop 2006.231.08:21:47.95$4f8m12a/vc4f8 2006.231.08:21:47.95$vc4f8/valo=1,532.99 2006.231.08:21:47.95#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.08:21:47.95#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.08:21:47.95#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:47.95#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:21:47.95#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:21:47.95#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:21:47.95#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:21:47.95#ibcon#first serial, iclass 33, count 0 2006.231.08:21:47.95#ibcon#enter sib2, iclass 33, count 0 2006.231.08:21:47.95#ibcon#flushed, iclass 33, count 0 2006.231.08:21:47.95#ibcon#about to write, iclass 33, count 0 2006.231.08:21:47.95#ibcon#wrote, iclass 33, count 0 2006.231.08:21:47.95#ibcon#about to read 3, iclass 33, count 0 2006.231.08:21:47.99#ibcon#read 3, iclass 33, count 0 2006.231.08:21:47.99#ibcon#about to read 4, iclass 33, count 0 2006.231.08:21:47.99#ibcon#read 4, iclass 33, count 0 2006.231.08:21:47.99#ibcon#about to read 5, iclass 33, count 0 2006.231.08:21:47.99#ibcon#read 5, iclass 33, count 0 2006.231.08:21:47.99#ibcon#about to read 6, iclass 33, count 0 2006.231.08:21:47.99#ibcon#read 6, iclass 33, count 0 2006.231.08:21:47.99#ibcon#end of sib2, iclass 33, count 0 2006.231.08:21:47.99#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:21:47.99#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:21:47.99#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:21:47.99#ibcon#*before write, iclass 33, count 0 2006.231.08:21:47.99#ibcon#enter sib2, iclass 33, count 0 2006.231.08:21:47.99#ibcon#flushed, iclass 33, count 0 2006.231.08:21:47.99#ibcon#about to write, iclass 33, count 0 2006.231.08:21:47.99#ibcon#wrote, iclass 33, count 0 2006.231.08:21:47.99#ibcon#about to read 3, iclass 33, count 0 2006.231.08:21:48.04#ibcon#read 3, iclass 33, count 0 2006.231.08:21:48.04#ibcon#about to read 4, iclass 33, count 0 2006.231.08:21:48.04#ibcon#read 4, iclass 33, count 0 2006.231.08:21:48.04#ibcon#about to read 5, iclass 33, count 0 2006.231.08:21:48.04#ibcon#read 5, iclass 33, count 0 2006.231.08:21:48.04#ibcon#about to read 6, iclass 33, count 0 2006.231.08:21:48.04#ibcon#read 6, iclass 33, count 0 2006.231.08:21:48.04#ibcon#end of sib2, iclass 33, count 0 2006.231.08:21:48.04#ibcon#*after write, iclass 33, count 0 2006.231.08:21:48.04#ibcon#*before return 0, iclass 33, count 0 2006.231.08:21:48.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:21:48.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:21:48.04#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:21:48.04#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:21:48.04$vc4f8/va=1,8 2006.231.08:21:48.04#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.08:21:48.04#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.08:21:48.04#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:48.04#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:21:48.04#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:21:48.04#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:21:48.04#ibcon#enter wrdev, iclass 35, count 2 2006.231.08:21:48.04#ibcon#first serial, iclass 35, count 2 2006.231.08:21:48.04#ibcon#enter sib2, iclass 35, count 2 2006.231.08:21:48.04#ibcon#flushed, iclass 35, count 2 2006.231.08:21:48.04#ibcon#about to write, iclass 35, count 2 2006.231.08:21:48.04#ibcon#wrote, iclass 35, count 2 2006.231.08:21:48.04#ibcon#about to read 3, iclass 35, count 2 2006.231.08:21:48.07#ibcon#read 3, iclass 35, count 2 2006.231.08:21:48.07#ibcon#about to read 4, iclass 35, count 2 2006.231.08:21:48.07#ibcon#read 4, iclass 35, count 2 2006.231.08:21:48.07#ibcon#about to read 5, iclass 35, count 2 2006.231.08:21:48.07#ibcon#read 5, iclass 35, count 2 2006.231.08:21:48.07#ibcon#about to read 6, iclass 35, count 2 2006.231.08:21:48.07#ibcon#read 6, iclass 35, count 2 2006.231.08:21:48.07#ibcon#end of sib2, iclass 35, count 2 2006.231.08:21:48.07#ibcon#*mode == 0, iclass 35, count 2 2006.231.08:21:48.07#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.08:21:48.07#ibcon#[25=AT01-08\r\n] 2006.231.08:21:48.07#ibcon#*before write, iclass 35, count 2 2006.231.08:21:48.07#ibcon#enter sib2, iclass 35, count 2 2006.231.08:21:48.07#ibcon#flushed, iclass 35, count 2 2006.231.08:21:48.07#ibcon#about to write, iclass 35, count 2 2006.231.08:21:48.07#ibcon#wrote, iclass 35, count 2 2006.231.08:21:48.07#ibcon#about to read 3, iclass 35, count 2 2006.231.08:21:48.10#ibcon#read 3, iclass 35, count 2 2006.231.08:21:48.10#ibcon#about to read 4, iclass 35, count 2 2006.231.08:21:48.10#ibcon#read 4, iclass 35, count 2 2006.231.08:21:48.10#ibcon#about to read 5, iclass 35, count 2 2006.231.08:21:48.10#ibcon#read 5, iclass 35, count 2 2006.231.08:21:48.10#ibcon#about to read 6, iclass 35, count 2 2006.231.08:21:48.10#ibcon#read 6, iclass 35, count 2 2006.231.08:21:48.10#ibcon#end of sib2, iclass 35, count 2 2006.231.08:21:48.10#ibcon#*after write, iclass 35, count 2 2006.231.08:21:48.10#ibcon#*before return 0, iclass 35, count 2 2006.231.08:21:48.10#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:21:48.10#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:21:48.10#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.08:21:48.10#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:48.10#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:21:48.22#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:21:48.22#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:21:48.22#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:21:48.22#ibcon#first serial, iclass 35, count 0 2006.231.08:21:48.22#ibcon#enter sib2, iclass 35, count 0 2006.231.08:21:48.22#ibcon#flushed, iclass 35, count 0 2006.231.08:21:48.22#ibcon#about to write, iclass 35, count 0 2006.231.08:21:48.22#ibcon#wrote, iclass 35, count 0 2006.231.08:21:48.22#ibcon#about to read 3, iclass 35, count 0 2006.231.08:21:48.25#ibcon#read 3, iclass 35, count 0 2006.231.08:21:48.25#ibcon#about to read 4, iclass 35, count 0 2006.231.08:21:48.25#ibcon#read 4, iclass 35, count 0 2006.231.08:21:48.25#ibcon#about to read 5, iclass 35, count 0 2006.231.08:21:48.25#ibcon#read 5, iclass 35, count 0 2006.231.08:21:48.25#ibcon#about to read 6, iclass 35, count 0 2006.231.08:21:48.25#ibcon#read 6, iclass 35, count 0 2006.231.08:21:48.25#ibcon#end of sib2, iclass 35, count 0 2006.231.08:21:48.25#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:21:48.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:21:48.25#ibcon#[25=USB\r\n] 2006.231.08:21:48.25#ibcon#*before write, iclass 35, count 0 2006.231.08:21:48.25#ibcon#enter sib2, iclass 35, count 0 2006.231.08:21:48.25#ibcon#flushed, iclass 35, count 0 2006.231.08:21:48.25#ibcon#about to write, iclass 35, count 0 2006.231.08:21:48.25#ibcon#wrote, iclass 35, count 0 2006.231.08:21:48.25#ibcon#about to read 3, iclass 35, count 0 2006.231.08:21:48.28#ibcon#read 3, iclass 35, count 0 2006.231.08:21:48.28#ibcon#about to read 4, iclass 35, count 0 2006.231.08:21:48.28#ibcon#read 4, iclass 35, count 0 2006.231.08:21:48.28#ibcon#about to read 5, iclass 35, count 0 2006.231.08:21:48.28#ibcon#read 5, iclass 35, count 0 2006.231.08:21:48.28#ibcon#about to read 6, iclass 35, count 0 2006.231.08:21:48.28#ibcon#read 6, iclass 35, count 0 2006.231.08:21:48.28#ibcon#end of sib2, iclass 35, count 0 2006.231.08:21:48.28#ibcon#*after write, iclass 35, count 0 2006.231.08:21:48.28#ibcon#*before return 0, iclass 35, count 0 2006.231.08:21:48.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:21:48.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:21:48.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:21:48.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:21:48.28$vc4f8/valo=2,572.99 2006.231.08:21:48.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.08:21:48.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.08:21:48.28#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:48.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:21:48.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:21:48.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:21:48.28#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:21:48.28#ibcon#first serial, iclass 37, count 0 2006.231.08:21:48.28#ibcon#enter sib2, iclass 37, count 0 2006.231.08:21:48.28#ibcon#flushed, iclass 37, count 0 2006.231.08:21:48.28#ibcon#about to write, iclass 37, count 0 2006.231.08:21:48.28#ibcon#wrote, iclass 37, count 0 2006.231.08:21:48.28#ibcon#about to read 3, iclass 37, count 0 2006.231.08:21:48.30#ibcon#read 3, iclass 37, count 0 2006.231.08:21:48.30#ibcon#about to read 4, iclass 37, count 0 2006.231.08:21:48.30#ibcon#read 4, iclass 37, count 0 2006.231.08:21:48.30#ibcon#about to read 5, iclass 37, count 0 2006.231.08:21:48.30#ibcon#read 5, iclass 37, count 0 2006.231.08:21:48.30#ibcon#about to read 6, iclass 37, count 0 2006.231.08:21:48.30#ibcon#read 6, iclass 37, count 0 2006.231.08:21:48.30#ibcon#end of sib2, iclass 37, count 0 2006.231.08:21:48.30#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:21:48.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:21:48.30#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:21:48.30#ibcon#*before write, iclass 37, count 0 2006.231.08:21:48.30#ibcon#enter sib2, iclass 37, count 0 2006.231.08:21:48.30#ibcon#flushed, iclass 37, count 0 2006.231.08:21:48.30#ibcon#about to write, iclass 37, count 0 2006.231.08:21:48.30#ibcon#wrote, iclass 37, count 0 2006.231.08:21:48.30#ibcon#about to read 3, iclass 37, count 0 2006.231.08:21:48.35#ibcon#read 3, iclass 37, count 0 2006.231.08:21:48.35#ibcon#about to read 4, iclass 37, count 0 2006.231.08:21:48.35#ibcon#read 4, iclass 37, count 0 2006.231.08:21:48.35#ibcon#about to read 5, iclass 37, count 0 2006.231.08:21:48.35#ibcon#read 5, iclass 37, count 0 2006.231.08:21:48.35#ibcon#about to read 6, iclass 37, count 0 2006.231.08:21:48.35#ibcon#read 6, iclass 37, count 0 2006.231.08:21:48.35#ibcon#end of sib2, iclass 37, count 0 2006.231.08:21:48.35#ibcon#*after write, iclass 37, count 0 2006.231.08:21:48.35#ibcon#*before return 0, iclass 37, count 0 2006.231.08:21:48.35#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:21:48.35#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:21:48.35#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:21:48.35#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:21:48.36$vc4f8/va=2,7 2006.231.08:21:48.36#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.08:21:48.36#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.08:21:48.36#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:48.36#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:21:48.39#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:21:48.39#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:21:48.39#ibcon#enter wrdev, iclass 39, count 2 2006.231.08:21:48.39#ibcon#first serial, iclass 39, count 2 2006.231.08:21:48.39#ibcon#enter sib2, iclass 39, count 2 2006.231.08:21:48.39#ibcon#flushed, iclass 39, count 2 2006.231.08:21:48.39#ibcon#about to write, iclass 39, count 2 2006.231.08:21:48.39#ibcon#wrote, iclass 39, count 2 2006.231.08:21:48.39#ibcon#about to read 3, iclass 39, count 2 2006.231.08:21:48.41#ibcon#read 3, iclass 39, count 2 2006.231.08:21:48.41#ibcon#about to read 4, iclass 39, count 2 2006.231.08:21:48.41#ibcon#read 4, iclass 39, count 2 2006.231.08:21:48.41#ibcon#about to read 5, iclass 39, count 2 2006.231.08:21:48.41#ibcon#read 5, iclass 39, count 2 2006.231.08:21:48.41#ibcon#about to read 6, iclass 39, count 2 2006.231.08:21:48.41#ibcon#read 6, iclass 39, count 2 2006.231.08:21:48.41#ibcon#end of sib2, iclass 39, count 2 2006.231.08:21:48.41#ibcon#*mode == 0, iclass 39, count 2 2006.231.08:21:48.41#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.08:21:48.41#ibcon#[25=AT02-07\r\n] 2006.231.08:21:48.41#ibcon#*before write, iclass 39, count 2 2006.231.08:21:48.41#ibcon#enter sib2, iclass 39, count 2 2006.231.08:21:48.41#ibcon#flushed, iclass 39, count 2 2006.231.08:21:48.41#ibcon#about to write, iclass 39, count 2 2006.231.08:21:48.41#ibcon#wrote, iclass 39, count 2 2006.231.08:21:48.41#ibcon#about to read 3, iclass 39, count 2 2006.231.08:21:48.44#ibcon#read 3, iclass 39, count 2 2006.231.08:21:48.44#ibcon#about to read 4, iclass 39, count 2 2006.231.08:21:48.44#ibcon#read 4, iclass 39, count 2 2006.231.08:21:48.44#ibcon#about to read 5, iclass 39, count 2 2006.231.08:21:48.44#ibcon#read 5, iclass 39, count 2 2006.231.08:21:48.44#ibcon#about to read 6, iclass 39, count 2 2006.231.08:21:48.44#ibcon#read 6, iclass 39, count 2 2006.231.08:21:48.44#ibcon#end of sib2, iclass 39, count 2 2006.231.08:21:48.44#ibcon#*after write, iclass 39, count 2 2006.231.08:21:48.44#ibcon#*before return 0, iclass 39, count 2 2006.231.08:21:48.44#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:21:48.44#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:21:48.44#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.08:21:48.44#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:48.44#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:21:48.56#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:21:48.56#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:21:48.56#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:21:48.56#ibcon#first serial, iclass 39, count 0 2006.231.08:21:48.56#ibcon#enter sib2, iclass 39, count 0 2006.231.08:21:48.56#ibcon#flushed, iclass 39, count 0 2006.231.08:21:48.56#ibcon#about to write, iclass 39, count 0 2006.231.08:21:48.56#ibcon#wrote, iclass 39, count 0 2006.231.08:21:48.56#ibcon#about to read 3, iclass 39, count 0 2006.231.08:21:48.58#ibcon#read 3, iclass 39, count 0 2006.231.08:21:48.58#ibcon#about to read 4, iclass 39, count 0 2006.231.08:21:48.58#ibcon#read 4, iclass 39, count 0 2006.231.08:21:48.58#ibcon#about to read 5, iclass 39, count 0 2006.231.08:21:48.58#ibcon#read 5, iclass 39, count 0 2006.231.08:21:48.58#ibcon#about to read 6, iclass 39, count 0 2006.231.08:21:48.58#ibcon#read 6, iclass 39, count 0 2006.231.08:21:48.58#ibcon#end of sib2, iclass 39, count 0 2006.231.08:21:48.58#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:21:48.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:21:48.58#ibcon#[25=USB\r\n] 2006.231.08:21:48.58#ibcon#*before write, iclass 39, count 0 2006.231.08:21:48.58#ibcon#enter sib2, iclass 39, count 0 2006.231.08:21:48.58#ibcon#flushed, iclass 39, count 0 2006.231.08:21:48.58#ibcon#about to write, iclass 39, count 0 2006.231.08:21:48.58#ibcon#wrote, iclass 39, count 0 2006.231.08:21:48.58#ibcon#about to read 3, iclass 39, count 0 2006.231.08:21:48.61#ibcon#read 3, iclass 39, count 0 2006.231.08:21:48.61#ibcon#about to read 4, iclass 39, count 0 2006.231.08:21:48.61#ibcon#read 4, iclass 39, count 0 2006.231.08:21:48.61#ibcon#about to read 5, iclass 39, count 0 2006.231.08:21:48.61#ibcon#read 5, iclass 39, count 0 2006.231.08:21:48.61#ibcon#about to read 6, iclass 39, count 0 2006.231.08:21:48.61#ibcon#read 6, iclass 39, count 0 2006.231.08:21:48.61#ibcon#end of sib2, iclass 39, count 0 2006.231.08:21:48.61#ibcon#*after write, iclass 39, count 0 2006.231.08:21:48.61#ibcon#*before return 0, iclass 39, count 0 2006.231.08:21:48.61#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:21:48.61#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:21:48.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:21:48.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:21:48.61$vc4f8/valo=3,672.99 2006.231.08:21:48.61#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.08:21:48.61#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.08:21:48.61#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:48.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:21:48.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:21:48.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:21:48.61#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:21:48.61#ibcon#first serial, iclass 3, count 0 2006.231.08:21:48.61#ibcon#enter sib2, iclass 3, count 0 2006.231.08:21:48.61#ibcon#flushed, iclass 3, count 0 2006.231.08:21:48.61#ibcon#about to write, iclass 3, count 0 2006.231.08:21:48.61#ibcon#wrote, iclass 3, count 0 2006.231.08:21:48.61#ibcon#about to read 3, iclass 3, count 0 2006.231.08:21:48.63#ibcon#read 3, iclass 3, count 0 2006.231.08:21:48.63#ibcon#about to read 4, iclass 3, count 0 2006.231.08:21:48.63#ibcon#read 4, iclass 3, count 0 2006.231.08:21:48.63#ibcon#about to read 5, iclass 3, count 0 2006.231.08:21:48.63#ibcon#read 5, iclass 3, count 0 2006.231.08:21:48.63#ibcon#about to read 6, iclass 3, count 0 2006.231.08:21:48.63#ibcon#read 6, iclass 3, count 0 2006.231.08:21:48.63#ibcon#end of sib2, iclass 3, count 0 2006.231.08:21:48.63#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:21:48.63#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:21:48.63#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:21:48.63#ibcon#*before write, iclass 3, count 0 2006.231.08:21:48.63#ibcon#enter sib2, iclass 3, count 0 2006.231.08:21:48.63#ibcon#flushed, iclass 3, count 0 2006.231.08:21:48.63#ibcon#about to write, iclass 3, count 0 2006.231.08:21:48.63#ibcon#wrote, iclass 3, count 0 2006.231.08:21:48.63#ibcon#about to read 3, iclass 3, count 0 2006.231.08:21:48.67#ibcon#read 3, iclass 3, count 0 2006.231.08:21:48.67#ibcon#about to read 4, iclass 3, count 0 2006.231.08:21:48.67#ibcon#read 4, iclass 3, count 0 2006.231.08:21:48.67#ibcon#about to read 5, iclass 3, count 0 2006.231.08:21:48.67#ibcon#read 5, iclass 3, count 0 2006.231.08:21:48.67#ibcon#about to read 6, iclass 3, count 0 2006.231.08:21:48.67#ibcon#read 6, iclass 3, count 0 2006.231.08:21:48.67#ibcon#end of sib2, iclass 3, count 0 2006.231.08:21:48.67#ibcon#*after write, iclass 3, count 0 2006.231.08:21:48.67#ibcon#*before return 0, iclass 3, count 0 2006.231.08:21:48.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:21:48.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:21:48.67#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:21:48.67#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:21:48.67$vc4f8/va=3,8 2006.231.08:21:48.67#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.08:21:48.67#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.08:21:48.67#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:48.67#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:21:48.73#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:21:48.73#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:21:48.73#ibcon#enter wrdev, iclass 5, count 2 2006.231.08:21:48.73#ibcon#first serial, iclass 5, count 2 2006.231.08:21:48.73#ibcon#enter sib2, iclass 5, count 2 2006.231.08:21:48.73#ibcon#flushed, iclass 5, count 2 2006.231.08:21:48.73#ibcon#about to write, iclass 5, count 2 2006.231.08:21:48.73#ibcon#wrote, iclass 5, count 2 2006.231.08:21:48.73#ibcon#about to read 3, iclass 5, count 2 2006.231.08:21:48.75#ibcon#read 3, iclass 5, count 2 2006.231.08:21:48.75#ibcon#about to read 4, iclass 5, count 2 2006.231.08:21:48.75#ibcon#read 4, iclass 5, count 2 2006.231.08:21:48.75#ibcon#about to read 5, iclass 5, count 2 2006.231.08:21:48.75#ibcon#read 5, iclass 5, count 2 2006.231.08:21:48.75#ibcon#about to read 6, iclass 5, count 2 2006.231.08:21:48.75#ibcon#read 6, iclass 5, count 2 2006.231.08:21:48.75#ibcon#end of sib2, iclass 5, count 2 2006.231.08:21:48.75#ibcon#*mode == 0, iclass 5, count 2 2006.231.08:21:48.75#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.08:21:48.75#ibcon#[25=AT03-08\r\n] 2006.231.08:21:48.75#ibcon#*before write, iclass 5, count 2 2006.231.08:21:48.75#ibcon#enter sib2, iclass 5, count 2 2006.231.08:21:48.75#ibcon#flushed, iclass 5, count 2 2006.231.08:21:48.75#ibcon#about to write, iclass 5, count 2 2006.231.08:21:48.75#ibcon#wrote, iclass 5, count 2 2006.231.08:21:48.75#ibcon#about to read 3, iclass 5, count 2 2006.231.08:21:48.78#ibcon#read 3, iclass 5, count 2 2006.231.08:21:48.78#ibcon#about to read 4, iclass 5, count 2 2006.231.08:21:48.78#ibcon#read 4, iclass 5, count 2 2006.231.08:21:48.78#ibcon#about to read 5, iclass 5, count 2 2006.231.08:21:48.78#ibcon#read 5, iclass 5, count 2 2006.231.08:21:48.78#ibcon#about to read 6, iclass 5, count 2 2006.231.08:21:48.78#ibcon#read 6, iclass 5, count 2 2006.231.08:21:48.78#ibcon#end of sib2, iclass 5, count 2 2006.231.08:21:48.78#ibcon#*after write, iclass 5, count 2 2006.231.08:21:48.78#ibcon#*before return 0, iclass 5, count 2 2006.231.08:21:48.78#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:21:48.78#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:21:48.78#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.08:21:48.78#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:48.78#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:21:48.90#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:21:48.90#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:21:48.90#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:21:48.90#ibcon#first serial, iclass 5, count 0 2006.231.08:21:48.90#ibcon#enter sib2, iclass 5, count 0 2006.231.08:21:48.90#ibcon#flushed, iclass 5, count 0 2006.231.08:21:48.90#ibcon#about to write, iclass 5, count 0 2006.231.08:21:48.90#ibcon#wrote, iclass 5, count 0 2006.231.08:21:48.90#ibcon#about to read 3, iclass 5, count 0 2006.231.08:21:48.92#ibcon#read 3, iclass 5, count 0 2006.231.08:21:48.92#ibcon#about to read 4, iclass 5, count 0 2006.231.08:21:48.92#ibcon#read 4, iclass 5, count 0 2006.231.08:21:48.92#ibcon#about to read 5, iclass 5, count 0 2006.231.08:21:48.92#ibcon#read 5, iclass 5, count 0 2006.231.08:21:48.92#ibcon#about to read 6, iclass 5, count 0 2006.231.08:21:48.92#ibcon#read 6, iclass 5, count 0 2006.231.08:21:48.92#ibcon#end of sib2, iclass 5, count 0 2006.231.08:21:48.92#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:21:48.92#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:21:48.92#ibcon#[25=USB\r\n] 2006.231.08:21:48.92#ibcon#*before write, iclass 5, count 0 2006.231.08:21:48.92#ibcon#enter sib2, iclass 5, count 0 2006.231.08:21:48.92#ibcon#flushed, iclass 5, count 0 2006.231.08:21:48.92#ibcon#about to write, iclass 5, count 0 2006.231.08:21:48.92#ibcon#wrote, iclass 5, count 0 2006.231.08:21:48.92#ibcon#about to read 3, iclass 5, count 0 2006.231.08:21:48.95#ibcon#read 3, iclass 5, count 0 2006.231.08:21:48.95#ibcon#about to read 4, iclass 5, count 0 2006.231.08:21:48.95#ibcon#read 4, iclass 5, count 0 2006.231.08:21:48.95#ibcon#about to read 5, iclass 5, count 0 2006.231.08:21:48.95#ibcon#read 5, iclass 5, count 0 2006.231.08:21:48.95#ibcon#about to read 6, iclass 5, count 0 2006.231.08:21:48.95#ibcon#read 6, iclass 5, count 0 2006.231.08:21:48.95#ibcon#end of sib2, iclass 5, count 0 2006.231.08:21:48.95#ibcon#*after write, iclass 5, count 0 2006.231.08:21:48.95#ibcon#*before return 0, iclass 5, count 0 2006.231.08:21:48.95#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:21:48.95#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:21:48.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:21:48.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:21:48.95$vc4f8/valo=4,832.99 2006.231.08:21:48.95#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.08:21:48.95#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.08:21:48.95#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:48.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:21:48.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:21:48.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:21:48.95#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:21:48.95#ibcon#first serial, iclass 7, count 0 2006.231.08:21:48.95#ibcon#enter sib2, iclass 7, count 0 2006.231.08:21:48.95#ibcon#flushed, iclass 7, count 0 2006.231.08:21:48.95#ibcon#about to write, iclass 7, count 0 2006.231.08:21:48.95#ibcon#wrote, iclass 7, count 0 2006.231.08:21:48.95#ibcon#about to read 3, iclass 7, count 0 2006.231.08:21:48.97#ibcon#read 3, iclass 7, count 0 2006.231.08:21:48.97#ibcon#about to read 4, iclass 7, count 0 2006.231.08:21:48.97#ibcon#read 4, iclass 7, count 0 2006.231.08:21:48.97#ibcon#about to read 5, iclass 7, count 0 2006.231.08:21:48.97#ibcon#read 5, iclass 7, count 0 2006.231.08:21:48.97#ibcon#about to read 6, iclass 7, count 0 2006.231.08:21:48.97#ibcon#read 6, iclass 7, count 0 2006.231.08:21:48.97#ibcon#end of sib2, iclass 7, count 0 2006.231.08:21:48.97#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:21:48.97#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:21:48.97#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:21:48.97#ibcon#*before write, iclass 7, count 0 2006.231.08:21:48.97#ibcon#enter sib2, iclass 7, count 0 2006.231.08:21:48.97#ibcon#flushed, iclass 7, count 0 2006.231.08:21:48.97#ibcon#about to write, iclass 7, count 0 2006.231.08:21:48.97#ibcon#wrote, iclass 7, count 0 2006.231.08:21:48.97#ibcon#about to read 3, iclass 7, count 0 2006.231.08:21:49.01#ibcon#read 3, iclass 7, count 0 2006.231.08:21:49.01#ibcon#about to read 4, iclass 7, count 0 2006.231.08:21:49.01#ibcon#read 4, iclass 7, count 0 2006.231.08:21:49.01#ibcon#about to read 5, iclass 7, count 0 2006.231.08:21:49.01#ibcon#read 5, iclass 7, count 0 2006.231.08:21:49.01#ibcon#about to read 6, iclass 7, count 0 2006.231.08:21:49.01#ibcon#read 6, iclass 7, count 0 2006.231.08:21:49.01#ibcon#end of sib2, iclass 7, count 0 2006.231.08:21:49.01#ibcon#*after write, iclass 7, count 0 2006.231.08:21:49.01#ibcon#*before return 0, iclass 7, count 0 2006.231.08:21:49.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:21:49.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:21:49.01#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:21:49.01#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:21:49.01$vc4f8/va=4,7 2006.231.08:21:49.01#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.08:21:49.01#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.08:21:49.01#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:49.01#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:21:49.07#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:21:49.07#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:21:49.07#ibcon#enter wrdev, iclass 11, count 2 2006.231.08:21:49.07#ibcon#first serial, iclass 11, count 2 2006.231.08:21:49.07#ibcon#enter sib2, iclass 11, count 2 2006.231.08:21:49.07#ibcon#flushed, iclass 11, count 2 2006.231.08:21:49.07#ibcon#about to write, iclass 11, count 2 2006.231.08:21:49.07#ibcon#wrote, iclass 11, count 2 2006.231.08:21:49.07#ibcon#about to read 3, iclass 11, count 2 2006.231.08:21:49.09#ibcon#read 3, iclass 11, count 2 2006.231.08:21:49.09#ibcon#about to read 4, iclass 11, count 2 2006.231.08:21:49.09#ibcon#read 4, iclass 11, count 2 2006.231.08:21:49.09#ibcon#about to read 5, iclass 11, count 2 2006.231.08:21:49.09#ibcon#read 5, iclass 11, count 2 2006.231.08:21:49.09#ibcon#about to read 6, iclass 11, count 2 2006.231.08:21:49.09#ibcon#read 6, iclass 11, count 2 2006.231.08:21:49.09#ibcon#end of sib2, iclass 11, count 2 2006.231.08:21:49.09#ibcon#*mode == 0, iclass 11, count 2 2006.231.08:21:49.09#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.08:21:49.09#ibcon#[25=AT04-07\r\n] 2006.231.08:21:49.09#ibcon#*before write, iclass 11, count 2 2006.231.08:21:49.09#ibcon#enter sib2, iclass 11, count 2 2006.231.08:21:49.09#ibcon#flushed, iclass 11, count 2 2006.231.08:21:49.09#ibcon#about to write, iclass 11, count 2 2006.231.08:21:49.09#ibcon#wrote, iclass 11, count 2 2006.231.08:21:49.09#ibcon#about to read 3, iclass 11, count 2 2006.231.08:21:49.12#ibcon#read 3, iclass 11, count 2 2006.231.08:21:49.12#ibcon#about to read 4, iclass 11, count 2 2006.231.08:21:49.12#ibcon#read 4, iclass 11, count 2 2006.231.08:21:49.12#ibcon#about to read 5, iclass 11, count 2 2006.231.08:21:49.12#ibcon#read 5, iclass 11, count 2 2006.231.08:21:49.12#ibcon#about to read 6, iclass 11, count 2 2006.231.08:21:49.12#ibcon#read 6, iclass 11, count 2 2006.231.08:21:49.12#ibcon#end of sib2, iclass 11, count 2 2006.231.08:21:49.12#ibcon#*after write, iclass 11, count 2 2006.231.08:21:49.12#ibcon#*before return 0, iclass 11, count 2 2006.231.08:21:49.12#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:21:49.12#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:21:49.12#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.08:21:49.12#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:49.12#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:21:49.24#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:21:49.24#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:21:49.24#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:21:49.24#ibcon#first serial, iclass 11, count 0 2006.231.08:21:49.24#ibcon#enter sib2, iclass 11, count 0 2006.231.08:21:49.24#ibcon#flushed, iclass 11, count 0 2006.231.08:21:49.24#ibcon#about to write, iclass 11, count 0 2006.231.08:21:49.24#ibcon#wrote, iclass 11, count 0 2006.231.08:21:49.24#ibcon#about to read 3, iclass 11, count 0 2006.231.08:21:49.26#ibcon#read 3, iclass 11, count 0 2006.231.08:21:49.26#ibcon#about to read 4, iclass 11, count 0 2006.231.08:21:49.26#ibcon#read 4, iclass 11, count 0 2006.231.08:21:49.26#ibcon#about to read 5, iclass 11, count 0 2006.231.08:21:49.26#ibcon#read 5, iclass 11, count 0 2006.231.08:21:49.26#ibcon#about to read 6, iclass 11, count 0 2006.231.08:21:49.26#ibcon#read 6, iclass 11, count 0 2006.231.08:21:49.26#ibcon#end of sib2, iclass 11, count 0 2006.231.08:21:49.26#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:21:49.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:21:49.26#ibcon#[25=USB\r\n] 2006.231.08:21:49.26#ibcon#*before write, iclass 11, count 0 2006.231.08:21:49.26#ibcon#enter sib2, iclass 11, count 0 2006.231.08:21:49.26#ibcon#flushed, iclass 11, count 0 2006.231.08:21:49.26#ibcon#about to write, iclass 11, count 0 2006.231.08:21:49.26#ibcon#wrote, iclass 11, count 0 2006.231.08:21:49.26#ibcon#about to read 3, iclass 11, count 0 2006.231.08:21:49.29#ibcon#read 3, iclass 11, count 0 2006.231.08:21:49.29#ibcon#about to read 4, iclass 11, count 0 2006.231.08:21:49.29#ibcon#read 4, iclass 11, count 0 2006.231.08:21:49.29#ibcon#about to read 5, iclass 11, count 0 2006.231.08:21:49.29#ibcon#read 5, iclass 11, count 0 2006.231.08:21:49.29#ibcon#about to read 6, iclass 11, count 0 2006.231.08:21:49.29#ibcon#read 6, iclass 11, count 0 2006.231.08:21:49.29#ibcon#end of sib2, iclass 11, count 0 2006.231.08:21:49.29#ibcon#*after write, iclass 11, count 0 2006.231.08:21:49.29#ibcon#*before return 0, iclass 11, count 0 2006.231.08:21:49.29#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:21:49.29#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:21:49.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:21:49.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:21:49.29$vc4f8/valo=5,652.99 2006.231.08:21:49.29#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.08:21:49.29#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.08:21:49.29#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:49.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:21:49.29#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:21:49.29#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:21:49.29#ibcon#enter wrdev, iclass 13, count 0 2006.231.08:21:49.29#ibcon#first serial, iclass 13, count 0 2006.231.08:21:49.29#ibcon#enter sib2, iclass 13, count 0 2006.231.08:21:49.29#ibcon#flushed, iclass 13, count 0 2006.231.08:21:49.29#ibcon#about to write, iclass 13, count 0 2006.231.08:21:49.29#ibcon#wrote, iclass 13, count 0 2006.231.08:21:49.29#ibcon#about to read 3, iclass 13, count 0 2006.231.08:21:49.31#ibcon#read 3, iclass 13, count 0 2006.231.08:21:49.31#ibcon#about to read 4, iclass 13, count 0 2006.231.08:21:49.31#ibcon#read 4, iclass 13, count 0 2006.231.08:21:49.31#ibcon#about to read 5, iclass 13, count 0 2006.231.08:21:49.31#ibcon#read 5, iclass 13, count 0 2006.231.08:21:49.31#ibcon#about to read 6, iclass 13, count 0 2006.231.08:21:49.31#ibcon#read 6, iclass 13, count 0 2006.231.08:21:49.31#ibcon#end of sib2, iclass 13, count 0 2006.231.08:21:49.31#ibcon#*mode == 0, iclass 13, count 0 2006.231.08:21:49.31#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.08:21:49.31#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:21:49.31#ibcon#*before write, iclass 13, count 0 2006.231.08:21:49.31#ibcon#enter sib2, iclass 13, count 0 2006.231.08:21:49.31#ibcon#flushed, iclass 13, count 0 2006.231.08:21:49.31#ibcon#about to write, iclass 13, count 0 2006.231.08:21:49.31#ibcon#wrote, iclass 13, count 0 2006.231.08:21:49.31#ibcon#about to read 3, iclass 13, count 0 2006.231.08:21:49.35#ibcon#read 3, iclass 13, count 0 2006.231.08:21:49.35#ibcon#about to read 4, iclass 13, count 0 2006.231.08:21:49.35#ibcon#read 4, iclass 13, count 0 2006.231.08:21:49.35#ibcon#about to read 5, iclass 13, count 0 2006.231.08:21:49.35#ibcon#read 5, iclass 13, count 0 2006.231.08:21:49.35#ibcon#about to read 6, iclass 13, count 0 2006.231.08:21:49.35#ibcon#read 6, iclass 13, count 0 2006.231.08:21:49.35#ibcon#end of sib2, iclass 13, count 0 2006.231.08:21:49.35#ibcon#*after write, iclass 13, count 0 2006.231.08:21:49.35#ibcon#*before return 0, iclass 13, count 0 2006.231.08:21:49.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:21:49.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:21:49.35#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.08:21:49.35#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.08:21:49.35$vc4f8/va=5,7 2006.231.08:21:49.35#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.08:21:49.35#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.08:21:49.35#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:49.35#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:21:49.41#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:21:49.41#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:21:49.41#ibcon#enter wrdev, iclass 15, count 2 2006.231.08:21:49.41#ibcon#first serial, iclass 15, count 2 2006.231.08:21:49.41#ibcon#enter sib2, iclass 15, count 2 2006.231.08:21:49.41#ibcon#flushed, iclass 15, count 2 2006.231.08:21:49.41#ibcon#about to write, iclass 15, count 2 2006.231.08:21:49.41#ibcon#wrote, iclass 15, count 2 2006.231.08:21:49.41#ibcon#about to read 3, iclass 15, count 2 2006.231.08:21:49.43#ibcon#read 3, iclass 15, count 2 2006.231.08:21:49.43#ibcon#about to read 4, iclass 15, count 2 2006.231.08:21:49.43#ibcon#read 4, iclass 15, count 2 2006.231.08:21:49.43#ibcon#about to read 5, iclass 15, count 2 2006.231.08:21:49.43#ibcon#read 5, iclass 15, count 2 2006.231.08:21:49.43#ibcon#about to read 6, iclass 15, count 2 2006.231.08:21:49.43#ibcon#read 6, iclass 15, count 2 2006.231.08:21:49.43#ibcon#end of sib2, iclass 15, count 2 2006.231.08:21:49.43#ibcon#*mode == 0, iclass 15, count 2 2006.231.08:21:49.43#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.08:21:49.43#ibcon#[25=AT05-07\r\n] 2006.231.08:21:49.43#ibcon#*before write, iclass 15, count 2 2006.231.08:21:49.43#ibcon#enter sib2, iclass 15, count 2 2006.231.08:21:49.43#ibcon#flushed, iclass 15, count 2 2006.231.08:21:49.43#ibcon#about to write, iclass 15, count 2 2006.231.08:21:49.43#ibcon#wrote, iclass 15, count 2 2006.231.08:21:49.43#ibcon#about to read 3, iclass 15, count 2 2006.231.08:21:49.46#ibcon#read 3, iclass 15, count 2 2006.231.08:21:49.46#ibcon#about to read 4, iclass 15, count 2 2006.231.08:21:49.46#ibcon#read 4, iclass 15, count 2 2006.231.08:21:49.46#ibcon#about to read 5, iclass 15, count 2 2006.231.08:21:49.46#ibcon#read 5, iclass 15, count 2 2006.231.08:21:49.46#ibcon#about to read 6, iclass 15, count 2 2006.231.08:21:49.46#ibcon#read 6, iclass 15, count 2 2006.231.08:21:49.46#ibcon#end of sib2, iclass 15, count 2 2006.231.08:21:49.46#ibcon#*after write, iclass 15, count 2 2006.231.08:21:49.46#ibcon#*before return 0, iclass 15, count 2 2006.231.08:21:49.46#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:21:49.46#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:21:49.46#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.08:21:49.46#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:49.46#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:21:49.58#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:21:49.58#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:21:49.58#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:21:49.58#ibcon#first serial, iclass 15, count 0 2006.231.08:21:49.58#ibcon#enter sib2, iclass 15, count 0 2006.231.08:21:49.58#ibcon#flushed, iclass 15, count 0 2006.231.08:21:49.58#ibcon#about to write, iclass 15, count 0 2006.231.08:21:49.58#ibcon#wrote, iclass 15, count 0 2006.231.08:21:49.58#ibcon#about to read 3, iclass 15, count 0 2006.231.08:21:49.61#ibcon#read 3, iclass 15, count 0 2006.231.08:21:49.61#ibcon#about to read 4, iclass 15, count 0 2006.231.08:21:49.61#ibcon#read 4, iclass 15, count 0 2006.231.08:21:49.61#ibcon#about to read 5, iclass 15, count 0 2006.231.08:21:49.61#ibcon#read 5, iclass 15, count 0 2006.231.08:21:49.61#ibcon#about to read 6, iclass 15, count 0 2006.231.08:21:49.61#ibcon#read 6, iclass 15, count 0 2006.231.08:21:49.61#ibcon#end of sib2, iclass 15, count 0 2006.231.08:21:49.61#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:21:49.61#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:21:49.61#ibcon#[25=USB\r\n] 2006.231.08:21:49.61#ibcon#*before write, iclass 15, count 0 2006.231.08:21:49.61#ibcon#enter sib2, iclass 15, count 0 2006.231.08:21:49.61#ibcon#flushed, iclass 15, count 0 2006.231.08:21:49.61#ibcon#about to write, iclass 15, count 0 2006.231.08:21:49.61#ibcon#wrote, iclass 15, count 0 2006.231.08:21:49.61#ibcon#about to read 3, iclass 15, count 0 2006.231.08:21:49.64#ibcon#read 3, iclass 15, count 0 2006.231.08:21:49.64#ibcon#about to read 4, iclass 15, count 0 2006.231.08:21:49.64#ibcon#read 4, iclass 15, count 0 2006.231.08:21:49.64#ibcon#about to read 5, iclass 15, count 0 2006.231.08:21:49.64#ibcon#read 5, iclass 15, count 0 2006.231.08:21:49.64#ibcon#about to read 6, iclass 15, count 0 2006.231.08:21:49.64#ibcon#read 6, iclass 15, count 0 2006.231.08:21:49.64#ibcon#end of sib2, iclass 15, count 0 2006.231.08:21:49.64#ibcon#*after write, iclass 15, count 0 2006.231.08:21:49.64#ibcon#*before return 0, iclass 15, count 0 2006.231.08:21:49.64#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:21:49.64#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:21:49.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:21:49.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:21:49.64$vc4f8/valo=6,772.99 2006.231.08:21:49.64#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.08:21:49.64#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.08:21:49.64#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:49.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:21:49.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:21:49.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:21:49.64#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:21:49.64#ibcon#first serial, iclass 17, count 0 2006.231.08:21:49.64#ibcon#enter sib2, iclass 17, count 0 2006.231.08:21:49.64#ibcon#flushed, iclass 17, count 0 2006.231.08:21:49.64#ibcon#about to write, iclass 17, count 0 2006.231.08:21:49.64#ibcon#wrote, iclass 17, count 0 2006.231.08:21:49.64#ibcon#about to read 3, iclass 17, count 0 2006.231.08:21:49.66#ibcon#read 3, iclass 17, count 0 2006.231.08:21:49.66#ibcon#about to read 4, iclass 17, count 0 2006.231.08:21:49.66#ibcon#read 4, iclass 17, count 0 2006.231.08:21:49.66#ibcon#about to read 5, iclass 17, count 0 2006.231.08:21:49.66#ibcon#read 5, iclass 17, count 0 2006.231.08:21:49.66#ibcon#about to read 6, iclass 17, count 0 2006.231.08:21:49.66#ibcon#read 6, iclass 17, count 0 2006.231.08:21:49.66#ibcon#end of sib2, iclass 17, count 0 2006.231.08:21:49.66#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:21:49.66#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:21:49.66#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:21:49.66#ibcon#*before write, iclass 17, count 0 2006.231.08:21:49.66#ibcon#enter sib2, iclass 17, count 0 2006.231.08:21:49.66#ibcon#flushed, iclass 17, count 0 2006.231.08:21:49.66#ibcon#about to write, iclass 17, count 0 2006.231.08:21:49.66#ibcon#wrote, iclass 17, count 0 2006.231.08:21:49.66#ibcon#about to read 3, iclass 17, count 0 2006.231.08:21:49.70#ibcon#read 3, iclass 17, count 0 2006.231.08:21:49.70#ibcon#about to read 4, iclass 17, count 0 2006.231.08:21:49.70#ibcon#read 4, iclass 17, count 0 2006.231.08:21:49.70#ibcon#about to read 5, iclass 17, count 0 2006.231.08:21:49.70#ibcon#read 5, iclass 17, count 0 2006.231.08:21:49.70#ibcon#about to read 6, iclass 17, count 0 2006.231.08:21:49.70#ibcon#read 6, iclass 17, count 0 2006.231.08:21:49.70#ibcon#end of sib2, iclass 17, count 0 2006.231.08:21:49.70#ibcon#*after write, iclass 17, count 0 2006.231.08:21:49.70#ibcon#*before return 0, iclass 17, count 0 2006.231.08:21:49.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:21:49.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:21:49.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:21:49.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:21:49.70$vc4f8/va=6,6 2006.231.08:21:49.70#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.231.08:21:49.70#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.231.08:21:49.70#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:49.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:21:49.76#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:21:49.76#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:21:49.76#ibcon#enter wrdev, iclass 19, count 2 2006.231.08:21:49.76#ibcon#first serial, iclass 19, count 2 2006.231.08:21:49.76#ibcon#enter sib2, iclass 19, count 2 2006.231.08:21:49.76#ibcon#flushed, iclass 19, count 2 2006.231.08:21:49.76#ibcon#about to write, iclass 19, count 2 2006.231.08:21:49.76#ibcon#wrote, iclass 19, count 2 2006.231.08:21:49.76#ibcon#about to read 3, iclass 19, count 2 2006.231.08:21:49.78#ibcon#read 3, iclass 19, count 2 2006.231.08:21:49.78#ibcon#about to read 4, iclass 19, count 2 2006.231.08:21:49.78#ibcon#read 4, iclass 19, count 2 2006.231.08:21:49.78#ibcon#about to read 5, iclass 19, count 2 2006.231.08:21:49.78#ibcon#read 5, iclass 19, count 2 2006.231.08:21:49.78#ibcon#about to read 6, iclass 19, count 2 2006.231.08:21:49.78#ibcon#read 6, iclass 19, count 2 2006.231.08:21:49.78#ibcon#end of sib2, iclass 19, count 2 2006.231.08:21:49.78#ibcon#*mode == 0, iclass 19, count 2 2006.231.08:21:49.78#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.231.08:21:49.78#ibcon#[25=AT06-06\r\n] 2006.231.08:21:49.78#ibcon#*before write, iclass 19, count 2 2006.231.08:21:49.78#ibcon#enter sib2, iclass 19, count 2 2006.231.08:21:49.78#ibcon#flushed, iclass 19, count 2 2006.231.08:21:49.78#ibcon#about to write, iclass 19, count 2 2006.231.08:21:49.78#ibcon#wrote, iclass 19, count 2 2006.231.08:21:49.78#ibcon#about to read 3, iclass 19, count 2 2006.231.08:21:49.81#ibcon#read 3, iclass 19, count 2 2006.231.08:21:49.81#ibcon#about to read 4, iclass 19, count 2 2006.231.08:21:49.81#ibcon#read 4, iclass 19, count 2 2006.231.08:21:49.81#ibcon#about to read 5, iclass 19, count 2 2006.231.08:21:49.81#ibcon#read 5, iclass 19, count 2 2006.231.08:21:49.81#ibcon#about to read 6, iclass 19, count 2 2006.231.08:21:49.81#ibcon#read 6, iclass 19, count 2 2006.231.08:21:49.81#ibcon#end of sib2, iclass 19, count 2 2006.231.08:21:49.81#ibcon#*after write, iclass 19, count 2 2006.231.08:21:49.81#ibcon#*before return 0, iclass 19, count 2 2006.231.08:21:49.81#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:21:49.81#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.231.08:21:49.81#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.231.08:21:49.81#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:49.81#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:21:49.93#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:21:49.93#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:21:49.93#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:21:49.93#ibcon#first serial, iclass 19, count 0 2006.231.08:21:49.93#ibcon#enter sib2, iclass 19, count 0 2006.231.08:21:49.93#ibcon#flushed, iclass 19, count 0 2006.231.08:21:49.93#ibcon#about to write, iclass 19, count 0 2006.231.08:21:49.93#ibcon#wrote, iclass 19, count 0 2006.231.08:21:49.93#ibcon#about to read 3, iclass 19, count 0 2006.231.08:21:49.95#ibcon#read 3, iclass 19, count 0 2006.231.08:21:49.95#ibcon#about to read 4, iclass 19, count 0 2006.231.08:21:49.95#ibcon#read 4, iclass 19, count 0 2006.231.08:21:49.95#ibcon#about to read 5, iclass 19, count 0 2006.231.08:21:49.95#ibcon#read 5, iclass 19, count 0 2006.231.08:21:49.95#ibcon#about to read 6, iclass 19, count 0 2006.231.08:21:49.95#ibcon#read 6, iclass 19, count 0 2006.231.08:21:49.95#ibcon#end of sib2, iclass 19, count 0 2006.231.08:21:49.95#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:21:49.95#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:21:49.95#ibcon#[25=USB\r\n] 2006.231.08:21:49.95#ibcon#*before write, iclass 19, count 0 2006.231.08:21:49.95#ibcon#enter sib2, iclass 19, count 0 2006.231.08:21:49.95#ibcon#flushed, iclass 19, count 0 2006.231.08:21:49.95#ibcon#about to write, iclass 19, count 0 2006.231.08:21:49.95#ibcon#wrote, iclass 19, count 0 2006.231.08:21:49.95#ibcon#about to read 3, iclass 19, count 0 2006.231.08:21:49.98#ibcon#read 3, iclass 19, count 0 2006.231.08:21:49.98#ibcon#about to read 4, iclass 19, count 0 2006.231.08:21:49.98#ibcon#read 4, iclass 19, count 0 2006.231.08:21:49.98#ibcon#about to read 5, iclass 19, count 0 2006.231.08:21:49.98#ibcon#read 5, iclass 19, count 0 2006.231.08:21:49.98#ibcon#about to read 6, iclass 19, count 0 2006.231.08:21:49.98#ibcon#read 6, iclass 19, count 0 2006.231.08:21:49.98#ibcon#end of sib2, iclass 19, count 0 2006.231.08:21:49.98#ibcon#*after write, iclass 19, count 0 2006.231.08:21:49.98#ibcon#*before return 0, iclass 19, count 0 2006.231.08:21:49.98#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:21:49.98#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.231.08:21:49.98#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:21:49.98#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:21:49.98$vc4f8/valo=7,832.99 2006.231.08:21:49.98#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.231.08:21:49.98#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.231.08:21:49.98#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:49.98#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:21:49.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:21:49.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:21:49.98#ibcon#enter wrdev, iclass 21, count 0 2006.231.08:21:49.98#ibcon#first serial, iclass 21, count 0 2006.231.08:21:49.98#ibcon#enter sib2, iclass 21, count 0 2006.231.08:21:49.98#ibcon#flushed, iclass 21, count 0 2006.231.08:21:49.98#ibcon#about to write, iclass 21, count 0 2006.231.08:21:49.98#ibcon#wrote, iclass 21, count 0 2006.231.08:21:49.98#ibcon#about to read 3, iclass 21, count 0 2006.231.08:21:50.00#ibcon#read 3, iclass 21, count 0 2006.231.08:21:50.00#ibcon#about to read 4, iclass 21, count 0 2006.231.08:21:50.00#ibcon#read 4, iclass 21, count 0 2006.231.08:21:50.00#ibcon#about to read 5, iclass 21, count 0 2006.231.08:21:50.00#ibcon#read 5, iclass 21, count 0 2006.231.08:21:50.00#ibcon#about to read 6, iclass 21, count 0 2006.231.08:21:50.00#ibcon#read 6, iclass 21, count 0 2006.231.08:21:50.00#ibcon#end of sib2, iclass 21, count 0 2006.231.08:21:50.00#ibcon#*mode == 0, iclass 21, count 0 2006.231.08:21:50.00#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.231.08:21:50.00#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:21:50.00#ibcon#*before write, iclass 21, count 0 2006.231.08:21:50.00#ibcon#enter sib2, iclass 21, count 0 2006.231.08:21:50.00#ibcon#flushed, iclass 21, count 0 2006.231.08:21:50.00#ibcon#about to write, iclass 21, count 0 2006.231.08:21:50.00#ibcon#wrote, iclass 21, count 0 2006.231.08:21:50.00#ibcon#about to read 3, iclass 21, count 0 2006.231.08:21:50.04#ibcon#read 3, iclass 21, count 0 2006.231.08:21:50.04#ibcon#about to read 4, iclass 21, count 0 2006.231.08:21:50.04#ibcon#read 4, iclass 21, count 0 2006.231.08:21:50.04#ibcon#about to read 5, iclass 21, count 0 2006.231.08:21:50.04#ibcon#read 5, iclass 21, count 0 2006.231.08:21:50.04#ibcon#about to read 6, iclass 21, count 0 2006.231.08:21:50.04#ibcon#read 6, iclass 21, count 0 2006.231.08:21:50.04#ibcon#end of sib2, iclass 21, count 0 2006.231.08:21:50.04#ibcon#*after write, iclass 21, count 0 2006.231.08:21:50.04#ibcon#*before return 0, iclass 21, count 0 2006.231.08:21:50.04#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:21:50.04#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.231.08:21:50.04#ibcon#about to clear, iclass 21 cls_cnt 0 2006.231.08:21:50.04#ibcon#cleared, iclass 21 cls_cnt 0 2006.231.08:21:50.04$vc4f8/va=7,6 2006.231.08:21:50.04#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.231.08:21:50.04#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.231.08:21:50.04#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:50.04#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:21:50.10#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:21:50.10#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:21:50.10#ibcon#enter wrdev, iclass 23, count 2 2006.231.08:21:50.10#ibcon#first serial, iclass 23, count 2 2006.231.08:21:50.10#ibcon#enter sib2, iclass 23, count 2 2006.231.08:21:50.10#ibcon#flushed, iclass 23, count 2 2006.231.08:21:50.10#ibcon#about to write, iclass 23, count 2 2006.231.08:21:50.10#ibcon#wrote, iclass 23, count 2 2006.231.08:21:50.10#ibcon#about to read 3, iclass 23, count 2 2006.231.08:21:50.12#ibcon#read 3, iclass 23, count 2 2006.231.08:21:50.12#ibcon#about to read 4, iclass 23, count 2 2006.231.08:21:50.12#ibcon#read 4, iclass 23, count 2 2006.231.08:21:50.12#ibcon#about to read 5, iclass 23, count 2 2006.231.08:21:50.12#ibcon#read 5, iclass 23, count 2 2006.231.08:21:50.12#ibcon#about to read 6, iclass 23, count 2 2006.231.08:21:50.12#ibcon#read 6, iclass 23, count 2 2006.231.08:21:50.12#ibcon#end of sib2, iclass 23, count 2 2006.231.08:21:50.12#ibcon#*mode == 0, iclass 23, count 2 2006.231.08:21:50.12#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.231.08:21:50.12#ibcon#[25=AT07-06\r\n] 2006.231.08:21:50.12#ibcon#*before write, iclass 23, count 2 2006.231.08:21:50.12#ibcon#enter sib2, iclass 23, count 2 2006.231.08:21:50.12#ibcon#flushed, iclass 23, count 2 2006.231.08:21:50.12#ibcon#about to write, iclass 23, count 2 2006.231.08:21:50.12#ibcon#wrote, iclass 23, count 2 2006.231.08:21:50.12#ibcon#about to read 3, iclass 23, count 2 2006.231.08:21:50.15#ibcon#read 3, iclass 23, count 2 2006.231.08:21:50.15#ibcon#about to read 4, iclass 23, count 2 2006.231.08:21:50.15#ibcon#read 4, iclass 23, count 2 2006.231.08:21:50.15#ibcon#about to read 5, iclass 23, count 2 2006.231.08:21:50.15#ibcon#read 5, iclass 23, count 2 2006.231.08:21:50.15#ibcon#about to read 6, iclass 23, count 2 2006.231.08:21:50.15#ibcon#read 6, iclass 23, count 2 2006.231.08:21:50.15#ibcon#end of sib2, iclass 23, count 2 2006.231.08:21:50.15#ibcon#*after write, iclass 23, count 2 2006.231.08:21:50.15#ibcon#*before return 0, iclass 23, count 2 2006.231.08:21:50.15#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:21:50.15#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.231.08:21:50.15#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.231.08:21:50.15#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:50.15#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:21:50.27#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:21:50.27#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:21:50.27#ibcon#enter wrdev, iclass 23, count 0 2006.231.08:21:50.27#ibcon#first serial, iclass 23, count 0 2006.231.08:21:50.27#ibcon#enter sib2, iclass 23, count 0 2006.231.08:21:50.27#ibcon#flushed, iclass 23, count 0 2006.231.08:21:50.27#ibcon#about to write, iclass 23, count 0 2006.231.08:21:50.27#ibcon#wrote, iclass 23, count 0 2006.231.08:21:50.27#ibcon#about to read 3, iclass 23, count 0 2006.231.08:21:50.29#ibcon#read 3, iclass 23, count 0 2006.231.08:21:50.29#ibcon#about to read 4, iclass 23, count 0 2006.231.08:21:50.29#ibcon#read 4, iclass 23, count 0 2006.231.08:21:50.29#ibcon#about to read 5, iclass 23, count 0 2006.231.08:21:50.29#ibcon#read 5, iclass 23, count 0 2006.231.08:21:50.29#ibcon#about to read 6, iclass 23, count 0 2006.231.08:21:50.29#ibcon#read 6, iclass 23, count 0 2006.231.08:21:50.29#ibcon#end of sib2, iclass 23, count 0 2006.231.08:21:50.29#ibcon#*mode == 0, iclass 23, count 0 2006.231.08:21:50.29#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.231.08:21:50.29#ibcon#[25=USB\r\n] 2006.231.08:21:50.29#ibcon#*before write, iclass 23, count 0 2006.231.08:21:50.29#ibcon#enter sib2, iclass 23, count 0 2006.231.08:21:50.29#ibcon#flushed, iclass 23, count 0 2006.231.08:21:50.29#ibcon#about to write, iclass 23, count 0 2006.231.08:21:50.29#ibcon#wrote, iclass 23, count 0 2006.231.08:21:50.29#ibcon#about to read 3, iclass 23, count 0 2006.231.08:21:50.32#ibcon#read 3, iclass 23, count 0 2006.231.08:21:50.32#ibcon#about to read 4, iclass 23, count 0 2006.231.08:21:50.32#ibcon#read 4, iclass 23, count 0 2006.231.08:21:50.32#ibcon#about to read 5, iclass 23, count 0 2006.231.08:21:50.32#ibcon#read 5, iclass 23, count 0 2006.231.08:21:50.32#ibcon#about to read 6, iclass 23, count 0 2006.231.08:21:50.32#ibcon#read 6, iclass 23, count 0 2006.231.08:21:50.32#ibcon#end of sib2, iclass 23, count 0 2006.231.08:21:50.32#ibcon#*after write, iclass 23, count 0 2006.231.08:21:50.32#ibcon#*before return 0, iclass 23, count 0 2006.231.08:21:50.32#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:21:50.32#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.231.08:21:50.32#ibcon#about to clear, iclass 23 cls_cnt 0 2006.231.08:21:50.32#ibcon#cleared, iclass 23 cls_cnt 0 2006.231.08:21:50.32$vc4f8/valo=8,852.99 2006.231.08:21:50.32#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.231.08:21:50.32#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.231.08:21:50.32#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:50.32#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:21:50.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:21:50.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:21:50.32#ibcon#enter wrdev, iclass 25, count 0 2006.231.08:21:50.32#ibcon#first serial, iclass 25, count 0 2006.231.08:21:50.32#ibcon#enter sib2, iclass 25, count 0 2006.231.08:21:50.32#ibcon#flushed, iclass 25, count 0 2006.231.08:21:50.32#ibcon#about to write, iclass 25, count 0 2006.231.08:21:50.32#ibcon#wrote, iclass 25, count 0 2006.231.08:21:50.32#ibcon#about to read 3, iclass 25, count 0 2006.231.08:21:50.34#ibcon#read 3, iclass 25, count 0 2006.231.08:21:50.34#ibcon#about to read 4, iclass 25, count 0 2006.231.08:21:50.34#ibcon#read 4, iclass 25, count 0 2006.231.08:21:50.34#ibcon#about to read 5, iclass 25, count 0 2006.231.08:21:50.34#ibcon#read 5, iclass 25, count 0 2006.231.08:21:50.34#ibcon#about to read 6, iclass 25, count 0 2006.231.08:21:50.34#ibcon#read 6, iclass 25, count 0 2006.231.08:21:50.34#ibcon#end of sib2, iclass 25, count 0 2006.231.08:21:50.34#ibcon#*mode == 0, iclass 25, count 0 2006.231.08:21:50.34#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.231.08:21:50.34#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:21:50.34#ibcon#*before write, iclass 25, count 0 2006.231.08:21:50.34#ibcon#enter sib2, iclass 25, count 0 2006.231.08:21:50.34#ibcon#flushed, iclass 25, count 0 2006.231.08:21:50.34#ibcon#about to write, iclass 25, count 0 2006.231.08:21:50.34#ibcon#wrote, iclass 25, count 0 2006.231.08:21:50.34#ibcon#about to read 3, iclass 25, count 0 2006.231.08:21:50.38#ibcon#read 3, iclass 25, count 0 2006.231.08:21:50.38#ibcon#about to read 4, iclass 25, count 0 2006.231.08:21:50.38#ibcon#read 4, iclass 25, count 0 2006.231.08:21:50.38#ibcon#about to read 5, iclass 25, count 0 2006.231.08:21:50.38#ibcon#read 5, iclass 25, count 0 2006.231.08:21:50.38#ibcon#about to read 6, iclass 25, count 0 2006.231.08:21:50.38#ibcon#read 6, iclass 25, count 0 2006.231.08:21:50.38#ibcon#end of sib2, iclass 25, count 0 2006.231.08:21:50.38#ibcon#*after write, iclass 25, count 0 2006.231.08:21:50.38#ibcon#*before return 0, iclass 25, count 0 2006.231.08:21:50.38#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:21:50.38#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.231.08:21:50.38#ibcon#about to clear, iclass 25 cls_cnt 0 2006.231.08:21:50.38#ibcon#cleared, iclass 25 cls_cnt 0 2006.231.08:21:50.38$vc4f8/va=8,6 2006.231.08:21:50.38#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.231.08:21:50.38#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.231.08:21:50.38#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:50.38#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:21:50.44#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:21:50.44#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:21:50.44#ibcon#enter wrdev, iclass 27, count 2 2006.231.08:21:50.44#ibcon#first serial, iclass 27, count 2 2006.231.08:21:50.44#ibcon#enter sib2, iclass 27, count 2 2006.231.08:21:50.44#ibcon#flushed, iclass 27, count 2 2006.231.08:21:50.44#ibcon#about to write, iclass 27, count 2 2006.231.08:21:50.44#ibcon#wrote, iclass 27, count 2 2006.231.08:21:50.44#ibcon#about to read 3, iclass 27, count 2 2006.231.08:21:50.46#ibcon#read 3, iclass 27, count 2 2006.231.08:21:50.46#ibcon#about to read 4, iclass 27, count 2 2006.231.08:21:50.46#ibcon#read 4, iclass 27, count 2 2006.231.08:21:50.46#ibcon#about to read 5, iclass 27, count 2 2006.231.08:21:50.46#ibcon#read 5, iclass 27, count 2 2006.231.08:21:50.46#ibcon#about to read 6, iclass 27, count 2 2006.231.08:21:50.46#ibcon#read 6, iclass 27, count 2 2006.231.08:21:50.46#ibcon#end of sib2, iclass 27, count 2 2006.231.08:21:50.46#ibcon#*mode == 0, iclass 27, count 2 2006.231.08:21:50.46#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.231.08:21:50.46#ibcon#[25=AT08-06\r\n] 2006.231.08:21:50.46#ibcon#*before write, iclass 27, count 2 2006.231.08:21:50.46#ibcon#enter sib2, iclass 27, count 2 2006.231.08:21:50.46#ibcon#flushed, iclass 27, count 2 2006.231.08:21:50.46#ibcon#about to write, iclass 27, count 2 2006.231.08:21:50.46#ibcon#wrote, iclass 27, count 2 2006.231.08:21:50.46#ibcon#about to read 3, iclass 27, count 2 2006.231.08:21:50.49#ibcon#read 3, iclass 27, count 2 2006.231.08:21:50.49#ibcon#about to read 4, iclass 27, count 2 2006.231.08:21:50.49#ibcon#read 4, iclass 27, count 2 2006.231.08:21:50.49#ibcon#about to read 5, iclass 27, count 2 2006.231.08:21:50.49#ibcon#read 5, iclass 27, count 2 2006.231.08:21:50.49#ibcon#about to read 6, iclass 27, count 2 2006.231.08:21:50.49#ibcon#read 6, iclass 27, count 2 2006.231.08:21:50.49#ibcon#end of sib2, iclass 27, count 2 2006.231.08:21:50.49#ibcon#*after write, iclass 27, count 2 2006.231.08:21:50.49#ibcon#*before return 0, iclass 27, count 2 2006.231.08:21:50.49#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:21:50.49#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.231.08:21:50.49#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.231.08:21:50.49#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:50.49#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:21:50.61#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:21:50.61#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:21:50.61#ibcon#enter wrdev, iclass 27, count 0 2006.231.08:21:50.61#ibcon#first serial, iclass 27, count 0 2006.231.08:21:50.61#ibcon#enter sib2, iclass 27, count 0 2006.231.08:21:50.61#ibcon#flushed, iclass 27, count 0 2006.231.08:21:50.61#ibcon#about to write, iclass 27, count 0 2006.231.08:21:50.61#ibcon#wrote, iclass 27, count 0 2006.231.08:21:50.61#ibcon#about to read 3, iclass 27, count 0 2006.231.08:21:50.63#ibcon#read 3, iclass 27, count 0 2006.231.08:21:50.63#ibcon#about to read 4, iclass 27, count 0 2006.231.08:21:50.63#ibcon#read 4, iclass 27, count 0 2006.231.08:21:50.63#ibcon#about to read 5, iclass 27, count 0 2006.231.08:21:50.63#ibcon#read 5, iclass 27, count 0 2006.231.08:21:50.63#ibcon#about to read 6, iclass 27, count 0 2006.231.08:21:50.63#ibcon#read 6, iclass 27, count 0 2006.231.08:21:50.63#ibcon#end of sib2, iclass 27, count 0 2006.231.08:21:50.63#ibcon#*mode == 0, iclass 27, count 0 2006.231.08:21:50.63#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.231.08:21:50.63#ibcon#[25=USB\r\n] 2006.231.08:21:50.63#ibcon#*before write, iclass 27, count 0 2006.231.08:21:50.63#ibcon#enter sib2, iclass 27, count 0 2006.231.08:21:50.63#ibcon#flushed, iclass 27, count 0 2006.231.08:21:50.63#ibcon#about to write, iclass 27, count 0 2006.231.08:21:50.63#ibcon#wrote, iclass 27, count 0 2006.231.08:21:50.63#ibcon#about to read 3, iclass 27, count 0 2006.231.08:21:50.66#ibcon#read 3, iclass 27, count 0 2006.231.08:21:50.66#ibcon#about to read 4, iclass 27, count 0 2006.231.08:21:50.66#ibcon#read 4, iclass 27, count 0 2006.231.08:21:50.66#ibcon#about to read 5, iclass 27, count 0 2006.231.08:21:50.66#ibcon#read 5, iclass 27, count 0 2006.231.08:21:50.66#ibcon#about to read 6, iclass 27, count 0 2006.231.08:21:50.66#ibcon#read 6, iclass 27, count 0 2006.231.08:21:50.66#ibcon#end of sib2, iclass 27, count 0 2006.231.08:21:50.66#ibcon#*after write, iclass 27, count 0 2006.231.08:21:50.66#ibcon#*before return 0, iclass 27, count 0 2006.231.08:21:50.66#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:21:50.66#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.231.08:21:50.66#ibcon#about to clear, iclass 27 cls_cnt 0 2006.231.08:21:50.66#ibcon#cleared, iclass 27 cls_cnt 0 2006.231.08:21:50.66$vc4f8/vblo=1,632.99 2006.231.08:21:50.66#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.231.08:21:50.66#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.231.08:21:50.66#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:50.66#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:21:50.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:21:50.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:21:50.66#ibcon#enter wrdev, iclass 29, count 0 2006.231.08:21:50.66#ibcon#first serial, iclass 29, count 0 2006.231.08:21:50.66#ibcon#enter sib2, iclass 29, count 0 2006.231.08:21:50.66#ibcon#flushed, iclass 29, count 0 2006.231.08:21:50.66#ibcon#about to write, iclass 29, count 0 2006.231.08:21:50.66#ibcon#wrote, iclass 29, count 0 2006.231.08:21:50.66#ibcon#about to read 3, iclass 29, count 0 2006.231.08:21:50.68#ibcon#read 3, iclass 29, count 0 2006.231.08:21:50.68#ibcon#about to read 4, iclass 29, count 0 2006.231.08:21:50.68#ibcon#read 4, iclass 29, count 0 2006.231.08:21:50.68#ibcon#about to read 5, iclass 29, count 0 2006.231.08:21:50.68#ibcon#read 5, iclass 29, count 0 2006.231.08:21:50.68#ibcon#about to read 6, iclass 29, count 0 2006.231.08:21:50.68#ibcon#read 6, iclass 29, count 0 2006.231.08:21:50.68#ibcon#end of sib2, iclass 29, count 0 2006.231.08:21:50.68#ibcon#*mode == 0, iclass 29, count 0 2006.231.08:21:50.68#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.231.08:21:50.68#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:21:50.68#ibcon#*before write, iclass 29, count 0 2006.231.08:21:50.68#ibcon#enter sib2, iclass 29, count 0 2006.231.08:21:50.68#ibcon#flushed, iclass 29, count 0 2006.231.08:21:50.68#ibcon#about to write, iclass 29, count 0 2006.231.08:21:50.68#ibcon#wrote, iclass 29, count 0 2006.231.08:21:50.68#ibcon#about to read 3, iclass 29, count 0 2006.231.08:21:50.72#ibcon#read 3, iclass 29, count 0 2006.231.08:21:50.72#ibcon#about to read 4, iclass 29, count 0 2006.231.08:21:50.72#ibcon#read 4, iclass 29, count 0 2006.231.08:21:50.72#ibcon#about to read 5, iclass 29, count 0 2006.231.08:21:50.72#ibcon#read 5, iclass 29, count 0 2006.231.08:21:50.72#ibcon#about to read 6, iclass 29, count 0 2006.231.08:21:50.72#ibcon#read 6, iclass 29, count 0 2006.231.08:21:50.72#ibcon#end of sib2, iclass 29, count 0 2006.231.08:21:50.72#ibcon#*after write, iclass 29, count 0 2006.231.08:21:50.72#ibcon#*before return 0, iclass 29, count 0 2006.231.08:21:50.72#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:21:50.72#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.231.08:21:50.72#ibcon#about to clear, iclass 29 cls_cnt 0 2006.231.08:21:50.72#ibcon#cleared, iclass 29 cls_cnt 0 2006.231.08:21:50.72$vc4f8/vb=1,4 2006.231.08:21:50.72#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.231.08:21:50.72#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.231.08:21:50.72#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:50.72#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:21:50.72#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:21:50.72#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:21:50.72#ibcon#enter wrdev, iclass 31, count 2 2006.231.08:21:50.72#ibcon#first serial, iclass 31, count 2 2006.231.08:21:50.72#ibcon#enter sib2, iclass 31, count 2 2006.231.08:21:50.72#ibcon#flushed, iclass 31, count 2 2006.231.08:21:50.72#ibcon#about to write, iclass 31, count 2 2006.231.08:21:50.72#ibcon#wrote, iclass 31, count 2 2006.231.08:21:50.72#ibcon#about to read 3, iclass 31, count 2 2006.231.08:21:50.74#ibcon#read 3, iclass 31, count 2 2006.231.08:21:50.74#ibcon#about to read 4, iclass 31, count 2 2006.231.08:21:50.74#ibcon#read 4, iclass 31, count 2 2006.231.08:21:50.74#ibcon#about to read 5, iclass 31, count 2 2006.231.08:21:50.74#ibcon#read 5, iclass 31, count 2 2006.231.08:21:50.74#ibcon#about to read 6, iclass 31, count 2 2006.231.08:21:50.74#ibcon#read 6, iclass 31, count 2 2006.231.08:21:50.74#ibcon#end of sib2, iclass 31, count 2 2006.231.08:21:50.74#ibcon#*mode == 0, iclass 31, count 2 2006.231.08:21:50.74#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.231.08:21:50.74#ibcon#[27=AT01-04\r\n] 2006.231.08:21:50.74#ibcon#*before write, iclass 31, count 2 2006.231.08:21:50.74#ibcon#enter sib2, iclass 31, count 2 2006.231.08:21:50.74#ibcon#flushed, iclass 31, count 2 2006.231.08:21:50.74#ibcon#about to write, iclass 31, count 2 2006.231.08:21:50.74#ibcon#wrote, iclass 31, count 2 2006.231.08:21:50.74#ibcon#about to read 3, iclass 31, count 2 2006.231.08:21:50.77#ibcon#read 3, iclass 31, count 2 2006.231.08:21:50.77#ibcon#about to read 4, iclass 31, count 2 2006.231.08:21:50.77#ibcon#read 4, iclass 31, count 2 2006.231.08:21:50.77#ibcon#about to read 5, iclass 31, count 2 2006.231.08:21:50.77#ibcon#read 5, iclass 31, count 2 2006.231.08:21:50.77#ibcon#about to read 6, iclass 31, count 2 2006.231.08:21:50.77#ibcon#read 6, iclass 31, count 2 2006.231.08:21:50.77#ibcon#end of sib2, iclass 31, count 2 2006.231.08:21:50.77#ibcon#*after write, iclass 31, count 2 2006.231.08:21:50.77#ibcon#*before return 0, iclass 31, count 2 2006.231.08:21:50.77#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:21:50.77#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.231.08:21:50.77#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.231.08:21:50.77#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:50.77#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:21:50.89#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:21:50.89#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:21:50.89#ibcon#enter wrdev, iclass 31, count 0 2006.231.08:21:50.89#ibcon#first serial, iclass 31, count 0 2006.231.08:21:50.89#ibcon#enter sib2, iclass 31, count 0 2006.231.08:21:50.89#ibcon#flushed, iclass 31, count 0 2006.231.08:21:50.89#ibcon#about to write, iclass 31, count 0 2006.231.08:21:50.89#ibcon#wrote, iclass 31, count 0 2006.231.08:21:50.89#ibcon#about to read 3, iclass 31, count 0 2006.231.08:21:50.91#ibcon#read 3, iclass 31, count 0 2006.231.08:21:50.91#ibcon#about to read 4, iclass 31, count 0 2006.231.08:21:50.91#ibcon#read 4, iclass 31, count 0 2006.231.08:21:50.91#ibcon#about to read 5, iclass 31, count 0 2006.231.08:21:50.91#ibcon#read 5, iclass 31, count 0 2006.231.08:21:50.91#ibcon#about to read 6, iclass 31, count 0 2006.231.08:21:50.91#ibcon#read 6, iclass 31, count 0 2006.231.08:21:50.91#ibcon#end of sib2, iclass 31, count 0 2006.231.08:21:50.91#ibcon#*mode == 0, iclass 31, count 0 2006.231.08:21:50.91#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.231.08:21:50.91#ibcon#[27=USB\r\n] 2006.231.08:21:50.91#ibcon#*before write, iclass 31, count 0 2006.231.08:21:50.91#ibcon#enter sib2, iclass 31, count 0 2006.231.08:21:50.91#ibcon#flushed, iclass 31, count 0 2006.231.08:21:50.91#ibcon#about to write, iclass 31, count 0 2006.231.08:21:50.91#ibcon#wrote, iclass 31, count 0 2006.231.08:21:50.91#ibcon#about to read 3, iclass 31, count 0 2006.231.08:21:50.94#ibcon#read 3, iclass 31, count 0 2006.231.08:21:50.94#ibcon#about to read 4, iclass 31, count 0 2006.231.08:21:50.94#ibcon#read 4, iclass 31, count 0 2006.231.08:21:50.94#ibcon#about to read 5, iclass 31, count 0 2006.231.08:21:50.94#ibcon#read 5, iclass 31, count 0 2006.231.08:21:50.94#ibcon#about to read 6, iclass 31, count 0 2006.231.08:21:50.94#ibcon#read 6, iclass 31, count 0 2006.231.08:21:50.94#ibcon#end of sib2, iclass 31, count 0 2006.231.08:21:50.94#ibcon#*after write, iclass 31, count 0 2006.231.08:21:50.94#ibcon#*before return 0, iclass 31, count 0 2006.231.08:21:50.94#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:21:50.94#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.231.08:21:50.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.231.08:21:50.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.231.08:21:50.94$vc4f8/vblo=2,640.99 2006.231.08:21:50.94#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.231.08:21:50.94#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.231.08:21:50.94#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:50.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:21:50.94#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:21:50.94#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:21:50.94#ibcon#enter wrdev, iclass 33, count 0 2006.231.08:21:50.94#ibcon#first serial, iclass 33, count 0 2006.231.08:21:50.94#ibcon#enter sib2, iclass 33, count 0 2006.231.08:21:50.94#ibcon#flushed, iclass 33, count 0 2006.231.08:21:50.94#ibcon#about to write, iclass 33, count 0 2006.231.08:21:50.94#ibcon#wrote, iclass 33, count 0 2006.231.08:21:50.94#ibcon#about to read 3, iclass 33, count 0 2006.231.08:21:50.96#ibcon#read 3, iclass 33, count 0 2006.231.08:21:50.96#ibcon#about to read 4, iclass 33, count 0 2006.231.08:21:50.96#ibcon#read 4, iclass 33, count 0 2006.231.08:21:50.96#ibcon#about to read 5, iclass 33, count 0 2006.231.08:21:50.96#ibcon#read 5, iclass 33, count 0 2006.231.08:21:50.96#ibcon#about to read 6, iclass 33, count 0 2006.231.08:21:50.96#ibcon#read 6, iclass 33, count 0 2006.231.08:21:50.96#ibcon#end of sib2, iclass 33, count 0 2006.231.08:21:50.96#ibcon#*mode == 0, iclass 33, count 0 2006.231.08:21:50.96#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.231.08:21:50.96#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:21:50.96#ibcon#*before write, iclass 33, count 0 2006.231.08:21:50.96#ibcon#enter sib2, iclass 33, count 0 2006.231.08:21:50.96#ibcon#flushed, iclass 33, count 0 2006.231.08:21:50.96#ibcon#about to write, iclass 33, count 0 2006.231.08:21:50.96#ibcon#wrote, iclass 33, count 0 2006.231.08:21:50.96#ibcon#about to read 3, iclass 33, count 0 2006.231.08:21:51.00#ibcon#read 3, iclass 33, count 0 2006.231.08:21:51.00#ibcon#about to read 4, iclass 33, count 0 2006.231.08:21:51.00#ibcon#read 4, iclass 33, count 0 2006.231.08:21:51.00#ibcon#about to read 5, iclass 33, count 0 2006.231.08:21:51.00#ibcon#read 5, iclass 33, count 0 2006.231.08:21:51.00#ibcon#about to read 6, iclass 33, count 0 2006.231.08:21:51.00#ibcon#read 6, iclass 33, count 0 2006.231.08:21:51.00#ibcon#end of sib2, iclass 33, count 0 2006.231.08:21:51.00#ibcon#*after write, iclass 33, count 0 2006.231.08:21:51.00#ibcon#*before return 0, iclass 33, count 0 2006.231.08:21:51.00#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:21:51.00#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.231.08:21:51.00#ibcon#about to clear, iclass 33 cls_cnt 0 2006.231.08:21:51.00#ibcon#cleared, iclass 33 cls_cnt 0 2006.231.08:21:51.00$vc4f8/vb=2,4 2006.231.08:21:51.00#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.231.08:21:51.00#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.231.08:21:51.00#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:51.00#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:21:51.06#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:21:51.06#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:21:51.06#ibcon#enter wrdev, iclass 35, count 2 2006.231.08:21:51.06#ibcon#first serial, iclass 35, count 2 2006.231.08:21:51.06#ibcon#enter sib2, iclass 35, count 2 2006.231.08:21:51.06#ibcon#flushed, iclass 35, count 2 2006.231.08:21:51.06#ibcon#about to write, iclass 35, count 2 2006.231.08:21:51.06#ibcon#wrote, iclass 35, count 2 2006.231.08:21:51.06#ibcon#about to read 3, iclass 35, count 2 2006.231.08:21:51.08#ibcon#read 3, iclass 35, count 2 2006.231.08:21:51.08#ibcon#about to read 4, iclass 35, count 2 2006.231.08:21:51.08#ibcon#read 4, iclass 35, count 2 2006.231.08:21:51.08#ibcon#about to read 5, iclass 35, count 2 2006.231.08:21:51.08#ibcon#read 5, iclass 35, count 2 2006.231.08:21:51.08#ibcon#about to read 6, iclass 35, count 2 2006.231.08:21:51.08#ibcon#read 6, iclass 35, count 2 2006.231.08:21:51.08#ibcon#end of sib2, iclass 35, count 2 2006.231.08:21:51.08#ibcon#*mode == 0, iclass 35, count 2 2006.231.08:21:51.08#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.231.08:21:51.08#ibcon#[27=AT02-04\r\n] 2006.231.08:21:51.08#ibcon#*before write, iclass 35, count 2 2006.231.08:21:51.08#ibcon#enter sib2, iclass 35, count 2 2006.231.08:21:51.08#ibcon#flushed, iclass 35, count 2 2006.231.08:21:51.08#ibcon#about to write, iclass 35, count 2 2006.231.08:21:51.08#ibcon#wrote, iclass 35, count 2 2006.231.08:21:51.08#ibcon#about to read 3, iclass 35, count 2 2006.231.08:21:51.11#ibcon#read 3, iclass 35, count 2 2006.231.08:21:51.11#ibcon#about to read 4, iclass 35, count 2 2006.231.08:21:51.11#ibcon#read 4, iclass 35, count 2 2006.231.08:21:51.11#ibcon#about to read 5, iclass 35, count 2 2006.231.08:21:51.11#ibcon#read 5, iclass 35, count 2 2006.231.08:21:51.11#ibcon#about to read 6, iclass 35, count 2 2006.231.08:21:51.11#ibcon#read 6, iclass 35, count 2 2006.231.08:21:51.11#ibcon#end of sib2, iclass 35, count 2 2006.231.08:21:51.11#ibcon#*after write, iclass 35, count 2 2006.231.08:21:51.11#ibcon#*before return 0, iclass 35, count 2 2006.231.08:21:51.11#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:21:51.11#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.231.08:21:51.11#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.231.08:21:51.11#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:51.11#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:21:51.23#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:21:51.23#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:21:51.23#ibcon#enter wrdev, iclass 35, count 0 2006.231.08:21:51.23#ibcon#first serial, iclass 35, count 0 2006.231.08:21:51.23#ibcon#enter sib2, iclass 35, count 0 2006.231.08:21:51.23#ibcon#flushed, iclass 35, count 0 2006.231.08:21:51.23#ibcon#about to write, iclass 35, count 0 2006.231.08:21:51.23#ibcon#wrote, iclass 35, count 0 2006.231.08:21:51.23#ibcon#about to read 3, iclass 35, count 0 2006.231.08:21:51.25#ibcon#read 3, iclass 35, count 0 2006.231.08:21:51.25#ibcon#about to read 4, iclass 35, count 0 2006.231.08:21:51.25#ibcon#read 4, iclass 35, count 0 2006.231.08:21:51.25#ibcon#about to read 5, iclass 35, count 0 2006.231.08:21:51.25#ibcon#read 5, iclass 35, count 0 2006.231.08:21:51.25#ibcon#about to read 6, iclass 35, count 0 2006.231.08:21:51.25#ibcon#read 6, iclass 35, count 0 2006.231.08:21:51.25#ibcon#end of sib2, iclass 35, count 0 2006.231.08:21:51.25#ibcon#*mode == 0, iclass 35, count 0 2006.231.08:21:51.25#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.231.08:21:51.25#ibcon#[27=USB\r\n] 2006.231.08:21:51.25#ibcon#*before write, iclass 35, count 0 2006.231.08:21:51.25#ibcon#enter sib2, iclass 35, count 0 2006.231.08:21:51.25#ibcon#flushed, iclass 35, count 0 2006.231.08:21:51.25#ibcon#about to write, iclass 35, count 0 2006.231.08:21:51.25#ibcon#wrote, iclass 35, count 0 2006.231.08:21:51.25#ibcon#about to read 3, iclass 35, count 0 2006.231.08:21:51.28#ibcon#read 3, iclass 35, count 0 2006.231.08:21:51.28#ibcon#about to read 4, iclass 35, count 0 2006.231.08:21:51.28#ibcon#read 4, iclass 35, count 0 2006.231.08:21:51.28#ibcon#about to read 5, iclass 35, count 0 2006.231.08:21:51.28#ibcon#read 5, iclass 35, count 0 2006.231.08:21:51.28#ibcon#about to read 6, iclass 35, count 0 2006.231.08:21:51.28#ibcon#read 6, iclass 35, count 0 2006.231.08:21:51.28#ibcon#end of sib2, iclass 35, count 0 2006.231.08:21:51.28#ibcon#*after write, iclass 35, count 0 2006.231.08:21:51.28#ibcon#*before return 0, iclass 35, count 0 2006.231.08:21:51.28#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:21:51.28#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.231.08:21:51.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.231.08:21:51.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.231.08:21:51.28$vc4f8/vblo=3,656.99 2006.231.08:21:51.28#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.231.08:21:51.28#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.231.08:21:51.28#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:51.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:21:51.28#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:21:51.28#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:21:51.28#ibcon#enter wrdev, iclass 37, count 0 2006.231.08:21:51.28#ibcon#first serial, iclass 37, count 0 2006.231.08:21:51.28#ibcon#enter sib2, iclass 37, count 0 2006.231.08:21:51.28#ibcon#flushed, iclass 37, count 0 2006.231.08:21:51.28#ibcon#about to write, iclass 37, count 0 2006.231.08:21:51.28#ibcon#wrote, iclass 37, count 0 2006.231.08:21:51.28#ibcon#about to read 3, iclass 37, count 0 2006.231.08:21:51.30#ibcon#read 3, iclass 37, count 0 2006.231.08:21:51.30#ibcon#about to read 4, iclass 37, count 0 2006.231.08:21:51.30#ibcon#read 4, iclass 37, count 0 2006.231.08:21:51.30#ibcon#about to read 5, iclass 37, count 0 2006.231.08:21:51.30#ibcon#read 5, iclass 37, count 0 2006.231.08:21:51.30#ibcon#about to read 6, iclass 37, count 0 2006.231.08:21:51.30#ibcon#read 6, iclass 37, count 0 2006.231.08:21:51.30#ibcon#end of sib2, iclass 37, count 0 2006.231.08:21:51.30#ibcon#*mode == 0, iclass 37, count 0 2006.231.08:21:51.30#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.231.08:21:51.30#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:21:51.30#ibcon#*before write, iclass 37, count 0 2006.231.08:21:51.30#ibcon#enter sib2, iclass 37, count 0 2006.231.08:21:51.30#ibcon#flushed, iclass 37, count 0 2006.231.08:21:51.30#ibcon#about to write, iclass 37, count 0 2006.231.08:21:51.30#ibcon#wrote, iclass 37, count 0 2006.231.08:21:51.30#ibcon#about to read 3, iclass 37, count 0 2006.231.08:21:51.34#ibcon#read 3, iclass 37, count 0 2006.231.08:21:51.34#ibcon#about to read 4, iclass 37, count 0 2006.231.08:21:51.34#ibcon#read 4, iclass 37, count 0 2006.231.08:21:51.34#ibcon#about to read 5, iclass 37, count 0 2006.231.08:21:51.34#ibcon#read 5, iclass 37, count 0 2006.231.08:21:51.34#ibcon#about to read 6, iclass 37, count 0 2006.231.08:21:51.34#ibcon#read 6, iclass 37, count 0 2006.231.08:21:51.34#ibcon#end of sib2, iclass 37, count 0 2006.231.08:21:51.34#ibcon#*after write, iclass 37, count 0 2006.231.08:21:51.34#ibcon#*before return 0, iclass 37, count 0 2006.231.08:21:51.34#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:21:51.34#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.231.08:21:51.34#ibcon#about to clear, iclass 37 cls_cnt 0 2006.231.08:21:51.34#ibcon#cleared, iclass 37 cls_cnt 0 2006.231.08:21:51.34$vc4f8/vb=3,4 2006.231.08:21:51.34#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.231.08:21:51.34#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.231.08:21:51.34#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:51.34#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:21:51.40#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:21:51.40#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:21:51.40#ibcon#enter wrdev, iclass 39, count 2 2006.231.08:21:51.40#ibcon#first serial, iclass 39, count 2 2006.231.08:21:51.40#ibcon#enter sib2, iclass 39, count 2 2006.231.08:21:51.40#ibcon#flushed, iclass 39, count 2 2006.231.08:21:51.40#ibcon#about to write, iclass 39, count 2 2006.231.08:21:51.40#ibcon#wrote, iclass 39, count 2 2006.231.08:21:51.40#ibcon#about to read 3, iclass 39, count 2 2006.231.08:21:51.42#ibcon#read 3, iclass 39, count 2 2006.231.08:21:51.42#ibcon#about to read 4, iclass 39, count 2 2006.231.08:21:51.42#ibcon#read 4, iclass 39, count 2 2006.231.08:21:51.42#ibcon#about to read 5, iclass 39, count 2 2006.231.08:21:51.42#ibcon#read 5, iclass 39, count 2 2006.231.08:21:51.42#ibcon#about to read 6, iclass 39, count 2 2006.231.08:21:51.42#ibcon#read 6, iclass 39, count 2 2006.231.08:21:51.42#ibcon#end of sib2, iclass 39, count 2 2006.231.08:21:51.42#ibcon#*mode == 0, iclass 39, count 2 2006.231.08:21:51.42#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.231.08:21:51.42#ibcon#[27=AT03-04\r\n] 2006.231.08:21:51.42#ibcon#*before write, iclass 39, count 2 2006.231.08:21:51.42#ibcon#enter sib2, iclass 39, count 2 2006.231.08:21:51.42#ibcon#flushed, iclass 39, count 2 2006.231.08:21:51.42#ibcon#about to write, iclass 39, count 2 2006.231.08:21:51.42#ibcon#wrote, iclass 39, count 2 2006.231.08:21:51.42#ibcon#about to read 3, iclass 39, count 2 2006.231.08:21:51.45#ibcon#read 3, iclass 39, count 2 2006.231.08:21:51.45#ibcon#about to read 4, iclass 39, count 2 2006.231.08:21:51.45#ibcon#read 4, iclass 39, count 2 2006.231.08:21:51.45#ibcon#about to read 5, iclass 39, count 2 2006.231.08:21:51.45#ibcon#read 5, iclass 39, count 2 2006.231.08:21:51.45#ibcon#about to read 6, iclass 39, count 2 2006.231.08:21:51.45#ibcon#read 6, iclass 39, count 2 2006.231.08:21:51.45#ibcon#end of sib2, iclass 39, count 2 2006.231.08:21:51.45#ibcon#*after write, iclass 39, count 2 2006.231.08:21:51.45#ibcon#*before return 0, iclass 39, count 2 2006.231.08:21:51.45#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:21:51.45#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.231.08:21:51.45#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.231.08:21:51.45#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:51.45#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:21:51.57#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:21:51.57#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:21:51.57#ibcon#enter wrdev, iclass 39, count 0 2006.231.08:21:51.57#ibcon#first serial, iclass 39, count 0 2006.231.08:21:51.57#ibcon#enter sib2, iclass 39, count 0 2006.231.08:21:51.57#ibcon#flushed, iclass 39, count 0 2006.231.08:21:51.57#ibcon#about to write, iclass 39, count 0 2006.231.08:21:51.57#ibcon#wrote, iclass 39, count 0 2006.231.08:21:51.57#ibcon#about to read 3, iclass 39, count 0 2006.231.08:21:51.59#ibcon#read 3, iclass 39, count 0 2006.231.08:21:51.59#ibcon#about to read 4, iclass 39, count 0 2006.231.08:21:51.59#ibcon#read 4, iclass 39, count 0 2006.231.08:21:51.59#ibcon#about to read 5, iclass 39, count 0 2006.231.08:21:51.59#ibcon#read 5, iclass 39, count 0 2006.231.08:21:51.59#ibcon#about to read 6, iclass 39, count 0 2006.231.08:21:51.59#ibcon#read 6, iclass 39, count 0 2006.231.08:21:51.59#ibcon#end of sib2, iclass 39, count 0 2006.231.08:21:51.59#ibcon#*mode == 0, iclass 39, count 0 2006.231.08:21:51.59#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.231.08:21:51.59#ibcon#[27=USB\r\n] 2006.231.08:21:51.59#ibcon#*before write, iclass 39, count 0 2006.231.08:21:51.59#ibcon#enter sib2, iclass 39, count 0 2006.231.08:21:51.59#ibcon#flushed, iclass 39, count 0 2006.231.08:21:51.59#ibcon#about to write, iclass 39, count 0 2006.231.08:21:51.59#ibcon#wrote, iclass 39, count 0 2006.231.08:21:51.59#ibcon#about to read 3, iclass 39, count 0 2006.231.08:21:51.63#ibcon#read 3, iclass 39, count 0 2006.231.08:21:51.63#ibcon#about to read 4, iclass 39, count 0 2006.231.08:21:51.63#ibcon#read 4, iclass 39, count 0 2006.231.08:21:51.63#ibcon#about to read 5, iclass 39, count 0 2006.231.08:21:51.63#ibcon#read 5, iclass 39, count 0 2006.231.08:21:51.63#ibcon#about to read 6, iclass 39, count 0 2006.231.08:21:51.63#ibcon#read 6, iclass 39, count 0 2006.231.08:21:51.63#ibcon#end of sib2, iclass 39, count 0 2006.231.08:21:51.63#ibcon#*after write, iclass 39, count 0 2006.231.08:21:51.63#ibcon#*before return 0, iclass 39, count 0 2006.231.08:21:51.63#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:21:51.63#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.231.08:21:51.63#ibcon#about to clear, iclass 39 cls_cnt 0 2006.231.08:21:51.63#ibcon#cleared, iclass 39 cls_cnt 0 2006.231.08:21:51.63$vc4f8/vblo=4,712.99 2006.231.08:21:51.63#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.231.08:21:51.63#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.231.08:21:51.63#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:51.63#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:21:51.63#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:21:51.63#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:21:51.63#ibcon#enter wrdev, iclass 3, count 0 2006.231.08:21:51.63#ibcon#first serial, iclass 3, count 0 2006.231.08:21:51.64#ibcon#enter sib2, iclass 3, count 0 2006.231.08:21:51.64#ibcon#flushed, iclass 3, count 0 2006.231.08:21:51.64#ibcon#about to write, iclass 3, count 0 2006.231.08:21:51.64#ibcon#wrote, iclass 3, count 0 2006.231.08:21:51.64#ibcon#about to read 3, iclass 3, count 0 2006.231.08:21:51.65#ibcon#read 3, iclass 3, count 0 2006.231.08:21:51.65#ibcon#about to read 4, iclass 3, count 0 2006.231.08:21:51.65#ibcon#read 4, iclass 3, count 0 2006.231.08:21:51.65#ibcon#about to read 5, iclass 3, count 0 2006.231.08:21:51.65#ibcon#read 5, iclass 3, count 0 2006.231.08:21:51.65#ibcon#about to read 6, iclass 3, count 0 2006.231.08:21:51.65#ibcon#read 6, iclass 3, count 0 2006.231.08:21:51.65#ibcon#end of sib2, iclass 3, count 0 2006.231.08:21:51.65#ibcon#*mode == 0, iclass 3, count 0 2006.231.08:21:51.65#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.231.08:21:51.65#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:21:51.65#ibcon#*before write, iclass 3, count 0 2006.231.08:21:51.65#ibcon#enter sib2, iclass 3, count 0 2006.231.08:21:51.65#ibcon#flushed, iclass 3, count 0 2006.231.08:21:51.65#ibcon#about to write, iclass 3, count 0 2006.231.08:21:51.65#ibcon#wrote, iclass 3, count 0 2006.231.08:21:51.65#ibcon#about to read 3, iclass 3, count 0 2006.231.08:21:51.69#ibcon#read 3, iclass 3, count 0 2006.231.08:21:51.69#ibcon#about to read 4, iclass 3, count 0 2006.231.08:21:51.69#ibcon#read 4, iclass 3, count 0 2006.231.08:21:51.69#ibcon#about to read 5, iclass 3, count 0 2006.231.08:21:51.69#ibcon#read 5, iclass 3, count 0 2006.231.08:21:51.69#ibcon#about to read 6, iclass 3, count 0 2006.231.08:21:51.69#ibcon#read 6, iclass 3, count 0 2006.231.08:21:51.69#ibcon#end of sib2, iclass 3, count 0 2006.231.08:21:51.69#ibcon#*after write, iclass 3, count 0 2006.231.08:21:51.69#ibcon#*before return 0, iclass 3, count 0 2006.231.08:21:51.69#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:21:51.69#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.231.08:21:51.69#ibcon#about to clear, iclass 3 cls_cnt 0 2006.231.08:21:51.69#ibcon#cleared, iclass 3 cls_cnt 0 2006.231.08:21:51.69$vc4f8/vb=4,4 2006.231.08:21:51.69#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.231.08:21:51.69#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.231.08:21:51.69#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:51.69#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:21:51.75#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:21:51.75#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:21:51.75#ibcon#enter wrdev, iclass 5, count 2 2006.231.08:21:51.75#ibcon#first serial, iclass 5, count 2 2006.231.08:21:51.75#ibcon#enter sib2, iclass 5, count 2 2006.231.08:21:51.75#ibcon#flushed, iclass 5, count 2 2006.231.08:21:51.75#ibcon#about to write, iclass 5, count 2 2006.231.08:21:51.75#ibcon#wrote, iclass 5, count 2 2006.231.08:21:51.75#ibcon#about to read 3, iclass 5, count 2 2006.231.08:21:51.77#ibcon#read 3, iclass 5, count 2 2006.231.08:21:51.77#ibcon#about to read 4, iclass 5, count 2 2006.231.08:21:51.77#ibcon#read 4, iclass 5, count 2 2006.231.08:21:51.77#ibcon#about to read 5, iclass 5, count 2 2006.231.08:21:51.77#ibcon#read 5, iclass 5, count 2 2006.231.08:21:51.77#ibcon#about to read 6, iclass 5, count 2 2006.231.08:21:51.77#ibcon#read 6, iclass 5, count 2 2006.231.08:21:51.77#ibcon#end of sib2, iclass 5, count 2 2006.231.08:21:51.77#ibcon#*mode == 0, iclass 5, count 2 2006.231.08:21:51.77#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.231.08:21:51.77#ibcon#[27=AT04-04\r\n] 2006.231.08:21:51.77#ibcon#*before write, iclass 5, count 2 2006.231.08:21:51.77#ibcon#enter sib2, iclass 5, count 2 2006.231.08:21:51.77#ibcon#flushed, iclass 5, count 2 2006.231.08:21:51.77#ibcon#about to write, iclass 5, count 2 2006.231.08:21:51.77#ibcon#wrote, iclass 5, count 2 2006.231.08:21:51.77#ibcon#about to read 3, iclass 5, count 2 2006.231.08:21:51.80#ibcon#read 3, iclass 5, count 2 2006.231.08:21:51.80#ibcon#about to read 4, iclass 5, count 2 2006.231.08:21:51.80#ibcon#read 4, iclass 5, count 2 2006.231.08:21:51.80#ibcon#about to read 5, iclass 5, count 2 2006.231.08:21:51.80#ibcon#read 5, iclass 5, count 2 2006.231.08:21:51.80#ibcon#about to read 6, iclass 5, count 2 2006.231.08:21:51.80#ibcon#read 6, iclass 5, count 2 2006.231.08:21:51.80#ibcon#end of sib2, iclass 5, count 2 2006.231.08:21:51.80#ibcon#*after write, iclass 5, count 2 2006.231.08:21:51.80#ibcon#*before return 0, iclass 5, count 2 2006.231.08:21:51.80#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:21:51.80#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.231.08:21:51.80#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.231.08:21:51.80#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:51.80#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:21:51.92#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:21:51.92#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:21:51.92#ibcon#enter wrdev, iclass 5, count 0 2006.231.08:21:51.92#ibcon#first serial, iclass 5, count 0 2006.231.08:21:51.92#ibcon#enter sib2, iclass 5, count 0 2006.231.08:21:51.92#ibcon#flushed, iclass 5, count 0 2006.231.08:21:51.92#ibcon#about to write, iclass 5, count 0 2006.231.08:21:51.92#ibcon#wrote, iclass 5, count 0 2006.231.08:21:51.92#ibcon#about to read 3, iclass 5, count 0 2006.231.08:21:51.94#ibcon#read 3, iclass 5, count 0 2006.231.08:21:51.94#ibcon#about to read 4, iclass 5, count 0 2006.231.08:21:51.94#ibcon#read 4, iclass 5, count 0 2006.231.08:21:51.94#ibcon#about to read 5, iclass 5, count 0 2006.231.08:21:51.94#ibcon#read 5, iclass 5, count 0 2006.231.08:21:51.94#ibcon#about to read 6, iclass 5, count 0 2006.231.08:21:51.94#ibcon#read 6, iclass 5, count 0 2006.231.08:21:51.94#ibcon#end of sib2, iclass 5, count 0 2006.231.08:21:51.94#ibcon#*mode == 0, iclass 5, count 0 2006.231.08:21:51.94#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.231.08:21:51.94#ibcon#[27=USB\r\n] 2006.231.08:21:51.94#ibcon#*before write, iclass 5, count 0 2006.231.08:21:51.94#ibcon#enter sib2, iclass 5, count 0 2006.231.08:21:51.94#ibcon#flushed, iclass 5, count 0 2006.231.08:21:51.94#ibcon#about to write, iclass 5, count 0 2006.231.08:21:51.94#ibcon#wrote, iclass 5, count 0 2006.231.08:21:51.94#ibcon#about to read 3, iclass 5, count 0 2006.231.08:21:51.97#ibcon#read 3, iclass 5, count 0 2006.231.08:21:51.97#ibcon#about to read 4, iclass 5, count 0 2006.231.08:21:51.97#ibcon#read 4, iclass 5, count 0 2006.231.08:21:51.97#ibcon#about to read 5, iclass 5, count 0 2006.231.08:21:51.97#ibcon#read 5, iclass 5, count 0 2006.231.08:21:51.97#ibcon#about to read 6, iclass 5, count 0 2006.231.08:21:51.97#ibcon#read 6, iclass 5, count 0 2006.231.08:21:51.97#ibcon#end of sib2, iclass 5, count 0 2006.231.08:21:51.97#ibcon#*after write, iclass 5, count 0 2006.231.08:21:51.97#ibcon#*before return 0, iclass 5, count 0 2006.231.08:21:51.97#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:21:51.97#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.231.08:21:51.97#ibcon#about to clear, iclass 5 cls_cnt 0 2006.231.08:21:51.97#ibcon#cleared, iclass 5 cls_cnt 0 2006.231.08:21:51.97$vc4f8/vblo=5,744.99 2006.231.08:21:51.97#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.231.08:21:51.97#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.231.08:21:51.97#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:51.97#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:21:51.97#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:21:51.97#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:21:51.97#ibcon#enter wrdev, iclass 7, count 0 2006.231.08:21:51.97#ibcon#first serial, iclass 7, count 0 2006.231.08:21:51.97#ibcon#enter sib2, iclass 7, count 0 2006.231.08:21:51.97#ibcon#flushed, iclass 7, count 0 2006.231.08:21:51.97#ibcon#about to write, iclass 7, count 0 2006.231.08:21:51.97#ibcon#wrote, iclass 7, count 0 2006.231.08:21:51.97#ibcon#about to read 3, iclass 7, count 0 2006.231.08:21:51.99#ibcon#read 3, iclass 7, count 0 2006.231.08:21:51.99#ibcon#about to read 4, iclass 7, count 0 2006.231.08:21:51.99#ibcon#read 4, iclass 7, count 0 2006.231.08:21:51.99#ibcon#about to read 5, iclass 7, count 0 2006.231.08:21:51.99#ibcon#read 5, iclass 7, count 0 2006.231.08:21:51.99#ibcon#about to read 6, iclass 7, count 0 2006.231.08:21:51.99#ibcon#read 6, iclass 7, count 0 2006.231.08:21:51.99#ibcon#end of sib2, iclass 7, count 0 2006.231.08:21:51.99#ibcon#*mode == 0, iclass 7, count 0 2006.231.08:21:51.99#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.231.08:21:51.99#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:21:51.99#ibcon#*before write, iclass 7, count 0 2006.231.08:21:51.99#ibcon#enter sib2, iclass 7, count 0 2006.231.08:21:51.99#ibcon#flushed, iclass 7, count 0 2006.231.08:21:51.99#ibcon#about to write, iclass 7, count 0 2006.231.08:21:51.99#ibcon#wrote, iclass 7, count 0 2006.231.08:21:51.99#ibcon#about to read 3, iclass 7, count 0 2006.231.08:21:52.03#ibcon#read 3, iclass 7, count 0 2006.231.08:21:52.03#ibcon#about to read 4, iclass 7, count 0 2006.231.08:21:52.03#ibcon#read 4, iclass 7, count 0 2006.231.08:21:52.03#ibcon#about to read 5, iclass 7, count 0 2006.231.08:21:52.03#ibcon#read 5, iclass 7, count 0 2006.231.08:21:52.03#ibcon#about to read 6, iclass 7, count 0 2006.231.08:21:52.03#ibcon#read 6, iclass 7, count 0 2006.231.08:21:52.03#ibcon#end of sib2, iclass 7, count 0 2006.231.08:21:52.03#ibcon#*after write, iclass 7, count 0 2006.231.08:21:52.03#ibcon#*before return 0, iclass 7, count 0 2006.231.08:21:52.03#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:21:52.03#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.231.08:21:52.03#ibcon#about to clear, iclass 7 cls_cnt 0 2006.231.08:21:52.03#ibcon#cleared, iclass 7 cls_cnt 0 2006.231.08:21:52.03$vc4f8/vb=5,3 2006.231.08:21:52.03#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.231.08:21:52.03#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.231.08:21:52.03#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:52.03#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:21:52.09#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:21:52.09#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:21:52.09#ibcon#enter wrdev, iclass 11, count 2 2006.231.08:21:52.09#ibcon#first serial, iclass 11, count 2 2006.231.08:21:52.09#ibcon#enter sib2, iclass 11, count 2 2006.231.08:21:52.09#ibcon#flushed, iclass 11, count 2 2006.231.08:21:52.09#ibcon#about to write, iclass 11, count 2 2006.231.08:21:52.09#ibcon#wrote, iclass 11, count 2 2006.231.08:21:52.09#ibcon#about to read 3, iclass 11, count 2 2006.231.08:21:52.11#ibcon#read 3, iclass 11, count 2 2006.231.08:21:52.11#ibcon#about to read 4, iclass 11, count 2 2006.231.08:21:52.11#ibcon#read 4, iclass 11, count 2 2006.231.08:21:52.11#ibcon#about to read 5, iclass 11, count 2 2006.231.08:21:52.11#ibcon#read 5, iclass 11, count 2 2006.231.08:21:52.11#ibcon#about to read 6, iclass 11, count 2 2006.231.08:21:52.11#ibcon#read 6, iclass 11, count 2 2006.231.08:21:52.11#ibcon#end of sib2, iclass 11, count 2 2006.231.08:21:52.11#ibcon#*mode == 0, iclass 11, count 2 2006.231.08:21:52.11#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.231.08:21:52.11#ibcon#[27=AT05-03\r\n] 2006.231.08:21:52.11#ibcon#*before write, iclass 11, count 2 2006.231.08:21:52.11#ibcon#enter sib2, iclass 11, count 2 2006.231.08:21:52.11#ibcon#flushed, iclass 11, count 2 2006.231.08:21:52.11#ibcon#about to write, iclass 11, count 2 2006.231.08:21:52.11#ibcon#wrote, iclass 11, count 2 2006.231.08:21:52.11#ibcon#about to read 3, iclass 11, count 2 2006.231.08:21:52.14#ibcon#read 3, iclass 11, count 2 2006.231.08:21:52.14#ibcon#about to read 4, iclass 11, count 2 2006.231.08:21:52.14#ibcon#read 4, iclass 11, count 2 2006.231.08:21:52.14#ibcon#about to read 5, iclass 11, count 2 2006.231.08:21:52.14#ibcon#read 5, iclass 11, count 2 2006.231.08:21:52.14#ibcon#about to read 6, iclass 11, count 2 2006.231.08:21:52.14#ibcon#read 6, iclass 11, count 2 2006.231.08:21:52.14#ibcon#end of sib2, iclass 11, count 2 2006.231.08:21:52.14#ibcon#*after write, iclass 11, count 2 2006.231.08:21:52.14#ibcon#*before return 0, iclass 11, count 2 2006.231.08:21:52.14#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:21:52.14#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.231.08:21:52.14#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.231.08:21:52.14#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:52.14#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:21:52.26#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:21:52.26#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:21:52.26#ibcon#enter wrdev, iclass 11, count 0 2006.231.08:21:52.26#ibcon#first serial, iclass 11, count 0 2006.231.08:21:52.26#ibcon#enter sib2, iclass 11, count 0 2006.231.08:21:52.26#ibcon#flushed, iclass 11, count 0 2006.231.08:21:52.26#ibcon#about to write, iclass 11, count 0 2006.231.08:21:52.26#ibcon#wrote, iclass 11, count 0 2006.231.08:21:52.26#ibcon#about to read 3, iclass 11, count 0 2006.231.08:21:52.28#ibcon#read 3, iclass 11, count 0 2006.231.08:21:52.28#ibcon#about to read 4, iclass 11, count 0 2006.231.08:21:52.28#ibcon#read 4, iclass 11, count 0 2006.231.08:21:52.28#ibcon#about to read 5, iclass 11, count 0 2006.231.08:21:52.28#ibcon#read 5, iclass 11, count 0 2006.231.08:21:52.28#ibcon#about to read 6, iclass 11, count 0 2006.231.08:21:52.28#ibcon#read 6, iclass 11, count 0 2006.231.08:21:52.28#ibcon#end of sib2, iclass 11, count 0 2006.231.08:21:52.28#ibcon#*mode == 0, iclass 11, count 0 2006.231.08:21:52.28#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.231.08:21:52.28#ibcon#[27=USB\r\n] 2006.231.08:21:52.28#ibcon#*before write, iclass 11, count 0 2006.231.08:21:52.28#ibcon#enter sib2, iclass 11, count 0 2006.231.08:21:52.28#ibcon#flushed, iclass 11, count 0 2006.231.08:21:52.28#ibcon#about to write, iclass 11, count 0 2006.231.08:21:52.28#ibcon#wrote, iclass 11, count 0 2006.231.08:21:52.28#ibcon#about to read 3, iclass 11, count 0 2006.231.08:21:52.31#ibcon#read 3, iclass 11, count 0 2006.231.08:21:52.31#ibcon#about to read 4, iclass 11, count 0 2006.231.08:21:52.31#ibcon#read 4, iclass 11, count 0 2006.231.08:21:52.31#ibcon#about to read 5, iclass 11, count 0 2006.231.08:21:52.31#ibcon#read 5, iclass 11, count 0 2006.231.08:21:52.31#ibcon#about to read 6, iclass 11, count 0 2006.231.08:21:52.31#ibcon#read 6, iclass 11, count 0 2006.231.08:21:52.31#ibcon#end of sib2, iclass 11, count 0 2006.231.08:21:52.31#ibcon#*after write, iclass 11, count 0 2006.231.08:21:52.31#ibcon#*before return 0, iclass 11, count 0 2006.231.08:21:52.31#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:21:52.31#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.231.08:21:52.31#ibcon#about to clear, iclass 11 cls_cnt 0 2006.231.08:21:52.31#ibcon#cleared, iclass 11 cls_cnt 0 2006.231.08:21:52.31$vc4f8/vblo=6,752.99 2006.231.08:21:52.31#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.231.08:21:52.31#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.231.08:21:52.31#ibcon#ireg 17 cls_cnt 0 2006.231.08:21:52.31#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:21:52.31#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:21:52.31#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:21:52.31#ibcon#enter wrdev, iclass 13, count 0 2006.231.08:21:52.31#ibcon#first serial, iclass 13, count 0 2006.231.08:21:52.31#ibcon#enter sib2, iclass 13, count 0 2006.231.08:21:52.31#ibcon#flushed, iclass 13, count 0 2006.231.08:21:52.31#ibcon#about to write, iclass 13, count 0 2006.231.08:21:52.31#ibcon#wrote, iclass 13, count 0 2006.231.08:21:52.31#ibcon#about to read 3, iclass 13, count 0 2006.231.08:21:52.33#ibcon#read 3, iclass 13, count 0 2006.231.08:21:52.33#ibcon#about to read 4, iclass 13, count 0 2006.231.08:21:52.33#ibcon#read 4, iclass 13, count 0 2006.231.08:21:52.33#ibcon#about to read 5, iclass 13, count 0 2006.231.08:21:52.33#ibcon#read 5, iclass 13, count 0 2006.231.08:21:52.33#ibcon#about to read 6, iclass 13, count 0 2006.231.08:21:52.33#ibcon#read 6, iclass 13, count 0 2006.231.08:21:52.33#ibcon#end of sib2, iclass 13, count 0 2006.231.08:21:52.33#ibcon#*mode == 0, iclass 13, count 0 2006.231.08:21:52.33#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.231.08:21:52.33#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:21:52.33#ibcon#*before write, iclass 13, count 0 2006.231.08:21:52.33#ibcon#enter sib2, iclass 13, count 0 2006.231.08:21:52.33#ibcon#flushed, iclass 13, count 0 2006.231.08:21:52.33#ibcon#about to write, iclass 13, count 0 2006.231.08:21:52.33#ibcon#wrote, iclass 13, count 0 2006.231.08:21:52.33#ibcon#about to read 3, iclass 13, count 0 2006.231.08:21:52.37#ibcon#read 3, iclass 13, count 0 2006.231.08:21:52.37#ibcon#about to read 4, iclass 13, count 0 2006.231.08:21:52.37#ibcon#read 4, iclass 13, count 0 2006.231.08:21:52.37#ibcon#about to read 5, iclass 13, count 0 2006.231.08:21:52.37#ibcon#read 5, iclass 13, count 0 2006.231.08:21:52.37#ibcon#about to read 6, iclass 13, count 0 2006.231.08:21:52.37#ibcon#read 6, iclass 13, count 0 2006.231.08:21:52.37#ibcon#end of sib2, iclass 13, count 0 2006.231.08:21:52.37#ibcon#*after write, iclass 13, count 0 2006.231.08:21:52.37#ibcon#*before return 0, iclass 13, count 0 2006.231.08:21:52.37#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:21:52.37#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.231.08:21:52.37#ibcon#about to clear, iclass 13 cls_cnt 0 2006.231.08:21:52.37#ibcon#cleared, iclass 13 cls_cnt 0 2006.231.08:21:52.37$vc4f8/vb=6,4 2006.231.08:21:52.37#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.231.08:21:52.37#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.231.08:21:52.37#ibcon#ireg 11 cls_cnt 2 2006.231.08:21:52.37#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:21:52.43#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:21:52.43#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:21:52.43#ibcon#enter wrdev, iclass 15, count 2 2006.231.08:21:52.43#ibcon#first serial, iclass 15, count 2 2006.231.08:21:52.43#ibcon#enter sib2, iclass 15, count 2 2006.231.08:21:52.43#ibcon#flushed, iclass 15, count 2 2006.231.08:21:52.43#ibcon#about to write, iclass 15, count 2 2006.231.08:21:52.43#ibcon#wrote, iclass 15, count 2 2006.231.08:21:52.43#ibcon#about to read 3, iclass 15, count 2 2006.231.08:21:52.45#ibcon#read 3, iclass 15, count 2 2006.231.08:21:52.45#ibcon#about to read 4, iclass 15, count 2 2006.231.08:21:52.45#ibcon#read 4, iclass 15, count 2 2006.231.08:21:52.45#ibcon#about to read 5, iclass 15, count 2 2006.231.08:21:52.45#ibcon#read 5, iclass 15, count 2 2006.231.08:21:52.45#ibcon#about to read 6, iclass 15, count 2 2006.231.08:21:52.45#ibcon#read 6, iclass 15, count 2 2006.231.08:21:52.45#ibcon#end of sib2, iclass 15, count 2 2006.231.08:21:52.45#ibcon#*mode == 0, iclass 15, count 2 2006.231.08:21:52.45#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.231.08:21:52.45#ibcon#[27=AT06-04\r\n] 2006.231.08:21:52.45#ibcon#*before write, iclass 15, count 2 2006.231.08:21:52.45#ibcon#enter sib2, iclass 15, count 2 2006.231.08:21:52.45#ibcon#flushed, iclass 15, count 2 2006.231.08:21:52.45#ibcon#about to write, iclass 15, count 2 2006.231.08:21:52.45#ibcon#wrote, iclass 15, count 2 2006.231.08:21:52.45#ibcon#about to read 3, iclass 15, count 2 2006.231.08:21:52.48#ibcon#read 3, iclass 15, count 2 2006.231.08:21:52.48#ibcon#about to read 4, iclass 15, count 2 2006.231.08:21:52.48#ibcon#read 4, iclass 15, count 2 2006.231.08:21:52.48#ibcon#about to read 5, iclass 15, count 2 2006.231.08:21:52.48#ibcon#read 5, iclass 15, count 2 2006.231.08:21:52.48#ibcon#about to read 6, iclass 15, count 2 2006.231.08:21:52.48#ibcon#read 6, iclass 15, count 2 2006.231.08:21:52.48#ibcon#end of sib2, iclass 15, count 2 2006.231.08:21:52.48#ibcon#*after write, iclass 15, count 2 2006.231.08:21:52.48#ibcon#*before return 0, iclass 15, count 2 2006.231.08:21:52.48#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:21:52.48#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.231.08:21:52.48#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.231.08:21:52.48#ibcon#ireg 7 cls_cnt 0 2006.231.08:21:52.48#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:21:52.60#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:21:52.60#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:21:52.60#ibcon#enter wrdev, iclass 15, count 0 2006.231.08:21:52.60#ibcon#first serial, iclass 15, count 0 2006.231.08:21:52.60#ibcon#enter sib2, iclass 15, count 0 2006.231.08:21:52.60#ibcon#flushed, iclass 15, count 0 2006.231.08:21:52.60#ibcon#about to write, iclass 15, count 0 2006.231.08:21:52.60#ibcon#wrote, iclass 15, count 0 2006.231.08:21:52.60#ibcon#about to read 3, iclass 15, count 0 2006.231.08:21:52.62#ibcon#read 3, iclass 15, count 0 2006.231.08:21:52.62#ibcon#about to read 4, iclass 15, count 0 2006.231.08:21:52.62#ibcon#read 4, iclass 15, count 0 2006.231.08:21:52.62#ibcon#about to read 5, iclass 15, count 0 2006.231.08:21:52.62#ibcon#read 5, iclass 15, count 0 2006.231.08:21:52.62#ibcon#about to read 6, iclass 15, count 0 2006.231.08:21:52.62#ibcon#read 6, iclass 15, count 0 2006.231.08:21:52.62#ibcon#end of sib2, iclass 15, count 0 2006.231.08:21:52.62#ibcon#*mode == 0, iclass 15, count 0 2006.231.08:21:52.62#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.231.08:21:52.62#ibcon#[27=USB\r\n] 2006.231.08:21:52.62#ibcon#*before write, iclass 15, count 0 2006.231.08:21:52.62#ibcon#enter sib2, iclass 15, count 0 2006.231.08:21:52.62#ibcon#flushed, iclass 15, count 0 2006.231.08:21:52.62#ibcon#about to write, iclass 15, count 0 2006.231.08:21:52.62#ibcon#wrote, iclass 15, count 0 2006.231.08:21:52.62#ibcon#about to read 3, iclass 15, count 0 2006.231.08:21:52.65#ibcon#read 3, iclass 15, count 0 2006.231.08:21:52.65#ibcon#about to read 4, iclass 15, count 0 2006.231.08:21:52.65#ibcon#read 4, iclass 15, count 0 2006.231.08:21:52.65#ibcon#about to read 5, iclass 15, count 0 2006.231.08:21:52.65#ibcon#read 5, iclass 15, count 0 2006.231.08:21:52.65#ibcon#about to read 6, iclass 15, count 0 2006.231.08:21:52.65#ibcon#read 6, iclass 15, count 0 2006.231.08:21:52.65#ibcon#end of sib2, iclass 15, count 0 2006.231.08:21:52.65#ibcon#*after write, iclass 15, count 0 2006.231.08:21:52.65#ibcon#*before return 0, iclass 15, count 0 2006.231.08:21:52.65#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:21:52.65#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.231.08:21:52.65#ibcon#about to clear, iclass 15 cls_cnt 0 2006.231.08:21:52.65#ibcon#cleared, iclass 15 cls_cnt 0 2006.231.08:21:52.65$vc4f8/vabw=wide 2006.231.08:21:52.65#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.231.08:21:52.65#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.231.08:21:52.65#ibcon#ireg 8 cls_cnt 0 2006.231.08:21:52.65#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:21:52.65#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:21:52.65#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:21:52.65#ibcon#enter wrdev, iclass 17, count 0 2006.231.08:21:52.65#ibcon#first serial, iclass 17, count 0 2006.231.08:21:52.65#ibcon#enter sib2, iclass 17, count 0 2006.231.08:21:52.65#ibcon#flushed, iclass 17, count 0 2006.231.08:21:52.65#ibcon#about to write, iclass 17, count 0 2006.231.08:21:52.65#ibcon#wrote, iclass 17, count 0 2006.231.08:21:52.65#ibcon#about to read 3, iclass 17, count 0 2006.231.08:21:52.67#ibcon#read 3, iclass 17, count 0 2006.231.08:21:52.67#ibcon#about to read 4, iclass 17, count 0 2006.231.08:21:52.67#ibcon#read 4, iclass 17, count 0 2006.231.08:21:52.67#ibcon#about to read 5, iclass 17, count 0 2006.231.08:21:52.67#ibcon#read 5, iclass 17, count 0 2006.231.08:21:52.67#ibcon#about to read 6, iclass 17, count 0 2006.231.08:21:52.67#ibcon#read 6, iclass 17, count 0 2006.231.08:21:52.67#ibcon#end of sib2, iclass 17, count 0 2006.231.08:21:52.67#ibcon#*mode == 0, iclass 17, count 0 2006.231.08:21:52.67#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.231.08:21:52.67#ibcon#[25=BW32\r\n] 2006.231.08:21:52.67#ibcon#*before write, iclass 17, count 0 2006.231.08:21:52.67#ibcon#enter sib2, iclass 17, count 0 2006.231.08:21:52.67#ibcon#flushed, iclass 17, count 0 2006.231.08:21:52.67#ibcon#about to write, iclass 17, count 0 2006.231.08:21:52.67#ibcon#wrote, iclass 17, count 0 2006.231.08:21:52.67#ibcon#about to read 3, iclass 17, count 0 2006.231.08:21:52.70#ibcon#read 3, iclass 17, count 0 2006.231.08:21:52.70#ibcon#about to read 4, iclass 17, count 0 2006.231.08:21:52.70#ibcon#read 4, iclass 17, count 0 2006.231.08:21:52.70#ibcon#about to read 5, iclass 17, count 0 2006.231.08:21:52.70#ibcon#read 5, iclass 17, count 0 2006.231.08:21:52.70#ibcon#about to read 6, iclass 17, count 0 2006.231.08:21:52.70#ibcon#read 6, iclass 17, count 0 2006.231.08:21:52.70#ibcon#end of sib2, iclass 17, count 0 2006.231.08:21:52.70#ibcon#*after write, iclass 17, count 0 2006.231.08:21:52.70#ibcon#*before return 0, iclass 17, count 0 2006.231.08:21:52.70#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:21:52.70#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.231.08:21:52.70#ibcon#about to clear, iclass 17 cls_cnt 0 2006.231.08:21:52.70#ibcon#cleared, iclass 17 cls_cnt 0 2006.231.08:21:52.70$vc4f8/vbbw=wide 2006.231.08:21:52.70#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.231.08:21:52.70#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.231.08:21:52.70#ibcon#ireg 8 cls_cnt 0 2006.231.08:21:52.70#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:21:52.77#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:21:52.77#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:21:52.77#ibcon#enter wrdev, iclass 19, count 0 2006.231.08:21:52.77#ibcon#first serial, iclass 19, count 0 2006.231.08:21:52.77#ibcon#enter sib2, iclass 19, count 0 2006.231.08:21:52.77#ibcon#flushed, iclass 19, count 0 2006.231.08:21:52.77#ibcon#about to write, iclass 19, count 0 2006.231.08:21:52.77#ibcon#wrote, iclass 19, count 0 2006.231.08:21:52.77#ibcon#about to read 3, iclass 19, count 0 2006.231.08:21:52.79#ibcon#read 3, iclass 19, count 0 2006.231.08:21:52.79#ibcon#about to read 4, iclass 19, count 0 2006.231.08:21:52.79#ibcon#read 4, iclass 19, count 0 2006.231.08:21:52.79#ibcon#about to read 5, iclass 19, count 0 2006.231.08:21:52.79#ibcon#read 5, iclass 19, count 0 2006.231.08:21:52.79#ibcon#about to read 6, iclass 19, count 0 2006.231.08:21:52.79#ibcon#read 6, iclass 19, count 0 2006.231.08:21:52.79#ibcon#end of sib2, iclass 19, count 0 2006.231.08:21:52.79#ibcon#*mode == 0, iclass 19, count 0 2006.231.08:21:52.79#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.231.08:21:52.79#ibcon#[27=BW32\r\n] 2006.231.08:21:52.79#ibcon#*before write, iclass 19, count 0 2006.231.08:21:52.79#ibcon#enter sib2, iclass 19, count 0 2006.231.08:21:52.79#ibcon#flushed, iclass 19, count 0 2006.231.08:21:52.79#ibcon#about to write, iclass 19, count 0 2006.231.08:21:52.79#ibcon#wrote, iclass 19, count 0 2006.231.08:21:52.79#ibcon#about to read 3, iclass 19, count 0 2006.231.08:21:52.82#ibcon#read 3, iclass 19, count 0 2006.231.08:21:52.82#ibcon#about to read 4, iclass 19, count 0 2006.231.08:21:52.82#ibcon#read 4, iclass 19, count 0 2006.231.08:21:52.82#ibcon#about to read 5, iclass 19, count 0 2006.231.08:21:52.82#ibcon#read 5, iclass 19, count 0 2006.231.08:21:52.82#ibcon#about to read 6, iclass 19, count 0 2006.231.08:21:52.82#ibcon#read 6, iclass 19, count 0 2006.231.08:21:52.82#ibcon#end of sib2, iclass 19, count 0 2006.231.08:21:52.82#ibcon#*after write, iclass 19, count 0 2006.231.08:21:52.82#ibcon#*before return 0, iclass 19, count 0 2006.231.08:21:52.82#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:21:52.82#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.231.08:21:52.82#ibcon#about to clear, iclass 19 cls_cnt 0 2006.231.08:21:52.82#ibcon#cleared, iclass 19 cls_cnt 0 2006.231.08:21:52.82$4f8m12a/ifd4f 2006.231.08:21:52.82$ifd4f/lo= 2006.231.08:21:52.82$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:21:52.82$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:21:52.82$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:21:52.82$ifd4f/patch= 2006.231.08:21:52.82$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:21:52.82$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:21:52.82$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:21:52.82$4f8m12a/"form=m,16.000,1:2 2006.231.08:21:52.82$4f8m12a/"tpicd 2006.231.08:21:52.82$4f8m12a/echo=off 2006.231.08:21:52.82$4f8m12a/xlog=off 2006.231.08:21:52.82:!2006.231.08:24:00 2006.231.08:22:30.14#trakl#Source acquired 2006.231.08:22:32.14#flagr#flagr/antenna,acquired 2006.231.08:24:00.00:preob 2006.231.08:24:00.14/onsource/TRACKING 2006.231.08:24:00.14:!2006.231.08:24:10 2006.231.08:24:10.00:data_valid=on 2006.231.08:24:10.00:midob 2006.231.08:24:11.14/onsource/TRACKING 2006.231.08:24:11.14/wx/30.22,1004.5,84 2006.231.08:24:11.37/cable/+6.3708E-03 2006.231.08:24:12.46/va/01,08,usb,yes,35,37 2006.231.08:24:12.46/va/02,07,usb,yes,36,37 2006.231.08:24:12.46/va/03,08,usb,yes,27,27 2006.231.08:24:12.46/va/04,07,usb,yes,37,40 2006.231.08:24:12.46/va/05,07,usb,yes,41,43 2006.231.08:24:12.46/va/06,06,usb,yes,40,40 2006.231.08:24:12.46/va/07,06,usb,yes,41,41 2006.231.08:24:12.46/va/08,06,usb,yes,44,43 2006.231.08:24:12.69/valo/01,532.99,yes,locked 2006.231.08:24:12.69/valo/02,572.99,yes,locked 2006.231.08:24:12.69/valo/03,672.99,yes,locked 2006.231.08:24:12.69/valo/04,832.99,yes,locked 2006.231.08:24:12.69/valo/05,652.99,yes,locked 2006.231.08:24:12.69/valo/06,772.99,yes,locked 2006.231.08:24:12.69/valo/07,832.99,yes,locked 2006.231.08:24:12.69/valo/08,852.99,yes,locked 2006.231.08:24:13.78/vb/01,04,usb,yes,32,68 2006.231.08:24:13.78/vb/02,04,usb,yes,34,67 2006.231.08:24:13.78/vb/03,04,usb,yes,31,37 2006.231.08:24:13.78/vb/04,04,usb,yes,32,32 2006.231.08:24:13.78/vb/05,03,usb,yes,39,44 2006.231.08:24:13.78/vb/06,04,usb,yes,32,35 2006.231.08:24:13.78/vb/07,04,usb,yes,33,33 2006.231.08:24:13.78/vb/08,04,usb,yes,30,34 2006.231.08:24:14.02/vblo/01,632.99,yes,locked 2006.231.08:24:14.02/vblo/02,640.99,yes,locked 2006.231.08:24:14.02/vblo/03,656.99,yes,locked 2006.231.08:24:14.02/vblo/04,712.99,yes,locked 2006.231.08:24:14.02/vblo/05,744.99,yes,locked 2006.231.08:24:14.02/vblo/06,752.99,yes,locked 2006.231.08:24:14.02/vblo/07,734.99,yes,locked 2006.231.08:24:14.02/vblo/08,744.99,yes,locked 2006.231.08:24:14.17/vabw/8 2006.231.08:24:14.32/vbbw/8 2006.231.08:24:14.41/xfe/off,on,12.2 2006.231.08:24:14.80/ifatt/23,28,28,28 2006.231.08:24:15.07/fmout-gps/S +4.47E-07 2006.231.08:24:15.11:!2006.231.08:25:10 2006.231.08:25:10.00:data_valid=off 2006.231.08:25:10.00:postob 2006.231.08:25:10.13/cable/+6.3713E-03 2006.231.08:25:10.13/wx/30.20,1004.6,84 2006.231.08:25:11.08/fmout-gps/S +4.47E-07 2006.231.08:25:11.08:scan_name=231-0826,k06231,60 2006.231.08:25:11.08:source=1803+784,180045.68,782804.0,2000.0,neutral 2006.231.08:25:11.13#flagr#flagr/antenna,new-source 2006.231.08:25:12.13:checkk5 2006.231.08:25:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.231.08:25:12.98/chk_autoobs//k5ts2/ autoobs is running! 2006.231.08:25:13.35/chk_autoobs//k5ts3/ autoobs is running! 2006.231.08:25:13.74/chk_autoobs//k5ts4/ autoobs is running! 2006.231.08:25:14.10/chk_obsdata//k5ts1/T2310824??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:25:14.47/chk_obsdata//k5ts2/T2310824??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:25:14.84/chk_obsdata//k5ts3/T2310824??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:25:15.20/chk_obsdata//k5ts4/T2310824??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:25:15.89/k5log//k5ts1_log_newline 2006.231.08:25:16.58/k5log//k5ts2_log_newline 2006.231.08:25:17.27/k5log//k5ts3_log_newline 2006.231.08:25:17.95/k5log//k5ts4_log_newline 2006.231.08:25:17.98/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:25:17.98:4f8m12a=3 2006.231.08:25:17.98$4f8m12a/echo=on 2006.231.08:25:17.98$4f8m12a/pcalon 2006.231.08:25:17.98$pcalon/"no phase cal control is implemented here 2006.231.08:25:17.98$4f8m12a/"tpicd=stop 2006.231.08:25:17.98$4f8m12a/vc4f8 2006.231.08:25:17.98$vc4f8/valo=1,532.99 2006.231.08:25:17.98#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.08:25:17.98#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.08:25:17.98#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:17.98#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:25:17.98#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:25:17.98#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:25:17.98#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:25:17.98#ibcon#first serial, iclass 34, count 0 2006.231.08:25:17.98#ibcon#enter sib2, iclass 34, count 0 2006.231.08:25:17.98#ibcon#flushed, iclass 34, count 0 2006.231.08:25:17.98#ibcon#about to write, iclass 34, count 0 2006.231.08:25:17.98#ibcon#wrote, iclass 34, count 0 2006.231.08:25:17.98#ibcon#about to read 3, iclass 34, count 0 2006.231.08:25:18.02#ibcon#read 3, iclass 34, count 0 2006.231.08:25:18.02#ibcon#about to read 4, iclass 34, count 0 2006.231.08:25:18.02#ibcon#read 4, iclass 34, count 0 2006.231.08:25:18.02#ibcon#about to read 5, iclass 34, count 0 2006.231.08:25:18.02#ibcon#read 5, iclass 34, count 0 2006.231.08:25:18.02#ibcon#about to read 6, iclass 34, count 0 2006.231.08:25:18.02#ibcon#read 6, iclass 34, count 0 2006.231.08:25:18.02#ibcon#end of sib2, iclass 34, count 0 2006.231.08:25:18.02#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:25:18.02#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:25:18.02#ibcon#[26=FRQ=01,532.99\r\n] 2006.231.08:25:18.02#ibcon#*before write, iclass 34, count 0 2006.231.08:25:18.02#ibcon#enter sib2, iclass 34, count 0 2006.231.08:25:18.02#ibcon#flushed, iclass 34, count 0 2006.231.08:25:18.02#ibcon#about to write, iclass 34, count 0 2006.231.08:25:18.02#ibcon#wrote, iclass 34, count 0 2006.231.08:25:18.02#ibcon#about to read 3, iclass 34, count 0 2006.231.08:25:18.07#ibcon#read 3, iclass 34, count 0 2006.231.08:25:18.07#ibcon#about to read 4, iclass 34, count 0 2006.231.08:25:18.07#ibcon#read 4, iclass 34, count 0 2006.231.08:25:18.07#ibcon#about to read 5, iclass 34, count 0 2006.231.08:25:18.07#ibcon#read 5, iclass 34, count 0 2006.231.08:25:18.07#ibcon#about to read 6, iclass 34, count 0 2006.231.08:25:18.07#ibcon#read 6, iclass 34, count 0 2006.231.08:25:18.07#ibcon#end of sib2, iclass 34, count 0 2006.231.08:25:18.07#ibcon#*after write, iclass 34, count 0 2006.231.08:25:18.07#ibcon#*before return 0, iclass 34, count 0 2006.231.08:25:18.07#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:25:18.07#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:25:18.07#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:25:18.07#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:25:18.07$vc4f8/va=1,8 2006.231.08:25:18.07#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.08:25:18.07#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.08:25:18.07#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:18.07#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:25:18.07#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:25:18.07#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:25:18.07#ibcon#enter wrdev, iclass 36, count 2 2006.231.08:25:18.07#ibcon#first serial, iclass 36, count 2 2006.231.08:25:18.07#ibcon#enter sib2, iclass 36, count 2 2006.231.08:25:18.07#ibcon#flushed, iclass 36, count 2 2006.231.08:25:18.07#ibcon#about to write, iclass 36, count 2 2006.231.08:25:18.07#ibcon#wrote, iclass 36, count 2 2006.231.08:25:18.07#ibcon#about to read 3, iclass 36, count 2 2006.231.08:25:18.09#ibcon#read 3, iclass 36, count 2 2006.231.08:25:18.09#ibcon#about to read 4, iclass 36, count 2 2006.231.08:25:18.09#ibcon#read 4, iclass 36, count 2 2006.231.08:25:18.09#ibcon#about to read 5, iclass 36, count 2 2006.231.08:25:18.09#ibcon#read 5, iclass 36, count 2 2006.231.08:25:18.09#ibcon#about to read 6, iclass 36, count 2 2006.231.08:25:18.09#ibcon#read 6, iclass 36, count 2 2006.231.08:25:18.09#ibcon#end of sib2, iclass 36, count 2 2006.231.08:25:18.09#ibcon#*mode == 0, iclass 36, count 2 2006.231.08:25:18.09#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.08:25:18.09#ibcon#[25=AT01-08\r\n] 2006.231.08:25:18.09#ibcon#*before write, iclass 36, count 2 2006.231.08:25:18.09#ibcon#enter sib2, iclass 36, count 2 2006.231.08:25:18.09#ibcon#flushed, iclass 36, count 2 2006.231.08:25:18.09#ibcon#about to write, iclass 36, count 2 2006.231.08:25:18.09#ibcon#wrote, iclass 36, count 2 2006.231.08:25:18.09#ibcon#about to read 3, iclass 36, count 2 2006.231.08:25:18.12#ibcon#read 3, iclass 36, count 2 2006.231.08:25:18.12#ibcon#about to read 4, iclass 36, count 2 2006.231.08:25:18.12#ibcon#read 4, iclass 36, count 2 2006.231.08:25:18.12#ibcon#about to read 5, iclass 36, count 2 2006.231.08:25:18.12#ibcon#read 5, iclass 36, count 2 2006.231.08:25:18.12#ibcon#about to read 6, iclass 36, count 2 2006.231.08:25:18.12#ibcon#read 6, iclass 36, count 2 2006.231.08:25:18.12#ibcon#end of sib2, iclass 36, count 2 2006.231.08:25:18.12#ibcon#*after write, iclass 36, count 2 2006.231.08:25:18.12#ibcon#*before return 0, iclass 36, count 2 2006.231.08:25:18.12#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:25:18.12#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:25:18.12#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.08:25:18.12#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:18.12#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:25:18.24#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:25:18.24#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:25:18.24#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:25:18.24#ibcon#first serial, iclass 36, count 0 2006.231.08:25:18.24#ibcon#enter sib2, iclass 36, count 0 2006.231.08:25:18.24#ibcon#flushed, iclass 36, count 0 2006.231.08:25:18.24#ibcon#about to write, iclass 36, count 0 2006.231.08:25:18.24#ibcon#wrote, iclass 36, count 0 2006.231.08:25:18.24#ibcon#about to read 3, iclass 36, count 0 2006.231.08:25:18.26#ibcon#read 3, iclass 36, count 0 2006.231.08:25:18.26#ibcon#about to read 4, iclass 36, count 0 2006.231.08:25:18.26#ibcon#read 4, iclass 36, count 0 2006.231.08:25:18.26#ibcon#about to read 5, iclass 36, count 0 2006.231.08:25:18.26#ibcon#read 5, iclass 36, count 0 2006.231.08:25:18.26#ibcon#about to read 6, iclass 36, count 0 2006.231.08:25:18.26#ibcon#read 6, iclass 36, count 0 2006.231.08:25:18.26#ibcon#end of sib2, iclass 36, count 0 2006.231.08:25:18.26#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:25:18.26#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:25:18.26#ibcon#[25=USB\r\n] 2006.231.08:25:18.26#ibcon#*before write, iclass 36, count 0 2006.231.08:25:18.26#ibcon#enter sib2, iclass 36, count 0 2006.231.08:25:18.26#ibcon#flushed, iclass 36, count 0 2006.231.08:25:18.26#ibcon#about to write, iclass 36, count 0 2006.231.08:25:18.26#ibcon#wrote, iclass 36, count 0 2006.231.08:25:18.26#ibcon#about to read 3, iclass 36, count 0 2006.231.08:25:18.29#ibcon#read 3, iclass 36, count 0 2006.231.08:25:18.29#ibcon#about to read 4, iclass 36, count 0 2006.231.08:25:18.29#ibcon#read 4, iclass 36, count 0 2006.231.08:25:18.29#ibcon#about to read 5, iclass 36, count 0 2006.231.08:25:18.29#ibcon#read 5, iclass 36, count 0 2006.231.08:25:18.29#ibcon#about to read 6, iclass 36, count 0 2006.231.08:25:18.29#ibcon#read 6, iclass 36, count 0 2006.231.08:25:18.29#ibcon#end of sib2, iclass 36, count 0 2006.231.08:25:18.29#ibcon#*after write, iclass 36, count 0 2006.231.08:25:18.29#ibcon#*before return 0, iclass 36, count 0 2006.231.08:25:18.29#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:25:18.29#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:25:18.29#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:25:18.29#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:25:18.29$vc4f8/valo=2,572.99 2006.231.08:25:18.29#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.08:25:18.29#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.08:25:18.29#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:18.29#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:25:18.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:25:18.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:25:18.29#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:25:18.29#ibcon#first serial, iclass 38, count 0 2006.231.08:25:18.29#ibcon#enter sib2, iclass 38, count 0 2006.231.08:25:18.29#ibcon#flushed, iclass 38, count 0 2006.231.08:25:18.29#ibcon#about to write, iclass 38, count 0 2006.231.08:25:18.29#ibcon#wrote, iclass 38, count 0 2006.231.08:25:18.29#ibcon#about to read 3, iclass 38, count 0 2006.231.08:25:18.32#ibcon#read 3, iclass 38, count 0 2006.231.08:25:18.32#ibcon#about to read 4, iclass 38, count 0 2006.231.08:25:18.32#ibcon#read 4, iclass 38, count 0 2006.231.08:25:18.32#ibcon#about to read 5, iclass 38, count 0 2006.231.08:25:18.32#ibcon#read 5, iclass 38, count 0 2006.231.08:25:18.32#ibcon#about to read 6, iclass 38, count 0 2006.231.08:25:18.32#ibcon#read 6, iclass 38, count 0 2006.231.08:25:18.32#ibcon#end of sib2, iclass 38, count 0 2006.231.08:25:18.32#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:25:18.32#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:25:18.32#ibcon#[26=FRQ=02,572.99\r\n] 2006.231.08:25:18.32#ibcon#*before write, iclass 38, count 0 2006.231.08:25:18.32#ibcon#enter sib2, iclass 38, count 0 2006.231.08:25:18.32#ibcon#flushed, iclass 38, count 0 2006.231.08:25:18.32#ibcon#about to write, iclass 38, count 0 2006.231.08:25:18.32#ibcon#wrote, iclass 38, count 0 2006.231.08:25:18.32#ibcon#about to read 3, iclass 38, count 0 2006.231.08:25:18.36#ibcon#read 3, iclass 38, count 0 2006.231.08:25:18.36#ibcon#about to read 4, iclass 38, count 0 2006.231.08:25:18.36#ibcon#read 4, iclass 38, count 0 2006.231.08:25:18.36#ibcon#about to read 5, iclass 38, count 0 2006.231.08:25:18.36#ibcon#read 5, iclass 38, count 0 2006.231.08:25:18.36#ibcon#about to read 6, iclass 38, count 0 2006.231.08:25:18.36#ibcon#read 6, iclass 38, count 0 2006.231.08:25:18.36#ibcon#end of sib2, iclass 38, count 0 2006.231.08:25:18.36#ibcon#*after write, iclass 38, count 0 2006.231.08:25:18.36#ibcon#*before return 0, iclass 38, count 0 2006.231.08:25:18.36#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:25:18.36#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:25:18.36#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:25:18.36#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:25:18.36$vc4f8/va=2,7 2006.231.08:25:18.36#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.08:25:18.36#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.08:25:18.36#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:18.36#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:25:18.41#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:25:18.41#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:25:18.41#ibcon#enter wrdev, iclass 40, count 2 2006.231.08:25:18.41#ibcon#first serial, iclass 40, count 2 2006.231.08:25:18.41#ibcon#enter sib2, iclass 40, count 2 2006.231.08:25:18.41#ibcon#flushed, iclass 40, count 2 2006.231.08:25:18.41#ibcon#about to write, iclass 40, count 2 2006.231.08:25:18.41#ibcon#wrote, iclass 40, count 2 2006.231.08:25:18.41#ibcon#about to read 3, iclass 40, count 2 2006.231.08:25:18.43#ibcon#read 3, iclass 40, count 2 2006.231.08:25:18.43#ibcon#about to read 4, iclass 40, count 2 2006.231.08:25:18.43#ibcon#read 4, iclass 40, count 2 2006.231.08:25:18.43#ibcon#about to read 5, iclass 40, count 2 2006.231.08:25:18.43#ibcon#read 5, iclass 40, count 2 2006.231.08:25:18.43#ibcon#about to read 6, iclass 40, count 2 2006.231.08:25:18.43#ibcon#read 6, iclass 40, count 2 2006.231.08:25:18.43#ibcon#end of sib2, iclass 40, count 2 2006.231.08:25:18.43#ibcon#*mode == 0, iclass 40, count 2 2006.231.08:25:18.43#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.08:25:18.43#ibcon#[25=AT02-07\r\n] 2006.231.08:25:18.43#ibcon#*before write, iclass 40, count 2 2006.231.08:25:18.43#ibcon#enter sib2, iclass 40, count 2 2006.231.08:25:18.43#ibcon#flushed, iclass 40, count 2 2006.231.08:25:18.43#ibcon#about to write, iclass 40, count 2 2006.231.08:25:18.43#ibcon#wrote, iclass 40, count 2 2006.231.08:25:18.43#ibcon#about to read 3, iclass 40, count 2 2006.231.08:25:18.46#ibcon#read 3, iclass 40, count 2 2006.231.08:25:18.46#ibcon#about to read 4, iclass 40, count 2 2006.231.08:25:18.46#ibcon#read 4, iclass 40, count 2 2006.231.08:25:18.46#ibcon#about to read 5, iclass 40, count 2 2006.231.08:25:18.46#ibcon#read 5, iclass 40, count 2 2006.231.08:25:18.46#ibcon#about to read 6, iclass 40, count 2 2006.231.08:25:18.46#ibcon#read 6, iclass 40, count 2 2006.231.08:25:18.46#ibcon#end of sib2, iclass 40, count 2 2006.231.08:25:18.46#ibcon#*after write, iclass 40, count 2 2006.231.08:25:18.46#ibcon#*before return 0, iclass 40, count 2 2006.231.08:25:18.46#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:25:18.46#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:25:18.46#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.08:25:18.46#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:18.46#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:25:18.58#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:25:18.58#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:25:18.58#ibcon#enter wrdev, iclass 40, count 0 2006.231.08:25:18.58#ibcon#first serial, iclass 40, count 0 2006.231.08:25:18.58#ibcon#enter sib2, iclass 40, count 0 2006.231.08:25:18.58#ibcon#flushed, iclass 40, count 0 2006.231.08:25:18.58#ibcon#about to write, iclass 40, count 0 2006.231.08:25:18.58#ibcon#wrote, iclass 40, count 0 2006.231.08:25:18.58#ibcon#about to read 3, iclass 40, count 0 2006.231.08:25:18.60#ibcon#read 3, iclass 40, count 0 2006.231.08:25:18.60#ibcon#about to read 4, iclass 40, count 0 2006.231.08:25:18.60#ibcon#read 4, iclass 40, count 0 2006.231.08:25:18.60#ibcon#about to read 5, iclass 40, count 0 2006.231.08:25:18.60#ibcon#read 5, iclass 40, count 0 2006.231.08:25:18.60#ibcon#about to read 6, iclass 40, count 0 2006.231.08:25:18.60#ibcon#read 6, iclass 40, count 0 2006.231.08:25:18.60#ibcon#end of sib2, iclass 40, count 0 2006.231.08:25:18.60#ibcon#*mode == 0, iclass 40, count 0 2006.231.08:25:18.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.08:25:18.60#ibcon#[25=USB\r\n] 2006.231.08:25:18.60#ibcon#*before write, iclass 40, count 0 2006.231.08:25:18.60#ibcon#enter sib2, iclass 40, count 0 2006.231.08:25:18.60#ibcon#flushed, iclass 40, count 0 2006.231.08:25:18.60#ibcon#about to write, iclass 40, count 0 2006.231.08:25:18.60#ibcon#wrote, iclass 40, count 0 2006.231.08:25:18.60#ibcon#about to read 3, iclass 40, count 0 2006.231.08:25:18.63#ibcon#read 3, iclass 40, count 0 2006.231.08:25:18.63#ibcon#about to read 4, iclass 40, count 0 2006.231.08:25:18.63#ibcon#read 4, iclass 40, count 0 2006.231.08:25:18.63#ibcon#about to read 5, iclass 40, count 0 2006.231.08:25:18.63#ibcon#read 5, iclass 40, count 0 2006.231.08:25:18.63#ibcon#about to read 6, iclass 40, count 0 2006.231.08:25:18.63#ibcon#read 6, iclass 40, count 0 2006.231.08:25:18.63#ibcon#end of sib2, iclass 40, count 0 2006.231.08:25:18.63#ibcon#*after write, iclass 40, count 0 2006.231.08:25:18.63#ibcon#*before return 0, iclass 40, count 0 2006.231.08:25:18.63#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:25:18.63#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:25:18.63#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.08:25:18.63#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.08:25:18.63$vc4f8/valo=3,672.99 2006.231.08:25:18.63#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.08:25:18.63#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.08:25:18.63#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:18.63#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:25:18.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:25:18.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:25:18.63#ibcon#enter wrdev, iclass 4, count 0 2006.231.08:25:18.63#ibcon#first serial, iclass 4, count 0 2006.231.08:25:18.63#ibcon#enter sib2, iclass 4, count 0 2006.231.08:25:18.63#ibcon#flushed, iclass 4, count 0 2006.231.08:25:18.63#ibcon#about to write, iclass 4, count 0 2006.231.08:25:18.63#ibcon#wrote, iclass 4, count 0 2006.231.08:25:18.63#ibcon#about to read 3, iclass 4, count 0 2006.231.08:25:18.65#ibcon#read 3, iclass 4, count 0 2006.231.08:25:18.65#ibcon#about to read 4, iclass 4, count 0 2006.231.08:25:18.65#ibcon#read 4, iclass 4, count 0 2006.231.08:25:18.65#ibcon#about to read 5, iclass 4, count 0 2006.231.08:25:18.65#ibcon#read 5, iclass 4, count 0 2006.231.08:25:18.65#ibcon#about to read 6, iclass 4, count 0 2006.231.08:25:18.65#ibcon#read 6, iclass 4, count 0 2006.231.08:25:18.65#ibcon#end of sib2, iclass 4, count 0 2006.231.08:25:18.65#ibcon#*mode == 0, iclass 4, count 0 2006.231.08:25:18.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.08:25:18.65#ibcon#[26=FRQ=03,672.99\r\n] 2006.231.08:25:18.65#ibcon#*before write, iclass 4, count 0 2006.231.08:25:18.65#ibcon#enter sib2, iclass 4, count 0 2006.231.08:25:18.65#ibcon#flushed, iclass 4, count 0 2006.231.08:25:18.65#ibcon#about to write, iclass 4, count 0 2006.231.08:25:18.65#ibcon#wrote, iclass 4, count 0 2006.231.08:25:18.65#ibcon#about to read 3, iclass 4, count 0 2006.231.08:25:18.69#ibcon#read 3, iclass 4, count 0 2006.231.08:25:18.69#ibcon#about to read 4, iclass 4, count 0 2006.231.08:25:18.69#ibcon#read 4, iclass 4, count 0 2006.231.08:25:18.69#ibcon#about to read 5, iclass 4, count 0 2006.231.08:25:18.69#ibcon#read 5, iclass 4, count 0 2006.231.08:25:18.69#ibcon#about to read 6, iclass 4, count 0 2006.231.08:25:18.69#ibcon#read 6, iclass 4, count 0 2006.231.08:25:18.69#ibcon#end of sib2, iclass 4, count 0 2006.231.08:25:18.69#ibcon#*after write, iclass 4, count 0 2006.231.08:25:18.69#ibcon#*before return 0, iclass 4, count 0 2006.231.08:25:18.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:25:18.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:25:18.69#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.08:25:18.69#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.08:25:18.69$vc4f8/va=3,8 2006.231.08:25:18.69#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.08:25:18.69#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.08:25:18.69#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:18.69#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:25:18.75#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:25:18.75#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:25:18.75#ibcon#enter wrdev, iclass 6, count 2 2006.231.08:25:18.75#ibcon#first serial, iclass 6, count 2 2006.231.08:25:18.75#ibcon#enter sib2, iclass 6, count 2 2006.231.08:25:18.75#ibcon#flushed, iclass 6, count 2 2006.231.08:25:18.75#ibcon#about to write, iclass 6, count 2 2006.231.08:25:18.75#ibcon#wrote, iclass 6, count 2 2006.231.08:25:18.75#ibcon#about to read 3, iclass 6, count 2 2006.231.08:25:18.77#ibcon#read 3, iclass 6, count 2 2006.231.08:25:18.77#ibcon#about to read 4, iclass 6, count 2 2006.231.08:25:18.77#ibcon#read 4, iclass 6, count 2 2006.231.08:25:18.77#ibcon#about to read 5, iclass 6, count 2 2006.231.08:25:18.77#ibcon#read 5, iclass 6, count 2 2006.231.08:25:18.77#ibcon#about to read 6, iclass 6, count 2 2006.231.08:25:18.77#ibcon#read 6, iclass 6, count 2 2006.231.08:25:18.77#ibcon#end of sib2, iclass 6, count 2 2006.231.08:25:18.77#ibcon#*mode == 0, iclass 6, count 2 2006.231.08:25:18.77#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.08:25:18.77#ibcon#[25=AT03-08\r\n] 2006.231.08:25:18.77#ibcon#*before write, iclass 6, count 2 2006.231.08:25:18.77#ibcon#enter sib2, iclass 6, count 2 2006.231.08:25:18.77#ibcon#flushed, iclass 6, count 2 2006.231.08:25:18.77#ibcon#about to write, iclass 6, count 2 2006.231.08:25:18.77#ibcon#wrote, iclass 6, count 2 2006.231.08:25:18.77#ibcon#about to read 3, iclass 6, count 2 2006.231.08:25:18.81#ibcon#read 3, iclass 6, count 2 2006.231.08:25:18.81#ibcon#about to read 4, iclass 6, count 2 2006.231.08:25:18.81#ibcon#read 4, iclass 6, count 2 2006.231.08:25:18.81#ibcon#about to read 5, iclass 6, count 2 2006.231.08:25:18.81#ibcon#read 5, iclass 6, count 2 2006.231.08:25:18.81#ibcon#about to read 6, iclass 6, count 2 2006.231.08:25:18.81#ibcon#read 6, iclass 6, count 2 2006.231.08:25:18.81#ibcon#end of sib2, iclass 6, count 2 2006.231.08:25:18.81#ibcon#*after write, iclass 6, count 2 2006.231.08:25:18.81#ibcon#*before return 0, iclass 6, count 2 2006.231.08:25:18.81#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:25:18.81#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:25:18.81#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.08:25:18.81#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:18.81#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:25:18.93#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:25:18.93#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:25:18.93#ibcon#enter wrdev, iclass 6, count 0 2006.231.08:25:18.93#ibcon#first serial, iclass 6, count 0 2006.231.08:25:18.93#ibcon#enter sib2, iclass 6, count 0 2006.231.08:25:18.93#ibcon#flushed, iclass 6, count 0 2006.231.08:25:18.93#ibcon#about to write, iclass 6, count 0 2006.231.08:25:18.93#ibcon#wrote, iclass 6, count 0 2006.231.08:25:18.93#ibcon#about to read 3, iclass 6, count 0 2006.231.08:25:18.95#ibcon#read 3, iclass 6, count 0 2006.231.08:25:18.95#ibcon#about to read 4, iclass 6, count 0 2006.231.08:25:18.95#ibcon#read 4, iclass 6, count 0 2006.231.08:25:18.95#ibcon#about to read 5, iclass 6, count 0 2006.231.08:25:18.95#ibcon#read 5, iclass 6, count 0 2006.231.08:25:18.95#ibcon#about to read 6, iclass 6, count 0 2006.231.08:25:18.95#ibcon#read 6, iclass 6, count 0 2006.231.08:25:18.95#ibcon#end of sib2, iclass 6, count 0 2006.231.08:25:18.95#ibcon#*mode == 0, iclass 6, count 0 2006.231.08:25:18.95#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.08:25:18.95#ibcon#[25=USB\r\n] 2006.231.08:25:18.95#ibcon#*before write, iclass 6, count 0 2006.231.08:25:18.95#ibcon#enter sib2, iclass 6, count 0 2006.231.08:25:18.95#ibcon#flushed, iclass 6, count 0 2006.231.08:25:18.95#ibcon#about to write, iclass 6, count 0 2006.231.08:25:18.95#ibcon#wrote, iclass 6, count 0 2006.231.08:25:18.95#ibcon#about to read 3, iclass 6, count 0 2006.231.08:25:18.98#ibcon#read 3, iclass 6, count 0 2006.231.08:25:18.98#ibcon#about to read 4, iclass 6, count 0 2006.231.08:25:18.98#ibcon#read 4, iclass 6, count 0 2006.231.08:25:18.98#ibcon#about to read 5, iclass 6, count 0 2006.231.08:25:18.98#ibcon#read 5, iclass 6, count 0 2006.231.08:25:18.98#ibcon#about to read 6, iclass 6, count 0 2006.231.08:25:18.98#ibcon#read 6, iclass 6, count 0 2006.231.08:25:18.98#ibcon#end of sib2, iclass 6, count 0 2006.231.08:25:18.98#ibcon#*after write, iclass 6, count 0 2006.231.08:25:18.98#ibcon#*before return 0, iclass 6, count 0 2006.231.08:25:18.98#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:25:18.98#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:25:18.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.08:25:18.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.08:25:18.98$vc4f8/valo=4,832.99 2006.231.08:25:18.98#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.08:25:18.98#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.08:25:18.98#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:18.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:25:18.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:25:18.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:25:18.98#ibcon#enter wrdev, iclass 10, count 0 2006.231.08:25:18.98#ibcon#first serial, iclass 10, count 0 2006.231.08:25:18.98#ibcon#enter sib2, iclass 10, count 0 2006.231.08:25:18.98#ibcon#flushed, iclass 10, count 0 2006.231.08:25:18.98#ibcon#about to write, iclass 10, count 0 2006.231.08:25:18.98#ibcon#wrote, iclass 10, count 0 2006.231.08:25:18.98#ibcon#about to read 3, iclass 10, count 0 2006.231.08:25:19.00#ibcon#read 3, iclass 10, count 0 2006.231.08:25:19.00#ibcon#about to read 4, iclass 10, count 0 2006.231.08:25:19.00#ibcon#read 4, iclass 10, count 0 2006.231.08:25:19.00#ibcon#about to read 5, iclass 10, count 0 2006.231.08:25:19.00#ibcon#read 5, iclass 10, count 0 2006.231.08:25:19.00#ibcon#about to read 6, iclass 10, count 0 2006.231.08:25:19.00#ibcon#read 6, iclass 10, count 0 2006.231.08:25:19.00#ibcon#end of sib2, iclass 10, count 0 2006.231.08:25:19.00#ibcon#*mode == 0, iclass 10, count 0 2006.231.08:25:19.00#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.08:25:19.00#ibcon#[26=FRQ=04,832.99\r\n] 2006.231.08:25:19.00#ibcon#*before write, iclass 10, count 0 2006.231.08:25:19.00#ibcon#enter sib2, iclass 10, count 0 2006.231.08:25:19.00#ibcon#flushed, iclass 10, count 0 2006.231.08:25:19.00#ibcon#about to write, iclass 10, count 0 2006.231.08:25:19.00#ibcon#wrote, iclass 10, count 0 2006.231.08:25:19.00#ibcon#about to read 3, iclass 10, count 0 2006.231.08:25:19.04#ibcon#read 3, iclass 10, count 0 2006.231.08:25:19.04#ibcon#about to read 4, iclass 10, count 0 2006.231.08:25:19.04#ibcon#read 4, iclass 10, count 0 2006.231.08:25:19.04#ibcon#about to read 5, iclass 10, count 0 2006.231.08:25:19.04#ibcon#read 5, iclass 10, count 0 2006.231.08:25:19.04#ibcon#about to read 6, iclass 10, count 0 2006.231.08:25:19.04#ibcon#read 6, iclass 10, count 0 2006.231.08:25:19.04#ibcon#end of sib2, iclass 10, count 0 2006.231.08:25:19.04#ibcon#*after write, iclass 10, count 0 2006.231.08:25:19.04#ibcon#*before return 0, iclass 10, count 0 2006.231.08:25:19.04#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:25:19.04#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:25:19.04#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.08:25:19.04#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.08:25:19.04$vc4f8/va=4,7 2006.231.08:25:19.04#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.08:25:19.04#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.08:25:19.04#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:19.04#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:25:19.10#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:25:19.10#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:25:19.10#ibcon#enter wrdev, iclass 12, count 2 2006.231.08:25:19.10#ibcon#first serial, iclass 12, count 2 2006.231.08:25:19.10#ibcon#enter sib2, iclass 12, count 2 2006.231.08:25:19.10#ibcon#flushed, iclass 12, count 2 2006.231.08:25:19.10#ibcon#about to write, iclass 12, count 2 2006.231.08:25:19.10#ibcon#wrote, iclass 12, count 2 2006.231.08:25:19.10#ibcon#about to read 3, iclass 12, count 2 2006.231.08:25:19.12#ibcon#read 3, iclass 12, count 2 2006.231.08:25:19.12#ibcon#about to read 4, iclass 12, count 2 2006.231.08:25:19.12#ibcon#read 4, iclass 12, count 2 2006.231.08:25:19.12#ibcon#about to read 5, iclass 12, count 2 2006.231.08:25:19.12#ibcon#read 5, iclass 12, count 2 2006.231.08:25:19.12#ibcon#about to read 6, iclass 12, count 2 2006.231.08:25:19.12#ibcon#read 6, iclass 12, count 2 2006.231.08:25:19.12#ibcon#end of sib2, iclass 12, count 2 2006.231.08:25:19.12#ibcon#*mode == 0, iclass 12, count 2 2006.231.08:25:19.12#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.08:25:19.12#ibcon#[25=AT04-07\r\n] 2006.231.08:25:19.12#ibcon#*before write, iclass 12, count 2 2006.231.08:25:19.12#ibcon#enter sib2, iclass 12, count 2 2006.231.08:25:19.12#ibcon#flushed, iclass 12, count 2 2006.231.08:25:19.12#ibcon#about to write, iclass 12, count 2 2006.231.08:25:19.12#ibcon#wrote, iclass 12, count 2 2006.231.08:25:19.12#ibcon#about to read 3, iclass 12, count 2 2006.231.08:25:19.15#ibcon#read 3, iclass 12, count 2 2006.231.08:25:19.15#ibcon#about to read 4, iclass 12, count 2 2006.231.08:25:19.15#ibcon#read 4, iclass 12, count 2 2006.231.08:25:19.15#ibcon#about to read 5, iclass 12, count 2 2006.231.08:25:19.15#ibcon#read 5, iclass 12, count 2 2006.231.08:25:19.15#ibcon#about to read 6, iclass 12, count 2 2006.231.08:25:19.15#ibcon#read 6, iclass 12, count 2 2006.231.08:25:19.15#ibcon#end of sib2, iclass 12, count 2 2006.231.08:25:19.15#ibcon#*after write, iclass 12, count 2 2006.231.08:25:19.15#ibcon#*before return 0, iclass 12, count 2 2006.231.08:25:19.15#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:25:19.15#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:25:19.15#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.08:25:19.15#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:19.15#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:25:19.27#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:25:19.27#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:25:19.27#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:25:19.27#ibcon#first serial, iclass 12, count 0 2006.231.08:25:19.27#ibcon#enter sib2, iclass 12, count 0 2006.231.08:25:19.27#ibcon#flushed, iclass 12, count 0 2006.231.08:25:19.27#ibcon#about to write, iclass 12, count 0 2006.231.08:25:19.27#ibcon#wrote, iclass 12, count 0 2006.231.08:25:19.27#ibcon#about to read 3, iclass 12, count 0 2006.231.08:25:19.29#ibcon#read 3, iclass 12, count 0 2006.231.08:25:19.29#ibcon#about to read 4, iclass 12, count 0 2006.231.08:25:19.29#ibcon#read 4, iclass 12, count 0 2006.231.08:25:19.29#ibcon#about to read 5, iclass 12, count 0 2006.231.08:25:19.29#ibcon#read 5, iclass 12, count 0 2006.231.08:25:19.29#ibcon#about to read 6, iclass 12, count 0 2006.231.08:25:19.29#ibcon#read 6, iclass 12, count 0 2006.231.08:25:19.29#ibcon#end of sib2, iclass 12, count 0 2006.231.08:25:19.29#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:25:19.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:25:19.29#ibcon#[25=USB\r\n] 2006.231.08:25:19.29#ibcon#*before write, iclass 12, count 0 2006.231.08:25:19.29#ibcon#enter sib2, iclass 12, count 0 2006.231.08:25:19.29#ibcon#flushed, iclass 12, count 0 2006.231.08:25:19.29#ibcon#about to write, iclass 12, count 0 2006.231.08:25:19.29#ibcon#wrote, iclass 12, count 0 2006.231.08:25:19.29#ibcon#about to read 3, iclass 12, count 0 2006.231.08:25:19.32#ibcon#read 3, iclass 12, count 0 2006.231.08:25:19.32#ibcon#about to read 4, iclass 12, count 0 2006.231.08:25:19.32#ibcon#read 4, iclass 12, count 0 2006.231.08:25:19.32#ibcon#about to read 5, iclass 12, count 0 2006.231.08:25:19.32#ibcon#read 5, iclass 12, count 0 2006.231.08:25:19.32#ibcon#about to read 6, iclass 12, count 0 2006.231.08:25:19.32#ibcon#read 6, iclass 12, count 0 2006.231.08:25:19.32#ibcon#end of sib2, iclass 12, count 0 2006.231.08:25:19.32#ibcon#*after write, iclass 12, count 0 2006.231.08:25:19.32#ibcon#*before return 0, iclass 12, count 0 2006.231.08:25:19.32#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:25:19.32#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:25:19.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:25:19.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:25:19.32$vc4f8/valo=5,652.99 2006.231.08:25:19.32#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.08:25:19.32#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.08:25:19.32#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:19.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:25:19.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:25:19.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:25:19.32#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:25:19.32#ibcon#first serial, iclass 14, count 0 2006.231.08:25:19.32#ibcon#enter sib2, iclass 14, count 0 2006.231.08:25:19.32#ibcon#flushed, iclass 14, count 0 2006.231.08:25:19.32#ibcon#about to write, iclass 14, count 0 2006.231.08:25:19.32#ibcon#wrote, iclass 14, count 0 2006.231.08:25:19.32#ibcon#about to read 3, iclass 14, count 0 2006.231.08:25:19.34#ibcon#read 3, iclass 14, count 0 2006.231.08:25:19.34#ibcon#about to read 4, iclass 14, count 0 2006.231.08:25:19.34#ibcon#read 4, iclass 14, count 0 2006.231.08:25:19.34#ibcon#about to read 5, iclass 14, count 0 2006.231.08:25:19.34#ibcon#read 5, iclass 14, count 0 2006.231.08:25:19.34#ibcon#about to read 6, iclass 14, count 0 2006.231.08:25:19.34#ibcon#read 6, iclass 14, count 0 2006.231.08:25:19.34#ibcon#end of sib2, iclass 14, count 0 2006.231.08:25:19.34#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:25:19.34#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:25:19.34#ibcon#[26=FRQ=05,652.99\r\n] 2006.231.08:25:19.34#ibcon#*before write, iclass 14, count 0 2006.231.08:25:19.34#ibcon#enter sib2, iclass 14, count 0 2006.231.08:25:19.34#ibcon#flushed, iclass 14, count 0 2006.231.08:25:19.34#ibcon#about to write, iclass 14, count 0 2006.231.08:25:19.34#ibcon#wrote, iclass 14, count 0 2006.231.08:25:19.34#ibcon#about to read 3, iclass 14, count 0 2006.231.08:25:19.38#ibcon#read 3, iclass 14, count 0 2006.231.08:25:19.38#ibcon#about to read 4, iclass 14, count 0 2006.231.08:25:19.38#ibcon#read 4, iclass 14, count 0 2006.231.08:25:19.38#ibcon#about to read 5, iclass 14, count 0 2006.231.08:25:19.38#ibcon#read 5, iclass 14, count 0 2006.231.08:25:19.38#ibcon#about to read 6, iclass 14, count 0 2006.231.08:25:19.38#ibcon#read 6, iclass 14, count 0 2006.231.08:25:19.38#ibcon#end of sib2, iclass 14, count 0 2006.231.08:25:19.38#ibcon#*after write, iclass 14, count 0 2006.231.08:25:19.38#ibcon#*before return 0, iclass 14, count 0 2006.231.08:25:19.38#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:25:19.38#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:25:19.38#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:25:19.38#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:25:19.38$vc4f8/va=5,7 2006.231.08:25:19.38#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.08:25:19.38#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.08:25:19.38#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:19.38#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:25:19.44#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:25:19.44#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:25:19.44#ibcon#enter wrdev, iclass 16, count 2 2006.231.08:25:19.44#ibcon#first serial, iclass 16, count 2 2006.231.08:25:19.44#ibcon#enter sib2, iclass 16, count 2 2006.231.08:25:19.44#ibcon#flushed, iclass 16, count 2 2006.231.08:25:19.44#ibcon#about to write, iclass 16, count 2 2006.231.08:25:19.44#ibcon#wrote, iclass 16, count 2 2006.231.08:25:19.44#ibcon#about to read 3, iclass 16, count 2 2006.231.08:25:19.46#ibcon#read 3, iclass 16, count 2 2006.231.08:25:19.46#ibcon#about to read 4, iclass 16, count 2 2006.231.08:25:19.46#ibcon#read 4, iclass 16, count 2 2006.231.08:25:19.46#ibcon#about to read 5, iclass 16, count 2 2006.231.08:25:19.46#ibcon#read 5, iclass 16, count 2 2006.231.08:25:19.46#ibcon#about to read 6, iclass 16, count 2 2006.231.08:25:19.46#ibcon#read 6, iclass 16, count 2 2006.231.08:25:19.46#ibcon#end of sib2, iclass 16, count 2 2006.231.08:25:19.46#ibcon#*mode == 0, iclass 16, count 2 2006.231.08:25:19.46#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.08:25:19.46#ibcon#[25=AT05-07\r\n] 2006.231.08:25:19.46#ibcon#*before write, iclass 16, count 2 2006.231.08:25:19.46#ibcon#enter sib2, iclass 16, count 2 2006.231.08:25:19.46#ibcon#flushed, iclass 16, count 2 2006.231.08:25:19.46#ibcon#about to write, iclass 16, count 2 2006.231.08:25:19.46#ibcon#wrote, iclass 16, count 2 2006.231.08:25:19.46#ibcon#about to read 3, iclass 16, count 2 2006.231.08:25:19.49#ibcon#read 3, iclass 16, count 2 2006.231.08:25:19.49#ibcon#about to read 4, iclass 16, count 2 2006.231.08:25:19.49#ibcon#read 4, iclass 16, count 2 2006.231.08:25:19.49#ibcon#about to read 5, iclass 16, count 2 2006.231.08:25:19.49#ibcon#read 5, iclass 16, count 2 2006.231.08:25:19.49#ibcon#about to read 6, iclass 16, count 2 2006.231.08:25:19.49#ibcon#read 6, iclass 16, count 2 2006.231.08:25:19.49#ibcon#end of sib2, iclass 16, count 2 2006.231.08:25:19.49#ibcon#*after write, iclass 16, count 2 2006.231.08:25:19.49#ibcon#*before return 0, iclass 16, count 2 2006.231.08:25:19.49#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:25:19.49#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:25:19.49#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.08:25:19.49#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:19.49#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:25:19.61#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:25:19.61#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:25:19.61#ibcon#enter wrdev, iclass 16, count 0 2006.231.08:25:19.61#ibcon#first serial, iclass 16, count 0 2006.231.08:25:19.61#ibcon#enter sib2, iclass 16, count 0 2006.231.08:25:19.61#ibcon#flushed, iclass 16, count 0 2006.231.08:25:19.61#ibcon#about to write, iclass 16, count 0 2006.231.08:25:19.61#ibcon#wrote, iclass 16, count 0 2006.231.08:25:19.61#ibcon#about to read 3, iclass 16, count 0 2006.231.08:25:19.63#ibcon#read 3, iclass 16, count 0 2006.231.08:25:19.63#ibcon#about to read 4, iclass 16, count 0 2006.231.08:25:19.63#ibcon#read 4, iclass 16, count 0 2006.231.08:25:19.63#ibcon#about to read 5, iclass 16, count 0 2006.231.08:25:19.63#ibcon#read 5, iclass 16, count 0 2006.231.08:25:19.63#ibcon#about to read 6, iclass 16, count 0 2006.231.08:25:19.63#ibcon#read 6, iclass 16, count 0 2006.231.08:25:19.63#ibcon#end of sib2, iclass 16, count 0 2006.231.08:25:19.63#ibcon#*mode == 0, iclass 16, count 0 2006.231.08:25:19.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.08:25:19.63#ibcon#[25=USB\r\n] 2006.231.08:25:19.63#ibcon#*before write, iclass 16, count 0 2006.231.08:25:19.63#ibcon#enter sib2, iclass 16, count 0 2006.231.08:25:19.63#ibcon#flushed, iclass 16, count 0 2006.231.08:25:19.63#ibcon#about to write, iclass 16, count 0 2006.231.08:25:19.63#ibcon#wrote, iclass 16, count 0 2006.231.08:25:19.63#ibcon#about to read 3, iclass 16, count 0 2006.231.08:25:19.66#ibcon#read 3, iclass 16, count 0 2006.231.08:25:19.66#ibcon#about to read 4, iclass 16, count 0 2006.231.08:25:19.66#ibcon#read 4, iclass 16, count 0 2006.231.08:25:19.66#ibcon#about to read 5, iclass 16, count 0 2006.231.08:25:19.66#ibcon#read 5, iclass 16, count 0 2006.231.08:25:19.66#ibcon#about to read 6, iclass 16, count 0 2006.231.08:25:19.66#ibcon#read 6, iclass 16, count 0 2006.231.08:25:19.66#ibcon#end of sib2, iclass 16, count 0 2006.231.08:25:19.66#ibcon#*after write, iclass 16, count 0 2006.231.08:25:19.66#ibcon#*before return 0, iclass 16, count 0 2006.231.08:25:19.66#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:25:19.66#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:25:19.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.08:25:19.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.08:25:19.66$vc4f8/valo=6,772.99 2006.231.08:25:19.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.08:25:19.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.08:25:19.66#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:19.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:25:19.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:25:19.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:25:19.66#ibcon#enter wrdev, iclass 18, count 0 2006.231.08:25:19.66#ibcon#first serial, iclass 18, count 0 2006.231.08:25:19.66#ibcon#enter sib2, iclass 18, count 0 2006.231.08:25:19.66#ibcon#flushed, iclass 18, count 0 2006.231.08:25:19.66#ibcon#about to write, iclass 18, count 0 2006.231.08:25:19.66#ibcon#wrote, iclass 18, count 0 2006.231.08:25:19.66#ibcon#about to read 3, iclass 18, count 0 2006.231.08:25:19.68#ibcon#read 3, iclass 18, count 0 2006.231.08:25:19.68#ibcon#about to read 4, iclass 18, count 0 2006.231.08:25:19.68#ibcon#read 4, iclass 18, count 0 2006.231.08:25:19.68#ibcon#about to read 5, iclass 18, count 0 2006.231.08:25:19.68#ibcon#read 5, iclass 18, count 0 2006.231.08:25:19.68#ibcon#about to read 6, iclass 18, count 0 2006.231.08:25:19.68#ibcon#read 6, iclass 18, count 0 2006.231.08:25:19.68#ibcon#end of sib2, iclass 18, count 0 2006.231.08:25:19.68#ibcon#*mode == 0, iclass 18, count 0 2006.231.08:25:19.68#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.08:25:19.68#ibcon#[26=FRQ=06,772.99\r\n] 2006.231.08:25:19.68#ibcon#*before write, iclass 18, count 0 2006.231.08:25:19.68#ibcon#enter sib2, iclass 18, count 0 2006.231.08:25:19.68#ibcon#flushed, iclass 18, count 0 2006.231.08:25:19.68#ibcon#about to write, iclass 18, count 0 2006.231.08:25:19.68#ibcon#wrote, iclass 18, count 0 2006.231.08:25:19.68#ibcon#about to read 3, iclass 18, count 0 2006.231.08:25:19.72#ibcon#read 3, iclass 18, count 0 2006.231.08:25:19.72#ibcon#about to read 4, iclass 18, count 0 2006.231.08:25:19.72#ibcon#read 4, iclass 18, count 0 2006.231.08:25:19.72#ibcon#about to read 5, iclass 18, count 0 2006.231.08:25:19.72#ibcon#read 5, iclass 18, count 0 2006.231.08:25:19.72#ibcon#about to read 6, iclass 18, count 0 2006.231.08:25:19.72#ibcon#read 6, iclass 18, count 0 2006.231.08:25:19.72#ibcon#end of sib2, iclass 18, count 0 2006.231.08:25:19.72#ibcon#*after write, iclass 18, count 0 2006.231.08:25:19.72#ibcon#*before return 0, iclass 18, count 0 2006.231.08:25:19.72#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:25:19.72#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:25:19.72#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.08:25:19.72#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.08:25:19.72$vc4f8/va=6,6 2006.231.08:25:19.72#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.231.08:25:19.72#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.231.08:25:19.72#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:19.72#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:25:19.78#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:25:19.78#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:25:19.78#ibcon#enter wrdev, iclass 20, count 2 2006.231.08:25:19.78#ibcon#first serial, iclass 20, count 2 2006.231.08:25:19.78#ibcon#enter sib2, iclass 20, count 2 2006.231.08:25:19.78#ibcon#flushed, iclass 20, count 2 2006.231.08:25:19.78#ibcon#about to write, iclass 20, count 2 2006.231.08:25:19.78#ibcon#wrote, iclass 20, count 2 2006.231.08:25:19.78#ibcon#about to read 3, iclass 20, count 2 2006.231.08:25:19.80#ibcon#read 3, iclass 20, count 2 2006.231.08:25:19.80#ibcon#about to read 4, iclass 20, count 2 2006.231.08:25:19.80#ibcon#read 4, iclass 20, count 2 2006.231.08:25:19.80#ibcon#about to read 5, iclass 20, count 2 2006.231.08:25:19.80#ibcon#read 5, iclass 20, count 2 2006.231.08:25:19.80#ibcon#about to read 6, iclass 20, count 2 2006.231.08:25:19.80#ibcon#read 6, iclass 20, count 2 2006.231.08:25:19.80#ibcon#end of sib2, iclass 20, count 2 2006.231.08:25:19.80#ibcon#*mode == 0, iclass 20, count 2 2006.231.08:25:19.80#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.231.08:25:19.80#ibcon#[25=AT06-06\r\n] 2006.231.08:25:19.80#ibcon#*before write, iclass 20, count 2 2006.231.08:25:19.80#ibcon#enter sib2, iclass 20, count 2 2006.231.08:25:19.80#ibcon#flushed, iclass 20, count 2 2006.231.08:25:19.80#ibcon#about to write, iclass 20, count 2 2006.231.08:25:19.80#ibcon#wrote, iclass 20, count 2 2006.231.08:25:19.80#ibcon#about to read 3, iclass 20, count 2 2006.231.08:25:19.83#ibcon#read 3, iclass 20, count 2 2006.231.08:25:19.83#ibcon#about to read 4, iclass 20, count 2 2006.231.08:25:19.83#ibcon#read 4, iclass 20, count 2 2006.231.08:25:19.83#ibcon#about to read 5, iclass 20, count 2 2006.231.08:25:19.83#ibcon#read 5, iclass 20, count 2 2006.231.08:25:19.83#ibcon#about to read 6, iclass 20, count 2 2006.231.08:25:19.83#ibcon#read 6, iclass 20, count 2 2006.231.08:25:19.83#ibcon#end of sib2, iclass 20, count 2 2006.231.08:25:19.83#ibcon#*after write, iclass 20, count 2 2006.231.08:25:19.83#ibcon#*before return 0, iclass 20, count 2 2006.231.08:25:19.83#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:25:19.83#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.231.08:25:19.83#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.231.08:25:19.83#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:19.83#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:25:19.95#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:25:19.95#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:25:19.95#ibcon#enter wrdev, iclass 20, count 0 2006.231.08:25:19.95#ibcon#first serial, iclass 20, count 0 2006.231.08:25:19.95#ibcon#enter sib2, iclass 20, count 0 2006.231.08:25:19.95#ibcon#flushed, iclass 20, count 0 2006.231.08:25:19.95#ibcon#about to write, iclass 20, count 0 2006.231.08:25:19.95#ibcon#wrote, iclass 20, count 0 2006.231.08:25:19.95#ibcon#about to read 3, iclass 20, count 0 2006.231.08:25:19.97#ibcon#read 3, iclass 20, count 0 2006.231.08:25:19.97#ibcon#about to read 4, iclass 20, count 0 2006.231.08:25:19.97#ibcon#read 4, iclass 20, count 0 2006.231.08:25:19.97#ibcon#about to read 5, iclass 20, count 0 2006.231.08:25:19.97#ibcon#read 5, iclass 20, count 0 2006.231.08:25:19.97#ibcon#about to read 6, iclass 20, count 0 2006.231.08:25:19.97#ibcon#read 6, iclass 20, count 0 2006.231.08:25:19.97#ibcon#end of sib2, iclass 20, count 0 2006.231.08:25:19.97#ibcon#*mode == 0, iclass 20, count 0 2006.231.08:25:19.97#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.08:25:19.97#ibcon#[25=USB\r\n] 2006.231.08:25:19.97#ibcon#*before write, iclass 20, count 0 2006.231.08:25:19.97#ibcon#enter sib2, iclass 20, count 0 2006.231.08:25:19.97#ibcon#flushed, iclass 20, count 0 2006.231.08:25:19.97#ibcon#about to write, iclass 20, count 0 2006.231.08:25:19.97#ibcon#wrote, iclass 20, count 0 2006.231.08:25:19.97#ibcon#about to read 3, iclass 20, count 0 2006.231.08:25:20.00#ibcon#read 3, iclass 20, count 0 2006.231.08:25:20.00#ibcon#about to read 4, iclass 20, count 0 2006.231.08:25:20.00#ibcon#read 4, iclass 20, count 0 2006.231.08:25:20.00#ibcon#about to read 5, iclass 20, count 0 2006.231.08:25:20.00#ibcon#read 5, iclass 20, count 0 2006.231.08:25:20.00#ibcon#about to read 6, iclass 20, count 0 2006.231.08:25:20.00#ibcon#read 6, iclass 20, count 0 2006.231.08:25:20.00#ibcon#end of sib2, iclass 20, count 0 2006.231.08:25:20.00#ibcon#*after write, iclass 20, count 0 2006.231.08:25:20.00#ibcon#*before return 0, iclass 20, count 0 2006.231.08:25:20.00#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:25:20.00#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.231.08:25:20.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.08:25:20.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.08:25:20.00$vc4f8/valo=7,832.99 2006.231.08:25:20.00#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.231.08:25:20.00#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.231.08:25:20.00#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:20.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:25:20.00#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:25:20.00#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:25:20.00#ibcon#enter wrdev, iclass 22, count 0 2006.231.08:25:20.00#ibcon#first serial, iclass 22, count 0 2006.231.08:25:20.00#ibcon#enter sib2, iclass 22, count 0 2006.231.08:25:20.00#ibcon#flushed, iclass 22, count 0 2006.231.08:25:20.00#ibcon#about to write, iclass 22, count 0 2006.231.08:25:20.00#ibcon#wrote, iclass 22, count 0 2006.231.08:25:20.00#ibcon#about to read 3, iclass 22, count 0 2006.231.08:25:20.02#ibcon#read 3, iclass 22, count 0 2006.231.08:25:20.02#ibcon#about to read 4, iclass 22, count 0 2006.231.08:25:20.02#ibcon#read 4, iclass 22, count 0 2006.231.08:25:20.02#ibcon#about to read 5, iclass 22, count 0 2006.231.08:25:20.02#ibcon#read 5, iclass 22, count 0 2006.231.08:25:20.02#ibcon#about to read 6, iclass 22, count 0 2006.231.08:25:20.02#ibcon#read 6, iclass 22, count 0 2006.231.08:25:20.02#ibcon#end of sib2, iclass 22, count 0 2006.231.08:25:20.02#ibcon#*mode == 0, iclass 22, count 0 2006.231.08:25:20.02#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.231.08:25:20.02#ibcon#[26=FRQ=07,832.99\r\n] 2006.231.08:25:20.02#ibcon#*before write, iclass 22, count 0 2006.231.08:25:20.02#ibcon#enter sib2, iclass 22, count 0 2006.231.08:25:20.02#ibcon#flushed, iclass 22, count 0 2006.231.08:25:20.02#ibcon#about to write, iclass 22, count 0 2006.231.08:25:20.02#ibcon#wrote, iclass 22, count 0 2006.231.08:25:20.02#ibcon#about to read 3, iclass 22, count 0 2006.231.08:25:20.06#ibcon#read 3, iclass 22, count 0 2006.231.08:25:20.06#ibcon#about to read 4, iclass 22, count 0 2006.231.08:25:20.06#ibcon#read 4, iclass 22, count 0 2006.231.08:25:20.06#ibcon#about to read 5, iclass 22, count 0 2006.231.08:25:20.06#ibcon#read 5, iclass 22, count 0 2006.231.08:25:20.06#ibcon#about to read 6, iclass 22, count 0 2006.231.08:25:20.06#ibcon#read 6, iclass 22, count 0 2006.231.08:25:20.06#ibcon#end of sib2, iclass 22, count 0 2006.231.08:25:20.06#ibcon#*after write, iclass 22, count 0 2006.231.08:25:20.06#ibcon#*before return 0, iclass 22, count 0 2006.231.08:25:20.06#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:25:20.06#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.231.08:25:20.06#ibcon#about to clear, iclass 22 cls_cnt 0 2006.231.08:25:20.06#ibcon#cleared, iclass 22 cls_cnt 0 2006.231.08:25:20.06$vc4f8/va=7,6 2006.231.08:25:20.06#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.231.08:25:20.06#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.231.08:25:20.06#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:20.06#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:25:20.12#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:25:20.12#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:25:20.12#ibcon#enter wrdev, iclass 24, count 2 2006.231.08:25:20.12#ibcon#first serial, iclass 24, count 2 2006.231.08:25:20.12#ibcon#enter sib2, iclass 24, count 2 2006.231.08:25:20.12#ibcon#flushed, iclass 24, count 2 2006.231.08:25:20.12#ibcon#about to write, iclass 24, count 2 2006.231.08:25:20.12#ibcon#wrote, iclass 24, count 2 2006.231.08:25:20.12#ibcon#about to read 3, iclass 24, count 2 2006.231.08:25:20.14#ibcon#read 3, iclass 24, count 2 2006.231.08:25:20.14#ibcon#about to read 4, iclass 24, count 2 2006.231.08:25:20.14#ibcon#read 4, iclass 24, count 2 2006.231.08:25:20.14#ibcon#about to read 5, iclass 24, count 2 2006.231.08:25:20.14#ibcon#read 5, iclass 24, count 2 2006.231.08:25:20.14#ibcon#about to read 6, iclass 24, count 2 2006.231.08:25:20.14#ibcon#read 6, iclass 24, count 2 2006.231.08:25:20.14#ibcon#end of sib2, iclass 24, count 2 2006.231.08:25:20.14#ibcon#*mode == 0, iclass 24, count 2 2006.231.08:25:20.14#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.231.08:25:20.14#ibcon#[25=AT07-06\r\n] 2006.231.08:25:20.14#ibcon#*before write, iclass 24, count 2 2006.231.08:25:20.14#ibcon#enter sib2, iclass 24, count 2 2006.231.08:25:20.14#ibcon#flushed, iclass 24, count 2 2006.231.08:25:20.14#ibcon#about to write, iclass 24, count 2 2006.231.08:25:20.14#ibcon#wrote, iclass 24, count 2 2006.231.08:25:20.14#ibcon#about to read 3, iclass 24, count 2 2006.231.08:25:20.17#ibcon#read 3, iclass 24, count 2 2006.231.08:25:20.17#ibcon#about to read 4, iclass 24, count 2 2006.231.08:25:20.17#ibcon#read 4, iclass 24, count 2 2006.231.08:25:20.17#ibcon#about to read 5, iclass 24, count 2 2006.231.08:25:20.17#ibcon#read 5, iclass 24, count 2 2006.231.08:25:20.17#ibcon#about to read 6, iclass 24, count 2 2006.231.08:25:20.17#ibcon#read 6, iclass 24, count 2 2006.231.08:25:20.17#ibcon#end of sib2, iclass 24, count 2 2006.231.08:25:20.17#ibcon#*after write, iclass 24, count 2 2006.231.08:25:20.17#ibcon#*before return 0, iclass 24, count 2 2006.231.08:25:20.17#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:25:20.17#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.231.08:25:20.17#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.231.08:25:20.17#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:20.17#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:25:20.29#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:25:20.29#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:25:20.29#ibcon#enter wrdev, iclass 24, count 0 2006.231.08:25:20.29#ibcon#first serial, iclass 24, count 0 2006.231.08:25:20.29#ibcon#enter sib2, iclass 24, count 0 2006.231.08:25:20.29#ibcon#flushed, iclass 24, count 0 2006.231.08:25:20.29#ibcon#about to write, iclass 24, count 0 2006.231.08:25:20.29#ibcon#wrote, iclass 24, count 0 2006.231.08:25:20.29#ibcon#about to read 3, iclass 24, count 0 2006.231.08:25:20.31#ibcon#read 3, iclass 24, count 0 2006.231.08:25:20.31#ibcon#about to read 4, iclass 24, count 0 2006.231.08:25:20.31#ibcon#read 4, iclass 24, count 0 2006.231.08:25:20.31#ibcon#about to read 5, iclass 24, count 0 2006.231.08:25:20.31#ibcon#read 5, iclass 24, count 0 2006.231.08:25:20.31#ibcon#about to read 6, iclass 24, count 0 2006.231.08:25:20.31#ibcon#read 6, iclass 24, count 0 2006.231.08:25:20.31#ibcon#end of sib2, iclass 24, count 0 2006.231.08:25:20.31#ibcon#*mode == 0, iclass 24, count 0 2006.231.08:25:20.31#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.231.08:25:20.31#ibcon#[25=USB\r\n] 2006.231.08:25:20.31#ibcon#*before write, iclass 24, count 0 2006.231.08:25:20.31#ibcon#enter sib2, iclass 24, count 0 2006.231.08:25:20.31#ibcon#flushed, iclass 24, count 0 2006.231.08:25:20.31#ibcon#about to write, iclass 24, count 0 2006.231.08:25:20.31#ibcon#wrote, iclass 24, count 0 2006.231.08:25:20.31#ibcon#about to read 3, iclass 24, count 0 2006.231.08:25:20.34#ibcon#read 3, iclass 24, count 0 2006.231.08:25:20.34#ibcon#about to read 4, iclass 24, count 0 2006.231.08:25:20.34#ibcon#read 4, iclass 24, count 0 2006.231.08:25:20.34#ibcon#about to read 5, iclass 24, count 0 2006.231.08:25:20.34#ibcon#read 5, iclass 24, count 0 2006.231.08:25:20.34#ibcon#about to read 6, iclass 24, count 0 2006.231.08:25:20.34#ibcon#read 6, iclass 24, count 0 2006.231.08:25:20.34#ibcon#end of sib2, iclass 24, count 0 2006.231.08:25:20.34#ibcon#*after write, iclass 24, count 0 2006.231.08:25:20.34#ibcon#*before return 0, iclass 24, count 0 2006.231.08:25:20.34#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:25:20.34#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.231.08:25:20.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.231.08:25:20.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.231.08:25:20.34$vc4f8/valo=8,852.99 2006.231.08:25:20.34#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.231.08:25:20.34#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.231.08:25:20.34#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:20.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:25:20.34#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:25:20.34#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:25:20.34#ibcon#enter wrdev, iclass 26, count 0 2006.231.08:25:20.34#ibcon#first serial, iclass 26, count 0 2006.231.08:25:20.34#ibcon#enter sib2, iclass 26, count 0 2006.231.08:25:20.34#ibcon#flushed, iclass 26, count 0 2006.231.08:25:20.34#ibcon#about to write, iclass 26, count 0 2006.231.08:25:20.34#ibcon#wrote, iclass 26, count 0 2006.231.08:25:20.34#ibcon#about to read 3, iclass 26, count 0 2006.231.08:25:20.36#ibcon#read 3, iclass 26, count 0 2006.231.08:25:20.36#ibcon#about to read 4, iclass 26, count 0 2006.231.08:25:20.36#ibcon#read 4, iclass 26, count 0 2006.231.08:25:20.36#ibcon#about to read 5, iclass 26, count 0 2006.231.08:25:20.36#ibcon#read 5, iclass 26, count 0 2006.231.08:25:20.36#ibcon#about to read 6, iclass 26, count 0 2006.231.08:25:20.36#ibcon#read 6, iclass 26, count 0 2006.231.08:25:20.36#ibcon#end of sib2, iclass 26, count 0 2006.231.08:25:20.36#ibcon#*mode == 0, iclass 26, count 0 2006.231.08:25:20.36#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.231.08:25:20.36#ibcon#[26=FRQ=08,852.99\r\n] 2006.231.08:25:20.36#ibcon#*before write, iclass 26, count 0 2006.231.08:25:20.36#ibcon#enter sib2, iclass 26, count 0 2006.231.08:25:20.36#ibcon#flushed, iclass 26, count 0 2006.231.08:25:20.36#ibcon#about to write, iclass 26, count 0 2006.231.08:25:20.36#ibcon#wrote, iclass 26, count 0 2006.231.08:25:20.36#ibcon#about to read 3, iclass 26, count 0 2006.231.08:25:20.40#ibcon#read 3, iclass 26, count 0 2006.231.08:25:20.40#ibcon#about to read 4, iclass 26, count 0 2006.231.08:25:20.40#ibcon#read 4, iclass 26, count 0 2006.231.08:25:20.40#ibcon#about to read 5, iclass 26, count 0 2006.231.08:25:20.40#ibcon#read 5, iclass 26, count 0 2006.231.08:25:20.40#ibcon#about to read 6, iclass 26, count 0 2006.231.08:25:20.40#ibcon#read 6, iclass 26, count 0 2006.231.08:25:20.40#ibcon#end of sib2, iclass 26, count 0 2006.231.08:25:20.40#ibcon#*after write, iclass 26, count 0 2006.231.08:25:20.40#ibcon#*before return 0, iclass 26, count 0 2006.231.08:25:20.40#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:25:20.40#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.231.08:25:20.40#ibcon#about to clear, iclass 26 cls_cnt 0 2006.231.08:25:20.40#ibcon#cleared, iclass 26 cls_cnt 0 2006.231.08:25:20.40$vc4f8/va=8,6 2006.231.08:25:20.40#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.231.08:25:20.40#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.231.08:25:20.40#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:20.40#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:25:20.46#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:25:20.46#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:25:20.46#ibcon#enter wrdev, iclass 28, count 2 2006.231.08:25:20.46#ibcon#first serial, iclass 28, count 2 2006.231.08:25:20.46#ibcon#enter sib2, iclass 28, count 2 2006.231.08:25:20.46#ibcon#flushed, iclass 28, count 2 2006.231.08:25:20.46#ibcon#about to write, iclass 28, count 2 2006.231.08:25:20.46#ibcon#wrote, iclass 28, count 2 2006.231.08:25:20.46#ibcon#about to read 3, iclass 28, count 2 2006.231.08:25:20.48#ibcon#read 3, iclass 28, count 2 2006.231.08:25:20.48#ibcon#about to read 4, iclass 28, count 2 2006.231.08:25:20.48#ibcon#read 4, iclass 28, count 2 2006.231.08:25:20.48#ibcon#about to read 5, iclass 28, count 2 2006.231.08:25:20.48#ibcon#read 5, iclass 28, count 2 2006.231.08:25:20.48#ibcon#about to read 6, iclass 28, count 2 2006.231.08:25:20.48#ibcon#read 6, iclass 28, count 2 2006.231.08:25:20.48#ibcon#end of sib2, iclass 28, count 2 2006.231.08:25:20.48#ibcon#*mode == 0, iclass 28, count 2 2006.231.08:25:20.48#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.231.08:25:20.48#ibcon#[25=AT08-06\r\n] 2006.231.08:25:20.48#ibcon#*before write, iclass 28, count 2 2006.231.08:25:20.48#ibcon#enter sib2, iclass 28, count 2 2006.231.08:25:20.48#ibcon#flushed, iclass 28, count 2 2006.231.08:25:20.48#ibcon#about to write, iclass 28, count 2 2006.231.08:25:20.49#ibcon#wrote, iclass 28, count 2 2006.231.08:25:20.49#ibcon#about to read 3, iclass 28, count 2 2006.231.08:25:20.52#ibcon#read 3, iclass 28, count 2 2006.231.08:25:20.52#ibcon#about to read 4, iclass 28, count 2 2006.231.08:25:20.52#ibcon#read 4, iclass 28, count 2 2006.231.08:25:20.52#ibcon#about to read 5, iclass 28, count 2 2006.231.08:25:20.52#ibcon#read 5, iclass 28, count 2 2006.231.08:25:20.52#ibcon#about to read 6, iclass 28, count 2 2006.231.08:25:20.52#ibcon#read 6, iclass 28, count 2 2006.231.08:25:20.52#ibcon#end of sib2, iclass 28, count 2 2006.231.08:25:20.52#ibcon#*after write, iclass 28, count 2 2006.231.08:25:20.52#ibcon#*before return 0, iclass 28, count 2 2006.231.08:25:20.52#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:25:20.52#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.231.08:25:20.52#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.231.08:25:20.52#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:20.52#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:25:20.64#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:25:20.64#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:25:20.64#ibcon#enter wrdev, iclass 28, count 0 2006.231.08:25:20.64#ibcon#first serial, iclass 28, count 0 2006.231.08:25:20.64#ibcon#enter sib2, iclass 28, count 0 2006.231.08:25:20.64#ibcon#flushed, iclass 28, count 0 2006.231.08:25:20.64#ibcon#about to write, iclass 28, count 0 2006.231.08:25:20.64#ibcon#wrote, iclass 28, count 0 2006.231.08:25:20.64#ibcon#about to read 3, iclass 28, count 0 2006.231.08:25:20.66#ibcon#read 3, iclass 28, count 0 2006.231.08:25:20.66#ibcon#about to read 4, iclass 28, count 0 2006.231.08:25:20.66#ibcon#read 4, iclass 28, count 0 2006.231.08:25:20.66#ibcon#about to read 5, iclass 28, count 0 2006.231.08:25:20.66#ibcon#read 5, iclass 28, count 0 2006.231.08:25:20.66#ibcon#about to read 6, iclass 28, count 0 2006.231.08:25:20.66#ibcon#read 6, iclass 28, count 0 2006.231.08:25:20.66#ibcon#end of sib2, iclass 28, count 0 2006.231.08:25:20.66#ibcon#*mode == 0, iclass 28, count 0 2006.231.08:25:20.66#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.231.08:25:20.66#ibcon#[25=USB\r\n] 2006.231.08:25:20.66#ibcon#*before write, iclass 28, count 0 2006.231.08:25:20.66#ibcon#enter sib2, iclass 28, count 0 2006.231.08:25:20.66#ibcon#flushed, iclass 28, count 0 2006.231.08:25:20.66#ibcon#about to write, iclass 28, count 0 2006.231.08:25:20.66#ibcon#wrote, iclass 28, count 0 2006.231.08:25:20.66#ibcon#about to read 3, iclass 28, count 0 2006.231.08:25:20.69#ibcon#read 3, iclass 28, count 0 2006.231.08:25:20.69#ibcon#about to read 4, iclass 28, count 0 2006.231.08:25:20.69#ibcon#read 4, iclass 28, count 0 2006.231.08:25:20.69#ibcon#about to read 5, iclass 28, count 0 2006.231.08:25:20.69#ibcon#read 5, iclass 28, count 0 2006.231.08:25:20.69#ibcon#about to read 6, iclass 28, count 0 2006.231.08:25:20.69#ibcon#read 6, iclass 28, count 0 2006.231.08:25:20.69#ibcon#end of sib2, iclass 28, count 0 2006.231.08:25:20.69#ibcon#*after write, iclass 28, count 0 2006.231.08:25:20.69#ibcon#*before return 0, iclass 28, count 0 2006.231.08:25:20.69#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:25:20.69#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.231.08:25:20.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.231.08:25:20.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.231.08:25:20.69$vc4f8/vblo=1,632.99 2006.231.08:25:20.69#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.231.08:25:20.69#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.231.08:25:20.69#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:20.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:25:20.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:25:20.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:25:20.69#ibcon#enter wrdev, iclass 30, count 0 2006.231.08:25:20.69#ibcon#first serial, iclass 30, count 0 2006.231.08:25:20.69#ibcon#enter sib2, iclass 30, count 0 2006.231.08:25:20.69#ibcon#flushed, iclass 30, count 0 2006.231.08:25:20.69#ibcon#about to write, iclass 30, count 0 2006.231.08:25:20.69#ibcon#wrote, iclass 30, count 0 2006.231.08:25:20.69#ibcon#about to read 3, iclass 30, count 0 2006.231.08:25:20.71#ibcon#read 3, iclass 30, count 0 2006.231.08:25:20.71#ibcon#about to read 4, iclass 30, count 0 2006.231.08:25:20.71#ibcon#read 4, iclass 30, count 0 2006.231.08:25:20.71#ibcon#about to read 5, iclass 30, count 0 2006.231.08:25:20.71#ibcon#read 5, iclass 30, count 0 2006.231.08:25:20.71#ibcon#about to read 6, iclass 30, count 0 2006.231.08:25:20.71#ibcon#read 6, iclass 30, count 0 2006.231.08:25:20.71#ibcon#end of sib2, iclass 30, count 0 2006.231.08:25:20.71#ibcon#*mode == 0, iclass 30, count 0 2006.231.08:25:20.71#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.231.08:25:20.71#ibcon#[28=FRQ=01,632.99\r\n] 2006.231.08:25:20.71#ibcon#*before write, iclass 30, count 0 2006.231.08:25:20.71#ibcon#enter sib2, iclass 30, count 0 2006.231.08:25:20.71#ibcon#flushed, iclass 30, count 0 2006.231.08:25:20.71#ibcon#about to write, iclass 30, count 0 2006.231.08:25:20.71#ibcon#wrote, iclass 30, count 0 2006.231.08:25:20.71#ibcon#about to read 3, iclass 30, count 0 2006.231.08:25:20.75#ibcon#read 3, iclass 30, count 0 2006.231.08:25:20.75#ibcon#about to read 4, iclass 30, count 0 2006.231.08:25:20.75#ibcon#read 4, iclass 30, count 0 2006.231.08:25:20.75#ibcon#about to read 5, iclass 30, count 0 2006.231.08:25:20.75#ibcon#read 5, iclass 30, count 0 2006.231.08:25:20.75#ibcon#about to read 6, iclass 30, count 0 2006.231.08:25:20.75#ibcon#read 6, iclass 30, count 0 2006.231.08:25:20.75#ibcon#end of sib2, iclass 30, count 0 2006.231.08:25:20.75#ibcon#*after write, iclass 30, count 0 2006.231.08:25:20.75#ibcon#*before return 0, iclass 30, count 0 2006.231.08:25:20.75#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:25:20.75#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.231.08:25:20.75#ibcon#about to clear, iclass 30 cls_cnt 0 2006.231.08:25:20.75#ibcon#cleared, iclass 30 cls_cnt 0 2006.231.08:25:20.75$vc4f8/vb=1,4 2006.231.08:25:20.75#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.231.08:25:20.75#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.231.08:25:20.75#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:20.75#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:25:20.75#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:25:20.75#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:25:20.75#ibcon#enter wrdev, iclass 32, count 2 2006.231.08:25:20.75#ibcon#first serial, iclass 32, count 2 2006.231.08:25:20.75#ibcon#enter sib2, iclass 32, count 2 2006.231.08:25:20.75#ibcon#flushed, iclass 32, count 2 2006.231.08:25:20.75#ibcon#about to write, iclass 32, count 2 2006.231.08:25:20.75#ibcon#wrote, iclass 32, count 2 2006.231.08:25:20.75#ibcon#about to read 3, iclass 32, count 2 2006.231.08:25:20.77#ibcon#read 3, iclass 32, count 2 2006.231.08:25:20.77#ibcon#about to read 4, iclass 32, count 2 2006.231.08:25:20.77#ibcon#read 4, iclass 32, count 2 2006.231.08:25:20.77#ibcon#about to read 5, iclass 32, count 2 2006.231.08:25:20.77#ibcon#read 5, iclass 32, count 2 2006.231.08:25:20.77#ibcon#about to read 6, iclass 32, count 2 2006.231.08:25:20.77#ibcon#read 6, iclass 32, count 2 2006.231.08:25:20.77#ibcon#end of sib2, iclass 32, count 2 2006.231.08:25:20.77#ibcon#*mode == 0, iclass 32, count 2 2006.231.08:25:20.77#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.231.08:25:20.77#ibcon#[27=AT01-04\r\n] 2006.231.08:25:20.77#ibcon#*before write, iclass 32, count 2 2006.231.08:25:20.77#ibcon#enter sib2, iclass 32, count 2 2006.231.08:25:20.77#ibcon#flushed, iclass 32, count 2 2006.231.08:25:20.77#ibcon#about to write, iclass 32, count 2 2006.231.08:25:20.77#ibcon#wrote, iclass 32, count 2 2006.231.08:25:20.77#ibcon#about to read 3, iclass 32, count 2 2006.231.08:25:20.80#ibcon#read 3, iclass 32, count 2 2006.231.08:25:20.80#ibcon#about to read 4, iclass 32, count 2 2006.231.08:25:20.80#ibcon#read 4, iclass 32, count 2 2006.231.08:25:20.80#ibcon#about to read 5, iclass 32, count 2 2006.231.08:25:20.80#ibcon#read 5, iclass 32, count 2 2006.231.08:25:20.80#ibcon#about to read 6, iclass 32, count 2 2006.231.08:25:20.80#ibcon#read 6, iclass 32, count 2 2006.231.08:25:20.80#ibcon#end of sib2, iclass 32, count 2 2006.231.08:25:20.80#ibcon#*after write, iclass 32, count 2 2006.231.08:25:20.80#ibcon#*before return 0, iclass 32, count 2 2006.231.08:25:20.80#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:25:20.80#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.231.08:25:20.80#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.231.08:25:20.80#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:20.80#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:25:20.92#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:25:20.92#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:25:20.92#ibcon#enter wrdev, iclass 32, count 0 2006.231.08:25:20.92#ibcon#first serial, iclass 32, count 0 2006.231.08:25:20.92#ibcon#enter sib2, iclass 32, count 0 2006.231.08:25:20.92#ibcon#flushed, iclass 32, count 0 2006.231.08:25:20.92#ibcon#about to write, iclass 32, count 0 2006.231.08:25:20.92#ibcon#wrote, iclass 32, count 0 2006.231.08:25:20.92#ibcon#about to read 3, iclass 32, count 0 2006.231.08:25:20.94#ibcon#read 3, iclass 32, count 0 2006.231.08:25:20.94#ibcon#about to read 4, iclass 32, count 0 2006.231.08:25:20.94#ibcon#read 4, iclass 32, count 0 2006.231.08:25:20.94#ibcon#about to read 5, iclass 32, count 0 2006.231.08:25:20.94#ibcon#read 5, iclass 32, count 0 2006.231.08:25:20.94#ibcon#about to read 6, iclass 32, count 0 2006.231.08:25:20.94#ibcon#read 6, iclass 32, count 0 2006.231.08:25:20.94#ibcon#end of sib2, iclass 32, count 0 2006.231.08:25:20.94#ibcon#*mode == 0, iclass 32, count 0 2006.231.08:25:20.94#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.231.08:25:20.94#ibcon#[27=USB\r\n] 2006.231.08:25:20.94#ibcon#*before write, iclass 32, count 0 2006.231.08:25:20.94#ibcon#enter sib2, iclass 32, count 0 2006.231.08:25:20.94#ibcon#flushed, iclass 32, count 0 2006.231.08:25:20.94#ibcon#about to write, iclass 32, count 0 2006.231.08:25:20.94#ibcon#wrote, iclass 32, count 0 2006.231.08:25:20.94#ibcon#about to read 3, iclass 32, count 0 2006.231.08:25:20.97#ibcon#read 3, iclass 32, count 0 2006.231.08:25:20.97#ibcon#about to read 4, iclass 32, count 0 2006.231.08:25:20.97#ibcon#read 4, iclass 32, count 0 2006.231.08:25:20.97#ibcon#about to read 5, iclass 32, count 0 2006.231.08:25:20.97#ibcon#read 5, iclass 32, count 0 2006.231.08:25:20.97#ibcon#about to read 6, iclass 32, count 0 2006.231.08:25:20.97#ibcon#read 6, iclass 32, count 0 2006.231.08:25:20.97#ibcon#end of sib2, iclass 32, count 0 2006.231.08:25:20.97#ibcon#*after write, iclass 32, count 0 2006.231.08:25:20.97#ibcon#*before return 0, iclass 32, count 0 2006.231.08:25:20.97#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:25:20.97#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.231.08:25:20.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.231.08:25:20.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.231.08:25:20.97$vc4f8/vblo=2,640.99 2006.231.08:25:20.97#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.231.08:25:20.97#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.231.08:25:20.97#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:20.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:25:20.97#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:25:20.97#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:25:20.97#ibcon#enter wrdev, iclass 34, count 0 2006.231.08:25:20.97#ibcon#first serial, iclass 34, count 0 2006.231.08:25:20.97#ibcon#enter sib2, iclass 34, count 0 2006.231.08:25:20.97#ibcon#flushed, iclass 34, count 0 2006.231.08:25:20.97#ibcon#about to write, iclass 34, count 0 2006.231.08:25:20.97#ibcon#wrote, iclass 34, count 0 2006.231.08:25:20.97#ibcon#about to read 3, iclass 34, count 0 2006.231.08:25:20.99#ibcon#read 3, iclass 34, count 0 2006.231.08:25:20.99#ibcon#about to read 4, iclass 34, count 0 2006.231.08:25:20.99#ibcon#read 4, iclass 34, count 0 2006.231.08:25:20.99#ibcon#about to read 5, iclass 34, count 0 2006.231.08:25:20.99#ibcon#read 5, iclass 34, count 0 2006.231.08:25:20.99#ibcon#about to read 6, iclass 34, count 0 2006.231.08:25:20.99#ibcon#read 6, iclass 34, count 0 2006.231.08:25:20.99#ibcon#end of sib2, iclass 34, count 0 2006.231.08:25:20.99#ibcon#*mode == 0, iclass 34, count 0 2006.231.08:25:20.99#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.231.08:25:20.99#ibcon#[28=FRQ=02,640.99\r\n] 2006.231.08:25:20.99#ibcon#*before write, iclass 34, count 0 2006.231.08:25:20.99#ibcon#enter sib2, iclass 34, count 0 2006.231.08:25:20.99#ibcon#flushed, iclass 34, count 0 2006.231.08:25:20.99#ibcon#about to write, iclass 34, count 0 2006.231.08:25:20.99#ibcon#wrote, iclass 34, count 0 2006.231.08:25:20.99#ibcon#about to read 3, iclass 34, count 0 2006.231.08:25:21.03#ibcon#read 3, iclass 34, count 0 2006.231.08:25:21.03#ibcon#about to read 4, iclass 34, count 0 2006.231.08:25:21.03#ibcon#read 4, iclass 34, count 0 2006.231.08:25:21.03#ibcon#about to read 5, iclass 34, count 0 2006.231.08:25:21.03#ibcon#read 5, iclass 34, count 0 2006.231.08:25:21.03#ibcon#about to read 6, iclass 34, count 0 2006.231.08:25:21.03#ibcon#read 6, iclass 34, count 0 2006.231.08:25:21.03#ibcon#end of sib2, iclass 34, count 0 2006.231.08:25:21.03#ibcon#*after write, iclass 34, count 0 2006.231.08:25:21.03#ibcon#*before return 0, iclass 34, count 0 2006.231.08:25:21.03#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:25:21.03#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.231.08:25:21.03#ibcon#about to clear, iclass 34 cls_cnt 0 2006.231.08:25:21.03#ibcon#cleared, iclass 34 cls_cnt 0 2006.231.08:25:21.03$vc4f8/vb=2,4 2006.231.08:25:21.03#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.231.08:25:21.03#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.231.08:25:21.03#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:21.03#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:25:21.09#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:25:21.09#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:25:21.09#ibcon#enter wrdev, iclass 36, count 2 2006.231.08:25:21.09#ibcon#first serial, iclass 36, count 2 2006.231.08:25:21.09#ibcon#enter sib2, iclass 36, count 2 2006.231.08:25:21.09#ibcon#flushed, iclass 36, count 2 2006.231.08:25:21.09#ibcon#about to write, iclass 36, count 2 2006.231.08:25:21.09#ibcon#wrote, iclass 36, count 2 2006.231.08:25:21.09#ibcon#about to read 3, iclass 36, count 2 2006.231.08:25:21.11#ibcon#read 3, iclass 36, count 2 2006.231.08:25:21.11#ibcon#about to read 4, iclass 36, count 2 2006.231.08:25:21.11#ibcon#read 4, iclass 36, count 2 2006.231.08:25:21.11#ibcon#about to read 5, iclass 36, count 2 2006.231.08:25:21.11#ibcon#read 5, iclass 36, count 2 2006.231.08:25:21.11#ibcon#about to read 6, iclass 36, count 2 2006.231.08:25:21.11#ibcon#read 6, iclass 36, count 2 2006.231.08:25:21.11#ibcon#end of sib2, iclass 36, count 2 2006.231.08:25:21.11#ibcon#*mode == 0, iclass 36, count 2 2006.231.08:25:21.11#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.231.08:25:21.11#ibcon#[27=AT02-04\r\n] 2006.231.08:25:21.11#ibcon#*before write, iclass 36, count 2 2006.231.08:25:21.11#ibcon#enter sib2, iclass 36, count 2 2006.231.08:25:21.11#ibcon#flushed, iclass 36, count 2 2006.231.08:25:21.11#ibcon#about to write, iclass 36, count 2 2006.231.08:25:21.11#ibcon#wrote, iclass 36, count 2 2006.231.08:25:21.11#ibcon#about to read 3, iclass 36, count 2 2006.231.08:25:21.14#ibcon#read 3, iclass 36, count 2 2006.231.08:25:21.14#ibcon#about to read 4, iclass 36, count 2 2006.231.08:25:21.14#ibcon#read 4, iclass 36, count 2 2006.231.08:25:21.14#ibcon#about to read 5, iclass 36, count 2 2006.231.08:25:21.14#ibcon#read 5, iclass 36, count 2 2006.231.08:25:21.14#ibcon#about to read 6, iclass 36, count 2 2006.231.08:25:21.14#ibcon#read 6, iclass 36, count 2 2006.231.08:25:21.14#ibcon#end of sib2, iclass 36, count 2 2006.231.08:25:21.14#ibcon#*after write, iclass 36, count 2 2006.231.08:25:21.14#ibcon#*before return 0, iclass 36, count 2 2006.231.08:25:21.14#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:25:21.14#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.231.08:25:21.14#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.231.08:25:21.14#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:21.14#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:25:21.26#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:25:21.26#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:25:21.26#ibcon#enter wrdev, iclass 36, count 0 2006.231.08:25:21.26#ibcon#first serial, iclass 36, count 0 2006.231.08:25:21.26#ibcon#enter sib2, iclass 36, count 0 2006.231.08:25:21.26#ibcon#flushed, iclass 36, count 0 2006.231.08:25:21.26#ibcon#about to write, iclass 36, count 0 2006.231.08:25:21.26#ibcon#wrote, iclass 36, count 0 2006.231.08:25:21.26#ibcon#about to read 3, iclass 36, count 0 2006.231.08:25:21.28#ibcon#read 3, iclass 36, count 0 2006.231.08:25:21.28#ibcon#about to read 4, iclass 36, count 0 2006.231.08:25:21.28#ibcon#read 4, iclass 36, count 0 2006.231.08:25:21.28#ibcon#about to read 5, iclass 36, count 0 2006.231.08:25:21.28#ibcon#read 5, iclass 36, count 0 2006.231.08:25:21.28#ibcon#about to read 6, iclass 36, count 0 2006.231.08:25:21.28#ibcon#read 6, iclass 36, count 0 2006.231.08:25:21.28#ibcon#end of sib2, iclass 36, count 0 2006.231.08:25:21.28#ibcon#*mode == 0, iclass 36, count 0 2006.231.08:25:21.28#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.231.08:25:21.28#ibcon#[27=USB\r\n] 2006.231.08:25:21.28#ibcon#*before write, iclass 36, count 0 2006.231.08:25:21.28#ibcon#enter sib2, iclass 36, count 0 2006.231.08:25:21.28#ibcon#flushed, iclass 36, count 0 2006.231.08:25:21.28#ibcon#about to write, iclass 36, count 0 2006.231.08:25:21.28#ibcon#wrote, iclass 36, count 0 2006.231.08:25:21.28#ibcon#about to read 3, iclass 36, count 0 2006.231.08:25:21.31#ibcon#read 3, iclass 36, count 0 2006.231.08:25:21.31#ibcon#about to read 4, iclass 36, count 0 2006.231.08:25:21.31#ibcon#read 4, iclass 36, count 0 2006.231.08:25:21.31#ibcon#about to read 5, iclass 36, count 0 2006.231.08:25:21.31#ibcon#read 5, iclass 36, count 0 2006.231.08:25:21.31#ibcon#about to read 6, iclass 36, count 0 2006.231.08:25:21.31#ibcon#read 6, iclass 36, count 0 2006.231.08:25:21.31#ibcon#end of sib2, iclass 36, count 0 2006.231.08:25:21.31#ibcon#*after write, iclass 36, count 0 2006.231.08:25:21.31#ibcon#*before return 0, iclass 36, count 0 2006.231.08:25:21.31#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:25:21.31#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.231.08:25:21.31#ibcon#about to clear, iclass 36 cls_cnt 0 2006.231.08:25:21.31#ibcon#cleared, iclass 36 cls_cnt 0 2006.231.08:25:21.31$vc4f8/vblo=3,656.99 2006.231.08:25:21.31#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.231.08:25:21.31#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.231.08:25:21.31#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:21.31#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:25:21.31#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:25:21.31#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:25:21.31#ibcon#enter wrdev, iclass 38, count 0 2006.231.08:25:21.31#ibcon#first serial, iclass 38, count 0 2006.231.08:25:21.31#ibcon#enter sib2, iclass 38, count 0 2006.231.08:25:21.31#ibcon#flushed, iclass 38, count 0 2006.231.08:25:21.31#ibcon#about to write, iclass 38, count 0 2006.231.08:25:21.31#ibcon#wrote, iclass 38, count 0 2006.231.08:25:21.31#ibcon#about to read 3, iclass 38, count 0 2006.231.08:25:21.33#ibcon#read 3, iclass 38, count 0 2006.231.08:25:21.33#ibcon#about to read 4, iclass 38, count 0 2006.231.08:25:21.33#ibcon#read 4, iclass 38, count 0 2006.231.08:25:21.33#ibcon#about to read 5, iclass 38, count 0 2006.231.08:25:21.33#ibcon#read 5, iclass 38, count 0 2006.231.08:25:21.33#ibcon#about to read 6, iclass 38, count 0 2006.231.08:25:21.33#ibcon#read 6, iclass 38, count 0 2006.231.08:25:21.33#ibcon#end of sib2, iclass 38, count 0 2006.231.08:25:21.33#ibcon#*mode == 0, iclass 38, count 0 2006.231.08:25:21.33#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.231.08:25:21.33#ibcon#[28=FRQ=03,656.99\r\n] 2006.231.08:25:21.33#ibcon#*before write, iclass 38, count 0 2006.231.08:25:21.33#ibcon#enter sib2, iclass 38, count 0 2006.231.08:25:21.33#ibcon#flushed, iclass 38, count 0 2006.231.08:25:21.33#ibcon#about to write, iclass 38, count 0 2006.231.08:25:21.33#ibcon#wrote, iclass 38, count 0 2006.231.08:25:21.33#ibcon#about to read 3, iclass 38, count 0 2006.231.08:25:21.37#ibcon#read 3, iclass 38, count 0 2006.231.08:25:21.37#ibcon#about to read 4, iclass 38, count 0 2006.231.08:25:21.37#ibcon#read 4, iclass 38, count 0 2006.231.08:25:21.37#ibcon#about to read 5, iclass 38, count 0 2006.231.08:25:21.37#ibcon#read 5, iclass 38, count 0 2006.231.08:25:21.37#ibcon#about to read 6, iclass 38, count 0 2006.231.08:25:21.37#ibcon#read 6, iclass 38, count 0 2006.231.08:25:21.37#ibcon#end of sib2, iclass 38, count 0 2006.231.08:25:21.37#ibcon#*after write, iclass 38, count 0 2006.231.08:25:21.37#ibcon#*before return 0, iclass 38, count 0 2006.231.08:25:21.37#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:25:21.37#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.231.08:25:21.37#ibcon#about to clear, iclass 38 cls_cnt 0 2006.231.08:25:21.37#ibcon#cleared, iclass 38 cls_cnt 0 2006.231.08:25:21.37$vc4f8/vb=3,4 2006.231.08:25:21.37#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.231.08:25:21.37#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.231.08:25:21.37#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:21.37#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:25:21.43#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:25:21.43#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:25:21.43#ibcon#enter wrdev, iclass 40, count 2 2006.231.08:25:21.43#ibcon#first serial, iclass 40, count 2 2006.231.08:25:21.43#ibcon#enter sib2, iclass 40, count 2 2006.231.08:25:21.43#ibcon#flushed, iclass 40, count 2 2006.231.08:25:21.43#ibcon#about to write, iclass 40, count 2 2006.231.08:25:21.43#ibcon#wrote, iclass 40, count 2 2006.231.08:25:21.43#ibcon#about to read 3, iclass 40, count 2 2006.231.08:25:21.45#ibcon#read 3, iclass 40, count 2 2006.231.08:25:21.45#ibcon#about to read 4, iclass 40, count 2 2006.231.08:25:21.45#ibcon#read 4, iclass 40, count 2 2006.231.08:25:21.45#ibcon#about to read 5, iclass 40, count 2 2006.231.08:25:21.45#ibcon#read 5, iclass 40, count 2 2006.231.08:25:21.45#ibcon#about to read 6, iclass 40, count 2 2006.231.08:25:21.45#ibcon#read 6, iclass 40, count 2 2006.231.08:25:21.45#ibcon#end of sib2, iclass 40, count 2 2006.231.08:25:21.45#ibcon#*mode == 0, iclass 40, count 2 2006.231.08:25:21.45#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.231.08:25:21.45#ibcon#[27=AT03-04\r\n] 2006.231.08:25:21.45#ibcon#*before write, iclass 40, count 2 2006.231.08:25:21.45#ibcon#enter sib2, iclass 40, count 2 2006.231.08:25:21.45#ibcon#flushed, iclass 40, count 2 2006.231.08:25:21.45#ibcon#about to write, iclass 40, count 2 2006.231.08:25:21.45#ibcon#wrote, iclass 40, count 2 2006.231.08:25:21.45#ibcon#about to read 3, iclass 40, count 2 2006.231.08:25:21.48#ibcon#read 3, iclass 40, count 2 2006.231.08:25:21.48#ibcon#about to read 4, iclass 40, count 2 2006.231.08:25:21.48#ibcon#read 4, iclass 40, count 2 2006.231.08:25:21.48#ibcon#about to read 5, iclass 40, count 2 2006.231.08:25:21.48#ibcon#read 5, iclass 40, count 2 2006.231.08:25:21.48#ibcon#about to read 6, iclass 40, count 2 2006.231.08:25:21.48#ibcon#read 6, iclass 40, count 2 2006.231.08:25:21.48#ibcon#end of sib2, iclass 40, count 2 2006.231.08:25:21.48#ibcon#*after write, iclass 40, count 2 2006.231.08:25:21.48#ibcon#*before return 0, iclass 40, count 2 2006.231.08:25:21.48#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:25:21.48#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.231.08:25:21.48#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.231.08:25:21.48#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:21.48#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:25:21.60#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:25:21.60#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:25:21.60#ibcon#enter wrdev, iclass 40, count 0 2006.231.08:25:21.60#ibcon#first serial, iclass 40, count 0 2006.231.08:25:21.60#ibcon#enter sib2, iclass 40, count 0 2006.231.08:25:21.60#ibcon#flushed, iclass 40, count 0 2006.231.08:25:21.60#ibcon#about to write, iclass 40, count 0 2006.231.08:25:21.60#ibcon#wrote, iclass 40, count 0 2006.231.08:25:21.60#ibcon#about to read 3, iclass 40, count 0 2006.231.08:25:21.62#ibcon#read 3, iclass 40, count 0 2006.231.08:25:21.62#ibcon#about to read 4, iclass 40, count 0 2006.231.08:25:21.62#ibcon#read 4, iclass 40, count 0 2006.231.08:25:21.62#ibcon#about to read 5, iclass 40, count 0 2006.231.08:25:21.62#ibcon#read 5, iclass 40, count 0 2006.231.08:25:21.62#ibcon#about to read 6, iclass 40, count 0 2006.231.08:25:21.62#ibcon#read 6, iclass 40, count 0 2006.231.08:25:21.62#ibcon#end of sib2, iclass 40, count 0 2006.231.08:25:21.62#ibcon#*mode == 0, iclass 40, count 0 2006.231.08:25:21.62#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.231.08:25:21.62#ibcon#[27=USB\r\n] 2006.231.08:25:21.62#ibcon#*before write, iclass 40, count 0 2006.231.08:25:21.62#ibcon#enter sib2, iclass 40, count 0 2006.231.08:25:21.62#ibcon#flushed, iclass 40, count 0 2006.231.08:25:21.62#ibcon#about to write, iclass 40, count 0 2006.231.08:25:21.62#ibcon#wrote, iclass 40, count 0 2006.231.08:25:21.62#ibcon#about to read 3, iclass 40, count 0 2006.231.08:25:21.65#ibcon#read 3, iclass 40, count 0 2006.231.08:25:21.65#ibcon#about to read 4, iclass 40, count 0 2006.231.08:25:21.65#ibcon#read 4, iclass 40, count 0 2006.231.08:25:21.65#ibcon#about to read 5, iclass 40, count 0 2006.231.08:25:21.65#ibcon#read 5, iclass 40, count 0 2006.231.08:25:21.65#ibcon#about to read 6, iclass 40, count 0 2006.231.08:25:21.65#ibcon#read 6, iclass 40, count 0 2006.231.08:25:21.65#ibcon#end of sib2, iclass 40, count 0 2006.231.08:25:21.65#ibcon#*after write, iclass 40, count 0 2006.231.08:25:21.65#ibcon#*before return 0, iclass 40, count 0 2006.231.08:25:21.65#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:25:21.65#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.231.08:25:21.65#ibcon#about to clear, iclass 40 cls_cnt 0 2006.231.08:25:21.65#ibcon#cleared, iclass 40 cls_cnt 0 2006.231.08:25:21.65$vc4f8/vblo=4,712.99 2006.231.08:25:21.65#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.231.08:25:21.65#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.231.08:25:21.65#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:21.65#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:25:21.65#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:25:21.65#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:25:21.65#ibcon#enter wrdev, iclass 4, count 0 2006.231.08:25:21.65#ibcon#first serial, iclass 4, count 0 2006.231.08:25:21.65#ibcon#enter sib2, iclass 4, count 0 2006.231.08:25:21.65#ibcon#flushed, iclass 4, count 0 2006.231.08:25:21.65#ibcon#about to write, iclass 4, count 0 2006.231.08:25:21.65#ibcon#wrote, iclass 4, count 0 2006.231.08:25:21.65#ibcon#about to read 3, iclass 4, count 0 2006.231.08:25:21.67#ibcon#read 3, iclass 4, count 0 2006.231.08:25:21.67#ibcon#about to read 4, iclass 4, count 0 2006.231.08:25:21.67#ibcon#read 4, iclass 4, count 0 2006.231.08:25:21.67#ibcon#about to read 5, iclass 4, count 0 2006.231.08:25:21.67#ibcon#read 5, iclass 4, count 0 2006.231.08:25:21.67#ibcon#about to read 6, iclass 4, count 0 2006.231.08:25:21.67#ibcon#read 6, iclass 4, count 0 2006.231.08:25:21.67#ibcon#end of sib2, iclass 4, count 0 2006.231.08:25:21.67#ibcon#*mode == 0, iclass 4, count 0 2006.231.08:25:21.67#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.231.08:25:21.67#ibcon#[28=FRQ=04,712.99\r\n] 2006.231.08:25:21.67#ibcon#*before write, iclass 4, count 0 2006.231.08:25:21.67#ibcon#enter sib2, iclass 4, count 0 2006.231.08:25:21.67#ibcon#flushed, iclass 4, count 0 2006.231.08:25:21.67#ibcon#about to write, iclass 4, count 0 2006.231.08:25:21.67#ibcon#wrote, iclass 4, count 0 2006.231.08:25:21.67#ibcon#about to read 3, iclass 4, count 0 2006.231.08:25:21.71#ibcon#read 3, iclass 4, count 0 2006.231.08:25:21.71#ibcon#about to read 4, iclass 4, count 0 2006.231.08:25:21.71#ibcon#read 4, iclass 4, count 0 2006.231.08:25:21.71#ibcon#about to read 5, iclass 4, count 0 2006.231.08:25:21.71#ibcon#read 5, iclass 4, count 0 2006.231.08:25:21.71#ibcon#about to read 6, iclass 4, count 0 2006.231.08:25:21.71#ibcon#read 6, iclass 4, count 0 2006.231.08:25:21.71#ibcon#end of sib2, iclass 4, count 0 2006.231.08:25:21.71#ibcon#*after write, iclass 4, count 0 2006.231.08:25:21.71#ibcon#*before return 0, iclass 4, count 0 2006.231.08:25:21.71#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:25:21.71#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.231.08:25:21.71#ibcon#about to clear, iclass 4 cls_cnt 0 2006.231.08:25:21.71#ibcon#cleared, iclass 4 cls_cnt 0 2006.231.08:25:21.71$vc4f8/vb=4,4 2006.231.08:25:21.71#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.231.08:25:21.71#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.231.08:25:21.71#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:21.71#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:25:21.77#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:25:21.77#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:25:21.77#ibcon#enter wrdev, iclass 6, count 2 2006.231.08:25:21.77#ibcon#first serial, iclass 6, count 2 2006.231.08:25:21.77#ibcon#enter sib2, iclass 6, count 2 2006.231.08:25:21.77#ibcon#flushed, iclass 6, count 2 2006.231.08:25:21.77#ibcon#about to write, iclass 6, count 2 2006.231.08:25:21.77#ibcon#wrote, iclass 6, count 2 2006.231.08:25:21.77#ibcon#about to read 3, iclass 6, count 2 2006.231.08:25:21.79#ibcon#read 3, iclass 6, count 2 2006.231.08:25:21.79#ibcon#about to read 4, iclass 6, count 2 2006.231.08:25:21.79#ibcon#read 4, iclass 6, count 2 2006.231.08:25:21.79#ibcon#about to read 5, iclass 6, count 2 2006.231.08:25:21.79#ibcon#read 5, iclass 6, count 2 2006.231.08:25:21.79#ibcon#about to read 6, iclass 6, count 2 2006.231.08:25:21.79#ibcon#read 6, iclass 6, count 2 2006.231.08:25:21.79#ibcon#end of sib2, iclass 6, count 2 2006.231.08:25:21.79#ibcon#*mode == 0, iclass 6, count 2 2006.231.08:25:21.79#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.231.08:25:21.79#ibcon#[27=AT04-04\r\n] 2006.231.08:25:21.79#ibcon#*before write, iclass 6, count 2 2006.231.08:25:21.79#ibcon#enter sib2, iclass 6, count 2 2006.231.08:25:21.79#ibcon#flushed, iclass 6, count 2 2006.231.08:25:21.79#ibcon#about to write, iclass 6, count 2 2006.231.08:25:21.79#ibcon#wrote, iclass 6, count 2 2006.231.08:25:21.79#ibcon#about to read 3, iclass 6, count 2 2006.231.08:25:21.82#ibcon#read 3, iclass 6, count 2 2006.231.08:25:21.82#ibcon#about to read 4, iclass 6, count 2 2006.231.08:25:21.82#ibcon#read 4, iclass 6, count 2 2006.231.08:25:21.82#ibcon#about to read 5, iclass 6, count 2 2006.231.08:25:21.82#ibcon#read 5, iclass 6, count 2 2006.231.08:25:21.82#ibcon#about to read 6, iclass 6, count 2 2006.231.08:25:21.82#ibcon#read 6, iclass 6, count 2 2006.231.08:25:21.82#ibcon#end of sib2, iclass 6, count 2 2006.231.08:25:21.82#ibcon#*after write, iclass 6, count 2 2006.231.08:25:21.82#ibcon#*before return 0, iclass 6, count 2 2006.231.08:25:21.82#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:25:21.82#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.231.08:25:21.82#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.231.08:25:21.82#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:21.82#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:25:21.94#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:25:21.94#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:25:21.94#ibcon#enter wrdev, iclass 6, count 0 2006.231.08:25:21.94#ibcon#first serial, iclass 6, count 0 2006.231.08:25:21.94#ibcon#enter sib2, iclass 6, count 0 2006.231.08:25:21.94#ibcon#flushed, iclass 6, count 0 2006.231.08:25:21.94#ibcon#about to write, iclass 6, count 0 2006.231.08:25:21.94#ibcon#wrote, iclass 6, count 0 2006.231.08:25:21.94#ibcon#about to read 3, iclass 6, count 0 2006.231.08:25:21.96#ibcon#read 3, iclass 6, count 0 2006.231.08:25:21.96#ibcon#about to read 4, iclass 6, count 0 2006.231.08:25:21.96#ibcon#read 4, iclass 6, count 0 2006.231.08:25:21.96#ibcon#about to read 5, iclass 6, count 0 2006.231.08:25:21.96#ibcon#read 5, iclass 6, count 0 2006.231.08:25:21.96#ibcon#about to read 6, iclass 6, count 0 2006.231.08:25:21.96#ibcon#read 6, iclass 6, count 0 2006.231.08:25:21.96#ibcon#end of sib2, iclass 6, count 0 2006.231.08:25:21.96#ibcon#*mode == 0, iclass 6, count 0 2006.231.08:25:21.96#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.231.08:25:21.96#ibcon#[27=USB\r\n] 2006.231.08:25:21.96#ibcon#*before write, iclass 6, count 0 2006.231.08:25:21.96#ibcon#enter sib2, iclass 6, count 0 2006.231.08:25:21.96#ibcon#flushed, iclass 6, count 0 2006.231.08:25:21.96#ibcon#about to write, iclass 6, count 0 2006.231.08:25:21.96#ibcon#wrote, iclass 6, count 0 2006.231.08:25:21.96#ibcon#about to read 3, iclass 6, count 0 2006.231.08:25:21.99#ibcon#read 3, iclass 6, count 0 2006.231.08:25:21.99#ibcon#about to read 4, iclass 6, count 0 2006.231.08:25:21.99#ibcon#read 4, iclass 6, count 0 2006.231.08:25:21.99#ibcon#about to read 5, iclass 6, count 0 2006.231.08:25:21.99#ibcon#read 5, iclass 6, count 0 2006.231.08:25:21.99#ibcon#about to read 6, iclass 6, count 0 2006.231.08:25:21.99#ibcon#read 6, iclass 6, count 0 2006.231.08:25:21.99#ibcon#end of sib2, iclass 6, count 0 2006.231.08:25:21.99#ibcon#*after write, iclass 6, count 0 2006.231.08:25:21.99#ibcon#*before return 0, iclass 6, count 0 2006.231.08:25:21.99#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:25:21.99#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.231.08:25:21.99#ibcon#about to clear, iclass 6 cls_cnt 0 2006.231.08:25:21.99#ibcon#cleared, iclass 6 cls_cnt 0 2006.231.08:25:21.99$vc4f8/vblo=5,744.99 2006.231.08:25:21.99#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.231.08:25:21.99#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.231.08:25:21.99#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:21.99#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:25:21.99#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:25:21.99#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:25:21.99#ibcon#enter wrdev, iclass 10, count 0 2006.231.08:25:21.99#ibcon#first serial, iclass 10, count 0 2006.231.08:25:21.99#ibcon#enter sib2, iclass 10, count 0 2006.231.08:25:21.99#ibcon#flushed, iclass 10, count 0 2006.231.08:25:21.99#ibcon#about to write, iclass 10, count 0 2006.231.08:25:21.99#ibcon#wrote, iclass 10, count 0 2006.231.08:25:21.99#ibcon#about to read 3, iclass 10, count 0 2006.231.08:25:22.01#ibcon#read 3, iclass 10, count 0 2006.231.08:25:22.01#ibcon#about to read 4, iclass 10, count 0 2006.231.08:25:22.01#ibcon#read 4, iclass 10, count 0 2006.231.08:25:22.01#ibcon#about to read 5, iclass 10, count 0 2006.231.08:25:22.01#ibcon#read 5, iclass 10, count 0 2006.231.08:25:22.01#ibcon#about to read 6, iclass 10, count 0 2006.231.08:25:22.01#ibcon#read 6, iclass 10, count 0 2006.231.08:25:22.01#ibcon#end of sib2, iclass 10, count 0 2006.231.08:25:22.01#ibcon#*mode == 0, iclass 10, count 0 2006.231.08:25:22.01#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.231.08:25:22.01#ibcon#[28=FRQ=05,744.99\r\n] 2006.231.08:25:22.01#ibcon#*before write, iclass 10, count 0 2006.231.08:25:22.01#ibcon#enter sib2, iclass 10, count 0 2006.231.08:25:22.01#ibcon#flushed, iclass 10, count 0 2006.231.08:25:22.01#ibcon#about to write, iclass 10, count 0 2006.231.08:25:22.01#ibcon#wrote, iclass 10, count 0 2006.231.08:25:22.01#ibcon#about to read 3, iclass 10, count 0 2006.231.08:25:22.05#ibcon#read 3, iclass 10, count 0 2006.231.08:25:22.05#ibcon#about to read 4, iclass 10, count 0 2006.231.08:25:22.05#ibcon#read 4, iclass 10, count 0 2006.231.08:25:22.05#ibcon#about to read 5, iclass 10, count 0 2006.231.08:25:22.05#ibcon#read 5, iclass 10, count 0 2006.231.08:25:22.05#ibcon#about to read 6, iclass 10, count 0 2006.231.08:25:22.05#ibcon#read 6, iclass 10, count 0 2006.231.08:25:22.05#ibcon#end of sib2, iclass 10, count 0 2006.231.08:25:22.05#ibcon#*after write, iclass 10, count 0 2006.231.08:25:22.05#ibcon#*before return 0, iclass 10, count 0 2006.231.08:25:22.05#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:25:22.05#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.231.08:25:22.05#ibcon#about to clear, iclass 10 cls_cnt 0 2006.231.08:25:22.05#ibcon#cleared, iclass 10 cls_cnt 0 2006.231.08:25:22.05$vc4f8/vb=5,3 2006.231.08:25:22.05#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.231.08:25:22.05#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.231.08:25:22.05#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:22.05#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:25:22.11#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:25:22.11#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:25:22.11#ibcon#enter wrdev, iclass 12, count 2 2006.231.08:25:22.11#ibcon#first serial, iclass 12, count 2 2006.231.08:25:22.11#ibcon#enter sib2, iclass 12, count 2 2006.231.08:25:22.11#ibcon#flushed, iclass 12, count 2 2006.231.08:25:22.11#ibcon#about to write, iclass 12, count 2 2006.231.08:25:22.11#ibcon#wrote, iclass 12, count 2 2006.231.08:25:22.11#ibcon#about to read 3, iclass 12, count 2 2006.231.08:25:22.13#ibcon#read 3, iclass 12, count 2 2006.231.08:25:22.13#ibcon#about to read 4, iclass 12, count 2 2006.231.08:25:22.13#ibcon#read 4, iclass 12, count 2 2006.231.08:25:22.13#ibcon#about to read 5, iclass 12, count 2 2006.231.08:25:22.13#ibcon#read 5, iclass 12, count 2 2006.231.08:25:22.13#ibcon#about to read 6, iclass 12, count 2 2006.231.08:25:22.13#ibcon#read 6, iclass 12, count 2 2006.231.08:25:22.13#ibcon#end of sib2, iclass 12, count 2 2006.231.08:25:22.13#ibcon#*mode == 0, iclass 12, count 2 2006.231.08:25:22.13#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.231.08:25:22.13#ibcon#[27=AT05-03\r\n] 2006.231.08:25:22.13#ibcon#*before write, iclass 12, count 2 2006.231.08:25:22.13#ibcon#enter sib2, iclass 12, count 2 2006.231.08:25:22.13#ibcon#flushed, iclass 12, count 2 2006.231.08:25:22.13#ibcon#about to write, iclass 12, count 2 2006.231.08:25:22.13#ibcon#wrote, iclass 12, count 2 2006.231.08:25:22.13#ibcon#about to read 3, iclass 12, count 2 2006.231.08:25:22.17#ibcon#read 3, iclass 12, count 2 2006.231.08:25:22.17#ibcon#about to read 4, iclass 12, count 2 2006.231.08:25:22.17#ibcon#read 4, iclass 12, count 2 2006.231.08:25:22.17#ibcon#about to read 5, iclass 12, count 2 2006.231.08:25:22.17#ibcon#read 5, iclass 12, count 2 2006.231.08:25:22.17#ibcon#about to read 6, iclass 12, count 2 2006.231.08:25:22.17#ibcon#read 6, iclass 12, count 2 2006.231.08:25:22.17#ibcon#end of sib2, iclass 12, count 2 2006.231.08:25:22.17#ibcon#*after write, iclass 12, count 2 2006.231.08:25:22.17#ibcon#*before return 0, iclass 12, count 2 2006.231.08:25:22.17#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:25:22.17#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.231.08:25:22.17#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.231.08:25:22.17#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:22.17#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:25:22.29#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:25:22.29#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:25:22.29#ibcon#enter wrdev, iclass 12, count 0 2006.231.08:25:22.29#ibcon#first serial, iclass 12, count 0 2006.231.08:25:22.29#ibcon#enter sib2, iclass 12, count 0 2006.231.08:25:22.29#ibcon#flushed, iclass 12, count 0 2006.231.08:25:22.29#ibcon#about to write, iclass 12, count 0 2006.231.08:25:22.29#ibcon#wrote, iclass 12, count 0 2006.231.08:25:22.29#ibcon#about to read 3, iclass 12, count 0 2006.231.08:25:22.31#ibcon#read 3, iclass 12, count 0 2006.231.08:25:22.31#ibcon#about to read 4, iclass 12, count 0 2006.231.08:25:22.31#ibcon#read 4, iclass 12, count 0 2006.231.08:25:22.31#ibcon#about to read 5, iclass 12, count 0 2006.231.08:25:22.31#ibcon#read 5, iclass 12, count 0 2006.231.08:25:22.31#ibcon#about to read 6, iclass 12, count 0 2006.231.08:25:22.31#ibcon#read 6, iclass 12, count 0 2006.231.08:25:22.31#ibcon#end of sib2, iclass 12, count 0 2006.231.08:25:22.31#ibcon#*mode == 0, iclass 12, count 0 2006.231.08:25:22.31#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.231.08:25:22.31#ibcon#[27=USB\r\n] 2006.231.08:25:22.31#ibcon#*before write, iclass 12, count 0 2006.231.08:25:22.31#ibcon#enter sib2, iclass 12, count 0 2006.231.08:25:22.31#ibcon#flushed, iclass 12, count 0 2006.231.08:25:22.31#ibcon#about to write, iclass 12, count 0 2006.231.08:25:22.31#ibcon#wrote, iclass 12, count 0 2006.231.08:25:22.31#ibcon#about to read 3, iclass 12, count 0 2006.231.08:25:22.34#ibcon#read 3, iclass 12, count 0 2006.231.08:25:22.34#ibcon#about to read 4, iclass 12, count 0 2006.231.08:25:22.34#ibcon#read 4, iclass 12, count 0 2006.231.08:25:22.34#ibcon#about to read 5, iclass 12, count 0 2006.231.08:25:22.34#ibcon#read 5, iclass 12, count 0 2006.231.08:25:22.34#ibcon#about to read 6, iclass 12, count 0 2006.231.08:25:22.34#ibcon#read 6, iclass 12, count 0 2006.231.08:25:22.34#ibcon#end of sib2, iclass 12, count 0 2006.231.08:25:22.34#ibcon#*after write, iclass 12, count 0 2006.231.08:25:22.34#ibcon#*before return 0, iclass 12, count 0 2006.231.08:25:22.34#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:25:22.34#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.231.08:25:22.34#ibcon#about to clear, iclass 12 cls_cnt 0 2006.231.08:25:22.34#ibcon#cleared, iclass 12 cls_cnt 0 2006.231.08:25:22.34$vc4f8/vblo=6,752.99 2006.231.08:25:22.34#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.231.08:25:22.34#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.231.08:25:22.34#ibcon#ireg 17 cls_cnt 0 2006.231.08:25:22.34#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:25:22.34#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:25:22.34#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:25:22.34#ibcon#enter wrdev, iclass 14, count 0 2006.231.08:25:22.34#ibcon#first serial, iclass 14, count 0 2006.231.08:25:22.34#ibcon#enter sib2, iclass 14, count 0 2006.231.08:25:22.34#ibcon#flushed, iclass 14, count 0 2006.231.08:25:22.34#ibcon#about to write, iclass 14, count 0 2006.231.08:25:22.34#ibcon#wrote, iclass 14, count 0 2006.231.08:25:22.34#ibcon#about to read 3, iclass 14, count 0 2006.231.08:25:22.36#ibcon#read 3, iclass 14, count 0 2006.231.08:25:22.36#ibcon#about to read 4, iclass 14, count 0 2006.231.08:25:22.36#ibcon#read 4, iclass 14, count 0 2006.231.08:25:22.36#ibcon#about to read 5, iclass 14, count 0 2006.231.08:25:22.36#ibcon#read 5, iclass 14, count 0 2006.231.08:25:22.36#ibcon#about to read 6, iclass 14, count 0 2006.231.08:25:22.36#ibcon#read 6, iclass 14, count 0 2006.231.08:25:22.36#ibcon#end of sib2, iclass 14, count 0 2006.231.08:25:22.36#ibcon#*mode == 0, iclass 14, count 0 2006.231.08:25:22.36#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.231.08:25:22.36#ibcon#[28=FRQ=06,752.99\r\n] 2006.231.08:25:22.36#ibcon#*before write, iclass 14, count 0 2006.231.08:25:22.36#ibcon#enter sib2, iclass 14, count 0 2006.231.08:25:22.36#ibcon#flushed, iclass 14, count 0 2006.231.08:25:22.36#ibcon#about to write, iclass 14, count 0 2006.231.08:25:22.36#ibcon#wrote, iclass 14, count 0 2006.231.08:25:22.36#ibcon#about to read 3, iclass 14, count 0 2006.231.08:25:22.40#ibcon#read 3, iclass 14, count 0 2006.231.08:25:22.40#ibcon#about to read 4, iclass 14, count 0 2006.231.08:25:22.40#ibcon#read 4, iclass 14, count 0 2006.231.08:25:22.40#ibcon#about to read 5, iclass 14, count 0 2006.231.08:25:22.40#ibcon#read 5, iclass 14, count 0 2006.231.08:25:22.40#ibcon#about to read 6, iclass 14, count 0 2006.231.08:25:22.40#ibcon#read 6, iclass 14, count 0 2006.231.08:25:22.40#ibcon#end of sib2, iclass 14, count 0 2006.231.08:25:22.40#ibcon#*after write, iclass 14, count 0 2006.231.08:25:22.40#ibcon#*before return 0, iclass 14, count 0 2006.231.08:25:22.40#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:25:22.40#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.231.08:25:22.40#ibcon#about to clear, iclass 14 cls_cnt 0 2006.231.08:25:22.40#ibcon#cleared, iclass 14 cls_cnt 0 2006.231.08:25:22.40$vc4f8/vb=6,4 2006.231.08:25:22.40#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.231.08:25:22.40#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.231.08:25:22.40#ibcon#ireg 11 cls_cnt 2 2006.231.08:25:22.40#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:25:22.46#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:25:22.46#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:25:22.46#ibcon#enter wrdev, iclass 16, count 2 2006.231.08:25:22.46#ibcon#first serial, iclass 16, count 2 2006.231.08:25:22.46#ibcon#enter sib2, iclass 16, count 2 2006.231.08:25:22.46#ibcon#flushed, iclass 16, count 2 2006.231.08:25:22.46#ibcon#about to write, iclass 16, count 2 2006.231.08:25:22.46#ibcon#wrote, iclass 16, count 2 2006.231.08:25:22.46#ibcon#about to read 3, iclass 16, count 2 2006.231.08:25:22.48#ibcon#read 3, iclass 16, count 2 2006.231.08:25:22.48#ibcon#about to read 4, iclass 16, count 2 2006.231.08:25:22.48#ibcon#read 4, iclass 16, count 2 2006.231.08:25:22.48#ibcon#about to read 5, iclass 16, count 2 2006.231.08:25:22.48#ibcon#read 5, iclass 16, count 2 2006.231.08:25:22.48#ibcon#about to read 6, iclass 16, count 2 2006.231.08:25:22.48#ibcon#read 6, iclass 16, count 2 2006.231.08:25:22.48#ibcon#end of sib2, iclass 16, count 2 2006.231.08:25:22.48#ibcon#*mode == 0, iclass 16, count 2 2006.231.08:25:22.48#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.231.08:25:22.48#ibcon#[27=AT06-04\r\n] 2006.231.08:25:22.48#ibcon#*before write, iclass 16, count 2 2006.231.08:25:22.48#ibcon#enter sib2, iclass 16, count 2 2006.231.08:25:22.48#ibcon#flushed, iclass 16, count 2 2006.231.08:25:22.48#ibcon#about to write, iclass 16, count 2 2006.231.08:25:22.48#ibcon#wrote, iclass 16, count 2 2006.231.08:25:22.48#ibcon#about to read 3, iclass 16, count 2 2006.231.08:25:22.51#ibcon#read 3, iclass 16, count 2 2006.231.08:25:22.51#ibcon#about to read 4, iclass 16, count 2 2006.231.08:25:22.51#ibcon#read 4, iclass 16, count 2 2006.231.08:25:22.51#ibcon#about to read 5, iclass 16, count 2 2006.231.08:25:22.51#ibcon#read 5, iclass 16, count 2 2006.231.08:25:22.51#ibcon#about to read 6, iclass 16, count 2 2006.231.08:25:22.51#ibcon#read 6, iclass 16, count 2 2006.231.08:25:22.51#ibcon#end of sib2, iclass 16, count 2 2006.231.08:25:22.51#ibcon#*after write, iclass 16, count 2 2006.231.08:25:22.51#ibcon#*before return 0, iclass 16, count 2 2006.231.08:25:22.51#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:25:22.51#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.231.08:25:22.51#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.231.08:25:22.51#ibcon#ireg 7 cls_cnt 0 2006.231.08:25:22.51#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:25:22.63#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:25:22.63#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:25:22.63#ibcon#enter wrdev, iclass 16, count 0 2006.231.08:25:22.63#ibcon#first serial, iclass 16, count 0 2006.231.08:25:22.63#ibcon#enter sib2, iclass 16, count 0 2006.231.08:25:22.63#ibcon#flushed, iclass 16, count 0 2006.231.08:25:22.63#ibcon#about to write, iclass 16, count 0 2006.231.08:25:22.63#ibcon#wrote, iclass 16, count 0 2006.231.08:25:22.63#ibcon#about to read 3, iclass 16, count 0 2006.231.08:25:22.65#ibcon#read 3, iclass 16, count 0 2006.231.08:25:22.65#ibcon#about to read 4, iclass 16, count 0 2006.231.08:25:22.65#ibcon#read 4, iclass 16, count 0 2006.231.08:25:22.65#ibcon#about to read 5, iclass 16, count 0 2006.231.08:25:22.65#ibcon#read 5, iclass 16, count 0 2006.231.08:25:22.65#ibcon#about to read 6, iclass 16, count 0 2006.231.08:25:22.65#ibcon#read 6, iclass 16, count 0 2006.231.08:25:22.65#ibcon#end of sib2, iclass 16, count 0 2006.231.08:25:22.65#ibcon#*mode == 0, iclass 16, count 0 2006.231.08:25:22.65#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.231.08:25:22.65#ibcon#[27=USB\r\n] 2006.231.08:25:22.65#ibcon#*before write, iclass 16, count 0 2006.231.08:25:22.65#ibcon#enter sib2, iclass 16, count 0 2006.231.08:25:22.65#ibcon#flushed, iclass 16, count 0 2006.231.08:25:22.65#ibcon#about to write, iclass 16, count 0 2006.231.08:25:22.65#ibcon#wrote, iclass 16, count 0 2006.231.08:25:22.65#ibcon#about to read 3, iclass 16, count 0 2006.231.08:25:22.68#ibcon#read 3, iclass 16, count 0 2006.231.08:25:22.68#ibcon#about to read 4, iclass 16, count 0 2006.231.08:25:22.68#ibcon#read 4, iclass 16, count 0 2006.231.08:25:22.68#ibcon#about to read 5, iclass 16, count 0 2006.231.08:25:22.68#ibcon#read 5, iclass 16, count 0 2006.231.08:25:22.68#ibcon#about to read 6, iclass 16, count 0 2006.231.08:25:22.68#ibcon#read 6, iclass 16, count 0 2006.231.08:25:22.68#ibcon#end of sib2, iclass 16, count 0 2006.231.08:25:22.68#ibcon#*after write, iclass 16, count 0 2006.231.08:25:22.68#ibcon#*before return 0, iclass 16, count 0 2006.231.08:25:22.68#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:25:22.68#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.231.08:25:22.68#ibcon#about to clear, iclass 16 cls_cnt 0 2006.231.08:25:22.68#ibcon#cleared, iclass 16 cls_cnt 0 2006.231.08:25:22.68$vc4f8/vabw=wide 2006.231.08:25:22.68#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.231.08:25:22.68#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.231.08:25:22.68#ibcon#ireg 8 cls_cnt 0 2006.231.08:25:22.68#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:25:22.68#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:25:22.68#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:25:22.68#ibcon#enter wrdev, iclass 18, count 0 2006.231.08:25:22.68#ibcon#first serial, iclass 18, count 0 2006.231.08:25:22.68#ibcon#enter sib2, iclass 18, count 0 2006.231.08:25:22.68#ibcon#flushed, iclass 18, count 0 2006.231.08:25:22.68#ibcon#about to write, iclass 18, count 0 2006.231.08:25:22.68#ibcon#wrote, iclass 18, count 0 2006.231.08:25:22.68#ibcon#about to read 3, iclass 18, count 0 2006.231.08:25:22.70#ibcon#read 3, iclass 18, count 0 2006.231.08:25:22.70#ibcon#about to read 4, iclass 18, count 0 2006.231.08:25:22.70#ibcon#read 4, iclass 18, count 0 2006.231.08:25:22.70#ibcon#about to read 5, iclass 18, count 0 2006.231.08:25:22.70#ibcon#read 5, iclass 18, count 0 2006.231.08:25:22.70#ibcon#about to read 6, iclass 18, count 0 2006.231.08:25:22.70#ibcon#read 6, iclass 18, count 0 2006.231.08:25:22.70#ibcon#end of sib2, iclass 18, count 0 2006.231.08:25:22.70#ibcon#*mode == 0, iclass 18, count 0 2006.231.08:25:22.70#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.231.08:25:22.70#ibcon#[25=BW32\r\n] 2006.231.08:25:22.70#ibcon#*before write, iclass 18, count 0 2006.231.08:25:22.70#ibcon#enter sib2, iclass 18, count 0 2006.231.08:25:22.70#ibcon#flushed, iclass 18, count 0 2006.231.08:25:22.70#ibcon#about to write, iclass 18, count 0 2006.231.08:25:22.70#ibcon#wrote, iclass 18, count 0 2006.231.08:25:22.70#ibcon#about to read 3, iclass 18, count 0 2006.231.08:25:22.73#ibcon#read 3, iclass 18, count 0 2006.231.08:25:22.73#ibcon#about to read 4, iclass 18, count 0 2006.231.08:25:22.73#ibcon#read 4, iclass 18, count 0 2006.231.08:25:22.73#ibcon#about to read 5, iclass 18, count 0 2006.231.08:25:22.73#ibcon#read 5, iclass 18, count 0 2006.231.08:25:22.73#ibcon#about to read 6, iclass 18, count 0 2006.231.08:25:22.73#ibcon#read 6, iclass 18, count 0 2006.231.08:25:22.73#ibcon#end of sib2, iclass 18, count 0 2006.231.08:25:22.73#ibcon#*after write, iclass 18, count 0 2006.231.08:25:22.73#ibcon#*before return 0, iclass 18, count 0 2006.231.08:25:22.73#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:25:22.73#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.231.08:25:22.73#ibcon#about to clear, iclass 18 cls_cnt 0 2006.231.08:25:22.73#ibcon#cleared, iclass 18 cls_cnt 0 2006.231.08:25:22.73$vc4f8/vbbw=wide 2006.231.08:25:22.73#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.231.08:25:22.73#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.231.08:25:22.73#ibcon#ireg 8 cls_cnt 0 2006.231.08:25:22.73#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:25:22.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:25:22.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:25:22.80#ibcon#enter wrdev, iclass 20, count 0 2006.231.08:25:22.80#ibcon#first serial, iclass 20, count 0 2006.231.08:25:22.80#ibcon#enter sib2, iclass 20, count 0 2006.231.08:25:22.80#ibcon#flushed, iclass 20, count 0 2006.231.08:25:22.80#ibcon#about to write, iclass 20, count 0 2006.231.08:25:22.80#ibcon#wrote, iclass 20, count 0 2006.231.08:25:22.80#ibcon#about to read 3, iclass 20, count 0 2006.231.08:25:22.82#ibcon#read 3, iclass 20, count 0 2006.231.08:25:22.82#ibcon#about to read 4, iclass 20, count 0 2006.231.08:25:22.82#ibcon#read 4, iclass 20, count 0 2006.231.08:25:22.82#ibcon#about to read 5, iclass 20, count 0 2006.231.08:25:22.82#ibcon#read 5, iclass 20, count 0 2006.231.08:25:22.82#ibcon#about to read 6, iclass 20, count 0 2006.231.08:25:22.82#ibcon#read 6, iclass 20, count 0 2006.231.08:25:22.82#ibcon#end of sib2, iclass 20, count 0 2006.231.08:25:22.82#ibcon#*mode == 0, iclass 20, count 0 2006.231.08:25:22.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.231.08:25:22.82#ibcon#[27=BW32\r\n] 2006.231.08:25:22.82#ibcon#*before write, iclass 20, count 0 2006.231.08:25:22.82#ibcon#enter sib2, iclass 20, count 0 2006.231.08:25:22.82#ibcon#flushed, iclass 20, count 0 2006.231.08:25:22.82#ibcon#about to write, iclass 20, count 0 2006.231.08:25:22.82#ibcon#wrote, iclass 20, count 0 2006.231.08:25:22.82#ibcon#about to read 3, iclass 20, count 0 2006.231.08:25:22.85#ibcon#read 3, iclass 20, count 0 2006.231.08:25:22.85#ibcon#about to read 4, iclass 20, count 0 2006.231.08:25:22.85#ibcon#read 4, iclass 20, count 0 2006.231.08:25:22.85#ibcon#about to read 5, iclass 20, count 0 2006.231.08:25:22.85#ibcon#read 5, iclass 20, count 0 2006.231.08:25:22.85#ibcon#about to read 6, iclass 20, count 0 2006.231.08:25:22.85#ibcon#read 6, iclass 20, count 0 2006.231.08:25:22.85#ibcon#end of sib2, iclass 20, count 0 2006.231.08:25:22.85#ibcon#*after write, iclass 20, count 0 2006.231.08:25:22.85#ibcon#*before return 0, iclass 20, count 0 2006.231.08:25:22.85#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:25:22.85#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.231.08:25:22.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.231.08:25:22.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.231.08:25:22.85$4f8m12a/ifd4f 2006.231.08:25:22.85$ifd4f/lo= 2006.231.08:25:22.85$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.231.08:25:22.85$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.231.08:25:22.85$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.231.08:25:22.85$ifd4f/patch= 2006.231.08:25:22.85$ifd4f/patch=lo1,a1,a2,a3,a4 2006.231.08:25:22.85$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.231.08:25:22.85$ifd4f/patch=lo3,a5,a6,a7,a8 2006.231.08:25:22.85$4f8m12a/"form=m,16.000,1:2 2006.231.08:25:22.85$4f8m12a/"tpicd 2006.231.08:25:22.85$4f8m12a/echo=off 2006.231.08:25:22.85$4f8m12a/xlog=off 2006.231.08:25:22.85:!2006.231.08:25:50 2006.231.08:25:34.13#trakl#Source acquired 2006.231.08:25:35.13#flagr#flagr/antenna,acquired 2006.231.08:25:50.00:preob 2006.231.08:25:51.13/onsource/TRACKING 2006.231.08:25:51.13:!2006.231.08:26:00 2006.231.08:26:00.00:data_valid=on 2006.231.08:26:00.00:midob 2006.231.08:26:00.13/onsource/TRACKING 2006.231.08:26:00.13/wx/30.19,1004.6,84 2006.231.08:26:00.34/cable/+6.3730E-03 2006.231.08:26:01.43/va/01,08,usb,yes,30,31 2006.231.08:26:01.43/va/02,07,usb,yes,30,31 2006.231.08:26:01.43/va/03,08,usb,yes,22,22 2006.231.08:26:01.43/va/04,07,usb,yes,31,34 2006.231.08:26:01.43/va/05,07,usb,yes,34,36 2006.231.08:26:01.43/va/06,06,usb,yes,33,33 2006.231.08:26:01.43/va/07,06,usb,yes,34,34 2006.231.08:26:01.43/va/08,06,usb,yes,36,35 2006.231.08:26:01.66/valo/01,532.99,yes,locked 2006.231.08:26:01.66/valo/02,572.99,yes,locked 2006.231.08:26:01.66/valo/03,672.99,yes,locked 2006.231.08:26:01.66/valo/04,832.99,yes,locked 2006.231.08:26:01.66/valo/05,652.99,yes,locked 2006.231.08:26:01.66/valo/06,772.99,yes,locked 2006.231.08:26:01.66/valo/07,832.99,yes,locked 2006.231.08:26:01.66/valo/08,852.99,yes,locked 2006.231.08:26:02.75/vb/01,04,usb,yes,31,29 2006.231.08:26:02.75/vb/02,04,usb,yes,32,34 2006.231.08:26:02.75/vb/03,04,usb,yes,29,33 2006.231.08:26:02.75/vb/04,04,usb,yes,30,30 2006.231.08:26:02.75/vb/05,03,usb,yes,35,40 2006.231.08:26:02.75/vb/06,04,usb,yes,29,32 2006.231.08:26:02.75/vb/07,04,usb,yes,31,31 2006.231.08:26:02.75/vb/08,04,usb,yes,29,32 2006.231.08:26:02.99/vblo/01,632.99,yes,locked 2006.231.08:26:02.99/vblo/02,640.99,yes,locked 2006.231.08:26:02.99/vblo/03,656.99,yes,locked 2006.231.08:26:02.99/vblo/04,712.99,yes,locked 2006.231.08:26:02.99/vblo/05,744.99,yes,locked 2006.231.08:26:02.99/vblo/06,752.99,yes,locked 2006.231.08:26:02.99/vblo/07,734.99,yes,locked 2006.231.08:26:02.99/vblo/08,744.99,yes,locked 2006.231.08:26:03.14/vabw/8 2006.231.08:26:03.29/vbbw/8 2006.231.08:26:03.40/xfe/off,on,12.2 2006.231.08:26:03.77/ifatt/23,28,28,28 2006.231.08:26:04.07/fmout-gps/S +4.47E-07 2006.231.08:26:04.11:!2006.231.08:27:00 2006.231.08:27:00.00:data_valid=off 2006.231.08:27:00.00:postob 2006.231.08:27:00.18/cable/+6.3719E-03 2006.231.08:27:00.18/wx/30.18,1004.6,84 2006.231.08:27:01.08/fmout-gps/S +4.48E-07 2006.231.08:27:01.08:checkk5last 2006.231.08:27:01.09&checkk5last/chk_obsdata=1 2006.231.08:27:01.09&checkk5last/chk_obsdata=2 2006.231.08:27:01.09&checkk5last/chk_obsdata=3 2006.231.08:27:01.10&checkk5last/chk_obsdata=4 2006.231.08:27:01.10&checkk5last/k5log=1 2006.231.08:27:01.10&checkk5last/k5log=2 2006.231.08:27:01.11&checkk5last/k5log=3 2006.231.08:27:01.11&checkk5last/k5log=4 2006.231.08:27:01.11&checkk5last/obsinfo 2006.231.08:27:01.50/chk_obsdata//k5ts1/T2310826??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:27:01.87/chk_obsdata//k5ts2/T2310826??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:27:02.24/chk_obsdata//k5ts3/T2310826??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:27:02.61/chk_obsdata//k5ts4/T2310826??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.231.08:27:03.30/k5log//k5ts1_log_newline 2006.231.08:27:03.99/k5log//k5ts2_log_newline 2006.231.08:27:04.68/k5log//k5ts3_log_newline 2006.231.08:27:05.36/k5log//k5ts4_log_newline 2006.231.08:27:05.39/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.231.08:27:05.39:"sched_end 2006.231.08:27:05.39:source=idle 2006.231.08:27:06.14:stow 2006.231.08:27:06.14&stow/source=idle 2006.231.08:27:06.14&stow/"this is stow command. 2006.231.08:27:06.14&stow/antenna=m3 2006.231.08:27:06.14#flagr#flagr/antenna,new-source 2006.231.08:27:09.01:!+10m 2006.231.08:37:09.02:standby 2006.231.08:37:09.02&standby/"this is standby command. 2006.231.08:37:09.02&standby/antenna=m0 2006.231.08:37:10.01:checkk5hdd 2006.231.08:37:10.01&checkk5hdd/chk_hdd=1 2006.231.08:37:10.01&checkk5hdd/chk_hdd=2 2006.231.08:37:10.01&checkk5hdd/chk_hdd=3 2006.231.08:37:10.01&checkk5hdd/chk_hdd=4 2006.231.08:37:12.81/chk_hdd//k5ts1/GSI00275:T231073000a.dat~T231082600a.dat[12937396224Byte] 2006.231.08:37:15.61/chk_hdd//k5ts2/GSI00163:T231073000b.dat~T231082600b.dat[12937396224Byte] 2006.231.08:37:18.40/chk_hdd//k5ts3/GSI00278:T231073000c.dat~T231082600c.dat[12937396224Byte] 2006.231.08:37:21.21/chk_hdd//k5ts4/GSI00141:T231073000d.dat~T231082600d.dat[12937396224Byte] 2006.231.08:37:21.21:sy=cp /usr2/log/k06231ts.log /usr2/log_backup/ 2006.231.08:37:21.29:log=k06232ts