2006.224.08:37:31.35:Log Opened: Mark IV Field System Version 9.7.7 2006.224.08:37:31.35:location,TSUKUB32,-140.09,36.10,61.0 2006.224.08:37:31.35:horizon1,0.,5.,360. 2006.224.08:37:31.36:antenna,32.0,180.0,180.0,10.0,710.0,5.0,88.0,azel 2006.224.08:37:31.36:equip,k42c/mk4,vlbab,vlbab,mk4,500.10,3,a/d,101,60,20,none,41,1,in,8bit,cdp,3 2006.224.08:37:31.36:drivev11,330,270,no 2006.224.08:37:31.36:drivev12,mvme117,0,11.400,2548.000,152.780,-6.655,0.014,152,10.000,54500 2006.224.08:37:31.36:drivev13,15.000,268,10.000,10.000,10.000 2006.224.08:37:31.36:drivev21,330,270,no 2006.224.08:37:31.36:drivev22,mvme117,0,11.500,2821.000,127.500,-8.640,0.015,152,14.000,54500 2006.224.08:37:31.36:drivev23,15.000,268,10.000,10.000,10.000 2006.224.08:37:31.36:head10,all,all,all,odd,adaptive,no,5.0000,1 2006.224.08:37:31.36:head11,131.5,16.4,-291.0,131.5,16.4,0.8,168.30,168.30 2006.224.08:37:31.36:head12,122.8,13.9,-150.8,122.8,14.7,2.5,167.61,167.61 2006.224.08:37:31.36:head20,all,all,all,odd,adaptive,no,5.0000,1 2006.224.08:37:31.36:head21,145.3,16.1,-209.3,137.2,16.1,58.9,165.28,165.28 2006.224.08:37:31.36:head22,157.5,17.4,-203.7,149.2,16.6,56.5,169.73,169.73 2006.224.08:37:31.36:time,-0.364,101.533,rate 2006.224.08:37:31.36:flagr,200 2006.224.08:37:31.36:proc=k06225ts 2006.224.08:37:31.36:" k06225 2006 tsukub32 t ts 2006.224.08:37:31.36:" t tsukub32 azel .0000 180.0 14 10.0 710.0 180.0 14 5.0 88.0 32.0 ts 108 2006.224.08:37:31.36:" ts tsukub32 -3957408.75120 3310229.34660 3737494.83600 73452301 2006.224.08:37:31.36:" 108 tsukub32 14 17400 2006.224.08:37:31.36:" drudg version 050216 compiled under fs 9.7.07 2006.224.08:37:31.36:" rack=k4-2/m4 recorder 1=k5 recorder 2=none 2006.224.08:37:31.36:!2006.225.06:29:50 2006.224.10:29:07.57?ERROR st -97 Trouble decoding pressure data 2006.224.10:29:07.57#wxget#05 0.7 1.7 22.311001005.3 2006.225.06:29:50.00:sy=/usr2/oper/k5/bin/freeze_chk.pl & 2006.225.06:29:50.02:!2006.225.07:19:50 2006.225.07:19:50.00:unstow 2006.225.07:19:50.00&unstow/antenna=e 2006.225.07:19:50.00&unstow/!+10s 2006.225.07:19:50.00&unstow/antenna=m2 2006.225.07:20:02.01:scan_name=225-0730,k06225,60 2006.225.07:20:02.01:source=3c418,203837.03,511912.7,2000.0,ccw 2006.225.07:20:02.01#antcn#PM 1 00019 2005 228 00 22 31 00 2006.225.07:20:02.01#antcn#PM 2 90.0000 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 2006.225.07:20:02.01#antcn#PM 2 -0.0279715 0.0000000 -0.0282214 -0.0241630 -0.0014011 2006.225.07:20:02.01#antcn#PM 3 -0.0059899 0.0042895 -0.0643783 0.0000000 0.0000000 2006.225.07:20:02.01#antcn#PM 4 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.225.07:20:02.01#antcn#PM 5 0.0000000 0.0000000 0.0000000 0.0000000 0.0000000 2006.225.07:20:03.14:ready_k5 2006.225.07:20:03.14&ready_k5/obsinfo=st 2006.225.07:20:03.14&ready_k5/autoobs=1 2006.225.07:20:03.14&ready_k5/autoobs=2 2006.225.07:20:03.14&ready_k5/autoobs=3 2006.225.07:20:03.14&ready_k5/autoobs=4 2006.225.07:20:03.14&ready_k5/obsinfo 2006.225.07:20:03.14/obsinfo=st/error_log.tmp was not found (or not removed). 2006.225.07:20:03.14#flagr#flagr/antenna,new-source 2006.225.07:20:06.32/autoobs//k5ts1/ autoobs started! 2006.225.07:20:09.43/autoobs//k5ts2/ autoobs started! 2006.225.07:20:12.55/autoobs//k5ts3/ autoobs started! 2006.225.07:20:15.67/autoobs//k5ts4/ autoobs started! 2006.225.07:20:15.70/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:20:15.70:4f8m12a=1 2006.225.07:20:15.70&4f8m12a/xlog=on 2006.225.07:20:15.70&4f8m12a/echo=on 2006.225.07:20:15.70&4f8m12a/pcalon 2006.225.07:20:15.70&4f8m12a/"tpicd=stop 2006.225.07:20:15.70&4f8m12a/vc4f8 2006.225.07:20:15.70&4f8m12a/ifd4f 2006.225.07:20:15.70&4f8m12a/"form=m,16.000,1:2 2006.225.07:20:15.70&4f8m12a/"tpicd 2006.225.07:20:15.70&4f8m12a/echo=off 2006.225.07:20:15.70&4f8m12a/xlog=off 2006.225.07:20:15.70$4f8m12a/echo=on 2006.225.07:20:15.70$4f8m12a/pcalon 2006.225.07:20:15.70&pcalon/"no phase cal control is implemented here 2006.225.07:20:15.70$pcalon/"no phase cal control is implemented here 2006.225.07:20:15.70$4f8m12a/"tpicd=stop 2006.225.07:20:15.70$4f8m12a/vc4f8 2006.225.07:20:15.70&vc4f8/valo=1,532.99 2006.225.07:20:15.70&vc4f8/va=1,8 2006.225.07:20:15.70&vc4f8/valo=2,572.99 2006.225.07:20:15.70&vc4f8/va=2,7 2006.225.07:20:15.70&vc4f8/valo=3,672.99 2006.225.07:20:15.70&vc4f8/va=3,6 2006.225.07:20:15.70&vc4f8/valo=4,832.99 2006.225.07:20:15.70&vc4f8/va=4,7 2006.225.07:20:15.70&vc4f8/valo=5,652.99 2006.225.07:20:15.70&vc4f8/va=5,7 2006.225.07:20:15.70&vc4f8/valo=6,772.99 2006.225.07:20:15.70&vc4f8/va=6,6 2006.225.07:20:15.70&vc4f8/valo=7,832.99 2006.225.07:20:15.70&vc4f8/va=7,6 2006.225.07:20:15.70&vc4f8/valo=8,852.99 2006.225.07:20:15.70&vc4f8/va=8,7 2006.225.07:20:15.70&vc4f8/vblo=1,632.99 2006.225.07:20:15.70&vc4f8/vb=1,4 2006.225.07:20:15.70&vc4f8/vblo=2,640.99 2006.225.07:20:15.70&vc4f8/vb=2,4 2006.225.07:20:15.70&vc4f8/vblo=3,656.99 2006.225.07:20:15.70&vc4f8/vb=3,4 2006.225.07:20:15.70&vc4f8/vblo=4,712.99 2006.225.07:20:15.70&vc4f8/vb=4,4 2006.225.07:20:15.70&vc4f8/vblo=5,744.99 2006.225.07:20:15.70&vc4f8/vb=5,4 2006.225.07:20:15.70&vc4f8/vblo=6,752.99 2006.225.07:20:15.70&vc4f8/vb=6,4 2006.225.07:20:15.70&vc4f8/vabw=wide 2006.225.07:20:15.70&vc4f8/vbbw=wide 2006.225.07:20:15.70$vc4f8/valo=1,532.99 2006.225.07:20:15.71#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.07:20:15.71#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.07:20:15.71#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:15.71#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:20:15.71#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:20:15.71#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:20:15.71#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:20:15.71#ibcon#first serial, iclass 36, count 0 2006.225.07:20:15.71#ibcon#enter sib2, iclass 36, count 0 2006.225.07:20:15.71#ibcon#flushed, iclass 36, count 0 2006.225.07:20:15.71#ibcon#about to write, iclass 36, count 0 2006.225.07:20:15.71#ibcon#wrote, iclass 36, count 0 2006.225.07:20:15.71#ibcon#about to read 3, iclass 36, count 0 2006.225.07:20:15.74#ibcon#read 3, iclass 36, count 0 2006.225.07:20:15.74#ibcon#about to read 4, iclass 36, count 0 2006.225.07:20:15.74#ibcon#read 4, iclass 36, count 0 2006.225.07:20:15.74#ibcon#about to read 5, iclass 36, count 0 2006.225.07:20:15.74#ibcon#read 5, iclass 36, count 0 2006.225.07:20:15.74#ibcon#about to read 6, iclass 36, count 0 2006.225.07:20:15.74#ibcon#read 6, iclass 36, count 0 2006.225.07:20:15.74#ibcon#end of sib2, iclass 36, count 0 2006.225.07:20:15.74#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:20:15.74#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:20:15.74#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:20:15.74#ibcon#*before write, iclass 36, count 0 2006.225.07:20:15.74#ibcon#enter sib2, iclass 36, count 0 2006.225.07:20:15.74#ibcon#flushed, iclass 36, count 0 2006.225.07:20:15.74#ibcon#about to write, iclass 36, count 0 2006.225.07:20:15.74#ibcon#wrote, iclass 36, count 0 2006.225.07:20:15.74#ibcon#about to read 3, iclass 36, count 0 2006.225.07:20:15.79#ibcon#read 3, iclass 36, count 0 2006.225.07:20:15.79#ibcon#about to read 4, iclass 36, count 0 2006.225.07:20:15.79#ibcon#read 4, iclass 36, count 0 2006.225.07:20:15.79#ibcon#about to read 5, iclass 36, count 0 2006.225.07:20:15.79#ibcon#read 5, iclass 36, count 0 2006.225.07:20:15.79#ibcon#about to read 6, iclass 36, count 0 2006.225.07:20:15.79#ibcon#read 6, iclass 36, count 0 2006.225.07:20:15.79#ibcon#end of sib2, iclass 36, count 0 2006.225.07:20:15.79#ibcon#*after write, iclass 36, count 0 2006.225.07:20:15.79#ibcon#*before return 0, iclass 36, count 0 2006.225.07:20:15.79#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:20:15.79#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:20:15.79#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:20:15.79#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:20:15.79$vc4f8/va=1,8 2006.225.07:20:15.79#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.07:20:15.79#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.07:20:15.79#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:15.79#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:20:15.79#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:20:15.79#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:20:15.79#ibcon#enter wrdev, iclass 38, count 2 2006.225.07:20:15.79#ibcon#first serial, iclass 38, count 2 2006.225.07:20:15.79#ibcon#enter sib2, iclass 38, count 2 2006.225.07:20:15.79#ibcon#flushed, iclass 38, count 2 2006.225.07:20:15.79#ibcon#about to write, iclass 38, count 2 2006.225.07:20:15.79#ibcon#wrote, iclass 38, count 2 2006.225.07:20:15.79#ibcon#about to read 3, iclass 38, count 2 2006.225.07:20:15.81#ibcon#read 3, iclass 38, count 2 2006.225.07:20:15.81#ibcon#about to read 4, iclass 38, count 2 2006.225.07:20:15.81#ibcon#read 4, iclass 38, count 2 2006.225.07:20:15.81#ibcon#about to read 5, iclass 38, count 2 2006.225.07:20:15.81#ibcon#read 5, iclass 38, count 2 2006.225.07:20:15.81#ibcon#about to read 6, iclass 38, count 2 2006.225.07:20:15.81#ibcon#read 6, iclass 38, count 2 2006.225.07:20:15.81#ibcon#end of sib2, iclass 38, count 2 2006.225.07:20:15.81#ibcon#*mode == 0, iclass 38, count 2 2006.225.07:20:15.81#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.07:20:15.81#ibcon#[25=AT01-08\r\n] 2006.225.07:20:15.81#ibcon#*before write, iclass 38, count 2 2006.225.07:20:15.81#ibcon#enter sib2, iclass 38, count 2 2006.225.07:20:15.81#ibcon#flushed, iclass 38, count 2 2006.225.07:20:15.81#ibcon#about to write, iclass 38, count 2 2006.225.07:20:15.81#ibcon#wrote, iclass 38, count 2 2006.225.07:20:15.81#ibcon#about to read 3, iclass 38, count 2 2006.225.07:20:15.85#ibcon#read 3, iclass 38, count 2 2006.225.07:20:15.85#ibcon#about to read 4, iclass 38, count 2 2006.225.07:20:15.85#ibcon#read 4, iclass 38, count 2 2006.225.07:20:15.85#ibcon#about to read 5, iclass 38, count 2 2006.225.07:20:15.85#ibcon#read 5, iclass 38, count 2 2006.225.07:20:15.85#ibcon#about to read 6, iclass 38, count 2 2006.225.07:20:15.85#ibcon#read 6, iclass 38, count 2 2006.225.07:20:15.85#ibcon#end of sib2, iclass 38, count 2 2006.225.07:20:15.85#ibcon#*after write, iclass 38, count 2 2006.225.07:20:15.85#ibcon#*before return 0, iclass 38, count 2 2006.225.07:20:15.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:20:15.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:20:15.85#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.07:20:15.85#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:15.85#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:20:15.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:20:15.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:20:15.97#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:20:15.97#ibcon#first serial, iclass 38, count 0 2006.225.07:20:15.97#ibcon#enter sib2, iclass 38, count 0 2006.225.07:20:15.97#ibcon#flushed, iclass 38, count 0 2006.225.07:20:15.97#ibcon#about to write, iclass 38, count 0 2006.225.07:20:15.97#ibcon#wrote, iclass 38, count 0 2006.225.07:20:15.97#ibcon#about to read 3, iclass 38, count 0 2006.225.07:20:15.99#ibcon#read 3, iclass 38, count 0 2006.225.07:20:15.99#ibcon#about to read 4, iclass 38, count 0 2006.225.07:20:15.99#ibcon#read 4, iclass 38, count 0 2006.225.07:20:15.99#ibcon#about to read 5, iclass 38, count 0 2006.225.07:20:15.99#ibcon#read 5, iclass 38, count 0 2006.225.07:20:15.99#ibcon#about to read 6, iclass 38, count 0 2006.225.07:20:15.99#ibcon#read 6, iclass 38, count 0 2006.225.07:20:15.99#ibcon#end of sib2, iclass 38, count 0 2006.225.07:20:15.99#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:20:15.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:20:15.99#ibcon#[25=USB\r\n] 2006.225.07:20:15.99#ibcon#*before write, iclass 38, count 0 2006.225.07:20:15.99#ibcon#enter sib2, iclass 38, count 0 2006.225.07:20:15.99#ibcon#flushed, iclass 38, count 0 2006.225.07:20:15.99#ibcon#about to write, iclass 38, count 0 2006.225.07:20:15.99#ibcon#wrote, iclass 38, count 0 2006.225.07:20:15.99#ibcon#about to read 3, iclass 38, count 0 2006.225.07:20:16.02#ibcon#read 3, iclass 38, count 0 2006.225.07:20:16.02#ibcon#about to read 4, iclass 38, count 0 2006.225.07:20:16.02#ibcon#read 4, iclass 38, count 0 2006.225.07:20:16.02#ibcon#about to read 5, iclass 38, count 0 2006.225.07:20:16.02#ibcon#read 5, iclass 38, count 0 2006.225.07:20:16.02#ibcon#about to read 6, iclass 38, count 0 2006.225.07:20:16.02#ibcon#read 6, iclass 38, count 0 2006.225.07:20:16.02#ibcon#end of sib2, iclass 38, count 0 2006.225.07:20:16.02#ibcon#*after write, iclass 38, count 0 2006.225.07:20:16.02#ibcon#*before return 0, iclass 38, count 0 2006.225.07:20:16.02#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:20:16.02#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:20:16.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:20:16.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:20:16.02$vc4f8/valo=2,572.99 2006.225.07:20:16.02#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.07:20:16.02#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.07:20:16.02#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:16.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:20:16.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:20:16.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:20:16.02#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:20:16.02#ibcon#first serial, iclass 40, count 0 2006.225.07:20:16.02#ibcon#enter sib2, iclass 40, count 0 2006.225.07:20:16.02#ibcon#flushed, iclass 40, count 0 2006.225.07:20:16.02#ibcon#about to write, iclass 40, count 0 2006.225.07:20:16.02#ibcon#wrote, iclass 40, count 0 2006.225.07:20:16.02#ibcon#about to read 3, iclass 40, count 0 2006.225.07:20:16.04#ibcon#read 3, iclass 40, count 0 2006.225.07:20:16.04#ibcon#about to read 4, iclass 40, count 0 2006.225.07:20:16.04#ibcon#read 4, iclass 40, count 0 2006.225.07:20:16.04#ibcon#about to read 5, iclass 40, count 0 2006.225.07:20:16.04#ibcon#read 5, iclass 40, count 0 2006.225.07:20:16.04#ibcon#about to read 6, iclass 40, count 0 2006.225.07:20:16.04#ibcon#read 6, iclass 40, count 0 2006.225.07:20:16.04#ibcon#end of sib2, iclass 40, count 0 2006.225.07:20:16.04#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:20:16.04#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:20:16.04#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:20:16.04#ibcon#*before write, iclass 40, count 0 2006.225.07:20:16.04#ibcon#enter sib2, iclass 40, count 0 2006.225.07:20:16.04#ibcon#flushed, iclass 40, count 0 2006.225.07:20:16.04#ibcon#about to write, iclass 40, count 0 2006.225.07:20:16.04#ibcon#wrote, iclass 40, count 0 2006.225.07:20:16.04#ibcon#about to read 3, iclass 40, count 0 2006.225.07:20:16.08#ibcon#read 3, iclass 40, count 0 2006.225.07:20:16.08#ibcon#about to read 4, iclass 40, count 0 2006.225.07:20:16.08#ibcon#read 4, iclass 40, count 0 2006.225.07:20:16.08#ibcon#about to read 5, iclass 40, count 0 2006.225.07:20:16.08#ibcon#read 5, iclass 40, count 0 2006.225.07:20:16.08#ibcon#about to read 6, iclass 40, count 0 2006.225.07:20:16.08#ibcon#read 6, iclass 40, count 0 2006.225.07:20:16.08#ibcon#end of sib2, iclass 40, count 0 2006.225.07:20:16.08#ibcon#*after write, iclass 40, count 0 2006.225.07:20:16.08#ibcon#*before return 0, iclass 40, count 0 2006.225.07:20:16.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:20:16.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:20:16.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:20:16.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:20:16.08$vc4f8/va=2,7 2006.225.07:20:16.08#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.07:20:16.08#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.07:20:16.08#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:16.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:20:16.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:20:16.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:20:16.14#ibcon#enter wrdev, iclass 4, count 2 2006.225.07:20:16.14#ibcon#first serial, iclass 4, count 2 2006.225.07:20:16.14#ibcon#enter sib2, iclass 4, count 2 2006.225.07:20:16.14#ibcon#flushed, iclass 4, count 2 2006.225.07:20:16.14#ibcon#about to write, iclass 4, count 2 2006.225.07:20:16.14#ibcon#wrote, iclass 4, count 2 2006.225.07:20:16.14#ibcon#about to read 3, iclass 4, count 2 2006.225.07:20:16.16#ibcon#read 3, iclass 4, count 2 2006.225.07:20:16.16#ibcon#about to read 4, iclass 4, count 2 2006.225.07:20:16.16#ibcon#read 4, iclass 4, count 2 2006.225.07:20:16.16#ibcon#about to read 5, iclass 4, count 2 2006.225.07:20:16.16#ibcon#read 5, iclass 4, count 2 2006.225.07:20:16.16#ibcon#about to read 6, iclass 4, count 2 2006.225.07:20:16.16#ibcon#read 6, iclass 4, count 2 2006.225.07:20:16.16#ibcon#end of sib2, iclass 4, count 2 2006.225.07:20:16.16#ibcon#*mode == 0, iclass 4, count 2 2006.225.07:20:16.16#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.07:20:16.16#ibcon#[25=AT02-07\r\n] 2006.225.07:20:16.16#ibcon#*before write, iclass 4, count 2 2006.225.07:20:16.16#ibcon#enter sib2, iclass 4, count 2 2006.225.07:20:16.16#ibcon#flushed, iclass 4, count 2 2006.225.07:20:16.16#ibcon#about to write, iclass 4, count 2 2006.225.07:20:16.16#ibcon#wrote, iclass 4, count 2 2006.225.07:20:16.16#ibcon#about to read 3, iclass 4, count 2 2006.225.07:20:16.19#ibcon#read 3, iclass 4, count 2 2006.225.07:20:16.19#ibcon#about to read 4, iclass 4, count 2 2006.225.07:20:16.19#ibcon#read 4, iclass 4, count 2 2006.225.07:20:16.19#ibcon#about to read 5, iclass 4, count 2 2006.225.07:20:16.19#ibcon#read 5, iclass 4, count 2 2006.225.07:20:16.19#ibcon#about to read 6, iclass 4, count 2 2006.225.07:20:16.19#ibcon#read 6, iclass 4, count 2 2006.225.07:20:16.19#ibcon#end of sib2, iclass 4, count 2 2006.225.07:20:16.19#ibcon#*after write, iclass 4, count 2 2006.225.07:20:16.19#ibcon#*before return 0, iclass 4, count 2 2006.225.07:20:16.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:20:16.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:20:16.19#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.07:20:16.19#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:16.19#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:20:16.31#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:20:16.31#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:20:16.31#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:20:16.31#ibcon#first serial, iclass 4, count 0 2006.225.07:20:16.31#ibcon#enter sib2, iclass 4, count 0 2006.225.07:20:16.31#ibcon#flushed, iclass 4, count 0 2006.225.07:20:16.31#ibcon#about to write, iclass 4, count 0 2006.225.07:20:16.31#ibcon#wrote, iclass 4, count 0 2006.225.07:20:16.31#ibcon#about to read 3, iclass 4, count 0 2006.225.07:20:16.33#ibcon#read 3, iclass 4, count 0 2006.225.07:20:16.33#ibcon#about to read 4, iclass 4, count 0 2006.225.07:20:16.33#ibcon#read 4, iclass 4, count 0 2006.225.07:20:16.33#ibcon#about to read 5, iclass 4, count 0 2006.225.07:20:16.33#ibcon#read 5, iclass 4, count 0 2006.225.07:20:16.33#ibcon#about to read 6, iclass 4, count 0 2006.225.07:20:16.33#ibcon#read 6, iclass 4, count 0 2006.225.07:20:16.33#ibcon#end of sib2, iclass 4, count 0 2006.225.07:20:16.33#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:20:16.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:20:16.33#ibcon#[25=USB\r\n] 2006.225.07:20:16.33#ibcon#*before write, iclass 4, count 0 2006.225.07:20:16.33#ibcon#enter sib2, iclass 4, count 0 2006.225.07:20:16.33#ibcon#flushed, iclass 4, count 0 2006.225.07:20:16.33#ibcon#about to write, iclass 4, count 0 2006.225.07:20:16.33#ibcon#wrote, iclass 4, count 0 2006.225.07:20:16.33#ibcon#about to read 3, iclass 4, count 0 2006.225.07:20:16.36#ibcon#read 3, iclass 4, count 0 2006.225.07:20:16.36#ibcon#about to read 4, iclass 4, count 0 2006.225.07:20:16.36#ibcon#read 4, iclass 4, count 0 2006.225.07:20:16.36#ibcon#about to read 5, iclass 4, count 0 2006.225.07:20:16.36#ibcon#read 5, iclass 4, count 0 2006.225.07:20:16.36#ibcon#about to read 6, iclass 4, count 0 2006.225.07:20:16.36#ibcon#read 6, iclass 4, count 0 2006.225.07:20:16.36#ibcon#end of sib2, iclass 4, count 0 2006.225.07:20:16.36#ibcon#*after write, iclass 4, count 0 2006.225.07:20:16.36#ibcon#*before return 0, iclass 4, count 0 2006.225.07:20:16.36#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:20:16.36#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:20:16.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:20:16.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:20:16.36$vc4f8/valo=3,672.99 2006.225.07:20:16.36#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.07:20:16.36#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.07:20:16.36#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:16.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:20:16.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:20:16.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:20:16.36#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:20:16.36#ibcon#first serial, iclass 6, count 0 2006.225.07:20:16.36#ibcon#enter sib2, iclass 6, count 0 2006.225.07:20:16.36#ibcon#flushed, iclass 6, count 0 2006.225.07:20:16.36#ibcon#about to write, iclass 6, count 0 2006.225.07:20:16.36#ibcon#wrote, iclass 6, count 0 2006.225.07:20:16.36#ibcon#about to read 3, iclass 6, count 0 2006.225.07:20:16.38#ibcon#read 3, iclass 6, count 0 2006.225.07:20:16.38#ibcon#about to read 4, iclass 6, count 0 2006.225.07:20:16.38#ibcon#read 4, iclass 6, count 0 2006.225.07:20:16.38#ibcon#about to read 5, iclass 6, count 0 2006.225.07:20:16.38#ibcon#read 5, iclass 6, count 0 2006.225.07:20:16.38#ibcon#about to read 6, iclass 6, count 0 2006.225.07:20:16.38#ibcon#read 6, iclass 6, count 0 2006.225.07:20:16.38#ibcon#end of sib2, iclass 6, count 0 2006.225.07:20:16.38#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:20:16.38#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:20:16.38#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:20:16.38#ibcon#*before write, iclass 6, count 0 2006.225.07:20:16.38#ibcon#enter sib2, iclass 6, count 0 2006.225.07:20:16.38#ibcon#flushed, iclass 6, count 0 2006.225.07:20:16.38#ibcon#about to write, iclass 6, count 0 2006.225.07:20:16.38#ibcon#wrote, iclass 6, count 0 2006.225.07:20:16.38#ibcon#about to read 3, iclass 6, count 0 2006.225.07:20:16.42#ibcon#read 3, iclass 6, count 0 2006.225.07:20:16.42#ibcon#about to read 4, iclass 6, count 0 2006.225.07:20:16.42#ibcon#read 4, iclass 6, count 0 2006.225.07:20:16.42#ibcon#about to read 5, iclass 6, count 0 2006.225.07:20:16.42#ibcon#read 5, iclass 6, count 0 2006.225.07:20:16.42#ibcon#about to read 6, iclass 6, count 0 2006.225.07:20:16.42#ibcon#read 6, iclass 6, count 0 2006.225.07:20:16.42#ibcon#end of sib2, iclass 6, count 0 2006.225.07:20:16.42#ibcon#*after write, iclass 6, count 0 2006.225.07:20:16.42#ibcon#*before return 0, iclass 6, count 0 2006.225.07:20:16.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:20:16.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:20:16.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:20:16.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:20:16.42$vc4f8/va=3,6 2006.225.07:20:16.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.225.07:20:16.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.225.07:20:16.42#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:16.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:20:16.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:20:16.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:20:16.48#ibcon#enter wrdev, iclass 10, count 2 2006.225.07:20:16.48#ibcon#first serial, iclass 10, count 2 2006.225.07:20:16.48#ibcon#enter sib2, iclass 10, count 2 2006.225.07:20:16.48#ibcon#flushed, iclass 10, count 2 2006.225.07:20:16.48#ibcon#about to write, iclass 10, count 2 2006.225.07:20:16.48#ibcon#wrote, iclass 10, count 2 2006.225.07:20:16.48#ibcon#about to read 3, iclass 10, count 2 2006.225.07:20:16.50#ibcon#read 3, iclass 10, count 2 2006.225.07:20:16.50#ibcon#about to read 4, iclass 10, count 2 2006.225.07:20:16.50#ibcon#read 4, iclass 10, count 2 2006.225.07:20:16.50#ibcon#about to read 5, iclass 10, count 2 2006.225.07:20:16.50#ibcon#read 5, iclass 10, count 2 2006.225.07:20:16.50#ibcon#about to read 6, iclass 10, count 2 2006.225.07:20:16.50#ibcon#read 6, iclass 10, count 2 2006.225.07:20:16.50#ibcon#end of sib2, iclass 10, count 2 2006.225.07:20:16.50#ibcon#*mode == 0, iclass 10, count 2 2006.225.07:20:16.50#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.225.07:20:16.50#ibcon#[25=AT03-06\r\n] 2006.225.07:20:16.50#ibcon#*before write, iclass 10, count 2 2006.225.07:20:16.50#ibcon#enter sib2, iclass 10, count 2 2006.225.07:20:16.50#ibcon#flushed, iclass 10, count 2 2006.225.07:20:16.50#ibcon#about to write, iclass 10, count 2 2006.225.07:20:16.50#ibcon#wrote, iclass 10, count 2 2006.225.07:20:16.50#ibcon#about to read 3, iclass 10, count 2 2006.225.07:20:16.53#ibcon#read 3, iclass 10, count 2 2006.225.07:20:16.53#ibcon#about to read 4, iclass 10, count 2 2006.225.07:20:16.53#ibcon#read 4, iclass 10, count 2 2006.225.07:20:16.53#ibcon#about to read 5, iclass 10, count 2 2006.225.07:20:16.53#ibcon#read 5, iclass 10, count 2 2006.225.07:20:16.53#ibcon#about to read 6, iclass 10, count 2 2006.225.07:20:16.53#ibcon#read 6, iclass 10, count 2 2006.225.07:20:16.53#ibcon#end of sib2, iclass 10, count 2 2006.225.07:20:16.53#ibcon#*after write, iclass 10, count 2 2006.225.07:20:16.53#ibcon#*before return 0, iclass 10, count 2 2006.225.07:20:16.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:20:16.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:20:16.53#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.225.07:20:16.53#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:16.53#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:20:16.65#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:20:16.65#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:20:16.65#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:20:16.65#ibcon#first serial, iclass 10, count 0 2006.225.07:20:16.65#ibcon#enter sib2, iclass 10, count 0 2006.225.07:20:16.65#ibcon#flushed, iclass 10, count 0 2006.225.07:20:16.65#ibcon#about to write, iclass 10, count 0 2006.225.07:20:16.65#ibcon#wrote, iclass 10, count 0 2006.225.07:20:16.65#ibcon#about to read 3, iclass 10, count 0 2006.225.07:20:16.67#ibcon#read 3, iclass 10, count 0 2006.225.07:20:16.67#ibcon#about to read 4, iclass 10, count 0 2006.225.07:20:16.67#ibcon#read 4, iclass 10, count 0 2006.225.07:20:16.67#ibcon#about to read 5, iclass 10, count 0 2006.225.07:20:16.67#ibcon#read 5, iclass 10, count 0 2006.225.07:20:16.67#ibcon#about to read 6, iclass 10, count 0 2006.225.07:20:16.67#ibcon#read 6, iclass 10, count 0 2006.225.07:20:16.67#ibcon#end of sib2, iclass 10, count 0 2006.225.07:20:16.67#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:20:16.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:20:16.67#ibcon#[25=USB\r\n] 2006.225.07:20:16.67#ibcon#*before write, iclass 10, count 0 2006.225.07:20:16.67#ibcon#enter sib2, iclass 10, count 0 2006.225.07:20:16.67#ibcon#flushed, iclass 10, count 0 2006.225.07:20:16.67#ibcon#about to write, iclass 10, count 0 2006.225.07:20:16.67#ibcon#wrote, iclass 10, count 0 2006.225.07:20:16.67#ibcon#about to read 3, iclass 10, count 0 2006.225.07:20:16.70#ibcon#read 3, iclass 10, count 0 2006.225.07:20:16.70#ibcon#about to read 4, iclass 10, count 0 2006.225.07:20:16.70#ibcon#read 4, iclass 10, count 0 2006.225.07:20:16.70#ibcon#about to read 5, iclass 10, count 0 2006.225.07:20:16.70#ibcon#read 5, iclass 10, count 0 2006.225.07:20:16.70#ibcon#about to read 6, iclass 10, count 0 2006.225.07:20:16.70#ibcon#read 6, iclass 10, count 0 2006.225.07:20:16.70#ibcon#end of sib2, iclass 10, count 0 2006.225.07:20:16.70#ibcon#*after write, iclass 10, count 0 2006.225.07:20:16.70#ibcon#*before return 0, iclass 10, count 0 2006.225.07:20:16.70#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:20:16.70#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:20:16.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:20:16.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:20:16.70$vc4f8/valo=4,832.99 2006.225.07:20:16.70#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.07:20:16.70#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.07:20:16.70#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:16.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:20:16.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:20:16.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:20:16.70#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:20:16.70#ibcon#first serial, iclass 12, count 0 2006.225.07:20:16.70#ibcon#enter sib2, iclass 12, count 0 2006.225.07:20:16.70#ibcon#flushed, iclass 12, count 0 2006.225.07:20:16.70#ibcon#about to write, iclass 12, count 0 2006.225.07:20:16.70#ibcon#wrote, iclass 12, count 0 2006.225.07:20:16.70#ibcon#about to read 3, iclass 12, count 0 2006.225.07:20:16.72#ibcon#read 3, iclass 12, count 0 2006.225.07:20:16.72#ibcon#about to read 4, iclass 12, count 0 2006.225.07:20:16.72#ibcon#read 4, iclass 12, count 0 2006.225.07:20:16.72#ibcon#about to read 5, iclass 12, count 0 2006.225.07:20:16.72#ibcon#read 5, iclass 12, count 0 2006.225.07:20:16.72#ibcon#about to read 6, iclass 12, count 0 2006.225.07:20:16.72#ibcon#read 6, iclass 12, count 0 2006.225.07:20:16.72#ibcon#end of sib2, iclass 12, count 0 2006.225.07:20:16.72#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:20:16.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:20:16.72#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:20:16.72#ibcon#*before write, iclass 12, count 0 2006.225.07:20:16.72#ibcon#enter sib2, iclass 12, count 0 2006.225.07:20:16.72#ibcon#flushed, iclass 12, count 0 2006.225.07:20:16.72#ibcon#about to write, iclass 12, count 0 2006.225.07:20:16.72#ibcon#wrote, iclass 12, count 0 2006.225.07:20:16.72#ibcon#about to read 3, iclass 12, count 0 2006.225.07:20:16.76#ibcon#read 3, iclass 12, count 0 2006.225.07:20:16.76#ibcon#about to read 4, iclass 12, count 0 2006.225.07:20:16.76#ibcon#read 4, iclass 12, count 0 2006.225.07:20:16.76#ibcon#about to read 5, iclass 12, count 0 2006.225.07:20:16.76#ibcon#read 5, iclass 12, count 0 2006.225.07:20:16.76#ibcon#about to read 6, iclass 12, count 0 2006.225.07:20:16.76#ibcon#read 6, iclass 12, count 0 2006.225.07:20:16.76#ibcon#end of sib2, iclass 12, count 0 2006.225.07:20:16.76#ibcon#*after write, iclass 12, count 0 2006.225.07:20:16.76#ibcon#*before return 0, iclass 12, count 0 2006.225.07:20:16.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:20:16.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:20:16.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:20:16.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:20:16.76$vc4f8/va=4,7 2006.225.07:20:16.76#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.225.07:20:16.76#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.225.07:20:16.76#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:16.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:20:16.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:20:16.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:20:16.82#ibcon#enter wrdev, iclass 14, count 2 2006.225.07:20:16.82#ibcon#first serial, iclass 14, count 2 2006.225.07:20:16.82#ibcon#enter sib2, iclass 14, count 2 2006.225.07:20:16.82#ibcon#flushed, iclass 14, count 2 2006.225.07:20:16.82#ibcon#about to write, iclass 14, count 2 2006.225.07:20:16.82#ibcon#wrote, iclass 14, count 2 2006.225.07:20:16.82#ibcon#about to read 3, iclass 14, count 2 2006.225.07:20:16.84#ibcon#read 3, iclass 14, count 2 2006.225.07:20:16.84#ibcon#about to read 4, iclass 14, count 2 2006.225.07:20:16.84#ibcon#read 4, iclass 14, count 2 2006.225.07:20:16.84#ibcon#about to read 5, iclass 14, count 2 2006.225.07:20:16.84#ibcon#read 5, iclass 14, count 2 2006.225.07:20:16.84#ibcon#about to read 6, iclass 14, count 2 2006.225.07:20:16.84#ibcon#read 6, iclass 14, count 2 2006.225.07:20:16.84#ibcon#end of sib2, iclass 14, count 2 2006.225.07:20:16.84#ibcon#*mode == 0, iclass 14, count 2 2006.225.07:20:16.84#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.225.07:20:16.84#ibcon#[25=AT04-07\r\n] 2006.225.07:20:16.84#ibcon#*before write, iclass 14, count 2 2006.225.07:20:16.84#ibcon#enter sib2, iclass 14, count 2 2006.225.07:20:16.84#ibcon#flushed, iclass 14, count 2 2006.225.07:20:16.84#ibcon#about to write, iclass 14, count 2 2006.225.07:20:16.84#ibcon#wrote, iclass 14, count 2 2006.225.07:20:16.84#ibcon#about to read 3, iclass 14, count 2 2006.225.07:20:16.87#ibcon#read 3, iclass 14, count 2 2006.225.07:20:16.87#ibcon#about to read 4, iclass 14, count 2 2006.225.07:20:16.87#ibcon#read 4, iclass 14, count 2 2006.225.07:20:16.87#ibcon#about to read 5, iclass 14, count 2 2006.225.07:20:16.87#ibcon#read 5, iclass 14, count 2 2006.225.07:20:16.87#ibcon#about to read 6, iclass 14, count 2 2006.225.07:20:16.87#ibcon#read 6, iclass 14, count 2 2006.225.07:20:16.87#ibcon#end of sib2, iclass 14, count 2 2006.225.07:20:16.87#ibcon#*after write, iclass 14, count 2 2006.225.07:20:16.87#ibcon#*before return 0, iclass 14, count 2 2006.225.07:20:16.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:20:16.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:20:16.87#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.225.07:20:16.87#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:16.87#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:20:16.99#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:20:16.99#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:20:16.99#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:20:16.99#ibcon#first serial, iclass 14, count 0 2006.225.07:20:16.99#ibcon#enter sib2, iclass 14, count 0 2006.225.07:20:16.99#ibcon#flushed, iclass 14, count 0 2006.225.07:20:16.99#ibcon#about to write, iclass 14, count 0 2006.225.07:20:16.99#ibcon#wrote, iclass 14, count 0 2006.225.07:20:16.99#ibcon#about to read 3, iclass 14, count 0 2006.225.07:20:17.01#ibcon#read 3, iclass 14, count 0 2006.225.07:20:17.01#ibcon#about to read 4, iclass 14, count 0 2006.225.07:20:17.01#ibcon#read 4, iclass 14, count 0 2006.225.07:20:17.01#ibcon#about to read 5, iclass 14, count 0 2006.225.07:20:17.01#ibcon#read 5, iclass 14, count 0 2006.225.07:20:17.01#ibcon#about to read 6, iclass 14, count 0 2006.225.07:20:17.01#ibcon#read 6, iclass 14, count 0 2006.225.07:20:17.01#ibcon#end of sib2, iclass 14, count 0 2006.225.07:20:17.01#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:20:17.01#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:20:17.01#ibcon#[25=USB\r\n] 2006.225.07:20:17.01#ibcon#*before write, iclass 14, count 0 2006.225.07:20:17.01#ibcon#enter sib2, iclass 14, count 0 2006.225.07:20:17.01#ibcon#flushed, iclass 14, count 0 2006.225.07:20:17.01#ibcon#about to write, iclass 14, count 0 2006.225.07:20:17.01#ibcon#wrote, iclass 14, count 0 2006.225.07:20:17.01#ibcon#about to read 3, iclass 14, count 0 2006.225.07:20:17.04#ibcon#read 3, iclass 14, count 0 2006.225.07:20:17.04#ibcon#about to read 4, iclass 14, count 0 2006.225.07:20:17.04#ibcon#read 4, iclass 14, count 0 2006.225.07:20:17.04#ibcon#about to read 5, iclass 14, count 0 2006.225.07:20:17.04#ibcon#read 5, iclass 14, count 0 2006.225.07:20:17.04#ibcon#about to read 6, iclass 14, count 0 2006.225.07:20:17.04#ibcon#read 6, iclass 14, count 0 2006.225.07:20:17.04#ibcon#end of sib2, iclass 14, count 0 2006.225.07:20:17.04#ibcon#*after write, iclass 14, count 0 2006.225.07:20:17.04#ibcon#*before return 0, iclass 14, count 0 2006.225.07:20:17.04#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:20:17.04#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:20:17.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:20:17.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:20:17.04$vc4f8/valo=5,652.99 2006.225.07:20:17.04#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.07:20:17.04#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.07:20:17.04#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:17.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:20:17.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:20:17.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:20:17.04#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:20:17.04#ibcon#first serial, iclass 16, count 0 2006.225.07:20:17.04#ibcon#enter sib2, iclass 16, count 0 2006.225.07:20:17.04#ibcon#flushed, iclass 16, count 0 2006.225.07:20:17.04#ibcon#about to write, iclass 16, count 0 2006.225.07:20:17.04#ibcon#wrote, iclass 16, count 0 2006.225.07:20:17.04#ibcon#about to read 3, iclass 16, count 0 2006.225.07:20:17.06#ibcon#read 3, iclass 16, count 0 2006.225.07:20:17.06#ibcon#about to read 4, iclass 16, count 0 2006.225.07:20:17.06#ibcon#read 4, iclass 16, count 0 2006.225.07:20:17.06#ibcon#about to read 5, iclass 16, count 0 2006.225.07:20:17.06#ibcon#read 5, iclass 16, count 0 2006.225.07:20:17.06#ibcon#about to read 6, iclass 16, count 0 2006.225.07:20:17.06#ibcon#read 6, iclass 16, count 0 2006.225.07:20:17.06#ibcon#end of sib2, iclass 16, count 0 2006.225.07:20:17.06#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:20:17.06#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:20:17.06#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:20:17.06#ibcon#*before write, iclass 16, count 0 2006.225.07:20:17.06#ibcon#enter sib2, iclass 16, count 0 2006.225.07:20:17.06#ibcon#flushed, iclass 16, count 0 2006.225.07:20:17.06#ibcon#about to write, iclass 16, count 0 2006.225.07:20:17.06#ibcon#wrote, iclass 16, count 0 2006.225.07:20:17.06#ibcon#about to read 3, iclass 16, count 0 2006.225.07:20:17.10#ibcon#read 3, iclass 16, count 0 2006.225.07:20:17.10#ibcon#about to read 4, iclass 16, count 0 2006.225.07:20:17.10#ibcon#read 4, iclass 16, count 0 2006.225.07:20:17.10#ibcon#about to read 5, iclass 16, count 0 2006.225.07:20:17.10#ibcon#read 5, iclass 16, count 0 2006.225.07:20:17.10#ibcon#about to read 6, iclass 16, count 0 2006.225.07:20:17.10#ibcon#read 6, iclass 16, count 0 2006.225.07:20:17.10#ibcon#end of sib2, iclass 16, count 0 2006.225.07:20:17.10#ibcon#*after write, iclass 16, count 0 2006.225.07:20:17.10#ibcon#*before return 0, iclass 16, count 0 2006.225.07:20:17.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:20:17.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:20:17.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:20:17.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:20:17.10$vc4f8/va=5,7 2006.225.07:20:17.10#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.225.07:20:17.10#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.225.07:20:17.10#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:17.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:20:17.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:20:17.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:20:17.16#ibcon#enter wrdev, iclass 18, count 2 2006.225.07:20:17.16#ibcon#first serial, iclass 18, count 2 2006.225.07:20:17.16#ibcon#enter sib2, iclass 18, count 2 2006.225.07:20:17.16#ibcon#flushed, iclass 18, count 2 2006.225.07:20:17.16#ibcon#about to write, iclass 18, count 2 2006.225.07:20:17.16#ibcon#wrote, iclass 18, count 2 2006.225.07:20:17.16#ibcon#about to read 3, iclass 18, count 2 2006.225.07:20:17.18#ibcon#read 3, iclass 18, count 2 2006.225.07:20:17.18#ibcon#about to read 4, iclass 18, count 2 2006.225.07:20:17.18#ibcon#read 4, iclass 18, count 2 2006.225.07:20:17.18#ibcon#about to read 5, iclass 18, count 2 2006.225.07:20:17.18#ibcon#read 5, iclass 18, count 2 2006.225.07:20:17.18#ibcon#about to read 6, iclass 18, count 2 2006.225.07:20:17.18#ibcon#read 6, iclass 18, count 2 2006.225.07:20:17.18#ibcon#end of sib2, iclass 18, count 2 2006.225.07:20:17.18#ibcon#*mode == 0, iclass 18, count 2 2006.225.07:20:17.18#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.225.07:20:17.18#ibcon#[25=AT05-07\r\n] 2006.225.07:20:17.18#ibcon#*before write, iclass 18, count 2 2006.225.07:20:17.18#ibcon#enter sib2, iclass 18, count 2 2006.225.07:20:17.18#ibcon#flushed, iclass 18, count 2 2006.225.07:20:17.18#ibcon#about to write, iclass 18, count 2 2006.225.07:20:17.18#ibcon#wrote, iclass 18, count 2 2006.225.07:20:17.18#ibcon#about to read 3, iclass 18, count 2 2006.225.07:20:17.21#ibcon#read 3, iclass 18, count 2 2006.225.07:20:17.21#ibcon#about to read 4, iclass 18, count 2 2006.225.07:20:17.21#ibcon#read 4, iclass 18, count 2 2006.225.07:20:17.21#ibcon#about to read 5, iclass 18, count 2 2006.225.07:20:17.21#ibcon#read 5, iclass 18, count 2 2006.225.07:20:17.21#ibcon#about to read 6, iclass 18, count 2 2006.225.07:20:17.21#ibcon#read 6, iclass 18, count 2 2006.225.07:20:17.21#ibcon#end of sib2, iclass 18, count 2 2006.225.07:20:17.21#ibcon#*after write, iclass 18, count 2 2006.225.07:20:17.21#ibcon#*before return 0, iclass 18, count 2 2006.225.07:20:17.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:20:17.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:20:17.21#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.225.07:20:17.21#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:17.21#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:20:17.33#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:20:17.33#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:20:17.33#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:20:17.33#ibcon#first serial, iclass 18, count 0 2006.225.07:20:17.33#ibcon#enter sib2, iclass 18, count 0 2006.225.07:20:17.33#ibcon#flushed, iclass 18, count 0 2006.225.07:20:17.33#ibcon#about to write, iclass 18, count 0 2006.225.07:20:17.33#ibcon#wrote, iclass 18, count 0 2006.225.07:20:17.33#ibcon#about to read 3, iclass 18, count 0 2006.225.07:20:17.35#ibcon#read 3, iclass 18, count 0 2006.225.07:20:17.35#ibcon#about to read 4, iclass 18, count 0 2006.225.07:20:17.35#ibcon#read 4, iclass 18, count 0 2006.225.07:20:17.35#ibcon#about to read 5, iclass 18, count 0 2006.225.07:20:17.35#ibcon#read 5, iclass 18, count 0 2006.225.07:20:17.35#ibcon#about to read 6, iclass 18, count 0 2006.225.07:20:17.35#ibcon#read 6, iclass 18, count 0 2006.225.07:20:17.35#ibcon#end of sib2, iclass 18, count 0 2006.225.07:20:17.35#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:20:17.35#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:20:17.35#ibcon#[25=USB\r\n] 2006.225.07:20:17.35#ibcon#*before write, iclass 18, count 0 2006.225.07:20:17.35#ibcon#enter sib2, iclass 18, count 0 2006.225.07:20:17.35#ibcon#flushed, iclass 18, count 0 2006.225.07:20:17.35#ibcon#about to write, iclass 18, count 0 2006.225.07:20:17.35#ibcon#wrote, iclass 18, count 0 2006.225.07:20:17.35#ibcon#about to read 3, iclass 18, count 0 2006.225.07:20:17.38#ibcon#read 3, iclass 18, count 0 2006.225.07:20:17.38#ibcon#about to read 4, iclass 18, count 0 2006.225.07:20:17.38#ibcon#read 4, iclass 18, count 0 2006.225.07:20:17.38#ibcon#about to read 5, iclass 18, count 0 2006.225.07:20:17.38#ibcon#read 5, iclass 18, count 0 2006.225.07:20:17.38#ibcon#about to read 6, iclass 18, count 0 2006.225.07:20:17.38#ibcon#read 6, iclass 18, count 0 2006.225.07:20:17.38#ibcon#end of sib2, iclass 18, count 0 2006.225.07:20:17.38#ibcon#*after write, iclass 18, count 0 2006.225.07:20:17.38#ibcon#*before return 0, iclass 18, count 0 2006.225.07:20:17.38#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:20:17.38#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:20:17.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:20:17.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:20:17.38$vc4f8/valo=6,772.99 2006.225.07:20:17.38#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.225.07:20:17.38#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.225.07:20:17.38#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:17.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:20:17.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:20:17.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:20:17.38#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:20:17.38#ibcon#first serial, iclass 20, count 0 2006.225.07:20:17.38#ibcon#enter sib2, iclass 20, count 0 2006.225.07:20:17.38#ibcon#flushed, iclass 20, count 0 2006.225.07:20:17.38#ibcon#about to write, iclass 20, count 0 2006.225.07:20:17.38#ibcon#wrote, iclass 20, count 0 2006.225.07:20:17.38#ibcon#about to read 3, iclass 20, count 0 2006.225.07:20:17.40#ibcon#read 3, iclass 20, count 0 2006.225.07:20:17.40#ibcon#about to read 4, iclass 20, count 0 2006.225.07:20:17.40#ibcon#read 4, iclass 20, count 0 2006.225.07:20:17.40#ibcon#about to read 5, iclass 20, count 0 2006.225.07:20:17.40#ibcon#read 5, iclass 20, count 0 2006.225.07:20:17.40#ibcon#about to read 6, iclass 20, count 0 2006.225.07:20:17.40#ibcon#read 6, iclass 20, count 0 2006.225.07:20:17.40#ibcon#end of sib2, iclass 20, count 0 2006.225.07:20:17.40#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:20:17.40#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:20:17.40#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:20:17.40#ibcon#*before write, iclass 20, count 0 2006.225.07:20:17.40#ibcon#enter sib2, iclass 20, count 0 2006.225.07:20:17.40#ibcon#flushed, iclass 20, count 0 2006.225.07:20:17.40#ibcon#about to write, iclass 20, count 0 2006.225.07:20:17.40#ibcon#wrote, iclass 20, count 0 2006.225.07:20:17.40#ibcon#about to read 3, iclass 20, count 0 2006.225.07:20:17.44#ibcon#read 3, iclass 20, count 0 2006.225.07:20:17.44#ibcon#about to read 4, iclass 20, count 0 2006.225.07:20:17.44#ibcon#read 4, iclass 20, count 0 2006.225.07:20:17.44#ibcon#about to read 5, iclass 20, count 0 2006.225.07:20:17.44#ibcon#read 5, iclass 20, count 0 2006.225.07:20:17.44#ibcon#about to read 6, iclass 20, count 0 2006.225.07:20:17.44#ibcon#read 6, iclass 20, count 0 2006.225.07:20:17.44#ibcon#end of sib2, iclass 20, count 0 2006.225.07:20:17.44#ibcon#*after write, iclass 20, count 0 2006.225.07:20:17.44#ibcon#*before return 0, iclass 20, count 0 2006.225.07:20:17.44#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:20:17.44#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:20:17.44#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:20:17.44#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:20:17.44$vc4f8/va=6,6 2006.225.07:20:17.44#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.225.07:20:17.44#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.225.07:20:17.44#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:17.44#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:20:17.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:20:17.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:20:17.50#ibcon#enter wrdev, iclass 22, count 2 2006.225.07:20:17.50#ibcon#first serial, iclass 22, count 2 2006.225.07:20:17.50#ibcon#enter sib2, iclass 22, count 2 2006.225.07:20:17.50#ibcon#flushed, iclass 22, count 2 2006.225.07:20:17.50#ibcon#about to write, iclass 22, count 2 2006.225.07:20:17.50#ibcon#wrote, iclass 22, count 2 2006.225.07:20:17.50#ibcon#about to read 3, iclass 22, count 2 2006.225.07:20:17.52#ibcon#read 3, iclass 22, count 2 2006.225.07:20:17.52#ibcon#about to read 4, iclass 22, count 2 2006.225.07:20:17.52#ibcon#read 4, iclass 22, count 2 2006.225.07:20:17.52#ibcon#about to read 5, iclass 22, count 2 2006.225.07:20:17.52#ibcon#read 5, iclass 22, count 2 2006.225.07:20:17.52#ibcon#about to read 6, iclass 22, count 2 2006.225.07:20:17.52#ibcon#read 6, iclass 22, count 2 2006.225.07:20:17.52#ibcon#end of sib2, iclass 22, count 2 2006.225.07:20:17.52#ibcon#*mode == 0, iclass 22, count 2 2006.225.07:20:17.52#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.225.07:20:17.52#ibcon#[25=AT06-06\r\n] 2006.225.07:20:17.52#ibcon#*before write, iclass 22, count 2 2006.225.07:20:17.52#ibcon#enter sib2, iclass 22, count 2 2006.225.07:20:17.52#ibcon#flushed, iclass 22, count 2 2006.225.07:20:17.52#ibcon#about to write, iclass 22, count 2 2006.225.07:20:17.52#ibcon#wrote, iclass 22, count 2 2006.225.07:20:17.52#ibcon#about to read 3, iclass 22, count 2 2006.225.07:20:17.55#ibcon#read 3, iclass 22, count 2 2006.225.07:20:17.55#ibcon#about to read 4, iclass 22, count 2 2006.225.07:20:17.55#ibcon#read 4, iclass 22, count 2 2006.225.07:20:17.55#ibcon#about to read 5, iclass 22, count 2 2006.225.07:20:17.55#ibcon#read 5, iclass 22, count 2 2006.225.07:20:17.55#ibcon#about to read 6, iclass 22, count 2 2006.225.07:20:17.55#ibcon#read 6, iclass 22, count 2 2006.225.07:20:17.55#ibcon#end of sib2, iclass 22, count 2 2006.225.07:20:17.55#ibcon#*after write, iclass 22, count 2 2006.225.07:20:17.55#ibcon#*before return 0, iclass 22, count 2 2006.225.07:20:17.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:20:17.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:20:17.55#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.225.07:20:17.55#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:17.55#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:20:17.67#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:20:17.67#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:20:17.67#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:20:17.67#ibcon#first serial, iclass 22, count 0 2006.225.07:20:17.67#ibcon#enter sib2, iclass 22, count 0 2006.225.07:20:17.67#ibcon#flushed, iclass 22, count 0 2006.225.07:20:17.67#ibcon#about to write, iclass 22, count 0 2006.225.07:20:17.67#ibcon#wrote, iclass 22, count 0 2006.225.07:20:17.67#ibcon#about to read 3, iclass 22, count 0 2006.225.07:20:17.69#ibcon#read 3, iclass 22, count 0 2006.225.07:20:17.69#ibcon#about to read 4, iclass 22, count 0 2006.225.07:20:17.69#ibcon#read 4, iclass 22, count 0 2006.225.07:20:17.69#ibcon#about to read 5, iclass 22, count 0 2006.225.07:20:17.69#ibcon#read 5, iclass 22, count 0 2006.225.07:20:17.69#ibcon#about to read 6, iclass 22, count 0 2006.225.07:20:17.69#ibcon#read 6, iclass 22, count 0 2006.225.07:20:17.69#ibcon#end of sib2, iclass 22, count 0 2006.225.07:20:17.69#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:20:17.69#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:20:17.69#ibcon#[25=USB\r\n] 2006.225.07:20:17.69#ibcon#*before write, iclass 22, count 0 2006.225.07:20:17.69#ibcon#enter sib2, iclass 22, count 0 2006.225.07:20:17.69#ibcon#flushed, iclass 22, count 0 2006.225.07:20:17.69#ibcon#about to write, iclass 22, count 0 2006.225.07:20:17.69#ibcon#wrote, iclass 22, count 0 2006.225.07:20:17.69#ibcon#about to read 3, iclass 22, count 0 2006.225.07:20:17.72#ibcon#read 3, iclass 22, count 0 2006.225.07:20:17.72#ibcon#about to read 4, iclass 22, count 0 2006.225.07:20:17.72#ibcon#read 4, iclass 22, count 0 2006.225.07:20:17.72#ibcon#about to read 5, iclass 22, count 0 2006.225.07:20:17.72#ibcon#read 5, iclass 22, count 0 2006.225.07:20:17.72#ibcon#about to read 6, iclass 22, count 0 2006.225.07:20:17.72#ibcon#read 6, iclass 22, count 0 2006.225.07:20:17.72#ibcon#end of sib2, iclass 22, count 0 2006.225.07:20:17.72#ibcon#*after write, iclass 22, count 0 2006.225.07:20:17.72#ibcon#*before return 0, iclass 22, count 0 2006.225.07:20:17.72#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:20:17.72#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:20:17.72#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:20:17.72#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:20:17.72$vc4f8/valo=7,832.99 2006.225.07:20:17.72#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.07:20:17.72#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.07:20:17.72#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:17.72#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:20:17.72#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:20:17.72#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:20:17.72#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:20:17.72#ibcon#first serial, iclass 24, count 0 2006.225.07:20:17.72#ibcon#enter sib2, iclass 24, count 0 2006.225.07:20:17.72#ibcon#flushed, iclass 24, count 0 2006.225.07:20:17.72#ibcon#about to write, iclass 24, count 0 2006.225.07:20:17.72#ibcon#wrote, iclass 24, count 0 2006.225.07:20:17.72#ibcon#about to read 3, iclass 24, count 0 2006.225.07:20:17.74#ibcon#read 3, iclass 24, count 0 2006.225.07:20:17.74#ibcon#about to read 4, iclass 24, count 0 2006.225.07:20:17.74#ibcon#read 4, iclass 24, count 0 2006.225.07:20:17.74#ibcon#about to read 5, iclass 24, count 0 2006.225.07:20:17.74#ibcon#read 5, iclass 24, count 0 2006.225.07:20:17.74#ibcon#about to read 6, iclass 24, count 0 2006.225.07:20:17.74#ibcon#read 6, iclass 24, count 0 2006.225.07:20:17.74#ibcon#end of sib2, iclass 24, count 0 2006.225.07:20:17.74#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:20:17.74#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:20:17.74#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:20:17.74#ibcon#*before write, iclass 24, count 0 2006.225.07:20:17.74#ibcon#enter sib2, iclass 24, count 0 2006.225.07:20:17.74#ibcon#flushed, iclass 24, count 0 2006.225.07:20:17.74#ibcon#about to write, iclass 24, count 0 2006.225.07:20:17.74#ibcon#wrote, iclass 24, count 0 2006.225.07:20:17.74#ibcon#about to read 3, iclass 24, count 0 2006.225.07:20:17.78#ibcon#read 3, iclass 24, count 0 2006.225.07:20:17.78#ibcon#about to read 4, iclass 24, count 0 2006.225.07:20:17.78#ibcon#read 4, iclass 24, count 0 2006.225.07:20:17.78#ibcon#about to read 5, iclass 24, count 0 2006.225.07:20:17.78#ibcon#read 5, iclass 24, count 0 2006.225.07:20:17.78#ibcon#about to read 6, iclass 24, count 0 2006.225.07:20:17.78#ibcon#read 6, iclass 24, count 0 2006.225.07:20:17.78#ibcon#end of sib2, iclass 24, count 0 2006.225.07:20:17.78#ibcon#*after write, iclass 24, count 0 2006.225.07:20:17.78#ibcon#*before return 0, iclass 24, count 0 2006.225.07:20:17.78#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:20:17.78#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:20:17.78#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:20:17.78#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:20:17.78$vc4f8/va=7,6 2006.225.07:20:17.78#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.225.07:20:17.78#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.225.07:20:17.78#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:17.78#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:20:17.84#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:20:17.84#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:20:17.84#ibcon#enter wrdev, iclass 26, count 2 2006.225.07:20:17.84#ibcon#first serial, iclass 26, count 2 2006.225.07:20:17.84#ibcon#enter sib2, iclass 26, count 2 2006.225.07:20:17.84#ibcon#flushed, iclass 26, count 2 2006.225.07:20:17.84#ibcon#about to write, iclass 26, count 2 2006.225.07:20:17.84#ibcon#wrote, iclass 26, count 2 2006.225.07:20:17.84#ibcon#about to read 3, iclass 26, count 2 2006.225.07:20:17.86#ibcon#read 3, iclass 26, count 2 2006.225.07:20:17.86#ibcon#about to read 4, iclass 26, count 2 2006.225.07:20:17.86#ibcon#read 4, iclass 26, count 2 2006.225.07:20:17.86#ibcon#about to read 5, iclass 26, count 2 2006.225.07:20:17.86#ibcon#read 5, iclass 26, count 2 2006.225.07:20:17.86#ibcon#about to read 6, iclass 26, count 2 2006.225.07:20:17.86#ibcon#read 6, iclass 26, count 2 2006.225.07:20:17.86#ibcon#end of sib2, iclass 26, count 2 2006.225.07:20:17.86#ibcon#*mode == 0, iclass 26, count 2 2006.225.07:20:17.86#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.225.07:20:17.86#ibcon#[25=AT07-06\r\n] 2006.225.07:20:17.86#ibcon#*before write, iclass 26, count 2 2006.225.07:20:17.86#ibcon#enter sib2, iclass 26, count 2 2006.225.07:20:17.86#ibcon#flushed, iclass 26, count 2 2006.225.07:20:17.86#ibcon#about to write, iclass 26, count 2 2006.225.07:20:17.86#ibcon#wrote, iclass 26, count 2 2006.225.07:20:17.86#ibcon#about to read 3, iclass 26, count 2 2006.225.07:20:17.89#ibcon#read 3, iclass 26, count 2 2006.225.07:20:17.89#ibcon#about to read 4, iclass 26, count 2 2006.225.07:20:17.89#ibcon#read 4, iclass 26, count 2 2006.225.07:20:17.89#ibcon#about to read 5, iclass 26, count 2 2006.225.07:20:17.89#ibcon#read 5, iclass 26, count 2 2006.225.07:20:17.89#ibcon#about to read 6, iclass 26, count 2 2006.225.07:20:17.89#ibcon#read 6, iclass 26, count 2 2006.225.07:20:17.89#ibcon#end of sib2, iclass 26, count 2 2006.225.07:20:17.89#ibcon#*after write, iclass 26, count 2 2006.225.07:20:17.89#ibcon#*before return 0, iclass 26, count 2 2006.225.07:20:17.89#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:20:17.89#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:20:17.89#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.225.07:20:17.89#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:17.89#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:20:18.01#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:20:18.01#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:20:18.01#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:20:18.01#ibcon#first serial, iclass 26, count 0 2006.225.07:20:18.01#ibcon#enter sib2, iclass 26, count 0 2006.225.07:20:18.01#ibcon#flushed, iclass 26, count 0 2006.225.07:20:18.01#ibcon#about to write, iclass 26, count 0 2006.225.07:20:18.01#ibcon#wrote, iclass 26, count 0 2006.225.07:20:18.01#ibcon#about to read 3, iclass 26, count 0 2006.225.07:20:18.03#ibcon#read 3, iclass 26, count 0 2006.225.07:20:18.03#ibcon#about to read 4, iclass 26, count 0 2006.225.07:20:18.03#ibcon#read 4, iclass 26, count 0 2006.225.07:20:18.03#ibcon#about to read 5, iclass 26, count 0 2006.225.07:20:18.03#ibcon#read 5, iclass 26, count 0 2006.225.07:20:18.03#ibcon#about to read 6, iclass 26, count 0 2006.225.07:20:18.03#ibcon#read 6, iclass 26, count 0 2006.225.07:20:18.03#ibcon#end of sib2, iclass 26, count 0 2006.225.07:20:18.03#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:20:18.03#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:20:18.03#ibcon#[25=USB\r\n] 2006.225.07:20:18.03#ibcon#*before write, iclass 26, count 0 2006.225.07:20:18.03#ibcon#enter sib2, iclass 26, count 0 2006.225.07:20:18.03#ibcon#flushed, iclass 26, count 0 2006.225.07:20:18.03#ibcon#about to write, iclass 26, count 0 2006.225.07:20:18.03#ibcon#wrote, iclass 26, count 0 2006.225.07:20:18.03#ibcon#about to read 3, iclass 26, count 0 2006.225.07:20:18.06#ibcon#read 3, iclass 26, count 0 2006.225.07:20:18.06#ibcon#about to read 4, iclass 26, count 0 2006.225.07:20:18.06#ibcon#read 4, iclass 26, count 0 2006.225.07:20:18.06#ibcon#about to read 5, iclass 26, count 0 2006.225.07:20:18.06#ibcon#read 5, iclass 26, count 0 2006.225.07:20:18.06#ibcon#about to read 6, iclass 26, count 0 2006.225.07:20:18.06#ibcon#read 6, iclass 26, count 0 2006.225.07:20:18.06#ibcon#end of sib2, iclass 26, count 0 2006.225.07:20:18.06#ibcon#*after write, iclass 26, count 0 2006.225.07:20:18.06#ibcon#*before return 0, iclass 26, count 0 2006.225.07:20:18.06#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:20:18.06#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:20:18.06#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:20:18.06#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:20:18.06$vc4f8/valo=8,852.99 2006.225.07:20:18.06#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.07:20:18.06#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.07:20:18.06#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:18.06#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:20:18.06#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:20:18.06#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:20:18.06#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:20:18.06#ibcon#first serial, iclass 28, count 0 2006.225.07:20:18.06#ibcon#enter sib2, iclass 28, count 0 2006.225.07:20:18.06#ibcon#flushed, iclass 28, count 0 2006.225.07:20:18.06#ibcon#about to write, iclass 28, count 0 2006.225.07:20:18.06#ibcon#wrote, iclass 28, count 0 2006.225.07:20:18.06#ibcon#about to read 3, iclass 28, count 0 2006.225.07:20:18.08#ibcon#read 3, iclass 28, count 0 2006.225.07:20:18.08#ibcon#about to read 4, iclass 28, count 0 2006.225.07:20:18.08#ibcon#read 4, iclass 28, count 0 2006.225.07:20:18.08#ibcon#about to read 5, iclass 28, count 0 2006.225.07:20:18.08#ibcon#read 5, iclass 28, count 0 2006.225.07:20:18.08#ibcon#about to read 6, iclass 28, count 0 2006.225.07:20:18.08#ibcon#read 6, iclass 28, count 0 2006.225.07:20:18.08#ibcon#end of sib2, iclass 28, count 0 2006.225.07:20:18.08#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:20:18.08#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:20:18.08#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:20:18.08#ibcon#*before write, iclass 28, count 0 2006.225.07:20:18.08#ibcon#enter sib2, iclass 28, count 0 2006.225.07:20:18.08#ibcon#flushed, iclass 28, count 0 2006.225.07:20:18.08#ibcon#about to write, iclass 28, count 0 2006.225.07:20:18.08#ibcon#wrote, iclass 28, count 0 2006.225.07:20:18.08#ibcon#about to read 3, iclass 28, count 0 2006.225.07:20:18.12#ibcon#read 3, iclass 28, count 0 2006.225.07:20:18.12#ibcon#about to read 4, iclass 28, count 0 2006.225.07:20:18.12#ibcon#read 4, iclass 28, count 0 2006.225.07:20:18.12#ibcon#about to read 5, iclass 28, count 0 2006.225.07:20:18.12#ibcon#read 5, iclass 28, count 0 2006.225.07:20:18.12#ibcon#about to read 6, iclass 28, count 0 2006.225.07:20:18.12#ibcon#read 6, iclass 28, count 0 2006.225.07:20:18.12#ibcon#end of sib2, iclass 28, count 0 2006.225.07:20:18.12#ibcon#*after write, iclass 28, count 0 2006.225.07:20:18.12#ibcon#*before return 0, iclass 28, count 0 2006.225.07:20:18.12#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:20:18.12#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:20:18.12#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:20:18.12#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:20:18.12$vc4f8/va=8,7 2006.225.07:20:18.12#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.07:20:18.12#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.07:20:18.12#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:18.12#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:20:18.18#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:20:18.18#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:20:18.18#ibcon#enter wrdev, iclass 30, count 2 2006.225.07:20:18.18#ibcon#first serial, iclass 30, count 2 2006.225.07:20:18.18#ibcon#enter sib2, iclass 30, count 2 2006.225.07:20:18.18#ibcon#flushed, iclass 30, count 2 2006.225.07:20:18.18#ibcon#about to write, iclass 30, count 2 2006.225.07:20:18.18#ibcon#wrote, iclass 30, count 2 2006.225.07:20:18.18#ibcon#about to read 3, iclass 30, count 2 2006.225.07:20:18.20#ibcon#read 3, iclass 30, count 2 2006.225.07:20:18.20#ibcon#about to read 4, iclass 30, count 2 2006.225.07:20:18.20#ibcon#read 4, iclass 30, count 2 2006.225.07:20:18.20#ibcon#about to read 5, iclass 30, count 2 2006.225.07:20:18.20#ibcon#read 5, iclass 30, count 2 2006.225.07:20:18.20#ibcon#about to read 6, iclass 30, count 2 2006.225.07:20:18.20#ibcon#read 6, iclass 30, count 2 2006.225.07:20:18.20#ibcon#end of sib2, iclass 30, count 2 2006.225.07:20:18.20#ibcon#*mode == 0, iclass 30, count 2 2006.225.07:20:18.20#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.07:20:18.20#ibcon#[25=AT08-07\r\n] 2006.225.07:20:18.20#ibcon#*before write, iclass 30, count 2 2006.225.07:20:18.20#ibcon#enter sib2, iclass 30, count 2 2006.225.07:20:18.20#ibcon#flushed, iclass 30, count 2 2006.225.07:20:18.20#ibcon#about to write, iclass 30, count 2 2006.225.07:20:18.20#ibcon#wrote, iclass 30, count 2 2006.225.07:20:18.20#ibcon#about to read 3, iclass 30, count 2 2006.225.07:20:18.23#ibcon#read 3, iclass 30, count 2 2006.225.07:20:18.23#ibcon#about to read 4, iclass 30, count 2 2006.225.07:20:18.23#ibcon#read 4, iclass 30, count 2 2006.225.07:20:18.23#ibcon#about to read 5, iclass 30, count 2 2006.225.07:20:18.23#ibcon#read 5, iclass 30, count 2 2006.225.07:20:18.23#ibcon#about to read 6, iclass 30, count 2 2006.225.07:20:18.23#ibcon#read 6, iclass 30, count 2 2006.225.07:20:18.23#ibcon#end of sib2, iclass 30, count 2 2006.225.07:20:18.23#ibcon#*after write, iclass 30, count 2 2006.225.07:20:18.23#ibcon#*before return 0, iclass 30, count 2 2006.225.07:20:18.23#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:20:18.23#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:20:18.23#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.07:20:18.23#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:18.23#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:20:18.35#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:20:18.35#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:20:18.35#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:20:18.35#ibcon#first serial, iclass 30, count 0 2006.225.07:20:18.35#ibcon#enter sib2, iclass 30, count 0 2006.225.07:20:18.35#ibcon#flushed, iclass 30, count 0 2006.225.07:20:18.35#ibcon#about to write, iclass 30, count 0 2006.225.07:20:18.35#ibcon#wrote, iclass 30, count 0 2006.225.07:20:18.35#ibcon#about to read 3, iclass 30, count 0 2006.225.07:20:18.37#ibcon#read 3, iclass 30, count 0 2006.225.07:20:18.37#ibcon#about to read 4, iclass 30, count 0 2006.225.07:20:18.37#ibcon#read 4, iclass 30, count 0 2006.225.07:20:18.37#ibcon#about to read 5, iclass 30, count 0 2006.225.07:20:18.37#ibcon#read 5, iclass 30, count 0 2006.225.07:20:18.37#ibcon#about to read 6, iclass 30, count 0 2006.225.07:20:18.37#ibcon#read 6, iclass 30, count 0 2006.225.07:20:18.37#ibcon#end of sib2, iclass 30, count 0 2006.225.07:20:18.37#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:20:18.37#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:20:18.37#ibcon#[25=USB\r\n] 2006.225.07:20:18.37#ibcon#*before write, iclass 30, count 0 2006.225.07:20:18.37#ibcon#enter sib2, iclass 30, count 0 2006.225.07:20:18.37#ibcon#flushed, iclass 30, count 0 2006.225.07:20:18.37#ibcon#about to write, iclass 30, count 0 2006.225.07:20:18.37#ibcon#wrote, iclass 30, count 0 2006.225.07:20:18.37#ibcon#about to read 3, iclass 30, count 0 2006.225.07:20:18.40#ibcon#read 3, iclass 30, count 0 2006.225.07:20:18.40#ibcon#about to read 4, iclass 30, count 0 2006.225.07:20:18.40#ibcon#read 4, iclass 30, count 0 2006.225.07:20:18.40#ibcon#about to read 5, iclass 30, count 0 2006.225.07:20:18.40#ibcon#read 5, iclass 30, count 0 2006.225.07:20:18.40#ibcon#about to read 6, iclass 30, count 0 2006.225.07:20:18.40#ibcon#read 6, iclass 30, count 0 2006.225.07:20:18.40#ibcon#end of sib2, iclass 30, count 0 2006.225.07:20:18.40#ibcon#*after write, iclass 30, count 0 2006.225.07:20:18.40#ibcon#*before return 0, iclass 30, count 0 2006.225.07:20:18.40#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:20:18.40#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:20:18.40#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:20:18.40#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:20:18.40$vc4f8/vblo=1,632.99 2006.225.07:20:18.40#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.07:20:18.40#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.07:20:18.40#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:18.40#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:20:18.40#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:20:18.40#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:20:18.40#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:20:18.40#ibcon#first serial, iclass 32, count 0 2006.225.07:20:18.40#ibcon#enter sib2, iclass 32, count 0 2006.225.07:20:18.40#ibcon#flushed, iclass 32, count 0 2006.225.07:20:18.40#ibcon#about to write, iclass 32, count 0 2006.225.07:20:18.40#ibcon#wrote, iclass 32, count 0 2006.225.07:20:18.40#ibcon#about to read 3, iclass 32, count 0 2006.225.07:20:18.42#ibcon#read 3, iclass 32, count 0 2006.225.07:20:18.42#ibcon#about to read 4, iclass 32, count 0 2006.225.07:20:18.42#ibcon#read 4, iclass 32, count 0 2006.225.07:20:18.42#ibcon#about to read 5, iclass 32, count 0 2006.225.07:20:18.42#ibcon#read 5, iclass 32, count 0 2006.225.07:20:18.42#ibcon#about to read 6, iclass 32, count 0 2006.225.07:20:18.42#ibcon#read 6, iclass 32, count 0 2006.225.07:20:18.42#ibcon#end of sib2, iclass 32, count 0 2006.225.07:20:18.42#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:20:18.42#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:20:18.42#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:20:18.42#ibcon#*before write, iclass 32, count 0 2006.225.07:20:18.42#ibcon#enter sib2, iclass 32, count 0 2006.225.07:20:18.42#ibcon#flushed, iclass 32, count 0 2006.225.07:20:18.42#ibcon#about to write, iclass 32, count 0 2006.225.07:20:18.42#ibcon#wrote, iclass 32, count 0 2006.225.07:20:18.42#ibcon#about to read 3, iclass 32, count 0 2006.225.07:20:18.46#ibcon#read 3, iclass 32, count 0 2006.225.07:20:18.46#ibcon#about to read 4, iclass 32, count 0 2006.225.07:20:18.46#ibcon#read 4, iclass 32, count 0 2006.225.07:20:18.46#ibcon#about to read 5, iclass 32, count 0 2006.225.07:20:18.46#ibcon#read 5, iclass 32, count 0 2006.225.07:20:18.46#ibcon#about to read 6, iclass 32, count 0 2006.225.07:20:18.46#ibcon#read 6, iclass 32, count 0 2006.225.07:20:18.46#ibcon#end of sib2, iclass 32, count 0 2006.225.07:20:18.46#ibcon#*after write, iclass 32, count 0 2006.225.07:20:18.46#ibcon#*before return 0, iclass 32, count 0 2006.225.07:20:18.46#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:20:18.46#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:20:18.46#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:20:18.46#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:20:18.46$vc4f8/vb=1,4 2006.225.07:20:18.46#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.07:20:18.46#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.07:20:18.46#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:18.46#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:20:18.46#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:20:18.46#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:20:18.46#ibcon#enter wrdev, iclass 34, count 2 2006.225.07:20:18.46#ibcon#first serial, iclass 34, count 2 2006.225.07:20:18.46#ibcon#enter sib2, iclass 34, count 2 2006.225.07:20:18.46#ibcon#flushed, iclass 34, count 2 2006.225.07:20:18.46#ibcon#about to write, iclass 34, count 2 2006.225.07:20:18.46#ibcon#wrote, iclass 34, count 2 2006.225.07:20:18.46#ibcon#about to read 3, iclass 34, count 2 2006.225.07:20:18.48#ibcon#read 3, iclass 34, count 2 2006.225.07:20:18.48#ibcon#about to read 4, iclass 34, count 2 2006.225.07:20:18.48#ibcon#read 4, iclass 34, count 2 2006.225.07:20:18.48#ibcon#about to read 5, iclass 34, count 2 2006.225.07:20:18.48#ibcon#read 5, iclass 34, count 2 2006.225.07:20:18.48#ibcon#about to read 6, iclass 34, count 2 2006.225.07:20:18.48#ibcon#read 6, iclass 34, count 2 2006.225.07:20:18.48#ibcon#end of sib2, iclass 34, count 2 2006.225.07:20:18.48#ibcon#*mode == 0, iclass 34, count 2 2006.225.07:20:18.48#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.07:20:18.48#ibcon#[27=AT01-04\r\n] 2006.225.07:20:18.48#ibcon#*before write, iclass 34, count 2 2006.225.07:20:18.48#ibcon#enter sib2, iclass 34, count 2 2006.225.07:20:18.48#ibcon#flushed, iclass 34, count 2 2006.225.07:20:18.48#ibcon#about to write, iclass 34, count 2 2006.225.07:20:18.48#ibcon#wrote, iclass 34, count 2 2006.225.07:20:18.48#ibcon#about to read 3, iclass 34, count 2 2006.225.07:20:18.51#ibcon#read 3, iclass 34, count 2 2006.225.07:20:18.51#ibcon#about to read 4, iclass 34, count 2 2006.225.07:20:18.51#ibcon#read 4, iclass 34, count 2 2006.225.07:20:18.51#ibcon#about to read 5, iclass 34, count 2 2006.225.07:20:18.51#ibcon#read 5, iclass 34, count 2 2006.225.07:20:18.51#ibcon#about to read 6, iclass 34, count 2 2006.225.07:20:18.51#ibcon#read 6, iclass 34, count 2 2006.225.07:20:18.51#ibcon#end of sib2, iclass 34, count 2 2006.225.07:20:18.51#ibcon#*after write, iclass 34, count 2 2006.225.07:20:18.51#ibcon#*before return 0, iclass 34, count 2 2006.225.07:20:18.51#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:20:18.51#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:20:18.51#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.07:20:18.51#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:18.51#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:20:18.63#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:20:18.63#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:20:18.63#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:20:18.63#ibcon#first serial, iclass 34, count 0 2006.225.07:20:18.63#ibcon#enter sib2, iclass 34, count 0 2006.225.07:20:18.63#ibcon#flushed, iclass 34, count 0 2006.225.07:20:18.63#ibcon#about to write, iclass 34, count 0 2006.225.07:20:18.63#ibcon#wrote, iclass 34, count 0 2006.225.07:20:18.63#ibcon#about to read 3, iclass 34, count 0 2006.225.07:20:18.65#ibcon#read 3, iclass 34, count 0 2006.225.07:20:18.65#ibcon#about to read 4, iclass 34, count 0 2006.225.07:20:18.65#ibcon#read 4, iclass 34, count 0 2006.225.07:20:18.65#ibcon#about to read 5, iclass 34, count 0 2006.225.07:20:18.65#ibcon#read 5, iclass 34, count 0 2006.225.07:20:18.65#ibcon#about to read 6, iclass 34, count 0 2006.225.07:20:18.65#ibcon#read 6, iclass 34, count 0 2006.225.07:20:18.65#ibcon#end of sib2, iclass 34, count 0 2006.225.07:20:18.65#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:20:18.65#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:20:18.65#ibcon#[27=USB\r\n] 2006.225.07:20:18.65#ibcon#*before write, iclass 34, count 0 2006.225.07:20:18.65#ibcon#enter sib2, iclass 34, count 0 2006.225.07:20:18.65#ibcon#flushed, iclass 34, count 0 2006.225.07:20:18.65#ibcon#about to write, iclass 34, count 0 2006.225.07:20:18.65#ibcon#wrote, iclass 34, count 0 2006.225.07:20:18.65#ibcon#about to read 3, iclass 34, count 0 2006.225.07:20:18.68#ibcon#read 3, iclass 34, count 0 2006.225.07:20:18.68#ibcon#about to read 4, iclass 34, count 0 2006.225.07:20:18.68#ibcon#read 4, iclass 34, count 0 2006.225.07:20:18.68#ibcon#about to read 5, iclass 34, count 0 2006.225.07:20:18.68#ibcon#read 5, iclass 34, count 0 2006.225.07:20:18.68#ibcon#about to read 6, iclass 34, count 0 2006.225.07:20:18.68#ibcon#read 6, iclass 34, count 0 2006.225.07:20:18.68#ibcon#end of sib2, iclass 34, count 0 2006.225.07:20:18.68#ibcon#*after write, iclass 34, count 0 2006.225.07:20:18.68#ibcon#*before return 0, iclass 34, count 0 2006.225.07:20:18.68#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:20:18.68#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:20:18.68#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:20:18.68#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:20:18.68$vc4f8/vblo=2,640.99 2006.225.07:20:18.68#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.07:20:18.68#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.07:20:18.68#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:18.68#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:20:18.68#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:20:18.68#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:20:18.68#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:20:18.68#ibcon#first serial, iclass 36, count 0 2006.225.07:20:18.68#ibcon#enter sib2, iclass 36, count 0 2006.225.07:20:18.68#ibcon#flushed, iclass 36, count 0 2006.225.07:20:18.68#ibcon#about to write, iclass 36, count 0 2006.225.07:20:18.68#ibcon#wrote, iclass 36, count 0 2006.225.07:20:18.68#ibcon#about to read 3, iclass 36, count 0 2006.225.07:20:18.70#ibcon#read 3, iclass 36, count 0 2006.225.07:20:18.70#ibcon#about to read 4, iclass 36, count 0 2006.225.07:20:18.70#ibcon#read 4, iclass 36, count 0 2006.225.07:20:18.70#ibcon#about to read 5, iclass 36, count 0 2006.225.07:20:18.70#ibcon#read 5, iclass 36, count 0 2006.225.07:20:18.70#ibcon#about to read 6, iclass 36, count 0 2006.225.07:20:18.70#ibcon#read 6, iclass 36, count 0 2006.225.07:20:18.70#ibcon#end of sib2, iclass 36, count 0 2006.225.07:20:18.70#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:20:18.70#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:20:18.70#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:20:18.70#ibcon#*before write, iclass 36, count 0 2006.225.07:20:18.70#ibcon#enter sib2, iclass 36, count 0 2006.225.07:20:18.70#ibcon#flushed, iclass 36, count 0 2006.225.07:20:18.70#ibcon#about to write, iclass 36, count 0 2006.225.07:20:18.70#ibcon#wrote, iclass 36, count 0 2006.225.07:20:18.70#ibcon#about to read 3, iclass 36, count 0 2006.225.07:20:18.74#ibcon#read 3, iclass 36, count 0 2006.225.07:20:18.74#ibcon#about to read 4, iclass 36, count 0 2006.225.07:20:18.74#ibcon#read 4, iclass 36, count 0 2006.225.07:20:18.74#ibcon#about to read 5, iclass 36, count 0 2006.225.07:20:18.74#ibcon#read 5, iclass 36, count 0 2006.225.07:20:18.74#ibcon#about to read 6, iclass 36, count 0 2006.225.07:20:18.74#ibcon#read 6, iclass 36, count 0 2006.225.07:20:18.74#ibcon#end of sib2, iclass 36, count 0 2006.225.07:20:18.74#ibcon#*after write, iclass 36, count 0 2006.225.07:20:18.74#ibcon#*before return 0, iclass 36, count 0 2006.225.07:20:18.74#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:20:18.74#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:20:18.74#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:20:18.74#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:20:18.74$vc4f8/vb=2,4 2006.225.07:20:18.74#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.07:20:18.74#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.07:20:18.74#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:18.74#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:20:18.80#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:20:18.80#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:20:18.80#ibcon#enter wrdev, iclass 38, count 2 2006.225.07:20:18.80#ibcon#first serial, iclass 38, count 2 2006.225.07:20:18.80#ibcon#enter sib2, iclass 38, count 2 2006.225.07:20:18.80#ibcon#flushed, iclass 38, count 2 2006.225.07:20:18.80#ibcon#about to write, iclass 38, count 2 2006.225.07:20:18.80#ibcon#wrote, iclass 38, count 2 2006.225.07:20:18.80#ibcon#about to read 3, iclass 38, count 2 2006.225.07:20:18.82#ibcon#read 3, iclass 38, count 2 2006.225.07:20:18.82#ibcon#about to read 4, iclass 38, count 2 2006.225.07:20:18.82#ibcon#read 4, iclass 38, count 2 2006.225.07:20:18.82#ibcon#about to read 5, iclass 38, count 2 2006.225.07:20:18.82#ibcon#read 5, iclass 38, count 2 2006.225.07:20:18.82#ibcon#about to read 6, iclass 38, count 2 2006.225.07:20:18.82#ibcon#read 6, iclass 38, count 2 2006.225.07:20:18.82#ibcon#end of sib2, iclass 38, count 2 2006.225.07:20:18.82#ibcon#*mode == 0, iclass 38, count 2 2006.225.07:20:18.82#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.07:20:18.82#ibcon#[27=AT02-04\r\n] 2006.225.07:20:18.82#ibcon#*before write, iclass 38, count 2 2006.225.07:20:18.82#ibcon#enter sib2, iclass 38, count 2 2006.225.07:20:18.82#ibcon#flushed, iclass 38, count 2 2006.225.07:20:18.82#ibcon#about to write, iclass 38, count 2 2006.225.07:20:18.82#ibcon#wrote, iclass 38, count 2 2006.225.07:20:18.82#ibcon#about to read 3, iclass 38, count 2 2006.225.07:20:18.85#ibcon#read 3, iclass 38, count 2 2006.225.07:20:18.85#ibcon#about to read 4, iclass 38, count 2 2006.225.07:20:18.85#ibcon#read 4, iclass 38, count 2 2006.225.07:20:18.85#ibcon#about to read 5, iclass 38, count 2 2006.225.07:20:18.85#ibcon#read 5, iclass 38, count 2 2006.225.07:20:18.85#ibcon#about to read 6, iclass 38, count 2 2006.225.07:20:18.85#ibcon#read 6, iclass 38, count 2 2006.225.07:20:18.85#ibcon#end of sib2, iclass 38, count 2 2006.225.07:20:18.85#ibcon#*after write, iclass 38, count 2 2006.225.07:20:18.85#ibcon#*before return 0, iclass 38, count 2 2006.225.07:20:18.85#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:20:18.85#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:20:18.85#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.07:20:18.85#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:18.85#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:20:18.97#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:20:18.97#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:20:18.97#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:20:18.97#ibcon#first serial, iclass 38, count 0 2006.225.07:20:18.97#ibcon#enter sib2, iclass 38, count 0 2006.225.07:20:18.97#ibcon#flushed, iclass 38, count 0 2006.225.07:20:18.97#ibcon#about to write, iclass 38, count 0 2006.225.07:20:18.97#ibcon#wrote, iclass 38, count 0 2006.225.07:20:18.97#ibcon#about to read 3, iclass 38, count 0 2006.225.07:20:18.99#ibcon#read 3, iclass 38, count 0 2006.225.07:20:18.99#ibcon#about to read 4, iclass 38, count 0 2006.225.07:20:18.99#ibcon#read 4, iclass 38, count 0 2006.225.07:20:18.99#ibcon#about to read 5, iclass 38, count 0 2006.225.07:20:18.99#ibcon#read 5, iclass 38, count 0 2006.225.07:20:18.99#ibcon#about to read 6, iclass 38, count 0 2006.225.07:20:18.99#ibcon#read 6, iclass 38, count 0 2006.225.07:20:18.99#ibcon#end of sib2, iclass 38, count 0 2006.225.07:20:18.99#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:20:18.99#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:20:18.99#ibcon#[27=USB\r\n] 2006.225.07:20:18.99#ibcon#*before write, iclass 38, count 0 2006.225.07:20:18.99#ibcon#enter sib2, iclass 38, count 0 2006.225.07:20:18.99#ibcon#flushed, iclass 38, count 0 2006.225.07:20:18.99#ibcon#about to write, iclass 38, count 0 2006.225.07:20:18.99#ibcon#wrote, iclass 38, count 0 2006.225.07:20:18.99#ibcon#about to read 3, iclass 38, count 0 2006.225.07:20:19.02#ibcon#read 3, iclass 38, count 0 2006.225.07:20:19.02#ibcon#about to read 4, iclass 38, count 0 2006.225.07:20:19.02#ibcon#read 4, iclass 38, count 0 2006.225.07:20:19.02#ibcon#about to read 5, iclass 38, count 0 2006.225.07:20:19.02#ibcon#read 5, iclass 38, count 0 2006.225.07:20:19.02#ibcon#about to read 6, iclass 38, count 0 2006.225.07:20:19.02#ibcon#read 6, iclass 38, count 0 2006.225.07:20:19.02#ibcon#end of sib2, iclass 38, count 0 2006.225.07:20:19.02#ibcon#*after write, iclass 38, count 0 2006.225.07:20:19.02#ibcon#*before return 0, iclass 38, count 0 2006.225.07:20:19.02#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:20:19.02#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:20:19.02#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:20:19.02#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:20:19.02$vc4f8/vblo=3,656.99 2006.225.07:20:19.02#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.07:20:19.02#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.07:20:19.02#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:19.02#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:20:19.02#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:20:19.02#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:20:19.02#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:20:19.02#ibcon#first serial, iclass 40, count 0 2006.225.07:20:19.02#ibcon#enter sib2, iclass 40, count 0 2006.225.07:20:19.02#ibcon#flushed, iclass 40, count 0 2006.225.07:20:19.02#ibcon#about to write, iclass 40, count 0 2006.225.07:20:19.02#ibcon#wrote, iclass 40, count 0 2006.225.07:20:19.02#ibcon#about to read 3, iclass 40, count 0 2006.225.07:20:19.04#ibcon#read 3, iclass 40, count 0 2006.225.07:20:19.04#ibcon#about to read 4, iclass 40, count 0 2006.225.07:20:19.04#ibcon#read 4, iclass 40, count 0 2006.225.07:20:19.04#ibcon#about to read 5, iclass 40, count 0 2006.225.07:20:19.04#ibcon#read 5, iclass 40, count 0 2006.225.07:20:19.04#ibcon#about to read 6, iclass 40, count 0 2006.225.07:20:19.04#ibcon#read 6, iclass 40, count 0 2006.225.07:20:19.04#ibcon#end of sib2, iclass 40, count 0 2006.225.07:20:19.04#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:20:19.04#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:20:19.04#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:20:19.04#ibcon#*before write, iclass 40, count 0 2006.225.07:20:19.04#ibcon#enter sib2, iclass 40, count 0 2006.225.07:20:19.04#ibcon#flushed, iclass 40, count 0 2006.225.07:20:19.04#ibcon#about to write, iclass 40, count 0 2006.225.07:20:19.04#ibcon#wrote, iclass 40, count 0 2006.225.07:20:19.04#ibcon#about to read 3, iclass 40, count 0 2006.225.07:20:19.08#ibcon#read 3, iclass 40, count 0 2006.225.07:20:19.08#ibcon#about to read 4, iclass 40, count 0 2006.225.07:20:19.08#ibcon#read 4, iclass 40, count 0 2006.225.07:20:19.08#ibcon#about to read 5, iclass 40, count 0 2006.225.07:20:19.08#ibcon#read 5, iclass 40, count 0 2006.225.07:20:19.08#ibcon#about to read 6, iclass 40, count 0 2006.225.07:20:19.08#ibcon#read 6, iclass 40, count 0 2006.225.07:20:19.08#ibcon#end of sib2, iclass 40, count 0 2006.225.07:20:19.08#ibcon#*after write, iclass 40, count 0 2006.225.07:20:19.08#ibcon#*before return 0, iclass 40, count 0 2006.225.07:20:19.08#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:20:19.08#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:20:19.08#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:20:19.08#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:20:19.08$vc4f8/vb=3,4 2006.225.07:20:19.08#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.07:20:19.08#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.07:20:19.08#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:19.08#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:20:19.14#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:20:19.14#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:20:19.14#ibcon#enter wrdev, iclass 4, count 2 2006.225.07:20:19.14#ibcon#first serial, iclass 4, count 2 2006.225.07:20:19.14#ibcon#enter sib2, iclass 4, count 2 2006.225.07:20:19.14#ibcon#flushed, iclass 4, count 2 2006.225.07:20:19.14#ibcon#about to write, iclass 4, count 2 2006.225.07:20:19.14#ibcon#wrote, iclass 4, count 2 2006.225.07:20:19.14#ibcon#about to read 3, iclass 4, count 2 2006.225.07:20:19.16#ibcon#read 3, iclass 4, count 2 2006.225.07:20:19.16#ibcon#about to read 4, iclass 4, count 2 2006.225.07:20:19.16#ibcon#read 4, iclass 4, count 2 2006.225.07:20:19.16#ibcon#about to read 5, iclass 4, count 2 2006.225.07:20:19.16#ibcon#read 5, iclass 4, count 2 2006.225.07:20:19.16#ibcon#about to read 6, iclass 4, count 2 2006.225.07:20:19.16#ibcon#read 6, iclass 4, count 2 2006.225.07:20:19.16#ibcon#end of sib2, iclass 4, count 2 2006.225.07:20:19.16#ibcon#*mode == 0, iclass 4, count 2 2006.225.07:20:19.16#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.07:20:19.16#ibcon#[27=AT03-04\r\n] 2006.225.07:20:19.16#ibcon#*before write, iclass 4, count 2 2006.225.07:20:19.16#ibcon#enter sib2, iclass 4, count 2 2006.225.07:20:19.16#ibcon#flushed, iclass 4, count 2 2006.225.07:20:19.16#ibcon#about to write, iclass 4, count 2 2006.225.07:20:19.16#ibcon#wrote, iclass 4, count 2 2006.225.07:20:19.16#ibcon#about to read 3, iclass 4, count 2 2006.225.07:20:19.19#ibcon#read 3, iclass 4, count 2 2006.225.07:20:19.19#ibcon#about to read 4, iclass 4, count 2 2006.225.07:20:19.19#ibcon#read 4, iclass 4, count 2 2006.225.07:20:19.19#ibcon#about to read 5, iclass 4, count 2 2006.225.07:20:19.19#ibcon#read 5, iclass 4, count 2 2006.225.07:20:19.19#ibcon#about to read 6, iclass 4, count 2 2006.225.07:20:19.19#ibcon#read 6, iclass 4, count 2 2006.225.07:20:19.19#ibcon#end of sib2, iclass 4, count 2 2006.225.07:20:19.19#ibcon#*after write, iclass 4, count 2 2006.225.07:20:19.19#ibcon#*before return 0, iclass 4, count 2 2006.225.07:20:19.19#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:20:19.19#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:20:19.19#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.07:20:19.19#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:19.19#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:20:19.31#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:20:19.31#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:20:19.31#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:20:19.31#ibcon#first serial, iclass 4, count 0 2006.225.07:20:19.31#ibcon#enter sib2, iclass 4, count 0 2006.225.07:20:19.31#ibcon#flushed, iclass 4, count 0 2006.225.07:20:19.31#ibcon#about to write, iclass 4, count 0 2006.225.07:20:19.31#ibcon#wrote, iclass 4, count 0 2006.225.07:20:19.31#ibcon#about to read 3, iclass 4, count 0 2006.225.07:20:19.33#ibcon#read 3, iclass 4, count 0 2006.225.07:20:19.33#ibcon#about to read 4, iclass 4, count 0 2006.225.07:20:19.33#ibcon#read 4, iclass 4, count 0 2006.225.07:20:19.33#ibcon#about to read 5, iclass 4, count 0 2006.225.07:20:19.33#ibcon#read 5, iclass 4, count 0 2006.225.07:20:19.33#ibcon#about to read 6, iclass 4, count 0 2006.225.07:20:19.33#ibcon#read 6, iclass 4, count 0 2006.225.07:20:19.33#ibcon#end of sib2, iclass 4, count 0 2006.225.07:20:19.33#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:20:19.33#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:20:19.33#ibcon#[27=USB\r\n] 2006.225.07:20:19.33#ibcon#*before write, iclass 4, count 0 2006.225.07:20:19.33#ibcon#enter sib2, iclass 4, count 0 2006.225.07:20:19.33#ibcon#flushed, iclass 4, count 0 2006.225.07:20:19.33#ibcon#about to write, iclass 4, count 0 2006.225.07:20:19.33#ibcon#wrote, iclass 4, count 0 2006.225.07:20:19.33#ibcon#about to read 3, iclass 4, count 0 2006.225.07:20:19.36#ibcon#read 3, iclass 4, count 0 2006.225.07:20:19.36#ibcon#about to read 4, iclass 4, count 0 2006.225.07:20:19.36#ibcon#read 4, iclass 4, count 0 2006.225.07:20:19.36#ibcon#about to read 5, iclass 4, count 0 2006.225.07:20:19.36#ibcon#read 5, iclass 4, count 0 2006.225.07:20:19.36#ibcon#about to read 6, iclass 4, count 0 2006.225.07:20:19.36#ibcon#read 6, iclass 4, count 0 2006.225.07:20:19.36#ibcon#end of sib2, iclass 4, count 0 2006.225.07:20:19.36#ibcon#*after write, iclass 4, count 0 2006.225.07:20:19.36#ibcon#*before return 0, iclass 4, count 0 2006.225.07:20:19.36#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:20:19.36#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:20:19.36#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:20:19.36#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:20:19.36$vc4f8/vblo=4,712.99 2006.225.07:20:19.36#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.07:20:19.36#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.07:20:19.36#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:19.36#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:20:19.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:20:19.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:20:19.36#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:20:19.36#ibcon#first serial, iclass 6, count 0 2006.225.07:20:19.36#ibcon#enter sib2, iclass 6, count 0 2006.225.07:20:19.36#ibcon#flushed, iclass 6, count 0 2006.225.07:20:19.36#ibcon#about to write, iclass 6, count 0 2006.225.07:20:19.36#ibcon#wrote, iclass 6, count 0 2006.225.07:20:19.36#ibcon#about to read 3, iclass 6, count 0 2006.225.07:20:19.38#ibcon#read 3, iclass 6, count 0 2006.225.07:20:19.38#ibcon#about to read 4, iclass 6, count 0 2006.225.07:20:19.38#ibcon#read 4, iclass 6, count 0 2006.225.07:20:19.38#ibcon#about to read 5, iclass 6, count 0 2006.225.07:20:19.38#ibcon#read 5, iclass 6, count 0 2006.225.07:20:19.38#ibcon#about to read 6, iclass 6, count 0 2006.225.07:20:19.38#ibcon#read 6, iclass 6, count 0 2006.225.07:20:19.38#ibcon#end of sib2, iclass 6, count 0 2006.225.07:20:19.38#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:20:19.38#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:20:19.38#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:20:19.38#ibcon#*before write, iclass 6, count 0 2006.225.07:20:19.38#ibcon#enter sib2, iclass 6, count 0 2006.225.07:20:19.38#ibcon#flushed, iclass 6, count 0 2006.225.07:20:19.38#ibcon#about to write, iclass 6, count 0 2006.225.07:20:19.38#ibcon#wrote, iclass 6, count 0 2006.225.07:20:19.38#ibcon#about to read 3, iclass 6, count 0 2006.225.07:20:19.42#ibcon#read 3, iclass 6, count 0 2006.225.07:20:19.42#ibcon#about to read 4, iclass 6, count 0 2006.225.07:20:19.42#ibcon#read 4, iclass 6, count 0 2006.225.07:20:19.42#ibcon#about to read 5, iclass 6, count 0 2006.225.07:20:19.42#ibcon#read 5, iclass 6, count 0 2006.225.07:20:19.42#ibcon#about to read 6, iclass 6, count 0 2006.225.07:20:19.42#ibcon#read 6, iclass 6, count 0 2006.225.07:20:19.42#ibcon#end of sib2, iclass 6, count 0 2006.225.07:20:19.42#ibcon#*after write, iclass 6, count 0 2006.225.07:20:19.42#ibcon#*before return 0, iclass 6, count 0 2006.225.07:20:19.42#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:20:19.42#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:20:19.42#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:20:19.42#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:20:19.42$vc4f8/vb=4,4 2006.225.07:20:19.42#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.225.07:20:19.42#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.225.07:20:19.42#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:19.42#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:20:19.48#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:20:19.48#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:20:19.48#ibcon#enter wrdev, iclass 10, count 2 2006.225.07:20:19.48#ibcon#first serial, iclass 10, count 2 2006.225.07:20:19.48#ibcon#enter sib2, iclass 10, count 2 2006.225.07:20:19.48#ibcon#flushed, iclass 10, count 2 2006.225.07:20:19.48#ibcon#about to write, iclass 10, count 2 2006.225.07:20:19.48#ibcon#wrote, iclass 10, count 2 2006.225.07:20:19.48#ibcon#about to read 3, iclass 10, count 2 2006.225.07:20:19.50#ibcon#read 3, iclass 10, count 2 2006.225.07:20:19.50#ibcon#about to read 4, iclass 10, count 2 2006.225.07:20:19.50#ibcon#read 4, iclass 10, count 2 2006.225.07:20:19.50#ibcon#about to read 5, iclass 10, count 2 2006.225.07:20:19.50#ibcon#read 5, iclass 10, count 2 2006.225.07:20:19.50#ibcon#about to read 6, iclass 10, count 2 2006.225.07:20:19.50#ibcon#read 6, iclass 10, count 2 2006.225.07:20:19.50#ibcon#end of sib2, iclass 10, count 2 2006.225.07:20:19.50#ibcon#*mode == 0, iclass 10, count 2 2006.225.07:20:19.50#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.225.07:20:19.50#ibcon#[27=AT04-04\r\n] 2006.225.07:20:19.50#ibcon#*before write, iclass 10, count 2 2006.225.07:20:19.50#ibcon#enter sib2, iclass 10, count 2 2006.225.07:20:19.50#ibcon#flushed, iclass 10, count 2 2006.225.07:20:19.50#ibcon#about to write, iclass 10, count 2 2006.225.07:20:19.50#ibcon#wrote, iclass 10, count 2 2006.225.07:20:19.50#ibcon#about to read 3, iclass 10, count 2 2006.225.07:20:19.53#ibcon#read 3, iclass 10, count 2 2006.225.07:20:19.53#ibcon#about to read 4, iclass 10, count 2 2006.225.07:20:19.53#ibcon#read 4, iclass 10, count 2 2006.225.07:20:19.53#ibcon#about to read 5, iclass 10, count 2 2006.225.07:20:19.53#ibcon#read 5, iclass 10, count 2 2006.225.07:20:19.53#ibcon#about to read 6, iclass 10, count 2 2006.225.07:20:19.53#ibcon#read 6, iclass 10, count 2 2006.225.07:20:19.53#ibcon#end of sib2, iclass 10, count 2 2006.225.07:20:19.53#ibcon#*after write, iclass 10, count 2 2006.225.07:20:19.53#ibcon#*before return 0, iclass 10, count 2 2006.225.07:20:19.53#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:20:19.53#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:20:19.53#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.225.07:20:19.53#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:19.53#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:20:19.65#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:20:19.65#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:20:19.65#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:20:19.65#ibcon#first serial, iclass 10, count 0 2006.225.07:20:19.65#ibcon#enter sib2, iclass 10, count 0 2006.225.07:20:19.65#ibcon#flushed, iclass 10, count 0 2006.225.07:20:19.65#ibcon#about to write, iclass 10, count 0 2006.225.07:20:19.65#ibcon#wrote, iclass 10, count 0 2006.225.07:20:19.65#ibcon#about to read 3, iclass 10, count 0 2006.225.07:20:19.67#ibcon#read 3, iclass 10, count 0 2006.225.07:20:19.67#ibcon#about to read 4, iclass 10, count 0 2006.225.07:20:19.67#ibcon#read 4, iclass 10, count 0 2006.225.07:20:19.67#ibcon#about to read 5, iclass 10, count 0 2006.225.07:20:19.67#ibcon#read 5, iclass 10, count 0 2006.225.07:20:19.67#ibcon#about to read 6, iclass 10, count 0 2006.225.07:20:19.67#ibcon#read 6, iclass 10, count 0 2006.225.07:20:19.67#ibcon#end of sib2, iclass 10, count 0 2006.225.07:20:19.67#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:20:19.67#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:20:19.67#ibcon#[27=USB\r\n] 2006.225.07:20:19.67#ibcon#*before write, iclass 10, count 0 2006.225.07:20:19.67#ibcon#enter sib2, iclass 10, count 0 2006.225.07:20:19.67#ibcon#flushed, iclass 10, count 0 2006.225.07:20:19.67#ibcon#about to write, iclass 10, count 0 2006.225.07:20:19.67#ibcon#wrote, iclass 10, count 0 2006.225.07:20:19.67#ibcon#about to read 3, iclass 10, count 0 2006.225.07:20:19.70#ibcon#read 3, iclass 10, count 0 2006.225.07:20:19.70#ibcon#about to read 4, iclass 10, count 0 2006.225.07:20:19.70#ibcon#read 4, iclass 10, count 0 2006.225.07:20:19.70#ibcon#about to read 5, iclass 10, count 0 2006.225.07:20:19.70#ibcon#read 5, iclass 10, count 0 2006.225.07:20:19.70#ibcon#about to read 6, iclass 10, count 0 2006.225.07:20:19.70#ibcon#read 6, iclass 10, count 0 2006.225.07:20:19.70#ibcon#end of sib2, iclass 10, count 0 2006.225.07:20:19.70#ibcon#*after write, iclass 10, count 0 2006.225.07:20:19.70#ibcon#*before return 0, iclass 10, count 0 2006.225.07:20:19.70#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:20:19.70#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:20:19.70#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:20:19.70#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:20:19.70$vc4f8/vblo=5,744.99 2006.225.07:20:19.70#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.07:20:19.70#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.07:20:19.70#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:19.70#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:20:19.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:20:19.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:20:19.70#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:20:19.70#ibcon#first serial, iclass 12, count 0 2006.225.07:20:19.70#ibcon#enter sib2, iclass 12, count 0 2006.225.07:20:19.70#ibcon#flushed, iclass 12, count 0 2006.225.07:20:19.70#ibcon#about to write, iclass 12, count 0 2006.225.07:20:19.70#ibcon#wrote, iclass 12, count 0 2006.225.07:20:19.70#ibcon#about to read 3, iclass 12, count 0 2006.225.07:20:19.72#ibcon#read 3, iclass 12, count 0 2006.225.07:20:19.72#ibcon#about to read 4, iclass 12, count 0 2006.225.07:20:19.72#ibcon#read 4, iclass 12, count 0 2006.225.07:20:19.72#ibcon#about to read 5, iclass 12, count 0 2006.225.07:20:19.72#ibcon#read 5, iclass 12, count 0 2006.225.07:20:19.72#ibcon#about to read 6, iclass 12, count 0 2006.225.07:20:19.72#ibcon#read 6, iclass 12, count 0 2006.225.07:20:19.72#ibcon#end of sib2, iclass 12, count 0 2006.225.07:20:19.72#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:20:19.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:20:19.72#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:20:19.72#ibcon#*before write, iclass 12, count 0 2006.225.07:20:19.72#ibcon#enter sib2, iclass 12, count 0 2006.225.07:20:19.72#ibcon#flushed, iclass 12, count 0 2006.225.07:20:19.72#ibcon#about to write, iclass 12, count 0 2006.225.07:20:19.72#ibcon#wrote, iclass 12, count 0 2006.225.07:20:19.72#ibcon#about to read 3, iclass 12, count 0 2006.225.07:20:19.76#ibcon#read 3, iclass 12, count 0 2006.225.07:20:19.76#ibcon#about to read 4, iclass 12, count 0 2006.225.07:20:19.76#ibcon#read 4, iclass 12, count 0 2006.225.07:20:19.76#ibcon#about to read 5, iclass 12, count 0 2006.225.07:20:19.76#ibcon#read 5, iclass 12, count 0 2006.225.07:20:19.76#ibcon#about to read 6, iclass 12, count 0 2006.225.07:20:19.76#ibcon#read 6, iclass 12, count 0 2006.225.07:20:19.76#ibcon#end of sib2, iclass 12, count 0 2006.225.07:20:19.76#ibcon#*after write, iclass 12, count 0 2006.225.07:20:19.76#ibcon#*before return 0, iclass 12, count 0 2006.225.07:20:19.76#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:20:19.76#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:20:19.76#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:20:19.76#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:20:19.76$vc4f8/vb=5,4 2006.225.07:20:19.76#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.225.07:20:19.76#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.225.07:20:19.76#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:19.76#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:20:19.82#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:20:19.82#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:20:19.82#ibcon#enter wrdev, iclass 14, count 2 2006.225.07:20:19.82#ibcon#first serial, iclass 14, count 2 2006.225.07:20:19.82#ibcon#enter sib2, iclass 14, count 2 2006.225.07:20:19.82#ibcon#flushed, iclass 14, count 2 2006.225.07:20:19.82#ibcon#about to write, iclass 14, count 2 2006.225.07:20:19.82#ibcon#wrote, iclass 14, count 2 2006.225.07:20:19.82#ibcon#about to read 3, iclass 14, count 2 2006.225.07:20:19.84#ibcon#read 3, iclass 14, count 2 2006.225.07:20:19.84#ibcon#about to read 4, iclass 14, count 2 2006.225.07:20:19.84#ibcon#read 4, iclass 14, count 2 2006.225.07:20:19.84#ibcon#about to read 5, iclass 14, count 2 2006.225.07:20:19.84#ibcon#read 5, iclass 14, count 2 2006.225.07:20:19.84#ibcon#about to read 6, iclass 14, count 2 2006.225.07:20:19.84#ibcon#read 6, iclass 14, count 2 2006.225.07:20:19.84#ibcon#end of sib2, iclass 14, count 2 2006.225.07:20:19.84#ibcon#*mode == 0, iclass 14, count 2 2006.225.07:20:19.84#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.225.07:20:19.84#ibcon#[27=AT05-04\r\n] 2006.225.07:20:19.84#ibcon#*before write, iclass 14, count 2 2006.225.07:20:19.84#ibcon#enter sib2, iclass 14, count 2 2006.225.07:20:19.84#ibcon#flushed, iclass 14, count 2 2006.225.07:20:19.84#ibcon#about to write, iclass 14, count 2 2006.225.07:20:19.84#ibcon#wrote, iclass 14, count 2 2006.225.07:20:19.84#ibcon#about to read 3, iclass 14, count 2 2006.225.07:20:19.87#ibcon#read 3, iclass 14, count 2 2006.225.07:20:19.87#ibcon#about to read 4, iclass 14, count 2 2006.225.07:20:19.87#ibcon#read 4, iclass 14, count 2 2006.225.07:20:19.87#ibcon#about to read 5, iclass 14, count 2 2006.225.07:20:19.87#ibcon#read 5, iclass 14, count 2 2006.225.07:20:19.87#ibcon#about to read 6, iclass 14, count 2 2006.225.07:20:19.87#ibcon#read 6, iclass 14, count 2 2006.225.07:20:19.87#ibcon#end of sib2, iclass 14, count 2 2006.225.07:20:19.87#ibcon#*after write, iclass 14, count 2 2006.225.07:20:19.87#ibcon#*before return 0, iclass 14, count 2 2006.225.07:20:19.87#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:20:19.87#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:20:19.87#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.225.07:20:19.87#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:19.87#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:20:19.99#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:20:19.99#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:20:19.99#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:20:19.99#ibcon#first serial, iclass 14, count 0 2006.225.07:20:19.99#ibcon#enter sib2, iclass 14, count 0 2006.225.07:20:19.99#ibcon#flushed, iclass 14, count 0 2006.225.07:20:19.99#ibcon#about to write, iclass 14, count 0 2006.225.07:20:19.99#ibcon#wrote, iclass 14, count 0 2006.225.07:20:19.99#ibcon#about to read 3, iclass 14, count 0 2006.225.07:20:20.01#ibcon#read 3, iclass 14, count 0 2006.225.07:20:20.01#ibcon#about to read 4, iclass 14, count 0 2006.225.07:20:20.01#ibcon#read 4, iclass 14, count 0 2006.225.07:20:20.01#ibcon#about to read 5, iclass 14, count 0 2006.225.07:20:20.01#ibcon#read 5, iclass 14, count 0 2006.225.07:20:20.01#ibcon#about to read 6, iclass 14, count 0 2006.225.07:20:20.01#ibcon#read 6, iclass 14, count 0 2006.225.07:20:20.01#ibcon#end of sib2, iclass 14, count 0 2006.225.07:20:20.01#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:20:20.01#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:20:20.01#ibcon#[27=USB\r\n] 2006.225.07:20:20.01#ibcon#*before write, iclass 14, count 0 2006.225.07:20:20.01#ibcon#enter sib2, iclass 14, count 0 2006.225.07:20:20.01#ibcon#flushed, iclass 14, count 0 2006.225.07:20:20.01#ibcon#about to write, iclass 14, count 0 2006.225.07:20:20.01#ibcon#wrote, iclass 14, count 0 2006.225.07:20:20.01#ibcon#about to read 3, iclass 14, count 0 2006.225.07:20:20.04#ibcon#read 3, iclass 14, count 0 2006.225.07:20:20.04#ibcon#about to read 4, iclass 14, count 0 2006.225.07:20:20.04#ibcon#read 4, iclass 14, count 0 2006.225.07:20:20.04#ibcon#about to read 5, iclass 14, count 0 2006.225.07:20:20.04#ibcon#read 5, iclass 14, count 0 2006.225.07:20:20.04#ibcon#about to read 6, iclass 14, count 0 2006.225.07:20:20.04#ibcon#read 6, iclass 14, count 0 2006.225.07:20:20.04#ibcon#end of sib2, iclass 14, count 0 2006.225.07:20:20.04#ibcon#*after write, iclass 14, count 0 2006.225.07:20:20.04#ibcon#*before return 0, iclass 14, count 0 2006.225.07:20:20.04#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:20:20.04#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:20:20.04#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:20:20.04#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:20:20.04$vc4f8/vblo=6,752.99 2006.225.07:20:20.04#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.07:20:20.04#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.07:20:20.04#ibcon#ireg 17 cls_cnt 0 2006.225.07:20:20.04#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:20:20.04#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:20:20.04#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:20:20.04#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:20:20.04#ibcon#first serial, iclass 16, count 0 2006.225.07:20:20.04#ibcon#enter sib2, iclass 16, count 0 2006.225.07:20:20.04#ibcon#flushed, iclass 16, count 0 2006.225.07:20:20.04#ibcon#about to write, iclass 16, count 0 2006.225.07:20:20.04#ibcon#wrote, iclass 16, count 0 2006.225.07:20:20.04#ibcon#about to read 3, iclass 16, count 0 2006.225.07:20:20.06#ibcon#read 3, iclass 16, count 0 2006.225.07:20:20.06#ibcon#about to read 4, iclass 16, count 0 2006.225.07:20:20.06#ibcon#read 4, iclass 16, count 0 2006.225.07:20:20.06#ibcon#about to read 5, iclass 16, count 0 2006.225.07:20:20.06#ibcon#read 5, iclass 16, count 0 2006.225.07:20:20.06#ibcon#about to read 6, iclass 16, count 0 2006.225.07:20:20.06#ibcon#read 6, iclass 16, count 0 2006.225.07:20:20.06#ibcon#end of sib2, iclass 16, count 0 2006.225.07:20:20.06#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:20:20.06#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:20:20.06#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:20:20.06#ibcon#*before write, iclass 16, count 0 2006.225.07:20:20.06#ibcon#enter sib2, iclass 16, count 0 2006.225.07:20:20.06#ibcon#flushed, iclass 16, count 0 2006.225.07:20:20.06#ibcon#about to write, iclass 16, count 0 2006.225.07:20:20.06#ibcon#wrote, iclass 16, count 0 2006.225.07:20:20.06#ibcon#about to read 3, iclass 16, count 0 2006.225.07:20:20.10#ibcon#read 3, iclass 16, count 0 2006.225.07:20:20.10#ibcon#about to read 4, iclass 16, count 0 2006.225.07:20:20.10#ibcon#read 4, iclass 16, count 0 2006.225.07:20:20.10#ibcon#about to read 5, iclass 16, count 0 2006.225.07:20:20.10#ibcon#read 5, iclass 16, count 0 2006.225.07:20:20.10#ibcon#about to read 6, iclass 16, count 0 2006.225.07:20:20.10#ibcon#read 6, iclass 16, count 0 2006.225.07:20:20.10#ibcon#end of sib2, iclass 16, count 0 2006.225.07:20:20.10#ibcon#*after write, iclass 16, count 0 2006.225.07:20:20.10#ibcon#*before return 0, iclass 16, count 0 2006.225.07:20:20.10#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:20:20.10#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:20:20.10#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:20:20.10#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:20:20.10$vc4f8/vb=6,4 2006.225.07:20:20.10#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.225.07:20:20.10#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.225.07:20:20.10#ibcon#ireg 11 cls_cnt 2 2006.225.07:20:20.10#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:20:20.16#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:20:20.16#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:20:20.16#ibcon#enter wrdev, iclass 18, count 2 2006.225.07:20:20.16#ibcon#first serial, iclass 18, count 2 2006.225.07:20:20.16#ibcon#enter sib2, iclass 18, count 2 2006.225.07:20:20.16#ibcon#flushed, iclass 18, count 2 2006.225.07:20:20.16#ibcon#about to write, iclass 18, count 2 2006.225.07:20:20.16#ibcon#wrote, iclass 18, count 2 2006.225.07:20:20.16#ibcon#about to read 3, iclass 18, count 2 2006.225.07:20:20.18#ibcon#read 3, iclass 18, count 2 2006.225.07:20:20.18#ibcon#about to read 4, iclass 18, count 2 2006.225.07:20:20.18#ibcon#read 4, iclass 18, count 2 2006.225.07:20:20.18#ibcon#about to read 5, iclass 18, count 2 2006.225.07:20:20.18#ibcon#read 5, iclass 18, count 2 2006.225.07:20:20.18#ibcon#about to read 6, iclass 18, count 2 2006.225.07:20:20.18#ibcon#read 6, iclass 18, count 2 2006.225.07:20:20.18#ibcon#end of sib2, iclass 18, count 2 2006.225.07:20:20.18#ibcon#*mode == 0, iclass 18, count 2 2006.225.07:20:20.18#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.225.07:20:20.18#ibcon#[27=AT06-04\r\n] 2006.225.07:20:20.18#ibcon#*before write, iclass 18, count 2 2006.225.07:20:20.18#ibcon#enter sib2, iclass 18, count 2 2006.225.07:20:20.18#ibcon#flushed, iclass 18, count 2 2006.225.07:20:20.18#ibcon#about to write, iclass 18, count 2 2006.225.07:20:20.18#ibcon#wrote, iclass 18, count 2 2006.225.07:20:20.18#ibcon#about to read 3, iclass 18, count 2 2006.225.07:20:20.21#ibcon#read 3, iclass 18, count 2 2006.225.07:20:20.21#ibcon#about to read 4, iclass 18, count 2 2006.225.07:20:20.21#ibcon#read 4, iclass 18, count 2 2006.225.07:20:20.21#ibcon#about to read 5, iclass 18, count 2 2006.225.07:20:20.21#ibcon#read 5, iclass 18, count 2 2006.225.07:20:20.21#ibcon#about to read 6, iclass 18, count 2 2006.225.07:20:20.21#ibcon#read 6, iclass 18, count 2 2006.225.07:20:20.21#ibcon#end of sib2, iclass 18, count 2 2006.225.07:20:20.21#ibcon#*after write, iclass 18, count 2 2006.225.07:20:20.21#ibcon#*before return 0, iclass 18, count 2 2006.225.07:20:20.21#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:20:20.21#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:20:20.21#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.225.07:20:20.21#ibcon#ireg 7 cls_cnt 0 2006.225.07:20:20.21#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:20:20.33#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:20:20.33#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:20:20.33#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:20:20.33#ibcon#first serial, iclass 18, count 0 2006.225.07:20:20.33#ibcon#enter sib2, iclass 18, count 0 2006.225.07:20:20.33#ibcon#flushed, iclass 18, count 0 2006.225.07:20:20.33#ibcon#about to write, iclass 18, count 0 2006.225.07:20:20.33#ibcon#wrote, iclass 18, count 0 2006.225.07:20:20.33#ibcon#about to read 3, iclass 18, count 0 2006.225.07:20:20.35#ibcon#read 3, iclass 18, count 0 2006.225.07:20:20.35#ibcon#about to read 4, iclass 18, count 0 2006.225.07:20:20.35#ibcon#read 4, iclass 18, count 0 2006.225.07:20:20.35#ibcon#about to read 5, iclass 18, count 0 2006.225.07:20:20.35#ibcon#read 5, iclass 18, count 0 2006.225.07:20:20.35#ibcon#about to read 6, iclass 18, count 0 2006.225.07:20:20.35#ibcon#read 6, iclass 18, count 0 2006.225.07:20:20.35#ibcon#end of sib2, iclass 18, count 0 2006.225.07:20:20.35#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:20:20.35#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:20:20.35#ibcon#[27=USB\r\n] 2006.225.07:20:20.35#ibcon#*before write, iclass 18, count 0 2006.225.07:20:20.35#ibcon#enter sib2, iclass 18, count 0 2006.225.07:20:20.35#ibcon#flushed, iclass 18, count 0 2006.225.07:20:20.35#ibcon#about to write, iclass 18, count 0 2006.225.07:20:20.35#ibcon#wrote, iclass 18, count 0 2006.225.07:20:20.35#ibcon#about to read 3, iclass 18, count 0 2006.225.07:20:20.38#ibcon#read 3, iclass 18, count 0 2006.225.07:20:20.38#ibcon#about to read 4, iclass 18, count 0 2006.225.07:20:20.38#ibcon#read 4, iclass 18, count 0 2006.225.07:20:20.38#ibcon#about to read 5, iclass 18, count 0 2006.225.07:20:20.38#ibcon#read 5, iclass 18, count 0 2006.225.07:20:20.38#ibcon#about to read 6, iclass 18, count 0 2006.225.07:20:20.38#ibcon#read 6, iclass 18, count 0 2006.225.07:20:20.38#ibcon#end of sib2, iclass 18, count 0 2006.225.07:20:20.38#ibcon#*after write, iclass 18, count 0 2006.225.07:20:20.38#ibcon#*before return 0, iclass 18, count 0 2006.225.07:20:20.38#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:20:20.38#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:20:20.38#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:20:20.38#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:20:20.38$vc4f8/vabw=wide 2006.225.07:20:20.38#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.225.07:20:20.38#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.225.07:20:20.38#ibcon#ireg 8 cls_cnt 0 2006.225.07:20:20.38#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:20:20.38#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:20:20.38#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:20:20.38#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:20:20.38#ibcon#first serial, iclass 20, count 0 2006.225.07:20:20.38#ibcon#enter sib2, iclass 20, count 0 2006.225.07:20:20.38#ibcon#flushed, iclass 20, count 0 2006.225.07:20:20.38#ibcon#about to write, iclass 20, count 0 2006.225.07:20:20.38#ibcon#wrote, iclass 20, count 0 2006.225.07:20:20.38#ibcon#about to read 3, iclass 20, count 0 2006.225.07:20:20.40#ibcon#read 3, iclass 20, count 0 2006.225.07:20:20.40#ibcon#about to read 4, iclass 20, count 0 2006.225.07:20:20.40#ibcon#read 4, iclass 20, count 0 2006.225.07:20:20.40#ibcon#about to read 5, iclass 20, count 0 2006.225.07:20:20.40#ibcon#read 5, iclass 20, count 0 2006.225.07:20:20.40#ibcon#about to read 6, iclass 20, count 0 2006.225.07:20:20.40#ibcon#read 6, iclass 20, count 0 2006.225.07:20:20.40#ibcon#end of sib2, iclass 20, count 0 2006.225.07:20:20.40#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:20:20.40#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:20:20.40#ibcon#[25=BW32\r\n] 2006.225.07:20:20.40#ibcon#*before write, iclass 20, count 0 2006.225.07:20:20.40#ibcon#enter sib2, iclass 20, count 0 2006.225.07:20:20.40#ibcon#flushed, iclass 20, count 0 2006.225.07:20:20.40#ibcon#about to write, iclass 20, count 0 2006.225.07:20:20.40#ibcon#wrote, iclass 20, count 0 2006.225.07:20:20.40#ibcon#about to read 3, iclass 20, count 0 2006.225.07:20:20.43#ibcon#read 3, iclass 20, count 0 2006.225.07:20:20.43#ibcon#about to read 4, iclass 20, count 0 2006.225.07:20:20.43#ibcon#read 4, iclass 20, count 0 2006.225.07:20:20.43#ibcon#about to read 5, iclass 20, count 0 2006.225.07:20:20.43#ibcon#read 5, iclass 20, count 0 2006.225.07:20:20.43#ibcon#about to read 6, iclass 20, count 0 2006.225.07:20:20.43#ibcon#read 6, iclass 20, count 0 2006.225.07:20:20.43#ibcon#end of sib2, iclass 20, count 0 2006.225.07:20:20.43#ibcon#*after write, iclass 20, count 0 2006.225.07:20:20.43#ibcon#*before return 0, iclass 20, count 0 2006.225.07:20:20.43#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:20:20.43#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:20:20.43#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:20:20.43#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:20:20.43$vc4f8/vbbw=wide 2006.225.07:20:20.43#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.07:20:20.43#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.07:20:20.43#ibcon#ireg 8 cls_cnt 0 2006.225.07:20:20.43#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:20:20.50#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:20:20.50#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:20:20.50#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:20:20.50#ibcon#first serial, iclass 22, count 0 2006.225.07:20:20.50#ibcon#enter sib2, iclass 22, count 0 2006.225.07:20:20.50#ibcon#flushed, iclass 22, count 0 2006.225.07:20:20.50#ibcon#about to write, iclass 22, count 0 2006.225.07:20:20.50#ibcon#wrote, iclass 22, count 0 2006.225.07:20:20.50#ibcon#about to read 3, iclass 22, count 0 2006.225.07:20:20.52#ibcon#read 3, iclass 22, count 0 2006.225.07:20:20.52#ibcon#about to read 4, iclass 22, count 0 2006.225.07:20:20.52#ibcon#read 4, iclass 22, count 0 2006.225.07:20:20.52#ibcon#about to read 5, iclass 22, count 0 2006.225.07:20:20.52#ibcon#read 5, iclass 22, count 0 2006.225.07:20:20.52#ibcon#about to read 6, iclass 22, count 0 2006.225.07:20:20.52#ibcon#read 6, iclass 22, count 0 2006.225.07:20:20.52#ibcon#end of sib2, iclass 22, count 0 2006.225.07:20:20.52#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:20:20.52#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:20:20.52#ibcon#[27=BW32\r\n] 2006.225.07:20:20.52#ibcon#*before write, iclass 22, count 0 2006.225.07:20:20.52#ibcon#enter sib2, iclass 22, count 0 2006.225.07:20:20.52#ibcon#flushed, iclass 22, count 0 2006.225.07:20:20.52#ibcon#about to write, iclass 22, count 0 2006.225.07:20:20.52#ibcon#wrote, iclass 22, count 0 2006.225.07:20:20.52#ibcon#about to read 3, iclass 22, count 0 2006.225.07:20:20.55#ibcon#read 3, iclass 22, count 0 2006.225.07:20:20.55#ibcon#about to read 4, iclass 22, count 0 2006.225.07:20:20.55#ibcon#read 4, iclass 22, count 0 2006.225.07:20:20.55#ibcon#about to read 5, iclass 22, count 0 2006.225.07:20:20.55#ibcon#read 5, iclass 22, count 0 2006.225.07:20:20.55#ibcon#about to read 6, iclass 22, count 0 2006.225.07:20:20.55#ibcon#read 6, iclass 22, count 0 2006.225.07:20:20.55#ibcon#end of sib2, iclass 22, count 0 2006.225.07:20:20.55#ibcon#*after write, iclass 22, count 0 2006.225.07:20:20.55#ibcon#*before return 0, iclass 22, count 0 2006.225.07:20:20.55#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:20:20.55#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:20:20.55#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:20:20.55#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:20:20.55$4f8m12a/ifd4f 2006.225.07:20:20.55&ifd4f/lo= 2006.225.07:20:20.55&ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:20:20.55&ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:20:20.55&ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:20:20.55&ifd4f/patch= 2006.225.07:20:20.55&ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:20:20.55&ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:20:20.55&ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:20:20.55$ifd4f/lo= 2006.225.07:20:20.55$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:20:20.55$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:20:20.55$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:20:20.55$ifd4f/patch= 2006.225.07:20:20.55$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:20:20.55$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:20:20.55$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:20:20.55$4f8m12a/"form=m,16.000,1:2 2006.225.07:20:20.55$4f8m12a/"tpicd 2006.225.07:20:20.55$4f8m12a/echo=off 2006.225.07:20:20.55$4f8m12a/xlog=off 2006.225.07:20:20.55:!2006.225.07:29:50 2006.225.07:20:38.14#trakl#Source acquired 2006.225.07:20:38.14#flagr#flagr/antenna,acquired 2006.225.07:29:50.01:preob 2006.225.07:29:50.01&preob/onsource 2006.225.07:29:51.14/onsource/TRACKING 2006.225.07:29:51.14:!2006.225.07:30:00 2006.225.07:30:00.00:data_valid=on 2006.225.07:30:00.00:midob 2006.225.07:30:00.00&midob/onsource 2006.225.07:30:00.00&midob/wx 2006.225.07:30:00.00&midob/cable 2006.225.07:30:00.00&midob/va 2006.225.07:30:00.00&midob/valo 2006.225.07:30:00.00&midob/vb 2006.225.07:30:00.00&midob/vblo 2006.225.07:30:00.00&midob/vabw 2006.225.07:30:00.00&midob/vbbw 2006.225.07:30:00.00&midob/"form 2006.225.07:30:00.00&midob/xfe 2006.225.07:30:00.00&midob/ifatt 2006.225.07:30:00.00&midob/clockoff 2006.225.07:30:00.00&midob/sy=logmail 2006.225.07:30:00.00&midob/"sy=run setcl adapt & 2006.225.07:30:00.14/onsource/TRACKING 2006.225.07:30:00.14/wx/28.14,1003.2,74 2006.225.07:30:00.25/cable/+6.4024E-03 2006.225.07:30:01.34/va/01,08,usb,yes,30,32 2006.225.07:30:01.34/va/02,07,usb,yes,30,32 2006.225.07:30:01.34/va/03,06,usb,yes,32,32 2006.225.07:30:01.34/va/04,07,usb,yes,32,34 2006.225.07:30:01.34/va/05,07,usb,yes,34,36 2006.225.07:30:01.34/va/06,06,usb,yes,34,33 2006.225.07:30:01.34/va/07,06,usb,yes,34,34 2006.225.07:30:01.34/va/08,07,usb,yes,32,32 2006.225.07:30:01.57/valo/01,532.99,yes,locked 2006.225.07:30:01.57/valo/02,572.99,yes,locked 2006.225.07:30:01.57/valo/03,672.99,yes,locked 2006.225.07:30:01.57/valo/04,832.99,yes,locked 2006.225.07:30:01.57/valo/05,652.99,yes,locked 2006.225.07:30:01.57/valo/06,772.99,yes,locked 2006.225.07:30:01.57/valo/07,832.99,yes,locked 2006.225.07:30:01.57/valo/08,852.99,yes,locked 2006.225.07:30:02.66/vb/01,04,usb,yes,32,30 2006.225.07:30:02.66/vb/02,04,usb,yes,33,35 2006.225.07:30:02.66/vb/03,04,usb,yes,30,34 2006.225.07:30:02.66/vb/04,04,usb,yes,31,31 2006.225.07:30:02.66/vb/05,04,usb,yes,29,33 2006.225.07:30:02.66/vb/06,04,usb,yes,30,33 2006.225.07:30:02.66/vb/07,04,usb,yes,32,32 2006.225.07:30:02.66/vb/08,04,usb,yes,30,33 2006.225.07:30:02.89/vblo/01,632.99,yes,locked 2006.225.07:30:02.89/vblo/02,640.99,yes,locked 2006.225.07:30:02.89/vblo/03,656.99,yes,locked 2006.225.07:30:02.89/vblo/04,712.99,yes,locked 2006.225.07:30:02.89/vblo/05,744.99,yes,locked 2006.225.07:30:02.89/vblo/06,752.99,yes,locked 2006.225.07:30:02.89/vblo/07,734.99,yes,locked 2006.225.07:30:02.89/vblo/08,744.99,yes,locked 2006.225.07:30:03.04/vabw/8 2006.225.07:30:03.19/vbbw/8 2006.225.07:30:03.28/xfe/off,on,15.2 2006.225.07:30:03.68/ifatt/23,28,28,28 2006.225.07:30:03.68&clockoff/"gps-fmout=1p 2006.225.07:30:03.68&clockoff/fmout-gps=1p 2006.225.07:30:04.07/fmout-gps/S +4.43E-07 2006.225.07:30:04.15:!2006.225.07:31:00 2006.225.07:31:00.01:data_valid=off 2006.225.07:31:00.02:postob 2006.225.07:31:00.02&postob/cable 2006.225.07:31:00.02&postob/wx 2006.225.07:31:00.02&postob/clockoff 2006.225.07:31:00.21/cable/+6.4029E-03 2006.225.07:31:00.21/wx/28.08,1003.2,71 2006.225.07:31:00.27/fmout-gps/S +4.43E-07 2006.225.07:31:00.27:scan_name=225-0733,k06225,60 2006.225.07:31:00.27:source=0743+259,074625.87,254902.1,2000.0,ccw 2006.225.07:31:01.14#flagr#flagr/antenna,new-source 2006.225.07:31:01.14:checkk5 2006.225.07:31:01.14&checkk5/chk_autoobs=1 2006.225.07:31:01.15&checkk5/chk_autoobs=2 2006.225.07:31:01.15&checkk5/chk_autoobs=3 2006.225.07:31:01.15&checkk5/chk_autoobs=4 2006.225.07:31:01.15&checkk5/chk_obsdata=1 2006.225.07:31:01.15&checkk5/chk_obsdata=2 2006.225.07:31:01.15&checkk5/chk_obsdata=3 2006.225.07:31:01.15&checkk5/chk_obsdata=4 2006.225.07:31:01.15&checkk5/k5log=1 2006.225.07:31:01.15&checkk5/k5log=2 2006.225.07:31:01.15&checkk5/k5log=3 2006.225.07:31:01.15&checkk5/k5log=4 2006.225.07:31:01.15&checkk5/obsinfo 2006.225.07:31:01.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:31:01.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:31:02.25/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:31:02.63/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:31:03.00/chk_obsdata//k5ts1/T2250730??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:31:03.37/chk_obsdata//k5ts2/T2250730??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:31:03.74/chk_obsdata//k5ts3/T2250730??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:31:04.10/chk_obsdata//k5ts4/T2250730??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:31:04.81/k5log//k5ts1_log_newline 2006.225.07:31:05.49/k5log//k5ts2_log_newline 2006.225.07:31:06.17/k5log//k5ts3_log_newline 2006.225.07:31:06.86/k5log//k5ts4_log_newline 2006.225.07:31:06.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:31:06.88:4f8m12a=1 2006.225.07:31:06.88$4f8m12a/echo=on 2006.225.07:31:06.88$4f8m12a/pcalon 2006.225.07:31:06.88$pcalon/"no phase cal control is implemented here 2006.225.07:31:06.88$4f8m12a/"tpicd=stop 2006.225.07:31:06.88$4f8m12a/vc4f8 2006.225.07:31:06.88$vc4f8/valo=1,532.99 2006.225.07:31:06.89#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.07:31:06.89#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.07:31:06.89#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:06.89#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:31:06.89#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:31:06.89#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:31:06.89#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:31:06.89#ibcon#first serial, iclass 29, count 0 2006.225.07:31:06.89#ibcon#enter sib2, iclass 29, count 0 2006.225.07:31:06.89#ibcon#flushed, iclass 29, count 0 2006.225.07:31:06.89#ibcon#about to write, iclass 29, count 0 2006.225.07:31:06.89#ibcon#wrote, iclass 29, count 0 2006.225.07:31:06.89#ibcon#about to read 3, iclass 29, count 0 2006.225.07:31:06.93#ibcon#read 3, iclass 29, count 0 2006.225.07:31:06.93#ibcon#about to read 4, iclass 29, count 0 2006.225.07:31:06.93#ibcon#read 4, iclass 29, count 0 2006.225.07:31:06.93#ibcon#about to read 5, iclass 29, count 0 2006.225.07:31:06.93#ibcon#read 5, iclass 29, count 0 2006.225.07:31:06.93#ibcon#about to read 6, iclass 29, count 0 2006.225.07:31:06.93#ibcon#read 6, iclass 29, count 0 2006.225.07:31:06.93#ibcon#end of sib2, iclass 29, count 0 2006.225.07:31:06.93#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:31:06.93#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:31:06.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:31:06.93#ibcon#*before write, iclass 29, count 0 2006.225.07:31:06.93#ibcon#enter sib2, iclass 29, count 0 2006.225.07:31:06.93#ibcon#flushed, iclass 29, count 0 2006.225.07:31:06.93#ibcon#about to write, iclass 29, count 0 2006.225.07:31:06.93#ibcon#wrote, iclass 29, count 0 2006.225.07:31:06.93#ibcon#about to read 3, iclass 29, count 0 2006.225.07:31:06.97#ibcon#read 3, iclass 29, count 0 2006.225.07:31:06.97#ibcon#about to read 4, iclass 29, count 0 2006.225.07:31:06.97#ibcon#read 4, iclass 29, count 0 2006.225.07:31:06.97#ibcon#about to read 5, iclass 29, count 0 2006.225.07:31:06.97#ibcon#read 5, iclass 29, count 0 2006.225.07:31:06.97#ibcon#about to read 6, iclass 29, count 0 2006.225.07:31:06.97#ibcon#read 6, iclass 29, count 0 2006.225.07:31:06.97#ibcon#end of sib2, iclass 29, count 0 2006.225.07:31:06.97#ibcon#*after write, iclass 29, count 0 2006.225.07:31:06.97#ibcon#*before return 0, iclass 29, count 0 2006.225.07:31:06.97#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:31:06.97#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:31:06.97#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:31:06.97#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:31:06.97$vc4f8/va=1,8 2006.225.07:31:06.97#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.07:31:06.97#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.07:31:06.97#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:06.97#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:31:06.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:31:06.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:31:06.97#ibcon#enter wrdev, iclass 31, count 2 2006.225.07:31:06.97#ibcon#first serial, iclass 31, count 2 2006.225.07:31:06.97#ibcon#enter sib2, iclass 31, count 2 2006.225.07:31:06.97#ibcon#flushed, iclass 31, count 2 2006.225.07:31:06.97#ibcon#about to write, iclass 31, count 2 2006.225.07:31:06.97#ibcon#wrote, iclass 31, count 2 2006.225.07:31:06.97#ibcon#about to read 3, iclass 31, count 2 2006.225.07:31:06.99#ibcon#read 3, iclass 31, count 2 2006.225.07:31:06.99#ibcon#about to read 4, iclass 31, count 2 2006.225.07:31:06.99#ibcon#read 4, iclass 31, count 2 2006.225.07:31:06.99#ibcon#about to read 5, iclass 31, count 2 2006.225.07:31:06.99#ibcon#read 5, iclass 31, count 2 2006.225.07:31:06.99#ibcon#about to read 6, iclass 31, count 2 2006.225.07:31:06.99#ibcon#read 6, iclass 31, count 2 2006.225.07:31:06.99#ibcon#end of sib2, iclass 31, count 2 2006.225.07:31:06.99#ibcon#*mode == 0, iclass 31, count 2 2006.225.07:31:06.99#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.07:31:06.99#ibcon#[25=AT01-08\r\n] 2006.225.07:31:06.99#ibcon#*before write, iclass 31, count 2 2006.225.07:31:06.99#ibcon#enter sib2, iclass 31, count 2 2006.225.07:31:06.99#ibcon#flushed, iclass 31, count 2 2006.225.07:31:06.99#ibcon#about to write, iclass 31, count 2 2006.225.07:31:06.99#ibcon#wrote, iclass 31, count 2 2006.225.07:31:06.99#ibcon#about to read 3, iclass 31, count 2 2006.225.07:31:07.02#ibcon#read 3, iclass 31, count 2 2006.225.07:31:07.02#ibcon#about to read 4, iclass 31, count 2 2006.225.07:31:07.02#ibcon#read 4, iclass 31, count 2 2006.225.07:31:07.02#ibcon#about to read 5, iclass 31, count 2 2006.225.07:31:07.02#ibcon#read 5, iclass 31, count 2 2006.225.07:31:07.02#ibcon#about to read 6, iclass 31, count 2 2006.225.07:31:07.02#ibcon#read 6, iclass 31, count 2 2006.225.07:31:07.02#ibcon#end of sib2, iclass 31, count 2 2006.225.07:31:07.02#ibcon#*after write, iclass 31, count 2 2006.225.07:31:07.02#ibcon#*before return 0, iclass 31, count 2 2006.225.07:31:07.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:31:07.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:31:07.02#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.07:31:07.02#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:07.02#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:31:07.14#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:31:07.14#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:31:07.14#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:31:07.14#ibcon#first serial, iclass 31, count 0 2006.225.07:31:07.14#ibcon#enter sib2, iclass 31, count 0 2006.225.07:31:07.14#ibcon#flushed, iclass 31, count 0 2006.225.07:31:07.14#ibcon#about to write, iclass 31, count 0 2006.225.07:31:07.14#ibcon#wrote, iclass 31, count 0 2006.225.07:31:07.14#ibcon#about to read 3, iclass 31, count 0 2006.225.07:31:07.16#ibcon#read 3, iclass 31, count 0 2006.225.07:31:07.16#ibcon#about to read 4, iclass 31, count 0 2006.225.07:31:07.16#ibcon#read 4, iclass 31, count 0 2006.225.07:31:07.16#ibcon#about to read 5, iclass 31, count 0 2006.225.07:31:07.16#ibcon#read 5, iclass 31, count 0 2006.225.07:31:07.16#ibcon#about to read 6, iclass 31, count 0 2006.225.07:31:07.16#ibcon#read 6, iclass 31, count 0 2006.225.07:31:07.16#ibcon#end of sib2, iclass 31, count 0 2006.225.07:31:07.16#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:31:07.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:31:07.16#ibcon#[25=USB\r\n] 2006.225.07:31:07.16#ibcon#*before write, iclass 31, count 0 2006.225.07:31:07.16#ibcon#enter sib2, iclass 31, count 0 2006.225.07:31:07.16#ibcon#flushed, iclass 31, count 0 2006.225.07:31:07.16#ibcon#about to write, iclass 31, count 0 2006.225.07:31:07.16#ibcon#wrote, iclass 31, count 0 2006.225.07:31:07.16#ibcon#about to read 3, iclass 31, count 0 2006.225.07:31:07.19#ibcon#read 3, iclass 31, count 0 2006.225.07:31:07.19#ibcon#about to read 4, iclass 31, count 0 2006.225.07:31:07.19#ibcon#read 4, iclass 31, count 0 2006.225.07:31:07.19#ibcon#about to read 5, iclass 31, count 0 2006.225.07:31:07.19#ibcon#read 5, iclass 31, count 0 2006.225.07:31:07.19#ibcon#about to read 6, iclass 31, count 0 2006.225.07:31:07.19#ibcon#read 6, iclass 31, count 0 2006.225.07:31:07.19#ibcon#end of sib2, iclass 31, count 0 2006.225.07:31:07.19#ibcon#*after write, iclass 31, count 0 2006.225.07:31:07.19#ibcon#*before return 0, iclass 31, count 0 2006.225.07:31:07.19#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:31:07.19#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:31:07.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:31:07.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:31:07.19$vc4f8/valo=2,572.99 2006.225.07:31:07.19#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.07:31:07.19#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.07:31:07.19#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:07.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:31:07.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:31:07.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:31:07.19#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:31:07.19#ibcon#first serial, iclass 33, count 0 2006.225.07:31:07.19#ibcon#enter sib2, iclass 33, count 0 2006.225.07:31:07.19#ibcon#flushed, iclass 33, count 0 2006.225.07:31:07.19#ibcon#about to write, iclass 33, count 0 2006.225.07:31:07.19#ibcon#wrote, iclass 33, count 0 2006.225.07:31:07.19#ibcon#about to read 3, iclass 33, count 0 2006.225.07:31:07.22#ibcon#read 3, iclass 33, count 0 2006.225.07:31:07.22#ibcon#about to read 4, iclass 33, count 0 2006.225.07:31:07.22#ibcon#read 4, iclass 33, count 0 2006.225.07:31:07.22#ibcon#about to read 5, iclass 33, count 0 2006.225.07:31:07.22#ibcon#read 5, iclass 33, count 0 2006.225.07:31:07.22#ibcon#about to read 6, iclass 33, count 0 2006.225.07:31:07.22#ibcon#read 6, iclass 33, count 0 2006.225.07:31:07.22#ibcon#end of sib2, iclass 33, count 0 2006.225.07:31:07.22#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:31:07.22#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:31:07.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:31:07.22#ibcon#*before write, iclass 33, count 0 2006.225.07:31:07.22#ibcon#enter sib2, iclass 33, count 0 2006.225.07:31:07.22#ibcon#flushed, iclass 33, count 0 2006.225.07:31:07.22#ibcon#about to write, iclass 33, count 0 2006.225.07:31:07.22#ibcon#wrote, iclass 33, count 0 2006.225.07:31:07.22#ibcon#about to read 3, iclass 33, count 0 2006.225.07:31:07.26#ibcon#read 3, iclass 33, count 0 2006.225.07:31:07.26#ibcon#about to read 4, iclass 33, count 0 2006.225.07:31:07.26#ibcon#read 4, iclass 33, count 0 2006.225.07:31:07.26#ibcon#about to read 5, iclass 33, count 0 2006.225.07:31:07.26#ibcon#read 5, iclass 33, count 0 2006.225.07:31:07.26#ibcon#about to read 6, iclass 33, count 0 2006.225.07:31:07.26#ibcon#read 6, iclass 33, count 0 2006.225.07:31:07.26#ibcon#end of sib2, iclass 33, count 0 2006.225.07:31:07.26#ibcon#*after write, iclass 33, count 0 2006.225.07:31:07.26#ibcon#*before return 0, iclass 33, count 0 2006.225.07:31:07.26#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:31:07.26#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:31:07.26#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:31:07.26#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:31:07.26$vc4f8/va=2,7 2006.225.07:31:07.26#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.07:31:07.26#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.07:31:07.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:07.26#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:31:07.32#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:31:07.32#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:31:07.32#ibcon#enter wrdev, iclass 35, count 2 2006.225.07:31:07.32#ibcon#first serial, iclass 35, count 2 2006.225.07:31:07.32#ibcon#enter sib2, iclass 35, count 2 2006.225.07:31:07.32#ibcon#flushed, iclass 35, count 2 2006.225.07:31:07.32#ibcon#about to write, iclass 35, count 2 2006.225.07:31:07.32#ibcon#wrote, iclass 35, count 2 2006.225.07:31:07.32#ibcon#about to read 3, iclass 35, count 2 2006.225.07:31:07.33#ibcon#read 3, iclass 35, count 2 2006.225.07:31:07.33#ibcon#about to read 4, iclass 35, count 2 2006.225.07:31:07.33#ibcon#read 4, iclass 35, count 2 2006.225.07:31:07.33#ibcon#about to read 5, iclass 35, count 2 2006.225.07:31:07.33#ibcon#read 5, iclass 35, count 2 2006.225.07:31:07.33#ibcon#about to read 6, iclass 35, count 2 2006.225.07:31:07.33#ibcon#read 6, iclass 35, count 2 2006.225.07:31:07.33#ibcon#end of sib2, iclass 35, count 2 2006.225.07:31:07.33#ibcon#*mode == 0, iclass 35, count 2 2006.225.07:31:07.33#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.07:31:07.33#ibcon#[25=AT02-07\r\n] 2006.225.07:31:07.33#ibcon#*before write, iclass 35, count 2 2006.225.07:31:07.33#ibcon#enter sib2, iclass 35, count 2 2006.225.07:31:07.33#ibcon#flushed, iclass 35, count 2 2006.225.07:31:07.33#ibcon#about to write, iclass 35, count 2 2006.225.07:31:07.33#ibcon#wrote, iclass 35, count 2 2006.225.07:31:07.33#ibcon#about to read 3, iclass 35, count 2 2006.225.07:31:07.36#ibcon#read 3, iclass 35, count 2 2006.225.07:31:07.36#ibcon#about to read 4, iclass 35, count 2 2006.225.07:31:07.36#ibcon#read 4, iclass 35, count 2 2006.225.07:31:07.36#ibcon#about to read 5, iclass 35, count 2 2006.225.07:31:07.36#ibcon#read 5, iclass 35, count 2 2006.225.07:31:07.36#ibcon#about to read 6, iclass 35, count 2 2006.225.07:31:07.36#ibcon#read 6, iclass 35, count 2 2006.225.07:31:07.36#ibcon#end of sib2, iclass 35, count 2 2006.225.07:31:07.36#ibcon#*after write, iclass 35, count 2 2006.225.07:31:07.36#ibcon#*before return 0, iclass 35, count 2 2006.225.07:31:07.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:31:07.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:31:07.36#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.07:31:07.36#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:07.36#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:31:07.48#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:31:07.48#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:31:07.48#ibcon#enter wrdev, iclass 35, count 0 2006.225.07:31:07.48#ibcon#first serial, iclass 35, count 0 2006.225.07:31:07.48#ibcon#enter sib2, iclass 35, count 0 2006.225.07:31:07.48#ibcon#flushed, iclass 35, count 0 2006.225.07:31:07.48#ibcon#about to write, iclass 35, count 0 2006.225.07:31:07.48#ibcon#wrote, iclass 35, count 0 2006.225.07:31:07.48#ibcon#about to read 3, iclass 35, count 0 2006.225.07:31:07.50#ibcon#read 3, iclass 35, count 0 2006.225.07:31:07.50#ibcon#about to read 4, iclass 35, count 0 2006.225.07:31:07.50#ibcon#read 4, iclass 35, count 0 2006.225.07:31:07.50#ibcon#about to read 5, iclass 35, count 0 2006.225.07:31:07.50#ibcon#read 5, iclass 35, count 0 2006.225.07:31:07.50#ibcon#about to read 6, iclass 35, count 0 2006.225.07:31:07.50#ibcon#read 6, iclass 35, count 0 2006.225.07:31:07.50#ibcon#end of sib2, iclass 35, count 0 2006.225.07:31:07.50#ibcon#*mode == 0, iclass 35, count 0 2006.225.07:31:07.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.07:31:07.50#ibcon#[25=USB\r\n] 2006.225.07:31:07.50#ibcon#*before write, iclass 35, count 0 2006.225.07:31:07.50#ibcon#enter sib2, iclass 35, count 0 2006.225.07:31:07.50#ibcon#flushed, iclass 35, count 0 2006.225.07:31:07.50#ibcon#about to write, iclass 35, count 0 2006.225.07:31:07.50#ibcon#wrote, iclass 35, count 0 2006.225.07:31:07.50#ibcon#about to read 3, iclass 35, count 0 2006.225.07:31:07.53#ibcon#read 3, iclass 35, count 0 2006.225.07:31:07.53#ibcon#about to read 4, iclass 35, count 0 2006.225.07:31:07.53#ibcon#read 4, iclass 35, count 0 2006.225.07:31:07.53#ibcon#about to read 5, iclass 35, count 0 2006.225.07:31:07.53#ibcon#read 5, iclass 35, count 0 2006.225.07:31:07.53#ibcon#about to read 6, iclass 35, count 0 2006.225.07:31:07.53#ibcon#read 6, iclass 35, count 0 2006.225.07:31:07.53#ibcon#end of sib2, iclass 35, count 0 2006.225.07:31:07.53#ibcon#*after write, iclass 35, count 0 2006.225.07:31:07.53#ibcon#*before return 0, iclass 35, count 0 2006.225.07:31:07.53#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:31:07.53#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:31:07.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.07:31:07.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.07:31:07.53$vc4f8/valo=3,672.99 2006.225.07:31:07.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.07:31:07.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.07:31:07.53#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:07.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:31:07.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:31:07.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:31:07.53#ibcon#enter wrdev, iclass 37, count 0 2006.225.07:31:07.53#ibcon#first serial, iclass 37, count 0 2006.225.07:31:07.53#ibcon#enter sib2, iclass 37, count 0 2006.225.07:31:07.53#ibcon#flushed, iclass 37, count 0 2006.225.07:31:07.53#ibcon#about to write, iclass 37, count 0 2006.225.07:31:07.53#ibcon#wrote, iclass 37, count 0 2006.225.07:31:07.53#ibcon#about to read 3, iclass 37, count 0 2006.225.07:31:07.56#ibcon#read 3, iclass 37, count 0 2006.225.07:31:07.56#ibcon#about to read 4, iclass 37, count 0 2006.225.07:31:07.56#ibcon#read 4, iclass 37, count 0 2006.225.07:31:07.56#ibcon#about to read 5, iclass 37, count 0 2006.225.07:31:07.56#ibcon#read 5, iclass 37, count 0 2006.225.07:31:07.56#ibcon#about to read 6, iclass 37, count 0 2006.225.07:31:07.56#ibcon#read 6, iclass 37, count 0 2006.225.07:31:07.56#ibcon#end of sib2, iclass 37, count 0 2006.225.07:31:07.56#ibcon#*mode == 0, iclass 37, count 0 2006.225.07:31:07.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.07:31:07.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:31:07.56#ibcon#*before write, iclass 37, count 0 2006.225.07:31:07.56#ibcon#enter sib2, iclass 37, count 0 2006.225.07:31:07.56#ibcon#flushed, iclass 37, count 0 2006.225.07:31:07.56#ibcon#about to write, iclass 37, count 0 2006.225.07:31:07.56#ibcon#wrote, iclass 37, count 0 2006.225.07:31:07.56#ibcon#about to read 3, iclass 37, count 0 2006.225.07:31:07.60#ibcon#read 3, iclass 37, count 0 2006.225.07:31:07.60#ibcon#about to read 4, iclass 37, count 0 2006.225.07:31:07.60#ibcon#read 4, iclass 37, count 0 2006.225.07:31:07.60#ibcon#about to read 5, iclass 37, count 0 2006.225.07:31:07.60#ibcon#read 5, iclass 37, count 0 2006.225.07:31:07.60#ibcon#about to read 6, iclass 37, count 0 2006.225.07:31:07.60#ibcon#read 6, iclass 37, count 0 2006.225.07:31:07.60#ibcon#end of sib2, iclass 37, count 0 2006.225.07:31:07.60#ibcon#*after write, iclass 37, count 0 2006.225.07:31:07.60#ibcon#*before return 0, iclass 37, count 0 2006.225.07:31:07.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:31:07.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:31:07.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.07:31:07.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.07:31:07.60$vc4f8/va=3,6 2006.225.07:31:07.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.07:31:07.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.07:31:07.60#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:07.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:31:07.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:31:07.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:31:07.66#ibcon#enter wrdev, iclass 39, count 2 2006.225.07:31:07.66#ibcon#first serial, iclass 39, count 2 2006.225.07:31:07.66#ibcon#enter sib2, iclass 39, count 2 2006.225.07:31:07.66#ibcon#flushed, iclass 39, count 2 2006.225.07:31:07.66#ibcon#about to write, iclass 39, count 2 2006.225.07:31:07.66#ibcon#wrote, iclass 39, count 2 2006.225.07:31:07.66#ibcon#about to read 3, iclass 39, count 2 2006.225.07:31:07.67#ibcon#read 3, iclass 39, count 2 2006.225.07:31:07.67#ibcon#about to read 4, iclass 39, count 2 2006.225.07:31:07.67#ibcon#read 4, iclass 39, count 2 2006.225.07:31:07.67#ibcon#about to read 5, iclass 39, count 2 2006.225.07:31:07.67#ibcon#read 5, iclass 39, count 2 2006.225.07:31:07.67#ibcon#about to read 6, iclass 39, count 2 2006.225.07:31:07.67#ibcon#read 6, iclass 39, count 2 2006.225.07:31:07.67#ibcon#end of sib2, iclass 39, count 2 2006.225.07:31:07.67#ibcon#*mode == 0, iclass 39, count 2 2006.225.07:31:07.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.07:31:07.67#ibcon#[25=AT03-06\r\n] 2006.225.07:31:07.67#ibcon#*before write, iclass 39, count 2 2006.225.07:31:07.67#ibcon#enter sib2, iclass 39, count 2 2006.225.07:31:07.67#ibcon#flushed, iclass 39, count 2 2006.225.07:31:07.67#ibcon#about to write, iclass 39, count 2 2006.225.07:31:07.67#ibcon#wrote, iclass 39, count 2 2006.225.07:31:07.67#ibcon#about to read 3, iclass 39, count 2 2006.225.07:31:07.70#ibcon#read 3, iclass 39, count 2 2006.225.07:31:07.70#ibcon#about to read 4, iclass 39, count 2 2006.225.07:31:07.70#ibcon#read 4, iclass 39, count 2 2006.225.07:31:07.70#ibcon#about to read 5, iclass 39, count 2 2006.225.07:31:07.70#ibcon#read 5, iclass 39, count 2 2006.225.07:31:07.70#ibcon#about to read 6, iclass 39, count 2 2006.225.07:31:07.70#ibcon#read 6, iclass 39, count 2 2006.225.07:31:07.70#ibcon#end of sib2, iclass 39, count 2 2006.225.07:31:07.70#ibcon#*after write, iclass 39, count 2 2006.225.07:31:07.70#ibcon#*before return 0, iclass 39, count 2 2006.225.07:31:07.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:31:07.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:31:07.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.07:31:07.70#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:07.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:31:07.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:31:07.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:31:07.82#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:31:07.82#ibcon#first serial, iclass 39, count 0 2006.225.07:31:07.82#ibcon#enter sib2, iclass 39, count 0 2006.225.07:31:07.82#ibcon#flushed, iclass 39, count 0 2006.225.07:31:07.82#ibcon#about to write, iclass 39, count 0 2006.225.07:31:07.82#ibcon#wrote, iclass 39, count 0 2006.225.07:31:07.82#ibcon#about to read 3, iclass 39, count 0 2006.225.07:31:07.84#ibcon#read 3, iclass 39, count 0 2006.225.07:31:07.84#ibcon#about to read 4, iclass 39, count 0 2006.225.07:31:07.84#ibcon#read 4, iclass 39, count 0 2006.225.07:31:07.84#ibcon#about to read 5, iclass 39, count 0 2006.225.07:31:07.84#ibcon#read 5, iclass 39, count 0 2006.225.07:31:07.84#ibcon#about to read 6, iclass 39, count 0 2006.225.07:31:07.84#ibcon#read 6, iclass 39, count 0 2006.225.07:31:07.84#ibcon#end of sib2, iclass 39, count 0 2006.225.07:31:07.84#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:31:07.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:31:07.84#ibcon#[25=USB\r\n] 2006.225.07:31:07.84#ibcon#*before write, iclass 39, count 0 2006.225.07:31:07.84#ibcon#enter sib2, iclass 39, count 0 2006.225.07:31:07.84#ibcon#flushed, iclass 39, count 0 2006.225.07:31:07.84#ibcon#about to write, iclass 39, count 0 2006.225.07:31:07.84#ibcon#wrote, iclass 39, count 0 2006.225.07:31:07.84#ibcon#about to read 3, iclass 39, count 0 2006.225.07:31:07.87#ibcon#read 3, iclass 39, count 0 2006.225.07:31:07.87#ibcon#about to read 4, iclass 39, count 0 2006.225.07:31:07.87#ibcon#read 4, iclass 39, count 0 2006.225.07:31:07.87#ibcon#about to read 5, iclass 39, count 0 2006.225.07:31:07.87#ibcon#read 5, iclass 39, count 0 2006.225.07:31:07.87#ibcon#about to read 6, iclass 39, count 0 2006.225.07:31:07.87#ibcon#read 6, iclass 39, count 0 2006.225.07:31:07.87#ibcon#end of sib2, iclass 39, count 0 2006.225.07:31:07.87#ibcon#*after write, iclass 39, count 0 2006.225.07:31:07.87#ibcon#*before return 0, iclass 39, count 0 2006.225.07:31:07.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:31:07.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:31:07.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:31:07.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:31:07.87$vc4f8/valo=4,832.99 2006.225.07:31:07.87#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.07:31:07.87#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.07:31:07.87#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:07.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:31:07.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:31:07.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:31:07.87#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:31:07.87#ibcon#first serial, iclass 3, count 0 2006.225.07:31:07.87#ibcon#enter sib2, iclass 3, count 0 2006.225.07:31:07.87#ibcon#flushed, iclass 3, count 0 2006.225.07:31:07.87#ibcon#about to write, iclass 3, count 0 2006.225.07:31:07.87#ibcon#wrote, iclass 3, count 0 2006.225.07:31:07.87#ibcon#about to read 3, iclass 3, count 0 2006.225.07:31:07.90#ibcon#read 3, iclass 3, count 0 2006.225.07:31:07.90#ibcon#about to read 4, iclass 3, count 0 2006.225.07:31:07.90#ibcon#read 4, iclass 3, count 0 2006.225.07:31:07.90#ibcon#about to read 5, iclass 3, count 0 2006.225.07:31:07.90#ibcon#read 5, iclass 3, count 0 2006.225.07:31:07.90#ibcon#about to read 6, iclass 3, count 0 2006.225.07:31:07.90#ibcon#read 6, iclass 3, count 0 2006.225.07:31:07.90#ibcon#end of sib2, iclass 3, count 0 2006.225.07:31:07.90#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:31:07.90#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:31:07.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:31:07.90#ibcon#*before write, iclass 3, count 0 2006.225.07:31:07.90#ibcon#enter sib2, iclass 3, count 0 2006.225.07:31:07.90#ibcon#flushed, iclass 3, count 0 2006.225.07:31:07.90#ibcon#about to write, iclass 3, count 0 2006.225.07:31:07.90#ibcon#wrote, iclass 3, count 0 2006.225.07:31:07.90#ibcon#about to read 3, iclass 3, count 0 2006.225.07:31:07.94#ibcon#read 3, iclass 3, count 0 2006.225.07:31:07.94#ibcon#about to read 4, iclass 3, count 0 2006.225.07:31:07.94#ibcon#read 4, iclass 3, count 0 2006.225.07:31:07.94#ibcon#about to read 5, iclass 3, count 0 2006.225.07:31:07.94#ibcon#read 5, iclass 3, count 0 2006.225.07:31:07.94#ibcon#about to read 6, iclass 3, count 0 2006.225.07:31:07.94#ibcon#read 6, iclass 3, count 0 2006.225.07:31:07.94#ibcon#end of sib2, iclass 3, count 0 2006.225.07:31:07.94#ibcon#*after write, iclass 3, count 0 2006.225.07:31:07.94#ibcon#*before return 0, iclass 3, count 0 2006.225.07:31:07.94#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:31:07.94#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:31:07.94#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:31:07.94#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:31:07.94$vc4f8/va=4,7 2006.225.07:31:07.94#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.07:31:07.94#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.07:31:07.94#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:07.94#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:31:07.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:31:07.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:31:07.99#ibcon#enter wrdev, iclass 5, count 2 2006.225.07:31:07.99#ibcon#first serial, iclass 5, count 2 2006.225.07:31:07.99#ibcon#enter sib2, iclass 5, count 2 2006.225.07:31:07.99#ibcon#flushed, iclass 5, count 2 2006.225.07:31:07.99#ibcon#about to write, iclass 5, count 2 2006.225.07:31:07.99#ibcon#wrote, iclass 5, count 2 2006.225.07:31:07.99#ibcon#about to read 3, iclass 5, count 2 2006.225.07:31:08.01#ibcon#read 3, iclass 5, count 2 2006.225.07:31:08.01#ibcon#about to read 4, iclass 5, count 2 2006.225.07:31:08.01#ibcon#read 4, iclass 5, count 2 2006.225.07:31:08.01#ibcon#about to read 5, iclass 5, count 2 2006.225.07:31:08.01#ibcon#read 5, iclass 5, count 2 2006.225.07:31:08.01#ibcon#about to read 6, iclass 5, count 2 2006.225.07:31:08.01#ibcon#read 6, iclass 5, count 2 2006.225.07:31:08.01#ibcon#end of sib2, iclass 5, count 2 2006.225.07:31:08.01#ibcon#*mode == 0, iclass 5, count 2 2006.225.07:31:08.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.07:31:08.01#ibcon#[25=AT04-07\r\n] 2006.225.07:31:08.01#ibcon#*before write, iclass 5, count 2 2006.225.07:31:08.01#ibcon#enter sib2, iclass 5, count 2 2006.225.07:31:08.01#ibcon#flushed, iclass 5, count 2 2006.225.07:31:08.01#ibcon#about to write, iclass 5, count 2 2006.225.07:31:08.01#ibcon#wrote, iclass 5, count 2 2006.225.07:31:08.01#ibcon#about to read 3, iclass 5, count 2 2006.225.07:31:08.04#ibcon#read 3, iclass 5, count 2 2006.225.07:31:08.04#ibcon#about to read 4, iclass 5, count 2 2006.225.07:31:08.04#ibcon#read 4, iclass 5, count 2 2006.225.07:31:08.04#ibcon#about to read 5, iclass 5, count 2 2006.225.07:31:08.04#ibcon#read 5, iclass 5, count 2 2006.225.07:31:08.04#ibcon#about to read 6, iclass 5, count 2 2006.225.07:31:08.04#ibcon#read 6, iclass 5, count 2 2006.225.07:31:08.04#ibcon#end of sib2, iclass 5, count 2 2006.225.07:31:08.04#ibcon#*after write, iclass 5, count 2 2006.225.07:31:08.04#ibcon#*before return 0, iclass 5, count 2 2006.225.07:31:08.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:31:08.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:31:08.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.07:31:08.04#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:08.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:31:08.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:31:08.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:31:08.16#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:31:08.16#ibcon#first serial, iclass 5, count 0 2006.225.07:31:08.16#ibcon#enter sib2, iclass 5, count 0 2006.225.07:31:08.16#ibcon#flushed, iclass 5, count 0 2006.225.07:31:08.16#ibcon#about to write, iclass 5, count 0 2006.225.07:31:08.16#ibcon#wrote, iclass 5, count 0 2006.225.07:31:08.16#ibcon#about to read 3, iclass 5, count 0 2006.225.07:31:08.18#ibcon#read 3, iclass 5, count 0 2006.225.07:31:08.18#ibcon#about to read 4, iclass 5, count 0 2006.225.07:31:08.18#ibcon#read 4, iclass 5, count 0 2006.225.07:31:08.18#ibcon#about to read 5, iclass 5, count 0 2006.225.07:31:08.18#ibcon#read 5, iclass 5, count 0 2006.225.07:31:08.18#ibcon#about to read 6, iclass 5, count 0 2006.225.07:31:08.18#ibcon#read 6, iclass 5, count 0 2006.225.07:31:08.18#ibcon#end of sib2, iclass 5, count 0 2006.225.07:31:08.18#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:31:08.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:31:08.18#ibcon#[25=USB\r\n] 2006.225.07:31:08.18#ibcon#*before write, iclass 5, count 0 2006.225.07:31:08.18#ibcon#enter sib2, iclass 5, count 0 2006.225.07:31:08.18#ibcon#flushed, iclass 5, count 0 2006.225.07:31:08.18#ibcon#about to write, iclass 5, count 0 2006.225.07:31:08.18#ibcon#wrote, iclass 5, count 0 2006.225.07:31:08.18#ibcon#about to read 3, iclass 5, count 0 2006.225.07:31:08.21#ibcon#read 3, iclass 5, count 0 2006.225.07:31:08.21#ibcon#about to read 4, iclass 5, count 0 2006.225.07:31:08.21#ibcon#read 4, iclass 5, count 0 2006.225.07:31:08.21#ibcon#about to read 5, iclass 5, count 0 2006.225.07:31:08.21#ibcon#read 5, iclass 5, count 0 2006.225.07:31:08.21#ibcon#about to read 6, iclass 5, count 0 2006.225.07:31:08.21#ibcon#read 6, iclass 5, count 0 2006.225.07:31:08.21#ibcon#end of sib2, iclass 5, count 0 2006.225.07:31:08.21#ibcon#*after write, iclass 5, count 0 2006.225.07:31:08.21#ibcon#*before return 0, iclass 5, count 0 2006.225.07:31:08.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:31:08.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:31:08.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:31:08.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:31:08.21$vc4f8/valo=5,652.99 2006.225.07:31:08.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.225.07:31:08.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.225.07:31:08.21#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:08.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:31:08.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:31:08.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:31:08.21#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:31:08.21#ibcon#first serial, iclass 7, count 0 2006.225.07:31:08.21#ibcon#enter sib2, iclass 7, count 0 2006.225.07:31:08.21#ibcon#flushed, iclass 7, count 0 2006.225.07:31:08.21#ibcon#about to write, iclass 7, count 0 2006.225.07:31:08.21#ibcon#wrote, iclass 7, count 0 2006.225.07:31:08.21#ibcon#about to read 3, iclass 7, count 0 2006.225.07:31:08.23#ibcon#read 3, iclass 7, count 0 2006.225.07:31:08.23#ibcon#about to read 4, iclass 7, count 0 2006.225.07:31:08.23#ibcon#read 4, iclass 7, count 0 2006.225.07:31:08.23#ibcon#about to read 5, iclass 7, count 0 2006.225.07:31:08.23#ibcon#read 5, iclass 7, count 0 2006.225.07:31:08.23#ibcon#about to read 6, iclass 7, count 0 2006.225.07:31:08.23#ibcon#read 6, iclass 7, count 0 2006.225.07:31:08.23#ibcon#end of sib2, iclass 7, count 0 2006.225.07:31:08.23#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:31:08.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:31:08.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:31:08.23#ibcon#*before write, iclass 7, count 0 2006.225.07:31:08.23#ibcon#enter sib2, iclass 7, count 0 2006.225.07:31:08.23#ibcon#flushed, iclass 7, count 0 2006.225.07:31:08.23#ibcon#about to write, iclass 7, count 0 2006.225.07:31:08.23#ibcon#wrote, iclass 7, count 0 2006.225.07:31:08.23#ibcon#about to read 3, iclass 7, count 0 2006.225.07:31:08.27#ibcon#read 3, iclass 7, count 0 2006.225.07:31:08.27#ibcon#about to read 4, iclass 7, count 0 2006.225.07:31:08.27#ibcon#read 4, iclass 7, count 0 2006.225.07:31:08.27#ibcon#about to read 5, iclass 7, count 0 2006.225.07:31:08.27#ibcon#read 5, iclass 7, count 0 2006.225.07:31:08.27#ibcon#about to read 6, iclass 7, count 0 2006.225.07:31:08.27#ibcon#read 6, iclass 7, count 0 2006.225.07:31:08.27#ibcon#end of sib2, iclass 7, count 0 2006.225.07:31:08.27#ibcon#*after write, iclass 7, count 0 2006.225.07:31:08.27#ibcon#*before return 0, iclass 7, count 0 2006.225.07:31:08.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:31:08.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:31:08.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:31:08.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:31:08.27$vc4f8/va=5,7 2006.225.07:31:08.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.225.07:31:08.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.225.07:31:08.27#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:08.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:31:08.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:31:08.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:31:08.33#ibcon#enter wrdev, iclass 11, count 2 2006.225.07:31:08.33#ibcon#first serial, iclass 11, count 2 2006.225.07:31:08.33#ibcon#enter sib2, iclass 11, count 2 2006.225.07:31:08.33#ibcon#flushed, iclass 11, count 2 2006.225.07:31:08.33#ibcon#about to write, iclass 11, count 2 2006.225.07:31:08.33#ibcon#wrote, iclass 11, count 2 2006.225.07:31:08.33#ibcon#about to read 3, iclass 11, count 2 2006.225.07:31:08.35#ibcon#read 3, iclass 11, count 2 2006.225.07:31:08.35#ibcon#about to read 4, iclass 11, count 2 2006.225.07:31:08.35#ibcon#read 4, iclass 11, count 2 2006.225.07:31:08.35#ibcon#about to read 5, iclass 11, count 2 2006.225.07:31:08.35#ibcon#read 5, iclass 11, count 2 2006.225.07:31:08.35#ibcon#about to read 6, iclass 11, count 2 2006.225.07:31:08.35#ibcon#read 6, iclass 11, count 2 2006.225.07:31:08.35#ibcon#end of sib2, iclass 11, count 2 2006.225.07:31:08.35#ibcon#*mode == 0, iclass 11, count 2 2006.225.07:31:08.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.225.07:31:08.35#ibcon#[25=AT05-07\r\n] 2006.225.07:31:08.35#ibcon#*before write, iclass 11, count 2 2006.225.07:31:08.35#ibcon#enter sib2, iclass 11, count 2 2006.225.07:31:08.35#ibcon#flushed, iclass 11, count 2 2006.225.07:31:08.35#ibcon#about to write, iclass 11, count 2 2006.225.07:31:08.35#ibcon#wrote, iclass 11, count 2 2006.225.07:31:08.35#ibcon#about to read 3, iclass 11, count 2 2006.225.07:31:08.38#ibcon#read 3, iclass 11, count 2 2006.225.07:31:08.38#ibcon#about to read 4, iclass 11, count 2 2006.225.07:31:08.38#ibcon#read 4, iclass 11, count 2 2006.225.07:31:08.38#ibcon#about to read 5, iclass 11, count 2 2006.225.07:31:08.38#ibcon#read 5, iclass 11, count 2 2006.225.07:31:08.38#ibcon#about to read 6, iclass 11, count 2 2006.225.07:31:08.38#ibcon#read 6, iclass 11, count 2 2006.225.07:31:08.38#ibcon#end of sib2, iclass 11, count 2 2006.225.07:31:08.38#ibcon#*after write, iclass 11, count 2 2006.225.07:31:08.38#ibcon#*before return 0, iclass 11, count 2 2006.225.07:31:08.38#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:31:08.38#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:31:08.38#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.225.07:31:08.38#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:08.38#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:31:08.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:31:08.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:31:08.50#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:31:08.50#ibcon#first serial, iclass 11, count 0 2006.225.07:31:08.50#ibcon#enter sib2, iclass 11, count 0 2006.225.07:31:08.50#ibcon#flushed, iclass 11, count 0 2006.225.07:31:08.50#ibcon#about to write, iclass 11, count 0 2006.225.07:31:08.50#ibcon#wrote, iclass 11, count 0 2006.225.07:31:08.50#ibcon#about to read 3, iclass 11, count 0 2006.225.07:31:08.52#ibcon#read 3, iclass 11, count 0 2006.225.07:31:08.52#ibcon#about to read 4, iclass 11, count 0 2006.225.07:31:08.52#ibcon#read 4, iclass 11, count 0 2006.225.07:31:08.52#ibcon#about to read 5, iclass 11, count 0 2006.225.07:31:08.52#ibcon#read 5, iclass 11, count 0 2006.225.07:31:08.52#ibcon#about to read 6, iclass 11, count 0 2006.225.07:31:08.52#ibcon#read 6, iclass 11, count 0 2006.225.07:31:08.52#ibcon#end of sib2, iclass 11, count 0 2006.225.07:31:08.52#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:31:08.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:31:08.52#ibcon#[25=USB\r\n] 2006.225.07:31:08.52#ibcon#*before write, iclass 11, count 0 2006.225.07:31:08.52#ibcon#enter sib2, iclass 11, count 0 2006.225.07:31:08.52#ibcon#flushed, iclass 11, count 0 2006.225.07:31:08.52#ibcon#about to write, iclass 11, count 0 2006.225.07:31:08.52#ibcon#wrote, iclass 11, count 0 2006.225.07:31:08.52#ibcon#about to read 3, iclass 11, count 0 2006.225.07:31:08.55#ibcon#read 3, iclass 11, count 0 2006.225.07:31:08.55#ibcon#about to read 4, iclass 11, count 0 2006.225.07:31:08.55#ibcon#read 4, iclass 11, count 0 2006.225.07:31:08.55#ibcon#about to read 5, iclass 11, count 0 2006.225.07:31:08.55#ibcon#read 5, iclass 11, count 0 2006.225.07:31:08.55#ibcon#about to read 6, iclass 11, count 0 2006.225.07:31:08.55#ibcon#read 6, iclass 11, count 0 2006.225.07:31:08.55#ibcon#end of sib2, iclass 11, count 0 2006.225.07:31:08.55#ibcon#*after write, iclass 11, count 0 2006.225.07:31:08.55#ibcon#*before return 0, iclass 11, count 0 2006.225.07:31:08.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:31:08.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:31:08.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:31:08.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:31:08.55$vc4f8/valo=6,772.99 2006.225.07:31:08.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.07:31:08.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.07:31:08.55#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:08.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:31:08.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:31:08.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:31:08.55#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:31:08.55#ibcon#first serial, iclass 13, count 0 2006.225.07:31:08.55#ibcon#enter sib2, iclass 13, count 0 2006.225.07:31:08.55#ibcon#flushed, iclass 13, count 0 2006.225.07:31:08.55#ibcon#about to write, iclass 13, count 0 2006.225.07:31:08.55#ibcon#wrote, iclass 13, count 0 2006.225.07:31:08.55#ibcon#about to read 3, iclass 13, count 0 2006.225.07:31:08.57#ibcon#read 3, iclass 13, count 0 2006.225.07:31:08.57#ibcon#about to read 4, iclass 13, count 0 2006.225.07:31:08.57#ibcon#read 4, iclass 13, count 0 2006.225.07:31:08.57#ibcon#about to read 5, iclass 13, count 0 2006.225.07:31:08.57#ibcon#read 5, iclass 13, count 0 2006.225.07:31:08.57#ibcon#about to read 6, iclass 13, count 0 2006.225.07:31:08.57#ibcon#read 6, iclass 13, count 0 2006.225.07:31:08.57#ibcon#end of sib2, iclass 13, count 0 2006.225.07:31:08.57#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:31:08.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:31:08.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:31:08.57#ibcon#*before write, iclass 13, count 0 2006.225.07:31:08.57#ibcon#enter sib2, iclass 13, count 0 2006.225.07:31:08.57#ibcon#flushed, iclass 13, count 0 2006.225.07:31:08.57#ibcon#about to write, iclass 13, count 0 2006.225.07:31:08.57#ibcon#wrote, iclass 13, count 0 2006.225.07:31:08.57#ibcon#about to read 3, iclass 13, count 0 2006.225.07:31:08.61#ibcon#read 3, iclass 13, count 0 2006.225.07:31:08.61#ibcon#about to read 4, iclass 13, count 0 2006.225.07:31:08.61#ibcon#read 4, iclass 13, count 0 2006.225.07:31:08.61#ibcon#about to read 5, iclass 13, count 0 2006.225.07:31:08.61#ibcon#read 5, iclass 13, count 0 2006.225.07:31:08.61#ibcon#about to read 6, iclass 13, count 0 2006.225.07:31:08.61#ibcon#read 6, iclass 13, count 0 2006.225.07:31:08.61#ibcon#end of sib2, iclass 13, count 0 2006.225.07:31:08.61#ibcon#*after write, iclass 13, count 0 2006.225.07:31:08.61#ibcon#*before return 0, iclass 13, count 0 2006.225.07:31:08.61#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:31:08.61#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:31:08.61#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:31:08.61#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:31:08.61$vc4f8/va=6,6 2006.225.07:31:08.61#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.225.07:31:08.61#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.225.07:31:08.61#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:08.61#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:31:08.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:31:08.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:31:08.67#ibcon#enter wrdev, iclass 15, count 2 2006.225.07:31:08.67#ibcon#first serial, iclass 15, count 2 2006.225.07:31:08.67#ibcon#enter sib2, iclass 15, count 2 2006.225.07:31:08.67#ibcon#flushed, iclass 15, count 2 2006.225.07:31:08.67#ibcon#about to write, iclass 15, count 2 2006.225.07:31:08.67#ibcon#wrote, iclass 15, count 2 2006.225.07:31:08.67#ibcon#about to read 3, iclass 15, count 2 2006.225.07:31:08.69#ibcon#read 3, iclass 15, count 2 2006.225.07:31:08.69#ibcon#about to read 4, iclass 15, count 2 2006.225.07:31:08.69#ibcon#read 4, iclass 15, count 2 2006.225.07:31:08.69#ibcon#about to read 5, iclass 15, count 2 2006.225.07:31:08.69#ibcon#read 5, iclass 15, count 2 2006.225.07:31:08.69#ibcon#about to read 6, iclass 15, count 2 2006.225.07:31:08.69#ibcon#read 6, iclass 15, count 2 2006.225.07:31:08.69#ibcon#end of sib2, iclass 15, count 2 2006.225.07:31:08.69#ibcon#*mode == 0, iclass 15, count 2 2006.225.07:31:08.69#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.225.07:31:08.69#ibcon#[25=AT06-06\r\n] 2006.225.07:31:08.69#ibcon#*before write, iclass 15, count 2 2006.225.07:31:08.69#ibcon#enter sib2, iclass 15, count 2 2006.225.07:31:08.69#ibcon#flushed, iclass 15, count 2 2006.225.07:31:08.69#ibcon#about to write, iclass 15, count 2 2006.225.07:31:08.69#ibcon#wrote, iclass 15, count 2 2006.225.07:31:08.69#ibcon#about to read 3, iclass 15, count 2 2006.225.07:31:08.72#ibcon#read 3, iclass 15, count 2 2006.225.07:31:08.72#ibcon#about to read 4, iclass 15, count 2 2006.225.07:31:08.72#ibcon#read 4, iclass 15, count 2 2006.225.07:31:08.72#ibcon#about to read 5, iclass 15, count 2 2006.225.07:31:08.72#ibcon#read 5, iclass 15, count 2 2006.225.07:31:08.72#ibcon#about to read 6, iclass 15, count 2 2006.225.07:31:08.72#ibcon#read 6, iclass 15, count 2 2006.225.07:31:08.72#ibcon#end of sib2, iclass 15, count 2 2006.225.07:31:08.72#ibcon#*after write, iclass 15, count 2 2006.225.07:31:08.72#ibcon#*before return 0, iclass 15, count 2 2006.225.07:31:08.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:31:08.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:31:08.72#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.225.07:31:08.72#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:08.72#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:31:08.84#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:31:08.84#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:31:08.84#ibcon#enter wrdev, iclass 15, count 0 2006.225.07:31:08.84#ibcon#first serial, iclass 15, count 0 2006.225.07:31:08.84#ibcon#enter sib2, iclass 15, count 0 2006.225.07:31:08.84#ibcon#flushed, iclass 15, count 0 2006.225.07:31:08.84#ibcon#about to write, iclass 15, count 0 2006.225.07:31:08.84#ibcon#wrote, iclass 15, count 0 2006.225.07:31:08.84#ibcon#about to read 3, iclass 15, count 0 2006.225.07:31:08.86#ibcon#read 3, iclass 15, count 0 2006.225.07:31:08.86#ibcon#about to read 4, iclass 15, count 0 2006.225.07:31:08.86#ibcon#read 4, iclass 15, count 0 2006.225.07:31:08.86#ibcon#about to read 5, iclass 15, count 0 2006.225.07:31:08.86#ibcon#read 5, iclass 15, count 0 2006.225.07:31:08.86#ibcon#about to read 6, iclass 15, count 0 2006.225.07:31:08.86#ibcon#read 6, iclass 15, count 0 2006.225.07:31:08.86#ibcon#end of sib2, iclass 15, count 0 2006.225.07:31:08.86#ibcon#*mode == 0, iclass 15, count 0 2006.225.07:31:08.86#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.07:31:08.86#ibcon#[25=USB\r\n] 2006.225.07:31:08.86#ibcon#*before write, iclass 15, count 0 2006.225.07:31:08.86#ibcon#enter sib2, iclass 15, count 0 2006.225.07:31:08.86#ibcon#flushed, iclass 15, count 0 2006.225.07:31:08.86#ibcon#about to write, iclass 15, count 0 2006.225.07:31:08.86#ibcon#wrote, iclass 15, count 0 2006.225.07:31:08.86#ibcon#about to read 3, iclass 15, count 0 2006.225.07:31:08.89#ibcon#read 3, iclass 15, count 0 2006.225.07:31:08.89#ibcon#about to read 4, iclass 15, count 0 2006.225.07:31:08.89#ibcon#read 4, iclass 15, count 0 2006.225.07:31:08.89#ibcon#about to read 5, iclass 15, count 0 2006.225.07:31:08.89#ibcon#read 5, iclass 15, count 0 2006.225.07:31:08.89#ibcon#about to read 6, iclass 15, count 0 2006.225.07:31:08.89#ibcon#read 6, iclass 15, count 0 2006.225.07:31:08.89#ibcon#end of sib2, iclass 15, count 0 2006.225.07:31:08.89#ibcon#*after write, iclass 15, count 0 2006.225.07:31:08.89#ibcon#*before return 0, iclass 15, count 0 2006.225.07:31:08.89#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:31:08.89#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:31:08.89#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.07:31:08.89#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.07:31:08.89$vc4f8/valo=7,832.99 2006.225.07:31:08.89#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.225.07:31:08.89#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.225.07:31:08.89#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:08.89#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:31:08.89#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:31:08.89#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:31:08.89#ibcon#enter wrdev, iclass 17, count 0 2006.225.07:31:08.89#ibcon#first serial, iclass 17, count 0 2006.225.07:31:08.89#ibcon#enter sib2, iclass 17, count 0 2006.225.07:31:08.89#ibcon#flushed, iclass 17, count 0 2006.225.07:31:08.89#ibcon#about to write, iclass 17, count 0 2006.225.07:31:08.89#ibcon#wrote, iclass 17, count 0 2006.225.07:31:08.89#ibcon#about to read 3, iclass 17, count 0 2006.225.07:31:08.91#ibcon#read 3, iclass 17, count 0 2006.225.07:31:08.91#ibcon#about to read 4, iclass 17, count 0 2006.225.07:31:08.91#ibcon#read 4, iclass 17, count 0 2006.225.07:31:08.91#ibcon#about to read 5, iclass 17, count 0 2006.225.07:31:08.91#ibcon#read 5, iclass 17, count 0 2006.225.07:31:08.91#ibcon#about to read 6, iclass 17, count 0 2006.225.07:31:08.91#ibcon#read 6, iclass 17, count 0 2006.225.07:31:08.91#ibcon#end of sib2, iclass 17, count 0 2006.225.07:31:08.91#ibcon#*mode == 0, iclass 17, count 0 2006.225.07:31:08.91#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.07:31:08.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:31:08.91#ibcon#*before write, iclass 17, count 0 2006.225.07:31:08.91#ibcon#enter sib2, iclass 17, count 0 2006.225.07:31:08.91#ibcon#flushed, iclass 17, count 0 2006.225.07:31:08.91#ibcon#about to write, iclass 17, count 0 2006.225.07:31:08.91#ibcon#wrote, iclass 17, count 0 2006.225.07:31:08.91#ibcon#about to read 3, iclass 17, count 0 2006.225.07:31:08.95#ibcon#read 3, iclass 17, count 0 2006.225.07:31:08.95#ibcon#about to read 4, iclass 17, count 0 2006.225.07:31:08.95#ibcon#read 4, iclass 17, count 0 2006.225.07:31:08.95#ibcon#about to read 5, iclass 17, count 0 2006.225.07:31:08.95#ibcon#read 5, iclass 17, count 0 2006.225.07:31:08.95#ibcon#about to read 6, iclass 17, count 0 2006.225.07:31:08.95#ibcon#read 6, iclass 17, count 0 2006.225.07:31:08.95#ibcon#end of sib2, iclass 17, count 0 2006.225.07:31:08.95#ibcon#*after write, iclass 17, count 0 2006.225.07:31:08.95#ibcon#*before return 0, iclass 17, count 0 2006.225.07:31:08.95#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:31:08.95#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:31:08.95#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.07:31:08.95#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.07:31:08.95$vc4f8/va=7,6 2006.225.07:31:08.95#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.225.07:31:08.95#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.225.07:31:08.95#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:08.95#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:31:09.01#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:31:09.01#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:31:09.01#ibcon#enter wrdev, iclass 19, count 2 2006.225.07:31:09.01#ibcon#first serial, iclass 19, count 2 2006.225.07:31:09.01#ibcon#enter sib2, iclass 19, count 2 2006.225.07:31:09.01#ibcon#flushed, iclass 19, count 2 2006.225.07:31:09.01#ibcon#about to write, iclass 19, count 2 2006.225.07:31:09.01#ibcon#wrote, iclass 19, count 2 2006.225.07:31:09.01#ibcon#about to read 3, iclass 19, count 2 2006.225.07:31:09.03#ibcon#read 3, iclass 19, count 2 2006.225.07:31:09.03#ibcon#about to read 4, iclass 19, count 2 2006.225.07:31:09.03#ibcon#read 4, iclass 19, count 2 2006.225.07:31:09.03#ibcon#about to read 5, iclass 19, count 2 2006.225.07:31:09.03#ibcon#read 5, iclass 19, count 2 2006.225.07:31:09.03#ibcon#about to read 6, iclass 19, count 2 2006.225.07:31:09.03#ibcon#read 6, iclass 19, count 2 2006.225.07:31:09.03#ibcon#end of sib2, iclass 19, count 2 2006.225.07:31:09.03#ibcon#*mode == 0, iclass 19, count 2 2006.225.07:31:09.03#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.225.07:31:09.03#ibcon#[25=AT07-06\r\n] 2006.225.07:31:09.03#ibcon#*before write, iclass 19, count 2 2006.225.07:31:09.03#ibcon#enter sib2, iclass 19, count 2 2006.225.07:31:09.03#ibcon#flushed, iclass 19, count 2 2006.225.07:31:09.03#ibcon#about to write, iclass 19, count 2 2006.225.07:31:09.03#ibcon#wrote, iclass 19, count 2 2006.225.07:31:09.03#ibcon#about to read 3, iclass 19, count 2 2006.225.07:31:09.06#ibcon#read 3, iclass 19, count 2 2006.225.07:31:09.06#ibcon#about to read 4, iclass 19, count 2 2006.225.07:31:09.06#ibcon#read 4, iclass 19, count 2 2006.225.07:31:09.06#ibcon#about to read 5, iclass 19, count 2 2006.225.07:31:09.06#ibcon#read 5, iclass 19, count 2 2006.225.07:31:09.06#ibcon#about to read 6, iclass 19, count 2 2006.225.07:31:09.06#ibcon#read 6, iclass 19, count 2 2006.225.07:31:09.06#ibcon#end of sib2, iclass 19, count 2 2006.225.07:31:09.06#ibcon#*after write, iclass 19, count 2 2006.225.07:31:09.06#ibcon#*before return 0, iclass 19, count 2 2006.225.07:31:09.06#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:31:09.06#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:31:09.06#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.225.07:31:09.06#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:09.06#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:31:09.18#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:31:09.18#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:31:09.18#ibcon#enter wrdev, iclass 19, count 0 2006.225.07:31:09.18#ibcon#first serial, iclass 19, count 0 2006.225.07:31:09.18#ibcon#enter sib2, iclass 19, count 0 2006.225.07:31:09.18#ibcon#flushed, iclass 19, count 0 2006.225.07:31:09.18#ibcon#about to write, iclass 19, count 0 2006.225.07:31:09.18#ibcon#wrote, iclass 19, count 0 2006.225.07:31:09.18#ibcon#about to read 3, iclass 19, count 0 2006.225.07:31:09.20#ibcon#read 3, iclass 19, count 0 2006.225.07:31:09.20#ibcon#about to read 4, iclass 19, count 0 2006.225.07:31:09.20#ibcon#read 4, iclass 19, count 0 2006.225.07:31:09.20#ibcon#about to read 5, iclass 19, count 0 2006.225.07:31:09.20#ibcon#read 5, iclass 19, count 0 2006.225.07:31:09.20#ibcon#about to read 6, iclass 19, count 0 2006.225.07:31:09.20#ibcon#read 6, iclass 19, count 0 2006.225.07:31:09.20#ibcon#end of sib2, iclass 19, count 0 2006.225.07:31:09.20#ibcon#*mode == 0, iclass 19, count 0 2006.225.07:31:09.20#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.07:31:09.20#ibcon#[25=USB\r\n] 2006.225.07:31:09.20#ibcon#*before write, iclass 19, count 0 2006.225.07:31:09.20#ibcon#enter sib2, iclass 19, count 0 2006.225.07:31:09.20#ibcon#flushed, iclass 19, count 0 2006.225.07:31:09.20#ibcon#about to write, iclass 19, count 0 2006.225.07:31:09.20#ibcon#wrote, iclass 19, count 0 2006.225.07:31:09.20#ibcon#about to read 3, iclass 19, count 0 2006.225.07:31:09.23#ibcon#read 3, iclass 19, count 0 2006.225.07:31:09.23#ibcon#about to read 4, iclass 19, count 0 2006.225.07:31:09.23#ibcon#read 4, iclass 19, count 0 2006.225.07:31:09.23#ibcon#about to read 5, iclass 19, count 0 2006.225.07:31:09.23#ibcon#read 5, iclass 19, count 0 2006.225.07:31:09.23#ibcon#about to read 6, iclass 19, count 0 2006.225.07:31:09.23#ibcon#read 6, iclass 19, count 0 2006.225.07:31:09.23#ibcon#end of sib2, iclass 19, count 0 2006.225.07:31:09.23#ibcon#*after write, iclass 19, count 0 2006.225.07:31:09.23#ibcon#*before return 0, iclass 19, count 0 2006.225.07:31:09.23#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:31:09.23#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:31:09.23#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.07:31:09.23#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.07:31:09.23$vc4f8/valo=8,852.99 2006.225.07:31:09.23#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.225.07:31:09.23#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.225.07:31:09.23#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:09.23#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:31:09.23#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:31:09.23#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:31:09.23#ibcon#enter wrdev, iclass 21, count 0 2006.225.07:31:09.23#ibcon#first serial, iclass 21, count 0 2006.225.07:31:09.23#ibcon#enter sib2, iclass 21, count 0 2006.225.07:31:09.23#ibcon#flushed, iclass 21, count 0 2006.225.07:31:09.23#ibcon#about to write, iclass 21, count 0 2006.225.07:31:09.23#ibcon#wrote, iclass 21, count 0 2006.225.07:31:09.23#ibcon#about to read 3, iclass 21, count 0 2006.225.07:31:09.25#ibcon#read 3, iclass 21, count 0 2006.225.07:31:09.25#ibcon#about to read 4, iclass 21, count 0 2006.225.07:31:09.25#ibcon#read 4, iclass 21, count 0 2006.225.07:31:09.25#ibcon#about to read 5, iclass 21, count 0 2006.225.07:31:09.25#ibcon#read 5, iclass 21, count 0 2006.225.07:31:09.25#ibcon#about to read 6, iclass 21, count 0 2006.225.07:31:09.25#ibcon#read 6, iclass 21, count 0 2006.225.07:31:09.25#ibcon#end of sib2, iclass 21, count 0 2006.225.07:31:09.25#ibcon#*mode == 0, iclass 21, count 0 2006.225.07:31:09.25#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.07:31:09.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:31:09.25#ibcon#*before write, iclass 21, count 0 2006.225.07:31:09.25#ibcon#enter sib2, iclass 21, count 0 2006.225.07:31:09.25#ibcon#flushed, iclass 21, count 0 2006.225.07:31:09.25#ibcon#about to write, iclass 21, count 0 2006.225.07:31:09.25#ibcon#wrote, iclass 21, count 0 2006.225.07:31:09.25#ibcon#about to read 3, iclass 21, count 0 2006.225.07:31:09.29#ibcon#read 3, iclass 21, count 0 2006.225.07:31:09.29#ibcon#about to read 4, iclass 21, count 0 2006.225.07:31:09.29#ibcon#read 4, iclass 21, count 0 2006.225.07:31:09.29#ibcon#about to read 5, iclass 21, count 0 2006.225.07:31:09.29#ibcon#read 5, iclass 21, count 0 2006.225.07:31:09.29#ibcon#about to read 6, iclass 21, count 0 2006.225.07:31:09.29#ibcon#read 6, iclass 21, count 0 2006.225.07:31:09.29#ibcon#end of sib2, iclass 21, count 0 2006.225.07:31:09.29#ibcon#*after write, iclass 21, count 0 2006.225.07:31:09.29#ibcon#*before return 0, iclass 21, count 0 2006.225.07:31:09.29#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:31:09.29#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:31:09.29#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.07:31:09.29#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.07:31:09.29$vc4f8/va=8,7 2006.225.07:31:09.29#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.225.07:31:09.29#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.225.07:31:09.29#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:09.29#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:31:09.35#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:31:09.35#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:31:09.35#ibcon#enter wrdev, iclass 23, count 2 2006.225.07:31:09.35#ibcon#first serial, iclass 23, count 2 2006.225.07:31:09.35#ibcon#enter sib2, iclass 23, count 2 2006.225.07:31:09.35#ibcon#flushed, iclass 23, count 2 2006.225.07:31:09.35#ibcon#about to write, iclass 23, count 2 2006.225.07:31:09.35#ibcon#wrote, iclass 23, count 2 2006.225.07:31:09.35#ibcon#about to read 3, iclass 23, count 2 2006.225.07:31:09.37#ibcon#read 3, iclass 23, count 2 2006.225.07:31:09.37#ibcon#about to read 4, iclass 23, count 2 2006.225.07:31:09.37#ibcon#read 4, iclass 23, count 2 2006.225.07:31:09.37#ibcon#about to read 5, iclass 23, count 2 2006.225.07:31:09.37#ibcon#read 5, iclass 23, count 2 2006.225.07:31:09.37#ibcon#about to read 6, iclass 23, count 2 2006.225.07:31:09.37#ibcon#read 6, iclass 23, count 2 2006.225.07:31:09.37#ibcon#end of sib2, iclass 23, count 2 2006.225.07:31:09.37#ibcon#*mode == 0, iclass 23, count 2 2006.225.07:31:09.37#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.225.07:31:09.37#ibcon#[25=AT08-07\r\n] 2006.225.07:31:09.37#ibcon#*before write, iclass 23, count 2 2006.225.07:31:09.37#ibcon#enter sib2, iclass 23, count 2 2006.225.07:31:09.37#ibcon#flushed, iclass 23, count 2 2006.225.07:31:09.37#ibcon#about to write, iclass 23, count 2 2006.225.07:31:09.37#ibcon#wrote, iclass 23, count 2 2006.225.07:31:09.37#ibcon#about to read 3, iclass 23, count 2 2006.225.07:31:09.40#ibcon#read 3, iclass 23, count 2 2006.225.07:31:09.40#ibcon#about to read 4, iclass 23, count 2 2006.225.07:31:09.40#ibcon#read 4, iclass 23, count 2 2006.225.07:31:09.40#ibcon#about to read 5, iclass 23, count 2 2006.225.07:31:09.40#ibcon#read 5, iclass 23, count 2 2006.225.07:31:09.40#ibcon#about to read 6, iclass 23, count 2 2006.225.07:31:09.40#ibcon#read 6, iclass 23, count 2 2006.225.07:31:09.40#ibcon#end of sib2, iclass 23, count 2 2006.225.07:31:09.40#ibcon#*after write, iclass 23, count 2 2006.225.07:31:09.40#ibcon#*before return 0, iclass 23, count 2 2006.225.07:31:09.40#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:31:09.40#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:31:09.40#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.225.07:31:09.40#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:09.40#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:31:09.52#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:31:09.52#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:31:09.52#ibcon#enter wrdev, iclass 23, count 0 2006.225.07:31:09.52#ibcon#first serial, iclass 23, count 0 2006.225.07:31:09.52#ibcon#enter sib2, iclass 23, count 0 2006.225.07:31:09.52#ibcon#flushed, iclass 23, count 0 2006.225.07:31:09.52#ibcon#about to write, iclass 23, count 0 2006.225.07:31:09.52#ibcon#wrote, iclass 23, count 0 2006.225.07:31:09.52#ibcon#about to read 3, iclass 23, count 0 2006.225.07:31:09.54#ibcon#read 3, iclass 23, count 0 2006.225.07:31:09.54#ibcon#about to read 4, iclass 23, count 0 2006.225.07:31:09.54#ibcon#read 4, iclass 23, count 0 2006.225.07:31:09.54#ibcon#about to read 5, iclass 23, count 0 2006.225.07:31:09.54#ibcon#read 5, iclass 23, count 0 2006.225.07:31:09.54#ibcon#about to read 6, iclass 23, count 0 2006.225.07:31:09.54#ibcon#read 6, iclass 23, count 0 2006.225.07:31:09.54#ibcon#end of sib2, iclass 23, count 0 2006.225.07:31:09.54#ibcon#*mode == 0, iclass 23, count 0 2006.225.07:31:09.54#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.07:31:09.54#ibcon#[25=USB\r\n] 2006.225.07:31:09.54#ibcon#*before write, iclass 23, count 0 2006.225.07:31:09.54#ibcon#enter sib2, iclass 23, count 0 2006.225.07:31:09.54#ibcon#flushed, iclass 23, count 0 2006.225.07:31:09.54#ibcon#about to write, iclass 23, count 0 2006.225.07:31:09.54#ibcon#wrote, iclass 23, count 0 2006.225.07:31:09.54#ibcon#about to read 3, iclass 23, count 0 2006.225.07:31:09.57#ibcon#read 3, iclass 23, count 0 2006.225.07:31:09.57#ibcon#about to read 4, iclass 23, count 0 2006.225.07:31:09.57#ibcon#read 4, iclass 23, count 0 2006.225.07:31:09.57#ibcon#about to read 5, iclass 23, count 0 2006.225.07:31:09.57#ibcon#read 5, iclass 23, count 0 2006.225.07:31:09.57#ibcon#about to read 6, iclass 23, count 0 2006.225.07:31:09.57#ibcon#read 6, iclass 23, count 0 2006.225.07:31:09.57#ibcon#end of sib2, iclass 23, count 0 2006.225.07:31:09.57#ibcon#*after write, iclass 23, count 0 2006.225.07:31:09.57#ibcon#*before return 0, iclass 23, count 0 2006.225.07:31:09.57#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:31:09.57#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:31:09.57#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.07:31:09.57#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.07:31:09.57$vc4f8/vblo=1,632.99 2006.225.07:31:09.57#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.225.07:31:09.57#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.225.07:31:09.57#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:09.57#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:31:09.57#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:31:09.57#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:31:09.57#ibcon#enter wrdev, iclass 25, count 0 2006.225.07:31:09.57#ibcon#first serial, iclass 25, count 0 2006.225.07:31:09.57#ibcon#enter sib2, iclass 25, count 0 2006.225.07:31:09.57#ibcon#flushed, iclass 25, count 0 2006.225.07:31:09.57#ibcon#about to write, iclass 25, count 0 2006.225.07:31:09.57#ibcon#wrote, iclass 25, count 0 2006.225.07:31:09.57#ibcon#about to read 3, iclass 25, count 0 2006.225.07:31:09.59#ibcon#read 3, iclass 25, count 0 2006.225.07:31:09.59#ibcon#about to read 4, iclass 25, count 0 2006.225.07:31:09.59#ibcon#read 4, iclass 25, count 0 2006.225.07:31:09.59#ibcon#about to read 5, iclass 25, count 0 2006.225.07:31:09.59#ibcon#read 5, iclass 25, count 0 2006.225.07:31:09.59#ibcon#about to read 6, iclass 25, count 0 2006.225.07:31:09.59#ibcon#read 6, iclass 25, count 0 2006.225.07:31:09.59#ibcon#end of sib2, iclass 25, count 0 2006.225.07:31:09.59#ibcon#*mode == 0, iclass 25, count 0 2006.225.07:31:09.59#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.07:31:09.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:31:09.59#ibcon#*before write, iclass 25, count 0 2006.225.07:31:09.59#ibcon#enter sib2, iclass 25, count 0 2006.225.07:31:09.59#ibcon#flushed, iclass 25, count 0 2006.225.07:31:09.59#ibcon#about to write, iclass 25, count 0 2006.225.07:31:09.59#ibcon#wrote, iclass 25, count 0 2006.225.07:31:09.59#ibcon#about to read 3, iclass 25, count 0 2006.225.07:31:09.63#ibcon#read 3, iclass 25, count 0 2006.225.07:31:09.63#ibcon#about to read 4, iclass 25, count 0 2006.225.07:31:09.63#ibcon#read 4, iclass 25, count 0 2006.225.07:31:09.63#ibcon#about to read 5, iclass 25, count 0 2006.225.07:31:09.63#ibcon#read 5, iclass 25, count 0 2006.225.07:31:09.63#ibcon#about to read 6, iclass 25, count 0 2006.225.07:31:09.63#ibcon#read 6, iclass 25, count 0 2006.225.07:31:09.63#ibcon#end of sib2, iclass 25, count 0 2006.225.07:31:09.63#ibcon#*after write, iclass 25, count 0 2006.225.07:31:09.63#ibcon#*before return 0, iclass 25, count 0 2006.225.07:31:09.63#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:31:09.63#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:31:09.63#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.07:31:09.63#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.07:31:09.63$vc4f8/vb=1,4 2006.225.07:31:09.63#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.225.07:31:09.63#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.225.07:31:09.63#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:09.63#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:31:09.63#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:31:09.63#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:31:09.63#ibcon#enter wrdev, iclass 27, count 2 2006.225.07:31:09.63#ibcon#first serial, iclass 27, count 2 2006.225.07:31:09.63#ibcon#enter sib2, iclass 27, count 2 2006.225.07:31:09.63#ibcon#flushed, iclass 27, count 2 2006.225.07:31:09.63#ibcon#about to write, iclass 27, count 2 2006.225.07:31:09.63#ibcon#wrote, iclass 27, count 2 2006.225.07:31:09.63#ibcon#about to read 3, iclass 27, count 2 2006.225.07:31:09.65#ibcon#read 3, iclass 27, count 2 2006.225.07:31:09.65#ibcon#about to read 4, iclass 27, count 2 2006.225.07:31:09.65#ibcon#read 4, iclass 27, count 2 2006.225.07:31:09.65#ibcon#about to read 5, iclass 27, count 2 2006.225.07:31:09.65#ibcon#read 5, iclass 27, count 2 2006.225.07:31:09.65#ibcon#about to read 6, iclass 27, count 2 2006.225.07:31:09.65#ibcon#read 6, iclass 27, count 2 2006.225.07:31:09.65#ibcon#end of sib2, iclass 27, count 2 2006.225.07:31:09.65#ibcon#*mode == 0, iclass 27, count 2 2006.225.07:31:09.65#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.225.07:31:09.65#ibcon#[27=AT01-04\r\n] 2006.225.07:31:09.65#ibcon#*before write, iclass 27, count 2 2006.225.07:31:09.65#ibcon#enter sib2, iclass 27, count 2 2006.225.07:31:09.65#ibcon#flushed, iclass 27, count 2 2006.225.07:31:09.65#ibcon#about to write, iclass 27, count 2 2006.225.07:31:09.65#ibcon#wrote, iclass 27, count 2 2006.225.07:31:09.65#ibcon#about to read 3, iclass 27, count 2 2006.225.07:31:09.68#ibcon#read 3, iclass 27, count 2 2006.225.07:31:09.68#ibcon#about to read 4, iclass 27, count 2 2006.225.07:31:09.68#ibcon#read 4, iclass 27, count 2 2006.225.07:31:09.68#ibcon#about to read 5, iclass 27, count 2 2006.225.07:31:09.68#ibcon#read 5, iclass 27, count 2 2006.225.07:31:09.68#ibcon#about to read 6, iclass 27, count 2 2006.225.07:31:09.68#ibcon#read 6, iclass 27, count 2 2006.225.07:31:09.68#ibcon#end of sib2, iclass 27, count 2 2006.225.07:31:09.68#ibcon#*after write, iclass 27, count 2 2006.225.07:31:09.68#ibcon#*before return 0, iclass 27, count 2 2006.225.07:31:09.68#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:31:09.68#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:31:09.68#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.225.07:31:09.68#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:09.68#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:31:09.80#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:31:09.80#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:31:09.80#ibcon#enter wrdev, iclass 27, count 0 2006.225.07:31:09.80#ibcon#first serial, iclass 27, count 0 2006.225.07:31:09.80#ibcon#enter sib2, iclass 27, count 0 2006.225.07:31:09.80#ibcon#flushed, iclass 27, count 0 2006.225.07:31:09.80#ibcon#about to write, iclass 27, count 0 2006.225.07:31:09.80#ibcon#wrote, iclass 27, count 0 2006.225.07:31:09.80#ibcon#about to read 3, iclass 27, count 0 2006.225.07:31:09.82#ibcon#read 3, iclass 27, count 0 2006.225.07:31:09.82#ibcon#about to read 4, iclass 27, count 0 2006.225.07:31:09.82#ibcon#read 4, iclass 27, count 0 2006.225.07:31:09.82#ibcon#about to read 5, iclass 27, count 0 2006.225.07:31:09.82#ibcon#read 5, iclass 27, count 0 2006.225.07:31:09.82#ibcon#about to read 6, iclass 27, count 0 2006.225.07:31:09.82#ibcon#read 6, iclass 27, count 0 2006.225.07:31:09.82#ibcon#end of sib2, iclass 27, count 0 2006.225.07:31:09.82#ibcon#*mode == 0, iclass 27, count 0 2006.225.07:31:09.82#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.07:31:09.82#ibcon#[27=USB\r\n] 2006.225.07:31:09.82#ibcon#*before write, iclass 27, count 0 2006.225.07:31:09.82#ibcon#enter sib2, iclass 27, count 0 2006.225.07:31:09.82#ibcon#flushed, iclass 27, count 0 2006.225.07:31:09.82#ibcon#about to write, iclass 27, count 0 2006.225.07:31:09.82#ibcon#wrote, iclass 27, count 0 2006.225.07:31:09.82#ibcon#about to read 3, iclass 27, count 0 2006.225.07:31:09.85#ibcon#read 3, iclass 27, count 0 2006.225.07:31:09.85#ibcon#about to read 4, iclass 27, count 0 2006.225.07:31:09.85#ibcon#read 4, iclass 27, count 0 2006.225.07:31:09.85#ibcon#about to read 5, iclass 27, count 0 2006.225.07:31:09.85#ibcon#read 5, iclass 27, count 0 2006.225.07:31:09.85#ibcon#about to read 6, iclass 27, count 0 2006.225.07:31:09.85#ibcon#read 6, iclass 27, count 0 2006.225.07:31:09.85#ibcon#end of sib2, iclass 27, count 0 2006.225.07:31:09.85#ibcon#*after write, iclass 27, count 0 2006.225.07:31:09.85#ibcon#*before return 0, iclass 27, count 0 2006.225.07:31:09.85#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:31:09.85#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:31:09.85#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.07:31:09.85#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.07:31:09.85$vc4f8/vblo=2,640.99 2006.225.07:31:09.85#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.07:31:09.85#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.07:31:09.85#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:09.85#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:31:09.85#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:31:09.85#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:31:09.85#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:31:09.85#ibcon#first serial, iclass 29, count 0 2006.225.07:31:09.85#ibcon#enter sib2, iclass 29, count 0 2006.225.07:31:09.85#ibcon#flushed, iclass 29, count 0 2006.225.07:31:09.85#ibcon#about to write, iclass 29, count 0 2006.225.07:31:09.85#ibcon#wrote, iclass 29, count 0 2006.225.07:31:09.85#ibcon#about to read 3, iclass 29, count 0 2006.225.07:31:09.87#ibcon#read 3, iclass 29, count 0 2006.225.07:31:09.87#ibcon#about to read 4, iclass 29, count 0 2006.225.07:31:09.87#ibcon#read 4, iclass 29, count 0 2006.225.07:31:09.87#ibcon#about to read 5, iclass 29, count 0 2006.225.07:31:09.87#ibcon#read 5, iclass 29, count 0 2006.225.07:31:09.87#ibcon#about to read 6, iclass 29, count 0 2006.225.07:31:09.87#ibcon#read 6, iclass 29, count 0 2006.225.07:31:09.87#ibcon#end of sib2, iclass 29, count 0 2006.225.07:31:09.87#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:31:09.87#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:31:09.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:31:09.87#ibcon#*before write, iclass 29, count 0 2006.225.07:31:09.87#ibcon#enter sib2, iclass 29, count 0 2006.225.07:31:09.87#ibcon#flushed, iclass 29, count 0 2006.225.07:31:09.87#ibcon#about to write, iclass 29, count 0 2006.225.07:31:09.87#ibcon#wrote, iclass 29, count 0 2006.225.07:31:09.87#ibcon#about to read 3, iclass 29, count 0 2006.225.07:31:09.91#ibcon#read 3, iclass 29, count 0 2006.225.07:31:09.91#ibcon#about to read 4, iclass 29, count 0 2006.225.07:31:09.91#ibcon#read 4, iclass 29, count 0 2006.225.07:31:09.91#ibcon#about to read 5, iclass 29, count 0 2006.225.07:31:09.91#ibcon#read 5, iclass 29, count 0 2006.225.07:31:09.91#ibcon#about to read 6, iclass 29, count 0 2006.225.07:31:09.91#ibcon#read 6, iclass 29, count 0 2006.225.07:31:09.91#ibcon#end of sib2, iclass 29, count 0 2006.225.07:31:09.91#ibcon#*after write, iclass 29, count 0 2006.225.07:31:09.91#ibcon#*before return 0, iclass 29, count 0 2006.225.07:31:09.91#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:31:09.91#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:31:09.91#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:31:09.91#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:31:09.91$vc4f8/vb=2,4 2006.225.07:31:09.91#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.07:31:09.91#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.07:31:09.91#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:09.91#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:31:09.97#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:31:09.97#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:31:09.97#ibcon#enter wrdev, iclass 31, count 2 2006.225.07:31:09.97#ibcon#first serial, iclass 31, count 2 2006.225.07:31:09.97#ibcon#enter sib2, iclass 31, count 2 2006.225.07:31:09.97#ibcon#flushed, iclass 31, count 2 2006.225.07:31:09.97#ibcon#about to write, iclass 31, count 2 2006.225.07:31:09.97#ibcon#wrote, iclass 31, count 2 2006.225.07:31:09.97#ibcon#about to read 3, iclass 31, count 2 2006.225.07:31:09.99#ibcon#read 3, iclass 31, count 2 2006.225.07:31:09.99#ibcon#about to read 4, iclass 31, count 2 2006.225.07:31:09.99#ibcon#read 4, iclass 31, count 2 2006.225.07:31:09.99#ibcon#about to read 5, iclass 31, count 2 2006.225.07:31:09.99#ibcon#read 5, iclass 31, count 2 2006.225.07:31:09.99#ibcon#about to read 6, iclass 31, count 2 2006.225.07:31:09.99#ibcon#read 6, iclass 31, count 2 2006.225.07:31:09.99#ibcon#end of sib2, iclass 31, count 2 2006.225.07:31:09.99#ibcon#*mode == 0, iclass 31, count 2 2006.225.07:31:09.99#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.07:31:09.99#ibcon#[27=AT02-04\r\n] 2006.225.07:31:09.99#ibcon#*before write, iclass 31, count 2 2006.225.07:31:09.99#ibcon#enter sib2, iclass 31, count 2 2006.225.07:31:09.99#ibcon#flushed, iclass 31, count 2 2006.225.07:31:09.99#ibcon#about to write, iclass 31, count 2 2006.225.07:31:09.99#ibcon#wrote, iclass 31, count 2 2006.225.07:31:09.99#ibcon#about to read 3, iclass 31, count 2 2006.225.07:31:10.02#ibcon#read 3, iclass 31, count 2 2006.225.07:31:10.02#ibcon#about to read 4, iclass 31, count 2 2006.225.07:31:10.02#ibcon#read 4, iclass 31, count 2 2006.225.07:31:10.02#ibcon#about to read 5, iclass 31, count 2 2006.225.07:31:10.02#ibcon#read 5, iclass 31, count 2 2006.225.07:31:10.02#ibcon#about to read 6, iclass 31, count 2 2006.225.07:31:10.02#ibcon#read 6, iclass 31, count 2 2006.225.07:31:10.02#ibcon#end of sib2, iclass 31, count 2 2006.225.07:31:10.02#ibcon#*after write, iclass 31, count 2 2006.225.07:31:10.02#ibcon#*before return 0, iclass 31, count 2 2006.225.07:31:10.02#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:31:10.02#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:31:10.02#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.07:31:10.02#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:10.02#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:31:10.14#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:31:10.14#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:31:10.14#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:31:10.14#ibcon#first serial, iclass 31, count 0 2006.225.07:31:10.14#ibcon#enter sib2, iclass 31, count 0 2006.225.07:31:10.14#ibcon#flushed, iclass 31, count 0 2006.225.07:31:10.14#ibcon#about to write, iclass 31, count 0 2006.225.07:31:10.14#ibcon#wrote, iclass 31, count 0 2006.225.07:31:10.14#ibcon#about to read 3, iclass 31, count 0 2006.225.07:31:10.16#ibcon#read 3, iclass 31, count 0 2006.225.07:31:10.16#ibcon#about to read 4, iclass 31, count 0 2006.225.07:31:10.16#ibcon#read 4, iclass 31, count 0 2006.225.07:31:10.16#ibcon#about to read 5, iclass 31, count 0 2006.225.07:31:10.16#ibcon#read 5, iclass 31, count 0 2006.225.07:31:10.16#ibcon#about to read 6, iclass 31, count 0 2006.225.07:31:10.16#ibcon#read 6, iclass 31, count 0 2006.225.07:31:10.16#ibcon#end of sib2, iclass 31, count 0 2006.225.07:31:10.16#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:31:10.16#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:31:10.16#ibcon#[27=USB\r\n] 2006.225.07:31:10.16#ibcon#*before write, iclass 31, count 0 2006.225.07:31:10.16#ibcon#enter sib2, iclass 31, count 0 2006.225.07:31:10.16#ibcon#flushed, iclass 31, count 0 2006.225.07:31:10.16#ibcon#about to write, iclass 31, count 0 2006.225.07:31:10.16#ibcon#wrote, iclass 31, count 0 2006.225.07:31:10.16#ibcon#about to read 3, iclass 31, count 0 2006.225.07:31:10.19#ibcon#read 3, iclass 31, count 0 2006.225.07:31:10.19#ibcon#about to read 4, iclass 31, count 0 2006.225.07:31:10.19#ibcon#read 4, iclass 31, count 0 2006.225.07:31:10.19#ibcon#about to read 5, iclass 31, count 0 2006.225.07:31:10.19#ibcon#read 5, iclass 31, count 0 2006.225.07:31:10.19#ibcon#about to read 6, iclass 31, count 0 2006.225.07:31:10.19#ibcon#read 6, iclass 31, count 0 2006.225.07:31:10.19#ibcon#end of sib2, iclass 31, count 0 2006.225.07:31:10.19#ibcon#*after write, iclass 31, count 0 2006.225.07:31:10.19#ibcon#*before return 0, iclass 31, count 0 2006.225.07:31:10.19#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:31:10.19#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:31:10.19#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:31:10.19#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:31:10.19$vc4f8/vblo=3,656.99 2006.225.07:31:10.19#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.07:31:10.19#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.07:31:10.19#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:10.19#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:31:10.19#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:31:10.19#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:31:10.19#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:31:10.19#ibcon#first serial, iclass 33, count 0 2006.225.07:31:10.19#ibcon#enter sib2, iclass 33, count 0 2006.225.07:31:10.19#ibcon#flushed, iclass 33, count 0 2006.225.07:31:10.19#ibcon#about to write, iclass 33, count 0 2006.225.07:31:10.19#ibcon#wrote, iclass 33, count 0 2006.225.07:31:10.19#ibcon#about to read 3, iclass 33, count 0 2006.225.07:31:10.21#ibcon#read 3, iclass 33, count 0 2006.225.07:31:10.21#ibcon#about to read 4, iclass 33, count 0 2006.225.07:31:10.21#ibcon#read 4, iclass 33, count 0 2006.225.07:31:10.21#ibcon#about to read 5, iclass 33, count 0 2006.225.07:31:10.21#ibcon#read 5, iclass 33, count 0 2006.225.07:31:10.21#ibcon#about to read 6, iclass 33, count 0 2006.225.07:31:10.21#ibcon#read 6, iclass 33, count 0 2006.225.07:31:10.21#ibcon#end of sib2, iclass 33, count 0 2006.225.07:31:10.21#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:31:10.21#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:31:10.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:31:10.21#ibcon#*before write, iclass 33, count 0 2006.225.07:31:10.21#ibcon#enter sib2, iclass 33, count 0 2006.225.07:31:10.21#ibcon#flushed, iclass 33, count 0 2006.225.07:31:10.21#ibcon#about to write, iclass 33, count 0 2006.225.07:31:10.21#ibcon#wrote, iclass 33, count 0 2006.225.07:31:10.21#ibcon#about to read 3, iclass 33, count 0 2006.225.07:31:10.25#ibcon#read 3, iclass 33, count 0 2006.225.07:31:10.25#ibcon#about to read 4, iclass 33, count 0 2006.225.07:31:10.25#ibcon#read 4, iclass 33, count 0 2006.225.07:31:10.25#ibcon#about to read 5, iclass 33, count 0 2006.225.07:31:10.25#ibcon#read 5, iclass 33, count 0 2006.225.07:31:10.25#ibcon#about to read 6, iclass 33, count 0 2006.225.07:31:10.25#ibcon#read 6, iclass 33, count 0 2006.225.07:31:10.25#ibcon#end of sib2, iclass 33, count 0 2006.225.07:31:10.25#ibcon#*after write, iclass 33, count 0 2006.225.07:31:10.25#ibcon#*before return 0, iclass 33, count 0 2006.225.07:31:10.25#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:31:10.25#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:31:10.25#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:31:10.25#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:31:10.25$vc4f8/vb=3,4 2006.225.07:31:10.25#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.07:31:10.25#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.07:31:10.25#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:10.25#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:31:10.31#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:31:10.31#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:31:10.31#ibcon#enter wrdev, iclass 35, count 2 2006.225.07:31:10.31#ibcon#first serial, iclass 35, count 2 2006.225.07:31:10.31#ibcon#enter sib2, iclass 35, count 2 2006.225.07:31:10.31#ibcon#flushed, iclass 35, count 2 2006.225.07:31:10.31#ibcon#about to write, iclass 35, count 2 2006.225.07:31:10.31#ibcon#wrote, iclass 35, count 2 2006.225.07:31:10.31#ibcon#about to read 3, iclass 35, count 2 2006.225.07:31:10.33#ibcon#read 3, iclass 35, count 2 2006.225.07:31:10.33#ibcon#about to read 4, iclass 35, count 2 2006.225.07:31:10.33#ibcon#read 4, iclass 35, count 2 2006.225.07:31:10.33#ibcon#about to read 5, iclass 35, count 2 2006.225.07:31:10.33#ibcon#read 5, iclass 35, count 2 2006.225.07:31:10.33#ibcon#about to read 6, iclass 35, count 2 2006.225.07:31:10.33#ibcon#read 6, iclass 35, count 2 2006.225.07:31:10.33#ibcon#end of sib2, iclass 35, count 2 2006.225.07:31:10.33#ibcon#*mode == 0, iclass 35, count 2 2006.225.07:31:10.33#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.07:31:10.33#ibcon#[27=AT03-04\r\n] 2006.225.07:31:10.33#ibcon#*before write, iclass 35, count 2 2006.225.07:31:10.33#ibcon#enter sib2, iclass 35, count 2 2006.225.07:31:10.33#ibcon#flushed, iclass 35, count 2 2006.225.07:31:10.33#ibcon#about to write, iclass 35, count 2 2006.225.07:31:10.33#ibcon#wrote, iclass 35, count 2 2006.225.07:31:10.33#ibcon#about to read 3, iclass 35, count 2 2006.225.07:31:10.36#ibcon#read 3, iclass 35, count 2 2006.225.07:31:10.36#ibcon#about to read 4, iclass 35, count 2 2006.225.07:31:10.36#ibcon#read 4, iclass 35, count 2 2006.225.07:31:10.36#ibcon#about to read 5, iclass 35, count 2 2006.225.07:31:10.36#ibcon#read 5, iclass 35, count 2 2006.225.07:31:10.36#ibcon#about to read 6, iclass 35, count 2 2006.225.07:31:10.36#ibcon#read 6, iclass 35, count 2 2006.225.07:31:10.36#ibcon#end of sib2, iclass 35, count 2 2006.225.07:31:10.36#ibcon#*after write, iclass 35, count 2 2006.225.07:31:10.36#ibcon#*before return 0, iclass 35, count 2 2006.225.07:31:10.36#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:31:10.36#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:31:10.36#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.07:31:10.36#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:10.36#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:31:10.48#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:31:10.48#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:31:10.48#ibcon#enter wrdev, iclass 35, count 0 2006.225.07:31:10.48#ibcon#first serial, iclass 35, count 0 2006.225.07:31:10.48#ibcon#enter sib2, iclass 35, count 0 2006.225.07:31:10.48#ibcon#flushed, iclass 35, count 0 2006.225.07:31:10.48#ibcon#about to write, iclass 35, count 0 2006.225.07:31:10.48#ibcon#wrote, iclass 35, count 0 2006.225.07:31:10.48#ibcon#about to read 3, iclass 35, count 0 2006.225.07:31:10.50#ibcon#read 3, iclass 35, count 0 2006.225.07:31:10.50#ibcon#about to read 4, iclass 35, count 0 2006.225.07:31:10.50#ibcon#read 4, iclass 35, count 0 2006.225.07:31:10.50#ibcon#about to read 5, iclass 35, count 0 2006.225.07:31:10.50#ibcon#read 5, iclass 35, count 0 2006.225.07:31:10.50#ibcon#about to read 6, iclass 35, count 0 2006.225.07:31:10.50#ibcon#read 6, iclass 35, count 0 2006.225.07:31:10.50#ibcon#end of sib2, iclass 35, count 0 2006.225.07:31:10.50#ibcon#*mode == 0, iclass 35, count 0 2006.225.07:31:10.50#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.07:31:10.50#ibcon#[27=USB\r\n] 2006.225.07:31:10.50#ibcon#*before write, iclass 35, count 0 2006.225.07:31:10.50#ibcon#enter sib2, iclass 35, count 0 2006.225.07:31:10.50#ibcon#flushed, iclass 35, count 0 2006.225.07:31:10.50#ibcon#about to write, iclass 35, count 0 2006.225.07:31:10.50#ibcon#wrote, iclass 35, count 0 2006.225.07:31:10.50#ibcon#about to read 3, iclass 35, count 0 2006.225.07:31:10.53#ibcon#read 3, iclass 35, count 0 2006.225.07:31:10.53#ibcon#about to read 4, iclass 35, count 0 2006.225.07:31:10.53#ibcon#read 4, iclass 35, count 0 2006.225.07:31:10.53#ibcon#about to read 5, iclass 35, count 0 2006.225.07:31:10.53#ibcon#read 5, iclass 35, count 0 2006.225.07:31:10.53#ibcon#about to read 6, iclass 35, count 0 2006.225.07:31:10.53#ibcon#read 6, iclass 35, count 0 2006.225.07:31:10.53#ibcon#end of sib2, iclass 35, count 0 2006.225.07:31:10.53#ibcon#*after write, iclass 35, count 0 2006.225.07:31:10.53#ibcon#*before return 0, iclass 35, count 0 2006.225.07:31:10.53#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:31:10.53#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:31:10.53#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.07:31:10.53#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.07:31:10.53$vc4f8/vblo=4,712.99 2006.225.07:31:10.53#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.07:31:10.53#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.07:31:10.53#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:10.53#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:31:10.53#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:31:10.53#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:31:10.53#ibcon#enter wrdev, iclass 37, count 0 2006.225.07:31:10.53#ibcon#first serial, iclass 37, count 0 2006.225.07:31:10.53#ibcon#enter sib2, iclass 37, count 0 2006.225.07:31:10.53#ibcon#flushed, iclass 37, count 0 2006.225.07:31:10.53#ibcon#about to write, iclass 37, count 0 2006.225.07:31:10.53#ibcon#wrote, iclass 37, count 0 2006.225.07:31:10.53#ibcon#about to read 3, iclass 37, count 0 2006.225.07:31:10.56#ibcon#read 3, iclass 37, count 0 2006.225.07:31:10.56#ibcon#about to read 4, iclass 37, count 0 2006.225.07:31:10.56#ibcon#read 4, iclass 37, count 0 2006.225.07:31:10.56#ibcon#about to read 5, iclass 37, count 0 2006.225.07:31:10.56#ibcon#read 5, iclass 37, count 0 2006.225.07:31:10.56#ibcon#about to read 6, iclass 37, count 0 2006.225.07:31:10.56#ibcon#read 6, iclass 37, count 0 2006.225.07:31:10.56#ibcon#end of sib2, iclass 37, count 0 2006.225.07:31:10.56#ibcon#*mode == 0, iclass 37, count 0 2006.225.07:31:10.56#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.07:31:10.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:31:10.56#ibcon#*before write, iclass 37, count 0 2006.225.07:31:10.56#ibcon#enter sib2, iclass 37, count 0 2006.225.07:31:10.56#ibcon#flushed, iclass 37, count 0 2006.225.07:31:10.56#ibcon#about to write, iclass 37, count 0 2006.225.07:31:10.56#ibcon#wrote, iclass 37, count 0 2006.225.07:31:10.56#ibcon#about to read 3, iclass 37, count 0 2006.225.07:31:10.60#ibcon#read 3, iclass 37, count 0 2006.225.07:31:10.60#ibcon#about to read 4, iclass 37, count 0 2006.225.07:31:10.60#ibcon#read 4, iclass 37, count 0 2006.225.07:31:10.60#ibcon#about to read 5, iclass 37, count 0 2006.225.07:31:10.60#ibcon#read 5, iclass 37, count 0 2006.225.07:31:10.60#ibcon#about to read 6, iclass 37, count 0 2006.225.07:31:10.60#ibcon#read 6, iclass 37, count 0 2006.225.07:31:10.60#ibcon#end of sib2, iclass 37, count 0 2006.225.07:31:10.60#ibcon#*after write, iclass 37, count 0 2006.225.07:31:10.60#ibcon#*before return 0, iclass 37, count 0 2006.225.07:31:10.60#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:31:10.60#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:31:10.60#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.07:31:10.60#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.07:31:10.60$vc4f8/vb=4,4 2006.225.07:31:10.60#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.07:31:10.60#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.07:31:10.60#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:10.60#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:31:10.66#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:31:10.66#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:31:10.66#ibcon#enter wrdev, iclass 39, count 2 2006.225.07:31:10.66#ibcon#first serial, iclass 39, count 2 2006.225.07:31:10.66#ibcon#enter sib2, iclass 39, count 2 2006.225.07:31:10.66#ibcon#flushed, iclass 39, count 2 2006.225.07:31:10.66#ibcon#about to write, iclass 39, count 2 2006.225.07:31:10.66#ibcon#wrote, iclass 39, count 2 2006.225.07:31:10.66#ibcon#about to read 3, iclass 39, count 2 2006.225.07:31:10.67#ibcon#read 3, iclass 39, count 2 2006.225.07:31:10.67#ibcon#about to read 4, iclass 39, count 2 2006.225.07:31:10.67#ibcon#read 4, iclass 39, count 2 2006.225.07:31:10.67#ibcon#about to read 5, iclass 39, count 2 2006.225.07:31:10.67#ibcon#read 5, iclass 39, count 2 2006.225.07:31:10.67#ibcon#about to read 6, iclass 39, count 2 2006.225.07:31:10.67#ibcon#read 6, iclass 39, count 2 2006.225.07:31:10.67#ibcon#end of sib2, iclass 39, count 2 2006.225.07:31:10.67#ibcon#*mode == 0, iclass 39, count 2 2006.225.07:31:10.67#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.07:31:10.67#ibcon#[27=AT04-04\r\n] 2006.225.07:31:10.67#ibcon#*before write, iclass 39, count 2 2006.225.07:31:10.67#ibcon#enter sib2, iclass 39, count 2 2006.225.07:31:10.67#ibcon#flushed, iclass 39, count 2 2006.225.07:31:10.67#ibcon#about to write, iclass 39, count 2 2006.225.07:31:10.67#ibcon#wrote, iclass 39, count 2 2006.225.07:31:10.67#ibcon#about to read 3, iclass 39, count 2 2006.225.07:31:10.70#ibcon#read 3, iclass 39, count 2 2006.225.07:31:10.70#ibcon#about to read 4, iclass 39, count 2 2006.225.07:31:10.70#ibcon#read 4, iclass 39, count 2 2006.225.07:31:10.70#ibcon#about to read 5, iclass 39, count 2 2006.225.07:31:10.70#ibcon#read 5, iclass 39, count 2 2006.225.07:31:10.70#ibcon#about to read 6, iclass 39, count 2 2006.225.07:31:10.70#ibcon#read 6, iclass 39, count 2 2006.225.07:31:10.70#ibcon#end of sib2, iclass 39, count 2 2006.225.07:31:10.70#ibcon#*after write, iclass 39, count 2 2006.225.07:31:10.70#ibcon#*before return 0, iclass 39, count 2 2006.225.07:31:10.70#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:31:10.70#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:31:10.70#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.07:31:10.70#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:10.70#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:31:10.82#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:31:10.82#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:31:10.82#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:31:10.82#ibcon#first serial, iclass 39, count 0 2006.225.07:31:10.82#ibcon#enter sib2, iclass 39, count 0 2006.225.07:31:10.82#ibcon#flushed, iclass 39, count 0 2006.225.07:31:10.82#ibcon#about to write, iclass 39, count 0 2006.225.07:31:10.82#ibcon#wrote, iclass 39, count 0 2006.225.07:31:10.82#ibcon#about to read 3, iclass 39, count 0 2006.225.07:31:10.84#ibcon#read 3, iclass 39, count 0 2006.225.07:31:10.84#ibcon#about to read 4, iclass 39, count 0 2006.225.07:31:10.84#ibcon#read 4, iclass 39, count 0 2006.225.07:31:10.84#ibcon#about to read 5, iclass 39, count 0 2006.225.07:31:10.84#ibcon#read 5, iclass 39, count 0 2006.225.07:31:10.84#ibcon#about to read 6, iclass 39, count 0 2006.225.07:31:10.84#ibcon#read 6, iclass 39, count 0 2006.225.07:31:10.84#ibcon#end of sib2, iclass 39, count 0 2006.225.07:31:10.84#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:31:10.84#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:31:10.84#ibcon#[27=USB\r\n] 2006.225.07:31:10.84#ibcon#*before write, iclass 39, count 0 2006.225.07:31:10.84#ibcon#enter sib2, iclass 39, count 0 2006.225.07:31:10.84#ibcon#flushed, iclass 39, count 0 2006.225.07:31:10.84#ibcon#about to write, iclass 39, count 0 2006.225.07:31:10.84#ibcon#wrote, iclass 39, count 0 2006.225.07:31:10.84#ibcon#about to read 3, iclass 39, count 0 2006.225.07:31:10.87#ibcon#read 3, iclass 39, count 0 2006.225.07:31:10.87#ibcon#about to read 4, iclass 39, count 0 2006.225.07:31:10.87#ibcon#read 4, iclass 39, count 0 2006.225.07:31:10.87#ibcon#about to read 5, iclass 39, count 0 2006.225.07:31:10.87#ibcon#read 5, iclass 39, count 0 2006.225.07:31:10.87#ibcon#about to read 6, iclass 39, count 0 2006.225.07:31:10.87#ibcon#read 6, iclass 39, count 0 2006.225.07:31:10.87#ibcon#end of sib2, iclass 39, count 0 2006.225.07:31:10.87#ibcon#*after write, iclass 39, count 0 2006.225.07:31:10.87#ibcon#*before return 0, iclass 39, count 0 2006.225.07:31:10.87#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:31:10.87#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:31:10.87#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:31:10.87#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:31:10.87$vc4f8/vblo=5,744.99 2006.225.07:31:10.87#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.07:31:10.87#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.07:31:10.87#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:10.87#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:31:10.87#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:31:10.87#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:31:10.87#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:31:10.87#ibcon#first serial, iclass 3, count 0 2006.225.07:31:10.87#ibcon#enter sib2, iclass 3, count 0 2006.225.07:31:10.87#ibcon#flushed, iclass 3, count 0 2006.225.07:31:10.87#ibcon#about to write, iclass 3, count 0 2006.225.07:31:10.87#ibcon#wrote, iclass 3, count 0 2006.225.07:31:10.87#ibcon#about to read 3, iclass 3, count 0 2006.225.07:31:10.89#ibcon#read 3, iclass 3, count 0 2006.225.07:31:10.89#ibcon#about to read 4, iclass 3, count 0 2006.225.07:31:10.89#ibcon#read 4, iclass 3, count 0 2006.225.07:31:10.89#ibcon#about to read 5, iclass 3, count 0 2006.225.07:31:10.89#ibcon#read 5, iclass 3, count 0 2006.225.07:31:10.89#ibcon#about to read 6, iclass 3, count 0 2006.225.07:31:10.89#ibcon#read 6, iclass 3, count 0 2006.225.07:31:10.89#ibcon#end of sib2, iclass 3, count 0 2006.225.07:31:10.89#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:31:10.89#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:31:10.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:31:10.89#ibcon#*before write, iclass 3, count 0 2006.225.07:31:10.89#ibcon#enter sib2, iclass 3, count 0 2006.225.07:31:10.89#ibcon#flushed, iclass 3, count 0 2006.225.07:31:10.89#ibcon#about to write, iclass 3, count 0 2006.225.07:31:10.89#ibcon#wrote, iclass 3, count 0 2006.225.07:31:10.89#ibcon#about to read 3, iclass 3, count 0 2006.225.07:31:10.93#ibcon#read 3, iclass 3, count 0 2006.225.07:31:10.93#ibcon#about to read 4, iclass 3, count 0 2006.225.07:31:10.93#ibcon#read 4, iclass 3, count 0 2006.225.07:31:10.93#ibcon#about to read 5, iclass 3, count 0 2006.225.07:31:10.93#ibcon#read 5, iclass 3, count 0 2006.225.07:31:10.93#ibcon#about to read 6, iclass 3, count 0 2006.225.07:31:10.93#ibcon#read 6, iclass 3, count 0 2006.225.07:31:10.93#ibcon#end of sib2, iclass 3, count 0 2006.225.07:31:10.93#ibcon#*after write, iclass 3, count 0 2006.225.07:31:10.93#ibcon#*before return 0, iclass 3, count 0 2006.225.07:31:10.93#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:31:10.93#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:31:10.93#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:31:10.93#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:31:10.93$vc4f8/vb=5,4 2006.225.07:31:10.93#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.07:31:10.93#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.07:31:10.93#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:10.93#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:31:10.99#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:31:10.99#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:31:10.99#ibcon#enter wrdev, iclass 5, count 2 2006.225.07:31:10.99#ibcon#first serial, iclass 5, count 2 2006.225.07:31:10.99#ibcon#enter sib2, iclass 5, count 2 2006.225.07:31:10.99#ibcon#flushed, iclass 5, count 2 2006.225.07:31:10.99#ibcon#about to write, iclass 5, count 2 2006.225.07:31:10.99#ibcon#wrote, iclass 5, count 2 2006.225.07:31:10.99#ibcon#about to read 3, iclass 5, count 2 2006.225.07:31:11.01#ibcon#read 3, iclass 5, count 2 2006.225.07:31:11.01#ibcon#about to read 4, iclass 5, count 2 2006.225.07:31:11.01#ibcon#read 4, iclass 5, count 2 2006.225.07:31:11.01#ibcon#about to read 5, iclass 5, count 2 2006.225.07:31:11.01#ibcon#read 5, iclass 5, count 2 2006.225.07:31:11.01#ibcon#about to read 6, iclass 5, count 2 2006.225.07:31:11.01#ibcon#read 6, iclass 5, count 2 2006.225.07:31:11.01#ibcon#end of sib2, iclass 5, count 2 2006.225.07:31:11.01#ibcon#*mode == 0, iclass 5, count 2 2006.225.07:31:11.01#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.07:31:11.01#ibcon#[27=AT05-04\r\n] 2006.225.07:31:11.01#ibcon#*before write, iclass 5, count 2 2006.225.07:31:11.01#ibcon#enter sib2, iclass 5, count 2 2006.225.07:31:11.01#ibcon#flushed, iclass 5, count 2 2006.225.07:31:11.01#ibcon#about to write, iclass 5, count 2 2006.225.07:31:11.01#ibcon#wrote, iclass 5, count 2 2006.225.07:31:11.01#ibcon#about to read 3, iclass 5, count 2 2006.225.07:31:11.04#ibcon#read 3, iclass 5, count 2 2006.225.07:31:11.04#ibcon#about to read 4, iclass 5, count 2 2006.225.07:31:11.04#ibcon#read 4, iclass 5, count 2 2006.225.07:31:11.04#ibcon#about to read 5, iclass 5, count 2 2006.225.07:31:11.04#ibcon#read 5, iclass 5, count 2 2006.225.07:31:11.04#ibcon#about to read 6, iclass 5, count 2 2006.225.07:31:11.04#ibcon#read 6, iclass 5, count 2 2006.225.07:31:11.04#ibcon#end of sib2, iclass 5, count 2 2006.225.07:31:11.04#ibcon#*after write, iclass 5, count 2 2006.225.07:31:11.04#ibcon#*before return 0, iclass 5, count 2 2006.225.07:31:11.04#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:31:11.04#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:31:11.04#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.07:31:11.04#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:11.04#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:31:11.16#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:31:11.16#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:31:11.16#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:31:11.16#ibcon#first serial, iclass 5, count 0 2006.225.07:31:11.16#ibcon#enter sib2, iclass 5, count 0 2006.225.07:31:11.16#ibcon#flushed, iclass 5, count 0 2006.225.07:31:11.16#ibcon#about to write, iclass 5, count 0 2006.225.07:31:11.16#ibcon#wrote, iclass 5, count 0 2006.225.07:31:11.16#ibcon#about to read 3, iclass 5, count 0 2006.225.07:31:11.18#ibcon#read 3, iclass 5, count 0 2006.225.07:31:11.18#ibcon#about to read 4, iclass 5, count 0 2006.225.07:31:11.18#ibcon#read 4, iclass 5, count 0 2006.225.07:31:11.18#ibcon#about to read 5, iclass 5, count 0 2006.225.07:31:11.18#ibcon#read 5, iclass 5, count 0 2006.225.07:31:11.18#ibcon#about to read 6, iclass 5, count 0 2006.225.07:31:11.18#ibcon#read 6, iclass 5, count 0 2006.225.07:31:11.18#ibcon#end of sib2, iclass 5, count 0 2006.225.07:31:11.18#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:31:11.18#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:31:11.18#ibcon#[27=USB\r\n] 2006.225.07:31:11.18#ibcon#*before write, iclass 5, count 0 2006.225.07:31:11.18#ibcon#enter sib2, iclass 5, count 0 2006.225.07:31:11.18#ibcon#flushed, iclass 5, count 0 2006.225.07:31:11.18#ibcon#about to write, iclass 5, count 0 2006.225.07:31:11.18#ibcon#wrote, iclass 5, count 0 2006.225.07:31:11.18#ibcon#about to read 3, iclass 5, count 0 2006.225.07:31:11.21#ibcon#read 3, iclass 5, count 0 2006.225.07:31:11.21#ibcon#about to read 4, iclass 5, count 0 2006.225.07:31:11.21#ibcon#read 4, iclass 5, count 0 2006.225.07:31:11.21#ibcon#about to read 5, iclass 5, count 0 2006.225.07:31:11.21#ibcon#read 5, iclass 5, count 0 2006.225.07:31:11.21#ibcon#about to read 6, iclass 5, count 0 2006.225.07:31:11.21#ibcon#read 6, iclass 5, count 0 2006.225.07:31:11.21#ibcon#end of sib2, iclass 5, count 0 2006.225.07:31:11.21#ibcon#*after write, iclass 5, count 0 2006.225.07:31:11.21#ibcon#*before return 0, iclass 5, count 0 2006.225.07:31:11.21#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:31:11.21#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:31:11.21#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:31:11.21#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:31:11.21$vc4f8/vblo=6,752.99 2006.225.07:31:11.21#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.225.07:31:11.21#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.225.07:31:11.21#ibcon#ireg 17 cls_cnt 0 2006.225.07:31:11.21#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:31:11.21#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:31:11.21#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:31:11.21#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:31:11.21#ibcon#first serial, iclass 7, count 0 2006.225.07:31:11.21#ibcon#enter sib2, iclass 7, count 0 2006.225.07:31:11.21#ibcon#flushed, iclass 7, count 0 2006.225.07:31:11.21#ibcon#about to write, iclass 7, count 0 2006.225.07:31:11.21#ibcon#wrote, iclass 7, count 0 2006.225.07:31:11.21#ibcon#about to read 3, iclass 7, count 0 2006.225.07:31:11.23#ibcon#read 3, iclass 7, count 0 2006.225.07:31:11.23#ibcon#about to read 4, iclass 7, count 0 2006.225.07:31:11.23#ibcon#read 4, iclass 7, count 0 2006.225.07:31:11.23#ibcon#about to read 5, iclass 7, count 0 2006.225.07:31:11.23#ibcon#read 5, iclass 7, count 0 2006.225.07:31:11.23#ibcon#about to read 6, iclass 7, count 0 2006.225.07:31:11.23#ibcon#read 6, iclass 7, count 0 2006.225.07:31:11.23#ibcon#end of sib2, iclass 7, count 0 2006.225.07:31:11.23#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:31:11.23#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:31:11.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:31:11.23#ibcon#*before write, iclass 7, count 0 2006.225.07:31:11.23#ibcon#enter sib2, iclass 7, count 0 2006.225.07:31:11.23#ibcon#flushed, iclass 7, count 0 2006.225.07:31:11.23#ibcon#about to write, iclass 7, count 0 2006.225.07:31:11.23#ibcon#wrote, iclass 7, count 0 2006.225.07:31:11.23#ibcon#about to read 3, iclass 7, count 0 2006.225.07:31:11.27#ibcon#read 3, iclass 7, count 0 2006.225.07:31:11.27#ibcon#about to read 4, iclass 7, count 0 2006.225.07:31:11.27#ibcon#read 4, iclass 7, count 0 2006.225.07:31:11.27#ibcon#about to read 5, iclass 7, count 0 2006.225.07:31:11.27#ibcon#read 5, iclass 7, count 0 2006.225.07:31:11.27#ibcon#about to read 6, iclass 7, count 0 2006.225.07:31:11.27#ibcon#read 6, iclass 7, count 0 2006.225.07:31:11.27#ibcon#end of sib2, iclass 7, count 0 2006.225.07:31:11.27#ibcon#*after write, iclass 7, count 0 2006.225.07:31:11.27#ibcon#*before return 0, iclass 7, count 0 2006.225.07:31:11.27#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:31:11.27#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:31:11.27#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:31:11.27#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:31:11.27$vc4f8/vb=6,4 2006.225.07:31:11.27#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.225.07:31:11.27#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.225.07:31:11.27#ibcon#ireg 11 cls_cnt 2 2006.225.07:31:11.27#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:31:11.33#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:31:11.33#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:31:11.33#ibcon#enter wrdev, iclass 11, count 2 2006.225.07:31:11.33#ibcon#first serial, iclass 11, count 2 2006.225.07:31:11.33#ibcon#enter sib2, iclass 11, count 2 2006.225.07:31:11.33#ibcon#flushed, iclass 11, count 2 2006.225.07:31:11.33#ibcon#about to write, iclass 11, count 2 2006.225.07:31:11.33#ibcon#wrote, iclass 11, count 2 2006.225.07:31:11.33#ibcon#about to read 3, iclass 11, count 2 2006.225.07:31:11.35#ibcon#read 3, iclass 11, count 2 2006.225.07:31:11.35#ibcon#about to read 4, iclass 11, count 2 2006.225.07:31:11.35#ibcon#read 4, iclass 11, count 2 2006.225.07:31:11.35#ibcon#about to read 5, iclass 11, count 2 2006.225.07:31:11.35#ibcon#read 5, iclass 11, count 2 2006.225.07:31:11.35#ibcon#about to read 6, iclass 11, count 2 2006.225.07:31:11.35#ibcon#read 6, iclass 11, count 2 2006.225.07:31:11.35#ibcon#end of sib2, iclass 11, count 2 2006.225.07:31:11.35#ibcon#*mode == 0, iclass 11, count 2 2006.225.07:31:11.35#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.225.07:31:11.35#ibcon#[27=AT06-04\r\n] 2006.225.07:31:11.35#ibcon#*before write, iclass 11, count 2 2006.225.07:31:11.35#ibcon#enter sib2, iclass 11, count 2 2006.225.07:31:11.35#ibcon#flushed, iclass 11, count 2 2006.225.07:31:11.35#ibcon#about to write, iclass 11, count 2 2006.225.07:31:11.35#ibcon#wrote, iclass 11, count 2 2006.225.07:31:11.35#ibcon#about to read 3, iclass 11, count 2 2006.225.07:31:11.39#ibcon#read 3, iclass 11, count 2 2006.225.07:31:11.39#ibcon#about to read 4, iclass 11, count 2 2006.225.07:31:11.39#ibcon#read 4, iclass 11, count 2 2006.225.07:31:11.39#ibcon#about to read 5, iclass 11, count 2 2006.225.07:31:11.39#ibcon#read 5, iclass 11, count 2 2006.225.07:31:11.39#ibcon#about to read 6, iclass 11, count 2 2006.225.07:31:11.39#ibcon#read 6, iclass 11, count 2 2006.225.07:31:11.39#ibcon#end of sib2, iclass 11, count 2 2006.225.07:31:11.39#ibcon#*after write, iclass 11, count 2 2006.225.07:31:11.39#ibcon#*before return 0, iclass 11, count 2 2006.225.07:31:11.39#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:31:11.39#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:31:11.39#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.225.07:31:11.39#ibcon#ireg 7 cls_cnt 0 2006.225.07:31:11.39#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:31:11.50#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:31:11.50#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:31:11.50#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:31:11.50#ibcon#first serial, iclass 11, count 0 2006.225.07:31:11.50#ibcon#enter sib2, iclass 11, count 0 2006.225.07:31:11.50#ibcon#flushed, iclass 11, count 0 2006.225.07:31:11.50#ibcon#about to write, iclass 11, count 0 2006.225.07:31:11.50#ibcon#wrote, iclass 11, count 0 2006.225.07:31:11.50#ibcon#about to read 3, iclass 11, count 0 2006.225.07:31:11.52#ibcon#read 3, iclass 11, count 0 2006.225.07:31:11.52#ibcon#about to read 4, iclass 11, count 0 2006.225.07:31:11.52#ibcon#read 4, iclass 11, count 0 2006.225.07:31:11.52#ibcon#about to read 5, iclass 11, count 0 2006.225.07:31:11.52#ibcon#read 5, iclass 11, count 0 2006.225.07:31:11.52#ibcon#about to read 6, iclass 11, count 0 2006.225.07:31:11.52#ibcon#read 6, iclass 11, count 0 2006.225.07:31:11.52#ibcon#end of sib2, iclass 11, count 0 2006.225.07:31:11.52#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:31:11.52#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:31:11.52#ibcon#[27=USB\r\n] 2006.225.07:31:11.52#ibcon#*before write, iclass 11, count 0 2006.225.07:31:11.52#ibcon#enter sib2, iclass 11, count 0 2006.225.07:31:11.52#ibcon#flushed, iclass 11, count 0 2006.225.07:31:11.52#ibcon#about to write, iclass 11, count 0 2006.225.07:31:11.52#ibcon#wrote, iclass 11, count 0 2006.225.07:31:11.52#ibcon#about to read 3, iclass 11, count 0 2006.225.07:31:11.55#ibcon#read 3, iclass 11, count 0 2006.225.07:31:11.55#ibcon#about to read 4, iclass 11, count 0 2006.225.07:31:11.55#ibcon#read 4, iclass 11, count 0 2006.225.07:31:11.55#ibcon#about to read 5, iclass 11, count 0 2006.225.07:31:11.55#ibcon#read 5, iclass 11, count 0 2006.225.07:31:11.55#ibcon#about to read 6, iclass 11, count 0 2006.225.07:31:11.55#ibcon#read 6, iclass 11, count 0 2006.225.07:31:11.55#ibcon#end of sib2, iclass 11, count 0 2006.225.07:31:11.55#ibcon#*after write, iclass 11, count 0 2006.225.07:31:11.55#ibcon#*before return 0, iclass 11, count 0 2006.225.07:31:11.55#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:31:11.55#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:31:11.55#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:31:11.55#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:31:11.55$vc4f8/vabw=wide 2006.225.07:31:11.55#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.07:31:11.55#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.07:31:11.55#ibcon#ireg 8 cls_cnt 0 2006.225.07:31:11.55#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:31:11.55#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:31:11.55#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:31:11.55#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:31:11.55#ibcon#first serial, iclass 13, count 0 2006.225.07:31:11.55#ibcon#enter sib2, iclass 13, count 0 2006.225.07:31:11.55#ibcon#flushed, iclass 13, count 0 2006.225.07:31:11.55#ibcon#about to write, iclass 13, count 0 2006.225.07:31:11.55#ibcon#wrote, iclass 13, count 0 2006.225.07:31:11.55#ibcon#about to read 3, iclass 13, count 0 2006.225.07:31:11.57#ibcon#read 3, iclass 13, count 0 2006.225.07:31:11.57#ibcon#about to read 4, iclass 13, count 0 2006.225.07:31:11.57#ibcon#read 4, iclass 13, count 0 2006.225.07:31:11.57#ibcon#about to read 5, iclass 13, count 0 2006.225.07:31:11.57#ibcon#read 5, iclass 13, count 0 2006.225.07:31:11.57#ibcon#about to read 6, iclass 13, count 0 2006.225.07:31:11.57#ibcon#read 6, iclass 13, count 0 2006.225.07:31:11.57#ibcon#end of sib2, iclass 13, count 0 2006.225.07:31:11.57#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:31:11.57#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:31:11.57#ibcon#[25=BW32\r\n] 2006.225.07:31:11.57#ibcon#*before write, iclass 13, count 0 2006.225.07:31:11.57#ibcon#enter sib2, iclass 13, count 0 2006.225.07:31:11.57#ibcon#flushed, iclass 13, count 0 2006.225.07:31:11.57#ibcon#about to write, iclass 13, count 0 2006.225.07:31:11.57#ibcon#wrote, iclass 13, count 0 2006.225.07:31:11.57#ibcon#about to read 3, iclass 13, count 0 2006.225.07:31:11.60#ibcon#read 3, iclass 13, count 0 2006.225.07:31:11.60#ibcon#about to read 4, iclass 13, count 0 2006.225.07:31:11.60#ibcon#read 4, iclass 13, count 0 2006.225.07:31:11.60#ibcon#about to read 5, iclass 13, count 0 2006.225.07:31:11.60#ibcon#read 5, iclass 13, count 0 2006.225.07:31:11.60#ibcon#about to read 6, iclass 13, count 0 2006.225.07:31:11.60#ibcon#read 6, iclass 13, count 0 2006.225.07:31:11.60#ibcon#end of sib2, iclass 13, count 0 2006.225.07:31:11.60#ibcon#*after write, iclass 13, count 0 2006.225.07:31:11.60#ibcon#*before return 0, iclass 13, count 0 2006.225.07:31:11.60#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:31:11.60#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:31:11.60#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:31:11.60#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:31:11.60$vc4f8/vbbw=wide 2006.225.07:31:11.60#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.07:31:11.60#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.07:31:11.60#ibcon#ireg 8 cls_cnt 0 2006.225.07:31:11.60#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:31:11.67#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:31:11.67#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:31:11.67#ibcon#enter wrdev, iclass 15, count 0 2006.225.07:31:11.67#ibcon#first serial, iclass 15, count 0 2006.225.07:31:11.67#ibcon#enter sib2, iclass 15, count 0 2006.225.07:31:11.67#ibcon#flushed, iclass 15, count 0 2006.225.07:31:11.67#ibcon#about to write, iclass 15, count 0 2006.225.07:31:11.67#ibcon#wrote, iclass 15, count 0 2006.225.07:31:11.67#ibcon#about to read 3, iclass 15, count 0 2006.225.07:31:11.69#ibcon#read 3, iclass 15, count 0 2006.225.07:31:11.69#ibcon#about to read 4, iclass 15, count 0 2006.225.07:31:11.69#ibcon#read 4, iclass 15, count 0 2006.225.07:31:11.69#ibcon#about to read 5, iclass 15, count 0 2006.225.07:31:11.69#ibcon#read 5, iclass 15, count 0 2006.225.07:31:11.69#ibcon#about to read 6, iclass 15, count 0 2006.225.07:31:11.69#ibcon#read 6, iclass 15, count 0 2006.225.07:31:11.69#ibcon#end of sib2, iclass 15, count 0 2006.225.07:31:11.69#ibcon#*mode == 0, iclass 15, count 0 2006.225.07:31:11.69#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.07:31:11.69#ibcon#[27=BW32\r\n] 2006.225.07:31:11.69#ibcon#*before write, iclass 15, count 0 2006.225.07:31:11.69#ibcon#enter sib2, iclass 15, count 0 2006.225.07:31:11.69#ibcon#flushed, iclass 15, count 0 2006.225.07:31:11.69#ibcon#about to write, iclass 15, count 0 2006.225.07:31:11.69#ibcon#wrote, iclass 15, count 0 2006.225.07:31:11.69#ibcon#about to read 3, iclass 15, count 0 2006.225.07:31:11.72#ibcon#read 3, iclass 15, count 0 2006.225.07:31:11.72#ibcon#about to read 4, iclass 15, count 0 2006.225.07:31:11.72#ibcon#read 4, iclass 15, count 0 2006.225.07:31:11.72#ibcon#about to read 5, iclass 15, count 0 2006.225.07:31:11.72#ibcon#read 5, iclass 15, count 0 2006.225.07:31:11.72#ibcon#about to read 6, iclass 15, count 0 2006.225.07:31:11.72#ibcon#read 6, iclass 15, count 0 2006.225.07:31:11.72#ibcon#end of sib2, iclass 15, count 0 2006.225.07:31:11.72#ibcon#*after write, iclass 15, count 0 2006.225.07:31:11.72#ibcon#*before return 0, iclass 15, count 0 2006.225.07:31:11.72#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:31:11.72#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:31:11.72#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.07:31:11.72#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.07:31:11.72$4f8m12a/ifd4f 2006.225.07:31:11.72$ifd4f/lo= 2006.225.07:31:11.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:31:11.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:31:11.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:31:11.72$ifd4f/patch= 2006.225.07:31:11.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:31:11.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:31:11.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:31:11.73$4f8m12a/"form=m,16.000,1:2 2006.225.07:31:11.73$4f8m12a/"tpicd 2006.225.07:31:11.73$4f8m12a/echo=off 2006.225.07:31:11.73$4f8m12a/xlog=off 2006.225.07:31:11.73:!2006.225.07:33:20 2006.225.07:31:44.14#trakl#Source acquired 2006.225.07:31:45.14#flagr#flagr/antenna,acquired 2006.225.07:33:20.01:preob 2006.225.07:33:21.14/onsource/TRACKING 2006.225.07:33:21.14:!2006.225.07:33:30 2006.225.07:33:30.00:data_valid=on 2006.225.07:33:30.00:midob 2006.225.07:33:30.14/onsource/TRACKING 2006.225.07:33:30.14/wx/27.97,1003.2,72 2006.225.07:33:30.25/cable/+6.4048E-03 2006.225.07:33:31.34/va/01,08,usb,yes,36,38 2006.225.07:33:31.34/va/02,07,usb,yes,36,38 2006.225.07:33:31.34/va/03,06,usb,yes,39,39 2006.225.07:33:31.34/va/04,07,usb,yes,38,41 2006.225.07:33:31.34/va/05,07,usb,yes,41,44 2006.225.07:33:31.34/va/06,06,usb,yes,42,41 2006.225.07:33:31.34/va/07,06,usb,yes,41,41 2006.225.07:33:31.34/va/08,07,usb,yes,39,38 2006.225.07:33:31.57/valo/01,532.99,yes,locked 2006.225.07:33:31.57/valo/02,572.99,yes,locked 2006.225.07:33:31.57/valo/03,672.99,yes,locked 2006.225.07:33:31.57/valo/04,832.99,yes,locked 2006.225.07:33:31.57/valo/05,652.99,yes,locked 2006.225.07:33:31.57/valo/06,772.99,yes,locked 2006.225.07:33:31.57/valo/07,832.99,yes,locked 2006.225.07:33:31.57/valo/08,852.99,yes,locked 2006.225.07:33:32.66/vb/01,04,usb,yes,35,33 2006.225.07:33:32.66/vb/02,04,usb,yes,36,38 2006.225.07:33:32.66/vb/03,04,usb,yes,32,37 2006.225.07:33:32.66/vb/04,04,usb,yes,34,34 2006.225.07:33:32.66/vb/05,04,usb,yes,32,36 2006.225.07:33:32.66/vb/06,04,usb,yes,33,36 2006.225.07:33:32.66/vb/07,04,usb,yes,35,35 2006.225.07:33:32.66/vb/08,04,usb,yes,32,36 2006.225.07:33:32.90/vblo/01,632.99,yes,locked 2006.225.07:33:32.90/vblo/02,640.99,yes,locked 2006.225.07:33:32.90/vblo/03,656.99,yes,locked 2006.225.07:33:32.90/vblo/04,712.99,yes,locked 2006.225.07:33:32.90/vblo/05,744.99,yes,locked 2006.225.07:33:32.90/vblo/06,752.99,yes,locked 2006.225.07:33:32.90/vblo/07,734.99,yes,locked 2006.225.07:33:32.90/vblo/08,744.99,yes,locked 2006.225.07:33:33.05/vabw/8 2006.225.07:33:33.20/vbbw/8 2006.225.07:33:33.33/xfe/off,on,15.2 2006.225.07:33:33.70/ifatt/23,28,28,28 2006.225.07:33:34.07/fmout-gps/S +4.42E-07 2006.225.07:33:34.11:!2006.225.07:34:30 2006.225.07:34:30.00:data_valid=off 2006.225.07:34:30.01:postob 2006.225.07:34:30.06/cable/+6.4051E-03 2006.225.07:34:30.07/wx/27.94,1003.2,73 2006.225.07:34:31.07/fmout-gps/S +4.44E-07 2006.225.07:34:31.08:scan_name=225-0735,k06225,60 2006.225.07:34:31.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.225.07:34:32.12#flagr#flagr/antenna,new-source 2006.225.07:34:32.13:checkk5 2006.225.07:34:32.50/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:34:32.87/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:34:33.24/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:34:33.62/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:34:33.99/chk_obsdata//k5ts1/T2250733??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:34:34.35/chk_obsdata//k5ts2/T2250733??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:34:34.72/chk_obsdata//k5ts3/T2250733??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:34:35.08/chk_obsdata//k5ts4/T2250733??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:34:35.77/k5log//k5ts1_log_newline 2006.225.07:34:36.46/k5log//k5ts2_log_newline 2006.225.07:34:37.16/k5log//k5ts3_log_newline 2006.225.07:34:37.84/k5log//k5ts4_log_newline 2006.225.07:34:37.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:34:37.86:4f8m12a=1 2006.225.07:34:37.86$4f8m12a/echo=on 2006.225.07:34:37.86$4f8m12a/pcalon 2006.225.07:34:37.86$pcalon/"no phase cal control is implemented here 2006.225.07:34:37.86$4f8m12a/"tpicd=stop 2006.225.07:34:37.86$4f8m12a/vc4f8 2006.225.07:34:37.86$vc4f8/valo=1,532.99 2006.225.07:34:37.86#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.07:34:37.86#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.07:34:37.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:37.86#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:34:37.86#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:34:37.86#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:34:37.86#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:34:37.86#ibcon#first serial, iclass 30, count 0 2006.225.07:34:37.86#ibcon#enter sib2, iclass 30, count 0 2006.225.07:34:37.86#ibcon#flushed, iclass 30, count 0 2006.225.07:34:37.86#ibcon#about to write, iclass 30, count 0 2006.225.07:34:37.86#ibcon#wrote, iclass 30, count 0 2006.225.07:34:37.86#ibcon#about to read 3, iclass 30, count 0 2006.225.07:34:37.91#ibcon#read 3, iclass 30, count 0 2006.225.07:34:37.91#ibcon#about to read 4, iclass 30, count 0 2006.225.07:34:37.91#ibcon#read 4, iclass 30, count 0 2006.225.07:34:37.91#ibcon#about to read 5, iclass 30, count 0 2006.225.07:34:37.91#ibcon#read 5, iclass 30, count 0 2006.225.07:34:37.91#ibcon#about to read 6, iclass 30, count 0 2006.225.07:34:37.91#ibcon#read 6, iclass 30, count 0 2006.225.07:34:37.91#ibcon#end of sib2, iclass 30, count 0 2006.225.07:34:37.91#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:34:37.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:34:37.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:34:37.91#ibcon#*before write, iclass 30, count 0 2006.225.07:34:37.91#ibcon#enter sib2, iclass 30, count 0 2006.225.07:34:37.91#ibcon#flushed, iclass 30, count 0 2006.225.07:34:37.91#ibcon#about to write, iclass 30, count 0 2006.225.07:34:37.91#ibcon#wrote, iclass 30, count 0 2006.225.07:34:37.91#ibcon#about to read 3, iclass 30, count 0 2006.225.07:34:37.95#ibcon#read 3, iclass 30, count 0 2006.225.07:34:37.95#ibcon#about to read 4, iclass 30, count 0 2006.225.07:34:37.95#ibcon#read 4, iclass 30, count 0 2006.225.07:34:37.95#ibcon#about to read 5, iclass 30, count 0 2006.225.07:34:37.95#ibcon#read 5, iclass 30, count 0 2006.225.07:34:37.95#ibcon#about to read 6, iclass 30, count 0 2006.225.07:34:37.95#ibcon#read 6, iclass 30, count 0 2006.225.07:34:37.95#ibcon#end of sib2, iclass 30, count 0 2006.225.07:34:37.95#ibcon#*after write, iclass 30, count 0 2006.225.07:34:37.95#ibcon#*before return 0, iclass 30, count 0 2006.225.07:34:37.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:34:37.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:34:37.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:34:37.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:34:37.95$vc4f8/va=1,8 2006.225.07:34:37.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.225.07:34:37.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.225.07:34:37.95#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:37.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:34:37.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:34:37.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:34:37.95#ibcon#enter wrdev, iclass 32, count 2 2006.225.07:34:37.95#ibcon#first serial, iclass 32, count 2 2006.225.07:34:37.95#ibcon#enter sib2, iclass 32, count 2 2006.225.07:34:37.95#ibcon#flushed, iclass 32, count 2 2006.225.07:34:37.95#ibcon#about to write, iclass 32, count 2 2006.225.07:34:37.95#ibcon#wrote, iclass 32, count 2 2006.225.07:34:37.95#ibcon#about to read 3, iclass 32, count 2 2006.225.07:34:37.97#ibcon#read 3, iclass 32, count 2 2006.225.07:34:37.97#ibcon#about to read 4, iclass 32, count 2 2006.225.07:34:37.97#ibcon#read 4, iclass 32, count 2 2006.225.07:34:37.97#ibcon#about to read 5, iclass 32, count 2 2006.225.07:34:37.97#ibcon#read 5, iclass 32, count 2 2006.225.07:34:37.97#ibcon#about to read 6, iclass 32, count 2 2006.225.07:34:37.97#ibcon#read 6, iclass 32, count 2 2006.225.07:34:37.97#ibcon#end of sib2, iclass 32, count 2 2006.225.07:34:37.97#ibcon#*mode == 0, iclass 32, count 2 2006.225.07:34:37.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.225.07:34:37.97#ibcon#[25=AT01-08\r\n] 2006.225.07:34:37.97#ibcon#*before write, iclass 32, count 2 2006.225.07:34:37.97#ibcon#enter sib2, iclass 32, count 2 2006.225.07:34:37.97#ibcon#flushed, iclass 32, count 2 2006.225.07:34:37.97#ibcon#about to write, iclass 32, count 2 2006.225.07:34:37.97#ibcon#wrote, iclass 32, count 2 2006.225.07:34:37.97#ibcon#about to read 3, iclass 32, count 2 2006.225.07:34:38.00#ibcon#read 3, iclass 32, count 2 2006.225.07:34:38.00#ibcon#about to read 4, iclass 32, count 2 2006.225.07:34:38.00#ibcon#read 4, iclass 32, count 2 2006.225.07:34:38.00#ibcon#about to read 5, iclass 32, count 2 2006.225.07:34:38.00#ibcon#read 5, iclass 32, count 2 2006.225.07:34:38.00#ibcon#about to read 6, iclass 32, count 2 2006.225.07:34:38.00#ibcon#read 6, iclass 32, count 2 2006.225.07:34:38.00#ibcon#end of sib2, iclass 32, count 2 2006.225.07:34:38.00#ibcon#*after write, iclass 32, count 2 2006.225.07:34:38.00#ibcon#*before return 0, iclass 32, count 2 2006.225.07:34:38.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:34:38.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:34:38.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.225.07:34:38.00#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:38.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:34:38.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:34:38.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:34:38.12#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:34:38.12#ibcon#first serial, iclass 32, count 0 2006.225.07:34:38.12#ibcon#enter sib2, iclass 32, count 0 2006.225.07:34:38.12#ibcon#flushed, iclass 32, count 0 2006.225.07:34:38.12#ibcon#about to write, iclass 32, count 0 2006.225.07:34:38.12#ibcon#wrote, iclass 32, count 0 2006.225.07:34:38.12#ibcon#about to read 3, iclass 32, count 0 2006.225.07:34:38.14#ibcon#read 3, iclass 32, count 0 2006.225.07:34:38.14#ibcon#about to read 4, iclass 32, count 0 2006.225.07:34:38.14#ibcon#read 4, iclass 32, count 0 2006.225.07:34:38.14#ibcon#about to read 5, iclass 32, count 0 2006.225.07:34:38.14#ibcon#read 5, iclass 32, count 0 2006.225.07:34:38.14#ibcon#about to read 6, iclass 32, count 0 2006.225.07:34:38.14#ibcon#read 6, iclass 32, count 0 2006.225.07:34:38.14#ibcon#end of sib2, iclass 32, count 0 2006.225.07:34:38.14#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:34:38.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:34:38.14#ibcon#[25=USB\r\n] 2006.225.07:34:38.14#ibcon#*before write, iclass 32, count 0 2006.225.07:34:38.14#ibcon#enter sib2, iclass 32, count 0 2006.225.07:34:38.14#ibcon#flushed, iclass 32, count 0 2006.225.07:34:38.14#ibcon#about to write, iclass 32, count 0 2006.225.07:34:38.14#ibcon#wrote, iclass 32, count 0 2006.225.07:34:38.14#ibcon#about to read 3, iclass 32, count 0 2006.225.07:34:38.17#ibcon#read 3, iclass 32, count 0 2006.225.07:34:38.17#ibcon#about to read 4, iclass 32, count 0 2006.225.07:34:38.17#ibcon#read 4, iclass 32, count 0 2006.225.07:34:38.17#ibcon#about to read 5, iclass 32, count 0 2006.225.07:34:38.17#ibcon#read 5, iclass 32, count 0 2006.225.07:34:38.17#ibcon#about to read 6, iclass 32, count 0 2006.225.07:34:38.17#ibcon#read 6, iclass 32, count 0 2006.225.07:34:38.17#ibcon#end of sib2, iclass 32, count 0 2006.225.07:34:38.17#ibcon#*after write, iclass 32, count 0 2006.225.07:34:38.17#ibcon#*before return 0, iclass 32, count 0 2006.225.07:34:38.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:34:38.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:34:38.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:34:38.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:34:38.17$vc4f8/valo=2,572.99 2006.225.07:34:38.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.07:34:38.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.07:34:38.17#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:38.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:34:38.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:34:38.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:34:38.17#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:34:38.17#ibcon#first serial, iclass 34, count 0 2006.225.07:34:38.17#ibcon#enter sib2, iclass 34, count 0 2006.225.07:34:38.17#ibcon#flushed, iclass 34, count 0 2006.225.07:34:38.17#ibcon#about to write, iclass 34, count 0 2006.225.07:34:38.17#ibcon#wrote, iclass 34, count 0 2006.225.07:34:38.17#ibcon#about to read 3, iclass 34, count 0 2006.225.07:34:38.20#ibcon#read 3, iclass 34, count 0 2006.225.07:34:38.20#ibcon#about to read 4, iclass 34, count 0 2006.225.07:34:38.20#ibcon#read 4, iclass 34, count 0 2006.225.07:34:38.20#ibcon#about to read 5, iclass 34, count 0 2006.225.07:34:38.20#ibcon#read 5, iclass 34, count 0 2006.225.07:34:38.20#ibcon#about to read 6, iclass 34, count 0 2006.225.07:34:38.20#ibcon#read 6, iclass 34, count 0 2006.225.07:34:38.20#ibcon#end of sib2, iclass 34, count 0 2006.225.07:34:38.20#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:34:38.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:34:38.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:34:38.20#ibcon#*before write, iclass 34, count 0 2006.225.07:34:38.20#ibcon#enter sib2, iclass 34, count 0 2006.225.07:34:38.20#ibcon#flushed, iclass 34, count 0 2006.225.07:34:38.20#ibcon#about to write, iclass 34, count 0 2006.225.07:34:38.20#ibcon#wrote, iclass 34, count 0 2006.225.07:34:38.20#ibcon#about to read 3, iclass 34, count 0 2006.225.07:34:38.24#ibcon#read 3, iclass 34, count 0 2006.225.07:34:38.24#ibcon#about to read 4, iclass 34, count 0 2006.225.07:34:38.24#ibcon#read 4, iclass 34, count 0 2006.225.07:34:38.24#ibcon#about to read 5, iclass 34, count 0 2006.225.07:34:38.24#ibcon#read 5, iclass 34, count 0 2006.225.07:34:38.24#ibcon#about to read 6, iclass 34, count 0 2006.225.07:34:38.24#ibcon#read 6, iclass 34, count 0 2006.225.07:34:38.24#ibcon#end of sib2, iclass 34, count 0 2006.225.07:34:38.24#ibcon#*after write, iclass 34, count 0 2006.225.07:34:38.24#ibcon#*before return 0, iclass 34, count 0 2006.225.07:34:38.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:34:38.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:34:38.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:34:38.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:34:38.24$vc4f8/va=2,7 2006.225.07:34:38.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.07:34:38.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.07:34:38.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:38.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:34:38.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:34:38.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:34:38.29#ibcon#enter wrdev, iclass 36, count 2 2006.225.07:34:38.29#ibcon#first serial, iclass 36, count 2 2006.225.07:34:38.29#ibcon#enter sib2, iclass 36, count 2 2006.225.07:34:38.29#ibcon#flushed, iclass 36, count 2 2006.225.07:34:38.29#ibcon#about to write, iclass 36, count 2 2006.225.07:34:38.29#ibcon#wrote, iclass 36, count 2 2006.225.07:34:38.29#ibcon#about to read 3, iclass 36, count 2 2006.225.07:34:38.31#ibcon#read 3, iclass 36, count 2 2006.225.07:34:38.31#ibcon#about to read 4, iclass 36, count 2 2006.225.07:34:38.31#ibcon#read 4, iclass 36, count 2 2006.225.07:34:38.31#ibcon#about to read 5, iclass 36, count 2 2006.225.07:34:38.31#ibcon#read 5, iclass 36, count 2 2006.225.07:34:38.31#ibcon#about to read 6, iclass 36, count 2 2006.225.07:34:38.31#ibcon#read 6, iclass 36, count 2 2006.225.07:34:38.31#ibcon#end of sib2, iclass 36, count 2 2006.225.07:34:38.31#ibcon#*mode == 0, iclass 36, count 2 2006.225.07:34:38.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.07:34:38.31#ibcon#[25=AT02-07\r\n] 2006.225.07:34:38.31#ibcon#*before write, iclass 36, count 2 2006.225.07:34:38.31#ibcon#enter sib2, iclass 36, count 2 2006.225.07:34:38.31#ibcon#flushed, iclass 36, count 2 2006.225.07:34:38.31#ibcon#about to write, iclass 36, count 2 2006.225.07:34:38.31#ibcon#wrote, iclass 36, count 2 2006.225.07:34:38.31#ibcon#about to read 3, iclass 36, count 2 2006.225.07:34:38.34#ibcon#read 3, iclass 36, count 2 2006.225.07:34:38.34#ibcon#about to read 4, iclass 36, count 2 2006.225.07:34:38.34#ibcon#read 4, iclass 36, count 2 2006.225.07:34:38.34#ibcon#about to read 5, iclass 36, count 2 2006.225.07:34:38.34#ibcon#read 5, iclass 36, count 2 2006.225.07:34:38.34#ibcon#about to read 6, iclass 36, count 2 2006.225.07:34:38.34#ibcon#read 6, iclass 36, count 2 2006.225.07:34:38.34#ibcon#end of sib2, iclass 36, count 2 2006.225.07:34:38.34#ibcon#*after write, iclass 36, count 2 2006.225.07:34:38.34#ibcon#*before return 0, iclass 36, count 2 2006.225.07:34:38.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:34:38.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:34:38.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.07:34:38.34#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:38.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:34:38.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:34:38.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:34:38.46#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:34:38.46#ibcon#first serial, iclass 36, count 0 2006.225.07:34:38.46#ibcon#enter sib2, iclass 36, count 0 2006.225.07:34:38.46#ibcon#flushed, iclass 36, count 0 2006.225.07:34:38.46#ibcon#about to write, iclass 36, count 0 2006.225.07:34:38.46#ibcon#wrote, iclass 36, count 0 2006.225.07:34:38.46#ibcon#about to read 3, iclass 36, count 0 2006.225.07:34:38.48#ibcon#read 3, iclass 36, count 0 2006.225.07:34:38.48#ibcon#about to read 4, iclass 36, count 0 2006.225.07:34:38.48#ibcon#read 4, iclass 36, count 0 2006.225.07:34:38.48#ibcon#about to read 5, iclass 36, count 0 2006.225.07:34:38.48#ibcon#read 5, iclass 36, count 0 2006.225.07:34:38.48#ibcon#about to read 6, iclass 36, count 0 2006.225.07:34:38.48#ibcon#read 6, iclass 36, count 0 2006.225.07:34:38.48#ibcon#end of sib2, iclass 36, count 0 2006.225.07:34:38.48#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:34:38.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:34:38.48#ibcon#[25=USB\r\n] 2006.225.07:34:38.48#ibcon#*before write, iclass 36, count 0 2006.225.07:34:38.48#ibcon#enter sib2, iclass 36, count 0 2006.225.07:34:38.48#ibcon#flushed, iclass 36, count 0 2006.225.07:34:38.48#ibcon#about to write, iclass 36, count 0 2006.225.07:34:38.48#ibcon#wrote, iclass 36, count 0 2006.225.07:34:38.48#ibcon#about to read 3, iclass 36, count 0 2006.225.07:34:38.51#ibcon#read 3, iclass 36, count 0 2006.225.07:34:38.51#ibcon#about to read 4, iclass 36, count 0 2006.225.07:34:38.51#ibcon#read 4, iclass 36, count 0 2006.225.07:34:38.51#ibcon#about to read 5, iclass 36, count 0 2006.225.07:34:38.51#ibcon#read 5, iclass 36, count 0 2006.225.07:34:38.51#ibcon#about to read 6, iclass 36, count 0 2006.225.07:34:38.51#ibcon#read 6, iclass 36, count 0 2006.225.07:34:38.51#ibcon#end of sib2, iclass 36, count 0 2006.225.07:34:38.51#ibcon#*after write, iclass 36, count 0 2006.225.07:34:38.51#ibcon#*before return 0, iclass 36, count 0 2006.225.07:34:38.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:34:38.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:34:38.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:34:38.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:34:38.51$vc4f8/valo=3,672.99 2006.225.07:34:38.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.07:34:38.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.07:34:38.51#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:38.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:34:38.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:34:38.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:34:38.51#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:34:38.51#ibcon#first serial, iclass 38, count 0 2006.225.07:34:38.51#ibcon#enter sib2, iclass 38, count 0 2006.225.07:34:38.51#ibcon#flushed, iclass 38, count 0 2006.225.07:34:38.51#ibcon#about to write, iclass 38, count 0 2006.225.07:34:38.51#ibcon#wrote, iclass 38, count 0 2006.225.07:34:38.51#ibcon#about to read 3, iclass 38, count 0 2006.225.07:34:38.54#ibcon#read 3, iclass 38, count 0 2006.225.07:34:38.54#ibcon#about to read 4, iclass 38, count 0 2006.225.07:34:38.54#ibcon#read 4, iclass 38, count 0 2006.225.07:34:38.54#ibcon#about to read 5, iclass 38, count 0 2006.225.07:34:38.54#ibcon#read 5, iclass 38, count 0 2006.225.07:34:38.54#ibcon#about to read 6, iclass 38, count 0 2006.225.07:34:38.54#ibcon#read 6, iclass 38, count 0 2006.225.07:34:38.54#ibcon#end of sib2, iclass 38, count 0 2006.225.07:34:38.54#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:34:38.54#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:34:38.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:34:38.54#ibcon#*before write, iclass 38, count 0 2006.225.07:34:38.54#ibcon#enter sib2, iclass 38, count 0 2006.225.07:34:38.54#ibcon#flushed, iclass 38, count 0 2006.225.07:34:38.54#ibcon#about to write, iclass 38, count 0 2006.225.07:34:38.54#ibcon#wrote, iclass 38, count 0 2006.225.07:34:38.54#ibcon#about to read 3, iclass 38, count 0 2006.225.07:34:38.58#ibcon#read 3, iclass 38, count 0 2006.225.07:34:38.58#ibcon#about to read 4, iclass 38, count 0 2006.225.07:34:38.58#ibcon#read 4, iclass 38, count 0 2006.225.07:34:38.58#ibcon#about to read 5, iclass 38, count 0 2006.225.07:34:38.58#ibcon#read 5, iclass 38, count 0 2006.225.07:34:38.58#ibcon#about to read 6, iclass 38, count 0 2006.225.07:34:38.58#ibcon#read 6, iclass 38, count 0 2006.225.07:34:38.58#ibcon#end of sib2, iclass 38, count 0 2006.225.07:34:38.58#ibcon#*after write, iclass 38, count 0 2006.225.07:34:38.58#ibcon#*before return 0, iclass 38, count 0 2006.225.07:34:38.58#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:34:38.58#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:34:38.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:34:38.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:34:38.58$vc4f8/va=3,6 2006.225.07:34:38.58#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.225.07:34:38.58#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.225.07:34:38.58#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:38.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:34:38.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:34:38.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:34:38.63#ibcon#enter wrdev, iclass 40, count 2 2006.225.07:34:38.63#ibcon#first serial, iclass 40, count 2 2006.225.07:34:38.63#ibcon#enter sib2, iclass 40, count 2 2006.225.07:34:38.63#ibcon#flushed, iclass 40, count 2 2006.225.07:34:38.63#ibcon#about to write, iclass 40, count 2 2006.225.07:34:38.63#ibcon#wrote, iclass 40, count 2 2006.225.07:34:38.63#ibcon#about to read 3, iclass 40, count 2 2006.225.07:34:38.65#ibcon#read 3, iclass 40, count 2 2006.225.07:34:38.65#ibcon#about to read 4, iclass 40, count 2 2006.225.07:34:38.65#ibcon#read 4, iclass 40, count 2 2006.225.07:34:38.65#ibcon#about to read 5, iclass 40, count 2 2006.225.07:34:38.65#ibcon#read 5, iclass 40, count 2 2006.225.07:34:38.65#ibcon#about to read 6, iclass 40, count 2 2006.225.07:34:38.65#ibcon#read 6, iclass 40, count 2 2006.225.07:34:38.65#ibcon#end of sib2, iclass 40, count 2 2006.225.07:34:38.65#ibcon#*mode == 0, iclass 40, count 2 2006.225.07:34:38.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.225.07:34:38.65#ibcon#[25=AT03-06\r\n] 2006.225.07:34:38.65#ibcon#*before write, iclass 40, count 2 2006.225.07:34:38.65#ibcon#enter sib2, iclass 40, count 2 2006.225.07:34:38.65#ibcon#flushed, iclass 40, count 2 2006.225.07:34:38.65#ibcon#about to write, iclass 40, count 2 2006.225.07:34:38.65#ibcon#wrote, iclass 40, count 2 2006.225.07:34:38.65#ibcon#about to read 3, iclass 40, count 2 2006.225.07:34:38.68#ibcon#read 3, iclass 40, count 2 2006.225.07:34:38.68#ibcon#about to read 4, iclass 40, count 2 2006.225.07:34:38.68#ibcon#read 4, iclass 40, count 2 2006.225.07:34:38.68#ibcon#about to read 5, iclass 40, count 2 2006.225.07:34:38.68#ibcon#read 5, iclass 40, count 2 2006.225.07:34:38.68#ibcon#about to read 6, iclass 40, count 2 2006.225.07:34:38.68#ibcon#read 6, iclass 40, count 2 2006.225.07:34:38.68#ibcon#end of sib2, iclass 40, count 2 2006.225.07:34:38.68#ibcon#*after write, iclass 40, count 2 2006.225.07:34:38.68#ibcon#*before return 0, iclass 40, count 2 2006.225.07:34:38.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:34:38.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:34:38.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.225.07:34:38.68#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:38.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:34:38.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:34:38.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:34:38.80#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:34:38.80#ibcon#first serial, iclass 40, count 0 2006.225.07:34:38.80#ibcon#enter sib2, iclass 40, count 0 2006.225.07:34:38.80#ibcon#flushed, iclass 40, count 0 2006.225.07:34:38.80#ibcon#about to write, iclass 40, count 0 2006.225.07:34:38.80#ibcon#wrote, iclass 40, count 0 2006.225.07:34:38.80#ibcon#about to read 3, iclass 40, count 0 2006.225.07:34:38.82#ibcon#read 3, iclass 40, count 0 2006.225.07:34:38.82#ibcon#about to read 4, iclass 40, count 0 2006.225.07:34:38.82#ibcon#read 4, iclass 40, count 0 2006.225.07:34:38.82#ibcon#about to read 5, iclass 40, count 0 2006.225.07:34:38.82#ibcon#read 5, iclass 40, count 0 2006.225.07:34:38.82#ibcon#about to read 6, iclass 40, count 0 2006.225.07:34:38.82#ibcon#read 6, iclass 40, count 0 2006.225.07:34:38.82#ibcon#end of sib2, iclass 40, count 0 2006.225.07:34:38.82#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:34:38.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:34:38.82#ibcon#[25=USB\r\n] 2006.225.07:34:38.82#ibcon#*before write, iclass 40, count 0 2006.225.07:34:38.82#ibcon#enter sib2, iclass 40, count 0 2006.225.07:34:38.82#ibcon#flushed, iclass 40, count 0 2006.225.07:34:38.82#ibcon#about to write, iclass 40, count 0 2006.225.07:34:38.82#ibcon#wrote, iclass 40, count 0 2006.225.07:34:38.82#ibcon#about to read 3, iclass 40, count 0 2006.225.07:34:38.85#ibcon#read 3, iclass 40, count 0 2006.225.07:34:38.85#ibcon#about to read 4, iclass 40, count 0 2006.225.07:34:38.85#ibcon#read 4, iclass 40, count 0 2006.225.07:34:38.85#ibcon#about to read 5, iclass 40, count 0 2006.225.07:34:38.85#ibcon#read 5, iclass 40, count 0 2006.225.07:34:38.85#ibcon#about to read 6, iclass 40, count 0 2006.225.07:34:38.85#ibcon#read 6, iclass 40, count 0 2006.225.07:34:38.85#ibcon#end of sib2, iclass 40, count 0 2006.225.07:34:38.85#ibcon#*after write, iclass 40, count 0 2006.225.07:34:38.85#ibcon#*before return 0, iclass 40, count 0 2006.225.07:34:38.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:34:38.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:34:38.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:34:38.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:34:38.85$vc4f8/valo=4,832.99 2006.225.07:34:38.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.07:34:38.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.07:34:38.85#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:38.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:34:38.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:34:38.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:34:38.85#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:34:38.85#ibcon#first serial, iclass 4, count 0 2006.225.07:34:38.85#ibcon#enter sib2, iclass 4, count 0 2006.225.07:34:38.85#ibcon#flushed, iclass 4, count 0 2006.225.07:34:38.85#ibcon#about to write, iclass 4, count 0 2006.225.07:34:38.85#ibcon#wrote, iclass 4, count 0 2006.225.07:34:38.85#ibcon#about to read 3, iclass 4, count 0 2006.225.07:34:38.88#ibcon#read 3, iclass 4, count 0 2006.225.07:34:38.88#ibcon#about to read 4, iclass 4, count 0 2006.225.07:34:38.88#ibcon#read 4, iclass 4, count 0 2006.225.07:34:38.88#ibcon#about to read 5, iclass 4, count 0 2006.225.07:34:38.88#ibcon#read 5, iclass 4, count 0 2006.225.07:34:38.88#ibcon#about to read 6, iclass 4, count 0 2006.225.07:34:38.88#ibcon#read 6, iclass 4, count 0 2006.225.07:34:38.88#ibcon#end of sib2, iclass 4, count 0 2006.225.07:34:38.88#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:34:38.88#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:34:38.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:34:38.88#ibcon#*before write, iclass 4, count 0 2006.225.07:34:38.88#ibcon#enter sib2, iclass 4, count 0 2006.225.07:34:38.88#ibcon#flushed, iclass 4, count 0 2006.225.07:34:38.88#ibcon#about to write, iclass 4, count 0 2006.225.07:34:38.88#ibcon#wrote, iclass 4, count 0 2006.225.07:34:38.88#ibcon#about to read 3, iclass 4, count 0 2006.225.07:34:38.92#ibcon#read 3, iclass 4, count 0 2006.225.07:34:38.92#ibcon#about to read 4, iclass 4, count 0 2006.225.07:34:38.92#ibcon#read 4, iclass 4, count 0 2006.225.07:34:38.92#ibcon#about to read 5, iclass 4, count 0 2006.225.07:34:38.92#ibcon#read 5, iclass 4, count 0 2006.225.07:34:38.92#ibcon#about to read 6, iclass 4, count 0 2006.225.07:34:38.92#ibcon#read 6, iclass 4, count 0 2006.225.07:34:38.92#ibcon#end of sib2, iclass 4, count 0 2006.225.07:34:38.92#ibcon#*after write, iclass 4, count 0 2006.225.07:34:38.92#ibcon#*before return 0, iclass 4, count 0 2006.225.07:34:38.92#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:34:38.92#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:34:38.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:34:38.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:34:38.92$vc4f8/va=4,7 2006.225.07:34:38.92#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.225.07:34:38.92#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.225.07:34:38.92#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:38.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:34:38.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:34:38.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:34:38.97#ibcon#enter wrdev, iclass 6, count 2 2006.225.07:34:38.97#ibcon#first serial, iclass 6, count 2 2006.225.07:34:38.97#ibcon#enter sib2, iclass 6, count 2 2006.225.07:34:38.97#ibcon#flushed, iclass 6, count 2 2006.225.07:34:38.97#ibcon#about to write, iclass 6, count 2 2006.225.07:34:38.97#ibcon#wrote, iclass 6, count 2 2006.225.07:34:38.97#ibcon#about to read 3, iclass 6, count 2 2006.225.07:34:38.99#ibcon#read 3, iclass 6, count 2 2006.225.07:34:38.99#ibcon#about to read 4, iclass 6, count 2 2006.225.07:34:38.99#ibcon#read 4, iclass 6, count 2 2006.225.07:34:38.99#ibcon#about to read 5, iclass 6, count 2 2006.225.07:34:38.99#ibcon#read 5, iclass 6, count 2 2006.225.07:34:38.99#ibcon#about to read 6, iclass 6, count 2 2006.225.07:34:38.99#ibcon#read 6, iclass 6, count 2 2006.225.07:34:38.99#ibcon#end of sib2, iclass 6, count 2 2006.225.07:34:38.99#ibcon#*mode == 0, iclass 6, count 2 2006.225.07:34:38.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.225.07:34:38.99#ibcon#[25=AT04-07\r\n] 2006.225.07:34:38.99#ibcon#*before write, iclass 6, count 2 2006.225.07:34:38.99#ibcon#enter sib2, iclass 6, count 2 2006.225.07:34:38.99#ibcon#flushed, iclass 6, count 2 2006.225.07:34:38.99#ibcon#about to write, iclass 6, count 2 2006.225.07:34:38.99#ibcon#wrote, iclass 6, count 2 2006.225.07:34:38.99#ibcon#about to read 3, iclass 6, count 2 2006.225.07:34:39.02#ibcon#read 3, iclass 6, count 2 2006.225.07:34:39.02#ibcon#about to read 4, iclass 6, count 2 2006.225.07:34:39.02#ibcon#read 4, iclass 6, count 2 2006.225.07:34:39.02#ibcon#about to read 5, iclass 6, count 2 2006.225.07:34:39.02#ibcon#read 5, iclass 6, count 2 2006.225.07:34:39.02#ibcon#about to read 6, iclass 6, count 2 2006.225.07:34:39.02#ibcon#read 6, iclass 6, count 2 2006.225.07:34:39.02#ibcon#end of sib2, iclass 6, count 2 2006.225.07:34:39.02#ibcon#*after write, iclass 6, count 2 2006.225.07:34:39.02#ibcon#*before return 0, iclass 6, count 2 2006.225.07:34:39.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:34:39.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:34:39.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.225.07:34:39.02#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:39.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:34:39.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:34:39.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:34:39.14#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:34:39.14#ibcon#first serial, iclass 6, count 0 2006.225.07:34:39.14#ibcon#enter sib2, iclass 6, count 0 2006.225.07:34:39.14#ibcon#flushed, iclass 6, count 0 2006.225.07:34:39.14#ibcon#about to write, iclass 6, count 0 2006.225.07:34:39.14#ibcon#wrote, iclass 6, count 0 2006.225.07:34:39.14#ibcon#about to read 3, iclass 6, count 0 2006.225.07:34:39.16#ibcon#read 3, iclass 6, count 0 2006.225.07:34:39.16#ibcon#about to read 4, iclass 6, count 0 2006.225.07:34:39.16#ibcon#read 4, iclass 6, count 0 2006.225.07:34:39.16#ibcon#about to read 5, iclass 6, count 0 2006.225.07:34:39.16#ibcon#read 5, iclass 6, count 0 2006.225.07:34:39.16#ibcon#about to read 6, iclass 6, count 0 2006.225.07:34:39.16#ibcon#read 6, iclass 6, count 0 2006.225.07:34:39.16#ibcon#end of sib2, iclass 6, count 0 2006.225.07:34:39.16#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:34:39.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:34:39.16#ibcon#[25=USB\r\n] 2006.225.07:34:39.16#ibcon#*before write, iclass 6, count 0 2006.225.07:34:39.16#ibcon#enter sib2, iclass 6, count 0 2006.225.07:34:39.16#ibcon#flushed, iclass 6, count 0 2006.225.07:34:39.16#ibcon#about to write, iclass 6, count 0 2006.225.07:34:39.16#ibcon#wrote, iclass 6, count 0 2006.225.07:34:39.16#ibcon#about to read 3, iclass 6, count 0 2006.225.07:34:39.19#ibcon#read 3, iclass 6, count 0 2006.225.07:34:39.19#ibcon#about to read 4, iclass 6, count 0 2006.225.07:34:39.19#ibcon#read 4, iclass 6, count 0 2006.225.07:34:39.19#ibcon#about to read 5, iclass 6, count 0 2006.225.07:34:39.19#ibcon#read 5, iclass 6, count 0 2006.225.07:34:39.19#ibcon#about to read 6, iclass 6, count 0 2006.225.07:34:39.19#ibcon#read 6, iclass 6, count 0 2006.225.07:34:39.19#ibcon#end of sib2, iclass 6, count 0 2006.225.07:34:39.19#ibcon#*after write, iclass 6, count 0 2006.225.07:34:39.19#ibcon#*before return 0, iclass 6, count 0 2006.225.07:34:39.19#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:34:39.19#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:34:39.19#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:34:39.19#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:34:39.19$vc4f8/valo=5,652.99 2006.225.07:34:39.19#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.07:34:39.19#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.07:34:39.19#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:39.19#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:34:39.19#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:34:39.19#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:34:39.19#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:34:39.19#ibcon#first serial, iclass 10, count 0 2006.225.07:34:39.19#ibcon#enter sib2, iclass 10, count 0 2006.225.07:34:39.19#ibcon#flushed, iclass 10, count 0 2006.225.07:34:39.19#ibcon#about to write, iclass 10, count 0 2006.225.07:34:39.19#ibcon#wrote, iclass 10, count 0 2006.225.07:34:39.19#ibcon#about to read 3, iclass 10, count 0 2006.225.07:34:39.21#ibcon#read 3, iclass 10, count 0 2006.225.07:34:39.21#ibcon#about to read 4, iclass 10, count 0 2006.225.07:34:39.21#ibcon#read 4, iclass 10, count 0 2006.225.07:34:39.21#ibcon#about to read 5, iclass 10, count 0 2006.225.07:34:39.21#ibcon#read 5, iclass 10, count 0 2006.225.07:34:39.21#ibcon#about to read 6, iclass 10, count 0 2006.225.07:34:39.21#ibcon#read 6, iclass 10, count 0 2006.225.07:34:39.21#ibcon#end of sib2, iclass 10, count 0 2006.225.07:34:39.21#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:34:39.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:34:39.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:34:39.21#ibcon#*before write, iclass 10, count 0 2006.225.07:34:39.21#ibcon#enter sib2, iclass 10, count 0 2006.225.07:34:39.21#ibcon#flushed, iclass 10, count 0 2006.225.07:34:39.21#ibcon#about to write, iclass 10, count 0 2006.225.07:34:39.21#ibcon#wrote, iclass 10, count 0 2006.225.07:34:39.21#ibcon#about to read 3, iclass 10, count 0 2006.225.07:34:39.25#ibcon#read 3, iclass 10, count 0 2006.225.07:34:39.25#ibcon#about to read 4, iclass 10, count 0 2006.225.07:34:39.25#ibcon#read 4, iclass 10, count 0 2006.225.07:34:39.25#ibcon#about to read 5, iclass 10, count 0 2006.225.07:34:39.25#ibcon#read 5, iclass 10, count 0 2006.225.07:34:39.25#ibcon#about to read 6, iclass 10, count 0 2006.225.07:34:39.25#ibcon#read 6, iclass 10, count 0 2006.225.07:34:39.25#ibcon#end of sib2, iclass 10, count 0 2006.225.07:34:39.25#ibcon#*after write, iclass 10, count 0 2006.225.07:34:39.25#ibcon#*before return 0, iclass 10, count 0 2006.225.07:34:39.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:34:39.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:34:39.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:34:39.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:34:39.25$vc4f8/va=5,7 2006.225.07:34:39.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.07:34:39.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.07:34:39.25#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:39.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:34:39.31#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:34:39.31#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:34:39.31#ibcon#enter wrdev, iclass 12, count 2 2006.225.07:34:39.31#ibcon#first serial, iclass 12, count 2 2006.225.07:34:39.31#ibcon#enter sib2, iclass 12, count 2 2006.225.07:34:39.31#ibcon#flushed, iclass 12, count 2 2006.225.07:34:39.31#ibcon#about to write, iclass 12, count 2 2006.225.07:34:39.31#ibcon#wrote, iclass 12, count 2 2006.225.07:34:39.31#ibcon#about to read 3, iclass 12, count 2 2006.225.07:34:39.33#ibcon#read 3, iclass 12, count 2 2006.225.07:34:39.33#ibcon#about to read 4, iclass 12, count 2 2006.225.07:34:39.33#ibcon#read 4, iclass 12, count 2 2006.225.07:34:39.33#ibcon#about to read 5, iclass 12, count 2 2006.225.07:34:39.33#ibcon#read 5, iclass 12, count 2 2006.225.07:34:39.33#ibcon#about to read 6, iclass 12, count 2 2006.225.07:34:39.33#ibcon#read 6, iclass 12, count 2 2006.225.07:34:39.33#ibcon#end of sib2, iclass 12, count 2 2006.225.07:34:39.33#ibcon#*mode == 0, iclass 12, count 2 2006.225.07:34:39.33#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.07:34:39.33#ibcon#[25=AT05-07\r\n] 2006.225.07:34:39.33#ibcon#*before write, iclass 12, count 2 2006.225.07:34:39.33#ibcon#enter sib2, iclass 12, count 2 2006.225.07:34:39.33#ibcon#flushed, iclass 12, count 2 2006.225.07:34:39.33#ibcon#about to write, iclass 12, count 2 2006.225.07:34:39.33#ibcon#wrote, iclass 12, count 2 2006.225.07:34:39.33#ibcon#about to read 3, iclass 12, count 2 2006.225.07:34:39.36#ibcon#read 3, iclass 12, count 2 2006.225.07:34:39.36#ibcon#about to read 4, iclass 12, count 2 2006.225.07:34:39.36#ibcon#read 4, iclass 12, count 2 2006.225.07:34:39.36#ibcon#about to read 5, iclass 12, count 2 2006.225.07:34:39.36#ibcon#read 5, iclass 12, count 2 2006.225.07:34:39.36#ibcon#about to read 6, iclass 12, count 2 2006.225.07:34:39.36#ibcon#read 6, iclass 12, count 2 2006.225.07:34:39.36#ibcon#end of sib2, iclass 12, count 2 2006.225.07:34:39.36#ibcon#*after write, iclass 12, count 2 2006.225.07:34:39.36#ibcon#*before return 0, iclass 12, count 2 2006.225.07:34:39.36#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:34:39.36#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:34:39.36#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.07:34:39.36#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:39.36#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:34:39.48#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:34:39.48#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:34:39.48#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:34:39.48#ibcon#first serial, iclass 12, count 0 2006.225.07:34:39.48#ibcon#enter sib2, iclass 12, count 0 2006.225.07:34:39.48#ibcon#flushed, iclass 12, count 0 2006.225.07:34:39.48#ibcon#about to write, iclass 12, count 0 2006.225.07:34:39.48#ibcon#wrote, iclass 12, count 0 2006.225.07:34:39.48#ibcon#about to read 3, iclass 12, count 0 2006.225.07:34:39.50#ibcon#read 3, iclass 12, count 0 2006.225.07:34:39.50#ibcon#about to read 4, iclass 12, count 0 2006.225.07:34:39.50#ibcon#read 4, iclass 12, count 0 2006.225.07:34:39.50#ibcon#about to read 5, iclass 12, count 0 2006.225.07:34:39.50#ibcon#read 5, iclass 12, count 0 2006.225.07:34:39.50#ibcon#about to read 6, iclass 12, count 0 2006.225.07:34:39.50#ibcon#read 6, iclass 12, count 0 2006.225.07:34:39.50#ibcon#end of sib2, iclass 12, count 0 2006.225.07:34:39.50#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:34:39.50#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:34:39.50#ibcon#[25=USB\r\n] 2006.225.07:34:39.50#ibcon#*before write, iclass 12, count 0 2006.225.07:34:39.50#ibcon#enter sib2, iclass 12, count 0 2006.225.07:34:39.50#ibcon#flushed, iclass 12, count 0 2006.225.07:34:39.50#ibcon#about to write, iclass 12, count 0 2006.225.07:34:39.50#ibcon#wrote, iclass 12, count 0 2006.225.07:34:39.50#ibcon#about to read 3, iclass 12, count 0 2006.225.07:34:39.53#ibcon#read 3, iclass 12, count 0 2006.225.07:34:39.53#ibcon#about to read 4, iclass 12, count 0 2006.225.07:34:39.53#ibcon#read 4, iclass 12, count 0 2006.225.07:34:39.53#ibcon#about to read 5, iclass 12, count 0 2006.225.07:34:39.53#ibcon#read 5, iclass 12, count 0 2006.225.07:34:39.53#ibcon#about to read 6, iclass 12, count 0 2006.225.07:34:39.53#ibcon#read 6, iclass 12, count 0 2006.225.07:34:39.53#ibcon#end of sib2, iclass 12, count 0 2006.225.07:34:39.53#ibcon#*after write, iclass 12, count 0 2006.225.07:34:39.53#ibcon#*before return 0, iclass 12, count 0 2006.225.07:34:39.53#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:34:39.53#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:34:39.53#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:34:39.53#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:34:39.53$vc4f8/valo=6,772.99 2006.225.07:34:39.53#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.07:34:39.53#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.07:34:39.53#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:39.53#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:34:39.53#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:34:39.53#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:34:39.53#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:34:39.53#ibcon#first serial, iclass 14, count 0 2006.225.07:34:39.53#ibcon#enter sib2, iclass 14, count 0 2006.225.07:34:39.53#ibcon#flushed, iclass 14, count 0 2006.225.07:34:39.53#ibcon#about to write, iclass 14, count 0 2006.225.07:34:39.53#ibcon#wrote, iclass 14, count 0 2006.225.07:34:39.53#ibcon#about to read 3, iclass 14, count 0 2006.225.07:34:39.55#ibcon#read 3, iclass 14, count 0 2006.225.07:34:39.55#ibcon#about to read 4, iclass 14, count 0 2006.225.07:34:39.55#ibcon#read 4, iclass 14, count 0 2006.225.07:34:39.55#ibcon#about to read 5, iclass 14, count 0 2006.225.07:34:39.55#ibcon#read 5, iclass 14, count 0 2006.225.07:34:39.55#ibcon#about to read 6, iclass 14, count 0 2006.225.07:34:39.55#ibcon#read 6, iclass 14, count 0 2006.225.07:34:39.55#ibcon#end of sib2, iclass 14, count 0 2006.225.07:34:39.55#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:34:39.55#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:34:39.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:34:39.55#ibcon#*before write, iclass 14, count 0 2006.225.07:34:39.55#ibcon#enter sib2, iclass 14, count 0 2006.225.07:34:39.55#ibcon#flushed, iclass 14, count 0 2006.225.07:34:39.55#ibcon#about to write, iclass 14, count 0 2006.225.07:34:39.55#ibcon#wrote, iclass 14, count 0 2006.225.07:34:39.55#ibcon#about to read 3, iclass 14, count 0 2006.225.07:34:39.59#ibcon#read 3, iclass 14, count 0 2006.225.07:34:39.59#ibcon#about to read 4, iclass 14, count 0 2006.225.07:34:39.59#ibcon#read 4, iclass 14, count 0 2006.225.07:34:39.59#ibcon#about to read 5, iclass 14, count 0 2006.225.07:34:39.59#ibcon#read 5, iclass 14, count 0 2006.225.07:34:39.59#ibcon#about to read 6, iclass 14, count 0 2006.225.07:34:39.59#ibcon#read 6, iclass 14, count 0 2006.225.07:34:39.59#ibcon#end of sib2, iclass 14, count 0 2006.225.07:34:39.59#ibcon#*after write, iclass 14, count 0 2006.225.07:34:39.59#ibcon#*before return 0, iclass 14, count 0 2006.225.07:34:39.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:34:39.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:34:39.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:34:39.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:34:39.59$vc4f8/va=6,6 2006.225.07:34:39.59#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.07:34:39.59#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.07:34:39.59#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:39.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:34:39.65#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:34:39.65#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:34:39.65#ibcon#enter wrdev, iclass 16, count 2 2006.225.07:34:39.65#ibcon#first serial, iclass 16, count 2 2006.225.07:34:39.65#ibcon#enter sib2, iclass 16, count 2 2006.225.07:34:39.65#ibcon#flushed, iclass 16, count 2 2006.225.07:34:39.65#ibcon#about to write, iclass 16, count 2 2006.225.07:34:39.65#ibcon#wrote, iclass 16, count 2 2006.225.07:34:39.65#ibcon#about to read 3, iclass 16, count 2 2006.225.07:34:39.67#ibcon#read 3, iclass 16, count 2 2006.225.07:34:39.67#ibcon#about to read 4, iclass 16, count 2 2006.225.07:34:39.67#ibcon#read 4, iclass 16, count 2 2006.225.07:34:39.67#ibcon#about to read 5, iclass 16, count 2 2006.225.07:34:39.67#ibcon#read 5, iclass 16, count 2 2006.225.07:34:39.67#ibcon#about to read 6, iclass 16, count 2 2006.225.07:34:39.67#ibcon#read 6, iclass 16, count 2 2006.225.07:34:39.67#ibcon#end of sib2, iclass 16, count 2 2006.225.07:34:39.67#ibcon#*mode == 0, iclass 16, count 2 2006.225.07:34:39.67#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.07:34:39.67#ibcon#[25=AT06-06\r\n] 2006.225.07:34:39.67#ibcon#*before write, iclass 16, count 2 2006.225.07:34:39.67#ibcon#enter sib2, iclass 16, count 2 2006.225.07:34:39.67#ibcon#flushed, iclass 16, count 2 2006.225.07:34:39.67#ibcon#about to write, iclass 16, count 2 2006.225.07:34:39.67#ibcon#wrote, iclass 16, count 2 2006.225.07:34:39.67#ibcon#about to read 3, iclass 16, count 2 2006.225.07:34:39.70#ibcon#read 3, iclass 16, count 2 2006.225.07:34:39.70#ibcon#about to read 4, iclass 16, count 2 2006.225.07:34:39.70#ibcon#read 4, iclass 16, count 2 2006.225.07:34:39.70#ibcon#about to read 5, iclass 16, count 2 2006.225.07:34:39.70#ibcon#read 5, iclass 16, count 2 2006.225.07:34:39.70#ibcon#about to read 6, iclass 16, count 2 2006.225.07:34:39.70#ibcon#read 6, iclass 16, count 2 2006.225.07:34:39.70#ibcon#end of sib2, iclass 16, count 2 2006.225.07:34:39.70#ibcon#*after write, iclass 16, count 2 2006.225.07:34:39.70#ibcon#*before return 0, iclass 16, count 2 2006.225.07:34:39.70#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:34:39.70#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:34:39.70#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.07:34:39.70#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:39.70#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:34:39.82#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:34:39.82#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:34:39.82#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:34:39.82#ibcon#first serial, iclass 16, count 0 2006.225.07:34:39.82#ibcon#enter sib2, iclass 16, count 0 2006.225.07:34:39.82#ibcon#flushed, iclass 16, count 0 2006.225.07:34:39.82#ibcon#about to write, iclass 16, count 0 2006.225.07:34:39.82#ibcon#wrote, iclass 16, count 0 2006.225.07:34:39.82#ibcon#about to read 3, iclass 16, count 0 2006.225.07:34:39.84#ibcon#read 3, iclass 16, count 0 2006.225.07:34:39.84#ibcon#about to read 4, iclass 16, count 0 2006.225.07:34:39.84#ibcon#read 4, iclass 16, count 0 2006.225.07:34:39.84#ibcon#about to read 5, iclass 16, count 0 2006.225.07:34:39.84#ibcon#read 5, iclass 16, count 0 2006.225.07:34:39.84#ibcon#about to read 6, iclass 16, count 0 2006.225.07:34:39.84#ibcon#read 6, iclass 16, count 0 2006.225.07:34:39.84#ibcon#end of sib2, iclass 16, count 0 2006.225.07:34:39.84#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:34:39.84#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:34:39.84#ibcon#[25=USB\r\n] 2006.225.07:34:39.84#ibcon#*before write, iclass 16, count 0 2006.225.07:34:39.84#ibcon#enter sib2, iclass 16, count 0 2006.225.07:34:39.84#ibcon#flushed, iclass 16, count 0 2006.225.07:34:39.84#ibcon#about to write, iclass 16, count 0 2006.225.07:34:39.84#ibcon#wrote, iclass 16, count 0 2006.225.07:34:39.84#ibcon#about to read 3, iclass 16, count 0 2006.225.07:34:39.87#ibcon#read 3, iclass 16, count 0 2006.225.07:34:39.87#ibcon#about to read 4, iclass 16, count 0 2006.225.07:34:39.87#ibcon#read 4, iclass 16, count 0 2006.225.07:34:39.87#ibcon#about to read 5, iclass 16, count 0 2006.225.07:34:39.87#ibcon#read 5, iclass 16, count 0 2006.225.07:34:39.87#ibcon#about to read 6, iclass 16, count 0 2006.225.07:34:39.87#ibcon#read 6, iclass 16, count 0 2006.225.07:34:39.87#ibcon#end of sib2, iclass 16, count 0 2006.225.07:34:39.87#ibcon#*after write, iclass 16, count 0 2006.225.07:34:39.87#ibcon#*before return 0, iclass 16, count 0 2006.225.07:34:39.87#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:34:39.87#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:34:39.87#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:34:39.87#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:34:39.87$vc4f8/valo=7,832.99 2006.225.07:34:39.87#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.07:34:39.87#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.07:34:39.87#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:39.87#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:34:39.87#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:34:39.87#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:34:39.87#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:34:39.87#ibcon#first serial, iclass 18, count 0 2006.225.07:34:39.87#ibcon#enter sib2, iclass 18, count 0 2006.225.07:34:39.87#ibcon#flushed, iclass 18, count 0 2006.225.07:34:39.87#ibcon#about to write, iclass 18, count 0 2006.225.07:34:39.87#ibcon#wrote, iclass 18, count 0 2006.225.07:34:39.87#ibcon#about to read 3, iclass 18, count 0 2006.225.07:34:39.89#ibcon#read 3, iclass 18, count 0 2006.225.07:34:39.89#ibcon#about to read 4, iclass 18, count 0 2006.225.07:34:39.89#ibcon#read 4, iclass 18, count 0 2006.225.07:34:39.89#ibcon#about to read 5, iclass 18, count 0 2006.225.07:34:39.89#ibcon#read 5, iclass 18, count 0 2006.225.07:34:39.89#ibcon#about to read 6, iclass 18, count 0 2006.225.07:34:39.89#ibcon#read 6, iclass 18, count 0 2006.225.07:34:39.89#ibcon#end of sib2, iclass 18, count 0 2006.225.07:34:39.89#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:34:39.89#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:34:39.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:34:39.89#ibcon#*before write, iclass 18, count 0 2006.225.07:34:39.89#ibcon#enter sib2, iclass 18, count 0 2006.225.07:34:39.89#ibcon#flushed, iclass 18, count 0 2006.225.07:34:39.89#ibcon#about to write, iclass 18, count 0 2006.225.07:34:39.89#ibcon#wrote, iclass 18, count 0 2006.225.07:34:39.89#ibcon#about to read 3, iclass 18, count 0 2006.225.07:34:39.93#ibcon#read 3, iclass 18, count 0 2006.225.07:34:39.93#ibcon#about to read 4, iclass 18, count 0 2006.225.07:34:39.93#ibcon#read 4, iclass 18, count 0 2006.225.07:34:39.93#ibcon#about to read 5, iclass 18, count 0 2006.225.07:34:39.93#ibcon#read 5, iclass 18, count 0 2006.225.07:34:39.93#ibcon#about to read 6, iclass 18, count 0 2006.225.07:34:39.93#ibcon#read 6, iclass 18, count 0 2006.225.07:34:39.93#ibcon#end of sib2, iclass 18, count 0 2006.225.07:34:39.93#ibcon#*after write, iclass 18, count 0 2006.225.07:34:39.93#ibcon#*before return 0, iclass 18, count 0 2006.225.07:34:39.93#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:34:39.93#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:34:39.93#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:34:39.93#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:34:39.93$vc4f8/va=7,6 2006.225.07:34:39.93#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.07:34:39.93#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.07:34:39.93#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:39.93#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:34:39.99#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:34:39.99#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:34:39.99#ibcon#enter wrdev, iclass 20, count 2 2006.225.07:34:39.99#ibcon#first serial, iclass 20, count 2 2006.225.07:34:39.99#ibcon#enter sib2, iclass 20, count 2 2006.225.07:34:39.99#ibcon#flushed, iclass 20, count 2 2006.225.07:34:39.99#ibcon#about to write, iclass 20, count 2 2006.225.07:34:39.99#ibcon#wrote, iclass 20, count 2 2006.225.07:34:39.99#ibcon#about to read 3, iclass 20, count 2 2006.225.07:34:40.01#ibcon#read 3, iclass 20, count 2 2006.225.07:34:40.01#ibcon#about to read 4, iclass 20, count 2 2006.225.07:34:40.01#ibcon#read 4, iclass 20, count 2 2006.225.07:34:40.01#ibcon#about to read 5, iclass 20, count 2 2006.225.07:34:40.01#ibcon#read 5, iclass 20, count 2 2006.225.07:34:40.01#ibcon#about to read 6, iclass 20, count 2 2006.225.07:34:40.01#ibcon#read 6, iclass 20, count 2 2006.225.07:34:40.01#ibcon#end of sib2, iclass 20, count 2 2006.225.07:34:40.01#ibcon#*mode == 0, iclass 20, count 2 2006.225.07:34:40.01#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.07:34:40.01#ibcon#[25=AT07-06\r\n] 2006.225.07:34:40.01#ibcon#*before write, iclass 20, count 2 2006.225.07:34:40.01#ibcon#enter sib2, iclass 20, count 2 2006.225.07:34:40.01#ibcon#flushed, iclass 20, count 2 2006.225.07:34:40.01#ibcon#about to write, iclass 20, count 2 2006.225.07:34:40.01#ibcon#wrote, iclass 20, count 2 2006.225.07:34:40.01#ibcon#about to read 3, iclass 20, count 2 2006.225.07:34:40.04#ibcon#read 3, iclass 20, count 2 2006.225.07:34:40.04#ibcon#about to read 4, iclass 20, count 2 2006.225.07:34:40.04#ibcon#read 4, iclass 20, count 2 2006.225.07:34:40.04#ibcon#about to read 5, iclass 20, count 2 2006.225.07:34:40.04#ibcon#read 5, iclass 20, count 2 2006.225.07:34:40.04#ibcon#about to read 6, iclass 20, count 2 2006.225.07:34:40.04#ibcon#read 6, iclass 20, count 2 2006.225.07:34:40.04#ibcon#end of sib2, iclass 20, count 2 2006.225.07:34:40.04#ibcon#*after write, iclass 20, count 2 2006.225.07:34:40.04#ibcon#*before return 0, iclass 20, count 2 2006.225.07:34:40.04#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:34:40.04#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:34:40.04#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.07:34:40.04#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:40.04#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:34:40.16#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:34:40.16#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:34:40.16#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:34:40.16#ibcon#first serial, iclass 20, count 0 2006.225.07:34:40.16#ibcon#enter sib2, iclass 20, count 0 2006.225.07:34:40.16#ibcon#flushed, iclass 20, count 0 2006.225.07:34:40.16#ibcon#about to write, iclass 20, count 0 2006.225.07:34:40.16#ibcon#wrote, iclass 20, count 0 2006.225.07:34:40.16#ibcon#about to read 3, iclass 20, count 0 2006.225.07:34:40.18#ibcon#read 3, iclass 20, count 0 2006.225.07:34:40.18#ibcon#about to read 4, iclass 20, count 0 2006.225.07:34:40.18#ibcon#read 4, iclass 20, count 0 2006.225.07:34:40.18#ibcon#about to read 5, iclass 20, count 0 2006.225.07:34:40.18#ibcon#read 5, iclass 20, count 0 2006.225.07:34:40.18#ibcon#about to read 6, iclass 20, count 0 2006.225.07:34:40.18#ibcon#read 6, iclass 20, count 0 2006.225.07:34:40.18#ibcon#end of sib2, iclass 20, count 0 2006.225.07:34:40.18#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:34:40.18#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:34:40.18#ibcon#[25=USB\r\n] 2006.225.07:34:40.18#ibcon#*before write, iclass 20, count 0 2006.225.07:34:40.18#ibcon#enter sib2, iclass 20, count 0 2006.225.07:34:40.18#ibcon#flushed, iclass 20, count 0 2006.225.07:34:40.18#ibcon#about to write, iclass 20, count 0 2006.225.07:34:40.18#ibcon#wrote, iclass 20, count 0 2006.225.07:34:40.18#ibcon#about to read 3, iclass 20, count 0 2006.225.07:34:40.21#ibcon#read 3, iclass 20, count 0 2006.225.07:34:40.21#ibcon#about to read 4, iclass 20, count 0 2006.225.07:34:40.21#ibcon#read 4, iclass 20, count 0 2006.225.07:34:40.21#ibcon#about to read 5, iclass 20, count 0 2006.225.07:34:40.21#ibcon#read 5, iclass 20, count 0 2006.225.07:34:40.21#ibcon#about to read 6, iclass 20, count 0 2006.225.07:34:40.21#ibcon#read 6, iclass 20, count 0 2006.225.07:34:40.21#ibcon#end of sib2, iclass 20, count 0 2006.225.07:34:40.21#ibcon#*after write, iclass 20, count 0 2006.225.07:34:40.21#ibcon#*before return 0, iclass 20, count 0 2006.225.07:34:40.21#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:34:40.21#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:34:40.21#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:34:40.21#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:34:40.21$vc4f8/valo=8,852.99 2006.225.07:34:40.21#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.07:34:40.21#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.07:34:40.21#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:40.21#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:34:40.21#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:34:40.21#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:34:40.21#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:34:40.21#ibcon#first serial, iclass 22, count 0 2006.225.07:34:40.21#ibcon#enter sib2, iclass 22, count 0 2006.225.07:34:40.21#ibcon#flushed, iclass 22, count 0 2006.225.07:34:40.21#ibcon#about to write, iclass 22, count 0 2006.225.07:34:40.21#ibcon#wrote, iclass 22, count 0 2006.225.07:34:40.21#ibcon#about to read 3, iclass 22, count 0 2006.225.07:34:40.23#ibcon#read 3, iclass 22, count 0 2006.225.07:34:40.23#ibcon#about to read 4, iclass 22, count 0 2006.225.07:34:40.23#ibcon#read 4, iclass 22, count 0 2006.225.07:34:40.23#ibcon#about to read 5, iclass 22, count 0 2006.225.07:34:40.23#ibcon#read 5, iclass 22, count 0 2006.225.07:34:40.23#ibcon#about to read 6, iclass 22, count 0 2006.225.07:34:40.23#ibcon#read 6, iclass 22, count 0 2006.225.07:34:40.23#ibcon#end of sib2, iclass 22, count 0 2006.225.07:34:40.23#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:34:40.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:34:40.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:34:40.23#ibcon#*before write, iclass 22, count 0 2006.225.07:34:40.23#ibcon#enter sib2, iclass 22, count 0 2006.225.07:34:40.23#ibcon#flushed, iclass 22, count 0 2006.225.07:34:40.23#ibcon#about to write, iclass 22, count 0 2006.225.07:34:40.23#ibcon#wrote, iclass 22, count 0 2006.225.07:34:40.23#ibcon#about to read 3, iclass 22, count 0 2006.225.07:34:40.27#ibcon#read 3, iclass 22, count 0 2006.225.07:34:40.27#ibcon#about to read 4, iclass 22, count 0 2006.225.07:34:40.27#ibcon#read 4, iclass 22, count 0 2006.225.07:34:40.27#ibcon#about to read 5, iclass 22, count 0 2006.225.07:34:40.27#ibcon#read 5, iclass 22, count 0 2006.225.07:34:40.27#ibcon#about to read 6, iclass 22, count 0 2006.225.07:34:40.27#ibcon#read 6, iclass 22, count 0 2006.225.07:34:40.27#ibcon#end of sib2, iclass 22, count 0 2006.225.07:34:40.27#ibcon#*after write, iclass 22, count 0 2006.225.07:34:40.27#ibcon#*before return 0, iclass 22, count 0 2006.225.07:34:40.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:34:40.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:34:40.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:34:40.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:34:40.27$vc4f8/va=8,7 2006.225.07:34:40.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.07:34:40.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.07:34:40.27#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:40.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:34:40.33#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:34:40.33#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:34:40.33#ibcon#enter wrdev, iclass 24, count 2 2006.225.07:34:40.33#ibcon#first serial, iclass 24, count 2 2006.225.07:34:40.33#ibcon#enter sib2, iclass 24, count 2 2006.225.07:34:40.33#ibcon#flushed, iclass 24, count 2 2006.225.07:34:40.33#ibcon#about to write, iclass 24, count 2 2006.225.07:34:40.33#ibcon#wrote, iclass 24, count 2 2006.225.07:34:40.33#ibcon#about to read 3, iclass 24, count 2 2006.225.07:34:40.35#ibcon#read 3, iclass 24, count 2 2006.225.07:34:40.35#ibcon#about to read 4, iclass 24, count 2 2006.225.07:34:40.35#ibcon#read 4, iclass 24, count 2 2006.225.07:34:40.35#ibcon#about to read 5, iclass 24, count 2 2006.225.07:34:40.35#ibcon#read 5, iclass 24, count 2 2006.225.07:34:40.35#ibcon#about to read 6, iclass 24, count 2 2006.225.07:34:40.35#ibcon#read 6, iclass 24, count 2 2006.225.07:34:40.35#ibcon#end of sib2, iclass 24, count 2 2006.225.07:34:40.35#ibcon#*mode == 0, iclass 24, count 2 2006.225.07:34:40.35#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.07:34:40.35#ibcon#[25=AT08-07\r\n] 2006.225.07:34:40.35#ibcon#*before write, iclass 24, count 2 2006.225.07:34:40.35#ibcon#enter sib2, iclass 24, count 2 2006.225.07:34:40.35#ibcon#flushed, iclass 24, count 2 2006.225.07:34:40.35#ibcon#about to write, iclass 24, count 2 2006.225.07:34:40.35#ibcon#wrote, iclass 24, count 2 2006.225.07:34:40.35#ibcon#about to read 3, iclass 24, count 2 2006.225.07:34:40.38#ibcon#read 3, iclass 24, count 2 2006.225.07:34:40.38#ibcon#about to read 4, iclass 24, count 2 2006.225.07:34:40.38#ibcon#read 4, iclass 24, count 2 2006.225.07:34:40.38#ibcon#about to read 5, iclass 24, count 2 2006.225.07:34:40.38#ibcon#read 5, iclass 24, count 2 2006.225.07:34:40.38#ibcon#about to read 6, iclass 24, count 2 2006.225.07:34:40.38#ibcon#read 6, iclass 24, count 2 2006.225.07:34:40.38#ibcon#end of sib2, iclass 24, count 2 2006.225.07:34:40.38#ibcon#*after write, iclass 24, count 2 2006.225.07:34:40.38#ibcon#*before return 0, iclass 24, count 2 2006.225.07:34:40.38#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:34:40.38#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:34:40.38#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.07:34:40.38#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:40.38#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:34:40.50#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:34:40.50#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:34:40.50#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:34:40.50#ibcon#first serial, iclass 24, count 0 2006.225.07:34:40.50#ibcon#enter sib2, iclass 24, count 0 2006.225.07:34:40.50#ibcon#flushed, iclass 24, count 0 2006.225.07:34:40.50#ibcon#about to write, iclass 24, count 0 2006.225.07:34:40.50#ibcon#wrote, iclass 24, count 0 2006.225.07:34:40.50#ibcon#about to read 3, iclass 24, count 0 2006.225.07:34:40.52#ibcon#read 3, iclass 24, count 0 2006.225.07:34:40.52#ibcon#about to read 4, iclass 24, count 0 2006.225.07:34:40.52#ibcon#read 4, iclass 24, count 0 2006.225.07:34:40.52#ibcon#about to read 5, iclass 24, count 0 2006.225.07:34:40.52#ibcon#read 5, iclass 24, count 0 2006.225.07:34:40.52#ibcon#about to read 6, iclass 24, count 0 2006.225.07:34:40.52#ibcon#read 6, iclass 24, count 0 2006.225.07:34:40.52#ibcon#end of sib2, iclass 24, count 0 2006.225.07:34:40.52#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:34:40.52#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:34:40.52#ibcon#[25=USB\r\n] 2006.225.07:34:40.52#ibcon#*before write, iclass 24, count 0 2006.225.07:34:40.52#ibcon#enter sib2, iclass 24, count 0 2006.225.07:34:40.52#ibcon#flushed, iclass 24, count 0 2006.225.07:34:40.52#ibcon#about to write, iclass 24, count 0 2006.225.07:34:40.52#ibcon#wrote, iclass 24, count 0 2006.225.07:34:40.52#ibcon#about to read 3, iclass 24, count 0 2006.225.07:34:40.55#ibcon#read 3, iclass 24, count 0 2006.225.07:34:40.55#ibcon#about to read 4, iclass 24, count 0 2006.225.07:34:40.55#ibcon#read 4, iclass 24, count 0 2006.225.07:34:40.55#ibcon#about to read 5, iclass 24, count 0 2006.225.07:34:40.55#ibcon#read 5, iclass 24, count 0 2006.225.07:34:40.55#ibcon#about to read 6, iclass 24, count 0 2006.225.07:34:40.55#ibcon#read 6, iclass 24, count 0 2006.225.07:34:40.55#ibcon#end of sib2, iclass 24, count 0 2006.225.07:34:40.55#ibcon#*after write, iclass 24, count 0 2006.225.07:34:40.55#ibcon#*before return 0, iclass 24, count 0 2006.225.07:34:40.55#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:34:40.55#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:34:40.55#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:34:40.55#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:34:40.55$vc4f8/vblo=1,632.99 2006.225.07:34:40.55#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.07:34:40.55#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.07:34:40.55#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:40.55#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:34:40.55#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:34:40.55#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:34:40.55#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:34:40.55#ibcon#first serial, iclass 26, count 0 2006.225.07:34:40.55#ibcon#enter sib2, iclass 26, count 0 2006.225.07:34:40.55#ibcon#flushed, iclass 26, count 0 2006.225.07:34:40.55#ibcon#about to write, iclass 26, count 0 2006.225.07:34:40.55#ibcon#wrote, iclass 26, count 0 2006.225.07:34:40.55#ibcon#about to read 3, iclass 26, count 0 2006.225.07:34:40.57#ibcon#read 3, iclass 26, count 0 2006.225.07:34:40.57#ibcon#about to read 4, iclass 26, count 0 2006.225.07:34:40.57#ibcon#read 4, iclass 26, count 0 2006.225.07:34:40.57#ibcon#about to read 5, iclass 26, count 0 2006.225.07:34:40.57#ibcon#read 5, iclass 26, count 0 2006.225.07:34:40.57#ibcon#about to read 6, iclass 26, count 0 2006.225.07:34:40.57#ibcon#read 6, iclass 26, count 0 2006.225.07:34:40.57#ibcon#end of sib2, iclass 26, count 0 2006.225.07:34:40.57#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:34:40.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:34:40.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:34:40.57#ibcon#*before write, iclass 26, count 0 2006.225.07:34:40.57#ibcon#enter sib2, iclass 26, count 0 2006.225.07:34:40.57#ibcon#flushed, iclass 26, count 0 2006.225.07:34:40.57#ibcon#about to write, iclass 26, count 0 2006.225.07:34:40.57#ibcon#wrote, iclass 26, count 0 2006.225.07:34:40.57#ibcon#about to read 3, iclass 26, count 0 2006.225.07:34:40.61#ibcon#read 3, iclass 26, count 0 2006.225.07:34:40.61#ibcon#about to read 4, iclass 26, count 0 2006.225.07:34:40.61#ibcon#read 4, iclass 26, count 0 2006.225.07:34:40.61#ibcon#about to read 5, iclass 26, count 0 2006.225.07:34:40.61#ibcon#read 5, iclass 26, count 0 2006.225.07:34:40.61#ibcon#about to read 6, iclass 26, count 0 2006.225.07:34:40.61#ibcon#read 6, iclass 26, count 0 2006.225.07:34:40.61#ibcon#end of sib2, iclass 26, count 0 2006.225.07:34:40.61#ibcon#*after write, iclass 26, count 0 2006.225.07:34:40.61#ibcon#*before return 0, iclass 26, count 0 2006.225.07:34:40.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:34:40.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:34:40.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:34:40.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:34:40.61$vc4f8/vb=1,4 2006.225.07:34:40.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.07:34:40.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.07:34:40.61#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:40.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:34:40.61#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:34:40.61#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:34:40.61#ibcon#enter wrdev, iclass 28, count 2 2006.225.07:34:40.61#ibcon#first serial, iclass 28, count 2 2006.225.07:34:40.61#ibcon#enter sib2, iclass 28, count 2 2006.225.07:34:40.61#ibcon#flushed, iclass 28, count 2 2006.225.07:34:40.61#ibcon#about to write, iclass 28, count 2 2006.225.07:34:40.61#ibcon#wrote, iclass 28, count 2 2006.225.07:34:40.61#ibcon#about to read 3, iclass 28, count 2 2006.225.07:34:40.63#ibcon#read 3, iclass 28, count 2 2006.225.07:34:40.63#ibcon#about to read 4, iclass 28, count 2 2006.225.07:34:40.63#ibcon#read 4, iclass 28, count 2 2006.225.07:34:40.63#ibcon#about to read 5, iclass 28, count 2 2006.225.07:34:40.63#ibcon#read 5, iclass 28, count 2 2006.225.07:34:40.63#ibcon#about to read 6, iclass 28, count 2 2006.225.07:34:40.63#ibcon#read 6, iclass 28, count 2 2006.225.07:34:40.63#ibcon#end of sib2, iclass 28, count 2 2006.225.07:34:40.63#ibcon#*mode == 0, iclass 28, count 2 2006.225.07:34:40.63#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.07:34:40.63#ibcon#[27=AT01-04\r\n] 2006.225.07:34:40.63#ibcon#*before write, iclass 28, count 2 2006.225.07:34:40.63#ibcon#enter sib2, iclass 28, count 2 2006.225.07:34:40.63#ibcon#flushed, iclass 28, count 2 2006.225.07:34:40.63#ibcon#about to write, iclass 28, count 2 2006.225.07:34:40.63#ibcon#wrote, iclass 28, count 2 2006.225.07:34:40.63#ibcon#about to read 3, iclass 28, count 2 2006.225.07:34:40.66#ibcon#read 3, iclass 28, count 2 2006.225.07:34:40.66#ibcon#about to read 4, iclass 28, count 2 2006.225.07:34:40.66#ibcon#read 4, iclass 28, count 2 2006.225.07:34:40.66#ibcon#about to read 5, iclass 28, count 2 2006.225.07:34:40.66#ibcon#read 5, iclass 28, count 2 2006.225.07:34:40.66#ibcon#about to read 6, iclass 28, count 2 2006.225.07:34:40.66#ibcon#read 6, iclass 28, count 2 2006.225.07:34:40.66#ibcon#end of sib2, iclass 28, count 2 2006.225.07:34:40.66#ibcon#*after write, iclass 28, count 2 2006.225.07:34:40.66#ibcon#*before return 0, iclass 28, count 2 2006.225.07:34:40.66#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:34:40.66#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:34:40.66#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.07:34:40.66#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:40.66#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:34:40.78#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:34:40.78#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:34:40.78#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:34:40.78#ibcon#first serial, iclass 28, count 0 2006.225.07:34:40.78#ibcon#enter sib2, iclass 28, count 0 2006.225.07:34:40.78#ibcon#flushed, iclass 28, count 0 2006.225.07:34:40.78#ibcon#about to write, iclass 28, count 0 2006.225.07:34:40.78#ibcon#wrote, iclass 28, count 0 2006.225.07:34:40.78#ibcon#about to read 3, iclass 28, count 0 2006.225.07:34:40.80#ibcon#read 3, iclass 28, count 0 2006.225.07:34:40.80#ibcon#about to read 4, iclass 28, count 0 2006.225.07:34:40.80#ibcon#read 4, iclass 28, count 0 2006.225.07:34:40.80#ibcon#about to read 5, iclass 28, count 0 2006.225.07:34:40.80#ibcon#read 5, iclass 28, count 0 2006.225.07:34:40.80#ibcon#about to read 6, iclass 28, count 0 2006.225.07:34:40.80#ibcon#read 6, iclass 28, count 0 2006.225.07:34:40.80#ibcon#end of sib2, iclass 28, count 0 2006.225.07:34:40.80#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:34:40.80#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:34:40.80#ibcon#[27=USB\r\n] 2006.225.07:34:40.80#ibcon#*before write, iclass 28, count 0 2006.225.07:34:40.80#ibcon#enter sib2, iclass 28, count 0 2006.225.07:34:40.80#ibcon#flushed, iclass 28, count 0 2006.225.07:34:40.80#ibcon#about to write, iclass 28, count 0 2006.225.07:34:40.80#ibcon#wrote, iclass 28, count 0 2006.225.07:34:40.80#ibcon#about to read 3, iclass 28, count 0 2006.225.07:34:40.83#ibcon#read 3, iclass 28, count 0 2006.225.07:34:40.83#ibcon#about to read 4, iclass 28, count 0 2006.225.07:34:40.83#ibcon#read 4, iclass 28, count 0 2006.225.07:34:40.83#ibcon#about to read 5, iclass 28, count 0 2006.225.07:34:40.83#ibcon#read 5, iclass 28, count 0 2006.225.07:34:40.83#ibcon#about to read 6, iclass 28, count 0 2006.225.07:34:40.83#ibcon#read 6, iclass 28, count 0 2006.225.07:34:40.83#ibcon#end of sib2, iclass 28, count 0 2006.225.07:34:40.83#ibcon#*after write, iclass 28, count 0 2006.225.07:34:40.83#ibcon#*before return 0, iclass 28, count 0 2006.225.07:34:40.83#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:34:40.83#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:34:40.83#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:34:40.83#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:34:40.83$vc4f8/vblo=2,640.99 2006.225.07:34:40.83#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.07:34:40.83#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.07:34:40.83#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:40.83#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:34:40.83#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:34:40.83#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:34:40.83#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:34:40.83#ibcon#first serial, iclass 30, count 0 2006.225.07:34:40.83#ibcon#enter sib2, iclass 30, count 0 2006.225.07:34:40.83#ibcon#flushed, iclass 30, count 0 2006.225.07:34:40.83#ibcon#about to write, iclass 30, count 0 2006.225.07:34:40.83#ibcon#wrote, iclass 30, count 0 2006.225.07:34:40.83#ibcon#about to read 3, iclass 30, count 0 2006.225.07:34:40.85#ibcon#read 3, iclass 30, count 0 2006.225.07:34:40.85#ibcon#about to read 4, iclass 30, count 0 2006.225.07:34:40.85#ibcon#read 4, iclass 30, count 0 2006.225.07:34:40.85#ibcon#about to read 5, iclass 30, count 0 2006.225.07:34:40.85#ibcon#read 5, iclass 30, count 0 2006.225.07:34:40.85#ibcon#about to read 6, iclass 30, count 0 2006.225.07:34:40.85#ibcon#read 6, iclass 30, count 0 2006.225.07:34:40.85#ibcon#end of sib2, iclass 30, count 0 2006.225.07:34:40.85#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:34:40.85#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:34:40.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:34:40.85#ibcon#*before write, iclass 30, count 0 2006.225.07:34:40.85#ibcon#enter sib2, iclass 30, count 0 2006.225.07:34:40.85#ibcon#flushed, iclass 30, count 0 2006.225.07:34:40.85#ibcon#about to write, iclass 30, count 0 2006.225.07:34:40.85#ibcon#wrote, iclass 30, count 0 2006.225.07:34:40.85#ibcon#about to read 3, iclass 30, count 0 2006.225.07:34:40.89#ibcon#read 3, iclass 30, count 0 2006.225.07:34:40.89#ibcon#about to read 4, iclass 30, count 0 2006.225.07:34:40.89#ibcon#read 4, iclass 30, count 0 2006.225.07:34:40.89#ibcon#about to read 5, iclass 30, count 0 2006.225.07:34:40.89#ibcon#read 5, iclass 30, count 0 2006.225.07:34:40.89#ibcon#about to read 6, iclass 30, count 0 2006.225.07:34:40.89#ibcon#read 6, iclass 30, count 0 2006.225.07:34:40.89#ibcon#end of sib2, iclass 30, count 0 2006.225.07:34:40.89#ibcon#*after write, iclass 30, count 0 2006.225.07:34:40.89#ibcon#*before return 0, iclass 30, count 0 2006.225.07:34:40.89#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:34:40.89#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:34:40.89#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:34:40.89#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:34:40.89$vc4f8/vb=2,4 2006.225.07:34:40.89#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.225.07:34:40.89#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.225.07:34:40.89#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:40.89#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:34:40.95#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:34:40.95#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:34:40.95#ibcon#enter wrdev, iclass 32, count 2 2006.225.07:34:40.95#ibcon#first serial, iclass 32, count 2 2006.225.07:34:40.95#ibcon#enter sib2, iclass 32, count 2 2006.225.07:34:40.95#ibcon#flushed, iclass 32, count 2 2006.225.07:34:40.95#ibcon#about to write, iclass 32, count 2 2006.225.07:34:40.95#ibcon#wrote, iclass 32, count 2 2006.225.07:34:40.95#ibcon#about to read 3, iclass 32, count 2 2006.225.07:34:40.97#ibcon#read 3, iclass 32, count 2 2006.225.07:34:40.97#ibcon#about to read 4, iclass 32, count 2 2006.225.07:34:40.97#ibcon#read 4, iclass 32, count 2 2006.225.07:34:40.97#ibcon#about to read 5, iclass 32, count 2 2006.225.07:34:40.97#ibcon#read 5, iclass 32, count 2 2006.225.07:34:40.97#ibcon#about to read 6, iclass 32, count 2 2006.225.07:34:40.97#ibcon#read 6, iclass 32, count 2 2006.225.07:34:40.97#ibcon#end of sib2, iclass 32, count 2 2006.225.07:34:40.97#ibcon#*mode == 0, iclass 32, count 2 2006.225.07:34:40.97#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.225.07:34:40.97#ibcon#[27=AT02-04\r\n] 2006.225.07:34:40.97#ibcon#*before write, iclass 32, count 2 2006.225.07:34:40.97#ibcon#enter sib2, iclass 32, count 2 2006.225.07:34:40.97#ibcon#flushed, iclass 32, count 2 2006.225.07:34:40.97#ibcon#about to write, iclass 32, count 2 2006.225.07:34:40.97#ibcon#wrote, iclass 32, count 2 2006.225.07:34:40.97#ibcon#about to read 3, iclass 32, count 2 2006.225.07:34:41.00#ibcon#read 3, iclass 32, count 2 2006.225.07:34:41.00#ibcon#about to read 4, iclass 32, count 2 2006.225.07:34:41.00#ibcon#read 4, iclass 32, count 2 2006.225.07:34:41.00#ibcon#about to read 5, iclass 32, count 2 2006.225.07:34:41.00#ibcon#read 5, iclass 32, count 2 2006.225.07:34:41.00#ibcon#about to read 6, iclass 32, count 2 2006.225.07:34:41.00#ibcon#read 6, iclass 32, count 2 2006.225.07:34:41.00#ibcon#end of sib2, iclass 32, count 2 2006.225.07:34:41.00#ibcon#*after write, iclass 32, count 2 2006.225.07:34:41.00#ibcon#*before return 0, iclass 32, count 2 2006.225.07:34:41.00#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:34:41.00#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:34:41.00#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.225.07:34:41.00#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:41.00#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:34:41.12#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:34:41.12#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:34:41.12#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:34:41.12#ibcon#first serial, iclass 32, count 0 2006.225.07:34:41.12#ibcon#enter sib2, iclass 32, count 0 2006.225.07:34:41.12#ibcon#flushed, iclass 32, count 0 2006.225.07:34:41.12#ibcon#about to write, iclass 32, count 0 2006.225.07:34:41.12#ibcon#wrote, iclass 32, count 0 2006.225.07:34:41.12#ibcon#about to read 3, iclass 32, count 0 2006.225.07:34:41.14#ibcon#read 3, iclass 32, count 0 2006.225.07:34:41.14#ibcon#about to read 4, iclass 32, count 0 2006.225.07:34:41.14#ibcon#read 4, iclass 32, count 0 2006.225.07:34:41.14#ibcon#about to read 5, iclass 32, count 0 2006.225.07:34:41.14#ibcon#read 5, iclass 32, count 0 2006.225.07:34:41.14#ibcon#about to read 6, iclass 32, count 0 2006.225.07:34:41.14#ibcon#read 6, iclass 32, count 0 2006.225.07:34:41.14#ibcon#end of sib2, iclass 32, count 0 2006.225.07:34:41.14#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:34:41.14#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:34:41.14#ibcon#[27=USB\r\n] 2006.225.07:34:41.14#ibcon#*before write, iclass 32, count 0 2006.225.07:34:41.14#ibcon#enter sib2, iclass 32, count 0 2006.225.07:34:41.14#ibcon#flushed, iclass 32, count 0 2006.225.07:34:41.14#ibcon#about to write, iclass 32, count 0 2006.225.07:34:41.14#ibcon#wrote, iclass 32, count 0 2006.225.07:34:41.14#ibcon#about to read 3, iclass 32, count 0 2006.225.07:34:41.17#ibcon#read 3, iclass 32, count 0 2006.225.07:34:41.17#ibcon#about to read 4, iclass 32, count 0 2006.225.07:34:41.17#ibcon#read 4, iclass 32, count 0 2006.225.07:34:41.17#ibcon#about to read 5, iclass 32, count 0 2006.225.07:34:41.17#ibcon#read 5, iclass 32, count 0 2006.225.07:34:41.17#ibcon#about to read 6, iclass 32, count 0 2006.225.07:34:41.17#ibcon#read 6, iclass 32, count 0 2006.225.07:34:41.17#ibcon#end of sib2, iclass 32, count 0 2006.225.07:34:41.17#ibcon#*after write, iclass 32, count 0 2006.225.07:34:41.17#ibcon#*before return 0, iclass 32, count 0 2006.225.07:34:41.17#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:34:41.17#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:34:41.17#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:34:41.17#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:34:41.17$vc4f8/vblo=3,656.99 2006.225.07:34:41.17#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.07:34:41.17#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.07:34:41.17#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:41.17#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:34:41.17#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:34:41.17#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:34:41.17#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:34:41.17#ibcon#first serial, iclass 34, count 0 2006.225.07:34:41.17#ibcon#enter sib2, iclass 34, count 0 2006.225.07:34:41.17#ibcon#flushed, iclass 34, count 0 2006.225.07:34:41.17#ibcon#about to write, iclass 34, count 0 2006.225.07:34:41.17#ibcon#wrote, iclass 34, count 0 2006.225.07:34:41.17#ibcon#about to read 3, iclass 34, count 0 2006.225.07:34:41.20#ibcon#read 3, iclass 34, count 0 2006.225.07:34:41.20#ibcon#about to read 4, iclass 34, count 0 2006.225.07:34:41.20#ibcon#read 4, iclass 34, count 0 2006.225.07:34:41.20#ibcon#about to read 5, iclass 34, count 0 2006.225.07:34:41.20#ibcon#read 5, iclass 34, count 0 2006.225.07:34:41.20#ibcon#about to read 6, iclass 34, count 0 2006.225.07:34:41.20#ibcon#read 6, iclass 34, count 0 2006.225.07:34:41.20#ibcon#end of sib2, iclass 34, count 0 2006.225.07:34:41.20#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:34:41.20#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:34:41.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:34:41.20#ibcon#*before write, iclass 34, count 0 2006.225.07:34:41.20#ibcon#enter sib2, iclass 34, count 0 2006.225.07:34:41.20#ibcon#flushed, iclass 34, count 0 2006.225.07:34:41.20#ibcon#about to write, iclass 34, count 0 2006.225.07:34:41.20#ibcon#wrote, iclass 34, count 0 2006.225.07:34:41.20#ibcon#about to read 3, iclass 34, count 0 2006.225.07:34:41.24#ibcon#read 3, iclass 34, count 0 2006.225.07:34:41.24#ibcon#about to read 4, iclass 34, count 0 2006.225.07:34:41.24#ibcon#read 4, iclass 34, count 0 2006.225.07:34:41.24#ibcon#about to read 5, iclass 34, count 0 2006.225.07:34:41.24#ibcon#read 5, iclass 34, count 0 2006.225.07:34:41.24#ibcon#about to read 6, iclass 34, count 0 2006.225.07:34:41.24#ibcon#read 6, iclass 34, count 0 2006.225.07:34:41.24#ibcon#end of sib2, iclass 34, count 0 2006.225.07:34:41.24#ibcon#*after write, iclass 34, count 0 2006.225.07:34:41.24#ibcon#*before return 0, iclass 34, count 0 2006.225.07:34:41.24#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:34:41.24#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:34:41.24#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:34:41.24#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:34:41.24$vc4f8/vb=3,4 2006.225.07:34:41.24#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.07:34:41.24#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.07:34:41.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:41.24#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:34:41.29#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:34:41.29#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:34:41.29#ibcon#enter wrdev, iclass 36, count 2 2006.225.07:34:41.29#ibcon#first serial, iclass 36, count 2 2006.225.07:34:41.29#ibcon#enter sib2, iclass 36, count 2 2006.225.07:34:41.29#ibcon#flushed, iclass 36, count 2 2006.225.07:34:41.29#ibcon#about to write, iclass 36, count 2 2006.225.07:34:41.29#ibcon#wrote, iclass 36, count 2 2006.225.07:34:41.29#ibcon#about to read 3, iclass 36, count 2 2006.225.07:34:41.31#ibcon#read 3, iclass 36, count 2 2006.225.07:34:41.31#ibcon#about to read 4, iclass 36, count 2 2006.225.07:34:41.31#ibcon#read 4, iclass 36, count 2 2006.225.07:34:41.31#ibcon#about to read 5, iclass 36, count 2 2006.225.07:34:41.31#ibcon#read 5, iclass 36, count 2 2006.225.07:34:41.31#ibcon#about to read 6, iclass 36, count 2 2006.225.07:34:41.31#ibcon#read 6, iclass 36, count 2 2006.225.07:34:41.31#ibcon#end of sib2, iclass 36, count 2 2006.225.07:34:41.31#ibcon#*mode == 0, iclass 36, count 2 2006.225.07:34:41.31#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.07:34:41.31#ibcon#[27=AT03-04\r\n] 2006.225.07:34:41.31#ibcon#*before write, iclass 36, count 2 2006.225.07:34:41.31#ibcon#enter sib2, iclass 36, count 2 2006.225.07:34:41.31#ibcon#flushed, iclass 36, count 2 2006.225.07:34:41.31#ibcon#about to write, iclass 36, count 2 2006.225.07:34:41.31#ibcon#wrote, iclass 36, count 2 2006.225.07:34:41.31#ibcon#about to read 3, iclass 36, count 2 2006.225.07:34:41.34#ibcon#read 3, iclass 36, count 2 2006.225.07:34:41.34#ibcon#about to read 4, iclass 36, count 2 2006.225.07:34:41.34#ibcon#read 4, iclass 36, count 2 2006.225.07:34:41.34#ibcon#about to read 5, iclass 36, count 2 2006.225.07:34:41.34#ibcon#read 5, iclass 36, count 2 2006.225.07:34:41.34#ibcon#about to read 6, iclass 36, count 2 2006.225.07:34:41.34#ibcon#read 6, iclass 36, count 2 2006.225.07:34:41.34#ibcon#end of sib2, iclass 36, count 2 2006.225.07:34:41.34#ibcon#*after write, iclass 36, count 2 2006.225.07:34:41.34#ibcon#*before return 0, iclass 36, count 2 2006.225.07:34:41.34#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:34:41.34#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:34:41.34#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.07:34:41.34#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:41.34#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:34:41.46#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:34:41.46#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:34:41.46#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:34:41.46#ibcon#first serial, iclass 36, count 0 2006.225.07:34:41.46#ibcon#enter sib2, iclass 36, count 0 2006.225.07:34:41.46#ibcon#flushed, iclass 36, count 0 2006.225.07:34:41.46#ibcon#about to write, iclass 36, count 0 2006.225.07:34:41.46#ibcon#wrote, iclass 36, count 0 2006.225.07:34:41.46#ibcon#about to read 3, iclass 36, count 0 2006.225.07:34:41.48#ibcon#read 3, iclass 36, count 0 2006.225.07:34:41.48#ibcon#about to read 4, iclass 36, count 0 2006.225.07:34:41.48#ibcon#read 4, iclass 36, count 0 2006.225.07:34:41.48#ibcon#about to read 5, iclass 36, count 0 2006.225.07:34:41.48#ibcon#read 5, iclass 36, count 0 2006.225.07:34:41.48#ibcon#about to read 6, iclass 36, count 0 2006.225.07:34:41.48#ibcon#read 6, iclass 36, count 0 2006.225.07:34:41.48#ibcon#end of sib2, iclass 36, count 0 2006.225.07:34:41.48#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:34:41.48#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:34:41.48#ibcon#[27=USB\r\n] 2006.225.07:34:41.48#ibcon#*before write, iclass 36, count 0 2006.225.07:34:41.48#ibcon#enter sib2, iclass 36, count 0 2006.225.07:34:41.48#ibcon#flushed, iclass 36, count 0 2006.225.07:34:41.48#ibcon#about to write, iclass 36, count 0 2006.225.07:34:41.48#ibcon#wrote, iclass 36, count 0 2006.225.07:34:41.48#ibcon#about to read 3, iclass 36, count 0 2006.225.07:34:41.51#ibcon#read 3, iclass 36, count 0 2006.225.07:34:41.51#ibcon#about to read 4, iclass 36, count 0 2006.225.07:34:41.51#ibcon#read 4, iclass 36, count 0 2006.225.07:34:41.51#ibcon#about to read 5, iclass 36, count 0 2006.225.07:34:41.51#ibcon#read 5, iclass 36, count 0 2006.225.07:34:41.51#ibcon#about to read 6, iclass 36, count 0 2006.225.07:34:41.51#ibcon#read 6, iclass 36, count 0 2006.225.07:34:41.51#ibcon#end of sib2, iclass 36, count 0 2006.225.07:34:41.51#ibcon#*after write, iclass 36, count 0 2006.225.07:34:41.51#ibcon#*before return 0, iclass 36, count 0 2006.225.07:34:41.51#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:34:41.51#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:34:41.51#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:34:41.51#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:34:41.51$vc4f8/vblo=4,712.99 2006.225.07:34:41.51#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.07:34:41.51#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.07:34:41.51#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:41.51#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:34:41.51#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:34:41.51#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:34:41.51#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:34:41.51#ibcon#first serial, iclass 38, count 0 2006.225.07:34:41.51#ibcon#enter sib2, iclass 38, count 0 2006.225.07:34:41.51#ibcon#flushed, iclass 38, count 0 2006.225.07:34:41.51#ibcon#about to write, iclass 38, count 0 2006.225.07:34:41.51#ibcon#wrote, iclass 38, count 0 2006.225.07:34:41.51#ibcon#about to read 3, iclass 38, count 0 2006.225.07:34:41.53#ibcon#read 3, iclass 38, count 0 2006.225.07:34:41.53#ibcon#about to read 4, iclass 38, count 0 2006.225.07:34:41.53#ibcon#read 4, iclass 38, count 0 2006.225.07:34:41.53#ibcon#about to read 5, iclass 38, count 0 2006.225.07:34:41.53#ibcon#read 5, iclass 38, count 0 2006.225.07:34:41.53#ibcon#about to read 6, iclass 38, count 0 2006.225.07:34:41.53#ibcon#read 6, iclass 38, count 0 2006.225.07:34:41.53#ibcon#end of sib2, iclass 38, count 0 2006.225.07:34:41.53#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:34:41.53#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:34:41.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:34:41.53#ibcon#*before write, iclass 38, count 0 2006.225.07:34:41.53#ibcon#enter sib2, iclass 38, count 0 2006.225.07:34:41.53#ibcon#flushed, iclass 38, count 0 2006.225.07:34:41.53#ibcon#about to write, iclass 38, count 0 2006.225.07:34:41.53#ibcon#wrote, iclass 38, count 0 2006.225.07:34:41.53#ibcon#about to read 3, iclass 38, count 0 2006.225.07:34:41.57#ibcon#read 3, iclass 38, count 0 2006.225.07:34:41.57#ibcon#about to read 4, iclass 38, count 0 2006.225.07:34:41.57#ibcon#read 4, iclass 38, count 0 2006.225.07:34:41.57#ibcon#about to read 5, iclass 38, count 0 2006.225.07:34:41.57#ibcon#read 5, iclass 38, count 0 2006.225.07:34:41.57#ibcon#about to read 6, iclass 38, count 0 2006.225.07:34:41.57#ibcon#read 6, iclass 38, count 0 2006.225.07:34:41.57#ibcon#end of sib2, iclass 38, count 0 2006.225.07:34:41.57#ibcon#*after write, iclass 38, count 0 2006.225.07:34:41.57#ibcon#*before return 0, iclass 38, count 0 2006.225.07:34:41.57#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:34:41.57#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:34:41.57#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:34:41.57#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:34:41.57$vc4f8/vb=4,4 2006.225.07:34:41.57#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.225.07:34:41.57#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.225.07:34:41.57#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:41.57#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:34:41.63#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:34:41.63#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:34:41.63#ibcon#enter wrdev, iclass 40, count 2 2006.225.07:34:41.63#ibcon#first serial, iclass 40, count 2 2006.225.07:34:41.63#ibcon#enter sib2, iclass 40, count 2 2006.225.07:34:41.63#ibcon#flushed, iclass 40, count 2 2006.225.07:34:41.63#ibcon#about to write, iclass 40, count 2 2006.225.07:34:41.63#ibcon#wrote, iclass 40, count 2 2006.225.07:34:41.63#ibcon#about to read 3, iclass 40, count 2 2006.225.07:34:41.65#ibcon#read 3, iclass 40, count 2 2006.225.07:34:41.65#ibcon#about to read 4, iclass 40, count 2 2006.225.07:34:41.65#ibcon#read 4, iclass 40, count 2 2006.225.07:34:41.65#ibcon#about to read 5, iclass 40, count 2 2006.225.07:34:41.65#ibcon#read 5, iclass 40, count 2 2006.225.07:34:41.65#ibcon#about to read 6, iclass 40, count 2 2006.225.07:34:41.65#ibcon#read 6, iclass 40, count 2 2006.225.07:34:41.65#ibcon#end of sib2, iclass 40, count 2 2006.225.07:34:41.65#ibcon#*mode == 0, iclass 40, count 2 2006.225.07:34:41.65#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.225.07:34:41.65#ibcon#[27=AT04-04\r\n] 2006.225.07:34:41.65#ibcon#*before write, iclass 40, count 2 2006.225.07:34:41.65#ibcon#enter sib2, iclass 40, count 2 2006.225.07:34:41.65#ibcon#flushed, iclass 40, count 2 2006.225.07:34:41.65#ibcon#about to write, iclass 40, count 2 2006.225.07:34:41.65#ibcon#wrote, iclass 40, count 2 2006.225.07:34:41.65#ibcon#about to read 3, iclass 40, count 2 2006.225.07:34:41.68#ibcon#read 3, iclass 40, count 2 2006.225.07:34:41.68#ibcon#about to read 4, iclass 40, count 2 2006.225.07:34:41.68#ibcon#read 4, iclass 40, count 2 2006.225.07:34:41.68#ibcon#about to read 5, iclass 40, count 2 2006.225.07:34:41.68#ibcon#read 5, iclass 40, count 2 2006.225.07:34:41.68#ibcon#about to read 6, iclass 40, count 2 2006.225.07:34:41.68#ibcon#read 6, iclass 40, count 2 2006.225.07:34:41.68#ibcon#end of sib2, iclass 40, count 2 2006.225.07:34:41.68#ibcon#*after write, iclass 40, count 2 2006.225.07:34:41.68#ibcon#*before return 0, iclass 40, count 2 2006.225.07:34:41.68#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:34:41.68#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:34:41.68#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.225.07:34:41.68#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:41.68#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:34:41.80#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:34:41.80#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:34:41.80#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:34:41.80#ibcon#first serial, iclass 40, count 0 2006.225.07:34:41.80#ibcon#enter sib2, iclass 40, count 0 2006.225.07:34:41.80#ibcon#flushed, iclass 40, count 0 2006.225.07:34:41.80#ibcon#about to write, iclass 40, count 0 2006.225.07:34:41.80#ibcon#wrote, iclass 40, count 0 2006.225.07:34:41.80#ibcon#about to read 3, iclass 40, count 0 2006.225.07:34:41.82#ibcon#read 3, iclass 40, count 0 2006.225.07:34:41.82#ibcon#about to read 4, iclass 40, count 0 2006.225.07:34:41.82#ibcon#read 4, iclass 40, count 0 2006.225.07:34:41.82#ibcon#about to read 5, iclass 40, count 0 2006.225.07:34:41.82#ibcon#read 5, iclass 40, count 0 2006.225.07:34:41.82#ibcon#about to read 6, iclass 40, count 0 2006.225.07:34:41.82#ibcon#read 6, iclass 40, count 0 2006.225.07:34:41.82#ibcon#end of sib2, iclass 40, count 0 2006.225.07:34:41.82#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:34:41.82#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:34:41.82#ibcon#[27=USB\r\n] 2006.225.07:34:41.82#ibcon#*before write, iclass 40, count 0 2006.225.07:34:41.82#ibcon#enter sib2, iclass 40, count 0 2006.225.07:34:41.82#ibcon#flushed, iclass 40, count 0 2006.225.07:34:41.82#ibcon#about to write, iclass 40, count 0 2006.225.07:34:41.82#ibcon#wrote, iclass 40, count 0 2006.225.07:34:41.82#ibcon#about to read 3, iclass 40, count 0 2006.225.07:34:41.85#ibcon#read 3, iclass 40, count 0 2006.225.07:34:41.85#ibcon#about to read 4, iclass 40, count 0 2006.225.07:34:41.85#ibcon#read 4, iclass 40, count 0 2006.225.07:34:41.85#ibcon#about to read 5, iclass 40, count 0 2006.225.07:34:41.85#ibcon#read 5, iclass 40, count 0 2006.225.07:34:41.85#ibcon#about to read 6, iclass 40, count 0 2006.225.07:34:41.85#ibcon#read 6, iclass 40, count 0 2006.225.07:34:41.85#ibcon#end of sib2, iclass 40, count 0 2006.225.07:34:41.85#ibcon#*after write, iclass 40, count 0 2006.225.07:34:41.85#ibcon#*before return 0, iclass 40, count 0 2006.225.07:34:41.85#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:34:41.85#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:34:41.85#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:34:41.85#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:34:41.85$vc4f8/vblo=5,744.99 2006.225.07:34:41.85#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.07:34:41.85#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.07:34:41.85#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:41.85#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:34:41.85#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:34:41.85#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:34:41.85#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:34:41.85#ibcon#first serial, iclass 4, count 0 2006.225.07:34:41.85#ibcon#enter sib2, iclass 4, count 0 2006.225.07:34:41.85#ibcon#flushed, iclass 4, count 0 2006.225.07:34:41.85#ibcon#about to write, iclass 4, count 0 2006.225.07:34:41.85#ibcon#wrote, iclass 4, count 0 2006.225.07:34:41.85#ibcon#about to read 3, iclass 4, count 0 2006.225.07:34:41.87#ibcon#read 3, iclass 4, count 0 2006.225.07:34:41.87#ibcon#about to read 4, iclass 4, count 0 2006.225.07:34:41.87#ibcon#read 4, iclass 4, count 0 2006.225.07:34:41.87#ibcon#about to read 5, iclass 4, count 0 2006.225.07:34:41.87#ibcon#read 5, iclass 4, count 0 2006.225.07:34:41.87#ibcon#about to read 6, iclass 4, count 0 2006.225.07:34:41.87#ibcon#read 6, iclass 4, count 0 2006.225.07:34:41.87#ibcon#end of sib2, iclass 4, count 0 2006.225.07:34:41.87#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:34:41.87#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:34:41.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:34:41.87#ibcon#*before write, iclass 4, count 0 2006.225.07:34:41.87#ibcon#enter sib2, iclass 4, count 0 2006.225.07:34:41.87#ibcon#flushed, iclass 4, count 0 2006.225.07:34:41.87#ibcon#about to write, iclass 4, count 0 2006.225.07:34:41.87#ibcon#wrote, iclass 4, count 0 2006.225.07:34:41.87#ibcon#about to read 3, iclass 4, count 0 2006.225.07:34:41.91#ibcon#read 3, iclass 4, count 0 2006.225.07:34:41.91#ibcon#about to read 4, iclass 4, count 0 2006.225.07:34:41.91#ibcon#read 4, iclass 4, count 0 2006.225.07:34:41.91#ibcon#about to read 5, iclass 4, count 0 2006.225.07:34:41.91#ibcon#read 5, iclass 4, count 0 2006.225.07:34:41.91#ibcon#about to read 6, iclass 4, count 0 2006.225.07:34:41.91#ibcon#read 6, iclass 4, count 0 2006.225.07:34:41.91#ibcon#end of sib2, iclass 4, count 0 2006.225.07:34:41.91#ibcon#*after write, iclass 4, count 0 2006.225.07:34:41.91#ibcon#*before return 0, iclass 4, count 0 2006.225.07:34:41.91#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:34:41.91#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:34:41.91#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:34:41.91#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:34:41.91$vc4f8/vb=5,4 2006.225.07:34:41.91#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.225.07:34:41.91#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.225.07:34:41.91#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:41.91#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:34:41.97#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:34:41.97#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:34:41.97#ibcon#enter wrdev, iclass 6, count 2 2006.225.07:34:41.97#ibcon#first serial, iclass 6, count 2 2006.225.07:34:41.97#ibcon#enter sib2, iclass 6, count 2 2006.225.07:34:41.97#ibcon#flushed, iclass 6, count 2 2006.225.07:34:41.97#ibcon#about to write, iclass 6, count 2 2006.225.07:34:41.97#ibcon#wrote, iclass 6, count 2 2006.225.07:34:41.97#ibcon#about to read 3, iclass 6, count 2 2006.225.07:34:41.99#ibcon#read 3, iclass 6, count 2 2006.225.07:34:41.99#ibcon#about to read 4, iclass 6, count 2 2006.225.07:34:41.99#ibcon#read 4, iclass 6, count 2 2006.225.07:34:41.99#ibcon#about to read 5, iclass 6, count 2 2006.225.07:34:41.99#ibcon#read 5, iclass 6, count 2 2006.225.07:34:41.99#ibcon#about to read 6, iclass 6, count 2 2006.225.07:34:41.99#ibcon#read 6, iclass 6, count 2 2006.225.07:34:41.99#ibcon#end of sib2, iclass 6, count 2 2006.225.07:34:41.99#ibcon#*mode == 0, iclass 6, count 2 2006.225.07:34:41.99#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.225.07:34:41.99#ibcon#[27=AT05-04\r\n] 2006.225.07:34:41.99#ibcon#*before write, iclass 6, count 2 2006.225.07:34:41.99#ibcon#enter sib2, iclass 6, count 2 2006.225.07:34:41.99#ibcon#flushed, iclass 6, count 2 2006.225.07:34:41.99#ibcon#about to write, iclass 6, count 2 2006.225.07:34:41.99#ibcon#wrote, iclass 6, count 2 2006.225.07:34:41.99#ibcon#about to read 3, iclass 6, count 2 2006.225.07:34:42.02#ibcon#read 3, iclass 6, count 2 2006.225.07:34:42.02#ibcon#about to read 4, iclass 6, count 2 2006.225.07:34:42.02#ibcon#read 4, iclass 6, count 2 2006.225.07:34:42.02#ibcon#about to read 5, iclass 6, count 2 2006.225.07:34:42.02#ibcon#read 5, iclass 6, count 2 2006.225.07:34:42.02#ibcon#about to read 6, iclass 6, count 2 2006.225.07:34:42.02#ibcon#read 6, iclass 6, count 2 2006.225.07:34:42.02#ibcon#end of sib2, iclass 6, count 2 2006.225.07:34:42.02#ibcon#*after write, iclass 6, count 2 2006.225.07:34:42.02#ibcon#*before return 0, iclass 6, count 2 2006.225.07:34:42.02#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:34:42.02#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:34:42.02#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.225.07:34:42.02#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:42.02#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:34:42.14#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:34:42.14#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:34:42.14#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:34:42.14#ibcon#first serial, iclass 6, count 0 2006.225.07:34:42.14#ibcon#enter sib2, iclass 6, count 0 2006.225.07:34:42.14#ibcon#flushed, iclass 6, count 0 2006.225.07:34:42.14#ibcon#about to write, iclass 6, count 0 2006.225.07:34:42.14#ibcon#wrote, iclass 6, count 0 2006.225.07:34:42.14#ibcon#about to read 3, iclass 6, count 0 2006.225.07:34:42.16#ibcon#read 3, iclass 6, count 0 2006.225.07:34:42.16#ibcon#about to read 4, iclass 6, count 0 2006.225.07:34:42.16#ibcon#read 4, iclass 6, count 0 2006.225.07:34:42.16#ibcon#about to read 5, iclass 6, count 0 2006.225.07:34:42.16#ibcon#read 5, iclass 6, count 0 2006.225.07:34:42.16#ibcon#about to read 6, iclass 6, count 0 2006.225.07:34:42.16#ibcon#read 6, iclass 6, count 0 2006.225.07:34:42.16#ibcon#end of sib2, iclass 6, count 0 2006.225.07:34:42.16#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:34:42.16#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:34:42.16#ibcon#[27=USB\r\n] 2006.225.07:34:42.16#ibcon#*before write, iclass 6, count 0 2006.225.07:34:42.16#ibcon#enter sib2, iclass 6, count 0 2006.225.07:34:42.16#ibcon#flushed, iclass 6, count 0 2006.225.07:34:42.16#ibcon#about to write, iclass 6, count 0 2006.225.07:34:42.16#ibcon#wrote, iclass 6, count 0 2006.225.07:34:42.16#ibcon#about to read 3, iclass 6, count 0 2006.225.07:34:42.20#ibcon#read 3, iclass 6, count 0 2006.225.07:34:42.20#ibcon#about to read 4, iclass 6, count 0 2006.225.07:34:42.20#ibcon#read 4, iclass 6, count 0 2006.225.07:34:42.20#ibcon#about to read 5, iclass 6, count 0 2006.225.07:34:42.20#ibcon#read 5, iclass 6, count 0 2006.225.07:34:42.20#ibcon#about to read 6, iclass 6, count 0 2006.225.07:34:42.20#ibcon#read 6, iclass 6, count 0 2006.225.07:34:42.20#ibcon#end of sib2, iclass 6, count 0 2006.225.07:34:42.20#ibcon#*after write, iclass 6, count 0 2006.225.07:34:42.20#ibcon#*before return 0, iclass 6, count 0 2006.225.07:34:42.20#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:34:42.20#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:34:42.20#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:34:42.20#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:34:42.20$vc4f8/vblo=6,752.99 2006.225.07:34:42.20#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.07:34:42.20#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.07:34:42.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:34:42.20#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:34:42.20#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:34:42.20#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:34:42.20#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:34:42.20#ibcon#first serial, iclass 10, count 0 2006.225.07:34:42.20#ibcon#enter sib2, iclass 10, count 0 2006.225.07:34:42.20#ibcon#flushed, iclass 10, count 0 2006.225.07:34:42.20#ibcon#about to write, iclass 10, count 0 2006.225.07:34:42.20#ibcon#wrote, iclass 10, count 0 2006.225.07:34:42.20#ibcon#about to read 3, iclass 10, count 0 2006.225.07:34:42.21#ibcon#read 3, iclass 10, count 0 2006.225.07:34:42.21#ibcon#about to read 4, iclass 10, count 0 2006.225.07:34:42.21#ibcon#read 4, iclass 10, count 0 2006.225.07:34:42.21#ibcon#about to read 5, iclass 10, count 0 2006.225.07:34:42.21#ibcon#read 5, iclass 10, count 0 2006.225.07:34:42.21#ibcon#about to read 6, iclass 10, count 0 2006.225.07:34:42.21#ibcon#read 6, iclass 10, count 0 2006.225.07:34:42.21#ibcon#end of sib2, iclass 10, count 0 2006.225.07:34:42.21#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:34:42.21#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:34:42.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:34:42.21#ibcon#*before write, iclass 10, count 0 2006.225.07:34:42.21#ibcon#enter sib2, iclass 10, count 0 2006.225.07:34:42.21#ibcon#flushed, iclass 10, count 0 2006.225.07:34:42.21#ibcon#about to write, iclass 10, count 0 2006.225.07:34:42.21#ibcon#wrote, iclass 10, count 0 2006.225.07:34:42.21#ibcon#about to read 3, iclass 10, count 0 2006.225.07:34:42.25#ibcon#read 3, iclass 10, count 0 2006.225.07:34:42.25#ibcon#about to read 4, iclass 10, count 0 2006.225.07:34:42.25#ibcon#read 4, iclass 10, count 0 2006.225.07:34:42.25#ibcon#about to read 5, iclass 10, count 0 2006.225.07:34:42.25#ibcon#read 5, iclass 10, count 0 2006.225.07:34:42.25#ibcon#about to read 6, iclass 10, count 0 2006.225.07:34:42.25#ibcon#read 6, iclass 10, count 0 2006.225.07:34:42.25#ibcon#end of sib2, iclass 10, count 0 2006.225.07:34:42.25#ibcon#*after write, iclass 10, count 0 2006.225.07:34:42.25#ibcon#*before return 0, iclass 10, count 0 2006.225.07:34:42.25#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:34:42.25#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:34:42.25#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:34:42.25#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:34:42.25$vc4f8/vb=6,4 2006.225.07:34:42.25#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.07:34:42.25#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.07:34:42.25#ibcon#ireg 11 cls_cnt 2 2006.225.07:34:42.25#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:34:42.32#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:34:42.32#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:34:42.32#ibcon#enter wrdev, iclass 12, count 2 2006.225.07:34:42.32#ibcon#first serial, iclass 12, count 2 2006.225.07:34:42.32#ibcon#enter sib2, iclass 12, count 2 2006.225.07:34:42.32#ibcon#flushed, iclass 12, count 2 2006.225.07:34:42.32#ibcon#about to write, iclass 12, count 2 2006.225.07:34:42.32#ibcon#wrote, iclass 12, count 2 2006.225.07:34:42.32#ibcon#about to read 3, iclass 12, count 2 2006.225.07:34:42.34#ibcon#read 3, iclass 12, count 2 2006.225.07:34:42.34#ibcon#about to read 4, iclass 12, count 2 2006.225.07:34:42.34#ibcon#read 4, iclass 12, count 2 2006.225.07:34:42.34#ibcon#about to read 5, iclass 12, count 2 2006.225.07:34:42.34#ibcon#read 5, iclass 12, count 2 2006.225.07:34:42.34#ibcon#about to read 6, iclass 12, count 2 2006.225.07:34:42.34#ibcon#read 6, iclass 12, count 2 2006.225.07:34:42.34#ibcon#end of sib2, iclass 12, count 2 2006.225.07:34:42.34#ibcon#*mode == 0, iclass 12, count 2 2006.225.07:34:42.34#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.07:34:42.34#ibcon#[27=AT06-04\r\n] 2006.225.07:34:42.34#ibcon#*before write, iclass 12, count 2 2006.225.07:34:42.34#ibcon#enter sib2, iclass 12, count 2 2006.225.07:34:42.34#ibcon#flushed, iclass 12, count 2 2006.225.07:34:42.34#ibcon#about to write, iclass 12, count 2 2006.225.07:34:42.34#ibcon#wrote, iclass 12, count 2 2006.225.07:34:42.34#ibcon#about to read 3, iclass 12, count 2 2006.225.07:34:42.37#ibcon#read 3, iclass 12, count 2 2006.225.07:34:42.37#ibcon#about to read 4, iclass 12, count 2 2006.225.07:34:42.37#ibcon#read 4, iclass 12, count 2 2006.225.07:34:42.37#ibcon#about to read 5, iclass 12, count 2 2006.225.07:34:42.37#ibcon#read 5, iclass 12, count 2 2006.225.07:34:42.37#ibcon#about to read 6, iclass 12, count 2 2006.225.07:34:42.37#ibcon#read 6, iclass 12, count 2 2006.225.07:34:42.37#ibcon#end of sib2, iclass 12, count 2 2006.225.07:34:42.37#ibcon#*after write, iclass 12, count 2 2006.225.07:34:42.37#ibcon#*before return 0, iclass 12, count 2 2006.225.07:34:42.37#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:34:42.37#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:34:42.37#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.07:34:42.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:34:42.37#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:34:42.49#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:34:42.49#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:34:42.49#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:34:42.49#ibcon#first serial, iclass 12, count 0 2006.225.07:34:42.49#ibcon#enter sib2, iclass 12, count 0 2006.225.07:34:42.49#ibcon#flushed, iclass 12, count 0 2006.225.07:34:42.49#ibcon#about to write, iclass 12, count 0 2006.225.07:34:42.49#ibcon#wrote, iclass 12, count 0 2006.225.07:34:42.49#ibcon#about to read 3, iclass 12, count 0 2006.225.07:34:42.51#ibcon#read 3, iclass 12, count 0 2006.225.07:34:42.51#ibcon#about to read 4, iclass 12, count 0 2006.225.07:34:42.51#ibcon#read 4, iclass 12, count 0 2006.225.07:34:42.51#ibcon#about to read 5, iclass 12, count 0 2006.225.07:34:42.51#ibcon#read 5, iclass 12, count 0 2006.225.07:34:42.51#ibcon#about to read 6, iclass 12, count 0 2006.225.07:34:42.51#ibcon#read 6, iclass 12, count 0 2006.225.07:34:42.51#ibcon#end of sib2, iclass 12, count 0 2006.225.07:34:42.51#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:34:42.51#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:34:42.51#ibcon#[27=USB\r\n] 2006.225.07:34:42.51#ibcon#*before write, iclass 12, count 0 2006.225.07:34:42.51#ibcon#enter sib2, iclass 12, count 0 2006.225.07:34:42.51#ibcon#flushed, iclass 12, count 0 2006.225.07:34:42.51#ibcon#about to write, iclass 12, count 0 2006.225.07:34:42.51#ibcon#wrote, iclass 12, count 0 2006.225.07:34:42.51#ibcon#about to read 3, iclass 12, count 0 2006.225.07:34:42.54#ibcon#read 3, iclass 12, count 0 2006.225.07:34:42.54#ibcon#about to read 4, iclass 12, count 0 2006.225.07:34:42.54#ibcon#read 4, iclass 12, count 0 2006.225.07:34:42.54#ibcon#about to read 5, iclass 12, count 0 2006.225.07:34:42.54#ibcon#read 5, iclass 12, count 0 2006.225.07:34:42.54#ibcon#about to read 6, iclass 12, count 0 2006.225.07:34:42.54#ibcon#read 6, iclass 12, count 0 2006.225.07:34:42.54#ibcon#end of sib2, iclass 12, count 0 2006.225.07:34:42.54#ibcon#*after write, iclass 12, count 0 2006.225.07:34:42.54#ibcon#*before return 0, iclass 12, count 0 2006.225.07:34:42.54#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:34:42.54#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:34:42.54#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:34:42.54#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:34:42.54$vc4f8/vabw=wide 2006.225.07:34:42.54#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.07:34:42.54#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.07:34:42.54#ibcon#ireg 8 cls_cnt 0 2006.225.07:34:42.54#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:34:42.54#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:34:42.54#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:34:42.54#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:34:42.54#ibcon#first serial, iclass 14, count 0 2006.225.07:34:42.54#ibcon#enter sib2, iclass 14, count 0 2006.225.07:34:42.54#ibcon#flushed, iclass 14, count 0 2006.225.07:34:42.54#ibcon#about to write, iclass 14, count 0 2006.225.07:34:42.54#ibcon#wrote, iclass 14, count 0 2006.225.07:34:42.54#ibcon#about to read 3, iclass 14, count 0 2006.225.07:34:42.56#ibcon#read 3, iclass 14, count 0 2006.225.07:34:42.56#ibcon#about to read 4, iclass 14, count 0 2006.225.07:34:42.56#ibcon#read 4, iclass 14, count 0 2006.225.07:34:42.56#ibcon#about to read 5, iclass 14, count 0 2006.225.07:34:42.56#ibcon#read 5, iclass 14, count 0 2006.225.07:34:42.56#ibcon#about to read 6, iclass 14, count 0 2006.225.07:34:42.56#ibcon#read 6, iclass 14, count 0 2006.225.07:34:42.56#ibcon#end of sib2, iclass 14, count 0 2006.225.07:34:42.56#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:34:42.56#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:34:42.56#ibcon#[25=BW32\r\n] 2006.225.07:34:42.56#ibcon#*before write, iclass 14, count 0 2006.225.07:34:42.56#ibcon#enter sib2, iclass 14, count 0 2006.225.07:34:42.56#ibcon#flushed, iclass 14, count 0 2006.225.07:34:42.56#ibcon#about to write, iclass 14, count 0 2006.225.07:34:42.56#ibcon#wrote, iclass 14, count 0 2006.225.07:34:42.56#ibcon#about to read 3, iclass 14, count 0 2006.225.07:34:42.59#ibcon#read 3, iclass 14, count 0 2006.225.07:34:42.59#ibcon#about to read 4, iclass 14, count 0 2006.225.07:34:42.59#ibcon#read 4, iclass 14, count 0 2006.225.07:34:42.59#ibcon#about to read 5, iclass 14, count 0 2006.225.07:34:42.59#ibcon#read 5, iclass 14, count 0 2006.225.07:34:42.59#ibcon#about to read 6, iclass 14, count 0 2006.225.07:34:42.59#ibcon#read 6, iclass 14, count 0 2006.225.07:34:42.59#ibcon#end of sib2, iclass 14, count 0 2006.225.07:34:42.59#ibcon#*after write, iclass 14, count 0 2006.225.07:34:42.59#ibcon#*before return 0, iclass 14, count 0 2006.225.07:34:42.59#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:34:42.59#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:34:42.59#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:34:42.59#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:34:42.59$vc4f8/vbbw=wide 2006.225.07:34:42.59#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.07:34:42.59#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.07:34:42.59#ibcon#ireg 8 cls_cnt 0 2006.225.07:34:42.59#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:34:42.66#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:34:42.66#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:34:42.66#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:34:42.66#ibcon#first serial, iclass 16, count 0 2006.225.07:34:42.66#ibcon#enter sib2, iclass 16, count 0 2006.225.07:34:42.66#ibcon#flushed, iclass 16, count 0 2006.225.07:34:42.66#ibcon#about to write, iclass 16, count 0 2006.225.07:34:42.66#ibcon#wrote, iclass 16, count 0 2006.225.07:34:42.66#ibcon#about to read 3, iclass 16, count 0 2006.225.07:34:42.68#ibcon#read 3, iclass 16, count 0 2006.225.07:34:42.68#ibcon#about to read 4, iclass 16, count 0 2006.225.07:34:42.68#ibcon#read 4, iclass 16, count 0 2006.225.07:34:42.68#ibcon#about to read 5, iclass 16, count 0 2006.225.07:34:42.68#ibcon#read 5, iclass 16, count 0 2006.225.07:34:42.68#ibcon#about to read 6, iclass 16, count 0 2006.225.07:34:42.68#ibcon#read 6, iclass 16, count 0 2006.225.07:34:42.68#ibcon#end of sib2, iclass 16, count 0 2006.225.07:34:42.68#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:34:42.68#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:34:42.68#ibcon#[27=BW32\r\n] 2006.225.07:34:42.68#ibcon#*before write, iclass 16, count 0 2006.225.07:34:42.68#ibcon#enter sib2, iclass 16, count 0 2006.225.07:34:42.68#ibcon#flushed, iclass 16, count 0 2006.225.07:34:42.68#ibcon#about to write, iclass 16, count 0 2006.225.07:34:42.68#ibcon#wrote, iclass 16, count 0 2006.225.07:34:42.68#ibcon#about to read 3, iclass 16, count 0 2006.225.07:34:42.71#ibcon#read 3, iclass 16, count 0 2006.225.07:34:42.71#ibcon#about to read 4, iclass 16, count 0 2006.225.07:34:42.71#ibcon#read 4, iclass 16, count 0 2006.225.07:34:42.71#ibcon#about to read 5, iclass 16, count 0 2006.225.07:34:42.71#ibcon#read 5, iclass 16, count 0 2006.225.07:34:42.71#ibcon#about to read 6, iclass 16, count 0 2006.225.07:34:42.71#ibcon#read 6, iclass 16, count 0 2006.225.07:34:42.71#ibcon#end of sib2, iclass 16, count 0 2006.225.07:34:42.71#ibcon#*after write, iclass 16, count 0 2006.225.07:34:42.71#ibcon#*before return 0, iclass 16, count 0 2006.225.07:34:42.71#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:34:42.71#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:34:42.71#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:34:42.71#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:34:42.71$4f8m12a/ifd4f 2006.225.07:34:42.71$ifd4f/lo= 2006.225.07:34:42.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:34:42.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:34:42.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:34:42.71$ifd4f/patch= 2006.225.07:34:42.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:34:42.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:34:42.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:34:42.71$4f8m12a/"form=m,16.000,1:2 2006.225.07:34:42.71$4f8m12a/"tpicd 2006.225.07:34:42.71$4f8m12a/echo=off 2006.225.07:34:42.71$4f8m12a/xlog=off 2006.225.07:34:42.72:!2006.225.07:35:10 2006.225.07:34:53.13#trakl#Source acquired 2006.225.07:34:54.13#flagr#flagr/antenna,acquired 2006.225.07:35:10.01:preob 2006.225.07:35:11.13/onsource/TRACKING 2006.225.07:35:11.13:!2006.225.07:35:20 2006.225.07:35:20.00:data_valid=on 2006.225.07:35:20.00:midob 2006.225.07:35:20.13/onsource/TRACKING 2006.225.07:35:20.13/wx/27.93,1003.2,72 2006.225.07:35:20.18/cable/+6.4059E-03 2006.225.07:35:21.27/va/01,08,usb,yes,29,30 2006.225.07:35:21.27/va/02,07,usb,yes,29,30 2006.225.07:35:21.27/va/03,06,usb,yes,30,31 2006.225.07:35:21.27/va/04,07,usb,yes,30,32 2006.225.07:35:21.27/va/05,07,usb,yes,32,34 2006.225.07:35:21.27/va/06,06,usb,yes,32,31 2006.225.07:35:21.27/va/07,06,usb,yes,32,32 2006.225.07:35:21.27/va/08,07,usb,yes,30,30 2006.225.07:35:21.50/valo/01,532.99,yes,locked 2006.225.07:35:21.50/valo/02,572.99,yes,locked 2006.225.07:35:21.50/valo/03,672.99,yes,locked 2006.225.07:35:21.50/valo/04,832.99,yes,locked 2006.225.07:35:21.50/valo/05,652.99,yes,locked 2006.225.07:35:21.50/valo/06,772.99,yes,locked 2006.225.07:35:21.50/valo/07,832.99,yes,locked 2006.225.07:35:21.50/valo/08,852.99,yes,locked 2006.225.07:35:22.59/vb/01,04,usb,yes,30,29 2006.225.07:35:22.59/vb/02,04,usb,yes,32,34 2006.225.07:35:22.59/vb/03,04,usb,yes,29,32 2006.225.07:35:22.59/vb/04,04,usb,yes,29,30 2006.225.07:35:22.59/vb/05,04,usb,yes,28,32 2006.225.07:35:22.59/vb/06,04,usb,yes,29,32 2006.225.07:35:22.59/vb/07,04,usb,yes,31,31 2006.225.07:35:22.59/vb/08,04,usb,yes,28,32 2006.225.07:35:22.82/vblo/01,632.99,yes,locked 2006.225.07:35:22.82/vblo/02,640.99,yes,locked 2006.225.07:35:22.82/vblo/03,656.99,yes,locked 2006.225.07:35:22.82/vblo/04,712.99,yes,locked 2006.225.07:35:22.82/vblo/05,744.99,yes,locked 2006.225.07:35:22.82/vblo/06,752.99,yes,locked 2006.225.07:35:22.82/vblo/07,734.99,yes,locked 2006.225.07:35:22.82/vblo/08,744.99,yes,locked 2006.225.07:35:22.97/vabw/8 2006.225.07:35:23.12/vbbw/8 2006.225.07:35:23.21/xfe/off,on,15.2 2006.225.07:35:23.59/ifatt/23,28,28,28 2006.225.07:35:24.07/fmout-gps/S +4.44E-07 2006.225.07:35:24.11:!2006.225.07:36:20 2006.225.07:36:20.00:data_valid=off 2006.225.07:36:20.00:postob 2006.225.07:36:20.06/cable/+6.4049E-03 2006.225.07:36:20.06/wx/27.91,1003.2,71 2006.225.07:36:21.07/fmout-gps/S +4.45E-07 2006.225.07:36:21.07:scan_name=225-0737,k06225,60 2006.225.07:36:21.07:source=0602+673,060752.67,672055.4,2000.0,ccw 2006.225.07:36:22.14#flagr#flagr/antenna,new-source 2006.225.07:36:22.14:checkk5 2006.225.07:36:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:36:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:36:23.25/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:36:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:36:23.99/chk_obsdata//k5ts1/T2250735??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:36:24.36/chk_obsdata//k5ts2/T2250735??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:36:24.73/chk_obsdata//k5ts3/T2250735??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:36:25.09/chk_obsdata//k5ts4/T2250735??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:36:25.79/k5log//k5ts1_log_newline 2006.225.07:36:26.48/k5log//k5ts2_log_newline 2006.225.07:36:27.16/k5log//k5ts3_log_newline 2006.225.07:36:27.84/k5log//k5ts4_log_newline 2006.225.07:36:27.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:36:27.86:4f8m12a=1 2006.225.07:36:27.86$4f8m12a/echo=on 2006.225.07:36:27.86$4f8m12a/pcalon 2006.225.07:36:27.86$pcalon/"no phase cal control is implemented here 2006.225.07:36:27.86$4f8m12a/"tpicd=stop 2006.225.07:36:27.86$4f8m12a/vc4f8 2006.225.07:36:27.86$vc4f8/valo=1,532.99 2006.225.07:36:27.86#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.225.07:36:27.86#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.225.07:36:27.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:27.86#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:36:27.86#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:36:27.86#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:36:27.86#ibcon#enter wrdev, iclass 23, count 0 2006.225.07:36:27.86#ibcon#first serial, iclass 23, count 0 2006.225.07:36:27.86#ibcon#enter sib2, iclass 23, count 0 2006.225.07:36:27.86#ibcon#flushed, iclass 23, count 0 2006.225.07:36:27.86#ibcon#about to write, iclass 23, count 0 2006.225.07:36:27.86#ibcon#wrote, iclass 23, count 0 2006.225.07:36:27.86#ibcon#about to read 3, iclass 23, count 0 2006.225.07:36:27.88#ibcon#read 3, iclass 23, count 0 2006.225.07:36:27.88#ibcon#about to read 4, iclass 23, count 0 2006.225.07:36:27.88#ibcon#read 4, iclass 23, count 0 2006.225.07:36:27.88#ibcon#about to read 5, iclass 23, count 0 2006.225.07:36:27.88#ibcon#read 5, iclass 23, count 0 2006.225.07:36:27.88#ibcon#about to read 6, iclass 23, count 0 2006.225.07:36:27.88#ibcon#read 6, iclass 23, count 0 2006.225.07:36:27.88#ibcon#end of sib2, iclass 23, count 0 2006.225.07:36:27.88#ibcon#*mode == 0, iclass 23, count 0 2006.225.07:36:27.88#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.07:36:27.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:36:27.88#ibcon#*before write, iclass 23, count 0 2006.225.07:36:27.88#ibcon#enter sib2, iclass 23, count 0 2006.225.07:36:27.88#ibcon#flushed, iclass 23, count 0 2006.225.07:36:27.88#ibcon#about to write, iclass 23, count 0 2006.225.07:36:27.88#ibcon#wrote, iclass 23, count 0 2006.225.07:36:27.88#ibcon#about to read 3, iclass 23, count 0 2006.225.07:36:27.93#ibcon#read 3, iclass 23, count 0 2006.225.07:36:27.93#ibcon#about to read 4, iclass 23, count 0 2006.225.07:36:27.93#ibcon#read 4, iclass 23, count 0 2006.225.07:36:27.93#ibcon#about to read 5, iclass 23, count 0 2006.225.07:36:27.93#ibcon#read 5, iclass 23, count 0 2006.225.07:36:27.93#ibcon#about to read 6, iclass 23, count 0 2006.225.07:36:27.93#ibcon#read 6, iclass 23, count 0 2006.225.07:36:27.93#ibcon#end of sib2, iclass 23, count 0 2006.225.07:36:27.93#ibcon#*after write, iclass 23, count 0 2006.225.07:36:27.93#ibcon#*before return 0, iclass 23, count 0 2006.225.07:36:27.93#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:36:27.93#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:36:27.93#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.07:36:27.93#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.07:36:27.93$vc4f8/va=1,8 2006.225.07:36:27.93#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.225.07:36:27.93#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.225.07:36:27.93#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:27.93#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:36:27.93#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:36:27.93#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:36:27.93#ibcon#enter wrdev, iclass 25, count 2 2006.225.07:36:27.93#ibcon#first serial, iclass 25, count 2 2006.225.07:36:27.93#ibcon#enter sib2, iclass 25, count 2 2006.225.07:36:27.93#ibcon#flushed, iclass 25, count 2 2006.225.07:36:27.93#ibcon#about to write, iclass 25, count 2 2006.225.07:36:27.93#ibcon#wrote, iclass 25, count 2 2006.225.07:36:27.93#ibcon#about to read 3, iclass 25, count 2 2006.225.07:36:27.95#ibcon#read 3, iclass 25, count 2 2006.225.07:36:27.95#ibcon#about to read 4, iclass 25, count 2 2006.225.07:36:27.95#ibcon#read 4, iclass 25, count 2 2006.225.07:36:27.95#ibcon#about to read 5, iclass 25, count 2 2006.225.07:36:27.95#ibcon#read 5, iclass 25, count 2 2006.225.07:36:27.95#ibcon#about to read 6, iclass 25, count 2 2006.225.07:36:27.95#ibcon#read 6, iclass 25, count 2 2006.225.07:36:27.95#ibcon#end of sib2, iclass 25, count 2 2006.225.07:36:27.95#ibcon#*mode == 0, iclass 25, count 2 2006.225.07:36:27.95#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.225.07:36:27.95#ibcon#[25=AT01-08\r\n] 2006.225.07:36:27.95#ibcon#*before write, iclass 25, count 2 2006.225.07:36:27.95#ibcon#enter sib2, iclass 25, count 2 2006.225.07:36:27.95#ibcon#flushed, iclass 25, count 2 2006.225.07:36:27.95#ibcon#about to write, iclass 25, count 2 2006.225.07:36:27.95#ibcon#wrote, iclass 25, count 2 2006.225.07:36:27.95#ibcon#about to read 3, iclass 25, count 2 2006.225.07:36:27.99#ibcon#read 3, iclass 25, count 2 2006.225.07:36:27.99#ibcon#about to read 4, iclass 25, count 2 2006.225.07:36:27.99#ibcon#read 4, iclass 25, count 2 2006.225.07:36:27.99#ibcon#about to read 5, iclass 25, count 2 2006.225.07:36:27.99#ibcon#read 5, iclass 25, count 2 2006.225.07:36:27.99#ibcon#about to read 6, iclass 25, count 2 2006.225.07:36:27.99#ibcon#read 6, iclass 25, count 2 2006.225.07:36:27.99#ibcon#end of sib2, iclass 25, count 2 2006.225.07:36:27.99#ibcon#*after write, iclass 25, count 2 2006.225.07:36:27.99#ibcon#*before return 0, iclass 25, count 2 2006.225.07:36:27.99#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:36:27.99#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:36:27.99#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.225.07:36:27.99#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:27.99#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:36:28.10#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:36:28.10#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:36:28.10#ibcon#enter wrdev, iclass 25, count 0 2006.225.07:36:28.10#ibcon#first serial, iclass 25, count 0 2006.225.07:36:28.10#ibcon#enter sib2, iclass 25, count 0 2006.225.07:36:28.10#ibcon#flushed, iclass 25, count 0 2006.225.07:36:28.10#ibcon#about to write, iclass 25, count 0 2006.225.07:36:28.10#ibcon#wrote, iclass 25, count 0 2006.225.07:36:28.10#ibcon#about to read 3, iclass 25, count 0 2006.225.07:36:28.12#ibcon#read 3, iclass 25, count 0 2006.225.07:36:28.12#ibcon#about to read 4, iclass 25, count 0 2006.225.07:36:28.12#ibcon#read 4, iclass 25, count 0 2006.225.07:36:28.12#ibcon#about to read 5, iclass 25, count 0 2006.225.07:36:28.12#ibcon#read 5, iclass 25, count 0 2006.225.07:36:28.12#ibcon#about to read 6, iclass 25, count 0 2006.225.07:36:28.12#ibcon#read 6, iclass 25, count 0 2006.225.07:36:28.12#ibcon#end of sib2, iclass 25, count 0 2006.225.07:36:28.12#ibcon#*mode == 0, iclass 25, count 0 2006.225.07:36:28.12#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.07:36:28.12#ibcon#[25=USB\r\n] 2006.225.07:36:28.12#ibcon#*before write, iclass 25, count 0 2006.225.07:36:28.12#ibcon#enter sib2, iclass 25, count 0 2006.225.07:36:28.12#ibcon#flushed, iclass 25, count 0 2006.225.07:36:28.12#ibcon#about to write, iclass 25, count 0 2006.225.07:36:28.12#ibcon#wrote, iclass 25, count 0 2006.225.07:36:28.12#ibcon#about to read 3, iclass 25, count 0 2006.225.07:36:28.15#ibcon#read 3, iclass 25, count 0 2006.225.07:36:28.15#ibcon#about to read 4, iclass 25, count 0 2006.225.07:36:28.15#ibcon#read 4, iclass 25, count 0 2006.225.07:36:28.15#ibcon#about to read 5, iclass 25, count 0 2006.225.07:36:28.15#ibcon#read 5, iclass 25, count 0 2006.225.07:36:28.15#ibcon#about to read 6, iclass 25, count 0 2006.225.07:36:28.15#ibcon#read 6, iclass 25, count 0 2006.225.07:36:28.15#ibcon#end of sib2, iclass 25, count 0 2006.225.07:36:28.15#ibcon#*after write, iclass 25, count 0 2006.225.07:36:28.15#ibcon#*before return 0, iclass 25, count 0 2006.225.07:36:28.15#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:36:28.15#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:36:28.15#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.07:36:28.15#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.07:36:28.15$vc4f8/valo=2,572.99 2006.225.07:36:28.15#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.07:36:28.15#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.07:36:28.15#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:28.15#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:36:28.15#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:36:28.15#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:36:28.15#ibcon#enter wrdev, iclass 27, count 0 2006.225.07:36:28.15#ibcon#first serial, iclass 27, count 0 2006.225.07:36:28.15#ibcon#enter sib2, iclass 27, count 0 2006.225.07:36:28.15#ibcon#flushed, iclass 27, count 0 2006.225.07:36:28.15#ibcon#about to write, iclass 27, count 0 2006.225.07:36:28.15#ibcon#wrote, iclass 27, count 0 2006.225.07:36:28.15#ibcon#about to read 3, iclass 27, count 0 2006.225.07:36:28.18#ibcon#read 3, iclass 27, count 0 2006.225.07:36:28.18#ibcon#about to read 4, iclass 27, count 0 2006.225.07:36:28.18#ibcon#read 4, iclass 27, count 0 2006.225.07:36:28.18#ibcon#about to read 5, iclass 27, count 0 2006.225.07:36:28.18#ibcon#read 5, iclass 27, count 0 2006.225.07:36:28.18#ibcon#about to read 6, iclass 27, count 0 2006.225.07:36:28.18#ibcon#read 6, iclass 27, count 0 2006.225.07:36:28.18#ibcon#end of sib2, iclass 27, count 0 2006.225.07:36:28.18#ibcon#*mode == 0, iclass 27, count 0 2006.225.07:36:28.18#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.07:36:28.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:36:28.18#ibcon#*before write, iclass 27, count 0 2006.225.07:36:28.18#ibcon#enter sib2, iclass 27, count 0 2006.225.07:36:28.18#ibcon#flushed, iclass 27, count 0 2006.225.07:36:28.18#ibcon#about to write, iclass 27, count 0 2006.225.07:36:28.18#ibcon#wrote, iclass 27, count 0 2006.225.07:36:28.18#ibcon#about to read 3, iclass 27, count 0 2006.225.07:36:28.22#ibcon#read 3, iclass 27, count 0 2006.225.07:36:28.22#ibcon#about to read 4, iclass 27, count 0 2006.225.07:36:28.22#ibcon#read 4, iclass 27, count 0 2006.225.07:36:28.22#ibcon#about to read 5, iclass 27, count 0 2006.225.07:36:28.22#ibcon#read 5, iclass 27, count 0 2006.225.07:36:28.22#ibcon#about to read 6, iclass 27, count 0 2006.225.07:36:28.22#ibcon#read 6, iclass 27, count 0 2006.225.07:36:28.22#ibcon#end of sib2, iclass 27, count 0 2006.225.07:36:28.22#ibcon#*after write, iclass 27, count 0 2006.225.07:36:28.22#ibcon#*before return 0, iclass 27, count 0 2006.225.07:36:28.22#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:36:28.22#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:36:28.22#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.07:36:28.22#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.07:36:28.22$vc4f8/va=2,7 2006.225.07:36:28.22#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.225.07:36:28.22#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.225.07:36:28.22#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:28.22#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:36:28.27#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:36:28.27#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:36:28.27#ibcon#enter wrdev, iclass 29, count 2 2006.225.07:36:28.27#ibcon#first serial, iclass 29, count 2 2006.225.07:36:28.27#ibcon#enter sib2, iclass 29, count 2 2006.225.07:36:28.27#ibcon#flushed, iclass 29, count 2 2006.225.07:36:28.27#ibcon#about to write, iclass 29, count 2 2006.225.07:36:28.27#ibcon#wrote, iclass 29, count 2 2006.225.07:36:28.27#ibcon#about to read 3, iclass 29, count 2 2006.225.07:36:28.29#ibcon#read 3, iclass 29, count 2 2006.225.07:36:28.29#ibcon#about to read 4, iclass 29, count 2 2006.225.07:36:28.29#ibcon#read 4, iclass 29, count 2 2006.225.07:36:28.29#ibcon#about to read 5, iclass 29, count 2 2006.225.07:36:28.29#ibcon#read 5, iclass 29, count 2 2006.225.07:36:28.29#ibcon#about to read 6, iclass 29, count 2 2006.225.07:36:28.29#ibcon#read 6, iclass 29, count 2 2006.225.07:36:28.29#ibcon#end of sib2, iclass 29, count 2 2006.225.07:36:28.29#ibcon#*mode == 0, iclass 29, count 2 2006.225.07:36:28.29#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.225.07:36:28.29#ibcon#[25=AT02-07\r\n] 2006.225.07:36:28.29#ibcon#*before write, iclass 29, count 2 2006.225.07:36:28.29#ibcon#enter sib2, iclass 29, count 2 2006.225.07:36:28.29#ibcon#flushed, iclass 29, count 2 2006.225.07:36:28.29#ibcon#about to write, iclass 29, count 2 2006.225.07:36:28.29#ibcon#wrote, iclass 29, count 2 2006.225.07:36:28.29#ibcon#about to read 3, iclass 29, count 2 2006.225.07:36:28.32#ibcon#read 3, iclass 29, count 2 2006.225.07:36:28.32#ibcon#about to read 4, iclass 29, count 2 2006.225.07:36:28.32#ibcon#read 4, iclass 29, count 2 2006.225.07:36:28.32#ibcon#about to read 5, iclass 29, count 2 2006.225.07:36:28.32#ibcon#read 5, iclass 29, count 2 2006.225.07:36:28.32#ibcon#about to read 6, iclass 29, count 2 2006.225.07:36:28.32#ibcon#read 6, iclass 29, count 2 2006.225.07:36:28.32#ibcon#end of sib2, iclass 29, count 2 2006.225.07:36:28.32#ibcon#*after write, iclass 29, count 2 2006.225.07:36:28.32#ibcon#*before return 0, iclass 29, count 2 2006.225.07:36:28.32#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:36:28.32#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:36:28.32#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.225.07:36:28.32#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:28.32#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:36:28.44#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:36:28.44#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:36:28.44#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:36:28.44#ibcon#first serial, iclass 29, count 0 2006.225.07:36:28.44#ibcon#enter sib2, iclass 29, count 0 2006.225.07:36:28.44#ibcon#flushed, iclass 29, count 0 2006.225.07:36:28.44#ibcon#about to write, iclass 29, count 0 2006.225.07:36:28.44#ibcon#wrote, iclass 29, count 0 2006.225.07:36:28.44#ibcon#about to read 3, iclass 29, count 0 2006.225.07:36:28.46#ibcon#read 3, iclass 29, count 0 2006.225.07:36:28.46#ibcon#about to read 4, iclass 29, count 0 2006.225.07:36:28.46#ibcon#read 4, iclass 29, count 0 2006.225.07:36:28.46#ibcon#about to read 5, iclass 29, count 0 2006.225.07:36:28.46#ibcon#read 5, iclass 29, count 0 2006.225.07:36:28.46#ibcon#about to read 6, iclass 29, count 0 2006.225.07:36:28.46#ibcon#read 6, iclass 29, count 0 2006.225.07:36:28.46#ibcon#end of sib2, iclass 29, count 0 2006.225.07:36:28.46#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:36:28.46#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:36:28.46#ibcon#[25=USB\r\n] 2006.225.07:36:28.46#ibcon#*before write, iclass 29, count 0 2006.225.07:36:28.46#ibcon#enter sib2, iclass 29, count 0 2006.225.07:36:28.46#ibcon#flushed, iclass 29, count 0 2006.225.07:36:28.46#ibcon#about to write, iclass 29, count 0 2006.225.07:36:28.46#ibcon#wrote, iclass 29, count 0 2006.225.07:36:28.46#ibcon#about to read 3, iclass 29, count 0 2006.225.07:36:28.49#ibcon#read 3, iclass 29, count 0 2006.225.07:36:28.49#ibcon#about to read 4, iclass 29, count 0 2006.225.07:36:28.49#ibcon#read 4, iclass 29, count 0 2006.225.07:36:28.49#ibcon#about to read 5, iclass 29, count 0 2006.225.07:36:28.49#ibcon#read 5, iclass 29, count 0 2006.225.07:36:28.49#ibcon#about to read 6, iclass 29, count 0 2006.225.07:36:28.49#ibcon#read 6, iclass 29, count 0 2006.225.07:36:28.49#ibcon#end of sib2, iclass 29, count 0 2006.225.07:36:28.49#ibcon#*after write, iclass 29, count 0 2006.225.07:36:28.49#ibcon#*before return 0, iclass 29, count 0 2006.225.07:36:28.49#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:36:28.49#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:36:28.49#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:36:28.49#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:36:28.49$vc4f8/valo=3,672.99 2006.225.07:36:28.49#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.07:36:28.49#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.07:36:28.49#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:28.49#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:36:28.49#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:36:28.49#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:36:28.49#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:36:28.49#ibcon#first serial, iclass 31, count 0 2006.225.07:36:28.49#ibcon#enter sib2, iclass 31, count 0 2006.225.07:36:28.49#ibcon#flushed, iclass 31, count 0 2006.225.07:36:28.49#ibcon#about to write, iclass 31, count 0 2006.225.07:36:28.49#ibcon#wrote, iclass 31, count 0 2006.225.07:36:28.49#ibcon#about to read 3, iclass 31, count 0 2006.225.07:36:28.52#ibcon#read 3, iclass 31, count 0 2006.225.07:36:28.52#ibcon#about to read 4, iclass 31, count 0 2006.225.07:36:28.52#ibcon#read 4, iclass 31, count 0 2006.225.07:36:28.52#ibcon#about to read 5, iclass 31, count 0 2006.225.07:36:28.52#ibcon#read 5, iclass 31, count 0 2006.225.07:36:28.52#ibcon#about to read 6, iclass 31, count 0 2006.225.07:36:28.52#ibcon#read 6, iclass 31, count 0 2006.225.07:36:28.52#ibcon#end of sib2, iclass 31, count 0 2006.225.07:36:28.52#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:36:28.52#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:36:28.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:36:28.52#ibcon#*before write, iclass 31, count 0 2006.225.07:36:28.52#ibcon#enter sib2, iclass 31, count 0 2006.225.07:36:28.52#ibcon#flushed, iclass 31, count 0 2006.225.07:36:28.52#ibcon#about to write, iclass 31, count 0 2006.225.07:36:28.52#ibcon#wrote, iclass 31, count 0 2006.225.07:36:28.52#ibcon#about to read 3, iclass 31, count 0 2006.225.07:36:28.56#ibcon#read 3, iclass 31, count 0 2006.225.07:36:28.56#ibcon#about to read 4, iclass 31, count 0 2006.225.07:36:28.56#ibcon#read 4, iclass 31, count 0 2006.225.07:36:28.56#ibcon#about to read 5, iclass 31, count 0 2006.225.07:36:28.56#ibcon#read 5, iclass 31, count 0 2006.225.07:36:28.56#ibcon#about to read 6, iclass 31, count 0 2006.225.07:36:28.56#ibcon#read 6, iclass 31, count 0 2006.225.07:36:28.56#ibcon#end of sib2, iclass 31, count 0 2006.225.07:36:28.56#ibcon#*after write, iclass 31, count 0 2006.225.07:36:28.56#ibcon#*before return 0, iclass 31, count 0 2006.225.07:36:28.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:36:28.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:36:28.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:36:28.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:36:28.56$vc4f8/va=3,6 2006.225.07:36:28.56#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.225.07:36:28.56#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.225.07:36:28.56#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:28.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:36:28.61#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:36:28.61#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:36:28.61#ibcon#enter wrdev, iclass 33, count 2 2006.225.07:36:28.61#ibcon#first serial, iclass 33, count 2 2006.225.07:36:28.61#ibcon#enter sib2, iclass 33, count 2 2006.225.07:36:28.61#ibcon#flushed, iclass 33, count 2 2006.225.07:36:28.61#ibcon#about to write, iclass 33, count 2 2006.225.07:36:28.61#ibcon#wrote, iclass 33, count 2 2006.225.07:36:28.61#ibcon#about to read 3, iclass 33, count 2 2006.225.07:36:28.63#ibcon#read 3, iclass 33, count 2 2006.225.07:36:28.63#ibcon#about to read 4, iclass 33, count 2 2006.225.07:36:28.63#ibcon#read 4, iclass 33, count 2 2006.225.07:36:28.63#ibcon#about to read 5, iclass 33, count 2 2006.225.07:36:28.63#ibcon#read 5, iclass 33, count 2 2006.225.07:36:28.63#ibcon#about to read 6, iclass 33, count 2 2006.225.07:36:28.63#ibcon#read 6, iclass 33, count 2 2006.225.07:36:28.63#ibcon#end of sib2, iclass 33, count 2 2006.225.07:36:28.63#ibcon#*mode == 0, iclass 33, count 2 2006.225.07:36:28.63#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.225.07:36:28.63#ibcon#[25=AT03-06\r\n] 2006.225.07:36:28.63#ibcon#*before write, iclass 33, count 2 2006.225.07:36:28.63#ibcon#enter sib2, iclass 33, count 2 2006.225.07:36:28.63#ibcon#flushed, iclass 33, count 2 2006.225.07:36:28.63#ibcon#about to write, iclass 33, count 2 2006.225.07:36:28.63#ibcon#wrote, iclass 33, count 2 2006.225.07:36:28.63#ibcon#about to read 3, iclass 33, count 2 2006.225.07:36:28.66#ibcon#read 3, iclass 33, count 2 2006.225.07:36:28.66#ibcon#about to read 4, iclass 33, count 2 2006.225.07:36:28.66#ibcon#read 4, iclass 33, count 2 2006.225.07:36:28.66#ibcon#about to read 5, iclass 33, count 2 2006.225.07:36:28.66#ibcon#read 5, iclass 33, count 2 2006.225.07:36:28.66#ibcon#about to read 6, iclass 33, count 2 2006.225.07:36:28.66#ibcon#read 6, iclass 33, count 2 2006.225.07:36:28.66#ibcon#end of sib2, iclass 33, count 2 2006.225.07:36:28.66#ibcon#*after write, iclass 33, count 2 2006.225.07:36:28.66#ibcon#*before return 0, iclass 33, count 2 2006.225.07:36:28.66#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:36:28.66#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:36:28.66#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.225.07:36:28.66#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:28.66#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:36:28.70#abcon#<5=/06 3.3 6.7 27.91 721003.2\r\n> 2006.225.07:36:28.73#abcon#{5=INTERFACE CLEAR} 2006.225.07:36:28.78#abcon#[5=S1D000X0/0*\r\n] 2006.225.07:36:28.78#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:36:28.78#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:36:28.78#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:36:28.78#ibcon#first serial, iclass 33, count 0 2006.225.07:36:28.78#ibcon#enter sib2, iclass 33, count 0 2006.225.07:36:28.78#ibcon#flushed, iclass 33, count 0 2006.225.07:36:28.78#ibcon#about to write, iclass 33, count 0 2006.225.07:36:28.78#ibcon#wrote, iclass 33, count 0 2006.225.07:36:28.78#ibcon#about to read 3, iclass 33, count 0 2006.225.07:36:28.81#ibcon#read 3, iclass 33, count 0 2006.225.07:36:28.81#ibcon#about to read 4, iclass 33, count 0 2006.225.07:36:28.81#ibcon#read 4, iclass 33, count 0 2006.225.07:36:28.81#ibcon#about to read 5, iclass 33, count 0 2006.225.07:36:28.81#ibcon#read 5, iclass 33, count 0 2006.225.07:36:28.81#ibcon#about to read 6, iclass 33, count 0 2006.225.07:36:28.81#ibcon#read 6, iclass 33, count 0 2006.225.07:36:28.81#ibcon#end of sib2, iclass 33, count 0 2006.225.07:36:28.81#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:36:28.81#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:36:28.81#ibcon#[25=USB\r\n] 2006.225.07:36:28.81#ibcon#*before write, iclass 33, count 0 2006.225.07:36:28.81#ibcon#enter sib2, iclass 33, count 0 2006.225.07:36:28.81#ibcon#flushed, iclass 33, count 0 2006.225.07:36:28.81#ibcon#about to write, iclass 33, count 0 2006.225.07:36:28.81#ibcon#wrote, iclass 33, count 0 2006.225.07:36:28.81#ibcon#about to read 3, iclass 33, count 0 2006.225.07:36:28.84#ibcon#read 3, iclass 33, count 0 2006.225.07:36:28.84#ibcon#about to read 4, iclass 33, count 0 2006.225.07:36:28.84#ibcon#read 4, iclass 33, count 0 2006.225.07:36:28.84#ibcon#about to read 5, iclass 33, count 0 2006.225.07:36:28.84#ibcon#read 5, iclass 33, count 0 2006.225.07:36:28.84#ibcon#about to read 6, iclass 33, count 0 2006.225.07:36:28.84#ibcon#read 6, iclass 33, count 0 2006.225.07:36:28.84#ibcon#end of sib2, iclass 33, count 0 2006.225.07:36:28.84#ibcon#*after write, iclass 33, count 0 2006.225.07:36:28.84#ibcon#*before return 0, iclass 33, count 0 2006.225.07:36:28.84#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:36:28.84#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:36:28.84#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:36:28.84#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:36:28.84$vc4f8/valo=4,832.99 2006.225.07:36:28.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.07:36:28.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.07:36:28.84#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:28.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:36:28.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:36:28.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:36:28.84#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:36:28.84#ibcon#first serial, iclass 39, count 0 2006.225.07:36:28.84#ibcon#enter sib2, iclass 39, count 0 2006.225.07:36:28.84#ibcon#flushed, iclass 39, count 0 2006.225.07:36:28.84#ibcon#about to write, iclass 39, count 0 2006.225.07:36:28.84#ibcon#wrote, iclass 39, count 0 2006.225.07:36:28.84#ibcon#about to read 3, iclass 39, count 0 2006.225.07:36:28.86#ibcon#read 3, iclass 39, count 0 2006.225.07:36:28.86#ibcon#about to read 4, iclass 39, count 0 2006.225.07:36:28.86#ibcon#read 4, iclass 39, count 0 2006.225.07:36:28.86#ibcon#about to read 5, iclass 39, count 0 2006.225.07:36:28.86#ibcon#read 5, iclass 39, count 0 2006.225.07:36:28.86#ibcon#about to read 6, iclass 39, count 0 2006.225.07:36:28.86#ibcon#read 6, iclass 39, count 0 2006.225.07:36:28.86#ibcon#end of sib2, iclass 39, count 0 2006.225.07:36:28.86#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:36:28.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:36:28.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:36:28.86#ibcon#*before write, iclass 39, count 0 2006.225.07:36:28.86#ibcon#enter sib2, iclass 39, count 0 2006.225.07:36:28.86#ibcon#flushed, iclass 39, count 0 2006.225.07:36:28.86#ibcon#about to write, iclass 39, count 0 2006.225.07:36:28.86#ibcon#wrote, iclass 39, count 0 2006.225.07:36:28.86#ibcon#about to read 3, iclass 39, count 0 2006.225.07:36:28.90#ibcon#read 3, iclass 39, count 0 2006.225.07:36:28.90#ibcon#about to read 4, iclass 39, count 0 2006.225.07:36:28.90#ibcon#read 4, iclass 39, count 0 2006.225.07:36:28.90#ibcon#about to read 5, iclass 39, count 0 2006.225.07:36:28.90#ibcon#read 5, iclass 39, count 0 2006.225.07:36:28.90#ibcon#about to read 6, iclass 39, count 0 2006.225.07:36:28.90#ibcon#read 6, iclass 39, count 0 2006.225.07:36:28.90#ibcon#end of sib2, iclass 39, count 0 2006.225.07:36:28.90#ibcon#*after write, iclass 39, count 0 2006.225.07:36:28.90#ibcon#*before return 0, iclass 39, count 0 2006.225.07:36:28.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:36:28.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:36:28.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:36:28.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:36:28.90$vc4f8/va=4,7 2006.225.07:36:28.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.07:36:28.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.07:36:28.90#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:28.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:36:28.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:36:28.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:36:28.96#ibcon#enter wrdev, iclass 3, count 2 2006.225.07:36:28.96#ibcon#first serial, iclass 3, count 2 2006.225.07:36:28.96#ibcon#enter sib2, iclass 3, count 2 2006.225.07:36:28.96#ibcon#flushed, iclass 3, count 2 2006.225.07:36:28.96#ibcon#about to write, iclass 3, count 2 2006.225.07:36:28.96#ibcon#wrote, iclass 3, count 2 2006.225.07:36:28.96#ibcon#about to read 3, iclass 3, count 2 2006.225.07:36:28.98#ibcon#read 3, iclass 3, count 2 2006.225.07:36:28.98#ibcon#about to read 4, iclass 3, count 2 2006.225.07:36:28.98#ibcon#read 4, iclass 3, count 2 2006.225.07:36:28.98#ibcon#about to read 5, iclass 3, count 2 2006.225.07:36:28.98#ibcon#read 5, iclass 3, count 2 2006.225.07:36:28.98#ibcon#about to read 6, iclass 3, count 2 2006.225.07:36:28.98#ibcon#read 6, iclass 3, count 2 2006.225.07:36:28.98#ibcon#end of sib2, iclass 3, count 2 2006.225.07:36:28.98#ibcon#*mode == 0, iclass 3, count 2 2006.225.07:36:28.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.07:36:28.98#ibcon#[25=AT04-07\r\n] 2006.225.07:36:28.98#ibcon#*before write, iclass 3, count 2 2006.225.07:36:28.98#ibcon#enter sib2, iclass 3, count 2 2006.225.07:36:28.98#ibcon#flushed, iclass 3, count 2 2006.225.07:36:28.98#ibcon#about to write, iclass 3, count 2 2006.225.07:36:28.98#ibcon#wrote, iclass 3, count 2 2006.225.07:36:28.98#ibcon#about to read 3, iclass 3, count 2 2006.225.07:36:29.01#ibcon#read 3, iclass 3, count 2 2006.225.07:36:29.01#ibcon#about to read 4, iclass 3, count 2 2006.225.07:36:29.01#ibcon#read 4, iclass 3, count 2 2006.225.07:36:29.01#ibcon#about to read 5, iclass 3, count 2 2006.225.07:36:29.01#ibcon#read 5, iclass 3, count 2 2006.225.07:36:29.01#ibcon#about to read 6, iclass 3, count 2 2006.225.07:36:29.01#ibcon#read 6, iclass 3, count 2 2006.225.07:36:29.01#ibcon#end of sib2, iclass 3, count 2 2006.225.07:36:29.01#ibcon#*after write, iclass 3, count 2 2006.225.07:36:29.01#ibcon#*before return 0, iclass 3, count 2 2006.225.07:36:29.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:36:29.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:36:29.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.07:36:29.01#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:29.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:36:29.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:36:29.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:36:29.13#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:36:29.13#ibcon#first serial, iclass 3, count 0 2006.225.07:36:29.13#ibcon#enter sib2, iclass 3, count 0 2006.225.07:36:29.13#ibcon#flushed, iclass 3, count 0 2006.225.07:36:29.13#ibcon#about to write, iclass 3, count 0 2006.225.07:36:29.13#ibcon#wrote, iclass 3, count 0 2006.225.07:36:29.13#ibcon#about to read 3, iclass 3, count 0 2006.225.07:36:29.15#ibcon#read 3, iclass 3, count 0 2006.225.07:36:29.15#ibcon#about to read 4, iclass 3, count 0 2006.225.07:36:29.15#ibcon#read 4, iclass 3, count 0 2006.225.07:36:29.15#ibcon#about to read 5, iclass 3, count 0 2006.225.07:36:29.15#ibcon#read 5, iclass 3, count 0 2006.225.07:36:29.15#ibcon#about to read 6, iclass 3, count 0 2006.225.07:36:29.15#ibcon#read 6, iclass 3, count 0 2006.225.07:36:29.15#ibcon#end of sib2, iclass 3, count 0 2006.225.07:36:29.15#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:36:29.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:36:29.15#ibcon#[25=USB\r\n] 2006.225.07:36:29.15#ibcon#*before write, iclass 3, count 0 2006.225.07:36:29.15#ibcon#enter sib2, iclass 3, count 0 2006.225.07:36:29.15#ibcon#flushed, iclass 3, count 0 2006.225.07:36:29.15#ibcon#about to write, iclass 3, count 0 2006.225.07:36:29.15#ibcon#wrote, iclass 3, count 0 2006.225.07:36:29.15#ibcon#about to read 3, iclass 3, count 0 2006.225.07:36:29.18#ibcon#read 3, iclass 3, count 0 2006.225.07:36:29.18#ibcon#about to read 4, iclass 3, count 0 2006.225.07:36:29.18#ibcon#read 4, iclass 3, count 0 2006.225.07:36:29.18#ibcon#about to read 5, iclass 3, count 0 2006.225.07:36:29.18#ibcon#read 5, iclass 3, count 0 2006.225.07:36:29.18#ibcon#about to read 6, iclass 3, count 0 2006.225.07:36:29.18#ibcon#read 6, iclass 3, count 0 2006.225.07:36:29.18#ibcon#end of sib2, iclass 3, count 0 2006.225.07:36:29.18#ibcon#*after write, iclass 3, count 0 2006.225.07:36:29.18#ibcon#*before return 0, iclass 3, count 0 2006.225.07:36:29.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:36:29.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:36:29.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:36:29.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:36:29.18$vc4f8/valo=5,652.99 2006.225.07:36:29.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.07:36:29.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.07:36:29.18#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:29.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:36:29.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:36:29.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:36:29.18#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:36:29.18#ibcon#first serial, iclass 5, count 0 2006.225.07:36:29.18#ibcon#enter sib2, iclass 5, count 0 2006.225.07:36:29.18#ibcon#flushed, iclass 5, count 0 2006.225.07:36:29.18#ibcon#about to write, iclass 5, count 0 2006.225.07:36:29.18#ibcon#wrote, iclass 5, count 0 2006.225.07:36:29.18#ibcon#about to read 3, iclass 5, count 0 2006.225.07:36:29.20#ibcon#read 3, iclass 5, count 0 2006.225.07:36:29.20#ibcon#about to read 4, iclass 5, count 0 2006.225.07:36:29.20#ibcon#read 4, iclass 5, count 0 2006.225.07:36:29.20#ibcon#about to read 5, iclass 5, count 0 2006.225.07:36:29.20#ibcon#read 5, iclass 5, count 0 2006.225.07:36:29.20#ibcon#about to read 6, iclass 5, count 0 2006.225.07:36:29.20#ibcon#read 6, iclass 5, count 0 2006.225.07:36:29.20#ibcon#end of sib2, iclass 5, count 0 2006.225.07:36:29.20#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:36:29.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:36:29.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:36:29.20#ibcon#*before write, iclass 5, count 0 2006.225.07:36:29.20#ibcon#enter sib2, iclass 5, count 0 2006.225.07:36:29.20#ibcon#flushed, iclass 5, count 0 2006.225.07:36:29.20#ibcon#about to write, iclass 5, count 0 2006.225.07:36:29.20#ibcon#wrote, iclass 5, count 0 2006.225.07:36:29.20#ibcon#about to read 3, iclass 5, count 0 2006.225.07:36:29.24#ibcon#read 3, iclass 5, count 0 2006.225.07:36:29.24#ibcon#about to read 4, iclass 5, count 0 2006.225.07:36:29.24#ibcon#read 4, iclass 5, count 0 2006.225.07:36:29.24#ibcon#about to read 5, iclass 5, count 0 2006.225.07:36:29.24#ibcon#read 5, iclass 5, count 0 2006.225.07:36:29.24#ibcon#about to read 6, iclass 5, count 0 2006.225.07:36:29.24#ibcon#read 6, iclass 5, count 0 2006.225.07:36:29.24#ibcon#end of sib2, iclass 5, count 0 2006.225.07:36:29.24#ibcon#*after write, iclass 5, count 0 2006.225.07:36:29.24#ibcon#*before return 0, iclass 5, count 0 2006.225.07:36:29.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:36:29.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:36:29.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:36:29.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:36:29.24$vc4f8/va=5,7 2006.225.07:36:29.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.07:36:29.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.07:36:29.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:29.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:36:29.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:36:29.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:36:29.30#ibcon#enter wrdev, iclass 7, count 2 2006.225.07:36:29.30#ibcon#first serial, iclass 7, count 2 2006.225.07:36:29.30#ibcon#enter sib2, iclass 7, count 2 2006.225.07:36:29.30#ibcon#flushed, iclass 7, count 2 2006.225.07:36:29.30#ibcon#about to write, iclass 7, count 2 2006.225.07:36:29.30#ibcon#wrote, iclass 7, count 2 2006.225.07:36:29.30#ibcon#about to read 3, iclass 7, count 2 2006.225.07:36:29.32#ibcon#read 3, iclass 7, count 2 2006.225.07:36:29.32#ibcon#about to read 4, iclass 7, count 2 2006.225.07:36:29.32#ibcon#read 4, iclass 7, count 2 2006.225.07:36:29.32#ibcon#about to read 5, iclass 7, count 2 2006.225.07:36:29.32#ibcon#read 5, iclass 7, count 2 2006.225.07:36:29.32#ibcon#about to read 6, iclass 7, count 2 2006.225.07:36:29.32#ibcon#read 6, iclass 7, count 2 2006.225.07:36:29.32#ibcon#end of sib2, iclass 7, count 2 2006.225.07:36:29.32#ibcon#*mode == 0, iclass 7, count 2 2006.225.07:36:29.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.07:36:29.32#ibcon#[25=AT05-07\r\n] 2006.225.07:36:29.32#ibcon#*before write, iclass 7, count 2 2006.225.07:36:29.32#ibcon#enter sib2, iclass 7, count 2 2006.225.07:36:29.32#ibcon#flushed, iclass 7, count 2 2006.225.07:36:29.32#ibcon#about to write, iclass 7, count 2 2006.225.07:36:29.32#ibcon#wrote, iclass 7, count 2 2006.225.07:36:29.32#ibcon#about to read 3, iclass 7, count 2 2006.225.07:36:29.35#ibcon#read 3, iclass 7, count 2 2006.225.07:36:29.35#ibcon#about to read 4, iclass 7, count 2 2006.225.07:36:29.35#ibcon#read 4, iclass 7, count 2 2006.225.07:36:29.35#ibcon#about to read 5, iclass 7, count 2 2006.225.07:36:29.35#ibcon#read 5, iclass 7, count 2 2006.225.07:36:29.35#ibcon#about to read 6, iclass 7, count 2 2006.225.07:36:29.35#ibcon#read 6, iclass 7, count 2 2006.225.07:36:29.35#ibcon#end of sib2, iclass 7, count 2 2006.225.07:36:29.35#ibcon#*after write, iclass 7, count 2 2006.225.07:36:29.35#ibcon#*before return 0, iclass 7, count 2 2006.225.07:36:29.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:36:29.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:36:29.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.07:36:29.35#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:29.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:36:29.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:36:29.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:36:29.47#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:36:29.47#ibcon#first serial, iclass 7, count 0 2006.225.07:36:29.47#ibcon#enter sib2, iclass 7, count 0 2006.225.07:36:29.47#ibcon#flushed, iclass 7, count 0 2006.225.07:36:29.47#ibcon#about to write, iclass 7, count 0 2006.225.07:36:29.47#ibcon#wrote, iclass 7, count 0 2006.225.07:36:29.47#ibcon#about to read 3, iclass 7, count 0 2006.225.07:36:29.49#ibcon#read 3, iclass 7, count 0 2006.225.07:36:29.49#ibcon#about to read 4, iclass 7, count 0 2006.225.07:36:29.49#ibcon#read 4, iclass 7, count 0 2006.225.07:36:29.49#ibcon#about to read 5, iclass 7, count 0 2006.225.07:36:29.49#ibcon#read 5, iclass 7, count 0 2006.225.07:36:29.49#ibcon#about to read 6, iclass 7, count 0 2006.225.07:36:29.49#ibcon#read 6, iclass 7, count 0 2006.225.07:36:29.49#ibcon#end of sib2, iclass 7, count 0 2006.225.07:36:29.49#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:36:29.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:36:29.49#ibcon#[25=USB\r\n] 2006.225.07:36:29.49#ibcon#*before write, iclass 7, count 0 2006.225.07:36:29.49#ibcon#enter sib2, iclass 7, count 0 2006.225.07:36:29.49#ibcon#flushed, iclass 7, count 0 2006.225.07:36:29.49#ibcon#about to write, iclass 7, count 0 2006.225.07:36:29.49#ibcon#wrote, iclass 7, count 0 2006.225.07:36:29.49#ibcon#about to read 3, iclass 7, count 0 2006.225.07:36:29.52#ibcon#read 3, iclass 7, count 0 2006.225.07:36:29.52#ibcon#about to read 4, iclass 7, count 0 2006.225.07:36:29.52#ibcon#read 4, iclass 7, count 0 2006.225.07:36:29.52#ibcon#about to read 5, iclass 7, count 0 2006.225.07:36:29.52#ibcon#read 5, iclass 7, count 0 2006.225.07:36:29.52#ibcon#about to read 6, iclass 7, count 0 2006.225.07:36:29.52#ibcon#read 6, iclass 7, count 0 2006.225.07:36:29.52#ibcon#end of sib2, iclass 7, count 0 2006.225.07:36:29.52#ibcon#*after write, iclass 7, count 0 2006.225.07:36:29.52#ibcon#*before return 0, iclass 7, count 0 2006.225.07:36:29.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:36:29.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:36:29.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:36:29.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:36:29.52$vc4f8/valo=6,772.99 2006.225.07:36:29.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.07:36:29.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.07:36:29.52#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:29.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:36:29.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:36:29.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:36:29.52#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:36:29.52#ibcon#first serial, iclass 11, count 0 2006.225.07:36:29.52#ibcon#enter sib2, iclass 11, count 0 2006.225.07:36:29.52#ibcon#flushed, iclass 11, count 0 2006.225.07:36:29.52#ibcon#about to write, iclass 11, count 0 2006.225.07:36:29.52#ibcon#wrote, iclass 11, count 0 2006.225.07:36:29.52#ibcon#about to read 3, iclass 11, count 0 2006.225.07:36:29.54#ibcon#read 3, iclass 11, count 0 2006.225.07:36:29.54#ibcon#about to read 4, iclass 11, count 0 2006.225.07:36:29.54#ibcon#read 4, iclass 11, count 0 2006.225.07:36:29.54#ibcon#about to read 5, iclass 11, count 0 2006.225.07:36:29.54#ibcon#read 5, iclass 11, count 0 2006.225.07:36:29.54#ibcon#about to read 6, iclass 11, count 0 2006.225.07:36:29.54#ibcon#read 6, iclass 11, count 0 2006.225.07:36:29.54#ibcon#end of sib2, iclass 11, count 0 2006.225.07:36:29.54#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:36:29.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:36:29.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:36:29.54#ibcon#*before write, iclass 11, count 0 2006.225.07:36:29.54#ibcon#enter sib2, iclass 11, count 0 2006.225.07:36:29.54#ibcon#flushed, iclass 11, count 0 2006.225.07:36:29.54#ibcon#about to write, iclass 11, count 0 2006.225.07:36:29.54#ibcon#wrote, iclass 11, count 0 2006.225.07:36:29.54#ibcon#about to read 3, iclass 11, count 0 2006.225.07:36:29.58#ibcon#read 3, iclass 11, count 0 2006.225.07:36:29.58#ibcon#about to read 4, iclass 11, count 0 2006.225.07:36:29.58#ibcon#read 4, iclass 11, count 0 2006.225.07:36:29.58#ibcon#about to read 5, iclass 11, count 0 2006.225.07:36:29.58#ibcon#read 5, iclass 11, count 0 2006.225.07:36:29.58#ibcon#about to read 6, iclass 11, count 0 2006.225.07:36:29.58#ibcon#read 6, iclass 11, count 0 2006.225.07:36:29.58#ibcon#end of sib2, iclass 11, count 0 2006.225.07:36:29.58#ibcon#*after write, iclass 11, count 0 2006.225.07:36:29.58#ibcon#*before return 0, iclass 11, count 0 2006.225.07:36:29.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:36:29.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:36:29.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:36:29.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:36:29.58$vc4f8/va=6,6 2006.225.07:36:29.58#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.07:36:29.58#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.07:36:29.58#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:29.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:36:29.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:36:29.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:36:29.64#ibcon#enter wrdev, iclass 13, count 2 2006.225.07:36:29.64#ibcon#first serial, iclass 13, count 2 2006.225.07:36:29.64#ibcon#enter sib2, iclass 13, count 2 2006.225.07:36:29.64#ibcon#flushed, iclass 13, count 2 2006.225.07:36:29.64#ibcon#about to write, iclass 13, count 2 2006.225.07:36:29.64#ibcon#wrote, iclass 13, count 2 2006.225.07:36:29.64#ibcon#about to read 3, iclass 13, count 2 2006.225.07:36:29.66#ibcon#read 3, iclass 13, count 2 2006.225.07:36:29.66#ibcon#about to read 4, iclass 13, count 2 2006.225.07:36:29.66#ibcon#read 4, iclass 13, count 2 2006.225.07:36:29.66#ibcon#about to read 5, iclass 13, count 2 2006.225.07:36:29.66#ibcon#read 5, iclass 13, count 2 2006.225.07:36:29.66#ibcon#about to read 6, iclass 13, count 2 2006.225.07:36:29.66#ibcon#read 6, iclass 13, count 2 2006.225.07:36:29.66#ibcon#end of sib2, iclass 13, count 2 2006.225.07:36:29.66#ibcon#*mode == 0, iclass 13, count 2 2006.225.07:36:29.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.07:36:29.66#ibcon#[25=AT06-06\r\n] 2006.225.07:36:29.66#ibcon#*before write, iclass 13, count 2 2006.225.07:36:29.66#ibcon#enter sib2, iclass 13, count 2 2006.225.07:36:29.66#ibcon#flushed, iclass 13, count 2 2006.225.07:36:29.66#ibcon#about to write, iclass 13, count 2 2006.225.07:36:29.66#ibcon#wrote, iclass 13, count 2 2006.225.07:36:29.66#ibcon#about to read 3, iclass 13, count 2 2006.225.07:36:29.69#ibcon#read 3, iclass 13, count 2 2006.225.07:36:29.69#ibcon#about to read 4, iclass 13, count 2 2006.225.07:36:29.69#ibcon#read 4, iclass 13, count 2 2006.225.07:36:29.69#ibcon#about to read 5, iclass 13, count 2 2006.225.07:36:29.69#ibcon#read 5, iclass 13, count 2 2006.225.07:36:29.69#ibcon#about to read 6, iclass 13, count 2 2006.225.07:36:29.69#ibcon#read 6, iclass 13, count 2 2006.225.07:36:29.69#ibcon#end of sib2, iclass 13, count 2 2006.225.07:36:29.69#ibcon#*after write, iclass 13, count 2 2006.225.07:36:29.69#ibcon#*before return 0, iclass 13, count 2 2006.225.07:36:29.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:36:29.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:36:29.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.07:36:29.69#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:29.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:36:29.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:36:29.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:36:29.81#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:36:29.81#ibcon#first serial, iclass 13, count 0 2006.225.07:36:29.81#ibcon#enter sib2, iclass 13, count 0 2006.225.07:36:29.81#ibcon#flushed, iclass 13, count 0 2006.225.07:36:29.81#ibcon#about to write, iclass 13, count 0 2006.225.07:36:29.81#ibcon#wrote, iclass 13, count 0 2006.225.07:36:29.81#ibcon#about to read 3, iclass 13, count 0 2006.225.07:36:29.83#ibcon#read 3, iclass 13, count 0 2006.225.07:36:29.83#ibcon#about to read 4, iclass 13, count 0 2006.225.07:36:29.83#ibcon#read 4, iclass 13, count 0 2006.225.07:36:29.83#ibcon#about to read 5, iclass 13, count 0 2006.225.07:36:29.83#ibcon#read 5, iclass 13, count 0 2006.225.07:36:29.83#ibcon#about to read 6, iclass 13, count 0 2006.225.07:36:29.83#ibcon#read 6, iclass 13, count 0 2006.225.07:36:29.83#ibcon#end of sib2, iclass 13, count 0 2006.225.07:36:29.83#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:36:29.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:36:29.83#ibcon#[25=USB\r\n] 2006.225.07:36:29.83#ibcon#*before write, iclass 13, count 0 2006.225.07:36:29.83#ibcon#enter sib2, iclass 13, count 0 2006.225.07:36:29.83#ibcon#flushed, iclass 13, count 0 2006.225.07:36:29.83#ibcon#about to write, iclass 13, count 0 2006.225.07:36:29.83#ibcon#wrote, iclass 13, count 0 2006.225.07:36:29.83#ibcon#about to read 3, iclass 13, count 0 2006.225.07:36:29.86#ibcon#read 3, iclass 13, count 0 2006.225.07:36:29.86#ibcon#about to read 4, iclass 13, count 0 2006.225.07:36:29.86#ibcon#read 4, iclass 13, count 0 2006.225.07:36:29.86#ibcon#about to read 5, iclass 13, count 0 2006.225.07:36:29.86#ibcon#read 5, iclass 13, count 0 2006.225.07:36:29.86#ibcon#about to read 6, iclass 13, count 0 2006.225.07:36:29.86#ibcon#read 6, iclass 13, count 0 2006.225.07:36:29.86#ibcon#end of sib2, iclass 13, count 0 2006.225.07:36:29.86#ibcon#*after write, iclass 13, count 0 2006.225.07:36:29.86#ibcon#*before return 0, iclass 13, count 0 2006.225.07:36:29.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:36:29.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:36:29.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:36:29.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:36:29.86$vc4f8/valo=7,832.99 2006.225.07:36:29.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.07:36:29.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.07:36:29.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:29.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:36:29.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:36:29.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:36:29.86#ibcon#enter wrdev, iclass 15, count 0 2006.225.07:36:29.86#ibcon#first serial, iclass 15, count 0 2006.225.07:36:29.86#ibcon#enter sib2, iclass 15, count 0 2006.225.07:36:29.86#ibcon#flushed, iclass 15, count 0 2006.225.07:36:29.86#ibcon#about to write, iclass 15, count 0 2006.225.07:36:29.86#ibcon#wrote, iclass 15, count 0 2006.225.07:36:29.86#ibcon#about to read 3, iclass 15, count 0 2006.225.07:36:29.88#ibcon#read 3, iclass 15, count 0 2006.225.07:36:29.88#ibcon#about to read 4, iclass 15, count 0 2006.225.07:36:29.88#ibcon#read 4, iclass 15, count 0 2006.225.07:36:29.88#ibcon#about to read 5, iclass 15, count 0 2006.225.07:36:29.88#ibcon#read 5, iclass 15, count 0 2006.225.07:36:29.88#ibcon#about to read 6, iclass 15, count 0 2006.225.07:36:29.88#ibcon#read 6, iclass 15, count 0 2006.225.07:36:29.88#ibcon#end of sib2, iclass 15, count 0 2006.225.07:36:29.88#ibcon#*mode == 0, iclass 15, count 0 2006.225.07:36:29.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.07:36:29.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:36:29.88#ibcon#*before write, iclass 15, count 0 2006.225.07:36:29.88#ibcon#enter sib2, iclass 15, count 0 2006.225.07:36:29.88#ibcon#flushed, iclass 15, count 0 2006.225.07:36:29.88#ibcon#about to write, iclass 15, count 0 2006.225.07:36:29.88#ibcon#wrote, iclass 15, count 0 2006.225.07:36:29.88#ibcon#about to read 3, iclass 15, count 0 2006.225.07:36:29.92#ibcon#read 3, iclass 15, count 0 2006.225.07:36:29.92#ibcon#about to read 4, iclass 15, count 0 2006.225.07:36:29.92#ibcon#read 4, iclass 15, count 0 2006.225.07:36:29.92#ibcon#about to read 5, iclass 15, count 0 2006.225.07:36:29.92#ibcon#read 5, iclass 15, count 0 2006.225.07:36:29.92#ibcon#about to read 6, iclass 15, count 0 2006.225.07:36:29.92#ibcon#read 6, iclass 15, count 0 2006.225.07:36:29.92#ibcon#end of sib2, iclass 15, count 0 2006.225.07:36:29.92#ibcon#*after write, iclass 15, count 0 2006.225.07:36:29.92#ibcon#*before return 0, iclass 15, count 0 2006.225.07:36:29.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:36:29.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:36:29.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.07:36:29.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.07:36:29.92$vc4f8/va=7,6 2006.225.07:36:29.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.07:36:29.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.07:36:29.92#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:29.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:36:29.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:36:29.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:36:29.98#ibcon#enter wrdev, iclass 17, count 2 2006.225.07:36:29.98#ibcon#first serial, iclass 17, count 2 2006.225.07:36:29.98#ibcon#enter sib2, iclass 17, count 2 2006.225.07:36:29.98#ibcon#flushed, iclass 17, count 2 2006.225.07:36:29.98#ibcon#about to write, iclass 17, count 2 2006.225.07:36:29.98#ibcon#wrote, iclass 17, count 2 2006.225.07:36:29.98#ibcon#about to read 3, iclass 17, count 2 2006.225.07:36:30.00#ibcon#read 3, iclass 17, count 2 2006.225.07:36:30.00#ibcon#about to read 4, iclass 17, count 2 2006.225.07:36:30.00#ibcon#read 4, iclass 17, count 2 2006.225.07:36:30.00#ibcon#about to read 5, iclass 17, count 2 2006.225.07:36:30.00#ibcon#read 5, iclass 17, count 2 2006.225.07:36:30.00#ibcon#about to read 6, iclass 17, count 2 2006.225.07:36:30.00#ibcon#read 6, iclass 17, count 2 2006.225.07:36:30.00#ibcon#end of sib2, iclass 17, count 2 2006.225.07:36:30.00#ibcon#*mode == 0, iclass 17, count 2 2006.225.07:36:30.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.07:36:30.00#ibcon#[25=AT07-06\r\n] 2006.225.07:36:30.00#ibcon#*before write, iclass 17, count 2 2006.225.07:36:30.00#ibcon#enter sib2, iclass 17, count 2 2006.225.07:36:30.00#ibcon#flushed, iclass 17, count 2 2006.225.07:36:30.00#ibcon#about to write, iclass 17, count 2 2006.225.07:36:30.00#ibcon#wrote, iclass 17, count 2 2006.225.07:36:30.00#ibcon#about to read 3, iclass 17, count 2 2006.225.07:36:30.03#ibcon#read 3, iclass 17, count 2 2006.225.07:36:30.03#ibcon#about to read 4, iclass 17, count 2 2006.225.07:36:30.03#ibcon#read 4, iclass 17, count 2 2006.225.07:36:30.03#ibcon#about to read 5, iclass 17, count 2 2006.225.07:36:30.03#ibcon#read 5, iclass 17, count 2 2006.225.07:36:30.03#ibcon#about to read 6, iclass 17, count 2 2006.225.07:36:30.03#ibcon#read 6, iclass 17, count 2 2006.225.07:36:30.03#ibcon#end of sib2, iclass 17, count 2 2006.225.07:36:30.03#ibcon#*after write, iclass 17, count 2 2006.225.07:36:30.03#ibcon#*before return 0, iclass 17, count 2 2006.225.07:36:30.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:36:30.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:36:30.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.07:36:30.03#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:30.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:36:30.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:36:30.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:36:30.15#ibcon#enter wrdev, iclass 17, count 0 2006.225.07:36:30.15#ibcon#first serial, iclass 17, count 0 2006.225.07:36:30.15#ibcon#enter sib2, iclass 17, count 0 2006.225.07:36:30.15#ibcon#flushed, iclass 17, count 0 2006.225.07:36:30.15#ibcon#about to write, iclass 17, count 0 2006.225.07:36:30.15#ibcon#wrote, iclass 17, count 0 2006.225.07:36:30.15#ibcon#about to read 3, iclass 17, count 0 2006.225.07:36:30.17#ibcon#read 3, iclass 17, count 0 2006.225.07:36:30.17#ibcon#about to read 4, iclass 17, count 0 2006.225.07:36:30.17#ibcon#read 4, iclass 17, count 0 2006.225.07:36:30.17#ibcon#about to read 5, iclass 17, count 0 2006.225.07:36:30.17#ibcon#read 5, iclass 17, count 0 2006.225.07:36:30.17#ibcon#about to read 6, iclass 17, count 0 2006.225.07:36:30.17#ibcon#read 6, iclass 17, count 0 2006.225.07:36:30.17#ibcon#end of sib2, iclass 17, count 0 2006.225.07:36:30.17#ibcon#*mode == 0, iclass 17, count 0 2006.225.07:36:30.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.07:36:30.17#ibcon#[25=USB\r\n] 2006.225.07:36:30.17#ibcon#*before write, iclass 17, count 0 2006.225.07:36:30.17#ibcon#enter sib2, iclass 17, count 0 2006.225.07:36:30.17#ibcon#flushed, iclass 17, count 0 2006.225.07:36:30.17#ibcon#about to write, iclass 17, count 0 2006.225.07:36:30.17#ibcon#wrote, iclass 17, count 0 2006.225.07:36:30.17#ibcon#about to read 3, iclass 17, count 0 2006.225.07:36:30.20#ibcon#read 3, iclass 17, count 0 2006.225.07:36:30.20#ibcon#about to read 4, iclass 17, count 0 2006.225.07:36:30.20#ibcon#read 4, iclass 17, count 0 2006.225.07:36:30.20#ibcon#about to read 5, iclass 17, count 0 2006.225.07:36:30.20#ibcon#read 5, iclass 17, count 0 2006.225.07:36:30.20#ibcon#about to read 6, iclass 17, count 0 2006.225.07:36:30.20#ibcon#read 6, iclass 17, count 0 2006.225.07:36:30.20#ibcon#end of sib2, iclass 17, count 0 2006.225.07:36:30.20#ibcon#*after write, iclass 17, count 0 2006.225.07:36:30.20#ibcon#*before return 0, iclass 17, count 0 2006.225.07:36:30.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:36:30.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:36:30.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.07:36:30.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.07:36:30.20$vc4f8/valo=8,852.99 2006.225.07:36:30.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.07:36:30.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.07:36:30.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:30.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:36:30.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:36:30.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:36:30.20#ibcon#enter wrdev, iclass 19, count 0 2006.225.07:36:30.20#ibcon#first serial, iclass 19, count 0 2006.225.07:36:30.20#ibcon#enter sib2, iclass 19, count 0 2006.225.07:36:30.20#ibcon#flushed, iclass 19, count 0 2006.225.07:36:30.20#ibcon#about to write, iclass 19, count 0 2006.225.07:36:30.20#ibcon#wrote, iclass 19, count 0 2006.225.07:36:30.20#ibcon#about to read 3, iclass 19, count 0 2006.225.07:36:30.22#ibcon#read 3, iclass 19, count 0 2006.225.07:36:30.22#ibcon#about to read 4, iclass 19, count 0 2006.225.07:36:30.22#ibcon#read 4, iclass 19, count 0 2006.225.07:36:30.22#ibcon#about to read 5, iclass 19, count 0 2006.225.07:36:30.22#ibcon#read 5, iclass 19, count 0 2006.225.07:36:30.22#ibcon#about to read 6, iclass 19, count 0 2006.225.07:36:30.22#ibcon#read 6, iclass 19, count 0 2006.225.07:36:30.22#ibcon#end of sib2, iclass 19, count 0 2006.225.07:36:30.22#ibcon#*mode == 0, iclass 19, count 0 2006.225.07:36:30.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.07:36:30.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:36:30.22#ibcon#*before write, iclass 19, count 0 2006.225.07:36:30.22#ibcon#enter sib2, iclass 19, count 0 2006.225.07:36:30.22#ibcon#flushed, iclass 19, count 0 2006.225.07:36:30.22#ibcon#about to write, iclass 19, count 0 2006.225.07:36:30.22#ibcon#wrote, iclass 19, count 0 2006.225.07:36:30.22#ibcon#about to read 3, iclass 19, count 0 2006.225.07:36:30.26#ibcon#read 3, iclass 19, count 0 2006.225.07:36:30.26#ibcon#about to read 4, iclass 19, count 0 2006.225.07:36:30.26#ibcon#read 4, iclass 19, count 0 2006.225.07:36:30.26#ibcon#about to read 5, iclass 19, count 0 2006.225.07:36:30.26#ibcon#read 5, iclass 19, count 0 2006.225.07:36:30.26#ibcon#about to read 6, iclass 19, count 0 2006.225.07:36:30.26#ibcon#read 6, iclass 19, count 0 2006.225.07:36:30.26#ibcon#end of sib2, iclass 19, count 0 2006.225.07:36:30.26#ibcon#*after write, iclass 19, count 0 2006.225.07:36:30.26#ibcon#*before return 0, iclass 19, count 0 2006.225.07:36:30.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:36:30.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:36:30.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.07:36:30.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.07:36:30.26$vc4f8/va=8,7 2006.225.07:36:30.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.225.07:36:30.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.225.07:36:30.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:30.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:36:30.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:36:30.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:36:30.32#ibcon#enter wrdev, iclass 21, count 2 2006.225.07:36:30.32#ibcon#first serial, iclass 21, count 2 2006.225.07:36:30.32#ibcon#enter sib2, iclass 21, count 2 2006.225.07:36:30.32#ibcon#flushed, iclass 21, count 2 2006.225.07:36:30.32#ibcon#about to write, iclass 21, count 2 2006.225.07:36:30.32#ibcon#wrote, iclass 21, count 2 2006.225.07:36:30.32#ibcon#about to read 3, iclass 21, count 2 2006.225.07:36:30.34#ibcon#read 3, iclass 21, count 2 2006.225.07:36:30.34#ibcon#about to read 4, iclass 21, count 2 2006.225.07:36:30.34#ibcon#read 4, iclass 21, count 2 2006.225.07:36:30.34#ibcon#about to read 5, iclass 21, count 2 2006.225.07:36:30.34#ibcon#read 5, iclass 21, count 2 2006.225.07:36:30.34#ibcon#about to read 6, iclass 21, count 2 2006.225.07:36:30.34#ibcon#read 6, iclass 21, count 2 2006.225.07:36:30.34#ibcon#end of sib2, iclass 21, count 2 2006.225.07:36:30.34#ibcon#*mode == 0, iclass 21, count 2 2006.225.07:36:30.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.225.07:36:30.34#ibcon#[25=AT08-07\r\n] 2006.225.07:36:30.34#ibcon#*before write, iclass 21, count 2 2006.225.07:36:30.34#ibcon#enter sib2, iclass 21, count 2 2006.225.07:36:30.34#ibcon#flushed, iclass 21, count 2 2006.225.07:36:30.34#ibcon#about to write, iclass 21, count 2 2006.225.07:36:30.34#ibcon#wrote, iclass 21, count 2 2006.225.07:36:30.34#ibcon#about to read 3, iclass 21, count 2 2006.225.07:36:30.37#ibcon#read 3, iclass 21, count 2 2006.225.07:36:30.37#ibcon#about to read 4, iclass 21, count 2 2006.225.07:36:30.37#ibcon#read 4, iclass 21, count 2 2006.225.07:36:30.37#ibcon#about to read 5, iclass 21, count 2 2006.225.07:36:30.37#ibcon#read 5, iclass 21, count 2 2006.225.07:36:30.37#ibcon#about to read 6, iclass 21, count 2 2006.225.07:36:30.37#ibcon#read 6, iclass 21, count 2 2006.225.07:36:30.37#ibcon#end of sib2, iclass 21, count 2 2006.225.07:36:30.37#ibcon#*after write, iclass 21, count 2 2006.225.07:36:30.37#ibcon#*before return 0, iclass 21, count 2 2006.225.07:36:30.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:36:30.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:36:30.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.225.07:36:30.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:30.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:36:30.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:36:30.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:36:30.49#ibcon#enter wrdev, iclass 21, count 0 2006.225.07:36:30.49#ibcon#first serial, iclass 21, count 0 2006.225.07:36:30.49#ibcon#enter sib2, iclass 21, count 0 2006.225.07:36:30.49#ibcon#flushed, iclass 21, count 0 2006.225.07:36:30.49#ibcon#about to write, iclass 21, count 0 2006.225.07:36:30.49#ibcon#wrote, iclass 21, count 0 2006.225.07:36:30.49#ibcon#about to read 3, iclass 21, count 0 2006.225.07:36:30.51#ibcon#read 3, iclass 21, count 0 2006.225.07:36:30.51#ibcon#about to read 4, iclass 21, count 0 2006.225.07:36:30.51#ibcon#read 4, iclass 21, count 0 2006.225.07:36:30.51#ibcon#about to read 5, iclass 21, count 0 2006.225.07:36:30.51#ibcon#read 5, iclass 21, count 0 2006.225.07:36:30.51#ibcon#about to read 6, iclass 21, count 0 2006.225.07:36:30.51#ibcon#read 6, iclass 21, count 0 2006.225.07:36:30.51#ibcon#end of sib2, iclass 21, count 0 2006.225.07:36:30.51#ibcon#*mode == 0, iclass 21, count 0 2006.225.07:36:30.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.07:36:30.51#ibcon#[25=USB\r\n] 2006.225.07:36:30.51#ibcon#*before write, iclass 21, count 0 2006.225.07:36:30.51#ibcon#enter sib2, iclass 21, count 0 2006.225.07:36:30.51#ibcon#flushed, iclass 21, count 0 2006.225.07:36:30.51#ibcon#about to write, iclass 21, count 0 2006.225.07:36:30.51#ibcon#wrote, iclass 21, count 0 2006.225.07:36:30.51#ibcon#about to read 3, iclass 21, count 0 2006.225.07:36:30.54#ibcon#read 3, iclass 21, count 0 2006.225.07:36:30.54#ibcon#about to read 4, iclass 21, count 0 2006.225.07:36:30.54#ibcon#read 4, iclass 21, count 0 2006.225.07:36:30.54#ibcon#about to read 5, iclass 21, count 0 2006.225.07:36:30.54#ibcon#read 5, iclass 21, count 0 2006.225.07:36:30.54#ibcon#about to read 6, iclass 21, count 0 2006.225.07:36:30.54#ibcon#read 6, iclass 21, count 0 2006.225.07:36:30.54#ibcon#end of sib2, iclass 21, count 0 2006.225.07:36:30.54#ibcon#*after write, iclass 21, count 0 2006.225.07:36:30.54#ibcon#*before return 0, iclass 21, count 0 2006.225.07:36:30.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:36:30.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:36:30.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.07:36:30.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.07:36:30.54$vc4f8/vblo=1,632.99 2006.225.07:36:30.54#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.225.07:36:30.54#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.225.07:36:30.54#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:30.54#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:36:30.54#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:36:30.54#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:36:30.54#ibcon#enter wrdev, iclass 23, count 0 2006.225.07:36:30.54#ibcon#first serial, iclass 23, count 0 2006.225.07:36:30.54#ibcon#enter sib2, iclass 23, count 0 2006.225.07:36:30.54#ibcon#flushed, iclass 23, count 0 2006.225.07:36:30.54#ibcon#about to write, iclass 23, count 0 2006.225.07:36:30.54#ibcon#wrote, iclass 23, count 0 2006.225.07:36:30.54#ibcon#about to read 3, iclass 23, count 0 2006.225.07:36:30.56#ibcon#read 3, iclass 23, count 0 2006.225.07:36:30.56#ibcon#about to read 4, iclass 23, count 0 2006.225.07:36:30.56#ibcon#read 4, iclass 23, count 0 2006.225.07:36:30.56#ibcon#about to read 5, iclass 23, count 0 2006.225.07:36:30.56#ibcon#read 5, iclass 23, count 0 2006.225.07:36:30.56#ibcon#about to read 6, iclass 23, count 0 2006.225.07:36:30.56#ibcon#read 6, iclass 23, count 0 2006.225.07:36:30.56#ibcon#end of sib2, iclass 23, count 0 2006.225.07:36:30.56#ibcon#*mode == 0, iclass 23, count 0 2006.225.07:36:30.56#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.07:36:30.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:36:30.56#ibcon#*before write, iclass 23, count 0 2006.225.07:36:30.56#ibcon#enter sib2, iclass 23, count 0 2006.225.07:36:30.56#ibcon#flushed, iclass 23, count 0 2006.225.07:36:30.56#ibcon#about to write, iclass 23, count 0 2006.225.07:36:30.56#ibcon#wrote, iclass 23, count 0 2006.225.07:36:30.56#ibcon#about to read 3, iclass 23, count 0 2006.225.07:36:30.60#ibcon#read 3, iclass 23, count 0 2006.225.07:36:30.60#ibcon#about to read 4, iclass 23, count 0 2006.225.07:36:30.60#ibcon#read 4, iclass 23, count 0 2006.225.07:36:30.60#ibcon#about to read 5, iclass 23, count 0 2006.225.07:36:30.60#ibcon#read 5, iclass 23, count 0 2006.225.07:36:30.60#ibcon#about to read 6, iclass 23, count 0 2006.225.07:36:30.60#ibcon#read 6, iclass 23, count 0 2006.225.07:36:30.60#ibcon#end of sib2, iclass 23, count 0 2006.225.07:36:30.60#ibcon#*after write, iclass 23, count 0 2006.225.07:36:30.60#ibcon#*before return 0, iclass 23, count 0 2006.225.07:36:30.60#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:36:30.60#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:36:30.60#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.07:36:30.60#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.07:36:30.61$vc4f8/vb=1,4 2006.225.07:36:30.61#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.225.07:36:30.61#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.225.07:36:30.61#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:30.61#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:36:30.61#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:36:30.61#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:36:30.61#ibcon#enter wrdev, iclass 25, count 2 2006.225.07:36:30.61#ibcon#first serial, iclass 25, count 2 2006.225.07:36:30.61#ibcon#enter sib2, iclass 25, count 2 2006.225.07:36:30.61#ibcon#flushed, iclass 25, count 2 2006.225.07:36:30.61#ibcon#about to write, iclass 25, count 2 2006.225.07:36:30.61#ibcon#wrote, iclass 25, count 2 2006.225.07:36:30.61#ibcon#about to read 3, iclass 25, count 2 2006.225.07:36:30.62#ibcon#read 3, iclass 25, count 2 2006.225.07:36:30.62#ibcon#about to read 4, iclass 25, count 2 2006.225.07:36:30.62#ibcon#read 4, iclass 25, count 2 2006.225.07:36:30.62#ibcon#about to read 5, iclass 25, count 2 2006.225.07:36:30.62#ibcon#read 5, iclass 25, count 2 2006.225.07:36:30.62#ibcon#about to read 6, iclass 25, count 2 2006.225.07:36:30.62#ibcon#read 6, iclass 25, count 2 2006.225.07:36:30.62#ibcon#end of sib2, iclass 25, count 2 2006.225.07:36:30.62#ibcon#*mode == 0, iclass 25, count 2 2006.225.07:36:30.62#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.225.07:36:30.62#ibcon#[27=AT01-04\r\n] 2006.225.07:36:30.62#ibcon#*before write, iclass 25, count 2 2006.225.07:36:30.62#ibcon#enter sib2, iclass 25, count 2 2006.225.07:36:30.62#ibcon#flushed, iclass 25, count 2 2006.225.07:36:30.62#ibcon#about to write, iclass 25, count 2 2006.225.07:36:30.62#ibcon#wrote, iclass 25, count 2 2006.225.07:36:30.62#ibcon#about to read 3, iclass 25, count 2 2006.225.07:36:30.65#ibcon#read 3, iclass 25, count 2 2006.225.07:36:30.65#ibcon#about to read 4, iclass 25, count 2 2006.225.07:36:30.65#ibcon#read 4, iclass 25, count 2 2006.225.07:36:30.65#ibcon#about to read 5, iclass 25, count 2 2006.225.07:36:30.65#ibcon#read 5, iclass 25, count 2 2006.225.07:36:30.65#ibcon#about to read 6, iclass 25, count 2 2006.225.07:36:30.65#ibcon#read 6, iclass 25, count 2 2006.225.07:36:30.65#ibcon#end of sib2, iclass 25, count 2 2006.225.07:36:30.65#ibcon#*after write, iclass 25, count 2 2006.225.07:36:30.65#ibcon#*before return 0, iclass 25, count 2 2006.225.07:36:30.65#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:36:30.65#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:36:30.65#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.225.07:36:30.65#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:30.65#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:36:30.77#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:36:30.77#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:36:30.77#ibcon#enter wrdev, iclass 25, count 0 2006.225.07:36:30.77#ibcon#first serial, iclass 25, count 0 2006.225.07:36:30.77#ibcon#enter sib2, iclass 25, count 0 2006.225.07:36:30.77#ibcon#flushed, iclass 25, count 0 2006.225.07:36:30.77#ibcon#about to write, iclass 25, count 0 2006.225.07:36:30.77#ibcon#wrote, iclass 25, count 0 2006.225.07:36:30.77#ibcon#about to read 3, iclass 25, count 0 2006.225.07:36:30.79#ibcon#read 3, iclass 25, count 0 2006.225.07:36:30.79#ibcon#about to read 4, iclass 25, count 0 2006.225.07:36:30.79#ibcon#read 4, iclass 25, count 0 2006.225.07:36:30.79#ibcon#about to read 5, iclass 25, count 0 2006.225.07:36:30.79#ibcon#read 5, iclass 25, count 0 2006.225.07:36:30.79#ibcon#about to read 6, iclass 25, count 0 2006.225.07:36:30.79#ibcon#read 6, iclass 25, count 0 2006.225.07:36:30.79#ibcon#end of sib2, iclass 25, count 0 2006.225.07:36:30.79#ibcon#*mode == 0, iclass 25, count 0 2006.225.07:36:30.79#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.07:36:30.79#ibcon#[27=USB\r\n] 2006.225.07:36:30.79#ibcon#*before write, iclass 25, count 0 2006.225.07:36:30.79#ibcon#enter sib2, iclass 25, count 0 2006.225.07:36:30.79#ibcon#flushed, iclass 25, count 0 2006.225.07:36:30.79#ibcon#about to write, iclass 25, count 0 2006.225.07:36:30.79#ibcon#wrote, iclass 25, count 0 2006.225.07:36:30.79#ibcon#about to read 3, iclass 25, count 0 2006.225.07:36:30.82#ibcon#read 3, iclass 25, count 0 2006.225.07:36:30.82#ibcon#about to read 4, iclass 25, count 0 2006.225.07:36:30.82#ibcon#read 4, iclass 25, count 0 2006.225.07:36:30.82#ibcon#about to read 5, iclass 25, count 0 2006.225.07:36:30.82#ibcon#read 5, iclass 25, count 0 2006.225.07:36:30.82#ibcon#about to read 6, iclass 25, count 0 2006.225.07:36:30.82#ibcon#read 6, iclass 25, count 0 2006.225.07:36:30.82#ibcon#end of sib2, iclass 25, count 0 2006.225.07:36:30.82#ibcon#*after write, iclass 25, count 0 2006.225.07:36:30.82#ibcon#*before return 0, iclass 25, count 0 2006.225.07:36:30.82#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:36:30.82#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:36:30.82#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.07:36:30.82#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.07:36:30.82$vc4f8/vblo=2,640.99 2006.225.07:36:30.82#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.07:36:30.82#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.07:36:30.82#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:30.82#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:36:30.82#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:36:30.82#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:36:30.82#ibcon#enter wrdev, iclass 27, count 0 2006.225.07:36:30.82#ibcon#first serial, iclass 27, count 0 2006.225.07:36:30.82#ibcon#enter sib2, iclass 27, count 0 2006.225.07:36:30.82#ibcon#flushed, iclass 27, count 0 2006.225.07:36:30.82#ibcon#about to write, iclass 27, count 0 2006.225.07:36:30.82#ibcon#wrote, iclass 27, count 0 2006.225.07:36:30.82#ibcon#about to read 3, iclass 27, count 0 2006.225.07:36:30.84#ibcon#read 3, iclass 27, count 0 2006.225.07:36:30.84#ibcon#about to read 4, iclass 27, count 0 2006.225.07:36:30.84#ibcon#read 4, iclass 27, count 0 2006.225.07:36:30.84#ibcon#about to read 5, iclass 27, count 0 2006.225.07:36:30.84#ibcon#read 5, iclass 27, count 0 2006.225.07:36:30.84#ibcon#about to read 6, iclass 27, count 0 2006.225.07:36:30.84#ibcon#read 6, iclass 27, count 0 2006.225.07:36:30.84#ibcon#end of sib2, iclass 27, count 0 2006.225.07:36:30.84#ibcon#*mode == 0, iclass 27, count 0 2006.225.07:36:30.84#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.07:36:30.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:36:30.84#ibcon#*before write, iclass 27, count 0 2006.225.07:36:30.84#ibcon#enter sib2, iclass 27, count 0 2006.225.07:36:30.84#ibcon#flushed, iclass 27, count 0 2006.225.07:36:30.84#ibcon#about to write, iclass 27, count 0 2006.225.07:36:30.84#ibcon#wrote, iclass 27, count 0 2006.225.07:36:30.84#ibcon#about to read 3, iclass 27, count 0 2006.225.07:36:30.88#ibcon#read 3, iclass 27, count 0 2006.225.07:36:30.88#ibcon#about to read 4, iclass 27, count 0 2006.225.07:36:30.88#ibcon#read 4, iclass 27, count 0 2006.225.07:36:30.88#ibcon#about to read 5, iclass 27, count 0 2006.225.07:36:30.88#ibcon#read 5, iclass 27, count 0 2006.225.07:36:30.88#ibcon#about to read 6, iclass 27, count 0 2006.225.07:36:30.88#ibcon#read 6, iclass 27, count 0 2006.225.07:36:30.88#ibcon#end of sib2, iclass 27, count 0 2006.225.07:36:30.88#ibcon#*after write, iclass 27, count 0 2006.225.07:36:30.88#ibcon#*before return 0, iclass 27, count 0 2006.225.07:36:30.88#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:36:30.88#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:36:30.88#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.07:36:30.88#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.07:36:30.88$vc4f8/vb=2,4 2006.225.07:36:30.88#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.225.07:36:30.88#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.225.07:36:30.88#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:30.88#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:36:30.94#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:36:30.94#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:36:30.94#ibcon#enter wrdev, iclass 29, count 2 2006.225.07:36:30.94#ibcon#first serial, iclass 29, count 2 2006.225.07:36:30.94#ibcon#enter sib2, iclass 29, count 2 2006.225.07:36:30.94#ibcon#flushed, iclass 29, count 2 2006.225.07:36:30.94#ibcon#about to write, iclass 29, count 2 2006.225.07:36:30.94#ibcon#wrote, iclass 29, count 2 2006.225.07:36:30.94#ibcon#about to read 3, iclass 29, count 2 2006.225.07:36:30.96#ibcon#read 3, iclass 29, count 2 2006.225.07:36:30.96#ibcon#about to read 4, iclass 29, count 2 2006.225.07:36:30.96#ibcon#read 4, iclass 29, count 2 2006.225.07:36:30.96#ibcon#about to read 5, iclass 29, count 2 2006.225.07:36:30.96#ibcon#read 5, iclass 29, count 2 2006.225.07:36:30.96#ibcon#about to read 6, iclass 29, count 2 2006.225.07:36:30.96#ibcon#read 6, iclass 29, count 2 2006.225.07:36:30.96#ibcon#end of sib2, iclass 29, count 2 2006.225.07:36:30.96#ibcon#*mode == 0, iclass 29, count 2 2006.225.07:36:30.96#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.225.07:36:30.96#ibcon#[27=AT02-04\r\n] 2006.225.07:36:30.96#ibcon#*before write, iclass 29, count 2 2006.225.07:36:30.96#ibcon#enter sib2, iclass 29, count 2 2006.225.07:36:30.96#ibcon#flushed, iclass 29, count 2 2006.225.07:36:30.96#ibcon#about to write, iclass 29, count 2 2006.225.07:36:30.96#ibcon#wrote, iclass 29, count 2 2006.225.07:36:30.96#ibcon#about to read 3, iclass 29, count 2 2006.225.07:36:30.99#ibcon#read 3, iclass 29, count 2 2006.225.07:36:30.99#ibcon#about to read 4, iclass 29, count 2 2006.225.07:36:30.99#ibcon#read 4, iclass 29, count 2 2006.225.07:36:30.99#ibcon#about to read 5, iclass 29, count 2 2006.225.07:36:30.99#ibcon#read 5, iclass 29, count 2 2006.225.07:36:30.99#ibcon#about to read 6, iclass 29, count 2 2006.225.07:36:30.99#ibcon#read 6, iclass 29, count 2 2006.225.07:36:30.99#ibcon#end of sib2, iclass 29, count 2 2006.225.07:36:30.99#ibcon#*after write, iclass 29, count 2 2006.225.07:36:30.99#ibcon#*before return 0, iclass 29, count 2 2006.225.07:36:30.99#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:36:30.99#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:36:30.99#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.225.07:36:30.99#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:30.99#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:36:31.11#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:36:31.11#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:36:31.11#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:36:31.11#ibcon#first serial, iclass 29, count 0 2006.225.07:36:31.11#ibcon#enter sib2, iclass 29, count 0 2006.225.07:36:31.11#ibcon#flushed, iclass 29, count 0 2006.225.07:36:31.11#ibcon#about to write, iclass 29, count 0 2006.225.07:36:31.11#ibcon#wrote, iclass 29, count 0 2006.225.07:36:31.11#ibcon#about to read 3, iclass 29, count 0 2006.225.07:36:31.13#ibcon#read 3, iclass 29, count 0 2006.225.07:36:31.13#ibcon#about to read 4, iclass 29, count 0 2006.225.07:36:31.13#ibcon#read 4, iclass 29, count 0 2006.225.07:36:31.13#ibcon#about to read 5, iclass 29, count 0 2006.225.07:36:31.13#ibcon#read 5, iclass 29, count 0 2006.225.07:36:31.13#ibcon#about to read 6, iclass 29, count 0 2006.225.07:36:31.13#ibcon#read 6, iclass 29, count 0 2006.225.07:36:31.13#ibcon#end of sib2, iclass 29, count 0 2006.225.07:36:31.13#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:36:31.13#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:36:31.13#ibcon#[27=USB\r\n] 2006.225.07:36:31.13#ibcon#*before write, iclass 29, count 0 2006.225.07:36:31.13#ibcon#enter sib2, iclass 29, count 0 2006.225.07:36:31.13#ibcon#flushed, iclass 29, count 0 2006.225.07:36:31.13#ibcon#about to write, iclass 29, count 0 2006.225.07:36:31.13#ibcon#wrote, iclass 29, count 0 2006.225.07:36:31.13#ibcon#about to read 3, iclass 29, count 0 2006.225.07:36:31.16#ibcon#read 3, iclass 29, count 0 2006.225.07:36:31.16#ibcon#about to read 4, iclass 29, count 0 2006.225.07:36:31.16#ibcon#read 4, iclass 29, count 0 2006.225.07:36:31.16#ibcon#about to read 5, iclass 29, count 0 2006.225.07:36:31.16#ibcon#read 5, iclass 29, count 0 2006.225.07:36:31.16#ibcon#about to read 6, iclass 29, count 0 2006.225.07:36:31.16#ibcon#read 6, iclass 29, count 0 2006.225.07:36:31.16#ibcon#end of sib2, iclass 29, count 0 2006.225.07:36:31.16#ibcon#*after write, iclass 29, count 0 2006.225.07:36:31.16#ibcon#*before return 0, iclass 29, count 0 2006.225.07:36:31.16#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:36:31.16#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:36:31.16#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:36:31.16#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:36:31.16$vc4f8/vblo=3,656.99 2006.225.07:36:31.16#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.07:36:31.16#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.07:36:31.16#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:31.16#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:36:31.16#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:36:31.16#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:36:31.16#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:36:31.16#ibcon#first serial, iclass 31, count 0 2006.225.07:36:31.16#ibcon#enter sib2, iclass 31, count 0 2006.225.07:36:31.16#ibcon#flushed, iclass 31, count 0 2006.225.07:36:31.16#ibcon#about to write, iclass 31, count 0 2006.225.07:36:31.16#ibcon#wrote, iclass 31, count 0 2006.225.07:36:31.16#ibcon#about to read 3, iclass 31, count 0 2006.225.07:36:31.18#ibcon#read 3, iclass 31, count 0 2006.225.07:36:31.18#ibcon#about to read 4, iclass 31, count 0 2006.225.07:36:31.18#ibcon#read 4, iclass 31, count 0 2006.225.07:36:31.18#ibcon#about to read 5, iclass 31, count 0 2006.225.07:36:31.18#ibcon#read 5, iclass 31, count 0 2006.225.07:36:31.18#ibcon#about to read 6, iclass 31, count 0 2006.225.07:36:31.18#ibcon#read 6, iclass 31, count 0 2006.225.07:36:31.18#ibcon#end of sib2, iclass 31, count 0 2006.225.07:36:31.18#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:36:31.18#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:36:31.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:36:31.18#ibcon#*before write, iclass 31, count 0 2006.225.07:36:31.18#ibcon#enter sib2, iclass 31, count 0 2006.225.07:36:31.18#ibcon#flushed, iclass 31, count 0 2006.225.07:36:31.18#ibcon#about to write, iclass 31, count 0 2006.225.07:36:31.18#ibcon#wrote, iclass 31, count 0 2006.225.07:36:31.18#ibcon#about to read 3, iclass 31, count 0 2006.225.07:36:31.22#ibcon#read 3, iclass 31, count 0 2006.225.07:36:31.22#ibcon#about to read 4, iclass 31, count 0 2006.225.07:36:31.22#ibcon#read 4, iclass 31, count 0 2006.225.07:36:31.22#ibcon#about to read 5, iclass 31, count 0 2006.225.07:36:31.22#ibcon#read 5, iclass 31, count 0 2006.225.07:36:31.22#ibcon#about to read 6, iclass 31, count 0 2006.225.07:36:31.22#ibcon#read 6, iclass 31, count 0 2006.225.07:36:31.22#ibcon#end of sib2, iclass 31, count 0 2006.225.07:36:31.22#ibcon#*after write, iclass 31, count 0 2006.225.07:36:31.22#ibcon#*before return 0, iclass 31, count 0 2006.225.07:36:31.22#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:36:31.22#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:36:31.22#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:36:31.22#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:36:31.22$vc4f8/vb=3,4 2006.225.07:36:31.22#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.225.07:36:31.22#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.225.07:36:31.22#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:31.22#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:36:31.28#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:36:31.28#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:36:31.28#ibcon#enter wrdev, iclass 33, count 2 2006.225.07:36:31.28#ibcon#first serial, iclass 33, count 2 2006.225.07:36:31.28#ibcon#enter sib2, iclass 33, count 2 2006.225.07:36:31.28#ibcon#flushed, iclass 33, count 2 2006.225.07:36:31.28#ibcon#about to write, iclass 33, count 2 2006.225.07:36:31.28#ibcon#wrote, iclass 33, count 2 2006.225.07:36:31.28#ibcon#about to read 3, iclass 33, count 2 2006.225.07:36:31.30#ibcon#read 3, iclass 33, count 2 2006.225.07:36:31.30#ibcon#about to read 4, iclass 33, count 2 2006.225.07:36:31.30#ibcon#read 4, iclass 33, count 2 2006.225.07:36:31.30#ibcon#about to read 5, iclass 33, count 2 2006.225.07:36:31.30#ibcon#read 5, iclass 33, count 2 2006.225.07:36:31.30#ibcon#about to read 6, iclass 33, count 2 2006.225.07:36:31.30#ibcon#read 6, iclass 33, count 2 2006.225.07:36:31.30#ibcon#end of sib2, iclass 33, count 2 2006.225.07:36:31.30#ibcon#*mode == 0, iclass 33, count 2 2006.225.07:36:31.30#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.225.07:36:31.30#ibcon#[27=AT03-04\r\n] 2006.225.07:36:31.30#ibcon#*before write, iclass 33, count 2 2006.225.07:36:31.30#ibcon#enter sib2, iclass 33, count 2 2006.225.07:36:31.30#ibcon#flushed, iclass 33, count 2 2006.225.07:36:31.30#ibcon#about to write, iclass 33, count 2 2006.225.07:36:31.30#ibcon#wrote, iclass 33, count 2 2006.225.07:36:31.30#ibcon#about to read 3, iclass 33, count 2 2006.225.07:36:31.33#ibcon#read 3, iclass 33, count 2 2006.225.07:36:31.33#ibcon#about to read 4, iclass 33, count 2 2006.225.07:36:31.33#ibcon#read 4, iclass 33, count 2 2006.225.07:36:31.33#ibcon#about to read 5, iclass 33, count 2 2006.225.07:36:31.33#ibcon#read 5, iclass 33, count 2 2006.225.07:36:31.33#ibcon#about to read 6, iclass 33, count 2 2006.225.07:36:31.33#ibcon#read 6, iclass 33, count 2 2006.225.07:36:31.33#ibcon#end of sib2, iclass 33, count 2 2006.225.07:36:31.33#ibcon#*after write, iclass 33, count 2 2006.225.07:36:31.33#ibcon#*before return 0, iclass 33, count 2 2006.225.07:36:31.33#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:36:31.33#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:36:31.33#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.225.07:36:31.33#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:31.33#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:36:31.45#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:36:31.45#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:36:31.45#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:36:31.45#ibcon#first serial, iclass 33, count 0 2006.225.07:36:31.45#ibcon#enter sib2, iclass 33, count 0 2006.225.07:36:31.45#ibcon#flushed, iclass 33, count 0 2006.225.07:36:31.45#ibcon#about to write, iclass 33, count 0 2006.225.07:36:31.45#ibcon#wrote, iclass 33, count 0 2006.225.07:36:31.45#ibcon#about to read 3, iclass 33, count 0 2006.225.07:36:31.47#ibcon#read 3, iclass 33, count 0 2006.225.07:36:31.47#ibcon#about to read 4, iclass 33, count 0 2006.225.07:36:31.47#ibcon#read 4, iclass 33, count 0 2006.225.07:36:31.47#ibcon#about to read 5, iclass 33, count 0 2006.225.07:36:31.47#ibcon#read 5, iclass 33, count 0 2006.225.07:36:31.47#ibcon#about to read 6, iclass 33, count 0 2006.225.07:36:31.47#ibcon#read 6, iclass 33, count 0 2006.225.07:36:31.47#ibcon#end of sib2, iclass 33, count 0 2006.225.07:36:31.47#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:36:31.47#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:36:31.47#ibcon#[27=USB\r\n] 2006.225.07:36:31.47#ibcon#*before write, iclass 33, count 0 2006.225.07:36:31.47#ibcon#enter sib2, iclass 33, count 0 2006.225.07:36:31.47#ibcon#flushed, iclass 33, count 0 2006.225.07:36:31.47#ibcon#about to write, iclass 33, count 0 2006.225.07:36:31.47#ibcon#wrote, iclass 33, count 0 2006.225.07:36:31.47#ibcon#about to read 3, iclass 33, count 0 2006.225.07:36:31.50#ibcon#read 3, iclass 33, count 0 2006.225.07:36:31.50#ibcon#about to read 4, iclass 33, count 0 2006.225.07:36:31.50#ibcon#read 4, iclass 33, count 0 2006.225.07:36:31.50#ibcon#about to read 5, iclass 33, count 0 2006.225.07:36:31.50#ibcon#read 5, iclass 33, count 0 2006.225.07:36:31.50#ibcon#about to read 6, iclass 33, count 0 2006.225.07:36:31.50#ibcon#read 6, iclass 33, count 0 2006.225.07:36:31.50#ibcon#end of sib2, iclass 33, count 0 2006.225.07:36:31.50#ibcon#*after write, iclass 33, count 0 2006.225.07:36:31.50#ibcon#*before return 0, iclass 33, count 0 2006.225.07:36:31.50#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:36:31.50#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:36:31.50#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:36:31.50#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:36:31.50$vc4f8/vblo=4,712.99 2006.225.07:36:31.50#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.225.07:36:31.50#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.225.07:36:31.50#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:31.50#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:36:31.50#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:36:31.50#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:36:31.50#ibcon#enter wrdev, iclass 35, count 0 2006.225.07:36:31.50#ibcon#first serial, iclass 35, count 0 2006.225.07:36:31.50#ibcon#enter sib2, iclass 35, count 0 2006.225.07:36:31.50#ibcon#flushed, iclass 35, count 0 2006.225.07:36:31.50#ibcon#about to write, iclass 35, count 0 2006.225.07:36:31.50#ibcon#wrote, iclass 35, count 0 2006.225.07:36:31.50#ibcon#about to read 3, iclass 35, count 0 2006.225.07:36:31.53#ibcon#read 3, iclass 35, count 0 2006.225.07:36:31.53#ibcon#about to read 4, iclass 35, count 0 2006.225.07:36:31.53#ibcon#read 4, iclass 35, count 0 2006.225.07:36:31.53#ibcon#about to read 5, iclass 35, count 0 2006.225.07:36:31.53#ibcon#read 5, iclass 35, count 0 2006.225.07:36:31.53#ibcon#about to read 6, iclass 35, count 0 2006.225.07:36:31.53#ibcon#read 6, iclass 35, count 0 2006.225.07:36:31.53#ibcon#end of sib2, iclass 35, count 0 2006.225.07:36:31.53#ibcon#*mode == 0, iclass 35, count 0 2006.225.07:36:31.53#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.07:36:31.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:36:31.53#ibcon#*before write, iclass 35, count 0 2006.225.07:36:31.53#ibcon#enter sib2, iclass 35, count 0 2006.225.07:36:31.53#ibcon#flushed, iclass 35, count 0 2006.225.07:36:31.53#ibcon#about to write, iclass 35, count 0 2006.225.07:36:31.53#ibcon#wrote, iclass 35, count 0 2006.225.07:36:31.53#ibcon#about to read 3, iclass 35, count 0 2006.225.07:36:31.57#ibcon#read 3, iclass 35, count 0 2006.225.07:36:31.57#ibcon#about to read 4, iclass 35, count 0 2006.225.07:36:31.57#ibcon#read 4, iclass 35, count 0 2006.225.07:36:31.57#ibcon#about to read 5, iclass 35, count 0 2006.225.07:36:31.57#ibcon#read 5, iclass 35, count 0 2006.225.07:36:31.57#ibcon#about to read 6, iclass 35, count 0 2006.225.07:36:31.57#ibcon#read 6, iclass 35, count 0 2006.225.07:36:31.57#ibcon#end of sib2, iclass 35, count 0 2006.225.07:36:31.57#ibcon#*after write, iclass 35, count 0 2006.225.07:36:31.57#ibcon#*before return 0, iclass 35, count 0 2006.225.07:36:31.57#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:36:31.57#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:36:31.57#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.07:36:31.57#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.07:36:31.57$vc4f8/vb=4,4 2006.225.07:36:31.57#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.225.07:36:31.57#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.225.07:36:31.57#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:31.57#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:36:31.62#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:36:31.62#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:36:31.62#ibcon#enter wrdev, iclass 37, count 2 2006.225.07:36:31.62#ibcon#first serial, iclass 37, count 2 2006.225.07:36:31.62#ibcon#enter sib2, iclass 37, count 2 2006.225.07:36:31.62#ibcon#flushed, iclass 37, count 2 2006.225.07:36:31.62#ibcon#about to write, iclass 37, count 2 2006.225.07:36:31.62#ibcon#wrote, iclass 37, count 2 2006.225.07:36:31.62#ibcon#about to read 3, iclass 37, count 2 2006.225.07:36:31.64#ibcon#read 3, iclass 37, count 2 2006.225.07:36:31.64#ibcon#about to read 4, iclass 37, count 2 2006.225.07:36:31.64#ibcon#read 4, iclass 37, count 2 2006.225.07:36:31.64#ibcon#about to read 5, iclass 37, count 2 2006.225.07:36:31.64#ibcon#read 5, iclass 37, count 2 2006.225.07:36:31.64#ibcon#about to read 6, iclass 37, count 2 2006.225.07:36:31.64#ibcon#read 6, iclass 37, count 2 2006.225.07:36:31.64#ibcon#end of sib2, iclass 37, count 2 2006.225.07:36:31.64#ibcon#*mode == 0, iclass 37, count 2 2006.225.07:36:31.64#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.225.07:36:31.64#ibcon#[27=AT04-04\r\n] 2006.225.07:36:31.64#ibcon#*before write, iclass 37, count 2 2006.225.07:36:31.64#ibcon#enter sib2, iclass 37, count 2 2006.225.07:36:31.64#ibcon#flushed, iclass 37, count 2 2006.225.07:36:31.64#ibcon#about to write, iclass 37, count 2 2006.225.07:36:31.64#ibcon#wrote, iclass 37, count 2 2006.225.07:36:31.64#ibcon#about to read 3, iclass 37, count 2 2006.225.07:36:31.67#ibcon#read 3, iclass 37, count 2 2006.225.07:36:31.67#ibcon#about to read 4, iclass 37, count 2 2006.225.07:36:31.67#ibcon#read 4, iclass 37, count 2 2006.225.07:36:31.67#ibcon#about to read 5, iclass 37, count 2 2006.225.07:36:31.67#ibcon#read 5, iclass 37, count 2 2006.225.07:36:31.67#ibcon#about to read 6, iclass 37, count 2 2006.225.07:36:31.67#ibcon#read 6, iclass 37, count 2 2006.225.07:36:31.67#ibcon#end of sib2, iclass 37, count 2 2006.225.07:36:31.67#ibcon#*after write, iclass 37, count 2 2006.225.07:36:31.67#ibcon#*before return 0, iclass 37, count 2 2006.225.07:36:31.67#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:36:31.67#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:36:31.67#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.225.07:36:31.67#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:31.67#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:36:31.79#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:36:31.79#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:36:31.79#ibcon#enter wrdev, iclass 37, count 0 2006.225.07:36:31.79#ibcon#first serial, iclass 37, count 0 2006.225.07:36:31.79#ibcon#enter sib2, iclass 37, count 0 2006.225.07:36:31.79#ibcon#flushed, iclass 37, count 0 2006.225.07:36:31.79#ibcon#about to write, iclass 37, count 0 2006.225.07:36:31.79#ibcon#wrote, iclass 37, count 0 2006.225.07:36:31.79#ibcon#about to read 3, iclass 37, count 0 2006.225.07:36:31.81#ibcon#read 3, iclass 37, count 0 2006.225.07:36:31.81#ibcon#about to read 4, iclass 37, count 0 2006.225.07:36:31.81#ibcon#read 4, iclass 37, count 0 2006.225.07:36:31.81#ibcon#about to read 5, iclass 37, count 0 2006.225.07:36:31.81#ibcon#read 5, iclass 37, count 0 2006.225.07:36:31.81#ibcon#about to read 6, iclass 37, count 0 2006.225.07:36:31.81#ibcon#read 6, iclass 37, count 0 2006.225.07:36:31.81#ibcon#end of sib2, iclass 37, count 0 2006.225.07:36:31.81#ibcon#*mode == 0, iclass 37, count 0 2006.225.07:36:31.81#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.07:36:31.81#ibcon#[27=USB\r\n] 2006.225.07:36:31.81#ibcon#*before write, iclass 37, count 0 2006.225.07:36:31.81#ibcon#enter sib2, iclass 37, count 0 2006.225.07:36:31.81#ibcon#flushed, iclass 37, count 0 2006.225.07:36:31.81#ibcon#about to write, iclass 37, count 0 2006.225.07:36:31.81#ibcon#wrote, iclass 37, count 0 2006.225.07:36:31.81#ibcon#about to read 3, iclass 37, count 0 2006.225.07:36:31.84#ibcon#read 3, iclass 37, count 0 2006.225.07:36:31.84#ibcon#about to read 4, iclass 37, count 0 2006.225.07:36:31.84#ibcon#read 4, iclass 37, count 0 2006.225.07:36:31.84#ibcon#about to read 5, iclass 37, count 0 2006.225.07:36:31.84#ibcon#read 5, iclass 37, count 0 2006.225.07:36:31.84#ibcon#about to read 6, iclass 37, count 0 2006.225.07:36:31.84#ibcon#read 6, iclass 37, count 0 2006.225.07:36:31.84#ibcon#end of sib2, iclass 37, count 0 2006.225.07:36:31.84#ibcon#*after write, iclass 37, count 0 2006.225.07:36:31.84#ibcon#*before return 0, iclass 37, count 0 2006.225.07:36:31.84#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:36:31.84#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:36:31.84#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.07:36:31.84#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.07:36:31.84$vc4f8/vblo=5,744.99 2006.225.07:36:31.84#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.07:36:31.84#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.07:36:31.84#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:31.84#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:36:31.84#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:36:31.84#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:36:31.84#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:36:31.84#ibcon#first serial, iclass 39, count 0 2006.225.07:36:31.84#ibcon#enter sib2, iclass 39, count 0 2006.225.07:36:31.84#ibcon#flushed, iclass 39, count 0 2006.225.07:36:31.84#ibcon#about to write, iclass 39, count 0 2006.225.07:36:31.84#ibcon#wrote, iclass 39, count 0 2006.225.07:36:31.84#ibcon#about to read 3, iclass 39, count 0 2006.225.07:36:31.86#ibcon#read 3, iclass 39, count 0 2006.225.07:36:31.86#ibcon#about to read 4, iclass 39, count 0 2006.225.07:36:31.86#ibcon#read 4, iclass 39, count 0 2006.225.07:36:31.86#ibcon#about to read 5, iclass 39, count 0 2006.225.07:36:31.86#ibcon#read 5, iclass 39, count 0 2006.225.07:36:31.86#ibcon#about to read 6, iclass 39, count 0 2006.225.07:36:31.86#ibcon#read 6, iclass 39, count 0 2006.225.07:36:31.86#ibcon#end of sib2, iclass 39, count 0 2006.225.07:36:31.86#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:36:31.86#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:36:31.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:36:31.86#ibcon#*before write, iclass 39, count 0 2006.225.07:36:31.86#ibcon#enter sib2, iclass 39, count 0 2006.225.07:36:31.86#ibcon#flushed, iclass 39, count 0 2006.225.07:36:31.86#ibcon#about to write, iclass 39, count 0 2006.225.07:36:31.86#ibcon#wrote, iclass 39, count 0 2006.225.07:36:31.86#ibcon#about to read 3, iclass 39, count 0 2006.225.07:36:31.90#ibcon#read 3, iclass 39, count 0 2006.225.07:36:31.90#ibcon#about to read 4, iclass 39, count 0 2006.225.07:36:31.90#ibcon#read 4, iclass 39, count 0 2006.225.07:36:31.90#ibcon#about to read 5, iclass 39, count 0 2006.225.07:36:31.90#ibcon#read 5, iclass 39, count 0 2006.225.07:36:31.90#ibcon#about to read 6, iclass 39, count 0 2006.225.07:36:31.90#ibcon#read 6, iclass 39, count 0 2006.225.07:36:31.90#ibcon#end of sib2, iclass 39, count 0 2006.225.07:36:31.90#ibcon#*after write, iclass 39, count 0 2006.225.07:36:31.90#ibcon#*before return 0, iclass 39, count 0 2006.225.07:36:31.90#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:36:31.90#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:36:31.90#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:36:31.90#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:36:31.90$vc4f8/vb=5,4 2006.225.07:36:31.90#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.07:36:31.90#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.07:36:31.90#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:31.90#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:36:31.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:36:31.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:36:31.96#ibcon#enter wrdev, iclass 3, count 2 2006.225.07:36:31.96#ibcon#first serial, iclass 3, count 2 2006.225.07:36:31.96#ibcon#enter sib2, iclass 3, count 2 2006.225.07:36:31.96#ibcon#flushed, iclass 3, count 2 2006.225.07:36:31.96#ibcon#about to write, iclass 3, count 2 2006.225.07:36:31.96#ibcon#wrote, iclass 3, count 2 2006.225.07:36:31.96#ibcon#about to read 3, iclass 3, count 2 2006.225.07:36:31.98#ibcon#read 3, iclass 3, count 2 2006.225.07:36:31.98#ibcon#about to read 4, iclass 3, count 2 2006.225.07:36:31.98#ibcon#read 4, iclass 3, count 2 2006.225.07:36:31.98#ibcon#about to read 5, iclass 3, count 2 2006.225.07:36:31.98#ibcon#read 5, iclass 3, count 2 2006.225.07:36:31.98#ibcon#about to read 6, iclass 3, count 2 2006.225.07:36:31.98#ibcon#read 6, iclass 3, count 2 2006.225.07:36:31.98#ibcon#end of sib2, iclass 3, count 2 2006.225.07:36:31.98#ibcon#*mode == 0, iclass 3, count 2 2006.225.07:36:31.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.07:36:31.98#ibcon#[27=AT05-04\r\n] 2006.225.07:36:31.98#ibcon#*before write, iclass 3, count 2 2006.225.07:36:31.98#ibcon#enter sib2, iclass 3, count 2 2006.225.07:36:31.98#ibcon#flushed, iclass 3, count 2 2006.225.07:36:31.98#ibcon#about to write, iclass 3, count 2 2006.225.07:36:31.98#ibcon#wrote, iclass 3, count 2 2006.225.07:36:31.98#ibcon#about to read 3, iclass 3, count 2 2006.225.07:36:32.01#ibcon#read 3, iclass 3, count 2 2006.225.07:36:32.01#ibcon#about to read 4, iclass 3, count 2 2006.225.07:36:32.01#ibcon#read 4, iclass 3, count 2 2006.225.07:36:32.01#ibcon#about to read 5, iclass 3, count 2 2006.225.07:36:32.01#ibcon#read 5, iclass 3, count 2 2006.225.07:36:32.01#ibcon#about to read 6, iclass 3, count 2 2006.225.07:36:32.01#ibcon#read 6, iclass 3, count 2 2006.225.07:36:32.01#ibcon#end of sib2, iclass 3, count 2 2006.225.07:36:32.01#ibcon#*after write, iclass 3, count 2 2006.225.07:36:32.01#ibcon#*before return 0, iclass 3, count 2 2006.225.07:36:32.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:36:32.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:36:32.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.07:36:32.01#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:32.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:36:32.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:36:32.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:36:32.13#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:36:32.13#ibcon#first serial, iclass 3, count 0 2006.225.07:36:32.13#ibcon#enter sib2, iclass 3, count 0 2006.225.07:36:32.13#ibcon#flushed, iclass 3, count 0 2006.225.07:36:32.13#ibcon#about to write, iclass 3, count 0 2006.225.07:36:32.13#ibcon#wrote, iclass 3, count 0 2006.225.07:36:32.13#ibcon#about to read 3, iclass 3, count 0 2006.225.07:36:32.15#ibcon#read 3, iclass 3, count 0 2006.225.07:36:32.15#ibcon#about to read 4, iclass 3, count 0 2006.225.07:36:32.15#ibcon#read 4, iclass 3, count 0 2006.225.07:36:32.15#ibcon#about to read 5, iclass 3, count 0 2006.225.07:36:32.15#ibcon#read 5, iclass 3, count 0 2006.225.07:36:32.15#ibcon#about to read 6, iclass 3, count 0 2006.225.07:36:32.15#ibcon#read 6, iclass 3, count 0 2006.225.07:36:32.15#ibcon#end of sib2, iclass 3, count 0 2006.225.07:36:32.15#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:36:32.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:36:32.15#ibcon#[27=USB\r\n] 2006.225.07:36:32.15#ibcon#*before write, iclass 3, count 0 2006.225.07:36:32.15#ibcon#enter sib2, iclass 3, count 0 2006.225.07:36:32.15#ibcon#flushed, iclass 3, count 0 2006.225.07:36:32.15#ibcon#about to write, iclass 3, count 0 2006.225.07:36:32.15#ibcon#wrote, iclass 3, count 0 2006.225.07:36:32.15#ibcon#about to read 3, iclass 3, count 0 2006.225.07:36:32.18#ibcon#read 3, iclass 3, count 0 2006.225.07:36:32.18#ibcon#about to read 4, iclass 3, count 0 2006.225.07:36:32.18#ibcon#read 4, iclass 3, count 0 2006.225.07:36:32.18#ibcon#about to read 5, iclass 3, count 0 2006.225.07:36:32.18#ibcon#read 5, iclass 3, count 0 2006.225.07:36:32.18#ibcon#about to read 6, iclass 3, count 0 2006.225.07:36:32.18#ibcon#read 6, iclass 3, count 0 2006.225.07:36:32.18#ibcon#end of sib2, iclass 3, count 0 2006.225.07:36:32.18#ibcon#*after write, iclass 3, count 0 2006.225.07:36:32.18#ibcon#*before return 0, iclass 3, count 0 2006.225.07:36:32.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:36:32.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:36:32.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:36:32.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:36:32.18$vc4f8/vblo=6,752.99 2006.225.07:36:32.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.07:36:32.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.07:36:32.18#ibcon#ireg 17 cls_cnt 0 2006.225.07:36:32.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:36:32.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:36:32.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:36:32.18#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:36:32.18#ibcon#first serial, iclass 5, count 0 2006.225.07:36:32.18#ibcon#enter sib2, iclass 5, count 0 2006.225.07:36:32.18#ibcon#flushed, iclass 5, count 0 2006.225.07:36:32.18#ibcon#about to write, iclass 5, count 0 2006.225.07:36:32.18#ibcon#wrote, iclass 5, count 0 2006.225.07:36:32.18#ibcon#about to read 3, iclass 5, count 0 2006.225.07:36:32.20#ibcon#read 3, iclass 5, count 0 2006.225.07:36:32.20#ibcon#about to read 4, iclass 5, count 0 2006.225.07:36:32.20#ibcon#read 4, iclass 5, count 0 2006.225.07:36:32.20#ibcon#about to read 5, iclass 5, count 0 2006.225.07:36:32.20#ibcon#read 5, iclass 5, count 0 2006.225.07:36:32.20#ibcon#about to read 6, iclass 5, count 0 2006.225.07:36:32.20#ibcon#read 6, iclass 5, count 0 2006.225.07:36:32.20#ibcon#end of sib2, iclass 5, count 0 2006.225.07:36:32.20#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:36:32.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:36:32.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:36:32.20#ibcon#*before write, iclass 5, count 0 2006.225.07:36:32.20#ibcon#enter sib2, iclass 5, count 0 2006.225.07:36:32.20#ibcon#flushed, iclass 5, count 0 2006.225.07:36:32.20#ibcon#about to write, iclass 5, count 0 2006.225.07:36:32.20#ibcon#wrote, iclass 5, count 0 2006.225.07:36:32.20#ibcon#about to read 3, iclass 5, count 0 2006.225.07:36:32.24#ibcon#read 3, iclass 5, count 0 2006.225.07:36:32.24#ibcon#about to read 4, iclass 5, count 0 2006.225.07:36:32.24#ibcon#read 4, iclass 5, count 0 2006.225.07:36:32.24#ibcon#about to read 5, iclass 5, count 0 2006.225.07:36:32.24#ibcon#read 5, iclass 5, count 0 2006.225.07:36:32.24#ibcon#about to read 6, iclass 5, count 0 2006.225.07:36:32.24#ibcon#read 6, iclass 5, count 0 2006.225.07:36:32.24#ibcon#end of sib2, iclass 5, count 0 2006.225.07:36:32.24#ibcon#*after write, iclass 5, count 0 2006.225.07:36:32.24#ibcon#*before return 0, iclass 5, count 0 2006.225.07:36:32.24#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:36:32.24#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:36:32.24#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:36:32.24#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:36:32.24$vc4f8/vb=6,4 2006.225.07:36:32.24#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.07:36:32.24#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.07:36:32.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:36:32.24#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:36:32.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:36:32.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:36:32.30#ibcon#enter wrdev, iclass 7, count 2 2006.225.07:36:32.30#ibcon#first serial, iclass 7, count 2 2006.225.07:36:32.30#ibcon#enter sib2, iclass 7, count 2 2006.225.07:36:32.30#ibcon#flushed, iclass 7, count 2 2006.225.07:36:32.30#ibcon#about to write, iclass 7, count 2 2006.225.07:36:32.30#ibcon#wrote, iclass 7, count 2 2006.225.07:36:32.30#ibcon#about to read 3, iclass 7, count 2 2006.225.07:36:32.32#ibcon#read 3, iclass 7, count 2 2006.225.07:36:32.32#ibcon#about to read 4, iclass 7, count 2 2006.225.07:36:32.32#ibcon#read 4, iclass 7, count 2 2006.225.07:36:32.32#ibcon#about to read 5, iclass 7, count 2 2006.225.07:36:32.32#ibcon#read 5, iclass 7, count 2 2006.225.07:36:32.32#ibcon#about to read 6, iclass 7, count 2 2006.225.07:36:32.32#ibcon#read 6, iclass 7, count 2 2006.225.07:36:32.32#ibcon#end of sib2, iclass 7, count 2 2006.225.07:36:32.32#ibcon#*mode == 0, iclass 7, count 2 2006.225.07:36:32.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.07:36:32.32#ibcon#[27=AT06-04\r\n] 2006.225.07:36:32.32#ibcon#*before write, iclass 7, count 2 2006.225.07:36:32.32#ibcon#enter sib2, iclass 7, count 2 2006.225.07:36:32.32#ibcon#flushed, iclass 7, count 2 2006.225.07:36:32.32#ibcon#about to write, iclass 7, count 2 2006.225.07:36:32.32#ibcon#wrote, iclass 7, count 2 2006.225.07:36:32.32#ibcon#about to read 3, iclass 7, count 2 2006.225.07:36:32.35#ibcon#read 3, iclass 7, count 2 2006.225.07:36:32.35#ibcon#about to read 4, iclass 7, count 2 2006.225.07:36:32.35#ibcon#read 4, iclass 7, count 2 2006.225.07:36:32.35#ibcon#about to read 5, iclass 7, count 2 2006.225.07:36:32.35#ibcon#read 5, iclass 7, count 2 2006.225.07:36:32.35#ibcon#about to read 6, iclass 7, count 2 2006.225.07:36:32.35#ibcon#read 6, iclass 7, count 2 2006.225.07:36:32.35#ibcon#end of sib2, iclass 7, count 2 2006.225.07:36:32.35#ibcon#*after write, iclass 7, count 2 2006.225.07:36:32.35#ibcon#*before return 0, iclass 7, count 2 2006.225.07:36:32.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:36:32.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:36:32.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.07:36:32.35#ibcon#ireg 7 cls_cnt 0 2006.225.07:36:32.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:36:32.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:36:32.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:36:32.47#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:36:32.47#ibcon#first serial, iclass 7, count 0 2006.225.07:36:32.47#ibcon#enter sib2, iclass 7, count 0 2006.225.07:36:32.47#ibcon#flushed, iclass 7, count 0 2006.225.07:36:32.47#ibcon#about to write, iclass 7, count 0 2006.225.07:36:32.47#ibcon#wrote, iclass 7, count 0 2006.225.07:36:32.47#ibcon#about to read 3, iclass 7, count 0 2006.225.07:36:32.49#ibcon#read 3, iclass 7, count 0 2006.225.07:36:32.49#ibcon#about to read 4, iclass 7, count 0 2006.225.07:36:32.49#ibcon#read 4, iclass 7, count 0 2006.225.07:36:32.49#ibcon#about to read 5, iclass 7, count 0 2006.225.07:36:32.49#ibcon#read 5, iclass 7, count 0 2006.225.07:36:32.49#ibcon#about to read 6, iclass 7, count 0 2006.225.07:36:32.49#ibcon#read 6, iclass 7, count 0 2006.225.07:36:32.49#ibcon#end of sib2, iclass 7, count 0 2006.225.07:36:32.49#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:36:32.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:36:32.49#ibcon#[27=USB\r\n] 2006.225.07:36:32.49#ibcon#*before write, iclass 7, count 0 2006.225.07:36:32.49#ibcon#enter sib2, iclass 7, count 0 2006.225.07:36:32.49#ibcon#flushed, iclass 7, count 0 2006.225.07:36:32.49#ibcon#about to write, iclass 7, count 0 2006.225.07:36:32.49#ibcon#wrote, iclass 7, count 0 2006.225.07:36:32.49#ibcon#about to read 3, iclass 7, count 0 2006.225.07:36:32.52#ibcon#read 3, iclass 7, count 0 2006.225.07:36:32.52#ibcon#about to read 4, iclass 7, count 0 2006.225.07:36:32.52#ibcon#read 4, iclass 7, count 0 2006.225.07:36:32.52#ibcon#about to read 5, iclass 7, count 0 2006.225.07:36:32.52#ibcon#read 5, iclass 7, count 0 2006.225.07:36:32.52#ibcon#about to read 6, iclass 7, count 0 2006.225.07:36:32.52#ibcon#read 6, iclass 7, count 0 2006.225.07:36:32.52#ibcon#end of sib2, iclass 7, count 0 2006.225.07:36:32.52#ibcon#*after write, iclass 7, count 0 2006.225.07:36:32.52#ibcon#*before return 0, iclass 7, count 0 2006.225.07:36:32.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:36:32.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:36:32.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:36:32.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:36:32.52$vc4f8/vabw=wide 2006.225.07:36:32.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.07:36:32.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.07:36:32.52#ibcon#ireg 8 cls_cnt 0 2006.225.07:36:32.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:36:32.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:36:32.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:36:32.52#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:36:32.52#ibcon#first serial, iclass 11, count 0 2006.225.07:36:32.52#ibcon#enter sib2, iclass 11, count 0 2006.225.07:36:32.52#ibcon#flushed, iclass 11, count 0 2006.225.07:36:32.52#ibcon#about to write, iclass 11, count 0 2006.225.07:36:32.52#ibcon#wrote, iclass 11, count 0 2006.225.07:36:32.52#ibcon#about to read 3, iclass 11, count 0 2006.225.07:36:32.55#ibcon#read 3, iclass 11, count 0 2006.225.07:36:32.55#ibcon#about to read 4, iclass 11, count 0 2006.225.07:36:32.55#ibcon#read 4, iclass 11, count 0 2006.225.07:36:32.55#ibcon#about to read 5, iclass 11, count 0 2006.225.07:36:32.55#ibcon#read 5, iclass 11, count 0 2006.225.07:36:32.55#ibcon#about to read 6, iclass 11, count 0 2006.225.07:36:32.55#ibcon#read 6, iclass 11, count 0 2006.225.07:36:32.55#ibcon#end of sib2, iclass 11, count 0 2006.225.07:36:32.55#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:36:32.55#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:36:32.55#ibcon#[25=BW32\r\n] 2006.225.07:36:32.55#ibcon#*before write, iclass 11, count 0 2006.225.07:36:32.55#ibcon#enter sib2, iclass 11, count 0 2006.225.07:36:32.55#ibcon#flushed, iclass 11, count 0 2006.225.07:36:32.55#ibcon#about to write, iclass 11, count 0 2006.225.07:36:32.55#ibcon#wrote, iclass 11, count 0 2006.225.07:36:32.55#ibcon#about to read 3, iclass 11, count 0 2006.225.07:36:32.58#ibcon#read 3, iclass 11, count 0 2006.225.07:36:32.58#ibcon#about to read 4, iclass 11, count 0 2006.225.07:36:32.58#ibcon#read 4, iclass 11, count 0 2006.225.07:36:32.58#ibcon#about to read 5, iclass 11, count 0 2006.225.07:36:32.58#ibcon#read 5, iclass 11, count 0 2006.225.07:36:32.58#ibcon#about to read 6, iclass 11, count 0 2006.225.07:36:32.58#ibcon#read 6, iclass 11, count 0 2006.225.07:36:32.58#ibcon#end of sib2, iclass 11, count 0 2006.225.07:36:32.58#ibcon#*after write, iclass 11, count 0 2006.225.07:36:32.58#ibcon#*before return 0, iclass 11, count 0 2006.225.07:36:32.58#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:36:32.58#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:36:32.58#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:36:32.58#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:36:32.58$vc4f8/vbbw=wide 2006.225.07:36:32.58#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.07:36:32.58#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.07:36:32.58#ibcon#ireg 8 cls_cnt 0 2006.225.07:36:32.58#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:36:32.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:36:32.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:36:32.64#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:36:32.64#ibcon#first serial, iclass 13, count 0 2006.225.07:36:32.64#ibcon#enter sib2, iclass 13, count 0 2006.225.07:36:32.64#ibcon#flushed, iclass 13, count 0 2006.225.07:36:32.64#ibcon#about to write, iclass 13, count 0 2006.225.07:36:32.64#ibcon#wrote, iclass 13, count 0 2006.225.07:36:32.64#ibcon#about to read 3, iclass 13, count 0 2006.225.07:36:32.66#ibcon#read 3, iclass 13, count 0 2006.225.07:36:32.66#ibcon#about to read 4, iclass 13, count 0 2006.225.07:36:32.66#ibcon#read 4, iclass 13, count 0 2006.225.07:36:32.66#ibcon#about to read 5, iclass 13, count 0 2006.225.07:36:32.66#ibcon#read 5, iclass 13, count 0 2006.225.07:36:32.66#ibcon#about to read 6, iclass 13, count 0 2006.225.07:36:32.66#ibcon#read 6, iclass 13, count 0 2006.225.07:36:32.66#ibcon#end of sib2, iclass 13, count 0 2006.225.07:36:32.66#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:36:32.66#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:36:32.66#ibcon#[27=BW32\r\n] 2006.225.07:36:32.66#ibcon#*before write, iclass 13, count 0 2006.225.07:36:32.66#ibcon#enter sib2, iclass 13, count 0 2006.225.07:36:32.66#ibcon#flushed, iclass 13, count 0 2006.225.07:36:32.66#ibcon#about to write, iclass 13, count 0 2006.225.07:36:32.66#ibcon#wrote, iclass 13, count 0 2006.225.07:36:32.66#ibcon#about to read 3, iclass 13, count 0 2006.225.07:36:32.69#ibcon#read 3, iclass 13, count 0 2006.225.07:36:32.69#ibcon#about to read 4, iclass 13, count 0 2006.225.07:36:32.69#ibcon#read 4, iclass 13, count 0 2006.225.07:36:32.69#ibcon#about to read 5, iclass 13, count 0 2006.225.07:36:32.69#ibcon#read 5, iclass 13, count 0 2006.225.07:36:32.69#ibcon#about to read 6, iclass 13, count 0 2006.225.07:36:32.69#ibcon#read 6, iclass 13, count 0 2006.225.07:36:32.69#ibcon#end of sib2, iclass 13, count 0 2006.225.07:36:32.69#ibcon#*after write, iclass 13, count 0 2006.225.07:36:32.69#ibcon#*before return 0, iclass 13, count 0 2006.225.07:36:32.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:36:32.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:36:32.69#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:36:32.69#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:36:32.69$4f8m12a/ifd4f 2006.225.07:36:32.69$ifd4f/lo= 2006.225.07:36:32.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:36:32.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:36:32.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:36:32.69$ifd4f/patch= 2006.225.07:36:32.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:36:32.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:36:32.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:36:32.69$4f8m12a/"form=m,16.000,1:2 2006.225.07:36:32.69$4f8m12a/"tpicd 2006.225.07:36:32.69$4f8m12a/echo=off 2006.225.07:36:32.69$4f8m12a/xlog=off 2006.225.07:36:32.69:!2006.225.07:37:00 2006.225.07:36:42.14#trakl#Source acquired 2006.225.07:36:44.14#flagr#flagr/antenna,acquired 2006.225.07:37:00.00:preob 2006.225.07:37:00.14/onsource/TRACKING 2006.225.07:37:00.14:!2006.225.07:37:10 2006.225.07:37:10.00:data_valid=on 2006.225.07:37:10.00:midob 2006.225.07:37:11.14/onsource/TRACKING 2006.225.07:37:11.14/wx/27.91,1003.1,70 2006.225.07:37:11.30/cable/+6.4056E-03 2006.225.07:37:12.39/va/01,08,usb,yes,30,32 2006.225.07:37:12.39/va/02,07,usb,yes,30,32 2006.225.07:37:12.39/va/03,06,usb,yes,32,32 2006.225.07:37:12.39/va/04,07,usb,yes,32,34 2006.225.07:37:12.39/va/05,07,usb,yes,34,36 2006.225.07:37:12.39/va/06,06,usb,yes,33,33 2006.225.07:37:12.39/va/07,06,usb,yes,34,33 2006.225.07:37:12.39/va/08,07,usb,yes,32,31 2006.225.07:37:12.62/valo/01,532.99,yes,locked 2006.225.07:37:12.62/valo/02,572.99,yes,locked 2006.225.07:37:12.62/valo/03,672.99,yes,locked 2006.225.07:37:12.62/valo/04,832.99,yes,locked 2006.225.07:37:12.62/valo/05,652.99,yes,locked 2006.225.07:37:12.62/valo/06,772.99,yes,locked 2006.225.07:37:12.62/valo/07,832.99,yes,locked 2006.225.07:37:12.62/valo/08,852.99,yes,locked 2006.225.07:37:13.71/vb/01,04,usb,yes,31,30 2006.225.07:37:13.71/vb/02,04,usb,yes,33,35 2006.225.07:37:13.71/vb/03,04,usb,yes,30,34 2006.225.07:37:13.71/vb/04,04,usb,yes,30,31 2006.225.07:37:13.71/vb/05,04,usb,yes,29,33 2006.225.07:37:13.71/vb/06,04,usb,yes,30,33 2006.225.07:37:13.71/vb/07,04,usb,yes,32,32 2006.225.07:37:13.71/vb/08,04,usb,yes,30,33 2006.225.07:37:13.94/vblo/01,632.99,yes,locked 2006.225.07:37:13.94/vblo/02,640.99,yes,locked 2006.225.07:37:13.94/vblo/03,656.99,yes,locked 2006.225.07:37:13.94/vblo/04,712.99,yes,locked 2006.225.07:37:13.94/vblo/05,744.99,yes,locked 2006.225.07:37:13.94/vblo/06,752.99,yes,locked 2006.225.07:37:13.94/vblo/07,734.99,yes,locked 2006.225.07:37:13.94/vblo/08,744.99,yes,locked 2006.225.07:37:14.09/vabw/8 2006.225.07:37:14.24/vbbw/8 2006.225.07:37:14.33/xfe/off,on,15.2 2006.225.07:37:14.70/ifatt/23,28,28,28 2006.225.07:37:15.07/fmout-gps/S +4.44E-07 2006.225.07:37:15.11:!2006.225.07:38:10 2006.225.07:38:10.01:data_valid=off 2006.225.07:38:10.02:postob 2006.225.07:38:10.17/cable/+6.4030E-03 2006.225.07:38:10.18/wx/27.91,1003.2,70 2006.225.07:38:11.07/fmout-gps/S +4.45E-07 2006.225.07:38:11.08:scan_name=225-0739,k06225,70 2006.225.07:38:11.08:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.225.07:38:11.15#flagr#flagr/antenna,new-source 2006.225.07:38:12.13:checkk5 2006.225.07:38:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:38:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:38:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:38:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:38:13.98/chk_obsdata//k5ts1/T2250737??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:38:14.35/chk_obsdata//k5ts2/T2250737??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:38:14.72/chk_obsdata//k5ts3/T2250737??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:38:15.08/chk_obsdata//k5ts4/T2250737??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:38:15.78/k5log//k5ts1_log_newline 2006.225.07:38:16.46/k5log//k5ts2_log_newline 2006.225.07:38:17.15/k5log//k5ts3_log_newline 2006.225.07:38:17.83/k5log//k5ts4_log_newline 2006.225.07:38:17.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:38:17.86:4f8m12a=1 2006.225.07:38:17.86$4f8m12a/echo=on 2006.225.07:38:17.86$4f8m12a/pcalon 2006.225.07:38:17.86$pcalon/"no phase cal control is implemented here 2006.225.07:38:17.86$4f8m12a/"tpicd=stop 2006.225.07:38:17.86$4f8m12a/vc4f8 2006.225.07:38:17.86$vc4f8/valo=1,532.99 2006.225.07:38:17.86#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.225.07:38:17.86#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.225.07:38:17.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:17.86#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:38:17.86#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:38:17.86#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:38:17.86#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:38:17.86#ibcon#first serial, iclass 20, count 0 2006.225.07:38:17.86#ibcon#enter sib2, iclass 20, count 0 2006.225.07:38:17.86#ibcon#flushed, iclass 20, count 0 2006.225.07:38:17.86#ibcon#about to write, iclass 20, count 0 2006.225.07:38:17.86#ibcon#wrote, iclass 20, count 0 2006.225.07:38:17.86#ibcon#about to read 3, iclass 20, count 0 2006.225.07:38:17.90#ibcon#read 3, iclass 20, count 0 2006.225.07:38:17.90#ibcon#about to read 4, iclass 20, count 0 2006.225.07:38:17.90#ibcon#read 4, iclass 20, count 0 2006.225.07:38:17.90#ibcon#about to read 5, iclass 20, count 0 2006.225.07:38:17.90#ibcon#read 5, iclass 20, count 0 2006.225.07:38:17.90#ibcon#about to read 6, iclass 20, count 0 2006.225.07:38:17.90#ibcon#read 6, iclass 20, count 0 2006.225.07:38:17.90#ibcon#end of sib2, iclass 20, count 0 2006.225.07:38:17.90#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:38:17.90#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:38:17.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:38:17.90#ibcon#*before write, iclass 20, count 0 2006.225.07:38:17.90#ibcon#enter sib2, iclass 20, count 0 2006.225.07:38:17.90#ibcon#flushed, iclass 20, count 0 2006.225.07:38:17.90#ibcon#about to write, iclass 20, count 0 2006.225.07:38:17.90#ibcon#wrote, iclass 20, count 0 2006.225.07:38:17.90#ibcon#about to read 3, iclass 20, count 0 2006.225.07:38:17.94#ibcon#read 3, iclass 20, count 0 2006.225.07:38:17.94#ibcon#about to read 4, iclass 20, count 0 2006.225.07:38:17.94#ibcon#read 4, iclass 20, count 0 2006.225.07:38:17.94#ibcon#about to read 5, iclass 20, count 0 2006.225.07:38:17.94#ibcon#read 5, iclass 20, count 0 2006.225.07:38:17.94#ibcon#about to read 6, iclass 20, count 0 2006.225.07:38:17.94#ibcon#read 6, iclass 20, count 0 2006.225.07:38:17.94#ibcon#end of sib2, iclass 20, count 0 2006.225.07:38:17.94#ibcon#*after write, iclass 20, count 0 2006.225.07:38:17.94#ibcon#*before return 0, iclass 20, count 0 2006.225.07:38:17.94#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:38:17.94#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:38:17.94#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:38:17.94#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:38:17.94$vc4f8/va=1,8 2006.225.07:38:17.94#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.225.07:38:17.94#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.225.07:38:17.94#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:17.94#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:38:17.94#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:38:17.94#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:38:17.94#ibcon#enter wrdev, iclass 22, count 2 2006.225.07:38:17.94#ibcon#first serial, iclass 22, count 2 2006.225.07:38:17.94#ibcon#enter sib2, iclass 22, count 2 2006.225.07:38:17.94#ibcon#flushed, iclass 22, count 2 2006.225.07:38:17.94#ibcon#about to write, iclass 22, count 2 2006.225.07:38:17.94#ibcon#wrote, iclass 22, count 2 2006.225.07:38:17.94#ibcon#about to read 3, iclass 22, count 2 2006.225.07:38:17.96#ibcon#read 3, iclass 22, count 2 2006.225.07:38:17.96#ibcon#about to read 4, iclass 22, count 2 2006.225.07:38:17.96#ibcon#read 4, iclass 22, count 2 2006.225.07:38:17.96#ibcon#about to read 5, iclass 22, count 2 2006.225.07:38:17.96#ibcon#read 5, iclass 22, count 2 2006.225.07:38:17.96#ibcon#about to read 6, iclass 22, count 2 2006.225.07:38:17.96#ibcon#read 6, iclass 22, count 2 2006.225.07:38:17.96#ibcon#end of sib2, iclass 22, count 2 2006.225.07:38:17.96#ibcon#*mode == 0, iclass 22, count 2 2006.225.07:38:17.96#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.225.07:38:17.96#ibcon#[25=AT01-08\r\n] 2006.225.07:38:17.96#ibcon#*before write, iclass 22, count 2 2006.225.07:38:17.96#ibcon#enter sib2, iclass 22, count 2 2006.225.07:38:17.96#ibcon#flushed, iclass 22, count 2 2006.225.07:38:17.96#ibcon#about to write, iclass 22, count 2 2006.225.07:38:17.96#ibcon#wrote, iclass 22, count 2 2006.225.07:38:17.96#ibcon#about to read 3, iclass 22, count 2 2006.225.07:38:17.99#ibcon#read 3, iclass 22, count 2 2006.225.07:38:17.99#ibcon#about to read 4, iclass 22, count 2 2006.225.07:38:17.99#ibcon#read 4, iclass 22, count 2 2006.225.07:38:17.99#ibcon#about to read 5, iclass 22, count 2 2006.225.07:38:17.99#ibcon#read 5, iclass 22, count 2 2006.225.07:38:17.99#ibcon#about to read 6, iclass 22, count 2 2006.225.07:38:17.99#ibcon#read 6, iclass 22, count 2 2006.225.07:38:17.99#ibcon#end of sib2, iclass 22, count 2 2006.225.07:38:17.99#ibcon#*after write, iclass 22, count 2 2006.225.07:38:17.99#ibcon#*before return 0, iclass 22, count 2 2006.225.07:38:17.99#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:38:17.99#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:38:17.99#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.225.07:38:17.99#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:17.99#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:38:18.11#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:38:18.11#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:38:18.11#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:38:18.11#ibcon#first serial, iclass 22, count 0 2006.225.07:38:18.11#ibcon#enter sib2, iclass 22, count 0 2006.225.07:38:18.11#ibcon#flushed, iclass 22, count 0 2006.225.07:38:18.11#ibcon#about to write, iclass 22, count 0 2006.225.07:38:18.11#ibcon#wrote, iclass 22, count 0 2006.225.07:38:18.11#ibcon#about to read 3, iclass 22, count 0 2006.225.07:38:18.13#ibcon#read 3, iclass 22, count 0 2006.225.07:38:18.13#ibcon#about to read 4, iclass 22, count 0 2006.225.07:38:18.13#ibcon#read 4, iclass 22, count 0 2006.225.07:38:18.13#ibcon#about to read 5, iclass 22, count 0 2006.225.07:38:18.13#ibcon#read 5, iclass 22, count 0 2006.225.07:38:18.13#ibcon#about to read 6, iclass 22, count 0 2006.225.07:38:18.13#ibcon#read 6, iclass 22, count 0 2006.225.07:38:18.13#ibcon#end of sib2, iclass 22, count 0 2006.225.07:38:18.13#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:38:18.13#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:38:18.13#ibcon#[25=USB\r\n] 2006.225.07:38:18.13#ibcon#*before write, iclass 22, count 0 2006.225.07:38:18.13#ibcon#enter sib2, iclass 22, count 0 2006.225.07:38:18.13#ibcon#flushed, iclass 22, count 0 2006.225.07:38:18.13#ibcon#about to write, iclass 22, count 0 2006.225.07:38:18.13#ibcon#wrote, iclass 22, count 0 2006.225.07:38:18.13#ibcon#about to read 3, iclass 22, count 0 2006.225.07:38:18.16#ibcon#read 3, iclass 22, count 0 2006.225.07:38:18.16#ibcon#about to read 4, iclass 22, count 0 2006.225.07:38:18.16#ibcon#read 4, iclass 22, count 0 2006.225.07:38:18.16#ibcon#about to read 5, iclass 22, count 0 2006.225.07:38:18.16#ibcon#read 5, iclass 22, count 0 2006.225.07:38:18.16#ibcon#about to read 6, iclass 22, count 0 2006.225.07:38:18.16#ibcon#read 6, iclass 22, count 0 2006.225.07:38:18.16#ibcon#end of sib2, iclass 22, count 0 2006.225.07:38:18.16#ibcon#*after write, iclass 22, count 0 2006.225.07:38:18.16#ibcon#*before return 0, iclass 22, count 0 2006.225.07:38:18.16#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:38:18.16#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:38:18.16#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:38:18.16#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:38:18.16$vc4f8/valo=2,572.99 2006.225.07:38:18.16#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.07:38:18.16#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.07:38:18.16#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:18.16#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:38:18.16#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:38:18.16#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:38:18.16#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:38:18.16#ibcon#first serial, iclass 24, count 0 2006.225.07:38:18.16#ibcon#enter sib2, iclass 24, count 0 2006.225.07:38:18.16#ibcon#flushed, iclass 24, count 0 2006.225.07:38:18.16#ibcon#about to write, iclass 24, count 0 2006.225.07:38:18.16#ibcon#wrote, iclass 24, count 0 2006.225.07:38:18.16#ibcon#about to read 3, iclass 24, count 0 2006.225.07:38:18.19#ibcon#read 3, iclass 24, count 0 2006.225.07:38:18.19#ibcon#about to read 4, iclass 24, count 0 2006.225.07:38:18.19#ibcon#read 4, iclass 24, count 0 2006.225.07:38:18.19#ibcon#about to read 5, iclass 24, count 0 2006.225.07:38:18.19#ibcon#read 5, iclass 24, count 0 2006.225.07:38:18.19#ibcon#about to read 6, iclass 24, count 0 2006.225.07:38:18.19#ibcon#read 6, iclass 24, count 0 2006.225.07:38:18.19#ibcon#end of sib2, iclass 24, count 0 2006.225.07:38:18.19#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:38:18.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:38:18.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:38:18.19#ibcon#*before write, iclass 24, count 0 2006.225.07:38:18.19#ibcon#enter sib2, iclass 24, count 0 2006.225.07:38:18.19#ibcon#flushed, iclass 24, count 0 2006.225.07:38:18.19#ibcon#about to write, iclass 24, count 0 2006.225.07:38:18.19#ibcon#wrote, iclass 24, count 0 2006.225.07:38:18.19#ibcon#about to read 3, iclass 24, count 0 2006.225.07:38:18.23#ibcon#read 3, iclass 24, count 0 2006.225.07:38:18.23#ibcon#about to read 4, iclass 24, count 0 2006.225.07:38:18.23#ibcon#read 4, iclass 24, count 0 2006.225.07:38:18.23#ibcon#about to read 5, iclass 24, count 0 2006.225.07:38:18.23#ibcon#read 5, iclass 24, count 0 2006.225.07:38:18.23#ibcon#about to read 6, iclass 24, count 0 2006.225.07:38:18.23#ibcon#read 6, iclass 24, count 0 2006.225.07:38:18.23#ibcon#end of sib2, iclass 24, count 0 2006.225.07:38:18.23#ibcon#*after write, iclass 24, count 0 2006.225.07:38:18.23#ibcon#*before return 0, iclass 24, count 0 2006.225.07:38:18.23#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:38:18.23#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:38:18.23#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:38:18.23#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:38:18.23$vc4f8/va=2,7 2006.225.07:38:18.23#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.225.07:38:18.23#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.225.07:38:18.23#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:18.23#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:38:18.28#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:38:18.28#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:38:18.28#ibcon#enter wrdev, iclass 26, count 2 2006.225.07:38:18.28#ibcon#first serial, iclass 26, count 2 2006.225.07:38:18.28#ibcon#enter sib2, iclass 26, count 2 2006.225.07:38:18.28#ibcon#flushed, iclass 26, count 2 2006.225.07:38:18.28#ibcon#about to write, iclass 26, count 2 2006.225.07:38:18.28#ibcon#wrote, iclass 26, count 2 2006.225.07:38:18.28#ibcon#about to read 3, iclass 26, count 2 2006.225.07:38:18.30#ibcon#read 3, iclass 26, count 2 2006.225.07:38:18.30#ibcon#about to read 4, iclass 26, count 2 2006.225.07:38:18.30#ibcon#read 4, iclass 26, count 2 2006.225.07:38:18.30#ibcon#about to read 5, iclass 26, count 2 2006.225.07:38:18.30#ibcon#read 5, iclass 26, count 2 2006.225.07:38:18.30#ibcon#about to read 6, iclass 26, count 2 2006.225.07:38:18.30#ibcon#read 6, iclass 26, count 2 2006.225.07:38:18.30#ibcon#end of sib2, iclass 26, count 2 2006.225.07:38:18.30#ibcon#*mode == 0, iclass 26, count 2 2006.225.07:38:18.30#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.225.07:38:18.30#ibcon#[25=AT02-07\r\n] 2006.225.07:38:18.30#ibcon#*before write, iclass 26, count 2 2006.225.07:38:18.30#ibcon#enter sib2, iclass 26, count 2 2006.225.07:38:18.30#ibcon#flushed, iclass 26, count 2 2006.225.07:38:18.30#ibcon#about to write, iclass 26, count 2 2006.225.07:38:18.30#ibcon#wrote, iclass 26, count 2 2006.225.07:38:18.30#ibcon#about to read 3, iclass 26, count 2 2006.225.07:38:18.33#ibcon#read 3, iclass 26, count 2 2006.225.07:38:18.33#ibcon#about to read 4, iclass 26, count 2 2006.225.07:38:18.33#ibcon#read 4, iclass 26, count 2 2006.225.07:38:18.33#ibcon#about to read 5, iclass 26, count 2 2006.225.07:38:18.33#ibcon#read 5, iclass 26, count 2 2006.225.07:38:18.33#ibcon#about to read 6, iclass 26, count 2 2006.225.07:38:18.33#ibcon#read 6, iclass 26, count 2 2006.225.07:38:18.33#ibcon#end of sib2, iclass 26, count 2 2006.225.07:38:18.33#ibcon#*after write, iclass 26, count 2 2006.225.07:38:18.33#ibcon#*before return 0, iclass 26, count 2 2006.225.07:38:18.33#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:38:18.33#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:38:18.33#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.225.07:38:18.33#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:18.33#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:38:18.45#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:38:18.45#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:38:18.45#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:38:18.45#ibcon#first serial, iclass 26, count 0 2006.225.07:38:18.45#ibcon#enter sib2, iclass 26, count 0 2006.225.07:38:18.45#ibcon#flushed, iclass 26, count 0 2006.225.07:38:18.45#ibcon#about to write, iclass 26, count 0 2006.225.07:38:18.45#ibcon#wrote, iclass 26, count 0 2006.225.07:38:18.45#ibcon#about to read 3, iclass 26, count 0 2006.225.07:38:18.47#ibcon#read 3, iclass 26, count 0 2006.225.07:38:18.47#ibcon#about to read 4, iclass 26, count 0 2006.225.07:38:18.47#ibcon#read 4, iclass 26, count 0 2006.225.07:38:18.47#ibcon#about to read 5, iclass 26, count 0 2006.225.07:38:18.47#ibcon#read 5, iclass 26, count 0 2006.225.07:38:18.47#ibcon#about to read 6, iclass 26, count 0 2006.225.07:38:18.47#ibcon#read 6, iclass 26, count 0 2006.225.07:38:18.47#ibcon#end of sib2, iclass 26, count 0 2006.225.07:38:18.47#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:38:18.47#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:38:18.47#ibcon#[25=USB\r\n] 2006.225.07:38:18.47#ibcon#*before write, iclass 26, count 0 2006.225.07:38:18.47#ibcon#enter sib2, iclass 26, count 0 2006.225.07:38:18.47#ibcon#flushed, iclass 26, count 0 2006.225.07:38:18.47#ibcon#about to write, iclass 26, count 0 2006.225.07:38:18.47#ibcon#wrote, iclass 26, count 0 2006.225.07:38:18.47#ibcon#about to read 3, iclass 26, count 0 2006.225.07:38:18.50#ibcon#read 3, iclass 26, count 0 2006.225.07:38:18.50#ibcon#about to read 4, iclass 26, count 0 2006.225.07:38:18.50#ibcon#read 4, iclass 26, count 0 2006.225.07:38:18.50#ibcon#about to read 5, iclass 26, count 0 2006.225.07:38:18.50#ibcon#read 5, iclass 26, count 0 2006.225.07:38:18.50#ibcon#about to read 6, iclass 26, count 0 2006.225.07:38:18.50#ibcon#read 6, iclass 26, count 0 2006.225.07:38:18.50#ibcon#end of sib2, iclass 26, count 0 2006.225.07:38:18.50#ibcon#*after write, iclass 26, count 0 2006.225.07:38:18.50#ibcon#*before return 0, iclass 26, count 0 2006.225.07:38:18.50#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:38:18.50#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:38:18.50#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:38:18.50#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:38:18.50$vc4f8/valo=3,672.99 2006.225.07:38:18.50#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.07:38:18.50#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.07:38:18.50#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:18.50#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:38:18.50#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:38:18.50#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:38:18.50#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:38:18.50#ibcon#first serial, iclass 28, count 0 2006.225.07:38:18.50#ibcon#enter sib2, iclass 28, count 0 2006.225.07:38:18.50#ibcon#flushed, iclass 28, count 0 2006.225.07:38:18.50#ibcon#about to write, iclass 28, count 0 2006.225.07:38:18.50#ibcon#wrote, iclass 28, count 0 2006.225.07:38:18.50#ibcon#about to read 3, iclass 28, count 0 2006.225.07:38:18.53#ibcon#read 3, iclass 28, count 0 2006.225.07:38:18.53#ibcon#about to read 4, iclass 28, count 0 2006.225.07:38:18.53#ibcon#read 4, iclass 28, count 0 2006.225.07:38:18.53#ibcon#about to read 5, iclass 28, count 0 2006.225.07:38:18.53#ibcon#read 5, iclass 28, count 0 2006.225.07:38:18.53#ibcon#about to read 6, iclass 28, count 0 2006.225.07:38:18.53#ibcon#read 6, iclass 28, count 0 2006.225.07:38:18.53#ibcon#end of sib2, iclass 28, count 0 2006.225.07:38:18.53#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:38:18.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:38:18.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:38:18.53#ibcon#*before write, iclass 28, count 0 2006.225.07:38:18.53#ibcon#enter sib2, iclass 28, count 0 2006.225.07:38:18.53#ibcon#flushed, iclass 28, count 0 2006.225.07:38:18.53#ibcon#about to write, iclass 28, count 0 2006.225.07:38:18.53#ibcon#wrote, iclass 28, count 0 2006.225.07:38:18.53#ibcon#about to read 3, iclass 28, count 0 2006.225.07:38:18.57#ibcon#read 3, iclass 28, count 0 2006.225.07:38:18.57#ibcon#about to read 4, iclass 28, count 0 2006.225.07:38:18.57#ibcon#read 4, iclass 28, count 0 2006.225.07:38:18.57#ibcon#about to read 5, iclass 28, count 0 2006.225.07:38:18.57#ibcon#read 5, iclass 28, count 0 2006.225.07:38:18.57#ibcon#about to read 6, iclass 28, count 0 2006.225.07:38:18.57#ibcon#read 6, iclass 28, count 0 2006.225.07:38:18.57#ibcon#end of sib2, iclass 28, count 0 2006.225.07:38:18.57#ibcon#*after write, iclass 28, count 0 2006.225.07:38:18.57#ibcon#*before return 0, iclass 28, count 0 2006.225.07:38:18.57#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:38:18.57#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:38:18.57#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:38:18.57#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:38:18.57$vc4f8/va=3,6 2006.225.07:38:18.57#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.07:38:18.57#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.07:38:18.57#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:18.57#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:38:18.62#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:38:18.62#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:38:18.62#ibcon#enter wrdev, iclass 30, count 2 2006.225.07:38:18.62#ibcon#first serial, iclass 30, count 2 2006.225.07:38:18.62#ibcon#enter sib2, iclass 30, count 2 2006.225.07:38:18.62#ibcon#flushed, iclass 30, count 2 2006.225.07:38:18.62#ibcon#about to write, iclass 30, count 2 2006.225.07:38:18.62#ibcon#wrote, iclass 30, count 2 2006.225.07:38:18.62#ibcon#about to read 3, iclass 30, count 2 2006.225.07:38:18.64#ibcon#read 3, iclass 30, count 2 2006.225.07:38:18.64#ibcon#about to read 4, iclass 30, count 2 2006.225.07:38:18.64#ibcon#read 4, iclass 30, count 2 2006.225.07:38:18.64#ibcon#about to read 5, iclass 30, count 2 2006.225.07:38:18.64#ibcon#read 5, iclass 30, count 2 2006.225.07:38:18.64#ibcon#about to read 6, iclass 30, count 2 2006.225.07:38:18.64#ibcon#read 6, iclass 30, count 2 2006.225.07:38:18.64#ibcon#end of sib2, iclass 30, count 2 2006.225.07:38:18.64#ibcon#*mode == 0, iclass 30, count 2 2006.225.07:38:18.64#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.07:38:18.64#ibcon#[25=AT03-06\r\n] 2006.225.07:38:18.64#ibcon#*before write, iclass 30, count 2 2006.225.07:38:18.64#ibcon#enter sib2, iclass 30, count 2 2006.225.07:38:18.64#ibcon#flushed, iclass 30, count 2 2006.225.07:38:18.64#ibcon#about to write, iclass 30, count 2 2006.225.07:38:18.64#ibcon#wrote, iclass 30, count 2 2006.225.07:38:18.64#ibcon#about to read 3, iclass 30, count 2 2006.225.07:38:18.67#ibcon#read 3, iclass 30, count 2 2006.225.07:38:18.67#ibcon#about to read 4, iclass 30, count 2 2006.225.07:38:18.67#ibcon#read 4, iclass 30, count 2 2006.225.07:38:18.67#ibcon#about to read 5, iclass 30, count 2 2006.225.07:38:18.67#ibcon#read 5, iclass 30, count 2 2006.225.07:38:18.67#ibcon#about to read 6, iclass 30, count 2 2006.225.07:38:18.67#ibcon#read 6, iclass 30, count 2 2006.225.07:38:18.67#ibcon#end of sib2, iclass 30, count 2 2006.225.07:38:18.67#ibcon#*after write, iclass 30, count 2 2006.225.07:38:18.67#ibcon#*before return 0, iclass 30, count 2 2006.225.07:38:18.67#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:38:18.67#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:38:18.67#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.07:38:18.67#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:18.67#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:38:18.79#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:38:18.79#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:38:18.79#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:38:18.79#ibcon#first serial, iclass 30, count 0 2006.225.07:38:18.79#ibcon#enter sib2, iclass 30, count 0 2006.225.07:38:18.79#ibcon#flushed, iclass 30, count 0 2006.225.07:38:18.79#ibcon#about to write, iclass 30, count 0 2006.225.07:38:18.79#ibcon#wrote, iclass 30, count 0 2006.225.07:38:18.79#ibcon#about to read 3, iclass 30, count 0 2006.225.07:38:18.81#ibcon#read 3, iclass 30, count 0 2006.225.07:38:18.81#ibcon#about to read 4, iclass 30, count 0 2006.225.07:38:18.81#ibcon#read 4, iclass 30, count 0 2006.225.07:38:18.81#ibcon#about to read 5, iclass 30, count 0 2006.225.07:38:18.81#ibcon#read 5, iclass 30, count 0 2006.225.07:38:18.81#ibcon#about to read 6, iclass 30, count 0 2006.225.07:38:18.81#ibcon#read 6, iclass 30, count 0 2006.225.07:38:18.81#ibcon#end of sib2, iclass 30, count 0 2006.225.07:38:18.81#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:38:18.81#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:38:18.81#ibcon#[25=USB\r\n] 2006.225.07:38:18.81#ibcon#*before write, iclass 30, count 0 2006.225.07:38:18.81#ibcon#enter sib2, iclass 30, count 0 2006.225.07:38:18.81#ibcon#flushed, iclass 30, count 0 2006.225.07:38:18.81#ibcon#about to write, iclass 30, count 0 2006.225.07:38:18.81#ibcon#wrote, iclass 30, count 0 2006.225.07:38:18.81#ibcon#about to read 3, iclass 30, count 0 2006.225.07:38:18.84#ibcon#read 3, iclass 30, count 0 2006.225.07:38:18.84#ibcon#about to read 4, iclass 30, count 0 2006.225.07:38:18.84#ibcon#read 4, iclass 30, count 0 2006.225.07:38:18.84#ibcon#about to read 5, iclass 30, count 0 2006.225.07:38:18.84#ibcon#read 5, iclass 30, count 0 2006.225.07:38:18.84#ibcon#about to read 6, iclass 30, count 0 2006.225.07:38:18.84#ibcon#read 6, iclass 30, count 0 2006.225.07:38:18.84#ibcon#end of sib2, iclass 30, count 0 2006.225.07:38:18.84#ibcon#*after write, iclass 30, count 0 2006.225.07:38:18.84#ibcon#*before return 0, iclass 30, count 0 2006.225.07:38:18.84#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:38:18.84#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:38:18.84#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:38:18.84#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:38:18.84$vc4f8/valo=4,832.99 2006.225.07:38:18.84#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.07:38:18.84#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.07:38:18.84#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:18.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:38:18.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:38:18.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:38:18.84#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:38:18.84#ibcon#first serial, iclass 32, count 0 2006.225.07:38:18.84#ibcon#enter sib2, iclass 32, count 0 2006.225.07:38:18.84#ibcon#flushed, iclass 32, count 0 2006.225.07:38:18.84#ibcon#about to write, iclass 32, count 0 2006.225.07:38:18.84#ibcon#wrote, iclass 32, count 0 2006.225.07:38:18.84#ibcon#about to read 3, iclass 32, count 0 2006.225.07:38:18.87#ibcon#read 3, iclass 32, count 0 2006.225.07:38:18.87#ibcon#about to read 4, iclass 32, count 0 2006.225.07:38:18.87#ibcon#read 4, iclass 32, count 0 2006.225.07:38:18.87#ibcon#about to read 5, iclass 32, count 0 2006.225.07:38:18.87#ibcon#read 5, iclass 32, count 0 2006.225.07:38:18.87#ibcon#about to read 6, iclass 32, count 0 2006.225.07:38:18.87#ibcon#read 6, iclass 32, count 0 2006.225.07:38:18.87#ibcon#end of sib2, iclass 32, count 0 2006.225.07:38:18.87#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:38:18.87#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:38:18.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:38:18.87#ibcon#*before write, iclass 32, count 0 2006.225.07:38:18.87#ibcon#enter sib2, iclass 32, count 0 2006.225.07:38:18.87#ibcon#flushed, iclass 32, count 0 2006.225.07:38:18.87#ibcon#about to write, iclass 32, count 0 2006.225.07:38:18.87#ibcon#wrote, iclass 32, count 0 2006.225.07:38:18.87#ibcon#about to read 3, iclass 32, count 0 2006.225.07:38:18.91#ibcon#read 3, iclass 32, count 0 2006.225.07:38:18.91#ibcon#about to read 4, iclass 32, count 0 2006.225.07:38:18.91#ibcon#read 4, iclass 32, count 0 2006.225.07:38:18.91#ibcon#about to read 5, iclass 32, count 0 2006.225.07:38:18.91#ibcon#read 5, iclass 32, count 0 2006.225.07:38:18.91#ibcon#about to read 6, iclass 32, count 0 2006.225.07:38:18.91#ibcon#read 6, iclass 32, count 0 2006.225.07:38:18.91#ibcon#end of sib2, iclass 32, count 0 2006.225.07:38:18.91#ibcon#*after write, iclass 32, count 0 2006.225.07:38:18.91#ibcon#*before return 0, iclass 32, count 0 2006.225.07:38:18.91#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:38:18.91#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:38:18.91#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:38:18.91#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:38:18.91$vc4f8/va=4,7 2006.225.07:38:18.91#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.07:38:18.91#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.07:38:18.91#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:18.91#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:38:18.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:38:18.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:38:18.96#ibcon#enter wrdev, iclass 34, count 2 2006.225.07:38:18.96#ibcon#first serial, iclass 34, count 2 2006.225.07:38:18.96#ibcon#enter sib2, iclass 34, count 2 2006.225.07:38:18.96#ibcon#flushed, iclass 34, count 2 2006.225.07:38:18.96#ibcon#about to write, iclass 34, count 2 2006.225.07:38:18.96#ibcon#wrote, iclass 34, count 2 2006.225.07:38:18.96#ibcon#about to read 3, iclass 34, count 2 2006.225.07:38:18.98#ibcon#read 3, iclass 34, count 2 2006.225.07:38:18.98#ibcon#about to read 4, iclass 34, count 2 2006.225.07:38:18.98#ibcon#read 4, iclass 34, count 2 2006.225.07:38:18.98#ibcon#about to read 5, iclass 34, count 2 2006.225.07:38:18.98#ibcon#read 5, iclass 34, count 2 2006.225.07:38:18.98#ibcon#about to read 6, iclass 34, count 2 2006.225.07:38:18.98#ibcon#read 6, iclass 34, count 2 2006.225.07:38:18.98#ibcon#end of sib2, iclass 34, count 2 2006.225.07:38:18.98#ibcon#*mode == 0, iclass 34, count 2 2006.225.07:38:18.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.07:38:18.98#ibcon#[25=AT04-07\r\n] 2006.225.07:38:18.98#ibcon#*before write, iclass 34, count 2 2006.225.07:38:18.98#ibcon#enter sib2, iclass 34, count 2 2006.225.07:38:18.98#ibcon#flushed, iclass 34, count 2 2006.225.07:38:18.98#ibcon#about to write, iclass 34, count 2 2006.225.07:38:18.98#ibcon#wrote, iclass 34, count 2 2006.225.07:38:18.98#ibcon#about to read 3, iclass 34, count 2 2006.225.07:38:19.01#ibcon#read 3, iclass 34, count 2 2006.225.07:38:19.01#ibcon#about to read 4, iclass 34, count 2 2006.225.07:38:19.01#ibcon#read 4, iclass 34, count 2 2006.225.07:38:19.01#ibcon#about to read 5, iclass 34, count 2 2006.225.07:38:19.01#ibcon#read 5, iclass 34, count 2 2006.225.07:38:19.01#ibcon#about to read 6, iclass 34, count 2 2006.225.07:38:19.01#ibcon#read 6, iclass 34, count 2 2006.225.07:38:19.01#ibcon#end of sib2, iclass 34, count 2 2006.225.07:38:19.01#ibcon#*after write, iclass 34, count 2 2006.225.07:38:19.01#ibcon#*before return 0, iclass 34, count 2 2006.225.07:38:19.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:38:19.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:38:19.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.07:38:19.01#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:19.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:38:19.13#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:38:19.13#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:38:19.13#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:38:19.13#ibcon#first serial, iclass 34, count 0 2006.225.07:38:19.13#ibcon#enter sib2, iclass 34, count 0 2006.225.07:38:19.13#ibcon#flushed, iclass 34, count 0 2006.225.07:38:19.13#ibcon#about to write, iclass 34, count 0 2006.225.07:38:19.13#ibcon#wrote, iclass 34, count 0 2006.225.07:38:19.13#ibcon#about to read 3, iclass 34, count 0 2006.225.07:38:19.15#ibcon#read 3, iclass 34, count 0 2006.225.07:38:19.15#ibcon#about to read 4, iclass 34, count 0 2006.225.07:38:19.15#ibcon#read 4, iclass 34, count 0 2006.225.07:38:19.15#ibcon#about to read 5, iclass 34, count 0 2006.225.07:38:19.15#ibcon#read 5, iclass 34, count 0 2006.225.07:38:19.15#ibcon#about to read 6, iclass 34, count 0 2006.225.07:38:19.15#ibcon#read 6, iclass 34, count 0 2006.225.07:38:19.15#ibcon#end of sib2, iclass 34, count 0 2006.225.07:38:19.15#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:38:19.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:38:19.15#ibcon#[25=USB\r\n] 2006.225.07:38:19.15#ibcon#*before write, iclass 34, count 0 2006.225.07:38:19.15#ibcon#enter sib2, iclass 34, count 0 2006.225.07:38:19.15#ibcon#flushed, iclass 34, count 0 2006.225.07:38:19.15#ibcon#about to write, iclass 34, count 0 2006.225.07:38:19.15#ibcon#wrote, iclass 34, count 0 2006.225.07:38:19.15#ibcon#about to read 3, iclass 34, count 0 2006.225.07:38:19.18#ibcon#read 3, iclass 34, count 0 2006.225.07:38:19.18#ibcon#about to read 4, iclass 34, count 0 2006.225.07:38:19.18#ibcon#read 4, iclass 34, count 0 2006.225.07:38:19.18#ibcon#about to read 5, iclass 34, count 0 2006.225.07:38:19.18#ibcon#read 5, iclass 34, count 0 2006.225.07:38:19.18#ibcon#about to read 6, iclass 34, count 0 2006.225.07:38:19.18#ibcon#read 6, iclass 34, count 0 2006.225.07:38:19.18#ibcon#end of sib2, iclass 34, count 0 2006.225.07:38:19.18#ibcon#*after write, iclass 34, count 0 2006.225.07:38:19.18#ibcon#*before return 0, iclass 34, count 0 2006.225.07:38:19.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:38:19.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:38:19.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:38:19.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:38:19.18$vc4f8/valo=5,652.99 2006.225.07:38:19.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.07:38:19.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.07:38:19.18#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:19.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:38:19.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:38:19.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:38:19.18#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:38:19.18#ibcon#first serial, iclass 36, count 0 2006.225.07:38:19.18#ibcon#enter sib2, iclass 36, count 0 2006.225.07:38:19.18#ibcon#flushed, iclass 36, count 0 2006.225.07:38:19.18#ibcon#about to write, iclass 36, count 0 2006.225.07:38:19.18#ibcon#wrote, iclass 36, count 0 2006.225.07:38:19.18#ibcon#about to read 3, iclass 36, count 0 2006.225.07:38:19.20#ibcon#read 3, iclass 36, count 0 2006.225.07:38:19.20#ibcon#about to read 4, iclass 36, count 0 2006.225.07:38:19.20#ibcon#read 4, iclass 36, count 0 2006.225.07:38:19.20#ibcon#about to read 5, iclass 36, count 0 2006.225.07:38:19.20#ibcon#read 5, iclass 36, count 0 2006.225.07:38:19.20#ibcon#about to read 6, iclass 36, count 0 2006.225.07:38:19.20#ibcon#read 6, iclass 36, count 0 2006.225.07:38:19.20#ibcon#end of sib2, iclass 36, count 0 2006.225.07:38:19.20#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:38:19.20#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:38:19.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:38:19.20#ibcon#*before write, iclass 36, count 0 2006.225.07:38:19.20#ibcon#enter sib2, iclass 36, count 0 2006.225.07:38:19.20#ibcon#flushed, iclass 36, count 0 2006.225.07:38:19.20#ibcon#about to write, iclass 36, count 0 2006.225.07:38:19.20#ibcon#wrote, iclass 36, count 0 2006.225.07:38:19.20#ibcon#about to read 3, iclass 36, count 0 2006.225.07:38:19.24#ibcon#read 3, iclass 36, count 0 2006.225.07:38:19.24#ibcon#about to read 4, iclass 36, count 0 2006.225.07:38:19.24#ibcon#read 4, iclass 36, count 0 2006.225.07:38:19.24#ibcon#about to read 5, iclass 36, count 0 2006.225.07:38:19.24#ibcon#read 5, iclass 36, count 0 2006.225.07:38:19.24#ibcon#about to read 6, iclass 36, count 0 2006.225.07:38:19.24#ibcon#read 6, iclass 36, count 0 2006.225.07:38:19.24#ibcon#end of sib2, iclass 36, count 0 2006.225.07:38:19.24#ibcon#*after write, iclass 36, count 0 2006.225.07:38:19.24#ibcon#*before return 0, iclass 36, count 0 2006.225.07:38:19.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:38:19.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:38:19.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:38:19.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:38:19.24$vc4f8/va=5,7 2006.225.07:38:19.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.07:38:19.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.07:38:19.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:19.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:38:19.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:38:19.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:38:19.30#ibcon#enter wrdev, iclass 38, count 2 2006.225.07:38:19.30#ibcon#first serial, iclass 38, count 2 2006.225.07:38:19.30#ibcon#enter sib2, iclass 38, count 2 2006.225.07:38:19.30#ibcon#flushed, iclass 38, count 2 2006.225.07:38:19.30#ibcon#about to write, iclass 38, count 2 2006.225.07:38:19.30#ibcon#wrote, iclass 38, count 2 2006.225.07:38:19.30#ibcon#about to read 3, iclass 38, count 2 2006.225.07:38:19.32#ibcon#read 3, iclass 38, count 2 2006.225.07:38:19.32#ibcon#about to read 4, iclass 38, count 2 2006.225.07:38:19.32#ibcon#read 4, iclass 38, count 2 2006.225.07:38:19.32#ibcon#about to read 5, iclass 38, count 2 2006.225.07:38:19.32#ibcon#read 5, iclass 38, count 2 2006.225.07:38:19.32#ibcon#about to read 6, iclass 38, count 2 2006.225.07:38:19.32#ibcon#read 6, iclass 38, count 2 2006.225.07:38:19.32#ibcon#end of sib2, iclass 38, count 2 2006.225.07:38:19.32#ibcon#*mode == 0, iclass 38, count 2 2006.225.07:38:19.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.07:38:19.32#ibcon#[25=AT05-07\r\n] 2006.225.07:38:19.32#ibcon#*before write, iclass 38, count 2 2006.225.07:38:19.32#ibcon#enter sib2, iclass 38, count 2 2006.225.07:38:19.32#ibcon#flushed, iclass 38, count 2 2006.225.07:38:19.32#ibcon#about to write, iclass 38, count 2 2006.225.07:38:19.32#ibcon#wrote, iclass 38, count 2 2006.225.07:38:19.32#ibcon#about to read 3, iclass 38, count 2 2006.225.07:38:19.35#ibcon#read 3, iclass 38, count 2 2006.225.07:38:19.35#ibcon#about to read 4, iclass 38, count 2 2006.225.07:38:19.35#ibcon#read 4, iclass 38, count 2 2006.225.07:38:19.35#ibcon#about to read 5, iclass 38, count 2 2006.225.07:38:19.35#ibcon#read 5, iclass 38, count 2 2006.225.07:38:19.35#ibcon#about to read 6, iclass 38, count 2 2006.225.07:38:19.35#ibcon#read 6, iclass 38, count 2 2006.225.07:38:19.35#ibcon#end of sib2, iclass 38, count 2 2006.225.07:38:19.35#ibcon#*after write, iclass 38, count 2 2006.225.07:38:19.35#ibcon#*before return 0, iclass 38, count 2 2006.225.07:38:19.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:38:19.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:38:19.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.07:38:19.35#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:19.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:38:19.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:38:19.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:38:19.47#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:38:19.47#ibcon#first serial, iclass 38, count 0 2006.225.07:38:19.47#ibcon#enter sib2, iclass 38, count 0 2006.225.07:38:19.47#ibcon#flushed, iclass 38, count 0 2006.225.07:38:19.47#ibcon#about to write, iclass 38, count 0 2006.225.07:38:19.47#ibcon#wrote, iclass 38, count 0 2006.225.07:38:19.47#ibcon#about to read 3, iclass 38, count 0 2006.225.07:38:19.49#ibcon#read 3, iclass 38, count 0 2006.225.07:38:19.49#ibcon#about to read 4, iclass 38, count 0 2006.225.07:38:19.49#ibcon#read 4, iclass 38, count 0 2006.225.07:38:19.49#ibcon#about to read 5, iclass 38, count 0 2006.225.07:38:19.49#ibcon#read 5, iclass 38, count 0 2006.225.07:38:19.49#ibcon#about to read 6, iclass 38, count 0 2006.225.07:38:19.49#ibcon#read 6, iclass 38, count 0 2006.225.07:38:19.49#ibcon#end of sib2, iclass 38, count 0 2006.225.07:38:19.49#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:38:19.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:38:19.49#ibcon#[25=USB\r\n] 2006.225.07:38:19.49#ibcon#*before write, iclass 38, count 0 2006.225.07:38:19.49#ibcon#enter sib2, iclass 38, count 0 2006.225.07:38:19.49#ibcon#flushed, iclass 38, count 0 2006.225.07:38:19.49#ibcon#about to write, iclass 38, count 0 2006.225.07:38:19.49#ibcon#wrote, iclass 38, count 0 2006.225.07:38:19.49#ibcon#about to read 3, iclass 38, count 0 2006.225.07:38:19.52#ibcon#read 3, iclass 38, count 0 2006.225.07:38:19.52#ibcon#about to read 4, iclass 38, count 0 2006.225.07:38:19.52#ibcon#read 4, iclass 38, count 0 2006.225.07:38:19.52#ibcon#about to read 5, iclass 38, count 0 2006.225.07:38:19.52#ibcon#read 5, iclass 38, count 0 2006.225.07:38:19.52#ibcon#about to read 6, iclass 38, count 0 2006.225.07:38:19.52#ibcon#read 6, iclass 38, count 0 2006.225.07:38:19.52#ibcon#end of sib2, iclass 38, count 0 2006.225.07:38:19.52#ibcon#*after write, iclass 38, count 0 2006.225.07:38:19.52#ibcon#*before return 0, iclass 38, count 0 2006.225.07:38:19.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:38:19.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:38:19.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:38:19.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:38:19.52$vc4f8/valo=6,772.99 2006.225.07:38:19.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.07:38:19.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.07:38:19.52#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:19.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:38:19.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:38:19.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:38:19.52#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:38:19.52#ibcon#first serial, iclass 40, count 0 2006.225.07:38:19.52#ibcon#enter sib2, iclass 40, count 0 2006.225.07:38:19.52#ibcon#flushed, iclass 40, count 0 2006.225.07:38:19.52#ibcon#about to write, iclass 40, count 0 2006.225.07:38:19.52#ibcon#wrote, iclass 40, count 0 2006.225.07:38:19.52#ibcon#about to read 3, iclass 40, count 0 2006.225.07:38:19.55#ibcon#read 3, iclass 40, count 0 2006.225.07:38:19.55#ibcon#about to read 4, iclass 40, count 0 2006.225.07:38:19.55#ibcon#read 4, iclass 40, count 0 2006.225.07:38:19.55#ibcon#about to read 5, iclass 40, count 0 2006.225.07:38:19.55#ibcon#read 5, iclass 40, count 0 2006.225.07:38:19.55#ibcon#about to read 6, iclass 40, count 0 2006.225.07:38:19.55#ibcon#read 6, iclass 40, count 0 2006.225.07:38:19.55#ibcon#end of sib2, iclass 40, count 0 2006.225.07:38:19.55#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:38:19.55#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:38:19.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:38:19.55#ibcon#*before write, iclass 40, count 0 2006.225.07:38:19.55#ibcon#enter sib2, iclass 40, count 0 2006.225.07:38:19.55#ibcon#flushed, iclass 40, count 0 2006.225.07:38:19.55#ibcon#about to write, iclass 40, count 0 2006.225.07:38:19.55#ibcon#wrote, iclass 40, count 0 2006.225.07:38:19.55#ibcon#about to read 3, iclass 40, count 0 2006.225.07:38:19.59#ibcon#read 3, iclass 40, count 0 2006.225.07:38:19.59#ibcon#about to read 4, iclass 40, count 0 2006.225.07:38:19.59#ibcon#read 4, iclass 40, count 0 2006.225.07:38:19.59#ibcon#about to read 5, iclass 40, count 0 2006.225.07:38:19.59#ibcon#read 5, iclass 40, count 0 2006.225.07:38:19.59#ibcon#about to read 6, iclass 40, count 0 2006.225.07:38:19.59#ibcon#read 6, iclass 40, count 0 2006.225.07:38:19.59#ibcon#end of sib2, iclass 40, count 0 2006.225.07:38:19.59#ibcon#*after write, iclass 40, count 0 2006.225.07:38:19.59#ibcon#*before return 0, iclass 40, count 0 2006.225.07:38:19.59#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:38:19.59#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:38:19.59#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:38:19.59#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:38:19.59$vc4f8/va=6,6 2006.225.07:38:19.59#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.07:38:19.59#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.07:38:19.59#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:19.59#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:38:19.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:38:19.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:38:19.64#ibcon#enter wrdev, iclass 4, count 2 2006.225.07:38:19.64#ibcon#first serial, iclass 4, count 2 2006.225.07:38:19.64#ibcon#enter sib2, iclass 4, count 2 2006.225.07:38:19.64#ibcon#flushed, iclass 4, count 2 2006.225.07:38:19.64#ibcon#about to write, iclass 4, count 2 2006.225.07:38:19.64#ibcon#wrote, iclass 4, count 2 2006.225.07:38:19.64#ibcon#about to read 3, iclass 4, count 2 2006.225.07:38:19.66#ibcon#read 3, iclass 4, count 2 2006.225.07:38:19.66#ibcon#about to read 4, iclass 4, count 2 2006.225.07:38:19.66#ibcon#read 4, iclass 4, count 2 2006.225.07:38:19.66#ibcon#about to read 5, iclass 4, count 2 2006.225.07:38:19.66#ibcon#read 5, iclass 4, count 2 2006.225.07:38:19.66#ibcon#about to read 6, iclass 4, count 2 2006.225.07:38:19.66#ibcon#read 6, iclass 4, count 2 2006.225.07:38:19.66#ibcon#end of sib2, iclass 4, count 2 2006.225.07:38:19.66#ibcon#*mode == 0, iclass 4, count 2 2006.225.07:38:19.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.07:38:19.66#ibcon#[25=AT06-06\r\n] 2006.225.07:38:19.66#ibcon#*before write, iclass 4, count 2 2006.225.07:38:19.66#ibcon#enter sib2, iclass 4, count 2 2006.225.07:38:19.66#ibcon#flushed, iclass 4, count 2 2006.225.07:38:19.66#ibcon#about to write, iclass 4, count 2 2006.225.07:38:19.66#ibcon#wrote, iclass 4, count 2 2006.225.07:38:19.66#ibcon#about to read 3, iclass 4, count 2 2006.225.07:38:19.69#ibcon#read 3, iclass 4, count 2 2006.225.07:38:19.69#ibcon#about to read 4, iclass 4, count 2 2006.225.07:38:19.69#ibcon#read 4, iclass 4, count 2 2006.225.07:38:19.69#ibcon#about to read 5, iclass 4, count 2 2006.225.07:38:19.69#ibcon#read 5, iclass 4, count 2 2006.225.07:38:19.69#ibcon#about to read 6, iclass 4, count 2 2006.225.07:38:19.69#ibcon#read 6, iclass 4, count 2 2006.225.07:38:19.69#ibcon#end of sib2, iclass 4, count 2 2006.225.07:38:19.69#ibcon#*after write, iclass 4, count 2 2006.225.07:38:19.69#ibcon#*before return 0, iclass 4, count 2 2006.225.07:38:19.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:38:19.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:38:19.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.07:38:19.69#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:19.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:38:19.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:38:19.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:38:19.81#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:38:19.81#ibcon#first serial, iclass 4, count 0 2006.225.07:38:19.81#ibcon#enter sib2, iclass 4, count 0 2006.225.07:38:19.81#ibcon#flushed, iclass 4, count 0 2006.225.07:38:19.81#ibcon#about to write, iclass 4, count 0 2006.225.07:38:19.81#ibcon#wrote, iclass 4, count 0 2006.225.07:38:19.81#ibcon#about to read 3, iclass 4, count 0 2006.225.07:38:19.83#ibcon#read 3, iclass 4, count 0 2006.225.07:38:19.83#ibcon#about to read 4, iclass 4, count 0 2006.225.07:38:19.83#ibcon#read 4, iclass 4, count 0 2006.225.07:38:19.83#ibcon#about to read 5, iclass 4, count 0 2006.225.07:38:19.83#ibcon#read 5, iclass 4, count 0 2006.225.07:38:19.83#ibcon#about to read 6, iclass 4, count 0 2006.225.07:38:19.83#ibcon#read 6, iclass 4, count 0 2006.225.07:38:19.83#ibcon#end of sib2, iclass 4, count 0 2006.225.07:38:19.83#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:38:19.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:38:19.83#ibcon#[25=USB\r\n] 2006.225.07:38:19.83#ibcon#*before write, iclass 4, count 0 2006.225.07:38:19.83#ibcon#enter sib2, iclass 4, count 0 2006.225.07:38:19.83#ibcon#flushed, iclass 4, count 0 2006.225.07:38:19.83#ibcon#about to write, iclass 4, count 0 2006.225.07:38:19.83#ibcon#wrote, iclass 4, count 0 2006.225.07:38:19.83#ibcon#about to read 3, iclass 4, count 0 2006.225.07:38:19.86#ibcon#read 3, iclass 4, count 0 2006.225.07:38:19.86#ibcon#about to read 4, iclass 4, count 0 2006.225.07:38:19.86#ibcon#read 4, iclass 4, count 0 2006.225.07:38:19.86#ibcon#about to read 5, iclass 4, count 0 2006.225.07:38:19.86#ibcon#read 5, iclass 4, count 0 2006.225.07:38:19.86#ibcon#about to read 6, iclass 4, count 0 2006.225.07:38:19.86#ibcon#read 6, iclass 4, count 0 2006.225.07:38:19.86#ibcon#end of sib2, iclass 4, count 0 2006.225.07:38:19.86#ibcon#*after write, iclass 4, count 0 2006.225.07:38:19.86#ibcon#*before return 0, iclass 4, count 0 2006.225.07:38:19.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:38:19.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:38:19.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:38:19.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:38:19.86$vc4f8/valo=7,832.99 2006.225.07:38:19.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.07:38:19.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.07:38:19.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:19.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:38:19.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:38:19.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:38:19.86#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:38:19.86#ibcon#first serial, iclass 6, count 0 2006.225.07:38:19.86#ibcon#enter sib2, iclass 6, count 0 2006.225.07:38:19.86#ibcon#flushed, iclass 6, count 0 2006.225.07:38:19.86#ibcon#about to write, iclass 6, count 0 2006.225.07:38:19.86#ibcon#wrote, iclass 6, count 0 2006.225.07:38:19.86#ibcon#about to read 3, iclass 6, count 0 2006.225.07:38:19.88#ibcon#read 3, iclass 6, count 0 2006.225.07:38:19.88#ibcon#about to read 4, iclass 6, count 0 2006.225.07:38:19.88#ibcon#read 4, iclass 6, count 0 2006.225.07:38:19.88#ibcon#about to read 5, iclass 6, count 0 2006.225.07:38:19.88#ibcon#read 5, iclass 6, count 0 2006.225.07:38:19.88#ibcon#about to read 6, iclass 6, count 0 2006.225.07:38:19.88#ibcon#read 6, iclass 6, count 0 2006.225.07:38:19.88#ibcon#end of sib2, iclass 6, count 0 2006.225.07:38:19.88#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:38:19.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:38:19.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:38:19.88#ibcon#*before write, iclass 6, count 0 2006.225.07:38:19.88#ibcon#enter sib2, iclass 6, count 0 2006.225.07:38:19.88#ibcon#flushed, iclass 6, count 0 2006.225.07:38:19.88#ibcon#about to write, iclass 6, count 0 2006.225.07:38:19.88#ibcon#wrote, iclass 6, count 0 2006.225.07:38:19.88#ibcon#about to read 3, iclass 6, count 0 2006.225.07:38:19.92#ibcon#read 3, iclass 6, count 0 2006.225.07:38:19.92#ibcon#about to read 4, iclass 6, count 0 2006.225.07:38:19.92#ibcon#read 4, iclass 6, count 0 2006.225.07:38:19.92#ibcon#about to read 5, iclass 6, count 0 2006.225.07:38:19.92#ibcon#read 5, iclass 6, count 0 2006.225.07:38:19.92#ibcon#about to read 6, iclass 6, count 0 2006.225.07:38:19.92#ibcon#read 6, iclass 6, count 0 2006.225.07:38:19.92#ibcon#end of sib2, iclass 6, count 0 2006.225.07:38:19.92#ibcon#*after write, iclass 6, count 0 2006.225.07:38:19.92#ibcon#*before return 0, iclass 6, count 0 2006.225.07:38:19.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:38:19.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:38:19.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:38:19.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:38:19.92$vc4f8/va=7,6 2006.225.07:38:19.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.225.07:38:19.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.225.07:38:19.92#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:19.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:38:19.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:38:19.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:38:19.98#ibcon#enter wrdev, iclass 10, count 2 2006.225.07:38:19.98#ibcon#first serial, iclass 10, count 2 2006.225.07:38:19.98#ibcon#enter sib2, iclass 10, count 2 2006.225.07:38:19.98#ibcon#flushed, iclass 10, count 2 2006.225.07:38:19.98#ibcon#about to write, iclass 10, count 2 2006.225.07:38:19.98#ibcon#wrote, iclass 10, count 2 2006.225.07:38:19.98#ibcon#about to read 3, iclass 10, count 2 2006.225.07:38:20.00#ibcon#read 3, iclass 10, count 2 2006.225.07:38:20.00#ibcon#about to read 4, iclass 10, count 2 2006.225.07:38:20.00#ibcon#read 4, iclass 10, count 2 2006.225.07:38:20.00#ibcon#about to read 5, iclass 10, count 2 2006.225.07:38:20.00#ibcon#read 5, iclass 10, count 2 2006.225.07:38:20.00#ibcon#about to read 6, iclass 10, count 2 2006.225.07:38:20.00#ibcon#read 6, iclass 10, count 2 2006.225.07:38:20.00#ibcon#end of sib2, iclass 10, count 2 2006.225.07:38:20.00#ibcon#*mode == 0, iclass 10, count 2 2006.225.07:38:20.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.225.07:38:20.00#ibcon#[25=AT07-06\r\n] 2006.225.07:38:20.00#ibcon#*before write, iclass 10, count 2 2006.225.07:38:20.00#ibcon#enter sib2, iclass 10, count 2 2006.225.07:38:20.00#ibcon#flushed, iclass 10, count 2 2006.225.07:38:20.00#ibcon#about to write, iclass 10, count 2 2006.225.07:38:20.00#ibcon#wrote, iclass 10, count 2 2006.225.07:38:20.00#ibcon#about to read 3, iclass 10, count 2 2006.225.07:38:20.03#ibcon#read 3, iclass 10, count 2 2006.225.07:38:20.03#ibcon#about to read 4, iclass 10, count 2 2006.225.07:38:20.03#ibcon#read 4, iclass 10, count 2 2006.225.07:38:20.03#ibcon#about to read 5, iclass 10, count 2 2006.225.07:38:20.03#ibcon#read 5, iclass 10, count 2 2006.225.07:38:20.03#ibcon#about to read 6, iclass 10, count 2 2006.225.07:38:20.03#ibcon#read 6, iclass 10, count 2 2006.225.07:38:20.03#ibcon#end of sib2, iclass 10, count 2 2006.225.07:38:20.03#ibcon#*after write, iclass 10, count 2 2006.225.07:38:20.03#ibcon#*before return 0, iclass 10, count 2 2006.225.07:38:20.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:38:20.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:38:20.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.225.07:38:20.03#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:20.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:38:20.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:38:20.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:38:20.15#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:38:20.15#ibcon#first serial, iclass 10, count 0 2006.225.07:38:20.15#ibcon#enter sib2, iclass 10, count 0 2006.225.07:38:20.15#ibcon#flushed, iclass 10, count 0 2006.225.07:38:20.15#ibcon#about to write, iclass 10, count 0 2006.225.07:38:20.15#ibcon#wrote, iclass 10, count 0 2006.225.07:38:20.15#ibcon#about to read 3, iclass 10, count 0 2006.225.07:38:20.17#ibcon#read 3, iclass 10, count 0 2006.225.07:38:20.17#ibcon#about to read 4, iclass 10, count 0 2006.225.07:38:20.17#ibcon#read 4, iclass 10, count 0 2006.225.07:38:20.17#ibcon#about to read 5, iclass 10, count 0 2006.225.07:38:20.17#ibcon#read 5, iclass 10, count 0 2006.225.07:38:20.17#ibcon#about to read 6, iclass 10, count 0 2006.225.07:38:20.17#ibcon#read 6, iclass 10, count 0 2006.225.07:38:20.17#ibcon#end of sib2, iclass 10, count 0 2006.225.07:38:20.17#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:38:20.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:38:20.17#ibcon#[25=USB\r\n] 2006.225.07:38:20.17#ibcon#*before write, iclass 10, count 0 2006.225.07:38:20.17#ibcon#enter sib2, iclass 10, count 0 2006.225.07:38:20.17#ibcon#flushed, iclass 10, count 0 2006.225.07:38:20.17#ibcon#about to write, iclass 10, count 0 2006.225.07:38:20.17#ibcon#wrote, iclass 10, count 0 2006.225.07:38:20.17#ibcon#about to read 3, iclass 10, count 0 2006.225.07:38:20.20#ibcon#read 3, iclass 10, count 0 2006.225.07:38:20.20#ibcon#about to read 4, iclass 10, count 0 2006.225.07:38:20.20#ibcon#read 4, iclass 10, count 0 2006.225.07:38:20.20#ibcon#about to read 5, iclass 10, count 0 2006.225.07:38:20.20#ibcon#read 5, iclass 10, count 0 2006.225.07:38:20.20#ibcon#about to read 6, iclass 10, count 0 2006.225.07:38:20.20#ibcon#read 6, iclass 10, count 0 2006.225.07:38:20.20#ibcon#end of sib2, iclass 10, count 0 2006.225.07:38:20.20#ibcon#*after write, iclass 10, count 0 2006.225.07:38:20.20#ibcon#*before return 0, iclass 10, count 0 2006.225.07:38:20.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:38:20.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:38:20.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:38:20.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:38:20.20$vc4f8/valo=8,852.99 2006.225.07:38:20.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.07:38:20.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.07:38:20.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:20.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:38:20.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:38:20.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:38:20.20#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:38:20.20#ibcon#first serial, iclass 12, count 0 2006.225.07:38:20.20#ibcon#enter sib2, iclass 12, count 0 2006.225.07:38:20.20#ibcon#flushed, iclass 12, count 0 2006.225.07:38:20.20#ibcon#about to write, iclass 12, count 0 2006.225.07:38:20.20#ibcon#wrote, iclass 12, count 0 2006.225.07:38:20.20#ibcon#about to read 3, iclass 12, count 0 2006.225.07:38:20.22#ibcon#read 3, iclass 12, count 0 2006.225.07:38:20.22#ibcon#about to read 4, iclass 12, count 0 2006.225.07:38:20.22#ibcon#read 4, iclass 12, count 0 2006.225.07:38:20.22#ibcon#about to read 5, iclass 12, count 0 2006.225.07:38:20.22#ibcon#read 5, iclass 12, count 0 2006.225.07:38:20.22#ibcon#about to read 6, iclass 12, count 0 2006.225.07:38:20.22#ibcon#read 6, iclass 12, count 0 2006.225.07:38:20.22#ibcon#end of sib2, iclass 12, count 0 2006.225.07:38:20.22#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:38:20.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:38:20.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:38:20.22#ibcon#*before write, iclass 12, count 0 2006.225.07:38:20.22#ibcon#enter sib2, iclass 12, count 0 2006.225.07:38:20.22#ibcon#flushed, iclass 12, count 0 2006.225.07:38:20.22#ibcon#about to write, iclass 12, count 0 2006.225.07:38:20.22#ibcon#wrote, iclass 12, count 0 2006.225.07:38:20.22#ibcon#about to read 3, iclass 12, count 0 2006.225.07:38:20.26#ibcon#read 3, iclass 12, count 0 2006.225.07:38:20.26#ibcon#about to read 4, iclass 12, count 0 2006.225.07:38:20.26#ibcon#read 4, iclass 12, count 0 2006.225.07:38:20.26#ibcon#about to read 5, iclass 12, count 0 2006.225.07:38:20.26#ibcon#read 5, iclass 12, count 0 2006.225.07:38:20.26#ibcon#about to read 6, iclass 12, count 0 2006.225.07:38:20.26#ibcon#read 6, iclass 12, count 0 2006.225.07:38:20.26#ibcon#end of sib2, iclass 12, count 0 2006.225.07:38:20.26#ibcon#*after write, iclass 12, count 0 2006.225.07:38:20.26#ibcon#*before return 0, iclass 12, count 0 2006.225.07:38:20.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:38:20.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:38:20.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:38:20.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:38:20.26$vc4f8/va=8,7 2006.225.07:38:20.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.225.07:38:20.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.225.07:38:20.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:20.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:38:20.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:38:20.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:38:20.32#ibcon#enter wrdev, iclass 14, count 2 2006.225.07:38:20.32#ibcon#first serial, iclass 14, count 2 2006.225.07:38:20.32#ibcon#enter sib2, iclass 14, count 2 2006.225.07:38:20.32#ibcon#flushed, iclass 14, count 2 2006.225.07:38:20.32#ibcon#about to write, iclass 14, count 2 2006.225.07:38:20.32#ibcon#wrote, iclass 14, count 2 2006.225.07:38:20.32#ibcon#about to read 3, iclass 14, count 2 2006.225.07:38:20.34#ibcon#read 3, iclass 14, count 2 2006.225.07:38:20.34#ibcon#about to read 4, iclass 14, count 2 2006.225.07:38:20.34#ibcon#read 4, iclass 14, count 2 2006.225.07:38:20.34#ibcon#about to read 5, iclass 14, count 2 2006.225.07:38:20.34#ibcon#read 5, iclass 14, count 2 2006.225.07:38:20.34#ibcon#about to read 6, iclass 14, count 2 2006.225.07:38:20.34#ibcon#read 6, iclass 14, count 2 2006.225.07:38:20.34#ibcon#end of sib2, iclass 14, count 2 2006.225.07:38:20.34#ibcon#*mode == 0, iclass 14, count 2 2006.225.07:38:20.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.225.07:38:20.34#ibcon#[25=AT08-07\r\n] 2006.225.07:38:20.34#ibcon#*before write, iclass 14, count 2 2006.225.07:38:20.34#ibcon#enter sib2, iclass 14, count 2 2006.225.07:38:20.34#ibcon#flushed, iclass 14, count 2 2006.225.07:38:20.34#ibcon#about to write, iclass 14, count 2 2006.225.07:38:20.34#ibcon#wrote, iclass 14, count 2 2006.225.07:38:20.34#ibcon#about to read 3, iclass 14, count 2 2006.225.07:38:20.37#ibcon#read 3, iclass 14, count 2 2006.225.07:38:20.37#ibcon#about to read 4, iclass 14, count 2 2006.225.07:38:20.37#ibcon#read 4, iclass 14, count 2 2006.225.07:38:20.37#ibcon#about to read 5, iclass 14, count 2 2006.225.07:38:20.37#ibcon#read 5, iclass 14, count 2 2006.225.07:38:20.37#ibcon#about to read 6, iclass 14, count 2 2006.225.07:38:20.37#ibcon#read 6, iclass 14, count 2 2006.225.07:38:20.37#ibcon#end of sib2, iclass 14, count 2 2006.225.07:38:20.37#ibcon#*after write, iclass 14, count 2 2006.225.07:38:20.37#ibcon#*before return 0, iclass 14, count 2 2006.225.07:38:20.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:38:20.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:38:20.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.225.07:38:20.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:20.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:38:20.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:38:20.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:38:20.49#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:38:20.49#ibcon#first serial, iclass 14, count 0 2006.225.07:38:20.49#ibcon#enter sib2, iclass 14, count 0 2006.225.07:38:20.49#ibcon#flushed, iclass 14, count 0 2006.225.07:38:20.49#ibcon#about to write, iclass 14, count 0 2006.225.07:38:20.49#ibcon#wrote, iclass 14, count 0 2006.225.07:38:20.49#ibcon#about to read 3, iclass 14, count 0 2006.225.07:38:20.51#ibcon#read 3, iclass 14, count 0 2006.225.07:38:20.51#ibcon#about to read 4, iclass 14, count 0 2006.225.07:38:20.51#ibcon#read 4, iclass 14, count 0 2006.225.07:38:20.51#ibcon#about to read 5, iclass 14, count 0 2006.225.07:38:20.51#ibcon#read 5, iclass 14, count 0 2006.225.07:38:20.51#ibcon#about to read 6, iclass 14, count 0 2006.225.07:38:20.51#ibcon#read 6, iclass 14, count 0 2006.225.07:38:20.51#ibcon#end of sib2, iclass 14, count 0 2006.225.07:38:20.51#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:38:20.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:38:20.51#ibcon#[25=USB\r\n] 2006.225.07:38:20.51#ibcon#*before write, iclass 14, count 0 2006.225.07:38:20.51#ibcon#enter sib2, iclass 14, count 0 2006.225.07:38:20.51#ibcon#flushed, iclass 14, count 0 2006.225.07:38:20.51#ibcon#about to write, iclass 14, count 0 2006.225.07:38:20.51#ibcon#wrote, iclass 14, count 0 2006.225.07:38:20.51#ibcon#about to read 3, iclass 14, count 0 2006.225.07:38:20.54#ibcon#read 3, iclass 14, count 0 2006.225.07:38:20.54#ibcon#about to read 4, iclass 14, count 0 2006.225.07:38:20.54#ibcon#read 4, iclass 14, count 0 2006.225.07:38:20.54#ibcon#about to read 5, iclass 14, count 0 2006.225.07:38:20.54#ibcon#read 5, iclass 14, count 0 2006.225.07:38:20.54#ibcon#about to read 6, iclass 14, count 0 2006.225.07:38:20.54#ibcon#read 6, iclass 14, count 0 2006.225.07:38:20.54#ibcon#end of sib2, iclass 14, count 0 2006.225.07:38:20.54#ibcon#*after write, iclass 14, count 0 2006.225.07:38:20.54#ibcon#*before return 0, iclass 14, count 0 2006.225.07:38:20.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:38:20.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:38:20.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:38:20.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:38:20.54$vc4f8/vblo=1,632.99 2006.225.07:38:20.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.07:38:20.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.07:38:20.54#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:20.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:38:20.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:38:20.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:38:20.54#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:38:20.54#ibcon#first serial, iclass 16, count 0 2006.225.07:38:20.54#ibcon#enter sib2, iclass 16, count 0 2006.225.07:38:20.54#ibcon#flushed, iclass 16, count 0 2006.225.07:38:20.54#ibcon#about to write, iclass 16, count 0 2006.225.07:38:20.54#ibcon#wrote, iclass 16, count 0 2006.225.07:38:20.54#ibcon#about to read 3, iclass 16, count 0 2006.225.07:38:20.56#ibcon#read 3, iclass 16, count 0 2006.225.07:38:20.56#ibcon#about to read 4, iclass 16, count 0 2006.225.07:38:20.56#ibcon#read 4, iclass 16, count 0 2006.225.07:38:20.56#ibcon#about to read 5, iclass 16, count 0 2006.225.07:38:20.56#ibcon#read 5, iclass 16, count 0 2006.225.07:38:20.56#ibcon#about to read 6, iclass 16, count 0 2006.225.07:38:20.56#ibcon#read 6, iclass 16, count 0 2006.225.07:38:20.56#ibcon#end of sib2, iclass 16, count 0 2006.225.07:38:20.56#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:38:20.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:38:20.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:38:20.56#ibcon#*before write, iclass 16, count 0 2006.225.07:38:20.56#ibcon#enter sib2, iclass 16, count 0 2006.225.07:38:20.56#ibcon#flushed, iclass 16, count 0 2006.225.07:38:20.56#ibcon#about to write, iclass 16, count 0 2006.225.07:38:20.56#ibcon#wrote, iclass 16, count 0 2006.225.07:38:20.56#ibcon#about to read 3, iclass 16, count 0 2006.225.07:38:20.60#ibcon#read 3, iclass 16, count 0 2006.225.07:38:20.60#ibcon#about to read 4, iclass 16, count 0 2006.225.07:38:20.60#ibcon#read 4, iclass 16, count 0 2006.225.07:38:20.60#ibcon#about to read 5, iclass 16, count 0 2006.225.07:38:20.60#ibcon#read 5, iclass 16, count 0 2006.225.07:38:20.60#ibcon#about to read 6, iclass 16, count 0 2006.225.07:38:20.60#ibcon#read 6, iclass 16, count 0 2006.225.07:38:20.60#ibcon#end of sib2, iclass 16, count 0 2006.225.07:38:20.60#ibcon#*after write, iclass 16, count 0 2006.225.07:38:20.60#ibcon#*before return 0, iclass 16, count 0 2006.225.07:38:20.60#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:38:20.60#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:38:20.60#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:38:20.60#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:38:20.60$vc4f8/vb=1,4 2006.225.07:38:20.60#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.225.07:38:20.60#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.225.07:38:20.60#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:20.60#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:38:20.60#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:38:20.60#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:38:20.60#ibcon#enter wrdev, iclass 18, count 2 2006.225.07:38:20.60#ibcon#first serial, iclass 18, count 2 2006.225.07:38:20.60#ibcon#enter sib2, iclass 18, count 2 2006.225.07:38:20.60#ibcon#flushed, iclass 18, count 2 2006.225.07:38:20.60#ibcon#about to write, iclass 18, count 2 2006.225.07:38:20.60#ibcon#wrote, iclass 18, count 2 2006.225.07:38:20.60#ibcon#about to read 3, iclass 18, count 2 2006.225.07:38:20.62#ibcon#read 3, iclass 18, count 2 2006.225.07:38:20.62#ibcon#about to read 4, iclass 18, count 2 2006.225.07:38:20.62#ibcon#read 4, iclass 18, count 2 2006.225.07:38:20.62#ibcon#about to read 5, iclass 18, count 2 2006.225.07:38:20.62#ibcon#read 5, iclass 18, count 2 2006.225.07:38:20.62#ibcon#about to read 6, iclass 18, count 2 2006.225.07:38:20.62#ibcon#read 6, iclass 18, count 2 2006.225.07:38:20.62#ibcon#end of sib2, iclass 18, count 2 2006.225.07:38:20.62#ibcon#*mode == 0, iclass 18, count 2 2006.225.07:38:20.62#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.225.07:38:20.62#ibcon#[27=AT01-04\r\n] 2006.225.07:38:20.62#ibcon#*before write, iclass 18, count 2 2006.225.07:38:20.62#ibcon#enter sib2, iclass 18, count 2 2006.225.07:38:20.62#ibcon#flushed, iclass 18, count 2 2006.225.07:38:20.62#ibcon#about to write, iclass 18, count 2 2006.225.07:38:20.62#ibcon#wrote, iclass 18, count 2 2006.225.07:38:20.62#ibcon#about to read 3, iclass 18, count 2 2006.225.07:38:20.65#ibcon#read 3, iclass 18, count 2 2006.225.07:38:20.65#ibcon#about to read 4, iclass 18, count 2 2006.225.07:38:20.65#ibcon#read 4, iclass 18, count 2 2006.225.07:38:20.65#ibcon#about to read 5, iclass 18, count 2 2006.225.07:38:20.65#ibcon#read 5, iclass 18, count 2 2006.225.07:38:20.65#ibcon#about to read 6, iclass 18, count 2 2006.225.07:38:20.65#ibcon#read 6, iclass 18, count 2 2006.225.07:38:20.65#ibcon#end of sib2, iclass 18, count 2 2006.225.07:38:20.65#ibcon#*after write, iclass 18, count 2 2006.225.07:38:20.65#ibcon#*before return 0, iclass 18, count 2 2006.225.07:38:20.65#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:38:20.65#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:38:20.65#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.225.07:38:20.65#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:20.65#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:38:20.67#abcon#<5=/07 3.1 5.4 27.91 711003.2\r\n> 2006.225.07:38:20.69#abcon#{5=INTERFACE CLEAR} 2006.225.07:38:20.75#abcon#[5=S1D000X0/0*\r\n] 2006.225.07:38:20.77#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:38:20.77#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:38:20.77#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:38:20.77#ibcon#first serial, iclass 18, count 0 2006.225.07:38:20.77#ibcon#enter sib2, iclass 18, count 0 2006.225.07:38:20.77#ibcon#flushed, iclass 18, count 0 2006.225.07:38:20.77#ibcon#about to write, iclass 18, count 0 2006.225.07:38:20.77#ibcon#wrote, iclass 18, count 0 2006.225.07:38:20.77#ibcon#about to read 3, iclass 18, count 0 2006.225.07:38:20.79#ibcon#read 3, iclass 18, count 0 2006.225.07:38:20.79#ibcon#about to read 4, iclass 18, count 0 2006.225.07:38:20.79#ibcon#read 4, iclass 18, count 0 2006.225.07:38:20.79#ibcon#about to read 5, iclass 18, count 0 2006.225.07:38:20.79#ibcon#read 5, iclass 18, count 0 2006.225.07:38:20.79#ibcon#about to read 6, iclass 18, count 0 2006.225.07:38:20.79#ibcon#read 6, iclass 18, count 0 2006.225.07:38:20.79#ibcon#end of sib2, iclass 18, count 0 2006.225.07:38:20.79#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:38:20.79#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:38:20.79#ibcon#[27=USB\r\n] 2006.225.07:38:20.79#ibcon#*before write, iclass 18, count 0 2006.225.07:38:20.79#ibcon#enter sib2, iclass 18, count 0 2006.225.07:38:20.79#ibcon#flushed, iclass 18, count 0 2006.225.07:38:20.79#ibcon#about to write, iclass 18, count 0 2006.225.07:38:20.79#ibcon#wrote, iclass 18, count 0 2006.225.07:38:20.79#ibcon#about to read 3, iclass 18, count 0 2006.225.07:38:20.82#ibcon#read 3, iclass 18, count 0 2006.225.07:38:20.82#ibcon#about to read 4, iclass 18, count 0 2006.225.07:38:20.82#ibcon#read 4, iclass 18, count 0 2006.225.07:38:20.82#ibcon#about to read 5, iclass 18, count 0 2006.225.07:38:20.82#ibcon#read 5, iclass 18, count 0 2006.225.07:38:20.82#ibcon#about to read 6, iclass 18, count 0 2006.225.07:38:20.82#ibcon#read 6, iclass 18, count 0 2006.225.07:38:20.82#ibcon#end of sib2, iclass 18, count 0 2006.225.07:38:20.82#ibcon#*after write, iclass 18, count 0 2006.225.07:38:20.82#ibcon#*before return 0, iclass 18, count 0 2006.225.07:38:20.82#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:38:20.82#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:38:20.82#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:38:20.82#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:38:20.82$vc4f8/vblo=2,640.99 2006.225.07:38:20.82#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.07:38:20.82#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.07:38:20.82#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:20.82#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:38:20.82#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:38:20.82#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:38:20.82#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:38:20.82#ibcon#first serial, iclass 24, count 0 2006.225.07:38:20.82#ibcon#enter sib2, iclass 24, count 0 2006.225.07:38:20.82#ibcon#flushed, iclass 24, count 0 2006.225.07:38:20.82#ibcon#about to write, iclass 24, count 0 2006.225.07:38:20.82#ibcon#wrote, iclass 24, count 0 2006.225.07:38:20.82#ibcon#about to read 3, iclass 24, count 0 2006.225.07:38:20.84#ibcon#read 3, iclass 24, count 0 2006.225.07:38:20.84#ibcon#about to read 4, iclass 24, count 0 2006.225.07:38:20.84#ibcon#read 4, iclass 24, count 0 2006.225.07:38:20.84#ibcon#about to read 5, iclass 24, count 0 2006.225.07:38:20.84#ibcon#read 5, iclass 24, count 0 2006.225.07:38:20.84#ibcon#about to read 6, iclass 24, count 0 2006.225.07:38:20.84#ibcon#read 6, iclass 24, count 0 2006.225.07:38:20.84#ibcon#end of sib2, iclass 24, count 0 2006.225.07:38:20.84#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:38:20.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:38:20.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:38:20.84#ibcon#*before write, iclass 24, count 0 2006.225.07:38:20.84#ibcon#enter sib2, iclass 24, count 0 2006.225.07:38:20.84#ibcon#flushed, iclass 24, count 0 2006.225.07:38:20.84#ibcon#about to write, iclass 24, count 0 2006.225.07:38:20.84#ibcon#wrote, iclass 24, count 0 2006.225.07:38:20.84#ibcon#about to read 3, iclass 24, count 0 2006.225.07:38:20.88#ibcon#read 3, iclass 24, count 0 2006.225.07:38:20.88#ibcon#about to read 4, iclass 24, count 0 2006.225.07:38:20.88#ibcon#read 4, iclass 24, count 0 2006.225.07:38:20.88#ibcon#about to read 5, iclass 24, count 0 2006.225.07:38:20.88#ibcon#read 5, iclass 24, count 0 2006.225.07:38:20.88#ibcon#about to read 6, iclass 24, count 0 2006.225.07:38:20.88#ibcon#read 6, iclass 24, count 0 2006.225.07:38:20.88#ibcon#end of sib2, iclass 24, count 0 2006.225.07:38:20.88#ibcon#*after write, iclass 24, count 0 2006.225.07:38:20.88#ibcon#*before return 0, iclass 24, count 0 2006.225.07:38:20.88#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:38:20.88#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:38:20.88#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:38:20.88#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:38:20.88$vc4f8/vb=2,4 2006.225.07:38:20.88#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.225.07:38:20.88#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.225.07:38:20.88#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:20.88#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:38:20.94#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:38:20.94#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:38:20.94#ibcon#enter wrdev, iclass 26, count 2 2006.225.07:38:20.94#ibcon#first serial, iclass 26, count 2 2006.225.07:38:20.94#ibcon#enter sib2, iclass 26, count 2 2006.225.07:38:20.94#ibcon#flushed, iclass 26, count 2 2006.225.07:38:20.94#ibcon#about to write, iclass 26, count 2 2006.225.07:38:20.94#ibcon#wrote, iclass 26, count 2 2006.225.07:38:20.94#ibcon#about to read 3, iclass 26, count 2 2006.225.07:38:20.96#ibcon#read 3, iclass 26, count 2 2006.225.07:38:20.96#ibcon#about to read 4, iclass 26, count 2 2006.225.07:38:20.96#ibcon#read 4, iclass 26, count 2 2006.225.07:38:20.96#ibcon#about to read 5, iclass 26, count 2 2006.225.07:38:20.96#ibcon#read 5, iclass 26, count 2 2006.225.07:38:20.96#ibcon#about to read 6, iclass 26, count 2 2006.225.07:38:20.96#ibcon#read 6, iclass 26, count 2 2006.225.07:38:20.96#ibcon#end of sib2, iclass 26, count 2 2006.225.07:38:20.96#ibcon#*mode == 0, iclass 26, count 2 2006.225.07:38:20.96#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.225.07:38:20.96#ibcon#[27=AT02-04\r\n] 2006.225.07:38:20.96#ibcon#*before write, iclass 26, count 2 2006.225.07:38:20.96#ibcon#enter sib2, iclass 26, count 2 2006.225.07:38:20.96#ibcon#flushed, iclass 26, count 2 2006.225.07:38:20.96#ibcon#about to write, iclass 26, count 2 2006.225.07:38:20.96#ibcon#wrote, iclass 26, count 2 2006.225.07:38:20.96#ibcon#about to read 3, iclass 26, count 2 2006.225.07:38:20.99#ibcon#read 3, iclass 26, count 2 2006.225.07:38:20.99#ibcon#about to read 4, iclass 26, count 2 2006.225.07:38:20.99#ibcon#read 4, iclass 26, count 2 2006.225.07:38:20.99#ibcon#about to read 5, iclass 26, count 2 2006.225.07:38:20.99#ibcon#read 5, iclass 26, count 2 2006.225.07:38:20.99#ibcon#about to read 6, iclass 26, count 2 2006.225.07:38:20.99#ibcon#read 6, iclass 26, count 2 2006.225.07:38:20.99#ibcon#end of sib2, iclass 26, count 2 2006.225.07:38:20.99#ibcon#*after write, iclass 26, count 2 2006.225.07:38:20.99#ibcon#*before return 0, iclass 26, count 2 2006.225.07:38:20.99#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:38:20.99#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:38:20.99#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.225.07:38:20.99#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:20.99#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:38:21.11#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:38:21.11#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:38:21.11#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:38:21.11#ibcon#first serial, iclass 26, count 0 2006.225.07:38:21.11#ibcon#enter sib2, iclass 26, count 0 2006.225.07:38:21.11#ibcon#flushed, iclass 26, count 0 2006.225.07:38:21.11#ibcon#about to write, iclass 26, count 0 2006.225.07:38:21.11#ibcon#wrote, iclass 26, count 0 2006.225.07:38:21.11#ibcon#about to read 3, iclass 26, count 0 2006.225.07:38:21.13#ibcon#read 3, iclass 26, count 0 2006.225.07:38:21.13#ibcon#about to read 4, iclass 26, count 0 2006.225.07:38:21.13#ibcon#read 4, iclass 26, count 0 2006.225.07:38:21.13#ibcon#about to read 5, iclass 26, count 0 2006.225.07:38:21.13#ibcon#read 5, iclass 26, count 0 2006.225.07:38:21.13#ibcon#about to read 6, iclass 26, count 0 2006.225.07:38:21.13#ibcon#read 6, iclass 26, count 0 2006.225.07:38:21.13#ibcon#end of sib2, iclass 26, count 0 2006.225.07:38:21.13#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:38:21.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:38:21.13#ibcon#[27=USB\r\n] 2006.225.07:38:21.13#ibcon#*before write, iclass 26, count 0 2006.225.07:38:21.13#ibcon#enter sib2, iclass 26, count 0 2006.225.07:38:21.13#ibcon#flushed, iclass 26, count 0 2006.225.07:38:21.13#ibcon#about to write, iclass 26, count 0 2006.225.07:38:21.13#ibcon#wrote, iclass 26, count 0 2006.225.07:38:21.13#ibcon#about to read 3, iclass 26, count 0 2006.225.07:38:21.16#ibcon#read 3, iclass 26, count 0 2006.225.07:38:21.16#ibcon#about to read 4, iclass 26, count 0 2006.225.07:38:21.16#ibcon#read 4, iclass 26, count 0 2006.225.07:38:21.16#ibcon#about to read 5, iclass 26, count 0 2006.225.07:38:21.16#ibcon#read 5, iclass 26, count 0 2006.225.07:38:21.16#ibcon#about to read 6, iclass 26, count 0 2006.225.07:38:21.16#ibcon#read 6, iclass 26, count 0 2006.225.07:38:21.16#ibcon#end of sib2, iclass 26, count 0 2006.225.07:38:21.16#ibcon#*after write, iclass 26, count 0 2006.225.07:38:21.16#ibcon#*before return 0, iclass 26, count 0 2006.225.07:38:21.16#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:38:21.16#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:38:21.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:38:21.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:38:21.16$vc4f8/vblo=3,656.99 2006.225.07:38:21.16#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.07:38:21.16#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.07:38:21.16#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:21.16#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:38:21.16#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:38:21.16#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:38:21.16#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:38:21.16#ibcon#first serial, iclass 28, count 0 2006.225.07:38:21.16#ibcon#enter sib2, iclass 28, count 0 2006.225.07:38:21.16#ibcon#flushed, iclass 28, count 0 2006.225.07:38:21.16#ibcon#about to write, iclass 28, count 0 2006.225.07:38:21.16#ibcon#wrote, iclass 28, count 0 2006.225.07:38:21.16#ibcon#about to read 3, iclass 28, count 0 2006.225.07:38:21.18#ibcon#read 3, iclass 28, count 0 2006.225.07:38:21.18#ibcon#about to read 4, iclass 28, count 0 2006.225.07:38:21.18#ibcon#read 4, iclass 28, count 0 2006.225.07:38:21.18#ibcon#about to read 5, iclass 28, count 0 2006.225.07:38:21.18#ibcon#read 5, iclass 28, count 0 2006.225.07:38:21.18#ibcon#about to read 6, iclass 28, count 0 2006.225.07:38:21.18#ibcon#read 6, iclass 28, count 0 2006.225.07:38:21.18#ibcon#end of sib2, iclass 28, count 0 2006.225.07:38:21.18#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:38:21.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:38:21.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:38:21.18#ibcon#*before write, iclass 28, count 0 2006.225.07:38:21.18#ibcon#enter sib2, iclass 28, count 0 2006.225.07:38:21.18#ibcon#flushed, iclass 28, count 0 2006.225.07:38:21.18#ibcon#about to write, iclass 28, count 0 2006.225.07:38:21.18#ibcon#wrote, iclass 28, count 0 2006.225.07:38:21.18#ibcon#about to read 3, iclass 28, count 0 2006.225.07:38:21.22#ibcon#read 3, iclass 28, count 0 2006.225.07:38:21.22#ibcon#about to read 4, iclass 28, count 0 2006.225.07:38:21.22#ibcon#read 4, iclass 28, count 0 2006.225.07:38:21.22#ibcon#about to read 5, iclass 28, count 0 2006.225.07:38:21.22#ibcon#read 5, iclass 28, count 0 2006.225.07:38:21.22#ibcon#about to read 6, iclass 28, count 0 2006.225.07:38:21.22#ibcon#read 6, iclass 28, count 0 2006.225.07:38:21.22#ibcon#end of sib2, iclass 28, count 0 2006.225.07:38:21.22#ibcon#*after write, iclass 28, count 0 2006.225.07:38:21.22#ibcon#*before return 0, iclass 28, count 0 2006.225.07:38:21.22#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:38:21.22#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:38:21.22#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:38:21.22#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:38:21.22$vc4f8/vb=3,4 2006.225.07:38:21.22#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.07:38:21.22#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.07:38:21.22#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:21.22#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:38:21.28#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:38:21.28#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:38:21.28#ibcon#enter wrdev, iclass 30, count 2 2006.225.07:38:21.28#ibcon#first serial, iclass 30, count 2 2006.225.07:38:21.28#ibcon#enter sib2, iclass 30, count 2 2006.225.07:38:21.28#ibcon#flushed, iclass 30, count 2 2006.225.07:38:21.28#ibcon#about to write, iclass 30, count 2 2006.225.07:38:21.28#ibcon#wrote, iclass 30, count 2 2006.225.07:38:21.28#ibcon#about to read 3, iclass 30, count 2 2006.225.07:38:21.30#ibcon#read 3, iclass 30, count 2 2006.225.07:38:21.30#ibcon#about to read 4, iclass 30, count 2 2006.225.07:38:21.30#ibcon#read 4, iclass 30, count 2 2006.225.07:38:21.30#ibcon#about to read 5, iclass 30, count 2 2006.225.07:38:21.30#ibcon#read 5, iclass 30, count 2 2006.225.07:38:21.30#ibcon#about to read 6, iclass 30, count 2 2006.225.07:38:21.30#ibcon#read 6, iclass 30, count 2 2006.225.07:38:21.30#ibcon#end of sib2, iclass 30, count 2 2006.225.07:38:21.30#ibcon#*mode == 0, iclass 30, count 2 2006.225.07:38:21.30#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.07:38:21.30#ibcon#[27=AT03-04\r\n] 2006.225.07:38:21.30#ibcon#*before write, iclass 30, count 2 2006.225.07:38:21.30#ibcon#enter sib2, iclass 30, count 2 2006.225.07:38:21.30#ibcon#flushed, iclass 30, count 2 2006.225.07:38:21.30#ibcon#about to write, iclass 30, count 2 2006.225.07:38:21.30#ibcon#wrote, iclass 30, count 2 2006.225.07:38:21.30#ibcon#about to read 3, iclass 30, count 2 2006.225.07:38:21.33#ibcon#read 3, iclass 30, count 2 2006.225.07:38:21.33#ibcon#about to read 4, iclass 30, count 2 2006.225.07:38:21.33#ibcon#read 4, iclass 30, count 2 2006.225.07:38:21.33#ibcon#about to read 5, iclass 30, count 2 2006.225.07:38:21.33#ibcon#read 5, iclass 30, count 2 2006.225.07:38:21.33#ibcon#about to read 6, iclass 30, count 2 2006.225.07:38:21.33#ibcon#read 6, iclass 30, count 2 2006.225.07:38:21.33#ibcon#end of sib2, iclass 30, count 2 2006.225.07:38:21.33#ibcon#*after write, iclass 30, count 2 2006.225.07:38:21.33#ibcon#*before return 0, iclass 30, count 2 2006.225.07:38:21.33#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:38:21.33#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:38:21.33#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.07:38:21.33#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:21.33#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:38:21.45#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:38:21.45#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:38:21.45#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:38:21.45#ibcon#first serial, iclass 30, count 0 2006.225.07:38:21.45#ibcon#enter sib2, iclass 30, count 0 2006.225.07:38:21.45#ibcon#flushed, iclass 30, count 0 2006.225.07:38:21.45#ibcon#about to write, iclass 30, count 0 2006.225.07:38:21.45#ibcon#wrote, iclass 30, count 0 2006.225.07:38:21.45#ibcon#about to read 3, iclass 30, count 0 2006.225.07:38:21.47#ibcon#read 3, iclass 30, count 0 2006.225.07:38:21.47#ibcon#about to read 4, iclass 30, count 0 2006.225.07:38:21.47#ibcon#read 4, iclass 30, count 0 2006.225.07:38:21.47#ibcon#about to read 5, iclass 30, count 0 2006.225.07:38:21.47#ibcon#read 5, iclass 30, count 0 2006.225.07:38:21.47#ibcon#about to read 6, iclass 30, count 0 2006.225.07:38:21.47#ibcon#read 6, iclass 30, count 0 2006.225.07:38:21.47#ibcon#end of sib2, iclass 30, count 0 2006.225.07:38:21.47#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:38:21.47#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:38:21.47#ibcon#[27=USB\r\n] 2006.225.07:38:21.47#ibcon#*before write, iclass 30, count 0 2006.225.07:38:21.47#ibcon#enter sib2, iclass 30, count 0 2006.225.07:38:21.47#ibcon#flushed, iclass 30, count 0 2006.225.07:38:21.47#ibcon#about to write, iclass 30, count 0 2006.225.07:38:21.47#ibcon#wrote, iclass 30, count 0 2006.225.07:38:21.47#ibcon#about to read 3, iclass 30, count 0 2006.225.07:38:21.50#ibcon#read 3, iclass 30, count 0 2006.225.07:38:21.50#ibcon#about to read 4, iclass 30, count 0 2006.225.07:38:21.50#ibcon#read 4, iclass 30, count 0 2006.225.07:38:21.50#ibcon#about to read 5, iclass 30, count 0 2006.225.07:38:21.50#ibcon#read 5, iclass 30, count 0 2006.225.07:38:21.50#ibcon#about to read 6, iclass 30, count 0 2006.225.07:38:21.50#ibcon#read 6, iclass 30, count 0 2006.225.07:38:21.50#ibcon#end of sib2, iclass 30, count 0 2006.225.07:38:21.50#ibcon#*after write, iclass 30, count 0 2006.225.07:38:21.50#ibcon#*before return 0, iclass 30, count 0 2006.225.07:38:21.50#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:38:21.50#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:38:21.50#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:38:21.50#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:38:21.50$vc4f8/vblo=4,712.99 2006.225.07:38:21.50#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.07:38:21.50#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.07:38:21.50#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:21.50#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:38:21.50#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:38:21.50#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:38:21.50#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:38:21.50#ibcon#first serial, iclass 32, count 0 2006.225.07:38:21.50#ibcon#enter sib2, iclass 32, count 0 2006.225.07:38:21.50#ibcon#flushed, iclass 32, count 0 2006.225.07:38:21.50#ibcon#about to write, iclass 32, count 0 2006.225.07:38:21.50#ibcon#wrote, iclass 32, count 0 2006.225.07:38:21.50#ibcon#about to read 3, iclass 32, count 0 2006.225.07:38:21.52#ibcon#read 3, iclass 32, count 0 2006.225.07:38:21.52#ibcon#about to read 4, iclass 32, count 0 2006.225.07:38:21.52#ibcon#read 4, iclass 32, count 0 2006.225.07:38:21.52#ibcon#about to read 5, iclass 32, count 0 2006.225.07:38:21.52#ibcon#read 5, iclass 32, count 0 2006.225.07:38:21.52#ibcon#about to read 6, iclass 32, count 0 2006.225.07:38:21.52#ibcon#read 6, iclass 32, count 0 2006.225.07:38:21.52#ibcon#end of sib2, iclass 32, count 0 2006.225.07:38:21.52#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:38:21.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:38:21.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:38:21.52#ibcon#*before write, iclass 32, count 0 2006.225.07:38:21.52#ibcon#enter sib2, iclass 32, count 0 2006.225.07:38:21.52#ibcon#flushed, iclass 32, count 0 2006.225.07:38:21.52#ibcon#about to write, iclass 32, count 0 2006.225.07:38:21.52#ibcon#wrote, iclass 32, count 0 2006.225.07:38:21.52#ibcon#about to read 3, iclass 32, count 0 2006.225.07:38:21.56#ibcon#read 3, iclass 32, count 0 2006.225.07:38:21.56#ibcon#about to read 4, iclass 32, count 0 2006.225.07:38:21.56#ibcon#read 4, iclass 32, count 0 2006.225.07:38:21.56#ibcon#about to read 5, iclass 32, count 0 2006.225.07:38:21.56#ibcon#read 5, iclass 32, count 0 2006.225.07:38:21.56#ibcon#about to read 6, iclass 32, count 0 2006.225.07:38:21.56#ibcon#read 6, iclass 32, count 0 2006.225.07:38:21.56#ibcon#end of sib2, iclass 32, count 0 2006.225.07:38:21.56#ibcon#*after write, iclass 32, count 0 2006.225.07:38:21.56#ibcon#*before return 0, iclass 32, count 0 2006.225.07:38:21.56#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:38:21.56#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:38:21.56#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:38:21.56#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:38:21.56$vc4f8/vb=4,4 2006.225.07:38:21.56#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.07:38:21.56#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.07:38:21.56#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:21.56#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:38:21.62#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:38:21.62#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:38:21.62#ibcon#enter wrdev, iclass 34, count 2 2006.225.07:38:21.62#ibcon#first serial, iclass 34, count 2 2006.225.07:38:21.62#ibcon#enter sib2, iclass 34, count 2 2006.225.07:38:21.62#ibcon#flushed, iclass 34, count 2 2006.225.07:38:21.62#ibcon#about to write, iclass 34, count 2 2006.225.07:38:21.62#ibcon#wrote, iclass 34, count 2 2006.225.07:38:21.62#ibcon#about to read 3, iclass 34, count 2 2006.225.07:38:21.64#ibcon#read 3, iclass 34, count 2 2006.225.07:38:21.64#ibcon#about to read 4, iclass 34, count 2 2006.225.07:38:21.64#ibcon#read 4, iclass 34, count 2 2006.225.07:38:21.64#ibcon#about to read 5, iclass 34, count 2 2006.225.07:38:21.64#ibcon#read 5, iclass 34, count 2 2006.225.07:38:21.64#ibcon#about to read 6, iclass 34, count 2 2006.225.07:38:21.64#ibcon#read 6, iclass 34, count 2 2006.225.07:38:21.64#ibcon#end of sib2, iclass 34, count 2 2006.225.07:38:21.64#ibcon#*mode == 0, iclass 34, count 2 2006.225.07:38:21.64#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.07:38:21.64#ibcon#[27=AT04-04\r\n] 2006.225.07:38:21.64#ibcon#*before write, iclass 34, count 2 2006.225.07:38:21.64#ibcon#enter sib2, iclass 34, count 2 2006.225.07:38:21.64#ibcon#flushed, iclass 34, count 2 2006.225.07:38:21.64#ibcon#about to write, iclass 34, count 2 2006.225.07:38:21.64#ibcon#wrote, iclass 34, count 2 2006.225.07:38:21.64#ibcon#about to read 3, iclass 34, count 2 2006.225.07:38:21.67#ibcon#read 3, iclass 34, count 2 2006.225.07:38:21.67#ibcon#about to read 4, iclass 34, count 2 2006.225.07:38:21.67#ibcon#read 4, iclass 34, count 2 2006.225.07:38:21.67#ibcon#about to read 5, iclass 34, count 2 2006.225.07:38:21.67#ibcon#read 5, iclass 34, count 2 2006.225.07:38:21.67#ibcon#about to read 6, iclass 34, count 2 2006.225.07:38:21.67#ibcon#read 6, iclass 34, count 2 2006.225.07:38:21.67#ibcon#end of sib2, iclass 34, count 2 2006.225.07:38:21.67#ibcon#*after write, iclass 34, count 2 2006.225.07:38:21.67#ibcon#*before return 0, iclass 34, count 2 2006.225.07:38:21.67#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:38:21.67#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:38:21.67#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.07:38:21.67#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:21.67#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:38:21.79#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:38:21.79#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:38:21.79#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:38:21.79#ibcon#first serial, iclass 34, count 0 2006.225.07:38:21.79#ibcon#enter sib2, iclass 34, count 0 2006.225.07:38:21.79#ibcon#flushed, iclass 34, count 0 2006.225.07:38:21.79#ibcon#about to write, iclass 34, count 0 2006.225.07:38:21.79#ibcon#wrote, iclass 34, count 0 2006.225.07:38:21.79#ibcon#about to read 3, iclass 34, count 0 2006.225.07:38:21.81#ibcon#read 3, iclass 34, count 0 2006.225.07:38:21.81#ibcon#about to read 4, iclass 34, count 0 2006.225.07:38:21.81#ibcon#read 4, iclass 34, count 0 2006.225.07:38:21.81#ibcon#about to read 5, iclass 34, count 0 2006.225.07:38:21.81#ibcon#read 5, iclass 34, count 0 2006.225.07:38:21.81#ibcon#about to read 6, iclass 34, count 0 2006.225.07:38:21.81#ibcon#read 6, iclass 34, count 0 2006.225.07:38:21.81#ibcon#end of sib2, iclass 34, count 0 2006.225.07:38:21.81#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:38:21.81#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:38:21.81#ibcon#[27=USB\r\n] 2006.225.07:38:21.81#ibcon#*before write, iclass 34, count 0 2006.225.07:38:21.81#ibcon#enter sib2, iclass 34, count 0 2006.225.07:38:21.81#ibcon#flushed, iclass 34, count 0 2006.225.07:38:21.81#ibcon#about to write, iclass 34, count 0 2006.225.07:38:21.81#ibcon#wrote, iclass 34, count 0 2006.225.07:38:21.81#ibcon#about to read 3, iclass 34, count 0 2006.225.07:38:21.84#ibcon#read 3, iclass 34, count 0 2006.225.07:38:21.84#ibcon#about to read 4, iclass 34, count 0 2006.225.07:38:21.84#ibcon#read 4, iclass 34, count 0 2006.225.07:38:21.84#ibcon#about to read 5, iclass 34, count 0 2006.225.07:38:21.84#ibcon#read 5, iclass 34, count 0 2006.225.07:38:21.84#ibcon#about to read 6, iclass 34, count 0 2006.225.07:38:21.84#ibcon#read 6, iclass 34, count 0 2006.225.07:38:21.84#ibcon#end of sib2, iclass 34, count 0 2006.225.07:38:21.84#ibcon#*after write, iclass 34, count 0 2006.225.07:38:21.84#ibcon#*before return 0, iclass 34, count 0 2006.225.07:38:21.84#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:38:21.84#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:38:21.84#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:38:21.84#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:38:21.84$vc4f8/vblo=5,744.99 2006.225.07:38:21.84#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.07:38:21.84#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.07:38:21.84#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:21.84#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:38:21.84#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:38:21.84#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:38:21.84#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:38:21.84#ibcon#first serial, iclass 36, count 0 2006.225.07:38:21.84#ibcon#enter sib2, iclass 36, count 0 2006.225.07:38:21.84#ibcon#flushed, iclass 36, count 0 2006.225.07:38:21.84#ibcon#about to write, iclass 36, count 0 2006.225.07:38:21.84#ibcon#wrote, iclass 36, count 0 2006.225.07:38:21.84#ibcon#about to read 3, iclass 36, count 0 2006.225.07:38:21.86#ibcon#read 3, iclass 36, count 0 2006.225.07:38:21.86#ibcon#about to read 4, iclass 36, count 0 2006.225.07:38:21.86#ibcon#read 4, iclass 36, count 0 2006.225.07:38:21.86#ibcon#about to read 5, iclass 36, count 0 2006.225.07:38:21.86#ibcon#read 5, iclass 36, count 0 2006.225.07:38:21.86#ibcon#about to read 6, iclass 36, count 0 2006.225.07:38:21.86#ibcon#read 6, iclass 36, count 0 2006.225.07:38:21.86#ibcon#end of sib2, iclass 36, count 0 2006.225.07:38:21.86#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:38:21.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:38:21.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:38:21.86#ibcon#*before write, iclass 36, count 0 2006.225.07:38:21.86#ibcon#enter sib2, iclass 36, count 0 2006.225.07:38:21.86#ibcon#flushed, iclass 36, count 0 2006.225.07:38:21.86#ibcon#about to write, iclass 36, count 0 2006.225.07:38:21.86#ibcon#wrote, iclass 36, count 0 2006.225.07:38:21.86#ibcon#about to read 3, iclass 36, count 0 2006.225.07:38:21.90#ibcon#read 3, iclass 36, count 0 2006.225.07:38:21.90#ibcon#about to read 4, iclass 36, count 0 2006.225.07:38:21.90#ibcon#read 4, iclass 36, count 0 2006.225.07:38:21.90#ibcon#about to read 5, iclass 36, count 0 2006.225.07:38:21.90#ibcon#read 5, iclass 36, count 0 2006.225.07:38:21.90#ibcon#about to read 6, iclass 36, count 0 2006.225.07:38:21.90#ibcon#read 6, iclass 36, count 0 2006.225.07:38:21.90#ibcon#end of sib2, iclass 36, count 0 2006.225.07:38:21.90#ibcon#*after write, iclass 36, count 0 2006.225.07:38:21.90#ibcon#*before return 0, iclass 36, count 0 2006.225.07:38:21.90#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:38:21.90#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:38:21.90#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:38:21.90#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:38:21.90$vc4f8/vb=5,4 2006.225.07:38:21.90#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.07:38:21.90#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.07:38:21.90#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:21.90#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:38:21.96#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:38:21.96#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:38:21.96#ibcon#enter wrdev, iclass 38, count 2 2006.225.07:38:21.96#ibcon#first serial, iclass 38, count 2 2006.225.07:38:21.96#ibcon#enter sib2, iclass 38, count 2 2006.225.07:38:21.96#ibcon#flushed, iclass 38, count 2 2006.225.07:38:21.96#ibcon#about to write, iclass 38, count 2 2006.225.07:38:21.96#ibcon#wrote, iclass 38, count 2 2006.225.07:38:21.96#ibcon#about to read 3, iclass 38, count 2 2006.225.07:38:21.98#ibcon#read 3, iclass 38, count 2 2006.225.07:38:21.98#ibcon#about to read 4, iclass 38, count 2 2006.225.07:38:21.98#ibcon#read 4, iclass 38, count 2 2006.225.07:38:21.98#ibcon#about to read 5, iclass 38, count 2 2006.225.07:38:21.98#ibcon#read 5, iclass 38, count 2 2006.225.07:38:21.98#ibcon#about to read 6, iclass 38, count 2 2006.225.07:38:21.98#ibcon#read 6, iclass 38, count 2 2006.225.07:38:21.98#ibcon#end of sib2, iclass 38, count 2 2006.225.07:38:21.98#ibcon#*mode == 0, iclass 38, count 2 2006.225.07:38:21.98#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.07:38:21.98#ibcon#[27=AT05-04\r\n] 2006.225.07:38:21.98#ibcon#*before write, iclass 38, count 2 2006.225.07:38:21.98#ibcon#enter sib2, iclass 38, count 2 2006.225.07:38:21.98#ibcon#flushed, iclass 38, count 2 2006.225.07:38:21.98#ibcon#about to write, iclass 38, count 2 2006.225.07:38:21.98#ibcon#wrote, iclass 38, count 2 2006.225.07:38:21.98#ibcon#about to read 3, iclass 38, count 2 2006.225.07:38:22.01#ibcon#read 3, iclass 38, count 2 2006.225.07:38:22.01#ibcon#about to read 4, iclass 38, count 2 2006.225.07:38:22.01#ibcon#read 4, iclass 38, count 2 2006.225.07:38:22.01#ibcon#about to read 5, iclass 38, count 2 2006.225.07:38:22.01#ibcon#read 5, iclass 38, count 2 2006.225.07:38:22.01#ibcon#about to read 6, iclass 38, count 2 2006.225.07:38:22.01#ibcon#read 6, iclass 38, count 2 2006.225.07:38:22.01#ibcon#end of sib2, iclass 38, count 2 2006.225.07:38:22.01#ibcon#*after write, iclass 38, count 2 2006.225.07:38:22.01#ibcon#*before return 0, iclass 38, count 2 2006.225.07:38:22.01#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:38:22.01#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:38:22.01#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.07:38:22.01#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:22.01#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:38:22.13#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:38:22.13#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:38:22.13#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:38:22.13#ibcon#first serial, iclass 38, count 0 2006.225.07:38:22.13#ibcon#enter sib2, iclass 38, count 0 2006.225.07:38:22.13#ibcon#flushed, iclass 38, count 0 2006.225.07:38:22.13#ibcon#about to write, iclass 38, count 0 2006.225.07:38:22.13#ibcon#wrote, iclass 38, count 0 2006.225.07:38:22.13#ibcon#about to read 3, iclass 38, count 0 2006.225.07:38:22.15#ibcon#read 3, iclass 38, count 0 2006.225.07:38:22.15#ibcon#about to read 4, iclass 38, count 0 2006.225.07:38:22.15#ibcon#read 4, iclass 38, count 0 2006.225.07:38:22.15#ibcon#about to read 5, iclass 38, count 0 2006.225.07:38:22.15#ibcon#read 5, iclass 38, count 0 2006.225.07:38:22.15#ibcon#about to read 6, iclass 38, count 0 2006.225.07:38:22.15#ibcon#read 6, iclass 38, count 0 2006.225.07:38:22.15#ibcon#end of sib2, iclass 38, count 0 2006.225.07:38:22.15#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:38:22.15#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:38:22.15#ibcon#[27=USB\r\n] 2006.225.07:38:22.15#ibcon#*before write, iclass 38, count 0 2006.225.07:38:22.15#ibcon#enter sib2, iclass 38, count 0 2006.225.07:38:22.15#ibcon#flushed, iclass 38, count 0 2006.225.07:38:22.15#ibcon#about to write, iclass 38, count 0 2006.225.07:38:22.15#ibcon#wrote, iclass 38, count 0 2006.225.07:38:22.15#ibcon#about to read 3, iclass 38, count 0 2006.225.07:38:22.18#ibcon#read 3, iclass 38, count 0 2006.225.07:38:22.18#ibcon#about to read 4, iclass 38, count 0 2006.225.07:38:22.18#ibcon#read 4, iclass 38, count 0 2006.225.07:38:22.18#ibcon#about to read 5, iclass 38, count 0 2006.225.07:38:22.18#ibcon#read 5, iclass 38, count 0 2006.225.07:38:22.18#ibcon#about to read 6, iclass 38, count 0 2006.225.07:38:22.18#ibcon#read 6, iclass 38, count 0 2006.225.07:38:22.18#ibcon#end of sib2, iclass 38, count 0 2006.225.07:38:22.18#ibcon#*after write, iclass 38, count 0 2006.225.07:38:22.18#ibcon#*before return 0, iclass 38, count 0 2006.225.07:38:22.18#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:38:22.18#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:38:22.18#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:38:22.18#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:38:22.18$vc4f8/vblo=6,752.99 2006.225.07:38:22.18#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.07:38:22.18#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.07:38:22.18#ibcon#ireg 17 cls_cnt 0 2006.225.07:38:22.18#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:38:22.18#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:38:22.18#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:38:22.18#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:38:22.18#ibcon#first serial, iclass 40, count 0 2006.225.07:38:22.18#ibcon#enter sib2, iclass 40, count 0 2006.225.07:38:22.18#ibcon#flushed, iclass 40, count 0 2006.225.07:38:22.18#ibcon#about to write, iclass 40, count 0 2006.225.07:38:22.18#ibcon#wrote, iclass 40, count 0 2006.225.07:38:22.18#ibcon#about to read 3, iclass 40, count 0 2006.225.07:38:22.20#ibcon#read 3, iclass 40, count 0 2006.225.07:38:22.20#ibcon#about to read 4, iclass 40, count 0 2006.225.07:38:22.20#ibcon#read 4, iclass 40, count 0 2006.225.07:38:22.20#ibcon#about to read 5, iclass 40, count 0 2006.225.07:38:22.20#ibcon#read 5, iclass 40, count 0 2006.225.07:38:22.20#ibcon#about to read 6, iclass 40, count 0 2006.225.07:38:22.20#ibcon#read 6, iclass 40, count 0 2006.225.07:38:22.20#ibcon#end of sib2, iclass 40, count 0 2006.225.07:38:22.20#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:38:22.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:38:22.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:38:22.20#ibcon#*before write, iclass 40, count 0 2006.225.07:38:22.20#ibcon#enter sib2, iclass 40, count 0 2006.225.07:38:22.20#ibcon#flushed, iclass 40, count 0 2006.225.07:38:22.20#ibcon#about to write, iclass 40, count 0 2006.225.07:38:22.20#ibcon#wrote, iclass 40, count 0 2006.225.07:38:22.20#ibcon#about to read 3, iclass 40, count 0 2006.225.07:38:22.24#ibcon#read 3, iclass 40, count 0 2006.225.07:38:22.24#ibcon#about to read 4, iclass 40, count 0 2006.225.07:38:22.24#ibcon#read 4, iclass 40, count 0 2006.225.07:38:22.24#ibcon#about to read 5, iclass 40, count 0 2006.225.07:38:22.24#ibcon#read 5, iclass 40, count 0 2006.225.07:38:22.24#ibcon#about to read 6, iclass 40, count 0 2006.225.07:38:22.24#ibcon#read 6, iclass 40, count 0 2006.225.07:38:22.24#ibcon#end of sib2, iclass 40, count 0 2006.225.07:38:22.24#ibcon#*after write, iclass 40, count 0 2006.225.07:38:22.24#ibcon#*before return 0, iclass 40, count 0 2006.225.07:38:22.24#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:38:22.24#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:38:22.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:38:22.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:38:22.24$vc4f8/vb=6,4 2006.225.07:38:22.24#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.07:38:22.24#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.07:38:22.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:38:22.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:38:22.30#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:38:22.30#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:38:22.30#ibcon#enter wrdev, iclass 4, count 2 2006.225.07:38:22.30#ibcon#first serial, iclass 4, count 2 2006.225.07:38:22.30#ibcon#enter sib2, iclass 4, count 2 2006.225.07:38:22.30#ibcon#flushed, iclass 4, count 2 2006.225.07:38:22.30#ibcon#about to write, iclass 4, count 2 2006.225.07:38:22.30#ibcon#wrote, iclass 4, count 2 2006.225.07:38:22.30#ibcon#about to read 3, iclass 4, count 2 2006.225.07:38:22.32#ibcon#read 3, iclass 4, count 2 2006.225.07:38:22.32#ibcon#about to read 4, iclass 4, count 2 2006.225.07:38:22.32#ibcon#read 4, iclass 4, count 2 2006.225.07:38:22.32#ibcon#about to read 5, iclass 4, count 2 2006.225.07:38:22.32#ibcon#read 5, iclass 4, count 2 2006.225.07:38:22.32#ibcon#about to read 6, iclass 4, count 2 2006.225.07:38:22.32#ibcon#read 6, iclass 4, count 2 2006.225.07:38:22.32#ibcon#end of sib2, iclass 4, count 2 2006.225.07:38:22.32#ibcon#*mode == 0, iclass 4, count 2 2006.225.07:38:22.32#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.07:38:22.32#ibcon#[27=AT06-04\r\n] 2006.225.07:38:22.32#ibcon#*before write, iclass 4, count 2 2006.225.07:38:22.32#ibcon#enter sib2, iclass 4, count 2 2006.225.07:38:22.32#ibcon#flushed, iclass 4, count 2 2006.225.07:38:22.32#ibcon#about to write, iclass 4, count 2 2006.225.07:38:22.32#ibcon#wrote, iclass 4, count 2 2006.225.07:38:22.32#ibcon#about to read 3, iclass 4, count 2 2006.225.07:38:22.35#ibcon#read 3, iclass 4, count 2 2006.225.07:38:22.35#ibcon#about to read 4, iclass 4, count 2 2006.225.07:38:22.35#ibcon#read 4, iclass 4, count 2 2006.225.07:38:22.35#ibcon#about to read 5, iclass 4, count 2 2006.225.07:38:22.35#ibcon#read 5, iclass 4, count 2 2006.225.07:38:22.35#ibcon#about to read 6, iclass 4, count 2 2006.225.07:38:22.35#ibcon#read 6, iclass 4, count 2 2006.225.07:38:22.35#ibcon#end of sib2, iclass 4, count 2 2006.225.07:38:22.35#ibcon#*after write, iclass 4, count 2 2006.225.07:38:22.35#ibcon#*before return 0, iclass 4, count 2 2006.225.07:38:22.35#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:38:22.35#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:38:22.35#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.07:38:22.35#ibcon#ireg 7 cls_cnt 0 2006.225.07:38:22.35#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:38:22.47#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:38:22.47#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:38:22.47#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:38:22.47#ibcon#first serial, iclass 4, count 0 2006.225.07:38:22.47#ibcon#enter sib2, iclass 4, count 0 2006.225.07:38:22.47#ibcon#flushed, iclass 4, count 0 2006.225.07:38:22.47#ibcon#about to write, iclass 4, count 0 2006.225.07:38:22.47#ibcon#wrote, iclass 4, count 0 2006.225.07:38:22.47#ibcon#about to read 3, iclass 4, count 0 2006.225.07:38:22.49#ibcon#read 3, iclass 4, count 0 2006.225.07:38:22.49#ibcon#about to read 4, iclass 4, count 0 2006.225.07:38:22.49#ibcon#read 4, iclass 4, count 0 2006.225.07:38:22.49#ibcon#about to read 5, iclass 4, count 0 2006.225.07:38:22.49#ibcon#read 5, iclass 4, count 0 2006.225.07:38:22.49#ibcon#about to read 6, iclass 4, count 0 2006.225.07:38:22.49#ibcon#read 6, iclass 4, count 0 2006.225.07:38:22.49#ibcon#end of sib2, iclass 4, count 0 2006.225.07:38:22.49#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:38:22.49#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:38:22.49#ibcon#[27=USB\r\n] 2006.225.07:38:22.49#ibcon#*before write, iclass 4, count 0 2006.225.07:38:22.49#ibcon#enter sib2, iclass 4, count 0 2006.225.07:38:22.49#ibcon#flushed, iclass 4, count 0 2006.225.07:38:22.49#ibcon#about to write, iclass 4, count 0 2006.225.07:38:22.49#ibcon#wrote, iclass 4, count 0 2006.225.07:38:22.49#ibcon#about to read 3, iclass 4, count 0 2006.225.07:38:22.52#ibcon#read 3, iclass 4, count 0 2006.225.07:38:22.52#ibcon#about to read 4, iclass 4, count 0 2006.225.07:38:22.52#ibcon#read 4, iclass 4, count 0 2006.225.07:38:22.52#ibcon#about to read 5, iclass 4, count 0 2006.225.07:38:22.52#ibcon#read 5, iclass 4, count 0 2006.225.07:38:22.52#ibcon#about to read 6, iclass 4, count 0 2006.225.07:38:22.52#ibcon#read 6, iclass 4, count 0 2006.225.07:38:22.52#ibcon#end of sib2, iclass 4, count 0 2006.225.07:38:22.52#ibcon#*after write, iclass 4, count 0 2006.225.07:38:22.52#ibcon#*before return 0, iclass 4, count 0 2006.225.07:38:22.52#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:38:22.52#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:38:22.52#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:38:22.52#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:38:22.52$vc4f8/vabw=wide 2006.225.07:38:22.52#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.07:38:22.52#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.07:38:22.52#ibcon#ireg 8 cls_cnt 0 2006.225.07:38:22.52#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:38:22.52#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:38:22.52#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:38:22.52#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:38:22.52#ibcon#first serial, iclass 6, count 0 2006.225.07:38:22.52#ibcon#enter sib2, iclass 6, count 0 2006.225.07:38:22.52#ibcon#flushed, iclass 6, count 0 2006.225.07:38:22.52#ibcon#about to write, iclass 6, count 0 2006.225.07:38:22.52#ibcon#wrote, iclass 6, count 0 2006.225.07:38:22.52#ibcon#about to read 3, iclass 6, count 0 2006.225.07:38:22.54#ibcon#read 3, iclass 6, count 0 2006.225.07:38:22.54#ibcon#about to read 4, iclass 6, count 0 2006.225.07:38:22.54#ibcon#read 4, iclass 6, count 0 2006.225.07:38:22.54#ibcon#about to read 5, iclass 6, count 0 2006.225.07:38:22.54#ibcon#read 5, iclass 6, count 0 2006.225.07:38:22.54#ibcon#about to read 6, iclass 6, count 0 2006.225.07:38:22.54#ibcon#read 6, iclass 6, count 0 2006.225.07:38:22.54#ibcon#end of sib2, iclass 6, count 0 2006.225.07:38:22.54#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:38:22.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:38:22.54#ibcon#[25=BW32\r\n] 2006.225.07:38:22.54#ibcon#*before write, iclass 6, count 0 2006.225.07:38:22.54#ibcon#enter sib2, iclass 6, count 0 2006.225.07:38:22.54#ibcon#flushed, iclass 6, count 0 2006.225.07:38:22.54#ibcon#about to write, iclass 6, count 0 2006.225.07:38:22.54#ibcon#wrote, iclass 6, count 0 2006.225.07:38:22.54#ibcon#about to read 3, iclass 6, count 0 2006.225.07:38:22.57#ibcon#read 3, iclass 6, count 0 2006.225.07:38:22.57#ibcon#about to read 4, iclass 6, count 0 2006.225.07:38:22.57#ibcon#read 4, iclass 6, count 0 2006.225.07:38:22.57#ibcon#about to read 5, iclass 6, count 0 2006.225.07:38:22.57#ibcon#read 5, iclass 6, count 0 2006.225.07:38:22.57#ibcon#about to read 6, iclass 6, count 0 2006.225.07:38:22.57#ibcon#read 6, iclass 6, count 0 2006.225.07:38:22.57#ibcon#end of sib2, iclass 6, count 0 2006.225.07:38:22.57#ibcon#*after write, iclass 6, count 0 2006.225.07:38:22.57#ibcon#*before return 0, iclass 6, count 0 2006.225.07:38:22.57#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:38:22.57#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:38:22.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:38:22.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:38:22.57$vc4f8/vbbw=wide 2006.225.07:38:22.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.07:38:22.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.07:38:22.57#ibcon#ireg 8 cls_cnt 0 2006.225.07:38:22.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:38:22.64#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:38:22.64#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:38:22.64#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:38:22.64#ibcon#first serial, iclass 10, count 0 2006.225.07:38:22.64#ibcon#enter sib2, iclass 10, count 0 2006.225.07:38:22.64#ibcon#flushed, iclass 10, count 0 2006.225.07:38:22.64#ibcon#about to write, iclass 10, count 0 2006.225.07:38:22.64#ibcon#wrote, iclass 10, count 0 2006.225.07:38:22.64#ibcon#about to read 3, iclass 10, count 0 2006.225.07:38:22.66#ibcon#read 3, iclass 10, count 0 2006.225.07:38:22.66#ibcon#about to read 4, iclass 10, count 0 2006.225.07:38:22.66#ibcon#read 4, iclass 10, count 0 2006.225.07:38:22.66#ibcon#about to read 5, iclass 10, count 0 2006.225.07:38:22.66#ibcon#read 5, iclass 10, count 0 2006.225.07:38:22.66#ibcon#about to read 6, iclass 10, count 0 2006.225.07:38:22.66#ibcon#read 6, iclass 10, count 0 2006.225.07:38:22.66#ibcon#end of sib2, iclass 10, count 0 2006.225.07:38:22.66#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:38:22.66#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:38:22.66#ibcon#[27=BW32\r\n] 2006.225.07:38:22.66#ibcon#*before write, iclass 10, count 0 2006.225.07:38:22.66#ibcon#enter sib2, iclass 10, count 0 2006.225.07:38:22.66#ibcon#flushed, iclass 10, count 0 2006.225.07:38:22.66#ibcon#about to write, iclass 10, count 0 2006.225.07:38:22.66#ibcon#wrote, iclass 10, count 0 2006.225.07:38:22.66#ibcon#about to read 3, iclass 10, count 0 2006.225.07:38:22.69#ibcon#read 3, iclass 10, count 0 2006.225.07:38:22.69#ibcon#about to read 4, iclass 10, count 0 2006.225.07:38:22.69#ibcon#read 4, iclass 10, count 0 2006.225.07:38:22.69#ibcon#about to read 5, iclass 10, count 0 2006.225.07:38:22.69#ibcon#read 5, iclass 10, count 0 2006.225.07:38:22.69#ibcon#about to read 6, iclass 10, count 0 2006.225.07:38:22.69#ibcon#read 6, iclass 10, count 0 2006.225.07:38:22.69#ibcon#end of sib2, iclass 10, count 0 2006.225.07:38:22.69#ibcon#*after write, iclass 10, count 0 2006.225.07:38:22.69#ibcon#*before return 0, iclass 10, count 0 2006.225.07:38:22.69#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:38:22.69#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:38:22.69#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:38:22.69#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:38:22.69$4f8m12a/ifd4f 2006.225.07:38:22.69$ifd4f/lo= 2006.225.07:38:22.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:38:22.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:38:22.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:38:22.69$ifd4f/patch= 2006.225.07:38:22.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:38:22.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:38:22.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:38:22.69$4f8m12a/"form=m,16.000,1:2 2006.225.07:38:22.69$4f8m12a/"tpicd 2006.225.07:38:22.69$4f8m12a/echo=off 2006.225.07:38:22.69$4f8m12a/xlog=off 2006.225.07:38:22.69:!2006.225.07:39:10 2006.225.07:38:49.14#trakl#Source acquired 2006.225.07:38:50.14#flagr#flagr/antenna,acquired 2006.225.07:39:10.00:preob 2006.225.07:39:10.14/onsource/TRACKING 2006.225.07:39:10.14:!2006.225.07:39:20 2006.225.07:39:20.00:data_valid=on 2006.225.07:39:20.00:midob 2006.225.07:39:20.14/onsource/TRACKING 2006.225.07:39:20.14/wx/27.92,1003.2,68 2006.225.07:39:20.29/cable/+6.4058E-03 2006.225.07:39:21.38/va/01,08,usb,yes,29,30 2006.225.07:39:21.38/va/02,07,usb,yes,29,30 2006.225.07:39:21.38/va/03,06,usb,yes,30,31 2006.225.07:39:21.38/va/04,07,usb,yes,30,32 2006.225.07:39:21.38/va/05,07,usb,yes,32,34 2006.225.07:39:21.38/va/06,06,usb,yes,31,31 2006.225.07:39:21.38/va/07,06,usb,yes,32,31 2006.225.07:39:21.38/va/08,07,usb,yes,30,29 2006.225.07:39:21.61/valo/01,532.99,yes,locked 2006.225.07:39:21.61/valo/02,572.99,yes,locked 2006.225.07:39:21.61/valo/03,672.99,yes,locked 2006.225.07:39:21.61/valo/04,832.99,yes,locked 2006.225.07:39:21.61/valo/05,652.99,yes,locked 2006.225.07:39:21.61/valo/06,772.99,yes,locked 2006.225.07:39:21.61/valo/07,832.99,yes,locked 2006.225.07:39:21.61/valo/08,852.99,yes,locked 2006.225.07:39:22.70/vb/01,04,usb,yes,31,29 2006.225.07:39:22.70/vb/02,04,usb,yes,32,34 2006.225.07:39:22.70/vb/03,04,usb,yes,29,32 2006.225.07:39:22.70/vb/04,04,usb,yes,29,30 2006.225.07:39:22.70/vb/05,04,usb,yes,28,32 2006.225.07:39:22.70/vb/06,04,usb,yes,29,32 2006.225.07:39:22.70/vb/07,04,usb,yes,31,31 2006.225.07:39:22.70/vb/08,04,usb,yes,29,32 2006.225.07:39:22.93/vblo/01,632.99,yes,locked 2006.225.07:39:22.93/vblo/02,640.99,yes,locked 2006.225.07:39:22.93/vblo/03,656.99,yes,locked 2006.225.07:39:22.93/vblo/04,712.99,yes,locked 2006.225.07:39:22.93/vblo/05,744.99,yes,locked 2006.225.07:39:22.93/vblo/06,752.99,yes,locked 2006.225.07:39:22.93/vblo/07,734.99,yes,locked 2006.225.07:39:22.93/vblo/08,744.99,yes,locked 2006.225.07:39:23.08/vabw/8 2006.225.07:39:23.23/vbbw/8 2006.225.07:39:23.37/xfe/off,on,15.2 2006.225.07:39:23.75/ifatt/23,28,28,28 2006.225.07:39:24.08/fmout-gps/S +4.46E-07 2006.225.07:39:24.12:!2006.225.07:40:30 2006.225.07:40:30.00:data_valid=off 2006.225.07:40:30.00:postob 2006.225.07:40:30.14/cable/+6.4044E-03 2006.225.07:40:30.14/wx/27.93,1003.2,68 2006.225.07:40:31.07/fmout-gps/S +4.46E-07 2006.225.07:40:31.07:scan_name=225-0741,k06225,60 2006.225.07:40:31.07:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.225.07:40:32.14#flagr#flagr/antenna,new-source 2006.225.07:40:32.14:checkk5 2006.225.07:40:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:40:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:40:33.25/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:40:33.62/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:40:33.98/chk_obsdata//k5ts1/T2250739??a.dat file size is correct (nominal:560MB, actual:560MB). 2006.225.07:40:34.34/chk_obsdata//k5ts2/T2250739??b.dat file size is correct (nominal:560MB, actual:560MB). 2006.225.07:40:34.71/chk_obsdata//k5ts3/T2250739??c.dat file size is correct (nominal:560MB, actual:560MB). 2006.225.07:40:35.07/chk_obsdata//k5ts4/T2250739??d.dat file size is correct (nominal:560MB, actual:560MB). 2006.225.07:40:35.76/k5log//k5ts1_log_newline 2006.225.07:40:36.44/k5log//k5ts2_log_newline 2006.225.07:40:37.12/k5log//k5ts3_log_newline 2006.225.07:40:37.81/k5log//k5ts4_log_newline 2006.225.07:40:37.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:40:37.84:4f8m12a=1 2006.225.07:40:37.84$4f8m12a/echo=on 2006.225.07:40:37.84$4f8m12a/pcalon 2006.225.07:40:37.84$pcalon/"no phase cal control is implemented here 2006.225.07:40:37.84$4f8m12a/"tpicd=stop 2006.225.07:40:37.84$4f8m12a/vc4f8 2006.225.07:40:37.84$vc4f8/valo=1,532.99 2006.225.07:40:37.84#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.07:40:37.84#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.07:40:37.84#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:37.84#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:40:37.84#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:40:37.84#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:40:37.84#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:40:37.84#ibcon#first serial, iclass 29, count 0 2006.225.07:40:37.84#ibcon#enter sib2, iclass 29, count 0 2006.225.07:40:37.84#ibcon#flushed, iclass 29, count 0 2006.225.07:40:37.84#ibcon#about to write, iclass 29, count 0 2006.225.07:40:37.84#ibcon#wrote, iclass 29, count 0 2006.225.07:40:37.84#ibcon#about to read 3, iclass 29, count 0 2006.225.07:40:37.88#ibcon#read 3, iclass 29, count 0 2006.225.07:40:37.88#ibcon#about to read 4, iclass 29, count 0 2006.225.07:40:37.88#ibcon#read 4, iclass 29, count 0 2006.225.07:40:37.88#ibcon#about to read 5, iclass 29, count 0 2006.225.07:40:37.88#ibcon#read 5, iclass 29, count 0 2006.225.07:40:37.88#ibcon#about to read 6, iclass 29, count 0 2006.225.07:40:37.88#ibcon#read 6, iclass 29, count 0 2006.225.07:40:37.88#ibcon#end of sib2, iclass 29, count 0 2006.225.07:40:37.88#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:40:37.88#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:40:37.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:40:37.88#ibcon#*before write, iclass 29, count 0 2006.225.07:40:37.88#ibcon#enter sib2, iclass 29, count 0 2006.225.07:40:37.88#ibcon#flushed, iclass 29, count 0 2006.225.07:40:37.88#ibcon#about to write, iclass 29, count 0 2006.225.07:40:37.88#ibcon#wrote, iclass 29, count 0 2006.225.07:40:37.88#ibcon#about to read 3, iclass 29, count 0 2006.225.07:40:37.93#ibcon#read 3, iclass 29, count 0 2006.225.07:40:37.93#ibcon#about to read 4, iclass 29, count 0 2006.225.07:40:37.93#ibcon#read 4, iclass 29, count 0 2006.225.07:40:37.93#ibcon#about to read 5, iclass 29, count 0 2006.225.07:40:37.93#ibcon#read 5, iclass 29, count 0 2006.225.07:40:37.93#ibcon#about to read 6, iclass 29, count 0 2006.225.07:40:37.93#ibcon#read 6, iclass 29, count 0 2006.225.07:40:37.93#ibcon#end of sib2, iclass 29, count 0 2006.225.07:40:37.93#ibcon#*after write, iclass 29, count 0 2006.225.07:40:37.93#ibcon#*before return 0, iclass 29, count 0 2006.225.07:40:37.93#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:40:37.93#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:40:37.93#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:40:37.93#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:40:37.93$vc4f8/va=1,8 2006.225.07:40:37.93#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.07:40:37.93#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.07:40:37.93#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:37.93#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:40:37.93#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:40:37.93#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:40:37.93#ibcon#enter wrdev, iclass 31, count 2 2006.225.07:40:37.93#ibcon#first serial, iclass 31, count 2 2006.225.07:40:37.93#ibcon#enter sib2, iclass 31, count 2 2006.225.07:40:37.93#ibcon#flushed, iclass 31, count 2 2006.225.07:40:37.93#ibcon#about to write, iclass 31, count 2 2006.225.07:40:37.93#ibcon#wrote, iclass 31, count 2 2006.225.07:40:37.93#ibcon#about to read 3, iclass 31, count 2 2006.225.07:40:37.96#ibcon#read 3, iclass 31, count 2 2006.225.07:40:37.96#ibcon#about to read 4, iclass 31, count 2 2006.225.07:40:37.96#ibcon#read 4, iclass 31, count 2 2006.225.07:40:37.96#ibcon#about to read 5, iclass 31, count 2 2006.225.07:40:37.96#ibcon#read 5, iclass 31, count 2 2006.225.07:40:37.96#ibcon#about to read 6, iclass 31, count 2 2006.225.07:40:37.96#ibcon#read 6, iclass 31, count 2 2006.225.07:40:37.96#ibcon#end of sib2, iclass 31, count 2 2006.225.07:40:37.96#ibcon#*mode == 0, iclass 31, count 2 2006.225.07:40:37.96#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.07:40:37.96#ibcon#[25=AT01-08\r\n] 2006.225.07:40:37.96#ibcon#*before write, iclass 31, count 2 2006.225.07:40:37.96#ibcon#enter sib2, iclass 31, count 2 2006.225.07:40:37.96#ibcon#flushed, iclass 31, count 2 2006.225.07:40:37.96#ibcon#about to write, iclass 31, count 2 2006.225.07:40:37.96#ibcon#wrote, iclass 31, count 2 2006.225.07:40:37.96#ibcon#about to read 3, iclass 31, count 2 2006.225.07:40:37.99#ibcon#read 3, iclass 31, count 2 2006.225.07:40:37.99#ibcon#about to read 4, iclass 31, count 2 2006.225.07:40:37.99#ibcon#read 4, iclass 31, count 2 2006.225.07:40:37.99#ibcon#about to read 5, iclass 31, count 2 2006.225.07:40:37.99#ibcon#read 5, iclass 31, count 2 2006.225.07:40:37.99#ibcon#about to read 6, iclass 31, count 2 2006.225.07:40:37.99#ibcon#read 6, iclass 31, count 2 2006.225.07:40:37.99#ibcon#end of sib2, iclass 31, count 2 2006.225.07:40:37.99#ibcon#*after write, iclass 31, count 2 2006.225.07:40:37.99#ibcon#*before return 0, iclass 31, count 2 2006.225.07:40:37.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:40:37.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:40:37.99#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.07:40:37.99#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:37.99#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:40:38.11#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:40:38.11#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:40:38.11#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:40:38.11#ibcon#first serial, iclass 31, count 0 2006.225.07:40:38.11#ibcon#enter sib2, iclass 31, count 0 2006.225.07:40:38.11#ibcon#flushed, iclass 31, count 0 2006.225.07:40:38.11#ibcon#about to write, iclass 31, count 0 2006.225.07:40:38.11#ibcon#wrote, iclass 31, count 0 2006.225.07:40:38.11#ibcon#about to read 3, iclass 31, count 0 2006.225.07:40:38.13#ibcon#read 3, iclass 31, count 0 2006.225.07:40:38.13#ibcon#about to read 4, iclass 31, count 0 2006.225.07:40:38.13#ibcon#read 4, iclass 31, count 0 2006.225.07:40:38.13#ibcon#about to read 5, iclass 31, count 0 2006.225.07:40:38.13#ibcon#read 5, iclass 31, count 0 2006.225.07:40:38.13#ibcon#about to read 6, iclass 31, count 0 2006.225.07:40:38.13#ibcon#read 6, iclass 31, count 0 2006.225.07:40:38.13#ibcon#end of sib2, iclass 31, count 0 2006.225.07:40:38.13#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:40:38.13#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:40:38.13#ibcon#[25=USB\r\n] 2006.225.07:40:38.13#ibcon#*before write, iclass 31, count 0 2006.225.07:40:38.13#ibcon#enter sib2, iclass 31, count 0 2006.225.07:40:38.13#ibcon#flushed, iclass 31, count 0 2006.225.07:40:38.13#ibcon#about to write, iclass 31, count 0 2006.225.07:40:38.13#ibcon#wrote, iclass 31, count 0 2006.225.07:40:38.13#ibcon#about to read 3, iclass 31, count 0 2006.225.07:40:38.16#ibcon#read 3, iclass 31, count 0 2006.225.07:40:38.16#ibcon#about to read 4, iclass 31, count 0 2006.225.07:40:38.16#ibcon#read 4, iclass 31, count 0 2006.225.07:40:38.16#ibcon#about to read 5, iclass 31, count 0 2006.225.07:40:38.16#ibcon#read 5, iclass 31, count 0 2006.225.07:40:38.16#ibcon#about to read 6, iclass 31, count 0 2006.225.07:40:38.16#ibcon#read 6, iclass 31, count 0 2006.225.07:40:38.16#ibcon#end of sib2, iclass 31, count 0 2006.225.07:40:38.16#ibcon#*after write, iclass 31, count 0 2006.225.07:40:38.16#ibcon#*before return 0, iclass 31, count 0 2006.225.07:40:38.16#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:40:38.16#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:40:38.16#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:40:38.16#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:40:38.16$vc4f8/valo=2,572.99 2006.225.07:40:38.16#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.07:40:38.16#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.07:40:38.16#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:38.16#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:40:38.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:40:38.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:40:38.16#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:40:38.16#ibcon#first serial, iclass 33, count 0 2006.225.07:40:38.16#ibcon#enter sib2, iclass 33, count 0 2006.225.07:40:38.16#ibcon#flushed, iclass 33, count 0 2006.225.07:40:38.16#ibcon#about to write, iclass 33, count 0 2006.225.07:40:38.16#ibcon#wrote, iclass 33, count 0 2006.225.07:40:38.16#ibcon#about to read 3, iclass 33, count 0 2006.225.07:40:38.19#ibcon#read 3, iclass 33, count 0 2006.225.07:40:38.19#ibcon#about to read 4, iclass 33, count 0 2006.225.07:40:38.19#ibcon#read 4, iclass 33, count 0 2006.225.07:40:38.19#ibcon#about to read 5, iclass 33, count 0 2006.225.07:40:38.19#ibcon#read 5, iclass 33, count 0 2006.225.07:40:38.19#ibcon#about to read 6, iclass 33, count 0 2006.225.07:40:38.19#ibcon#read 6, iclass 33, count 0 2006.225.07:40:38.19#ibcon#end of sib2, iclass 33, count 0 2006.225.07:40:38.19#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:40:38.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:40:38.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:40:38.19#ibcon#*before write, iclass 33, count 0 2006.225.07:40:38.19#ibcon#enter sib2, iclass 33, count 0 2006.225.07:40:38.19#ibcon#flushed, iclass 33, count 0 2006.225.07:40:38.19#ibcon#about to write, iclass 33, count 0 2006.225.07:40:38.19#ibcon#wrote, iclass 33, count 0 2006.225.07:40:38.19#ibcon#about to read 3, iclass 33, count 0 2006.225.07:40:38.23#ibcon#read 3, iclass 33, count 0 2006.225.07:40:38.23#ibcon#about to read 4, iclass 33, count 0 2006.225.07:40:38.23#ibcon#read 4, iclass 33, count 0 2006.225.07:40:38.23#ibcon#about to read 5, iclass 33, count 0 2006.225.07:40:38.23#ibcon#read 5, iclass 33, count 0 2006.225.07:40:38.23#ibcon#about to read 6, iclass 33, count 0 2006.225.07:40:38.23#ibcon#read 6, iclass 33, count 0 2006.225.07:40:38.23#ibcon#end of sib2, iclass 33, count 0 2006.225.07:40:38.23#ibcon#*after write, iclass 33, count 0 2006.225.07:40:38.23#ibcon#*before return 0, iclass 33, count 0 2006.225.07:40:38.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:40:38.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:40:38.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:40:38.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:40:38.23$vc4f8/va=2,7 2006.225.07:40:38.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.07:40:38.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.07:40:38.23#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:38.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:40:38.28#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:40:38.28#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:40:38.28#ibcon#enter wrdev, iclass 35, count 2 2006.225.07:40:38.28#ibcon#first serial, iclass 35, count 2 2006.225.07:40:38.28#ibcon#enter sib2, iclass 35, count 2 2006.225.07:40:38.28#ibcon#flushed, iclass 35, count 2 2006.225.07:40:38.28#ibcon#about to write, iclass 35, count 2 2006.225.07:40:38.28#ibcon#wrote, iclass 35, count 2 2006.225.07:40:38.28#ibcon#about to read 3, iclass 35, count 2 2006.225.07:40:38.30#ibcon#read 3, iclass 35, count 2 2006.225.07:40:38.30#ibcon#about to read 4, iclass 35, count 2 2006.225.07:40:38.30#ibcon#read 4, iclass 35, count 2 2006.225.07:40:38.30#ibcon#about to read 5, iclass 35, count 2 2006.225.07:40:38.30#ibcon#read 5, iclass 35, count 2 2006.225.07:40:38.30#ibcon#about to read 6, iclass 35, count 2 2006.225.07:40:38.30#ibcon#read 6, iclass 35, count 2 2006.225.07:40:38.30#ibcon#end of sib2, iclass 35, count 2 2006.225.07:40:38.30#ibcon#*mode == 0, iclass 35, count 2 2006.225.07:40:38.30#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.07:40:38.30#ibcon#[25=AT02-07\r\n] 2006.225.07:40:38.30#ibcon#*before write, iclass 35, count 2 2006.225.07:40:38.30#ibcon#enter sib2, iclass 35, count 2 2006.225.07:40:38.30#ibcon#flushed, iclass 35, count 2 2006.225.07:40:38.30#ibcon#about to write, iclass 35, count 2 2006.225.07:40:38.30#ibcon#wrote, iclass 35, count 2 2006.225.07:40:38.30#ibcon#about to read 3, iclass 35, count 2 2006.225.07:40:38.33#ibcon#read 3, iclass 35, count 2 2006.225.07:40:38.33#ibcon#about to read 4, iclass 35, count 2 2006.225.07:40:38.33#ibcon#read 4, iclass 35, count 2 2006.225.07:40:38.33#ibcon#about to read 5, iclass 35, count 2 2006.225.07:40:38.33#ibcon#read 5, iclass 35, count 2 2006.225.07:40:38.33#ibcon#about to read 6, iclass 35, count 2 2006.225.07:40:38.33#ibcon#read 6, iclass 35, count 2 2006.225.07:40:38.33#ibcon#end of sib2, iclass 35, count 2 2006.225.07:40:38.33#ibcon#*after write, iclass 35, count 2 2006.225.07:40:38.33#ibcon#*before return 0, iclass 35, count 2 2006.225.07:40:38.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:40:38.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:40:38.33#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.07:40:38.33#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:38.33#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:40:38.45#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:40:38.45#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:40:38.45#ibcon#enter wrdev, iclass 35, count 0 2006.225.07:40:38.45#ibcon#first serial, iclass 35, count 0 2006.225.07:40:38.45#ibcon#enter sib2, iclass 35, count 0 2006.225.07:40:38.45#ibcon#flushed, iclass 35, count 0 2006.225.07:40:38.45#ibcon#about to write, iclass 35, count 0 2006.225.07:40:38.45#ibcon#wrote, iclass 35, count 0 2006.225.07:40:38.45#ibcon#about to read 3, iclass 35, count 0 2006.225.07:40:38.47#ibcon#read 3, iclass 35, count 0 2006.225.07:40:38.47#ibcon#about to read 4, iclass 35, count 0 2006.225.07:40:38.47#ibcon#read 4, iclass 35, count 0 2006.225.07:40:38.47#ibcon#about to read 5, iclass 35, count 0 2006.225.07:40:38.47#ibcon#read 5, iclass 35, count 0 2006.225.07:40:38.47#ibcon#about to read 6, iclass 35, count 0 2006.225.07:40:38.47#ibcon#read 6, iclass 35, count 0 2006.225.07:40:38.47#ibcon#end of sib2, iclass 35, count 0 2006.225.07:40:38.47#ibcon#*mode == 0, iclass 35, count 0 2006.225.07:40:38.47#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.07:40:38.47#ibcon#[25=USB\r\n] 2006.225.07:40:38.47#ibcon#*before write, iclass 35, count 0 2006.225.07:40:38.47#ibcon#enter sib2, iclass 35, count 0 2006.225.07:40:38.47#ibcon#flushed, iclass 35, count 0 2006.225.07:40:38.47#ibcon#about to write, iclass 35, count 0 2006.225.07:40:38.47#ibcon#wrote, iclass 35, count 0 2006.225.07:40:38.47#ibcon#about to read 3, iclass 35, count 0 2006.225.07:40:38.50#ibcon#read 3, iclass 35, count 0 2006.225.07:40:38.50#ibcon#about to read 4, iclass 35, count 0 2006.225.07:40:38.50#ibcon#read 4, iclass 35, count 0 2006.225.07:40:38.50#ibcon#about to read 5, iclass 35, count 0 2006.225.07:40:38.50#ibcon#read 5, iclass 35, count 0 2006.225.07:40:38.50#ibcon#about to read 6, iclass 35, count 0 2006.225.07:40:38.50#ibcon#read 6, iclass 35, count 0 2006.225.07:40:38.50#ibcon#end of sib2, iclass 35, count 0 2006.225.07:40:38.50#ibcon#*after write, iclass 35, count 0 2006.225.07:40:38.50#ibcon#*before return 0, iclass 35, count 0 2006.225.07:40:38.50#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:40:38.50#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:40:38.50#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.07:40:38.50#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.07:40:38.50$vc4f8/valo=3,672.99 2006.225.07:40:38.50#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.07:40:38.50#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.07:40:38.50#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:38.50#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:40:38.50#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:40:38.50#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:40:38.50#ibcon#enter wrdev, iclass 37, count 0 2006.225.07:40:38.50#ibcon#first serial, iclass 37, count 0 2006.225.07:40:38.50#ibcon#enter sib2, iclass 37, count 0 2006.225.07:40:38.50#ibcon#flushed, iclass 37, count 0 2006.225.07:40:38.50#ibcon#about to write, iclass 37, count 0 2006.225.07:40:38.50#ibcon#wrote, iclass 37, count 0 2006.225.07:40:38.50#ibcon#about to read 3, iclass 37, count 0 2006.225.07:40:38.53#ibcon#read 3, iclass 37, count 0 2006.225.07:40:38.53#ibcon#about to read 4, iclass 37, count 0 2006.225.07:40:38.53#ibcon#read 4, iclass 37, count 0 2006.225.07:40:38.53#ibcon#about to read 5, iclass 37, count 0 2006.225.07:40:38.53#ibcon#read 5, iclass 37, count 0 2006.225.07:40:38.53#ibcon#about to read 6, iclass 37, count 0 2006.225.07:40:38.53#ibcon#read 6, iclass 37, count 0 2006.225.07:40:38.53#ibcon#end of sib2, iclass 37, count 0 2006.225.07:40:38.53#ibcon#*mode == 0, iclass 37, count 0 2006.225.07:40:38.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.07:40:38.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:40:38.53#ibcon#*before write, iclass 37, count 0 2006.225.07:40:38.53#ibcon#enter sib2, iclass 37, count 0 2006.225.07:40:38.53#ibcon#flushed, iclass 37, count 0 2006.225.07:40:38.53#ibcon#about to write, iclass 37, count 0 2006.225.07:40:38.53#ibcon#wrote, iclass 37, count 0 2006.225.07:40:38.53#ibcon#about to read 3, iclass 37, count 0 2006.225.07:40:38.57#ibcon#read 3, iclass 37, count 0 2006.225.07:40:38.57#ibcon#about to read 4, iclass 37, count 0 2006.225.07:40:38.57#ibcon#read 4, iclass 37, count 0 2006.225.07:40:38.57#ibcon#about to read 5, iclass 37, count 0 2006.225.07:40:38.57#ibcon#read 5, iclass 37, count 0 2006.225.07:40:38.57#ibcon#about to read 6, iclass 37, count 0 2006.225.07:40:38.57#ibcon#read 6, iclass 37, count 0 2006.225.07:40:38.57#ibcon#end of sib2, iclass 37, count 0 2006.225.07:40:38.57#ibcon#*after write, iclass 37, count 0 2006.225.07:40:38.57#ibcon#*before return 0, iclass 37, count 0 2006.225.07:40:38.57#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:40:38.57#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:40:38.57#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.07:40:38.57#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.07:40:38.57$vc4f8/va=3,6 2006.225.07:40:38.57#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.07:40:38.57#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.07:40:38.57#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:38.57#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:40:38.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:40:38.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:40:38.62#ibcon#enter wrdev, iclass 39, count 2 2006.225.07:40:38.62#ibcon#first serial, iclass 39, count 2 2006.225.07:40:38.62#ibcon#enter sib2, iclass 39, count 2 2006.225.07:40:38.62#ibcon#flushed, iclass 39, count 2 2006.225.07:40:38.62#ibcon#about to write, iclass 39, count 2 2006.225.07:40:38.62#ibcon#wrote, iclass 39, count 2 2006.225.07:40:38.62#ibcon#about to read 3, iclass 39, count 2 2006.225.07:40:38.64#ibcon#read 3, iclass 39, count 2 2006.225.07:40:38.64#ibcon#about to read 4, iclass 39, count 2 2006.225.07:40:38.64#ibcon#read 4, iclass 39, count 2 2006.225.07:40:38.64#ibcon#about to read 5, iclass 39, count 2 2006.225.07:40:38.64#ibcon#read 5, iclass 39, count 2 2006.225.07:40:38.64#ibcon#about to read 6, iclass 39, count 2 2006.225.07:40:38.64#ibcon#read 6, iclass 39, count 2 2006.225.07:40:38.64#ibcon#end of sib2, iclass 39, count 2 2006.225.07:40:38.64#ibcon#*mode == 0, iclass 39, count 2 2006.225.07:40:38.64#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.07:40:38.64#ibcon#[25=AT03-06\r\n] 2006.225.07:40:38.64#ibcon#*before write, iclass 39, count 2 2006.225.07:40:38.64#ibcon#enter sib2, iclass 39, count 2 2006.225.07:40:38.64#ibcon#flushed, iclass 39, count 2 2006.225.07:40:38.64#ibcon#about to write, iclass 39, count 2 2006.225.07:40:38.64#ibcon#wrote, iclass 39, count 2 2006.225.07:40:38.64#ibcon#about to read 3, iclass 39, count 2 2006.225.07:40:38.67#ibcon#read 3, iclass 39, count 2 2006.225.07:40:38.67#ibcon#about to read 4, iclass 39, count 2 2006.225.07:40:38.67#ibcon#read 4, iclass 39, count 2 2006.225.07:40:38.67#ibcon#about to read 5, iclass 39, count 2 2006.225.07:40:38.67#ibcon#read 5, iclass 39, count 2 2006.225.07:40:38.67#ibcon#about to read 6, iclass 39, count 2 2006.225.07:40:38.67#ibcon#read 6, iclass 39, count 2 2006.225.07:40:38.67#ibcon#end of sib2, iclass 39, count 2 2006.225.07:40:38.67#ibcon#*after write, iclass 39, count 2 2006.225.07:40:38.67#ibcon#*before return 0, iclass 39, count 2 2006.225.07:40:38.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:40:38.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:40:38.67#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.07:40:38.67#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:38.67#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:40:38.79#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:40:38.79#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:40:38.79#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:40:38.79#ibcon#first serial, iclass 39, count 0 2006.225.07:40:38.79#ibcon#enter sib2, iclass 39, count 0 2006.225.07:40:38.79#ibcon#flushed, iclass 39, count 0 2006.225.07:40:38.79#ibcon#about to write, iclass 39, count 0 2006.225.07:40:38.79#ibcon#wrote, iclass 39, count 0 2006.225.07:40:38.79#ibcon#about to read 3, iclass 39, count 0 2006.225.07:40:38.81#ibcon#read 3, iclass 39, count 0 2006.225.07:40:38.81#ibcon#about to read 4, iclass 39, count 0 2006.225.07:40:38.81#ibcon#read 4, iclass 39, count 0 2006.225.07:40:38.81#ibcon#about to read 5, iclass 39, count 0 2006.225.07:40:38.81#ibcon#read 5, iclass 39, count 0 2006.225.07:40:38.81#ibcon#about to read 6, iclass 39, count 0 2006.225.07:40:38.81#ibcon#read 6, iclass 39, count 0 2006.225.07:40:38.81#ibcon#end of sib2, iclass 39, count 0 2006.225.07:40:38.81#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:40:38.81#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:40:38.81#ibcon#[25=USB\r\n] 2006.225.07:40:38.81#ibcon#*before write, iclass 39, count 0 2006.225.07:40:38.81#ibcon#enter sib2, iclass 39, count 0 2006.225.07:40:38.81#ibcon#flushed, iclass 39, count 0 2006.225.07:40:38.81#ibcon#about to write, iclass 39, count 0 2006.225.07:40:38.81#ibcon#wrote, iclass 39, count 0 2006.225.07:40:38.81#ibcon#about to read 3, iclass 39, count 0 2006.225.07:40:38.84#ibcon#read 3, iclass 39, count 0 2006.225.07:40:38.84#ibcon#about to read 4, iclass 39, count 0 2006.225.07:40:38.84#ibcon#read 4, iclass 39, count 0 2006.225.07:40:38.84#ibcon#about to read 5, iclass 39, count 0 2006.225.07:40:38.84#ibcon#read 5, iclass 39, count 0 2006.225.07:40:38.84#ibcon#about to read 6, iclass 39, count 0 2006.225.07:40:38.84#ibcon#read 6, iclass 39, count 0 2006.225.07:40:38.84#ibcon#end of sib2, iclass 39, count 0 2006.225.07:40:38.84#ibcon#*after write, iclass 39, count 0 2006.225.07:40:38.84#ibcon#*before return 0, iclass 39, count 0 2006.225.07:40:38.84#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:40:38.84#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:40:38.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:40:38.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:40:38.84$vc4f8/valo=4,832.99 2006.225.07:40:38.84#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.07:40:38.84#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.07:40:38.84#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:38.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:40:38.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:40:38.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:40:38.84#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:40:38.84#ibcon#first serial, iclass 3, count 0 2006.225.07:40:38.84#ibcon#enter sib2, iclass 3, count 0 2006.225.07:40:38.84#ibcon#flushed, iclass 3, count 0 2006.225.07:40:38.84#ibcon#about to write, iclass 3, count 0 2006.225.07:40:38.84#ibcon#wrote, iclass 3, count 0 2006.225.07:40:38.84#ibcon#about to read 3, iclass 3, count 0 2006.225.07:40:38.87#ibcon#read 3, iclass 3, count 0 2006.225.07:40:38.87#ibcon#about to read 4, iclass 3, count 0 2006.225.07:40:38.87#ibcon#read 4, iclass 3, count 0 2006.225.07:40:38.87#ibcon#about to read 5, iclass 3, count 0 2006.225.07:40:38.87#ibcon#read 5, iclass 3, count 0 2006.225.07:40:38.87#ibcon#about to read 6, iclass 3, count 0 2006.225.07:40:38.87#ibcon#read 6, iclass 3, count 0 2006.225.07:40:38.87#ibcon#end of sib2, iclass 3, count 0 2006.225.07:40:38.87#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:40:38.87#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:40:38.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:40:38.87#ibcon#*before write, iclass 3, count 0 2006.225.07:40:38.87#ibcon#enter sib2, iclass 3, count 0 2006.225.07:40:38.87#ibcon#flushed, iclass 3, count 0 2006.225.07:40:38.87#ibcon#about to write, iclass 3, count 0 2006.225.07:40:38.87#ibcon#wrote, iclass 3, count 0 2006.225.07:40:38.87#ibcon#about to read 3, iclass 3, count 0 2006.225.07:40:38.91#ibcon#read 3, iclass 3, count 0 2006.225.07:40:38.91#ibcon#about to read 4, iclass 3, count 0 2006.225.07:40:38.91#ibcon#read 4, iclass 3, count 0 2006.225.07:40:38.91#ibcon#about to read 5, iclass 3, count 0 2006.225.07:40:38.91#ibcon#read 5, iclass 3, count 0 2006.225.07:40:38.91#ibcon#about to read 6, iclass 3, count 0 2006.225.07:40:38.91#ibcon#read 6, iclass 3, count 0 2006.225.07:40:38.91#ibcon#end of sib2, iclass 3, count 0 2006.225.07:40:38.91#ibcon#*after write, iclass 3, count 0 2006.225.07:40:38.91#ibcon#*before return 0, iclass 3, count 0 2006.225.07:40:38.91#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:40:38.91#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:40:38.91#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:40:38.91#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:40:38.91$vc4f8/va=4,7 2006.225.07:40:38.91#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.07:40:38.91#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.07:40:38.91#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:38.91#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:40:38.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:40:38.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:40:38.96#ibcon#enter wrdev, iclass 5, count 2 2006.225.07:40:38.96#ibcon#first serial, iclass 5, count 2 2006.225.07:40:38.96#ibcon#enter sib2, iclass 5, count 2 2006.225.07:40:38.96#ibcon#flushed, iclass 5, count 2 2006.225.07:40:38.96#ibcon#about to write, iclass 5, count 2 2006.225.07:40:38.96#ibcon#wrote, iclass 5, count 2 2006.225.07:40:38.96#ibcon#about to read 3, iclass 5, count 2 2006.225.07:40:38.98#ibcon#read 3, iclass 5, count 2 2006.225.07:40:38.98#ibcon#about to read 4, iclass 5, count 2 2006.225.07:40:38.98#ibcon#read 4, iclass 5, count 2 2006.225.07:40:38.98#ibcon#about to read 5, iclass 5, count 2 2006.225.07:40:38.98#ibcon#read 5, iclass 5, count 2 2006.225.07:40:38.98#ibcon#about to read 6, iclass 5, count 2 2006.225.07:40:38.98#ibcon#read 6, iclass 5, count 2 2006.225.07:40:38.98#ibcon#end of sib2, iclass 5, count 2 2006.225.07:40:38.98#ibcon#*mode == 0, iclass 5, count 2 2006.225.07:40:38.98#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.07:40:38.98#ibcon#[25=AT04-07\r\n] 2006.225.07:40:38.98#ibcon#*before write, iclass 5, count 2 2006.225.07:40:38.98#ibcon#enter sib2, iclass 5, count 2 2006.225.07:40:38.98#ibcon#flushed, iclass 5, count 2 2006.225.07:40:38.98#ibcon#about to write, iclass 5, count 2 2006.225.07:40:38.98#ibcon#wrote, iclass 5, count 2 2006.225.07:40:38.98#ibcon#about to read 3, iclass 5, count 2 2006.225.07:40:39.01#ibcon#read 3, iclass 5, count 2 2006.225.07:40:39.01#ibcon#about to read 4, iclass 5, count 2 2006.225.07:40:39.01#ibcon#read 4, iclass 5, count 2 2006.225.07:40:39.01#ibcon#about to read 5, iclass 5, count 2 2006.225.07:40:39.01#ibcon#read 5, iclass 5, count 2 2006.225.07:40:39.01#ibcon#about to read 6, iclass 5, count 2 2006.225.07:40:39.01#ibcon#read 6, iclass 5, count 2 2006.225.07:40:39.01#ibcon#end of sib2, iclass 5, count 2 2006.225.07:40:39.01#ibcon#*after write, iclass 5, count 2 2006.225.07:40:39.01#ibcon#*before return 0, iclass 5, count 2 2006.225.07:40:39.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:40:39.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:40:39.01#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.07:40:39.01#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:39.01#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:40:39.13#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:40:39.13#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:40:39.13#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:40:39.13#ibcon#first serial, iclass 5, count 0 2006.225.07:40:39.13#ibcon#enter sib2, iclass 5, count 0 2006.225.07:40:39.13#ibcon#flushed, iclass 5, count 0 2006.225.07:40:39.13#ibcon#about to write, iclass 5, count 0 2006.225.07:40:39.13#ibcon#wrote, iclass 5, count 0 2006.225.07:40:39.13#ibcon#about to read 3, iclass 5, count 0 2006.225.07:40:39.15#ibcon#read 3, iclass 5, count 0 2006.225.07:40:39.15#ibcon#about to read 4, iclass 5, count 0 2006.225.07:40:39.15#ibcon#read 4, iclass 5, count 0 2006.225.07:40:39.15#ibcon#about to read 5, iclass 5, count 0 2006.225.07:40:39.15#ibcon#read 5, iclass 5, count 0 2006.225.07:40:39.15#ibcon#about to read 6, iclass 5, count 0 2006.225.07:40:39.15#ibcon#read 6, iclass 5, count 0 2006.225.07:40:39.15#ibcon#end of sib2, iclass 5, count 0 2006.225.07:40:39.15#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:40:39.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:40:39.15#ibcon#[25=USB\r\n] 2006.225.07:40:39.15#ibcon#*before write, iclass 5, count 0 2006.225.07:40:39.15#ibcon#enter sib2, iclass 5, count 0 2006.225.07:40:39.15#ibcon#flushed, iclass 5, count 0 2006.225.07:40:39.15#ibcon#about to write, iclass 5, count 0 2006.225.07:40:39.15#ibcon#wrote, iclass 5, count 0 2006.225.07:40:39.15#ibcon#about to read 3, iclass 5, count 0 2006.225.07:40:39.18#ibcon#read 3, iclass 5, count 0 2006.225.07:40:39.18#ibcon#about to read 4, iclass 5, count 0 2006.225.07:40:39.18#ibcon#read 4, iclass 5, count 0 2006.225.07:40:39.18#ibcon#about to read 5, iclass 5, count 0 2006.225.07:40:39.18#ibcon#read 5, iclass 5, count 0 2006.225.07:40:39.18#ibcon#about to read 6, iclass 5, count 0 2006.225.07:40:39.18#ibcon#read 6, iclass 5, count 0 2006.225.07:40:39.18#ibcon#end of sib2, iclass 5, count 0 2006.225.07:40:39.18#ibcon#*after write, iclass 5, count 0 2006.225.07:40:39.18#ibcon#*before return 0, iclass 5, count 0 2006.225.07:40:39.18#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:40:39.18#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:40:39.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:40:39.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:40:39.18$vc4f8/valo=5,652.99 2006.225.07:40:39.18#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.225.07:40:39.18#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.225.07:40:39.18#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:39.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:40:39.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:40:39.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:40:39.18#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:40:39.18#ibcon#first serial, iclass 7, count 0 2006.225.07:40:39.18#ibcon#enter sib2, iclass 7, count 0 2006.225.07:40:39.18#ibcon#flushed, iclass 7, count 0 2006.225.07:40:39.18#ibcon#about to write, iclass 7, count 0 2006.225.07:40:39.18#ibcon#wrote, iclass 7, count 0 2006.225.07:40:39.18#ibcon#about to read 3, iclass 7, count 0 2006.225.07:40:39.20#ibcon#read 3, iclass 7, count 0 2006.225.07:40:39.20#ibcon#about to read 4, iclass 7, count 0 2006.225.07:40:39.20#ibcon#read 4, iclass 7, count 0 2006.225.07:40:39.20#ibcon#about to read 5, iclass 7, count 0 2006.225.07:40:39.20#ibcon#read 5, iclass 7, count 0 2006.225.07:40:39.20#ibcon#about to read 6, iclass 7, count 0 2006.225.07:40:39.20#ibcon#read 6, iclass 7, count 0 2006.225.07:40:39.20#ibcon#end of sib2, iclass 7, count 0 2006.225.07:40:39.20#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:40:39.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:40:39.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:40:39.20#ibcon#*before write, iclass 7, count 0 2006.225.07:40:39.20#ibcon#enter sib2, iclass 7, count 0 2006.225.07:40:39.20#ibcon#flushed, iclass 7, count 0 2006.225.07:40:39.20#ibcon#about to write, iclass 7, count 0 2006.225.07:40:39.20#ibcon#wrote, iclass 7, count 0 2006.225.07:40:39.20#ibcon#about to read 3, iclass 7, count 0 2006.225.07:40:39.24#ibcon#read 3, iclass 7, count 0 2006.225.07:40:39.24#ibcon#about to read 4, iclass 7, count 0 2006.225.07:40:39.24#ibcon#read 4, iclass 7, count 0 2006.225.07:40:39.24#ibcon#about to read 5, iclass 7, count 0 2006.225.07:40:39.24#ibcon#read 5, iclass 7, count 0 2006.225.07:40:39.24#ibcon#about to read 6, iclass 7, count 0 2006.225.07:40:39.24#ibcon#read 6, iclass 7, count 0 2006.225.07:40:39.24#ibcon#end of sib2, iclass 7, count 0 2006.225.07:40:39.24#ibcon#*after write, iclass 7, count 0 2006.225.07:40:39.24#ibcon#*before return 0, iclass 7, count 0 2006.225.07:40:39.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:40:39.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:40:39.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:40:39.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:40:39.24$vc4f8/va=5,7 2006.225.07:40:39.24#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.225.07:40:39.24#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.225.07:40:39.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:39.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:40:39.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:40:39.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:40:39.30#ibcon#enter wrdev, iclass 11, count 2 2006.225.07:40:39.30#ibcon#first serial, iclass 11, count 2 2006.225.07:40:39.30#ibcon#enter sib2, iclass 11, count 2 2006.225.07:40:39.30#ibcon#flushed, iclass 11, count 2 2006.225.07:40:39.30#ibcon#about to write, iclass 11, count 2 2006.225.07:40:39.30#ibcon#wrote, iclass 11, count 2 2006.225.07:40:39.30#ibcon#about to read 3, iclass 11, count 2 2006.225.07:40:39.32#ibcon#read 3, iclass 11, count 2 2006.225.07:40:39.32#ibcon#about to read 4, iclass 11, count 2 2006.225.07:40:39.32#ibcon#read 4, iclass 11, count 2 2006.225.07:40:39.32#ibcon#about to read 5, iclass 11, count 2 2006.225.07:40:39.32#ibcon#read 5, iclass 11, count 2 2006.225.07:40:39.32#ibcon#about to read 6, iclass 11, count 2 2006.225.07:40:39.32#ibcon#read 6, iclass 11, count 2 2006.225.07:40:39.32#ibcon#end of sib2, iclass 11, count 2 2006.225.07:40:39.32#ibcon#*mode == 0, iclass 11, count 2 2006.225.07:40:39.32#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.225.07:40:39.32#ibcon#[25=AT05-07\r\n] 2006.225.07:40:39.32#ibcon#*before write, iclass 11, count 2 2006.225.07:40:39.32#ibcon#enter sib2, iclass 11, count 2 2006.225.07:40:39.32#ibcon#flushed, iclass 11, count 2 2006.225.07:40:39.32#ibcon#about to write, iclass 11, count 2 2006.225.07:40:39.32#ibcon#wrote, iclass 11, count 2 2006.225.07:40:39.32#ibcon#about to read 3, iclass 11, count 2 2006.225.07:40:39.35#ibcon#read 3, iclass 11, count 2 2006.225.07:40:39.35#ibcon#about to read 4, iclass 11, count 2 2006.225.07:40:39.35#ibcon#read 4, iclass 11, count 2 2006.225.07:40:39.35#ibcon#about to read 5, iclass 11, count 2 2006.225.07:40:39.35#ibcon#read 5, iclass 11, count 2 2006.225.07:40:39.35#ibcon#about to read 6, iclass 11, count 2 2006.225.07:40:39.35#ibcon#read 6, iclass 11, count 2 2006.225.07:40:39.35#ibcon#end of sib2, iclass 11, count 2 2006.225.07:40:39.35#ibcon#*after write, iclass 11, count 2 2006.225.07:40:39.35#ibcon#*before return 0, iclass 11, count 2 2006.225.07:40:39.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:40:39.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:40:39.35#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.225.07:40:39.35#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:39.35#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:40:39.47#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:40:39.47#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:40:39.47#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:40:39.47#ibcon#first serial, iclass 11, count 0 2006.225.07:40:39.47#ibcon#enter sib2, iclass 11, count 0 2006.225.07:40:39.47#ibcon#flushed, iclass 11, count 0 2006.225.07:40:39.47#ibcon#about to write, iclass 11, count 0 2006.225.07:40:39.47#ibcon#wrote, iclass 11, count 0 2006.225.07:40:39.47#ibcon#about to read 3, iclass 11, count 0 2006.225.07:40:39.49#ibcon#read 3, iclass 11, count 0 2006.225.07:40:39.49#ibcon#about to read 4, iclass 11, count 0 2006.225.07:40:39.49#ibcon#read 4, iclass 11, count 0 2006.225.07:40:39.49#ibcon#about to read 5, iclass 11, count 0 2006.225.07:40:39.49#ibcon#read 5, iclass 11, count 0 2006.225.07:40:39.49#ibcon#about to read 6, iclass 11, count 0 2006.225.07:40:39.49#ibcon#read 6, iclass 11, count 0 2006.225.07:40:39.49#ibcon#end of sib2, iclass 11, count 0 2006.225.07:40:39.49#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:40:39.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:40:39.49#ibcon#[25=USB\r\n] 2006.225.07:40:39.49#ibcon#*before write, iclass 11, count 0 2006.225.07:40:39.49#ibcon#enter sib2, iclass 11, count 0 2006.225.07:40:39.49#ibcon#flushed, iclass 11, count 0 2006.225.07:40:39.49#ibcon#about to write, iclass 11, count 0 2006.225.07:40:39.49#ibcon#wrote, iclass 11, count 0 2006.225.07:40:39.49#ibcon#about to read 3, iclass 11, count 0 2006.225.07:40:39.52#ibcon#read 3, iclass 11, count 0 2006.225.07:40:39.52#ibcon#about to read 4, iclass 11, count 0 2006.225.07:40:39.52#ibcon#read 4, iclass 11, count 0 2006.225.07:40:39.52#ibcon#about to read 5, iclass 11, count 0 2006.225.07:40:39.52#ibcon#read 5, iclass 11, count 0 2006.225.07:40:39.52#ibcon#about to read 6, iclass 11, count 0 2006.225.07:40:39.52#ibcon#read 6, iclass 11, count 0 2006.225.07:40:39.52#ibcon#end of sib2, iclass 11, count 0 2006.225.07:40:39.52#ibcon#*after write, iclass 11, count 0 2006.225.07:40:39.52#ibcon#*before return 0, iclass 11, count 0 2006.225.07:40:39.52#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:40:39.52#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:40:39.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:40:39.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:40:39.52$vc4f8/valo=6,772.99 2006.225.07:40:39.52#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.07:40:39.52#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.07:40:39.52#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:39.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:40:39.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:40:39.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:40:39.52#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:40:39.52#ibcon#first serial, iclass 13, count 0 2006.225.07:40:39.52#ibcon#enter sib2, iclass 13, count 0 2006.225.07:40:39.52#ibcon#flushed, iclass 13, count 0 2006.225.07:40:39.52#ibcon#about to write, iclass 13, count 0 2006.225.07:40:39.52#ibcon#wrote, iclass 13, count 0 2006.225.07:40:39.52#ibcon#about to read 3, iclass 13, count 0 2006.225.07:40:39.54#ibcon#read 3, iclass 13, count 0 2006.225.07:40:39.54#ibcon#about to read 4, iclass 13, count 0 2006.225.07:40:39.54#ibcon#read 4, iclass 13, count 0 2006.225.07:40:39.54#ibcon#about to read 5, iclass 13, count 0 2006.225.07:40:39.54#ibcon#read 5, iclass 13, count 0 2006.225.07:40:39.54#ibcon#about to read 6, iclass 13, count 0 2006.225.07:40:39.54#ibcon#read 6, iclass 13, count 0 2006.225.07:40:39.54#ibcon#end of sib2, iclass 13, count 0 2006.225.07:40:39.54#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:40:39.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:40:39.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:40:39.54#ibcon#*before write, iclass 13, count 0 2006.225.07:40:39.54#ibcon#enter sib2, iclass 13, count 0 2006.225.07:40:39.54#ibcon#flushed, iclass 13, count 0 2006.225.07:40:39.54#ibcon#about to write, iclass 13, count 0 2006.225.07:40:39.54#ibcon#wrote, iclass 13, count 0 2006.225.07:40:39.54#ibcon#about to read 3, iclass 13, count 0 2006.225.07:40:39.58#ibcon#read 3, iclass 13, count 0 2006.225.07:40:39.58#ibcon#about to read 4, iclass 13, count 0 2006.225.07:40:39.58#ibcon#read 4, iclass 13, count 0 2006.225.07:40:39.58#ibcon#about to read 5, iclass 13, count 0 2006.225.07:40:39.58#ibcon#read 5, iclass 13, count 0 2006.225.07:40:39.58#ibcon#about to read 6, iclass 13, count 0 2006.225.07:40:39.58#ibcon#read 6, iclass 13, count 0 2006.225.07:40:39.58#ibcon#end of sib2, iclass 13, count 0 2006.225.07:40:39.58#ibcon#*after write, iclass 13, count 0 2006.225.07:40:39.58#ibcon#*before return 0, iclass 13, count 0 2006.225.07:40:39.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:40:39.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:40:39.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:40:39.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:40:39.58$vc4f8/va=6,6 2006.225.07:40:39.58#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.225.07:40:39.58#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.225.07:40:39.58#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:39.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:40:39.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:40:39.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:40:39.64#ibcon#enter wrdev, iclass 15, count 2 2006.225.07:40:39.64#ibcon#first serial, iclass 15, count 2 2006.225.07:40:39.64#ibcon#enter sib2, iclass 15, count 2 2006.225.07:40:39.64#ibcon#flushed, iclass 15, count 2 2006.225.07:40:39.64#ibcon#about to write, iclass 15, count 2 2006.225.07:40:39.64#ibcon#wrote, iclass 15, count 2 2006.225.07:40:39.64#ibcon#about to read 3, iclass 15, count 2 2006.225.07:40:39.66#ibcon#read 3, iclass 15, count 2 2006.225.07:40:39.66#ibcon#about to read 4, iclass 15, count 2 2006.225.07:40:39.66#ibcon#read 4, iclass 15, count 2 2006.225.07:40:39.66#ibcon#about to read 5, iclass 15, count 2 2006.225.07:40:39.66#ibcon#read 5, iclass 15, count 2 2006.225.07:40:39.66#ibcon#about to read 6, iclass 15, count 2 2006.225.07:40:39.66#ibcon#read 6, iclass 15, count 2 2006.225.07:40:39.66#ibcon#end of sib2, iclass 15, count 2 2006.225.07:40:39.66#ibcon#*mode == 0, iclass 15, count 2 2006.225.07:40:39.66#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.225.07:40:39.66#ibcon#[25=AT06-06\r\n] 2006.225.07:40:39.66#ibcon#*before write, iclass 15, count 2 2006.225.07:40:39.66#ibcon#enter sib2, iclass 15, count 2 2006.225.07:40:39.66#ibcon#flushed, iclass 15, count 2 2006.225.07:40:39.66#ibcon#about to write, iclass 15, count 2 2006.225.07:40:39.66#ibcon#wrote, iclass 15, count 2 2006.225.07:40:39.66#ibcon#about to read 3, iclass 15, count 2 2006.225.07:40:39.69#ibcon#read 3, iclass 15, count 2 2006.225.07:40:39.69#ibcon#about to read 4, iclass 15, count 2 2006.225.07:40:39.69#ibcon#read 4, iclass 15, count 2 2006.225.07:40:39.69#ibcon#about to read 5, iclass 15, count 2 2006.225.07:40:39.69#ibcon#read 5, iclass 15, count 2 2006.225.07:40:39.69#ibcon#about to read 6, iclass 15, count 2 2006.225.07:40:39.69#ibcon#read 6, iclass 15, count 2 2006.225.07:40:39.69#ibcon#end of sib2, iclass 15, count 2 2006.225.07:40:39.69#ibcon#*after write, iclass 15, count 2 2006.225.07:40:39.69#ibcon#*before return 0, iclass 15, count 2 2006.225.07:40:39.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:40:39.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:40:39.69#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.225.07:40:39.69#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:39.69#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:40:39.81#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:40:39.81#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:40:39.81#ibcon#enter wrdev, iclass 15, count 0 2006.225.07:40:39.81#ibcon#first serial, iclass 15, count 0 2006.225.07:40:39.81#ibcon#enter sib2, iclass 15, count 0 2006.225.07:40:39.81#ibcon#flushed, iclass 15, count 0 2006.225.07:40:39.81#ibcon#about to write, iclass 15, count 0 2006.225.07:40:39.81#ibcon#wrote, iclass 15, count 0 2006.225.07:40:39.81#ibcon#about to read 3, iclass 15, count 0 2006.225.07:40:39.83#ibcon#read 3, iclass 15, count 0 2006.225.07:40:39.83#ibcon#about to read 4, iclass 15, count 0 2006.225.07:40:39.83#ibcon#read 4, iclass 15, count 0 2006.225.07:40:39.83#ibcon#about to read 5, iclass 15, count 0 2006.225.07:40:39.83#ibcon#read 5, iclass 15, count 0 2006.225.07:40:39.83#ibcon#about to read 6, iclass 15, count 0 2006.225.07:40:39.83#ibcon#read 6, iclass 15, count 0 2006.225.07:40:39.83#ibcon#end of sib2, iclass 15, count 0 2006.225.07:40:39.83#ibcon#*mode == 0, iclass 15, count 0 2006.225.07:40:39.83#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.07:40:39.83#ibcon#[25=USB\r\n] 2006.225.07:40:39.83#ibcon#*before write, iclass 15, count 0 2006.225.07:40:39.83#ibcon#enter sib2, iclass 15, count 0 2006.225.07:40:39.83#ibcon#flushed, iclass 15, count 0 2006.225.07:40:39.83#ibcon#about to write, iclass 15, count 0 2006.225.07:40:39.83#ibcon#wrote, iclass 15, count 0 2006.225.07:40:39.83#ibcon#about to read 3, iclass 15, count 0 2006.225.07:40:39.86#ibcon#read 3, iclass 15, count 0 2006.225.07:40:39.86#ibcon#about to read 4, iclass 15, count 0 2006.225.07:40:39.86#ibcon#read 4, iclass 15, count 0 2006.225.07:40:39.86#ibcon#about to read 5, iclass 15, count 0 2006.225.07:40:39.86#ibcon#read 5, iclass 15, count 0 2006.225.07:40:39.86#ibcon#about to read 6, iclass 15, count 0 2006.225.07:40:39.86#ibcon#read 6, iclass 15, count 0 2006.225.07:40:39.86#ibcon#end of sib2, iclass 15, count 0 2006.225.07:40:39.86#ibcon#*after write, iclass 15, count 0 2006.225.07:40:39.86#ibcon#*before return 0, iclass 15, count 0 2006.225.07:40:39.86#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:40:39.86#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:40:39.86#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.07:40:39.86#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.07:40:39.86$vc4f8/valo=7,832.99 2006.225.07:40:39.86#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.225.07:40:39.86#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.225.07:40:39.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:39.86#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:40:39.86#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:40:39.86#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:40:39.86#ibcon#enter wrdev, iclass 17, count 0 2006.225.07:40:39.86#ibcon#first serial, iclass 17, count 0 2006.225.07:40:39.86#ibcon#enter sib2, iclass 17, count 0 2006.225.07:40:39.86#ibcon#flushed, iclass 17, count 0 2006.225.07:40:39.86#ibcon#about to write, iclass 17, count 0 2006.225.07:40:39.86#ibcon#wrote, iclass 17, count 0 2006.225.07:40:39.86#ibcon#about to read 3, iclass 17, count 0 2006.225.07:40:39.88#ibcon#read 3, iclass 17, count 0 2006.225.07:40:39.88#ibcon#about to read 4, iclass 17, count 0 2006.225.07:40:39.88#ibcon#read 4, iclass 17, count 0 2006.225.07:40:39.88#ibcon#about to read 5, iclass 17, count 0 2006.225.07:40:39.88#ibcon#read 5, iclass 17, count 0 2006.225.07:40:39.88#ibcon#about to read 6, iclass 17, count 0 2006.225.07:40:39.88#ibcon#read 6, iclass 17, count 0 2006.225.07:40:39.88#ibcon#end of sib2, iclass 17, count 0 2006.225.07:40:39.88#ibcon#*mode == 0, iclass 17, count 0 2006.225.07:40:39.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.07:40:39.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:40:39.88#ibcon#*before write, iclass 17, count 0 2006.225.07:40:39.88#ibcon#enter sib2, iclass 17, count 0 2006.225.07:40:39.88#ibcon#flushed, iclass 17, count 0 2006.225.07:40:39.88#ibcon#about to write, iclass 17, count 0 2006.225.07:40:39.88#ibcon#wrote, iclass 17, count 0 2006.225.07:40:39.88#ibcon#about to read 3, iclass 17, count 0 2006.225.07:40:39.92#ibcon#read 3, iclass 17, count 0 2006.225.07:40:39.92#ibcon#about to read 4, iclass 17, count 0 2006.225.07:40:39.92#ibcon#read 4, iclass 17, count 0 2006.225.07:40:39.92#ibcon#about to read 5, iclass 17, count 0 2006.225.07:40:39.92#ibcon#read 5, iclass 17, count 0 2006.225.07:40:39.92#ibcon#about to read 6, iclass 17, count 0 2006.225.07:40:39.92#ibcon#read 6, iclass 17, count 0 2006.225.07:40:39.92#ibcon#end of sib2, iclass 17, count 0 2006.225.07:40:39.92#ibcon#*after write, iclass 17, count 0 2006.225.07:40:39.92#ibcon#*before return 0, iclass 17, count 0 2006.225.07:40:39.92#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:40:39.92#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:40:39.92#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.07:40:39.92#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.07:40:39.92$vc4f8/va=7,6 2006.225.07:40:39.92#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.225.07:40:39.92#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.225.07:40:39.92#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:39.92#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:40:39.98#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:40:39.98#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:40:39.98#ibcon#enter wrdev, iclass 19, count 2 2006.225.07:40:39.98#ibcon#first serial, iclass 19, count 2 2006.225.07:40:39.98#ibcon#enter sib2, iclass 19, count 2 2006.225.07:40:39.98#ibcon#flushed, iclass 19, count 2 2006.225.07:40:39.98#ibcon#about to write, iclass 19, count 2 2006.225.07:40:39.98#ibcon#wrote, iclass 19, count 2 2006.225.07:40:39.98#ibcon#about to read 3, iclass 19, count 2 2006.225.07:40:40.00#ibcon#read 3, iclass 19, count 2 2006.225.07:40:40.00#ibcon#about to read 4, iclass 19, count 2 2006.225.07:40:40.00#ibcon#read 4, iclass 19, count 2 2006.225.07:40:40.00#ibcon#about to read 5, iclass 19, count 2 2006.225.07:40:40.00#ibcon#read 5, iclass 19, count 2 2006.225.07:40:40.00#ibcon#about to read 6, iclass 19, count 2 2006.225.07:40:40.00#ibcon#read 6, iclass 19, count 2 2006.225.07:40:40.00#ibcon#end of sib2, iclass 19, count 2 2006.225.07:40:40.00#ibcon#*mode == 0, iclass 19, count 2 2006.225.07:40:40.00#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.225.07:40:40.00#ibcon#[25=AT07-06\r\n] 2006.225.07:40:40.00#ibcon#*before write, iclass 19, count 2 2006.225.07:40:40.00#ibcon#enter sib2, iclass 19, count 2 2006.225.07:40:40.00#ibcon#flushed, iclass 19, count 2 2006.225.07:40:40.00#ibcon#about to write, iclass 19, count 2 2006.225.07:40:40.00#ibcon#wrote, iclass 19, count 2 2006.225.07:40:40.00#ibcon#about to read 3, iclass 19, count 2 2006.225.07:40:40.03#ibcon#read 3, iclass 19, count 2 2006.225.07:40:40.03#ibcon#about to read 4, iclass 19, count 2 2006.225.07:40:40.03#ibcon#read 4, iclass 19, count 2 2006.225.07:40:40.03#ibcon#about to read 5, iclass 19, count 2 2006.225.07:40:40.03#ibcon#read 5, iclass 19, count 2 2006.225.07:40:40.03#ibcon#about to read 6, iclass 19, count 2 2006.225.07:40:40.03#ibcon#read 6, iclass 19, count 2 2006.225.07:40:40.03#ibcon#end of sib2, iclass 19, count 2 2006.225.07:40:40.03#ibcon#*after write, iclass 19, count 2 2006.225.07:40:40.03#ibcon#*before return 0, iclass 19, count 2 2006.225.07:40:40.03#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:40:40.03#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:40:40.03#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.225.07:40:40.03#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:40.03#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:40:40.15#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:40:40.15#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:40:40.15#ibcon#enter wrdev, iclass 19, count 0 2006.225.07:40:40.15#ibcon#first serial, iclass 19, count 0 2006.225.07:40:40.15#ibcon#enter sib2, iclass 19, count 0 2006.225.07:40:40.15#ibcon#flushed, iclass 19, count 0 2006.225.07:40:40.15#ibcon#about to write, iclass 19, count 0 2006.225.07:40:40.15#ibcon#wrote, iclass 19, count 0 2006.225.07:40:40.15#ibcon#about to read 3, iclass 19, count 0 2006.225.07:40:40.17#ibcon#read 3, iclass 19, count 0 2006.225.07:40:40.17#ibcon#about to read 4, iclass 19, count 0 2006.225.07:40:40.17#ibcon#read 4, iclass 19, count 0 2006.225.07:40:40.17#ibcon#about to read 5, iclass 19, count 0 2006.225.07:40:40.17#ibcon#read 5, iclass 19, count 0 2006.225.07:40:40.17#ibcon#about to read 6, iclass 19, count 0 2006.225.07:40:40.17#ibcon#read 6, iclass 19, count 0 2006.225.07:40:40.17#ibcon#end of sib2, iclass 19, count 0 2006.225.07:40:40.17#ibcon#*mode == 0, iclass 19, count 0 2006.225.07:40:40.17#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.07:40:40.17#ibcon#[25=USB\r\n] 2006.225.07:40:40.17#ibcon#*before write, iclass 19, count 0 2006.225.07:40:40.17#ibcon#enter sib2, iclass 19, count 0 2006.225.07:40:40.17#ibcon#flushed, iclass 19, count 0 2006.225.07:40:40.17#ibcon#about to write, iclass 19, count 0 2006.225.07:40:40.17#ibcon#wrote, iclass 19, count 0 2006.225.07:40:40.17#ibcon#about to read 3, iclass 19, count 0 2006.225.07:40:40.20#ibcon#read 3, iclass 19, count 0 2006.225.07:40:40.20#ibcon#about to read 4, iclass 19, count 0 2006.225.07:40:40.20#ibcon#read 4, iclass 19, count 0 2006.225.07:40:40.20#ibcon#about to read 5, iclass 19, count 0 2006.225.07:40:40.20#ibcon#read 5, iclass 19, count 0 2006.225.07:40:40.20#ibcon#about to read 6, iclass 19, count 0 2006.225.07:40:40.20#ibcon#read 6, iclass 19, count 0 2006.225.07:40:40.20#ibcon#end of sib2, iclass 19, count 0 2006.225.07:40:40.20#ibcon#*after write, iclass 19, count 0 2006.225.07:40:40.20#ibcon#*before return 0, iclass 19, count 0 2006.225.07:40:40.20#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:40:40.20#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:40:40.20#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.07:40:40.20#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.07:40:40.20$vc4f8/valo=8,852.99 2006.225.07:40:40.20#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.225.07:40:40.20#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.225.07:40:40.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:40.20#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:40:40.20#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:40:40.20#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:40:40.20#ibcon#enter wrdev, iclass 21, count 0 2006.225.07:40:40.20#ibcon#first serial, iclass 21, count 0 2006.225.07:40:40.20#ibcon#enter sib2, iclass 21, count 0 2006.225.07:40:40.20#ibcon#flushed, iclass 21, count 0 2006.225.07:40:40.20#ibcon#about to write, iclass 21, count 0 2006.225.07:40:40.20#ibcon#wrote, iclass 21, count 0 2006.225.07:40:40.20#ibcon#about to read 3, iclass 21, count 0 2006.225.07:40:40.22#ibcon#read 3, iclass 21, count 0 2006.225.07:40:40.22#ibcon#about to read 4, iclass 21, count 0 2006.225.07:40:40.22#ibcon#read 4, iclass 21, count 0 2006.225.07:40:40.22#ibcon#about to read 5, iclass 21, count 0 2006.225.07:40:40.22#ibcon#read 5, iclass 21, count 0 2006.225.07:40:40.22#ibcon#about to read 6, iclass 21, count 0 2006.225.07:40:40.22#ibcon#read 6, iclass 21, count 0 2006.225.07:40:40.22#ibcon#end of sib2, iclass 21, count 0 2006.225.07:40:40.22#ibcon#*mode == 0, iclass 21, count 0 2006.225.07:40:40.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.07:40:40.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:40:40.22#ibcon#*before write, iclass 21, count 0 2006.225.07:40:40.22#ibcon#enter sib2, iclass 21, count 0 2006.225.07:40:40.22#ibcon#flushed, iclass 21, count 0 2006.225.07:40:40.22#ibcon#about to write, iclass 21, count 0 2006.225.07:40:40.22#ibcon#wrote, iclass 21, count 0 2006.225.07:40:40.22#ibcon#about to read 3, iclass 21, count 0 2006.225.07:40:40.26#ibcon#read 3, iclass 21, count 0 2006.225.07:40:40.26#ibcon#about to read 4, iclass 21, count 0 2006.225.07:40:40.26#ibcon#read 4, iclass 21, count 0 2006.225.07:40:40.26#ibcon#about to read 5, iclass 21, count 0 2006.225.07:40:40.26#ibcon#read 5, iclass 21, count 0 2006.225.07:40:40.26#ibcon#about to read 6, iclass 21, count 0 2006.225.07:40:40.26#ibcon#read 6, iclass 21, count 0 2006.225.07:40:40.26#ibcon#end of sib2, iclass 21, count 0 2006.225.07:40:40.26#ibcon#*after write, iclass 21, count 0 2006.225.07:40:40.26#ibcon#*before return 0, iclass 21, count 0 2006.225.07:40:40.26#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:40:40.26#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:40:40.26#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.07:40:40.26#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.07:40:40.26$vc4f8/va=8,7 2006.225.07:40:40.26#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.225.07:40:40.26#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.225.07:40:40.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:40.26#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:40:40.32#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:40:40.32#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:40:40.32#ibcon#enter wrdev, iclass 23, count 2 2006.225.07:40:40.32#ibcon#first serial, iclass 23, count 2 2006.225.07:40:40.32#ibcon#enter sib2, iclass 23, count 2 2006.225.07:40:40.32#ibcon#flushed, iclass 23, count 2 2006.225.07:40:40.32#ibcon#about to write, iclass 23, count 2 2006.225.07:40:40.32#ibcon#wrote, iclass 23, count 2 2006.225.07:40:40.32#ibcon#about to read 3, iclass 23, count 2 2006.225.07:40:40.34#ibcon#read 3, iclass 23, count 2 2006.225.07:40:40.34#ibcon#about to read 4, iclass 23, count 2 2006.225.07:40:40.34#ibcon#read 4, iclass 23, count 2 2006.225.07:40:40.34#ibcon#about to read 5, iclass 23, count 2 2006.225.07:40:40.34#ibcon#read 5, iclass 23, count 2 2006.225.07:40:40.34#ibcon#about to read 6, iclass 23, count 2 2006.225.07:40:40.34#ibcon#read 6, iclass 23, count 2 2006.225.07:40:40.34#ibcon#end of sib2, iclass 23, count 2 2006.225.07:40:40.34#ibcon#*mode == 0, iclass 23, count 2 2006.225.07:40:40.34#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.225.07:40:40.34#ibcon#[25=AT08-07\r\n] 2006.225.07:40:40.34#ibcon#*before write, iclass 23, count 2 2006.225.07:40:40.34#ibcon#enter sib2, iclass 23, count 2 2006.225.07:40:40.34#ibcon#flushed, iclass 23, count 2 2006.225.07:40:40.34#ibcon#about to write, iclass 23, count 2 2006.225.07:40:40.34#ibcon#wrote, iclass 23, count 2 2006.225.07:40:40.34#ibcon#about to read 3, iclass 23, count 2 2006.225.07:40:40.37#ibcon#read 3, iclass 23, count 2 2006.225.07:40:40.37#ibcon#about to read 4, iclass 23, count 2 2006.225.07:40:40.37#ibcon#read 4, iclass 23, count 2 2006.225.07:40:40.37#ibcon#about to read 5, iclass 23, count 2 2006.225.07:40:40.37#ibcon#read 5, iclass 23, count 2 2006.225.07:40:40.37#ibcon#about to read 6, iclass 23, count 2 2006.225.07:40:40.37#ibcon#read 6, iclass 23, count 2 2006.225.07:40:40.37#ibcon#end of sib2, iclass 23, count 2 2006.225.07:40:40.37#ibcon#*after write, iclass 23, count 2 2006.225.07:40:40.37#ibcon#*before return 0, iclass 23, count 2 2006.225.07:40:40.37#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:40:40.37#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:40:40.37#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.225.07:40:40.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:40.37#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:40:40.49#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:40:40.49#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:40:40.49#ibcon#enter wrdev, iclass 23, count 0 2006.225.07:40:40.49#ibcon#first serial, iclass 23, count 0 2006.225.07:40:40.49#ibcon#enter sib2, iclass 23, count 0 2006.225.07:40:40.49#ibcon#flushed, iclass 23, count 0 2006.225.07:40:40.49#ibcon#about to write, iclass 23, count 0 2006.225.07:40:40.49#ibcon#wrote, iclass 23, count 0 2006.225.07:40:40.49#ibcon#about to read 3, iclass 23, count 0 2006.225.07:40:40.51#ibcon#read 3, iclass 23, count 0 2006.225.07:40:40.51#ibcon#about to read 4, iclass 23, count 0 2006.225.07:40:40.51#ibcon#read 4, iclass 23, count 0 2006.225.07:40:40.51#ibcon#about to read 5, iclass 23, count 0 2006.225.07:40:40.51#ibcon#read 5, iclass 23, count 0 2006.225.07:40:40.51#ibcon#about to read 6, iclass 23, count 0 2006.225.07:40:40.51#ibcon#read 6, iclass 23, count 0 2006.225.07:40:40.51#ibcon#end of sib2, iclass 23, count 0 2006.225.07:40:40.51#ibcon#*mode == 0, iclass 23, count 0 2006.225.07:40:40.51#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.07:40:40.51#ibcon#[25=USB\r\n] 2006.225.07:40:40.51#ibcon#*before write, iclass 23, count 0 2006.225.07:40:40.51#ibcon#enter sib2, iclass 23, count 0 2006.225.07:40:40.51#ibcon#flushed, iclass 23, count 0 2006.225.07:40:40.51#ibcon#about to write, iclass 23, count 0 2006.225.07:40:40.51#ibcon#wrote, iclass 23, count 0 2006.225.07:40:40.51#ibcon#about to read 3, iclass 23, count 0 2006.225.07:40:40.54#ibcon#read 3, iclass 23, count 0 2006.225.07:40:40.54#ibcon#about to read 4, iclass 23, count 0 2006.225.07:40:40.54#ibcon#read 4, iclass 23, count 0 2006.225.07:40:40.54#ibcon#about to read 5, iclass 23, count 0 2006.225.07:40:40.54#ibcon#read 5, iclass 23, count 0 2006.225.07:40:40.54#ibcon#about to read 6, iclass 23, count 0 2006.225.07:40:40.54#ibcon#read 6, iclass 23, count 0 2006.225.07:40:40.54#ibcon#end of sib2, iclass 23, count 0 2006.225.07:40:40.54#ibcon#*after write, iclass 23, count 0 2006.225.07:40:40.54#ibcon#*before return 0, iclass 23, count 0 2006.225.07:40:40.54#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:40:40.54#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:40:40.54#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.07:40:40.54#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.07:40:40.54$vc4f8/vblo=1,632.99 2006.225.07:40:40.54#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.225.07:40:40.54#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.225.07:40:40.54#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:40.54#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:40:40.54#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:40:40.54#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:40:40.54#ibcon#enter wrdev, iclass 25, count 0 2006.225.07:40:40.54#ibcon#first serial, iclass 25, count 0 2006.225.07:40:40.54#ibcon#enter sib2, iclass 25, count 0 2006.225.07:40:40.54#ibcon#flushed, iclass 25, count 0 2006.225.07:40:40.54#ibcon#about to write, iclass 25, count 0 2006.225.07:40:40.54#ibcon#wrote, iclass 25, count 0 2006.225.07:40:40.54#ibcon#about to read 3, iclass 25, count 0 2006.225.07:40:40.56#ibcon#read 3, iclass 25, count 0 2006.225.07:40:40.56#ibcon#about to read 4, iclass 25, count 0 2006.225.07:40:40.56#ibcon#read 4, iclass 25, count 0 2006.225.07:40:40.56#ibcon#about to read 5, iclass 25, count 0 2006.225.07:40:40.56#ibcon#read 5, iclass 25, count 0 2006.225.07:40:40.56#ibcon#about to read 6, iclass 25, count 0 2006.225.07:40:40.56#ibcon#read 6, iclass 25, count 0 2006.225.07:40:40.56#ibcon#end of sib2, iclass 25, count 0 2006.225.07:40:40.56#ibcon#*mode == 0, iclass 25, count 0 2006.225.07:40:40.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.07:40:40.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:40:40.56#ibcon#*before write, iclass 25, count 0 2006.225.07:40:40.56#ibcon#enter sib2, iclass 25, count 0 2006.225.07:40:40.56#ibcon#flushed, iclass 25, count 0 2006.225.07:40:40.56#ibcon#about to write, iclass 25, count 0 2006.225.07:40:40.56#ibcon#wrote, iclass 25, count 0 2006.225.07:40:40.56#ibcon#about to read 3, iclass 25, count 0 2006.225.07:40:40.60#ibcon#read 3, iclass 25, count 0 2006.225.07:40:40.60#ibcon#about to read 4, iclass 25, count 0 2006.225.07:40:40.60#ibcon#read 4, iclass 25, count 0 2006.225.07:40:40.60#ibcon#about to read 5, iclass 25, count 0 2006.225.07:40:40.60#ibcon#read 5, iclass 25, count 0 2006.225.07:40:40.60#ibcon#about to read 6, iclass 25, count 0 2006.225.07:40:40.60#ibcon#read 6, iclass 25, count 0 2006.225.07:40:40.60#ibcon#end of sib2, iclass 25, count 0 2006.225.07:40:40.60#ibcon#*after write, iclass 25, count 0 2006.225.07:40:40.60#ibcon#*before return 0, iclass 25, count 0 2006.225.07:40:40.60#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:40:40.60#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:40:40.60#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.07:40:40.60#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.07:40:40.60$vc4f8/vb=1,4 2006.225.07:40:40.60#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.225.07:40:40.60#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.225.07:40:40.60#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:40.60#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:40:40.60#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:40:40.60#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:40:40.60#ibcon#enter wrdev, iclass 27, count 2 2006.225.07:40:40.60#ibcon#first serial, iclass 27, count 2 2006.225.07:40:40.60#ibcon#enter sib2, iclass 27, count 2 2006.225.07:40:40.60#ibcon#flushed, iclass 27, count 2 2006.225.07:40:40.60#ibcon#about to write, iclass 27, count 2 2006.225.07:40:40.60#ibcon#wrote, iclass 27, count 2 2006.225.07:40:40.60#ibcon#about to read 3, iclass 27, count 2 2006.225.07:40:40.62#ibcon#read 3, iclass 27, count 2 2006.225.07:40:40.62#ibcon#about to read 4, iclass 27, count 2 2006.225.07:40:40.62#ibcon#read 4, iclass 27, count 2 2006.225.07:40:40.62#ibcon#about to read 5, iclass 27, count 2 2006.225.07:40:40.62#ibcon#read 5, iclass 27, count 2 2006.225.07:40:40.62#ibcon#about to read 6, iclass 27, count 2 2006.225.07:40:40.62#ibcon#read 6, iclass 27, count 2 2006.225.07:40:40.62#ibcon#end of sib2, iclass 27, count 2 2006.225.07:40:40.62#ibcon#*mode == 0, iclass 27, count 2 2006.225.07:40:40.62#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.225.07:40:40.62#ibcon#[27=AT01-04\r\n] 2006.225.07:40:40.62#ibcon#*before write, iclass 27, count 2 2006.225.07:40:40.62#ibcon#enter sib2, iclass 27, count 2 2006.225.07:40:40.62#ibcon#flushed, iclass 27, count 2 2006.225.07:40:40.62#ibcon#about to write, iclass 27, count 2 2006.225.07:40:40.62#ibcon#wrote, iclass 27, count 2 2006.225.07:40:40.62#ibcon#about to read 3, iclass 27, count 2 2006.225.07:40:40.65#ibcon#read 3, iclass 27, count 2 2006.225.07:40:40.65#ibcon#about to read 4, iclass 27, count 2 2006.225.07:40:40.65#ibcon#read 4, iclass 27, count 2 2006.225.07:40:40.65#ibcon#about to read 5, iclass 27, count 2 2006.225.07:40:40.65#ibcon#read 5, iclass 27, count 2 2006.225.07:40:40.65#ibcon#about to read 6, iclass 27, count 2 2006.225.07:40:40.65#ibcon#read 6, iclass 27, count 2 2006.225.07:40:40.65#ibcon#end of sib2, iclass 27, count 2 2006.225.07:40:40.65#ibcon#*after write, iclass 27, count 2 2006.225.07:40:40.65#ibcon#*before return 0, iclass 27, count 2 2006.225.07:40:40.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:40:40.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:40:40.65#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.225.07:40:40.65#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:40.65#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:40:40.77#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:40:40.77#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:40:40.77#ibcon#enter wrdev, iclass 27, count 0 2006.225.07:40:40.77#ibcon#first serial, iclass 27, count 0 2006.225.07:40:40.77#ibcon#enter sib2, iclass 27, count 0 2006.225.07:40:40.77#ibcon#flushed, iclass 27, count 0 2006.225.07:40:40.77#ibcon#about to write, iclass 27, count 0 2006.225.07:40:40.77#ibcon#wrote, iclass 27, count 0 2006.225.07:40:40.77#ibcon#about to read 3, iclass 27, count 0 2006.225.07:40:40.79#ibcon#read 3, iclass 27, count 0 2006.225.07:40:40.79#ibcon#about to read 4, iclass 27, count 0 2006.225.07:40:40.79#ibcon#read 4, iclass 27, count 0 2006.225.07:40:40.79#ibcon#about to read 5, iclass 27, count 0 2006.225.07:40:40.79#ibcon#read 5, iclass 27, count 0 2006.225.07:40:40.79#ibcon#about to read 6, iclass 27, count 0 2006.225.07:40:40.79#ibcon#read 6, iclass 27, count 0 2006.225.07:40:40.79#ibcon#end of sib2, iclass 27, count 0 2006.225.07:40:40.79#ibcon#*mode == 0, iclass 27, count 0 2006.225.07:40:40.79#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.07:40:40.79#ibcon#[27=USB\r\n] 2006.225.07:40:40.79#ibcon#*before write, iclass 27, count 0 2006.225.07:40:40.79#ibcon#enter sib2, iclass 27, count 0 2006.225.07:40:40.79#ibcon#flushed, iclass 27, count 0 2006.225.07:40:40.79#ibcon#about to write, iclass 27, count 0 2006.225.07:40:40.79#ibcon#wrote, iclass 27, count 0 2006.225.07:40:40.79#ibcon#about to read 3, iclass 27, count 0 2006.225.07:40:40.82#ibcon#read 3, iclass 27, count 0 2006.225.07:40:40.82#ibcon#about to read 4, iclass 27, count 0 2006.225.07:40:40.82#ibcon#read 4, iclass 27, count 0 2006.225.07:40:40.82#ibcon#about to read 5, iclass 27, count 0 2006.225.07:40:40.82#ibcon#read 5, iclass 27, count 0 2006.225.07:40:40.82#ibcon#about to read 6, iclass 27, count 0 2006.225.07:40:40.82#ibcon#read 6, iclass 27, count 0 2006.225.07:40:40.82#ibcon#end of sib2, iclass 27, count 0 2006.225.07:40:40.82#ibcon#*after write, iclass 27, count 0 2006.225.07:40:40.82#ibcon#*before return 0, iclass 27, count 0 2006.225.07:40:40.82#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:40:40.82#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:40:40.82#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.07:40:40.82#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.07:40:40.82$vc4f8/vblo=2,640.99 2006.225.07:40:40.82#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.07:40:40.82#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.07:40:40.82#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:40.82#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:40:40.82#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:40:40.82#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:40:40.82#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:40:40.82#ibcon#first serial, iclass 29, count 0 2006.225.07:40:40.82#ibcon#enter sib2, iclass 29, count 0 2006.225.07:40:40.82#ibcon#flushed, iclass 29, count 0 2006.225.07:40:40.82#ibcon#about to write, iclass 29, count 0 2006.225.07:40:40.82#ibcon#wrote, iclass 29, count 0 2006.225.07:40:40.82#ibcon#about to read 3, iclass 29, count 0 2006.225.07:40:40.84#ibcon#read 3, iclass 29, count 0 2006.225.07:40:40.84#ibcon#about to read 4, iclass 29, count 0 2006.225.07:40:40.84#ibcon#read 4, iclass 29, count 0 2006.225.07:40:40.84#ibcon#about to read 5, iclass 29, count 0 2006.225.07:40:40.84#ibcon#read 5, iclass 29, count 0 2006.225.07:40:40.84#ibcon#about to read 6, iclass 29, count 0 2006.225.07:40:40.84#ibcon#read 6, iclass 29, count 0 2006.225.07:40:40.84#ibcon#end of sib2, iclass 29, count 0 2006.225.07:40:40.84#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:40:40.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:40:40.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:40:40.84#ibcon#*before write, iclass 29, count 0 2006.225.07:40:40.84#ibcon#enter sib2, iclass 29, count 0 2006.225.07:40:40.84#ibcon#flushed, iclass 29, count 0 2006.225.07:40:40.84#ibcon#about to write, iclass 29, count 0 2006.225.07:40:40.84#ibcon#wrote, iclass 29, count 0 2006.225.07:40:40.84#ibcon#about to read 3, iclass 29, count 0 2006.225.07:40:40.88#ibcon#read 3, iclass 29, count 0 2006.225.07:40:40.88#ibcon#about to read 4, iclass 29, count 0 2006.225.07:40:40.88#ibcon#read 4, iclass 29, count 0 2006.225.07:40:40.88#ibcon#about to read 5, iclass 29, count 0 2006.225.07:40:40.88#ibcon#read 5, iclass 29, count 0 2006.225.07:40:40.88#ibcon#about to read 6, iclass 29, count 0 2006.225.07:40:40.88#ibcon#read 6, iclass 29, count 0 2006.225.07:40:40.88#ibcon#end of sib2, iclass 29, count 0 2006.225.07:40:40.88#ibcon#*after write, iclass 29, count 0 2006.225.07:40:40.88#ibcon#*before return 0, iclass 29, count 0 2006.225.07:40:40.88#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:40:40.88#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:40:40.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:40:40.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:40:40.88$vc4f8/vb=2,4 2006.225.07:40:40.88#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.07:40:40.88#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.07:40:40.88#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:40.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:40:40.94#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:40:40.94#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:40:40.94#ibcon#enter wrdev, iclass 31, count 2 2006.225.07:40:40.94#ibcon#first serial, iclass 31, count 2 2006.225.07:40:40.94#ibcon#enter sib2, iclass 31, count 2 2006.225.07:40:40.94#ibcon#flushed, iclass 31, count 2 2006.225.07:40:40.94#ibcon#about to write, iclass 31, count 2 2006.225.07:40:40.94#ibcon#wrote, iclass 31, count 2 2006.225.07:40:40.94#ibcon#about to read 3, iclass 31, count 2 2006.225.07:40:40.96#ibcon#read 3, iclass 31, count 2 2006.225.07:40:40.96#ibcon#about to read 4, iclass 31, count 2 2006.225.07:40:40.96#ibcon#read 4, iclass 31, count 2 2006.225.07:40:40.96#ibcon#about to read 5, iclass 31, count 2 2006.225.07:40:40.96#ibcon#read 5, iclass 31, count 2 2006.225.07:40:40.96#ibcon#about to read 6, iclass 31, count 2 2006.225.07:40:40.96#ibcon#read 6, iclass 31, count 2 2006.225.07:40:40.96#ibcon#end of sib2, iclass 31, count 2 2006.225.07:40:40.96#ibcon#*mode == 0, iclass 31, count 2 2006.225.07:40:40.96#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.07:40:40.96#ibcon#[27=AT02-04\r\n] 2006.225.07:40:40.96#ibcon#*before write, iclass 31, count 2 2006.225.07:40:40.96#ibcon#enter sib2, iclass 31, count 2 2006.225.07:40:40.96#ibcon#flushed, iclass 31, count 2 2006.225.07:40:40.96#ibcon#about to write, iclass 31, count 2 2006.225.07:40:40.96#ibcon#wrote, iclass 31, count 2 2006.225.07:40:40.96#ibcon#about to read 3, iclass 31, count 2 2006.225.07:40:40.99#ibcon#read 3, iclass 31, count 2 2006.225.07:40:40.99#ibcon#about to read 4, iclass 31, count 2 2006.225.07:40:40.99#ibcon#read 4, iclass 31, count 2 2006.225.07:40:40.99#ibcon#about to read 5, iclass 31, count 2 2006.225.07:40:40.99#ibcon#read 5, iclass 31, count 2 2006.225.07:40:40.99#ibcon#about to read 6, iclass 31, count 2 2006.225.07:40:40.99#ibcon#read 6, iclass 31, count 2 2006.225.07:40:40.99#ibcon#end of sib2, iclass 31, count 2 2006.225.07:40:40.99#ibcon#*after write, iclass 31, count 2 2006.225.07:40:40.99#ibcon#*before return 0, iclass 31, count 2 2006.225.07:40:40.99#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:40:40.99#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:40:40.99#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.07:40:40.99#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:40.99#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:40:41.11#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:40:41.11#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:40:41.11#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:40:41.11#ibcon#first serial, iclass 31, count 0 2006.225.07:40:41.11#ibcon#enter sib2, iclass 31, count 0 2006.225.07:40:41.11#ibcon#flushed, iclass 31, count 0 2006.225.07:40:41.11#ibcon#about to write, iclass 31, count 0 2006.225.07:40:41.11#ibcon#wrote, iclass 31, count 0 2006.225.07:40:41.11#ibcon#about to read 3, iclass 31, count 0 2006.225.07:40:41.13#ibcon#read 3, iclass 31, count 0 2006.225.07:40:41.13#ibcon#about to read 4, iclass 31, count 0 2006.225.07:40:41.13#ibcon#read 4, iclass 31, count 0 2006.225.07:40:41.13#ibcon#about to read 5, iclass 31, count 0 2006.225.07:40:41.13#ibcon#read 5, iclass 31, count 0 2006.225.07:40:41.13#ibcon#about to read 6, iclass 31, count 0 2006.225.07:40:41.13#ibcon#read 6, iclass 31, count 0 2006.225.07:40:41.13#ibcon#end of sib2, iclass 31, count 0 2006.225.07:40:41.13#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:40:41.13#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:40:41.13#ibcon#[27=USB\r\n] 2006.225.07:40:41.13#ibcon#*before write, iclass 31, count 0 2006.225.07:40:41.13#ibcon#enter sib2, iclass 31, count 0 2006.225.07:40:41.13#ibcon#flushed, iclass 31, count 0 2006.225.07:40:41.13#ibcon#about to write, iclass 31, count 0 2006.225.07:40:41.13#ibcon#wrote, iclass 31, count 0 2006.225.07:40:41.13#ibcon#about to read 3, iclass 31, count 0 2006.225.07:40:41.16#ibcon#read 3, iclass 31, count 0 2006.225.07:40:41.16#ibcon#about to read 4, iclass 31, count 0 2006.225.07:40:41.16#ibcon#read 4, iclass 31, count 0 2006.225.07:40:41.16#ibcon#about to read 5, iclass 31, count 0 2006.225.07:40:41.16#ibcon#read 5, iclass 31, count 0 2006.225.07:40:41.16#ibcon#about to read 6, iclass 31, count 0 2006.225.07:40:41.16#ibcon#read 6, iclass 31, count 0 2006.225.07:40:41.16#ibcon#end of sib2, iclass 31, count 0 2006.225.07:40:41.16#ibcon#*after write, iclass 31, count 0 2006.225.07:40:41.16#ibcon#*before return 0, iclass 31, count 0 2006.225.07:40:41.16#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:40:41.16#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:40:41.16#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:40:41.16#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:40:41.16$vc4f8/vblo=3,656.99 2006.225.07:40:41.16#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.07:40:41.16#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.07:40:41.16#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:41.16#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:40:41.16#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:40:41.16#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:40:41.16#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:40:41.16#ibcon#first serial, iclass 33, count 0 2006.225.07:40:41.16#ibcon#enter sib2, iclass 33, count 0 2006.225.07:40:41.16#ibcon#flushed, iclass 33, count 0 2006.225.07:40:41.16#ibcon#about to write, iclass 33, count 0 2006.225.07:40:41.16#ibcon#wrote, iclass 33, count 0 2006.225.07:40:41.16#ibcon#about to read 3, iclass 33, count 0 2006.225.07:40:41.18#ibcon#read 3, iclass 33, count 0 2006.225.07:40:41.18#ibcon#about to read 4, iclass 33, count 0 2006.225.07:40:41.18#ibcon#read 4, iclass 33, count 0 2006.225.07:40:41.18#ibcon#about to read 5, iclass 33, count 0 2006.225.07:40:41.18#ibcon#read 5, iclass 33, count 0 2006.225.07:40:41.18#ibcon#about to read 6, iclass 33, count 0 2006.225.07:40:41.18#ibcon#read 6, iclass 33, count 0 2006.225.07:40:41.18#ibcon#end of sib2, iclass 33, count 0 2006.225.07:40:41.18#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:40:41.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:40:41.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:40:41.18#ibcon#*before write, iclass 33, count 0 2006.225.07:40:41.18#ibcon#enter sib2, iclass 33, count 0 2006.225.07:40:41.18#ibcon#flushed, iclass 33, count 0 2006.225.07:40:41.18#ibcon#about to write, iclass 33, count 0 2006.225.07:40:41.18#ibcon#wrote, iclass 33, count 0 2006.225.07:40:41.18#ibcon#about to read 3, iclass 33, count 0 2006.225.07:40:41.22#ibcon#read 3, iclass 33, count 0 2006.225.07:40:41.22#ibcon#about to read 4, iclass 33, count 0 2006.225.07:40:41.22#ibcon#read 4, iclass 33, count 0 2006.225.07:40:41.22#ibcon#about to read 5, iclass 33, count 0 2006.225.07:40:41.22#ibcon#read 5, iclass 33, count 0 2006.225.07:40:41.22#ibcon#about to read 6, iclass 33, count 0 2006.225.07:40:41.22#ibcon#read 6, iclass 33, count 0 2006.225.07:40:41.22#ibcon#end of sib2, iclass 33, count 0 2006.225.07:40:41.22#ibcon#*after write, iclass 33, count 0 2006.225.07:40:41.22#ibcon#*before return 0, iclass 33, count 0 2006.225.07:40:41.22#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:40:41.22#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:40:41.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:40:41.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:40:41.22$vc4f8/vb=3,4 2006.225.07:40:41.22#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.07:40:41.22#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.07:40:41.22#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:41.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:40:41.28#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:40:41.28#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:40:41.28#ibcon#enter wrdev, iclass 35, count 2 2006.225.07:40:41.28#ibcon#first serial, iclass 35, count 2 2006.225.07:40:41.28#ibcon#enter sib2, iclass 35, count 2 2006.225.07:40:41.28#ibcon#flushed, iclass 35, count 2 2006.225.07:40:41.28#ibcon#about to write, iclass 35, count 2 2006.225.07:40:41.28#ibcon#wrote, iclass 35, count 2 2006.225.07:40:41.28#ibcon#about to read 3, iclass 35, count 2 2006.225.07:40:41.30#ibcon#read 3, iclass 35, count 2 2006.225.07:40:41.30#ibcon#about to read 4, iclass 35, count 2 2006.225.07:40:41.30#ibcon#read 4, iclass 35, count 2 2006.225.07:40:41.30#ibcon#about to read 5, iclass 35, count 2 2006.225.07:40:41.30#ibcon#read 5, iclass 35, count 2 2006.225.07:40:41.30#ibcon#about to read 6, iclass 35, count 2 2006.225.07:40:41.30#ibcon#read 6, iclass 35, count 2 2006.225.07:40:41.30#ibcon#end of sib2, iclass 35, count 2 2006.225.07:40:41.30#ibcon#*mode == 0, iclass 35, count 2 2006.225.07:40:41.30#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.07:40:41.30#ibcon#[27=AT03-04\r\n] 2006.225.07:40:41.30#ibcon#*before write, iclass 35, count 2 2006.225.07:40:41.30#ibcon#enter sib2, iclass 35, count 2 2006.225.07:40:41.30#ibcon#flushed, iclass 35, count 2 2006.225.07:40:41.30#ibcon#about to write, iclass 35, count 2 2006.225.07:40:41.30#ibcon#wrote, iclass 35, count 2 2006.225.07:40:41.30#ibcon#about to read 3, iclass 35, count 2 2006.225.07:40:41.33#ibcon#read 3, iclass 35, count 2 2006.225.07:40:41.33#ibcon#about to read 4, iclass 35, count 2 2006.225.07:40:41.33#ibcon#read 4, iclass 35, count 2 2006.225.07:40:41.33#ibcon#about to read 5, iclass 35, count 2 2006.225.07:40:41.33#ibcon#read 5, iclass 35, count 2 2006.225.07:40:41.33#ibcon#about to read 6, iclass 35, count 2 2006.225.07:40:41.33#ibcon#read 6, iclass 35, count 2 2006.225.07:40:41.33#ibcon#end of sib2, iclass 35, count 2 2006.225.07:40:41.33#ibcon#*after write, iclass 35, count 2 2006.225.07:40:41.33#ibcon#*before return 0, iclass 35, count 2 2006.225.07:40:41.33#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:40:41.33#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:40:41.33#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.07:40:41.33#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:41.33#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:40:41.45#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:40:41.45#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:40:41.45#ibcon#enter wrdev, iclass 35, count 0 2006.225.07:40:41.45#ibcon#first serial, iclass 35, count 0 2006.225.07:40:41.45#ibcon#enter sib2, iclass 35, count 0 2006.225.07:40:41.45#ibcon#flushed, iclass 35, count 0 2006.225.07:40:41.45#ibcon#about to write, iclass 35, count 0 2006.225.07:40:41.45#ibcon#wrote, iclass 35, count 0 2006.225.07:40:41.45#ibcon#about to read 3, iclass 35, count 0 2006.225.07:40:41.47#ibcon#read 3, iclass 35, count 0 2006.225.07:40:41.47#ibcon#about to read 4, iclass 35, count 0 2006.225.07:40:41.47#ibcon#read 4, iclass 35, count 0 2006.225.07:40:41.47#ibcon#about to read 5, iclass 35, count 0 2006.225.07:40:41.47#ibcon#read 5, iclass 35, count 0 2006.225.07:40:41.47#ibcon#about to read 6, iclass 35, count 0 2006.225.07:40:41.47#ibcon#read 6, iclass 35, count 0 2006.225.07:40:41.47#ibcon#end of sib2, iclass 35, count 0 2006.225.07:40:41.47#ibcon#*mode == 0, iclass 35, count 0 2006.225.07:40:41.47#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.07:40:41.47#ibcon#[27=USB\r\n] 2006.225.07:40:41.47#ibcon#*before write, iclass 35, count 0 2006.225.07:40:41.47#ibcon#enter sib2, iclass 35, count 0 2006.225.07:40:41.47#ibcon#flushed, iclass 35, count 0 2006.225.07:40:41.47#ibcon#about to write, iclass 35, count 0 2006.225.07:40:41.47#ibcon#wrote, iclass 35, count 0 2006.225.07:40:41.47#ibcon#about to read 3, iclass 35, count 0 2006.225.07:40:41.50#ibcon#read 3, iclass 35, count 0 2006.225.07:40:41.50#ibcon#about to read 4, iclass 35, count 0 2006.225.07:40:41.50#ibcon#read 4, iclass 35, count 0 2006.225.07:40:41.50#ibcon#about to read 5, iclass 35, count 0 2006.225.07:40:41.50#ibcon#read 5, iclass 35, count 0 2006.225.07:40:41.50#ibcon#about to read 6, iclass 35, count 0 2006.225.07:40:41.50#ibcon#read 6, iclass 35, count 0 2006.225.07:40:41.50#ibcon#end of sib2, iclass 35, count 0 2006.225.07:40:41.50#ibcon#*after write, iclass 35, count 0 2006.225.07:40:41.50#ibcon#*before return 0, iclass 35, count 0 2006.225.07:40:41.50#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:40:41.50#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:40:41.50#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.07:40:41.50#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.07:40:41.50$vc4f8/vblo=4,712.99 2006.225.07:40:41.50#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.07:40:41.50#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.07:40:41.50#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:41.50#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:40:41.50#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:40:41.50#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:40:41.50#ibcon#enter wrdev, iclass 37, count 0 2006.225.07:40:41.50#ibcon#first serial, iclass 37, count 0 2006.225.07:40:41.50#ibcon#enter sib2, iclass 37, count 0 2006.225.07:40:41.50#ibcon#flushed, iclass 37, count 0 2006.225.07:40:41.50#ibcon#about to write, iclass 37, count 0 2006.225.07:40:41.50#ibcon#wrote, iclass 37, count 0 2006.225.07:40:41.50#ibcon#about to read 3, iclass 37, count 0 2006.225.07:40:41.52#ibcon#read 3, iclass 37, count 0 2006.225.07:40:41.52#ibcon#about to read 4, iclass 37, count 0 2006.225.07:40:41.52#ibcon#read 4, iclass 37, count 0 2006.225.07:40:41.52#ibcon#about to read 5, iclass 37, count 0 2006.225.07:40:41.52#ibcon#read 5, iclass 37, count 0 2006.225.07:40:41.52#ibcon#about to read 6, iclass 37, count 0 2006.225.07:40:41.52#ibcon#read 6, iclass 37, count 0 2006.225.07:40:41.52#ibcon#end of sib2, iclass 37, count 0 2006.225.07:40:41.52#ibcon#*mode == 0, iclass 37, count 0 2006.225.07:40:41.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.07:40:41.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:40:41.52#ibcon#*before write, iclass 37, count 0 2006.225.07:40:41.52#ibcon#enter sib2, iclass 37, count 0 2006.225.07:40:41.52#ibcon#flushed, iclass 37, count 0 2006.225.07:40:41.52#ibcon#about to write, iclass 37, count 0 2006.225.07:40:41.52#ibcon#wrote, iclass 37, count 0 2006.225.07:40:41.52#ibcon#about to read 3, iclass 37, count 0 2006.225.07:40:41.56#ibcon#read 3, iclass 37, count 0 2006.225.07:40:41.56#ibcon#about to read 4, iclass 37, count 0 2006.225.07:40:41.56#ibcon#read 4, iclass 37, count 0 2006.225.07:40:41.56#ibcon#about to read 5, iclass 37, count 0 2006.225.07:40:41.56#ibcon#read 5, iclass 37, count 0 2006.225.07:40:41.56#ibcon#about to read 6, iclass 37, count 0 2006.225.07:40:41.56#ibcon#read 6, iclass 37, count 0 2006.225.07:40:41.56#ibcon#end of sib2, iclass 37, count 0 2006.225.07:40:41.56#ibcon#*after write, iclass 37, count 0 2006.225.07:40:41.56#ibcon#*before return 0, iclass 37, count 0 2006.225.07:40:41.56#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:40:41.56#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:40:41.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.07:40:41.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.07:40:41.56$vc4f8/vb=4,4 2006.225.07:40:41.56#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.07:40:41.56#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.07:40:41.56#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:41.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:40:41.62#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:40:41.62#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:40:41.62#ibcon#enter wrdev, iclass 39, count 2 2006.225.07:40:41.62#ibcon#first serial, iclass 39, count 2 2006.225.07:40:41.62#ibcon#enter sib2, iclass 39, count 2 2006.225.07:40:41.62#ibcon#flushed, iclass 39, count 2 2006.225.07:40:41.62#ibcon#about to write, iclass 39, count 2 2006.225.07:40:41.62#ibcon#wrote, iclass 39, count 2 2006.225.07:40:41.62#ibcon#about to read 3, iclass 39, count 2 2006.225.07:40:41.64#ibcon#read 3, iclass 39, count 2 2006.225.07:40:41.64#ibcon#about to read 4, iclass 39, count 2 2006.225.07:40:41.64#ibcon#read 4, iclass 39, count 2 2006.225.07:40:41.64#ibcon#about to read 5, iclass 39, count 2 2006.225.07:40:41.64#ibcon#read 5, iclass 39, count 2 2006.225.07:40:41.64#ibcon#about to read 6, iclass 39, count 2 2006.225.07:40:41.64#ibcon#read 6, iclass 39, count 2 2006.225.07:40:41.64#ibcon#end of sib2, iclass 39, count 2 2006.225.07:40:41.64#ibcon#*mode == 0, iclass 39, count 2 2006.225.07:40:41.64#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.07:40:41.64#ibcon#[27=AT04-04\r\n] 2006.225.07:40:41.64#ibcon#*before write, iclass 39, count 2 2006.225.07:40:41.64#ibcon#enter sib2, iclass 39, count 2 2006.225.07:40:41.64#ibcon#flushed, iclass 39, count 2 2006.225.07:40:41.64#ibcon#about to write, iclass 39, count 2 2006.225.07:40:41.64#ibcon#wrote, iclass 39, count 2 2006.225.07:40:41.64#ibcon#about to read 3, iclass 39, count 2 2006.225.07:40:41.67#ibcon#read 3, iclass 39, count 2 2006.225.07:40:41.67#ibcon#about to read 4, iclass 39, count 2 2006.225.07:40:41.67#ibcon#read 4, iclass 39, count 2 2006.225.07:40:41.67#ibcon#about to read 5, iclass 39, count 2 2006.225.07:40:41.67#ibcon#read 5, iclass 39, count 2 2006.225.07:40:41.67#ibcon#about to read 6, iclass 39, count 2 2006.225.07:40:41.67#ibcon#read 6, iclass 39, count 2 2006.225.07:40:41.67#ibcon#end of sib2, iclass 39, count 2 2006.225.07:40:41.67#ibcon#*after write, iclass 39, count 2 2006.225.07:40:41.67#ibcon#*before return 0, iclass 39, count 2 2006.225.07:40:41.67#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:40:41.67#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:40:41.67#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.07:40:41.67#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:41.67#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:40:41.79#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:40:41.79#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:40:41.79#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:40:41.79#ibcon#first serial, iclass 39, count 0 2006.225.07:40:41.79#ibcon#enter sib2, iclass 39, count 0 2006.225.07:40:41.79#ibcon#flushed, iclass 39, count 0 2006.225.07:40:41.79#ibcon#about to write, iclass 39, count 0 2006.225.07:40:41.79#ibcon#wrote, iclass 39, count 0 2006.225.07:40:41.79#ibcon#about to read 3, iclass 39, count 0 2006.225.07:40:41.81#ibcon#read 3, iclass 39, count 0 2006.225.07:40:41.81#ibcon#about to read 4, iclass 39, count 0 2006.225.07:40:41.81#ibcon#read 4, iclass 39, count 0 2006.225.07:40:41.81#ibcon#about to read 5, iclass 39, count 0 2006.225.07:40:41.81#ibcon#read 5, iclass 39, count 0 2006.225.07:40:41.81#ibcon#about to read 6, iclass 39, count 0 2006.225.07:40:41.81#ibcon#read 6, iclass 39, count 0 2006.225.07:40:41.81#ibcon#end of sib2, iclass 39, count 0 2006.225.07:40:41.81#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:40:41.81#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:40:41.81#ibcon#[27=USB\r\n] 2006.225.07:40:41.81#ibcon#*before write, iclass 39, count 0 2006.225.07:40:41.81#ibcon#enter sib2, iclass 39, count 0 2006.225.07:40:41.81#ibcon#flushed, iclass 39, count 0 2006.225.07:40:41.81#ibcon#about to write, iclass 39, count 0 2006.225.07:40:41.81#ibcon#wrote, iclass 39, count 0 2006.225.07:40:41.81#ibcon#about to read 3, iclass 39, count 0 2006.225.07:40:41.84#ibcon#read 3, iclass 39, count 0 2006.225.07:40:41.84#ibcon#about to read 4, iclass 39, count 0 2006.225.07:40:41.84#ibcon#read 4, iclass 39, count 0 2006.225.07:40:41.84#ibcon#about to read 5, iclass 39, count 0 2006.225.07:40:41.84#ibcon#read 5, iclass 39, count 0 2006.225.07:40:41.84#ibcon#about to read 6, iclass 39, count 0 2006.225.07:40:41.84#ibcon#read 6, iclass 39, count 0 2006.225.07:40:41.84#ibcon#end of sib2, iclass 39, count 0 2006.225.07:40:41.84#ibcon#*after write, iclass 39, count 0 2006.225.07:40:41.84#ibcon#*before return 0, iclass 39, count 0 2006.225.07:40:41.84#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:40:41.84#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:40:41.84#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:40:41.84#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:40:41.84$vc4f8/vblo=5,744.99 2006.225.07:40:41.84#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.07:40:41.84#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.07:40:41.84#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:41.84#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:40:41.84#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:40:41.84#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:40:41.84#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:40:41.84#ibcon#first serial, iclass 3, count 0 2006.225.07:40:41.84#ibcon#enter sib2, iclass 3, count 0 2006.225.07:40:41.84#ibcon#flushed, iclass 3, count 0 2006.225.07:40:41.84#ibcon#about to write, iclass 3, count 0 2006.225.07:40:41.84#ibcon#wrote, iclass 3, count 0 2006.225.07:40:41.84#ibcon#about to read 3, iclass 3, count 0 2006.225.07:40:41.86#ibcon#read 3, iclass 3, count 0 2006.225.07:40:41.86#ibcon#about to read 4, iclass 3, count 0 2006.225.07:40:41.86#ibcon#read 4, iclass 3, count 0 2006.225.07:40:41.86#ibcon#about to read 5, iclass 3, count 0 2006.225.07:40:41.86#ibcon#read 5, iclass 3, count 0 2006.225.07:40:41.86#ibcon#about to read 6, iclass 3, count 0 2006.225.07:40:41.86#ibcon#read 6, iclass 3, count 0 2006.225.07:40:41.86#ibcon#end of sib2, iclass 3, count 0 2006.225.07:40:41.86#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:40:41.86#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:40:41.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:40:41.86#ibcon#*before write, iclass 3, count 0 2006.225.07:40:41.86#ibcon#enter sib2, iclass 3, count 0 2006.225.07:40:41.86#ibcon#flushed, iclass 3, count 0 2006.225.07:40:41.86#ibcon#about to write, iclass 3, count 0 2006.225.07:40:41.86#ibcon#wrote, iclass 3, count 0 2006.225.07:40:41.86#ibcon#about to read 3, iclass 3, count 0 2006.225.07:40:41.90#ibcon#read 3, iclass 3, count 0 2006.225.07:40:41.90#ibcon#about to read 4, iclass 3, count 0 2006.225.07:40:41.90#ibcon#read 4, iclass 3, count 0 2006.225.07:40:41.90#ibcon#about to read 5, iclass 3, count 0 2006.225.07:40:41.90#ibcon#read 5, iclass 3, count 0 2006.225.07:40:41.90#ibcon#about to read 6, iclass 3, count 0 2006.225.07:40:41.90#ibcon#read 6, iclass 3, count 0 2006.225.07:40:41.90#ibcon#end of sib2, iclass 3, count 0 2006.225.07:40:41.90#ibcon#*after write, iclass 3, count 0 2006.225.07:40:41.90#ibcon#*before return 0, iclass 3, count 0 2006.225.07:40:41.90#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:40:41.90#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:40:41.90#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:40:41.90#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:40:41.90$vc4f8/vb=5,4 2006.225.07:40:41.90#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.07:40:41.90#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.07:40:41.90#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:41.90#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:40:41.96#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:40:41.96#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:40:41.96#ibcon#enter wrdev, iclass 5, count 2 2006.225.07:40:41.96#ibcon#first serial, iclass 5, count 2 2006.225.07:40:41.96#ibcon#enter sib2, iclass 5, count 2 2006.225.07:40:41.96#ibcon#flushed, iclass 5, count 2 2006.225.07:40:41.96#ibcon#about to write, iclass 5, count 2 2006.225.07:40:41.96#ibcon#wrote, iclass 5, count 2 2006.225.07:40:41.96#ibcon#about to read 3, iclass 5, count 2 2006.225.07:40:41.98#ibcon#read 3, iclass 5, count 2 2006.225.07:40:41.98#ibcon#about to read 4, iclass 5, count 2 2006.225.07:40:41.98#ibcon#read 4, iclass 5, count 2 2006.225.07:40:41.98#ibcon#about to read 5, iclass 5, count 2 2006.225.07:40:41.98#ibcon#read 5, iclass 5, count 2 2006.225.07:40:41.98#ibcon#about to read 6, iclass 5, count 2 2006.225.07:40:41.98#ibcon#read 6, iclass 5, count 2 2006.225.07:40:41.98#ibcon#end of sib2, iclass 5, count 2 2006.225.07:40:41.98#ibcon#*mode == 0, iclass 5, count 2 2006.225.07:40:41.98#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.07:40:41.98#ibcon#[27=AT05-04\r\n] 2006.225.07:40:41.98#ibcon#*before write, iclass 5, count 2 2006.225.07:40:41.98#ibcon#enter sib2, iclass 5, count 2 2006.225.07:40:41.98#ibcon#flushed, iclass 5, count 2 2006.225.07:40:41.98#ibcon#about to write, iclass 5, count 2 2006.225.07:40:41.98#ibcon#wrote, iclass 5, count 2 2006.225.07:40:41.98#ibcon#about to read 3, iclass 5, count 2 2006.225.07:40:42.01#ibcon#read 3, iclass 5, count 2 2006.225.07:40:42.01#ibcon#about to read 4, iclass 5, count 2 2006.225.07:40:42.01#ibcon#read 4, iclass 5, count 2 2006.225.07:40:42.01#ibcon#about to read 5, iclass 5, count 2 2006.225.07:40:42.01#ibcon#read 5, iclass 5, count 2 2006.225.07:40:42.01#ibcon#about to read 6, iclass 5, count 2 2006.225.07:40:42.01#ibcon#read 6, iclass 5, count 2 2006.225.07:40:42.01#ibcon#end of sib2, iclass 5, count 2 2006.225.07:40:42.01#ibcon#*after write, iclass 5, count 2 2006.225.07:40:42.01#ibcon#*before return 0, iclass 5, count 2 2006.225.07:40:42.01#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:40:42.01#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:40:42.01#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.07:40:42.01#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:42.01#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:40:42.13#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:40:42.13#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:40:42.13#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:40:42.13#ibcon#first serial, iclass 5, count 0 2006.225.07:40:42.13#ibcon#enter sib2, iclass 5, count 0 2006.225.07:40:42.13#ibcon#flushed, iclass 5, count 0 2006.225.07:40:42.13#ibcon#about to write, iclass 5, count 0 2006.225.07:40:42.13#ibcon#wrote, iclass 5, count 0 2006.225.07:40:42.13#ibcon#about to read 3, iclass 5, count 0 2006.225.07:40:42.15#ibcon#read 3, iclass 5, count 0 2006.225.07:40:42.15#ibcon#about to read 4, iclass 5, count 0 2006.225.07:40:42.15#ibcon#read 4, iclass 5, count 0 2006.225.07:40:42.15#ibcon#about to read 5, iclass 5, count 0 2006.225.07:40:42.15#ibcon#read 5, iclass 5, count 0 2006.225.07:40:42.15#ibcon#about to read 6, iclass 5, count 0 2006.225.07:40:42.15#ibcon#read 6, iclass 5, count 0 2006.225.07:40:42.15#ibcon#end of sib2, iclass 5, count 0 2006.225.07:40:42.15#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:40:42.15#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:40:42.15#ibcon#[27=USB\r\n] 2006.225.07:40:42.15#ibcon#*before write, iclass 5, count 0 2006.225.07:40:42.15#ibcon#enter sib2, iclass 5, count 0 2006.225.07:40:42.15#ibcon#flushed, iclass 5, count 0 2006.225.07:40:42.15#ibcon#about to write, iclass 5, count 0 2006.225.07:40:42.15#ibcon#wrote, iclass 5, count 0 2006.225.07:40:42.15#ibcon#about to read 3, iclass 5, count 0 2006.225.07:40:42.18#ibcon#read 3, iclass 5, count 0 2006.225.07:40:42.18#ibcon#about to read 4, iclass 5, count 0 2006.225.07:40:42.18#ibcon#read 4, iclass 5, count 0 2006.225.07:40:42.18#ibcon#about to read 5, iclass 5, count 0 2006.225.07:40:42.18#ibcon#read 5, iclass 5, count 0 2006.225.07:40:42.18#ibcon#about to read 6, iclass 5, count 0 2006.225.07:40:42.18#ibcon#read 6, iclass 5, count 0 2006.225.07:40:42.18#ibcon#end of sib2, iclass 5, count 0 2006.225.07:40:42.18#ibcon#*after write, iclass 5, count 0 2006.225.07:40:42.18#ibcon#*before return 0, iclass 5, count 0 2006.225.07:40:42.18#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:40:42.18#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:40:42.18#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:40:42.18#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:40:42.18$vc4f8/vblo=6,752.99 2006.225.07:40:42.18#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.225.07:40:42.18#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.225.07:40:42.18#ibcon#ireg 17 cls_cnt 0 2006.225.07:40:42.18#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:40:42.18#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:40:42.18#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:40:42.18#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:40:42.18#ibcon#first serial, iclass 7, count 0 2006.225.07:40:42.18#ibcon#enter sib2, iclass 7, count 0 2006.225.07:40:42.18#ibcon#flushed, iclass 7, count 0 2006.225.07:40:42.18#ibcon#about to write, iclass 7, count 0 2006.225.07:40:42.18#ibcon#wrote, iclass 7, count 0 2006.225.07:40:42.18#ibcon#about to read 3, iclass 7, count 0 2006.225.07:40:42.20#ibcon#read 3, iclass 7, count 0 2006.225.07:40:42.20#ibcon#about to read 4, iclass 7, count 0 2006.225.07:40:42.20#ibcon#read 4, iclass 7, count 0 2006.225.07:40:42.20#ibcon#about to read 5, iclass 7, count 0 2006.225.07:40:42.20#ibcon#read 5, iclass 7, count 0 2006.225.07:40:42.20#ibcon#about to read 6, iclass 7, count 0 2006.225.07:40:42.20#ibcon#read 6, iclass 7, count 0 2006.225.07:40:42.20#ibcon#end of sib2, iclass 7, count 0 2006.225.07:40:42.20#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:40:42.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:40:42.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:40:42.20#ibcon#*before write, iclass 7, count 0 2006.225.07:40:42.20#ibcon#enter sib2, iclass 7, count 0 2006.225.07:40:42.20#ibcon#flushed, iclass 7, count 0 2006.225.07:40:42.20#ibcon#about to write, iclass 7, count 0 2006.225.07:40:42.20#ibcon#wrote, iclass 7, count 0 2006.225.07:40:42.20#ibcon#about to read 3, iclass 7, count 0 2006.225.07:40:42.24#ibcon#read 3, iclass 7, count 0 2006.225.07:40:42.24#ibcon#about to read 4, iclass 7, count 0 2006.225.07:40:42.24#ibcon#read 4, iclass 7, count 0 2006.225.07:40:42.24#ibcon#about to read 5, iclass 7, count 0 2006.225.07:40:42.24#ibcon#read 5, iclass 7, count 0 2006.225.07:40:42.24#ibcon#about to read 6, iclass 7, count 0 2006.225.07:40:42.24#ibcon#read 6, iclass 7, count 0 2006.225.07:40:42.24#ibcon#end of sib2, iclass 7, count 0 2006.225.07:40:42.24#ibcon#*after write, iclass 7, count 0 2006.225.07:40:42.24#ibcon#*before return 0, iclass 7, count 0 2006.225.07:40:42.24#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:40:42.24#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:40:42.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:40:42.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:40:42.24$vc4f8/vb=6,4 2006.225.07:40:42.24#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.225.07:40:42.24#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.225.07:40:42.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:40:42.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:40:42.30#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:40:42.30#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:40:42.30#ibcon#enter wrdev, iclass 11, count 2 2006.225.07:40:42.30#ibcon#first serial, iclass 11, count 2 2006.225.07:40:42.30#ibcon#enter sib2, iclass 11, count 2 2006.225.07:40:42.30#ibcon#flushed, iclass 11, count 2 2006.225.07:40:42.30#ibcon#about to write, iclass 11, count 2 2006.225.07:40:42.30#ibcon#wrote, iclass 11, count 2 2006.225.07:40:42.30#ibcon#about to read 3, iclass 11, count 2 2006.225.07:40:42.32#ibcon#read 3, iclass 11, count 2 2006.225.07:40:42.32#ibcon#about to read 4, iclass 11, count 2 2006.225.07:40:42.32#ibcon#read 4, iclass 11, count 2 2006.225.07:40:42.32#ibcon#about to read 5, iclass 11, count 2 2006.225.07:40:42.32#ibcon#read 5, iclass 11, count 2 2006.225.07:40:42.32#ibcon#about to read 6, iclass 11, count 2 2006.225.07:40:42.32#ibcon#read 6, iclass 11, count 2 2006.225.07:40:42.32#ibcon#end of sib2, iclass 11, count 2 2006.225.07:40:42.32#ibcon#*mode == 0, iclass 11, count 2 2006.225.07:40:42.32#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.225.07:40:42.32#ibcon#[27=AT06-04\r\n] 2006.225.07:40:42.32#ibcon#*before write, iclass 11, count 2 2006.225.07:40:42.32#ibcon#enter sib2, iclass 11, count 2 2006.225.07:40:42.32#ibcon#flushed, iclass 11, count 2 2006.225.07:40:42.32#ibcon#about to write, iclass 11, count 2 2006.225.07:40:42.32#ibcon#wrote, iclass 11, count 2 2006.225.07:40:42.32#ibcon#about to read 3, iclass 11, count 2 2006.225.07:40:42.35#ibcon#read 3, iclass 11, count 2 2006.225.07:40:42.35#ibcon#about to read 4, iclass 11, count 2 2006.225.07:40:42.35#ibcon#read 4, iclass 11, count 2 2006.225.07:40:42.35#ibcon#about to read 5, iclass 11, count 2 2006.225.07:40:42.35#ibcon#read 5, iclass 11, count 2 2006.225.07:40:42.35#ibcon#about to read 6, iclass 11, count 2 2006.225.07:40:42.35#ibcon#read 6, iclass 11, count 2 2006.225.07:40:42.35#ibcon#end of sib2, iclass 11, count 2 2006.225.07:40:42.35#ibcon#*after write, iclass 11, count 2 2006.225.07:40:42.35#ibcon#*before return 0, iclass 11, count 2 2006.225.07:40:42.35#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:40:42.35#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:40:42.35#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.225.07:40:42.35#ibcon#ireg 7 cls_cnt 0 2006.225.07:40:42.35#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:40:42.47#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:40:42.47#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:40:42.47#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:40:42.47#ibcon#first serial, iclass 11, count 0 2006.225.07:40:42.47#ibcon#enter sib2, iclass 11, count 0 2006.225.07:40:42.47#ibcon#flushed, iclass 11, count 0 2006.225.07:40:42.47#ibcon#about to write, iclass 11, count 0 2006.225.07:40:42.47#ibcon#wrote, iclass 11, count 0 2006.225.07:40:42.47#ibcon#about to read 3, iclass 11, count 0 2006.225.07:40:42.49#ibcon#read 3, iclass 11, count 0 2006.225.07:40:42.49#ibcon#about to read 4, iclass 11, count 0 2006.225.07:40:42.49#ibcon#read 4, iclass 11, count 0 2006.225.07:40:42.49#ibcon#about to read 5, iclass 11, count 0 2006.225.07:40:42.49#ibcon#read 5, iclass 11, count 0 2006.225.07:40:42.49#ibcon#about to read 6, iclass 11, count 0 2006.225.07:40:42.49#ibcon#read 6, iclass 11, count 0 2006.225.07:40:42.49#ibcon#end of sib2, iclass 11, count 0 2006.225.07:40:42.49#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:40:42.49#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:40:42.49#ibcon#[27=USB\r\n] 2006.225.07:40:42.49#ibcon#*before write, iclass 11, count 0 2006.225.07:40:42.49#ibcon#enter sib2, iclass 11, count 0 2006.225.07:40:42.49#ibcon#flushed, iclass 11, count 0 2006.225.07:40:42.49#ibcon#about to write, iclass 11, count 0 2006.225.07:40:42.49#ibcon#wrote, iclass 11, count 0 2006.225.07:40:42.49#ibcon#about to read 3, iclass 11, count 0 2006.225.07:40:42.52#ibcon#read 3, iclass 11, count 0 2006.225.07:40:42.52#ibcon#about to read 4, iclass 11, count 0 2006.225.07:40:42.52#ibcon#read 4, iclass 11, count 0 2006.225.07:40:42.52#ibcon#about to read 5, iclass 11, count 0 2006.225.07:40:42.52#ibcon#read 5, iclass 11, count 0 2006.225.07:40:42.52#ibcon#about to read 6, iclass 11, count 0 2006.225.07:40:42.52#ibcon#read 6, iclass 11, count 0 2006.225.07:40:42.52#ibcon#end of sib2, iclass 11, count 0 2006.225.07:40:42.52#ibcon#*after write, iclass 11, count 0 2006.225.07:40:42.52#ibcon#*before return 0, iclass 11, count 0 2006.225.07:40:42.52#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:40:42.52#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:40:42.52#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:40:42.52#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:40:42.52$vc4f8/vabw=wide 2006.225.07:40:42.52#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.07:40:42.52#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.07:40:42.52#ibcon#ireg 8 cls_cnt 0 2006.225.07:40:42.52#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:40:42.52#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:40:42.52#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:40:42.52#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:40:42.52#ibcon#first serial, iclass 13, count 0 2006.225.07:40:42.52#ibcon#enter sib2, iclass 13, count 0 2006.225.07:40:42.52#ibcon#flushed, iclass 13, count 0 2006.225.07:40:42.52#ibcon#about to write, iclass 13, count 0 2006.225.07:40:42.52#ibcon#wrote, iclass 13, count 0 2006.225.07:40:42.52#ibcon#about to read 3, iclass 13, count 0 2006.225.07:40:42.55#ibcon#read 3, iclass 13, count 0 2006.225.07:40:42.55#ibcon#about to read 4, iclass 13, count 0 2006.225.07:40:42.55#ibcon#read 4, iclass 13, count 0 2006.225.07:40:42.55#ibcon#about to read 5, iclass 13, count 0 2006.225.07:40:42.55#ibcon#read 5, iclass 13, count 0 2006.225.07:40:42.55#ibcon#about to read 6, iclass 13, count 0 2006.225.07:40:42.55#ibcon#read 6, iclass 13, count 0 2006.225.07:40:42.55#ibcon#end of sib2, iclass 13, count 0 2006.225.07:40:42.55#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:40:42.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:40:42.55#ibcon#[25=BW32\r\n] 2006.225.07:40:42.55#ibcon#*before write, iclass 13, count 0 2006.225.07:40:42.55#ibcon#enter sib2, iclass 13, count 0 2006.225.07:40:42.55#ibcon#flushed, iclass 13, count 0 2006.225.07:40:42.55#ibcon#about to write, iclass 13, count 0 2006.225.07:40:42.55#ibcon#wrote, iclass 13, count 0 2006.225.07:40:42.55#ibcon#about to read 3, iclass 13, count 0 2006.225.07:40:42.58#ibcon#read 3, iclass 13, count 0 2006.225.07:40:42.58#ibcon#about to read 4, iclass 13, count 0 2006.225.07:40:42.58#ibcon#read 4, iclass 13, count 0 2006.225.07:40:42.58#ibcon#about to read 5, iclass 13, count 0 2006.225.07:40:42.58#ibcon#read 5, iclass 13, count 0 2006.225.07:40:42.58#ibcon#about to read 6, iclass 13, count 0 2006.225.07:40:42.58#ibcon#read 6, iclass 13, count 0 2006.225.07:40:42.58#ibcon#end of sib2, iclass 13, count 0 2006.225.07:40:42.58#ibcon#*after write, iclass 13, count 0 2006.225.07:40:42.58#ibcon#*before return 0, iclass 13, count 0 2006.225.07:40:42.58#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:40:42.58#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:40:42.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:40:42.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:40:42.58$vc4f8/vbbw=wide 2006.225.07:40:42.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.07:40:42.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.07:40:42.58#ibcon#ireg 8 cls_cnt 0 2006.225.07:40:42.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:40:42.64#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:40:42.64#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:40:42.64#ibcon#enter wrdev, iclass 15, count 0 2006.225.07:40:42.64#ibcon#first serial, iclass 15, count 0 2006.225.07:40:42.64#ibcon#enter sib2, iclass 15, count 0 2006.225.07:40:42.64#ibcon#flushed, iclass 15, count 0 2006.225.07:40:42.64#ibcon#about to write, iclass 15, count 0 2006.225.07:40:42.64#ibcon#wrote, iclass 15, count 0 2006.225.07:40:42.64#ibcon#about to read 3, iclass 15, count 0 2006.225.07:40:42.66#ibcon#read 3, iclass 15, count 0 2006.225.07:40:42.66#ibcon#about to read 4, iclass 15, count 0 2006.225.07:40:42.66#ibcon#read 4, iclass 15, count 0 2006.225.07:40:42.66#ibcon#about to read 5, iclass 15, count 0 2006.225.07:40:42.66#ibcon#read 5, iclass 15, count 0 2006.225.07:40:42.66#ibcon#about to read 6, iclass 15, count 0 2006.225.07:40:42.66#ibcon#read 6, iclass 15, count 0 2006.225.07:40:42.66#ibcon#end of sib2, iclass 15, count 0 2006.225.07:40:42.66#ibcon#*mode == 0, iclass 15, count 0 2006.225.07:40:42.66#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.07:40:42.66#ibcon#[27=BW32\r\n] 2006.225.07:40:42.66#ibcon#*before write, iclass 15, count 0 2006.225.07:40:42.66#ibcon#enter sib2, iclass 15, count 0 2006.225.07:40:42.66#ibcon#flushed, iclass 15, count 0 2006.225.07:40:42.66#ibcon#about to write, iclass 15, count 0 2006.225.07:40:42.66#ibcon#wrote, iclass 15, count 0 2006.225.07:40:42.66#ibcon#about to read 3, iclass 15, count 0 2006.225.07:40:42.69#ibcon#read 3, iclass 15, count 0 2006.225.07:40:42.69#ibcon#about to read 4, iclass 15, count 0 2006.225.07:40:42.69#ibcon#read 4, iclass 15, count 0 2006.225.07:40:42.69#ibcon#about to read 5, iclass 15, count 0 2006.225.07:40:42.69#ibcon#read 5, iclass 15, count 0 2006.225.07:40:42.69#ibcon#about to read 6, iclass 15, count 0 2006.225.07:40:42.69#ibcon#read 6, iclass 15, count 0 2006.225.07:40:42.69#ibcon#end of sib2, iclass 15, count 0 2006.225.07:40:42.69#ibcon#*after write, iclass 15, count 0 2006.225.07:40:42.69#ibcon#*before return 0, iclass 15, count 0 2006.225.07:40:42.69#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:40:42.69#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:40:42.69#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.07:40:42.69#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.07:40:42.69$4f8m12a/ifd4f 2006.225.07:40:42.69$ifd4f/lo= 2006.225.07:40:42.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:40:42.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:40:42.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:40:42.69$ifd4f/patch= 2006.225.07:40:42.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:40:42.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:40:42.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:40:42.69$4f8m12a/"form=m,16.000,1:2 2006.225.07:40:42.69$4f8m12a/"tpicd 2006.225.07:40:42.69$4f8m12a/echo=off 2006.225.07:40:42.69$4f8m12a/xlog=off 2006.225.07:40:42.69:!2006.225.07:41:30 2006.225.07:41:04.14#trakl#Source acquired 2006.225.07:41:06.14#flagr#flagr/antenna,acquired 2006.225.07:41:30.00:preob 2006.225.07:41:31.14/onsource/TRACKING 2006.225.07:41:31.14:!2006.225.07:41:40 2006.225.07:41:40.00:data_valid=on 2006.225.07:41:40.00:midob 2006.225.07:41:40.14/onsource/TRACKING 2006.225.07:41:40.14/wx/27.95,1003.2,69 2006.225.07:41:40.23/cable/+6.4040E-03 2006.225.07:41:41.32/va/01,08,usb,yes,28,29 2006.225.07:41:41.32/va/02,07,usb,yes,28,29 2006.225.07:41:41.32/va/03,06,usb,yes,30,30 2006.225.07:41:41.32/va/04,07,usb,yes,29,32 2006.225.07:41:41.32/va/05,07,usb,yes,32,34 2006.225.07:41:41.32/va/06,06,usb,yes,33,32 2006.225.07:41:41.32/va/07,06,usb,yes,32,32 2006.225.07:41:41.32/va/08,07,usb,yes,30,29 2006.225.07:41:41.55/valo/01,532.99,yes,locked 2006.225.07:41:41.55/valo/02,572.99,yes,locked 2006.225.07:41:41.55/valo/03,672.99,yes,locked 2006.225.07:41:41.55/valo/04,832.99,yes,locked 2006.225.07:41:41.55/valo/05,652.99,yes,locked 2006.225.07:41:41.55/valo/06,772.99,yes,locked 2006.225.07:41:41.55/valo/07,832.99,yes,locked 2006.225.07:41:41.55/valo/08,852.99,yes,locked 2006.225.07:41:42.64/vb/01,04,usb,yes,30,29 2006.225.07:41:42.64/vb/02,04,usb,yes,32,33 2006.225.07:41:42.64/vb/03,04,usb,yes,28,32 2006.225.07:41:42.64/vb/04,04,usb,yes,29,29 2006.225.07:41:42.64/vb/05,04,usb,yes,28,32 2006.225.07:41:42.64/vb/06,04,usb,yes,28,31 2006.225.07:41:42.64/vb/07,04,usb,yes,31,31 2006.225.07:41:42.64/vb/08,04,usb,yes,28,32 2006.225.07:41:42.88/vblo/01,632.99,yes,locked 2006.225.07:41:42.88/vblo/02,640.99,yes,locked 2006.225.07:41:42.88/vblo/03,656.99,yes,locked 2006.225.07:41:42.88/vblo/04,712.99,yes,locked 2006.225.07:41:42.88/vblo/05,744.99,yes,locked 2006.225.07:41:42.88/vblo/06,752.99,yes,locked 2006.225.07:41:42.88/vblo/07,734.99,yes,locked 2006.225.07:41:42.88/vblo/08,744.99,yes,locked 2006.225.07:41:43.03/vabw/8 2006.225.07:41:43.18/vbbw/8 2006.225.07:41:43.27/xfe/off,on,15.2 2006.225.07:41:43.66/ifatt/23,28,28,28 2006.225.07:41:44.07/fmout-gps/S +4.47E-07 2006.225.07:41:44.11:!2006.225.07:42:40 2006.225.07:42:40.01:data_valid=off 2006.225.07:42:40.02:postob 2006.225.07:42:40.22/cable/+6.4064E-03 2006.225.07:42:40.22/wx/27.99,1003.3,70 2006.225.07:42:41.07/fmout-gps/S +4.48E-07 2006.225.07:42:41.07:scan_name=225-0743,k06225,60 2006.225.07:42:41.08:source=1300+580,130252.47,574837.6,2000.0,ccw 2006.225.07:42:41.13#flagr#flagr/antenna,new-source 2006.225.07:42:42.13:checkk5 2006.225.07:42:42.50/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:42:42.87/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:42:43.24/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:42:43.61/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:42:43.97/chk_obsdata//k5ts1/T2250741??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:42:44.34/chk_obsdata//k5ts2/T2250741??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:42:44.71/chk_obsdata//k5ts3/T2250741??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:42:45.08/chk_obsdata//k5ts4/T2250741??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:42:45.76/k5log//k5ts1_log_newline 2006.225.07:42:46.46/k5log//k5ts2_log_newline 2006.225.07:42:47.14/k5log//k5ts3_log_newline 2006.225.07:42:47.83/k5log//k5ts4_log_newline 2006.225.07:42:47.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:42:47.86:4f8m12a=1 2006.225.07:42:47.86$4f8m12a/echo=on 2006.225.07:42:47.86$4f8m12a/pcalon 2006.225.07:42:47.86$pcalon/"no phase cal control is implemented here 2006.225.07:42:47.86$4f8m12a/"tpicd=stop 2006.225.07:42:47.86$4f8m12a/vc4f8 2006.225.07:42:47.86$vc4f8/valo=1,532.99 2006.225.07:42:47.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.07:42:47.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.07:42:47.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:47.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:42:47.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:42:47.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:42:47.86#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:42:47.86#ibcon#first serial, iclass 34, count 0 2006.225.07:42:47.86#ibcon#enter sib2, iclass 34, count 0 2006.225.07:42:47.86#ibcon#flushed, iclass 34, count 0 2006.225.07:42:47.86#ibcon#about to write, iclass 34, count 0 2006.225.07:42:47.86#ibcon#wrote, iclass 34, count 0 2006.225.07:42:47.86#ibcon#about to read 3, iclass 34, count 0 2006.225.07:42:47.90#ibcon#read 3, iclass 34, count 0 2006.225.07:42:47.90#ibcon#about to read 4, iclass 34, count 0 2006.225.07:42:47.90#ibcon#read 4, iclass 34, count 0 2006.225.07:42:47.90#ibcon#about to read 5, iclass 34, count 0 2006.225.07:42:47.90#ibcon#read 5, iclass 34, count 0 2006.225.07:42:47.90#ibcon#about to read 6, iclass 34, count 0 2006.225.07:42:47.90#ibcon#read 6, iclass 34, count 0 2006.225.07:42:47.90#ibcon#end of sib2, iclass 34, count 0 2006.225.07:42:47.90#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:42:47.90#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:42:47.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:42:47.90#ibcon#*before write, iclass 34, count 0 2006.225.07:42:47.90#ibcon#enter sib2, iclass 34, count 0 2006.225.07:42:47.90#ibcon#flushed, iclass 34, count 0 2006.225.07:42:47.90#ibcon#about to write, iclass 34, count 0 2006.225.07:42:47.90#ibcon#wrote, iclass 34, count 0 2006.225.07:42:47.90#ibcon#about to read 3, iclass 34, count 0 2006.225.07:42:47.95#ibcon#read 3, iclass 34, count 0 2006.225.07:42:47.95#ibcon#about to read 4, iclass 34, count 0 2006.225.07:42:47.95#ibcon#read 4, iclass 34, count 0 2006.225.07:42:47.95#ibcon#about to read 5, iclass 34, count 0 2006.225.07:42:47.95#ibcon#read 5, iclass 34, count 0 2006.225.07:42:47.95#ibcon#about to read 6, iclass 34, count 0 2006.225.07:42:47.95#ibcon#read 6, iclass 34, count 0 2006.225.07:42:47.95#ibcon#end of sib2, iclass 34, count 0 2006.225.07:42:47.95#ibcon#*after write, iclass 34, count 0 2006.225.07:42:47.95#ibcon#*before return 0, iclass 34, count 0 2006.225.07:42:47.95#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:42:47.95#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:42:47.95#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:42:47.95#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:42:47.95$vc4f8/va=1,8 2006.225.07:42:47.95#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.07:42:47.95#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.07:42:47.95#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:47.95#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:42:47.95#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:42:47.95#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:42:47.95#ibcon#enter wrdev, iclass 36, count 2 2006.225.07:42:47.95#ibcon#first serial, iclass 36, count 2 2006.225.07:42:47.95#ibcon#enter sib2, iclass 36, count 2 2006.225.07:42:47.95#ibcon#flushed, iclass 36, count 2 2006.225.07:42:47.95#ibcon#about to write, iclass 36, count 2 2006.225.07:42:47.95#ibcon#wrote, iclass 36, count 2 2006.225.07:42:47.95#ibcon#about to read 3, iclass 36, count 2 2006.225.07:42:47.98#ibcon#read 3, iclass 36, count 2 2006.225.07:42:47.98#ibcon#about to read 4, iclass 36, count 2 2006.225.07:42:47.98#ibcon#read 4, iclass 36, count 2 2006.225.07:42:47.98#ibcon#about to read 5, iclass 36, count 2 2006.225.07:42:47.98#ibcon#read 5, iclass 36, count 2 2006.225.07:42:47.98#ibcon#about to read 6, iclass 36, count 2 2006.225.07:42:47.98#ibcon#read 6, iclass 36, count 2 2006.225.07:42:47.98#ibcon#end of sib2, iclass 36, count 2 2006.225.07:42:47.98#ibcon#*mode == 0, iclass 36, count 2 2006.225.07:42:47.98#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.07:42:47.98#ibcon#[25=AT01-08\r\n] 2006.225.07:42:47.98#ibcon#*before write, iclass 36, count 2 2006.225.07:42:47.98#ibcon#enter sib2, iclass 36, count 2 2006.225.07:42:47.98#ibcon#flushed, iclass 36, count 2 2006.225.07:42:47.98#ibcon#about to write, iclass 36, count 2 2006.225.07:42:47.98#ibcon#wrote, iclass 36, count 2 2006.225.07:42:47.98#ibcon#about to read 3, iclass 36, count 2 2006.225.07:42:48.01#ibcon#read 3, iclass 36, count 2 2006.225.07:42:48.01#ibcon#about to read 4, iclass 36, count 2 2006.225.07:42:48.01#ibcon#read 4, iclass 36, count 2 2006.225.07:42:48.01#ibcon#about to read 5, iclass 36, count 2 2006.225.07:42:48.01#ibcon#read 5, iclass 36, count 2 2006.225.07:42:48.01#ibcon#about to read 6, iclass 36, count 2 2006.225.07:42:48.01#ibcon#read 6, iclass 36, count 2 2006.225.07:42:48.01#ibcon#end of sib2, iclass 36, count 2 2006.225.07:42:48.01#ibcon#*after write, iclass 36, count 2 2006.225.07:42:48.01#ibcon#*before return 0, iclass 36, count 2 2006.225.07:42:48.01#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:42:48.01#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:42:48.01#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.07:42:48.01#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:48.01#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:42:48.13#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:42:48.13#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:42:48.13#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:42:48.13#ibcon#first serial, iclass 36, count 0 2006.225.07:42:48.13#ibcon#enter sib2, iclass 36, count 0 2006.225.07:42:48.13#ibcon#flushed, iclass 36, count 0 2006.225.07:42:48.13#ibcon#about to write, iclass 36, count 0 2006.225.07:42:48.13#ibcon#wrote, iclass 36, count 0 2006.225.07:42:48.13#ibcon#about to read 3, iclass 36, count 0 2006.225.07:42:48.15#ibcon#read 3, iclass 36, count 0 2006.225.07:42:48.15#ibcon#about to read 4, iclass 36, count 0 2006.225.07:42:48.15#ibcon#read 4, iclass 36, count 0 2006.225.07:42:48.15#ibcon#about to read 5, iclass 36, count 0 2006.225.07:42:48.15#ibcon#read 5, iclass 36, count 0 2006.225.07:42:48.15#ibcon#about to read 6, iclass 36, count 0 2006.225.07:42:48.15#ibcon#read 6, iclass 36, count 0 2006.225.07:42:48.15#ibcon#end of sib2, iclass 36, count 0 2006.225.07:42:48.15#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:42:48.15#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:42:48.15#ibcon#[25=USB\r\n] 2006.225.07:42:48.15#ibcon#*before write, iclass 36, count 0 2006.225.07:42:48.15#ibcon#enter sib2, iclass 36, count 0 2006.225.07:42:48.15#ibcon#flushed, iclass 36, count 0 2006.225.07:42:48.15#ibcon#about to write, iclass 36, count 0 2006.225.07:42:48.15#ibcon#wrote, iclass 36, count 0 2006.225.07:42:48.15#ibcon#about to read 3, iclass 36, count 0 2006.225.07:42:48.18#ibcon#read 3, iclass 36, count 0 2006.225.07:42:48.18#ibcon#about to read 4, iclass 36, count 0 2006.225.07:42:48.18#ibcon#read 4, iclass 36, count 0 2006.225.07:42:48.18#ibcon#about to read 5, iclass 36, count 0 2006.225.07:42:48.18#ibcon#read 5, iclass 36, count 0 2006.225.07:42:48.18#ibcon#about to read 6, iclass 36, count 0 2006.225.07:42:48.18#ibcon#read 6, iclass 36, count 0 2006.225.07:42:48.18#ibcon#end of sib2, iclass 36, count 0 2006.225.07:42:48.18#ibcon#*after write, iclass 36, count 0 2006.225.07:42:48.18#ibcon#*before return 0, iclass 36, count 0 2006.225.07:42:48.18#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:42:48.18#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:42:48.18#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:42:48.18#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:42:48.18$vc4f8/valo=2,572.99 2006.225.07:42:48.18#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.07:42:48.18#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.07:42:48.18#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:48.18#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:42:48.18#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:42:48.18#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:42:48.18#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:42:48.18#ibcon#first serial, iclass 38, count 0 2006.225.07:42:48.18#ibcon#enter sib2, iclass 38, count 0 2006.225.07:42:48.18#ibcon#flushed, iclass 38, count 0 2006.225.07:42:48.18#ibcon#about to write, iclass 38, count 0 2006.225.07:42:48.18#ibcon#wrote, iclass 38, count 0 2006.225.07:42:48.18#ibcon#about to read 3, iclass 38, count 0 2006.225.07:42:48.21#ibcon#read 3, iclass 38, count 0 2006.225.07:42:48.21#ibcon#about to read 4, iclass 38, count 0 2006.225.07:42:48.21#ibcon#read 4, iclass 38, count 0 2006.225.07:42:48.21#ibcon#about to read 5, iclass 38, count 0 2006.225.07:42:48.21#ibcon#read 5, iclass 38, count 0 2006.225.07:42:48.21#ibcon#about to read 6, iclass 38, count 0 2006.225.07:42:48.21#ibcon#read 6, iclass 38, count 0 2006.225.07:42:48.21#ibcon#end of sib2, iclass 38, count 0 2006.225.07:42:48.21#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:42:48.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:42:48.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:42:48.21#ibcon#*before write, iclass 38, count 0 2006.225.07:42:48.21#ibcon#enter sib2, iclass 38, count 0 2006.225.07:42:48.21#ibcon#flushed, iclass 38, count 0 2006.225.07:42:48.21#ibcon#about to write, iclass 38, count 0 2006.225.07:42:48.21#ibcon#wrote, iclass 38, count 0 2006.225.07:42:48.21#ibcon#about to read 3, iclass 38, count 0 2006.225.07:42:48.25#ibcon#read 3, iclass 38, count 0 2006.225.07:42:48.25#ibcon#about to read 4, iclass 38, count 0 2006.225.07:42:48.25#ibcon#read 4, iclass 38, count 0 2006.225.07:42:48.25#ibcon#about to read 5, iclass 38, count 0 2006.225.07:42:48.25#ibcon#read 5, iclass 38, count 0 2006.225.07:42:48.25#ibcon#about to read 6, iclass 38, count 0 2006.225.07:42:48.25#ibcon#read 6, iclass 38, count 0 2006.225.07:42:48.25#ibcon#end of sib2, iclass 38, count 0 2006.225.07:42:48.25#ibcon#*after write, iclass 38, count 0 2006.225.07:42:48.25#ibcon#*before return 0, iclass 38, count 0 2006.225.07:42:48.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:42:48.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:42:48.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:42:48.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:42:48.25$vc4f8/va=2,7 2006.225.07:42:48.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.225.07:42:48.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.225.07:42:48.25#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:48.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:42:48.30#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:42:48.30#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:42:48.30#ibcon#enter wrdev, iclass 40, count 2 2006.225.07:42:48.30#ibcon#first serial, iclass 40, count 2 2006.225.07:42:48.30#ibcon#enter sib2, iclass 40, count 2 2006.225.07:42:48.30#ibcon#flushed, iclass 40, count 2 2006.225.07:42:48.30#ibcon#about to write, iclass 40, count 2 2006.225.07:42:48.30#ibcon#wrote, iclass 40, count 2 2006.225.07:42:48.30#ibcon#about to read 3, iclass 40, count 2 2006.225.07:42:48.32#ibcon#read 3, iclass 40, count 2 2006.225.07:42:48.32#ibcon#about to read 4, iclass 40, count 2 2006.225.07:42:48.32#ibcon#read 4, iclass 40, count 2 2006.225.07:42:48.32#ibcon#about to read 5, iclass 40, count 2 2006.225.07:42:48.32#ibcon#read 5, iclass 40, count 2 2006.225.07:42:48.32#ibcon#about to read 6, iclass 40, count 2 2006.225.07:42:48.32#ibcon#read 6, iclass 40, count 2 2006.225.07:42:48.32#ibcon#end of sib2, iclass 40, count 2 2006.225.07:42:48.32#ibcon#*mode == 0, iclass 40, count 2 2006.225.07:42:48.32#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.225.07:42:48.32#ibcon#[25=AT02-07\r\n] 2006.225.07:42:48.32#ibcon#*before write, iclass 40, count 2 2006.225.07:42:48.32#ibcon#enter sib2, iclass 40, count 2 2006.225.07:42:48.32#ibcon#flushed, iclass 40, count 2 2006.225.07:42:48.32#ibcon#about to write, iclass 40, count 2 2006.225.07:42:48.32#ibcon#wrote, iclass 40, count 2 2006.225.07:42:48.32#ibcon#about to read 3, iclass 40, count 2 2006.225.07:42:48.35#ibcon#read 3, iclass 40, count 2 2006.225.07:42:48.35#ibcon#about to read 4, iclass 40, count 2 2006.225.07:42:48.35#ibcon#read 4, iclass 40, count 2 2006.225.07:42:48.35#ibcon#about to read 5, iclass 40, count 2 2006.225.07:42:48.35#ibcon#read 5, iclass 40, count 2 2006.225.07:42:48.35#ibcon#about to read 6, iclass 40, count 2 2006.225.07:42:48.35#ibcon#read 6, iclass 40, count 2 2006.225.07:42:48.35#ibcon#end of sib2, iclass 40, count 2 2006.225.07:42:48.35#ibcon#*after write, iclass 40, count 2 2006.225.07:42:48.35#ibcon#*before return 0, iclass 40, count 2 2006.225.07:42:48.35#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:42:48.35#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:42:48.35#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.225.07:42:48.35#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:48.35#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:42:48.47#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:42:48.47#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:42:48.47#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:42:48.47#ibcon#first serial, iclass 40, count 0 2006.225.07:42:48.47#ibcon#enter sib2, iclass 40, count 0 2006.225.07:42:48.47#ibcon#flushed, iclass 40, count 0 2006.225.07:42:48.47#ibcon#about to write, iclass 40, count 0 2006.225.07:42:48.47#ibcon#wrote, iclass 40, count 0 2006.225.07:42:48.47#ibcon#about to read 3, iclass 40, count 0 2006.225.07:42:48.49#ibcon#read 3, iclass 40, count 0 2006.225.07:42:48.49#ibcon#about to read 4, iclass 40, count 0 2006.225.07:42:48.49#ibcon#read 4, iclass 40, count 0 2006.225.07:42:48.49#ibcon#about to read 5, iclass 40, count 0 2006.225.07:42:48.49#ibcon#read 5, iclass 40, count 0 2006.225.07:42:48.49#ibcon#about to read 6, iclass 40, count 0 2006.225.07:42:48.49#ibcon#read 6, iclass 40, count 0 2006.225.07:42:48.49#ibcon#end of sib2, iclass 40, count 0 2006.225.07:42:48.49#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:42:48.49#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:42:48.49#ibcon#[25=USB\r\n] 2006.225.07:42:48.49#ibcon#*before write, iclass 40, count 0 2006.225.07:42:48.49#ibcon#enter sib2, iclass 40, count 0 2006.225.07:42:48.49#ibcon#flushed, iclass 40, count 0 2006.225.07:42:48.49#ibcon#about to write, iclass 40, count 0 2006.225.07:42:48.49#ibcon#wrote, iclass 40, count 0 2006.225.07:42:48.49#ibcon#about to read 3, iclass 40, count 0 2006.225.07:42:48.52#ibcon#read 3, iclass 40, count 0 2006.225.07:42:48.52#ibcon#about to read 4, iclass 40, count 0 2006.225.07:42:48.52#ibcon#read 4, iclass 40, count 0 2006.225.07:42:48.52#ibcon#about to read 5, iclass 40, count 0 2006.225.07:42:48.52#ibcon#read 5, iclass 40, count 0 2006.225.07:42:48.52#ibcon#about to read 6, iclass 40, count 0 2006.225.07:42:48.52#ibcon#read 6, iclass 40, count 0 2006.225.07:42:48.52#ibcon#end of sib2, iclass 40, count 0 2006.225.07:42:48.52#ibcon#*after write, iclass 40, count 0 2006.225.07:42:48.52#ibcon#*before return 0, iclass 40, count 0 2006.225.07:42:48.52#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:42:48.52#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:42:48.52#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:42:48.52#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:42:48.52$vc4f8/valo=3,672.99 2006.225.07:42:48.52#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.07:42:48.52#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.07:42:48.52#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:48.52#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:42:48.52#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:42:48.52#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:42:48.52#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:42:48.52#ibcon#first serial, iclass 4, count 0 2006.225.07:42:48.52#ibcon#enter sib2, iclass 4, count 0 2006.225.07:42:48.52#ibcon#flushed, iclass 4, count 0 2006.225.07:42:48.52#ibcon#about to write, iclass 4, count 0 2006.225.07:42:48.52#ibcon#wrote, iclass 4, count 0 2006.225.07:42:48.52#ibcon#about to read 3, iclass 4, count 0 2006.225.07:42:48.55#ibcon#read 3, iclass 4, count 0 2006.225.07:42:48.55#ibcon#about to read 4, iclass 4, count 0 2006.225.07:42:48.55#ibcon#read 4, iclass 4, count 0 2006.225.07:42:48.55#ibcon#about to read 5, iclass 4, count 0 2006.225.07:42:48.55#ibcon#read 5, iclass 4, count 0 2006.225.07:42:48.55#ibcon#about to read 6, iclass 4, count 0 2006.225.07:42:48.55#ibcon#read 6, iclass 4, count 0 2006.225.07:42:48.55#ibcon#end of sib2, iclass 4, count 0 2006.225.07:42:48.55#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:42:48.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:42:48.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:42:48.55#ibcon#*before write, iclass 4, count 0 2006.225.07:42:48.55#ibcon#enter sib2, iclass 4, count 0 2006.225.07:42:48.55#ibcon#flushed, iclass 4, count 0 2006.225.07:42:48.55#ibcon#about to write, iclass 4, count 0 2006.225.07:42:48.55#ibcon#wrote, iclass 4, count 0 2006.225.07:42:48.55#ibcon#about to read 3, iclass 4, count 0 2006.225.07:42:48.59#ibcon#read 3, iclass 4, count 0 2006.225.07:42:48.59#ibcon#about to read 4, iclass 4, count 0 2006.225.07:42:48.59#ibcon#read 4, iclass 4, count 0 2006.225.07:42:48.59#ibcon#about to read 5, iclass 4, count 0 2006.225.07:42:48.59#ibcon#read 5, iclass 4, count 0 2006.225.07:42:48.59#ibcon#about to read 6, iclass 4, count 0 2006.225.07:42:48.59#ibcon#read 6, iclass 4, count 0 2006.225.07:42:48.59#ibcon#end of sib2, iclass 4, count 0 2006.225.07:42:48.59#ibcon#*after write, iclass 4, count 0 2006.225.07:42:48.59#ibcon#*before return 0, iclass 4, count 0 2006.225.07:42:48.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:42:48.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:42:48.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:42:48.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:42:48.59$vc4f8/va=3,6 2006.225.07:42:48.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.225.07:42:48.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.225.07:42:48.59#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:48.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:42:48.64#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:42:48.64#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:42:48.64#ibcon#enter wrdev, iclass 6, count 2 2006.225.07:42:48.64#ibcon#first serial, iclass 6, count 2 2006.225.07:42:48.64#ibcon#enter sib2, iclass 6, count 2 2006.225.07:42:48.64#ibcon#flushed, iclass 6, count 2 2006.225.07:42:48.64#ibcon#about to write, iclass 6, count 2 2006.225.07:42:48.64#ibcon#wrote, iclass 6, count 2 2006.225.07:42:48.64#ibcon#about to read 3, iclass 6, count 2 2006.225.07:42:48.66#ibcon#read 3, iclass 6, count 2 2006.225.07:42:48.66#ibcon#about to read 4, iclass 6, count 2 2006.225.07:42:48.66#ibcon#read 4, iclass 6, count 2 2006.225.07:42:48.66#ibcon#about to read 5, iclass 6, count 2 2006.225.07:42:48.66#ibcon#read 5, iclass 6, count 2 2006.225.07:42:48.66#ibcon#about to read 6, iclass 6, count 2 2006.225.07:42:48.66#ibcon#read 6, iclass 6, count 2 2006.225.07:42:48.66#ibcon#end of sib2, iclass 6, count 2 2006.225.07:42:48.66#ibcon#*mode == 0, iclass 6, count 2 2006.225.07:42:48.66#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.225.07:42:48.66#ibcon#[25=AT03-06\r\n] 2006.225.07:42:48.66#ibcon#*before write, iclass 6, count 2 2006.225.07:42:48.66#ibcon#enter sib2, iclass 6, count 2 2006.225.07:42:48.66#ibcon#flushed, iclass 6, count 2 2006.225.07:42:48.66#ibcon#about to write, iclass 6, count 2 2006.225.07:42:48.66#ibcon#wrote, iclass 6, count 2 2006.225.07:42:48.66#ibcon#about to read 3, iclass 6, count 2 2006.225.07:42:48.69#ibcon#read 3, iclass 6, count 2 2006.225.07:42:48.69#ibcon#about to read 4, iclass 6, count 2 2006.225.07:42:48.69#ibcon#read 4, iclass 6, count 2 2006.225.07:42:48.69#ibcon#about to read 5, iclass 6, count 2 2006.225.07:42:48.69#ibcon#read 5, iclass 6, count 2 2006.225.07:42:48.69#ibcon#about to read 6, iclass 6, count 2 2006.225.07:42:48.69#ibcon#read 6, iclass 6, count 2 2006.225.07:42:48.69#ibcon#end of sib2, iclass 6, count 2 2006.225.07:42:48.69#ibcon#*after write, iclass 6, count 2 2006.225.07:42:48.69#ibcon#*before return 0, iclass 6, count 2 2006.225.07:42:48.69#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:42:48.69#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:42:48.69#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.225.07:42:48.69#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:48.69#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:42:48.81#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:42:48.81#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:42:48.81#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:42:48.81#ibcon#first serial, iclass 6, count 0 2006.225.07:42:48.81#ibcon#enter sib2, iclass 6, count 0 2006.225.07:42:48.81#ibcon#flushed, iclass 6, count 0 2006.225.07:42:48.81#ibcon#about to write, iclass 6, count 0 2006.225.07:42:48.81#ibcon#wrote, iclass 6, count 0 2006.225.07:42:48.81#ibcon#about to read 3, iclass 6, count 0 2006.225.07:42:48.83#ibcon#read 3, iclass 6, count 0 2006.225.07:42:48.83#ibcon#about to read 4, iclass 6, count 0 2006.225.07:42:48.83#ibcon#read 4, iclass 6, count 0 2006.225.07:42:48.83#ibcon#about to read 5, iclass 6, count 0 2006.225.07:42:48.83#ibcon#read 5, iclass 6, count 0 2006.225.07:42:48.83#ibcon#about to read 6, iclass 6, count 0 2006.225.07:42:48.83#ibcon#read 6, iclass 6, count 0 2006.225.07:42:48.83#ibcon#end of sib2, iclass 6, count 0 2006.225.07:42:48.83#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:42:48.83#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:42:48.83#ibcon#[25=USB\r\n] 2006.225.07:42:48.83#ibcon#*before write, iclass 6, count 0 2006.225.07:42:48.83#ibcon#enter sib2, iclass 6, count 0 2006.225.07:42:48.83#ibcon#flushed, iclass 6, count 0 2006.225.07:42:48.83#ibcon#about to write, iclass 6, count 0 2006.225.07:42:48.83#ibcon#wrote, iclass 6, count 0 2006.225.07:42:48.83#ibcon#about to read 3, iclass 6, count 0 2006.225.07:42:48.86#ibcon#read 3, iclass 6, count 0 2006.225.07:42:48.86#ibcon#about to read 4, iclass 6, count 0 2006.225.07:42:48.86#ibcon#read 4, iclass 6, count 0 2006.225.07:42:48.86#ibcon#about to read 5, iclass 6, count 0 2006.225.07:42:48.86#ibcon#read 5, iclass 6, count 0 2006.225.07:42:48.86#ibcon#about to read 6, iclass 6, count 0 2006.225.07:42:48.86#ibcon#read 6, iclass 6, count 0 2006.225.07:42:48.86#ibcon#end of sib2, iclass 6, count 0 2006.225.07:42:48.86#ibcon#*after write, iclass 6, count 0 2006.225.07:42:48.86#ibcon#*before return 0, iclass 6, count 0 2006.225.07:42:48.86#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:42:48.86#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:42:48.86#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:42:48.86#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:42:48.86$vc4f8/valo=4,832.99 2006.225.07:42:48.86#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.07:42:48.86#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.07:42:48.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:48.86#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:42:48.86#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:42:48.86#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:42:48.86#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:42:48.86#ibcon#first serial, iclass 10, count 0 2006.225.07:42:48.86#ibcon#enter sib2, iclass 10, count 0 2006.225.07:42:48.86#ibcon#flushed, iclass 10, count 0 2006.225.07:42:48.86#ibcon#about to write, iclass 10, count 0 2006.225.07:42:48.86#ibcon#wrote, iclass 10, count 0 2006.225.07:42:48.86#ibcon#about to read 3, iclass 10, count 0 2006.225.07:42:48.88#ibcon#read 3, iclass 10, count 0 2006.225.07:42:48.88#ibcon#about to read 4, iclass 10, count 0 2006.225.07:42:48.88#ibcon#read 4, iclass 10, count 0 2006.225.07:42:48.88#ibcon#about to read 5, iclass 10, count 0 2006.225.07:42:48.88#ibcon#read 5, iclass 10, count 0 2006.225.07:42:48.88#ibcon#about to read 6, iclass 10, count 0 2006.225.07:42:48.88#ibcon#read 6, iclass 10, count 0 2006.225.07:42:48.88#ibcon#end of sib2, iclass 10, count 0 2006.225.07:42:48.88#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:42:48.88#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:42:48.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:42:48.88#ibcon#*before write, iclass 10, count 0 2006.225.07:42:48.88#ibcon#enter sib2, iclass 10, count 0 2006.225.07:42:48.88#ibcon#flushed, iclass 10, count 0 2006.225.07:42:48.88#ibcon#about to write, iclass 10, count 0 2006.225.07:42:48.88#ibcon#wrote, iclass 10, count 0 2006.225.07:42:48.88#ibcon#about to read 3, iclass 10, count 0 2006.225.07:42:48.92#ibcon#read 3, iclass 10, count 0 2006.225.07:42:48.92#ibcon#about to read 4, iclass 10, count 0 2006.225.07:42:48.92#ibcon#read 4, iclass 10, count 0 2006.225.07:42:48.92#ibcon#about to read 5, iclass 10, count 0 2006.225.07:42:48.92#ibcon#read 5, iclass 10, count 0 2006.225.07:42:48.92#ibcon#about to read 6, iclass 10, count 0 2006.225.07:42:48.92#ibcon#read 6, iclass 10, count 0 2006.225.07:42:48.92#ibcon#end of sib2, iclass 10, count 0 2006.225.07:42:48.92#ibcon#*after write, iclass 10, count 0 2006.225.07:42:48.92#ibcon#*before return 0, iclass 10, count 0 2006.225.07:42:48.92#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:42:48.92#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:42:48.92#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:42:48.92#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:42:48.92$vc4f8/va=4,7 2006.225.07:42:48.92#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.07:42:48.92#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.07:42:48.92#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:48.92#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:42:48.98#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:42:48.98#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:42:48.98#ibcon#enter wrdev, iclass 12, count 2 2006.225.07:42:48.98#ibcon#first serial, iclass 12, count 2 2006.225.07:42:48.98#ibcon#enter sib2, iclass 12, count 2 2006.225.07:42:48.98#ibcon#flushed, iclass 12, count 2 2006.225.07:42:48.98#ibcon#about to write, iclass 12, count 2 2006.225.07:42:48.98#ibcon#wrote, iclass 12, count 2 2006.225.07:42:48.98#ibcon#about to read 3, iclass 12, count 2 2006.225.07:42:49.00#ibcon#read 3, iclass 12, count 2 2006.225.07:42:49.00#ibcon#about to read 4, iclass 12, count 2 2006.225.07:42:49.00#ibcon#read 4, iclass 12, count 2 2006.225.07:42:49.00#ibcon#about to read 5, iclass 12, count 2 2006.225.07:42:49.00#ibcon#read 5, iclass 12, count 2 2006.225.07:42:49.00#ibcon#about to read 6, iclass 12, count 2 2006.225.07:42:49.00#ibcon#read 6, iclass 12, count 2 2006.225.07:42:49.00#ibcon#end of sib2, iclass 12, count 2 2006.225.07:42:49.00#ibcon#*mode == 0, iclass 12, count 2 2006.225.07:42:49.00#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.07:42:49.00#ibcon#[25=AT04-07\r\n] 2006.225.07:42:49.00#ibcon#*before write, iclass 12, count 2 2006.225.07:42:49.00#ibcon#enter sib2, iclass 12, count 2 2006.225.07:42:49.00#ibcon#flushed, iclass 12, count 2 2006.225.07:42:49.00#ibcon#about to write, iclass 12, count 2 2006.225.07:42:49.00#ibcon#wrote, iclass 12, count 2 2006.225.07:42:49.00#ibcon#about to read 3, iclass 12, count 2 2006.225.07:42:49.03#ibcon#read 3, iclass 12, count 2 2006.225.07:42:49.03#ibcon#about to read 4, iclass 12, count 2 2006.225.07:42:49.03#ibcon#read 4, iclass 12, count 2 2006.225.07:42:49.03#ibcon#about to read 5, iclass 12, count 2 2006.225.07:42:49.03#ibcon#read 5, iclass 12, count 2 2006.225.07:42:49.03#ibcon#about to read 6, iclass 12, count 2 2006.225.07:42:49.03#ibcon#read 6, iclass 12, count 2 2006.225.07:42:49.03#ibcon#end of sib2, iclass 12, count 2 2006.225.07:42:49.03#ibcon#*after write, iclass 12, count 2 2006.225.07:42:49.03#ibcon#*before return 0, iclass 12, count 2 2006.225.07:42:49.03#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:42:49.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:42:49.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.07:42:49.03#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:49.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:42:49.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:42:49.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:42:49.15#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:42:49.15#ibcon#first serial, iclass 12, count 0 2006.225.07:42:49.15#ibcon#enter sib2, iclass 12, count 0 2006.225.07:42:49.15#ibcon#flushed, iclass 12, count 0 2006.225.07:42:49.15#ibcon#about to write, iclass 12, count 0 2006.225.07:42:49.15#ibcon#wrote, iclass 12, count 0 2006.225.07:42:49.15#ibcon#about to read 3, iclass 12, count 0 2006.225.07:42:49.17#ibcon#read 3, iclass 12, count 0 2006.225.07:42:49.17#ibcon#about to read 4, iclass 12, count 0 2006.225.07:42:49.17#ibcon#read 4, iclass 12, count 0 2006.225.07:42:49.17#ibcon#about to read 5, iclass 12, count 0 2006.225.07:42:49.17#ibcon#read 5, iclass 12, count 0 2006.225.07:42:49.17#ibcon#about to read 6, iclass 12, count 0 2006.225.07:42:49.17#ibcon#read 6, iclass 12, count 0 2006.225.07:42:49.17#ibcon#end of sib2, iclass 12, count 0 2006.225.07:42:49.17#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:42:49.17#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:42:49.17#ibcon#[25=USB\r\n] 2006.225.07:42:49.17#ibcon#*before write, iclass 12, count 0 2006.225.07:42:49.17#ibcon#enter sib2, iclass 12, count 0 2006.225.07:42:49.17#ibcon#flushed, iclass 12, count 0 2006.225.07:42:49.17#ibcon#about to write, iclass 12, count 0 2006.225.07:42:49.17#ibcon#wrote, iclass 12, count 0 2006.225.07:42:49.17#ibcon#about to read 3, iclass 12, count 0 2006.225.07:42:49.20#ibcon#read 3, iclass 12, count 0 2006.225.07:42:49.20#ibcon#about to read 4, iclass 12, count 0 2006.225.07:42:49.20#ibcon#read 4, iclass 12, count 0 2006.225.07:42:49.20#ibcon#about to read 5, iclass 12, count 0 2006.225.07:42:49.20#ibcon#read 5, iclass 12, count 0 2006.225.07:42:49.20#ibcon#about to read 6, iclass 12, count 0 2006.225.07:42:49.20#ibcon#read 6, iclass 12, count 0 2006.225.07:42:49.20#ibcon#end of sib2, iclass 12, count 0 2006.225.07:42:49.20#ibcon#*after write, iclass 12, count 0 2006.225.07:42:49.20#ibcon#*before return 0, iclass 12, count 0 2006.225.07:42:49.20#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:42:49.20#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:42:49.20#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:42:49.20#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:42:49.20$vc4f8/valo=5,652.99 2006.225.07:42:49.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.07:42:49.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.07:42:49.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:49.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:42:49.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:42:49.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:42:49.20#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:42:49.20#ibcon#first serial, iclass 14, count 0 2006.225.07:42:49.20#ibcon#enter sib2, iclass 14, count 0 2006.225.07:42:49.20#ibcon#flushed, iclass 14, count 0 2006.225.07:42:49.20#ibcon#about to write, iclass 14, count 0 2006.225.07:42:49.20#ibcon#wrote, iclass 14, count 0 2006.225.07:42:49.20#ibcon#about to read 3, iclass 14, count 0 2006.225.07:42:49.22#ibcon#read 3, iclass 14, count 0 2006.225.07:42:49.22#ibcon#about to read 4, iclass 14, count 0 2006.225.07:42:49.22#ibcon#read 4, iclass 14, count 0 2006.225.07:42:49.22#ibcon#about to read 5, iclass 14, count 0 2006.225.07:42:49.22#ibcon#read 5, iclass 14, count 0 2006.225.07:42:49.22#ibcon#about to read 6, iclass 14, count 0 2006.225.07:42:49.22#ibcon#read 6, iclass 14, count 0 2006.225.07:42:49.22#ibcon#end of sib2, iclass 14, count 0 2006.225.07:42:49.22#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:42:49.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:42:49.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:42:49.22#ibcon#*before write, iclass 14, count 0 2006.225.07:42:49.22#ibcon#enter sib2, iclass 14, count 0 2006.225.07:42:49.22#ibcon#flushed, iclass 14, count 0 2006.225.07:42:49.22#ibcon#about to write, iclass 14, count 0 2006.225.07:42:49.22#ibcon#wrote, iclass 14, count 0 2006.225.07:42:49.22#ibcon#about to read 3, iclass 14, count 0 2006.225.07:42:49.26#ibcon#read 3, iclass 14, count 0 2006.225.07:42:49.26#ibcon#about to read 4, iclass 14, count 0 2006.225.07:42:49.26#ibcon#read 4, iclass 14, count 0 2006.225.07:42:49.26#ibcon#about to read 5, iclass 14, count 0 2006.225.07:42:49.26#ibcon#read 5, iclass 14, count 0 2006.225.07:42:49.26#ibcon#about to read 6, iclass 14, count 0 2006.225.07:42:49.26#ibcon#read 6, iclass 14, count 0 2006.225.07:42:49.26#ibcon#end of sib2, iclass 14, count 0 2006.225.07:42:49.26#ibcon#*after write, iclass 14, count 0 2006.225.07:42:49.26#ibcon#*before return 0, iclass 14, count 0 2006.225.07:42:49.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:42:49.26#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:42:49.26#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:42:49.26#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:42:49.26$vc4f8/va=5,7 2006.225.07:42:49.26#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.07:42:49.26#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.07:42:49.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:49.26#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:42:49.32#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:42:49.32#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:42:49.32#ibcon#enter wrdev, iclass 16, count 2 2006.225.07:42:49.32#ibcon#first serial, iclass 16, count 2 2006.225.07:42:49.32#ibcon#enter sib2, iclass 16, count 2 2006.225.07:42:49.32#ibcon#flushed, iclass 16, count 2 2006.225.07:42:49.32#ibcon#about to write, iclass 16, count 2 2006.225.07:42:49.32#ibcon#wrote, iclass 16, count 2 2006.225.07:42:49.32#ibcon#about to read 3, iclass 16, count 2 2006.225.07:42:49.34#ibcon#read 3, iclass 16, count 2 2006.225.07:42:49.34#ibcon#about to read 4, iclass 16, count 2 2006.225.07:42:49.34#ibcon#read 4, iclass 16, count 2 2006.225.07:42:49.34#ibcon#about to read 5, iclass 16, count 2 2006.225.07:42:49.34#ibcon#read 5, iclass 16, count 2 2006.225.07:42:49.34#ibcon#about to read 6, iclass 16, count 2 2006.225.07:42:49.34#ibcon#read 6, iclass 16, count 2 2006.225.07:42:49.34#ibcon#end of sib2, iclass 16, count 2 2006.225.07:42:49.34#ibcon#*mode == 0, iclass 16, count 2 2006.225.07:42:49.34#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.07:42:49.34#ibcon#[25=AT05-07\r\n] 2006.225.07:42:49.34#ibcon#*before write, iclass 16, count 2 2006.225.07:42:49.34#ibcon#enter sib2, iclass 16, count 2 2006.225.07:42:49.34#ibcon#flushed, iclass 16, count 2 2006.225.07:42:49.34#ibcon#about to write, iclass 16, count 2 2006.225.07:42:49.34#ibcon#wrote, iclass 16, count 2 2006.225.07:42:49.34#ibcon#about to read 3, iclass 16, count 2 2006.225.07:42:49.37#ibcon#read 3, iclass 16, count 2 2006.225.07:42:49.37#ibcon#about to read 4, iclass 16, count 2 2006.225.07:42:49.37#ibcon#read 4, iclass 16, count 2 2006.225.07:42:49.37#ibcon#about to read 5, iclass 16, count 2 2006.225.07:42:49.37#ibcon#read 5, iclass 16, count 2 2006.225.07:42:49.37#ibcon#about to read 6, iclass 16, count 2 2006.225.07:42:49.37#ibcon#read 6, iclass 16, count 2 2006.225.07:42:49.37#ibcon#end of sib2, iclass 16, count 2 2006.225.07:42:49.37#ibcon#*after write, iclass 16, count 2 2006.225.07:42:49.37#ibcon#*before return 0, iclass 16, count 2 2006.225.07:42:49.37#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:42:49.37#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:42:49.37#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.07:42:49.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:49.37#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:42:49.49#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:42:49.49#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:42:49.49#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:42:49.49#ibcon#first serial, iclass 16, count 0 2006.225.07:42:49.49#ibcon#enter sib2, iclass 16, count 0 2006.225.07:42:49.49#ibcon#flushed, iclass 16, count 0 2006.225.07:42:49.49#ibcon#about to write, iclass 16, count 0 2006.225.07:42:49.49#ibcon#wrote, iclass 16, count 0 2006.225.07:42:49.49#ibcon#about to read 3, iclass 16, count 0 2006.225.07:42:49.51#ibcon#read 3, iclass 16, count 0 2006.225.07:42:49.51#ibcon#about to read 4, iclass 16, count 0 2006.225.07:42:49.51#ibcon#read 4, iclass 16, count 0 2006.225.07:42:49.51#ibcon#about to read 5, iclass 16, count 0 2006.225.07:42:49.51#ibcon#read 5, iclass 16, count 0 2006.225.07:42:49.51#ibcon#about to read 6, iclass 16, count 0 2006.225.07:42:49.51#ibcon#read 6, iclass 16, count 0 2006.225.07:42:49.51#ibcon#end of sib2, iclass 16, count 0 2006.225.07:42:49.51#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:42:49.51#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:42:49.51#ibcon#[25=USB\r\n] 2006.225.07:42:49.51#ibcon#*before write, iclass 16, count 0 2006.225.07:42:49.51#ibcon#enter sib2, iclass 16, count 0 2006.225.07:42:49.51#ibcon#flushed, iclass 16, count 0 2006.225.07:42:49.51#ibcon#about to write, iclass 16, count 0 2006.225.07:42:49.51#ibcon#wrote, iclass 16, count 0 2006.225.07:42:49.51#ibcon#about to read 3, iclass 16, count 0 2006.225.07:42:49.54#ibcon#read 3, iclass 16, count 0 2006.225.07:42:49.54#ibcon#about to read 4, iclass 16, count 0 2006.225.07:42:49.54#ibcon#read 4, iclass 16, count 0 2006.225.07:42:49.54#ibcon#about to read 5, iclass 16, count 0 2006.225.07:42:49.54#ibcon#read 5, iclass 16, count 0 2006.225.07:42:49.54#ibcon#about to read 6, iclass 16, count 0 2006.225.07:42:49.54#ibcon#read 6, iclass 16, count 0 2006.225.07:42:49.54#ibcon#end of sib2, iclass 16, count 0 2006.225.07:42:49.54#ibcon#*after write, iclass 16, count 0 2006.225.07:42:49.54#ibcon#*before return 0, iclass 16, count 0 2006.225.07:42:49.54#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:42:49.54#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:42:49.54#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:42:49.54#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:42:49.54$vc4f8/valo=6,772.99 2006.225.07:42:49.54#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.07:42:49.54#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.07:42:49.54#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:49.54#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:42:49.54#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:42:49.54#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:42:49.54#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:42:49.54#ibcon#first serial, iclass 18, count 0 2006.225.07:42:49.54#ibcon#enter sib2, iclass 18, count 0 2006.225.07:42:49.54#ibcon#flushed, iclass 18, count 0 2006.225.07:42:49.54#ibcon#about to write, iclass 18, count 0 2006.225.07:42:49.54#ibcon#wrote, iclass 18, count 0 2006.225.07:42:49.54#ibcon#about to read 3, iclass 18, count 0 2006.225.07:42:49.56#ibcon#read 3, iclass 18, count 0 2006.225.07:42:49.56#ibcon#about to read 4, iclass 18, count 0 2006.225.07:42:49.56#ibcon#read 4, iclass 18, count 0 2006.225.07:42:49.56#ibcon#about to read 5, iclass 18, count 0 2006.225.07:42:49.56#ibcon#read 5, iclass 18, count 0 2006.225.07:42:49.56#ibcon#about to read 6, iclass 18, count 0 2006.225.07:42:49.56#ibcon#read 6, iclass 18, count 0 2006.225.07:42:49.56#ibcon#end of sib2, iclass 18, count 0 2006.225.07:42:49.56#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:42:49.56#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:42:49.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:42:49.56#ibcon#*before write, iclass 18, count 0 2006.225.07:42:49.56#ibcon#enter sib2, iclass 18, count 0 2006.225.07:42:49.56#ibcon#flushed, iclass 18, count 0 2006.225.07:42:49.56#ibcon#about to write, iclass 18, count 0 2006.225.07:42:49.56#ibcon#wrote, iclass 18, count 0 2006.225.07:42:49.56#ibcon#about to read 3, iclass 18, count 0 2006.225.07:42:49.60#ibcon#read 3, iclass 18, count 0 2006.225.07:42:49.60#ibcon#about to read 4, iclass 18, count 0 2006.225.07:42:49.60#ibcon#read 4, iclass 18, count 0 2006.225.07:42:49.60#ibcon#about to read 5, iclass 18, count 0 2006.225.07:42:49.60#ibcon#read 5, iclass 18, count 0 2006.225.07:42:49.60#ibcon#about to read 6, iclass 18, count 0 2006.225.07:42:49.60#ibcon#read 6, iclass 18, count 0 2006.225.07:42:49.60#ibcon#end of sib2, iclass 18, count 0 2006.225.07:42:49.60#ibcon#*after write, iclass 18, count 0 2006.225.07:42:49.60#ibcon#*before return 0, iclass 18, count 0 2006.225.07:42:49.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:42:49.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:42:49.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:42:49.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:42:49.60$vc4f8/va=6,6 2006.225.07:42:49.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.07:42:49.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.07:42:49.60#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:49.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:42:49.66#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:42:49.66#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:42:49.66#ibcon#enter wrdev, iclass 20, count 2 2006.225.07:42:49.66#ibcon#first serial, iclass 20, count 2 2006.225.07:42:49.66#ibcon#enter sib2, iclass 20, count 2 2006.225.07:42:49.66#ibcon#flushed, iclass 20, count 2 2006.225.07:42:49.66#ibcon#about to write, iclass 20, count 2 2006.225.07:42:49.66#ibcon#wrote, iclass 20, count 2 2006.225.07:42:49.66#ibcon#about to read 3, iclass 20, count 2 2006.225.07:42:49.68#ibcon#read 3, iclass 20, count 2 2006.225.07:42:49.68#ibcon#about to read 4, iclass 20, count 2 2006.225.07:42:49.68#ibcon#read 4, iclass 20, count 2 2006.225.07:42:49.68#ibcon#about to read 5, iclass 20, count 2 2006.225.07:42:49.68#ibcon#read 5, iclass 20, count 2 2006.225.07:42:49.68#ibcon#about to read 6, iclass 20, count 2 2006.225.07:42:49.68#ibcon#read 6, iclass 20, count 2 2006.225.07:42:49.68#ibcon#end of sib2, iclass 20, count 2 2006.225.07:42:49.68#ibcon#*mode == 0, iclass 20, count 2 2006.225.07:42:49.68#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.07:42:49.68#ibcon#[25=AT06-06\r\n] 2006.225.07:42:49.68#ibcon#*before write, iclass 20, count 2 2006.225.07:42:49.68#ibcon#enter sib2, iclass 20, count 2 2006.225.07:42:49.68#ibcon#flushed, iclass 20, count 2 2006.225.07:42:49.68#ibcon#about to write, iclass 20, count 2 2006.225.07:42:49.68#ibcon#wrote, iclass 20, count 2 2006.225.07:42:49.68#ibcon#about to read 3, iclass 20, count 2 2006.225.07:42:49.71#ibcon#read 3, iclass 20, count 2 2006.225.07:42:49.71#ibcon#about to read 4, iclass 20, count 2 2006.225.07:42:49.71#ibcon#read 4, iclass 20, count 2 2006.225.07:42:49.71#ibcon#about to read 5, iclass 20, count 2 2006.225.07:42:49.71#ibcon#read 5, iclass 20, count 2 2006.225.07:42:49.71#ibcon#about to read 6, iclass 20, count 2 2006.225.07:42:49.71#ibcon#read 6, iclass 20, count 2 2006.225.07:42:49.71#ibcon#end of sib2, iclass 20, count 2 2006.225.07:42:49.71#ibcon#*after write, iclass 20, count 2 2006.225.07:42:49.71#ibcon#*before return 0, iclass 20, count 2 2006.225.07:42:49.71#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:42:49.71#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:42:49.71#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.07:42:49.71#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:49.71#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:42:49.83#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:42:49.83#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:42:49.83#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:42:49.83#ibcon#first serial, iclass 20, count 0 2006.225.07:42:49.83#ibcon#enter sib2, iclass 20, count 0 2006.225.07:42:49.83#ibcon#flushed, iclass 20, count 0 2006.225.07:42:49.83#ibcon#about to write, iclass 20, count 0 2006.225.07:42:49.83#ibcon#wrote, iclass 20, count 0 2006.225.07:42:49.83#ibcon#about to read 3, iclass 20, count 0 2006.225.07:42:49.85#ibcon#read 3, iclass 20, count 0 2006.225.07:42:49.85#ibcon#about to read 4, iclass 20, count 0 2006.225.07:42:49.85#ibcon#read 4, iclass 20, count 0 2006.225.07:42:49.85#ibcon#about to read 5, iclass 20, count 0 2006.225.07:42:49.85#ibcon#read 5, iclass 20, count 0 2006.225.07:42:49.85#ibcon#about to read 6, iclass 20, count 0 2006.225.07:42:49.85#ibcon#read 6, iclass 20, count 0 2006.225.07:42:49.85#ibcon#end of sib2, iclass 20, count 0 2006.225.07:42:49.85#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:42:49.85#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:42:49.85#ibcon#[25=USB\r\n] 2006.225.07:42:49.85#ibcon#*before write, iclass 20, count 0 2006.225.07:42:49.85#ibcon#enter sib2, iclass 20, count 0 2006.225.07:42:49.85#ibcon#flushed, iclass 20, count 0 2006.225.07:42:49.85#ibcon#about to write, iclass 20, count 0 2006.225.07:42:49.85#ibcon#wrote, iclass 20, count 0 2006.225.07:42:49.85#ibcon#about to read 3, iclass 20, count 0 2006.225.07:42:49.88#ibcon#read 3, iclass 20, count 0 2006.225.07:42:49.88#ibcon#about to read 4, iclass 20, count 0 2006.225.07:42:49.88#ibcon#read 4, iclass 20, count 0 2006.225.07:42:49.88#ibcon#about to read 5, iclass 20, count 0 2006.225.07:42:49.88#ibcon#read 5, iclass 20, count 0 2006.225.07:42:49.88#ibcon#about to read 6, iclass 20, count 0 2006.225.07:42:49.88#ibcon#read 6, iclass 20, count 0 2006.225.07:42:49.88#ibcon#end of sib2, iclass 20, count 0 2006.225.07:42:49.88#ibcon#*after write, iclass 20, count 0 2006.225.07:42:49.88#ibcon#*before return 0, iclass 20, count 0 2006.225.07:42:49.88#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:42:49.88#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:42:49.88#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:42:49.88#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:42:49.88$vc4f8/valo=7,832.99 2006.225.07:42:49.88#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.07:42:49.88#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.07:42:49.88#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:49.88#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:42:49.88#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:42:49.88#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:42:49.88#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:42:49.88#ibcon#first serial, iclass 22, count 0 2006.225.07:42:49.88#ibcon#enter sib2, iclass 22, count 0 2006.225.07:42:49.88#ibcon#flushed, iclass 22, count 0 2006.225.07:42:49.88#ibcon#about to write, iclass 22, count 0 2006.225.07:42:49.88#ibcon#wrote, iclass 22, count 0 2006.225.07:42:49.88#ibcon#about to read 3, iclass 22, count 0 2006.225.07:42:49.90#ibcon#read 3, iclass 22, count 0 2006.225.07:42:49.90#ibcon#about to read 4, iclass 22, count 0 2006.225.07:42:49.90#ibcon#read 4, iclass 22, count 0 2006.225.07:42:49.90#ibcon#about to read 5, iclass 22, count 0 2006.225.07:42:49.90#ibcon#read 5, iclass 22, count 0 2006.225.07:42:49.90#ibcon#about to read 6, iclass 22, count 0 2006.225.07:42:49.90#ibcon#read 6, iclass 22, count 0 2006.225.07:42:49.90#ibcon#end of sib2, iclass 22, count 0 2006.225.07:42:49.90#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:42:49.90#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:42:49.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:42:49.90#ibcon#*before write, iclass 22, count 0 2006.225.07:42:49.90#ibcon#enter sib2, iclass 22, count 0 2006.225.07:42:49.90#ibcon#flushed, iclass 22, count 0 2006.225.07:42:49.90#ibcon#about to write, iclass 22, count 0 2006.225.07:42:49.90#ibcon#wrote, iclass 22, count 0 2006.225.07:42:49.90#ibcon#about to read 3, iclass 22, count 0 2006.225.07:42:49.94#ibcon#read 3, iclass 22, count 0 2006.225.07:42:49.94#ibcon#about to read 4, iclass 22, count 0 2006.225.07:42:49.94#ibcon#read 4, iclass 22, count 0 2006.225.07:42:49.94#ibcon#about to read 5, iclass 22, count 0 2006.225.07:42:49.94#ibcon#read 5, iclass 22, count 0 2006.225.07:42:49.94#ibcon#about to read 6, iclass 22, count 0 2006.225.07:42:49.94#ibcon#read 6, iclass 22, count 0 2006.225.07:42:49.94#ibcon#end of sib2, iclass 22, count 0 2006.225.07:42:49.94#ibcon#*after write, iclass 22, count 0 2006.225.07:42:49.94#ibcon#*before return 0, iclass 22, count 0 2006.225.07:42:49.94#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:42:49.94#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:42:49.94#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:42:49.94#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:42:49.94$vc4f8/va=7,6 2006.225.07:42:49.94#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.07:42:49.94#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.07:42:49.94#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:49.94#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:42:50.00#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:42:50.00#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:42:50.00#ibcon#enter wrdev, iclass 24, count 2 2006.225.07:42:50.00#ibcon#first serial, iclass 24, count 2 2006.225.07:42:50.00#ibcon#enter sib2, iclass 24, count 2 2006.225.07:42:50.00#ibcon#flushed, iclass 24, count 2 2006.225.07:42:50.00#ibcon#about to write, iclass 24, count 2 2006.225.07:42:50.00#ibcon#wrote, iclass 24, count 2 2006.225.07:42:50.00#ibcon#about to read 3, iclass 24, count 2 2006.225.07:42:50.02#ibcon#read 3, iclass 24, count 2 2006.225.07:42:50.02#ibcon#about to read 4, iclass 24, count 2 2006.225.07:42:50.02#ibcon#read 4, iclass 24, count 2 2006.225.07:42:50.02#ibcon#about to read 5, iclass 24, count 2 2006.225.07:42:50.02#ibcon#read 5, iclass 24, count 2 2006.225.07:42:50.02#ibcon#about to read 6, iclass 24, count 2 2006.225.07:42:50.02#ibcon#read 6, iclass 24, count 2 2006.225.07:42:50.02#ibcon#end of sib2, iclass 24, count 2 2006.225.07:42:50.02#ibcon#*mode == 0, iclass 24, count 2 2006.225.07:42:50.02#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.07:42:50.02#ibcon#[25=AT07-06\r\n] 2006.225.07:42:50.02#ibcon#*before write, iclass 24, count 2 2006.225.07:42:50.02#ibcon#enter sib2, iclass 24, count 2 2006.225.07:42:50.02#ibcon#flushed, iclass 24, count 2 2006.225.07:42:50.02#ibcon#about to write, iclass 24, count 2 2006.225.07:42:50.02#ibcon#wrote, iclass 24, count 2 2006.225.07:42:50.02#ibcon#about to read 3, iclass 24, count 2 2006.225.07:42:50.05#ibcon#read 3, iclass 24, count 2 2006.225.07:42:50.05#ibcon#about to read 4, iclass 24, count 2 2006.225.07:42:50.05#ibcon#read 4, iclass 24, count 2 2006.225.07:42:50.05#ibcon#about to read 5, iclass 24, count 2 2006.225.07:42:50.05#ibcon#read 5, iclass 24, count 2 2006.225.07:42:50.05#ibcon#about to read 6, iclass 24, count 2 2006.225.07:42:50.05#ibcon#read 6, iclass 24, count 2 2006.225.07:42:50.05#ibcon#end of sib2, iclass 24, count 2 2006.225.07:42:50.05#ibcon#*after write, iclass 24, count 2 2006.225.07:42:50.05#ibcon#*before return 0, iclass 24, count 2 2006.225.07:42:50.05#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:42:50.05#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:42:50.05#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.07:42:50.05#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:50.05#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:42:50.17#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:42:50.17#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:42:50.17#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:42:50.17#ibcon#first serial, iclass 24, count 0 2006.225.07:42:50.17#ibcon#enter sib2, iclass 24, count 0 2006.225.07:42:50.17#ibcon#flushed, iclass 24, count 0 2006.225.07:42:50.17#ibcon#about to write, iclass 24, count 0 2006.225.07:42:50.17#ibcon#wrote, iclass 24, count 0 2006.225.07:42:50.17#ibcon#about to read 3, iclass 24, count 0 2006.225.07:42:50.19#ibcon#read 3, iclass 24, count 0 2006.225.07:42:50.19#ibcon#about to read 4, iclass 24, count 0 2006.225.07:42:50.19#ibcon#read 4, iclass 24, count 0 2006.225.07:42:50.19#ibcon#about to read 5, iclass 24, count 0 2006.225.07:42:50.19#ibcon#read 5, iclass 24, count 0 2006.225.07:42:50.19#ibcon#about to read 6, iclass 24, count 0 2006.225.07:42:50.19#ibcon#read 6, iclass 24, count 0 2006.225.07:42:50.19#ibcon#end of sib2, iclass 24, count 0 2006.225.07:42:50.19#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:42:50.19#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:42:50.19#ibcon#[25=USB\r\n] 2006.225.07:42:50.19#ibcon#*before write, iclass 24, count 0 2006.225.07:42:50.19#ibcon#enter sib2, iclass 24, count 0 2006.225.07:42:50.19#ibcon#flushed, iclass 24, count 0 2006.225.07:42:50.19#ibcon#about to write, iclass 24, count 0 2006.225.07:42:50.19#ibcon#wrote, iclass 24, count 0 2006.225.07:42:50.19#ibcon#about to read 3, iclass 24, count 0 2006.225.07:42:50.22#ibcon#read 3, iclass 24, count 0 2006.225.07:42:50.22#ibcon#about to read 4, iclass 24, count 0 2006.225.07:42:50.22#ibcon#read 4, iclass 24, count 0 2006.225.07:42:50.22#ibcon#about to read 5, iclass 24, count 0 2006.225.07:42:50.22#ibcon#read 5, iclass 24, count 0 2006.225.07:42:50.22#ibcon#about to read 6, iclass 24, count 0 2006.225.07:42:50.22#ibcon#read 6, iclass 24, count 0 2006.225.07:42:50.22#ibcon#end of sib2, iclass 24, count 0 2006.225.07:42:50.22#ibcon#*after write, iclass 24, count 0 2006.225.07:42:50.22#ibcon#*before return 0, iclass 24, count 0 2006.225.07:42:50.22#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:42:50.22#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:42:50.22#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:42:50.22#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:42:50.22$vc4f8/valo=8,852.99 2006.225.07:42:50.22#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.07:42:50.22#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.07:42:50.22#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:50.22#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:42:50.22#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:42:50.22#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:42:50.22#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:42:50.22#ibcon#first serial, iclass 26, count 0 2006.225.07:42:50.22#ibcon#enter sib2, iclass 26, count 0 2006.225.07:42:50.22#ibcon#flushed, iclass 26, count 0 2006.225.07:42:50.22#ibcon#about to write, iclass 26, count 0 2006.225.07:42:50.22#ibcon#wrote, iclass 26, count 0 2006.225.07:42:50.22#ibcon#about to read 3, iclass 26, count 0 2006.225.07:42:50.24#ibcon#read 3, iclass 26, count 0 2006.225.07:42:50.24#ibcon#about to read 4, iclass 26, count 0 2006.225.07:42:50.24#ibcon#read 4, iclass 26, count 0 2006.225.07:42:50.24#ibcon#about to read 5, iclass 26, count 0 2006.225.07:42:50.24#ibcon#read 5, iclass 26, count 0 2006.225.07:42:50.24#ibcon#about to read 6, iclass 26, count 0 2006.225.07:42:50.24#ibcon#read 6, iclass 26, count 0 2006.225.07:42:50.24#ibcon#end of sib2, iclass 26, count 0 2006.225.07:42:50.24#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:42:50.24#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:42:50.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:42:50.24#ibcon#*before write, iclass 26, count 0 2006.225.07:42:50.24#ibcon#enter sib2, iclass 26, count 0 2006.225.07:42:50.24#ibcon#flushed, iclass 26, count 0 2006.225.07:42:50.24#ibcon#about to write, iclass 26, count 0 2006.225.07:42:50.24#ibcon#wrote, iclass 26, count 0 2006.225.07:42:50.24#ibcon#about to read 3, iclass 26, count 0 2006.225.07:42:50.28#ibcon#read 3, iclass 26, count 0 2006.225.07:42:50.28#ibcon#about to read 4, iclass 26, count 0 2006.225.07:42:50.28#ibcon#read 4, iclass 26, count 0 2006.225.07:42:50.28#ibcon#about to read 5, iclass 26, count 0 2006.225.07:42:50.28#ibcon#read 5, iclass 26, count 0 2006.225.07:42:50.28#ibcon#about to read 6, iclass 26, count 0 2006.225.07:42:50.28#ibcon#read 6, iclass 26, count 0 2006.225.07:42:50.28#ibcon#end of sib2, iclass 26, count 0 2006.225.07:42:50.28#ibcon#*after write, iclass 26, count 0 2006.225.07:42:50.28#ibcon#*before return 0, iclass 26, count 0 2006.225.07:42:50.28#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:42:50.28#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:42:50.28#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:42:50.28#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:42:50.28$vc4f8/va=8,7 2006.225.07:42:50.28#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.07:42:50.28#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.07:42:50.28#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:50.28#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:42:50.34#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:42:50.34#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:42:50.34#ibcon#enter wrdev, iclass 28, count 2 2006.225.07:42:50.34#ibcon#first serial, iclass 28, count 2 2006.225.07:42:50.34#ibcon#enter sib2, iclass 28, count 2 2006.225.07:42:50.34#ibcon#flushed, iclass 28, count 2 2006.225.07:42:50.34#ibcon#about to write, iclass 28, count 2 2006.225.07:42:50.34#ibcon#wrote, iclass 28, count 2 2006.225.07:42:50.34#ibcon#about to read 3, iclass 28, count 2 2006.225.07:42:50.36#ibcon#read 3, iclass 28, count 2 2006.225.07:42:50.36#ibcon#about to read 4, iclass 28, count 2 2006.225.07:42:50.36#ibcon#read 4, iclass 28, count 2 2006.225.07:42:50.36#ibcon#about to read 5, iclass 28, count 2 2006.225.07:42:50.36#ibcon#read 5, iclass 28, count 2 2006.225.07:42:50.36#ibcon#about to read 6, iclass 28, count 2 2006.225.07:42:50.36#ibcon#read 6, iclass 28, count 2 2006.225.07:42:50.36#ibcon#end of sib2, iclass 28, count 2 2006.225.07:42:50.36#ibcon#*mode == 0, iclass 28, count 2 2006.225.07:42:50.36#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.07:42:50.36#ibcon#[25=AT08-07\r\n] 2006.225.07:42:50.36#ibcon#*before write, iclass 28, count 2 2006.225.07:42:50.36#ibcon#enter sib2, iclass 28, count 2 2006.225.07:42:50.36#ibcon#flushed, iclass 28, count 2 2006.225.07:42:50.36#ibcon#about to write, iclass 28, count 2 2006.225.07:42:50.36#ibcon#wrote, iclass 28, count 2 2006.225.07:42:50.36#ibcon#about to read 3, iclass 28, count 2 2006.225.07:42:50.39#ibcon#read 3, iclass 28, count 2 2006.225.07:42:50.39#ibcon#about to read 4, iclass 28, count 2 2006.225.07:42:50.39#ibcon#read 4, iclass 28, count 2 2006.225.07:42:50.39#ibcon#about to read 5, iclass 28, count 2 2006.225.07:42:50.39#ibcon#read 5, iclass 28, count 2 2006.225.07:42:50.39#ibcon#about to read 6, iclass 28, count 2 2006.225.07:42:50.39#ibcon#read 6, iclass 28, count 2 2006.225.07:42:50.39#ibcon#end of sib2, iclass 28, count 2 2006.225.07:42:50.39#ibcon#*after write, iclass 28, count 2 2006.225.07:42:50.39#ibcon#*before return 0, iclass 28, count 2 2006.225.07:42:50.39#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:42:50.39#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:42:50.39#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.07:42:50.39#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:50.39#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:42:50.51#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:42:50.51#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:42:50.51#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:42:50.51#ibcon#first serial, iclass 28, count 0 2006.225.07:42:50.51#ibcon#enter sib2, iclass 28, count 0 2006.225.07:42:50.51#ibcon#flushed, iclass 28, count 0 2006.225.07:42:50.51#ibcon#about to write, iclass 28, count 0 2006.225.07:42:50.51#ibcon#wrote, iclass 28, count 0 2006.225.07:42:50.51#ibcon#about to read 3, iclass 28, count 0 2006.225.07:42:50.53#ibcon#read 3, iclass 28, count 0 2006.225.07:42:50.53#ibcon#about to read 4, iclass 28, count 0 2006.225.07:42:50.53#ibcon#read 4, iclass 28, count 0 2006.225.07:42:50.53#ibcon#about to read 5, iclass 28, count 0 2006.225.07:42:50.53#ibcon#read 5, iclass 28, count 0 2006.225.07:42:50.53#ibcon#about to read 6, iclass 28, count 0 2006.225.07:42:50.53#ibcon#read 6, iclass 28, count 0 2006.225.07:42:50.53#ibcon#end of sib2, iclass 28, count 0 2006.225.07:42:50.53#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:42:50.53#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:42:50.53#ibcon#[25=USB\r\n] 2006.225.07:42:50.53#ibcon#*before write, iclass 28, count 0 2006.225.07:42:50.53#ibcon#enter sib2, iclass 28, count 0 2006.225.07:42:50.53#ibcon#flushed, iclass 28, count 0 2006.225.07:42:50.53#ibcon#about to write, iclass 28, count 0 2006.225.07:42:50.53#ibcon#wrote, iclass 28, count 0 2006.225.07:42:50.53#ibcon#about to read 3, iclass 28, count 0 2006.225.07:42:50.56#ibcon#read 3, iclass 28, count 0 2006.225.07:42:50.56#ibcon#about to read 4, iclass 28, count 0 2006.225.07:42:50.56#ibcon#read 4, iclass 28, count 0 2006.225.07:42:50.56#ibcon#about to read 5, iclass 28, count 0 2006.225.07:42:50.56#ibcon#read 5, iclass 28, count 0 2006.225.07:42:50.56#ibcon#about to read 6, iclass 28, count 0 2006.225.07:42:50.56#ibcon#read 6, iclass 28, count 0 2006.225.07:42:50.56#ibcon#end of sib2, iclass 28, count 0 2006.225.07:42:50.56#ibcon#*after write, iclass 28, count 0 2006.225.07:42:50.56#ibcon#*before return 0, iclass 28, count 0 2006.225.07:42:50.56#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:42:50.56#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:42:50.56#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:42:50.56#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:42:50.56$vc4f8/vblo=1,632.99 2006.225.07:42:50.56#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.07:42:50.56#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.07:42:50.56#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:50.56#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:42:50.56#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:42:50.56#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:42:50.56#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:42:50.56#ibcon#first serial, iclass 30, count 0 2006.225.07:42:50.56#ibcon#enter sib2, iclass 30, count 0 2006.225.07:42:50.56#ibcon#flushed, iclass 30, count 0 2006.225.07:42:50.56#ibcon#about to write, iclass 30, count 0 2006.225.07:42:50.56#ibcon#wrote, iclass 30, count 0 2006.225.07:42:50.56#ibcon#about to read 3, iclass 30, count 0 2006.225.07:42:50.59#ibcon#read 3, iclass 30, count 0 2006.225.07:42:50.59#ibcon#about to read 4, iclass 30, count 0 2006.225.07:42:50.59#ibcon#read 4, iclass 30, count 0 2006.225.07:42:50.59#ibcon#about to read 5, iclass 30, count 0 2006.225.07:42:50.59#ibcon#read 5, iclass 30, count 0 2006.225.07:42:50.59#ibcon#about to read 6, iclass 30, count 0 2006.225.07:42:50.59#ibcon#read 6, iclass 30, count 0 2006.225.07:42:50.59#ibcon#end of sib2, iclass 30, count 0 2006.225.07:42:50.59#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:42:50.59#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:42:50.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:42:50.59#ibcon#*before write, iclass 30, count 0 2006.225.07:42:50.59#ibcon#enter sib2, iclass 30, count 0 2006.225.07:42:50.59#ibcon#flushed, iclass 30, count 0 2006.225.07:42:50.59#ibcon#about to write, iclass 30, count 0 2006.225.07:42:50.59#ibcon#wrote, iclass 30, count 0 2006.225.07:42:50.59#ibcon#about to read 3, iclass 30, count 0 2006.225.07:42:50.63#ibcon#read 3, iclass 30, count 0 2006.225.07:42:50.63#ibcon#about to read 4, iclass 30, count 0 2006.225.07:42:50.63#ibcon#read 4, iclass 30, count 0 2006.225.07:42:50.63#ibcon#about to read 5, iclass 30, count 0 2006.225.07:42:50.63#ibcon#read 5, iclass 30, count 0 2006.225.07:42:50.63#ibcon#about to read 6, iclass 30, count 0 2006.225.07:42:50.63#ibcon#read 6, iclass 30, count 0 2006.225.07:42:50.63#ibcon#end of sib2, iclass 30, count 0 2006.225.07:42:50.63#ibcon#*after write, iclass 30, count 0 2006.225.07:42:50.63#ibcon#*before return 0, iclass 30, count 0 2006.225.07:42:50.63#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:42:50.63#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:42:50.63#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:42:50.63#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:42:50.63$vc4f8/vb=1,4 2006.225.07:42:50.63#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.225.07:42:50.63#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.225.07:42:50.63#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:50.63#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:42:50.63#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:42:50.63#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:42:50.63#ibcon#enter wrdev, iclass 32, count 2 2006.225.07:42:50.63#ibcon#first serial, iclass 32, count 2 2006.225.07:42:50.63#ibcon#enter sib2, iclass 32, count 2 2006.225.07:42:50.63#ibcon#flushed, iclass 32, count 2 2006.225.07:42:50.63#ibcon#about to write, iclass 32, count 2 2006.225.07:42:50.63#ibcon#wrote, iclass 32, count 2 2006.225.07:42:50.63#ibcon#about to read 3, iclass 32, count 2 2006.225.07:42:50.65#ibcon#read 3, iclass 32, count 2 2006.225.07:42:50.65#ibcon#about to read 4, iclass 32, count 2 2006.225.07:42:50.65#ibcon#read 4, iclass 32, count 2 2006.225.07:42:50.65#ibcon#about to read 5, iclass 32, count 2 2006.225.07:42:50.65#ibcon#read 5, iclass 32, count 2 2006.225.07:42:50.65#ibcon#about to read 6, iclass 32, count 2 2006.225.07:42:50.65#ibcon#read 6, iclass 32, count 2 2006.225.07:42:50.65#ibcon#end of sib2, iclass 32, count 2 2006.225.07:42:50.65#ibcon#*mode == 0, iclass 32, count 2 2006.225.07:42:50.65#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.225.07:42:50.65#ibcon#[27=AT01-04\r\n] 2006.225.07:42:50.65#ibcon#*before write, iclass 32, count 2 2006.225.07:42:50.65#ibcon#enter sib2, iclass 32, count 2 2006.225.07:42:50.65#ibcon#flushed, iclass 32, count 2 2006.225.07:42:50.65#ibcon#about to write, iclass 32, count 2 2006.225.07:42:50.65#ibcon#wrote, iclass 32, count 2 2006.225.07:42:50.65#ibcon#about to read 3, iclass 32, count 2 2006.225.07:42:50.68#ibcon#read 3, iclass 32, count 2 2006.225.07:42:50.68#ibcon#about to read 4, iclass 32, count 2 2006.225.07:42:50.68#ibcon#read 4, iclass 32, count 2 2006.225.07:42:50.68#ibcon#about to read 5, iclass 32, count 2 2006.225.07:42:50.68#ibcon#read 5, iclass 32, count 2 2006.225.07:42:50.68#ibcon#about to read 6, iclass 32, count 2 2006.225.07:42:50.68#ibcon#read 6, iclass 32, count 2 2006.225.07:42:50.68#ibcon#end of sib2, iclass 32, count 2 2006.225.07:42:50.68#ibcon#*after write, iclass 32, count 2 2006.225.07:42:50.68#ibcon#*before return 0, iclass 32, count 2 2006.225.07:42:50.68#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:42:50.68#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:42:50.68#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.225.07:42:50.68#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:50.68#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:42:50.80#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:42:50.80#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:42:50.80#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:42:50.80#ibcon#first serial, iclass 32, count 0 2006.225.07:42:50.80#ibcon#enter sib2, iclass 32, count 0 2006.225.07:42:50.80#ibcon#flushed, iclass 32, count 0 2006.225.07:42:50.80#ibcon#about to write, iclass 32, count 0 2006.225.07:42:50.80#ibcon#wrote, iclass 32, count 0 2006.225.07:42:50.80#ibcon#about to read 3, iclass 32, count 0 2006.225.07:42:50.82#ibcon#read 3, iclass 32, count 0 2006.225.07:42:50.82#ibcon#about to read 4, iclass 32, count 0 2006.225.07:42:50.82#ibcon#read 4, iclass 32, count 0 2006.225.07:42:50.82#ibcon#about to read 5, iclass 32, count 0 2006.225.07:42:50.82#ibcon#read 5, iclass 32, count 0 2006.225.07:42:50.82#ibcon#about to read 6, iclass 32, count 0 2006.225.07:42:50.82#ibcon#read 6, iclass 32, count 0 2006.225.07:42:50.82#ibcon#end of sib2, iclass 32, count 0 2006.225.07:42:50.82#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:42:50.82#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:42:50.82#ibcon#[27=USB\r\n] 2006.225.07:42:50.82#ibcon#*before write, iclass 32, count 0 2006.225.07:42:50.82#ibcon#enter sib2, iclass 32, count 0 2006.225.07:42:50.82#ibcon#flushed, iclass 32, count 0 2006.225.07:42:50.82#ibcon#about to write, iclass 32, count 0 2006.225.07:42:50.82#ibcon#wrote, iclass 32, count 0 2006.225.07:42:50.82#ibcon#about to read 3, iclass 32, count 0 2006.225.07:42:50.85#ibcon#read 3, iclass 32, count 0 2006.225.07:42:50.85#ibcon#about to read 4, iclass 32, count 0 2006.225.07:42:50.85#ibcon#read 4, iclass 32, count 0 2006.225.07:42:50.85#ibcon#about to read 5, iclass 32, count 0 2006.225.07:42:50.85#ibcon#read 5, iclass 32, count 0 2006.225.07:42:50.85#ibcon#about to read 6, iclass 32, count 0 2006.225.07:42:50.85#ibcon#read 6, iclass 32, count 0 2006.225.07:42:50.85#ibcon#end of sib2, iclass 32, count 0 2006.225.07:42:50.85#ibcon#*after write, iclass 32, count 0 2006.225.07:42:50.85#ibcon#*before return 0, iclass 32, count 0 2006.225.07:42:50.85#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:42:50.85#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:42:50.85#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:42:50.85#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:42:50.85$vc4f8/vblo=2,640.99 2006.225.07:42:50.85#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.07:42:50.85#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.07:42:50.85#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:50.85#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:42:50.85#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:42:50.85#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:42:50.85#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:42:50.85#ibcon#first serial, iclass 34, count 0 2006.225.07:42:50.85#ibcon#enter sib2, iclass 34, count 0 2006.225.07:42:50.85#ibcon#flushed, iclass 34, count 0 2006.225.07:42:50.85#ibcon#about to write, iclass 34, count 0 2006.225.07:42:50.85#ibcon#wrote, iclass 34, count 0 2006.225.07:42:50.85#ibcon#about to read 3, iclass 34, count 0 2006.225.07:42:50.87#ibcon#read 3, iclass 34, count 0 2006.225.07:42:50.87#ibcon#about to read 4, iclass 34, count 0 2006.225.07:42:50.87#ibcon#read 4, iclass 34, count 0 2006.225.07:42:50.87#ibcon#about to read 5, iclass 34, count 0 2006.225.07:42:50.87#ibcon#read 5, iclass 34, count 0 2006.225.07:42:50.87#ibcon#about to read 6, iclass 34, count 0 2006.225.07:42:50.87#ibcon#read 6, iclass 34, count 0 2006.225.07:42:50.87#ibcon#end of sib2, iclass 34, count 0 2006.225.07:42:50.87#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:42:50.87#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:42:50.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:42:50.87#ibcon#*before write, iclass 34, count 0 2006.225.07:42:50.87#ibcon#enter sib2, iclass 34, count 0 2006.225.07:42:50.87#ibcon#flushed, iclass 34, count 0 2006.225.07:42:50.87#ibcon#about to write, iclass 34, count 0 2006.225.07:42:50.87#ibcon#wrote, iclass 34, count 0 2006.225.07:42:50.87#ibcon#about to read 3, iclass 34, count 0 2006.225.07:42:50.91#ibcon#read 3, iclass 34, count 0 2006.225.07:42:50.91#ibcon#about to read 4, iclass 34, count 0 2006.225.07:42:50.91#ibcon#read 4, iclass 34, count 0 2006.225.07:42:50.91#ibcon#about to read 5, iclass 34, count 0 2006.225.07:42:50.91#ibcon#read 5, iclass 34, count 0 2006.225.07:42:50.91#ibcon#about to read 6, iclass 34, count 0 2006.225.07:42:50.91#ibcon#read 6, iclass 34, count 0 2006.225.07:42:50.91#ibcon#end of sib2, iclass 34, count 0 2006.225.07:42:50.91#ibcon#*after write, iclass 34, count 0 2006.225.07:42:50.91#ibcon#*before return 0, iclass 34, count 0 2006.225.07:42:50.91#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:42:50.91#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:42:50.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:42:50.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:42:50.91$vc4f8/vb=2,4 2006.225.07:42:50.91#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.07:42:50.91#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.07:42:50.91#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:50.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:42:50.97#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:42:50.97#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:42:50.97#ibcon#enter wrdev, iclass 36, count 2 2006.225.07:42:50.97#ibcon#first serial, iclass 36, count 2 2006.225.07:42:50.97#ibcon#enter sib2, iclass 36, count 2 2006.225.07:42:50.97#ibcon#flushed, iclass 36, count 2 2006.225.07:42:50.97#ibcon#about to write, iclass 36, count 2 2006.225.07:42:50.97#ibcon#wrote, iclass 36, count 2 2006.225.07:42:50.97#ibcon#about to read 3, iclass 36, count 2 2006.225.07:42:50.99#ibcon#read 3, iclass 36, count 2 2006.225.07:42:50.99#ibcon#about to read 4, iclass 36, count 2 2006.225.07:42:50.99#ibcon#read 4, iclass 36, count 2 2006.225.07:42:50.99#ibcon#about to read 5, iclass 36, count 2 2006.225.07:42:50.99#ibcon#read 5, iclass 36, count 2 2006.225.07:42:50.99#ibcon#about to read 6, iclass 36, count 2 2006.225.07:42:50.99#ibcon#read 6, iclass 36, count 2 2006.225.07:42:50.99#ibcon#end of sib2, iclass 36, count 2 2006.225.07:42:50.99#ibcon#*mode == 0, iclass 36, count 2 2006.225.07:42:50.99#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.07:42:50.99#ibcon#[27=AT02-04\r\n] 2006.225.07:42:50.99#ibcon#*before write, iclass 36, count 2 2006.225.07:42:50.99#ibcon#enter sib2, iclass 36, count 2 2006.225.07:42:50.99#ibcon#flushed, iclass 36, count 2 2006.225.07:42:50.99#ibcon#about to write, iclass 36, count 2 2006.225.07:42:50.99#ibcon#wrote, iclass 36, count 2 2006.225.07:42:50.99#ibcon#about to read 3, iclass 36, count 2 2006.225.07:42:51.02#ibcon#read 3, iclass 36, count 2 2006.225.07:42:51.02#ibcon#about to read 4, iclass 36, count 2 2006.225.07:42:51.02#ibcon#read 4, iclass 36, count 2 2006.225.07:42:51.02#ibcon#about to read 5, iclass 36, count 2 2006.225.07:42:51.02#ibcon#read 5, iclass 36, count 2 2006.225.07:42:51.02#ibcon#about to read 6, iclass 36, count 2 2006.225.07:42:51.02#ibcon#read 6, iclass 36, count 2 2006.225.07:42:51.02#ibcon#end of sib2, iclass 36, count 2 2006.225.07:42:51.02#ibcon#*after write, iclass 36, count 2 2006.225.07:42:51.02#ibcon#*before return 0, iclass 36, count 2 2006.225.07:42:51.02#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:42:51.02#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:42:51.02#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.07:42:51.02#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:51.02#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:42:51.14#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:42:51.14#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:42:51.14#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:42:51.14#ibcon#first serial, iclass 36, count 0 2006.225.07:42:51.14#ibcon#enter sib2, iclass 36, count 0 2006.225.07:42:51.14#ibcon#flushed, iclass 36, count 0 2006.225.07:42:51.14#ibcon#about to write, iclass 36, count 0 2006.225.07:42:51.14#ibcon#wrote, iclass 36, count 0 2006.225.07:42:51.14#ibcon#about to read 3, iclass 36, count 0 2006.225.07:42:51.16#ibcon#read 3, iclass 36, count 0 2006.225.07:42:51.16#ibcon#about to read 4, iclass 36, count 0 2006.225.07:42:51.16#ibcon#read 4, iclass 36, count 0 2006.225.07:42:51.16#ibcon#about to read 5, iclass 36, count 0 2006.225.07:42:51.16#ibcon#read 5, iclass 36, count 0 2006.225.07:42:51.16#ibcon#about to read 6, iclass 36, count 0 2006.225.07:42:51.16#ibcon#read 6, iclass 36, count 0 2006.225.07:42:51.16#ibcon#end of sib2, iclass 36, count 0 2006.225.07:42:51.16#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:42:51.16#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:42:51.16#ibcon#[27=USB\r\n] 2006.225.07:42:51.16#ibcon#*before write, iclass 36, count 0 2006.225.07:42:51.16#ibcon#enter sib2, iclass 36, count 0 2006.225.07:42:51.16#ibcon#flushed, iclass 36, count 0 2006.225.07:42:51.16#ibcon#about to write, iclass 36, count 0 2006.225.07:42:51.16#ibcon#wrote, iclass 36, count 0 2006.225.07:42:51.16#ibcon#about to read 3, iclass 36, count 0 2006.225.07:42:51.19#ibcon#read 3, iclass 36, count 0 2006.225.07:42:51.19#ibcon#about to read 4, iclass 36, count 0 2006.225.07:42:51.19#ibcon#read 4, iclass 36, count 0 2006.225.07:42:51.19#ibcon#about to read 5, iclass 36, count 0 2006.225.07:42:51.19#ibcon#read 5, iclass 36, count 0 2006.225.07:42:51.19#ibcon#about to read 6, iclass 36, count 0 2006.225.07:42:51.19#ibcon#read 6, iclass 36, count 0 2006.225.07:42:51.19#ibcon#end of sib2, iclass 36, count 0 2006.225.07:42:51.19#ibcon#*after write, iclass 36, count 0 2006.225.07:42:51.19#ibcon#*before return 0, iclass 36, count 0 2006.225.07:42:51.19#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:42:51.19#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:42:51.19#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:42:51.19#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:42:51.19$vc4f8/vblo=3,656.99 2006.225.07:42:51.19#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.07:42:51.19#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.07:42:51.19#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:51.19#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:42:51.19#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:42:51.19#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:42:51.19#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:42:51.19#ibcon#first serial, iclass 38, count 0 2006.225.07:42:51.19#ibcon#enter sib2, iclass 38, count 0 2006.225.07:42:51.19#ibcon#flushed, iclass 38, count 0 2006.225.07:42:51.19#ibcon#about to write, iclass 38, count 0 2006.225.07:42:51.19#ibcon#wrote, iclass 38, count 0 2006.225.07:42:51.19#ibcon#about to read 3, iclass 38, count 0 2006.225.07:42:51.21#ibcon#read 3, iclass 38, count 0 2006.225.07:42:51.21#ibcon#about to read 4, iclass 38, count 0 2006.225.07:42:51.21#ibcon#read 4, iclass 38, count 0 2006.225.07:42:51.21#ibcon#about to read 5, iclass 38, count 0 2006.225.07:42:51.21#ibcon#read 5, iclass 38, count 0 2006.225.07:42:51.21#ibcon#about to read 6, iclass 38, count 0 2006.225.07:42:51.21#ibcon#read 6, iclass 38, count 0 2006.225.07:42:51.21#ibcon#end of sib2, iclass 38, count 0 2006.225.07:42:51.21#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:42:51.21#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:42:51.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:42:51.21#ibcon#*before write, iclass 38, count 0 2006.225.07:42:51.21#ibcon#enter sib2, iclass 38, count 0 2006.225.07:42:51.21#ibcon#flushed, iclass 38, count 0 2006.225.07:42:51.21#ibcon#about to write, iclass 38, count 0 2006.225.07:42:51.21#ibcon#wrote, iclass 38, count 0 2006.225.07:42:51.21#ibcon#about to read 3, iclass 38, count 0 2006.225.07:42:51.25#ibcon#read 3, iclass 38, count 0 2006.225.07:42:51.25#ibcon#about to read 4, iclass 38, count 0 2006.225.07:42:51.25#ibcon#read 4, iclass 38, count 0 2006.225.07:42:51.25#ibcon#about to read 5, iclass 38, count 0 2006.225.07:42:51.25#ibcon#read 5, iclass 38, count 0 2006.225.07:42:51.25#ibcon#about to read 6, iclass 38, count 0 2006.225.07:42:51.25#ibcon#read 6, iclass 38, count 0 2006.225.07:42:51.25#ibcon#end of sib2, iclass 38, count 0 2006.225.07:42:51.25#ibcon#*after write, iclass 38, count 0 2006.225.07:42:51.25#ibcon#*before return 0, iclass 38, count 0 2006.225.07:42:51.25#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:42:51.25#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:42:51.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:42:51.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:42:51.25$vc4f8/vb=3,4 2006.225.07:42:51.25#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.225.07:42:51.25#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.225.07:42:51.25#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:51.25#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:42:51.31#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:42:51.31#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:42:51.31#ibcon#enter wrdev, iclass 40, count 2 2006.225.07:42:51.31#ibcon#first serial, iclass 40, count 2 2006.225.07:42:51.31#ibcon#enter sib2, iclass 40, count 2 2006.225.07:42:51.31#ibcon#flushed, iclass 40, count 2 2006.225.07:42:51.31#ibcon#about to write, iclass 40, count 2 2006.225.07:42:51.31#ibcon#wrote, iclass 40, count 2 2006.225.07:42:51.31#ibcon#about to read 3, iclass 40, count 2 2006.225.07:42:51.33#ibcon#read 3, iclass 40, count 2 2006.225.07:42:51.33#ibcon#about to read 4, iclass 40, count 2 2006.225.07:42:51.33#ibcon#read 4, iclass 40, count 2 2006.225.07:42:51.33#ibcon#about to read 5, iclass 40, count 2 2006.225.07:42:51.33#ibcon#read 5, iclass 40, count 2 2006.225.07:42:51.33#ibcon#about to read 6, iclass 40, count 2 2006.225.07:42:51.33#ibcon#read 6, iclass 40, count 2 2006.225.07:42:51.33#ibcon#end of sib2, iclass 40, count 2 2006.225.07:42:51.33#ibcon#*mode == 0, iclass 40, count 2 2006.225.07:42:51.33#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.225.07:42:51.33#ibcon#[27=AT03-04\r\n] 2006.225.07:42:51.33#ibcon#*before write, iclass 40, count 2 2006.225.07:42:51.33#ibcon#enter sib2, iclass 40, count 2 2006.225.07:42:51.33#ibcon#flushed, iclass 40, count 2 2006.225.07:42:51.33#ibcon#about to write, iclass 40, count 2 2006.225.07:42:51.33#ibcon#wrote, iclass 40, count 2 2006.225.07:42:51.33#ibcon#about to read 3, iclass 40, count 2 2006.225.07:42:51.36#ibcon#read 3, iclass 40, count 2 2006.225.07:42:51.36#ibcon#about to read 4, iclass 40, count 2 2006.225.07:42:51.36#ibcon#read 4, iclass 40, count 2 2006.225.07:42:51.36#ibcon#about to read 5, iclass 40, count 2 2006.225.07:42:51.36#ibcon#read 5, iclass 40, count 2 2006.225.07:42:51.36#ibcon#about to read 6, iclass 40, count 2 2006.225.07:42:51.36#ibcon#read 6, iclass 40, count 2 2006.225.07:42:51.36#ibcon#end of sib2, iclass 40, count 2 2006.225.07:42:51.36#ibcon#*after write, iclass 40, count 2 2006.225.07:42:51.36#ibcon#*before return 0, iclass 40, count 2 2006.225.07:42:51.36#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:42:51.36#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:42:51.36#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.225.07:42:51.36#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:51.36#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:42:51.48#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:42:51.48#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:42:51.48#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:42:51.48#ibcon#first serial, iclass 40, count 0 2006.225.07:42:51.48#ibcon#enter sib2, iclass 40, count 0 2006.225.07:42:51.48#ibcon#flushed, iclass 40, count 0 2006.225.07:42:51.48#ibcon#about to write, iclass 40, count 0 2006.225.07:42:51.48#ibcon#wrote, iclass 40, count 0 2006.225.07:42:51.48#ibcon#about to read 3, iclass 40, count 0 2006.225.07:42:51.50#ibcon#read 3, iclass 40, count 0 2006.225.07:42:51.50#ibcon#about to read 4, iclass 40, count 0 2006.225.07:42:51.50#ibcon#read 4, iclass 40, count 0 2006.225.07:42:51.50#ibcon#about to read 5, iclass 40, count 0 2006.225.07:42:51.50#ibcon#read 5, iclass 40, count 0 2006.225.07:42:51.50#ibcon#about to read 6, iclass 40, count 0 2006.225.07:42:51.50#ibcon#read 6, iclass 40, count 0 2006.225.07:42:51.50#ibcon#end of sib2, iclass 40, count 0 2006.225.07:42:51.50#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:42:51.50#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:42:51.50#ibcon#[27=USB\r\n] 2006.225.07:42:51.50#ibcon#*before write, iclass 40, count 0 2006.225.07:42:51.50#ibcon#enter sib2, iclass 40, count 0 2006.225.07:42:51.50#ibcon#flushed, iclass 40, count 0 2006.225.07:42:51.50#ibcon#about to write, iclass 40, count 0 2006.225.07:42:51.50#ibcon#wrote, iclass 40, count 0 2006.225.07:42:51.50#ibcon#about to read 3, iclass 40, count 0 2006.225.07:42:51.53#ibcon#read 3, iclass 40, count 0 2006.225.07:42:51.53#ibcon#about to read 4, iclass 40, count 0 2006.225.07:42:51.53#ibcon#read 4, iclass 40, count 0 2006.225.07:42:51.53#ibcon#about to read 5, iclass 40, count 0 2006.225.07:42:51.53#ibcon#read 5, iclass 40, count 0 2006.225.07:42:51.53#ibcon#about to read 6, iclass 40, count 0 2006.225.07:42:51.53#ibcon#read 6, iclass 40, count 0 2006.225.07:42:51.53#ibcon#end of sib2, iclass 40, count 0 2006.225.07:42:51.53#ibcon#*after write, iclass 40, count 0 2006.225.07:42:51.53#ibcon#*before return 0, iclass 40, count 0 2006.225.07:42:51.53#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:42:51.53#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:42:51.53#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:42:51.53#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:42:51.53$vc4f8/vblo=4,712.99 2006.225.07:42:51.53#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.07:42:51.53#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.07:42:51.53#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:51.53#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:42:51.53#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:42:51.53#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:42:51.53#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:42:51.53#ibcon#first serial, iclass 4, count 0 2006.225.07:42:51.53#ibcon#enter sib2, iclass 4, count 0 2006.225.07:42:51.53#ibcon#flushed, iclass 4, count 0 2006.225.07:42:51.53#ibcon#about to write, iclass 4, count 0 2006.225.07:42:51.53#ibcon#wrote, iclass 4, count 0 2006.225.07:42:51.53#ibcon#about to read 3, iclass 4, count 0 2006.225.07:42:51.55#ibcon#read 3, iclass 4, count 0 2006.225.07:42:51.55#ibcon#about to read 4, iclass 4, count 0 2006.225.07:42:51.55#ibcon#read 4, iclass 4, count 0 2006.225.07:42:51.55#ibcon#about to read 5, iclass 4, count 0 2006.225.07:42:51.55#ibcon#read 5, iclass 4, count 0 2006.225.07:42:51.55#ibcon#about to read 6, iclass 4, count 0 2006.225.07:42:51.55#ibcon#read 6, iclass 4, count 0 2006.225.07:42:51.55#ibcon#end of sib2, iclass 4, count 0 2006.225.07:42:51.55#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:42:51.55#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:42:51.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:42:51.55#ibcon#*before write, iclass 4, count 0 2006.225.07:42:51.55#ibcon#enter sib2, iclass 4, count 0 2006.225.07:42:51.55#ibcon#flushed, iclass 4, count 0 2006.225.07:42:51.55#ibcon#about to write, iclass 4, count 0 2006.225.07:42:51.55#ibcon#wrote, iclass 4, count 0 2006.225.07:42:51.55#ibcon#about to read 3, iclass 4, count 0 2006.225.07:42:51.59#ibcon#read 3, iclass 4, count 0 2006.225.07:42:51.59#ibcon#about to read 4, iclass 4, count 0 2006.225.07:42:51.59#ibcon#read 4, iclass 4, count 0 2006.225.07:42:51.59#ibcon#about to read 5, iclass 4, count 0 2006.225.07:42:51.59#ibcon#read 5, iclass 4, count 0 2006.225.07:42:51.59#ibcon#about to read 6, iclass 4, count 0 2006.225.07:42:51.59#ibcon#read 6, iclass 4, count 0 2006.225.07:42:51.59#ibcon#end of sib2, iclass 4, count 0 2006.225.07:42:51.59#ibcon#*after write, iclass 4, count 0 2006.225.07:42:51.59#ibcon#*before return 0, iclass 4, count 0 2006.225.07:42:51.59#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:42:51.59#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:42:51.59#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:42:51.59#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:42:51.59$vc4f8/vb=4,4 2006.225.07:42:51.59#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.225.07:42:51.59#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.225.07:42:51.59#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:51.59#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:42:51.65#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:42:51.65#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:42:51.65#ibcon#enter wrdev, iclass 6, count 2 2006.225.07:42:51.65#ibcon#first serial, iclass 6, count 2 2006.225.07:42:51.65#ibcon#enter sib2, iclass 6, count 2 2006.225.07:42:51.65#ibcon#flushed, iclass 6, count 2 2006.225.07:42:51.65#ibcon#about to write, iclass 6, count 2 2006.225.07:42:51.65#ibcon#wrote, iclass 6, count 2 2006.225.07:42:51.65#ibcon#about to read 3, iclass 6, count 2 2006.225.07:42:51.67#ibcon#read 3, iclass 6, count 2 2006.225.07:42:51.67#ibcon#about to read 4, iclass 6, count 2 2006.225.07:42:51.67#ibcon#read 4, iclass 6, count 2 2006.225.07:42:51.67#ibcon#about to read 5, iclass 6, count 2 2006.225.07:42:51.67#ibcon#read 5, iclass 6, count 2 2006.225.07:42:51.67#ibcon#about to read 6, iclass 6, count 2 2006.225.07:42:51.67#ibcon#read 6, iclass 6, count 2 2006.225.07:42:51.67#ibcon#end of sib2, iclass 6, count 2 2006.225.07:42:51.67#ibcon#*mode == 0, iclass 6, count 2 2006.225.07:42:51.67#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.225.07:42:51.67#ibcon#[27=AT04-04\r\n] 2006.225.07:42:51.67#ibcon#*before write, iclass 6, count 2 2006.225.07:42:51.67#ibcon#enter sib2, iclass 6, count 2 2006.225.07:42:51.67#ibcon#flushed, iclass 6, count 2 2006.225.07:42:51.67#ibcon#about to write, iclass 6, count 2 2006.225.07:42:51.67#ibcon#wrote, iclass 6, count 2 2006.225.07:42:51.67#ibcon#about to read 3, iclass 6, count 2 2006.225.07:42:51.70#ibcon#read 3, iclass 6, count 2 2006.225.07:42:51.70#ibcon#about to read 4, iclass 6, count 2 2006.225.07:42:51.70#ibcon#read 4, iclass 6, count 2 2006.225.07:42:51.70#ibcon#about to read 5, iclass 6, count 2 2006.225.07:42:51.70#ibcon#read 5, iclass 6, count 2 2006.225.07:42:51.70#ibcon#about to read 6, iclass 6, count 2 2006.225.07:42:51.70#ibcon#read 6, iclass 6, count 2 2006.225.07:42:51.70#ibcon#end of sib2, iclass 6, count 2 2006.225.07:42:51.70#ibcon#*after write, iclass 6, count 2 2006.225.07:42:51.70#ibcon#*before return 0, iclass 6, count 2 2006.225.07:42:51.70#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:42:51.70#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:42:51.70#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.225.07:42:51.70#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:51.70#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:42:51.82#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:42:51.82#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:42:51.82#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:42:51.82#ibcon#first serial, iclass 6, count 0 2006.225.07:42:51.82#ibcon#enter sib2, iclass 6, count 0 2006.225.07:42:51.82#ibcon#flushed, iclass 6, count 0 2006.225.07:42:51.82#ibcon#about to write, iclass 6, count 0 2006.225.07:42:51.82#ibcon#wrote, iclass 6, count 0 2006.225.07:42:51.82#ibcon#about to read 3, iclass 6, count 0 2006.225.07:42:51.84#ibcon#read 3, iclass 6, count 0 2006.225.07:42:51.84#ibcon#about to read 4, iclass 6, count 0 2006.225.07:42:51.84#ibcon#read 4, iclass 6, count 0 2006.225.07:42:51.84#ibcon#about to read 5, iclass 6, count 0 2006.225.07:42:51.84#ibcon#read 5, iclass 6, count 0 2006.225.07:42:51.84#ibcon#about to read 6, iclass 6, count 0 2006.225.07:42:51.84#ibcon#read 6, iclass 6, count 0 2006.225.07:42:51.84#ibcon#end of sib2, iclass 6, count 0 2006.225.07:42:51.84#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:42:51.84#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:42:51.84#ibcon#[27=USB\r\n] 2006.225.07:42:51.84#ibcon#*before write, iclass 6, count 0 2006.225.07:42:51.84#ibcon#enter sib2, iclass 6, count 0 2006.225.07:42:51.84#ibcon#flushed, iclass 6, count 0 2006.225.07:42:51.84#ibcon#about to write, iclass 6, count 0 2006.225.07:42:51.84#ibcon#wrote, iclass 6, count 0 2006.225.07:42:51.84#ibcon#about to read 3, iclass 6, count 0 2006.225.07:42:51.87#ibcon#read 3, iclass 6, count 0 2006.225.07:42:51.87#ibcon#about to read 4, iclass 6, count 0 2006.225.07:42:51.87#ibcon#read 4, iclass 6, count 0 2006.225.07:42:51.87#ibcon#about to read 5, iclass 6, count 0 2006.225.07:42:51.87#ibcon#read 5, iclass 6, count 0 2006.225.07:42:51.87#ibcon#about to read 6, iclass 6, count 0 2006.225.07:42:51.87#ibcon#read 6, iclass 6, count 0 2006.225.07:42:51.87#ibcon#end of sib2, iclass 6, count 0 2006.225.07:42:51.87#ibcon#*after write, iclass 6, count 0 2006.225.07:42:51.87#ibcon#*before return 0, iclass 6, count 0 2006.225.07:42:51.87#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:42:51.87#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:42:51.87#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:42:51.87#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:42:51.87$vc4f8/vblo=5,744.99 2006.225.07:42:51.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.07:42:51.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.07:42:51.87#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:51.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:42:51.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:42:51.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:42:51.87#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:42:51.87#ibcon#first serial, iclass 10, count 0 2006.225.07:42:51.87#ibcon#enter sib2, iclass 10, count 0 2006.225.07:42:51.87#ibcon#flushed, iclass 10, count 0 2006.225.07:42:51.87#ibcon#about to write, iclass 10, count 0 2006.225.07:42:51.87#ibcon#wrote, iclass 10, count 0 2006.225.07:42:51.87#ibcon#about to read 3, iclass 10, count 0 2006.225.07:42:51.89#ibcon#read 3, iclass 10, count 0 2006.225.07:42:51.89#ibcon#about to read 4, iclass 10, count 0 2006.225.07:42:51.89#ibcon#read 4, iclass 10, count 0 2006.225.07:42:51.89#ibcon#about to read 5, iclass 10, count 0 2006.225.07:42:51.89#ibcon#read 5, iclass 10, count 0 2006.225.07:42:51.89#ibcon#about to read 6, iclass 10, count 0 2006.225.07:42:51.89#ibcon#read 6, iclass 10, count 0 2006.225.07:42:51.89#ibcon#end of sib2, iclass 10, count 0 2006.225.07:42:51.89#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:42:51.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:42:51.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:42:51.89#ibcon#*before write, iclass 10, count 0 2006.225.07:42:51.89#ibcon#enter sib2, iclass 10, count 0 2006.225.07:42:51.89#ibcon#flushed, iclass 10, count 0 2006.225.07:42:51.89#ibcon#about to write, iclass 10, count 0 2006.225.07:42:51.89#ibcon#wrote, iclass 10, count 0 2006.225.07:42:51.89#ibcon#about to read 3, iclass 10, count 0 2006.225.07:42:51.93#ibcon#read 3, iclass 10, count 0 2006.225.07:42:51.93#ibcon#about to read 4, iclass 10, count 0 2006.225.07:42:51.93#ibcon#read 4, iclass 10, count 0 2006.225.07:42:51.93#ibcon#about to read 5, iclass 10, count 0 2006.225.07:42:51.93#ibcon#read 5, iclass 10, count 0 2006.225.07:42:51.93#ibcon#about to read 6, iclass 10, count 0 2006.225.07:42:51.93#ibcon#read 6, iclass 10, count 0 2006.225.07:42:51.93#ibcon#end of sib2, iclass 10, count 0 2006.225.07:42:51.93#ibcon#*after write, iclass 10, count 0 2006.225.07:42:51.93#ibcon#*before return 0, iclass 10, count 0 2006.225.07:42:51.93#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:42:51.93#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:42:51.93#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:42:51.93#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:42:51.93$vc4f8/vb=5,4 2006.225.07:42:51.93#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.07:42:51.93#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.07:42:51.93#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:51.93#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:42:51.99#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:42:51.99#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:42:51.99#ibcon#enter wrdev, iclass 12, count 2 2006.225.07:42:51.99#ibcon#first serial, iclass 12, count 2 2006.225.07:42:51.99#ibcon#enter sib2, iclass 12, count 2 2006.225.07:42:51.99#ibcon#flushed, iclass 12, count 2 2006.225.07:42:51.99#ibcon#about to write, iclass 12, count 2 2006.225.07:42:51.99#ibcon#wrote, iclass 12, count 2 2006.225.07:42:51.99#ibcon#about to read 3, iclass 12, count 2 2006.225.07:42:52.01#ibcon#read 3, iclass 12, count 2 2006.225.07:42:52.01#ibcon#about to read 4, iclass 12, count 2 2006.225.07:42:52.01#ibcon#read 4, iclass 12, count 2 2006.225.07:42:52.01#ibcon#about to read 5, iclass 12, count 2 2006.225.07:42:52.01#ibcon#read 5, iclass 12, count 2 2006.225.07:42:52.01#ibcon#about to read 6, iclass 12, count 2 2006.225.07:42:52.01#ibcon#read 6, iclass 12, count 2 2006.225.07:42:52.01#ibcon#end of sib2, iclass 12, count 2 2006.225.07:42:52.01#ibcon#*mode == 0, iclass 12, count 2 2006.225.07:42:52.01#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.07:42:52.01#ibcon#[27=AT05-04\r\n] 2006.225.07:42:52.01#ibcon#*before write, iclass 12, count 2 2006.225.07:42:52.01#ibcon#enter sib2, iclass 12, count 2 2006.225.07:42:52.01#ibcon#flushed, iclass 12, count 2 2006.225.07:42:52.01#ibcon#about to write, iclass 12, count 2 2006.225.07:42:52.01#ibcon#wrote, iclass 12, count 2 2006.225.07:42:52.01#ibcon#about to read 3, iclass 12, count 2 2006.225.07:42:52.04#ibcon#read 3, iclass 12, count 2 2006.225.07:42:52.04#ibcon#about to read 4, iclass 12, count 2 2006.225.07:42:52.04#ibcon#read 4, iclass 12, count 2 2006.225.07:42:52.04#ibcon#about to read 5, iclass 12, count 2 2006.225.07:42:52.04#ibcon#read 5, iclass 12, count 2 2006.225.07:42:52.04#ibcon#about to read 6, iclass 12, count 2 2006.225.07:42:52.04#ibcon#read 6, iclass 12, count 2 2006.225.07:42:52.04#ibcon#end of sib2, iclass 12, count 2 2006.225.07:42:52.04#ibcon#*after write, iclass 12, count 2 2006.225.07:42:52.04#ibcon#*before return 0, iclass 12, count 2 2006.225.07:42:52.04#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:42:52.04#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:42:52.04#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.07:42:52.04#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:52.04#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:42:52.16#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:42:52.16#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:42:52.16#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:42:52.16#ibcon#first serial, iclass 12, count 0 2006.225.07:42:52.16#ibcon#enter sib2, iclass 12, count 0 2006.225.07:42:52.16#ibcon#flushed, iclass 12, count 0 2006.225.07:42:52.16#ibcon#about to write, iclass 12, count 0 2006.225.07:42:52.16#ibcon#wrote, iclass 12, count 0 2006.225.07:42:52.16#ibcon#about to read 3, iclass 12, count 0 2006.225.07:42:52.18#ibcon#read 3, iclass 12, count 0 2006.225.07:42:52.18#ibcon#about to read 4, iclass 12, count 0 2006.225.07:42:52.18#ibcon#read 4, iclass 12, count 0 2006.225.07:42:52.18#ibcon#about to read 5, iclass 12, count 0 2006.225.07:42:52.18#ibcon#read 5, iclass 12, count 0 2006.225.07:42:52.18#ibcon#about to read 6, iclass 12, count 0 2006.225.07:42:52.18#ibcon#read 6, iclass 12, count 0 2006.225.07:42:52.18#ibcon#end of sib2, iclass 12, count 0 2006.225.07:42:52.18#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:42:52.18#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:42:52.18#ibcon#[27=USB\r\n] 2006.225.07:42:52.18#ibcon#*before write, iclass 12, count 0 2006.225.07:42:52.18#ibcon#enter sib2, iclass 12, count 0 2006.225.07:42:52.18#ibcon#flushed, iclass 12, count 0 2006.225.07:42:52.18#ibcon#about to write, iclass 12, count 0 2006.225.07:42:52.18#ibcon#wrote, iclass 12, count 0 2006.225.07:42:52.18#ibcon#about to read 3, iclass 12, count 0 2006.225.07:42:52.21#ibcon#read 3, iclass 12, count 0 2006.225.07:42:52.21#ibcon#about to read 4, iclass 12, count 0 2006.225.07:42:52.21#ibcon#read 4, iclass 12, count 0 2006.225.07:42:52.21#ibcon#about to read 5, iclass 12, count 0 2006.225.07:42:52.21#ibcon#read 5, iclass 12, count 0 2006.225.07:42:52.21#ibcon#about to read 6, iclass 12, count 0 2006.225.07:42:52.21#ibcon#read 6, iclass 12, count 0 2006.225.07:42:52.21#ibcon#end of sib2, iclass 12, count 0 2006.225.07:42:52.21#ibcon#*after write, iclass 12, count 0 2006.225.07:42:52.21#ibcon#*before return 0, iclass 12, count 0 2006.225.07:42:52.21#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:42:52.21#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:42:52.21#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:42:52.21#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:42:52.21$vc4f8/vblo=6,752.99 2006.225.07:42:52.21#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.07:42:52.21#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.07:42:52.21#ibcon#ireg 17 cls_cnt 0 2006.225.07:42:52.21#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:42:52.21#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:42:52.21#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:42:52.21#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:42:52.21#ibcon#first serial, iclass 14, count 0 2006.225.07:42:52.21#ibcon#enter sib2, iclass 14, count 0 2006.225.07:42:52.21#ibcon#flushed, iclass 14, count 0 2006.225.07:42:52.21#ibcon#about to write, iclass 14, count 0 2006.225.07:42:52.21#ibcon#wrote, iclass 14, count 0 2006.225.07:42:52.21#ibcon#about to read 3, iclass 14, count 0 2006.225.07:42:52.23#ibcon#read 3, iclass 14, count 0 2006.225.07:42:52.23#ibcon#about to read 4, iclass 14, count 0 2006.225.07:42:52.23#ibcon#read 4, iclass 14, count 0 2006.225.07:42:52.23#ibcon#about to read 5, iclass 14, count 0 2006.225.07:42:52.23#ibcon#read 5, iclass 14, count 0 2006.225.07:42:52.23#ibcon#about to read 6, iclass 14, count 0 2006.225.07:42:52.23#ibcon#read 6, iclass 14, count 0 2006.225.07:42:52.23#ibcon#end of sib2, iclass 14, count 0 2006.225.07:42:52.23#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:42:52.23#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:42:52.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:42:52.23#ibcon#*before write, iclass 14, count 0 2006.225.07:42:52.23#ibcon#enter sib2, iclass 14, count 0 2006.225.07:42:52.23#ibcon#flushed, iclass 14, count 0 2006.225.07:42:52.23#ibcon#about to write, iclass 14, count 0 2006.225.07:42:52.23#ibcon#wrote, iclass 14, count 0 2006.225.07:42:52.23#ibcon#about to read 3, iclass 14, count 0 2006.225.07:42:52.27#ibcon#read 3, iclass 14, count 0 2006.225.07:42:52.27#ibcon#about to read 4, iclass 14, count 0 2006.225.07:42:52.27#ibcon#read 4, iclass 14, count 0 2006.225.07:42:52.27#ibcon#about to read 5, iclass 14, count 0 2006.225.07:42:52.27#ibcon#read 5, iclass 14, count 0 2006.225.07:42:52.27#ibcon#about to read 6, iclass 14, count 0 2006.225.07:42:52.27#ibcon#read 6, iclass 14, count 0 2006.225.07:42:52.27#ibcon#end of sib2, iclass 14, count 0 2006.225.07:42:52.27#ibcon#*after write, iclass 14, count 0 2006.225.07:42:52.27#ibcon#*before return 0, iclass 14, count 0 2006.225.07:42:52.27#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:42:52.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:42:52.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:42:52.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:42:52.27$vc4f8/vb=6,4 2006.225.07:42:52.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.07:42:52.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.07:42:52.27#ibcon#ireg 11 cls_cnt 2 2006.225.07:42:52.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:42:52.33#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:42:52.33#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:42:52.33#ibcon#enter wrdev, iclass 16, count 2 2006.225.07:42:52.33#ibcon#first serial, iclass 16, count 2 2006.225.07:42:52.33#ibcon#enter sib2, iclass 16, count 2 2006.225.07:42:52.33#ibcon#flushed, iclass 16, count 2 2006.225.07:42:52.33#ibcon#about to write, iclass 16, count 2 2006.225.07:42:52.33#ibcon#wrote, iclass 16, count 2 2006.225.07:42:52.33#ibcon#about to read 3, iclass 16, count 2 2006.225.07:42:52.35#ibcon#read 3, iclass 16, count 2 2006.225.07:42:52.35#ibcon#about to read 4, iclass 16, count 2 2006.225.07:42:52.35#ibcon#read 4, iclass 16, count 2 2006.225.07:42:52.35#ibcon#about to read 5, iclass 16, count 2 2006.225.07:42:52.35#ibcon#read 5, iclass 16, count 2 2006.225.07:42:52.35#ibcon#about to read 6, iclass 16, count 2 2006.225.07:42:52.35#ibcon#read 6, iclass 16, count 2 2006.225.07:42:52.35#ibcon#end of sib2, iclass 16, count 2 2006.225.07:42:52.35#ibcon#*mode == 0, iclass 16, count 2 2006.225.07:42:52.35#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.07:42:52.35#ibcon#[27=AT06-04\r\n] 2006.225.07:42:52.35#ibcon#*before write, iclass 16, count 2 2006.225.07:42:52.35#ibcon#enter sib2, iclass 16, count 2 2006.225.07:42:52.35#ibcon#flushed, iclass 16, count 2 2006.225.07:42:52.35#ibcon#about to write, iclass 16, count 2 2006.225.07:42:52.35#ibcon#wrote, iclass 16, count 2 2006.225.07:42:52.35#ibcon#about to read 3, iclass 16, count 2 2006.225.07:42:52.38#ibcon#read 3, iclass 16, count 2 2006.225.07:42:52.38#ibcon#about to read 4, iclass 16, count 2 2006.225.07:42:52.38#ibcon#read 4, iclass 16, count 2 2006.225.07:42:52.38#ibcon#about to read 5, iclass 16, count 2 2006.225.07:42:52.38#ibcon#read 5, iclass 16, count 2 2006.225.07:42:52.38#ibcon#about to read 6, iclass 16, count 2 2006.225.07:42:52.38#ibcon#read 6, iclass 16, count 2 2006.225.07:42:52.38#ibcon#end of sib2, iclass 16, count 2 2006.225.07:42:52.38#ibcon#*after write, iclass 16, count 2 2006.225.07:42:52.38#ibcon#*before return 0, iclass 16, count 2 2006.225.07:42:52.38#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:42:52.38#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:42:52.38#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.07:42:52.38#ibcon#ireg 7 cls_cnt 0 2006.225.07:42:52.38#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:42:52.50#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:42:52.50#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:42:52.50#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:42:52.50#ibcon#first serial, iclass 16, count 0 2006.225.07:42:52.50#ibcon#enter sib2, iclass 16, count 0 2006.225.07:42:52.50#ibcon#flushed, iclass 16, count 0 2006.225.07:42:52.50#ibcon#about to write, iclass 16, count 0 2006.225.07:42:52.50#ibcon#wrote, iclass 16, count 0 2006.225.07:42:52.50#ibcon#about to read 3, iclass 16, count 0 2006.225.07:42:52.52#ibcon#read 3, iclass 16, count 0 2006.225.07:42:52.52#ibcon#about to read 4, iclass 16, count 0 2006.225.07:42:52.52#ibcon#read 4, iclass 16, count 0 2006.225.07:42:52.52#ibcon#about to read 5, iclass 16, count 0 2006.225.07:42:52.52#ibcon#read 5, iclass 16, count 0 2006.225.07:42:52.52#ibcon#about to read 6, iclass 16, count 0 2006.225.07:42:52.52#ibcon#read 6, iclass 16, count 0 2006.225.07:42:52.52#ibcon#end of sib2, iclass 16, count 0 2006.225.07:42:52.52#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:42:52.52#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:42:52.52#ibcon#[27=USB\r\n] 2006.225.07:42:52.52#ibcon#*before write, iclass 16, count 0 2006.225.07:42:52.52#ibcon#enter sib2, iclass 16, count 0 2006.225.07:42:52.52#ibcon#flushed, iclass 16, count 0 2006.225.07:42:52.52#ibcon#about to write, iclass 16, count 0 2006.225.07:42:52.52#ibcon#wrote, iclass 16, count 0 2006.225.07:42:52.52#ibcon#about to read 3, iclass 16, count 0 2006.225.07:42:52.55#ibcon#read 3, iclass 16, count 0 2006.225.07:42:52.55#ibcon#about to read 4, iclass 16, count 0 2006.225.07:42:52.55#ibcon#read 4, iclass 16, count 0 2006.225.07:42:52.55#ibcon#about to read 5, iclass 16, count 0 2006.225.07:42:52.55#ibcon#read 5, iclass 16, count 0 2006.225.07:42:52.55#ibcon#about to read 6, iclass 16, count 0 2006.225.07:42:52.55#ibcon#read 6, iclass 16, count 0 2006.225.07:42:52.55#ibcon#end of sib2, iclass 16, count 0 2006.225.07:42:52.55#ibcon#*after write, iclass 16, count 0 2006.225.07:42:52.55#ibcon#*before return 0, iclass 16, count 0 2006.225.07:42:52.55#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:42:52.55#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:42:52.55#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:42:52.55#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:42:52.55$vc4f8/vabw=wide 2006.225.07:42:52.55#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.07:42:52.55#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.07:42:52.55#ibcon#ireg 8 cls_cnt 0 2006.225.07:42:52.55#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:42:52.55#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:42:52.55#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:42:52.55#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:42:52.55#ibcon#first serial, iclass 18, count 0 2006.225.07:42:52.55#ibcon#enter sib2, iclass 18, count 0 2006.225.07:42:52.55#ibcon#flushed, iclass 18, count 0 2006.225.07:42:52.55#ibcon#about to write, iclass 18, count 0 2006.225.07:42:52.55#ibcon#wrote, iclass 18, count 0 2006.225.07:42:52.55#ibcon#about to read 3, iclass 18, count 0 2006.225.07:42:52.57#ibcon#read 3, iclass 18, count 0 2006.225.07:42:52.57#ibcon#about to read 4, iclass 18, count 0 2006.225.07:42:52.57#ibcon#read 4, iclass 18, count 0 2006.225.07:42:52.57#ibcon#about to read 5, iclass 18, count 0 2006.225.07:42:52.57#ibcon#read 5, iclass 18, count 0 2006.225.07:42:52.57#ibcon#about to read 6, iclass 18, count 0 2006.225.07:42:52.57#ibcon#read 6, iclass 18, count 0 2006.225.07:42:52.57#ibcon#end of sib2, iclass 18, count 0 2006.225.07:42:52.57#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:42:52.57#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:42:52.57#ibcon#[25=BW32\r\n] 2006.225.07:42:52.57#ibcon#*before write, iclass 18, count 0 2006.225.07:42:52.57#ibcon#enter sib2, iclass 18, count 0 2006.225.07:42:52.57#ibcon#flushed, iclass 18, count 0 2006.225.07:42:52.57#ibcon#about to write, iclass 18, count 0 2006.225.07:42:52.57#ibcon#wrote, iclass 18, count 0 2006.225.07:42:52.57#ibcon#about to read 3, iclass 18, count 0 2006.225.07:42:52.60#ibcon#read 3, iclass 18, count 0 2006.225.07:42:52.60#ibcon#about to read 4, iclass 18, count 0 2006.225.07:42:52.60#ibcon#read 4, iclass 18, count 0 2006.225.07:42:52.60#ibcon#about to read 5, iclass 18, count 0 2006.225.07:42:52.60#ibcon#read 5, iclass 18, count 0 2006.225.07:42:52.60#ibcon#about to read 6, iclass 18, count 0 2006.225.07:42:52.60#ibcon#read 6, iclass 18, count 0 2006.225.07:42:52.60#ibcon#end of sib2, iclass 18, count 0 2006.225.07:42:52.60#ibcon#*after write, iclass 18, count 0 2006.225.07:42:52.60#ibcon#*before return 0, iclass 18, count 0 2006.225.07:42:52.60#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:42:52.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:42:52.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:42:52.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:42:52.60$vc4f8/vbbw=wide 2006.225.07:42:52.60#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.225.07:42:52.60#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.225.07:42:52.60#ibcon#ireg 8 cls_cnt 0 2006.225.07:42:52.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:42:52.67#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:42:52.67#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:42:52.67#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:42:52.67#ibcon#first serial, iclass 20, count 0 2006.225.07:42:52.67#ibcon#enter sib2, iclass 20, count 0 2006.225.07:42:52.67#ibcon#flushed, iclass 20, count 0 2006.225.07:42:52.67#ibcon#about to write, iclass 20, count 0 2006.225.07:42:52.67#ibcon#wrote, iclass 20, count 0 2006.225.07:42:52.67#ibcon#about to read 3, iclass 20, count 0 2006.225.07:42:52.69#ibcon#read 3, iclass 20, count 0 2006.225.07:42:52.69#ibcon#about to read 4, iclass 20, count 0 2006.225.07:42:52.69#ibcon#read 4, iclass 20, count 0 2006.225.07:42:52.69#ibcon#about to read 5, iclass 20, count 0 2006.225.07:42:52.69#ibcon#read 5, iclass 20, count 0 2006.225.07:42:52.69#ibcon#about to read 6, iclass 20, count 0 2006.225.07:42:52.69#ibcon#read 6, iclass 20, count 0 2006.225.07:42:52.69#ibcon#end of sib2, iclass 20, count 0 2006.225.07:42:52.69#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:42:52.69#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:42:52.69#ibcon#[27=BW32\r\n] 2006.225.07:42:52.69#ibcon#*before write, iclass 20, count 0 2006.225.07:42:52.69#ibcon#enter sib2, iclass 20, count 0 2006.225.07:42:52.69#ibcon#flushed, iclass 20, count 0 2006.225.07:42:52.69#ibcon#about to write, iclass 20, count 0 2006.225.07:42:52.69#ibcon#wrote, iclass 20, count 0 2006.225.07:42:52.69#ibcon#about to read 3, iclass 20, count 0 2006.225.07:42:52.72#ibcon#read 3, iclass 20, count 0 2006.225.07:42:52.72#ibcon#about to read 4, iclass 20, count 0 2006.225.07:42:52.72#ibcon#read 4, iclass 20, count 0 2006.225.07:42:52.72#ibcon#about to read 5, iclass 20, count 0 2006.225.07:42:52.72#ibcon#read 5, iclass 20, count 0 2006.225.07:42:52.72#ibcon#about to read 6, iclass 20, count 0 2006.225.07:42:52.72#ibcon#read 6, iclass 20, count 0 2006.225.07:42:52.72#ibcon#end of sib2, iclass 20, count 0 2006.225.07:42:52.72#ibcon#*after write, iclass 20, count 0 2006.225.07:42:52.72#ibcon#*before return 0, iclass 20, count 0 2006.225.07:42:52.72#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:42:52.72#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:42:52.72#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:42:52.72#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:42:52.72$4f8m12a/ifd4f 2006.225.07:42:52.72$ifd4f/lo= 2006.225.07:42:52.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:42:52.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:42:52.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:42:52.72$ifd4f/patch= 2006.225.07:42:52.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:42:52.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:42:52.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:42:52.72$4f8m12a/"form=m,16.000,1:2 2006.225.07:42:52.72$4f8m12a/"tpicd 2006.225.07:42:52.72$4f8m12a/echo=off 2006.225.07:42:52.72$4f8m12a/xlog=off 2006.225.07:42:52.72:!2006.225.07:43:20 2006.225.07:43:01.13#trakl#Source acquired 2006.225.07:43:02.13#flagr#flagr/antenna,acquired 2006.225.07:43:20.00:preob 2006.225.07:43:21.13/onsource/TRACKING 2006.225.07:43:21.13:!2006.225.07:43:30 2006.225.07:43:30.00:data_valid=on 2006.225.07:43:30.00:midob 2006.225.07:43:30.13/onsource/TRACKING 2006.225.07:43:30.13/wx/28.02,1003.3,71 2006.225.07:43:30.34/cable/+6.4047E-03 2006.225.07:43:31.43/va/01,08,usb,yes,28,29 2006.225.07:43:31.43/va/02,07,usb,yes,28,30 2006.225.07:43:31.43/va/03,06,usb,yes,30,30 2006.225.07:43:31.43/va/04,07,usb,yes,29,32 2006.225.07:43:31.43/va/05,07,usb,yes,32,33 2006.225.07:43:31.43/va/06,06,usb,yes,31,31 2006.225.07:43:31.43/va/07,06,usb,yes,31,31 2006.225.07:43:31.43/va/08,07,usb,yes,30,29 2006.225.07:43:31.66/valo/01,532.99,yes,locked 2006.225.07:43:31.66/valo/02,572.99,yes,locked 2006.225.07:43:31.66/valo/03,672.99,yes,locked 2006.225.07:43:31.66/valo/04,832.99,yes,locked 2006.225.07:43:31.66/valo/05,652.99,yes,locked 2006.225.07:43:31.66/valo/06,772.99,yes,locked 2006.225.07:43:31.66/valo/07,832.99,yes,locked 2006.225.07:43:31.66/valo/08,852.99,yes,locked 2006.225.07:43:32.75/vb/01,04,usb,yes,30,29 2006.225.07:43:32.75/vb/02,04,usb,yes,32,33 2006.225.07:43:32.75/vb/03,04,usb,yes,28,32 2006.225.07:43:32.75/vb/04,04,usb,yes,29,29 2006.225.07:43:32.75/vb/05,04,usb,yes,27,31 2006.225.07:43:32.75/vb/06,04,usb,yes,28,31 2006.225.07:43:32.75/vb/07,04,usb,yes,31,30 2006.225.07:43:32.75/vb/08,04,usb,yes,28,31 2006.225.07:43:32.99/vblo/01,632.99,yes,locked 2006.225.07:43:32.99/vblo/02,640.99,yes,locked 2006.225.07:43:32.99/vblo/03,656.99,yes,locked 2006.225.07:43:32.99/vblo/04,712.99,yes,locked 2006.225.07:43:32.99/vblo/05,744.99,yes,locked 2006.225.07:43:32.99/vblo/06,752.99,yes,locked 2006.225.07:43:32.99/vblo/07,734.99,yes,locked 2006.225.07:43:32.99/vblo/08,744.99,yes,locked 2006.225.07:43:33.14/vabw/8 2006.225.07:43:33.29/vbbw/8 2006.225.07:43:33.38/xfe/off,on,15.2 2006.225.07:43:33.77/ifatt/23,28,28,28 2006.225.07:43:34.07/fmout-gps/S +4.49E-07 2006.225.07:43:34.11:!2006.225.07:44:30 2006.225.07:44:30.01:data_valid=off 2006.225.07:44:30.01:postob 2006.225.07:44:30.10/cable/+6.4049E-03 2006.225.07:44:30.10/wx/28.05,1003.3,69 2006.225.07:44:31.07/fmout-gps/S +4.49E-07 2006.225.07:44:31.07:scan_name=225-0745,k06225,60 2006.225.07:44:31.08:source=0804+499,080839.67,495036.5,2000.0,ccw 2006.225.07:44:31.14#flagr#flagr/antenna,new-source 2006.225.07:44:32.14:checkk5 2006.225.07:44:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:44:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:44:33.25/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:44:33.62/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:44:33.98/chk_obsdata//k5ts1/T2250743??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:44:34.36/chk_obsdata//k5ts2/T2250743??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:44:34.72/chk_obsdata//k5ts3/T2250743??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:44:35.09/chk_obsdata//k5ts4/T2250743??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:44:35.79/k5log//k5ts1_log_newline 2006.225.07:44:36.47/k5log//k5ts2_log_newline 2006.225.07:44:37.15/k5log//k5ts3_log_newline 2006.225.07:44:37.85/k5log//k5ts4_log_newline 2006.225.07:44:37.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:44:37.88:4f8m12a=1 2006.225.07:44:37.88$4f8m12a/echo=on 2006.225.07:44:37.88$4f8m12a/pcalon 2006.225.07:44:37.88$pcalon/"no phase cal control is implemented here 2006.225.07:44:37.88$4f8m12a/"tpicd=stop 2006.225.07:44:37.88$4f8m12a/vc4f8 2006.225.07:44:37.88$vc4f8/valo=1,532.99 2006.225.07:44:37.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.07:44:37.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.07:44:37.88#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:37.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:44:37.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:44:37.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:44:37.88#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:44:37.88#ibcon#first serial, iclass 31, count 0 2006.225.07:44:37.88#ibcon#enter sib2, iclass 31, count 0 2006.225.07:44:37.88#ibcon#flushed, iclass 31, count 0 2006.225.07:44:37.88#ibcon#about to write, iclass 31, count 0 2006.225.07:44:37.88#ibcon#wrote, iclass 31, count 0 2006.225.07:44:37.88#ibcon#about to read 3, iclass 31, count 0 2006.225.07:44:37.92#ibcon#read 3, iclass 31, count 0 2006.225.07:44:37.92#ibcon#about to read 4, iclass 31, count 0 2006.225.07:44:37.92#ibcon#read 4, iclass 31, count 0 2006.225.07:44:37.92#ibcon#about to read 5, iclass 31, count 0 2006.225.07:44:37.92#ibcon#read 5, iclass 31, count 0 2006.225.07:44:37.92#ibcon#about to read 6, iclass 31, count 0 2006.225.07:44:37.92#ibcon#read 6, iclass 31, count 0 2006.225.07:44:37.92#ibcon#end of sib2, iclass 31, count 0 2006.225.07:44:37.92#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:44:37.92#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:44:37.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:44:37.92#ibcon#*before write, iclass 31, count 0 2006.225.07:44:37.92#ibcon#enter sib2, iclass 31, count 0 2006.225.07:44:37.92#ibcon#flushed, iclass 31, count 0 2006.225.07:44:37.92#ibcon#about to write, iclass 31, count 0 2006.225.07:44:37.92#ibcon#wrote, iclass 31, count 0 2006.225.07:44:37.92#ibcon#about to read 3, iclass 31, count 0 2006.225.07:44:37.97#ibcon#read 3, iclass 31, count 0 2006.225.07:44:37.97#ibcon#about to read 4, iclass 31, count 0 2006.225.07:44:37.97#ibcon#read 4, iclass 31, count 0 2006.225.07:44:37.97#ibcon#about to read 5, iclass 31, count 0 2006.225.07:44:37.97#ibcon#read 5, iclass 31, count 0 2006.225.07:44:37.97#ibcon#about to read 6, iclass 31, count 0 2006.225.07:44:37.97#ibcon#read 6, iclass 31, count 0 2006.225.07:44:37.97#ibcon#end of sib2, iclass 31, count 0 2006.225.07:44:37.97#ibcon#*after write, iclass 31, count 0 2006.225.07:44:37.97#ibcon#*before return 0, iclass 31, count 0 2006.225.07:44:37.97#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:44:37.97#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:44:37.97#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:44:37.97#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:44:37.97$vc4f8/va=1,8 2006.225.07:44:37.97#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.225.07:44:37.97#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.225.07:44:37.97#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:37.97#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:44:37.97#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:44:37.97#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:44:37.97#ibcon#enter wrdev, iclass 33, count 2 2006.225.07:44:37.97#ibcon#first serial, iclass 33, count 2 2006.225.07:44:37.97#ibcon#enter sib2, iclass 33, count 2 2006.225.07:44:37.97#ibcon#flushed, iclass 33, count 2 2006.225.07:44:37.97#ibcon#about to write, iclass 33, count 2 2006.225.07:44:37.97#ibcon#wrote, iclass 33, count 2 2006.225.07:44:37.97#ibcon#about to read 3, iclass 33, count 2 2006.225.07:44:38.00#ibcon#read 3, iclass 33, count 2 2006.225.07:44:38.00#ibcon#about to read 4, iclass 33, count 2 2006.225.07:44:38.00#ibcon#read 4, iclass 33, count 2 2006.225.07:44:38.00#ibcon#about to read 5, iclass 33, count 2 2006.225.07:44:38.00#ibcon#read 5, iclass 33, count 2 2006.225.07:44:38.00#ibcon#about to read 6, iclass 33, count 2 2006.225.07:44:38.00#ibcon#read 6, iclass 33, count 2 2006.225.07:44:38.00#ibcon#end of sib2, iclass 33, count 2 2006.225.07:44:38.00#ibcon#*mode == 0, iclass 33, count 2 2006.225.07:44:38.00#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.225.07:44:38.00#ibcon#[25=AT01-08\r\n] 2006.225.07:44:38.00#ibcon#*before write, iclass 33, count 2 2006.225.07:44:38.00#ibcon#enter sib2, iclass 33, count 2 2006.225.07:44:38.00#ibcon#flushed, iclass 33, count 2 2006.225.07:44:38.00#ibcon#about to write, iclass 33, count 2 2006.225.07:44:38.00#ibcon#wrote, iclass 33, count 2 2006.225.07:44:38.00#ibcon#about to read 3, iclass 33, count 2 2006.225.07:44:38.03#ibcon#read 3, iclass 33, count 2 2006.225.07:44:38.03#ibcon#about to read 4, iclass 33, count 2 2006.225.07:44:38.03#ibcon#read 4, iclass 33, count 2 2006.225.07:44:38.03#ibcon#about to read 5, iclass 33, count 2 2006.225.07:44:38.03#ibcon#read 5, iclass 33, count 2 2006.225.07:44:38.03#ibcon#about to read 6, iclass 33, count 2 2006.225.07:44:38.03#ibcon#read 6, iclass 33, count 2 2006.225.07:44:38.03#ibcon#end of sib2, iclass 33, count 2 2006.225.07:44:38.03#ibcon#*after write, iclass 33, count 2 2006.225.07:44:38.03#ibcon#*before return 0, iclass 33, count 2 2006.225.07:44:38.03#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:44:38.03#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:44:38.03#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.225.07:44:38.03#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:38.03#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:44:38.15#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:44:38.15#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:44:38.15#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:44:38.15#ibcon#first serial, iclass 33, count 0 2006.225.07:44:38.15#ibcon#enter sib2, iclass 33, count 0 2006.225.07:44:38.15#ibcon#flushed, iclass 33, count 0 2006.225.07:44:38.15#ibcon#about to write, iclass 33, count 0 2006.225.07:44:38.15#ibcon#wrote, iclass 33, count 0 2006.225.07:44:38.15#ibcon#about to read 3, iclass 33, count 0 2006.225.07:44:38.17#ibcon#read 3, iclass 33, count 0 2006.225.07:44:38.17#ibcon#about to read 4, iclass 33, count 0 2006.225.07:44:38.17#ibcon#read 4, iclass 33, count 0 2006.225.07:44:38.17#ibcon#about to read 5, iclass 33, count 0 2006.225.07:44:38.17#ibcon#read 5, iclass 33, count 0 2006.225.07:44:38.17#ibcon#about to read 6, iclass 33, count 0 2006.225.07:44:38.17#ibcon#read 6, iclass 33, count 0 2006.225.07:44:38.17#ibcon#end of sib2, iclass 33, count 0 2006.225.07:44:38.17#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:44:38.17#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:44:38.17#ibcon#[25=USB\r\n] 2006.225.07:44:38.17#ibcon#*before write, iclass 33, count 0 2006.225.07:44:38.17#ibcon#enter sib2, iclass 33, count 0 2006.225.07:44:38.17#ibcon#flushed, iclass 33, count 0 2006.225.07:44:38.17#ibcon#about to write, iclass 33, count 0 2006.225.07:44:38.17#ibcon#wrote, iclass 33, count 0 2006.225.07:44:38.17#ibcon#about to read 3, iclass 33, count 0 2006.225.07:44:38.20#ibcon#read 3, iclass 33, count 0 2006.225.07:44:38.20#ibcon#about to read 4, iclass 33, count 0 2006.225.07:44:38.20#ibcon#read 4, iclass 33, count 0 2006.225.07:44:38.20#ibcon#about to read 5, iclass 33, count 0 2006.225.07:44:38.20#ibcon#read 5, iclass 33, count 0 2006.225.07:44:38.20#ibcon#about to read 6, iclass 33, count 0 2006.225.07:44:38.20#ibcon#read 6, iclass 33, count 0 2006.225.07:44:38.20#ibcon#end of sib2, iclass 33, count 0 2006.225.07:44:38.20#ibcon#*after write, iclass 33, count 0 2006.225.07:44:38.20#ibcon#*before return 0, iclass 33, count 0 2006.225.07:44:38.20#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:44:38.20#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:44:38.20#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:44:38.20#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:44:38.20$vc4f8/valo=2,572.99 2006.225.07:44:38.20#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.225.07:44:38.20#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.225.07:44:38.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:38.20#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:44:38.20#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:44:38.20#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:44:38.20#ibcon#enter wrdev, iclass 35, count 0 2006.225.07:44:38.20#ibcon#first serial, iclass 35, count 0 2006.225.07:44:38.20#ibcon#enter sib2, iclass 35, count 0 2006.225.07:44:38.20#ibcon#flushed, iclass 35, count 0 2006.225.07:44:38.20#ibcon#about to write, iclass 35, count 0 2006.225.07:44:38.20#ibcon#wrote, iclass 35, count 0 2006.225.07:44:38.20#ibcon#about to read 3, iclass 35, count 0 2006.225.07:44:38.22#ibcon#read 3, iclass 35, count 0 2006.225.07:44:38.22#ibcon#about to read 4, iclass 35, count 0 2006.225.07:44:38.22#ibcon#read 4, iclass 35, count 0 2006.225.07:44:38.22#ibcon#about to read 5, iclass 35, count 0 2006.225.07:44:38.22#ibcon#read 5, iclass 35, count 0 2006.225.07:44:38.22#ibcon#about to read 6, iclass 35, count 0 2006.225.07:44:38.22#ibcon#read 6, iclass 35, count 0 2006.225.07:44:38.22#ibcon#end of sib2, iclass 35, count 0 2006.225.07:44:38.22#ibcon#*mode == 0, iclass 35, count 0 2006.225.07:44:38.22#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.07:44:38.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:44:38.22#ibcon#*before write, iclass 35, count 0 2006.225.07:44:38.22#ibcon#enter sib2, iclass 35, count 0 2006.225.07:44:38.22#ibcon#flushed, iclass 35, count 0 2006.225.07:44:38.22#ibcon#about to write, iclass 35, count 0 2006.225.07:44:38.22#ibcon#wrote, iclass 35, count 0 2006.225.07:44:38.22#ibcon#about to read 3, iclass 35, count 0 2006.225.07:44:38.26#ibcon#read 3, iclass 35, count 0 2006.225.07:44:38.26#ibcon#about to read 4, iclass 35, count 0 2006.225.07:44:38.26#ibcon#read 4, iclass 35, count 0 2006.225.07:44:38.26#ibcon#about to read 5, iclass 35, count 0 2006.225.07:44:38.26#ibcon#read 5, iclass 35, count 0 2006.225.07:44:38.26#ibcon#about to read 6, iclass 35, count 0 2006.225.07:44:38.26#ibcon#read 6, iclass 35, count 0 2006.225.07:44:38.26#ibcon#end of sib2, iclass 35, count 0 2006.225.07:44:38.26#ibcon#*after write, iclass 35, count 0 2006.225.07:44:38.26#ibcon#*before return 0, iclass 35, count 0 2006.225.07:44:38.26#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:44:38.26#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:44:38.26#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.07:44:38.26#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.07:44:38.26$vc4f8/va=2,7 2006.225.07:44:38.26#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.225.07:44:38.26#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.225.07:44:38.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:38.26#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:44:38.32#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:44:38.32#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:44:38.32#ibcon#enter wrdev, iclass 37, count 2 2006.225.07:44:38.32#ibcon#first serial, iclass 37, count 2 2006.225.07:44:38.32#ibcon#enter sib2, iclass 37, count 2 2006.225.07:44:38.32#ibcon#flushed, iclass 37, count 2 2006.225.07:44:38.32#ibcon#about to write, iclass 37, count 2 2006.225.07:44:38.32#ibcon#wrote, iclass 37, count 2 2006.225.07:44:38.32#ibcon#about to read 3, iclass 37, count 2 2006.225.07:44:38.34#ibcon#read 3, iclass 37, count 2 2006.225.07:44:38.34#ibcon#about to read 4, iclass 37, count 2 2006.225.07:44:38.34#ibcon#read 4, iclass 37, count 2 2006.225.07:44:38.34#ibcon#about to read 5, iclass 37, count 2 2006.225.07:44:38.34#ibcon#read 5, iclass 37, count 2 2006.225.07:44:38.34#ibcon#about to read 6, iclass 37, count 2 2006.225.07:44:38.34#ibcon#read 6, iclass 37, count 2 2006.225.07:44:38.34#ibcon#end of sib2, iclass 37, count 2 2006.225.07:44:38.34#ibcon#*mode == 0, iclass 37, count 2 2006.225.07:44:38.34#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.225.07:44:38.34#ibcon#[25=AT02-07\r\n] 2006.225.07:44:38.34#ibcon#*before write, iclass 37, count 2 2006.225.07:44:38.34#ibcon#enter sib2, iclass 37, count 2 2006.225.07:44:38.34#ibcon#flushed, iclass 37, count 2 2006.225.07:44:38.34#ibcon#about to write, iclass 37, count 2 2006.225.07:44:38.34#ibcon#wrote, iclass 37, count 2 2006.225.07:44:38.34#ibcon#about to read 3, iclass 37, count 2 2006.225.07:44:38.37#ibcon#read 3, iclass 37, count 2 2006.225.07:44:38.37#ibcon#about to read 4, iclass 37, count 2 2006.225.07:44:38.37#ibcon#read 4, iclass 37, count 2 2006.225.07:44:38.37#ibcon#about to read 5, iclass 37, count 2 2006.225.07:44:38.37#ibcon#read 5, iclass 37, count 2 2006.225.07:44:38.37#ibcon#about to read 6, iclass 37, count 2 2006.225.07:44:38.37#ibcon#read 6, iclass 37, count 2 2006.225.07:44:38.37#ibcon#end of sib2, iclass 37, count 2 2006.225.07:44:38.37#ibcon#*after write, iclass 37, count 2 2006.225.07:44:38.37#ibcon#*before return 0, iclass 37, count 2 2006.225.07:44:38.37#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:44:38.37#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:44:38.37#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.225.07:44:38.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:38.37#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:44:38.49#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:44:38.49#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:44:38.49#ibcon#enter wrdev, iclass 37, count 0 2006.225.07:44:38.49#ibcon#first serial, iclass 37, count 0 2006.225.07:44:38.49#ibcon#enter sib2, iclass 37, count 0 2006.225.07:44:38.49#ibcon#flushed, iclass 37, count 0 2006.225.07:44:38.49#ibcon#about to write, iclass 37, count 0 2006.225.07:44:38.49#ibcon#wrote, iclass 37, count 0 2006.225.07:44:38.49#ibcon#about to read 3, iclass 37, count 0 2006.225.07:44:38.51#ibcon#read 3, iclass 37, count 0 2006.225.07:44:38.51#ibcon#about to read 4, iclass 37, count 0 2006.225.07:44:38.51#ibcon#read 4, iclass 37, count 0 2006.225.07:44:38.51#ibcon#about to read 5, iclass 37, count 0 2006.225.07:44:38.51#ibcon#read 5, iclass 37, count 0 2006.225.07:44:38.51#ibcon#about to read 6, iclass 37, count 0 2006.225.07:44:38.51#ibcon#read 6, iclass 37, count 0 2006.225.07:44:38.51#ibcon#end of sib2, iclass 37, count 0 2006.225.07:44:38.51#ibcon#*mode == 0, iclass 37, count 0 2006.225.07:44:38.51#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.07:44:38.51#ibcon#[25=USB\r\n] 2006.225.07:44:38.51#ibcon#*before write, iclass 37, count 0 2006.225.07:44:38.51#ibcon#enter sib2, iclass 37, count 0 2006.225.07:44:38.51#ibcon#flushed, iclass 37, count 0 2006.225.07:44:38.51#ibcon#about to write, iclass 37, count 0 2006.225.07:44:38.51#ibcon#wrote, iclass 37, count 0 2006.225.07:44:38.51#ibcon#about to read 3, iclass 37, count 0 2006.225.07:44:38.54#ibcon#read 3, iclass 37, count 0 2006.225.07:44:38.54#ibcon#about to read 4, iclass 37, count 0 2006.225.07:44:38.54#ibcon#read 4, iclass 37, count 0 2006.225.07:44:38.54#ibcon#about to read 5, iclass 37, count 0 2006.225.07:44:38.54#ibcon#read 5, iclass 37, count 0 2006.225.07:44:38.54#ibcon#about to read 6, iclass 37, count 0 2006.225.07:44:38.54#ibcon#read 6, iclass 37, count 0 2006.225.07:44:38.54#ibcon#end of sib2, iclass 37, count 0 2006.225.07:44:38.54#ibcon#*after write, iclass 37, count 0 2006.225.07:44:38.54#ibcon#*before return 0, iclass 37, count 0 2006.225.07:44:38.54#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:44:38.54#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:44:38.54#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.07:44:38.54#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.07:44:38.54$vc4f8/valo=3,672.99 2006.225.07:44:38.54#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.07:44:38.54#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.07:44:38.54#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:38.54#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:44:38.54#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:44:38.54#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:44:38.54#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:44:38.54#ibcon#first serial, iclass 39, count 0 2006.225.07:44:38.54#ibcon#enter sib2, iclass 39, count 0 2006.225.07:44:38.54#ibcon#flushed, iclass 39, count 0 2006.225.07:44:38.54#ibcon#about to write, iclass 39, count 0 2006.225.07:44:38.54#ibcon#wrote, iclass 39, count 0 2006.225.07:44:38.54#ibcon#about to read 3, iclass 39, count 0 2006.225.07:44:38.56#ibcon#read 3, iclass 39, count 0 2006.225.07:44:38.56#ibcon#about to read 4, iclass 39, count 0 2006.225.07:44:38.56#ibcon#read 4, iclass 39, count 0 2006.225.07:44:38.56#ibcon#about to read 5, iclass 39, count 0 2006.225.07:44:38.56#ibcon#read 5, iclass 39, count 0 2006.225.07:44:38.56#ibcon#about to read 6, iclass 39, count 0 2006.225.07:44:38.56#ibcon#read 6, iclass 39, count 0 2006.225.07:44:38.56#ibcon#end of sib2, iclass 39, count 0 2006.225.07:44:38.56#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:44:38.56#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:44:38.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:44:38.56#ibcon#*before write, iclass 39, count 0 2006.225.07:44:38.56#ibcon#enter sib2, iclass 39, count 0 2006.225.07:44:38.56#ibcon#flushed, iclass 39, count 0 2006.225.07:44:38.56#ibcon#about to write, iclass 39, count 0 2006.225.07:44:38.56#ibcon#wrote, iclass 39, count 0 2006.225.07:44:38.56#ibcon#about to read 3, iclass 39, count 0 2006.225.07:44:38.60#ibcon#read 3, iclass 39, count 0 2006.225.07:44:38.60#ibcon#about to read 4, iclass 39, count 0 2006.225.07:44:38.60#ibcon#read 4, iclass 39, count 0 2006.225.07:44:38.60#ibcon#about to read 5, iclass 39, count 0 2006.225.07:44:38.60#ibcon#read 5, iclass 39, count 0 2006.225.07:44:38.60#ibcon#about to read 6, iclass 39, count 0 2006.225.07:44:38.60#ibcon#read 6, iclass 39, count 0 2006.225.07:44:38.60#ibcon#end of sib2, iclass 39, count 0 2006.225.07:44:38.60#ibcon#*after write, iclass 39, count 0 2006.225.07:44:38.60#ibcon#*before return 0, iclass 39, count 0 2006.225.07:44:38.60#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:44:38.60#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:44:38.60#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:44:38.60#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:44:38.60$vc4f8/va=3,6 2006.225.07:44:38.60#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.07:44:38.60#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.07:44:38.60#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:38.60#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:44:38.66#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:44:38.66#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:44:38.66#ibcon#enter wrdev, iclass 3, count 2 2006.225.07:44:38.66#ibcon#first serial, iclass 3, count 2 2006.225.07:44:38.66#ibcon#enter sib2, iclass 3, count 2 2006.225.07:44:38.66#ibcon#flushed, iclass 3, count 2 2006.225.07:44:38.66#ibcon#about to write, iclass 3, count 2 2006.225.07:44:38.66#ibcon#wrote, iclass 3, count 2 2006.225.07:44:38.66#ibcon#about to read 3, iclass 3, count 2 2006.225.07:44:38.69#ibcon#read 3, iclass 3, count 2 2006.225.07:44:38.69#ibcon#about to read 4, iclass 3, count 2 2006.225.07:44:38.69#ibcon#read 4, iclass 3, count 2 2006.225.07:44:38.69#ibcon#about to read 5, iclass 3, count 2 2006.225.07:44:38.69#ibcon#read 5, iclass 3, count 2 2006.225.07:44:38.69#ibcon#about to read 6, iclass 3, count 2 2006.225.07:44:38.69#ibcon#read 6, iclass 3, count 2 2006.225.07:44:38.69#ibcon#end of sib2, iclass 3, count 2 2006.225.07:44:38.69#ibcon#*mode == 0, iclass 3, count 2 2006.225.07:44:38.69#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.07:44:38.69#ibcon#[25=AT03-06\r\n] 2006.225.07:44:38.69#ibcon#*before write, iclass 3, count 2 2006.225.07:44:38.69#ibcon#enter sib2, iclass 3, count 2 2006.225.07:44:38.69#ibcon#flushed, iclass 3, count 2 2006.225.07:44:38.69#ibcon#about to write, iclass 3, count 2 2006.225.07:44:38.69#ibcon#wrote, iclass 3, count 2 2006.225.07:44:38.69#ibcon#about to read 3, iclass 3, count 2 2006.225.07:44:38.72#ibcon#read 3, iclass 3, count 2 2006.225.07:44:38.72#ibcon#about to read 4, iclass 3, count 2 2006.225.07:44:38.72#ibcon#read 4, iclass 3, count 2 2006.225.07:44:38.72#ibcon#about to read 5, iclass 3, count 2 2006.225.07:44:38.72#ibcon#read 5, iclass 3, count 2 2006.225.07:44:38.72#ibcon#about to read 6, iclass 3, count 2 2006.225.07:44:38.72#ibcon#read 6, iclass 3, count 2 2006.225.07:44:38.72#ibcon#end of sib2, iclass 3, count 2 2006.225.07:44:38.72#ibcon#*after write, iclass 3, count 2 2006.225.07:44:38.72#ibcon#*before return 0, iclass 3, count 2 2006.225.07:44:38.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:44:38.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:44:38.72#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.07:44:38.72#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:38.72#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:44:38.84#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:44:38.84#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:44:38.84#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:44:38.84#ibcon#first serial, iclass 3, count 0 2006.225.07:44:38.84#ibcon#enter sib2, iclass 3, count 0 2006.225.07:44:38.84#ibcon#flushed, iclass 3, count 0 2006.225.07:44:38.84#ibcon#about to write, iclass 3, count 0 2006.225.07:44:38.84#ibcon#wrote, iclass 3, count 0 2006.225.07:44:38.84#ibcon#about to read 3, iclass 3, count 0 2006.225.07:44:38.86#ibcon#read 3, iclass 3, count 0 2006.225.07:44:38.86#ibcon#about to read 4, iclass 3, count 0 2006.225.07:44:38.86#ibcon#read 4, iclass 3, count 0 2006.225.07:44:38.86#ibcon#about to read 5, iclass 3, count 0 2006.225.07:44:38.86#ibcon#read 5, iclass 3, count 0 2006.225.07:44:38.86#ibcon#about to read 6, iclass 3, count 0 2006.225.07:44:38.86#ibcon#read 6, iclass 3, count 0 2006.225.07:44:38.86#ibcon#end of sib2, iclass 3, count 0 2006.225.07:44:38.86#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:44:38.86#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:44:38.86#ibcon#[25=USB\r\n] 2006.225.07:44:38.86#ibcon#*before write, iclass 3, count 0 2006.225.07:44:38.86#ibcon#enter sib2, iclass 3, count 0 2006.225.07:44:38.86#ibcon#flushed, iclass 3, count 0 2006.225.07:44:38.86#ibcon#about to write, iclass 3, count 0 2006.225.07:44:38.86#ibcon#wrote, iclass 3, count 0 2006.225.07:44:38.86#ibcon#about to read 3, iclass 3, count 0 2006.225.07:44:38.89#ibcon#read 3, iclass 3, count 0 2006.225.07:44:38.89#ibcon#about to read 4, iclass 3, count 0 2006.225.07:44:38.89#ibcon#read 4, iclass 3, count 0 2006.225.07:44:38.89#ibcon#about to read 5, iclass 3, count 0 2006.225.07:44:38.89#ibcon#read 5, iclass 3, count 0 2006.225.07:44:38.89#ibcon#about to read 6, iclass 3, count 0 2006.225.07:44:38.89#ibcon#read 6, iclass 3, count 0 2006.225.07:44:38.89#ibcon#end of sib2, iclass 3, count 0 2006.225.07:44:38.89#ibcon#*after write, iclass 3, count 0 2006.225.07:44:38.89#ibcon#*before return 0, iclass 3, count 0 2006.225.07:44:38.89#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:44:38.89#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:44:38.89#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:44:38.89#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:44:38.89$vc4f8/valo=4,832.99 2006.225.07:44:38.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.07:44:38.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.07:44:38.89#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:38.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:44:38.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:44:38.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:44:38.89#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:44:38.89#ibcon#first serial, iclass 5, count 0 2006.225.07:44:38.89#ibcon#enter sib2, iclass 5, count 0 2006.225.07:44:38.89#ibcon#flushed, iclass 5, count 0 2006.225.07:44:38.89#ibcon#about to write, iclass 5, count 0 2006.225.07:44:38.89#ibcon#wrote, iclass 5, count 0 2006.225.07:44:38.89#ibcon#about to read 3, iclass 5, count 0 2006.225.07:44:38.91#ibcon#read 3, iclass 5, count 0 2006.225.07:44:38.91#ibcon#about to read 4, iclass 5, count 0 2006.225.07:44:38.91#ibcon#read 4, iclass 5, count 0 2006.225.07:44:38.91#ibcon#about to read 5, iclass 5, count 0 2006.225.07:44:38.91#ibcon#read 5, iclass 5, count 0 2006.225.07:44:38.91#ibcon#about to read 6, iclass 5, count 0 2006.225.07:44:38.91#ibcon#read 6, iclass 5, count 0 2006.225.07:44:38.91#ibcon#end of sib2, iclass 5, count 0 2006.225.07:44:38.91#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:44:38.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:44:38.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:44:38.91#ibcon#*before write, iclass 5, count 0 2006.225.07:44:38.91#ibcon#enter sib2, iclass 5, count 0 2006.225.07:44:38.91#ibcon#flushed, iclass 5, count 0 2006.225.07:44:38.91#ibcon#about to write, iclass 5, count 0 2006.225.07:44:38.91#ibcon#wrote, iclass 5, count 0 2006.225.07:44:38.91#ibcon#about to read 3, iclass 5, count 0 2006.225.07:44:38.95#ibcon#read 3, iclass 5, count 0 2006.225.07:44:38.95#ibcon#about to read 4, iclass 5, count 0 2006.225.07:44:38.95#ibcon#read 4, iclass 5, count 0 2006.225.07:44:38.95#ibcon#about to read 5, iclass 5, count 0 2006.225.07:44:38.95#ibcon#read 5, iclass 5, count 0 2006.225.07:44:38.95#ibcon#about to read 6, iclass 5, count 0 2006.225.07:44:38.95#ibcon#read 6, iclass 5, count 0 2006.225.07:44:38.95#ibcon#end of sib2, iclass 5, count 0 2006.225.07:44:38.95#ibcon#*after write, iclass 5, count 0 2006.225.07:44:38.95#ibcon#*before return 0, iclass 5, count 0 2006.225.07:44:38.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:44:38.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:44:38.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:44:38.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:44:38.95$vc4f8/va=4,7 2006.225.07:44:38.95#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.07:44:38.95#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.07:44:38.95#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:38.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:44:39.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:44:39.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:44:39.01#ibcon#enter wrdev, iclass 7, count 2 2006.225.07:44:39.01#ibcon#first serial, iclass 7, count 2 2006.225.07:44:39.01#ibcon#enter sib2, iclass 7, count 2 2006.225.07:44:39.01#ibcon#flushed, iclass 7, count 2 2006.225.07:44:39.01#ibcon#about to write, iclass 7, count 2 2006.225.07:44:39.01#ibcon#wrote, iclass 7, count 2 2006.225.07:44:39.01#ibcon#about to read 3, iclass 7, count 2 2006.225.07:44:39.03#ibcon#read 3, iclass 7, count 2 2006.225.07:44:39.03#ibcon#about to read 4, iclass 7, count 2 2006.225.07:44:39.03#ibcon#read 4, iclass 7, count 2 2006.225.07:44:39.03#ibcon#about to read 5, iclass 7, count 2 2006.225.07:44:39.03#ibcon#read 5, iclass 7, count 2 2006.225.07:44:39.03#ibcon#about to read 6, iclass 7, count 2 2006.225.07:44:39.03#ibcon#read 6, iclass 7, count 2 2006.225.07:44:39.03#ibcon#end of sib2, iclass 7, count 2 2006.225.07:44:39.03#ibcon#*mode == 0, iclass 7, count 2 2006.225.07:44:39.03#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.07:44:39.03#ibcon#[25=AT04-07\r\n] 2006.225.07:44:39.03#ibcon#*before write, iclass 7, count 2 2006.225.07:44:39.03#ibcon#enter sib2, iclass 7, count 2 2006.225.07:44:39.03#ibcon#flushed, iclass 7, count 2 2006.225.07:44:39.03#ibcon#about to write, iclass 7, count 2 2006.225.07:44:39.03#ibcon#wrote, iclass 7, count 2 2006.225.07:44:39.03#ibcon#about to read 3, iclass 7, count 2 2006.225.07:44:39.06#ibcon#read 3, iclass 7, count 2 2006.225.07:44:39.06#ibcon#about to read 4, iclass 7, count 2 2006.225.07:44:39.06#ibcon#read 4, iclass 7, count 2 2006.225.07:44:39.06#ibcon#about to read 5, iclass 7, count 2 2006.225.07:44:39.06#ibcon#read 5, iclass 7, count 2 2006.225.07:44:39.06#ibcon#about to read 6, iclass 7, count 2 2006.225.07:44:39.06#ibcon#read 6, iclass 7, count 2 2006.225.07:44:39.06#ibcon#end of sib2, iclass 7, count 2 2006.225.07:44:39.06#ibcon#*after write, iclass 7, count 2 2006.225.07:44:39.06#ibcon#*before return 0, iclass 7, count 2 2006.225.07:44:39.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:44:39.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:44:39.06#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.07:44:39.06#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:39.06#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:44:39.18#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:44:39.18#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:44:39.18#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:44:39.18#ibcon#first serial, iclass 7, count 0 2006.225.07:44:39.18#ibcon#enter sib2, iclass 7, count 0 2006.225.07:44:39.18#ibcon#flushed, iclass 7, count 0 2006.225.07:44:39.18#ibcon#about to write, iclass 7, count 0 2006.225.07:44:39.18#ibcon#wrote, iclass 7, count 0 2006.225.07:44:39.18#ibcon#about to read 3, iclass 7, count 0 2006.225.07:44:39.20#ibcon#read 3, iclass 7, count 0 2006.225.07:44:39.20#ibcon#about to read 4, iclass 7, count 0 2006.225.07:44:39.20#ibcon#read 4, iclass 7, count 0 2006.225.07:44:39.20#ibcon#about to read 5, iclass 7, count 0 2006.225.07:44:39.20#ibcon#read 5, iclass 7, count 0 2006.225.07:44:39.20#ibcon#about to read 6, iclass 7, count 0 2006.225.07:44:39.20#ibcon#read 6, iclass 7, count 0 2006.225.07:44:39.20#ibcon#end of sib2, iclass 7, count 0 2006.225.07:44:39.20#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:44:39.20#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:44:39.20#ibcon#[25=USB\r\n] 2006.225.07:44:39.20#ibcon#*before write, iclass 7, count 0 2006.225.07:44:39.20#ibcon#enter sib2, iclass 7, count 0 2006.225.07:44:39.20#ibcon#flushed, iclass 7, count 0 2006.225.07:44:39.20#ibcon#about to write, iclass 7, count 0 2006.225.07:44:39.20#ibcon#wrote, iclass 7, count 0 2006.225.07:44:39.20#ibcon#about to read 3, iclass 7, count 0 2006.225.07:44:39.23#ibcon#read 3, iclass 7, count 0 2006.225.07:44:39.23#ibcon#about to read 4, iclass 7, count 0 2006.225.07:44:39.23#ibcon#read 4, iclass 7, count 0 2006.225.07:44:39.23#ibcon#about to read 5, iclass 7, count 0 2006.225.07:44:39.23#ibcon#read 5, iclass 7, count 0 2006.225.07:44:39.23#ibcon#about to read 6, iclass 7, count 0 2006.225.07:44:39.23#ibcon#read 6, iclass 7, count 0 2006.225.07:44:39.23#ibcon#end of sib2, iclass 7, count 0 2006.225.07:44:39.23#ibcon#*after write, iclass 7, count 0 2006.225.07:44:39.23#ibcon#*before return 0, iclass 7, count 0 2006.225.07:44:39.23#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:44:39.23#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:44:39.23#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:44:39.23#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:44:39.23$vc4f8/valo=5,652.99 2006.225.07:44:39.23#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.07:44:39.23#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.07:44:39.23#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:39.23#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:44:39.23#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:44:39.23#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:44:39.23#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:44:39.23#ibcon#first serial, iclass 11, count 0 2006.225.07:44:39.23#ibcon#enter sib2, iclass 11, count 0 2006.225.07:44:39.23#ibcon#flushed, iclass 11, count 0 2006.225.07:44:39.23#ibcon#about to write, iclass 11, count 0 2006.225.07:44:39.23#ibcon#wrote, iclass 11, count 0 2006.225.07:44:39.23#ibcon#about to read 3, iclass 11, count 0 2006.225.07:44:39.25#ibcon#read 3, iclass 11, count 0 2006.225.07:44:39.25#ibcon#about to read 4, iclass 11, count 0 2006.225.07:44:39.25#ibcon#read 4, iclass 11, count 0 2006.225.07:44:39.25#ibcon#about to read 5, iclass 11, count 0 2006.225.07:44:39.25#ibcon#read 5, iclass 11, count 0 2006.225.07:44:39.25#ibcon#about to read 6, iclass 11, count 0 2006.225.07:44:39.25#ibcon#read 6, iclass 11, count 0 2006.225.07:44:39.25#ibcon#end of sib2, iclass 11, count 0 2006.225.07:44:39.25#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:44:39.25#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:44:39.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:44:39.25#ibcon#*before write, iclass 11, count 0 2006.225.07:44:39.25#ibcon#enter sib2, iclass 11, count 0 2006.225.07:44:39.25#ibcon#flushed, iclass 11, count 0 2006.225.07:44:39.25#ibcon#about to write, iclass 11, count 0 2006.225.07:44:39.25#ibcon#wrote, iclass 11, count 0 2006.225.07:44:39.25#ibcon#about to read 3, iclass 11, count 0 2006.225.07:44:39.29#ibcon#read 3, iclass 11, count 0 2006.225.07:44:39.29#ibcon#about to read 4, iclass 11, count 0 2006.225.07:44:39.29#ibcon#read 4, iclass 11, count 0 2006.225.07:44:39.29#ibcon#about to read 5, iclass 11, count 0 2006.225.07:44:39.29#ibcon#read 5, iclass 11, count 0 2006.225.07:44:39.29#ibcon#about to read 6, iclass 11, count 0 2006.225.07:44:39.29#ibcon#read 6, iclass 11, count 0 2006.225.07:44:39.29#ibcon#end of sib2, iclass 11, count 0 2006.225.07:44:39.29#ibcon#*after write, iclass 11, count 0 2006.225.07:44:39.29#ibcon#*before return 0, iclass 11, count 0 2006.225.07:44:39.29#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:44:39.29#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:44:39.29#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:44:39.29#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:44:39.29$vc4f8/va=5,7 2006.225.07:44:39.29#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.07:44:39.29#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.07:44:39.29#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:39.29#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:44:39.35#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:44:39.35#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:44:39.35#ibcon#enter wrdev, iclass 13, count 2 2006.225.07:44:39.35#ibcon#first serial, iclass 13, count 2 2006.225.07:44:39.35#ibcon#enter sib2, iclass 13, count 2 2006.225.07:44:39.35#ibcon#flushed, iclass 13, count 2 2006.225.07:44:39.35#ibcon#about to write, iclass 13, count 2 2006.225.07:44:39.35#ibcon#wrote, iclass 13, count 2 2006.225.07:44:39.35#ibcon#about to read 3, iclass 13, count 2 2006.225.07:44:39.37#ibcon#read 3, iclass 13, count 2 2006.225.07:44:39.37#ibcon#about to read 4, iclass 13, count 2 2006.225.07:44:39.37#ibcon#read 4, iclass 13, count 2 2006.225.07:44:39.37#ibcon#about to read 5, iclass 13, count 2 2006.225.07:44:39.37#ibcon#read 5, iclass 13, count 2 2006.225.07:44:39.37#ibcon#about to read 6, iclass 13, count 2 2006.225.07:44:39.37#ibcon#read 6, iclass 13, count 2 2006.225.07:44:39.37#ibcon#end of sib2, iclass 13, count 2 2006.225.07:44:39.37#ibcon#*mode == 0, iclass 13, count 2 2006.225.07:44:39.37#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.07:44:39.37#ibcon#[25=AT05-07\r\n] 2006.225.07:44:39.37#ibcon#*before write, iclass 13, count 2 2006.225.07:44:39.37#ibcon#enter sib2, iclass 13, count 2 2006.225.07:44:39.37#ibcon#flushed, iclass 13, count 2 2006.225.07:44:39.37#ibcon#about to write, iclass 13, count 2 2006.225.07:44:39.37#ibcon#wrote, iclass 13, count 2 2006.225.07:44:39.37#ibcon#about to read 3, iclass 13, count 2 2006.225.07:44:39.40#ibcon#read 3, iclass 13, count 2 2006.225.07:44:39.40#ibcon#about to read 4, iclass 13, count 2 2006.225.07:44:39.40#ibcon#read 4, iclass 13, count 2 2006.225.07:44:39.40#ibcon#about to read 5, iclass 13, count 2 2006.225.07:44:39.40#ibcon#read 5, iclass 13, count 2 2006.225.07:44:39.40#ibcon#about to read 6, iclass 13, count 2 2006.225.07:44:39.40#ibcon#read 6, iclass 13, count 2 2006.225.07:44:39.40#ibcon#end of sib2, iclass 13, count 2 2006.225.07:44:39.40#ibcon#*after write, iclass 13, count 2 2006.225.07:44:39.40#ibcon#*before return 0, iclass 13, count 2 2006.225.07:44:39.40#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:44:39.40#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:44:39.40#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.07:44:39.40#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:39.40#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:44:39.52#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:44:39.52#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:44:39.52#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:44:39.52#ibcon#first serial, iclass 13, count 0 2006.225.07:44:39.52#ibcon#enter sib2, iclass 13, count 0 2006.225.07:44:39.52#ibcon#flushed, iclass 13, count 0 2006.225.07:44:39.52#ibcon#about to write, iclass 13, count 0 2006.225.07:44:39.52#ibcon#wrote, iclass 13, count 0 2006.225.07:44:39.52#ibcon#about to read 3, iclass 13, count 0 2006.225.07:44:39.54#ibcon#read 3, iclass 13, count 0 2006.225.07:44:39.54#ibcon#about to read 4, iclass 13, count 0 2006.225.07:44:39.54#ibcon#read 4, iclass 13, count 0 2006.225.07:44:39.54#ibcon#about to read 5, iclass 13, count 0 2006.225.07:44:39.54#ibcon#read 5, iclass 13, count 0 2006.225.07:44:39.54#ibcon#about to read 6, iclass 13, count 0 2006.225.07:44:39.54#ibcon#read 6, iclass 13, count 0 2006.225.07:44:39.54#ibcon#end of sib2, iclass 13, count 0 2006.225.07:44:39.54#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:44:39.54#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:44:39.54#ibcon#[25=USB\r\n] 2006.225.07:44:39.54#ibcon#*before write, iclass 13, count 0 2006.225.07:44:39.54#ibcon#enter sib2, iclass 13, count 0 2006.225.07:44:39.54#ibcon#flushed, iclass 13, count 0 2006.225.07:44:39.54#ibcon#about to write, iclass 13, count 0 2006.225.07:44:39.54#ibcon#wrote, iclass 13, count 0 2006.225.07:44:39.54#ibcon#about to read 3, iclass 13, count 0 2006.225.07:44:39.57#ibcon#read 3, iclass 13, count 0 2006.225.07:44:39.57#ibcon#about to read 4, iclass 13, count 0 2006.225.07:44:39.57#ibcon#read 4, iclass 13, count 0 2006.225.07:44:39.57#ibcon#about to read 5, iclass 13, count 0 2006.225.07:44:39.57#ibcon#read 5, iclass 13, count 0 2006.225.07:44:39.57#ibcon#about to read 6, iclass 13, count 0 2006.225.07:44:39.57#ibcon#read 6, iclass 13, count 0 2006.225.07:44:39.57#ibcon#end of sib2, iclass 13, count 0 2006.225.07:44:39.57#ibcon#*after write, iclass 13, count 0 2006.225.07:44:39.57#ibcon#*before return 0, iclass 13, count 0 2006.225.07:44:39.57#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:44:39.57#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:44:39.57#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:44:39.57#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:44:39.57$vc4f8/valo=6,772.99 2006.225.07:44:39.57#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.07:44:39.57#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.07:44:39.57#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:39.57#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:44:39.57#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:44:39.57#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:44:39.57#ibcon#enter wrdev, iclass 15, count 0 2006.225.07:44:39.57#ibcon#first serial, iclass 15, count 0 2006.225.07:44:39.57#ibcon#enter sib2, iclass 15, count 0 2006.225.07:44:39.57#ibcon#flushed, iclass 15, count 0 2006.225.07:44:39.57#ibcon#about to write, iclass 15, count 0 2006.225.07:44:39.57#ibcon#wrote, iclass 15, count 0 2006.225.07:44:39.57#ibcon#about to read 3, iclass 15, count 0 2006.225.07:44:39.60#ibcon#read 3, iclass 15, count 0 2006.225.07:44:39.60#ibcon#about to read 4, iclass 15, count 0 2006.225.07:44:39.60#ibcon#read 4, iclass 15, count 0 2006.225.07:44:39.60#ibcon#about to read 5, iclass 15, count 0 2006.225.07:44:39.60#ibcon#read 5, iclass 15, count 0 2006.225.07:44:39.60#ibcon#about to read 6, iclass 15, count 0 2006.225.07:44:39.60#ibcon#read 6, iclass 15, count 0 2006.225.07:44:39.60#ibcon#end of sib2, iclass 15, count 0 2006.225.07:44:39.60#ibcon#*mode == 0, iclass 15, count 0 2006.225.07:44:39.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.07:44:39.60#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:44:39.60#ibcon#*before write, iclass 15, count 0 2006.225.07:44:39.60#ibcon#enter sib2, iclass 15, count 0 2006.225.07:44:39.60#ibcon#flushed, iclass 15, count 0 2006.225.07:44:39.60#ibcon#about to write, iclass 15, count 0 2006.225.07:44:39.60#ibcon#wrote, iclass 15, count 0 2006.225.07:44:39.60#ibcon#about to read 3, iclass 15, count 0 2006.225.07:44:39.64#ibcon#read 3, iclass 15, count 0 2006.225.07:44:39.64#ibcon#about to read 4, iclass 15, count 0 2006.225.07:44:39.64#ibcon#read 4, iclass 15, count 0 2006.225.07:44:39.64#ibcon#about to read 5, iclass 15, count 0 2006.225.07:44:39.64#ibcon#read 5, iclass 15, count 0 2006.225.07:44:39.64#ibcon#about to read 6, iclass 15, count 0 2006.225.07:44:39.64#ibcon#read 6, iclass 15, count 0 2006.225.07:44:39.64#ibcon#end of sib2, iclass 15, count 0 2006.225.07:44:39.64#ibcon#*after write, iclass 15, count 0 2006.225.07:44:39.64#ibcon#*before return 0, iclass 15, count 0 2006.225.07:44:39.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:44:39.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:44:39.64#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.07:44:39.64#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.07:44:39.64$vc4f8/va=6,6 2006.225.07:44:39.64#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.07:44:39.64#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.07:44:39.64#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:39.64#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:44:39.69#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:44:39.69#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:44:39.69#ibcon#enter wrdev, iclass 17, count 2 2006.225.07:44:39.69#ibcon#first serial, iclass 17, count 2 2006.225.07:44:39.69#ibcon#enter sib2, iclass 17, count 2 2006.225.07:44:39.69#ibcon#flushed, iclass 17, count 2 2006.225.07:44:39.69#ibcon#about to write, iclass 17, count 2 2006.225.07:44:39.69#ibcon#wrote, iclass 17, count 2 2006.225.07:44:39.69#ibcon#about to read 3, iclass 17, count 2 2006.225.07:44:39.71#ibcon#read 3, iclass 17, count 2 2006.225.07:44:39.71#ibcon#about to read 4, iclass 17, count 2 2006.225.07:44:39.71#ibcon#read 4, iclass 17, count 2 2006.225.07:44:39.71#ibcon#about to read 5, iclass 17, count 2 2006.225.07:44:39.71#ibcon#read 5, iclass 17, count 2 2006.225.07:44:39.71#ibcon#about to read 6, iclass 17, count 2 2006.225.07:44:39.71#ibcon#read 6, iclass 17, count 2 2006.225.07:44:39.71#ibcon#end of sib2, iclass 17, count 2 2006.225.07:44:39.71#ibcon#*mode == 0, iclass 17, count 2 2006.225.07:44:39.71#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.07:44:39.71#ibcon#[25=AT06-06\r\n] 2006.225.07:44:39.71#ibcon#*before write, iclass 17, count 2 2006.225.07:44:39.71#ibcon#enter sib2, iclass 17, count 2 2006.225.07:44:39.71#ibcon#flushed, iclass 17, count 2 2006.225.07:44:39.71#ibcon#about to write, iclass 17, count 2 2006.225.07:44:39.71#ibcon#wrote, iclass 17, count 2 2006.225.07:44:39.71#ibcon#about to read 3, iclass 17, count 2 2006.225.07:44:39.74#ibcon#read 3, iclass 17, count 2 2006.225.07:44:39.74#ibcon#about to read 4, iclass 17, count 2 2006.225.07:44:39.74#ibcon#read 4, iclass 17, count 2 2006.225.07:44:39.74#ibcon#about to read 5, iclass 17, count 2 2006.225.07:44:39.74#ibcon#read 5, iclass 17, count 2 2006.225.07:44:39.74#ibcon#about to read 6, iclass 17, count 2 2006.225.07:44:39.74#ibcon#read 6, iclass 17, count 2 2006.225.07:44:39.74#ibcon#end of sib2, iclass 17, count 2 2006.225.07:44:39.74#ibcon#*after write, iclass 17, count 2 2006.225.07:44:39.74#ibcon#*before return 0, iclass 17, count 2 2006.225.07:44:39.74#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:44:39.74#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:44:39.74#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.07:44:39.74#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:39.74#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:44:39.86#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:44:39.86#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:44:39.86#ibcon#enter wrdev, iclass 17, count 0 2006.225.07:44:39.86#ibcon#first serial, iclass 17, count 0 2006.225.07:44:39.86#ibcon#enter sib2, iclass 17, count 0 2006.225.07:44:39.86#ibcon#flushed, iclass 17, count 0 2006.225.07:44:39.86#ibcon#about to write, iclass 17, count 0 2006.225.07:44:39.86#ibcon#wrote, iclass 17, count 0 2006.225.07:44:39.86#ibcon#about to read 3, iclass 17, count 0 2006.225.07:44:39.88#ibcon#read 3, iclass 17, count 0 2006.225.07:44:39.88#ibcon#about to read 4, iclass 17, count 0 2006.225.07:44:39.88#ibcon#read 4, iclass 17, count 0 2006.225.07:44:39.88#ibcon#about to read 5, iclass 17, count 0 2006.225.07:44:39.88#ibcon#read 5, iclass 17, count 0 2006.225.07:44:39.88#ibcon#about to read 6, iclass 17, count 0 2006.225.07:44:39.88#ibcon#read 6, iclass 17, count 0 2006.225.07:44:39.88#ibcon#end of sib2, iclass 17, count 0 2006.225.07:44:39.88#ibcon#*mode == 0, iclass 17, count 0 2006.225.07:44:39.88#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.07:44:39.88#ibcon#[25=USB\r\n] 2006.225.07:44:39.88#ibcon#*before write, iclass 17, count 0 2006.225.07:44:39.88#ibcon#enter sib2, iclass 17, count 0 2006.225.07:44:39.88#ibcon#flushed, iclass 17, count 0 2006.225.07:44:39.88#ibcon#about to write, iclass 17, count 0 2006.225.07:44:39.88#ibcon#wrote, iclass 17, count 0 2006.225.07:44:39.88#ibcon#about to read 3, iclass 17, count 0 2006.225.07:44:39.91#ibcon#read 3, iclass 17, count 0 2006.225.07:44:39.91#ibcon#about to read 4, iclass 17, count 0 2006.225.07:44:39.91#ibcon#read 4, iclass 17, count 0 2006.225.07:44:39.91#ibcon#about to read 5, iclass 17, count 0 2006.225.07:44:39.91#ibcon#read 5, iclass 17, count 0 2006.225.07:44:39.91#ibcon#about to read 6, iclass 17, count 0 2006.225.07:44:39.91#ibcon#read 6, iclass 17, count 0 2006.225.07:44:39.91#ibcon#end of sib2, iclass 17, count 0 2006.225.07:44:39.91#ibcon#*after write, iclass 17, count 0 2006.225.07:44:39.91#ibcon#*before return 0, iclass 17, count 0 2006.225.07:44:39.91#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:44:39.91#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:44:39.91#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.07:44:39.91#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.07:44:39.91$vc4f8/valo=7,832.99 2006.225.07:44:39.91#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.07:44:39.91#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.07:44:39.91#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:39.91#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:44:39.91#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:44:39.91#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:44:39.91#ibcon#enter wrdev, iclass 19, count 0 2006.225.07:44:39.91#ibcon#first serial, iclass 19, count 0 2006.225.07:44:39.91#ibcon#enter sib2, iclass 19, count 0 2006.225.07:44:39.91#ibcon#flushed, iclass 19, count 0 2006.225.07:44:39.91#ibcon#about to write, iclass 19, count 0 2006.225.07:44:39.91#ibcon#wrote, iclass 19, count 0 2006.225.07:44:39.91#ibcon#about to read 3, iclass 19, count 0 2006.225.07:44:39.93#ibcon#read 3, iclass 19, count 0 2006.225.07:44:39.93#ibcon#about to read 4, iclass 19, count 0 2006.225.07:44:39.93#ibcon#read 4, iclass 19, count 0 2006.225.07:44:39.93#ibcon#about to read 5, iclass 19, count 0 2006.225.07:44:39.93#ibcon#read 5, iclass 19, count 0 2006.225.07:44:39.93#ibcon#about to read 6, iclass 19, count 0 2006.225.07:44:39.93#ibcon#read 6, iclass 19, count 0 2006.225.07:44:39.93#ibcon#end of sib2, iclass 19, count 0 2006.225.07:44:39.93#ibcon#*mode == 0, iclass 19, count 0 2006.225.07:44:39.93#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.07:44:39.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:44:39.93#ibcon#*before write, iclass 19, count 0 2006.225.07:44:39.93#ibcon#enter sib2, iclass 19, count 0 2006.225.07:44:39.93#ibcon#flushed, iclass 19, count 0 2006.225.07:44:39.93#ibcon#about to write, iclass 19, count 0 2006.225.07:44:39.93#ibcon#wrote, iclass 19, count 0 2006.225.07:44:39.93#ibcon#about to read 3, iclass 19, count 0 2006.225.07:44:39.97#ibcon#read 3, iclass 19, count 0 2006.225.07:44:39.97#ibcon#about to read 4, iclass 19, count 0 2006.225.07:44:39.97#ibcon#read 4, iclass 19, count 0 2006.225.07:44:39.97#ibcon#about to read 5, iclass 19, count 0 2006.225.07:44:39.97#ibcon#read 5, iclass 19, count 0 2006.225.07:44:39.97#ibcon#about to read 6, iclass 19, count 0 2006.225.07:44:39.97#ibcon#read 6, iclass 19, count 0 2006.225.07:44:39.97#ibcon#end of sib2, iclass 19, count 0 2006.225.07:44:39.97#ibcon#*after write, iclass 19, count 0 2006.225.07:44:39.97#ibcon#*before return 0, iclass 19, count 0 2006.225.07:44:39.97#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:44:39.97#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:44:39.97#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.07:44:39.97#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.07:44:39.97$vc4f8/va=7,6 2006.225.07:44:39.97#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.225.07:44:39.97#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.225.07:44:39.97#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:39.97#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:44:40.03#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:44:40.03#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:44:40.03#ibcon#enter wrdev, iclass 21, count 2 2006.225.07:44:40.03#ibcon#first serial, iclass 21, count 2 2006.225.07:44:40.03#ibcon#enter sib2, iclass 21, count 2 2006.225.07:44:40.03#ibcon#flushed, iclass 21, count 2 2006.225.07:44:40.03#ibcon#about to write, iclass 21, count 2 2006.225.07:44:40.03#ibcon#wrote, iclass 21, count 2 2006.225.07:44:40.03#ibcon#about to read 3, iclass 21, count 2 2006.225.07:44:40.05#ibcon#read 3, iclass 21, count 2 2006.225.07:44:40.05#ibcon#about to read 4, iclass 21, count 2 2006.225.07:44:40.05#ibcon#read 4, iclass 21, count 2 2006.225.07:44:40.05#ibcon#about to read 5, iclass 21, count 2 2006.225.07:44:40.05#ibcon#read 5, iclass 21, count 2 2006.225.07:44:40.05#ibcon#about to read 6, iclass 21, count 2 2006.225.07:44:40.05#ibcon#read 6, iclass 21, count 2 2006.225.07:44:40.05#ibcon#end of sib2, iclass 21, count 2 2006.225.07:44:40.05#ibcon#*mode == 0, iclass 21, count 2 2006.225.07:44:40.05#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.225.07:44:40.05#ibcon#[25=AT07-06\r\n] 2006.225.07:44:40.05#ibcon#*before write, iclass 21, count 2 2006.225.07:44:40.05#ibcon#enter sib2, iclass 21, count 2 2006.225.07:44:40.05#ibcon#flushed, iclass 21, count 2 2006.225.07:44:40.05#ibcon#about to write, iclass 21, count 2 2006.225.07:44:40.05#ibcon#wrote, iclass 21, count 2 2006.225.07:44:40.05#ibcon#about to read 3, iclass 21, count 2 2006.225.07:44:40.08#ibcon#read 3, iclass 21, count 2 2006.225.07:44:40.08#ibcon#about to read 4, iclass 21, count 2 2006.225.07:44:40.08#ibcon#read 4, iclass 21, count 2 2006.225.07:44:40.08#ibcon#about to read 5, iclass 21, count 2 2006.225.07:44:40.08#ibcon#read 5, iclass 21, count 2 2006.225.07:44:40.08#ibcon#about to read 6, iclass 21, count 2 2006.225.07:44:40.08#ibcon#read 6, iclass 21, count 2 2006.225.07:44:40.08#ibcon#end of sib2, iclass 21, count 2 2006.225.07:44:40.08#ibcon#*after write, iclass 21, count 2 2006.225.07:44:40.08#ibcon#*before return 0, iclass 21, count 2 2006.225.07:44:40.08#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:44:40.08#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:44:40.08#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.225.07:44:40.08#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:40.08#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:44:40.20#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:44:40.20#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:44:40.20#ibcon#enter wrdev, iclass 21, count 0 2006.225.07:44:40.20#ibcon#first serial, iclass 21, count 0 2006.225.07:44:40.20#ibcon#enter sib2, iclass 21, count 0 2006.225.07:44:40.20#ibcon#flushed, iclass 21, count 0 2006.225.07:44:40.20#ibcon#about to write, iclass 21, count 0 2006.225.07:44:40.20#ibcon#wrote, iclass 21, count 0 2006.225.07:44:40.20#ibcon#about to read 3, iclass 21, count 0 2006.225.07:44:40.22#ibcon#read 3, iclass 21, count 0 2006.225.07:44:40.22#ibcon#about to read 4, iclass 21, count 0 2006.225.07:44:40.22#ibcon#read 4, iclass 21, count 0 2006.225.07:44:40.22#ibcon#about to read 5, iclass 21, count 0 2006.225.07:44:40.22#ibcon#read 5, iclass 21, count 0 2006.225.07:44:40.22#ibcon#about to read 6, iclass 21, count 0 2006.225.07:44:40.22#ibcon#read 6, iclass 21, count 0 2006.225.07:44:40.22#ibcon#end of sib2, iclass 21, count 0 2006.225.07:44:40.22#ibcon#*mode == 0, iclass 21, count 0 2006.225.07:44:40.22#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.07:44:40.22#ibcon#[25=USB\r\n] 2006.225.07:44:40.22#ibcon#*before write, iclass 21, count 0 2006.225.07:44:40.22#ibcon#enter sib2, iclass 21, count 0 2006.225.07:44:40.22#ibcon#flushed, iclass 21, count 0 2006.225.07:44:40.22#ibcon#about to write, iclass 21, count 0 2006.225.07:44:40.22#ibcon#wrote, iclass 21, count 0 2006.225.07:44:40.22#ibcon#about to read 3, iclass 21, count 0 2006.225.07:44:40.25#ibcon#read 3, iclass 21, count 0 2006.225.07:44:40.25#ibcon#about to read 4, iclass 21, count 0 2006.225.07:44:40.25#ibcon#read 4, iclass 21, count 0 2006.225.07:44:40.25#ibcon#about to read 5, iclass 21, count 0 2006.225.07:44:40.25#ibcon#read 5, iclass 21, count 0 2006.225.07:44:40.25#ibcon#about to read 6, iclass 21, count 0 2006.225.07:44:40.25#ibcon#read 6, iclass 21, count 0 2006.225.07:44:40.25#ibcon#end of sib2, iclass 21, count 0 2006.225.07:44:40.25#ibcon#*after write, iclass 21, count 0 2006.225.07:44:40.25#ibcon#*before return 0, iclass 21, count 0 2006.225.07:44:40.25#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:44:40.25#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:44:40.25#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.07:44:40.25#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.07:44:40.25$vc4f8/valo=8,852.99 2006.225.07:44:40.25#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.225.07:44:40.25#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.225.07:44:40.25#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:40.25#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:44:40.25#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:44:40.25#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:44:40.25#ibcon#enter wrdev, iclass 23, count 0 2006.225.07:44:40.25#ibcon#first serial, iclass 23, count 0 2006.225.07:44:40.25#ibcon#enter sib2, iclass 23, count 0 2006.225.07:44:40.25#ibcon#flushed, iclass 23, count 0 2006.225.07:44:40.25#ibcon#about to write, iclass 23, count 0 2006.225.07:44:40.25#ibcon#wrote, iclass 23, count 0 2006.225.07:44:40.25#ibcon#about to read 3, iclass 23, count 0 2006.225.07:44:40.27#ibcon#read 3, iclass 23, count 0 2006.225.07:44:40.27#ibcon#about to read 4, iclass 23, count 0 2006.225.07:44:40.27#ibcon#read 4, iclass 23, count 0 2006.225.07:44:40.27#ibcon#about to read 5, iclass 23, count 0 2006.225.07:44:40.27#ibcon#read 5, iclass 23, count 0 2006.225.07:44:40.27#ibcon#about to read 6, iclass 23, count 0 2006.225.07:44:40.27#ibcon#read 6, iclass 23, count 0 2006.225.07:44:40.27#ibcon#end of sib2, iclass 23, count 0 2006.225.07:44:40.27#ibcon#*mode == 0, iclass 23, count 0 2006.225.07:44:40.27#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.07:44:40.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:44:40.27#ibcon#*before write, iclass 23, count 0 2006.225.07:44:40.27#ibcon#enter sib2, iclass 23, count 0 2006.225.07:44:40.27#ibcon#flushed, iclass 23, count 0 2006.225.07:44:40.27#ibcon#about to write, iclass 23, count 0 2006.225.07:44:40.27#ibcon#wrote, iclass 23, count 0 2006.225.07:44:40.27#ibcon#about to read 3, iclass 23, count 0 2006.225.07:44:40.31#ibcon#read 3, iclass 23, count 0 2006.225.07:44:40.31#ibcon#about to read 4, iclass 23, count 0 2006.225.07:44:40.31#ibcon#read 4, iclass 23, count 0 2006.225.07:44:40.31#ibcon#about to read 5, iclass 23, count 0 2006.225.07:44:40.31#ibcon#read 5, iclass 23, count 0 2006.225.07:44:40.31#ibcon#about to read 6, iclass 23, count 0 2006.225.07:44:40.31#ibcon#read 6, iclass 23, count 0 2006.225.07:44:40.31#ibcon#end of sib2, iclass 23, count 0 2006.225.07:44:40.31#ibcon#*after write, iclass 23, count 0 2006.225.07:44:40.31#ibcon#*before return 0, iclass 23, count 0 2006.225.07:44:40.31#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:44:40.31#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:44:40.31#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.07:44:40.31#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.07:44:40.31$vc4f8/va=8,7 2006.225.07:44:40.31#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.225.07:44:40.31#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.225.07:44:40.31#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:40.31#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:44:40.37#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:44:40.37#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:44:40.37#ibcon#enter wrdev, iclass 25, count 2 2006.225.07:44:40.37#ibcon#first serial, iclass 25, count 2 2006.225.07:44:40.37#ibcon#enter sib2, iclass 25, count 2 2006.225.07:44:40.37#ibcon#flushed, iclass 25, count 2 2006.225.07:44:40.37#ibcon#about to write, iclass 25, count 2 2006.225.07:44:40.37#ibcon#wrote, iclass 25, count 2 2006.225.07:44:40.37#ibcon#about to read 3, iclass 25, count 2 2006.225.07:44:40.39#ibcon#read 3, iclass 25, count 2 2006.225.07:44:40.39#ibcon#about to read 4, iclass 25, count 2 2006.225.07:44:40.39#ibcon#read 4, iclass 25, count 2 2006.225.07:44:40.39#ibcon#about to read 5, iclass 25, count 2 2006.225.07:44:40.39#ibcon#read 5, iclass 25, count 2 2006.225.07:44:40.39#ibcon#about to read 6, iclass 25, count 2 2006.225.07:44:40.39#ibcon#read 6, iclass 25, count 2 2006.225.07:44:40.39#ibcon#end of sib2, iclass 25, count 2 2006.225.07:44:40.39#ibcon#*mode == 0, iclass 25, count 2 2006.225.07:44:40.39#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.225.07:44:40.39#ibcon#[25=AT08-07\r\n] 2006.225.07:44:40.39#ibcon#*before write, iclass 25, count 2 2006.225.07:44:40.39#ibcon#enter sib2, iclass 25, count 2 2006.225.07:44:40.39#ibcon#flushed, iclass 25, count 2 2006.225.07:44:40.39#ibcon#about to write, iclass 25, count 2 2006.225.07:44:40.39#ibcon#wrote, iclass 25, count 2 2006.225.07:44:40.39#ibcon#about to read 3, iclass 25, count 2 2006.225.07:44:40.42#ibcon#read 3, iclass 25, count 2 2006.225.07:44:40.42#ibcon#about to read 4, iclass 25, count 2 2006.225.07:44:40.42#ibcon#read 4, iclass 25, count 2 2006.225.07:44:40.42#ibcon#about to read 5, iclass 25, count 2 2006.225.07:44:40.42#ibcon#read 5, iclass 25, count 2 2006.225.07:44:40.42#ibcon#about to read 6, iclass 25, count 2 2006.225.07:44:40.42#ibcon#read 6, iclass 25, count 2 2006.225.07:44:40.42#ibcon#end of sib2, iclass 25, count 2 2006.225.07:44:40.42#ibcon#*after write, iclass 25, count 2 2006.225.07:44:40.42#ibcon#*before return 0, iclass 25, count 2 2006.225.07:44:40.42#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:44:40.42#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:44:40.42#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.225.07:44:40.42#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:40.42#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:44:40.54#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:44:40.54#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:44:40.54#ibcon#enter wrdev, iclass 25, count 0 2006.225.07:44:40.54#ibcon#first serial, iclass 25, count 0 2006.225.07:44:40.54#ibcon#enter sib2, iclass 25, count 0 2006.225.07:44:40.54#ibcon#flushed, iclass 25, count 0 2006.225.07:44:40.54#ibcon#about to write, iclass 25, count 0 2006.225.07:44:40.54#ibcon#wrote, iclass 25, count 0 2006.225.07:44:40.54#ibcon#about to read 3, iclass 25, count 0 2006.225.07:44:40.56#ibcon#read 3, iclass 25, count 0 2006.225.07:44:40.56#ibcon#about to read 4, iclass 25, count 0 2006.225.07:44:40.56#ibcon#read 4, iclass 25, count 0 2006.225.07:44:40.56#ibcon#about to read 5, iclass 25, count 0 2006.225.07:44:40.56#ibcon#read 5, iclass 25, count 0 2006.225.07:44:40.56#ibcon#about to read 6, iclass 25, count 0 2006.225.07:44:40.56#ibcon#read 6, iclass 25, count 0 2006.225.07:44:40.56#ibcon#end of sib2, iclass 25, count 0 2006.225.07:44:40.56#ibcon#*mode == 0, iclass 25, count 0 2006.225.07:44:40.56#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.07:44:40.56#ibcon#[25=USB\r\n] 2006.225.07:44:40.56#ibcon#*before write, iclass 25, count 0 2006.225.07:44:40.56#ibcon#enter sib2, iclass 25, count 0 2006.225.07:44:40.56#ibcon#flushed, iclass 25, count 0 2006.225.07:44:40.56#ibcon#about to write, iclass 25, count 0 2006.225.07:44:40.56#ibcon#wrote, iclass 25, count 0 2006.225.07:44:40.56#ibcon#about to read 3, iclass 25, count 0 2006.225.07:44:40.59#ibcon#read 3, iclass 25, count 0 2006.225.07:44:40.59#ibcon#about to read 4, iclass 25, count 0 2006.225.07:44:40.59#ibcon#read 4, iclass 25, count 0 2006.225.07:44:40.59#ibcon#about to read 5, iclass 25, count 0 2006.225.07:44:40.59#ibcon#read 5, iclass 25, count 0 2006.225.07:44:40.59#ibcon#about to read 6, iclass 25, count 0 2006.225.07:44:40.59#ibcon#read 6, iclass 25, count 0 2006.225.07:44:40.59#ibcon#end of sib2, iclass 25, count 0 2006.225.07:44:40.59#ibcon#*after write, iclass 25, count 0 2006.225.07:44:40.59#ibcon#*before return 0, iclass 25, count 0 2006.225.07:44:40.59#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:44:40.59#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:44:40.59#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.07:44:40.59#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.07:44:40.59$vc4f8/vblo=1,632.99 2006.225.07:44:40.59#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.07:44:40.59#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.07:44:40.59#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:40.59#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:44:40.59#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:44:40.59#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:44:40.59#ibcon#enter wrdev, iclass 27, count 0 2006.225.07:44:40.59#ibcon#first serial, iclass 27, count 0 2006.225.07:44:40.59#ibcon#enter sib2, iclass 27, count 0 2006.225.07:44:40.59#ibcon#flushed, iclass 27, count 0 2006.225.07:44:40.59#ibcon#about to write, iclass 27, count 0 2006.225.07:44:40.59#ibcon#wrote, iclass 27, count 0 2006.225.07:44:40.59#ibcon#about to read 3, iclass 27, count 0 2006.225.07:44:40.61#ibcon#read 3, iclass 27, count 0 2006.225.07:44:40.61#ibcon#about to read 4, iclass 27, count 0 2006.225.07:44:40.61#ibcon#read 4, iclass 27, count 0 2006.225.07:44:40.61#ibcon#about to read 5, iclass 27, count 0 2006.225.07:44:40.61#ibcon#read 5, iclass 27, count 0 2006.225.07:44:40.61#ibcon#about to read 6, iclass 27, count 0 2006.225.07:44:40.61#ibcon#read 6, iclass 27, count 0 2006.225.07:44:40.61#ibcon#end of sib2, iclass 27, count 0 2006.225.07:44:40.61#ibcon#*mode == 0, iclass 27, count 0 2006.225.07:44:40.61#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.07:44:40.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:44:40.61#ibcon#*before write, iclass 27, count 0 2006.225.07:44:40.61#ibcon#enter sib2, iclass 27, count 0 2006.225.07:44:40.61#ibcon#flushed, iclass 27, count 0 2006.225.07:44:40.61#ibcon#about to write, iclass 27, count 0 2006.225.07:44:40.61#ibcon#wrote, iclass 27, count 0 2006.225.07:44:40.61#ibcon#about to read 3, iclass 27, count 0 2006.225.07:44:40.65#ibcon#read 3, iclass 27, count 0 2006.225.07:44:40.65#ibcon#about to read 4, iclass 27, count 0 2006.225.07:44:40.65#ibcon#read 4, iclass 27, count 0 2006.225.07:44:40.65#ibcon#about to read 5, iclass 27, count 0 2006.225.07:44:40.65#ibcon#read 5, iclass 27, count 0 2006.225.07:44:40.65#ibcon#about to read 6, iclass 27, count 0 2006.225.07:44:40.65#ibcon#read 6, iclass 27, count 0 2006.225.07:44:40.65#ibcon#end of sib2, iclass 27, count 0 2006.225.07:44:40.65#ibcon#*after write, iclass 27, count 0 2006.225.07:44:40.65#ibcon#*before return 0, iclass 27, count 0 2006.225.07:44:40.65#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:44:40.65#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:44:40.65#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.07:44:40.65#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.07:44:40.65$vc4f8/vb=1,4 2006.225.07:44:40.65#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.225.07:44:40.65#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.225.07:44:40.65#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:40.65#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:44:40.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:44:40.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:44:40.65#ibcon#enter wrdev, iclass 29, count 2 2006.225.07:44:40.65#ibcon#first serial, iclass 29, count 2 2006.225.07:44:40.65#ibcon#enter sib2, iclass 29, count 2 2006.225.07:44:40.65#ibcon#flushed, iclass 29, count 2 2006.225.07:44:40.65#ibcon#about to write, iclass 29, count 2 2006.225.07:44:40.65#ibcon#wrote, iclass 29, count 2 2006.225.07:44:40.65#ibcon#about to read 3, iclass 29, count 2 2006.225.07:44:40.67#ibcon#read 3, iclass 29, count 2 2006.225.07:44:40.67#ibcon#about to read 4, iclass 29, count 2 2006.225.07:44:40.67#ibcon#read 4, iclass 29, count 2 2006.225.07:44:40.67#ibcon#about to read 5, iclass 29, count 2 2006.225.07:44:40.67#ibcon#read 5, iclass 29, count 2 2006.225.07:44:40.67#ibcon#about to read 6, iclass 29, count 2 2006.225.07:44:40.67#ibcon#read 6, iclass 29, count 2 2006.225.07:44:40.67#ibcon#end of sib2, iclass 29, count 2 2006.225.07:44:40.67#ibcon#*mode == 0, iclass 29, count 2 2006.225.07:44:40.67#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.225.07:44:40.67#ibcon#[27=AT01-04\r\n] 2006.225.07:44:40.67#ibcon#*before write, iclass 29, count 2 2006.225.07:44:40.67#ibcon#enter sib2, iclass 29, count 2 2006.225.07:44:40.67#ibcon#flushed, iclass 29, count 2 2006.225.07:44:40.67#ibcon#about to write, iclass 29, count 2 2006.225.07:44:40.67#ibcon#wrote, iclass 29, count 2 2006.225.07:44:40.67#ibcon#about to read 3, iclass 29, count 2 2006.225.07:44:40.70#ibcon#read 3, iclass 29, count 2 2006.225.07:44:40.70#ibcon#about to read 4, iclass 29, count 2 2006.225.07:44:40.70#ibcon#read 4, iclass 29, count 2 2006.225.07:44:40.70#ibcon#about to read 5, iclass 29, count 2 2006.225.07:44:40.70#ibcon#read 5, iclass 29, count 2 2006.225.07:44:40.70#ibcon#about to read 6, iclass 29, count 2 2006.225.07:44:40.70#ibcon#read 6, iclass 29, count 2 2006.225.07:44:40.70#ibcon#end of sib2, iclass 29, count 2 2006.225.07:44:40.70#ibcon#*after write, iclass 29, count 2 2006.225.07:44:40.70#ibcon#*before return 0, iclass 29, count 2 2006.225.07:44:40.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:44:40.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:44:40.70#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.225.07:44:40.70#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:40.70#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:44:40.82#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:44:40.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:44:40.82#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:44:40.82#ibcon#first serial, iclass 29, count 0 2006.225.07:44:40.82#ibcon#enter sib2, iclass 29, count 0 2006.225.07:44:40.82#ibcon#flushed, iclass 29, count 0 2006.225.07:44:40.82#ibcon#about to write, iclass 29, count 0 2006.225.07:44:40.82#ibcon#wrote, iclass 29, count 0 2006.225.07:44:40.82#ibcon#about to read 3, iclass 29, count 0 2006.225.07:44:40.84#ibcon#read 3, iclass 29, count 0 2006.225.07:44:40.84#ibcon#about to read 4, iclass 29, count 0 2006.225.07:44:40.84#ibcon#read 4, iclass 29, count 0 2006.225.07:44:40.84#ibcon#about to read 5, iclass 29, count 0 2006.225.07:44:40.84#ibcon#read 5, iclass 29, count 0 2006.225.07:44:40.84#ibcon#about to read 6, iclass 29, count 0 2006.225.07:44:40.84#ibcon#read 6, iclass 29, count 0 2006.225.07:44:40.84#ibcon#end of sib2, iclass 29, count 0 2006.225.07:44:40.84#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:44:40.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:44:40.84#ibcon#[27=USB\r\n] 2006.225.07:44:40.84#ibcon#*before write, iclass 29, count 0 2006.225.07:44:40.84#ibcon#enter sib2, iclass 29, count 0 2006.225.07:44:40.84#ibcon#flushed, iclass 29, count 0 2006.225.07:44:40.84#ibcon#about to write, iclass 29, count 0 2006.225.07:44:40.84#ibcon#wrote, iclass 29, count 0 2006.225.07:44:40.84#ibcon#about to read 3, iclass 29, count 0 2006.225.07:44:40.87#ibcon#read 3, iclass 29, count 0 2006.225.07:44:40.87#ibcon#about to read 4, iclass 29, count 0 2006.225.07:44:40.87#ibcon#read 4, iclass 29, count 0 2006.225.07:44:40.87#ibcon#about to read 5, iclass 29, count 0 2006.225.07:44:40.87#ibcon#read 5, iclass 29, count 0 2006.225.07:44:40.87#ibcon#about to read 6, iclass 29, count 0 2006.225.07:44:40.87#ibcon#read 6, iclass 29, count 0 2006.225.07:44:40.87#ibcon#end of sib2, iclass 29, count 0 2006.225.07:44:40.87#ibcon#*after write, iclass 29, count 0 2006.225.07:44:40.87#ibcon#*before return 0, iclass 29, count 0 2006.225.07:44:40.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:44:40.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:44:40.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:44:40.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:44:40.87$vc4f8/vblo=2,640.99 2006.225.07:44:40.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.07:44:40.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.07:44:40.87#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:40.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:44:40.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:44:40.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:44:40.87#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:44:40.87#ibcon#first serial, iclass 31, count 0 2006.225.07:44:40.87#ibcon#enter sib2, iclass 31, count 0 2006.225.07:44:40.87#ibcon#flushed, iclass 31, count 0 2006.225.07:44:40.87#ibcon#about to write, iclass 31, count 0 2006.225.07:44:40.87#ibcon#wrote, iclass 31, count 0 2006.225.07:44:40.87#ibcon#about to read 3, iclass 31, count 0 2006.225.07:44:40.89#ibcon#read 3, iclass 31, count 0 2006.225.07:44:40.89#ibcon#about to read 4, iclass 31, count 0 2006.225.07:44:40.89#ibcon#read 4, iclass 31, count 0 2006.225.07:44:40.89#ibcon#about to read 5, iclass 31, count 0 2006.225.07:44:40.89#ibcon#read 5, iclass 31, count 0 2006.225.07:44:40.89#ibcon#about to read 6, iclass 31, count 0 2006.225.07:44:40.89#ibcon#read 6, iclass 31, count 0 2006.225.07:44:40.89#ibcon#end of sib2, iclass 31, count 0 2006.225.07:44:40.89#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:44:40.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:44:40.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:44:40.89#ibcon#*before write, iclass 31, count 0 2006.225.07:44:40.89#ibcon#enter sib2, iclass 31, count 0 2006.225.07:44:40.89#ibcon#flushed, iclass 31, count 0 2006.225.07:44:40.89#ibcon#about to write, iclass 31, count 0 2006.225.07:44:40.89#ibcon#wrote, iclass 31, count 0 2006.225.07:44:40.89#ibcon#about to read 3, iclass 31, count 0 2006.225.07:44:40.93#ibcon#read 3, iclass 31, count 0 2006.225.07:44:40.93#ibcon#about to read 4, iclass 31, count 0 2006.225.07:44:40.93#ibcon#read 4, iclass 31, count 0 2006.225.07:44:40.93#ibcon#about to read 5, iclass 31, count 0 2006.225.07:44:40.93#ibcon#read 5, iclass 31, count 0 2006.225.07:44:40.93#ibcon#about to read 6, iclass 31, count 0 2006.225.07:44:40.93#ibcon#read 6, iclass 31, count 0 2006.225.07:44:40.93#ibcon#end of sib2, iclass 31, count 0 2006.225.07:44:40.93#ibcon#*after write, iclass 31, count 0 2006.225.07:44:40.93#ibcon#*before return 0, iclass 31, count 0 2006.225.07:44:40.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:44:40.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:44:40.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:44:40.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:44:40.93$vc4f8/vb=2,4 2006.225.07:44:40.93#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.225.07:44:40.93#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.225.07:44:40.93#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:40.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:44:40.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:44:40.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:44:40.99#ibcon#enter wrdev, iclass 33, count 2 2006.225.07:44:40.99#ibcon#first serial, iclass 33, count 2 2006.225.07:44:40.99#ibcon#enter sib2, iclass 33, count 2 2006.225.07:44:40.99#ibcon#flushed, iclass 33, count 2 2006.225.07:44:40.99#ibcon#about to write, iclass 33, count 2 2006.225.07:44:40.99#ibcon#wrote, iclass 33, count 2 2006.225.07:44:40.99#ibcon#about to read 3, iclass 33, count 2 2006.225.07:44:41.01#ibcon#read 3, iclass 33, count 2 2006.225.07:44:41.01#ibcon#about to read 4, iclass 33, count 2 2006.225.07:44:41.01#ibcon#read 4, iclass 33, count 2 2006.225.07:44:41.01#ibcon#about to read 5, iclass 33, count 2 2006.225.07:44:41.01#ibcon#read 5, iclass 33, count 2 2006.225.07:44:41.01#ibcon#about to read 6, iclass 33, count 2 2006.225.07:44:41.01#ibcon#read 6, iclass 33, count 2 2006.225.07:44:41.01#ibcon#end of sib2, iclass 33, count 2 2006.225.07:44:41.01#ibcon#*mode == 0, iclass 33, count 2 2006.225.07:44:41.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.225.07:44:41.01#ibcon#[27=AT02-04\r\n] 2006.225.07:44:41.01#ibcon#*before write, iclass 33, count 2 2006.225.07:44:41.01#ibcon#enter sib2, iclass 33, count 2 2006.225.07:44:41.01#ibcon#flushed, iclass 33, count 2 2006.225.07:44:41.01#ibcon#about to write, iclass 33, count 2 2006.225.07:44:41.01#ibcon#wrote, iclass 33, count 2 2006.225.07:44:41.01#ibcon#about to read 3, iclass 33, count 2 2006.225.07:44:41.04#ibcon#read 3, iclass 33, count 2 2006.225.07:44:41.04#ibcon#about to read 4, iclass 33, count 2 2006.225.07:44:41.04#ibcon#read 4, iclass 33, count 2 2006.225.07:44:41.04#ibcon#about to read 5, iclass 33, count 2 2006.225.07:44:41.04#ibcon#read 5, iclass 33, count 2 2006.225.07:44:41.04#ibcon#about to read 6, iclass 33, count 2 2006.225.07:44:41.04#ibcon#read 6, iclass 33, count 2 2006.225.07:44:41.04#ibcon#end of sib2, iclass 33, count 2 2006.225.07:44:41.04#ibcon#*after write, iclass 33, count 2 2006.225.07:44:41.04#ibcon#*before return 0, iclass 33, count 2 2006.225.07:44:41.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:44:41.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:44:41.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.225.07:44:41.04#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:41.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:44:41.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:44:41.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:44:41.16#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:44:41.16#ibcon#first serial, iclass 33, count 0 2006.225.07:44:41.16#ibcon#enter sib2, iclass 33, count 0 2006.225.07:44:41.16#ibcon#flushed, iclass 33, count 0 2006.225.07:44:41.16#ibcon#about to write, iclass 33, count 0 2006.225.07:44:41.16#ibcon#wrote, iclass 33, count 0 2006.225.07:44:41.16#ibcon#about to read 3, iclass 33, count 0 2006.225.07:44:41.18#ibcon#read 3, iclass 33, count 0 2006.225.07:44:41.18#ibcon#about to read 4, iclass 33, count 0 2006.225.07:44:41.18#ibcon#read 4, iclass 33, count 0 2006.225.07:44:41.18#ibcon#about to read 5, iclass 33, count 0 2006.225.07:44:41.18#ibcon#read 5, iclass 33, count 0 2006.225.07:44:41.18#ibcon#about to read 6, iclass 33, count 0 2006.225.07:44:41.18#ibcon#read 6, iclass 33, count 0 2006.225.07:44:41.18#ibcon#end of sib2, iclass 33, count 0 2006.225.07:44:41.18#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:44:41.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:44:41.18#ibcon#[27=USB\r\n] 2006.225.07:44:41.18#ibcon#*before write, iclass 33, count 0 2006.225.07:44:41.18#ibcon#enter sib2, iclass 33, count 0 2006.225.07:44:41.18#ibcon#flushed, iclass 33, count 0 2006.225.07:44:41.18#ibcon#about to write, iclass 33, count 0 2006.225.07:44:41.18#ibcon#wrote, iclass 33, count 0 2006.225.07:44:41.18#ibcon#about to read 3, iclass 33, count 0 2006.225.07:44:41.21#ibcon#read 3, iclass 33, count 0 2006.225.07:44:41.21#ibcon#about to read 4, iclass 33, count 0 2006.225.07:44:41.21#ibcon#read 4, iclass 33, count 0 2006.225.07:44:41.21#ibcon#about to read 5, iclass 33, count 0 2006.225.07:44:41.21#ibcon#read 5, iclass 33, count 0 2006.225.07:44:41.21#ibcon#about to read 6, iclass 33, count 0 2006.225.07:44:41.21#ibcon#read 6, iclass 33, count 0 2006.225.07:44:41.21#ibcon#end of sib2, iclass 33, count 0 2006.225.07:44:41.21#ibcon#*after write, iclass 33, count 0 2006.225.07:44:41.21#ibcon#*before return 0, iclass 33, count 0 2006.225.07:44:41.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:44:41.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:44:41.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:44:41.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:44:41.21$vc4f8/vblo=3,656.99 2006.225.07:44:41.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.225.07:44:41.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.225.07:44:41.21#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:41.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:44:41.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:44:41.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:44:41.21#ibcon#enter wrdev, iclass 35, count 0 2006.225.07:44:41.21#ibcon#first serial, iclass 35, count 0 2006.225.07:44:41.21#ibcon#enter sib2, iclass 35, count 0 2006.225.07:44:41.21#ibcon#flushed, iclass 35, count 0 2006.225.07:44:41.21#ibcon#about to write, iclass 35, count 0 2006.225.07:44:41.21#ibcon#wrote, iclass 35, count 0 2006.225.07:44:41.21#ibcon#about to read 3, iclass 35, count 0 2006.225.07:44:41.23#ibcon#read 3, iclass 35, count 0 2006.225.07:44:41.23#ibcon#about to read 4, iclass 35, count 0 2006.225.07:44:41.23#ibcon#read 4, iclass 35, count 0 2006.225.07:44:41.23#ibcon#about to read 5, iclass 35, count 0 2006.225.07:44:41.23#ibcon#read 5, iclass 35, count 0 2006.225.07:44:41.23#ibcon#about to read 6, iclass 35, count 0 2006.225.07:44:41.23#ibcon#read 6, iclass 35, count 0 2006.225.07:44:41.23#ibcon#end of sib2, iclass 35, count 0 2006.225.07:44:41.23#ibcon#*mode == 0, iclass 35, count 0 2006.225.07:44:41.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.07:44:41.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:44:41.23#ibcon#*before write, iclass 35, count 0 2006.225.07:44:41.23#ibcon#enter sib2, iclass 35, count 0 2006.225.07:44:41.23#ibcon#flushed, iclass 35, count 0 2006.225.07:44:41.23#ibcon#about to write, iclass 35, count 0 2006.225.07:44:41.23#ibcon#wrote, iclass 35, count 0 2006.225.07:44:41.23#ibcon#about to read 3, iclass 35, count 0 2006.225.07:44:41.27#ibcon#read 3, iclass 35, count 0 2006.225.07:44:41.27#ibcon#about to read 4, iclass 35, count 0 2006.225.07:44:41.27#ibcon#read 4, iclass 35, count 0 2006.225.07:44:41.27#ibcon#about to read 5, iclass 35, count 0 2006.225.07:44:41.27#ibcon#read 5, iclass 35, count 0 2006.225.07:44:41.27#ibcon#about to read 6, iclass 35, count 0 2006.225.07:44:41.27#ibcon#read 6, iclass 35, count 0 2006.225.07:44:41.27#ibcon#end of sib2, iclass 35, count 0 2006.225.07:44:41.27#ibcon#*after write, iclass 35, count 0 2006.225.07:44:41.27#ibcon#*before return 0, iclass 35, count 0 2006.225.07:44:41.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:44:41.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:44:41.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.07:44:41.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.07:44:41.27$vc4f8/vb=3,4 2006.225.07:44:41.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.225.07:44:41.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.225.07:44:41.27#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:41.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:44:41.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:44:41.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:44:41.33#ibcon#enter wrdev, iclass 37, count 2 2006.225.07:44:41.33#ibcon#first serial, iclass 37, count 2 2006.225.07:44:41.33#ibcon#enter sib2, iclass 37, count 2 2006.225.07:44:41.33#ibcon#flushed, iclass 37, count 2 2006.225.07:44:41.33#ibcon#about to write, iclass 37, count 2 2006.225.07:44:41.33#ibcon#wrote, iclass 37, count 2 2006.225.07:44:41.33#ibcon#about to read 3, iclass 37, count 2 2006.225.07:44:41.35#ibcon#read 3, iclass 37, count 2 2006.225.07:44:41.35#ibcon#about to read 4, iclass 37, count 2 2006.225.07:44:41.35#ibcon#read 4, iclass 37, count 2 2006.225.07:44:41.35#ibcon#about to read 5, iclass 37, count 2 2006.225.07:44:41.35#ibcon#read 5, iclass 37, count 2 2006.225.07:44:41.35#ibcon#about to read 6, iclass 37, count 2 2006.225.07:44:41.35#ibcon#read 6, iclass 37, count 2 2006.225.07:44:41.35#ibcon#end of sib2, iclass 37, count 2 2006.225.07:44:41.35#ibcon#*mode == 0, iclass 37, count 2 2006.225.07:44:41.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.225.07:44:41.35#ibcon#[27=AT03-04\r\n] 2006.225.07:44:41.35#ibcon#*before write, iclass 37, count 2 2006.225.07:44:41.35#ibcon#enter sib2, iclass 37, count 2 2006.225.07:44:41.35#ibcon#flushed, iclass 37, count 2 2006.225.07:44:41.35#ibcon#about to write, iclass 37, count 2 2006.225.07:44:41.35#ibcon#wrote, iclass 37, count 2 2006.225.07:44:41.35#ibcon#about to read 3, iclass 37, count 2 2006.225.07:44:41.38#ibcon#read 3, iclass 37, count 2 2006.225.07:44:41.38#ibcon#about to read 4, iclass 37, count 2 2006.225.07:44:41.38#ibcon#read 4, iclass 37, count 2 2006.225.07:44:41.38#ibcon#about to read 5, iclass 37, count 2 2006.225.07:44:41.38#ibcon#read 5, iclass 37, count 2 2006.225.07:44:41.38#ibcon#about to read 6, iclass 37, count 2 2006.225.07:44:41.38#ibcon#read 6, iclass 37, count 2 2006.225.07:44:41.38#ibcon#end of sib2, iclass 37, count 2 2006.225.07:44:41.38#ibcon#*after write, iclass 37, count 2 2006.225.07:44:41.38#ibcon#*before return 0, iclass 37, count 2 2006.225.07:44:41.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:44:41.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:44:41.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.225.07:44:41.38#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:41.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:44:41.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:44:41.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:44:41.50#ibcon#enter wrdev, iclass 37, count 0 2006.225.07:44:41.50#ibcon#first serial, iclass 37, count 0 2006.225.07:44:41.50#ibcon#enter sib2, iclass 37, count 0 2006.225.07:44:41.50#ibcon#flushed, iclass 37, count 0 2006.225.07:44:41.50#ibcon#about to write, iclass 37, count 0 2006.225.07:44:41.50#ibcon#wrote, iclass 37, count 0 2006.225.07:44:41.50#ibcon#about to read 3, iclass 37, count 0 2006.225.07:44:41.52#ibcon#read 3, iclass 37, count 0 2006.225.07:44:41.52#ibcon#about to read 4, iclass 37, count 0 2006.225.07:44:41.52#ibcon#read 4, iclass 37, count 0 2006.225.07:44:41.52#ibcon#about to read 5, iclass 37, count 0 2006.225.07:44:41.52#ibcon#read 5, iclass 37, count 0 2006.225.07:44:41.52#ibcon#about to read 6, iclass 37, count 0 2006.225.07:44:41.52#ibcon#read 6, iclass 37, count 0 2006.225.07:44:41.52#ibcon#end of sib2, iclass 37, count 0 2006.225.07:44:41.52#ibcon#*mode == 0, iclass 37, count 0 2006.225.07:44:41.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.07:44:41.52#ibcon#[27=USB\r\n] 2006.225.07:44:41.52#ibcon#*before write, iclass 37, count 0 2006.225.07:44:41.52#ibcon#enter sib2, iclass 37, count 0 2006.225.07:44:41.52#ibcon#flushed, iclass 37, count 0 2006.225.07:44:41.52#ibcon#about to write, iclass 37, count 0 2006.225.07:44:41.52#ibcon#wrote, iclass 37, count 0 2006.225.07:44:41.52#ibcon#about to read 3, iclass 37, count 0 2006.225.07:44:41.55#ibcon#read 3, iclass 37, count 0 2006.225.07:44:41.55#ibcon#about to read 4, iclass 37, count 0 2006.225.07:44:41.55#ibcon#read 4, iclass 37, count 0 2006.225.07:44:41.55#ibcon#about to read 5, iclass 37, count 0 2006.225.07:44:41.55#ibcon#read 5, iclass 37, count 0 2006.225.07:44:41.55#ibcon#about to read 6, iclass 37, count 0 2006.225.07:44:41.55#ibcon#read 6, iclass 37, count 0 2006.225.07:44:41.55#ibcon#end of sib2, iclass 37, count 0 2006.225.07:44:41.55#ibcon#*after write, iclass 37, count 0 2006.225.07:44:41.55#ibcon#*before return 0, iclass 37, count 0 2006.225.07:44:41.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:44:41.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:44:41.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.07:44:41.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.07:44:41.55$vc4f8/vblo=4,712.99 2006.225.07:44:41.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.07:44:41.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.07:44:41.55#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:41.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:44:41.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:44:41.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:44:41.55#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:44:41.55#ibcon#first serial, iclass 39, count 0 2006.225.07:44:41.55#ibcon#enter sib2, iclass 39, count 0 2006.225.07:44:41.55#ibcon#flushed, iclass 39, count 0 2006.225.07:44:41.55#ibcon#about to write, iclass 39, count 0 2006.225.07:44:41.55#ibcon#wrote, iclass 39, count 0 2006.225.07:44:41.55#ibcon#about to read 3, iclass 39, count 0 2006.225.07:44:41.57#ibcon#read 3, iclass 39, count 0 2006.225.07:44:41.57#ibcon#about to read 4, iclass 39, count 0 2006.225.07:44:41.57#ibcon#read 4, iclass 39, count 0 2006.225.07:44:41.57#ibcon#about to read 5, iclass 39, count 0 2006.225.07:44:41.57#ibcon#read 5, iclass 39, count 0 2006.225.07:44:41.57#ibcon#about to read 6, iclass 39, count 0 2006.225.07:44:41.57#ibcon#read 6, iclass 39, count 0 2006.225.07:44:41.57#ibcon#end of sib2, iclass 39, count 0 2006.225.07:44:41.57#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:44:41.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:44:41.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:44:41.57#ibcon#*before write, iclass 39, count 0 2006.225.07:44:41.57#ibcon#enter sib2, iclass 39, count 0 2006.225.07:44:41.57#ibcon#flushed, iclass 39, count 0 2006.225.07:44:41.57#ibcon#about to write, iclass 39, count 0 2006.225.07:44:41.57#ibcon#wrote, iclass 39, count 0 2006.225.07:44:41.57#ibcon#about to read 3, iclass 39, count 0 2006.225.07:44:41.61#ibcon#read 3, iclass 39, count 0 2006.225.07:44:41.61#ibcon#about to read 4, iclass 39, count 0 2006.225.07:44:41.61#ibcon#read 4, iclass 39, count 0 2006.225.07:44:41.61#ibcon#about to read 5, iclass 39, count 0 2006.225.07:44:41.61#ibcon#read 5, iclass 39, count 0 2006.225.07:44:41.61#ibcon#about to read 6, iclass 39, count 0 2006.225.07:44:41.61#ibcon#read 6, iclass 39, count 0 2006.225.07:44:41.61#ibcon#end of sib2, iclass 39, count 0 2006.225.07:44:41.61#ibcon#*after write, iclass 39, count 0 2006.225.07:44:41.61#ibcon#*before return 0, iclass 39, count 0 2006.225.07:44:41.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:44:41.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:44:41.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:44:41.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:44:41.61$vc4f8/vb=4,4 2006.225.07:44:41.61#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.07:44:41.61#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.07:44:41.61#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:41.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:44:41.67#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:44:41.67#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:44:41.67#ibcon#enter wrdev, iclass 3, count 2 2006.225.07:44:41.67#ibcon#first serial, iclass 3, count 2 2006.225.07:44:41.67#ibcon#enter sib2, iclass 3, count 2 2006.225.07:44:41.67#ibcon#flushed, iclass 3, count 2 2006.225.07:44:41.67#ibcon#about to write, iclass 3, count 2 2006.225.07:44:41.67#ibcon#wrote, iclass 3, count 2 2006.225.07:44:41.67#ibcon#about to read 3, iclass 3, count 2 2006.225.07:44:41.69#ibcon#read 3, iclass 3, count 2 2006.225.07:44:41.69#ibcon#about to read 4, iclass 3, count 2 2006.225.07:44:41.69#ibcon#read 4, iclass 3, count 2 2006.225.07:44:41.69#ibcon#about to read 5, iclass 3, count 2 2006.225.07:44:41.69#ibcon#read 5, iclass 3, count 2 2006.225.07:44:41.69#ibcon#about to read 6, iclass 3, count 2 2006.225.07:44:41.69#ibcon#read 6, iclass 3, count 2 2006.225.07:44:41.69#ibcon#end of sib2, iclass 3, count 2 2006.225.07:44:41.69#ibcon#*mode == 0, iclass 3, count 2 2006.225.07:44:41.69#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.07:44:41.69#ibcon#[27=AT04-04\r\n] 2006.225.07:44:41.69#ibcon#*before write, iclass 3, count 2 2006.225.07:44:41.69#ibcon#enter sib2, iclass 3, count 2 2006.225.07:44:41.69#ibcon#flushed, iclass 3, count 2 2006.225.07:44:41.69#ibcon#about to write, iclass 3, count 2 2006.225.07:44:41.69#ibcon#wrote, iclass 3, count 2 2006.225.07:44:41.69#ibcon#about to read 3, iclass 3, count 2 2006.225.07:44:41.72#ibcon#read 3, iclass 3, count 2 2006.225.07:44:41.72#ibcon#about to read 4, iclass 3, count 2 2006.225.07:44:41.72#ibcon#read 4, iclass 3, count 2 2006.225.07:44:41.72#ibcon#about to read 5, iclass 3, count 2 2006.225.07:44:41.72#ibcon#read 5, iclass 3, count 2 2006.225.07:44:41.72#ibcon#about to read 6, iclass 3, count 2 2006.225.07:44:41.72#ibcon#read 6, iclass 3, count 2 2006.225.07:44:41.72#ibcon#end of sib2, iclass 3, count 2 2006.225.07:44:41.72#ibcon#*after write, iclass 3, count 2 2006.225.07:44:41.72#ibcon#*before return 0, iclass 3, count 2 2006.225.07:44:41.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:44:41.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:44:41.72#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.07:44:41.72#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:41.72#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:44:41.84#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:44:41.84#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:44:41.84#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:44:41.84#ibcon#first serial, iclass 3, count 0 2006.225.07:44:41.84#ibcon#enter sib2, iclass 3, count 0 2006.225.07:44:41.84#ibcon#flushed, iclass 3, count 0 2006.225.07:44:41.84#ibcon#about to write, iclass 3, count 0 2006.225.07:44:41.84#ibcon#wrote, iclass 3, count 0 2006.225.07:44:41.84#ibcon#about to read 3, iclass 3, count 0 2006.225.07:44:41.86#ibcon#read 3, iclass 3, count 0 2006.225.07:44:41.86#ibcon#about to read 4, iclass 3, count 0 2006.225.07:44:41.86#ibcon#read 4, iclass 3, count 0 2006.225.07:44:41.86#ibcon#about to read 5, iclass 3, count 0 2006.225.07:44:41.86#ibcon#read 5, iclass 3, count 0 2006.225.07:44:41.86#ibcon#about to read 6, iclass 3, count 0 2006.225.07:44:41.86#ibcon#read 6, iclass 3, count 0 2006.225.07:44:41.86#ibcon#end of sib2, iclass 3, count 0 2006.225.07:44:41.86#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:44:41.86#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:44:41.86#ibcon#[27=USB\r\n] 2006.225.07:44:41.86#ibcon#*before write, iclass 3, count 0 2006.225.07:44:41.86#ibcon#enter sib2, iclass 3, count 0 2006.225.07:44:41.86#ibcon#flushed, iclass 3, count 0 2006.225.07:44:41.86#ibcon#about to write, iclass 3, count 0 2006.225.07:44:41.86#ibcon#wrote, iclass 3, count 0 2006.225.07:44:41.86#ibcon#about to read 3, iclass 3, count 0 2006.225.07:44:41.89#ibcon#read 3, iclass 3, count 0 2006.225.07:44:41.89#ibcon#about to read 4, iclass 3, count 0 2006.225.07:44:41.89#ibcon#read 4, iclass 3, count 0 2006.225.07:44:41.89#ibcon#about to read 5, iclass 3, count 0 2006.225.07:44:41.89#ibcon#read 5, iclass 3, count 0 2006.225.07:44:41.89#ibcon#about to read 6, iclass 3, count 0 2006.225.07:44:41.89#ibcon#read 6, iclass 3, count 0 2006.225.07:44:41.89#ibcon#end of sib2, iclass 3, count 0 2006.225.07:44:41.89#ibcon#*after write, iclass 3, count 0 2006.225.07:44:41.89#ibcon#*before return 0, iclass 3, count 0 2006.225.07:44:41.89#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:44:41.89#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:44:41.89#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:44:41.89#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:44:41.89$vc4f8/vblo=5,744.99 2006.225.07:44:41.89#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.07:44:41.89#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.07:44:41.89#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:41.89#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:44:41.89#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:44:41.89#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:44:41.89#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:44:41.89#ibcon#first serial, iclass 5, count 0 2006.225.07:44:41.89#ibcon#enter sib2, iclass 5, count 0 2006.225.07:44:41.89#ibcon#flushed, iclass 5, count 0 2006.225.07:44:41.89#ibcon#about to write, iclass 5, count 0 2006.225.07:44:41.89#ibcon#wrote, iclass 5, count 0 2006.225.07:44:41.89#ibcon#about to read 3, iclass 5, count 0 2006.225.07:44:41.91#ibcon#read 3, iclass 5, count 0 2006.225.07:44:41.91#ibcon#about to read 4, iclass 5, count 0 2006.225.07:44:41.91#ibcon#read 4, iclass 5, count 0 2006.225.07:44:41.91#ibcon#about to read 5, iclass 5, count 0 2006.225.07:44:41.91#ibcon#read 5, iclass 5, count 0 2006.225.07:44:41.91#ibcon#about to read 6, iclass 5, count 0 2006.225.07:44:41.91#ibcon#read 6, iclass 5, count 0 2006.225.07:44:41.91#ibcon#end of sib2, iclass 5, count 0 2006.225.07:44:41.91#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:44:41.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:44:41.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:44:41.91#ibcon#*before write, iclass 5, count 0 2006.225.07:44:41.91#ibcon#enter sib2, iclass 5, count 0 2006.225.07:44:41.91#ibcon#flushed, iclass 5, count 0 2006.225.07:44:41.91#ibcon#about to write, iclass 5, count 0 2006.225.07:44:41.91#ibcon#wrote, iclass 5, count 0 2006.225.07:44:41.91#ibcon#about to read 3, iclass 5, count 0 2006.225.07:44:41.95#ibcon#read 3, iclass 5, count 0 2006.225.07:44:41.95#ibcon#about to read 4, iclass 5, count 0 2006.225.07:44:41.95#ibcon#read 4, iclass 5, count 0 2006.225.07:44:41.95#ibcon#about to read 5, iclass 5, count 0 2006.225.07:44:41.95#ibcon#read 5, iclass 5, count 0 2006.225.07:44:41.95#ibcon#about to read 6, iclass 5, count 0 2006.225.07:44:41.95#ibcon#read 6, iclass 5, count 0 2006.225.07:44:41.95#ibcon#end of sib2, iclass 5, count 0 2006.225.07:44:41.95#ibcon#*after write, iclass 5, count 0 2006.225.07:44:41.95#ibcon#*before return 0, iclass 5, count 0 2006.225.07:44:41.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:44:41.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:44:41.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:44:41.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:44:41.95$vc4f8/vb=5,4 2006.225.07:44:41.95#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.07:44:41.95#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.07:44:41.95#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:41.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:44:42.01#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:44:42.01#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:44:42.01#ibcon#enter wrdev, iclass 7, count 2 2006.225.07:44:42.01#ibcon#first serial, iclass 7, count 2 2006.225.07:44:42.01#ibcon#enter sib2, iclass 7, count 2 2006.225.07:44:42.01#ibcon#flushed, iclass 7, count 2 2006.225.07:44:42.01#ibcon#about to write, iclass 7, count 2 2006.225.07:44:42.01#ibcon#wrote, iclass 7, count 2 2006.225.07:44:42.01#ibcon#about to read 3, iclass 7, count 2 2006.225.07:44:42.03#ibcon#read 3, iclass 7, count 2 2006.225.07:44:42.03#ibcon#about to read 4, iclass 7, count 2 2006.225.07:44:42.03#ibcon#read 4, iclass 7, count 2 2006.225.07:44:42.03#ibcon#about to read 5, iclass 7, count 2 2006.225.07:44:42.03#ibcon#read 5, iclass 7, count 2 2006.225.07:44:42.03#ibcon#about to read 6, iclass 7, count 2 2006.225.07:44:42.03#ibcon#read 6, iclass 7, count 2 2006.225.07:44:42.03#ibcon#end of sib2, iclass 7, count 2 2006.225.07:44:42.03#ibcon#*mode == 0, iclass 7, count 2 2006.225.07:44:42.03#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.07:44:42.03#ibcon#[27=AT05-04\r\n] 2006.225.07:44:42.03#ibcon#*before write, iclass 7, count 2 2006.225.07:44:42.03#ibcon#enter sib2, iclass 7, count 2 2006.225.07:44:42.03#ibcon#flushed, iclass 7, count 2 2006.225.07:44:42.03#ibcon#about to write, iclass 7, count 2 2006.225.07:44:42.03#ibcon#wrote, iclass 7, count 2 2006.225.07:44:42.03#ibcon#about to read 3, iclass 7, count 2 2006.225.07:44:42.06#ibcon#read 3, iclass 7, count 2 2006.225.07:44:42.06#ibcon#about to read 4, iclass 7, count 2 2006.225.07:44:42.06#ibcon#read 4, iclass 7, count 2 2006.225.07:44:42.06#ibcon#about to read 5, iclass 7, count 2 2006.225.07:44:42.06#ibcon#read 5, iclass 7, count 2 2006.225.07:44:42.06#ibcon#about to read 6, iclass 7, count 2 2006.225.07:44:42.06#ibcon#read 6, iclass 7, count 2 2006.225.07:44:42.06#ibcon#end of sib2, iclass 7, count 2 2006.225.07:44:42.06#ibcon#*after write, iclass 7, count 2 2006.225.07:44:42.06#ibcon#*before return 0, iclass 7, count 2 2006.225.07:44:42.06#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:44:42.06#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:44:42.06#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.07:44:42.06#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:42.06#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:44:42.18#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:44:42.18#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:44:42.18#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:44:42.18#ibcon#first serial, iclass 7, count 0 2006.225.07:44:42.18#ibcon#enter sib2, iclass 7, count 0 2006.225.07:44:42.18#ibcon#flushed, iclass 7, count 0 2006.225.07:44:42.18#ibcon#about to write, iclass 7, count 0 2006.225.07:44:42.18#ibcon#wrote, iclass 7, count 0 2006.225.07:44:42.18#ibcon#about to read 3, iclass 7, count 0 2006.225.07:44:42.21#ibcon#read 3, iclass 7, count 0 2006.225.07:44:42.21#ibcon#about to read 4, iclass 7, count 0 2006.225.07:44:42.21#ibcon#read 4, iclass 7, count 0 2006.225.07:44:42.21#ibcon#about to read 5, iclass 7, count 0 2006.225.07:44:42.21#ibcon#read 5, iclass 7, count 0 2006.225.07:44:42.21#ibcon#about to read 6, iclass 7, count 0 2006.225.07:44:42.21#ibcon#read 6, iclass 7, count 0 2006.225.07:44:42.21#ibcon#end of sib2, iclass 7, count 0 2006.225.07:44:42.21#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:44:42.21#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:44:42.21#ibcon#[27=USB\r\n] 2006.225.07:44:42.21#ibcon#*before write, iclass 7, count 0 2006.225.07:44:42.21#ibcon#enter sib2, iclass 7, count 0 2006.225.07:44:42.21#ibcon#flushed, iclass 7, count 0 2006.225.07:44:42.21#ibcon#about to write, iclass 7, count 0 2006.225.07:44:42.21#ibcon#wrote, iclass 7, count 0 2006.225.07:44:42.21#ibcon#about to read 3, iclass 7, count 0 2006.225.07:44:42.24#ibcon#read 3, iclass 7, count 0 2006.225.07:44:42.24#ibcon#about to read 4, iclass 7, count 0 2006.225.07:44:42.24#ibcon#read 4, iclass 7, count 0 2006.225.07:44:42.24#ibcon#about to read 5, iclass 7, count 0 2006.225.07:44:42.24#ibcon#read 5, iclass 7, count 0 2006.225.07:44:42.24#ibcon#about to read 6, iclass 7, count 0 2006.225.07:44:42.24#ibcon#read 6, iclass 7, count 0 2006.225.07:44:42.24#ibcon#end of sib2, iclass 7, count 0 2006.225.07:44:42.24#ibcon#*after write, iclass 7, count 0 2006.225.07:44:42.24#ibcon#*before return 0, iclass 7, count 0 2006.225.07:44:42.24#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:44:42.24#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:44:42.24#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:44:42.24#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:44:42.24$vc4f8/vblo=6,752.99 2006.225.07:44:42.24#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.07:44:42.24#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.07:44:42.24#ibcon#ireg 17 cls_cnt 0 2006.225.07:44:42.24#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:44:42.24#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:44:42.24#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:44:42.24#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:44:42.24#ibcon#first serial, iclass 11, count 0 2006.225.07:44:42.24#ibcon#enter sib2, iclass 11, count 0 2006.225.07:44:42.24#ibcon#flushed, iclass 11, count 0 2006.225.07:44:42.24#ibcon#about to write, iclass 11, count 0 2006.225.07:44:42.24#ibcon#wrote, iclass 11, count 0 2006.225.07:44:42.24#ibcon#about to read 3, iclass 11, count 0 2006.225.07:44:42.26#ibcon#read 3, iclass 11, count 0 2006.225.07:44:42.26#ibcon#about to read 4, iclass 11, count 0 2006.225.07:44:42.26#ibcon#read 4, iclass 11, count 0 2006.225.07:44:42.26#ibcon#about to read 5, iclass 11, count 0 2006.225.07:44:42.26#ibcon#read 5, iclass 11, count 0 2006.225.07:44:42.26#ibcon#about to read 6, iclass 11, count 0 2006.225.07:44:42.26#ibcon#read 6, iclass 11, count 0 2006.225.07:44:42.26#ibcon#end of sib2, iclass 11, count 0 2006.225.07:44:42.26#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:44:42.26#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:44:42.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:44:42.26#ibcon#*before write, iclass 11, count 0 2006.225.07:44:42.26#ibcon#enter sib2, iclass 11, count 0 2006.225.07:44:42.26#ibcon#flushed, iclass 11, count 0 2006.225.07:44:42.26#ibcon#about to write, iclass 11, count 0 2006.225.07:44:42.26#ibcon#wrote, iclass 11, count 0 2006.225.07:44:42.26#ibcon#about to read 3, iclass 11, count 0 2006.225.07:44:42.30#ibcon#read 3, iclass 11, count 0 2006.225.07:44:42.30#ibcon#about to read 4, iclass 11, count 0 2006.225.07:44:42.30#ibcon#read 4, iclass 11, count 0 2006.225.07:44:42.30#ibcon#about to read 5, iclass 11, count 0 2006.225.07:44:42.30#ibcon#read 5, iclass 11, count 0 2006.225.07:44:42.30#ibcon#about to read 6, iclass 11, count 0 2006.225.07:44:42.30#ibcon#read 6, iclass 11, count 0 2006.225.07:44:42.30#ibcon#end of sib2, iclass 11, count 0 2006.225.07:44:42.30#ibcon#*after write, iclass 11, count 0 2006.225.07:44:42.30#ibcon#*before return 0, iclass 11, count 0 2006.225.07:44:42.30#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:44:42.30#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:44:42.30#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:44:42.30#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:44:42.30$vc4f8/vb=6,4 2006.225.07:44:42.30#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.07:44:42.30#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.07:44:42.30#ibcon#ireg 11 cls_cnt 2 2006.225.07:44:42.30#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:44:42.36#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:44:42.36#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:44:42.36#ibcon#enter wrdev, iclass 13, count 2 2006.225.07:44:42.36#ibcon#first serial, iclass 13, count 2 2006.225.07:44:42.36#ibcon#enter sib2, iclass 13, count 2 2006.225.07:44:42.36#ibcon#flushed, iclass 13, count 2 2006.225.07:44:42.36#ibcon#about to write, iclass 13, count 2 2006.225.07:44:42.36#ibcon#wrote, iclass 13, count 2 2006.225.07:44:42.36#ibcon#about to read 3, iclass 13, count 2 2006.225.07:44:42.38#ibcon#read 3, iclass 13, count 2 2006.225.07:44:42.38#ibcon#about to read 4, iclass 13, count 2 2006.225.07:44:42.38#ibcon#read 4, iclass 13, count 2 2006.225.07:44:42.38#ibcon#about to read 5, iclass 13, count 2 2006.225.07:44:42.38#ibcon#read 5, iclass 13, count 2 2006.225.07:44:42.38#ibcon#about to read 6, iclass 13, count 2 2006.225.07:44:42.38#ibcon#read 6, iclass 13, count 2 2006.225.07:44:42.38#ibcon#end of sib2, iclass 13, count 2 2006.225.07:44:42.38#ibcon#*mode == 0, iclass 13, count 2 2006.225.07:44:42.38#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.07:44:42.38#ibcon#[27=AT06-04\r\n] 2006.225.07:44:42.38#ibcon#*before write, iclass 13, count 2 2006.225.07:44:42.38#ibcon#enter sib2, iclass 13, count 2 2006.225.07:44:42.38#ibcon#flushed, iclass 13, count 2 2006.225.07:44:42.38#ibcon#about to write, iclass 13, count 2 2006.225.07:44:42.38#ibcon#wrote, iclass 13, count 2 2006.225.07:44:42.38#ibcon#about to read 3, iclass 13, count 2 2006.225.07:44:42.41#ibcon#read 3, iclass 13, count 2 2006.225.07:44:42.41#ibcon#about to read 4, iclass 13, count 2 2006.225.07:44:42.41#ibcon#read 4, iclass 13, count 2 2006.225.07:44:42.41#ibcon#about to read 5, iclass 13, count 2 2006.225.07:44:42.41#ibcon#read 5, iclass 13, count 2 2006.225.07:44:42.41#ibcon#about to read 6, iclass 13, count 2 2006.225.07:44:42.41#ibcon#read 6, iclass 13, count 2 2006.225.07:44:42.41#ibcon#end of sib2, iclass 13, count 2 2006.225.07:44:42.41#ibcon#*after write, iclass 13, count 2 2006.225.07:44:42.41#ibcon#*before return 0, iclass 13, count 2 2006.225.07:44:42.41#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:44:42.41#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:44:42.41#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.07:44:42.41#ibcon#ireg 7 cls_cnt 0 2006.225.07:44:42.41#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:44:42.53#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:44:42.53#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:44:42.53#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:44:42.53#ibcon#first serial, iclass 13, count 0 2006.225.07:44:42.53#ibcon#enter sib2, iclass 13, count 0 2006.225.07:44:42.53#ibcon#flushed, iclass 13, count 0 2006.225.07:44:42.53#ibcon#about to write, iclass 13, count 0 2006.225.07:44:42.53#ibcon#wrote, iclass 13, count 0 2006.225.07:44:42.53#ibcon#about to read 3, iclass 13, count 0 2006.225.07:44:42.55#ibcon#read 3, iclass 13, count 0 2006.225.07:44:42.55#ibcon#about to read 4, iclass 13, count 0 2006.225.07:44:42.55#ibcon#read 4, iclass 13, count 0 2006.225.07:44:42.55#ibcon#about to read 5, iclass 13, count 0 2006.225.07:44:42.55#ibcon#read 5, iclass 13, count 0 2006.225.07:44:42.55#ibcon#about to read 6, iclass 13, count 0 2006.225.07:44:42.55#ibcon#read 6, iclass 13, count 0 2006.225.07:44:42.55#ibcon#end of sib2, iclass 13, count 0 2006.225.07:44:42.55#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:44:42.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:44:42.55#ibcon#[27=USB\r\n] 2006.225.07:44:42.55#ibcon#*before write, iclass 13, count 0 2006.225.07:44:42.55#ibcon#enter sib2, iclass 13, count 0 2006.225.07:44:42.55#ibcon#flushed, iclass 13, count 0 2006.225.07:44:42.55#ibcon#about to write, iclass 13, count 0 2006.225.07:44:42.55#ibcon#wrote, iclass 13, count 0 2006.225.07:44:42.55#ibcon#about to read 3, iclass 13, count 0 2006.225.07:44:42.58#ibcon#read 3, iclass 13, count 0 2006.225.07:44:42.58#ibcon#about to read 4, iclass 13, count 0 2006.225.07:44:42.58#ibcon#read 4, iclass 13, count 0 2006.225.07:44:42.58#ibcon#about to read 5, iclass 13, count 0 2006.225.07:44:42.58#ibcon#read 5, iclass 13, count 0 2006.225.07:44:42.58#ibcon#about to read 6, iclass 13, count 0 2006.225.07:44:42.58#ibcon#read 6, iclass 13, count 0 2006.225.07:44:42.58#ibcon#end of sib2, iclass 13, count 0 2006.225.07:44:42.58#ibcon#*after write, iclass 13, count 0 2006.225.07:44:42.58#ibcon#*before return 0, iclass 13, count 0 2006.225.07:44:42.58#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:44:42.58#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:44:42.58#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:44:42.58#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:44:42.58$vc4f8/vabw=wide 2006.225.07:44:42.58#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.07:44:42.58#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.07:44:42.58#ibcon#ireg 8 cls_cnt 0 2006.225.07:44:42.58#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:44:42.58#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:44:42.58#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:44:42.58#ibcon#enter wrdev, iclass 15, count 0 2006.225.07:44:42.58#ibcon#first serial, iclass 15, count 0 2006.225.07:44:42.58#ibcon#enter sib2, iclass 15, count 0 2006.225.07:44:42.58#ibcon#flushed, iclass 15, count 0 2006.225.07:44:42.58#ibcon#about to write, iclass 15, count 0 2006.225.07:44:42.58#ibcon#wrote, iclass 15, count 0 2006.225.07:44:42.58#ibcon#about to read 3, iclass 15, count 0 2006.225.07:44:42.60#ibcon#read 3, iclass 15, count 0 2006.225.07:44:42.60#ibcon#about to read 4, iclass 15, count 0 2006.225.07:44:42.60#ibcon#read 4, iclass 15, count 0 2006.225.07:44:42.60#ibcon#about to read 5, iclass 15, count 0 2006.225.07:44:42.60#ibcon#read 5, iclass 15, count 0 2006.225.07:44:42.60#ibcon#about to read 6, iclass 15, count 0 2006.225.07:44:42.60#ibcon#read 6, iclass 15, count 0 2006.225.07:44:42.60#ibcon#end of sib2, iclass 15, count 0 2006.225.07:44:42.60#ibcon#*mode == 0, iclass 15, count 0 2006.225.07:44:42.60#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.07:44:42.60#ibcon#[25=BW32\r\n] 2006.225.07:44:42.60#ibcon#*before write, iclass 15, count 0 2006.225.07:44:42.60#ibcon#enter sib2, iclass 15, count 0 2006.225.07:44:42.60#ibcon#flushed, iclass 15, count 0 2006.225.07:44:42.60#ibcon#about to write, iclass 15, count 0 2006.225.07:44:42.60#ibcon#wrote, iclass 15, count 0 2006.225.07:44:42.60#ibcon#about to read 3, iclass 15, count 0 2006.225.07:44:42.63#ibcon#read 3, iclass 15, count 0 2006.225.07:44:42.63#ibcon#about to read 4, iclass 15, count 0 2006.225.07:44:42.63#ibcon#read 4, iclass 15, count 0 2006.225.07:44:42.63#ibcon#about to read 5, iclass 15, count 0 2006.225.07:44:42.63#ibcon#read 5, iclass 15, count 0 2006.225.07:44:42.63#ibcon#about to read 6, iclass 15, count 0 2006.225.07:44:42.63#ibcon#read 6, iclass 15, count 0 2006.225.07:44:42.63#ibcon#end of sib2, iclass 15, count 0 2006.225.07:44:42.63#ibcon#*after write, iclass 15, count 0 2006.225.07:44:42.63#ibcon#*before return 0, iclass 15, count 0 2006.225.07:44:42.63#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:44:42.63#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:44:42.63#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.07:44:42.63#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.07:44:42.63$vc4f8/vbbw=wide 2006.225.07:44:42.63#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.225.07:44:42.63#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.225.07:44:42.63#ibcon#ireg 8 cls_cnt 0 2006.225.07:44:42.63#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:44:42.70#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:44:42.70#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:44:42.70#ibcon#enter wrdev, iclass 17, count 0 2006.225.07:44:42.70#ibcon#first serial, iclass 17, count 0 2006.225.07:44:42.70#ibcon#enter sib2, iclass 17, count 0 2006.225.07:44:42.70#ibcon#flushed, iclass 17, count 0 2006.225.07:44:42.70#ibcon#about to write, iclass 17, count 0 2006.225.07:44:42.70#ibcon#wrote, iclass 17, count 0 2006.225.07:44:42.70#ibcon#about to read 3, iclass 17, count 0 2006.225.07:44:42.72#ibcon#read 3, iclass 17, count 0 2006.225.07:44:42.72#ibcon#about to read 4, iclass 17, count 0 2006.225.07:44:42.72#ibcon#read 4, iclass 17, count 0 2006.225.07:44:42.72#ibcon#about to read 5, iclass 17, count 0 2006.225.07:44:42.72#ibcon#read 5, iclass 17, count 0 2006.225.07:44:42.72#ibcon#about to read 6, iclass 17, count 0 2006.225.07:44:42.72#ibcon#read 6, iclass 17, count 0 2006.225.07:44:42.72#ibcon#end of sib2, iclass 17, count 0 2006.225.07:44:42.72#ibcon#*mode == 0, iclass 17, count 0 2006.225.07:44:42.72#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.07:44:42.72#ibcon#[27=BW32\r\n] 2006.225.07:44:42.72#ibcon#*before write, iclass 17, count 0 2006.225.07:44:42.72#ibcon#enter sib2, iclass 17, count 0 2006.225.07:44:42.72#ibcon#flushed, iclass 17, count 0 2006.225.07:44:42.72#ibcon#about to write, iclass 17, count 0 2006.225.07:44:42.72#ibcon#wrote, iclass 17, count 0 2006.225.07:44:42.72#ibcon#about to read 3, iclass 17, count 0 2006.225.07:44:42.75#ibcon#read 3, iclass 17, count 0 2006.225.07:44:42.75#ibcon#about to read 4, iclass 17, count 0 2006.225.07:44:42.75#ibcon#read 4, iclass 17, count 0 2006.225.07:44:42.75#ibcon#about to read 5, iclass 17, count 0 2006.225.07:44:42.75#ibcon#read 5, iclass 17, count 0 2006.225.07:44:42.75#ibcon#about to read 6, iclass 17, count 0 2006.225.07:44:42.75#ibcon#read 6, iclass 17, count 0 2006.225.07:44:42.75#ibcon#end of sib2, iclass 17, count 0 2006.225.07:44:42.75#ibcon#*after write, iclass 17, count 0 2006.225.07:44:42.75#ibcon#*before return 0, iclass 17, count 0 2006.225.07:44:42.75#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:44:42.75#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:44:42.75#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.07:44:42.75#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.07:44:42.75$4f8m12a/ifd4f 2006.225.07:44:42.75$ifd4f/lo= 2006.225.07:44:42.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:44:42.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:44:42.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:44:42.75$ifd4f/patch= 2006.225.07:44:42.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:44:42.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:44:42.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:44:42.75$4f8m12a/"form=m,16.000,1:2 2006.225.07:44:42.75$4f8m12a/"tpicd 2006.225.07:44:42.75$4f8m12a/echo=off 2006.225.07:44:42.75$4f8m12a/xlog=off 2006.225.07:44:42.75:!2006.225.07:45:10 2006.225.07:44:57.14#trakl#Source acquired 2006.225.07:44:58.14#flagr#flagr/antenna,acquired 2006.225.07:45:10.00:preob 2006.225.07:45:11.14/onsource/TRACKING 2006.225.07:45:11.14:!2006.225.07:45:20 2006.225.07:45:20.00:data_valid=on 2006.225.07:45:20.00:midob 2006.225.07:45:20.14/onsource/TRACKING 2006.225.07:45:20.14/wx/28.07,1003.3,71 2006.225.07:45:20.23/cable/+6.4042E-03 2006.225.07:45:21.32/va/01,08,usb,yes,30,31 2006.225.07:45:21.32/va/02,07,usb,yes,30,32 2006.225.07:45:21.32/va/03,06,usb,yes,32,32 2006.225.07:45:21.32/va/04,07,usb,yes,31,34 2006.225.07:45:21.32/va/05,07,usb,yes,34,36 2006.225.07:45:21.32/va/06,06,usb,yes,33,33 2006.225.07:45:21.32/va/07,06,usb,yes,34,34 2006.225.07:45:21.32/va/08,07,usb,yes,32,32 2006.225.07:45:21.55/valo/01,532.99,yes,locked 2006.225.07:45:21.55/valo/02,572.99,yes,locked 2006.225.07:45:21.55/valo/03,672.99,yes,locked 2006.225.07:45:21.55/valo/04,832.99,yes,locked 2006.225.07:45:21.55/valo/05,652.99,yes,locked 2006.225.07:45:21.55/valo/06,772.99,yes,locked 2006.225.07:45:21.55/valo/07,832.99,yes,locked 2006.225.07:45:21.55/valo/08,852.99,yes,locked 2006.225.07:45:22.64/vb/01,04,usb,yes,31,30 2006.225.07:45:22.64/vb/02,04,usb,yes,33,35 2006.225.07:45:22.64/vb/03,04,usb,yes,29,33 2006.225.07:45:22.64/vb/04,04,usb,yes,30,31 2006.225.07:45:22.64/vb/05,04,usb,yes,29,33 2006.225.07:45:22.64/vb/06,04,usb,yes,30,33 2006.225.07:45:22.64/vb/07,04,usb,yes,32,32 2006.225.07:45:22.64/vb/08,04,usb,yes,29,33 2006.225.07:45:22.88/vblo/01,632.99,yes,locked 2006.225.07:45:22.88/vblo/02,640.99,yes,locked 2006.225.07:45:22.88/vblo/03,656.99,yes,locked 2006.225.07:45:22.88/vblo/04,712.99,yes,locked 2006.225.07:45:22.88/vblo/05,744.99,yes,locked 2006.225.07:45:22.88/vblo/06,752.99,yes,locked 2006.225.07:45:22.88/vblo/07,734.99,yes,locked 2006.225.07:45:22.88/vblo/08,744.99,yes,locked 2006.225.07:45:23.03/vabw/8 2006.225.07:45:23.18/vbbw/8 2006.225.07:45:23.27/xfe/off,on,15.2 2006.225.07:45:23.66/ifatt/23,28,28,28 2006.225.07:45:24.07/fmout-gps/S +4.50E-07 2006.225.07:45:24.11:!2006.225.07:46:20 2006.225.07:46:20.01:data_valid=off 2006.225.07:46:20.01:postob 2006.225.07:46:20.17/cable/+6.4040E-03 2006.225.07:46:20.17/wx/28.10,1003.3,72 2006.225.07:46:21.08/fmout-gps/S +4.50E-07 2006.225.07:46:21.08:scan_name=225-0747,k06225,60 2006.225.07:46:21.09:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.225.07:46:21.14#flagr#flagr/antenna,new-source 2006.225.07:46:22.14:checkk5 2006.225.07:46:22.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:46:22.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:46:23.26/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:46:23.63/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:46:24.00/chk_obsdata//k5ts1/T2250745??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.07:46:24.37/chk_obsdata//k5ts2/T2250745??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.07:46:24.74/chk_obsdata//k5ts3/T2250745??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.07:46:25.11/chk_obsdata//k5ts4/T2250745??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.07:46:25.82/k5log//k5ts1_log_newline 2006.225.07:46:26.51/k5log//k5ts2_log_newline 2006.225.07:46:27.19/k5log//k5ts3_log_newline 2006.225.07:46:27.87/k5log//k5ts4_log_newline 2006.225.07:46:27.90/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:46:27.90:4f8m12a=1 2006.225.07:46:27.90$4f8m12a/echo=on 2006.225.07:46:27.90$4f8m12a/pcalon 2006.225.07:46:27.90$pcalon/"no phase cal control is implemented here 2006.225.07:46:27.90$4f8m12a/"tpicd=stop 2006.225.07:46:27.90$4f8m12a/vc4f8 2006.225.07:46:27.90$vc4f8/valo=1,532.99 2006.225.07:46:27.90#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.07:46:27.90#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.07:46:27.90#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:27.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:46:27.90#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:46:27.90#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:46:27.90#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:46:27.90#ibcon#first serial, iclass 24, count 0 2006.225.07:46:27.90#ibcon#enter sib2, iclass 24, count 0 2006.225.07:46:27.90#ibcon#flushed, iclass 24, count 0 2006.225.07:46:27.90#ibcon#about to write, iclass 24, count 0 2006.225.07:46:27.90#ibcon#wrote, iclass 24, count 0 2006.225.07:46:27.90#ibcon#about to read 3, iclass 24, count 0 2006.225.07:46:27.94#ibcon#read 3, iclass 24, count 0 2006.225.07:46:27.94#ibcon#about to read 4, iclass 24, count 0 2006.225.07:46:27.94#ibcon#read 4, iclass 24, count 0 2006.225.07:46:27.94#ibcon#about to read 5, iclass 24, count 0 2006.225.07:46:27.94#ibcon#read 5, iclass 24, count 0 2006.225.07:46:27.94#ibcon#about to read 6, iclass 24, count 0 2006.225.07:46:27.94#ibcon#read 6, iclass 24, count 0 2006.225.07:46:27.94#ibcon#end of sib2, iclass 24, count 0 2006.225.07:46:27.94#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:46:27.94#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:46:27.94#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:46:27.94#ibcon#*before write, iclass 24, count 0 2006.225.07:46:27.94#ibcon#enter sib2, iclass 24, count 0 2006.225.07:46:27.94#ibcon#flushed, iclass 24, count 0 2006.225.07:46:27.94#ibcon#about to write, iclass 24, count 0 2006.225.07:46:27.94#ibcon#wrote, iclass 24, count 0 2006.225.07:46:27.94#ibcon#about to read 3, iclass 24, count 0 2006.225.07:46:27.99#ibcon#read 3, iclass 24, count 0 2006.225.07:46:27.99#ibcon#about to read 4, iclass 24, count 0 2006.225.07:46:27.99#ibcon#read 4, iclass 24, count 0 2006.225.07:46:27.99#ibcon#about to read 5, iclass 24, count 0 2006.225.07:46:27.99#ibcon#read 5, iclass 24, count 0 2006.225.07:46:27.99#ibcon#about to read 6, iclass 24, count 0 2006.225.07:46:27.99#ibcon#read 6, iclass 24, count 0 2006.225.07:46:27.99#ibcon#end of sib2, iclass 24, count 0 2006.225.07:46:27.99#ibcon#*after write, iclass 24, count 0 2006.225.07:46:27.99#ibcon#*before return 0, iclass 24, count 0 2006.225.07:46:27.99#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:46:27.99#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:46:27.99#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:46:27.99#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:46:27.99$vc4f8/va=1,8 2006.225.07:46:27.99#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.225.07:46:27.99#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.225.07:46:27.99#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:27.99#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:46:27.99#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:46:27.99#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:46:27.99#ibcon#enter wrdev, iclass 26, count 2 2006.225.07:46:27.99#ibcon#first serial, iclass 26, count 2 2006.225.07:46:27.99#ibcon#enter sib2, iclass 26, count 2 2006.225.07:46:27.99#ibcon#flushed, iclass 26, count 2 2006.225.07:46:27.99#ibcon#about to write, iclass 26, count 2 2006.225.07:46:27.99#ibcon#wrote, iclass 26, count 2 2006.225.07:46:27.99#ibcon#about to read 3, iclass 26, count 2 2006.225.07:46:28.02#ibcon#read 3, iclass 26, count 2 2006.225.07:46:28.02#ibcon#about to read 4, iclass 26, count 2 2006.225.07:46:28.02#ibcon#read 4, iclass 26, count 2 2006.225.07:46:28.02#ibcon#about to read 5, iclass 26, count 2 2006.225.07:46:28.02#ibcon#read 5, iclass 26, count 2 2006.225.07:46:28.02#ibcon#about to read 6, iclass 26, count 2 2006.225.07:46:28.02#ibcon#read 6, iclass 26, count 2 2006.225.07:46:28.02#ibcon#end of sib2, iclass 26, count 2 2006.225.07:46:28.02#ibcon#*mode == 0, iclass 26, count 2 2006.225.07:46:28.02#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.225.07:46:28.02#ibcon#[25=AT01-08\r\n] 2006.225.07:46:28.02#ibcon#*before write, iclass 26, count 2 2006.225.07:46:28.02#ibcon#enter sib2, iclass 26, count 2 2006.225.07:46:28.02#ibcon#flushed, iclass 26, count 2 2006.225.07:46:28.02#ibcon#about to write, iclass 26, count 2 2006.225.07:46:28.02#ibcon#wrote, iclass 26, count 2 2006.225.07:46:28.02#ibcon#about to read 3, iclass 26, count 2 2006.225.07:46:28.05#ibcon#read 3, iclass 26, count 2 2006.225.07:46:28.05#ibcon#about to read 4, iclass 26, count 2 2006.225.07:46:28.05#ibcon#read 4, iclass 26, count 2 2006.225.07:46:28.05#ibcon#about to read 5, iclass 26, count 2 2006.225.07:46:28.05#ibcon#read 5, iclass 26, count 2 2006.225.07:46:28.05#ibcon#about to read 6, iclass 26, count 2 2006.225.07:46:28.05#ibcon#read 6, iclass 26, count 2 2006.225.07:46:28.05#ibcon#end of sib2, iclass 26, count 2 2006.225.07:46:28.05#ibcon#*after write, iclass 26, count 2 2006.225.07:46:28.05#ibcon#*before return 0, iclass 26, count 2 2006.225.07:46:28.05#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:46:28.05#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:46:28.05#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.225.07:46:28.05#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:28.05#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:46:28.17#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:46:28.17#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:46:28.17#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:46:28.17#ibcon#first serial, iclass 26, count 0 2006.225.07:46:28.17#ibcon#enter sib2, iclass 26, count 0 2006.225.07:46:28.17#ibcon#flushed, iclass 26, count 0 2006.225.07:46:28.17#ibcon#about to write, iclass 26, count 0 2006.225.07:46:28.17#ibcon#wrote, iclass 26, count 0 2006.225.07:46:28.17#ibcon#about to read 3, iclass 26, count 0 2006.225.07:46:28.20#ibcon#read 3, iclass 26, count 0 2006.225.07:46:28.20#ibcon#about to read 4, iclass 26, count 0 2006.225.07:46:28.20#ibcon#read 4, iclass 26, count 0 2006.225.07:46:28.20#ibcon#about to read 5, iclass 26, count 0 2006.225.07:46:28.20#ibcon#read 5, iclass 26, count 0 2006.225.07:46:28.20#ibcon#about to read 6, iclass 26, count 0 2006.225.07:46:28.20#ibcon#read 6, iclass 26, count 0 2006.225.07:46:28.20#ibcon#end of sib2, iclass 26, count 0 2006.225.07:46:28.20#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:46:28.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:46:28.20#ibcon#[25=USB\r\n] 2006.225.07:46:28.20#ibcon#*before write, iclass 26, count 0 2006.225.07:46:28.20#ibcon#enter sib2, iclass 26, count 0 2006.225.07:46:28.20#ibcon#flushed, iclass 26, count 0 2006.225.07:46:28.20#ibcon#about to write, iclass 26, count 0 2006.225.07:46:28.20#ibcon#wrote, iclass 26, count 0 2006.225.07:46:28.20#ibcon#about to read 3, iclass 26, count 0 2006.225.07:46:28.23#ibcon#read 3, iclass 26, count 0 2006.225.07:46:28.23#ibcon#about to read 4, iclass 26, count 0 2006.225.07:46:28.23#ibcon#read 4, iclass 26, count 0 2006.225.07:46:28.23#ibcon#about to read 5, iclass 26, count 0 2006.225.07:46:28.23#ibcon#read 5, iclass 26, count 0 2006.225.07:46:28.23#ibcon#about to read 6, iclass 26, count 0 2006.225.07:46:28.23#ibcon#read 6, iclass 26, count 0 2006.225.07:46:28.23#ibcon#end of sib2, iclass 26, count 0 2006.225.07:46:28.23#ibcon#*after write, iclass 26, count 0 2006.225.07:46:28.23#ibcon#*before return 0, iclass 26, count 0 2006.225.07:46:28.23#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:46:28.23#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:46:28.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:46:28.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:46:28.23$vc4f8/valo=2,572.99 2006.225.07:46:28.23#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.07:46:28.23#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.07:46:28.23#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:28.23#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:46:28.23#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:46:28.23#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:46:28.23#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:46:28.23#ibcon#first serial, iclass 28, count 0 2006.225.07:46:28.23#ibcon#enter sib2, iclass 28, count 0 2006.225.07:46:28.23#ibcon#flushed, iclass 28, count 0 2006.225.07:46:28.23#ibcon#about to write, iclass 28, count 0 2006.225.07:46:28.23#ibcon#wrote, iclass 28, count 0 2006.225.07:46:28.23#ibcon#about to read 3, iclass 28, count 0 2006.225.07:46:28.25#ibcon#read 3, iclass 28, count 0 2006.225.07:46:28.25#ibcon#about to read 4, iclass 28, count 0 2006.225.07:46:28.25#ibcon#read 4, iclass 28, count 0 2006.225.07:46:28.25#ibcon#about to read 5, iclass 28, count 0 2006.225.07:46:28.25#ibcon#read 5, iclass 28, count 0 2006.225.07:46:28.25#ibcon#about to read 6, iclass 28, count 0 2006.225.07:46:28.25#ibcon#read 6, iclass 28, count 0 2006.225.07:46:28.25#ibcon#end of sib2, iclass 28, count 0 2006.225.07:46:28.25#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:46:28.25#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:46:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:46:28.25#ibcon#*before write, iclass 28, count 0 2006.225.07:46:28.25#ibcon#enter sib2, iclass 28, count 0 2006.225.07:46:28.25#ibcon#flushed, iclass 28, count 0 2006.225.07:46:28.25#ibcon#about to write, iclass 28, count 0 2006.225.07:46:28.25#ibcon#wrote, iclass 28, count 0 2006.225.07:46:28.25#ibcon#about to read 3, iclass 28, count 0 2006.225.07:46:28.29#ibcon#read 3, iclass 28, count 0 2006.225.07:46:28.29#ibcon#about to read 4, iclass 28, count 0 2006.225.07:46:28.29#ibcon#read 4, iclass 28, count 0 2006.225.07:46:28.29#ibcon#about to read 5, iclass 28, count 0 2006.225.07:46:28.29#ibcon#read 5, iclass 28, count 0 2006.225.07:46:28.29#ibcon#about to read 6, iclass 28, count 0 2006.225.07:46:28.29#ibcon#read 6, iclass 28, count 0 2006.225.07:46:28.29#ibcon#end of sib2, iclass 28, count 0 2006.225.07:46:28.29#ibcon#*after write, iclass 28, count 0 2006.225.07:46:28.29#ibcon#*before return 0, iclass 28, count 0 2006.225.07:46:28.29#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:46:28.29#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:46:28.29#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:46:28.29#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:46:28.29$vc4f8/va=2,7 2006.225.07:46:28.29#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.07:46:28.29#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.07:46:28.29#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:28.29#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:46:28.35#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:46:28.35#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:46:28.35#ibcon#enter wrdev, iclass 30, count 2 2006.225.07:46:28.35#ibcon#first serial, iclass 30, count 2 2006.225.07:46:28.35#ibcon#enter sib2, iclass 30, count 2 2006.225.07:46:28.35#ibcon#flushed, iclass 30, count 2 2006.225.07:46:28.35#ibcon#about to write, iclass 30, count 2 2006.225.07:46:28.35#ibcon#wrote, iclass 30, count 2 2006.225.07:46:28.35#ibcon#about to read 3, iclass 30, count 2 2006.225.07:46:28.37#ibcon#read 3, iclass 30, count 2 2006.225.07:46:28.37#ibcon#about to read 4, iclass 30, count 2 2006.225.07:46:28.37#ibcon#read 4, iclass 30, count 2 2006.225.07:46:28.37#ibcon#about to read 5, iclass 30, count 2 2006.225.07:46:28.37#ibcon#read 5, iclass 30, count 2 2006.225.07:46:28.37#ibcon#about to read 6, iclass 30, count 2 2006.225.07:46:28.37#ibcon#read 6, iclass 30, count 2 2006.225.07:46:28.37#ibcon#end of sib2, iclass 30, count 2 2006.225.07:46:28.37#ibcon#*mode == 0, iclass 30, count 2 2006.225.07:46:28.37#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.07:46:28.37#ibcon#[25=AT02-07\r\n] 2006.225.07:46:28.37#ibcon#*before write, iclass 30, count 2 2006.225.07:46:28.37#ibcon#enter sib2, iclass 30, count 2 2006.225.07:46:28.37#ibcon#flushed, iclass 30, count 2 2006.225.07:46:28.37#ibcon#about to write, iclass 30, count 2 2006.225.07:46:28.37#ibcon#wrote, iclass 30, count 2 2006.225.07:46:28.37#ibcon#about to read 3, iclass 30, count 2 2006.225.07:46:28.40#ibcon#read 3, iclass 30, count 2 2006.225.07:46:28.40#ibcon#about to read 4, iclass 30, count 2 2006.225.07:46:28.40#ibcon#read 4, iclass 30, count 2 2006.225.07:46:28.40#ibcon#about to read 5, iclass 30, count 2 2006.225.07:46:28.40#ibcon#read 5, iclass 30, count 2 2006.225.07:46:28.40#ibcon#about to read 6, iclass 30, count 2 2006.225.07:46:28.40#ibcon#read 6, iclass 30, count 2 2006.225.07:46:28.40#ibcon#end of sib2, iclass 30, count 2 2006.225.07:46:28.40#ibcon#*after write, iclass 30, count 2 2006.225.07:46:28.40#ibcon#*before return 0, iclass 30, count 2 2006.225.07:46:28.40#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:46:28.40#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:46:28.40#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.07:46:28.40#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:28.40#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:46:28.52#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:46:28.52#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:46:28.52#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:46:28.52#ibcon#first serial, iclass 30, count 0 2006.225.07:46:28.52#ibcon#enter sib2, iclass 30, count 0 2006.225.07:46:28.52#ibcon#flushed, iclass 30, count 0 2006.225.07:46:28.52#ibcon#about to write, iclass 30, count 0 2006.225.07:46:28.52#ibcon#wrote, iclass 30, count 0 2006.225.07:46:28.52#ibcon#about to read 3, iclass 30, count 0 2006.225.07:46:28.54#ibcon#read 3, iclass 30, count 0 2006.225.07:46:28.54#ibcon#about to read 4, iclass 30, count 0 2006.225.07:46:28.54#ibcon#read 4, iclass 30, count 0 2006.225.07:46:28.54#ibcon#about to read 5, iclass 30, count 0 2006.225.07:46:28.54#ibcon#read 5, iclass 30, count 0 2006.225.07:46:28.54#ibcon#about to read 6, iclass 30, count 0 2006.225.07:46:28.54#ibcon#read 6, iclass 30, count 0 2006.225.07:46:28.54#ibcon#end of sib2, iclass 30, count 0 2006.225.07:46:28.54#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:46:28.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:46:28.54#ibcon#[25=USB\r\n] 2006.225.07:46:28.54#ibcon#*before write, iclass 30, count 0 2006.225.07:46:28.54#ibcon#enter sib2, iclass 30, count 0 2006.225.07:46:28.54#ibcon#flushed, iclass 30, count 0 2006.225.07:46:28.54#ibcon#about to write, iclass 30, count 0 2006.225.07:46:28.54#ibcon#wrote, iclass 30, count 0 2006.225.07:46:28.54#ibcon#about to read 3, iclass 30, count 0 2006.225.07:46:28.57#ibcon#read 3, iclass 30, count 0 2006.225.07:46:28.57#ibcon#about to read 4, iclass 30, count 0 2006.225.07:46:28.57#ibcon#read 4, iclass 30, count 0 2006.225.07:46:28.57#ibcon#about to read 5, iclass 30, count 0 2006.225.07:46:28.57#ibcon#read 5, iclass 30, count 0 2006.225.07:46:28.57#ibcon#about to read 6, iclass 30, count 0 2006.225.07:46:28.57#ibcon#read 6, iclass 30, count 0 2006.225.07:46:28.57#ibcon#end of sib2, iclass 30, count 0 2006.225.07:46:28.57#ibcon#*after write, iclass 30, count 0 2006.225.07:46:28.57#ibcon#*before return 0, iclass 30, count 0 2006.225.07:46:28.57#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:46:28.57#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:46:28.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:46:28.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:46:28.57$vc4f8/valo=3,672.99 2006.225.07:46:28.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.07:46:28.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.07:46:28.57#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:28.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:46:28.57#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:46:28.57#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:46:28.57#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:46:28.57#ibcon#first serial, iclass 32, count 0 2006.225.07:46:28.57#ibcon#enter sib2, iclass 32, count 0 2006.225.07:46:28.57#ibcon#flushed, iclass 32, count 0 2006.225.07:46:28.57#ibcon#about to write, iclass 32, count 0 2006.225.07:46:28.57#ibcon#wrote, iclass 32, count 0 2006.225.07:46:28.57#ibcon#about to read 3, iclass 32, count 0 2006.225.07:46:28.60#ibcon#read 3, iclass 32, count 0 2006.225.07:46:28.60#ibcon#about to read 4, iclass 32, count 0 2006.225.07:46:28.60#ibcon#read 4, iclass 32, count 0 2006.225.07:46:28.60#ibcon#about to read 5, iclass 32, count 0 2006.225.07:46:28.60#ibcon#read 5, iclass 32, count 0 2006.225.07:46:28.60#ibcon#about to read 6, iclass 32, count 0 2006.225.07:46:28.60#ibcon#read 6, iclass 32, count 0 2006.225.07:46:28.60#ibcon#end of sib2, iclass 32, count 0 2006.225.07:46:28.60#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:46:28.60#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:46:28.60#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:46:28.60#ibcon#*before write, iclass 32, count 0 2006.225.07:46:28.60#ibcon#enter sib2, iclass 32, count 0 2006.225.07:46:28.60#ibcon#flushed, iclass 32, count 0 2006.225.07:46:28.60#ibcon#about to write, iclass 32, count 0 2006.225.07:46:28.60#ibcon#wrote, iclass 32, count 0 2006.225.07:46:28.60#ibcon#about to read 3, iclass 32, count 0 2006.225.07:46:28.64#ibcon#read 3, iclass 32, count 0 2006.225.07:46:28.64#ibcon#about to read 4, iclass 32, count 0 2006.225.07:46:28.64#ibcon#read 4, iclass 32, count 0 2006.225.07:46:28.64#ibcon#about to read 5, iclass 32, count 0 2006.225.07:46:28.64#ibcon#read 5, iclass 32, count 0 2006.225.07:46:28.64#ibcon#about to read 6, iclass 32, count 0 2006.225.07:46:28.64#ibcon#read 6, iclass 32, count 0 2006.225.07:46:28.64#ibcon#end of sib2, iclass 32, count 0 2006.225.07:46:28.64#ibcon#*after write, iclass 32, count 0 2006.225.07:46:28.64#ibcon#*before return 0, iclass 32, count 0 2006.225.07:46:28.64#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:46:28.64#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:46:28.64#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:46:28.64#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:46:28.64$vc4f8/va=3,6 2006.225.07:46:28.64#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.07:46:28.64#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.07:46:28.64#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:28.64#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:46:28.69#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:46:28.69#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:46:28.69#ibcon#enter wrdev, iclass 34, count 2 2006.225.07:46:28.69#ibcon#first serial, iclass 34, count 2 2006.225.07:46:28.69#ibcon#enter sib2, iclass 34, count 2 2006.225.07:46:28.69#ibcon#flushed, iclass 34, count 2 2006.225.07:46:28.69#ibcon#about to write, iclass 34, count 2 2006.225.07:46:28.69#ibcon#wrote, iclass 34, count 2 2006.225.07:46:28.69#ibcon#about to read 3, iclass 34, count 2 2006.225.07:46:28.71#ibcon#read 3, iclass 34, count 2 2006.225.07:46:28.71#ibcon#about to read 4, iclass 34, count 2 2006.225.07:46:28.71#ibcon#read 4, iclass 34, count 2 2006.225.07:46:28.71#ibcon#about to read 5, iclass 34, count 2 2006.225.07:46:28.71#ibcon#read 5, iclass 34, count 2 2006.225.07:46:28.71#ibcon#about to read 6, iclass 34, count 2 2006.225.07:46:28.71#ibcon#read 6, iclass 34, count 2 2006.225.07:46:28.71#ibcon#end of sib2, iclass 34, count 2 2006.225.07:46:28.71#ibcon#*mode == 0, iclass 34, count 2 2006.225.07:46:28.71#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.07:46:28.71#ibcon#[25=AT03-06\r\n] 2006.225.07:46:28.71#ibcon#*before write, iclass 34, count 2 2006.225.07:46:28.71#ibcon#enter sib2, iclass 34, count 2 2006.225.07:46:28.71#ibcon#flushed, iclass 34, count 2 2006.225.07:46:28.71#ibcon#about to write, iclass 34, count 2 2006.225.07:46:28.71#ibcon#wrote, iclass 34, count 2 2006.225.07:46:28.71#ibcon#about to read 3, iclass 34, count 2 2006.225.07:46:28.74#ibcon#read 3, iclass 34, count 2 2006.225.07:46:28.74#ibcon#about to read 4, iclass 34, count 2 2006.225.07:46:28.74#ibcon#read 4, iclass 34, count 2 2006.225.07:46:28.74#ibcon#about to read 5, iclass 34, count 2 2006.225.07:46:28.74#ibcon#read 5, iclass 34, count 2 2006.225.07:46:28.74#ibcon#about to read 6, iclass 34, count 2 2006.225.07:46:28.74#ibcon#read 6, iclass 34, count 2 2006.225.07:46:28.74#ibcon#end of sib2, iclass 34, count 2 2006.225.07:46:28.74#ibcon#*after write, iclass 34, count 2 2006.225.07:46:28.74#ibcon#*before return 0, iclass 34, count 2 2006.225.07:46:28.74#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:46:28.74#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:46:28.74#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.07:46:28.74#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:28.74#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:46:28.86#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:46:28.86#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:46:28.86#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:46:28.86#ibcon#first serial, iclass 34, count 0 2006.225.07:46:28.86#ibcon#enter sib2, iclass 34, count 0 2006.225.07:46:28.86#ibcon#flushed, iclass 34, count 0 2006.225.07:46:28.86#ibcon#about to write, iclass 34, count 0 2006.225.07:46:28.86#ibcon#wrote, iclass 34, count 0 2006.225.07:46:28.86#ibcon#about to read 3, iclass 34, count 0 2006.225.07:46:28.88#ibcon#read 3, iclass 34, count 0 2006.225.07:46:28.88#ibcon#about to read 4, iclass 34, count 0 2006.225.07:46:28.88#ibcon#read 4, iclass 34, count 0 2006.225.07:46:28.88#ibcon#about to read 5, iclass 34, count 0 2006.225.07:46:28.88#ibcon#read 5, iclass 34, count 0 2006.225.07:46:28.88#ibcon#about to read 6, iclass 34, count 0 2006.225.07:46:28.88#ibcon#read 6, iclass 34, count 0 2006.225.07:46:28.88#ibcon#end of sib2, iclass 34, count 0 2006.225.07:46:28.88#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:46:28.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:46:28.88#ibcon#[25=USB\r\n] 2006.225.07:46:28.88#ibcon#*before write, iclass 34, count 0 2006.225.07:46:28.88#ibcon#enter sib2, iclass 34, count 0 2006.225.07:46:28.88#ibcon#flushed, iclass 34, count 0 2006.225.07:46:28.88#ibcon#about to write, iclass 34, count 0 2006.225.07:46:28.88#ibcon#wrote, iclass 34, count 0 2006.225.07:46:28.88#ibcon#about to read 3, iclass 34, count 0 2006.225.07:46:28.91#ibcon#read 3, iclass 34, count 0 2006.225.07:46:28.91#ibcon#about to read 4, iclass 34, count 0 2006.225.07:46:28.91#ibcon#read 4, iclass 34, count 0 2006.225.07:46:28.91#ibcon#about to read 5, iclass 34, count 0 2006.225.07:46:28.91#ibcon#read 5, iclass 34, count 0 2006.225.07:46:28.91#ibcon#about to read 6, iclass 34, count 0 2006.225.07:46:28.91#ibcon#read 6, iclass 34, count 0 2006.225.07:46:28.91#ibcon#end of sib2, iclass 34, count 0 2006.225.07:46:28.91#ibcon#*after write, iclass 34, count 0 2006.225.07:46:28.91#ibcon#*before return 0, iclass 34, count 0 2006.225.07:46:28.91#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:46:28.91#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:46:28.91#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:46:28.91#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:46:28.91$vc4f8/valo=4,832.99 2006.225.07:46:28.91#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.07:46:28.91#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.07:46:28.91#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:28.91#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:46:28.91#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:46:28.91#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:46:28.91#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:46:28.91#ibcon#first serial, iclass 36, count 0 2006.225.07:46:28.91#ibcon#enter sib2, iclass 36, count 0 2006.225.07:46:28.91#ibcon#flushed, iclass 36, count 0 2006.225.07:46:28.91#ibcon#about to write, iclass 36, count 0 2006.225.07:46:28.91#ibcon#wrote, iclass 36, count 0 2006.225.07:46:28.91#ibcon#about to read 3, iclass 36, count 0 2006.225.07:46:28.93#ibcon#read 3, iclass 36, count 0 2006.225.07:46:28.93#ibcon#about to read 4, iclass 36, count 0 2006.225.07:46:28.93#ibcon#read 4, iclass 36, count 0 2006.225.07:46:28.93#ibcon#about to read 5, iclass 36, count 0 2006.225.07:46:28.93#ibcon#read 5, iclass 36, count 0 2006.225.07:46:28.93#ibcon#about to read 6, iclass 36, count 0 2006.225.07:46:28.93#ibcon#read 6, iclass 36, count 0 2006.225.07:46:28.93#ibcon#end of sib2, iclass 36, count 0 2006.225.07:46:28.93#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:46:28.93#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:46:28.93#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:46:28.93#ibcon#*before write, iclass 36, count 0 2006.225.07:46:28.93#ibcon#enter sib2, iclass 36, count 0 2006.225.07:46:28.93#ibcon#flushed, iclass 36, count 0 2006.225.07:46:28.93#ibcon#about to write, iclass 36, count 0 2006.225.07:46:28.93#ibcon#wrote, iclass 36, count 0 2006.225.07:46:28.93#ibcon#about to read 3, iclass 36, count 0 2006.225.07:46:28.97#ibcon#read 3, iclass 36, count 0 2006.225.07:46:28.97#ibcon#about to read 4, iclass 36, count 0 2006.225.07:46:28.97#ibcon#read 4, iclass 36, count 0 2006.225.07:46:28.97#ibcon#about to read 5, iclass 36, count 0 2006.225.07:46:28.97#ibcon#read 5, iclass 36, count 0 2006.225.07:46:28.97#ibcon#about to read 6, iclass 36, count 0 2006.225.07:46:28.97#ibcon#read 6, iclass 36, count 0 2006.225.07:46:28.97#ibcon#end of sib2, iclass 36, count 0 2006.225.07:46:28.97#ibcon#*after write, iclass 36, count 0 2006.225.07:46:28.97#ibcon#*before return 0, iclass 36, count 0 2006.225.07:46:28.97#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:46:28.97#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:46:28.97#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:46:28.97#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:46:28.97$vc4f8/va=4,7 2006.225.07:46:28.97#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.07:46:28.97#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.07:46:28.97#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:28.97#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:46:29.03#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:46:29.03#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:46:29.03#ibcon#enter wrdev, iclass 38, count 2 2006.225.07:46:29.03#ibcon#first serial, iclass 38, count 2 2006.225.07:46:29.03#ibcon#enter sib2, iclass 38, count 2 2006.225.07:46:29.03#ibcon#flushed, iclass 38, count 2 2006.225.07:46:29.03#ibcon#about to write, iclass 38, count 2 2006.225.07:46:29.03#ibcon#wrote, iclass 38, count 2 2006.225.07:46:29.03#ibcon#about to read 3, iclass 38, count 2 2006.225.07:46:29.05#ibcon#read 3, iclass 38, count 2 2006.225.07:46:29.05#ibcon#about to read 4, iclass 38, count 2 2006.225.07:46:29.05#ibcon#read 4, iclass 38, count 2 2006.225.07:46:29.05#ibcon#about to read 5, iclass 38, count 2 2006.225.07:46:29.05#ibcon#read 5, iclass 38, count 2 2006.225.07:46:29.05#ibcon#about to read 6, iclass 38, count 2 2006.225.07:46:29.05#ibcon#read 6, iclass 38, count 2 2006.225.07:46:29.05#ibcon#end of sib2, iclass 38, count 2 2006.225.07:46:29.05#ibcon#*mode == 0, iclass 38, count 2 2006.225.07:46:29.05#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.07:46:29.05#ibcon#[25=AT04-07\r\n] 2006.225.07:46:29.05#ibcon#*before write, iclass 38, count 2 2006.225.07:46:29.05#ibcon#enter sib2, iclass 38, count 2 2006.225.07:46:29.05#ibcon#flushed, iclass 38, count 2 2006.225.07:46:29.05#ibcon#about to write, iclass 38, count 2 2006.225.07:46:29.05#ibcon#wrote, iclass 38, count 2 2006.225.07:46:29.05#ibcon#about to read 3, iclass 38, count 2 2006.225.07:46:29.08#ibcon#read 3, iclass 38, count 2 2006.225.07:46:29.08#ibcon#about to read 4, iclass 38, count 2 2006.225.07:46:29.08#ibcon#read 4, iclass 38, count 2 2006.225.07:46:29.08#ibcon#about to read 5, iclass 38, count 2 2006.225.07:46:29.08#ibcon#read 5, iclass 38, count 2 2006.225.07:46:29.08#ibcon#about to read 6, iclass 38, count 2 2006.225.07:46:29.08#ibcon#read 6, iclass 38, count 2 2006.225.07:46:29.08#ibcon#end of sib2, iclass 38, count 2 2006.225.07:46:29.08#ibcon#*after write, iclass 38, count 2 2006.225.07:46:29.08#ibcon#*before return 0, iclass 38, count 2 2006.225.07:46:29.08#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:46:29.08#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:46:29.08#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.07:46:29.08#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:29.08#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:46:29.14#abcon#<5=/06 3.0 5.7 28.11 721003.4\r\n> 2006.225.07:46:29.16#abcon#{5=INTERFACE CLEAR} 2006.225.07:46:29.20#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:46:29.20#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:46:29.20#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:46:29.20#ibcon#first serial, iclass 38, count 0 2006.225.07:46:29.20#ibcon#enter sib2, iclass 38, count 0 2006.225.07:46:29.20#ibcon#flushed, iclass 38, count 0 2006.225.07:46:29.20#ibcon#about to write, iclass 38, count 0 2006.225.07:46:29.20#ibcon#wrote, iclass 38, count 0 2006.225.07:46:29.20#ibcon#about to read 3, iclass 38, count 0 2006.225.07:46:29.22#ibcon#read 3, iclass 38, count 0 2006.225.07:46:29.22#ibcon#about to read 4, iclass 38, count 0 2006.225.07:46:29.22#ibcon#read 4, iclass 38, count 0 2006.225.07:46:29.22#ibcon#about to read 5, iclass 38, count 0 2006.225.07:46:29.22#ibcon#read 5, iclass 38, count 0 2006.225.07:46:29.22#ibcon#about to read 6, iclass 38, count 0 2006.225.07:46:29.22#ibcon#read 6, iclass 38, count 0 2006.225.07:46:29.22#ibcon#end of sib2, iclass 38, count 0 2006.225.07:46:29.22#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:46:29.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:46:29.22#ibcon#[25=USB\r\n] 2006.225.07:46:29.22#ibcon#*before write, iclass 38, count 0 2006.225.07:46:29.22#ibcon#enter sib2, iclass 38, count 0 2006.225.07:46:29.22#ibcon#flushed, iclass 38, count 0 2006.225.07:46:29.22#ibcon#about to write, iclass 38, count 0 2006.225.07:46:29.22#ibcon#wrote, iclass 38, count 0 2006.225.07:46:29.22#ibcon#about to read 3, iclass 38, count 0 2006.225.07:46:29.22#abcon#[5=S1D000X0/0*\r\n] 2006.225.07:46:29.25#ibcon#read 3, iclass 38, count 0 2006.225.07:46:29.25#ibcon#about to read 4, iclass 38, count 0 2006.225.07:46:29.25#ibcon#read 4, iclass 38, count 0 2006.225.07:46:29.25#ibcon#about to read 5, iclass 38, count 0 2006.225.07:46:29.25#ibcon#read 5, iclass 38, count 0 2006.225.07:46:29.25#ibcon#about to read 6, iclass 38, count 0 2006.225.07:46:29.25#ibcon#read 6, iclass 38, count 0 2006.225.07:46:29.25#ibcon#end of sib2, iclass 38, count 0 2006.225.07:46:29.25#ibcon#*after write, iclass 38, count 0 2006.225.07:46:29.25#ibcon#*before return 0, iclass 38, count 0 2006.225.07:46:29.25#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:46:29.25#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:46:29.25#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:46:29.25#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:46:29.25$vc4f8/valo=5,652.99 2006.225.07:46:29.25#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.07:46:29.25#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.07:46:29.25#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:29.25#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:46:29.25#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:46:29.25#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:46:29.25#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:46:29.25#ibcon#first serial, iclass 6, count 0 2006.225.07:46:29.25#ibcon#enter sib2, iclass 6, count 0 2006.225.07:46:29.25#ibcon#flushed, iclass 6, count 0 2006.225.07:46:29.25#ibcon#about to write, iclass 6, count 0 2006.225.07:46:29.25#ibcon#wrote, iclass 6, count 0 2006.225.07:46:29.25#ibcon#about to read 3, iclass 6, count 0 2006.225.07:46:29.27#ibcon#read 3, iclass 6, count 0 2006.225.07:46:29.27#ibcon#about to read 4, iclass 6, count 0 2006.225.07:46:29.27#ibcon#read 4, iclass 6, count 0 2006.225.07:46:29.27#ibcon#about to read 5, iclass 6, count 0 2006.225.07:46:29.27#ibcon#read 5, iclass 6, count 0 2006.225.07:46:29.27#ibcon#about to read 6, iclass 6, count 0 2006.225.07:46:29.27#ibcon#read 6, iclass 6, count 0 2006.225.07:46:29.27#ibcon#end of sib2, iclass 6, count 0 2006.225.07:46:29.27#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:46:29.27#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:46:29.27#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:46:29.27#ibcon#*before write, iclass 6, count 0 2006.225.07:46:29.27#ibcon#enter sib2, iclass 6, count 0 2006.225.07:46:29.27#ibcon#flushed, iclass 6, count 0 2006.225.07:46:29.27#ibcon#about to write, iclass 6, count 0 2006.225.07:46:29.27#ibcon#wrote, iclass 6, count 0 2006.225.07:46:29.27#ibcon#about to read 3, iclass 6, count 0 2006.225.07:46:29.31#ibcon#read 3, iclass 6, count 0 2006.225.07:46:29.31#ibcon#about to read 4, iclass 6, count 0 2006.225.07:46:29.31#ibcon#read 4, iclass 6, count 0 2006.225.07:46:29.31#ibcon#about to read 5, iclass 6, count 0 2006.225.07:46:29.31#ibcon#read 5, iclass 6, count 0 2006.225.07:46:29.31#ibcon#about to read 6, iclass 6, count 0 2006.225.07:46:29.31#ibcon#read 6, iclass 6, count 0 2006.225.07:46:29.31#ibcon#end of sib2, iclass 6, count 0 2006.225.07:46:29.31#ibcon#*after write, iclass 6, count 0 2006.225.07:46:29.31#ibcon#*before return 0, iclass 6, count 0 2006.225.07:46:29.31#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:46:29.31#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:46:29.31#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:46:29.31#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:46:29.31$vc4f8/va=5,7 2006.225.07:46:29.31#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.225.07:46:29.31#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.225.07:46:29.31#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:29.31#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:46:29.37#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:46:29.37#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:46:29.37#ibcon#enter wrdev, iclass 10, count 2 2006.225.07:46:29.37#ibcon#first serial, iclass 10, count 2 2006.225.07:46:29.37#ibcon#enter sib2, iclass 10, count 2 2006.225.07:46:29.37#ibcon#flushed, iclass 10, count 2 2006.225.07:46:29.37#ibcon#about to write, iclass 10, count 2 2006.225.07:46:29.37#ibcon#wrote, iclass 10, count 2 2006.225.07:46:29.37#ibcon#about to read 3, iclass 10, count 2 2006.225.07:46:29.39#ibcon#read 3, iclass 10, count 2 2006.225.07:46:29.39#ibcon#about to read 4, iclass 10, count 2 2006.225.07:46:29.39#ibcon#read 4, iclass 10, count 2 2006.225.07:46:29.39#ibcon#about to read 5, iclass 10, count 2 2006.225.07:46:29.39#ibcon#read 5, iclass 10, count 2 2006.225.07:46:29.39#ibcon#about to read 6, iclass 10, count 2 2006.225.07:46:29.39#ibcon#read 6, iclass 10, count 2 2006.225.07:46:29.39#ibcon#end of sib2, iclass 10, count 2 2006.225.07:46:29.39#ibcon#*mode == 0, iclass 10, count 2 2006.225.07:46:29.39#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.225.07:46:29.39#ibcon#[25=AT05-07\r\n] 2006.225.07:46:29.39#ibcon#*before write, iclass 10, count 2 2006.225.07:46:29.39#ibcon#enter sib2, iclass 10, count 2 2006.225.07:46:29.39#ibcon#flushed, iclass 10, count 2 2006.225.07:46:29.39#ibcon#about to write, iclass 10, count 2 2006.225.07:46:29.39#ibcon#wrote, iclass 10, count 2 2006.225.07:46:29.39#ibcon#about to read 3, iclass 10, count 2 2006.225.07:46:29.42#ibcon#read 3, iclass 10, count 2 2006.225.07:46:29.42#ibcon#about to read 4, iclass 10, count 2 2006.225.07:46:29.42#ibcon#read 4, iclass 10, count 2 2006.225.07:46:29.42#ibcon#about to read 5, iclass 10, count 2 2006.225.07:46:29.42#ibcon#read 5, iclass 10, count 2 2006.225.07:46:29.42#ibcon#about to read 6, iclass 10, count 2 2006.225.07:46:29.42#ibcon#read 6, iclass 10, count 2 2006.225.07:46:29.42#ibcon#end of sib2, iclass 10, count 2 2006.225.07:46:29.42#ibcon#*after write, iclass 10, count 2 2006.225.07:46:29.42#ibcon#*before return 0, iclass 10, count 2 2006.225.07:46:29.42#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:46:29.42#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:46:29.42#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.225.07:46:29.42#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:29.42#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:46:29.54#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:46:29.54#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:46:29.54#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:46:29.54#ibcon#first serial, iclass 10, count 0 2006.225.07:46:29.54#ibcon#enter sib2, iclass 10, count 0 2006.225.07:46:29.54#ibcon#flushed, iclass 10, count 0 2006.225.07:46:29.54#ibcon#about to write, iclass 10, count 0 2006.225.07:46:29.54#ibcon#wrote, iclass 10, count 0 2006.225.07:46:29.54#ibcon#about to read 3, iclass 10, count 0 2006.225.07:46:29.56#ibcon#read 3, iclass 10, count 0 2006.225.07:46:29.56#ibcon#about to read 4, iclass 10, count 0 2006.225.07:46:29.56#ibcon#read 4, iclass 10, count 0 2006.225.07:46:29.56#ibcon#about to read 5, iclass 10, count 0 2006.225.07:46:29.56#ibcon#read 5, iclass 10, count 0 2006.225.07:46:29.56#ibcon#about to read 6, iclass 10, count 0 2006.225.07:46:29.56#ibcon#read 6, iclass 10, count 0 2006.225.07:46:29.56#ibcon#end of sib2, iclass 10, count 0 2006.225.07:46:29.56#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:46:29.56#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:46:29.56#ibcon#[25=USB\r\n] 2006.225.07:46:29.56#ibcon#*before write, iclass 10, count 0 2006.225.07:46:29.56#ibcon#enter sib2, iclass 10, count 0 2006.225.07:46:29.56#ibcon#flushed, iclass 10, count 0 2006.225.07:46:29.56#ibcon#about to write, iclass 10, count 0 2006.225.07:46:29.56#ibcon#wrote, iclass 10, count 0 2006.225.07:46:29.56#ibcon#about to read 3, iclass 10, count 0 2006.225.07:46:29.59#ibcon#read 3, iclass 10, count 0 2006.225.07:46:29.59#ibcon#about to read 4, iclass 10, count 0 2006.225.07:46:29.59#ibcon#read 4, iclass 10, count 0 2006.225.07:46:29.59#ibcon#about to read 5, iclass 10, count 0 2006.225.07:46:29.59#ibcon#read 5, iclass 10, count 0 2006.225.07:46:29.59#ibcon#about to read 6, iclass 10, count 0 2006.225.07:46:29.59#ibcon#read 6, iclass 10, count 0 2006.225.07:46:29.59#ibcon#end of sib2, iclass 10, count 0 2006.225.07:46:29.59#ibcon#*after write, iclass 10, count 0 2006.225.07:46:29.59#ibcon#*before return 0, iclass 10, count 0 2006.225.07:46:29.59#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:46:29.59#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:46:29.59#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:46:29.59#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:46:29.59$vc4f8/valo=6,772.99 2006.225.07:46:29.59#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.07:46:29.59#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.07:46:29.59#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:29.59#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:46:29.59#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:46:29.59#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:46:29.59#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:46:29.59#ibcon#first serial, iclass 12, count 0 2006.225.07:46:29.59#ibcon#enter sib2, iclass 12, count 0 2006.225.07:46:29.59#ibcon#flushed, iclass 12, count 0 2006.225.07:46:29.59#ibcon#about to write, iclass 12, count 0 2006.225.07:46:29.59#ibcon#wrote, iclass 12, count 0 2006.225.07:46:29.59#ibcon#about to read 3, iclass 12, count 0 2006.225.07:46:29.61#ibcon#read 3, iclass 12, count 0 2006.225.07:46:29.61#ibcon#about to read 4, iclass 12, count 0 2006.225.07:46:29.61#ibcon#read 4, iclass 12, count 0 2006.225.07:46:29.61#ibcon#about to read 5, iclass 12, count 0 2006.225.07:46:29.61#ibcon#read 5, iclass 12, count 0 2006.225.07:46:29.61#ibcon#about to read 6, iclass 12, count 0 2006.225.07:46:29.61#ibcon#read 6, iclass 12, count 0 2006.225.07:46:29.61#ibcon#end of sib2, iclass 12, count 0 2006.225.07:46:29.61#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:46:29.61#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:46:29.61#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:46:29.61#ibcon#*before write, iclass 12, count 0 2006.225.07:46:29.61#ibcon#enter sib2, iclass 12, count 0 2006.225.07:46:29.61#ibcon#flushed, iclass 12, count 0 2006.225.07:46:29.61#ibcon#about to write, iclass 12, count 0 2006.225.07:46:29.61#ibcon#wrote, iclass 12, count 0 2006.225.07:46:29.61#ibcon#about to read 3, iclass 12, count 0 2006.225.07:46:29.65#ibcon#read 3, iclass 12, count 0 2006.225.07:46:29.65#ibcon#about to read 4, iclass 12, count 0 2006.225.07:46:29.65#ibcon#read 4, iclass 12, count 0 2006.225.07:46:29.65#ibcon#about to read 5, iclass 12, count 0 2006.225.07:46:29.65#ibcon#read 5, iclass 12, count 0 2006.225.07:46:29.65#ibcon#about to read 6, iclass 12, count 0 2006.225.07:46:29.65#ibcon#read 6, iclass 12, count 0 2006.225.07:46:29.65#ibcon#end of sib2, iclass 12, count 0 2006.225.07:46:29.65#ibcon#*after write, iclass 12, count 0 2006.225.07:46:29.65#ibcon#*before return 0, iclass 12, count 0 2006.225.07:46:29.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:46:29.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:46:29.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:46:29.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:46:29.65$vc4f8/va=6,6 2006.225.07:46:29.65#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.225.07:46:29.65#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.225.07:46:29.65#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:29.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:46:29.71#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:46:29.71#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:46:29.71#ibcon#enter wrdev, iclass 14, count 2 2006.225.07:46:29.71#ibcon#first serial, iclass 14, count 2 2006.225.07:46:29.71#ibcon#enter sib2, iclass 14, count 2 2006.225.07:46:29.71#ibcon#flushed, iclass 14, count 2 2006.225.07:46:29.71#ibcon#about to write, iclass 14, count 2 2006.225.07:46:29.71#ibcon#wrote, iclass 14, count 2 2006.225.07:46:29.71#ibcon#about to read 3, iclass 14, count 2 2006.225.07:46:29.73#ibcon#read 3, iclass 14, count 2 2006.225.07:46:29.73#ibcon#about to read 4, iclass 14, count 2 2006.225.07:46:29.73#ibcon#read 4, iclass 14, count 2 2006.225.07:46:29.73#ibcon#about to read 5, iclass 14, count 2 2006.225.07:46:29.73#ibcon#read 5, iclass 14, count 2 2006.225.07:46:29.73#ibcon#about to read 6, iclass 14, count 2 2006.225.07:46:29.73#ibcon#read 6, iclass 14, count 2 2006.225.07:46:29.73#ibcon#end of sib2, iclass 14, count 2 2006.225.07:46:29.73#ibcon#*mode == 0, iclass 14, count 2 2006.225.07:46:29.73#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.225.07:46:29.73#ibcon#[25=AT06-06\r\n] 2006.225.07:46:29.73#ibcon#*before write, iclass 14, count 2 2006.225.07:46:29.73#ibcon#enter sib2, iclass 14, count 2 2006.225.07:46:29.73#ibcon#flushed, iclass 14, count 2 2006.225.07:46:29.73#ibcon#about to write, iclass 14, count 2 2006.225.07:46:29.73#ibcon#wrote, iclass 14, count 2 2006.225.07:46:29.73#ibcon#about to read 3, iclass 14, count 2 2006.225.07:46:29.76#ibcon#read 3, iclass 14, count 2 2006.225.07:46:29.76#ibcon#about to read 4, iclass 14, count 2 2006.225.07:46:29.76#ibcon#read 4, iclass 14, count 2 2006.225.07:46:29.76#ibcon#about to read 5, iclass 14, count 2 2006.225.07:46:29.76#ibcon#read 5, iclass 14, count 2 2006.225.07:46:29.76#ibcon#about to read 6, iclass 14, count 2 2006.225.07:46:29.76#ibcon#read 6, iclass 14, count 2 2006.225.07:46:29.76#ibcon#end of sib2, iclass 14, count 2 2006.225.07:46:29.76#ibcon#*after write, iclass 14, count 2 2006.225.07:46:29.76#ibcon#*before return 0, iclass 14, count 2 2006.225.07:46:29.76#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:46:29.76#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:46:29.76#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.225.07:46:29.76#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:29.76#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:46:29.88#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:46:29.88#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:46:29.88#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:46:29.88#ibcon#first serial, iclass 14, count 0 2006.225.07:46:29.88#ibcon#enter sib2, iclass 14, count 0 2006.225.07:46:29.88#ibcon#flushed, iclass 14, count 0 2006.225.07:46:29.88#ibcon#about to write, iclass 14, count 0 2006.225.07:46:29.88#ibcon#wrote, iclass 14, count 0 2006.225.07:46:29.88#ibcon#about to read 3, iclass 14, count 0 2006.225.07:46:29.90#ibcon#read 3, iclass 14, count 0 2006.225.07:46:29.90#ibcon#about to read 4, iclass 14, count 0 2006.225.07:46:29.90#ibcon#read 4, iclass 14, count 0 2006.225.07:46:29.90#ibcon#about to read 5, iclass 14, count 0 2006.225.07:46:29.90#ibcon#read 5, iclass 14, count 0 2006.225.07:46:29.90#ibcon#about to read 6, iclass 14, count 0 2006.225.07:46:29.90#ibcon#read 6, iclass 14, count 0 2006.225.07:46:29.90#ibcon#end of sib2, iclass 14, count 0 2006.225.07:46:29.90#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:46:29.90#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:46:29.90#ibcon#[25=USB\r\n] 2006.225.07:46:29.90#ibcon#*before write, iclass 14, count 0 2006.225.07:46:29.90#ibcon#enter sib2, iclass 14, count 0 2006.225.07:46:29.90#ibcon#flushed, iclass 14, count 0 2006.225.07:46:29.90#ibcon#about to write, iclass 14, count 0 2006.225.07:46:29.90#ibcon#wrote, iclass 14, count 0 2006.225.07:46:29.90#ibcon#about to read 3, iclass 14, count 0 2006.225.07:46:29.93#ibcon#read 3, iclass 14, count 0 2006.225.07:46:29.93#ibcon#about to read 4, iclass 14, count 0 2006.225.07:46:29.93#ibcon#read 4, iclass 14, count 0 2006.225.07:46:29.93#ibcon#about to read 5, iclass 14, count 0 2006.225.07:46:29.93#ibcon#read 5, iclass 14, count 0 2006.225.07:46:29.93#ibcon#about to read 6, iclass 14, count 0 2006.225.07:46:29.93#ibcon#read 6, iclass 14, count 0 2006.225.07:46:29.93#ibcon#end of sib2, iclass 14, count 0 2006.225.07:46:29.93#ibcon#*after write, iclass 14, count 0 2006.225.07:46:29.93#ibcon#*before return 0, iclass 14, count 0 2006.225.07:46:29.93#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:46:29.93#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:46:29.93#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:46:29.93#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:46:29.93$vc4f8/valo=7,832.99 2006.225.07:46:29.93#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.07:46:29.93#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.07:46:29.93#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:29.93#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:46:29.93#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:46:29.93#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:46:29.93#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:46:29.93#ibcon#first serial, iclass 16, count 0 2006.225.07:46:29.93#ibcon#enter sib2, iclass 16, count 0 2006.225.07:46:29.93#ibcon#flushed, iclass 16, count 0 2006.225.07:46:29.93#ibcon#about to write, iclass 16, count 0 2006.225.07:46:29.93#ibcon#wrote, iclass 16, count 0 2006.225.07:46:29.93#ibcon#about to read 3, iclass 16, count 0 2006.225.07:46:29.95#ibcon#read 3, iclass 16, count 0 2006.225.07:46:29.95#ibcon#about to read 4, iclass 16, count 0 2006.225.07:46:29.95#ibcon#read 4, iclass 16, count 0 2006.225.07:46:29.95#ibcon#about to read 5, iclass 16, count 0 2006.225.07:46:29.95#ibcon#read 5, iclass 16, count 0 2006.225.07:46:29.95#ibcon#about to read 6, iclass 16, count 0 2006.225.07:46:29.95#ibcon#read 6, iclass 16, count 0 2006.225.07:46:29.95#ibcon#end of sib2, iclass 16, count 0 2006.225.07:46:29.95#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:46:29.95#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:46:29.95#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:46:29.95#ibcon#*before write, iclass 16, count 0 2006.225.07:46:29.95#ibcon#enter sib2, iclass 16, count 0 2006.225.07:46:29.95#ibcon#flushed, iclass 16, count 0 2006.225.07:46:29.95#ibcon#about to write, iclass 16, count 0 2006.225.07:46:29.95#ibcon#wrote, iclass 16, count 0 2006.225.07:46:29.95#ibcon#about to read 3, iclass 16, count 0 2006.225.07:46:29.99#ibcon#read 3, iclass 16, count 0 2006.225.07:46:29.99#ibcon#about to read 4, iclass 16, count 0 2006.225.07:46:29.99#ibcon#read 4, iclass 16, count 0 2006.225.07:46:29.99#ibcon#about to read 5, iclass 16, count 0 2006.225.07:46:29.99#ibcon#read 5, iclass 16, count 0 2006.225.07:46:29.99#ibcon#about to read 6, iclass 16, count 0 2006.225.07:46:29.99#ibcon#read 6, iclass 16, count 0 2006.225.07:46:29.99#ibcon#end of sib2, iclass 16, count 0 2006.225.07:46:29.99#ibcon#*after write, iclass 16, count 0 2006.225.07:46:29.99#ibcon#*before return 0, iclass 16, count 0 2006.225.07:46:29.99#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:46:29.99#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:46:29.99#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:46:29.99#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:46:29.99$vc4f8/va=7,6 2006.225.07:46:29.99#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.225.07:46:29.99#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.225.07:46:29.99#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:29.99#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:46:30.05#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:46:30.05#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:46:30.05#ibcon#enter wrdev, iclass 18, count 2 2006.225.07:46:30.05#ibcon#first serial, iclass 18, count 2 2006.225.07:46:30.05#ibcon#enter sib2, iclass 18, count 2 2006.225.07:46:30.05#ibcon#flushed, iclass 18, count 2 2006.225.07:46:30.05#ibcon#about to write, iclass 18, count 2 2006.225.07:46:30.05#ibcon#wrote, iclass 18, count 2 2006.225.07:46:30.05#ibcon#about to read 3, iclass 18, count 2 2006.225.07:46:30.07#ibcon#read 3, iclass 18, count 2 2006.225.07:46:30.07#ibcon#about to read 4, iclass 18, count 2 2006.225.07:46:30.07#ibcon#read 4, iclass 18, count 2 2006.225.07:46:30.07#ibcon#about to read 5, iclass 18, count 2 2006.225.07:46:30.07#ibcon#read 5, iclass 18, count 2 2006.225.07:46:30.07#ibcon#about to read 6, iclass 18, count 2 2006.225.07:46:30.07#ibcon#read 6, iclass 18, count 2 2006.225.07:46:30.07#ibcon#end of sib2, iclass 18, count 2 2006.225.07:46:30.07#ibcon#*mode == 0, iclass 18, count 2 2006.225.07:46:30.07#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.225.07:46:30.07#ibcon#[25=AT07-06\r\n] 2006.225.07:46:30.07#ibcon#*before write, iclass 18, count 2 2006.225.07:46:30.07#ibcon#enter sib2, iclass 18, count 2 2006.225.07:46:30.07#ibcon#flushed, iclass 18, count 2 2006.225.07:46:30.07#ibcon#about to write, iclass 18, count 2 2006.225.07:46:30.07#ibcon#wrote, iclass 18, count 2 2006.225.07:46:30.07#ibcon#about to read 3, iclass 18, count 2 2006.225.07:46:30.10#ibcon#read 3, iclass 18, count 2 2006.225.07:46:30.10#ibcon#about to read 4, iclass 18, count 2 2006.225.07:46:30.10#ibcon#read 4, iclass 18, count 2 2006.225.07:46:30.10#ibcon#about to read 5, iclass 18, count 2 2006.225.07:46:30.10#ibcon#read 5, iclass 18, count 2 2006.225.07:46:30.10#ibcon#about to read 6, iclass 18, count 2 2006.225.07:46:30.10#ibcon#read 6, iclass 18, count 2 2006.225.07:46:30.10#ibcon#end of sib2, iclass 18, count 2 2006.225.07:46:30.10#ibcon#*after write, iclass 18, count 2 2006.225.07:46:30.10#ibcon#*before return 0, iclass 18, count 2 2006.225.07:46:30.10#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:46:30.10#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:46:30.10#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.225.07:46:30.10#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:30.10#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:46:30.22#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:46:30.22#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:46:30.22#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:46:30.22#ibcon#first serial, iclass 18, count 0 2006.225.07:46:30.22#ibcon#enter sib2, iclass 18, count 0 2006.225.07:46:30.22#ibcon#flushed, iclass 18, count 0 2006.225.07:46:30.22#ibcon#about to write, iclass 18, count 0 2006.225.07:46:30.22#ibcon#wrote, iclass 18, count 0 2006.225.07:46:30.22#ibcon#about to read 3, iclass 18, count 0 2006.225.07:46:30.24#ibcon#read 3, iclass 18, count 0 2006.225.07:46:30.24#ibcon#about to read 4, iclass 18, count 0 2006.225.07:46:30.24#ibcon#read 4, iclass 18, count 0 2006.225.07:46:30.24#ibcon#about to read 5, iclass 18, count 0 2006.225.07:46:30.24#ibcon#read 5, iclass 18, count 0 2006.225.07:46:30.24#ibcon#about to read 6, iclass 18, count 0 2006.225.07:46:30.24#ibcon#read 6, iclass 18, count 0 2006.225.07:46:30.24#ibcon#end of sib2, iclass 18, count 0 2006.225.07:46:30.24#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:46:30.24#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:46:30.24#ibcon#[25=USB\r\n] 2006.225.07:46:30.24#ibcon#*before write, iclass 18, count 0 2006.225.07:46:30.24#ibcon#enter sib2, iclass 18, count 0 2006.225.07:46:30.24#ibcon#flushed, iclass 18, count 0 2006.225.07:46:30.24#ibcon#about to write, iclass 18, count 0 2006.225.07:46:30.24#ibcon#wrote, iclass 18, count 0 2006.225.07:46:30.24#ibcon#about to read 3, iclass 18, count 0 2006.225.07:46:30.27#ibcon#read 3, iclass 18, count 0 2006.225.07:46:30.27#ibcon#about to read 4, iclass 18, count 0 2006.225.07:46:30.27#ibcon#read 4, iclass 18, count 0 2006.225.07:46:30.27#ibcon#about to read 5, iclass 18, count 0 2006.225.07:46:30.27#ibcon#read 5, iclass 18, count 0 2006.225.07:46:30.27#ibcon#about to read 6, iclass 18, count 0 2006.225.07:46:30.27#ibcon#read 6, iclass 18, count 0 2006.225.07:46:30.27#ibcon#end of sib2, iclass 18, count 0 2006.225.07:46:30.27#ibcon#*after write, iclass 18, count 0 2006.225.07:46:30.27#ibcon#*before return 0, iclass 18, count 0 2006.225.07:46:30.27#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:46:30.27#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:46:30.27#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:46:30.27#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:46:30.27$vc4f8/valo=8,852.99 2006.225.07:46:30.27#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.225.07:46:30.27#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.225.07:46:30.27#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:30.27#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:46:30.27#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:46:30.27#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:46:30.27#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:46:30.27#ibcon#first serial, iclass 20, count 0 2006.225.07:46:30.27#ibcon#enter sib2, iclass 20, count 0 2006.225.07:46:30.27#ibcon#flushed, iclass 20, count 0 2006.225.07:46:30.27#ibcon#about to write, iclass 20, count 0 2006.225.07:46:30.27#ibcon#wrote, iclass 20, count 0 2006.225.07:46:30.27#ibcon#about to read 3, iclass 20, count 0 2006.225.07:46:30.29#ibcon#read 3, iclass 20, count 0 2006.225.07:46:30.29#ibcon#about to read 4, iclass 20, count 0 2006.225.07:46:30.29#ibcon#read 4, iclass 20, count 0 2006.225.07:46:30.29#ibcon#about to read 5, iclass 20, count 0 2006.225.07:46:30.29#ibcon#read 5, iclass 20, count 0 2006.225.07:46:30.29#ibcon#about to read 6, iclass 20, count 0 2006.225.07:46:30.29#ibcon#read 6, iclass 20, count 0 2006.225.07:46:30.29#ibcon#end of sib2, iclass 20, count 0 2006.225.07:46:30.29#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:46:30.29#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:46:30.29#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:46:30.29#ibcon#*before write, iclass 20, count 0 2006.225.07:46:30.29#ibcon#enter sib2, iclass 20, count 0 2006.225.07:46:30.29#ibcon#flushed, iclass 20, count 0 2006.225.07:46:30.29#ibcon#about to write, iclass 20, count 0 2006.225.07:46:30.29#ibcon#wrote, iclass 20, count 0 2006.225.07:46:30.29#ibcon#about to read 3, iclass 20, count 0 2006.225.07:46:30.33#ibcon#read 3, iclass 20, count 0 2006.225.07:46:30.33#ibcon#about to read 4, iclass 20, count 0 2006.225.07:46:30.33#ibcon#read 4, iclass 20, count 0 2006.225.07:46:30.33#ibcon#about to read 5, iclass 20, count 0 2006.225.07:46:30.33#ibcon#read 5, iclass 20, count 0 2006.225.07:46:30.33#ibcon#about to read 6, iclass 20, count 0 2006.225.07:46:30.33#ibcon#read 6, iclass 20, count 0 2006.225.07:46:30.33#ibcon#end of sib2, iclass 20, count 0 2006.225.07:46:30.33#ibcon#*after write, iclass 20, count 0 2006.225.07:46:30.33#ibcon#*before return 0, iclass 20, count 0 2006.225.07:46:30.33#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:46:30.33#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:46:30.33#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:46:30.33#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:46:30.33$vc4f8/va=8,7 2006.225.07:46:30.33#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.225.07:46:30.33#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.225.07:46:30.33#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:30.33#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:46:30.39#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:46:30.39#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:46:30.39#ibcon#enter wrdev, iclass 22, count 2 2006.225.07:46:30.39#ibcon#first serial, iclass 22, count 2 2006.225.07:46:30.39#ibcon#enter sib2, iclass 22, count 2 2006.225.07:46:30.39#ibcon#flushed, iclass 22, count 2 2006.225.07:46:30.39#ibcon#about to write, iclass 22, count 2 2006.225.07:46:30.39#ibcon#wrote, iclass 22, count 2 2006.225.07:46:30.39#ibcon#about to read 3, iclass 22, count 2 2006.225.07:46:30.41#ibcon#read 3, iclass 22, count 2 2006.225.07:46:30.41#ibcon#about to read 4, iclass 22, count 2 2006.225.07:46:30.41#ibcon#read 4, iclass 22, count 2 2006.225.07:46:30.41#ibcon#about to read 5, iclass 22, count 2 2006.225.07:46:30.41#ibcon#read 5, iclass 22, count 2 2006.225.07:46:30.41#ibcon#about to read 6, iclass 22, count 2 2006.225.07:46:30.41#ibcon#read 6, iclass 22, count 2 2006.225.07:46:30.41#ibcon#end of sib2, iclass 22, count 2 2006.225.07:46:30.41#ibcon#*mode == 0, iclass 22, count 2 2006.225.07:46:30.41#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.225.07:46:30.41#ibcon#[25=AT08-07\r\n] 2006.225.07:46:30.41#ibcon#*before write, iclass 22, count 2 2006.225.07:46:30.41#ibcon#enter sib2, iclass 22, count 2 2006.225.07:46:30.41#ibcon#flushed, iclass 22, count 2 2006.225.07:46:30.41#ibcon#about to write, iclass 22, count 2 2006.225.07:46:30.41#ibcon#wrote, iclass 22, count 2 2006.225.07:46:30.41#ibcon#about to read 3, iclass 22, count 2 2006.225.07:46:30.44#ibcon#read 3, iclass 22, count 2 2006.225.07:46:30.44#ibcon#about to read 4, iclass 22, count 2 2006.225.07:46:30.44#ibcon#read 4, iclass 22, count 2 2006.225.07:46:30.44#ibcon#about to read 5, iclass 22, count 2 2006.225.07:46:30.44#ibcon#read 5, iclass 22, count 2 2006.225.07:46:30.44#ibcon#about to read 6, iclass 22, count 2 2006.225.07:46:30.44#ibcon#read 6, iclass 22, count 2 2006.225.07:46:30.44#ibcon#end of sib2, iclass 22, count 2 2006.225.07:46:30.44#ibcon#*after write, iclass 22, count 2 2006.225.07:46:30.44#ibcon#*before return 0, iclass 22, count 2 2006.225.07:46:30.44#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:46:30.44#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:46:30.44#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.225.07:46:30.44#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:30.44#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:46:30.56#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:46:30.56#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:46:30.56#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:46:30.56#ibcon#first serial, iclass 22, count 0 2006.225.07:46:30.56#ibcon#enter sib2, iclass 22, count 0 2006.225.07:46:30.56#ibcon#flushed, iclass 22, count 0 2006.225.07:46:30.56#ibcon#about to write, iclass 22, count 0 2006.225.07:46:30.56#ibcon#wrote, iclass 22, count 0 2006.225.07:46:30.56#ibcon#about to read 3, iclass 22, count 0 2006.225.07:46:30.58#ibcon#read 3, iclass 22, count 0 2006.225.07:46:30.58#ibcon#about to read 4, iclass 22, count 0 2006.225.07:46:30.58#ibcon#read 4, iclass 22, count 0 2006.225.07:46:30.58#ibcon#about to read 5, iclass 22, count 0 2006.225.07:46:30.58#ibcon#read 5, iclass 22, count 0 2006.225.07:46:30.58#ibcon#about to read 6, iclass 22, count 0 2006.225.07:46:30.58#ibcon#read 6, iclass 22, count 0 2006.225.07:46:30.58#ibcon#end of sib2, iclass 22, count 0 2006.225.07:46:30.58#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:46:30.58#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:46:30.58#ibcon#[25=USB\r\n] 2006.225.07:46:30.58#ibcon#*before write, iclass 22, count 0 2006.225.07:46:30.58#ibcon#enter sib2, iclass 22, count 0 2006.225.07:46:30.58#ibcon#flushed, iclass 22, count 0 2006.225.07:46:30.58#ibcon#about to write, iclass 22, count 0 2006.225.07:46:30.58#ibcon#wrote, iclass 22, count 0 2006.225.07:46:30.58#ibcon#about to read 3, iclass 22, count 0 2006.225.07:46:30.61#ibcon#read 3, iclass 22, count 0 2006.225.07:46:30.61#ibcon#about to read 4, iclass 22, count 0 2006.225.07:46:30.61#ibcon#read 4, iclass 22, count 0 2006.225.07:46:30.61#ibcon#about to read 5, iclass 22, count 0 2006.225.07:46:30.61#ibcon#read 5, iclass 22, count 0 2006.225.07:46:30.61#ibcon#about to read 6, iclass 22, count 0 2006.225.07:46:30.61#ibcon#read 6, iclass 22, count 0 2006.225.07:46:30.61#ibcon#end of sib2, iclass 22, count 0 2006.225.07:46:30.61#ibcon#*after write, iclass 22, count 0 2006.225.07:46:30.61#ibcon#*before return 0, iclass 22, count 0 2006.225.07:46:30.61#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:46:30.61#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:46:30.61#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:46:30.61#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:46:30.61$vc4f8/vblo=1,632.99 2006.225.07:46:30.61#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.07:46:30.61#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.07:46:30.61#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:30.61#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:46:30.61#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:46:30.61#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:46:30.61#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:46:30.61#ibcon#first serial, iclass 24, count 0 2006.225.07:46:30.61#ibcon#enter sib2, iclass 24, count 0 2006.225.07:46:30.61#ibcon#flushed, iclass 24, count 0 2006.225.07:46:30.61#ibcon#about to write, iclass 24, count 0 2006.225.07:46:30.61#ibcon#wrote, iclass 24, count 0 2006.225.07:46:30.61#ibcon#about to read 3, iclass 24, count 0 2006.225.07:46:30.63#ibcon#read 3, iclass 24, count 0 2006.225.07:46:30.63#ibcon#about to read 4, iclass 24, count 0 2006.225.07:46:30.63#ibcon#read 4, iclass 24, count 0 2006.225.07:46:30.63#ibcon#about to read 5, iclass 24, count 0 2006.225.07:46:30.63#ibcon#read 5, iclass 24, count 0 2006.225.07:46:30.63#ibcon#about to read 6, iclass 24, count 0 2006.225.07:46:30.63#ibcon#read 6, iclass 24, count 0 2006.225.07:46:30.63#ibcon#end of sib2, iclass 24, count 0 2006.225.07:46:30.63#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:46:30.63#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:46:30.63#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:46:30.63#ibcon#*before write, iclass 24, count 0 2006.225.07:46:30.63#ibcon#enter sib2, iclass 24, count 0 2006.225.07:46:30.63#ibcon#flushed, iclass 24, count 0 2006.225.07:46:30.63#ibcon#about to write, iclass 24, count 0 2006.225.07:46:30.63#ibcon#wrote, iclass 24, count 0 2006.225.07:46:30.63#ibcon#about to read 3, iclass 24, count 0 2006.225.07:46:30.67#ibcon#read 3, iclass 24, count 0 2006.225.07:46:30.67#ibcon#about to read 4, iclass 24, count 0 2006.225.07:46:30.67#ibcon#read 4, iclass 24, count 0 2006.225.07:46:30.67#ibcon#about to read 5, iclass 24, count 0 2006.225.07:46:30.67#ibcon#read 5, iclass 24, count 0 2006.225.07:46:30.67#ibcon#about to read 6, iclass 24, count 0 2006.225.07:46:30.67#ibcon#read 6, iclass 24, count 0 2006.225.07:46:30.67#ibcon#end of sib2, iclass 24, count 0 2006.225.07:46:30.67#ibcon#*after write, iclass 24, count 0 2006.225.07:46:30.67#ibcon#*before return 0, iclass 24, count 0 2006.225.07:46:30.67#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:46:30.67#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:46:30.67#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:46:30.67#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:46:30.67$vc4f8/vb=1,4 2006.225.07:46:30.67#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.225.07:46:30.67#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.225.07:46:30.67#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:30.67#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:46:30.67#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:46:30.67#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:46:30.67#ibcon#enter wrdev, iclass 26, count 2 2006.225.07:46:30.67#ibcon#first serial, iclass 26, count 2 2006.225.07:46:30.67#ibcon#enter sib2, iclass 26, count 2 2006.225.07:46:30.67#ibcon#flushed, iclass 26, count 2 2006.225.07:46:30.67#ibcon#about to write, iclass 26, count 2 2006.225.07:46:30.67#ibcon#wrote, iclass 26, count 2 2006.225.07:46:30.67#ibcon#about to read 3, iclass 26, count 2 2006.225.07:46:30.69#ibcon#read 3, iclass 26, count 2 2006.225.07:46:30.69#ibcon#about to read 4, iclass 26, count 2 2006.225.07:46:30.69#ibcon#read 4, iclass 26, count 2 2006.225.07:46:30.69#ibcon#about to read 5, iclass 26, count 2 2006.225.07:46:30.69#ibcon#read 5, iclass 26, count 2 2006.225.07:46:30.69#ibcon#about to read 6, iclass 26, count 2 2006.225.07:46:30.69#ibcon#read 6, iclass 26, count 2 2006.225.07:46:30.69#ibcon#end of sib2, iclass 26, count 2 2006.225.07:46:30.69#ibcon#*mode == 0, iclass 26, count 2 2006.225.07:46:30.69#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.225.07:46:30.69#ibcon#[27=AT01-04\r\n] 2006.225.07:46:30.69#ibcon#*before write, iclass 26, count 2 2006.225.07:46:30.69#ibcon#enter sib2, iclass 26, count 2 2006.225.07:46:30.69#ibcon#flushed, iclass 26, count 2 2006.225.07:46:30.69#ibcon#about to write, iclass 26, count 2 2006.225.07:46:30.69#ibcon#wrote, iclass 26, count 2 2006.225.07:46:30.69#ibcon#about to read 3, iclass 26, count 2 2006.225.07:46:30.72#ibcon#read 3, iclass 26, count 2 2006.225.07:46:30.72#ibcon#about to read 4, iclass 26, count 2 2006.225.07:46:30.72#ibcon#read 4, iclass 26, count 2 2006.225.07:46:30.72#ibcon#about to read 5, iclass 26, count 2 2006.225.07:46:30.72#ibcon#read 5, iclass 26, count 2 2006.225.07:46:30.72#ibcon#about to read 6, iclass 26, count 2 2006.225.07:46:30.72#ibcon#read 6, iclass 26, count 2 2006.225.07:46:30.72#ibcon#end of sib2, iclass 26, count 2 2006.225.07:46:30.72#ibcon#*after write, iclass 26, count 2 2006.225.07:46:30.72#ibcon#*before return 0, iclass 26, count 2 2006.225.07:46:30.72#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:46:30.72#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:46:30.72#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.225.07:46:30.72#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:30.72#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:46:30.84#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:46:30.84#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:46:30.84#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:46:30.84#ibcon#first serial, iclass 26, count 0 2006.225.07:46:30.84#ibcon#enter sib2, iclass 26, count 0 2006.225.07:46:30.84#ibcon#flushed, iclass 26, count 0 2006.225.07:46:30.84#ibcon#about to write, iclass 26, count 0 2006.225.07:46:30.84#ibcon#wrote, iclass 26, count 0 2006.225.07:46:30.84#ibcon#about to read 3, iclass 26, count 0 2006.225.07:46:30.86#ibcon#read 3, iclass 26, count 0 2006.225.07:46:30.86#ibcon#about to read 4, iclass 26, count 0 2006.225.07:46:30.86#ibcon#read 4, iclass 26, count 0 2006.225.07:46:30.86#ibcon#about to read 5, iclass 26, count 0 2006.225.07:46:30.86#ibcon#read 5, iclass 26, count 0 2006.225.07:46:30.86#ibcon#about to read 6, iclass 26, count 0 2006.225.07:46:30.86#ibcon#read 6, iclass 26, count 0 2006.225.07:46:30.86#ibcon#end of sib2, iclass 26, count 0 2006.225.07:46:30.86#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:46:30.86#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:46:30.86#ibcon#[27=USB\r\n] 2006.225.07:46:30.86#ibcon#*before write, iclass 26, count 0 2006.225.07:46:30.86#ibcon#enter sib2, iclass 26, count 0 2006.225.07:46:30.86#ibcon#flushed, iclass 26, count 0 2006.225.07:46:30.86#ibcon#about to write, iclass 26, count 0 2006.225.07:46:30.86#ibcon#wrote, iclass 26, count 0 2006.225.07:46:30.86#ibcon#about to read 3, iclass 26, count 0 2006.225.07:46:30.89#ibcon#read 3, iclass 26, count 0 2006.225.07:46:30.89#ibcon#about to read 4, iclass 26, count 0 2006.225.07:46:30.89#ibcon#read 4, iclass 26, count 0 2006.225.07:46:30.89#ibcon#about to read 5, iclass 26, count 0 2006.225.07:46:30.89#ibcon#read 5, iclass 26, count 0 2006.225.07:46:30.89#ibcon#about to read 6, iclass 26, count 0 2006.225.07:46:30.89#ibcon#read 6, iclass 26, count 0 2006.225.07:46:30.89#ibcon#end of sib2, iclass 26, count 0 2006.225.07:46:30.89#ibcon#*after write, iclass 26, count 0 2006.225.07:46:30.89#ibcon#*before return 0, iclass 26, count 0 2006.225.07:46:30.89#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:46:30.89#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:46:30.89#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:46:30.89#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:46:30.89$vc4f8/vblo=2,640.99 2006.225.07:46:30.89#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.07:46:30.89#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.07:46:30.89#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:30.89#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:46:30.89#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:46:30.89#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:46:30.89#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:46:30.89#ibcon#first serial, iclass 28, count 0 2006.225.07:46:30.89#ibcon#enter sib2, iclass 28, count 0 2006.225.07:46:30.89#ibcon#flushed, iclass 28, count 0 2006.225.07:46:30.89#ibcon#about to write, iclass 28, count 0 2006.225.07:46:30.89#ibcon#wrote, iclass 28, count 0 2006.225.07:46:30.89#ibcon#about to read 3, iclass 28, count 0 2006.225.07:46:30.91#ibcon#read 3, iclass 28, count 0 2006.225.07:46:30.91#ibcon#about to read 4, iclass 28, count 0 2006.225.07:46:30.91#ibcon#read 4, iclass 28, count 0 2006.225.07:46:30.91#ibcon#about to read 5, iclass 28, count 0 2006.225.07:46:30.91#ibcon#read 5, iclass 28, count 0 2006.225.07:46:30.91#ibcon#about to read 6, iclass 28, count 0 2006.225.07:46:30.91#ibcon#read 6, iclass 28, count 0 2006.225.07:46:30.91#ibcon#end of sib2, iclass 28, count 0 2006.225.07:46:30.91#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:46:30.91#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:46:30.91#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:46:30.91#ibcon#*before write, iclass 28, count 0 2006.225.07:46:30.91#ibcon#enter sib2, iclass 28, count 0 2006.225.07:46:30.91#ibcon#flushed, iclass 28, count 0 2006.225.07:46:30.91#ibcon#about to write, iclass 28, count 0 2006.225.07:46:30.91#ibcon#wrote, iclass 28, count 0 2006.225.07:46:30.91#ibcon#about to read 3, iclass 28, count 0 2006.225.07:46:30.95#ibcon#read 3, iclass 28, count 0 2006.225.07:46:30.95#ibcon#about to read 4, iclass 28, count 0 2006.225.07:46:30.95#ibcon#read 4, iclass 28, count 0 2006.225.07:46:30.95#ibcon#about to read 5, iclass 28, count 0 2006.225.07:46:30.95#ibcon#read 5, iclass 28, count 0 2006.225.07:46:30.95#ibcon#about to read 6, iclass 28, count 0 2006.225.07:46:30.95#ibcon#read 6, iclass 28, count 0 2006.225.07:46:30.95#ibcon#end of sib2, iclass 28, count 0 2006.225.07:46:30.95#ibcon#*after write, iclass 28, count 0 2006.225.07:46:30.95#ibcon#*before return 0, iclass 28, count 0 2006.225.07:46:30.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:46:30.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:46:30.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:46:30.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:46:30.95$vc4f8/vb=2,4 2006.225.07:46:30.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.07:46:30.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.07:46:30.95#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:30.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:46:31.01#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:46:31.01#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:46:31.01#ibcon#enter wrdev, iclass 30, count 2 2006.225.07:46:31.01#ibcon#first serial, iclass 30, count 2 2006.225.07:46:31.01#ibcon#enter sib2, iclass 30, count 2 2006.225.07:46:31.01#ibcon#flushed, iclass 30, count 2 2006.225.07:46:31.01#ibcon#about to write, iclass 30, count 2 2006.225.07:46:31.01#ibcon#wrote, iclass 30, count 2 2006.225.07:46:31.01#ibcon#about to read 3, iclass 30, count 2 2006.225.07:46:31.03#ibcon#read 3, iclass 30, count 2 2006.225.07:46:31.03#ibcon#about to read 4, iclass 30, count 2 2006.225.07:46:31.03#ibcon#read 4, iclass 30, count 2 2006.225.07:46:31.03#ibcon#about to read 5, iclass 30, count 2 2006.225.07:46:31.03#ibcon#read 5, iclass 30, count 2 2006.225.07:46:31.03#ibcon#about to read 6, iclass 30, count 2 2006.225.07:46:31.03#ibcon#read 6, iclass 30, count 2 2006.225.07:46:31.03#ibcon#end of sib2, iclass 30, count 2 2006.225.07:46:31.03#ibcon#*mode == 0, iclass 30, count 2 2006.225.07:46:31.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.07:46:31.03#ibcon#[27=AT02-04\r\n] 2006.225.07:46:31.03#ibcon#*before write, iclass 30, count 2 2006.225.07:46:31.03#ibcon#enter sib2, iclass 30, count 2 2006.225.07:46:31.03#ibcon#flushed, iclass 30, count 2 2006.225.07:46:31.03#ibcon#about to write, iclass 30, count 2 2006.225.07:46:31.03#ibcon#wrote, iclass 30, count 2 2006.225.07:46:31.03#ibcon#about to read 3, iclass 30, count 2 2006.225.07:46:31.06#ibcon#read 3, iclass 30, count 2 2006.225.07:46:31.06#ibcon#about to read 4, iclass 30, count 2 2006.225.07:46:31.06#ibcon#read 4, iclass 30, count 2 2006.225.07:46:31.06#ibcon#about to read 5, iclass 30, count 2 2006.225.07:46:31.06#ibcon#read 5, iclass 30, count 2 2006.225.07:46:31.06#ibcon#about to read 6, iclass 30, count 2 2006.225.07:46:31.06#ibcon#read 6, iclass 30, count 2 2006.225.07:46:31.06#ibcon#end of sib2, iclass 30, count 2 2006.225.07:46:31.06#ibcon#*after write, iclass 30, count 2 2006.225.07:46:31.06#ibcon#*before return 0, iclass 30, count 2 2006.225.07:46:31.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:46:31.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:46:31.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.07:46:31.06#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:31.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:46:31.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:46:31.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:46:31.18#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:46:31.18#ibcon#first serial, iclass 30, count 0 2006.225.07:46:31.18#ibcon#enter sib2, iclass 30, count 0 2006.225.07:46:31.18#ibcon#flushed, iclass 30, count 0 2006.225.07:46:31.18#ibcon#about to write, iclass 30, count 0 2006.225.07:46:31.18#ibcon#wrote, iclass 30, count 0 2006.225.07:46:31.18#ibcon#about to read 3, iclass 30, count 0 2006.225.07:46:31.20#ibcon#read 3, iclass 30, count 0 2006.225.07:46:31.20#ibcon#about to read 4, iclass 30, count 0 2006.225.07:46:31.20#ibcon#read 4, iclass 30, count 0 2006.225.07:46:31.20#ibcon#about to read 5, iclass 30, count 0 2006.225.07:46:31.20#ibcon#read 5, iclass 30, count 0 2006.225.07:46:31.20#ibcon#about to read 6, iclass 30, count 0 2006.225.07:46:31.20#ibcon#read 6, iclass 30, count 0 2006.225.07:46:31.20#ibcon#end of sib2, iclass 30, count 0 2006.225.07:46:31.20#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:46:31.20#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:46:31.20#ibcon#[27=USB\r\n] 2006.225.07:46:31.20#ibcon#*before write, iclass 30, count 0 2006.225.07:46:31.20#ibcon#enter sib2, iclass 30, count 0 2006.225.07:46:31.20#ibcon#flushed, iclass 30, count 0 2006.225.07:46:31.20#ibcon#about to write, iclass 30, count 0 2006.225.07:46:31.20#ibcon#wrote, iclass 30, count 0 2006.225.07:46:31.20#ibcon#about to read 3, iclass 30, count 0 2006.225.07:46:31.23#ibcon#read 3, iclass 30, count 0 2006.225.07:46:31.23#ibcon#about to read 4, iclass 30, count 0 2006.225.07:46:31.23#ibcon#read 4, iclass 30, count 0 2006.225.07:46:31.23#ibcon#about to read 5, iclass 30, count 0 2006.225.07:46:31.23#ibcon#read 5, iclass 30, count 0 2006.225.07:46:31.23#ibcon#about to read 6, iclass 30, count 0 2006.225.07:46:31.23#ibcon#read 6, iclass 30, count 0 2006.225.07:46:31.23#ibcon#end of sib2, iclass 30, count 0 2006.225.07:46:31.23#ibcon#*after write, iclass 30, count 0 2006.225.07:46:31.23#ibcon#*before return 0, iclass 30, count 0 2006.225.07:46:31.23#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:46:31.23#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:46:31.23#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:46:31.23#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:46:31.23$vc4f8/vblo=3,656.99 2006.225.07:46:31.23#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.07:46:31.23#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.07:46:31.23#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:31.23#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:46:31.23#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:46:31.23#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:46:31.23#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:46:31.23#ibcon#first serial, iclass 32, count 0 2006.225.07:46:31.23#ibcon#enter sib2, iclass 32, count 0 2006.225.07:46:31.23#ibcon#flushed, iclass 32, count 0 2006.225.07:46:31.23#ibcon#about to write, iclass 32, count 0 2006.225.07:46:31.23#ibcon#wrote, iclass 32, count 0 2006.225.07:46:31.23#ibcon#about to read 3, iclass 32, count 0 2006.225.07:46:31.25#ibcon#read 3, iclass 32, count 0 2006.225.07:46:31.25#ibcon#about to read 4, iclass 32, count 0 2006.225.07:46:31.25#ibcon#read 4, iclass 32, count 0 2006.225.07:46:31.25#ibcon#about to read 5, iclass 32, count 0 2006.225.07:46:31.25#ibcon#read 5, iclass 32, count 0 2006.225.07:46:31.25#ibcon#about to read 6, iclass 32, count 0 2006.225.07:46:31.25#ibcon#read 6, iclass 32, count 0 2006.225.07:46:31.25#ibcon#end of sib2, iclass 32, count 0 2006.225.07:46:31.25#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:46:31.25#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:46:31.25#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:46:31.25#ibcon#*before write, iclass 32, count 0 2006.225.07:46:31.25#ibcon#enter sib2, iclass 32, count 0 2006.225.07:46:31.25#ibcon#flushed, iclass 32, count 0 2006.225.07:46:31.25#ibcon#about to write, iclass 32, count 0 2006.225.07:46:31.25#ibcon#wrote, iclass 32, count 0 2006.225.07:46:31.25#ibcon#about to read 3, iclass 32, count 0 2006.225.07:46:31.29#ibcon#read 3, iclass 32, count 0 2006.225.07:46:31.29#ibcon#about to read 4, iclass 32, count 0 2006.225.07:46:31.29#ibcon#read 4, iclass 32, count 0 2006.225.07:46:31.29#ibcon#about to read 5, iclass 32, count 0 2006.225.07:46:31.29#ibcon#read 5, iclass 32, count 0 2006.225.07:46:31.29#ibcon#about to read 6, iclass 32, count 0 2006.225.07:46:31.29#ibcon#read 6, iclass 32, count 0 2006.225.07:46:31.29#ibcon#end of sib2, iclass 32, count 0 2006.225.07:46:31.29#ibcon#*after write, iclass 32, count 0 2006.225.07:46:31.29#ibcon#*before return 0, iclass 32, count 0 2006.225.07:46:31.29#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:46:31.29#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:46:31.29#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:46:31.29#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:46:31.29$vc4f8/vb=3,4 2006.225.07:46:31.29#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.07:46:31.29#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.07:46:31.29#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:31.29#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:46:31.35#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:46:31.35#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:46:31.35#ibcon#enter wrdev, iclass 34, count 2 2006.225.07:46:31.35#ibcon#first serial, iclass 34, count 2 2006.225.07:46:31.35#ibcon#enter sib2, iclass 34, count 2 2006.225.07:46:31.35#ibcon#flushed, iclass 34, count 2 2006.225.07:46:31.35#ibcon#about to write, iclass 34, count 2 2006.225.07:46:31.35#ibcon#wrote, iclass 34, count 2 2006.225.07:46:31.35#ibcon#about to read 3, iclass 34, count 2 2006.225.07:46:31.37#ibcon#read 3, iclass 34, count 2 2006.225.07:46:31.37#ibcon#about to read 4, iclass 34, count 2 2006.225.07:46:31.37#ibcon#read 4, iclass 34, count 2 2006.225.07:46:31.37#ibcon#about to read 5, iclass 34, count 2 2006.225.07:46:31.37#ibcon#read 5, iclass 34, count 2 2006.225.07:46:31.37#ibcon#about to read 6, iclass 34, count 2 2006.225.07:46:31.37#ibcon#read 6, iclass 34, count 2 2006.225.07:46:31.37#ibcon#end of sib2, iclass 34, count 2 2006.225.07:46:31.38#ibcon#*mode == 0, iclass 34, count 2 2006.225.07:46:31.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.07:46:31.38#ibcon#[27=AT03-04\r\n] 2006.225.07:46:31.38#ibcon#*before write, iclass 34, count 2 2006.225.07:46:31.38#ibcon#enter sib2, iclass 34, count 2 2006.225.07:46:31.38#ibcon#flushed, iclass 34, count 2 2006.225.07:46:31.38#ibcon#about to write, iclass 34, count 2 2006.225.07:46:31.38#ibcon#wrote, iclass 34, count 2 2006.225.07:46:31.38#ibcon#about to read 3, iclass 34, count 2 2006.225.07:46:31.41#ibcon#read 3, iclass 34, count 2 2006.225.07:46:31.41#ibcon#about to read 4, iclass 34, count 2 2006.225.07:46:31.41#ibcon#read 4, iclass 34, count 2 2006.225.07:46:31.41#ibcon#about to read 5, iclass 34, count 2 2006.225.07:46:31.41#ibcon#read 5, iclass 34, count 2 2006.225.07:46:31.41#ibcon#about to read 6, iclass 34, count 2 2006.225.07:46:31.41#ibcon#read 6, iclass 34, count 2 2006.225.07:46:31.41#ibcon#end of sib2, iclass 34, count 2 2006.225.07:46:31.41#ibcon#*after write, iclass 34, count 2 2006.225.07:46:31.41#ibcon#*before return 0, iclass 34, count 2 2006.225.07:46:31.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:46:31.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:46:31.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.07:46:31.41#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:31.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:46:31.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:46:31.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:46:31.53#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:46:31.53#ibcon#first serial, iclass 34, count 0 2006.225.07:46:31.53#ibcon#enter sib2, iclass 34, count 0 2006.225.07:46:31.53#ibcon#flushed, iclass 34, count 0 2006.225.07:46:31.53#ibcon#about to write, iclass 34, count 0 2006.225.07:46:31.53#ibcon#wrote, iclass 34, count 0 2006.225.07:46:31.53#ibcon#about to read 3, iclass 34, count 0 2006.225.07:46:31.55#ibcon#read 3, iclass 34, count 0 2006.225.07:46:31.55#ibcon#about to read 4, iclass 34, count 0 2006.225.07:46:31.55#ibcon#read 4, iclass 34, count 0 2006.225.07:46:31.55#ibcon#about to read 5, iclass 34, count 0 2006.225.07:46:31.55#ibcon#read 5, iclass 34, count 0 2006.225.07:46:31.55#ibcon#about to read 6, iclass 34, count 0 2006.225.07:46:31.55#ibcon#read 6, iclass 34, count 0 2006.225.07:46:31.55#ibcon#end of sib2, iclass 34, count 0 2006.225.07:46:31.55#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:46:31.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:46:31.55#ibcon#[27=USB\r\n] 2006.225.07:46:31.55#ibcon#*before write, iclass 34, count 0 2006.225.07:46:31.55#ibcon#enter sib2, iclass 34, count 0 2006.225.07:46:31.55#ibcon#flushed, iclass 34, count 0 2006.225.07:46:31.55#ibcon#about to write, iclass 34, count 0 2006.225.07:46:31.55#ibcon#wrote, iclass 34, count 0 2006.225.07:46:31.55#ibcon#about to read 3, iclass 34, count 0 2006.225.07:46:31.58#ibcon#read 3, iclass 34, count 0 2006.225.07:46:31.58#ibcon#about to read 4, iclass 34, count 0 2006.225.07:46:31.58#ibcon#read 4, iclass 34, count 0 2006.225.07:46:31.58#ibcon#about to read 5, iclass 34, count 0 2006.225.07:46:31.58#ibcon#read 5, iclass 34, count 0 2006.225.07:46:31.58#ibcon#about to read 6, iclass 34, count 0 2006.225.07:46:31.58#ibcon#read 6, iclass 34, count 0 2006.225.07:46:31.58#ibcon#end of sib2, iclass 34, count 0 2006.225.07:46:31.58#ibcon#*after write, iclass 34, count 0 2006.225.07:46:31.58#ibcon#*before return 0, iclass 34, count 0 2006.225.07:46:31.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:46:31.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:46:31.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:46:31.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:46:31.58$vc4f8/vblo=4,712.99 2006.225.07:46:31.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.07:46:31.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.07:46:31.58#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:31.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:46:31.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:46:31.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:46:31.58#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:46:31.58#ibcon#first serial, iclass 36, count 0 2006.225.07:46:31.58#ibcon#enter sib2, iclass 36, count 0 2006.225.07:46:31.58#ibcon#flushed, iclass 36, count 0 2006.225.07:46:31.58#ibcon#about to write, iclass 36, count 0 2006.225.07:46:31.58#ibcon#wrote, iclass 36, count 0 2006.225.07:46:31.58#ibcon#about to read 3, iclass 36, count 0 2006.225.07:46:31.60#ibcon#read 3, iclass 36, count 0 2006.225.07:46:31.60#ibcon#about to read 4, iclass 36, count 0 2006.225.07:46:31.60#ibcon#read 4, iclass 36, count 0 2006.225.07:46:31.60#ibcon#about to read 5, iclass 36, count 0 2006.225.07:46:31.60#ibcon#read 5, iclass 36, count 0 2006.225.07:46:31.60#ibcon#about to read 6, iclass 36, count 0 2006.225.07:46:31.60#ibcon#read 6, iclass 36, count 0 2006.225.07:46:31.60#ibcon#end of sib2, iclass 36, count 0 2006.225.07:46:31.60#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:46:31.60#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:46:31.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:46:31.60#ibcon#*before write, iclass 36, count 0 2006.225.07:46:31.60#ibcon#enter sib2, iclass 36, count 0 2006.225.07:46:31.60#ibcon#flushed, iclass 36, count 0 2006.225.07:46:31.60#ibcon#about to write, iclass 36, count 0 2006.225.07:46:31.60#ibcon#wrote, iclass 36, count 0 2006.225.07:46:31.60#ibcon#about to read 3, iclass 36, count 0 2006.225.07:46:31.64#ibcon#read 3, iclass 36, count 0 2006.225.07:46:31.64#ibcon#about to read 4, iclass 36, count 0 2006.225.07:46:31.64#ibcon#read 4, iclass 36, count 0 2006.225.07:46:31.64#ibcon#about to read 5, iclass 36, count 0 2006.225.07:46:31.64#ibcon#read 5, iclass 36, count 0 2006.225.07:46:31.64#ibcon#about to read 6, iclass 36, count 0 2006.225.07:46:31.64#ibcon#read 6, iclass 36, count 0 2006.225.07:46:31.64#ibcon#end of sib2, iclass 36, count 0 2006.225.07:46:31.64#ibcon#*after write, iclass 36, count 0 2006.225.07:46:31.64#ibcon#*before return 0, iclass 36, count 0 2006.225.07:46:31.64#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:46:31.64#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:46:31.64#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:46:31.64#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:46:31.64$vc4f8/vb=4,4 2006.225.07:46:31.64#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.07:46:31.64#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.07:46:31.64#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:31.64#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:46:31.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:46:31.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:46:31.70#ibcon#enter wrdev, iclass 38, count 2 2006.225.07:46:31.70#ibcon#first serial, iclass 38, count 2 2006.225.07:46:31.70#ibcon#enter sib2, iclass 38, count 2 2006.225.07:46:31.70#ibcon#flushed, iclass 38, count 2 2006.225.07:46:31.70#ibcon#about to write, iclass 38, count 2 2006.225.07:46:31.70#ibcon#wrote, iclass 38, count 2 2006.225.07:46:31.70#ibcon#about to read 3, iclass 38, count 2 2006.225.07:46:31.72#ibcon#read 3, iclass 38, count 2 2006.225.07:46:31.72#ibcon#about to read 4, iclass 38, count 2 2006.225.07:46:31.72#ibcon#read 4, iclass 38, count 2 2006.225.07:46:31.72#ibcon#about to read 5, iclass 38, count 2 2006.225.07:46:31.72#ibcon#read 5, iclass 38, count 2 2006.225.07:46:31.72#ibcon#about to read 6, iclass 38, count 2 2006.225.07:46:31.72#ibcon#read 6, iclass 38, count 2 2006.225.07:46:31.72#ibcon#end of sib2, iclass 38, count 2 2006.225.07:46:31.72#ibcon#*mode == 0, iclass 38, count 2 2006.225.07:46:31.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.07:46:31.72#ibcon#[27=AT04-04\r\n] 2006.225.07:46:31.72#ibcon#*before write, iclass 38, count 2 2006.225.07:46:31.72#ibcon#enter sib2, iclass 38, count 2 2006.225.07:46:31.72#ibcon#flushed, iclass 38, count 2 2006.225.07:46:31.72#ibcon#about to write, iclass 38, count 2 2006.225.07:46:31.72#ibcon#wrote, iclass 38, count 2 2006.225.07:46:31.72#ibcon#about to read 3, iclass 38, count 2 2006.225.07:46:31.75#ibcon#read 3, iclass 38, count 2 2006.225.07:46:31.75#ibcon#about to read 4, iclass 38, count 2 2006.225.07:46:31.75#ibcon#read 4, iclass 38, count 2 2006.225.07:46:31.75#ibcon#about to read 5, iclass 38, count 2 2006.225.07:46:31.75#ibcon#read 5, iclass 38, count 2 2006.225.07:46:31.75#ibcon#about to read 6, iclass 38, count 2 2006.225.07:46:31.75#ibcon#read 6, iclass 38, count 2 2006.225.07:46:31.75#ibcon#end of sib2, iclass 38, count 2 2006.225.07:46:31.75#ibcon#*after write, iclass 38, count 2 2006.225.07:46:31.75#ibcon#*before return 0, iclass 38, count 2 2006.225.07:46:31.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:46:31.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:46:31.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.07:46:31.75#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:31.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:46:31.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:46:31.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:46:31.87#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:46:31.87#ibcon#first serial, iclass 38, count 0 2006.225.07:46:31.87#ibcon#enter sib2, iclass 38, count 0 2006.225.07:46:31.87#ibcon#flushed, iclass 38, count 0 2006.225.07:46:31.87#ibcon#about to write, iclass 38, count 0 2006.225.07:46:31.87#ibcon#wrote, iclass 38, count 0 2006.225.07:46:31.87#ibcon#about to read 3, iclass 38, count 0 2006.225.07:46:31.89#ibcon#read 3, iclass 38, count 0 2006.225.07:46:31.89#ibcon#about to read 4, iclass 38, count 0 2006.225.07:46:31.89#ibcon#read 4, iclass 38, count 0 2006.225.07:46:31.89#ibcon#about to read 5, iclass 38, count 0 2006.225.07:46:31.89#ibcon#read 5, iclass 38, count 0 2006.225.07:46:31.89#ibcon#about to read 6, iclass 38, count 0 2006.225.07:46:31.89#ibcon#read 6, iclass 38, count 0 2006.225.07:46:31.89#ibcon#end of sib2, iclass 38, count 0 2006.225.07:46:31.89#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:46:31.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:46:31.89#ibcon#[27=USB\r\n] 2006.225.07:46:31.89#ibcon#*before write, iclass 38, count 0 2006.225.07:46:31.89#ibcon#enter sib2, iclass 38, count 0 2006.225.07:46:31.89#ibcon#flushed, iclass 38, count 0 2006.225.07:46:31.89#ibcon#about to write, iclass 38, count 0 2006.225.07:46:31.89#ibcon#wrote, iclass 38, count 0 2006.225.07:46:31.89#ibcon#about to read 3, iclass 38, count 0 2006.225.07:46:31.92#ibcon#read 3, iclass 38, count 0 2006.225.07:46:31.92#ibcon#about to read 4, iclass 38, count 0 2006.225.07:46:31.92#ibcon#read 4, iclass 38, count 0 2006.225.07:46:31.92#ibcon#about to read 5, iclass 38, count 0 2006.225.07:46:31.92#ibcon#read 5, iclass 38, count 0 2006.225.07:46:31.92#ibcon#about to read 6, iclass 38, count 0 2006.225.07:46:31.92#ibcon#read 6, iclass 38, count 0 2006.225.07:46:31.92#ibcon#end of sib2, iclass 38, count 0 2006.225.07:46:31.92#ibcon#*after write, iclass 38, count 0 2006.225.07:46:31.92#ibcon#*before return 0, iclass 38, count 0 2006.225.07:46:31.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:46:31.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:46:31.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:46:31.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:46:31.92$vc4f8/vblo=5,744.99 2006.225.07:46:31.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.07:46:31.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.07:46:31.92#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:31.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:46:31.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:46:31.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:46:31.92#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:46:31.92#ibcon#first serial, iclass 40, count 0 2006.225.07:46:31.92#ibcon#enter sib2, iclass 40, count 0 2006.225.07:46:31.92#ibcon#flushed, iclass 40, count 0 2006.225.07:46:31.92#ibcon#about to write, iclass 40, count 0 2006.225.07:46:31.92#ibcon#wrote, iclass 40, count 0 2006.225.07:46:31.92#ibcon#about to read 3, iclass 40, count 0 2006.225.07:46:31.94#ibcon#read 3, iclass 40, count 0 2006.225.07:46:31.94#ibcon#about to read 4, iclass 40, count 0 2006.225.07:46:31.94#ibcon#read 4, iclass 40, count 0 2006.225.07:46:31.94#ibcon#about to read 5, iclass 40, count 0 2006.225.07:46:31.94#ibcon#read 5, iclass 40, count 0 2006.225.07:46:31.94#ibcon#about to read 6, iclass 40, count 0 2006.225.07:46:31.94#ibcon#read 6, iclass 40, count 0 2006.225.07:46:31.94#ibcon#end of sib2, iclass 40, count 0 2006.225.07:46:31.94#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:46:31.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:46:31.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:46:31.94#ibcon#*before write, iclass 40, count 0 2006.225.07:46:31.94#ibcon#enter sib2, iclass 40, count 0 2006.225.07:46:31.94#ibcon#flushed, iclass 40, count 0 2006.225.07:46:31.94#ibcon#about to write, iclass 40, count 0 2006.225.07:46:31.94#ibcon#wrote, iclass 40, count 0 2006.225.07:46:31.94#ibcon#about to read 3, iclass 40, count 0 2006.225.07:46:31.98#ibcon#read 3, iclass 40, count 0 2006.225.07:46:31.98#ibcon#about to read 4, iclass 40, count 0 2006.225.07:46:31.98#ibcon#read 4, iclass 40, count 0 2006.225.07:46:31.98#ibcon#about to read 5, iclass 40, count 0 2006.225.07:46:31.98#ibcon#read 5, iclass 40, count 0 2006.225.07:46:31.98#ibcon#about to read 6, iclass 40, count 0 2006.225.07:46:31.98#ibcon#read 6, iclass 40, count 0 2006.225.07:46:31.98#ibcon#end of sib2, iclass 40, count 0 2006.225.07:46:31.98#ibcon#*after write, iclass 40, count 0 2006.225.07:46:31.98#ibcon#*before return 0, iclass 40, count 0 2006.225.07:46:31.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:46:31.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:46:31.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:46:31.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:46:31.98$vc4f8/vb=5,4 2006.225.07:46:31.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.07:46:31.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.07:46:31.98#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:31.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:46:32.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:46:32.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:46:32.04#ibcon#enter wrdev, iclass 4, count 2 2006.225.07:46:32.04#ibcon#first serial, iclass 4, count 2 2006.225.07:46:32.04#ibcon#enter sib2, iclass 4, count 2 2006.225.07:46:32.04#ibcon#flushed, iclass 4, count 2 2006.225.07:46:32.04#ibcon#about to write, iclass 4, count 2 2006.225.07:46:32.04#ibcon#wrote, iclass 4, count 2 2006.225.07:46:32.04#ibcon#about to read 3, iclass 4, count 2 2006.225.07:46:32.06#ibcon#read 3, iclass 4, count 2 2006.225.07:46:32.06#ibcon#about to read 4, iclass 4, count 2 2006.225.07:46:32.06#ibcon#read 4, iclass 4, count 2 2006.225.07:46:32.06#ibcon#about to read 5, iclass 4, count 2 2006.225.07:46:32.06#ibcon#read 5, iclass 4, count 2 2006.225.07:46:32.06#ibcon#about to read 6, iclass 4, count 2 2006.225.07:46:32.06#ibcon#read 6, iclass 4, count 2 2006.225.07:46:32.06#ibcon#end of sib2, iclass 4, count 2 2006.225.07:46:32.06#ibcon#*mode == 0, iclass 4, count 2 2006.225.07:46:32.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.07:46:32.06#ibcon#[27=AT05-04\r\n] 2006.225.07:46:32.06#ibcon#*before write, iclass 4, count 2 2006.225.07:46:32.06#ibcon#enter sib2, iclass 4, count 2 2006.225.07:46:32.06#ibcon#flushed, iclass 4, count 2 2006.225.07:46:32.06#ibcon#about to write, iclass 4, count 2 2006.225.07:46:32.06#ibcon#wrote, iclass 4, count 2 2006.225.07:46:32.06#ibcon#about to read 3, iclass 4, count 2 2006.225.07:46:32.09#ibcon#read 3, iclass 4, count 2 2006.225.07:46:32.09#ibcon#about to read 4, iclass 4, count 2 2006.225.07:46:32.09#ibcon#read 4, iclass 4, count 2 2006.225.07:46:32.09#ibcon#about to read 5, iclass 4, count 2 2006.225.07:46:32.09#ibcon#read 5, iclass 4, count 2 2006.225.07:46:32.09#ibcon#about to read 6, iclass 4, count 2 2006.225.07:46:32.09#ibcon#read 6, iclass 4, count 2 2006.225.07:46:32.09#ibcon#end of sib2, iclass 4, count 2 2006.225.07:46:32.09#ibcon#*after write, iclass 4, count 2 2006.225.07:46:32.09#ibcon#*before return 0, iclass 4, count 2 2006.225.07:46:32.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:46:32.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:46:32.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.07:46:32.09#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:32.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:46:32.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:46:32.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:46:32.21#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:46:32.21#ibcon#first serial, iclass 4, count 0 2006.225.07:46:32.21#ibcon#enter sib2, iclass 4, count 0 2006.225.07:46:32.21#ibcon#flushed, iclass 4, count 0 2006.225.07:46:32.21#ibcon#about to write, iclass 4, count 0 2006.225.07:46:32.21#ibcon#wrote, iclass 4, count 0 2006.225.07:46:32.21#ibcon#about to read 3, iclass 4, count 0 2006.225.07:46:32.23#ibcon#read 3, iclass 4, count 0 2006.225.07:46:32.23#ibcon#about to read 4, iclass 4, count 0 2006.225.07:46:32.23#ibcon#read 4, iclass 4, count 0 2006.225.07:46:32.23#ibcon#about to read 5, iclass 4, count 0 2006.225.07:46:32.23#ibcon#read 5, iclass 4, count 0 2006.225.07:46:32.23#ibcon#about to read 6, iclass 4, count 0 2006.225.07:46:32.23#ibcon#read 6, iclass 4, count 0 2006.225.07:46:32.23#ibcon#end of sib2, iclass 4, count 0 2006.225.07:46:32.23#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:46:32.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:46:32.23#ibcon#[27=USB\r\n] 2006.225.07:46:32.23#ibcon#*before write, iclass 4, count 0 2006.225.07:46:32.23#ibcon#enter sib2, iclass 4, count 0 2006.225.07:46:32.23#ibcon#flushed, iclass 4, count 0 2006.225.07:46:32.23#ibcon#about to write, iclass 4, count 0 2006.225.07:46:32.23#ibcon#wrote, iclass 4, count 0 2006.225.07:46:32.23#ibcon#about to read 3, iclass 4, count 0 2006.225.07:46:32.26#ibcon#read 3, iclass 4, count 0 2006.225.07:46:32.26#ibcon#about to read 4, iclass 4, count 0 2006.225.07:46:32.26#ibcon#read 4, iclass 4, count 0 2006.225.07:46:32.26#ibcon#about to read 5, iclass 4, count 0 2006.225.07:46:32.26#ibcon#read 5, iclass 4, count 0 2006.225.07:46:32.26#ibcon#about to read 6, iclass 4, count 0 2006.225.07:46:32.26#ibcon#read 6, iclass 4, count 0 2006.225.07:46:32.26#ibcon#end of sib2, iclass 4, count 0 2006.225.07:46:32.26#ibcon#*after write, iclass 4, count 0 2006.225.07:46:32.26#ibcon#*before return 0, iclass 4, count 0 2006.225.07:46:32.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:46:32.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:46:32.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:46:32.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:46:32.26$vc4f8/vblo=6,752.99 2006.225.07:46:32.26#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.07:46:32.26#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.07:46:32.26#ibcon#ireg 17 cls_cnt 0 2006.225.07:46:32.26#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:46:32.26#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:46:32.26#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:46:32.26#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:46:32.26#ibcon#first serial, iclass 6, count 0 2006.225.07:46:32.26#ibcon#enter sib2, iclass 6, count 0 2006.225.07:46:32.26#ibcon#flushed, iclass 6, count 0 2006.225.07:46:32.26#ibcon#about to write, iclass 6, count 0 2006.225.07:46:32.26#ibcon#wrote, iclass 6, count 0 2006.225.07:46:32.26#ibcon#about to read 3, iclass 6, count 0 2006.225.07:46:32.28#ibcon#read 3, iclass 6, count 0 2006.225.07:46:32.28#ibcon#about to read 4, iclass 6, count 0 2006.225.07:46:32.28#ibcon#read 4, iclass 6, count 0 2006.225.07:46:32.28#ibcon#about to read 5, iclass 6, count 0 2006.225.07:46:32.28#ibcon#read 5, iclass 6, count 0 2006.225.07:46:32.28#ibcon#about to read 6, iclass 6, count 0 2006.225.07:46:32.28#ibcon#read 6, iclass 6, count 0 2006.225.07:46:32.28#ibcon#end of sib2, iclass 6, count 0 2006.225.07:46:32.28#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:46:32.28#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:46:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:46:32.28#ibcon#*before write, iclass 6, count 0 2006.225.07:46:32.28#ibcon#enter sib2, iclass 6, count 0 2006.225.07:46:32.28#ibcon#flushed, iclass 6, count 0 2006.225.07:46:32.28#ibcon#about to write, iclass 6, count 0 2006.225.07:46:32.28#ibcon#wrote, iclass 6, count 0 2006.225.07:46:32.28#ibcon#about to read 3, iclass 6, count 0 2006.225.07:46:32.32#ibcon#read 3, iclass 6, count 0 2006.225.07:46:32.32#ibcon#about to read 4, iclass 6, count 0 2006.225.07:46:32.32#ibcon#read 4, iclass 6, count 0 2006.225.07:46:32.32#ibcon#about to read 5, iclass 6, count 0 2006.225.07:46:32.32#ibcon#read 5, iclass 6, count 0 2006.225.07:46:32.32#ibcon#about to read 6, iclass 6, count 0 2006.225.07:46:32.32#ibcon#read 6, iclass 6, count 0 2006.225.07:46:32.32#ibcon#end of sib2, iclass 6, count 0 2006.225.07:46:32.32#ibcon#*after write, iclass 6, count 0 2006.225.07:46:32.32#ibcon#*before return 0, iclass 6, count 0 2006.225.07:46:32.32#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:46:32.32#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:46:32.32#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:46:32.32#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:46:32.32$vc4f8/vb=6,4 2006.225.07:46:32.32#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.225.07:46:32.32#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.225.07:46:32.32#ibcon#ireg 11 cls_cnt 2 2006.225.07:46:32.32#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:46:32.38#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:46:32.38#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:46:32.38#ibcon#enter wrdev, iclass 10, count 2 2006.225.07:46:32.38#ibcon#first serial, iclass 10, count 2 2006.225.07:46:32.38#ibcon#enter sib2, iclass 10, count 2 2006.225.07:46:32.38#ibcon#flushed, iclass 10, count 2 2006.225.07:46:32.38#ibcon#about to write, iclass 10, count 2 2006.225.07:46:32.38#ibcon#wrote, iclass 10, count 2 2006.225.07:46:32.38#ibcon#about to read 3, iclass 10, count 2 2006.225.07:46:32.40#ibcon#read 3, iclass 10, count 2 2006.225.07:46:32.40#ibcon#about to read 4, iclass 10, count 2 2006.225.07:46:32.40#ibcon#read 4, iclass 10, count 2 2006.225.07:46:32.40#ibcon#about to read 5, iclass 10, count 2 2006.225.07:46:32.40#ibcon#read 5, iclass 10, count 2 2006.225.07:46:32.40#ibcon#about to read 6, iclass 10, count 2 2006.225.07:46:32.40#ibcon#read 6, iclass 10, count 2 2006.225.07:46:32.40#ibcon#end of sib2, iclass 10, count 2 2006.225.07:46:32.40#ibcon#*mode == 0, iclass 10, count 2 2006.225.07:46:32.40#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.225.07:46:32.40#ibcon#[27=AT06-04\r\n] 2006.225.07:46:32.40#ibcon#*before write, iclass 10, count 2 2006.225.07:46:32.40#ibcon#enter sib2, iclass 10, count 2 2006.225.07:46:32.40#ibcon#flushed, iclass 10, count 2 2006.225.07:46:32.40#ibcon#about to write, iclass 10, count 2 2006.225.07:46:32.40#ibcon#wrote, iclass 10, count 2 2006.225.07:46:32.40#ibcon#about to read 3, iclass 10, count 2 2006.225.07:46:32.43#ibcon#read 3, iclass 10, count 2 2006.225.07:46:32.43#ibcon#about to read 4, iclass 10, count 2 2006.225.07:46:32.43#ibcon#read 4, iclass 10, count 2 2006.225.07:46:32.43#ibcon#about to read 5, iclass 10, count 2 2006.225.07:46:32.43#ibcon#read 5, iclass 10, count 2 2006.225.07:46:32.43#ibcon#about to read 6, iclass 10, count 2 2006.225.07:46:32.43#ibcon#read 6, iclass 10, count 2 2006.225.07:46:32.43#ibcon#end of sib2, iclass 10, count 2 2006.225.07:46:32.43#ibcon#*after write, iclass 10, count 2 2006.225.07:46:32.43#ibcon#*before return 0, iclass 10, count 2 2006.225.07:46:32.43#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:46:32.43#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:46:32.43#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.225.07:46:32.43#ibcon#ireg 7 cls_cnt 0 2006.225.07:46:32.43#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:46:32.55#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:46:32.55#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:46:32.55#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:46:32.55#ibcon#first serial, iclass 10, count 0 2006.225.07:46:32.55#ibcon#enter sib2, iclass 10, count 0 2006.225.07:46:32.55#ibcon#flushed, iclass 10, count 0 2006.225.07:46:32.55#ibcon#about to write, iclass 10, count 0 2006.225.07:46:32.55#ibcon#wrote, iclass 10, count 0 2006.225.07:46:32.55#ibcon#about to read 3, iclass 10, count 0 2006.225.07:46:32.57#ibcon#read 3, iclass 10, count 0 2006.225.07:46:32.57#ibcon#about to read 4, iclass 10, count 0 2006.225.07:46:32.57#ibcon#read 4, iclass 10, count 0 2006.225.07:46:32.57#ibcon#about to read 5, iclass 10, count 0 2006.225.07:46:32.57#ibcon#read 5, iclass 10, count 0 2006.225.07:46:32.57#ibcon#about to read 6, iclass 10, count 0 2006.225.07:46:32.57#ibcon#read 6, iclass 10, count 0 2006.225.07:46:32.57#ibcon#end of sib2, iclass 10, count 0 2006.225.07:46:32.57#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:46:32.57#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:46:32.57#ibcon#[27=USB\r\n] 2006.225.07:46:32.57#ibcon#*before write, iclass 10, count 0 2006.225.07:46:32.57#ibcon#enter sib2, iclass 10, count 0 2006.225.07:46:32.57#ibcon#flushed, iclass 10, count 0 2006.225.07:46:32.57#ibcon#about to write, iclass 10, count 0 2006.225.07:46:32.57#ibcon#wrote, iclass 10, count 0 2006.225.07:46:32.57#ibcon#about to read 3, iclass 10, count 0 2006.225.07:46:32.60#ibcon#read 3, iclass 10, count 0 2006.225.07:46:32.60#ibcon#about to read 4, iclass 10, count 0 2006.225.07:46:32.60#ibcon#read 4, iclass 10, count 0 2006.225.07:46:32.60#ibcon#about to read 5, iclass 10, count 0 2006.225.07:46:32.60#ibcon#read 5, iclass 10, count 0 2006.225.07:46:32.60#ibcon#about to read 6, iclass 10, count 0 2006.225.07:46:32.60#ibcon#read 6, iclass 10, count 0 2006.225.07:46:32.60#ibcon#end of sib2, iclass 10, count 0 2006.225.07:46:32.60#ibcon#*after write, iclass 10, count 0 2006.225.07:46:32.60#ibcon#*before return 0, iclass 10, count 0 2006.225.07:46:32.60#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:46:32.60#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:46:32.60#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:46:32.60#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:46:32.60$vc4f8/vabw=wide 2006.225.07:46:32.60#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.07:46:32.60#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.07:46:32.60#ibcon#ireg 8 cls_cnt 0 2006.225.07:46:32.60#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:46:32.60#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:46:32.60#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:46:32.60#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:46:32.60#ibcon#first serial, iclass 12, count 0 2006.225.07:46:32.60#ibcon#enter sib2, iclass 12, count 0 2006.225.07:46:32.60#ibcon#flushed, iclass 12, count 0 2006.225.07:46:32.60#ibcon#about to write, iclass 12, count 0 2006.225.07:46:32.60#ibcon#wrote, iclass 12, count 0 2006.225.07:46:32.60#ibcon#about to read 3, iclass 12, count 0 2006.225.07:46:32.62#ibcon#read 3, iclass 12, count 0 2006.225.07:46:32.62#ibcon#about to read 4, iclass 12, count 0 2006.225.07:46:32.62#ibcon#read 4, iclass 12, count 0 2006.225.07:46:32.62#ibcon#about to read 5, iclass 12, count 0 2006.225.07:46:32.62#ibcon#read 5, iclass 12, count 0 2006.225.07:46:32.62#ibcon#about to read 6, iclass 12, count 0 2006.225.07:46:32.62#ibcon#read 6, iclass 12, count 0 2006.225.07:46:32.62#ibcon#end of sib2, iclass 12, count 0 2006.225.07:46:32.62#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:46:32.62#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:46:32.62#ibcon#[25=BW32\r\n] 2006.225.07:46:32.62#ibcon#*before write, iclass 12, count 0 2006.225.07:46:32.62#ibcon#enter sib2, iclass 12, count 0 2006.225.07:46:32.62#ibcon#flushed, iclass 12, count 0 2006.225.07:46:32.62#ibcon#about to write, iclass 12, count 0 2006.225.07:46:32.62#ibcon#wrote, iclass 12, count 0 2006.225.07:46:32.62#ibcon#about to read 3, iclass 12, count 0 2006.225.07:46:32.65#ibcon#read 3, iclass 12, count 0 2006.225.07:46:32.65#ibcon#about to read 4, iclass 12, count 0 2006.225.07:46:32.65#ibcon#read 4, iclass 12, count 0 2006.225.07:46:32.65#ibcon#about to read 5, iclass 12, count 0 2006.225.07:46:32.65#ibcon#read 5, iclass 12, count 0 2006.225.07:46:32.65#ibcon#about to read 6, iclass 12, count 0 2006.225.07:46:32.65#ibcon#read 6, iclass 12, count 0 2006.225.07:46:32.65#ibcon#end of sib2, iclass 12, count 0 2006.225.07:46:32.65#ibcon#*after write, iclass 12, count 0 2006.225.07:46:32.65#ibcon#*before return 0, iclass 12, count 0 2006.225.07:46:32.65#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:46:32.65#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:46:32.65#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:46:32.65#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:46:32.65$vc4f8/vbbw=wide 2006.225.07:46:32.65#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.07:46:32.65#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.07:46:32.65#ibcon#ireg 8 cls_cnt 0 2006.225.07:46:32.65#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:46:32.72#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:46:32.72#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:46:32.72#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:46:32.72#ibcon#first serial, iclass 14, count 0 2006.225.07:46:32.72#ibcon#enter sib2, iclass 14, count 0 2006.225.07:46:32.72#ibcon#flushed, iclass 14, count 0 2006.225.07:46:32.72#ibcon#about to write, iclass 14, count 0 2006.225.07:46:32.72#ibcon#wrote, iclass 14, count 0 2006.225.07:46:32.72#ibcon#about to read 3, iclass 14, count 0 2006.225.07:46:32.74#ibcon#read 3, iclass 14, count 0 2006.225.07:46:32.74#ibcon#about to read 4, iclass 14, count 0 2006.225.07:46:32.74#ibcon#read 4, iclass 14, count 0 2006.225.07:46:32.74#ibcon#about to read 5, iclass 14, count 0 2006.225.07:46:32.74#ibcon#read 5, iclass 14, count 0 2006.225.07:46:32.74#ibcon#about to read 6, iclass 14, count 0 2006.225.07:46:32.74#ibcon#read 6, iclass 14, count 0 2006.225.07:46:32.74#ibcon#end of sib2, iclass 14, count 0 2006.225.07:46:32.74#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:46:32.74#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:46:32.74#ibcon#[27=BW32\r\n] 2006.225.07:46:32.74#ibcon#*before write, iclass 14, count 0 2006.225.07:46:32.74#ibcon#enter sib2, iclass 14, count 0 2006.225.07:46:32.74#ibcon#flushed, iclass 14, count 0 2006.225.07:46:32.74#ibcon#about to write, iclass 14, count 0 2006.225.07:46:32.74#ibcon#wrote, iclass 14, count 0 2006.225.07:46:32.74#ibcon#about to read 3, iclass 14, count 0 2006.225.07:46:32.77#ibcon#read 3, iclass 14, count 0 2006.225.07:46:32.77#ibcon#about to read 4, iclass 14, count 0 2006.225.07:46:32.77#ibcon#read 4, iclass 14, count 0 2006.225.07:46:32.77#ibcon#about to read 5, iclass 14, count 0 2006.225.07:46:32.77#ibcon#read 5, iclass 14, count 0 2006.225.07:46:32.77#ibcon#about to read 6, iclass 14, count 0 2006.225.07:46:32.77#ibcon#read 6, iclass 14, count 0 2006.225.07:46:32.77#ibcon#end of sib2, iclass 14, count 0 2006.225.07:46:32.77#ibcon#*after write, iclass 14, count 0 2006.225.07:46:32.77#ibcon#*before return 0, iclass 14, count 0 2006.225.07:46:32.77#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:46:32.77#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:46:32.77#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:46:32.77#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:46:32.77$4f8m12a/ifd4f 2006.225.07:46:32.77$ifd4f/lo= 2006.225.07:46:32.77$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:46:32.77$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:46:32.77$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:46:32.77$ifd4f/patch= 2006.225.07:46:32.77$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:46:32.77$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:46:32.77$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:46:32.77$4f8m12a/"form=m,16.000,1:2 2006.225.07:46:32.77$4f8m12a/"tpicd 2006.225.07:46:32.77$4f8m12a/echo=off 2006.225.07:46:32.77$4f8m12a/xlog=off 2006.225.07:46:32.77:!2006.225.07:47:00 2006.225.07:46:45.14#trakl#Source acquired 2006.225.07:46:45.14#flagr#flagr/antenna,acquired 2006.225.07:47:00.00:preob 2006.225.07:47:01.14/onsource/TRACKING 2006.225.07:47:01.14:!2006.225.07:47:10 2006.225.07:47:10.00:data_valid=on 2006.225.07:47:10.00:midob 2006.225.07:47:10.14/onsource/TRACKING 2006.225.07:47:10.14/wx/28.13,1003.4,71 2006.225.07:47:10.21/cable/+6.4049E-03 2006.225.07:47:11.30/va/01,08,usb,yes,28,30 2006.225.07:47:11.30/va/02,07,usb,yes,28,30 2006.225.07:47:11.30/va/03,06,usb,yes,30,30 2006.225.07:47:11.30/va/04,07,usb,yes,29,32 2006.225.07:47:11.30/va/05,07,usb,yes,32,34 2006.225.07:47:11.30/va/06,06,usb,yes,31,31 2006.225.07:47:11.30/va/07,06,usb,yes,32,31 2006.225.07:47:11.30/va/08,07,usb,yes,30,29 2006.225.07:47:11.53/valo/01,532.99,yes,locked 2006.225.07:47:11.53/valo/02,572.99,yes,locked 2006.225.07:47:11.53/valo/03,672.99,yes,locked 2006.225.07:47:11.53/valo/04,832.99,yes,locked 2006.225.07:47:11.53/valo/05,652.99,yes,locked 2006.225.07:47:11.53/valo/06,772.99,yes,locked 2006.225.07:47:11.53/valo/07,832.99,yes,locked 2006.225.07:47:11.53/valo/08,852.99,yes,locked 2006.225.07:47:12.62/vb/01,04,usb,yes,30,29 2006.225.07:47:12.62/vb/02,04,usb,yes,32,33 2006.225.07:47:12.62/vb/03,04,usb,yes,28,32 2006.225.07:47:12.62/vb/04,04,usb,yes,29,29 2006.225.07:47:12.62/vb/05,04,usb,yes,28,32 2006.225.07:47:12.62/vb/06,04,usb,yes,29,31 2006.225.07:47:12.62/vb/07,04,usb,yes,31,31 2006.225.07:47:12.62/vb/08,04,usb,yes,28,32 2006.225.07:47:12.86/vblo/01,632.99,yes,locked 2006.225.07:47:12.86/vblo/02,640.99,yes,locked 2006.225.07:47:12.86/vblo/03,656.99,yes,locked 2006.225.07:47:12.86/vblo/04,712.99,yes,locked 2006.225.07:47:12.86/vblo/05,744.99,yes,locked 2006.225.07:47:12.86/vblo/06,752.99,yes,locked 2006.225.07:47:12.86/vblo/07,734.99,yes,locked 2006.225.07:47:12.86/vblo/08,744.99,yes,locked 2006.225.07:47:13.01/vabw/8 2006.225.07:47:13.16/vbbw/8 2006.225.07:47:13.25/xfe/off,on,15.2 2006.225.07:47:13.62/ifatt/23,28,28,28 2006.225.07:47:14.07/fmout-gps/S +4.51E-07 2006.225.07:47:14.11:!2006.225.07:48:10 2006.225.07:48:10.00:data_valid=off 2006.225.07:48:10.00:postob 2006.225.07:48:10.13/cable/+6.4056E-03 2006.225.07:48:10.13/wx/28.17,1003.4,70 2006.225.07:48:11.07/fmout-gps/S +4.51E-07 2006.225.07:48:11.07:scan_name=225-0749,k06225,60 2006.225.07:48:11.08:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.225.07:48:11.14#flagr#flagr/antenna,new-source 2006.225.07:48:12.14:checkk5 2006.225.07:48:12.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:48:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:48:13.26/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:48:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:48:13.99/chk_obsdata//k5ts1/T2250747??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:48:14.37/chk_obsdata//k5ts2/T2250747??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:48:14.74/chk_obsdata//k5ts3/T2250747??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:48:15.11/chk_obsdata//k5ts4/T2250747??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:48:15.79/k5log//k5ts1_log_newline 2006.225.07:48:16.47/k5log//k5ts2_log_newline 2006.225.07:48:17.16/k5log//k5ts3_log_newline 2006.225.07:48:17.84/k5log//k5ts4_log_newline 2006.225.07:48:17.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:48:17.87:4f8m12a=1 2006.225.07:48:17.87$4f8m12a/echo=on 2006.225.07:48:17.87$4f8m12a/pcalon 2006.225.07:48:17.87$pcalon/"no phase cal control is implemented here 2006.225.07:48:17.87$4f8m12a/"tpicd=stop 2006.225.07:48:17.87$4f8m12a/vc4f8 2006.225.07:48:17.87$vc4f8/valo=1,532.99 2006.225.07:48:17.87#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.225.07:48:17.87#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.225.07:48:17.87#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:17.87#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:48:17.87#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:48:17.87#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:48:17.87#ibcon#enter wrdev, iclass 21, count 0 2006.225.07:48:17.87#ibcon#first serial, iclass 21, count 0 2006.225.07:48:17.87#ibcon#enter sib2, iclass 21, count 0 2006.225.07:48:17.87#ibcon#flushed, iclass 21, count 0 2006.225.07:48:17.87#ibcon#about to write, iclass 21, count 0 2006.225.07:48:17.87#ibcon#wrote, iclass 21, count 0 2006.225.07:48:17.87#ibcon#about to read 3, iclass 21, count 0 2006.225.07:48:17.91#ibcon#read 3, iclass 21, count 0 2006.225.07:48:17.91#ibcon#about to read 4, iclass 21, count 0 2006.225.07:48:17.91#ibcon#read 4, iclass 21, count 0 2006.225.07:48:17.91#ibcon#about to read 5, iclass 21, count 0 2006.225.07:48:17.91#ibcon#read 5, iclass 21, count 0 2006.225.07:48:17.91#ibcon#about to read 6, iclass 21, count 0 2006.225.07:48:17.91#ibcon#read 6, iclass 21, count 0 2006.225.07:48:17.91#ibcon#end of sib2, iclass 21, count 0 2006.225.07:48:17.91#ibcon#*mode == 0, iclass 21, count 0 2006.225.07:48:17.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.07:48:17.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:48:17.91#ibcon#*before write, iclass 21, count 0 2006.225.07:48:17.91#ibcon#enter sib2, iclass 21, count 0 2006.225.07:48:17.91#ibcon#flushed, iclass 21, count 0 2006.225.07:48:17.91#ibcon#about to write, iclass 21, count 0 2006.225.07:48:17.91#ibcon#wrote, iclass 21, count 0 2006.225.07:48:17.91#ibcon#about to read 3, iclass 21, count 0 2006.225.07:48:17.96#ibcon#read 3, iclass 21, count 0 2006.225.07:48:17.96#ibcon#about to read 4, iclass 21, count 0 2006.225.07:48:17.96#ibcon#read 4, iclass 21, count 0 2006.225.07:48:17.96#ibcon#about to read 5, iclass 21, count 0 2006.225.07:48:17.96#ibcon#read 5, iclass 21, count 0 2006.225.07:48:17.96#ibcon#about to read 6, iclass 21, count 0 2006.225.07:48:17.96#ibcon#read 6, iclass 21, count 0 2006.225.07:48:17.96#ibcon#end of sib2, iclass 21, count 0 2006.225.07:48:17.96#ibcon#*after write, iclass 21, count 0 2006.225.07:48:17.96#ibcon#*before return 0, iclass 21, count 0 2006.225.07:48:17.96#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:48:17.96#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:48:17.96#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.07:48:17.96#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.07:48:17.96$vc4f8/va=1,8 2006.225.07:48:17.96#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.225.07:48:17.96#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.225.07:48:17.96#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:17.96#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:48:17.96#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:48:17.96#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:48:17.96#ibcon#enter wrdev, iclass 23, count 2 2006.225.07:48:17.96#ibcon#first serial, iclass 23, count 2 2006.225.07:48:17.96#ibcon#enter sib2, iclass 23, count 2 2006.225.07:48:17.96#ibcon#flushed, iclass 23, count 2 2006.225.07:48:17.96#ibcon#about to write, iclass 23, count 2 2006.225.07:48:17.96#ibcon#wrote, iclass 23, count 2 2006.225.07:48:17.96#ibcon#about to read 3, iclass 23, count 2 2006.225.07:48:17.99#ibcon#read 3, iclass 23, count 2 2006.225.07:48:17.99#ibcon#about to read 4, iclass 23, count 2 2006.225.07:48:17.99#ibcon#read 4, iclass 23, count 2 2006.225.07:48:17.99#ibcon#about to read 5, iclass 23, count 2 2006.225.07:48:17.99#ibcon#read 5, iclass 23, count 2 2006.225.07:48:17.99#ibcon#about to read 6, iclass 23, count 2 2006.225.07:48:17.99#ibcon#read 6, iclass 23, count 2 2006.225.07:48:17.99#ibcon#end of sib2, iclass 23, count 2 2006.225.07:48:17.99#ibcon#*mode == 0, iclass 23, count 2 2006.225.07:48:17.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.225.07:48:17.99#ibcon#[25=AT01-08\r\n] 2006.225.07:48:17.99#ibcon#*before write, iclass 23, count 2 2006.225.07:48:17.99#ibcon#enter sib2, iclass 23, count 2 2006.225.07:48:17.99#ibcon#flushed, iclass 23, count 2 2006.225.07:48:17.99#ibcon#about to write, iclass 23, count 2 2006.225.07:48:17.99#ibcon#wrote, iclass 23, count 2 2006.225.07:48:17.99#ibcon#about to read 3, iclass 23, count 2 2006.225.07:48:18.02#ibcon#read 3, iclass 23, count 2 2006.225.07:48:18.02#ibcon#about to read 4, iclass 23, count 2 2006.225.07:48:18.02#ibcon#read 4, iclass 23, count 2 2006.225.07:48:18.02#ibcon#about to read 5, iclass 23, count 2 2006.225.07:48:18.02#ibcon#read 5, iclass 23, count 2 2006.225.07:48:18.02#ibcon#about to read 6, iclass 23, count 2 2006.225.07:48:18.02#ibcon#read 6, iclass 23, count 2 2006.225.07:48:18.02#ibcon#end of sib2, iclass 23, count 2 2006.225.07:48:18.02#ibcon#*after write, iclass 23, count 2 2006.225.07:48:18.02#ibcon#*before return 0, iclass 23, count 2 2006.225.07:48:18.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:48:18.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:48:18.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.225.07:48:18.02#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:18.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:48:18.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:48:18.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:48:18.14#ibcon#enter wrdev, iclass 23, count 0 2006.225.07:48:18.14#ibcon#first serial, iclass 23, count 0 2006.225.07:48:18.14#ibcon#enter sib2, iclass 23, count 0 2006.225.07:48:18.14#ibcon#flushed, iclass 23, count 0 2006.225.07:48:18.14#ibcon#about to write, iclass 23, count 0 2006.225.07:48:18.14#ibcon#wrote, iclass 23, count 0 2006.225.07:48:18.14#ibcon#about to read 3, iclass 23, count 0 2006.225.07:48:18.16#ibcon#read 3, iclass 23, count 0 2006.225.07:48:18.16#ibcon#about to read 4, iclass 23, count 0 2006.225.07:48:18.16#ibcon#read 4, iclass 23, count 0 2006.225.07:48:18.16#ibcon#about to read 5, iclass 23, count 0 2006.225.07:48:18.16#ibcon#read 5, iclass 23, count 0 2006.225.07:48:18.16#ibcon#about to read 6, iclass 23, count 0 2006.225.07:48:18.16#ibcon#read 6, iclass 23, count 0 2006.225.07:48:18.16#ibcon#end of sib2, iclass 23, count 0 2006.225.07:48:18.16#ibcon#*mode == 0, iclass 23, count 0 2006.225.07:48:18.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.07:48:18.16#ibcon#[25=USB\r\n] 2006.225.07:48:18.16#ibcon#*before write, iclass 23, count 0 2006.225.07:48:18.16#ibcon#enter sib2, iclass 23, count 0 2006.225.07:48:18.16#ibcon#flushed, iclass 23, count 0 2006.225.07:48:18.16#ibcon#about to write, iclass 23, count 0 2006.225.07:48:18.16#ibcon#wrote, iclass 23, count 0 2006.225.07:48:18.16#ibcon#about to read 3, iclass 23, count 0 2006.225.07:48:18.19#ibcon#read 3, iclass 23, count 0 2006.225.07:48:18.19#ibcon#about to read 4, iclass 23, count 0 2006.225.07:48:18.19#ibcon#read 4, iclass 23, count 0 2006.225.07:48:18.19#ibcon#about to read 5, iclass 23, count 0 2006.225.07:48:18.19#ibcon#read 5, iclass 23, count 0 2006.225.07:48:18.19#ibcon#about to read 6, iclass 23, count 0 2006.225.07:48:18.19#ibcon#read 6, iclass 23, count 0 2006.225.07:48:18.19#ibcon#end of sib2, iclass 23, count 0 2006.225.07:48:18.19#ibcon#*after write, iclass 23, count 0 2006.225.07:48:18.19#ibcon#*before return 0, iclass 23, count 0 2006.225.07:48:18.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:48:18.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:48:18.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.07:48:18.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.07:48:18.19$vc4f8/valo=2,572.99 2006.225.07:48:18.19#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.225.07:48:18.19#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.225.07:48:18.19#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:18.19#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:48:18.19#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:48:18.19#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:48:18.19#ibcon#enter wrdev, iclass 25, count 0 2006.225.07:48:18.19#ibcon#first serial, iclass 25, count 0 2006.225.07:48:18.19#ibcon#enter sib2, iclass 25, count 0 2006.225.07:48:18.19#ibcon#flushed, iclass 25, count 0 2006.225.07:48:18.19#ibcon#about to write, iclass 25, count 0 2006.225.07:48:18.19#ibcon#wrote, iclass 25, count 0 2006.225.07:48:18.19#ibcon#about to read 3, iclass 25, count 0 2006.225.07:48:18.22#ibcon#read 3, iclass 25, count 0 2006.225.07:48:18.22#ibcon#about to read 4, iclass 25, count 0 2006.225.07:48:18.22#ibcon#read 4, iclass 25, count 0 2006.225.07:48:18.22#ibcon#about to read 5, iclass 25, count 0 2006.225.07:48:18.22#ibcon#read 5, iclass 25, count 0 2006.225.07:48:18.22#ibcon#about to read 6, iclass 25, count 0 2006.225.07:48:18.22#ibcon#read 6, iclass 25, count 0 2006.225.07:48:18.22#ibcon#end of sib2, iclass 25, count 0 2006.225.07:48:18.22#ibcon#*mode == 0, iclass 25, count 0 2006.225.07:48:18.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.07:48:18.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:48:18.22#ibcon#*before write, iclass 25, count 0 2006.225.07:48:18.22#ibcon#enter sib2, iclass 25, count 0 2006.225.07:48:18.22#ibcon#flushed, iclass 25, count 0 2006.225.07:48:18.22#ibcon#about to write, iclass 25, count 0 2006.225.07:48:18.22#ibcon#wrote, iclass 25, count 0 2006.225.07:48:18.22#ibcon#about to read 3, iclass 25, count 0 2006.225.07:48:18.26#ibcon#read 3, iclass 25, count 0 2006.225.07:48:18.26#ibcon#about to read 4, iclass 25, count 0 2006.225.07:48:18.26#ibcon#read 4, iclass 25, count 0 2006.225.07:48:18.26#ibcon#about to read 5, iclass 25, count 0 2006.225.07:48:18.26#ibcon#read 5, iclass 25, count 0 2006.225.07:48:18.26#ibcon#about to read 6, iclass 25, count 0 2006.225.07:48:18.26#ibcon#read 6, iclass 25, count 0 2006.225.07:48:18.26#ibcon#end of sib2, iclass 25, count 0 2006.225.07:48:18.26#ibcon#*after write, iclass 25, count 0 2006.225.07:48:18.26#ibcon#*before return 0, iclass 25, count 0 2006.225.07:48:18.26#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:48:18.26#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.225.07:48:18.26#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.07:48:18.26#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.07:48:18.26$vc4f8/va=2,7 2006.225.07:48:18.26#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.225.07:48:18.26#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.225.07:48:18.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:18.26#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:48:18.31#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:48:18.31#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:48:18.31#ibcon#enter wrdev, iclass 27, count 2 2006.225.07:48:18.31#ibcon#first serial, iclass 27, count 2 2006.225.07:48:18.31#ibcon#enter sib2, iclass 27, count 2 2006.225.07:48:18.31#ibcon#flushed, iclass 27, count 2 2006.225.07:48:18.31#ibcon#about to write, iclass 27, count 2 2006.225.07:48:18.31#ibcon#wrote, iclass 27, count 2 2006.225.07:48:18.31#ibcon#about to read 3, iclass 27, count 2 2006.225.07:48:18.33#ibcon#read 3, iclass 27, count 2 2006.225.07:48:18.33#ibcon#about to read 4, iclass 27, count 2 2006.225.07:48:18.33#ibcon#read 4, iclass 27, count 2 2006.225.07:48:18.33#ibcon#about to read 5, iclass 27, count 2 2006.225.07:48:18.33#ibcon#read 5, iclass 27, count 2 2006.225.07:48:18.33#ibcon#about to read 6, iclass 27, count 2 2006.225.07:48:18.33#ibcon#read 6, iclass 27, count 2 2006.225.07:48:18.33#ibcon#end of sib2, iclass 27, count 2 2006.225.07:48:18.33#ibcon#*mode == 0, iclass 27, count 2 2006.225.07:48:18.33#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.225.07:48:18.33#ibcon#[25=AT02-07\r\n] 2006.225.07:48:18.33#ibcon#*before write, iclass 27, count 2 2006.225.07:48:18.33#ibcon#enter sib2, iclass 27, count 2 2006.225.07:48:18.33#ibcon#flushed, iclass 27, count 2 2006.225.07:48:18.33#ibcon#about to write, iclass 27, count 2 2006.225.07:48:18.33#ibcon#wrote, iclass 27, count 2 2006.225.07:48:18.33#ibcon#about to read 3, iclass 27, count 2 2006.225.07:48:18.36#ibcon#read 3, iclass 27, count 2 2006.225.07:48:18.36#ibcon#about to read 4, iclass 27, count 2 2006.225.07:48:18.36#ibcon#read 4, iclass 27, count 2 2006.225.07:48:18.36#ibcon#about to read 5, iclass 27, count 2 2006.225.07:48:18.36#ibcon#read 5, iclass 27, count 2 2006.225.07:48:18.36#ibcon#about to read 6, iclass 27, count 2 2006.225.07:48:18.36#ibcon#read 6, iclass 27, count 2 2006.225.07:48:18.36#ibcon#end of sib2, iclass 27, count 2 2006.225.07:48:18.36#ibcon#*after write, iclass 27, count 2 2006.225.07:48:18.36#ibcon#*before return 0, iclass 27, count 2 2006.225.07:48:18.36#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:48:18.36#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.225.07:48:18.36#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.225.07:48:18.36#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:18.36#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:48:18.48#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:48:18.48#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:48:18.48#ibcon#enter wrdev, iclass 27, count 0 2006.225.07:48:18.48#ibcon#first serial, iclass 27, count 0 2006.225.07:48:18.48#ibcon#enter sib2, iclass 27, count 0 2006.225.07:48:18.48#ibcon#flushed, iclass 27, count 0 2006.225.07:48:18.48#ibcon#about to write, iclass 27, count 0 2006.225.07:48:18.48#ibcon#wrote, iclass 27, count 0 2006.225.07:48:18.48#ibcon#about to read 3, iclass 27, count 0 2006.225.07:48:18.50#ibcon#read 3, iclass 27, count 0 2006.225.07:48:18.50#ibcon#about to read 4, iclass 27, count 0 2006.225.07:48:18.50#ibcon#read 4, iclass 27, count 0 2006.225.07:48:18.50#ibcon#about to read 5, iclass 27, count 0 2006.225.07:48:18.50#ibcon#read 5, iclass 27, count 0 2006.225.07:48:18.50#ibcon#about to read 6, iclass 27, count 0 2006.225.07:48:18.50#ibcon#read 6, iclass 27, count 0 2006.225.07:48:18.50#ibcon#end of sib2, iclass 27, count 0 2006.225.07:48:18.50#ibcon#*mode == 0, iclass 27, count 0 2006.225.07:48:18.50#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.07:48:18.50#ibcon#[25=USB\r\n] 2006.225.07:48:18.50#ibcon#*before write, iclass 27, count 0 2006.225.07:48:18.50#ibcon#enter sib2, iclass 27, count 0 2006.225.07:48:18.50#ibcon#flushed, iclass 27, count 0 2006.225.07:48:18.50#ibcon#about to write, iclass 27, count 0 2006.225.07:48:18.50#ibcon#wrote, iclass 27, count 0 2006.225.07:48:18.50#ibcon#about to read 3, iclass 27, count 0 2006.225.07:48:18.53#ibcon#read 3, iclass 27, count 0 2006.225.07:48:18.53#ibcon#about to read 4, iclass 27, count 0 2006.225.07:48:18.53#ibcon#read 4, iclass 27, count 0 2006.225.07:48:18.53#ibcon#about to read 5, iclass 27, count 0 2006.225.07:48:18.53#ibcon#read 5, iclass 27, count 0 2006.225.07:48:18.53#ibcon#about to read 6, iclass 27, count 0 2006.225.07:48:18.53#ibcon#read 6, iclass 27, count 0 2006.225.07:48:18.53#ibcon#end of sib2, iclass 27, count 0 2006.225.07:48:18.53#ibcon#*after write, iclass 27, count 0 2006.225.07:48:18.53#ibcon#*before return 0, iclass 27, count 0 2006.225.07:48:18.53#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:48:18.53#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.225.07:48:18.53#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.07:48:18.53#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.07:48:18.53$vc4f8/valo=3,672.99 2006.225.07:48:18.53#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.07:48:18.53#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.07:48:18.53#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:18.53#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:48:18.53#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:48:18.53#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:48:18.53#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:48:18.53#ibcon#first serial, iclass 29, count 0 2006.225.07:48:18.53#ibcon#enter sib2, iclass 29, count 0 2006.225.07:48:18.53#ibcon#flushed, iclass 29, count 0 2006.225.07:48:18.53#ibcon#about to write, iclass 29, count 0 2006.225.07:48:18.53#ibcon#wrote, iclass 29, count 0 2006.225.07:48:18.53#ibcon#about to read 3, iclass 29, count 0 2006.225.07:48:18.56#ibcon#read 3, iclass 29, count 0 2006.225.07:48:18.56#ibcon#about to read 4, iclass 29, count 0 2006.225.07:48:18.56#ibcon#read 4, iclass 29, count 0 2006.225.07:48:18.56#ibcon#about to read 5, iclass 29, count 0 2006.225.07:48:18.56#ibcon#read 5, iclass 29, count 0 2006.225.07:48:18.56#ibcon#about to read 6, iclass 29, count 0 2006.225.07:48:18.56#ibcon#read 6, iclass 29, count 0 2006.225.07:48:18.56#ibcon#end of sib2, iclass 29, count 0 2006.225.07:48:18.56#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:48:18.56#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:48:18.56#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:48:18.56#ibcon#*before write, iclass 29, count 0 2006.225.07:48:18.56#ibcon#enter sib2, iclass 29, count 0 2006.225.07:48:18.56#ibcon#flushed, iclass 29, count 0 2006.225.07:48:18.56#ibcon#about to write, iclass 29, count 0 2006.225.07:48:18.56#ibcon#wrote, iclass 29, count 0 2006.225.07:48:18.56#ibcon#about to read 3, iclass 29, count 0 2006.225.07:48:18.60#ibcon#read 3, iclass 29, count 0 2006.225.07:48:18.60#ibcon#about to read 4, iclass 29, count 0 2006.225.07:48:18.60#ibcon#read 4, iclass 29, count 0 2006.225.07:48:18.60#ibcon#about to read 5, iclass 29, count 0 2006.225.07:48:18.60#ibcon#read 5, iclass 29, count 0 2006.225.07:48:18.60#ibcon#about to read 6, iclass 29, count 0 2006.225.07:48:18.60#ibcon#read 6, iclass 29, count 0 2006.225.07:48:18.60#ibcon#end of sib2, iclass 29, count 0 2006.225.07:48:18.60#ibcon#*after write, iclass 29, count 0 2006.225.07:48:18.60#ibcon#*before return 0, iclass 29, count 0 2006.225.07:48:18.60#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:48:18.60#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:48:18.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:48:18.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:48:18.60$vc4f8/va=3,6 2006.225.07:48:18.60#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.07:48:18.60#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.07:48:18.60#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:18.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:48:18.65#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:48:18.65#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:48:18.65#ibcon#enter wrdev, iclass 31, count 2 2006.225.07:48:18.65#ibcon#first serial, iclass 31, count 2 2006.225.07:48:18.65#ibcon#enter sib2, iclass 31, count 2 2006.225.07:48:18.65#ibcon#flushed, iclass 31, count 2 2006.225.07:48:18.65#ibcon#about to write, iclass 31, count 2 2006.225.07:48:18.65#ibcon#wrote, iclass 31, count 2 2006.225.07:48:18.65#ibcon#about to read 3, iclass 31, count 2 2006.225.07:48:18.67#ibcon#read 3, iclass 31, count 2 2006.225.07:48:18.67#ibcon#about to read 4, iclass 31, count 2 2006.225.07:48:18.67#ibcon#read 4, iclass 31, count 2 2006.225.07:48:18.67#ibcon#about to read 5, iclass 31, count 2 2006.225.07:48:18.67#ibcon#read 5, iclass 31, count 2 2006.225.07:48:18.67#ibcon#about to read 6, iclass 31, count 2 2006.225.07:48:18.67#ibcon#read 6, iclass 31, count 2 2006.225.07:48:18.67#ibcon#end of sib2, iclass 31, count 2 2006.225.07:48:18.67#ibcon#*mode == 0, iclass 31, count 2 2006.225.07:48:18.67#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.07:48:18.67#ibcon#[25=AT03-06\r\n] 2006.225.07:48:18.67#ibcon#*before write, iclass 31, count 2 2006.225.07:48:18.67#ibcon#enter sib2, iclass 31, count 2 2006.225.07:48:18.67#ibcon#flushed, iclass 31, count 2 2006.225.07:48:18.67#ibcon#about to write, iclass 31, count 2 2006.225.07:48:18.67#ibcon#wrote, iclass 31, count 2 2006.225.07:48:18.67#ibcon#about to read 3, iclass 31, count 2 2006.225.07:48:18.70#ibcon#read 3, iclass 31, count 2 2006.225.07:48:18.70#ibcon#about to read 4, iclass 31, count 2 2006.225.07:48:18.70#ibcon#read 4, iclass 31, count 2 2006.225.07:48:18.70#ibcon#about to read 5, iclass 31, count 2 2006.225.07:48:18.70#ibcon#read 5, iclass 31, count 2 2006.225.07:48:18.70#ibcon#about to read 6, iclass 31, count 2 2006.225.07:48:18.70#ibcon#read 6, iclass 31, count 2 2006.225.07:48:18.70#ibcon#end of sib2, iclass 31, count 2 2006.225.07:48:18.70#ibcon#*after write, iclass 31, count 2 2006.225.07:48:18.70#ibcon#*before return 0, iclass 31, count 2 2006.225.07:48:18.70#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:48:18.70#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:48:18.70#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.07:48:18.70#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:18.70#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:48:18.82#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:48:18.82#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:48:18.82#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:48:18.82#ibcon#first serial, iclass 31, count 0 2006.225.07:48:18.82#ibcon#enter sib2, iclass 31, count 0 2006.225.07:48:18.82#ibcon#flushed, iclass 31, count 0 2006.225.07:48:18.82#ibcon#about to write, iclass 31, count 0 2006.225.07:48:18.82#ibcon#wrote, iclass 31, count 0 2006.225.07:48:18.82#ibcon#about to read 3, iclass 31, count 0 2006.225.07:48:18.84#ibcon#read 3, iclass 31, count 0 2006.225.07:48:18.84#ibcon#about to read 4, iclass 31, count 0 2006.225.07:48:18.84#ibcon#read 4, iclass 31, count 0 2006.225.07:48:18.84#ibcon#about to read 5, iclass 31, count 0 2006.225.07:48:18.84#ibcon#read 5, iclass 31, count 0 2006.225.07:48:18.84#ibcon#about to read 6, iclass 31, count 0 2006.225.07:48:18.84#ibcon#read 6, iclass 31, count 0 2006.225.07:48:18.84#ibcon#end of sib2, iclass 31, count 0 2006.225.07:48:18.84#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:48:18.84#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:48:18.84#ibcon#[25=USB\r\n] 2006.225.07:48:18.84#ibcon#*before write, iclass 31, count 0 2006.225.07:48:18.84#ibcon#enter sib2, iclass 31, count 0 2006.225.07:48:18.84#ibcon#flushed, iclass 31, count 0 2006.225.07:48:18.84#ibcon#about to write, iclass 31, count 0 2006.225.07:48:18.84#ibcon#wrote, iclass 31, count 0 2006.225.07:48:18.84#ibcon#about to read 3, iclass 31, count 0 2006.225.07:48:18.87#ibcon#read 3, iclass 31, count 0 2006.225.07:48:18.87#ibcon#about to read 4, iclass 31, count 0 2006.225.07:48:18.87#ibcon#read 4, iclass 31, count 0 2006.225.07:48:18.87#ibcon#about to read 5, iclass 31, count 0 2006.225.07:48:18.87#ibcon#read 5, iclass 31, count 0 2006.225.07:48:18.87#ibcon#about to read 6, iclass 31, count 0 2006.225.07:48:18.87#ibcon#read 6, iclass 31, count 0 2006.225.07:48:18.87#ibcon#end of sib2, iclass 31, count 0 2006.225.07:48:18.87#ibcon#*after write, iclass 31, count 0 2006.225.07:48:18.87#ibcon#*before return 0, iclass 31, count 0 2006.225.07:48:18.87#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:48:18.87#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:48:18.87#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:48:18.87#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:48:18.87$vc4f8/valo=4,832.99 2006.225.07:48:18.87#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.07:48:18.87#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.07:48:18.87#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:18.87#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:48:18.87#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:48:18.87#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:48:18.87#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:48:18.87#ibcon#first serial, iclass 33, count 0 2006.225.07:48:18.87#ibcon#enter sib2, iclass 33, count 0 2006.225.07:48:18.87#ibcon#flushed, iclass 33, count 0 2006.225.07:48:18.87#ibcon#about to write, iclass 33, count 0 2006.225.07:48:18.87#ibcon#wrote, iclass 33, count 0 2006.225.07:48:18.87#ibcon#about to read 3, iclass 33, count 0 2006.225.07:48:18.90#ibcon#read 3, iclass 33, count 0 2006.225.07:48:18.90#ibcon#about to read 4, iclass 33, count 0 2006.225.07:48:18.90#ibcon#read 4, iclass 33, count 0 2006.225.07:48:18.90#ibcon#about to read 5, iclass 33, count 0 2006.225.07:48:18.90#ibcon#read 5, iclass 33, count 0 2006.225.07:48:18.90#ibcon#about to read 6, iclass 33, count 0 2006.225.07:48:18.90#ibcon#read 6, iclass 33, count 0 2006.225.07:48:18.90#ibcon#end of sib2, iclass 33, count 0 2006.225.07:48:18.90#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:48:18.90#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:48:18.90#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:48:18.90#ibcon#*before write, iclass 33, count 0 2006.225.07:48:18.90#ibcon#enter sib2, iclass 33, count 0 2006.225.07:48:18.90#ibcon#flushed, iclass 33, count 0 2006.225.07:48:18.90#ibcon#about to write, iclass 33, count 0 2006.225.07:48:18.90#ibcon#wrote, iclass 33, count 0 2006.225.07:48:18.90#ibcon#about to read 3, iclass 33, count 0 2006.225.07:48:18.94#ibcon#read 3, iclass 33, count 0 2006.225.07:48:18.94#ibcon#about to read 4, iclass 33, count 0 2006.225.07:48:18.94#ibcon#read 4, iclass 33, count 0 2006.225.07:48:18.94#ibcon#about to read 5, iclass 33, count 0 2006.225.07:48:18.94#ibcon#read 5, iclass 33, count 0 2006.225.07:48:18.94#ibcon#about to read 6, iclass 33, count 0 2006.225.07:48:18.94#ibcon#read 6, iclass 33, count 0 2006.225.07:48:18.94#ibcon#end of sib2, iclass 33, count 0 2006.225.07:48:18.94#ibcon#*after write, iclass 33, count 0 2006.225.07:48:18.94#ibcon#*before return 0, iclass 33, count 0 2006.225.07:48:18.94#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:48:18.94#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:48:18.94#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:48:18.94#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:48:18.94$vc4f8/va=4,7 2006.225.07:48:18.94#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.07:48:18.94#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.07:48:18.94#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:18.94#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:48:18.99#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:48:18.99#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:48:18.99#ibcon#enter wrdev, iclass 35, count 2 2006.225.07:48:18.99#ibcon#first serial, iclass 35, count 2 2006.225.07:48:18.99#ibcon#enter sib2, iclass 35, count 2 2006.225.07:48:18.99#ibcon#flushed, iclass 35, count 2 2006.225.07:48:18.99#ibcon#about to write, iclass 35, count 2 2006.225.07:48:18.99#ibcon#wrote, iclass 35, count 2 2006.225.07:48:18.99#ibcon#about to read 3, iclass 35, count 2 2006.225.07:48:19.01#ibcon#read 3, iclass 35, count 2 2006.225.07:48:19.01#ibcon#about to read 4, iclass 35, count 2 2006.225.07:48:19.01#ibcon#read 4, iclass 35, count 2 2006.225.07:48:19.01#ibcon#about to read 5, iclass 35, count 2 2006.225.07:48:19.01#ibcon#read 5, iclass 35, count 2 2006.225.07:48:19.01#ibcon#about to read 6, iclass 35, count 2 2006.225.07:48:19.01#ibcon#read 6, iclass 35, count 2 2006.225.07:48:19.01#ibcon#end of sib2, iclass 35, count 2 2006.225.07:48:19.01#ibcon#*mode == 0, iclass 35, count 2 2006.225.07:48:19.01#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.07:48:19.01#ibcon#[25=AT04-07\r\n] 2006.225.07:48:19.01#ibcon#*before write, iclass 35, count 2 2006.225.07:48:19.01#ibcon#enter sib2, iclass 35, count 2 2006.225.07:48:19.01#ibcon#flushed, iclass 35, count 2 2006.225.07:48:19.01#ibcon#about to write, iclass 35, count 2 2006.225.07:48:19.01#ibcon#wrote, iclass 35, count 2 2006.225.07:48:19.01#ibcon#about to read 3, iclass 35, count 2 2006.225.07:48:19.04#ibcon#read 3, iclass 35, count 2 2006.225.07:48:19.04#ibcon#about to read 4, iclass 35, count 2 2006.225.07:48:19.04#ibcon#read 4, iclass 35, count 2 2006.225.07:48:19.04#ibcon#about to read 5, iclass 35, count 2 2006.225.07:48:19.04#ibcon#read 5, iclass 35, count 2 2006.225.07:48:19.04#ibcon#about to read 6, iclass 35, count 2 2006.225.07:48:19.04#ibcon#read 6, iclass 35, count 2 2006.225.07:48:19.04#ibcon#end of sib2, iclass 35, count 2 2006.225.07:48:19.04#ibcon#*after write, iclass 35, count 2 2006.225.07:48:19.04#ibcon#*before return 0, iclass 35, count 2 2006.225.07:48:19.04#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:48:19.04#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:48:19.04#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.07:48:19.04#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:19.04#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:48:19.16#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:48:19.16#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:48:19.16#ibcon#enter wrdev, iclass 35, count 0 2006.225.07:48:19.16#ibcon#first serial, iclass 35, count 0 2006.225.07:48:19.16#ibcon#enter sib2, iclass 35, count 0 2006.225.07:48:19.16#ibcon#flushed, iclass 35, count 0 2006.225.07:48:19.16#ibcon#about to write, iclass 35, count 0 2006.225.07:48:19.16#ibcon#wrote, iclass 35, count 0 2006.225.07:48:19.16#ibcon#about to read 3, iclass 35, count 0 2006.225.07:48:19.18#ibcon#read 3, iclass 35, count 0 2006.225.07:48:19.18#ibcon#about to read 4, iclass 35, count 0 2006.225.07:48:19.18#ibcon#read 4, iclass 35, count 0 2006.225.07:48:19.18#ibcon#about to read 5, iclass 35, count 0 2006.225.07:48:19.18#ibcon#read 5, iclass 35, count 0 2006.225.07:48:19.18#ibcon#about to read 6, iclass 35, count 0 2006.225.07:48:19.18#ibcon#read 6, iclass 35, count 0 2006.225.07:48:19.18#ibcon#end of sib2, iclass 35, count 0 2006.225.07:48:19.18#ibcon#*mode == 0, iclass 35, count 0 2006.225.07:48:19.18#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.07:48:19.18#ibcon#[25=USB\r\n] 2006.225.07:48:19.18#ibcon#*before write, iclass 35, count 0 2006.225.07:48:19.18#ibcon#enter sib2, iclass 35, count 0 2006.225.07:48:19.18#ibcon#flushed, iclass 35, count 0 2006.225.07:48:19.18#ibcon#about to write, iclass 35, count 0 2006.225.07:48:19.18#ibcon#wrote, iclass 35, count 0 2006.225.07:48:19.18#ibcon#about to read 3, iclass 35, count 0 2006.225.07:48:19.21#ibcon#read 3, iclass 35, count 0 2006.225.07:48:19.21#ibcon#about to read 4, iclass 35, count 0 2006.225.07:48:19.21#ibcon#read 4, iclass 35, count 0 2006.225.07:48:19.21#ibcon#about to read 5, iclass 35, count 0 2006.225.07:48:19.21#ibcon#read 5, iclass 35, count 0 2006.225.07:48:19.21#ibcon#about to read 6, iclass 35, count 0 2006.225.07:48:19.21#ibcon#read 6, iclass 35, count 0 2006.225.07:48:19.21#ibcon#end of sib2, iclass 35, count 0 2006.225.07:48:19.21#ibcon#*after write, iclass 35, count 0 2006.225.07:48:19.21#ibcon#*before return 0, iclass 35, count 0 2006.225.07:48:19.21#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:48:19.21#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:48:19.21#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.07:48:19.21#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.07:48:19.21$vc4f8/valo=5,652.99 2006.225.07:48:19.21#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.07:48:19.21#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.07:48:19.21#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:19.21#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:48:19.21#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:48:19.21#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:48:19.21#ibcon#enter wrdev, iclass 37, count 0 2006.225.07:48:19.21#ibcon#first serial, iclass 37, count 0 2006.225.07:48:19.21#ibcon#enter sib2, iclass 37, count 0 2006.225.07:48:19.21#ibcon#flushed, iclass 37, count 0 2006.225.07:48:19.21#ibcon#about to write, iclass 37, count 0 2006.225.07:48:19.21#ibcon#wrote, iclass 37, count 0 2006.225.07:48:19.21#ibcon#about to read 3, iclass 37, count 0 2006.225.07:48:19.23#ibcon#read 3, iclass 37, count 0 2006.225.07:48:19.23#ibcon#about to read 4, iclass 37, count 0 2006.225.07:48:19.23#ibcon#read 4, iclass 37, count 0 2006.225.07:48:19.23#ibcon#about to read 5, iclass 37, count 0 2006.225.07:48:19.23#ibcon#read 5, iclass 37, count 0 2006.225.07:48:19.23#ibcon#about to read 6, iclass 37, count 0 2006.225.07:48:19.23#ibcon#read 6, iclass 37, count 0 2006.225.07:48:19.23#ibcon#end of sib2, iclass 37, count 0 2006.225.07:48:19.23#ibcon#*mode == 0, iclass 37, count 0 2006.225.07:48:19.23#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.07:48:19.23#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:48:19.23#ibcon#*before write, iclass 37, count 0 2006.225.07:48:19.23#ibcon#enter sib2, iclass 37, count 0 2006.225.07:48:19.23#ibcon#flushed, iclass 37, count 0 2006.225.07:48:19.23#ibcon#about to write, iclass 37, count 0 2006.225.07:48:19.23#ibcon#wrote, iclass 37, count 0 2006.225.07:48:19.23#ibcon#about to read 3, iclass 37, count 0 2006.225.07:48:19.27#ibcon#read 3, iclass 37, count 0 2006.225.07:48:19.27#ibcon#about to read 4, iclass 37, count 0 2006.225.07:48:19.27#ibcon#read 4, iclass 37, count 0 2006.225.07:48:19.27#ibcon#about to read 5, iclass 37, count 0 2006.225.07:48:19.27#ibcon#read 5, iclass 37, count 0 2006.225.07:48:19.27#ibcon#about to read 6, iclass 37, count 0 2006.225.07:48:19.27#ibcon#read 6, iclass 37, count 0 2006.225.07:48:19.27#ibcon#end of sib2, iclass 37, count 0 2006.225.07:48:19.27#ibcon#*after write, iclass 37, count 0 2006.225.07:48:19.27#ibcon#*before return 0, iclass 37, count 0 2006.225.07:48:19.27#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:48:19.27#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:48:19.27#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.07:48:19.27#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.07:48:19.27$vc4f8/va=5,7 2006.225.07:48:19.27#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.07:48:19.27#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.07:48:19.27#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:19.27#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:48:19.33#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:48:19.33#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:48:19.33#ibcon#enter wrdev, iclass 39, count 2 2006.225.07:48:19.33#ibcon#first serial, iclass 39, count 2 2006.225.07:48:19.33#ibcon#enter sib2, iclass 39, count 2 2006.225.07:48:19.33#ibcon#flushed, iclass 39, count 2 2006.225.07:48:19.33#ibcon#about to write, iclass 39, count 2 2006.225.07:48:19.33#ibcon#wrote, iclass 39, count 2 2006.225.07:48:19.33#ibcon#about to read 3, iclass 39, count 2 2006.225.07:48:19.35#ibcon#read 3, iclass 39, count 2 2006.225.07:48:19.35#ibcon#about to read 4, iclass 39, count 2 2006.225.07:48:19.35#ibcon#read 4, iclass 39, count 2 2006.225.07:48:19.35#ibcon#about to read 5, iclass 39, count 2 2006.225.07:48:19.35#ibcon#read 5, iclass 39, count 2 2006.225.07:48:19.35#ibcon#about to read 6, iclass 39, count 2 2006.225.07:48:19.35#ibcon#read 6, iclass 39, count 2 2006.225.07:48:19.35#ibcon#end of sib2, iclass 39, count 2 2006.225.07:48:19.35#ibcon#*mode == 0, iclass 39, count 2 2006.225.07:48:19.35#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.07:48:19.35#ibcon#[25=AT05-07\r\n] 2006.225.07:48:19.35#ibcon#*before write, iclass 39, count 2 2006.225.07:48:19.35#ibcon#enter sib2, iclass 39, count 2 2006.225.07:48:19.35#ibcon#flushed, iclass 39, count 2 2006.225.07:48:19.35#ibcon#about to write, iclass 39, count 2 2006.225.07:48:19.35#ibcon#wrote, iclass 39, count 2 2006.225.07:48:19.35#ibcon#about to read 3, iclass 39, count 2 2006.225.07:48:19.38#ibcon#read 3, iclass 39, count 2 2006.225.07:48:19.38#ibcon#about to read 4, iclass 39, count 2 2006.225.07:48:19.38#ibcon#read 4, iclass 39, count 2 2006.225.07:48:19.38#ibcon#about to read 5, iclass 39, count 2 2006.225.07:48:19.38#ibcon#read 5, iclass 39, count 2 2006.225.07:48:19.38#ibcon#about to read 6, iclass 39, count 2 2006.225.07:48:19.38#ibcon#read 6, iclass 39, count 2 2006.225.07:48:19.38#ibcon#end of sib2, iclass 39, count 2 2006.225.07:48:19.38#ibcon#*after write, iclass 39, count 2 2006.225.07:48:19.38#ibcon#*before return 0, iclass 39, count 2 2006.225.07:48:19.38#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:48:19.38#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:48:19.38#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.07:48:19.38#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:19.38#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:48:19.50#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:48:19.50#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:48:19.50#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:48:19.50#ibcon#first serial, iclass 39, count 0 2006.225.07:48:19.50#ibcon#enter sib2, iclass 39, count 0 2006.225.07:48:19.50#ibcon#flushed, iclass 39, count 0 2006.225.07:48:19.50#ibcon#about to write, iclass 39, count 0 2006.225.07:48:19.50#ibcon#wrote, iclass 39, count 0 2006.225.07:48:19.50#ibcon#about to read 3, iclass 39, count 0 2006.225.07:48:19.52#ibcon#read 3, iclass 39, count 0 2006.225.07:48:19.52#ibcon#about to read 4, iclass 39, count 0 2006.225.07:48:19.52#ibcon#read 4, iclass 39, count 0 2006.225.07:48:19.52#ibcon#about to read 5, iclass 39, count 0 2006.225.07:48:19.52#ibcon#read 5, iclass 39, count 0 2006.225.07:48:19.52#ibcon#about to read 6, iclass 39, count 0 2006.225.07:48:19.52#ibcon#read 6, iclass 39, count 0 2006.225.07:48:19.52#ibcon#end of sib2, iclass 39, count 0 2006.225.07:48:19.52#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:48:19.52#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:48:19.52#ibcon#[25=USB\r\n] 2006.225.07:48:19.52#ibcon#*before write, iclass 39, count 0 2006.225.07:48:19.52#ibcon#enter sib2, iclass 39, count 0 2006.225.07:48:19.52#ibcon#flushed, iclass 39, count 0 2006.225.07:48:19.52#ibcon#about to write, iclass 39, count 0 2006.225.07:48:19.52#ibcon#wrote, iclass 39, count 0 2006.225.07:48:19.52#ibcon#about to read 3, iclass 39, count 0 2006.225.07:48:19.55#ibcon#read 3, iclass 39, count 0 2006.225.07:48:19.55#ibcon#about to read 4, iclass 39, count 0 2006.225.07:48:19.55#ibcon#read 4, iclass 39, count 0 2006.225.07:48:19.55#ibcon#about to read 5, iclass 39, count 0 2006.225.07:48:19.55#ibcon#read 5, iclass 39, count 0 2006.225.07:48:19.55#ibcon#about to read 6, iclass 39, count 0 2006.225.07:48:19.55#ibcon#read 6, iclass 39, count 0 2006.225.07:48:19.55#ibcon#end of sib2, iclass 39, count 0 2006.225.07:48:19.55#ibcon#*after write, iclass 39, count 0 2006.225.07:48:19.55#ibcon#*before return 0, iclass 39, count 0 2006.225.07:48:19.55#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:48:19.55#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:48:19.55#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:48:19.55#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:48:19.55$vc4f8/valo=6,772.99 2006.225.07:48:19.55#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.07:48:19.55#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.07:48:19.55#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:19.55#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:48:19.55#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:48:19.55#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:48:19.55#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:48:19.55#ibcon#first serial, iclass 3, count 0 2006.225.07:48:19.55#ibcon#enter sib2, iclass 3, count 0 2006.225.07:48:19.55#ibcon#flushed, iclass 3, count 0 2006.225.07:48:19.55#ibcon#about to write, iclass 3, count 0 2006.225.07:48:19.55#ibcon#wrote, iclass 3, count 0 2006.225.07:48:19.55#ibcon#about to read 3, iclass 3, count 0 2006.225.07:48:19.57#ibcon#read 3, iclass 3, count 0 2006.225.07:48:19.57#ibcon#about to read 4, iclass 3, count 0 2006.225.07:48:19.57#ibcon#read 4, iclass 3, count 0 2006.225.07:48:19.57#ibcon#about to read 5, iclass 3, count 0 2006.225.07:48:19.57#ibcon#read 5, iclass 3, count 0 2006.225.07:48:19.57#ibcon#about to read 6, iclass 3, count 0 2006.225.07:48:19.57#ibcon#read 6, iclass 3, count 0 2006.225.07:48:19.57#ibcon#end of sib2, iclass 3, count 0 2006.225.07:48:19.57#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:48:19.57#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:48:19.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:48:19.57#ibcon#*before write, iclass 3, count 0 2006.225.07:48:19.57#ibcon#enter sib2, iclass 3, count 0 2006.225.07:48:19.57#ibcon#flushed, iclass 3, count 0 2006.225.07:48:19.57#ibcon#about to write, iclass 3, count 0 2006.225.07:48:19.57#ibcon#wrote, iclass 3, count 0 2006.225.07:48:19.57#ibcon#about to read 3, iclass 3, count 0 2006.225.07:48:19.61#ibcon#read 3, iclass 3, count 0 2006.225.07:48:19.61#ibcon#about to read 4, iclass 3, count 0 2006.225.07:48:19.61#ibcon#read 4, iclass 3, count 0 2006.225.07:48:19.61#ibcon#about to read 5, iclass 3, count 0 2006.225.07:48:19.61#ibcon#read 5, iclass 3, count 0 2006.225.07:48:19.61#ibcon#about to read 6, iclass 3, count 0 2006.225.07:48:19.61#ibcon#read 6, iclass 3, count 0 2006.225.07:48:19.61#ibcon#end of sib2, iclass 3, count 0 2006.225.07:48:19.61#ibcon#*after write, iclass 3, count 0 2006.225.07:48:19.61#ibcon#*before return 0, iclass 3, count 0 2006.225.07:48:19.61#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:48:19.61#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:48:19.61#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:48:19.61#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:48:19.61$vc4f8/va=6,6 2006.225.07:48:19.61#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.07:48:19.61#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.07:48:19.61#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:19.61#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:48:19.67#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:48:19.67#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:48:19.67#ibcon#enter wrdev, iclass 5, count 2 2006.225.07:48:19.67#ibcon#first serial, iclass 5, count 2 2006.225.07:48:19.67#ibcon#enter sib2, iclass 5, count 2 2006.225.07:48:19.67#ibcon#flushed, iclass 5, count 2 2006.225.07:48:19.67#ibcon#about to write, iclass 5, count 2 2006.225.07:48:19.67#ibcon#wrote, iclass 5, count 2 2006.225.07:48:19.67#ibcon#about to read 3, iclass 5, count 2 2006.225.07:48:19.69#ibcon#read 3, iclass 5, count 2 2006.225.07:48:19.69#ibcon#about to read 4, iclass 5, count 2 2006.225.07:48:19.69#ibcon#read 4, iclass 5, count 2 2006.225.07:48:19.69#ibcon#about to read 5, iclass 5, count 2 2006.225.07:48:19.69#ibcon#read 5, iclass 5, count 2 2006.225.07:48:19.69#ibcon#about to read 6, iclass 5, count 2 2006.225.07:48:19.69#ibcon#read 6, iclass 5, count 2 2006.225.07:48:19.69#ibcon#end of sib2, iclass 5, count 2 2006.225.07:48:19.69#ibcon#*mode == 0, iclass 5, count 2 2006.225.07:48:19.69#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.07:48:19.69#ibcon#[25=AT06-06\r\n] 2006.225.07:48:19.69#ibcon#*before write, iclass 5, count 2 2006.225.07:48:19.69#ibcon#enter sib2, iclass 5, count 2 2006.225.07:48:19.69#ibcon#flushed, iclass 5, count 2 2006.225.07:48:19.69#ibcon#about to write, iclass 5, count 2 2006.225.07:48:19.69#ibcon#wrote, iclass 5, count 2 2006.225.07:48:19.69#ibcon#about to read 3, iclass 5, count 2 2006.225.07:48:19.72#ibcon#read 3, iclass 5, count 2 2006.225.07:48:19.72#ibcon#about to read 4, iclass 5, count 2 2006.225.07:48:19.72#ibcon#read 4, iclass 5, count 2 2006.225.07:48:19.72#ibcon#about to read 5, iclass 5, count 2 2006.225.07:48:19.72#ibcon#read 5, iclass 5, count 2 2006.225.07:48:19.72#ibcon#about to read 6, iclass 5, count 2 2006.225.07:48:19.72#ibcon#read 6, iclass 5, count 2 2006.225.07:48:19.72#ibcon#end of sib2, iclass 5, count 2 2006.225.07:48:19.72#ibcon#*after write, iclass 5, count 2 2006.225.07:48:19.72#ibcon#*before return 0, iclass 5, count 2 2006.225.07:48:19.72#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:48:19.72#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:48:19.72#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.07:48:19.72#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:19.72#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:48:19.84#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:48:19.84#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:48:19.84#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:48:19.84#ibcon#first serial, iclass 5, count 0 2006.225.07:48:19.84#ibcon#enter sib2, iclass 5, count 0 2006.225.07:48:19.84#ibcon#flushed, iclass 5, count 0 2006.225.07:48:19.84#ibcon#about to write, iclass 5, count 0 2006.225.07:48:19.84#ibcon#wrote, iclass 5, count 0 2006.225.07:48:19.84#ibcon#about to read 3, iclass 5, count 0 2006.225.07:48:19.86#ibcon#read 3, iclass 5, count 0 2006.225.07:48:19.86#ibcon#about to read 4, iclass 5, count 0 2006.225.07:48:19.86#ibcon#read 4, iclass 5, count 0 2006.225.07:48:19.86#ibcon#about to read 5, iclass 5, count 0 2006.225.07:48:19.86#ibcon#read 5, iclass 5, count 0 2006.225.07:48:19.86#ibcon#about to read 6, iclass 5, count 0 2006.225.07:48:19.86#ibcon#read 6, iclass 5, count 0 2006.225.07:48:19.86#ibcon#end of sib2, iclass 5, count 0 2006.225.07:48:19.86#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:48:19.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:48:19.86#ibcon#[25=USB\r\n] 2006.225.07:48:19.86#ibcon#*before write, iclass 5, count 0 2006.225.07:48:19.86#ibcon#enter sib2, iclass 5, count 0 2006.225.07:48:19.86#ibcon#flushed, iclass 5, count 0 2006.225.07:48:19.86#ibcon#about to write, iclass 5, count 0 2006.225.07:48:19.86#ibcon#wrote, iclass 5, count 0 2006.225.07:48:19.86#ibcon#about to read 3, iclass 5, count 0 2006.225.07:48:19.89#ibcon#read 3, iclass 5, count 0 2006.225.07:48:19.89#ibcon#about to read 4, iclass 5, count 0 2006.225.07:48:19.89#ibcon#read 4, iclass 5, count 0 2006.225.07:48:19.89#ibcon#about to read 5, iclass 5, count 0 2006.225.07:48:19.89#ibcon#read 5, iclass 5, count 0 2006.225.07:48:19.89#ibcon#about to read 6, iclass 5, count 0 2006.225.07:48:19.89#ibcon#read 6, iclass 5, count 0 2006.225.07:48:19.89#ibcon#end of sib2, iclass 5, count 0 2006.225.07:48:19.89#ibcon#*after write, iclass 5, count 0 2006.225.07:48:19.89#ibcon#*before return 0, iclass 5, count 0 2006.225.07:48:19.89#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:48:19.89#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:48:19.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:48:19.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:48:19.89$vc4f8/valo=7,832.99 2006.225.07:48:19.89#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.225.07:48:19.89#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.225.07:48:19.89#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:19.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:48:19.89#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:48:19.89#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:48:19.89#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:48:19.89#ibcon#first serial, iclass 7, count 0 2006.225.07:48:19.89#ibcon#enter sib2, iclass 7, count 0 2006.225.07:48:19.89#ibcon#flushed, iclass 7, count 0 2006.225.07:48:19.89#ibcon#about to write, iclass 7, count 0 2006.225.07:48:19.89#ibcon#wrote, iclass 7, count 0 2006.225.07:48:19.89#ibcon#about to read 3, iclass 7, count 0 2006.225.07:48:19.91#ibcon#read 3, iclass 7, count 0 2006.225.07:48:19.91#ibcon#about to read 4, iclass 7, count 0 2006.225.07:48:19.91#ibcon#read 4, iclass 7, count 0 2006.225.07:48:19.91#ibcon#about to read 5, iclass 7, count 0 2006.225.07:48:19.91#ibcon#read 5, iclass 7, count 0 2006.225.07:48:19.91#ibcon#about to read 6, iclass 7, count 0 2006.225.07:48:19.91#ibcon#read 6, iclass 7, count 0 2006.225.07:48:19.91#ibcon#end of sib2, iclass 7, count 0 2006.225.07:48:19.91#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:48:19.91#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:48:19.91#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:48:19.91#ibcon#*before write, iclass 7, count 0 2006.225.07:48:19.91#ibcon#enter sib2, iclass 7, count 0 2006.225.07:48:19.91#ibcon#flushed, iclass 7, count 0 2006.225.07:48:19.91#ibcon#about to write, iclass 7, count 0 2006.225.07:48:19.91#ibcon#wrote, iclass 7, count 0 2006.225.07:48:19.91#ibcon#about to read 3, iclass 7, count 0 2006.225.07:48:19.95#ibcon#read 3, iclass 7, count 0 2006.225.07:48:19.95#ibcon#about to read 4, iclass 7, count 0 2006.225.07:48:19.95#ibcon#read 4, iclass 7, count 0 2006.225.07:48:19.95#ibcon#about to read 5, iclass 7, count 0 2006.225.07:48:19.95#ibcon#read 5, iclass 7, count 0 2006.225.07:48:19.95#ibcon#about to read 6, iclass 7, count 0 2006.225.07:48:19.95#ibcon#read 6, iclass 7, count 0 2006.225.07:48:19.95#ibcon#end of sib2, iclass 7, count 0 2006.225.07:48:19.95#ibcon#*after write, iclass 7, count 0 2006.225.07:48:19.95#ibcon#*before return 0, iclass 7, count 0 2006.225.07:48:19.95#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:48:19.95#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:48:19.95#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:48:19.95#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:48:19.95$vc4f8/va=7,6 2006.225.07:48:19.95#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.225.07:48:19.95#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.225.07:48:19.95#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:19.95#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:48:20.01#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:48:20.01#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:48:20.01#ibcon#enter wrdev, iclass 11, count 2 2006.225.07:48:20.01#ibcon#first serial, iclass 11, count 2 2006.225.07:48:20.01#ibcon#enter sib2, iclass 11, count 2 2006.225.07:48:20.01#ibcon#flushed, iclass 11, count 2 2006.225.07:48:20.01#ibcon#about to write, iclass 11, count 2 2006.225.07:48:20.01#ibcon#wrote, iclass 11, count 2 2006.225.07:48:20.01#ibcon#about to read 3, iclass 11, count 2 2006.225.07:48:20.03#ibcon#read 3, iclass 11, count 2 2006.225.07:48:20.03#ibcon#about to read 4, iclass 11, count 2 2006.225.07:48:20.03#ibcon#read 4, iclass 11, count 2 2006.225.07:48:20.03#ibcon#about to read 5, iclass 11, count 2 2006.225.07:48:20.03#ibcon#read 5, iclass 11, count 2 2006.225.07:48:20.03#ibcon#about to read 6, iclass 11, count 2 2006.225.07:48:20.03#ibcon#read 6, iclass 11, count 2 2006.225.07:48:20.03#ibcon#end of sib2, iclass 11, count 2 2006.225.07:48:20.03#ibcon#*mode == 0, iclass 11, count 2 2006.225.07:48:20.03#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.225.07:48:20.03#ibcon#[25=AT07-06\r\n] 2006.225.07:48:20.03#ibcon#*before write, iclass 11, count 2 2006.225.07:48:20.03#ibcon#enter sib2, iclass 11, count 2 2006.225.07:48:20.03#ibcon#flushed, iclass 11, count 2 2006.225.07:48:20.03#ibcon#about to write, iclass 11, count 2 2006.225.07:48:20.03#ibcon#wrote, iclass 11, count 2 2006.225.07:48:20.03#ibcon#about to read 3, iclass 11, count 2 2006.225.07:48:20.06#ibcon#read 3, iclass 11, count 2 2006.225.07:48:20.06#ibcon#about to read 4, iclass 11, count 2 2006.225.07:48:20.06#ibcon#read 4, iclass 11, count 2 2006.225.07:48:20.06#ibcon#about to read 5, iclass 11, count 2 2006.225.07:48:20.06#ibcon#read 5, iclass 11, count 2 2006.225.07:48:20.06#ibcon#about to read 6, iclass 11, count 2 2006.225.07:48:20.06#ibcon#read 6, iclass 11, count 2 2006.225.07:48:20.06#ibcon#end of sib2, iclass 11, count 2 2006.225.07:48:20.06#ibcon#*after write, iclass 11, count 2 2006.225.07:48:20.06#ibcon#*before return 0, iclass 11, count 2 2006.225.07:48:20.06#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:48:20.06#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.225.07:48:20.06#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.225.07:48:20.06#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:20.06#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:48:20.18#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:48:20.18#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:48:20.18#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:48:20.18#ibcon#first serial, iclass 11, count 0 2006.225.07:48:20.18#ibcon#enter sib2, iclass 11, count 0 2006.225.07:48:20.18#ibcon#flushed, iclass 11, count 0 2006.225.07:48:20.18#ibcon#about to write, iclass 11, count 0 2006.225.07:48:20.18#ibcon#wrote, iclass 11, count 0 2006.225.07:48:20.18#ibcon#about to read 3, iclass 11, count 0 2006.225.07:48:20.20#ibcon#read 3, iclass 11, count 0 2006.225.07:48:20.20#ibcon#about to read 4, iclass 11, count 0 2006.225.07:48:20.20#ibcon#read 4, iclass 11, count 0 2006.225.07:48:20.20#ibcon#about to read 5, iclass 11, count 0 2006.225.07:48:20.20#ibcon#read 5, iclass 11, count 0 2006.225.07:48:20.20#ibcon#about to read 6, iclass 11, count 0 2006.225.07:48:20.20#ibcon#read 6, iclass 11, count 0 2006.225.07:48:20.20#ibcon#end of sib2, iclass 11, count 0 2006.225.07:48:20.20#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:48:20.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:48:20.20#ibcon#[25=USB\r\n] 2006.225.07:48:20.20#ibcon#*before write, iclass 11, count 0 2006.225.07:48:20.20#ibcon#enter sib2, iclass 11, count 0 2006.225.07:48:20.20#ibcon#flushed, iclass 11, count 0 2006.225.07:48:20.20#ibcon#about to write, iclass 11, count 0 2006.225.07:48:20.20#ibcon#wrote, iclass 11, count 0 2006.225.07:48:20.20#ibcon#about to read 3, iclass 11, count 0 2006.225.07:48:20.23#ibcon#read 3, iclass 11, count 0 2006.225.07:48:20.23#ibcon#about to read 4, iclass 11, count 0 2006.225.07:48:20.23#ibcon#read 4, iclass 11, count 0 2006.225.07:48:20.23#ibcon#about to read 5, iclass 11, count 0 2006.225.07:48:20.23#ibcon#read 5, iclass 11, count 0 2006.225.07:48:20.23#ibcon#about to read 6, iclass 11, count 0 2006.225.07:48:20.23#ibcon#read 6, iclass 11, count 0 2006.225.07:48:20.23#ibcon#end of sib2, iclass 11, count 0 2006.225.07:48:20.23#ibcon#*after write, iclass 11, count 0 2006.225.07:48:20.23#ibcon#*before return 0, iclass 11, count 0 2006.225.07:48:20.23#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:48:20.23#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.225.07:48:20.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:48:20.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:48:20.23$vc4f8/valo=8,852.99 2006.225.07:48:20.23#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.07:48:20.23#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.07:48:20.23#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:20.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:48:20.23#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:48:20.23#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:48:20.23#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:48:20.23#ibcon#first serial, iclass 13, count 0 2006.225.07:48:20.23#ibcon#enter sib2, iclass 13, count 0 2006.225.07:48:20.23#ibcon#flushed, iclass 13, count 0 2006.225.07:48:20.23#ibcon#about to write, iclass 13, count 0 2006.225.07:48:20.23#ibcon#wrote, iclass 13, count 0 2006.225.07:48:20.23#ibcon#about to read 3, iclass 13, count 0 2006.225.07:48:20.25#ibcon#read 3, iclass 13, count 0 2006.225.07:48:20.25#ibcon#about to read 4, iclass 13, count 0 2006.225.07:48:20.25#ibcon#read 4, iclass 13, count 0 2006.225.07:48:20.25#ibcon#about to read 5, iclass 13, count 0 2006.225.07:48:20.25#ibcon#read 5, iclass 13, count 0 2006.225.07:48:20.25#ibcon#about to read 6, iclass 13, count 0 2006.225.07:48:20.25#ibcon#read 6, iclass 13, count 0 2006.225.07:48:20.25#ibcon#end of sib2, iclass 13, count 0 2006.225.07:48:20.25#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:48:20.25#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:48:20.25#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:48:20.25#ibcon#*before write, iclass 13, count 0 2006.225.07:48:20.25#ibcon#enter sib2, iclass 13, count 0 2006.225.07:48:20.25#ibcon#flushed, iclass 13, count 0 2006.225.07:48:20.25#ibcon#about to write, iclass 13, count 0 2006.225.07:48:20.25#ibcon#wrote, iclass 13, count 0 2006.225.07:48:20.25#ibcon#about to read 3, iclass 13, count 0 2006.225.07:48:20.29#ibcon#read 3, iclass 13, count 0 2006.225.07:48:20.29#ibcon#about to read 4, iclass 13, count 0 2006.225.07:48:20.29#ibcon#read 4, iclass 13, count 0 2006.225.07:48:20.29#ibcon#about to read 5, iclass 13, count 0 2006.225.07:48:20.29#ibcon#read 5, iclass 13, count 0 2006.225.07:48:20.29#ibcon#about to read 6, iclass 13, count 0 2006.225.07:48:20.29#ibcon#read 6, iclass 13, count 0 2006.225.07:48:20.29#ibcon#end of sib2, iclass 13, count 0 2006.225.07:48:20.29#ibcon#*after write, iclass 13, count 0 2006.225.07:48:20.29#ibcon#*before return 0, iclass 13, count 0 2006.225.07:48:20.29#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:48:20.29#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.07:48:20.29#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:48:20.29#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:48:20.29$vc4f8/va=8,7 2006.225.07:48:20.29#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.225.07:48:20.29#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.225.07:48:20.29#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:20.29#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:48:20.35#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:48:20.35#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:48:20.35#ibcon#enter wrdev, iclass 15, count 2 2006.225.07:48:20.35#ibcon#first serial, iclass 15, count 2 2006.225.07:48:20.35#ibcon#enter sib2, iclass 15, count 2 2006.225.07:48:20.35#ibcon#flushed, iclass 15, count 2 2006.225.07:48:20.35#ibcon#about to write, iclass 15, count 2 2006.225.07:48:20.35#ibcon#wrote, iclass 15, count 2 2006.225.07:48:20.35#ibcon#about to read 3, iclass 15, count 2 2006.225.07:48:20.37#ibcon#read 3, iclass 15, count 2 2006.225.07:48:20.37#ibcon#about to read 4, iclass 15, count 2 2006.225.07:48:20.37#ibcon#read 4, iclass 15, count 2 2006.225.07:48:20.37#ibcon#about to read 5, iclass 15, count 2 2006.225.07:48:20.37#ibcon#read 5, iclass 15, count 2 2006.225.07:48:20.37#ibcon#about to read 6, iclass 15, count 2 2006.225.07:48:20.37#ibcon#read 6, iclass 15, count 2 2006.225.07:48:20.37#ibcon#end of sib2, iclass 15, count 2 2006.225.07:48:20.37#ibcon#*mode == 0, iclass 15, count 2 2006.225.07:48:20.37#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.225.07:48:20.37#ibcon#[25=AT08-07\r\n] 2006.225.07:48:20.37#ibcon#*before write, iclass 15, count 2 2006.225.07:48:20.37#ibcon#enter sib2, iclass 15, count 2 2006.225.07:48:20.37#ibcon#flushed, iclass 15, count 2 2006.225.07:48:20.37#ibcon#about to write, iclass 15, count 2 2006.225.07:48:20.37#ibcon#wrote, iclass 15, count 2 2006.225.07:48:20.37#ibcon#about to read 3, iclass 15, count 2 2006.225.07:48:20.40#ibcon#read 3, iclass 15, count 2 2006.225.07:48:20.40#ibcon#about to read 4, iclass 15, count 2 2006.225.07:48:20.40#ibcon#read 4, iclass 15, count 2 2006.225.07:48:20.40#ibcon#about to read 5, iclass 15, count 2 2006.225.07:48:20.40#ibcon#read 5, iclass 15, count 2 2006.225.07:48:20.40#ibcon#about to read 6, iclass 15, count 2 2006.225.07:48:20.40#ibcon#read 6, iclass 15, count 2 2006.225.07:48:20.40#ibcon#end of sib2, iclass 15, count 2 2006.225.07:48:20.40#ibcon#*after write, iclass 15, count 2 2006.225.07:48:20.40#ibcon#*before return 0, iclass 15, count 2 2006.225.07:48:20.40#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:48:20.40#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.225.07:48:20.40#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.225.07:48:20.40#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:20.40#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:48:20.52#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:48:20.52#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:48:20.52#ibcon#enter wrdev, iclass 15, count 0 2006.225.07:48:20.52#ibcon#first serial, iclass 15, count 0 2006.225.07:48:20.52#ibcon#enter sib2, iclass 15, count 0 2006.225.07:48:20.52#ibcon#flushed, iclass 15, count 0 2006.225.07:48:20.52#ibcon#about to write, iclass 15, count 0 2006.225.07:48:20.52#ibcon#wrote, iclass 15, count 0 2006.225.07:48:20.52#ibcon#about to read 3, iclass 15, count 0 2006.225.07:48:20.54#ibcon#read 3, iclass 15, count 0 2006.225.07:48:20.54#ibcon#about to read 4, iclass 15, count 0 2006.225.07:48:20.54#ibcon#read 4, iclass 15, count 0 2006.225.07:48:20.54#ibcon#about to read 5, iclass 15, count 0 2006.225.07:48:20.54#ibcon#read 5, iclass 15, count 0 2006.225.07:48:20.54#ibcon#about to read 6, iclass 15, count 0 2006.225.07:48:20.54#ibcon#read 6, iclass 15, count 0 2006.225.07:48:20.54#ibcon#end of sib2, iclass 15, count 0 2006.225.07:48:20.54#ibcon#*mode == 0, iclass 15, count 0 2006.225.07:48:20.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.07:48:20.54#ibcon#[25=USB\r\n] 2006.225.07:48:20.54#ibcon#*before write, iclass 15, count 0 2006.225.07:48:20.54#ibcon#enter sib2, iclass 15, count 0 2006.225.07:48:20.54#ibcon#flushed, iclass 15, count 0 2006.225.07:48:20.54#ibcon#about to write, iclass 15, count 0 2006.225.07:48:20.54#ibcon#wrote, iclass 15, count 0 2006.225.07:48:20.54#ibcon#about to read 3, iclass 15, count 0 2006.225.07:48:20.57#ibcon#read 3, iclass 15, count 0 2006.225.07:48:20.57#ibcon#about to read 4, iclass 15, count 0 2006.225.07:48:20.57#ibcon#read 4, iclass 15, count 0 2006.225.07:48:20.57#ibcon#about to read 5, iclass 15, count 0 2006.225.07:48:20.57#ibcon#read 5, iclass 15, count 0 2006.225.07:48:20.57#ibcon#about to read 6, iclass 15, count 0 2006.225.07:48:20.57#ibcon#read 6, iclass 15, count 0 2006.225.07:48:20.57#ibcon#end of sib2, iclass 15, count 0 2006.225.07:48:20.57#ibcon#*after write, iclass 15, count 0 2006.225.07:48:20.57#ibcon#*before return 0, iclass 15, count 0 2006.225.07:48:20.57#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:48:20.57#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.225.07:48:20.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.07:48:20.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.07:48:20.57$vc4f8/vblo=1,632.99 2006.225.07:48:20.57#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.225.07:48:20.57#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.225.07:48:20.57#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:20.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:48:20.57#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:48:20.57#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:48:20.57#ibcon#enter wrdev, iclass 17, count 0 2006.225.07:48:20.57#ibcon#first serial, iclass 17, count 0 2006.225.07:48:20.57#ibcon#enter sib2, iclass 17, count 0 2006.225.07:48:20.57#ibcon#flushed, iclass 17, count 0 2006.225.07:48:20.57#ibcon#about to write, iclass 17, count 0 2006.225.07:48:20.57#ibcon#wrote, iclass 17, count 0 2006.225.07:48:20.57#ibcon#about to read 3, iclass 17, count 0 2006.225.07:48:20.59#ibcon#read 3, iclass 17, count 0 2006.225.07:48:20.59#ibcon#about to read 4, iclass 17, count 0 2006.225.07:48:20.59#ibcon#read 4, iclass 17, count 0 2006.225.07:48:20.59#ibcon#about to read 5, iclass 17, count 0 2006.225.07:48:20.59#ibcon#read 5, iclass 17, count 0 2006.225.07:48:20.59#ibcon#about to read 6, iclass 17, count 0 2006.225.07:48:20.59#ibcon#read 6, iclass 17, count 0 2006.225.07:48:20.59#ibcon#end of sib2, iclass 17, count 0 2006.225.07:48:20.59#ibcon#*mode == 0, iclass 17, count 0 2006.225.07:48:20.59#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.07:48:20.59#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:48:20.59#ibcon#*before write, iclass 17, count 0 2006.225.07:48:20.59#ibcon#enter sib2, iclass 17, count 0 2006.225.07:48:20.59#ibcon#flushed, iclass 17, count 0 2006.225.07:48:20.59#ibcon#about to write, iclass 17, count 0 2006.225.07:48:20.59#ibcon#wrote, iclass 17, count 0 2006.225.07:48:20.59#ibcon#about to read 3, iclass 17, count 0 2006.225.07:48:20.63#ibcon#read 3, iclass 17, count 0 2006.225.07:48:20.63#ibcon#about to read 4, iclass 17, count 0 2006.225.07:48:20.63#ibcon#read 4, iclass 17, count 0 2006.225.07:48:20.63#ibcon#about to read 5, iclass 17, count 0 2006.225.07:48:20.63#ibcon#read 5, iclass 17, count 0 2006.225.07:48:20.63#ibcon#about to read 6, iclass 17, count 0 2006.225.07:48:20.63#ibcon#read 6, iclass 17, count 0 2006.225.07:48:20.63#ibcon#end of sib2, iclass 17, count 0 2006.225.07:48:20.63#ibcon#*after write, iclass 17, count 0 2006.225.07:48:20.63#ibcon#*before return 0, iclass 17, count 0 2006.225.07:48:20.63#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:48:20.63#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.225.07:48:20.63#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.07:48:20.63#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.07:48:20.63$vc4f8/vb=1,4 2006.225.07:48:20.63#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.225.07:48:20.63#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.225.07:48:20.63#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:20.63#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:48:20.63#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:48:20.63#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:48:20.63#ibcon#enter wrdev, iclass 19, count 2 2006.225.07:48:20.63#ibcon#first serial, iclass 19, count 2 2006.225.07:48:20.63#ibcon#enter sib2, iclass 19, count 2 2006.225.07:48:20.63#ibcon#flushed, iclass 19, count 2 2006.225.07:48:20.63#ibcon#about to write, iclass 19, count 2 2006.225.07:48:20.63#ibcon#wrote, iclass 19, count 2 2006.225.07:48:20.63#ibcon#about to read 3, iclass 19, count 2 2006.225.07:48:20.65#ibcon#read 3, iclass 19, count 2 2006.225.07:48:20.65#ibcon#about to read 4, iclass 19, count 2 2006.225.07:48:20.65#ibcon#read 4, iclass 19, count 2 2006.225.07:48:20.65#ibcon#about to read 5, iclass 19, count 2 2006.225.07:48:20.65#ibcon#read 5, iclass 19, count 2 2006.225.07:48:20.65#ibcon#about to read 6, iclass 19, count 2 2006.225.07:48:20.65#ibcon#read 6, iclass 19, count 2 2006.225.07:48:20.65#ibcon#end of sib2, iclass 19, count 2 2006.225.07:48:20.65#ibcon#*mode == 0, iclass 19, count 2 2006.225.07:48:20.65#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.225.07:48:20.65#ibcon#[27=AT01-04\r\n] 2006.225.07:48:20.65#ibcon#*before write, iclass 19, count 2 2006.225.07:48:20.65#ibcon#enter sib2, iclass 19, count 2 2006.225.07:48:20.65#ibcon#flushed, iclass 19, count 2 2006.225.07:48:20.65#ibcon#about to write, iclass 19, count 2 2006.225.07:48:20.65#ibcon#wrote, iclass 19, count 2 2006.225.07:48:20.65#ibcon#about to read 3, iclass 19, count 2 2006.225.07:48:20.68#ibcon#read 3, iclass 19, count 2 2006.225.07:48:20.68#ibcon#about to read 4, iclass 19, count 2 2006.225.07:48:20.68#ibcon#read 4, iclass 19, count 2 2006.225.07:48:20.68#ibcon#about to read 5, iclass 19, count 2 2006.225.07:48:20.68#ibcon#read 5, iclass 19, count 2 2006.225.07:48:20.68#ibcon#about to read 6, iclass 19, count 2 2006.225.07:48:20.68#ibcon#read 6, iclass 19, count 2 2006.225.07:48:20.68#ibcon#end of sib2, iclass 19, count 2 2006.225.07:48:20.68#ibcon#*after write, iclass 19, count 2 2006.225.07:48:20.68#ibcon#*before return 0, iclass 19, count 2 2006.225.07:48:20.68#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:48:20.68#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.225.07:48:20.68#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.225.07:48:20.68#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:20.68#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:48:20.80#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:48:20.80#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:48:20.80#ibcon#enter wrdev, iclass 19, count 0 2006.225.07:48:20.80#ibcon#first serial, iclass 19, count 0 2006.225.07:48:20.80#ibcon#enter sib2, iclass 19, count 0 2006.225.07:48:20.80#ibcon#flushed, iclass 19, count 0 2006.225.07:48:20.80#ibcon#about to write, iclass 19, count 0 2006.225.07:48:20.80#ibcon#wrote, iclass 19, count 0 2006.225.07:48:20.80#ibcon#about to read 3, iclass 19, count 0 2006.225.07:48:20.82#ibcon#read 3, iclass 19, count 0 2006.225.07:48:20.82#ibcon#about to read 4, iclass 19, count 0 2006.225.07:48:20.82#ibcon#read 4, iclass 19, count 0 2006.225.07:48:20.82#ibcon#about to read 5, iclass 19, count 0 2006.225.07:48:20.82#ibcon#read 5, iclass 19, count 0 2006.225.07:48:20.82#ibcon#about to read 6, iclass 19, count 0 2006.225.07:48:20.82#ibcon#read 6, iclass 19, count 0 2006.225.07:48:20.82#ibcon#end of sib2, iclass 19, count 0 2006.225.07:48:20.82#ibcon#*mode == 0, iclass 19, count 0 2006.225.07:48:20.82#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.07:48:20.82#ibcon#[27=USB\r\n] 2006.225.07:48:20.82#ibcon#*before write, iclass 19, count 0 2006.225.07:48:20.82#ibcon#enter sib2, iclass 19, count 0 2006.225.07:48:20.82#ibcon#flushed, iclass 19, count 0 2006.225.07:48:20.82#ibcon#about to write, iclass 19, count 0 2006.225.07:48:20.82#ibcon#wrote, iclass 19, count 0 2006.225.07:48:20.82#ibcon#about to read 3, iclass 19, count 0 2006.225.07:48:20.85#ibcon#read 3, iclass 19, count 0 2006.225.07:48:20.85#ibcon#about to read 4, iclass 19, count 0 2006.225.07:48:20.85#ibcon#read 4, iclass 19, count 0 2006.225.07:48:20.85#ibcon#about to read 5, iclass 19, count 0 2006.225.07:48:20.85#ibcon#read 5, iclass 19, count 0 2006.225.07:48:20.85#ibcon#about to read 6, iclass 19, count 0 2006.225.07:48:20.85#ibcon#read 6, iclass 19, count 0 2006.225.07:48:20.85#ibcon#end of sib2, iclass 19, count 0 2006.225.07:48:20.85#ibcon#*after write, iclass 19, count 0 2006.225.07:48:20.85#ibcon#*before return 0, iclass 19, count 0 2006.225.07:48:20.85#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:48:20.85#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.225.07:48:20.85#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.07:48:20.85#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.07:48:20.85$vc4f8/vblo=2,640.99 2006.225.07:48:20.85#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.225.07:48:20.85#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.225.07:48:20.85#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:20.85#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:48:20.85#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:48:20.85#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:48:20.85#ibcon#enter wrdev, iclass 21, count 0 2006.225.07:48:20.85#ibcon#first serial, iclass 21, count 0 2006.225.07:48:20.85#ibcon#enter sib2, iclass 21, count 0 2006.225.07:48:20.85#ibcon#flushed, iclass 21, count 0 2006.225.07:48:20.85#ibcon#about to write, iclass 21, count 0 2006.225.07:48:20.85#ibcon#wrote, iclass 21, count 0 2006.225.07:48:20.85#ibcon#about to read 3, iclass 21, count 0 2006.225.07:48:20.87#ibcon#read 3, iclass 21, count 0 2006.225.07:48:20.87#ibcon#about to read 4, iclass 21, count 0 2006.225.07:48:20.87#ibcon#read 4, iclass 21, count 0 2006.225.07:48:20.87#ibcon#about to read 5, iclass 21, count 0 2006.225.07:48:20.87#ibcon#read 5, iclass 21, count 0 2006.225.07:48:20.87#ibcon#about to read 6, iclass 21, count 0 2006.225.07:48:20.87#ibcon#read 6, iclass 21, count 0 2006.225.07:48:20.87#ibcon#end of sib2, iclass 21, count 0 2006.225.07:48:20.87#ibcon#*mode == 0, iclass 21, count 0 2006.225.07:48:20.87#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.07:48:20.87#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:48:20.87#ibcon#*before write, iclass 21, count 0 2006.225.07:48:20.87#ibcon#enter sib2, iclass 21, count 0 2006.225.07:48:20.87#ibcon#flushed, iclass 21, count 0 2006.225.07:48:20.87#ibcon#about to write, iclass 21, count 0 2006.225.07:48:20.87#ibcon#wrote, iclass 21, count 0 2006.225.07:48:20.87#ibcon#about to read 3, iclass 21, count 0 2006.225.07:48:20.91#ibcon#read 3, iclass 21, count 0 2006.225.07:48:20.91#ibcon#about to read 4, iclass 21, count 0 2006.225.07:48:20.91#ibcon#read 4, iclass 21, count 0 2006.225.07:48:20.91#ibcon#about to read 5, iclass 21, count 0 2006.225.07:48:20.91#ibcon#read 5, iclass 21, count 0 2006.225.07:48:20.91#ibcon#about to read 6, iclass 21, count 0 2006.225.07:48:20.91#ibcon#read 6, iclass 21, count 0 2006.225.07:48:20.91#ibcon#end of sib2, iclass 21, count 0 2006.225.07:48:20.91#ibcon#*after write, iclass 21, count 0 2006.225.07:48:20.91#ibcon#*before return 0, iclass 21, count 0 2006.225.07:48:20.91#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:48:20.91#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.225.07:48:20.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.07:48:20.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.07:48:20.91$vc4f8/vb=2,4 2006.225.07:48:20.91#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.225.07:48:20.91#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.225.07:48:20.91#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:20.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:48:20.97#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:48:20.97#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:48:20.97#ibcon#enter wrdev, iclass 23, count 2 2006.225.07:48:20.97#ibcon#first serial, iclass 23, count 2 2006.225.07:48:20.97#ibcon#enter sib2, iclass 23, count 2 2006.225.07:48:20.97#ibcon#flushed, iclass 23, count 2 2006.225.07:48:20.97#ibcon#about to write, iclass 23, count 2 2006.225.07:48:20.97#ibcon#wrote, iclass 23, count 2 2006.225.07:48:20.97#ibcon#about to read 3, iclass 23, count 2 2006.225.07:48:20.99#ibcon#read 3, iclass 23, count 2 2006.225.07:48:20.99#ibcon#about to read 4, iclass 23, count 2 2006.225.07:48:20.99#ibcon#read 4, iclass 23, count 2 2006.225.07:48:20.99#ibcon#about to read 5, iclass 23, count 2 2006.225.07:48:20.99#ibcon#read 5, iclass 23, count 2 2006.225.07:48:20.99#ibcon#about to read 6, iclass 23, count 2 2006.225.07:48:20.99#ibcon#read 6, iclass 23, count 2 2006.225.07:48:20.99#ibcon#end of sib2, iclass 23, count 2 2006.225.07:48:20.99#ibcon#*mode == 0, iclass 23, count 2 2006.225.07:48:20.99#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.225.07:48:20.99#ibcon#[27=AT02-04\r\n] 2006.225.07:48:20.99#ibcon#*before write, iclass 23, count 2 2006.225.07:48:20.99#ibcon#enter sib2, iclass 23, count 2 2006.225.07:48:20.99#ibcon#flushed, iclass 23, count 2 2006.225.07:48:20.99#ibcon#about to write, iclass 23, count 2 2006.225.07:48:20.99#ibcon#wrote, iclass 23, count 2 2006.225.07:48:20.99#ibcon#about to read 3, iclass 23, count 2 2006.225.07:48:21.01#abcon#<5=/06 3.0 5.7 28.18 711003.4\r\n> 2006.225.07:48:21.02#ibcon#read 3, iclass 23, count 2 2006.225.07:48:21.02#ibcon#about to read 4, iclass 23, count 2 2006.225.07:48:21.02#ibcon#read 4, iclass 23, count 2 2006.225.07:48:21.02#ibcon#about to read 5, iclass 23, count 2 2006.225.07:48:21.02#ibcon#read 5, iclass 23, count 2 2006.225.07:48:21.02#ibcon#about to read 6, iclass 23, count 2 2006.225.07:48:21.02#ibcon#read 6, iclass 23, count 2 2006.225.07:48:21.02#ibcon#end of sib2, iclass 23, count 2 2006.225.07:48:21.02#ibcon#*after write, iclass 23, count 2 2006.225.07:48:21.02#ibcon#*before return 0, iclass 23, count 2 2006.225.07:48:21.02#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:48:21.02#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.225.07:48:21.02#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.225.07:48:21.02#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:21.02#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:48:21.03#abcon#{5=INTERFACE CLEAR} 2006.225.07:48:21.09#abcon#[5=S1D000X0/0*\r\n] 2006.225.07:48:21.14#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:48:21.14#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:48:21.14#ibcon#enter wrdev, iclass 23, count 0 2006.225.07:48:21.14#ibcon#first serial, iclass 23, count 0 2006.225.07:48:21.14#ibcon#enter sib2, iclass 23, count 0 2006.225.07:48:21.14#ibcon#flushed, iclass 23, count 0 2006.225.07:48:21.14#ibcon#about to write, iclass 23, count 0 2006.225.07:48:21.14#ibcon#wrote, iclass 23, count 0 2006.225.07:48:21.14#ibcon#about to read 3, iclass 23, count 0 2006.225.07:48:21.16#ibcon#read 3, iclass 23, count 0 2006.225.07:48:21.16#ibcon#about to read 4, iclass 23, count 0 2006.225.07:48:21.16#ibcon#read 4, iclass 23, count 0 2006.225.07:48:21.16#ibcon#about to read 5, iclass 23, count 0 2006.225.07:48:21.16#ibcon#read 5, iclass 23, count 0 2006.225.07:48:21.16#ibcon#about to read 6, iclass 23, count 0 2006.225.07:48:21.16#ibcon#read 6, iclass 23, count 0 2006.225.07:48:21.16#ibcon#end of sib2, iclass 23, count 0 2006.225.07:48:21.16#ibcon#*mode == 0, iclass 23, count 0 2006.225.07:48:21.16#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.07:48:21.16#ibcon#[27=USB\r\n] 2006.225.07:48:21.16#ibcon#*before write, iclass 23, count 0 2006.225.07:48:21.16#ibcon#enter sib2, iclass 23, count 0 2006.225.07:48:21.16#ibcon#flushed, iclass 23, count 0 2006.225.07:48:21.16#ibcon#about to write, iclass 23, count 0 2006.225.07:48:21.16#ibcon#wrote, iclass 23, count 0 2006.225.07:48:21.16#ibcon#about to read 3, iclass 23, count 0 2006.225.07:48:21.19#ibcon#read 3, iclass 23, count 0 2006.225.07:48:21.19#ibcon#about to read 4, iclass 23, count 0 2006.225.07:48:21.19#ibcon#read 4, iclass 23, count 0 2006.225.07:48:21.19#ibcon#about to read 5, iclass 23, count 0 2006.225.07:48:21.19#ibcon#read 5, iclass 23, count 0 2006.225.07:48:21.19#ibcon#about to read 6, iclass 23, count 0 2006.225.07:48:21.19#ibcon#read 6, iclass 23, count 0 2006.225.07:48:21.19#ibcon#end of sib2, iclass 23, count 0 2006.225.07:48:21.19#ibcon#*after write, iclass 23, count 0 2006.225.07:48:21.19#ibcon#*before return 0, iclass 23, count 0 2006.225.07:48:21.19#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:48:21.19#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.225.07:48:21.19#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.07:48:21.19#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.07:48:21.19$vc4f8/vblo=3,656.99 2006.225.07:48:21.19#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.07:48:21.19#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.07:48:21.19#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:21.19#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:48:21.19#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:48:21.19#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:48:21.19#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:48:21.19#ibcon#first serial, iclass 29, count 0 2006.225.07:48:21.19#ibcon#enter sib2, iclass 29, count 0 2006.225.07:48:21.19#ibcon#flushed, iclass 29, count 0 2006.225.07:48:21.19#ibcon#about to write, iclass 29, count 0 2006.225.07:48:21.19#ibcon#wrote, iclass 29, count 0 2006.225.07:48:21.19#ibcon#about to read 3, iclass 29, count 0 2006.225.07:48:21.21#ibcon#read 3, iclass 29, count 0 2006.225.07:48:21.21#ibcon#about to read 4, iclass 29, count 0 2006.225.07:48:21.21#ibcon#read 4, iclass 29, count 0 2006.225.07:48:21.21#ibcon#about to read 5, iclass 29, count 0 2006.225.07:48:21.21#ibcon#read 5, iclass 29, count 0 2006.225.07:48:21.21#ibcon#about to read 6, iclass 29, count 0 2006.225.07:48:21.21#ibcon#read 6, iclass 29, count 0 2006.225.07:48:21.21#ibcon#end of sib2, iclass 29, count 0 2006.225.07:48:21.21#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:48:21.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:48:21.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:48:21.21#ibcon#*before write, iclass 29, count 0 2006.225.07:48:21.21#ibcon#enter sib2, iclass 29, count 0 2006.225.07:48:21.21#ibcon#flushed, iclass 29, count 0 2006.225.07:48:21.21#ibcon#about to write, iclass 29, count 0 2006.225.07:48:21.21#ibcon#wrote, iclass 29, count 0 2006.225.07:48:21.21#ibcon#about to read 3, iclass 29, count 0 2006.225.07:48:21.25#ibcon#read 3, iclass 29, count 0 2006.225.07:48:21.25#ibcon#about to read 4, iclass 29, count 0 2006.225.07:48:21.25#ibcon#read 4, iclass 29, count 0 2006.225.07:48:21.25#ibcon#about to read 5, iclass 29, count 0 2006.225.07:48:21.25#ibcon#read 5, iclass 29, count 0 2006.225.07:48:21.25#ibcon#about to read 6, iclass 29, count 0 2006.225.07:48:21.25#ibcon#read 6, iclass 29, count 0 2006.225.07:48:21.25#ibcon#end of sib2, iclass 29, count 0 2006.225.07:48:21.25#ibcon#*after write, iclass 29, count 0 2006.225.07:48:21.25#ibcon#*before return 0, iclass 29, count 0 2006.225.07:48:21.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:48:21.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:48:21.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:48:21.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:48:21.25$vc4f8/vb=3,4 2006.225.07:48:21.25#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.07:48:21.25#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.07:48:21.25#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:21.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:48:21.31#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:48:21.31#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:48:21.31#ibcon#enter wrdev, iclass 31, count 2 2006.225.07:48:21.31#ibcon#first serial, iclass 31, count 2 2006.225.07:48:21.31#ibcon#enter sib2, iclass 31, count 2 2006.225.07:48:21.31#ibcon#flushed, iclass 31, count 2 2006.225.07:48:21.31#ibcon#about to write, iclass 31, count 2 2006.225.07:48:21.31#ibcon#wrote, iclass 31, count 2 2006.225.07:48:21.31#ibcon#about to read 3, iclass 31, count 2 2006.225.07:48:21.33#ibcon#read 3, iclass 31, count 2 2006.225.07:48:21.33#ibcon#about to read 4, iclass 31, count 2 2006.225.07:48:21.33#ibcon#read 4, iclass 31, count 2 2006.225.07:48:21.33#ibcon#about to read 5, iclass 31, count 2 2006.225.07:48:21.33#ibcon#read 5, iclass 31, count 2 2006.225.07:48:21.33#ibcon#about to read 6, iclass 31, count 2 2006.225.07:48:21.33#ibcon#read 6, iclass 31, count 2 2006.225.07:48:21.33#ibcon#end of sib2, iclass 31, count 2 2006.225.07:48:21.33#ibcon#*mode == 0, iclass 31, count 2 2006.225.07:48:21.33#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.07:48:21.33#ibcon#[27=AT03-04\r\n] 2006.225.07:48:21.33#ibcon#*before write, iclass 31, count 2 2006.225.07:48:21.33#ibcon#enter sib2, iclass 31, count 2 2006.225.07:48:21.33#ibcon#flushed, iclass 31, count 2 2006.225.07:48:21.33#ibcon#about to write, iclass 31, count 2 2006.225.07:48:21.33#ibcon#wrote, iclass 31, count 2 2006.225.07:48:21.33#ibcon#about to read 3, iclass 31, count 2 2006.225.07:48:21.36#ibcon#read 3, iclass 31, count 2 2006.225.07:48:21.36#ibcon#about to read 4, iclass 31, count 2 2006.225.07:48:21.36#ibcon#read 4, iclass 31, count 2 2006.225.07:48:21.36#ibcon#about to read 5, iclass 31, count 2 2006.225.07:48:21.36#ibcon#read 5, iclass 31, count 2 2006.225.07:48:21.36#ibcon#about to read 6, iclass 31, count 2 2006.225.07:48:21.36#ibcon#read 6, iclass 31, count 2 2006.225.07:48:21.36#ibcon#end of sib2, iclass 31, count 2 2006.225.07:48:21.36#ibcon#*after write, iclass 31, count 2 2006.225.07:48:21.36#ibcon#*before return 0, iclass 31, count 2 2006.225.07:48:21.36#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:48:21.36#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.07:48:21.36#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.07:48:21.36#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:21.36#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:48:21.48#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:48:21.48#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:48:21.48#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:48:21.48#ibcon#first serial, iclass 31, count 0 2006.225.07:48:21.48#ibcon#enter sib2, iclass 31, count 0 2006.225.07:48:21.48#ibcon#flushed, iclass 31, count 0 2006.225.07:48:21.48#ibcon#about to write, iclass 31, count 0 2006.225.07:48:21.48#ibcon#wrote, iclass 31, count 0 2006.225.07:48:21.48#ibcon#about to read 3, iclass 31, count 0 2006.225.07:48:21.50#ibcon#read 3, iclass 31, count 0 2006.225.07:48:21.50#ibcon#about to read 4, iclass 31, count 0 2006.225.07:48:21.50#ibcon#read 4, iclass 31, count 0 2006.225.07:48:21.50#ibcon#about to read 5, iclass 31, count 0 2006.225.07:48:21.50#ibcon#read 5, iclass 31, count 0 2006.225.07:48:21.50#ibcon#about to read 6, iclass 31, count 0 2006.225.07:48:21.50#ibcon#read 6, iclass 31, count 0 2006.225.07:48:21.50#ibcon#end of sib2, iclass 31, count 0 2006.225.07:48:21.50#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:48:21.50#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:48:21.50#ibcon#[27=USB\r\n] 2006.225.07:48:21.50#ibcon#*before write, iclass 31, count 0 2006.225.07:48:21.50#ibcon#enter sib2, iclass 31, count 0 2006.225.07:48:21.50#ibcon#flushed, iclass 31, count 0 2006.225.07:48:21.50#ibcon#about to write, iclass 31, count 0 2006.225.07:48:21.50#ibcon#wrote, iclass 31, count 0 2006.225.07:48:21.50#ibcon#about to read 3, iclass 31, count 0 2006.225.07:48:21.53#ibcon#read 3, iclass 31, count 0 2006.225.07:48:21.53#ibcon#about to read 4, iclass 31, count 0 2006.225.07:48:21.53#ibcon#read 4, iclass 31, count 0 2006.225.07:48:21.53#ibcon#about to read 5, iclass 31, count 0 2006.225.07:48:21.53#ibcon#read 5, iclass 31, count 0 2006.225.07:48:21.53#ibcon#about to read 6, iclass 31, count 0 2006.225.07:48:21.53#ibcon#read 6, iclass 31, count 0 2006.225.07:48:21.53#ibcon#end of sib2, iclass 31, count 0 2006.225.07:48:21.53#ibcon#*after write, iclass 31, count 0 2006.225.07:48:21.53#ibcon#*before return 0, iclass 31, count 0 2006.225.07:48:21.53#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:48:21.53#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.07:48:21.53#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:48:21.53#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:48:21.53$vc4f8/vblo=4,712.99 2006.225.07:48:21.53#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.07:48:21.53#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.07:48:21.53#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:21.53#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:48:21.53#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:48:21.53#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:48:21.53#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:48:21.53#ibcon#first serial, iclass 33, count 0 2006.225.07:48:21.53#ibcon#enter sib2, iclass 33, count 0 2006.225.07:48:21.53#ibcon#flushed, iclass 33, count 0 2006.225.07:48:21.53#ibcon#about to write, iclass 33, count 0 2006.225.07:48:21.53#ibcon#wrote, iclass 33, count 0 2006.225.07:48:21.53#ibcon#about to read 3, iclass 33, count 0 2006.225.07:48:21.55#ibcon#read 3, iclass 33, count 0 2006.225.07:48:21.55#ibcon#about to read 4, iclass 33, count 0 2006.225.07:48:21.55#ibcon#read 4, iclass 33, count 0 2006.225.07:48:21.55#ibcon#about to read 5, iclass 33, count 0 2006.225.07:48:21.55#ibcon#read 5, iclass 33, count 0 2006.225.07:48:21.55#ibcon#about to read 6, iclass 33, count 0 2006.225.07:48:21.55#ibcon#read 6, iclass 33, count 0 2006.225.07:48:21.55#ibcon#end of sib2, iclass 33, count 0 2006.225.07:48:21.55#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:48:21.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:48:21.55#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:48:21.55#ibcon#*before write, iclass 33, count 0 2006.225.07:48:21.55#ibcon#enter sib2, iclass 33, count 0 2006.225.07:48:21.55#ibcon#flushed, iclass 33, count 0 2006.225.07:48:21.55#ibcon#about to write, iclass 33, count 0 2006.225.07:48:21.55#ibcon#wrote, iclass 33, count 0 2006.225.07:48:21.55#ibcon#about to read 3, iclass 33, count 0 2006.225.07:48:21.59#ibcon#read 3, iclass 33, count 0 2006.225.07:48:21.59#ibcon#about to read 4, iclass 33, count 0 2006.225.07:48:21.59#ibcon#read 4, iclass 33, count 0 2006.225.07:48:21.59#ibcon#about to read 5, iclass 33, count 0 2006.225.07:48:21.59#ibcon#read 5, iclass 33, count 0 2006.225.07:48:21.59#ibcon#about to read 6, iclass 33, count 0 2006.225.07:48:21.59#ibcon#read 6, iclass 33, count 0 2006.225.07:48:21.59#ibcon#end of sib2, iclass 33, count 0 2006.225.07:48:21.59#ibcon#*after write, iclass 33, count 0 2006.225.07:48:21.59#ibcon#*before return 0, iclass 33, count 0 2006.225.07:48:21.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:48:21.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.07:48:21.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:48:21.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:48:21.59$vc4f8/vb=4,4 2006.225.07:48:21.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.07:48:21.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.07:48:21.59#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:21.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:48:21.65#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:48:21.65#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:48:21.65#ibcon#enter wrdev, iclass 35, count 2 2006.225.07:48:21.65#ibcon#first serial, iclass 35, count 2 2006.225.07:48:21.65#ibcon#enter sib2, iclass 35, count 2 2006.225.07:48:21.65#ibcon#flushed, iclass 35, count 2 2006.225.07:48:21.65#ibcon#about to write, iclass 35, count 2 2006.225.07:48:21.65#ibcon#wrote, iclass 35, count 2 2006.225.07:48:21.65#ibcon#about to read 3, iclass 35, count 2 2006.225.07:48:21.67#ibcon#read 3, iclass 35, count 2 2006.225.07:48:21.67#ibcon#about to read 4, iclass 35, count 2 2006.225.07:48:21.67#ibcon#read 4, iclass 35, count 2 2006.225.07:48:21.67#ibcon#about to read 5, iclass 35, count 2 2006.225.07:48:21.67#ibcon#read 5, iclass 35, count 2 2006.225.07:48:21.67#ibcon#about to read 6, iclass 35, count 2 2006.225.07:48:21.67#ibcon#read 6, iclass 35, count 2 2006.225.07:48:21.67#ibcon#end of sib2, iclass 35, count 2 2006.225.07:48:21.67#ibcon#*mode == 0, iclass 35, count 2 2006.225.07:48:21.67#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.07:48:21.67#ibcon#[27=AT04-04\r\n] 2006.225.07:48:21.67#ibcon#*before write, iclass 35, count 2 2006.225.07:48:21.67#ibcon#enter sib2, iclass 35, count 2 2006.225.07:48:21.67#ibcon#flushed, iclass 35, count 2 2006.225.07:48:21.67#ibcon#about to write, iclass 35, count 2 2006.225.07:48:21.67#ibcon#wrote, iclass 35, count 2 2006.225.07:48:21.67#ibcon#about to read 3, iclass 35, count 2 2006.225.07:48:21.70#ibcon#read 3, iclass 35, count 2 2006.225.07:48:21.70#ibcon#about to read 4, iclass 35, count 2 2006.225.07:48:21.70#ibcon#read 4, iclass 35, count 2 2006.225.07:48:21.70#ibcon#about to read 5, iclass 35, count 2 2006.225.07:48:21.70#ibcon#read 5, iclass 35, count 2 2006.225.07:48:21.70#ibcon#about to read 6, iclass 35, count 2 2006.225.07:48:21.70#ibcon#read 6, iclass 35, count 2 2006.225.07:48:21.70#ibcon#end of sib2, iclass 35, count 2 2006.225.07:48:21.70#ibcon#*after write, iclass 35, count 2 2006.225.07:48:21.70#ibcon#*before return 0, iclass 35, count 2 2006.225.07:48:21.70#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:48:21.70#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.07:48:21.70#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.07:48:21.70#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:21.70#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:48:21.82#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:48:21.82#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:48:21.82#ibcon#enter wrdev, iclass 35, count 0 2006.225.07:48:21.82#ibcon#first serial, iclass 35, count 0 2006.225.07:48:21.82#ibcon#enter sib2, iclass 35, count 0 2006.225.07:48:21.82#ibcon#flushed, iclass 35, count 0 2006.225.07:48:21.82#ibcon#about to write, iclass 35, count 0 2006.225.07:48:21.82#ibcon#wrote, iclass 35, count 0 2006.225.07:48:21.82#ibcon#about to read 3, iclass 35, count 0 2006.225.07:48:21.84#ibcon#read 3, iclass 35, count 0 2006.225.07:48:21.84#ibcon#about to read 4, iclass 35, count 0 2006.225.07:48:21.84#ibcon#read 4, iclass 35, count 0 2006.225.07:48:21.84#ibcon#about to read 5, iclass 35, count 0 2006.225.07:48:21.84#ibcon#read 5, iclass 35, count 0 2006.225.07:48:21.84#ibcon#about to read 6, iclass 35, count 0 2006.225.07:48:21.84#ibcon#read 6, iclass 35, count 0 2006.225.07:48:21.84#ibcon#end of sib2, iclass 35, count 0 2006.225.07:48:21.84#ibcon#*mode == 0, iclass 35, count 0 2006.225.07:48:21.84#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.07:48:21.84#ibcon#[27=USB\r\n] 2006.225.07:48:21.84#ibcon#*before write, iclass 35, count 0 2006.225.07:48:21.84#ibcon#enter sib2, iclass 35, count 0 2006.225.07:48:21.84#ibcon#flushed, iclass 35, count 0 2006.225.07:48:21.84#ibcon#about to write, iclass 35, count 0 2006.225.07:48:21.84#ibcon#wrote, iclass 35, count 0 2006.225.07:48:21.84#ibcon#about to read 3, iclass 35, count 0 2006.225.07:48:21.87#ibcon#read 3, iclass 35, count 0 2006.225.07:48:21.87#ibcon#about to read 4, iclass 35, count 0 2006.225.07:48:21.87#ibcon#read 4, iclass 35, count 0 2006.225.07:48:21.87#ibcon#about to read 5, iclass 35, count 0 2006.225.07:48:21.87#ibcon#read 5, iclass 35, count 0 2006.225.07:48:21.87#ibcon#about to read 6, iclass 35, count 0 2006.225.07:48:21.87#ibcon#read 6, iclass 35, count 0 2006.225.07:48:21.87#ibcon#end of sib2, iclass 35, count 0 2006.225.07:48:21.87#ibcon#*after write, iclass 35, count 0 2006.225.07:48:21.87#ibcon#*before return 0, iclass 35, count 0 2006.225.07:48:21.87#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:48:21.87#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.07:48:21.87#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.07:48:21.87#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.07:48:21.87$vc4f8/vblo=5,744.99 2006.225.07:48:21.87#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.07:48:21.87#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.07:48:21.87#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:21.87#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:48:21.87#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:48:21.87#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:48:21.87#ibcon#enter wrdev, iclass 37, count 0 2006.225.07:48:21.87#ibcon#first serial, iclass 37, count 0 2006.225.07:48:21.87#ibcon#enter sib2, iclass 37, count 0 2006.225.07:48:21.87#ibcon#flushed, iclass 37, count 0 2006.225.07:48:21.87#ibcon#about to write, iclass 37, count 0 2006.225.07:48:21.87#ibcon#wrote, iclass 37, count 0 2006.225.07:48:21.87#ibcon#about to read 3, iclass 37, count 0 2006.225.07:48:21.89#ibcon#read 3, iclass 37, count 0 2006.225.07:48:21.89#ibcon#about to read 4, iclass 37, count 0 2006.225.07:48:21.89#ibcon#read 4, iclass 37, count 0 2006.225.07:48:21.89#ibcon#about to read 5, iclass 37, count 0 2006.225.07:48:21.89#ibcon#read 5, iclass 37, count 0 2006.225.07:48:21.89#ibcon#about to read 6, iclass 37, count 0 2006.225.07:48:21.89#ibcon#read 6, iclass 37, count 0 2006.225.07:48:21.89#ibcon#end of sib2, iclass 37, count 0 2006.225.07:48:21.89#ibcon#*mode == 0, iclass 37, count 0 2006.225.07:48:21.89#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.07:48:21.89#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:48:21.89#ibcon#*before write, iclass 37, count 0 2006.225.07:48:21.89#ibcon#enter sib2, iclass 37, count 0 2006.225.07:48:21.89#ibcon#flushed, iclass 37, count 0 2006.225.07:48:21.89#ibcon#about to write, iclass 37, count 0 2006.225.07:48:21.89#ibcon#wrote, iclass 37, count 0 2006.225.07:48:21.89#ibcon#about to read 3, iclass 37, count 0 2006.225.07:48:21.93#ibcon#read 3, iclass 37, count 0 2006.225.07:48:21.93#ibcon#about to read 4, iclass 37, count 0 2006.225.07:48:21.93#ibcon#read 4, iclass 37, count 0 2006.225.07:48:21.93#ibcon#about to read 5, iclass 37, count 0 2006.225.07:48:21.93#ibcon#read 5, iclass 37, count 0 2006.225.07:48:21.93#ibcon#about to read 6, iclass 37, count 0 2006.225.07:48:21.93#ibcon#read 6, iclass 37, count 0 2006.225.07:48:21.93#ibcon#end of sib2, iclass 37, count 0 2006.225.07:48:21.93#ibcon#*after write, iclass 37, count 0 2006.225.07:48:21.93#ibcon#*before return 0, iclass 37, count 0 2006.225.07:48:21.93#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:48:21.93#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.07:48:21.93#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.07:48:21.93#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.07:48:21.93$vc4f8/vb=5,4 2006.225.07:48:21.93#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.07:48:21.93#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.07:48:21.93#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:21.93#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:48:21.99#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:48:21.99#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:48:21.99#ibcon#enter wrdev, iclass 39, count 2 2006.225.07:48:21.99#ibcon#first serial, iclass 39, count 2 2006.225.07:48:21.99#ibcon#enter sib2, iclass 39, count 2 2006.225.07:48:21.99#ibcon#flushed, iclass 39, count 2 2006.225.07:48:21.99#ibcon#about to write, iclass 39, count 2 2006.225.07:48:21.99#ibcon#wrote, iclass 39, count 2 2006.225.07:48:21.99#ibcon#about to read 3, iclass 39, count 2 2006.225.07:48:22.01#ibcon#read 3, iclass 39, count 2 2006.225.07:48:22.01#ibcon#about to read 4, iclass 39, count 2 2006.225.07:48:22.01#ibcon#read 4, iclass 39, count 2 2006.225.07:48:22.01#ibcon#about to read 5, iclass 39, count 2 2006.225.07:48:22.01#ibcon#read 5, iclass 39, count 2 2006.225.07:48:22.01#ibcon#about to read 6, iclass 39, count 2 2006.225.07:48:22.01#ibcon#read 6, iclass 39, count 2 2006.225.07:48:22.01#ibcon#end of sib2, iclass 39, count 2 2006.225.07:48:22.01#ibcon#*mode == 0, iclass 39, count 2 2006.225.07:48:22.01#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.07:48:22.01#ibcon#[27=AT05-04\r\n] 2006.225.07:48:22.01#ibcon#*before write, iclass 39, count 2 2006.225.07:48:22.01#ibcon#enter sib2, iclass 39, count 2 2006.225.07:48:22.01#ibcon#flushed, iclass 39, count 2 2006.225.07:48:22.01#ibcon#about to write, iclass 39, count 2 2006.225.07:48:22.01#ibcon#wrote, iclass 39, count 2 2006.225.07:48:22.01#ibcon#about to read 3, iclass 39, count 2 2006.225.07:48:22.04#ibcon#read 3, iclass 39, count 2 2006.225.07:48:22.04#ibcon#about to read 4, iclass 39, count 2 2006.225.07:48:22.04#ibcon#read 4, iclass 39, count 2 2006.225.07:48:22.04#ibcon#about to read 5, iclass 39, count 2 2006.225.07:48:22.04#ibcon#read 5, iclass 39, count 2 2006.225.07:48:22.04#ibcon#about to read 6, iclass 39, count 2 2006.225.07:48:22.04#ibcon#read 6, iclass 39, count 2 2006.225.07:48:22.04#ibcon#end of sib2, iclass 39, count 2 2006.225.07:48:22.04#ibcon#*after write, iclass 39, count 2 2006.225.07:48:22.04#ibcon#*before return 0, iclass 39, count 2 2006.225.07:48:22.04#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:48:22.04#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.07:48:22.04#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.07:48:22.04#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:22.04#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:48:22.16#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:48:22.16#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:48:22.16#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:48:22.16#ibcon#first serial, iclass 39, count 0 2006.225.07:48:22.16#ibcon#enter sib2, iclass 39, count 0 2006.225.07:48:22.16#ibcon#flushed, iclass 39, count 0 2006.225.07:48:22.16#ibcon#about to write, iclass 39, count 0 2006.225.07:48:22.16#ibcon#wrote, iclass 39, count 0 2006.225.07:48:22.16#ibcon#about to read 3, iclass 39, count 0 2006.225.07:48:22.18#ibcon#read 3, iclass 39, count 0 2006.225.07:48:22.18#ibcon#about to read 4, iclass 39, count 0 2006.225.07:48:22.18#ibcon#read 4, iclass 39, count 0 2006.225.07:48:22.18#ibcon#about to read 5, iclass 39, count 0 2006.225.07:48:22.18#ibcon#read 5, iclass 39, count 0 2006.225.07:48:22.18#ibcon#about to read 6, iclass 39, count 0 2006.225.07:48:22.18#ibcon#read 6, iclass 39, count 0 2006.225.07:48:22.18#ibcon#end of sib2, iclass 39, count 0 2006.225.07:48:22.18#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:48:22.18#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:48:22.18#ibcon#[27=USB\r\n] 2006.225.07:48:22.18#ibcon#*before write, iclass 39, count 0 2006.225.07:48:22.18#ibcon#enter sib2, iclass 39, count 0 2006.225.07:48:22.18#ibcon#flushed, iclass 39, count 0 2006.225.07:48:22.18#ibcon#about to write, iclass 39, count 0 2006.225.07:48:22.18#ibcon#wrote, iclass 39, count 0 2006.225.07:48:22.18#ibcon#about to read 3, iclass 39, count 0 2006.225.07:48:22.21#ibcon#read 3, iclass 39, count 0 2006.225.07:48:22.21#ibcon#about to read 4, iclass 39, count 0 2006.225.07:48:22.21#ibcon#read 4, iclass 39, count 0 2006.225.07:48:22.21#ibcon#about to read 5, iclass 39, count 0 2006.225.07:48:22.21#ibcon#read 5, iclass 39, count 0 2006.225.07:48:22.21#ibcon#about to read 6, iclass 39, count 0 2006.225.07:48:22.21#ibcon#read 6, iclass 39, count 0 2006.225.07:48:22.21#ibcon#end of sib2, iclass 39, count 0 2006.225.07:48:22.21#ibcon#*after write, iclass 39, count 0 2006.225.07:48:22.21#ibcon#*before return 0, iclass 39, count 0 2006.225.07:48:22.21#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:48:22.21#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.07:48:22.21#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:48:22.21#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:48:22.21$vc4f8/vblo=6,752.99 2006.225.07:48:22.21#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.07:48:22.21#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.07:48:22.21#ibcon#ireg 17 cls_cnt 0 2006.225.07:48:22.21#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:48:22.21#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:48:22.21#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:48:22.21#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:48:22.21#ibcon#first serial, iclass 3, count 0 2006.225.07:48:22.21#ibcon#enter sib2, iclass 3, count 0 2006.225.07:48:22.21#ibcon#flushed, iclass 3, count 0 2006.225.07:48:22.21#ibcon#about to write, iclass 3, count 0 2006.225.07:48:22.21#ibcon#wrote, iclass 3, count 0 2006.225.07:48:22.21#ibcon#about to read 3, iclass 3, count 0 2006.225.07:48:22.23#ibcon#read 3, iclass 3, count 0 2006.225.07:48:22.23#ibcon#about to read 4, iclass 3, count 0 2006.225.07:48:22.23#ibcon#read 4, iclass 3, count 0 2006.225.07:48:22.23#ibcon#about to read 5, iclass 3, count 0 2006.225.07:48:22.23#ibcon#read 5, iclass 3, count 0 2006.225.07:48:22.23#ibcon#about to read 6, iclass 3, count 0 2006.225.07:48:22.23#ibcon#read 6, iclass 3, count 0 2006.225.07:48:22.23#ibcon#end of sib2, iclass 3, count 0 2006.225.07:48:22.23#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:48:22.23#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:48:22.23#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:48:22.23#ibcon#*before write, iclass 3, count 0 2006.225.07:48:22.23#ibcon#enter sib2, iclass 3, count 0 2006.225.07:48:22.23#ibcon#flushed, iclass 3, count 0 2006.225.07:48:22.23#ibcon#about to write, iclass 3, count 0 2006.225.07:48:22.23#ibcon#wrote, iclass 3, count 0 2006.225.07:48:22.23#ibcon#about to read 3, iclass 3, count 0 2006.225.07:48:22.27#ibcon#read 3, iclass 3, count 0 2006.225.07:48:22.27#ibcon#about to read 4, iclass 3, count 0 2006.225.07:48:22.27#ibcon#read 4, iclass 3, count 0 2006.225.07:48:22.27#ibcon#about to read 5, iclass 3, count 0 2006.225.07:48:22.27#ibcon#read 5, iclass 3, count 0 2006.225.07:48:22.27#ibcon#about to read 6, iclass 3, count 0 2006.225.07:48:22.27#ibcon#read 6, iclass 3, count 0 2006.225.07:48:22.27#ibcon#end of sib2, iclass 3, count 0 2006.225.07:48:22.27#ibcon#*after write, iclass 3, count 0 2006.225.07:48:22.27#ibcon#*before return 0, iclass 3, count 0 2006.225.07:48:22.27#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:48:22.27#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.07:48:22.27#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:48:22.27#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:48:22.27$vc4f8/vb=6,4 2006.225.07:48:22.27#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.07:48:22.27#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.07:48:22.27#ibcon#ireg 11 cls_cnt 2 2006.225.07:48:22.27#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:48:22.33#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:48:22.33#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:48:22.33#ibcon#enter wrdev, iclass 5, count 2 2006.225.07:48:22.33#ibcon#first serial, iclass 5, count 2 2006.225.07:48:22.33#ibcon#enter sib2, iclass 5, count 2 2006.225.07:48:22.33#ibcon#flushed, iclass 5, count 2 2006.225.07:48:22.33#ibcon#about to write, iclass 5, count 2 2006.225.07:48:22.33#ibcon#wrote, iclass 5, count 2 2006.225.07:48:22.33#ibcon#about to read 3, iclass 5, count 2 2006.225.07:48:22.35#ibcon#read 3, iclass 5, count 2 2006.225.07:48:22.35#ibcon#about to read 4, iclass 5, count 2 2006.225.07:48:22.35#ibcon#read 4, iclass 5, count 2 2006.225.07:48:22.35#ibcon#about to read 5, iclass 5, count 2 2006.225.07:48:22.35#ibcon#read 5, iclass 5, count 2 2006.225.07:48:22.35#ibcon#about to read 6, iclass 5, count 2 2006.225.07:48:22.35#ibcon#read 6, iclass 5, count 2 2006.225.07:48:22.35#ibcon#end of sib2, iclass 5, count 2 2006.225.07:48:22.35#ibcon#*mode == 0, iclass 5, count 2 2006.225.07:48:22.35#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.07:48:22.35#ibcon#[27=AT06-04\r\n] 2006.225.07:48:22.35#ibcon#*before write, iclass 5, count 2 2006.225.07:48:22.35#ibcon#enter sib2, iclass 5, count 2 2006.225.07:48:22.35#ibcon#flushed, iclass 5, count 2 2006.225.07:48:22.35#ibcon#about to write, iclass 5, count 2 2006.225.07:48:22.35#ibcon#wrote, iclass 5, count 2 2006.225.07:48:22.35#ibcon#about to read 3, iclass 5, count 2 2006.225.07:48:22.38#ibcon#read 3, iclass 5, count 2 2006.225.07:48:22.38#ibcon#about to read 4, iclass 5, count 2 2006.225.07:48:22.38#ibcon#read 4, iclass 5, count 2 2006.225.07:48:22.38#ibcon#about to read 5, iclass 5, count 2 2006.225.07:48:22.38#ibcon#read 5, iclass 5, count 2 2006.225.07:48:22.38#ibcon#about to read 6, iclass 5, count 2 2006.225.07:48:22.38#ibcon#read 6, iclass 5, count 2 2006.225.07:48:22.38#ibcon#end of sib2, iclass 5, count 2 2006.225.07:48:22.38#ibcon#*after write, iclass 5, count 2 2006.225.07:48:22.38#ibcon#*before return 0, iclass 5, count 2 2006.225.07:48:22.38#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:48:22.38#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:48:22.38#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.07:48:22.38#ibcon#ireg 7 cls_cnt 0 2006.225.07:48:22.38#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:48:22.50#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:48:22.50#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:48:22.50#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:48:22.50#ibcon#first serial, iclass 5, count 0 2006.225.07:48:22.50#ibcon#enter sib2, iclass 5, count 0 2006.225.07:48:22.50#ibcon#flushed, iclass 5, count 0 2006.225.07:48:22.50#ibcon#about to write, iclass 5, count 0 2006.225.07:48:22.50#ibcon#wrote, iclass 5, count 0 2006.225.07:48:22.50#ibcon#about to read 3, iclass 5, count 0 2006.225.07:48:22.52#ibcon#read 3, iclass 5, count 0 2006.225.07:48:22.52#ibcon#about to read 4, iclass 5, count 0 2006.225.07:48:22.52#ibcon#read 4, iclass 5, count 0 2006.225.07:48:22.52#ibcon#about to read 5, iclass 5, count 0 2006.225.07:48:22.52#ibcon#read 5, iclass 5, count 0 2006.225.07:48:22.52#ibcon#about to read 6, iclass 5, count 0 2006.225.07:48:22.52#ibcon#read 6, iclass 5, count 0 2006.225.07:48:22.52#ibcon#end of sib2, iclass 5, count 0 2006.225.07:48:22.52#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:48:22.52#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:48:22.52#ibcon#[27=USB\r\n] 2006.225.07:48:22.52#ibcon#*before write, iclass 5, count 0 2006.225.07:48:22.52#ibcon#enter sib2, iclass 5, count 0 2006.225.07:48:22.52#ibcon#flushed, iclass 5, count 0 2006.225.07:48:22.52#ibcon#about to write, iclass 5, count 0 2006.225.07:48:22.52#ibcon#wrote, iclass 5, count 0 2006.225.07:48:22.52#ibcon#about to read 3, iclass 5, count 0 2006.225.07:48:22.55#ibcon#read 3, iclass 5, count 0 2006.225.07:48:22.55#ibcon#about to read 4, iclass 5, count 0 2006.225.07:48:22.55#ibcon#read 4, iclass 5, count 0 2006.225.07:48:22.55#ibcon#about to read 5, iclass 5, count 0 2006.225.07:48:22.55#ibcon#read 5, iclass 5, count 0 2006.225.07:48:22.55#ibcon#about to read 6, iclass 5, count 0 2006.225.07:48:22.55#ibcon#read 6, iclass 5, count 0 2006.225.07:48:22.55#ibcon#end of sib2, iclass 5, count 0 2006.225.07:48:22.55#ibcon#*after write, iclass 5, count 0 2006.225.07:48:22.55#ibcon#*before return 0, iclass 5, count 0 2006.225.07:48:22.55#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:48:22.55#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:48:22.55#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:48:22.55#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:48:22.55$vc4f8/vabw=wide 2006.225.07:48:22.55#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.225.07:48:22.55#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.225.07:48:22.55#ibcon#ireg 8 cls_cnt 0 2006.225.07:48:22.55#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:48:22.55#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:48:22.55#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:48:22.55#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:48:22.55#ibcon#first serial, iclass 7, count 0 2006.225.07:48:22.55#ibcon#enter sib2, iclass 7, count 0 2006.225.07:48:22.55#ibcon#flushed, iclass 7, count 0 2006.225.07:48:22.55#ibcon#about to write, iclass 7, count 0 2006.225.07:48:22.55#ibcon#wrote, iclass 7, count 0 2006.225.07:48:22.55#ibcon#about to read 3, iclass 7, count 0 2006.225.07:48:22.57#ibcon#read 3, iclass 7, count 0 2006.225.07:48:22.57#ibcon#about to read 4, iclass 7, count 0 2006.225.07:48:22.57#ibcon#read 4, iclass 7, count 0 2006.225.07:48:22.57#ibcon#about to read 5, iclass 7, count 0 2006.225.07:48:22.57#ibcon#read 5, iclass 7, count 0 2006.225.07:48:22.57#ibcon#about to read 6, iclass 7, count 0 2006.225.07:48:22.57#ibcon#read 6, iclass 7, count 0 2006.225.07:48:22.57#ibcon#end of sib2, iclass 7, count 0 2006.225.07:48:22.57#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:48:22.57#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:48:22.57#ibcon#[25=BW32\r\n] 2006.225.07:48:22.57#ibcon#*before write, iclass 7, count 0 2006.225.07:48:22.57#ibcon#enter sib2, iclass 7, count 0 2006.225.07:48:22.57#ibcon#flushed, iclass 7, count 0 2006.225.07:48:22.57#ibcon#about to write, iclass 7, count 0 2006.225.07:48:22.57#ibcon#wrote, iclass 7, count 0 2006.225.07:48:22.57#ibcon#about to read 3, iclass 7, count 0 2006.225.07:48:22.60#ibcon#read 3, iclass 7, count 0 2006.225.07:48:22.60#ibcon#about to read 4, iclass 7, count 0 2006.225.07:48:22.60#ibcon#read 4, iclass 7, count 0 2006.225.07:48:22.60#ibcon#about to read 5, iclass 7, count 0 2006.225.07:48:22.60#ibcon#read 5, iclass 7, count 0 2006.225.07:48:22.60#ibcon#about to read 6, iclass 7, count 0 2006.225.07:48:22.60#ibcon#read 6, iclass 7, count 0 2006.225.07:48:22.60#ibcon#end of sib2, iclass 7, count 0 2006.225.07:48:22.60#ibcon#*after write, iclass 7, count 0 2006.225.07:48:22.60#ibcon#*before return 0, iclass 7, count 0 2006.225.07:48:22.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:48:22.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.225.07:48:22.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:48:22.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:48:22.60$vc4f8/vbbw=wide 2006.225.07:48:22.60#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.07:48:22.60#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.07:48:22.60#ibcon#ireg 8 cls_cnt 0 2006.225.07:48:22.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:48:22.67#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:48:22.67#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:48:22.67#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:48:22.67#ibcon#first serial, iclass 11, count 0 2006.225.07:48:22.67#ibcon#enter sib2, iclass 11, count 0 2006.225.07:48:22.67#ibcon#flushed, iclass 11, count 0 2006.225.07:48:22.67#ibcon#about to write, iclass 11, count 0 2006.225.07:48:22.67#ibcon#wrote, iclass 11, count 0 2006.225.07:48:22.67#ibcon#about to read 3, iclass 11, count 0 2006.225.07:48:22.69#ibcon#read 3, iclass 11, count 0 2006.225.07:48:22.69#ibcon#about to read 4, iclass 11, count 0 2006.225.07:48:22.69#ibcon#read 4, iclass 11, count 0 2006.225.07:48:22.69#ibcon#about to read 5, iclass 11, count 0 2006.225.07:48:22.69#ibcon#read 5, iclass 11, count 0 2006.225.07:48:22.69#ibcon#about to read 6, iclass 11, count 0 2006.225.07:48:22.69#ibcon#read 6, iclass 11, count 0 2006.225.07:48:22.69#ibcon#end of sib2, iclass 11, count 0 2006.225.07:48:22.69#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:48:22.69#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:48:22.69#ibcon#[27=BW32\r\n] 2006.225.07:48:22.69#ibcon#*before write, iclass 11, count 0 2006.225.07:48:22.69#ibcon#enter sib2, iclass 11, count 0 2006.225.07:48:22.69#ibcon#flushed, iclass 11, count 0 2006.225.07:48:22.69#ibcon#about to write, iclass 11, count 0 2006.225.07:48:22.69#ibcon#wrote, iclass 11, count 0 2006.225.07:48:22.69#ibcon#about to read 3, iclass 11, count 0 2006.225.07:48:22.72#ibcon#read 3, iclass 11, count 0 2006.225.07:48:22.72#ibcon#about to read 4, iclass 11, count 0 2006.225.07:48:22.72#ibcon#read 4, iclass 11, count 0 2006.225.07:48:22.72#ibcon#about to read 5, iclass 11, count 0 2006.225.07:48:22.72#ibcon#read 5, iclass 11, count 0 2006.225.07:48:22.72#ibcon#about to read 6, iclass 11, count 0 2006.225.07:48:22.72#ibcon#read 6, iclass 11, count 0 2006.225.07:48:22.72#ibcon#end of sib2, iclass 11, count 0 2006.225.07:48:22.72#ibcon#*after write, iclass 11, count 0 2006.225.07:48:22.72#ibcon#*before return 0, iclass 11, count 0 2006.225.07:48:22.72#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:48:22.72#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:48:22.72#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:48:22.72#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:48:22.72$4f8m12a/ifd4f 2006.225.07:48:22.72$ifd4f/lo= 2006.225.07:48:22.72$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:48:22.72$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:48:22.72$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:48:22.72$ifd4f/patch= 2006.225.07:48:22.72$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:48:22.72$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:48:22.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:48:22.72$4f8m12a/"form=m,16.000,1:2 2006.225.07:48:22.72$4f8m12a/"tpicd 2006.225.07:48:22.72$4f8m12a/echo=off 2006.225.07:48:22.72$4f8m12a/xlog=off 2006.225.07:48:22.72:!2006.225.07:48:50 2006.225.07:48:32.14#trakl#Source acquired 2006.225.07:48:32.14#flagr#flagr/antenna,acquired 2006.225.07:48:50.00:preob 2006.225.07:48:51.14/onsource/TRACKING 2006.225.07:48:51.14:!2006.225.07:49:00 2006.225.07:49:00.00:data_valid=on 2006.225.07:49:00.00:midob 2006.225.07:49:00.14/onsource/TRACKING 2006.225.07:49:00.14/wx/28.20,1003.4,71 2006.225.07:49:00.31/cable/+6.4048E-03 2006.225.07:49:01.40/va/01,08,usb,yes,30,31 2006.225.07:49:01.40/va/02,07,usb,yes,30,31 2006.225.07:49:01.40/va/03,06,usb,yes,32,32 2006.225.07:49:01.40/va/04,07,usb,yes,31,34 2006.225.07:49:01.40/va/05,07,usb,yes,34,36 2006.225.07:49:01.40/va/06,06,usb,yes,33,33 2006.225.07:49:01.40/va/07,06,usb,yes,34,33 2006.225.07:49:01.40/va/08,07,usb,yes,32,31 2006.225.07:49:01.63/valo/01,532.99,yes,locked 2006.225.07:49:01.63/valo/02,572.99,yes,locked 2006.225.07:49:01.63/valo/03,672.99,yes,locked 2006.225.07:49:01.63/valo/04,832.99,yes,locked 2006.225.07:49:01.63/valo/05,652.99,yes,locked 2006.225.07:49:01.63/valo/06,772.99,yes,locked 2006.225.07:49:01.63/valo/07,832.99,yes,locked 2006.225.07:49:01.63/valo/08,852.99,yes,locked 2006.225.07:49:02.72/vb/01,04,usb,yes,31,30 2006.225.07:49:02.72/vb/02,04,usb,yes,33,35 2006.225.07:49:02.72/vb/03,04,usb,yes,29,33 2006.225.07:49:02.72/vb/04,04,usb,yes,30,30 2006.225.07:49:02.72/vb/05,04,usb,yes,29,33 2006.225.07:49:02.72/vb/06,04,usb,yes,30,33 2006.225.07:49:02.72/vb/07,04,usb,yes,32,32 2006.225.07:49:02.72/vb/08,04,usb,yes,29,33 2006.225.07:49:02.96/vblo/01,632.99,yes,locked 2006.225.07:49:02.96/vblo/02,640.99,yes,locked 2006.225.07:49:02.96/vblo/03,656.99,yes,locked 2006.225.07:49:02.96/vblo/04,712.99,yes,locked 2006.225.07:49:02.96/vblo/05,744.99,yes,locked 2006.225.07:49:02.96/vblo/06,752.99,yes,locked 2006.225.07:49:02.96/vblo/07,734.99,yes,locked 2006.225.07:49:02.96/vblo/08,744.99,yes,locked 2006.225.07:49:03.11/vabw/8 2006.225.07:49:03.26/vbbw/8 2006.225.07:49:03.35/xfe/off,on,15.2 2006.225.07:49:03.74/ifatt/23,28,28,28 2006.225.07:49:04.07/fmout-gps/S +4.51E-07 2006.225.07:49:04.11:!2006.225.07:50:00 2006.225.07:50:00.00:data_valid=off 2006.225.07:50:00.00:postob 2006.225.07:50:00.17/cable/+6.4048E-03 2006.225.07:50:00.17/wx/28.24,1003.4,70 2006.225.07:50:01.07/fmout-gps/S +4.52E-07 2006.225.07:50:01.07:scan_name=225-0750,k06225,60 2006.225.07:50:01.08:source=0642+449,064632.03,445116.6,2000.0,ccw 2006.225.07:50:01.14#flagr#flagr/antenna,new-source 2006.225.07:50:02.14:checkk5 2006.225.07:50:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:50:02.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:50:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:50:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:50:04.00/chk_obsdata//k5ts1/T2250749??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:50:04.37/chk_obsdata//k5ts2/T2250749??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:50:04.74/chk_obsdata//k5ts3/T2250749??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:50:05.11/chk_obsdata//k5ts4/T2250749??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:50:05.79/k5log//k5ts1_log_newline 2006.225.07:50:06.49/k5log//k5ts2_log_newline 2006.225.07:50:07.17/k5log//k5ts3_log_newline 2006.225.07:50:07.85/k5log//k5ts4_log_newline 2006.225.07:50:07.88/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:50:07.88:4f8m12a=1 2006.225.07:50:07.88$4f8m12a/echo=on 2006.225.07:50:07.88$4f8m12a/pcalon 2006.225.07:50:07.88$pcalon/"no phase cal control is implemented here 2006.225.07:50:07.88$4f8m12a/"tpicd=stop 2006.225.07:50:07.88$4f8m12a/vc4f8 2006.225.07:50:07.88$vc4f8/valo=1,532.99 2006.225.07:50:07.88#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.07:50:07.88#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.07:50:07.88#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:07.88#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:50:07.88#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:50:07.88#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:50:07.88#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:50:07.88#ibcon#first serial, iclass 18, count 0 2006.225.07:50:07.88#ibcon#enter sib2, iclass 18, count 0 2006.225.07:50:07.88#ibcon#flushed, iclass 18, count 0 2006.225.07:50:07.88#ibcon#about to write, iclass 18, count 0 2006.225.07:50:07.88#ibcon#wrote, iclass 18, count 0 2006.225.07:50:07.88#ibcon#about to read 3, iclass 18, count 0 2006.225.07:50:07.92#ibcon#read 3, iclass 18, count 0 2006.225.07:50:07.92#ibcon#about to read 4, iclass 18, count 0 2006.225.07:50:07.92#ibcon#read 4, iclass 18, count 0 2006.225.07:50:07.92#ibcon#about to read 5, iclass 18, count 0 2006.225.07:50:07.92#ibcon#read 5, iclass 18, count 0 2006.225.07:50:07.92#ibcon#about to read 6, iclass 18, count 0 2006.225.07:50:07.92#ibcon#read 6, iclass 18, count 0 2006.225.07:50:07.92#ibcon#end of sib2, iclass 18, count 0 2006.225.07:50:07.92#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:50:07.92#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:50:07.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:50:07.92#ibcon#*before write, iclass 18, count 0 2006.225.07:50:07.92#ibcon#enter sib2, iclass 18, count 0 2006.225.07:50:07.92#ibcon#flushed, iclass 18, count 0 2006.225.07:50:07.92#ibcon#about to write, iclass 18, count 0 2006.225.07:50:07.92#ibcon#wrote, iclass 18, count 0 2006.225.07:50:07.92#ibcon#about to read 3, iclass 18, count 0 2006.225.07:50:07.97#ibcon#read 3, iclass 18, count 0 2006.225.07:50:07.97#ibcon#about to read 4, iclass 18, count 0 2006.225.07:50:07.97#ibcon#read 4, iclass 18, count 0 2006.225.07:50:07.97#ibcon#about to read 5, iclass 18, count 0 2006.225.07:50:07.97#ibcon#read 5, iclass 18, count 0 2006.225.07:50:07.97#ibcon#about to read 6, iclass 18, count 0 2006.225.07:50:07.97#ibcon#read 6, iclass 18, count 0 2006.225.07:50:07.97#ibcon#end of sib2, iclass 18, count 0 2006.225.07:50:07.97#ibcon#*after write, iclass 18, count 0 2006.225.07:50:07.97#ibcon#*before return 0, iclass 18, count 0 2006.225.07:50:07.97#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:50:07.97#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:50:07.97#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:50:07.97#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:50:07.97$vc4f8/va=1,8 2006.225.07:50:07.97#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.07:50:07.97#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.07:50:07.97#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:07.97#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:50:07.97#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:50:07.97#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:50:07.97#ibcon#enter wrdev, iclass 20, count 2 2006.225.07:50:07.97#ibcon#first serial, iclass 20, count 2 2006.225.07:50:07.97#ibcon#enter sib2, iclass 20, count 2 2006.225.07:50:07.97#ibcon#flushed, iclass 20, count 2 2006.225.07:50:07.97#ibcon#about to write, iclass 20, count 2 2006.225.07:50:07.97#ibcon#wrote, iclass 20, count 2 2006.225.07:50:07.97#ibcon#about to read 3, iclass 20, count 2 2006.225.07:50:08.00#ibcon#read 3, iclass 20, count 2 2006.225.07:50:08.00#ibcon#about to read 4, iclass 20, count 2 2006.225.07:50:08.00#ibcon#read 4, iclass 20, count 2 2006.225.07:50:08.00#ibcon#about to read 5, iclass 20, count 2 2006.225.07:50:08.00#ibcon#read 5, iclass 20, count 2 2006.225.07:50:08.00#ibcon#about to read 6, iclass 20, count 2 2006.225.07:50:08.00#ibcon#read 6, iclass 20, count 2 2006.225.07:50:08.00#ibcon#end of sib2, iclass 20, count 2 2006.225.07:50:08.00#ibcon#*mode == 0, iclass 20, count 2 2006.225.07:50:08.00#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.07:50:08.00#ibcon#[25=AT01-08\r\n] 2006.225.07:50:08.00#ibcon#*before write, iclass 20, count 2 2006.225.07:50:08.00#ibcon#enter sib2, iclass 20, count 2 2006.225.07:50:08.00#ibcon#flushed, iclass 20, count 2 2006.225.07:50:08.00#ibcon#about to write, iclass 20, count 2 2006.225.07:50:08.00#ibcon#wrote, iclass 20, count 2 2006.225.07:50:08.00#ibcon#about to read 3, iclass 20, count 2 2006.225.07:50:08.03#ibcon#read 3, iclass 20, count 2 2006.225.07:50:08.03#ibcon#about to read 4, iclass 20, count 2 2006.225.07:50:08.03#ibcon#read 4, iclass 20, count 2 2006.225.07:50:08.03#ibcon#about to read 5, iclass 20, count 2 2006.225.07:50:08.03#ibcon#read 5, iclass 20, count 2 2006.225.07:50:08.03#ibcon#about to read 6, iclass 20, count 2 2006.225.07:50:08.03#ibcon#read 6, iclass 20, count 2 2006.225.07:50:08.03#ibcon#end of sib2, iclass 20, count 2 2006.225.07:50:08.03#ibcon#*after write, iclass 20, count 2 2006.225.07:50:08.03#ibcon#*before return 0, iclass 20, count 2 2006.225.07:50:08.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:50:08.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:50:08.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.07:50:08.03#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:08.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:50:08.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:50:08.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:50:08.15#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:50:08.15#ibcon#first serial, iclass 20, count 0 2006.225.07:50:08.15#ibcon#enter sib2, iclass 20, count 0 2006.225.07:50:08.15#ibcon#flushed, iclass 20, count 0 2006.225.07:50:08.15#ibcon#about to write, iclass 20, count 0 2006.225.07:50:08.15#ibcon#wrote, iclass 20, count 0 2006.225.07:50:08.15#ibcon#about to read 3, iclass 20, count 0 2006.225.07:50:08.17#ibcon#read 3, iclass 20, count 0 2006.225.07:50:08.17#ibcon#about to read 4, iclass 20, count 0 2006.225.07:50:08.17#ibcon#read 4, iclass 20, count 0 2006.225.07:50:08.17#ibcon#about to read 5, iclass 20, count 0 2006.225.07:50:08.17#ibcon#read 5, iclass 20, count 0 2006.225.07:50:08.17#ibcon#about to read 6, iclass 20, count 0 2006.225.07:50:08.17#ibcon#read 6, iclass 20, count 0 2006.225.07:50:08.17#ibcon#end of sib2, iclass 20, count 0 2006.225.07:50:08.17#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:50:08.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:50:08.17#ibcon#[25=USB\r\n] 2006.225.07:50:08.17#ibcon#*before write, iclass 20, count 0 2006.225.07:50:08.17#ibcon#enter sib2, iclass 20, count 0 2006.225.07:50:08.17#ibcon#flushed, iclass 20, count 0 2006.225.07:50:08.17#ibcon#about to write, iclass 20, count 0 2006.225.07:50:08.17#ibcon#wrote, iclass 20, count 0 2006.225.07:50:08.17#ibcon#about to read 3, iclass 20, count 0 2006.225.07:50:08.20#ibcon#read 3, iclass 20, count 0 2006.225.07:50:08.20#ibcon#about to read 4, iclass 20, count 0 2006.225.07:50:08.20#ibcon#read 4, iclass 20, count 0 2006.225.07:50:08.20#ibcon#about to read 5, iclass 20, count 0 2006.225.07:50:08.20#ibcon#read 5, iclass 20, count 0 2006.225.07:50:08.20#ibcon#about to read 6, iclass 20, count 0 2006.225.07:50:08.20#ibcon#read 6, iclass 20, count 0 2006.225.07:50:08.20#ibcon#end of sib2, iclass 20, count 0 2006.225.07:50:08.20#ibcon#*after write, iclass 20, count 0 2006.225.07:50:08.20#ibcon#*before return 0, iclass 20, count 0 2006.225.07:50:08.20#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:50:08.20#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:50:08.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:50:08.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:50:08.20$vc4f8/valo=2,572.99 2006.225.07:50:08.20#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.07:50:08.20#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.07:50:08.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:08.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:50:08.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:50:08.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:50:08.20#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:50:08.20#ibcon#first serial, iclass 22, count 0 2006.225.07:50:08.20#ibcon#enter sib2, iclass 22, count 0 2006.225.07:50:08.20#ibcon#flushed, iclass 22, count 0 2006.225.07:50:08.20#ibcon#about to write, iclass 22, count 0 2006.225.07:50:08.20#ibcon#wrote, iclass 22, count 0 2006.225.07:50:08.20#ibcon#about to read 3, iclass 22, count 0 2006.225.07:50:08.23#ibcon#read 3, iclass 22, count 0 2006.225.07:50:08.23#ibcon#about to read 4, iclass 22, count 0 2006.225.07:50:08.23#ibcon#read 4, iclass 22, count 0 2006.225.07:50:08.23#ibcon#about to read 5, iclass 22, count 0 2006.225.07:50:08.23#ibcon#read 5, iclass 22, count 0 2006.225.07:50:08.23#ibcon#about to read 6, iclass 22, count 0 2006.225.07:50:08.23#ibcon#read 6, iclass 22, count 0 2006.225.07:50:08.23#ibcon#end of sib2, iclass 22, count 0 2006.225.07:50:08.23#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:50:08.23#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:50:08.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:50:08.23#ibcon#*before write, iclass 22, count 0 2006.225.07:50:08.23#ibcon#enter sib2, iclass 22, count 0 2006.225.07:50:08.23#ibcon#flushed, iclass 22, count 0 2006.225.07:50:08.23#ibcon#about to write, iclass 22, count 0 2006.225.07:50:08.23#ibcon#wrote, iclass 22, count 0 2006.225.07:50:08.23#ibcon#about to read 3, iclass 22, count 0 2006.225.07:50:08.27#ibcon#read 3, iclass 22, count 0 2006.225.07:50:08.27#ibcon#about to read 4, iclass 22, count 0 2006.225.07:50:08.27#ibcon#read 4, iclass 22, count 0 2006.225.07:50:08.27#ibcon#about to read 5, iclass 22, count 0 2006.225.07:50:08.27#ibcon#read 5, iclass 22, count 0 2006.225.07:50:08.27#ibcon#about to read 6, iclass 22, count 0 2006.225.07:50:08.27#ibcon#read 6, iclass 22, count 0 2006.225.07:50:08.27#ibcon#end of sib2, iclass 22, count 0 2006.225.07:50:08.27#ibcon#*after write, iclass 22, count 0 2006.225.07:50:08.27#ibcon#*before return 0, iclass 22, count 0 2006.225.07:50:08.27#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:50:08.27#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:50:08.27#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:50:08.27#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:50:08.27$vc4f8/va=2,7 2006.225.07:50:08.27#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.07:50:08.27#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.07:50:08.27#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:08.27#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:50:08.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:50:08.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:50:08.32#ibcon#enter wrdev, iclass 24, count 2 2006.225.07:50:08.32#ibcon#first serial, iclass 24, count 2 2006.225.07:50:08.32#ibcon#enter sib2, iclass 24, count 2 2006.225.07:50:08.32#ibcon#flushed, iclass 24, count 2 2006.225.07:50:08.32#ibcon#about to write, iclass 24, count 2 2006.225.07:50:08.32#ibcon#wrote, iclass 24, count 2 2006.225.07:50:08.32#ibcon#about to read 3, iclass 24, count 2 2006.225.07:50:08.34#ibcon#read 3, iclass 24, count 2 2006.225.07:50:08.34#ibcon#about to read 4, iclass 24, count 2 2006.225.07:50:08.34#ibcon#read 4, iclass 24, count 2 2006.225.07:50:08.34#ibcon#about to read 5, iclass 24, count 2 2006.225.07:50:08.34#ibcon#read 5, iclass 24, count 2 2006.225.07:50:08.34#ibcon#about to read 6, iclass 24, count 2 2006.225.07:50:08.34#ibcon#read 6, iclass 24, count 2 2006.225.07:50:08.34#ibcon#end of sib2, iclass 24, count 2 2006.225.07:50:08.34#ibcon#*mode == 0, iclass 24, count 2 2006.225.07:50:08.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.07:50:08.34#ibcon#[25=AT02-07\r\n] 2006.225.07:50:08.34#ibcon#*before write, iclass 24, count 2 2006.225.07:50:08.34#ibcon#enter sib2, iclass 24, count 2 2006.225.07:50:08.34#ibcon#flushed, iclass 24, count 2 2006.225.07:50:08.34#ibcon#about to write, iclass 24, count 2 2006.225.07:50:08.34#ibcon#wrote, iclass 24, count 2 2006.225.07:50:08.34#ibcon#about to read 3, iclass 24, count 2 2006.225.07:50:08.37#ibcon#read 3, iclass 24, count 2 2006.225.07:50:08.37#ibcon#about to read 4, iclass 24, count 2 2006.225.07:50:08.37#ibcon#read 4, iclass 24, count 2 2006.225.07:50:08.37#ibcon#about to read 5, iclass 24, count 2 2006.225.07:50:08.37#ibcon#read 5, iclass 24, count 2 2006.225.07:50:08.37#ibcon#about to read 6, iclass 24, count 2 2006.225.07:50:08.37#ibcon#read 6, iclass 24, count 2 2006.225.07:50:08.37#ibcon#end of sib2, iclass 24, count 2 2006.225.07:50:08.37#ibcon#*after write, iclass 24, count 2 2006.225.07:50:08.37#ibcon#*before return 0, iclass 24, count 2 2006.225.07:50:08.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:50:08.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:50:08.37#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.07:50:08.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:08.37#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:50:08.49#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:50:08.49#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:50:08.49#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:50:08.49#ibcon#first serial, iclass 24, count 0 2006.225.07:50:08.49#ibcon#enter sib2, iclass 24, count 0 2006.225.07:50:08.49#ibcon#flushed, iclass 24, count 0 2006.225.07:50:08.49#ibcon#about to write, iclass 24, count 0 2006.225.07:50:08.49#ibcon#wrote, iclass 24, count 0 2006.225.07:50:08.49#ibcon#about to read 3, iclass 24, count 0 2006.225.07:50:08.51#ibcon#read 3, iclass 24, count 0 2006.225.07:50:08.51#ibcon#about to read 4, iclass 24, count 0 2006.225.07:50:08.51#ibcon#read 4, iclass 24, count 0 2006.225.07:50:08.51#ibcon#about to read 5, iclass 24, count 0 2006.225.07:50:08.51#ibcon#read 5, iclass 24, count 0 2006.225.07:50:08.51#ibcon#about to read 6, iclass 24, count 0 2006.225.07:50:08.51#ibcon#read 6, iclass 24, count 0 2006.225.07:50:08.51#ibcon#end of sib2, iclass 24, count 0 2006.225.07:50:08.51#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:50:08.51#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:50:08.51#ibcon#[25=USB\r\n] 2006.225.07:50:08.51#ibcon#*before write, iclass 24, count 0 2006.225.07:50:08.51#ibcon#enter sib2, iclass 24, count 0 2006.225.07:50:08.51#ibcon#flushed, iclass 24, count 0 2006.225.07:50:08.51#ibcon#about to write, iclass 24, count 0 2006.225.07:50:08.51#ibcon#wrote, iclass 24, count 0 2006.225.07:50:08.51#ibcon#about to read 3, iclass 24, count 0 2006.225.07:50:08.54#ibcon#read 3, iclass 24, count 0 2006.225.07:50:08.54#ibcon#about to read 4, iclass 24, count 0 2006.225.07:50:08.54#ibcon#read 4, iclass 24, count 0 2006.225.07:50:08.54#ibcon#about to read 5, iclass 24, count 0 2006.225.07:50:08.54#ibcon#read 5, iclass 24, count 0 2006.225.07:50:08.54#ibcon#about to read 6, iclass 24, count 0 2006.225.07:50:08.54#ibcon#read 6, iclass 24, count 0 2006.225.07:50:08.54#ibcon#end of sib2, iclass 24, count 0 2006.225.07:50:08.54#ibcon#*after write, iclass 24, count 0 2006.225.07:50:08.54#ibcon#*before return 0, iclass 24, count 0 2006.225.07:50:08.54#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:50:08.54#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:50:08.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:50:08.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:50:08.54$vc4f8/valo=3,672.99 2006.225.07:50:08.54#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.07:50:08.54#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.07:50:08.54#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:08.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:50:08.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:50:08.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:50:08.54#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:50:08.54#ibcon#first serial, iclass 26, count 0 2006.225.07:50:08.54#ibcon#enter sib2, iclass 26, count 0 2006.225.07:50:08.54#ibcon#flushed, iclass 26, count 0 2006.225.07:50:08.54#ibcon#about to write, iclass 26, count 0 2006.225.07:50:08.54#ibcon#wrote, iclass 26, count 0 2006.225.07:50:08.54#ibcon#about to read 3, iclass 26, count 0 2006.225.07:50:08.57#ibcon#read 3, iclass 26, count 0 2006.225.07:50:08.57#ibcon#about to read 4, iclass 26, count 0 2006.225.07:50:08.57#ibcon#read 4, iclass 26, count 0 2006.225.07:50:08.57#ibcon#about to read 5, iclass 26, count 0 2006.225.07:50:08.57#ibcon#read 5, iclass 26, count 0 2006.225.07:50:08.57#ibcon#about to read 6, iclass 26, count 0 2006.225.07:50:08.57#ibcon#read 6, iclass 26, count 0 2006.225.07:50:08.57#ibcon#end of sib2, iclass 26, count 0 2006.225.07:50:08.57#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:50:08.57#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:50:08.57#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:50:08.57#ibcon#*before write, iclass 26, count 0 2006.225.07:50:08.57#ibcon#enter sib2, iclass 26, count 0 2006.225.07:50:08.57#ibcon#flushed, iclass 26, count 0 2006.225.07:50:08.57#ibcon#about to write, iclass 26, count 0 2006.225.07:50:08.57#ibcon#wrote, iclass 26, count 0 2006.225.07:50:08.57#ibcon#about to read 3, iclass 26, count 0 2006.225.07:50:08.61#ibcon#read 3, iclass 26, count 0 2006.225.07:50:08.61#ibcon#about to read 4, iclass 26, count 0 2006.225.07:50:08.61#ibcon#read 4, iclass 26, count 0 2006.225.07:50:08.61#ibcon#about to read 5, iclass 26, count 0 2006.225.07:50:08.61#ibcon#read 5, iclass 26, count 0 2006.225.07:50:08.61#ibcon#about to read 6, iclass 26, count 0 2006.225.07:50:08.61#ibcon#read 6, iclass 26, count 0 2006.225.07:50:08.61#ibcon#end of sib2, iclass 26, count 0 2006.225.07:50:08.61#ibcon#*after write, iclass 26, count 0 2006.225.07:50:08.61#ibcon#*before return 0, iclass 26, count 0 2006.225.07:50:08.61#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:50:08.61#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:50:08.61#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:50:08.61#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:50:08.61$vc4f8/va=3,6 2006.225.07:50:08.61#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.07:50:08.61#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.07:50:08.61#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:08.61#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:50:08.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:50:08.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:50:08.66#ibcon#enter wrdev, iclass 28, count 2 2006.225.07:50:08.66#ibcon#first serial, iclass 28, count 2 2006.225.07:50:08.66#ibcon#enter sib2, iclass 28, count 2 2006.225.07:50:08.66#ibcon#flushed, iclass 28, count 2 2006.225.07:50:08.66#ibcon#about to write, iclass 28, count 2 2006.225.07:50:08.66#ibcon#wrote, iclass 28, count 2 2006.225.07:50:08.66#ibcon#about to read 3, iclass 28, count 2 2006.225.07:50:08.68#ibcon#read 3, iclass 28, count 2 2006.225.07:50:08.68#ibcon#about to read 4, iclass 28, count 2 2006.225.07:50:08.68#ibcon#read 4, iclass 28, count 2 2006.225.07:50:08.68#ibcon#about to read 5, iclass 28, count 2 2006.225.07:50:08.68#ibcon#read 5, iclass 28, count 2 2006.225.07:50:08.68#ibcon#about to read 6, iclass 28, count 2 2006.225.07:50:08.68#ibcon#read 6, iclass 28, count 2 2006.225.07:50:08.68#ibcon#end of sib2, iclass 28, count 2 2006.225.07:50:08.68#ibcon#*mode == 0, iclass 28, count 2 2006.225.07:50:08.68#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.07:50:08.68#ibcon#[25=AT03-06\r\n] 2006.225.07:50:08.68#ibcon#*before write, iclass 28, count 2 2006.225.07:50:08.68#ibcon#enter sib2, iclass 28, count 2 2006.225.07:50:08.68#ibcon#flushed, iclass 28, count 2 2006.225.07:50:08.68#ibcon#about to write, iclass 28, count 2 2006.225.07:50:08.68#ibcon#wrote, iclass 28, count 2 2006.225.07:50:08.68#ibcon#about to read 3, iclass 28, count 2 2006.225.07:50:08.71#ibcon#read 3, iclass 28, count 2 2006.225.07:50:08.71#ibcon#about to read 4, iclass 28, count 2 2006.225.07:50:08.71#ibcon#read 4, iclass 28, count 2 2006.225.07:50:08.71#ibcon#about to read 5, iclass 28, count 2 2006.225.07:50:08.71#ibcon#read 5, iclass 28, count 2 2006.225.07:50:08.71#ibcon#about to read 6, iclass 28, count 2 2006.225.07:50:08.71#ibcon#read 6, iclass 28, count 2 2006.225.07:50:08.71#ibcon#end of sib2, iclass 28, count 2 2006.225.07:50:08.71#ibcon#*after write, iclass 28, count 2 2006.225.07:50:08.71#ibcon#*before return 0, iclass 28, count 2 2006.225.07:50:08.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:50:08.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:50:08.71#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.07:50:08.71#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:08.71#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:50:08.83#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:50:08.83#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:50:08.83#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:50:08.83#ibcon#first serial, iclass 28, count 0 2006.225.07:50:08.83#ibcon#enter sib2, iclass 28, count 0 2006.225.07:50:08.83#ibcon#flushed, iclass 28, count 0 2006.225.07:50:08.83#ibcon#about to write, iclass 28, count 0 2006.225.07:50:08.83#ibcon#wrote, iclass 28, count 0 2006.225.07:50:08.83#ibcon#about to read 3, iclass 28, count 0 2006.225.07:50:08.85#ibcon#read 3, iclass 28, count 0 2006.225.07:50:08.85#ibcon#about to read 4, iclass 28, count 0 2006.225.07:50:08.85#ibcon#read 4, iclass 28, count 0 2006.225.07:50:08.85#ibcon#about to read 5, iclass 28, count 0 2006.225.07:50:08.85#ibcon#read 5, iclass 28, count 0 2006.225.07:50:08.85#ibcon#about to read 6, iclass 28, count 0 2006.225.07:50:08.85#ibcon#read 6, iclass 28, count 0 2006.225.07:50:08.85#ibcon#end of sib2, iclass 28, count 0 2006.225.07:50:08.85#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:50:08.85#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:50:08.85#ibcon#[25=USB\r\n] 2006.225.07:50:08.85#ibcon#*before write, iclass 28, count 0 2006.225.07:50:08.85#ibcon#enter sib2, iclass 28, count 0 2006.225.07:50:08.85#ibcon#flushed, iclass 28, count 0 2006.225.07:50:08.85#ibcon#about to write, iclass 28, count 0 2006.225.07:50:08.85#ibcon#wrote, iclass 28, count 0 2006.225.07:50:08.85#ibcon#about to read 3, iclass 28, count 0 2006.225.07:50:08.88#ibcon#read 3, iclass 28, count 0 2006.225.07:50:08.88#ibcon#about to read 4, iclass 28, count 0 2006.225.07:50:08.88#ibcon#read 4, iclass 28, count 0 2006.225.07:50:08.88#ibcon#about to read 5, iclass 28, count 0 2006.225.07:50:08.88#ibcon#read 5, iclass 28, count 0 2006.225.07:50:08.88#ibcon#about to read 6, iclass 28, count 0 2006.225.07:50:08.88#ibcon#read 6, iclass 28, count 0 2006.225.07:50:08.88#ibcon#end of sib2, iclass 28, count 0 2006.225.07:50:08.88#ibcon#*after write, iclass 28, count 0 2006.225.07:50:08.88#ibcon#*before return 0, iclass 28, count 0 2006.225.07:50:08.88#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:50:08.88#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:50:08.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:50:08.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:50:08.88$vc4f8/valo=4,832.99 2006.225.07:50:08.88#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.07:50:08.88#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.07:50:08.88#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:08.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:50:08.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:50:08.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:50:08.88#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:50:08.88#ibcon#first serial, iclass 30, count 0 2006.225.07:50:08.88#ibcon#enter sib2, iclass 30, count 0 2006.225.07:50:08.88#ibcon#flushed, iclass 30, count 0 2006.225.07:50:08.88#ibcon#about to write, iclass 30, count 0 2006.225.07:50:08.88#ibcon#wrote, iclass 30, count 0 2006.225.07:50:08.88#ibcon#about to read 3, iclass 30, count 0 2006.225.07:50:08.91#ibcon#read 3, iclass 30, count 0 2006.225.07:50:08.91#ibcon#about to read 4, iclass 30, count 0 2006.225.07:50:08.91#ibcon#read 4, iclass 30, count 0 2006.225.07:50:08.91#ibcon#about to read 5, iclass 30, count 0 2006.225.07:50:08.91#ibcon#read 5, iclass 30, count 0 2006.225.07:50:08.91#ibcon#about to read 6, iclass 30, count 0 2006.225.07:50:08.91#ibcon#read 6, iclass 30, count 0 2006.225.07:50:08.91#ibcon#end of sib2, iclass 30, count 0 2006.225.07:50:08.91#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:50:08.91#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:50:08.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:50:08.91#ibcon#*before write, iclass 30, count 0 2006.225.07:50:08.91#ibcon#enter sib2, iclass 30, count 0 2006.225.07:50:08.91#ibcon#flushed, iclass 30, count 0 2006.225.07:50:08.91#ibcon#about to write, iclass 30, count 0 2006.225.07:50:08.91#ibcon#wrote, iclass 30, count 0 2006.225.07:50:08.91#ibcon#about to read 3, iclass 30, count 0 2006.225.07:50:08.95#ibcon#read 3, iclass 30, count 0 2006.225.07:50:08.95#ibcon#about to read 4, iclass 30, count 0 2006.225.07:50:08.95#ibcon#read 4, iclass 30, count 0 2006.225.07:50:08.95#ibcon#about to read 5, iclass 30, count 0 2006.225.07:50:08.95#ibcon#read 5, iclass 30, count 0 2006.225.07:50:08.95#ibcon#about to read 6, iclass 30, count 0 2006.225.07:50:08.95#ibcon#read 6, iclass 30, count 0 2006.225.07:50:08.95#ibcon#end of sib2, iclass 30, count 0 2006.225.07:50:08.95#ibcon#*after write, iclass 30, count 0 2006.225.07:50:08.95#ibcon#*before return 0, iclass 30, count 0 2006.225.07:50:08.95#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:50:08.95#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:50:08.95#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:50:08.95#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:50:08.95$vc4f8/va=4,7 2006.225.07:50:08.95#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.225.07:50:08.95#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.225.07:50:08.95#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:08.95#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:50:09.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:50:09.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:50:09.00#ibcon#enter wrdev, iclass 32, count 2 2006.225.07:50:09.00#ibcon#first serial, iclass 32, count 2 2006.225.07:50:09.00#ibcon#enter sib2, iclass 32, count 2 2006.225.07:50:09.00#ibcon#flushed, iclass 32, count 2 2006.225.07:50:09.00#ibcon#about to write, iclass 32, count 2 2006.225.07:50:09.00#ibcon#wrote, iclass 32, count 2 2006.225.07:50:09.00#ibcon#about to read 3, iclass 32, count 2 2006.225.07:50:09.02#ibcon#read 3, iclass 32, count 2 2006.225.07:50:09.02#ibcon#about to read 4, iclass 32, count 2 2006.225.07:50:09.02#ibcon#read 4, iclass 32, count 2 2006.225.07:50:09.02#ibcon#about to read 5, iclass 32, count 2 2006.225.07:50:09.02#ibcon#read 5, iclass 32, count 2 2006.225.07:50:09.02#ibcon#about to read 6, iclass 32, count 2 2006.225.07:50:09.02#ibcon#read 6, iclass 32, count 2 2006.225.07:50:09.02#ibcon#end of sib2, iclass 32, count 2 2006.225.07:50:09.02#ibcon#*mode == 0, iclass 32, count 2 2006.225.07:50:09.02#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.225.07:50:09.02#ibcon#[25=AT04-07\r\n] 2006.225.07:50:09.02#ibcon#*before write, iclass 32, count 2 2006.225.07:50:09.02#ibcon#enter sib2, iclass 32, count 2 2006.225.07:50:09.02#ibcon#flushed, iclass 32, count 2 2006.225.07:50:09.02#ibcon#about to write, iclass 32, count 2 2006.225.07:50:09.02#ibcon#wrote, iclass 32, count 2 2006.225.07:50:09.02#ibcon#about to read 3, iclass 32, count 2 2006.225.07:50:09.05#ibcon#read 3, iclass 32, count 2 2006.225.07:50:09.05#ibcon#about to read 4, iclass 32, count 2 2006.225.07:50:09.05#ibcon#read 4, iclass 32, count 2 2006.225.07:50:09.05#ibcon#about to read 5, iclass 32, count 2 2006.225.07:50:09.05#ibcon#read 5, iclass 32, count 2 2006.225.07:50:09.05#ibcon#about to read 6, iclass 32, count 2 2006.225.07:50:09.05#ibcon#read 6, iclass 32, count 2 2006.225.07:50:09.05#ibcon#end of sib2, iclass 32, count 2 2006.225.07:50:09.05#ibcon#*after write, iclass 32, count 2 2006.225.07:50:09.05#ibcon#*before return 0, iclass 32, count 2 2006.225.07:50:09.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:50:09.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:50:09.05#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.225.07:50:09.05#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:09.05#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:50:09.17#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:50:09.17#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:50:09.17#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:50:09.17#ibcon#first serial, iclass 32, count 0 2006.225.07:50:09.17#ibcon#enter sib2, iclass 32, count 0 2006.225.07:50:09.17#ibcon#flushed, iclass 32, count 0 2006.225.07:50:09.17#ibcon#about to write, iclass 32, count 0 2006.225.07:50:09.17#ibcon#wrote, iclass 32, count 0 2006.225.07:50:09.17#ibcon#about to read 3, iclass 32, count 0 2006.225.07:50:09.19#ibcon#read 3, iclass 32, count 0 2006.225.07:50:09.19#ibcon#about to read 4, iclass 32, count 0 2006.225.07:50:09.19#ibcon#read 4, iclass 32, count 0 2006.225.07:50:09.19#ibcon#about to read 5, iclass 32, count 0 2006.225.07:50:09.19#ibcon#read 5, iclass 32, count 0 2006.225.07:50:09.19#ibcon#about to read 6, iclass 32, count 0 2006.225.07:50:09.19#ibcon#read 6, iclass 32, count 0 2006.225.07:50:09.19#ibcon#end of sib2, iclass 32, count 0 2006.225.07:50:09.19#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:50:09.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:50:09.19#ibcon#[25=USB\r\n] 2006.225.07:50:09.19#ibcon#*before write, iclass 32, count 0 2006.225.07:50:09.19#ibcon#enter sib2, iclass 32, count 0 2006.225.07:50:09.19#ibcon#flushed, iclass 32, count 0 2006.225.07:50:09.19#ibcon#about to write, iclass 32, count 0 2006.225.07:50:09.19#ibcon#wrote, iclass 32, count 0 2006.225.07:50:09.19#ibcon#about to read 3, iclass 32, count 0 2006.225.07:50:09.22#ibcon#read 3, iclass 32, count 0 2006.225.07:50:09.22#ibcon#about to read 4, iclass 32, count 0 2006.225.07:50:09.22#ibcon#read 4, iclass 32, count 0 2006.225.07:50:09.22#ibcon#about to read 5, iclass 32, count 0 2006.225.07:50:09.22#ibcon#read 5, iclass 32, count 0 2006.225.07:50:09.22#ibcon#about to read 6, iclass 32, count 0 2006.225.07:50:09.22#ibcon#read 6, iclass 32, count 0 2006.225.07:50:09.22#ibcon#end of sib2, iclass 32, count 0 2006.225.07:50:09.22#ibcon#*after write, iclass 32, count 0 2006.225.07:50:09.22#ibcon#*before return 0, iclass 32, count 0 2006.225.07:50:09.22#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:50:09.22#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:50:09.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:50:09.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:50:09.22$vc4f8/valo=5,652.99 2006.225.07:50:09.22#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.07:50:09.22#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.07:50:09.22#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:09.22#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:50:09.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:50:09.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:50:09.22#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:50:09.22#ibcon#first serial, iclass 34, count 0 2006.225.07:50:09.22#ibcon#enter sib2, iclass 34, count 0 2006.225.07:50:09.22#ibcon#flushed, iclass 34, count 0 2006.225.07:50:09.22#ibcon#about to write, iclass 34, count 0 2006.225.07:50:09.22#ibcon#wrote, iclass 34, count 0 2006.225.07:50:09.22#ibcon#about to read 3, iclass 34, count 0 2006.225.07:50:09.24#ibcon#read 3, iclass 34, count 0 2006.225.07:50:09.24#ibcon#about to read 4, iclass 34, count 0 2006.225.07:50:09.24#ibcon#read 4, iclass 34, count 0 2006.225.07:50:09.24#ibcon#about to read 5, iclass 34, count 0 2006.225.07:50:09.24#ibcon#read 5, iclass 34, count 0 2006.225.07:50:09.24#ibcon#about to read 6, iclass 34, count 0 2006.225.07:50:09.24#ibcon#read 6, iclass 34, count 0 2006.225.07:50:09.24#ibcon#end of sib2, iclass 34, count 0 2006.225.07:50:09.24#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:50:09.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:50:09.24#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:50:09.24#ibcon#*before write, iclass 34, count 0 2006.225.07:50:09.24#ibcon#enter sib2, iclass 34, count 0 2006.225.07:50:09.24#ibcon#flushed, iclass 34, count 0 2006.225.07:50:09.24#ibcon#about to write, iclass 34, count 0 2006.225.07:50:09.24#ibcon#wrote, iclass 34, count 0 2006.225.07:50:09.24#ibcon#about to read 3, iclass 34, count 0 2006.225.07:50:09.28#ibcon#read 3, iclass 34, count 0 2006.225.07:50:09.28#ibcon#about to read 4, iclass 34, count 0 2006.225.07:50:09.28#ibcon#read 4, iclass 34, count 0 2006.225.07:50:09.28#ibcon#about to read 5, iclass 34, count 0 2006.225.07:50:09.28#ibcon#read 5, iclass 34, count 0 2006.225.07:50:09.28#ibcon#about to read 6, iclass 34, count 0 2006.225.07:50:09.28#ibcon#read 6, iclass 34, count 0 2006.225.07:50:09.28#ibcon#end of sib2, iclass 34, count 0 2006.225.07:50:09.28#ibcon#*after write, iclass 34, count 0 2006.225.07:50:09.28#ibcon#*before return 0, iclass 34, count 0 2006.225.07:50:09.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:50:09.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:50:09.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:50:09.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:50:09.28$vc4f8/va=5,7 2006.225.07:50:09.28#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.07:50:09.28#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.07:50:09.28#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:09.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:50:09.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:50:09.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:50:09.34#ibcon#enter wrdev, iclass 36, count 2 2006.225.07:50:09.34#ibcon#first serial, iclass 36, count 2 2006.225.07:50:09.34#ibcon#enter sib2, iclass 36, count 2 2006.225.07:50:09.34#ibcon#flushed, iclass 36, count 2 2006.225.07:50:09.34#ibcon#about to write, iclass 36, count 2 2006.225.07:50:09.34#ibcon#wrote, iclass 36, count 2 2006.225.07:50:09.34#ibcon#about to read 3, iclass 36, count 2 2006.225.07:50:09.36#ibcon#read 3, iclass 36, count 2 2006.225.07:50:09.36#ibcon#about to read 4, iclass 36, count 2 2006.225.07:50:09.36#ibcon#read 4, iclass 36, count 2 2006.225.07:50:09.36#ibcon#about to read 5, iclass 36, count 2 2006.225.07:50:09.36#ibcon#read 5, iclass 36, count 2 2006.225.07:50:09.36#ibcon#about to read 6, iclass 36, count 2 2006.225.07:50:09.36#ibcon#read 6, iclass 36, count 2 2006.225.07:50:09.36#ibcon#end of sib2, iclass 36, count 2 2006.225.07:50:09.36#ibcon#*mode == 0, iclass 36, count 2 2006.225.07:50:09.36#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.07:50:09.36#ibcon#[25=AT05-07\r\n] 2006.225.07:50:09.36#ibcon#*before write, iclass 36, count 2 2006.225.07:50:09.36#ibcon#enter sib2, iclass 36, count 2 2006.225.07:50:09.36#ibcon#flushed, iclass 36, count 2 2006.225.07:50:09.36#ibcon#about to write, iclass 36, count 2 2006.225.07:50:09.36#ibcon#wrote, iclass 36, count 2 2006.225.07:50:09.36#ibcon#about to read 3, iclass 36, count 2 2006.225.07:50:09.39#ibcon#read 3, iclass 36, count 2 2006.225.07:50:09.39#ibcon#about to read 4, iclass 36, count 2 2006.225.07:50:09.39#ibcon#read 4, iclass 36, count 2 2006.225.07:50:09.39#ibcon#about to read 5, iclass 36, count 2 2006.225.07:50:09.39#ibcon#read 5, iclass 36, count 2 2006.225.07:50:09.39#ibcon#about to read 6, iclass 36, count 2 2006.225.07:50:09.39#ibcon#read 6, iclass 36, count 2 2006.225.07:50:09.39#ibcon#end of sib2, iclass 36, count 2 2006.225.07:50:09.39#ibcon#*after write, iclass 36, count 2 2006.225.07:50:09.39#ibcon#*before return 0, iclass 36, count 2 2006.225.07:50:09.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:50:09.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:50:09.39#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.07:50:09.39#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:09.39#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:50:09.51#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:50:09.51#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:50:09.51#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:50:09.51#ibcon#first serial, iclass 36, count 0 2006.225.07:50:09.51#ibcon#enter sib2, iclass 36, count 0 2006.225.07:50:09.51#ibcon#flushed, iclass 36, count 0 2006.225.07:50:09.51#ibcon#about to write, iclass 36, count 0 2006.225.07:50:09.51#ibcon#wrote, iclass 36, count 0 2006.225.07:50:09.51#ibcon#about to read 3, iclass 36, count 0 2006.225.07:50:09.53#ibcon#read 3, iclass 36, count 0 2006.225.07:50:09.53#ibcon#about to read 4, iclass 36, count 0 2006.225.07:50:09.53#ibcon#read 4, iclass 36, count 0 2006.225.07:50:09.53#ibcon#about to read 5, iclass 36, count 0 2006.225.07:50:09.53#ibcon#read 5, iclass 36, count 0 2006.225.07:50:09.53#ibcon#about to read 6, iclass 36, count 0 2006.225.07:50:09.53#ibcon#read 6, iclass 36, count 0 2006.225.07:50:09.53#ibcon#end of sib2, iclass 36, count 0 2006.225.07:50:09.53#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:50:09.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:50:09.53#ibcon#[25=USB\r\n] 2006.225.07:50:09.53#ibcon#*before write, iclass 36, count 0 2006.225.07:50:09.53#ibcon#enter sib2, iclass 36, count 0 2006.225.07:50:09.53#ibcon#flushed, iclass 36, count 0 2006.225.07:50:09.53#ibcon#about to write, iclass 36, count 0 2006.225.07:50:09.53#ibcon#wrote, iclass 36, count 0 2006.225.07:50:09.53#ibcon#about to read 3, iclass 36, count 0 2006.225.07:50:09.56#ibcon#read 3, iclass 36, count 0 2006.225.07:50:09.56#ibcon#about to read 4, iclass 36, count 0 2006.225.07:50:09.56#ibcon#read 4, iclass 36, count 0 2006.225.07:50:09.56#ibcon#about to read 5, iclass 36, count 0 2006.225.07:50:09.56#ibcon#read 5, iclass 36, count 0 2006.225.07:50:09.56#ibcon#about to read 6, iclass 36, count 0 2006.225.07:50:09.56#ibcon#read 6, iclass 36, count 0 2006.225.07:50:09.56#ibcon#end of sib2, iclass 36, count 0 2006.225.07:50:09.56#ibcon#*after write, iclass 36, count 0 2006.225.07:50:09.56#ibcon#*before return 0, iclass 36, count 0 2006.225.07:50:09.56#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:50:09.56#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:50:09.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:50:09.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:50:09.56$vc4f8/valo=6,772.99 2006.225.07:50:09.56#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.07:50:09.56#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.07:50:09.56#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:09.56#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:50:09.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:50:09.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:50:09.56#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:50:09.56#ibcon#first serial, iclass 38, count 0 2006.225.07:50:09.56#ibcon#enter sib2, iclass 38, count 0 2006.225.07:50:09.56#ibcon#flushed, iclass 38, count 0 2006.225.07:50:09.56#ibcon#about to write, iclass 38, count 0 2006.225.07:50:09.56#ibcon#wrote, iclass 38, count 0 2006.225.07:50:09.56#ibcon#about to read 3, iclass 38, count 0 2006.225.07:50:09.59#ibcon#read 3, iclass 38, count 0 2006.225.07:50:09.59#ibcon#about to read 4, iclass 38, count 0 2006.225.07:50:09.59#ibcon#read 4, iclass 38, count 0 2006.225.07:50:09.59#ibcon#about to read 5, iclass 38, count 0 2006.225.07:50:09.59#ibcon#read 5, iclass 38, count 0 2006.225.07:50:09.59#ibcon#about to read 6, iclass 38, count 0 2006.225.07:50:09.59#ibcon#read 6, iclass 38, count 0 2006.225.07:50:09.59#ibcon#end of sib2, iclass 38, count 0 2006.225.07:50:09.59#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:50:09.59#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:50:09.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:50:09.59#ibcon#*before write, iclass 38, count 0 2006.225.07:50:09.59#ibcon#enter sib2, iclass 38, count 0 2006.225.07:50:09.59#ibcon#flushed, iclass 38, count 0 2006.225.07:50:09.59#ibcon#about to write, iclass 38, count 0 2006.225.07:50:09.59#ibcon#wrote, iclass 38, count 0 2006.225.07:50:09.59#ibcon#about to read 3, iclass 38, count 0 2006.225.07:50:09.63#ibcon#read 3, iclass 38, count 0 2006.225.07:50:09.63#ibcon#about to read 4, iclass 38, count 0 2006.225.07:50:09.63#ibcon#read 4, iclass 38, count 0 2006.225.07:50:09.63#ibcon#about to read 5, iclass 38, count 0 2006.225.07:50:09.63#ibcon#read 5, iclass 38, count 0 2006.225.07:50:09.63#ibcon#about to read 6, iclass 38, count 0 2006.225.07:50:09.63#ibcon#read 6, iclass 38, count 0 2006.225.07:50:09.63#ibcon#end of sib2, iclass 38, count 0 2006.225.07:50:09.63#ibcon#*after write, iclass 38, count 0 2006.225.07:50:09.63#ibcon#*before return 0, iclass 38, count 0 2006.225.07:50:09.63#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:50:09.63#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:50:09.63#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:50:09.63#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:50:09.63$vc4f8/va=6,6 2006.225.07:50:09.63#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.225.07:50:09.63#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.225.07:50:09.63#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:09.63#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:50:09.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:50:09.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:50:09.68#ibcon#enter wrdev, iclass 40, count 2 2006.225.07:50:09.68#ibcon#first serial, iclass 40, count 2 2006.225.07:50:09.68#ibcon#enter sib2, iclass 40, count 2 2006.225.07:50:09.68#ibcon#flushed, iclass 40, count 2 2006.225.07:50:09.68#ibcon#about to write, iclass 40, count 2 2006.225.07:50:09.68#ibcon#wrote, iclass 40, count 2 2006.225.07:50:09.68#ibcon#about to read 3, iclass 40, count 2 2006.225.07:50:09.70#ibcon#read 3, iclass 40, count 2 2006.225.07:50:09.70#ibcon#about to read 4, iclass 40, count 2 2006.225.07:50:09.70#ibcon#read 4, iclass 40, count 2 2006.225.07:50:09.70#ibcon#about to read 5, iclass 40, count 2 2006.225.07:50:09.70#ibcon#read 5, iclass 40, count 2 2006.225.07:50:09.70#ibcon#about to read 6, iclass 40, count 2 2006.225.07:50:09.70#ibcon#read 6, iclass 40, count 2 2006.225.07:50:09.70#ibcon#end of sib2, iclass 40, count 2 2006.225.07:50:09.70#ibcon#*mode == 0, iclass 40, count 2 2006.225.07:50:09.70#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.225.07:50:09.70#ibcon#[25=AT06-06\r\n] 2006.225.07:50:09.70#ibcon#*before write, iclass 40, count 2 2006.225.07:50:09.70#ibcon#enter sib2, iclass 40, count 2 2006.225.07:50:09.70#ibcon#flushed, iclass 40, count 2 2006.225.07:50:09.70#ibcon#about to write, iclass 40, count 2 2006.225.07:50:09.70#ibcon#wrote, iclass 40, count 2 2006.225.07:50:09.70#ibcon#about to read 3, iclass 40, count 2 2006.225.07:50:09.73#ibcon#read 3, iclass 40, count 2 2006.225.07:50:09.73#ibcon#about to read 4, iclass 40, count 2 2006.225.07:50:09.73#ibcon#read 4, iclass 40, count 2 2006.225.07:50:09.73#ibcon#about to read 5, iclass 40, count 2 2006.225.07:50:09.73#ibcon#read 5, iclass 40, count 2 2006.225.07:50:09.73#ibcon#about to read 6, iclass 40, count 2 2006.225.07:50:09.73#ibcon#read 6, iclass 40, count 2 2006.225.07:50:09.73#ibcon#end of sib2, iclass 40, count 2 2006.225.07:50:09.73#ibcon#*after write, iclass 40, count 2 2006.225.07:50:09.73#ibcon#*before return 0, iclass 40, count 2 2006.225.07:50:09.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:50:09.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:50:09.73#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.225.07:50:09.73#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:09.73#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:50:09.85#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:50:09.85#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:50:09.85#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:50:09.85#ibcon#first serial, iclass 40, count 0 2006.225.07:50:09.85#ibcon#enter sib2, iclass 40, count 0 2006.225.07:50:09.85#ibcon#flushed, iclass 40, count 0 2006.225.07:50:09.85#ibcon#about to write, iclass 40, count 0 2006.225.07:50:09.85#ibcon#wrote, iclass 40, count 0 2006.225.07:50:09.85#ibcon#about to read 3, iclass 40, count 0 2006.225.07:50:09.87#ibcon#read 3, iclass 40, count 0 2006.225.07:50:09.87#ibcon#about to read 4, iclass 40, count 0 2006.225.07:50:09.87#ibcon#read 4, iclass 40, count 0 2006.225.07:50:09.87#ibcon#about to read 5, iclass 40, count 0 2006.225.07:50:09.87#ibcon#read 5, iclass 40, count 0 2006.225.07:50:09.87#ibcon#about to read 6, iclass 40, count 0 2006.225.07:50:09.87#ibcon#read 6, iclass 40, count 0 2006.225.07:50:09.87#ibcon#end of sib2, iclass 40, count 0 2006.225.07:50:09.87#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:50:09.87#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:50:09.87#ibcon#[25=USB\r\n] 2006.225.07:50:09.87#ibcon#*before write, iclass 40, count 0 2006.225.07:50:09.87#ibcon#enter sib2, iclass 40, count 0 2006.225.07:50:09.87#ibcon#flushed, iclass 40, count 0 2006.225.07:50:09.87#ibcon#about to write, iclass 40, count 0 2006.225.07:50:09.87#ibcon#wrote, iclass 40, count 0 2006.225.07:50:09.87#ibcon#about to read 3, iclass 40, count 0 2006.225.07:50:09.90#ibcon#read 3, iclass 40, count 0 2006.225.07:50:09.90#ibcon#about to read 4, iclass 40, count 0 2006.225.07:50:09.90#ibcon#read 4, iclass 40, count 0 2006.225.07:50:09.90#ibcon#about to read 5, iclass 40, count 0 2006.225.07:50:09.90#ibcon#read 5, iclass 40, count 0 2006.225.07:50:09.90#ibcon#about to read 6, iclass 40, count 0 2006.225.07:50:09.90#ibcon#read 6, iclass 40, count 0 2006.225.07:50:09.90#ibcon#end of sib2, iclass 40, count 0 2006.225.07:50:09.90#ibcon#*after write, iclass 40, count 0 2006.225.07:50:09.90#ibcon#*before return 0, iclass 40, count 0 2006.225.07:50:09.90#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:50:09.90#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:50:09.90#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:50:09.90#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:50:09.90$vc4f8/valo=7,832.99 2006.225.07:50:09.90#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.07:50:09.90#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.07:50:09.90#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:09.90#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:50:09.90#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:50:09.90#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:50:09.90#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:50:09.90#ibcon#first serial, iclass 4, count 0 2006.225.07:50:09.90#ibcon#enter sib2, iclass 4, count 0 2006.225.07:50:09.90#ibcon#flushed, iclass 4, count 0 2006.225.07:50:09.90#ibcon#about to write, iclass 4, count 0 2006.225.07:50:09.90#ibcon#wrote, iclass 4, count 0 2006.225.07:50:09.90#ibcon#about to read 3, iclass 4, count 0 2006.225.07:50:09.92#ibcon#read 3, iclass 4, count 0 2006.225.07:50:09.92#ibcon#about to read 4, iclass 4, count 0 2006.225.07:50:09.92#ibcon#read 4, iclass 4, count 0 2006.225.07:50:09.92#ibcon#about to read 5, iclass 4, count 0 2006.225.07:50:09.92#ibcon#read 5, iclass 4, count 0 2006.225.07:50:09.92#ibcon#about to read 6, iclass 4, count 0 2006.225.07:50:09.92#ibcon#read 6, iclass 4, count 0 2006.225.07:50:09.92#ibcon#end of sib2, iclass 4, count 0 2006.225.07:50:09.92#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:50:09.92#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:50:09.92#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:50:09.92#ibcon#*before write, iclass 4, count 0 2006.225.07:50:09.92#ibcon#enter sib2, iclass 4, count 0 2006.225.07:50:09.92#ibcon#flushed, iclass 4, count 0 2006.225.07:50:09.92#ibcon#about to write, iclass 4, count 0 2006.225.07:50:09.92#ibcon#wrote, iclass 4, count 0 2006.225.07:50:09.92#ibcon#about to read 3, iclass 4, count 0 2006.225.07:50:09.96#ibcon#read 3, iclass 4, count 0 2006.225.07:50:09.96#ibcon#about to read 4, iclass 4, count 0 2006.225.07:50:09.96#ibcon#read 4, iclass 4, count 0 2006.225.07:50:09.96#ibcon#about to read 5, iclass 4, count 0 2006.225.07:50:09.96#ibcon#read 5, iclass 4, count 0 2006.225.07:50:09.96#ibcon#about to read 6, iclass 4, count 0 2006.225.07:50:09.96#ibcon#read 6, iclass 4, count 0 2006.225.07:50:09.96#ibcon#end of sib2, iclass 4, count 0 2006.225.07:50:09.96#ibcon#*after write, iclass 4, count 0 2006.225.07:50:09.96#ibcon#*before return 0, iclass 4, count 0 2006.225.07:50:09.96#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:50:09.96#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:50:09.96#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:50:09.96#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:50:09.96$vc4f8/va=7,6 2006.225.07:50:09.96#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.225.07:50:09.96#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.225.07:50:09.96#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:09.96#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:50:10.02#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:50:10.02#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:50:10.02#ibcon#enter wrdev, iclass 6, count 2 2006.225.07:50:10.02#ibcon#first serial, iclass 6, count 2 2006.225.07:50:10.02#ibcon#enter sib2, iclass 6, count 2 2006.225.07:50:10.02#ibcon#flushed, iclass 6, count 2 2006.225.07:50:10.02#ibcon#about to write, iclass 6, count 2 2006.225.07:50:10.02#ibcon#wrote, iclass 6, count 2 2006.225.07:50:10.02#ibcon#about to read 3, iclass 6, count 2 2006.225.07:50:10.04#ibcon#read 3, iclass 6, count 2 2006.225.07:50:10.04#ibcon#about to read 4, iclass 6, count 2 2006.225.07:50:10.04#ibcon#read 4, iclass 6, count 2 2006.225.07:50:10.04#ibcon#about to read 5, iclass 6, count 2 2006.225.07:50:10.04#ibcon#read 5, iclass 6, count 2 2006.225.07:50:10.04#ibcon#about to read 6, iclass 6, count 2 2006.225.07:50:10.04#ibcon#read 6, iclass 6, count 2 2006.225.07:50:10.04#ibcon#end of sib2, iclass 6, count 2 2006.225.07:50:10.04#ibcon#*mode == 0, iclass 6, count 2 2006.225.07:50:10.04#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.225.07:50:10.04#ibcon#[25=AT07-06\r\n] 2006.225.07:50:10.04#ibcon#*before write, iclass 6, count 2 2006.225.07:50:10.04#ibcon#enter sib2, iclass 6, count 2 2006.225.07:50:10.04#ibcon#flushed, iclass 6, count 2 2006.225.07:50:10.04#ibcon#about to write, iclass 6, count 2 2006.225.07:50:10.04#ibcon#wrote, iclass 6, count 2 2006.225.07:50:10.04#ibcon#about to read 3, iclass 6, count 2 2006.225.07:50:10.07#ibcon#read 3, iclass 6, count 2 2006.225.07:50:10.07#ibcon#about to read 4, iclass 6, count 2 2006.225.07:50:10.07#ibcon#read 4, iclass 6, count 2 2006.225.07:50:10.07#ibcon#about to read 5, iclass 6, count 2 2006.225.07:50:10.07#ibcon#read 5, iclass 6, count 2 2006.225.07:50:10.07#ibcon#about to read 6, iclass 6, count 2 2006.225.07:50:10.07#ibcon#read 6, iclass 6, count 2 2006.225.07:50:10.07#ibcon#end of sib2, iclass 6, count 2 2006.225.07:50:10.07#ibcon#*after write, iclass 6, count 2 2006.225.07:50:10.07#ibcon#*before return 0, iclass 6, count 2 2006.225.07:50:10.07#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:50:10.07#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:50:10.07#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.225.07:50:10.07#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:10.07#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:50:10.19#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:50:10.19#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:50:10.19#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:50:10.19#ibcon#first serial, iclass 6, count 0 2006.225.07:50:10.19#ibcon#enter sib2, iclass 6, count 0 2006.225.07:50:10.19#ibcon#flushed, iclass 6, count 0 2006.225.07:50:10.19#ibcon#about to write, iclass 6, count 0 2006.225.07:50:10.19#ibcon#wrote, iclass 6, count 0 2006.225.07:50:10.19#ibcon#about to read 3, iclass 6, count 0 2006.225.07:50:10.21#ibcon#read 3, iclass 6, count 0 2006.225.07:50:10.21#ibcon#about to read 4, iclass 6, count 0 2006.225.07:50:10.21#ibcon#read 4, iclass 6, count 0 2006.225.07:50:10.21#ibcon#about to read 5, iclass 6, count 0 2006.225.07:50:10.21#ibcon#read 5, iclass 6, count 0 2006.225.07:50:10.21#ibcon#about to read 6, iclass 6, count 0 2006.225.07:50:10.21#ibcon#read 6, iclass 6, count 0 2006.225.07:50:10.21#ibcon#end of sib2, iclass 6, count 0 2006.225.07:50:10.21#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:50:10.21#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:50:10.21#ibcon#[25=USB\r\n] 2006.225.07:50:10.21#ibcon#*before write, iclass 6, count 0 2006.225.07:50:10.21#ibcon#enter sib2, iclass 6, count 0 2006.225.07:50:10.21#ibcon#flushed, iclass 6, count 0 2006.225.07:50:10.21#ibcon#about to write, iclass 6, count 0 2006.225.07:50:10.21#ibcon#wrote, iclass 6, count 0 2006.225.07:50:10.21#ibcon#about to read 3, iclass 6, count 0 2006.225.07:50:10.24#ibcon#read 3, iclass 6, count 0 2006.225.07:50:10.24#ibcon#about to read 4, iclass 6, count 0 2006.225.07:50:10.24#ibcon#read 4, iclass 6, count 0 2006.225.07:50:10.24#ibcon#about to read 5, iclass 6, count 0 2006.225.07:50:10.24#ibcon#read 5, iclass 6, count 0 2006.225.07:50:10.24#ibcon#about to read 6, iclass 6, count 0 2006.225.07:50:10.24#ibcon#read 6, iclass 6, count 0 2006.225.07:50:10.24#ibcon#end of sib2, iclass 6, count 0 2006.225.07:50:10.24#ibcon#*after write, iclass 6, count 0 2006.225.07:50:10.24#ibcon#*before return 0, iclass 6, count 0 2006.225.07:50:10.24#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:50:10.24#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:50:10.24#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:50:10.24#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:50:10.24$vc4f8/valo=8,852.99 2006.225.07:50:10.24#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.07:50:10.24#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.07:50:10.24#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:10.24#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:50:10.24#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:50:10.24#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:50:10.24#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:50:10.24#ibcon#first serial, iclass 10, count 0 2006.225.07:50:10.24#ibcon#enter sib2, iclass 10, count 0 2006.225.07:50:10.24#ibcon#flushed, iclass 10, count 0 2006.225.07:50:10.24#ibcon#about to write, iclass 10, count 0 2006.225.07:50:10.24#ibcon#wrote, iclass 10, count 0 2006.225.07:50:10.24#ibcon#about to read 3, iclass 10, count 0 2006.225.07:50:10.26#ibcon#read 3, iclass 10, count 0 2006.225.07:50:10.26#ibcon#about to read 4, iclass 10, count 0 2006.225.07:50:10.26#ibcon#read 4, iclass 10, count 0 2006.225.07:50:10.26#ibcon#about to read 5, iclass 10, count 0 2006.225.07:50:10.26#ibcon#read 5, iclass 10, count 0 2006.225.07:50:10.26#ibcon#about to read 6, iclass 10, count 0 2006.225.07:50:10.26#ibcon#read 6, iclass 10, count 0 2006.225.07:50:10.26#ibcon#end of sib2, iclass 10, count 0 2006.225.07:50:10.26#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:50:10.26#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:50:10.26#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:50:10.26#ibcon#*before write, iclass 10, count 0 2006.225.07:50:10.26#ibcon#enter sib2, iclass 10, count 0 2006.225.07:50:10.26#ibcon#flushed, iclass 10, count 0 2006.225.07:50:10.26#ibcon#about to write, iclass 10, count 0 2006.225.07:50:10.26#ibcon#wrote, iclass 10, count 0 2006.225.07:50:10.26#ibcon#about to read 3, iclass 10, count 0 2006.225.07:50:10.30#ibcon#read 3, iclass 10, count 0 2006.225.07:50:10.30#ibcon#about to read 4, iclass 10, count 0 2006.225.07:50:10.30#ibcon#read 4, iclass 10, count 0 2006.225.07:50:10.30#ibcon#about to read 5, iclass 10, count 0 2006.225.07:50:10.30#ibcon#read 5, iclass 10, count 0 2006.225.07:50:10.30#ibcon#about to read 6, iclass 10, count 0 2006.225.07:50:10.30#ibcon#read 6, iclass 10, count 0 2006.225.07:50:10.30#ibcon#end of sib2, iclass 10, count 0 2006.225.07:50:10.30#ibcon#*after write, iclass 10, count 0 2006.225.07:50:10.30#ibcon#*before return 0, iclass 10, count 0 2006.225.07:50:10.30#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:50:10.30#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:50:10.30#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:50:10.30#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:50:10.30$vc4f8/va=8,7 2006.225.07:50:10.30#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.07:50:10.30#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.07:50:10.30#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:10.30#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:50:10.36#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:50:10.36#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:50:10.36#ibcon#enter wrdev, iclass 12, count 2 2006.225.07:50:10.36#ibcon#first serial, iclass 12, count 2 2006.225.07:50:10.36#ibcon#enter sib2, iclass 12, count 2 2006.225.07:50:10.36#ibcon#flushed, iclass 12, count 2 2006.225.07:50:10.36#ibcon#about to write, iclass 12, count 2 2006.225.07:50:10.36#ibcon#wrote, iclass 12, count 2 2006.225.07:50:10.36#ibcon#about to read 3, iclass 12, count 2 2006.225.07:50:10.38#ibcon#read 3, iclass 12, count 2 2006.225.07:50:10.38#ibcon#about to read 4, iclass 12, count 2 2006.225.07:50:10.38#ibcon#read 4, iclass 12, count 2 2006.225.07:50:10.38#ibcon#about to read 5, iclass 12, count 2 2006.225.07:50:10.38#ibcon#read 5, iclass 12, count 2 2006.225.07:50:10.38#ibcon#about to read 6, iclass 12, count 2 2006.225.07:50:10.38#ibcon#read 6, iclass 12, count 2 2006.225.07:50:10.38#ibcon#end of sib2, iclass 12, count 2 2006.225.07:50:10.38#ibcon#*mode == 0, iclass 12, count 2 2006.225.07:50:10.38#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.07:50:10.38#ibcon#[25=AT08-07\r\n] 2006.225.07:50:10.38#ibcon#*before write, iclass 12, count 2 2006.225.07:50:10.38#ibcon#enter sib2, iclass 12, count 2 2006.225.07:50:10.38#ibcon#flushed, iclass 12, count 2 2006.225.07:50:10.38#ibcon#about to write, iclass 12, count 2 2006.225.07:50:10.38#ibcon#wrote, iclass 12, count 2 2006.225.07:50:10.38#ibcon#about to read 3, iclass 12, count 2 2006.225.07:50:10.41#ibcon#read 3, iclass 12, count 2 2006.225.07:50:10.41#ibcon#about to read 4, iclass 12, count 2 2006.225.07:50:10.41#ibcon#read 4, iclass 12, count 2 2006.225.07:50:10.41#ibcon#about to read 5, iclass 12, count 2 2006.225.07:50:10.41#ibcon#read 5, iclass 12, count 2 2006.225.07:50:10.41#ibcon#about to read 6, iclass 12, count 2 2006.225.07:50:10.41#ibcon#read 6, iclass 12, count 2 2006.225.07:50:10.41#ibcon#end of sib2, iclass 12, count 2 2006.225.07:50:10.41#ibcon#*after write, iclass 12, count 2 2006.225.07:50:10.41#ibcon#*before return 0, iclass 12, count 2 2006.225.07:50:10.41#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:50:10.41#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:50:10.41#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.07:50:10.41#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:10.41#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:50:10.53#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:50:10.53#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:50:10.53#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:50:10.53#ibcon#first serial, iclass 12, count 0 2006.225.07:50:10.53#ibcon#enter sib2, iclass 12, count 0 2006.225.07:50:10.53#ibcon#flushed, iclass 12, count 0 2006.225.07:50:10.53#ibcon#about to write, iclass 12, count 0 2006.225.07:50:10.53#ibcon#wrote, iclass 12, count 0 2006.225.07:50:10.53#ibcon#about to read 3, iclass 12, count 0 2006.225.07:50:10.55#ibcon#read 3, iclass 12, count 0 2006.225.07:50:10.55#ibcon#about to read 4, iclass 12, count 0 2006.225.07:50:10.55#ibcon#read 4, iclass 12, count 0 2006.225.07:50:10.55#ibcon#about to read 5, iclass 12, count 0 2006.225.07:50:10.55#ibcon#read 5, iclass 12, count 0 2006.225.07:50:10.55#ibcon#about to read 6, iclass 12, count 0 2006.225.07:50:10.55#ibcon#read 6, iclass 12, count 0 2006.225.07:50:10.55#ibcon#end of sib2, iclass 12, count 0 2006.225.07:50:10.55#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:50:10.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:50:10.55#ibcon#[25=USB\r\n] 2006.225.07:50:10.55#ibcon#*before write, iclass 12, count 0 2006.225.07:50:10.55#ibcon#enter sib2, iclass 12, count 0 2006.225.07:50:10.55#ibcon#flushed, iclass 12, count 0 2006.225.07:50:10.55#ibcon#about to write, iclass 12, count 0 2006.225.07:50:10.55#ibcon#wrote, iclass 12, count 0 2006.225.07:50:10.55#ibcon#about to read 3, iclass 12, count 0 2006.225.07:50:10.58#ibcon#read 3, iclass 12, count 0 2006.225.07:50:10.58#ibcon#about to read 4, iclass 12, count 0 2006.225.07:50:10.58#ibcon#read 4, iclass 12, count 0 2006.225.07:50:10.58#ibcon#about to read 5, iclass 12, count 0 2006.225.07:50:10.58#ibcon#read 5, iclass 12, count 0 2006.225.07:50:10.58#ibcon#about to read 6, iclass 12, count 0 2006.225.07:50:10.58#ibcon#read 6, iclass 12, count 0 2006.225.07:50:10.58#ibcon#end of sib2, iclass 12, count 0 2006.225.07:50:10.58#ibcon#*after write, iclass 12, count 0 2006.225.07:50:10.58#ibcon#*before return 0, iclass 12, count 0 2006.225.07:50:10.58#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:50:10.58#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:50:10.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:50:10.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:50:10.58$vc4f8/vblo=1,632.99 2006.225.07:50:10.58#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.07:50:10.58#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.07:50:10.58#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:10.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:50:10.58#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:50:10.58#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:50:10.58#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:50:10.58#ibcon#first serial, iclass 14, count 0 2006.225.07:50:10.58#ibcon#enter sib2, iclass 14, count 0 2006.225.07:50:10.58#ibcon#flushed, iclass 14, count 0 2006.225.07:50:10.58#ibcon#about to write, iclass 14, count 0 2006.225.07:50:10.58#ibcon#wrote, iclass 14, count 0 2006.225.07:50:10.58#ibcon#about to read 3, iclass 14, count 0 2006.225.07:50:10.60#ibcon#read 3, iclass 14, count 0 2006.225.07:50:10.60#ibcon#about to read 4, iclass 14, count 0 2006.225.07:50:10.60#ibcon#read 4, iclass 14, count 0 2006.225.07:50:10.60#ibcon#about to read 5, iclass 14, count 0 2006.225.07:50:10.60#ibcon#read 5, iclass 14, count 0 2006.225.07:50:10.60#ibcon#about to read 6, iclass 14, count 0 2006.225.07:50:10.60#ibcon#read 6, iclass 14, count 0 2006.225.07:50:10.60#ibcon#end of sib2, iclass 14, count 0 2006.225.07:50:10.60#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:50:10.60#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:50:10.60#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:50:10.60#ibcon#*before write, iclass 14, count 0 2006.225.07:50:10.60#ibcon#enter sib2, iclass 14, count 0 2006.225.07:50:10.60#ibcon#flushed, iclass 14, count 0 2006.225.07:50:10.60#ibcon#about to write, iclass 14, count 0 2006.225.07:50:10.60#ibcon#wrote, iclass 14, count 0 2006.225.07:50:10.60#ibcon#about to read 3, iclass 14, count 0 2006.225.07:50:10.64#ibcon#read 3, iclass 14, count 0 2006.225.07:50:10.64#ibcon#about to read 4, iclass 14, count 0 2006.225.07:50:10.64#ibcon#read 4, iclass 14, count 0 2006.225.07:50:10.64#ibcon#about to read 5, iclass 14, count 0 2006.225.07:50:10.64#ibcon#read 5, iclass 14, count 0 2006.225.07:50:10.64#ibcon#about to read 6, iclass 14, count 0 2006.225.07:50:10.64#ibcon#read 6, iclass 14, count 0 2006.225.07:50:10.64#ibcon#end of sib2, iclass 14, count 0 2006.225.07:50:10.64#ibcon#*after write, iclass 14, count 0 2006.225.07:50:10.64#ibcon#*before return 0, iclass 14, count 0 2006.225.07:50:10.64#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:50:10.64#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:50:10.64#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:50:10.64#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:50:10.64$vc4f8/vb=1,4 2006.225.07:50:10.64#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.07:50:10.64#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.07:50:10.64#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:10.64#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:50:10.64#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:50:10.64#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:50:10.64#ibcon#enter wrdev, iclass 16, count 2 2006.225.07:50:10.64#ibcon#first serial, iclass 16, count 2 2006.225.07:50:10.64#ibcon#enter sib2, iclass 16, count 2 2006.225.07:50:10.64#ibcon#flushed, iclass 16, count 2 2006.225.07:50:10.64#ibcon#about to write, iclass 16, count 2 2006.225.07:50:10.64#ibcon#wrote, iclass 16, count 2 2006.225.07:50:10.64#ibcon#about to read 3, iclass 16, count 2 2006.225.07:50:10.66#ibcon#read 3, iclass 16, count 2 2006.225.07:50:10.66#ibcon#about to read 4, iclass 16, count 2 2006.225.07:50:10.66#ibcon#read 4, iclass 16, count 2 2006.225.07:50:10.66#ibcon#about to read 5, iclass 16, count 2 2006.225.07:50:10.66#ibcon#read 5, iclass 16, count 2 2006.225.07:50:10.66#ibcon#about to read 6, iclass 16, count 2 2006.225.07:50:10.66#ibcon#read 6, iclass 16, count 2 2006.225.07:50:10.66#ibcon#end of sib2, iclass 16, count 2 2006.225.07:50:10.66#ibcon#*mode == 0, iclass 16, count 2 2006.225.07:50:10.66#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.07:50:10.66#ibcon#[27=AT01-04\r\n] 2006.225.07:50:10.66#ibcon#*before write, iclass 16, count 2 2006.225.07:50:10.66#ibcon#enter sib2, iclass 16, count 2 2006.225.07:50:10.66#ibcon#flushed, iclass 16, count 2 2006.225.07:50:10.66#ibcon#about to write, iclass 16, count 2 2006.225.07:50:10.66#ibcon#wrote, iclass 16, count 2 2006.225.07:50:10.66#ibcon#about to read 3, iclass 16, count 2 2006.225.07:50:10.69#ibcon#read 3, iclass 16, count 2 2006.225.07:50:10.69#ibcon#about to read 4, iclass 16, count 2 2006.225.07:50:10.69#ibcon#read 4, iclass 16, count 2 2006.225.07:50:10.69#ibcon#about to read 5, iclass 16, count 2 2006.225.07:50:10.69#ibcon#read 5, iclass 16, count 2 2006.225.07:50:10.69#ibcon#about to read 6, iclass 16, count 2 2006.225.07:50:10.69#ibcon#read 6, iclass 16, count 2 2006.225.07:50:10.69#ibcon#end of sib2, iclass 16, count 2 2006.225.07:50:10.69#ibcon#*after write, iclass 16, count 2 2006.225.07:50:10.69#ibcon#*before return 0, iclass 16, count 2 2006.225.07:50:10.69#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:50:10.69#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:50:10.69#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.07:50:10.69#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:10.69#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:50:10.81#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:50:10.81#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:50:10.81#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:50:10.81#ibcon#first serial, iclass 16, count 0 2006.225.07:50:10.81#ibcon#enter sib2, iclass 16, count 0 2006.225.07:50:10.81#ibcon#flushed, iclass 16, count 0 2006.225.07:50:10.81#ibcon#about to write, iclass 16, count 0 2006.225.07:50:10.81#ibcon#wrote, iclass 16, count 0 2006.225.07:50:10.81#ibcon#about to read 3, iclass 16, count 0 2006.225.07:50:10.83#ibcon#read 3, iclass 16, count 0 2006.225.07:50:10.83#ibcon#about to read 4, iclass 16, count 0 2006.225.07:50:10.83#ibcon#read 4, iclass 16, count 0 2006.225.07:50:10.83#ibcon#about to read 5, iclass 16, count 0 2006.225.07:50:10.83#ibcon#read 5, iclass 16, count 0 2006.225.07:50:10.83#ibcon#about to read 6, iclass 16, count 0 2006.225.07:50:10.83#ibcon#read 6, iclass 16, count 0 2006.225.07:50:10.83#ibcon#end of sib2, iclass 16, count 0 2006.225.07:50:10.83#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:50:10.83#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:50:10.83#ibcon#[27=USB\r\n] 2006.225.07:50:10.83#ibcon#*before write, iclass 16, count 0 2006.225.07:50:10.83#ibcon#enter sib2, iclass 16, count 0 2006.225.07:50:10.83#ibcon#flushed, iclass 16, count 0 2006.225.07:50:10.83#ibcon#about to write, iclass 16, count 0 2006.225.07:50:10.83#ibcon#wrote, iclass 16, count 0 2006.225.07:50:10.83#ibcon#about to read 3, iclass 16, count 0 2006.225.07:50:10.86#ibcon#read 3, iclass 16, count 0 2006.225.07:50:10.86#ibcon#about to read 4, iclass 16, count 0 2006.225.07:50:10.86#ibcon#read 4, iclass 16, count 0 2006.225.07:50:10.86#ibcon#about to read 5, iclass 16, count 0 2006.225.07:50:10.86#ibcon#read 5, iclass 16, count 0 2006.225.07:50:10.86#ibcon#about to read 6, iclass 16, count 0 2006.225.07:50:10.86#ibcon#read 6, iclass 16, count 0 2006.225.07:50:10.86#ibcon#end of sib2, iclass 16, count 0 2006.225.07:50:10.86#ibcon#*after write, iclass 16, count 0 2006.225.07:50:10.86#ibcon#*before return 0, iclass 16, count 0 2006.225.07:50:10.86#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:50:10.86#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:50:10.86#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:50:10.86#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:50:10.86$vc4f8/vblo=2,640.99 2006.225.07:50:10.86#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.07:50:10.86#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.07:50:10.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:10.86#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:50:10.86#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:50:10.86#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:50:10.86#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:50:10.86#ibcon#first serial, iclass 18, count 0 2006.225.07:50:10.86#ibcon#enter sib2, iclass 18, count 0 2006.225.07:50:10.86#ibcon#flushed, iclass 18, count 0 2006.225.07:50:10.86#ibcon#about to write, iclass 18, count 0 2006.225.07:50:10.86#ibcon#wrote, iclass 18, count 0 2006.225.07:50:10.86#ibcon#about to read 3, iclass 18, count 0 2006.225.07:50:10.88#ibcon#read 3, iclass 18, count 0 2006.225.07:50:10.88#ibcon#about to read 4, iclass 18, count 0 2006.225.07:50:10.88#ibcon#read 4, iclass 18, count 0 2006.225.07:50:10.88#ibcon#about to read 5, iclass 18, count 0 2006.225.07:50:10.88#ibcon#read 5, iclass 18, count 0 2006.225.07:50:10.88#ibcon#about to read 6, iclass 18, count 0 2006.225.07:50:10.88#ibcon#read 6, iclass 18, count 0 2006.225.07:50:10.88#ibcon#end of sib2, iclass 18, count 0 2006.225.07:50:10.88#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:50:10.88#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:50:10.88#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:50:10.88#ibcon#*before write, iclass 18, count 0 2006.225.07:50:10.88#ibcon#enter sib2, iclass 18, count 0 2006.225.07:50:10.88#ibcon#flushed, iclass 18, count 0 2006.225.07:50:10.88#ibcon#about to write, iclass 18, count 0 2006.225.07:50:10.88#ibcon#wrote, iclass 18, count 0 2006.225.07:50:10.88#ibcon#about to read 3, iclass 18, count 0 2006.225.07:50:10.92#ibcon#read 3, iclass 18, count 0 2006.225.07:50:10.92#ibcon#about to read 4, iclass 18, count 0 2006.225.07:50:10.92#ibcon#read 4, iclass 18, count 0 2006.225.07:50:10.92#ibcon#about to read 5, iclass 18, count 0 2006.225.07:50:10.92#ibcon#read 5, iclass 18, count 0 2006.225.07:50:10.92#ibcon#about to read 6, iclass 18, count 0 2006.225.07:50:10.92#ibcon#read 6, iclass 18, count 0 2006.225.07:50:10.92#ibcon#end of sib2, iclass 18, count 0 2006.225.07:50:10.92#ibcon#*after write, iclass 18, count 0 2006.225.07:50:10.92#ibcon#*before return 0, iclass 18, count 0 2006.225.07:50:10.92#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:50:10.92#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:50:10.92#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:50:10.92#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:50:10.92$vc4f8/vb=2,4 2006.225.07:50:10.92#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.07:50:10.92#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.07:50:10.92#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:10.92#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:50:10.98#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:50:10.98#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:50:10.98#ibcon#enter wrdev, iclass 20, count 2 2006.225.07:50:10.98#ibcon#first serial, iclass 20, count 2 2006.225.07:50:10.98#ibcon#enter sib2, iclass 20, count 2 2006.225.07:50:10.98#ibcon#flushed, iclass 20, count 2 2006.225.07:50:10.98#ibcon#about to write, iclass 20, count 2 2006.225.07:50:10.98#ibcon#wrote, iclass 20, count 2 2006.225.07:50:10.98#ibcon#about to read 3, iclass 20, count 2 2006.225.07:50:11.00#ibcon#read 3, iclass 20, count 2 2006.225.07:50:11.00#ibcon#about to read 4, iclass 20, count 2 2006.225.07:50:11.00#ibcon#read 4, iclass 20, count 2 2006.225.07:50:11.00#ibcon#about to read 5, iclass 20, count 2 2006.225.07:50:11.00#ibcon#read 5, iclass 20, count 2 2006.225.07:50:11.00#ibcon#about to read 6, iclass 20, count 2 2006.225.07:50:11.00#ibcon#read 6, iclass 20, count 2 2006.225.07:50:11.00#ibcon#end of sib2, iclass 20, count 2 2006.225.07:50:11.00#ibcon#*mode == 0, iclass 20, count 2 2006.225.07:50:11.00#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.07:50:11.00#ibcon#[27=AT02-04\r\n] 2006.225.07:50:11.00#ibcon#*before write, iclass 20, count 2 2006.225.07:50:11.00#ibcon#enter sib2, iclass 20, count 2 2006.225.07:50:11.00#ibcon#flushed, iclass 20, count 2 2006.225.07:50:11.00#ibcon#about to write, iclass 20, count 2 2006.225.07:50:11.00#ibcon#wrote, iclass 20, count 2 2006.225.07:50:11.00#ibcon#about to read 3, iclass 20, count 2 2006.225.07:50:11.03#ibcon#read 3, iclass 20, count 2 2006.225.07:50:11.03#ibcon#about to read 4, iclass 20, count 2 2006.225.07:50:11.03#ibcon#read 4, iclass 20, count 2 2006.225.07:50:11.03#ibcon#about to read 5, iclass 20, count 2 2006.225.07:50:11.03#ibcon#read 5, iclass 20, count 2 2006.225.07:50:11.03#ibcon#about to read 6, iclass 20, count 2 2006.225.07:50:11.03#ibcon#read 6, iclass 20, count 2 2006.225.07:50:11.03#ibcon#end of sib2, iclass 20, count 2 2006.225.07:50:11.03#ibcon#*after write, iclass 20, count 2 2006.225.07:50:11.03#ibcon#*before return 0, iclass 20, count 2 2006.225.07:50:11.03#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:50:11.03#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:50:11.03#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.07:50:11.03#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:11.03#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:50:11.15#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:50:11.15#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:50:11.15#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:50:11.15#ibcon#first serial, iclass 20, count 0 2006.225.07:50:11.15#ibcon#enter sib2, iclass 20, count 0 2006.225.07:50:11.15#ibcon#flushed, iclass 20, count 0 2006.225.07:50:11.15#ibcon#about to write, iclass 20, count 0 2006.225.07:50:11.15#ibcon#wrote, iclass 20, count 0 2006.225.07:50:11.15#ibcon#about to read 3, iclass 20, count 0 2006.225.07:50:11.17#ibcon#read 3, iclass 20, count 0 2006.225.07:50:11.17#ibcon#about to read 4, iclass 20, count 0 2006.225.07:50:11.17#ibcon#read 4, iclass 20, count 0 2006.225.07:50:11.17#ibcon#about to read 5, iclass 20, count 0 2006.225.07:50:11.17#ibcon#read 5, iclass 20, count 0 2006.225.07:50:11.17#ibcon#about to read 6, iclass 20, count 0 2006.225.07:50:11.17#ibcon#read 6, iclass 20, count 0 2006.225.07:50:11.17#ibcon#end of sib2, iclass 20, count 0 2006.225.07:50:11.17#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:50:11.17#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:50:11.17#ibcon#[27=USB\r\n] 2006.225.07:50:11.17#ibcon#*before write, iclass 20, count 0 2006.225.07:50:11.17#ibcon#enter sib2, iclass 20, count 0 2006.225.07:50:11.17#ibcon#flushed, iclass 20, count 0 2006.225.07:50:11.17#ibcon#about to write, iclass 20, count 0 2006.225.07:50:11.17#ibcon#wrote, iclass 20, count 0 2006.225.07:50:11.17#ibcon#about to read 3, iclass 20, count 0 2006.225.07:50:11.20#ibcon#read 3, iclass 20, count 0 2006.225.07:50:11.20#ibcon#about to read 4, iclass 20, count 0 2006.225.07:50:11.20#ibcon#read 4, iclass 20, count 0 2006.225.07:50:11.20#ibcon#about to read 5, iclass 20, count 0 2006.225.07:50:11.20#ibcon#read 5, iclass 20, count 0 2006.225.07:50:11.20#ibcon#about to read 6, iclass 20, count 0 2006.225.07:50:11.20#ibcon#read 6, iclass 20, count 0 2006.225.07:50:11.20#ibcon#end of sib2, iclass 20, count 0 2006.225.07:50:11.20#ibcon#*after write, iclass 20, count 0 2006.225.07:50:11.20#ibcon#*before return 0, iclass 20, count 0 2006.225.07:50:11.20#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:50:11.20#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:50:11.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:50:11.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:50:11.20$vc4f8/vblo=3,656.99 2006.225.07:50:11.20#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.07:50:11.20#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.07:50:11.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:11.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:50:11.20#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:50:11.20#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:50:11.20#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:50:11.20#ibcon#first serial, iclass 22, count 0 2006.225.07:50:11.20#ibcon#enter sib2, iclass 22, count 0 2006.225.07:50:11.20#ibcon#flushed, iclass 22, count 0 2006.225.07:50:11.20#ibcon#about to write, iclass 22, count 0 2006.225.07:50:11.20#ibcon#wrote, iclass 22, count 0 2006.225.07:50:11.20#ibcon#about to read 3, iclass 22, count 0 2006.225.07:50:11.22#ibcon#read 3, iclass 22, count 0 2006.225.07:50:11.22#ibcon#about to read 4, iclass 22, count 0 2006.225.07:50:11.22#ibcon#read 4, iclass 22, count 0 2006.225.07:50:11.22#ibcon#about to read 5, iclass 22, count 0 2006.225.07:50:11.22#ibcon#read 5, iclass 22, count 0 2006.225.07:50:11.22#ibcon#about to read 6, iclass 22, count 0 2006.225.07:50:11.22#ibcon#read 6, iclass 22, count 0 2006.225.07:50:11.22#ibcon#end of sib2, iclass 22, count 0 2006.225.07:50:11.22#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:50:11.22#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:50:11.22#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:50:11.22#ibcon#*before write, iclass 22, count 0 2006.225.07:50:11.22#ibcon#enter sib2, iclass 22, count 0 2006.225.07:50:11.22#ibcon#flushed, iclass 22, count 0 2006.225.07:50:11.22#ibcon#about to write, iclass 22, count 0 2006.225.07:50:11.22#ibcon#wrote, iclass 22, count 0 2006.225.07:50:11.22#ibcon#about to read 3, iclass 22, count 0 2006.225.07:50:11.26#ibcon#read 3, iclass 22, count 0 2006.225.07:50:11.26#ibcon#about to read 4, iclass 22, count 0 2006.225.07:50:11.26#ibcon#read 4, iclass 22, count 0 2006.225.07:50:11.26#ibcon#about to read 5, iclass 22, count 0 2006.225.07:50:11.26#ibcon#read 5, iclass 22, count 0 2006.225.07:50:11.26#ibcon#about to read 6, iclass 22, count 0 2006.225.07:50:11.26#ibcon#read 6, iclass 22, count 0 2006.225.07:50:11.26#ibcon#end of sib2, iclass 22, count 0 2006.225.07:50:11.26#ibcon#*after write, iclass 22, count 0 2006.225.07:50:11.26#ibcon#*before return 0, iclass 22, count 0 2006.225.07:50:11.26#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:50:11.26#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:50:11.26#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:50:11.26#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:50:11.26$vc4f8/vb=3,4 2006.225.07:50:11.26#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.07:50:11.26#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.07:50:11.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:11.26#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:50:11.32#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:50:11.32#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:50:11.32#ibcon#enter wrdev, iclass 24, count 2 2006.225.07:50:11.32#ibcon#first serial, iclass 24, count 2 2006.225.07:50:11.32#ibcon#enter sib2, iclass 24, count 2 2006.225.07:50:11.32#ibcon#flushed, iclass 24, count 2 2006.225.07:50:11.32#ibcon#about to write, iclass 24, count 2 2006.225.07:50:11.32#ibcon#wrote, iclass 24, count 2 2006.225.07:50:11.32#ibcon#about to read 3, iclass 24, count 2 2006.225.07:50:11.34#ibcon#read 3, iclass 24, count 2 2006.225.07:50:11.34#ibcon#about to read 4, iclass 24, count 2 2006.225.07:50:11.34#ibcon#read 4, iclass 24, count 2 2006.225.07:50:11.34#ibcon#about to read 5, iclass 24, count 2 2006.225.07:50:11.34#ibcon#read 5, iclass 24, count 2 2006.225.07:50:11.34#ibcon#about to read 6, iclass 24, count 2 2006.225.07:50:11.34#ibcon#read 6, iclass 24, count 2 2006.225.07:50:11.34#ibcon#end of sib2, iclass 24, count 2 2006.225.07:50:11.34#ibcon#*mode == 0, iclass 24, count 2 2006.225.07:50:11.34#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.07:50:11.34#ibcon#[27=AT03-04\r\n] 2006.225.07:50:11.34#ibcon#*before write, iclass 24, count 2 2006.225.07:50:11.34#ibcon#enter sib2, iclass 24, count 2 2006.225.07:50:11.34#ibcon#flushed, iclass 24, count 2 2006.225.07:50:11.34#ibcon#about to write, iclass 24, count 2 2006.225.07:50:11.34#ibcon#wrote, iclass 24, count 2 2006.225.07:50:11.34#ibcon#about to read 3, iclass 24, count 2 2006.225.07:50:11.37#ibcon#read 3, iclass 24, count 2 2006.225.07:50:11.37#ibcon#about to read 4, iclass 24, count 2 2006.225.07:50:11.37#ibcon#read 4, iclass 24, count 2 2006.225.07:50:11.37#ibcon#about to read 5, iclass 24, count 2 2006.225.07:50:11.37#ibcon#read 5, iclass 24, count 2 2006.225.07:50:11.37#ibcon#about to read 6, iclass 24, count 2 2006.225.07:50:11.37#ibcon#read 6, iclass 24, count 2 2006.225.07:50:11.37#ibcon#end of sib2, iclass 24, count 2 2006.225.07:50:11.37#ibcon#*after write, iclass 24, count 2 2006.225.07:50:11.37#ibcon#*before return 0, iclass 24, count 2 2006.225.07:50:11.37#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:50:11.37#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:50:11.37#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.07:50:11.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:11.37#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:50:11.49#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:50:11.49#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:50:11.49#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:50:11.49#ibcon#first serial, iclass 24, count 0 2006.225.07:50:11.49#ibcon#enter sib2, iclass 24, count 0 2006.225.07:50:11.49#ibcon#flushed, iclass 24, count 0 2006.225.07:50:11.49#ibcon#about to write, iclass 24, count 0 2006.225.07:50:11.49#ibcon#wrote, iclass 24, count 0 2006.225.07:50:11.49#ibcon#about to read 3, iclass 24, count 0 2006.225.07:50:11.51#ibcon#read 3, iclass 24, count 0 2006.225.07:50:11.51#ibcon#about to read 4, iclass 24, count 0 2006.225.07:50:11.51#ibcon#read 4, iclass 24, count 0 2006.225.07:50:11.51#ibcon#about to read 5, iclass 24, count 0 2006.225.07:50:11.51#ibcon#read 5, iclass 24, count 0 2006.225.07:50:11.51#ibcon#about to read 6, iclass 24, count 0 2006.225.07:50:11.51#ibcon#read 6, iclass 24, count 0 2006.225.07:50:11.51#ibcon#end of sib2, iclass 24, count 0 2006.225.07:50:11.51#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:50:11.51#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:50:11.51#ibcon#[27=USB\r\n] 2006.225.07:50:11.51#ibcon#*before write, iclass 24, count 0 2006.225.07:50:11.51#ibcon#enter sib2, iclass 24, count 0 2006.225.07:50:11.51#ibcon#flushed, iclass 24, count 0 2006.225.07:50:11.51#ibcon#about to write, iclass 24, count 0 2006.225.07:50:11.51#ibcon#wrote, iclass 24, count 0 2006.225.07:50:11.51#ibcon#about to read 3, iclass 24, count 0 2006.225.07:50:11.54#ibcon#read 3, iclass 24, count 0 2006.225.07:50:11.54#ibcon#about to read 4, iclass 24, count 0 2006.225.07:50:11.54#ibcon#read 4, iclass 24, count 0 2006.225.07:50:11.54#ibcon#about to read 5, iclass 24, count 0 2006.225.07:50:11.54#ibcon#read 5, iclass 24, count 0 2006.225.07:50:11.54#ibcon#about to read 6, iclass 24, count 0 2006.225.07:50:11.54#ibcon#read 6, iclass 24, count 0 2006.225.07:50:11.54#ibcon#end of sib2, iclass 24, count 0 2006.225.07:50:11.54#ibcon#*after write, iclass 24, count 0 2006.225.07:50:11.54#ibcon#*before return 0, iclass 24, count 0 2006.225.07:50:11.54#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:50:11.54#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:50:11.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:50:11.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:50:11.54$vc4f8/vblo=4,712.99 2006.225.07:50:11.54#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.07:50:11.54#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.07:50:11.54#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:11.54#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:50:11.54#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:50:11.54#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:50:11.54#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:50:11.54#ibcon#first serial, iclass 26, count 0 2006.225.07:50:11.54#ibcon#enter sib2, iclass 26, count 0 2006.225.07:50:11.54#ibcon#flushed, iclass 26, count 0 2006.225.07:50:11.54#ibcon#about to write, iclass 26, count 0 2006.225.07:50:11.54#ibcon#wrote, iclass 26, count 0 2006.225.07:50:11.54#ibcon#about to read 3, iclass 26, count 0 2006.225.07:50:11.56#ibcon#read 3, iclass 26, count 0 2006.225.07:50:11.56#ibcon#about to read 4, iclass 26, count 0 2006.225.07:50:11.56#ibcon#read 4, iclass 26, count 0 2006.225.07:50:11.56#ibcon#about to read 5, iclass 26, count 0 2006.225.07:50:11.56#ibcon#read 5, iclass 26, count 0 2006.225.07:50:11.56#ibcon#about to read 6, iclass 26, count 0 2006.225.07:50:11.56#ibcon#read 6, iclass 26, count 0 2006.225.07:50:11.56#ibcon#end of sib2, iclass 26, count 0 2006.225.07:50:11.56#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:50:11.56#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:50:11.56#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:50:11.56#ibcon#*before write, iclass 26, count 0 2006.225.07:50:11.56#ibcon#enter sib2, iclass 26, count 0 2006.225.07:50:11.56#ibcon#flushed, iclass 26, count 0 2006.225.07:50:11.56#ibcon#about to write, iclass 26, count 0 2006.225.07:50:11.56#ibcon#wrote, iclass 26, count 0 2006.225.07:50:11.56#ibcon#about to read 3, iclass 26, count 0 2006.225.07:50:11.60#ibcon#read 3, iclass 26, count 0 2006.225.07:50:11.60#ibcon#about to read 4, iclass 26, count 0 2006.225.07:50:11.60#ibcon#read 4, iclass 26, count 0 2006.225.07:50:11.60#ibcon#about to read 5, iclass 26, count 0 2006.225.07:50:11.60#ibcon#read 5, iclass 26, count 0 2006.225.07:50:11.60#ibcon#about to read 6, iclass 26, count 0 2006.225.07:50:11.60#ibcon#read 6, iclass 26, count 0 2006.225.07:50:11.60#ibcon#end of sib2, iclass 26, count 0 2006.225.07:50:11.60#ibcon#*after write, iclass 26, count 0 2006.225.07:50:11.60#ibcon#*before return 0, iclass 26, count 0 2006.225.07:50:11.60#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:50:11.60#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:50:11.60#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:50:11.60#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:50:11.60$vc4f8/vb=4,4 2006.225.07:50:11.60#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.07:50:11.60#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.07:50:11.60#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:11.60#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:50:11.66#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:50:11.66#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:50:11.66#ibcon#enter wrdev, iclass 28, count 2 2006.225.07:50:11.66#ibcon#first serial, iclass 28, count 2 2006.225.07:50:11.66#ibcon#enter sib2, iclass 28, count 2 2006.225.07:50:11.66#ibcon#flushed, iclass 28, count 2 2006.225.07:50:11.66#ibcon#about to write, iclass 28, count 2 2006.225.07:50:11.66#ibcon#wrote, iclass 28, count 2 2006.225.07:50:11.66#ibcon#about to read 3, iclass 28, count 2 2006.225.07:50:11.68#ibcon#read 3, iclass 28, count 2 2006.225.07:50:11.68#ibcon#about to read 4, iclass 28, count 2 2006.225.07:50:11.68#ibcon#read 4, iclass 28, count 2 2006.225.07:50:11.68#ibcon#about to read 5, iclass 28, count 2 2006.225.07:50:11.68#ibcon#read 5, iclass 28, count 2 2006.225.07:50:11.68#ibcon#about to read 6, iclass 28, count 2 2006.225.07:50:11.68#ibcon#read 6, iclass 28, count 2 2006.225.07:50:11.68#ibcon#end of sib2, iclass 28, count 2 2006.225.07:50:11.68#ibcon#*mode == 0, iclass 28, count 2 2006.225.07:50:11.68#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.07:50:11.68#ibcon#[27=AT04-04\r\n] 2006.225.07:50:11.68#ibcon#*before write, iclass 28, count 2 2006.225.07:50:11.68#ibcon#enter sib2, iclass 28, count 2 2006.225.07:50:11.68#ibcon#flushed, iclass 28, count 2 2006.225.07:50:11.68#ibcon#about to write, iclass 28, count 2 2006.225.07:50:11.68#ibcon#wrote, iclass 28, count 2 2006.225.07:50:11.68#ibcon#about to read 3, iclass 28, count 2 2006.225.07:50:11.71#ibcon#read 3, iclass 28, count 2 2006.225.07:50:11.71#ibcon#about to read 4, iclass 28, count 2 2006.225.07:50:11.71#ibcon#read 4, iclass 28, count 2 2006.225.07:50:11.71#ibcon#about to read 5, iclass 28, count 2 2006.225.07:50:11.71#ibcon#read 5, iclass 28, count 2 2006.225.07:50:11.71#ibcon#about to read 6, iclass 28, count 2 2006.225.07:50:11.71#ibcon#read 6, iclass 28, count 2 2006.225.07:50:11.71#ibcon#end of sib2, iclass 28, count 2 2006.225.07:50:11.71#ibcon#*after write, iclass 28, count 2 2006.225.07:50:11.71#ibcon#*before return 0, iclass 28, count 2 2006.225.07:50:11.71#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:50:11.71#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:50:11.71#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.07:50:11.71#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:11.71#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:50:11.83#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:50:11.83#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:50:11.83#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:50:11.83#ibcon#first serial, iclass 28, count 0 2006.225.07:50:11.83#ibcon#enter sib2, iclass 28, count 0 2006.225.07:50:11.83#ibcon#flushed, iclass 28, count 0 2006.225.07:50:11.83#ibcon#about to write, iclass 28, count 0 2006.225.07:50:11.83#ibcon#wrote, iclass 28, count 0 2006.225.07:50:11.83#ibcon#about to read 3, iclass 28, count 0 2006.225.07:50:11.85#ibcon#read 3, iclass 28, count 0 2006.225.07:50:11.85#ibcon#about to read 4, iclass 28, count 0 2006.225.07:50:11.85#ibcon#read 4, iclass 28, count 0 2006.225.07:50:11.85#ibcon#about to read 5, iclass 28, count 0 2006.225.07:50:11.85#ibcon#read 5, iclass 28, count 0 2006.225.07:50:11.85#ibcon#about to read 6, iclass 28, count 0 2006.225.07:50:11.85#ibcon#read 6, iclass 28, count 0 2006.225.07:50:11.85#ibcon#end of sib2, iclass 28, count 0 2006.225.07:50:11.85#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:50:11.85#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:50:11.85#ibcon#[27=USB\r\n] 2006.225.07:50:11.85#ibcon#*before write, iclass 28, count 0 2006.225.07:50:11.85#ibcon#enter sib2, iclass 28, count 0 2006.225.07:50:11.85#ibcon#flushed, iclass 28, count 0 2006.225.07:50:11.85#ibcon#about to write, iclass 28, count 0 2006.225.07:50:11.85#ibcon#wrote, iclass 28, count 0 2006.225.07:50:11.85#ibcon#about to read 3, iclass 28, count 0 2006.225.07:50:11.88#ibcon#read 3, iclass 28, count 0 2006.225.07:50:11.88#ibcon#about to read 4, iclass 28, count 0 2006.225.07:50:11.88#ibcon#read 4, iclass 28, count 0 2006.225.07:50:11.88#ibcon#about to read 5, iclass 28, count 0 2006.225.07:50:11.88#ibcon#read 5, iclass 28, count 0 2006.225.07:50:11.88#ibcon#about to read 6, iclass 28, count 0 2006.225.07:50:11.88#ibcon#read 6, iclass 28, count 0 2006.225.07:50:11.88#ibcon#end of sib2, iclass 28, count 0 2006.225.07:50:11.88#ibcon#*after write, iclass 28, count 0 2006.225.07:50:11.88#ibcon#*before return 0, iclass 28, count 0 2006.225.07:50:11.88#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:50:11.88#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:50:11.88#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:50:11.88#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:50:11.88$vc4f8/vblo=5,744.99 2006.225.07:50:11.88#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.07:50:11.88#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.07:50:11.88#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:11.88#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:50:11.88#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:50:11.88#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:50:11.88#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:50:11.88#ibcon#first serial, iclass 30, count 0 2006.225.07:50:11.88#ibcon#enter sib2, iclass 30, count 0 2006.225.07:50:11.88#ibcon#flushed, iclass 30, count 0 2006.225.07:50:11.88#ibcon#about to write, iclass 30, count 0 2006.225.07:50:11.88#ibcon#wrote, iclass 30, count 0 2006.225.07:50:11.88#ibcon#about to read 3, iclass 30, count 0 2006.225.07:50:11.90#ibcon#read 3, iclass 30, count 0 2006.225.07:50:11.90#ibcon#about to read 4, iclass 30, count 0 2006.225.07:50:11.90#ibcon#read 4, iclass 30, count 0 2006.225.07:50:11.90#ibcon#about to read 5, iclass 30, count 0 2006.225.07:50:11.90#ibcon#read 5, iclass 30, count 0 2006.225.07:50:11.90#ibcon#about to read 6, iclass 30, count 0 2006.225.07:50:11.90#ibcon#read 6, iclass 30, count 0 2006.225.07:50:11.90#ibcon#end of sib2, iclass 30, count 0 2006.225.07:50:11.90#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:50:11.90#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:50:11.90#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:50:11.90#ibcon#*before write, iclass 30, count 0 2006.225.07:50:11.90#ibcon#enter sib2, iclass 30, count 0 2006.225.07:50:11.90#ibcon#flushed, iclass 30, count 0 2006.225.07:50:11.90#ibcon#about to write, iclass 30, count 0 2006.225.07:50:11.90#ibcon#wrote, iclass 30, count 0 2006.225.07:50:11.90#ibcon#about to read 3, iclass 30, count 0 2006.225.07:50:11.94#ibcon#read 3, iclass 30, count 0 2006.225.07:50:11.94#ibcon#about to read 4, iclass 30, count 0 2006.225.07:50:11.94#ibcon#read 4, iclass 30, count 0 2006.225.07:50:11.94#ibcon#about to read 5, iclass 30, count 0 2006.225.07:50:11.94#ibcon#read 5, iclass 30, count 0 2006.225.07:50:11.94#ibcon#about to read 6, iclass 30, count 0 2006.225.07:50:11.94#ibcon#read 6, iclass 30, count 0 2006.225.07:50:11.94#ibcon#end of sib2, iclass 30, count 0 2006.225.07:50:11.94#ibcon#*after write, iclass 30, count 0 2006.225.07:50:11.94#ibcon#*before return 0, iclass 30, count 0 2006.225.07:50:11.94#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:50:11.94#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:50:11.94#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:50:11.94#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:50:11.94$vc4f8/vb=5,4 2006.225.07:50:11.94#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.225.07:50:11.94#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.225.07:50:11.94#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:11.94#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:50:12.00#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:50:12.00#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:50:12.00#ibcon#enter wrdev, iclass 32, count 2 2006.225.07:50:12.00#ibcon#first serial, iclass 32, count 2 2006.225.07:50:12.00#ibcon#enter sib2, iclass 32, count 2 2006.225.07:50:12.00#ibcon#flushed, iclass 32, count 2 2006.225.07:50:12.00#ibcon#about to write, iclass 32, count 2 2006.225.07:50:12.00#ibcon#wrote, iclass 32, count 2 2006.225.07:50:12.00#ibcon#about to read 3, iclass 32, count 2 2006.225.07:50:12.02#ibcon#read 3, iclass 32, count 2 2006.225.07:50:12.02#ibcon#about to read 4, iclass 32, count 2 2006.225.07:50:12.02#ibcon#read 4, iclass 32, count 2 2006.225.07:50:12.02#ibcon#about to read 5, iclass 32, count 2 2006.225.07:50:12.02#ibcon#read 5, iclass 32, count 2 2006.225.07:50:12.02#ibcon#about to read 6, iclass 32, count 2 2006.225.07:50:12.02#ibcon#read 6, iclass 32, count 2 2006.225.07:50:12.02#ibcon#end of sib2, iclass 32, count 2 2006.225.07:50:12.02#ibcon#*mode == 0, iclass 32, count 2 2006.225.07:50:12.02#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.225.07:50:12.02#ibcon#[27=AT05-04\r\n] 2006.225.07:50:12.02#ibcon#*before write, iclass 32, count 2 2006.225.07:50:12.02#ibcon#enter sib2, iclass 32, count 2 2006.225.07:50:12.02#ibcon#flushed, iclass 32, count 2 2006.225.07:50:12.02#ibcon#about to write, iclass 32, count 2 2006.225.07:50:12.02#ibcon#wrote, iclass 32, count 2 2006.225.07:50:12.02#ibcon#about to read 3, iclass 32, count 2 2006.225.07:50:12.05#ibcon#read 3, iclass 32, count 2 2006.225.07:50:12.05#ibcon#about to read 4, iclass 32, count 2 2006.225.07:50:12.05#ibcon#read 4, iclass 32, count 2 2006.225.07:50:12.05#ibcon#about to read 5, iclass 32, count 2 2006.225.07:50:12.05#ibcon#read 5, iclass 32, count 2 2006.225.07:50:12.05#ibcon#about to read 6, iclass 32, count 2 2006.225.07:50:12.05#ibcon#read 6, iclass 32, count 2 2006.225.07:50:12.05#ibcon#end of sib2, iclass 32, count 2 2006.225.07:50:12.05#ibcon#*after write, iclass 32, count 2 2006.225.07:50:12.05#ibcon#*before return 0, iclass 32, count 2 2006.225.07:50:12.05#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:50:12.05#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:50:12.05#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.225.07:50:12.05#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:12.05#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:50:12.17#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:50:12.17#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:50:12.17#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:50:12.17#ibcon#first serial, iclass 32, count 0 2006.225.07:50:12.17#ibcon#enter sib2, iclass 32, count 0 2006.225.07:50:12.17#ibcon#flushed, iclass 32, count 0 2006.225.07:50:12.17#ibcon#about to write, iclass 32, count 0 2006.225.07:50:12.17#ibcon#wrote, iclass 32, count 0 2006.225.07:50:12.17#ibcon#about to read 3, iclass 32, count 0 2006.225.07:50:12.19#ibcon#read 3, iclass 32, count 0 2006.225.07:50:12.19#ibcon#about to read 4, iclass 32, count 0 2006.225.07:50:12.19#ibcon#read 4, iclass 32, count 0 2006.225.07:50:12.19#ibcon#about to read 5, iclass 32, count 0 2006.225.07:50:12.19#ibcon#read 5, iclass 32, count 0 2006.225.07:50:12.19#ibcon#about to read 6, iclass 32, count 0 2006.225.07:50:12.19#ibcon#read 6, iclass 32, count 0 2006.225.07:50:12.19#ibcon#end of sib2, iclass 32, count 0 2006.225.07:50:12.19#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:50:12.19#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:50:12.19#ibcon#[27=USB\r\n] 2006.225.07:50:12.19#ibcon#*before write, iclass 32, count 0 2006.225.07:50:12.19#ibcon#enter sib2, iclass 32, count 0 2006.225.07:50:12.19#ibcon#flushed, iclass 32, count 0 2006.225.07:50:12.19#ibcon#about to write, iclass 32, count 0 2006.225.07:50:12.19#ibcon#wrote, iclass 32, count 0 2006.225.07:50:12.19#ibcon#about to read 3, iclass 32, count 0 2006.225.07:50:12.22#ibcon#read 3, iclass 32, count 0 2006.225.07:50:12.22#ibcon#about to read 4, iclass 32, count 0 2006.225.07:50:12.22#ibcon#read 4, iclass 32, count 0 2006.225.07:50:12.22#ibcon#about to read 5, iclass 32, count 0 2006.225.07:50:12.22#ibcon#read 5, iclass 32, count 0 2006.225.07:50:12.22#ibcon#about to read 6, iclass 32, count 0 2006.225.07:50:12.22#ibcon#read 6, iclass 32, count 0 2006.225.07:50:12.22#ibcon#end of sib2, iclass 32, count 0 2006.225.07:50:12.22#ibcon#*after write, iclass 32, count 0 2006.225.07:50:12.22#ibcon#*before return 0, iclass 32, count 0 2006.225.07:50:12.22#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:50:12.22#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:50:12.22#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:50:12.22#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:50:12.22$vc4f8/vblo=6,752.99 2006.225.07:50:12.22#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.07:50:12.22#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.07:50:12.22#ibcon#ireg 17 cls_cnt 0 2006.225.07:50:12.22#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:50:12.22#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:50:12.22#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:50:12.22#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:50:12.22#ibcon#first serial, iclass 34, count 0 2006.225.07:50:12.22#ibcon#enter sib2, iclass 34, count 0 2006.225.07:50:12.22#ibcon#flushed, iclass 34, count 0 2006.225.07:50:12.22#ibcon#about to write, iclass 34, count 0 2006.225.07:50:12.22#ibcon#wrote, iclass 34, count 0 2006.225.07:50:12.22#ibcon#about to read 3, iclass 34, count 0 2006.225.07:50:12.24#ibcon#read 3, iclass 34, count 0 2006.225.07:50:12.24#ibcon#about to read 4, iclass 34, count 0 2006.225.07:50:12.24#ibcon#read 4, iclass 34, count 0 2006.225.07:50:12.24#ibcon#about to read 5, iclass 34, count 0 2006.225.07:50:12.24#ibcon#read 5, iclass 34, count 0 2006.225.07:50:12.24#ibcon#about to read 6, iclass 34, count 0 2006.225.07:50:12.24#ibcon#read 6, iclass 34, count 0 2006.225.07:50:12.24#ibcon#end of sib2, iclass 34, count 0 2006.225.07:50:12.24#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:50:12.24#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:50:12.24#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:50:12.24#ibcon#*before write, iclass 34, count 0 2006.225.07:50:12.24#ibcon#enter sib2, iclass 34, count 0 2006.225.07:50:12.24#ibcon#flushed, iclass 34, count 0 2006.225.07:50:12.24#ibcon#about to write, iclass 34, count 0 2006.225.07:50:12.24#ibcon#wrote, iclass 34, count 0 2006.225.07:50:12.24#ibcon#about to read 3, iclass 34, count 0 2006.225.07:50:12.28#ibcon#read 3, iclass 34, count 0 2006.225.07:50:12.28#ibcon#about to read 4, iclass 34, count 0 2006.225.07:50:12.28#ibcon#read 4, iclass 34, count 0 2006.225.07:50:12.28#ibcon#about to read 5, iclass 34, count 0 2006.225.07:50:12.28#ibcon#read 5, iclass 34, count 0 2006.225.07:50:12.28#ibcon#about to read 6, iclass 34, count 0 2006.225.07:50:12.28#ibcon#read 6, iclass 34, count 0 2006.225.07:50:12.28#ibcon#end of sib2, iclass 34, count 0 2006.225.07:50:12.28#ibcon#*after write, iclass 34, count 0 2006.225.07:50:12.28#ibcon#*before return 0, iclass 34, count 0 2006.225.07:50:12.28#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:50:12.28#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:50:12.28#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:50:12.28#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:50:12.28$vc4f8/vb=6,4 2006.225.07:50:12.28#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.07:50:12.28#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.07:50:12.28#ibcon#ireg 11 cls_cnt 2 2006.225.07:50:12.28#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:50:12.34#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:50:12.34#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:50:12.34#ibcon#enter wrdev, iclass 36, count 2 2006.225.07:50:12.34#ibcon#first serial, iclass 36, count 2 2006.225.07:50:12.34#ibcon#enter sib2, iclass 36, count 2 2006.225.07:50:12.34#ibcon#flushed, iclass 36, count 2 2006.225.07:50:12.34#ibcon#about to write, iclass 36, count 2 2006.225.07:50:12.34#ibcon#wrote, iclass 36, count 2 2006.225.07:50:12.34#ibcon#about to read 3, iclass 36, count 2 2006.225.07:50:12.36#ibcon#read 3, iclass 36, count 2 2006.225.07:50:12.36#ibcon#about to read 4, iclass 36, count 2 2006.225.07:50:12.36#ibcon#read 4, iclass 36, count 2 2006.225.07:50:12.36#ibcon#about to read 5, iclass 36, count 2 2006.225.07:50:12.36#ibcon#read 5, iclass 36, count 2 2006.225.07:50:12.36#ibcon#about to read 6, iclass 36, count 2 2006.225.07:50:12.36#ibcon#read 6, iclass 36, count 2 2006.225.07:50:12.36#ibcon#end of sib2, iclass 36, count 2 2006.225.07:50:12.36#ibcon#*mode == 0, iclass 36, count 2 2006.225.07:50:12.36#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.07:50:12.36#ibcon#[27=AT06-04\r\n] 2006.225.07:50:12.36#ibcon#*before write, iclass 36, count 2 2006.225.07:50:12.36#ibcon#enter sib2, iclass 36, count 2 2006.225.07:50:12.36#ibcon#flushed, iclass 36, count 2 2006.225.07:50:12.36#ibcon#about to write, iclass 36, count 2 2006.225.07:50:12.36#ibcon#wrote, iclass 36, count 2 2006.225.07:50:12.36#ibcon#about to read 3, iclass 36, count 2 2006.225.07:50:12.39#ibcon#read 3, iclass 36, count 2 2006.225.07:50:12.39#ibcon#about to read 4, iclass 36, count 2 2006.225.07:50:12.39#ibcon#read 4, iclass 36, count 2 2006.225.07:50:12.39#ibcon#about to read 5, iclass 36, count 2 2006.225.07:50:12.39#ibcon#read 5, iclass 36, count 2 2006.225.07:50:12.39#ibcon#about to read 6, iclass 36, count 2 2006.225.07:50:12.39#ibcon#read 6, iclass 36, count 2 2006.225.07:50:12.39#ibcon#end of sib2, iclass 36, count 2 2006.225.07:50:12.39#ibcon#*after write, iclass 36, count 2 2006.225.07:50:12.39#ibcon#*before return 0, iclass 36, count 2 2006.225.07:50:12.39#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:50:12.39#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:50:12.39#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.07:50:12.39#ibcon#ireg 7 cls_cnt 0 2006.225.07:50:12.39#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:50:12.51#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:50:12.51#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:50:12.51#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:50:12.51#ibcon#first serial, iclass 36, count 0 2006.225.07:50:12.51#ibcon#enter sib2, iclass 36, count 0 2006.225.07:50:12.51#ibcon#flushed, iclass 36, count 0 2006.225.07:50:12.51#ibcon#about to write, iclass 36, count 0 2006.225.07:50:12.51#ibcon#wrote, iclass 36, count 0 2006.225.07:50:12.51#ibcon#about to read 3, iclass 36, count 0 2006.225.07:50:12.53#ibcon#read 3, iclass 36, count 0 2006.225.07:50:12.53#ibcon#about to read 4, iclass 36, count 0 2006.225.07:50:12.53#ibcon#read 4, iclass 36, count 0 2006.225.07:50:12.53#ibcon#about to read 5, iclass 36, count 0 2006.225.07:50:12.53#ibcon#read 5, iclass 36, count 0 2006.225.07:50:12.53#ibcon#about to read 6, iclass 36, count 0 2006.225.07:50:12.53#ibcon#read 6, iclass 36, count 0 2006.225.07:50:12.53#ibcon#end of sib2, iclass 36, count 0 2006.225.07:50:12.53#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:50:12.53#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:50:12.53#ibcon#[27=USB\r\n] 2006.225.07:50:12.53#ibcon#*before write, iclass 36, count 0 2006.225.07:50:12.53#ibcon#enter sib2, iclass 36, count 0 2006.225.07:50:12.53#ibcon#flushed, iclass 36, count 0 2006.225.07:50:12.53#ibcon#about to write, iclass 36, count 0 2006.225.07:50:12.53#ibcon#wrote, iclass 36, count 0 2006.225.07:50:12.53#ibcon#about to read 3, iclass 36, count 0 2006.225.07:50:12.56#ibcon#read 3, iclass 36, count 0 2006.225.07:50:12.56#ibcon#about to read 4, iclass 36, count 0 2006.225.07:50:12.56#ibcon#read 4, iclass 36, count 0 2006.225.07:50:12.56#ibcon#about to read 5, iclass 36, count 0 2006.225.07:50:12.56#ibcon#read 5, iclass 36, count 0 2006.225.07:50:12.56#ibcon#about to read 6, iclass 36, count 0 2006.225.07:50:12.56#ibcon#read 6, iclass 36, count 0 2006.225.07:50:12.56#ibcon#end of sib2, iclass 36, count 0 2006.225.07:50:12.56#ibcon#*after write, iclass 36, count 0 2006.225.07:50:12.56#ibcon#*before return 0, iclass 36, count 0 2006.225.07:50:12.56#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:50:12.56#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:50:12.56#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:50:12.56#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:50:12.56$vc4f8/vabw=wide 2006.225.07:50:12.56#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.07:50:12.56#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.07:50:12.56#ibcon#ireg 8 cls_cnt 0 2006.225.07:50:12.56#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:50:12.56#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:50:12.56#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:50:12.56#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:50:12.56#ibcon#first serial, iclass 38, count 0 2006.225.07:50:12.56#ibcon#enter sib2, iclass 38, count 0 2006.225.07:50:12.56#ibcon#flushed, iclass 38, count 0 2006.225.07:50:12.56#ibcon#about to write, iclass 38, count 0 2006.225.07:50:12.56#ibcon#wrote, iclass 38, count 0 2006.225.07:50:12.56#ibcon#about to read 3, iclass 38, count 0 2006.225.07:50:12.58#ibcon#read 3, iclass 38, count 0 2006.225.07:50:12.58#ibcon#about to read 4, iclass 38, count 0 2006.225.07:50:12.58#ibcon#read 4, iclass 38, count 0 2006.225.07:50:12.58#ibcon#about to read 5, iclass 38, count 0 2006.225.07:50:12.58#ibcon#read 5, iclass 38, count 0 2006.225.07:50:12.58#ibcon#about to read 6, iclass 38, count 0 2006.225.07:50:12.58#ibcon#read 6, iclass 38, count 0 2006.225.07:50:12.58#ibcon#end of sib2, iclass 38, count 0 2006.225.07:50:12.58#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:50:12.58#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:50:12.58#ibcon#[25=BW32\r\n] 2006.225.07:50:12.58#ibcon#*before write, iclass 38, count 0 2006.225.07:50:12.58#ibcon#enter sib2, iclass 38, count 0 2006.225.07:50:12.58#ibcon#flushed, iclass 38, count 0 2006.225.07:50:12.58#ibcon#about to write, iclass 38, count 0 2006.225.07:50:12.58#ibcon#wrote, iclass 38, count 0 2006.225.07:50:12.58#ibcon#about to read 3, iclass 38, count 0 2006.225.07:50:12.61#ibcon#read 3, iclass 38, count 0 2006.225.07:50:12.61#ibcon#about to read 4, iclass 38, count 0 2006.225.07:50:12.61#ibcon#read 4, iclass 38, count 0 2006.225.07:50:12.61#ibcon#about to read 5, iclass 38, count 0 2006.225.07:50:12.61#ibcon#read 5, iclass 38, count 0 2006.225.07:50:12.61#ibcon#about to read 6, iclass 38, count 0 2006.225.07:50:12.61#ibcon#read 6, iclass 38, count 0 2006.225.07:50:12.61#ibcon#end of sib2, iclass 38, count 0 2006.225.07:50:12.61#ibcon#*after write, iclass 38, count 0 2006.225.07:50:12.61#ibcon#*before return 0, iclass 38, count 0 2006.225.07:50:12.61#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:50:12.61#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:50:12.61#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:50:12.61#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:50:12.61$vc4f8/vbbw=wide 2006.225.07:50:12.61#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.07:50:12.61#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.07:50:12.61#ibcon#ireg 8 cls_cnt 0 2006.225.07:50:12.61#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:50:12.68#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:50:12.68#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:50:12.68#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:50:12.68#ibcon#first serial, iclass 40, count 0 2006.225.07:50:12.68#ibcon#enter sib2, iclass 40, count 0 2006.225.07:50:12.68#ibcon#flushed, iclass 40, count 0 2006.225.07:50:12.68#ibcon#about to write, iclass 40, count 0 2006.225.07:50:12.68#ibcon#wrote, iclass 40, count 0 2006.225.07:50:12.68#ibcon#about to read 3, iclass 40, count 0 2006.225.07:50:12.70#ibcon#read 3, iclass 40, count 0 2006.225.07:50:12.70#ibcon#about to read 4, iclass 40, count 0 2006.225.07:50:12.70#ibcon#read 4, iclass 40, count 0 2006.225.07:50:12.70#ibcon#about to read 5, iclass 40, count 0 2006.225.07:50:12.70#ibcon#read 5, iclass 40, count 0 2006.225.07:50:12.70#ibcon#about to read 6, iclass 40, count 0 2006.225.07:50:12.70#ibcon#read 6, iclass 40, count 0 2006.225.07:50:12.70#ibcon#end of sib2, iclass 40, count 0 2006.225.07:50:12.70#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:50:12.70#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:50:12.70#ibcon#[27=BW32\r\n] 2006.225.07:50:12.70#ibcon#*before write, iclass 40, count 0 2006.225.07:50:12.70#ibcon#enter sib2, iclass 40, count 0 2006.225.07:50:12.70#ibcon#flushed, iclass 40, count 0 2006.225.07:50:12.70#ibcon#about to write, iclass 40, count 0 2006.225.07:50:12.70#ibcon#wrote, iclass 40, count 0 2006.225.07:50:12.70#ibcon#about to read 3, iclass 40, count 0 2006.225.07:50:12.73#ibcon#read 3, iclass 40, count 0 2006.225.07:50:12.73#ibcon#about to read 4, iclass 40, count 0 2006.225.07:50:12.73#ibcon#read 4, iclass 40, count 0 2006.225.07:50:12.73#ibcon#about to read 5, iclass 40, count 0 2006.225.07:50:12.73#ibcon#read 5, iclass 40, count 0 2006.225.07:50:12.73#ibcon#about to read 6, iclass 40, count 0 2006.225.07:50:12.73#ibcon#read 6, iclass 40, count 0 2006.225.07:50:12.73#ibcon#end of sib2, iclass 40, count 0 2006.225.07:50:12.73#ibcon#*after write, iclass 40, count 0 2006.225.07:50:12.73#ibcon#*before return 0, iclass 40, count 0 2006.225.07:50:12.73#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:50:12.73#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:50:12.73#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:50:12.73#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:50:12.73$4f8m12a/ifd4f 2006.225.07:50:12.73$ifd4f/lo= 2006.225.07:50:12.73$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:50:12.73$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:50:12.73$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:50:12.73$ifd4f/patch= 2006.225.07:50:12.73$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:50:12.73$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:50:12.73$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:50:12.73$4f8m12a/"form=m,16.000,1:2 2006.225.07:50:12.73$4f8m12a/"tpicd 2006.225.07:50:12.73$4f8m12a/echo=off 2006.225.07:50:12.73$4f8m12a/xlog=off 2006.225.07:50:12.73:!2006.225.07:50:40 2006.225.07:50:21.14#trakl#Source acquired 2006.225.07:50:22.14#flagr#flagr/antenna,acquired 2006.225.07:50:40.00:preob 2006.225.07:50:41.14/onsource/TRACKING 2006.225.07:50:41.14:!2006.225.07:50:50 2006.225.07:50:50.00:data_valid=on 2006.225.07:50:50.00:midob 2006.225.07:50:50.13/onsource/TRACKING 2006.225.07:50:50.13/wx/28.26,1003.4,72 2006.225.07:50:50.18/cable/+6.4032E-03 2006.225.07:50:51.27/va/01,08,usb,yes,38,39 2006.225.07:50:51.27/va/02,07,usb,yes,38,39 2006.225.07:50:51.27/va/03,06,usb,yes,40,40 2006.225.07:50:51.27/va/04,07,usb,yes,40,43 2006.225.07:50:51.27/va/05,07,usb,yes,44,46 2006.225.07:50:51.27/va/06,06,usb,yes,43,43 2006.225.07:50:51.27/va/07,06,usb,yes,43,43 2006.225.07:50:51.27/va/08,07,usb,yes,41,40 2006.225.07:50:51.50/valo/01,532.99,yes,locked 2006.225.07:50:51.50/valo/02,572.99,yes,locked 2006.225.07:50:51.50/valo/03,672.99,yes,locked 2006.225.07:50:51.50/valo/04,832.99,yes,locked 2006.225.07:50:51.50/valo/05,652.99,yes,locked 2006.225.07:50:51.50/valo/06,772.99,yes,locked 2006.225.07:50:51.50/valo/07,832.99,yes,locked 2006.225.07:50:51.50/valo/08,852.99,yes,locked 2006.225.07:50:52.59/vb/01,04,usb,yes,35,34 2006.225.07:50:52.59/vb/02,04,usb,yes,37,39 2006.225.07:50:52.59/vb/03,04,usb,yes,33,38 2006.225.07:50:52.59/vb/04,04,usb,yes,35,35 2006.225.07:50:52.59/vb/05,04,usb,yes,33,37 2006.225.07:50:52.59/vb/06,04,usb,yes,34,37 2006.225.07:50:52.59/vb/07,04,usb,yes,37,36 2006.225.07:50:52.59/vb/08,04,usb,yes,34,37 2006.225.07:50:52.83/vblo/01,632.99,yes,locked 2006.225.07:50:52.83/vblo/02,640.99,yes,locked 2006.225.07:50:52.83/vblo/03,656.99,yes,locked 2006.225.07:50:52.83/vblo/04,712.99,yes,locked 2006.225.07:50:52.83/vblo/05,744.99,yes,locked 2006.225.07:50:52.83/vblo/06,752.99,yes,locked 2006.225.07:50:52.83/vblo/07,734.99,yes,locked 2006.225.07:50:52.83/vblo/08,744.99,yes,locked 2006.225.07:50:52.98/vabw/8 2006.225.07:50:53.13/vbbw/8 2006.225.07:50:53.22/xfe/off,on,15.5 2006.225.07:50:53.62/ifatt/23,28,28,28 2006.225.07:50:54.08/fmout-gps/S +4.53E-07 2006.225.07:50:54.12:!2006.225.07:51:50 2006.225.07:51:50.00:data_valid=off 2006.225.07:51:50.00:postob 2006.225.07:51:50.13/cable/+6.4050E-03 2006.225.07:51:50.13/wx/28.30,1003.3,71 2006.225.07:51:51.08/fmout-gps/S +4.53E-07 2006.225.07:51:51.08:scan_name=225-0752,k06225,60 2006.225.07:51:51.08:source=0955+476,095819.67,472507.8,2000.0,ccw 2006.225.07:51:51.13#flagr#flagr/antenna,new-source 2006.225.07:51:52.13:checkk5 2006.225.07:51:52.49/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:51:52.86/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:51:53.24/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:51:53.62/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:51:53.99/chk_obsdata//k5ts1/T2250750??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.07:51:54.36/chk_obsdata//k5ts2/T2250750??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.07:51:54.72/chk_obsdata//k5ts3/T2250750??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.07:51:55.08/chk_obsdata//k5ts4/T2250750??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.07:51:55.77/k5log//k5ts1_log_newline 2006.225.07:51:56.46/k5log//k5ts2_log_newline 2006.225.07:51:57.14/k5log//k5ts3_log_newline 2006.225.07:51:57.82/k5log//k5ts4_log_newline 2006.225.07:51:57.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:51:57.85:4f8m12a=1 2006.225.07:51:57.85$4f8m12a/echo=on 2006.225.07:51:57.85$4f8m12a/pcalon 2006.225.07:51:57.85$pcalon/"no phase cal control is implemented here 2006.225.07:51:57.85$4f8m12a/"tpicd=stop 2006.225.07:51:57.85$4f8m12a/vc4f8 2006.225.07:51:57.85$vc4f8/valo=1,532.99 2006.225.07:51:57.85#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.07:51:57.85#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.07:51:57.85#ibcon#ireg 17 cls_cnt 0 2006.225.07:51:57.85#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:51:57.85#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:51:57.85#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:51:57.85#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:51:57.85#ibcon#first serial, iclass 10, count 0 2006.225.07:51:57.85#ibcon#enter sib2, iclass 10, count 0 2006.225.07:51:57.85#ibcon#flushed, iclass 10, count 0 2006.225.07:51:57.85#ibcon#about to write, iclass 10, count 0 2006.225.07:51:57.85#ibcon#wrote, iclass 10, count 0 2006.225.07:51:57.85#ibcon#about to read 3, iclass 10, count 0 2006.225.07:51:57.89#ibcon#read 3, iclass 10, count 0 2006.225.07:51:57.89#ibcon#about to read 4, iclass 10, count 0 2006.225.07:51:57.89#ibcon#read 4, iclass 10, count 0 2006.225.07:51:57.89#ibcon#about to read 5, iclass 10, count 0 2006.225.07:51:57.89#ibcon#read 5, iclass 10, count 0 2006.225.07:51:57.89#ibcon#about to read 6, iclass 10, count 0 2006.225.07:51:57.89#ibcon#read 6, iclass 10, count 0 2006.225.07:51:57.89#ibcon#end of sib2, iclass 10, count 0 2006.225.07:51:57.89#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:51:57.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:51:57.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:51:57.89#ibcon#*before write, iclass 10, count 0 2006.225.07:51:57.89#ibcon#enter sib2, iclass 10, count 0 2006.225.07:51:57.89#ibcon#flushed, iclass 10, count 0 2006.225.07:51:57.89#ibcon#about to write, iclass 10, count 0 2006.225.07:51:57.89#ibcon#wrote, iclass 10, count 0 2006.225.07:51:57.89#ibcon#about to read 3, iclass 10, count 0 2006.225.07:51:57.94#ibcon#read 3, iclass 10, count 0 2006.225.07:51:57.94#ibcon#about to read 4, iclass 10, count 0 2006.225.07:51:57.94#ibcon#read 4, iclass 10, count 0 2006.225.07:51:57.94#ibcon#about to read 5, iclass 10, count 0 2006.225.07:51:57.94#ibcon#read 5, iclass 10, count 0 2006.225.07:51:57.94#ibcon#about to read 6, iclass 10, count 0 2006.225.07:51:57.94#ibcon#read 6, iclass 10, count 0 2006.225.07:51:57.94#ibcon#end of sib2, iclass 10, count 0 2006.225.07:51:57.94#ibcon#*after write, iclass 10, count 0 2006.225.07:51:57.94#ibcon#*before return 0, iclass 10, count 0 2006.225.07:51:57.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:51:57.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:51:57.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:51:57.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:51:57.94$vc4f8/va=1,8 2006.225.07:51:57.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.07:51:57.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.07:51:57.94#ibcon#ireg 11 cls_cnt 2 2006.225.07:51:57.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:51:57.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:51:57.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:51:57.94#ibcon#enter wrdev, iclass 12, count 2 2006.225.07:51:57.94#ibcon#first serial, iclass 12, count 2 2006.225.07:51:57.94#ibcon#enter sib2, iclass 12, count 2 2006.225.07:51:57.94#ibcon#flushed, iclass 12, count 2 2006.225.07:51:57.94#ibcon#about to write, iclass 12, count 2 2006.225.07:51:57.94#ibcon#wrote, iclass 12, count 2 2006.225.07:51:57.94#ibcon#about to read 3, iclass 12, count 2 2006.225.07:51:57.96#ibcon#read 3, iclass 12, count 2 2006.225.07:51:57.96#ibcon#about to read 4, iclass 12, count 2 2006.225.07:51:57.96#ibcon#read 4, iclass 12, count 2 2006.225.07:51:57.96#ibcon#about to read 5, iclass 12, count 2 2006.225.07:51:57.96#ibcon#read 5, iclass 12, count 2 2006.225.07:51:57.96#ibcon#about to read 6, iclass 12, count 2 2006.225.07:51:57.96#ibcon#read 6, iclass 12, count 2 2006.225.07:51:57.96#ibcon#end of sib2, iclass 12, count 2 2006.225.07:51:57.96#ibcon#*mode == 0, iclass 12, count 2 2006.225.07:51:57.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.07:51:57.96#ibcon#[25=AT01-08\r\n] 2006.225.07:51:57.96#ibcon#*before write, iclass 12, count 2 2006.225.07:51:57.96#ibcon#enter sib2, iclass 12, count 2 2006.225.07:51:57.96#ibcon#flushed, iclass 12, count 2 2006.225.07:51:57.96#ibcon#about to write, iclass 12, count 2 2006.225.07:51:57.96#ibcon#wrote, iclass 12, count 2 2006.225.07:51:57.96#ibcon#about to read 3, iclass 12, count 2 2006.225.07:51:57.99#ibcon#read 3, iclass 12, count 2 2006.225.07:51:57.99#ibcon#about to read 4, iclass 12, count 2 2006.225.07:51:57.99#ibcon#read 4, iclass 12, count 2 2006.225.07:51:57.99#ibcon#about to read 5, iclass 12, count 2 2006.225.07:51:57.99#ibcon#read 5, iclass 12, count 2 2006.225.07:51:57.99#ibcon#about to read 6, iclass 12, count 2 2006.225.07:51:57.99#ibcon#read 6, iclass 12, count 2 2006.225.07:51:57.99#ibcon#end of sib2, iclass 12, count 2 2006.225.07:51:57.99#ibcon#*after write, iclass 12, count 2 2006.225.07:51:57.99#ibcon#*before return 0, iclass 12, count 2 2006.225.07:51:57.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:51:57.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:51:57.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.07:51:57.99#ibcon#ireg 7 cls_cnt 0 2006.225.07:51:57.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:51:58.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:51:58.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:51:58.11#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:51:58.11#ibcon#first serial, iclass 12, count 0 2006.225.07:51:58.11#ibcon#enter sib2, iclass 12, count 0 2006.225.07:51:58.11#ibcon#flushed, iclass 12, count 0 2006.225.07:51:58.11#ibcon#about to write, iclass 12, count 0 2006.225.07:51:58.11#ibcon#wrote, iclass 12, count 0 2006.225.07:51:58.11#ibcon#about to read 3, iclass 12, count 0 2006.225.07:51:58.13#ibcon#read 3, iclass 12, count 0 2006.225.07:51:58.13#ibcon#about to read 4, iclass 12, count 0 2006.225.07:51:58.13#ibcon#read 4, iclass 12, count 0 2006.225.07:51:58.13#ibcon#about to read 5, iclass 12, count 0 2006.225.07:51:58.13#ibcon#read 5, iclass 12, count 0 2006.225.07:51:58.13#ibcon#about to read 6, iclass 12, count 0 2006.225.07:51:58.13#ibcon#read 6, iclass 12, count 0 2006.225.07:51:58.13#ibcon#end of sib2, iclass 12, count 0 2006.225.07:51:58.13#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:51:58.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:51:58.13#ibcon#[25=USB\r\n] 2006.225.07:51:58.13#ibcon#*before write, iclass 12, count 0 2006.225.07:51:58.13#ibcon#enter sib2, iclass 12, count 0 2006.225.07:51:58.13#ibcon#flushed, iclass 12, count 0 2006.225.07:51:58.13#ibcon#about to write, iclass 12, count 0 2006.225.07:51:58.13#ibcon#wrote, iclass 12, count 0 2006.225.07:51:58.13#ibcon#about to read 3, iclass 12, count 0 2006.225.07:51:58.16#ibcon#read 3, iclass 12, count 0 2006.225.07:51:58.16#ibcon#about to read 4, iclass 12, count 0 2006.225.07:51:58.16#ibcon#read 4, iclass 12, count 0 2006.225.07:51:58.16#ibcon#about to read 5, iclass 12, count 0 2006.225.07:51:58.16#ibcon#read 5, iclass 12, count 0 2006.225.07:51:58.16#ibcon#about to read 6, iclass 12, count 0 2006.225.07:51:58.16#ibcon#read 6, iclass 12, count 0 2006.225.07:51:58.16#ibcon#end of sib2, iclass 12, count 0 2006.225.07:51:58.16#ibcon#*after write, iclass 12, count 0 2006.225.07:51:58.16#ibcon#*before return 0, iclass 12, count 0 2006.225.07:51:58.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:51:58.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:51:58.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:51:58.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:51:58.16$vc4f8/valo=2,572.99 2006.225.07:51:58.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.07:51:58.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.07:51:58.16#ibcon#ireg 17 cls_cnt 0 2006.225.07:51:58.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:51:58.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:51:58.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:51:58.16#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:51:58.16#ibcon#first serial, iclass 14, count 0 2006.225.07:51:58.16#ibcon#enter sib2, iclass 14, count 0 2006.225.07:51:58.16#ibcon#flushed, iclass 14, count 0 2006.225.07:51:58.16#ibcon#about to write, iclass 14, count 0 2006.225.07:51:58.16#ibcon#wrote, iclass 14, count 0 2006.225.07:51:58.16#ibcon#about to read 3, iclass 14, count 0 2006.225.07:51:58.18#ibcon#read 3, iclass 14, count 0 2006.225.07:51:58.18#ibcon#about to read 4, iclass 14, count 0 2006.225.07:51:58.18#ibcon#read 4, iclass 14, count 0 2006.225.07:51:58.18#ibcon#about to read 5, iclass 14, count 0 2006.225.07:51:58.19#ibcon#read 5, iclass 14, count 0 2006.225.07:51:58.19#ibcon#about to read 6, iclass 14, count 0 2006.225.07:51:58.19#ibcon#read 6, iclass 14, count 0 2006.225.07:51:58.19#ibcon#end of sib2, iclass 14, count 0 2006.225.07:51:58.19#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:51:58.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:51:58.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:51:58.19#ibcon#*before write, iclass 14, count 0 2006.225.07:51:58.19#ibcon#enter sib2, iclass 14, count 0 2006.225.07:51:58.19#ibcon#flushed, iclass 14, count 0 2006.225.07:51:58.19#ibcon#about to write, iclass 14, count 0 2006.225.07:51:58.19#ibcon#wrote, iclass 14, count 0 2006.225.07:51:58.19#ibcon#about to read 3, iclass 14, count 0 2006.225.07:51:58.23#ibcon#read 3, iclass 14, count 0 2006.225.07:51:58.23#ibcon#about to read 4, iclass 14, count 0 2006.225.07:51:58.23#ibcon#read 4, iclass 14, count 0 2006.225.07:51:58.23#ibcon#about to read 5, iclass 14, count 0 2006.225.07:51:58.23#ibcon#read 5, iclass 14, count 0 2006.225.07:51:58.23#ibcon#about to read 6, iclass 14, count 0 2006.225.07:51:58.23#ibcon#read 6, iclass 14, count 0 2006.225.07:51:58.23#ibcon#end of sib2, iclass 14, count 0 2006.225.07:51:58.23#ibcon#*after write, iclass 14, count 0 2006.225.07:51:58.23#ibcon#*before return 0, iclass 14, count 0 2006.225.07:51:58.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:51:58.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:51:58.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:51:58.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:51:58.23$vc4f8/va=2,7 2006.225.07:51:58.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.07:51:58.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.07:51:58.23#ibcon#ireg 11 cls_cnt 2 2006.225.07:51:58.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:51:58.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:51:58.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:51:58.28#ibcon#enter wrdev, iclass 16, count 2 2006.225.07:51:58.28#ibcon#first serial, iclass 16, count 2 2006.225.07:51:58.28#ibcon#enter sib2, iclass 16, count 2 2006.225.07:51:58.28#ibcon#flushed, iclass 16, count 2 2006.225.07:51:58.28#ibcon#about to write, iclass 16, count 2 2006.225.07:51:58.28#ibcon#wrote, iclass 16, count 2 2006.225.07:51:58.28#ibcon#about to read 3, iclass 16, count 2 2006.225.07:51:58.30#ibcon#read 3, iclass 16, count 2 2006.225.07:51:58.30#ibcon#about to read 4, iclass 16, count 2 2006.225.07:51:58.30#ibcon#read 4, iclass 16, count 2 2006.225.07:51:58.30#ibcon#about to read 5, iclass 16, count 2 2006.225.07:51:58.30#ibcon#read 5, iclass 16, count 2 2006.225.07:51:58.30#ibcon#about to read 6, iclass 16, count 2 2006.225.07:51:58.30#ibcon#read 6, iclass 16, count 2 2006.225.07:51:58.30#ibcon#end of sib2, iclass 16, count 2 2006.225.07:51:58.30#ibcon#*mode == 0, iclass 16, count 2 2006.225.07:51:58.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.07:51:58.30#ibcon#[25=AT02-07\r\n] 2006.225.07:51:58.30#ibcon#*before write, iclass 16, count 2 2006.225.07:51:58.30#ibcon#enter sib2, iclass 16, count 2 2006.225.07:51:58.30#ibcon#flushed, iclass 16, count 2 2006.225.07:51:58.30#ibcon#about to write, iclass 16, count 2 2006.225.07:51:58.30#ibcon#wrote, iclass 16, count 2 2006.225.07:51:58.30#ibcon#about to read 3, iclass 16, count 2 2006.225.07:51:58.33#ibcon#read 3, iclass 16, count 2 2006.225.07:51:58.33#ibcon#about to read 4, iclass 16, count 2 2006.225.07:51:58.33#ibcon#read 4, iclass 16, count 2 2006.225.07:51:58.33#ibcon#about to read 5, iclass 16, count 2 2006.225.07:51:58.33#ibcon#read 5, iclass 16, count 2 2006.225.07:51:58.33#ibcon#about to read 6, iclass 16, count 2 2006.225.07:51:58.33#ibcon#read 6, iclass 16, count 2 2006.225.07:51:58.33#ibcon#end of sib2, iclass 16, count 2 2006.225.07:51:58.33#ibcon#*after write, iclass 16, count 2 2006.225.07:51:58.33#ibcon#*before return 0, iclass 16, count 2 2006.225.07:51:58.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:51:58.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:51:58.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.07:51:58.33#ibcon#ireg 7 cls_cnt 0 2006.225.07:51:58.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:51:58.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:51:58.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:51:58.45#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:51:58.45#ibcon#first serial, iclass 16, count 0 2006.225.07:51:58.45#ibcon#enter sib2, iclass 16, count 0 2006.225.07:51:58.45#ibcon#flushed, iclass 16, count 0 2006.225.07:51:58.45#ibcon#about to write, iclass 16, count 0 2006.225.07:51:58.45#ibcon#wrote, iclass 16, count 0 2006.225.07:51:58.45#ibcon#about to read 3, iclass 16, count 0 2006.225.07:51:58.47#ibcon#read 3, iclass 16, count 0 2006.225.07:51:58.47#ibcon#about to read 4, iclass 16, count 0 2006.225.07:51:58.47#ibcon#read 4, iclass 16, count 0 2006.225.07:51:58.47#ibcon#about to read 5, iclass 16, count 0 2006.225.07:51:58.47#ibcon#read 5, iclass 16, count 0 2006.225.07:51:58.47#ibcon#about to read 6, iclass 16, count 0 2006.225.07:51:58.47#ibcon#read 6, iclass 16, count 0 2006.225.07:51:58.47#ibcon#end of sib2, iclass 16, count 0 2006.225.07:51:58.47#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:51:58.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:51:58.47#ibcon#[25=USB\r\n] 2006.225.07:51:58.47#ibcon#*before write, iclass 16, count 0 2006.225.07:51:58.47#ibcon#enter sib2, iclass 16, count 0 2006.225.07:51:58.47#ibcon#flushed, iclass 16, count 0 2006.225.07:51:58.47#ibcon#about to write, iclass 16, count 0 2006.225.07:51:58.47#ibcon#wrote, iclass 16, count 0 2006.225.07:51:58.47#ibcon#about to read 3, iclass 16, count 0 2006.225.07:51:58.50#ibcon#read 3, iclass 16, count 0 2006.225.07:51:58.50#ibcon#about to read 4, iclass 16, count 0 2006.225.07:51:58.50#ibcon#read 4, iclass 16, count 0 2006.225.07:51:58.50#ibcon#about to read 5, iclass 16, count 0 2006.225.07:51:58.50#ibcon#read 5, iclass 16, count 0 2006.225.07:51:58.50#ibcon#about to read 6, iclass 16, count 0 2006.225.07:51:58.50#ibcon#read 6, iclass 16, count 0 2006.225.07:51:58.50#ibcon#end of sib2, iclass 16, count 0 2006.225.07:51:58.50#ibcon#*after write, iclass 16, count 0 2006.225.07:51:58.50#ibcon#*before return 0, iclass 16, count 0 2006.225.07:51:58.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:51:58.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:51:58.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:51:58.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:51:58.50$vc4f8/valo=3,672.99 2006.225.07:51:58.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.07:51:58.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.07:51:58.50#ibcon#ireg 17 cls_cnt 0 2006.225.07:51:58.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:51:58.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:51:58.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:51:58.50#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:51:58.50#ibcon#first serial, iclass 18, count 0 2006.225.07:51:58.50#ibcon#enter sib2, iclass 18, count 0 2006.225.07:51:58.50#ibcon#flushed, iclass 18, count 0 2006.225.07:51:58.50#ibcon#about to write, iclass 18, count 0 2006.225.07:51:58.50#ibcon#wrote, iclass 18, count 0 2006.225.07:51:58.50#ibcon#about to read 3, iclass 18, count 0 2006.225.07:51:58.52#ibcon#read 3, iclass 18, count 0 2006.225.07:51:58.53#ibcon#about to read 4, iclass 18, count 0 2006.225.07:51:58.53#ibcon#read 4, iclass 18, count 0 2006.225.07:51:58.53#ibcon#about to read 5, iclass 18, count 0 2006.225.07:51:58.53#ibcon#read 5, iclass 18, count 0 2006.225.07:51:58.53#ibcon#about to read 6, iclass 18, count 0 2006.225.07:51:58.53#ibcon#read 6, iclass 18, count 0 2006.225.07:51:58.53#ibcon#end of sib2, iclass 18, count 0 2006.225.07:51:58.53#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:51:58.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:51:58.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:51:58.53#ibcon#*before write, iclass 18, count 0 2006.225.07:51:58.53#ibcon#enter sib2, iclass 18, count 0 2006.225.07:51:58.53#ibcon#flushed, iclass 18, count 0 2006.225.07:51:58.53#ibcon#about to write, iclass 18, count 0 2006.225.07:51:58.53#ibcon#wrote, iclass 18, count 0 2006.225.07:51:58.53#ibcon#about to read 3, iclass 18, count 0 2006.225.07:51:58.57#ibcon#read 3, iclass 18, count 0 2006.225.07:51:58.57#ibcon#about to read 4, iclass 18, count 0 2006.225.07:51:58.57#ibcon#read 4, iclass 18, count 0 2006.225.07:51:58.57#ibcon#about to read 5, iclass 18, count 0 2006.225.07:51:58.57#ibcon#read 5, iclass 18, count 0 2006.225.07:51:58.57#ibcon#about to read 6, iclass 18, count 0 2006.225.07:51:58.57#ibcon#read 6, iclass 18, count 0 2006.225.07:51:58.57#ibcon#end of sib2, iclass 18, count 0 2006.225.07:51:58.57#ibcon#*after write, iclass 18, count 0 2006.225.07:51:58.57#ibcon#*before return 0, iclass 18, count 0 2006.225.07:51:58.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:51:58.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:51:58.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:51:58.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:51:58.57$vc4f8/va=3,6 2006.225.07:51:58.57#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.07:51:58.57#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.07:51:58.57#ibcon#ireg 11 cls_cnt 2 2006.225.07:51:58.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:51:58.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:51:58.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:51:58.62#ibcon#enter wrdev, iclass 20, count 2 2006.225.07:51:58.62#ibcon#first serial, iclass 20, count 2 2006.225.07:51:58.62#ibcon#enter sib2, iclass 20, count 2 2006.225.07:51:58.62#ibcon#flushed, iclass 20, count 2 2006.225.07:51:58.62#ibcon#about to write, iclass 20, count 2 2006.225.07:51:58.62#ibcon#wrote, iclass 20, count 2 2006.225.07:51:58.62#ibcon#about to read 3, iclass 20, count 2 2006.225.07:51:58.64#ibcon#read 3, iclass 20, count 2 2006.225.07:51:58.64#ibcon#about to read 4, iclass 20, count 2 2006.225.07:51:58.64#ibcon#read 4, iclass 20, count 2 2006.225.07:51:58.64#ibcon#about to read 5, iclass 20, count 2 2006.225.07:51:58.64#ibcon#read 5, iclass 20, count 2 2006.225.07:51:58.64#ibcon#about to read 6, iclass 20, count 2 2006.225.07:51:58.64#ibcon#read 6, iclass 20, count 2 2006.225.07:51:58.64#ibcon#end of sib2, iclass 20, count 2 2006.225.07:51:58.64#ibcon#*mode == 0, iclass 20, count 2 2006.225.07:51:58.64#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.07:51:58.64#ibcon#[25=AT03-06\r\n] 2006.225.07:51:58.64#ibcon#*before write, iclass 20, count 2 2006.225.07:51:58.64#ibcon#enter sib2, iclass 20, count 2 2006.225.07:51:58.64#ibcon#flushed, iclass 20, count 2 2006.225.07:51:58.64#ibcon#about to write, iclass 20, count 2 2006.225.07:51:58.64#ibcon#wrote, iclass 20, count 2 2006.225.07:51:58.64#ibcon#about to read 3, iclass 20, count 2 2006.225.07:51:58.67#ibcon#read 3, iclass 20, count 2 2006.225.07:51:58.67#ibcon#about to read 4, iclass 20, count 2 2006.225.07:51:58.67#ibcon#read 4, iclass 20, count 2 2006.225.07:51:58.67#ibcon#about to read 5, iclass 20, count 2 2006.225.07:51:58.67#ibcon#read 5, iclass 20, count 2 2006.225.07:51:58.67#ibcon#about to read 6, iclass 20, count 2 2006.225.07:51:58.67#ibcon#read 6, iclass 20, count 2 2006.225.07:51:58.67#ibcon#end of sib2, iclass 20, count 2 2006.225.07:51:58.67#ibcon#*after write, iclass 20, count 2 2006.225.07:51:58.67#ibcon#*before return 0, iclass 20, count 2 2006.225.07:51:58.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:51:58.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:51:58.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.07:51:58.67#ibcon#ireg 7 cls_cnt 0 2006.225.07:51:58.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:51:58.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:51:58.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:51:58.79#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:51:58.79#ibcon#first serial, iclass 20, count 0 2006.225.07:51:58.79#ibcon#enter sib2, iclass 20, count 0 2006.225.07:51:58.79#ibcon#flushed, iclass 20, count 0 2006.225.07:51:58.79#ibcon#about to write, iclass 20, count 0 2006.225.07:51:58.79#ibcon#wrote, iclass 20, count 0 2006.225.07:51:58.79#ibcon#about to read 3, iclass 20, count 0 2006.225.07:51:58.81#ibcon#read 3, iclass 20, count 0 2006.225.07:51:58.81#ibcon#about to read 4, iclass 20, count 0 2006.225.07:51:58.81#ibcon#read 4, iclass 20, count 0 2006.225.07:51:58.81#ibcon#about to read 5, iclass 20, count 0 2006.225.07:51:58.81#ibcon#read 5, iclass 20, count 0 2006.225.07:51:58.81#ibcon#about to read 6, iclass 20, count 0 2006.225.07:51:58.81#ibcon#read 6, iclass 20, count 0 2006.225.07:51:58.81#ibcon#end of sib2, iclass 20, count 0 2006.225.07:51:58.81#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:51:58.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:51:58.81#ibcon#[25=USB\r\n] 2006.225.07:51:58.81#ibcon#*before write, iclass 20, count 0 2006.225.07:51:58.81#ibcon#enter sib2, iclass 20, count 0 2006.225.07:51:58.81#ibcon#flushed, iclass 20, count 0 2006.225.07:51:58.81#ibcon#about to write, iclass 20, count 0 2006.225.07:51:58.81#ibcon#wrote, iclass 20, count 0 2006.225.07:51:58.81#ibcon#about to read 3, iclass 20, count 0 2006.225.07:51:58.84#ibcon#read 3, iclass 20, count 0 2006.225.07:51:58.84#ibcon#about to read 4, iclass 20, count 0 2006.225.07:51:58.84#ibcon#read 4, iclass 20, count 0 2006.225.07:51:58.84#ibcon#about to read 5, iclass 20, count 0 2006.225.07:51:58.84#ibcon#read 5, iclass 20, count 0 2006.225.07:51:58.84#ibcon#about to read 6, iclass 20, count 0 2006.225.07:51:58.84#ibcon#read 6, iclass 20, count 0 2006.225.07:51:58.84#ibcon#end of sib2, iclass 20, count 0 2006.225.07:51:58.84#ibcon#*after write, iclass 20, count 0 2006.225.07:51:58.84#ibcon#*before return 0, iclass 20, count 0 2006.225.07:51:58.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:51:58.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:51:58.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:51:58.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:51:58.84$vc4f8/valo=4,832.99 2006.225.07:51:58.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.07:51:58.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.07:51:58.84#ibcon#ireg 17 cls_cnt 0 2006.225.07:51:58.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:51:58.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:51:58.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:51:58.84#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:51:58.84#ibcon#first serial, iclass 22, count 0 2006.225.07:51:58.84#ibcon#enter sib2, iclass 22, count 0 2006.225.07:51:58.84#ibcon#flushed, iclass 22, count 0 2006.225.07:51:58.84#ibcon#about to write, iclass 22, count 0 2006.225.07:51:58.84#ibcon#wrote, iclass 22, count 0 2006.225.07:51:58.84#ibcon#about to read 3, iclass 22, count 0 2006.225.07:51:58.86#ibcon#read 3, iclass 22, count 0 2006.225.07:51:58.86#ibcon#about to read 4, iclass 22, count 0 2006.225.07:51:58.86#ibcon#read 4, iclass 22, count 0 2006.225.07:51:58.86#ibcon#about to read 5, iclass 22, count 0 2006.225.07:51:58.86#ibcon#read 5, iclass 22, count 0 2006.225.07:51:58.87#ibcon#about to read 6, iclass 22, count 0 2006.225.07:51:58.87#ibcon#read 6, iclass 22, count 0 2006.225.07:51:58.87#ibcon#end of sib2, iclass 22, count 0 2006.225.07:51:58.87#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:51:58.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:51:58.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:51:58.87#ibcon#*before write, iclass 22, count 0 2006.225.07:51:58.87#ibcon#enter sib2, iclass 22, count 0 2006.225.07:51:58.87#ibcon#flushed, iclass 22, count 0 2006.225.07:51:58.87#ibcon#about to write, iclass 22, count 0 2006.225.07:51:58.87#ibcon#wrote, iclass 22, count 0 2006.225.07:51:58.87#ibcon#about to read 3, iclass 22, count 0 2006.225.07:51:58.91#ibcon#read 3, iclass 22, count 0 2006.225.07:51:58.91#ibcon#about to read 4, iclass 22, count 0 2006.225.07:51:58.91#ibcon#read 4, iclass 22, count 0 2006.225.07:51:58.91#ibcon#about to read 5, iclass 22, count 0 2006.225.07:51:58.91#ibcon#read 5, iclass 22, count 0 2006.225.07:51:58.91#ibcon#about to read 6, iclass 22, count 0 2006.225.07:51:58.91#ibcon#read 6, iclass 22, count 0 2006.225.07:51:58.91#ibcon#end of sib2, iclass 22, count 0 2006.225.07:51:58.91#ibcon#*after write, iclass 22, count 0 2006.225.07:51:58.91#ibcon#*before return 0, iclass 22, count 0 2006.225.07:51:58.91#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:51:58.91#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:51:58.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:51:58.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:51:58.91$vc4f8/va=4,7 2006.225.07:51:58.91#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.07:51:58.91#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.07:51:58.91#ibcon#ireg 11 cls_cnt 2 2006.225.07:51:58.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:51:58.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:51:58.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:51:58.96#ibcon#enter wrdev, iclass 24, count 2 2006.225.07:51:58.96#ibcon#first serial, iclass 24, count 2 2006.225.07:51:58.96#ibcon#enter sib2, iclass 24, count 2 2006.225.07:51:58.96#ibcon#flushed, iclass 24, count 2 2006.225.07:51:58.96#ibcon#about to write, iclass 24, count 2 2006.225.07:51:58.96#ibcon#wrote, iclass 24, count 2 2006.225.07:51:58.96#ibcon#about to read 3, iclass 24, count 2 2006.225.07:51:58.98#ibcon#read 3, iclass 24, count 2 2006.225.07:51:58.98#ibcon#about to read 4, iclass 24, count 2 2006.225.07:51:58.98#ibcon#read 4, iclass 24, count 2 2006.225.07:51:58.98#ibcon#about to read 5, iclass 24, count 2 2006.225.07:51:58.98#ibcon#read 5, iclass 24, count 2 2006.225.07:51:58.98#ibcon#about to read 6, iclass 24, count 2 2006.225.07:51:58.98#ibcon#read 6, iclass 24, count 2 2006.225.07:51:58.98#ibcon#end of sib2, iclass 24, count 2 2006.225.07:51:58.98#ibcon#*mode == 0, iclass 24, count 2 2006.225.07:51:58.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.07:51:58.98#ibcon#[25=AT04-07\r\n] 2006.225.07:51:58.98#ibcon#*before write, iclass 24, count 2 2006.225.07:51:58.98#ibcon#enter sib2, iclass 24, count 2 2006.225.07:51:58.98#ibcon#flushed, iclass 24, count 2 2006.225.07:51:58.98#ibcon#about to write, iclass 24, count 2 2006.225.07:51:58.98#ibcon#wrote, iclass 24, count 2 2006.225.07:51:58.98#ibcon#about to read 3, iclass 24, count 2 2006.225.07:51:59.01#ibcon#read 3, iclass 24, count 2 2006.225.07:51:59.01#ibcon#about to read 4, iclass 24, count 2 2006.225.07:51:59.01#ibcon#read 4, iclass 24, count 2 2006.225.07:51:59.01#ibcon#about to read 5, iclass 24, count 2 2006.225.07:51:59.01#ibcon#read 5, iclass 24, count 2 2006.225.07:51:59.01#ibcon#about to read 6, iclass 24, count 2 2006.225.07:51:59.01#ibcon#read 6, iclass 24, count 2 2006.225.07:51:59.01#ibcon#end of sib2, iclass 24, count 2 2006.225.07:51:59.01#ibcon#*after write, iclass 24, count 2 2006.225.07:51:59.01#ibcon#*before return 0, iclass 24, count 2 2006.225.07:51:59.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:51:59.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:51:59.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.07:51:59.01#ibcon#ireg 7 cls_cnt 0 2006.225.07:51:59.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:51:59.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:51:59.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:51:59.13#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:51:59.13#ibcon#first serial, iclass 24, count 0 2006.225.07:51:59.13#ibcon#enter sib2, iclass 24, count 0 2006.225.07:51:59.13#ibcon#flushed, iclass 24, count 0 2006.225.07:51:59.13#ibcon#about to write, iclass 24, count 0 2006.225.07:51:59.13#ibcon#wrote, iclass 24, count 0 2006.225.07:51:59.13#ibcon#about to read 3, iclass 24, count 0 2006.225.07:51:59.15#ibcon#read 3, iclass 24, count 0 2006.225.07:51:59.15#ibcon#about to read 4, iclass 24, count 0 2006.225.07:51:59.15#ibcon#read 4, iclass 24, count 0 2006.225.07:51:59.15#ibcon#about to read 5, iclass 24, count 0 2006.225.07:51:59.15#ibcon#read 5, iclass 24, count 0 2006.225.07:51:59.15#ibcon#about to read 6, iclass 24, count 0 2006.225.07:51:59.15#ibcon#read 6, iclass 24, count 0 2006.225.07:51:59.15#ibcon#end of sib2, iclass 24, count 0 2006.225.07:51:59.15#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:51:59.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:51:59.15#ibcon#[25=USB\r\n] 2006.225.07:51:59.15#ibcon#*before write, iclass 24, count 0 2006.225.07:51:59.15#ibcon#enter sib2, iclass 24, count 0 2006.225.07:51:59.15#ibcon#flushed, iclass 24, count 0 2006.225.07:51:59.15#ibcon#about to write, iclass 24, count 0 2006.225.07:51:59.15#ibcon#wrote, iclass 24, count 0 2006.225.07:51:59.15#ibcon#about to read 3, iclass 24, count 0 2006.225.07:51:59.18#ibcon#read 3, iclass 24, count 0 2006.225.07:51:59.18#ibcon#about to read 4, iclass 24, count 0 2006.225.07:51:59.18#ibcon#read 4, iclass 24, count 0 2006.225.07:51:59.18#ibcon#about to read 5, iclass 24, count 0 2006.225.07:51:59.18#ibcon#read 5, iclass 24, count 0 2006.225.07:51:59.18#ibcon#about to read 6, iclass 24, count 0 2006.225.07:51:59.18#ibcon#read 6, iclass 24, count 0 2006.225.07:51:59.18#ibcon#end of sib2, iclass 24, count 0 2006.225.07:51:59.18#ibcon#*after write, iclass 24, count 0 2006.225.07:51:59.18#ibcon#*before return 0, iclass 24, count 0 2006.225.07:51:59.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:51:59.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:51:59.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:51:59.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:51:59.18$vc4f8/valo=5,652.99 2006.225.07:51:59.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.07:51:59.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.07:51:59.18#ibcon#ireg 17 cls_cnt 0 2006.225.07:51:59.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:51:59.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:51:59.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:51:59.18#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:51:59.18#ibcon#first serial, iclass 26, count 0 2006.225.07:51:59.18#ibcon#enter sib2, iclass 26, count 0 2006.225.07:51:59.18#ibcon#flushed, iclass 26, count 0 2006.225.07:51:59.18#ibcon#about to write, iclass 26, count 0 2006.225.07:51:59.18#ibcon#wrote, iclass 26, count 0 2006.225.07:51:59.18#ibcon#about to read 3, iclass 26, count 0 2006.225.07:51:59.20#ibcon#read 3, iclass 26, count 0 2006.225.07:51:59.20#ibcon#about to read 4, iclass 26, count 0 2006.225.07:51:59.20#ibcon#read 4, iclass 26, count 0 2006.225.07:51:59.20#ibcon#about to read 5, iclass 26, count 0 2006.225.07:51:59.20#ibcon#read 5, iclass 26, count 0 2006.225.07:51:59.20#ibcon#about to read 6, iclass 26, count 0 2006.225.07:51:59.20#ibcon#read 6, iclass 26, count 0 2006.225.07:51:59.20#ibcon#end of sib2, iclass 26, count 0 2006.225.07:51:59.20#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:51:59.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:51:59.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:51:59.20#ibcon#*before write, iclass 26, count 0 2006.225.07:51:59.20#ibcon#enter sib2, iclass 26, count 0 2006.225.07:51:59.20#ibcon#flushed, iclass 26, count 0 2006.225.07:51:59.20#ibcon#about to write, iclass 26, count 0 2006.225.07:51:59.20#ibcon#wrote, iclass 26, count 0 2006.225.07:51:59.20#ibcon#about to read 3, iclass 26, count 0 2006.225.07:51:59.24#ibcon#read 3, iclass 26, count 0 2006.225.07:51:59.24#ibcon#about to read 4, iclass 26, count 0 2006.225.07:51:59.24#ibcon#read 4, iclass 26, count 0 2006.225.07:51:59.24#ibcon#about to read 5, iclass 26, count 0 2006.225.07:51:59.24#ibcon#read 5, iclass 26, count 0 2006.225.07:51:59.24#ibcon#about to read 6, iclass 26, count 0 2006.225.07:51:59.24#ibcon#read 6, iclass 26, count 0 2006.225.07:51:59.24#ibcon#end of sib2, iclass 26, count 0 2006.225.07:51:59.24#ibcon#*after write, iclass 26, count 0 2006.225.07:51:59.24#ibcon#*before return 0, iclass 26, count 0 2006.225.07:51:59.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:51:59.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:51:59.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:51:59.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:51:59.24$vc4f8/va=5,7 2006.225.07:51:59.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.07:51:59.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.07:51:59.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:51:59.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:51:59.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:51:59.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:51:59.30#ibcon#enter wrdev, iclass 28, count 2 2006.225.07:51:59.30#ibcon#first serial, iclass 28, count 2 2006.225.07:51:59.30#ibcon#enter sib2, iclass 28, count 2 2006.225.07:51:59.30#ibcon#flushed, iclass 28, count 2 2006.225.07:51:59.30#ibcon#about to write, iclass 28, count 2 2006.225.07:51:59.30#ibcon#wrote, iclass 28, count 2 2006.225.07:51:59.30#ibcon#about to read 3, iclass 28, count 2 2006.225.07:51:59.32#ibcon#read 3, iclass 28, count 2 2006.225.07:51:59.32#ibcon#about to read 4, iclass 28, count 2 2006.225.07:51:59.32#ibcon#read 4, iclass 28, count 2 2006.225.07:51:59.32#ibcon#about to read 5, iclass 28, count 2 2006.225.07:51:59.32#ibcon#read 5, iclass 28, count 2 2006.225.07:51:59.32#ibcon#about to read 6, iclass 28, count 2 2006.225.07:51:59.32#ibcon#read 6, iclass 28, count 2 2006.225.07:51:59.32#ibcon#end of sib2, iclass 28, count 2 2006.225.07:51:59.32#ibcon#*mode == 0, iclass 28, count 2 2006.225.07:51:59.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.07:51:59.32#ibcon#[25=AT05-07\r\n] 2006.225.07:51:59.32#ibcon#*before write, iclass 28, count 2 2006.225.07:51:59.32#ibcon#enter sib2, iclass 28, count 2 2006.225.07:51:59.32#ibcon#flushed, iclass 28, count 2 2006.225.07:51:59.32#ibcon#about to write, iclass 28, count 2 2006.225.07:51:59.32#ibcon#wrote, iclass 28, count 2 2006.225.07:51:59.32#ibcon#about to read 3, iclass 28, count 2 2006.225.07:51:59.35#ibcon#read 3, iclass 28, count 2 2006.225.07:51:59.35#ibcon#about to read 4, iclass 28, count 2 2006.225.07:51:59.35#ibcon#read 4, iclass 28, count 2 2006.225.07:51:59.35#ibcon#about to read 5, iclass 28, count 2 2006.225.07:51:59.35#ibcon#read 5, iclass 28, count 2 2006.225.07:51:59.35#ibcon#about to read 6, iclass 28, count 2 2006.225.07:51:59.35#ibcon#read 6, iclass 28, count 2 2006.225.07:51:59.35#ibcon#end of sib2, iclass 28, count 2 2006.225.07:51:59.35#ibcon#*after write, iclass 28, count 2 2006.225.07:51:59.35#ibcon#*before return 0, iclass 28, count 2 2006.225.07:51:59.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:51:59.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:51:59.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.07:51:59.35#ibcon#ireg 7 cls_cnt 0 2006.225.07:51:59.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:51:59.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:51:59.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:51:59.47#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:51:59.47#ibcon#first serial, iclass 28, count 0 2006.225.07:51:59.47#ibcon#enter sib2, iclass 28, count 0 2006.225.07:51:59.47#ibcon#flushed, iclass 28, count 0 2006.225.07:51:59.47#ibcon#about to write, iclass 28, count 0 2006.225.07:51:59.47#ibcon#wrote, iclass 28, count 0 2006.225.07:51:59.47#ibcon#about to read 3, iclass 28, count 0 2006.225.07:51:59.49#ibcon#read 3, iclass 28, count 0 2006.225.07:51:59.49#ibcon#about to read 4, iclass 28, count 0 2006.225.07:51:59.49#ibcon#read 4, iclass 28, count 0 2006.225.07:51:59.49#ibcon#about to read 5, iclass 28, count 0 2006.225.07:51:59.49#ibcon#read 5, iclass 28, count 0 2006.225.07:51:59.49#ibcon#about to read 6, iclass 28, count 0 2006.225.07:51:59.49#ibcon#read 6, iclass 28, count 0 2006.225.07:51:59.49#ibcon#end of sib2, iclass 28, count 0 2006.225.07:51:59.49#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:51:59.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:51:59.49#ibcon#[25=USB\r\n] 2006.225.07:51:59.49#ibcon#*before write, iclass 28, count 0 2006.225.07:51:59.49#ibcon#enter sib2, iclass 28, count 0 2006.225.07:51:59.49#ibcon#flushed, iclass 28, count 0 2006.225.07:51:59.49#ibcon#about to write, iclass 28, count 0 2006.225.07:51:59.49#ibcon#wrote, iclass 28, count 0 2006.225.07:51:59.49#ibcon#about to read 3, iclass 28, count 0 2006.225.07:51:59.52#ibcon#read 3, iclass 28, count 0 2006.225.07:51:59.52#ibcon#about to read 4, iclass 28, count 0 2006.225.07:51:59.52#ibcon#read 4, iclass 28, count 0 2006.225.07:51:59.52#ibcon#about to read 5, iclass 28, count 0 2006.225.07:51:59.52#ibcon#read 5, iclass 28, count 0 2006.225.07:51:59.52#ibcon#about to read 6, iclass 28, count 0 2006.225.07:51:59.52#ibcon#read 6, iclass 28, count 0 2006.225.07:51:59.52#ibcon#end of sib2, iclass 28, count 0 2006.225.07:51:59.52#ibcon#*after write, iclass 28, count 0 2006.225.07:51:59.52#ibcon#*before return 0, iclass 28, count 0 2006.225.07:51:59.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:51:59.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:51:59.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:51:59.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:51:59.52$vc4f8/valo=6,772.99 2006.225.07:51:59.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.07:51:59.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.07:51:59.52#ibcon#ireg 17 cls_cnt 0 2006.225.07:51:59.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:51:59.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:51:59.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:51:59.52#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:51:59.52#ibcon#first serial, iclass 30, count 0 2006.225.07:51:59.52#ibcon#enter sib2, iclass 30, count 0 2006.225.07:51:59.52#ibcon#flushed, iclass 30, count 0 2006.225.07:51:59.52#ibcon#about to write, iclass 30, count 0 2006.225.07:51:59.52#ibcon#wrote, iclass 30, count 0 2006.225.07:51:59.52#ibcon#about to read 3, iclass 30, count 0 2006.225.07:51:59.54#ibcon#read 3, iclass 30, count 0 2006.225.07:51:59.54#ibcon#about to read 4, iclass 30, count 0 2006.225.07:51:59.54#ibcon#read 4, iclass 30, count 0 2006.225.07:51:59.54#ibcon#about to read 5, iclass 30, count 0 2006.225.07:51:59.54#ibcon#read 5, iclass 30, count 0 2006.225.07:51:59.54#ibcon#about to read 6, iclass 30, count 0 2006.225.07:51:59.54#ibcon#read 6, iclass 30, count 0 2006.225.07:51:59.54#ibcon#end of sib2, iclass 30, count 0 2006.225.07:51:59.54#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:51:59.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:51:59.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:51:59.54#ibcon#*before write, iclass 30, count 0 2006.225.07:51:59.54#ibcon#enter sib2, iclass 30, count 0 2006.225.07:51:59.54#ibcon#flushed, iclass 30, count 0 2006.225.07:51:59.54#ibcon#about to write, iclass 30, count 0 2006.225.07:51:59.54#ibcon#wrote, iclass 30, count 0 2006.225.07:51:59.54#ibcon#about to read 3, iclass 30, count 0 2006.225.07:51:59.58#ibcon#read 3, iclass 30, count 0 2006.225.07:51:59.58#ibcon#about to read 4, iclass 30, count 0 2006.225.07:51:59.58#ibcon#read 4, iclass 30, count 0 2006.225.07:51:59.58#ibcon#about to read 5, iclass 30, count 0 2006.225.07:51:59.58#ibcon#read 5, iclass 30, count 0 2006.225.07:51:59.58#ibcon#about to read 6, iclass 30, count 0 2006.225.07:51:59.58#ibcon#read 6, iclass 30, count 0 2006.225.07:51:59.58#ibcon#end of sib2, iclass 30, count 0 2006.225.07:51:59.58#ibcon#*after write, iclass 30, count 0 2006.225.07:51:59.58#ibcon#*before return 0, iclass 30, count 0 2006.225.07:51:59.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:51:59.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:51:59.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:51:59.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:51:59.58$vc4f8/va=6,6 2006.225.07:51:59.58#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.225.07:51:59.58#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.225.07:51:59.58#ibcon#ireg 11 cls_cnt 2 2006.225.07:51:59.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:51:59.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:51:59.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:51:59.64#ibcon#enter wrdev, iclass 32, count 2 2006.225.07:51:59.64#ibcon#first serial, iclass 32, count 2 2006.225.07:51:59.64#ibcon#enter sib2, iclass 32, count 2 2006.225.07:51:59.64#ibcon#flushed, iclass 32, count 2 2006.225.07:51:59.64#ibcon#about to write, iclass 32, count 2 2006.225.07:51:59.64#ibcon#wrote, iclass 32, count 2 2006.225.07:51:59.64#ibcon#about to read 3, iclass 32, count 2 2006.225.07:51:59.66#ibcon#read 3, iclass 32, count 2 2006.225.07:51:59.66#ibcon#about to read 4, iclass 32, count 2 2006.225.07:51:59.66#ibcon#read 4, iclass 32, count 2 2006.225.07:51:59.66#ibcon#about to read 5, iclass 32, count 2 2006.225.07:51:59.66#ibcon#read 5, iclass 32, count 2 2006.225.07:51:59.66#ibcon#about to read 6, iclass 32, count 2 2006.225.07:51:59.66#ibcon#read 6, iclass 32, count 2 2006.225.07:51:59.66#ibcon#end of sib2, iclass 32, count 2 2006.225.07:51:59.66#ibcon#*mode == 0, iclass 32, count 2 2006.225.07:51:59.66#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.225.07:51:59.66#ibcon#[25=AT06-06\r\n] 2006.225.07:51:59.66#ibcon#*before write, iclass 32, count 2 2006.225.07:51:59.66#ibcon#enter sib2, iclass 32, count 2 2006.225.07:51:59.66#ibcon#flushed, iclass 32, count 2 2006.225.07:51:59.66#ibcon#about to write, iclass 32, count 2 2006.225.07:51:59.66#ibcon#wrote, iclass 32, count 2 2006.225.07:51:59.66#ibcon#about to read 3, iclass 32, count 2 2006.225.07:51:59.69#ibcon#read 3, iclass 32, count 2 2006.225.07:51:59.69#ibcon#about to read 4, iclass 32, count 2 2006.225.07:51:59.69#ibcon#read 4, iclass 32, count 2 2006.225.07:51:59.69#ibcon#about to read 5, iclass 32, count 2 2006.225.07:51:59.69#ibcon#read 5, iclass 32, count 2 2006.225.07:51:59.69#ibcon#about to read 6, iclass 32, count 2 2006.225.07:51:59.69#ibcon#read 6, iclass 32, count 2 2006.225.07:51:59.69#ibcon#end of sib2, iclass 32, count 2 2006.225.07:51:59.69#ibcon#*after write, iclass 32, count 2 2006.225.07:51:59.69#ibcon#*before return 0, iclass 32, count 2 2006.225.07:51:59.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:51:59.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.225.07:51:59.69#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.225.07:51:59.69#ibcon#ireg 7 cls_cnt 0 2006.225.07:51:59.69#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:51:59.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:51:59.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:51:59.81#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:51:59.81#ibcon#first serial, iclass 32, count 0 2006.225.07:51:59.81#ibcon#enter sib2, iclass 32, count 0 2006.225.07:51:59.81#ibcon#flushed, iclass 32, count 0 2006.225.07:51:59.81#ibcon#about to write, iclass 32, count 0 2006.225.07:51:59.81#ibcon#wrote, iclass 32, count 0 2006.225.07:51:59.81#ibcon#about to read 3, iclass 32, count 0 2006.225.07:51:59.83#ibcon#read 3, iclass 32, count 0 2006.225.07:51:59.83#ibcon#about to read 4, iclass 32, count 0 2006.225.07:51:59.83#ibcon#read 4, iclass 32, count 0 2006.225.07:51:59.83#ibcon#about to read 5, iclass 32, count 0 2006.225.07:51:59.83#ibcon#read 5, iclass 32, count 0 2006.225.07:51:59.83#ibcon#about to read 6, iclass 32, count 0 2006.225.07:51:59.83#ibcon#read 6, iclass 32, count 0 2006.225.07:51:59.83#ibcon#end of sib2, iclass 32, count 0 2006.225.07:51:59.83#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:51:59.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:51:59.83#ibcon#[25=USB\r\n] 2006.225.07:51:59.83#ibcon#*before write, iclass 32, count 0 2006.225.07:51:59.83#ibcon#enter sib2, iclass 32, count 0 2006.225.07:51:59.83#ibcon#flushed, iclass 32, count 0 2006.225.07:51:59.83#ibcon#about to write, iclass 32, count 0 2006.225.07:51:59.83#ibcon#wrote, iclass 32, count 0 2006.225.07:51:59.83#ibcon#about to read 3, iclass 32, count 0 2006.225.07:51:59.86#ibcon#read 3, iclass 32, count 0 2006.225.07:51:59.86#ibcon#about to read 4, iclass 32, count 0 2006.225.07:51:59.86#ibcon#read 4, iclass 32, count 0 2006.225.07:51:59.86#ibcon#about to read 5, iclass 32, count 0 2006.225.07:51:59.86#ibcon#read 5, iclass 32, count 0 2006.225.07:51:59.86#ibcon#about to read 6, iclass 32, count 0 2006.225.07:51:59.86#ibcon#read 6, iclass 32, count 0 2006.225.07:51:59.86#ibcon#end of sib2, iclass 32, count 0 2006.225.07:51:59.86#ibcon#*after write, iclass 32, count 0 2006.225.07:51:59.86#ibcon#*before return 0, iclass 32, count 0 2006.225.07:51:59.86#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:51:59.86#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.225.07:51:59.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:51:59.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:51:59.86$vc4f8/valo=7,832.99 2006.225.07:51:59.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.07:51:59.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.07:51:59.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:51:59.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:51:59.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:51:59.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:51:59.86#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:51:59.86#ibcon#first serial, iclass 34, count 0 2006.225.07:51:59.86#ibcon#enter sib2, iclass 34, count 0 2006.225.07:51:59.86#ibcon#flushed, iclass 34, count 0 2006.225.07:51:59.86#ibcon#about to write, iclass 34, count 0 2006.225.07:51:59.86#ibcon#wrote, iclass 34, count 0 2006.225.07:51:59.86#ibcon#about to read 3, iclass 34, count 0 2006.225.07:51:59.88#ibcon#read 3, iclass 34, count 0 2006.225.07:51:59.88#ibcon#about to read 4, iclass 34, count 0 2006.225.07:51:59.88#ibcon#read 4, iclass 34, count 0 2006.225.07:51:59.88#ibcon#about to read 5, iclass 34, count 0 2006.225.07:51:59.88#ibcon#read 5, iclass 34, count 0 2006.225.07:51:59.88#ibcon#about to read 6, iclass 34, count 0 2006.225.07:51:59.88#ibcon#read 6, iclass 34, count 0 2006.225.07:51:59.88#ibcon#end of sib2, iclass 34, count 0 2006.225.07:51:59.88#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:51:59.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:51:59.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:51:59.88#ibcon#*before write, iclass 34, count 0 2006.225.07:51:59.88#ibcon#enter sib2, iclass 34, count 0 2006.225.07:51:59.88#ibcon#flushed, iclass 34, count 0 2006.225.07:51:59.88#ibcon#about to write, iclass 34, count 0 2006.225.07:51:59.88#ibcon#wrote, iclass 34, count 0 2006.225.07:51:59.88#ibcon#about to read 3, iclass 34, count 0 2006.225.07:51:59.92#ibcon#read 3, iclass 34, count 0 2006.225.07:51:59.92#ibcon#about to read 4, iclass 34, count 0 2006.225.07:51:59.92#ibcon#read 4, iclass 34, count 0 2006.225.07:51:59.92#ibcon#about to read 5, iclass 34, count 0 2006.225.07:51:59.92#ibcon#read 5, iclass 34, count 0 2006.225.07:51:59.92#ibcon#about to read 6, iclass 34, count 0 2006.225.07:51:59.92#ibcon#read 6, iclass 34, count 0 2006.225.07:51:59.92#ibcon#end of sib2, iclass 34, count 0 2006.225.07:51:59.92#ibcon#*after write, iclass 34, count 0 2006.225.07:51:59.92#ibcon#*before return 0, iclass 34, count 0 2006.225.07:51:59.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:51:59.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.07:51:59.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:51:59.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:51:59.92$vc4f8/va=7,6 2006.225.07:51:59.92#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.07:51:59.92#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.07:51:59.92#ibcon#ireg 11 cls_cnt 2 2006.225.07:51:59.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:51:59.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:51:59.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:51:59.98#ibcon#enter wrdev, iclass 36, count 2 2006.225.07:51:59.98#ibcon#first serial, iclass 36, count 2 2006.225.07:51:59.98#ibcon#enter sib2, iclass 36, count 2 2006.225.07:51:59.98#ibcon#flushed, iclass 36, count 2 2006.225.07:51:59.98#ibcon#about to write, iclass 36, count 2 2006.225.07:51:59.98#ibcon#wrote, iclass 36, count 2 2006.225.07:51:59.98#ibcon#about to read 3, iclass 36, count 2 2006.225.07:52:00.00#ibcon#read 3, iclass 36, count 2 2006.225.07:52:00.00#ibcon#about to read 4, iclass 36, count 2 2006.225.07:52:00.00#ibcon#read 4, iclass 36, count 2 2006.225.07:52:00.00#ibcon#about to read 5, iclass 36, count 2 2006.225.07:52:00.00#ibcon#read 5, iclass 36, count 2 2006.225.07:52:00.00#ibcon#about to read 6, iclass 36, count 2 2006.225.07:52:00.00#ibcon#read 6, iclass 36, count 2 2006.225.07:52:00.00#ibcon#end of sib2, iclass 36, count 2 2006.225.07:52:00.00#ibcon#*mode == 0, iclass 36, count 2 2006.225.07:52:00.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.07:52:00.00#ibcon#[25=AT07-06\r\n] 2006.225.07:52:00.00#ibcon#*before write, iclass 36, count 2 2006.225.07:52:00.00#ibcon#enter sib2, iclass 36, count 2 2006.225.07:52:00.00#ibcon#flushed, iclass 36, count 2 2006.225.07:52:00.00#ibcon#about to write, iclass 36, count 2 2006.225.07:52:00.00#ibcon#wrote, iclass 36, count 2 2006.225.07:52:00.00#ibcon#about to read 3, iclass 36, count 2 2006.225.07:52:00.03#ibcon#read 3, iclass 36, count 2 2006.225.07:52:00.03#ibcon#about to read 4, iclass 36, count 2 2006.225.07:52:00.03#ibcon#read 4, iclass 36, count 2 2006.225.07:52:00.03#ibcon#about to read 5, iclass 36, count 2 2006.225.07:52:00.03#ibcon#read 5, iclass 36, count 2 2006.225.07:52:00.03#ibcon#about to read 6, iclass 36, count 2 2006.225.07:52:00.03#ibcon#read 6, iclass 36, count 2 2006.225.07:52:00.03#ibcon#end of sib2, iclass 36, count 2 2006.225.07:52:00.03#ibcon#*after write, iclass 36, count 2 2006.225.07:52:00.03#ibcon#*before return 0, iclass 36, count 2 2006.225.07:52:00.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:52:00.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.07:52:00.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.07:52:00.03#ibcon#ireg 7 cls_cnt 0 2006.225.07:52:00.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:52:00.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:52:00.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:52:00.15#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:52:00.15#ibcon#first serial, iclass 36, count 0 2006.225.07:52:00.15#ibcon#enter sib2, iclass 36, count 0 2006.225.07:52:00.15#ibcon#flushed, iclass 36, count 0 2006.225.07:52:00.15#ibcon#about to write, iclass 36, count 0 2006.225.07:52:00.15#ibcon#wrote, iclass 36, count 0 2006.225.07:52:00.15#ibcon#about to read 3, iclass 36, count 0 2006.225.07:52:00.17#ibcon#read 3, iclass 36, count 0 2006.225.07:52:00.17#ibcon#about to read 4, iclass 36, count 0 2006.225.07:52:00.17#ibcon#read 4, iclass 36, count 0 2006.225.07:52:00.17#ibcon#about to read 5, iclass 36, count 0 2006.225.07:52:00.17#ibcon#read 5, iclass 36, count 0 2006.225.07:52:00.17#ibcon#about to read 6, iclass 36, count 0 2006.225.07:52:00.17#ibcon#read 6, iclass 36, count 0 2006.225.07:52:00.17#ibcon#end of sib2, iclass 36, count 0 2006.225.07:52:00.17#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:52:00.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:52:00.17#ibcon#[25=USB\r\n] 2006.225.07:52:00.17#ibcon#*before write, iclass 36, count 0 2006.225.07:52:00.17#ibcon#enter sib2, iclass 36, count 0 2006.225.07:52:00.17#ibcon#flushed, iclass 36, count 0 2006.225.07:52:00.17#ibcon#about to write, iclass 36, count 0 2006.225.07:52:00.17#ibcon#wrote, iclass 36, count 0 2006.225.07:52:00.17#ibcon#about to read 3, iclass 36, count 0 2006.225.07:52:00.20#ibcon#read 3, iclass 36, count 0 2006.225.07:52:00.20#ibcon#about to read 4, iclass 36, count 0 2006.225.07:52:00.20#ibcon#read 4, iclass 36, count 0 2006.225.07:52:00.20#ibcon#about to read 5, iclass 36, count 0 2006.225.07:52:00.20#ibcon#read 5, iclass 36, count 0 2006.225.07:52:00.20#ibcon#about to read 6, iclass 36, count 0 2006.225.07:52:00.20#ibcon#read 6, iclass 36, count 0 2006.225.07:52:00.20#ibcon#end of sib2, iclass 36, count 0 2006.225.07:52:00.20#ibcon#*after write, iclass 36, count 0 2006.225.07:52:00.20#ibcon#*before return 0, iclass 36, count 0 2006.225.07:52:00.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:52:00.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.07:52:00.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:52:00.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:52:00.20$vc4f8/valo=8,852.99 2006.225.07:52:00.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.07:52:00.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.07:52:00.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:52:00.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:52:00.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:52:00.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:52:00.20#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:52:00.20#ibcon#first serial, iclass 38, count 0 2006.225.07:52:00.20#ibcon#enter sib2, iclass 38, count 0 2006.225.07:52:00.20#ibcon#flushed, iclass 38, count 0 2006.225.07:52:00.20#ibcon#about to write, iclass 38, count 0 2006.225.07:52:00.20#ibcon#wrote, iclass 38, count 0 2006.225.07:52:00.20#ibcon#about to read 3, iclass 38, count 0 2006.225.07:52:00.22#ibcon#read 3, iclass 38, count 0 2006.225.07:52:00.22#ibcon#about to read 4, iclass 38, count 0 2006.225.07:52:00.22#ibcon#read 4, iclass 38, count 0 2006.225.07:52:00.22#ibcon#about to read 5, iclass 38, count 0 2006.225.07:52:00.22#ibcon#read 5, iclass 38, count 0 2006.225.07:52:00.22#ibcon#about to read 6, iclass 38, count 0 2006.225.07:52:00.22#ibcon#read 6, iclass 38, count 0 2006.225.07:52:00.22#ibcon#end of sib2, iclass 38, count 0 2006.225.07:52:00.22#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:52:00.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:52:00.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:52:00.22#ibcon#*before write, iclass 38, count 0 2006.225.07:52:00.22#ibcon#enter sib2, iclass 38, count 0 2006.225.07:52:00.22#ibcon#flushed, iclass 38, count 0 2006.225.07:52:00.22#ibcon#about to write, iclass 38, count 0 2006.225.07:52:00.22#ibcon#wrote, iclass 38, count 0 2006.225.07:52:00.22#ibcon#about to read 3, iclass 38, count 0 2006.225.07:52:00.26#ibcon#read 3, iclass 38, count 0 2006.225.07:52:00.26#ibcon#about to read 4, iclass 38, count 0 2006.225.07:52:00.26#ibcon#read 4, iclass 38, count 0 2006.225.07:52:00.26#ibcon#about to read 5, iclass 38, count 0 2006.225.07:52:00.26#ibcon#read 5, iclass 38, count 0 2006.225.07:52:00.26#ibcon#about to read 6, iclass 38, count 0 2006.225.07:52:00.26#ibcon#read 6, iclass 38, count 0 2006.225.07:52:00.26#ibcon#end of sib2, iclass 38, count 0 2006.225.07:52:00.26#ibcon#*after write, iclass 38, count 0 2006.225.07:52:00.26#ibcon#*before return 0, iclass 38, count 0 2006.225.07:52:00.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:52:00.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.07:52:00.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:52:00.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:52:00.26$vc4f8/va=8,7 2006.225.07:52:00.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.225.07:52:00.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.225.07:52:00.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:52:00.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:52:00.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:52:00.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:52:00.32#ibcon#enter wrdev, iclass 40, count 2 2006.225.07:52:00.32#ibcon#first serial, iclass 40, count 2 2006.225.07:52:00.32#ibcon#enter sib2, iclass 40, count 2 2006.225.07:52:00.32#ibcon#flushed, iclass 40, count 2 2006.225.07:52:00.32#ibcon#about to write, iclass 40, count 2 2006.225.07:52:00.32#ibcon#wrote, iclass 40, count 2 2006.225.07:52:00.32#ibcon#about to read 3, iclass 40, count 2 2006.225.07:52:00.34#ibcon#read 3, iclass 40, count 2 2006.225.07:52:00.34#ibcon#about to read 4, iclass 40, count 2 2006.225.07:52:00.34#ibcon#read 4, iclass 40, count 2 2006.225.07:52:00.34#ibcon#about to read 5, iclass 40, count 2 2006.225.07:52:00.34#ibcon#read 5, iclass 40, count 2 2006.225.07:52:00.34#ibcon#about to read 6, iclass 40, count 2 2006.225.07:52:00.34#ibcon#read 6, iclass 40, count 2 2006.225.07:52:00.34#ibcon#end of sib2, iclass 40, count 2 2006.225.07:52:00.34#ibcon#*mode == 0, iclass 40, count 2 2006.225.07:52:00.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.225.07:52:00.34#ibcon#[25=AT08-07\r\n] 2006.225.07:52:00.34#ibcon#*before write, iclass 40, count 2 2006.225.07:52:00.34#ibcon#enter sib2, iclass 40, count 2 2006.225.07:52:00.34#ibcon#flushed, iclass 40, count 2 2006.225.07:52:00.34#ibcon#about to write, iclass 40, count 2 2006.225.07:52:00.34#ibcon#wrote, iclass 40, count 2 2006.225.07:52:00.34#ibcon#about to read 3, iclass 40, count 2 2006.225.07:52:00.37#ibcon#read 3, iclass 40, count 2 2006.225.07:52:00.37#ibcon#about to read 4, iclass 40, count 2 2006.225.07:52:00.37#ibcon#read 4, iclass 40, count 2 2006.225.07:52:00.37#ibcon#about to read 5, iclass 40, count 2 2006.225.07:52:00.37#ibcon#read 5, iclass 40, count 2 2006.225.07:52:00.37#ibcon#about to read 6, iclass 40, count 2 2006.225.07:52:00.37#ibcon#read 6, iclass 40, count 2 2006.225.07:52:00.37#ibcon#end of sib2, iclass 40, count 2 2006.225.07:52:00.37#ibcon#*after write, iclass 40, count 2 2006.225.07:52:00.37#ibcon#*before return 0, iclass 40, count 2 2006.225.07:52:00.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:52:00.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.225.07:52:00.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.225.07:52:00.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:52:00.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:52:00.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:52:00.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:52:00.49#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:52:00.49#ibcon#first serial, iclass 40, count 0 2006.225.07:52:00.49#ibcon#enter sib2, iclass 40, count 0 2006.225.07:52:00.49#ibcon#flushed, iclass 40, count 0 2006.225.07:52:00.49#ibcon#about to write, iclass 40, count 0 2006.225.07:52:00.49#ibcon#wrote, iclass 40, count 0 2006.225.07:52:00.49#ibcon#about to read 3, iclass 40, count 0 2006.225.07:52:00.51#ibcon#read 3, iclass 40, count 0 2006.225.07:52:00.51#ibcon#about to read 4, iclass 40, count 0 2006.225.07:52:00.51#ibcon#read 4, iclass 40, count 0 2006.225.07:52:00.51#ibcon#about to read 5, iclass 40, count 0 2006.225.07:52:00.51#ibcon#read 5, iclass 40, count 0 2006.225.07:52:00.51#ibcon#about to read 6, iclass 40, count 0 2006.225.07:52:00.51#ibcon#read 6, iclass 40, count 0 2006.225.07:52:00.51#ibcon#end of sib2, iclass 40, count 0 2006.225.07:52:00.51#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:52:00.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:52:00.51#ibcon#[25=USB\r\n] 2006.225.07:52:00.51#ibcon#*before write, iclass 40, count 0 2006.225.07:52:00.51#ibcon#enter sib2, iclass 40, count 0 2006.225.07:52:00.51#ibcon#flushed, iclass 40, count 0 2006.225.07:52:00.51#ibcon#about to write, iclass 40, count 0 2006.225.07:52:00.51#ibcon#wrote, iclass 40, count 0 2006.225.07:52:00.51#ibcon#about to read 3, iclass 40, count 0 2006.225.07:52:00.54#ibcon#read 3, iclass 40, count 0 2006.225.07:52:00.54#ibcon#about to read 4, iclass 40, count 0 2006.225.07:52:00.54#ibcon#read 4, iclass 40, count 0 2006.225.07:52:00.54#ibcon#about to read 5, iclass 40, count 0 2006.225.07:52:00.54#ibcon#read 5, iclass 40, count 0 2006.225.07:52:00.54#ibcon#about to read 6, iclass 40, count 0 2006.225.07:52:00.54#ibcon#read 6, iclass 40, count 0 2006.225.07:52:00.54#ibcon#end of sib2, iclass 40, count 0 2006.225.07:52:00.54#ibcon#*after write, iclass 40, count 0 2006.225.07:52:00.54#ibcon#*before return 0, iclass 40, count 0 2006.225.07:52:00.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:52:00.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.225.07:52:00.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:52:00.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:52:00.54$vc4f8/vblo=1,632.99 2006.225.07:52:00.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.07:52:00.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.07:52:00.54#ibcon#ireg 17 cls_cnt 0 2006.225.07:52:00.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:52:00.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:52:00.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:52:00.54#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:52:00.54#ibcon#first serial, iclass 4, count 0 2006.225.07:52:00.54#ibcon#enter sib2, iclass 4, count 0 2006.225.07:52:00.54#ibcon#flushed, iclass 4, count 0 2006.225.07:52:00.54#ibcon#about to write, iclass 4, count 0 2006.225.07:52:00.54#ibcon#wrote, iclass 4, count 0 2006.225.07:52:00.54#ibcon#about to read 3, iclass 4, count 0 2006.225.07:52:00.56#ibcon#read 3, iclass 4, count 0 2006.225.07:52:00.56#ibcon#about to read 4, iclass 4, count 0 2006.225.07:52:00.56#ibcon#read 4, iclass 4, count 0 2006.225.07:52:00.56#ibcon#about to read 5, iclass 4, count 0 2006.225.07:52:00.57#ibcon#read 5, iclass 4, count 0 2006.225.07:52:00.57#ibcon#about to read 6, iclass 4, count 0 2006.225.07:52:00.57#ibcon#read 6, iclass 4, count 0 2006.225.07:52:00.57#ibcon#end of sib2, iclass 4, count 0 2006.225.07:52:00.57#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:52:00.57#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:52:00.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:52:00.57#ibcon#*before write, iclass 4, count 0 2006.225.07:52:00.57#ibcon#enter sib2, iclass 4, count 0 2006.225.07:52:00.57#ibcon#flushed, iclass 4, count 0 2006.225.07:52:00.57#ibcon#about to write, iclass 4, count 0 2006.225.07:52:00.57#ibcon#wrote, iclass 4, count 0 2006.225.07:52:00.57#ibcon#about to read 3, iclass 4, count 0 2006.225.07:52:00.61#ibcon#read 3, iclass 4, count 0 2006.225.07:52:00.61#ibcon#about to read 4, iclass 4, count 0 2006.225.07:52:00.61#ibcon#read 4, iclass 4, count 0 2006.225.07:52:00.61#ibcon#about to read 5, iclass 4, count 0 2006.225.07:52:00.61#ibcon#read 5, iclass 4, count 0 2006.225.07:52:00.61#ibcon#about to read 6, iclass 4, count 0 2006.225.07:52:00.61#ibcon#read 6, iclass 4, count 0 2006.225.07:52:00.61#ibcon#end of sib2, iclass 4, count 0 2006.225.07:52:00.61#ibcon#*after write, iclass 4, count 0 2006.225.07:52:00.61#ibcon#*before return 0, iclass 4, count 0 2006.225.07:52:00.61#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:52:00.61#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.07:52:00.61#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:52:00.61#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:52:00.61$vc4f8/vb=1,4 2006.225.07:52:00.61#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.225.07:52:00.61#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.225.07:52:00.61#ibcon#ireg 11 cls_cnt 2 2006.225.07:52:00.61#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:52:00.61#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:52:00.61#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:52:00.61#ibcon#enter wrdev, iclass 6, count 2 2006.225.07:52:00.61#ibcon#first serial, iclass 6, count 2 2006.225.07:52:00.61#ibcon#enter sib2, iclass 6, count 2 2006.225.07:52:00.61#ibcon#flushed, iclass 6, count 2 2006.225.07:52:00.61#ibcon#about to write, iclass 6, count 2 2006.225.07:52:00.61#ibcon#wrote, iclass 6, count 2 2006.225.07:52:00.61#ibcon#about to read 3, iclass 6, count 2 2006.225.07:52:00.63#ibcon#read 3, iclass 6, count 2 2006.225.07:52:00.63#ibcon#about to read 4, iclass 6, count 2 2006.225.07:52:00.63#ibcon#read 4, iclass 6, count 2 2006.225.07:52:00.63#ibcon#about to read 5, iclass 6, count 2 2006.225.07:52:00.63#ibcon#read 5, iclass 6, count 2 2006.225.07:52:00.63#ibcon#about to read 6, iclass 6, count 2 2006.225.07:52:00.63#ibcon#read 6, iclass 6, count 2 2006.225.07:52:00.63#ibcon#end of sib2, iclass 6, count 2 2006.225.07:52:00.63#ibcon#*mode == 0, iclass 6, count 2 2006.225.07:52:00.63#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.225.07:52:00.63#ibcon#[27=AT01-04\r\n] 2006.225.07:52:00.63#ibcon#*before write, iclass 6, count 2 2006.225.07:52:00.63#ibcon#enter sib2, iclass 6, count 2 2006.225.07:52:00.63#ibcon#flushed, iclass 6, count 2 2006.225.07:52:00.63#ibcon#about to write, iclass 6, count 2 2006.225.07:52:00.63#ibcon#wrote, iclass 6, count 2 2006.225.07:52:00.63#ibcon#about to read 3, iclass 6, count 2 2006.225.07:52:00.66#ibcon#read 3, iclass 6, count 2 2006.225.07:52:00.66#ibcon#about to read 4, iclass 6, count 2 2006.225.07:52:00.66#ibcon#read 4, iclass 6, count 2 2006.225.07:52:00.66#ibcon#about to read 5, iclass 6, count 2 2006.225.07:52:00.66#ibcon#read 5, iclass 6, count 2 2006.225.07:52:00.66#ibcon#about to read 6, iclass 6, count 2 2006.225.07:52:00.66#ibcon#read 6, iclass 6, count 2 2006.225.07:52:00.66#ibcon#end of sib2, iclass 6, count 2 2006.225.07:52:00.66#ibcon#*after write, iclass 6, count 2 2006.225.07:52:00.66#ibcon#*before return 0, iclass 6, count 2 2006.225.07:52:00.66#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:52:00.66#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.225.07:52:00.66#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.225.07:52:00.66#ibcon#ireg 7 cls_cnt 0 2006.225.07:52:00.66#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:52:00.78#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:52:00.78#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:52:00.78#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:52:00.78#ibcon#first serial, iclass 6, count 0 2006.225.07:52:00.78#ibcon#enter sib2, iclass 6, count 0 2006.225.07:52:00.78#ibcon#flushed, iclass 6, count 0 2006.225.07:52:00.78#ibcon#about to write, iclass 6, count 0 2006.225.07:52:00.78#ibcon#wrote, iclass 6, count 0 2006.225.07:52:00.78#ibcon#about to read 3, iclass 6, count 0 2006.225.07:52:00.80#ibcon#read 3, iclass 6, count 0 2006.225.07:52:00.80#ibcon#about to read 4, iclass 6, count 0 2006.225.07:52:00.80#ibcon#read 4, iclass 6, count 0 2006.225.07:52:00.80#ibcon#about to read 5, iclass 6, count 0 2006.225.07:52:00.80#ibcon#read 5, iclass 6, count 0 2006.225.07:52:00.80#ibcon#about to read 6, iclass 6, count 0 2006.225.07:52:00.80#ibcon#read 6, iclass 6, count 0 2006.225.07:52:00.80#ibcon#end of sib2, iclass 6, count 0 2006.225.07:52:00.80#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:52:00.80#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:52:00.80#ibcon#[27=USB\r\n] 2006.225.07:52:00.80#ibcon#*before write, iclass 6, count 0 2006.225.07:52:00.80#ibcon#enter sib2, iclass 6, count 0 2006.225.07:52:00.80#ibcon#flushed, iclass 6, count 0 2006.225.07:52:00.80#ibcon#about to write, iclass 6, count 0 2006.225.07:52:00.80#ibcon#wrote, iclass 6, count 0 2006.225.07:52:00.80#ibcon#about to read 3, iclass 6, count 0 2006.225.07:52:00.83#ibcon#read 3, iclass 6, count 0 2006.225.07:52:00.83#ibcon#about to read 4, iclass 6, count 0 2006.225.07:52:00.83#ibcon#read 4, iclass 6, count 0 2006.225.07:52:00.83#ibcon#about to read 5, iclass 6, count 0 2006.225.07:52:00.83#ibcon#read 5, iclass 6, count 0 2006.225.07:52:00.83#ibcon#about to read 6, iclass 6, count 0 2006.225.07:52:00.83#ibcon#read 6, iclass 6, count 0 2006.225.07:52:00.83#ibcon#end of sib2, iclass 6, count 0 2006.225.07:52:00.83#ibcon#*after write, iclass 6, count 0 2006.225.07:52:00.83#ibcon#*before return 0, iclass 6, count 0 2006.225.07:52:00.83#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:52:00.83#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.225.07:52:00.83#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:52:00.83#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:52:00.83$vc4f8/vblo=2,640.99 2006.225.07:52:00.83#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.07:52:00.83#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.07:52:00.83#ibcon#ireg 17 cls_cnt 0 2006.225.07:52:00.83#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:52:00.83#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:52:00.83#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:52:00.83#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:52:00.83#ibcon#first serial, iclass 10, count 0 2006.225.07:52:00.83#ibcon#enter sib2, iclass 10, count 0 2006.225.07:52:00.83#ibcon#flushed, iclass 10, count 0 2006.225.07:52:00.83#ibcon#about to write, iclass 10, count 0 2006.225.07:52:00.83#ibcon#wrote, iclass 10, count 0 2006.225.07:52:00.83#ibcon#about to read 3, iclass 10, count 0 2006.225.07:52:00.85#ibcon#read 3, iclass 10, count 0 2006.225.07:52:00.85#ibcon#about to read 4, iclass 10, count 0 2006.225.07:52:00.85#ibcon#read 4, iclass 10, count 0 2006.225.07:52:00.85#ibcon#about to read 5, iclass 10, count 0 2006.225.07:52:00.85#ibcon#read 5, iclass 10, count 0 2006.225.07:52:00.85#ibcon#about to read 6, iclass 10, count 0 2006.225.07:52:00.85#ibcon#read 6, iclass 10, count 0 2006.225.07:52:00.85#ibcon#end of sib2, iclass 10, count 0 2006.225.07:52:00.85#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:52:00.85#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:52:00.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:52:00.85#ibcon#*before write, iclass 10, count 0 2006.225.07:52:00.85#ibcon#enter sib2, iclass 10, count 0 2006.225.07:52:00.85#ibcon#flushed, iclass 10, count 0 2006.225.07:52:00.85#ibcon#about to write, iclass 10, count 0 2006.225.07:52:00.85#ibcon#wrote, iclass 10, count 0 2006.225.07:52:00.85#ibcon#about to read 3, iclass 10, count 0 2006.225.07:52:00.89#ibcon#read 3, iclass 10, count 0 2006.225.07:52:00.89#ibcon#about to read 4, iclass 10, count 0 2006.225.07:52:00.89#ibcon#read 4, iclass 10, count 0 2006.225.07:52:00.89#ibcon#about to read 5, iclass 10, count 0 2006.225.07:52:00.89#ibcon#read 5, iclass 10, count 0 2006.225.07:52:00.89#ibcon#about to read 6, iclass 10, count 0 2006.225.07:52:00.89#ibcon#read 6, iclass 10, count 0 2006.225.07:52:00.89#ibcon#end of sib2, iclass 10, count 0 2006.225.07:52:00.89#ibcon#*after write, iclass 10, count 0 2006.225.07:52:00.89#ibcon#*before return 0, iclass 10, count 0 2006.225.07:52:00.89#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:52:00.89#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.07:52:00.89#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:52:00.89#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:52:00.89$vc4f8/vb=2,4 2006.225.07:52:00.89#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.07:52:00.89#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.07:52:00.89#ibcon#ireg 11 cls_cnt 2 2006.225.07:52:00.89#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:52:00.95#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:52:00.95#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:52:00.95#ibcon#enter wrdev, iclass 12, count 2 2006.225.07:52:00.95#ibcon#first serial, iclass 12, count 2 2006.225.07:52:00.95#ibcon#enter sib2, iclass 12, count 2 2006.225.07:52:00.95#ibcon#flushed, iclass 12, count 2 2006.225.07:52:00.95#ibcon#about to write, iclass 12, count 2 2006.225.07:52:00.95#ibcon#wrote, iclass 12, count 2 2006.225.07:52:00.95#ibcon#about to read 3, iclass 12, count 2 2006.225.07:52:00.97#ibcon#read 3, iclass 12, count 2 2006.225.07:52:00.97#ibcon#about to read 4, iclass 12, count 2 2006.225.07:52:00.97#ibcon#read 4, iclass 12, count 2 2006.225.07:52:00.97#ibcon#about to read 5, iclass 12, count 2 2006.225.07:52:00.97#ibcon#read 5, iclass 12, count 2 2006.225.07:52:00.97#ibcon#about to read 6, iclass 12, count 2 2006.225.07:52:00.97#ibcon#read 6, iclass 12, count 2 2006.225.07:52:00.97#ibcon#end of sib2, iclass 12, count 2 2006.225.07:52:00.97#ibcon#*mode == 0, iclass 12, count 2 2006.225.07:52:00.97#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.07:52:00.97#ibcon#[27=AT02-04\r\n] 2006.225.07:52:00.97#ibcon#*before write, iclass 12, count 2 2006.225.07:52:00.97#ibcon#enter sib2, iclass 12, count 2 2006.225.07:52:00.97#ibcon#flushed, iclass 12, count 2 2006.225.07:52:00.97#ibcon#about to write, iclass 12, count 2 2006.225.07:52:00.97#ibcon#wrote, iclass 12, count 2 2006.225.07:52:00.97#ibcon#about to read 3, iclass 12, count 2 2006.225.07:52:01.00#ibcon#read 3, iclass 12, count 2 2006.225.07:52:01.00#ibcon#about to read 4, iclass 12, count 2 2006.225.07:52:01.00#ibcon#read 4, iclass 12, count 2 2006.225.07:52:01.00#ibcon#about to read 5, iclass 12, count 2 2006.225.07:52:01.00#ibcon#read 5, iclass 12, count 2 2006.225.07:52:01.00#ibcon#about to read 6, iclass 12, count 2 2006.225.07:52:01.00#ibcon#read 6, iclass 12, count 2 2006.225.07:52:01.00#ibcon#end of sib2, iclass 12, count 2 2006.225.07:52:01.00#ibcon#*after write, iclass 12, count 2 2006.225.07:52:01.00#ibcon#*before return 0, iclass 12, count 2 2006.225.07:52:01.00#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:52:01.00#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.07:52:01.00#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.07:52:01.00#ibcon#ireg 7 cls_cnt 0 2006.225.07:52:01.00#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:52:01.12#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:52:01.12#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:52:01.12#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:52:01.12#ibcon#first serial, iclass 12, count 0 2006.225.07:52:01.12#ibcon#enter sib2, iclass 12, count 0 2006.225.07:52:01.12#ibcon#flushed, iclass 12, count 0 2006.225.07:52:01.12#ibcon#about to write, iclass 12, count 0 2006.225.07:52:01.12#ibcon#wrote, iclass 12, count 0 2006.225.07:52:01.12#ibcon#about to read 3, iclass 12, count 0 2006.225.07:52:01.14#ibcon#read 3, iclass 12, count 0 2006.225.07:52:01.14#ibcon#about to read 4, iclass 12, count 0 2006.225.07:52:01.14#ibcon#read 4, iclass 12, count 0 2006.225.07:52:01.14#ibcon#about to read 5, iclass 12, count 0 2006.225.07:52:01.14#ibcon#read 5, iclass 12, count 0 2006.225.07:52:01.14#ibcon#about to read 6, iclass 12, count 0 2006.225.07:52:01.14#ibcon#read 6, iclass 12, count 0 2006.225.07:52:01.14#ibcon#end of sib2, iclass 12, count 0 2006.225.07:52:01.14#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:52:01.14#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:52:01.14#ibcon#[27=USB\r\n] 2006.225.07:52:01.14#ibcon#*before write, iclass 12, count 0 2006.225.07:52:01.14#ibcon#enter sib2, iclass 12, count 0 2006.225.07:52:01.14#ibcon#flushed, iclass 12, count 0 2006.225.07:52:01.14#ibcon#about to write, iclass 12, count 0 2006.225.07:52:01.14#ibcon#wrote, iclass 12, count 0 2006.225.07:52:01.14#ibcon#about to read 3, iclass 12, count 0 2006.225.07:52:01.17#ibcon#read 3, iclass 12, count 0 2006.225.07:52:01.17#ibcon#about to read 4, iclass 12, count 0 2006.225.07:52:01.17#ibcon#read 4, iclass 12, count 0 2006.225.07:52:01.17#ibcon#about to read 5, iclass 12, count 0 2006.225.07:52:01.17#ibcon#read 5, iclass 12, count 0 2006.225.07:52:01.17#ibcon#about to read 6, iclass 12, count 0 2006.225.07:52:01.17#ibcon#read 6, iclass 12, count 0 2006.225.07:52:01.17#ibcon#end of sib2, iclass 12, count 0 2006.225.07:52:01.17#ibcon#*after write, iclass 12, count 0 2006.225.07:52:01.17#ibcon#*before return 0, iclass 12, count 0 2006.225.07:52:01.17#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:52:01.17#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.07:52:01.17#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:52:01.17#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:52:01.17$vc4f8/vblo=3,656.99 2006.225.07:52:01.17#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.07:52:01.17#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.07:52:01.17#ibcon#ireg 17 cls_cnt 0 2006.225.07:52:01.17#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:52:01.17#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:52:01.17#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:52:01.17#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:52:01.17#ibcon#first serial, iclass 14, count 0 2006.225.07:52:01.17#ibcon#enter sib2, iclass 14, count 0 2006.225.07:52:01.17#ibcon#flushed, iclass 14, count 0 2006.225.07:52:01.17#ibcon#about to write, iclass 14, count 0 2006.225.07:52:01.17#ibcon#wrote, iclass 14, count 0 2006.225.07:52:01.17#ibcon#about to read 3, iclass 14, count 0 2006.225.07:52:01.19#ibcon#read 3, iclass 14, count 0 2006.225.07:52:01.19#ibcon#about to read 4, iclass 14, count 0 2006.225.07:52:01.19#ibcon#read 4, iclass 14, count 0 2006.225.07:52:01.19#ibcon#about to read 5, iclass 14, count 0 2006.225.07:52:01.19#ibcon#read 5, iclass 14, count 0 2006.225.07:52:01.19#ibcon#about to read 6, iclass 14, count 0 2006.225.07:52:01.19#ibcon#read 6, iclass 14, count 0 2006.225.07:52:01.19#ibcon#end of sib2, iclass 14, count 0 2006.225.07:52:01.19#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:52:01.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:52:01.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:52:01.19#ibcon#*before write, iclass 14, count 0 2006.225.07:52:01.19#ibcon#enter sib2, iclass 14, count 0 2006.225.07:52:01.19#ibcon#flushed, iclass 14, count 0 2006.225.07:52:01.19#ibcon#about to write, iclass 14, count 0 2006.225.07:52:01.19#ibcon#wrote, iclass 14, count 0 2006.225.07:52:01.19#ibcon#about to read 3, iclass 14, count 0 2006.225.07:52:01.23#ibcon#read 3, iclass 14, count 0 2006.225.07:52:01.23#ibcon#about to read 4, iclass 14, count 0 2006.225.07:52:01.23#ibcon#read 4, iclass 14, count 0 2006.225.07:52:01.23#ibcon#about to read 5, iclass 14, count 0 2006.225.07:52:01.23#ibcon#read 5, iclass 14, count 0 2006.225.07:52:01.23#ibcon#about to read 6, iclass 14, count 0 2006.225.07:52:01.23#ibcon#read 6, iclass 14, count 0 2006.225.07:52:01.23#ibcon#end of sib2, iclass 14, count 0 2006.225.07:52:01.23#ibcon#*after write, iclass 14, count 0 2006.225.07:52:01.23#ibcon#*before return 0, iclass 14, count 0 2006.225.07:52:01.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:52:01.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:52:01.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:52:01.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:52:01.23$vc4f8/vb=3,4 2006.225.07:52:01.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.07:52:01.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.07:52:01.23#ibcon#ireg 11 cls_cnt 2 2006.225.07:52:01.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:52:01.29#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:52:01.29#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:52:01.29#ibcon#enter wrdev, iclass 16, count 2 2006.225.07:52:01.29#ibcon#first serial, iclass 16, count 2 2006.225.07:52:01.29#ibcon#enter sib2, iclass 16, count 2 2006.225.07:52:01.29#ibcon#flushed, iclass 16, count 2 2006.225.07:52:01.29#ibcon#about to write, iclass 16, count 2 2006.225.07:52:01.29#ibcon#wrote, iclass 16, count 2 2006.225.07:52:01.29#ibcon#about to read 3, iclass 16, count 2 2006.225.07:52:01.31#ibcon#read 3, iclass 16, count 2 2006.225.07:52:01.31#ibcon#about to read 4, iclass 16, count 2 2006.225.07:52:01.31#ibcon#read 4, iclass 16, count 2 2006.225.07:52:01.31#ibcon#about to read 5, iclass 16, count 2 2006.225.07:52:01.31#ibcon#read 5, iclass 16, count 2 2006.225.07:52:01.31#ibcon#about to read 6, iclass 16, count 2 2006.225.07:52:01.31#ibcon#read 6, iclass 16, count 2 2006.225.07:52:01.31#ibcon#end of sib2, iclass 16, count 2 2006.225.07:52:01.31#ibcon#*mode == 0, iclass 16, count 2 2006.225.07:52:01.31#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.07:52:01.31#ibcon#[27=AT03-04\r\n] 2006.225.07:52:01.31#ibcon#*before write, iclass 16, count 2 2006.225.07:52:01.31#ibcon#enter sib2, iclass 16, count 2 2006.225.07:52:01.31#ibcon#flushed, iclass 16, count 2 2006.225.07:52:01.31#ibcon#about to write, iclass 16, count 2 2006.225.07:52:01.31#ibcon#wrote, iclass 16, count 2 2006.225.07:52:01.31#ibcon#about to read 3, iclass 16, count 2 2006.225.07:52:01.34#ibcon#read 3, iclass 16, count 2 2006.225.07:52:01.34#ibcon#about to read 4, iclass 16, count 2 2006.225.07:52:01.34#ibcon#read 4, iclass 16, count 2 2006.225.07:52:01.34#ibcon#about to read 5, iclass 16, count 2 2006.225.07:52:01.34#ibcon#read 5, iclass 16, count 2 2006.225.07:52:01.34#ibcon#about to read 6, iclass 16, count 2 2006.225.07:52:01.34#ibcon#read 6, iclass 16, count 2 2006.225.07:52:01.34#ibcon#end of sib2, iclass 16, count 2 2006.225.07:52:01.34#ibcon#*after write, iclass 16, count 2 2006.225.07:52:01.34#ibcon#*before return 0, iclass 16, count 2 2006.225.07:52:01.34#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:52:01.34#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.07:52:01.34#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.07:52:01.34#ibcon#ireg 7 cls_cnt 0 2006.225.07:52:01.34#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:52:01.46#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:52:01.46#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:52:01.46#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:52:01.46#ibcon#first serial, iclass 16, count 0 2006.225.07:52:01.46#ibcon#enter sib2, iclass 16, count 0 2006.225.07:52:01.46#ibcon#flushed, iclass 16, count 0 2006.225.07:52:01.46#ibcon#about to write, iclass 16, count 0 2006.225.07:52:01.46#ibcon#wrote, iclass 16, count 0 2006.225.07:52:01.46#ibcon#about to read 3, iclass 16, count 0 2006.225.07:52:01.48#ibcon#read 3, iclass 16, count 0 2006.225.07:52:01.48#ibcon#about to read 4, iclass 16, count 0 2006.225.07:52:01.48#ibcon#read 4, iclass 16, count 0 2006.225.07:52:01.48#ibcon#about to read 5, iclass 16, count 0 2006.225.07:52:01.48#ibcon#read 5, iclass 16, count 0 2006.225.07:52:01.48#ibcon#about to read 6, iclass 16, count 0 2006.225.07:52:01.48#ibcon#read 6, iclass 16, count 0 2006.225.07:52:01.48#ibcon#end of sib2, iclass 16, count 0 2006.225.07:52:01.48#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:52:01.48#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:52:01.48#ibcon#[27=USB\r\n] 2006.225.07:52:01.48#ibcon#*before write, iclass 16, count 0 2006.225.07:52:01.48#ibcon#enter sib2, iclass 16, count 0 2006.225.07:52:01.48#ibcon#flushed, iclass 16, count 0 2006.225.07:52:01.48#ibcon#about to write, iclass 16, count 0 2006.225.07:52:01.48#ibcon#wrote, iclass 16, count 0 2006.225.07:52:01.48#ibcon#about to read 3, iclass 16, count 0 2006.225.07:52:01.51#ibcon#read 3, iclass 16, count 0 2006.225.07:52:01.51#ibcon#about to read 4, iclass 16, count 0 2006.225.07:52:01.51#ibcon#read 4, iclass 16, count 0 2006.225.07:52:01.51#ibcon#about to read 5, iclass 16, count 0 2006.225.07:52:01.51#ibcon#read 5, iclass 16, count 0 2006.225.07:52:01.51#ibcon#about to read 6, iclass 16, count 0 2006.225.07:52:01.51#ibcon#read 6, iclass 16, count 0 2006.225.07:52:01.51#ibcon#end of sib2, iclass 16, count 0 2006.225.07:52:01.51#ibcon#*after write, iclass 16, count 0 2006.225.07:52:01.51#ibcon#*before return 0, iclass 16, count 0 2006.225.07:52:01.51#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:52:01.51#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.07:52:01.51#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:52:01.51#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:52:01.51$vc4f8/vblo=4,712.99 2006.225.07:52:01.51#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.07:52:01.51#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.07:52:01.51#ibcon#ireg 17 cls_cnt 0 2006.225.07:52:01.51#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:52:01.51#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:52:01.51#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:52:01.51#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:52:01.51#ibcon#first serial, iclass 18, count 0 2006.225.07:52:01.51#ibcon#enter sib2, iclass 18, count 0 2006.225.07:52:01.51#ibcon#flushed, iclass 18, count 0 2006.225.07:52:01.51#ibcon#about to write, iclass 18, count 0 2006.225.07:52:01.51#ibcon#wrote, iclass 18, count 0 2006.225.07:52:01.51#ibcon#about to read 3, iclass 18, count 0 2006.225.07:52:01.53#ibcon#read 3, iclass 18, count 0 2006.225.07:52:01.53#ibcon#about to read 4, iclass 18, count 0 2006.225.07:52:01.53#ibcon#read 4, iclass 18, count 0 2006.225.07:52:01.54#ibcon#about to read 5, iclass 18, count 0 2006.225.07:52:01.54#ibcon#read 5, iclass 18, count 0 2006.225.07:52:01.54#ibcon#about to read 6, iclass 18, count 0 2006.225.07:52:01.54#ibcon#read 6, iclass 18, count 0 2006.225.07:52:01.54#ibcon#end of sib2, iclass 18, count 0 2006.225.07:52:01.54#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:52:01.54#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:52:01.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:52:01.54#ibcon#*before write, iclass 18, count 0 2006.225.07:52:01.54#ibcon#enter sib2, iclass 18, count 0 2006.225.07:52:01.54#ibcon#flushed, iclass 18, count 0 2006.225.07:52:01.54#ibcon#about to write, iclass 18, count 0 2006.225.07:52:01.54#ibcon#wrote, iclass 18, count 0 2006.225.07:52:01.54#ibcon#about to read 3, iclass 18, count 0 2006.225.07:52:01.58#ibcon#read 3, iclass 18, count 0 2006.225.07:52:01.58#ibcon#about to read 4, iclass 18, count 0 2006.225.07:52:01.58#ibcon#read 4, iclass 18, count 0 2006.225.07:52:01.58#ibcon#about to read 5, iclass 18, count 0 2006.225.07:52:01.58#ibcon#read 5, iclass 18, count 0 2006.225.07:52:01.58#ibcon#about to read 6, iclass 18, count 0 2006.225.07:52:01.58#ibcon#read 6, iclass 18, count 0 2006.225.07:52:01.58#ibcon#end of sib2, iclass 18, count 0 2006.225.07:52:01.58#ibcon#*after write, iclass 18, count 0 2006.225.07:52:01.58#ibcon#*before return 0, iclass 18, count 0 2006.225.07:52:01.58#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:52:01.58#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.07:52:01.58#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:52:01.58#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:52:01.58$vc4f8/vb=4,4 2006.225.07:52:01.58#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.07:52:01.58#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.07:52:01.58#ibcon#ireg 11 cls_cnt 2 2006.225.07:52:01.58#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:52:01.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:52:01.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:52:01.63#ibcon#enter wrdev, iclass 20, count 2 2006.225.07:52:01.63#ibcon#first serial, iclass 20, count 2 2006.225.07:52:01.63#ibcon#enter sib2, iclass 20, count 2 2006.225.07:52:01.63#ibcon#flushed, iclass 20, count 2 2006.225.07:52:01.63#ibcon#about to write, iclass 20, count 2 2006.225.07:52:01.63#ibcon#wrote, iclass 20, count 2 2006.225.07:52:01.63#ibcon#about to read 3, iclass 20, count 2 2006.225.07:52:01.65#ibcon#read 3, iclass 20, count 2 2006.225.07:52:01.65#ibcon#about to read 4, iclass 20, count 2 2006.225.07:52:01.65#ibcon#read 4, iclass 20, count 2 2006.225.07:52:01.65#ibcon#about to read 5, iclass 20, count 2 2006.225.07:52:01.65#ibcon#read 5, iclass 20, count 2 2006.225.07:52:01.65#ibcon#about to read 6, iclass 20, count 2 2006.225.07:52:01.65#ibcon#read 6, iclass 20, count 2 2006.225.07:52:01.65#ibcon#end of sib2, iclass 20, count 2 2006.225.07:52:01.65#ibcon#*mode == 0, iclass 20, count 2 2006.225.07:52:01.65#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.07:52:01.65#ibcon#[27=AT04-04\r\n] 2006.225.07:52:01.65#ibcon#*before write, iclass 20, count 2 2006.225.07:52:01.65#ibcon#enter sib2, iclass 20, count 2 2006.225.07:52:01.65#ibcon#flushed, iclass 20, count 2 2006.225.07:52:01.65#ibcon#about to write, iclass 20, count 2 2006.225.07:52:01.65#ibcon#wrote, iclass 20, count 2 2006.225.07:52:01.65#ibcon#about to read 3, iclass 20, count 2 2006.225.07:52:01.68#ibcon#read 3, iclass 20, count 2 2006.225.07:52:01.68#ibcon#about to read 4, iclass 20, count 2 2006.225.07:52:01.68#ibcon#read 4, iclass 20, count 2 2006.225.07:52:01.68#ibcon#about to read 5, iclass 20, count 2 2006.225.07:52:01.68#ibcon#read 5, iclass 20, count 2 2006.225.07:52:01.68#ibcon#about to read 6, iclass 20, count 2 2006.225.07:52:01.68#ibcon#read 6, iclass 20, count 2 2006.225.07:52:01.68#ibcon#end of sib2, iclass 20, count 2 2006.225.07:52:01.68#ibcon#*after write, iclass 20, count 2 2006.225.07:52:01.68#ibcon#*before return 0, iclass 20, count 2 2006.225.07:52:01.68#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:52:01.68#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.07:52:01.68#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.07:52:01.68#ibcon#ireg 7 cls_cnt 0 2006.225.07:52:01.68#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:52:01.80#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:52:01.80#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:52:01.80#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:52:01.80#ibcon#first serial, iclass 20, count 0 2006.225.07:52:01.80#ibcon#enter sib2, iclass 20, count 0 2006.225.07:52:01.80#ibcon#flushed, iclass 20, count 0 2006.225.07:52:01.80#ibcon#about to write, iclass 20, count 0 2006.225.07:52:01.80#ibcon#wrote, iclass 20, count 0 2006.225.07:52:01.80#ibcon#about to read 3, iclass 20, count 0 2006.225.07:52:01.82#ibcon#read 3, iclass 20, count 0 2006.225.07:52:01.82#ibcon#about to read 4, iclass 20, count 0 2006.225.07:52:01.82#ibcon#read 4, iclass 20, count 0 2006.225.07:52:01.82#ibcon#about to read 5, iclass 20, count 0 2006.225.07:52:01.82#ibcon#read 5, iclass 20, count 0 2006.225.07:52:01.82#ibcon#about to read 6, iclass 20, count 0 2006.225.07:52:01.82#ibcon#read 6, iclass 20, count 0 2006.225.07:52:01.82#ibcon#end of sib2, iclass 20, count 0 2006.225.07:52:01.82#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:52:01.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:52:01.82#ibcon#[27=USB\r\n] 2006.225.07:52:01.82#ibcon#*before write, iclass 20, count 0 2006.225.07:52:01.82#ibcon#enter sib2, iclass 20, count 0 2006.225.07:52:01.82#ibcon#flushed, iclass 20, count 0 2006.225.07:52:01.82#ibcon#about to write, iclass 20, count 0 2006.225.07:52:01.82#ibcon#wrote, iclass 20, count 0 2006.225.07:52:01.82#ibcon#about to read 3, iclass 20, count 0 2006.225.07:52:01.85#ibcon#read 3, iclass 20, count 0 2006.225.07:52:01.85#ibcon#about to read 4, iclass 20, count 0 2006.225.07:52:01.85#ibcon#read 4, iclass 20, count 0 2006.225.07:52:01.85#ibcon#about to read 5, iclass 20, count 0 2006.225.07:52:01.85#ibcon#read 5, iclass 20, count 0 2006.225.07:52:01.85#ibcon#about to read 6, iclass 20, count 0 2006.225.07:52:01.85#ibcon#read 6, iclass 20, count 0 2006.225.07:52:01.85#ibcon#end of sib2, iclass 20, count 0 2006.225.07:52:01.85#ibcon#*after write, iclass 20, count 0 2006.225.07:52:01.85#ibcon#*before return 0, iclass 20, count 0 2006.225.07:52:01.85#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:52:01.85#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.07:52:01.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:52:01.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:52:01.85$vc4f8/vblo=5,744.99 2006.225.07:52:01.85#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.07:52:01.85#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.07:52:01.85#ibcon#ireg 17 cls_cnt 0 2006.225.07:52:01.85#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:52:01.85#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:52:01.85#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:52:01.85#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:52:01.85#ibcon#first serial, iclass 22, count 0 2006.225.07:52:01.85#ibcon#enter sib2, iclass 22, count 0 2006.225.07:52:01.85#ibcon#flushed, iclass 22, count 0 2006.225.07:52:01.85#ibcon#about to write, iclass 22, count 0 2006.225.07:52:01.85#ibcon#wrote, iclass 22, count 0 2006.225.07:52:01.85#ibcon#about to read 3, iclass 22, count 0 2006.225.07:52:01.87#ibcon#read 3, iclass 22, count 0 2006.225.07:52:01.87#ibcon#about to read 4, iclass 22, count 0 2006.225.07:52:01.87#ibcon#read 4, iclass 22, count 0 2006.225.07:52:01.87#ibcon#about to read 5, iclass 22, count 0 2006.225.07:52:01.87#ibcon#read 5, iclass 22, count 0 2006.225.07:52:01.87#ibcon#about to read 6, iclass 22, count 0 2006.225.07:52:01.87#ibcon#read 6, iclass 22, count 0 2006.225.07:52:01.87#ibcon#end of sib2, iclass 22, count 0 2006.225.07:52:01.87#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:52:01.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:52:01.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:52:01.87#ibcon#*before write, iclass 22, count 0 2006.225.07:52:01.87#ibcon#enter sib2, iclass 22, count 0 2006.225.07:52:01.87#ibcon#flushed, iclass 22, count 0 2006.225.07:52:01.87#ibcon#about to write, iclass 22, count 0 2006.225.07:52:01.87#ibcon#wrote, iclass 22, count 0 2006.225.07:52:01.87#ibcon#about to read 3, iclass 22, count 0 2006.225.07:52:01.91#ibcon#read 3, iclass 22, count 0 2006.225.07:52:01.91#ibcon#about to read 4, iclass 22, count 0 2006.225.07:52:01.91#ibcon#read 4, iclass 22, count 0 2006.225.07:52:01.91#ibcon#about to read 5, iclass 22, count 0 2006.225.07:52:01.91#ibcon#read 5, iclass 22, count 0 2006.225.07:52:01.91#ibcon#about to read 6, iclass 22, count 0 2006.225.07:52:01.91#ibcon#read 6, iclass 22, count 0 2006.225.07:52:01.91#ibcon#end of sib2, iclass 22, count 0 2006.225.07:52:01.91#ibcon#*after write, iclass 22, count 0 2006.225.07:52:01.91#ibcon#*before return 0, iclass 22, count 0 2006.225.07:52:01.91#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:52:01.91#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.07:52:01.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:52:01.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:52:01.91$vc4f8/vb=5,4 2006.225.07:52:01.91#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.07:52:01.91#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.07:52:01.91#ibcon#ireg 11 cls_cnt 2 2006.225.07:52:01.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:52:01.97#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:52:01.97#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:52:01.97#ibcon#enter wrdev, iclass 24, count 2 2006.225.07:52:01.97#ibcon#first serial, iclass 24, count 2 2006.225.07:52:01.97#ibcon#enter sib2, iclass 24, count 2 2006.225.07:52:01.97#ibcon#flushed, iclass 24, count 2 2006.225.07:52:01.97#ibcon#about to write, iclass 24, count 2 2006.225.07:52:01.97#ibcon#wrote, iclass 24, count 2 2006.225.07:52:01.97#ibcon#about to read 3, iclass 24, count 2 2006.225.07:52:01.99#ibcon#read 3, iclass 24, count 2 2006.225.07:52:01.99#ibcon#about to read 4, iclass 24, count 2 2006.225.07:52:01.99#ibcon#read 4, iclass 24, count 2 2006.225.07:52:01.99#ibcon#about to read 5, iclass 24, count 2 2006.225.07:52:01.99#ibcon#read 5, iclass 24, count 2 2006.225.07:52:01.99#ibcon#about to read 6, iclass 24, count 2 2006.225.07:52:01.99#ibcon#read 6, iclass 24, count 2 2006.225.07:52:01.99#ibcon#end of sib2, iclass 24, count 2 2006.225.07:52:01.99#ibcon#*mode == 0, iclass 24, count 2 2006.225.07:52:01.99#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.07:52:01.99#ibcon#[27=AT05-04\r\n] 2006.225.07:52:01.99#ibcon#*before write, iclass 24, count 2 2006.225.07:52:01.99#ibcon#enter sib2, iclass 24, count 2 2006.225.07:52:01.99#ibcon#flushed, iclass 24, count 2 2006.225.07:52:01.99#ibcon#about to write, iclass 24, count 2 2006.225.07:52:01.99#ibcon#wrote, iclass 24, count 2 2006.225.07:52:01.99#ibcon#about to read 3, iclass 24, count 2 2006.225.07:52:02.02#ibcon#read 3, iclass 24, count 2 2006.225.07:52:02.02#ibcon#about to read 4, iclass 24, count 2 2006.225.07:52:02.02#ibcon#read 4, iclass 24, count 2 2006.225.07:52:02.02#ibcon#about to read 5, iclass 24, count 2 2006.225.07:52:02.02#ibcon#read 5, iclass 24, count 2 2006.225.07:52:02.02#ibcon#about to read 6, iclass 24, count 2 2006.225.07:52:02.02#ibcon#read 6, iclass 24, count 2 2006.225.07:52:02.02#ibcon#end of sib2, iclass 24, count 2 2006.225.07:52:02.02#ibcon#*after write, iclass 24, count 2 2006.225.07:52:02.02#ibcon#*before return 0, iclass 24, count 2 2006.225.07:52:02.02#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:52:02.02#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.07:52:02.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.07:52:02.02#ibcon#ireg 7 cls_cnt 0 2006.225.07:52:02.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:52:02.14#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:52:02.14#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:52:02.14#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:52:02.14#ibcon#first serial, iclass 24, count 0 2006.225.07:52:02.14#ibcon#enter sib2, iclass 24, count 0 2006.225.07:52:02.14#ibcon#flushed, iclass 24, count 0 2006.225.07:52:02.14#ibcon#about to write, iclass 24, count 0 2006.225.07:52:02.14#ibcon#wrote, iclass 24, count 0 2006.225.07:52:02.14#ibcon#about to read 3, iclass 24, count 0 2006.225.07:52:02.16#ibcon#read 3, iclass 24, count 0 2006.225.07:52:02.16#ibcon#about to read 4, iclass 24, count 0 2006.225.07:52:02.16#ibcon#read 4, iclass 24, count 0 2006.225.07:52:02.16#ibcon#about to read 5, iclass 24, count 0 2006.225.07:52:02.16#ibcon#read 5, iclass 24, count 0 2006.225.07:52:02.16#ibcon#about to read 6, iclass 24, count 0 2006.225.07:52:02.16#ibcon#read 6, iclass 24, count 0 2006.225.07:52:02.16#ibcon#end of sib2, iclass 24, count 0 2006.225.07:52:02.16#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:52:02.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:52:02.16#ibcon#[27=USB\r\n] 2006.225.07:52:02.16#ibcon#*before write, iclass 24, count 0 2006.225.07:52:02.16#ibcon#enter sib2, iclass 24, count 0 2006.225.07:52:02.16#ibcon#flushed, iclass 24, count 0 2006.225.07:52:02.16#ibcon#about to write, iclass 24, count 0 2006.225.07:52:02.16#ibcon#wrote, iclass 24, count 0 2006.225.07:52:02.16#ibcon#about to read 3, iclass 24, count 0 2006.225.07:52:02.19#ibcon#read 3, iclass 24, count 0 2006.225.07:52:02.19#ibcon#about to read 4, iclass 24, count 0 2006.225.07:52:02.19#ibcon#read 4, iclass 24, count 0 2006.225.07:52:02.19#ibcon#about to read 5, iclass 24, count 0 2006.225.07:52:02.19#ibcon#read 5, iclass 24, count 0 2006.225.07:52:02.19#ibcon#about to read 6, iclass 24, count 0 2006.225.07:52:02.19#ibcon#read 6, iclass 24, count 0 2006.225.07:52:02.19#ibcon#end of sib2, iclass 24, count 0 2006.225.07:52:02.19#ibcon#*after write, iclass 24, count 0 2006.225.07:52:02.19#ibcon#*before return 0, iclass 24, count 0 2006.225.07:52:02.19#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:52:02.19#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.07:52:02.19#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:52:02.19#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:52:02.19$vc4f8/vblo=6,752.99 2006.225.07:52:02.19#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.07:52:02.19#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.07:52:02.19#ibcon#ireg 17 cls_cnt 0 2006.225.07:52:02.19#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:52:02.19#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:52:02.19#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:52:02.19#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:52:02.19#ibcon#first serial, iclass 26, count 0 2006.225.07:52:02.19#ibcon#enter sib2, iclass 26, count 0 2006.225.07:52:02.19#ibcon#flushed, iclass 26, count 0 2006.225.07:52:02.19#ibcon#about to write, iclass 26, count 0 2006.225.07:52:02.19#ibcon#wrote, iclass 26, count 0 2006.225.07:52:02.19#ibcon#about to read 3, iclass 26, count 0 2006.225.07:52:02.21#ibcon#read 3, iclass 26, count 0 2006.225.07:52:02.21#ibcon#about to read 4, iclass 26, count 0 2006.225.07:52:02.21#ibcon#read 4, iclass 26, count 0 2006.225.07:52:02.21#ibcon#about to read 5, iclass 26, count 0 2006.225.07:52:02.21#ibcon#read 5, iclass 26, count 0 2006.225.07:52:02.21#ibcon#about to read 6, iclass 26, count 0 2006.225.07:52:02.21#ibcon#read 6, iclass 26, count 0 2006.225.07:52:02.21#ibcon#end of sib2, iclass 26, count 0 2006.225.07:52:02.21#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:52:02.21#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:52:02.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:52:02.21#ibcon#*before write, iclass 26, count 0 2006.225.07:52:02.21#ibcon#enter sib2, iclass 26, count 0 2006.225.07:52:02.21#ibcon#flushed, iclass 26, count 0 2006.225.07:52:02.21#ibcon#about to write, iclass 26, count 0 2006.225.07:52:02.21#ibcon#wrote, iclass 26, count 0 2006.225.07:52:02.21#ibcon#about to read 3, iclass 26, count 0 2006.225.07:52:02.25#ibcon#read 3, iclass 26, count 0 2006.225.07:52:02.25#ibcon#about to read 4, iclass 26, count 0 2006.225.07:52:02.25#ibcon#read 4, iclass 26, count 0 2006.225.07:52:02.25#ibcon#about to read 5, iclass 26, count 0 2006.225.07:52:02.25#ibcon#read 5, iclass 26, count 0 2006.225.07:52:02.25#ibcon#about to read 6, iclass 26, count 0 2006.225.07:52:02.25#ibcon#read 6, iclass 26, count 0 2006.225.07:52:02.25#ibcon#end of sib2, iclass 26, count 0 2006.225.07:52:02.25#ibcon#*after write, iclass 26, count 0 2006.225.07:52:02.25#ibcon#*before return 0, iclass 26, count 0 2006.225.07:52:02.25#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:52:02.25#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.07:52:02.25#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:52:02.25#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:52:02.25$vc4f8/vb=6,4 2006.225.07:52:02.25#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.07:52:02.25#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.07:52:02.25#ibcon#ireg 11 cls_cnt 2 2006.225.07:52:02.25#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:52:02.31#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:52:02.31#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:52:02.31#ibcon#enter wrdev, iclass 28, count 2 2006.225.07:52:02.31#ibcon#first serial, iclass 28, count 2 2006.225.07:52:02.31#ibcon#enter sib2, iclass 28, count 2 2006.225.07:52:02.31#ibcon#flushed, iclass 28, count 2 2006.225.07:52:02.31#ibcon#about to write, iclass 28, count 2 2006.225.07:52:02.31#ibcon#wrote, iclass 28, count 2 2006.225.07:52:02.31#ibcon#about to read 3, iclass 28, count 2 2006.225.07:52:02.33#ibcon#read 3, iclass 28, count 2 2006.225.07:52:02.33#ibcon#about to read 4, iclass 28, count 2 2006.225.07:52:02.33#ibcon#read 4, iclass 28, count 2 2006.225.07:52:02.33#ibcon#about to read 5, iclass 28, count 2 2006.225.07:52:02.33#ibcon#read 5, iclass 28, count 2 2006.225.07:52:02.33#ibcon#about to read 6, iclass 28, count 2 2006.225.07:52:02.33#ibcon#read 6, iclass 28, count 2 2006.225.07:52:02.33#ibcon#end of sib2, iclass 28, count 2 2006.225.07:52:02.33#ibcon#*mode == 0, iclass 28, count 2 2006.225.07:52:02.33#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.07:52:02.33#ibcon#[27=AT06-04\r\n] 2006.225.07:52:02.33#ibcon#*before write, iclass 28, count 2 2006.225.07:52:02.33#ibcon#enter sib2, iclass 28, count 2 2006.225.07:52:02.33#ibcon#flushed, iclass 28, count 2 2006.225.07:52:02.33#ibcon#about to write, iclass 28, count 2 2006.225.07:52:02.33#ibcon#wrote, iclass 28, count 2 2006.225.07:52:02.33#ibcon#about to read 3, iclass 28, count 2 2006.225.07:52:02.36#ibcon#read 3, iclass 28, count 2 2006.225.07:52:02.36#ibcon#about to read 4, iclass 28, count 2 2006.225.07:52:02.36#ibcon#read 4, iclass 28, count 2 2006.225.07:52:02.36#ibcon#about to read 5, iclass 28, count 2 2006.225.07:52:02.36#ibcon#read 5, iclass 28, count 2 2006.225.07:52:02.36#ibcon#about to read 6, iclass 28, count 2 2006.225.07:52:02.36#ibcon#read 6, iclass 28, count 2 2006.225.07:52:02.36#ibcon#end of sib2, iclass 28, count 2 2006.225.07:52:02.36#ibcon#*after write, iclass 28, count 2 2006.225.07:52:02.36#ibcon#*before return 0, iclass 28, count 2 2006.225.07:52:02.36#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:52:02.36#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.07:52:02.36#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.07:52:02.36#ibcon#ireg 7 cls_cnt 0 2006.225.07:52:02.36#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:52:02.48#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:52:02.48#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:52:02.48#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:52:02.48#ibcon#first serial, iclass 28, count 0 2006.225.07:52:02.48#ibcon#enter sib2, iclass 28, count 0 2006.225.07:52:02.48#ibcon#flushed, iclass 28, count 0 2006.225.07:52:02.48#ibcon#about to write, iclass 28, count 0 2006.225.07:52:02.48#ibcon#wrote, iclass 28, count 0 2006.225.07:52:02.48#ibcon#about to read 3, iclass 28, count 0 2006.225.07:52:02.50#ibcon#read 3, iclass 28, count 0 2006.225.07:52:02.50#ibcon#about to read 4, iclass 28, count 0 2006.225.07:52:02.50#ibcon#read 4, iclass 28, count 0 2006.225.07:52:02.50#ibcon#about to read 5, iclass 28, count 0 2006.225.07:52:02.50#ibcon#read 5, iclass 28, count 0 2006.225.07:52:02.50#ibcon#about to read 6, iclass 28, count 0 2006.225.07:52:02.50#ibcon#read 6, iclass 28, count 0 2006.225.07:52:02.50#ibcon#end of sib2, iclass 28, count 0 2006.225.07:52:02.50#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:52:02.50#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:52:02.50#ibcon#[27=USB\r\n] 2006.225.07:52:02.50#ibcon#*before write, iclass 28, count 0 2006.225.07:52:02.50#ibcon#enter sib2, iclass 28, count 0 2006.225.07:52:02.50#ibcon#flushed, iclass 28, count 0 2006.225.07:52:02.50#ibcon#about to write, iclass 28, count 0 2006.225.07:52:02.50#ibcon#wrote, iclass 28, count 0 2006.225.07:52:02.50#ibcon#about to read 3, iclass 28, count 0 2006.225.07:52:02.53#ibcon#read 3, iclass 28, count 0 2006.225.07:52:02.53#ibcon#about to read 4, iclass 28, count 0 2006.225.07:52:02.53#ibcon#read 4, iclass 28, count 0 2006.225.07:52:02.53#ibcon#about to read 5, iclass 28, count 0 2006.225.07:52:02.53#ibcon#read 5, iclass 28, count 0 2006.225.07:52:02.53#ibcon#about to read 6, iclass 28, count 0 2006.225.07:52:02.53#ibcon#read 6, iclass 28, count 0 2006.225.07:52:02.53#ibcon#end of sib2, iclass 28, count 0 2006.225.07:52:02.53#ibcon#*after write, iclass 28, count 0 2006.225.07:52:02.53#ibcon#*before return 0, iclass 28, count 0 2006.225.07:52:02.53#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:52:02.53#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.07:52:02.53#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:52:02.53#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:52:02.53$vc4f8/vabw=wide 2006.225.07:52:02.53#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.07:52:02.53#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.07:52:02.53#ibcon#ireg 8 cls_cnt 0 2006.225.07:52:02.53#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:52:02.53#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:52:02.53#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:52:02.53#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:52:02.53#ibcon#first serial, iclass 30, count 0 2006.225.07:52:02.53#ibcon#enter sib2, iclass 30, count 0 2006.225.07:52:02.53#ibcon#flushed, iclass 30, count 0 2006.225.07:52:02.53#ibcon#about to write, iclass 30, count 0 2006.225.07:52:02.53#ibcon#wrote, iclass 30, count 0 2006.225.07:52:02.53#ibcon#about to read 3, iclass 30, count 0 2006.225.07:52:02.55#ibcon#read 3, iclass 30, count 0 2006.225.07:52:02.55#ibcon#about to read 4, iclass 30, count 0 2006.225.07:52:02.55#ibcon#read 4, iclass 30, count 0 2006.225.07:52:02.55#ibcon#about to read 5, iclass 30, count 0 2006.225.07:52:02.55#ibcon#read 5, iclass 30, count 0 2006.225.07:52:02.55#ibcon#about to read 6, iclass 30, count 0 2006.225.07:52:02.55#ibcon#read 6, iclass 30, count 0 2006.225.07:52:02.55#ibcon#end of sib2, iclass 30, count 0 2006.225.07:52:02.55#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:52:02.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:52:02.55#ibcon#[25=BW32\r\n] 2006.225.07:52:02.55#ibcon#*before write, iclass 30, count 0 2006.225.07:52:02.55#ibcon#enter sib2, iclass 30, count 0 2006.225.07:52:02.55#ibcon#flushed, iclass 30, count 0 2006.225.07:52:02.55#ibcon#about to write, iclass 30, count 0 2006.225.07:52:02.55#ibcon#wrote, iclass 30, count 0 2006.225.07:52:02.55#ibcon#about to read 3, iclass 30, count 0 2006.225.07:52:02.58#ibcon#read 3, iclass 30, count 0 2006.225.07:52:02.58#ibcon#about to read 4, iclass 30, count 0 2006.225.07:52:02.58#ibcon#read 4, iclass 30, count 0 2006.225.07:52:02.58#ibcon#about to read 5, iclass 30, count 0 2006.225.07:52:02.58#ibcon#read 5, iclass 30, count 0 2006.225.07:52:02.58#ibcon#about to read 6, iclass 30, count 0 2006.225.07:52:02.58#ibcon#read 6, iclass 30, count 0 2006.225.07:52:02.58#ibcon#end of sib2, iclass 30, count 0 2006.225.07:52:02.58#ibcon#*after write, iclass 30, count 0 2006.225.07:52:02.58#ibcon#*before return 0, iclass 30, count 0 2006.225.07:52:02.58#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:52:02.58#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.07:52:02.58#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:52:02.58#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:52:02.58$vc4f8/vbbw=wide 2006.225.07:52:02.58#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.07:52:02.58#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.07:52:02.58#ibcon#ireg 8 cls_cnt 0 2006.225.07:52:02.58#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:52:02.65#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:52:02.65#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:52:02.65#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:52:02.65#ibcon#first serial, iclass 32, count 0 2006.225.07:52:02.65#ibcon#enter sib2, iclass 32, count 0 2006.225.07:52:02.65#ibcon#flushed, iclass 32, count 0 2006.225.07:52:02.65#ibcon#about to write, iclass 32, count 0 2006.225.07:52:02.65#ibcon#wrote, iclass 32, count 0 2006.225.07:52:02.65#ibcon#about to read 3, iclass 32, count 0 2006.225.07:52:02.67#ibcon#read 3, iclass 32, count 0 2006.225.07:52:02.67#ibcon#about to read 4, iclass 32, count 0 2006.225.07:52:02.67#ibcon#read 4, iclass 32, count 0 2006.225.07:52:02.67#ibcon#about to read 5, iclass 32, count 0 2006.225.07:52:02.67#ibcon#read 5, iclass 32, count 0 2006.225.07:52:02.67#ibcon#about to read 6, iclass 32, count 0 2006.225.07:52:02.67#ibcon#read 6, iclass 32, count 0 2006.225.07:52:02.67#ibcon#end of sib2, iclass 32, count 0 2006.225.07:52:02.67#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:52:02.67#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:52:02.67#ibcon#[27=BW32\r\n] 2006.225.07:52:02.67#ibcon#*before write, iclass 32, count 0 2006.225.07:52:02.67#ibcon#enter sib2, iclass 32, count 0 2006.225.07:52:02.67#ibcon#flushed, iclass 32, count 0 2006.225.07:52:02.67#ibcon#about to write, iclass 32, count 0 2006.225.07:52:02.67#ibcon#wrote, iclass 32, count 0 2006.225.07:52:02.67#ibcon#about to read 3, iclass 32, count 0 2006.225.07:52:02.70#ibcon#read 3, iclass 32, count 0 2006.225.07:52:02.70#ibcon#about to read 4, iclass 32, count 0 2006.225.07:52:02.70#ibcon#read 4, iclass 32, count 0 2006.225.07:52:02.70#ibcon#about to read 5, iclass 32, count 0 2006.225.07:52:02.70#ibcon#read 5, iclass 32, count 0 2006.225.07:52:02.70#ibcon#about to read 6, iclass 32, count 0 2006.225.07:52:02.70#ibcon#read 6, iclass 32, count 0 2006.225.07:52:02.70#ibcon#end of sib2, iclass 32, count 0 2006.225.07:52:02.70#ibcon#*after write, iclass 32, count 0 2006.225.07:52:02.70#ibcon#*before return 0, iclass 32, count 0 2006.225.07:52:02.70#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:52:02.70#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:52:02.70#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:52:02.70#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:52:02.70$4f8m12a/ifd4f 2006.225.07:52:02.70$ifd4f/lo= 2006.225.07:52:02.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:52:02.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:52:02.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:52:02.70$ifd4f/patch= 2006.225.07:52:02.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:52:02.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:52:02.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:52:02.70$4f8m12a/"form=m,16.000,1:2 2006.225.07:52:02.70$4f8m12a/"tpicd 2006.225.07:52:02.70$4f8m12a/echo=off 2006.225.07:52:02.70$4f8m12a/xlog=off 2006.225.07:52:02.70:!2006.225.07:52:30 2006.225.07:52:12.13#trakl#Source acquired 2006.225.07:52:12.13#flagr#flagr/antenna,acquired 2006.225.07:52:30.00:preob 2006.225.07:52:31.13/onsource/TRACKING 2006.225.07:52:31.13:!2006.225.07:52:40 2006.225.07:52:40.00:data_valid=on 2006.225.07:52:40.00:midob 2006.225.07:52:40.13/onsource/TRACKING 2006.225.07:52:40.13/wx/28.32,1003.3,71 2006.225.07:52:40.30/cable/+6.4051E-03 2006.225.07:52:41.39/va/01,08,usb,yes,29,30 2006.225.07:52:41.39/va/02,07,usb,yes,29,30 2006.225.07:52:41.39/va/03,06,usb,yes,31,31 2006.225.07:52:41.39/va/04,07,usb,yes,30,32 2006.225.07:52:41.39/va/05,07,usb,yes,33,34 2006.225.07:52:41.39/va/06,06,usb,yes,32,32 2006.225.07:52:41.39/va/07,06,usb,yes,32,32 2006.225.07:52:41.39/va/08,07,usb,yes,31,30 2006.225.07:52:41.62/valo/01,532.99,yes,locked 2006.225.07:52:41.62/valo/02,572.99,yes,locked 2006.225.07:52:41.62/valo/03,672.99,yes,locked 2006.225.07:52:41.62/valo/04,832.99,yes,locked 2006.225.07:52:41.62/valo/05,652.99,yes,locked 2006.225.07:52:41.62/valo/06,772.99,yes,locked 2006.225.07:52:41.62/valo/07,832.99,yes,locked 2006.225.07:52:41.62/valo/08,852.99,yes,locked 2006.225.07:52:42.71/vb/01,04,usb,yes,31,29 2006.225.07:52:42.71/vb/02,04,usb,yes,32,34 2006.225.07:52:42.71/vb/03,04,usb,yes,29,33 2006.225.07:52:42.71/vb/04,04,usb,yes,30,30 2006.225.07:52:42.71/vb/05,04,usb,yes,28,32 2006.225.07:52:42.71/vb/06,04,usb,yes,29,32 2006.225.07:52:42.71/vb/07,04,usb,yes,31,31 2006.225.07:52:42.71/vb/08,04,usb,yes,29,32 2006.225.07:52:42.94/vblo/01,632.99,yes,locked 2006.225.07:52:42.94/vblo/02,640.99,yes,locked 2006.225.07:52:42.94/vblo/03,656.99,yes,locked 2006.225.07:52:42.94/vblo/04,712.99,yes,locked 2006.225.07:52:42.94/vblo/05,744.99,yes,locked 2006.225.07:52:42.94/vblo/06,752.99,yes,locked 2006.225.07:52:42.94/vblo/07,734.99,yes,locked 2006.225.07:52:42.94/vblo/08,744.99,yes,locked 2006.225.07:52:43.09/vabw/8 2006.225.07:52:43.24/vbbw/8 2006.225.07:52:43.33/xfe/off,on,16.0 2006.225.07:52:43.71/ifatt/23,28,28,28 2006.225.07:52:44.08/fmout-gps/S +4.53E-07 2006.225.07:52:44.12:!2006.225.07:53:40 2006.225.07:53:40.00:data_valid=off 2006.225.07:53:40.00:postob 2006.225.07:53:40.10/cable/+6.4036E-03 2006.225.07:53:40.10/wx/28.34,1003.3,70 2006.225.07:53:41.08/fmout-gps/S +4.55E-07 2006.225.07:53:41.08:scan_name=225-0755,k06225,60 2006.225.07:53:41.08:source=3c418,203837.03,511912.7,2000.0,cw 2006.225.07:53:41.15#flagr#flagr/antenna,new-source 2006.225.07:53:42.14:checkk5 2006.225.07:53:42.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:53:42.89/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:53:43.26/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:53:43.64/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:53:44.01/chk_obsdata//k5ts1/T2250752??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:53:44.38/chk_obsdata//k5ts2/T2250752??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:53:44.74/chk_obsdata//k5ts3/T2250752??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:53:45.11/chk_obsdata//k5ts4/T2250752??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:53:45.80/k5log//k5ts1_log_newline 2006.225.07:53:46.48/k5log//k5ts2_log_newline 2006.225.07:53:47.16/k5log//k5ts3_log_newline 2006.225.07:53:47.84/k5log//k5ts4_log_newline 2006.225.07:53:47.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:53:47.87:4f8m12a=2 2006.225.07:53:47.87$4f8m12a/echo=on 2006.225.07:53:47.87$4f8m12a/pcalon 2006.225.07:53:47.87$pcalon/"no phase cal control is implemented here 2006.225.07:53:47.87$4f8m12a/"tpicd=stop 2006.225.07:53:47.87$4f8m12a/vc4f8 2006.225.07:53:47.87$vc4f8/valo=1,532.99 2006.225.07:53:47.88#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.07:53:47.88#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.07:53:47.88#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:47.88#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:53:47.88#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:53:47.88#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:53:47.88#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:53:47.88#ibcon#first serial, iclass 39, count 0 2006.225.07:53:47.88#ibcon#enter sib2, iclass 39, count 0 2006.225.07:53:47.88#ibcon#flushed, iclass 39, count 0 2006.225.07:53:47.88#ibcon#about to write, iclass 39, count 0 2006.225.07:53:47.88#ibcon#wrote, iclass 39, count 0 2006.225.07:53:47.88#ibcon#about to read 3, iclass 39, count 0 2006.225.07:53:47.91#ibcon#read 3, iclass 39, count 0 2006.225.07:53:47.91#ibcon#about to read 4, iclass 39, count 0 2006.225.07:53:47.91#ibcon#read 4, iclass 39, count 0 2006.225.07:53:47.91#ibcon#about to read 5, iclass 39, count 0 2006.225.07:53:47.91#ibcon#read 5, iclass 39, count 0 2006.225.07:53:47.91#ibcon#about to read 6, iclass 39, count 0 2006.225.07:53:47.91#ibcon#read 6, iclass 39, count 0 2006.225.07:53:47.91#ibcon#end of sib2, iclass 39, count 0 2006.225.07:53:47.91#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:53:47.91#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:53:47.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:53:47.91#ibcon#*before write, iclass 39, count 0 2006.225.07:53:47.91#ibcon#enter sib2, iclass 39, count 0 2006.225.07:53:47.91#ibcon#flushed, iclass 39, count 0 2006.225.07:53:47.91#ibcon#about to write, iclass 39, count 0 2006.225.07:53:47.91#ibcon#wrote, iclass 39, count 0 2006.225.07:53:47.91#ibcon#about to read 3, iclass 39, count 0 2006.225.07:53:47.96#ibcon#read 3, iclass 39, count 0 2006.225.07:53:47.96#ibcon#about to read 4, iclass 39, count 0 2006.225.07:53:47.96#ibcon#read 4, iclass 39, count 0 2006.225.07:53:47.96#ibcon#about to read 5, iclass 39, count 0 2006.225.07:53:47.96#ibcon#read 5, iclass 39, count 0 2006.225.07:53:47.96#ibcon#about to read 6, iclass 39, count 0 2006.225.07:53:47.96#ibcon#read 6, iclass 39, count 0 2006.225.07:53:47.96#ibcon#end of sib2, iclass 39, count 0 2006.225.07:53:47.96#ibcon#*after write, iclass 39, count 0 2006.225.07:53:47.96#ibcon#*before return 0, iclass 39, count 0 2006.225.07:53:47.96#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:53:47.96#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:53:47.96#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:53:47.96#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:53:47.96$vc4f8/va=1,8 2006.225.07:53:47.96#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.07:53:47.96#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.07:53:47.96#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:47.96#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:53:47.96#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:53:47.96#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:53:47.96#ibcon#enter wrdev, iclass 3, count 2 2006.225.07:53:47.96#ibcon#first serial, iclass 3, count 2 2006.225.07:53:47.96#ibcon#enter sib2, iclass 3, count 2 2006.225.07:53:47.96#ibcon#flushed, iclass 3, count 2 2006.225.07:53:47.96#ibcon#about to write, iclass 3, count 2 2006.225.07:53:47.96#ibcon#wrote, iclass 3, count 2 2006.225.07:53:47.96#ibcon#about to read 3, iclass 3, count 2 2006.225.07:53:47.98#ibcon#read 3, iclass 3, count 2 2006.225.07:53:47.98#ibcon#about to read 4, iclass 3, count 2 2006.225.07:53:47.98#ibcon#read 4, iclass 3, count 2 2006.225.07:53:47.98#ibcon#about to read 5, iclass 3, count 2 2006.225.07:53:47.98#ibcon#read 5, iclass 3, count 2 2006.225.07:53:47.98#ibcon#about to read 6, iclass 3, count 2 2006.225.07:53:47.98#ibcon#read 6, iclass 3, count 2 2006.225.07:53:47.98#ibcon#end of sib2, iclass 3, count 2 2006.225.07:53:47.98#ibcon#*mode == 0, iclass 3, count 2 2006.225.07:53:47.98#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.07:53:47.98#ibcon#[25=AT01-08\r\n] 2006.225.07:53:47.98#ibcon#*before write, iclass 3, count 2 2006.225.07:53:47.98#ibcon#enter sib2, iclass 3, count 2 2006.225.07:53:47.98#ibcon#flushed, iclass 3, count 2 2006.225.07:53:47.98#ibcon#about to write, iclass 3, count 2 2006.225.07:53:47.98#ibcon#wrote, iclass 3, count 2 2006.225.07:53:47.98#ibcon#about to read 3, iclass 3, count 2 2006.225.07:53:48.01#ibcon#read 3, iclass 3, count 2 2006.225.07:53:48.01#ibcon#about to read 4, iclass 3, count 2 2006.225.07:53:48.01#ibcon#read 4, iclass 3, count 2 2006.225.07:53:48.01#ibcon#about to read 5, iclass 3, count 2 2006.225.07:53:48.01#ibcon#read 5, iclass 3, count 2 2006.225.07:53:48.01#ibcon#about to read 6, iclass 3, count 2 2006.225.07:53:48.01#ibcon#read 6, iclass 3, count 2 2006.225.07:53:48.01#ibcon#end of sib2, iclass 3, count 2 2006.225.07:53:48.01#ibcon#*after write, iclass 3, count 2 2006.225.07:53:48.01#ibcon#*before return 0, iclass 3, count 2 2006.225.07:53:48.01#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:53:48.01#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:53:48.01#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.07:53:48.01#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:48.01#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:53:48.13#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:53:48.13#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:53:48.13#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:53:48.13#ibcon#first serial, iclass 3, count 0 2006.225.07:53:48.13#ibcon#enter sib2, iclass 3, count 0 2006.225.07:53:48.13#ibcon#flushed, iclass 3, count 0 2006.225.07:53:48.13#ibcon#about to write, iclass 3, count 0 2006.225.07:53:48.13#ibcon#wrote, iclass 3, count 0 2006.225.07:53:48.13#ibcon#about to read 3, iclass 3, count 0 2006.225.07:53:48.15#ibcon#read 3, iclass 3, count 0 2006.225.07:53:48.15#ibcon#about to read 4, iclass 3, count 0 2006.225.07:53:48.15#ibcon#read 4, iclass 3, count 0 2006.225.07:53:48.15#ibcon#about to read 5, iclass 3, count 0 2006.225.07:53:48.15#ibcon#read 5, iclass 3, count 0 2006.225.07:53:48.15#ibcon#about to read 6, iclass 3, count 0 2006.225.07:53:48.15#ibcon#read 6, iclass 3, count 0 2006.225.07:53:48.15#ibcon#end of sib2, iclass 3, count 0 2006.225.07:53:48.15#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:53:48.15#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:53:48.15#ibcon#[25=USB\r\n] 2006.225.07:53:48.15#ibcon#*before write, iclass 3, count 0 2006.225.07:53:48.15#ibcon#enter sib2, iclass 3, count 0 2006.225.07:53:48.15#ibcon#flushed, iclass 3, count 0 2006.225.07:53:48.15#ibcon#about to write, iclass 3, count 0 2006.225.07:53:48.15#ibcon#wrote, iclass 3, count 0 2006.225.07:53:48.15#ibcon#about to read 3, iclass 3, count 0 2006.225.07:53:48.18#ibcon#read 3, iclass 3, count 0 2006.225.07:53:48.18#ibcon#about to read 4, iclass 3, count 0 2006.225.07:53:48.18#ibcon#read 4, iclass 3, count 0 2006.225.07:53:48.18#ibcon#about to read 5, iclass 3, count 0 2006.225.07:53:48.18#ibcon#read 5, iclass 3, count 0 2006.225.07:53:48.18#ibcon#about to read 6, iclass 3, count 0 2006.225.07:53:48.18#ibcon#read 6, iclass 3, count 0 2006.225.07:53:48.18#ibcon#end of sib2, iclass 3, count 0 2006.225.07:53:48.18#ibcon#*after write, iclass 3, count 0 2006.225.07:53:48.18#ibcon#*before return 0, iclass 3, count 0 2006.225.07:53:48.18#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:53:48.18#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:53:48.18#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:53:48.18#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:53:48.18$vc4f8/valo=2,572.99 2006.225.07:53:48.18#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.07:53:48.18#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.07:53:48.18#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:48.18#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:53:48.18#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:53:48.18#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:53:48.18#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:53:48.18#ibcon#first serial, iclass 5, count 0 2006.225.07:53:48.18#ibcon#enter sib2, iclass 5, count 0 2006.225.07:53:48.18#ibcon#flushed, iclass 5, count 0 2006.225.07:53:48.18#ibcon#about to write, iclass 5, count 0 2006.225.07:53:48.18#ibcon#wrote, iclass 5, count 0 2006.225.07:53:48.18#ibcon#about to read 3, iclass 5, count 0 2006.225.07:53:48.20#ibcon#read 3, iclass 5, count 0 2006.225.07:53:48.20#ibcon#about to read 4, iclass 5, count 0 2006.225.07:53:48.20#ibcon#read 4, iclass 5, count 0 2006.225.07:53:48.20#ibcon#about to read 5, iclass 5, count 0 2006.225.07:53:48.20#ibcon#read 5, iclass 5, count 0 2006.225.07:53:48.20#ibcon#about to read 6, iclass 5, count 0 2006.225.07:53:48.20#ibcon#read 6, iclass 5, count 0 2006.225.07:53:48.20#ibcon#end of sib2, iclass 5, count 0 2006.225.07:53:48.20#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:53:48.20#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:53:48.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:53:48.20#ibcon#*before write, iclass 5, count 0 2006.225.07:53:48.20#ibcon#enter sib2, iclass 5, count 0 2006.225.07:53:48.20#ibcon#flushed, iclass 5, count 0 2006.225.07:53:48.20#ibcon#about to write, iclass 5, count 0 2006.225.07:53:48.20#ibcon#wrote, iclass 5, count 0 2006.225.07:53:48.20#ibcon#about to read 3, iclass 5, count 0 2006.225.07:53:48.25#ibcon#read 3, iclass 5, count 0 2006.225.07:53:48.25#ibcon#about to read 4, iclass 5, count 0 2006.225.07:53:48.25#ibcon#read 4, iclass 5, count 0 2006.225.07:53:48.25#ibcon#about to read 5, iclass 5, count 0 2006.225.07:53:48.25#ibcon#read 5, iclass 5, count 0 2006.225.07:53:48.25#ibcon#about to read 6, iclass 5, count 0 2006.225.07:53:48.25#ibcon#read 6, iclass 5, count 0 2006.225.07:53:48.25#ibcon#end of sib2, iclass 5, count 0 2006.225.07:53:48.25#ibcon#*after write, iclass 5, count 0 2006.225.07:53:48.25#ibcon#*before return 0, iclass 5, count 0 2006.225.07:53:48.25#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:53:48.25#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:53:48.25#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:53:48.25#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:53:48.25$vc4f8/va=2,7 2006.225.07:53:48.25#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.07:53:48.25#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.07:53:48.25#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:48.25#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:53:48.30#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:53:48.30#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:53:48.30#ibcon#enter wrdev, iclass 7, count 2 2006.225.07:53:48.30#ibcon#first serial, iclass 7, count 2 2006.225.07:53:48.30#ibcon#enter sib2, iclass 7, count 2 2006.225.07:53:48.30#ibcon#flushed, iclass 7, count 2 2006.225.07:53:48.30#ibcon#about to write, iclass 7, count 2 2006.225.07:53:48.30#ibcon#wrote, iclass 7, count 2 2006.225.07:53:48.30#ibcon#about to read 3, iclass 7, count 2 2006.225.07:53:48.32#ibcon#read 3, iclass 7, count 2 2006.225.07:53:48.32#ibcon#about to read 4, iclass 7, count 2 2006.225.07:53:48.32#ibcon#read 4, iclass 7, count 2 2006.225.07:53:48.32#ibcon#about to read 5, iclass 7, count 2 2006.225.07:53:48.32#ibcon#read 5, iclass 7, count 2 2006.225.07:53:48.32#ibcon#about to read 6, iclass 7, count 2 2006.225.07:53:48.32#ibcon#read 6, iclass 7, count 2 2006.225.07:53:48.32#ibcon#end of sib2, iclass 7, count 2 2006.225.07:53:48.32#ibcon#*mode == 0, iclass 7, count 2 2006.225.07:53:48.32#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.07:53:48.32#ibcon#[25=AT02-07\r\n] 2006.225.07:53:48.32#ibcon#*before write, iclass 7, count 2 2006.225.07:53:48.32#ibcon#enter sib2, iclass 7, count 2 2006.225.07:53:48.32#ibcon#flushed, iclass 7, count 2 2006.225.07:53:48.32#ibcon#about to write, iclass 7, count 2 2006.225.07:53:48.32#ibcon#wrote, iclass 7, count 2 2006.225.07:53:48.32#ibcon#about to read 3, iclass 7, count 2 2006.225.07:53:48.35#ibcon#read 3, iclass 7, count 2 2006.225.07:53:48.35#ibcon#about to read 4, iclass 7, count 2 2006.225.07:53:48.35#ibcon#read 4, iclass 7, count 2 2006.225.07:53:48.35#ibcon#about to read 5, iclass 7, count 2 2006.225.07:53:48.35#ibcon#read 5, iclass 7, count 2 2006.225.07:53:48.35#ibcon#about to read 6, iclass 7, count 2 2006.225.07:53:48.35#ibcon#read 6, iclass 7, count 2 2006.225.07:53:48.35#ibcon#end of sib2, iclass 7, count 2 2006.225.07:53:48.35#ibcon#*after write, iclass 7, count 2 2006.225.07:53:48.35#ibcon#*before return 0, iclass 7, count 2 2006.225.07:53:48.35#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:53:48.35#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:53:48.35#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.07:53:48.35#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:48.35#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:53:48.47#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:53:48.47#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:53:48.47#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:53:48.47#ibcon#first serial, iclass 7, count 0 2006.225.07:53:48.47#ibcon#enter sib2, iclass 7, count 0 2006.225.07:53:48.47#ibcon#flushed, iclass 7, count 0 2006.225.07:53:48.47#ibcon#about to write, iclass 7, count 0 2006.225.07:53:48.47#ibcon#wrote, iclass 7, count 0 2006.225.07:53:48.47#ibcon#about to read 3, iclass 7, count 0 2006.225.07:53:48.49#ibcon#read 3, iclass 7, count 0 2006.225.07:53:48.49#ibcon#about to read 4, iclass 7, count 0 2006.225.07:53:48.49#ibcon#read 4, iclass 7, count 0 2006.225.07:53:48.49#ibcon#about to read 5, iclass 7, count 0 2006.225.07:53:48.49#ibcon#read 5, iclass 7, count 0 2006.225.07:53:48.49#ibcon#about to read 6, iclass 7, count 0 2006.225.07:53:48.49#ibcon#read 6, iclass 7, count 0 2006.225.07:53:48.49#ibcon#end of sib2, iclass 7, count 0 2006.225.07:53:48.49#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:53:48.49#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:53:48.49#ibcon#[25=USB\r\n] 2006.225.07:53:48.49#ibcon#*before write, iclass 7, count 0 2006.225.07:53:48.49#ibcon#enter sib2, iclass 7, count 0 2006.225.07:53:48.49#ibcon#flushed, iclass 7, count 0 2006.225.07:53:48.49#ibcon#about to write, iclass 7, count 0 2006.225.07:53:48.49#ibcon#wrote, iclass 7, count 0 2006.225.07:53:48.49#ibcon#about to read 3, iclass 7, count 0 2006.225.07:53:48.52#ibcon#read 3, iclass 7, count 0 2006.225.07:53:48.52#ibcon#about to read 4, iclass 7, count 0 2006.225.07:53:48.52#ibcon#read 4, iclass 7, count 0 2006.225.07:53:48.52#ibcon#about to read 5, iclass 7, count 0 2006.225.07:53:48.52#ibcon#read 5, iclass 7, count 0 2006.225.07:53:48.52#ibcon#about to read 6, iclass 7, count 0 2006.225.07:53:48.52#ibcon#read 6, iclass 7, count 0 2006.225.07:53:48.52#ibcon#end of sib2, iclass 7, count 0 2006.225.07:53:48.52#ibcon#*after write, iclass 7, count 0 2006.225.07:53:48.52#ibcon#*before return 0, iclass 7, count 0 2006.225.07:53:48.52#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:53:48.52#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:53:48.52#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:53:48.52#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:53:48.52$vc4f8/valo=3,672.99 2006.225.07:53:48.52#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.07:53:48.52#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.07:53:48.52#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:48.52#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:53:48.52#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:53:48.52#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:53:48.52#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:53:48.52#ibcon#first serial, iclass 11, count 0 2006.225.07:53:48.52#ibcon#enter sib2, iclass 11, count 0 2006.225.07:53:48.52#ibcon#flushed, iclass 11, count 0 2006.225.07:53:48.52#ibcon#about to write, iclass 11, count 0 2006.225.07:53:48.52#ibcon#wrote, iclass 11, count 0 2006.225.07:53:48.52#ibcon#about to read 3, iclass 11, count 0 2006.225.07:53:48.54#ibcon#read 3, iclass 11, count 0 2006.225.07:53:48.54#ibcon#about to read 4, iclass 11, count 0 2006.225.07:53:48.54#ibcon#read 4, iclass 11, count 0 2006.225.07:53:48.54#ibcon#about to read 5, iclass 11, count 0 2006.225.07:53:48.54#ibcon#read 5, iclass 11, count 0 2006.225.07:53:48.54#ibcon#about to read 6, iclass 11, count 0 2006.225.07:53:48.54#ibcon#read 6, iclass 11, count 0 2006.225.07:53:48.54#ibcon#end of sib2, iclass 11, count 0 2006.225.07:53:48.54#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:53:48.54#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:53:48.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:53:48.54#ibcon#*before write, iclass 11, count 0 2006.225.07:53:48.54#ibcon#enter sib2, iclass 11, count 0 2006.225.07:53:48.54#ibcon#flushed, iclass 11, count 0 2006.225.07:53:48.54#ibcon#about to write, iclass 11, count 0 2006.225.07:53:48.54#ibcon#wrote, iclass 11, count 0 2006.225.07:53:48.54#ibcon#about to read 3, iclass 11, count 0 2006.225.07:53:48.59#ibcon#read 3, iclass 11, count 0 2006.225.07:53:48.59#ibcon#about to read 4, iclass 11, count 0 2006.225.07:53:48.59#ibcon#read 4, iclass 11, count 0 2006.225.07:53:48.59#ibcon#about to read 5, iclass 11, count 0 2006.225.07:53:48.59#ibcon#read 5, iclass 11, count 0 2006.225.07:53:48.59#ibcon#about to read 6, iclass 11, count 0 2006.225.07:53:48.59#ibcon#read 6, iclass 11, count 0 2006.225.07:53:48.59#ibcon#end of sib2, iclass 11, count 0 2006.225.07:53:48.59#ibcon#*after write, iclass 11, count 0 2006.225.07:53:48.59#ibcon#*before return 0, iclass 11, count 0 2006.225.07:53:48.59#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:53:48.59#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:53:48.59#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:53:48.59#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:53:48.59$vc4f8/va=3,6 2006.225.07:53:48.59#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.07:53:48.59#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.07:53:48.59#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:48.59#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:53:48.64#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:53:48.64#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:53:48.64#ibcon#enter wrdev, iclass 13, count 2 2006.225.07:53:48.64#ibcon#first serial, iclass 13, count 2 2006.225.07:53:48.64#ibcon#enter sib2, iclass 13, count 2 2006.225.07:53:48.64#ibcon#flushed, iclass 13, count 2 2006.225.07:53:48.64#ibcon#about to write, iclass 13, count 2 2006.225.07:53:48.64#ibcon#wrote, iclass 13, count 2 2006.225.07:53:48.64#ibcon#about to read 3, iclass 13, count 2 2006.225.07:53:48.66#ibcon#read 3, iclass 13, count 2 2006.225.07:53:48.66#ibcon#about to read 4, iclass 13, count 2 2006.225.07:53:48.66#ibcon#read 4, iclass 13, count 2 2006.225.07:53:48.66#ibcon#about to read 5, iclass 13, count 2 2006.225.07:53:48.66#ibcon#read 5, iclass 13, count 2 2006.225.07:53:48.66#ibcon#about to read 6, iclass 13, count 2 2006.225.07:53:48.66#ibcon#read 6, iclass 13, count 2 2006.225.07:53:48.66#ibcon#end of sib2, iclass 13, count 2 2006.225.07:53:48.66#ibcon#*mode == 0, iclass 13, count 2 2006.225.07:53:48.66#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.07:53:48.66#ibcon#[25=AT03-06\r\n] 2006.225.07:53:48.66#ibcon#*before write, iclass 13, count 2 2006.225.07:53:48.66#ibcon#enter sib2, iclass 13, count 2 2006.225.07:53:48.66#ibcon#flushed, iclass 13, count 2 2006.225.07:53:48.66#ibcon#about to write, iclass 13, count 2 2006.225.07:53:48.66#ibcon#wrote, iclass 13, count 2 2006.225.07:53:48.66#ibcon#about to read 3, iclass 13, count 2 2006.225.07:53:48.69#ibcon#read 3, iclass 13, count 2 2006.225.07:53:48.69#ibcon#about to read 4, iclass 13, count 2 2006.225.07:53:48.69#ibcon#read 4, iclass 13, count 2 2006.225.07:53:48.69#ibcon#about to read 5, iclass 13, count 2 2006.225.07:53:48.69#ibcon#read 5, iclass 13, count 2 2006.225.07:53:48.69#ibcon#about to read 6, iclass 13, count 2 2006.225.07:53:48.69#ibcon#read 6, iclass 13, count 2 2006.225.07:53:48.69#ibcon#end of sib2, iclass 13, count 2 2006.225.07:53:48.69#ibcon#*after write, iclass 13, count 2 2006.225.07:53:48.69#ibcon#*before return 0, iclass 13, count 2 2006.225.07:53:48.69#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:53:48.69#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:53:48.69#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.07:53:48.69#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:48.69#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:53:48.81#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:53:48.81#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:53:48.81#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:53:48.81#ibcon#first serial, iclass 13, count 0 2006.225.07:53:48.81#ibcon#enter sib2, iclass 13, count 0 2006.225.07:53:48.81#ibcon#flushed, iclass 13, count 0 2006.225.07:53:48.81#ibcon#about to write, iclass 13, count 0 2006.225.07:53:48.81#ibcon#wrote, iclass 13, count 0 2006.225.07:53:48.81#ibcon#about to read 3, iclass 13, count 0 2006.225.07:53:48.83#ibcon#read 3, iclass 13, count 0 2006.225.07:53:48.83#ibcon#about to read 4, iclass 13, count 0 2006.225.07:53:48.83#ibcon#read 4, iclass 13, count 0 2006.225.07:53:48.83#ibcon#about to read 5, iclass 13, count 0 2006.225.07:53:48.83#ibcon#read 5, iclass 13, count 0 2006.225.07:53:48.83#ibcon#about to read 6, iclass 13, count 0 2006.225.07:53:48.83#ibcon#read 6, iclass 13, count 0 2006.225.07:53:48.83#ibcon#end of sib2, iclass 13, count 0 2006.225.07:53:48.83#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:53:48.83#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:53:48.83#ibcon#[25=USB\r\n] 2006.225.07:53:48.83#ibcon#*before write, iclass 13, count 0 2006.225.07:53:48.83#ibcon#enter sib2, iclass 13, count 0 2006.225.07:53:48.83#ibcon#flushed, iclass 13, count 0 2006.225.07:53:48.83#ibcon#about to write, iclass 13, count 0 2006.225.07:53:48.83#ibcon#wrote, iclass 13, count 0 2006.225.07:53:48.83#ibcon#about to read 3, iclass 13, count 0 2006.225.07:53:48.86#ibcon#read 3, iclass 13, count 0 2006.225.07:53:48.86#ibcon#about to read 4, iclass 13, count 0 2006.225.07:53:48.86#ibcon#read 4, iclass 13, count 0 2006.225.07:53:48.86#ibcon#about to read 5, iclass 13, count 0 2006.225.07:53:48.86#ibcon#read 5, iclass 13, count 0 2006.225.07:53:48.86#ibcon#about to read 6, iclass 13, count 0 2006.225.07:53:48.86#ibcon#read 6, iclass 13, count 0 2006.225.07:53:48.86#ibcon#end of sib2, iclass 13, count 0 2006.225.07:53:48.86#ibcon#*after write, iclass 13, count 0 2006.225.07:53:48.86#ibcon#*before return 0, iclass 13, count 0 2006.225.07:53:48.86#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:53:48.86#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:53:48.86#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:53:48.86#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:53:48.86$vc4f8/valo=4,832.99 2006.225.07:53:48.86#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.07:53:48.86#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.07:53:48.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:48.86#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:53:48.86#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:53:48.86#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:53:48.86#ibcon#enter wrdev, iclass 15, count 0 2006.225.07:53:48.86#ibcon#first serial, iclass 15, count 0 2006.225.07:53:48.86#ibcon#enter sib2, iclass 15, count 0 2006.225.07:53:48.86#ibcon#flushed, iclass 15, count 0 2006.225.07:53:48.86#ibcon#about to write, iclass 15, count 0 2006.225.07:53:48.86#ibcon#wrote, iclass 15, count 0 2006.225.07:53:48.86#ibcon#about to read 3, iclass 15, count 0 2006.225.07:53:48.88#ibcon#read 3, iclass 15, count 0 2006.225.07:53:48.88#ibcon#about to read 4, iclass 15, count 0 2006.225.07:53:48.88#ibcon#read 4, iclass 15, count 0 2006.225.07:53:48.88#ibcon#about to read 5, iclass 15, count 0 2006.225.07:53:48.88#ibcon#read 5, iclass 15, count 0 2006.225.07:53:48.88#ibcon#about to read 6, iclass 15, count 0 2006.225.07:53:48.88#ibcon#read 6, iclass 15, count 0 2006.225.07:53:48.88#ibcon#end of sib2, iclass 15, count 0 2006.225.07:53:48.88#ibcon#*mode == 0, iclass 15, count 0 2006.225.07:53:48.88#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.07:53:48.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:53:48.88#ibcon#*before write, iclass 15, count 0 2006.225.07:53:48.88#ibcon#enter sib2, iclass 15, count 0 2006.225.07:53:48.88#ibcon#flushed, iclass 15, count 0 2006.225.07:53:48.88#ibcon#about to write, iclass 15, count 0 2006.225.07:53:48.88#ibcon#wrote, iclass 15, count 0 2006.225.07:53:48.88#ibcon#about to read 3, iclass 15, count 0 2006.225.07:53:48.92#ibcon#read 3, iclass 15, count 0 2006.225.07:53:48.92#ibcon#about to read 4, iclass 15, count 0 2006.225.07:53:48.92#ibcon#read 4, iclass 15, count 0 2006.225.07:53:48.92#ibcon#about to read 5, iclass 15, count 0 2006.225.07:53:48.92#ibcon#read 5, iclass 15, count 0 2006.225.07:53:48.92#ibcon#about to read 6, iclass 15, count 0 2006.225.07:53:48.92#ibcon#read 6, iclass 15, count 0 2006.225.07:53:48.92#ibcon#end of sib2, iclass 15, count 0 2006.225.07:53:48.92#ibcon#*after write, iclass 15, count 0 2006.225.07:53:48.92#ibcon#*before return 0, iclass 15, count 0 2006.225.07:53:48.92#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:53:48.92#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:53:48.92#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.07:53:48.92#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.07:53:48.92$vc4f8/va=4,7 2006.225.07:53:48.92#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.07:53:48.92#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.07:53:48.92#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:48.92#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:53:48.98#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:53:48.98#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:53:48.98#ibcon#enter wrdev, iclass 17, count 2 2006.225.07:53:48.98#ibcon#first serial, iclass 17, count 2 2006.225.07:53:48.98#ibcon#enter sib2, iclass 17, count 2 2006.225.07:53:48.98#ibcon#flushed, iclass 17, count 2 2006.225.07:53:48.98#ibcon#about to write, iclass 17, count 2 2006.225.07:53:48.98#ibcon#wrote, iclass 17, count 2 2006.225.07:53:48.98#ibcon#about to read 3, iclass 17, count 2 2006.225.07:53:49.00#ibcon#read 3, iclass 17, count 2 2006.225.07:53:49.00#ibcon#about to read 4, iclass 17, count 2 2006.225.07:53:49.00#ibcon#read 4, iclass 17, count 2 2006.225.07:53:49.00#ibcon#about to read 5, iclass 17, count 2 2006.225.07:53:49.00#ibcon#read 5, iclass 17, count 2 2006.225.07:53:49.00#ibcon#about to read 6, iclass 17, count 2 2006.225.07:53:49.00#ibcon#read 6, iclass 17, count 2 2006.225.07:53:49.00#ibcon#end of sib2, iclass 17, count 2 2006.225.07:53:49.00#ibcon#*mode == 0, iclass 17, count 2 2006.225.07:53:49.00#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.07:53:49.00#ibcon#[25=AT04-07\r\n] 2006.225.07:53:49.00#ibcon#*before write, iclass 17, count 2 2006.225.07:53:49.00#ibcon#enter sib2, iclass 17, count 2 2006.225.07:53:49.00#ibcon#flushed, iclass 17, count 2 2006.225.07:53:49.00#ibcon#about to write, iclass 17, count 2 2006.225.07:53:49.00#ibcon#wrote, iclass 17, count 2 2006.225.07:53:49.00#ibcon#about to read 3, iclass 17, count 2 2006.225.07:53:49.03#ibcon#read 3, iclass 17, count 2 2006.225.07:53:49.03#ibcon#about to read 4, iclass 17, count 2 2006.225.07:53:49.03#ibcon#read 4, iclass 17, count 2 2006.225.07:53:49.03#ibcon#about to read 5, iclass 17, count 2 2006.225.07:53:49.03#ibcon#read 5, iclass 17, count 2 2006.225.07:53:49.03#ibcon#about to read 6, iclass 17, count 2 2006.225.07:53:49.03#ibcon#read 6, iclass 17, count 2 2006.225.07:53:49.03#ibcon#end of sib2, iclass 17, count 2 2006.225.07:53:49.03#ibcon#*after write, iclass 17, count 2 2006.225.07:53:49.03#ibcon#*before return 0, iclass 17, count 2 2006.225.07:53:49.03#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:53:49.03#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:53:49.03#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.07:53:49.03#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:49.03#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:53:49.15#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:53:49.15#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:53:49.15#ibcon#enter wrdev, iclass 17, count 0 2006.225.07:53:49.15#ibcon#first serial, iclass 17, count 0 2006.225.07:53:49.15#ibcon#enter sib2, iclass 17, count 0 2006.225.07:53:49.15#ibcon#flushed, iclass 17, count 0 2006.225.07:53:49.15#ibcon#about to write, iclass 17, count 0 2006.225.07:53:49.15#ibcon#wrote, iclass 17, count 0 2006.225.07:53:49.15#ibcon#about to read 3, iclass 17, count 0 2006.225.07:53:49.17#ibcon#read 3, iclass 17, count 0 2006.225.07:53:49.17#ibcon#about to read 4, iclass 17, count 0 2006.225.07:53:49.17#ibcon#read 4, iclass 17, count 0 2006.225.07:53:49.17#ibcon#about to read 5, iclass 17, count 0 2006.225.07:53:49.17#ibcon#read 5, iclass 17, count 0 2006.225.07:53:49.17#ibcon#about to read 6, iclass 17, count 0 2006.225.07:53:49.17#ibcon#read 6, iclass 17, count 0 2006.225.07:53:49.17#ibcon#end of sib2, iclass 17, count 0 2006.225.07:53:49.17#ibcon#*mode == 0, iclass 17, count 0 2006.225.07:53:49.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.07:53:49.17#ibcon#[25=USB\r\n] 2006.225.07:53:49.17#ibcon#*before write, iclass 17, count 0 2006.225.07:53:49.17#ibcon#enter sib2, iclass 17, count 0 2006.225.07:53:49.17#ibcon#flushed, iclass 17, count 0 2006.225.07:53:49.17#ibcon#about to write, iclass 17, count 0 2006.225.07:53:49.17#ibcon#wrote, iclass 17, count 0 2006.225.07:53:49.17#ibcon#about to read 3, iclass 17, count 0 2006.225.07:53:49.20#ibcon#read 3, iclass 17, count 0 2006.225.07:53:49.20#ibcon#about to read 4, iclass 17, count 0 2006.225.07:53:49.20#ibcon#read 4, iclass 17, count 0 2006.225.07:53:49.20#ibcon#about to read 5, iclass 17, count 0 2006.225.07:53:49.20#ibcon#read 5, iclass 17, count 0 2006.225.07:53:49.20#ibcon#about to read 6, iclass 17, count 0 2006.225.07:53:49.20#ibcon#read 6, iclass 17, count 0 2006.225.07:53:49.20#ibcon#end of sib2, iclass 17, count 0 2006.225.07:53:49.20#ibcon#*after write, iclass 17, count 0 2006.225.07:53:49.20#ibcon#*before return 0, iclass 17, count 0 2006.225.07:53:49.20#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:53:49.20#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:53:49.20#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.07:53:49.20#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.07:53:49.20$vc4f8/valo=5,652.99 2006.225.07:53:49.20#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.07:53:49.20#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.07:53:49.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:49.20#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:53:49.20#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:53:49.20#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:53:49.20#ibcon#enter wrdev, iclass 19, count 0 2006.225.07:53:49.20#ibcon#first serial, iclass 19, count 0 2006.225.07:53:49.20#ibcon#enter sib2, iclass 19, count 0 2006.225.07:53:49.20#ibcon#flushed, iclass 19, count 0 2006.225.07:53:49.20#ibcon#about to write, iclass 19, count 0 2006.225.07:53:49.20#ibcon#wrote, iclass 19, count 0 2006.225.07:53:49.20#ibcon#about to read 3, iclass 19, count 0 2006.225.07:53:49.22#ibcon#read 3, iclass 19, count 0 2006.225.07:53:49.22#ibcon#about to read 4, iclass 19, count 0 2006.225.07:53:49.22#ibcon#read 4, iclass 19, count 0 2006.225.07:53:49.22#ibcon#about to read 5, iclass 19, count 0 2006.225.07:53:49.22#ibcon#read 5, iclass 19, count 0 2006.225.07:53:49.22#ibcon#about to read 6, iclass 19, count 0 2006.225.07:53:49.22#ibcon#read 6, iclass 19, count 0 2006.225.07:53:49.22#ibcon#end of sib2, iclass 19, count 0 2006.225.07:53:49.22#ibcon#*mode == 0, iclass 19, count 0 2006.225.07:53:49.22#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.07:53:49.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:53:49.22#ibcon#*before write, iclass 19, count 0 2006.225.07:53:49.22#ibcon#enter sib2, iclass 19, count 0 2006.225.07:53:49.22#ibcon#flushed, iclass 19, count 0 2006.225.07:53:49.22#ibcon#about to write, iclass 19, count 0 2006.225.07:53:49.22#ibcon#wrote, iclass 19, count 0 2006.225.07:53:49.22#ibcon#about to read 3, iclass 19, count 0 2006.225.07:53:49.26#ibcon#read 3, iclass 19, count 0 2006.225.07:53:49.26#ibcon#about to read 4, iclass 19, count 0 2006.225.07:53:49.26#ibcon#read 4, iclass 19, count 0 2006.225.07:53:49.26#ibcon#about to read 5, iclass 19, count 0 2006.225.07:53:49.26#ibcon#read 5, iclass 19, count 0 2006.225.07:53:49.26#ibcon#about to read 6, iclass 19, count 0 2006.225.07:53:49.26#ibcon#read 6, iclass 19, count 0 2006.225.07:53:49.26#ibcon#end of sib2, iclass 19, count 0 2006.225.07:53:49.26#ibcon#*after write, iclass 19, count 0 2006.225.07:53:49.26#ibcon#*before return 0, iclass 19, count 0 2006.225.07:53:49.26#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:53:49.26#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:53:49.26#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.07:53:49.26#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.07:53:49.26$vc4f8/va=5,7 2006.225.07:53:49.26#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.225.07:53:49.26#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.225.07:53:49.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:49.26#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:53:49.32#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:53:49.32#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:53:49.32#ibcon#enter wrdev, iclass 21, count 2 2006.225.07:53:49.32#ibcon#first serial, iclass 21, count 2 2006.225.07:53:49.32#ibcon#enter sib2, iclass 21, count 2 2006.225.07:53:49.32#ibcon#flushed, iclass 21, count 2 2006.225.07:53:49.32#ibcon#about to write, iclass 21, count 2 2006.225.07:53:49.32#ibcon#wrote, iclass 21, count 2 2006.225.07:53:49.32#ibcon#about to read 3, iclass 21, count 2 2006.225.07:53:49.34#ibcon#read 3, iclass 21, count 2 2006.225.07:53:49.34#ibcon#about to read 4, iclass 21, count 2 2006.225.07:53:49.34#ibcon#read 4, iclass 21, count 2 2006.225.07:53:49.34#ibcon#about to read 5, iclass 21, count 2 2006.225.07:53:49.34#ibcon#read 5, iclass 21, count 2 2006.225.07:53:49.34#ibcon#about to read 6, iclass 21, count 2 2006.225.07:53:49.34#ibcon#read 6, iclass 21, count 2 2006.225.07:53:49.34#ibcon#end of sib2, iclass 21, count 2 2006.225.07:53:49.34#ibcon#*mode == 0, iclass 21, count 2 2006.225.07:53:49.34#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.225.07:53:49.34#ibcon#[25=AT05-07\r\n] 2006.225.07:53:49.34#ibcon#*before write, iclass 21, count 2 2006.225.07:53:49.34#ibcon#enter sib2, iclass 21, count 2 2006.225.07:53:49.34#ibcon#flushed, iclass 21, count 2 2006.225.07:53:49.34#ibcon#about to write, iclass 21, count 2 2006.225.07:53:49.34#ibcon#wrote, iclass 21, count 2 2006.225.07:53:49.34#ibcon#about to read 3, iclass 21, count 2 2006.225.07:53:49.37#ibcon#read 3, iclass 21, count 2 2006.225.07:53:49.37#ibcon#about to read 4, iclass 21, count 2 2006.225.07:53:49.37#ibcon#read 4, iclass 21, count 2 2006.225.07:53:49.37#ibcon#about to read 5, iclass 21, count 2 2006.225.07:53:49.37#ibcon#read 5, iclass 21, count 2 2006.225.07:53:49.37#ibcon#about to read 6, iclass 21, count 2 2006.225.07:53:49.37#ibcon#read 6, iclass 21, count 2 2006.225.07:53:49.37#ibcon#end of sib2, iclass 21, count 2 2006.225.07:53:49.37#ibcon#*after write, iclass 21, count 2 2006.225.07:53:49.37#ibcon#*before return 0, iclass 21, count 2 2006.225.07:53:49.37#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:53:49.37#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:53:49.37#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.225.07:53:49.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:49.37#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:53:49.39#abcon#<5=/06 2.8 5.1 28.35 711003.3\r\n> 2006.225.07:53:49.41#abcon#{5=INTERFACE CLEAR} 2006.225.07:53:49.47#abcon#[5=S1D000X0/0*\r\n] 2006.225.07:53:49.49#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:53:49.49#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:53:49.49#ibcon#enter wrdev, iclass 21, count 0 2006.225.07:53:49.49#ibcon#first serial, iclass 21, count 0 2006.225.07:53:49.49#ibcon#enter sib2, iclass 21, count 0 2006.225.07:53:49.49#ibcon#flushed, iclass 21, count 0 2006.225.07:53:49.49#ibcon#about to write, iclass 21, count 0 2006.225.07:53:49.49#ibcon#wrote, iclass 21, count 0 2006.225.07:53:49.49#ibcon#about to read 3, iclass 21, count 0 2006.225.07:53:49.51#ibcon#read 3, iclass 21, count 0 2006.225.07:53:49.51#ibcon#about to read 4, iclass 21, count 0 2006.225.07:53:49.51#ibcon#read 4, iclass 21, count 0 2006.225.07:53:49.51#ibcon#about to read 5, iclass 21, count 0 2006.225.07:53:49.51#ibcon#read 5, iclass 21, count 0 2006.225.07:53:49.51#ibcon#about to read 6, iclass 21, count 0 2006.225.07:53:49.51#ibcon#read 6, iclass 21, count 0 2006.225.07:53:49.51#ibcon#end of sib2, iclass 21, count 0 2006.225.07:53:49.51#ibcon#*mode == 0, iclass 21, count 0 2006.225.07:53:49.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.07:53:49.51#ibcon#[25=USB\r\n] 2006.225.07:53:49.51#ibcon#*before write, iclass 21, count 0 2006.225.07:53:49.51#ibcon#enter sib2, iclass 21, count 0 2006.225.07:53:49.51#ibcon#flushed, iclass 21, count 0 2006.225.07:53:49.51#ibcon#about to write, iclass 21, count 0 2006.225.07:53:49.51#ibcon#wrote, iclass 21, count 0 2006.225.07:53:49.51#ibcon#about to read 3, iclass 21, count 0 2006.225.07:53:49.54#ibcon#read 3, iclass 21, count 0 2006.225.07:53:49.54#ibcon#about to read 4, iclass 21, count 0 2006.225.07:53:49.54#ibcon#read 4, iclass 21, count 0 2006.225.07:53:49.54#ibcon#about to read 5, iclass 21, count 0 2006.225.07:53:49.54#ibcon#read 5, iclass 21, count 0 2006.225.07:53:49.54#ibcon#about to read 6, iclass 21, count 0 2006.225.07:53:49.54#ibcon#read 6, iclass 21, count 0 2006.225.07:53:49.54#ibcon#end of sib2, iclass 21, count 0 2006.225.07:53:49.54#ibcon#*after write, iclass 21, count 0 2006.225.07:53:49.54#ibcon#*before return 0, iclass 21, count 0 2006.225.07:53:49.54#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:53:49.54#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:53:49.54#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.07:53:49.54#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.07:53:49.54$vc4f8/valo=6,772.99 2006.225.07:53:49.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.07:53:49.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.07:53:49.54#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:49.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:53:49.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:53:49.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:53:49.54#ibcon#enter wrdev, iclass 27, count 0 2006.225.07:53:49.54#ibcon#first serial, iclass 27, count 0 2006.225.07:53:49.54#ibcon#enter sib2, iclass 27, count 0 2006.225.07:53:49.54#ibcon#flushed, iclass 27, count 0 2006.225.07:53:49.54#ibcon#about to write, iclass 27, count 0 2006.225.07:53:49.54#ibcon#wrote, iclass 27, count 0 2006.225.07:53:49.54#ibcon#about to read 3, iclass 27, count 0 2006.225.07:53:49.56#ibcon#read 3, iclass 27, count 0 2006.225.07:53:49.56#ibcon#about to read 4, iclass 27, count 0 2006.225.07:53:49.56#ibcon#read 4, iclass 27, count 0 2006.225.07:53:49.56#ibcon#about to read 5, iclass 27, count 0 2006.225.07:53:49.56#ibcon#read 5, iclass 27, count 0 2006.225.07:53:49.56#ibcon#about to read 6, iclass 27, count 0 2006.225.07:53:49.56#ibcon#read 6, iclass 27, count 0 2006.225.07:53:49.56#ibcon#end of sib2, iclass 27, count 0 2006.225.07:53:49.56#ibcon#*mode == 0, iclass 27, count 0 2006.225.07:53:49.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.07:53:49.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:53:49.56#ibcon#*before write, iclass 27, count 0 2006.225.07:53:49.56#ibcon#enter sib2, iclass 27, count 0 2006.225.07:53:49.56#ibcon#flushed, iclass 27, count 0 2006.225.07:53:49.56#ibcon#about to write, iclass 27, count 0 2006.225.07:53:49.56#ibcon#wrote, iclass 27, count 0 2006.225.07:53:49.56#ibcon#about to read 3, iclass 27, count 0 2006.225.07:53:49.60#ibcon#read 3, iclass 27, count 0 2006.225.07:53:49.60#ibcon#about to read 4, iclass 27, count 0 2006.225.07:53:49.60#ibcon#read 4, iclass 27, count 0 2006.225.07:53:49.60#ibcon#about to read 5, iclass 27, count 0 2006.225.07:53:49.60#ibcon#read 5, iclass 27, count 0 2006.225.07:53:49.60#ibcon#about to read 6, iclass 27, count 0 2006.225.07:53:49.60#ibcon#read 6, iclass 27, count 0 2006.225.07:53:49.60#ibcon#end of sib2, iclass 27, count 0 2006.225.07:53:49.60#ibcon#*after write, iclass 27, count 0 2006.225.07:53:49.60#ibcon#*before return 0, iclass 27, count 0 2006.225.07:53:49.60#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:53:49.60#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:53:49.60#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.07:53:49.60#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.07:53:49.60$vc4f8/va=6,6 2006.225.07:53:49.60#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.225.07:53:49.60#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.225.07:53:49.60#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:49.60#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:53:49.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:53:49.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:53:49.66#ibcon#enter wrdev, iclass 29, count 2 2006.225.07:53:49.66#ibcon#first serial, iclass 29, count 2 2006.225.07:53:49.66#ibcon#enter sib2, iclass 29, count 2 2006.225.07:53:49.66#ibcon#flushed, iclass 29, count 2 2006.225.07:53:49.66#ibcon#about to write, iclass 29, count 2 2006.225.07:53:49.66#ibcon#wrote, iclass 29, count 2 2006.225.07:53:49.66#ibcon#about to read 3, iclass 29, count 2 2006.225.07:53:49.68#ibcon#read 3, iclass 29, count 2 2006.225.07:53:49.68#ibcon#about to read 4, iclass 29, count 2 2006.225.07:53:49.68#ibcon#read 4, iclass 29, count 2 2006.225.07:53:49.68#ibcon#about to read 5, iclass 29, count 2 2006.225.07:53:49.68#ibcon#read 5, iclass 29, count 2 2006.225.07:53:49.68#ibcon#about to read 6, iclass 29, count 2 2006.225.07:53:49.68#ibcon#read 6, iclass 29, count 2 2006.225.07:53:49.68#ibcon#end of sib2, iclass 29, count 2 2006.225.07:53:49.68#ibcon#*mode == 0, iclass 29, count 2 2006.225.07:53:49.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.225.07:53:49.68#ibcon#[25=AT06-06\r\n] 2006.225.07:53:49.68#ibcon#*before write, iclass 29, count 2 2006.225.07:53:49.68#ibcon#enter sib2, iclass 29, count 2 2006.225.07:53:49.68#ibcon#flushed, iclass 29, count 2 2006.225.07:53:49.68#ibcon#about to write, iclass 29, count 2 2006.225.07:53:49.68#ibcon#wrote, iclass 29, count 2 2006.225.07:53:49.68#ibcon#about to read 3, iclass 29, count 2 2006.225.07:53:49.71#ibcon#read 3, iclass 29, count 2 2006.225.07:53:49.71#ibcon#about to read 4, iclass 29, count 2 2006.225.07:53:49.71#ibcon#read 4, iclass 29, count 2 2006.225.07:53:49.71#ibcon#about to read 5, iclass 29, count 2 2006.225.07:53:49.71#ibcon#read 5, iclass 29, count 2 2006.225.07:53:49.71#ibcon#about to read 6, iclass 29, count 2 2006.225.07:53:49.71#ibcon#read 6, iclass 29, count 2 2006.225.07:53:49.71#ibcon#end of sib2, iclass 29, count 2 2006.225.07:53:49.71#ibcon#*after write, iclass 29, count 2 2006.225.07:53:49.71#ibcon#*before return 0, iclass 29, count 2 2006.225.07:53:49.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:53:49.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.225.07:53:49.71#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.225.07:53:49.71#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:49.71#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:53:49.83#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:53:49.83#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:53:49.83#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:53:49.83#ibcon#first serial, iclass 29, count 0 2006.225.07:53:49.83#ibcon#enter sib2, iclass 29, count 0 2006.225.07:53:49.83#ibcon#flushed, iclass 29, count 0 2006.225.07:53:49.83#ibcon#about to write, iclass 29, count 0 2006.225.07:53:49.83#ibcon#wrote, iclass 29, count 0 2006.225.07:53:49.83#ibcon#about to read 3, iclass 29, count 0 2006.225.07:53:49.85#ibcon#read 3, iclass 29, count 0 2006.225.07:53:49.85#ibcon#about to read 4, iclass 29, count 0 2006.225.07:53:49.85#ibcon#read 4, iclass 29, count 0 2006.225.07:53:49.85#ibcon#about to read 5, iclass 29, count 0 2006.225.07:53:49.85#ibcon#read 5, iclass 29, count 0 2006.225.07:53:49.85#ibcon#about to read 6, iclass 29, count 0 2006.225.07:53:49.85#ibcon#read 6, iclass 29, count 0 2006.225.07:53:49.85#ibcon#end of sib2, iclass 29, count 0 2006.225.07:53:49.85#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:53:49.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:53:49.85#ibcon#[25=USB\r\n] 2006.225.07:53:49.85#ibcon#*before write, iclass 29, count 0 2006.225.07:53:49.85#ibcon#enter sib2, iclass 29, count 0 2006.225.07:53:49.85#ibcon#flushed, iclass 29, count 0 2006.225.07:53:49.85#ibcon#about to write, iclass 29, count 0 2006.225.07:53:49.85#ibcon#wrote, iclass 29, count 0 2006.225.07:53:49.85#ibcon#about to read 3, iclass 29, count 0 2006.225.07:53:49.88#ibcon#read 3, iclass 29, count 0 2006.225.07:53:49.88#ibcon#about to read 4, iclass 29, count 0 2006.225.07:53:49.88#ibcon#read 4, iclass 29, count 0 2006.225.07:53:49.88#ibcon#about to read 5, iclass 29, count 0 2006.225.07:53:49.88#ibcon#read 5, iclass 29, count 0 2006.225.07:53:49.88#ibcon#about to read 6, iclass 29, count 0 2006.225.07:53:49.88#ibcon#read 6, iclass 29, count 0 2006.225.07:53:49.88#ibcon#end of sib2, iclass 29, count 0 2006.225.07:53:49.88#ibcon#*after write, iclass 29, count 0 2006.225.07:53:49.88#ibcon#*before return 0, iclass 29, count 0 2006.225.07:53:49.88#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:53:49.88#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.225.07:53:49.88#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:53:49.88#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:53:49.88$vc4f8/valo=7,832.99 2006.225.07:53:49.88#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.07:53:49.88#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.07:53:49.88#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:49.88#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:53:49.88#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:53:49.88#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:53:49.88#ibcon#enter wrdev, iclass 31, count 0 2006.225.07:53:49.88#ibcon#first serial, iclass 31, count 0 2006.225.07:53:49.88#ibcon#enter sib2, iclass 31, count 0 2006.225.07:53:49.88#ibcon#flushed, iclass 31, count 0 2006.225.07:53:49.88#ibcon#about to write, iclass 31, count 0 2006.225.07:53:49.88#ibcon#wrote, iclass 31, count 0 2006.225.07:53:49.88#ibcon#about to read 3, iclass 31, count 0 2006.225.07:53:49.90#ibcon#read 3, iclass 31, count 0 2006.225.07:53:49.90#ibcon#about to read 4, iclass 31, count 0 2006.225.07:53:49.90#ibcon#read 4, iclass 31, count 0 2006.225.07:53:49.90#ibcon#about to read 5, iclass 31, count 0 2006.225.07:53:49.90#ibcon#read 5, iclass 31, count 0 2006.225.07:53:49.90#ibcon#about to read 6, iclass 31, count 0 2006.225.07:53:49.90#ibcon#read 6, iclass 31, count 0 2006.225.07:53:49.90#ibcon#end of sib2, iclass 31, count 0 2006.225.07:53:49.90#ibcon#*mode == 0, iclass 31, count 0 2006.225.07:53:49.90#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.07:53:49.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:53:49.90#ibcon#*before write, iclass 31, count 0 2006.225.07:53:49.90#ibcon#enter sib2, iclass 31, count 0 2006.225.07:53:49.90#ibcon#flushed, iclass 31, count 0 2006.225.07:53:49.90#ibcon#about to write, iclass 31, count 0 2006.225.07:53:49.90#ibcon#wrote, iclass 31, count 0 2006.225.07:53:49.90#ibcon#about to read 3, iclass 31, count 0 2006.225.07:53:49.94#ibcon#read 3, iclass 31, count 0 2006.225.07:53:49.94#ibcon#about to read 4, iclass 31, count 0 2006.225.07:53:49.94#ibcon#read 4, iclass 31, count 0 2006.225.07:53:49.94#ibcon#about to read 5, iclass 31, count 0 2006.225.07:53:49.94#ibcon#read 5, iclass 31, count 0 2006.225.07:53:49.94#ibcon#about to read 6, iclass 31, count 0 2006.225.07:53:49.94#ibcon#read 6, iclass 31, count 0 2006.225.07:53:49.94#ibcon#end of sib2, iclass 31, count 0 2006.225.07:53:49.94#ibcon#*after write, iclass 31, count 0 2006.225.07:53:49.94#ibcon#*before return 0, iclass 31, count 0 2006.225.07:53:49.94#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:53:49.94#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.07:53:49.94#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.07:53:49.94#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.07:53:49.94$vc4f8/va=7,6 2006.225.07:53:49.94#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.225.07:53:49.94#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.225.07:53:49.94#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:49.94#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:53:50.00#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:53:50.00#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:53:50.00#ibcon#enter wrdev, iclass 33, count 2 2006.225.07:53:50.00#ibcon#first serial, iclass 33, count 2 2006.225.07:53:50.00#ibcon#enter sib2, iclass 33, count 2 2006.225.07:53:50.00#ibcon#flushed, iclass 33, count 2 2006.225.07:53:50.00#ibcon#about to write, iclass 33, count 2 2006.225.07:53:50.00#ibcon#wrote, iclass 33, count 2 2006.225.07:53:50.00#ibcon#about to read 3, iclass 33, count 2 2006.225.07:53:50.02#ibcon#read 3, iclass 33, count 2 2006.225.07:53:50.02#ibcon#about to read 4, iclass 33, count 2 2006.225.07:53:50.02#ibcon#read 4, iclass 33, count 2 2006.225.07:53:50.02#ibcon#about to read 5, iclass 33, count 2 2006.225.07:53:50.02#ibcon#read 5, iclass 33, count 2 2006.225.07:53:50.02#ibcon#about to read 6, iclass 33, count 2 2006.225.07:53:50.02#ibcon#read 6, iclass 33, count 2 2006.225.07:53:50.02#ibcon#end of sib2, iclass 33, count 2 2006.225.07:53:50.02#ibcon#*mode == 0, iclass 33, count 2 2006.225.07:53:50.02#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.225.07:53:50.02#ibcon#[25=AT07-06\r\n] 2006.225.07:53:50.02#ibcon#*before write, iclass 33, count 2 2006.225.07:53:50.02#ibcon#enter sib2, iclass 33, count 2 2006.225.07:53:50.02#ibcon#flushed, iclass 33, count 2 2006.225.07:53:50.02#ibcon#about to write, iclass 33, count 2 2006.225.07:53:50.02#ibcon#wrote, iclass 33, count 2 2006.225.07:53:50.02#ibcon#about to read 3, iclass 33, count 2 2006.225.07:53:50.05#ibcon#read 3, iclass 33, count 2 2006.225.07:53:50.05#ibcon#about to read 4, iclass 33, count 2 2006.225.07:53:50.05#ibcon#read 4, iclass 33, count 2 2006.225.07:53:50.05#ibcon#about to read 5, iclass 33, count 2 2006.225.07:53:50.05#ibcon#read 5, iclass 33, count 2 2006.225.07:53:50.05#ibcon#about to read 6, iclass 33, count 2 2006.225.07:53:50.05#ibcon#read 6, iclass 33, count 2 2006.225.07:53:50.05#ibcon#end of sib2, iclass 33, count 2 2006.225.07:53:50.05#ibcon#*after write, iclass 33, count 2 2006.225.07:53:50.05#ibcon#*before return 0, iclass 33, count 2 2006.225.07:53:50.05#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:53:50.05#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.225.07:53:50.05#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.225.07:53:50.05#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:50.05#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:53:50.17#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:53:50.17#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:53:50.17#ibcon#enter wrdev, iclass 33, count 0 2006.225.07:53:50.17#ibcon#first serial, iclass 33, count 0 2006.225.07:53:50.17#ibcon#enter sib2, iclass 33, count 0 2006.225.07:53:50.17#ibcon#flushed, iclass 33, count 0 2006.225.07:53:50.17#ibcon#about to write, iclass 33, count 0 2006.225.07:53:50.17#ibcon#wrote, iclass 33, count 0 2006.225.07:53:50.17#ibcon#about to read 3, iclass 33, count 0 2006.225.07:53:50.19#ibcon#read 3, iclass 33, count 0 2006.225.07:53:50.19#ibcon#about to read 4, iclass 33, count 0 2006.225.07:53:50.19#ibcon#read 4, iclass 33, count 0 2006.225.07:53:50.19#ibcon#about to read 5, iclass 33, count 0 2006.225.07:53:50.19#ibcon#read 5, iclass 33, count 0 2006.225.07:53:50.19#ibcon#about to read 6, iclass 33, count 0 2006.225.07:53:50.19#ibcon#read 6, iclass 33, count 0 2006.225.07:53:50.19#ibcon#end of sib2, iclass 33, count 0 2006.225.07:53:50.19#ibcon#*mode == 0, iclass 33, count 0 2006.225.07:53:50.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.07:53:50.19#ibcon#[25=USB\r\n] 2006.225.07:53:50.19#ibcon#*before write, iclass 33, count 0 2006.225.07:53:50.19#ibcon#enter sib2, iclass 33, count 0 2006.225.07:53:50.19#ibcon#flushed, iclass 33, count 0 2006.225.07:53:50.19#ibcon#about to write, iclass 33, count 0 2006.225.07:53:50.19#ibcon#wrote, iclass 33, count 0 2006.225.07:53:50.19#ibcon#about to read 3, iclass 33, count 0 2006.225.07:53:50.22#ibcon#read 3, iclass 33, count 0 2006.225.07:53:50.22#ibcon#about to read 4, iclass 33, count 0 2006.225.07:53:50.22#ibcon#read 4, iclass 33, count 0 2006.225.07:53:50.22#ibcon#about to read 5, iclass 33, count 0 2006.225.07:53:50.22#ibcon#read 5, iclass 33, count 0 2006.225.07:53:50.22#ibcon#about to read 6, iclass 33, count 0 2006.225.07:53:50.22#ibcon#read 6, iclass 33, count 0 2006.225.07:53:50.22#ibcon#end of sib2, iclass 33, count 0 2006.225.07:53:50.22#ibcon#*after write, iclass 33, count 0 2006.225.07:53:50.22#ibcon#*before return 0, iclass 33, count 0 2006.225.07:53:50.22#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:53:50.22#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.225.07:53:50.22#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.07:53:50.22#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.07:53:50.22$vc4f8/valo=8,852.99 2006.225.07:53:50.22#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.225.07:53:50.22#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.225.07:53:50.22#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:50.22#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:53:50.22#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:53:50.22#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:53:50.22#ibcon#enter wrdev, iclass 35, count 0 2006.225.07:53:50.22#ibcon#first serial, iclass 35, count 0 2006.225.07:53:50.22#ibcon#enter sib2, iclass 35, count 0 2006.225.07:53:50.22#ibcon#flushed, iclass 35, count 0 2006.225.07:53:50.22#ibcon#about to write, iclass 35, count 0 2006.225.07:53:50.22#ibcon#wrote, iclass 35, count 0 2006.225.07:53:50.22#ibcon#about to read 3, iclass 35, count 0 2006.225.07:53:50.24#ibcon#read 3, iclass 35, count 0 2006.225.07:53:50.24#ibcon#about to read 4, iclass 35, count 0 2006.225.07:53:50.24#ibcon#read 4, iclass 35, count 0 2006.225.07:53:50.24#ibcon#about to read 5, iclass 35, count 0 2006.225.07:53:50.24#ibcon#read 5, iclass 35, count 0 2006.225.07:53:50.24#ibcon#about to read 6, iclass 35, count 0 2006.225.07:53:50.24#ibcon#read 6, iclass 35, count 0 2006.225.07:53:50.24#ibcon#end of sib2, iclass 35, count 0 2006.225.07:53:50.24#ibcon#*mode == 0, iclass 35, count 0 2006.225.07:53:50.24#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.07:53:50.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:53:50.24#ibcon#*before write, iclass 35, count 0 2006.225.07:53:50.24#ibcon#enter sib2, iclass 35, count 0 2006.225.07:53:50.24#ibcon#flushed, iclass 35, count 0 2006.225.07:53:50.24#ibcon#about to write, iclass 35, count 0 2006.225.07:53:50.24#ibcon#wrote, iclass 35, count 0 2006.225.07:53:50.24#ibcon#about to read 3, iclass 35, count 0 2006.225.07:53:50.28#ibcon#read 3, iclass 35, count 0 2006.225.07:53:50.28#ibcon#about to read 4, iclass 35, count 0 2006.225.07:53:50.28#ibcon#read 4, iclass 35, count 0 2006.225.07:53:50.28#ibcon#about to read 5, iclass 35, count 0 2006.225.07:53:50.28#ibcon#read 5, iclass 35, count 0 2006.225.07:53:50.28#ibcon#about to read 6, iclass 35, count 0 2006.225.07:53:50.28#ibcon#read 6, iclass 35, count 0 2006.225.07:53:50.28#ibcon#end of sib2, iclass 35, count 0 2006.225.07:53:50.28#ibcon#*after write, iclass 35, count 0 2006.225.07:53:50.28#ibcon#*before return 0, iclass 35, count 0 2006.225.07:53:50.28#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:53:50.28#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.225.07:53:50.28#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.07:53:50.28#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.07:53:50.28$vc4f8/va=8,7 2006.225.07:53:50.28#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.225.07:53:50.28#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.225.07:53:50.28#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:50.28#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:53:50.34#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:53:50.34#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:53:50.34#ibcon#enter wrdev, iclass 37, count 2 2006.225.07:53:50.34#ibcon#first serial, iclass 37, count 2 2006.225.07:53:50.34#ibcon#enter sib2, iclass 37, count 2 2006.225.07:53:50.34#ibcon#flushed, iclass 37, count 2 2006.225.07:53:50.34#ibcon#about to write, iclass 37, count 2 2006.225.07:53:50.34#ibcon#wrote, iclass 37, count 2 2006.225.07:53:50.34#ibcon#about to read 3, iclass 37, count 2 2006.225.07:53:50.36#ibcon#read 3, iclass 37, count 2 2006.225.07:53:50.36#ibcon#about to read 4, iclass 37, count 2 2006.225.07:53:50.36#ibcon#read 4, iclass 37, count 2 2006.225.07:53:50.36#ibcon#about to read 5, iclass 37, count 2 2006.225.07:53:50.36#ibcon#read 5, iclass 37, count 2 2006.225.07:53:50.36#ibcon#about to read 6, iclass 37, count 2 2006.225.07:53:50.36#ibcon#read 6, iclass 37, count 2 2006.225.07:53:50.36#ibcon#end of sib2, iclass 37, count 2 2006.225.07:53:50.36#ibcon#*mode == 0, iclass 37, count 2 2006.225.07:53:50.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.225.07:53:50.36#ibcon#[25=AT08-07\r\n] 2006.225.07:53:50.36#ibcon#*before write, iclass 37, count 2 2006.225.07:53:50.36#ibcon#enter sib2, iclass 37, count 2 2006.225.07:53:50.36#ibcon#flushed, iclass 37, count 2 2006.225.07:53:50.36#ibcon#about to write, iclass 37, count 2 2006.225.07:53:50.36#ibcon#wrote, iclass 37, count 2 2006.225.07:53:50.36#ibcon#about to read 3, iclass 37, count 2 2006.225.07:53:50.39#ibcon#read 3, iclass 37, count 2 2006.225.07:53:50.39#ibcon#about to read 4, iclass 37, count 2 2006.225.07:53:50.39#ibcon#read 4, iclass 37, count 2 2006.225.07:53:50.39#ibcon#about to read 5, iclass 37, count 2 2006.225.07:53:50.39#ibcon#read 5, iclass 37, count 2 2006.225.07:53:50.39#ibcon#about to read 6, iclass 37, count 2 2006.225.07:53:50.39#ibcon#read 6, iclass 37, count 2 2006.225.07:53:50.39#ibcon#end of sib2, iclass 37, count 2 2006.225.07:53:50.39#ibcon#*after write, iclass 37, count 2 2006.225.07:53:50.39#ibcon#*before return 0, iclass 37, count 2 2006.225.07:53:50.39#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:53:50.39#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.225.07:53:50.39#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.225.07:53:50.39#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:50.39#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:53:50.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:53:50.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:53:50.51#ibcon#enter wrdev, iclass 37, count 0 2006.225.07:53:50.51#ibcon#first serial, iclass 37, count 0 2006.225.07:53:50.51#ibcon#enter sib2, iclass 37, count 0 2006.225.07:53:50.51#ibcon#flushed, iclass 37, count 0 2006.225.07:53:50.51#ibcon#about to write, iclass 37, count 0 2006.225.07:53:50.51#ibcon#wrote, iclass 37, count 0 2006.225.07:53:50.51#ibcon#about to read 3, iclass 37, count 0 2006.225.07:53:50.53#ibcon#read 3, iclass 37, count 0 2006.225.07:53:50.53#ibcon#about to read 4, iclass 37, count 0 2006.225.07:53:50.53#ibcon#read 4, iclass 37, count 0 2006.225.07:53:50.53#ibcon#about to read 5, iclass 37, count 0 2006.225.07:53:50.53#ibcon#read 5, iclass 37, count 0 2006.225.07:53:50.53#ibcon#about to read 6, iclass 37, count 0 2006.225.07:53:50.53#ibcon#read 6, iclass 37, count 0 2006.225.07:53:50.53#ibcon#end of sib2, iclass 37, count 0 2006.225.07:53:50.53#ibcon#*mode == 0, iclass 37, count 0 2006.225.07:53:50.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.07:53:50.53#ibcon#[25=USB\r\n] 2006.225.07:53:50.53#ibcon#*before write, iclass 37, count 0 2006.225.07:53:50.53#ibcon#enter sib2, iclass 37, count 0 2006.225.07:53:50.53#ibcon#flushed, iclass 37, count 0 2006.225.07:53:50.53#ibcon#about to write, iclass 37, count 0 2006.225.07:53:50.53#ibcon#wrote, iclass 37, count 0 2006.225.07:53:50.53#ibcon#about to read 3, iclass 37, count 0 2006.225.07:53:50.56#ibcon#read 3, iclass 37, count 0 2006.225.07:53:50.56#ibcon#about to read 4, iclass 37, count 0 2006.225.07:53:50.56#ibcon#read 4, iclass 37, count 0 2006.225.07:53:50.56#ibcon#about to read 5, iclass 37, count 0 2006.225.07:53:50.56#ibcon#read 5, iclass 37, count 0 2006.225.07:53:50.56#ibcon#about to read 6, iclass 37, count 0 2006.225.07:53:50.56#ibcon#read 6, iclass 37, count 0 2006.225.07:53:50.56#ibcon#end of sib2, iclass 37, count 0 2006.225.07:53:50.56#ibcon#*after write, iclass 37, count 0 2006.225.07:53:50.56#ibcon#*before return 0, iclass 37, count 0 2006.225.07:53:50.56#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:53:50.56#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.225.07:53:50.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.07:53:50.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.07:53:50.56$vc4f8/vblo=1,632.99 2006.225.07:53:50.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.07:53:50.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.07:53:50.56#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:50.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:53:50.56#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:53:50.56#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:53:50.56#ibcon#enter wrdev, iclass 39, count 0 2006.225.07:53:50.56#ibcon#first serial, iclass 39, count 0 2006.225.07:53:50.56#ibcon#enter sib2, iclass 39, count 0 2006.225.07:53:50.56#ibcon#flushed, iclass 39, count 0 2006.225.07:53:50.56#ibcon#about to write, iclass 39, count 0 2006.225.07:53:50.56#ibcon#wrote, iclass 39, count 0 2006.225.07:53:50.56#ibcon#about to read 3, iclass 39, count 0 2006.225.07:53:50.58#ibcon#read 3, iclass 39, count 0 2006.225.07:53:50.58#ibcon#about to read 4, iclass 39, count 0 2006.225.07:53:50.58#ibcon#read 4, iclass 39, count 0 2006.225.07:53:50.58#ibcon#about to read 5, iclass 39, count 0 2006.225.07:53:50.58#ibcon#read 5, iclass 39, count 0 2006.225.07:53:50.58#ibcon#about to read 6, iclass 39, count 0 2006.225.07:53:50.58#ibcon#read 6, iclass 39, count 0 2006.225.07:53:50.58#ibcon#end of sib2, iclass 39, count 0 2006.225.07:53:50.58#ibcon#*mode == 0, iclass 39, count 0 2006.225.07:53:50.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.07:53:50.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:53:50.58#ibcon#*before write, iclass 39, count 0 2006.225.07:53:50.58#ibcon#enter sib2, iclass 39, count 0 2006.225.07:53:50.58#ibcon#flushed, iclass 39, count 0 2006.225.07:53:50.58#ibcon#about to write, iclass 39, count 0 2006.225.07:53:50.58#ibcon#wrote, iclass 39, count 0 2006.225.07:53:50.58#ibcon#about to read 3, iclass 39, count 0 2006.225.07:53:50.62#ibcon#read 3, iclass 39, count 0 2006.225.07:53:50.62#ibcon#about to read 4, iclass 39, count 0 2006.225.07:53:50.62#ibcon#read 4, iclass 39, count 0 2006.225.07:53:50.62#ibcon#about to read 5, iclass 39, count 0 2006.225.07:53:50.62#ibcon#read 5, iclass 39, count 0 2006.225.07:53:50.62#ibcon#about to read 6, iclass 39, count 0 2006.225.07:53:50.62#ibcon#read 6, iclass 39, count 0 2006.225.07:53:50.62#ibcon#end of sib2, iclass 39, count 0 2006.225.07:53:50.62#ibcon#*after write, iclass 39, count 0 2006.225.07:53:50.62#ibcon#*before return 0, iclass 39, count 0 2006.225.07:53:50.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:53:50.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.07:53:50.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.07:53:50.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.07:53:50.62$vc4f8/vb=1,4 2006.225.07:53:50.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.07:53:50.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.07:53:50.62#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:50.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:53:50.62#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:53:50.62#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:53:50.62#ibcon#enter wrdev, iclass 3, count 2 2006.225.07:53:50.62#ibcon#first serial, iclass 3, count 2 2006.225.07:53:50.62#ibcon#enter sib2, iclass 3, count 2 2006.225.07:53:50.62#ibcon#flushed, iclass 3, count 2 2006.225.07:53:50.62#ibcon#about to write, iclass 3, count 2 2006.225.07:53:50.62#ibcon#wrote, iclass 3, count 2 2006.225.07:53:50.62#ibcon#about to read 3, iclass 3, count 2 2006.225.07:53:50.64#ibcon#read 3, iclass 3, count 2 2006.225.07:53:50.64#ibcon#about to read 4, iclass 3, count 2 2006.225.07:53:50.64#ibcon#read 4, iclass 3, count 2 2006.225.07:53:50.64#ibcon#about to read 5, iclass 3, count 2 2006.225.07:53:50.64#ibcon#read 5, iclass 3, count 2 2006.225.07:53:50.64#ibcon#about to read 6, iclass 3, count 2 2006.225.07:53:50.64#ibcon#read 6, iclass 3, count 2 2006.225.07:53:50.64#ibcon#end of sib2, iclass 3, count 2 2006.225.07:53:50.64#ibcon#*mode == 0, iclass 3, count 2 2006.225.07:53:50.64#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.07:53:50.64#ibcon#[27=AT01-04\r\n] 2006.225.07:53:50.64#ibcon#*before write, iclass 3, count 2 2006.225.07:53:50.64#ibcon#enter sib2, iclass 3, count 2 2006.225.07:53:50.64#ibcon#flushed, iclass 3, count 2 2006.225.07:53:50.64#ibcon#about to write, iclass 3, count 2 2006.225.07:53:50.64#ibcon#wrote, iclass 3, count 2 2006.225.07:53:50.64#ibcon#about to read 3, iclass 3, count 2 2006.225.07:53:50.67#ibcon#read 3, iclass 3, count 2 2006.225.07:53:50.67#ibcon#about to read 4, iclass 3, count 2 2006.225.07:53:50.67#ibcon#read 4, iclass 3, count 2 2006.225.07:53:50.67#ibcon#about to read 5, iclass 3, count 2 2006.225.07:53:50.67#ibcon#read 5, iclass 3, count 2 2006.225.07:53:50.67#ibcon#about to read 6, iclass 3, count 2 2006.225.07:53:50.67#ibcon#read 6, iclass 3, count 2 2006.225.07:53:50.67#ibcon#end of sib2, iclass 3, count 2 2006.225.07:53:50.67#ibcon#*after write, iclass 3, count 2 2006.225.07:53:50.67#ibcon#*before return 0, iclass 3, count 2 2006.225.07:53:50.67#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:53:50.67#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.07:53:50.67#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.07:53:50.67#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:50.67#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:53:50.79#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:53:50.79#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:53:50.79#ibcon#enter wrdev, iclass 3, count 0 2006.225.07:53:50.79#ibcon#first serial, iclass 3, count 0 2006.225.07:53:50.79#ibcon#enter sib2, iclass 3, count 0 2006.225.07:53:50.79#ibcon#flushed, iclass 3, count 0 2006.225.07:53:50.79#ibcon#about to write, iclass 3, count 0 2006.225.07:53:50.79#ibcon#wrote, iclass 3, count 0 2006.225.07:53:50.79#ibcon#about to read 3, iclass 3, count 0 2006.225.07:53:50.81#ibcon#read 3, iclass 3, count 0 2006.225.07:53:50.81#ibcon#about to read 4, iclass 3, count 0 2006.225.07:53:50.81#ibcon#read 4, iclass 3, count 0 2006.225.07:53:50.81#ibcon#about to read 5, iclass 3, count 0 2006.225.07:53:50.81#ibcon#read 5, iclass 3, count 0 2006.225.07:53:50.81#ibcon#about to read 6, iclass 3, count 0 2006.225.07:53:50.81#ibcon#read 6, iclass 3, count 0 2006.225.07:53:50.81#ibcon#end of sib2, iclass 3, count 0 2006.225.07:53:50.81#ibcon#*mode == 0, iclass 3, count 0 2006.225.07:53:50.81#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.07:53:50.81#ibcon#[27=USB\r\n] 2006.225.07:53:50.81#ibcon#*before write, iclass 3, count 0 2006.225.07:53:50.81#ibcon#enter sib2, iclass 3, count 0 2006.225.07:53:50.81#ibcon#flushed, iclass 3, count 0 2006.225.07:53:50.81#ibcon#about to write, iclass 3, count 0 2006.225.07:53:50.81#ibcon#wrote, iclass 3, count 0 2006.225.07:53:50.81#ibcon#about to read 3, iclass 3, count 0 2006.225.07:53:50.84#ibcon#read 3, iclass 3, count 0 2006.225.07:53:50.84#ibcon#about to read 4, iclass 3, count 0 2006.225.07:53:50.84#ibcon#read 4, iclass 3, count 0 2006.225.07:53:50.84#ibcon#about to read 5, iclass 3, count 0 2006.225.07:53:50.84#ibcon#read 5, iclass 3, count 0 2006.225.07:53:50.84#ibcon#about to read 6, iclass 3, count 0 2006.225.07:53:50.84#ibcon#read 6, iclass 3, count 0 2006.225.07:53:50.84#ibcon#end of sib2, iclass 3, count 0 2006.225.07:53:50.84#ibcon#*after write, iclass 3, count 0 2006.225.07:53:50.84#ibcon#*before return 0, iclass 3, count 0 2006.225.07:53:50.84#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:53:50.84#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.07:53:50.84#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.07:53:50.84#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.07:53:50.84$vc4f8/vblo=2,640.99 2006.225.07:53:50.84#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.07:53:50.84#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.07:53:50.84#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:50.84#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:53:50.84#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:53:50.84#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:53:50.84#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:53:50.84#ibcon#first serial, iclass 5, count 0 2006.225.07:53:50.84#ibcon#enter sib2, iclass 5, count 0 2006.225.07:53:50.84#ibcon#flushed, iclass 5, count 0 2006.225.07:53:50.84#ibcon#about to write, iclass 5, count 0 2006.225.07:53:50.84#ibcon#wrote, iclass 5, count 0 2006.225.07:53:50.84#ibcon#about to read 3, iclass 5, count 0 2006.225.07:53:50.86#ibcon#read 3, iclass 5, count 0 2006.225.07:53:50.86#ibcon#about to read 4, iclass 5, count 0 2006.225.07:53:50.86#ibcon#read 4, iclass 5, count 0 2006.225.07:53:50.86#ibcon#about to read 5, iclass 5, count 0 2006.225.07:53:50.86#ibcon#read 5, iclass 5, count 0 2006.225.07:53:50.86#ibcon#about to read 6, iclass 5, count 0 2006.225.07:53:50.86#ibcon#read 6, iclass 5, count 0 2006.225.07:53:50.86#ibcon#end of sib2, iclass 5, count 0 2006.225.07:53:50.86#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:53:50.86#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:53:50.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:53:50.86#ibcon#*before write, iclass 5, count 0 2006.225.07:53:50.86#ibcon#enter sib2, iclass 5, count 0 2006.225.07:53:50.86#ibcon#flushed, iclass 5, count 0 2006.225.07:53:50.86#ibcon#about to write, iclass 5, count 0 2006.225.07:53:50.86#ibcon#wrote, iclass 5, count 0 2006.225.07:53:50.86#ibcon#about to read 3, iclass 5, count 0 2006.225.07:53:50.90#ibcon#read 3, iclass 5, count 0 2006.225.07:53:50.90#ibcon#about to read 4, iclass 5, count 0 2006.225.07:53:50.90#ibcon#read 4, iclass 5, count 0 2006.225.07:53:50.90#ibcon#about to read 5, iclass 5, count 0 2006.225.07:53:50.90#ibcon#read 5, iclass 5, count 0 2006.225.07:53:50.90#ibcon#about to read 6, iclass 5, count 0 2006.225.07:53:50.90#ibcon#read 6, iclass 5, count 0 2006.225.07:53:50.90#ibcon#end of sib2, iclass 5, count 0 2006.225.07:53:50.90#ibcon#*after write, iclass 5, count 0 2006.225.07:53:50.90#ibcon#*before return 0, iclass 5, count 0 2006.225.07:53:50.90#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:53:50.90#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.07:53:50.90#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:53:50.90#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:53:50.90$vc4f8/vb=2,4 2006.225.07:53:50.90#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.07:53:50.90#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.07:53:50.90#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:50.90#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:53:50.96#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:53:50.96#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:53:50.96#ibcon#enter wrdev, iclass 7, count 2 2006.225.07:53:50.96#ibcon#first serial, iclass 7, count 2 2006.225.07:53:50.96#ibcon#enter sib2, iclass 7, count 2 2006.225.07:53:50.96#ibcon#flushed, iclass 7, count 2 2006.225.07:53:50.96#ibcon#about to write, iclass 7, count 2 2006.225.07:53:50.96#ibcon#wrote, iclass 7, count 2 2006.225.07:53:50.96#ibcon#about to read 3, iclass 7, count 2 2006.225.07:53:50.98#ibcon#read 3, iclass 7, count 2 2006.225.07:53:50.98#ibcon#about to read 4, iclass 7, count 2 2006.225.07:53:50.98#ibcon#read 4, iclass 7, count 2 2006.225.07:53:50.98#ibcon#about to read 5, iclass 7, count 2 2006.225.07:53:50.98#ibcon#read 5, iclass 7, count 2 2006.225.07:53:50.98#ibcon#about to read 6, iclass 7, count 2 2006.225.07:53:50.98#ibcon#read 6, iclass 7, count 2 2006.225.07:53:50.98#ibcon#end of sib2, iclass 7, count 2 2006.225.07:53:50.98#ibcon#*mode == 0, iclass 7, count 2 2006.225.07:53:50.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.07:53:50.98#ibcon#[27=AT02-04\r\n] 2006.225.07:53:50.98#ibcon#*before write, iclass 7, count 2 2006.225.07:53:50.98#ibcon#enter sib2, iclass 7, count 2 2006.225.07:53:50.98#ibcon#flushed, iclass 7, count 2 2006.225.07:53:50.98#ibcon#about to write, iclass 7, count 2 2006.225.07:53:50.98#ibcon#wrote, iclass 7, count 2 2006.225.07:53:50.98#ibcon#about to read 3, iclass 7, count 2 2006.225.07:53:51.01#ibcon#read 3, iclass 7, count 2 2006.225.07:53:51.01#ibcon#about to read 4, iclass 7, count 2 2006.225.07:53:51.01#ibcon#read 4, iclass 7, count 2 2006.225.07:53:51.01#ibcon#about to read 5, iclass 7, count 2 2006.225.07:53:51.01#ibcon#read 5, iclass 7, count 2 2006.225.07:53:51.01#ibcon#about to read 6, iclass 7, count 2 2006.225.07:53:51.01#ibcon#read 6, iclass 7, count 2 2006.225.07:53:51.01#ibcon#end of sib2, iclass 7, count 2 2006.225.07:53:51.01#ibcon#*after write, iclass 7, count 2 2006.225.07:53:51.01#ibcon#*before return 0, iclass 7, count 2 2006.225.07:53:51.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:53:51.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.07:53:51.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.07:53:51.01#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:51.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:53:51.13#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:53:51.13#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:53:51.13#ibcon#enter wrdev, iclass 7, count 0 2006.225.07:53:51.13#ibcon#first serial, iclass 7, count 0 2006.225.07:53:51.13#ibcon#enter sib2, iclass 7, count 0 2006.225.07:53:51.13#ibcon#flushed, iclass 7, count 0 2006.225.07:53:51.13#ibcon#about to write, iclass 7, count 0 2006.225.07:53:51.13#ibcon#wrote, iclass 7, count 0 2006.225.07:53:51.13#ibcon#about to read 3, iclass 7, count 0 2006.225.07:53:51.15#ibcon#read 3, iclass 7, count 0 2006.225.07:53:51.15#ibcon#about to read 4, iclass 7, count 0 2006.225.07:53:51.15#ibcon#read 4, iclass 7, count 0 2006.225.07:53:51.15#ibcon#about to read 5, iclass 7, count 0 2006.225.07:53:51.15#ibcon#read 5, iclass 7, count 0 2006.225.07:53:51.15#ibcon#about to read 6, iclass 7, count 0 2006.225.07:53:51.15#ibcon#read 6, iclass 7, count 0 2006.225.07:53:51.15#ibcon#end of sib2, iclass 7, count 0 2006.225.07:53:51.15#ibcon#*mode == 0, iclass 7, count 0 2006.225.07:53:51.15#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.07:53:51.15#ibcon#[27=USB\r\n] 2006.225.07:53:51.15#ibcon#*before write, iclass 7, count 0 2006.225.07:53:51.15#ibcon#enter sib2, iclass 7, count 0 2006.225.07:53:51.15#ibcon#flushed, iclass 7, count 0 2006.225.07:53:51.15#ibcon#about to write, iclass 7, count 0 2006.225.07:53:51.15#ibcon#wrote, iclass 7, count 0 2006.225.07:53:51.15#ibcon#about to read 3, iclass 7, count 0 2006.225.07:53:51.18#ibcon#read 3, iclass 7, count 0 2006.225.07:53:51.18#ibcon#about to read 4, iclass 7, count 0 2006.225.07:53:51.18#ibcon#read 4, iclass 7, count 0 2006.225.07:53:51.18#ibcon#about to read 5, iclass 7, count 0 2006.225.07:53:51.18#ibcon#read 5, iclass 7, count 0 2006.225.07:53:51.18#ibcon#about to read 6, iclass 7, count 0 2006.225.07:53:51.18#ibcon#read 6, iclass 7, count 0 2006.225.07:53:51.18#ibcon#end of sib2, iclass 7, count 0 2006.225.07:53:51.18#ibcon#*after write, iclass 7, count 0 2006.225.07:53:51.18#ibcon#*before return 0, iclass 7, count 0 2006.225.07:53:51.18#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:53:51.18#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.07:53:51.18#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.07:53:51.18#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.07:53:51.18$vc4f8/vblo=3,656.99 2006.225.07:53:51.18#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.07:53:51.18#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.07:53:51.18#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:51.18#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:53:51.18#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:53:51.18#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:53:51.18#ibcon#enter wrdev, iclass 11, count 0 2006.225.07:53:51.18#ibcon#first serial, iclass 11, count 0 2006.225.07:53:51.18#ibcon#enter sib2, iclass 11, count 0 2006.225.07:53:51.18#ibcon#flushed, iclass 11, count 0 2006.225.07:53:51.18#ibcon#about to write, iclass 11, count 0 2006.225.07:53:51.18#ibcon#wrote, iclass 11, count 0 2006.225.07:53:51.18#ibcon#about to read 3, iclass 11, count 0 2006.225.07:53:51.20#ibcon#read 3, iclass 11, count 0 2006.225.07:53:51.20#ibcon#about to read 4, iclass 11, count 0 2006.225.07:53:51.20#ibcon#read 4, iclass 11, count 0 2006.225.07:53:51.20#ibcon#about to read 5, iclass 11, count 0 2006.225.07:53:51.20#ibcon#read 5, iclass 11, count 0 2006.225.07:53:51.20#ibcon#about to read 6, iclass 11, count 0 2006.225.07:53:51.20#ibcon#read 6, iclass 11, count 0 2006.225.07:53:51.20#ibcon#end of sib2, iclass 11, count 0 2006.225.07:53:51.20#ibcon#*mode == 0, iclass 11, count 0 2006.225.07:53:51.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.07:53:51.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:53:51.20#ibcon#*before write, iclass 11, count 0 2006.225.07:53:51.20#ibcon#enter sib2, iclass 11, count 0 2006.225.07:53:51.20#ibcon#flushed, iclass 11, count 0 2006.225.07:53:51.20#ibcon#about to write, iclass 11, count 0 2006.225.07:53:51.20#ibcon#wrote, iclass 11, count 0 2006.225.07:53:51.20#ibcon#about to read 3, iclass 11, count 0 2006.225.07:53:51.24#ibcon#read 3, iclass 11, count 0 2006.225.07:53:51.24#ibcon#about to read 4, iclass 11, count 0 2006.225.07:53:51.24#ibcon#read 4, iclass 11, count 0 2006.225.07:53:51.24#ibcon#about to read 5, iclass 11, count 0 2006.225.07:53:51.24#ibcon#read 5, iclass 11, count 0 2006.225.07:53:51.24#ibcon#about to read 6, iclass 11, count 0 2006.225.07:53:51.24#ibcon#read 6, iclass 11, count 0 2006.225.07:53:51.24#ibcon#end of sib2, iclass 11, count 0 2006.225.07:53:51.24#ibcon#*after write, iclass 11, count 0 2006.225.07:53:51.24#ibcon#*before return 0, iclass 11, count 0 2006.225.07:53:51.24#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:53:51.24#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.07:53:51.24#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.07:53:51.24#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.07:53:51.24$vc4f8/vb=3,4 2006.225.07:53:51.24#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.07:53:51.24#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.07:53:51.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:51.24#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:53:51.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:53:51.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:53:51.30#ibcon#enter wrdev, iclass 13, count 2 2006.225.07:53:51.30#ibcon#first serial, iclass 13, count 2 2006.225.07:53:51.30#ibcon#enter sib2, iclass 13, count 2 2006.225.07:53:51.30#ibcon#flushed, iclass 13, count 2 2006.225.07:53:51.30#ibcon#about to write, iclass 13, count 2 2006.225.07:53:51.30#ibcon#wrote, iclass 13, count 2 2006.225.07:53:51.30#ibcon#about to read 3, iclass 13, count 2 2006.225.07:53:51.32#ibcon#read 3, iclass 13, count 2 2006.225.07:53:51.32#ibcon#about to read 4, iclass 13, count 2 2006.225.07:53:51.32#ibcon#read 4, iclass 13, count 2 2006.225.07:53:51.32#ibcon#about to read 5, iclass 13, count 2 2006.225.07:53:51.32#ibcon#read 5, iclass 13, count 2 2006.225.07:53:51.32#ibcon#about to read 6, iclass 13, count 2 2006.225.07:53:51.32#ibcon#read 6, iclass 13, count 2 2006.225.07:53:51.32#ibcon#end of sib2, iclass 13, count 2 2006.225.07:53:51.32#ibcon#*mode == 0, iclass 13, count 2 2006.225.07:53:51.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.07:53:51.32#ibcon#[27=AT03-04\r\n] 2006.225.07:53:51.32#ibcon#*before write, iclass 13, count 2 2006.225.07:53:51.32#ibcon#enter sib2, iclass 13, count 2 2006.225.07:53:51.32#ibcon#flushed, iclass 13, count 2 2006.225.07:53:51.32#ibcon#about to write, iclass 13, count 2 2006.225.07:53:51.32#ibcon#wrote, iclass 13, count 2 2006.225.07:53:51.32#ibcon#about to read 3, iclass 13, count 2 2006.225.07:53:51.35#ibcon#read 3, iclass 13, count 2 2006.225.07:53:51.35#ibcon#about to read 4, iclass 13, count 2 2006.225.07:53:51.35#ibcon#read 4, iclass 13, count 2 2006.225.07:53:51.35#ibcon#about to read 5, iclass 13, count 2 2006.225.07:53:51.35#ibcon#read 5, iclass 13, count 2 2006.225.07:53:51.35#ibcon#about to read 6, iclass 13, count 2 2006.225.07:53:51.35#ibcon#read 6, iclass 13, count 2 2006.225.07:53:51.35#ibcon#end of sib2, iclass 13, count 2 2006.225.07:53:51.35#ibcon#*after write, iclass 13, count 2 2006.225.07:53:51.35#ibcon#*before return 0, iclass 13, count 2 2006.225.07:53:51.35#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:53:51.35#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.07:53:51.35#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.07:53:51.35#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:51.35#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:53:51.47#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:53:51.47#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:53:51.47#ibcon#enter wrdev, iclass 13, count 0 2006.225.07:53:51.47#ibcon#first serial, iclass 13, count 0 2006.225.07:53:51.47#ibcon#enter sib2, iclass 13, count 0 2006.225.07:53:51.47#ibcon#flushed, iclass 13, count 0 2006.225.07:53:51.47#ibcon#about to write, iclass 13, count 0 2006.225.07:53:51.47#ibcon#wrote, iclass 13, count 0 2006.225.07:53:51.47#ibcon#about to read 3, iclass 13, count 0 2006.225.07:53:51.49#ibcon#read 3, iclass 13, count 0 2006.225.07:53:51.49#ibcon#about to read 4, iclass 13, count 0 2006.225.07:53:51.49#ibcon#read 4, iclass 13, count 0 2006.225.07:53:51.49#ibcon#about to read 5, iclass 13, count 0 2006.225.07:53:51.49#ibcon#read 5, iclass 13, count 0 2006.225.07:53:51.49#ibcon#about to read 6, iclass 13, count 0 2006.225.07:53:51.49#ibcon#read 6, iclass 13, count 0 2006.225.07:53:51.49#ibcon#end of sib2, iclass 13, count 0 2006.225.07:53:51.49#ibcon#*mode == 0, iclass 13, count 0 2006.225.07:53:51.49#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.07:53:51.49#ibcon#[27=USB\r\n] 2006.225.07:53:51.49#ibcon#*before write, iclass 13, count 0 2006.225.07:53:51.49#ibcon#enter sib2, iclass 13, count 0 2006.225.07:53:51.49#ibcon#flushed, iclass 13, count 0 2006.225.07:53:51.49#ibcon#about to write, iclass 13, count 0 2006.225.07:53:51.49#ibcon#wrote, iclass 13, count 0 2006.225.07:53:51.49#ibcon#about to read 3, iclass 13, count 0 2006.225.07:53:51.52#ibcon#read 3, iclass 13, count 0 2006.225.07:53:51.52#ibcon#about to read 4, iclass 13, count 0 2006.225.07:53:51.52#ibcon#read 4, iclass 13, count 0 2006.225.07:53:51.52#ibcon#about to read 5, iclass 13, count 0 2006.225.07:53:51.52#ibcon#read 5, iclass 13, count 0 2006.225.07:53:51.52#ibcon#about to read 6, iclass 13, count 0 2006.225.07:53:51.52#ibcon#read 6, iclass 13, count 0 2006.225.07:53:51.52#ibcon#end of sib2, iclass 13, count 0 2006.225.07:53:51.52#ibcon#*after write, iclass 13, count 0 2006.225.07:53:51.52#ibcon#*before return 0, iclass 13, count 0 2006.225.07:53:51.52#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:53:51.52#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.07:53:51.52#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.07:53:51.52#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.07:53:51.52$vc4f8/vblo=4,712.99 2006.225.07:53:51.52#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.07:53:51.52#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.07:53:51.52#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:51.52#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:53:51.52#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:53:51.52#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:53:51.52#ibcon#enter wrdev, iclass 15, count 0 2006.225.07:53:51.52#ibcon#first serial, iclass 15, count 0 2006.225.07:53:51.52#ibcon#enter sib2, iclass 15, count 0 2006.225.07:53:51.52#ibcon#flushed, iclass 15, count 0 2006.225.07:53:51.52#ibcon#about to write, iclass 15, count 0 2006.225.07:53:51.52#ibcon#wrote, iclass 15, count 0 2006.225.07:53:51.52#ibcon#about to read 3, iclass 15, count 0 2006.225.07:53:51.54#ibcon#read 3, iclass 15, count 0 2006.225.07:53:51.54#ibcon#about to read 4, iclass 15, count 0 2006.225.07:53:51.54#ibcon#read 4, iclass 15, count 0 2006.225.07:53:51.54#ibcon#about to read 5, iclass 15, count 0 2006.225.07:53:51.54#ibcon#read 5, iclass 15, count 0 2006.225.07:53:51.54#ibcon#about to read 6, iclass 15, count 0 2006.225.07:53:51.54#ibcon#read 6, iclass 15, count 0 2006.225.07:53:51.54#ibcon#end of sib2, iclass 15, count 0 2006.225.07:53:51.54#ibcon#*mode == 0, iclass 15, count 0 2006.225.07:53:51.54#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.07:53:51.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:53:51.54#ibcon#*before write, iclass 15, count 0 2006.225.07:53:51.54#ibcon#enter sib2, iclass 15, count 0 2006.225.07:53:51.54#ibcon#flushed, iclass 15, count 0 2006.225.07:53:51.54#ibcon#about to write, iclass 15, count 0 2006.225.07:53:51.54#ibcon#wrote, iclass 15, count 0 2006.225.07:53:51.54#ibcon#about to read 3, iclass 15, count 0 2006.225.07:53:51.58#ibcon#read 3, iclass 15, count 0 2006.225.07:53:51.58#ibcon#about to read 4, iclass 15, count 0 2006.225.07:53:51.58#ibcon#read 4, iclass 15, count 0 2006.225.07:53:51.58#ibcon#about to read 5, iclass 15, count 0 2006.225.07:53:51.58#ibcon#read 5, iclass 15, count 0 2006.225.07:53:51.58#ibcon#about to read 6, iclass 15, count 0 2006.225.07:53:51.58#ibcon#read 6, iclass 15, count 0 2006.225.07:53:51.58#ibcon#end of sib2, iclass 15, count 0 2006.225.07:53:51.58#ibcon#*after write, iclass 15, count 0 2006.225.07:53:51.58#ibcon#*before return 0, iclass 15, count 0 2006.225.07:53:51.58#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:53:51.58#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.07:53:51.58#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.07:53:51.58#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.07:53:51.58$vc4f8/vb=4,4 2006.225.07:53:51.58#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.07:53:51.58#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.07:53:51.58#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:51.58#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:53:51.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:53:51.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:53:51.64#ibcon#enter wrdev, iclass 17, count 2 2006.225.07:53:51.64#ibcon#first serial, iclass 17, count 2 2006.225.07:53:51.64#ibcon#enter sib2, iclass 17, count 2 2006.225.07:53:51.64#ibcon#flushed, iclass 17, count 2 2006.225.07:53:51.64#ibcon#about to write, iclass 17, count 2 2006.225.07:53:51.64#ibcon#wrote, iclass 17, count 2 2006.225.07:53:51.64#ibcon#about to read 3, iclass 17, count 2 2006.225.07:53:51.66#ibcon#read 3, iclass 17, count 2 2006.225.07:53:51.66#ibcon#about to read 4, iclass 17, count 2 2006.225.07:53:51.66#ibcon#read 4, iclass 17, count 2 2006.225.07:53:51.66#ibcon#about to read 5, iclass 17, count 2 2006.225.07:53:51.66#ibcon#read 5, iclass 17, count 2 2006.225.07:53:51.66#ibcon#about to read 6, iclass 17, count 2 2006.225.07:53:51.66#ibcon#read 6, iclass 17, count 2 2006.225.07:53:51.66#ibcon#end of sib2, iclass 17, count 2 2006.225.07:53:51.66#ibcon#*mode == 0, iclass 17, count 2 2006.225.07:53:51.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.07:53:51.66#ibcon#[27=AT04-04\r\n] 2006.225.07:53:51.66#ibcon#*before write, iclass 17, count 2 2006.225.07:53:51.66#ibcon#enter sib2, iclass 17, count 2 2006.225.07:53:51.66#ibcon#flushed, iclass 17, count 2 2006.225.07:53:51.66#ibcon#about to write, iclass 17, count 2 2006.225.07:53:51.66#ibcon#wrote, iclass 17, count 2 2006.225.07:53:51.66#ibcon#about to read 3, iclass 17, count 2 2006.225.07:53:51.69#ibcon#read 3, iclass 17, count 2 2006.225.07:53:51.69#ibcon#about to read 4, iclass 17, count 2 2006.225.07:53:51.69#ibcon#read 4, iclass 17, count 2 2006.225.07:53:51.69#ibcon#about to read 5, iclass 17, count 2 2006.225.07:53:51.69#ibcon#read 5, iclass 17, count 2 2006.225.07:53:51.69#ibcon#about to read 6, iclass 17, count 2 2006.225.07:53:51.69#ibcon#read 6, iclass 17, count 2 2006.225.07:53:51.69#ibcon#end of sib2, iclass 17, count 2 2006.225.07:53:51.69#ibcon#*after write, iclass 17, count 2 2006.225.07:53:51.69#ibcon#*before return 0, iclass 17, count 2 2006.225.07:53:51.69#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:53:51.69#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.07:53:51.69#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.07:53:51.69#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:51.69#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:53:51.81#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:53:51.81#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:53:51.81#ibcon#enter wrdev, iclass 17, count 0 2006.225.07:53:51.81#ibcon#first serial, iclass 17, count 0 2006.225.07:53:51.81#ibcon#enter sib2, iclass 17, count 0 2006.225.07:53:51.81#ibcon#flushed, iclass 17, count 0 2006.225.07:53:51.81#ibcon#about to write, iclass 17, count 0 2006.225.07:53:51.81#ibcon#wrote, iclass 17, count 0 2006.225.07:53:51.81#ibcon#about to read 3, iclass 17, count 0 2006.225.07:53:51.83#ibcon#read 3, iclass 17, count 0 2006.225.07:53:51.83#ibcon#about to read 4, iclass 17, count 0 2006.225.07:53:51.83#ibcon#read 4, iclass 17, count 0 2006.225.07:53:51.83#ibcon#about to read 5, iclass 17, count 0 2006.225.07:53:51.83#ibcon#read 5, iclass 17, count 0 2006.225.07:53:51.83#ibcon#about to read 6, iclass 17, count 0 2006.225.07:53:51.83#ibcon#read 6, iclass 17, count 0 2006.225.07:53:51.83#ibcon#end of sib2, iclass 17, count 0 2006.225.07:53:51.83#ibcon#*mode == 0, iclass 17, count 0 2006.225.07:53:51.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.07:53:51.83#ibcon#[27=USB\r\n] 2006.225.07:53:51.83#ibcon#*before write, iclass 17, count 0 2006.225.07:53:51.83#ibcon#enter sib2, iclass 17, count 0 2006.225.07:53:51.83#ibcon#flushed, iclass 17, count 0 2006.225.07:53:51.83#ibcon#about to write, iclass 17, count 0 2006.225.07:53:51.83#ibcon#wrote, iclass 17, count 0 2006.225.07:53:51.83#ibcon#about to read 3, iclass 17, count 0 2006.225.07:53:51.86#ibcon#read 3, iclass 17, count 0 2006.225.07:53:51.86#ibcon#about to read 4, iclass 17, count 0 2006.225.07:53:51.86#ibcon#read 4, iclass 17, count 0 2006.225.07:53:51.86#ibcon#about to read 5, iclass 17, count 0 2006.225.07:53:51.86#ibcon#read 5, iclass 17, count 0 2006.225.07:53:51.86#ibcon#about to read 6, iclass 17, count 0 2006.225.07:53:51.86#ibcon#read 6, iclass 17, count 0 2006.225.07:53:51.86#ibcon#end of sib2, iclass 17, count 0 2006.225.07:53:51.86#ibcon#*after write, iclass 17, count 0 2006.225.07:53:51.86#ibcon#*before return 0, iclass 17, count 0 2006.225.07:53:51.86#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:53:51.86#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.07:53:51.86#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.07:53:51.86#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.07:53:51.86$vc4f8/vblo=5,744.99 2006.225.07:53:51.86#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.07:53:51.86#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.07:53:51.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:51.86#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:53:51.86#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:53:51.86#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:53:51.86#ibcon#enter wrdev, iclass 19, count 0 2006.225.07:53:51.86#ibcon#first serial, iclass 19, count 0 2006.225.07:53:51.86#ibcon#enter sib2, iclass 19, count 0 2006.225.07:53:51.86#ibcon#flushed, iclass 19, count 0 2006.225.07:53:51.86#ibcon#about to write, iclass 19, count 0 2006.225.07:53:51.86#ibcon#wrote, iclass 19, count 0 2006.225.07:53:51.86#ibcon#about to read 3, iclass 19, count 0 2006.225.07:53:51.88#ibcon#read 3, iclass 19, count 0 2006.225.07:53:51.88#ibcon#about to read 4, iclass 19, count 0 2006.225.07:53:51.88#ibcon#read 4, iclass 19, count 0 2006.225.07:53:51.88#ibcon#about to read 5, iclass 19, count 0 2006.225.07:53:51.88#ibcon#read 5, iclass 19, count 0 2006.225.07:53:51.88#ibcon#about to read 6, iclass 19, count 0 2006.225.07:53:51.88#ibcon#read 6, iclass 19, count 0 2006.225.07:53:51.88#ibcon#end of sib2, iclass 19, count 0 2006.225.07:53:51.88#ibcon#*mode == 0, iclass 19, count 0 2006.225.07:53:51.88#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.07:53:51.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:53:51.88#ibcon#*before write, iclass 19, count 0 2006.225.07:53:51.88#ibcon#enter sib2, iclass 19, count 0 2006.225.07:53:51.88#ibcon#flushed, iclass 19, count 0 2006.225.07:53:51.88#ibcon#about to write, iclass 19, count 0 2006.225.07:53:51.88#ibcon#wrote, iclass 19, count 0 2006.225.07:53:51.88#ibcon#about to read 3, iclass 19, count 0 2006.225.07:53:51.92#ibcon#read 3, iclass 19, count 0 2006.225.07:53:51.92#ibcon#about to read 4, iclass 19, count 0 2006.225.07:53:51.92#ibcon#read 4, iclass 19, count 0 2006.225.07:53:51.92#ibcon#about to read 5, iclass 19, count 0 2006.225.07:53:51.92#ibcon#read 5, iclass 19, count 0 2006.225.07:53:51.92#ibcon#about to read 6, iclass 19, count 0 2006.225.07:53:51.92#ibcon#read 6, iclass 19, count 0 2006.225.07:53:51.92#ibcon#end of sib2, iclass 19, count 0 2006.225.07:53:51.92#ibcon#*after write, iclass 19, count 0 2006.225.07:53:51.92#ibcon#*before return 0, iclass 19, count 0 2006.225.07:53:51.92#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:53:51.92#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.07:53:51.92#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.07:53:51.92#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.07:53:51.92$vc4f8/vb=5,4 2006.225.07:53:51.92#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.225.07:53:51.92#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.225.07:53:51.92#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:51.92#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:53:51.98#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:53:51.98#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:53:51.98#ibcon#enter wrdev, iclass 21, count 2 2006.225.07:53:51.98#ibcon#first serial, iclass 21, count 2 2006.225.07:53:51.98#ibcon#enter sib2, iclass 21, count 2 2006.225.07:53:51.98#ibcon#flushed, iclass 21, count 2 2006.225.07:53:51.98#ibcon#about to write, iclass 21, count 2 2006.225.07:53:51.98#ibcon#wrote, iclass 21, count 2 2006.225.07:53:51.98#ibcon#about to read 3, iclass 21, count 2 2006.225.07:53:52.00#ibcon#read 3, iclass 21, count 2 2006.225.07:53:52.00#ibcon#about to read 4, iclass 21, count 2 2006.225.07:53:52.00#ibcon#read 4, iclass 21, count 2 2006.225.07:53:52.00#ibcon#about to read 5, iclass 21, count 2 2006.225.07:53:52.00#ibcon#read 5, iclass 21, count 2 2006.225.07:53:52.00#ibcon#about to read 6, iclass 21, count 2 2006.225.07:53:52.00#ibcon#read 6, iclass 21, count 2 2006.225.07:53:52.00#ibcon#end of sib2, iclass 21, count 2 2006.225.07:53:52.00#ibcon#*mode == 0, iclass 21, count 2 2006.225.07:53:52.00#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.225.07:53:52.00#ibcon#[27=AT05-04\r\n] 2006.225.07:53:52.00#ibcon#*before write, iclass 21, count 2 2006.225.07:53:52.00#ibcon#enter sib2, iclass 21, count 2 2006.225.07:53:52.00#ibcon#flushed, iclass 21, count 2 2006.225.07:53:52.00#ibcon#about to write, iclass 21, count 2 2006.225.07:53:52.00#ibcon#wrote, iclass 21, count 2 2006.225.07:53:52.00#ibcon#about to read 3, iclass 21, count 2 2006.225.07:53:52.03#ibcon#read 3, iclass 21, count 2 2006.225.07:53:52.03#ibcon#about to read 4, iclass 21, count 2 2006.225.07:53:52.03#ibcon#read 4, iclass 21, count 2 2006.225.07:53:52.03#ibcon#about to read 5, iclass 21, count 2 2006.225.07:53:52.03#ibcon#read 5, iclass 21, count 2 2006.225.07:53:52.03#ibcon#about to read 6, iclass 21, count 2 2006.225.07:53:52.03#ibcon#read 6, iclass 21, count 2 2006.225.07:53:52.03#ibcon#end of sib2, iclass 21, count 2 2006.225.07:53:52.03#ibcon#*after write, iclass 21, count 2 2006.225.07:53:52.03#ibcon#*before return 0, iclass 21, count 2 2006.225.07:53:52.03#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:53:52.03#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.225.07:53:52.03#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.225.07:53:52.03#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:52.03#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:53:52.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:53:52.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:53:52.15#ibcon#enter wrdev, iclass 21, count 0 2006.225.07:53:52.15#ibcon#first serial, iclass 21, count 0 2006.225.07:53:52.15#ibcon#enter sib2, iclass 21, count 0 2006.225.07:53:52.15#ibcon#flushed, iclass 21, count 0 2006.225.07:53:52.15#ibcon#about to write, iclass 21, count 0 2006.225.07:53:52.15#ibcon#wrote, iclass 21, count 0 2006.225.07:53:52.15#ibcon#about to read 3, iclass 21, count 0 2006.225.07:53:52.17#ibcon#read 3, iclass 21, count 0 2006.225.07:53:52.17#ibcon#about to read 4, iclass 21, count 0 2006.225.07:53:52.17#ibcon#read 4, iclass 21, count 0 2006.225.07:53:52.17#ibcon#about to read 5, iclass 21, count 0 2006.225.07:53:52.17#ibcon#read 5, iclass 21, count 0 2006.225.07:53:52.17#ibcon#about to read 6, iclass 21, count 0 2006.225.07:53:52.17#ibcon#read 6, iclass 21, count 0 2006.225.07:53:52.17#ibcon#end of sib2, iclass 21, count 0 2006.225.07:53:52.17#ibcon#*mode == 0, iclass 21, count 0 2006.225.07:53:52.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.07:53:52.17#ibcon#[27=USB\r\n] 2006.225.07:53:52.17#ibcon#*before write, iclass 21, count 0 2006.225.07:53:52.17#ibcon#enter sib2, iclass 21, count 0 2006.225.07:53:52.17#ibcon#flushed, iclass 21, count 0 2006.225.07:53:52.17#ibcon#about to write, iclass 21, count 0 2006.225.07:53:52.17#ibcon#wrote, iclass 21, count 0 2006.225.07:53:52.17#ibcon#about to read 3, iclass 21, count 0 2006.225.07:53:52.20#ibcon#read 3, iclass 21, count 0 2006.225.07:53:52.20#ibcon#about to read 4, iclass 21, count 0 2006.225.07:53:52.20#ibcon#read 4, iclass 21, count 0 2006.225.07:53:52.20#ibcon#about to read 5, iclass 21, count 0 2006.225.07:53:52.20#ibcon#read 5, iclass 21, count 0 2006.225.07:53:52.20#ibcon#about to read 6, iclass 21, count 0 2006.225.07:53:52.20#ibcon#read 6, iclass 21, count 0 2006.225.07:53:52.20#ibcon#end of sib2, iclass 21, count 0 2006.225.07:53:52.20#ibcon#*after write, iclass 21, count 0 2006.225.07:53:52.20#ibcon#*before return 0, iclass 21, count 0 2006.225.07:53:52.20#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:53:52.20#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.225.07:53:52.20#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.07:53:52.20#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.07:53:52.20$vc4f8/vblo=6,752.99 2006.225.07:53:52.20#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.225.07:53:52.20#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.225.07:53:52.20#ibcon#ireg 17 cls_cnt 0 2006.225.07:53:52.20#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:53:52.20#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:53:52.20#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:53:52.20#ibcon#enter wrdev, iclass 23, count 0 2006.225.07:53:52.20#ibcon#first serial, iclass 23, count 0 2006.225.07:53:52.20#ibcon#enter sib2, iclass 23, count 0 2006.225.07:53:52.20#ibcon#flushed, iclass 23, count 0 2006.225.07:53:52.20#ibcon#about to write, iclass 23, count 0 2006.225.07:53:52.20#ibcon#wrote, iclass 23, count 0 2006.225.07:53:52.20#ibcon#about to read 3, iclass 23, count 0 2006.225.07:53:52.22#ibcon#read 3, iclass 23, count 0 2006.225.07:53:52.22#ibcon#about to read 4, iclass 23, count 0 2006.225.07:53:52.22#ibcon#read 4, iclass 23, count 0 2006.225.07:53:52.22#ibcon#about to read 5, iclass 23, count 0 2006.225.07:53:52.22#ibcon#read 5, iclass 23, count 0 2006.225.07:53:52.22#ibcon#about to read 6, iclass 23, count 0 2006.225.07:53:52.22#ibcon#read 6, iclass 23, count 0 2006.225.07:53:52.22#ibcon#end of sib2, iclass 23, count 0 2006.225.07:53:52.22#ibcon#*mode == 0, iclass 23, count 0 2006.225.07:53:52.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.07:53:52.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:53:52.22#ibcon#*before write, iclass 23, count 0 2006.225.07:53:52.22#ibcon#enter sib2, iclass 23, count 0 2006.225.07:53:52.22#ibcon#flushed, iclass 23, count 0 2006.225.07:53:52.22#ibcon#about to write, iclass 23, count 0 2006.225.07:53:52.22#ibcon#wrote, iclass 23, count 0 2006.225.07:53:52.22#ibcon#about to read 3, iclass 23, count 0 2006.225.07:53:52.26#ibcon#read 3, iclass 23, count 0 2006.225.07:53:52.26#ibcon#about to read 4, iclass 23, count 0 2006.225.07:53:52.26#ibcon#read 4, iclass 23, count 0 2006.225.07:53:52.26#ibcon#about to read 5, iclass 23, count 0 2006.225.07:53:52.26#ibcon#read 5, iclass 23, count 0 2006.225.07:53:52.26#ibcon#about to read 6, iclass 23, count 0 2006.225.07:53:52.26#ibcon#read 6, iclass 23, count 0 2006.225.07:53:52.26#ibcon#end of sib2, iclass 23, count 0 2006.225.07:53:52.26#ibcon#*after write, iclass 23, count 0 2006.225.07:53:52.26#ibcon#*before return 0, iclass 23, count 0 2006.225.07:53:52.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:53:52.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.225.07:53:52.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.07:53:52.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.07:53:52.26$vc4f8/vb=6,4 2006.225.07:53:52.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.225.07:53:52.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.225.07:53:52.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:53:52.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:53:52.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:53:52.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:53:52.32#ibcon#enter wrdev, iclass 25, count 2 2006.225.07:53:52.32#ibcon#first serial, iclass 25, count 2 2006.225.07:53:52.32#ibcon#enter sib2, iclass 25, count 2 2006.225.07:53:52.32#ibcon#flushed, iclass 25, count 2 2006.225.07:53:52.32#ibcon#about to write, iclass 25, count 2 2006.225.07:53:52.32#ibcon#wrote, iclass 25, count 2 2006.225.07:53:52.32#ibcon#about to read 3, iclass 25, count 2 2006.225.07:53:52.34#ibcon#read 3, iclass 25, count 2 2006.225.07:53:52.34#ibcon#about to read 4, iclass 25, count 2 2006.225.07:53:52.34#ibcon#read 4, iclass 25, count 2 2006.225.07:53:52.34#ibcon#about to read 5, iclass 25, count 2 2006.225.07:53:52.34#ibcon#read 5, iclass 25, count 2 2006.225.07:53:52.34#ibcon#about to read 6, iclass 25, count 2 2006.225.07:53:52.34#ibcon#read 6, iclass 25, count 2 2006.225.07:53:52.34#ibcon#end of sib2, iclass 25, count 2 2006.225.07:53:52.34#ibcon#*mode == 0, iclass 25, count 2 2006.225.07:53:52.34#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.225.07:53:52.34#ibcon#[27=AT06-04\r\n] 2006.225.07:53:52.34#ibcon#*before write, iclass 25, count 2 2006.225.07:53:52.34#ibcon#enter sib2, iclass 25, count 2 2006.225.07:53:52.34#ibcon#flushed, iclass 25, count 2 2006.225.07:53:52.34#ibcon#about to write, iclass 25, count 2 2006.225.07:53:52.34#ibcon#wrote, iclass 25, count 2 2006.225.07:53:52.34#ibcon#about to read 3, iclass 25, count 2 2006.225.07:53:52.37#ibcon#read 3, iclass 25, count 2 2006.225.07:53:52.37#ibcon#about to read 4, iclass 25, count 2 2006.225.07:53:52.37#ibcon#read 4, iclass 25, count 2 2006.225.07:53:52.37#ibcon#about to read 5, iclass 25, count 2 2006.225.07:53:52.37#ibcon#read 5, iclass 25, count 2 2006.225.07:53:52.37#ibcon#about to read 6, iclass 25, count 2 2006.225.07:53:52.37#ibcon#read 6, iclass 25, count 2 2006.225.07:53:52.37#ibcon#end of sib2, iclass 25, count 2 2006.225.07:53:52.37#ibcon#*after write, iclass 25, count 2 2006.225.07:53:52.37#ibcon#*before return 0, iclass 25, count 2 2006.225.07:53:52.37#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:53:52.37#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.225.07:53:52.37#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.225.07:53:52.37#ibcon#ireg 7 cls_cnt 0 2006.225.07:53:52.37#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:53:52.49#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:53:52.49#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:53:52.49#ibcon#enter wrdev, iclass 25, count 0 2006.225.07:53:52.49#ibcon#first serial, iclass 25, count 0 2006.225.07:53:52.49#ibcon#enter sib2, iclass 25, count 0 2006.225.07:53:52.49#ibcon#flushed, iclass 25, count 0 2006.225.07:53:52.49#ibcon#about to write, iclass 25, count 0 2006.225.07:53:52.49#ibcon#wrote, iclass 25, count 0 2006.225.07:53:52.49#ibcon#about to read 3, iclass 25, count 0 2006.225.07:53:52.51#ibcon#read 3, iclass 25, count 0 2006.225.07:53:52.51#ibcon#about to read 4, iclass 25, count 0 2006.225.07:53:52.51#ibcon#read 4, iclass 25, count 0 2006.225.07:53:52.51#ibcon#about to read 5, iclass 25, count 0 2006.225.07:53:52.51#ibcon#read 5, iclass 25, count 0 2006.225.07:53:52.51#ibcon#about to read 6, iclass 25, count 0 2006.225.07:53:52.51#ibcon#read 6, iclass 25, count 0 2006.225.07:53:52.51#ibcon#end of sib2, iclass 25, count 0 2006.225.07:53:52.51#ibcon#*mode == 0, iclass 25, count 0 2006.225.07:53:52.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.07:53:52.51#ibcon#[27=USB\r\n] 2006.225.07:53:52.51#ibcon#*before write, iclass 25, count 0 2006.225.07:53:52.51#ibcon#enter sib2, iclass 25, count 0 2006.225.07:53:52.51#ibcon#flushed, iclass 25, count 0 2006.225.07:53:52.51#ibcon#about to write, iclass 25, count 0 2006.225.07:53:52.51#ibcon#wrote, iclass 25, count 0 2006.225.07:53:52.51#ibcon#about to read 3, iclass 25, count 0 2006.225.07:53:52.54#ibcon#read 3, iclass 25, count 0 2006.225.07:53:52.54#ibcon#about to read 4, iclass 25, count 0 2006.225.07:53:52.54#ibcon#read 4, iclass 25, count 0 2006.225.07:53:52.54#ibcon#about to read 5, iclass 25, count 0 2006.225.07:53:52.54#ibcon#read 5, iclass 25, count 0 2006.225.07:53:52.54#ibcon#about to read 6, iclass 25, count 0 2006.225.07:53:52.54#ibcon#read 6, iclass 25, count 0 2006.225.07:53:52.54#ibcon#end of sib2, iclass 25, count 0 2006.225.07:53:52.54#ibcon#*after write, iclass 25, count 0 2006.225.07:53:52.54#ibcon#*before return 0, iclass 25, count 0 2006.225.07:53:52.54#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:53:52.54#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.225.07:53:52.54#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.07:53:52.54#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.07:53:52.54$vc4f8/vabw=wide 2006.225.07:53:52.54#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.07:53:52.54#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.07:53:52.54#ibcon#ireg 8 cls_cnt 0 2006.225.07:53:52.54#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:53:52.54#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:53:52.54#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:53:52.54#ibcon#enter wrdev, iclass 27, count 0 2006.225.07:53:52.54#ibcon#first serial, iclass 27, count 0 2006.225.07:53:52.54#ibcon#enter sib2, iclass 27, count 0 2006.225.07:53:52.54#ibcon#flushed, iclass 27, count 0 2006.225.07:53:52.54#ibcon#about to write, iclass 27, count 0 2006.225.07:53:52.54#ibcon#wrote, iclass 27, count 0 2006.225.07:53:52.54#ibcon#about to read 3, iclass 27, count 0 2006.225.07:53:52.56#ibcon#read 3, iclass 27, count 0 2006.225.07:53:52.56#ibcon#about to read 4, iclass 27, count 0 2006.225.07:53:52.56#ibcon#read 4, iclass 27, count 0 2006.225.07:53:52.56#ibcon#about to read 5, iclass 27, count 0 2006.225.07:53:52.56#ibcon#read 5, iclass 27, count 0 2006.225.07:53:52.56#ibcon#about to read 6, iclass 27, count 0 2006.225.07:53:52.56#ibcon#read 6, iclass 27, count 0 2006.225.07:53:52.56#ibcon#end of sib2, iclass 27, count 0 2006.225.07:53:52.56#ibcon#*mode == 0, iclass 27, count 0 2006.225.07:53:52.56#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.07:53:52.56#ibcon#[25=BW32\r\n] 2006.225.07:53:52.56#ibcon#*before write, iclass 27, count 0 2006.225.07:53:52.56#ibcon#enter sib2, iclass 27, count 0 2006.225.07:53:52.56#ibcon#flushed, iclass 27, count 0 2006.225.07:53:52.56#ibcon#about to write, iclass 27, count 0 2006.225.07:53:52.56#ibcon#wrote, iclass 27, count 0 2006.225.07:53:52.56#ibcon#about to read 3, iclass 27, count 0 2006.225.07:53:52.59#ibcon#read 3, iclass 27, count 0 2006.225.07:53:52.59#ibcon#about to read 4, iclass 27, count 0 2006.225.07:53:52.59#ibcon#read 4, iclass 27, count 0 2006.225.07:53:52.59#ibcon#about to read 5, iclass 27, count 0 2006.225.07:53:52.59#ibcon#read 5, iclass 27, count 0 2006.225.07:53:52.59#ibcon#about to read 6, iclass 27, count 0 2006.225.07:53:52.59#ibcon#read 6, iclass 27, count 0 2006.225.07:53:52.59#ibcon#end of sib2, iclass 27, count 0 2006.225.07:53:52.59#ibcon#*after write, iclass 27, count 0 2006.225.07:53:52.59#ibcon#*before return 0, iclass 27, count 0 2006.225.07:53:52.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:53:52.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.07:53:52.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.07:53:52.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.07:53:52.59$vc4f8/vbbw=wide 2006.225.07:53:52.59#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.07:53:52.59#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.07:53:52.59#ibcon#ireg 8 cls_cnt 0 2006.225.07:53:52.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:53:52.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:53:52.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:53:52.66#ibcon#enter wrdev, iclass 29, count 0 2006.225.07:53:52.66#ibcon#first serial, iclass 29, count 0 2006.225.07:53:52.66#ibcon#enter sib2, iclass 29, count 0 2006.225.07:53:52.66#ibcon#flushed, iclass 29, count 0 2006.225.07:53:52.66#ibcon#about to write, iclass 29, count 0 2006.225.07:53:52.66#ibcon#wrote, iclass 29, count 0 2006.225.07:53:52.66#ibcon#about to read 3, iclass 29, count 0 2006.225.07:53:52.68#ibcon#read 3, iclass 29, count 0 2006.225.07:53:52.68#ibcon#about to read 4, iclass 29, count 0 2006.225.07:53:52.68#ibcon#read 4, iclass 29, count 0 2006.225.07:53:52.68#ibcon#about to read 5, iclass 29, count 0 2006.225.07:53:52.68#ibcon#read 5, iclass 29, count 0 2006.225.07:53:52.68#ibcon#about to read 6, iclass 29, count 0 2006.225.07:53:52.68#ibcon#read 6, iclass 29, count 0 2006.225.07:53:52.68#ibcon#end of sib2, iclass 29, count 0 2006.225.07:53:52.68#ibcon#*mode == 0, iclass 29, count 0 2006.225.07:53:52.68#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.07:53:52.68#ibcon#[27=BW32\r\n] 2006.225.07:53:52.68#ibcon#*before write, iclass 29, count 0 2006.225.07:53:52.68#ibcon#enter sib2, iclass 29, count 0 2006.225.07:53:52.68#ibcon#flushed, iclass 29, count 0 2006.225.07:53:52.68#ibcon#about to write, iclass 29, count 0 2006.225.07:53:52.68#ibcon#wrote, iclass 29, count 0 2006.225.07:53:52.68#ibcon#about to read 3, iclass 29, count 0 2006.225.07:53:52.71#ibcon#read 3, iclass 29, count 0 2006.225.07:53:52.71#ibcon#about to read 4, iclass 29, count 0 2006.225.07:53:52.71#ibcon#read 4, iclass 29, count 0 2006.225.07:53:52.71#ibcon#about to read 5, iclass 29, count 0 2006.225.07:53:52.71#ibcon#read 5, iclass 29, count 0 2006.225.07:53:52.71#ibcon#about to read 6, iclass 29, count 0 2006.225.07:53:52.71#ibcon#read 6, iclass 29, count 0 2006.225.07:53:52.71#ibcon#end of sib2, iclass 29, count 0 2006.225.07:53:52.71#ibcon#*after write, iclass 29, count 0 2006.225.07:53:52.71#ibcon#*before return 0, iclass 29, count 0 2006.225.07:53:52.71#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:53:52.71#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.07:53:52.71#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.07:53:52.71#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.07:53:52.71$4f8m12a/ifd4f 2006.225.07:53:52.71$ifd4f/lo= 2006.225.07:53:52.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:53:52.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:53:52.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:53:52.71$ifd4f/patch= 2006.225.07:53:52.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:53:52.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:53:52.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:53:52.71$4f8m12a/"form=m,16.000,1:2 2006.225.07:53:52.71$4f8m12a/"tpicd 2006.225.07:53:52.71$4f8m12a/echo=off 2006.225.07:53:52.71$4f8m12a/xlog=off 2006.225.07:53:52.71:!2006.225.07:55:20 2006.225.07:54:22.14#trakl#Source acquired 2006.225.07:54:23.14#flagr#flagr/antenna,acquired 2006.225.07:55:20.00:preob 2006.225.07:55:21.14/onsource/TRACKING 2006.225.07:55:21.14:!2006.225.07:55:30 2006.225.07:55:30.00:data_valid=on 2006.225.07:55:30.00:midob 2006.225.07:55:30.14/onsource/TRACKING 2006.225.07:55:30.14/wx/28.37,1003.3,70 2006.225.07:55:30.23/cable/+6.4036E-03 2006.225.07:55:31.32/va/01,08,usb,yes,40,42 2006.225.07:55:31.32/va/02,07,usb,yes,40,42 2006.225.07:55:31.32/va/03,06,usb,yes,43,43 2006.225.07:55:31.32/va/04,07,usb,yes,42,45 2006.225.07:55:31.32/va/05,07,usb,yes,47,49 2006.225.07:55:31.32/va/06,06,usb,yes,46,46 2006.225.07:55:31.32/va/07,06,usb,yes,47,47 2006.225.07:55:31.32/va/08,07,usb,yes,45,44 2006.225.07:55:31.55/valo/01,532.99,yes,locked 2006.225.07:55:31.55/valo/02,572.99,yes,locked 2006.225.07:55:31.55/valo/03,672.99,yes,locked 2006.225.07:55:31.55/valo/04,832.99,yes,locked 2006.225.07:55:31.55/valo/05,652.99,yes,locked 2006.225.07:55:31.55/valo/06,772.99,yes,locked 2006.225.07:55:31.55/valo/07,832.99,yes,locked 2006.225.07:55:31.55/valo/08,852.99,yes,locked 2006.225.07:55:32.64/vb/01,04,usb,yes,32,30 2006.225.07:55:32.64/vb/02,04,usb,yes,34,35 2006.225.07:55:32.64/vb/03,04,usb,yes,30,34 2006.225.07:55:32.64/vb/04,04,usb,yes,31,31 2006.225.07:55:32.64/vb/05,04,usb,yes,29,33 2006.225.07:55:32.64/vb/06,04,usb,yes,30,33 2006.225.07:55:32.64/vb/07,04,usb,yes,32,32 2006.225.07:55:32.64/vb/08,04,usb,yes,30,33 2006.225.07:55:32.88/vblo/01,632.99,yes,locked 2006.225.07:55:32.88/vblo/02,640.99,yes,locked 2006.225.07:55:32.88/vblo/03,656.99,yes,locked 2006.225.07:55:32.88/vblo/04,712.99,yes,locked 2006.225.07:55:32.88/vblo/05,744.99,yes,locked 2006.225.07:55:32.88/vblo/06,752.99,yes,locked 2006.225.07:55:32.88/vblo/07,734.99,yes,locked 2006.225.07:55:32.88/vblo/08,744.99,yes,locked 2006.225.07:55:33.03/vabw/8 2006.225.07:55:33.18/vbbw/8 2006.225.07:55:33.27/xfe/off,on,15.2 2006.225.07:55:33.65/ifatt/23,28,28,28 2006.225.07:55:34.08/fmout-gps/S +4.55E-07 2006.225.07:55:34.12:!2006.225.07:56:30 2006.225.07:56:30.01:data_valid=off 2006.225.07:56:30.01:postob 2006.225.07:56:30.22/cable/+6.4031E-03 2006.225.07:56:30.22/wx/28.37,1003.3,71 2006.225.07:56:31.08/fmout-gps/S +4.55E-07 2006.225.07:56:31.08:scan_name=225-0759,k06225,60 2006.225.07:56:31.08:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.225.07:56:31.14#flagr#flagr/antenna,new-source 2006.225.07:56:32.14:checkk5 2006.225.07:56:32.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.07:56:32.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.07:56:33.27/chk_autoobs//k5ts3/ autoobs is running! 2006.225.07:56:33.64/chk_autoobs//k5ts4/ autoobs is running! 2006.225.07:56:34.00/chk_obsdata//k5ts1/T2250755??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:56:34.37/chk_obsdata//k5ts2/T2250755??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:56:34.73/chk_obsdata//k5ts3/T2250755??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:56:35.10/chk_obsdata//k5ts4/T2250755??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.07:56:35.78/k5log//k5ts1_log_newline 2006.225.07:56:36.47/k5log//k5ts2_log_newline 2006.225.07:56:37.15/k5log//k5ts3_log_newline 2006.225.07:56:37.83/k5log//k5ts4_log_newline 2006.225.07:56:37.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.07:56:37.86:4f8m12a=2 2006.225.07:56:37.86$4f8m12a/echo=on 2006.225.07:56:37.86$4f8m12a/pcalon 2006.225.07:56:37.86$pcalon/"no phase cal control is implemented here 2006.225.07:56:37.86$4f8m12a/"tpicd=stop 2006.225.07:56:37.86$4f8m12a/vc4f8 2006.225.07:56:37.86$vc4f8/valo=1,532.99 2006.225.07:56:37.86#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.07:56:37.86#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.07:56:37.86#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:37.86#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:56:37.86#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:56:37.86#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:56:37.86#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:56:37.86#ibcon#first serial, iclass 24, count 0 2006.225.07:56:37.86#ibcon#enter sib2, iclass 24, count 0 2006.225.07:56:37.86#ibcon#flushed, iclass 24, count 0 2006.225.07:56:37.86#ibcon#about to write, iclass 24, count 0 2006.225.07:56:37.86#ibcon#wrote, iclass 24, count 0 2006.225.07:56:37.86#ibcon#about to read 3, iclass 24, count 0 2006.225.07:56:37.90#ibcon#read 3, iclass 24, count 0 2006.225.07:56:37.90#ibcon#about to read 4, iclass 24, count 0 2006.225.07:56:37.90#ibcon#read 4, iclass 24, count 0 2006.225.07:56:37.90#ibcon#about to read 5, iclass 24, count 0 2006.225.07:56:37.90#ibcon#read 5, iclass 24, count 0 2006.225.07:56:37.90#ibcon#about to read 6, iclass 24, count 0 2006.225.07:56:37.90#ibcon#read 6, iclass 24, count 0 2006.225.07:56:37.90#ibcon#end of sib2, iclass 24, count 0 2006.225.07:56:37.90#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:56:37.90#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:56:37.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.07:56:37.90#ibcon#*before write, iclass 24, count 0 2006.225.07:56:37.90#ibcon#enter sib2, iclass 24, count 0 2006.225.07:56:37.90#ibcon#flushed, iclass 24, count 0 2006.225.07:56:37.90#ibcon#about to write, iclass 24, count 0 2006.225.07:56:37.90#ibcon#wrote, iclass 24, count 0 2006.225.07:56:37.90#ibcon#about to read 3, iclass 24, count 0 2006.225.07:56:37.95#ibcon#read 3, iclass 24, count 0 2006.225.07:56:37.95#ibcon#about to read 4, iclass 24, count 0 2006.225.07:56:37.95#ibcon#read 4, iclass 24, count 0 2006.225.07:56:37.95#ibcon#about to read 5, iclass 24, count 0 2006.225.07:56:37.95#ibcon#read 5, iclass 24, count 0 2006.225.07:56:37.95#ibcon#about to read 6, iclass 24, count 0 2006.225.07:56:37.95#ibcon#read 6, iclass 24, count 0 2006.225.07:56:37.95#ibcon#end of sib2, iclass 24, count 0 2006.225.07:56:37.95#ibcon#*after write, iclass 24, count 0 2006.225.07:56:37.95#ibcon#*before return 0, iclass 24, count 0 2006.225.07:56:37.95#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:56:37.95#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:56:37.95#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:56:37.95#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:56:37.95$vc4f8/va=1,8 2006.225.07:56:37.95#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.225.07:56:37.95#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.225.07:56:37.95#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:37.95#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:56:37.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:56:37.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:56:37.95#ibcon#enter wrdev, iclass 26, count 2 2006.225.07:56:37.95#ibcon#first serial, iclass 26, count 2 2006.225.07:56:37.95#ibcon#enter sib2, iclass 26, count 2 2006.225.07:56:37.95#ibcon#flushed, iclass 26, count 2 2006.225.07:56:37.95#ibcon#about to write, iclass 26, count 2 2006.225.07:56:37.95#ibcon#wrote, iclass 26, count 2 2006.225.07:56:37.95#ibcon#about to read 3, iclass 26, count 2 2006.225.07:56:37.97#ibcon#read 3, iclass 26, count 2 2006.225.07:56:37.97#ibcon#about to read 4, iclass 26, count 2 2006.225.07:56:37.97#ibcon#read 4, iclass 26, count 2 2006.225.07:56:37.97#ibcon#about to read 5, iclass 26, count 2 2006.225.07:56:37.97#ibcon#read 5, iclass 26, count 2 2006.225.07:56:37.97#ibcon#about to read 6, iclass 26, count 2 2006.225.07:56:37.97#ibcon#read 6, iclass 26, count 2 2006.225.07:56:37.97#ibcon#end of sib2, iclass 26, count 2 2006.225.07:56:37.97#ibcon#*mode == 0, iclass 26, count 2 2006.225.07:56:37.97#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.225.07:56:37.97#ibcon#[25=AT01-08\r\n] 2006.225.07:56:37.97#ibcon#*before write, iclass 26, count 2 2006.225.07:56:37.97#ibcon#enter sib2, iclass 26, count 2 2006.225.07:56:37.97#ibcon#flushed, iclass 26, count 2 2006.225.07:56:37.97#ibcon#about to write, iclass 26, count 2 2006.225.07:56:37.97#ibcon#wrote, iclass 26, count 2 2006.225.07:56:37.97#ibcon#about to read 3, iclass 26, count 2 2006.225.07:56:38.00#ibcon#read 3, iclass 26, count 2 2006.225.07:56:38.00#ibcon#about to read 4, iclass 26, count 2 2006.225.07:56:38.00#ibcon#read 4, iclass 26, count 2 2006.225.07:56:38.00#ibcon#about to read 5, iclass 26, count 2 2006.225.07:56:38.00#ibcon#read 5, iclass 26, count 2 2006.225.07:56:38.00#ibcon#about to read 6, iclass 26, count 2 2006.225.07:56:38.00#ibcon#read 6, iclass 26, count 2 2006.225.07:56:38.00#ibcon#end of sib2, iclass 26, count 2 2006.225.07:56:38.00#ibcon#*after write, iclass 26, count 2 2006.225.07:56:38.00#ibcon#*before return 0, iclass 26, count 2 2006.225.07:56:38.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:56:38.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:56:38.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.225.07:56:38.00#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:38.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:56:38.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:56:38.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:56:38.12#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:56:38.12#ibcon#first serial, iclass 26, count 0 2006.225.07:56:38.12#ibcon#enter sib2, iclass 26, count 0 2006.225.07:56:38.12#ibcon#flushed, iclass 26, count 0 2006.225.07:56:38.12#ibcon#about to write, iclass 26, count 0 2006.225.07:56:38.12#ibcon#wrote, iclass 26, count 0 2006.225.07:56:38.12#ibcon#about to read 3, iclass 26, count 0 2006.225.07:56:38.14#ibcon#read 3, iclass 26, count 0 2006.225.07:56:38.14#ibcon#about to read 4, iclass 26, count 0 2006.225.07:56:38.14#ibcon#read 4, iclass 26, count 0 2006.225.07:56:38.14#ibcon#about to read 5, iclass 26, count 0 2006.225.07:56:38.14#ibcon#read 5, iclass 26, count 0 2006.225.07:56:38.14#ibcon#about to read 6, iclass 26, count 0 2006.225.07:56:38.14#ibcon#read 6, iclass 26, count 0 2006.225.07:56:38.14#ibcon#end of sib2, iclass 26, count 0 2006.225.07:56:38.14#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:56:38.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:56:38.14#ibcon#[25=USB\r\n] 2006.225.07:56:38.14#ibcon#*before write, iclass 26, count 0 2006.225.07:56:38.14#ibcon#enter sib2, iclass 26, count 0 2006.225.07:56:38.14#ibcon#flushed, iclass 26, count 0 2006.225.07:56:38.14#ibcon#about to write, iclass 26, count 0 2006.225.07:56:38.14#ibcon#wrote, iclass 26, count 0 2006.225.07:56:38.14#ibcon#about to read 3, iclass 26, count 0 2006.225.07:56:38.17#ibcon#read 3, iclass 26, count 0 2006.225.07:56:38.17#ibcon#about to read 4, iclass 26, count 0 2006.225.07:56:38.17#ibcon#read 4, iclass 26, count 0 2006.225.07:56:38.17#ibcon#about to read 5, iclass 26, count 0 2006.225.07:56:38.17#ibcon#read 5, iclass 26, count 0 2006.225.07:56:38.17#ibcon#about to read 6, iclass 26, count 0 2006.225.07:56:38.17#ibcon#read 6, iclass 26, count 0 2006.225.07:56:38.17#ibcon#end of sib2, iclass 26, count 0 2006.225.07:56:38.17#ibcon#*after write, iclass 26, count 0 2006.225.07:56:38.17#ibcon#*before return 0, iclass 26, count 0 2006.225.07:56:38.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:56:38.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:56:38.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:56:38.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:56:38.17$vc4f8/valo=2,572.99 2006.225.07:56:38.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.07:56:38.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.07:56:38.17#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:38.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:56:38.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:56:38.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:56:38.17#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:56:38.17#ibcon#first serial, iclass 28, count 0 2006.225.07:56:38.17#ibcon#enter sib2, iclass 28, count 0 2006.225.07:56:38.17#ibcon#flushed, iclass 28, count 0 2006.225.07:56:38.17#ibcon#about to write, iclass 28, count 0 2006.225.07:56:38.17#ibcon#wrote, iclass 28, count 0 2006.225.07:56:38.17#ibcon#about to read 3, iclass 28, count 0 2006.225.07:56:38.19#ibcon#read 3, iclass 28, count 0 2006.225.07:56:38.19#ibcon#about to read 4, iclass 28, count 0 2006.225.07:56:38.19#ibcon#read 4, iclass 28, count 0 2006.225.07:56:38.19#ibcon#about to read 5, iclass 28, count 0 2006.225.07:56:38.19#ibcon#read 5, iclass 28, count 0 2006.225.07:56:38.19#ibcon#about to read 6, iclass 28, count 0 2006.225.07:56:38.19#ibcon#read 6, iclass 28, count 0 2006.225.07:56:38.19#ibcon#end of sib2, iclass 28, count 0 2006.225.07:56:38.19#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:56:38.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:56:38.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.07:56:38.19#ibcon#*before write, iclass 28, count 0 2006.225.07:56:38.19#ibcon#enter sib2, iclass 28, count 0 2006.225.07:56:38.19#ibcon#flushed, iclass 28, count 0 2006.225.07:56:38.19#ibcon#about to write, iclass 28, count 0 2006.225.07:56:38.19#ibcon#wrote, iclass 28, count 0 2006.225.07:56:38.19#ibcon#about to read 3, iclass 28, count 0 2006.225.07:56:38.24#ibcon#read 3, iclass 28, count 0 2006.225.07:56:38.24#ibcon#about to read 4, iclass 28, count 0 2006.225.07:56:38.24#ibcon#read 4, iclass 28, count 0 2006.225.07:56:38.24#ibcon#about to read 5, iclass 28, count 0 2006.225.07:56:38.24#ibcon#read 5, iclass 28, count 0 2006.225.07:56:38.24#ibcon#about to read 6, iclass 28, count 0 2006.225.07:56:38.24#ibcon#read 6, iclass 28, count 0 2006.225.07:56:38.24#ibcon#end of sib2, iclass 28, count 0 2006.225.07:56:38.24#ibcon#*after write, iclass 28, count 0 2006.225.07:56:38.24#ibcon#*before return 0, iclass 28, count 0 2006.225.07:56:38.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:56:38.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:56:38.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:56:38.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:56:38.24$vc4f8/va=2,7 2006.225.07:56:38.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.07:56:38.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.07:56:38.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:38.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:56:38.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:56:38.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:56:38.29#ibcon#enter wrdev, iclass 30, count 2 2006.225.07:56:38.29#ibcon#first serial, iclass 30, count 2 2006.225.07:56:38.29#ibcon#enter sib2, iclass 30, count 2 2006.225.07:56:38.29#ibcon#flushed, iclass 30, count 2 2006.225.07:56:38.29#ibcon#about to write, iclass 30, count 2 2006.225.07:56:38.29#ibcon#wrote, iclass 30, count 2 2006.225.07:56:38.29#ibcon#about to read 3, iclass 30, count 2 2006.225.07:56:38.31#ibcon#read 3, iclass 30, count 2 2006.225.07:56:38.31#ibcon#about to read 4, iclass 30, count 2 2006.225.07:56:38.31#ibcon#read 4, iclass 30, count 2 2006.225.07:56:38.31#ibcon#about to read 5, iclass 30, count 2 2006.225.07:56:38.31#ibcon#read 5, iclass 30, count 2 2006.225.07:56:38.31#ibcon#about to read 6, iclass 30, count 2 2006.225.07:56:38.31#ibcon#read 6, iclass 30, count 2 2006.225.07:56:38.31#ibcon#end of sib2, iclass 30, count 2 2006.225.07:56:38.31#ibcon#*mode == 0, iclass 30, count 2 2006.225.07:56:38.31#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.07:56:38.31#ibcon#[25=AT02-07\r\n] 2006.225.07:56:38.31#ibcon#*before write, iclass 30, count 2 2006.225.07:56:38.31#ibcon#enter sib2, iclass 30, count 2 2006.225.07:56:38.31#ibcon#flushed, iclass 30, count 2 2006.225.07:56:38.31#ibcon#about to write, iclass 30, count 2 2006.225.07:56:38.31#ibcon#wrote, iclass 30, count 2 2006.225.07:56:38.31#ibcon#about to read 3, iclass 30, count 2 2006.225.07:56:38.34#ibcon#read 3, iclass 30, count 2 2006.225.07:56:38.34#ibcon#about to read 4, iclass 30, count 2 2006.225.07:56:38.34#ibcon#read 4, iclass 30, count 2 2006.225.07:56:38.34#ibcon#about to read 5, iclass 30, count 2 2006.225.07:56:38.34#ibcon#read 5, iclass 30, count 2 2006.225.07:56:38.34#ibcon#about to read 6, iclass 30, count 2 2006.225.07:56:38.34#ibcon#read 6, iclass 30, count 2 2006.225.07:56:38.34#ibcon#end of sib2, iclass 30, count 2 2006.225.07:56:38.34#ibcon#*after write, iclass 30, count 2 2006.225.07:56:38.34#ibcon#*before return 0, iclass 30, count 2 2006.225.07:56:38.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:56:38.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:56:38.34#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.07:56:38.34#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:38.34#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:56:38.46#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:56:38.46#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:56:38.46#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:56:38.46#ibcon#first serial, iclass 30, count 0 2006.225.07:56:38.46#ibcon#enter sib2, iclass 30, count 0 2006.225.07:56:38.46#ibcon#flushed, iclass 30, count 0 2006.225.07:56:38.46#ibcon#about to write, iclass 30, count 0 2006.225.07:56:38.46#ibcon#wrote, iclass 30, count 0 2006.225.07:56:38.46#ibcon#about to read 3, iclass 30, count 0 2006.225.07:56:38.48#ibcon#read 3, iclass 30, count 0 2006.225.07:56:38.48#ibcon#about to read 4, iclass 30, count 0 2006.225.07:56:38.48#ibcon#read 4, iclass 30, count 0 2006.225.07:56:38.48#ibcon#about to read 5, iclass 30, count 0 2006.225.07:56:38.48#ibcon#read 5, iclass 30, count 0 2006.225.07:56:38.48#ibcon#about to read 6, iclass 30, count 0 2006.225.07:56:38.48#ibcon#read 6, iclass 30, count 0 2006.225.07:56:38.48#ibcon#end of sib2, iclass 30, count 0 2006.225.07:56:38.48#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:56:38.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:56:38.48#ibcon#[25=USB\r\n] 2006.225.07:56:38.48#ibcon#*before write, iclass 30, count 0 2006.225.07:56:38.48#ibcon#enter sib2, iclass 30, count 0 2006.225.07:56:38.48#ibcon#flushed, iclass 30, count 0 2006.225.07:56:38.48#ibcon#about to write, iclass 30, count 0 2006.225.07:56:38.48#ibcon#wrote, iclass 30, count 0 2006.225.07:56:38.48#ibcon#about to read 3, iclass 30, count 0 2006.225.07:56:38.51#ibcon#read 3, iclass 30, count 0 2006.225.07:56:38.51#ibcon#about to read 4, iclass 30, count 0 2006.225.07:56:38.51#ibcon#read 4, iclass 30, count 0 2006.225.07:56:38.51#ibcon#about to read 5, iclass 30, count 0 2006.225.07:56:38.51#ibcon#read 5, iclass 30, count 0 2006.225.07:56:38.51#ibcon#about to read 6, iclass 30, count 0 2006.225.07:56:38.51#ibcon#read 6, iclass 30, count 0 2006.225.07:56:38.51#ibcon#end of sib2, iclass 30, count 0 2006.225.07:56:38.51#ibcon#*after write, iclass 30, count 0 2006.225.07:56:38.51#ibcon#*before return 0, iclass 30, count 0 2006.225.07:56:38.51#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:56:38.51#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:56:38.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:56:38.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:56:38.51$vc4f8/valo=3,672.99 2006.225.07:56:38.51#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.07:56:38.51#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.07:56:38.51#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:38.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:56:38.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:56:38.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:56:38.51#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:56:38.51#ibcon#first serial, iclass 32, count 0 2006.225.07:56:38.51#ibcon#enter sib2, iclass 32, count 0 2006.225.07:56:38.51#ibcon#flushed, iclass 32, count 0 2006.225.07:56:38.51#ibcon#about to write, iclass 32, count 0 2006.225.07:56:38.51#ibcon#wrote, iclass 32, count 0 2006.225.07:56:38.51#ibcon#about to read 3, iclass 32, count 0 2006.225.07:56:38.53#ibcon#read 3, iclass 32, count 0 2006.225.07:56:38.53#ibcon#about to read 4, iclass 32, count 0 2006.225.07:56:38.53#ibcon#read 4, iclass 32, count 0 2006.225.07:56:38.53#ibcon#about to read 5, iclass 32, count 0 2006.225.07:56:38.53#ibcon#read 5, iclass 32, count 0 2006.225.07:56:38.53#ibcon#about to read 6, iclass 32, count 0 2006.225.07:56:38.53#ibcon#read 6, iclass 32, count 0 2006.225.07:56:38.53#ibcon#end of sib2, iclass 32, count 0 2006.225.07:56:38.53#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:56:38.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:56:38.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.07:56:38.53#ibcon#*before write, iclass 32, count 0 2006.225.07:56:38.53#ibcon#enter sib2, iclass 32, count 0 2006.225.07:56:38.53#ibcon#flushed, iclass 32, count 0 2006.225.07:56:38.53#ibcon#about to write, iclass 32, count 0 2006.225.07:56:38.53#ibcon#wrote, iclass 32, count 0 2006.225.07:56:38.53#ibcon#about to read 3, iclass 32, count 0 2006.225.07:56:38.58#ibcon#read 3, iclass 32, count 0 2006.225.07:56:38.58#ibcon#about to read 4, iclass 32, count 0 2006.225.07:56:38.58#ibcon#read 4, iclass 32, count 0 2006.225.07:56:38.58#ibcon#about to read 5, iclass 32, count 0 2006.225.07:56:38.58#ibcon#read 5, iclass 32, count 0 2006.225.07:56:38.58#ibcon#about to read 6, iclass 32, count 0 2006.225.07:56:38.58#ibcon#read 6, iclass 32, count 0 2006.225.07:56:38.58#ibcon#end of sib2, iclass 32, count 0 2006.225.07:56:38.58#ibcon#*after write, iclass 32, count 0 2006.225.07:56:38.58#ibcon#*before return 0, iclass 32, count 0 2006.225.07:56:38.58#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:56:38.58#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:56:38.58#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:56:38.58#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:56:38.58$vc4f8/va=3,6 2006.225.07:56:38.58#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.07:56:38.58#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.07:56:38.58#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:38.58#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:56:38.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:56:38.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:56:38.63#ibcon#enter wrdev, iclass 34, count 2 2006.225.07:56:38.63#ibcon#first serial, iclass 34, count 2 2006.225.07:56:38.63#ibcon#enter sib2, iclass 34, count 2 2006.225.07:56:38.63#ibcon#flushed, iclass 34, count 2 2006.225.07:56:38.63#ibcon#about to write, iclass 34, count 2 2006.225.07:56:38.63#ibcon#wrote, iclass 34, count 2 2006.225.07:56:38.63#ibcon#about to read 3, iclass 34, count 2 2006.225.07:56:38.65#ibcon#read 3, iclass 34, count 2 2006.225.07:56:38.65#ibcon#about to read 4, iclass 34, count 2 2006.225.07:56:38.65#ibcon#read 4, iclass 34, count 2 2006.225.07:56:38.65#ibcon#about to read 5, iclass 34, count 2 2006.225.07:56:38.65#ibcon#read 5, iclass 34, count 2 2006.225.07:56:38.65#ibcon#about to read 6, iclass 34, count 2 2006.225.07:56:38.65#ibcon#read 6, iclass 34, count 2 2006.225.07:56:38.65#ibcon#end of sib2, iclass 34, count 2 2006.225.07:56:38.65#ibcon#*mode == 0, iclass 34, count 2 2006.225.07:56:38.65#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.07:56:38.65#ibcon#[25=AT03-06\r\n] 2006.225.07:56:38.65#ibcon#*before write, iclass 34, count 2 2006.225.07:56:38.65#ibcon#enter sib2, iclass 34, count 2 2006.225.07:56:38.65#ibcon#flushed, iclass 34, count 2 2006.225.07:56:38.65#ibcon#about to write, iclass 34, count 2 2006.225.07:56:38.65#ibcon#wrote, iclass 34, count 2 2006.225.07:56:38.65#ibcon#about to read 3, iclass 34, count 2 2006.225.07:56:38.68#ibcon#read 3, iclass 34, count 2 2006.225.07:56:38.68#ibcon#about to read 4, iclass 34, count 2 2006.225.07:56:38.68#ibcon#read 4, iclass 34, count 2 2006.225.07:56:38.68#ibcon#about to read 5, iclass 34, count 2 2006.225.07:56:38.68#ibcon#read 5, iclass 34, count 2 2006.225.07:56:38.68#ibcon#about to read 6, iclass 34, count 2 2006.225.07:56:38.68#ibcon#read 6, iclass 34, count 2 2006.225.07:56:38.68#ibcon#end of sib2, iclass 34, count 2 2006.225.07:56:38.68#ibcon#*after write, iclass 34, count 2 2006.225.07:56:38.68#ibcon#*before return 0, iclass 34, count 2 2006.225.07:56:38.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:56:38.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:56:38.68#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.07:56:38.68#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:38.68#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:56:38.80#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:56:38.80#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:56:38.80#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:56:38.80#ibcon#first serial, iclass 34, count 0 2006.225.07:56:38.80#ibcon#enter sib2, iclass 34, count 0 2006.225.07:56:38.80#ibcon#flushed, iclass 34, count 0 2006.225.07:56:38.80#ibcon#about to write, iclass 34, count 0 2006.225.07:56:38.80#ibcon#wrote, iclass 34, count 0 2006.225.07:56:38.80#ibcon#about to read 3, iclass 34, count 0 2006.225.07:56:38.82#ibcon#read 3, iclass 34, count 0 2006.225.07:56:38.82#ibcon#about to read 4, iclass 34, count 0 2006.225.07:56:38.82#ibcon#read 4, iclass 34, count 0 2006.225.07:56:38.82#ibcon#about to read 5, iclass 34, count 0 2006.225.07:56:38.82#ibcon#read 5, iclass 34, count 0 2006.225.07:56:38.82#ibcon#about to read 6, iclass 34, count 0 2006.225.07:56:38.82#ibcon#read 6, iclass 34, count 0 2006.225.07:56:38.82#ibcon#end of sib2, iclass 34, count 0 2006.225.07:56:38.82#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:56:38.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:56:38.82#ibcon#[25=USB\r\n] 2006.225.07:56:38.82#ibcon#*before write, iclass 34, count 0 2006.225.07:56:38.82#ibcon#enter sib2, iclass 34, count 0 2006.225.07:56:38.82#ibcon#flushed, iclass 34, count 0 2006.225.07:56:38.82#ibcon#about to write, iclass 34, count 0 2006.225.07:56:38.82#ibcon#wrote, iclass 34, count 0 2006.225.07:56:38.82#ibcon#about to read 3, iclass 34, count 0 2006.225.07:56:38.85#ibcon#read 3, iclass 34, count 0 2006.225.07:56:38.85#ibcon#about to read 4, iclass 34, count 0 2006.225.07:56:38.85#ibcon#read 4, iclass 34, count 0 2006.225.07:56:38.85#ibcon#about to read 5, iclass 34, count 0 2006.225.07:56:38.85#ibcon#read 5, iclass 34, count 0 2006.225.07:56:38.85#ibcon#about to read 6, iclass 34, count 0 2006.225.07:56:38.85#ibcon#read 6, iclass 34, count 0 2006.225.07:56:38.85#ibcon#end of sib2, iclass 34, count 0 2006.225.07:56:38.85#ibcon#*after write, iclass 34, count 0 2006.225.07:56:38.85#ibcon#*before return 0, iclass 34, count 0 2006.225.07:56:38.85#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:56:38.85#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:56:38.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:56:38.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:56:38.85$vc4f8/valo=4,832.99 2006.225.07:56:38.85#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.07:56:38.85#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.07:56:38.85#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:38.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:56:38.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:56:38.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:56:38.85#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:56:38.85#ibcon#first serial, iclass 36, count 0 2006.225.07:56:38.85#ibcon#enter sib2, iclass 36, count 0 2006.225.07:56:38.85#ibcon#flushed, iclass 36, count 0 2006.225.07:56:38.85#ibcon#about to write, iclass 36, count 0 2006.225.07:56:38.85#ibcon#wrote, iclass 36, count 0 2006.225.07:56:38.85#ibcon#about to read 3, iclass 36, count 0 2006.225.07:56:38.87#ibcon#read 3, iclass 36, count 0 2006.225.07:56:38.87#ibcon#about to read 4, iclass 36, count 0 2006.225.07:56:38.87#ibcon#read 4, iclass 36, count 0 2006.225.07:56:38.87#ibcon#about to read 5, iclass 36, count 0 2006.225.07:56:38.87#ibcon#read 5, iclass 36, count 0 2006.225.07:56:38.87#ibcon#about to read 6, iclass 36, count 0 2006.225.07:56:38.87#ibcon#read 6, iclass 36, count 0 2006.225.07:56:38.87#ibcon#end of sib2, iclass 36, count 0 2006.225.07:56:38.87#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:56:38.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:56:38.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.07:56:38.87#ibcon#*before write, iclass 36, count 0 2006.225.07:56:38.87#ibcon#enter sib2, iclass 36, count 0 2006.225.07:56:38.87#ibcon#flushed, iclass 36, count 0 2006.225.07:56:38.87#ibcon#about to write, iclass 36, count 0 2006.225.07:56:38.87#ibcon#wrote, iclass 36, count 0 2006.225.07:56:38.87#ibcon#about to read 3, iclass 36, count 0 2006.225.07:56:38.92#ibcon#read 3, iclass 36, count 0 2006.225.07:56:38.92#ibcon#about to read 4, iclass 36, count 0 2006.225.07:56:38.92#ibcon#read 4, iclass 36, count 0 2006.225.07:56:38.92#ibcon#about to read 5, iclass 36, count 0 2006.225.07:56:38.92#ibcon#read 5, iclass 36, count 0 2006.225.07:56:38.92#ibcon#about to read 6, iclass 36, count 0 2006.225.07:56:38.92#ibcon#read 6, iclass 36, count 0 2006.225.07:56:38.92#ibcon#end of sib2, iclass 36, count 0 2006.225.07:56:38.92#ibcon#*after write, iclass 36, count 0 2006.225.07:56:38.92#ibcon#*before return 0, iclass 36, count 0 2006.225.07:56:38.92#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:56:38.92#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:56:38.92#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:56:38.92#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:56:38.92$vc4f8/va=4,7 2006.225.07:56:38.92#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.07:56:38.92#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.07:56:38.92#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:38.92#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:56:38.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:56:38.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:56:38.97#ibcon#enter wrdev, iclass 38, count 2 2006.225.07:56:38.97#ibcon#first serial, iclass 38, count 2 2006.225.07:56:38.97#ibcon#enter sib2, iclass 38, count 2 2006.225.07:56:38.97#ibcon#flushed, iclass 38, count 2 2006.225.07:56:38.97#ibcon#about to write, iclass 38, count 2 2006.225.07:56:38.97#ibcon#wrote, iclass 38, count 2 2006.225.07:56:38.97#ibcon#about to read 3, iclass 38, count 2 2006.225.07:56:38.99#ibcon#read 3, iclass 38, count 2 2006.225.07:56:38.99#ibcon#about to read 4, iclass 38, count 2 2006.225.07:56:38.99#ibcon#read 4, iclass 38, count 2 2006.225.07:56:38.99#ibcon#about to read 5, iclass 38, count 2 2006.225.07:56:38.99#ibcon#read 5, iclass 38, count 2 2006.225.07:56:38.99#ibcon#about to read 6, iclass 38, count 2 2006.225.07:56:38.99#ibcon#read 6, iclass 38, count 2 2006.225.07:56:38.99#ibcon#end of sib2, iclass 38, count 2 2006.225.07:56:38.99#ibcon#*mode == 0, iclass 38, count 2 2006.225.07:56:38.99#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.07:56:38.99#ibcon#[25=AT04-07\r\n] 2006.225.07:56:38.99#ibcon#*before write, iclass 38, count 2 2006.225.07:56:38.99#ibcon#enter sib2, iclass 38, count 2 2006.225.07:56:38.99#ibcon#flushed, iclass 38, count 2 2006.225.07:56:38.99#ibcon#about to write, iclass 38, count 2 2006.225.07:56:38.99#ibcon#wrote, iclass 38, count 2 2006.225.07:56:38.99#ibcon#about to read 3, iclass 38, count 2 2006.225.07:56:39.02#ibcon#read 3, iclass 38, count 2 2006.225.07:56:39.02#ibcon#about to read 4, iclass 38, count 2 2006.225.07:56:39.02#ibcon#read 4, iclass 38, count 2 2006.225.07:56:39.02#ibcon#about to read 5, iclass 38, count 2 2006.225.07:56:39.02#ibcon#read 5, iclass 38, count 2 2006.225.07:56:39.02#ibcon#about to read 6, iclass 38, count 2 2006.225.07:56:39.02#ibcon#read 6, iclass 38, count 2 2006.225.07:56:39.02#ibcon#end of sib2, iclass 38, count 2 2006.225.07:56:39.02#ibcon#*after write, iclass 38, count 2 2006.225.07:56:39.02#ibcon#*before return 0, iclass 38, count 2 2006.225.07:56:39.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:56:39.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:56:39.02#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.07:56:39.02#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:39.02#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:56:39.14#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:56:39.14#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:56:39.14#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:56:39.14#ibcon#first serial, iclass 38, count 0 2006.225.07:56:39.14#ibcon#enter sib2, iclass 38, count 0 2006.225.07:56:39.14#ibcon#flushed, iclass 38, count 0 2006.225.07:56:39.14#ibcon#about to write, iclass 38, count 0 2006.225.07:56:39.14#ibcon#wrote, iclass 38, count 0 2006.225.07:56:39.14#ibcon#about to read 3, iclass 38, count 0 2006.225.07:56:39.16#ibcon#read 3, iclass 38, count 0 2006.225.07:56:39.16#ibcon#about to read 4, iclass 38, count 0 2006.225.07:56:39.16#ibcon#read 4, iclass 38, count 0 2006.225.07:56:39.16#ibcon#about to read 5, iclass 38, count 0 2006.225.07:56:39.16#ibcon#read 5, iclass 38, count 0 2006.225.07:56:39.16#ibcon#about to read 6, iclass 38, count 0 2006.225.07:56:39.16#ibcon#read 6, iclass 38, count 0 2006.225.07:56:39.16#ibcon#end of sib2, iclass 38, count 0 2006.225.07:56:39.16#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:56:39.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:56:39.16#ibcon#[25=USB\r\n] 2006.225.07:56:39.16#ibcon#*before write, iclass 38, count 0 2006.225.07:56:39.16#ibcon#enter sib2, iclass 38, count 0 2006.225.07:56:39.16#ibcon#flushed, iclass 38, count 0 2006.225.07:56:39.16#ibcon#about to write, iclass 38, count 0 2006.225.07:56:39.16#ibcon#wrote, iclass 38, count 0 2006.225.07:56:39.16#ibcon#about to read 3, iclass 38, count 0 2006.225.07:56:39.19#ibcon#read 3, iclass 38, count 0 2006.225.07:56:39.19#ibcon#about to read 4, iclass 38, count 0 2006.225.07:56:39.19#ibcon#read 4, iclass 38, count 0 2006.225.07:56:39.19#ibcon#about to read 5, iclass 38, count 0 2006.225.07:56:39.19#ibcon#read 5, iclass 38, count 0 2006.225.07:56:39.19#ibcon#about to read 6, iclass 38, count 0 2006.225.07:56:39.19#ibcon#read 6, iclass 38, count 0 2006.225.07:56:39.19#ibcon#end of sib2, iclass 38, count 0 2006.225.07:56:39.19#ibcon#*after write, iclass 38, count 0 2006.225.07:56:39.19#ibcon#*before return 0, iclass 38, count 0 2006.225.07:56:39.19#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:56:39.19#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:56:39.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:56:39.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:56:39.19$vc4f8/valo=5,652.99 2006.225.07:56:39.19#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.07:56:39.19#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.07:56:39.19#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:39.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:56:39.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:56:39.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:56:39.19#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:56:39.19#ibcon#first serial, iclass 40, count 0 2006.225.07:56:39.19#ibcon#enter sib2, iclass 40, count 0 2006.225.07:56:39.19#ibcon#flushed, iclass 40, count 0 2006.225.07:56:39.19#ibcon#about to write, iclass 40, count 0 2006.225.07:56:39.19#ibcon#wrote, iclass 40, count 0 2006.225.07:56:39.19#ibcon#about to read 3, iclass 40, count 0 2006.225.07:56:39.21#ibcon#read 3, iclass 40, count 0 2006.225.07:56:39.21#ibcon#about to read 4, iclass 40, count 0 2006.225.07:56:39.21#ibcon#read 4, iclass 40, count 0 2006.225.07:56:39.21#ibcon#about to read 5, iclass 40, count 0 2006.225.07:56:39.21#ibcon#read 5, iclass 40, count 0 2006.225.07:56:39.21#ibcon#about to read 6, iclass 40, count 0 2006.225.07:56:39.21#ibcon#read 6, iclass 40, count 0 2006.225.07:56:39.21#ibcon#end of sib2, iclass 40, count 0 2006.225.07:56:39.21#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:56:39.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:56:39.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.07:56:39.21#ibcon#*before write, iclass 40, count 0 2006.225.07:56:39.21#ibcon#enter sib2, iclass 40, count 0 2006.225.07:56:39.21#ibcon#flushed, iclass 40, count 0 2006.225.07:56:39.21#ibcon#about to write, iclass 40, count 0 2006.225.07:56:39.21#ibcon#wrote, iclass 40, count 0 2006.225.07:56:39.21#ibcon#about to read 3, iclass 40, count 0 2006.225.07:56:39.25#ibcon#read 3, iclass 40, count 0 2006.225.07:56:39.25#ibcon#about to read 4, iclass 40, count 0 2006.225.07:56:39.25#ibcon#read 4, iclass 40, count 0 2006.225.07:56:39.25#ibcon#about to read 5, iclass 40, count 0 2006.225.07:56:39.25#ibcon#read 5, iclass 40, count 0 2006.225.07:56:39.25#ibcon#about to read 6, iclass 40, count 0 2006.225.07:56:39.25#ibcon#read 6, iclass 40, count 0 2006.225.07:56:39.25#ibcon#end of sib2, iclass 40, count 0 2006.225.07:56:39.25#ibcon#*after write, iclass 40, count 0 2006.225.07:56:39.25#ibcon#*before return 0, iclass 40, count 0 2006.225.07:56:39.25#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:56:39.25#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:56:39.25#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:56:39.25#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:56:39.25$vc4f8/va=5,7 2006.225.07:56:39.25#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.07:56:39.25#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.07:56:39.25#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:39.25#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:56:39.31#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:56:39.31#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:56:39.31#ibcon#enter wrdev, iclass 4, count 2 2006.225.07:56:39.31#ibcon#first serial, iclass 4, count 2 2006.225.07:56:39.31#ibcon#enter sib2, iclass 4, count 2 2006.225.07:56:39.31#ibcon#flushed, iclass 4, count 2 2006.225.07:56:39.31#ibcon#about to write, iclass 4, count 2 2006.225.07:56:39.31#ibcon#wrote, iclass 4, count 2 2006.225.07:56:39.31#ibcon#about to read 3, iclass 4, count 2 2006.225.07:56:39.33#ibcon#read 3, iclass 4, count 2 2006.225.07:56:39.33#ibcon#about to read 4, iclass 4, count 2 2006.225.07:56:39.33#ibcon#read 4, iclass 4, count 2 2006.225.07:56:39.33#ibcon#about to read 5, iclass 4, count 2 2006.225.07:56:39.33#ibcon#read 5, iclass 4, count 2 2006.225.07:56:39.33#ibcon#about to read 6, iclass 4, count 2 2006.225.07:56:39.33#ibcon#read 6, iclass 4, count 2 2006.225.07:56:39.33#ibcon#end of sib2, iclass 4, count 2 2006.225.07:56:39.33#ibcon#*mode == 0, iclass 4, count 2 2006.225.07:56:39.33#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.07:56:39.33#ibcon#[25=AT05-07\r\n] 2006.225.07:56:39.33#ibcon#*before write, iclass 4, count 2 2006.225.07:56:39.33#ibcon#enter sib2, iclass 4, count 2 2006.225.07:56:39.33#ibcon#flushed, iclass 4, count 2 2006.225.07:56:39.33#ibcon#about to write, iclass 4, count 2 2006.225.07:56:39.33#ibcon#wrote, iclass 4, count 2 2006.225.07:56:39.33#ibcon#about to read 3, iclass 4, count 2 2006.225.07:56:39.36#ibcon#read 3, iclass 4, count 2 2006.225.07:56:39.36#ibcon#about to read 4, iclass 4, count 2 2006.225.07:56:39.36#ibcon#read 4, iclass 4, count 2 2006.225.07:56:39.36#ibcon#about to read 5, iclass 4, count 2 2006.225.07:56:39.36#ibcon#read 5, iclass 4, count 2 2006.225.07:56:39.36#ibcon#about to read 6, iclass 4, count 2 2006.225.07:56:39.36#ibcon#read 6, iclass 4, count 2 2006.225.07:56:39.36#ibcon#end of sib2, iclass 4, count 2 2006.225.07:56:39.36#ibcon#*after write, iclass 4, count 2 2006.225.07:56:39.36#ibcon#*before return 0, iclass 4, count 2 2006.225.07:56:39.36#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:56:39.36#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.07:56:39.36#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.07:56:39.36#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:39.36#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:56:39.48#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:56:39.48#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:56:39.48#ibcon#enter wrdev, iclass 4, count 0 2006.225.07:56:39.48#ibcon#first serial, iclass 4, count 0 2006.225.07:56:39.48#ibcon#enter sib2, iclass 4, count 0 2006.225.07:56:39.48#ibcon#flushed, iclass 4, count 0 2006.225.07:56:39.48#ibcon#about to write, iclass 4, count 0 2006.225.07:56:39.48#ibcon#wrote, iclass 4, count 0 2006.225.07:56:39.48#ibcon#about to read 3, iclass 4, count 0 2006.225.07:56:39.50#ibcon#read 3, iclass 4, count 0 2006.225.07:56:39.50#ibcon#about to read 4, iclass 4, count 0 2006.225.07:56:39.50#ibcon#read 4, iclass 4, count 0 2006.225.07:56:39.50#ibcon#about to read 5, iclass 4, count 0 2006.225.07:56:39.50#ibcon#read 5, iclass 4, count 0 2006.225.07:56:39.50#ibcon#about to read 6, iclass 4, count 0 2006.225.07:56:39.50#ibcon#read 6, iclass 4, count 0 2006.225.07:56:39.50#ibcon#end of sib2, iclass 4, count 0 2006.225.07:56:39.50#ibcon#*mode == 0, iclass 4, count 0 2006.225.07:56:39.50#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.07:56:39.50#ibcon#[25=USB\r\n] 2006.225.07:56:39.50#ibcon#*before write, iclass 4, count 0 2006.225.07:56:39.50#ibcon#enter sib2, iclass 4, count 0 2006.225.07:56:39.50#ibcon#flushed, iclass 4, count 0 2006.225.07:56:39.50#ibcon#about to write, iclass 4, count 0 2006.225.07:56:39.50#ibcon#wrote, iclass 4, count 0 2006.225.07:56:39.50#ibcon#about to read 3, iclass 4, count 0 2006.225.07:56:39.53#ibcon#read 3, iclass 4, count 0 2006.225.07:56:39.53#ibcon#about to read 4, iclass 4, count 0 2006.225.07:56:39.53#ibcon#read 4, iclass 4, count 0 2006.225.07:56:39.53#ibcon#about to read 5, iclass 4, count 0 2006.225.07:56:39.53#ibcon#read 5, iclass 4, count 0 2006.225.07:56:39.53#ibcon#about to read 6, iclass 4, count 0 2006.225.07:56:39.53#ibcon#read 6, iclass 4, count 0 2006.225.07:56:39.53#ibcon#end of sib2, iclass 4, count 0 2006.225.07:56:39.53#ibcon#*after write, iclass 4, count 0 2006.225.07:56:39.53#ibcon#*before return 0, iclass 4, count 0 2006.225.07:56:39.53#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:56:39.53#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.07:56:39.53#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.07:56:39.53#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.07:56:39.53$vc4f8/valo=6,772.99 2006.225.07:56:39.53#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.07:56:39.53#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.07:56:39.53#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:39.53#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:56:39.53#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:56:39.53#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:56:39.53#ibcon#enter wrdev, iclass 6, count 0 2006.225.07:56:39.53#ibcon#first serial, iclass 6, count 0 2006.225.07:56:39.53#ibcon#enter sib2, iclass 6, count 0 2006.225.07:56:39.53#ibcon#flushed, iclass 6, count 0 2006.225.07:56:39.53#ibcon#about to write, iclass 6, count 0 2006.225.07:56:39.53#ibcon#wrote, iclass 6, count 0 2006.225.07:56:39.53#ibcon#about to read 3, iclass 6, count 0 2006.225.07:56:39.55#ibcon#read 3, iclass 6, count 0 2006.225.07:56:39.55#ibcon#about to read 4, iclass 6, count 0 2006.225.07:56:39.55#ibcon#read 4, iclass 6, count 0 2006.225.07:56:39.55#ibcon#about to read 5, iclass 6, count 0 2006.225.07:56:39.55#ibcon#read 5, iclass 6, count 0 2006.225.07:56:39.55#ibcon#about to read 6, iclass 6, count 0 2006.225.07:56:39.55#ibcon#read 6, iclass 6, count 0 2006.225.07:56:39.55#ibcon#end of sib2, iclass 6, count 0 2006.225.07:56:39.55#ibcon#*mode == 0, iclass 6, count 0 2006.225.07:56:39.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.07:56:39.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.07:56:39.55#ibcon#*before write, iclass 6, count 0 2006.225.07:56:39.55#ibcon#enter sib2, iclass 6, count 0 2006.225.07:56:39.55#ibcon#flushed, iclass 6, count 0 2006.225.07:56:39.55#ibcon#about to write, iclass 6, count 0 2006.225.07:56:39.55#ibcon#wrote, iclass 6, count 0 2006.225.07:56:39.55#ibcon#about to read 3, iclass 6, count 0 2006.225.07:56:39.60#ibcon#read 3, iclass 6, count 0 2006.225.07:56:39.60#ibcon#about to read 4, iclass 6, count 0 2006.225.07:56:39.60#ibcon#read 4, iclass 6, count 0 2006.225.07:56:39.60#ibcon#about to read 5, iclass 6, count 0 2006.225.07:56:39.60#ibcon#read 5, iclass 6, count 0 2006.225.07:56:39.60#ibcon#about to read 6, iclass 6, count 0 2006.225.07:56:39.60#ibcon#read 6, iclass 6, count 0 2006.225.07:56:39.60#ibcon#end of sib2, iclass 6, count 0 2006.225.07:56:39.60#ibcon#*after write, iclass 6, count 0 2006.225.07:56:39.60#ibcon#*before return 0, iclass 6, count 0 2006.225.07:56:39.60#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:56:39.60#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.07:56:39.60#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.07:56:39.60#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.07:56:39.60$vc4f8/va=6,6 2006.225.07:56:39.60#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.225.07:56:39.60#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.225.07:56:39.60#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:39.60#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:56:39.65#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:56:39.65#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:56:39.65#ibcon#enter wrdev, iclass 10, count 2 2006.225.07:56:39.65#ibcon#first serial, iclass 10, count 2 2006.225.07:56:39.65#ibcon#enter sib2, iclass 10, count 2 2006.225.07:56:39.65#ibcon#flushed, iclass 10, count 2 2006.225.07:56:39.65#ibcon#about to write, iclass 10, count 2 2006.225.07:56:39.65#ibcon#wrote, iclass 10, count 2 2006.225.07:56:39.65#ibcon#about to read 3, iclass 10, count 2 2006.225.07:56:39.67#ibcon#read 3, iclass 10, count 2 2006.225.07:56:39.67#ibcon#about to read 4, iclass 10, count 2 2006.225.07:56:39.67#ibcon#read 4, iclass 10, count 2 2006.225.07:56:39.67#ibcon#about to read 5, iclass 10, count 2 2006.225.07:56:39.67#ibcon#read 5, iclass 10, count 2 2006.225.07:56:39.67#ibcon#about to read 6, iclass 10, count 2 2006.225.07:56:39.67#ibcon#read 6, iclass 10, count 2 2006.225.07:56:39.67#ibcon#end of sib2, iclass 10, count 2 2006.225.07:56:39.67#ibcon#*mode == 0, iclass 10, count 2 2006.225.07:56:39.67#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.225.07:56:39.67#ibcon#[25=AT06-06\r\n] 2006.225.07:56:39.67#ibcon#*before write, iclass 10, count 2 2006.225.07:56:39.67#ibcon#enter sib2, iclass 10, count 2 2006.225.07:56:39.67#ibcon#flushed, iclass 10, count 2 2006.225.07:56:39.67#ibcon#about to write, iclass 10, count 2 2006.225.07:56:39.67#ibcon#wrote, iclass 10, count 2 2006.225.07:56:39.67#ibcon#about to read 3, iclass 10, count 2 2006.225.07:56:39.70#ibcon#read 3, iclass 10, count 2 2006.225.07:56:39.70#ibcon#about to read 4, iclass 10, count 2 2006.225.07:56:39.70#ibcon#read 4, iclass 10, count 2 2006.225.07:56:39.70#ibcon#about to read 5, iclass 10, count 2 2006.225.07:56:39.70#ibcon#read 5, iclass 10, count 2 2006.225.07:56:39.70#ibcon#about to read 6, iclass 10, count 2 2006.225.07:56:39.70#ibcon#read 6, iclass 10, count 2 2006.225.07:56:39.70#ibcon#end of sib2, iclass 10, count 2 2006.225.07:56:39.70#ibcon#*after write, iclass 10, count 2 2006.225.07:56:39.70#ibcon#*before return 0, iclass 10, count 2 2006.225.07:56:39.70#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:56:39.70#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.225.07:56:39.70#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.225.07:56:39.70#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:39.70#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:56:39.82#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:56:39.82#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:56:39.82#ibcon#enter wrdev, iclass 10, count 0 2006.225.07:56:39.82#ibcon#first serial, iclass 10, count 0 2006.225.07:56:39.82#ibcon#enter sib2, iclass 10, count 0 2006.225.07:56:39.82#ibcon#flushed, iclass 10, count 0 2006.225.07:56:39.82#ibcon#about to write, iclass 10, count 0 2006.225.07:56:39.82#ibcon#wrote, iclass 10, count 0 2006.225.07:56:39.82#ibcon#about to read 3, iclass 10, count 0 2006.225.07:56:39.84#ibcon#read 3, iclass 10, count 0 2006.225.07:56:39.84#ibcon#about to read 4, iclass 10, count 0 2006.225.07:56:39.84#ibcon#read 4, iclass 10, count 0 2006.225.07:56:39.84#ibcon#about to read 5, iclass 10, count 0 2006.225.07:56:39.84#ibcon#read 5, iclass 10, count 0 2006.225.07:56:39.84#ibcon#about to read 6, iclass 10, count 0 2006.225.07:56:39.84#ibcon#read 6, iclass 10, count 0 2006.225.07:56:39.84#ibcon#end of sib2, iclass 10, count 0 2006.225.07:56:39.84#ibcon#*mode == 0, iclass 10, count 0 2006.225.07:56:39.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.07:56:39.84#ibcon#[25=USB\r\n] 2006.225.07:56:39.84#ibcon#*before write, iclass 10, count 0 2006.225.07:56:39.84#ibcon#enter sib2, iclass 10, count 0 2006.225.07:56:39.84#ibcon#flushed, iclass 10, count 0 2006.225.07:56:39.84#ibcon#about to write, iclass 10, count 0 2006.225.07:56:39.84#ibcon#wrote, iclass 10, count 0 2006.225.07:56:39.84#ibcon#about to read 3, iclass 10, count 0 2006.225.07:56:39.87#ibcon#read 3, iclass 10, count 0 2006.225.07:56:39.87#ibcon#about to read 4, iclass 10, count 0 2006.225.07:56:39.87#ibcon#read 4, iclass 10, count 0 2006.225.07:56:39.87#ibcon#about to read 5, iclass 10, count 0 2006.225.07:56:39.87#ibcon#read 5, iclass 10, count 0 2006.225.07:56:39.87#ibcon#about to read 6, iclass 10, count 0 2006.225.07:56:39.87#ibcon#read 6, iclass 10, count 0 2006.225.07:56:39.87#ibcon#end of sib2, iclass 10, count 0 2006.225.07:56:39.87#ibcon#*after write, iclass 10, count 0 2006.225.07:56:39.87#ibcon#*before return 0, iclass 10, count 0 2006.225.07:56:39.87#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:56:39.87#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.225.07:56:39.87#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.07:56:39.87#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.07:56:39.87$vc4f8/valo=7,832.99 2006.225.07:56:39.87#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.07:56:39.87#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.07:56:39.87#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:39.87#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:56:39.87#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:56:39.87#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:56:39.87#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:56:39.87#ibcon#first serial, iclass 12, count 0 2006.225.07:56:39.87#ibcon#enter sib2, iclass 12, count 0 2006.225.07:56:39.87#ibcon#flushed, iclass 12, count 0 2006.225.07:56:39.87#ibcon#about to write, iclass 12, count 0 2006.225.07:56:39.87#ibcon#wrote, iclass 12, count 0 2006.225.07:56:39.87#ibcon#about to read 3, iclass 12, count 0 2006.225.07:56:39.89#ibcon#read 3, iclass 12, count 0 2006.225.07:56:39.89#ibcon#about to read 4, iclass 12, count 0 2006.225.07:56:39.89#ibcon#read 4, iclass 12, count 0 2006.225.07:56:39.89#ibcon#about to read 5, iclass 12, count 0 2006.225.07:56:39.89#ibcon#read 5, iclass 12, count 0 2006.225.07:56:39.89#ibcon#about to read 6, iclass 12, count 0 2006.225.07:56:39.89#ibcon#read 6, iclass 12, count 0 2006.225.07:56:39.89#ibcon#end of sib2, iclass 12, count 0 2006.225.07:56:39.89#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:56:39.89#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:56:39.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.07:56:39.89#ibcon#*before write, iclass 12, count 0 2006.225.07:56:39.89#ibcon#enter sib2, iclass 12, count 0 2006.225.07:56:39.89#ibcon#flushed, iclass 12, count 0 2006.225.07:56:39.89#ibcon#about to write, iclass 12, count 0 2006.225.07:56:39.89#ibcon#wrote, iclass 12, count 0 2006.225.07:56:39.89#ibcon#about to read 3, iclass 12, count 0 2006.225.07:56:39.93#ibcon#read 3, iclass 12, count 0 2006.225.07:56:39.93#ibcon#about to read 4, iclass 12, count 0 2006.225.07:56:39.93#ibcon#read 4, iclass 12, count 0 2006.225.07:56:39.93#ibcon#about to read 5, iclass 12, count 0 2006.225.07:56:39.93#ibcon#read 5, iclass 12, count 0 2006.225.07:56:39.93#ibcon#about to read 6, iclass 12, count 0 2006.225.07:56:39.93#ibcon#read 6, iclass 12, count 0 2006.225.07:56:39.93#ibcon#end of sib2, iclass 12, count 0 2006.225.07:56:39.93#ibcon#*after write, iclass 12, count 0 2006.225.07:56:39.93#ibcon#*before return 0, iclass 12, count 0 2006.225.07:56:39.93#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:56:39.93#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:56:39.93#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:56:39.93#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:56:39.93$vc4f8/va=7,6 2006.225.07:56:39.93#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.225.07:56:39.93#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.225.07:56:39.93#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:39.93#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:56:39.99#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:56:39.99#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:56:39.99#ibcon#enter wrdev, iclass 14, count 2 2006.225.07:56:39.99#ibcon#first serial, iclass 14, count 2 2006.225.07:56:39.99#ibcon#enter sib2, iclass 14, count 2 2006.225.07:56:39.99#ibcon#flushed, iclass 14, count 2 2006.225.07:56:39.99#ibcon#about to write, iclass 14, count 2 2006.225.07:56:39.99#ibcon#wrote, iclass 14, count 2 2006.225.07:56:39.99#ibcon#about to read 3, iclass 14, count 2 2006.225.07:56:40.01#ibcon#read 3, iclass 14, count 2 2006.225.07:56:40.01#ibcon#about to read 4, iclass 14, count 2 2006.225.07:56:40.01#ibcon#read 4, iclass 14, count 2 2006.225.07:56:40.01#ibcon#about to read 5, iclass 14, count 2 2006.225.07:56:40.01#ibcon#read 5, iclass 14, count 2 2006.225.07:56:40.01#ibcon#about to read 6, iclass 14, count 2 2006.225.07:56:40.01#ibcon#read 6, iclass 14, count 2 2006.225.07:56:40.01#ibcon#end of sib2, iclass 14, count 2 2006.225.07:56:40.01#ibcon#*mode == 0, iclass 14, count 2 2006.225.07:56:40.01#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.225.07:56:40.01#ibcon#[25=AT07-06\r\n] 2006.225.07:56:40.01#ibcon#*before write, iclass 14, count 2 2006.225.07:56:40.01#ibcon#enter sib2, iclass 14, count 2 2006.225.07:56:40.01#ibcon#flushed, iclass 14, count 2 2006.225.07:56:40.01#ibcon#about to write, iclass 14, count 2 2006.225.07:56:40.01#ibcon#wrote, iclass 14, count 2 2006.225.07:56:40.01#ibcon#about to read 3, iclass 14, count 2 2006.225.07:56:40.04#ibcon#read 3, iclass 14, count 2 2006.225.07:56:40.04#ibcon#about to read 4, iclass 14, count 2 2006.225.07:56:40.04#ibcon#read 4, iclass 14, count 2 2006.225.07:56:40.04#ibcon#about to read 5, iclass 14, count 2 2006.225.07:56:40.04#ibcon#read 5, iclass 14, count 2 2006.225.07:56:40.04#ibcon#about to read 6, iclass 14, count 2 2006.225.07:56:40.04#ibcon#read 6, iclass 14, count 2 2006.225.07:56:40.04#ibcon#end of sib2, iclass 14, count 2 2006.225.07:56:40.04#ibcon#*after write, iclass 14, count 2 2006.225.07:56:40.04#ibcon#*before return 0, iclass 14, count 2 2006.225.07:56:40.04#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:56:40.04#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.225.07:56:40.04#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.225.07:56:40.04#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:40.04#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:56:40.16#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:56:40.16#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:56:40.16#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:56:40.16#ibcon#first serial, iclass 14, count 0 2006.225.07:56:40.16#ibcon#enter sib2, iclass 14, count 0 2006.225.07:56:40.16#ibcon#flushed, iclass 14, count 0 2006.225.07:56:40.16#ibcon#about to write, iclass 14, count 0 2006.225.07:56:40.16#ibcon#wrote, iclass 14, count 0 2006.225.07:56:40.16#ibcon#about to read 3, iclass 14, count 0 2006.225.07:56:40.18#ibcon#read 3, iclass 14, count 0 2006.225.07:56:40.18#ibcon#about to read 4, iclass 14, count 0 2006.225.07:56:40.18#ibcon#read 4, iclass 14, count 0 2006.225.07:56:40.18#ibcon#about to read 5, iclass 14, count 0 2006.225.07:56:40.18#ibcon#read 5, iclass 14, count 0 2006.225.07:56:40.18#ibcon#about to read 6, iclass 14, count 0 2006.225.07:56:40.18#ibcon#read 6, iclass 14, count 0 2006.225.07:56:40.18#ibcon#end of sib2, iclass 14, count 0 2006.225.07:56:40.18#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:56:40.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:56:40.18#ibcon#[25=USB\r\n] 2006.225.07:56:40.18#ibcon#*before write, iclass 14, count 0 2006.225.07:56:40.18#ibcon#enter sib2, iclass 14, count 0 2006.225.07:56:40.18#ibcon#flushed, iclass 14, count 0 2006.225.07:56:40.18#ibcon#about to write, iclass 14, count 0 2006.225.07:56:40.18#ibcon#wrote, iclass 14, count 0 2006.225.07:56:40.18#ibcon#about to read 3, iclass 14, count 0 2006.225.07:56:40.21#ibcon#read 3, iclass 14, count 0 2006.225.07:56:40.21#ibcon#about to read 4, iclass 14, count 0 2006.225.07:56:40.21#ibcon#read 4, iclass 14, count 0 2006.225.07:56:40.21#ibcon#about to read 5, iclass 14, count 0 2006.225.07:56:40.21#ibcon#read 5, iclass 14, count 0 2006.225.07:56:40.21#ibcon#about to read 6, iclass 14, count 0 2006.225.07:56:40.21#ibcon#read 6, iclass 14, count 0 2006.225.07:56:40.21#ibcon#end of sib2, iclass 14, count 0 2006.225.07:56:40.21#ibcon#*after write, iclass 14, count 0 2006.225.07:56:40.21#ibcon#*before return 0, iclass 14, count 0 2006.225.07:56:40.21#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:56:40.21#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.225.07:56:40.21#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:56:40.21#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:56:40.21$vc4f8/valo=8,852.99 2006.225.07:56:40.21#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.07:56:40.21#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.07:56:40.21#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:40.21#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:56:40.21#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:56:40.21#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:56:40.21#ibcon#enter wrdev, iclass 16, count 0 2006.225.07:56:40.21#ibcon#first serial, iclass 16, count 0 2006.225.07:56:40.21#ibcon#enter sib2, iclass 16, count 0 2006.225.07:56:40.21#ibcon#flushed, iclass 16, count 0 2006.225.07:56:40.21#ibcon#about to write, iclass 16, count 0 2006.225.07:56:40.21#ibcon#wrote, iclass 16, count 0 2006.225.07:56:40.21#ibcon#about to read 3, iclass 16, count 0 2006.225.07:56:40.23#ibcon#read 3, iclass 16, count 0 2006.225.07:56:40.23#ibcon#about to read 4, iclass 16, count 0 2006.225.07:56:40.23#ibcon#read 4, iclass 16, count 0 2006.225.07:56:40.23#ibcon#about to read 5, iclass 16, count 0 2006.225.07:56:40.23#ibcon#read 5, iclass 16, count 0 2006.225.07:56:40.23#ibcon#about to read 6, iclass 16, count 0 2006.225.07:56:40.23#ibcon#read 6, iclass 16, count 0 2006.225.07:56:40.23#ibcon#end of sib2, iclass 16, count 0 2006.225.07:56:40.23#ibcon#*mode == 0, iclass 16, count 0 2006.225.07:56:40.23#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.07:56:40.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.07:56:40.23#ibcon#*before write, iclass 16, count 0 2006.225.07:56:40.23#ibcon#enter sib2, iclass 16, count 0 2006.225.07:56:40.23#ibcon#flushed, iclass 16, count 0 2006.225.07:56:40.23#ibcon#about to write, iclass 16, count 0 2006.225.07:56:40.23#ibcon#wrote, iclass 16, count 0 2006.225.07:56:40.23#ibcon#about to read 3, iclass 16, count 0 2006.225.07:56:40.27#ibcon#read 3, iclass 16, count 0 2006.225.07:56:40.27#ibcon#about to read 4, iclass 16, count 0 2006.225.07:56:40.27#ibcon#read 4, iclass 16, count 0 2006.225.07:56:40.27#ibcon#about to read 5, iclass 16, count 0 2006.225.07:56:40.27#ibcon#read 5, iclass 16, count 0 2006.225.07:56:40.27#ibcon#about to read 6, iclass 16, count 0 2006.225.07:56:40.27#ibcon#read 6, iclass 16, count 0 2006.225.07:56:40.27#ibcon#end of sib2, iclass 16, count 0 2006.225.07:56:40.27#ibcon#*after write, iclass 16, count 0 2006.225.07:56:40.27#ibcon#*before return 0, iclass 16, count 0 2006.225.07:56:40.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:56:40.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.07:56:40.27#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.07:56:40.27#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.07:56:40.27$vc4f8/va=8,7 2006.225.07:56:40.27#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.225.07:56:40.27#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.225.07:56:40.27#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:40.27#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:56:40.33#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:56:40.33#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:56:40.33#ibcon#enter wrdev, iclass 18, count 2 2006.225.07:56:40.33#ibcon#first serial, iclass 18, count 2 2006.225.07:56:40.33#ibcon#enter sib2, iclass 18, count 2 2006.225.07:56:40.33#ibcon#flushed, iclass 18, count 2 2006.225.07:56:40.33#ibcon#about to write, iclass 18, count 2 2006.225.07:56:40.33#ibcon#wrote, iclass 18, count 2 2006.225.07:56:40.33#ibcon#about to read 3, iclass 18, count 2 2006.225.07:56:40.35#ibcon#read 3, iclass 18, count 2 2006.225.07:56:40.35#ibcon#about to read 4, iclass 18, count 2 2006.225.07:56:40.35#ibcon#read 4, iclass 18, count 2 2006.225.07:56:40.35#ibcon#about to read 5, iclass 18, count 2 2006.225.07:56:40.35#ibcon#read 5, iclass 18, count 2 2006.225.07:56:40.35#ibcon#about to read 6, iclass 18, count 2 2006.225.07:56:40.35#ibcon#read 6, iclass 18, count 2 2006.225.07:56:40.35#ibcon#end of sib2, iclass 18, count 2 2006.225.07:56:40.35#ibcon#*mode == 0, iclass 18, count 2 2006.225.07:56:40.35#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.225.07:56:40.35#ibcon#[25=AT08-07\r\n] 2006.225.07:56:40.35#ibcon#*before write, iclass 18, count 2 2006.225.07:56:40.35#ibcon#enter sib2, iclass 18, count 2 2006.225.07:56:40.35#ibcon#flushed, iclass 18, count 2 2006.225.07:56:40.35#ibcon#about to write, iclass 18, count 2 2006.225.07:56:40.35#ibcon#wrote, iclass 18, count 2 2006.225.07:56:40.35#ibcon#about to read 3, iclass 18, count 2 2006.225.07:56:40.38#ibcon#read 3, iclass 18, count 2 2006.225.07:56:40.38#ibcon#about to read 4, iclass 18, count 2 2006.225.07:56:40.38#ibcon#read 4, iclass 18, count 2 2006.225.07:56:40.38#ibcon#about to read 5, iclass 18, count 2 2006.225.07:56:40.38#ibcon#read 5, iclass 18, count 2 2006.225.07:56:40.38#ibcon#about to read 6, iclass 18, count 2 2006.225.07:56:40.38#ibcon#read 6, iclass 18, count 2 2006.225.07:56:40.38#ibcon#end of sib2, iclass 18, count 2 2006.225.07:56:40.38#ibcon#*after write, iclass 18, count 2 2006.225.07:56:40.38#ibcon#*before return 0, iclass 18, count 2 2006.225.07:56:40.38#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:56:40.38#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.225.07:56:40.38#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.225.07:56:40.38#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:40.38#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:56:40.50#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:56:40.50#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:56:40.50#ibcon#enter wrdev, iclass 18, count 0 2006.225.07:56:40.50#ibcon#first serial, iclass 18, count 0 2006.225.07:56:40.50#ibcon#enter sib2, iclass 18, count 0 2006.225.07:56:40.50#ibcon#flushed, iclass 18, count 0 2006.225.07:56:40.50#ibcon#about to write, iclass 18, count 0 2006.225.07:56:40.50#ibcon#wrote, iclass 18, count 0 2006.225.07:56:40.50#ibcon#about to read 3, iclass 18, count 0 2006.225.07:56:40.52#ibcon#read 3, iclass 18, count 0 2006.225.07:56:40.52#ibcon#about to read 4, iclass 18, count 0 2006.225.07:56:40.52#ibcon#read 4, iclass 18, count 0 2006.225.07:56:40.52#ibcon#about to read 5, iclass 18, count 0 2006.225.07:56:40.52#ibcon#read 5, iclass 18, count 0 2006.225.07:56:40.52#ibcon#about to read 6, iclass 18, count 0 2006.225.07:56:40.52#ibcon#read 6, iclass 18, count 0 2006.225.07:56:40.52#ibcon#end of sib2, iclass 18, count 0 2006.225.07:56:40.52#ibcon#*mode == 0, iclass 18, count 0 2006.225.07:56:40.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.07:56:40.52#ibcon#[25=USB\r\n] 2006.225.07:56:40.52#ibcon#*before write, iclass 18, count 0 2006.225.07:56:40.52#ibcon#enter sib2, iclass 18, count 0 2006.225.07:56:40.52#ibcon#flushed, iclass 18, count 0 2006.225.07:56:40.52#ibcon#about to write, iclass 18, count 0 2006.225.07:56:40.52#ibcon#wrote, iclass 18, count 0 2006.225.07:56:40.52#ibcon#about to read 3, iclass 18, count 0 2006.225.07:56:40.55#ibcon#read 3, iclass 18, count 0 2006.225.07:56:40.55#ibcon#about to read 4, iclass 18, count 0 2006.225.07:56:40.55#ibcon#read 4, iclass 18, count 0 2006.225.07:56:40.55#ibcon#about to read 5, iclass 18, count 0 2006.225.07:56:40.55#ibcon#read 5, iclass 18, count 0 2006.225.07:56:40.55#ibcon#about to read 6, iclass 18, count 0 2006.225.07:56:40.55#ibcon#read 6, iclass 18, count 0 2006.225.07:56:40.55#ibcon#end of sib2, iclass 18, count 0 2006.225.07:56:40.55#ibcon#*after write, iclass 18, count 0 2006.225.07:56:40.55#ibcon#*before return 0, iclass 18, count 0 2006.225.07:56:40.55#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:56:40.55#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.225.07:56:40.55#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.07:56:40.55#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.07:56:40.55$vc4f8/vblo=1,632.99 2006.225.07:56:40.55#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.225.07:56:40.55#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.225.07:56:40.55#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:40.55#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:56:40.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:56:40.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:56:40.55#ibcon#enter wrdev, iclass 20, count 0 2006.225.07:56:40.55#ibcon#first serial, iclass 20, count 0 2006.225.07:56:40.55#ibcon#enter sib2, iclass 20, count 0 2006.225.07:56:40.55#ibcon#flushed, iclass 20, count 0 2006.225.07:56:40.55#ibcon#about to write, iclass 20, count 0 2006.225.07:56:40.55#ibcon#wrote, iclass 20, count 0 2006.225.07:56:40.55#ibcon#about to read 3, iclass 20, count 0 2006.225.07:56:40.57#ibcon#read 3, iclass 20, count 0 2006.225.07:56:40.57#ibcon#about to read 4, iclass 20, count 0 2006.225.07:56:40.57#ibcon#read 4, iclass 20, count 0 2006.225.07:56:40.57#ibcon#about to read 5, iclass 20, count 0 2006.225.07:56:40.57#ibcon#read 5, iclass 20, count 0 2006.225.07:56:40.57#ibcon#about to read 6, iclass 20, count 0 2006.225.07:56:40.57#ibcon#read 6, iclass 20, count 0 2006.225.07:56:40.57#ibcon#end of sib2, iclass 20, count 0 2006.225.07:56:40.57#ibcon#*mode == 0, iclass 20, count 0 2006.225.07:56:40.57#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.07:56:40.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.07:56:40.57#ibcon#*before write, iclass 20, count 0 2006.225.07:56:40.57#ibcon#enter sib2, iclass 20, count 0 2006.225.07:56:40.57#ibcon#flushed, iclass 20, count 0 2006.225.07:56:40.57#ibcon#about to write, iclass 20, count 0 2006.225.07:56:40.57#ibcon#wrote, iclass 20, count 0 2006.225.07:56:40.57#ibcon#about to read 3, iclass 20, count 0 2006.225.07:56:40.61#ibcon#read 3, iclass 20, count 0 2006.225.07:56:40.61#ibcon#about to read 4, iclass 20, count 0 2006.225.07:56:40.61#ibcon#read 4, iclass 20, count 0 2006.225.07:56:40.61#ibcon#about to read 5, iclass 20, count 0 2006.225.07:56:40.61#ibcon#read 5, iclass 20, count 0 2006.225.07:56:40.61#ibcon#about to read 6, iclass 20, count 0 2006.225.07:56:40.61#ibcon#read 6, iclass 20, count 0 2006.225.07:56:40.61#ibcon#end of sib2, iclass 20, count 0 2006.225.07:56:40.61#ibcon#*after write, iclass 20, count 0 2006.225.07:56:40.61#ibcon#*before return 0, iclass 20, count 0 2006.225.07:56:40.61#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:56:40.61#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.225.07:56:40.61#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.07:56:40.61#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.07:56:40.61$vc4f8/vb=1,4 2006.225.07:56:40.61#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.225.07:56:40.61#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.225.07:56:40.61#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:40.61#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:56:40.61#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:56:40.61#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:56:40.61#ibcon#enter wrdev, iclass 22, count 2 2006.225.07:56:40.61#ibcon#first serial, iclass 22, count 2 2006.225.07:56:40.61#ibcon#enter sib2, iclass 22, count 2 2006.225.07:56:40.61#ibcon#flushed, iclass 22, count 2 2006.225.07:56:40.61#ibcon#about to write, iclass 22, count 2 2006.225.07:56:40.61#ibcon#wrote, iclass 22, count 2 2006.225.07:56:40.61#ibcon#about to read 3, iclass 22, count 2 2006.225.07:56:40.63#ibcon#read 3, iclass 22, count 2 2006.225.07:56:40.63#ibcon#about to read 4, iclass 22, count 2 2006.225.07:56:40.63#ibcon#read 4, iclass 22, count 2 2006.225.07:56:40.63#ibcon#about to read 5, iclass 22, count 2 2006.225.07:56:40.63#ibcon#read 5, iclass 22, count 2 2006.225.07:56:40.63#ibcon#about to read 6, iclass 22, count 2 2006.225.07:56:40.63#ibcon#read 6, iclass 22, count 2 2006.225.07:56:40.63#ibcon#end of sib2, iclass 22, count 2 2006.225.07:56:40.63#ibcon#*mode == 0, iclass 22, count 2 2006.225.07:56:40.63#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.225.07:56:40.63#ibcon#[27=AT01-04\r\n] 2006.225.07:56:40.63#ibcon#*before write, iclass 22, count 2 2006.225.07:56:40.63#ibcon#enter sib2, iclass 22, count 2 2006.225.07:56:40.63#ibcon#flushed, iclass 22, count 2 2006.225.07:56:40.63#ibcon#about to write, iclass 22, count 2 2006.225.07:56:40.63#ibcon#wrote, iclass 22, count 2 2006.225.07:56:40.63#ibcon#about to read 3, iclass 22, count 2 2006.225.07:56:40.66#ibcon#read 3, iclass 22, count 2 2006.225.07:56:40.66#ibcon#about to read 4, iclass 22, count 2 2006.225.07:56:40.66#ibcon#read 4, iclass 22, count 2 2006.225.07:56:40.66#ibcon#about to read 5, iclass 22, count 2 2006.225.07:56:40.66#ibcon#read 5, iclass 22, count 2 2006.225.07:56:40.66#ibcon#about to read 6, iclass 22, count 2 2006.225.07:56:40.66#ibcon#read 6, iclass 22, count 2 2006.225.07:56:40.66#ibcon#end of sib2, iclass 22, count 2 2006.225.07:56:40.66#ibcon#*after write, iclass 22, count 2 2006.225.07:56:40.66#ibcon#*before return 0, iclass 22, count 2 2006.225.07:56:40.66#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:56:40.66#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.225.07:56:40.66#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.225.07:56:40.66#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:40.66#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:56:40.78#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:56:40.78#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:56:40.78#ibcon#enter wrdev, iclass 22, count 0 2006.225.07:56:40.78#ibcon#first serial, iclass 22, count 0 2006.225.07:56:40.78#ibcon#enter sib2, iclass 22, count 0 2006.225.07:56:40.78#ibcon#flushed, iclass 22, count 0 2006.225.07:56:40.78#ibcon#about to write, iclass 22, count 0 2006.225.07:56:40.78#ibcon#wrote, iclass 22, count 0 2006.225.07:56:40.78#ibcon#about to read 3, iclass 22, count 0 2006.225.07:56:40.80#ibcon#read 3, iclass 22, count 0 2006.225.07:56:40.80#ibcon#about to read 4, iclass 22, count 0 2006.225.07:56:40.80#ibcon#read 4, iclass 22, count 0 2006.225.07:56:40.80#ibcon#about to read 5, iclass 22, count 0 2006.225.07:56:40.80#ibcon#read 5, iclass 22, count 0 2006.225.07:56:40.80#ibcon#about to read 6, iclass 22, count 0 2006.225.07:56:40.80#ibcon#read 6, iclass 22, count 0 2006.225.07:56:40.80#ibcon#end of sib2, iclass 22, count 0 2006.225.07:56:40.80#ibcon#*mode == 0, iclass 22, count 0 2006.225.07:56:40.80#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.07:56:40.80#ibcon#[27=USB\r\n] 2006.225.07:56:40.80#ibcon#*before write, iclass 22, count 0 2006.225.07:56:40.80#ibcon#enter sib2, iclass 22, count 0 2006.225.07:56:40.80#ibcon#flushed, iclass 22, count 0 2006.225.07:56:40.80#ibcon#about to write, iclass 22, count 0 2006.225.07:56:40.80#ibcon#wrote, iclass 22, count 0 2006.225.07:56:40.80#ibcon#about to read 3, iclass 22, count 0 2006.225.07:56:40.83#ibcon#read 3, iclass 22, count 0 2006.225.07:56:40.83#ibcon#about to read 4, iclass 22, count 0 2006.225.07:56:40.83#ibcon#read 4, iclass 22, count 0 2006.225.07:56:40.83#ibcon#about to read 5, iclass 22, count 0 2006.225.07:56:40.83#ibcon#read 5, iclass 22, count 0 2006.225.07:56:40.83#ibcon#about to read 6, iclass 22, count 0 2006.225.07:56:40.83#ibcon#read 6, iclass 22, count 0 2006.225.07:56:40.83#ibcon#end of sib2, iclass 22, count 0 2006.225.07:56:40.83#ibcon#*after write, iclass 22, count 0 2006.225.07:56:40.83#ibcon#*before return 0, iclass 22, count 0 2006.225.07:56:40.83#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:56:40.83#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.225.07:56:40.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.07:56:40.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.07:56:40.83$vc4f8/vblo=2,640.99 2006.225.07:56:40.83#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.07:56:40.83#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.07:56:40.83#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:40.83#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:56:40.83#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:56:40.83#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:56:40.83#ibcon#enter wrdev, iclass 24, count 0 2006.225.07:56:40.83#ibcon#first serial, iclass 24, count 0 2006.225.07:56:40.83#ibcon#enter sib2, iclass 24, count 0 2006.225.07:56:40.83#ibcon#flushed, iclass 24, count 0 2006.225.07:56:40.83#ibcon#about to write, iclass 24, count 0 2006.225.07:56:40.83#ibcon#wrote, iclass 24, count 0 2006.225.07:56:40.83#ibcon#about to read 3, iclass 24, count 0 2006.225.07:56:40.85#ibcon#read 3, iclass 24, count 0 2006.225.07:56:40.85#ibcon#about to read 4, iclass 24, count 0 2006.225.07:56:40.85#ibcon#read 4, iclass 24, count 0 2006.225.07:56:40.85#ibcon#about to read 5, iclass 24, count 0 2006.225.07:56:40.85#ibcon#read 5, iclass 24, count 0 2006.225.07:56:40.85#ibcon#about to read 6, iclass 24, count 0 2006.225.07:56:40.85#ibcon#read 6, iclass 24, count 0 2006.225.07:56:40.85#ibcon#end of sib2, iclass 24, count 0 2006.225.07:56:40.85#ibcon#*mode == 0, iclass 24, count 0 2006.225.07:56:40.85#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.07:56:40.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.07:56:40.85#ibcon#*before write, iclass 24, count 0 2006.225.07:56:40.85#ibcon#enter sib2, iclass 24, count 0 2006.225.07:56:40.85#ibcon#flushed, iclass 24, count 0 2006.225.07:56:40.85#ibcon#about to write, iclass 24, count 0 2006.225.07:56:40.85#ibcon#wrote, iclass 24, count 0 2006.225.07:56:40.85#ibcon#about to read 3, iclass 24, count 0 2006.225.07:56:40.89#ibcon#read 3, iclass 24, count 0 2006.225.07:56:40.89#ibcon#about to read 4, iclass 24, count 0 2006.225.07:56:40.89#ibcon#read 4, iclass 24, count 0 2006.225.07:56:40.89#ibcon#about to read 5, iclass 24, count 0 2006.225.07:56:40.89#ibcon#read 5, iclass 24, count 0 2006.225.07:56:40.89#ibcon#about to read 6, iclass 24, count 0 2006.225.07:56:40.89#ibcon#read 6, iclass 24, count 0 2006.225.07:56:40.89#ibcon#end of sib2, iclass 24, count 0 2006.225.07:56:40.89#ibcon#*after write, iclass 24, count 0 2006.225.07:56:40.89#ibcon#*before return 0, iclass 24, count 0 2006.225.07:56:40.89#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:56:40.89#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.07:56:40.89#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.07:56:40.89#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.07:56:40.89$vc4f8/vb=2,4 2006.225.07:56:40.89#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.225.07:56:40.89#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.225.07:56:40.89#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:40.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:56:40.95#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:56:40.95#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:56:40.95#ibcon#enter wrdev, iclass 26, count 2 2006.225.07:56:40.95#ibcon#first serial, iclass 26, count 2 2006.225.07:56:40.95#ibcon#enter sib2, iclass 26, count 2 2006.225.07:56:40.95#ibcon#flushed, iclass 26, count 2 2006.225.07:56:40.95#ibcon#about to write, iclass 26, count 2 2006.225.07:56:40.95#ibcon#wrote, iclass 26, count 2 2006.225.07:56:40.95#ibcon#about to read 3, iclass 26, count 2 2006.225.07:56:40.97#ibcon#read 3, iclass 26, count 2 2006.225.07:56:40.97#ibcon#about to read 4, iclass 26, count 2 2006.225.07:56:40.97#ibcon#read 4, iclass 26, count 2 2006.225.07:56:40.97#ibcon#about to read 5, iclass 26, count 2 2006.225.07:56:40.97#ibcon#read 5, iclass 26, count 2 2006.225.07:56:40.97#ibcon#about to read 6, iclass 26, count 2 2006.225.07:56:40.97#ibcon#read 6, iclass 26, count 2 2006.225.07:56:40.97#ibcon#end of sib2, iclass 26, count 2 2006.225.07:56:40.97#ibcon#*mode == 0, iclass 26, count 2 2006.225.07:56:40.97#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.225.07:56:40.97#ibcon#[27=AT02-04\r\n] 2006.225.07:56:40.97#ibcon#*before write, iclass 26, count 2 2006.225.07:56:40.97#ibcon#enter sib2, iclass 26, count 2 2006.225.07:56:40.97#ibcon#flushed, iclass 26, count 2 2006.225.07:56:40.97#ibcon#about to write, iclass 26, count 2 2006.225.07:56:40.97#ibcon#wrote, iclass 26, count 2 2006.225.07:56:40.97#ibcon#about to read 3, iclass 26, count 2 2006.225.07:56:41.00#ibcon#read 3, iclass 26, count 2 2006.225.07:56:41.00#ibcon#about to read 4, iclass 26, count 2 2006.225.07:56:41.00#ibcon#read 4, iclass 26, count 2 2006.225.07:56:41.00#ibcon#about to read 5, iclass 26, count 2 2006.225.07:56:41.00#ibcon#read 5, iclass 26, count 2 2006.225.07:56:41.00#ibcon#about to read 6, iclass 26, count 2 2006.225.07:56:41.00#ibcon#read 6, iclass 26, count 2 2006.225.07:56:41.00#ibcon#end of sib2, iclass 26, count 2 2006.225.07:56:41.00#ibcon#*after write, iclass 26, count 2 2006.225.07:56:41.00#ibcon#*before return 0, iclass 26, count 2 2006.225.07:56:41.00#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:56:41.00#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.225.07:56:41.00#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.225.07:56:41.00#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:41.00#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:56:41.12#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:56:41.12#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:56:41.12#ibcon#enter wrdev, iclass 26, count 0 2006.225.07:56:41.12#ibcon#first serial, iclass 26, count 0 2006.225.07:56:41.12#ibcon#enter sib2, iclass 26, count 0 2006.225.07:56:41.12#ibcon#flushed, iclass 26, count 0 2006.225.07:56:41.12#ibcon#about to write, iclass 26, count 0 2006.225.07:56:41.12#ibcon#wrote, iclass 26, count 0 2006.225.07:56:41.12#ibcon#about to read 3, iclass 26, count 0 2006.225.07:56:41.14#ibcon#read 3, iclass 26, count 0 2006.225.07:56:41.14#ibcon#about to read 4, iclass 26, count 0 2006.225.07:56:41.14#ibcon#read 4, iclass 26, count 0 2006.225.07:56:41.14#ibcon#about to read 5, iclass 26, count 0 2006.225.07:56:41.14#ibcon#read 5, iclass 26, count 0 2006.225.07:56:41.14#ibcon#about to read 6, iclass 26, count 0 2006.225.07:56:41.14#ibcon#read 6, iclass 26, count 0 2006.225.07:56:41.14#ibcon#end of sib2, iclass 26, count 0 2006.225.07:56:41.14#ibcon#*mode == 0, iclass 26, count 0 2006.225.07:56:41.14#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.07:56:41.14#ibcon#[27=USB\r\n] 2006.225.07:56:41.14#ibcon#*before write, iclass 26, count 0 2006.225.07:56:41.14#ibcon#enter sib2, iclass 26, count 0 2006.225.07:56:41.14#ibcon#flushed, iclass 26, count 0 2006.225.07:56:41.14#ibcon#about to write, iclass 26, count 0 2006.225.07:56:41.14#ibcon#wrote, iclass 26, count 0 2006.225.07:56:41.14#ibcon#about to read 3, iclass 26, count 0 2006.225.07:56:41.17#ibcon#read 3, iclass 26, count 0 2006.225.07:56:41.17#ibcon#about to read 4, iclass 26, count 0 2006.225.07:56:41.17#ibcon#read 4, iclass 26, count 0 2006.225.07:56:41.17#ibcon#about to read 5, iclass 26, count 0 2006.225.07:56:41.17#ibcon#read 5, iclass 26, count 0 2006.225.07:56:41.17#ibcon#about to read 6, iclass 26, count 0 2006.225.07:56:41.17#ibcon#read 6, iclass 26, count 0 2006.225.07:56:41.17#ibcon#end of sib2, iclass 26, count 0 2006.225.07:56:41.17#ibcon#*after write, iclass 26, count 0 2006.225.07:56:41.17#ibcon#*before return 0, iclass 26, count 0 2006.225.07:56:41.17#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:56:41.17#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.225.07:56:41.17#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.07:56:41.17#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.07:56:41.17$vc4f8/vblo=3,656.99 2006.225.07:56:41.17#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.07:56:41.17#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.07:56:41.17#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:41.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:56:41.17#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:56:41.17#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:56:41.17#ibcon#enter wrdev, iclass 28, count 0 2006.225.07:56:41.17#ibcon#first serial, iclass 28, count 0 2006.225.07:56:41.17#ibcon#enter sib2, iclass 28, count 0 2006.225.07:56:41.17#ibcon#flushed, iclass 28, count 0 2006.225.07:56:41.17#ibcon#about to write, iclass 28, count 0 2006.225.07:56:41.17#ibcon#wrote, iclass 28, count 0 2006.225.07:56:41.17#ibcon#about to read 3, iclass 28, count 0 2006.225.07:56:41.19#ibcon#read 3, iclass 28, count 0 2006.225.07:56:41.19#ibcon#about to read 4, iclass 28, count 0 2006.225.07:56:41.19#ibcon#read 4, iclass 28, count 0 2006.225.07:56:41.19#ibcon#about to read 5, iclass 28, count 0 2006.225.07:56:41.19#ibcon#read 5, iclass 28, count 0 2006.225.07:56:41.19#ibcon#about to read 6, iclass 28, count 0 2006.225.07:56:41.19#ibcon#read 6, iclass 28, count 0 2006.225.07:56:41.19#ibcon#end of sib2, iclass 28, count 0 2006.225.07:56:41.19#ibcon#*mode == 0, iclass 28, count 0 2006.225.07:56:41.19#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.07:56:41.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.07:56:41.19#ibcon#*before write, iclass 28, count 0 2006.225.07:56:41.19#ibcon#enter sib2, iclass 28, count 0 2006.225.07:56:41.19#ibcon#flushed, iclass 28, count 0 2006.225.07:56:41.19#ibcon#about to write, iclass 28, count 0 2006.225.07:56:41.19#ibcon#wrote, iclass 28, count 0 2006.225.07:56:41.19#ibcon#about to read 3, iclass 28, count 0 2006.225.07:56:41.24#ibcon#read 3, iclass 28, count 0 2006.225.07:56:41.24#ibcon#about to read 4, iclass 28, count 0 2006.225.07:56:41.24#ibcon#read 4, iclass 28, count 0 2006.225.07:56:41.24#ibcon#about to read 5, iclass 28, count 0 2006.225.07:56:41.24#ibcon#read 5, iclass 28, count 0 2006.225.07:56:41.24#ibcon#about to read 6, iclass 28, count 0 2006.225.07:56:41.24#ibcon#read 6, iclass 28, count 0 2006.225.07:56:41.24#ibcon#end of sib2, iclass 28, count 0 2006.225.07:56:41.24#ibcon#*after write, iclass 28, count 0 2006.225.07:56:41.24#ibcon#*before return 0, iclass 28, count 0 2006.225.07:56:41.24#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:56:41.24#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.07:56:41.24#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.07:56:41.24#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.07:56:41.24$vc4f8/vb=3,4 2006.225.07:56:41.24#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.07:56:41.24#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.07:56:41.24#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:41.24#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:56:41.29#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:56:41.29#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:56:41.29#ibcon#enter wrdev, iclass 30, count 2 2006.225.07:56:41.29#ibcon#first serial, iclass 30, count 2 2006.225.07:56:41.29#ibcon#enter sib2, iclass 30, count 2 2006.225.07:56:41.29#ibcon#flushed, iclass 30, count 2 2006.225.07:56:41.29#ibcon#about to write, iclass 30, count 2 2006.225.07:56:41.29#ibcon#wrote, iclass 30, count 2 2006.225.07:56:41.29#ibcon#about to read 3, iclass 30, count 2 2006.225.07:56:41.31#ibcon#read 3, iclass 30, count 2 2006.225.07:56:41.31#ibcon#about to read 4, iclass 30, count 2 2006.225.07:56:41.31#ibcon#read 4, iclass 30, count 2 2006.225.07:56:41.31#ibcon#about to read 5, iclass 30, count 2 2006.225.07:56:41.31#ibcon#read 5, iclass 30, count 2 2006.225.07:56:41.31#ibcon#about to read 6, iclass 30, count 2 2006.225.07:56:41.31#ibcon#read 6, iclass 30, count 2 2006.225.07:56:41.31#ibcon#end of sib2, iclass 30, count 2 2006.225.07:56:41.31#ibcon#*mode == 0, iclass 30, count 2 2006.225.07:56:41.31#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.07:56:41.31#ibcon#[27=AT03-04\r\n] 2006.225.07:56:41.31#ibcon#*before write, iclass 30, count 2 2006.225.07:56:41.31#ibcon#enter sib2, iclass 30, count 2 2006.225.07:56:41.31#ibcon#flushed, iclass 30, count 2 2006.225.07:56:41.31#ibcon#about to write, iclass 30, count 2 2006.225.07:56:41.31#ibcon#wrote, iclass 30, count 2 2006.225.07:56:41.31#ibcon#about to read 3, iclass 30, count 2 2006.225.07:56:41.34#ibcon#read 3, iclass 30, count 2 2006.225.07:56:41.34#ibcon#about to read 4, iclass 30, count 2 2006.225.07:56:41.34#ibcon#read 4, iclass 30, count 2 2006.225.07:56:41.34#ibcon#about to read 5, iclass 30, count 2 2006.225.07:56:41.34#ibcon#read 5, iclass 30, count 2 2006.225.07:56:41.34#ibcon#about to read 6, iclass 30, count 2 2006.225.07:56:41.34#ibcon#read 6, iclass 30, count 2 2006.225.07:56:41.34#ibcon#end of sib2, iclass 30, count 2 2006.225.07:56:41.34#ibcon#*after write, iclass 30, count 2 2006.225.07:56:41.34#ibcon#*before return 0, iclass 30, count 2 2006.225.07:56:41.34#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:56:41.34#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.07:56:41.34#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.07:56:41.34#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:41.34#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:56:41.46#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:56:41.46#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:56:41.46#ibcon#enter wrdev, iclass 30, count 0 2006.225.07:56:41.46#ibcon#first serial, iclass 30, count 0 2006.225.07:56:41.46#ibcon#enter sib2, iclass 30, count 0 2006.225.07:56:41.46#ibcon#flushed, iclass 30, count 0 2006.225.07:56:41.46#ibcon#about to write, iclass 30, count 0 2006.225.07:56:41.46#ibcon#wrote, iclass 30, count 0 2006.225.07:56:41.46#ibcon#about to read 3, iclass 30, count 0 2006.225.07:56:41.48#ibcon#read 3, iclass 30, count 0 2006.225.07:56:41.48#ibcon#about to read 4, iclass 30, count 0 2006.225.07:56:41.48#ibcon#read 4, iclass 30, count 0 2006.225.07:56:41.48#ibcon#about to read 5, iclass 30, count 0 2006.225.07:56:41.48#ibcon#read 5, iclass 30, count 0 2006.225.07:56:41.48#ibcon#about to read 6, iclass 30, count 0 2006.225.07:56:41.48#ibcon#read 6, iclass 30, count 0 2006.225.07:56:41.48#ibcon#end of sib2, iclass 30, count 0 2006.225.07:56:41.48#ibcon#*mode == 0, iclass 30, count 0 2006.225.07:56:41.48#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.07:56:41.48#ibcon#[27=USB\r\n] 2006.225.07:56:41.48#ibcon#*before write, iclass 30, count 0 2006.225.07:56:41.48#ibcon#enter sib2, iclass 30, count 0 2006.225.07:56:41.48#ibcon#flushed, iclass 30, count 0 2006.225.07:56:41.48#ibcon#about to write, iclass 30, count 0 2006.225.07:56:41.48#ibcon#wrote, iclass 30, count 0 2006.225.07:56:41.48#ibcon#about to read 3, iclass 30, count 0 2006.225.07:56:41.51#ibcon#read 3, iclass 30, count 0 2006.225.07:56:41.51#ibcon#about to read 4, iclass 30, count 0 2006.225.07:56:41.51#ibcon#read 4, iclass 30, count 0 2006.225.07:56:41.51#ibcon#about to read 5, iclass 30, count 0 2006.225.07:56:41.51#ibcon#read 5, iclass 30, count 0 2006.225.07:56:41.51#ibcon#about to read 6, iclass 30, count 0 2006.225.07:56:41.51#ibcon#read 6, iclass 30, count 0 2006.225.07:56:41.51#ibcon#end of sib2, iclass 30, count 0 2006.225.07:56:41.51#ibcon#*after write, iclass 30, count 0 2006.225.07:56:41.51#ibcon#*before return 0, iclass 30, count 0 2006.225.07:56:41.51#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:56:41.51#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.07:56:41.51#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.07:56:41.51#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.07:56:41.51$vc4f8/vblo=4,712.99 2006.225.07:56:41.51#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.07:56:41.51#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.07:56:41.51#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:41.51#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:56:41.51#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:56:41.51#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:56:41.51#ibcon#enter wrdev, iclass 32, count 0 2006.225.07:56:41.51#ibcon#first serial, iclass 32, count 0 2006.225.07:56:41.51#ibcon#enter sib2, iclass 32, count 0 2006.225.07:56:41.51#ibcon#flushed, iclass 32, count 0 2006.225.07:56:41.51#ibcon#about to write, iclass 32, count 0 2006.225.07:56:41.51#ibcon#wrote, iclass 32, count 0 2006.225.07:56:41.51#ibcon#about to read 3, iclass 32, count 0 2006.225.07:56:41.53#ibcon#read 3, iclass 32, count 0 2006.225.07:56:41.53#ibcon#about to read 4, iclass 32, count 0 2006.225.07:56:41.53#ibcon#read 4, iclass 32, count 0 2006.225.07:56:41.53#ibcon#about to read 5, iclass 32, count 0 2006.225.07:56:41.53#ibcon#read 5, iclass 32, count 0 2006.225.07:56:41.53#ibcon#about to read 6, iclass 32, count 0 2006.225.07:56:41.53#ibcon#read 6, iclass 32, count 0 2006.225.07:56:41.53#ibcon#end of sib2, iclass 32, count 0 2006.225.07:56:41.53#ibcon#*mode == 0, iclass 32, count 0 2006.225.07:56:41.53#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.07:56:41.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.07:56:41.53#ibcon#*before write, iclass 32, count 0 2006.225.07:56:41.53#ibcon#enter sib2, iclass 32, count 0 2006.225.07:56:41.53#ibcon#flushed, iclass 32, count 0 2006.225.07:56:41.53#ibcon#about to write, iclass 32, count 0 2006.225.07:56:41.53#ibcon#wrote, iclass 32, count 0 2006.225.07:56:41.53#ibcon#about to read 3, iclass 32, count 0 2006.225.07:56:41.57#ibcon#read 3, iclass 32, count 0 2006.225.07:56:41.57#ibcon#about to read 4, iclass 32, count 0 2006.225.07:56:41.57#ibcon#read 4, iclass 32, count 0 2006.225.07:56:41.57#ibcon#about to read 5, iclass 32, count 0 2006.225.07:56:41.57#ibcon#read 5, iclass 32, count 0 2006.225.07:56:41.57#ibcon#about to read 6, iclass 32, count 0 2006.225.07:56:41.57#ibcon#read 6, iclass 32, count 0 2006.225.07:56:41.57#ibcon#end of sib2, iclass 32, count 0 2006.225.07:56:41.57#ibcon#*after write, iclass 32, count 0 2006.225.07:56:41.57#ibcon#*before return 0, iclass 32, count 0 2006.225.07:56:41.57#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:56:41.57#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.07:56:41.57#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.07:56:41.57#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.07:56:41.57$vc4f8/vb=4,4 2006.225.07:56:41.57#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.07:56:41.57#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.07:56:41.57#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:41.57#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:56:41.63#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:56:41.63#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:56:41.63#ibcon#enter wrdev, iclass 34, count 2 2006.225.07:56:41.63#ibcon#first serial, iclass 34, count 2 2006.225.07:56:41.63#ibcon#enter sib2, iclass 34, count 2 2006.225.07:56:41.63#ibcon#flushed, iclass 34, count 2 2006.225.07:56:41.63#ibcon#about to write, iclass 34, count 2 2006.225.07:56:41.63#ibcon#wrote, iclass 34, count 2 2006.225.07:56:41.63#ibcon#about to read 3, iclass 34, count 2 2006.225.07:56:41.65#ibcon#read 3, iclass 34, count 2 2006.225.07:56:41.65#ibcon#about to read 4, iclass 34, count 2 2006.225.07:56:41.65#ibcon#read 4, iclass 34, count 2 2006.225.07:56:41.65#ibcon#about to read 5, iclass 34, count 2 2006.225.07:56:41.65#ibcon#read 5, iclass 34, count 2 2006.225.07:56:41.65#ibcon#about to read 6, iclass 34, count 2 2006.225.07:56:41.65#ibcon#read 6, iclass 34, count 2 2006.225.07:56:41.65#ibcon#end of sib2, iclass 34, count 2 2006.225.07:56:41.65#ibcon#*mode == 0, iclass 34, count 2 2006.225.07:56:41.65#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.07:56:41.65#ibcon#[27=AT04-04\r\n] 2006.225.07:56:41.65#ibcon#*before write, iclass 34, count 2 2006.225.07:56:41.65#ibcon#enter sib2, iclass 34, count 2 2006.225.07:56:41.65#ibcon#flushed, iclass 34, count 2 2006.225.07:56:41.65#ibcon#about to write, iclass 34, count 2 2006.225.07:56:41.65#ibcon#wrote, iclass 34, count 2 2006.225.07:56:41.65#ibcon#about to read 3, iclass 34, count 2 2006.225.07:56:41.68#ibcon#read 3, iclass 34, count 2 2006.225.07:56:41.68#ibcon#about to read 4, iclass 34, count 2 2006.225.07:56:41.68#ibcon#read 4, iclass 34, count 2 2006.225.07:56:41.68#ibcon#about to read 5, iclass 34, count 2 2006.225.07:56:41.68#ibcon#read 5, iclass 34, count 2 2006.225.07:56:41.68#ibcon#about to read 6, iclass 34, count 2 2006.225.07:56:41.68#ibcon#read 6, iclass 34, count 2 2006.225.07:56:41.68#ibcon#end of sib2, iclass 34, count 2 2006.225.07:56:41.68#ibcon#*after write, iclass 34, count 2 2006.225.07:56:41.68#ibcon#*before return 0, iclass 34, count 2 2006.225.07:56:41.68#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:56:41.68#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.07:56:41.68#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.07:56:41.68#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:41.68#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:56:41.80#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:56:41.80#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:56:41.80#ibcon#enter wrdev, iclass 34, count 0 2006.225.07:56:41.80#ibcon#first serial, iclass 34, count 0 2006.225.07:56:41.80#ibcon#enter sib2, iclass 34, count 0 2006.225.07:56:41.80#ibcon#flushed, iclass 34, count 0 2006.225.07:56:41.80#ibcon#about to write, iclass 34, count 0 2006.225.07:56:41.80#ibcon#wrote, iclass 34, count 0 2006.225.07:56:41.80#ibcon#about to read 3, iclass 34, count 0 2006.225.07:56:41.82#ibcon#read 3, iclass 34, count 0 2006.225.07:56:41.82#ibcon#about to read 4, iclass 34, count 0 2006.225.07:56:41.82#ibcon#read 4, iclass 34, count 0 2006.225.07:56:41.82#ibcon#about to read 5, iclass 34, count 0 2006.225.07:56:41.82#ibcon#read 5, iclass 34, count 0 2006.225.07:56:41.82#ibcon#about to read 6, iclass 34, count 0 2006.225.07:56:41.82#ibcon#read 6, iclass 34, count 0 2006.225.07:56:41.82#ibcon#end of sib2, iclass 34, count 0 2006.225.07:56:41.82#ibcon#*mode == 0, iclass 34, count 0 2006.225.07:56:41.82#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.07:56:41.82#ibcon#[27=USB\r\n] 2006.225.07:56:41.82#ibcon#*before write, iclass 34, count 0 2006.225.07:56:41.82#ibcon#enter sib2, iclass 34, count 0 2006.225.07:56:41.82#ibcon#flushed, iclass 34, count 0 2006.225.07:56:41.82#ibcon#about to write, iclass 34, count 0 2006.225.07:56:41.82#ibcon#wrote, iclass 34, count 0 2006.225.07:56:41.82#ibcon#about to read 3, iclass 34, count 0 2006.225.07:56:41.85#ibcon#read 3, iclass 34, count 0 2006.225.07:56:41.85#ibcon#about to read 4, iclass 34, count 0 2006.225.07:56:41.85#ibcon#read 4, iclass 34, count 0 2006.225.07:56:41.85#ibcon#about to read 5, iclass 34, count 0 2006.225.07:56:41.85#ibcon#read 5, iclass 34, count 0 2006.225.07:56:41.85#ibcon#about to read 6, iclass 34, count 0 2006.225.07:56:41.85#ibcon#read 6, iclass 34, count 0 2006.225.07:56:41.85#ibcon#end of sib2, iclass 34, count 0 2006.225.07:56:41.85#ibcon#*after write, iclass 34, count 0 2006.225.07:56:41.85#ibcon#*before return 0, iclass 34, count 0 2006.225.07:56:41.85#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:56:41.85#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.07:56:41.85#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.07:56:41.85#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.07:56:41.85$vc4f8/vblo=5,744.99 2006.225.07:56:41.85#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.07:56:41.85#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.07:56:41.85#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:41.85#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:56:41.85#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:56:41.85#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:56:41.85#ibcon#enter wrdev, iclass 36, count 0 2006.225.07:56:41.85#ibcon#first serial, iclass 36, count 0 2006.225.07:56:41.85#ibcon#enter sib2, iclass 36, count 0 2006.225.07:56:41.85#ibcon#flushed, iclass 36, count 0 2006.225.07:56:41.85#ibcon#about to write, iclass 36, count 0 2006.225.07:56:41.85#ibcon#wrote, iclass 36, count 0 2006.225.07:56:41.85#ibcon#about to read 3, iclass 36, count 0 2006.225.07:56:41.87#ibcon#read 3, iclass 36, count 0 2006.225.07:56:41.87#ibcon#about to read 4, iclass 36, count 0 2006.225.07:56:41.87#ibcon#read 4, iclass 36, count 0 2006.225.07:56:41.87#ibcon#about to read 5, iclass 36, count 0 2006.225.07:56:41.87#ibcon#read 5, iclass 36, count 0 2006.225.07:56:41.87#ibcon#about to read 6, iclass 36, count 0 2006.225.07:56:41.87#ibcon#read 6, iclass 36, count 0 2006.225.07:56:41.87#ibcon#end of sib2, iclass 36, count 0 2006.225.07:56:41.87#ibcon#*mode == 0, iclass 36, count 0 2006.225.07:56:41.87#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.07:56:41.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.07:56:41.87#ibcon#*before write, iclass 36, count 0 2006.225.07:56:41.87#ibcon#enter sib2, iclass 36, count 0 2006.225.07:56:41.87#ibcon#flushed, iclass 36, count 0 2006.225.07:56:41.87#ibcon#about to write, iclass 36, count 0 2006.225.07:56:41.87#ibcon#wrote, iclass 36, count 0 2006.225.07:56:41.87#ibcon#about to read 3, iclass 36, count 0 2006.225.07:56:41.91#ibcon#read 3, iclass 36, count 0 2006.225.07:56:41.91#ibcon#about to read 4, iclass 36, count 0 2006.225.07:56:41.91#ibcon#read 4, iclass 36, count 0 2006.225.07:56:41.91#ibcon#about to read 5, iclass 36, count 0 2006.225.07:56:41.91#ibcon#read 5, iclass 36, count 0 2006.225.07:56:41.91#ibcon#about to read 6, iclass 36, count 0 2006.225.07:56:41.91#ibcon#read 6, iclass 36, count 0 2006.225.07:56:41.91#ibcon#end of sib2, iclass 36, count 0 2006.225.07:56:41.91#ibcon#*after write, iclass 36, count 0 2006.225.07:56:41.91#ibcon#*before return 0, iclass 36, count 0 2006.225.07:56:41.91#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:56:41.91#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.07:56:41.91#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.07:56:41.91#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.07:56:41.91$vc4f8/vb=5,4 2006.225.07:56:41.91#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.07:56:41.91#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.07:56:41.91#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:41.91#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:56:41.97#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:56:41.97#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:56:41.97#ibcon#enter wrdev, iclass 38, count 2 2006.225.07:56:41.97#ibcon#first serial, iclass 38, count 2 2006.225.07:56:41.97#ibcon#enter sib2, iclass 38, count 2 2006.225.07:56:41.97#ibcon#flushed, iclass 38, count 2 2006.225.07:56:41.97#ibcon#about to write, iclass 38, count 2 2006.225.07:56:41.97#ibcon#wrote, iclass 38, count 2 2006.225.07:56:41.97#ibcon#about to read 3, iclass 38, count 2 2006.225.07:56:41.99#ibcon#read 3, iclass 38, count 2 2006.225.07:56:41.99#ibcon#about to read 4, iclass 38, count 2 2006.225.07:56:41.99#ibcon#read 4, iclass 38, count 2 2006.225.07:56:41.99#ibcon#about to read 5, iclass 38, count 2 2006.225.07:56:41.99#ibcon#read 5, iclass 38, count 2 2006.225.07:56:41.99#ibcon#about to read 6, iclass 38, count 2 2006.225.07:56:41.99#ibcon#read 6, iclass 38, count 2 2006.225.07:56:41.99#ibcon#end of sib2, iclass 38, count 2 2006.225.07:56:41.99#ibcon#*mode == 0, iclass 38, count 2 2006.225.07:56:41.99#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.07:56:41.99#ibcon#[27=AT05-04\r\n] 2006.225.07:56:41.99#ibcon#*before write, iclass 38, count 2 2006.225.07:56:41.99#ibcon#enter sib2, iclass 38, count 2 2006.225.07:56:41.99#ibcon#flushed, iclass 38, count 2 2006.225.07:56:41.99#ibcon#about to write, iclass 38, count 2 2006.225.07:56:41.99#ibcon#wrote, iclass 38, count 2 2006.225.07:56:41.99#ibcon#about to read 3, iclass 38, count 2 2006.225.07:56:42.02#ibcon#read 3, iclass 38, count 2 2006.225.07:56:42.02#ibcon#about to read 4, iclass 38, count 2 2006.225.07:56:42.02#ibcon#read 4, iclass 38, count 2 2006.225.07:56:42.02#ibcon#about to read 5, iclass 38, count 2 2006.225.07:56:42.02#ibcon#read 5, iclass 38, count 2 2006.225.07:56:42.02#ibcon#about to read 6, iclass 38, count 2 2006.225.07:56:42.02#ibcon#read 6, iclass 38, count 2 2006.225.07:56:42.02#ibcon#end of sib2, iclass 38, count 2 2006.225.07:56:42.02#ibcon#*after write, iclass 38, count 2 2006.225.07:56:42.02#ibcon#*before return 0, iclass 38, count 2 2006.225.07:56:42.02#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:56:42.02#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.07:56:42.02#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.07:56:42.02#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:42.02#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:56:42.14#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:56:42.14#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:56:42.14#ibcon#enter wrdev, iclass 38, count 0 2006.225.07:56:42.14#ibcon#first serial, iclass 38, count 0 2006.225.07:56:42.14#ibcon#enter sib2, iclass 38, count 0 2006.225.07:56:42.14#ibcon#flushed, iclass 38, count 0 2006.225.07:56:42.14#ibcon#about to write, iclass 38, count 0 2006.225.07:56:42.14#ibcon#wrote, iclass 38, count 0 2006.225.07:56:42.14#ibcon#about to read 3, iclass 38, count 0 2006.225.07:56:42.16#ibcon#read 3, iclass 38, count 0 2006.225.07:56:42.16#ibcon#about to read 4, iclass 38, count 0 2006.225.07:56:42.16#ibcon#read 4, iclass 38, count 0 2006.225.07:56:42.16#ibcon#about to read 5, iclass 38, count 0 2006.225.07:56:42.16#ibcon#read 5, iclass 38, count 0 2006.225.07:56:42.16#ibcon#about to read 6, iclass 38, count 0 2006.225.07:56:42.16#ibcon#read 6, iclass 38, count 0 2006.225.07:56:42.16#ibcon#end of sib2, iclass 38, count 0 2006.225.07:56:42.16#ibcon#*mode == 0, iclass 38, count 0 2006.225.07:56:42.16#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.07:56:42.16#ibcon#[27=USB\r\n] 2006.225.07:56:42.16#ibcon#*before write, iclass 38, count 0 2006.225.07:56:42.16#ibcon#enter sib2, iclass 38, count 0 2006.225.07:56:42.16#ibcon#flushed, iclass 38, count 0 2006.225.07:56:42.16#ibcon#about to write, iclass 38, count 0 2006.225.07:56:42.16#ibcon#wrote, iclass 38, count 0 2006.225.07:56:42.16#ibcon#about to read 3, iclass 38, count 0 2006.225.07:56:42.19#ibcon#read 3, iclass 38, count 0 2006.225.07:56:42.19#ibcon#about to read 4, iclass 38, count 0 2006.225.07:56:42.19#ibcon#read 4, iclass 38, count 0 2006.225.07:56:42.19#ibcon#about to read 5, iclass 38, count 0 2006.225.07:56:42.19#ibcon#read 5, iclass 38, count 0 2006.225.07:56:42.19#ibcon#about to read 6, iclass 38, count 0 2006.225.07:56:42.19#ibcon#read 6, iclass 38, count 0 2006.225.07:56:42.19#ibcon#end of sib2, iclass 38, count 0 2006.225.07:56:42.19#ibcon#*after write, iclass 38, count 0 2006.225.07:56:42.19#ibcon#*before return 0, iclass 38, count 0 2006.225.07:56:42.19#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:56:42.19#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.07:56:42.19#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.07:56:42.19#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.07:56:42.19$vc4f8/vblo=6,752.99 2006.225.07:56:42.19#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.07:56:42.19#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.07:56:42.19#ibcon#ireg 17 cls_cnt 0 2006.225.07:56:42.19#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:56:42.19#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:56:42.19#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:56:42.19#ibcon#enter wrdev, iclass 40, count 0 2006.225.07:56:42.19#ibcon#first serial, iclass 40, count 0 2006.225.07:56:42.19#ibcon#enter sib2, iclass 40, count 0 2006.225.07:56:42.19#ibcon#flushed, iclass 40, count 0 2006.225.07:56:42.19#ibcon#about to write, iclass 40, count 0 2006.225.07:56:42.19#ibcon#wrote, iclass 40, count 0 2006.225.07:56:42.19#ibcon#about to read 3, iclass 40, count 0 2006.225.07:56:42.21#ibcon#read 3, iclass 40, count 0 2006.225.07:56:42.21#ibcon#about to read 4, iclass 40, count 0 2006.225.07:56:42.21#ibcon#read 4, iclass 40, count 0 2006.225.07:56:42.21#ibcon#about to read 5, iclass 40, count 0 2006.225.07:56:42.21#ibcon#read 5, iclass 40, count 0 2006.225.07:56:42.21#ibcon#about to read 6, iclass 40, count 0 2006.225.07:56:42.21#ibcon#read 6, iclass 40, count 0 2006.225.07:56:42.21#ibcon#end of sib2, iclass 40, count 0 2006.225.07:56:42.21#ibcon#*mode == 0, iclass 40, count 0 2006.225.07:56:42.21#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.07:56:42.21#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.07:56:42.21#ibcon#*before write, iclass 40, count 0 2006.225.07:56:42.21#ibcon#enter sib2, iclass 40, count 0 2006.225.07:56:42.21#ibcon#flushed, iclass 40, count 0 2006.225.07:56:42.21#ibcon#about to write, iclass 40, count 0 2006.225.07:56:42.21#ibcon#wrote, iclass 40, count 0 2006.225.07:56:42.21#ibcon#about to read 3, iclass 40, count 0 2006.225.07:56:42.26#ibcon#read 3, iclass 40, count 0 2006.225.07:56:42.26#ibcon#about to read 4, iclass 40, count 0 2006.225.07:56:42.26#ibcon#read 4, iclass 40, count 0 2006.225.07:56:42.26#ibcon#about to read 5, iclass 40, count 0 2006.225.07:56:42.26#ibcon#read 5, iclass 40, count 0 2006.225.07:56:42.26#ibcon#about to read 6, iclass 40, count 0 2006.225.07:56:42.26#ibcon#read 6, iclass 40, count 0 2006.225.07:56:42.26#ibcon#end of sib2, iclass 40, count 0 2006.225.07:56:42.26#ibcon#*after write, iclass 40, count 0 2006.225.07:56:42.26#ibcon#*before return 0, iclass 40, count 0 2006.225.07:56:42.26#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:56:42.26#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.07:56:42.26#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.07:56:42.26#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.07:56:42.26$vc4f8/vb=6,4 2006.225.07:56:42.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.07:56:42.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.07:56:42.26#ibcon#ireg 11 cls_cnt 2 2006.225.07:56:42.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:56:42.29#abcon#<5=/05 2.7 5.1 28.38 721003.3\r\n> 2006.225.07:56:42.31#abcon#{5=INTERFACE CLEAR} 2006.225.07:56:42.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:56:42.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:56:42.31#ibcon#enter wrdev, iclass 5, count 2 2006.225.07:56:42.31#ibcon#first serial, iclass 5, count 2 2006.225.07:56:42.31#ibcon#enter sib2, iclass 5, count 2 2006.225.07:56:42.31#ibcon#flushed, iclass 5, count 2 2006.225.07:56:42.31#ibcon#about to write, iclass 5, count 2 2006.225.07:56:42.31#ibcon#wrote, iclass 5, count 2 2006.225.07:56:42.31#ibcon#about to read 3, iclass 5, count 2 2006.225.07:56:42.33#ibcon#read 3, iclass 5, count 2 2006.225.07:56:42.33#ibcon#about to read 4, iclass 5, count 2 2006.225.07:56:42.33#ibcon#read 4, iclass 5, count 2 2006.225.07:56:42.33#ibcon#about to read 5, iclass 5, count 2 2006.225.07:56:42.33#ibcon#read 5, iclass 5, count 2 2006.225.07:56:42.33#ibcon#about to read 6, iclass 5, count 2 2006.225.07:56:42.33#ibcon#read 6, iclass 5, count 2 2006.225.07:56:42.33#ibcon#end of sib2, iclass 5, count 2 2006.225.07:56:42.33#ibcon#*mode == 0, iclass 5, count 2 2006.225.07:56:42.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.07:56:42.33#ibcon#[27=AT06-04\r\n] 2006.225.07:56:42.33#ibcon#*before write, iclass 5, count 2 2006.225.07:56:42.33#ibcon#enter sib2, iclass 5, count 2 2006.225.07:56:42.33#ibcon#flushed, iclass 5, count 2 2006.225.07:56:42.33#ibcon#about to write, iclass 5, count 2 2006.225.07:56:42.33#ibcon#wrote, iclass 5, count 2 2006.225.07:56:42.33#ibcon#about to read 3, iclass 5, count 2 2006.225.07:56:42.36#ibcon#read 3, iclass 5, count 2 2006.225.07:56:42.36#ibcon#about to read 4, iclass 5, count 2 2006.225.07:56:42.36#ibcon#read 4, iclass 5, count 2 2006.225.07:56:42.36#ibcon#about to read 5, iclass 5, count 2 2006.225.07:56:42.36#ibcon#read 5, iclass 5, count 2 2006.225.07:56:42.36#ibcon#about to read 6, iclass 5, count 2 2006.225.07:56:42.36#ibcon#read 6, iclass 5, count 2 2006.225.07:56:42.36#ibcon#end of sib2, iclass 5, count 2 2006.225.07:56:42.36#ibcon#*after write, iclass 5, count 2 2006.225.07:56:42.36#ibcon#*before return 0, iclass 5, count 2 2006.225.07:56:42.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:56:42.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.07:56:42.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.07:56:42.36#ibcon#ireg 7 cls_cnt 0 2006.225.07:56:42.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:56:42.37#abcon#[5=S1D000X0/0*\r\n] 2006.225.07:56:42.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:56:42.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:56:42.48#ibcon#enter wrdev, iclass 5, count 0 2006.225.07:56:42.48#ibcon#first serial, iclass 5, count 0 2006.225.07:56:42.48#ibcon#enter sib2, iclass 5, count 0 2006.225.07:56:42.48#ibcon#flushed, iclass 5, count 0 2006.225.07:56:42.48#ibcon#about to write, iclass 5, count 0 2006.225.07:56:42.48#ibcon#wrote, iclass 5, count 0 2006.225.07:56:42.48#ibcon#about to read 3, iclass 5, count 0 2006.225.07:56:42.50#ibcon#read 3, iclass 5, count 0 2006.225.07:56:42.50#ibcon#about to read 4, iclass 5, count 0 2006.225.07:56:42.50#ibcon#read 4, iclass 5, count 0 2006.225.07:56:42.50#ibcon#about to read 5, iclass 5, count 0 2006.225.07:56:42.50#ibcon#read 5, iclass 5, count 0 2006.225.07:56:42.50#ibcon#about to read 6, iclass 5, count 0 2006.225.07:56:42.50#ibcon#read 6, iclass 5, count 0 2006.225.07:56:42.50#ibcon#end of sib2, iclass 5, count 0 2006.225.07:56:42.50#ibcon#*mode == 0, iclass 5, count 0 2006.225.07:56:42.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.07:56:42.50#ibcon#[27=USB\r\n] 2006.225.07:56:42.50#ibcon#*before write, iclass 5, count 0 2006.225.07:56:42.50#ibcon#enter sib2, iclass 5, count 0 2006.225.07:56:42.50#ibcon#flushed, iclass 5, count 0 2006.225.07:56:42.50#ibcon#about to write, iclass 5, count 0 2006.225.07:56:42.50#ibcon#wrote, iclass 5, count 0 2006.225.07:56:42.50#ibcon#about to read 3, iclass 5, count 0 2006.225.07:56:42.53#ibcon#read 3, iclass 5, count 0 2006.225.07:56:42.53#ibcon#about to read 4, iclass 5, count 0 2006.225.07:56:42.53#ibcon#read 4, iclass 5, count 0 2006.225.07:56:42.53#ibcon#about to read 5, iclass 5, count 0 2006.225.07:56:42.53#ibcon#read 5, iclass 5, count 0 2006.225.07:56:42.53#ibcon#about to read 6, iclass 5, count 0 2006.225.07:56:42.53#ibcon#read 6, iclass 5, count 0 2006.225.07:56:42.53#ibcon#end of sib2, iclass 5, count 0 2006.225.07:56:42.53#ibcon#*after write, iclass 5, count 0 2006.225.07:56:42.53#ibcon#*before return 0, iclass 5, count 0 2006.225.07:56:42.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:56:42.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.07:56:42.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.07:56:42.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.07:56:42.53$vc4f8/vabw=wide 2006.225.07:56:42.53#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.07:56:42.53#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.07:56:42.53#ibcon#ireg 8 cls_cnt 0 2006.225.07:56:42.53#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:56:42.53#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:56:42.53#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:56:42.53#ibcon#enter wrdev, iclass 12, count 0 2006.225.07:56:42.53#ibcon#first serial, iclass 12, count 0 2006.225.07:56:42.53#ibcon#enter sib2, iclass 12, count 0 2006.225.07:56:42.53#ibcon#flushed, iclass 12, count 0 2006.225.07:56:42.53#ibcon#about to write, iclass 12, count 0 2006.225.07:56:42.53#ibcon#wrote, iclass 12, count 0 2006.225.07:56:42.53#ibcon#about to read 3, iclass 12, count 0 2006.225.07:56:42.55#ibcon#read 3, iclass 12, count 0 2006.225.07:56:42.55#ibcon#about to read 4, iclass 12, count 0 2006.225.07:56:42.55#ibcon#read 4, iclass 12, count 0 2006.225.07:56:42.55#ibcon#about to read 5, iclass 12, count 0 2006.225.07:56:42.55#ibcon#read 5, iclass 12, count 0 2006.225.07:56:42.55#ibcon#about to read 6, iclass 12, count 0 2006.225.07:56:42.55#ibcon#read 6, iclass 12, count 0 2006.225.07:56:42.55#ibcon#end of sib2, iclass 12, count 0 2006.225.07:56:42.55#ibcon#*mode == 0, iclass 12, count 0 2006.225.07:56:42.55#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.07:56:42.55#ibcon#[25=BW32\r\n] 2006.225.07:56:42.55#ibcon#*before write, iclass 12, count 0 2006.225.07:56:42.55#ibcon#enter sib2, iclass 12, count 0 2006.225.07:56:42.55#ibcon#flushed, iclass 12, count 0 2006.225.07:56:42.55#ibcon#about to write, iclass 12, count 0 2006.225.07:56:42.55#ibcon#wrote, iclass 12, count 0 2006.225.07:56:42.55#ibcon#about to read 3, iclass 12, count 0 2006.225.07:56:42.58#ibcon#read 3, iclass 12, count 0 2006.225.07:56:42.58#ibcon#about to read 4, iclass 12, count 0 2006.225.07:56:42.58#ibcon#read 4, iclass 12, count 0 2006.225.07:56:42.58#ibcon#about to read 5, iclass 12, count 0 2006.225.07:56:42.58#ibcon#read 5, iclass 12, count 0 2006.225.07:56:42.58#ibcon#about to read 6, iclass 12, count 0 2006.225.07:56:42.58#ibcon#read 6, iclass 12, count 0 2006.225.07:56:42.58#ibcon#end of sib2, iclass 12, count 0 2006.225.07:56:42.58#ibcon#*after write, iclass 12, count 0 2006.225.07:56:42.58#ibcon#*before return 0, iclass 12, count 0 2006.225.07:56:42.58#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:56:42.58#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.07:56:42.58#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.07:56:42.58#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.07:56:42.58$vc4f8/vbbw=wide 2006.225.07:56:42.58#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.07:56:42.58#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.07:56:42.58#ibcon#ireg 8 cls_cnt 0 2006.225.07:56:42.58#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:56:42.65#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:56:42.65#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:56:42.65#ibcon#enter wrdev, iclass 14, count 0 2006.225.07:56:42.65#ibcon#first serial, iclass 14, count 0 2006.225.07:56:42.65#ibcon#enter sib2, iclass 14, count 0 2006.225.07:56:42.65#ibcon#flushed, iclass 14, count 0 2006.225.07:56:42.65#ibcon#about to write, iclass 14, count 0 2006.225.07:56:42.65#ibcon#wrote, iclass 14, count 0 2006.225.07:56:42.65#ibcon#about to read 3, iclass 14, count 0 2006.225.07:56:42.67#ibcon#read 3, iclass 14, count 0 2006.225.07:56:42.67#ibcon#about to read 4, iclass 14, count 0 2006.225.07:56:42.67#ibcon#read 4, iclass 14, count 0 2006.225.07:56:42.67#ibcon#about to read 5, iclass 14, count 0 2006.225.07:56:42.67#ibcon#read 5, iclass 14, count 0 2006.225.07:56:42.67#ibcon#about to read 6, iclass 14, count 0 2006.225.07:56:42.67#ibcon#read 6, iclass 14, count 0 2006.225.07:56:42.67#ibcon#end of sib2, iclass 14, count 0 2006.225.07:56:42.67#ibcon#*mode == 0, iclass 14, count 0 2006.225.07:56:42.67#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.07:56:42.67#ibcon#[27=BW32\r\n] 2006.225.07:56:42.67#ibcon#*before write, iclass 14, count 0 2006.225.07:56:42.67#ibcon#enter sib2, iclass 14, count 0 2006.225.07:56:42.67#ibcon#flushed, iclass 14, count 0 2006.225.07:56:42.67#ibcon#about to write, iclass 14, count 0 2006.225.07:56:42.67#ibcon#wrote, iclass 14, count 0 2006.225.07:56:42.67#ibcon#about to read 3, iclass 14, count 0 2006.225.07:56:42.70#ibcon#read 3, iclass 14, count 0 2006.225.07:56:42.70#ibcon#about to read 4, iclass 14, count 0 2006.225.07:56:42.70#ibcon#read 4, iclass 14, count 0 2006.225.07:56:42.70#ibcon#about to read 5, iclass 14, count 0 2006.225.07:56:42.70#ibcon#read 5, iclass 14, count 0 2006.225.07:56:42.70#ibcon#about to read 6, iclass 14, count 0 2006.225.07:56:42.70#ibcon#read 6, iclass 14, count 0 2006.225.07:56:42.70#ibcon#end of sib2, iclass 14, count 0 2006.225.07:56:42.70#ibcon#*after write, iclass 14, count 0 2006.225.07:56:42.70#ibcon#*before return 0, iclass 14, count 0 2006.225.07:56:42.70#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:56:42.70#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.07:56:42.70#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.07:56:42.70#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.07:56:42.70$4f8m12a/ifd4f 2006.225.07:56:42.70$ifd4f/lo= 2006.225.07:56:42.70$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.07:56:42.70$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.07:56:42.70$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.07:56:42.70$ifd4f/patch= 2006.225.07:56:42.70$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.07:56:42.70$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.07:56:42.70$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.07:56:42.70$4f8m12a/"form=m,16.000,1:2 2006.225.07:56:42.70$4f8m12a/"tpicd 2006.225.07:56:42.70$4f8m12a/echo=off 2006.225.07:56:42.70$4f8m12a/xlog=off 2006.225.07:56:42.70:!2006.225.07:58:50 2006.225.07:57:14.14#trakl#Source acquired 2006.225.07:57:16.14#flagr#flagr/antenna,acquired 2006.225.07:58:50.00:preob 2006.225.07:58:50.14/onsource/TRACKING 2006.225.07:58:50.14:!2006.225.07:59:00 2006.225.07:59:00.00:data_valid=on 2006.225.07:59:00.00:midob 2006.225.07:59:01.14/onsource/TRACKING 2006.225.07:59:01.14/wx/28.36,1003.4,71 2006.225.07:59:01.30/cable/+6.4048E-03 2006.225.07:59:02.39/va/01,08,usb,yes,28,29 2006.225.07:59:02.39/va/02,07,usb,yes,28,29 2006.225.07:59:02.39/va/03,06,usb,yes,30,30 2006.225.07:59:02.39/va/04,07,usb,yes,29,32 2006.225.07:59:02.39/va/05,07,usb,yes,31,33 2006.225.07:59:02.39/va/06,06,usb,yes,31,31 2006.225.07:59:02.39/va/07,06,usb,yes,31,31 2006.225.07:59:02.39/va/08,07,usb,yes,30,29 2006.225.07:59:02.62/valo/01,532.99,yes,locked 2006.225.07:59:02.62/valo/02,572.99,yes,locked 2006.225.07:59:02.62/valo/03,672.99,yes,locked 2006.225.07:59:02.62/valo/04,832.99,yes,locked 2006.225.07:59:02.62/valo/05,652.99,yes,locked 2006.225.07:59:02.62/valo/06,772.99,yes,locked 2006.225.07:59:02.62/valo/07,832.99,yes,locked 2006.225.07:59:02.62/valo/08,852.99,yes,locked 2006.225.07:59:03.71/vb/01,04,usb,yes,30,29 2006.225.07:59:03.71/vb/02,04,usb,yes,32,34 2006.225.07:59:03.71/vb/03,04,usb,yes,28,32 2006.225.07:59:03.71/vb/04,04,usb,yes,29,29 2006.225.07:59:03.71/vb/05,04,usb,yes,28,32 2006.225.07:59:03.71/vb/06,04,usb,yes,28,31 2006.225.07:59:03.71/vb/07,04,usb,yes,31,31 2006.225.07:59:03.71/vb/08,04,usb,yes,28,32 2006.225.07:59:03.95/vblo/01,632.99,yes,locked 2006.225.07:59:03.95/vblo/02,640.99,yes,locked 2006.225.07:59:03.95/vblo/03,656.99,yes,locked 2006.225.07:59:03.95/vblo/04,712.99,yes,locked 2006.225.07:59:03.95/vblo/05,744.99,yes,locked 2006.225.07:59:03.95/vblo/06,752.99,yes,locked 2006.225.07:59:03.95/vblo/07,734.99,yes,locked 2006.225.07:59:03.95/vblo/08,744.99,yes,locked 2006.225.07:59:04.10/vabw/8 2006.225.07:59:04.25/vbbw/8 2006.225.07:59:04.34/xfe/off,on,15.0 2006.225.07:59:04.74/ifatt/23,28,28,28 2006.225.07:59:05.08/fmout-gps/S +4.55E-07 2006.225.07:59:05.12:!2006.225.08:00:00 2006.225.08:00:00.00:data_valid=off 2006.225.08:00:00.00:postob 2006.225.08:00:00.15/cable/+6.4040E-03 2006.225.08:00:00.15/wx/28.35,1003.4,71 2006.225.08:00:01.08/fmout-gps/S +4.55E-07 2006.225.08:00:01.08:scan_name=225-0800,k06225,60 2006.225.08:00:01.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.225.08:00:01.13#flagr#flagr/antenna,new-source 2006.225.08:00:02.13:checkk5 2006.225.08:00:02.50/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:00:02.86/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:00:03.25/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:00:03.62/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:00:03.98/chk_obsdata//k5ts1/T2250759??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:00:04.35/chk_obsdata//k5ts2/T2250759??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:00:04.71/chk_obsdata//k5ts3/T2250759??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:00:05.08/chk_obsdata//k5ts4/T2250759??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:00:05.76/k5log//k5ts1_log_newline 2006.225.08:00:06.45/k5log//k5ts2_log_newline 2006.225.08:00:07.13/k5log//k5ts3_log_newline 2006.225.08:00:07.81/k5log//k5ts4_log_newline 2006.225.08:00:07.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:00:07.84:4f8m12a=2 2006.225.08:00:07.84$4f8m12a/echo=on 2006.225.08:00:07.84$4f8m12a/pcalon 2006.225.08:00:07.84$pcalon/"no phase cal control is implemented here 2006.225.08:00:07.84$4f8m12a/"tpicd=stop 2006.225.08:00:07.84$4f8m12a/vc4f8 2006.225.08:00:07.84$vc4f8/valo=1,532.99 2006.225.08:00:07.84#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.08:00:07.84#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.08:00:07.84#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:07.84#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:00:07.84#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:00:07.84#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:00:07.84#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:00:07.84#ibcon#first serial, iclass 16, count 0 2006.225.08:00:07.84#ibcon#enter sib2, iclass 16, count 0 2006.225.08:00:07.84#ibcon#flushed, iclass 16, count 0 2006.225.08:00:07.84#ibcon#about to write, iclass 16, count 0 2006.225.08:00:07.84#ibcon#wrote, iclass 16, count 0 2006.225.08:00:07.84#ibcon#about to read 3, iclass 16, count 0 2006.225.08:00:07.86#ibcon#read 3, iclass 16, count 0 2006.225.08:00:07.86#ibcon#about to read 4, iclass 16, count 0 2006.225.08:00:07.86#ibcon#read 4, iclass 16, count 0 2006.225.08:00:07.86#ibcon#about to read 5, iclass 16, count 0 2006.225.08:00:07.86#ibcon#read 5, iclass 16, count 0 2006.225.08:00:07.86#ibcon#about to read 6, iclass 16, count 0 2006.225.08:00:07.86#ibcon#read 6, iclass 16, count 0 2006.225.08:00:07.86#ibcon#end of sib2, iclass 16, count 0 2006.225.08:00:07.86#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:00:07.86#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:00:07.86#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:00:07.86#ibcon#*before write, iclass 16, count 0 2006.225.08:00:07.86#ibcon#enter sib2, iclass 16, count 0 2006.225.08:00:07.86#ibcon#flushed, iclass 16, count 0 2006.225.08:00:07.86#ibcon#about to write, iclass 16, count 0 2006.225.08:00:07.86#ibcon#wrote, iclass 16, count 0 2006.225.08:00:07.86#ibcon#about to read 3, iclass 16, count 0 2006.225.08:00:07.91#ibcon#read 3, iclass 16, count 0 2006.225.08:00:07.91#ibcon#about to read 4, iclass 16, count 0 2006.225.08:00:07.91#ibcon#read 4, iclass 16, count 0 2006.225.08:00:07.91#ibcon#about to read 5, iclass 16, count 0 2006.225.08:00:07.91#ibcon#read 5, iclass 16, count 0 2006.225.08:00:07.91#ibcon#about to read 6, iclass 16, count 0 2006.225.08:00:07.91#ibcon#read 6, iclass 16, count 0 2006.225.08:00:07.91#ibcon#end of sib2, iclass 16, count 0 2006.225.08:00:07.91#ibcon#*after write, iclass 16, count 0 2006.225.08:00:07.91#ibcon#*before return 0, iclass 16, count 0 2006.225.08:00:07.91#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:00:07.91#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:00:07.91#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:00:07.91#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:00:07.91$vc4f8/va=1,8 2006.225.08:00:07.91#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.225.08:00:07.91#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.225.08:00:07.91#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:07.91#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:00:07.91#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:00:07.91#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:00:07.91#ibcon#enter wrdev, iclass 18, count 2 2006.225.08:00:07.91#ibcon#first serial, iclass 18, count 2 2006.225.08:00:07.91#ibcon#enter sib2, iclass 18, count 2 2006.225.08:00:07.91#ibcon#flushed, iclass 18, count 2 2006.225.08:00:07.91#ibcon#about to write, iclass 18, count 2 2006.225.08:00:07.91#ibcon#wrote, iclass 18, count 2 2006.225.08:00:07.91#ibcon#about to read 3, iclass 18, count 2 2006.225.08:00:07.93#ibcon#read 3, iclass 18, count 2 2006.225.08:00:07.93#ibcon#about to read 4, iclass 18, count 2 2006.225.08:00:07.93#ibcon#read 4, iclass 18, count 2 2006.225.08:00:07.93#ibcon#about to read 5, iclass 18, count 2 2006.225.08:00:07.93#ibcon#read 5, iclass 18, count 2 2006.225.08:00:07.93#ibcon#about to read 6, iclass 18, count 2 2006.225.08:00:07.93#ibcon#read 6, iclass 18, count 2 2006.225.08:00:07.93#ibcon#end of sib2, iclass 18, count 2 2006.225.08:00:07.93#ibcon#*mode == 0, iclass 18, count 2 2006.225.08:00:07.93#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.225.08:00:07.93#ibcon#[25=AT01-08\r\n] 2006.225.08:00:07.93#ibcon#*before write, iclass 18, count 2 2006.225.08:00:07.93#ibcon#enter sib2, iclass 18, count 2 2006.225.08:00:07.93#ibcon#flushed, iclass 18, count 2 2006.225.08:00:07.93#ibcon#about to write, iclass 18, count 2 2006.225.08:00:07.93#ibcon#wrote, iclass 18, count 2 2006.225.08:00:07.93#ibcon#about to read 3, iclass 18, count 2 2006.225.08:00:07.96#ibcon#read 3, iclass 18, count 2 2006.225.08:00:07.96#ibcon#about to read 4, iclass 18, count 2 2006.225.08:00:07.96#ibcon#read 4, iclass 18, count 2 2006.225.08:00:07.96#ibcon#about to read 5, iclass 18, count 2 2006.225.08:00:07.96#ibcon#read 5, iclass 18, count 2 2006.225.08:00:07.96#ibcon#about to read 6, iclass 18, count 2 2006.225.08:00:07.96#ibcon#read 6, iclass 18, count 2 2006.225.08:00:07.96#ibcon#end of sib2, iclass 18, count 2 2006.225.08:00:07.96#ibcon#*after write, iclass 18, count 2 2006.225.08:00:07.96#ibcon#*before return 0, iclass 18, count 2 2006.225.08:00:07.96#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:00:07.96#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:00:07.96#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.225.08:00:07.96#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:07.96#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:00:08.08#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:00:08.08#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:00:08.08#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:00:08.08#ibcon#first serial, iclass 18, count 0 2006.225.08:00:08.08#ibcon#enter sib2, iclass 18, count 0 2006.225.08:00:08.08#ibcon#flushed, iclass 18, count 0 2006.225.08:00:08.08#ibcon#about to write, iclass 18, count 0 2006.225.08:00:08.08#ibcon#wrote, iclass 18, count 0 2006.225.08:00:08.08#ibcon#about to read 3, iclass 18, count 0 2006.225.08:00:08.10#ibcon#read 3, iclass 18, count 0 2006.225.08:00:08.10#ibcon#about to read 4, iclass 18, count 0 2006.225.08:00:08.10#ibcon#read 4, iclass 18, count 0 2006.225.08:00:08.10#ibcon#about to read 5, iclass 18, count 0 2006.225.08:00:08.10#ibcon#read 5, iclass 18, count 0 2006.225.08:00:08.10#ibcon#about to read 6, iclass 18, count 0 2006.225.08:00:08.10#ibcon#read 6, iclass 18, count 0 2006.225.08:00:08.10#ibcon#end of sib2, iclass 18, count 0 2006.225.08:00:08.10#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:00:08.10#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:00:08.10#ibcon#[25=USB\r\n] 2006.225.08:00:08.10#ibcon#*before write, iclass 18, count 0 2006.225.08:00:08.10#ibcon#enter sib2, iclass 18, count 0 2006.225.08:00:08.10#ibcon#flushed, iclass 18, count 0 2006.225.08:00:08.10#ibcon#about to write, iclass 18, count 0 2006.225.08:00:08.10#ibcon#wrote, iclass 18, count 0 2006.225.08:00:08.10#ibcon#about to read 3, iclass 18, count 0 2006.225.08:00:08.13#ibcon#read 3, iclass 18, count 0 2006.225.08:00:08.13#ibcon#about to read 4, iclass 18, count 0 2006.225.08:00:08.13#ibcon#read 4, iclass 18, count 0 2006.225.08:00:08.13#ibcon#about to read 5, iclass 18, count 0 2006.225.08:00:08.13#ibcon#read 5, iclass 18, count 0 2006.225.08:00:08.13#ibcon#about to read 6, iclass 18, count 0 2006.225.08:00:08.13#ibcon#read 6, iclass 18, count 0 2006.225.08:00:08.13#ibcon#end of sib2, iclass 18, count 0 2006.225.08:00:08.13#ibcon#*after write, iclass 18, count 0 2006.225.08:00:08.13#ibcon#*before return 0, iclass 18, count 0 2006.225.08:00:08.13#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:00:08.13#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:00:08.13#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:00:08.13#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:00:08.13$vc4f8/valo=2,572.99 2006.225.08:00:08.13#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.225.08:00:08.13#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.225.08:00:08.13#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:08.13#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:00:08.13#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:00:08.13#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:00:08.13#ibcon#enter wrdev, iclass 20, count 0 2006.225.08:00:08.13#ibcon#first serial, iclass 20, count 0 2006.225.08:00:08.13#ibcon#enter sib2, iclass 20, count 0 2006.225.08:00:08.13#ibcon#flushed, iclass 20, count 0 2006.225.08:00:08.13#ibcon#about to write, iclass 20, count 0 2006.225.08:00:08.13#ibcon#wrote, iclass 20, count 0 2006.225.08:00:08.13#ibcon#about to read 3, iclass 20, count 0 2006.225.08:00:08.15#ibcon#read 3, iclass 20, count 0 2006.225.08:00:08.15#ibcon#about to read 4, iclass 20, count 0 2006.225.08:00:08.15#ibcon#read 4, iclass 20, count 0 2006.225.08:00:08.15#ibcon#about to read 5, iclass 20, count 0 2006.225.08:00:08.15#ibcon#read 5, iclass 20, count 0 2006.225.08:00:08.15#ibcon#about to read 6, iclass 20, count 0 2006.225.08:00:08.15#ibcon#read 6, iclass 20, count 0 2006.225.08:00:08.15#ibcon#end of sib2, iclass 20, count 0 2006.225.08:00:08.15#ibcon#*mode == 0, iclass 20, count 0 2006.225.08:00:08.15#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.08:00:08.15#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:00:08.15#ibcon#*before write, iclass 20, count 0 2006.225.08:00:08.15#ibcon#enter sib2, iclass 20, count 0 2006.225.08:00:08.15#ibcon#flushed, iclass 20, count 0 2006.225.08:00:08.15#ibcon#about to write, iclass 20, count 0 2006.225.08:00:08.15#ibcon#wrote, iclass 20, count 0 2006.225.08:00:08.15#ibcon#about to read 3, iclass 20, count 0 2006.225.08:00:08.20#ibcon#read 3, iclass 20, count 0 2006.225.08:00:08.20#ibcon#about to read 4, iclass 20, count 0 2006.225.08:00:08.20#ibcon#read 4, iclass 20, count 0 2006.225.08:00:08.20#ibcon#about to read 5, iclass 20, count 0 2006.225.08:00:08.20#ibcon#read 5, iclass 20, count 0 2006.225.08:00:08.20#ibcon#about to read 6, iclass 20, count 0 2006.225.08:00:08.20#ibcon#read 6, iclass 20, count 0 2006.225.08:00:08.20#ibcon#end of sib2, iclass 20, count 0 2006.225.08:00:08.20#ibcon#*after write, iclass 20, count 0 2006.225.08:00:08.20#ibcon#*before return 0, iclass 20, count 0 2006.225.08:00:08.20#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:00:08.20#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:00:08.20#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.08:00:08.20#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.08:00:08.20$vc4f8/va=2,7 2006.225.08:00:08.20#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.225.08:00:08.20#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.225.08:00:08.20#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:08.20#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:00:08.25#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:00:08.25#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:00:08.25#ibcon#enter wrdev, iclass 22, count 2 2006.225.08:00:08.25#ibcon#first serial, iclass 22, count 2 2006.225.08:00:08.25#ibcon#enter sib2, iclass 22, count 2 2006.225.08:00:08.25#ibcon#flushed, iclass 22, count 2 2006.225.08:00:08.25#ibcon#about to write, iclass 22, count 2 2006.225.08:00:08.25#ibcon#wrote, iclass 22, count 2 2006.225.08:00:08.25#ibcon#about to read 3, iclass 22, count 2 2006.225.08:00:08.27#ibcon#read 3, iclass 22, count 2 2006.225.08:00:08.27#ibcon#about to read 4, iclass 22, count 2 2006.225.08:00:08.27#ibcon#read 4, iclass 22, count 2 2006.225.08:00:08.27#ibcon#about to read 5, iclass 22, count 2 2006.225.08:00:08.27#ibcon#read 5, iclass 22, count 2 2006.225.08:00:08.27#ibcon#about to read 6, iclass 22, count 2 2006.225.08:00:08.27#ibcon#read 6, iclass 22, count 2 2006.225.08:00:08.27#ibcon#end of sib2, iclass 22, count 2 2006.225.08:00:08.27#ibcon#*mode == 0, iclass 22, count 2 2006.225.08:00:08.27#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.225.08:00:08.27#ibcon#[25=AT02-07\r\n] 2006.225.08:00:08.27#ibcon#*before write, iclass 22, count 2 2006.225.08:00:08.27#ibcon#enter sib2, iclass 22, count 2 2006.225.08:00:08.27#ibcon#flushed, iclass 22, count 2 2006.225.08:00:08.27#ibcon#about to write, iclass 22, count 2 2006.225.08:00:08.27#ibcon#wrote, iclass 22, count 2 2006.225.08:00:08.27#ibcon#about to read 3, iclass 22, count 2 2006.225.08:00:08.30#ibcon#read 3, iclass 22, count 2 2006.225.08:00:08.30#ibcon#about to read 4, iclass 22, count 2 2006.225.08:00:08.30#ibcon#read 4, iclass 22, count 2 2006.225.08:00:08.30#ibcon#about to read 5, iclass 22, count 2 2006.225.08:00:08.30#ibcon#read 5, iclass 22, count 2 2006.225.08:00:08.30#ibcon#about to read 6, iclass 22, count 2 2006.225.08:00:08.30#ibcon#read 6, iclass 22, count 2 2006.225.08:00:08.30#ibcon#end of sib2, iclass 22, count 2 2006.225.08:00:08.30#ibcon#*after write, iclass 22, count 2 2006.225.08:00:08.30#ibcon#*before return 0, iclass 22, count 2 2006.225.08:00:08.30#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:00:08.30#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:00:08.30#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.225.08:00:08.30#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:08.30#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:00:08.42#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:00:08.42#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:00:08.42#ibcon#enter wrdev, iclass 22, count 0 2006.225.08:00:08.42#ibcon#first serial, iclass 22, count 0 2006.225.08:00:08.42#ibcon#enter sib2, iclass 22, count 0 2006.225.08:00:08.42#ibcon#flushed, iclass 22, count 0 2006.225.08:00:08.42#ibcon#about to write, iclass 22, count 0 2006.225.08:00:08.42#ibcon#wrote, iclass 22, count 0 2006.225.08:00:08.42#ibcon#about to read 3, iclass 22, count 0 2006.225.08:00:08.44#ibcon#read 3, iclass 22, count 0 2006.225.08:00:08.44#ibcon#about to read 4, iclass 22, count 0 2006.225.08:00:08.44#ibcon#read 4, iclass 22, count 0 2006.225.08:00:08.44#ibcon#about to read 5, iclass 22, count 0 2006.225.08:00:08.44#ibcon#read 5, iclass 22, count 0 2006.225.08:00:08.44#ibcon#about to read 6, iclass 22, count 0 2006.225.08:00:08.44#ibcon#read 6, iclass 22, count 0 2006.225.08:00:08.44#ibcon#end of sib2, iclass 22, count 0 2006.225.08:00:08.44#ibcon#*mode == 0, iclass 22, count 0 2006.225.08:00:08.44#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.08:00:08.44#ibcon#[25=USB\r\n] 2006.225.08:00:08.44#ibcon#*before write, iclass 22, count 0 2006.225.08:00:08.44#ibcon#enter sib2, iclass 22, count 0 2006.225.08:00:08.44#ibcon#flushed, iclass 22, count 0 2006.225.08:00:08.44#ibcon#about to write, iclass 22, count 0 2006.225.08:00:08.44#ibcon#wrote, iclass 22, count 0 2006.225.08:00:08.44#ibcon#about to read 3, iclass 22, count 0 2006.225.08:00:08.47#ibcon#read 3, iclass 22, count 0 2006.225.08:00:08.47#ibcon#about to read 4, iclass 22, count 0 2006.225.08:00:08.47#ibcon#read 4, iclass 22, count 0 2006.225.08:00:08.47#ibcon#about to read 5, iclass 22, count 0 2006.225.08:00:08.47#ibcon#read 5, iclass 22, count 0 2006.225.08:00:08.47#ibcon#about to read 6, iclass 22, count 0 2006.225.08:00:08.47#ibcon#read 6, iclass 22, count 0 2006.225.08:00:08.47#ibcon#end of sib2, iclass 22, count 0 2006.225.08:00:08.47#ibcon#*after write, iclass 22, count 0 2006.225.08:00:08.47#ibcon#*before return 0, iclass 22, count 0 2006.225.08:00:08.47#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:00:08.47#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:00:08.47#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.08:00:08.47#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.08:00:08.47$vc4f8/valo=3,672.99 2006.225.08:00:08.47#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.08:00:08.47#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.08:00:08.47#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:08.47#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:00:08.47#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:00:08.47#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:00:08.47#ibcon#enter wrdev, iclass 24, count 0 2006.225.08:00:08.47#ibcon#first serial, iclass 24, count 0 2006.225.08:00:08.47#ibcon#enter sib2, iclass 24, count 0 2006.225.08:00:08.47#ibcon#flushed, iclass 24, count 0 2006.225.08:00:08.47#ibcon#about to write, iclass 24, count 0 2006.225.08:00:08.47#ibcon#wrote, iclass 24, count 0 2006.225.08:00:08.47#ibcon#about to read 3, iclass 24, count 0 2006.225.08:00:08.49#ibcon#read 3, iclass 24, count 0 2006.225.08:00:08.49#ibcon#about to read 4, iclass 24, count 0 2006.225.08:00:08.49#ibcon#read 4, iclass 24, count 0 2006.225.08:00:08.49#ibcon#about to read 5, iclass 24, count 0 2006.225.08:00:08.49#ibcon#read 5, iclass 24, count 0 2006.225.08:00:08.49#ibcon#about to read 6, iclass 24, count 0 2006.225.08:00:08.49#ibcon#read 6, iclass 24, count 0 2006.225.08:00:08.49#ibcon#end of sib2, iclass 24, count 0 2006.225.08:00:08.49#ibcon#*mode == 0, iclass 24, count 0 2006.225.08:00:08.49#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.08:00:08.49#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:00:08.49#ibcon#*before write, iclass 24, count 0 2006.225.08:00:08.49#ibcon#enter sib2, iclass 24, count 0 2006.225.08:00:08.49#ibcon#flushed, iclass 24, count 0 2006.225.08:00:08.49#ibcon#about to write, iclass 24, count 0 2006.225.08:00:08.49#ibcon#wrote, iclass 24, count 0 2006.225.08:00:08.49#ibcon#about to read 3, iclass 24, count 0 2006.225.08:00:08.52#abcon#<5=/05 2.7 5.2 28.34 711003.4\r\n> 2006.225.08:00:08.54#abcon#{5=INTERFACE CLEAR} 2006.225.08:00:08.54#ibcon#read 3, iclass 24, count 0 2006.225.08:00:08.54#ibcon#about to read 4, iclass 24, count 0 2006.225.08:00:08.54#ibcon#read 4, iclass 24, count 0 2006.225.08:00:08.54#ibcon#about to read 5, iclass 24, count 0 2006.225.08:00:08.54#ibcon#read 5, iclass 24, count 0 2006.225.08:00:08.54#ibcon#about to read 6, iclass 24, count 0 2006.225.08:00:08.54#ibcon#read 6, iclass 24, count 0 2006.225.08:00:08.54#ibcon#end of sib2, iclass 24, count 0 2006.225.08:00:08.54#ibcon#*after write, iclass 24, count 0 2006.225.08:00:08.54#ibcon#*before return 0, iclass 24, count 0 2006.225.08:00:08.54#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:00:08.54#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:00:08.54#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.08:00:08.54#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.08:00:08.54$vc4f8/va=3,6 2006.225.08:00:08.54#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.225.08:00:08.54#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.225.08:00:08.54#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:08.54#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:00:08.59#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:00:08.59#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:00:08.59#ibcon#enter wrdev, iclass 29, count 2 2006.225.08:00:08.59#ibcon#first serial, iclass 29, count 2 2006.225.08:00:08.59#ibcon#enter sib2, iclass 29, count 2 2006.225.08:00:08.59#ibcon#flushed, iclass 29, count 2 2006.225.08:00:08.59#ibcon#about to write, iclass 29, count 2 2006.225.08:00:08.59#ibcon#wrote, iclass 29, count 2 2006.225.08:00:08.59#ibcon#about to read 3, iclass 29, count 2 2006.225.08:00:08.60#abcon#[5=S1D000X0/0*\r\n] 2006.225.08:00:08.61#ibcon#read 3, iclass 29, count 2 2006.225.08:00:08.61#ibcon#about to read 4, iclass 29, count 2 2006.225.08:00:08.61#ibcon#read 4, iclass 29, count 2 2006.225.08:00:08.61#ibcon#about to read 5, iclass 29, count 2 2006.225.08:00:08.61#ibcon#read 5, iclass 29, count 2 2006.225.08:00:08.61#ibcon#about to read 6, iclass 29, count 2 2006.225.08:00:08.61#ibcon#read 6, iclass 29, count 2 2006.225.08:00:08.61#ibcon#end of sib2, iclass 29, count 2 2006.225.08:00:08.61#ibcon#*mode == 0, iclass 29, count 2 2006.225.08:00:08.61#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.225.08:00:08.61#ibcon#[25=AT03-06\r\n] 2006.225.08:00:08.61#ibcon#*before write, iclass 29, count 2 2006.225.08:00:08.61#ibcon#enter sib2, iclass 29, count 2 2006.225.08:00:08.61#ibcon#flushed, iclass 29, count 2 2006.225.08:00:08.61#ibcon#about to write, iclass 29, count 2 2006.225.08:00:08.61#ibcon#wrote, iclass 29, count 2 2006.225.08:00:08.61#ibcon#about to read 3, iclass 29, count 2 2006.225.08:00:08.64#ibcon#read 3, iclass 29, count 2 2006.225.08:00:08.64#ibcon#about to read 4, iclass 29, count 2 2006.225.08:00:08.64#ibcon#read 4, iclass 29, count 2 2006.225.08:00:08.64#ibcon#about to read 5, iclass 29, count 2 2006.225.08:00:08.64#ibcon#read 5, iclass 29, count 2 2006.225.08:00:08.64#ibcon#about to read 6, iclass 29, count 2 2006.225.08:00:08.64#ibcon#read 6, iclass 29, count 2 2006.225.08:00:08.64#ibcon#end of sib2, iclass 29, count 2 2006.225.08:00:08.64#ibcon#*after write, iclass 29, count 2 2006.225.08:00:08.64#ibcon#*before return 0, iclass 29, count 2 2006.225.08:00:08.64#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:00:08.64#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:00:08.64#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.225.08:00:08.64#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:08.64#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:00:08.76#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:00:08.76#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:00:08.76#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:00:08.76#ibcon#first serial, iclass 29, count 0 2006.225.08:00:08.76#ibcon#enter sib2, iclass 29, count 0 2006.225.08:00:08.76#ibcon#flushed, iclass 29, count 0 2006.225.08:00:08.76#ibcon#about to write, iclass 29, count 0 2006.225.08:00:08.76#ibcon#wrote, iclass 29, count 0 2006.225.08:00:08.76#ibcon#about to read 3, iclass 29, count 0 2006.225.08:00:08.78#ibcon#read 3, iclass 29, count 0 2006.225.08:00:08.78#ibcon#about to read 4, iclass 29, count 0 2006.225.08:00:08.78#ibcon#read 4, iclass 29, count 0 2006.225.08:00:08.78#ibcon#about to read 5, iclass 29, count 0 2006.225.08:00:08.78#ibcon#read 5, iclass 29, count 0 2006.225.08:00:08.78#ibcon#about to read 6, iclass 29, count 0 2006.225.08:00:08.78#ibcon#read 6, iclass 29, count 0 2006.225.08:00:08.78#ibcon#end of sib2, iclass 29, count 0 2006.225.08:00:08.78#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:00:08.78#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:00:08.78#ibcon#[25=USB\r\n] 2006.225.08:00:08.78#ibcon#*before write, iclass 29, count 0 2006.225.08:00:08.78#ibcon#enter sib2, iclass 29, count 0 2006.225.08:00:08.78#ibcon#flushed, iclass 29, count 0 2006.225.08:00:08.78#ibcon#about to write, iclass 29, count 0 2006.225.08:00:08.78#ibcon#wrote, iclass 29, count 0 2006.225.08:00:08.78#ibcon#about to read 3, iclass 29, count 0 2006.225.08:00:08.81#ibcon#read 3, iclass 29, count 0 2006.225.08:00:08.81#ibcon#about to read 4, iclass 29, count 0 2006.225.08:00:08.81#ibcon#read 4, iclass 29, count 0 2006.225.08:00:08.81#ibcon#about to read 5, iclass 29, count 0 2006.225.08:00:08.81#ibcon#read 5, iclass 29, count 0 2006.225.08:00:08.81#ibcon#about to read 6, iclass 29, count 0 2006.225.08:00:08.81#ibcon#read 6, iclass 29, count 0 2006.225.08:00:08.81#ibcon#end of sib2, iclass 29, count 0 2006.225.08:00:08.81#ibcon#*after write, iclass 29, count 0 2006.225.08:00:08.81#ibcon#*before return 0, iclass 29, count 0 2006.225.08:00:08.81#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:00:08.81#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:00:08.81#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:00:08.81#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:00:08.81$vc4f8/valo=4,832.99 2006.225.08:00:08.81#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.08:00:08.81#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.08:00:08.81#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:08.81#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:00:08.81#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:00:08.81#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:00:08.81#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:00:08.81#ibcon#first serial, iclass 32, count 0 2006.225.08:00:08.81#ibcon#enter sib2, iclass 32, count 0 2006.225.08:00:08.81#ibcon#flushed, iclass 32, count 0 2006.225.08:00:08.81#ibcon#about to write, iclass 32, count 0 2006.225.08:00:08.81#ibcon#wrote, iclass 32, count 0 2006.225.08:00:08.81#ibcon#about to read 3, iclass 32, count 0 2006.225.08:00:08.83#ibcon#read 3, iclass 32, count 0 2006.225.08:00:08.83#ibcon#about to read 4, iclass 32, count 0 2006.225.08:00:08.83#ibcon#read 4, iclass 32, count 0 2006.225.08:00:08.83#ibcon#about to read 5, iclass 32, count 0 2006.225.08:00:08.83#ibcon#read 5, iclass 32, count 0 2006.225.08:00:08.83#ibcon#about to read 6, iclass 32, count 0 2006.225.08:00:08.83#ibcon#read 6, iclass 32, count 0 2006.225.08:00:08.83#ibcon#end of sib2, iclass 32, count 0 2006.225.08:00:08.83#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:00:08.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:00:08.83#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:00:08.83#ibcon#*before write, iclass 32, count 0 2006.225.08:00:08.83#ibcon#enter sib2, iclass 32, count 0 2006.225.08:00:08.83#ibcon#flushed, iclass 32, count 0 2006.225.08:00:08.83#ibcon#about to write, iclass 32, count 0 2006.225.08:00:08.83#ibcon#wrote, iclass 32, count 0 2006.225.08:00:08.83#ibcon#about to read 3, iclass 32, count 0 2006.225.08:00:08.87#ibcon#read 3, iclass 32, count 0 2006.225.08:00:08.87#ibcon#about to read 4, iclass 32, count 0 2006.225.08:00:08.87#ibcon#read 4, iclass 32, count 0 2006.225.08:00:08.87#ibcon#about to read 5, iclass 32, count 0 2006.225.08:00:08.87#ibcon#read 5, iclass 32, count 0 2006.225.08:00:08.87#ibcon#about to read 6, iclass 32, count 0 2006.225.08:00:08.87#ibcon#read 6, iclass 32, count 0 2006.225.08:00:08.87#ibcon#end of sib2, iclass 32, count 0 2006.225.08:00:08.87#ibcon#*after write, iclass 32, count 0 2006.225.08:00:08.87#ibcon#*before return 0, iclass 32, count 0 2006.225.08:00:08.87#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:00:08.87#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:00:08.87#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:00:08.87#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:00:08.87$vc4f8/va=4,7 2006.225.08:00:08.87#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.08:00:08.87#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.08:00:08.87#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:08.87#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:00:08.93#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:00:08.93#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:00:08.93#ibcon#enter wrdev, iclass 34, count 2 2006.225.08:00:08.93#ibcon#first serial, iclass 34, count 2 2006.225.08:00:08.93#ibcon#enter sib2, iclass 34, count 2 2006.225.08:00:08.93#ibcon#flushed, iclass 34, count 2 2006.225.08:00:08.93#ibcon#about to write, iclass 34, count 2 2006.225.08:00:08.93#ibcon#wrote, iclass 34, count 2 2006.225.08:00:08.93#ibcon#about to read 3, iclass 34, count 2 2006.225.08:00:08.95#ibcon#read 3, iclass 34, count 2 2006.225.08:00:08.95#ibcon#about to read 4, iclass 34, count 2 2006.225.08:00:08.95#ibcon#read 4, iclass 34, count 2 2006.225.08:00:08.95#ibcon#about to read 5, iclass 34, count 2 2006.225.08:00:08.95#ibcon#read 5, iclass 34, count 2 2006.225.08:00:08.95#ibcon#about to read 6, iclass 34, count 2 2006.225.08:00:08.95#ibcon#read 6, iclass 34, count 2 2006.225.08:00:08.95#ibcon#end of sib2, iclass 34, count 2 2006.225.08:00:08.95#ibcon#*mode == 0, iclass 34, count 2 2006.225.08:00:08.95#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.08:00:08.95#ibcon#[25=AT04-07\r\n] 2006.225.08:00:08.95#ibcon#*before write, iclass 34, count 2 2006.225.08:00:08.95#ibcon#enter sib2, iclass 34, count 2 2006.225.08:00:08.95#ibcon#flushed, iclass 34, count 2 2006.225.08:00:08.95#ibcon#about to write, iclass 34, count 2 2006.225.08:00:08.95#ibcon#wrote, iclass 34, count 2 2006.225.08:00:08.95#ibcon#about to read 3, iclass 34, count 2 2006.225.08:00:08.98#ibcon#read 3, iclass 34, count 2 2006.225.08:00:08.98#ibcon#about to read 4, iclass 34, count 2 2006.225.08:00:08.98#ibcon#read 4, iclass 34, count 2 2006.225.08:00:08.98#ibcon#about to read 5, iclass 34, count 2 2006.225.08:00:08.98#ibcon#read 5, iclass 34, count 2 2006.225.08:00:08.98#ibcon#about to read 6, iclass 34, count 2 2006.225.08:00:08.98#ibcon#read 6, iclass 34, count 2 2006.225.08:00:08.98#ibcon#end of sib2, iclass 34, count 2 2006.225.08:00:08.98#ibcon#*after write, iclass 34, count 2 2006.225.08:00:08.98#ibcon#*before return 0, iclass 34, count 2 2006.225.08:00:08.98#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:00:08.98#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:00:08.98#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.08:00:08.98#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:08.98#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:00:09.10#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:00:09.10#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:00:09.10#ibcon#enter wrdev, iclass 34, count 0 2006.225.08:00:09.10#ibcon#first serial, iclass 34, count 0 2006.225.08:00:09.10#ibcon#enter sib2, iclass 34, count 0 2006.225.08:00:09.10#ibcon#flushed, iclass 34, count 0 2006.225.08:00:09.10#ibcon#about to write, iclass 34, count 0 2006.225.08:00:09.10#ibcon#wrote, iclass 34, count 0 2006.225.08:00:09.10#ibcon#about to read 3, iclass 34, count 0 2006.225.08:00:09.12#ibcon#read 3, iclass 34, count 0 2006.225.08:00:09.12#ibcon#about to read 4, iclass 34, count 0 2006.225.08:00:09.12#ibcon#read 4, iclass 34, count 0 2006.225.08:00:09.12#ibcon#about to read 5, iclass 34, count 0 2006.225.08:00:09.12#ibcon#read 5, iclass 34, count 0 2006.225.08:00:09.12#ibcon#about to read 6, iclass 34, count 0 2006.225.08:00:09.12#ibcon#read 6, iclass 34, count 0 2006.225.08:00:09.12#ibcon#end of sib2, iclass 34, count 0 2006.225.08:00:09.12#ibcon#*mode == 0, iclass 34, count 0 2006.225.08:00:09.12#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.08:00:09.12#ibcon#[25=USB\r\n] 2006.225.08:00:09.12#ibcon#*before write, iclass 34, count 0 2006.225.08:00:09.12#ibcon#enter sib2, iclass 34, count 0 2006.225.08:00:09.12#ibcon#flushed, iclass 34, count 0 2006.225.08:00:09.12#ibcon#about to write, iclass 34, count 0 2006.225.08:00:09.12#ibcon#wrote, iclass 34, count 0 2006.225.08:00:09.12#ibcon#about to read 3, iclass 34, count 0 2006.225.08:00:09.15#ibcon#read 3, iclass 34, count 0 2006.225.08:00:09.15#ibcon#about to read 4, iclass 34, count 0 2006.225.08:00:09.15#ibcon#read 4, iclass 34, count 0 2006.225.08:00:09.15#ibcon#about to read 5, iclass 34, count 0 2006.225.08:00:09.15#ibcon#read 5, iclass 34, count 0 2006.225.08:00:09.15#ibcon#about to read 6, iclass 34, count 0 2006.225.08:00:09.15#ibcon#read 6, iclass 34, count 0 2006.225.08:00:09.15#ibcon#end of sib2, iclass 34, count 0 2006.225.08:00:09.15#ibcon#*after write, iclass 34, count 0 2006.225.08:00:09.15#ibcon#*before return 0, iclass 34, count 0 2006.225.08:00:09.15#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:00:09.15#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:00:09.15#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.08:00:09.15#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.08:00:09.15$vc4f8/valo=5,652.99 2006.225.08:00:09.15#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.08:00:09.15#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.08:00:09.15#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:09.15#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:00:09.15#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:00:09.15#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:00:09.15#ibcon#enter wrdev, iclass 36, count 0 2006.225.08:00:09.15#ibcon#first serial, iclass 36, count 0 2006.225.08:00:09.15#ibcon#enter sib2, iclass 36, count 0 2006.225.08:00:09.15#ibcon#flushed, iclass 36, count 0 2006.225.08:00:09.15#ibcon#about to write, iclass 36, count 0 2006.225.08:00:09.15#ibcon#wrote, iclass 36, count 0 2006.225.08:00:09.15#ibcon#about to read 3, iclass 36, count 0 2006.225.08:00:09.17#ibcon#read 3, iclass 36, count 0 2006.225.08:00:09.17#ibcon#about to read 4, iclass 36, count 0 2006.225.08:00:09.17#ibcon#read 4, iclass 36, count 0 2006.225.08:00:09.17#ibcon#about to read 5, iclass 36, count 0 2006.225.08:00:09.17#ibcon#read 5, iclass 36, count 0 2006.225.08:00:09.17#ibcon#about to read 6, iclass 36, count 0 2006.225.08:00:09.17#ibcon#read 6, iclass 36, count 0 2006.225.08:00:09.17#ibcon#end of sib2, iclass 36, count 0 2006.225.08:00:09.17#ibcon#*mode == 0, iclass 36, count 0 2006.225.08:00:09.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.08:00:09.17#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:00:09.17#ibcon#*before write, iclass 36, count 0 2006.225.08:00:09.17#ibcon#enter sib2, iclass 36, count 0 2006.225.08:00:09.17#ibcon#flushed, iclass 36, count 0 2006.225.08:00:09.17#ibcon#about to write, iclass 36, count 0 2006.225.08:00:09.17#ibcon#wrote, iclass 36, count 0 2006.225.08:00:09.17#ibcon#about to read 3, iclass 36, count 0 2006.225.08:00:09.21#ibcon#read 3, iclass 36, count 0 2006.225.08:00:09.21#ibcon#about to read 4, iclass 36, count 0 2006.225.08:00:09.21#ibcon#read 4, iclass 36, count 0 2006.225.08:00:09.21#ibcon#about to read 5, iclass 36, count 0 2006.225.08:00:09.21#ibcon#read 5, iclass 36, count 0 2006.225.08:00:09.21#ibcon#about to read 6, iclass 36, count 0 2006.225.08:00:09.21#ibcon#read 6, iclass 36, count 0 2006.225.08:00:09.21#ibcon#end of sib2, iclass 36, count 0 2006.225.08:00:09.21#ibcon#*after write, iclass 36, count 0 2006.225.08:00:09.21#ibcon#*before return 0, iclass 36, count 0 2006.225.08:00:09.21#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:00:09.21#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:00:09.21#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.08:00:09.21#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.08:00:09.21$vc4f8/va=5,7 2006.225.08:00:09.21#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.08:00:09.21#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.08:00:09.21#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:09.21#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:00:09.27#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:00:09.27#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:00:09.27#ibcon#enter wrdev, iclass 38, count 2 2006.225.08:00:09.27#ibcon#first serial, iclass 38, count 2 2006.225.08:00:09.27#ibcon#enter sib2, iclass 38, count 2 2006.225.08:00:09.27#ibcon#flushed, iclass 38, count 2 2006.225.08:00:09.27#ibcon#about to write, iclass 38, count 2 2006.225.08:00:09.27#ibcon#wrote, iclass 38, count 2 2006.225.08:00:09.27#ibcon#about to read 3, iclass 38, count 2 2006.225.08:00:09.29#ibcon#read 3, iclass 38, count 2 2006.225.08:00:09.29#ibcon#about to read 4, iclass 38, count 2 2006.225.08:00:09.29#ibcon#read 4, iclass 38, count 2 2006.225.08:00:09.29#ibcon#about to read 5, iclass 38, count 2 2006.225.08:00:09.29#ibcon#read 5, iclass 38, count 2 2006.225.08:00:09.29#ibcon#about to read 6, iclass 38, count 2 2006.225.08:00:09.29#ibcon#read 6, iclass 38, count 2 2006.225.08:00:09.29#ibcon#end of sib2, iclass 38, count 2 2006.225.08:00:09.29#ibcon#*mode == 0, iclass 38, count 2 2006.225.08:00:09.29#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.08:00:09.29#ibcon#[25=AT05-07\r\n] 2006.225.08:00:09.29#ibcon#*before write, iclass 38, count 2 2006.225.08:00:09.29#ibcon#enter sib2, iclass 38, count 2 2006.225.08:00:09.29#ibcon#flushed, iclass 38, count 2 2006.225.08:00:09.29#ibcon#about to write, iclass 38, count 2 2006.225.08:00:09.29#ibcon#wrote, iclass 38, count 2 2006.225.08:00:09.29#ibcon#about to read 3, iclass 38, count 2 2006.225.08:00:09.32#ibcon#read 3, iclass 38, count 2 2006.225.08:00:09.32#ibcon#about to read 4, iclass 38, count 2 2006.225.08:00:09.32#ibcon#read 4, iclass 38, count 2 2006.225.08:00:09.32#ibcon#about to read 5, iclass 38, count 2 2006.225.08:00:09.32#ibcon#read 5, iclass 38, count 2 2006.225.08:00:09.32#ibcon#about to read 6, iclass 38, count 2 2006.225.08:00:09.32#ibcon#read 6, iclass 38, count 2 2006.225.08:00:09.32#ibcon#end of sib2, iclass 38, count 2 2006.225.08:00:09.32#ibcon#*after write, iclass 38, count 2 2006.225.08:00:09.32#ibcon#*before return 0, iclass 38, count 2 2006.225.08:00:09.32#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:00:09.32#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:00:09.32#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.08:00:09.32#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:09.32#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:00:09.44#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:00:09.44#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:00:09.44#ibcon#enter wrdev, iclass 38, count 0 2006.225.08:00:09.44#ibcon#first serial, iclass 38, count 0 2006.225.08:00:09.44#ibcon#enter sib2, iclass 38, count 0 2006.225.08:00:09.44#ibcon#flushed, iclass 38, count 0 2006.225.08:00:09.44#ibcon#about to write, iclass 38, count 0 2006.225.08:00:09.44#ibcon#wrote, iclass 38, count 0 2006.225.08:00:09.44#ibcon#about to read 3, iclass 38, count 0 2006.225.08:00:09.46#ibcon#read 3, iclass 38, count 0 2006.225.08:00:09.46#ibcon#about to read 4, iclass 38, count 0 2006.225.08:00:09.46#ibcon#read 4, iclass 38, count 0 2006.225.08:00:09.46#ibcon#about to read 5, iclass 38, count 0 2006.225.08:00:09.46#ibcon#read 5, iclass 38, count 0 2006.225.08:00:09.46#ibcon#about to read 6, iclass 38, count 0 2006.225.08:00:09.46#ibcon#read 6, iclass 38, count 0 2006.225.08:00:09.46#ibcon#end of sib2, iclass 38, count 0 2006.225.08:00:09.46#ibcon#*mode == 0, iclass 38, count 0 2006.225.08:00:09.46#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.08:00:09.46#ibcon#[25=USB\r\n] 2006.225.08:00:09.46#ibcon#*before write, iclass 38, count 0 2006.225.08:00:09.46#ibcon#enter sib2, iclass 38, count 0 2006.225.08:00:09.46#ibcon#flushed, iclass 38, count 0 2006.225.08:00:09.46#ibcon#about to write, iclass 38, count 0 2006.225.08:00:09.46#ibcon#wrote, iclass 38, count 0 2006.225.08:00:09.46#ibcon#about to read 3, iclass 38, count 0 2006.225.08:00:09.49#ibcon#read 3, iclass 38, count 0 2006.225.08:00:09.49#ibcon#about to read 4, iclass 38, count 0 2006.225.08:00:09.49#ibcon#read 4, iclass 38, count 0 2006.225.08:00:09.49#ibcon#about to read 5, iclass 38, count 0 2006.225.08:00:09.49#ibcon#read 5, iclass 38, count 0 2006.225.08:00:09.49#ibcon#about to read 6, iclass 38, count 0 2006.225.08:00:09.49#ibcon#read 6, iclass 38, count 0 2006.225.08:00:09.49#ibcon#end of sib2, iclass 38, count 0 2006.225.08:00:09.49#ibcon#*after write, iclass 38, count 0 2006.225.08:00:09.49#ibcon#*before return 0, iclass 38, count 0 2006.225.08:00:09.49#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:00:09.49#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:00:09.49#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.08:00:09.49#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.08:00:09.49$vc4f8/valo=6,772.99 2006.225.08:00:09.49#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.08:00:09.49#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.08:00:09.49#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:09.49#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:00:09.49#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:00:09.49#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:00:09.49#ibcon#enter wrdev, iclass 40, count 0 2006.225.08:00:09.49#ibcon#first serial, iclass 40, count 0 2006.225.08:00:09.49#ibcon#enter sib2, iclass 40, count 0 2006.225.08:00:09.49#ibcon#flushed, iclass 40, count 0 2006.225.08:00:09.49#ibcon#about to write, iclass 40, count 0 2006.225.08:00:09.49#ibcon#wrote, iclass 40, count 0 2006.225.08:00:09.49#ibcon#about to read 3, iclass 40, count 0 2006.225.08:00:09.51#ibcon#read 3, iclass 40, count 0 2006.225.08:00:09.51#ibcon#about to read 4, iclass 40, count 0 2006.225.08:00:09.51#ibcon#read 4, iclass 40, count 0 2006.225.08:00:09.51#ibcon#about to read 5, iclass 40, count 0 2006.225.08:00:09.51#ibcon#read 5, iclass 40, count 0 2006.225.08:00:09.51#ibcon#about to read 6, iclass 40, count 0 2006.225.08:00:09.51#ibcon#read 6, iclass 40, count 0 2006.225.08:00:09.51#ibcon#end of sib2, iclass 40, count 0 2006.225.08:00:09.51#ibcon#*mode == 0, iclass 40, count 0 2006.225.08:00:09.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.08:00:09.51#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:00:09.51#ibcon#*before write, iclass 40, count 0 2006.225.08:00:09.51#ibcon#enter sib2, iclass 40, count 0 2006.225.08:00:09.51#ibcon#flushed, iclass 40, count 0 2006.225.08:00:09.51#ibcon#about to write, iclass 40, count 0 2006.225.08:00:09.51#ibcon#wrote, iclass 40, count 0 2006.225.08:00:09.51#ibcon#about to read 3, iclass 40, count 0 2006.225.08:00:09.56#ibcon#read 3, iclass 40, count 0 2006.225.08:00:09.56#ibcon#about to read 4, iclass 40, count 0 2006.225.08:00:09.56#ibcon#read 4, iclass 40, count 0 2006.225.08:00:09.56#ibcon#about to read 5, iclass 40, count 0 2006.225.08:00:09.56#ibcon#read 5, iclass 40, count 0 2006.225.08:00:09.56#ibcon#about to read 6, iclass 40, count 0 2006.225.08:00:09.56#ibcon#read 6, iclass 40, count 0 2006.225.08:00:09.56#ibcon#end of sib2, iclass 40, count 0 2006.225.08:00:09.56#ibcon#*after write, iclass 40, count 0 2006.225.08:00:09.56#ibcon#*before return 0, iclass 40, count 0 2006.225.08:00:09.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:00:09.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:00:09.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.08:00:09.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.08:00:09.56$vc4f8/va=6,6 2006.225.08:00:09.56#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.08:00:09.56#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.08:00:09.56#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:09.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:00:09.61#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:00:09.61#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:00:09.61#ibcon#enter wrdev, iclass 4, count 2 2006.225.08:00:09.61#ibcon#first serial, iclass 4, count 2 2006.225.08:00:09.61#ibcon#enter sib2, iclass 4, count 2 2006.225.08:00:09.61#ibcon#flushed, iclass 4, count 2 2006.225.08:00:09.61#ibcon#about to write, iclass 4, count 2 2006.225.08:00:09.61#ibcon#wrote, iclass 4, count 2 2006.225.08:00:09.61#ibcon#about to read 3, iclass 4, count 2 2006.225.08:00:09.63#ibcon#read 3, iclass 4, count 2 2006.225.08:00:09.63#ibcon#about to read 4, iclass 4, count 2 2006.225.08:00:09.63#ibcon#read 4, iclass 4, count 2 2006.225.08:00:09.63#ibcon#about to read 5, iclass 4, count 2 2006.225.08:00:09.63#ibcon#read 5, iclass 4, count 2 2006.225.08:00:09.63#ibcon#about to read 6, iclass 4, count 2 2006.225.08:00:09.63#ibcon#read 6, iclass 4, count 2 2006.225.08:00:09.63#ibcon#end of sib2, iclass 4, count 2 2006.225.08:00:09.63#ibcon#*mode == 0, iclass 4, count 2 2006.225.08:00:09.63#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.08:00:09.63#ibcon#[25=AT06-06\r\n] 2006.225.08:00:09.63#ibcon#*before write, iclass 4, count 2 2006.225.08:00:09.63#ibcon#enter sib2, iclass 4, count 2 2006.225.08:00:09.63#ibcon#flushed, iclass 4, count 2 2006.225.08:00:09.63#ibcon#about to write, iclass 4, count 2 2006.225.08:00:09.63#ibcon#wrote, iclass 4, count 2 2006.225.08:00:09.63#ibcon#about to read 3, iclass 4, count 2 2006.225.08:00:09.66#ibcon#read 3, iclass 4, count 2 2006.225.08:00:09.66#ibcon#about to read 4, iclass 4, count 2 2006.225.08:00:09.66#ibcon#read 4, iclass 4, count 2 2006.225.08:00:09.66#ibcon#about to read 5, iclass 4, count 2 2006.225.08:00:09.66#ibcon#read 5, iclass 4, count 2 2006.225.08:00:09.66#ibcon#about to read 6, iclass 4, count 2 2006.225.08:00:09.66#ibcon#read 6, iclass 4, count 2 2006.225.08:00:09.66#ibcon#end of sib2, iclass 4, count 2 2006.225.08:00:09.66#ibcon#*after write, iclass 4, count 2 2006.225.08:00:09.66#ibcon#*before return 0, iclass 4, count 2 2006.225.08:00:09.66#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:00:09.66#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:00:09.66#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.08:00:09.66#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:09.66#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:00:09.78#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:00:09.78#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:00:09.78#ibcon#enter wrdev, iclass 4, count 0 2006.225.08:00:09.78#ibcon#first serial, iclass 4, count 0 2006.225.08:00:09.78#ibcon#enter sib2, iclass 4, count 0 2006.225.08:00:09.78#ibcon#flushed, iclass 4, count 0 2006.225.08:00:09.78#ibcon#about to write, iclass 4, count 0 2006.225.08:00:09.78#ibcon#wrote, iclass 4, count 0 2006.225.08:00:09.78#ibcon#about to read 3, iclass 4, count 0 2006.225.08:00:09.80#ibcon#read 3, iclass 4, count 0 2006.225.08:00:09.80#ibcon#about to read 4, iclass 4, count 0 2006.225.08:00:09.80#ibcon#read 4, iclass 4, count 0 2006.225.08:00:09.80#ibcon#about to read 5, iclass 4, count 0 2006.225.08:00:09.80#ibcon#read 5, iclass 4, count 0 2006.225.08:00:09.80#ibcon#about to read 6, iclass 4, count 0 2006.225.08:00:09.80#ibcon#read 6, iclass 4, count 0 2006.225.08:00:09.80#ibcon#end of sib2, iclass 4, count 0 2006.225.08:00:09.80#ibcon#*mode == 0, iclass 4, count 0 2006.225.08:00:09.80#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.08:00:09.80#ibcon#[25=USB\r\n] 2006.225.08:00:09.80#ibcon#*before write, iclass 4, count 0 2006.225.08:00:09.80#ibcon#enter sib2, iclass 4, count 0 2006.225.08:00:09.80#ibcon#flushed, iclass 4, count 0 2006.225.08:00:09.80#ibcon#about to write, iclass 4, count 0 2006.225.08:00:09.80#ibcon#wrote, iclass 4, count 0 2006.225.08:00:09.80#ibcon#about to read 3, iclass 4, count 0 2006.225.08:00:09.83#ibcon#read 3, iclass 4, count 0 2006.225.08:00:09.83#ibcon#about to read 4, iclass 4, count 0 2006.225.08:00:09.83#ibcon#read 4, iclass 4, count 0 2006.225.08:00:09.83#ibcon#about to read 5, iclass 4, count 0 2006.225.08:00:09.83#ibcon#read 5, iclass 4, count 0 2006.225.08:00:09.83#ibcon#about to read 6, iclass 4, count 0 2006.225.08:00:09.83#ibcon#read 6, iclass 4, count 0 2006.225.08:00:09.83#ibcon#end of sib2, iclass 4, count 0 2006.225.08:00:09.83#ibcon#*after write, iclass 4, count 0 2006.225.08:00:09.83#ibcon#*before return 0, iclass 4, count 0 2006.225.08:00:09.83#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:00:09.83#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:00:09.83#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.08:00:09.83#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.08:00:09.83$vc4f8/valo=7,832.99 2006.225.08:00:09.83#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.08:00:09.83#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.08:00:09.83#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:09.83#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:00:09.83#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:00:09.83#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:00:09.83#ibcon#enter wrdev, iclass 6, count 0 2006.225.08:00:09.83#ibcon#first serial, iclass 6, count 0 2006.225.08:00:09.83#ibcon#enter sib2, iclass 6, count 0 2006.225.08:00:09.83#ibcon#flushed, iclass 6, count 0 2006.225.08:00:09.83#ibcon#about to write, iclass 6, count 0 2006.225.08:00:09.83#ibcon#wrote, iclass 6, count 0 2006.225.08:00:09.83#ibcon#about to read 3, iclass 6, count 0 2006.225.08:00:09.85#ibcon#read 3, iclass 6, count 0 2006.225.08:00:09.85#ibcon#about to read 4, iclass 6, count 0 2006.225.08:00:09.85#ibcon#read 4, iclass 6, count 0 2006.225.08:00:09.85#ibcon#about to read 5, iclass 6, count 0 2006.225.08:00:09.85#ibcon#read 5, iclass 6, count 0 2006.225.08:00:09.85#ibcon#about to read 6, iclass 6, count 0 2006.225.08:00:09.85#ibcon#read 6, iclass 6, count 0 2006.225.08:00:09.85#ibcon#end of sib2, iclass 6, count 0 2006.225.08:00:09.85#ibcon#*mode == 0, iclass 6, count 0 2006.225.08:00:09.85#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.08:00:09.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:00:09.85#ibcon#*before write, iclass 6, count 0 2006.225.08:00:09.85#ibcon#enter sib2, iclass 6, count 0 2006.225.08:00:09.85#ibcon#flushed, iclass 6, count 0 2006.225.08:00:09.85#ibcon#about to write, iclass 6, count 0 2006.225.08:00:09.85#ibcon#wrote, iclass 6, count 0 2006.225.08:00:09.85#ibcon#about to read 3, iclass 6, count 0 2006.225.08:00:09.89#ibcon#read 3, iclass 6, count 0 2006.225.08:00:09.89#ibcon#about to read 4, iclass 6, count 0 2006.225.08:00:09.89#ibcon#read 4, iclass 6, count 0 2006.225.08:00:09.89#ibcon#about to read 5, iclass 6, count 0 2006.225.08:00:09.89#ibcon#read 5, iclass 6, count 0 2006.225.08:00:09.89#ibcon#about to read 6, iclass 6, count 0 2006.225.08:00:09.89#ibcon#read 6, iclass 6, count 0 2006.225.08:00:09.89#ibcon#end of sib2, iclass 6, count 0 2006.225.08:00:09.89#ibcon#*after write, iclass 6, count 0 2006.225.08:00:09.89#ibcon#*before return 0, iclass 6, count 0 2006.225.08:00:09.89#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:00:09.89#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:00:09.89#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.08:00:09.89#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.08:00:09.89$vc4f8/va=7,6 2006.225.08:00:09.89#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.225.08:00:09.89#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.225.08:00:09.89#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:09.89#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:00:09.95#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:00:09.95#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:00:09.95#ibcon#enter wrdev, iclass 10, count 2 2006.225.08:00:09.95#ibcon#first serial, iclass 10, count 2 2006.225.08:00:09.95#ibcon#enter sib2, iclass 10, count 2 2006.225.08:00:09.95#ibcon#flushed, iclass 10, count 2 2006.225.08:00:09.95#ibcon#about to write, iclass 10, count 2 2006.225.08:00:09.95#ibcon#wrote, iclass 10, count 2 2006.225.08:00:09.95#ibcon#about to read 3, iclass 10, count 2 2006.225.08:00:09.97#ibcon#read 3, iclass 10, count 2 2006.225.08:00:09.97#ibcon#about to read 4, iclass 10, count 2 2006.225.08:00:09.97#ibcon#read 4, iclass 10, count 2 2006.225.08:00:09.97#ibcon#about to read 5, iclass 10, count 2 2006.225.08:00:09.97#ibcon#read 5, iclass 10, count 2 2006.225.08:00:09.97#ibcon#about to read 6, iclass 10, count 2 2006.225.08:00:09.97#ibcon#read 6, iclass 10, count 2 2006.225.08:00:09.97#ibcon#end of sib2, iclass 10, count 2 2006.225.08:00:09.97#ibcon#*mode == 0, iclass 10, count 2 2006.225.08:00:09.97#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.225.08:00:09.97#ibcon#[25=AT07-06\r\n] 2006.225.08:00:09.97#ibcon#*before write, iclass 10, count 2 2006.225.08:00:09.97#ibcon#enter sib2, iclass 10, count 2 2006.225.08:00:09.97#ibcon#flushed, iclass 10, count 2 2006.225.08:00:09.97#ibcon#about to write, iclass 10, count 2 2006.225.08:00:09.97#ibcon#wrote, iclass 10, count 2 2006.225.08:00:09.97#ibcon#about to read 3, iclass 10, count 2 2006.225.08:00:10.00#ibcon#read 3, iclass 10, count 2 2006.225.08:00:10.00#ibcon#about to read 4, iclass 10, count 2 2006.225.08:00:10.00#ibcon#read 4, iclass 10, count 2 2006.225.08:00:10.00#ibcon#about to read 5, iclass 10, count 2 2006.225.08:00:10.00#ibcon#read 5, iclass 10, count 2 2006.225.08:00:10.00#ibcon#about to read 6, iclass 10, count 2 2006.225.08:00:10.00#ibcon#read 6, iclass 10, count 2 2006.225.08:00:10.00#ibcon#end of sib2, iclass 10, count 2 2006.225.08:00:10.00#ibcon#*after write, iclass 10, count 2 2006.225.08:00:10.00#ibcon#*before return 0, iclass 10, count 2 2006.225.08:00:10.00#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:00:10.00#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:00:10.00#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.225.08:00:10.00#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:10.00#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:00:10.12#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:00:10.12#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:00:10.12#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:00:10.12#ibcon#first serial, iclass 10, count 0 2006.225.08:00:10.12#ibcon#enter sib2, iclass 10, count 0 2006.225.08:00:10.12#ibcon#flushed, iclass 10, count 0 2006.225.08:00:10.12#ibcon#about to write, iclass 10, count 0 2006.225.08:00:10.12#ibcon#wrote, iclass 10, count 0 2006.225.08:00:10.12#ibcon#about to read 3, iclass 10, count 0 2006.225.08:00:10.14#ibcon#read 3, iclass 10, count 0 2006.225.08:00:10.14#ibcon#about to read 4, iclass 10, count 0 2006.225.08:00:10.14#ibcon#read 4, iclass 10, count 0 2006.225.08:00:10.14#ibcon#about to read 5, iclass 10, count 0 2006.225.08:00:10.14#ibcon#read 5, iclass 10, count 0 2006.225.08:00:10.14#ibcon#about to read 6, iclass 10, count 0 2006.225.08:00:10.14#ibcon#read 6, iclass 10, count 0 2006.225.08:00:10.14#ibcon#end of sib2, iclass 10, count 0 2006.225.08:00:10.14#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:00:10.14#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:00:10.14#ibcon#[25=USB\r\n] 2006.225.08:00:10.14#ibcon#*before write, iclass 10, count 0 2006.225.08:00:10.14#ibcon#enter sib2, iclass 10, count 0 2006.225.08:00:10.14#ibcon#flushed, iclass 10, count 0 2006.225.08:00:10.14#ibcon#about to write, iclass 10, count 0 2006.225.08:00:10.14#ibcon#wrote, iclass 10, count 0 2006.225.08:00:10.14#ibcon#about to read 3, iclass 10, count 0 2006.225.08:00:10.17#ibcon#read 3, iclass 10, count 0 2006.225.08:00:10.17#ibcon#about to read 4, iclass 10, count 0 2006.225.08:00:10.17#ibcon#read 4, iclass 10, count 0 2006.225.08:00:10.17#ibcon#about to read 5, iclass 10, count 0 2006.225.08:00:10.17#ibcon#read 5, iclass 10, count 0 2006.225.08:00:10.17#ibcon#about to read 6, iclass 10, count 0 2006.225.08:00:10.17#ibcon#read 6, iclass 10, count 0 2006.225.08:00:10.17#ibcon#end of sib2, iclass 10, count 0 2006.225.08:00:10.17#ibcon#*after write, iclass 10, count 0 2006.225.08:00:10.17#ibcon#*before return 0, iclass 10, count 0 2006.225.08:00:10.17#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:00:10.17#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:00:10.17#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:00:10.17#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:00:10.17$vc4f8/valo=8,852.99 2006.225.08:00:10.17#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.08:00:10.17#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.08:00:10.17#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:10.17#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:00:10.17#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:00:10.17#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:00:10.17#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:00:10.17#ibcon#first serial, iclass 12, count 0 2006.225.08:00:10.17#ibcon#enter sib2, iclass 12, count 0 2006.225.08:00:10.17#ibcon#flushed, iclass 12, count 0 2006.225.08:00:10.17#ibcon#about to write, iclass 12, count 0 2006.225.08:00:10.17#ibcon#wrote, iclass 12, count 0 2006.225.08:00:10.17#ibcon#about to read 3, iclass 12, count 0 2006.225.08:00:10.19#ibcon#read 3, iclass 12, count 0 2006.225.08:00:10.19#ibcon#about to read 4, iclass 12, count 0 2006.225.08:00:10.19#ibcon#read 4, iclass 12, count 0 2006.225.08:00:10.19#ibcon#about to read 5, iclass 12, count 0 2006.225.08:00:10.19#ibcon#read 5, iclass 12, count 0 2006.225.08:00:10.19#ibcon#about to read 6, iclass 12, count 0 2006.225.08:00:10.19#ibcon#read 6, iclass 12, count 0 2006.225.08:00:10.19#ibcon#end of sib2, iclass 12, count 0 2006.225.08:00:10.19#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:00:10.19#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:00:10.19#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:00:10.19#ibcon#*before write, iclass 12, count 0 2006.225.08:00:10.19#ibcon#enter sib2, iclass 12, count 0 2006.225.08:00:10.19#ibcon#flushed, iclass 12, count 0 2006.225.08:00:10.19#ibcon#about to write, iclass 12, count 0 2006.225.08:00:10.19#ibcon#wrote, iclass 12, count 0 2006.225.08:00:10.19#ibcon#about to read 3, iclass 12, count 0 2006.225.08:00:10.23#ibcon#read 3, iclass 12, count 0 2006.225.08:00:10.23#ibcon#about to read 4, iclass 12, count 0 2006.225.08:00:10.23#ibcon#read 4, iclass 12, count 0 2006.225.08:00:10.23#ibcon#about to read 5, iclass 12, count 0 2006.225.08:00:10.23#ibcon#read 5, iclass 12, count 0 2006.225.08:00:10.23#ibcon#about to read 6, iclass 12, count 0 2006.225.08:00:10.23#ibcon#read 6, iclass 12, count 0 2006.225.08:00:10.23#ibcon#end of sib2, iclass 12, count 0 2006.225.08:00:10.23#ibcon#*after write, iclass 12, count 0 2006.225.08:00:10.23#ibcon#*before return 0, iclass 12, count 0 2006.225.08:00:10.23#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:00:10.23#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:00:10.23#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:00:10.23#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:00:10.23$vc4f8/va=8,7 2006.225.08:00:10.23#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.225.08:00:10.23#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.225.08:00:10.23#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:10.23#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:00:10.29#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:00:10.29#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:00:10.29#ibcon#enter wrdev, iclass 14, count 2 2006.225.08:00:10.29#ibcon#first serial, iclass 14, count 2 2006.225.08:00:10.29#ibcon#enter sib2, iclass 14, count 2 2006.225.08:00:10.29#ibcon#flushed, iclass 14, count 2 2006.225.08:00:10.29#ibcon#about to write, iclass 14, count 2 2006.225.08:00:10.29#ibcon#wrote, iclass 14, count 2 2006.225.08:00:10.29#ibcon#about to read 3, iclass 14, count 2 2006.225.08:00:10.31#ibcon#read 3, iclass 14, count 2 2006.225.08:00:10.31#ibcon#about to read 4, iclass 14, count 2 2006.225.08:00:10.31#ibcon#read 4, iclass 14, count 2 2006.225.08:00:10.31#ibcon#about to read 5, iclass 14, count 2 2006.225.08:00:10.31#ibcon#read 5, iclass 14, count 2 2006.225.08:00:10.31#ibcon#about to read 6, iclass 14, count 2 2006.225.08:00:10.31#ibcon#read 6, iclass 14, count 2 2006.225.08:00:10.31#ibcon#end of sib2, iclass 14, count 2 2006.225.08:00:10.31#ibcon#*mode == 0, iclass 14, count 2 2006.225.08:00:10.31#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.225.08:00:10.31#ibcon#[25=AT08-07\r\n] 2006.225.08:00:10.31#ibcon#*before write, iclass 14, count 2 2006.225.08:00:10.31#ibcon#enter sib2, iclass 14, count 2 2006.225.08:00:10.31#ibcon#flushed, iclass 14, count 2 2006.225.08:00:10.31#ibcon#about to write, iclass 14, count 2 2006.225.08:00:10.31#ibcon#wrote, iclass 14, count 2 2006.225.08:00:10.31#ibcon#about to read 3, iclass 14, count 2 2006.225.08:00:10.34#ibcon#read 3, iclass 14, count 2 2006.225.08:00:10.34#ibcon#about to read 4, iclass 14, count 2 2006.225.08:00:10.34#ibcon#read 4, iclass 14, count 2 2006.225.08:00:10.34#ibcon#about to read 5, iclass 14, count 2 2006.225.08:00:10.34#ibcon#read 5, iclass 14, count 2 2006.225.08:00:10.34#ibcon#about to read 6, iclass 14, count 2 2006.225.08:00:10.34#ibcon#read 6, iclass 14, count 2 2006.225.08:00:10.34#ibcon#end of sib2, iclass 14, count 2 2006.225.08:00:10.34#ibcon#*after write, iclass 14, count 2 2006.225.08:00:10.34#ibcon#*before return 0, iclass 14, count 2 2006.225.08:00:10.34#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:00:10.34#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:00:10.34#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.225.08:00:10.34#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:10.34#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:00:10.46#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:00:10.46#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:00:10.46#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:00:10.46#ibcon#first serial, iclass 14, count 0 2006.225.08:00:10.46#ibcon#enter sib2, iclass 14, count 0 2006.225.08:00:10.46#ibcon#flushed, iclass 14, count 0 2006.225.08:00:10.46#ibcon#about to write, iclass 14, count 0 2006.225.08:00:10.46#ibcon#wrote, iclass 14, count 0 2006.225.08:00:10.46#ibcon#about to read 3, iclass 14, count 0 2006.225.08:00:10.48#ibcon#read 3, iclass 14, count 0 2006.225.08:00:10.48#ibcon#about to read 4, iclass 14, count 0 2006.225.08:00:10.48#ibcon#read 4, iclass 14, count 0 2006.225.08:00:10.48#ibcon#about to read 5, iclass 14, count 0 2006.225.08:00:10.48#ibcon#read 5, iclass 14, count 0 2006.225.08:00:10.48#ibcon#about to read 6, iclass 14, count 0 2006.225.08:00:10.48#ibcon#read 6, iclass 14, count 0 2006.225.08:00:10.48#ibcon#end of sib2, iclass 14, count 0 2006.225.08:00:10.48#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:00:10.48#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:00:10.48#ibcon#[25=USB\r\n] 2006.225.08:00:10.48#ibcon#*before write, iclass 14, count 0 2006.225.08:00:10.48#ibcon#enter sib2, iclass 14, count 0 2006.225.08:00:10.48#ibcon#flushed, iclass 14, count 0 2006.225.08:00:10.48#ibcon#about to write, iclass 14, count 0 2006.225.08:00:10.48#ibcon#wrote, iclass 14, count 0 2006.225.08:00:10.48#ibcon#about to read 3, iclass 14, count 0 2006.225.08:00:10.51#ibcon#read 3, iclass 14, count 0 2006.225.08:00:10.51#ibcon#about to read 4, iclass 14, count 0 2006.225.08:00:10.51#ibcon#read 4, iclass 14, count 0 2006.225.08:00:10.51#ibcon#about to read 5, iclass 14, count 0 2006.225.08:00:10.51#ibcon#read 5, iclass 14, count 0 2006.225.08:00:10.51#ibcon#about to read 6, iclass 14, count 0 2006.225.08:00:10.51#ibcon#read 6, iclass 14, count 0 2006.225.08:00:10.51#ibcon#end of sib2, iclass 14, count 0 2006.225.08:00:10.51#ibcon#*after write, iclass 14, count 0 2006.225.08:00:10.51#ibcon#*before return 0, iclass 14, count 0 2006.225.08:00:10.51#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:00:10.51#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:00:10.51#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:00:10.51#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:00:10.51$vc4f8/vblo=1,632.99 2006.225.08:00:10.51#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.08:00:10.51#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.08:00:10.51#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:10.51#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:00:10.51#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:00:10.51#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:00:10.51#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:00:10.51#ibcon#first serial, iclass 16, count 0 2006.225.08:00:10.51#ibcon#enter sib2, iclass 16, count 0 2006.225.08:00:10.51#ibcon#flushed, iclass 16, count 0 2006.225.08:00:10.51#ibcon#about to write, iclass 16, count 0 2006.225.08:00:10.51#ibcon#wrote, iclass 16, count 0 2006.225.08:00:10.51#ibcon#about to read 3, iclass 16, count 0 2006.225.08:00:10.53#ibcon#read 3, iclass 16, count 0 2006.225.08:00:10.53#ibcon#about to read 4, iclass 16, count 0 2006.225.08:00:10.53#ibcon#read 4, iclass 16, count 0 2006.225.08:00:10.53#ibcon#about to read 5, iclass 16, count 0 2006.225.08:00:10.53#ibcon#read 5, iclass 16, count 0 2006.225.08:00:10.53#ibcon#about to read 6, iclass 16, count 0 2006.225.08:00:10.53#ibcon#read 6, iclass 16, count 0 2006.225.08:00:10.53#ibcon#end of sib2, iclass 16, count 0 2006.225.08:00:10.53#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:00:10.53#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:00:10.53#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:00:10.53#ibcon#*before write, iclass 16, count 0 2006.225.08:00:10.53#ibcon#enter sib2, iclass 16, count 0 2006.225.08:00:10.53#ibcon#flushed, iclass 16, count 0 2006.225.08:00:10.53#ibcon#about to write, iclass 16, count 0 2006.225.08:00:10.53#ibcon#wrote, iclass 16, count 0 2006.225.08:00:10.53#ibcon#about to read 3, iclass 16, count 0 2006.225.08:00:10.58#ibcon#read 3, iclass 16, count 0 2006.225.08:00:10.58#ibcon#about to read 4, iclass 16, count 0 2006.225.08:00:10.58#ibcon#read 4, iclass 16, count 0 2006.225.08:00:10.58#ibcon#about to read 5, iclass 16, count 0 2006.225.08:00:10.58#ibcon#read 5, iclass 16, count 0 2006.225.08:00:10.58#ibcon#about to read 6, iclass 16, count 0 2006.225.08:00:10.58#ibcon#read 6, iclass 16, count 0 2006.225.08:00:10.58#ibcon#end of sib2, iclass 16, count 0 2006.225.08:00:10.58#ibcon#*after write, iclass 16, count 0 2006.225.08:00:10.58#ibcon#*before return 0, iclass 16, count 0 2006.225.08:00:10.58#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:00:10.58#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:00:10.58#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:00:10.58#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:00:10.58$vc4f8/vb=1,4 2006.225.08:00:10.58#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.225.08:00:10.58#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.225.08:00:10.58#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:10.58#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:00:10.58#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:00:10.58#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:00:10.58#ibcon#enter wrdev, iclass 18, count 2 2006.225.08:00:10.58#ibcon#first serial, iclass 18, count 2 2006.225.08:00:10.58#ibcon#enter sib2, iclass 18, count 2 2006.225.08:00:10.58#ibcon#flushed, iclass 18, count 2 2006.225.08:00:10.58#ibcon#about to write, iclass 18, count 2 2006.225.08:00:10.58#ibcon#wrote, iclass 18, count 2 2006.225.08:00:10.58#ibcon#about to read 3, iclass 18, count 2 2006.225.08:00:10.60#ibcon#read 3, iclass 18, count 2 2006.225.08:00:10.60#ibcon#about to read 4, iclass 18, count 2 2006.225.08:00:10.60#ibcon#read 4, iclass 18, count 2 2006.225.08:00:10.60#ibcon#about to read 5, iclass 18, count 2 2006.225.08:00:10.60#ibcon#read 5, iclass 18, count 2 2006.225.08:00:10.60#ibcon#about to read 6, iclass 18, count 2 2006.225.08:00:10.60#ibcon#read 6, iclass 18, count 2 2006.225.08:00:10.60#ibcon#end of sib2, iclass 18, count 2 2006.225.08:00:10.60#ibcon#*mode == 0, iclass 18, count 2 2006.225.08:00:10.60#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.225.08:00:10.60#ibcon#[27=AT01-04\r\n] 2006.225.08:00:10.60#ibcon#*before write, iclass 18, count 2 2006.225.08:00:10.60#ibcon#enter sib2, iclass 18, count 2 2006.225.08:00:10.60#ibcon#flushed, iclass 18, count 2 2006.225.08:00:10.60#ibcon#about to write, iclass 18, count 2 2006.225.08:00:10.60#ibcon#wrote, iclass 18, count 2 2006.225.08:00:10.60#ibcon#about to read 3, iclass 18, count 2 2006.225.08:00:10.63#ibcon#read 3, iclass 18, count 2 2006.225.08:00:10.63#ibcon#about to read 4, iclass 18, count 2 2006.225.08:00:10.63#ibcon#read 4, iclass 18, count 2 2006.225.08:00:10.63#ibcon#about to read 5, iclass 18, count 2 2006.225.08:00:10.63#ibcon#read 5, iclass 18, count 2 2006.225.08:00:10.63#ibcon#about to read 6, iclass 18, count 2 2006.225.08:00:10.63#ibcon#read 6, iclass 18, count 2 2006.225.08:00:10.63#ibcon#end of sib2, iclass 18, count 2 2006.225.08:00:10.63#ibcon#*after write, iclass 18, count 2 2006.225.08:00:10.63#ibcon#*before return 0, iclass 18, count 2 2006.225.08:00:10.63#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:00:10.63#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:00:10.63#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.225.08:00:10.63#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:10.63#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:00:10.75#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:00:10.75#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:00:10.75#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:00:10.75#ibcon#first serial, iclass 18, count 0 2006.225.08:00:10.75#ibcon#enter sib2, iclass 18, count 0 2006.225.08:00:10.75#ibcon#flushed, iclass 18, count 0 2006.225.08:00:10.75#ibcon#about to write, iclass 18, count 0 2006.225.08:00:10.75#ibcon#wrote, iclass 18, count 0 2006.225.08:00:10.75#ibcon#about to read 3, iclass 18, count 0 2006.225.08:00:10.77#ibcon#read 3, iclass 18, count 0 2006.225.08:00:10.77#ibcon#about to read 4, iclass 18, count 0 2006.225.08:00:10.77#ibcon#read 4, iclass 18, count 0 2006.225.08:00:10.77#ibcon#about to read 5, iclass 18, count 0 2006.225.08:00:10.77#ibcon#read 5, iclass 18, count 0 2006.225.08:00:10.77#ibcon#about to read 6, iclass 18, count 0 2006.225.08:00:10.77#ibcon#read 6, iclass 18, count 0 2006.225.08:00:10.77#ibcon#end of sib2, iclass 18, count 0 2006.225.08:00:10.77#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:00:10.77#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:00:10.77#ibcon#[27=USB\r\n] 2006.225.08:00:10.77#ibcon#*before write, iclass 18, count 0 2006.225.08:00:10.77#ibcon#enter sib2, iclass 18, count 0 2006.225.08:00:10.77#ibcon#flushed, iclass 18, count 0 2006.225.08:00:10.77#ibcon#about to write, iclass 18, count 0 2006.225.08:00:10.77#ibcon#wrote, iclass 18, count 0 2006.225.08:00:10.77#ibcon#about to read 3, iclass 18, count 0 2006.225.08:00:10.80#ibcon#read 3, iclass 18, count 0 2006.225.08:00:10.80#ibcon#about to read 4, iclass 18, count 0 2006.225.08:00:10.80#ibcon#read 4, iclass 18, count 0 2006.225.08:00:10.80#ibcon#about to read 5, iclass 18, count 0 2006.225.08:00:10.80#ibcon#read 5, iclass 18, count 0 2006.225.08:00:10.80#ibcon#about to read 6, iclass 18, count 0 2006.225.08:00:10.80#ibcon#read 6, iclass 18, count 0 2006.225.08:00:10.80#ibcon#end of sib2, iclass 18, count 0 2006.225.08:00:10.80#ibcon#*after write, iclass 18, count 0 2006.225.08:00:10.80#ibcon#*before return 0, iclass 18, count 0 2006.225.08:00:10.80#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:00:10.80#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:00:10.80#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:00:10.80#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:00:10.80$vc4f8/vblo=2,640.99 2006.225.08:00:10.80#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.225.08:00:10.80#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.225.08:00:10.80#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:10.80#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:00:10.80#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:00:10.80#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:00:10.80#ibcon#enter wrdev, iclass 20, count 0 2006.225.08:00:10.80#ibcon#first serial, iclass 20, count 0 2006.225.08:00:10.80#ibcon#enter sib2, iclass 20, count 0 2006.225.08:00:10.80#ibcon#flushed, iclass 20, count 0 2006.225.08:00:10.80#ibcon#about to write, iclass 20, count 0 2006.225.08:00:10.80#ibcon#wrote, iclass 20, count 0 2006.225.08:00:10.80#ibcon#about to read 3, iclass 20, count 0 2006.225.08:00:10.82#ibcon#read 3, iclass 20, count 0 2006.225.08:00:10.82#ibcon#about to read 4, iclass 20, count 0 2006.225.08:00:10.82#ibcon#read 4, iclass 20, count 0 2006.225.08:00:10.82#ibcon#about to read 5, iclass 20, count 0 2006.225.08:00:10.82#ibcon#read 5, iclass 20, count 0 2006.225.08:00:10.82#ibcon#about to read 6, iclass 20, count 0 2006.225.08:00:10.82#ibcon#read 6, iclass 20, count 0 2006.225.08:00:10.82#ibcon#end of sib2, iclass 20, count 0 2006.225.08:00:10.82#ibcon#*mode == 0, iclass 20, count 0 2006.225.08:00:10.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.08:00:10.82#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:00:10.82#ibcon#*before write, iclass 20, count 0 2006.225.08:00:10.82#ibcon#enter sib2, iclass 20, count 0 2006.225.08:00:10.82#ibcon#flushed, iclass 20, count 0 2006.225.08:00:10.82#ibcon#about to write, iclass 20, count 0 2006.225.08:00:10.82#ibcon#wrote, iclass 20, count 0 2006.225.08:00:10.82#ibcon#about to read 3, iclass 20, count 0 2006.225.08:00:10.86#ibcon#read 3, iclass 20, count 0 2006.225.08:00:10.86#ibcon#about to read 4, iclass 20, count 0 2006.225.08:00:10.86#ibcon#read 4, iclass 20, count 0 2006.225.08:00:10.86#ibcon#about to read 5, iclass 20, count 0 2006.225.08:00:10.86#ibcon#read 5, iclass 20, count 0 2006.225.08:00:10.86#ibcon#about to read 6, iclass 20, count 0 2006.225.08:00:10.86#ibcon#read 6, iclass 20, count 0 2006.225.08:00:10.86#ibcon#end of sib2, iclass 20, count 0 2006.225.08:00:10.86#ibcon#*after write, iclass 20, count 0 2006.225.08:00:10.86#ibcon#*before return 0, iclass 20, count 0 2006.225.08:00:10.86#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:00:10.86#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:00:10.86#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.08:00:10.86#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.08:00:10.86$vc4f8/vb=2,4 2006.225.08:00:10.86#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.225.08:00:10.86#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.225.08:00:10.86#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:10.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:00:10.92#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:00:10.92#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:00:10.92#ibcon#enter wrdev, iclass 22, count 2 2006.225.08:00:10.92#ibcon#first serial, iclass 22, count 2 2006.225.08:00:10.92#ibcon#enter sib2, iclass 22, count 2 2006.225.08:00:10.92#ibcon#flushed, iclass 22, count 2 2006.225.08:00:10.92#ibcon#about to write, iclass 22, count 2 2006.225.08:00:10.92#ibcon#wrote, iclass 22, count 2 2006.225.08:00:10.92#ibcon#about to read 3, iclass 22, count 2 2006.225.08:00:10.94#ibcon#read 3, iclass 22, count 2 2006.225.08:00:10.94#ibcon#about to read 4, iclass 22, count 2 2006.225.08:00:10.94#ibcon#read 4, iclass 22, count 2 2006.225.08:00:10.94#ibcon#about to read 5, iclass 22, count 2 2006.225.08:00:10.94#ibcon#read 5, iclass 22, count 2 2006.225.08:00:10.94#ibcon#about to read 6, iclass 22, count 2 2006.225.08:00:10.94#ibcon#read 6, iclass 22, count 2 2006.225.08:00:10.94#ibcon#end of sib2, iclass 22, count 2 2006.225.08:00:10.94#ibcon#*mode == 0, iclass 22, count 2 2006.225.08:00:10.94#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.225.08:00:10.94#ibcon#[27=AT02-04\r\n] 2006.225.08:00:10.94#ibcon#*before write, iclass 22, count 2 2006.225.08:00:10.94#ibcon#enter sib2, iclass 22, count 2 2006.225.08:00:10.94#ibcon#flushed, iclass 22, count 2 2006.225.08:00:10.94#ibcon#about to write, iclass 22, count 2 2006.225.08:00:10.94#ibcon#wrote, iclass 22, count 2 2006.225.08:00:10.94#ibcon#about to read 3, iclass 22, count 2 2006.225.08:00:10.97#ibcon#read 3, iclass 22, count 2 2006.225.08:00:10.97#ibcon#about to read 4, iclass 22, count 2 2006.225.08:00:10.97#ibcon#read 4, iclass 22, count 2 2006.225.08:00:10.97#ibcon#about to read 5, iclass 22, count 2 2006.225.08:00:10.97#ibcon#read 5, iclass 22, count 2 2006.225.08:00:10.97#ibcon#about to read 6, iclass 22, count 2 2006.225.08:00:10.97#ibcon#read 6, iclass 22, count 2 2006.225.08:00:10.97#ibcon#end of sib2, iclass 22, count 2 2006.225.08:00:10.97#ibcon#*after write, iclass 22, count 2 2006.225.08:00:10.97#ibcon#*before return 0, iclass 22, count 2 2006.225.08:00:10.97#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:00:10.97#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:00:10.97#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.225.08:00:10.97#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:10.97#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:00:11.09#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:00:11.09#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:00:11.09#ibcon#enter wrdev, iclass 22, count 0 2006.225.08:00:11.09#ibcon#first serial, iclass 22, count 0 2006.225.08:00:11.09#ibcon#enter sib2, iclass 22, count 0 2006.225.08:00:11.09#ibcon#flushed, iclass 22, count 0 2006.225.08:00:11.09#ibcon#about to write, iclass 22, count 0 2006.225.08:00:11.09#ibcon#wrote, iclass 22, count 0 2006.225.08:00:11.09#ibcon#about to read 3, iclass 22, count 0 2006.225.08:00:11.11#ibcon#read 3, iclass 22, count 0 2006.225.08:00:11.11#ibcon#about to read 4, iclass 22, count 0 2006.225.08:00:11.11#ibcon#read 4, iclass 22, count 0 2006.225.08:00:11.11#ibcon#about to read 5, iclass 22, count 0 2006.225.08:00:11.11#ibcon#read 5, iclass 22, count 0 2006.225.08:00:11.11#ibcon#about to read 6, iclass 22, count 0 2006.225.08:00:11.11#ibcon#read 6, iclass 22, count 0 2006.225.08:00:11.11#ibcon#end of sib2, iclass 22, count 0 2006.225.08:00:11.11#ibcon#*mode == 0, iclass 22, count 0 2006.225.08:00:11.11#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.08:00:11.11#ibcon#[27=USB\r\n] 2006.225.08:00:11.11#ibcon#*before write, iclass 22, count 0 2006.225.08:00:11.11#ibcon#enter sib2, iclass 22, count 0 2006.225.08:00:11.11#ibcon#flushed, iclass 22, count 0 2006.225.08:00:11.11#ibcon#about to write, iclass 22, count 0 2006.225.08:00:11.11#ibcon#wrote, iclass 22, count 0 2006.225.08:00:11.11#ibcon#about to read 3, iclass 22, count 0 2006.225.08:00:11.14#ibcon#read 3, iclass 22, count 0 2006.225.08:00:11.14#ibcon#about to read 4, iclass 22, count 0 2006.225.08:00:11.14#ibcon#read 4, iclass 22, count 0 2006.225.08:00:11.14#ibcon#about to read 5, iclass 22, count 0 2006.225.08:00:11.14#ibcon#read 5, iclass 22, count 0 2006.225.08:00:11.14#ibcon#about to read 6, iclass 22, count 0 2006.225.08:00:11.14#ibcon#read 6, iclass 22, count 0 2006.225.08:00:11.14#ibcon#end of sib2, iclass 22, count 0 2006.225.08:00:11.14#ibcon#*after write, iclass 22, count 0 2006.225.08:00:11.14#ibcon#*before return 0, iclass 22, count 0 2006.225.08:00:11.14#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:00:11.14#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:00:11.14#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.08:00:11.14#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.08:00:11.14$vc4f8/vblo=3,656.99 2006.225.08:00:11.14#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.08:00:11.14#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.08:00:11.14#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:11.14#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:00:11.14#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:00:11.14#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:00:11.14#ibcon#enter wrdev, iclass 24, count 0 2006.225.08:00:11.14#ibcon#first serial, iclass 24, count 0 2006.225.08:00:11.14#ibcon#enter sib2, iclass 24, count 0 2006.225.08:00:11.14#ibcon#flushed, iclass 24, count 0 2006.225.08:00:11.14#ibcon#about to write, iclass 24, count 0 2006.225.08:00:11.14#ibcon#wrote, iclass 24, count 0 2006.225.08:00:11.14#ibcon#about to read 3, iclass 24, count 0 2006.225.08:00:11.16#ibcon#read 3, iclass 24, count 0 2006.225.08:00:11.16#ibcon#about to read 4, iclass 24, count 0 2006.225.08:00:11.16#ibcon#read 4, iclass 24, count 0 2006.225.08:00:11.16#ibcon#about to read 5, iclass 24, count 0 2006.225.08:00:11.16#ibcon#read 5, iclass 24, count 0 2006.225.08:00:11.16#ibcon#about to read 6, iclass 24, count 0 2006.225.08:00:11.16#ibcon#read 6, iclass 24, count 0 2006.225.08:00:11.16#ibcon#end of sib2, iclass 24, count 0 2006.225.08:00:11.16#ibcon#*mode == 0, iclass 24, count 0 2006.225.08:00:11.16#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.08:00:11.16#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:00:11.16#ibcon#*before write, iclass 24, count 0 2006.225.08:00:11.16#ibcon#enter sib2, iclass 24, count 0 2006.225.08:00:11.16#ibcon#flushed, iclass 24, count 0 2006.225.08:00:11.16#ibcon#about to write, iclass 24, count 0 2006.225.08:00:11.16#ibcon#wrote, iclass 24, count 0 2006.225.08:00:11.16#ibcon#about to read 3, iclass 24, count 0 2006.225.08:00:11.20#ibcon#read 3, iclass 24, count 0 2006.225.08:00:11.20#ibcon#about to read 4, iclass 24, count 0 2006.225.08:00:11.20#ibcon#read 4, iclass 24, count 0 2006.225.08:00:11.20#ibcon#about to read 5, iclass 24, count 0 2006.225.08:00:11.20#ibcon#read 5, iclass 24, count 0 2006.225.08:00:11.20#ibcon#about to read 6, iclass 24, count 0 2006.225.08:00:11.20#ibcon#read 6, iclass 24, count 0 2006.225.08:00:11.20#ibcon#end of sib2, iclass 24, count 0 2006.225.08:00:11.20#ibcon#*after write, iclass 24, count 0 2006.225.08:00:11.20#ibcon#*before return 0, iclass 24, count 0 2006.225.08:00:11.20#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:00:11.20#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:00:11.20#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.08:00:11.20#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.08:00:11.20$vc4f8/vb=3,4 2006.225.08:00:11.20#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.225.08:00:11.20#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.225.08:00:11.20#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:11.20#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.08:00:11.26#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.08:00:11.26#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.08:00:11.26#ibcon#enter wrdev, iclass 26, count 2 2006.225.08:00:11.26#ibcon#first serial, iclass 26, count 2 2006.225.08:00:11.26#ibcon#enter sib2, iclass 26, count 2 2006.225.08:00:11.26#ibcon#flushed, iclass 26, count 2 2006.225.08:00:11.26#ibcon#about to write, iclass 26, count 2 2006.225.08:00:11.26#ibcon#wrote, iclass 26, count 2 2006.225.08:00:11.26#ibcon#about to read 3, iclass 26, count 2 2006.225.08:00:11.28#ibcon#read 3, iclass 26, count 2 2006.225.08:00:11.28#ibcon#about to read 4, iclass 26, count 2 2006.225.08:00:11.28#ibcon#read 4, iclass 26, count 2 2006.225.08:00:11.28#ibcon#about to read 5, iclass 26, count 2 2006.225.08:00:11.28#ibcon#read 5, iclass 26, count 2 2006.225.08:00:11.28#ibcon#about to read 6, iclass 26, count 2 2006.225.08:00:11.28#ibcon#read 6, iclass 26, count 2 2006.225.08:00:11.28#ibcon#end of sib2, iclass 26, count 2 2006.225.08:00:11.28#ibcon#*mode == 0, iclass 26, count 2 2006.225.08:00:11.28#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.225.08:00:11.28#ibcon#[27=AT03-04\r\n] 2006.225.08:00:11.28#ibcon#*before write, iclass 26, count 2 2006.225.08:00:11.28#ibcon#enter sib2, iclass 26, count 2 2006.225.08:00:11.28#ibcon#flushed, iclass 26, count 2 2006.225.08:00:11.28#ibcon#about to write, iclass 26, count 2 2006.225.08:00:11.28#ibcon#wrote, iclass 26, count 2 2006.225.08:00:11.28#ibcon#about to read 3, iclass 26, count 2 2006.225.08:00:11.32#ibcon#read 3, iclass 26, count 2 2006.225.08:00:11.32#ibcon#about to read 4, iclass 26, count 2 2006.225.08:00:11.32#ibcon#read 4, iclass 26, count 2 2006.225.08:00:11.32#ibcon#about to read 5, iclass 26, count 2 2006.225.08:00:11.32#ibcon#read 5, iclass 26, count 2 2006.225.08:00:11.32#ibcon#about to read 6, iclass 26, count 2 2006.225.08:00:11.32#ibcon#read 6, iclass 26, count 2 2006.225.08:00:11.32#ibcon#end of sib2, iclass 26, count 2 2006.225.08:00:11.32#ibcon#*after write, iclass 26, count 2 2006.225.08:00:11.32#ibcon#*before return 0, iclass 26, count 2 2006.225.08:00:11.32#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.08:00:11.32#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.225.08:00:11.32#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.225.08:00:11.32#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:11.32#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.08:00:11.44#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.08:00:11.44#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.08:00:11.44#ibcon#enter wrdev, iclass 26, count 0 2006.225.08:00:11.44#ibcon#first serial, iclass 26, count 0 2006.225.08:00:11.44#ibcon#enter sib2, iclass 26, count 0 2006.225.08:00:11.44#ibcon#flushed, iclass 26, count 0 2006.225.08:00:11.44#ibcon#about to write, iclass 26, count 0 2006.225.08:00:11.44#ibcon#wrote, iclass 26, count 0 2006.225.08:00:11.44#ibcon#about to read 3, iclass 26, count 0 2006.225.08:00:11.46#ibcon#read 3, iclass 26, count 0 2006.225.08:00:11.46#ibcon#about to read 4, iclass 26, count 0 2006.225.08:00:11.46#ibcon#read 4, iclass 26, count 0 2006.225.08:00:11.46#ibcon#about to read 5, iclass 26, count 0 2006.225.08:00:11.46#ibcon#read 5, iclass 26, count 0 2006.225.08:00:11.46#ibcon#about to read 6, iclass 26, count 0 2006.225.08:00:11.46#ibcon#read 6, iclass 26, count 0 2006.225.08:00:11.46#ibcon#end of sib2, iclass 26, count 0 2006.225.08:00:11.46#ibcon#*mode == 0, iclass 26, count 0 2006.225.08:00:11.46#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.08:00:11.46#ibcon#[27=USB\r\n] 2006.225.08:00:11.46#ibcon#*before write, iclass 26, count 0 2006.225.08:00:11.46#ibcon#enter sib2, iclass 26, count 0 2006.225.08:00:11.46#ibcon#flushed, iclass 26, count 0 2006.225.08:00:11.46#ibcon#about to write, iclass 26, count 0 2006.225.08:00:11.46#ibcon#wrote, iclass 26, count 0 2006.225.08:00:11.46#ibcon#about to read 3, iclass 26, count 0 2006.225.08:00:11.49#ibcon#read 3, iclass 26, count 0 2006.225.08:00:11.49#ibcon#about to read 4, iclass 26, count 0 2006.225.08:00:11.49#ibcon#read 4, iclass 26, count 0 2006.225.08:00:11.49#ibcon#about to read 5, iclass 26, count 0 2006.225.08:00:11.49#ibcon#read 5, iclass 26, count 0 2006.225.08:00:11.49#ibcon#about to read 6, iclass 26, count 0 2006.225.08:00:11.49#ibcon#read 6, iclass 26, count 0 2006.225.08:00:11.49#ibcon#end of sib2, iclass 26, count 0 2006.225.08:00:11.49#ibcon#*after write, iclass 26, count 0 2006.225.08:00:11.49#ibcon#*before return 0, iclass 26, count 0 2006.225.08:00:11.49#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.08:00:11.49#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.225.08:00:11.49#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.08:00:11.49#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.08:00:11.49$vc4f8/vblo=4,712.99 2006.225.08:00:11.49#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.08:00:11.49#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.08:00:11.49#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:11.49#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:00:11.49#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:00:11.49#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:00:11.49#ibcon#enter wrdev, iclass 28, count 0 2006.225.08:00:11.49#ibcon#first serial, iclass 28, count 0 2006.225.08:00:11.49#ibcon#enter sib2, iclass 28, count 0 2006.225.08:00:11.49#ibcon#flushed, iclass 28, count 0 2006.225.08:00:11.49#ibcon#about to write, iclass 28, count 0 2006.225.08:00:11.49#ibcon#wrote, iclass 28, count 0 2006.225.08:00:11.49#ibcon#about to read 3, iclass 28, count 0 2006.225.08:00:11.51#ibcon#read 3, iclass 28, count 0 2006.225.08:00:11.51#ibcon#about to read 4, iclass 28, count 0 2006.225.08:00:11.51#ibcon#read 4, iclass 28, count 0 2006.225.08:00:11.51#ibcon#about to read 5, iclass 28, count 0 2006.225.08:00:11.51#ibcon#read 5, iclass 28, count 0 2006.225.08:00:11.51#ibcon#about to read 6, iclass 28, count 0 2006.225.08:00:11.51#ibcon#read 6, iclass 28, count 0 2006.225.08:00:11.51#ibcon#end of sib2, iclass 28, count 0 2006.225.08:00:11.51#ibcon#*mode == 0, iclass 28, count 0 2006.225.08:00:11.51#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.08:00:11.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:00:11.51#ibcon#*before write, iclass 28, count 0 2006.225.08:00:11.51#ibcon#enter sib2, iclass 28, count 0 2006.225.08:00:11.51#ibcon#flushed, iclass 28, count 0 2006.225.08:00:11.51#ibcon#about to write, iclass 28, count 0 2006.225.08:00:11.51#ibcon#wrote, iclass 28, count 0 2006.225.08:00:11.51#ibcon#about to read 3, iclass 28, count 0 2006.225.08:00:11.55#ibcon#read 3, iclass 28, count 0 2006.225.08:00:11.55#ibcon#about to read 4, iclass 28, count 0 2006.225.08:00:11.55#ibcon#read 4, iclass 28, count 0 2006.225.08:00:11.55#ibcon#about to read 5, iclass 28, count 0 2006.225.08:00:11.55#ibcon#read 5, iclass 28, count 0 2006.225.08:00:11.55#ibcon#about to read 6, iclass 28, count 0 2006.225.08:00:11.55#ibcon#read 6, iclass 28, count 0 2006.225.08:00:11.55#ibcon#end of sib2, iclass 28, count 0 2006.225.08:00:11.55#ibcon#*after write, iclass 28, count 0 2006.225.08:00:11.55#ibcon#*before return 0, iclass 28, count 0 2006.225.08:00:11.55#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:00:11.55#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:00:11.55#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.08:00:11.55#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.08:00:11.55$vc4f8/vb=4,4 2006.225.08:00:11.55#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.08:00:11.55#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.08:00:11.55#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:11.55#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:00:11.61#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:00:11.61#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:00:11.61#ibcon#enter wrdev, iclass 30, count 2 2006.225.08:00:11.61#ibcon#first serial, iclass 30, count 2 2006.225.08:00:11.61#ibcon#enter sib2, iclass 30, count 2 2006.225.08:00:11.61#ibcon#flushed, iclass 30, count 2 2006.225.08:00:11.61#ibcon#about to write, iclass 30, count 2 2006.225.08:00:11.61#ibcon#wrote, iclass 30, count 2 2006.225.08:00:11.61#ibcon#about to read 3, iclass 30, count 2 2006.225.08:00:11.63#ibcon#read 3, iclass 30, count 2 2006.225.08:00:11.63#ibcon#about to read 4, iclass 30, count 2 2006.225.08:00:11.63#ibcon#read 4, iclass 30, count 2 2006.225.08:00:11.63#ibcon#about to read 5, iclass 30, count 2 2006.225.08:00:11.63#ibcon#read 5, iclass 30, count 2 2006.225.08:00:11.63#ibcon#about to read 6, iclass 30, count 2 2006.225.08:00:11.63#ibcon#read 6, iclass 30, count 2 2006.225.08:00:11.63#ibcon#end of sib2, iclass 30, count 2 2006.225.08:00:11.63#ibcon#*mode == 0, iclass 30, count 2 2006.225.08:00:11.63#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.08:00:11.63#ibcon#[27=AT04-04\r\n] 2006.225.08:00:11.63#ibcon#*before write, iclass 30, count 2 2006.225.08:00:11.63#ibcon#enter sib2, iclass 30, count 2 2006.225.08:00:11.63#ibcon#flushed, iclass 30, count 2 2006.225.08:00:11.63#ibcon#about to write, iclass 30, count 2 2006.225.08:00:11.63#ibcon#wrote, iclass 30, count 2 2006.225.08:00:11.63#ibcon#about to read 3, iclass 30, count 2 2006.225.08:00:11.66#ibcon#read 3, iclass 30, count 2 2006.225.08:00:11.66#ibcon#about to read 4, iclass 30, count 2 2006.225.08:00:11.66#ibcon#read 4, iclass 30, count 2 2006.225.08:00:11.66#ibcon#about to read 5, iclass 30, count 2 2006.225.08:00:11.66#ibcon#read 5, iclass 30, count 2 2006.225.08:00:11.66#ibcon#about to read 6, iclass 30, count 2 2006.225.08:00:11.66#ibcon#read 6, iclass 30, count 2 2006.225.08:00:11.66#ibcon#end of sib2, iclass 30, count 2 2006.225.08:00:11.66#ibcon#*after write, iclass 30, count 2 2006.225.08:00:11.66#ibcon#*before return 0, iclass 30, count 2 2006.225.08:00:11.66#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:00:11.66#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:00:11.66#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.08:00:11.66#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:11.66#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:00:11.78#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:00:11.78#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:00:11.78#ibcon#enter wrdev, iclass 30, count 0 2006.225.08:00:11.78#ibcon#first serial, iclass 30, count 0 2006.225.08:00:11.78#ibcon#enter sib2, iclass 30, count 0 2006.225.08:00:11.78#ibcon#flushed, iclass 30, count 0 2006.225.08:00:11.78#ibcon#about to write, iclass 30, count 0 2006.225.08:00:11.78#ibcon#wrote, iclass 30, count 0 2006.225.08:00:11.78#ibcon#about to read 3, iclass 30, count 0 2006.225.08:00:11.80#ibcon#read 3, iclass 30, count 0 2006.225.08:00:11.80#ibcon#about to read 4, iclass 30, count 0 2006.225.08:00:11.80#ibcon#read 4, iclass 30, count 0 2006.225.08:00:11.80#ibcon#about to read 5, iclass 30, count 0 2006.225.08:00:11.80#ibcon#read 5, iclass 30, count 0 2006.225.08:00:11.80#ibcon#about to read 6, iclass 30, count 0 2006.225.08:00:11.80#ibcon#read 6, iclass 30, count 0 2006.225.08:00:11.80#ibcon#end of sib2, iclass 30, count 0 2006.225.08:00:11.80#ibcon#*mode == 0, iclass 30, count 0 2006.225.08:00:11.80#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.08:00:11.80#ibcon#[27=USB\r\n] 2006.225.08:00:11.80#ibcon#*before write, iclass 30, count 0 2006.225.08:00:11.80#ibcon#enter sib2, iclass 30, count 0 2006.225.08:00:11.80#ibcon#flushed, iclass 30, count 0 2006.225.08:00:11.80#ibcon#about to write, iclass 30, count 0 2006.225.08:00:11.80#ibcon#wrote, iclass 30, count 0 2006.225.08:00:11.80#ibcon#about to read 3, iclass 30, count 0 2006.225.08:00:11.83#ibcon#read 3, iclass 30, count 0 2006.225.08:00:11.83#ibcon#about to read 4, iclass 30, count 0 2006.225.08:00:11.83#ibcon#read 4, iclass 30, count 0 2006.225.08:00:11.83#ibcon#about to read 5, iclass 30, count 0 2006.225.08:00:11.83#ibcon#read 5, iclass 30, count 0 2006.225.08:00:11.83#ibcon#about to read 6, iclass 30, count 0 2006.225.08:00:11.83#ibcon#read 6, iclass 30, count 0 2006.225.08:00:11.83#ibcon#end of sib2, iclass 30, count 0 2006.225.08:00:11.83#ibcon#*after write, iclass 30, count 0 2006.225.08:00:11.83#ibcon#*before return 0, iclass 30, count 0 2006.225.08:00:11.83#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:00:11.83#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:00:11.83#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.08:00:11.83#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.08:00:11.83$vc4f8/vblo=5,744.99 2006.225.08:00:11.83#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.08:00:11.83#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.08:00:11.83#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:11.83#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:00:11.83#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:00:11.83#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:00:11.83#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:00:11.83#ibcon#first serial, iclass 32, count 0 2006.225.08:00:11.83#ibcon#enter sib2, iclass 32, count 0 2006.225.08:00:11.83#ibcon#flushed, iclass 32, count 0 2006.225.08:00:11.83#ibcon#about to write, iclass 32, count 0 2006.225.08:00:11.83#ibcon#wrote, iclass 32, count 0 2006.225.08:00:11.83#ibcon#about to read 3, iclass 32, count 0 2006.225.08:00:11.85#ibcon#read 3, iclass 32, count 0 2006.225.08:00:11.85#ibcon#about to read 4, iclass 32, count 0 2006.225.08:00:11.85#ibcon#read 4, iclass 32, count 0 2006.225.08:00:11.85#ibcon#about to read 5, iclass 32, count 0 2006.225.08:00:11.85#ibcon#read 5, iclass 32, count 0 2006.225.08:00:11.85#ibcon#about to read 6, iclass 32, count 0 2006.225.08:00:11.85#ibcon#read 6, iclass 32, count 0 2006.225.08:00:11.85#ibcon#end of sib2, iclass 32, count 0 2006.225.08:00:11.85#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:00:11.85#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:00:11.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:00:11.85#ibcon#*before write, iclass 32, count 0 2006.225.08:00:11.85#ibcon#enter sib2, iclass 32, count 0 2006.225.08:00:11.85#ibcon#flushed, iclass 32, count 0 2006.225.08:00:11.85#ibcon#about to write, iclass 32, count 0 2006.225.08:00:11.85#ibcon#wrote, iclass 32, count 0 2006.225.08:00:11.85#ibcon#about to read 3, iclass 32, count 0 2006.225.08:00:11.89#ibcon#read 3, iclass 32, count 0 2006.225.08:00:11.89#ibcon#about to read 4, iclass 32, count 0 2006.225.08:00:11.89#ibcon#read 4, iclass 32, count 0 2006.225.08:00:11.89#ibcon#about to read 5, iclass 32, count 0 2006.225.08:00:11.89#ibcon#read 5, iclass 32, count 0 2006.225.08:00:11.89#ibcon#about to read 6, iclass 32, count 0 2006.225.08:00:11.89#ibcon#read 6, iclass 32, count 0 2006.225.08:00:11.89#ibcon#end of sib2, iclass 32, count 0 2006.225.08:00:11.89#ibcon#*after write, iclass 32, count 0 2006.225.08:00:11.89#ibcon#*before return 0, iclass 32, count 0 2006.225.08:00:11.89#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:00:11.89#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:00:11.89#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:00:11.89#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:00:11.89$vc4f8/vb=5,4 2006.225.08:00:11.89#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.08:00:11.89#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.08:00:11.89#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:11.89#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:00:11.95#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:00:11.95#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:00:11.95#ibcon#enter wrdev, iclass 34, count 2 2006.225.08:00:11.95#ibcon#first serial, iclass 34, count 2 2006.225.08:00:11.95#ibcon#enter sib2, iclass 34, count 2 2006.225.08:00:11.95#ibcon#flushed, iclass 34, count 2 2006.225.08:00:11.95#ibcon#about to write, iclass 34, count 2 2006.225.08:00:11.95#ibcon#wrote, iclass 34, count 2 2006.225.08:00:11.95#ibcon#about to read 3, iclass 34, count 2 2006.225.08:00:11.97#ibcon#read 3, iclass 34, count 2 2006.225.08:00:11.97#ibcon#about to read 4, iclass 34, count 2 2006.225.08:00:11.97#ibcon#read 4, iclass 34, count 2 2006.225.08:00:11.97#ibcon#about to read 5, iclass 34, count 2 2006.225.08:00:11.97#ibcon#read 5, iclass 34, count 2 2006.225.08:00:11.97#ibcon#about to read 6, iclass 34, count 2 2006.225.08:00:11.97#ibcon#read 6, iclass 34, count 2 2006.225.08:00:11.97#ibcon#end of sib2, iclass 34, count 2 2006.225.08:00:11.97#ibcon#*mode == 0, iclass 34, count 2 2006.225.08:00:11.97#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.08:00:11.97#ibcon#[27=AT05-04\r\n] 2006.225.08:00:11.97#ibcon#*before write, iclass 34, count 2 2006.225.08:00:11.97#ibcon#enter sib2, iclass 34, count 2 2006.225.08:00:11.97#ibcon#flushed, iclass 34, count 2 2006.225.08:00:11.97#ibcon#about to write, iclass 34, count 2 2006.225.08:00:11.97#ibcon#wrote, iclass 34, count 2 2006.225.08:00:11.97#ibcon#about to read 3, iclass 34, count 2 2006.225.08:00:12.00#ibcon#read 3, iclass 34, count 2 2006.225.08:00:12.00#ibcon#about to read 4, iclass 34, count 2 2006.225.08:00:12.00#ibcon#read 4, iclass 34, count 2 2006.225.08:00:12.00#ibcon#about to read 5, iclass 34, count 2 2006.225.08:00:12.00#ibcon#read 5, iclass 34, count 2 2006.225.08:00:12.00#ibcon#about to read 6, iclass 34, count 2 2006.225.08:00:12.00#ibcon#read 6, iclass 34, count 2 2006.225.08:00:12.00#ibcon#end of sib2, iclass 34, count 2 2006.225.08:00:12.00#ibcon#*after write, iclass 34, count 2 2006.225.08:00:12.00#ibcon#*before return 0, iclass 34, count 2 2006.225.08:00:12.00#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:00:12.00#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:00:12.00#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.08:00:12.00#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:12.00#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:00:12.12#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:00:12.12#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:00:12.12#ibcon#enter wrdev, iclass 34, count 0 2006.225.08:00:12.12#ibcon#first serial, iclass 34, count 0 2006.225.08:00:12.12#ibcon#enter sib2, iclass 34, count 0 2006.225.08:00:12.12#ibcon#flushed, iclass 34, count 0 2006.225.08:00:12.12#ibcon#about to write, iclass 34, count 0 2006.225.08:00:12.12#ibcon#wrote, iclass 34, count 0 2006.225.08:00:12.12#ibcon#about to read 3, iclass 34, count 0 2006.225.08:00:12.14#ibcon#read 3, iclass 34, count 0 2006.225.08:00:12.14#ibcon#about to read 4, iclass 34, count 0 2006.225.08:00:12.14#ibcon#read 4, iclass 34, count 0 2006.225.08:00:12.14#ibcon#about to read 5, iclass 34, count 0 2006.225.08:00:12.14#ibcon#read 5, iclass 34, count 0 2006.225.08:00:12.14#ibcon#about to read 6, iclass 34, count 0 2006.225.08:00:12.14#ibcon#read 6, iclass 34, count 0 2006.225.08:00:12.14#ibcon#end of sib2, iclass 34, count 0 2006.225.08:00:12.14#ibcon#*mode == 0, iclass 34, count 0 2006.225.08:00:12.14#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.08:00:12.14#ibcon#[27=USB\r\n] 2006.225.08:00:12.14#ibcon#*before write, iclass 34, count 0 2006.225.08:00:12.14#ibcon#enter sib2, iclass 34, count 0 2006.225.08:00:12.14#ibcon#flushed, iclass 34, count 0 2006.225.08:00:12.14#ibcon#about to write, iclass 34, count 0 2006.225.08:00:12.14#ibcon#wrote, iclass 34, count 0 2006.225.08:00:12.14#ibcon#about to read 3, iclass 34, count 0 2006.225.08:00:12.17#ibcon#read 3, iclass 34, count 0 2006.225.08:00:12.17#ibcon#about to read 4, iclass 34, count 0 2006.225.08:00:12.17#ibcon#read 4, iclass 34, count 0 2006.225.08:00:12.17#ibcon#about to read 5, iclass 34, count 0 2006.225.08:00:12.17#ibcon#read 5, iclass 34, count 0 2006.225.08:00:12.17#ibcon#about to read 6, iclass 34, count 0 2006.225.08:00:12.17#ibcon#read 6, iclass 34, count 0 2006.225.08:00:12.17#ibcon#end of sib2, iclass 34, count 0 2006.225.08:00:12.17#ibcon#*after write, iclass 34, count 0 2006.225.08:00:12.17#ibcon#*before return 0, iclass 34, count 0 2006.225.08:00:12.17#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:00:12.17#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:00:12.17#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.08:00:12.17#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.08:00:12.17$vc4f8/vblo=6,752.99 2006.225.08:00:12.17#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.08:00:12.17#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.08:00:12.17#ibcon#ireg 17 cls_cnt 0 2006.225.08:00:12.17#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:00:12.17#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:00:12.17#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:00:12.17#ibcon#enter wrdev, iclass 36, count 0 2006.225.08:00:12.17#ibcon#first serial, iclass 36, count 0 2006.225.08:00:12.17#ibcon#enter sib2, iclass 36, count 0 2006.225.08:00:12.17#ibcon#flushed, iclass 36, count 0 2006.225.08:00:12.17#ibcon#about to write, iclass 36, count 0 2006.225.08:00:12.17#ibcon#wrote, iclass 36, count 0 2006.225.08:00:12.17#ibcon#about to read 3, iclass 36, count 0 2006.225.08:00:12.19#ibcon#read 3, iclass 36, count 0 2006.225.08:00:12.19#ibcon#about to read 4, iclass 36, count 0 2006.225.08:00:12.19#ibcon#read 4, iclass 36, count 0 2006.225.08:00:12.19#ibcon#about to read 5, iclass 36, count 0 2006.225.08:00:12.19#ibcon#read 5, iclass 36, count 0 2006.225.08:00:12.19#ibcon#about to read 6, iclass 36, count 0 2006.225.08:00:12.19#ibcon#read 6, iclass 36, count 0 2006.225.08:00:12.19#ibcon#end of sib2, iclass 36, count 0 2006.225.08:00:12.19#ibcon#*mode == 0, iclass 36, count 0 2006.225.08:00:12.19#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.08:00:12.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:00:12.19#ibcon#*before write, iclass 36, count 0 2006.225.08:00:12.19#ibcon#enter sib2, iclass 36, count 0 2006.225.08:00:12.19#ibcon#flushed, iclass 36, count 0 2006.225.08:00:12.19#ibcon#about to write, iclass 36, count 0 2006.225.08:00:12.19#ibcon#wrote, iclass 36, count 0 2006.225.08:00:12.19#ibcon#about to read 3, iclass 36, count 0 2006.225.08:00:12.24#ibcon#read 3, iclass 36, count 0 2006.225.08:00:12.24#ibcon#about to read 4, iclass 36, count 0 2006.225.08:00:12.24#ibcon#read 4, iclass 36, count 0 2006.225.08:00:12.24#ibcon#about to read 5, iclass 36, count 0 2006.225.08:00:12.24#ibcon#read 5, iclass 36, count 0 2006.225.08:00:12.24#ibcon#about to read 6, iclass 36, count 0 2006.225.08:00:12.24#ibcon#read 6, iclass 36, count 0 2006.225.08:00:12.24#ibcon#end of sib2, iclass 36, count 0 2006.225.08:00:12.24#ibcon#*after write, iclass 36, count 0 2006.225.08:00:12.24#ibcon#*before return 0, iclass 36, count 0 2006.225.08:00:12.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:00:12.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:00:12.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.08:00:12.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.08:00:12.24$vc4f8/vb=6,4 2006.225.08:00:12.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.08:00:12.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.08:00:12.24#ibcon#ireg 11 cls_cnt 2 2006.225.08:00:12.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:00:12.29#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:00:12.29#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:00:12.29#ibcon#enter wrdev, iclass 38, count 2 2006.225.08:00:12.29#ibcon#first serial, iclass 38, count 2 2006.225.08:00:12.29#ibcon#enter sib2, iclass 38, count 2 2006.225.08:00:12.29#ibcon#flushed, iclass 38, count 2 2006.225.08:00:12.29#ibcon#about to write, iclass 38, count 2 2006.225.08:00:12.29#ibcon#wrote, iclass 38, count 2 2006.225.08:00:12.29#ibcon#about to read 3, iclass 38, count 2 2006.225.08:00:12.31#ibcon#read 3, iclass 38, count 2 2006.225.08:00:12.31#ibcon#about to read 4, iclass 38, count 2 2006.225.08:00:12.31#ibcon#read 4, iclass 38, count 2 2006.225.08:00:12.31#ibcon#about to read 5, iclass 38, count 2 2006.225.08:00:12.31#ibcon#read 5, iclass 38, count 2 2006.225.08:00:12.31#ibcon#about to read 6, iclass 38, count 2 2006.225.08:00:12.31#ibcon#read 6, iclass 38, count 2 2006.225.08:00:12.31#ibcon#end of sib2, iclass 38, count 2 2006.225.08:00:12.31#ibcon#*mode == 0, iclass 38, count 2 2006.225.08:00:12.31#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.08:00:12.31#ibcon#[27=AT06-04\r\n] 2006.225.08:00:12.31#ibcon#*before write, iclass 38, count 2 2006.225.08:00:12.31#ibcon#enter sib2, iclass 38, count 2 2006.225.08:00:12.31#ibcon#flushed, iclass 38, count 2 2006.225.08:00:12.31#ibcon#about to write, iclass 38, count 2 2006.225.08:00:12.31#ibcon#wrote, iclass 38, count 2 2006.225.08:00:12.31#ibcon#about to read 3, iclass 38, count 2 2006.225.08:00:12.34#ibcon#read 3, iclass 38, count 2 2006.225.08:00:12.34#ibcon#about to read 4, iclass 38, count 2 2006.225.08:00:12.34#ibcon#read 4, iclass 38, count 2 2006.225.08:00:12.34#ibcon#about to read 5, iclass 38, count 2 2006.225.08:00:12.34#ibcon#read 5, iclass 38, count 2 2006.225.08:00:12.34#ibcon#about to read 6, iclass 38, count 2 2006.225.08:00:12.34#ibcon#read 6, iclass 38, count 2 2006.225.08:00:12.34#ibcon#end of sib2, iclass 38, count 2 2006.225.08:00:12.34#ibcon#*after write, iclass 38, count 2 2006.225.08:00:12.34#ibcon#*before return 0, iclass 38, count 2 2006.225.08:00:12.34#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:00:12.34#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:00:12.34#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.08:00:12.34#ibcon#ireg 7 cls_cnt 0 2006.225.08:00:12.34#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:00:12.46#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:00:12.46#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:00:12.46#ibcon#enter wrdev, iclass 38, count 0 2006.225.08:00:12.46#ibcon#first serial, iclass 38, count 0 2006.225.08:00:12.46#ibcon#enter sib2, iclass 38, count 0 2006.225.08:00:12.46#ibcon#flushed, iclass 38, count 0 2006.225.08:00:12.46#ibcon#about to write, iclass 38, count 0 2006.225.08:00:12.46#ibcon#wrote, iclass 38, count 0 2006.225.08:00:12.46#ibcon#about to read 3, iclass 38, count 0 2006.225.08:00:12.48#ibcon#read 3, iclass 38, count 0 2006.225.08:00:12.48#ibcon#about to read 4, iclass 38, count 0 2006.225.08:00:12.48#ibcon#read 4, iclass 38, count 0 2006.225.08:00:12.48#ibcon#about to read 5, iclass 38, count 0 2006.225.08:00:12.48#ibcon#read 5, iclass 38, count 0 2006.225.08:00:12.48#ibcon#about to read 6, iclass 38, count 0 2006.225.08:00:12.48#ibcon#read 6, iclass 38, count 0 2006.225.08:00:12.48#ibcon#end of sib2, iclass 38, count 0 2006.225.08:00:12.48#ibcon#*mode == 0, iclass 38, count 0 2006.225.08:00:12.48#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.08:00:12.48#ibcon#[27=USB\r\n] 2006.225.08:00:12.48#ibcon#*before write, iclass 38, count 0 2006.225.08:00:12.48#ibcon#enter sib2, iclass 38, count 0 2006.225.08:00:12.48#ibcon#flushed, iclass 38, count 0 2006.225.08:00:12.48#ibcon#about to write, iclass 38, count 0 2006.225.08:00:12.48#ibcon#wrote, iclass 38, count 0 2006.225.08:00:12.48#ibcon#about to read 3, iclass 38, count 0 2006.225.08:00:12.51#ibcon#read 3, iclass 38, count 0 2006.225.08:00:12.51#ibcon#about to read 4, iclass 38, count 0 2006.225.08:00:12.51#ibcon#read 4, iclass 38, count 0 2006.225.08:00:12.51#ibcon#about to read 5, iclass 38, count 0 2006.225.08:00:12.51#ibcon#read 5, iclass 38, count 0 2006.225.08:00:12.51#ibcon#about to read 6, iclass 38, count 0 2006.225.08:00:12.51#ibcon#read 6, iclass 38, count 0 2006.225.08:00:12.51#ibcon#end of sib2, iclass 38, count 0 2006.225.08:00:12.51#ibcon#*after write, iclass 38, count 0 2006.225.08:00:12.51#ibcon#*before return 0, iclass 38, count 0 2006.225.08:00:12.51#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:00:12.51#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:00:12.51#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.08:00:12.51#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.08:00:12.51$vc4f8/vabw=wide 2006.225.08:00:12.51#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.08:00:12.51#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.08:00:12.51#ibcon#ireg 8 cls_cnt 0 2006.225.08:00:12.51#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:00:12.51#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:00:12.51#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:00:12.51#ibcon#enter wrdev, iclass 40, count 0 2006.225.08:00:12.51#ibcon#first serial, iclass 40, count 0 2006.225.08:00:12.51#ibcon#enter sib2, iclass 40, count 0 2006.225.08:00:12.51#ibcon#flushed, iclass 40, count 0 2006.225.08:00:12.51#ibcon#about to write, iclass 40, count 0 2006.225.08:00:12.51#ibcon#wrote, iclass 40, count 0 2006.225.08:00:12.51#ibcon#about to read 3, iclass 40, count 0 2006.225.08:00:12.53#ibcon#read 3, iclass 40, count 0 2006.225.08:00:12.53#ibcon#about to read 4, iclass 40, count 0 2006.225.08:00:12.53#ibcon#read 4, iclass 40, count 0 2006.225.08:00:12.53#ibcon#about to read 5, iclass 40, count 0 2006.225.08:00:12.53#ibcon#read 5, iclass 40, count 0 2006.225.08:00:12.53#ibcon#about to read 6, iclass 40, count 0 2006.225.08:00:12.53#ibcon#read 6, iclass 40, count 0 2006.225.08:00:12.53#ibcon#end of sib2, iclass 40, count 0 2006.225.08:00:12.53#ibcon#*mode == 0, iclass 40, count 0 2006.225.08:00:12.53#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.08:00:12.53#ibcon#[25=BW32\r\n] 2006.225.08:00:12.53#ibcon#*before write, iclass 40, count 0 2006.225.08:00:12.53#ibcon#enter sib2, iclass 40, count 0 2006.225.08:00:12.53#ibcon#flushed, iclass 40, count 0 2006.225.08:00:12.53#ibcon#about to write, iclass 40, count 0 2006.225.08:00:12.53#ibcon#wrote, iclass 40, count 0 2006.225.08:00:12.53#ibcon#about to read 3, iclass 40, count 0 2006.225.08:00:12.56#ibcon#read 3, iclass 40, count 0 2006.225.08:00:12.56#ibcon#about to read 4, iclass 40, count 0 2006.225.08:00:12.56#ibcon#read 4, iclass 40, count 0 2006.225.08:00:12.56#ibcon#about to read 5, iclass 40, count 0 2006.225.08:00:12.56#ibcon#read 5, iclass 40, count 0 2006.225.08:00:12.56#ibcon#about to read 6, iclass 40, count 0 2006.225.08:00:12.56#ibcon#read 6, iclass 40, count 0 2006.225.08:00:12.56#ibcon#end of sib2, iclass 40, count 0 2006.225.08:00:12.56#ibcon#*after write, iclass 40, count 0 2006.225.08:00:12.56#ibcon#*before return 0, iclass 40, count 0 2006.225.08:00:12.56#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:00:12.56#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:00:12.56#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.08:00:12.56#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.08:00:12.56$vc4f8/vbbw=wide 2006.225.08:00:12.56#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.08:00:12.56#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.08:00:12.56#ibcon#ireg 8 cls_cnt 0 2006.225.08:00:12.56#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:00:12.63#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:00:12.63#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:00:12.63#ibcon#enter wrdev, iclass 4, count 0 2006.225.08:00:12.63#ibcon#first serial, iclass 4, count 0 2006.225.08:00:12.63#ibcon#enter sib2, iclass 4, count 0 2006.225.08:00:12.63#ibcon#flushed, iclass 4, count 0 2006.225.08:00:12.63#ibcon#about to write, iclass 4, count 0 2006.225.08:00:12.63#ibcon#wrote, iclass 4, count 0 2006.225.08:00:12.63#ibcon#about to read 3, iclass 4, count 0 2006.225.08:00:12.65#ibcon#read 3, iclass 4, count 0 2006.225.08:00:12.65#ibcon#about to read 4, iclass 4, count 0 2006.225.08:00:12.65#ibcon#read 4, iclass 4, count 0 2006.225.08:00:12.65#ibcon#about to read 5, iclass 4, count 0 2006.225.08:00:12.65#ibcon#read 5, iclass 4, count 0 2006.225.08:00:12.65#ibcon#about to read 6, iclass 4, count 0 2006.225.08:00:12.65#ibcon#read 6, iclass 4, count 0 2006.225.08:00:12.65#ibcon#end of sib2, iclass 4, count 0 2006.225.08:00:12.65#ibcon#*mode == 0, iclass 4, count 0 2006.225.08:00:12.65#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.08:00:12.65#ibcon#[27=BW32\r\n] 2006.225.08:00:12.65#ibcon#*before write, iclass 4, count 0 2006.225.08:00:12.65#ibcon#enter sib2, iclass 4, count 0 2006.225.08:00:12.65#ibcon#flushed, iclass 4, count 0 2006.225.08:00:12.65#ibcon#about to write, iclass 4, count 0 2006.225.08:00:12.65#ibcon#wrote, iclass 4, count 0 2006.225.08:00:12.65#ibcon#about to read 3, iclass 4, count 0 2006.225.08:00:12.68#ibcon#read 3, iclass 4, count 0 2006.225.08:00:12.68#ibcon#about to read 4, iclass 4, count 0 2006.225.08:00:12.68#ibcon#read 4, iclass 4, count 0 2006.225.08:00:12.68#ibcon#about to read 5, iclass 4, count 0 2006.225.08:00:12.68#ibcon#read 5, iclass 4, count 0 2006.225.08:00:12.68#ibcon#about to read 6, iclass 4, count 0 2006.225.08:00:12.68#ibcon#read 6, iclass 4, count 0 2006.225.08:00:12.68#ibcon#end of sib2, iclass 4, count 0 2006.225.08:00:12.68#ibcon#*after write, iclass 4, count 0 2006.225.08:00:12.68#ibcon#*before return 0, iclass 4, count 0 2006.225.08:00:12.68#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:00:12.68#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:00:12.68#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.08:00:12.68#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.08:00:12.68$4f8m12a/ifd4f 2006.225.08:00:12.68$ifd4f/lo= 2006.225.08:00:12.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:00:12.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:00:12.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:00:12.68$ifd4f/patch= 2006.225.08:00:12.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:00:12.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:00:12.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:00:12.68$4f8m12a/"form=m,16.000,1:2 2006.225.08:00:12.68$4f8m12a/"tpicd 2006.225.08:00:12.68$4f8m12a/echo=off 2006.225.08:00:12.68$4f8m12a/xlog=off 2006.225.08:00:12.68:!2006.225.08:00:40 2006.225.08:00:23.13#trakl#Source acquired 2006.225.08:00:25.13#flagr#flagr/antenna,acquired 2006.225.08:00:40.00:preob 2006.225.08:00:41.13/onsource/TRACKING 2006.225.08:00:41.13:!2006.225.08:00:50 2006.225.08:00:50.00:data_valid=on 2006.225.08:00:50.00:midob 2006.225.08:00:50.13/onsource/TRACKING 2006.225.08:00:50.13/wx/28.33,1003.4,70 2006.225.08:00:50.29/cable/+6.4044E-03 2006.225.08:00:51.38/va/01,08,usb,yes,28,30 2006.225.08:00:51.38/va/02,07,usb,yes,28,30 2006.225.08:00:51.38/va/03,06,usb,yes,30,30 2006.225.08:00:51.38/va/04,07,usb,yes,29,32 2006.225.08:00:51.38/va/05,07,usb,yes,32,34 2006.225.08:00:51.38/va/06,06,usb,yes,31,31 2006.225.08:00:51.38/va/07,06,usb,yes,32,31 2006.225.08:00:51.38/va/08,07,usb,yes,30,29 2006.225.08:00:51.61/valo/01,532.99,yes,locked 2006.225.08:00:51.61/valo/02,572.99,yes,locked 2006.225.08:00:51.61/valo/03,672.99,yes,locked 2006.225.08:00:51.61/valo/04,832.99,yes,locked 2006.225.08:00:51.61/valo/05,652.99,yes,locked 2006.225.08:00:51.61/valo/06,772.99,yes,locked 2006.225.08:00:51.61/valo/07,832.99,yes,locked 2006.225.08:00:51.61/valo/08,852.99,yes,locked 2006.225.08:00:52.70/vb/01,04,usb,yes,30,29 2006.225.08:00:52.70/vb/02,04,usb,yes,32,34 2006.225.08:00:52.70/vb/03,04,usb,yes,29,32 2006.225.08:00:52.70/vb/04,04,usb,yes,29,29 2006.225.08:00:52.70/vb/05,04,usb,yes,28,32 2006.225.08:00:52.70/vb/06,04,usb,yes,29,32 2006.225.08:00:52.70/vb/07,04,usb,yes,31,31 2006.225.08:00:52.70/vb/08,04,usb,yes,28,32 2006.225.08:00:52.94/vblo/01,632.99,yes,locked 2006.225.08:00:52.94/vblo/02,640.99,yes,locked 2006.225.08:00:52.94/vblo/03,656.99,yes,locked 2006.225.08:00:52.94/vblo/04,712.99,yes,locked 2006.225.08:00:52.94/vblo/05,744.99,yes,locked 2006.225.08:00:52.94/vblo/06,752.99,yes,locked 2006.225.08:00:52.94/vblo/07,734.99,yes,locked 2006.225.08:00:52.94/vblo/08,744.99,yes,locked 2006.225.08:00:53.09/vabw/8 2006.225.08:00:53.24/vbbw/8 2006.225.08:00:53.33/xfe/off,on,15.0 2006.225.08:00:53.71/ifatt/23,28,28,28 2006.225.08:00:54.08/fmout-gps/S +4.55E-07 2006.225.08:00:54.12:!2006.225.08:01:50 2006.225.08:01:50.00:data_valid=off 2006.225.08:01:50.00:postob 2006.225.08:01:50.14/cable/+6.4050E-03 2006.225.08:01:50.14/wx/28.31,1003.4,70 2006.225.08:01:51.07/fmout-gps/S +4.58E-07 2006.225.08:01:51.07:scan_name=225-0802,k06225,60 2006.225.08:01:51.07:source=4c39.25,092703.01,390220.9,2000.0,ccw 2006.225.08:01:51.14#flagr#flagr/antenna,new-source 2006.225.08:01:52.14:checkk5 2006.225.08:01:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:01:52.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:01:53.26/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:01:53.62/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:01:53.98/chk_obsdata//k5ts1/T2250800??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:01:54.35/chk_obsdata//k5ts2/T2250800??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:01:54.71/chk_obsdata//k5ts3/T2250800??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:01:55.08/chk_obsdata//k5ts4/T2250800??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:01:55.76/k5log//k5ts1_log_newline 2006.225.08:01:56.45/k5log//k5ts2_log_newline 2006.225.08:01:57.13/k5log//k5ts3_log_newline 2006.225.08:01:57.81/k5log//k5ts4_log_newline 2006.225.08:01:57.84/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:01:57.84:4f8m12a=2 2006.225.08:01:57.84$4f8m12a/echo=on 2006.225.08:01:57.84$4f8m12a/pcalon 2006.225.08:01:57.84$pcalon/"no phase cal control is implemented here 2006.225.08:01:57.84$4f8m12a/"tpicd=stop 2006.225.08:01:57.84$4f8m12a/vc4f8 2006.225.08:01:57.84$vc4f8/valo=1,532.99 2006.225.08:01:57.84#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.08:01:57.84#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.08:01:57.84#ibcon#ireg 17 cls_cnt 0 2006.225.08:01:57.84#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:01:57.84#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:01:57.84#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:01:57.84#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:01:57.84#ibcon#first serial, iclass 13, count 0 2006.225.08:01:57.84#ibcon#enter sib2, iclass 13, count 0 2006.225.08:01:57.84#ibcon#flushed, iclass 13, count 0 2006.225.08:01:57.84#ibcon#about to write, iclass 13, count 0 2006.225.08:01:57.84#ibcon#wrote, iclass 13, count 0 2006.225.08:01:57.84#ibcon#about to read 3, iclass 13, count 0 2006.225.08:01:57.88#ibcon#read 3, iclass 13, count 0 2006.225.08:01:57.88#ibcon#about to read 4, iclass 13, count 0 2006.225.08:01:57.88#ibcon#read 4, iclass 13, count 0 2006.225.08:01:57.88#ibcon#about to read 5, iclass 13, count 0 2006.225.08:01:57.88#ibcon#read 5, iclass 13, count 0 2006.225.08:01:57.88#ibcon#about to read 6, iclass 13, count 0 2006.225.08:01:57.88#ibcon#read 6, iclass 13, count 0 2006.225.08:01:57.88#ibcon#end of sib2, iclass 13, count 0 2006.225.08:01:57.88#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:01:57.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:01:57.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:01:57.88#ibcon#*before write, iclass 13, count 0 2006.225.08:01:57.88#ibcon#enter sib2, iclass 13, count 0 2006.225.08:01:57.88#ibcon#flushed, iclass 13, count 0 2006.225.08:01:57.88#ibcon#about to write, iclass 13, count 0 2006.225.08:01:57.88#ibcon#wrote, iclass 13, count 0 2006.225.08:01:57.88#ibcon#about to read 3, iclass 13, count 0 2006.225.08:01:57.93#ibcon#read 3, iclass 13, count 0 2006.225.08:01:57.93#ibcon#about to read 4, iclass 13, count 0 2006.225.08:01:57.93#ibcon#read 4, iclass 13, count 0 2006.225.08:01:57.93#ibcon#about to read 5, iclass 13, count 0 2006.225.08:01:57.93#ibcon#read 5, iclass 13, count 0 2006.225.08:01:57.93#ibcon#about to read 6, iclass 13, count 0 2006.225.08:01:57.93#ibcon#read 6, iclass 13, count 0 2006.225.08:01:57.93#ibcon#end of sib2, iclass 13, count 0 2006.225.08:01:57.93#ibcon#*after write, iclass 13, count 0 2006.225.08:01:57.93#ibcon#*before return 0, iclass 13, count 0 2006.225.08:01:57.93#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:01:57.93#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:01:57.93#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:01:57.93#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:01:57.93$vc4f8/va=1,8 2006.225.08:01:57.93#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.225.08:01:57.93#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.225.08:01:57.93#ibcon#ireg 11 cls_cnt 2 2006.225.08:01:57.93#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:01:57.93#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:01:57.93#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:01:57.93#ibcon#enter wrdev, iclass 15, count 2 2006.225.08:01:57.93#ibcon#first serial, iclass 15, count 2 2006.225.08:01:57.93#ibcon#enter sib2, iclass 15, count 2 2006.225.08:01:57.93#ibcon#flushed, iclass 15, count 2 2006.225.08:01:57.93#ibcon#about to write, iclass 15, count 2 2006.225.08:01:57.93#ibcon#wrote, iclass 15, count 2 2006.225.08:01:57.93#ibcon#about to read 3, iclass 15, count 2 2006.225.08:01:57.95#ibcon#read 3, iclass 15, count 2 2006.225.08:01:57.95#ibcon#about to read 4, iclass 15, count 2 2006.225.08:01:57.95#ibcon#read 4, iclass 15, count 2 2006.225.08:01:57.95#ibcon#about to read 5, iclass 15, count 2 2006.225.08:01:57.95#ibcon#read 5, iclass 15, count 2 2006.225.08:01:57.95#ibcon#about to read 6, iclass 15, count 2 2006.225.08:01:57.95#ibcon#read 6, iclass 15, count 2 2006.225.08:01:57.95#ibcon#end of sib2, iclass 15, count 2 2006.225.08:01:57.95#ibcon#*mode == 0, iclass 15, count 2 2006.225.08:01:57.95#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.225.08:01:57.95#ibcon#[25=AT01-08\r\n] 2006.225.08:01:57.95#ibcon#*before write, iclass 15, count 2 2006.225.08:01:57.95#ibcon#enter sib2, iclass 15, count 2 2006.225.08:01:57.95#ibcon#flushed, iclass 15, count 2 2006.225.08:01:57.95#ibcon#about to write, iclass 15, count 2 2006.225.08:01:57.95#ibcon#wrote, iclass 15, count 2 2006.225.08:01:57.95#ibcon#about to read 3, iclass 15, count 2 2006.225.08:01:57.98#ibcon#read 3, iclass 15, count 2 2006.225.08:01:57.98#ibcon#about to read 4, iclass 15, count 2 2006.225.08:01:57.98#ibcon#read 4, iclass 15, count 2 2006.225.08:01:57.98#ibcon#about to read 5, iclass 15, count 2 2006.225.08:01:57.98#ibcon#read 5, iclass 15, count 2 2006.225.08:01:57.98#ibcon#about to read 6, iclass 15, count 2 2006.225.08:01:57.98#ibcon#read 6, iclass 15, count 2 2006.225.08:01:57.98#ibcon#end of sib2, iclass 15, count 2 2006.225.08:01:57.98#ibcon#*after write, iclass 15, count 2 2006.225.08:01:57.98#ibcon#*before return 0, iclass 15, count 2 2006.225.08:01:57.98#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:01:57.98#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:01:57.98#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.225.08:01:57.98#ibcon#ireg 7 cls_cnt 0 2006.225.08:01:57.98#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:01:58.10#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:01:58.10#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:01:58.10#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:01:58.10#ibcon#first serial, iclass 15, count 0 2006.225.08:01:58.10#ibcon#enter sib2, iclass 15, count 0 2006.225.08:01:58.10#ibcon#flushed, iclass 15, count 0 2006.225.08:01:58.10#ibcon#about to write, iclass 15, count 0 2006.225.08:01:58.10#ibcon#wrote, iclass 15, count 0 2006.225.08:01:58.10#ibcon#about to read 3, iclass 15, count 0 2006.225.08:01:58.12#ibcon#read 3, iclass 15, count 0 2006.225.08:01:58.12#ibcon#about to read 4, iclass 15, count 0 2006.225.08:01:58.12#ibcon#read 4, iclass 15, count 0 2006.225.08:01:58.12#ibcon#about to read 5, iclass 15, count 0 2006.225.08:01:58.12#ibcon#read 5, iclass 15, count 0 2006.225.08:01:58.12#ibcon#about to read 6, iclass 15, count 0 2006.225.08:01:58.12#ibcon#read 6, iclass 15, count 0 2006.225.08:01:58.12#ibcon#end of sib2, iclass 15, count 0 2006.225.08:01:58.12#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:01:58.12#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:01:58.12#ibcon#[25=USB\r\n] 2006.225.08:01:58.12#ibcon#*before write, iclass 15, count 0 2006.225.08:01:58.12#ibcon#enter sib2, iclass 15, count 0 2006.225.08:01:58.12#ibcon#flushed, iclass 15, count 0 2006.225.08:01:58.12#ibcon#about to write, iclass 15, count 0 2006.225.08:01:58.12#ibcon#wrote, iclass 15, count 0 2006.225.08:01:58.12#ibcon#about to read 3, iclass 15, count 0 2006.225.08:01:58.15#ibcon#read 3, iclass 15, count 0 2006.225.08:01:58.15#ibcon#about to read 4, iclass 15, count 0 2006.225.08:01:58.15#ibcon#read 4, iclass 15, count 0 2006.225.08:01:58.15#ibcon#about to read 5, iclass 15, count 0 2006.225.08:01:58.15#ibcon#read 5, iclass 15, count 0 2006.225.08:01:58.15#ibcon#about to read 6, iclass 15, count 0 2006.225.08:01:58.15#ibcon#read 6, iclass 15, count 0 2006.225.08:01:58.15#ibcon#end of sib2, iclass 15, count 0 2006.225.08:01:58.15#ibcon#*after write, iclass 15, count 0 2006.225.08:01:58.15#ibcon#*before return 0, iclass 15, count 0 2006.225.08:01:58.15#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:01:58.15#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:01:58.15#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:01:58.15#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:01:58.15$vc4f8/valo=2,572.99 2006.225.08:01:58.15#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.225.08:01:58.15#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.225.08:01:58.15#ibcon#ireg 17 cls_cnt 0 2006.225.08:01:58.15#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:01:58.15#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:01:58.15#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:01:58.15#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:01:58.15#ibcon#first serial, iclass 17, count 0 2006.225.08:01:58.15#ibcon#enter sib2, iclass 17, count 0 2006.225.08:01:58.15#ibcon#flushed, iclass 17, count 0 2006.225.08:01:58.15#ibcon#about to write, iclass 17, count 0 2006.225.08:01:58.15#ibcon#wrote, iclass 17, count 0 2006.225.08:01:58.15#ibcon#about to read 3, iclass 17, count 0 2006.225.08:01:58.17#ibcon#read 3, iclass 17, count 0 2006.225.08:01:58.17#ibcon#about to read 4, iclass 17, count 0 2006.225.08:01:58.17#ibcon#read 4, iclass 17, count 0 2006.225.08:01:58.17#ibcon#about to read 5, iclass 17, count 0 2006.225.08:01:58.17#ibcon#read 5, iclass 17, count 0 2006.225.08:01:58.17#ibcon#about to read 6, iclass 17, count 0 2006.225.08:01:58.17#ibcon#read 6, iclass 17, count 0 2006.225.08:01:58.17#ibcon#end of sib2, iclass 17, count 0 2006.225.08:01:58.17#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:01:58.17#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:01:58.17#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:01:58.17#ibcon#*before write, iclass 17, count 0 2006.225.08:01:58.17#ibcon#enter sib2, iclass 17, count 0 2006.225.08:01:58.17#ibcon#flushed, iclass 17, count 0 2006.225.08:01:58.17#ibcon#about to write, iclass 17, count 0 2006.225.08:01:58.17#ibcon#wrote, iclass 17, count 0 2006.225.08:01:58.17#ibcon#about to read 3, iclass 17, count 0 2006.225.08:01:58.21#ibcon#read 3, iclass 17, count 0 2006.225.08:01:58.21#ibcon#about to read 4, iclass 17, count 0 2006.225.08:01:58.21#ibcon#read 4, iclass 17, count 0 2006.225.08:01:58.21#ibcon#about to read 5, iclass 17, count 0 2006.225.08:01:58.21#ibcon#read 5, iclass 17, count 0 2006.225.08:01:58.21#ibcon#about to read 6, iclass 17, count 0 2006.225.08:01:58.21#ibcon#read 6, iclass 17, count 0 2006.225.08:01:58.21#ibcon#end of sib2, iclass 17, count 0 2006.225.08:01:58.21#ibcon#*after write, iclass 17, count 0 2006.225.08:01:58.21#ibcon#*before return 0, iclass 17, count 0 2006.225.08:01:58.21#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:01:58.21#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:01:58.21#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:01:58.21#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:01:58.21$vc4f8/va=2,7 2006.225.08:01:58.21#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.225.08:01:58.21#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.225.08:01:58.21#ibcon#ireg 11 cls_cnt 2 2006.225.08:01:58.21#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:01:58.27#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:01:58.27#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:01:58.27#ibcon#enter wrdev, iclass 19, count 2 2006.225.08:01:58.27#ibcon#first serial, iclass 19, count 2 2006.225.08:01:58.27#ibcon#enter sib2, iclass 19, count 2 2006.225.08:01:58.27#ibcon#flushed, iclass 19, count 2 2006.225.08:01:58.27#ibcon#about to write, iclass 19, count 2 2006.225.08:01:58.27#ibcon#wrote, iclass 19, count 2 2006.225.08:01:58.27#ibcon#about to read 3, iclass 19, count 2 2006.225.08:01:58.29#ibcon#read 3, iclass 19, count 2 2006.225.08:01:58.29#ibcon#about to read 4, iclass 19, count 2 2006.225.08:01:58.29#ibcon#read 4, iclass 19, count 2 2006.225.08:01:58.29#ibcon#about to read 5, iclass 19, count 2 2006.225.08:01:58.29#ibcon#read 5, iclass 19, count 2 2006.225.08:01:58.29#ibcon#about to read 6, iclass 19, count 2 2006.225.08:01:58.29#ibcon#read 6, iclass 19, count 2 2006.225.08:01:58.29#ibcon#end of sib2, iclass 19, count 2 2006.225.08:01:58.29#ibcon#*mode == 0, iclass 19, count 2 2006.225.08:01:58.29#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.225.08:01:58.29#ibcon#[25=AT02-07\r\n] 2006.225.08:01:58.29#ibcon#*before write, iclass 19, count 2 2006.225.08:01:58.29#ibcon#enter sib2, iclass 19, count 2 2006.225.08:01:58.29#ibcon#flushed, iclass 19, count 2 2006.225.08:01:58.29#ibcon#about to write, iclass 19, count 2 2006.225.08:01:58.29#ibcon#wrote, iclass 19, count 2 2006.225.08:01:58.29#ibcon#about to read 3, iclass 19, count 2 2006.225.08:01:58.32#ibcon#read 3, iclass 19, count 2 2006.225.08:01:58.32#ibcon#about to read 4, iclass 19, count 2 2006.225.08:01:58.32#ibcon#read 4, iclass 19, count 2 2006.225.08:01:58.32#ibcon#about to read 5, iclass 19, count 2 2006.225.08:01:58.32#ibcon#read 5, iclass 19, count 2 2006.225.08:01:58.32#ibcon#about to read 6, iclass 19, count 2 2006.225.08:01:58.32#ibcon#read 6, iclass 19, count 2 2006.225.08:01:58.32#ibcon#end of sib2, iclass 19, count 2 2006.225.08:01:58.32#ibcon#*after write, iclass 19, count 2 2006.225.08:01:58.32#ibcon#*before return 0, iclass 19, count 2 2006.225.08:01:58.32#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:01:58.32#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:01:58.32#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.225.08:01:58.32#ibcon#ireg 7 cls_cnt 0 2006.225.08:01:58.32#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:01:58.44#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:01:58.44#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:01:58.44#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:01:58.44#ibcon#first serial, iclass 19, count 0 2006.225.08:01:58.44#ibcon#enter sib2, iclass 19, count 0 2006.225.08:01:58.44#ibcon#flushed, iclass 19, count 0 2006.225.08:01:58.44#ibcon#about to write, iclass 19, count 0 2006.225.08:01:58.44#ibcon#wrote, iclass 19, count 0 2006.225.08:01:58.44#ibcon#about to read 3, iclass 19, count 0 2006.225.08:01:58.46#ibcon#read 3, iclass 19, count 0 2006.225.08:01:58.46#ibcon#about to read 4, iclass 19, count 0 2006.225.08:01:58.46#ibcon#read 4, iclass 19, count 0 2006.225.08:01:58.46#ibcon#about to read 5, iclass 19, count 0 2006.225.08:01:58.46#ibcon#read 5, iclass 19, count 0 2006.225.08:01:58.46#ibcon#about to read 6, iclass 19, count 0 2006.225.08:01:58.46#ibcon#read 6, iclass 19, count 0 2006.225.08:01:58.46#ibcon#end of sib2, iclass 19, count 0 2006.225.08:01:58.46#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:01:58.46#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:01:58.46#ibcon#[25=USB\r\n] 2006.225.08:01:58.46#ibcon#*before write, iclass 19, count 0 2006.225.08:01:58.46#ibcon#enter sib2, iclass 19, count 0 2006.225.08:01:58.46#ibcon#flushed, iclass 19, count 0 2006.225.08:01:58.46#ibcon#about to write, iclass 19, count 0 2006.225.08:01:58.46#ibcon#wrote, iclass 19, count 0 2006.225.08:01:58.46#ibcon#about to read 3, iclass 19, count 0 2006.225.08:01:58.49#ibcon#read 3, iclass 19, count 0 2006.225.08:01:58.49#ibcon#about to read 4, iclass 19, count 0 2006.225.08:01:58.49#ibcon#read 4, iclass 19, count 0 2006.225.08:01:58.49#ibcon#about to read 5, iclass 19, count 0 2006.225.08:01:58.49#ibcon#read 5, iclass 19, count 0 2006.225.08:01:58.49#ibcon#about to read 6, iclass 19, count 0 2006.225.08:01:58.49#ibcon#read 6, iclass 19, count 0 2006.225.08:01:58.49#ibcon#end of sib2, iclass 19, count 0 2006.225.08:01:58.49#ibcon#*after write, iclass 19, count 0 2006.225.08:01:58.49#ibcon#*before return 0, iclass 19, count 0 2006.225.08:01:58.49#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:01:58.49#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:01:58.49#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:01:58.49#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:01:58.49$vc4f8/valo=3,672.99 2006.225.08:01:58.49#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.225.08:01:58.49#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.225.08:01:58.49#ibcon#ireg 17 cls_cnt 0 2006.225.08:01:58.49#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:01:58.49#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:01:58.49#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:01:58.49#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:01:58.49#ibcon#first serial, iclass 21, count 0 2006.225.08:01:58.49#ibcon#enter sib2, iclass 21, count 0 2006.225.08:01:58.49#ibcon#flushed, iclass 21, count 0 2006.225.08:01:58.49#ibcon#about to write, iclass 21, count 0 2006.225.08:01:58.49#ibcon#wrote, iclass 21, count 0 2006.225.08:01:58.49#ibcon#about to read 3, iclass 21, count 0 2006.225.08:01:58.51#ibcon#read 3, iclass 21, count 0 2006.225.08:01:58.51#ibcon#about to read 4, iclass 21, count 0 2006.225.08:01:58.51#ibcon#read 4, iclass 21, count 0 2006.225.08:01:58.51#ibcon#about to read 5, iclass 21, count 0 2006.225.08:01:58.51#ibcon#read 5, iclass 21, count 0 2006.225.08:01:58.51#ibcon#about to read 6, iclass 21, count 0 2006.225.08:01:58.51#ibcon#read 6, iclass 21, count 0 2006.225.08:01:58.51#ibcon#end of sib2, iclass 21, count 0 2006.225.08:01:58.51#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:01:58.51#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:01:58.51#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:01:58.51#ibcon#*before write, iclass 21, count 0 2006.225.08:01:58.51#ibcon#enter sib2, iclass 21, count 0 2006.225.08:01:58.51#ibcon#flushed, iclass 21, count 0 2006.225.08:01:58.51#ibcon#about to write, iclass 21, count 0 2006.225.08:01:58.51#ibcon#wrote, iclass 21, count 0 2006.225.08:01:58.51#ibcon#about to read 3, iclass 21, count 0 2006.225.08:01:58.55#ibcon#read 3, iclass 21, count 0 2006.225.08:01:58.55#ibcon#about to read 4, iclass 21, count 0 2006.225.08:01:58.55#ibcon#read 4, iclass 21, count 0 2006.225.08:01:58.55#ibcon#about to read 5, iclass 21, count 0 2006.225.08:01:58.55#ibcon#read 5, iclass 21, count 0 2006.225.08:01:58.55#ibcon#about to read 6, iclass 21, count 0 2006.225.08:01:58.55#ibcon#read 6, iclass 21, count 0 2006.225.08:01:58.55#ibcon#end of sib2, iclass 21, count 0 2006.225.08:01:58.55#ibcon#*after write, iclass 21, count 0 2006.225.08:01:58.55#ibcon#*before return 0, iclass 21, count 0 2006.225.08:01:58.55#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:01:58.55#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:01:58.55#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:01:58.55#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:01:58.55$vc4f8/va=3,6 2006.225.08:01:58.55#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.225.08:01:58.55#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.225.08:01:58.55#ibcon#ireg 11 cls_cnt 2 2006.225.08:01:58.55#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:01:58.61#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:01:58.61#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:01:58.61#ibcon#enter wrdev, iclass 23, count 2 2006.225.08:01:58.61#ibcon#first serial, iclass 23, count 2 2006.225.08:01:58.61#ibcon#enter sib2, iclass 23, count 2 2006.225.08:01:58.61#ibcon#flushed, iclass 23, count 2 2006.225.08:01:58.61#ibcon#about to write, iclass 23, count 2 2006.225.08:01:58.61#ibcon#wrote, iclass 23, count 2 2006.225.08:01:58.61#ibcon#about to read 3, iclass 23, count 2 2006.225.08:01:58.63#ibcon#read 3, iclass 23, count 2 2006.225.08:01:58.63#ibcon#about to read 4, iclass 23, count 2 2006.225.08:01:58.63#ibcon#read 4, iclass 23, count 2 2006.225.08:01:58.63#ibcon#about to read 5, iclass 23, count 2 2006.225.08:01:58.63#ibcon#read 5, iclass 23, count 2 2006.225.08:01:58.63#ibcon#about to read 6, iclass 23, count 2 2006.225.08:01:58.63#ibcon#read 6, iclass 23, count 2 2006.225.08:01:58.63#ibcon#end of sib2, iclass 23, count 2 2006.225.08:01:58.63#ibcon#*mode == 0, iclass 23, count 2 2006.225.08:01:58.63#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.225.08:01:58.63#ibcon#[25=AT03-06\r\n] 2006.225.08:01:58.63#ibcon#*before write, iclass 23, count 2 2006.225.08:01:58.63#ibcon#enter sib2, iclass 23, count 2 2006.225.08:01:58.63#ibcon#flushed, iclass 23, count 2 2006.225.08:01:58.63#ibcon#about to write, iclass 23, count 2 2006.225.08:01:58.63#ibcon#wrote, iclass 23, count 2 2006.225.08:01:58.63#ibcon#about to read 3, iclass 23, count 2 2006.225.08:01:58.66#ibcon#read 3, iclass 23, count 2 2006.225.08:01:58.66#ibcon#about to read 4, iclass 23, count 2 2006.225.08:01:58.66#ibcon#read 4, iclass 23, count 2 2006.225.08:01:58.66#ibcon#about to read 5, iclass 23, count 2 2006.225.08:01:58.66#ibcon#read 5, iclass 23, count 2 2006.225.08:01:58.66#ibcon#about to read 6, iclass 23, count 2 2006.225.08:01:58.66#ibcon#read 6, iclass 23, count 2 2006.225.08:01:58.66#ibcon#end of sib2, iclass 23, count 2 2006.225.08:01:58.66#ibcon#*after write, iclass 23, count 2 2006.225.08:01:58.66#ibcon#*before return 0, iclass 23, count 2 2006.225.08:01:58.66#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:01:58.66#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:01:58.66#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.225.08:01:58.66#ibcon#ireg 7 cls_cnt 0 2006.225.08:01:58.66#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:01:58.78#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:01:58.78#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:01:58.78#ibcon#enter wrdev, iclass 23, count 0 2006.225.08:01:58.78#ibcon#first serial, iclass 23, count 0 2006.225.08:01:58.78#ibcon#enter sib2, iclass 23, count 0 2006.225.08:01:58.78#ibcon#flushed, iclass 23, count 0 2006.225.08:01:58.78#ibcon#about to write, iclass 23, count 0 2006.225.08:01:58.78#ibcon#wrote, iclass 23, count 0 2006.225.08:01:58.78#ibcon#about to read 3, iclass 23, count 0 2006.225.08:01:58.80#ibcon#read 3, iclass 23, count 0 2006.225.08:01:58.80#ibcon#about to read 4, iclass 23, count 0 2006.225.08:01:58.80#ibcon#read 4, iclass 23, count 0 2006.225.08:01:58.80#ibcon#about to read 5, iclass 23, count 0 2006.225.08:01:58.80#ibcon#read 5, iclass 23, count 0 2006.225.08:01:58.80#ibcon#about to read 6, iclass 23, count 0 2006.225.08:01:58.80#ibcon#read 6, iclass 23, count 0 2006.225.08:01:58.80#ibcon#end of sib2, iclass 23, count 0 2006.225.08:01:58.80#ibcon#*mode == 0, iclass 23, count 0 2006.225.08:01:58.80#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.08:01:58.80#ibcon#[25=USB\r\n] 2006.225.08:01:58.80#ibcon#*before write, iclass 23, count 0 2006.225.08:01:58.80#ibcon#enter sib2, iclass 23, count 0 2006.225.08:01:58.80#ibcon#flushed, iclass 23, count 0 2006.225.08:01:58.80#ibcon#about to write, iclass 23, count 0 2006.225.08:01:58.80#ibcon#wrote, iclass 23, count 0 2006.225.08:01:58.80#ibcon#about to read 3, iclass 23, count 0 2006.225.08:01:58.83#ibcon#read 3, iclass 23, count 0 2006.225.08:01:58.83#ibcon#about to read 4, iclass 23, count 0 2006.225.08:01:58.83#ibcon#read 4, iclass 23, count 0 2006.225.08:01:58.83#ibcon#about to read 5, iclass 23, count 0 2006.225.08:01:58.83#ibcon#read 5, iclass 23, count 0 2006.225.08:01:58.83#ibcon#about to read 6, iclass 23, count 0 2006.225.08:01:58.83#ibcon#read 6, iclass 23, count 0 2006.225.08:01:58.83#ibcon#end of sib2, iclass 23, count 0 2006.225.08:01:58.83#ibcon#*after write, iclass 23, count 0 2006.225.08:01:58.83#ibcon#*before return 0, iclass 23, count 0 2006.225.08:01:58.83#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:01:58.83#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:01:58.83#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.08:01:58.83#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.08:01:58.83$vc4f8/valo=4,832.99 2006.225.08:01:58.83#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.225.08:01:58.83#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.225.08:01:58.83#ibcon#ireg 17 cls_cnt 0 2006.225.08:01:58.83#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:01:58.83#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:01:58.83#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:01:58.83#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:01:58.83#ibcon#first serial, iclass 25, count 0 2006.225.08:01:58.83#ibcon#enter sib2, iclass 25, count 0 2006.225.08:01:58.83#ibcon#flushed, iclass 25, count 0 2006.225.08:01:58.83#ibcon#about to write, iclass 25, count 0 2006.225.08:01:58.83#ibcon#wrote, iclass 25, count 0 2006.225.08:01:58.83#ibcon#about to read 3, iclass 25, count 0 2006.225.08:01:58.85#ibcon#read 3, iclass 25, count 0 2006.225.08:01:58.85#ibcon#about to read 4, iclass 25, count 0 2006.225.08:01:58.85#ibcon#read 4, iclass 25, count 0 2006.225.08:01:58.85#ibcon#about to read 5, iclass 25, count 0 2006.225.08:01:58.85#ibcon#read 5, iclass 25, count 0 2006.225.08:01:58.85#ibcon#about to read 6, iclass 25, count 0 2006.225.08:01:58.85#ibcon#read 6, iclass 25, count 0 2006.225.08:01:58.85#ibcon#end of sib2, iclass 25, count 0 2006.225.08:01:58.85#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:01:58.85#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:01:58.85#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:01:58.85#ibcon#*before write, iclass 25, count 0 2006.225.08:01:58.85#ibcon#enter sib2, iclass 25, count 0 2006.225.08:01:58.85#ibcon#flushed, iclass 25, count 0 2006.225.08:01:58.85#ibcon#about to write, iclass 25, count 0 2006.225.08:01:58.85#ibcon#wrote, iclass 25, count 0 2006.225.08:01:58.85#ibcon#about to read 3, iclass 25, count 0 2006.225.08:01:58.89#ibcon#read 3, iclass 25, count 0 2006.225.08:01:58.89#ibcon#about to read 4, iclass 25, count 0 2006.225.08:01:58.89#ibcon#read 4, iclass 25, count 0 2006.225.08:01:58.89#ibcon#about to read 5, iclass 25, count 0 2006.225.08:01:58.89#ibcon#read 5, iclass 25, count 0 2006.225.08:01:58.89#ibcon#about to read 6, iclass 25, count 0 2006.225.08:01:58.89#ibcon#read 6, iclass 25, count 0 2006.225.08:01:58.89#ibcon#end of sib2, iclass 25, count 0 2006.225.08:01:58.89#ibcon#*after write, iclass 25, count 0 2006.225.08:01:58.89#ibcon#*before return 0, iclass 25, count 0 2006.225.08:01:58.89#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:01:58.89#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:01:58.89#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:01:58.89#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:01:58.89$vc4f8/va=4,7 2006.225.08:01:58.89#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.225.08:01:58.89#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.225.08:01:58.89#ibcon#ireg 11 cls_cnt 2 2006.225.08:01:58.89#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:01:58.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:01:58.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:01:58.95#ibcon#enter wrdev, iclass 27, count 2 2006.225.08:01:58.95#ibcon#first serial, iclass 27, count 2 2006.225.08:01:58.95#ibcon#enter sib2, iclass 27, count 2 2006.225.08:01:58.95#ibcon#flushed, iclass 27, count 2 2006.225.08:01:58.95#ibcon#about to write, iclass 27, count 2 2006.225.08:01:58.95#ibcon#wrote, iclass 27, count 2 2006.225.08:01:58.95#ibcon#about to read 3, iclass 27, count 2 2006.225.08:01:58.97#ibcon#read 3, iclass 27, count 2 2006.225.08:01:58.97#ibcon#about to read 4, iclass 27, count 2 2006.225.08:01:58.97#ibcon#read 4, iclass 27, count 2 2006.225.08:01:58.97#ibcon#about to read 5, iclass 27, count 2 2006.225.08:01:58.97#ibcon#read 5, iclass 27, count 2 2006.225.08:01:58.97#ibcon#about to read 6, iclass 27, count 2 2006.225.08:01:58.97#ibcon#read 6, iclass 27, count 2 2006.225.08:01:58.97#ibcon#end of sib2, iclass 27, count 2 2006.225.08:01:58.97#ibcon#*mode == 0, iclass 27, count 2 2006.225.08:01:58.97#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.225.08:01:58.97#ibcon#[25=AT04-07\r\n] 2006.225.08:01:58.97#ibcon#*before write, iclass 27, count 2 2006.225.08:01:58.97#ibcon#enter sib2, iclass 27, count 2 2006.225.08:01:58.97#ibcon#flushed, iclass 27, count 2 2006.225.08:01:58.97#ibcon#about to write, iclass 27, count 2 2006.225.08:01:58.97#ibcon#wrote, iclass 27, count 2 2006.225.08:01:58.97#ibcon#about to read 3, iclass 27, count 2 2006.225.08:01:59.00#ibcon#read 3, iclass 27, count 2 2006.225.08:01:59.00#ibcon#about to read 4, iclass 27, count 2 2006.225.08:01:59.00#ibcon#read 4, iclass 27, count 2 2006.225.08:01:59.00#ibcon#about to read 5, iclass 27, count 2 2006.225.08:01:59.00#ibcon#read 5, iclass 27, count 2 2006.225.08:01:59.00#ibcon#about to read 6, iclass 27, count 2 2006.225.08:01:59.00#ibcon#read 6, iclass 27, count 2 2006.225.08:01:59.00#ibcon#end of sib2, iclass 27, count 2 2006.225.08:01:59.00#ibcon#*after write, iclass 27, count 2 2006.225.08:01:59.00#ibcon#*before return 0, iclass 27, count 2 2006.225.08:01:59.00#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:01:59.00#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:01:59.00#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.225.08:01:59.00#ibcon#ireg 7 cls_cnt 0 2006.225.08:01:59.00#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:01:59.12#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:01:59.12#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:01:59.12#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:01:59.12#ibcon#first serial, iclass 27, count 0 2006.225.08:01:59.12#ibcon#enter sib2, iclass 27, count 0 2006.225.08:01:59.12#ibcon#flushed, iclass 27, count 0 2006.225.08:01:59.12#ibcon#about to write, iclass 27, count 0 2006.225.08:01:59.12#ibcon#wrote, iclass 27, count 0 2006.225.08:01:59.12#ibcon#about to read 3, iclass 27, count 0 2006.225.08:01:59.14#ibcon#read 3, iclass 27, count 0 2006.225.08:01:59.14#ibcon#about to read 4, iclass 27, count 0 2006.225.08:01:59.14#ibcon#read 4, iclass 27, count 0 2006.225.08:01:59.14#ibcon#about to read 5, iclass 27, count 0 2006.225.08:01:59.14#ibcon#read 5, iclass 27, count 0 2006.225.08:01:59.14#ibcon#about to read 6, iclass 27, count 0 2006.225.08:01:59.14#ibcon#read 6, iclass 27, count 0 2006.225.08:01:59.14#ibcon#end of sib2, iclass 27, count 0 2006.225.08:01:59.14#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:01:59.14#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:01:59.14#ibcon#[25=USB\r\n] 2006.225.08:01:59.14#ibcon#*before write, iclass 27, count 0 2006.225.08:01:59.14#ibcon#enter sib2, iclass 27, count 0 2006.225.08:01:59.14#ibcon#flushed, iclass 27, count 0 2006.225.08:01:59.14#ibcon#about to write, iclass 27, count 0 2006.225.08:01:59.14#ibcon#wrote, iclass 27, count 0 2006.225.08:01:59.14#ibcon#about to read 3, iclass 27, count 0 2006.225.08:01:59.17#ibcon#read 3, iclass 27, count 0 2006.225.08:01:59.17#ibcon#about to read 4, iclass 27, count 0 2006.225.08:01:59.17#ibcon#read 4, iclass 27, count 0 2006.225.08:01:59.17#ibcon#about to read 5, iclass 27, count 0 2006.225.08:01:59.17#ibcon#read 5, iclass 27, count 0 2006.225.08:01:59.17#ibcon#about to read 6, iclass 27, count 0 2006.225.08:01:59.17#ibcon#read 6, iclass 27, count 0 2006.225.08:01:59.17#ibcon#end of sib2, iclass 27, count 0 2006.225.08:01:59.17#ibcon#*after write, iclass 27, count 0 2006.225.08:01:59.17#ibcon#*before return 0, iclass 27, count 0 2006.225.08:01:59.17#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:01:59.17#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:01:59.17#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:01:59.17#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:01:59.17$vc4f8/valo=5,652.99 2006.225.08:01:59.17#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.08:01:59.17#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.08:01:59.17#ibcon#ireg 17 cls_cnt 0 2006.225.08:01:59.17#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:01:59.17#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:01:59.17#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:01:59.17#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:01:59.17#ibcon#first serial, iclass 29, count 0 2006.225.08:01:59.17#ibcon#enter sib2, iclass 29, count 0 2006.225.08:01:59.17#ibcon#flushed, iclass 29, count 0 2006.225.08:01:59.17#ibcon#about to write, iclass 29, count 0 2006.225.08:01:59.17#ibcon#wrote, iclass 29, count 0 2006.225.08:01:59.17#ibcon#about to read 3, iclass 29, count 0 2006.225.08:01:59.19#ibcon#read 3, iclass 29, count 0 2006.225.08:01:59.19#ibcon#about to read 4, iclass 29, count 0 2006.225.08:01:59.19#ibcon#read 4, iclass 29, count 0 2006.225.08:01:59.19#ibcon#about to read 5, iclass 29, count 0 2006.225.08:01:59.19#ibcon#read 5, iclass 29, count 0 2006.225.08:01:59.19#ibcon#about to read 6, iclass 29, count 0 2006.225.08:01:59.19#ibcon#read 6, iclass 29, count 0 2006.225.08:01:59.19#ibcon#end of sib2, iclass 29, count 0 2006.225.08:01:59.19#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:01:59.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:01:59.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:01:59.19#ibcon#*before write, iclass 29, count 0 2006.225.08:01:59.19#ibcon#enter sib2, iclass 29, count 0 2006.225.08:01:59.19#ibcon#flushed, iclass 29, count 0 2006.225.08:01:59.19#ibcon#about to write, iclass 29, count 0 2006.225.08:01:59.19#ibcon#wrote, iclass 29, count 0 2006.225.08:01:59.19#ibcon#about to read 3, iclass 29, count 0 2006.225.08:01:59.23#ibcon#read 3, iclass 29, count 0 2006.225.08:01:59.23#ibcon#about to read 4, iclass 29, count 0 2006.225.08:01:59.23#ibcon#read 4, iclass 29, count 0 2006.225.08:01:59.23#ibcon#about to read 5, iclass 29, count 0 2006.225.08:01:59.23#ibcon#read 5, iclass 29, count 0 2006.225.08:01:59.23#ibcon#about to read 6, iclass 29, count 0 2006.225.08:01:59.23#ibcon#read 6, iclass 29, count 0 2006.225.08:01:59.23#ibcon#end of sib2, iclass 29, count 0 2006.225.08:01:59.23#ibcon#*after write, iclass 29, count 0 2006.225.08:01:59.23#ibcon#*before return 0, iclass 29, count 0 2006.225.08:01:59.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:01:59.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:01:59.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:01:59.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:01:59.23$vc4f8/va=5,7 2006.225.08:01:59.23#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.08:01:59.23#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.08:01:59.23#ibcon#ireg 11 cls_cnt 2 2006.225.08:01:59.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:01:59.29#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:01:59.29#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:01:59.29#ibcon#enter wrdev, iclass 31, count 2 2006.225.08:01:59.29#ibcon#first serial, iclass 31, count 2 2006.225.08:01:59.29#ibcon#enter sib2, iclass 31, count 2 2006.225.08:01:59.29#ibcon#flushed, iclass 31, count 2 2006.225.08:01:59.29#ibcon#about to write, iclass 31, count 2 2006.225.08:01:59.29#ibcon#wrote, iclass 31, count 2 2006.225.08:01:59.29#ibcon#about to read 3, iclass 31, count 2 2006.225.08:01:59.31#ibcon#read 3, iclass 31, count 2 2006.225.08:01:59.31#ibcon#about to read 4, iclass 31, count 2 2006.225.08:01:59.31#ibcon#read 4, iclass 31, count 2 2006.225.08:01:59.31#ibcon#about to read 5, iclass 31, count 2 2006.225.08:01:59.31#ibcon#read 5, iclass 31, count 2 2006.225.08:01:59.31#ibcon#about to read 6, iclass 31, count 2 2006.225.08:01:59.31#ibcon#read 6, iclass 31, count 2 2006.225.08:01:59.31#ibcon#end of sib2, iclass 31, count 2 2006.225.08:01:59.31#ibcon#*mode == 0, iclass 31, count 2 2006.225.08:01:59.31#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.08:01:59.31#ibcon#[25=AT05-07\r\n] 2006.225.08:01:59.31#ibcon#*before write, iclass 31, count 2 2006.225.08:01:59.31#ibcon#enter sib2, iclass 31, count 2 2006.225.08:01:59.31#ibcon#flushed, iclass 31, count 2 2006.225.08:01:59.31#ibcon#about to write, iclass 31, count 2 2006.225.08:01:59.31#ibcon#wrote, iclass 31, count 2 2006.225.08:01:59.31#ibcon#about to read 3, iclass 31, count 2 2006.225.08:01:59.34#ibcon#read 3, iclass 31, count 2 2006.225.08:01:59.34#ibcon#about to read 4, iclass 31, count 2 2006.225.08:01:59.34#ibcon#read 4, iclass 31, count 2 2006.225.08:01:59.34#ibcon#about to read 5, iclass 31, count 2 2006.225.08:01:59.34#ibcon#read 5, iclass 31, count 2 2006.225.08:01:59.34#ibcon#about to read 6, iclass 31, count 2 2006.225.08:01:59.34#ibcon#read 6, iclass 31, count 2 2006.225.08:01:59.34#ibcon#end of sib2, iclass 31, count 2 2006.225.08:01:59.34#ibcon#*after write, iclass 31, count 2 2006.225.08:01:59.34#ibcon#*before return 0, iclass 31, count 2 2006.225.08:01:59.34#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:01:59.34#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:01:59.34#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.08:01:59.34#ibcon#ireg 7 cls_cnt 0 2006.225.08:01:59.34#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:01:59.46#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:01:59.46#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:01:59.46#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:01:59.46#ibcon#first serial, iclass 31, count 0 2006.225.08:01:59.46#ibcon#enter sib2, iclass 31, count 0 2006.225.08:01:59.46#ibcon#flushed, iclass 31, count 0 2006.225.08:01:59.46#ibcon#about to write, iclass 31, count 0 2006.225.08:01:59.46#ibcon#wrote, iclass 31, count 0 2006.225.08:01:59.46#ibcon#about to read 3, iclass 31, count 0 2006.225.08:01:59.48#ibcon#read 3, iclass 31, count 0 2006.225.08:01:59.48#ibcon#about to read 4, iclass 31, count 0 2006.225.08:01:59.48#ibcon#read 4, iclass 31, count 0 2006.225.08:01:59.48#ibcon#about to read 5, iclass 31, count 0 2006.225.08:01:59.48#ibcon#read 5, iclass 31, count 0 2006.225.08:01:59.48#ibcon#about to read 6, iclass 31, count 0 2006.225.08:01:59.48#ibcon#read 6, iclass 31, count 0 2006.225.08:01:59.48#ibcon#end of sib2, iclass 31, count 0 2006.225.08:01:59.48#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:01:59.48#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:01:59.48#ibcon#[25=USB\r\n] 2006.225.08:01:59.48#ibcon#*before write, iclass 31, count 0 2006.225.08:01:59.48#ibcon#enter sib2, iclass 31, count 0 2006.225.08:01:59.48#ibcon#flushed, iclass 31, count 0 2006.225.08:01:59.48#ibcon#about to write, iclass 31, count 0 2006.225.08:01:59.48#ibcon#wrote, iclass 31, count 0 2006.225.08:01:59.48#ibcon#about to read 3, iclass 31, count 0 2006.225.08:01:59.51#ibcon#read 3, iclass 31, count 0 2006.225.08:01:59.51#ibcon#about to read 4, iclass 31, count 0 2006.225.08:01:59.51#ibcon#read 4, iclass 31, count 0 2006.225.08:01:59.51#ibcon#about to read 5, iclass 31, count 0 2006.225.08:01:59.51#ibcon#read 5, iclass 31, count 0 2006.225.08:01:59.51#ibcon#about to read 6, iclass 31, count 0 2006.225.08:01:59.51#ibcon#read 6, iclass 31, count 0 2006.225.08:01:59.51#ibcon#end of sib2, iclass 31, count 0 2006.225.08:01:59.51#ibcon#*after write, iclass 31, count 0 2006.225.08:01:59.51#ibcon#*before return 0, iclass 31, count 0 2006.225.08:01:59.51#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:01:59.51#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:01:59.51#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:01:59.51#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:01:59.51$vc4f8/valo=6,772.99 2006.225.08:01:59.51#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.08:01:59.51#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.08:01:59.51#ibcon#ireg 17 cls_cnt 0 2006.225.08:01:59.51#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:01:59.51#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:01:59.51#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:01:59.51#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:01:59.51#ibcon#first serial, iclass 33, count 0 2006.225.08:01:59.51#ibcon#enter sib2, iclass 33, count 0 2006.225.08:01:59.51#ibcon#flushed, iclass 33, count 0 2006.225.08:01:59.51#ibcon#about to write, iclass 33, count 0 2006.225.08:01:59.51#ibcon#wrote, iclass 33, count 0 2006.225.08:01:59.51#ibcon#about to read 3, iclass 33, count 0 2006.225.08:01:59.53#ibcon#read 3, iclass 33, count 0 2006.225.08:01:59.53#ibcon#about to read 4, iclass 33, count 0 2006.225.08:01:59.53#ibcon#read 4, iclass 33, count 0 2006.225.08:01:59.53#ibcon#about to read 5, iclass 33, count 0 2006.225.08:01:59.53#ibcon#read 5, iclass 33, count 0 2006.225.08:01:59.53#ibcon#about to read 6, iclass 33, count 0 2006.225.08:01:59.53#ibcon#read 6, iclass 33, count 0 2006.225.08:01:59.53#ibcon#end of sib2, iclass 33, count 0 2006.225.08:01:59.53#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:01:59.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:01:59.53#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:01:59.53#ibcon#*before write, iclass 33, count 0 2006.225.08:01:59.53#ibcon#enter sib2, iclass 33, count 0 2006.225.08:01:59.53#ibcon#flushed, iclass 33, count 0 2006.225.08:01:59.53#ibcon#about to write, iclass 33, count 0 2006.225.08:01:59.53#ibcon#wrote, iclass 33, count 0 2006.225.08:01:59.53#ibcon#about to read 3, iclass 33, count 0 2006.225.08:01:59.57#ibcon#read 3, iclass 33, count 0 2006.225.08:01:59.57#ibcon#about to read 4, iclass 33, count 0 2006.225.08:01:59.57#ibcon#read 4, iclass 33, count 0 2006.225.08:01:59.57#ibcon#about to read 5, iclass 33, count 0 2006.225.08:01:59.57#ibcon#read 5, iclass 33, count 0 2006.225.08:01:59.57#ibcon#about to read 6, iclass 33, count 0 2006.225.08:01:59.57#ibcon#read 6, iclass 33, count 0 2006.225.08:01:59.57#ibcon#end of sib2, iclass 33, count 0 2006.225.08:01:59.57#ibcon#*after write, iclass 33, count 0 2006.225.08:01:59.57#ibcon#*before return 0, iclass 33, count 0 2006.225.08:01:59.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:01:59.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:01:59.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:01:59.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:01:59.57$vc4f8/va=6,6 2006.225.08:01:59.57#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.08:01:59.57#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.08:01:59.57#ibcon#ireg 11 cls_cnt 2 2006.225.08:01:59.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:01:59.63#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:01:59.63#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:01:59.63#ibcon#enter wrdev, iclass 35, count 2 2006.225.08:01:59.63#ibcon#first serial, iclass 35, count 2 2006.225.08:01:59.63#ibcon#enter sib2, iclass 35, count 2 2006.225.08:01:59.63#ibcon#flushed, iclass 35, count 2 2006.225.08:01:59.63#ibcon#about to write, iclass 35, count 2 2006.225.08:01:59.63#ibcon#wrote, iclass 35, count 2 2006.225.08:01:59.63#ibcon#about to read 3, iclass 35, count 2 2006.225.08:01:59.65#ibcon#read 3, iclass 35, count 2 2006.225.08:01:59.65#ibcon#about to read 4, iclass 35, count 2 2006.225.08:01:59.65#ibcon#read 4, iclass 35, count 2 2006.225.08:01:59.65#ibcon#about to read 5, iclass 35, count 2 2006.225.08:01:59.65#ibcon#read 5, iclass 35, count 2 2006.225.08:01:59.65#ibcon#about to read 6, iclass 35, count 2 2006.225.08:01:59.65#ibcon#read 6, iclass 35, count 2 2006.225.08:01:59.65#ibcon#end of sib2, iclass 35, count 2 2006.225.08:01:59.65#ibcon#*mode == 0, iclass 35, count 2 2006.225.08:01:59.65#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.08:01:59.65#ibcon#[25=AT06-06\r\n] 2006.225.08:01:59.65#ibcon#*before write, iclass 35, count 2 2006.225.08:01:59.65#ibcon#enter sib2, iclass 35, count 2 2006.225.08:01:59.65#ibcon#flushed, iclass 35, count 2 2006.225.08:01:59.65#ibcon#about to write, iclass 35, count 2 2006.225.08:01:59.65#ibcon#wrote, iclass 35, count 2 2006.225.08:01:59.65#ibcon#about to read 3, iclass 35, count 2 2006.225.08:01:59.68#ibcon#read 3, iclass 35, count 2 2006.225.08:01:59.68#ibcon#about to read 4, iclass 35, count 2 2006.225.08:01:59.68#ibcon#read 4, iclass 35, count 2 2006.225.08:01:59.68#ibcon#about to read 5, iclass 35, count 2 2006.225.08:01:59.68#ibcon#read 5, iclass 35, count 2 2006.225.08:01:59.68#ibcon#about to read 6, iclass 35, count 2 2006.225.08:01:59.68#ibcon#read 6, iclass 35, count 2 2006.225.08:01:59.68#ibcon#end of sib2, iclass 35, count 2 2006.225.08:01:59.68#ibcon#*after write, iclass 35, count 2 2006.225.08:01:59.68#ibcon#*before return 0, iclass 35, count 2 2006.225.08:01:59.68#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:01:59.68#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:01:59.68#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.08:01:59.68#ibcon#ireg 7 cls_cnt 0 2006.225.08:01:59.68#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:01:59.80#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:01:59.80#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:01:59.80#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:01:59.80#ibcon#first serial, iclass 35, count 0 2006.225.08:01:59.80#ibcon#enter sib2, iclass 35, count 0 2006.225.08:01:59.80#ibcon#flushed, iclass 35, count 0 2006.225.08:01:59.80#ibcon#about to write, iclass 35, count 0 2006.225.08:01:59.80#ibcon#wrote, iclass 35, count 0 2006.225.08:01:59.80#ibcon#about to read 3, iclass 35, count 0 2006.225.08:01:59.82#ibcon#read 3, iclass 35, count 0 2006.225.08:01:59.82#ibcon#about to read 4, iclass 35, count 0 2006.225.08:01:59.82#ibcon#read 4, iclass 35, count 0 2006.225.08:01:59.82#ibcon#about to read 5, iclass 35, count 0 2006.225.08:01:59.82#ibcon#read 5, iclass 35, count 0 2006.225.08:01:59.82#ibcon#about to read 6, iclass 35, count 0 2006.225.08:01:59.82#ibcon#read 6, iclass 35, count 0 2006.225.08:01:59.82#ibcon#end of sib2, iclass 35, count 0 2006.225.08:01:59.82#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:01:59.82#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:01:59.82#ibcon#[25=USB\r\n] 2006.225.08:01:59.82#ibcon#*before write, iclass 35, count 0 2006.225.08:01:59.82#ibcon#enter sib2, iclass 35, count 0 2006.225.08:01:59.82#ibcon#flushed, iclass 35, count 0 2006.225.08:01:59.82#ibcon#about to write, iclass 35, count 0 2006.225.08:01:59.82#ibcon#wrote, iclass 35, count 0 2006.225.08:01:59.82#ibcon#about to read 3, iclass 35, count 0 2006.225.08:01:59.85#ibcon#read 3, iclass 35, count 0 2006.225.08:01:59.85#ibcon#about to read 4, iclass 35, count 0 2006.225.08:01:59.85#ibcon#read 4, iclass 35, count 0 2006.225.08:01:59.85#ibcon#about to read 5, iclass 35, count 0 2006.225.08:01:59.85#ibcon#read 5, iclass 35, count 0 2006.225.08:01:59.85#ibcon#about to read 6, iclass 35, count 0 2006.225.08:01:59.85#ibcon#read 6, iclass 35, count 0 2006.225.08:01:59.85#ibcon#end of sib2, iclass 35, count 0 2006.225.08:01:59.85#ibcon#*after write, iclass 35, count 0 2006.225.08:01:59.85#ibcon#*before return 0, iclass 35, count 0 2006.225.08:01:59.85#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:01:59.85#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:01:59.85#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:01:59.85#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:01:59.85$vc4f8/valo=7,832.99 2006.225.08:01:59.85#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.08:01:59.85#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.08:01:59.85#ibcon#ireg 17 cls_cnt 0 2006.225.08:01:59.85#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:01:59.85#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:01:59.85#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:01:59.85#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:01:59.85#ibcon#first serial, iclass 37, count 0 2006.225.08:01:59.85#ibcon#enter sib2, iclass 37, count 0 2006.225.08:01:59.85#ibcon#flushed, iclass 37, count 0 2006.225.08:01:59.85#ibcon#about to write, iclass 37, count 0 2006.225.08:01:59.85#ibcon#wrote, iclass 37, count 0 2006.225.08:01:59.85#ibcon#about to read 3, iclass 37, count 0 2006.225.08:01:59.87#ibcon#read 3, iclass 37, count 0 2006.225.08:01:59.87#ibcon#about to read 4, iclass 37, count 0 2006.225.08:01:59.87#ibcon#read 4, iclass 37, count 0 2006.225.08:01:59.87#ibcon#about to read 5, iclass 37, count 0 2006.225.08:01:59.87#ibcon#read 5, iclass 37, count 0 2006.225.08:01:59.87#ibcon#about to read 6, iclass 37, count 0 2006.225.08:01:59.87#ibcon#read 6, iclass 37, count 0 2006.225.08:01:59.87#ibcon#end of sib2, iclass 37, count 0 2006.225.08:01:59.87#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:01:59.87#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:01:59.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:01:59.87#ibcon#*before write, iclass 37, count 0 2006.225.08:01:59.87#ibcon#enter sib2, iclass 37, count 0 2006.225.08:01:59.87#ibcon#flushed, iclass 37, count 0 2006.225.08:01:59.87#ibcon#about to write, iclass 37, count 0 2006.225.08:01:59.87#ibcon#wrote, iclass 37, count 0 2006.225.08:01:59.87#ibcon#about to read 3, iclass 37, count 0 2006.225.08:01:59.91#ibcon#read 3, iclass 37, count 0 2006.225.08:01:59.91#ibcon#about to read 4, iclass 37, count 0 2006.225.08:01:59.91#ibcon#read 4, iclass 37, count 0 2006.225.08:01:59.91#ibcon#about to read 5, iclass 37, count 0 2006.225.08:01:59.91#ibcon#read 5, iclass 37, count 0 2006.225.08:01:59.91#ibcon#about to read 6, iclass 37, count 0 2006.225.08:01:59.91#ibcon#read 6, iclass 37, count 0 2006.225.08:01:59.91#ibcon#end of sib2, iclass 37, count 0 2006.225.08:01:59.91#ibcon#*after write, iclass 37, count 0 2006.225.08:01:59.91#ibcon#*before return 0, iclass 37, count 0 2006.225.08:01:59.91#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:01:59.91#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:01:59.91#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:01:59.91#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:01:59.91$vc4f8/va=7,6 2006.225.08:01:59.91#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.08:01:59.91#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.08:01:59.91#ibcon#ireg 11 cls_cnt 2 2006.225.08:01:59.91#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:01:59.97#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:01:59.97#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:01:59.97#ibcon#enter wrdev, iclass 39, count 2 2006.225.08:01:59.97#ibcon#first serial, iclass 39, count 2 2006.225.08:01:59.97#ibcon#enter sib2, iclass 39, count 2 2006.225.08:01:59.97#ibcon#flushed, iclass 39, count 2 2006.225.08:01:59.97#ibcon#about to write, iclass 39, count 2 2006.225.08:01:59.97#ibcon#wrote, iclass 39, count 2 2006.225.08:01:59.97#ibcon#about to read 3, iclass 39, count 2 2006.225.08:01:59.99#ibcon#read 3, iclass 39, count 2 2006.225.08:01:59.99#ibcon#about to read 4, iclass 39, count 2 2006.225.08:01:59.99#ibcon#read 4, iclass 39, count 2 2006.225.08:01:59.99#ibcon#about to read 5, iclass 39, count 2 2006.225.08:01:59.99#ibcon#read 5, iclass 39, count 2 2006.225.08:01:59.99#ibcon#about to read 6, iclass 39, count 2 2006.225.08:01:59.99#ibcon#read 6, iclass 39, count 2 2006.225.08:01:59.99#ibcon#end of sib2, iclass 39, count 2 2006.225.08:01:59.99#ibcon#*mode == 0, iclass 39, count 2 2006.225.08:01:59.99#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.08:01:59.99#ibcon#[25=AT07-06\r\n] 2006.225.08:01:59.99#ibcon#*before write, iclass 39, count 2 2006.225.08:01:59.99#ibcon#enter sib2, iclass 39, count 2 2006.225.08:01:59.99#ibcon#flushed, iclass 39, count 2 2006.225.08:01:59.99#ibcon#about to write, iclass 39, count 2 2006.225.08:01:59.99#ibcon#wrote, iclass 39, count 2 2006.225.08:01:59.99#ibcon#about to read 3, iclass 39, count 2 2006.225.08:02:00.02#ibcon#read 3, iclass 39, count 2 2006.225.08:02:00.02#ibcon#about to read 4, iclass 39, count 2 2006.225.08:02:00.02#ibcon#read 4, iclass 39, count 2 2006.225.08:02:00.02#ibcon#about to read 5, iclass 39, count 2 2006.225.08:02:00.02#ibcon#read 5, iclass 39, count 2 2006.225.08:02:00.02#ibcon#about to read 6, iclass 39, count 2 2006.225.08:02:00.02#ibcon#read 6, iclass 39, count 2 2006.225.08:02:00.02#ibcon#end of sib2, iclass 39, count 2 2006.225.08:02:00.02#ibcon#*after write, iclass 39, count 2 2006.225.08:02:00.02#ibcon#*before return 0, iclass 39, count 2 2006.225.08:02:00.02#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:02:00.02#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:02:00.02#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.08:02:00.02#ibcon#ireg 7 cls_cnt 0 2006.225.08:02:00.02#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:02:00.14#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:02:00.14#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:02:00.14#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:02:00.14#ibcon#first serial, iclass 39, count 0 2006.225.08:02:00.14#ibcon#enter sib2, iclass 39, count 0 2006.225.08:02:00.14#ibcon#flushed, iclass 39, count 0 2006.225.08:02:00.14#ibcon#about to write, iclass 39, count 0 2006.225.08:02:00.14#ibcon#wrote, iclass 39, count 0 2006.225.08:02:00.14#ibcon#about to read 3, iclass 39, count 0 2006.225.08:02:00.16#ibcon#read 3, iclass 39, count 0 2006.225.08:02:00.16#ibcon#about to read 4, iclass 39, count 0 2006.225.08:02:00.16#ibcon#read 4, iclass 39, count 0 2006.225.08:02:00.16#ibcon#about to read 5, iclass 39, count 0 2006.225.08:02:00.16#ibcon#read 5, iclass 39, count 0 2006.225.08:02:00.16#ibcon#about to read 6, iclass 39, count 0 2006.225.08:02:00.16#ibcon#read 6, iclass 39, count 0 2006.225.08:02:00.16#ibcon#end of sib2, iclass 39, count 0 2006.225.08:02:00.16#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:02:00.16#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:02:00.16#ibcon#[25=USB\r\n] 2006.225.08:02:00.16#ibcon#*before write, iclass 39, count 0 2006.225.08:02:00.16#ibcon#enter sib2, iclass 39, count 0 2006.225.08:02:00.16#ibcon#flushed, iclass 39, count 0 2006.225.08:02:00.16#ibcon#about to write, iclass 39, count 0 2006.225.08:02:00.16#ibcon#wrote, iclass 39, count 0 2006.225.08:02:00.16#ibcon#about to read 3, iclass 39, count 0 2006.225.08:02:00.19#ibcon#read 3, iclass 39, count 0 2006.225.08:02:00.19#ibcon#about to read 4, iclass 39, count 0 2006.225.08:02:00.19#ibcon#read 4, iclass 39, count 0 2006.225.08:02:00.19#ibcon#about to read 5, iclass 39, count 0 2006.225.08:02:00.19#ibcon#read 5, iclass 39, count 0 2006.225.08:02:00.19#ibcon#about to read 6, iclass 39, count 0 2006.225.08:02:00.19#ibcon#read 6, iclass 39, count 0 2006.225.08:02:00.19#ibcon#end of sib2, iclass 39, count 0 2006.225.08:02:00.19#ibcon#*after write, iclass 39, count 0 2006.225.08:02:00.19#ibcon#*before return 0, iclass 39, count 0 2006.225.08:02:00.19#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:02:00.19#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:02:00.19#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:02:00.19#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:02:00.19$vc4f8/valo=8,852.99 2006.225.08:02:00.19#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.08:02:00.19#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.08:02:00.19#ibcon#ireg 17 cls_cnt 0 2006.225.08:02:00.19#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:02:00.19#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:02:00.19#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:02:00.19#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:02:00.19#ibcon#first serial, iclass 3, count 0 2006.225.08:02:00.19#ibcon#enter sib2, iclass 3, count 0 2006.225.08:02:00.19#ibcon#flushed, iclass 3, count 0 2006.225.08:02:00.19#ibcon#about to write, iclass 3, count 0 2006.225.08:02:00.19#ibcon#wrote, iclass 3, count 0 2006.225.08:02:00.19#ibcon#about to read 3, iclass 3, count 0 2006.225.08:02:00.21#ibcon#read 3, iclass 3, count 0 2006.225.08:02:00.21#ibcon#about to read 4, iclass 3, count 0 2006.225.08:02:00.21#ibcon#read 4, iclass 3, count 0 2006.225.08:02:00.21#ibcon#about to read 5, iclass 3, count 0 2006.225.08:02:00.21#ibcon#read 5, iclass 3, count 0 2006.225.08:02:00.21#ibcon#about to read 6, iclass 3, count 0 2006.225.08:02:00.21#ibcon#read 6, iclass 3, count 0 2006.225.08:02:00.21#ibcon#end of sib2, iclass 3, count 0 2006.225.08:02:00.21#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:02:00.21#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:02:00.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:02:00.21#ibcon#*before write, iclass 3, count 0 2006.225.08:02:00.21#ibcon#enter sib2, iclass 3, count 0 2006.225.08:02:00.21#ibcon#flushed, iclass 3, count 0 2006.225.08:02:00.21#ibcon#about to write, iclass 3, count 0 2006.225.08:02:00.21#ibcon#wrote, iclass 3, count 0 2006.225.08:02:00.21#ibcon#about to read 3, iclass 3, count 0 2006.225.08:02:00.25#ibcon#read 3, iclass 3, count 0 2006.225.08:02:00.25#ibcon#about to read 4, iclass 3, count 0 2006.225.08:02:00.25#ibcon#read 4, iclass 3, count 0 2006.225.08:02:00.25#ibcon#about to read 5, iclass 3, count 0 2006.225.08:02:00.25#ibcon#read 5, iclass 3, count 0 2006.225.08:02:00.25#ibcon#about to read 6, iclass 3, count 0 2006.225.08:02:00.25#ibcon#read 6, iclass 3, count 0 2006.225.08:02:00.25#ibcon#end of sib2, iclass 3, count 0 2006.225.08:02:00.25#ibcon#*after write, iclass 3, count 0 2006.225.08:02:00.25#ibcon#*before return 0, iclass 3, count 0 2006.225.08:02:00.25#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:02:00.25#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:02:00.25#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:02:00.25#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:02:00.25$vc4f8/va=8,7 2006.225.08:02:00.25#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.08:02:00.25#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.08:02:00.25#ibcon#ireg 11 cls_cnt 2 2006.225.08:02:00.25#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:02:00.31#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:02:00.31#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:02:00.31#ibcon#enter wrdev, iclass 5, count 2 2006.225.08:02:00.31#ibcon#first serial, iclass 5, count 2 2006.225.08:02:00.31#ibcon#enter sib2, iclass 5, count 2 2006.225.08:02:00.31#ibcon#flushed, iclass 5, count 2 2006.225.08:02:00.31#ibcon#about to write, iclass 5, count 2 2006.225.08:02:00.31#ibcon#wrote, iclass 5, count 2 2006.225.08:02:00.31#ibcon#about to read 3, iclass 5, count 2 2006.225.08:02:00.33#ibcon#read 3, iclass 5, count 2 2006.225.08:02:00.33#ibcon#about to read 4, iclass 5, count 2 2006.225.08:02:00.33#ibcon#read 4, iclass 5, count 2 2006.225.08:02:00.33#ibcon#about to read 5, iclass 5, count 2 2006.225.08:02:00.33#ibcon#read 5, iclass 5, count 2 2006.225.08:02:00.33#ibcon#about to read 6, iclass 5, count 2 2006.225.08:02:00.33#ibcon#read 6, iclass 5, count 2 2006.225.08:02:00.33#ibcon#end of sib2, iclass 5, count 2 2006.225.08:02:00.33#ibcon#*mode == 0, iclass 5, count 2 2006.225.08:02:00.33#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.08:02:00.33#ibcon#[25=AT08-07\r\n] 2006.225.08:02:00.33#ibcon#*before write, iclass 5, count 2 2006.225.08:02:00.33#ibcon#enter sib2, iclass 5, count 2 2006.225.08:02:00.33#ibcon#flushed, iclass 5, count 2 2006.225.08:02:00.33#ibcon#about to write, iclass 5, count 2 2006.225.08:02:00.33#ibcon#wrote, iclass 5, count 2 2006.225.08:02:00.33#ibcon#about to read 3, iclass 5, count 2 2006.225.08:02:00.36#ibcon#read 3, iclass 5, count 2 2006.225.08:02:00.36#ibcon#about to read 4, iclass 5, count 2 2006.225.08:02:00.36#ibcon#read 4, iclass 5, count 2 2006.225.08:02:00.36#ibcon#about to read 5, iclass 5, count 2 2006.225.08:02:00.36#ibcon#read 5, iclass 5, count 2 2006.225.08:02:00.36#ibcon#about to read 6, iclass 5, count 2 2006.225.08:02:00.36#ibcon#read 6, iclass 5, count 2 2006.225.08:02:00.36#ibcon#end of sib2, iclass 5, count 2 2006.225.08:02:00.36#ibcon#*after write, iclass 5, count 2 2006.225.08:02:00.36#ibcon#*before return 0, iclass 5, count 2 2006.225.08:02:00.36#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:02:00.36#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:02:00.36#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.08:02:00.36#ibcon#ireg 7 cls_cnt 0 2006.225.08:02:00.36#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:02:00.39#abcon#<5=/05 2.9 5.2 28.30 701003.5\r\n> 2006.225.08:02:00.41#abcon#{5=INTERFACE CLEAR} 2006.225.08:02:00.47#abcon#[5=S1D000X0/0*\r\n] 2006.225.08:02:00.48#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:02:00.48#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:02:00.48#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:02:00.48#ibcon#first serial, iclass 5, count 0 2006.225.08:02:00.48#ibcon#enter sib2, iclass 5, count 0 2006.225.08:02:00.48#ibcon#flushed, iclass 5, count 0 2006.225.08:02:00.48#ibcon#about to write, iclass 5, count 0 2006.225.08:02:00.48#ibcon#wrote, iclass 5, count 0 2006.225.08:02:00.48#ibcon#about to read 3, iclass 5, count 0 2006.225.08:02:00.50#ibcon#read 3, iclass 5, count 0 2006.225.08:02:00.50#ibcon#about to read 4, iclass 5, count 0 2006.225.08:02:00.50#ibcon#read 4, iclass 5, count 0 2006.225.08:02:00.50#ibcon#about to read 5, iclass 5, count 0 2006.225.08:02:00.50#ibcon#read 5, iclass 5, count 0 2006.225.08:02:00.50#ibcon#about to read 6, iclass 5, count 0 2006.225.08:02:00.50#ibcon#read 6, iclass 5, count 0 2006.225.08:02:00.50#ibcon#end of sib2, iclass 5, count 0 2006.225.08:02:00.50#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:02:00.50#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:02:00.50#ibcon#[25=USB\r\n] 2006.225.08:02:00.50#ibcon#*before write, iclass 5, count 0 2006.225.08:02:00.50#ibcon#enter sib2, iclass 5, count 0 2006.225.08:02:00.50#ibcon#flushed, iclass 5, count 0 2006.225.08:02:00.50#ibcon#about to write, iclass 5, count 0 2006.225.08:02:00.50#ibcon#wrote, iclass 5, count 0 2006.225.08:02:00.50#ibcon#about to read 3, iclass 5, count 0 2006.225.08:02:00.53#ibcon#read 3, iclass 5, count 0 2006.225.08:02:00.53#ibcon#about to read 4, iclass 5, count 0 2006.225.08:02:00.53#ibcon#read 4, iclass 5, count 0 2006.225.08:02:00.53#ibcon#about to read 5, iclass 5, count 0 2006.225.08:02:00.53#ibcon#read 5, iclass 5, count 0 2006.225.08:02:00.53#ibcon#about to read 6, iclass 5, count 0 2006.225.08:02:00.53#ibcon#read 6, iclass 5, count 0 2006.225.08:02:00.53#ibcon#end of sib2, iclass 5, count 0 2006.225.08:02:00.53#ibcon#*after write, iclass 5, count 0 2006.225.08:02:00.53#ibcon#*before return 0, iclass 5, count 0 2006.225.08:02:00.53#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:02:00.53#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:02:00.53#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:02:00.53#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:02:00.53$vc4f8/vblo=1,632.99 2006.225.08:02:00.53#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.08:02:00.53#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.08:02:00.53#ibcon#ireg 17 cls_cnt 0 2006.225.08:02:00.53#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:02:00.53#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:02:00.53#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:02:00.53#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:02:00.53#ibcon#first serial, iclass 13, count 0 2006.225.08:02:00.53#ibcon#enter sib2, iclass 13, count 0 2006.225.08:02:00.53#ibcon#flushed, iclass 13, count 0 2006.225.08:02:00.53#ibcon#about to write, iclass 13, count 0 2006.225.08:02:00.53#ibcon#wrote, iclass 13, count 0 2006.225.08:02:00.53#ibcon#about to read 3, iclass 13, count 0 2006.225.08:02:00.55#ibcon#read 3, iclass 13, count 0 2006.225.08:02:00.55#ibcon#about to read 4, iclass 13, count 0 2006.225.08:02:00.55#ibcon#read 4, iclass 13, count 0 2006.225.08:02:00.55#ibcon#about to read 5, iclass 13, count 0 2006.225.08:02:00.55#ibcon#read 5, iclass 13, count 0 2006.225.08:02:00.55#ibcon#about to read 6, iclass 13, count 0 2006.225.08:02:00.55#ibcon#read 6, iclass 13, count 0 2006.225.08:02:00.55#ibcon#end of sib2, iclass 13, count 0 2006.225.08:02:00.55#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:02:00.55#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:02:00.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:02:00.55#ibcon#*before write, iclass 13, count 0 2006.225.08:02:00.55#ibcon#enter sib2, iclass 13, count 0 2006.225.08:02:00.55#ibcon#flushed, iclass 13, count 0 2006.225.08:02:00.55#ibcon#about to write, iclass 13, count 0 2006.225.08:02:00.55#ibcon#wrote, iclass 13, count 0 2006.225.08:02:00.55#ibcon#about to read 3, iclass 13, count 0 2006.225.08:02:00.59#ibcon#read 3, iclass 13, count 0 2006.225.08:02:00.59#ibcon#about to read 4, iclass 13, count 0 2006.225.08:02:00.59#ibcon#read 4, iclass 13, count 0 2006.225.08:02:00.59#ibcon#about to read 5, iclass 13, count 0 2006.225.08:02:00.59#ibcon#read 5, iclass 13, count 0 2006.225.08:02:00.59#ibcon#about to read 6, iclass 13, count 0 2006.225.08:02:00.59#ibcon#read 6, iclass 13, count 0 2006.225.08:02:00.59#ibcon#end of sib2, iclass 13, count 0 2006.225.08:02:00.59#ibcon#*after write, iclass 13, count 0 2006.225.08:02:00.59#ibcon#*before return 0, iclass 13, count 0 2006.225.08:02:00.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:02:00.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:02:00.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:02:00.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:02:00.59$vc4f8/vb=1,4 2006.225.08:02:00.59#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.225.08:02:00.59#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.225.08:02:00.59#ibcon#ireg 11 cls_cnt 2 2006.225.08:02:00.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:02:00.59#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:02:00.59#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:02:00.59#ibcon#enter wrdev, iclass 15, count 2 2006.225.08:02:00.59#ibcon#first serial, iclass 15, count 2 2006.225.08:02:00.59#ibcon#enter sib2, iclass 15, count 2 2006.225.08:02:00.59#ibcon#flushed, iclass 15, count 2 2006.225.08:02:00.59#ibcon#about to write, iclass 15, count 2 2006.225.08:02:00.59#ibcon#wrote, iclass 15, count 2 2006.225.08:02:00.59#ibcon#about to read 3, iclass 15, count 2 2006.225.08:02:00.61#ibcon#read 3, iclass 15, count 2 2006.225.08:02:00.61#ibcon#about to read 4, iclass 15, count 2 2006.225.08:02:00.61#ibcon#read 4, iclass 15, count 2 2006.225.08:02:00.61#ibcon#about to read 5, iclass 15, count 2 2006.225.08:02:00.61#ibcon#read 5, iclass 15, count 2 2006.225.08:02:00.61#ibcon#about to read 6, iclass 15, count 2 2006.225.08:02:00.61#ibcon#read 6, iclass 15, count 2 2006.225.08:02:00.61#ibcon#end of sib2, iclass 15, count 2 2006.225.08:02:00.61#ibcon#*mode == 0, iclass 15, count 2 2006.225.08:02:00.61#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.225.08:02:00.61#ibcon#[27=AT01-04\r\n] 2006.225.08:02:00.61#ibcon#*before write, iclass 15, count 2 2006.225.08:02:00.61#ibcon#enter sib2, iclass 15, count 2 2006.225.08:02:00.61#ibcon#flushed, iclass 15, count 2 2006.225.08:02:00.61#ibcon#about to write, iclass 15, count 2 2006.225.08:02:00.61#ibcon#wrote, iclass 15, count 2 2006.225.08:02:00.61#ibcon#about to read 3, iclass 15, count 2 2006.225.08:02:00.64#ibcon#read 3, iclass 15, count 2 2006.225.08:02:00.64#ibcon#about to read 4, iclass 15, count 2 2006.225.08:02:00.64#ibcon#read 4, iclass 15, count 2 2006.225.08:02:00.64#ibcon#about to read 5, iclass 15, count 2 2006.225.08:02:00.64#ibcon#read 5, iclass 15, count 2 2006.225.08:02:00.64#ibcon#about to read 6, iclass 15, count 2 2006.225.08:02:00.64#ibcon#read 6, iclass 15, count 2 2006.225.08:02:00.64#ibcon#end of sib2, iclass 15, count 2 2006.225.08:02:00.64#ibcon#*after write, iclass 15, count 2 2006.225.08:02:00.64#ibcon#*before return 0, iclass 15, count 2 2006.225.08:02:00.64#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:02:00.64#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:02:00.64#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.225.08:02:00.64#ibcon#ireg 7 cls_cnt 0 2006.225.08:02:00.64#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:02:00.76#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:02:00.76#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:02:00.76#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:02:00.76#ibcon#first serial, iclass 15, count 0 2006.225.08:02:00.76#ibcon#enter sib2, iclass 15, count 0 2006.225.08:02:00.76#ibcon#flushed, iclass 15, count 0 2006.225.08:02:00.76#ibcon#about to write, iclass 15, count 0 2006.225.08:02:00.76#ibcon#wrote, iclass 15, count 0 2006.225.08:02:00.76#ibcon#about to read 3, iclass 15, count 0 2006.225.08:02:00.78#ibcon#read 3, iclass 15, count 0 2006.225.08:02:00.78#ibcon#about to read 4, iclass 15, count 0 2006.225.08:02:00.78#ibcon#read 4, iclass 15, count 0 2006.225.08:02:00.78#ibcon#about to read 5, iclass 15, count 0 2006.225.08:02:00.78#ibcon#read 5, iclass 15, count 0 2006.225.08:02:00.78#ibcon#about to read 6, iclass 15, count 0 2006.225.08:02:00.78#ibcon#read 6, iclass 15, count 0 2006.225.08:02:00.78#ibcon#end of sib2, iclass 15, count 0 2006.225.08:02:00.78#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:02:00.78#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:02:00.78#ibcon#[27=USB\r\n] 2006.225.08:02:00.78#ibcon#*before write, iclass 15, count 0 2006.225.08:02:00.78#ibcon#enter sib2, iclass 15, count 0 2006.225.08:02:00.78#ibcon#flushed, iclass 15, count 0 2006.225.08:02:00.78#ibcon#about to write, iclass 15, count 0 2006.225.08:02:00.78#ibcon#wrote, iclass 15, count 0 2006.225.08:02:00.78#ibcon#about to read 3, iclass 15, count 0 2006.225.08:02:00.81#ibcon#read 3, iclass 15, count 0 2006.225.08:02:00.81#ibcon#about to read 4, iclass 15, count 0 2006.225.08:02:00.81#ibcon#read 4, iclass 15, count 0 2006.225.08:02:00.81#ibcon#about to read 5, iclass 15, count 0 2006.225.08:02:00.81#ibcon#read 5, iclass 15, count 0 2006.225.08:02:00.81#ibcon#about to read 6, iclass 15, count 0 2006.225.08:02:00.81#ibcon#read 6, iclass 15, count 0 2006.225.08:02:00.81#ibcon#end of sib2, iclass 15, count 0 2006.225.08:02:00.81#ibcon#*after write, iclass 15, count 0 2006.225.08:02:00.81#ibcon#*before return 0, iclass 15, count 0 2006.225.08:02:00.81#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:02:00.81#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:02:00.81#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:02:00.81#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:02:00.81$vc4f8/vblo=2,640.99 2006.225.08:02:00.81#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.225.08:02:00.81#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.225.08:02:00.81#ibcon#ireg 17 cls_cnt 0 2006.225.08:02:00.81#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:02:00.81#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:02:00.81#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:02:00.81#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:02:00.81#ibcon#first serial, iclass 17, count 0 2006.225.08:02:00.81#ibcon#enter sib2, iclass 17, count 0 2006.225.08:02:00.81#ibcon#flushed, iclass 17, count 0 2006.225.08:02:00.81#ibcon#about to write, iclass 17, count 0 2006.225.08:02:00.81#ibcon#wrote, iclass 17, count 0 2006.225.08:02:00.81#ibcon#about to read 3, iclass 17, count 0 2006.225.08:02:00.83#ibcon#read 3, iclass 17, count 0 2006.225.08:02:00.83#ibcon#about to read 4, iclass 17, count 0 2006.225.08:02:00.83#ibcon#read 4, iclass 17, count 0 2006.225.08:02:00.83#ibcon#about to read 5, iclass 17, count 0 2006.225.08:02:00.83#ibcon#read 5, iclass 17, count 0 2006.225.08:02:00.83#ibcon#about to read 6, iclass 17, count 0 2006.225.08:02:00.83#ibcon#read 6, iclass 17, count 0 2006.225.08:02:00.83#ibcon#end of sib2, iclass 17, count 0 2006.225.08:02:00.83#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:02:00.83#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:02:00.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:02:00.83#ibcon#*before write, iclass 17, count 0 2006.225.08:02:00.83#ibcon#enter sib2, iclass 17, count 0 2006.225.08:02:00.83#ibcon#flushed, iclass 17, count 0 2006.225.08:02:00.83#ibcon#about to write, iclass 17, count 0 2006.225.08:02:00.83#ibcon#wrote, iclass 17, count 0 2006.225.08:02:00.83#ibcon#about to read 3, iclass 17, count 0 2006.225.08:02:00.87#ibcon#read 3, iclass 17, count 0 2006.225.08:02:00.87#ibcon#about to read 4, iclass 17, count 0 2006.225.08:02:00.87#ibcon#read 4, iclass 17, count 0 2006.225.08:02:00.87#ibcon#about to read 5, iclass 17, count 0 2006.225.08:02:00.87#ibcon#read 5, iclass 17, count 0 2006.225.08:02:00.87#ibcon#about to read 6, iclass 17, count 0 2006.225.08:02:00.87#ibcon#read 6, iclass 17, count 0 2006.225.08:02:00.87#ibcon#end of sib2, iclass 17, count 0 2006.225.08:02:00.87#ibcon#*after write, iclass 17, count 0 2006.225.08:02:00.87#ibcon#*before return 0, iclass 17, count 0 2006.225.08:02:00.87#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:02:00.87#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:02:00.87#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:02:00.87#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:02:00.87$vc4f8/vb=2,4 2006.225.08:02:00.87#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.225.08:02:00.87#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.225.08:02:00.87#ibcon#ireg 11 cls_cnt 2 2006.225.08:02:00.87#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:02:00.93#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:02:00.93#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:02:00.93#ibcon#enter wrdev, iclass 19, count 2 2006.225.08:02:00.93#ibcon#first serial, iclass 19, count 2 2006.225.08:02:00.93#ibcon#enter sib2, iclass 19, count 2 2006.225.08:02:00.93#ibcon#flushed, iclass 19, count 2 2006.225.08:02:00.93#ibcon#about to write, iclass 19, count 2 2006.225.08:02:00.93#ibcon#wrote, iclass 19, count 2 2006.225.08:02:00.93#ibcon#about to read 3, iclass 19, count 2 2006.225.08:02:00.95#ibcon#read 3, iclass 19, count 2 2006.225.08:02:00.95#ibcon#about to read 4, iclass 19, count 2 2006.225.08:02:00.95#ibcon#read 4, iclass 19, count 2 2006.225.08:02:00.95#ibcon#about to read 5, iclass 19, count 2 2006.225.08:02:00.95#ibcon#read 5, iclass 19, count 2 2006.225.08:02:00.95#ibcon#about to read 6, iclass 19, count 2 2006.225.08:02:00.95#ibcon#read 6, iclass 19, count 2 2006.225.08:02:00.95#ibcon#end of sib2, iclass 19, count 2 2006.225.08:02:00.95#ibcon#*mode == 0, iclass 19, count 2 2006.225.08:02:00.95#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.225.08:02:00.95#ibcon#[27=AT02-04\r\n] 2006.225.08:02:00.95#ibcon#*before write, iclass 19, count 2 2006.225.08:02:00.95#ibcon#enter sib2, iclass 19, count 2 2006.225.08:02:00.95#ibcon#flushed, iclass 19, count 2 2006.225.08:02:00.95#ibcon#about to write, iclass 19, count 2 2006.225.08:02:00.95#ibcon#wrote, iclass 19, count 2 2006.225.08:02:00.95#ibcon#about to read 3, iclass 19, count 2 2006.225.08:02:00.98#ibcon#read 3, iclass 19, count 2 2006.225.08:02:00.98#ibcon#about to read 4, iclass 19, count 2 2006.225.08:02:00.98#ibcon#read 4, iclass 19, count 2 2006.225.08:02:00.98#ibcon#about to read 5, iclass 19, count 2 2006.225.08:02:00.98#ibcon#read 5, iclass 19, count 2 2006.225.08:02:00.98#ibcon#about to read 6, iclass 19, count 2 2006.225.08:02:00.98#ibcon#read 6, iclass 19, count 2 2006.225.08:02:00.98#ibcon#end of sib2, iclass 19, count 2 2006.225.08:02:00.98#ibcon#*after write, iclass 19, count 2 2006.225.08:02:00.98#ibcon#*before return 0, iclass 19, count 2 2006.225.08:02:00.98#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:02:00.98#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:02:00.98#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.225.08:02:00.98#ibcon#ireg 7 cls_cnt 0 2006.225.08:02:00.98#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:02:01.10#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:02:01.10#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:02:01.10#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:02:01.10#ibcon#first serial, iclass 19, count 0 2006.225.08:02:01.10#ibcon#enter sib2, iclass 19, count 0 2006.225.08:02:01.10#ibcon#flushed, iclass 19, count 0 2006.225.08:02:01.10#ibcon#about to write, iclass 19, count 0 2006.225.08:02:01.10#ibcon#wrote, iclass 19, count 0 2006.225.08:02:01.10#ibcon#about to read 3, iclass 19, count 0 2006.225.08:02:01.12#ibcon#read 3, iclass 19, count 0 2006.225.08:02:01.12#ibcon#about to read 4, iclass 19, count 0 2006.225.08:02:01.12#ibcon#read 4, iclass 19, count 0 2006.225.08:02:01.12#ibcon#about to read 5, iclass 19, count 0 2006.225.08:02:01.12#ibcon#read 5, iclass 19, count 0 2006.225.08:02:01.12#ibcon#about to read 6, iclass 19, count 0 2006.225.08:02:01.12#ibcon#read 6, iclass 19, count 0 2006.225.08:02:01.12#ibcon#end of sib2, iclass 19, count 0 2006.225.08:02:01.12#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:02:01.12#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:02:01.12#ibcon#[27=USB\r\n] 2006.225.08:02:01.12#ibcon#*before write, iclass 19, count 0 2006.225.08:02:01.12#ibcon#enter sib2, iclass 19, count 0 2006.225.08:02:01.12#ibcon#flushed, iclass 19, count 0 2006.225.08:02:01.12#ibcon#about to write, iclass 19, count 0 2006.225.08:02:01.12#ibcon#wrote, iclass 19, count 0 2006.225.08:02:01.12#ibcon#about to read 3, iclass 19, count 0 2006.225.08:02:01.15#ibcon#read 3, iclass 19, count 0 2006.225.08:02:01.15#ibcon#about to read 4, iclass 19, count 0 2006.225.08:02:01.15#ibcon#read 4, iclass 19, count 0 2006.225.08:02:01.15#ibcon#about to read 5, iclass 19, count 0 2006.225.08:02:01.15#ibcon#read 5, iclass 19, count 0 2006.225.08:02:01.15#ibcon#about to read 6, iclass 19, count 0 2006.225.08:02:01.15#ibcon#read 6, iclass 19, count 0 2006.225.08:02:01.15#ibcon#end of sib2, iclass 19, count 0 2006.225.08:02:01.15#ibcon#*after write, iclass 19, count 0 2006.225.08:02:01.15#ibcon#*before return 0, iclass 19, count 0 2006.225.08:02:01.15#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:02:01.15#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:02:01.15#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:02:01.15#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:02:01.15$vc4f8/vblo=3,656.99 2006.225.08:02:01.15#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.225.08:02:01.15#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.225.08:02:01.15#ibcon#ireg 17 cls_cnt 0 2006.225.08:02:01.15#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:02:01.15#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:02:01.15#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:02:01.15#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:02:01.15#ibcon#first serial, iclass 21, count 0 2006.225.08:02:01.15#ibcon#enter sib2, iclass 21, count 0 2006.225.08:02:01.15#ibcon#flushed, iclass 21, count 0 2006.225.08:02:01.15#ibcon#about to write, iclass 21, count 0 2006.225.08:02:01.15#ibcon#wrote, iclass 21, count 0 2006.225.08:02:01.15#ibcon#about to read 3, iclass 21, count 0 2006.225.08:02:01.17#ibcon#read 3, iclass 21, count 0 2006.225.08:02:01.17#ibcon#about to read 4, iclass 21, count 0 2006.225.08:02:01.17#ibcon#read 4, iclass 21, count 0 2006.225.08:02:01.17#ibcon#about to read 5, iclass 21, count 0 2006.225.08:02:01.17#ibcon#read 5, iclass 21, count 0 2006.225.08:02:01.17#ibcon#about to read 6, iclass 21, count 0 2006.225.08:02:01.17#ibcon#read 6, iclass 21, count 0 2006.225.08:02:01.17#ibcon#end of sib2, iclass 21, count 0 2006.225.08:02:01.17#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:02:01.17#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:02:01.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:02:01.17#ibcon#*before write, iclass 21, count 0 2006.225.08:02:01.17#ibcon#enter sib2, iclass 21, count 0 2006.225.08:02:01.17#ibcon#flushed, iclass 21, count 0 2006.225.08:02:01.17#ibcon#about to write, iclass 21, count 0 2006.225.08:02:01.17#ibcon#wrote, iclass 21, count 0 2006.225.08:02:01.17#ibcon#about to read 3, iclass 21, count 0 2006.225.08:02:01.21#ibcon#read 3, iclass 21, count 0 2006.225.08:02:01.21#ibcon#about to read 4, iclass 21, count 0 2006.225.08:02:01.21#ibcon#read 4, iclass 21, count 0 2006.225.08:02:01.21#ibcon#about to read 5, iclass 21, count 0 2006.225.08:02:01.21#ibcon#read 5, iclass 21, count 0 2006.225.08:02:01.21#ibcon#about to read 6, iclass 21, count 0 2006.225.08:02:01.21#ibcon#read 6, iclass 21, count 0 2006.225.08:02:01.21#ibcon#end of sib2, iclass 21, count 0 2006.225.08:02:01.21#ibcon#*after write, iclass 21, count 0 2006.225.08:02:01.21#ibcon#*before return 0, iclass 21, count 0 2006.225.08:02:01.21#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:02:01.21#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:02:01.21#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:02:01.21#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:02:01.21$vc4f8/vb=3,4 2006.225.08:02:01.21#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.225.08:02:01.21#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.225.08:02:01.21#ibcon#ireg 11 cls_cnt 2 2006.225.08:02:01.21#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:02:01.27#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:02:01.27#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:02:01.27#ibcon#enter wrdev, iclass 23, count 2 2006.225.08:02:01.27#ibcon#first serial, iclass 23, count 2 2006.225.08:02:01.27#ibcon#enter sib2, iclass 23, count 2 2006.225.08:02:01.27#ibcon#flushed, iclass 23, count 2 2006.225.08:02:01.27#ibcon#about to write, iclass 23, count 2 2006.225.08:02:01.27#ibcon#wrote, iclass 23, count 2 2006.225.08:02:01.27#ibcon#about to read 3, iclass 23, count 2 2006.225.08:02:01.29#ibcon#read 3, iclass 23, count 2 2006.225.08:02:01.29#ibcon#about to read 4, iclass 23, count 2 2006.225.08:02:01.29#ibcon#read 4, iclass 23, count 2 2006.225.08:02:01.29#ibcon#about to read 5, iclass 23, count 2 2006.225.08:02:01.29#ibcon#read 5, iclass 23, count 2 2006.225.08:02:01.29#ibcon#about to read 6, iclass 23, count 2 2006.225.08:02:01.29#ibcon#read 6, iclass 23, count 2 2006.225.08:02:01.29#ibcon#end of sib2, iclass 23, count 2 2006.225.08:02:01.29#ibcon#*mode == 0, iclass 23, count 2 2006.225.08:02:01.29#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.225.08:02:01.29#ibcon#[27=AT03-04\r\n] 2006.225.08:02:01.29#ibcon#*before write, iclass 23, count 2 2006.225.08:02:01.29#ibcon#enter sib2, iclass 23, count 2 2006.225.08:02:01.29#ibcon#flushed, iclass 23, count 2 2006.225.08:02:01.29#ibcon#about to write, iclass 23, count 2 2006.225.08:02:01.29#ibcon#wrote, iclass 23, count 2 2006.225.08:02:01.29#ibcon#about to read 3, iclass 23, count 2 2006.225.08:02:01.32#ibcon#read 3, iclass 23, count 2 2006.225.08:02:01.32#ibcon#about to read 4, iclass 23, count 2 2006.225.08:02:01.32#ibcon#read 4, iclass 23, count 2 2006.225.08:02:01.32#ibcon#about to read 5, iclass 23, count 2 2006.225.08:02:01.32#ibcon#read 5, iclass 23, count 2 2006.225.08:02:01.32#ibcon#about to read 6, iclass 23, count 2 2006.225.08:02:01.32#ibcon#read 6, iclass 23, count 2 2006.225.08:02:01.32#ibcon#end of sib2, iclass 23, count 2 2006.225.08:02:01.32#ibcon#*after write, iclass 23, count 2 2006.225.08:02:01.32#ibcon#*before return 0, iclass 23, count 2 2006.225.08:02:01.32#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:02:01.32#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:02:01.32#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.225.08:02:01.32#ibcon#ireg 7 cls_cnt 0 2006.225.08:02:01.32#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:02:01.44#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:02:01.44#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:02:01.44#ibcon#enter wrdev, iclass 23, count 0 2006.225.08:02:01.44#ibcon#first serial, iclass 23, count 0 2006.225.08:02:01.44#ibcon#enter sib2, iclass 23, count 0 2006.225.08:02:01.44#ibcon#flushed, iclass 23, count 0 2006.225.08:02:01.44#ibcon#about to write, iclass 23, count 0 2006.225.08:02:01.44#ibcon#wrote, iclass 23, count 0 2006.225.08:02:01.44#ibcon#about to read 3, iclass 23, count 0 2006.225.08:02:01.46#ibcon#read 3, iclass 23, count 0 2006.225.08:02:01.46#ibcon#about to read 4, iclass 23, count 0 2006.225.08:02:01.46#ibcon#read 4, iclass 23, count 0 2006.225.08:02:01.46#ibcon#about to read 5, iclass 23, count 0 2006.225.08:02:01.46#ibcon#read 5, iclass 23, count 0 2006.225.08:02:01.46#ibcon#about to read 6, iclass 23, count 0 2006.225.08:02:01.46#ibcon#read 6, iclass 23, count 0 2006.225.08:02:01.46#ibcon#end of sib2, iclass 23, count 0 2006.225.08:02:01.46#ibcon#*mode == 0, iclass 23, count 0 2006.225.08:02:01.46#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.08:02:01.46#ibcon#[27=USB\r\n] 2006.225.08:02:01.46#ibcon#*before write, iclass 23, count 0 2006.225.08:02:01.46#ibcon#enter sib2, iclass 23, count 0 2006.225.08:02:01.46#ibcon#flushed, iclass 23, count 0 2006.225.08:02:01.46#ibcon#about to write, iclass 23, count 0 2006.225.08:02:01.46#ibcon#wrote, iclass 23, count 0 2006.225.08:02:01.46#ibcon#about to read 3, iclass 23, count 0 2006.225.08:02:01.49#ibcon#read 3, iclass 23, count 0 2006.225.08:02:01.49#ibcon#about to read 4, iclass 23, count 0 2006.225.08:02:01.49#ibcon#read 4, iclass 23, count 0 2006.225.08:02:01.49#ibcon#about to read 5, iclass 23, count 0 2006.225.08:02:01.49#ibcon#read 5, iclass 23, count 0 2006.225.08:02:01.49#ibcon#about to read 6, iclass 23, count 0 2006.225.08:02:01.49#ibcon#read 6, iclass 23, count 0 2006.225.08:02:01.49#ibcon#end of sib2, iclass 23, count 0 2006.225.08:02:01.49#ibcon#*after write, iclass 23, count 0 2006.225.08:02:01.49#ibcon#*before return 0, iclass 23, count 0 2006.225.08:02:01.49#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:02:01.49#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:02:01.49#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.08:02:01.49#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.08:02:01.49$vc4f8/vblo=4,712.99 2006.225.08:02:01.49#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.225.08:02:01.49#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.225.08:02:01.49#ibcon#ireg 17 cls_cnt 0 2006.225.08:02:01.49#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:02:01.49#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:02:01.49#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:02:01.49#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:02:01.49#ibcon#first serial, iclass 25, count 0 2006.225.08:02:01.49#ibcon#enter sib2, iclass 25, count 0 2006.225.08:02:01.49#ibcon#flushed, iclass 25, count 0 2006.225.08:02:01.49#ibcon#about to write, iclass 25, count 0 2006.225.08:02:01.49#ibcon#wrote, iclass 25, count 0 2006.225.08:02:01.49#ibcon#about to read 3, iclass 25, count 0 2006.225.08:02:01.51#ibcon#read 3, iclass 25, count 0 2006.225.08:02:01.51#ibcon#about to read 4, iclass 25, count 0 2006.225.08:02:01.51#ibcon#read 4, iclass 25, count 0 2006.225.08:02:01.51#ibcon#about to read 5, iclass 25, count 0 2006.225.08:02:01.51#ibcon#read 5, iclass 25, count 0 2006.225.08:02:01.51#ibcon#about to read 6, iclass 25, count 0 2006.225.08:02:01.51#ibcon#read 6, iclass 25, count 0 2006.225.08:02:01.51#ibcon#end of sib2, iclass 25, count 0 2006.225.08:02:01.51#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:02:01.51#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:02:01.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:02:01.51#ibcon#*before write, iclass 25, count 0 2006.225.08:02:01.51#ibcon#enter sib2, iclass 25, count 0 2006.225.08:02:01.51#ibcon#flushed, iclass 25, count 0 2006.225.08:02:01.51#ibcon#about to write, iclass 25, count 0 2006.225.08:02:01.51#ibcon#wrote, iclass 25, count 0 2006.225.08:02:01.51#ibcon#about to read 3, iclass 25, count 0 2006.225.08:02:01.55#ibcon#read 3, iclass 25, count 0 2006.225.08:02:01.55#ibcon#about to read 4, iclass 25, count 0 2006.225.08:02:01.55#ibcon#read 4, iclass 25, count 0 2006.225.08:02:01.55#ibcon#about to read 5, iclass 25, count 0 2006.225.08:02:01.55#ibcon#read 5, iclass 25, count 0 2006.225.08:02:01.55#ibcon#about to read 6, iclass 25, count 0 2006.225.08:02:01.55#ibcon#read 6, iclass 25, count 0 2006.225.08:02:01.55#ibcon#end of sib2, iclass 25, count 0 2006.225.08:02:01.55#ibcon#*after write, iclass 25, count 0 2006.225.08:02:01.55#ibcon#*before return 0, iclass 25, count 0 2006.225.08:02:01.55#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:02:01.55#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:02:01.55#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:02:01.55#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:02:01.55$vc4f8/vb=4,4 2006.225.08:02:01.55#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.225.08:02:01.55#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.225.08:02:01.55#ibcon#ireg 11 cls_cnt 2 2006.225.08:02:01.55#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:02:01.61#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:02:01.61#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:02:01.61#ibcon#enter wrdev, iclass 27, count 2 2006.225.08:02:01.61#ibcon#first serial, iclass 27, count 2 2006.225.08:02:01.61#ibcon#enter sib2, iclass 27, count 2 2006.225.08:02:01.61#ibcon#flushed, iclass 27, count 2 2006.225.08:02:01.61#ibcon#about to write, iclass 27, count 2 2006.225.08:02:01.61#ibcon#wrote, iclass 27, count 2 2006.225.08:02:01.61#ibcon#about to read 3, iclass 27, count 2 2006.225.08:02:01.63#ibcon#read 3, iclass 27, count 2 2006.225.08:02:01.63#ibcon#about to read 4, iclass 27, count 2 2006.225.08:02:01.63#ibcon#read 4, iclass 27, count 2 2006.225.08:02:01.63#ibcon#about to read 5, iclass 27, count 2 2006.225.08:02:01.63#ibcon#read 5, iclass 27, count 2 2006.225.08:02:01.63#ibcon#about to read 6, iclass 27, count 2 2006.225.08:02:01.63#ibcon#read 6, iclass 27, count 2 2006.225.08:02:01.63#ibcon#end of sib2, iclass 27, count 2 2006.225.08:02:01.63#ibcon#*mode == 0, iclass 27, count 2 2006.225.08:02:01.63#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.225.08:02:01.63#ibcon#[27=AT04-04\r\n] 2006.225.08:02:01.63#ibcon#*before write, iclass 27, count 2 2006.225.08:02:01.63#ibcon#enter sib2, iclass 27, count 2 2006.225.08:02:01.63#ibcon#flushed, iclass 27, count 2 2006.225.08:02:01.63#ibcon#about to write, iclass 27, count 2 2006.225.08:02:01.63#ibcon#wrote, iclass 27, count 2 2006.225.08:02:01.63#ibcon#about to read 3, iclass 27, count 2 2006.225.08:02:01.66#ibcon#read 3, iclass 27, count 2 2006.225.08:02:01.66#ibcon#about to read 4, iclass 27, count 2 2006.225.08:02:01.66#ibcon#read 4, iclass 27, count 2 2006.225.08:02:01.66#ibcon#about to read 5, iclass 27, count 2 2006.225.08:02:01.66#ibcon#read 5, iclass 27, count 2 2006.225.08:02:01.66#ibcon#about to read 6, iclass 27, count 2 2006.225.08:02:01.66#ibcon#read 6, iclass 27, count 2 2006.225.08:02:01.66#ibcon#end of sib2, iclass 27, count 2 2006.225.08:02:01.66#ibcon#*after write, iclass 27, count 2 2006.225.08:02:01.66#ibcon#*before return 0, iclass 27, count 2 2006.225.08:02:01.66#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:02:01.66#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:02:01.66#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.225.08:02:01.66#ibcon#ireg 7 cls_cnt 0 2006.225.08:02:01.66#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:02:01.78#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:02:01.78#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:02:01.78#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:02:01.78#ibcon#first serial, iclass 27, count 0 2006.225.08:02:01.78#ibcon#enter sib2, iclass 27, count 0 2006.225.08:02:01.78#ibcon#flushed, iclass 27, count 0 2006.225.08:02:01.78#ibcon#about to write, iclass 27, count 0 2006.225.08:02:01.78#ibcon#wrote, iclass 27, count 0 2006.225.08:02:01.78#ibcon#about to read 3, iclass 27, count 0 2006.225.08:02:01.80#ibcon#read 3, iclass 27, count 0 2006.225.08:02:01.80#ibcon#about to read 4, iclass 27, count 0 2006.225.08:02:01.80#ibcon#read 4, iclass 27, count 0 2006.225.08:02:01.80#ibcon#about to read 5, iclass 27, count 0 2006.225.08:02:01.80#ibcon#read 5, iclass 27, count 0 2006.225.08:02:01.80#ibcon#about to read 6, iclass 27, count 0 2006.225.08:02:01.80#ibcon#read 6, iclass 27, count 0 2006.225.08:02:01.80#ibcon#end of sib2, iclass 27, count 0 2006.225.08:02:01.80#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:02:01.80#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:02:01.80#ibcon#[27=USB\r\n] 2006.225.08:02:01.80#ibcon#*before write, iclass 27, count 0 2006.225.08:02:01.80#ibcon#enter sib2, iclass 27, count 0 2006.225.08:02:01.80#ibcon#flushed, iclass 27, count 0 2006.225.08:02:01.80#ibcon#about to write, iclass 27, count 0 2006.225.08:02:01.80#ibcon#wrote, iclass 27, count 0 2006.225.08:02:01.80#ibcon#about to read 3, iclass 27, count 0 2006.225.08:02:01.83#ibcon#read 3, iclass 27, count 0 2006.225.08:02:01.83#ibcon#about to read 4, iclass 27, count 0 2006.225.08:02:01.83#ibcon#read 4, iclass 27, count 0 2006.225.08:02:01.83#ibcon#about to read 5, iclass 27, count 0 2006.225.08:02:01.83#ibcon#read 5, iclass 27, count 0 2006.225.08:02:01.83#ibcon#about to read 6, iclass 27, count 0 2006.225.08:02:01.83#ibcon#read 6, iclass 27, count 0 2006.225.08:02:01.83#ibcon#end of sib2, iclass 27, count 0 2006.225.08:02:01.83#ibcon#*after write, iclass 27, count 0 2006.225.08:02:01.83#ibcon#*before return 0, iclass 27, count 0 2006.225.08:02:01.83#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:02:01.83#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:02:01.83#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:02:01.83#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:02:01.83$vc4f8/vblo=5,744.99 2006.225.08:02:01.83#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.08:02:01.83#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.08:02:01.83#ibcon#ireg 17 cls_cnt 0 2006.225.08:02:01.83#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:02:01.83#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:02:01.83#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:02:01.83#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:02:01.83#ibcon#first serial, iclass 29, count 0 2006.225.08:02:01.83#ibcon#enter sib2, iclass 29, count 0 2006.225.08:02:01.83#ibcon#flushed, iclass 29, count 0 2006.225.08:02:01.83#ibcon#about to write, iclass 29, count 0 2006.225.08:02:01.83#ibcon#wrote, iclass 29, count 0 2006.225.08:02:01.83#ibcon#about to read 3, iclass 29, count 0 2006.225.08:02:01.85#ibcon#read 3, iclass 29, count 0 2006.225.08:02:01.85#ibcon#about to read 4, iclass 29, count 0 2006.225.08:02:01.85#ibcon#read 4, iclass 29, count 0 2006.225.08:02:01.85#ibcon#about to read 5, iclass 29, count 0 2006.225.08:02:01.85#ibcon#read 5, iclass 29, count 0 2006.225.08:02:01.85#ibcon#about to read 6, iclass 29, count 0 2006.225.08:02:01.85#ibcon#read 6, iclass 29, count 0 2006.225.08:02:01.85#ibcon#end of sib2, iclass 29, count 0 2006.225.08:02:01.85#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:02:01.85#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:02:01.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:02:01.85#ibcon#*before write, iclass 29, count 0 2006.225.08:02:01.85#ibcon#enter sib2, iclass 29, count 0 2006.225.08:02:01.85#ibcon#flushed, iclass 29, count 0 2006.225.08:02:01.85#ibcon#about to write, iclass 29, count 0 2006.225.08:02:01.85#ibcon#wrote, iclass 29, count 0 2006.225.08:02:01.85#ibcon#about to read 3, iclass 29, count 0 2006.225.08:02:01.89#ibcon#read 3, iclass 29, count 0 2006.225.08:02:01.89#ibcon#about to read 4, iclass 29, count 0 2006.225.08:02:01.89#ibcon#read 4, iclass 29, count 0 2006.225.08:02:01.89#ibcon#about to read 5, iclass 29, count 0 2006.225.08:02:01.89#ibcon#read 5, iclass 29, count 0 2006.225.08:02:01.89#ibcon#about to read 6, iclass 29, count 0 2006.225.08:02:01.89#ibcon#read 6, iclass 29, count 0 2006.225.08:02:01.89#ibcon#end of sib2, iclass 29, count 0 2006.225.08:02:01.89#ibcon#*after write, iclass 29, count 0 2006.225.08:02:01.89#ibcon#*before return 0, iclass 29, count 0 2006.225.08:02:01.89#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:02:01.89#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:02:01.89#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:02:01.89#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:02:01.89$vc4f8/vb=5,4 2006.225.08:02:01.89#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.08:02:01.89#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.08:02:01.89#ibcon#ireg 11 cls_cnt 2 2006.225.08:02:01.89#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:02:01.95#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:02:01.95#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:02:01.95#ibcon#enter wrdev, iclass 31, count 2 2006.225.08:02:01.95#ibcon#first serial, iclass 31, count 2 2006.225.08:02:01.95#ibcon#enter sib2, iclass 31, count 2 2006.225.08:02:01.95#ibcon#flushed, iclass 31, count 2 2006.225.08:02:01.95#ibcon#about to write, iclass 31, count 2 2006.225.08:02:01.95#ibcon#wrote, iclass 31, count 2 2006.225.08:02:01.95#ibcon#about to read 3, iclass 31, count 2 2006.225.08:02:01.97#ibcon#read 3, iclass 31, count 2 2006.225.08:02:01.97#ibcon#about to read 4, iclass 31, count 2 2006.225.08:02:01.97#ibcon#read 4, iclass 31, count 2 2006.225.08:02:01.97#ibcon#about to read 5, iclass 31, count 2 2006.225.08:02:01.97#ibcon#read 5, iclass 31, count 2 2006.225.08:02:01.97#ibcon#about to read 6, iclass 31, count 2 2006.225.08:02:01.97#ibcon#read 6, iclass 31, count 2 2006.225.08:02:01.97#ibcon#end of sib2, iclass 31, count 2 2006.225.08:02:01.97#ibcon#*mode == 0, iclass 31, count 2 2006.225.08:02:01.97#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.08:02:01.97#ibcon#[27=AT05-04\r\n] 2006.225.08:02:01.97#ibcon#*before write, iclass 31, count 2 2006.225.08:02:01.97#ibcon#enter sib2, iclass 31, count 2 2006.225.08:02:01.97#ibcon#flushed, iclass 31, count 2 2006.225.08:02:01.97#ibcon#about to write, iclass 31, count 2 2006.225.08:02:01.97#ibcon#wrote, iclass 31, count 2 2006.225.08:02:01.97#ibcon#about to read 3, iclass 31, count 2 2006.225.08:02:02.00#ibcon#read 3, iclass 31, count 2 2006.225.08:02:02.00#ibcon#about to read 4, iclass 31, count 2 2006.225.08:02:02.00#ibcon#read 4, iclass 31, count 2 2006.225.08:02:02.00#ibcon#about to read 5, iclass 31, count 2 2006.225.08:02:02.00#ibcon#read 5, iclass 31, count 2 2006.225.08:02:02.00#ibcon#about to read 6, iclass 31, count 2 2006.225.08:02:02.00#ibcon#read 6, iclass 31, count 2 2006.225.08:02:02.00#ibcon#end of sib2, iclass 31, count 2 2006.225.08:02:02.00#ibcon#*after write, iclass 31, count 2 2006.225.08:02:02.00#ibcon#*before return 0, iclass 31, count 2 2006.225.08:02:02.00#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:02:02.00#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:02:02.00#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.08:02:02.00#ibcon#ireg 7 cls_cnt 0 2006.225.08:02:02.00#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:02:02.12#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:02:02.12#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:02:02.12#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:02:02.12#ibcon#first serial, iclass 31, count 0 2006.225.08:02:02.12#ibcon#enter sib2, iclass 31, count 0 2006.225.08:02:02.12#ibcon#flushed, iclass 31, count 0 2006.225.08:02:02.12#ibcon#about to write, iclass 31, count 0 2006.225.08:02:02.12#ibcon#wrote, iclass 31, count 0 2006.225.08:02:02.12#ibcon#about to read 3, iclass 31, count 0 2006.225.08:02:02.14#ibcon#read 3, iclass 31, count 0 2006.225.08:02:02.14#ibcon#about to read 4, iclass 31, count 0 2006.225.08:02:02.14#ibcon#read 4, iclass 31, count 0 2006.225.08:02:02.14#ibcon#about to read 5, iclass 31, count 0 2006.225.08:02:02.14#ibcon#read 5, iclass 31, count 0 2006.225.08:02:02.14#ibcon#about to read 6, iclass 31, count 0 2006.225.08:02:02.14#ibcon#read 6, iclass 31, count 0 2006.225.08:02:02.14#ibcon#end of sib2, iclass 31, count 0 2006.225.08:02:02.14#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:02:02.14#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:02:02.14#ibcon#[27=USB\r\n] 2006.225.08:02:02.14#ibcon#*before write, iclass 31, count 0 2006.225.08:02:02.14#ibcon#enter sib2, iclass 31, count 0 2006.225.08:02:02.14#ibcon#flushed, iclass 31, count 0 2006.225.08:02:02.14#ibcon#about to write, iclass 31, count 0 2006.225.08:02:02.14#ibcon#wrote, iclass 31, count 0 2006.225.08:02:02.14#ibcon#about to read 3, iclass 31, count 0 2006.225.08:02:02.17#ibcon#read 3, iclass 31, count 0 2006.225.08:02:02.17#ibcon#about to read 4, iclass 31, count 0 2006.225.08:02:02.17#ibcon#read 4, iclass 31, count 0 2006.225.08:02:02.17#ibcon#about to read 5, iclass 31, count 0 2006.225.08:02:02.17#ibcon#read 5, iclass 31, count 0 2006.225.08:02:02.17#ibcon#about to read 6, iclass 31, count 0 2006.225.08:02:02.17#ibcon#read 6, iclass 31, count 0 2006.225.08:02:02.17#ibcon#end of sib2, iclass 31, count 0 2006.225.08:02:02.17#ibcon#*after write, iclass 31, count 0 2006.225.08:02:02.17#ibcon#*before return 0, iclass 31, count 0 2006.225.08:02:02.17#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:02:02.17#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:02:02.17#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:02:02.17#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:02:02.17$vc4f8/vblo=6,752.99 2006.225.08:02:02.17#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.08:02:02.17#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.08:02:02.17#ibcon#ireg 17 cls_cnt 0 2006.225.08:02:02.17#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:02:02.17#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:02:02.17#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:02:02.17#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:02:02.17#ibcon#first serial, iclass 33, count 0 2006.225.08:02:02.17#ibcon#enter sib2, iclass 33, count 0 2006.225.08:02:02.17#ibcon#flushed, iclass 33, count 0 2006.225.08:02:02.17#ibcon#about to write, iclass 33, count 0 2006.225.08:02:02.17#ibcon#wrote, iclass 33, count 0 2006.225.08:02:02.17#ibcon#about to read 3, iclass 33, count 0 2006.225.08:02:02.19#ibcon#read 3, iclass 33, count 0 2006.225.08:02:02.19#ibcon#about to read 4, iclass 33, count 0 2006.225.08:02:02.19#ibcon#read 4, iclass 33, count 0 2006.225.08:02:02.19#ibcon#about to read 5, iclass 33, count 0 2006.225.08:02:02.19#ibcon#read 5, iclass 33, count 0 2006.225.08:02:02.19#ibcon#about to read 6, iclass 33, count 0 2006.225.08:02:02.19#ibcon#read 6, iclass 33, count 0 2006.225.08:02:02.19#ibcon#end of sib2, iclass 33, count 0 2006.225.08:02:02.19#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:02:02.19#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:02:02.19#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:02:02.19#ibcon#*before write, iclass 33, count 0 2006.225.08:02:02.19#ibcon#enter sib2, iclass 33, count 0 2006.225.08:02:02.19#ibcon#flushed, iclass 33, count 0 2006.225.08:02:02.19#ibcon#about to write, iclass 33, count 0 2006.225.08:02:02.19#ibcon#wrote, iclass 33, count 0 2006.225.08:02:02.19#ibcon#about to read 3, iclass 33, count 0 2006.225.08:02:02.23#ibcon#read 3, iclass 33, count 0 2006.225.08:02:02.23#ibcon#about to read 4, iclass 33, count 0 2006.225.08:02:02.23#ibcon#read 4, iclass 33, count 0 2006.225.08:02:02.23#ibcon#about to read 5, iclass 33, count 0 2006.225.08:02:02.23#ibcon#read 5, iclass 33, count 0 2006.225.08:02:02.23#ibcon#about to read 6, iclass 33, count 0 2006.225.08:02:02.23#ibcon#read 6, iclass 33, count 0 2006.225.08:02:02.23#ibcon#end of sib2, iclass 33, count 0 2006.225.08:02:02.23#ibcon#*after write, iclass 33, count 0 2006.225.08:02:02.23#ibcon#*before return 0, iclass 33, count 0 2006.225.08:02:02.23#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:02:02.23#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:02:02.23#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:02:02.23#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:02:02.23$vc4f8/vb=6,4 2006.225.08:02:02.23#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.08:02:02.23#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.08:02:02.23#ibcon#ireg 11 cls_cnt 2 2006.225.08:02:02.23#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:02:02.29#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:02:02.29#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:02:02.29#ibcon#enter wrdev, iclass 35, count 2 2006.225.08:02:02.29#ibcon#first serial, iclass 35, count 2 2006.225.08:02:02.29#ibcon#enter sib2, iclass 35, count 2 2006.225.08:02:02.29#ibcon#flushed, iclass 35, count 2 2006.225.08:02:02.29#ibcon#about to write, iclass 35, count 2 2006.225.08:02:02.29#ibcon#wrote, iclass 35, count 2 2006.225.08:02:02.29#ibcon#about to read 3, iclass 35, count 2 2006.225.08:02:02.31#ibcon#read 3, iclass 35, count 2 2006.225.08:02:02.31#ibcon#about to read 4, iclass 35, count 2 2006.225.08:02:02.31#ibcon#read 4, iclass 35, count 2 2006.225.08:02:02.31#ibcon#about to read 5, iclass 35, count 2 2006.225.08:02:02.31#ibcon#read 5, iclass 35, count 2 2006.225.08:02:02.31#ibcon#about to read 6, iclass 35, count 2 2006.225.08:02:02.31#ibcon#read 6, iclass 35, count 2 2006.225.08:02:02.31#ibcon#end of sib2, iclass 35, count 2 2006.225.08:02:02.31#ibcon#*mode == 0, iclass 35, count 2 2006.225.08:02:02.31#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.08:02:02.31#ibcon#[27=AT06-04\r\n] 2006.225.08:02:02.31#ibcon#*before write, iclass 35, count 2 2006.225.08:02:02.31#ibcon#enter sib2, iclass 35, count 2 2006.225.08:02:02.31#ibcon#flushed, iclass 35, count 2 2006.225.08:02:02.31#ibcon#about to write, iclass 35, count 2 2006.225.08:02:02.31#ibcon#wrote, iclass 35, count 2 2006.225.08:02:02.31#ibcon#about to read 3, iclass 35, count 2 2006.225.08:02:02.34#ibcon#read 3, iclass 35, count 2 2006.225.08:02:02.34#ibcon#about to read 4, iclass 35, count 2 2006.225.08:02:02.34#ibcon#read 4, iclass 35, count 2 2006.225.08:02:02.34#ibcon#about to read 5, iclass 35, count 2 2006.225.08:02:02.34#ibcon#read 5, iclass 35, count 2 2006.225.08:02:02.34#ibcon#about to read 6, iclass 35, count 2 2006.225.08:02:02.34#ibcon#read 6, iclass 35, count 2 2006.225.08:02:02.34#ibcon#end of sib2, iclass 35, count 2 2006.225.08:02:02.34#ibcon#*after write, iclass 35, count 2 2006.225.08:02:02.34#ibcon#*before return 0, iclass 35, count 2 2006.225.08:02:02.34#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:02:02.34#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:02:02.34#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.08:02:02.34#ibcon#ireg 7 cls_cnt 0 2006.225.08:02:02.34#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:02:02.46#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:02:02.46#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:02:02.46#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:02:02.46#ibcon#first serial, iclass 35, count 0 2006.225.08:02:02.46#ibcon#enter sib2, iclass 35, count 0 2006.225.08:02:02.46#ibcon#flushed, iclass 35, count 0 2006.225.08:02:02.46#ibcon#about to write, iclass 35, count 0 2006.225.08:02:02.46#ibcon#wrote, iclass 35, count 0 2006.225.08:02:02.46#ibcon#about to read 3, iclass 35, count 0 2006.225.08:02:02.48#ibcon#read 3, iclass 35, count 0 2006.225.08:02:02.48#ibcon#about to read 4, iclass 35, count 0 2006.225.08:02:02.48#ibcon#read 4, iclass 35, count 0 2006.225.08:02:02.48#ibcon#about to read 5, iclass 35, count 0 2006.225.08:02:02.48#ibcon#read 5, iclass 35, count 0 2006.225.08:02:02.48#ibcon#about to read 6, iclass 35, count 0 2006.225.08:02:02.48#ibcon#read 6, iclass 35, count 0 2006.225.08:02:02.48#ibcon#end of sib2, iclass 35, count 0 2006.225.08:02:02.48#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:02:02.48#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:02:02.48#ibcon#[27=USB\r\n] 2006.225.08:02:02.48#ibcon#*before write, iclass 35, count 0 2006.225.08:02:02.48#ibcon#enter sib2, iclass 35, count 0 2006.225.08:02:02.48#ibcon#flushed, iclass 35, count 0 2006.225.08:02:02.48#ibcon#about to write, iclass 35, count 0 2006.225.08:02:02.48#ibcon#wrote, iclass 35, count 0 2006.225.08:02:02.48#ibcon#about to read 3, iclass 35, count 0 2006.225.08:02:02.51#ibcon#read 3, iclass 35, count 0 2006.225.08:02:02.51#ibcon#about to read 4, iclass 35, count 0 2006.225.08:02:02.51#ibcon#read 4, iclass 35, count 0 2006.225.08:02:02.51#ibcon#about to read 5, iclass 35, count 0 2006.225.08:02:02.51#ibcon#read 5, iclass 35, count 0 2006.225.08:02:02.51#ibcon#about to read 6, iclass 35, count 0 2006.225.08:02:02.51#ibcon#read 6, iclass 35, count 0 2006.225.08:02:02.51#ibcon#end of sib2, iclass 35, count 0 2006.225.08:02:02.51#ibcon#*after write, iclass 35, count 0 2006.225.08:02:02.51#ibcon#*before return 0, iclass 35, count 0 2006.225.08:02:02.51#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:02:02.51#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:02:02.51#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:02:02.51#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:02:02.51$vc4f8/vabw=wide 2006.225.08:02:02.51#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.08:02:02.51#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.08:02:02.51#ibcon#ireg 8 cls_cnt 0 2006.225.08:02:02.51#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:02:02.51#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:02:02.51#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:02:02.51#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:02:02.51#ibcon#first serial, iclass 37, count 0 2006.225.08:02:02.51#ibcon#enter sib2, iclass 37, count 0 2006.225.08:02:02.51#ibcon#flushed, iclass 37, count 0 2006.225.08:02:02.51#ibcon#about to write, iclass 37, count 0 2006.225.08:02:02.51#ibcon#wrote, iclass 37, count 0 2006.225.08:02:02.51#ibcon#about to read 3, iclass 37, count 0 2006.225.08:02:02.53#ibcon#read 3, iclass 37, count 0 2006.225.08:02:02.53#ibcon#about to read 4, iclass 37, count 0 2006.225.08:02:02.53#ibcon#read 4, iclass 37, count 0 2006.225.08:02:02.53#ibcon#about to read 5, iclass 37, count 0 2006.225.08:02:02.53#ibcon#read 5, iclass 37, count 0 2006.225.08:02:02.53#ibcon#about to read 6, iclass 37, count 0 2006.225.08:02:02.53#ibcon#read 6, iclass 37, count 0 2006.225.08:02:02.53#ibcon#end of sib2, iclass 37, count 0 2006.225.08:02:02.53#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:02:02.53#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:02:02.53#ibcon#[25=BW32\r\n] 2006.225.08:02:02.53#ibcon#*before write, iclass 37, count 0 2006.225.08:02:02.53#ibcon#enter sib2, iclass 37, count 0 2006.225.08:02:02.53#ibcon#flushed, iclass 37, count 0 2006.225.08:02:02.53#ibcon#about to write, iclass 37, count 0 2006.225.08:02:02.53#ibcon#wrote, iclass 37, count 0 2006.225.08:02:02.53#ibcon#about to read 3, iclass 37, count 0 2006.225.08:02:02.56#ibcon#read 3, iclass 37, count 0 2006.225.08:02:02.56#ibcon#about to read 4, iclass 37, count 0 2006.225.08:02:02.56#ibcon#read 4, iclass 37, count 0 2006.225.08:02:02.56#ibcon#about to read 5, iclass 37, count 0 2006.225.08:02:02.56#ibcon#read 5, iclass 37, count 0 2006.225.08:02:02.56#ibcon#about to read 6, iclass 37, count 0 2006.225.08:02:02.56#ibcon#read 6, iclass 37, count 0 2006.225.08:02:02.56#ibcon#end of sib2, iclass 37, count 0 2006.225.08:02:02.56#ibcon#*after write, iclass 37, count 0 2006.225.08:02:02.56#ibcon#*before return 0, iclass 37, count 0 2006.225.08:02:02.56#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:02:02.56#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:02:02.56#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:02:02.56#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:02:02.56$vc4f8/vbbw=wide 2006.225.08:02:02.56#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.08:02:02.56#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.08:02:02.56#ibcon#ireg 8 cls_cnt 0 2006.225.08:02:02.56#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:02:02.63#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:02:02.63#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:02:02.63#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:02:02.63#ibcon#first serial, iclass 39, count 0 2006.225.08:02:02.63#ibcon#enter sib2, iclass 39, count 0 2006.225.08:02:02.63#ibcon#flushed, iclass 39, count 0 2006.225.08:02:02.63#ibcon#about to write, iclass 39, count 0 2006.225.08:02:02.63#ibcon#wrote, iclass 39, count 0 2006.225.08:02:02.63#ibcon#about to read 3, iclass 39, count 0 2006.225.08:02:02.65#ibcon#read 3, iclass 39, count 0 2006.225.08:02:02.65#ibcon#about to read 4, iclass 39, count 0 2006.225.08:02:02.65#ibcon#read 4, iclass 39, count 0 2006.225.08:02:02.65#ibcon#about to read 5, iclass 39, count 0 2006.225.08:02:02.65#ibcon#read 5, iclass 39, count 0 2006.225.08:02:02.65#ibcon#about to read 6, iclass 39, count 0 2006.225.08:02:02.65#ibcon#read 6, iclass 39, count 0 2006.225.08:02:02.65#ibcon#end of sib2, iclass 39, count 0 2006.225.08:02:02.65#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:02:02.65#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:02:02.65#ibcon#[27=BW32\r\n] 2006.225.08:02:02.65#ibcon#*before write, iclass 39, count 0 2006.225.08:02:02.65#ibcon#enter sib2, iclass 39, count 0 2006.225.08:02:02.65#ibcon#flushed, iclass 39, count 0 2006.225.08:02:02.65#ibcon#about to write, iclass 39, count 0 2006.225.08:02:02.65#ibcon#wrote, iclass 39, count 0 2006.225.08:02:02.65#ibcon#about to read 3, iclass 39, count 0 2006.225.08:02:02.68#ibcon#read 3, iclass 39, count 0 2006.225.08:02:02.68#ibcon#about to read 4, iclass 39, count 0 2006.225.08:02:02.68#ibcon#read 4, iclass 39, count 0 2006.225.08:02:02.68#ibcon#about to read 5, iclass 39, count 0 2006.225.08:02:02.68#ibcon#read 5, iclass 39, count 0 2006.225.08:02:02.68#ibcon#about to read 6, iclass 39, count 0 2006.225.08:02:02.68#ibcon#read 6, iclass 39, count 0 2006.225.08:02:02.68#ibcon#end of sib2, iclass 39, count 0 2006.225.08:02:02.68#ibcon#*after write, iclass 39, count 0 2006.225.08:02:02.68#ibcon#*before return 0, iclass 39, count 0 2006.225.08:02:02.68#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:02:02.68#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:02:02.68#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:02:02.68#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:02:02.68$4f8m12a/ifd4f 2006.225.08:02:02.68$ifd4f/lo= 2006.225.08:02:02.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:02:02.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:02:02.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:02:02.68$ifd4f/patch= 2006.225.08:02:02.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:02:02.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:02:02.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:02:02.68$4f8m12a/"form=m,16.000,1:2 2006.225.08:02:02.68$4f8m12a/"tpicd 2006.225.08:02:02.68$4f8m12a/echo=off 2006.225.08:02:02.68$4f8m12a/xlog=off 2006.225.08:02:02.68:!2006.225.08:02:30 2006.225.08:02:11.14#trakl#Source acquired 2006.225.08:02:12.14#flagr#flagr/antenna,acquired 2006.225.08:02:30.00:preob 2006.225.08:02:31.14/onsource/TRACKING 2006.225.08:02:31.14:!2006.225.08:02:40 2006.225.08:02:40.02:data_valid=on 2006.225.08:02:40.02:midob 2006.225.08:02:41.14/onsource/TRACKING 2006.225.08:02:41.14/wx/28.28,1003.5,70 2006.225.08:02:41.19/cable/+6.4056E-03 2006.225.08:02:42.27/va/01,08,usb,yes,30,31 2006.225.08:02:42.27/va/02,07,usb,yes,30,32 2006.225.08:02:42.27/va/03,06,usb,yes,32,32 2006.225.08:02:42.27/va/04,07,usb,yes,31,34 2006.225.08:02:42.27/va/05,07,usb,yes,34,36 2006.225.08:02:42.27/va/06,06,usb,yes,33,33 2006.225.08:02:42.27/va/07,06,usb,yes,34,33 2006.225.08:02:42.27/va/08,07,usb,yes,32,31 2006.225.08:02:42.50/valo/01,532.99,yes,locked 2006.225.08:02:42.50/valo/02,572.99,yes,locked 2006.225.08:02:42.50/valo/03,672.99,yes,locked 2006.225.08:02:42.50/valo/04,832.99,yes,locked 2006.225.08:02:42.50/valo/05,652.99,yes,locked 2006.225.08:02:42.50/valo/06,772.99,yes,locked 2006.225.08:02:42.50/valo/07,832.99,yes,locked 2006.225.08:02:42.50/valo/08,852.99,yes,locked 2006.225.08:02:43.59/vb/01,04,usb,yes,31,30 2006.225.08:02:43.59/vb/02,04,usb,yes,33,35 2006.225.08:02:43.59/vb/03,04,usb,yes,30,33 2006.225.08:02:43.59/vb/04,04,usb,yes,30,31 2006.225.08:02:43.59/vb/05,04,usb,yes,29,33 2006.225.08:02:43.59/vb/06,04,usb,yes,30,33 2006.225.08:02:43.59/vb/07,04,usb,yes,32,32 2006.225.08:02:43.59/vb/08,04,usb,yes,29,33 2006.225.08:02:43.83/vblo/01,632.99,yes,locked 2006.225.08:02:43.83/vblo/02,640.99,yes,locked 2006.225.08:02:43.83/vblo/03,656.99,yes,locked 2006.225.08:02:43.83/vblo/04,712.99,yes,locked 2006.225.08:02:43.83/vblo/05,744.99,yes,locked 2006.225.08:02:43.83/vblo/06,752.99,yes,locked 2006.225.08:02:43.83/vblo/07,734.99,yes,locked 2006.225.08:02:43.83/vblo/08,744.99,yes,locked 2006.225.08:02:43.98/vabw/8 2006.225.08:02:44.13/vbbw/8 2006.225.08:02:44.24/xfe/off,on,15.2 2006.225.08:02:44.61/ifatt/23,28,28,28 2006.225.08:02:45.08/fmout-gps/S +4.56E-07 2006.225.08:02:45.12:!2006.225.08:03:40 2006.225.08:03:40.02:data_valid=off 2006.225.08:03:40.02:postob 2006.225.08:03:40.22/cable/+6.4045E-03 2006.225.08:03:40.22/wx/28.25,1003.4,70 2006.225.08:03:40.28/fmout-gps/S +4.59E-07 2006.225.08:03:40.28:scan_name=225-0804,k06225,60 2006.225.08:03:40.28:source=1044+719,104827.62,714335.9,2000.0,ccw 2006.225.08:03:41.15#flagr#flagr/antenna,new-source 2006.225.08:03:41.15:checkk5 2006.225.08:03:41.53/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:03:41.90/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:03:42.28/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:03:42.64/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:03:43.01/chk_obsdata//k5ts1/T2250802??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:03:43.38/chk_obsdata//k5ts2/T2250802??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:03:43.74/chk_obsdata//k5ts3/T2250802??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:03:44.11/chk_obsdata//k5ts4/T2250802??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:03:44.80/k5log//k5ts1_log_newline 2006.225.08:03:45.48/k5log//k5ts2_log_newline 2006.225.08:03:46.16/k5log//k5ts3_log_newline 2006.225.08:03:46.85/k5log//k5ts4_log_newline 2006.225.08:03:46.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:03:46.87:4f8m12a=2 2006.225.08:03:46.87$4f8m12a/echo=on 2006.225.08:03:46.87$4f8m12a/pcalon 2006.225.08:03:46.87$pcalon/"no phase cal control is implemented here 2006.225.08:03:46.87$4f8m12a/"tpicd=stop 2006.225.08:03:46.87$4f8m12a/vc4f8 2006.225.08:03:46.87$vc4f8/valo=1,532.99 2006.225.08:03:46.88#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.08:03:46.88#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.08:03:46.88#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:46.88#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:03:46.88#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:03:46.88#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:03:46.88#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:03:46.88#ibcon#first serial, iclass 10, count 0 2006.225.08:03:46.88#ibcon#enter sib2, iclass 10, count 0 2006.225.08:03:46.88#ibcon#flushed, iclass 10, count 0 2006.225.08:03:46.88#ibcon#about to write, iclass 10, count 0 2006.225.08:03:46.88#ibcon#wrote, iclass 10, count 0 2006.225.08:03:46.88#ibcon#about to read 3, iclass 10, count 0 2006.225.08:03:46.92#ibcon#read 3, iclass 10, count 0 2006.225.08:03:46.92#ibcon#about to read 4, iclass 10, count 0 2006.225.08:03:46.92#ibcon#read 4, iclass 10, count 0 2006.225.08:03:46.92#ibcon#about to read 5, iclass 10, count 0 2006.225.08:03:46.92#ibcon#read 5, iclass 10, count 0 2006.225.08:03:46.92#ibcon#about to read 6, iclass 10, count 0 2006.225.08:03:46.92#ibcon#read 6, iclass 10, count 0 2006.225.08:03:46.92#ibcon#end of sib2, iclass 10, count 0 2006.225.08:03:46.92#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:03:46.92#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:03:46.92#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:03:46.92#ibcon#*before write, iclass 10, count 0 2006.225.08:03:46.92#ibcon#enter sib2, iclass 10, count 0 2006.225.08:03:46.92#ibcon#flushed, iclass 10, count 0 2006.225.08:03:46.92#ibcon#about to write, iclass 10, count 0 2006.225.08:03:46.92#ibcon#wrote, iclass 10, count 0 2006.225.08:03:46.92#ibcon#about to read 3, iclass 10, count 0 2006.225.08:03:46.96#ibcon#read 3, iclass 10, count 0 2006.225.08:03:46.96#ibcon#about to read 4, iclass 10, count 0 2006.225.08:03:46.96#ibcon#read 4, iclass 10, count 0 2006.225.08:03:46.96#ibcon#about to read 5, iclass 10, count 0 2006.225.08:03:46.96#ibcon#read 5, iclass 10, count 0 2006.225.08:03:46.96#ibcon#about to read 6, iclass 10, count 0 2006.225.08:03:46.96#ibcon#read 6, iclass 10, count 0 2006.225.08:03:46.96#ibcon#end of sib2, iclass 10, count 0 2006.225.08:03:46.96#ibcon#*after write, iclass 10, count 0 2006.225.08:03:46.96#ibcon#*before return 0, iclass 10, count 0 2006.225.08:03:46.96#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:03:46.96#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:03:46.96#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:03:46.96#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:03:46.97$vc4f8/va=1,8 2006.225.08:03:46.97#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.08:03:46.97#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.08:03:46.97#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:46.97#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:03:46.97#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:03:46.97#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:03:46.97#ibcon#enter wrdev, iclass 12, count 2 2006.225.08:03:46.97#ibcon#first serial, iclass 12, count 2 2006.225.08:03:46.97#ibcon#enter sib2, iclass 12, count 2 2006.225.08:03:46.97#ibcon#flushed, iclass 12, count 2 2006.225.08:03:46.97#ibcon#about to write, iclass 12, count 2 2006.225.08:03:46.97#ibcon#wrote, iclass 12, count 2 2006.225.08:03:46.97#ibcon#about to read 3, iclass 12, count 2 2006.225.08:03:46.99#ibcon#read 3, iclass 12, count 2 2006.225.08:03:46.99#ibcon#about to read 4, iclass 12, count 2 2006.225.08:03:46.99#ibcon#read 4, iclass 12, count 2 2006.225.08:03:46.99#ibcon#about to read 5, iclass 12, count 2 2006.225.08:03:46.99#ibcon#read 5, iclass 12, count 2 2006.225.08:03:46.99#ibcon#about to read 6, iclass 12, count 2 2006.225.08:03:46.99#ibcon#read 6, iclass 12, count 2 2006.225.08:03:46.99#ibcon#end of sib2, iclass 12, count 2 2006.225.08:03:46.99#ibcon#*mode == 0, iclass 12, count 2 2006.225.08:03:46.99#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.08:03:46.99#ibcon#[25=AT01-08\r\n] 2006.225.08:03:46.99#ibcon#*before write, iclass 12, count 2 2006.225.08:03:46.99#ibcon#enter sib2, iclass 12, count 2 2006.225.08:03:46.99#ibcon#flushed, iclass 12, count 2 2006.225.08:03:46.99#ibcon#about to write, iclass 12, count 2 2006.225.08:03:46.99#ibcon#wrote, iclass 12, count 2 2006.225.08:03:46.99#ibcon#about to read 3, iclass 12, count 2 2006.225.08:03:47.02#ibcon#read 3, iclass 12, count 2 2006.225.08:03:47.02#ibcon#about to read 4, iclass 12, count 2 2006.225.08:03:47.02#ibcon#read 4, iclass 12, count 2 2006.225.08:03:47.02#ibcon#about to read 5, iclass 12, count 2 2006.225.08:03:47.02#ibcon#read 5, iclass 12, count 2 2006.225.08:03:47.02#ibcon#about to read 6, iclass 12, count 2 2006.225.08:03:47.02#ibcon#read 6, iclass 12, count 2 2006.225.08:03:47.02#ibcon#end of sib2, iclass 12, count 2 2006.225.08:03:47.02#ibcon#*after write, iclass 12, count 2 2006.225.08:03:47.02#ibcon#*before return 0, iclass 12, count 2 2006.225.08:03:47.02#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:03:47.03#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:03:47.03#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.08:03:47.03#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:47.03#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:03:47.15#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:03:47.15#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:03:47.15#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:03:47.15#ibcon#first serial, iclass 12, count 0 2006.225.08:03:47.15#ibcon#enter sib2, iclass 12, count 0 2006.225.08:03:47.15#ibcon#flushed, iclass 12, count 0 2006.225.08:03:47.15#ibcon#about to write, iclass 12, count 0 2006.225.08:03:47.15#ibcon#wrote, iclass 12, count 0 2006.225.08:03:47.15#ibcon#about to read 3, iclass 12, count 0 2006.225.08:03:47.16#ibcon#read 3, iclass 12, count 0 2006.225.08:03:47.16#ibcon#about to read 4, iclass 12, count 0 2006.225.08:03:47.16#ibcon#read 4, iclass 12, count 0 2006.225.08:03:47.16#ibcon#about to read 5, iclass 12, count 0 2006.225.08:03:47.16#ibcon#read 5, iclass 12, count 0 2006.225.08:03:47.16#ibcon#about to read 6, iclass 12, count 0 2006.225.08:03:47.16#ibcon#read 6, iclass 12, count 0 2006.225.08:03:47.16#ibcon#end of sib2, iclass 12, count 0 2006.225.08:03:47.16#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:03:47.16#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:03:47.16#ibcon#[25=USB\r\n] 2006.225.08:03:47.16#ibcon#*before write, iclass 12, count 0 2006.225.08:03:47.16#ibcon#enter sib2, iclass 12, count 0 2006.225.08:03:47.16#ibcon#flushed, iclass 12, count 0 2006.225.08:03:47.16#ibcon#about to write, iclass 12, count 0 2006.225.08:03:47.17#ibcon#wrote, iclass 12, count 0 2006.225.08:03:47.17#ibcon#about to read 3, iclass 12, count 0 2006.225.08:03:47.19#ibcon#read 3, iclass 12, count 0 2006.225.08:03:47.19#ibcon#about to read 4, iclass 12, count 0 2006.225.08:03:47.19#ibcon#read 4, iclass 12, count 0 2006.225.08:03:47.19#ibcon#about to read 5, iclass 12, count 0 2006.225.08:03:47.19#ibcon#read 5, iclass 12, count 0 2006.225.08:03:47.19#ibcon#about to read 6, iclass 12, count 0 2006.225.08:03:47.19#ibcon#read 6, iclass 12, count 0 2006.225.08:03:47.19#ibcon#end of sib2, iclass 12, count 0 2006.225.08:03:47.19#ibcon#*after write, iclass 12, count 0 2006.225.08:03:47.19#ibcon#*before return 0, iclass 12, count 0 2006.225.08:03:47.19#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:03:47.19#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:03:47.19#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:03:47.19#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:03:47.20$vc4f8/valo=2,572.99 2006.225.08:03:47.20#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.08:03:47.20#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.08:03:47.20#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:47.20#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:03:47.20#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:03:47.20#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:03:47.20#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:03:47.20#ibcon#first serial, iclass 14, count 0 2006.225.08:03:47.20#ibcon#enter sib2, iclass 14, count 0 2006.225.08:03:47.20#ibcon#flushed, iclass 14, count 0 2006.225.08:03:47.20#ibcon#about to write, iclass 14, count 0 2006.225.08:03:47.20#ibcon#wrote, iclass 14, count 0 2006.225.08:03:47.20#ibcon#about to read 3, iclass 14, count 0 2006.225.08:03:47.22#ibcon#read 3, iclass 14, count 0 2006.225.08:03:47.22#ibcon#about to read 4, iclass 14, count 0 2006.225.08:03:47.22#ibcon#read 4, iclass 14, count 0 2006.225.08:03:47.22#ibcon#about to read 5, iclass 14, count 0 2006.225.08:03:47.22#ibcon#read 5, iclass 14, count 0 2006.225.08:03:47.22#ibcon#about to read 6, iclass 14, count 0 2006.225.08:03:47.22#ibcon#read 6, iclass 14, count 0 2006.225.08:03:47.22#ibcon#end of sib2, iclass 14, count 0 2006.225.08:03:47.22#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:03:47.22#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:03:47.22#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:03:47.22#ibcon#*before write, iclass 14, count 0 2006.225.08:03:47.22#ibcon#enter sib2, iclass 14, count 0 2006.225.08:03:47.22#ibcon#flushed, iclass 14, count 0 2006.225.08:03:47.22#ibcon#about to write, iclass 14, count 0 2006.225.08:03:47.22#ibcon#wrote, iclass 14, count 0 2006.225.08:03:47.22#ibcon#about to read 3, iclass 14, count 0 2006.225.08:03:47.26#ibcon#read 3, iclass 14, count 0 2006.225.08:03:47.26#ibcon#about to read 4, iclass 14, count 0 2006.225.08:03:47.26#ibcon#read 4, iclass 14, count 0 2006.225.08:03:47.26#ibcon#about to read 5, iclass 14, count 0 2006.225.08:03:47.26#ibcon#read 5, iclass 14, count 0 2006.225.08:03:47.26#ibcon#about to read 6, iclass 14, count 0 2006.225.08:03:47.26#ibcon#read 6, iclass 14, count 0 2006.225.08:03:47.26#ibcon#end of sib2, iclass 14, count 0 2006.225.08:03:47.26#ibcon#*after write, iclass 14, count 0 2006.225.08:03:47.26#ibcon#*before return 0, iclass 14, count 0 2006.225.08:03:47.26#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:03:47.27#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:03:47.27#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:03:47.27#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:03:47.27$vc4f8/va=2,7 2006.225.08:03:47.27#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.08:03:47.27#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.08:03:47.27#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:47.27#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:03:47.30#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:03:47.30#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:03:47.30#ibcon#enter wrdev, iclass 16, count 2 2006.225.08:03:47.30#ibcon#first serial, iclass 16, count 2 2006.225.08:03:47.30#ibcon#enter sib2, iclass 16, count 2 2006.225.08:03:47.30#ibcon#flushed, iclass 16, count 2 2006.225.08:03:47.30#ibcon#about to write, iclass 16, count 2 2006.225.08:03:47.30#ibcon#wrote, iclass 16, count 2 2006.225.08:03:47.30#ibcon#about to read 3, iclass 16, count 2 2006.225.08:03:47.32#ibcon#read 3, iclass 16, count 2 2006.225.08:03:47.32#ibcon#about to read 4, iclass 16, count 2 2006.225.08:03:47.32#ibcon#read 4, iclass 16, count 2 2006.225.08:03:47.32#ibcon#about to read 5, iclass 16, count 2 2006.225.08:03:47.32#ibcon#read 5, iclass 16, count 2 2006.225.08:03:47.32#ibcon#about to read 6, iclass 16, count 2 2006.225.08:03:47.32#ibcon#read 6, iclass 16, count 2 2006.225.08:03:47.32#ibcon#end of sib2, iclass 16, count 2 2006.225.08:03:47.32#ibcon#*mode == 0, iclass 16, count 2 2006.225.08:03:47.32#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.08:03:47.32#ibcon#[25=AT02-07\r\n] 2006.225.08:03:47.32#ibcon#*before write, iclass 16, count 2 2006.225.08:03:47.32#ibcon#enter sib2, iclass 16, count 2 2006.225.08:03:47.33#ibcon#flushed, iclass 16, count 2 2006.225.08:03:47.33#ibcon#about to write, iclass 16, count 2 2006.225.08:03:47.33#ibcon#wrote, iclass 16, count 2 2006.225.08:03:47.33#ibcon#about to read 3, iclass 16, count 2 2006.225.08:03:47.35#ibcon#read 3, iclass 16, count 2 2006.225.08:03:47.35#ibcon#about to read 4, iclass 16, count 2 2006.225.08:03:47.35#ibcon#read 4, iclass 16, count 2 2006.225.08:03:47.35#ibcon#about to read 5, iclass 16, count 2 2006.225.08:03:47.35#ibcon#read 5, iclass 16, count 2 2006.225.08:03:47.35#ibcon#about to read 6, iclass 16, count 2 2006.225.08:03:47.35#ibcon#read 6, iclass 16, count 2 2006.225.08:03:47.35#ibcon#end of sib2, iclass 16, count 2 2006.225.08:03:47.35#ibcon#*after write, iclass 16, count 2 2006.225.08:03:47.35#ibcon#*before return 0, iclass 16, count 2 2006.225.08:03:47.35#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:03:47.36#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:03:47.36#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.08:03:47.36#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:47.36#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:03:47.47#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:03:47.47#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:03:47.47#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:03:47.47#ibcon#first serial, iclass 16, count 0 2006.225.08:03:47.47#ibcon#enter sib2, iclass 16, count 0 2006.225.08:03:47.47#ibcon#flushed, iclass 16, count 0 2006.225.08:03:47.47#ibcon#about to write, iclass 16, count 0 2006.225.08:03:47.47#ibcon#wrote, iclass 16, count 0 2006.225.08:03:47.47#ibcon#about to read 3, iclass 16, count 0 2006.225.08:03:47.49#ibcon#read 3, iclass 16, count 0 2006.225.08:03:47.49#ibcon#about to read 4, iclass 16, count 0 2006.225.08:03:47.49#ibcon#read 4, iclass 16, count 0 2006.225.08:03:47.49#ibcon#about to read 5, iclass 16, count 0 2006.225.08:03:47.49#ibcon#read 5, iclass 16, count 0 2006.225.08:03:47.49#ibcon#about to read 6, iclass 16, count 0 2006.225.08:03:47.49#ibcon#read 6, iclass 16, count 0 2006.225.08:03:47.49#ibcon#end of sib2, iclass 16, count 0 2006.225.08:03:47.49#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:03:47.49#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:03:47.49#ibcon#[25=USB\r\n] 2006.225.08:03:47.49#ibcon#*before write, iclass 16, count 0 2006.225.08:03:47.49#ibcon#enter sib2, iclass 16, count 0 2006.225.08:03:47.49#ibcon#flushed, iclass 16, count 0 2006.225.08:03:47.49#ibcon#about to write, iclass 16, count 0 2006.225.08:03:47.50#ibcon#wrote, iclass 16, count 0 2006.225.08:03:47.50#ibcon#about to read 3, iclass 16, count 0 2006.225.08:03:47.52#ibcon#read 3, iclass 16, count 0 2006.225.08:03:47.52#ibcon#about to read 4, iclass 16, count 0 2006.225.08:03:47.52#ibcon#read 4, iclass 16, count 0 2006.225.08:03:47.52#ibcon#about to read 5, iclass 16, count 0 2006.225.08:03:47.52#ibcon#read 5, iclass 16, count 0 2006.225.08:03:47.52#ibcon#about to read 6, iclass 16, count 0 2006.225.08:03:47.52#ibcon#read 6, iclass 16, count 0 2006.225.08:03:47.52#ibcon#end of sib2, iclass 16, count 0 2006.225.08:03:47.52#ibcon#*after write, iclass 16, count 0 2006.225.08:03:47.52#ibcon#*before return 0, iclass 16, count 0 2006.225.08:03:47.52#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:03:47.52#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:03:47.52#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:03:47.52#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:03:47.53$vc4f8/valo=3,672.99 2006.225.08:03:47.53#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.08:03:47.53#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.08:03:47.53#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:47.53#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:03:47.53#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:03:47.53#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:03:47.53#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:03:47.53#ibcon#first serial, iclass 18, count 0 2006.225.08:03:47.53#ibcon#enter sib2, iclass 18, count 0 2006.225.08:03:47.53#ibcon#flushed, iclass 18, count 0 2006.225.08:03:47.53#ibcon#about to write, iclass 18, count 0 2006.225.08:03:47.53#ibcon#wrote, iclass 18, count 0 2006.225.08:03:47.53#ibcon#about to read 3, iclass 18, count 0 2006.225.08:03:47.55#ibcon#read 3, iclass 18, count 0 2006.225.08:03:47.55#ibcon#about to read 4, iclass 18, count 0 2006.225.08:03:47.55#ibcon#read 4, iclass 18, count 0 2006.225.08:03:47.55#ibcon#about to read 5, iclass 18, count 0 2006.225.08:03:47.55#ibcon#read 5, iclass 18, count 0 2006.225.08:03:47.55#ibcon#about to read 6, iclass 18, count 0 2006.225.08:03:47.55#ibcon#read 6, iclass 18, count 0 2006.225.08:03:47.55#ibcon#end of sib2, iclass 18, count 0 2006.225.08:03:47.55#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:03:47.55#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:03:47.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:03:47.55#ibcon#*before write, iclass 18, count 0 2006.225.08:03:47.55#ibcon#enter sib2, iclass 18, count 0 2006.225.08:03:47.55#ibcon#flushed, iclass 18, count 0 2006.225.08:03:47.55#ibcon#about to write, iclass 18, count 0 2006.225.08:03:47.55#ibcon#wrote, iclass 18, count 0 2006.225.08:03:47.55#ibcon#about to read 3, iclass 18, count 0 2006.225.08:03:47.59#ibcon#read 3, iclass 18, count 0 2006.225.08:03:47.59#ibcon#about to read 4, iclass 18, count 0 2006.225.08:03:47.59#ibcon#read 4, iclass 18, count 0 2006.225.08:03:47.59#ibcon#about to read 5, iclass 18, count 0 2006.225.08:03:47.59#ibcon#read 5, iclass 18, count 0 2006.225.08:03:47.59#ibcon#about to read 6, iclass 18, count 0 2006.225.08:03:47.59#ibcon#read 6, iclass 18, count 0 2006.225.08:03:47.59#ibcon#end of sib2, iclass 18, count 0 2006.225.08:03:47.59#ibcon#*after write, iclass 18, count 0 2006.225.08:03:47.59#ibcon#*before return 0, iclass 18, count 0 2006.225.08:03:47.59#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:03:47.60#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:03:47.60#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:03:47.60#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:03:47.60$vc4f8/va=3,6 2006.225.08:03:47.60#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.08:03:47.60#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.08:03:47.60#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:47.60#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:03:47.63#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:03:47.63#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:03:47.63#ibcon#enter wrdev, iclass 20, count 2 2006.225.08:03:47.63#ibcon#first serial, iclass 20, count 2 2006.225.08:03:47.63#ibcon#enter sib2, iclass 20, count 2 2006.225.08:03:47.63#ibcon#flushed, iclass 20, count 2 2006.225.08:03:47.63#ibcon#about to write, iclass 20, count 2 2006.225.08:03:47.63#ibcon#wrote, iclass 20, count 2 2006.225.08:03:47.63#ibcon#about to read 3, iclass 20, count 2 2006.225.08:03:47.66#ibcon#read 3, iclass 20, count 2 2006.225.08:03:47.66#ibcon#about to read 4, iclass 20, count 2 2006.225.08:03:47.66#ibcon#read 4, iclass 20, count 2 2006.225.08:03:47.66#ibcon#about to read 5, iclass 20, count 2 2006.225.08:03:47.66#ibcon#read 5, iclass 20, count 2 2006.225.08:03:47.66#ibcon#about to read 6, iclass 20, count 2 2006.225.08:03:47.66#ibcon#read 6, iclass 20, count 2 2006.225.08:03:47.66#ibcon#end of sib2, iclass 20, count 2 2006.225.08:03:47.66#ibcon#*mode == 0, iclass 20, count 2 2006.225.08:03:47.66#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.08:03:47.66#ibcon#[25=AT03-06\r\n] 2006.225.08:03:47.66#ibcon#*before write, iclass 20, count 2 2006.225.08:03:47.66#ibcon#enter sib2, iclass 20, count 2 2006.225.08:03:47.66#ibcon#flushed, iclass 20, count 2 2006.225.08:03:47.66#ibcon#about to write, iclass 20, count 2 2006.225.08:03:47.66#ibcon#wrote, iclass 20, count 2 2006.225.08:03:47.66#ibcon#about to read 3, iclass 20, count 2 2006.225.08:03:47.69#ibcon#read 3, iclass 20, count 2 2006.225.08:03:47.69#ibcon#about to read 4, iclass 20, count 2 2006.225.08:03:47.69#ibcon#read 4, iclass 20, count 2 2006.225.08:03:47.69#ibcon#about to read 5, iclass 20, count 2 2006.225.08:03:47.69#ibcon#read 5, iclass 20, count 2 2006.225.08:03:47.69#ibcon#about to read 6, iclass 20, count 2 2006.225.08:03:47.69#ibcon#read 6, iclass 20, count 2 2006.225.08:03:47.69#ibcon#end of sib2, iclass 20, count 2 2006.225.08:03:47.69#ibcon#*after write, iclass 20, count 2 2006.225.08:03:47.69#ibcon#*before return 0, iclass 20, count 2 2006.225.08:03:47.69#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:03:47.69#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:03:47.70#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.08:03:47.70#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:47.70#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:03:47.80#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:03:47.80#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:03:47.80#ibcon#enter wrdev, iclass 20, count 0 2006.225.08:03:47.80#ibcon#first serial, iclass 20, count 0 2006.225.08:03:47.80#ibcon#enter sib2, iclass 20, count 0 2006.225.08:03:47.80#ibcon#flushed, iclass 20, count 0 2006.225.08:03:47.80#ibcon#about to write, iclass 20, count 0 2006.225.08:03:47.80#ibcon#wrote, iclass 20, count 0 2006.225.08:03:47.80#ibcon#about to read 3, iclass 20, count 0 2006.225.08:03:47.82#ibcon#read 3, iclass 20, count 0 2006.225.08:03:47.82#ibcon#about to read 4, iclass 20, count 0 2006.225.08:03:47.82#ibcon#read 4, iclass 20, count 0 2006.225.08:03:47.82#ibcon#about to read 5, iclass 20, count 0 2006.225.08:03:47.82#ibcon#read 5, iclass 20, count 0 2006.225.08:03:47.82#ibcon#about to read 6, iclass 20, count 0 2006.225.08:03:47.82#ibcon#read 6, iclass 20, count 0 2006.225.08:03:47.82#ibcon#end of sib2, iclass 20, count 0 2006.225.08:03:47.82#ibcon#*mode == 0, iclass 20, count 0 2006.225.08:03:47.82#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.08:03:47.82#ibcon#[25=USB\r\n] 2006.225.08:03:47.82#ibcon#*before write, iclass 20, count 0 2006.225.08:03:47.82#ibcon#enter sib2, iclass 20, count 0 2006.225.08:03:47.82#ibcon#flushed, iclass 20, count 0 2006.225.08:03:47.82#ibcon#about to write, iclass 20, count 0 2006.225.08:03:47.83#ibcon#wrote, iclass 20, count 0 2006.225.08:03:47.83#ibcon#about to read 3, iclass 20, count 0 2006.225.08:03:47.85#ibcon#read 3, iclass 20, count 0 2006.225.08:03:47.85#ibcon#about to read 4, iclass 20, count 0 2006.225.08:03:47.85#ibcon#read 4, iclass 20, count 0 2006.225.08:03:47.85#ibcon#about to read 5, iclass 20, count 0 2006.225.08:03:47.85#ibcon#read 5, iclass 20, count 0 2006.225.08:03:47.85#ibcon#about to read 6, iclass 20, count 0 2006.225.08:03:47.85#ibcon#read 6, iclass 20, count 0 2006.225.08:03:47.85#ibcon#end of sib2, iclass 20, count 0 2006.225.08:03:47.85#ibcon#*after write, iclass 20, count 0 2006.225.08:03:47.85#ibcon#*before return 0, iclass 20, count 0 2006.225.08:03:47.85#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:03:47.85#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:03:47.85#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.08:03:47.85#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.08:03:47.86$vc4f8/valo=4,832.99 2006.225.08:03:47.86#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.08:03:47.86#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.08:03:47.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:47.86#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:03:47.86#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:03:47.86#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:03:47.86#ibcon#enter wrdev, iclass 22, count 0 2006.225.08:03:47.86#ibcon#first serial, iclass 22, count 0 2006.225.08:03:47.86#ibcon#enter sib2, iclass 22, count 0 2006.225.08:03:47.86#ibcon#flushed, iclass 22, count 0 2006.225.08:03:47.86#ibcon#about to write, iclass 22, count 0 2006.225.08:03:47.86#ibcon#wrote, iclass 22, count 0 2006.225.08:03:47.86#ibcon#about to read 3, iclass 22, count 0 2006.225.08:03:47.87#ibcon#read 3, iclass 22, count 0 2006.225.08:03:47.87#ibcon#about to read 4, iclass 22, count 0 2006.225.08:03:47.87#ibcon#read 4, iclass 22, count 0 2006.225.08:03:47.87#ibcon#about to read 5, iclass 22, count 0 2006.225.08:03:47.87#ibcon#read 5, iclass 22, count 0 2006.225.08:03:47.87#ibcon#about to read 6, iclass 22, count 0 2006.225.08:03:47.87#ibcon#read 6, iclass 22, count 0 2006.225.08:03:47.87#ibcon#end of sib2, iclass 22, count 0 2006.225.08:03:47.87#ibcon#*mode == 0, iclass 22, count 0 2006.225.08:03:47.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.08:03:47.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:03:47.87#ibcon#*before write, iclass 22, count 0 2006.225.08:03:47.87#ibcon#enter sib2, iclass 22, count 0 2006.225.08:03:47.87#ibcon#flushed, iclass 22, count 0 2006.225.08:03:47.87#ibcon#about to write, iclass 22, count 0 2006.225.08:03:47.88#ibcon#wrote, iclass 22, count 0 2006.225.08:03:47.88#ibcon#about to read 3, iclass 22, count 0 2006.225.08:03:47.91#ibcon#read 3, iclass 22, count 0 2006.225.08:03:47.91#ibcon#about to read 4, iclass 22, count 0 2006.225.08:03:47.91#ibcon#read 4, iclass 22, count 0 2006.225.08:03:47.91#ibcon#about to read 5, iclass 22, count 0 2006.225.08:03:47.91#ibcon#read 5, iclass 22, count 0 2006.225.08:03:47.91#ibcon#about to read 6, iclass 22, count 0 2006.225.08:03:47.91#ibcon#read 6, iclass 22, count 0 2006.225.08:03:47.91#ibcon#end of sib2, iclass 22, count 0 2006.225.08:03:47.91#ibcon#*after write, iclass 22, count 0 2006.225.08:03:47.91#ibcon#*before return 0, iclass 22, count 0 2006.225.08:03:47.91#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:03:47.91#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:03:47.92#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.08:03:47.92#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.08:03:47.92$vc4f8/va=4,7 2006.225.08:03:47.92#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.08:03:47.92#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.08:03:47.92#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:47.92#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:03:47.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:03:47.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:03:47.96#ibcon#enter wrdev, iclass 24, count 2 2006.225.08:03:47.96#ibcon#first serial, iclass 24, count 2 2006.225.08:03:47.96#ibcon#enter sib2, iclass 24, count 2 2006.225.08:03:47.96#ibcon#flushed, iclass 24, count 2 2006.225.08:03:47.96#ibcon#about to write, iclass 24, count 2 2006.225.08:03:47.96#ibcon#wrote, iclass 24, count 2 2006.225.08:03:47.96#ibcon#about to read 3, iclass 24, count 2 2006.225.08:03:47.98#ibcon#read 3, iclass 24, count 2 2006.225.08:03:47.98#ibcon#about to read 4, iclass 24, count 2 2006.225.08:03:47.98#ibcon#read 4, iclass 24, count 2 2006.225.08:03:47.98#ibcon#about to read 5, iclass 24, count 2 2006.225.08:03:47.98#ibcon#read 5, iclass 24, count 2 2006.225.08:03:47.98#ibcon#about to read 6, iclass 24, count 2 2006.225.08:03:47.98#ibcon#read 6, iclass 24, count 2 2006.225.08:03:47.98#ibcon#end of sib2, iclass 24, count 2 2006.225.08:03:47.98#ibcon#*mode == 0, iclass 24, count 2 2006.225.08:03:47.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.08:03:47.98#ibcon#[25=AT04-07\r\n] 2006.225.08:03:47.98#ibcon#*before write, iclass 24, count 2 2006.225.08:03:47.98#ibcon#enter sib2, iclass 24, count 2 2006.225.08:03:47.98#ibcon#flushed, iclass 24, count 2 2006.225.08:03:47.98#ibcon#about to write, iclass 24, count 2 2006.225.08:03:47.99#ibcon#wrote, iclass 24, count 2 2006.225.08:03:47.99#ibcon#about to read 3, iclass 24, count 2 2006.225.08:03:48.01#ibcon#read 3, iclass 24, count 2 2006.225.08:03:48.01#ibcon#about to read 4, iclass 24, count 2 2006.225.08:03:48.01#ibcon#read 4, iclass 24, count 2 2006.225.08:03:48.01#ibcon#about to read 5, iclass 24, count 2 2006.225.08:03:48.01#ibcon#read 5, iclass 24, count 2 2006.225.08:03:48.01#ibcon#about to read 6, iclass 24, count 2 2006.225.08:03:48.01#ibcon#read 6, iclass 24, count 2 2006.225.08:03:48.01#ibcon#end of sib2, iclass 24, count 2 2006.225.08:03:48.01#ibcon#*after write, iclass 24, count 2 2006.225.08:03:48.01#ibcon#*before return 0, iclass 24, count 2 2006.225.08:03:48.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:03:48.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:03:48.02#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.08:03:48.02#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:48.02#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:03:48.12#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:03:48.12#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:03:48.12#ibcon#enter wrdev, iclass 24, count 0 2006.225.08:03:48.12#ibcon#first serial, iclass 24, count 0 2006.225.08:03:48.12#ibcon#enter sib2, iclass 24, count 0 2006.225.08:03:48.12#ibcon#flushed, iclass 24, count 0 2006.225.08:03:48.12#ibcon#about to write, iclass 24, count 0 2006.225.08:03:48.12#ibcon#wrote, iclass 24, count 0 2006.225.08:03:48.12#ibcon#about to read 3, iclass 24, count 0 2006.225.08:03:48.14#ibcon#read 3, iclass 24, count 0 2006.225.08:03:48.14#ibcon#about to read 4, iclass 24, count 0 2006.225.08:03:48.14#ibcon#read 4, iclass 24, count 0 2006.225.08:03:48.14#ibcon#about to read 5, iclass 24, count 0 2006.225.08:03:48.14#ibcon#read 5, iclass 24, count 0 2006.225.08:03:48.14#ibcon#about to read 6, iclass 24, count 0 2006.225.08:03:48.14#ibcon#read 6, iclass 24, count 0 2006.225.08:03:48.14#ibcon#end of sib2, iclass 24, count 0 2006.225.08:03:48.14#ibcon#*mode == 0, iclass 24, count 0 2006.225.08:03:48.14#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.08:03:48.14#ibcon#[25=USB\r\n] 2006.225.08:03:48.14#ibcon#*before write, iclass 24, count 0 2006.225.08:03:48.14#ibcon#enter sib2, iclass 24, count 0 2006.225.08:03:48.14#ibcon#flushed, iclass 24, count 0 2006.225.08:03:48.14#ibcon#about to write, iclass 24, count 0 2006.225.08:03:48.15#ibcon#wrote, iclass 24, count 0 2006.225.08:03:48.15#ibcon#about to read 3, iclass 24, count 0 2006.225.08:03:48.17#ibcon#read 3, iclass 24, count 0 2006.225.08:03:48.17#ibcon#about to read 4, iclass 24, count 0 2006.225.08:03:48.17#ibcon#read 4, iclass 24, count 0 2006.225.08:03:48.17#ibcon#about to read 5, iclass 24, count 0 2006.225.08:03:48.17#ibcon#read 5, iclass 24, count 0 2006.225.08:03:48.17#ibcon#about to read 6, iclass 24, count 0 2006.225.08:03:48.17#ibcon#read 6, iclass 24, count 0 2006.225.08:03:48.17#ibcon#end of sib2, iclass 24, count 0 2006.225.08:03:48.17#ibcon#*after write, iclass 24, count 0 2006.225.08:03:48.17#ibcon#*before return 0, iclass 24, count 0 2006.225.08:03:48.17#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:03:48.17#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:03:48.17#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.08:03:48.17#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.08:03:48.18$vc4f8/valo=5,652.99 2006.225.08:03:48.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.08:03:48.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.08:03:48.18#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:48.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:03:48.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:03:48.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:03:48.18#ibcon#enter wrdev, iclass 26, count 0 2006.225.08:03:48.18#ibcon#first serial, iclass 26, count 0 2006.225.08:03:48.18#ibcon#enter sib2, iclass 26, count 0 2006.225.08:03:48.18#ibcon#flushed, iclass 26, count 0 2006.225.08:03:48.18#ibcon#about to write, iclass 26, count 0 2006.225.08:03:48.18#ibcon#wrote, iclass 26, count 0 2006.225.08:03:48.18#ibcon#about to read 3, iclass 26, count 0 2006.225.08:03:48.19#ibcon#read 3, iclass 26, count 0 2006.225.08:03:48.19#ibcon#about to read 4, iclass 26, count 0 2006.225.08:03:48.19#ibcon#read 4, iclass 26, count 0 2006.225.08:03:48.19#ibcon#about to read 5, iclass 26, count 0 2006.225.08:03:48.19#ibcon#read 5, iclass 26, count 0 2006.225.08:03:48.19#ibcon#about to read 6, iclass 26, count 0 2006.225.08:03:48.19#ibcon#read 6, iclass 26, count 0 2006.225.08:03:48.19#ibcon#end of sib2, iclass 26, count 0 2006.225.08:03:48.19#ibcon#*mode == 0, iclass 26, count 0 2006.225.08:03:48.19#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.08:03:48.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:03:48.19#ibcon#*before write, iclass 26, count 0 2006.225.08:03:48.19#ibcon#enter sib2, iclass 26, count 0 2006.225.08:03:48.19#ibcon#flushed, iclass 26, count 0 2006.225.08:03:48.19#ibcon#about to write, iclass 26, count 0 2006.225.08:03:48.20#ibcon#wrote, iclass 26, count 0 2006.225.08:03:48.20#ibcon#about to read 3, iclass 26, count 0 2006.225.08:03:48.23#ibcon#read 3, iclass 26, count 0 2006.225.08:03:48.23#ibcon#about to read 4, iclass 26, count 0 2006.225.08:03:48.23#ibcon#read 4, iclass 26, count 0 2006.225.08:03:48.23#ibcon#about to read 5, iclass 26, count 0 2006.225.08:03:48.23#ibcon#read 5, iclass 26, count 0 2006.225.08:03:48.23#ibcon#about to read 6, iclass 26, count 0 2006.225.08:03:48.23#ibcon#read 6, iclass 26, count 0 2006.225.08:03:48.23#ibcon#end of sib2, iclass 26, count 0 2006.225.08:03:48.23#ibcon#*after write, iclass 26, count 0 2006.225.08:03:48.23#ibcon#*before return 0, iclass 26, count 0 2006.225.08:03:48.23#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:03:48.23#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:03:48.23#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.08:03:48.23#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.08:03:48.24$vc4f8/va=5,7 2006.225.08:03:48.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.08:03:48.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.08:03:48.24#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:48.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:03:48.28#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:03:48.28#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:03:48.28#ibcon#enter wrdev, iclass 28, count 2 2006.225.08:03:48.28#ibcon#first serial, iclass 28, count 2 2006.225.08:03:48.28#ibcon#enter sib2, iclass 28, count 2 2006.225.08:03:48.28#ibcon#flushed, iclass 28, count 2 2006.225.08:03:48.28#ibcon#about to write, iclass 28, count 2 2006.225.08:03:48.28#ibcon#wrote, iclass 28, count 2 2006.225.08:03:48.28#ibcon#about to read 3, iclass 28, count 2 2006.225.08:03:48.30#ibcon#read 3, iclass 28, count 2 2006.225.08:03:48.30#ibcon#about to read 4, iclass 28, count 2 2006.225.08:03:48.30#ibcon#read 4, iclass 28, count 2 2006.225.08:03:48.30#ibcon#about to read 5, iclass 28, count 2 2006.225.08:03:48.30#ibcon#read 5, iclass 28, count 2 2006.225.08:03:48.30#ibcon#about to read 6, iclass 28, count 2 2006.225.08:03:48.30#ibcon#read 6, iclass 28, count 2 2006.225.08:03:48.30#ibcon#end of sib2, iclass 28, count 2 2006.225.08:03:48.30#ibcon#*mode == 0, iclass 28, count 2 2006.225.08:03:48.30#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.08:03:48.30#ibcon#[25=AT05-07\r\n] 2006.225.08:03:48.30#ibcon#*before write, iclass 28, count 2 2006.225.08:03:48.30#ibcon#enter sib2, iclass 28, count 2 2006.225.08:03:48.30#ibcon#flushed, iclass 28, count 2 2006.225.08:03:48.30#ibcon#about to write, iclass 28, count 2 2006.225.08:03:48.31#ibcon#wrote, iclass 28, count 2 2006.225.08:03:48.31#ibcon#about to read 3, iclass 28, count 2 2006.225.08:03:48.33#ibcon#read 3, iclass 28, count 2 2006.225.08:03:48.33#ibcon#about to read 4, iclass 28, count 2 2006.225.08:03:48.33#ibcon#read 4, iclass 28, count 2 2006.225.08:03:48.33#ibcon#about to read 5, iclass 28, count 2 2006.225.08:03:48.33#ibcon#read 5, iclass 28, count 2 2006.225.08:03:48.33#ibcon#about to read 6, iclass 28, count 2 2006.225.08:03:48.33#ibcon#read 6, iclass 28, count 2 2006.225.08:03:48.33#ibcon#end of sib2, iclass 28, count 2 2006.225.08:03:48.33#ibcon#*after write, iclass 28, count 2 2006.225.08:03:48.33#ibcon#*before return 0, iclass 28, count 2 2006.225.08:03:48.33#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:03:48.33#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:03:48.33#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.08:03:48.33#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:48.34#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:03:48.45#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:03:48.45#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:03:48.45#ibcon#enter wrdev, iclass 28, count 0 2006.225.08:03:48.45#ibcon#first serial, iclass 28, count 0 2006.225.08:03:48.45#ibcon#enter sib2, iclass 28, count 0 2006.225.08:03:48.45#ibcon#flushed, iclass 28, count 0 2006.225.08:03:48.45#ibcon#about to write, iclass 28, count 0 2006.225.08:03:48.45#ibcon#wrote, iclass 28, count 0 2006.225.08:03:48.45#ibcon#about to read 3, iclass 28, count 0 2006.225.08:03:48.47#ibcon#read 3, iclass 28, count 0 2006.225.08:03:48.47#ibcon#about to read 4, iclass 28, count 0 2006.225.08:03:48.47#ibcon#read 4, iclass 28, count 0 2006.225.08:03:48.47#ibcon#about to read 5, iclass 28, count 0 2006.225.08:03:48.47#ibcon#read 5, iclass 28, count 0 2006.225.08:03:48.47#ibcon#about to read 6, iclass 28, count 0 2006.225.08:03:48.47#ibcon#read 6, iclass 28, count 0 2006.225.08:03:48.47#ibcon#end of sib2, iclass 28, count 0 2006.225.08:03:48.47#ibcon#*mode == 0, iclass 28, count 0 2006.225.08:03:48.47#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.08:03:48.47#ibcon#[25=USB\r\n] 2006.225.08:03:48.47#ibcon#*before write, iclass 28, count 0 2006.225.08:03:48.47#ibcon#enter sib2, iclass 28, count 0 2006.225.08:03:48.47#ibcon#flushed, iclass 28, count 0 2006.225.08:03:48.47#ibcon#about to write, iclass 28, count 0 2006.225.08:03:48.48#ibcon#wrote, iclass 28, count 0 2006.225.08:03:48.48#ibcon#about to read 3, iclass 28, count 0 2006.225.08:03:48.50#ibcon#read 3, iclass 28, count 0 2006.225.08:03:48.50#ibcon#about to read 4, iclass 28, count 0 2006.225.08:03:48.50#ibcon#read 4, iclass 28, count 0 2006.225.08:03:48.50#ibcon#about to read 5, iclass 28, count 0 2006.225.08:03:48.50#ibcon#read 5, iclass 28, count 0 2006.225.08:03:48.50#ibcon#about to read 6, iclass 28, count 0 2006.225.08:03:48.50#ibcon#read 6, iclass 28, count 0 2006.225.08:03:48.50#ibcon#end of sib2, iclass 28, count 0 2006.225.08:03:48.50#ibcon#*after write, iclass 28, count 0 2006.225.08:03:48.50#ibcon#*before return 0, iclass 28, count 0 2006.225.08:03:48.50#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:03:48.50#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:03:48.50#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.08:03:48.50#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.08:03:48.51$vc4f8/valo=6,772.99 2006.225.08:03:48.51#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.08:03:48.51#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.08:03:48.51#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:48.51#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:03:48.51#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:03:48.51#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:03:48.51#ibcon#enter wrdev, iclass 30, count 0 2006.225.08:03:48.51#ibcon#first serial, iclass 30, count 0 2006.225.08:03:48.51#ibcon#enter sib2, iclass 30, count 0 2006.225.08:03:48.51#ibcon#flushed, iclass 30, count 0 2006.225.08:03:48.51#ibcon#about to write, iclass 30, count 0 2006.225.08:03:48.51#ibcon#wrote, iclass 30, count 0 2006.225.08:03:48.51#ibcon#about to read 3, iclass 30, count 0 2006.225.08:03:48.52#ibcon#read 3, iclass 30, count 0 2006.225.08:03:48.52#ibcon#about to read 4, iclass 30, count 0 2006.225.08:03:48.52#ibcon#read 4, iclass 30, count 0 2006.225.08:03:48.52#ibcon#about to read 5, iclass 30, count 0 2006.225.08:03:48.52#ibcon#read 5, iclass 30, count 0 2006.225.08:03:48.52#ibcon#about to read 6, iclass 30, count 0 2006.225.08:03:48.52#ibcon#read 6, iclass 30, count 0 2006.225.08:03:48.52#ibcon#end of sib2, iclass 30, count 0 2006.225.08:03:48.52#ibcon#*mode == 0, iclass 30, count 0 2006.225.08:03:48.52#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.08:03:48.52#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:03:48.52#ibcon#*before write, iclass 30, count 0 2006.225.08:03:48.52#ibcon#enter sib2, iclass 30, count 0 2006.225.08:03:48.52#ibcon#flushed, iclass 30, count 0 2006.225.08:03:48.52#ibcon#about to write, iclass 30, count 0 2006.225.08:03:48.53#ibcon#wrote, iclass 30, count 0 2006.225.08:03:48.53#ibcon#about to read 3, iclass 30, count 0 2006.225.08:03:48.56#ibcon#read 3, iclass 30, count 0 2006.225.08:03:48.56#ibcon#about to read 4, iclass 30, count 0 2006.225.08:03:48.56#ibcon#read 4, iclass 30, count 0 2006.225.08:03:48.56#ibcon#about to read 5, iclass 30, count 0 2006.225.08:03:48.56#ibcon#read 5, iclass 30, count 0 2006.225.08:03:48.56#ibcon#about to read 6, iclass 30, count 0 2006.225.08:03:48.56#ibcon#read 6, iclass 30, count 0 2006.225.08:03:48.56#ibcon#end of sib2, iclass 30, count 0 2006.225.08:03:48.56#ibcon#*after write, iclass 30, count 0 2006.225.08:03:48.56#ibcon#*before return 0, iclass 30, count 0 2006.225.08:03:48.56#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:03:48.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:03:48.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.08:03:48.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.08:03:48.57$vc4f8/va=6,6 2006.225.08:03:48.57#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.225.08:03:48.57#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.225.08:03:48.57#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:48.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:03:48.61#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:03:48.61#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:03:48.61#ibcon#enter wrdev, iclass 32, count 2 2006.225.08:03:48.61#ibcon#first serial, iclass 32, count 2 2006.225.08:03:48.61#ibcon#enter sib2, iclass 32, count 2 2006.225.08:03:48.61#ibcon#flushed, iclass 32, count 2 2006.225.08:03:48.61#ibcon#about to write, iclass 32, count 2 2006.225.08:03:48.61#ibcon#wrote, iclass 32, count 2 2006.225.08:03:48.61#ibcon#about to read 3, iclass 32, count 2 2006.225.08:03:48.63#ibcon#read 3, iclass 32, count 2 2006.225.08:03:48.63#ibcon#about to read 4, iclass 32, count 2 2006.225.08:03:48.63#ibcon#read 4, iclass 32, count 2 2006.225.08:03:48.63#ibcon#about to read 5, iclass 32, count 2 2006.225.08:03:48.63#ibcon#read 5, iclass 32, count 2 2006.225.08:03:48.63#ibcon#about to read 6, iclass 32, count 2 2006.225.08:03:48.63#ibcon#read 6, iclass 32, count 2 2006.225.08:03:48.63#ibcon#end of sib2, iclass 32, count 2 2006.225.08:03:48.63#ibcon#*mode == 0, iclass 32, count 2 2006.225.08:03:48.63#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.225.08:03:48.63#ibcon#[25=AT06-06\r\n] 2006.225.08:03:48.63#ibcon#*before write, iclass 32, count 2 2006.225.08:03:48.63#ibcon#enter sib2, iclass 32, count 2 2006.225.08:03:48.63#ibcon#flushed, iclass 32, count 2 2006.225.08:03:48.63#ibcon#about to write, iclass 32, count 2 2006.225.08:03:48.64#ibcon#wrote, iclass 32, count 2 2006.225.08:03:48.64#ibcon#about to read 3, iclass 32, count 2 2006.225.08:03:48.66#ibcon#read 3, iclass 32, count 2 2006.225.08:03:48.66#ibcon#about to read 4, iclass 32, count 2 2006.225.08:03:48.66#ibcon#read 4, iclass 32, count 2 2006.225.08:03:48.66#ibcon#about to read 5, iclass 32, count 2 2006.225.08:03:48.66#ibcon#read 5, iclass 32, count 2 2006.225.08:03:48.66#ibcon#about to read 6, iclass 32, count 2 2006.225.08:03:48.66#ibcon#read 6, iclass 32, count 2 2006.225.08:03:48.66#ibcon#end of sib2, iclass 32, count 2 2006.225.08:03:48.66#ibcon#*after write, iclass 32, count 2 2006.225.08:03:48.66#ibcon#*before return 0, iclass 32, count 2 2006.225.08:03:48.66#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:03:48.66#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:03:48.66#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.225.08:03:48.66#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:48.66#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:03:48.78#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:03:48.78#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:03:48.78#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:03:48.78#ibcon#first serial, iclass 32, count 0 2006.225.08:03:48.78#ibcon#enter sib2, iclass 32, count 0 2006.225.08:03:48.78#ibcon#flushed, iclass 32, count 0 2006.225.08:03:48.78#ibcon#about to write, iclass 32, count 0 2006.225.08:03:48.78#ibcon#wrote, iclass 32, count 0 2006.225.08:03:48.78#ibcon#about to read 3, iclass 32, count 0 2006.225.08:03:48.80#ibcon#read 3, iclass 32, count 0 2006.225.08:03:48.80#ibcon#about to read 4, iclass 32, count 0 2006.225.08:03:48.80#ibcon#read 4, iclass 32, count 0 2006.225.08:03:48.80#ibcon#about to read 5, iclass 32, count 0 2006.225.08:03:48.80#ibcon#read 5, iclass 32, count 0 2006.225.08:03:48.80#ibcon#about to read 6, iclass 32, count 0 2006.225.08:03:48.80#ibcon#read 6, iclass 32, count 0 2006.225.08:03:48.80#ibcon#end of sib2, iclass 32, count 0 2006.225.08:03:48.80#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:03:48.80#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:03:48.80#ibcon#[25=USB\r\n] 2006.225.08:03:48.80#ibcon#*before write, iclass 32, count 0 2006.225.08:03:48.80#ibcon#enter sib2, iclass 32, count 0 2006.225.08:03:48.80#ibcon#flushed, iclass 32, count 0 2006.225.08:03:48.80#ibcon#about to write, iclass 32, count 0 2006.225.08:03:48.81#ibcon#wrote, iclass 32, count 0 2006.225.08:03:48.81#ibcon#about to read 3, iclass 32, count 0 2006.225.08:03:48.83#ibcon#read 3, iclass 32, count 0 2006.225.08:03:48.83#ibcon#about to read 4, iclass 32, count 0 2006.225.08:03:48.83#ibcon#read 4, iclass 32, count 0 2006.225.08:03:48.83#ibcon#about to read 5, iclass 32, count 0 2006.225.08:03:48.83#ibcon#read 5, iclass 32, count 0 2006.225.08:03:48.83#ibcon#about to read 6, iclass 32, count 0 2006.225.08:03:48.83#ibcon#read 6, iclass 32, count 0 2006.225.08:03:48.83#ibcon#end of sib2, iclass 32, count 0 2006.225.08:03:48.83#ibcon#*after write, iclass 32, count 0 2006.225.08:03:48.83#ibcon#*before return 0, iclass 32, count 0 2006.225.08:03:48.83#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:03:48.83#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:03:48.83#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:03:48.83#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:03:48.84$vc4f8/valo=7,832.99 2006.225.08:03:48.84#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.08:03:48.84#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.08:03:48.84#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:48.84#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:03:48.84#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:03:48.84#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:03:48.84#ibcon#enter wrdev, iclass 34, count 0 2006.225.08:03:48.84#ibcon#first serial, iclass 34, count 0 2006.225.08:03:48.84#ibcon#enter sib2, iclass 34, count 0 2006.225.08:03:48.84#ibcon#flushed, iclass 34, count 0 2006.225.08:03:48.84#ibcon#about to write, iclass 34, count 0 2006.225.08:03:48.84#ibcon#wrote, iclass 34, count 0 2006.225.08:03:48.84#ibcon#about to read 3, iclass 34, count 0 2006.225.08:03:48.85#ibcon#read 3, iclass 34, count 0 2006.225.08:03:48.85#ibcon#about to read 4, iclass 34, count 0 2006.225.08:03:48.85#ibcon#read 4, iclass 34, count 0 2006.225.08:03:48.85#ibcon#about to read 5, iclass 34, count 0 2006.225.08:03:48.85#ibcon#read 5, iclass 34, count 0 2006.225.08:03:48.85#ibcon#about to read 6, iclass 34, count 0 2006.225.08:03:48.85#ibcon#read 6, iclass 34, count 0 2006.225.08:03:48.85#ibcon#end of sib2, iclass 34, count 0 2006.225.08:03:48.85#ibcon#*mode == 0, iclass 34, count 0 2006.225.08:03:48.85#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.08:03:48.85#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:03:48.85#ibcon#*before write, iclass 34, count 0 2006.225.08:03:48.85#ibcon#enter sib2, iclass 34, count 0 2006.225.08:03:48.85#ibcon#flushed, iclass 34, count 0 2006.225.08:03:48.85#ibcon#about to write, iclass 34, count 0 2006.225.08:03:48.86#ibcon#wrote, iclass 34, count 0 2006.225.08:03:48.86#ibcon#about to read 3, iclass 34, count 0 2006.225.08:03:48.89#ibcon#read 3, iclass 34, count 0 2006.225.08:03:48.89#ibcon#about to read 4, iclass 34, count 0 2006.225.08:03:48.89#ibcon#read 4, iclass 34, count 0 2006.225.08:03:48.89#ibcon#about to read 5, iclass 34, count 0 2006.225.08:03:48.89#ibcon#read 5, iclass 34, count 0 2006.225.08:03:48.89#ibcon#about to read 6, iclass 34, count 0 2006.225.08:03:48.89#ibcon#read 6, iclass 34, count 0 2006.225.08:03:48.89#ibcon#end of sib2, iclass 34, count 0 2006.225.08:03:48.89#ibcon#*after write, iclass 34, count 0 2006.225.08:03:48.89#ibcon#*before return 0, iclass 34, count 0 2006.225.08:03:48.89#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:03:48.89#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:03:48.89#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.08:03:48.89#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.08:03:48.90$vc4f8/va=7,6 2006.225.08:03:48.90#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.08:03:48.90#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.08:03:48.90#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:48.90#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:03:48.94#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:03:48.94#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:03:48.94#ibcon#enter wrdev, iclass 36, count 2 2006.225.08:03:48.94#ibcon#first serial, iclass 36, count 2 2006.225.08:03:48.94#ibcon#enter sib2, iclass 36, count 2 2006.225.08:03:48.94#ibcon#flushed, iclass 36, count 2 2006.225.08:03:48.94#ibcon#about to write, iclass 36, count 2 2006.225.08:03:48.94#ibcon#wrote, iclass 36, count 2 2006.225.08:03:48.94#ibcon#about to read 3, iclass 36, count 2 2006.225.08:03:48.96#ibcon#read 3, iclass 36, count 2 2006.225.08:03:48.96#ibcon#about to read 4, iclass 36, count 2 2006.225.08:03:48.96#ibcon#read 4, iclass 36, count 2 2006.225.08:03:48.96#ibcon#about to read 5, iclass 36, count 2 2006.225.08:03:48.96#ibcon#read 5, iclass 36, count 2 2006.225.08:03:48.96#ibcon#about to read 6, iclass 36, count 2 2006.225.08:03:48.96#ibcon#read 6, iclass 36, count 2 2006.225.08:03:48.96#ibcon#end of sib2, iclass 36, count 2 2006.225.08:03:48.96#ibcon#*mode == 0, iclass 36, count 2 2006.225.08:03:48.96#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.08:03:48.96#ibcon#[25=AT07-06\r\n] 2006.225.08:03:48.96#ibcon#*before write, iclass 36, count 2 2006.225.08:03:48.96#ibcon#enter sib2, iclass 36, count 2 2006.225.08:03:48.96#ibcon#flushed, iclass 36, count 2 2006.225.08:03:48.96#ibcon#about to write, iclass 36, count 2 2006.225.08:03:48.97#ibcon#wrote, iclass 36, count 2 2006.225.08:03:48.97#ibcon#about to read 3, iclass 36, count 2 2006.225.08:03:48.99#ibcon#read 3, iclass 36, count 2 2006.225.08:03:48.99#ibcon#about to read 4, iclass 36, count 2 2006.225.08:03:48.99#ibcon#read 4, iclass 36, count 2 2006.225.08:03:48.99#ibcon#about to read 5, iclass 36, count 2 2006.225.08:03:48.99#ibcon#read 5, iclass 36, count 2 2006.225.08:03:48.99#ibcon#about to read 6, iclass 36, count 2 2006.225.08:03:48.99#ibcon#read 6, iclass 36, count 2 2006.225.08:03:48.99#ibcon#end of sib2, iclass 36, count 2 2006.225.08:03:48.99#ibcon#*after write, iclass 36, count 2 2006.225.08:03:48.99#ibcon#*before return 0, iclass 36, count 2 2006.225.08:03:48.99#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:03:48.99#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:03:48.99#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.08:03:48.99#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:48.99#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:03:49.11#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:03:49.11#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:03:49.11#ibcon#enter wrdev, iclass 36, count 0 2006.225.08:03:49.11#ibcon#first serial, iclass 36, count 0 2006.225.08:03:49.11#ibcon#enter sib2, iclass 36, count 0 2006.225.08:03:49.11#ibcon#flushed, iclass 36, count 0 2006.225.08:03:49.11#ibcon#about to write, iclass 36, count 0 2006.225.08:03:49.11#ibcon#wrote, iclass 36, count 0 2006.225.08:03:49.11#ibcon#about to read 3, iclass 36, count 0 2006.225.08:03:49.13#ibcon#read 3, iclass 36, count 0 2006.225.08:03:49.13#ibcon#about to read 4, iclass 36, count 0 2006.225.08:03:49.13#ibcon#read 4, iclass 36, count 0 2006.225.08:03:49.13#ibcon#about to read 5, iclass 36, count 0 2006.225.08:03:49.13#ibcon#read 5, iclass 36, count 0 2006.225.08:03:49.13#ibcon#about to read 6, iclass 36, count 0 2006.225.08:03:49.13#ibcon#read 6, iclass 36, count 0 2006.225.08:03:49.13#ibcon#end of sib2, iclass 36, count 0 2006.225.08:03:49.13#ibcon#*mode == 0, iclass 36, count 0 2006.225.08:03:49.13#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.08:03:49.13#ibcon#[25=USB\r\n] 2006.225.08:03:49.13#ibcon#*before write, iclass 36, count 0 2006.225.08:03:49.13#ibcon#enter sib2, iclass 36, count 0 2006.225.08:03:49.13#ibcon#flushed, iclass 36, count 0 2006.225.08:03:49.13#ibcon#about to write, iclass 36, count 0 2006.225.08:03:49.14#ibcon#wrote, iclass 36, count 0 2006.225.08:03:49.14#ibcon#about to read 3, iclass 36, count 0 2006.225.08:03:49.16#ibcon#read 3, iclass 36, count 0 2006.225.08:03:49.16#ibcon#about to read 4, iclass 36, count 0 2006.225.08:03:49.16#ibcon#read 4, iclass 36, count 0 2006.225.08:03:49.16#ibcon#about to read 5, iclass 36, count 0 2006.225.08:03:49.16#ibcon#read 5, iclass 36, count 0 2006.225.08:03:49.16#ibcon#about to read 6, iclass 36, count 0 2006.225.08:03:49.16#ibcon#read 6, iclass 36, count 0 2006.225.08:03:49.16#ibcon#end of sib2, iclass 36, count 0 2006.225.08:03:49.16#ibcon#*after write, iclass 36, count 0 2006.225.08:03:49.16#ibcon#*before return 0, iclass 36, count 0 2006.225.08:03:49.16#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:03:49.16#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:03:49.16#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.08:03:49.16#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.08:03:49.17$vc4f8/valo=8,852.99 2006.225.08:03:49.17#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.08:03:49.17#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.08:03:49.17#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:49.17#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:03:49.17#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:03:49.17#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:03:49.17#ibcon#enter wrdev, iclass 38, count 0 2006.225.08:03:49.17#ibcon#first serial, iclass 38, count 0 2006.225.08:03:49.17#ibcon#enter sib2, iclass 38, count 0 2006.225.08:03:49.17#ibcon#flushed, iclass 38, count 0 2006.225.08:03:49.17#ibcon#about to write, iclass 38, count 0 2006.225.08:03:49.17#ibcon#wrote, iclass 38, count 0 2006.225.08:03:49.17#ibcon#about to read 3, iclass 38, count 0 2006.225.08:03:49.18#ibcon#read 3, iclass 38, count 0 2006.225.08:03:49.18#ibcon#about to read 4, iclass 38, count 0 2006.225.08:03:49.18#ibcon#read 4, iclass 38, count 0 2006.225.08:03:49.18#ibcon#about to read 5, iclass 38, count 0 2006.225.08:03:49.18#ibcon#read 5, iclass 38, count 0 2006.225.08:03:49.18#ibcon#about to read 6, iclass 38, count 0 2006.225.08:03:49.18#ibcon#read 6, iclass 38, count 0 2006.225.08:03:49.18#ibcon#end of sib2, iclass 38, count 0 2006.225.08:03:49.18#ibcon#*mode == 0, iclass 38, count 0 2006.225.08:03:49.18#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.08:03:49.18#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:03:49.18#ibcon#*before write, iclass 38, count 0 2006.225.08:03:49.18#ibcon#enter sib2, iclass 38, count 0 2006.225.08:03:49.18#ibcon#flushed, iclass 38, count 0 2006.225.08:03:49.18#ibcon#about to write, iclass 38, count 0 2006.225.08:03:49.19#ibcon#wrote, iclass 38, count 0 2006.225.08:03:49.19#ibcon#about to read 3, iclass 38, count 0 2006.225.08:03:49.22#ibcon#read 3, iclass 38, count 0 2006.225.08:03:49.22#ibcon#about to read 4, iclass 38, count 0 2006.225.08:03:49.22#ibcon#read 4, iclass 38, count 0 2006.225.08:03:49.22#ibcon#about to read 5, iclass 38, count 0 2006.225.08:03:49.22#ibcon#read 5, iclass 38, count 0 2006.225.08:03:49.22#ibcon#about to read 6, iclass 38, count 0 2006.225.08:03:49.22#ibcon#read 6, iclass 38, count 0 2006.225.08:03:49.22#ibcon#end of sib2, iclass 38, count 0 2006.225.08:03:49.22#ibcon#*after write, iclass 38, count 0 2006.225.08:03:49.22#ibcon#*before return 0, iclass 38, count 0 2006.225.08:03:49.22#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:03:49.22#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:03:49.22#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.08:03:49.22#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.08:03:49.23$vc4f8/va=8,7 2006.225.08:03:49.23#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.225.08:03:49.23#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.225.08:03:49.23#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:49.23#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:03:49.27#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:03:49.27#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:03:49.27#ibcon#enter wrdev, iclass 40, count 2 2006.225.08:03:49.27#ibcon#first serial, iclass 40, count 2 2006.225.08:03:49.27#ibcon#enter sib2, iclass 40, count 2 2006.225.08:03:49.27#ibcon#flushed, iclass 40, count 2 2006.225.08:03:49.27#ibcon#about to write, iclass 40, count 2 2006.225.08:03:49.27#ibcon#wrote, iclass 40, count 2 2006.225.08:03:49.27#ibcon#about to read 3, iclass 40, count 2 2006.225.08:03:49.29#ibcon#read 3, iclass 40, count 2 2006.225.08:03:49.29#ibcon#about to read 4, iclass 40, count 2 2006.225.08:03:49.29#ibcon#read 4, iclass 40, count 2 2006.225.08:03:49.29#ibcon#about to read 5, iclass 40, count 2 2006.225.08:03:49.29#ibcon#read 5, iclass 40, count 2 2006.225.08:03:49.29#ibcon#about to read 6, iclass 40, count 2 2006.225.08:03:49.29#ibcon#read 6, iclass 40, count 2 2006.225.08:03:49.29#ibcon#end of sib2, iclass 40, count 2 2006.225.08:03:49.29#ibcon#*mode == 0, iclass 40, count 2 2006.225.08:03:49.29#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.225.08:03:49.29#ibcon#[25=AT08-07\r\n] 2006.225.08:03:49.29#ibcon#*before write, iclass 40, count 2 2006.225.08:03:49.29#ibcon#enter sib2, iclass 40, count 2 2006.225.08:03:49.29#ibcon#flushed, iclass 40, count 2 2006.225.08:03:49.30#ibcon#about to write, iclass 40, count 2 2006.225.08:03:49.30#ibcon#wrote, iclass 40, count 2 2006.225.08:03:49.30#ibcon#about to read 3, iclass 40, count 2 2006.225.08:03:49.32#ibcon#read 3, iclass 40, count 2 2006.225.08:03:49.32#ibcon#about to read 4, iclass 40, count 2 2006.225.08:03:49.32#ibcon#read 4, iclass 40, count 2 2006.225.08:03:49.32#ibcon#about to read 5, iclass 40, count 2 2006.225.08:03:49.32#ibcon#read 5, iclass 40, count 2 2006.225.08:03:49.32#ibcon#about to read 6, iclass 40, count 2 2006.225.08:03:49.32#ibcon#read 6, iclass 40, count 2 2006.225.08:03:49.32#ibcon#end of sib2, iclass 40, count 2 2006.225.08:03:49.32#ibcon#*after write, iclass 40, count 2 2006.225.08:03:49.32#ibcon#*before return 0, iclass 40, count 2 2006.225.08:03:49.32#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:03:49.32#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:03:49.32#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.225.08:03:49.32#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:49.32#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:03:49.44#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:03:49.44#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:03:49.44#ibcon#enter wrdev, iclass 40, count 0 2006.225.08:03:49.44#ibcon#first serial, iclass 40, count 0 2006.225.08:03:49.44#ibcon#enter sib2, iclass 40, count 0 2006.225.08:03:49.44#ibcon#flushed, iclass 40, count 0 2006.225.08:03:49.44#ibcon#about to write, iclass 40, count 0 2006.225.08:03:49.44#ibcon#wrote, iclass 40, count 0 2006.225.08:03:49.44#ibcon#about to read 3, iclass 40, count 0 2006.225.08:03:49.46#ibcon#read 3, iclass 40, count 0 2006.225.08:03:49.46#ibcon#about to read 4, iclass 40, count 0 2006.225.08:03:49.46#ibcon#read 4, iclass 40, count 0 2006.225.08:03:49.46#ibcon#about to read 5, iclass 40, count 0 2006.225.08:03:49.46#ibcon#read 5, iclass 40, count 0 2006.225.08:03:49.46#ibcon#about to read 6, iclass 40, count 0 2006.225.08:03:49.46#ibcon#read 6, iclass 40, count 0 2006.225.08:03:49.46#ibcon#end of sib2, iclass 40, count 0 2006.225.08:03:49.46#ibcon#*mode == 0, iclass 40, count 0 2006.225.08:03:49.46#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.08:03:49.46#ibcon#[25=USB\r\n] 2006.225.08:03:49.46#ibcon#*before write, iclass 40, count 0 2006.225.08:03:49.46#ibcon#enter sib2, iclass 40, count 0 2006.225.08:03:49.46#ibcon#flushed, iclass 40, count 0 2006.225.08:03:49.46#ibcon#about to write, iclass 40, count 0 2006.225.08:03:49.47#ibcon#wrote, iclass 40, count 0 2006.225.08:03:49.47#ibcon#about to read 3, iclass 40, count 0 2006.225.08:03:49.49#ibcon#read 3, iclass 40, count 0 2006.225.08:03:49.49#ibcon#about to read 4, iclass 40, count 0 2006.225.08:03:49.49#ibcon#read 4, iclass 40, count 0 2006.225.08:03:49.49#ibcon#about to read 5, iclass 40, count 0 2006.225.08:03:49.49#ibcon#read 5, iclass 40, count 0 2006.225.08:03:49.49#ibcon#about to read 6, iclass 40, count 0 2006.225.08:03:49.49#ibcon#read 6, iclass 40, count 0 2006.225.08:03:49.49#ibcon#end of sib2, iclass 40, count 0 2006.225.08:03:49.49#ibcon#*after write, iclass 40, count 0 2006.225.08:03:49.49#ibcon#*before return 0, iclass 40, count 0 2006.225.08:03:49.49#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:03:49.49#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:03:49.49#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.08:03:49.49#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.08:03:49.50$vc4f8/vblo=1,632.99 2006.225.08:03:49.50#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.08:03:49.50#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.08:03:49.50#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:49.50#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:03:49.50#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:03:49.50#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:03:49.50#ibcon#enter wrdev, iclass 4, count 0 2006.225.08:03:49.50#ibcon#first serial, iclass 4, count 0 2006.225.08:03:49.50#ibcon#enter sib2, iclass 4, count 0 2006.225.08:03:49.50#ibcon#flushed, iclass 4, count 0 2006.225.08:03:49.50#ibcon#about to write, iclass 4, count 0 2006.225.08:03:49.50#ibcon#wrote, iclass 4, count 0 2006.225.08:03:49.50#ibcon#about to read 3, iclass 4, count 0 2006.225.08:03:49.52#ibcon#read 3, iclass 4, count 0 2006.225.08:03:49.52#ibcon#about to read 4, iclass 4, count 0 2006.225.08:03:49.52#ibcon#read 4, iclass 4, count 0 2006.225.08:03:49.52#ibcon#about to read 5, iclass 4, count 0 2006.225.08:03:49.52#ibcon#read 5, iclass 4, count 0 2006.225.08:03:49.52#ibcon#about to read 6, iclass 4, count 0 2006.225.08:03:49.52#ibcon#read 6, iclass 4, count 0 2006.225.08:03:49.52#ibcon#end of sib2, iclass 4, count 0 2006.225.08:03:49.52#ibcon#*mode == 0, iclass 4, count 0 2006.225.08:03:49.52#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.08:03:49.52#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:03:49.52#ibcon#*before write, iclass 4, count 0 2006.225.08:03:49.52#ibcon#enter sib2, iclass 4, count 0 2006.225.08:03:49.52#ibcon#flushed, iclass 4, count 0 2006.225.08:03:49.52#ibcon#about to write, iclass 4, count 0 2006.225.08:03:49.52#ibcon#wrote, iclass 4, count 0 2006.225.08:03:49.52#ibcon#about to read 3, iclass 4, count 0 2006.225.08:03:49.56#ibcon#read 3, iclass 4, count 0 2006.225.08:03:49.56#ibcon#about to read 4, iclass 4, count 0 2006.225.08:03:49.56#ibcon#read 4, iclass 4, count 0 2006.225.08:03:49.56#ibcon#about to read 5, iclass 4, count 0 2006.225.08:03:49.56#ibcon#read 5, iclass 4, count 0 2006.225.08:03:49.56#ibcon#about to read 6, iclass 4, count 0 2006.225.08:03:49.56#ibcon#read 6, iclass 4, count 0 2006.225.08:03:49.56#ibcon#end of sib2, iclass 4, count 0 2006.225.08:03:49.56#ibcon#*after write, iclass 4, count 0 2006.225.08:03:49.56#ibcon#*before return 0, iclass 4, count 0 2006.225.08:03:49.56#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:03:49.56#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:03:49.57#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.08:03:49.57#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.08:03:49.57$vc4f8/vb=1,4 2006.225.08:03:49.57#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.225.08:03:49.57#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.225.08:03:49.57#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:49.57#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:03:49.57#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:03:49.57#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:03:49.57#ibcon#enter wrdev, iclass 6, count 2 2006.225.08:03:49.57#ibcon#first serial, iclass 6, count 2 2006.225.08:03:49.57#ibcon#enter sib2, iclass 6, count 2 2006.225.08:03:49.57#ibcon#flushed, iclass 6, count 2 2006.225.08:03:49.57#ibcon#about to write, iclass 6, count 2 2006.225.08:03:49.57#ibcon#wrote, iclass 6, count 2 2006.225.08:03:49.57#ibcon#about to read 3, iclass 6, count 2 2006.225.08:03:49.58#ibcon#read 3, iclass 6, count 2 2006.225.08:03:49.58#ibcon#about to read 4, iclass 6, count 2 2006.225.08:03:49.58#ibcon#read 4, iclass 6, count 2 2006.225.08:03:49.58#ibcon#about to read 5, iclass 6, count 2 2006.225.08:03:49.58#ibcon#read 5, iclass 6, count 2 2006.225.08:03:49.58#ibcon#about to read 6, iclass 6, count 2 2006.225.08:03:49.58#ibcon#read 6, iclass 6, count 2 2006.225.08:03:49.58#ibcon#end of sib2, iclass 6, count 2 2006.225.08:03:49.58#ibcon#*mode == 0, iclass 6, count 2 2006.225.08:03:49.58#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.225.08:03:49.58#ibcon#[27=AT01-04\r\n] 2006.225.08:03:49.58#ibcon#*before write, iclass 6, count 2 2006.225.08:03:49.58#ibcon#enter sib2, iclass 6, count 2 2006.225.08:03:49.58#ibcon#flushed, iclass 6, count 2 2006.225.08:03:49.58#ibcon#about to write, iclass 6, count 2 2006.225.08:03:49.59#ibcon#wrote, iclass 6, count 2 2006.225.08:03:49.59#ibcon#about to read 3, iclass 6, count 2 2006.225.08:03:49.61#ibcon#read 3, iclass 6, count 2 2006.225.08:03:49.61#ibcon#about to read 4, iclass 6, count 2 2006.225.08:03:49.61#ibcon#read 4, iclass 6, count 2 2006.225.08:03:49.61#ibcon#about to read 5, iclass 6, count 2 2006.225.08:03:49.61#ibcon#read 5, iclass 6, count 2 2006.225.08:03:49.61#ibcon#about to read 6, iclass 6, count 2 2006.225.08:03:49.61#ibcon#read 6, iclass 6, count 2 2006.225.08:03:49.61#ibcon#end of sib2, iclass 6, count 2 2006.225.08:03:49.61#ibcon#*after write, iclass 6, count 2 2006.225.08:03:49.61#ibcon#*before return 0, iclass 6, count 2 2006.225.08:03:49.61#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:03:49.61#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:03:49.61#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.225.08:03:49.61#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:49.61#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:03:49.73#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:03:49.73#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:03:49.73#ibcon#enter wrdev, iclass 6, count 0 2006.225.08:03:49.73#ibcon#first serial, iclass 6, count 0 2006.225.08:03:49.73#ibcon#enter sib2, iclass 6, count 0 2006.225.08:03:49.73#ibcon#flushed, iclass 6, count 0 2006.225.08:03:49.73#ibcon#about to write, iclass 6, count 0 2006.225.08:03:49.73#ibcon#wrote, iclass 6, count 0 2006.225.08:03:49.73#ibcon#about to read 3, iclass 6, count 0 2006.225.08:03:49.75#ibcon#read 3, iclass 6, count 0 2006.225.08:03:49.75#ibcon#about to read 4, iclass 6, count 0 2006.225.08:03:49.75#ibcon#read 4, iclass 6, count 0 2006.225.08:03:49.75#ibcon#about to read 5, iclass 6, count 0 2006.225.08:03:49.75#ibcon#read 5, iclass 6, count 0 2006.225.08:03:49.75#ibcon#about to read 6, iclass 6, count 0 2006.225.08:03:49.75#ibcon#read 6, iclass 6, count 0 2006.225.08:03:49.75#ibcon#end of sib2, iclass 6, count 0 2006.225.08:03:49.75#ibcon#*mode == 0, iclass 6, count 0 2006.225.08:03:49.75#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.08:03:49.75#ibcon#[27=USB\r\n] 2006.225.08:03:49.75#ibcon#*before write, iclass 6, count 0 2006.225.08:03:49.75#ibcon#enter sib2, iclass 6, count 0 2006.225.08:03:49.75#ibcon#flushed, iclass 6, count 0 2006.225.08:03:49.75#ibcon#about to write, iclass 6, count 0 2006.225.08:03:49.76#ibcon#wrote, iclass 6, count 0 2006.225.08:03:49.76#ibcon#about to read 3, iclass 6, count 0 2006.225.08:03:49.78#ibcon#read 3, iclass 6, count 0 2006.225.08:03:49.78#ibcon#about to read 4, iclass 6, count 0 2006.225.08:03:49.78#ibcon#read 4, iclass 6, count 0 2006.225.08:03:49.78#ibcon#about to read 5, iclass 6, count 0 2006.225.08:03:49.78#ibcon#read 5, iclass 6, count 0 2006.225.08:03:49.78#ibcon#about to read 6, iclass 6, count 0 2006.225.08:03:49.78#ibcon#read 6, iclass 6, count 0 2006.225.08:03:49.78#ibcon#end of sib2, iclass 6, count 0 2006.225.08:03:49.78#ibcon#*after write, iclass 6, count 0 2006.225.08:03:49.78#ibcon#*before return 0, iclass 6, count 0 2006.225.08:03:49.78#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:03:49.78#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:03:49.78#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.08:03:49.78#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.08:03:49.79$vc4f8/vblo=2,640.99 2006.225.08:03:49.79#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.08:03:49.79#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.08:03:49.79#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:49.79#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:03:49.79#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:03:49.79#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:03:49.79#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:03:49.79#ibcon#first serial, iclass 10, count 0 2006.225.08:03:49.79#ibcon#enter sib2, iclass 10, count 0 2006.225.08:03:49.79#ibcon#flushed, iclass 10, count 0 2006.225.08:03:49.79#ibcon#about to write, iclass 10, count 0 2006.225.08:03:49.79#ibcon#wrote, iclass 10, count 0 2006.225.08:03:49.79#ibcon#about to read 3, iclass 10, count 0 2006.225.08:03:49.80#ibcon#read 3, iclass 10, count 0 2006.225.08:03:49.80#ibcon#about to read 4, iclass 10, count 0 2006.225.08:03:49.80#ibcon#read 4, iclass 10, count 0 2006.225.08:03:49.80#ibcon#about to read 5, iclass 10, count 0 2006.225.08:03:49.80#ibcon#read 5, iclass 10, count 0 2006.225.08:03:49.80#ibcon#about to read 6, iclass 10, count 0 2006.225.08:03:49.80#ibcon#read 6, iclass 10, count 0 2006.225.08:03:49.80#ibcon#end of sib2, iclass 10, count 0 2006.225.08:03:49.80#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:03:49.80#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:03:49.80#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:03:49.80#ibcon#*before write, iclass 10, count 0 2006.225.08:03:49.80#ibcon#enter sib2, iclass 10, count 0 2006.225.08:03:49.80#ibcon#flushed, iclass 10, count 0 2006.225.08:03:49.80#ibcon#about to write, iclass 10, count 0 2006.225.08:03:49.81#ibcon#wrote, iclass 10, count 0 2006.225.08:03:49.81#ibcon#about to read 3, iclass 10, count 0 2006.225.08:03:49.84#ibcon#read 3, iclass 10, count 0 2006.225.08:03:49.84#ibcon#about to read 4, iclass 10, count 0 2006.225.08:03:49.84#ibcon#read 4, iclass 10, count 0 2006.225.08:03:49.84#ibcon#about to read 5, iclass 10, count 0 2006.225.08:03:49.84#ibcon#read 5, iclass 10, count 0 2006.225.08:03:49.84#ibcon#about to read 6, iclass 10, count 0 2006.225.08:03:49.84#ibcon#read 6, iclass 10, count 0 2006.225.08:03:49.84#ibcon#end of sib2, iclass 10, count 0 2006.225.08:03:49.84#ibcon#*after write, iclass 10, count 0 2006.225.08:03:49.84#ibcon#*before return 0, iclass 10, count 0 2006.225.08:03:49.84#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:03:49.84#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:03:49.84#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:03:49.84#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:03:49.85$vc4f8/vb=2,4 2006.225.08:03:49.85#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.08:03:49.85#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.08:03:49.85#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:49.85#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:03:49.89#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:03:49.89#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:03:49.89#ibcon#enter wrdev, iclass 12, count 2 2006.225.08:03:49.89#ibcon#first serial, iclass 12, count 2 2006.225.08:03:49.89#ibcon#enter sib2, iclass 12, count 2 2006.225.08:03:49.89#ibcon#flushed, iclass 12, count 2 2006.225.08:03:49.89#ibcon#about to write, iclass 12, count 2 2006.225.08:03:49.89#ibcon#wrote, iclass 12, count 2 2006.225.08:03:49.89#ibcon#about to read 3, iclass 12, count 2 2006.225.08:03:49.91#ibcon#read 3, iclass 12, count 2 2006.225.08:03:49.91#ibcon#about to read 4, iclass 12, count 2 2006.225.08:03:49.91#ibcon#read 4, iclass 12, count 2 2006.225.08:03:49.91#ibcon#about to read 5, iclass 12, count 2 2006.225.08:03:49.91#ibcon#read 5, iclass 12, count 2 2006.225.08:03:49.91#ibcon#about to read 6, iclass 12, count 2 2006.225.08:03:49.91#ibcon#read 6, iclass 12, count 2 2006.225.08:03:49.91#ibcon#end of sib2, iclass 12, count 2 2006.225.08:03:49.91#ibcon#*mode == 0, iclass 12, count 2 2006.225.08:03:49.91#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.08:03:49.91#ibcon#[27=AT02-04\r\n] 2006.225.08:03:49.91#ibcon#*before write, iclass 12, count 2 2006.225.08:03:49.91#ibcon#enter sib2, iclass 12, count 2 2006.225.08:03:49.91#ibcon#flushed, iclass 12, count 2 2006.225.08:03:49.91#ibcon#about to write, iclass 12, count 2 2006.225.08:03:49.92#ibcon#wrote, iclass 12, count 2 2006.225.08:03:49.92#ibcon#about to read 3, iclass 12, count 2 2006.225.08:03:49.94#ibcon#read 3, iclass 12, count 2 2006.225.08:03:49.94#ibcon#about to read 4, iclass 12, count 2 2006.225.08:03:49.94#ibcon#read 4, iclass 12, count 2 2006.225.08:03:49.94#ibcon#about to read 5, iclass 12, count 2 2006.225.08:03:49.94#ibcon#read 5, iclass 12, count 2 2006.225.08:03:49.94#ibcon#about to read 6, iclass 12, count 2 2006.225.08:03:49.94#ibcon#read 6, iclass 12, count 2 2006.225.08:03:49.94#ibcon#end of sib2, iclass 12, count 2 2006.225.08:03:49.94#ibcon#*after write, iclass 12, count 2 2006.225.08:03:49.94#ibcon#*before return 0, iclass 12, count 2 2006.225.08:03:49.94#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:03:49.94#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:03:49.94#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.08:03:49.94#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:49.94#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:03:50.06#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:03:50.06#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:03:50.06#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:03:50.06#ibcon#first serial, iclass 12, count 0 2006.225.08:03:50.06#ibcon#enter sib2, iclass 12, count 0 2006.225.08:03:50.06#ibcon#flushed, iclass 12, count 0 2006.225.08:03:50.06#ibcon#about to write, iclass 12, count 0 2006.225.08:03:50.06#ibcon#wrote, iclass 12, count 0 2006.225.08:03:50.06#ibcon#about to read 3, iclass 12, count 0 2006.225.08:03:50.08#ibcon#read 3, iclass 12, count 0 2006.225.08:03:50.08#ibcon#about to read 4, iclass 12, count 0 2006.225.08:03:50.08#ibcon#read 4, iclass 12, count 0 2006.225.08:03:50.08#ibcon#about to read 5, iclass 12, count 0 2006.225.08:03:50.08#ibcon#read 5, iclass 12, count 0 2006.225.08:03:50.08#ibcon#about to read 6, iclass 12, count 0 2006.225.08:03:50.08#ibcon#read 6, iclass 12, count 0 2006.225.08:03:50.08#ibcon#end of sib2, iclass 12, count 0 2006.225.08:03:50.08#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:03:50.08#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:03:50.08#ibcon#[27=USB\r\n] 2006.225.08:03:50.08#ibcon#*before write, iclass 12, count 0 2006.225.08:03:50.08#ibcon#enter sib2, iclass 12, count 0 2006.225.08:03:50.08#ibcon#flushed, iclass 12, count 0 2006.225.08:03:50.08#ibcon#about to write, iclass 12, count 0 2006.225.08:03:50.09#ibcon#wrote, iclass 12, count 0 2006.225.08:03:50.09#ibcon#about to read 3, iclass 12, count 0 2006.225.08:03:50.11#ibcon#read 3, iclass 12, count 0 2006.225.08:03:50.11#ibcon#about to read 4, iclass 12, count 0 2006.225.08:03:50.11#ibcon#read 4, iclass 12, count 0 2006.225.08:03:50.11#ibcon#about to read 5, iclass 12, count 0 2006.225.08:03:50.11#ibcon#read 5, iclass 12, count 0 2006.225.08:03:50.11#ibcon#about to read 6, iclass 12, count 0 2006.225.08:03:50.11#ibcon#read 6, iclass 12, count 0 2006.225.08:03:50.11#ibcon#end of sib2, iclass 12, count 0 2006.225.08:03:50.11#ibcon#*after write, iclass 12, count 0 2006.225.08:03:50.11#ibcon#*before return 0, iclass 12, count 0 2006.225.08:03:50.11#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:03:50.11#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:03:50.11#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:03:50.11#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:03:50.12$vc4f8/vblo=3,656.99 2006.225.08:03:50.12#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.08:03:50.12#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.08:03:50.12#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:50.12#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:03:50.12#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:03:50.12#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:03:50.12#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:03:50.12#ibcon#first serial, iclass 14, count 0 2006.225.08:03:50.12#ibcon#enter sib2, iclass 14, count 0 2006.225.08:03:50.12#ibcon#flushed, iclass 14, count 0 2006.225.08:03:50.12#ibcon#about to write, iclass 14, count 0 2006.225.08:03:50.12#ibcon#wrote, iclass 14, count 0 2006.225.08:03:50.12#ibcon#about to read 3, iclass 14, count 0 2006.225.08:03:50.13#ibcon#read 3, iclass 14, count 0 2006.225.08:03:50.13#ibcon#about to read 4, iclass 14, count 0 2006.225.08:03:50.13#ibcon#read 4, iclass 14, count 0 2006.225.08:03:50.13#ibcon#about to read 5, iclass 14, count 0 2006.225.08:03:50.13#ibcon#read 5, iclass 14, count 0 2006.225.08:03:50.13#ibcon#about to read 6, iclass 14, count 0 2006.225.08:03:50.13#ibcon#read 6, iclass 14, count 0 2006.225.08:03:50.13#ibcon#end of sib2, iclass 14, count 0 2006.225.08:03:50.13#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:03:50.13#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:03:50.13#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:03:50.13#ibcon#*before write, iclass 14, count 0 2006.225.08:03:50.13#ibcon#enter sib2, iclass 14, count 0 2006.225.08:03:50.13#ibcon#flushed, iclass 14, count 0 2006.225.08:03:50.13#ibcon#about to write, iclass 14, count 0 2006.225.08:03:50.14#ibcon#wrote, iclass 14, count 0 2006.225.08:03:50.14#ibcon#about to read 3, iclass 14, count 0 2006.225.08:03:50.17#ibcon#read 3, iclass 14, count 0 2006.225.08:03:50.17#ibcon#about to read 4, iclass 14, count 0 2006.225.08:03:50.17#ibcon#read 4, iclass 14, count 0 2006.225.08:03:50.17#ibcon#about to read 5, iclass 14, count 0 2006.225.08:03:50.17#ibcon#read 5, iclass 14, count 0 2006.225.08:03:50.17#ibcon#about to read 6, iclass 14, count 0 2006.225.08:03:50.17#ibcon#read 6, iclass 14, count 0 2006.225.08:03:50.17#ibcon#end of sib2, iclass 14, count 0 2006.225.08:03:50.17#ibcon#*after write, iclass 14, count 0 2006.225.08:03:50.17#ibcon#*before return 0, iclass 14, count 0 2006.225.08:03:50.17#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:03:50.17#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:03:50.17#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:03:50.18#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:03:50.18$vc4f8/vb=3,4 2006.225.08:03:50.18#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.08:03:50.18#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.08:03:50.18#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:50.18#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:03:50.22#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:03:50.22#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:03:50.22#ibcon#enter wrdev, iclass 16, count 2 2006.225.08:03:50.22#ibcon#first serial, iclass 16, count 2 2006.225.08:03:50.22#ibcon#enter sib2, iclass 16, count 2 2006.225.08:03:50.22#ibcon#flushed, iclass 16, count 2 2006.225.08:03:50.22#ibcon#about to write, iclass 16, count 2 2006.225.08:03:50.22#ibcon#wrote, iclass 16, count 2 2006.225.08:03:50.22#ibcon#about to read 3, iclass 16, count 2 2006.225.08:03:50.24#ibcon#read 3, iclass 16, count 2 2006.225.08:03:50.24#ibcon#about to read 4, iclass 16, count 2 2006.225.08:03:50.24#ibcon#read 4, iclass 16, count 2 2006.225.08:03:50.24#ibcon#about to read 5, iclass 16, count 2 2006.225.08:03:50.24#ibcon#read 5, iclass 16, count 2 2006.225.08:03:50.24#ibcon#about to read 6, iclass 16, count 2 2006.225.08:03:50.24#ibcon#read 6, iclass 16, count 2 2006.225.08:03:50.24#ibcon#end of sib2, iclass 16, count 2 2006.225.08:03:50.24#ibcon#*mode == 0, iclass 16, count 2 2006.225.08:03:50.24#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.08:03:50.24#ibcon#[27=AT03-04\r\n] 2006.225.08:03:50.24#ibcon#*before write, iclass 16, count 2 2006.225.08:03:50.24#ibcon#enter sib2, iclass 16, count 2 2006.225.08:03:50.24#ibcon#flushed, iclass 16, count 2 2006.225.08:03:50.24#ibcon#about to write, iclass 16, count 2 2006.225.08:03:50.25#ibcon#wrote, iclass 16, count 2 2006.225.08:03:50.25#ibcon#about to read 3, iclass 16, count 2 2006.225.08:03:50.27#ibcon#read 3, iclass 16, count 2 2006.225.08:03:50.27#ibcon#about to read 4, iclass 16, count 2 2006.225.08:03:50.27#ibcon#read 4, iclass 16, count 2 2006.225.08:03:50.27#ibcon#about to read 5, iclass 16, count 2 2006.225.08:03:50.27#ibcon#read 5, iclass 16, count 2 2006.225.08:03:50.27#ibcon#about to read 6, iclass 16, count 2 2006.225.08:03:50.27#ibcon#read 6, iclass 16, count 2 2006.225.08:03:50.27#ibcon#end of sib2, iclass 16, count 2 2006.225.08:03:50.27#ibcon#*after write, iclass 16, count 2 2006.225.08:03:50.27#ibcon#*before return 0, iclass 16, count 2 2006.225.08:03:50.27#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:03:50.27#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:03:50.27#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.08:03:50.27#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:50.27#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:03:50.39#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:03:50.39#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:03:50.39#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:03:50.39#ibcon#first serial, iclass 16, count 0 2006.225.08:03:50.39#ibcon#enter sib2, iclass 16, count 0 2006.225.08:03:50.39#ibcon#flushed, iclass 16, count 0 2006.225.08:03:50.39#ibcon#about to write, iclass 16, count 0 2006.225.08:03:50.39#ibcon#wrote, iclass 16, count 0 2006.225.08:03:50.39#ibcon#about to read 3, iclass 16, count 0 2006.225.08:03:50.41#ibcon#read 3, iclass 16, count 0 2006.225.08:03:50.41#ibcon#about to read 4, iclass 16, count 0 2006.225.08:03:50.41#ibcon#read 4, iclass 16, count 0 2006.225.08:03:50.41#ibcon#about to read 5, iclass 16, count 0 2006.225.08:03:50.41#ibcon#read 5, iclass 16, count 0 2006.225.08:03:50.41#ibcon#about to read 6, iclass 16, count 0 2006.225.08:03:50.41#ibcon#read 6, iclass 16, count 0 2006.225.08:03:50.41#ibcon#end of sib2, iclass 16, count 0 2006.225.08:03:50.41#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:03:50.41#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:03:50.41#ibcon#[27=USB\r\n] 2006.225.08:03:50.41#ibcon#*before write, iclass 16, count 0 2006.225.08:03:50.41#ibcon#enter sib2, iclass 16, count 0 2006.225.08:03:50.41#ibcon#flushed, iclass 16, count 0 2006.225.08:03:50.41#ibcon#about to write, iclass 16, count 0 2006.225.08:03:50.42#ibcon#wrote, iclass 16, count 0 2006.225.08:03:50.42#ibcon#about to read 3, iclass 16, count 0 2006.225.08:03:50.44#ibcon#read 3, iclass 16, count 0 2006.225.08:03:50.44#ibcon#about to read 4, iclass 16, count 0 2006.225.08:03:50.44#ibcon#read 4, iclass 16, count 0 2006.225.08:03:50.44#ibcon#about to read 5, iclass 16, count 0 2006.225.08:03:50.44#ibcon#read 5, iclass 16, count 0 2006.225.08:03:50.44#ibcon#about to read 6, iclass 16, count 0 2006.225.08:03:50.44#ibcon#read 6, iclass 16, count 0 2006.225.08:03:50.44#ibcon#end of sib2, iclass 16, count 0 2006.225.08:03:50.44#ibcon#*after write, iclass 16, count 0 2006.225.08:03:50.44#ibcon#*before return 0, iclass 16, count 0 2006.225.08:03:50.44#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:03:50.44#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:03:50.44#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:03:50.44#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:03:50.45$vc4f8/vblo=4,712.99 2006.225.08:03:50.45#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.08:03:50.45#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.08:03:50.45#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:50.45#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:03:50.45#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:03:50.45#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:03:50.45#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:03:50.45#ibcon#first serial, iclass 18, count 0 2006.225.08:03:50.45#ibcon#enter sib2, iclass 18, count 0 2006.225.08:03:50.45#ibcon#flushed, iclass 18, count 0 2006.225.08:03:50.45#ibcon#about to write, iclass 18, count 0 2006.225.08:03:50.45#ibcon#wrote, iclass 18, count 0 2006.225.08:03:50.45#ibcon#about to read 3, iclass 18, count 0 2006.225.08:03:50.46#ibcon#read 3, iclass 18, count 0 2006.225.08:03:50.46#ibcon#about to read 4, iclass 18, count 0 2006.225.08:03:50.46#ibcon#read 4, iclass 18, count 0 2006.225.08:03:50.46#ibcon#about to read 5, iclass 18, count 0 2006.225.08:03:50.46#ibcon#read 5, iclass 18, count 0 2006.225.08:03:50.46#ibcon#about to read 6, iclass 18, count 0 2006.225.08:03:50.46#ibcon#read 6, iclass 18, count 0 2006.225.08:03:50.46#ibcon#end of sib2, iclass 18, count 0 2006.225.08:03:50.46#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:03:50.46#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:03:50.46#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:03:50.46#ibcon#*before write, iclass 18, count 0 2006.225.08:03:50.46#ibcon#enter sib2, iclass 18, count 0 2006.225.08:03:50.46#ibcon#flushed, iclass 18, count 0 2006.225.08:03:50.46#ibcon#about to write, iclass 18, count 0 2006.225.08:03:50.47#ibcon#wrote, iclass 18, count 0 2006.225.08:03:50.47#ibcon#about to read 3, iclass 18, count 0 2006.225.08:03:50.50#ibcon#read 3, iclass 18, count 0 2006.225.08:03:50.50#ibcon#about to read 4, iclass 18, count 0 2006.225.08:03:50.50#ibcon#read 4, iclass 18, count 0 2006.225.08:03:50.50#ibcon#about to read 5, iclass 18, count 0 2006.225.08:03:50.50#ibcon#read 5, iclass 18, count 0 2006.225.08:03:50.50#ibcon#about to read 6, iclass 18, count 0 2006.225.08:03:50.50#ibcon#read 6, iclass 18, count 0 2006.225.08:03:50.50#ibcon#end of sib2, iclass 18, count 0 2006.225.08:03:50.50#ibcon#*after write, iclass 18, count 0 2006.225.08:03:50.50#ibcon#*before return 0, iclass 18, count 0 2006.225.08:03:50.50#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:03:50.50#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:03:50.50#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:03:50.50#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:03:50.51$vc4f8/vb=4,4 2006.225.08:03:50.51#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.08:03:50.51#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.08:03:50.51#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:50.51#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:03:50.55#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:03:50.55#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:03:50.55#ibcon#enter wrdev, iclass 20, count 2 2006.225.08:03:50.55#ibcon#first serial, iclass 20, count 2 2006.225.08:03:50.55#ibcon#enter sib2, iclass 20, count 2 2006.225.08:03:50.55#ibcon#flushed, iclass 20, count 2 2006.225.08:03:50.55#ibcon#about to write, iclass 20, count 2 2006.225.08:03:50.55#ibcon#wrote, iclass 20, count 2 2006.225.08:03:50.55#ibcon#about to read 3, iclass 20, count 2 2006.225.08:03:50.57#ibcon#read 3, iclass 20, count 2 2006.225.08:03:50.57#ibcon#about to read 4, iclass 20, count 2 2006.225.08:03:50.57#ibcon#read 4, iclass 20, count 2 2006.225.08:03:50.57#ibcon#about to read 5, iclass 20, count 2 2006.225.08:03:50.57#ibcon#read 5, iclass 20, count 2 2006.225.08:03:50.57#ibcon#about to read 6, iclass 20, count 2 2006.225.08:03:50.57#ibcon#read 6, iclass 20, count 2 2006.225.08:03:50.57#ibcon#end of sib2, iclass 20, count 2 2006.225.08:03:50.57#ibcon#*mode == 0, iclass 20, count 2 2006.225.08:03:50.57#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.08:03:50.57#ibcon#[27=AT04-04\r\n] 2006.225.08:03:50.57#ibcon#*before write, iclass 20, count 2 2006.225.08:03:50.57#ibcon#enter sib2, iclass 20, count 2 2006.225.08:03:50.57#ibcon#flushed, iclass 20, count 2 2006.225.08:03:50.57#ibcon#about to write, iclass 20, count 2 2006.225.08:03:50.58#ibcon#wrote, iclass 20, count 2 2006.225.08:03:50.58#ibcon#about to read 3, iclass 20, count 2 2006.225.08:03:50.60#ibcon#read 3, iclass 20, count 2 2006.225.08:03:50.60#ibcon#about to read 4, iclass 20, count 2 2006.225.08:03:50.60#ibcon#read 4, iclass 20, count 2 2006.225.08:03:50.60#ibcon#about to read 5, iclass 20, count 2 2006.225.08:03:50.60#ibcon#read 5, iclass 20, count 2 2006.225.08:03:50.60#ibcon#about to read 6, iclass 20, count 2 2006.225.08:03:50.60#ibcon#read 6, iclass 20, count 2 2006.225.08:03:50.60#ibcon#end of sib2, iclass 20, count 2 2006.225.08:03:50.60#ibcon#*after write, iclass 20, count 2 2006.225.08:03:50.60#ibcon#*before return 0, iclass 20, count 2 2006.225.08:03:50.60#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:03:50.60#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:03:50.60#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.08:03:50.60#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:50.60#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:03:50.72#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:03:50.72#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:03:50.72#ibcon#enter wrdev, iclass 20, count 0 2006.225.08:03:50.72#ibcon#first serial, iclass 20, count 0 2006.225.08:03:50.72#ibcon#enter sib2, iclass 20, count 0 2006.225.08:03:50.72#ibcon#flushed, iclass 20, count 0 2006.225.08:03:50.72#ibcon#about to write, iclass 20, count 0 2006.225.08:03:50.72#ibcon#wrote, iclass 20, count 0 2006.225.08:03:50.72#ibcon#about to read 3, iclass 20, count 0 2006.225.08:03:50.74#ibcon#read 3, iclass 20, count 0 2006.225.08:03:50.74#ibcon#about to read 4, iclass 20, count 0 2006.225.08:03:50.74#ibcon#read 4, iclass 20, count 0 2006.225.08:03:50.74#ibcon#about to read 5, iclass 20, count 0 2006.225.08:03:50.74#ibcon#read 5, iclass 20, count 0 2006.225.08:03:50.74#ibcon#about to read 6, iclass 20, count 0 2006.225.08:03:50.74#ibcon#read 6, iclass 20, count 0 2006.225.08:03:50.74#ibcon#end of sib2, iclass 20, count 0 2006.225.08:03:50.74#ibcon#*mode == 0, iclass 20, count 0 2006.225.08:03:50.74#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.08:03:50.74#ibcon#[27=USB\r\n] 2006.225.08:03:50.74#ibcon#*before write, iclass 20, count 0 2006.225.08:03:50.74#ibcon#enter sib2, iclass 20, count 0 2006.225.08:03:50.74#ibcon#flushed, iclass 20, count 0 2006.225.08:03:50.74#ibcon#about to write, iclass 20, count 0 2006.225.08:03:50.75#ibcon#wrote, iclass 20, count 0 2006.225.08:03:50.75#ibcon#about to read 3, iclass 20, count 0 2006.225.08:03:50.77#ibcon#read 3, iclass 20, count 0 2006.225.08:03:50.77#ibcon#about to read 4, iclass 20, count 0 2006.225.08:03:50.77#ibcon#read 4, iclass 20, count 0 2006.225.08:03:50.77#ibcon#about to read 5, iclass 20, count 0 2006.225.08:03:50.77#ibcon#read 5, iclass 20, count 0 2006.225.08:03:50.77#ibcon#about to read 6, iclass 20, count 0 2006.225.08:03:50.77#ibcon#read 6, iclass 20, count 0 2006.225.08:03:50.77#ibcon#end of sib2, iclass 20, count 0 2006.225.08:03:50.77#ibcon#*after write, iclass 20, count 0 2006.225.08:03:50.77#ibcon#*before return 0, iclass 20, count 0 2006.225.08:03:50.77#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:03:50.77#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:03:50.77#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.08:03:50.77#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.08:03:50.78$vc4f8/vblo=5,744.99 2006.225.08:03:50.78#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.08:03:50.78#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.08:03:50.78#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:50.78#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:03:50.78#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:03:50.78#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:03:50.78#ibcon#enter wrdev, iclass 22, count 0 2006.225.08:03:50.78#ibcon#first serial, iclass 22, count 0 2006.225.08:03:50.78#ibcon#enter sib2, iclass 22, count 0 2006.225.08:03:50.78#ibcon#flushed, iclass 22, count 0 2006.225.08:03:50.78#ibcon#about to write, iclass 22, count 0 2006.225.08:03:50.78#ibcon#wrote, iclass 22, count 0 2006.225.08:03:50.78#ibcon#about to read 3, iclass 22, count 0 2006.225.08:03:50.79#ibcon#read 3, iclass 22, count 0 2006.225.08:03:50.79#ibcon#about to read 4, iclass 22, count 0 2006.225.08:03:50.79#ibcon#read 4, iclass 22, count 0 2006.225.08:03:50.79#ibcon#about to read 5, iclass 22, count 0 2006.225.08:03:50.79#ibcon#read 5, iclass 22, count 0 2006.225.08:03:50.79#ibcon#about to read 6, iclass 22, count 0 2006.225.08:03:50.79#ibcon#read 6, iclass 22, count 0 2006.225.08:03:50.79#ibcon#end of sib2, iclass 22, count 0 2006.225.08:03:50.79#ibcon#*mode == 0, iclass 22, count 0 2006.225.08:03:50.79#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.08:03:50.79#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:03:50.79#ibcon#*before write, iclass 22, count 0 2006.225.08:03:50.79#ibcon#enter sib2, iclass 22, count 0 2006.225.08:03:50.79#ibcon#flushed, iclass 22, count 0 2006.225.08:03:50.79#ibcon#about to write, iclass 22, count 0 2006.225.08:03:50.80#ibcon#wrote, iclass 22, count 0 2006.225.08:03:50.80#ibcon#about to read 3, iclass 22, count 0 2006.225.08:03:50.83#ibcon#read 3, iclass 22, count 0 2006.225.08:03:50.83#ibcon#about to read 4, iclass 22, count 0 2006.225.08:03:50.83#ibcon#read 4, iclass 22, count 0 2006.225.08:03:50.83#ibcon#about to read 5, iclass 22, count 0 2006.225.08:03:50.83#ibcon#read 5, iclass 22, count 0 2006.225.08:03:50.83#ibcon#about to read 6, iclass 22, count 0 2006.225.08:03:50.83#ibcon#read 6, iclass 22, count 0 2006.225.08:03:50.83#ibcon#end of sib2, iclass 22, count 0 2006.225.08:03:50.83#ibcon#*after write, iclass 22, count 0 2006.225.08:03:50.83#ibcon#*before return 0, iclass 22, count 0 2006.225.08:03:50.83#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:03:50.83#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:03:50.83#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.08:03:50.83#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.08:03:50.84$vc4f8/vb=5,4 2006.225.08:03:50.84#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.08:03:50.84#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.08:03:50.84#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:50.84#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:03:50.88#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:03:50.88#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:03:50.88#ibcon#enter wrdev, iclass 24, count 2 2006.225.08:03:50.88#ibcon#first serial, iclass 24, count 2 2006.225.08:03:50.88#ibcon#enter sib2, iclass 24, count 2 2006.225.08:03:50.88#ibcon#flushed, iclass 24, count 2 2006.225.08:03:50.88#ibcon#about to write, iclass 24, count 2 2006.225.08:03:50.88#ibcon#wrote, iclass 24, count 2 2006.225.08:03:50.88#ibcon#about to read 3, iclass 24, count 2 2006.225.08:03:50.90#ibcon#read 3, iclass 24, count 2 2006.225.08:03:50.90#ibcon#about to read 4, iclass 24, count 2 2006.225.08:03:50.90#ibcon#read 4, iclass 24, count 2 2006.225.08:03:50.90#ibcon#about to read 5, iclass 24, count 2 2006.225.08:03:50.90#ibcon#read 5, iclass 24, count 2 2006.225.08:03:50.90#ibcon#about to read 6, iclass 24, count 2 2006.225.08:03:50.90#ibcon#read 6, iclass 24, count 2 2006.225.08:03:50.90#ibcon#end of sib2, iclass 24, count 2 2006.225.08:03:50.90#ibcon#*mode == 0, iclass 24, count 2 2006.225.08:03:50.90#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.08:03:50.90#ibcon#[27=AT05-04\r\n] 2006.225.08:03:50.90#ibcon#*before write, iclass 24, count 2 2006.225.08:03:50.90#ibcon#enter sib2, iclass 24, count 2 2006.225.08:03:50.90#ibcon#flushed, iclass 24, count 2 2006.225.08:03:50.90#ibcon#about to write, iclass 24, count 2 2006.225.08:03:50.91#ibcon#wrote, iclass 24, count 2 2006.225.08:03:50.91#ibcon#about to read 3, iclass 24, count 2 2006.225.08:03:50.93#ibcon#read 3, iclass 24, count 2 2006.225.08:03:50.93#ibcon#about to read 4, iclass 24, count 2 2006.225.08:03:50.93#ibcon#read 4, iclass 24, count 2 2006.225.08:03:50.93#ibcon#about to read 5, iclass 24, count 2 2006.225.08:03:50.93#ibcon#read 5, iclass 24, count 2 2006.225.08:03:50.93#ibcon#about to read 6, iclass 24, count 2 2006.225.08:03:50.93#ibcon#read 6, iclass 24, count 2 2006.225.08:03:50.93#ibcon#end of sib2, iclass 24, count 2 2006.225.08:03:50.93#ibcon#*after write, iclass 24, count 2 2006.225.08:03:50.93#ibcon#*before return 0, iclass 24, count 2 2006.225.08:03:50.93#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:03:50.93#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:03:50.93#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.08:03:50.93#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:50.93#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:03:51.05#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:03:51.05#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:03:51.05#ibcon#enter wrdev, iclass 24, count 0 2006.225.08:03:51.05#ibcon#first serial, iclass 24, count 0 2006.225.08:03:51.05#ibcon#enter sib2, iclass 24, count 0 2006.225.08:03:51.05#ibcon#flushed, iclass 24, count 0 2006.225.08:03:51.05#ibcon#about to write, iclass 24, count 0 2006.225.08:03:51.05#ibcon#wrote, iclass 24, count 0 2006.225.08:03:51.05#ibcon#about to read 3, iclass 24, count 0 2006.225.08:03:51.07#ibcon#read 3, iclass 24, count 0 2006.225.08:03:51.07#ibcon#about to read 4, iclass 24, count 0 2006.225.08:03:51.07#ibcon#read 4, iclass 24, count 0 2006.225.08:03:51.07#ibcon#about to read 5, iclass 24, count 0 2006.225.08:03:51.07#ibcon#read 5, iclass 24, count 0 2006.225.08:03:51.07#ibcon#about to read 6, iclass 24, count 0 2006.225.08:03:51.07#ibcon#read 6, iclass 24, count 0 2006.225.08:03:51.07#ibcon#end of sib2, iclass 24, count 0 2006.225.08:03:51.07#ibcon#*mode == 0, iclass 24, count 0 2006.225.08:03:51.07#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.08:03:51.07#ibcon#[27=USB\r\n] 2006.225.08:03:51.07#ibcon#*before write, iclass 24, count 0 2006.225.08:03:51.07#ibcon#enter sib2, iclass 24, count 0 2006.225.08:03:51.07#ibcon#flushed, iclass 24, count 0 2006.225.08:03:51.07#ibcon#about to write, iclass 24, count 0 2006.225.08:03:51.07#ibcon#wrote, iclass 24, count 0 2006.225.08:03:51.08#ibcon#about to read 3, iclass 24, count 0 2006.225.08:03:51.10#ibcon#read 3, iclass 24, count 0 2006.225.08:03:51.10#ibcon#about to read 4, iclass 24, count 0 2006.225.08:03:51.10#ibcon#read 4, iclass 24, count 0 2006.225.08:03:51.10#ibcon#about to read 5, iclass 24, count 0 2006.225.08:03:51.10#ibcon#read 5, iclass 24, count 0 2006.225.08:03:51.10#ibcon#about to read 6, iclass 24, count 0 2006.225.08:03:51.10#ibcon#read 6, iclass 24, count 0 2006.225.08:03:51.10#ibcon#end of sib2, iclass 24, count 0 2006.225.08:03:51.10#ibcon#*after write, iclass 24, count 0 2006.225.08:03:51.10#ibcon#*before return 0, iclass 24, count 0 2006.225.08:03:51.10#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:03:51.10#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:03:51.10#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.08:03:51.10#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.08:03:51.11$vc4f8/vblo=6,752.99 2006.225.08:03:51.11#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.08:03:51.11#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.08:03:51.11#ibcon#ireg 17 cls_cnt 0 2006.225.08:03:51.11#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:03:51.11#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:03:51.11#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:03:51.11#ibcon#enter wrdev, iclass 26, count 0 2006.225.08:03:51.11#ibcon#first serial, iclass 26, count 0 2006.225.08:03:51.11#ibcon#enter sib2, iclass 26, count 0 2006.225.08:03:51.11#ibcon#flushed, iclass 26, count 0 2006.225.08:03:51.11#ibcon#about to write, iclass 26, count 0 2006.225.08:03:51.11#ibcon#wrote, iclass 26, count 0 2006.225.08:03:51.11#ibcon#about to read 3, iclass 26, count 0 2006.225.08:03:51.12#ibcon#read 3, iclass 26, count 0 2006.225.08:03:51.12#ibcon#about to read 4, iclass 26, count 0 2006.225.08:03:51.12#ibcon#read 4, iclass 26, count 0 2006.225.08:03:51.12#ibcon#about to read 5, iclass 26, count 0 2006.225.08:03:51.12#ibcon#read 5, iclass 26, count 0 2006.225.08:03:51.12#ibcon#about to read 6, iclass 26, count 0 2006.225.08:03:51.12#ibcon#read 6, iclass 26, count 0 2006.225.08:03:51.13#ibcon#end of sib2, iclass 26, count 0 2006.225.08:03:51.13#ibcon#*mode == 0, iclass 26, count 0 2006.225.08:03:51.13#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.08:03:51.13#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:03:51.13#ibcon#*before write, iclass 26, count 0 2006.225.08:03:51.13#ibcon#enter sib2, iclass 26, count 0 2006.225.08:03:51.13#ibcon#flushed, iclass 26, count 0 2006.225.08:03:51.13#ibcon#about to write, iclass 26, count 0 2006.225.08:03:51.13#ibcon#wrote, iclass 26, count 0 2006.225.08:03:51.13#ibcon#about to read 3, iclass 26, count 0 2006.225.08:03:51.16#ibcon#read 3, iclass 26, count 0 2006.225.08:03:51.16#ibcon#about to read 4, iclass 26, count 0 2006.225.08:03:51.16#ibcon#read 4, iclass 26, count 0 2006.225.08:03:51.16#ibcon#about to read 5, iclass 26, count 0 2006.225.08:03:51.16#ibcon#read 5, iclass 26, count 0 2006.225.08:03:51.16#ibcon#about to read 6, iclass 26, count 0 2006.225.08:03:51.16#ibcon#read 6, iclass 26, count 0 2006.225.08:03:51.16#ibcon#end of sib2, iclass 26, count 0 2006.225.08:03:51.16#ibcon#*after write, iclass 26, count 0 2006.225.08:03:51.16#ibcon#*before return 0, iclass 26, count 0 2006.225.08:03:51.16#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:03:51.16#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:03:51.16#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.08:03:51.16#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.08:03:51.17$vc4f8/vb=6,4 2006.225.08:03:51.17#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.08:03:51.17#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.08:03:51.17#ibcon#ireg 11 cls_cnt 2 2006.225.08:03:51.17#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:03:51.21#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:03:51.21#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:03:51.21#ibcon#enter wrdev, iclass 28, count 2 2006.225.08:03:51.21#ibcon#first serial, iclass 28, count 2 2006.225.08:03:51.21#ibcon#enter sib2, iclass 28, count 2 2006.225.08:03:51.21#ibcon#flushed, iclass 28, count 2 2006.225.08:03:51.21#ibcon#about to write, iclass 28, count 2 2006.225.08:03:51.21#ibcon#wrote, iclass 28, count 2 2006.225.08:03:51.21#ibcon#about to read 3, iclass 28, count 2 2006.225.08:03:51.23#ibcon#read 3, iclass 28, count 2 2006.225.08:03:51.23#ibcon#about to read 4, iclass 28, count 2 2006.225.08:03:51.23#ibcon#read 4, iclass 28, count 2 2006.225.08:03:51.23#ibcon#about to read 5, iclass 28, count 2 2006.225.08:03:51.23#ibcon#read 5, iclass 28, count 2 2006.225.08:03:51.23#ibcon#about to read 6, iclass 28, count 2 2006.225.08:03:51.23#ibcon#read 6, iclass 28, count 2 2006.225.08:03:51.23#ibcon#end of sib2, iclass 28, count 2 2006.225.08:03:51.23#ibcon#*mode == 0, iclass 28, count 2 2006.225.08:03:51.23#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.08:03:51.23#ibcon#[27=AT06-04\r\n] 2006.225.08:03:51.23#ibcon#*before write, iclass 28, count 2 2006.225.08:03:51.23#ibcon#enter sib2, iclass 28, count 2 2006.225.08:03:51.23#ibcon#flushed, iclass 28, count 2 2006.225.08:03:51.23#ibcon#about to write, iclass 28, count 2 2006.225.08:03:51.24#ibcon#wrote, iclass 28, count 2 2006.225.08:03:51.24#ibcon#about to read 3, iclass 28, count 2 2006.225.08:03:51.26#ibcon#read 3, iclass 28, count 2 2006.225.08:03:51.26#ibcon#about to read 4, iclass 28, count 2 2006.225.08:03:51.26#ibcon#read 4, iclass 28, count 2 2006.225.08:03:51.26#ibcon#about to read 5, iclass 28, count 2 2006.225.08:03:51.26#ibcon#read 5, iclass 28, count 2 2006.225.08:03:51.26#ibcon#about to read 6, iclass 28, count 2 2006.225.08:03:51.26#ibcon#read 6, iclass 28, count 2 2006.225.08:03:51.26#ibcon#end of sib2, iclass 28, count 2 2006.225.08:03:51.26#ibcon#*after write, iclass 28, count 2 2006.225.08:03:51.26#ibcon#*before return 0, iclass 28, count 2 2006.225.08:03:51.26#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:03:51.26#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:03:51.26#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.08:03:51.26#ibcon#ireg 7 cls_cnt 0 2006.225.08:03:51.26#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:03:51.38#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:03:51.38#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:03:51.38#ibcon#enter wrdev, iclass 28, count 0 2006.225.08:03:51.38#ibcon#first serial, iclass 28, count 0 2006.225.08:03:51.38#ibcon#enter sib2, iclass 28, count 0 2006.225.08:03:51.38#ibcon#flushed, iclass 28, count 0 2006.225.08:03:51.38#ibcon#about to write, iclass 28, count 0 2006.225.08:03:51.38#ibcon#wrote, iclass 28, count 0 2006.225.08:03:51.38#ibcon#about to read 3, iclass 28, count 0 2006.225.08:03:51.40#ibcon#read 3, iclass 28, count 0 2006.225.08:03:51.40#ibcon#about to read 4, iclass 28, count 0 2006.225.08:03:51.40#ibcon#read 4, iclass 28, count 0 2006.225.08:03:51.40#ibcon#about to read 5, iclass 28, count 0 2006.225.08:03:51.40#ibcon#read 5, iclass 28, count 0 2006.225.08:03:51.40#ibcon#about to read 6, iclass 28, count 0 2006.225.08:03:51.40#ibcon#read 6, iclass 28, count 0 2006.225.08:03:51.40#ibcon#end of sib2, iclass 28, count 0 2006.225.08:03:51.40#ibcon#*mode == 0, iclass 28, count 0 2006.225.08:03:51.40#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.08:03:51.40#ibcon#[27=USB\r\n] 2006.225.08:03:51.40#ibcon#*before write, iclass 28, count 0 2006.225.08:03:51.40#ibcon#enter sib2, iclass 28, count 0 2006.225.08:03:51.40#ibcon#flushed, iclass 28, count 0 2006.225.08:03:51.40#ibcon#about to write, iclass 28, count 0 2006.225.08:03:51.41#ibcon#wrote, iclass 28, count 0 2006.225.08:03:51.41#ibcon#about to read 3, iclass 28, count 0 2006.225.08:03:51.43#ibcon#read 3, iclass 28, count 0 2006.225.08:03:51.43#ibcon#about to read 4, iclass 28, count 0 2006.225.08:03:51.43#ibcon#read 4, iclass 28, count 0 2006.225.08:03:51.43#ibcon#about to read 5, iclass 28, count 0 2006.225.08:03:51.43#ibcon#read 5, iclass 28, count 0 2006.225.08:03:51.43#ibcon#about to read 6, iclass 28, count 0 2006.225.08:03:51.43#ibcon#read 6, iclass 28, count 0 2006.225.08:03:51.43#ibcon#end of sib2, iclass 28, count 0 2006.225.08:03:51.43#ibcon#*after write, iclass 28, count 0 2006.225.08:03:51.43#ibcon#*before return 0, iclass 28, count 0 2006.225.08:03:51.43#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:03:51.43#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:03:51.43#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.08:03:51.43#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.08:03:51.44$vc4f8/vabw=wide 2006.225.08:03:51.44#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.08:03:51.44#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.08:03:51.44#ibcon#ireg 8 cls_cnt 0 2006.225.08:03:51.44#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:03:51.44#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:03:51.44#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:03:51.44#ibcon#enter wrdev, iclass 30, count 0 2006.225.08:03:51.44#ibcon#first serial, iclass 30, count 0 2006.225.08:03:51.44#ibcon#enter sib2, iclass 30, count 0 2006.225.08:03:51.44#ibcon#flushed, iclass 30, count 0 2006.225.08:03:51.44#ibcon#about to write, iclass 30, count 0 2006.225.08:03:51.44#ibcon#wrote, iclass 30, count 0 2006.225.08:03:51.44#ibcon#about to read 3, iclass 30, count 0 2006.225.08:03:51.45#ibcon#read 3, iclass 30, count 0 2006.225.08:03:51.45#ibcon#about to read 4, iclass 30, count 0 2006.225.08:03:51.45#ibcon#read 4, iclass 30, count 0 2006.225.08:03:51.45#ibcon#about to read 5, iclass 30, count 0 2006.225.08:03:51.45#ibcon#read 5, iclass 30, count 0 2006.225.08:03:51.45#ibcon#about to read 6, iclass 30, count 0 2006.225.08:03:51.45#ibcon#read 6, iclass 30, count 0 2006.225.08:03:51.45#ibcon#end of sib2, iclass 30, count 0 2006.225.08:03:51.45#ibcon#*mode == 0, iclass 30, count 0 2006.225.08:03:51.45#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.08:03:51.45#ibcon#[25=BW32\r\n] 2006.225.08:03:51.45#ibcon#*before write, iclass 30, count 0 2006.225.08:03:51.45#ibcon#enter sib2, iclass 30, count 0 2006.225.08:03:51.45#ibcon#flushed, iclass 30, count 0 2006.225.08:03:51.45#ibcon#about to write, iclass 30, count 0 2006.225.08:03:51.46#ibcon#wrote, iclass 30, count 0 2006.225.08:03:51.46#ibcon#about to read 3, iclass 30, count 0 2006.225.08:03:51.48#ibcon#read 3, iclass 30, count 0 2006.225.08:03:51.48#ibcon#about to read 4, iclass 30, count 0 2006.225.08:03:51.48#ibcon#read 4, iclass 30, count 0 2006.225.08:03:51.48#ibcon#about to read 5, iclass 30, count 0 2006.225.08:03:51.48#ibcon#read 5, iclass 30, count 0 2006.225.08:03:51.48#ibcon#about to read 6, iclass 30, count 0 2006.225.08:03:51.48#ibcon#read 6, iclass 30, count 0 2006.225.08:03:51.48#ibcon#end of sib2, iclass 30, count 0 2006.225.08:03:51.48#ibcon#*after write, iclass 30, count 0 2006.225.08:03:51.48#ibcon#*before return 0, iclass 30, count 0 2006.225.08:03:51.48#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:03:51.48#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:03:51.48#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.08:03:51.48#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.08:03:51.49$vc4f8/vbbw=wide 2006.225.08:03:51.49#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.08:03:51.49#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.08:03:51.49#ibcon#ireg 8 cls_cnt 0 2006.225.08:03:51.49#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:03:51.54#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:03:51.54#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:03:51.54#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:03:51.54#ibcon#first serial, iclass 32, count 0 2006.225.08:03:51.54#ibcon#enter sib2, iclass 32, count 0 2006.225.08:03:51.54#ibcon#flushed, iclass 32, count 0 2006.225.08:03:51.54#ibcon#about to write, iclass 32, count 0 2006.225.08:03:51.54#ibcon#wrote, iclass 32, count 0 2006.225.08:03:51.54#ibcon#about to read 3, iclass 32, count 0 2006.225.08:03:51.56#ibcon#read 3, iclass 32, count 0 2006.225.08:03:51.56#ibcon#about to read 4, iclass 32, count 0 2006.225.08:03:51.56#ibcon#read 4, iclass 32, count 0 2006.225.08:03:51.56#ibcon#about to read 5, iclass 32, count 0 2006.225.08:03:51.56#ibcon#read 5, iclass 32, count 0 2006.225.08:03:51.56#ibcon#about to read 6, iclass 32, count 0 2006.225.08:03:51.56#ibcon#read 6, iclass 32, count 0 2006.225.08:03:51.56#ibcon#end of sib2, iclass 32, count 0 2006.225.08:03:51.56#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:03:51.56#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:03:51.56#ibcon#[27=BW32\r\n] 2006.225.08:03:51.56#ibcon#*before write, iclass 32, count 0 2006.225.08:03:51.56#ibcon#enter sib2, iclass 32, count 0 2006.225.08:03:51.56#ibcon#flushed, iclass 32, count 0 2006.225.08:03:51.56#ibcon#about to write, iclass 32, count 0 2006.225.08:03:51.57#ibcon#wrote, iclass 32, count 0 2006.225.08:03:51.57#ibcon#about to read 3, iclass 32, count 0 2006.225.08:03:51.59#ibcon#read 3, iclass 32, count 0 2006.225.08:03:51.59#ibcon#about to read 4, iclass 32, count 0 2006.225.08:03:51.59#ibcon#read 4, iclass 32, count 0 2006.225.08:03:51.59#ibcon#about to read 5, iclass 32, count 0 2006.225.08:03:51.59#ibcon#read 5, iclass 32, count 0 2006.225.08:03:51.59#ibcon#about to read 6, iclass 32, count 0 2006.225.08:03:51.59#ibcon#read 6, iclass 32, count 0 2006.225.08:03:51.59#ibcon#end of sib2, iclass 32, count 0 2006.225.08:03:51.59#ibcon#*after write, iclass 32, count 0 2006.225.08:03:51.59#ibcon#*before return 0, iclass 32, count 0 2006.225.08:03:51.59#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:03:51.59#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:03:51.59#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:03:51.59#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:03:51.60$4f8m12a/ifd4f 2006.225.08:03:51.60$ifd4f/lo= 2006.225.08:03:51.60$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:03:51.60$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:03:51.60$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:03:51.60$ifd4f/patch= 2006.225.08:03:51.60$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:03:51.60$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:03:51.60$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:03:51.60$4f8m12a/"form=m,16.000,1:2 2006.225.08:03:51.60$4f8m12a/"tpicd 2006.225.08:03:51.60$4f8m12a/echo=off 2006.225.08:03:51.60$4f8m12a/xlog=off 2006.225.08:03:51.60:!2006.225.08:04:20 2006.225.08:04:03.14#trakl#Source acquired 2006.225.08:04:03.15#flagr#flagr/antenna,acquired 2006.225.08:04:20.02:preob 2006.225.08:04:21.15/onsource/TRACKING 2006.225.08:04:21.15:!2006.225.08:04:30 2006.225.08:04:30.02:data_valid=on 2006.225.08:04:30.02:midob 2006.225.08:04:31.15/onsource/TRACKING 2006.225.08:04:31.15/wx/28.23,1003.4,69 2006.225.08:04:31.29/cable/+6.4065E-03 2006.225.08:04:32.38/va/01,08,usb,yes,29,30 2006.225.08:04:32.38/va/02,07,usb,yes,29,30 2006.225.08:04:32.38/va/03,06,usb,yes,30,31 2006.225.08:04:32.38/va/04,07,usb,yes,30,32 2006.225.08:04:32.38/va/05,07,usb,yes,32,34 2006.225.08:04:32.38/va/06,06,usb,yes,31,31 2006.225.08:04:32.38/va/07,06,usb,yes,32,32 2006.225.08:04:32.38/va/08,07,usb,yes,30,30 2006.225.08:04:32.61/valo/01,532.99,yes,locked 2006.225.08:04:32.61/valo/02,572.99,yes,locked 2006.225.08:04:32.61/valo/03,672.99,yes,locked 2006.225.08:04:32.61/valo/04,832.99,yes,locked 2006.225.08:04:32.61/valo/05,652.99,yes,locked 2006.225.08:04:32.61/valo/06,772.99,yes,locked 2006.225.08:04:32.61/valo/07,832.99,yes,locked 2006.225.08:04:32.61/valo/08,852.99,yes,locked 2006.225.08:04:33.70/vb/01,04,usb,yes,30,29 2006.225.08:04:33.70/vb/02,04,usb,yes,32,34 2006.225.08:04:33.70/vb/03,04,usb,yes,29,32 2006.225.08:04:33.70/vb/04,04,usb,yes,29,30 2006.225.08:04:33.70/vb/05,04,usb,yes,28,32 2006.225.08:04:33.70/vb/06,04,usb,yes,29,32 2006.225.08:04:33.70/vb/07,04,usb,yes,31,31 2006.225.08:04:33.70/vb/08,04,usb,yes,28,32 2006.225.08:04:33.93/vblo/01,632.99,yes,locked 2006.225.08:04:33.93/vblo/02,640.99,yes,locked 2006.225.08:04:33.93/vblo/03,656.99,yes,locked 2006.225.08:04:33.93/vblo/04,712.99,yes,locked 2006.225.08:04:33.93/vblo/05,744.99,yes,locked 2006.225.08:04:33.93/vblo/06,752.99,yes,locked 2006.225.08:04:33.93/vblo/07,734.99,yes,locked 2006.225.08:04:33.93/vblo/08,744.99,yes,locked 2006.225.08:04:34.08/vabw/8 2006.225.08:04:34.23/vbbw/8 2006.225.08:04:34.32/xfe/off,on,15.2 2006.225.08:04:34.72/ifatt/23,28,28,28 2006.225.08:04:35.07/fmout-gps/S +4.58E-07 2006.225.08:04:35.12:!2006.225.08:05:30 2006.225.08:05:30.01:data_valid=off 2006.225.08:05:30.02:postob 2006.225.08:05:30.10/cable/+6.4047E-03 2006.225.08:05:30.10/wx/28.20,1003.4,70 2006.225.08:05:31.07/fmout-gps/S +4.59E-07 2006.225.08:05:31.07:scan_name=225-0806,k06225,60 2006.225.08:05:31.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.225.08:05:32.15#flagr#flagr/antenna,new-source 2006.225.08:05:32.15:checkk5 2006.225.08:05:32.52/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:05:32.90/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:05:33.28/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:05:33.65/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:05:34.02/chk_obsdata//k5ts1/T2250804??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:05:34.38/chk_obsdata//k5ts2/T2250804??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:05:34.75/chk_obsdata//k5ts3/T2250804??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:05:35.11/chk_obsdata//k5ts4/T2250804??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:05:35.80/k5log//k5ts1_log_newline 2006.225.08:05:36.48/k5log//k5ts2_log_newline 2006.225.08:05:37.17/k5log//k5ts3_log_newline 2006.225.08:05:37.84/k5log//k5ts4_log_newline 2006.225.08:05:37.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:05:37.87:4f8m12a=2 2006.225.08:05:37.87$4f8m12a/echo=on 2006.225.08:05:37.87$4f8m12a/pcalon 2006.225.08:05:37.87$pcalon/"no phase cal control is implemented here 2006.225.08:05:37.87$4f8m12a/"tpicd=stop 2006.225.08:05:37.87$4f8m12a/vc4f8 2006.225.08:05:37.87$vc4f8/valo=1,532.99 2006.225.08:05:37.88#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.08:05:37.88#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.08:05:37.88#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:37.88#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:05:37.88#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:05:37.88#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:05:37.88#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:05:37.88#ibcon#first serial, iclass 5, count 0 2006.225.08:05:37.88#ibcon#enter sib2, iclass 5, count 0 2006.225.08:05:37.88#ibcon#flushed, iclass 5, count 0 2006.225.08:05:37.88#ibcon#about to write, iclass 5, count 0 2006.225.08:05:37.88#ibcon#wrote, iclass 5, count 0 2006.225.08:05:37.88#ibcon#about to read 3, iclass 5, count 0 2006.225.08:05:37.91#ibcon#read 3, iclass 5, count 0 2006.225.08:05:37.91#ibcon#about to read 4, iclass 5, count 0 2006.225.08:05:37.91#ibcon#read 4, iclass 5, count 0 2006.225.08:05:37.91#ibcon#about to read 5, iclass 5, count 0 2006.225.08:05:37.91#ibcon#read 5, iclass 5, count 0 2006.225.08:05:37.91#ibcon#about to read 6, iclass 5, count 0 2006.225.08:05:37.91#ibcon#read 6, iclass 5, count 0 2006.225.08:05:37.91#ibcon#end of sib2, iclass 5, count 0 2006.225.08:05:37.91#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:05:37.91#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:05:37.91#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:05:37.91#ibcon#*before write, iclass 5, count 0 2006.225.08:05:37.91#ibcon#enter sib2, iclass 5, count 0 2006.225.08:05:37.91#ibcon#flushed, iclass 5, count 0 2006.225.08:05:37.91#ibcon#about to write, iclass 5, count 0 2006.225.08:05:37.91#ibcon#wrote, iclass 5, count 0 2006.225.08:05:37.91#ibcon#about to read 3, iclass 5, count 0 2006.225.08:05:37.95#ibcon#read 3, iclass 5, count 0 2006.225.08:05:37.95#ibcon#about to read 4, iclass 5, count 0 2006.225.08:05:37.95#ibcon#read 4, iclass 5, count 0 2006.225.08:05:37.95#ibcon#about to read 5, iclass 5, count 0 2006.225.08:05:37.95#ibcon#read 5, iclass 5, count 0 2006.225.08:05:37.95#ibcon#about to read 6, iclass 5, count 0 2006.225.08:05:37.95#ibcon#read 6, iclass 5, count 0 2006.225.08:05:37.95#ibcon#end of sib2, iclass 5, count 0 2006.225.08:05:37.95#ibcon#*after write, iclass 5, count 0 2006.225.08:05:37.95#ibcon#*before return 0, iclass 5, count 0 2006.225.08:05:37.95#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:05:37.95#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:05:37.95#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:05:37.95#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:05:37.95$vc4f8/va=1,8 2006.225.08:05:37.95#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.08:05:37.95#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.08:05:37.95#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:37.95#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:05:37.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:05:37.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:05:37.95#ibcon#enter wrdev, iclass 7, count 2 2006.225.08:05:37.95#ibcon#first serial, iclass 7, count 2 2006.225.08:05:37.95#ibcon#enter sib2, iclass 7, count 2 2006.225.08:05:37.95#ibcon#flushed, iclass 7, count 2 2006.225.08:05:37.96#ibcon#about to write, iclass 7, count 2 2006.225.08:05:37.96#ibcon#wrote, iclass 7, count 2 2006.225.08:05:37.96#ibcon#about to read 3, iclass 7, count 2 2006.225.08:05:37.98#ibcon#read 3, iclass 7, count 2 2006.225.08:05:37.98#ibcon#about to read 4, iclass 7, count 2 2006.225.08:05:37.98#ibcon#read 4, iclass 7, count 2 2006.225.08:05:37.98#ibcon#about to read 5, iclass 7, count 2 2006.225.08:05:37.98#ibcon#read 5, iclass 7, count 2 2006.225.08:05:37.98#ibcon#about to read 6, iclass 7, count 2 2006.225.08:05:37.98#ibcon#read 6, iclass 7, count 2 2006.225.08:05:37.98#ibcon#end of sib2, iclass 7, count 2 2006.225.08:05:37.98#ibcon#*mode == 0, iclass 7, count 2 2006.225.08:05:37.98#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.08:05:37.98#ibcon#[25=AT01-08\r\n] 2006.225.08:05:37.98#ibcon#*before write, iclass 7, count 2 2006.225.08:05:37.98#ibcon#enter sib2, iclass 7, count 2 2006.225.08:05:37.98#ibcon#flushed, iclass 7, count 2 2006.225.08:05:37.98#ibcon#about to write, iclass 7, count 2 2006.225.08:05:37.98#ibcon#wrote, iclass 7, count 2 2006.225.08:05:37.98#ibcon#about to read 3, iclass 7, count 2 2006.225.08:05:38.01#ibcon#read 3, iclass 7, count 2 2006.225.08:05:38.01#ibcon#about to read 4, iclass 7, count 2 2006.225.08:05:38.01#ibcon#read 4, iclass 7, count 2 2006.225.08:05:38.01#ibcon#about to read 5, iclass 7, count 2 2006.225.08:05:38.01#ibcon#read 5, iclass 7, count 2 2006.225.08:05:38.01#ibcon#about to read 6, iclass 7, count 2 2006.225.08:05:38.01#ibcon#read 6, iclass 7, count 2 2006.225.08:05:38.01#ibcon#end of sib2, iclass 7, count 2 2006.225.08:05:38.01#ibcon#*after write, iclass 7, count 2 2006.225.08:05:38.01#ibcon#*before return 0, iclass 7, count 2 2006.225.08:05:38.01#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:05:38.01#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:05:38.01#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.08:05:38.01#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:38.01#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:05:38.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:05:38.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:05:38.12#ibcon#enter wrdev, iclass 7, count 0 2006.225.08:05:38.12#ibcon#first serial, iclass 7, count 0 2006.225.08:05:38.12#ibcon#enter sib2, iclass 7, count 0 2006.225.08:05:38.12#ibcon#flushed, iclass 7, count 0 2006.225.08:05:38.12#ibcon#about to write, iclass 7, count 0 2006.225.08:05:38.12#ibcon#wrote, iclass 7, count 0 2006.225.08:05:38.12#ibcon#about to read 3, iclass 7, count 0 2006.225.08:05:38.14#ibcon#read 3, iclass 7, count 0 2006.225.08:05:38.14#ibcon#about to read 4, iclass 7, count 0 2006.225.08:05:38.14#ibcon#read 4, iclass 7, count 0 2006.225.08:05:38.14#ibcon#about to read 5, iclass 7, count 0 2006.225.08:05:38.14#ibcon#read 5, iclass 7, count 0 2006.225.08:05:38.14#ibcon#about to read 6, iclass 7, count 0 2006.225.08:05:38.14#ibcon#read 6, iclass 7, count 0 2006.225.08:05:38.14#ibcon#end of sib2, iclass 7, count 0 2006.225.08:05:38.14#ibcon#*mode == 0, iclass 7, count 0 2006.225.08:05:38.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.08:05:38.14#ibcon#[25=USB\r\n] 2006.225.08:05:38.14#ibcon#*before write, iclass 7, count 0 2006.225.08:05:38.14#ibcon#enter sib2, iclass 7, count 0 2006.225.08:05:38.14#ibcon#flushed, iclass 7, count 0 2006.225.08:05:38.14#ibcon#about to write, iclass 7, count 0 2006.225.08:05:38.14#ibcon#wrote, iclass 7, count 0 2006.225.08:05:38.14#ibcon#about to read 3, iclass 7, count 0 2006.225.08:05:38.17#ibcon#read 3, iclass 7, count 0 2006.225.08:05:38.17#ibcon#about to read 4, iclass 7, count 0 2006.225.08:05:38.17#ibcon#read 4, iclass 7, count 0 2006.225.08:05:38.17#ibcon#about to read 5, iclass 7, count 0 2006.225.08:05:38.17#ibcon#read 5, iclass 7, count 0 2006.225.08:05:38.17#ibcon#about to read 6, iclass 7, count 0 2006.225.08:05:38.17#ibcon#read 6, iclass 7, count 0 2006.225.08:05:38.17#ibcon#end of sib2, iclass 7, count 0 2006.225.08:05:38.17#ibcon#*after write, iclass 7, count 0 2006.225.08:05:38.17#ibcon#*before return 0, iclass 7, count 0 2006.225.08:05:38.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:05:38.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:05:38.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.08:05:38.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.08:05:38.17$vc4f8/valo=2,572.99 2006.225.08:05:38.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.08:05:38.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.08:05:38.17#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:38.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:05:38.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:05:38.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:05:38.17#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:05:38.17#ibcon#first serial, iclass 11, count 0 2006.225.08:05:38.17#ibcon#enter sib2, iclass 11, count 0 2006.225.08:05:38.17#ibcon#flushed, iclass 11, count 0 2006.225.08:05:38.18#ibcon#about to write, iclass 11, count 0 2006.225.08:05:38.18#ibcon#wrote, iclass 11, count 0 2006.225.08:05:38.18#ibcon#about to read 3, iclass 11, count 0 2006.225.08:05:38.20#ibcon#read 3, iclass 11, count 0 2006.225.08:05:38.20#ibcon#about to read 4, iclass 11, count 0 2006.225.08:05:38.20#ibcon#read 4, iclass 11, count 0 2006.225.08:05:38.20#ibcon#about to read 5, iclass 11, count 0 2006.225.08:05:38.20#ibcon#read 5, iclass 11, count 0 2006.225.08:05:38.20#ibcon#about to read 6, iclass 11, count 0 2006.225.08:05:38.20#ibcon#read 6, iclass 11, count 0 2006.225.08:05:38.20#ibcon#end of sib2, iclass 11, count 0 2006.225.08:05:38.20#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:05:38.20#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:05:38.20#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:05:38.20#ibcon#*before write, iclass 11, count 0 2006.225.08:05:38.20#ibcon#enter sib2, iclass 11, count 0 2006.225.08:05:38.20#ibcon#flushed, iclass 11, count 0 2006.225.08:05:38.20#ibcon#about to write, iclass 11, count 0 2006.225.08:05:38.20#ibcon#wrote, iclass 11, count 0 2006.225.08:05:38.20#ibcon#about to read 3, iclass 11, count 0 2006.225.08:05:38.23#ibcon#read 3, iclass 11, count 0 2006.225.08:05:38.23#ibcon#about to read 4, iclass 11, count 0 2006.225.08:05:38.23#ibcon#read 4, iclass 11, count 0 2006.225.08:05:38.23#ibcon#about to read 5, iclass 11, count 0 2006.225.08:05:38.23#ibcon#read 5, iclass 11, count 0 2006.225.08:05:38.23#ibcon#about to read 6, iclass 11, count 0 2006.225.08:05:38.23#ibcon#read 6, iclass 11, count 0 2006.225.08:05:38.23#ibcon#end of sib2, iclass 11, count 0 2006.225.08:05:38.23#ibcon#*after write, iclass 11, count 0 2006.225.08:05:38.23#ibcon#*before return 0, iclass 11, count 0 2006.225.08:05:38.23#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:05:38.23#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:05:38.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:05:38.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:05:38.23$vc4f8/va=2,7 2006.225.08:05:38.23#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.08:05:38.23#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.08:05:38.23#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:38.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:05:38.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:05:38.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:05:38.30#ibcon#enter wrdev, iclass 13, count 2 2006.225.08:05:38.30#ibcon#first serial, iclass 13, count 2 2006.225.08:05:38.30#ibcon#enter sib2, iclass 13, count 2 2006.225.08:05:38.30#ibcon#flushed, iclass 13, count 2 2006.225.08:05:38.30#ibcon#about to write, iclass 13, count 2 2006.225.08:05:38.30#ibcon#wrote, iclass 13, count 2 2006.225.08:05:38.30#ibcon#about to read 3, iclass 13, count 2 2006.225.08:05:38.32#ibcon#read 3, iclass 13, count 2 2006.225.08:05:38.32#ibcon#about to read 4, iclass 13, count 2 2006.225.08:05:38.32#ibcon#read 4, iclass 13, count 2 2006.225.08:05:38.32#ibcon#about to read 5, iclass 13, count 2 2006.225.08:05:38.32#ibcon#read 5, iclass 13, count 2 2006.225.08:05:38.32#ibcon#about to read 6, iclass 13, count 2 2006.225.08:05:38.32#ibcon#read 6, iclass 13, count 2 2006.225.08:05:38.32#ibcon#end of sib2, iclass 13, count 2 2006.225.08:05:38.32#ibcon#*mode == 0, iclass 13, count 2 2006.225.08:05:38.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.08:05:38.32#ibcon#[25=AT02-07\r\n] 2006.225.08:05:38.32#ibcon#*before write, iclass 13, count 2 2006.225.08:05:38.32#ibcon#enter sib2, iclass 13, count 2 2006.225.08:05:38.32#ibcon#flushed, iclass 13, count 2 2006.225.08:05:38.32#ibcon#about to write, iclass 13, count 2 2006.225.08:05:38.32#ibcon#wrote, iclass 13, count 2 2006.225.08:05:38.32#ibcon#about to read 3, iclass 13, count 2 2006.225.08:05:38.34#ibcon#read 3, iclass 13, count 2 2006.225.08:05:38.34#ibcon#about to read 4, iclass 13, count 2 2006.225.08:05:38.34#ibcon#read 4, iclass 13, count 2 2006.225.08:05:38.34#ibcon#about to read 5, iclass 13, count 2 2006.225.08:05:38.34#ibcon#read 5, iclass 13, count 2 2006.225.08:05:38.34#ibcon#about to read 6, iclass 13, count 2 2006.225.08:05:38.34#ibcon#read 6, iclass 13, count 2 2006.225.08:05:38.34#ibcon#end of sib2, iclass 13, count 2 2006.225.08:05:38.34#ibcon#*after write, iclass 13, count 2 2006.225.08:05:38.34#ibcon#*before return 0, iclass 13, count 2 2006.225.08:05:38.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:05:38.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:05:38.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.08:05:38.34#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:38.34#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:05:38.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:05:38.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:05:38.46#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:05:38.46#ibcon#first serial, iclass 13, count 0 2006.225.08:05:38.46#ibcon#enter sib2, iclass 13, count 0 2006.225.08:05:38.46#ibcon#flushed, iclass 13, count 0 2006.225.08:05:38.46#ibcon#about to write, iclass 13, count 0 2006.225.08:05:38.46#ibcon#wrote, iclass 13, count 0 2006.225.08:05:38.46#ibcon#about to read 3, iclass 13, count 0 2006.225.08:05:38.48#ibcon#read 3, iclass 13, count 0 2006.225.08:05:38.48#ibcon#about to read 4, iclass 13, count 0 2006.225.08:05:38.48#ibcon#read 4, iclass 13, count 0 2006.225.08:05:38.48#ibcon#about to read 5, iclass 13, count 0 2006.225.08:05:38.48#ibcon#read 5, iclass 13, count 0 2006.225.08:05:38.48#ibcon#about to read 6, iclass 13, count 0 2006.225.08:05:38.48#ibcon#read 6, iclass 13, count 0 2006.225.08:05:38.48#ibcon#end of sib2, iclass 13, count 0 2006.225.08:05:38.48#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:05:38.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:05:38.48#ibcon#[25=USB\r\n] 2006.225.08:05:38.48#ibcon#*before write, iclass 13, count 0 2006.225.08:05:38.48#ibcon#enter sib2, iclass 13, count 0 2006.225.08:05:38.48#ibcon#flushed, iclass 13, count 0 2006.225.08:05:38.48#ibcon#about to write, iclass 13, count 0 2006.225.08:05:38.48#ibcon#wrote, iclass 13, count 0 2006.225.08:05:38.48#ibcon#about to read 3, iclass 13, count 0 2006.225.08:05:38.51#ibcon#read 3, iclass 13, count 0 2006.225.08:05:38.51#ibcon#about to read 4, iclass 13, count 0 2006.225.08:05:38.51#ibcon#read 4, iclass 13, count 0 2006.225.08:05:38.51#ibcon#about to read 5, iclass 13, count 0 2006.225.08:05:38.51#ibcon#read 5, iclass 13, count 0 2006.225.08:05:38.51#ibcon#about to read 6, iclass 13, count 0 2006.225.08:05:38.51#ibcon#read 6, iclass 13, count 0 2006.225.08:05:38.51#ibcon#end of sib2, iclass 13, count 0 2006.225.08:05:38.51#ibcon#*after write, iclass 13, count 0 2006.225.08:05:38.51#ibcon#*before return 0, iclass 13, count 0 2006.225.08:05:38.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:05:38.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:05:38.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:05:38.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:05:38.51$vc4f8/valo=3,672.99 2006.225.08:05:38.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.08:05:38.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.08:05:38.51#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:38.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:05:38.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:05:38.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:05:38.51#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:05:38.51#ibcon#first serial, iclass 15, count 0 2006.225.08:05:38.51#ibcon#enter sib2, iclass 15, count 0 2006.225.08:05:38.52#ibcon#flushed, iclass 15, count 0 2006.225.08:05:38.52#ibcon#about to write, iclass 15, count 0 2006.225.08:05:38.52#ibcon#wrote, iclass 15, count 0 2006.225.08:05:38.52#ibcon#about to read 3, iclass 15, count 0 2006.225.08:05:38.53#ibcon#read 3, iclass 15, count 0 2006.225.08:05:38.53#ibcon#about to read 4, iclass 15, count 0 2006.225.08:05:38.53#ibcon#read 4, iclass 15, count 0 2006.225.08:05:38.53#ibcon#about to read 5, iclass 15, count 0 2006.225.08:05:38.53#ibcon#read 5, iclass 15, count 0 2006.225.08:05:38.53#ibcon#about to read 6, iclass 15, count 0 2006.225.08:05:38.53#ibcon#read 6, iclass 15, count 0 2006.225.08:05:38.53#ibcon#end of sib2, iclass 15, count 0 2006.225.08:05:38.53#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:05:38.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:05:38.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:05:38.53#ibcon#*before write, iclass 15, count 0 2006.225.08:05:38.53#ibcon#enter sib2, iclass 15, count 0 2006.225.08:05:38.53#ibcon#flushed, iclass 15, count 0 2006.225.08:05:38.53#ibcon#about to write, iclass 15, count 0 2006.225.08:05:38.53#ibcon#wrote, iclass 15, count 0 2006.225.08:05:38.53#ibcon#about to read 3, iclass 15, count 0 2006.225.08:05:38.57#ibcon#read 3, iclass 15, count 0 2006.225.08:05:38.57#ibcon#about to read 4, iclass 15, count 0 2006.225.08:05:38.57#ibcon#read 4, iclass 15, count 0 2006.225.08:05:38.57#ibcon#about to read 5, iclass 15, count 0 2006.225.08:05:38.57#ibcon#read 5, iclass 15, count 0 2006.225.08:05:38.57#ibcon#about to read 6, iclass 15, count 0 2006.225.08:05:38.57#ibcon#read 6, iclass 15, count 0 2006.225.08:05:38.57#ibcon#end of sib2, iclass 15, count 0 2006.225.08:05:38.57#ibcon#*after write, iclass 15, count 0 2006.225.08:05:38.57#ibcon#*before return 0, iclass 15, count 0 2006.225.08:05:38.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:05:38.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:05:38.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:05:38.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:05:38.57$vc4f8/va=3,6 2006.225.08:05:38.57#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.08:05:38.57#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.08:05:38.57#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:38.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:05:38.64#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:05:38.64#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:05:38.64#ibcon#enter wrdev, iclass 17, count 2 2006.225.08:05:38.64#ibcon#first serial, iclass 17, count 2 2006.225.08:05:38.64#ibcon#enter sib2, iclass 17, count 2 2006.225.08:05:38.64#ibcon#flushed, iclass 17, count 2 2006.225.08:05:38.64#ibcon#about to write, iclass 17, count 2 2006.225.08:05:38.64#ibcon#wrote, iclass 17, count 2 2006.225.08:05:38.64#ibcon#about to read 3, iclass 17, count 2 2006.225.08:05:38.66#ibcon#read 3, iclass 17, count 2 2006.225.08:05:38.66#ibcon#about to read 4, iclass 17, count 2 2006.225.08:05:38.66#ibcon#read 4, iclass 17, count 2 2006.225.08:05:38.66#ibcon#about to read 5, iclass 17, count 2 2006.225.08:05:38.66#ibcon#read 5, iclass 17, count 2 2006.225.08:05:38.66#ibcon#about to read 6, iclass 17, count 2 2006.225.08:05:38.66#ibcon#read 6, iclass 17, count 2 2006.225.08:05:38.66#ibcon#end of sib2, iclass 17, count 2 2006.225.08:05:38.66#ibcon#*mode == 0, iclass 17, count 2 2006.225.08:05:38.66#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.08:05:38.66#ibcon#[25=AT03-06\r\n] 2006.225.08:05:38.66#ibcon#*before write, iclass 17, count 2 2006.225.08:05:38.66#ibcon#enter sib2, iclass 17, count 2 2006.225.08:05:38.66#ibcon#flushed, iclass 17, count 2 2006.225.08:05:38.66#ibcon#about to write, iclass 17, count 2 2006.225.08:05:38.66#ibcon#wrote, iclass 17, count 2 2006.225.08:05:38.66#ibcon#about to read 3, iclass 17, count 2 2006.225.08:05:38.68#ibcon#read 3, iclass 17, count 2 2006.225.08:05:38.68#ibcon#about to read 4, iclass 17, count 2 2006.225.08:05:38.68#ibcon#read 4, iclass 17, count 2 2006.225.08:05:38.68#ibcon#about to read 5, iclass 17, count 2 2006.225.08:05:38.68#ibcon#read 5, iclass 17, count 2 2006.225.08:05:38.68#ibcon#about to read 6, iclass 17, count 2 2006.225.08:05:38.68#ibcon#read 6, iclass 17, count 2 2006.225.08:05:38.68#ibcon#end of sib2, iclass 17, count 2 2006.225.08:05:38.68#ibcon#*after write, iclass 17, count 2 2006.225.08:05:38.68#ibcon#*before return 0, iclass 17, count 2 2006.225.08:05:38.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:05:38.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:05:38.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.08:05:38.68#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:38.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:05:38.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:05:38.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:05:38.80#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:05:38.80#ibcon#first serial, iclass 17, count 0 2006.225.08:05:38.80#ibcon#enter sib2, iclass 17, count 0 2006.225.08:05:38.80#ibcon#flushed, iclass 17, count 0 2006.225.08:05:38.80#ibcon#about to write, iclass 17, count 0 2006.225.08:05:38.80#ibcon#wrote, iclass 17, count 0 2006.225.08:05:38.80#ibcon#about to read 3, iclass 17, count 0 2006.225.08:05:38.82#ibcon#read 3, iclass 17, count 0 2006.225.08:05:38.82#ibcon#about to read 4, iclass 17, count 0 2006.225.08:05:38.82#ibcon#read 4, iclass 17, count 0 2006.225.08:05:38.82#ibcon#about to read 5, iclass 17, count 0 2006.225.08:05:38.82#ibcon#read 5, iclass 17, count 0 2006.225.08:05:38.82#ibcon#about to read 6, iclass 17, count 0 2006.225.08:05:38.82#ibcon#read 6, iclass 17, count 0 2006.225.08:05:38.82#ibcon#end of sib2, iclass 17, count 0 2006.225.08:05:38.82#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:05:38.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:05:38.82#ibcon#[25=USB\r\n] 2006.225.08:05:38.82#ibcon#*before write, iclass 17, count 0 2006.225.08:05:38.82#ibcon#enter sib2, iclass 17, count 0 2006.225.08:05:38.82#ibcon#flushed, iclass 17, count 0 2006.225.08:05:38.82#ibcon#about to write, iclass 17, count 0 2006.225.08:05:38.82#ibcon#wrote, iclass 17, count 0 2006.225.08:05:38.82#ibcon#about to read 3, iclass 17, count 0 2006.225.08:05:38.85#ibcon#read 3, iclass 17, count 0 2006.225.08:05:38.85#ibcon#about to read 4, iclass 17, count 0 2006.225.08:05:38.85#ibcon#read 4, iclass 17, count 0 2006.225.08:05:38.85#ibcon#about to read 5, iclass 17, count 0 2006.225.08:05:38.85#ibcon#read 5, iclass 17, count 0 2006.225.08:05:38.85#ibcon#about to read 6, iclass 17, count 0 2006.225.08:05:38.85#ibcon#read 6, iclass 17, count 0 2006.225.08:05:38.85#ibcon#end of sib2, iclass 17, count 0 2006.225.08:05:38.85#ibcon#*after write, iclass 17, count 0 2006.225.08:05:38.85#ibcon#*before return 0, iclass 17, count 0 2006.225.08:05:38.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:05:38.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:05:38.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:05:38.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:05:38.85$vc4f8/valo=4,832.99 2006.225.08:05:38.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.08:05:38.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.08:05:38.85#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:38.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:05:38.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:05:38.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:05:38.85#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:05:38.85#ibcon#first serial, iclass 19, count 0 2006.225.08:05:38.85#ibcon#enter sib2, iclass 19, count 0 2006.225.08:05:38.85#ibcon#flushed, iclass 19, count 0 2006.225.08:05:38.86#ibcon#about to write, iclass 19, count 0 2006.225.08:05:38.86#ibcon#wrote, iclass 19, count 0 2006.225.08:05:38.86#ibcon#about to read 3, iclass 19, count 0 2006.225.08:05:38.87#ibcon#read 3, iclass 19, count 0 2006.225.08:05:38.87#ibcon#about to read 4, iclass 19, count 0 2006.225.08:05:38.87#ibcon#read 4, iclass 19, count 0 2006.225.08:05:38.87#ibcon#about to read 5, iclass 19, count 0 2006.225.08:05:38.87#ibcon#read 5, iclass 19, count 0 2006.225.08:05:38.87#ibcon#about to read 6, iclass 19, count 0 2006.225.08:05:38.87#ibcon#read 6, iclass 19, count 0 2006.225.08:05:38.87#ibcon#end of sib2, iclass 19, count 0 2006.225.08:05:38.87#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:05:38.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:05:38.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:05:38.87#ibcon#*before write, iclass 19, count 0 2006.225.08:05:38.87#ibcon#enter sib2, iclass 19, count 0 2006.225.08:05:38.87#ibcon#flushed, iclass 19, count 0 2006.225.08:05:38.87#ibcon#about to write, iclass 19, count 0 2006.225.08:05:38.87#ibcon#wrote, iclass 19, count 0 2006.225.08:05:38.87#ibcon#about to read 3, iclass 19, count 0 2006.225.08:05:38.91#ibcon#read 3, iclass 19, count 0 2006.225.08:05:38.91#ibcon#about to read 4, iclass 19, count 0 2006.225.08:05:38.91#ibcon#read 4, iclass 19, count 0 2006.225.08:05:38.91#ibcon#about to read 5, iclass 19, count 0 2006.225.08:05:38.91#ibcon#read 5, iclass 19, count 0 2006.225.08:05:38.91#ibcon#about to read 6, iclass 19, count 0 2006.225.08:05:38.91#ibcon#read 6, iclass 19, count 0 2006.225.08:05:38.91#ibcon#end of sib2, iclass 19, count 0 2006.225.08:05:38.91#ibcon#*after write, iclass 19, count 0 2006.225.08:05:38.91#ibcon#*before return 0, iclass 19, count 0 2006.225.08:05:38.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:05:38.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:05:38.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:05:38.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:05:38.91$vc4f8/va=4,7 2006.225.08:05:38.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.225.08:05:38.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.225.08:05:38.91#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:38.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:05:38.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:05:38.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:05:38.97#ibcon#enter wrdev, iclass 21, count 2 2006.225.08:05:38.97#ibcon#first serial, iclass 21, count 2 2006.225.08:05:38.97#ibcon#enter sib2, iclass 21, count 2 2006.225.08:05:38.97#ibcon#flushed, iclass 21, count 2 2006.225.08:05:38.97#ibcon#about to write, iclass 21, count 2 2006.225.08:05:38.97#ibcon#wrote, iclass 21, count 2 2006.225.08:05:38.97#ibcon#about to read 3, iclass 21, count 2 2006.225.08:05:38.99#ibcon#read 3, iclass 21, count 2 2006.225.08:05:38.99#ibcon#about to read 4, iclass 21, count 2 2006.225.08:05:38.99#ibcon#read 4, iclass 21, count 2 2006.225.08:05:38.99#ibcon#about to read 5, iclass 21, count 2 2006.225.08:05:38.99#ibcon#read 5, iclass 21, count 2 2006.225.08:05:38.99#ibcon#about to read 6, iclass 21, count 2 2006.225.08:05:38.99#ibcon#read 6, iclass 21, count 2 2006.225.08:05:38.99#ibcon#end of sib2, iclass 21, count 2 2006.225.08:05:38.99#ibcon#*mode == 0, iclass 21, count 2 2006.225.08:05:38.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.225.08:05:38.99#ibcon#[25=AT04-07\r\n] 2006.225.08:05:38.99#ibcon#*before write, iclass 21, count 2 2006.225.08:05:38.99#ibcon#enter sib2, iclass 21, count 2 2006.225.08:05:38.99#ibcon#flushed, iclass 21, count 2 2006.225.08:05:38.99#ibcon#about to write, iclass 21, count 2 2006.225.08:05:38.99#ibcon#wrote, iclass 21, count 2 2006.225.08:05:38.99#ibcon#about to read 3, iclass 21, count 2 2006.225.08:05:39.02#ibcon#read 3, iclass 21, count 2 2006.225.08:05:39.02#ibcon#about to read 4, iclass 21, count 2 2006.225.08:05:39.02#ibcon#read 4, iclass 21, count 2 2006.225.08:05:39.02#ibcon#about to read 5, iclass 21, count 2 2006.225.08:05:39.02#ibcon#read 5, iclass 21, count 2 2006.225.08:05:39.02#ibcon#about to read 6, iclass 21, count 2 2006.225.08:05:39.02#ibcon#read 6, iclass 21, count 2 2006.225.08:05:39.02#ibcon#end of sib2, iclass 21, count 2 2006.225.08:05:39.02#ibcon#*after write, iclass 21, count 2 2006.225.08:05:39.02#ibcon#*before return 0, iclass 21, count 2 2006.225.08:05:39.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:05:39.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:05:39.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.225.08:05:39.02#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:39.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:05:39.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:05:39.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:05:39.15#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:05:39.15#ibcon#first serial, iclass 21, count 0 2006.225.08:05:39.15#ibcon#enter sib2, iclass 21, count 0 2006.225.08:05:39.15#ibcon#flushed, iclass 21, count 0 2006.225.08:05:39.15#ibcon#about to write, iclass 21, count 0 2006.225.08:05:39.15#ibcon#wrote, iclass 21, count 0 2006.225.08:05:39.15#ibcon#about to read 3, iclass 21, count 0 2006.225.08:05:39.16#ibcon#read 3, iclass 21, count 0 2006.225.08:05:39.16#ibcon#about to read 4, iclass 21, count 0 2006.225.08:05:39.16#ibcon#read 4, iclass 21, count 0 2006.225.08:05:39.16#ibcon#about to read 5, iclass 21, count 0 2006.225.08:05:39.16#ibcon#read 5, iclass 21, count 0 2006.225.08:05:39.16#ibcon#about to read 6, iclass 21, count 0 2006.225.08:05:39.16#ibcon#read 6, iclass 21, count 0 2006.225.08:05:39.16#ibcon#end of sib2, iclass 21, count 0 2006.225.08:05:39.16#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:05:39.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:05:39.16#ibcon#[25=USB\r\n] 2006.225.08:05:39.16#ibcon#*before write, iclass 21, count 0 2006.225.08:05:39.16#ibcon#enter sib2, iclass 21, count 0 2006.225.08:05:39.16#ibcon#flushed, iclass 21, count 0 2006.225.08:05:39.16#ibcon#about to write, iclass 21, count 0 2006.225.08:05:39.16#ibcon#wrote, iclass 21, count 0 2006.225.08:05:39.16#ibcon#about to read 3, iclass 21, count 0 2006.225.08:05:39.19#ibcon#read 3, iclass 21, count 0 2006.225.08:05:39.19#ibcon#about to read 4, iclass 21, count 0 2006.225.08:05:39.19#ibcon#read 4, iclass 21, count 0 2006.225.08:05:39.19#ibcon#about to read 5, iclass 21, count 0 2006.225.08:05:39.19#ibcon#read 5, iclass 21, count 0 2006.225.08:05:39.19#ibcon#about to read 6, iclass 21, count 0 2006.225.08:05:39.19#ibcon#read 6, iclass 21, count 0 2006.225.08:05:39.19#ibcon#end of sib2, iclass 21, count 0 2006.225.08:05:39.19#ibcon#*after write, iclass 21, count 0 2006.225.08:05:39.19#ibcon#*before return 0, iclass 21, count 0 2006.225.08:05:39.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:05:39.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:05:39.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:05:39.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:05:39.19$vc4f8/valo=5,652.99 2006.225.08:05:39.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.225.08:05:39.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.225.08:05:39.19#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:39.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:05:39.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:05:39.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:05:39.19#ibcon#enter wrdev, iclass 23, count 0 2006.225.08:05:39.19#ibcon#first serial, iclass 23, count 0 2006.225.08:05:39.19#ibcon#enter sib2, iclass 23, count 0 2006.225.08:05:39.20#ibcon#flushed, iclass 23, count 0 2006.225.08:05:39.20#ibcon#about to write, iclass 23, count 0 2006.225.08:05:39.20#ibcon#wrote, iclass 23, count 0 2006.225.08:05:39.20#ibcon#about to read 3, iclass 23, count 0 2006.225.08:05:39.21#ibcon#read 3, iclass 23, count 0 2006.225.08:05:39.21#ibcon#about to read 4, iclass 23, count 0 2006.225.08:05:39.21#ibcon#read 4, iclass 23, count 0 2006.225.08:05:39.21#ibcon#about to read 5, iclass 23, count 0 2006.225.08:05:39.21#ibcon#read 5, iclass 23, count 0 2006.225.08:05:39.21#ibcon#about to read 6, iclass 23, count 0 2006.225.08:05:39.21#ibcon#read 6, iclass 23, count 0 2006.225.08:05:39.21#ibcon#end of sib2, iclass 23, count 0 2006.225.08:05:39.21#ibcon#*mode == 0, iclass 23, count 0 2006.225.08:05:39.21#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.08:05:39.21#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:05:39.21#ibcon#*before write, iclass 23, count 0 2006.225.08:05:39.21#ibcon#enter sib2, iclass 23, count 0 2006.225.08:05:39.21#ibcon#flushed, iclass 23, count 0 2006.225.08:05:39.21#ibcon#about to write, iclass 23, count 0 2006.225.08:05:39.21#ibcon#wrote, iclass 23, count 0 2006.225.08:05:39.21#ibcon#about to read 3, iclass 23, count 0 2006.225.08:05:39.25#ibcon#read 3, iclass 23, count 0 2006.225.08:05:39.25#ibcon#about to read 4, iclass 23, count 0 2006.225.08:05:39.25#ibcon#read 4, iclass 23, count 0 2006.225.08:05:39.25#ibcon#about to read 5, iclass 23, count 0 2006.225.08:05:39.25#ibcon#read 5, iclass 23, count 0 2006.225.08:05:39.25#ibcon#about to read 6, iclass 23, count 0 2006.225.08:05:39.25#ibcon#read 6, iclass 23, count 0 2006.225.08:05:39.25#ibcon#end of sib2, iclass 23, count 0 2006.225.08:05:39.25#ibcon#*after write, iclass 23, count 0 2006.225.08:05:39.25#ibcon#*before return 0, iclass 23, count 0 2006.225.08:05:39.25#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:05:39.25#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:05:39.25#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.08:05:39.25#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.08:05:39.25$vc4f8/va=5,7 2006.225.08:05:39.25#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.225.08:05:39.25#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.225.08:05:39.25#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:39.25#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:05:39.31#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:05:39.31#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:05:39.31#ibcon#enter wrdev, iclass 25, count 2 2006.225.08:05:39.31#ibcon#first serial, iclass 25, count 2 2006.225.08:05:39.31#ibcon#enter sib2, iclass 25, count 2 2006.225.08:05:39.31#ibcon#flushed, iclass 25, count 2 2006.225.08:05:39.31#ibcon#about to write, iclass 25, count 2 2006.225.08:05:39.31#ibcon#wrote, iclass 25, count 2 2006.225.08:05:39.31#ibcon#about to read 3, iclass 25, count 2 2006.225.08:05:39.33#ibcon#read 3, iclass 25, count 2 2006.225.08:05:39.33#ibcon#about to read 4, iclass 25, count 2 2006.225.08:05:39.33#ibcon#read 4, iclass 25, count 2 2006.225.08:05:39.33#ibcon#about to read 5, iclass 25, count 2 2006.225.08:05:39.33#ibcon#read 5, iclass 25, count 2 2006.225.08:05:39.33#ibcon#about to read 6, iclass 25, count 2 2006.225.08:05:39.33#ibcon#read 6, iclass 25, count 2 2006.225.08:05:39.33#ibcon#end of sib2, iclass 25, count 2 2006.225.08:05:39.33#ibcon#*mode == 0, iclass 25, count 2 2006.225.08:05:39.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.225.08:05:39.33#ibcon#[25=AT05-07\r\n] 2006.225.08:05:39.33#ibcon#*before write, iclass 25, count 2 2006.225.08:05:39.33#ibcon#enter sib2, iclass 25, count 2 2006.225.08:05:39.33#ibcon#flushed, iclass 25, count 2 2006.225.08:05:39.33#ibcon#about to write, iclass 25, count 2 2006.225.08:05:39.33#ibcon#wrote, iclass 25, count 2 2006.225.08:05:39.33#ibcon#about to read 3, iclass 25, count 2 2006.225.08:05:39.36#ibcon#read 3, iclass 25, count 2 2006.225.08:05:39.36#ibcon#about to read 4, iclass 25, count 2 2006.225.08:05:39.36#ibcon#read 4, iclass 25, count 2 2006.225.08:05:39.36#ibcon#about to read 5, iclass 25, count 2 2006.225.08:05:39.36#ibcon#read 5, iclass 25, count 2 2006.225.08:05:39.36#ibcon#about to read 6, iclass 25, count 2 2006.225.08:05:39.36#ibcon#read 6, iclass 25, count 2 2006.225.08:05:39.36#ibcon#end of sib2, iclass 25, count 2 2006.225.08:05:39.36#ibcon#*after write, iclass 25, count 2 2006.225.08:05:39.36#ibcon#*before return 0, iclass 25, count 2 2006.225.08:05:39.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:05:39.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:05:39.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.225.08:05:39.36#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:39.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:05:39.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:05:39.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:05:39.48#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:05:39.48#ibcon#first serial, iclass 25, count 0 2006.225.08:05:39.48#ibcon#enter sib2, iclass 25, count 0 2006.225.08:05:39.48#ibcon#flushed, iclass 25, count 0 2006.225.08:05:39.48#ibcon#about to write, iclass 25, count 0 2006.225.08:05:39.48#ibcon#wrote, iclass 25, count 0 2006.225.08:05:39.48#ibcon#about to read 3, iclass 25, count 0 2006.225.08:05:39.50#ibcon#read 3, iclass 25, count 0 2006.225.08:05:39.50#ibcon#about to read 4, iclass 25, count 0 2006.225.08:05:39.50#ibcon#read 4, iclass 25, count 0 2006.225.08:05:39.50#ibcon#about to read 5, iclass 25, count 0 2006.225.08:05:39.50#ibcon#read 5, iclass 25, count 0 2006.225.08:05:39.50#ibcon#about to read 6, iclass 25, count 0 2006.225.08:05:39.50#ibcon#read 6, iclass 25, count 0 2006.225.08:05:39.50#ibcon#end of sib2, iclass 25, count 0 2006.225.08:05:39.50#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:05:39.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:05:39.50#ibcon#[25=USB\r\n] 2006.225.08:05:39.50#ibcon#*before write, iclass 25, count 0 2006.225.08:05:39.50#ibcon#enter sib2, iclass 25, count 0 2006.225.08:05:39.50#ibcon#flushed, iclass 25, count 0 2006.225.08:05:39.50#ibcon#about to write, iclass 25, count 0 2006.225.08:05:39.50#ibcon#wrote, iclass 25, count 0 2006.225.08:05:39.50#ibcon#about to read 3, iclass 25, count 0 2006.225.08:05:39.53#ibcon#read 3, iclass 25, count 0 2006.225.08:05:39.53#ibcon#about to read 4, iclass 25, count 0 2006.225.08:05:39.53#ibcon#read 4, iclass 25, count 0 2006.225.08:05:39.53#ibcon#about to read 5, iclass 25, count 0 2006.225.08:05:39.53#ibcon#read 5, iclass 25, count 0 2006.225.08:05:39.53#ibcon#about to read 6, iclass 25, count 0 2006.225.08:05:39.53#ibcon#read 6, iclass 25, count 0 2006.225.08:05:39.53#ibcon#end of sib2, iclass 25, count 0 2006.225.08:05:39.53#ibcon#*after write, iclass 25, count 0 2006.225.08:05:39.53#ibcon#*before return 0, iclass 25, count 0 2006.225.08:05:39.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:05:39.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:05:39.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:05:39.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:05:39.53$vc4f8/valo=6,772.99 2006.225.08:05:39.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.08:05:39.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.08:05:39.53#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:39.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:05:39.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:05:39.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:05:39.53#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:05:39.53#ibcon#first serial, iclass 27, count 0 2006.225.08:05:39.53#ibcon#enter sib2, iclass 27, count 0 2006.225.08:05:39.54#ibcon#flushed, iclass 27, count 0 2006.225.08:05:39.54#ibcon#about to write, iclass 27, count 0 2006.225.08:05:39.54#ibcon#wrote, iclass 27, count 0 2006.225.08:05:39.54#ibcon#about to read 3, iclass 27, count 0 2006.225.08:05:39.55#ibcon#read 3, iclass 27, count 0 2006.225.08:05:39.55#ibcon#about to read 4, iclass 27, count 0 2006.225.08:05:39.55#ibcon#read 4, iclass 27, count 0 2006.225.08:05:39.55#ibcon#about to read 5, iclass 27, count 0 2006.225.08:05:39.55#ibcon#read 5, iclass 27, count 0 2006.225.08:05:39.55#ibcon#about to read 6, iclass 27, count 0 2006.225.08:05:39.55#ibcon#read 6, iclass 27, count 0 2006.225.08:05:39.55#ibcon#end of sib2, iclass 27, count 0 2006.225.08:05:39.55#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:05:39.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:05:39.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:05:39.55#ibcon#*before write, iclass 27, count 0 2006.225.08:05:39.55#ibcon#enter sib2, iclass 27, count 0 2006.225.08:05:39.55#ibcon#flushed, iclass 27, count 0 2006.225.08:05:39.55#ibcon#about to write, iclass 27, count 0 2006.225.08:05:39.55#ibcon#wrote, iclass 27, count 0 2006.225.08:05:39.55#ibcon#about to read 3, iclass 27, count 0 2006.225.08:05:39.59#ibcon#read 3, iclass 27, count 0 2006.225.08:05:39.59#ibcon#about to read 4, iclass 27, count 0 2006.225.08:05:39.59#ibcon#read 4, iclass 27, count 0 2006.225.08:05:39.59#ibcon#about to read 5, iclass 27, count 0 2006.225.08:05:39.59#ibcon#read 5, iclass 27, count 0 2006.225.08:05:39.59#ibcon#about to read 6, iclass 27, count 0 2006.225.08:05:39.59#ibcon#read 6, iclass 27, count 0 2006.225.08:05:39.59#ibcon#end of sib2, iclass 27, count 0 2006.225.08:05:39.59#ibcon#*after write, iclass 27, count 0 2006.225.08:05:39.59#ibcon#*before return 0, iclass 27, count 0 2006.225.08:05:39.59#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:05:39.59#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:05:39.59#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:05:39.59#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:05:39.59$vc4f8/va=6,6 2006.225.08:05:39.59#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.225.08:05:39.59#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.225.08:05:39.59#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:39.59#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:05:39.66#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:05:39.66#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:05:39.66#ibcon#enter wrdev, iclass 29, count 2 2006.225.08:05:39.66#ibcon#first serial, iclass 29, count 2 2006.225.08:05:39.66#ibcon#enter sib2, iclass 29, count 2 2006.225.08:05:39.66#ibcon#flushed, iclass 29, count 2 2006.225.08:05:39.66#ibcon#about to write, iclass 29, count 2 2006.225.08:05:39.66#ibcon#wrote, iclass 29, count 2 2006.225.08:05:39.66#ibcon#about to read 3, iclass 29, count 2 2006.225.08:05:39.68#ibcon#read 3, iclass 29, count 2 2006.225.08:05:39.68#ibcon#about to read 4, iclass 29, count 2 2006.225.08:05:39.68#ibcon#read 4, iclass 29, count 2 2006.225.08:05:39.68#ibcon#about to read 5, iclass 29, count 2 2006.225.08:05:39.68#ibcon#read 5, iclass 29, count 2 2006.225.08:05:39.68#ibcon#about to read 6, iclass 29, count 2 2006.225.08:05:39.68#ibcon#read 6, iclass 29, count 2 2006.225.08:05:39.68#ibcon#end of sib2, iclass 29, count 2 2006.225.08:05:39.68#ibcon#*mode == 0, iclass 29, count 2 2006.225.08:05:39.68#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.225.08:05:39.68#ibcon#[25=AT06-06\r\n] 2006.225.08:05:39.68#ibcon#*before write, iclass 29, count 2 2006.225.08:05:39.68#ibcon#enter sib2, iclass 29, count 2 2006.225.08:05:39.68#ibcon#flushed, iclass 29, count 2 2006.225.08:05:39.68#ibcon#about to write, iclass 29, count 2 2006.225.08:05:39.68#ibcon#wrote, iclass 29, count 2 2006.225.08:05:39.68#ibcon#about to read 3, iclass 29, count 2 2006.225.08:05:39.70#ibcon#read 3, iclass 29, count 2 2006.225.08:05:39.70#ibcon#about to read 4, iclass 29, count 2 2006.225.08:05:39.70#ibcon#read 4, iclass 29, count 2 2006.225.08:05:39.70#ibcon#about to read 5, iclass 29, count 2 2006.225.08:05:39.70#ibcon#read 5, iclass 29, count 2 2006.225.08:05:39.70#ibcon#about to read 6, iclass 29, count 2 2006.225.08:05:39.70#ibcon#read 6, iclass 29, count 2 2006.225.08:05:39.70#ibcon#end of sib2, iclass 29, count 2 2006.225.08:05:39.70#ibcon#*after write, iclass 29, count 2 2006.225.08:05:39.70#ibcon#*before return 0, iclass 29, count 2 2006.225.08:05:39.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:05:39.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:05:39.70#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.225.08:05:39.70#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:39.70#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:05:39.82#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:05:39.82#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:05:39.82#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:05:39.82#ibcon#first serial, iclass 29, count 0 2006.225.08:05:39.82#ibcon#enter sib2, iclass 29, count 0 2006.225.08:05:39.82#ibcon#flushed, iclass 29, count 0 2006.225.08:05:39.82#ibcon#about to write, iclass 29, count 0 2006.225.08:05:39.82#ibcon#wrote, iclass 29, count 0 2006.225.08:05:39.82#ibcon#about to read 3, iclass 29, count 0 2006.225.08:05:39.84#ibcon#read 3, iclass 29, count 0 2006.225.08:05:39.84#ibcon#about to read 4, iclass 29, count 0 2006.225.08:05:39.84#ibcon#read 4, iclass 29, count 0 2006.225.08:05:39.84#ibcon#about to read 5, iclass 29, count 0 2006.225.08:05:39.84#ibcon#read 5, iclass 29, count 0 2006.225.08:05:39.84#ibcon#about to read 6, iclass 29, count 0 2006.225.08:05:39.84#ibcon#read 6, iclass 29, count 0 2006.225.08:05:39.84#ibcon#end of sib2, iclass 29, count 0 2006.225.08:05:39.84#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:05:39.84#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:05:39.84#ibcon#[25=USB\r\n] 2006.225.08:05:39.84#ibcon#*before write, iclass 29, count 0 2006.225.08:05:39.84#ibcon#enter sib2, iclass 29, count 0 2006.225.08:05:39.84#ibcon#flushed, iclass 29, count 0 2006.225.08:05:39.84#ibcon#about to write, iclass 29, count 0 2006.225.08:05:39.84#ibcon#wrote, iclass 29, count 0 2006.225.08:05:39.84#ibcon#about to read 3, iclass 29, count 0 2006.225.08:05:39.87#ibcon#read 3, iclass 29, count 0 2006.225.08:05:39.87#ibcon#about to read 4, iclass 29, count 0 2006.225.08:05:39.87#ibcon#read 4, iclass 29, count 0 2006.225.08:05:39.87#ibcon#about to read 5, iclass 29, count 0 2006.225.08:05:39.87#ibcon#read 5, iclass 29, count 0 2006.225.08:05:39.87#ibcon#about to read 6, iclass 29, count 0 2006.225.08:05:39.87#ibcon#read 6, iclass 29, count 0 2006.225.08:05:39.87#ibcon#end of sib2, iclass 29, count 0 2006.225.08:05:39.87#ibcon#*after write, iclass 29, count 0 2006.225.08:05:39.87#ibcon#*before return 0, iclass 29, count 0 2006.225.08:05:39.87#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:05:39.87#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:05:39.87#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:05:39.87#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:05:39.87$vc4f8/valo=7,832.99 2006.225.08:05:39.87#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.08:05:39.87#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.08:05:39.87#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:39.87#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:05:39.87#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:05:39.87#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:05:39.87#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:05:39.87#ibcon#first serial, iclass 31, count 0 2006.225.08:05:39.87#ibcon#enter sib2, iclass 31, count 0 2006.225.08:05:39.87#ibcon#flushed, iclass 31, count 0 2006.225.08:05:39.88#ibcon#about to write, iclass 31, count 0 2006.225.08:05:39.88#ibcon#wrote, iclass 31, count 0 2006.225.08:05:39.88#ibcon#about to read 3, iclass 31, count 0 2006.225.08:05:39.89#ibcon#read 3, iclass 31, count 0 2006.225.08:05:39.89#ibcon#about to read 4, iclass 31, count 0 2006.225.08:05:39.89#ibcon#read 4, iclass 31, count 0 2006.225.08:05:39.89#ibcon#about to read 5, iclass 31, count 0 2006.225.08:05:39.89#ibcon#read 5, iclass 31, count 0 2006.225.08:05:39.89#ibcon#about to read 6, iclass 31, count 0 2006.225.08:05:39.89#ibcon#read 6, iclass 31, count 0 2006.225.08:05:39.89#ibcon#end of sib2, iclass 31, count 0 2006.225.08:05:39.89#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:05:39.89#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:05:39.89#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:05:39.89#ibcon#*before write, iclass 31, count 0 2006.225.08:05:39.89#ibcon#enter sib2, iclass 31, count 0 2006.225.08:05:39.89#ibcon#flushed, iclass 31, count 0 2006.225.08:05:39.89#ibcon#about to write, iclass 31, count 0 2006.225.08:05:39.89#ibcon#wrote, iclass 31, count 0 2006.225.08:05:39.89#ibcon#about to read 3, iclass 31, count 0 2006.225.08:05:39.93#ibcon#read 3, iclass 31, count 0 2006.225.08:05:39.93#ibcon#about to read 4, iclass 31, count 0 2006.225.08:05:39.93#ibcon#read 4, iclass 31, count 0 2006.225.08:05:39.93#ibcon#about to read 5, iclass 31, count 0 2006.225.08:05:39.93#ibcon#read 5, iclass 31, count 0 2006.225.08:05:39.93#ibcon#about to read 6, iclass 31, count 0 2006.225.08:05:39.93#ibcon#read 6, iclass 31, count 0 2006.225.08:05:39.93#ibcon#end of sib2, iclass 31, count 0 2006.225.08:05:39.93#ibcon#*after write, iclass 31, count 0 2006.225.08:05:39.93#ibcon#*before return 0, iclass 31, count 0 2006.225.08:05:39.93#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:05:39.93#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:05:39.93#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:05:39.93#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:05:39.93$vc4f8/va=7,6 2006.225.08:05:39.93#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.225.08:05:39.93#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.225.08:05:39.93#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:39.93#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:05:39.99#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:05:39.99#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:05:39.99#ibcon#enter wrdev, iclass 33, count 2 2006.225.08:05:39.99#ibcon#first serial, iclass 33, count 2 2006.225.08:05:39.99#ibcon#enter sib2, iclass 33, count 2 2006.225.08:05:39.99#ibcon#flushed, iclass 33, count 2 2006.225.08:05:39.99#ibcon#about to write, iclass 33, count 2 2006.225.08:05:39.99#ibcon#wrote, iclass 33, count 2 2006.225.08:05:39.99#ibcon#about to read 3, iclass 33, count 2 2006.225.08:05:40.01#ibcon#read 3, iclass 33, count 2 2006.225.08:05:40.01#ibcon#about to read 4, iclass 33, count 2 2006.225.08:05:40.01#ibcon#read 4, iclass 33, count 2 2006.225.08:05:40.01#ibcon#about to read 5, iclass 33, count 2 2006.225.08:05:40.01#ibcon#read 5, iclass 33, count 2 2006.225.08:05:40.01#ibcon#about to read 6, iclass 33, count 2 2006.225.08:05:40.01#ibcon#read 6, iclass 33, count 2 2006.225.08:05:40.01#ibcon#end of sib2, iclass 33, count 2 2006.225.08:05:40.01#ibcon#*mode == 0, iclass 33, count 2 2006.225.08:05:40.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.225.08:05:40.01#ibcon#[25=AT07-06\r\n] 2006.225.08:05:40.01#ibcon#*before write, iclass 33, count 2 2006.225.08:05:40.01#ibcon#enter sib2, iclass 33, count 2 2006.225.08:05:40.01#ibcon#flushed, iclass 33, count 2 2006.225.08:05:40.01#ibcon#about to write, iclass 33, count 2 2006.225.08:05:40.01#ibcon#wrote, iclass 33, count 2 2006.225.08:05:40.01#ibcon#about to read 3, iclass 33, count 2 2006.225.08:05:40.04#ibcon#read 3, iclass 33, count 2 2006.225.08:05:40.04#ibcon#about to read 4, iclass 33, count 2 2006.225.08:05:40.04#ibcon#read 4, iclass 33, count 2 2006.225.08:05:40.04#ibcon#about to read 5, iclass 33, count 2 2006.225.08:05:40.04#ibcon#read 5, iclass 33, count 2 2006.225.08:05:40.04#ibcon#about to read 6, iclass 33, count 2 2006.225.08:05:40.04#ibcon#read 6, iclass 33, count 2 2006.225.08:05:40.04#ibcon#end of sib2, iclass 33, count 2 2006.225.08:05:40.04#ibcon#*after write, iclass 33, count 2 2006.225.08:05:40.04#ibcon#*before return 0, iclass 33, count 2 2006.225.08:05:40.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:05:40.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:05:40.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.225.08:05:40.04#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:40.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:05:40.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:05:40.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:05:40.16#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:05:40.16#ibcon#first serial, iclass 33, count 0 2006.225.08:05:40.16#ibcon#enter sib2, iclass 33, count 0 2006.225.08:05:40.16#ibcon#flushed, iclass 33, count 0 2006.225.08:05:40.16#ibcon#about to write, iclass 33, count 0 2006.225.08:05:40.16#ibcon#wrote, iclass 33, count 0 2006.225.08:05:40.16#ibcon#about to read 3, iclass 33, count 0 2006.225.08:05:40.18#ibcon#read 3, iclass 33, count 0 2006.225.08:05:40.18#ibcon#about to read 4, iclass 33, count 0 2006.225.08:05:40.18#ibcon#read 4, iclass 33, count 0 2006.225.08:05:40.18#ibcon#about to read 5, iclass 33, count 0 2006.225.08:05:40.18#ibcon#read 5, iclass 33, count 0 2006.225.08:05:40.18#ibcon#about to read 6, iclass 33, count 0 2006.225.08:05:40.18#ibcon#read 6, iclass 33, count 0 2006.225.08:05:40.18#ibcon#end of sib2, iclass 33, count 0 2006.225.08:05:40.18#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:05:40.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:05:40.18#ibcon#[25=USB\r\n] 2006.225.08:05:40.18#ibcon#*before write, iclass 33, count 0 2006.225.08:05:40.18#ibcon#enter sib2, iclass 33, count 0 2006.225.08:05:40.18#ibcon#flushed, iclass 33, count 0 2006.225.08:05:40.18#ibcon#about to write, iclass 33, count 0 2006.225.08:05:40.18#ibcon#wrote, iclass 33, count 0 2006.225.08:05:40.18#ibcon#about to read 3, iclass 33, count 0 2006.225.08:05:40.21#ibcon#read 3, iclass 33, count 0 2006.225.08:05:40.21#ibcon#about to read 4, iclass 33, count 0 2006.225.08:05:40.21#ibcon#read 4, iclass 33, count 0 2006.225.08:05:40.21#ibcon#about to read 5, iclass 33, count 0 2006.225.08:05:40.21#ibcon#read 5, iclass 33, count 0 2006.225.08:05:40.21#ibcon#about to read 6, iclass 33, count 0 2006.225.08:05:40.21#ibcon#read 6, iclass 33, count 0 2006.225.08:05:40.21#ibcon#end of sib2, iclass 33, count 0 2006.225.08:05:40.21#ibcon#*after write, iclass 33, count 0 2006.225.08:05:40.21#ibcon#*before return 0, iclass 33, count 0 2006.225.08:05:40.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:05:40.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:05:40.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:05:40.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:05:40.21$vc4f8/valo=8,852.99 2006.225.08:05:40.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.225.08:05:40.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.225.08:05:40.21#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:40.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:05:40.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:05:40.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:05:40.21#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:05:40.21#ibcon#first serial, iclass 35, count 0 2006.225.08:05:40.21#ibcon#enter sib2, iclass 35, count 0 2006.225.08:05:40.21#ibcon#flushed, iclass 35, count 0 2006.225.08:05:40.21#ibcon#about to write, iclass 35, count 0 2006.225.08:05:40.22#ibcon#wrote, iclass 35, count 0 2006.225.08:05:40.22#ibcon#about to read 3, iclass 35, count 0 2006.225.08:05:40.23#ibcon#read 3, iclass 35, count 0 2006.225.08:05:40.23#ibcon#about to read 4, iclass 35, count 0 2006.225.08:05:40.23#ibcon#read 4, iclass 35, count 0 2006.225.08:05:40.23#ibcon#about to read 5, iclass 35, count 0 2006.225.08:05:40.23#ibcon#read 5, iclass 35, count 0 2006.225.08:05:40.23#ibcon#about to read 6, iclass 35, count 0 2006.225.08:05:40.23#ibcon#read 6, iclass 35, count 0 2006.225.08:05:40.23#ibcon#end of sib2, iclass 35, count 0 2006.225.08:05:40.23#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:05:40.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:05:40.23#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:05:40.23#ibcon#*before write, iclass 35, count 0 2006.225.08:05:40.23#ibcon#enter sib2, iclass 35, count 0 2006.225.08:05:40.23#ibcon#flushed, iclass 35, count 0 2006.225.08:05:40.23#ibcon#about to write, iclass 35, count 0 2006.225.08:05:40.23#ibcon#wrote, iclass 35, count 0 2006.225.08:05:40.23#ibcon#about to read 3, iclass 35, count 0 2006.225.08:05:40.27#ibcon#read 3, iclass 35, count 0 2006.225.08:05:40.27#ibcon#about to read 4, iclass 35, count 0 2006.225.08:05:40.27#ibcon#read 4, iclass 35, count 0 2006.225.08:05:40.27#ibcon#about to read 5, iclass 35, count 0 2006.225.08:05:40.27#ibcon#read 5, iclass 35, count 0 2006.225.08:05:40.27#ibcon#about to read 6, iclass 35, count 0 2006.225.08:05:40.27#ibcon#read 6, iclass 35, count 0 2006.225.08:05:40.27#ibcon#end of sib2, iclass 35, count 0 2006.225.08:05:40.27#ibcon#*after write, iclass 35, count 0 2006.225.08:05:40.27#ibcon#*before return 0, iclass 35, count 0 2006.225.08:05:40.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:05:40.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:05:40.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:05:40.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:05:40.27$vc4f8/va=8,7 2006.225.08:05:40.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.225.08:05:40.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.225.08:05:40.27#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:40.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:05:40.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:05:40.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:05:40.33#ibcon#enter wrdev, iclass 37, count 2 2006.225.08:05:40.33#ibcon#first serial, iclass 37, count 2 2006.225.08:05:40.33#ibcon#enter sib2, iclass 37, count 2 2006.225.08:05:40.33#ibcon#flushed, iclass 37, count 2 2006.225.08:05:40.33#ibcon#about to write, iclass 37, count 2 2006.225.08:05:40.33#ibcon#wrote, iclass 37, count 2 2006.225.08:05:40.33#ibcon#about to read 3, iclass 37, count 2 2006.225.08:05:40.36#ibcon#read 3, iclass 37, count 2 2006.225.08:05:40.36#ibcon#about to read 4, iclass 37, count 2 2006.225.08:05:40.36#ibcon#read 4, iclass 37, count 2 2006.225.08:05:40.36#ibcon#about to read 5, iclass 37, count 2 2006.225.08:05:40.36#ibcon#read 5, iclass 37, count 2 2006.225.08:05:40.36#ibcon#about to read 6, iclass 37, count 2 2006.225.08:05:40.36#ibcon#read 6, iclass 37, count 2 2006.225.08:05:40.36#ibcon#end of sib2, iclass 37, count 2 2006.225.08:05:40.36#ibcon#*mode == 0, iclass 37, count 2 2006.225.08:05:40.36#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.225.08:05:40.36#ibcon#[25=AT08-07\r\n] 2006.225.08:05:40.36#ibcon#*before write, iclass 37, count 2 2006.225.08:05:40.36#ibcon#enter sib2, iclass 37, count 2 2006.225.08:05:40.36#ibcon#flushed, iclass 37, count 2 2006.225.08:05:40.36#ibcon#about to write, iclass 37, count 2 2006.225.08:05:40.36#ibcon#wrote, iclass 37, count 2 2006.225.08:05:40.36#ibcon#about to read 3, iclass 37, count 2 2006.225.08:05:40.38#ibcon#read 3, iclass 37, count 2 2006.225.08:05:40.38#ibcon#about to read 4, iclass 37, count 2 2006.225.08:05:40.38#ibcon#read 4, iclass 37, count 2 2006.225.08:05:40.38#ibcon#about to read 5, iclass 37, count 2 2006.225.08:05:40.38#ibcon#read 5, iclass 37, count 2 2006.225.08:05:40.38#ibcon#about to read 6, iclass 37, count 2 2006.225.08:05:40.38#ibcon#read 6, iclass 37, count 2 2006.225.08:05:40.38#ibcon#end of sib2, iclass 37, count 2 2006.225.08:05:40.38#ibcon#*after write, iclass 37, count 2 2006.225.08:05:40.38#ibcon#*before return 0, iclass 37, count 2 2006.225.08:05:40.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:05:40.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:05:40.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.225.08:05:40.38#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:40.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:05:40.50#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:05:40.50#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:05:40.50#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:05:40.50#ibcon#first serial, iclass 37, count 0 2006.225.08:05:40.50#ibcon#enter sib2, iclass 37, count 0 2006.225.08:05:40.50#ibcon#flushed, iclass 37, count 0 2006.225.08:05:40.50#ibcon#about to write, iclass 37, count 0 2006.225.08:05:40.50#ibcon#wrote, iclass 37, count 0 2006.225.08:05:40.50#ibcon#about to read 3, iclass 37, count 0 2006.225.08:05:40.52#ibcon#read 3, iclass 37, count 0 2006.225.08:05:40.52#ibcon#about to read 4, iclass 37, count 0 2006.225.08:05:40.52#ibcon#read 4, iclass 37, count 0 2006.225.08:05:40.52#ibcon#about to read 5, iclass 37, count 0 2006.225.08:05:40.52#ibcon#read 5, iclass 37, count 0 2006.225.08:05:40.52#ibcon#about to read 6, iclass 37, count 0 2006.225.08:05:40.52#ibcon#read 6, iclass 37, count 0 2006.225.08:05:40.52#ibcon#end of sib2, iclass 37, count 0 2006.225.08:05:40.52#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:05:40.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:05:40.52#ibcon#[25=USB\r\n] 2006.225.08:05:40.52#ibcon#*before write, iclass 37, count 0 2006.225.08:05:40.52#ibcon#enter sib2, iclass 37, count 0 2006.225.08:05:40.52#ibcon#flushed, iclass 37, count 0 2006.225.08:05:40.52#ibcon#about to write, iclass 37, count 0 2006.225.08:05:40.52#ibcon#wrote, iclass 37, count 0 2006.225.08:05:40.52#ibcon#about to read 3, iclass 37, count 0 2006.225.08:05:40.55#ibcon#read 3, iclass 37, count 0 2006.225.08:05:40.55#ibcon#about to read 4, iclass 37, count 0 2006.225.08:05:40.55#ibcon#read 4, iclass 37, count 0 2006.225.08:05:40.55#ibcon#about to read 5, iclass 37, count 0 2006.225.08:05:40.55#ibcon#read 5, iclass 37, count 0 2006.225.08:05:40.55#ibcon#about to read 6, iclass 37, count 0 2006.225.08:05:40.55#ibcon#read 6, iclass 37, count 0 2006.225.08:05:40.55#ibcon#end of sib2, iclass 37, count 0 2006.225.08:05:40.55#ibcon#*after write, iclass 37, count 0 2006.225.08:05:40.55#ibcon#*before return 0, iclass 37, count 0 2006.225.08:05:40.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:05:40.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:05:40.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:05:40.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:05:40.55$vc4f8/vblo=1,632.99 2006.225.08:05:40.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.08:05:40.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.08:05:40.55#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:40.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:05:40.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:05:40.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:05:40.55#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:05:40.55#ibcon#first serial, iclass 39, count 0 2006.225.08:05:40.55#ibcon#enter sib2, iclass 39, count 0 2006.225.08:05:40.56#ibcon#flushed, iclass 39, count 0 2006.225.08:05:40.56#ibcon#about to write, iclass 39, count 0 2006.225.08:05:40.56#ibcon#wrote, iclass 39, count 0 2006.225.08:05:40.56#ibcon#about to read 3, iclass 39, count 0 2006.225.08:05:40.57#ibcon#read 3, iclass 39, count 0 2006.225.08:05:40.57#ibcon#about to read 4, iclass 39, count 0 2006.225.08:05:40.57#ibcon#read 4, iclass 39, count 0 2006.225.08:05:40.57#ibcon#about to read 5, iclass 39, count 0 2006.225.08:05:40.57#ibcon#read 5, iclass 39, count 0 2006.225.08:05:40.57#ibcon#about to read 6, iclass 39, count 0 2006.225.08:05:40.57#ibcon#read 6, iclass 39, count 0 2006.225.08:05:40.57#ibcon#end of sib2, iclass 39, count 0 2006.225.08:05:40.57#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:05:40.57#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:05:40.57#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:05:40.57#ibcon#*before write, iclass 39, count 0 2006.225.08:05:40.57#ibcon#enter sib2, iclass 39, count 0 2006.225.08:05:40.57#ibcon#flushed, iclass 39, count 0 2006.225.08:05:40.57#ibcon#about to write, iclass 39, count 0 2006.225.08:05:40.57#ibcon#wrote, iclass 39, count 0 2006.225.08:05:40.57#ibcon#about to read 3, iclass 39, count 0 2006.225.08:05:40.61#ibcon#read 3, iclass 39, count 0 2006.225.08:05:40.61#ibcon#about to read 4, iclass 39, count 0 2006.225.08:05:40.61#ibcon#read 4, iclass 39, count 0 2006.225.08:05:40.61#ibcon#about to read 5, iclass 39, count 0 2006.225.08:05:40.61#ibcon#read 5, iclass 39, count 0 2006.225.08:05:40.61#ibcon#about to read 6, iclass 39, count 0 2006.225.08:05:40.61#ibcon#read 6, iclass 39, count 0 2006.225.08:05:40.61#ibcon#end of sib2, iclass 39, count 0 2006.225.08:05:40.61#ibcon#*after write, iclass 39, count 0 2006.225.08:05:40.61#ibcon#*before return 0, iclass 39, count 0 2006.225.08:05:40.61#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:05:40.61#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:05:40.61#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:05:40.61#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:05:40.61$vc4f8/vb=1,4 2006.225.08:05:40.61#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.08:05:40.61#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.08:05:40.61#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:40.61#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:05:40.61#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:05:40.61#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:05:40.61#ibcon#enter wrdev, iclass 3, count 2 2006.225.08:05:40.61#ibcon#first serial, iclass 3, count 2 2006.225.08:05:40.62#ibcon#enter sib2, iclass 3, count 2 2006.225.08:05:40.62#ibcon#flushed, iclass 3, count 2 2006.225.08:05:40.62#ibcon#about to write, iclass 3, count 2 2006.225.08:05:40.62#ibcon#wrote, iclass 3, count 2 2006.225.08:05:40.62#ibcon#about to read 3, iclass 3, count 2 2006.225.08:05:40.63#ibcon#read 3, iclass 3, count 2 2006.225.08:05:40.63#ibcon#about to read 4, iclass 3, count 2 2006.225.08:05:40.63#ibcon#read 4, iclass 3, count 2 2006.225.08:05:40.63#ibcon#about to read 5, iclass 3, count 2 2006.225.08:05:40.63#ibcon#read 5, iclass 3, count 2 2006.225.08:05:40.63#ibcon#about to read 6, iclass 3, count 2 2006.225.08:05:40.63#ibcon#read 6, iclass 3, count 2 2006.225.08:05:40.63#ibcon#end of sib2, iclass 3, count 2 2006.225.08:05:40.63#ibcon#*mode == 0, iclass 3, count 2 2006.225.08:05:40.63#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.08:05:40.63#ibcon#[27=AT01-04\r\n] 2006.225.08:05:40.63#ibcon#*before write, iclass 3, count 2 2006.225.08:05:40.63#ibcon#enter sib2, iclass 3, count 2 2006.225.08:05:40.63#ibcon#flushed, iclass 3, count 2 2006.225.08:05:40.63#ibcon#about to write, iclass 3, count 2 2006.225.08:05:40.63#ibcon#wrote, iclass 3, count 2 2006.225.08:05:40.63#ibcon#about to read 3, iclass 3, count 2 2006.225.08:05:40.66#ibcon#read 3, iclass 3, count 2 2006.225.08:05:40.66#ibcon#about to read 4, iclass 3, count 2 2006.225.08:05:40.66#ibcon#read 4, iclass 3, count 2 2006.225.08:05:40.66#ibcon#about to read 5, iclass 3, count 2 2006.225.08:05:40.66#ibcon#read 5, iclass 3, count 2 2006.225.08:05:40.66#ibcon#about to read 6, iclass 3, count 2 2006.225.08:05:40.66#ibcon#read 6, iclass 3, count 2 2006.225.08:05:40.66#ibcon#end of sib2, iclass 3, count 2 2006.225.08:05:40.66#ibcon#*after write, iclass 3, count 2 2006.225.08:05:40.66#ibcon#*before return 0, iclass 3, count 2 2006.225.08:05:40.66#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:05:40.66#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:05:40.66#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.08:05:40.66#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:40.66#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:05:40.78#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:05:40.78#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:05:40.78#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:05:40.78#ibcon#first serial, iclass 3, count 0 2006.225.08:05:40.78#ibcon#enter sib2, iclass 3, count 0 2006.225.08:05:40.78#ibcon#flushed, iclass 3, count 0 2006.225.08:05:40.78#ibcon#about to write, iclass 3, count 0 2006.225.08:05:40.78#ibcon#wrote, iclass 3, count 0 2006.225.08:05:40.78#ibcon#about to read 3, iclass 3, count 0 2006.225.08:05:40.80#ibcon#read 3, iclass 3, count 0 2006.225.08:05:40.80#ibcon#about to read 4, iclass 3, count 0 2006.225.08:05:40.80#ibcon#read 4, iclass 3, count 0 2006.225.08:05:40.80#ibcon#about to read 5, iclass 3, count 0 2006.225.08:05:40.80#ibcon#read 5, iclass 3, count 0 2006.225.08:05:40.80#ibcon#about to read 6, iclass 3, count 0 2006.225.08:05:40.80#ibcon#read 6, iclass 3, count 0 2006.225.08:05:40.80#ibcon#end of sib2, iclass 3, count 0 2006.225.08:05:40.80#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:05:40.80#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:05:40.80#ibcon#[27=USB\r\n] 2006.225.08:05:40.80#ibcon#*before write, iclass 3, count 0 2006.225.08:05:40.80#ibcon#enter sib2, iclass 3, count 0 2006.225.08:05:40.80#ibcon#flushed, iclass 3, count 0 2006.225.08:05:40.80#ibcon#about to write, iclass 3, count 0 2006.225.08:05:40.80#ibcon#wrote, iclass 3, count 0 2006.225.08:05:40.80#ibcon#about to read 3, iclass 3, count 0 2006.225.08:05:40.83#ibcon#read 3, iclass 3, count 0 2006.225.08:05:40.83#ibcon#about to read 4, iclass 3, count 0 2006.225.08:05:40.83#ibcon#read 4, iclass 3, count 0 2006.225.08:05:40.83#ibcon#about to read 5, iclass 3, count 0 2006.225.08:05:40.83#ibcon#read 5, iclass 3, count 0 2006.225.08:05:40.83#ibcon#about to read 6, iclass 3, count 0 2006.225.08:05:40.83#ibcon#read 6, iclass 3, count 0 2006.225.08:05:40.83#ibcon#end of sib2, iclass 3, count 0 2006.225.08:05:40.83#ibcon#*after write, iclass 3, count 0 2006.225.08:05:40.83#ibcon#*before return 0, iclass 3, count 0 2006.225.08:05:40.83#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:05:40.83#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:05:40.83#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:05:40.83#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:05:40.83$vc4f8/vblo=2,640.99 2006.225.08:05:40.83#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.08:05:40.83#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.08:05:40.83#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:40.83#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:05:40.83#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:05:40.83#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:05:40.83#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:05:40.83#ibcon#first serial, iclass 5, count 0 2006.225.08:05:40.83#ibcon#enter sib2, iclass 5, count 0 2006.225.08:05:40.84#ibcon#flushed, iclass 5, count 0 2006.225.08:05:40.84#ibcon#about to write, iclass 5, count 0 2006.225.08:05:40.84#ibcon#wrote, iclass 5, count 0 2006.225.08:05:40.84#ibcon#about to read 3, iclass 5, count 0 2006.225.08:05:40.85#ibcon#read 3, iclass 5, count 0 2006.225.08:05:40.85#ibcon#about to read 4, iclass 5, count 0 2006.225.08:05:40.85#ibcon#read 4, iclass 5, count 0 2006.225.08:05:40.85#ibcon#about to read 5, iclass 5, count 0 2006.225.08:05:40.85#ibcon#read 5, iclass 5, count 0 2006.225.08:05:40.85#ibcon#about to read 6, iclass 5, count 0 2006.225.08:05:40.85#ibcon#read 6, iclass 5, count 0 2006.225.08:05:40.85#ibcon#end of sib2, iclass 5, count 0 2006.225.08:05:40.85#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:05:40.85#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:05:40.85#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:05:40.85#ibcon#*before write, iclass 5, count 0 2006.225.08:05:40.85#ibcon#enter sib2, iclass 5, count 0 2006.225.08:05:40.85#ibcon#flushed, iclass 5, count 0 2006.225.08:05:40.85#ibcon#about to write, iclass 5, count 0 2006.225.08:05:40.85#ibcon#wrote, iclass 5, count 0 2006.225.08:05:40.85#ibcon#about to read 3, iclass 5, count 0 2006.225.08:05:40.89#ibcon#read 3, iclass 5, count 0 2006.225.08:05:40.89#ibcon#about to read 4, iclass 5, count 0 2006.225.08:05:40.89#ibcon#read 4, iclass 5, count 0 2006.225.08:05:40.89#ibcon#about to read 5, iclass 5, count 0 2006.225.08:05:40.89#ibcon#read 5, iclass 5, count 0 2006.225.08:05:40.89#ibcon#about to read 6, iclass 5, count 0 2006.225.08:05:40.89#ibcon#read 6, iclass 5, count 0 2006.225.08:05:40.89#ibcon#end of sib2, iclass 5, count 0 2006.225.08:05:40.89#ibcon#*after write, iclass 5, count 0 2006.225.08:05:40.89#ibcon#*before return 0, iclass 5, count 0 2006.225.08:05:40.89#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:05:40.89#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:05:40.89#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:05:40.89#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:05:40.89$vc4f8/vb=2,4 2006.225.08:05:40.89#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.08:05:40.89#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.08:05:40.89#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:40.89#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:05:40.95#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:05:40.95#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:05:40.95#ibcon#enter wrdev, iclass 7, count 2 2006.225.08:05:40.95#ibcon#first serial, iclass 7, count 2 2006.225.08:05:40.95#ibcon#enter sib2, iclass 7, count 2 2006.225.08:05:40.95#ibcon#flushed, iclass 7, count 2 2006.225.08:05:40.95#ibcon#about to write, iclass 7, count 2 2006.225.08:05:40.95#ibcon#wrote, iclass 7, count 2 2006.225.08:05:40.95#ibcon#about to read 3, iclass 7, count 2 2006.225.08:05:40.97#ibcon#read 3, iclass 7, count 2 2006.225.08:05:40.97#ibcon#about to read 4, iclass 7, count 2 2006.225.08:05:40.97#ibcon#read 4, iclass 7, count 2 2006.225.08:05:40.97#ibcon#about to read 5, iclass 7, count 2 2006.225.08:05:40.97#ibcon#read 5, iclass 7, count 2 2006.225.08:05:40.97#ibcon#about to read 6, iclass 7, count 2 2006.225.08:05:40.97#ibcon#read 6, iclass 7, count 2 2006.225.08:05:40.97#ibcon#end of sib2, iclass 7, count 2 2006.225.08:05:40.97#ibcon#*mode == 0, iclass 7, count 2 2006.225.08:05:40.97#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.08:05:40.97#ibcon#[27=AT02-04\r\n] 2006.225.08:05:40.97#ibcon#*before write, iclass 7, count 2 2006.225.08:05:40.97#ibcon#enter sib2, iclass 7, count 2 2006.225.08:05:40.97#ibcon#flushed, iclass 7, count 2 2006.225.08:05:40.97#ibcon#about to write, iclass 7, count 2 2006.225.08:05:40.97#ibcon#wrote, iclass 7, count 2 2006.225.08:05:40.97#ibcon#about to read 3, iclass 7, count 2 2006.225.08:05:41.00#ibcon#read 3, iclass 7, count 2 2006.225.08:05:41.00#ibcon#about to read 4, iclass 7, count 2 2006.225.08:05:41.00#ibcon#read 4, iclass 7, count 2 2006.225.08:05:41.00#ibcon#about to read 5, iclass 7, count 2 2006.225.08:05:41.00#ibcon#read 5, iclass 7, count 2 2006.225.08:05:41.00#ibcon#about to read 6, iclass 7, count 2 2006.225.08:05:41.00#ibcon#read 6, iclass 7, count 2 2006.225.08:05:41.00#ibcon#end of sib2, iclass 7, count 2 2006.225.08:05:41.00#ibcon#*after write, iclass 7, count 2 2006.225.08:05:41.00#ibcon#*before return 0, iclass 7, count 2 2006.225.08:05:41.00#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:05:41.00#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:05:41.00#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.08:05:41.00#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:41.00#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:05:41.12#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:05:41.12#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:05:41.12#ibcon#enter wrdev, iclass 7, count 0 2006.225.08:05:41.12#ibcon#first serial, iclass 7, count 0 2006.225.08:05:41.12#ibcon#enter sib2, iclass 7, count 0 2006.225.08:05:41.12#ibcon#flushed, iclass 7, count 0 2006.225.08:05:41.12#ibcon#about to write, iclass 7, count 0 2006.225.08:05:41.12#ibcon#wrote, iclass 7, count 0 2006.225.08:05:41.12#ibcon#about to read 3, iclass 7, count 0 2006.225.08:05:41.14#ibcon#read 3, iclass 7, count 0 2006.225.08:05:41.14#ibcon#about to read 4, iclass 7, count 0 2006.225.08:05:41.14#ibcon#read 4, iclass 7, count 0 2006.225.08:05:41.14#ibcon#about to read 5, iclass 7, count 0 2006.225.08:05:41.14#ibcon#read 5, iclass 7, count 0 2006.225.08:05:41.14#ibcon#about to read 6, iclass 7, count 0 2006.225.08:05:41.14#ibcon#read 6, iclass 7, count 0 2006.225.08:05:41.14#ibcon#end of sib2, iclass 7, count 0 2006.225.08:05:41.14#ibcon#*mode == 0, iclass 7, count 0 2006.225.08:05:41.14#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.08:05:41.14#ibcon#[27=USB\r\n] 2006.225.08:05:41.14#ibcon#*before write, iclass 7, count 0 2006.225.08:05:41.14#ibcon#enter sib2, iclass 7, count 0 2006.225.08:05:41.14#ibcon#flushed, iclass 7, count 0 2006.225.08:05:41.14#ibcon#about to write, iclass 7, count 0 2006.225.08:05:41.14#ibcon#wrote, iclass 7, count 0 2006.225.08:05:41.14#ibcon#about to read 3, iclass 7, count 0 2006.225.08:05:41.17#ibcon#read 3, iclass 7, count 0 2006.225.08:05:41.17#ibcon#about to read 4, iclass 7, count 0 2006.225.08:05:41.17#ibcon#read 4, iclass 7, count 0 2006.225.08:05:41.17#ibcon#about to read 5, iclass 7, count 0 2006.225.08:05:41.17#ibcon#read 5, iclass 7, count 0 2006.225.08:05:41.17#ibcon#about to read 6, iclass 7, count 0 2006.225.08:05:41.17#ibcon#read 6, iclass 7, count 0 2006.225.08:05:41.17#ibcon#end of sib2, iclass 7, count 0 2006.225.08:05:41.17#ibcon#*after write, iclass 7, count 0 2006.225.08:05:41.17#ibcon#*before return 0, iclass 7, count 0 2006.225.08:05:41.17#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:05:41.17#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:05:41.17#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.08:05:41.17#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.08:05:41.17$vc4f8/vblo=3,656.99 2006.225.08:05:41.17#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.08:05:41.17#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.08:05:41.17#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:41.17#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:05:41.17#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:05:41.17#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:05:41.17#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:05:41.17#ibcon#first serial, iclass 11, count 0 2006.225.08:05:41.17#ibcon#enter sib2, iclass 11, count 0 2006.225.08:05:41.17#ibcon#flushed, iclass 11, count 0 2006.225.08:05:41.17#ibcon#about to write, iclass 11, count 0 2006.225.08:05:41.18#ibcon#wrote, iclass 11, count 0 2006.225.08:05:41.18#ibcon#about to read 3, iclass 11, count 0 2006.225.08:05:41.19#ibcon#read 3, iclass 11, count 0 2006.225.08:05:41.19#ibcon#about to read 4, iclass 11, count 0 2006.225.08:05:41.19#ibcon#read 4, iclass 11, count 0 2006.225.08:05:41.19#ibcon#about to read 5, iclass 11, count 0 2006.225.08:05:41.19#ibcon#read 5, iclass 11, count 0 2006.225.08:05:41.19#ibcon#about to read 6, iclass 11, count 0 2006.225.08:05:41.19#ibcon#read 6, iclass 11, count 0 2006.225.08:05:41.19#ibcon#end of sib2, iclass 11, count 0 2006.225.08:05:41.19#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:05:41.19#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:05:41.19#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:05:41.19#ibcon#*before write, iclass 11, count 0 2006.225.08:05:41.19#ibcon#enter sib2, iclass 11, count 0 2006.225.08:05:41.19#ibcon#flushed, iclass 11, count 0 2006.225.08:05:41.19#ibcon#about to write, iclass 11, count 0 2006.225.08:05:41.19#ibcon#wrote, iclass 11, count 0 2006.225.08:05:41.19#ibcon#about to read 3, iclass 11, count 0 2006.225.08:05:41.23#ibcon#read 3, iclass 11, count 0 2006.225.08:05:41.23#ibcon#about to read 4, iclass 11, count 0 2006.225.08:05:41.23#ibcon#read 4, iclass 11, count 0 2006.225.08:05:41.23#ibcon#about to read 5, iclass 11, count 0 2006.225.08:05:41.23#ibcon#read 5, iclass 11, count 0 2006.225.08:05:41.23#ibcon#about to read 6, iclass 11, count 0 2006.225.08:05:41.23#ibcon#read 6, iclass 11, count 0 2006.225.08:05:41.23#ibcon#end of sib2, iclass 11, count 0 2006.225.08:05:41.23#ibcon#*after write, iclass 11, count 0 2006.225.08:05:41.23#ibcon#*before return 0, iclass 11, count 0 2006.225.08:05:41.23#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:05:41.23#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:05:41.23#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:05:41.23#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:05:41.23$vc4f8/vb=3,4 2006.225.08:05:41.23#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.08:05:41.23#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.08:05:41.23#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:41.23#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:05:41.30#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:05:41.30#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:05:41.30#ibcon#enter wrdev, iclass 13, count 2 2006.225.08:05:41.30#ibcon#first serial, iclass 13, count 2 2006.225.08:05:41.30#ibcon#enter sib2, iclass 13, count 2 2006.225.08:05:41.30#ibcon#flushed, iclass 13, count 2 2006.225.08:05:41.30#ibcon#about to write, iclass 13, count 2 2006.225.08:05:41.30#ibcon#wrote, iclass 13, count 2 2006.225.08:05:41.30#ibcon#about to read 3, iclass 13, count 2 2006.225.08:05:41.32#ibcon#read 3, iclass 13, count 2 2006.225.08:05:41.32#ibcon#about to read 4, iclass 13, count 2 2006.225.08:05:41.32#ibcon#read 4, iclass 13, count 2 2006.225.08:05:41.32#ibcon#about to read 5, iclass 13, count 2 2006.225.08:05:41.32#ibcon#read 5, iclass 13, count 2 2006.225.08:05:41.32#ibcon#about to read 6, iclass 13, count 2 2006.225.08:05:41.32#ibcon#read 6, iclass 13, count 2 2006.225.08:05:41.32#ibcon#end of sib2, iclass 13, count 2 2006.225.08:05:41.32#ibcon#*mode == 0, iclass 13, count 2 2006.225.08:05:41.32#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.08:05:41.32#ibcon#[27=AT03-04\r\n] 2006.225.08:05:41.32#ibcon#*before write, iclass 13, count 2 2006.225.08:05:41.32#ibcon#enter sib2, iclass 13, count 2 2006.225.08:05:41.32#ibcon#flushed, iclass 13, count 2 2006.225.08:05:41.32#ibcon#about to write, iclass 13, count 2 2006.225.08:05:41.32#ibcon#wrote, iclass 13, count 2 2006.225.08:05:41.32#ibcon#about to read 3, iclass 13, count 2 2006.225.08:05:41.34#ibcon#read 3, iclass 13, count 2 2006.225.08:05:41.34#ibcon#about to read 4, iclass 13, count 2 2006.225.08:05:41.34#ibcon#read 4, iclass 13, count 2 2006.225.08:05:41.34#ibcon#about to read 5, iclass 13, count 2 2006.225.08:05:41.34#ibcon#read 5, iclass 13, count 2 2006.225.08:05:41.34#ibcon#about to read 6, iclass 13, count 2 2006.225.08:05:41.34#ibcon#read 6, iclass 13, count 2 2006.225.08:05:41.34#ibcon#end of sib2, iclass 13, count 2 2006.225.08:05:41.34#ibcon#*after write, iclass 13, count 2 2006.225.08:05:41.34#ibcon#*before return 0, iclass 13, count 2 2006.225.08:05:41.34#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:05:41.34#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:05:41.34#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.08:05:41.34#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:41.34#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:05:41.46#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:05:41.46#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:05:41.46#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:05:41.46#ibcon#first serial, iclass 13, count 0 2006.225.08:05:41.46#ibcon#enter sib2, iclass 13, count 0 2006.225.08:05:41.46#ibcon#flushed, iclass 13, count 0 2006.225.08:05:41.46#ibcon#about to write, iclass 13, count 0 2006.225.08:05:41.46#ibcon#wrote, iclass 13, count 0 2006.225.08:05:41.46#ibcon#about to read 3, iclass 13, count 0 2006.225.08:05:41.48#ibcon#read 3, iclass 13, count 0 2006.225.08:05:41.48#ibcon#about to read 4, iclass 13, count 0 2006.225.08:05:41.48#ibcon#read 4, iclass 13, count 0 2006.225.08:05:41.48#ibcon#about to read 5, iclass 13, count 0 2006.225.08:05:41.48#ibcon#read 5, iclass 13, count 0 2006.225.08:05:41.48#ibcon#about to read 6, iclass 13, count 0 2006.225.08:05:41.48#ibcon#read 6, iclass 13, count 0 2006.225.08:05:41.48#ibcon#end of sib2, iclass 13, count 0 2006.225.08:05:41.48#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:05:41.48#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:05:41.48#ibcon#[27=USB\r\n] 2006.225.08:05:41.48#ibcon#*before write, iclass 13, count 0 2006.225.08:05:41.48#ibcon#enter sib2, iclass 13, count 0 2006.225.08:05:41.48#ibcon#flushed, iclass 13, count 0 2006.225.08:05:41.48#ibcon#about to write, iclass 13, count 0 2006.225.08:05:41.48#ibcon#wrote, iclass 13, count 0 2006.225.08:05:41.48#ibcon#about to read 3, iclass 13, count 0 2006.225.08:05:41.51#ibcon#read 3, iclass 13, count 0 2006.225.08:05:41.51#ibcon#about to read 4, iclass 13, count 0 2006.225.08:05:41.51#ibcon#read 4, iclass 13, count 0 2006.225.08:05:41.51#ibcon#about to read 5, iclass 13, count 0 2006.225.08:05:41.51#ibcon#read 5, iclass 13, count 0 2006.225.08:05:41.51#ibcon#about to read 6, iclass 13, count 0 2006.225.08:05:41.51#ibcon#read 6, iclass 13, count 0 2006.225.08:05:41.51#ibcon#end of sib2, iclass 13, count 0 2006.225.08:05:41.51#ibcon#*after write, iclass 13, count 0 2006.225.08:05:41.51#ibcon#*before return 0, iclass 13, count 0 2006.225.08:05:41.51#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:05:41.51#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:05:41.51#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:05:41.51#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:05:41.51$vc4f8/vblo=4,712.99 2006.225.08:05:41.51#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.08:05:41.51#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.08:05:41.51#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:41.51#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:05:41.51#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:05:41.51#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:05:41.51#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:05:41.51#ibcon#first serial, iclass 15, count 0 2006.225.08:05:41.51#ibcon#enter sib2, iclass 15, count 0 2006.225.08:05:41.51#ibcon#flushed, iclass 15, count 0 2006.225.08:05:41.51#ibcon#about to write, iclass 15, count 0 2006.225.08:05:41.52#ibcon#wrote, iclass 15, count 0 2006.225.08:05:41.52#ibcon#about to read 3, iclass 15, count 0 2006.225.08:05:41.53#ibcon#read 3, iclass 15, count 0 2006.225.08:05:41.53#ibcon#about to read 4, iclass 15, count 0 2006.225.08:05:41.53#ibcon#read 4, iclass 15, count 0 2006.225.08:05:41.53#ibcon#about to read 5, iclass 15, count 0 2006.225.08:05:41.53#ibcon#read 5, iclass 15, count 0 2006.225.08:05:41.53#ibcon#about to read 6, iclass 15, count 0 2006.225.08:05:41.53#ibcon#read 6, iclass 15, count 0 2006.225.08:05:41.53#ibcon#end of sib2, iclass 15, count 0 2006.225.08:05:41.53#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:05:41.53#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:05:41.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:05:41.53#ibcon#*before write, iclass 15, count 0 2006.225.08:05:41.53#ibcon#enter sib2, iclass 15, count 0 2006.225.08:05:41.53#ibcon#flushed, iclass 15, count 0 2006.225.08:05:41.53#ibcon#about to write, iclass 15, count 0 2006.225.08:05:41.53#ibcon#wrote, iclass 15, count 0 2006.225.08:05:41.53#ibcon#about to read 3, iclass 15, count 0 2006.225.08:05:41.57#ibcon#read 3, iclass 15, count 0 2006.225.08:05:41.57#ibcon#about to read 4, iclass 15, count 0 2006.225.08:05:41.57#ibcon#read 4, iclass 15, count 0 2006.225.08:05:41.57#ibcon#about to read 5, iclass 15, count 0 2006.225.08:05:41.57#ibcon#read 5, iclass 15, count 0 2006.225.08:05:41.57#ibcon#about to read 6, iclass 15, count 0 2006.225.08:05:41.57#ibcon#read 6, iclass 15, count 0 2006.225.08:05:41.57#ibcon#end of sib2, iclass 15, count 0 2006.225.08:05:41.57#ibcon#*after write, iclass 15, count 0 2006.225.08:05:41.57#ibcon#*before return 0, iclass 15, count 0 2006.225.08:05:41.57#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:05:41.57#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:05:41.57#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:05:41.57#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:05:41.57$vc4f8/vb=4,4 2006.225.08:05:41.57#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.08:05:41.57#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.08:05:41.57#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:41.57#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:05:41.63#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:05:41.63#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:05:41.63#ibcon#enter wrdev, iclass 17, count 2 2006.225.08:05:41.63#ibcon#first serial, iclass 17, count 2 2006.225.08:05:41.63#ibcon#enter sib2, iclass 17, count 2 2006.225.08:05:41.63#ibcon#flushed, iclass 17, count 2 2006.225.08:05:41.63#ibcon#about to write, iclass 17, count 2 2006.225.08:05:41.63#ibcon#wrote, iclass 17, count 2 2006.225.08:05:41.63#ibcon#about to read 3, iclass 17, count 2 2006.225.08:05:41.65#ibcon#read 3, iclass 17, count 2 2006.225.08:05:41.65#ibcon#about to read 4, iclass 17, count 2 2006.225.08:05:41.65#ibcon#read 4, iclass 17, count 2 2006.225.08:05:41.65#ibcon#about to read 5, iclass 17, count 2 2006.225.08:05:41.65#ibcon#read 5, iclass 17, count 2 2006.225.08:05:41.65#ibcon#about to read 6, iclass 17, count 2 2006.225.08:05:41.65#ibcon#read 6, iclass 17, count 2 2006.225.08:05:41.65#ibcon#end of sib2, iclass 17, count 2 2006.225.08:05:41.65#ibcon#*mode == 0, iclass 17, count 2 2006.225.08:05:41.65#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.08:05:41.65#ibcon#[27=AT04-04\r\n] 2006.225.08:05:41.65#ibcon#*before write, iclass 17, count 2 2006.225.08:05:41.65#ibcon#enter sib2, iclass 17, count 2 2006.225.08:05:41.65#ibcon#flushed, iclass 17, count 2 2006.225.08:05:41.65#ibcon#about to write, iclass 17, count 2 2006.225.08:05:41.65#ibcon#wrote, iclass 17, count 2 2006.225.08:05:41.65#ibcon#about to read 3, iclass 17, count 2 2006.225.08:05:41.68#ibcon#read 3, iclass 17, count 2 2006.225.08:05:41.68#ibcon#about to read 4, iclass 17, count 2 2006.225.08:05:41.68#ibcon#read 4, iclass 17, count 2 2006.225.08:05:41.68#ibcon#about to read 5, iclass 17, count 2 2006.225.08:05:41.68#ibcon#read 5, iclass 17, count 2 2006.225.08:05:41.68#ibcon#about to read 6, iclass 17, count 2 2006.225.08:05:41.68#ibcon#read 6, iclass 17, count 2 2006.225.08:05:41.68#ibcon#end of sib2, iclass 17, count 2 2006.225.08:05:41.68#ibcon#*after write, iclass 17, count 2 2006.225.08:05:41.68#ibcon#*before return 0, iclass 17, count 2 2006.225.08:05:41.68#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:05:41.68#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:05:41.68#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.08:05:41.68#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:41.68#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:05:41.80#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:05:41.80#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:05:41.80#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:05:41.80#ibcon#first serial, iclass 17, count 0 2006.225.08:05:41.80#ibcon#enter sib2, iclass 17, count 0 2006.225.08:05:41.80#ibcon#flushed, iclass 17, count 0 2006.225.08:05:41.80#ibcon#about to write, iclass 17, count 0 2006.225.08:05:41.80#ibcon#wrote, iclass 17, count 0 2006.225.08:05:41.80#ibcon#about to read 3, iclass 17, count 0 2006.225.08:05:41.82#ibcon#read 3, iclass 17, count 0 2006.225.08:05:41.82#ibcon#about to read 4, iclass 17, count 0 2006.225.08:05:41.82#ibcon#read 4, iclass 17, count 0 2006.225.08:05:41.82#ibcon#about to read 5, iclass 17, count 0 2006.225.08:05:41.82#ibcon#read 5, iclass 17, count 0 2006.225.08:05:41.82#ibcon#about to read 6, iclass 17, count 0 2006.225.08:05:41.82#ibcon#read 6, iclass 17, count 0 2006.225.08:05:41.82#ibcon#end of sib2, iclass 17, count 0 2006.225.08:05:41.82#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:05:41.82#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:05:41.82#ibcon#[27=USB\r\n] 2006.225.08:05:41.82#ibcon#*before write, iclass 17, count 0 2006.225.08:05:41.82#ibcon#enter sib2, iclass 17, count 0 2006.225.08:05:41.82#ibcon#flushed, iclass 17, count 0 2006.225.08:05:41.82#ibcon#about to write, iclass 17, count 0 2006.225.08:05:41.82#ibcon#wrote, iclass 17, count 0 2006.225.08:05:41.82#ibcon#about to read 3, iclass 17, count 0 2006.225.08:05:41.85#ibcon#read 3, iclass 17, count 0 2006.225.08:05:41.85#ibcon#about to read 4, iclass 17, count 0 2006.225.08:05:41.85#ibcon#read 4, iclass 17, count 0 2006.225.08:05:41.85#ibcon#about to read 5, iclass 17, count 0 2006.225.08:05:41.85#ibcon#read 5, iclass 17, count 0 2006.225.08:05:41.85#ibcon#about to read 6, iclass 17, count 0 2006.225.08:05:41.85#ibcon#read 6, iclass 17, count 0 2006.225.08:05:41.85#ibcon#end of sib2, iclass 17, count 0 2006.225.08:05:41.85#ibcon#*after write, iclass 17, count 0 2006.225.08:05:41.85#ibcon#*before return 0, iclass 17, count 0 2006.225.08:05:41.85#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:05:41.85#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:05:41.85#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:05:41.85#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:05:41.85$vc4f8/vblo=5,744.99 2006.225.08:05:41.85#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.08:05:41.85#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.08:05:41.85#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:41.85#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:05:41.85#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:05:41.85#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:05:41.85#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:05:41.85#ibcon#first serial, iclass 19, count 0 2006.225.08:05:41.85#ibcon#enter sib2, iclass 19, count 0 2006.225.08:05:41.86#ibcon#flushed, iclass 19, count 0 2006.225.08:05:41.86#ibcon#about to write, iclass 19, count 0 2006.225.08:05:41.86#ibcon#wrote, iclass 19, count 0 2006.225.08:05:41.86#ibcon#about to read 3, iclass 19, count 0 2006.225.08:05:41.87#ibcon#read 3, iclass 19, count 0 2006.225.08:05:41.87#ibcon#about to read 4, iclass 19, count 0 2006.225.08:05:41.87#ibcon#read 4, iclass 19, count 0 2006.225.08:05:41.87#ibcon#about to read 5, iclass 19, count 0 2006.225.08:05:41.87#ibcon#read 5, iclass 19, count 0 2006.225.08:05:41.87#ibcon#about to read 6, iclass 19, count 0 2006.225.08:05:41.87#ibcon#read 6, iclass 19, count 0 2006.225.08:05:41.87#ibcon#end of sib2, iclass 19, count 0 2006.225.08:05:41.87#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:05:41.87#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:05:41.87#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:05:41.87#ibcon#*before write, iclass 19, count 0 2006.225.08:05:41.87#ibcon#enter sib2, iclass 19, count 0 2006.225.08:05:41.87#ibcon#flushed, iclass 19, count 0 2006.225.08:05:41.87#ibcon#about to write, iclass 19, count 0 2006.225.08:05:41.87#ibcon#wrote, iclass 19, count 0 2006.225.08:05:41.87#ibcon#about to read 3, iclass 19, count 0 2006.225.08:05:41.91#ibcon#read 3, iclass 19, count 0 2006.225.08:05:41.91#ibcon#about to read 4, iclass 19, count 0 2006.225.08:05:41.91#ibcon#read 4, iclass 19, count 0 2006.225.08:05:41.91#ibcon#about to read 5, iclass 19, count 0 2006.225.08:05:41.91#ibcon#read 5, iclass 19, count 0 2006.225.08:05:41.91#ibcon#about to read 6, iclass 19, count 0 2006.225.08:05:41.91#ibcon#read 6, iclass 19, count 0 2006.225.08:05:41.91#ibcon#end of sib2, iclass 19, count 0 2006.225.08:05:41.91#ibcon#*after write, iclass 19, count 0 2006.225.08:05:41.91#ibcon#*before return 0, iclass 19, count 0 2006.225.08:05:41.91#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:05:41.91#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:05:41.91#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:05:41.91#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:05:41.91$vc4f8/vb=5,4 2006.225.08:05:41.91#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.225.08:05:41.91#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.225.08:05:41.91#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:41.91#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:05:41.97#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:05:41.97#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:05:41.97#ibcon#enter wrdev, iclass 21, count 2 2006.225.08:05:41.97#ibcon#first serial, iclass 21, count 2 2006.225.08:05:41.97#ibcon#enter sib2, iclass 21, count 2 2006.225.08:05:41.97#ibcon#flushed, iclass 21, count 2 2006.225.08:05:41.97#ibcon#about to write, iclass 21, count 2 2006.225.08:05:41.97#ibcon#wrote, iclass 21, count 2 2006.225.08:05:41.97#ibcon#about to read 3, iclass 21, count 2 2006.225.08:05:41.99#ibcon#read 3, iclass 21, count 2 2006.225.08:05:41.99#ibcon#about to read 4, iclass 21, count 2 2006.225.08:05:41.99#ibcon#read 4, iclass 21, count 2 2006.225.08:05:41.99#ibcon#about to read 5, iclass 21, count 2 2006.225.08:05:41.99#ibcon#read 5, iclass 21, count 2 2006.225.08:05:41.99#ibcon#about to read 6, iclass 21, count 2 2006.225.08:05:41.99#ibcon#read 6, iclass 21, count 2 2006.225.08:05:41.99#ibcon#end of sib2, iclass 21, count 2 2006.225.08:05:41.99#ibcon#*mode == 0, iclass 21, count 2 2006.225.08:05:41.99#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.225.08:05:41.99#ibcon#[27=AT05-04\r\n] 2006.225.08:05:41.99#ibcon#*before write, iclass 21, count 2 2006.225.08:05:41.99#ibcon#enter sib2, iclass 21, count 2 2006.225.08:05:41.99#ibcon#flushed, iclass 21, count 2 2006.225.08:05:41.99#ibcon#about to write, iclass 21, count 2 2006.225.08:05:41.99#ibcon#wrote, iclass 21, count 2 2006.225.08:05:41.99#ibcon#about to read 3, iclass 21, count 2 2006.225.08:05:42.02#ibcon#read 3, iclass 21, count 2 2006.225.08:05:42.02#ibcon#about to read 4, iclass 21, count 2 2006.225.08:05:42.02#ibcon#read 4, iclass 21, count 2 2006.225.08:05:42.02#ibcon#about to read 5, iclass 21, count 2 2006.225.08:05:42.02#ibcon#read 5, iclass 21, count 2 2006.225.08:05:42.02#ibcon#about to read 6, iclass 21, count 2 2006.225.08:05:42.02#ibcon#read 6, iclass 21, count 2 2006.225.08:05:42.02#ibcon#end of sib2, iclass 21, count 2 2006.225.08:05:42.02#ibcon#*after write, iclass 21, count 2 2006.225.08:05:42.02#ibcon#*before return 0, iclass 21, count 2 2006.225.08:05:42.02#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:05:42.02#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:05:42.02#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.225.08:05:42.02#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:42.02#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:05:42.15#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:05:42.15#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:05:42.15#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:05:42.15#ibcon#first serial, iclass 21, count 0 2006.225.08:05:42.15#ibcon#enter sib2, iclass 21, count 0 2006.225.08:05:42.15#ibcon#flushed, iclass 21, count 0 2006.225.08:05:42.15#ibcon#about to write, iclass 21, count 0 2006.225.08:05:42.15#ibcon#wrote, iclass 21, count 0 2006.225.08:05:42.15#ibcon#about to read 3, iclass 21, count 0 2006.225.08:05:42.16#ibcon#read 3, iclass 21, count 0 2006.225.08:05:42.16#ibcon#about to read 4, iclass 21, count 0 2006.225.08:05:42.16#ibcon#read 4, iclass 21, count 0 2006.225.08:05:42.16#ibcon#about to read 5, iclass 21, count 0 2006.225.08:05:42.16#ibcon#read 5, iclass 21, count 0 2006.225.08:05:42.16#ibcon#about to read 6, iclass 21, count 0 2006.225.08:05:42.16#ibcon#read 6, iclass 21, count 0 2006.225.08:05:42.16#ibcon#end of sib2, iclass 21, count 0 2006.225.08:05:42.16#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:05:42.16#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:05:42.16#ibcon#[27=USB\r\n] 2006.225.08:05:42.16#ibcon#*before write, iclass 21, count 0 2006.225.08:05:42.16#ibcon#enter sib2, iclass 21, count 0 2006.225.08:05:42.16#ibcon#flushed, iclass 21, count 0 2006.225.08:05:42.16#ibcon#about to write, iclass 21, count 0 2006.225.08:05:42.16#ibcon#wrote, iclass 21, count 0 2006.225.08:05:42.16#ibcon#about to read 3, iclass 21, count 0 2006.225.08:05:42.19#ibcon#read 3, iclass 21, count 0 2006.225.08:05:42.19#ibcon#about to read 4, iclass 21, count 0 2006.225.08:05:42.19#ibcon#read 4, iclass 21, count 0 2006.225.08:05:42.19#ibcon#about to read 5, iclass 21, count 0 2006.225.08:05:42.19#ibcon#read 5, iclass 21, count 0 2006.225.08:05:42.19#ibcon#about to read 6, iclass 21, count 0 2006.225.08:05:42.19#ibcon#read 6, iclass 21, count 0 2006.225.08:05:42.19#ibcon#end of sib2, iclass 21, count 0 2006.225.08:05:42.19#ibcon#*after write, iclass 21, count 0 2006.225.08:05:42.19#ibcon#*before return 0, iclass 21, count 0 2006.225.08:05:42.19#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:05:42.19#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:05:42.19#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:05:42.19#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:05:42.19$vc4f8/vblo=6,752.99 2006.225.08:05:42.19#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.225.08:05:42.19#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.225.08:05:42.19#ibcon#ireg 17 cls_cnt 0 2006.225.08:05:42.19#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:05:42.19#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:05:42.19#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:05:42.19#ibcon#enter wrdev, iclass 23, count 0 2006.225.08:05:42.19#ibcon#first serial, iclass 23, count 0 2006.225.08:05:42.19#ibcon#enter sib2, iclass 23, count 0 2006.225.08:05:42.20#ibcon#flushed, iclass 23, count 0 2006.225.08:05:42.20#ibcon#about to write, iclass 23, count 0 2006.225.08:05:42.20#ibcon#wrote, iclass 23, count 0 2006.225.08:05:42.20#ibcon#about to read 3, iclass 23, count 0 2006.225.08:05:42.22#ibcon#read 3, iclass 23, count 0 2006.225.08:05:42.22#ibcon#about to read 4, iclass 23, count 0 2006.225.08:05:42.22#ibcon#read 4, iclass 23, count 0 2006.225.08:05:42.22#ibcon#about to read 5, iclass 23, count 0 2006.225.08:05:42.22#ibcon#read 5, iclass 23, count 0 2006.225.08:05:42.22#ibcon#about to read 6, iclass 23, count 0 2006.225.08:05:42.22#ibcon#read 6, iclass 23, count 0 2006.225.08:05:42.22#ibcon#end of sib2, iclass 23, count 0 2006.225.08:05:42.22#ibcon#*mode == 0, iclass 23, count 0 2006.225.08:05:42.22#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.08:05:42.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:05:42.22#ibcon#*before write, iclass 23, count 0 2006.225.08:05:42.22#ibcon#enter sib2, iclass 23, count 0 2006.225.08:05:42.22#ibcon#flushed, iclass 23, count 0 2006.225.08:05:42.22#ibcon#about to write, iclass 23, count 0 2006.225.08:05:42.22#ibcon#wrote, iclass 23, count 0 2006.225.08:05:42.22#ibcon#about to read 3, iclass 23, count 0 2006.225.08:05:42.26#ibcon#read 3, iclass 23, count 0 2006.225.08:05:42.26#ibcon#about to read 4, iclass 23, count 0 2006.225.08:05:42.26#ibcon#read 4, iclass 23, count 0 2006.225.08:05:42.26#ibcon#about to read 5, iclass 23, count 0 2006.225.08:05:42.26#ibcon#read 5, iclass 23, count 0 2006.225.08:05:42.26#ibcon#about to read 6, iclass 23, count 0 2006.225.08:05:42.26#ibcon#read 6, iclass 23, count 0 2006.225.08:05:42.26#ibcon#end of sib2, iclass 23, count 0 2006.225.08:05:42.26#ibcon#*after write, iclass 23, count 0 2006.225.08:05:42.26#ibcon#*before return 0, iclass 23, count 0 2006.225.08:05:42.26#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:05:42.26#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:05:42.26#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.08:05:42.26#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.08:05:42.26$vc4f8/vb=6,4 2006.225.08:05:42.26#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.225.08:05:42.26#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.225.08:05:42.26#ibcon#ireg 11 cls_cnt 2 2006.225.08:05:42.26#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:05:42.32#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:05:42.32#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:05:42.32#ibcon#enter wrdev, iclass 25, count 2 2006.225.08:05:42.32#ibcon#first serial, iclass 25, count 2 2006.225.08:05:42.32#ibcon#enter sib2, iclass 25, count 2 2006.225.08:05:42.32#ibcon#flushed, iclass 25, count 2 2006.225.08:05:42.32#ibcon#about to write, iclass 25, count 2 2006.225.08:05:42.32#ibcon#wrote, iclass 25, count 2 2006.225.08:05:42.32#ibcon#about to read 3, iclass 25, count 2 2006.225.08:05:42.33#ibcon#read 3, iclass 25, count 2 2006.225.08:05:42.33#ibcon#about to read 4, iclass 25, count 2 2006.225.08:05:42.33#ibcon#read 4, iclass 25, count 2 2006.225.08:05:42.33#ibcon#about to read 5, iclass 25, count 2 2006.225.08:05:42.33#ibcon#read 5, iclass 25, count 2 2006.225.08:05:42.33#ibcon#about to read 6, iclass 25, count 2 2006.225.08:05:42.33#ibcon#read 6, iclass 25, count 2 2006.225.08:05:42.33#ibcon#end of sib2, iclass 25, count 2 2006.225.08:05:42.33#ibcon#*mode == 0, iclass 25, count 2 2006.225.08:05:42.33#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.225.08:05:42.33#ibcon#[27=AT06-04\r\n] 2006.225.08:05:42.33#ibcon#*before write, iclass 25, count 2 2006.225.08:05:42.33#ibcon#enter sib2, iclass 25, count 2 2006.225.08:05:42.33#ibcon#flushed, iclass 25, count 2 2006.225.08:05:42.33#ibcon#about to write, iclass 25, count 2 2006.225.08:05:42.33#ibcon#wrote, iclass 25, count 2 2006.225.08:05:42.33#ibcon#about to read 3, iclass 25, count 2 2006.225.08:05:42.36#ibcon#read 3, iclass 25, count 2 2006.225.08:05:42.36#ibcon#about to read 4, iclass 25, count 2 2006.225.08:05:42.36#ibcon#read 4, iclass 25, count 2 2006.225.08:05:42.36#ibcon#about to read 5, iclass 25, count 2 2006.225.08:05:42.36#ibcon#read 5, iclass 25, count 2 2006.225.08:05:42.36#ibcon#about to read 6, iclass 25, count 2 2006.225.08:05:42.36#ibcon#read 6, iclass 25, count 2 2006.225.08:05:42.36#ibcon#end of sib2, iclass 25, count 2 2006.225.08:05:42.36#ibcon#*after write, iclass 25, count 2 2006.225.08:05:42.36#ibcon#*before return 0, iclass 25, count 2 2006.225.08:05:42.36#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:05:42.36#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:05:42.36#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.225.08:05:42.36#ibcon#ireg 7 cls_cnt 0 2006.225.08:05:42.36#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:05:42.48#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:05:42.48#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:05:42.48#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:05:42.48#ibcon#first serial, iclass 25, count 0 2006.225.08:05:42.48#ibcon#enter sib2, iclass 25, count 0 2006.225.08:05:42.48#ibcon#flushed, iclass 25, count 0 2006.225.08:05:42.48#ibcon#about to write, iclass 25, count 0 2006.225.08:05:42.48#ibcon#wrote, iclass 25, count 0 2006.225.08:05:42.48#ibcon#about to read 3, iclass 25, count 0 2006.225.08:05:42.50#ibcon#read 3, iclass 25, count 0 2006.225.08:05:42.50#ibcon#about to read 4, iclass 25, count 0 2006.225.08:05:42.50#ibcon#read 4, iclass 25, count 0 2006.225.08:05:42.50#ibcon#about to read 5, iclass 25, count 0 2006.225.08:05:42.50#ibcon#read 5, iclass 25, count 0 2006.225.08:05:42.50#ibcon#about to read 6, iclass 25, count 0 2006.225.08:05:42.50#ibcon#read 6, iclass 25, count 0 2006.225.08:05:42.50#ibcon#end of sib2, iclass 25, count 0 2006.225.08:05:42.50#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:05:42.50#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:05:42.50#ibcon#[27=USB\r\n] 2006.225.08:05:42.50#ibcon#*before write, iclass 25, count 0 2006.225.08:05:42.50#ibcon#enter sib2, iclass 25, count 0 2006.225.08:05:42.50#ibcon#flushed, iclass 25, count 0 2006.225.08:05:42.50#ibcon#about to write, iclass 25, count 0 2006.225.08:05:42.50#ibcon#wrote, iclass 25, count 0 2006.225.08:05:42.50#ibcon#about to read 3, iclass 25, count 0 2006.225.08:05:42.53#ibcon#read 3, iclass 25, count 0 2006.225.08:05:42.53#ibcon#about to read 4, iclass 25, count 0 2006.225.08:05:42.53#ibcon#read 4, iclass 25, count 0 2006.225.08:05:42.53#ibcon#about to read 5, iclass 25, count 0 2006.225.08:05:42.53#ibcon#read 5, iclass 25, count 0 2006.225.08:05:42.53#ibcon#about to read 6, iclass 25, count 0 2006.225.08:05:42.53#ibcon#read 6, iclass 25, count 0 2006.225.08:05:42.53#ibcon#end of sib2, iclass 25, count 0 2006.225.08:05:42.53#ibcon#*after write, iclass 25, count 0 2006.225.08:05:42.53#ibcon#*before return 0, iclass 25, count 0 2006.225.08:05:42.53#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:05:42.53#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:05:42.53#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:05:42.53#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:05:42.53$vc4f8/vabw=wide 2006.225.08:05:42.53#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.08:05:42.53#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.08:05:42.53#ibcon#ireg 8 cls_cnt 0 2006.225.08:05:42.53#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:05:42.53#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:05:42.53#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:05:42.53#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:05:42.53#ibcon#first serial, iclass 27, count 0 2006.225.08:05:42.53#ibcon#enter sib2, iclass 27, count 0 2006.225.08:05:42.53#ibcon#flushed, iclass 27, count 0 2006.225.08:05:42.53#ibcon#about to write, iclass 27, count 0 2006.225.08:05:42.53#ibcon#wrote, iclass 27, count 0 2006.225.08:05:42.54#ibcon#about to read 3, iclass 27, count 0 2006.225.08:05:42.55#ibcon#read 3, iclass 27, count 0 2006.225.08:05:42.55#ibcon#about to read 4, iclass 27, count 0 2006.225.08:05:42.55#ibcon#read 4, iclass 27, count 0 2006.225.08:05:42.55#ibcon#about to read 5, iclass 27, count 0 2006.225.08:05:42.55#ibcon#read 5, iclass 27, count 0 2006.225.08:05:42.55#ibcon#about to read 6, iclass 27, count 0 2006.225.08:05:42.55#ibcon#read 6, iclass 27, count 0 2006.225.08:05:42.55#ibcon#end of sib2, iclass 27, count 0 2006.225.08:05:42.55#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:05:42.55#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:05:42.55#ibcon#[25=BW32\r\n] 2006.225.08:05:42.55#ibcon#*before write, iclass 27, count 0 2006.225.08:05:42.55#ibcon#enter sib2, iclass 27, count 0 2006.225.08:05:42.55#ibcon#flushed, iclass 27, count 0 2006.225.08:05:42.55#ibcon#about to write, iclass 27, count 0 2006.225.08:05:42.55#ibcon#wrote, iclass 27, count 0 2006.225.08:05:42.55#ibcon#about to read 3, iclass 27, count 0 2006.225.08:05:42.58#ibcon#read 3, iclass 27, count 0 2006.225.08:05:42.58#ibcon#about to read 4, iclass 27, count 0 2006.225.08:05:42.58#ibcon#read 4, iclass 27, count 0 2006.225.08:05:42.58#ibcon#about to read 5, iclass 27, count 0 2006.225.08:05:42.58#ibcon#read 5, iclass 27, count 0 2006.225.08:05:42.58#ibcon#about to read 6, iclass 27, count 0 2006.225.08:05:42.58#ibcon#read 6, iclass 27, count 0 2006.225.08:05:42.58#ibcon#end of sib2, iclass 27, count 0 2006.225.08:05:42.58#ibcon#*after write, iclass 27, count 0 2006.225.08:05:42.58#ibcon#*before return 0, iclass 27, count 0 2006.225.08:05:42.58#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:05:42.58#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:05:42.58#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:05:42.58#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:05:42.58$vc4f8/vbbw=wide 2006.225.08:05:42.58#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.08:05:42.58#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.08:05:42.58#ibcon#ireg 8 cls_cnt 0 2006.225.08:05:42.58#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:05:42.65#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:05:42.65#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:05:42.65#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:05:42.65#ibcon#first serial, iclass 29, count 0 2006.225.08:05:42.65#ibcon#enter sib2, iclass 29, count 0 2006.225.08:05:42.65#ibcon#flushed, iclass 29, count 0 2006.225.08:05:42.65#ibcon#about to write, iclass 29, count 0 2006.225.08:05:42.65#ibcon#wrote, iclass 29, count 0 2006.225.08:05:42.65#ibcon#about to read 3, iclass 29, count 0 2006.225.08:05:42.67#ibcon#read 3, iclass 29, count 0 2006.225.08:05:42.67#ibcon#about to read 4, iclass 29, count 0 2006.225.08:05:42.67#ibcon#read 4, iclass 29, count 0 2006.225.08:05:42.67#ibcon#about to read 5, iclass 29, count 0 2006.225.08:05:42.67#ibcon#read 5, iclass 29, count 0 2006.225.08:05:42.67#ibcon#about to read 6, iclass 29, count 0 2006.225.08:05:42.67#ibcon#read 6, iclass 29, count 0 2006.225.08:05:42.67#ibcon#end of sib2, iclass 29, count 0 2006.225.08:05:42.67#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:05:42.67#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:05:42.67#ibcon#[27=BW32\r\n] 2006.225.08:05:42.67#ibcon#*before write, iclass 29, count 0 2006.225.08:05:42.67#ibcon#enter sib2, iclass 29, count 0 2006.225.08:05:42.67#ibcon#flushed, iclass 29, count 0 2006.225.08:05:42.67#ibcon#about to write, iclass 29, count 0 2006.225.08:05:42.67#ibcon#wrote, iclass 29, count 0 2006.225.08:05:42.67#ibcon#about to read 3, iclass 29, count 0 2006.225.08:05:42.70#ibcon#read 3, iclass 29, count 0 2006.225.08:05:42.70#ibcon#about to read 4, iclass 29, count 0 2006.225.08:05:42.70#ibcon#read 4, iclass 29, count 0 2006.225.08:05:42.70#ibcon#about to read 5, iclass 29, count 0 2006.225.08:05:42.70#ibcon#read 5, iclass 29, count 0 2006.225.08:05:42.70#ibcon#about to read 6, iclass 29, count 0 2006.225.08:05:42.70#ibcon#read 6, iclass 29, count 0 2006.225.08:05:42.70#ibcon#end of sib2, iclass 29, count 0 2006.225.08:05:42.70#ibcon#*after write, iclass 29, count 0 2006.225.08:05:42.70#ibcon#*before return 0, iclass 29, count 0 2006.225.08:05:42.70#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:05:42.70#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:05:42.70#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:05:42.70#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:05:42.70$4f8m12a/ifd4f 2006.225.08:05:42.70$ifd4f/lo= 2006.225.08:05:42.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:05:42.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:05:42.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:05:42.71$ifd4f/patch= 2006.225.08:05:42.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:05:42.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:05:42.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:05:42.71$4f8m12a/"form=m,16.000,1:2 2006.225.08:05:42.71$4f8m12a/"tpicd 2006.225.08:05:42.71$4f8m12a/echo=off 2006.225.08:05:42.71$4f8m12a/xlog=off 2006.225.08:05:42.71:!2006.225.08:06:10 2006.225.08:05:52.14#trakl#Source acquired 2006.225.08:05:52.14#flagr#flagr/antenna,acquired 2006.225.08:06:10.01:preob 2006.225.08:06:11.14/onsource/TRACKING 2006.225.08:06:11.14:!2006.225.08:06:20 2006.225.08:06:20.00:data_valid=on 2006.225.08:06:20.00:midob 2006.225.08:06:20.14/onsource/TRACKING 2006.225.08:06:20.15/wx/28.18,1003.4,70 2006.225.08:06:20.29/cable/+6.4038E-03 2006.225.08:06:21.38/va/01,08,usb,yes,29,30 2006.225.08:06:21.38/va/02,07,usb,yes,29,30 2006.225.08:06:21.38/va/03,06,usb,yes,30,31 2006.225.08:06:21.38/va/04,07,usb,yes,30,32 2006.225.08:06:21.38/va/05,07,usb,yes,32,34 2006.225.08:06:21.38/va/06,06,usb,yes,31,31 2006.225.08:06:21.38/va/07,06,usb,yes,32,31 2006.225.08:06:21.38/va/08,07,usb,yes,30,29 2006.225.08:06:21.61/valo/01,532.99,yes,locked 2006.225.08:06:21.61/valo/02,572.99,yes,locked 2006.225.08:06:21.61/valo/03,672.99,yes,locked 2006.225.08:06:21.61/valo/04,832.99,yes,locked 2006.225.08:06:21.61/valo/05,652.99,yes,locked 2006.225.08:06:21.61/valo/06,772.99,yes,locked 2006.225.08:06:21.61/valo/07,832.99,yes,locked 2006.225.08:06:21.61/valo/08,852.99,yes,locked 2006.225.08:06:22.70/vb/01,04,usb,yes,30,29 2006.225.08:06:22.70/vb/02,04,usb,yes,32,33 2006.225.08:06:22.70/vb/03,04,usb,yes,28,32 2006.225.08:06:22.70/vb/04,04,usb,yes,29,29 2006.225.08:06:22.70/vb/05,04,usb,yes,28,32 2006.225.08:06:22.70/vb/06,04,usb,yes,29,32 2006.225.08:06:22.70/vb/07,04,usb,yes,31,31 2006.225.08:06:22.70/vb/08,04,usb,yes,28,32 2006.225.08:06:22.94/vblo/01,632.99,yes,locked 2006.225.08:06:22.94/vblo/02,640.99,yes,locked 2006.225.08:06:22.94/vblo/03,656.99,yes,locked 2006.225.08:06:22.94/vblo/04,712.99,yes,locked 2006.225.08:06:22.94/vblo/05,744.99,yes,locked 2006.225.08:06:22.94/vblo/06,752.99,yes,locked 2006.225.08:06:22.94/vblo/07,734.99,yes,locked 2006.225.08:06:22.94/vblo/08,744.99,yes,locked 2006.225.08:06:23.09/vabw/8 2006.225.08:06:23.24/vbbw/8 2006.225.08:06:23.33/xfe/off,on,15.2 2006.225.08:06:23.72/ifatt/23,28,28,28 2006.225.08:06:24.07/fmout-gps/S +4.59E-07 2006.225.08:06:24.12:!2006.225.08:07:20 2006.225.08:07:20.01:data_valid=off 2006.225.08:07:20.02:postob 2006.225.08:07:20.13/cable/+6.4031E-03 2006.225.08:07:20.13/wx/28.16,1003.4,70 2006.225.08:07:21.07/fmout-gps/S +4.59E-07 2006.225.08:07:21.07:scan_name=225-0808,k06225,60 2006.225.08:07:21.07:source=3c418,203837.03,511912.7,2000.0,cw 2006.225.08:07:21.14#flagr#flagr/antenna,new-source 2006.225.08:07:22.14:checkk5 2006.225.08:07:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:07:22.89/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:07:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:07:23.64/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:07:24.01/chk_obsdata//k5ts1/T2250806??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:07:24.37/chk_obsdata//k5ts2/T2250806??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:07:24.74/chk_obsdata//k5ts3/T2250806??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:07:25.11/chk_obsdata//k5ts4/T2250806??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:07:25.81/k5log//k5ts1_log_newline 2006.225.08:07:26.49/k5log//k5ts2_log_newline 2006.225.08:07:27.18/k5log//k5ts3_log_newline 2006.225.08:07:27.86/k5log//k5ts4_log_newline 2006.225.08:07:27.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:07:27.89:4f8m12a=2 2006.225.08:07:27.89$4f8m12a/echo=on 2006.225.08:07:27.89$4f8m12a/pcalon 2006.225.08:07:27.89$pcalon/"no phase cal control is implemented here 2006.225.08:07:27.89$4f8m12a/"tpicd=stop 2006.225.08:07:27.89$4f8m12a/vc4f8 2006.225.08:07:27.89$vc4f8/valo=1,532.99 2006.225.08:07:27.90#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.08:07:27.90#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.08:07:27.90#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:27.90#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:07:27.90#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:07:27.90#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:07:27.90#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:07:27.90#ibcon#first serial, iclass 31, count 0 2006.225.08:07:27.90#ibcon#enter sib2, iclass 31, count 0 2006.225.08:07:27.90#ibcon#flushed, iclass 31, count 0 2006.225.08:07:27.90#ibcon#about to write, iclass 31, count 0 2006.225.08:07:27.90#ibcon#wrote, iclass 31, count 0 2006.225.08:07:27.90#ibcon#about to read 3, iclass 31, count 0 2006.225.08:07:27.93#ibcon#read 3, iclass 31, count 0 2006.225.08:07:27.93#ibcon#about to read 4, iclass 31, count 0 2006.225.08:07:27.93#ibcon#read 4, iclass 31, count 0 2006.225.08:07:27.93#ibcon#about to read 5, iclass 31, count 0 2006.225.08:07:27.93#ibcon#read 5, iclass 31, count 0 2006.225.08:07:27.93#ibcon#about to read 6, iclass 31, count 0 2006.225.08:07:27.93#ibcon#read 6, iclass 31, count 0 2006.225.08:07:27.93#ibcon#end of sib2, iclass 31, count 0 2006.225.08:07:27.93#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:07:27.93#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:07:27.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:07:27.93#ibcon#*before write, iclass 31, count 0 2006.225.08:07:27.93#ibcon#enter sib2, iclass 31, count 0 2006.225.08:07:27.93#ibcon#flushed, iclass 31, count 0 2006.225.08:07:27.93#ibcon#about to write, iclass 31, count 0 2006.225.08:07:27.93#ibcon#wrote, iclass 31, count 0 2006.225.08:07:27.93#ibcon#about to read 3, iclass 31, count 0 2006.225.08:07:27.98#ibcon#read 3, iclass 31, count 0 2006.225.08:07:27.98#ibcon#about to read 4, iclass 31, count 0 2006.225.08:07:27.98#ibcon#read 4, iclass 31, count 0 2006.225.08:07:27.98#ibcon#about to read 5, iclass 31, count 0 2006.225.08:07:27.98#ibcon#read 5, iclass 31, count 0 2006.225.08:07:27.98#ibcon#about to read 6, iclass 31, count 0 2006.225.08:07:27.98#ibcon#read 6, iclass 31, count 0 2006.225.08:07:27.98#ibcon#end of sib2, iclass 31, count 0 2006.225.08:07:27.98#ibcon#*after write, iclass 31, count 0 2006.225.08:07:27.98#ibcon#*before return 0, iclass 31, count 0 2006.225.08:07:27.98#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:07:27.98#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:07:27.98#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:07:27.98#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:07:27.98$vc4f8/va=1,8 2006.225.08:07:27.98#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.225.08:07:27.98#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.225.08:07:27.98#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:27.98#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:07:27.98#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:07:27.98#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:07:27.98#ibcon#enter wrdev, iclass 33, count 2 2006.225.08:07:27.98#ibcon#first serial, iclass 33, count 2 2006.225.08:07:27.98#ibcon#enter sib2, iclass 33, count 2 2006.225.08:07:27.98#ibcon#flushed, iclass 33, count 2 2006.225.08:07:27.98#ibcon#about to write, iclass 33, count 2 2006.225.08:07:27.98#ibcon#wrote, iclass 33, count 2 2006.225.08:07:27.98#ibcon#about to read 3, iclass 33, count 2 2006.225.08:07:28.01#ibcon#read 3, iclass 33, count 2 2006.225.08:07:28.01#ibcon#about to read 4, iclass 33, count 2 2006.225.08:07:28.01#ibcon#read 4, iclass 33, count 2 2006.225.08:07:28.01#ibcon#about to read 5, iclass 33, count 2 2006.225.08:07:28.01#ibcon#read 5, iclass 33, count 2 2006.225.08:07:28.01#ibcon#about to read 6, iclass 33, count 2 2006.225.08:07:28.01#ibcon#read 6, iclass 33, count 2 2006.225.08:07:28.01#ibcon#end of sib2, iclass 33, count 2 2006.225.08:07:28.01#ibcon#*mode == 0, iclass 33, count 2 2006.225.08:07:28.01#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.225.08:07:28.01#ibcon#[25=AT01-08\r\n] 2006.225.08:07:28.01#ibcon#*before write, iclass 33, count 2 2006.225.08:07:28.01#ibcon#enter sib2, iclass 33, count 2 2006.225.08:07:28.01#ibcon#flushed, iclass 33, count 2 2006.225.08:07:28.01#ibcon#about to write, iclass 33, count 2 2006.225.08:07:28.01#ibcon#wrote, iclass 33, count 2 2006.225.08:07:28.01#ibcon#about to read 3, iclass 33, count 2 2006.225.08:07:28.04#ibcon#read 3, iclass 33, count 2 2006.225.08:07:28.04#ibcon#about to read 4, iclass 33, count 2 2006.225.08:07:28.04#ibcon#read 4, iclass 33, count 2 2006.225.08:07:28.04#ibcon#about to read 5, iclass 33, count 2 2006.225.08:07:28.04#ibcon#read 5, iclass 33, count 2 2006.225.08:07:28.04#ibcon#about to read 6, iclass 33, count 2 2006.225.08:07:28.04#ibcon#read 6, iclass 33, count 2 2006.225.08:07:28.04#ibcon#end of sib2, iclass 33, count 2 2006.225.08:07:28.04#ibcon#*after write, iclass 33, count 2 2006.225.08:07:28.04#ibcon#*before return 0, iclass 33, count 2 2006.225.08:07:28.04#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:07:28.04#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:07:28.04#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.225.08:07:28.04#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:28.04#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:07:28.16#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:07:28.16#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:07:28.16#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:07:28.16#ibcon#first serial, iclass 33, count 0 2006.225.08:07:28.16#ibcon#enter sib2, iclass 33, count 0 2006.225.08:07:28.16#ibcon#flushed, iclass 33, count 0 2006.225.08:07:28.16#ibcon#about to write, iclass 33, count 0 2006.225.08:07:28.16#ibcon#wrote, iclass 33, count 0 2006.225.08:07:28.16#ibcon#about to read 3, iclass 33, count 0 2006.225.08:07:28.18#ibcon#read 3, iclass 33, count 0 2006.225.08:07:28.18#ibcon#about to read 4, iclass 33, count 0 2006.225.08:07:28.18#ibcon#read 4, iclass 33, count 0 2006.225.08:07:28.18#ibcon#about to read 5, iclass 33, count 0 2006.225.08:07:28.18#ibcon#read 5, iclass 33, count 0 2006.225.08:07:28.18#ibcon#about to read 6, iclass 33, count 0 2006.225.08:07:28.18#ibcon#read 6, iclass 33, count 0 2006.225.08:07:28.18#ibcon#end of sib2, iclass 33, count 0 2006.225.08:07:28.18#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:07:28.18#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:07:28.18#ibcon#[25=USB\r\n] 2006.225.08:07:28.18#ibcon#*before write, iclass 33, count 0 2006.225.08:07:28.18#ibcon#enter sib2, iclass 33, count 0 2006.225.08:07:28.18#ibcon#flushed, iclass 33, count 0 2006.225.08:07:28.18#ibcon#about to write, iclass 33, count 0 2006.225.08:07:28.18#ibcon#wrote, iclass 33, count 0 2006.225.08:07:28.18#ibcon#about to read 3, iclass 33, count 0 2006.225.08:07:28.21#ibcon#read 3, iclass 33, count 0 2006.225.08:07:28.21#ibcon#about to read 4, iclass 33, count 0 2006.225.08:07:28.21#ibcon#read 4, iclass 33, count 0 2006.225.08:07:28.21#ibcon#about to read 5, iclass 33, count 0 2006.225.08:07:28.21#ibcon#read 5, iclass 33, count 0 2006.225.08:07:28.21#ibcon#about to read 6, iclass 33, count 0 2006.225.08:07:28.21#ibcon#read 6, iclass 33, count 0 2006.225.08:07:28.21#ibcon#end of sib2, iclass 33, count 0 2006.225.08:07:28.21#ibcon#*after write, iclass 33, count 0 2006.225.08:07:28.21#ibcon#*before return 0, iclass 33, count 0 2006.225.08:07:28.21#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:07:28.21#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:07:28.21#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:07:28.21#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:07:28.21$vc4f8/valo=2,572.99 2006.225.08:07:28.21#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.225.08:07:28.21#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.225.08:07:28.21#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:28.21#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:07:28.21#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:07:28.21#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:07:28.21#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:07:28.21#ibcon#first serial, iclass 35, count 0 2006.225.08:07:28.21#ibcon#enter sib2, iclass 35, count 0 2006.225.08:07:28.21#ibcon#flushed, iclass 35, count 0 2006.225.08:07:28.21#ibcon#about to write, iclass 35, count 0 2006.225.08:07:28.21#ibcon#wrote, iclass 35, count 0 2006.225.08:07:28.21#ibcon#about to read 3, iclass 35, count 0 2006.225.08:07:28.23#ibcon#read 3, iclass 35, count 0 2006.225.08:07:28.23#ibcon#about to read 4, iclass 35, count 0 2006.225.08:07:28.23#ibcon#read 4, iclass 35, count 0 2006.225.08:07:28.23#ibcon#about to read 5, iclass 35, count 0 2006.225.08:07:28.23#ibcon#read 5, iclass 35, count 0 2006.225.08:07:28.23#ibcon#about to read 6, iclass 35, count 0 2006.225.08:07:28.23#ibcon#read 6, iclass 35, count 0 2006.225.08:07:28.23#ibcon#end of sib2, iclass 35, count 0 2006.225.08:07:28.23#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:07:28.23#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:07:28.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:07:28.23#ibcon#*before write, iclass 35, count 0 2006.225.08:07:28.23#ibcon#enter sib2, iclass 35, count 0 2006.225.08:07:28.23#ibcon#flushed, iclass 35, count 0 2006.225.08:07:28.23#ibcon#about to write, iclass 35, count 0 2006.225.08:07:28.23#ibcon#wrote, iclass 35, count 0 2006.225.08:07:28.23#ibcon#about to read 3, iclass 35, count 0 2006.225.08:07:28.27#ibcon#read 3, iclass 35, count 0 2006.225.08:07:28.27#ibcon#about to read 4, iclass 35, count 0 2006.225.08:07:28.27#ibcon#read 4, iclass 35, count 0 2006.225.08:07:28.27#ibcon#about to read 5, iclass 35, count 0 2006.225.08:07:28.27#ibcon#read 5, iclass 35, count 0 2006.225.08:07:28.27#ibcon#about to read 6, iclass 35, count 0 2006.225.08:07:28.27#ibcon#read 6, iclass 35, count 0 2006.225.08:07:28.27#ibcon#end of sib2, iclass 35, count 0 2006.225.08:07:28.27#ibcon#*after write, iclass 35, count 0 2006.225.08:07:28.27#ibcon#*before return 0, iclass 35, count 0 2006.225.08:07:28.27#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:07:28.27#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:07:28.27#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:07:28.27#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:07:28.27$vc4f8/va=2,7 2006.225.08:07:28.27#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.225.08:07:28.27#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.225.08:07:28.27#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:28.27#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:07:28.33#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:07:28.33#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:07:28.33#ibcon#enter wrdev, iclass 37, count 2 2006.225.08:07:28.33#ibcon#first serial, iclass 37, count 2 2006.225.08:07:28.33#ibcon#enter sib2, iclass 37, count 2 2006.225.08:07:28.33#ibcon#flushed, iclass 37, count 2 2006.225.08:07:28.33#ibcon#about to write, iclass 37, count 2 2006.225.08:07:28.33#ibcon#wrote, iclass 37, count 2 2006.225.08:07:28.33#ibcon#about to read 3, iclass 37, count 2 2006.225.08:07:28.35#ibcon#read 3, iclass 37, count 2 2006.225.08:07:28.35#ibcon#about to read 4, iclass 37, count 2 2006.225.08:07:28.35#ibcon#read 4, iclass 37, count 2 2006.225.08:07:28.35#ibcon#about to read 5, iclass 37, count 2 2006.225.08:07:28.35#ibcon#read 5, iclass 37, count 2 2006.225.08:07:28.35#ibcon#about to read 6, iclass 37, count 2 2006.225.08:07:28.35#ibcon#read 6, iclass 37, count 2 2006.225.08:07:28.35#ibcon#end of sib2, iclass 37, count 2 2006.225.08:07:28.35#ibcon#*mode == 0, iclass 37, count 2 2006.225.08:07:28.35#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.225.08:07:28.35#ibcon#[25=AT02-07\r\n] 2006.225.08:07:28.35#ibcon#*before write, iclass 37, count 2 2006.225.08:07:28.35#ibcon#enter sib2, iclass 37, count 2 2006.225.08:07:28.35#ibcon#flushed, iclass 37, count 2 2006.225.08:07:28.35#ibcon#about to write, iclass 37, count 2 2006.225.08:07:28.35#ibcon#wrote, iclass 37, count 2 2006.225.08:07:28.35#ibcon#about to read 3, iclass 37, count 2 2006.225.08:07:28.38#ibcon#read 3, iclass 37, count 2 2006.225.08:07:28.38#ibcon#about to read 4, iclass 37, count 2 2006.225.08:07:28.38#ibcon#read 4, iclass 37, count 2 2006.225.08:07:28.38#ibcon#about to read 5, iclass 37, count 2 2006.225.08:07:28.38#ibcon#read 5, iclass 37, count 2 2006.225.08:07:28.38#ibcon#about to read 6, iclass 37, count 2 2006.225.08:07:28.38#ibcon#read 6, iclass 37, count 2 2006.225.08:07:28.38#ibcon#end of sib2, iclass 37, count 2 2006.225.08:07:28.38#ibcon#*after write, iclass 37, count 2 2006.225.08:07:28.38#ibcon#*before return 0, iclass 37, count 2 2006.225.08:07:28.38#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:07:28.38#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:07:28.38#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.225.08:07:28.38#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:28.38#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:07:28.51#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:07:28.51#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:07:28.51#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:07:28.51#ibcon#first serial, iclass 37, count 0 2006.225.08:07:28.51#ibcon#enter sib2, iclass 37, count 0 2006.225.08:07:28.51#ibcon#flushed, iclass 37, count 0 2006.225.08:07:28.51#ibcon#about to write, iclass 37, count 0 2006.225.08:07:28.51#ibcon#wrote, iclass 37, count 0 2006.225.08:07:28.51#ibcon#about to read 3, iclass 37, count 0 2006.225.08:07:28.52#ibcon#read 3, iclass 37, count 0 2006.225.08:07:28.52#ibcon#about to read 4, iclass 37, count 0 2006.225.08:07:28.52#ibcon#read 4, iclass 37, count 0 2006.225.08:07:28.52#ibcon#about to read 5, iclass 37, count 0 2006.225.08:07:28.52#ibcon#read 5, iclass 37, count 0 2006.225.08:07:28.52#ibcon#about to read 6, iclass 37, count 0 2006.225.08:07:28.52#ibcon#read 6, iclass 37, count 0 2006.225.08:07:28.52#ibcon#end of sib2, iclass 37, count 0 2006.225.08:07:28.52#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:07:28.52#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:07:28.52#ibcon#[25=USB\r\n] 2006.225.08:07:28.52#ibcon#*before write, iclass 37, count 0 2006.225.08:07:28.52#ibcon#enter sib2, iclass 37, count 0 2006.225.08:07:28.52#ibcon#flushed, iclass 37, count 0 2006.225.08:07:28.52#ibcon#about to write, iclass 37, count 0 2006.225.08:07:28.52#ibcon#wrote, iclass 37, count 0 2006.225.08:07:28.52#ibcon#about to read 3, iclass 37, count 0 2006.225.08:07:28.55#ibcon#read 3, iclass 37, count 0 2006.225.08:07:28.55#ibcon#about to read 4, iclass 37, count 0 2006.225.08:07:28.55#ibcon#read 4, iclass 37, count 0 2006.225.08:07:28.55#ibcon#about to read 5, iclass 37, count 0 2006.225.08:07:28.55#ibcon#read 5, iclass 37, count 0 2006.225.08:07:28.55#ibcon#about to read 6, iclass 37, count 0 2006.225.08:07:28.55#ibcon#read 6, iclass 37, count 0 2006.225.08:07:28.55#ibcon#end of sib2, iclass 37, count 0 2006.225.08:07:28.55#ibcon#*after write, iclass 37, count 0 2006.225.08:07:28.55#ibcon#*before return 0, iclass 37, count 0 2006.225.08:07:28.55#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:07:28.55#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:07:28.55#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:07:28.55#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:07:28.55$vc4f8/valo=3,672.99 2006.225.08:07:28.55#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.08:07:28.55#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.08:07:28.55#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:28.55#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:07:28.55#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:07:28.55#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:07:28.55#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:07:28.55#ibcon#first serial, iclass 39, count 0 2006.225.08:07:28.55#ibcon#enter sib2, iclass 39, count 0 2006.225.08:07:28.55#ibcon#flushed, iclass 39, count 0 2006.225.08:07:28.55#ibcon#about to write, iclass 39, count 0 2006.225.08:07:28.55#ibcon#wrote, iclass 39, count 0 2006.225.08:07:28.55#ibcon#about to read 3, iclass 39, count 0 2006.225.08:07:28.58#ibcon#read 3, iclass 39, count 0 2006.225.08:07:28.58#ibcon#about to read 4, iclass 39, count 0 2006.225.08:07:28.58#ibcon#read 4, iclass 39, count 0 2006.225.08:07:28.58#ibcon#about to read 5, iclass 39, count 0 2006.225.08:07:28.58#ibcon#read 5, iclass 39, count 0 2006.225.08:07:28.58#ibcon#about to read 6, iclass 39, count 0 2006.225.08:07:28.58#ibcon#read 6, iclass 39, count 0 2006.225.08:07:28.58#ibcon#end of sib2, iclass 39, count 0 2006.225.08:07:28.58#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:07:28.58#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:07:28.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:07:28.58#ibcon#*before write, iclass 39, count 0 2006.225.08:07:28.58#ibcon#enter sib2, iclass 39, count 0 2006.225.08:07:28.58#ibcon#flushed, iclass 39, count 0 2006.225.08:07:28.58#ibcon#about to write, iclass 39, count 0 2006.225.08:07:28.58#ibcon#wrote, iclass 39, count 0 2006.225.08:07:28.58#ibcon#about to read 3, iclass 39, count 0 2006.225.08:07:28.62#ibcon#read 3, iclass 39, count 0 2006.225.08:07:28.62#ibcon#about to read 4, iclass 39, count 0 2006.225.08:07:28.62#ibcon#read 4, iclass 39, count 0 2006.225.08:07:28.62#ibcon#about to read 5, iclass 39, count 0 2006.225.08:07:28.62#ibcon#read 5, iclass 39, count 0 2006.225.08:07:28.62#ibcon#about to read 6, iclass 39, count 0 2006.225.08:07:28.62#ibcon#read 6, iclass 39, count 0 2006.225.08:07:28.62#ibcon#end of sib2, iclass 39, count 0 2006.225.08:07:28.62#ibcon#*after write, iclass 39, count 0 2006.225.08:07:28.62#ibcon#*before return 0, iclass 39, count 0 2006.225.08:07:28.62#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:07:28.62#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:07:28.62#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:07:28.62#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:07:28.62$vc4f8/va=3,6 2006.225.08:07:28.62#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.08:07:28.62#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.08:07:28.62#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:28.62#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:07:28.68#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:07:28.68#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:07:28.68#ibcon#enter wrdev, iclass 3, count 2 2006.225.08:07:28.68#ibcon#first serial, iclass 3, count 2 2006.225.08:07:28.68#ibcon#enter sib2, iclass 3, count 2 2006.225.08:07:28.68#ibcon#flushed, iclass 3, count 2 2006.225.08:07:28.68#ibcon#about to write, iclass 3, count 2 2006.225.08:07:28.68#ibcon#wrote, iclass 3, count 2 2006.225.08:07:28.68#ibcon#about to read 3, iclass 3, count 2 2006.225.08:07:28.69#ibcon#read 3, iclass 3, count 2 2006.225.08:07:28.69#ibcon#about to read 4, iclass 3, count 2 2006.225.08:07:28.69#ibcon#read 4, iclass 3, count 2 2006.225.08:07:28.69#ibcon#about to read 5, iclass 3, count 2 2006.225.08:07:28.69#ibcon#read 5, iclass 3, count 2 2006.225.08:07:28.69#ibcon#about to read 6, iclass 3, count 2 2006.225.08:07:28.69#ibcon#read 6, iclass 3, count 2 2006.225.08:07:28.69#ibcon#end of sib2, iclass 3, count 2 2006.225.08:07:28.69#ibcon#*mode == 0, iclass 3, count 2 2006.225.08:07:28.69#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.08:07:28.69#ibcon#[25=AT03-06\r\n] 2006.225.08:07:28.69#ibcon#*before write, iclass 3, count 2 2006.225.08:07:28.69#ibcon#enter sib2, iclass 3, count 2 2006.225.08:07:28.69#ibcon#flushed, iclass 3, count 2 2006.225.08:07:28.69#ibcon#about to write, iclass 3, count 2 2006.225.08:07:28.69#ibcon#wrote, iclass 3, count 2 2006.225.08:07:28.69#ibcon#about to read 3, iclass 3, count 2 2006.225.08:07:28.72#ibcon#read 3, iclass 3, count 2 2006.225.08:07:28.72#ibcon#about to read 4, iclass 3, count 2 2006.225.08:07:28.72#ibcon#read 4, iclass 3, count 2 2006.225.08:07:28.72#ibcon#about to read 5, iclass 3, count 2 2006.225.08:07:28.72#ibcon#read 5, iclass 3, count 2 2006.225.08:07:28.72#ibcon#about to read 6, iclass 3, count 2 2006.225.08:07:28.72#ibcon#read 6, iclass 3, count 2 2006.225.08:07:28.72#ibcon#end of sib2, iclass 3, count 2 2006.225.08:07:28.72#ibcon#*after write, iclass 3, count 2 2006.225.08:07:28.72#ibcon#*before return 0, iclass 3, count 2 2006.225.08:07:28.72#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:07:28.72#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:07:28.72#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.08:07:28.72#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:28.72#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:07:28.76#abcon#<5=/05 2.8 5.2 28.15 701003.3\r\n> 2006.225.08:07:28.78#abcon#{5=INTERFACE CLEAR} 2006.225.08:07:28.84#abcon#[5=S1D000X0/0*\r\n] 2006.225.08:07:28.84#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:07:28.84#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:07:28.84#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:07:28.84#ibcon#first serial, iclass 3, count 0 2006.225.08:07:28.84#ibcon#enter sib2, iclass 3, count 0 2006.225.08:07:28.84#ibcon#flushed, iclass 3, count 0 2006.225.08:07:28.84#ibcon#about to write, iclass 3, count 0 2006.225.08:07:28.84#ibcon#wrote, iclass 3, count 0 2006.225.08:07:28.84#ibcon#about to read 3, iclass 3, count 0 2006.225.08:07:28.86#ibcon#read 3, iclass 3, count 0 2006.225.08:07:28.86#ibcon#about to read 4, iclass 3, count 0 2006.225.08:07:28.86#ibcon#read 4, iclass 3, count 0 2006.225.08:07:28.86#ibcon#about to read 5, iclass 3, count 0 2006.225.08:07:28.86#ibcon#read 5, iclass 3, count 0 2006.225.08:07:28.86#ibcon#about to read 6, iclass 3, count 0 2006.225.08:07:28.86#ibcon#read 6, iclass 3, count 0 2006.225.08:07:28.86#ibcon#end of sib2, iclass 3, count 0 2006.225.08:07:28.86#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:07:28.86#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:07:28.86#ibcon#[25=USB\r\n] 2006.225.08:07:28.86#ibcon#*before write, iclass 3, count 0 2006.225.08:07:28.86#ibcon#enter sib2, iclass 3, count 0 2006.225.08:07:28.86#ibcon#flushed, iclass 3, count 0 2006.225.08:07:28.86#ibcon#about to write, iclass 3, count 0 2006.225.08:07:28.86#ibcon#wrote, iclass 3, count 0 2006.225.08:07:28.86#ibcon#about to read 3, iclass 3, count 0 2006.225.08:07:28.89#ibcon#read 3, iclass 3, count 0 2006.225.08:07:28.89#ibcon#about to read 4, iclass 3, count 0 2006.225.08:07:28.89#ibcon#read 4, iclass 3, count 0 2006.225.08:07:28.89#ibcon#about to read 5, iclass 3, count 0 2006.225.08:07:28.89#ibcon#read 5, iclass 3, count 0 2006.225.08:07:28.89#ibcon#about to read 6, iclass 3, count 0 2006.225.08:07:28.89#ibcon#read 6, iclass 3, count 0 2006.225.08:07:28.89#ibcon#end of sib2, iclass 3, count 0 2006.225.08:07:28.89#ibcon#*after write, iclass 3, count 0 2006.225.08:07:28.89#ibcon#*before return 0, iclass 3, count 0 2006.225.08:07:28.89#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:07:28.89#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:07:28.89#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:07:28.89#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:07:28.89$vc4f8/valo=4,832.99 2006.225.08:07:28.89#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.08:07:28.89#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.08:07:28.89#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:28.89#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:07:28.89#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:07:28.89#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:07:28.89#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:07:28.89#ibcon#first serial, iclass 11, count 0 2006.225.08:07:28.89#ibcon#enter sib2, iclass 11, count 0 2006.225.08:07:28.89#ibcon#flushed, iclass 11, count 0 2006.225.08:07:28.89#ibcon#about to write, iclass 11, count 0 2006.225.08:07:28.89#ibcon#wrote, iclass 11, count 0 2006.225.08:07:28.89#ibcon#about to read 3, iclass 11, count 0 2006.225.08:07:28.91#ibcon#read 3, iclass 11, count 0 2006.225.08:07:28.91#ibcon#about to read 4, iclass 11, count 0 2006.225.08:07:28.91#ibcon#read 4, iclass 11, count 0 2006.225.08:07:28.91#ibcon#about to read 5, iclass 11, count 0 2006.225.08:07:28.91#ibcon#read 5, iclass 11, count 0 2006.225.08:07:28.91#ibcon#about to read 6, iclass 11, count 0 2006.225.08:07:28.91#ibcon#read 6, iclass 11, count 0 2006.225.08:07:28.91#ibcon#end of sib2, iclass 11, count 0 2006.225.08:07:28.91#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:07:28.91#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:07:28.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:07:28.91#ibcon#*before write, iclass 11, count 0 2006.225.08:07:28.91#ibcon#enter sib2, iclass 11, count 0 2006.225.08:07:28.91#ibcon#flushed, iclass 11, count 0 2006.225.08:07:28.91#ibcon#about to write, iclass 11, count 0 2006.225.08:07:28.91#ibcon#wrote, iclass 11, count 0 2006.225.08:07:28.91#ibcon#about to read 3, iclass 11, count 0 2006.225.08:07:28.95#ibcon#read 3, iclass 11, count 0 2006.225.08:07:28.95#ibcon#about to read 4, iclass 11, count 0 2006.225.08:07:28.95#ibcon#read 4, iclass 11, count 0 2006.225.08:07:28.95#ibcon#about to read 5, iclass 11, count 0 2006.225.08:07:28.95#ibcon#read 5, iclass 11, count 0 2006.225.08:07:28.95#ibcon#about to read 6, iclass 11, count 0 2006.225.08:07:28.95#ibcon#read 6, iclass 11, count 0 2006.225.08:07:28.95#ibcon#end of sib2, iclass 11, count 0 2006.225.08:07:28.95#ibcon#*after write, iclass 11, count 0 2006.225.08:07:28.95#ibcon#*before return 0, iclass 11, count 0 2006.225.08:07:28.95#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:07:28.95#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:07:28.95#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:07:28.95#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:07:28.95$vc4f8/va=4,7 2006.225.08:07:28.95#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.08:07:28.95#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.08:07:28.95#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:28.95#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:07:29.01#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:07:29.01#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:07:29.01#ibcon#enter wrdev, iclass 13, count 2 2006.225.08:07:29.01#ibcon#first serial, iclass 13, count 2 2006.225.08:07:29.01#ibcon#enter sib2, iclass 13, count 2 2006.225.08:07:29.01#ibcon#flushed, iclass 13, count 2 2006.225.08:07:29.01#ibcon#about to write, iclass 13, count 2 2006.225.08:07:29.01#ibcon#wrote, iclass 13, count 2 2006.225.08:07:29.01#ibcon#about to read 3, iclass 13, count 2 2006.225.08:07:29.03#ibcon#read 3, iclass 13, count 2 2006.225.08:07:29.03#ibcon#about to read 4, iclass 13, count 2 2006.225.08:07:29.03#ibcon#read 4, iclass 13, count 2 2006.225.08:07:29.03#ibcon#about to read 5, iclass 13, count 2 2006.225.08:07:29.03#ibcon#read 5, iclass 13, count 2 2006.225.08:07:29.03#ibcon#about to read 6, iclass 13, count 2 2006.225.08:07:29.03#ibcon#read 6, iclass 13, count 2 2006.225.08:07:29.03#ibcon#end of sib2, iclass 13, count 2 2006.225.08:07:29.03#ibcon#*mode == 0, iclass 13, count 2 2006.225.08:07:29.03#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.08:07:29.03#ibcon#[25=AT04-07\r\n] 2006.225.08:07:29.03#ibcon#*before write, iclass 13, count 2 2006.225.08:07:29.03#ibcon#enter sib2, iclass 13, count 2 2006.225.08:07:29.03#ibcon#flushed, iclass 13, count 2 2006.225.08:07:29.03#ibcon#about to write, iclass 13, count 2 2006.225.08:07:29.03#ibcon#wrote, iclass 13, count 2 2006.225.08:07:29.03#ibcon#about to read 3, iclass 13, count 2 2006.225.08:07:29.06#ibcon#read 3, iclass 13, count 2 2006.225.08:07:29.06#ibcon#about to read 4, iclass 13, count 2 2006.225.08:07:29.06#ibcon#read 4, iclass 13, count 2 2006.225.08:07:29.06#ibcon#about to read 5, iclass 13, count 2 2006.225.08:07:29.06#ibcon#read 5, iclass 13, count 2 2006.225.08:07:29.06#ibcon#about to read 6, iclass 13, count 2 2006.225.08:07:29.06#ibcon#read 6, iclass 13, count 2 2006.225.08:07:29.06#ibcon#end of sib2, iclass 13, count 2 2006.225.08:07:29.06#ibcon#*after write, iclass 13, count 2 2006.225.08:07:29.06#ibcon#*before return 0, iclass 13, count 2 2006.225.08:07:29.06#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:07:29.06#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:07:29.06#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.08:07:29.06#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:29.06#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:07:29.18#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:07:29.18#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:07:29.18#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:07:29.18#ibcon#first serial, iclass 13, count 0 2006.225.08:07:29.18#ibcon#enter sib2, iclass 13, count 0 2006.225.08:07:29.18#ibcon#flushed, iclass 13, count 0 2006.225.08:07:29.18#ibcon#about to write, iclass 13, count 0 2006.225.08:07:29.18#ibcon#wrote, iclass 13, count 0 2006.225.08:07:29.18#ibcon#about to read 3, iclass 13, count 0 2006.225.08:07:29.20#ibcon#read 3, iclass 13, count 0 2006.225.08:07:29.20#ibcon#about to read 4, iclass 13, count 0 2006.225.08:07:29.20#ibcon#read 4, iclass 13, count 0 2006.225.08:07:29.20#ibcon#about to read 5, iclass 13, count 0 2006.225.08:07:29.20#ibcon#read 5, iclass 13, count 0 2006.225.08:07:29.20#ibcon#about to read 6, iclass 13, count 0 2006.225.08:07:29.20#ibcon#read 6, iclass 13, count 0 2006.225.08:07:29.20#ibcon#end of sib2, iclass 13, count 0 2006.225.08:07:29.20#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:07:29.20#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:07:29.20#ibcon#[25=USB\r\n] 2006.225.08:07:29.20#ibcon#*before write, iclass 13, count 0 2006.225.08:07:29.20#ibcon#enter sib2, iclass 13, count 0 2006.225.08:07:29.20#ibcon#flushed, iclass 13, count 0 2006.225.08:07:29.20#ibcon#about to write, iclass 13, count 0 2006.225.08:07:29.20#ibcon#wrote, iclass 13, count 0 2006.225.08:07:29.20#ibcon#about to read 3, iclass 13, count 0 2006.225.08:07:29.23#ibcon#read 3, iclass 13, count 0 2006.225.08:07:29.23#ibcon#about to read 4, iclass 13, count 0 2006.225.08:07:29.23#ibcon#read 4, iclass 13, count 0 2006.225.08:07:29.23#ibcon#about to read 5, iclass 13, count 0 2006.225.08:07:29.23#ibcon#read 5, iclass 13, count 0 2006.225.08:07:29.23#ibcon#about to read 6, iclass 13, count 0 2006.225.08:07:29.23#ibcon#read 6, iclass 13, count 0 2006.225.08:07:29.23#ibcon#end of sib2, iclass 13, count 0 2006.225.08:07:29.23#ibcon#*after write, iclass 13, count 0 2006.225.08:07:29.23#ibcon#*before return 0, iclass 13, count 0 2006.225.08:07:29.23#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:07:29.23#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:07:29.23#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:07:29.23#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:07:29.23$vc4f8/valo=5,652.99 2006.225.08:07:29.23#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.08:07:29.23#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.08:07:29.23#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:29.23#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:07:29.23#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:07:29.23#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:07:29.23#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:07:29.23#ibcon#first serial, iclass 15, count 0 2006.225.08:07:29.23#ibcon#enter sib2, iclass 15, count 0 2006.225.08:07:29.23#ibcon#flushed, iclass 15, count 0 2006.225.08:07:29.23#ibcon#about to write, iclass 15, count 0 2006.225.08:07:29.23#ibcon#wrote, iclass 15, count 0 2006.225.08:07:29.23#ibcon#about to read 3, iclass 15, count 0 2006.225.08:07:29.25#ibcon#read 3, iclass 15, count 0 2006.225.08:07:29.25#ibcon#about to read 4, iclass 15, count 0 2006.225.08:07:29.25#ibcon#read 4, iclass 15, count 0 2006.225.08:07:29.25#ibcon#about to read 5, iclass 15, count 0 2006.225.08:07:29.25#ibcon#read 5, iclass 15, count 0 2006.225.08:07:29.25#ibcon#about to read 6, iclass 15, count 0 2006.225.08:07:29.25#ibcon#read 6, iclass 15, count 0 2006.225.08:07:29.25#ibcon#end of sib2, iclass 15, count 0 2006.225.08:07:29.25#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:07:29.25#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:07:29.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:07:29.25#ibcon#*before write, iclass 15, count 0 2006.225.08:07:29.25#ibcon#enter sib2, iclass 15, count 0 2006.225.08:07:29.25#ibcon#flushed, iclass 15, count 0 2006.225.08:07:29.25#ibcon#about to write, iclass 15, count 0 2006.225.08:07:29.25#ibcon#wrote, iclass 15, count 0 2006.225.08:07:29.25#ibcon#about to read 3, iclass 15, count 0 2006.225.08:07:29.29#ibcon#read 3, iclass 15, count 0 2006.225.08:07:29.29#ibcon#about to read 4, iclass 15, count 0 2006.225.08:07:29.29#ibcon#read 4, iclass 15, count 0 2006.225.08:07:29.29#ibcon#about to read 5, iclass 15, count 0 2006.225.08:07:29.29#ibcon#read 5, iclass 15, count 0 2006.225.08:07:29.29#ibcon#about to read 6, iclass 15, count 0 2006.225.08:07:29.29#ibcon#read 6, iclass 15, count 0 2006.225.08:07:29.29#ibcon#end of sib2, iclass 15, count 0 2006.225.08:07:29.29#ibcon#*after write, iclass 15, count 0 2006.225.08:07:29.29#ibcon#*before return 0, iclass 15, count 0 2006.225.08:07:29.29#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:07:29.29#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:07:29.29#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:07:29.29#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:07:29.29$vc4f8/va=5,7 2006.225.08:07:29.29#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.08:07:29.29#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.08:07:29.29#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:29.29#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:07:29.35#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:07:29.35#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:07:29.35#ibcon#enter wrdev, iclass 17, count 2 2006.225.08:07:29.35#ibcon#first serial, iclass 17, count 2 2006.225.08:07:29.35#ibcon#enter sib2, iclass 17, count 2 2006.225.08:07:29.35#ibcon#flushed, iclass 17, count 2 2006.225.08:07:29.35#ibcon#about to write, iclass 17, count 2 2006.225.08:07:29.35#ibcon#wrote, iclass 17, count 2 2006.225.08:07:29.35#ibcon#about to read 3, iclass 17, count 2 2006.225.08:07:29.37#ibcon#read 3, iclass 17, count 2 2006.225.08:07:29.37#ibcon#about to read 4, iclass 17, count 2 2006.225.08:07:29.37#ibcon#read 4, iclass 17, count 2 2006.225.08:07:29.37#ibcon#about to read 5, iclass 17, count 2 2006.225.08:07:29.37#ibcon#read 5, iclass 17, count 2 2006.225.08:07:29.37#ibcon#about to read 6, iclass 17, count 2 2006.225.08:07:29.37#ibcon#read 6, iclass 17, count 2 2006.225.08:07:29.37#ibcon#end of sib2, iclass 17, count 2 2006.225.08:07:29.37#ibcon#*mode == 0, iclass 17, count 2 2006.225.08:07:29.37#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.08:07:29.37#ibcon#[25=AT05-07\r\n] 2006.225.08:07:29.37#ibcon#*before write, iclass 17, count 2 2006.225.08:07:29.37#ibcon#enter sib2, iclass 17, count 2 2006.225.08:07:29.37#ibcon#flushed, iclass 17, count 2 2006.225.08:07:29.37#ibcon#about to write, iclass 17, count 2 2006.225.08:07:29.37#ibcon#wrote, iclass 17, count 2 2006.225.08:07:29.37#ibcon#about to read 3, iclass 17, count 2 2006.225.08:07:29.40#ibcon#read 3, iclass 17, count 2 2006.225.08:07:29.40#ibcon#about to read 4, iclass 17, count 2 2006.225.08:07:29.40#ibcon#read 4, iclass 17, count 2 2006.225.08:07:29.40#ibcon#about to read 5, iclass 17, count 2 2006.225.08:07:29.40#ibcon#read 5, iclass 17, count 2 2006.225.08:07:29.40#ibcon#about to read 6, iclass 17, count 2 2006.225.08:07:29.40#ibcon#read 6, iclass 17, count 2 2006.225.08:07:29.40#ibcon#end of sib2, iclass 17, count 2 2006.225.08:07:29.40#ibcon#*after write, iclass 17, count 2 2006.225.08:07:29.40#ibcon#*before return 0, iclass 17, count 2 2006.225.08:07:29.40#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:07:29.40#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:07:29.40#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.08:07:29.40#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:29.40#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:07:29.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:07:29.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:07:29.53#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:07:29.53#ibcon#first serial, iclass 17, count 0 2006.225.08:07:29.53#ibcon#enter sib2, iclass 17, count 0 2006.225.08:07:29.53#ibcon#flushed, iclass 17, count 0 2006.225.08:07:29.53#ibcon#about to write, iclass 17, count 0 2006.225.08:07:29.53#ibcon#wrote, iclass 17, count 0 2006.225.08:07:29.53#ibcon#about to read 3, iclass 17, count 0 2006.225.08:07:29.54#ibcon#read 3, iclass 17, count 0 2006.225.08:07:29.54#ibcon#about to read 4, iclass 17, count 0 2006.225.08:07:29.54#ibcon#read 4, iclass 17, count 0 2006.225.08:07:29.54#ibcon#about to read 5, iclass 17, count 0 2006.225.08:07:29.54#ibcon#read 5, iclass 17, count 0 2006.225.08:07:29.54#ibcon#about to read 6, iclass 17, count 0 2006.225.08:07:29.54#ibcon#read 6, iclass 17, count 0 2006.225.08:07:29.54#ibcon#end of sib2, iclass 17, count 0 2006.225.08:07:29.54#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:07:29.54#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:07:29.54#ibcon#[25=USB\r\n] 2006.225.08:07:29.54#ibcon#*before write, iclass 17, count 0 2006.225.08:07:29.54#ibcon#enter sib2, iclass 17, count 0 2006.225.08:07:29.54#ibcon#flushed, iclass 17, count 0 2006.225.08:07:29.54#ibcon#about to write, iclass 17, count 0 2006.225.08:07:29.54#ibcon#wrote, iclass 17, count 0 2006.225.08:07:29.54#ibcon#about to read 3, iclass 17, count 0 2006.225.08:07:29.57#ibcon#read 3, iclass 17, count 0 2006.225.08:07:29.57#ibcon#about to read 4, iclass 17, count 0 2006.225.08:07:29.57#ibcon#read 4, iclass 17, count 0 2006.225.08:07:29.57#ibcon#about to read 5, iclass 17, count 0 2006.225.08:07:29.57#ibcon#read 5, iclass 17, count 0 2006.225.08:07:29.57#ibcon#about to read 6, iclass 17, count 0 2006.225.08:07:29.57#ibcon#read 6, iclass 17, count 0 2006.225.08:07:29.57#ibcon#end of sib2, iclass 17, count 0 2006.225.08:07:29.57#ibcon#*after write, iclass 17, count 0 2006.225.08:07:29.57#ibcon#*before return 0, iclass 17, count 0 2006.225.08:07:29.57#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:07:29.57#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:07:29.57#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:07:29.57#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:07:29.57$vc4f8/valo=6,772.99 2006.225.08:07:29.57#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.08:07:29.57#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.08:07:29.57#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:29.57#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:07:29.57#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:07:29.57#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:07:29.57#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:07:29.57#ibcon#first serial, iclass 19, count 0 2006.225.08:07:29.57#ibcon#enter sib2, iclass 19, count 0 2006.225.08:07:29.57#ibcon#flushed, iclass 19, count 0 2006.225.08:07:29.57#ibcon#about to write, iclass 19, count 0 2006.225.08:07:29.57#ibcon#wrote, iclass 19, count 0 2006.225.08:07:29.57#ibcon#about to read 3, iclass 19, count 0 2006.225.08:07:29.59#ibcon#read 3, iclass 19, count 0 2006.225.08:07:29.59#ibcon#about to read 4, iclass 19, count 0 2006.225.08:07:29.59#ibcon#read 4, iclass 19, count 0 2006.225.08:07:29.59#ibcon#about to read 5, iclass 19, count 0 2006.225.08:07:29.59#ibcon#read 5, iclass 19, count 0 2006.225.08:07:29.59#ibcon#about to read 6, iclass 19, count 0 2006.225.08:07:29.59#ibcon#read 6, iclass 19, count 0 2006.225.08:07:29.59#ibcon#end of sib2, iclass 19, count 0 2006.225.08:07:29.59#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:07:29.59#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:07:29.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:07:29.59#ibcon#*before write, iclass 19, count 0 2006.225.08:07:29.59#ibcon#enter sib2, iclass 19, count 0 2006.225.08:07:29.59#ibcon#flushed, iclass 19, count 0 2006.225.08:07:29.59#ibcon#about to write, iclass 19, count 0 2006.225.08:07:29.59#ibcon#wrote, iclass 19, count 0 2006.225.08:07:29.59#ibcon#about to read 3, iclass 19, count 0 2006.225.08:07:29.63#ibcon#read 3, iclass 19, count 0 2006.225.08:07:29.63#ibcon#about to read 4, iclass 19, count 0 2006.225.08:07:29.63#ibcon#read 4, iclass 19, count 0 2006.225.08:07:29.63#ibcon#about to read 5, iclass 19, count 0 2006.225.08:07:29.63#ibcon#read 5, iclass 19, count 0 2006.225.08:07:29.63#ibcon#about to read 6, iclass 19, count 0 2006.225.08:07:29.63#ibcon#read 6, iclass 19, count 0 2006.225.08:07:29.63#ibcon#end of sib2, iclass 19, count 0 2006.225.08:07:29.63#ibcon#*after write, iclass 19, count 0 2006.225.08:07:29.63#ibcon#*before return 0, iclass 19, count 0 2006.225.08:07:29.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:07:29.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:07:29.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:07:29.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:07:29.63$vc4f8/va=6,6 2006.225.08:07:29.63#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.225.08:07:29.63#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.225.08:07:29.63#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:29.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:07:29.69#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:07:29.69#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:07:29.69#ibcon#enter wrdev, iclass 21, count 2 2006.225.08:07:29.69#ibcon#first serial, iclass 21, count 2 2006.225.08:07:29.69#ibcon#enter sib2, iclass 21, count 2 2006.225.08:07:29.69#ibcon#flushed, iclass 21, count 2 2006.225.08:07:29.69#ibcon#about to write, iclass 21, count 2 2006.225.08:07:29.69#ibcon#wrote, iclass 21, count 2 2006.225.08:07:29.69#ibcon#about to read 3, iclass 21, count 2 2006.225.08:07:29.71#ibcon#read 3, iclass 21, count 2 2006.225.08:07:29.71#ibcon#about to read 4, iclass 21, count 2 2006.225.08:07:29.71#ibcon#read 4, iclass 21, count 2 2006.225.08:07:29.71#ibcon#about to read 5, iclass 21, count 2 2006.225.08:07:29.71#ibcon#read 5, iclass 21, count 2 2006.225.08:07:29.71#ibcon#about to read 6, iclass 21, count 2 2006.225.08:07:29.71#ibcon#read 6, iclass 21, count 2 2006.225.08:07:29.71#ibcon#end of sib2, iclass 21, count 2 2006.225.08:07:29.71#ibcon#*mode == 0, iclass 21, count 2 2006.225.08:07:29.71#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.225.08:07:29.71#ibcon#[25=AT06-06\r\n] 2006.225.08:07:29.71#ibcon#*before write, iclass 21, count 2 2006.225.08:07:29.71#ibcon#enter sib2, iclass 21, count 2 2006.225.08:07:29.71#ibcon#flushed, iclass 21, count 2 2006.225.08:07:29.71#ibcon#about to write, iclass 21, count 2 2006.225.08:07:29.71#ibcon#wrote, iclass 21, count 2 2006.225.08:07:29.71#ibcon#about to read 3, iclass 21, count 2 2006.225.08:07:29.74#ibcon#read 3, iclass 21, count 2 2006.225.08:07:29.74#ibcon#about to read 4, iclass 21, count 2 2006.225.08:07:29.74#ibcon#read 4, iclass 21, count 2 2006.225.08:07:29.74#ibcon#about to read 5, iclass 21, count 2 2006.225.08:07:29.74#ibcon#read 5, iclass 21, count 2 2006.225.08:07:29.74#ibcon#about to read 6, iclass 21, count 2 2006.225.08:07:29.74#ibcon#read 6, iclass 21, count 2 2006.225.08:07:29.74#ibcon#end of sib2, iclass 21, count 2 2006.225.08:07:29.74#ibcon#*after write, iclass 21, count 2 2006.225.08:07:29.74#ibcon#*before return 0, iclass 21, count 2 2006.225.08:07:29.74#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:07:29.74#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:07:29.74#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.225.08:07:29.74#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:29.74#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:07:29.86#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:07:29.86#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:07:29.86#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:07:29.86#ibcon#first serial, iclass 21, count 0 2006.225.08:07:29.86#ibcon#enter sib2, iclass 21, count 0 2006.225.08:07:29.86#ibcon#flushed, iclass 21, count 0 2006.225.08:07:29.86#ibcon#about to write, iclass 21, count 0 2006.225.08:07:29.86#ibcon#wrote, iclass 21, count 0 2006.225.08:07:29.86#ibcon#about to read 3, iclass 21, count 0 2006.225.08:07:29.88#ibcon#read 3, iclass 21, count 0 2006.225.08:07:29.88#ibcon#about to read 4, iclass 21, count 0 2006.225.08:07:29.88#ibcon#read 4, iclass 21, count 0 2006.225.08:07:29.88#ibcon#about to read 5, iclass 21, count 0 2006.225.08:07:29.88#ibcon#read 5, iclass 21, count 0 2006.225.08:07:29.88#ibcon#about to read 6, iclass 21, count 0 2006.225.08:07:29.88#ibcon#read 6, iclass 21, count 0 2006.225.08:07:29.88#ibcon#end of sib2, iclass 21, count 0 2006.225.08:07:29.88#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:07:29.88#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:07:29.88#ibcon#[25=USB\r\n] 2006.225.08:07:29.88#ibcon#*before write, iclass 21, count 0 2006.225.08:07:29.88#ibcon#enter sib2, iclass 21, count 0 2006.225.08:07:29.88#ibcon#flushed, iclass 21, count 0 2006.225.08:07:29.88#ibcon#about to write, iclass 21, count 0 2006.225.08:07:29.88#ibcon#wrote, iclass 21, count 0 2006.225.08:07:29.88#ibcon#about to read 3, iclass 21, count 0 2006.225.08:07:29.91#ibcon#read 3, iclass 21, count 0 2006.225.08:07:29.91#ibcon#about to read 4, iclass 21, count 0 2006.225.08:07:29.91#ibcon#read 4, iclass 21, count 0 2006.225.08:07:29.91#ibcon#about to read 5, iclass 21, count 0 2006.225.08:07:29.91#ibcon#read 5, iclass 21, count 0 2006.225.08:07:29.91#ibcon#about to read 6, iclass 21, count 0 2006.225.08:07:29.91#ibcon#read 6, iclass 21, count 0 2006.225.08:07:29.91#ibcon#end of sib2, iclass 21, count 0 2006.225.08:07:29.91#ibcon#*after write, iclass 21, count 0 2006.225.08:07:29.91#ibcon#*before return 0, iclass 21, count 0 2006.225.08:07:29.91#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:07:29.91#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:07:29.91#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:07:29.91#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:07:29.91$vc4f8/valo=7,832.99 2006.225.08:07:29.91#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.225.08:07:29.91#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.225.08:07:29.91#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:29.91#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:07:29.91#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:07:29.91#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:07:29.91#ibcon#enter wrdev, iclass 23, count 0 2006.225.08:07:29.91#ibcon#first serial, iclass 23, count 0 2006.225.08:07:29.91#ibcon#enter sib2, iclass 23, count 0 2006.225.08:07:29.91#ibcon#flushed, iclass 23, count 0 2006.225.08:07:29.91#ibcon#about to write, iclass 23, count 0 2006.225.08:07:29.91#ibcon#wrote, iclass 23, count 0 2006.225.08:07:29.91#ibcon#about to read 3, iclass 23, count 0 2006.225.08:07:29.93#ibcon#read 3, iclass 23, count 0 2006.225.08:07:29.93#ibcon#about to read 4, iclass 23, count 0 2006.225.08:07:29.93#ibcon#read 4, iclass 23, count 0 2006.225.08:07:29.93#ibcon#about to read 5, iclass 23, count 0 2006.225.08:07:29.93#ibcon#read 5, iclass 23, count 0 2006.225.08:07:29.93#ibcon#about to read 6, iclass 23, count 0 2006.225.08:07:29.93#ibcon#read 6, iclass 23, count 0 2006.225.08:07:29.93#ibcon#end of sib2, iclass 23, count 0 2006.225.08:07:29.93#ibcon#*mode == 0, iclass 23, count 0 2006.225.08:07:29.93#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.08:07:29.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:07:29.93#ibcon#*before write, iclass 23, count 0 2006.225.08:07:29.93#ibcon#enter sib2, iclass 23, count 0 2006.225.08:07:29.93#ibcon#flushed, iclass 23, count 0 2006.225.08:07:29.93#ibcon#about to write, iclass 23, count 0 2006.225.08:07:29.93#ibcon#wrote, iclass 23, count 0 2006.225.08:07:29.93#ibcon#about to read 3, iclass 23, count 0 2006.225.08:07:29.97#ibcon#read 3, iclass 23, count 0 2006.225.08:07:29.97#ibcon#about to read 4, iclass 23, count 0 2006.225.08:07:29.97#ibcon#read 4, iclass 23, count 0 2006.225.08:07:29.97#ibcon#about to read 5, iclass 23, count 0 2006.225.08:07:29.97#ibcon#read 5, iclass 23, count 0 2006.225.08:07:29.97#ibcon#about to read 6, iclass 23, count 0 2006.225.08:07:29.97#ibcon#read 6, iclass 23, count 0 2006.225.08:07:29.97#ibcon#end of sib2, iclass 23, count 0 2006.225.08:07:29.97#ibcon#*after write, iclass 23, count 0 2006.225.08:07:29.97#ibcon#*before return 0, iclass 23, count 0 2006.225.08:07:29.97#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:07:29.97#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:07:29.97#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.08:07:29.97#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.08:07:29.97$vc4f8/va=7,6 2006.225.08:07:29.97#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.225.08:07:29.97#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.225.08:07:29.97#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:29.97#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:07:30.03#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:07:30.03#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:07:30.03#ibcon#enter wrdev, iclass 25, count 2 2006.225.08:07:30.03#ibcon#first serial, iclass 25, count 2 2006.225.08:07:30.03#ibcon#enter sib2, iclass 25, count 2 2006.225.08:07:30.03#ibcon#flushed, iclass 25, count 2 2006.225.08:07:30.03#ibcon#about to write, iclass 25, count 2 2006.225.08:07:30.03#ibcon#wrote, iclass 25, count 2 2006.225.08:07:30.03#ibcon#about to read 3, iclass 25, count 2 2006.225.08:07:30.05#ibcon#read 3, iclass 25, count 2 2006.225.08:07:30.05#ibcon#about to read 4, iclass 25, count 2 2006.225.08:07:30.05#ibcon#read 4, iclass 25, count 2 2006.225.08:07:30.05#ibcon#about to read 5, iclass 25, count 2 2006.225.08:07:30.05#ibcon#read 5, iclass 25, count 2 2006.225.08:07:30.05#ibcon#about to read 6, iclass 25, count 2 2006.225.08:07:30.05#ibcon#read 6, iclass 25, count 2 2006.225.08:07:30.05#ibcon#end of sib2, iclass 25, count 2 2006.225.08:07:30.05#ibcon#*mode == 0, iclass 25, count 2 2006.225.08:07:30.05#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.225.08:07:30.05#ibcon#[25=AT07-06\r\n] 2006.225.08:07:30.05#ibcon#*before write, iclass 25, count 2 2006.225.08:07:30.05#ibcon#enter sib2, iclass 25, count 2 2006.225.08:07:30.05#ibcon#flushed, iclass 25, count 2 2006.225.08:07:30.05#ibcon#about to write, iclass 25, count 2 2006.225.08:07:30.05#ibcon#wrote, iclass 25, count 2 2006.225.08:07:30.05#ibcon#about to read 3, iclass 25, count 2 2006.225.08:07:30.08#ibcon#read 3, iclass 25, count 2 2006.225.08:07:30.08#ibcon#about to read 4, iclass 25, count 2 2006.225.08:07:30.08#ibcon#read 4, iclass 25, count 2 2006.225.08:07:30.08#ibcon#about to read 5, iclass 25, count 2 2006.225.08:07:30.08#ibcon#read 5, iclass 25, count 2 2006.225.08:07:30.08#ibcon#about to read 6, iclass 25, count 2 2006.225.08:07:30.08#ibcon#read 6, iclass 25, count 2 2006.225.08:07:30.08#ibcon#end of sib2, iclass 25, count 2 2006.225.08:07:30.08#ibcon#*after write, iclass 25, count 2 2006.225.08:07:30.08#ibcon#*before return 0, iclass 25, count 2 2006.225.08:07:30.08#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:07:30.08#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:07:30.08#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.225.08:07:30.08#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:30.08#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:07:30.20#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:07:30.20#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:07:30.20#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:07:30.20#ibcon#first serial, iclass 25, count 0 2006.225.08:07:30.20#ibcon#enter sib2, iclass 25, count 0 2006.225.08:07:30.20#ibcon#flushed, iclass 25, count 0 2006.225.08:07:30.20#ibcon#about to write, iclass 25, count 0 2006.225.08:07:30.20#ibcon#wrote, iclass 25, count 0 2006.225.08:07:30.20#ibcon#about to read 3, iclass 25, count 0 2006.225.08:07:30.22#ibcon#read 3, iclass 25, count 0 2006.225.08:07:30.22#ibcon#about to read 4, iclass 25, count 0 2006.225.08:07:30.22#ibcon#read 4, iclass 25, count 0 2006.225.08:07:30.22#ibcon#about to read 5, iclass 25, count 0 2006.225.08:07:30.22#ibcon#read 5, iclass 25, count 0 2006.225.08:07:30.22#ibcon#about to read 6, iclass 25, count 0 2006.225.08:07:30.22#ibcon#read 6, iclass 25, count 0 2006.225.08:07:30.22#ibcon#end of sib2, iclass 25, count 0 2006.225.08:07:30.22#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:07:30.22#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:07:30.22#ibcon#[25=USB\r\n] 2006.225.08:07:30.22#ibcon#*before write, iclass 25, count 0 2006.225.08:07:30.22#ibcon#enter sib2, iclass 25, count 0 2006.225.08:07:30.22#ibcon#flushed, iclass 25, count 0 2006.225.08:07:30.22#ibcon#about to write, iclass 25, count 0 2006.225.08:07:30.22#ibcon#wrote, iclass 25, count 0 2006.225.08:07:30.22#ibcon#about to read 3, iclass 25, count 0 2006.225.08:07:30.25#ibcon#read 3, iclass 25, count 0 2006.225.08:07:30.25#ibcon#about to read 4, iclass 25, count 0 2006.225.08:07:30.25#ibcon#read 4, iclass 25, count 0 2006.225.08:07:30.25#ibcon#about to read 5, iclass 25, count 0 2006.225.08:07:30.25#ibcon#read 5, iclass 25, count 0 2006.225.08:07:30.25#ibcon#about to read 6, iclass 25, count 0 2006.225.08:07:30.25#ibcon#read 6, iclass 25, count 0 2006.225.08:07:30.25#ibcon#end of sib2, iclass 25, count 0 2006.225.08:07:30.25#ibcon#*after write, iclass 25, count 0 2006.225.08:07:30.25#ibcon#*before return 0, iclass 25, count 0 2006.225.08:07:30.25#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:07:30.25#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:07:30.25#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:07:30.25#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:07:30.25$vc4f8/valo=8,852.99 2006.225.08:07:30.25#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.08:07:30.25#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.08:07:30.25#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:30.25#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:07:30.25#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:07:30.25#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:07:30.25#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:07:30.25#ibcon#first serial, iclass 27, count 0 2006.225.08:07:30.25#ibcon#enter sib2, iclass 27, count 0 2006.225.08:07:30.25#ibcon#flushed, iclass 27, count 0 2006.225.08:07:30.25#ibcon#about to write, iclass 27, count 0 2006.225.08:07:30.25#ibcon#wrote, iclass 27, count 0 2006.225.08:07:30.25#ibcon#about to read 3, iclass 27, count 0 2006.225.08:07:30.27#ibcon#read 3, iclass 27, count 0 2006.225.08:07:30.27#ibcon#about to read 4, iclass 27, count 0 2006.225.08:07:30.27#ibcon#read 4, iclass 27, count 0 2006.225.08:07:30.27#ibcon#about to read 5, iclass 27, count 0 2006.225.08:07:30.27#ibcon#read 5, iclass 27, count 0 2006.225.08:07:30.27#ibcon#about to read 6, iclass 27, count 0 2006.225.08:07:30.27#ibcon#read 6, iclass 27, count 0 2006.225.08:07:30.27#ibcon#end of sib2, iclass 27, count 0 2006.225.08:07:30.27#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:07:30.27#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:07:30.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:07:30.27#ibcon#*before write, iclass 27, count 0 2006.225.08:07:30.27#ibcon#enter sib2, iclass 27, count 0 2006.225.08:07:30.27#ibcon#flushed, iclass 27, count 0 2006.225.08:07:30.27#ibcon#about to write, iclass 27, count 0 2006.225.08:07:30.27#ibcon#wrote, iclass 27, count 0 2006.225.08:07:30.27#ibcon#about to read 3, iclass 27, count 0 2006.225.08:07:30.31#ibcon#read 3, iclass 27, count 0 2006.225.08:07:30.31#ibcon#about to read 4, iclass 27, count 0 2006.225.08:07:30.31#ibcon#read 4, iclass 27, count 0 2006.225.08:07:30.31#ibcon#about to read 5, iclass 27, count 0 2006.225.08:07:30.31#ibcon#read 5, iclass 27, count 0 2006.225.08:07:30.31#ibcon#about to read 6, iclass 27, count 0 2006.225.08:07:30.31#ibcon#read 6, iclass 27, count 0 2006.225.08:07:30.31#ibcon#end of sib2, iclass 27, count 0 2006.225.08:07:30.31#ibcon#*after write, iclass 27, count 0 2006.225.08:07:30.31#ibcon#*before return 0, iclass 27, count 0 2006.225.08:07:30.31#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:07:30.31#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:07:30.31#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:07:30.31#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:07:30.31$vc4f8/va=8,7 2006.225.08:07:30.31#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.225.08:07:30.31#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.225.08:07:30.31#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:30.31#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:07:30.37#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:07:30.37#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:07:30.37#ibcon#enter wrdev, iclass 29, count 2 2006.225.08:07:30.37#ibcon#first serial, iclass 29, count 2 2006.225.08:07:30.37#ibcon#enter sib2, iclass 29, count 2 2006.225.08:07:30.37#ibcon#flushed, iclass 29, count 2 2006.225.08:07:30.37#ibcon#about to write, iclass 29, count 2 2006.225.08:07:30.37#ibcon#wrote, iclass 29, count 2 2006.225.08:07:30.37#ibcon#about to read 3, iclass 29, count 2 2006.225.08:07:30.40#ibcon#read 3, iclass 29, count 2 2006.225.08:07:30.40#ibcon#about to read 4, iclass 29, count 2 2006.225.08:07:30.40#ibcon#read 4, iclass 29, count 2 2006.225.08:07:30.40#ibcon#about to read 5, iclass 29, count 2 2006.225.08:07:30.40#ibcon#read 5, iclass 29, count 2 2006.225.08:07:30.40#ibcon#about to read 6, iclass 29, count 2 2006.225.08:07:30.40#ibcon#read 6, iclass 29, count 2 2006.225.08:07:30.40#ibcon#end of sib2, iclass 29, count 2 2006.225.08:07:30.40#ibcon#*mode == 0, iclass 29, count 2 2006.225.08:07:30.40#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.225.08:07:30.40#ibcon#[25=AT08-07\r\n] 2006.225.08:07:30.40#ibcon#*before write, iclass 29, count 2 2006.225.08:07:30.40#ibcon#enter sib2, iclass 29, count 2 2006.225.08:07:30.40#ibcon#flushed, iclass 29, count 2 2006.225.08:07:30.40#ibcon#about to write, iclass 29, count 2 2006.225.08:07:30.40#ibcon#wrote, iclass 29, count 2 2006.225.08:07:30.40#ibcon#about to read 3, iclass 29, count 2 2006.225.08:07:30.43#ibcon#read 3, iclass 29, count 2 2006.225.08:07:30.43#ibcon#about to read 4, iclass 29, count 2 2006.225.08:07:30.43#ibcon#read 4, iclass 29, count 2 2006.225.08:07:30.43#ibcon#about to read 5, iclass 29, count 2 2006.225.08:07:30.43#ibcon#read 5, iclass 29, count 2 2006.225.08:07:30.43#ibcon#about to read 6, iclass 29, count 2 2006.225.08:07:30.43#ibcon#read 6, iclass 29, count 2 2006.225.08:07:30.43#ibcon#end of sib2, iclass 29, count 2 2006.225.08:07:30.43#ibcon#*after write, iclass 29, count 2 2006.225.08:07:30.43#ibcon#*before return 0, iclass 29, count 2 2006.225.08:07:30.43#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:07:30.43#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:07:30.43#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.225.08:07:30.43#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:30.43#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:07:30.55#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:07:30.55#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:07:30.55#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:07:30.55#ibcon#first serial, iclass 29, count 0 2006.225.08:07:30.55#ibcon#enter sib2, iclass 29, count 0 2006.225.08:07:30.55#ibcon#flushed, iclass 29, count 0 2006.225.08:07:30.55#ibcon#about to write, iclass 29, count 0 2006.225.08:07:30.55#ibcon#wrote, iclass 29, count 0 2006.225.08:07:30.55#ibcon#about to read 3, iclass 29, count 0 2006.225.08:07:30.57#ibcon#read 3, iclass 29, count 0 2006.225.08:07:30.57#ibcon#about to read 4, iclass 29, count 0 2006.225.08:07:30.57#ibcon#read 4, iclass 29, count 0 2006.225.08:07:30.57#ibcon#about to read 5, iclass 29, count 0 2006.225.08:07:30.57#ibcon#read 5, iclass 29, count 0 2006.225.08:07:30.57#ibcon#about to read 6, iclass 29, count 0 2006.225.08:07:30.57#ibcon#read 6, iclass 29, count 0 2006.225.08:07:30.57#ibcon#end of sib2, iclass 29, count 0 2006.225.08:07:30.57#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:07:30.57#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:07:30.57#ibcon#[25=USB\r\n] 2006.225.08:07:30.57#ibcon#*before write, iclass 29, count 0 2006.225.08:07:30.57#ibcon#enter sib2, iclass 29, count 0 2006.225.08:07:30.57#ibcon#flushed, iclass 29, count 0 2006.225.08:07:30.57#ibcon#about to write, iclass 29, count 0 2006.225.08:07:30.57#ibcon#wrote, iclass 29, count 0 2006.225.08:07:30.57#ibcon#about to read 3, iclass 29, count 0 2006.225.08:07:30.60#ibcon#read 3, iclass 29, count 0 2006.225.08:07:30.60#ibcon#about to read 4, iclass 29, count 0 2006.225.08:07:30.60#ibcon#read 4, iclass 29, count 0 2006.225.08:07:30.60#ibcon#about to read 5, iclass 29, count 0 2006.225.08:07:30.60#ibcon#read 5, iclass 29, count 0 2006.225.08:07:30.60#ibcon#about to read 6, iclass 29, count 0 2006.225.08:07:30.60#ibcon#read 6, iclass 29, count 0 2006.225.08:07:30.60#ibcon#end of sib2, iclass 29, count 0 2006.225.08:07:30.60#ibcon#*after write, iclass 29, count 0 2006.225.08:07:30.60#ibcon#*before return 0, iclass 29, count 0 2006.225.08:07:30.60#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:07:30.60#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:07:30.60#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:07:30.60#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:07:30.60$vc4f8/vblo=1,632.99 2006.225.08:07:30.60#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.08:07:30.60#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.08:07:30.60#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:30.60#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:07:30.60#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:07:30.60#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:07:30.60#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:07:30.60#ibcon#first serial, iclass 31, count 0 2006.225.08:07:30.60#ibcon#enter sib2, iclass 31, count 0 2006.225.08:07:30.60#ibcon#flushed, iclass 31, count 0 2006.225.08:07:30.60#ibcon#about to write, iclass 31, count 0 2006.225.08:07:30.60#ibcon#wrote, iclass 31, count 0 2006.225.08:07:30.60#ibcon#about to read 3, iclass 31, count 0 2006.225.08:07:30.62#ibcon#read 3, iclass 31, count 0 2006.225.08:07:30.62#ibcon#about to read 4, iclass 31, count 0 2006.225.08:07:30.62#ibcon#read 4, iclass 31, count 0 2006.225.08:07:30.62#ibcon#about to read 5, iclass 31, count 0 2006.225.08:07:30.62#ibcon#read 5, iclass 31, count 0 2006.225.08:07:30.62#ibcon#about to read 6, iclass 31, count 0 2006.225.08:07:30.62#ibcon#read 6, iclass 31, count 0 2006.225.08:07:30.62#ibcon#end of sib2, iclass 31, count 0 2006.225.08:07:30.62#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:07:30.62#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:07:30.62#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:07:30.62#ibcon#*before write, iclass 31, count 0 2006.225.08:07:30.62#ibcon#enter sib2, iclass 31, count 0 2006.225.08:07:30.62#ibcon#flushed, iclass 31, count 0 2006.225.08:07:30.62#ibcon#about to write, iclass 31, count 0 2006.225.08:07:30.62#ibcon#wrote, iclass 31, count 0 2006.225.08:07:30.62#ibcon#about to read 3, iclass 31, count 0 2006.225.08:07:30.66#ibcon#read 3, iclass 31, count 0 2006.225.08:07:30.66#ibcon#about to read 4, iclass 31, count 0 2006.225.08:07:30.66#ibcon#read 4, iclass 31, count 0 2006.225.08:07:30.66#ibcon#about to read 5, iclass 31, count 0 2006.225.08:07:30.66#ibcon#read 5, iclass 31, count 0 2006.225.08:07:30.66#ibcon#about to read 6, iclass 31, count 0 2006.225.08:07:30.66#ibcon#read 6, iclass 31, count 0 2006.225.08:07:30.66#ibcon#end of sib2, iclass 31, count 0 2006.225.08:07:30.66#ibcon#*after write, iclass 31, count 0 2006.225.08:07:30.66#ibcon#*before return 0, iclass 31, count 0 2006.225.08:07:30.66#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:07:30.66#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:07:30.66#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:07:30.66#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:07:30.66$vc4f8/vb=1,4 2006.225.08:07:30.66#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.225.08:07:30.66#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.225.08:07:30.66#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:30.66#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:07:30.66#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:07:30.66#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:07:30.66#ibcon#enter wrdev, iclass 33, count 2 2006.225.08:07:30.66#ibcon#first serial, iclass 33, count 2 2006.225.08:07:30.66#ibcon#enter sib2, iclass 33, count 2 2006.225.08:07:30.66#ibcon#flushed, iclass 33, count 2 2006.225.08:07:30.66#ibcon#about to write, iclass 33, count 2 2006.225.08:07:30.66#ibcon#wrote, iclass 33, count 2 2006.225.08:07:30.66#ibcon#about to read 3, iclass 33, count 2 2006.225.08:07:30.68#ibcon#read 3, iclass 33, count 2 2006.225.08:07:30.68#ibcon#about to read 4, iclass 33, count 2 2006.225.08:07:30.68#ibcon#read 4, iclass 33, count 2 2006.225.08:07:30.68#ibcon#about to read 5, iclass 33, count 2 2006.225.08:07:30.68#ibcon#read 5, iclass 33, count 2 2006.225.08:07:30.68#ibcon#about to read 6, iclass 33, count 2 2006.225.08:07:30.68#ibcon#read 6, iclass 33, count 2 2006.225.08:07:30.68#ibcon#end of sib2, iclass 33, count 2 2006.225.08:07:30.68#ibcon#*mode == 0, iclass 33, count 2 2006.225.08:07:30.68#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.225.08:07:30.68#ibcon#[27=AT01-04\r\n] 2006.225.08:07:30.68#ibcon#*before write, iclass 33, count 2 2006.225.08:07:30.68#ibcon#enter sib2, iclass 33, count 2 2006.225.08:07:30.68#ibcon#flushed, iclass 33, count 2 2006.225.08:07:30.68#ibcon#about to write, iclass 33, count 2 2006.225.08:07:30.68#ibcon#wrote, iclass 33, count 2 2006.225.08:07:30.68#ibcon#about to read 3, iclass 33, count 2 2006.225.08:07:30.71#ibcon#read 3, iclass 33, count 2 2006.225.08:07:30.71#ibcon#about to read 4, iclass 33, count 2 2006.225.08:07:30.71#ibcon#read 4, iclass 33, count 2 2006.225.08:07:30.71#ibcon#about to read 5, iclass 33, count 2 2006.225.08:07:30.71#ibcon#read 5, iclass 33, count 2 2006.225.08:07:30.71#ibcon#about to read 6, iclass 33, count 2 2006.225.08:07:30.71#ibcon#read 6, iclass 33, count 2 2006.225.08:07:30.71#ibcon#end of sib2, iclass 33, count 2 2006.225.08:07:30.71#ibcon#*after write, iclass 33, count 2 2006.225.08:07:30.71#ibcon#*before return 0, iclass 33, count 2 2006.225.08:07:30.71#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:07:30.71#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:07:30.71#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.225.08:07:30.71#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:30.71#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:07:30.83#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:07:30.83#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:07:30.83#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:07:30.83#ibcon#first serial, iclass 33, count 0 2006.225.08:07:30.83#ibcon#enter sib2, iclass 33, count 0 2006.225.08:07:30.83#ibcon#flushed, iclass 33, count 0 2006.225.08:07:30.83#ibcon#about to write, iclass 33, count 0 2006.225.08:07:30.83#ibcon#wrote, iclass 33, count 0 2006.225.08:07:30.83#ibcon#about to read 3, iclass 33, count 0 2006.225.08:07:30.85#ibcon#read 3, iclass 33, count 0 2006.225.08:07:30.85#ibcon#about to read 4, iclass 33, count 0 2006.225.08:07:30.85#ibcon#read 4, iclass 33, count 0 2006.225.08:07:30.85#ibcon#about to read 5, iclass 33, count 0 2006.225.08:07:30.85#ibcon#read 5, iclass 33, count 0 2006.225.08:07:30.85#ibcon#about to read 6, iclass 33, count 0 2006.225.08:07:30.85#ibcon#read 6, iclass 33, count 0 2006.225.08:07:30.85#ibcon#end of sib2, iclass 33, count 0 2006.225.08:07:30.85#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:07:30.85#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:07:30.85#ibcon#[27=USB\r\n] 2006.225.08:07:30.85#ibcon#*before write, iclass 33, count 0 2006.225.08:07:30.85#ibcon#enter sib2, iclass 33, count 0 2006.225.08:07:30.85#ibcon#flushed, iclass 33, count 0 2006.225.08:07:30.85#ibcon#about to write, iclass 33, count 0 2006.225.08:07:30.85#ibcon#wrote, iclass 33, count 0 2006.225.08:07:30.85#ibcon#about to read 3, iclass 33, count 0 2006.225.08:07:30.88#ibcon#read 3, iclass 33, count 0 2006.225.08:07:30.88#ibcon#about to read 4, iclass 33, count 0 2006.225.08:07:30.88#ibcon#read 4, iclass 33, count 0 2006.225.08:07:30.88#ibcon#about to read 5, iclass 33, count 0 2006.225.08:07:30.88#ibcon#read 5, iclass 33, count 0 2006.225.08:07:30.88#ibcon#about to read 6, iclass 33, count 0 2006.225.08:07:30.88#ibcon#read 6, iclass 33, count 0 2006.225.08:07:30.88#ibcon#end of sib2, iclass 33, count 0 2006.225.08:07:30.88#ibcon#*after write, iclass 33, count 0 2006.225.08:07:30.88#ibcon#*before return 0, iclass 33, count 0 2006.225.08:07:30.88#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:07:30.88#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:07:30.88#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:07:30.88#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:07:30.88$vc4f8/vblo=2,640.99 2006.225.08:07:30.88#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.225.08:07:30.88#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.225.08:07:30.88#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:30.88#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:07:30.88#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:07:30.88#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:07:30.88#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:07:30.88#ibcon#first serial, iclass 35, count 0 2006.225.08:07:30.88#ibcon#enter sib2, iclass 35, count 0 2006.225.08:07:30.88#ibcon#flushed, iclass 35, count 0 2006.225.08:07:30.88#ibcon#about to write, iclass 35, count 0 2006.225.08:07:30.88#ibcon#wrote, iclass 35, count 0 2006.225.08:07:30.88#ibcon#about to read 3, iclass 35, count 0 2006.225.08:07:30.90#ibcon#read 3, iclass 35, count 0 2006.225.08:07:30.90#ibcon#about to read 4, iclass 35, count 0 2006.225.08:07:30.90#ibcon#read 4, iclass 35, count 0 2006.225.08:07:30.90#ibcon#about to read 5, iclass 35, count 0 2006.225.08:07:30.90#ibcon#read 5, iclass 35, count 0 2006.225.08:07:30.90#ibcon#about to read 6, iclass 35, count 0 2006.225.08:07:30.90#ibcon#read 6, iclass 35, count 0 2006.225.08:07:30.90#ibcon#end of sib2, iclass 35, count 0 2006.225.08:07:30.90#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:07:30.90#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:07:30.90#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:07:30.90#ibcon#*before write, iclass 35, count 0 2006.225.08:07:30.90#ibcon#enter sib2, iclass 35, count 0 2006.225.08:07:30.90#ibcon#flushed, iclass 35, count 0 2006.225.08:07:30.90#ibcon#about to write, iclass 35, count 0 2006.225.08:07:30.90#ibcon#wrote, iclass 35, count 0 2006.225.08:07:30.90#ibcon#about to read 3, iclass 35, count 0 2006.225.08:07:30.94#ibcon#read 3, iclass 35, count 0 2006.225.08:07:30.94#ibcon#about to read 4, iclass 35, count 0 2006.225.08:07:30.94#ibcon#read 4, iclass 35, count 0 2006.225.08:07:30.94#ibcon#about to read 5, iclass 35, count 0 2006.225.08:07:30.94#ibcon#read 5, iclass 35, count 0 2006.225.08:07:30.94#ibcon#about to read 6, iclass 35, count 0 2006.225.08:07:30.94#ibcon#read 6, iclass 35, count 0 2006.225.08:07:30.94#ibcon#end of sib2, iclass 35, count 0 2006.225.08:07:30.94#ibcon#*after write, iclass 35, count 0 2006.225.08:07:30.94#ibcon#*before return 0, iclass 35, count 0 2006.225.08:07:30.94#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:07:30.94#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:07:30.94#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:07:30.94#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:07:30.94$vc4f8/vb=2,4 2006.225.08:07:30.94#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.225.08:07:30.94#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.225.08:07:30.94#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:30.94#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:07:31.00#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:07:31.00#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:07:31.00#ibcon#enter wrdev, iclass 37, count 2 2006.225.08:07:31.00#ibcon#first serial, iclass 37, count 2 2006.225.08:07:31.00#ibcon#enter sib2, iclass 37, count 2 2006.225.08:07:31.00#ibcon#flushed, iclass 37, count 2 2006.225.08:07:31.00#ibcon#about to write, iclass 37, count 2 2006.225.08:07:31.00#ibcon#wrote, iclass 37, count 2 2006.225.08:07:31.00#ibcon#about to read 3, iclass 37, count 2 2006.225.08:07:31.02#ibcon#read 3, iclass 37, count 2 2006.225.08:07:31.02#ibcon#about to read 4, iclass 37, count 2 2006.225.08:07:31.02#ibcon#read 4, iclass 37, count 2 2006.225.08:07:31.02#ibcon#about to read 5, iclass 37, count 2 2006.225.08:07:31.02#ibcon#read 5, iclass 37, count 2 2006.225.08:07:31.02#ibcon#about to read 6, iclass 37, count 2 2006.225.08:07:31.02#ibcon#read 6, iclass 37, count 2 2006.225.08:07:31.02#ibcon#end of sib2, iclass 37, count 2 2006.225.08:07:31.02#ibcon#*mode == 0, iclass 37, count 2 2006.225.08:07:31.02#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.225.08:07:31.02#ibcon#[27=AT02-04\r\n] 2006.225.08:07:31.02#ibcon#*before write, iclass 37, count 2 2006.225.08:07:31.02#ibcon#enter sib2, iclass 37, count 2 2006.225.08:07:31.02#ibcon#flushed, iclass 37, count 2 2006.225.08:07:31.02#ibcon#about to write, iclass 37, count 2 2006.225.08:07:31.02#ibcon#wrote, iclass 37, count 2 2006.225.08:07:31.02#ibcon#about to read 3, iclass 37, count 2 2006.225.08:07:31.05#ibcon#read 3, iclass 37, count 2 2006.225.08:07:31.05#ibcon#about to read 4, iclass 37, count 2 2006.225.08:07:31.05#ibcon#read 4, iclass 37, count 2 2006.225.08:07:31.05#ibcon#about to read 5, iclass 37, count 2 2006.225.08:07:31.05#ibcon#read 5, iclass 37, count 2 2006.225.08:07:31.05#ibcon#about to read 6, iclass 37, count 2 2006.225.08:07:31.05#ibcon#read 6, iclass 37, count 2 2006.225.08:07:31.05#ibcon#end of sib2, iclass 37, count 2 2006.225.08:07:31.05#ibcon#*after write, iclass 37, count 2 2006.225.08:07:31.05#ibcon#*before return 0, iclass 37, count 2 2006.225.08:07:31.05#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:07:31.05#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:07:31.05#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.225.08:07:31.05#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:31.05#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:07:31.17#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:07:31.17#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:07:31.17#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:07:31.17#ibcon#first serial, iclass 37, count 0 2006.225.08:07:31.17#ibcon#enter sib2, iclass 37, count 0 2006.225.08:07:31.17#ibcon#flushed, iclass 37, count 0 2006.225.08:07:31.17#ibcon#about to write, iclass 37, count 0 2006.225.08:07:31.17#ibcon#wrote, iclass 37, count 0 2006.225.08:07:31.17#ibcon#about to read 3, iclass 37, count 0 2006.225.08:07:31.19#ibcon#read 3, iclass 37, count 0 2006.225.08:07:31.19#ibcon#about to read 4, iclass 37, count 0 2006.225.08:07:31.19#ibcon#read 4, iclass 37, count 0 2006.225.08:07:31.19#ibcon#about to read 5, iclass 37, count 0 2006.225.08:07:31.19#ibcon#read 5, iclass 37, count 0 2006.225.08:07:31.19#ibcon#about to read 6, iclass 37, count 0 2006.225.08:07:31.19#ibcon#read 6, iclass 37, count 0 2006.225.08:07:31.19#ibcon#end of sib2, iclass 37, count 0 2006.225.08:07:31.19#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:07:31.19#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:07:31.19#ibcon#[27=USB\r\n] 2006.225.08:07:31.19#ibcon#*before write, iclass 37, count 0 2006.225.08:07:31.19#ibcon#enter sib2, iclass 37, count 0 2006.225.08:07:31.19#ibcon#flushed, iclass 37, count 0 2006.225.08:07:31.19#ibcon#about to write, iclass 37, count 0 2006.225.08:07:31.19#ibcon#wrote, iclass 37, count 0 2006.225.08:07:31.19#ibcon#about to read 3, iclass 37, count 0 2006.225.08:07:31.22#ibcon#read 3, iclass 37, count 0 2006.225.08:07:31.22#ibcon#about to read 4, iclass 37, count 0 2006.225.08:07:31.22#ibcon#read 4, iclass 37, count 0 2006.225.08:07:31.22#ibcon#about to read 5, iclass 37, count 0 2006.225.08:07:31.22#ibcon#read 5, iclass 37, count 0 2006.225.08:07:31.22#ibcon#about to read 6, iclass 37, count 0 2006.225.08:07:31.22#ibcon#read 6, iclass 37, count 0 2006.225.08:07:31.22#ibcon#end of sib2, iclass 37, count 0 2006.225.08:07:31.22#ibcon#*after write, iclass 37, count 0 2006.225.08:07:31.22#ibcon#*before return 0, iclass 37, count 0 2006.225.08:07:31.22#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:07:31.22#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:07:31.22#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:07:31.22#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:07:31.22$vc4f8/vblo=3,656.99 2006.225.08:07:31.22#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.08:07:31.22#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.08:07:31.22#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:31.22#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:07:31.22#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:07:31.22#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:07:31.22#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:07:31.22#ibcon#first serial, iclass 39, count 0 2006.225.08:07:31.22#ibcon#enter sib2, iclass 39, count 0 2006.225.08:07:31.22#ibcon#flushed, iclass 39, count 0 2006.225.08:07:31.22#ibcon#about to write, iclass 39, count 0 2006.225.08:07:31.22#ibcon#wrote, iclass 39, count 0 2006.225.08:07:31.22#ibcon#about to read 3, iclass 39, count 0 2006.225.08:07:31.24#ibcon#read 3, iclass 39, count 0 2006.225.08:07:31.24#ibcon#about to read 4, iclass 39, count 0 2006.225.08:07:31.24#ibcon#read 4, iclass 39, count 0 2006.225.08:07:31.24#ibcon#about to read 5, iclass 39, count 0 2006.225.08:07:31.24#ibcon#read 5, iclass 39, count 0 2006.225.08:07:31.24#ibcon#about to read 6, iclass 39, count 0 2006.225.08:07:31.24#ibcon#read 6, iclass 39, count 0 2006.225.08:07:31.24#ibcon#end of sib2, iclass 39, count 0 2006.225.08:07:31.24#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:07:31.24#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:07:31.24#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:07:31.24#ibcon#*before write, iclass 39, count 0 2006.225.08:07:31.24#ibcon#enter sib2, iclass 39, count 0 2006.225.08:07:31.24#ibcon#flushed, iclass 39, count 0 2006.225.08:07:31.24#ibcon#about to write, iclass 39, count 0 2006.225.08:07:31.24#ibcon#wrote, iclass 39, count 0 2006.225.08:07:31.24#ibcon#about to read 3, iclass 39, count 0 2006.225.08:07:31.28#ibcon#read 3, iclass 39, count 0 2006.225.08:07:31.28#ibcon#about to read 4, iclass 39, count 0 2006.225.08:07:31.28#ibcon#read 4, iclass 39, count 0 2006.225.08:07:31.28#ibcon#about to read 5, iclass 39, count 0 2006.225.08:07:31.28#ibcon#read 5, iclass 39, count 0 2006.225.08:07:31.28#ibcon#about to read 6, iclass 39, count 0 2006.225.08:07:31.28#ibcon#read 6, iclass 39, count 0 2006.225.08:07:31.28#ibcon#end of sib2, iclass 39, count 0 2006.225.08:07:31.28#ibcon#*after write, iclass 39, count 0 2006.225.08:07:31.28#ibcon#*before return 0, iclass 39, count 0 2006.225.08:07:31.28#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:07:31.28#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:07:31.28#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:07:31.28#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:07:31.28$vc4f8/vb=3,4 2006.225.08:07:31.28#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.08:07:31.28#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.08:07:31.28#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:31.28#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:07:31.34#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:07:31.34#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:07:31.34#ibcon#enter wrdev, iclass 3, count 2 2006.225.08:07:31.34#ibcon#first serial, iclass 3, count 2 2006.225.08:07:31.34#ibcon#enter sib2, iclass 3, count 2 2006.225.08:07:31.34#ibcon#flushed, iclass 3, count 2 2006.225.08:07:31.34#ibcon#about to write, iclass 3, count 2 2006.225.08:07:31.34#ibcon#wrote, iclass 3, count 2 2006.225.08:07:31.34#ibcon#about to read 3, iclass 3, count 2 2006.225.08:07:31.36#ibcon#read 3, iclass 3, count 2 2006.225.08:07:31.36#ibcon#about to read 4, iclass 3, count 2 2006.225.08:07:31.36#ibcon#read 4, iclass 3, count 2 2006.225.08:07:31.36#ibcon#about to read 5, iclass 3, count 2 2006.225.08:07:31.36#ibcon#read 5, iclass 3, count 2 2006.225.08:07:31.36#ibcon#about to read 6, iclass 3, count 2 2006.225.08:07:31.36#ibcon#read 6, iclass 3, count 2 2006.225.08:07:31.36#ibcon#end of sib2, iclass 3, count 2 2006.225.08:07:31.36#ibcon#*mode == 0, iclass 3, count 2 2006.225.08:07:31.36#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.08:07:31.36#ibcon#[27=AT03-04\r\n] 2006.225.08:07:31.36#ibcon#*before write, iclass 3, count 2 2006.225.08:07:31.36#ibcon#enter sib2, iclass 3, count 2 2006.225.08:07:31.36#ibcon#flushed, iclass 3, count 2 2006.225.08:07:31.36#ibcon#about to write, iclass 3, count 2 2006.225.08:07:31.36#ibcon#wrote, iclass 3, count 2 2006.225.08:07:31.36#ibcon#about to read 3, iclass 3, count 2 2006.225.08:07:31.39#ibcon#read 3, iclass 3, count 2 2006.225.08:07:31.39#ibcon#about to read 4, iclass 3, count 2 2006.225.08:07:31.39#ibcon#read 4, iclass 3, count 2 2006.225.08:07:31.39#ibcon#about to read 5, iclass 3, count 2 2006.225.08:07:31.39#ibcon#read 5, iclass 3, count 2 2006.225.08:07:31.39#ibcon#about to read 6, iclass 3, count 2 2006.225.08:07:31.39#ibcon#read 6, iclass 3, count 2 2006.225.08:07:31.39#ibcon#end of sib2, iclass 3, count 2 2006.225.08:07:31.39#ibcon#*after write, iclass 3, count 2 2006.225.08:07:31.39#ibcon#*before return 0, iclass 3, count 2 2006.225.08:07:31.39#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:07:31.39#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:07:31.39#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.08:07:31.39#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:31.39#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:07:31.51#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:07:31.51#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:07:31.51#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:07:31.51#ibcon#first serial, iclass 3, count 0 2006.225.08:07:31.51#ibcon#enter sib2, iclass 3, count 0 2006.225.08:07:31.51#ibcon#flushed, iclass 3, count 0 2006.225.08:07:31.51#ibcon#about to write, iclass 3, count 0 2006.225.08:07:31.51#ibcon#wrote, iclass 3, count 0 2006.225.08:07:31.51#ibcon#about to read 3, iclass 3, count 0 2006.225.08:07:31.53#ibcon#read 3, iclass 3, count 0 2006.225.08:07:31.53#ibcon#about to read 4, iclass 3, count 0 2006.225.08:07:31.53#ibcon#read 4, iclass 3, count 0 2006.225.08:07:31.53#ibcon#about to read 5, iclass 3, count 0 2006.225.08:07:31.53#ibcon#read 5, iclass 3, count 0 2006.225.08:07:31.53#ibcon#about to read 6, iclass 3, count 0 2006.225.08:07:31.53#ibcon#read 6, iclass 3, count 0 2006.225.08:07:31.53#ibcon#end of sib2, iclass 3, count 0 2006.225.08:07:31.53#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:07:31.53#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:07:31.53#ibcon#[27=USB\r\n] 2006.225.08:07:31.53#ibcon#*before write, iclass 3, count 0 2006.225.08:07:31.53#ibcon#enter sib2, iclass 3, count 0 2006.225.08:07:31.53#ibcon#flushed, iclass 3, count 0 2006.225.08:07:31.53#ibcon#about to write, iclass 3, count 0 2006.225.08:07:31.53#ibcon#wrote, iclass 3, count 0 2006.225.08:07:31.53#ibcon#about to read 3, iclass 3, count 0 2006.225.08:07:31.56#ibcon#read 3, iclass 3, count 0 2006.225.08:07:31.56#ibcon#about to read 4, iclass 3, count 0 2006.225.08:07:31.56#ibcon#read 4, iclass 3, count 0 2006.225.08:07:31.56#ibcon#about to read 5, iclass 3, count 0 2006.225.08:07:31.56#ibcon#read 5, iclass 3, count 0 2006.225.08:07:31.56#ibcon#about to read 6, iclass 3, count 0 2006.225.08:07:31.56#ibcon#read 6, iclass 3, count 0 2006.225.08:07:31.56#ibcon#end of sib2, iclass 3, count 0 2006.225.08:07:31.56#ibcon#*after write, iclass 3, count 0 2006.225.08:07:31.56#ibcon#*before return 0, iclass 3, count 0 2006.225.08:07:31.56#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:07:31.56#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:07:31.56#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:07:31.56#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:07:31.56$vc4f8/vblo=4,712.99 2006.225.08:07:31.56#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.08:07:31.56#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.08:07:31.56#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:31.56#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:07:31.56#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:07:31.56#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:07:31.56#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:07:31.56#ibcon#first serial, iclass 5, count 0 2006.225.08:07:31.56#ibcon#enter sib2, iclass 5, count 0 2006.225.08:07:31.56#ibcon#flushed, iclass 5, count 0 2006.225.08:07:31.56#ibcon#about to write, iclass 5, count 0 2006.225.08:07:31.56#ibcon#wrote, iclass 5, count 0 2006.225.08:07:31.56#ibcon#about to read 3, iclass 5, count 0 2006.225.08:07:31.58#ibcon#read 3, iclass 5, count 0 2006.225.08:07:31.58#ibcon#about to read 4, iclass 5, count 0 2006.225.08:07:31.58#ibcon#read 4, iclass 5, count 0 2006.225.08:07:31.58#ibcon#about to read 5, iclass 5, count 0 2006.225.08:07:31.58#ibcon#read 5, iclass 5, count 0 2006.225.08:07:31.58#ibcon#about to read 6, iclass 5, count 0 2006.225.08:07:31.58#ibcon#read 6, iclass 5, count 0 2006.225.08:07:31.58#ibcon#end of sib2, iclass 5, count 0 2006.225.08:07:31.58#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:07:31.58#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:07:31.58#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:07:31.58#ibcon#*before write, iclass 5, count 0 2006.225.08:07:31.58#ibcon#enter sib2, iclass 5, count 0 2006.225.08:07:31.58#ibcon#flushed, iclass 5, count 0 2006.225.08:07:31.58#ibcon#about to write, iclass 5, count 0 2006.225.08:07:31.58#ibcon#wrote, iclass 5, count 0 2006.225.08:07:31.58#ibcon#about to read 3, iclass 5, count 0 2006.225.08:07:31.62#ibcon#read 3, iclass 5, count 0 2006.225.08:07:31.62#ibcon#about to read 4, iclass 5, count 0 2006.225.08:07:31.62#ibcon#read 4, iclass 5, count 0 2006.225.08:07:31.62#ibcon#about to read 5, iclass 5, count 0 2006.225.08:07:31.62#ibcon#read 5, iclass 5, count 0 2006.225.08:07:31.62#ibcon#about to read 6, iclass 5, count 0 2006.225.08:07:31.62#ibcon#read 6, iclass 5, count 0 2006.225.08:07:31.62#ibcon#end of sib2, iclass 5, count 0 2006.225.08:07:31.62#ibcon#*after write, iclass 5, count 0 2006.225.08:07:31.62#ibcon#*before return 0, iclass 5, count 0 2006.225.08:07:31.62#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:07:31.62#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:07:31.62#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:07:31.62#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:07:31.62$vc4f8/vb=4,4 2006.225.08:07:31.62#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.08:07:31.62#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.08:07:31.62#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:31.62#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:07:31.68#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:07:31.68#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:07:31.68#ibcon#enter wrdev, iclass 7, count 2 2006.225.08:07:31.68#ibcon#first serial, iclass 7, count 2 2006.225.08:07:31.68#ibcon#enter sib2, iclass 7, count 2 2006.225.08:07:31.68#ibcon#flushed, iclass 7, count 2 2006.225.08:07:31.68#ibcon#about to write, iclass 7, count 2 2006.225.08:07:31.68#ibcon#wrote, iclass 7, count 2 2006.225.08:07:31.68#ibcon#about to read 3, iclass 7, count 2 2006.225.08:07:31.70#ibcon#read 3, iclass 7, count 2 2006.225.08:07:31.70#ibcon#about to read 4, iclass 7, count 2 2006.225.08:07:31.70#ibcon#read 4, iclass 7, count 2 2006.225.08:07:31.70#ibcon#about to read 5, iclass 7, count 2 2006.225.08:07:31.70#ibcon#read 5, iclass 7, count 2 2006.225.08:07:31.70#ibcon#about to read 6, iclass 7, count 2 2006.225.08:07:31.70#ibcon#read 6, iclass 7, count 2 2006.225.08:07:31.70#ibcon#end of sib2, iclass 7, count 2 2006.225.08:07:31.70#ibcon#*mode == 0, iclass 7, count 2 2006.225.08:07:31.70#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.08:07:31.70#ibcon#[27=AT04-04\r\n] 2006.225.08:07:31.70#ibcon#*before write, iclass 7, count 2 2006.225.08:07:31.70#ibcon#enter sib2, iclass 7, count 2 2006.225.08:07:31.70#ibcon#flushed, iclass 7, count 2 2006.225.08:07:31.70#ibcon#about to write, iclass 7, count 2 2006.225.08:07:31.70#ibcon#wrote, iclass 7, count 2 2006.225.08:07:31.70#ibcon#about to read 3, iclass 7, count 2 2006.225.08:07:31.73#ibcon#read 3, iclass 7, count 2 2006.225.08:07:31.73#ibcon#about to read 4, iclass 7, count 2 2006.225.08:07:31.73#ibcon#read 4, iclass 7, count 2 2006.225.08:07:31.73#ibcon#about to read 5, iclass 7, count 2 2006.225.08:07:31.73#ibcon#read 5, iclass 7, count 2 2006.225.08:07:31.73#ibcon#about to read 6, iclass 7, count 2 2006.225.08:07:31.73#ibcon#read 6, iclass 7, count 2 2006.225.08:07:31.73#ibcon#end of sib2, iclass 7, count 2 2006.225.08:07:31.73#ibcon#*after write, iclass 7, count 2 2006.225.08:07:31.73#ibcon#*before return 0, iclass 7, count 2 2006.225.08:07:31.73#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:07:31.73#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:07:31.73#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.08:07:31.73#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:31.73#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:07:31.85#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:07:31.85#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:07:31.85#ibcon#enter wrdev, iclass 7, count 0 2006.225.08:07:31.85#ibcon#first serial, iclass 7, count 0 2006.225.08:07:31.85#ibcon#enter sib2, iclass 7, count 0 2006.225.08:07:31.85#ibcon#flushed, iclass 7, count 0 2006.225.08:07:31.85#ibcon#about to write, iclass 7, count 0 2006.225.08:07:31.85#ibcon#wrote, iclass 7, count 0 2006.225.08:07:31.85#ibcon#about to read 3, iclass 7, count 0 2006.225.08:07:31.87#ibcon#read 3, iclass 7, count 0 2006.225.08:07:31.87#ibcon#about to read 4, iclass 7, count 0 2006.225.08:07:31.87#ibcon#read 4, iclass 7, count 0 2006.225.08:07:31.87#ibcon#about to read 5, iclass 7, count 0 2006.225.08:07:31.87#ibcon#read 5, iclass 7, count 0 2006.225.08:07:31.87#ibcon#about to read 6, iclass 7, count 0 2006.225.08:07:31.87#ibcon#read 6, iclass 7, count 0 2006.225.08:07:31.87#ibcon#end of sib2, iclass 7, count 0 2006.225.08:07:31.87#ibcon#*mode == 0, iclass 7, count 0 2006.225.08:07:31.87#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.08:07:31.87#ibcon#[27=USB\r\n] 2006.225.08:07:31.87#ibcon#*before write, iclass 7, count 0 2006.225.08:07:31.87#ibcon#enter sib2, iclass 7, count 0 2006.225.08:07:31.87#ibcon#flushed, iclass 7, count 0 2006.225.08:07:31.87#ibcon#about to write, iclass 7, count 0 2006.225.08:07:31.87#ibcon#wrote, iclass 7, count 0 2006.225.08:07:31.87#ibcon#about to read 3, iclass 7, count 0 2006.225.08:07:31.90#ibcon#read 3, iclass 7, count 0 2006.225.08:07:31.90#ibcon#about to read 4, iclass 7, count 0 2006.225.08:07:31.90#ibcon#read 4, iclass 7, count 0 2006.225.08:07:31.90#ibcon#about to read 5, iclass 7, count 0 2006.225.08:07:31.90#ibcon#read 5, iclass 7, count 0 2006.225.08:07:31.90#ibcon#about to read 6, iclass 7, count 0 2006.225.08:07:31.90#ibcon#read 6, iclass 7, count 0 2006.225.08:07:31.90#ibcon#end of sib2, iclass 7, count 0 2006.225.08:07:31.90#ibcon#*after write, iclass 7, count 0 2006.225.08:07:31.90#ibcon#*before return 0, iclass 7, count 0 2006.225.08:07:31.90#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:07:31.90#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:07:31.90#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.08:07:31.90#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.08:07:31.90$vc4f8/vblo=5,744.99 2006.225.08:07:31.90#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.08:07:31.90#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.08:07:31.90#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:31.90#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:07:31.90#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:07:31.90#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:07:31.90#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:07:31.90#ibcon#first serial, iclass 11, count 0 2006.225.08:07:31.90#ibcon#enter sib2, iclass 11, count 0 2006.225.08:07:31.90#ibcon#flushed, iclass 11, count 0 2006.225.08:07:31.90#ibcon#about to write, iclass 11, count 0 2006.225.08:07:31.90#ibcon#wrote, iclass 11, count 0 2006.225.08:07:31.90#ibcon#about to read 3, iclass 11, count 0 2006.225.08:07:31.92#ibcon#read 3, iclass 11, count 0 2006.225.08:07:31.92#ibcon#about to read 4, iclass 11, count 0 2006.225.08:07:31.92#ibcon#read 4, iclass 11, count 0 2006.225.08:07:31.92#ibcon#about to read 5, iclass 11, count 0 2006.225.08:07:31.92#ibcon#read 5, iclass 11, count 0 2006.225.08:07:31.92#ibcon#about to read 6, iclass 11, count 0 2006.225.08:07:31.92#ibcon#read 6, iclass 11, count 0 2006.225.08:07:31.92#ibcon#end of sib2, iclass 11, count 0 2006.225.08:07:31.92#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:07:31.92#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:07:31.92#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:07:31.92#ibcon#*before write, iclass 11, count 0 2006.225.08:07:31.92#ibcon#enter sib2, iclass 11, count 0 2006.225.08:07:31.92#ibcon#flushed, iclass 11, count 0 2006.225.08:07:31.92#ibcon#about to write, iclass 11, count 0 2006.225.08:07:31.92#ibcon#wrote, iclass 11, count 0 2006.225.08:07:31.92#ibcon#about to read 3, iclass 11, count 0 2006.225.08:07:31.96#ibcon#read 3, iclass 11, count 0 2006.225.08:07:31.96#ibcon#about to read 4, iclass 11, count 0 2006.225.08:07:31.96#ibcon#read 4, iclass 11, count 0 2006.225.08:07:31.96#ibcon#about to read 5, iclass 11, count 0 2006.225.08:07:31.96#ibcon#read 5, iclass 11, count 0 2006.225.08:07:31.96#ibcon#about to read 6, iclass 11, count 0 2006.225.08:07:31.96#ibcon#read 6, iclass 11, count 0 2006.225.08:07:31.96#ibcon#end of sib2, iclass 11, count 0 2006.225.08:07:31.96#ibcon#*after write, iclass 11, count 0 2006.225.08:07:31.96#ibcon#*before return 0, iclass 11, count 0 2006.225.08:07:31.96#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:07:31.96#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:07:31.96#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:07:31.96#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:07:31.96$vc4f8/vb=5,4 2006.225.08:07:31.96#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.08:07:31.96#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.08:07:31.96#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:31.96#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:07:32.02#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:07:32.02#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:07:32.02#ibcon#enter wrdev, iclass 13, count 2 2006.225.08:07:32.02#ibcon#first serial, iclass 13, count 2 2006.225.08:07:32.02#ibcon#enter sib2, iclass 13, count 2 2006.225.08:07:32.02#ibcon#flushed, iclass 13, count 2 2006.225.08:07:32.02#ibcon#about to write, iclass 13, count 2 2006.225.08:07:32.02#ibcon#wrote, iclass 13, count 2 2006.225.08:07:32.02#ibcon#about to read 3, iclass 13, count 2 2006.225.08:07:32.04#ibcon#read 3, iclass 13, count 2 2006.225.08:07:32.04#ibcon#about to read 4, iclass 13, count 2 2006.225.08:07:32.04#ibcon#read 4, iclass 13, count 2 2006.225.08:07:32.04#ibcon#about to read 5, iclass 13, count 2 2006.225.08:07:32.04#ibcon#read 5, iclass 13, count 2 2006.225.08:07:32.04#ibcon#about to read 6, iclass 13, count 2 2006.225.08:07:32.04#ibcon#read 6, iclass 13, count 2 2006.225.08:07:32.04#ibcon#end of sib2, iclass 13, count 2 2006.225.08:07:32.04#ibcon#*mode == 0, iclass 13, count 2 2006.225.08:07:32.04#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.08:07:32.04#ibcon#[27=AT05-04\r\n] 2006.225.08:07:32.04#ibcon#*before write, iclass 13, count 2 2006.225.08:07:32.04#ibcon#enter sib2, iclass 13, count 2 2006.225.08:07:32.04#ibcon#flushed, iclass 13, count 2 2006.225.08:07:32.04#ibcon#about to write, iclass 13, count 2 2006.225.08:07:32.04#ibcon#wrote, iclass 13, count 2 2006.225.08:07:32.04#ibcon#about to read 3, iclass 13, count 2 2006.225.08:07:32.07#ibcon#read 3, iclass 13, count 2 2006.225.08:07:32.07#ibcon#about to read 4, iclass 13, count 2 2006.225.08:07:32.07#ibcon#read 4, iclass 13, count 2 2006.225.08:07:32.07#ibcon#about to read 5, iclass 13, count 2 2006.225.08:07:32.07#ibcon#read 5, iclass 13, count 2 2006.225.08:07:32.07#ibcon#about to read 6, iclass 13, count 2 2006.225.08:07:32.07#ibcon#read 6, iclass 13, count 2 2006.225.08:07:32.07#ibcon#end of sib2, iclass 13, count 2 2006.225.08:07:32.07#ibcon#*after write, iclass 13, count 2 2006.225.08:07:32.07#ibcon#*before return 0, iclass 13, count 2 2006.225.08:07:32.07#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:07:32.07#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:07:32.07#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.08:07:32.07#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:32.07#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:07:32.19#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:07:32.19#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:07:32.19#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:07:32.19#ibcon#first serial, iclass 13, count 0 2006.225.08:07:32.19#ibcon#enter sib2, iclass 13, count 0 2006.225.08:07:32.19#ibcon#flushed, iclass 13, count 0 2006.225.08:07:32.19#ibcon#about to write, iclass 13, count 0 2006.225.08:07:32.19#ibcon#wrote, iclass 13, count 0 2006.225.08:07:32.19#ibcon#about to read 3, iclass 13, count 0 2006.225.08:07:32.21#ibcon#read 3, iclass 13, count 0 2006.225.08:07:32.21#ibcon#about to read 4, iclass 13, count 0 2006.225.08:07:32.21#ibcon#read 4, iclass 13, count 0 2006.225.08:07:32.21#ibcon#about to read 5, iclass 13, count 0 2006.225.08:07:32.21#ibcon#read 5, iclass 13, count 0 2006.225.08:07:32.21#ibcon#about to read 6, iclass 13, count 0 2006.225.08:07:32.21#ibcon#read 6, iclass 13, count 0 2006.225.08:07:32.21#ibcon#end of sib2, iclass 13, count 0 2006.225.08:07:32.21#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:07:32.21#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:07:32.21#ibcon#[27=USB\r\n] 2006.225.08:07:32.21#ibcon#*before write, iclass 13, count 0 2006.225.08:07:32.21#ibcon#enter sib2, iclass 13, count 0 2006.225.08:07:32.21#ibcon#flushed, iclass 13, count 0 2006.225.08:07:32.21#ibcon#about to write, iclass 13, count 0 2006.225.08:07:32.21#ibcon#wrote, iclass 13, count 0 2006.225.08:07:32.21#ibcon#about to read 3, iclass 13, count 0 2006.225.08:07:32.24#ibcon#read 3, iclass 13, count 0 2006.225.08:07:32.24#ibcon#about to read 4, iclass 13, count 0 2006.225.08:07:32.24#ibcon#read 4, iclass 13, count 0 2006.225.08:07:32.24#ibcon#about to read 5, iclass 13, count 0 2006.225.08:07:32.24#ibcon#read 5, iclass 13, count 0 2006.225.08:07:32.24#ibcon#about to read 6, iclass 13, count 0 2006.225.08:07:32.24#ibcon#read 6, iclass 13, count 0 2006.225.08:07:32.24#ibcon#end of sib2, iclass 13, count 0 2006.225.08:07:32.24#ibcon#*after write, iclass 13, count 0 2006.225.08:07:32.24#ibcon#*before return 0, iclass 13, count 0 2006.225.08:07:32.24#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:07:32.24#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:07:32.24#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:07:32.24#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:07:32.24$vc4f8/vblo=6,752.99 2006.225.08:07:32.24#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.08:07:32.24#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.08:07:32.24#ibcon#ireg 17 cls_cnt 0 2006.225.08:07:32.24#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:07:32.24#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:07:32.24#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:07:32.24#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:07:32.24#ibcon#first serial, iclass 15, count 0 2006.225.08:07:32.24#ibcon#enter sib2, iclass 15, count 0 2006.225.08:07:32.24#ibcon#flushed, iclass 15, count 0 2006.225.08:07:32.24#ibcon#about to write, iclass 15, count 0 2006.225.08:07:32.24#ibcon#wrote, iclass 15, count 0 2006.225.08:07:32.24#ibcon#about to read 3, iclass 15, count 0 2006.225.08:07:32.26#ibcon#read 3, iclass 15, count 0 2006.225.08:07:32.26#ibcon#about to read 4, iclass 15, count 0 2006.225.08:07:32.26#ibcon#read 4, iclass 15, count 0 2006.225.08:07:32.26#ibcon#about to read 5, iclass 15, count 0 2006.225.08:07:32.26#ibcon#read 5, iclass 15, count 0 2006.225.08:07:32.26#ibcon#about to read 6, iclass 15, count 0 2006.225.08:07:32.26#ibcon#read 6, iclass 15, count 0 2006.225.08:07:32.26#ibcon#end of sib2, iclass 15, count 0 2006.225.08:07:32.26#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:07:32.26#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:07:32.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:07:32.26#ibcon#*before write, iclass 15, count 0 2006.225.08:07:32.26#ibcon#enter sib2, iclass 15, count 0 2006.225.08:07:32.26#ibcon#flushed, iclass 15, count 0 2006.225.08:07:32.26#ibcon#about to write, iclass 15, count 0 2006.225.08:07:32.26#ibcon#wrote, iclass 15, count 0 2006.225.08:07:32.26#ibcon#about to read 3, iclass 15, count 0 2006.225.08:07:32.30#ibcon#read 3, iclass 15, count 0 2006.225.08:07:32.30#ibcon#about to read 4, iclass 15, count 0 2006.225.08:07:32.30#ibcon#read 4, iclass 15, count 0 2006.225.08:07:32.30#ibcon#about to read 5, iclass 15, count 0 2006.225.08:07:32.30#ibcon#read 5, iclass 15, count 0 2006.225.08:07:32.30#ibcon#about to read 6, iclass 15, count 0 2006.225.08:07:32.30#ibcon#read 6, iclass 15, count 0 2006.225.08:07:32.30#ibcon#end of sib2, iclass 15, count 0 2006.225.08:07:32.30#ibcon#*after write, iclass 15, count 0 2006.225.08:07:32.30#ibcon#*before return 0, iclass 15, count 0 2006.225.08:07:32.30#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:07:32.30#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:07:32.30#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:07:32.30#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:07:32.30$vc4f8/vb=6,4 2006.225.08:07:32.30#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.08:07:32.30#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.08:07:32.30#ibcon#ireg 11 cls_cnt 2 2006.225.08:07:32.30#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:07:32.36#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:07:32.36#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:07:32.36#ibcon#enter wrdev, iclass 17, count 2 2006.225.08:07:32.36#ibcon#first serial, iclass 17, count 2 2006.225.08:07:32.36#ibcon#enter sib2, iclass 17, count 2 2006.225.08:07:32.36#ibcon#flushed, iclass 17, count 2 2006.225.08:07:32.36#ibcon#about to write, iclass 17, count 2 2006.225.08:07:32.36#ibcon#wrote, iclass 17, count 2 2006.225.08:07:32.36#ibcon#about to read 3, iclass 17, count 2 2006.225.08:07:32.38#ibcon#read 3, iclass 17, count 2 2006.225.08:07:32.38#ibcon#about to read 4, iclass 17, count 2 2006.225.08:07:32.38#ibcon#read 4, iclass 17, count 2 2006.225.08:07:32.38#ibcon#about to read 5, iclass 17, count 2 2006.225.08:07:32.38#ibcon#read 5, iclass 17, count 2 2006.225.08:07:32.38#ibcon#about to read 6, iclass 17, count 2 2006.225.08:07:32.38#ibcon#read 6, iclass 17, count 2 2006.225.08:07:32.38#ibcon#end of sib2, iclass 17, count 2 2006.225.08:07:32.38#ibcon#*mode == 0, iclass 17, count 2 2006.225.08:07:32.38#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.08:07:32.38#ibcon#[27=AT06-04\r\n] 2006.225.08:07:32.38#ibcon#*before write, iclass 17, count 2 2006.225.08:07:32.38#ibcon#enter sib2, iclass 17, count 2 2006.225.08:07:32.38#ibcon#flushed, iclass 17, count 2 2006.225.08:07:32.38#ibcon#about to write, iclass 17, count 2 2006.225.08:07:32.38#ibcon#wrote, iclass 17, count 2 2006.225.08:07:32.38#ibcon#about to read 3, iclass 17, count 2 2006.225.08:07:32.41#ibcon#read 3, iclass 17, count 2 2006.225.08:07:32.41#ibcon#about to read 4, iclass 17, count 2 2006.225.08:07:32.41#ibcon#read 4, iclass 17, count 2 2006.225.08:07:32.41#ibcon#about to read 5, iclass 17, count 2 2006.225.08:07:32.41#ibcon#read 5, iclass 17, count 2 2006.225.08:07:32.41#ibcon#about to read 6, iclass 17, count 2 2006.225.08:07:32.41#ibcon#read 6, iclass 17, count 2 2006.225.08:07:32.41#ibcon#end of sib2, iclass 17, count 2 2006.225.08:07:32.41#ibcon#*after write, iclass 17, count 2 2006.225.08:07:32.41#ibcon#*before return 0, iclass 17, count 2 2006.225.08:07:32.41#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:07:32.41#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:07:32.41#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.08:07:32.41#ibcon#ireg 7 cls_cnt 0 2006.225.08:07:32.41#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:07:32.53#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:07:32.53#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:07:32.53#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:07:32.53#ibcon#first serial, iclass 17, count 0 2006.225.08:07:32.53#ibcon#enter sib2, iclass 17, count 0 2006.225.08:07:32.53#ibcon#flushed, iclass 17, count 0 2006.225.08:07:32.53#ibcon#about to write, iclass 17, count 0 2006.225.08:07:32.53#ibcon#wrote, iclass 17, count 0 2006.225.08:07:32.53#ibcon#about to read 3, iclass 17, count 0 2006.225.08:07:32.55#ibcon#read 3, iclass 17, count 0 2006.225.08:07:32.55#ibcon#about to read 4, iclass 17, count 0 2006.225.08:07:32.55#ibcon#read 4, iclass 17, count 0 2006.225.08:07:32.55#ibcon#about to read 5, iclass 17, count 0 2006.225.08:07:32.55#ibcon#read 5, iclass 17, count 0 2006.225.08:07:32.55#ibcon#about to read 6, iclass 17, count 0 2006.225.08:07:32.55#ibcon#read 6, iclass 17, count 0 2006.225.08:07:32.55#ibcon#end of sib2, iclass 17, count 0 2006.225.08:07:32.55#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:07:32.55#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:07:32.55#ibcon#[27=USB\r\n] 2006.225.08:07:32.55#ibcon#*before write, iclass 17, count 0 2006.225.08:07:32.55#ibcon#enter sib2, iclass 17, count 0 2006.225.08:07:32.55#ibcon#flushed, iclass 17, count 0 2006.225.08:07:32.55#ibcon#about to write, iclass 17, count 0 2006.225.08:07:32.55#ibcon#wrote, iclass 17, count 0 2006.225.08:07:32.55#ibcon#about to read 3, iclass 17, count 0 2006.225.08:07:32.58#ibcon#read 3, iclass 17, count 0 2006.225.08:07:32.58#ibcon#about to read 4, iclass 17, count 0 2006.225.08:07:32.58#ibcon#read 4, iclass 17, count 0 2006.225.08:07:32.58#ibcon#about to read 5, iclass 17, count 0 2006.225.08:07:32.58#ibcon#read 5, iclass 17, count 0 2006.225.08:07:32.58#ibcon#about to read 6, iclass 17, count 0 2006.225.08:07:32.58#ibcon#read 6, iclass 17, count 0 2006.225.08:07:32.58#ibcon#end of sib2, iclass 17, count 0 2006.225.08:07:32.58#ibcon#*after write, iclass 17, count 0 2006.225.08:07:32.58#ibcon#*before return 0, iclass 17, count 0 2006.225.08:07:32.58#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:07:32.58#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:07:32.58#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:07:32.58#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:07:32.58$vc4f8/vabw=wide 2006.225.08:07:32.58#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.08:07:32.58#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.08:07:32.58#ibcon#ireg 8 cls_cnt 0 2006.225.08:07:32.58#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:07:32.58#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:07:32.58#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:07:32.58#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:07:32.58#ibcon#first serial, iclass 19, count 0 2006.225.08:07:32.58#ibcon#enter sib2, iclass 19, count 0 2006.225.08:07:32.58#ibcon#flushed, iclass 19, count 0 2006.225.08:07:32.58#ibcon#about to write, iclass 19, count 0 2006.225.08:07:32.58#ibcon#wrote, iclass 19, count 0 2006.225.08:07:32.58#ibcon#about to read 3, iclass 19, count 0 2006.225.08:07:32.60#ibcon#read 3, iclass 19, count 0 2006.225.08:07:32.60#ibcon#about to read 4, iclass 19, count 0 2006.225.08:07:32.60#ibcon#read 4, iclass 19, count 0 2006.225.08:07:32.60#ibcon#about to read 5, iclass 19, count 0 2006.225.08:07:32.60#ibcon#read 5, iclass 19, count 0 2006.225.08:07:32.60#ibcon#about to read 6, iclass 19, count 0 2006.225.08:07:32.60#ibcon#read 6, iclass 19, count 0 2006.225.08:07:32.60#ibcon#end of sib2, iclass 19, count 0 2006.225.08:07:32.60#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:07:32.60#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:07:32.60#ibcon#[25=BW32\r\n] 2006.225.08:07:32.60#ibcon#*before write, iclass 19, count 0 2006.225.08:07:32.60#ibcon#enter sib2, iclass 19, count 0 2006.225.08:07:32.60#ibcon#flushed, iclass 19, count 0 2006.225.08:07:32.60#ibcon#about to write, iclass 19, count 0 2006.225.08:07:32.60#ibcon#wrote, iclass 19, count 0 2006.225.08:07:32.60#ibcon#about to read 3, iclass 19, count 0 2006.225.08:07:32.63#ibcon#read 3, iclass 19, count 0 2006.225.08:07:32.63#ibcon#about to read 4, iclass 19, count 0 2006.225.08:07:32.63#ibcon#read 4, iclass 19, count 0 2006.225.08:07:32.63#ibcon#about to read 5, iclass 19, count 0 2006.225.08:07:32.63#ibcon#read 5, iclass 19, count 0 2006.225.08:07:32.63#ibcon#about to read 6, iclass 19, count 0 2006.225.08:07:32.63#ibcon#read 6, iclass 19, count 0 2006.225.08:07:32.63#ibcon#end of sib2, iclass 19, count 0 2006.225.08:07:32.63#ibcon#*after write, iclass 19, count 0 2006.225.08:07:32.63#ibcon#*before return 0, iclass 19, count 0 2006.225.08:07:32.63#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:07:32.63#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:07:32.63#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:07:32.63#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:07:32.63$vc4f8/vbbw=wide 2006.225.08:07:32.63#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.225.08:07:32.63#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.225.08:07:32.63#ibcon#ireg 8 cls_cnt 0 2006.225.08:07:32.63#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:07:32.70#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:07:32.70#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:07:32.70#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:07:32.70#ibcon#first serial, iclass 21, count 0 2006.225.08:07:32.70#ibcon#enter sib2, iclass 21, count 0 2006.225.08:07:32.70#ibcon#flushed, iclass 21, count 0 2006.225.08:07:32.70#ibcon#about to write, iclass 21, count 0 2006.225.08:07:32.70#ibcon#wrote, iclass 21, count 0 2006.225.08:07:32.70#ibcon#about to read 3, iclass 21, count 0 2006.225.08:07:32.72#ibcon#read 3, iclass 21, count 0 2006.225.08:07:32.72#ibcon#about to read 4, iclass 21, count 0 2006.225.08:07:32.72#ibcon#read 4, iclass 21, count 0 2006.225.08:07:32.72#ibcon#about to read 5, iclass 21, count 0 2006.225.08:07:32.72#ibcon#read 5, iclass 21, count 0 2006.225.08:07:32.72#ibcon#about to read 6, iclass 21, count 0 2006.225.08:07:32.72#ibcon#read 6, iclass 21, count 0 2006.225.08:07:32.72#ibcon#end of sib2, iclass 21, count 0 2006.225.08:07:32.72#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:07:32.72#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:07:32.72#ibcon#[27=BW32\r\n] 2006.225.08:07:32.72#ibcon#*before write, iclass 21, count 0 2006.225.08:07:32.72#ibcon#enter sib2, iclass 21, count 0 2006.225.08:07:32.72#ibcon#flushed, iclass 21, count 0 2006.225.08:07:32.72#ibcon#about to write, iclass 21, count 0 2006.225.08:07:32.72#ibcon#wrote, iclass 21, count 0 2006.225.08:07:32.72#ibcon#about to read 3, iclass 21, count 0 2006.225.08:07:32.75#ibcon#read 3, iclass 21, count 0 2006.225.08:07:32.75#ibcon#about to read 4, iclass 21, count 0 2006.225.08:07:32.75#ibcon#read 4, iclass 21, count 0 2006.225.08:07:32.75#ibcon#about to read 5, iclass 21, count 0 2006.225.08:07:32.75#ibcon#read 5, iclass 21, count 0 2006.225.08:07:32.75#ibcon#about to read 6, iclass 21, count 0 2006.225.08:07:32.75#ibcon#read 6, iclass 21, count 0 2006.225.08:07:32.75#ibcon#end of sib2, iclass 21, count 0 2006.225.08:07:32.75#ibcon#*after write, iclass 21, count 0 2006.225.08:07:32.75#ibcon#*before return 0, iclass 21, count 0 2006.225.08:07:32.75#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:07:32.75#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:07:32.75#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:07:32.75#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:07:32.75$4f8m12a/ifd4f 2006.225.08:07:32.75$ifd4f/lo= 2006.225.08:07:32.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:07:32.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:07:32.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:07:32.76$ifd4f/patch= 2006.225.08:07:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:07:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:07:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:07:32.76$4f8m12a/"form=m,16.000,1:2 2006.225.08:07:32.76$4f8m12a/"tpicd 2006.225.08:07:32.76$4f8m12a/echo=off 2006.225.08:07:32.76$4f8m12a/xlog=off 2006.225.08:07:32.76:!2006.225.08:08:00 2006.225.08:07:42.13#trakl#Source acquired 2006.225.08:07:42.13#flagr#flagr/antenna,acquired 2006.225.08:08:00.01:preob 2006.225.08:08:01.13/onsource/TRACKING 2006.225.08:08:01.13:!2006.225.08:08:10 2006.225.08:08:10.00:data_valid=on 2006.225.08:08:10.00:midob 2006.225.08:08:10.13/onsource/TRACKING 2006.225.08:08:10.13/wx/28.14,1003.3,70 2006.225.08:08:10.26/cable/+6.4036E-03 2006.225.08:08:11.35/va/01,08,usb,yes,30,31 2006.225.08:08:11.35/va/02,07,usb,yes,30,31 2006.225.08:08:11.35/va/03,06,usb,yes,32,32 2006.225.08:08:11.35/va/04,07,usb,yes,31,34 2006.225.08:08:11.35/va/05,07,usb,yes,34,36 2006.225.08:08:11.35/va/06,06,usb,yes,33,33 2006.225.08:08:11.35/va/07,06,usb,yes,34,34 2006.225.08:08:11.35/va/08,07,usb,yes,32,32 2006.225.08:08:11.58/valo/01,532.99,yes,locked 2006.225.08:08:11.58/valo/02,572.99,yes,locked 2006.225.08:08:11.58/valo/03,672.99,yes,locked 2006.225.08:08:11.58/valo/04,832.99,yes,locked 2006.225.08:08:11.58/valo/05,652.99,yes,locked 2006.225.08:08:11.58/valo/06,772.99,yes,locked 2006.225.08:08:11.58/valo/07,832.99,yes,locked 2006.225.08:08:11.58/valo/08,852.99,yes,locked 2006.225.08:08:12.67/vb/01,04,usb,yes,32,30 2006.225.08:08:12.67/vb/02,04,usb,yes,33,35 2006.225.08:08:12.67/vb/03,04,usb,yes,29,33 2006.225.08:08:12.67/vb/04,04,usb,yes,30,30 2006.225.08:08:12.67/vb/05,04,usb,yes,29,33 2006.225.08:08:12.67/vb/06,04,usb,yes,30,33 2006.225.08:08:12.67/vb/07,04,usb,yes,32,32 2006.225.08:08:12.67/vb/08,04,usb,yes,29,33 2006.225.08:08:12.90/vblo/01,632.99,yes,locked 2006.225.08:08:12.90/vblo/02,640.99,yes,locked 2006.225.08:08:12.90/vblo/03,656.99,yes,locked 2006.225.08:08:12.90/vblo/04,712.99,yes,locked 2006.225.08:08:12.90/vblo/05,744.99,yes,locked 2006.225.08:08:12.90/vblo/06,752.99,yes,locked 2006.225.08:08:12.90/vblo/07,734.99,yes,locked 2006.225.08:08:12.90/vblo/08,744.99,yes,locked 2006.225.08:08:13.05/vabw/8 2006.225.08:08:13.20/vbbw/8 2006.225.08:08:13.29/xfe/off,on,15.5 2006.225.08:08:13.66/ifatt/23,28,28,28 2006.225.08:08:14.07/fmout-gps/S +4.59E-07 2006.225.08:08:14.11:!2006.225.08:09:10 2006.225.08:09:10.01:data_valid=off 2006.225.08:09:10.02:postob 2006.225.08:09:10.22/cable/+6.4035E-03 2006.225.08:09:10.23/wx/28.13,1003.3,69 2006.225.08:09:11.07/fmout-gps/S +4.59E-07 2006.225.08:09:11.08:scan_name=225-0810,k06225,60 2006.225.08:09:11.08:source=1739+522,174036.98,521143.4,2000.0,cw 2006.225.08:09:11.13#flagr#flagr/antenna,new-source 2006.225.08:09:12.13:checkk5 2006.225.08:09:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:09:12.87/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:09:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:09:13.62/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:09:13.98/chk_obsdata//k5ts1/T2250808??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:09:14.35/chk_obsdata//k5ts2/T2250808??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:09:14.72/chk_obsdata//k5ts3/T2250808??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:09:15.09/chk_obsdata//k5ts4/T2250808??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:09:15.77/k5log//k5ts1_log_newline 2006.225.08:09:16.46/k5log//k5ts2_log_newline 2006.225.08:09:17.15/k5log//k5ts3_log_newline 2006.225.08:09:17.84/k5log//k5ts4_log_newline 2006.225.08:09:17.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:09:17.86:4f8m12a=2 2006.225.08:09:17.86$4f8m12a/echo=on 2006.225.08:09:17.86$4f8m12a/pcalon 2006.225.08:09:17.86$pcalon/"no phase cal control is implemented here 2006.225.08:09:17.86$4f8m12a/"tpicd=stop 2006.225.08:09:17.86$4f8m12a/vc4f8 2006.225.08:09:17.86$vc4f8/valo=1,532.99 2006.225.08:09:17.86#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.08:09:17.86#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.08:09:17.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:17.86#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:09:17.86#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:09:17.86#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:09:17.86#ibcon#enter wrdev, iclass 28, count 0 2006.225.08:09:17.86#ibcon#first serial, iclass 28, count 0 2006.225.08:09:17.86#ibcon#enter sib2, iclass 28, count 0 2006.225.08:09:17.86#ibcon#flushed, iclass 28, count 0 2006.225.08:09:17.86#ibcon#about to write, iclass 28, count 0 2006.225.08:09:17.86#ibcon#wrote, iclass 28, count 0 2006.225.08:09:17.86#ibcon#about to read 3, iclass 28, count 0 2006.225.08:09:17.90#ibcon#read 3, iclass 28, count 0 2006.225.08:09:17.90#ibcon#about to read 4, iclass 28, count 0 2006.225.08:09:17.90#ibcon#read 4, iclass 28, count 0 2006.225.08:09:17.90#ibcon#about to read 5, iclass 28, count 0 2006.225.08:09:17.90#ibcon#read 5, iclass 28, count 0 2006.225.08:09:17.90#ibcon#about to read 6, iclass 28, count 0 2006.225.08:09:17.90#ibcon#read 6, iclass 28, count 0 2006.225.08:09:17.90#ibcon#end of sib2, iclass 28, count 0 2006.225.08:09:17.90#ibcon#*mode == 0, iclass 28, count 0 2006.225.08:09:17.90#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.08:09:17.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:09:17.90#ibcon#*before write, iclass 28, count 0 2006.225.08:09:17.90#ibcon#enter sib2, iclass 28, count 0 2006.225.08:09:17.90#ibcon#flushed, iclass 28, count 0 2006.225.08:09:17.90#ibcon#about to write, iclass 28, count 0 2006.225.08:09:17.90#ibcon#wrote, iclass 28, count 0 2006.225.08:09:17.90#ibcon#about to read 3, iclass 28, count 0 2006.225.08:09:17.95#ibcon#read 3, iclass 28, count 0 2006.225.08:09:17.95#ibcon#about to read 4, iclass 28, count 0 2006.225.08:09:17.95#ibcon#read 4, iclass 28, count 0 2006.225.08:09:17.95#ibcon#about to read 5, iclass 28, count 0 2006.225.08:09:17.95#ibcon#read 5, iclass 28, count 0 2006.225.08:09:17.95#ibcon#about to read 6, iclass 28, count 0 2006.225.08:09:17.95#ibcon#read 6, iclass 28, count 0 2006.225.08:09:17.95#ibcon#end of sib2, iclass 28, count 0 2006.225.08:09:17.95#ibcon#*after write, iclass 28, count 0 2006.225.08:09:17.95#ibcon#*before return 0, iclass 28, count 0 2006.225.08:09:17.95#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:09:17.95#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:09:17.95#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.08:09:17.95#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.08:09:17.95$vc4f8/va=1,8 2006.225.08:09:17.95#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.08:09:17.95#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.08:09:17.95#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:17.95#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:09:17.95#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:09:17.95#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:09:17.95#ibcon#enter wrdev, iclass 30, count 2 2006.225.08:09:17.95#ibcon#first serial, iclass 30, count 2 2006.225.08:09:17.95#ibcon#enter sib2, iclass 30, count 2 2006.225.08:09:17.95#ibcon#flushed, iclass 30, count 2 2006.225.08:09:17.95#ibcon#about to write, iclass 30, count 2 2006.225.08:09:17.95#ibcon#wrote, iclass 30, count 2 2006.225.08:09:17.95#ibcon#about to read 3, iclass 30, count 2 2006.225.08:09:17.98#ibcon#read 3, iclass 30, count 2 2006.225.08:09:17.98#ibcon#about to read 4, iclass 30, count 2 2006.225.08:09:17.98#ibcon#read 4, iclass 30, count 2 2006.225.08:09:17.98#ibcon#about to read 5, iclass 30, count 2 2006.225.08:09:17.98#ibcon#read 5, iclass 30, count 2 2006.225.08:09:17.98#ibcon#about to read 6, iclass 30, count 2 2006.225.08:09:17.98#ibcon#read 6, iclass 30, count 2 2006.225.08:09:17.98#ibcon#end of sib2, iclass 30, count 2 2006.225.08:09:17.98#ibcon#*mode == 0, iclass 30, count 2 2006.225.08:09:17.98#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.08:09:17.98#ibcon#[25=AT01-08\r\n] 2006.225.08:09:17.98#ibcon#*before write, iclass 30, count 2 2006.225.08:09:17.98#ibcon#enter sib2, iclass 30, count 2 2006.225.08:09:17.98#ibcon#flushed, iclass 30, count 2 2006.225.08:09:17.98#ibcon#about to write, iclass 30, count 2 2006.225.08:09:17.98#ibcon#wrote, iclass 30, count 2 2006.225.08:09:17.98#ibcon#about to read 3, iclass 30, count 2 2006.225.08:09:18.01#ibcon#read 3, iclass 30, count 2 2006.225.08:09:18.01#ibcon#about to read 4, iclass 30, count 2 2006.225.08:09:18.01#ibcon#read 4, iclass 30, count 2 2006.225.08:09:18.01#ibcon#about to read 5, iclass 30, count 2 2006.225.08:09:18.01#ibcon#read 5, iclass 30, count 2 2006.225.08:09:18.01#ibcon#about to read 6, iclass 30, count 2 2006.225.08:09:18.01#ibcon#read 6, iclass 30, count 2 2006.225.08:09:18.01#ibcon#end of sib2, iclass 30, count 2 2006.225.08:09:18.01#ibcon#*after write, iclass 30, count 2 2006.225.08:09:18.01#ibcon#*before return 0, iclass 30, count 2 2006.225.08:09:18.01#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:09:18.01#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:09:18.01#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.08:09:18.01#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:18.01#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:09:18.13#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:09:18.13#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:09:18.13#ibcon#enter wrdev, iclass 30, count 0 2006.225.08:09:18.13#ibcon#first serial, iclass 30, count 0 2006.225.08:09:18.13#ibcon#enter sib2, iclass 30, count 0 2006.225.08:09:18.13#ibcon#flushed, iclass 30, count 0 2006.225.08:09:18.13#ibcon#about to write, iclass 30, count 0 2006.225.08:09:18.13#ibcon#wrote, iclass 30, count 0 2006.225.08:09:18.13#ibcon#about to read 3, iclass 30, count 0 2006.225.08:09:18.15#ibcon#read 3, iclass 30, count 0 2006.225.08:09:18.15#ibcon#about to read 4, iclass 30, count 0 2006.225.08:09:18.15#ibcon#read 4, iclass 30, count 0 2006.225.08:09:18.15#ibcon#about to read 5, iclass 30, count 0 2006.225.08:09:18.15#ibcon#read 5, iclass 30, count 0 2006.225.08:09:18.15#ibcon#about to read 6, iclass 30, count 0 2006.225.08:09:18.15#ibcon#read 6, iclass 30, count 0 2006.225.08:09:18.15#ibcon#end of sib2, iclass 30, count 0 2006.225.08:09:18.15#ibcon#*mode == 0, iclass 30, count 0 2006.225.08:09:18.15#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.08:09:18.15#ibcon#[25=USB\r\n] 2006.225.08:09:18.15#ibcon#*before write, iclass 30, count 0 2006.225.08:09:18.15#ibcon#enter sib2, iclass 30, count 0 2006.225.08:09:18.15#ibcon#flushed, iclass 30, count 0 2006.225.08:09:18.15#ibcon#about to write, iclass 30, count 0 2006.225.08:09:18.15#ibcon#wrote, iclass 30, count 0 2006.225.08:09:18.15#ibcon#about to read 3, iclass 30, count 0 2006.225.08:09:18.18#ibcon#read 3, iclass 30, count 0 2006.225.08:09:18.18#ibcon#about to read 4, iclass 30, count 0 2006.225.08:09:18.18#ibcon#read 4, iclass 30, count 0 2006.225.08:09:18.18#ibcon#about to read 5, iclass 30, count 0 2006.225.08:09:18.18#ibcon#read 5, iclass 30, count 0 2006.225.08:09:18.18#ibcon#about to read 6, iclass 30, count 0 2006.225.08:09:18.18#ibcon#read 6, iclass 30, count 0 2006.225.08:09:18.18#ibcon#end of sib2, iclass 30, count 0 2006.225.08:09:18.18#ibcon#*after write, iclass 30, count 0 2006.225.08:09:18.18#ibcon#*before return 0, iclass 30, count 0 2006.225.08:09:18.18#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:09:18.18#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:09:18.18#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.08:09:18.18#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.08:09:18.18$vc4f8/valo=2,572.99 2006.225.08:09:18.18#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.08:09:18.18#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.08:09:18.18#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:18.18#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:09:18.18#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:09:18.18#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:09:18.18#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:09:18.18#ibcon#first serial, iclass 32, count 0 2006.225.08:09:18.18#ibcon#enter sib2, iclass 32, count 0 2006.225.08:09:18.18#ibcon#flushed, iclass 32, count 0 2006.225.08:09:18.18#ibcon#about to write, iclass 32, count 0 2006.225.08:09:18.18#ibcon#wrote, iclass 32, count 0 2006.225.08:09:18.18#ibcon#about to read 3, iclass 32, count 0 2006.225.08:09:18.21#ibcon#read 3, iclass 32, count 0 2006.225.08:09:18.21#ibcon#about to read 4, iclass 32, count 0 2006.225.08:09:18.21#ibcon#read 4, iclass 32, count 0 2006.225.08:09:18.21#ibcon#about to read 5, iclass 32, count 0 2006.225.08:09:18.21#ibcon#read 5, iclass 32, count 0 2006.225.08:09:18.21#ibcon#about to read 6, iclass 32, count 0 2006.225.08:09:18.21#ibcon#read 6, iclass 32, count 0 2006.225.08:09:18.21#ibcon#end of sib2, iclass 32, count 0 2006.225.08:09:18.21#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:09:18.21#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:09:18.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:09:18.21#ibcon#*before write, iclass 32, count 0 2006.225.08:09:18.21#ibcon#enter sib2, iclass 32, count 0 2006.225.08:09:18.21#ibcon#flushed, iclass 32, count 0 2006.225.08:09:18.21#ibcon#about to write, iclass 32, count 0 2006.225.08:09:18.21#ibcon#wrote, iclass 32, count 0 2006.225.08:09:18.21#ibcon#about to read 3, iclass 32, count 0 2006.225.08:09:18.24#ibcon#read 3, iclass 32, count 0 2006.225.08:09:18.24#ibcon#about to read 4, iclass 32, count 0 2006.225.08:09:18.24#ibcon#read 4, iclass 32, count 0 2006.225.08:09:18.24#ibcon#about to read 5, iclass 32, count 0 2006.225.08:09:18.24#ibcon#read 5, iclass 32, count 0 2006.225.08:09:18.24#ibcon#about to read 6, iclass 32, count 0 2006.225.08:09:18.24#ibcon#read 6, iclass 32, count 0 2006.225.08:09:18.24#ibcon#end of sib2, iclass 32, count 0 2006.225.08:09:18.24#ibcon#*after write, iclass 32, count 0 2006.225.08:09:18.24#ibcon#*before return 0, iclass 32, count 0 2006.225.08:09:18.24#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:09:18.24#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:09:18.24#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:09:18.24#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:09:18.24$vc4f8/va=2,7 2006.225.08:09:18.24#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.08:09:18.24#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.08:09:18.24#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:18.24#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:09:18.31#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:09:18.31#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:09:18.31#ibcon#enter wrdev, iclass 34, count 2 2006.225.08:09:18.31#ibcon#first serial, iclass 34, count 2 2006.225.08:09:18.31#ibcon#enter sib2, iclass 34, count 2 2006.225.08:09:18.31#ibcon#flushed, iclass 34, count 2 2006.225.08:09:18.31#ibcon#about to write, iclass 34, count 2 2006.225.08:09:18.31#ibcon#wrote, iclass 34, count 2 2006.225.08:09:18.31#ibcon#about to read 3, iclass 34, count 2 2006.225.08:09:18.32#ibcon#read 3, iclass 34, count 2 2006.225.08:09:18.32#ibcon#about to read 4, iclass 34, count 2 2006.225.08:09:18.32#ibcon#read 4, iclass 34, count 2 2006.225.08:09:18.32#ibcon#about to read 5, iclass 34, count 2 2006.225.08:09:18.32#ibcon#read 5, iclass 34, count 2 2006.225.08:09:18.32#ibcon#about to read 6, iclass 34, count 2 2006.225.08:09:18.32#ibcon#read 6, iclass 34, count 2 2006.225.08:09:18.32#ibcon#end of sib2, iclass 34, count 2 2006.225.08:09:18.32#ibcon#*mode == 0, iclass 34, count 2 2006.225.08:09:18.32#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.08:09:18.32#ibcon#[25=AT02-07\r\n] 2006.225.08:09:18.32#ibcon#*before write, iclass 34, count 2 2006.225.08:09:18.32#ibcon#enter sib2, iclass 34, count 2 2006.225.08:09:18.32#ibcon#flushed, iclass 34, count 2 2006.225.08:09:18.32#ibcon#about to write, iclass 34, count 2 2006.225.08:09:18.32#ibcon#wrote, iclass 34, count 2 2006.225.08:09:18.32#ibcon#about to read 3, iclass 34, count 2 2006.225.08:09:18.35#ibcon#read 3, iclass 34, count 2 2006.225.08:09:18.35#ibcon#about to read 4, iclass 34, count 2 2006.225.08:09:18.35#ibcon#read 4, iclass 34, count 2 2006.225.08:09:18.35#ibcon#about to read 5, iclass 34, count 2 2006.225.08:09:18.35#ibcon#read 5, iclass 34, count 2 2006.225.08:09:18.35#ibcon#about to read 6, iclass 34, count 2 2006.225.08:09:18.35#ibcon#read 6, iclass 34, count 2 2006.225.08:09:18.35#ibcon#end of sib2, iclass 34, count 2 2006.225.08:09:18.35#ibcon#*after write, iclass 34, count 2 2006.225.08:09:18.35#ibcon#*before return 0, iclass 34, count 2 2006.225.08:09:18.35#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:09:18.35#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:09:18.35#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.08:09:18.35#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:18.35#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:09:18.47#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:09:18.47#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:09:18.47#ibcon#enter wrdev, iclass 34, count 0 2006.225.08:09:18.47#ibcon#first serial, iclass 34, count 0 2006.225.08:09:18.47#ibcon#enter sib2, iclass 34, count 0 2006.225.08:09:18.47#ibcon#flushed, iclass 34, count 0 2006.225.08:09:18.47#ibcon#about to write, iclass 34, count 0 2006.225.08:09:18.47#ibcon#wrote, iclass 34, count 0 2006.225.08:09:18.47#ibcon#about to read 3, iclass 34, count 0 2006.225.08:09:18.49#ibcon#read 3, iclass 34, count 0 2006.225.08:09:18.49#ibcon#about to read 4, iclass 34, count 0 2006.225.08:09:18.49#ibcon#read 4, iclass 34, count 0 2006.225.08:09:18.49#ibcon#about to read 5, iclass 34, count 0 2006.225.08:09:18.49#ibcon#read 5, iclass 34, count 0 2006.225.08:09:18.49#ibcon#about to read 6, iclass 34, count 0 2006.225.08:09:18.49#ibcon#read 6, iclass 34, count 0 2006.225.08:09:18.49#ibcon#end of sib2, iclass 34, count 0 2006.225.08:09:18.49#ibcon#*mode == 0, iclass 34, count 0 2006.225.08:09:18.49#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.08:09:18.49#ibcon#[25=USB\r\n] 2006.225.08:09:18.49#ibcon#*before write, iclass 34, count 0 2006.225.08:09:18.49#ibcon#enter sib2, iclass 34, count 0 2006.225.08:09:18.49#ibcon#flushed, iclass 34, count 0 2006.225.08:09:18.49#ibcon#about to write, iclass 34, count 0 2006.225.08:09:18.49#ibcon#wrote, iclass 34, count 0 2006.225.08:09:18.49#ibcon#about to read 3, iclass 34, count 0 2006.225.08:09:18.52#ibcon#read 3, iclass 34, count 0 2006.225.08:09:18.52#ibcon#about to read 4, iclass 34, count 0 2006.225.08:09:18.52#ibcon#read 4, iclass 34, count 0 2006.225.08:09:18.52#ibcon#about to read 5, iclass 34, count 0 2006.225.08:09:18.52#ibcon#read 5, iclass 34, count 0 2006.225.08:09:18.52#ibcon#about to read 6, iclass 34, count 0 2006.225.08:09:18.52#ibcon#read 6, iclass 34, count 0 2006.225.08:09:18.52#ibcon#end of sib2, iclass 34, count 0 2006.225.08:09:18.52#ibcon#*after write, iclass 34, count 0 2006.225.08:09:18.52#ibcon#*before return 0, iclass 34, count 0 2006.225.08:09:18.52#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:09:18.52#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:09:18.52#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.08:09:18.52#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.08:09:18.52$vc4f8/valo=3,672.99 2006.225.08:09:18.52#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.08:09:18.52#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.08:09:18.52#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:18.52#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:09:18.52#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:09:18.52#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:09:18.52#ibcon#enter wrdev, iclass 36, count 0 2006.225.08:09:18.52#ibcon#first serial, iclass 36, count 0 2006.225.08:09:18.52#ibcon#enter sib2, iclass 36, count 0 2006.225.08:09:18.52#ibcon#flushed, iclass 36, count 0 2006.225.08:09:18.52#ibcon#about to write, iclass 36, count 0 2006.225.08:09:18.52#ibcon#wrote, iclass 36, count 0 2006.225.08:09:18.52#ibcon#about to read 3, iclass 36, count 0 2006.225.08:09:18.54#ibcon#read 3, iclass 36, count 0 2006.225.08:09:18.54#ibcon#about to read 4, iclass 36, count 0 2006.225.08:09:18.54#ibcon#read 4, iclass 36, count 0 2006.225.08:09:18.54#ibcon#about to read 5, iclass 36, count 0 2006.225.08:09:18.54#ibcon#read 5, iclass 36, count 0 2006.225.08:09:18.54#ibcon#about to read 6, iclass 36, count 0 2006.225.08:09:18.54#ibcon#read 6, iclass 36, count 0 2006.225.08:09:18.54#ibcon#end of sib2, iclass 36, count 0 2006.225.08:09:18.54#ibcon#*mode == 0, iclass 36, count 0 2006.225.08:09:18.54#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.08:09:18.54#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:09:18.54#ibcon#*before write, iclass 36, count 0 2006.225.08:09:18.54#ibcon#enter sib2, iclass 36, count 0 2006.225.08:09:18.54#ibcon#flushed, iclass 36, count 0 2006.225.08:09:18.54#ibcon#about to write, iclass 36, count 0 2006.225.08:09:18.54#ibcon#wrote, iclass 36, count 0 2006.225.08:09:18.54#ibcon#about to read 3, iclass 36, count 0 2006.225.08:09:18.58#ibcon#read 3, iclass 36, count 0 2006.225.08:09:18.58#ibcon#about to read 4, iclass 36, count 0 2006.225.08:09:18.58#ibcon#read 4, iclass 36, count 0 2006.225.08:09:18.58#ibcon#about to read 5, iclass 36, count 0 2006.225.08:09:18.58#ibcon#read 5, iclass 36, count 0 2006.225.08:09:18.58#ibcon#about to read 6, iclass 36, count 0 2006.225.08:09:18.58#ibcon#read 6, iclass 36, count 0 2006.225.08:09:18.58#ibcon#end of sib2, iclass 36, count 0 2006.225.08:09:18.58#ibcon#*after write, iclass 36, count 0 2006.225.08:09:18.58#ibcon#*before return 0, iclass 36, count 0 2006.225.08:09:18.58#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:09:18.58#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:09:18.58#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.08:09:18.58#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.08:09:18.58$vc4f8/va=3,6 2006.225.08:09:18.58#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.08:09:18.58#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.08:09:18.58#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:18.58#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:09:18.65#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:09:18.65#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:09:18.65#ibcon#enter wrdev, iclass 38, count 2 2006.225.08:09:18.65#ibcon#first serial, iclass 38, count 2 2006.225.08:09:18.65#ibcon#enter sib2, iclass 38, count 2 2006.225.08:09:18.65#ibcon#flushed, iclass 38, count 2 2006.225.08:09:18.65#ibcon#about to write, iclass 38, count 2 2006.225.08:09:18.65#ibcon#wrote, iclass 38, count 2 2006.225.08:09:18.65#ibcon#about to read 3, iclass 38, count 2 2006.225.08:09:18.66#ibcon#read 3, iclass 38, count 2 2006.225.08:09:18.66#ibcon#about to read 4, iclass 38, count 2 2006.225.08:09:18.66#ibcon#read 4, iclass 38, count 2 2006.225.08:09:18.66#ibcon#about to read 5, iclass 38, count 2 2006.225.08:09:18.66#ibcon#read 5, iclass 38, count 2 2006.225.08:09:18.66#ibcon#about to read 6, iclass 38, count 2 2006.225.08:09:18.66#ibcon#read 6, iclass 38, count 2 2006.225.08:09:18.66#ibcon#end of sib2, iclass 38, count 2 2006.225.08:09:18.66#ibcon#*mode == 0, iclass 38, count 2 2006.225.08:09:18.66#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.08:09:18.66#ibcon#[25=AT03-06\r\n] 2006.225.08:09:18.66#ibcon#*before write, iclass 38, count 2 2006.225.08:09:18.66#ibcon#enter sib2, iclass 38, count 2 2006.225.08:09:18.66#ibcon#flushed, iclass 38, count 2 2006.225.08:09:18.66#ibcon#about to write, iclass 38, count 2 2006.225.08:09:18.66#ibcon#wrote, iclass 38, count 2 2006.225.08:09:18.66#ibcon#about to read 3, iclass 38, count 2 2006.225.08:09:18.69#ibcon#read 3, iclass 38, count 2 2006.225.08:09:18.69#ibcon#about to read 4, iclass 38, count 2 2006.225.08:09:18.69#ibcon#read 4, iclass 38, count 2 2006.225.08:09:18.69#ibcon#about to read 5, iclass 38, count 2 2006.225.08:09:18.69#ibcon#read 5, iclass 38, count 2 2006.225.08:09:18.69#ibcon#about to read 6, iclass 38, count 2 2006.225.08:09:18.69#ibcon#read 6, iclass 38, count 2 2006.225.08:09:18.69#ibcon#end of sib2, iclass 38, count 2 2006.225.08:09:18.69#ibcon#*after write, iclass 38, count 2 2006.225.08:09:18.69#ibcon#*before return 0, iclass 38, count 2 2006.225.08:09:18.69#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:09:18.69#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:09:18.69#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.08:09:18.69#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:18.69#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:09:18.81#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:09:18.81#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:09:18.81#ibcon#enter wrdev, iclass 38, count 0 2006.225.08:09:18.81#ibcon#first serial, iclass 38, count 0 2006.225.08:09:18.81#ibcon#enter sib2, iclass 38, count 0 2006.225.08:09:18.81#ibcon#flushed, iclass 38, count 0 2006.225.08:09:18.81#ibcon#about to write, iclass 38, count 0 2006.225.08:09:18.81#ibcon#wrote, iclass 38, count 0 2006.225.08:09:18.81#ibcon#about to read 3, iclass 38, count 0 2006.225.08:09:18.83#ibcon#read 3, iclass 38, count 0 2006.225.08:09:18.83#ibcon#about to read 4, iclass 38, count 0 2006.225.08:09:18.83#ibcon#read 4, iclass 38, count 0 2006.225.08:09:18.83#ibcon#about to read 5, iclass 38, count 0 2006.225.08:09:18.83#ibcon#read 5, iclass 38, count 0 2006.225.08:09:18.83#ibcon#about to read 6, iclass 38, count 0 2006.225.08:09:18.83#ibcon#read 6, iclass 38, count 0 2006.225.08:09:18.83#ibcon#end of sib2, iclass 38, count 0 2006.225.08:09:18.83#ibcon#*mode == 0, iclass 38, count 0 2006.225.08:09:18.83#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.08:09:18.83#ibcon#[25=USB\r\n] 2006.225.08:09:18.83#ibcon#*before write, iclass 38, count 0 2006.225.08:09:18.83#ibcon#enter sib2, iclass 38, count 0 2006.225.08:09:18.83#ibcon#flushed, iclass 38, count 0 2006.225.08:09:18.83#ibcon#about to write, iclass 38, count 0 2006.225.08:09:18.83#ibcon#wrote, iclass 38, count 0 2006.225.08:09:18.83#ibcon#about to read 3, iclass 38, count 0 2006.225.08:09:18.86#ibcon#read 3, iclass 38, count 0 2006.225.08:09:18.86#ibcon#about to read 4, iclass 38, count 0 2006.225.08:09:18.86#ibcon#read 4, iclass 38, count 0 2006.225.08:09:18.86#ibcon#about to read 5, iclass 38, count 0 2006.225.08:09:18.86#ibcon#read 5, iclass 38, count 0 2006.225.08:09:18.86#ibcon#about to read 6, iclass 38, count 0 2006.225.08:09:18.86#ibcon#read 6, iclass 38, count 0 2006.225.08:09:18.86#ibcon#end of sib2, iclass 38, count 0 2006.225.08:09:18.86#ibcon#*after write, iclass 38, count 0 2006.225.08:09:18.86#ibcon#*before return 0, iclass 38, count 0 2006.225.08:09:18.86#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:09:18.86#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:09:18.86#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.08:09:18.86#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.08:09:18.86$vc4f8/valo=4,832.99 2006.225.08:09:18.86#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.08:09:18.86#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.08:09:18.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:18.86#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:09:18.86#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:09:18.86#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:09:18.86#ibcon#enter wrdev, iclass 40, count 0 2006.225.08:09:18.86#ibcon#first serial, iclass 40, count 0 2006.225.08:09:18.86#ibcon#enter sib2, iclass 40, count 0 2006.225.08:09:18.86#ibcon#flushed, iclass 40, count 0 2006.225.08:09:18.86#ibcon#about to write, iclass 40, count 0 2006.225.08:09:18.86#ibcon#wrote, iclass 40, count 0 2006.225.08:09:18.86#ibcon#about to read 3, iclass 40, count 0 2006.225.08:09:18.88#ibcon#read 3, iclass 40, count 0 2006.225.08:09:18.88#ibcon#about to read 4, iclass 40, count 0 2006.225.08:09:18.88#ibcon#read 4, iclass 40, count 0 2006.225.08:09:18.88#ibcon#about to read 5, iclass 40, count 0 2006.225.08:09:18.88#ibcon#read 5, iclass 40, count 0 2006.225.08:09:18.88#ibcon#about to read 6, iclass 40, count 0 2006.225.08:09:18.88#ibcon#read 6, iclass 40, count 0 2006.225.08:09:18.88#ibcon#end of sib2, iclass 40, count 0 2006.225.08:09:18.88#ibcon#*mode == 0, iclass 40, count 0 2006.225.08:09:18.88#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.08:09:18.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:09:18.88#ibcon#*before write, iclass 40, count 0 2006.225.08:09:18.88#ibcon#enter sib2, iclass 40, count 0 2006.225.08:09:18.88#ibcon#flushed, iclass 40, count 0 2006.225.08:09:18.88#ibcon#about to write, iclass 40, count 0 2006.225.08:09:18.88#ibcon#wrote, iclass 40, count 0 2006.225.08:09:18.88#ibcon#about to read 3, iclass 40, count 0 2006.225.08:09:18.92#ibcon#read 3, iclass 40, count 0 2006.225.08:09:18.92#ibcon#about to read 4, iclass 40, count 0 2006.225.08:09:18.92#ibcon#read 4, iclass 40, count 0 2006.225.08:09:18.92#ibcon#about to read 5, iclass 40, count 0 2006.225.08:09:18.92#ibcon#read 5, iclass 40, count 0 2006.225.08:09:18.92#ibcon#about to read 6, iclass 40, count 0 2006.225.08:09:18.92#ibcon#read 6, iclass 40, count 0 2006.225.08:09:18.92#ibcon#end of sib2, iclass 40, count 0 2006.225.08:09:18.92#ibcon#*after write, iclass 40, count 0 2006.225.08:09:18.92#ibcon#*before return 0, iclass 40, count 0 2006.225.08:09:18.92#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:09:18.92#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:09:18.92#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.08:09:18.92#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.08:09:18.92$vc4f8/va=4,7 2006.225.08:09:18.92#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.08:09:18.92#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.08:09:18.92#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:18.92#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:09:18.99#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:09:18.99#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:09:18.99#ibcon#enter wrdev, iclass 4, count 2 2006.225.08:09:18.99#ibcon#first serial, iclass 4, count 2 2006.225.08:09:18.99#ibcon#enter sib2, iclass 4, count 2 2006.225.08:09:18.99#ibcon#flushed, iclass 4, count 2 2006.225.08:09:18.99#ibcon#about to write, iclass 4, count 2 2006.225.08:09:18.99#ibcon#wrote, iclass 4, count 2 2006.225.08:09:18.99#ibcon#about to read 3, iclass 4, count 2 2006.225.08:09:19.00#ibcon#read 3, iclass 4, count 2 2006.225.08:09:19.00#ibcon#about to read 4, iclass 4, count 2 2006.225.08:09:19.00#ibcon#read 4, iclass 4, count 2 2006.225.08:09:19.00#ibcon#about to read 5, iclass 4, count 2 2006.225.08:09:19.00#ibcon#read 5, iclass 4, count 2 2006.225.08:09:19.00#ibcon#about to read 6, iclass 4, count 2 2006.225.08:09:19.00#ibcon#read 6, iclass 4, count 2 2006.225.08:09:19.00#ibcon#end of sib2, iclass 4, count 2 2006.225.08:09:19.00#ibcon#*mode == 0, iclass 4, count 2 2006.225.08:09:19.00#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.08:09:19.00#ibcon#[25=AT04-07\r\n] 2006.225.08:09:19.00#ibcon#*before write, iclass 4, count 2 2006.225.08:09:19.00#ibcon#enter sib2, iclass 4, count 2 2006.225.08:09:19.00#ibcon#flushed, iclass 4, count 2 2006.225.08:09:19.00#ibcon#about to write, iclass 4, count 2 2006.225.08:09:19.00#ibcon#wrote, iclass 4, count 2 2006.225.08:09:19.00#ibcon#about to read 3, iclass 4, count 2 2006.225.08:09:19.03#ibcon#read 3, iclass 4, count 2 2006.225.08:09:19.03#ibcon#about to read 4, iclass 4, count 2 2006.225.08:09:19.03#ibcon#read 4, iclass 4, count 2 2006.225.08:09:19.03#ibcon#about to read 5, iclass 4, count 2 2006.225.08:09:19.03#ibcon#read 5, iclass 4, count 2 2006.225.08:09:19.03#ibcon#about to read 6, iclass 4, count 2 2006.225.08:09:19.03#ibcon#read 6, iclass 4, count 2 2006.225.08:09:19.03#ibcon#end of sib2, iclass 4, count 2 2006.225.08:09:19.03#ibcon#*after write, iclass 4, count 2 2006.225.08:09:19.03#ibcon#*before return 0, iclass 4, count 2 2006.225.08:09:19.03#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:09:19.03#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:09:19.03#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.08:09:19.03#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:19.03#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:09:19.15#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:09:19.15#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:09:19.15#ibcon#enter wrdev, iclass 4, count 0 2006.225.08:09:19.15#ibcon#first serial, iclass 4, count 0 2006.225.08:09:19.15#ibcon#enter sib2, iclass 4, count 0 2006.225.08:09:19.15#ibcon#flushed, iclass 4, count 0 2006.225.08:09:19.15#ibcon#about to write, iclass 4, count 0 2006.225.08:09:19.15#ibcon#wrote, iclass 4, count 0 2006.225.08:09:19.15#ibcon#about to read 3, iclass 4, count 0 2006.225.08:09:19.17#ibcon#read 3, iclass 4, count 0 2006.225.08:09:19.17#ibcon#about to read 4, iclass 4, count 0 2006.225.08:09:19.17#ibcon#read 4, iclass 4, count 0 2006.225.08:09:19.17#ibcon#about to read 5, iclass 4, count 0 2006.225.08:09:19.17#ibcon#read 5, iclass 4, count 0 2006.225.08:09:19.17#ibcon#about to read 6, iclass 4, count 0 2006.225.08:09:19.17#ibcon#read 6, iclass 4, count 0 2006.225.08:09:19.17#ibcon#end of sib2, iclass 4, count 0 2006.225.08:09:19.17#ibcon#*mode == 0, iclass 4, count 0 2006.225.08:09:19.17#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.08:09:19.17#ibcon#[25=USB\r\n] 2006.225.08:09:19.17#ibcon#*before write, iclass 4, count 0 2006.225.08:09:19.17#ibcon#enter sib2, iclass 4, count 0 2006.225.08:09:19.17#ibcon#flushed, iclass 4, count 0 2006.225.08:09:19.17#ibcon#about to write, iclass 4, count 0 2006.225.08:09:19.17#ibcon#wrote, iclass 4, count 0 2006.225.08:09:19.17#ibcon#about to read 3, iclass 4, count 0 2006.225.08:09:19.20#ibcon#read 3, iclass 4, count 0 2006.225.08:09:19.20#ibcon#about to read 4, iclass 4, count 0 2006.225.08:09:19.20#ibcon#read 4, iclass 4, count 0 2006.225.08:09:19.20#ibcon#about to read 5, iclass 4, count 0 2006.225.08:09:19.20#ibcon#read 5, iclass 4, count 0 2006.225.08:09:19.20#ibcon#about to read 6, iclass 4, count 0 2006.225.08:09:19.20#ibcon#read 6, iclass 4, count 0 2006.225.08:09:19.20#ibcon#end of sib2, iclass 4, count 0 2006.225.08:09:19.20#ibcon#*after write, iclass 4, count 0 2006.225.08:09:19.20#ibcon#*before return 0, iclass 4, count 0 2006.225.08:09:19.20#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:09:19.20#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:09:19.20#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.08:09:19.20#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.08:09:19.20$vc4f8/valo=5,652.99 2006.225.08:09:19.20#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.08:09:19.20#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.08:09:19.20#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:19.20#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:09:19.20#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:09:19.20#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:09:19.20#ibcon#enter wrdev, iclass 6, count 0 2006.225.08:09:19.20#ibcon#first serial, iclass 6, count 0 2006.225.08:09:19.20#ibcon#enter sib2, iclass 6, count 0 2006.225.08:09:19.20#ibcon#flushed, iclass 6, count 0 2006.225.08:09:19.20#ibcon#about to write, iclass 6, count 0 2006.225.08:09:19.20#ibcon#wrote, iclass 6, count 0 2006.225.08:09:19.20#ibcon#about to read 3, iclass 6, count 0 2006.225.08:09:19.22#ibcon#read 3, iclass 6, count 0 2006.225.08:09:19.22#ibcon#about to read 4, iclass 6, count 0 2006.225.08:09:19.22#ibcon#read 4, iclass 6, count 0 2006.225.08:09:19.22#ibcon#about to read 5, iclass 6, count 0 2006.225.08:09:19.22#ibcon#read 5, iclass 6, count 0 2006.225.08:09:19.22#ibcon#about to read 6, iclass 6, count 0 2006.225.08:09:19.22#ibcon#read 6, iclass 6, count 0 2006.225.08:09:19.22#ibcon#end of sib2, iclass 6, count 0 2006.225.08:09:19.22#ibcon#*mode == 0, iclass 6, count 0 2006.225.08:09:19.22#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.08:09:19.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:09:19.22#ibcon#*before write, iclass 6, count 0 2006.225.08:09:19.22#ibcon#enter sib2, iclass 6, count 0 2006.225.08:09:19.22#ibcon#flushed, iclass 6, count 0 2006.225.08:09:19.22#ibcon#about to write, iclass 6, count 0 2006.225.08:09:19.22#ibcon#wrote, iclass 6, count 0 2006.225.08:09:19.22#ibcon#about to read 3, iclass 6, count 0 2006.225.08:09:19.26#ibcon#read 3, iclass 6, count 0 2006.225.08:09:19.26#ibcon#about to read 4, iclass 6, count 0 2006.225.08:09:19.26#ibcon#read 4, iclass 6, count 0 2006.225.08:09:19.26#ibcon#about to read 5, iclass 6, count 0 2006.225.08:09:19.26#ibcon#read 5, iclass 6, count 0 2006.225.08:09:19.26#ibcon#about to read 6, iclass 6, count 0 2006.225.08:09:19.26#ibcon#read 6, iclass 6, count 0 2006.225.08:09:19.26#ibcon#end of sib2, iclass 6, count 0 2006.225.08:09:19.26#ibcon#*after write, iclass 6, count 0 2006.225.08:09:19.26#ibcon#*before return 0, iclass 6, count 0 2006.225.08:09:19.26#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:09:19.26#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:09:19.26#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.08:09:19.26#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.08:09:19.26$vc4f8/va=5,7 2006.225.08:09:19.26#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.225.08:09:19.26#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.225.08:09:19.26#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:19.26#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:09:19.32#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:09:19.32#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:09:19.32#ibcon#enter wrdev, iclass 10, count 2 2006.225.08:09:19.32#ibcon#first serial, iclass 10, count 2 2006.225.08:09:19.32#ibcon#enter sib2, iclass 10, count 2 2006.225.08:09:19.32#ibcon#flushed, iclass 10, count 2 2006.225.08:09:19.32#ibcon#about to write, iclass 10, count 2 2006.225.08:09:19.32#ibcon#wrote, iclass 10, count 2 2006.225.08:09:19.32#ibcon#about to read 3, iclass 10, count 2 2006.225.08:09:19.34#ibcon#read 3, iclass 10, count 2 2006.225.08:09:19.34#ibcon#about to read 4, iclass 10, count 2 2006.225.08:09:19.34#ibcon#read 4, iclass 10, count 2 2006.225.08:09:19.34#ibcon#about to read 5, iclass 10, count 2 2006.225.08:09:19.34#ibcon#read 5, iclass 10, count 2 2006.225.08:09:19.34#ibcon#about to read 6, iclass 10, count 2 2006.225.08:09:19.34#ibcon#read 6, iclass 10, count 2 2006.225.08:09:19.34#ibcon#end of sib2, iclass 10, count 2 2006.225.08:09:19.34#ibcon#*mode == 0, iclass 10, count 2 2006.225.08:09:19.34#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.225.08:09:19.34#ibcon#[25=AT05-07\r\n] 2006.225.08:09:19.34#ibcon#*before write, iclass 10, count 2 2006.225.08:09:19.34#ibcon#enter sib2, iclass 10, count 2 2006.225.08:09:19.34#ibcon#flushed, iclass 10, count 2 2006.225.08:09:19.34#ibcon#about to write, iclass 10, count 2 2006.225.08:09:19.34#ibcon#wrote, iclass 10, count 2 2006.225.08:09:19.34#ibcon#about to read 3, iclass 10, count 2 2006.225.08:09:19.38#ibcon#read 3, iclass 10, count 2 2006.225.08:09:19.38#ibcon#about to read 4, iclass 10, count 2 2006.225.08:09:19.38#ibcon#read 4, iclass 10, count 2 2006.225.08:09:19.38#ibcon#about to read 5, iclass 10, count 2 2006.225.08:09:19.38#ibcon#read 5, iclass 10, count 2 2006.225.08:09:19.38#ibcon#about to read 6, iclass 10, count 2 2006.225.08:09:19.38#ibcon#read 6, iclass 10, count 2 2006.225.08:09:19.38#ibcon#end of sib2, iclass 10, count 2 2006.225.08:09:19.38#ibcon#*after write, iclass 10, count 2 2006.225.08:09:19.38#ibcon#*before return 0, iclass 10, count 2 2006.225.08:09:19.38#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:09:19.38#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:09:19.38#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.225.08:09:19.38#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:19.38#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:09:19.49#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:09:19.49#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:09:19.49#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:09:19.49#ibcon#first serial, iclass 10, count 0 2006.225.08:09:19.49#ibcon#enter sib2, iclass 10, count 0 2006.225.08:09:19.49#ibcon#flushed, iclass 10, count 0 2006.225.08:09:19.50#ibcon#about to write, iclass 10, count 0 2006.225.08:09:19.50#ibcon#wrote, iclass 10, count 0 2006.225.08:09:19.50#ibcon#about to read 3, iclass 10, count 0 2006.225.08:09:19.51#ibcon#read 3, iclass 10, count 0 2006.225.08:09:19.51#ibcon#about to read 4, iclass 10, count 0 2006.225.08:09:19.51#ibcon#read 4, iclass 10, count 0 2006.225.08:09:19.51#ibcon#about to read 5, iclass 10, count 0 2006.225.08:09:19.51#ibcon#read 5, iclass 10, count 0 2006.225.08:09:19.51#ibcon#about to read 6, iclass 10, count 0 2006.225.08:09:19.51#ibcon#read 6, iclass 10, count 0 2006.225.08:09:19.51#ibcon#end of sib2, iclass 10, count 0 2006.225.08:09:19.51#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:09:19.51#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:09:19.51#ibcon#[25=USB\r\n] 2006.225.08:09:19.51#ibcon#*before write, iclass 10, count 0 2006.225.08:09:19.51#ibcon#enter sib2, iclass 10, count 0 2006.225.08:09:19.51#ibcon#flushed, iclass 10, count 0 2006.225.08:09:19.51#ibcon#about to write, iclass 10, count 0 2006.225.08:09:19.51#ibcon#wrote, iclass 10, count 0 2006.225.08:09:19.51#ibcon#about to read 3, iclass 10, count 0 2006.225.08:09:19.54#ibcon#read 3, iclass 10, count 0 2006.225.08:09:19.54#ibcon#about to read 4, iclass 10, count 0 2006.225.08:09:19.54#ibcon#read 4, iclass 10, count 0 2006.225.08:09:19.54#ibcon#about to read 5, iclass 10, count 0 2006.225.08:09:19.54#ibcon#read 5, iclass 10, count 0 2006.225.08:09:19.54#ibcon#about to read 6, iclass 10, count 0 2006.225.08:09:19.54#ibcon#read 6, iclass 10, count 0 2006.225.08:09:19.54#ibcon#end of sib2, iclass 10, count 0 2006.225.08:09:19.54#ibcon#*after write, iclass 10, count 0 2006.225.08:09:19.54#ibcon#*before return 0, iclass 10, count 0 2006.225.08:09:19.54#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:09:19.54#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:09:19.54#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:09:19.54#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:09:19.54$vc4f8/valo=6,772.99 2006.225.08:09:19.54#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.08:09:19.54#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.08:09:19.54#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:19.54#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:09:19.54#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:09:19.54#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:09:19.54#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:09:19.54#ibcon#first serial, iclass 12, count 0 2006.225.08:09:19.54#ibcon#enter sib2, iclass 12, count 0 2006.225.08:09:19.54#ibcon#flushed, iclass 12, count 0 2006.225.08:09:19.54#ibcon#about to write, iclass 12, count 0 2006.225.08:09:19.54#ibcon#wrote, iclass 12, count 0 2006.225.08:09:19.54#ibcon#about to read 3, iclass 12, count 0 2006.225.08:09:19.57#ibcon#read 3, iclass 12, count 0 2006.225.08:09:19.57#ibcon#about to read 4, iclass 12, count 0 2006.225.08:09:19.57#ibcon#read 4, iclass 12, count 0 2006.225.08:09:19.57#ibcon#about to read 5, iclass 12, count 0 2006.225.08:09:19.57#ibcon#read 5, iclass 12, count 0 2006.225.08:09:19.57#ibcon#about to read 6, iclass 12, count 0 2006.225.08:09:19.57#ibcon#read 6, iclass 12, count 0 2006.225.08:09:19.57#ibcon#end of sib2, iclass 12, count 0 2006.225.08:09:19.57#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:09:19.57#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:09:19.57#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:09:19.57#ibcon#*before write, iclass 12, count 0 2006.225.08:09:19.57#ibcon#enter sib2, iclass 12, count 0 2006.225.08:09:19.57#ibcon#flushed, iclass 12, count 0 2006.225.08:09:19.57#ibcon#about to write, iclass 12, count 0 2006.225.08:09:19.57#ibcon#wrote, iclass 12, count 0 2006.225.08:09:19.57#ibcon#about to read 3, iclass 12, count 0 2006.225.08:09:19.61#ibcon#read 3, iclass 12, count 0 2006.225.08:09:19.61#ibcon#about to read 4, iclass 12, count 0 2006.225.08:09:19.61#ibcon#read 4, iclass 12, count 0 2006.225.08:09:19.61#ibcon#about to read 5, iclass 12, count 0 2006.225.08:09:19.61#ibcon#read 5, iclass 12, count 0 2006.225.08:09:19.61#ibcon#about to read 6, iclass 12, count 0 2006.225.08:09:19.61#ibcon#read 6, iclass 12, count 0 2006.225.08:09:19.61#ibcon#end of sib2, iclass 12, count 0 2006.225.08:09:19.61#ibcon#*after write, iclass 12, count 0 2006.225.08:09:19.61#ibcon#*before return 0, iclass 12, count 0 2006.225.08:09:19.61#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:09:19.61#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:09:19.61#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:09:19.61#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:09:19.61$vc4f8/va=6,6 2006.225.08:09:19.61#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.225.08:09:19.61#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.225.08:09:19.61#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:19.61#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:09:19.66#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:09:19.66#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:09:19.66#ibcon#enter wrdev, iclass 14, count 2 2006.225.08:09:19.66#ibcon#first serial, iclass 14, count 2 2006.225.08:09:19.66#ibcon#enter sib2, iclass 14, count 2 2006.225.08:09:19.66#ibcon#flushed, iclass 14, count 2 2006.225.08:09:19.66#ibcon#about to write, iclass 14, count 2 2006.225.08:09:19.66#ibcon#wrote, iclass 14, count 2 2006.225.08:09:19.66#ibcon#about to read 3, iclass 14, count 2 2006.225.08:09:19.68#ibcon#read 3, iclass 14, count 2 2006.225.08:09:19.68#ibcon#about to read 4, iclass 14, count 2 2006.225.08:09:19.68#ibcon#read 4, iclass 14, count 2 2006.225.08:09:19.68#ibcon#about to read 5, iclass 14, count 2 2006.225.08:09:19.68#ibcon#read 5, iclass 14, count 2 2006.225.08:09:19.68#ibcon#about to read 6, iclass 14, count 2 2006.225.08:09:19.68#ibcon#read 6, iclass 14, count 2 2006.225.08:09:19.68#ibcon#end of sib2, iclass 14, count 2 2006.225.08:09:19.68#ibcon#*mode == 0, iclass 14, count 2 2006.225.08:09:19.68#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.225.08:09:19.68#ibcon#[25=AT06-06\r\n] 2006.225.08:09:19.68#ibcon#*before write, iclass 14, count 2 2006.225.08:09:19.68#ibcon#enter sib2, iclass 14, count 2 2006.225.08:09:19.68#ibcon#flushed, iclass 14, count 2 2006.225.08:09:19.68#ibcon#about to write, iclass 14, count 2 2006.225.08:09:19.68#ibcon#wrote, iclass 14, count 2 2006.225.08:09:19.68#ibcon#about to read 3, iclass 14, count 2 2006.225.08:09:19.71#ibcon#read 3, iclass 14, count 2 2006.225.08:09:19.71#ibcon#about to read 4, iclass 14, count 2 2006.225.08:09:19.71#ibcon#read 4, iclass 14, count 2 2006.225.08:09:19.71#ibcon#about to read 5, iclass 14, count 2 2006.225.08:09:19.71#ibcon#read 5, iclass 14, count 2 2006.225.08:09:19.71#ibcon#about to read 6, iclass 14, count 2 2006.225.08:09:19.71#ibcon#read 6, iclass 14, count 2 2006.225.08:09:19.71#ibcon#end of sib2, iclass 14, count 2 2006.225.08:09:19.71#ibcon#*after write, iclass 14, count 2 2006.225.08:09:19.71#ibcon#*before return 0, iclass 14, count 2 2006.225.08:09:19.71#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:09:19.71#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:09:19.71#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.225.08:09:19.71#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:19.71#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:09:19.83#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:09:19.83#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:09:19.83#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:09:19.83#ibcon#first serial, iclass 14, count 0 2006.225.08:09:19.83#ibcon#enter sib2, iclass 14, count 0 2006.225.08:09:19.83#ibcon#flushed, iclass 14, count 0 2006.225.08:09:19.83#ibcon#about to write, iclass 14, count 0 2006.225.08:09:19.83#ibcon#wrote, iclass 14, count 0 2006.225.08:09:19.83#ibcon#about to read 3, iclass 14, count 0 2006.225.08:09:19.85#ibcon#read 3, iclass 14, count 0 2006.225.08:09:19.85#ibcon#about to read 4, iclass 14, count 0 2006.225.08:09:19.85#ibcon#read 4, iclass 14, count 0 2006.225.08:09:19.85#ibcon#about to read 5, iclass 14, count 0 2006.225.08:09:19.85#ibcon#read 5, iclass 14, count 0 2006.225.08:09:19.85#ibcon#about to read 6, iclass 14, count 0 2006.225.08:09:19.85#ibcon#read 6, iclass 14, count 0 2006.225.08:09:19.85#ibcon#end of sib2, iclass 14, count 0 2006.225.08:09:19.85#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:09:19.85#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:09:19.85#ibcon#[25=USB\r\n] 2006.225.08:09:19.85#ibcon#*before write, iclass 14, count 0 2006.225.08:09:19.85#ibcon#enter sib2, iclass 14, count 0 2006.225.08:09:19.85#ibcon#flushed, iclass 14, count 0 2006.225.08:09:19.85#ibcon#about to write, iclass 14, count 0 2006.225.08:09:19.85#ibcon#wrote, iclass 14, count 0 2006.225.08:09:19.85#ibcon#about to read 3, iclass 14, count 0 2006.225.08:09:19.88#ibcon#read 3, iclass 14, count 0 2006.225.08:09:19.88#ibcon#about to read 4, iclass 14, count 0 2006.225.08:09:19.88#ibcon#read 4, iclass 14, count 0 2006.225.08:09:19.88#ibcon#about to read 5, iclass 14, count 0 2006.225.08:09:19.88#ibcon#read 5, iclass 14, count 0 2006.225.08:09:19.88#ibcon#about to read 6, iclass 14, count 0 2006.225.08:09:19.88#ibcon#read 6, iclass 14, count 0 2006.225.08:09:19.88#ibcon#end of sib2, iclass 14, count 0 2006.225.08:09:19.88#ibcon#*after write, iclass 14, count 0 2006.225.08:09:19.88#ibcon#*before return 0, iclass 14, count 0 2006.225.08:09:19.88#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:09:19.88#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:09:19.88#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:09:19.88#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:09:19.88$vc4f8/valo=7,832.99 2006.225.08:09:19.88#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.08:09:19.88#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.08:09:19.88#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:19.88#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:09:19.88#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:09:19.88#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:09:19.88#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:09:19.88#ibcon#first serial, iclass 16, count 0 2006.225.08:09:19.88#ibcon#enter sib2, iclass 16, count 0 2006.225.08:09:19.88#ibcon#flushed, iclass 16, count 0 2006.225.08:09:19.88#ibcon#about to write, iclass 16, count 0 2006.225.08:09:19.88#ibcon#wrote, iclass 16, count 0 2006.225.08:09:19.88#ibcon#about to read 3, iclass 16, count 0 2006.225.08:09:19.90#ibcon#read 3, iclass 16, count 0 2006.225.08:09:19.90#ibcon#about to read 4, iclass 16, count 0 2006.225.08:09:19.90#ibcon#read 4, iclass 16, count 0 2006.225.08:09:19.90#ibcon#about to read 5, iclass 16, count 0 2006.225.08:09:19.90#ibcon#read 5, iclass 16, count 0 2006.225.08:09:19.90#ibcon#about to read 6, iclass 16, count 0 2006.225.08:09:19.90#ibcon#read 6, iclass 16, count 0 2006.225.08:09:19.90#ibcon#end of sib2, iclass 16, count 0 2006.225.08:09:19.90#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:09:19.90#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:09:19.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:09:19.90#ibcon#*before write, iclass 16, count 0 2006.225.08:09:19.90#ibcon#enter sib2, iclass 16, count 0 2006.225.08:09:19.90#ibcon#flushed, iclass 16, count 0 2006.225.08:09:19.90#ibcon#about to write, iclass 16, count 0 2006.225.08:09:19.90#ibcon#wrote, iclass 16, count 0 2006.225.08:09:19.90#ibcon#about to read 3, iclass 16, count 0 2006.225.08:09:19.94#ibcon#read 3, iclass 16, count 0 2006.225.08:09:19.94#ibcon#about to read 4, iclass 16, count 0 2006.225.08:09:19.94#ibcon#read 4, iclass 16, count 0 2006.225.08:09:19.94#ibcon#about to read 5, iclass 16, count 0 2006.225.08:09:19.94#ibcon#read 5, iclass 16, count 0 2006.225.08:09:19.94#ibcon#about to read 6, iclass 16, count 0 2006.225.08:09:19.94#ibcon#read 6, iclass 16, count 0 2006.225.08:09:19.94#ibcon#end of sib2, iclass 16, count 0 2006.225.08:09:19.94#ibcon#*after write, iclass 16, count 0 2006.225.08:09:19.94#ibcon#*before return 0, iclass 16, count 0 2006.225.08:09:19.94#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:09:19.94#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:09:19.94#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:09:19.94#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:09:19.94$vc4f8/va=7,6 2006.225.08:09:19.94#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.225.08:09:19.94#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.225.08:09:19.94#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:19.94#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:09:20.00#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:09:20.00#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:09:20.00#ibcon#enter wrdev, iclass 18, count 2 2006.225.08:09:20.00#ibcon#first serial, iclass 18, count 2 2006.225.08:09:20.00#ibcon#enter sib2, iclass 18, count 2 2006.225.08:09:20.00#ibcon#flushed, iclass 18, count 2 2006.225.08:09:20.00#ibcon#about to write, iclass 18, count 2 2006.225.08:09:20.00#ibcon#wrote, iclass 18, count 2 2006.225.08:09:20.00#ibcon#about to read 3, iclass 18, count 2 2006.225.08:09:20.02#ibcon#read 3, iclass 18, count 2 2006.225.08:09:20.02#ibcon#about to read 4, iclass 18, count 2 2006.225.08:09:20.02#ibcon#read 4, iclass 18, count 2 2006.225.08:09:20.02#ibcon#about to read 5, iclass 18, count 2 2006.225.08:09:20.02#ibcon#read 5, iclass 18, count 2 2006.225.08:09:20.02#ibcon#about to read 6, iclass 18, count 2 2006.225.08:09:20.02#ibcon#read 6, iclass 18, count 2 2006.225.08:09:20.02#ibcon#end of sib2, iclass 18, count 2 2006.225.08:09:20.02#ibcon#*mode == 0, iclass 18, count 2 2006.225.08:09:20.02#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.225.08:09:20.02#ibcon#[25=AT07-06\r\n] 2006.225.08:09:20.02#ibcon#*before write, iclass 18, count 2 2006.225.08:09:20.02#ibcon#enter sib2, iclass 18, count 2 2006.225.08:09:20.02#ibcon#flushed, iclass 18, count 2 2006.225.08:09:20.02#ibcon#about to write, iclass 18, count 2 2006.225.08:09:20.02#ibcon#wrote, iclass 18, count 2 2006.225.08:09:20.02#ibcon#about to read 3, iclass 18, count 2 2006.225.08:09:20.05#ibcon#read 3, iclass 18, count 2 2006.225.08:09:20.05#ibcon#about to read 4, iclass 18, count 2 2006.225.08:09:20.05#ibcon#read 4, iclass 18, count 2 2006.225.08:09:20.05#ibcon#about to read 5, iclass 18, count 2 2006.225.08:09:20.05#ibcon#read 5, iclass 18, count 2 2006.225.08:09:20.05#ibcon#about to read 6, iclass 18, count 2 2006.225.08:09:20.05#ibcon#read 6, iclass 18, count 2 2006.225.08:09:20.05#ibcon#end of sib2, iclass 18, count 2 2006.225.08:09:20.05#ibcon#*after write, iclass 18, count 2 2006.225.08:09:20.05#ibcon#*before return 0, iclass 18, count 2 2006.225.08:09:20.05#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:09:20.05#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:09:20.05#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.225.08:09:20.05#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:20.05#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:09:20.17#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:09:20.17#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:09:20.17#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:09:20.17#ibcon#first serial, iclass 18, count 0 2006.225.08:09:20.17#ibcon#enter sib2, iclass 18, count 0 2006.225.08:09:20.17#ibcon#flushed, iclass 18, count 0 2006.225.08:09:20.17#ibcon#about to write, iclass 18, count 0 2006.225.08:09:20.17#ibcon#wrote, iclass 18, count 0 2006.225.08:09:20.17#ibcon#about to read 3, iclass 18, count 0 2006.225.08:09:20.19#ibcon#read 3, iclass 18, count 0 2006.225.08:09:20.19#ibcon#about to read 4, iclass 18, count 0 2006.225.08:09:20.19#ibcon#read 4, iclass 18, count 0 2006.225.08:09:20.19#ibcon#about to read 5, iclass 18, count 0 2006.225.08:09:20.19#ibcon#read 5, iclass 18, count 0 2006.225.08:09:20.19#ibcon#about to read 6, iclass 18, count 0 2006.225.08:09:20.19#ibcon#read 6, iclass 18, count 0 2006.225.08:09:20.19#ibcon#end of sib2, iclass 18, count 0 2006.225.08:09:20.19#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:09:20.19#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:09:20.19#ibcon#[25=USB\r\n] 2006.225.08:09:20.19#ibcon#*before write, iclass 18, count 0 2006.225.08:09:20.19#ibcon#enter sib2, iclass 18, count 0 2006.225.08:09:20.19#ibcon#flushed, iclass 18, count 0 2006.225.08:09:20.19#ibcon#about to write, iclass 18, count 0 2006.225.08:09:20.19#ibcon#wrote, iclass 18, count 0 2006.225.08:09:20.19#ibcon#about to read 3, iclass 18, count 0 2006.225.08:09:20.22#ibcon#read 3, iclass 18, count 0 2006.225.08:09:20.22#ibcon#about to read 4, iclass 18, count 0 2006.225.08:09:20.22#ibcon#read 4, iclass 18, count 0 2006.225.08:09:20.22#ibcon#about to read 5, iclass 18, count 0 2006.225.08:09:20.22#ibcon#read 5, iclass 18, count 0 2006.225.08:09:20.22#ibcon#about to read 6, iclass 18, count 0 2006.225.08:09:20.22#ibcon#read 6, iclass 18, count 0 2006.225.08:09:20.22#ibcon#end of sib2, iclass 18, count 0 2006.225.08:09:20.22#ibcon#*after write, iclass 18, count 0 2006.225.08:09:20.22#ibcon#*before return 0, iclass 18, count 0 2006.225.08:09:20.22#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:09:20.22#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:09:20.22#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:09:20.22#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:09:20.22$vc4f8/valo=8,852.99 2006.225.08:09:20.22#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.225.08:09:20.22#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.225.08:09:20.22#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:20.22#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:09:20.22#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:09:20.22#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:09:20.22#ibcon#enter wrdev, iclass 20, count 0 2006.225.08:09:20.22#ibcon#first serial, iclass 20, count 0 2006.225.08:09:20.22#ibcon#enter sib2, iclass 20, count 0 2006.225.08:09:20.22#ibcon#flushed, iclass 20, count 0 2006.225.08:09:20.22#ibcon#about to write, iclass 20, count 0 2006.225.08:09:20.22#ibcon#wrote, iclass 20, count 0 2006.225.08:09:20.22#ibcon#about to read 3, iclass 20, count 0 2006.225.08:09:20.24#ibcon#read 3, iclass 20, count 0 2006.225.08:09:20.24#ibcon#about to read 4, iclass 20, count 0 2006.225.08:09:20.24#ibcon#read 4, iclass 20, count 0 2006.225.08:09:20.24#ibcon#about to read 5, iclass 20, count 0 2006.225.08:09:20.24#ibcon#read 5, iclass 20, count 0 2006.225.08:09:20.24#ibcon#about to read 6, iclass 20, count 0 2006.225.08:09:20.24#ibcon#read 6, iclass 20, count 0 2006.225.08:09:20.24#ibcon#end of sib2, iclass 20, count 0 2006.225.08:09:20.24#ibcon#*mode == 0, iclass 20, count 0 2006.225.08:09:20.24#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.08:09:20.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:09:20.24#ibcon#*before write, iclass 20, count 0 2006.225.08:09:20.24#ibcon#enter sib2, iclass 20, count 0 2006.225.08:09:20.24#ibcon#flushed, iclass 20, count 0 2006.225.08:09:20.24#ibcon#about to write, iclass 20, count 0 2006.225.08:09:20.24#ibcon#wrote, iclass 20, count 0 2006.225.08:09:20.24#ibcon#about to read 3, iclass 20, count 0 2006.225.08:09:20.28#ibcon#read 3, iclass 20, count 0 2006.225.08:09:20.28#ibcon#about to read 4, iclass 20, count 0 2006.225.08:09:20.28#ibcon#read 4, iclass 20, count 0 2006.225.08:09:20.28#ibcon#about to read 5, iclass 20, count 0 2006.225.08:09:20.28#ibcon#read 5, iclass 20, count 0 2006.225.08:09:20.28#ibcon#about to read 6, iclass 20, count 0 2006.225.08:09:20.28#ibcon#read 6, iclass 20, count 0 2006.225.08:09:20.28#ibcon#end of sib2, iclass 20, count 0 2006.225.08:09:20.28#ibcon#*after write, iclass 20, count 0 2006.225.08:09:20.28#ibcon#*before return 0, iclass 20, count 0 2006.225.08:09:20.28#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:09:20.28#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:09:20.28#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.08:09:20.28#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.08:09:20.28$vc4f8/va=8,7 2006.225.08:09:20.28#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.225.08:09:20.28#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.225.08:09:20.28#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:20.28#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:09:20.34#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:09:20.34#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:09:20.34#ibcon#enter wrdev, iclass 22, count 2 2006.225.08:09:20.34#ibcon#first serial, iclass 22, count 2 2006.225.08:09:20.34#ibcon#enter sib2, iclass 22, count 2 2006.225.08:09:20.34#ibcon#flushed, iclass 22, count 2 2006.225.08:09:20.34#ibcon#about to write, iclass 22, count 2 2006.225.08:09:20.34#ibcon#wrote, iclass 22, count 2 2006.225.08:09:20.34#ibcon#about to read 3, iclass 22, count 2 2006.225.08:09:20.36#ibcon#read 3, iclass 22, count 2 2006.225.08:09:20.36#ibcon#about to read 4, iclass 22, count 2 2006.225.08:09:20.36#ibcon#read 4, iclass 22, count 2 2006.225.08:09:20.36#ibcon#about to read 5, iclass 22, count 2 2006.225.08:09:20.36#ibcon#read 5, iclass 22, count 2 2006.225.08:09:20.36#ibcon#about to read 6, iclass 22, count 2 2006.225.08:09:20.36#ibcon#read 6, iclass 22, count 2 2006.225.08:09:20.36#ibcon#end of sib2, iclass 22, count 2 2006.225.08:09:20.36#ibcon#*mode == 0, iclass 22, count 2 2006.225.08:09:20.36#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.225.08:09:20.36#ibcon#[25=AT08-07\r\n] 2006.225.08:09:20.36#ibcon#*before write, iclass 22, count 2 2006.225.08:09:20.36#ibcon#enter sib2, iclass 22, count 2 2006.225.08:09:20.36#ibcon#flushed, iclass 22, count 2 2006.225.08:09:20.36#ibcon#about to write, iclass 22, count 2 2006.225.08:09:20.36#ibcon#wrote, iclass 22, count 2 2006.225.08:09:20.36#ibcon#about to read 3, iclass 22, count 2 2006.225.08:09:20.39#ibcon#read 3, iclass 22, count 2 2006.225.08:09:20.39#ibcon#about to read 4, iclass 22, count 2 2006.225.08:09:20.39#ibcon#read 4, iclass 22, count 2 2006.225.08:09:20.39#ibcon#about to read 5, iclass 22, count 2 2006.225.08:09:20.39#ibcon#read 5, iclass 22, count 2 2006.225.08:09:20.39#ibcon#about to read 6, iclass 22, count 2 2006.225.08:09:20.39#ibcon#read 6, iclass 22, count 2 2006.225.08:09:20.39#ibcon#end of sib2, iclass 22, count 2 2006.225.08:09:20.39#ibcon#*after write, iclass 22, count 2 2006.225.08:09:20.39#ibcon#*before return 0, iclass 22, count 2 2006.225.08:09:20.39#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:09:20.39#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:09:20.39#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.225.08:09:20.39#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:20.39#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:09:20.51#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:09:20.51#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:09:20.51#ibcon#enter wrdev, iclass 22, count 0 2006.225.08:09:20.51#ibcon#first serial, iclass 22, count 0 2006.225.08:09:20.51#ibcon#enter sib2, iclass 22, count 0 2006.225.08:09:20.51#ibcon#flushed, iclass 22, count 0 2006.225.08:09:20.51#ibcon#about to write, iclass 22, count 0 2006.225.08:09:20.51#ibcon#wrote, iclass 22, count 0 2006.225.08:09:20.51#ibcon#about to read 3, iclass 22, count 0 2006.225.08:09:20.53#ibcon#read 3, iclass 22, count 0 2006.225.08:09:20.53#ibcon#about to read 4, iclass 22, count 0 2006.225.08:09:20.53#ibcon#read 4, iclass 22, count 0 2006.225.08:09:20.53#ibcon#about to read 5, iclass 22, count 0 2006.225.08:09:20.53#ibcon#read 5, iclass 22, count 0 2006.225.08:09:20.53#ibcon#about to read 6, iclass 22, count 0 2006.225.08:09:20.53#ibcon#read 6, iclass 22, count 0 2006.225.08:09:20.53#ibcon#end of sib2, iclass 22, count 0 2006.225.08:09:20.53#ibcon#*mode == 0, iclass 22, count 0 2006.225.08:09:20.53#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.08:09:20.53#ibcon#[25=USB\r\n] 2006.225.08:09:20.53#ibcon#*before write, iclass 22, count 0 2006.225.08:09:20.53#ibcon#enter sib2, iclass 22, count 0 2006.225.08:09:20.53#ibcon#flushed, iclass 22, count 0 2006.225.08:09:20.53#ibcon#about to write, iclass 22, count 0 2006.225.08:09:20.53#ibcon#wrote, iclass 22, count 0 2006.225.08:09:20.53#ibcon#about to read 3, iclass 22, count 0 2006.225.08:09:20.56#ibcon#read 3, iclass 22, count 0 2006.225.08:09:20.56#ibcon#about to read 4, iclass 22, count 0 2006.225.08:09:20.56#ibcon#read 4, iclass 22, count 0 2006.225.08:09:20.56#ibcon#about to read 5, iclass 22, count 0 2006.225.08:09:20.56#ibcon#read 5, iclass 22, count 0 2006.225.08:09:20.56#ibcon#about to read 6, iclass 22, count 0 2006.225.08:09:20.56#ibcon#read 6, iclass 22, count 0 2006.225.08:09:20.56#ibcon#end of sib2, iclass 22, count 0 2006.225.08:09:20.56#ibcon#*after write, iclass 22, count 0 2006.225.08:09:20.56#ibcon#*before return 0, iclass 22, count 0 2006.225.08:09:20.56#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:09:20.56#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:09:20.56#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.08:09:20.56#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.08:09:20.56$vc4f8/vblo=1,632.99 2006.225.08:09:20.56#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.08:09:20.56#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.08:09:20.56#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:20.56#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:09:20.56#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:09:20.56#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:09:20.56#ibcon#enter wrdev, iclass 24, count 0 2006.225.08:09:20.56#ibcon#first serial, iclass 24, count 0 2006.225.08:09:20.56#ibcon#enter sib2, iclass 24, count 0 2006.225.08:09:20.56#ibcon#flushed, iclass 24, count 0 2006.225.08:09:20.56#ibcon#about to write, iclass 24, count 0 2006.225.08:09:20.56#ibcon#wrote, iclass 24, count 0 2006.225.08:09:20.56#ibcon#about to read 3, iclass 24, count 0 2006.225.08:09:20.58#ibcon#read 3, iclass 24, count 0 2006.225.08:09:20.58#ibcon#about to read 4, iclass 24, count 0 2006.225.08:09:20.58#ibcon#read 4, iclass 24, count 0 2006.225.08:09:20.58#ibcon#about to read 5, iclass 24, count 0 2006.225.08:09:20.58#ibcon#read 5, iclass 24, count 0 2006.225.08:09:20.58#ibcon#about to read 6, iclass 24, count 0 2006.225.08:09:20.58#ibcon#read 6, iclass 24, count 0 2006.225.08:09:20.58#ibcon#end of sib2, iclass 24, count 0 2006.225.08:09:20.58#ibcon#*mode == 0, iclass 24, count 0 2006.225.08:09:20.58#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.08:09:20.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:09:20.58#ibcon#*before write, iclass 24, count 0 2006.225.08:09:20.58#ibcon#enter sib2, iclass 24, count 0 2006.225.08:09:20.58#ibcon#flushed, iclass 24, count 0 2006.225.08:09:20.58#ibcon#about to write, iclass 24, count 0 2006.225.08:09:20.58#ibcon#wrote, iclass 24, count 0 2006.225.08:09:20.58#ibcon#about to read 3, iclass 24, count 0 2006.225.08:09:20.62#ibcon#read 3, iclass 24, count 0 2006.225.08:09:20.62#ibcon#about to read 4, iclass 24, count 0 2006.225.08:09:20.62#ibcon#read 4, iclass 24, count 0 2006.225.08:09:20.62#ibcon#about to read 5, iclass 24, count 0 2006.225.08:09:20.62#ibcon#read 5, iclass 24, count 0 2006.225.08:09:20.62#ibcon#about to read 6, iclass 24, count 0 2006.225.08:09:20.62#ibcon#read 6, iclass 24, count 0 2006.225.08:09:20.62#ibcon#end of sib2, iclass 24, count 0 2006.225.08:09:20.62#ibcon#*after write, iclass 24, count 0 2006.225.08:09:20.62#ibcon#*before return 0, iclass 24, count 0 2006.225.08:09:20.62#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:09:20.62#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:09:20.62#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.08:09:20.62#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.08:09:20.62$vc4f8/vb=1,4 2006.225.08:09:20.62#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.225.08:09:20.62#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.225.08:09:20.62#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:20.62#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:09:20.62#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:09:20.62#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:09:20.62#ibcon#enter wrdev, iclass 27, count 2 2006.225.08:09:20.62#ibcon#first serial, iclass 27, count 2 2006.225.08:09:20.62#ibcon#enter sib2, iclass 27, count 2 2006.225.08:09:20.62#ibcon#flushed, iclass 27, count 2 2006.225.08:09:20.62#ibcon#about to write, iclass 27, count 2 2006.225.08:09:20.62#ibcon#wrote, iclass 27, count 2 2006.225.08:09:20.62#ibcon#about to read 3, iclass 27, count 2 2006.225.08:09:20.63#abcon#<5=/04 2.8 5.2 28.12 701003.3\r\n> 2006.225.08:09:20.64#ibcon#read 3, iclass 27, count 2 2006.225.08:09:20.64#ibcon#about to read 4, iclass 27, count 2 2006.225.08:09:20.64#ibcon#read 4, iclass 27, count 2 2006.225.08:09:20.64#ibcon#about to read 5, iclass 27, count 2 2006.225.08:09:20.64#ibcon#read 5, iclass 27, count 2 2006.225.08:09:20.64#ibcon#about to read 6, iclass 27, count 2 2006.225.08:09:20.64#ibcon#read 6, iclass 27, count 2 2006.225.08:09:20.64#ibcon#end of sib2, iclass 27, count 2 2006.225.08:09:20.64#ibcon#*mode == 0, iclass 27, count 2 2006.225.08:09:20.64#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.225.08:09:20.64#ibcon#[27=AT01-04\r\n] 2006.225.08:09:20.64#ibcon#*before write, iclass 27, count 2 2006.225.08:09:20.64#ibcon#enter sib2, iclass 27, count 2 2006.225.08:09:20.64#ibcon#flushed, iclass 27, count 2 2006.225.08:09:20.64#ibcon#about to write, iclass 27, count 2 2006.225.08:09:20.64#ibcon#wrote, iclass 27, count 2 2006.225.08:09:20.64#ibcon#about to read 3, iclass 27, count 2 2006.225.08:09:20.65#abcon#{5=INTERFACE CLEAR} 2006.225.08:09:20.67#ibcon#read 3, iclass 27, count 2 2006.225.08:09:20.67#ibcon#about to read 4, iclass 27, count 2 2006.225.08:09:20.67#ibcon#read 4, iclass 27, count 2 2006.225.08:09:20.67#ibcon#about to read 5, iclass 27, count 2 2006.225.08:09:20.67#ibcon#read 5, iclass 27, count 2 2006.225.08:09:20.67#ibcon#about to read 6, iclass 27, count 2 2006.225.08:09:20.67#ibcon#read 6, iclass 27, count 2 2006.225.08:09:20.67#ibcon#end of sib2, iclass 27, count 2 2006.225.08:09:20.67#ibcon#*after write, iclass 27, count 2 2006.225.08:09:20.67#ibcon#*before return 0, iclass 27, count 2 2006.225.08:09:20.67#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:09:20.67#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:09:20.67#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.225.08:09:20.67#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:20.67#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:09:20.71#abcon#[5=S1D000X0/0*\r\n] 2006.225.08:09:20.79#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:09:20.79#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:09:20.79#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:09:20.79#ibcon#first serial, iclass 27, count 0 2006.225.08:09:20.79#ibcon#enter sib2, iclass 27, count 0 2006.225.08:09:20.79#ibcon#flushed, iclass 27, count 0 2006.225.08:09:20.79#ibcon#about to write, iclass 27, count 0 2006.225.08:09:20.79#ibcon#wrote, iclass 27, count 0 2006.225.08:09:20.79#ibcon#about to read 3, iclass 27, count 0 2006.225.08:09:20.81#ibcon#read 3, iclass 27, count 0 2006.225.08:09:20.81#ibcon#about to read 4, iclass 27, count 0 2006.225.08:09:20.81#ibcon#read 4, iclass 27, count 0 2006.225.08:09:20.81#ibcon#about to read 5, iclass 27, count 0 2006.225.08:09:20.81#ibcon#read 5, iclass 27, count 0 2006.225.08:09:20.81#ibcon#about to read 6, iclass 27, count 0 2006.225.08:09:20.81#ibcon#read 6, iclass 27, count 0 2006.225.08:09:20.81#ibcon#end of sib2, iclass 27, count 0 2006.225.08:09:20.81#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:09:20.81#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:09:20.81#ibcon#[27=USB\r\n] 2006.225.08:09:20.81#ibcon#*before write, iclass 27, count 0 2006.225.08:09:20.81#ibcon#enter sib2, iclass 27, count 0 2006.225.08:09:20.81#ibcon#flushed, iclass 27, count 0 2006.225.08:09:20.81#ibcon#about to write, iclass 27, count 0 2006.225.08:09:20.81#ibcon#wrote, iclass 27, count 0 2006.225.08:09:20.81#ibcon#about to read 3, iclass 27, count 0 2006.225.08:09:20.84#ibcon#read 3, iclass 27, count 0 2006.225.08:09:20.84#ibcon#about to read 4, iclass 27, count 0 2006.225.08:09:20.84#ibcon#read 4, iclass 27, count 0 2006.225.08:09:20.84#ibcon#about to read 5, iclass 27, count 0 2006.225.08:09:20.84#ibcon#read 5, iclass 27, count 0 2006.225.08:09:20.84#ibcon#about to read 6, iclass 27, count 0 2006.225.08:09:20.84#ibcon#read 6, iclass 27, count 0 2006.225.08:09:20.84#ibcon#end of sib2, iclass 27, count 0 2006.225.08:09:20.84#ibcon#*after write, iclass 27, count 0 2006.225.08:09:20.84#ibcon#*before return 0, iclass 27, count 0 2006.225.08:09:20.84#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:09:20.84#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:09:20.84#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:09:20.84#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:09:20.84$vc4f8/vblo=2,640.99 2006.225.08:09:20.84#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.08:09:20.84#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.08:09:20.84#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:20.84#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:09:20.84#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:09:20.84#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:09:20.84#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:09:20.84#ibcon#first serial, iclass 32, count 0 2006.225.08:09:20.84#ibcon#enter sib2, iclass 32, count 0 2006.225.08:09:20.84#ibcon#flushed, iclass 32, count 0 2006.225.08:09:20.84#ibcon#about to write, iclass 32, count 0 2006.225.08:09:20.84#ibcon#wrote, iclass 32, count 0 2006.225.08:09:20.84#ibcon#about to read 3, iclass 32, count 0 2006.225.08:09:20.86#ibcon#read 3, iclass 32, count 0 2006.225.08:09:20.86#ibcon#about to read 4, iclass 32, count 0 2006.225.08:09:20.86#ibcon#read 4, iclass 32, count 0 2006.225.08:09:20.86#ibcon#about to read 5, iclass 32, count 0 2006.225.08:09:20.86#ibcon#read 5, iclass 32, count 0 2006.225.08:09:20.86#ibcon#about to read 6, iclass 32, count 0 2006.225.08:09:20.86#ibcon#read 6, iclass 32, count 0 2006.225.08:09:20.86#ibcon#end of sib2, iclass 32, count 0 2006.225.08:09:20.86#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:09:20.86#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:09:20.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:09:20.86#ibcon#*before write, iclass 32, count 0 2006.225.08:09:20.86#ibcon#enter sib2, iclass 32, count 0 2006.225.08:09:20.86#ibcon#flushed, iclass 32, count 0 2006.225.08:09:20.86#ibcon#about to write, iclass 32, count 0 2006.225.08:09:20.86#ibcon#wrote, iclass 32, count 0 2006.225.08:09:20.86#ibcon#about to read 3, iclass 32, count 0 2006.225.08:09:20.90#ibcon#read 3, iclass 32, count 0 2006.225.08:09:20.90#ibcon#about to read 4, iclass 32, count 0 2006.225.08:09:20.90#ibcon#read 4, iclass 32, count 0 2006.225.08:09:20.90#ibcon#about to read 5, iclass 32, count 0 2006.225.08:09:20.90#ibcon#read 5, iclass 32, count 0 2006.225.08:09:20.90#ibcon#about to read 6, iclass 32, count 0 2006.225.08:09:20.90#ibcon#read 6, iclass 32, count 0 2006.225.08:09:20.90#ibcon#end of sib2, iclass 32, count 0 2006.225.08:09:20.90#ibcon#*after write, iclass 32, count 0 2006.225.08:09:20.90#ibcon#*before return 0, iclass 32, count 0 2006.225.08:09:20.90#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:09:20.90#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:09:20.90#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:09:20.90#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:09:20.90$vc4f8/vb=2,4 2006.225.08:09:20.90#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.08:09:20.90#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.08:09:20.90#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:20.90#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:09:20.96#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:09:20.96#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:09:20.96#ibcon#enter wrdev, iclass 34, count 2 2006.225.08:09:20.96#ibcon#first serial, iclass 34, count 2 2006.225.08:09:20.96#ibcon#enter sib2, iclass 34, count 2 2006.225.08:09:20.96#ibcon#flushed, iclass 34, count 2 2006.225.08:09:20.96#ibcon#about to write, iclass 34, count 2 2006.225.08:09:20.96#ibcon#wrote, iclass 34, count 2 2006.225.08:09:20.96#ibcon#about to read 3, iclass 34, count 2 2006.225.08:09:20.98#ibcon#read 3, iclass 34, count 2 2006.225.08:09:20.98#ibcon#about to read 4, iclass 34, count 2 2006.225.08:09:20.98#ibcon#read 4, iclass 34, count 2 2006.225.08:09:20.98#ibcon#about to read 5, iclass 34, count 2 2006.225.08:09:20.98#ibcon#read 5, iclass 34, count 2 2006.225.08:09:20.98#ibcon#about to read 6, iclass 34, count 2 2006.225.08:09:20.98#ibcon#read 6, iclass 34, count 2 2006.225.08:09:20.98#ibcon#end of sib2, iclass 34, count 2 2006.225.08:09:20.98#ibcon#*mode == 0, iclass 34, count 2 2006.225.08:09:20.98#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.08:09:20.98#ibcon#[27=AT02-04\r\n] 2006.225.08:09:20.98#ibcon#*before write, iclass 34, count 2 2006.225.08:09:20.98#ibcon#enter sib2, iclass 34, count 2 2006.225.08:09:20.98#ibcon#flushed, iclass 34, count 2 2006.225.08:09:20.98#ibcon#about to write, iclass 34, count 2 2006.225.08:09:20.98#ibcon#wrote, iclass 34, count 2 2006.225.08:09:20.98#ibcon#about to read 3, iclass 34, count 2 2006.225.08:09:21.01#ibcon#read 3, iclass 34, count 2 2006.225.08:09:21.01#ibcon#about to read 4, iclass 34, count 2 2006.225.08:09:21.01#ibcon#read 4, iclass 34, count 2 2006.225.08:09:21.01#ibcon#about to read 5, iclass 34, count 2 2006.225.08:09:21.01#ibcon#read 5, iclass 34, count 2 2006.225.08:09:21.01#ibcon#about to read 6, iclass 34, count 2 2006.225.08:09:21.01#ibcon#read 6, iclass 34, count 2 2006.225.08:09:21.01#ibcon#end of sib2, iclass 34, count 2 2006.225.08:09:21.01#ibcon#*after write, iclass 34, count 2 2006.225.08:09:21.01#ibcon#*before return 0, iclass 34, count 2 2006.225.08:09:21.01#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:09:21.01#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:09:21.01#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.08:09:21.01#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:21.01#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:09:21.13#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:09:21.13#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:09:21.13#ibcon#enter wrdev, iclass 34, count 0 2006.225.08:09:21.13#ibcon#first serial, iclass 34, count 0 2006.225.08:09:21.13#ibcon#enter sib2, iclass 34, count 0 2006.225.08:09:21.13#ibcon#flushed, iclass 34, count 0 2006.225.08:09:21.13#ibcon#about to write, iclass 34, count 0 2006.225.08:09:21.13#ibcon#wrote, iclass 34, count 0 2006.225.08:09:21.13#ibcon#about to read 3, iclass 34, count 0 2006.225.08:09:21.15#ibcon#read 3, iclass 34, count 0 2006.225.08:09:21.15#ibcon#about to read 4, iclass 34, count 0 2006.225.08:09:21.15#ibcon#read 4, iclass 34, count 0 2006.225.08:09:21.15#ibcon#about to read 5, iclass 34, count 0 2006.225.08:09:21.15#ibcon#read 5, iclass 34, count 0 2006.225.08:09:21.15#ibcon#about to read 6, iclass 34, count 0 2006.225.08:09:21.15#ibcon#read 6, iclass 34, count 0 2006.225.08:09:21.15#ibcon#end of sib2, iclass 34, count 0 2006.225.08:09:21.15#ibcon#*mode == 0, iclass 34, count 0 2006.225.08:09:21.15#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.08:09:21.15#ibcon#[27=USB\r\n] 2006.225.08:09:21.15#ibcon#*before write, iclass 34, count 0 2006.225.08:09:21.15#ibcon#enter sib2, iclass 34, count 0 2006.225.08:09:21.15#ibcon#flushed, iclass 34, count 0 2006.225.08:09:21.15#ibcon#about to write, iclass 34, count 0 2006.225.08:09:21.15#ibcon#wrote, iclass 34, count 0 2006.225.08:09:21.15#ibcon#about to read 3, iclass 34, count 0 2006.225.08:09:21.18#ibcon#read 3, iclass 34, count 0 2006.225.08:09:21.18#ibcon#about to read 4, iclass 34, count 0 2006.225.08:09:21.18#ibcon#read 4, iclass 34, count 0 2006.225.08:09:21.18#ibcon#about to read 5, iclass 34, count 0 2006.225.08:09:21.18#ibcon#read 5, iclass 34, count 0 2006.225.08:09:21.18#ibcon#about to read 6, iclass 34, count 0 2006.225.08:09:21.18#ibcon#read 6, iclass 34, count 0 2006.225.08:09:21.18#ibcon#end of sib2, iclass 34, count 0 2006.225.08:09:21.18#ibcon#*after write, iclass 34, count 0 2006.225.08:09:21.18#ibcon#*before return 0, iclass 34, count 0 2006.225.08:09:21.18#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:09:21.18#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:09:21.18#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.08:09:21.18#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.08:09:21.18$vc4f8/vblo=3,656.99 2006.225.08:09:21.18#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.08:09:21.18#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.08:09:21.18#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:21.18#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:09:21.18#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:09:21.18#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:09:21.18#ibcon#enter wrdev, iclass 36, count 0 2006.225.08:09:21.18#ibcon#first serial, iclass 36, count 0 2006.225.08:09:21.18#ibcon#enter sib2, iclass 36, count 0 2006.225.08:09:21.18#ibcon#flushed, iclass 36, count 0 2006.225.08:09:21.18#ibcon#about to write, iclass 36, count 0 2006.225.08:09:21.18#ibcon#wrote, iclass 36, count 0 2006.225.08:09:21.18#ibcon#about to read 3, iclass 36, count 0 2006.225.08:09:21.21#ibcon#read 3, iclass 36, count 0 2006.225.08:09:21.21#ibcon#about to read 4, iclass 36, count 0 2006.225.08:09:21.21#ibcon#read 4, iclass 36, count 0 2006.225.08:09:21.21#ibcon#about to read 5, iclass 36, count 0 2006.225.08:09:21.21#ibcon#read 5, iclass 36, count 0 2006.225.08:09:21.21#ibcon#about to read 6, iclass 36, count 0 2006.225.08:09:21.21#ibcon#read 6, iclass 36, count 0 2006.225.08:09:21.21#ibcon#end of sib2, iclass 36, count 0 2006.225.08:09:21.21#ibcon#*mode == 0, iclass 36, count 0 2006.225.08:09:21.21#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.08:09:21.21#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:09:21.21#ibcon#*before write, iclass 36, count 0 2006.225.08:09:21.21#ibcon#enter sib2, iclass 36, count 0 2006.225.08:09:21.21#ibcon#flushed, iclass 36, count 0 2006.225.08:09:21.21#ibcon#about to write, iclass 36, count 0 2006.225.08:09:21.21#ibcon#wrote, iclass 36, count 0 2006.225.08:09:21.21#ibcon#about to read 3, iclass 36, count 0 2006.225.08:09:21.24#ibcon#read 3, iclass 36, count 0 2006.225.08:09:21.24#ibcon#about to read 4, iclass 36, count 0 2006.225.08:09:21.24#ibcon#read 4, iclass 36, count 0 2006.225.08:09:21.24#ibcon#about to read 5, iclass 36, count 0 2006.225.08:09:21.24#ibcon#read 5, iclass 36, count 0 2006.225.08:09:21.24#ibcon#about to read 6, iclass 36, count 0 2006.225.08:09:21.24#ibcon#read 6, iclass 36, count 0 2006.225.08:09:21.24#ibcon#end of sib2, iclass 36, count 0 2006.225.08:09:21.24#ibcon#*after write, iclass 36, count 0 2006.225.08:09:21.24#ibcon#*before return 0, iclass 36, count 0 2006.225.08:09:21.24#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:09:21.24#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:09:21.24#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.08:09:21.24#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.08:09:21.24$vc4f8/vb=3,4 2006.225.08:09:21.24#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.08:09:21.24#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.08:09:21.24#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:21.24#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:09:21.30#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:09:21.30#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:09:21.30#ibcon#enter wrdev, iclass 38, count 2 2006.225.08:09:21.30#ibcon#first serial, iclass 38, count 2 2006.225.08:09:21.30#ibcon#enter sib2, iclass 38, count 2 2006.225.08:09:21.30#ibcon#flushed, iclass 38, count 2 2006.225.08:09:21.30#ibcon#about to write, iclass 38, count 2 2006.225.08:09:21.30#ibcon#wrote, iclass 38, count 2 2006.225.08:09:21.30#ibcon#about to read 3, iclass 38, count 2 2006.225.08:09:21.32#ibcon#read 3, iclass 38, count 2 2006.225.08:09:21.32#ibcon#about to read 4, iclass 38, count 2 2006.225.08:09:21.32#ibcon#read 4, iclass 38, count 2 2006.225.08:09:21.32#ibcon#about to read 5, iclass 38, count 2 2006.225.08:09:21.32#ibcon#read 5, iclass 38, count 2 2006.225.08:09:21.32#ibcon#about to read 6, iclass 38, count 2 2006.225.08:09:21.32#ibcon#read 6, iclass 38, count 2 2006.225.08:09:21.32#ibcon#end of sib2, iclass 38, count 2 2006.225.08:09:21.32#ibcon#*mode == 0, iclass 38, count 2 2006.225.08:09:21.32#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.08:09:21.32#ibcon#[27=AT03-04\r\n] 2006.225.08:09:21.32#ibcon#*before write, iclass 38, count 2 2006.225.08:09:21.32#ibcon#enter sib2, iclass 38, count 2 2006.225.08:09:21.32#ibcon#flushed, iclass 38, count 2 2006.225.08:09:21.32#ibcon#about to write, iclass 38, count 2 2006.225.08:09:21.32#ibcon#wrote, iclass 38, count 2 2006.225.08:09:21.32#ibcon#about to read 3, iclass 38, count 2 2006.225.08:09:21.35#ibcon#read 3, iclass 38, count 2 2006.225.08:09:21.35#ibcon#about to read 4, iclass 38, count 2 2006.225.08:09:21.35#ibcon#read 4, iclass 38, count 2 2006.225.08:09:21.35#ibcon#about to read 5, iclass 38, count 2 2006.225.08:09:21.35#ibcon#read 5, iclass 38, count 2 2006.225.08:09:21.35#ibcon#about to read 6, iclass 38, count 2 2006.225.08:09:21.35#ibcon#read 6, iclass 38, count 2 2006.225.08:09:21.35#ibcon#end of sib2, iclass 38, count 2 2006.225.08:09:21.35#ibcon#*after write, iclass 38, count 2 2006.225.08:09:21.35#ibcon#*before return 0, iclass 38, count 2 2006.225.08:09:21.35#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:09:21.35#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:09:21.35#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.08:09:21.35#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:21.35#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:09:21.47#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:09:21.47#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:09:21.47#ibcon#enter wrdev, iclass 38, count 0 2006.225.08:09:21.47#ibcon#first serial, iclass 38, count 0 2006.225.08:09:21.47#ibcon#enter sib2, iclass 38, count 0 2006.225.08:09:21.47#ibcon#flushed, iclass 38, count 0 2006.225.08:09:21.47#ibcon#about to write, iclass 38, count 0 2006.225.08:09:21.47#ibcon#wrote, iclass 38, count 0 2006.225.08:09:21.47#ibcon#about to read 3, iclass 38, count 0 2006.225.08:09:21.49#ibcon#read 3, iclass 38, count 0 2006.225.08:09:21.49#ibcon#about to read 4, iclass 38, count 0 2006.225.08:09:21.49#ibcon#read 4, iclass 38, count 0 2006.225.08:09:21.49#ibcon#about to read 5, iclass 38, count 0 2006.225.08:09:21.49#ibcon#read 5, iclass 38, count 0 2006.225.08:09:21.49#ibcon#about to read 6, iclass 38, count 0 2006.225.08:09:21.49#ibcon#read 6, iclass 38, count 0 2006.225.08:09:21.49#ibcon#end of sib2, iclass 38, count 0 2006.225.08:09:21.49#ibcon#*mode == 0, iclass 38, count 0 2006.225.08:09:21.49#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.08:09:21.49#ibcon#[27=USB\r\n] 2006.225.08:09:21.49#ibcon#*before write, iclass 38, count 0 2006.225.08:09:21.49#ibcon#enter sib2, iclass 38, count 0 2006.225.08:09:21.49#ibcon#flushed, iclass 38, count 0 2006.225.08:09:21.49#ibcon#about to write, iclass 38, count 0 2006.225.08:09:21.49#ibcon#wrote, iclass 38, count 0 2006.225.08:09:21.49#ibcon#about to read 3, iclass 38, count 0 2006.225.08:09:21.52#ibcon#read 3, iclass 38, count 0 2006.225.08:09:21.52#ibcon#about to read 4, iclass 38, count 0 2006.225.08:09:21.52#ibcon#read 4, iclass 38, count 0 2006.225.08:09:21.52#ibcon#about to read 5, iclass 38, count 0 2006.225.08:09:21.52#ibcon#read 5, iclass 38, count 0 2006.225.08:09:21.52#ibcon#about to read 6, iclass 38, count 0 2006.225.08:09:21.52#ibcon#read 6, iclass 38, count 0 2006.225.08:09:21.52#ibcon#end of sib2, iclass 38, count 0 2006.225.08:09:21.52#ibcon#*after write, iclass 38, count 0 2006.225.08:09:21.52#ibcon#*before return 0, iclass 38, count 0 2006.225.08:09:21.52#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:09:21.52#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:09:21.52#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.08:09:21.52#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.08:09:21.52$vc4f8/vblo=4,712.99 2006.225.08:09:21.52#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.08:09:21.52#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.08:09:21.52#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:21.52#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:09:21.52#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:09:21.52#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:09:21.52#ibcon#enter wrdev, iclass 40, count 0 2006.225.08:09:21.52#ibcon#first serial, iclass 40, count 0 2006.225.08:09:21.52#ibcon#enter sib2, iclass 40, count 0 2006.225.08:09:21.52#ibcon#flushed, iclass 40, count 0 2006.225.08:09:21.52#ibcon#about to write, iclass 40, count 0 2006.225.08:09:21.52#ibcon#wrote, iclass 40, count 0 2006.225.08:09:21.52#ibcon#about to read 3, iclass 40, count 0 2006.225.08:09:21.54#ibcon#read 3, iclass 40, count 0 2006.225.08:09:21.54#ibcon#about to read 4, iclass 40, count 0 2006.225.08:09:21.54#ibcon#read 4, iclass 40, count 0 2006.225.08:09:21.54#ibcon#about to read 5, iclass 40, count 0 2006.225.08:09:21.54#ibcon#read 5, iclass 40, count 0 2006.225.08:09:21.54#ibcon#about to read 6, iclass 40, count 0 2006.225.08:09:21.54#ibcon#read 6, iclass 40, count 0 2006.225.08:09:21.54#ibcon#end of sib2, iclass 40, count 0 2006.225.08:09:21.54#ibcon#*mode == 0, iclass 40, count 0 2006.225.08:09:21.54#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.08:09:21.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:09:21.54#ibcon#*before write, iclass 40, count 0 2006.225.08:09:21.54#ibcon#enter sib2, iclass 40, count 0 2006.225.08:09:21.54#ibcon#flushed, iclass 40, count 0 2006.225.08:09:21.54#ibcon#about to write, iclass 40, count 0 2006.225.08:09:21.54#ibcon#wrote, iclass 40, count 0 2006.225.08:09:21.54#ibcon#about to read 3, iclass 40, count 0 2006.225.08:09:21.58#ibcon#read 3, iclass 40, count 0 2006.225.08:09:21.58#ibcon#about to read 4, iclass 40, count 0 2006.225.08:09:21.58#ibcon#read 4, iclass 40, count 0 2006.225.08:09:21.58#ibcon#about to read 5, iclass 40, count 0 2006.225.08:09:21.58#ibcon#read 5, iclass 40, count 0 2006.225.08:09:21.58#ibcon#about to read 6, iclass 40, count 0 2006.225.08:09:21.58#ibcon#read 6, iclass 40, count 0 2006.225.08:09:21.58#ibcon#end of sib2, iclass 40, count 0 2006.225.08:09:21.58#ibcon#*after write, iclass 40, count 0 2006.225.08:09:21.58#ibcon#*before return 0, iclass 40, count 0 2006.225.08:09:21.58#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:09:21.58#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:09:21.58#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.08:09:21.58#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.08:09:21.58$vc4f8/vb=4,4 2006.225.08:09:21.58#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.08:09:21.58#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.08:09:21.58#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:21.58#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:09:21.64#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:09:21.64#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:09:21.64#ibcon#enter wrdev, iclass 4, count 2 2006.225.08:09:21.64#ibcon#first serial, iclass 4, count 2 2006.225.08:09:21.64#ibcon#enter sib2, iclass 4, count 2 2006.225.08:09:21.64#ibcon#flushed, iclass 4, count 2 2006.225.08:09:21.64#ibcon#about to write, iclass 4, count 2 2006.225.08:09:21.64#ibcon#wrote, iclass 4, count 2 2006.225.08:09:21.64#ibcon#about to read 3, iclass 4, count 2 2006.225.08:09:21.66#ibcon#read 3, iclass 4, count 2 2006.225.08:09:21.66#ibcon#about to read 4, iclass 4, count 2 2006.225.08:09:21.66#ibcon#read 4, iclass 4, count 2 2006.225.08:09:21.66#ibcon#about to read 5, iclass 4, count 2 2006.225.08:09:21.66#ibcon#read 5, iclass 4, count 2 2006.225.08:09:21.66#ibcon#about to read 6, iclass 4, count 2 2006.225.08:09:21.66#ibcon#read 6, iclass 4, count 2 2006.225.08:09:21.66#ibcon#end of sib2, iclass 4, count 2 2006.225.08:09:21.66#ibcon#*mode == 0, iclass 4, count 2 2006.225.08:09:21.66#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.08:09:21.66#ibcon#[27=AT04-04\r\n] 2006.225.08:09:21.66#ibcon#*before write, iclass 4, count 2 2006.225.08:09:21.66#ibcon#enter sib2, iclass 4, count 2 2006.225.08:09:21.66#ibcon#flushed, iclass 4, count 2 2006.225.08:09:21.66#ibcon#about to write, iclass 4, count 2 2006.225.08:09:21.66#ibcon#wrote, iclass 4, count 2 2006.225.08:09:21.66#ibcon#about to read 3, iclass 4, count 2 2006.225.08:09:21.69#ibcon#read 3, iclass 4, count 2 2006.225.08:09:21.69#ibcon#about to read 4, iclass 4, count 2 2006.225.08:09:21.69#ibcon#read 4, iclass 4, count 2 2006.225.08:09:21.69#ibcon#about to read 5, iclass 4, count 2 2006.225.08:09:21.69#ibcon#read 5, iclass 4, count 2 2006.225.08:09:21.69#ibcon#about to read 6, iclass 4, count 2 2006.225.08:09:21.69#ibcon#read 6, iclass 4, count 2 2006.225.08:09:21.69#ibcon#end of sib2, iclass 4, count 2 2006.225.08:09:21.69#ibcon#*after write, iclass 4, count 2 2006.225.08:09:21.69#ibcon#*before return 0, iclass 4, count 2 2006.225.08:09:21.69#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:09:21.69#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:09:21.69#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.08:09:21.69#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:21.69#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:09:21.81#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:09:21.81#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:09:21.81#ibcon#enter wrdev, iclass 4, count 0 2006.225.08:09:21.81#ibcon#first serial, iclass 4, count 0 2006.225.08:09:21.81#ibcon#enter sib2, iclass 4, count 0 2006.225.08:09:21.81#ibcon#flushed, iclass 4, count 0 2006.225.08:09:21.81#ibcon#about to write, iclass 4, count 0 2006.225.08:09:21.81#ibcon#wrote, iclass 4, count 0 2006.225.08:09:21.81#ibcon#about to read 3, iclass 4, count 0 2006.225.08:09:21.83#ibcon#read 3, iclass 4, count 0 2006.225.08:09:21.83#ibcon#about to read 4, iclass 4, count 0 2006.225.08:09:21.83#ibcon#read 4, iclass 4, count 0 2006.225.08:09:21.83#ibcon#about to read 5, iclass 4, count 0 2006.225.08:09:21.83#ibcon#read 5, iclass 4, count 0 2006.225.08:09:21.83#ibcon#about to read 6, iclass 4, count 0 2006.225.08:09:21.83#ibcon#read 6, iclass 4, count 0 2006.225.08:09:21.83#ibcon#end of sib2, iclass 4, count 0 2006.225.08:09:21.83#ibcon#*mode == 0, iclass 4, count 0 2006.225.08:09:21.83#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.08:09:21.83#ibcon#[27=USB\r\n] 2006.225.08:09:21.83#ibcon#*before write, iclass 4, count 0 2006.225.08:09:21.83#ibcon#enter sib2, iclass 4, count 0 2006.225.08:09:21.83#ibcon#flushed, iclass 4, count 0 2006.225.08:09:21.83#ibcon#about to write, iclass 4, count 0 2006.225.08:09:21.83#ibcon#wrote, iclass 4, count 0 2006.225.08:09:21.83#ibcon#about to read 3, iclass 4, count 0 2006.225.08:09:21.86#ibcon#read 3, iclass 4, count 0 2006.225.08:09:21.86#ibcon#about to read 4, iclass 4, count 0 2006.225.08:09:21.86#ibcon#read 4, iclass 4, count 0 2006.225.08:09:21.86#ibcon#about to read 5, iclass 4, count 0 2006.225.08:09:21.86#ibcon#read 5, iclass 4, count 0 2006.225.08:09:21.86#ibcon#about to read 6, iclass 4, count 0 2006.225.08:09:21.86#ibcon#read 6, iclass 4, count 0 2006.225.08:09:21.86#ibcon#end of sib2, iclass 4, count 0 2006.225.08:09:21.86#ibcon#*after write, iclass 4, count 0 2006.225.08:09:21.86#ibcon#*before return 0, iclass 4, count 0 2006.225.08:09:21.86#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:09:21.86#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:09:21.86#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.08:09:21.86#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.08:09:21.86$vc4f8/vblo=5,744.99 2006.225.08:09:21.86#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.08:09:21.86#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.08:09:21.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:21.86#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:09:21.86#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:09:21.86#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:09:21.86#ibcon#enter wrdev, iclass 6, count 0 2006.225.08:09:21.86#ibcon#first serial, iclass 6, count 0 2006.225.08:09:21.86#ibcon#enter sib2, iclass 6, count 0 2006.225.08:09:21.86#ibcon#flushed, iclass 6, count 0 2006.225.08:09:21.86#ibcon#about to write, iclass 6, count 0 2006.225.08:09:21.86#ibcon#wrote, iclass 6, count 0 2006.225.08:09:21.86#ibcon#about to read 3, iclass 6, count 0 2006.225.08:09:21.88#ibcon#read 3, iclass 6, count 0 2006.225.08:09:21.88#ibcon#about to read 4, iclass 6, count 0 2006.225.08:09:21.88#ibcon#read 4, iclass 6, count 0 2006.225.08:09:21.88#ibcon#about to read 5, iclass 6, count 0 2006.225.08:09:21.88#ibcon#read 5, iclass 6, count 0 2006.225.08:09:21.88#ibcon#about to read 6, iclass 6, count 0 2006.225.08:09:21.88#ibcon#read 6, iclass 6, count 0 2006.225.08:09:21.88#ibcon#end of sib2, iclass 6, count 0 2006.225.08:09:21.88#ibcon#*mode == 0, iclass 6, count 0 2006.225.08:09:21.88#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.08:09:21.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:09:21.88#ibcon#*before write, iclass 6, count 0 2006.225.08:09:21.88#ibcon#enter sib2, iclass 6, count 0 2006.225.08:09:21.88#ibcon#flushed, iclass 6, count 0 2006.225.08:09:21.88#ibcon#about to write, iclass 6, count 0 2006.225.08:09:21.88#ibcon#wrote, iclass 6, count 0 2006.225.08:09:21.88#ibcon#about to read 3, iclass 6, count 0 2006.225.08:09:21.92#ibcon#read 3, iclass 6, count 0 2006.225.08:09:21.92#ibcon#about to read 4, iclass 6, count 0 2006.225.08:09:21.92#ibcon#read 4, iclass 6, count 0 2006.225.08:09:21.92#ibcon#about to read 5, iclass 6, count 0 2006.225.08:09:21.92#ibcon#read 5, iclass 6, count 0 2006.225.08:09:21.92#ibcon#about to read 6, iclass 6, count 0 2006.225.08:09:21.92#ibcon#read 6, iclass 6, count 0 2006.225.08:09:21.92#ibcon#end of sib2, iclass 6, count 0 2006.225.08:09:21.92#ibcon#*after write, iclass 6, count 0 2006.225.08:09:21.92#ibcon#*before return 0, iclass 6, count 0 2006.225.08:09:21.92#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:09:21.92#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:09:21.92#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.08:09:21.92#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.08:09:21.92$vc4f8/vb=5,4 2006.225.08:09:21.92#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.225.08:09:21.92#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.225.08:09:21.92#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:21.92#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:09:21.98#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:09:21.98#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:09:21.98#ibcon#enter wrdev, iclass 10, count 2 2006.225.08:09:21.98#ibcon#first serial, iclass 10, count 2 2006.225.08:09:21.98#ibcon#enter sib2, iclass 10, count 2 2006.225.08:09:21.98#ibcon#flushed, iclass 10, count 2 2006.225.08:09:21.98#ibcon#about to write, iclass 10, count 2 2006.225.08:09:21.98#ibcon#wrote, iclass 10, count 2 2006.225.08:09:21.98#ibcon#about to read 3, iclass 10, count 2 2006.225.08:09:22.00#ibcon#read 3, iclass 10, count 2 2006.225.08:09:22.00#ibcon#about to read 4, iclass 10, count 2 2006.225.08:09:22.00#ibcon#read 4, iclass 10, count 2 2006.225.08:09:22.00#ibcon#about to read 5, iclass 10, count 2 2006.225.08:09:22.00#ibcon#read 5, iclass 10, count 2 2006.225.08:09:22.00#ibcon#about to read 6, iclass 10, count 2 2006.225.08:09:22.00#ibcon#read 6, iclass 10, count 2 2006.225.08:09:22.00#ibcon#end of sib2, iclass 10, count 2 2006.225.08:09:22.00#ibcon#*mode == 0, iclass 10, count 2 2006.225.08:09:22.00#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.225.08:09:22.00#ibcon#[27=AT05-04\r\n] 2006.225.08:09:22.00#ibcon#*before write, iclass 10, count 2 2006.225.08:09:22.00#ibcon#enter sib2, iclass 10, count 2 2006.225.08:09:22.00#ibcon#flushed, iclass 10, count 2 2006.225.08:09:22.00#ibcon#about to write, iclass 10, count 2 2006.225.08:09:22.00#ibcon#wrote, iclass 10, count 2 2006.225.08:09:22.00#ibcon#about to read 3, iclass 10, count 2 2006.225.08:09:22.03#ibcon#read 3, iclass 10, count 2 2006.225.08:09:22.03#ibcon#about to read 4, iclass 10, count 2 2006.225.08:09:22.03#ibcon#read 4, iclass 10, count 2 2006.225.08:09:22.03#ibcon#about to read 5, iclass 10, count 2 2006.225.08:09:22.03#ibcon#read 5, iclass 10, count 2 2006.225.08:09:22.03#ibcon#about to read 6, iclass 10, count 2 2006.225.08:09:22.03#ibcon#read 6, iclass 10, count 2 2006.225.08:09:22.03#ibcon#end of sib2, iclass 10, count 2 2006.225.08:09:22.03#ibcon#*after write, iclass 10, count 2 2006.225.08:09:22.03#ibcon#*before return 0, iclass 10, count 2 2006.225.08:09:22.03#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:09:22.03#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:09:22.03#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.225.08:09:22.03#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:22.03#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:09:22.15#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:09:22.15#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:09:22.15#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:09:22.15#ibcon#first serial, iclass 10, count 0 2006.225.08:09:22.15#ibcon#enter sib2, iclass 10, count 0 2006.225.08:09:22.15#ibcon#flushed, iclass 10, count 0 2006.225.08:09:22.15#ibcon#about to write, iclass 10, count 0 2006.225.08:09:22.15#ibcon#wrote, iclass 10, count 0 2006.225.08:09:22.15#ibcon#about to read 3, iclass 10, count 0 2006.225.08:09:22.17#ibcon#read 3, iclass 10, count 0 2006.225.08:09:22.17#ibcon#about to read 4, iclass 10, count 0 2006.225.08:09:22.17#ibcon#read 4, iclass 10, count 0 2006.225.08:09:22.17#ibcon#about to read 5, iclass 10, count 0 2006.225.08:09:22.17#ibcon#read 5, iclass 10, count 0 2006.225.08:09:22.17#ibcon#about to read 6, iclass 10, count 0 2006.225.08:09:22.17#ibcon#read 6, iclass 10, count 0 2006.225.08:09:22.17#ibcon#end of sib2, iclass 10, count 0 2006.225.08:09:22.17#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:09:22.17#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:09:22.17#ibcon#[27=USB\r\n] 2006.225.08:09:22.17#ibcon#*before write, iclass 10, count 0 2006.225.08:09:22.17#ibcon#enter sib2, iclass 10, count 0 2006.225.08:09:22.17#ibcon#flushed, iclass 10, count 0 2006.225.08:09:22.17#ibcon#about to write, iclass 10, count 0 2006.225.08:09:22.17#ibcon#wrote, iclass 10, count 0 2006.225.08:09:22.17#ibcon#about to read 3, iclass 10, count 0 2006.225.08:09:22.20#ibcon#read 3, iclass 10, count 0 2006.225.08:09:22.20#ibcon#about to read 4, iclass 10, count 0 2006.225.08:09:22.20#ibcon#read 4, iclass 10, count 0 2006.225.08:09:22.20#ibcon#about to read 5, iclass 10, count 0 2006.225.08:09:22.20#ibcon#read 5, iclass 10, count 0 2006.225.08:09:22.20#ibcon#about to read 6, iclass 10, count 0 2006.225.08:09:22.20#ibcon#read 6, iclass 10, count 0 2006.225.08:09:22.20#ibcon#end of sib2, iclass 10, count 0 2006.225.08:09:22.20#ibcon#*after write, iclass 10, count 0 2006.225.08:09:22.20#ibcon#*before return 0, iclass 10, count 0 2006.225.08:09:22.20#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:09:22.20#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:09:22.20#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:09:22.20#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:09:22.20$vc4f8/vblo=6,752.99 2006.225.08:09:22.20#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.08:09:22.20#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.08:09:22.20#ibcon#ireg 17 cls_cnt 0 2006.225.08:09:22.20#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:09:22.20#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:09:22.20#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:09:22.20#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:09:22.20#ibcon#first serial, iclass 12, count 0 2006.225.08:09:22.20#ibcon#enter sib2, iclass 12, count 0 2006.225.08:09:22.20#ibcon#flushed, iclass 12, count 0 2006.225.08:09:22.20#ibcon#about to write, iclass 12, count 0 2006.225.08:09:22.20#ibcon#wrote, iclass 12, count 0 2006.225.08:09:22.20#ibcon#about to read 3, iclass 12, count 0 2006.225.08:09:22.22#ibcon#read 3, iclass 12, count 0 2006.225.08:09:22.22#ibcon#about to read 4, iclass 12, count 0 2006.225.08:09:22.22#ibcon#read 4, iclass 12, count 0 2006.225.08:09:22.22#ibcon#about to read 5, iclass 12, count 0 2006.225.08:09:22.22#ibcon#read 5, iclass 12, count 0 2006.225.08:09:22.22#ibcon#about to read 6, iclass 12, count 0 2006.225.08:09:22.22#ibcon#read 6, iclass 12, count 0 2006.225.08:09:22.22#ibcon#end of sib2, iclass 12, count 0 2006.225.08:09:22.22#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:09:22.22#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:09:22.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:09:22.22#ibcon#*before write, iclass 12, count 0 2006.225.08:09:22.22#ibcon#enter sib2, iclass 12, count 0 2006.225.08:09:22.22#ibcon#flushed, iclass 12, count 0 2006.225.08:09:22.22#ibcon#about to write, iclass 12, count 0 2006.225.08:09:22.22#ibcon#wrote, iclass 12, count 0 2006.225.08:09:22.22#ibcon#about to read 3, iclass 12, count 0 2006.225.08:09:22.26#ibcon#read 3, iclass 12, count 0 2006.225.08:09:22.26#ibcon#about to read 4, iclass 12, count 0 2006.225.08:09:22.26#ibcon#read 4, iclass 12, count 0 2006.225.08:09:22.26#ibcon#about to read 5, iclass 12, count 0 2006.225.08:09:22.26#ibcon#read 5, iclass 12, count 0 2006.225.08:09:22.26#ibcon#about to read 6, iclass 12, count 0 2006.225.08:09:22.26#ibcon#read 6, iclass 12, count 0 2006.225.08:09:22.26#ibcon#end of sib2, iclass 12, count 0 2006.225.08:09:22.26#ibcon#*after write, iclass 12, count 0 2006.225.08:09:22.26#ibcon#*before return 0, iclass 12, count 0 2006.225.08:09:22.26#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:09:22.26#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:09:22.26#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:09:22.26#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:09:22.26$vc4f8/vb=6,4 2006.225.08:09:22.26#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.225.08:09:22.26#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.225.08:09:22.26#ibcon#ireg 11 cls_cnt 2 2006.225.08:09:22.26#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:09:22.32#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:09:22.32#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:09:22.32#ibcon#enter wrdev, iclass 14, count 2 2006.225.08:09:22.32#ibcon#first serial, iclass 14, count 2 2006.225.08:09:22.32#ibcon#enter sib2, iclass 14, count 2 2006.225.08:09:22.32#ibcon#flushed, iclass 14, count 2 2006.225.08:09:22.32#ibcon#about to write, iclass 14, count 2 2006.225.08:09:22.32#ibcon#wrote, iclass 14, count 2 2006.225.08:09:22.32#ibcon#about to read 3, iclass 14, count 2 2006.225.08:09:22.34#ibcon#read 3, iclass 14, count 2 2006.225.08:09:22.34#ibcon#about to read 4, iclass 14, count 2 2006.225.08:09:22.34#ibcon#read 4, iclass 14, count 2 2006.225.08:09:22.34#ibcon#about to read 5, iclass 14, count 2 2006.225.08:09:22.34#ibcon#read 5, iclass 14, count 2 2006.225.08:09:22.34#ibcon#about to read 6, iclass 14, count 2 2006.225.08:09:22.34#ibcon#read 6, iclass 14, count 2 2006.225.08:09:22.34#ibcon#end of sib2, iclass 14, count 2 2006.225.08:09:22.34#ibcon#*mode == 0, iclass 14, count 2 2006.225.08:09:22.34#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.225.08:09:22.34#ibcon#[27=AT06-04\r\n] 2006.225.08:09:22.34#ibcon#*before write, iclass 14, count 2 2006.225.08:09:22.34#ibcon#enter sib2, iclass 14, count 2 2006.225.08:09:22.34#ibcon#flushed, iclass 14, count 2 2006.225.08:09:22.34#ibcon#about to write, iclass 14, count 2 2006.225.08:09:22.34#ibcon#wrote, iclass 14, count 2 2006.225.08:09:22.34#ibcon#about to read 3, iclass 14, count 2 2006.225.08:09:22.37#ibcon#read 3, iclass 14, count 2 2006.225.08:09:22.37#ibcon#about to read 4, iclass 14, count 2 2006.225.08:09:22.37#ibcon#read 4, iclass 14, count 2 2006.225.08:09:22.37#ibcon#about to read 5, iclass 14, count 2 2006.225.08:09:22.37#ibcon#read 5, iclass 14, count 2 2006.225.08:09:22.37#ibcon#about to read 6, iclass 14, count 2 2006.225.08:09:22.37#ibcon#read 6, iclass 14, count 2 2006.225.08:09:22.37#ibcon#end of sib2, iclass 14, count 2 2006.225.08:09:22.37#ibcon#*after write, iclass 14, count 2 2006.225.08:09:22.37#ibcon#*before return 0, iclass 14, count 2 2006.225.08:09:22.37#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:09:22.37#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:09:22.37#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.225.08:09:22.37#ibcon#ireg 7 cls_cnt 0 2006.225.08:09:22.37#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:09:22.49#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:09:22.49#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:09:22.49#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:09:22.49#ibcon#first serial, iclass 14, count 0 2006.225.08:09:22.49#ibcon#enter sib2, iclass 14, count 0 2006.225.08:09:22.49#ibcon#flushed, iclass 14, count 0 2006.225.08:09:22.49#ibcon#about to write, iclass 14, count 0 2006.225.08:09:22.49#ibcon#wrote, iclass 14, count 0 2006.225.08:09:22.49#ibcon#about to read 3, iclass 14, count 0 2006.225.08:09:22.51#ibcon#read 3, iclass 14, count 0 2006.225.08:09:22.51#ibcon#about to read 4, iclass 14, count 0 2006.225.08:09:22.51#ibcon#read 4, iclass 14, count 0 2006.225.08:09:22.51#ibcon#about to read 5, iclass 14, count 0 2006.225.08:09:22.51#ibcon#read 5, iclass 14, count 0 2006.225.08:09:22.51#ibcon#about to read 6, iclass 14, count 0 2006.225.08:09:22.51#ibcon#read 6, iclass 14, count 0 2006.225.08:09:22.51#ibcon#end of sib2, iclass 14, count 0 2006.225.08:09:22.51#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:09:22.51#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:09:22.51#ibcon#[27=USB\r\n] 2006.225.08:09:22.51#ibcon#*before write, iclass 14, count 0 2006.225.08:09:22.51#ibcon#enter sib2, iclass 14, count 0 2006.225.08:09:22.51#ibcon#flushed, iclass 14, count 0 2006.225.08:09:22.51#ibcon#about to write, iclass 14, count 0 2006.225.08:09:22.51#ibcon#wrote, iclass 14, count 0 2006.225.08:09:22.51#ibcon#about to read 3, iclass 14, count 0 2006.225.08:09:22.54#ibcon#read 3, iclass 14, count 0 2006.225.08:09:22.54#ibcon#about to read 4, iclass 14, count 0 2006.225.08:09:22.54#ibcon#read 4, iclass 14, count 0 2006.225.08:09:22.54#ibcon#about to read 5, iclass 14, count 0 2006.225.08:09:22.54#ibcon#read 5, iclass 14, count 0 2006.225.08:09:22.54#ibcon#about to read 6, iclass 14, count 0 2006.225.08:09:22.54#ibcon#read 6, iclass 14, count 0 2006.225.08:09:22.54#ibcon#end of sib2, iclass 14, count 0 2006.225.08:09:22.54#ibcon#*after write, iclass 14, count 0 2006.225.08:09:22.54#ibcon#*before return 0, iclass 14, count 0 2006.225.08:09:22.54#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:09:22.54#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:09:22.54#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:09:22.54#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:09:22.54$vc4f8/vabw=wide 2006.225.08:09:22.54#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.08:09:22.54#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.08:09:22.54#ibcon#ireg 8 cls_cnt 0 2006.225.08:09:22.54#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:09:22.54#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:09:22.54#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:09:22.54#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:09:22.54#ibcon#first serial, iclass 16, count 0 2006.225.08:09:22.54#ibcon#enter sib2, iclass 16, count 0 2006.225.08:09:22.54#ibcon#flushed, iclass 16, count 0 2006.225.08:09:22.54#ibcon#about to write, iclass 16, count 0 2006.225.08:09:22.54#ibcon#wrote, iclass 16, count 0 2006.225.08:09:22.54#ibcon#about to read 3, iclass 16, count 0 2006.225.08:09:22.56#ibcon#read 3, iclass 16, count 0 2006.225.08:09:22.56#ibcon#about to read 4, iclass 16, count 0 2006.225.08:09:22.56#ibcon#read 4, iclass 16, count 0 2006.225.08:09:22.56#ibcon#about to read 5, iclass 16, count 0 2006.225.08:09:22.56#ibcon#read 5, iclass 16, count 0 2006.225.08:09:22.56#ibcon#about to read 6, iclass 16, count 0 2006.225.08:09:22.56#ibcon#read 6, iclass 16, count 0 2006.225.08:09:22.56#ibcon#end of sib2, iclass 16, count 0 2006.225.08:09:22.56#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:09:22.56#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:09:22.56#ibcon#[25=BW32\r\n] 2006.225.08:09:22.56#ibcon#*before write, iclass 16, count 0 2006.225.08:09:22.56#ibcon#enter sib2, iclass 16, count 0 2006.225.08:09:22.56#ibcon#flushed, iclass 16, count 0 2006.225.08:09:22.56#ibcon#about to write, iclass 16, count 0 2006.225.08:09:22.56#ibcon#wrote, iclass 16, count 0 2006.225.08:09:22.56#ibcon#about to read 3, iclass 16, count 0 2006.225.08:09:22.59#ibcon#read 3, iclass 16, count 0 2006.225.08:09:22.59#ibcon#about to read 4, iclass 16, count 0 2006.225.08:09:22.59#ibcon#read 4, iclass 16, count 0 2006.225.08:09:22.59#ibcon#about to read 5, iclass 16, count 0 2006.225.08:09:22.59#ibcon#read 5, iclass 16, count 0 2006.225.08:09:22.59#ibcon#about to read 6, iclass 16, count 0 2006.225.08:09:22.59#ibcon#read 6, iclass 16, count 0 2006.225.08:09:22.59#ibcon#end of sib2, iclass 16, count 0 2006.225.08:09:22.59#ibcon#*after write, iclass 16, count 0 2006.225.08:09:22.59#ibcon#*before return 0, iclass 16, count 0 2006.225.08:09:22.59#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:09:22.59#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:09:22.59#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:09:22.59#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:09:22.59$vc4f8/vbbw=wide 2006.225.08:09:22.59#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.08:09:22.59#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.08:09:22.59#ibcon#ireg 8 cls_cnt 0 2006.225.08:09:22.59#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:09:22.66#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:09:22.66#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:09:22.66#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:09:22.66#ibcon#first serial, iclass 18, count 0 2006.225.08:09:22.66#ibcon#enter sib2, iclass 18, count 0 2006.225.08:09:22.66#ibcon#flushed, iclass 18, count 0 2006.225.08:09:22.66#ibcon#about to write, iclass 18, count 0 2006.225.08:09:22.66#ibcon#wrote, iclass 18, count 0 2006.225.08:09:22.66#ibcon#about to read 3, iclass 18, count 0 2006.225.08:09:22.68#ibcon#read 3, iclass 18, count 0 2006.225.08:09:22.68#ibcon#about to read 4, iclass 18, count 0 2006.225.08:09:22.68#ibcon#read 4, iclass 18, count 0 2006.225.08:09:22.68#ibcon#about to read 5, iclass 18, count 0 2006.225.08:09:22.68#ibcon#read 5, iclass 18, count 0 2006.225.08:09:22.68#ibcon#about to read 6, iclass 18, count 0 2006.225.08:09:22.68#ibcon#read 6, iclass 18, count 0 2006.225.08:09:22.68#ibcon#end of sib2, iclass 18, count 0 2006.225.08:09:22.68#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:09:22.68#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:09:22.68#ibcon#[27=BW32\r\n] 2006.225.08:09:22.68#ibcon#*before write, iclass 18, count 0 2006.225.08:09:22.68#ibcon#enter sib2, iclass 18, count 0 2006.225.08:09:22.68#ibcon#flushed, iclass 18, count 0 2006.225.08:09:22.68#ibcon#about to write, iclass 18, count 0 2006.225.08:09:22.68#ibcon#wrote, iclass 18, count 0 2006.225.08:09:22.68#ibcon#about to read 3, iclass 18, count 0 2006.225.08:09:22.71#ibcon#read 3, iclass 18, count 0 2006.225.08:09:22.71#ibcon#about to read 4, iclass 18, count 0 2006.225.08:09:22.71#ibcon#read 4, iclass 18, count 0 2006.225.08:09:22.71#ibcon#about to read 5, iclass 18, count 0 2006.225.08:09:22.71#ibcon#read 5, iclass 18, count 0 2006.225.08:09:22.71#ibcon#about to read 6, iclass 18, count 0 2006.225.08:09:22.71#ibcon#read 6, iclass 18, count 0 2006.225.08:09:22.71#ibcon#end of sib2, iclass 18, count 0 2006.225.08:09:22.71#ibcon#*after write, iclass 18, count 0 2006.225.08:09:22.71#ibcon#*before return 0, iclass 18, count 0 2006.225.08:09:22.71#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:09:22.71#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:09:22.71#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:09:22.71#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:09:22.71$4f8m12a/ifd4f 2006.225.08:09:22.71$ifd4f/lo= 2006.225.08:09:22.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:09:22.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:09:22.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:09:22.71$ifd4f/patch= 2006.225.08:09:22.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:09:22.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:09:22.72$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:09:22.72$4f8m12a/"form=m,16.000,1:2 2006.225.08:09:22.72$4f8m12a/"tpicd 2006.225.08:09:22.72$4f8m12a/echo=off 2006.225.08:09:22.72$4f8m12a/xlog=off 2006.225.08:09:22.72:!2006.225.08:09:50 2006.225.08:09:31.13#trakl#Source acquired 2006.225.08:09:32.13#flagr#flagr/antenna,acquired 2006.225.08:09:50.01:preob 2006.225.08:09:51.14/onsource/TRACKING 2006.225.08:09:51.14:!2006.225.08:10:00 2006.225.08:10:00.00:data_valid=on 2006.225.08:10:00.00:midob 2006.225.08:10:00.14/onsource/TRACKING 2006.225.08:10:00.14/wx/28.11,1003.3,70 2006.225.08:10:00.22/cable/+6.4038E-03 2006.225.08:10:01.31/va/01,08,usb,yes,28,30 2006.225.08:10:01.31/va/02,07,usb,yes,28,30 2006.225.08:10:01.31/va/03,06,usb,yes,30,30 2006.225.08:10:01.31/va/04,07,usb,yes,29,32 2006.225.08:10:01.31/va/05,07,usb,yes,32,34 2006.225.08:10:01.31/va/06,06,usb,yes,31,31 2006.225.08:10:01.31/va/07,06,usb,yes,32,31 2006.225.08:10:01.31/va/08,07,usb,yes,30,29 2006.225.08:10:01.54/valo/01,532.99,yes,locked 2006.225.08:10:01.54/valo/02,572.99,yes,locked 2006.225.08:10:01.54/valo/03,672.99,yes,locked 2006.225.08:10:01.54/valo/04,832.99,yes,locked 2006.225.08:10:01.54/valo/05,652.99,yes,locked 2006.225.08:10:01.54/valo/06,772.99,yes,locked 2006.225.08:10:01.54/valo/07,832.99,yes,locked 2006.225.08:10:01.54/valo/08,852.99,yes,locked 2006.225.08:10:02.63/vb/01,04,usb,yes,30,29 2006.225.08:10:02.63/vb/02,04,usb,yes,32,34 2006.225.08:10:02.63/vb/03,04,usb,yes,28,32 2006.225.08:10:02.63/vb/04,04,usb,yes,29,29 2006.225.08:10:02.63/vb/05,04,usb,yes,28,32 2006.225.08:10:02.63/vb/06,04,usb,yes,29,31 2006.225.08:10:02.63/vb/07,04,usb,yes,31,31 2006.225.08:10:02.63/vb/08,04,usb,yes,28,32 2006.225.08:10:02.87/vblo/01,632.99,yes,locked 2006.225.08:10:02.87/vblo/02,640.99,yes,locked 2006.225.08:10:02.87/vblo/03,656.99,yes,locked 2006.225.08:10:02.87/vblo/04,712.99,yes,locked 2006.225.08:10:02.87/vblo/05,744.99,yes,locked 2006.225.08:10:02.87/vblo/06,752.99,yes,locked 2006.225.08:10:02.87/vblo/07,734.99,yes,locked 2006.225.08:10:02.87/vblo/08,744.99,yes,locked 2006.225.08:10:03.02/vabw/8 2006.225.08:10:03.17/vbbw/8 2006.225.08:10:03.30/xfe/off,on,15.5 2006.225.08:10:03.69/ifatt/23,28,28,28 2006.225.08:10:04.07/fmout-gps/S +4.60E-07 2006.225.08:10:04.15:!2006.225.08:11:00 2006.225.08:11:00.01:data_valid=off 2006.225.08:11:00.02:postob 2006.225.08:11:00.13/cable/+6.4031E-03 2006.225.08:11:00.14/wx/28.10,1003.3,72 2006.225.08:11:01.07/fmout-gps/S +4.60E-07 2006.225.08:11:01.08:scan_name=225-0812,k06225,60 2006.225.08:11:01.08:source=1418+546,141946.60,542314.8,2000.0,ccw 2006.225.08:11:01.14#flagr#flagr/antenna,new-source 2006.225.08:11:02.14:checkk5 2006.225.08:11:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:11:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:11:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:11:03.64/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:11:04.00/chk_obsdata//k5ts1/T2250810??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:11:04.37/chk_obsdata//k5ts2/T2250810??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:11:04.74/chk_obsdata//k5ts3/T2250810??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:11:05.11/chk_obsdata//k5ts4/T2250810??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:11:05.77/k5log//k5ts1_log_newline 2006.225.08:11:06.45/k5log//k5ts2_log_newline 2006.225.08:11:07.14/k5log//k5ts3_log_newline 2006.225.08:11:07.83/k5log//k5ts4_log_newline 2006.225.08:11:07.85/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:11:07.85:4f8m12a=2 2006.225.08:11:07.85$4f8m12a/echo=on 2006.225.08:11:07.85$4f8m12a/pcalon 2006.225.08:11:07.85$pcalon/"no phase cal control is implemented here 2006.225.08:11:07.85$4f8m12a/"tpicd=stop 2006.225.08:11:07.85$4f8m12a/vc4f8 2006.225.08:11:07.85$vc4f8/valo=1,532.99 2006.225.08:11:07.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.225.08:11:07.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.225.08:11:07.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:07.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:11:07.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:11:07.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:11:07.86#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:11:07.86#ibcon#first serial, iclass 25, count 0 2006.225.08:11:07.86#ibcon#enter sib2, iclass 25, count 0 2006.225.08:11:07.86#ibcon#flushed, iclass 25, count 0 2006.225.08:11:07.86#ibcon#about to write, iclass 25, count 0 2006.225.08:11:07.86#ibcon#wrote, iclass 25, count 0 2006.225.08:11:07.86#ibcon#about to read 3, iclass 25, count 0 2006.225.08:11:07.90#ibcon#read 3, iclass 25, count 0 2006.225.08:11:07.90#ibcon#about to read 4, iclass 25, count 0 2006.225.08:11:07.90#ibcon#read 4, iclass 25, count 0 2006.225.08:11:07.90#ibcon#about to read 5, iclass 25, count 0 2006.225.08:11:07.90#ibcon#read 5, iclass 25, count 0 2006.225.08:11:07.90#ibcon#about to read 6, iclass 25, count 0 2006.225.08:11:07.90#ibcon#read 6, iclass 25, count 0 2006.225.08:11:07.90#ibcon#end of sib2, iclass 25, count 0 2006.225.08:11:07.90#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:11:07.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:11:07.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:11:07.90#ibcon#*before write, iclass 25, count 0 2006.225.08:11:07.90#ibcon#enter sib2, iclass 25, count 0 2006.225.08:11:07.90#ibcon#flushed, iclass 25, count 0 2006.225.08:11:07.90#ibcon#about to write, iclass 25, count 0 2006.225.08:11:07.90#ibcon#wrote, iclass 25, count 0 2006.225.08:11:07.90#ibcon#about to read 3, iclass 25, count 0 2006.225.08:11:07.94#ibcon#read 3, iclass 25, count 0 2006.225.08:11:07.94#ibcon#about to read 4, iclass 25, count 0 2006.225.08:11:07.94#ibcon#read 4, iclass 25, count 0 2006.225.08:11:07.94#ibcon#about to read 5, iclass 25, count 0 2006.225.08:11:07.94#ibcon#read 5, iclass 25, count 0 2006.225.08:11:07.94#ibcon#about to read 6, iclass 25, count 0 2006.225.08:11:07.94#ibcon#read 6, iclass 25, count 0 2006.225.08:11:07.94#ibcon#end of sib2, iclass 25, count 0 2006.225.08:11:07.94#ibcon#*after write, iclass 25, count 0 2006.225.08:11:07.94#ibcon#*before return 0, iclass 25, count 0 2006.225.08:11:07.94#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:11:07.94#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:11:07.94#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:11:07.94#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:11:07.94$vc4f8/va=1,8 2006.225.08:11:07.94#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.225.08:11:07.94#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.225.08:11:07.94#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:07.94#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:11:07.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:11:07.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:11:07.94#ibcon#enter wrdev, iclass 27, count 2 2006.225.08:11:07.94#ibcon#first serial, iclass 27, count 2 2006.225.08:11:07.94#ibcon#enter sib2, iclass 27, count 2 2006.225.08:11:07.94#ibcon#flushed, iclass 27, count 2 2006.225.08:11:07.94#ibcon#about to write, iclass 27, count 2 2006.225.08:11:07.94#ibcon#wrote, iclass 27, count 2 2006.225.08:11:07.94#ibcon#about to read 3, iclass 27, count 2 2006.225.08:11:07.96#ibcon#read 3, iclass 27, count 2 2006.225.08:11:07.96#ibcon#about to read 4, iclass 27, count 2 2006.225.08:11:07.96#ibcon#read 4, iclass 27, count 2 2006.225.08:11:07.96#ibcon#about to read 5, iclass 27, count 2 2006.225.08:11:07.96#ibcon#read 5, iclass 27, count 2 2006.225.08:11:07.96#ibcon#about to read 6, iclass 27, count 2 2006.225.08:11:07.96#ibcon#read 6, iclass 27, count 2 2006.225.08:11:07.96#ibcon#end of sib2, iclass 27, count 2 2006.225.08:11:07.96#ibcon#*mode == 0, iclass 27, count 2 2006.225.08:11:07.96#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.225.08:11:07.96#ibcon#[25=AT01-08\r\n] 2006.225.08:11:07.96#ibcon#*before write, iclass 27, count 2 2006.225.08:11:07.96#ibcon#enter sib2, iclass 27, count 2 2006.225.08:11:07.96#ibcon#flushed, iclass 27, count 2 2006.225.08:11:07.96#ibcon#about to write, iclass 27, count 2 2006.225.08:11:07.96#ibcon#wrote, iclass 27, count 2 2006.225.08:11:07.96#ibcon#about to read 3, iclass 27, count 2 2006.225.08:11:07.99#ibcon#read 3, iclass 27, count 2 2006.225.08:11:07.99#ibcon#about to read 4, iclass 27, count 2 2006.225.08:11:07.99#ibcon#read 4, iclass 27, count 2 2006.225.08:11:07.99#ibcon#about to read 5, iclass 27, count 2 2006.225.08:11:07.99#ibcon#read 5, iclass 27, count 2 2006.225.08:11:07.99#ibcon#about to read 6, iclass 27, count 2 2006.225.08:11:07.99#ibcon#read 6, iclass 27, count 2 2006.225.08:11:07.99#ibcon#end of sib2, iclass 27, count 2 2006.225.08:11:07.99#ibcon#*after write, iclass 27, count 2 2006.225.08:11:07.99#ibcon#*before return 0, iclass 27, count 2 2006.225.08:11:07.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:11:07.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:11:07.99#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.225.08:11:07.99#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:07.99#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:11:08.11#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:11:08.11#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:11:08.11#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:11:08.11#ibcon#first serial, iclass 27, count 0 2006.225.08:11:08.11#ibcon#enter sib2, iclass 27, count 0 2006.225.08:11:08.11#ibcon#flushed, iclass 27, count 0 2006.225.08:11:08.11#ibcon#about to write, iclass 27, count 0 2006.225.08:11:08.11#ibcon#wrote, iclass 27, count 0 2006.225.08:11:08.11#ibcon#about to read 3, iclass 27, count 0 2006.225.08:11:08.13#ibcon#read 3, iclass 27, count 0 2006.225.08:11:08.13#ibcon#about to read 4, iclass 27, count 0 2006.225.08:11:08.13#ibcon#read 4, iclass 27, count 0 2006.225.08:11:08.13#ibcon#about to read 5, iclass 27, count 0 2006.225.08:11:08.13#ibcon#read 5, iclass 27, count 0 2006.225.08:11:08.13#ibcon#about to read 6, iclass 27, count 0 2006.225.08:11:08.13#ibcon#read 6, iclass 27, count 0 2006.225.08:11:08.13#ibcon#end of sib2, iclass 27, count 0 2006.225.08:11:08.13#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:11:08.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:11:08.13#ibcon#[25=USB\r\n] 2006.225.08:11:08.13#ibcon#*before write, iclass 27, count 0 2006.225.08:11:08.13#ibcon#enter sib2, iclass 27, count 0 2006.225.08:11:08.13#ibcon#flushed, iclass 27, count 0 2006.225.08:11:08.13#ibcon#about to write, iclass 27, count 0 2006.225.08:11:08.13#ibcon#wrote, iclass 27, count 0 2006.225.08:11:08.13#ibcon#about to read 3, iclass 27, count 0 2006.225.08:11:08.16#ibcon#read 3, iclass 27, count 0 2006.225.08:11:08.16#ibcon#about to read 4, iclass 27, count 0 2006.225.08:11:08.16#ibcon#read 4, iclass 27, count 0 2006.225.08:11:08.16#ibcon#about to read 5, iclass 27, count 0 2006.225.08:11:08.16#ibcon#read 5, iclass 27, count 0 2006.225.08:11:08.16#ibcon#about to read 6, iclass 27, count 0 2006.225.08:11:08.16#ibcon#read 6, iclass 27, count 0 2006.225.08:11:08.16#ibcon#end of sib2, iclass 27, count 0 2006.225.08:11:08.16#ibcon#*after write, iclass 27, count 0 2006.225.08:11:08.16#ibcon#*before return 0, iclass 27, count 0 2006.225.08:11:08.16#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:11:08.16#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:11:08.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:11:08.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:11:08.16$vc4f8/valo=2,572.99 2006.225.08:11:08.16#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.08:11:08.16#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.08:11:08.16#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:08.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:11:08.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:11:08.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:11:08.16#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:11:08.16#ibcon#first serial, iclass 29, count 0 2006.225.08:11:08.16#ibcon#enter sib2, iclass 29, count 0 2006.225.08:11:08.16#ibcon#flushed, iclass 29, count 0 2006.225.08:11:08.16#ibcon#about to write, iclass 29, count 0 2006.225.08:11:08.16#ibcon#wrote, iclass 29, count 0 2006.225.08:11:08.16#ibcon#about to read 3, iclass 29, count 0 2006.225.08:11:08.19#ibcon#read 3, iclass 29, count 0 2006.225.08:11:08.19#ibcon#about to read 4, iclass 29, count 0 2006.225.08:11:08.19#ibcon#read 4, iclass 29, count 0 2006.225.08:11:08.19#ibcon#about to read 5, iclass 29, count 0 2006.225.08:11:08.19#ibcon#read 5, iclass 29, count 0 2006.225.08:11:08.19#ibcon#about to read 6, iclass 29, count 0 2006.225.08:11:08.19#ibcon#read 6, iclass 29, count 0 2006.225.08:11:08.19#ibcon#end of sib2, iclass 29, count 0 2006.225.08:11:08.19#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:11:08.19#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:11:08.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:11:08.19#ibcon#*before write, iclass 29, count 0 2006.225.08:11:08.19#ibcon#enter sib2, iclass 29, count 0 2006.225.08:11:08.19#ibcon#flushed, iclass 29, count 0 2006.225.08:11:08.19#ibcon#about to write, iclass 29, count 0 2006.225.08:11:08.19#ibcon#wrote, iclass 29, count 0 2006.225.08:11:08.19#ibcon#about to read 3, iclass 29, count 0 2006.225.08:11:08.23#ibcon#read 3, iclass 29, count 0 2006.225.08:11:08.23#ibcon#about to read 4, iclass 29, count 0 2006.225.08:11:08.23#ibcon#read 4, iclass 29, count 0 2006.225.08:11:08.23#ibcon#about to read 5, iclass 29, count 0 2006.225.08:11:08.23#ibcon#read 5, iclass 29, count 0 2006.225.08:11:08.23#ibcon#about to read 6, iclass 29, count 0 2006.225.08:11:08.23#ibcon#read 6, iclass 29, count 0 2006.225.08:11:08.23#ibcon#end of sib2, iclass 29, count 0 2006.225.08:11:08.23#ibcon#*after write, iclass 29, count 0 2006.225.08:11:08.23#ibcon#*before return 0, iclass 29, count 0 2006.225.08:11:08.23#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:11:08.23#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:11:08.23#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:11:08.23#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:11:08.23$vc4f8/va=2,7 2006.225.08:11:08.23#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.08:11:08.23#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.08:11:08.23#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:08.23#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:11:08.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:11:08.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:11:08.28#ibcon#enter wrdev, iclass 31, count 2 2006.225.08:11:08.28#ibcon#first serial, iclass 31, count 2 2006.225.08:11:08.28#ibcon#enter sib2, iclass 31, count 2 2006.225.08:11:08.28#ibcon#flushed, iclass 31, count 2 2006.225.08:11:08.28#ibcon#about to write, iclass 31, count 2 2006.225.08:11:08.28#ibcon#wrote, iclass 31, count 2 2006.225.08:11:08.28#ibcon#about to read 3, iclass 31, count 2 2006.225.08:11:08.30#ibcon#read 3, iclass 31, count 2 2006.225.08:11:08.30#ibcon#about to read 4, iclass 31, count 2 2006.225.08:11:08.30#ibcon#read 4, iclass 31, count 2 2006.225.08:11:08.30#ibcon#about to read 5, iclass 31, count 2 2006.225.08:11:08.30#ibcon#read 5, iclass 31, count 2 2006.225.08:11:08.30#ibcon#about to read 6, iclass 31, count 2 2006.225.08:11:08.30#ibcon#read 6, iclass 31, count 2 2006.225.08:11:08.30#ibcon#end of sib2, iclass 31, count 2 2006.225.08:11:08.30#ibcon#*mode == 0, iclass 31, count 2 2006.225.08:11:08.30#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.08:11:08.30#ibcon#[25=AT02-07\r\n] 2006.225.08:11:08.30#ibcon#*before write, iclass 31, count 2 2006.225.08:11:08.30#ibcon#enter sib2, iclass 31, count 2 2006.225.08:11:08.30#ibcon#flushed, iclass 31, count 2 2006.225.08:11:08.30#ibcon#about to write, iclass 31, count 2 2006.225.08:11:08.30#ibcon#wrote, iclass 31, count 2 2006.225.08:11:08.30#ibcon#about to read 3, iclass 31, count 2 2006.225.08:11:08.33#ibcon#read 3, iclass 31, count 2 2006.225.08:11:08.33#ibcon#about to read 4, iclass 31, count 2 2006.225.08:11:08.33#ibcon#read 4, iclass 31, count 2 2006.225.08:11:08.33#ibcon#about to read 5, iclass 31, count 2 2006.225.08:11:08.33#ibcon#read 5, iclass 31, count 2 2006.225.08:11:08.33#ibcon#about to read 6, iclass 31, count 2 2006.225.08:11:08.33#ibcon#read 6, iclass 31, count 2 2006.225.08:11:08.33#ibcon#end of sib2, iclass 31, count 2 2006.225.08:11:08.33#ibcon#*after write, iclass 31, count 2 2006.225.08:11:08.33#ibcon#*before return 0, iclass 31, count 2 2006.225.08:11:08.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:11:08.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:11:08.33#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.08:11:08.33#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:08.33#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:11:08.45#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:11:08.45#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:11:08.45#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:11:08.45#ibcon#first serial, iclass 31, count 0 2006.225.08:11:08.45#ibcon#enter sib2, iclass 31, count 0 2006.225.08:11:08.45#ibcon#flushed, iclass 31, count 0 2006.225.08:11:08.45#ibcon#about to write, iclass 31, count 0 2006.225.08:11:08.45#ibcon#wrote, iclass 31, count 0 2006.225.08:11:08.45#ibcon#about to read 3, iclass 31, count 0 2006.225.08:11:08.47#ibcon#read 3, iclass 31, count 0 2006.225.08:11:08.47#ibcon#about to read 4, iclass 31, count 0 2006.225.08:11:08.47#ibcon#read 4, iclass 31, count 0 2006.225.08:11:08.47#ibcon#about to read 5, iclass 31, count 0 2006.225.08:11:08.47#ibcon#read 5, iclass 31, count 0 2006.225.08:11:08.47#ibcon#about to read 6, iclass 31, count 0 2006.225.08:11:08.47#ibcon#read 6, iclass 31, count 0 2006.225.08:11:08.47#ibcon#end of sib2, iclass 31, count 0 2006.225.08:11:08.47#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:11:08.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:11:08.47#ibcon#[25=USB\r\n] 2006.225.08:11:08.47#ibcon#*before write, iclass 31, count 0 2006.225.08:11:08.47#ibcon#enter sib2, iclass 31, count 0 2006.225.08:11:08.47#ibcon#flushed, iclass 31, count 0 2006.225.08:11:08.47#ibcon#about to write, iclass 31, count 0 2006.225.08:11:08.47#ibcon#wrote, iclass 31, count 0 2006.225.08:11:08.47#ibcon#about to read 3, iclass 31, count 0 2006.225.08:11:08.50#ibcon#read 3, iclass 31, count 0 2006.225.08:11:08.50#ibcon#about to read 4, iclass 31, count 0 2006.225.08:11:08.50#ibcon#read 4, iclass 31, count 0 2006.225.08:11:08.50#ibcon#about to read 5, iclass 31, count 0 2006.225.08:11:08.50#ibcon#read 5, iclass 31, count 0 2006.225.08:11:08.50#ibcon#about to read 6, iclass 31, count 0 2006.225.08:11:08.50#ibcon#read 6, iclass 31, count 0 2006.225.08:11:08.50#ibcon#end of sib2, iclass 31, count 0 2006.225.08:11:08.50#ibcon#*after write, iclass 31, count 0 2006.225.08:11:08.50#ibcon#*before return 0, iclass 31, count 0 2006.225.08:11:08.50#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:11:08.50#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:11:08.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:11:08.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:11:08.50$vc4f8/valo=3,672.99 2006.225.08:11:08.50#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.08:11:08.50#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.08:11:08.50#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:08.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:11:08.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:11:08.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:11:08.50#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:11:08.50#ibcon#first serial, iclass 33, count 0 2006.225.08:11:08.50#ibcon#enter sib2, iclass 33, count 0 2006.225.08:11:08.50#ibcon#flushed, iclass 33, count 0 2006.225.08:11:08.50#ibcon#about to write, iclass 33, count 0 2006.225.08:11:08.50#ibcon#wrote, iclass 33, count 0 2006.225.08:11:08.50#ibcon#about to read 3, iclass 33, count 0 2006.225.08:11:08.53#ibcon#read 3, iclass 33, count 0 2006.225.08:11:08.53#ibcon#about to read 4, iclass 33, count 0 2006.225.08:11:08.53#ibcon#read 4, iclass 33, count 0 2006.225.08:11:08.53#ibcon#about to read 5, iclass 33, count 0 2006.225.08:11:08.53#ibcon#read 5, iclass 33, count 0 2006.225.08:11:08.53#ibcon#about to read 6, iclass 33, count 0 2006.225.08:11:08.53#ibcon#read 6, iclass 33, count 0 2006.225.08:11:08.53#ibcon#end of sib2, iclass 33, count 0 2006.225.08:11:08.53#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:11:08.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:11:08.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:11:08.53#ibcon#*before write, iclass 33, count 0 2006.225.08:11:08.53#ibcon#enter sib2, iclass 33, count 0 2006.225.08:11:08.53#ibcon#flushed, iclass 33, count 0 2006.225.08:11:08.53#ibcon#about to write, iclass 33, count 0 2006.225.08:11:08.53#ibcon#wrote, iclass 33, count 0 2006.225.08:11:08.53#ibcon#about to read 3, iclass 33, count 0 2006.225.08:11:08.57#ibcon#read 3, iclass 33, count 0 2006.225.08:11:08.57#ibcon#about to read 4, iclass 33, count 0 2006.225.08:11:08.57#ibcon#read 4, iclass 33, count 0 2006.225.08:11:08.57#ibcon#about to read 5, iclass 33, count 0 2006.225.08:11:08.57#ibcon#read 5, iclass 33, count 0 2006.225.08:11:08.57#ibcon#about to read 6, iclass 33, count 0 2006.225.08:11:08.57#ibcon#read 6, iclass 33, count 0 2006.225.08:11:08.57#ibcon#end of sib2, iclass 33, count 0 2006.225.08:11:08.57#ibcon#*after write, iclass 33, count 0 2006.225.08:11:08.57#ibcon#*before return 0, iclass 33, count 0 2006.225.08:11:08.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:11:08.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:11:08.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:11:08.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:11:08.57$vc4f8/va=3,6 2006.225.08:11:08.57#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.08:11:08.57#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.08:11:08.57#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:08.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:11:08.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:11:08.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:11:08.62#ibcon#enter wrdev, iclass 35, count 2 2006.225.08:11:08.62#ibcon#first serial, iclass 35, count 2 2006.225.08:11:08.62#ibcon#enter sib2, iclass 35, count 2 2006.225.08:11:08.62#ibcon#flushed, iclass 35, count 2 2006.225.08:11:08.62#ibcon#about to write, iclass 35, count 2 2006.225.08:11:08.62#ibcon#wrote, iclass 35, count 2 2006.225.08:11:08.62#ibcon#about to read 3, iclass 35, count 2 2006.225.08:11:08.64#ibcon#read 3, iclass 35, count 2 2006.225.08:11:08.64#ibcon#about to read 4, iclass 35, count 2 2006.225.08:11:08.64#ibcon#read 4, iclass 35, count 2 2006.225.08:11:08.64#ibcon#about to read 5, iclass 35, count 2 2006.225.08:11:08.64#ibcon#read 5, iclass 35, count 2 2006.225.08:11:08.64#ibcon#about to read 6, iclass 35, count 2 2006.225.08:11:08.64#ibcon#read 6, iclass 35, count 2 2006.225.08:11:08.64#ibcon#end of sib2, iclass 35, count 2 2006.225.08:11:08.64#ibcon#*mode == 0, iclass 35, count 2 2006.225.08:11:08.64#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.08:11:08.64#ibcon#[25=AT03-06\r\n] 2006.225.08:11:08.64#ibcon#*before write, iclass 35, count 2 2006.225.08:11:08.64#ibcon#enter sib2, iclass 35, count 2 2006.225.08:11:08.64#ibcon#flushed, iclass 35, count 2 2006.225.08:11:08.64#ibcon#about to write, iclass 35, count 2 2006.225.08:11:08.64#ibcon#wrote, iclass 35, count 2 2006.225.08:11:08.64#ibcon#about to read 3, iclass 35, count 2 2006.225.08:11:08.67#ibcon#read 3, iclass 35, count 2 2006.225.08:11:08.67#ibcon#about to read 4, iclass 35, count 2 2006.225.08:11:08.67#ibcon#read 4, iclass 35, count 2 2006.225.08:11:08.67#ibcon#about to read 5, iclass 35, count 2 2006.225.08:11:08.67#ibcon#read 5, iclass 35, count 2 2006.225.08:11:08.67#ibcon#about to read 6, iclass 35, count 2 2006.225.08:11:08.67#ibcon#read 6, iclass 35, count 2 2006.225.08:11:08.67#ibcon#end of sib2, iclass 35, count 2 2006.225.08:11:08.67#ibcon#*after write, iclass 35, count 2 2006.225.08:11:08.67#ibcon#*before return 0, iclass 35, count 2 2006.225.08:11:08.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:11:08.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:11:08.67#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.08:11:08.67#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:08.67#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:11:08.79#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:11:08.79#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:11:08.79#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:11:08.79#ibcon#first serial, iclass 35, count 0 2006.225.08:11:08.79#ibcon#enter sib2, iclass 35, count 0 2006.225.08:11:08.79#ibcon#flushed, iclass 35, count 0 2006.225.08:11:08.79#ibcon#about to write, iclass 35, count 0 2006.225.08:11:08.79#ibcon#wrote, iclass 35, count 0 2006.225.08:11:08.79#ibcon#about to read 3, iclass 35, count 0 2006.225.08:11:08.81#ibcon#read 3, iclass 35, count 0 2006.225.08:11:08.81#ibcon#about to read 4, iclass 35, count 0 2006.225.08:11:08.81#ibcon#read 4, iclass 35, count 0 2006.225.08:11:08.81#ibcon#about to read 5, iclass 35, count 0 2006.225.08:11:08.81#ibcon#read 5, iclass 35, count 0 2006.225.08:11:08.81#ibcon#about to read 6, iclass 35, count 0 2006.225.08:11:08.81#ibcon#read 6, iclass 35, count 0 2006.225.08:11:08.81#ibcon#end of sib2, iclass 35, count 0 2006.225.08:11:08.81#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:11:08.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:11:08.81#ibcon#[25=USB\r\n] 2006.225.08:11:08.81#ibcon#*before write, iclass 35, count 0 2006.225.08:11:08.81#ibcon#enter sib2, iclass 35, count 0 2006.225.08:11:08.81#ibcon#flushed, iclass 35, count 0 2006.225.08:11:08.81#ibcon#about to write, iclass 35, count 0 2006.225.08:11:08.81#ibcon#wrote, iclass 35, count 0 2006.225.08:11:08.81#ibcon#about to read 3, iclass 35, count 0 2006.225.08:11:08.84#ibcon#read 3, iclass 35, count 0 2006.225.08:11:08.84#ibcon#about to read 4, iclass 35, count 0 2006.225.08:11:08.84#ibcon#read 4, iclass 35, count 0 2006.225.08:11:08.84#ibcon#about to read 5, iclass 35, count 0 2006.225.08:11:08.84#ibcon#read 5, iclass 35, count 0 2006.225.08:11:08.84#ibcon#about to read 6, iclass 35, count 0 2006.225.08:11:08.84#ibcon#read 6, iclass 35, count 0 2006.225.08:11:08.84#ibcon#end of sib2, iclass 35, count 0 2006.225.08:11:08.84#ibcon#*after write, iclass 35, count 0 2006.225.08:11:08.84#ibcon#*before return 0, iclass 35, count 0 2006.225.08:11:08.84#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:11:08.84#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:11:08.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:11:08.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:11:08.84$vc4f8/valo=4,832.99 2006.225.08:11:08.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.08:11:08.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.08:11:08.84#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:08.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:11:08.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:11:08.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:11:08.84#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:11:08.84#ibcon#first serial, iclass 37, count 0 2006.225.08:11:08.84#ibcon#enter sib2, iclass 37, count 0 2006.225.08:11:08.84#ibcon#flushed, iclass 37, count 0 2006.225.08:11:08.84#ibcon#about to write, iclass 37, count 0 2006.225.08:11:08.84#ibcon#wrote, iclass 37, count 0 2006.225.08:11:08.84#ibcon#about to read 3, iclass 37, count 0 2006.225.08:11:08.86#ibcon#read 3, iclass 37, count 0 2006.225.08:11:08.86#ibcon#about to read 4, iclass 37, count 0 2006.225.08:11:08.86#ibcon#read 4, iclass 37, count 0 2006.225.08:11:08.86#ibcon#about to read 5, iclass 37, count 0 2006.225.08:11:08.86#ibcon#read 5, iclass 37, count 0 2006.225.08:11:08.86#ibcon#about to read 6, iclass 37, count 0 2006.225.08:11:08.86#ibcon#read 6, iclass 37, count 0 2006.225.08:11:08.86#ibcon#end of sib2, iclass 37, count 0 2006.225.08:11:08.86#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:11:08.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:11:08.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:11:08.86#ibcon#*before write, iclass 37, count 0 2006.225.08:11:08.86#ibcon#enter sib2, iclass 37, count 0 2006.225.08:11:08.86#ibcon#flushed, iclass 37, count 0 2006.225.08:11:08.86#ibcon#about to write, iclass 37, count 0 2006.225.08:11:08.86#ibcon#wrote, iclass 37, count 0 2006.225.08:11:08.86#ibcon#about to read 3, iclass 37, count 0 2006.225.08:11:08.90#ibcon#read 3, iclass 37, count 0 2006.225.08:11:08.90#ibcon#about to read 4, iclass 37, count 0 2006.225.08:11:08.90#ibcon#read 4, iclass 37, count 0 2006.225.08:11:08.90#ibcon#about to read 5, iclass 37, count 0 2006.225.08:11:08.90#ibcon#read 5, iclass 37, count 0 2006.225.08:11:08.90#ibcon#about to read 6, iclass 37, count 0 2006.225.08:11:08.90#ibcon#read 6, iclass 37, count 0 2006.225.08:11:08.90#ibcon#end of sib2, iclass 37, count 0 2006.225.08:11:08.90#ibcon#*after write, iclass 37, count 0 2006.225.08:11:08.90#ibcon#*before return 0, iclass 37, count 0 2006.225.08:11:08.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:11:08.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:11:08.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:11:08.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:11:08.90$vc4f8/va=4,7 2006.225.08:11:08.90#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.08:11:08.90#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.08:11:08.90#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:08.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:11:08.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:11:08.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:11:08.96#ibcon#enter wrdev, iclass 39, count 2 2006.225.08:11:08.96#ibcon#first serial, iclass 39, count 2 2006.225.08:11:08.96#ibcon#enter sib2, iclass 39, count 2 2006.225.08:11:08.96#ibcon#flushed, iclass 39, count 2 2006.225.08:11:08.96#ibcon#about to write, iclass 39, count 2 2006.225.08:11:08.96#ibcon#wrote, iclass 39, count 2 2006.225.08:11:08.96#ibcon#about to read 3, iclass 39, count 2 2006.225.08:11:08.98#ibcon#read 3, iclass 39, count 2 2006.225.08:11:08.98#ibcon#about to read 4, iclass 39, count 2 2006.225.08:11:08.98#ibcon#read 4, iclass 39, count 2 2006.225.08:11:08.98#ibcon#about to read 5, iclass 39, count 2 2006.225.08:11:08.98#ibcon#read 5, iclass 39, count 2 2006.225.08:11:08.98#ibcon#about to read 6, iclass 39, count 2 2006.225.08:11:08.98#ibcon#read 6, iclass 39, count 2 2006.225.08:11:08.98#ibcon#end of sib2, iclass 39, count 2 2006.225.08:11:08.98#ibcon#*mode == 0, iclass 39, count 2 2006.225.08:11:08.98#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.08:11:08.98#ibcon#[25=AT04-07\r\n] 2006.225.08:11:08.98#ibcon#*before write, iclass 39, count 2 2006.225.08:11:08.98#ibcon#enter sib2, iclass 39, count 2 2006.225.08:11:08.98#ibcon#flushed, iclass 39, count 2 2006.225.08:11:08.98#ibcon#about to write, iclass 39, count 2 2006.225.08:11:08.98#ibcon#wrote, iclass 39, count 2 2006.225.08:11:08.98#ibcon#about to read 3, iclass 39, count 2 2006.225.08:11:09.01#ibcon#read 3, iclass 39, count 2 2006.225.08:11:09.01#ibcon#about to read 4, iclass 39, count 2 2006.225.08:11:09.01#ibcon#read 4, iclass 39, count 2 2006.225.08:11:09.01#ibcon#about to read 5, iclass 39, count 2 2006.225.08:11:09.01#ibcon#read 5, iclass 39, count 2 2006.225.08:11:09.01#ibcon#about to read 6, iclass 39, count 2 2006.225.08:11:09.01#ibcon#read 6, iclass 39, count 2 2006.225.08:11:09.01#ibcon#end of sib2, iclass 39, count 2 2006.225.08:11:09.01#ibcon#*after write, iclass 39, count 2 2006.225.08:11:09.01#ibcon#*before return 0, iclass 39, count 2 2006.225.08:11:09.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:11:09.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:11:09.01#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.08:11:09.01#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:09.01#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:11:09.13#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:11:09.13#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:11:09.13#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:11:09.13#ibcon#first serial, iclass 39, count 0 2006.225.08:11:09.13#ibcon#enter sib2, iclass 39, count 0 2006.225.08:11:09.13#ibcon#flushed, iclass 39, count 0 2006.225.08:11:09.13#ibcon#about to write, iclass 39, count 0 2006.225.08:11:09.13#ibcon#wrote, iclass 39, count 0 2006.225.08:11:09.13#ibcon#about to read 3, iclass 39, count 0 2006.225.08:11:09.15#ibcon#read 3, iclass 39, count 0 2006.225.08:11:09.15#ibcon#about to read 4, iclass 39, count 0 2006.225.08:11:09.15#ibcon#read 4, iclass 39, count 0 2006.225.08:11:09.15#ibcon#about to read 5, iclass 39, count 0 2006.225.08:11:09.15#ibcon#read 5, iclass 39, count 0 2006.225.08:11:09.15#ibcon#about to read 6, iclass 39, count 0 2006.225.08:11:09.15#ibcon#read 6, iclass 39, count 0 2006.225.08:11:09.15#ibcon#end of sib2, iclass 39, count 0 2006.225.08:11:09.15#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:11:09.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:11:09.15#ibcon#[25=USB\r\n] 2006.225.08:11:09.15#ibcon#*before write, iclass 39, count 0 2006.225.08:11:09.15#ibcon#enter sib2, iclass 39, count 0 2006.225.08:11:09.15#ibcon#flushed, iclass 39, count 0 2006.225.08:11:09.15#ibcon#about to write, iclass 39, count 0 2006.225.08:11:09.15#ibcon#wrote, iclass 39, count 0 2006.225.08:11:09.15#ibcon#about to read 3, iclass 39, count 0 2006.225.08:11:09.18#ibcon#read 3, iclass 39, count 0 2006.225.08:11:09.18#ibcon#about to read 4, iclass 39, count 0 2006.225.08:11:09.18#ibcon#read 4, iclass 39, count 0 2006.225.08:11:09.18#ibcon#about to read 5, iclass 39, count 0 2006.225.08:11:09.18#ibcon#read 5, iclass 39, count 0 2006.225.08:11:09.18#ibcon#about to read 6, iclass 39, count 0 2006.225.08:11:09.18#ibcon#read 6, iclass 39, count 0 2006.225.08:11:09.18#ibcon#end of sib2, iclass 39, count 0 2006.225.08:11:09.18#ibcon#*after write, iclass 39, count 0 2006.225.08:11:09.18#ibcon#*before return 0, iclass 39, count 0 2006.225.08:11:09.18#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:11:09.18#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:11:09.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:11:09.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:11:09.18$vc4f8/valo=5,652.99 2006.225.08:11:09.18#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.08:11:09.18#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.08:11:09.18#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:09.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:11:09.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:11:09.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:11:09.18#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:11:09.18#ibcon#first serial, iclass 3, count 0 2006.225.08:11:09.18#ibcon#enter sib2, iclass 3, count 0 2006.225.08:11:09.18#ibcon#flushed, iclass 3, count 0 2006.225.08:11:09.18#ibcon#about to write, iclass 3, count 0 2006.225.08:11:09.18#ibcon#wrote, iclass 3, count 0 2006.225.08:11:09.18#ibcon#about to read 3, iclass 3, count 0 2006.225.08:11:09.20#ibcon#read 3, iclass 3, count 0 2006.225.08:11:09.20#ibcon#about to read 4, iclass 3, count 0 2006.225.08:11:09.20#ibcon#read 4, iclass 3, count 0 2006.225.08:11:09.20#ibcon#about to read 5, iclass 3, count 0 2006.225.08:11:09.20#ibcon#read 5, iclass 3, count 0 2006.225.08:11:09.20#ibcon#about to read 6, iclass 3, count 0 2006.225.08:11:09.20#ibcon#read 6, iclass 3, count 0 2006.225.08:11:09.20#ibcon#end of sib2, iclass 3, count 0 2006.225.08:11:09.20#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:11:09.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:11:09.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:11:09.20#ibcon#*before write, iclass 3, count 0 2006.225.08:11:09.20#ibcon#enter sib2, iclass 3, count 0 2006.225.08:11:09.20#ibcon#flushed, iclass 3, count 0 2006.225.08:11:09.20#ibcon#about to write, iclass 3, count 0 2006.225.08:11:09.20#ibcon#wrote, iclass 3, count 0 2006.225.08:11:09.20#ibcon#about to read 3, iclass 3, count 0 2006.225.08:11:09.24#ibcon#read 3, iclass 3, count 0 2006.225.08:11:09.24#ibcon#about to read 4, iclass 3, count 0 2006.225.08:11:09.24#ibcon#read 4, iclass 3, count 0 2006.225.08:11:09.24#ibcon#about to read 5, iclass 3, count 0 2006.225.08:11:09.24#ibcon#read 5, iclass 3, count 0 2006.225.08:11:09.24#ibcon#about to read 6, iclass 3, count 0 2006.225.08:11:09.24#ibcon#read 6, iclass 3, count 0 2006.225.08:11:09.24#ibcon#end of sib2, iclass 3, count 0 2006.225.08:11:09.24#ibcon#*after write, iclass 3, count 0 2006.225.08:11:09.24#ibcon#*before return 0, iclass 3, count 0 2006.225.08:11:09.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:11:09.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:11:09.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:11:09.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:11:09.24$vc4f8/va=5,7 2006.225.08:11:09.24#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.08:11:09.24#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.08:11:09.24#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:09.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:11:09.30#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:11:09.30#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:11:09.30#ibcon#enter wrdev, iclass 5, count 2 2006.225.08:11:09.30#ibcon#first serial, iclass 5, count 2 2006.225.08:11:09.30#ibcon#enter sib2, iclass 5, count 2 2006.225.08:11:09.30#ibcon#flushed, iclass 5, count 2 2006.225.08:11:09.30#ibcon#about to write, iclass 5, count 2 2006.225.08:11:09.30#ibcon#wrote, iclass 5, count 2 2006.225.08:11:09.30#ibcon#about to read 3, iclass 5, count 2 2006.225.08:11:09.32#ibcon#read 3, iclass 5, count 2 2006.225.08:11:09.32#ibcon#about to read 4, iclass 5, count 2 2006.225.08:11:09.32#ibcon#read 4, iclass 5, count 2 2006.225.08:11:09.32#ibcon#about to read 5, iclass 5, count 2 2006.225.08:11:09.32#ibcon#read 5, iclass 5, count 2 2006.225.08:11:09.32#ibcon#about to read 6, iclass 5, count 2 2006.225.08:11:09.32#ibcon#read 6, iclass 5, count 2 2006.225.08:11:09.32#ibcon#end of sib2, iclass 5, count 2 2006.225.08:11:09.32#ibcon#*mode == 0, iclass 5, count 2 2006.225.08:11:09.32#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.08:11:09.32#ibcon#[25=AT05-07\r\n] 2006.225.08:11:09.32#ibcon#*before write, iclass 5, count 2 2006.225.08:11:09.32#ibcon#enter sib2, iclass 5, count 2 2006.225.08:11:09.32#ibcon#flushed, iclass 5, count 2 2006.225.08:11:09.32#ibcon#about to write, iclass 5, count 2 2006.225.08:11:09.32#ibcon#wrote, iclass 5, count 2 2006.225.08:11:09.32#ibcon#about to read 3, iclass 5, count 2 2006.225.08:11:09.35#ibcon#read 3, iclass 5, count 2 2006.225.08:11:09.35#ibcon#about to read 4, iclass 5, count 2 2006.225.08:11:09.35#ibcon#read 4, iclass 5, count 2 2006.225.08:11:09.35#ibcon#about to read 5, iclass 5, count 2 2006.225.08:11:09.35#ibcon#read 5, iclass 5, count 2 2006.225.08:11:09.35#ibcon#about to read 6, iclass 5, count 2 2006.225.08:11:09.35#ibcon#read 6, iclass 5, count 2 2006.225.08:11:09.35#ibcon#end of sib2, iclass 5, count 2 2006.225.08:11:09.35#ibcon#*after write, iclass 5, count 2 2006.225.08:11:09.35#ibcon#*before return 0, iclass 5, count 2 2006.225.08:11:09.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:11:09.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:11:09.35#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.08:11:09.35#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:09.35#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:11:09.47#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:11:09.47#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:11:09.47#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:11:09.47#ibcon#first serial, iclass 5, count 0 2006.225.08:11:09.47#ibcon#enter sib2, iclass 5, count 0 2006.225.08:11:09.47#ibcon#flushed, iclass 5, count 0 2006.225.08:11:09.47#ibcon#about to write, iclass 5, count 0 2006.225.08:11:09.47#ibcon#wrote, iclass 5, count 0 2006.225.08:11:09.47#ibcon#about to read 3, iclass 5, count 0 2006.225.08:11:09.49#ibcon#read 3, iclass 5, count 0 2006.225.08:11:09.49#ibcon#about to read 4, iclass 5, count 0 2006.225.08:11:09.49#ibcon#read 4, iclass 5, count 0 2006.225.08:11:09.49#ibcon#about to read 5, iclass 5, count 0 2006.225.08:11:09.49#ibcon#read 5, iclass 5, count 0 2006.225.08:11:09.49#ibcon#about to read 6, iclass 5, count 0 2006.225.08:11:09.49#ibcon#read 6, iclass 5, count 0 2006.225.08:11:09.49#ibcon#end of sib2, iclass 5, count 0 2006.225.08:11:09.49#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:11:09.49#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:11:09.49#ibcon#[25=USB\r\n] 2006.225.08:11:09.49#ibcon#*before write, iclass 5, count 0 2006.225.08:11:09.49#ibcon#enter sib2, iclass 5, count 0 2006.225.08:11:09.49#ibcon#flushed, iclass 5, count 0 2006.225.08:11:09.49#ibcon#about to write, iclass 5, count 0 2006.225.08:11:09.49#ibcon#wrote, iclass 5, count 0 2006.225.08:11:09.49#ibcon#about to read 3, iclass 5, count 0 2006.225.08:11:09.52#ibcon#read 3, iclass 5, count 0 2006.225.08:11:09.52#ibcon#about to read 4, iclass 5, count 0 2006.225.08:11:09.52#ibcon#read 4, iclass 5, count 0 2006.225.08:11:09.52#ibcon#about to read 5, iclass 5, count 0 2006.225.08:11:09.52#ibcon#read 5, iclass 5, count 0 2006.225.08:11:09.52#ibcon#about to read 6, iclass 5, count 0 2006.225.08:11:09.52#ibcon#read 6, iclass 5, count 0 2006.225.08:11:09.52#ibcon#end of sib2, iclass 5, count 0 2006.225.08:11:09.52#ibcon#*after write, iclass 5, count 0 2006.225.08:11:09.52#ibcon#*before return 0, iclass 5, count 0 2006.225.08:11:09.52#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:11:09.52#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:11:09.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:11:09.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:11:09.52$vc4f8/valo=6,772.99 2006.225.08:11:09.52#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.225.08:11:09.52#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.225.08:11:09.52#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:09.52#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:11:09.52#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:11:09.52#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:11:09.52#ibcon#enter wrdev, iclass 7, count 0 2006.225.08:11:09.52#ibcon#first serial, iclass 7, count 0 2006.225.08:11:09.52#ibcon#enter sib2, iclass 7, count 0 2006.225.08:11:09.52#ibcon#flushed, iclass 7, count 0 2006.225.08:11:09.52#ibcon#about to write, iclass 7, count 0 2006.225.08:11:09.52#ibcon#wrote, iclass 7, count 0 2006.225.08:11:09.52#ibcon#about to read 3, iclass 7, count 0 2006.225.08:11:09.54#ibcon#read 3, iclass 7, count 0 2006.225.08:11:09.54#ibcon#about to read 4, iclass 7, count 0 2006.225.08:11:09.54#ibcon#read 4, iclass 7, count 0 2006.225.08:11:09.54#ibcon#about to read 5, iclass 7, count 0 2006.225.08:11:09.54#ibcon#read 5, iclass 7, count 0 2006.225.08:11:09.54#ibcon#about to read 6, iclass 7, count 0 2006.225.08:11:09.54#ibcon#read 6, iclass 7, count 0 2006.225.08:11:09.54#ibcon#end of sib2, iclass 7, count 0 2006.225.08:11:09.54#ibcon#*mode == 0, iclass 7, count 0 2006.225.08:11:09.54#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.08:11:09.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:11:09.54#ibcon#*before write, iclass 7, count 0 2006.225.08:11:09.54#ibcon#enter sib2, iclass 7, count 0 2006.225.08:11:09.54#ibcon#flushed, iclass 7, count 0 2006.225.08:11:09.54#ibcon#about to write, iclass 7, count 0 2006.225.08:11:09.54#ibcon#wrote, iclass 7, count 0 2006.225.08:11:09.54#ibcon#about to read 3, iclass 7, count 0 2006.225.08:11:09.58#ibcon#read 3, iclass 7, count 0 2006.225.08:11:09.58#ibcon#about to read 4, iclass 7, count 0 2006.225.08:11:09.58#ibcon#read 4, iclass 7, count 0 2006.225.08:11:09.58#ibcon#about to read 5, iclass 7, count 0 2006.225.08:11:09.58#ibcon#read 5, iclass 7, count 0 2006.225.08:11:09.58#ibcon#about to read 6, iclass 7, count 0 2006.225.08:11:09.58#ibcon#read 6, iclass 7, count 0 2006.225.08:11:09.58#ibcon#end of sib2, iclass 7, count 0 2006.225.08:11:09.58#ibcon#*after write, iclass 7, count 0 2006.225.08:11:09.58#ibcon#*before return 0, iclass 7, count 0 2006.225.08:11:09.58#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:11:09.58#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:11:09.58#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.08:11:09.58#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.08:11:09.58$vc4f8/va=6,6 2006.225.08:11:09.58#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.225.08:11:09.58#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.225.08:11:09.58#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:09.58#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:11:09.64#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:11:09.64#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:11:09.64#ibcon#enter wrdev, iclass 11, count 2 2006.225.08:11:09.64#ibcon#first serial, iclass 11, count 2 2006.225.08:11:09.64#ibcon#enter sib2, iclass 11, count 2 2006.225.08:11:09.64#ibcon#flushed, iclass 11, count 2 2006.225.08:11:09.64#ibcon#about to write, iclass 11, count 2 2006.225.08:11:09.64#ibcon#wrote, iclass 11, count 2 2006.225.08:11:09.64#ibcon#about to read 3, iclass 11, count 2 2006.225.08:11:09.66#ibcon#read 3, iclass 11, count 2 2006.225.08:11:09.66#ibcon#about to read 4, iclass 11, count 2 2006.225.08:11:09.66#ibcon#read 4, iclass 11, count 2 2006.225.08:11:09.66#ibcon#about to read 5, iclass 11, count 2 2006.225.08:11:09.66#ibcon#read 5, iclass 11, count 2 2006.225.08:11:09.66#ibcon#about to read 6, iclass 11, count 2 2006.225.08:11:09.66#ibcon#read 6, iclass 11, count 2 2006.225.08:11:09.66#ibcon#end of sib2, iclass 11, count 2 2006.225.08:11:09.66#ibcon#*mode == 0, iclass 11, count 2 2006.225.08:11:09.66#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.225.08:11:09.66#ibcon#[25=AT06-06\r\n] 2006.225.08:11:09.66#ibcon#*before write, iclass 11, count 2 2006.225.08:11:09.66#ibcon#enter sib2, iclass 11, count 2 2006.225.08:11:09.66#ibcon#flushed, iclass 11, count 2 2006.225.08:11:09.66#ibcon#about to write, iclass 11, count 2 2006.225.08:11:09.66#ibcon#wrote, iclass 11, count 2 2006.225.08:11:09.66#ibcon#about to read 3, iclass 11, count 2 2006.225.08:11:09.69#ibcon#read 3, iclass 11, count 2 2006.225.08:11:09.69#ibcon#about to read 4, iclass 11, count 2 2006.225.08:11:09.69#ibcon#read 4, iclass 11, count 2 2006.225.08:11:09.69#ibcon#about to read 5, iclass 11, count 2 2006.225.08:11:09.69#ibcon#read 5, iclass 11, count 2 2006.225.08:11:09.69#ibcon#about to read 6, iclass 11, count 2 2006.225.08:11:09.69#ibcon#read 6, iclass 11, count 2 2006.225.08:11:09.69#ibcon#end of sib2, iclass 11, count 2 2006.225.08:11:09.69#ibcon#*after write, iclass 11, count 2 2006.225.08:11:09.69#ibcon#*before return 0, iclass 11, count 2 2006.225.08:11:09.69#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:11:09.69#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:11:09.69#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.225.08:11:09.69#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:09.69#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:11:09.81#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:11:09.81#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:11:09.81#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:11:09.81#ibcon#first serial, iclass 11, count 0 2006.225.08:11:09.81#ibcon#enter sib2, iclass 11, count 0 2006.225.08:11:09.81#ibcon#flushed, iclass 11, count 0 2006.225.08:11:09.81#ibcon#about to write, iclass 11, count 0 2006.225.08:11:09.81#ibcon#wrote, iclass 11, count 0 2006.225.08:11:09.81#ibcon#about to read 3, iclass 11, count 0 2006.225.08:11:09.83#ibcon#read 3, iclass 11, count 0 2006.225.08:11:09.83#ibcon#about to read 4, iclass 11, count 0 2006.225.08:11:09.83#ibcon#read 4, iclass 11, count 0 2006.225.08:11:09.83#ibcon#about to read 5, iclass 11, count 0 2006.225.08:11:09.83#ibcon#read 5, iclass 11, count 0 2006.225.08:11:09.83#ibcon#about to read 6, iclass 11, count 0 2006.225.08:11:09.83#ibcon#read 6, iclass 11, count 0 2006.225.08:11:09.83#ibcon#end of sib2, iclass 11, count 0 2006.225.08:11:09.83#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:11:09.83#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:11:09.83#ibcon#[25=USB\r\n] 2006.225.08:11:09.83#ibcon#*before write, iclass 11, count 0 2006.225.08:11:09.83#ibcon#enter sib2, iclass 11, count 0 2006.225.08:11:09.83#ibcon#flushed, iclass 11, count 0 2006.225.08:11:09.83#ibcon#about to write, iclass 11, count 0 2006.225.08:11:09.83#ibcon#wrote, iclass 11, count 0 2006.225.08:11:09.83#ibcon#about to read 3, iclass 11, count 0 2006.225.08:11:09.86#ibcon#read 3, iclass 11, count 0 2006.225.08:11:09.86#ibcon#about to read 4, iclass 11, count 0 2006.225.08:11:09.86#ibcon#read 4, iclass 11, count 0 2006.225.08:11:09.86#ibcon#about to read 5, iclass 11, count 0 2006.225.08:11:09.86#ibcon#read 5, iclass 11, count 0 2006.225.08:11:09.86#ibcon#about to read 6, iclass 11, count 0 2006.225.08:11:09.86#ibcon#read 6, iclass 11, count 0 2006.225.08:11:09.86#ibcon#end of sib2, iclass 11, count 0 2006.225.08:11:09.86#ibcon#*after write, iclass 11, count 0 2006.225.08:11:09.86#ibcon#*before return 0, iclass 11, count 0 2006.225.08:11:09.86#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:11:09.86#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:11:09.86#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:11:09.86#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:11:09.86$vc4f8/valo=7,832.99 2006.225.08:11:09.86#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.08:11:09.86#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.08:11:09.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:09.86#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:11:09.86#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:11:09.86#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:11:09.86#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:11:09.86#ibcon#first serial, iclass 13, count 0 2006.225.08:11:09.86#ibcon#enter sib2, iclass 13, count 0 2006.225.08:11:09.86#ibcon#flushed, iclass 13, count 0 2006.225.08:11:09.86#ibcon#about to write, iclass 13, count 0 2006.225.08:11:09.86#ibcon#wrote, iclass 13, count 0 2006.225.08:11:09.86#ibcon#about to read 3, iclass 13, count 0 2006.225.08:11:09.88#ibcon#read 3, iclass 13, count 0 2006.225.08:11:09.88#ibcon#about to read 4, iclass 13, count 0 2006.225.08:11:09.88#ibcon#read 4, iclass 13, count 0 2006.225.08:11:09.88#ibcon#about to read 5, iclass 13, count 0 2006.225.08:11:09.88#ibcon#read 5, iclass 13, count 0 2006.225.08:11:09.88#ibcon#about to read 6, iclass 13, count 0 2006.225.08:11:09.88#ibcon#read 6, iclass 13, count 0 2006.225.08:11:09.88#ibcon#end of sib2, iclass 13, count 0 2006.225.08:11:09.88#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:11:09.88#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:11:09.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:11:09.88#ibcon#*before write, iclass 13, count 0 2006.225.08:11:09.88#ibcon#enter sib2, iclass 13, count 0 2006.225.08:11:09.88#ibcon#flushed, iclass 13, count 0 2006.225.08:11:09.88#ibcon#about to write, iclass 13, count 0 2006.225.08:11:09.88#ibcon#wrote, iclass 13, count 0 2006.225.08:11:09.88#ibcon#about to read 3, iclass 13, count 0 2006.225.08:11:09.92#ibcon#read 3, iclass 13, count 0 2006.225.08:11:09.92#ibcon#about to read 4, iclass 13, count 0 2006.225.08:11:09.92#ibcon#read 4, iclass 13, count 0 2006.225.08:11:09.92#ibcon#about to read 5, iclass 13, count 0 2006.225.08:11:09.92#ibcon#read 5, iclass 13, count 0 2006.225.08:11:09.92#ibcon#about to read 6, iclass 13, count 0 2006.225.08:11:09.92#ibcon#read 6, iclass 13, count 0 2006.225.08:11:09.92#ibcon#end of sib2, iclass 13, count 0 2006.225.08:11:09.92#ibcon#*after write, iclass 13, count 0 2006.225.08:11:09.92#ibcon#*before return 0, iclass 13, count 0 2006.225.08:11:09.92#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:11:09.92#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:11:09.92#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:11:09.92#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:11:09.92$vc4f8/va=7,6 2006.225.08:11:09.92#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.225.08:11:09.92#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.225.08:11:09.92#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:09.92#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:11:09.98#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:11:09.98#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:11:09.98#ibcon#enter wrdev, iclass 15, count 2 2006.225.08:11:09.98#ibcon#first serial, iclass 15, count 2 2006.225.08:11:09.98#ibcon#enter sib2, iclass 15, count 2 2006.225.08:11:09.98#ibcon#flushed, iclass 15, count 2 2006.225.08:11:09.98#ibcon#about to write, iclass 15, count 2 2006.225.08:11:09.98#ibcon#wrote, iclass 15, count 2 2006.225.08:11:09.98#ibcon#about to read 3, iclass 15, count 2 2006.225.08:11:10.00#ibcon#read 3, iclass 15, count 2 2006.225.08:11:10.00#ibcon#about to read 4, iclass 15, count 2 2006.225.08:11:10.00#ibcon#read 4, iclass 15, count 2 2006.225.08:11:10.00#ibcon#about to read 5, iclass 15, count 2 2006.225.08:11:10.00#ibcon#read 5, iclass 15, count 2 2006.225.08:11:10.00#ibcon#about to read 6, iclass 15, count 2 2006.225.08:11:10.00#ibcon#read 6, iclass 15, count 2 2006.225.08:11:10.00#ibcon#end of sib2, iclass 15, count 2 2006.225.08:11:10.00#ibcon#*mode == 0, iclass 15, count 2 2006.225.08:11:10.00#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.225.08:11:10.00#ibcon#[25=AT07-06\r\n] 2006.225.08:11:10.00#ibcon#*before write, iclass 15, count 2 2006.225.08:11:10.00#ibcon#enter sib2, iclass 15, count 2 2006.225.08:11:10.00#ibcon#flushed, iclass 15, count 2 2006.225.08:11:10.00#ibcon#about to write, iclass 15, count 2 2006.225.08:11:10.00#ibcon#wrote, iclass 15, count 2 2006.225.08:11:10.00#ibcon#about to read 3, iclass 15, count 2 2006.225.08:11:10.03#ibcon#read 3, iclass 15, count 2 2006.225.08:11:10.03#ibcon#about to read 4, iclass 15, count 2 2006.225.08:11:10.03#ibcon#read 4, iclass 15, count 2 2006.225.08:11:10.03#ibcon#about to read 5, iclass 15, count 2 2006.225.08:11:10.03#ibcon#read 5, iclass 15, count 2 2006.225.08:11:10.03#ibcon#about to read 6, iclass 15, count 2 2006.225.08:11:10.03#ibcon#read 6, iclass 15, count 2 2006.225.08:11:10.03#ibcon#end of sib2, iclass 15, count 2 2006.225.08:11:10.03#ibcon#*after write, iclass 15, count 2 2006.225.08:11:10.03#ibcon#*before return 0, iclass 15, count 2 2006.225.08:11:10.03#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:11:10.03#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:11:10.03#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.225.08:11:10.03#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:10.03#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:11:10.15#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:11:10.15#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:11:10.15#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:11:10.15#ibcon#first serial, iclass 15, count 0 2006.225.08:11:10.15#ibcon#enter sib2, iclass 15, count 0 2006.225.08:11:10.15#ibcon#flushed, iclass 15, count 0 2006.225.08:11:10.15#ibcon#about to write, iclass 15, count 0 2006.225.08:11:10.15#ibcon#wrote, iclass 15, count 0 2006.225.08:11:10.15#ibcon#about to read 3, iclass 15, count 0 2006.225.08:11:10.17#ibcon#read 3, iclass 15, count 0 2006.225.08:11:10.17#ibcon#about to read 4, iclass 15, count 0 2006.225.08:11:10.17#ibcon#read 4, iclass 15, count 0 2006.225.08:11:10.17#ibcon#about to read 5, iclass 15, count 0 2006.225.08:11:10.17#ibcon#read 5, iclass 15, count 0 2006.225.08:11:10.17#ibcon#about to read 6, iclass 15, count 0 2006.225.08:11:10.17#ibcon#read 6, iclass 15, count 0 2006.225.08:11:10.17#ibcon#end of sib2, iclass 15, count 0 2006.225.08:11:10.17#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:11:10.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:11:10.17#ibcon#[25=USB\r\n] 2006.225.08:11:10.17#ibcon#*before write, iclass 15, count 0 2006.225.08:11:10.17#ibcon#enter sib2, iclass 15, count 0 2006.225.08:11:10.17#ibcon#flushed, iclass 15, count 0 2006.225.08:11:10.17#ibcon#about to write, iclass 15, count 0 2006.225.08:11:10.17#ibcon#wrote, iclass 15, count 0 2006.225.08:11:10.17#ibcon#about to read 3, iclass 15, count 0 2006.225.08:11:10.20#ibcon#read 3, iclass 15, count 0 2006.225.08:11:10.20#ibcon#about to read 4, iclass 15, count 0 2006.225.08:11:10.20#ibcon#read 4, iclass 15, count 0 2006.225.08:11:10.20#ibcon#about to read 5, iclass 15, count 0 2006.225.08:11:10.20#ibcon#read 5, iclass 15, count 0 2006.225.08:11:10.20#ibcon#about to read 6, iclass 15, count 0 2006.225.08:11:10.20#ibcon#read 6, iclass 15, count 0 2006.225.08:11:10.20#ibcon#end of sib2, iclass 15, count 0 2006.225.08:11:10.20#ibcon#*after write, iclass 15, count 0 2006.225.08:11:10.20#ibcon#*before return 0, iclass 15, count 0 2006.225.08:11:10.20#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:11:10.20#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:11:10.20#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:11:10.20#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:11:10.20$vc4f8/valo=8,852.99 2006.225.08:11:10.20#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.225.08:11:10.20#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.225.08:11:10.20#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:10.20#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:11:10.20#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:11:10.20#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:11:10.20#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:11:10.20#ibcon#first serial, iclass 17, count 0 2006.225.08:11:10.20#ibcon#enter sib2, iclass 17, count 0 2006.225.08:11:10.20#ibcon#flushed, iclass 17, count 0 2006.225.08:11:10.20#ibcon#about to write, iclass 17, count 0 2006.225.08:11:10.20#ibcon#wrote, iclass 17, count 0 2006.225.08:11:10.20#ibcon#about to read 3, iclass 17, count 0 2006.225.08:11:10.22#ibcon#read 3, iclass 17, count 0 2006.225.08:11:10.22#ibcon#about to read 4, iclass 17, count 0 2006.225.08:11:10.22#ibcon#read 4, iclass 17, count 0 2006.225.08:11:10.22#ibcon#about to read 5, iclass 17, count 0 2006.225.08:11:10.22#ibcon#read 5, iclass 17, count 0 2006.225.08:11:10.22#ibcon#about to read 6, iclass 17, count 0 2006.225.08:11:10.22#ibcon#read 6, iclass 17, count 0 2006.225.08:11:10.22#ibcon#end of sib2, iclass 17, count 0 2006.225.08:11:10.22#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:11:10.22#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:11:10.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:11:10.22#ibcon#*before write, iclass 17, count 0 2006.225.08:11:10.22#ibcon#enter sib2, iclass 17, count 0 2006.225.08:11:10.22#ibcon#flushed, iclass 17, count 0 2006.225.08:11:10.22#ibcon#about to write, iclass 17, count 0 2006.225.08:11:10.22#ibcon#wrote, iclass 17, count 0 2006.225.08:11:10.22#ibcon#about to read 3, iclass 17, count 0 2006.225.08:11:10.26#ibcon#read 3, iclass 17, count 0 2006.225.08:11:10.26#ibcon#about to read 4, iclass 17, count 0 2006.225.08:11:10.26#ibcon#read 4, iclass 17, count 0 2006.225.08:11:10.26#ibcon#about to read 5, iclass 17, count 0 2006.225.08:11:10.26#ibcon#read 5, iclass 17, count 0 2006.225.08:11:10.26#ibcon#about to read 6, iclass 17, count 0 2006.225.08:11:10.26#ibcon#read 6, iclass 17, count 0 2006.225.08:11:10.26#ibcon#end of sib2, iclass 17, count 0 2006.225.08:11:10.26#ibcon#*after write, iclass 17, count 0 2006.225.08:11:10.26#ibcon#*before return 0, iclass 17, count 0 2006.225.08:11:10.26#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:11:10.26#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:11:10.26#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:11:10.26#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:11:10.26$vc4f8/va=8,7 2006.225.08:11:10.26#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.225.08:11:10.26#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.225.08:11:10.26#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:10.26#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:11:10.32#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:11:10.32#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:11:10.32#ibcon#enter wrdev, iclass 19, count 2 2006.225.08:11:10.32#ibcon#first serial, iclass 19, count 2 2006.225.08:11:10.32#ibcon#enter sib2, iclass 19, count 2 2006.225.08:11:10.32#ibcon#flushed, iclass 19, count 2 2006.225.08:11:10.32#ibcon#about to write, iclass 19, count 2 2006.225.08:11:10.32#ibcon#wrote, iclass 19, count 2 2006.225.08:11:10.32#ibcon#about to read 3, iclass 19, count 2 2006.225.08:11:10.34#ibcon#read 3, iclass 19, count 2 2006.225.08:11:10.34#ibcon#about to read 4, iclass 19, count 2 2006.225.08:11:10.34#ibcon#read 4, iclass 19, count 2 2006.225.08:11:10.34#ibcon#about to read 5, iclass 19, count 2 2006.225.08:11:10.34#ibcon#read 5, iclass 19, count 2 2006.225.08:11:10.34#ibcon#about to read 6, iclass 19, count 2 2006.225.08:11:10.34#ibcon#read 6, iclass 19, count 2 2006.225.08:11:10.34#ibcon#end of sib2, iclass 19, count 2 2006.225.08:11:10.34#ibcon#*mode == 0, iclass 19, count 2 2006.225.08:11:10.34#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.225.08:11:10.34#ibcon#[25=AT08-07\r\n] 2006.225.08:11:10.34#ibcon#*before write, iclass 19, count 2 2006.225.08:11:10.34#ibcon#enter sib2, iclass 19, count 2 2006.225.08:11:10.34#ibcon#flushed, iclass 19, count 2 2006.225.08:11:10.34#ibcon#about to write, iclass 19, count 2 2006.225.08:11:10.34#ibcon#wrote, iclass 19, count 2 2006.225.08:11:10.34#ibcon#about to read 3, iclass 19, count 2 2006.225.08:11:10.37#ibcon#read 3, iclass 19, count 2 2006.225.08:11:10.37#ibcon#about to read 4, iclass 19, count 2 2006.225.08:11:10.37#ibcon#read 4, iclass 19, count 2 2006.225.08:11:10.37#ibcon#about to read 5, iclass 19, count 2 2006.225.08:11:10.37#ibcon#read 5, iclass 19, count 2 2006.225.08:11:10.37#ibcon#about to read 6, iclass 19, count 2 2006.225.08:11:10.37#ibcon#read 6, iclass 19, count 2 2006.225.08:11:10.37#ibcon#end of sib2, iclass 19, count 2 2006.225.08:11:10.37#ibcon#*after write, iclass 19, count 2 2006.225.08:11:10.37#ibcon#*before return 0, iclass 19, count 2 2006.225.08:11:10.37#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:11:10.37#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:11:10.37#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.225.08:11:10.37#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:10.37#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:11:10.49#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:11:10.49#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:11:10.49#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:11:10.49#ibcon#first serial, iclass 19, count 0 2006.225.08:11:10.49#ibcon#enter sib2, iclass 19, count 0 2006.225.08:11:10.49#ibcon#flushed, iclass 19, count 0 2006.225.08:11:10.49#ibcon#about to write, iclass 19, count 0 2006.225.08:11:10.49#ibcon#wrote, iclass 19, count 0 2006.225.08:11:10.49#ibcon#about to read 3, iclass 19, count 0 2006.225.08:11:10.51#ibcon#read 3, iclass 19, count 0 2006.225.08:11:10.51#ibcon#about to read 4, iclass 19, count 0 2006.225.08:11:10.51#ibcon#read 4, iclass 19, count 0 2006.225.08:11:10.51#ibcon#about to read 5, iclass 19, count 0 2006.225.08:11:10.51#ibcon#read 5, iclass 19, count 0 2006.225.08:11:10.51#ibcon#about to read 6, iclass 19, count 0 2006.225.08:11:10.51#ibcon#read 6, iclass 19, count 0 2006.225.08:11:10.51#ibcon#end of sib2, iclass 19, count 0 2006.225.08:11:10.51#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:11:10.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:11:10.51#ibcon#[25=USB\r\n] 2006.225.08:11:10.51#ibcon#*before write, iclass 19, count 0 2006.225.08:11:10.51#ibcon#enter sib2, iclass 19, count 0 2006.225.08:11:10.51#ibcon#flushed, iclass 19, count 0 2006.225.08:11:10.51#ibcon#about to write, iclass 19, count 0 2006.225.08:11:10.51#ibcon#wrote, iclass 19, count 0 2006.225.08:11:10.51#ibcon#about to read 3, iclass 19, count 0 2006.225.08:11:10.54#ibcon#read 3, iclass 19, count 0 2006.225.08:11:10.54#ibcon#about to read 4, iclass 19, count 0 2006.225.08:11:10.54#ibcon#read 4, iclass 19, count 0 2006.225.08:11:10.54#ibcon#about to read 5, iclass 19, count 0 2006.225.08:11:10.54#ibcon#read 5, iclass 19, count 0 2006.225.08:11:10.54#ibcon#about to read 6, iclass 19, count 0 2006.225.08:11:10.54#ibcon#read 6, iclass 19, count 0 2006.225.08:11:10.54#ibcon#end of sib2, iclass 19, count 0 2006.225.08:11:10.54#ibcon#*after write, iclass 19, count 0 2006.225.08:11:10.54#ibcon#*before return 0, iclass 19, count 0 2006.225.08:11:10.54#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:11:10.54#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:11:10.54#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:11:10.54#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:11:10.54$vc4f8/vblo=1,632.99 2006.225.08:11:10.54#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.225.08:11:10.54#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.225.08:11:10.54#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:10.54#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:11:10.54#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:11:10.54#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:11:10.54#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:11:10.54#ibcon#first serial, iclass 21, count 0 2006.225.08:11:10.54#ibcon#enter sib2, iclass 21, count 0 2006.225.08:11:10.54#ibcon#flushed, iclass 21, count 0 2006.225.08:11:10.54#ibcon#about to write, iclass 21, count 0 2006.225.08:11:10.54#ibcon#wrote, iclass 21, count 0 2006.225.08:11:10.54#ibcon#about to read 3, iclass 21, count 0 2006.225.08:11:10.56#ibcon#read 3, iclass 21, count 0 2006.225.08:11:10.56#ibcon#about to read 4, iclass 21, count 0 2006.225.08:11:10.56#ibcon#read 4, iclass 21, count 0 2006.225.08:11:10.56#ibcon#about to read 5, iclass 21, count 0 2006.225.08:11:10.56#ibcon#read 5, iclass 21, count 0 2006.225.08:11:10.56#ibcon#about to read 6, iclass 21, count 0 2006.225.08:11:10.56#ibcon#read 6, iclass 21, count 0 2006.225.08:11:10.56#ibcon#end of sib2, iclass 21, count 0 2006.225.08:11:10.56#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:11:10.56#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:11:10.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:11:10.56#ibcon#*before write, iclass 21, count 0 2006.225.08:11:10.56#ibcon#enter sib2, iclass 21, count 0 2006.225.08:11:10.56#ibcon#flushed, iclass 21, count 0 2006.225.08:11:10.56#ibcon#about to write, iclass 21, count 0 2006.225.08:11:10.56#ibcon#wrote, iclass 21, count 0 2006.225.08:11:10.56#ibcon#about to read 3, iclass 21, count 0 2006.225.08:11:10.60#ibcon#read 3, iclass 21, count 0 2006.225.08:11:10.60#ibcon#about to read 4, iclass 21, count 0 2006.225.08:11:10.60#ibcon#read 4, iclass 21, count 0 2006.225.08:11:10.60#ibcon#about to read 5, iclass 21, count 0 2006.225.08:11:10.60#ibcon#read 5, iclass 21, count 0 2006.225.08:11:10.60#ibcon#about to read 6, iclass 21, count 0 2006.225.08:11:10.60#ibcon#read 6, iclass 21, count 0 2006.225.08:11:10.60#ibcon#end of sib2, iclass 21, count 0 2006.225.08:11:10.60#ibcon#*after write, iclass 21, count 0 2006.225.08:11:10.60#ibcon#*before return 0, iclass 21, count 0 2006.225.08:11:10.60#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:11:10.60#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:11:10.60#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:11:10.60#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:11:10.60$vc4f8/vb=1,4 2006.225.08:11:10.60#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.225.08:11:10.60#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.225.08:11:10.60#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:10.60#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:11:10.60#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:11:10.60#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:11:10.60#ibcon#enter wrdev, iclass 23, count 2 2006.225.08:11:10.60#ibcon#first serial, iclass 23, count 2 2006.225.08:11:10.60#ibcon#enter sib2, iclass 23, count 2 2006.225.08:11:10.60#ibcon#flushed, iclass 23, count 2 2006.225.08:11:10.60#ibcon#about to write, iclass 23, count 2 2006.225.08:11:10.60#ibcon#wrote, iclass 23, count 2 2006.225.08:11:10.60#ibcon#about to read 3, iclass 23, count 2 2006.225.08:11:10.62#ibcon#read 3, iclass 23, count 2 2006.225.08:11:10.62#ibcon#about to read 4, iclass 23, count 2 2006.225.08:11:10.62#ibcon#read 4, iclass 23, count 2 2006.225.08:11:10.62#ibcon#about to read 5, iclass 23, count 2 2006.225.08:11:10.62#ibcon#read 5, iclass 23, count 2 2006.225.08:11:10.62#ibcon#about to read 6, iclass 23, count 2 2006.225.08:11:10.62#ibcon#read 6, iclass 23, count 2 2006.225.08:11:10.62#ibcon#end of sib2, iclass 23, count 2 2006.225.08:11:10.62#ibcon#*mode == 0, iclass 23, count 2 2006.225.08:11:10.62#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.225.08:11:10.62#ibcon#[27=AT01-04\r\n] 2006.225.08:11:10.62#ibcon#*before write, iclass 23, count 2 2006.225.08:11:10.62#ibcon#enter sib2, iclass 23, count 2 2006.225.08:11:10.62#ibcon#flushed, iclass 23, count 2 2006.225.08:11:10.62#ibcon#about to write, iclass 23, count 2 2006.225.08:11:10.62#ibcon#wrote, iclass 23, count 2 2006.225.08:11:10.62#ibcon#about to read 3, iclass 23, count 2 2006.225.08:11:10.65#ibcon#read 3, iclass 23, count 2 2006.225.08:11:10.65#ibcon#about to read 4, iclass 23, count 2 2006.225.08:11:10.65#ibcon#read 4, iclass 23, count 2 2006.225.08:11:10.65#ibcon#about to read 5, iclass 23, count 2 2006.225.08:11:10.65#ibcon#read 5, iclass 23, count 2 2006.225.08:11:10.65#ibcon#about to read 6, iclass 23, count 2 2006.225.08:11:10.65#ibcon#read 6, iclass 23, count 2 2006.225.08:11:10.65#ibcon#end of sib2, iclass 23, count 2 2006.225.08:11:10.65#ibcon#*after write, iclass 23, count 2 2006.225.08:11:10.65#ibcon#*before return 0, iclass 23, count 2 2006.225.08:11:10.65#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:11:10.65#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:11:10.65#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.225.08:11:10.65#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:10.65#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:11:10.77#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:11:10.77#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:11:10.77#ibcon#enter wrdev, iclass 23, count 0 2006.225.08:11:10.77#ibcon#first serial, iclass 23, count 0 2006.225.08:11:10.77#ibcon#enter sib2, iclass 23, count 0 2006.225.08:11:10.77#ibcon#flushed, iclass 23, count 0 2006.225.08:11:10.77#ibcon#about to write, iclass 23, count 0 2006.225.08:11:10.77#ibcon#wrote, iclass 23, count 0 2006.225.08:11:10.77#ibcon#about to read 3, iclass 23, count 0 2006.225.08:11:10.79#ibcon#read 3, iclass 23, count 0 2006.225.08:11:10.79#ibcon#about to read 4, iclass 23, count 0 2006.225.08:11:10.79#ibcon#read 4, iclass 23, count 0 2006.225.08:11:10.79#ibcon#about to read 5, iclass 23, count 0 2006.225.08:11:10.79#ibcon#read 5, iclass 23, count 0 2006.225.08:11:10.79#ibcon#about to read 6, iclass 23, count 0 2006.225.08:11:10.79#ibcon#read 6, iclass 23, count 0 2006.225.08:11:10.79#ibcon#end of sib2, iclass 23, count 0 2006.225.08:11:10.79#ibcon#*mode == 0, iclass 23, count 0 2006.225.08:11:10.79#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.08:11:10.79#ibcon#[27=USB\r\n] 2006.225.08:11:10.79#ibcon#*before write, iclass 23, count 0 2006.225.08:11:10.79#ibcon#enter sib2, iclass 23, count 0 2006.225.08:11:10.79#ibcon#flushed, iclass 23, count 0 2006.225.08:11:10.79#ibcon#about to write, iclass 23, count 0 2006.225.08:11:10.79#ibcon#wrote, iclass 23, count 0 2006.225.08:11:10.79#ibcon#about to read 3, iclass 23, count 0 2006.225.08:11:10.82#ibcon#read 3, iclass 23, count 0 2006.225.08:11:10.82#ibcon#about to read 4, iclass 23, count 0 2006.225.08:11:10.82#ibcon#read 4, iclass 23, count 0 2006.225.08:11:10.82#ibcon#about to read 5, iclass 23, count 0 2006.225.08:11:10.82#ibcon#read 5, iclass 23, count 0 2006.225.08:11:10.82#ibcon#about to read 6, iclass 23, count 0 2006.225.08:11:10.82#ibcon#read 6, iclass 23, count 0 2006.225.08:11:10.82#ibcon#end of sib2, iclass 23, count 0 2006.225.08:11:10.82#ibcon#*after write, iclass 23, count 0 2006.225.08:11:10.82#ibcon#*before return 0, iclass 23, count 0 2006.225.08:11:10.82#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:11:10.82#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:11:10.82#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.08:11:10.82#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.08:11:10.82$vc4f8/vblo=2,640.99 2006.225.08:11:10.82#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.225.08:11:10.82#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.225.08:11:10.82#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:10.82#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:11:10.82#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:11:10.82#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:11:10.82#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:11:10.82#ibcon#first serial, iclass 25, count 0 2006.225.08:11:10.82#ibcon#enter sib2, iclass 25, count 0 2006.225.08:11:10.82#ibcon#flushed, iclass 25, count 0 2006.225.08:11:10.82#ibcon#about to write, iclass 25, count 0 2006.225.08:11:10.82#ibcon#wrote, iclass 25, count 0 2006.225.08:11:10.82#ibcon#about to read 3, iclass 25, count 0 2006.225.08:11:10.84#ibcon#read 3, iclass 25, count 0 2006.225.08:11:10.84#ibcon#about to read 4, iclass 25, count 0 2006.225.08:11:10.84#ibcon#read 4, iclass 25, count 0 2006.225.08:11:10.84#ibcon#about to read 5, iclass 25, count 0 2006.225.08:11:10.84#ibcon#read 5, iclass 25, count 0 2006.225.08:11:10.84#ibcon#about to read 6, iclass 25, count 0 2006.225.08:11:10.84#ibcon#read 6, iclass 25, count 0 2006.225.08:11:10.84#ibcon#end of sib2, iclass 25, count 0 2006.225.08:11:10.84#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:11:10.84#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:11:10.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:11:10.84#ibcon#*before write, iclass 25, count 0 2006.225.08:11:10.84#ibcon#enter sib2, iclass 25, count 0 2006.225.08:11:10.84#ibcon#flushed, iclass 25, count 0 2006.225.08:11:10.84#ibcon#about to write, iclass 25, count 0 2006.225.08:11:10.84#ibcon#wrote, iclass 25, count 0 2006.225.08:11:10.84#ibcon#about to read 3, iclass 25, count 0 2006.225.08:11:10.88#ibcon#read 3, iclass 25, count 0 2006.225.08:11:10.88#ibcon#about to read 4, iclass 25, count 0 2006.225.08:11:10.88#ibcon#read 4, iclass 25, count 0 2006.225.08:11:10.88#ibcon#about to read 5, iclass 25, count 0 2006.225.08:11:10.88#ibcon#read 5, iclass 25, count 0 2006.225.08:11:10.88#ibcon#about to read 6, iclass 25, count 0 2006.225.08:11:10.88#ibcon#read 6, iclass 25, count 0 2006.225.08:11:10.88#ibcon#end of sib2, iclass 25, count 0 2006.225.08:11:10.88#ibcon#*after write, iclass 25, count 0 2006.225.08:11:10.88#ibcon#*before return 0, iclass 25, count 0 2006.225.08:11:10.88#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:11:10.88#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:11:10.88#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:11:10.88#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:11:10.88$vc4f8/vb=2,4 2006.225.08:11:10.88#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.225.08:11:10.88#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.225.08:11:10.88#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:10.88#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:11:10.94#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:11:10.94#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:11:10.94#ibcon#enter wrdev, iclass 27, count 2 2006.225.08:11:10.94#ibcon#first serial, iclass 27, count 2 2006.225.08:11:10.94#ibcon#enter sib2, iclass 27, count 2 2006.225.08:11:10.94#ibcon#flushed, iclass 27, count 2 2006.225.08:11:10.94#ibcon#about to write, iclass 27, count 2 2006.225.08:11:10.94#ibcon#wrote, iclass 27, count 2 2006.225.08:11:10.94#ibcon#about to read 3, iclass 27, count 2 2006.225.08:11:10.96#ibcon#read 3, iclass 27, count 2 2006.225.08:11:10.96#ibcon#about to read 4, iclass 27, count 2 2006.225.08:11:10.96#ibcon#read 4, iclass 27, count 2 2006.225.08:11:10.96#ibcon#about to read 5, iclass 27, count 2 2006.225.08:11:10.96#ibcon#read 5, iclass 27, count 2 2006.225.08:11:10.96#ibcon#about to read 6, iclass 27, count 2 2006.225.08:11:10.96#ibcon#read 6, iclass 27, count 2 2006.225.08:11:10.96#ibcon#end of sib2, iclass 27, count 2 2006.225.08:11:10.96#ibcon#*mode == 0, iclass 27, count 2 2006.225.08:11:10.96#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.225.08:11:10.96#ibcon#[27=AT02-04\r\n] 2006.225.08:11:10.96#ibcon#*before write, iclass 27, count 2 2006.225.08:11:10.96#ibcon#enter sib2, iclass 27, count 2 2006.225.08:11:10.96#ibcon#flushed, iclass 27, count 2 2006.225.08:11:10.96#ibcon#about to write, iclass 27, count 2 2006.225.08:11:10.96#ibcon#wrote, iclass 27, count 2 2006.225.08:11:10.96#ibcon#about to read 3, iclass 27, count 2 2006.225.08:11:10.99#ibcon#read 3, iclass 27, count 2 2006.225.08:11:10.99#ibcon#about to read 4, iclass 27, count 2 2006.225.08:11:10.99#ibcon#read 4, iclass 27, count 2 2006.225.08:11:10.99#ibcon#about to read 5, iclass 27, count 2 2006.225.08:11:10.99#ibcon#read 5, iclass 27, count 2 2006.225.08:11:10.99#ibcon#about to read 6, iclass 27, count 2 2006.225.08:11:10.99#ibcon#read 6, iclass 27, count 2 2006.225.08:11:10.99#ibcon#end of sib2, iclass 27, count 2 2006.225.08:11:10.99#ibcon#*after write, iclass 27, count 2 2006.225.08:11:10.99#ibcon#*before return 0, iclass 27, count 2 2006.225.08:11:10.99#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:11:10.99#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:11:10.99#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.225.08:11:10.99#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:10.99#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:11:11.11#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:11:11.11#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:11:11.11#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:11:11.11#ibcon#first serial, iclass 27, count 0 2006.225.08:11:11.11#ibcon#enter sib2, iclass 27, count 0 2006.225.08:11:11.11#ibcon#flushed, iclass 27, count 0 2006.225.08:11:11.11#ibcon#about to write, iclass 27, count 0 2006.225.08:11:11.11#ibcon#wrote, iclass 27, count 0 2006.225.08:11:11.11#ibcon#about to read 3, iclass 27, count 0 2006.225.08:11:11.13#ibcon#read 3, iclass 27, count 0 2006.225.08:11:11.13#ibcon#about to read 4, iclass 27, count 0 2006.225.08:11:11.13#ibcon#read 4, iclass 27, count 0 2006.225.08:11:11.13#ibcon#about to read 5, iclass 27, count 0 2006.225.08:11:11.13#ibcon#read 5, iclass 27, count 0 2006.225.08:11:11.13#ibcon#about to read 6, iclass 27, count 0 2006.225.08:11:11.13#ibcon#read 6, iclass 27, count 0 2006.225.08:11:11.13#ibcon#end of sib2, iclass 27, count 0 2006.225.08:11:11.13#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:11:11.13#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:11:11.13#ibcon#[27=USB\r\n] 2006.225.08:11:11.13#ibcon#*before write, iclass 27, count 0 2006.225.08:11:11.13#ibcon#enter sib2, iclass 27, count 0 2006.225.08:11:11.13#ibcon#flushed, iclass 27, count 0 2006.225.08:11:11.13#ibcon#about to write, iclass 27, count 0 2006.225.08:11:11.13#ibcon#wrote, iclass 27, count 0 2006.225.08:11:11.13#ibcon#about to read 3, iclass 27, count 0 2006.225.08:11:11.16#ibcon#read 3, iclass 27, count 0 2006.225.08:11:11.16#ibcon#about to read 4, iclass 27, count 0 2006.225.08:11:11.16#ibcon#read 4, iclass 27, count 0 2006.225.08:11:11.16#ibcon#about to read 5, iclass 27, count 0 2006.225.08:11:11.16#ibcon#read 5, iclass 27, count 0 2006.225.08:11:11.16#ibcon#about to read 6, iclass 27, count 0 2006.225.08:11:11.16#ibcon#read 6, iclass 27, count 0 2006.225.08:11:11.16#ibcon#end of sib2, iclass 27, count 0 2006.225.08:11:11.16#ibcon#*after write, iclass 27, count 0 2006.225.08:11:11.16#ibcon#*before return 0, iclass 27, count 0 2006.225.08:11:11.16#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:11:11.16#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:11:11.16#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:11:11.16#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:11:11.16$vc4f8/vblo=3,656.99 2006.225.08:11:11.16#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.08:11:11.16#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.08:11:11.16#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:11.16#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:11:11.16#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:11:11.16#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:11:11.16#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:11:11.16#ibcon#first serial, iclass 29, count 0 2006.225.08:11:11.16#ibcon#enter sib2, iclass 29, count 0 2006.225.08:11:11.16#ibcon#flushed, iclass 29, count 0 2006.225.08:11:11.16#ibcon#about to write, iclass 29, count 0 2006.225.08:11:11.16#ibcon#wrote, iclass 29, count 0 2006.225.08:11:11.16#ibcon#about to read 3, iclass 29, count 0 2006.225.08:11:11.18#ibcon#read 3, iclass 29, count 0 2006.225.08:11:11.18#ibcon#about to read 4, iclass 29, count 0 2006.225.08:11:11.18#ibcon#read 4, iclass 29, count 0 2006.225.08:11:11.18#ibcon#about to read 5, iclass 29, count 0 2006.225.08:11:11.18#ibcon#read 5, iclass 29, count 0 2006.225.08:11:11.18#ibcon#about to read 6, iclass 29, count 0 2006.225.08:11:11.18#ibcon#read 6, iclass 29, count 0 2006.225.08:11:11.18#ibcon#end of sib2, iclass 29, count 0 2006.225.08:11:11.18#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:11:11.18#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:11:11.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:11:11.18#ibcon#*before write, iclass 29, count 0 2006.225.08:11:11.18#ibcon#enter sib2, iclass 29, count 0 2006.225.08:11:11.18#ibcon#flushed, iclass 29, count 0 2006.225.08:11:11.18#ibcon#about to write, iclass 29, count 0 2006.225.08:11:11.18#ibcon#wrote, iclass 29, count 0 2006.225.08:11:11.18#ibcon#about to read 3, iclass 29, count 0 2006.225.08:11:11.22#ibcon#read 3, iclass 29, count 0 2006.225.08:11:11.22#ibcon#about to read 4, iclass 29, count 0 2006.225.08:11:11.22#ibcon#read 4, iclass 29, count 0 2006.225.08:11:11.22#ibcon#about to read 5, iclass 29, count 0 2006.225.08:11:11.22#ibcon#read 5, iclass 29, count 0 2006.225.08:11:11.22#ibcon#about to read 6, iclass 29, count 0 2006.225.08:11:11.22#ibcon#read 6, iclass 29, count 0 2006.225.08:11:11.22#ibcon#end of sib2, iclass 29, count 0 2006.225.08:11:11.22#ibcon#*after write, iclass 29, count 0 2006.225.08:11:11.22#ibcon#*before return 0, iclass 29, count 0 2006.225.08:11:11.22#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:11:11.22#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:11:11.22#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:11:11.22#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:11:11.22$vc4f8/vb=3,4 2006.225.08:11:11.22#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.08:11:11.22#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.08:11:11.22#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:11.22#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:11:11.28#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:11:11.28#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:11:11.28#ibcon#enter wrdev, iclass 31, count 2 2006.225.08:11:11.28#ibcon#first serial, iclass 31, count 2 2006.225.08:11:11.28#ibcon#enter sib2, iclass 31, count 2 2006.225.08:11:11.28#ibcon#flushed, iclass 31, count 2 2006.225.08:11:11.28#ibcon#about to write, iclass 31, count 2 2006.225.08:11:11.28#ibcon#wrote, iclass 31, count 2 2006.225.08:11:11.28#ibcon#about to read 3, iclass 31, count 2 2006.225.08:11:11.30#ibcon#read 3, iclass 31, count 2 2006.225.08:11:11.30#ibcon#about to read 4, iclass 31, count 2 2006.225.08:11:11.30#ibcon#read 4, iclass 31, count 2 2006.225.08:11:11.30#ibcon#about to read 5, iclass 31, count 2 2006.225.08:11:11.30#ibcon#read 5, iclass 31, count 2 2006.225.08:11:11.30#ibcon#about to read 6, iclass 31, count 2 2006.225.08:11:11.30#ibcon#read 6, iclass 31, count 2 2006.225.08:11:11.30#ibcon#end of sib2, iclass 31, count 2 2006.225.08:11:11.30#ibcon#*mode == 0, iclass 31, count 2 2006.225.08:11:11.30#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.08:11:11.30#ibcon#[27=AT03-04\r\n] 2006.225.08:11:11.30#ibcon#*before write, iclass 31, count 2 2006.225.08:11:11.30#ibcon#enter sib2, iclass 31, count 2 2006.225.08:11:11.30#ibcon#flushed, iclass 31, count 2 2006.225.08:11:11.30#ibcon#about to write, iclass 31, count 2 2006.225.08:11:11.30#ibcon#wrote, iclass 31, count 2 2006.225.08:11:11.30#ibcon#about to read 3, iclass 31, count 2 2006.225.08:11:11.33#ibcon#read 3, iclass 31, count 2 2006.225.08:11:11.33#ibcon#about to read 4, iclass 31, count 2 2006.225.08:11:11.33#ibcon#read 4, iclass 31, count 2 2006.225.08:11:11.33#ibcon#about to read 5, iclass 31, count 2 2006.225.08:11:11.33#ibcon#read 5, iclass 31, count 2 2006.225.08:11:11.33#ibcon#about to read 6, iclass 31, count 2 2006.225.08:11:11.33#ibcon#read 6, iclass 31, count 2 2006.225.08:11:11.33#ibcon#end of sib2, iclass 31, count 2 2006.225.08:11:11.33#ibcon#*after write, iclass 31, count 2 2006.225.08:11:11.33#ibcon#*before return 0, iclass 31, count 2 2006.225.08:11:11.33#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:11:11.33#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:11:11.33#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.08:11:11.33#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:11.33#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:11:11.45#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:11:11.45#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:11:11.45#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:11:11.45#ibcon#first serial, iclass 31, count 0 2006.225.08:11:11.45#ibcon#enter sib2, iclass 31, count 0 2006.225.08:11:11.45#ibcon#flushed, iclass 31, count 0 2006.225.08:11:11.45#ibcon#about to write, iclass 31, count 0 2006.225.08:11:11.45#ibcon#wrote, iclass 31, count 0 2006.225.08:11:11.45#ibcon#about to read 3, iclass 31, count 0 2006.225.08:11:11.47#ibcon#read 3, iclass 31, count 0 2006.225.08:11:11.47#ibcon#about to read 4, iclass 31, count 0 2006.225.08:11:11.47#ibcon#read 4, iclass 31, count 0 2006.225.08:11:11.47#ibcon#about to read 5, iclass 31, count 0 2006.225.08:11:11.47#ibcon#read 5, iclass 31, count 0 2006.225.08:11:11.47#ibcon#about to read 6, iclass 31, count 0 2006.225.08:11:11.47#ibcon#read 6, iclass 31, count 0 2006.225.08:11:11.47#ibcon#end of sib2, iclass 31, count 0 2006.225.08:11:11.47#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:11:11.47#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:11:11.47#ibcon#[27=USB\r\n] 2006.225.08:11:11.47#ibcon#*before write, iclass 31, count 0 2006.225.08:11:11.47#ibcon#enter sib2, iclass 31, count 0 2006.225.08:11:11.47#ibcon#flushed, iclass 31, count 0 2006.225.08:11:11.47#ibcon#about to write, iclass 31, count 0 2006.225.08:11:11.47#ibcon#wrote, iclass 31, count 0 2006.225.08:11:11.47#ibcon#about to read 3, iclass 31, count 0 2006.225.08:11:11.50#ibcon#read 3, iclass 31, count 0 2006.225.08:11:11.50#ibcon#about to read 4, iclass 31, count 0 2006.225.08:11:11.50#ibcon#read 4, iclass 31, count 0 2006.225.08:11:11.50#ibcon#about to read 5, iclass 31, count 0 2006.225.08:11:11.50#ibcon#read 5, iclass 31, count 0 2006.225.08:11:11.50#ibcon#about to read 6, iclass 31, count 0 2006.225.08:11:11.50#ibcon#read 6, iclass 31, count 0 2006.225.08:11:11.50#ibcon#end of sib2, iclass 31, count 0 2006.225.08:11:11.50#ibcon#*after write, iclass 31, count 0 2006.225.08:11:11.50#ibcon#*before return 0, iclass 31, count 0 2006.225.08:11:11.50#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:11:11.50#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:11:11.50#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:11:11.50#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:11:11.50$vc4f8/vblo=4,712.99 2006.225.08:11:11.50#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.08:11:11.50#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.08:11:11.50#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:11.50#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:11:11.50#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:11:11.50#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:11:11.50#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:11:11.50#ibcon#first serial, iclass 33, count 0 2006.225.08:11:11.50#ibcon#enter sib2, iclass 33, count 0 2006.225.08:11:11.50#ibcon#flushed, iclass 33, count 0 2006.225.08:11:11.50#ibcon#about to write, iclass 33, count 0 2006.225.08:11:11.50#ibcon#wrote, iclass 33, count 0 2006.225.08:11:11.50#ibcon#about to read 3, iclass 33, count 0 2006.225.08:11:11.53#ibcon#read 3, iclass 33, count 0 2006.225.08:11:11.53#ibcon#about to read 4, iclass 33, count 0 2006.225.08:11:11.53#ibcon#read 4, iclass 33, count 0 2006.225.08:11:11.53#ibcon#about to read 5, iclass 33, count 0 2006.225.08:11:11.53#ibcon#read 5, iclass 33, count 0 2006.225.08:11:11.53#ibcon#about to read 6, iclass 33, count 0 2006.225.08:11:11.53#ibcon#read 6, iclass 33, count 0 2006.225.08:11:11.53#ibcon#end of sib2, iclass 33, count 0 2006.225.08:11:11.53#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:11:11.53#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:11:11.53#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:11:11.53#ibcon#*before write, iclass 33, count 0 2006.225.08:11:11.53#ibcon#enter sib2, iclass 33, count 0 2006.225.08:11:11.53#ibcon#flushed, iclass 33, count 0 2006.225.08:11:11.53#ibcon#about to write, iclass 33, count 0 2006.225.08:11:11.53#ibcon#wrote, iclass 33, count 0 2006.225.08:11:11.53#ibcon#about to read 3, iclass 33, count 0 2006.225.08:11:11.57#ibcon#read 3, iclass 33, count 0 2006.225.08:11:11.57#ibcon#about to read 4, iclass 33, count 0 2006.225.08:11:11.57#ibcon#read 4, iclass 33, count 0 2006.225.08:11:11.57#ibcon#about to read 5, iclass 33, count 0 2006.225.08:11:11.57#ibcon#read 5, iclass 33, count 0 2006.225.08:11:11.57#ibcon#about to read 6, iclass 33, count 0 2006.225.08:11:11.57#ibcon#read 6, iclass 33, count 0 2006.225.08:11:11.57#ibcon#end of sib2, iclass 33, count 0 2006.225.08:11:11.57#ibcon#*after write, iclass 33, count 0 2006.225.08:11:11.57#ibcon#*before return 0, iclass 33, count 0 2006.225.08:11:11.57#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:11:11.57#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:11:11.57#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:11:11.57#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:11:11.57$vc4f8/vb=4,4 2006.225.08:11:11.57#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.08:11:11.57#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.08:11:11.57#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:11.57#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:11:11.62#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:11:11.62#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:11:11.62#ibcon#enter wrdev, iclass 35, count 2 2006.225.08:11:11.62#ibcon#first serial, iclass 35, count 2 2006.225.08:11:11.62#ibcon#enter sib2, iclass 35, count 2 2006.225.08:11:11.62#ibcon#flushed, iclass 35, count 2 2006.225.08:11:11.62#ibcon#about to write, iclass 35, count 2 2006.225.08:11:11.62#ibcon#wrote, iclass 35, count 2 2006.225.08:11:11.62#ibcon#about to read 3, iclass 35, count 2 2006.225.08:11:11.64#ibcon#read 3, iclass 35, count 2 2006.225.08:11:11.64#ibcon#about to read 4, iclass 35, count 2 2006.225.08:11:11.64#ibcon#read 4, iclass 35, count 2 2006.225.08:11:11.64#ibcon#about to read 5, iclass 35, count 2 2006.225.08:11:11.64#ibcon#read 5, iclass 35, count 2 2006.225.08:11:11.64#ibcon#about to read 6, iclass 35, count 2 2006.225.08:11:11.64#ibcon#read 6, iclass 35, count 2 2006.225.08:11:11.64#ibcon#end of sib2, iclass 35, count 2 2006.225.08:11:11.64#ibcon#*mode == 0, iclass 35, count 2 2006.225.08:11:11.64#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.08:11:11.64#ibcon#[27=AT04-04\r\n] 2006.225.08:11:11.64#ibcon#*before write, iclass 35, count 2 2006.225.08:11:11.64#ibcon#enter sib2, iclass 35, count 2 2006.225.08:11:11.64#ibcon#flushed, iclass 35, count 2 2006.225.08:11:11.64#ibcon#about to write, iclass 35, count 2 2006.225.08:11:11.64#ibcon#wrote, iclass 35, count 2 2006.225.08:11:11.64#ibcon#about to read 3, iclass 35, count 2 2006.225.08:11:11.67#ibcon#read 3, iclass 35, count 2 2006.225.08:11:11.67#ibcon#about to read 4, iclass 35, count 2 2006.225.08:11:11.67#ibcon#read 4, iclass 35, count 2 2006.225.08:11:11.67#ibcon#about to read 5, iclass 35, count 2 2006.225.08:11:11.67#ibcon#read 5, iclass 35, count 2 2006.225.08:11:11.67#ibcon#about to read 6, iclass 35, count 2 2006.225.08:11:11.67#ibcon#read 6, iclass 35, count 2 2006.225.08:11:11.67#ibcon#end of sib2, iclass 35, count 2 2006.225.08:11:11.67#ibcon#*after write, iclass 35, count 2 2006.225.08:11:11.67#ibcon#*before return 0, iclass 35, count 2 2006.225.08:11:11.67#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:11:11.67#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:11:11.67#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.08:11:11.67#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:11.67#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:11:11.79#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:11:11.79#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:11:11.79#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:11:11.79#ibcon#first serial, iclass 35, count 0 2006.225.08:11:11.79#ibcon#enter sib2, iclass 35, count 0 2006.225.08:11:11.79#ibcon#flushed, iclass 35, count 0 2006.225.08:11:11.79#ibcon#about to write, iclass 35, count 0 2006.225.08:11:11.79#ibcon#wrote, iclass 35, count 0 2006.225.08:11:11.79#ibcon#about to read 3, iclass 35, count 0 2006.225.08:11:11.81#ibcon#read 3, iclass 35, count 0 2006.225.08:11:11.81#ibcon#about to read 4, iclass 35, count 0 2006.225.08:11:11.81#ibcon#read 4, iclass 35, count 0 2006.225.08:11:11.81#ibcon#about to read 5, iclass 35, count 0 2006.225.08:11:11.81#ibcon#read 5, iclass 35, count 0 2006.225.08:11:11.81#ibcon#about to read 6, iclass 35, count 0 2006.225.08:11:11.81#ibcon#read 6, iclass 35, count 0 2006.225.08:11:11.81#ibcon#end of sib2, iclass 35, count 0 2006.225.08:11:11.81#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:11:11.81#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:11:11.81#ibcon#[27=USB\r\n] 2006.225.08:11:11.81#ibcon#*before write, iclass 35, count 0 2006.225.08:11:11.81#ibcon#enter sib2, iclass 35, count 0 2006.225.08:11:11.81#ibcon#flushed, iclass 35, count 0 2006.225.08:11:11.81#ibcon#about to write, iclass 35, count 0 2006.225.08:11:11.81#ibcon#wrote, iclass 35, count 0 2006.225.08:11:11.81#ibcon#about to read 3, iclass 35, count 0 2006.225.08:11:11.84#ibcon#read 3, iclass 35, count 0 2006.225.08:11:11.84#ibcon#about to read 4, iclass 35, count 0 2006.225.08:11:11.84#ibcon#read 4, iclass 35, count 0 2006.225.08:11:11.84#ibcon#about to read 5, iclass 35, count 0 2006.225.08:11:11.84#ibcon#read 5, iclass 35, count 0 2006.225.08:11:11.84#ibcon#about to read 6, iclass 35, count 0 2006.225.08:11:11.84#ibcon#read 6, iclass 35, count 0 2006.225.08:11:11.84#ibcon#end of sib2, iclass 35, count 0 2006.225.08:11:11.84#ibcon#*after write, iclass 35, count 0 2006.225.08:11:11.84#ibcon#*before return 0, iclass 35, count 0 2006.225.08:11:11.84#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:11:11.84#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:11:11.84#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:11:11.84#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:11:11.84$vc4f8/vblo=5,744.99 2006.225.08:11:11.84#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.08:11:11.84#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.08:11:11.84#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:11.84#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:11:11.84#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:11:11.84#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:11:11.84#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:11:11.84#ibcon#first serial, iclass 37, count 0 2006.225.08:11:11.84#ibcon#enter sib2, iclass 37, count 0 2006.225.08:11:11.84#ibcon#flushed, iclass 37, count 0 2006.225.08:11:11.84#ibcon#about to write, iclass 37, count 0 2006.225.08:11:11.84#ibcon#wrote, iclass 37, count 0 2006.225.08:11:11.84#ibcon#about to read 3, iclass 37, count 0 2006.225.08:11:11.86#ibcon#read 3, iclass 37, count 0 2006.225.08:11:11.86#ibcon#about to read 4, iclass 37, count 0 2006.225.08:11:11.86#ibcon#read 4, iclass 37, count 0 2006.225.08:11:11.86#ibcon#about to read 5, iclass 37, count 0 2006.225.08:11:11.86#ibcon#read 5, iclass 37, count 0 2006.225.08:11:11.86#ibcon#about to read 6, iclass 37, count 0 2006.225.08:11:11.86#ibcon#read 6, iclass 37, count 0 2006.225.08:11:11.86#ibcon#end of sib2, iclass 37, count 0 2006.225.08:11:11.86#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:11:11.86#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:11:11.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:11:11.86#ibcon#*before write, iclass 37, count 0 2006.225.08:11:11.86#ibcon#enter sib2, iclass 37, count 0 2006.225.08:11:11.86#ibcon#flushed, iclass 37, count 0 2006.225.08:11:11.86#ibcon#about to write, iclass 37, count 0 2006.225.08:11:11.86#ibcon#wrote, iclass 37, count 0 2006.225.08:11:11.86#ibcon#about to read 3, iclass 37, count 0 2006.225.08:11:11.90#ibcon#read 3, iclass 37, count 0 2006.225.08:11:11.90#ibcon#about to read 4, iclass 37, count 0 2006.225.08:11:11.90#ibcon#read 4, iclass 37, count 0 2006.225.08:11:11.90#ibcon#about to read 5, iclass 37, count 0 2006.225.08:11:11.90#ibcon#read 5, iclass 37, count 0 2006.225.08:11:11.90#ibcon#about to read 6, iclass 37, count 0 2006.225.08:11:11.90#ibcon#read 6, iclass 37, count 0 2006.225.08:11:11.90#ibcon#end of sib2, iclass 37, count 0 2006.225.08:11:11.90#ibcon#*after write, iclass 37, count 0 2006.225.08:11:11.90#ibcon#*before return 0, iclass 37, count 0 2006.225.08:11:11.90#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:11:11.90#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:11:11.90#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:11:11.90#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:11:11.90$vc4f8/vb=5,4 2006.225.08:11:11.90#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.08:11:11.90#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.08:11:11.90#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:11.90#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:11:11.96#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:11:11.96#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:11:11.96#ibcon#enter wrdev, iclass 39, count 2 2006.225.08:11:11.96#ibcon#first serial, iclass 39, count 2 2006.225.08:11:11.96#ibcon#enter sib2, iclass 39, count 2 2006.225.08:11:11.96#ibcon#flushed, iclass 39, count 2 2006.225.08:11:11.96#ibcon#about to write, iclass 39, count 2 2006.225.08:11:11.96#ibcon#wrote, iclass 39, count 2 2006.225.08:11:11.96#ibcon#about to read 3, iclass 39, count 2 2006.225.08:11:11.98#ibcon#read 3, iclass 39, count 2 2006.225.08:11:11.98#ibcon#about to read 4, iclass 39, count 2 2006.225.08:11:11.98#ibcon#read 4, iclass 39, count 2 2006.225.08:11:11.98#ibcon#about to read 5, iclass 39, count 2 2006.225.08:11:11.98#ibcon#read 5, iclass 39, count 2 2006.225.08:11:11.98#ibcon#about to read 6, iclass 39, count 2 2006.225.08:11:11.98#ibcon#read 6, iclass 39, count 2 2006.225.08:11:11.98#ibcon#end of sib2, iclass 39, count 2 2006.225.08:11:11.98#ibcon#*mode == 0, iclass 39, count 2 2006.225.08:11:11.98#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.08:11:11.98#ibcon#[27=AT05-04\r\n] 2006.225.08:11:11.98#ibcon#*before write, iclass 39, count 2 2006.225.08:11:11.98#ibcon#enter sib2, iclass 39, count 2 2006.225.08:11:11.98#ibcon#flushed, iclass 39, count 2 2006.225.08:11:11.98#ibcon#about to write, iclass 39, count 2 2006.225.08:11:11.98#ibcon#wrote, iclass 39, count 2 2006.225.08:11:11.98#ibcon#about to read 3, iclass 39, count 2 2006.225.08:11:12.01#ibcon#read 3, iclass 39, count 2 2006.225.08:11:12.01#ibcon#about to read 4, iclass 39, count 2 2006.225.08:11:12.01#ibcon#read 4, iclass 39, count 2 2006.225.08:11:12.01#ibcon#about to read 5, iclass 39, count 2 2006.225.08:11:12.01#ibcon#read 5, iclass 39, count 2 2006.225.08:11:12.01#ibcon#about to read 6, iclass 39, count 2 2006.225.08:11:12.01#ibcon#read 6, iclass 39, count 2 2006.225.08:11:12.01#ibcon#end of sib2, iclass 39, count 2 2006.225.08:11:12.01#ibcon#*after write, iclass 39, count 2 2006.225.08:11:12.01#ibcon#*before return 0, iclass 39, count 2 2006.225.08:11:12.01#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:11:12.01#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:11:12.01#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.08:11:12.01#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:12.01#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:11:12.13#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:11:12.13#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:11:12.13#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:11:12.13#ibcon#first serial, iclass 39, count 0 2006.225.08:11:12.13#ibcon#enter sib2, iclass 39, count 0 2006.225.08:11:12.13#ibcon#flushed, iclass 39, count 0 2006.225.08:11:12.13#ibcon#about to write, iclass 39, count 0 2006.225.08:11:12.13#ibcon#wrote, iclass 39, count 0 2006.225.08:11:12.13#ibcon#about to read 3, iclass 39, count 0 2006.225.08:11:12.15#ibcon#read 3, iclass 39, count 0 2006.225.08:11:12.15#ibcon#about to read 4, iclass 39, count 0 2006.225.08:11:12.15#ibcon#read 4, iclass 39, count 0 2006.225.08:11:12.15#ibcon#about to read 5, iclass 39, count 0 2006.225.08:11:12.15#ibcon#read 5, iclass 39, count 0 2006.225.08:11:12.15#ibcon#about to read 6, iclass 39, count 0 2006.225.08:11:12.15#ibcon#read 6, iclass 39, count 0 2006.225.08:11:12.15#ibcon#end of sib2, iclass 39, count 0 2006.225.08:11:12.15#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:11:12.15#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:11:12.15#ibcon#[27=USB\r\n] 2006.225.08:11:12.15#ibcon#*before write, iclass 39, count 0 2006.225.08:11:12.15#ibcon#enter sib2, iclass 39, count 0 2006.225.08:11:12.15#ibcon#flushed, iclass 39, count 0 2006.225.08:11:12.15#ibcon#about to write, iclass 39, count 0 2006.225.08:11:12.15#ibcon#wrote, iclass 39, count 0 2006.225.08:11:12.15#ibcon#about to read 3, iclass 39, count 0 2006.225.08:11:12.18#ibcon#read 3, iclass 39, count 0 2006.225.08:11:12.18#ibcon#about to read 4, iclass 39, count 0 2006.225.08:11:12.18#ibcon#read 4, iclass 39, count 0 2006.225.08:11:12.18#ibcon#about to read 5, iclass 39, count 0 2006.225.08:11:12.18#ibcon#read 5, iclass 39, count 0 2006.225.08:11:12.18#ibcon#about to read 6, iclass 39, count 0 2006.225.08:11:12.18#ibcon#read 6, iclass 39, count 0 2006.225.08:11:12.18#ibcon#end of sib2, iclass 39, count 0 2006.225.08:11:12.18#ibcon#*after write, iclass 39, count 0 2006.225.08:11:12.18#ibcon#*before return 0, iclass 39, count 0 2006.225.08:11:12.18#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:11:12.18#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:11:12.18#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:11:12.18#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:11:12.18$vc4f8/vblo=6,752.99 2006.225.08:11:12.18#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.08:11:12.18#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.08:11:12.18#ibcon#ireg 17 cls_cnt 0 2006.225.08:11:12.18#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:11:12.18#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:11:12.18#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:11:12.18#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:11:12.18#ibcon#first serial, iclass 3, count 0 2006.225.08:11:12.18#ibcon#enter sib2, iclass 3, count 0 2006.225.08:11:12.18#ibcon#flushed, iclass 3, count 0 2006.225.08:11:12.18#ibcon#about to write, iclass 3, count 0 2006.225.08:11:12.18#ibcon#wrote, iclass 3, count 0 2006.225.08:11:12.18#ibcon#about to read 3, iclass 3, count 0 2006.225.08:11:12.20#ibcon#read 3, iclass 3, count 0 2006.225.08:11:12.20#ibcon#about to read 4, iclass 3, count 0 2006.225.08:11:12.20#ibcon#read 4, iclass 3, count 0 2006.225.08:11:12.20#ibcon#about to read 5, iclass 3, count 0 2006.225.08:11:12.20#ibcon#read 5, iclass 3, count 0 2006.225.08:11:12.20#ibcon#about to read 6, iclass 3, count 0 2006.225.08:11:12.20#ibcon#read 6, iclass 3, count 0 2006.225.08:11:12.20#ibcon#end of sib2, iclass 3, count 0 2006.225.08:11:12.20#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:11:12.20#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:11:12.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:11:12.20#ibcon#*before write, iclass 3, count 0 2006.225.08:11:12.20#ibcon#enter sib2, iclass 3, count 0 2006.225.08:11:12.20#ibcon#flushed, iclass 3, count 0 2006.225.08:11:12.20#ibcon#about to write, iclass 3, count 0 2006.225.08:11:12.20#ibcon#wrote, iclass 3, count 0 2006.225.08:11:12.20#ibcon#about to read 3, iclass 3, count 0 2006.225.08:11:12.24#ibcon#read 3, iclass 3, count 0 2006.225.08:11:12.24#ibcon#about to read 4, iclass 3, count 0 2006.225.08:11:12.24#ibcon#read 4, iclass 3, count 0 2006.225.08:11:12.24#ibcon#about to read 5, iclass 3, count 0 2006.225.08:11:12.24#ibcon#read 5, iclass 3, count 0 2006.225.08:11:12.24#ibcon#about to read 6, iclass 3, count 0 2006.225.08:11:12.24#ibcon#read 6, iclass 3, count 0 2006.225.08:11:12.24#ibcon#end of sib2, iclass 3, count 0 2006.225.08:11:12.24#ibcon#*after write, iclass 3, count 0 2006.225.08:11:12.24#ibcon#*before return 0, iclass 3, count 0 2006.225.08:11:12.24#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:11:12.24#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:11:12.24#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:11:12.24#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:11:12.24$vc4f8/vb=6,4 2006.225.08:11:12.24#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.08:11:12.24#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.08:11:12.24#ibcon#ireg 11 cls_cnt 2 2006.225.08:11:12.24#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:11:12.30#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:11:12.30#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:11:12.30#ibcon#enter wrdev, iclass 5, count 2 2006.225.08:11:12.30#ibcon#first serial, iclass 5, count 2 2006.225.08:11:12.30#ibcon#enter sib2, iclass 5, count 2 2006.225.08:11:12.30#ibcon#flushed, iclass 5, count 2 2006.225.08:11:12.30#ibcon#about to write, iclass 5, count 2 2006.225.08:11:12.30#ibcon#wrote, iclass 5, count 2 2006.225.08:11:12.30#ibcon#about to read 3, iclass 5, count 2 2006.225.08:11:12.32#ibcon#read 3, iclass 5, count 2 2006.225.08:11:12.32#ibcon#about to read 4, iclass 5, count 2 2006.225.08:11:12.32#ibcon#read 4, iclass 5, count 2 2006.225.08:11:12.32#ibcon#about to read 5, iclass 5, count 2 2006.225.08:11:12.32#ibcon#read 5, iclass 5, count 2 2006.225.08:11:12.32#ibcon#about to read 6, iclass 5, count 2 2006.225.08:11:12.32#ibcon#read 6, iclass 5, count 2 2006.225.08:11:12.32#ibcon#end of sib2, iclass 5, count 2 2006.225.08:11:12.32#ibcon#*mode == 0, iclass 5, count 2 2006.225.08:11:12.32#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.08:11:12.32#ibcon#[27=AT06-04\r\n] 2006.225.08:11:12.32#ibcon#*before write, iclass 5, count 2 2006.225.08:11:12.32#ibcon#enter sib2, iclass 5, count 2 2006.225.08:11:12.32#ibcon#flushed, iclass 5, count 2 2006.225.08:11:12.32#ibcon#about to write, iclass 5, count 2 2006.225.08:11:12.32#ibcon#wrote, iclass 5, count 2 2006.225.08:11:12.32#ibcon#about to read 3, iclass 5, count 2 2006.225.08:11:12.35#ibcon#read 3, iclass 5, count 2 2006.225.08:11:12.35#ibcon#about to read 4, iclass 5, count 2 2006.225.08:11:12.35#ibcon#read 4, iclass 5, count 2 2006.225.08:11:12.35#ibcon#about to read 5, iclass 5, count 2 2006.225.08:11:12.35#ibcon#read 5, iclass 5, count 2 2006.225.08:11:12.35#ibcon#about to read 6, iclass 5, count 2 2006.225.08:11:12.35#ibcon#read 6, iclass 5, count 2 2006.225.08:11:12.35#ibcon#end of sib2, iclass 5, count 2 2006.225.08:11:12.35#ibcon#*after write, iclass 5, count 2 2006.225.08:11:12.35#ibcon#*before return 0, iclass 5, count 2 2006.225.08:11:12.35#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:11:12.35#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:11:12.35#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.08:11:12.35#ibcon#ireg 7 cls_cnt 0 2006.225.08:11:12.35#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:11:12.47#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:11:12.47#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:11:12.47#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:11:12.47#ibcon#first serial, iclass 5, count 0 2006.225.08:11:12.47#ibcon#enter sib2, iclass 5, count 0 2006.225.08:11:12.47#ibcon#flushed, iclass 5, count 0 2006.225.08:11:12.47#ibcon#about to write, iclass 5, count 0 2006.225.08:11:12.47#ibcon#wrote, iclass 5, count 0 2006.225.08:11:12.47#ibcon#about to read 3, iclass 5, count 0 2006.225.08:11:12.49#ibcon#read 3, iclass 5, count 0 2006.225.08:11:12.49#ibcon#about to read 4, iclass 5, count 0 2006.225.08:11:12.49#ibcon#read 4, iclass 5, count 0 2006.225.08:11:12.49#ibcon#about to read 5, iclass 5, count 0 2006.225.08:11:12.49#ibcon#read 5, iclass 5, count 0 2006.225.08:11:12.49#ibcon#about to read 6, iclass 5, count 0 2006.225.08:11:12.49#ibcon#read 6, iclass 5, count 0 2006.225.08:11:12.49#ibcon#end of sib2, iclass 5, count 0 2006.225.08:11:12.49#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:11:12.49#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:11:12.49#ibcon#[27=USB\r\n] 2006.225.08:11:12.49#ibcon#*before write, iclass 5, count 0 2006.225.08:11:12.49#ibcon#enter sib2, iclass 5, count 0 2006.225.08:11:12.49#ibcon#flushed, iclass 5, count 0 2006.225.08:11:12.49#ibcon#about to write, iclass 5, count 0 2006.225.08:11:12.49#ibcon#wrote, iclass 5, count 0 2006.225.08:11:12.49#ibcon#about to read 3, iclass 5, count 0 2006.225.08:11:12.52#ibcon#read 3, iclass 5, count 0 2006.225.08:11:12.52#ibcon#about to read 4, iclass 5, count 0 2006.225.08:11:12.52#ibcon#read 4, iclass 5, count 0 2006.225.08:11:12.52#ibcon#about to read 5, iclass 5, count 0 2006.225.08:11:12.52#ibcon#read 5, iclass 5, count 0 2006.225.08:11:12.52#ibcon#about to read 6, iclass 5, count 0 2006.225.08:11:12.52#ibcon#read 6, iclass 5, count 0 2006.225.08:11:12.52#ibcon#end of sib2, iclass 5, count 0 2006.225.08:11:12.52#ibcon#*after write, iclass 5, count 0 2006.225.08:11:12.52#ibcon#*before return 0, iclass 5, count 0 2006.225.08:11:12.52#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:11:12.52#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:11:12.52#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:11:12.52#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:11:12.52$vc4f8/vabw=wide 2006.225.08:11:12.52#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.08:11:12.52#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.08:11:12.52#ibcon#ireg 8 cls_cnt 0 2006.225.08:11:12.52#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:11:12.52#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:11:12.52#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:11:12.52#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:11:12.52#ibcon#first serial, iclass 10, count 0 2006.225.08:11:12.52#ibcon#enter sib2, iclass 10, count 0 2006.225.08:11:12.52#ibcon#flushed, iclass 10, count 0 2006.225.08:11:12.52#ibcon#about to write, iclass 10, count 0 2006.225.08:11:12.52#ibcon#wrote, iclass 10, count 0 2006.225.08:11:12.52#ibcon#about to read 3, iclass 10, count 0 2006.225.08:11:12.53#abcon#<5=/04 2.7 5.2 28.09 711003.3\r\n> 2006.225.08:11:12.54#ibcon#read 3, iclass 10, count 0 2006.225.08:11:12.54#ibcon#about to read 4, iclass 10, count 0 2006.225.08:11:12.54#ibcon#read 4, iclass 10, count 0 2006.225.08:11:12.54#ibcon#about to read 5, iclass 10, count 0 2006.225.08:11:12.54#ibcon#read 5, iclass 10, count 0 2006.225.08:11:12.54#ibcon#about to read 6, iclass 10, count 0 2006.225.08:11:12.54#ibcon#read 6, iclass 10, count 0 2006.225.08:11:12.54#ibcon#end of sib2, iclass 10, count 0 2006.225.08:11:12.54#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:11:12.54#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:11:12.54#ibcon#[25=BW32\r\n] 2006.225.08:11:12.54#ibcon#*before write, iclass 10, count 0 2006.225.08:11:12.54#ibcon#enter sib2, iclass 10, count 0 2006.225.08:11:12.54#ibcon#flushed, iclass 10, count 0 2006.225.08:11:12.54#ibcon#about to write, iclass 10, count 0 2006.225.08:11:12.54#ibcon#wrote, iclass 10, count 0 2006.225.08:11:12.54#ibcon#about to read 3, iclass 10, count 0 2006.225.08:11:12.55#abcon#{5=INTERFACE CLEAR} 2006.225.08:11:12.57#ibcon#read 3, iclass 10, count 0 2006.225.08:11:12.57#ibcon#about to read 4, iclass 10, count 0 2006.225.08:11:12.57#ibcon#read 4, iclass 10, count 0 2006.225.08:11:12.57#ibcon#about to read 5, iclass 10, count 0 2006.225.08:11:12.57#ibcon#read 5, iclass 10, count 0 2006.225.08:11:12.57#ibcon#about to read 6, iclass 10, count 0 2006.225.08:11:12.57#ibcon#read 6, iclass 10, count 0 2006.225.08:11:12.57#ibcon#end of sib2, iclass 10, count 0 2006.225.08:11:12.57#ibcon#*after write, iclass 10, count 0 2006.225.08:11:12.57#ibcon#*before return 0, iclass 10, count 0 2006.225.08:11:12.57#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:11:12.57#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:11:12.57#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:11:12.57#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:11:12.57$vc4f8/vbbw=wide 2006.225.08:11:12.57#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.08:11:12.57#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.08:11:12.57#ibcon#ireg 8 cls_cnt 0 2006.225.08:11:12.57#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:11:12.61#abcon#[5=S1D000X0/0*\r\n] 2006.225.08:11:12.64#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:11:12.64#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:11:12.64#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:11:12.64#ibcon#first serial, iclass 14, count 0 2006.225.08:11:12.64#ibcon#enter sib2, iclass 14, count 0 2006.225.08:11:12.64#ibcon#flushed, iclass 14, count 0 2006.225.08:11:12.64#ibcon#about to write, iclass 14, count 0 2006.225.08:11:12.64#ibcon#wrote, iclass 14, count 0 2006.225.08:11:12.64#ibcon#about to read 3, iclass 14, count 0 2006.225.08:11:12.66#ibcon#read 3, iclass 14, count 0 2006.225.08:11:12.66#ibcon#about to read 4, iclass 14, count 0 2006.225.08:11:12.66#ibcon#read 4, iclass 14, count 0 2006.225.08:11:12.66#ibcon#about to read 5, iclass 14, count 0 2006.225.08:11:12.66#ibcon#read 5, iclass 14, count 0 2006.225.08:11:12.66#ibcon#about to read 6, iclass 14, count 0 2006.225.08:11:12.66#ibcon#read 6, iclass 14, count 0 2006.225.08:11:12.66#ibcon#end of sib2, iclass 14, count 0 2006.225.08:11:12.66#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:11:12.66#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:11:12.66#ibcon#[27=BW32\r\n] 2006.225.08:11:12.66#ibcon#*before write, iclass 14, count 0 2006.225.08:11:12.66#ibcon#enter sib2, iclass 14, count 0 2006.225.08:11:12.66#ibcon#flushed, iclass 14, count 0 2006.225.08:11:12.66#ibcon#about to write, iclass 14, count 0 2006.225.08:11:12.66#ibcon#wrote, iclass 14, count 0 2006.225.08:11:12.66#ibcon#about to read 3, iclass 14, count 0 2006.225.08:11:12.69#ibcon#read 3, iclass 14, count 0 2006.225.08:11:12.69#ibcon#about to read 4, iclass 14, count 0 2006.225.08:11:12.69#ibcon#read 4, iclass 14, count 0 2006.225.08:11:12.69#ibcon#about to read 5, iclass 14, count 0 2006.225.08:11:12.69#ibcon#read 5, iclass 14, count 0 2006.225.08:11:12.69#ibcon#about to read 6, iclass 14, count 0 2006.225.08:11:12.69#ibcon#read 6, iclass 14, count 0 2006.225.08:11:12.69#ibcon#end of sib2, iclass 14, count 0 2006.225.08:11:12.69#ibcon#*after write, iclass 14, count 0 2006.225.08:11:12.69#ibcon#*before return 0, iclass 14, count 0 2006.225.08:11:12.69#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:11:12.69#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:11:12.69#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:11:12.69#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:11:12.69$4f8m12a/ifd4f 2006.225.08:11:12.69$ifd4f/lo= 2006.225.08:11:12.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:11:12.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:11:12.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:11:12.69$ifd4f/patch= 2006.225.08:11:12.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:11:12.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:11:12.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:11:12.69$4f8m12a/"form=m,16.000,1:2 2006.225.08:11:12.69$4f8m12a/"tpicd 2006.225.08:11:12.70$4f8m12a/echo=off 2006.225.08:11:12.70$4f8m12a/xlog=off 2006.225.08:11:12.70:!2006.225.08:11:50 2006.225.08:11:31.14#trakl#Source acquired 2006.225.08:11:31.14#flagr#flagr/antenna,acquired 2006.225.08:11:50.01:preob 2006.225.08:11:51.14/onsource/TRACKING 2006.225.08:11:51.14:!2006.225.08:12:00 2006.225.08:12:00.00:data_valid=on 2006.225.08:12:00.00:midob 2006.225.08:12:00.14/onsource/TRACKING 2006.225.08:12:00.14/wx/28.09,1003.4,71 2006.225.08:12:00.21/cable/+6.4048E-03 2006.225.08:12:01.30/va/01,08,usb,yes,28,29 2006.225.08:12:01.30/va/02,07,usb,yes,28,30 2006.225.08:12:01.30/va/03,06,usb,yes,30,30 2006.225.08:12:01.30/va/04,07,usb,yes,29,32 2006.225.08:12:01.30/va/05,07,usb,yes,31,33 2006.225.08:12:01.30/va/06,06,usb,yes,30,30 2006.225.08:12:01.30/va/07,06,usb,yes,31,31 2006.225.08:12:01.30/va/08,07,usb,yes,29,29 2006.225.08:12:01.53/valo/01,532.99,yes,locked 2006.225.08:12:01.53/valo/02,572.99,yes,locked 2006.225.08:12:01.53/valo/03,672.99,yes,locked 2006.225.08:12:01.53/valo/04,832.99,yes,locked 2006.225.08:12:01.53/valo/05,652.99,yes,locked 2006.225.08:12:01.53/valo/06,772.99,yes,locked 2006.225.08:12:01.53/valo/07,832.99,yes,locked 2006.225.08:12:01.53/valo/08,852.99,yes,locked 2006.225.08:12:02.62/vb/01,04,usb,yes,30,29 2006.225.08:12:02.62/vb/02,04,usb,yes,32,33 2006.225.08:12:02.62/vb/03,04,usb,yes,28,32 2006.225.08:12:02.62/vb/04,04,usb,yes,29,29 2006.225.08:12:02.62/vb/05,04,usb,yes,27,31 2006.225.08:12:02.62/vb/06,04,usb,yes,28,31 2006.225.08:12:02.62/vb/07,04,usb,yes,31,30 2006.225.08:12:02.62/vb/08,04,usb,yes,28,31 2006.225.08:12:02.85/vblo/01,632.99,yes,locked 2006.225.08:12:02.85/vblo/02,640.99,yes,locked 2006.225.08:12:02.85/vblo/03,656.99,yes,locked 2006.225.08:12:02.85/vblo/04,712.99,yes,locked 2006.225.08:12:02.85/vblo/05,744.99,yes,locked 2006.225.08:12:02.85/vblo/06,752.99,yes,locked 2006.225.08:12:02.85/vblo/07,734.99,yes,locked 2006.225.08:12:02.85/vblo/08,744.99,yes,locked 2006.225.08:12:03.00/vabw/8 2006.225.08:12:03.15/vbbw/8 2006.225.08:12:03.24/xfe/off,on,15.2 2006.225.08:12:03.62/ifatt/23,28,28,28 2006.225.08:12:04.07/fmout-gps/S +4.60E-07 2006.225.08:12:04.11:!2006.225.08:13:00 2006.225.08:13:00.00:data_valid=off 2006.225.08:13:00.01:postob 2006.225.08:13:00.18/cable/+6.4062E-03 2006.225.08:13:00.19/wx/28.09,1003.4,72 2006.225.08:13:01.07/fmout-gps/S +4.60E-07 2006.225.08:13:01.08:scan_name=225-0814,k06225,70 2006.225.08:13:01.08:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.225.08:13:02.14#flagr#flagr/antenna,new-source 2006.225.08:13:02.15:checkk5 2006.225.08:13:02.52/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:13:02.90/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:13:03.28/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:13:03.65/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:13:04.02/chk_obsdata//k5ts1/T2250812??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:13:04.38/chk_obsdata//k5ts2/T2250812??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:13:04.75/chk_obsdata//k5ts3/T2250812??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:13:05.12/chk_obsdata//k5ts4/T2250812??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:13:05.81/k5log//k5ts1_log_newline 2006.225.08:13:06.49/k5log//k5ts2_log_newline 2006.225.08:13:07.18/k5log//k5ts3_log_newline 2006.225.08:13:07.87/k5log//k5ts4_log_newline 2006.225.08:13:07.89/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:13:07.89:4f8m12a=2 2006.225.08:13:07.89$4f8m12a/echo=on 2006.225.08:13:07.89$4f8m12a/pcalon 2006.225.08:13:07.89$pcalon/"no phase cal control is implemented here 2006.225.08:13:07.89$4f8m12a/"tpicd=stop 2006.225.08:13:07.89$4f8m12a/vc4f8 2006.225.08:13:07.89$vc4f8/valo=1,532.99 2006.225.08:13:07.89#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.08:13:07.89#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.08:13:07.89#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:07.89#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:13:07.89#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:13:07.89#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:13:07.89#ibcon#enter wrdev, iclass 26, count 0 2006.225.08:13:07.89#ibcon#first serial, iclass 26, count 0 2006.225.08:13:07.89#ibcon#enter sib2, iclass 26, count 0 2006.225.08:13:07.89#ibcon#flushed, iclass 26, count 0 2006.225.08:13:07.89#ibcon#about to write, iclass 26, count 0 2006.225.08:13:07.89#ibcon#wrote, iclass 26, count 0 2006.225.08:13:07.89#ibcon#about to read 3, iclass 26, count 0 2006.225.08:13:07.93#ibcon#read 3, iclass 26, count 0 2006.225.08:13:07.93#ibcon#about to read 4, iclass 26, count 0 2006.225.08:13:07.93#ibcon#read 4, iclass 26, count 0 2006.225.08:13:07.93#ibcon#about to read 5, iclass 26, count 0 2006.225.08:13:07.93#ibcon#read 5, iclass 26, count 0 2006.225.08:13:07.93#ibcon#about to read 6, iclass 26, count 0 2006.225.08:13:07.93#ibcon#read 6, iclass 26, count 0 2006.225.08:13:07.93#ibcon#end of sib2, iclass 26, count 0 2006.225.08:13:07.93#ibcon#*mode == 0, iclass 26, count 0 2006.225.08:13:07.93#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.08:13:07.93#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:13:07.93#ibcon#*before write, iclass 26, count 0 2006.225.08:13:07.93#ibcon#enter sib2, iclass 26, count 0 2006.225.08:13:07.93#ibcon#flushed, iclass 26, count 0 2006.225.08:13:07.93#ibcon#about to write, iclass 26, count 0 2006.225.08:13:07.93#ibcon#wrote, iclass 26, count 0 2006.225.08:13:07.93#ibcon#about to read 3, iclass 26, count 0 2006.225.08:13:07.98#ibcon#read 3, iclass 26, count 0 2006.225.08:13:07.98#ibcon#about to read 4, iclass 26, count 0 2006.225.08:13:07.98#ibcon#read 4, iclass 26, count 0 2006.225.08:13:07.98#ibcon#about to read 5, iclass 26, count 0 2006.225.08:13:07.98#ibcon#read 5, iclass 26, count 0 2006.225.08:13:07.98#ibcon#about to read 6, iclass 26, count 0 2006.225.08:13:07.98#ibcon#read 6, iclass 26, count 0 2006.225.08:13:07.98#ibcon#end of sib2, iclass 26, count 0 2006.225.08:13:07.98#ibcon#*after write, iclass 26, count 0 2006.225.08:13:07.98#ibcon#*before return 0, iclass 26, count 0 2006.225.08:13:07.98#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:13:07.98#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:13:07.98#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.08:13:07.98#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.08:13:07.98$vc4f8/va=1,8 2006.225.08:13:07.98#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.08:13:07.98#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.08:13:07.98#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:07.98#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:13:07.98#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:13:07.98#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:13:07.98#ibcon#enter wrdev, iclass 28, count 2 2006.225.08:13:07.98#ibcon#first serial, iclass 28, count 2 2006.225.08:13:07.98#ibcon#enter sib2, iclass 28, count 2 2006.225.08:13:07.98#ibcon#flushed, iclass 28, count 2 2006.225.08:13:07.98#ibcon#about to write, iclass 28, count 2 2006.225.08:13:07.98#ibcon#wrote, iclass 28, count 2 2006.225.08:13:07.98#ibcon#about to read 3, iclass 28, count 2 2006.225.08:13:08.01#ibcon#read 3, iclass 28, count 2 2006.225.08:13:08.01#ibcon#about to read 4, iclass 28, count 2 2006.225.08:13:08.01#ibcon#read 4, iclass 28, count 2 2006.225.08:13:08.01#ibcon#about to read 5, iclass 28, count 2 2006.225.08:13:08.01#ibcon#read 5, iclass 28, count 2 2006.225.08:13:08.01#ibcon#about to read 6, iclass 28, count 2 2006.225.08:13:08.01#ibcon#read 6, iclass 28, count 2 2006.225.08:13:08.01#ibcon#end of sib2, iclass 28, count 2 2006.225.08:13:08.01#ibcon#*mode == 0, iclass 28, count 2 2006.225.08:13:08.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.08:13:08.01#ibcon#[25=AT01-08\r\n] 2006.225.08:13:08.01#ibcon#*before write, iclass 28, count 2 2006.225.08:13:08.01#ibcon#enter sib2, iclass 28, count 2 2006.225.08:13:08.01#ibcon#flushed, iclass 28, count 2 2006.225.08:13:08.01#ibcon#about to write, iclass 28, count 2 2006.225.08:13:08.01#ibcon#wrote, iclass 28, count 2 2006.225.08:13:08.01#ibcon#about to read 3, iclass 28, count 2 2006.225.08:13:08.04#ibcon#read 3, iclass 28, count 2 2006.225.08:13:08.04#ibcon#about to read 4, iclass 28, count 2 2006.225.08:13:08.04#ibcon#read 4, iclass 28, count 2 2006.225.08:13:08.04#ibcon#about to read 5, iclass 28, count 2 2006.225.08:13:08.04#ibcon#read 5, iclass 28, count 2 2006.225.08:13:08.04#ibcon#about to read 6, iclass 28, count 2 2006.225.08:13:08.04#ibcon#read 6, iclass 28, count 2 2006.225.08:13:08.04#ibcon#end of sib2, iclass 28, count 2 2006.225.08:13:08.04#ibcon#*after write, iclass 28, count 2 2006.225.08:13:08.04#ibcon#*before return 0, iclass 28, count 2 2006.225.08:13:08.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:13:08.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:13:08.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.08:13:08.04#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:08.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:13:08.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:13:08.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:13:08.16#ibcon#enter wrdev, iclass 28, count 0 2006.225.08:13:08.16#ibcon#first serial, iclass 28, count 0 2006.225.08:13:08.16#ibcon#enter sib2, iclass 28, count 0 2006.225.08:13:08.16#ibcon#flushed, iclass 28, count 0 2006.225.08:13:08.16#ibcon#about to write, iclass 28, count 0 2006.225.08:13:08.16#ibcon#wrote, iclass 28, count 0 2006.225.08:13:08.16#ibcon#about to read 3, iclass 28, count 0 2006.225.08:13:08.18#ibcon#read 3, iclass 28, count 0 2006.225.08:13:08.18#ibcon#about to read 4, iclass 28, count 0 2006.225.08:13:08.18#ibcon#read 4, iclass 28, count 0 2006.225.08:13:08.18#ibcon#about to read 5, iclass 28, count 0 2006.225.08:13:08.18#ibcon#read 5, iclass 28, count 0 2006.225.08:13:08.18#ibcon#about to read 6, iclass 28, count 0 2006.225.08:13:08.18#ibcon#read 6, iclass 28, count 0 2006.225.08:13:08.18#ibcon#end of sib2, iclass 28, count 0 2006.225.08:13:08.18#ibcon#*mode == 0, iclass 28, count 0 2006.225.08:13:08.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.08:13:08.18#ibcon#[25=USB\r\n] 2006.225.08:13:08.18#ibcon#*before write, iclass 28, count 0 2006.225.08:13:08.18#ibcon#enter sib2, iclass 28, count 0 2006.225.08:13:08.18#ibcon#flushed, iclass 28, count 0 2006.225.08:13:08.18#ibcon#about to write, iclass 28, count 0 2006.225.08:13:08.18#ibcon#wrote, iclass 28, count 0 2006.225.08:13:08.18#ibcon#about to read 3, iclass 28, count 0 2006.225.08:13:08.21#ibcon#read 3, iclass 28, count 0 2006.225.08:13:08.21#ibcon#about to read 4, iclass 28, count 0 2006.225.08:13:08.21#ibcon#read 4, iclass 28, count 0 2006.225.08:13:08.21#ibcon#about to read 5, iclass 28, count 0 2006.225.08:13:08.21#ibcon#read 5, iclass 28, count 0 2006.225.08:13:08.21#ibcon#about to read 6, iclass 28, count 0 2006.225.08:13:08.21#ibcon#read 6, iclass 28, count 0 2006.225.08:13:08.21#ibcon#end of sib2, iclass 28, count 0 2006.225.08:13:08.21#ibcon#*after write, iclass 28, count 0 2006.225.08:13:08.21#ibcon#*before return 0, iclass 28, count 0 2006.225.08:13:08.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:13:08.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:13:08.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.08:13:08.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.08:13:08.21$vc4f8/valo=2,572.99 2006.225.08:13:08.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.08:13:08.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.08:13:08.21#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:08.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:13:08.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:13:08.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:13:08.21#ibcon#enter wrdev, iclass 30, count 0 2006.225.08:13:08.21#ibcon#first serial, iclass 30, count 0 2006.225.08:13:08.21#ibcon#enter sib2, iclass 30, count 0 2006.225.08:13:08.21#ibcon#flushed, iclass 30, count 0 2006.225.08:13:08.21#ibcon#about to write, iclass 30, count 0 2006.225.08:13:08.21#ibcon#wrote, iclass 30, count 0 2006.225.08:13:08.21#ibcon#about to read 3, iclass 30, count 0 2006.225.08:13:08.23#ibcon#read 3, iclass 30, count 0 2006.225.08:13:08.23#ibcon#about to read 4, iclass 30, count 0 2006.225.08:13:08.23#ibcon#read 4, iclass 30, count 0 2006.225.08:13:08.23#ibcon#about to read 5, iclass 30, count 0 2006.225.08:13:08.23#ibcon#read 5, iclass 30, count 0 2006.225.08:13:08.23#ibcon#about to read 6, iclass 30, count 0 2006.225.08:13:08.23#ibcon#read 6, iclass 30, count 0 2006.225.08:13:08.23#ibcon#end of sib2, iclass 30, count 0 2006.225.08:13:08.23#ibcon#*mode == 0, iclass 30, count 0 2006.225.08:13:08.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.08:13:08.23#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:13:08.23#ibcon#*before write, iclass 30, count 0 2006.225.08:13:08.23#ibcon#enter sib2, iclass 30, count 0 2006.225.08:13:08.23#ibcon#flushed, iclass 30, count 0 2006.225.08:13:08.23#ibcon#about to write, iclass 30, count 0 2006.225.08:13:08.23#ibcon#wrote, iclass 30, count 0 2006.225.08:13:08.23#ibcon#about to read 3, iclass 30, count 0 2006.225.08:13:08.27#ibcon#read 3, iclass 30, count 0 2006.225.08:13:08.27#ibcon#about to read 4, iclass 30, count 0 2006.225.08:13:08.27#ibcon#read 4, iclass 30, count 0 2006.225.08:13:08.27#ibcon#about to read 5, iclass 30, count 0 2006.225.08:13:08.27#ibcon#read 5, iclass 30, count 0 2006.225.08:13:08.27#ibcon#about to read 6, iclass 30, count 0 2006.225.08:13:08.27#ibcon#read 6, iclass 30, count 0 2006.225.08:13:08.27#ibcon#end of sib2, iclass 30, count 0 2006.225.08:13:08.27#ibcon#*after write, iclass 30, count 0 2006.225.08:13:08.27#ibcon#*before return 0, iclass 30, count 0 2006.225.08:13:08.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:13:08.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:13:08.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.08:13:08.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.08:13:08.27$vc4f8/va=2,7 2006.225.08:13:08.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.225.08:13:08.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.225.08:13:08.27#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:08.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:13:08.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:13:08.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:13:08.33#ibcon#enter wrdev, iclass 32, count 2 2006.225.08:13:08.33#ibcon#first serial, iclass 32, count 2 2006.225.08:13:08.33#ibcon#enter sib2, iclass 32, count 2 2006.225.08:13:08.33#ibcon#flushed, iclass 32, count 2 2006.225.08:13:08.33#ibcon#about to write, iclass 32, count 2 2006.225.08:13:08.33#ibcon#wrote, iclass 32, count 2 2006.225.08:13:08.33#ibcon#about to read 3, iclass 32, count 2 2006.225.08:13:08.35#ibcon#read 3, iclass 32, count 2 2006.225.08:13:08.35#ibcon#about to read 4, iclass 32, count 2 2006.225.08:13:08.35#ibcon#read 4, iclass 32, count 2 2006.225.08:13:08.35#ibcon#about to read 5, iclass 32, count 2 2006.225.08:13:08.35#ibcon#read 5, iclass 32, count 2 2006.225.08:13:08.35#ibcon#about to read 6, iclass 32, count 2 2006.225.08:13:08.35#ibcon#read 6, iclass 32, count 2 2006.225.08:13:08.35#ibcon#end of sib2, iclass 32, count 2 2006.225.08:13:08.35#ibcon#*mode == 0, iclass 32, count 2 2006.225.08:13:08.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.225.08:13:08.35#ibcon#[25=AT02-07\r\n] 2006.225.08:13:08.35#ibcon#*before write, iclass 32, count 2 2006.225.08:13:08.35#ibcon#enter sib2, iclass 32, count 2 2006.225.08:13:08.35#ibcon#flushed, iclass 32, count 2 2006.225.08:13:08.35#ibcon#about to write, iclass 32, count 2 2006.225.08:13:08.35#ibcon#wrote, iclass 32, count 2 2006.225.08:13:08.35#ibcon#about to read 3, iclass 32, count 2 2006.225.08:13:08.39#ibcon#read 3, iclass 32, count 2 2006.225.08:13:08.39#ibcon#about to read 4, iclass 32, count 2 2006.225.08:13:08.39#ibcon#read 4, iclass 32, count 2 2006.225.08:13:08.39#ibcon#about to read 5, iclass 32, count 2 2006.225.08:13:08.39#ibcon#read 5, iclass 32, count 2 2006.225.08:13:08.39#ibcon#about to read 6, iclass 32, count 2 2006.225.08:13:08.39#ibcon#read 6, iclass 32, count 2 2006.225.08:13:08.39#ibcon#end of sib2, iclass 32, count 2 2006.225.08:13:08.39#ibcon#*after write, iclass 32, count 2 2006.225.08:13:08.39#ibcon#*before return 0, iclass 32, count 2 2006.225.08:13:08.39#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:13:08.39#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:13:08.39#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.225.08:13:08.39#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:08.39#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:13:08.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:13:08.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:13:08.50#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:13:08.50#ibcon#first serial, iclass 32, count 0 2006.225.08:13:08.50#ibcon#enter sib2, iclass 32, count 0 2006.225.08:13:08.50#ibcon#flushed, iclass 32, count 0 2006.225.08:13:08.50#ibcon#about to write, iclass 32, count 0 2006.225.08:13:08.50#ibcon#wrote, iclass 32, count 0 2006.225.08:13:08.50#ibcon#about to read 3, iclass 32, count 0 2006.225.08:13:08.52#ibcon#read 3, iclass 32, count 0 2006.225.08:13:08.52#ibcon#about to read 4, iclass 32, count 0 2006.225.08:13:08.52#ibcon#read 4, iclass 32, count 0 2006.225.08:13:08.52#ibcon#about to read 5, iclass 32, count 0 2006.225.08:13:08.52#ibcon#read 5, iclass 32, count 0 2006.225.08:13:08.52#ibcon#about to read 6, iclass 32, count 0 2006.225.08:13:08.52#ibcon#read 6, iclass 32, count 0 2006.225.08:13:08.52#ibcon#end of sib2, iclass 32, count 0 2006.225.08:13:08.52#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:13:08.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:13:08.52#ibcon#[25=USB\r\n] 2006.225.08:13:08.52#ibcon#*before write, iclass 32, count 0 2006.225.08:13:08.52#ibcon#enter sib2, iclass 32, count 0 2006.225.08:13:08.52#ibcon#flushed, iclass 32, count 0 2006.225.08:13:08.52#ibcon#about to write, iclass 32, count 0 2006.225.08:13:08.52#ibcon#wrote, iclass 32, count 0 2006.225.08:13:08.52#ibcon#about to read 3, iclass 32, count 0 2006.225.08:13:08.55#ibcon#read 3, iclass 32, count 0 2006.225.08:13:08.55#ibcon#about to read 4, iclass 32, count 0 2006.225.08:13:08.55#ibcon#read 4, iclass 32, count 0 2006.225.08:13:08.55#ibcon#about to read 5, iclass 32, count 0 2006.225.08:13:08.55#ibcon#read 5, iclass 32, count 0 2006.225.08:13:08.55#ibcon#about to read 6, iclass 32, count 0 2006.225.08:13:08.55#ibcon#read 6, iclass 32, count 0 2006.225.08:13:08.55#ibcon#end of sib2, iclass 32, count 0 2006.225.08:13:08.55#ibcon#*after write, iclass 32, count 0 2006.225.08:13:08.55#ibcon#*before return 0, iclass 32, count 0 2006.225.08:13:08.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:13:08.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:13:08.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:13:08.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:13:08.55$vc4f8/valo=3,672.99 2006.225.08:13:08.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.08:13:08.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.08:13:08.55#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:08.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:13:08.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:13:08.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:13:08.55#ibcon#enter wrdev, iclass 34, count 0 2006.225.08:13:08.55#ibcon#first serial, iclass 34, count 0 2006.225.08:13:08.55#ibcon#enter sib2, iclass 34, count 0 2006.225.08:13:08.55#ibcon#flushed, iclass 34, count 0 2006.225.08:13:08.55#ibcon#about to write, iclass 34, count 0 2006.225.08:13:08.55#ibcon#wrote, iclass 34, count 0 2006.225.08:13:08.55#ibcon#about to read 3, iclass 34, count 0 2006.225.08:13:08.58#ibcon#read 3, iclass 34, count 0 2006.225.08:13:08.58#ibcon#about to read 4, iclass 34, count 0 2006.225.08:13:08.58#ibcon#read 4, iclass 34, count 0 2006.225.08:13:08.58#ibcon#about to read 5, iclass 34, count 0 2006.225.08:13:08.58#ibcon#read 5, iclass 34, count 0 2006.225.08:13:08.58#ibcon#about to read 6, iclass 34, count 0 2006.225.08:13:08.58#ibcon#read 6, iclass 34, count 0 2006.225.08:13:08.58#ibcon#end of sib2, iclass 34, count 0 2006.225.08:13:08.58#ibcon#*mode == 0, iclass 34, count 0 2006.225.08:13:08.58#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.08:13:08.58#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:13:08.58#ibcon#*before write, iclass 34, count 0 2006.225.08:13:08.58#ibcon#enter sib2, iclass 34, count 0 2006.225.08:13:08.58#ibcon#flushed, iclass 34, count 0 2006.225.08:13:08.58#ibcon#about to write, iclass 34, count 0 2006.225.08:13:08.58#ibcon#wrote, iclass 34, count 0 2006.225.08:13:08.58#ibcon#about to read 3, iclass 34, count 0 2006.225.08:13:08.62#ibcon#read 3, iclass 34, count 0 2006.225.08:13:08.62#ibcon#about to read 4, iclass 34, count 0 2006.225.08:13:08.62#ibcon#read 4, iclass 34, count 0 2006.225.08:13:08.62#ibcon#about to read 5, iclass 34, count 0 2006.225.08:13:08.62#ibcon#read 5, iclass 34, count 0 2006.225.08:13:08.62#ibcon#about to read 6, iclass 34, count 0 2006.225.08:13:08.62#ibcon#read 6, iclass 34, count 0 2006.225.08:13:08.62#ibcon#end of sib2, iclass 34, count 0 2006.225.08:13:08.62#ibcon#*after write, iclass 34, count 0 2006.225.08:13:08.62#ibcon#*before return 0, iclass 34, count 0 2006.225.08:13:08.62#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:13:08.62#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:13:08.62#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.08:13:08.62#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.08:13:08.62$vc4f8/va=3,6 2006.225.08:13:08.62#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.08:13:08.62#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.08:13:08.62#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:08.62#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:13:08.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:13:08.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:13:08.67#ibcon#enter wrdev, iclass 36, count 2 2006.225.08:13:08.67#ibcon#first serial, iclass 36, count 2 2006.225.08:13:08.67#ibcon#enter sib2, iclass 36, count 2 2006.225.08:13:08.67#ibcon#flushed, iclass 36, count 2 2006.225.08:13:08.67#ibcon#about to write, iclass 36, count 2 2006.225.08:13:08.67#ibcon#wrote, iclass 36, count 2 2006.225.08:13:08.67#ibcon#about to read 3, iclass 36, count 2 2006.225.08:13:08.69#ibcon#read 3, iclass 36, count 2 2006.225.08:13:08.69#ibcon#about to read 4, iclass 36, count 2 2006.225.08:13:08.69#ibcon#read 4, iclass 36, count 2 2006.225.08:13:08.69#ibcon#about to read 5, iclass 36, count 2 2006.225.08:13:08.69#ibcon#read 5, iclass 36, count 2 2006.225.08:13:08.69#ibcon#about to read 6, iclass 36, count 2 2006.225.08:13:08.69#ibcon#read 6, iclass 36, count 2 2006.225.08:13:08.69#ibcon#end of sib2, iclass 36, count 2 2006.225.08:13:08.69#ibcon#*mode == 0, iclass 36, count 2 2006.225.08:13:08.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.08:13:08.69#ibcon#[25=AT03-06\r\n] 2006.225.08:13:08.69#ibcon#*before write, iclass 36, count 2 2006.225.08:13:08.69#ibcon#enter sib2, iclass 36, count 2 2006.225.08:13:08.69#ibcon#flushed, iclass 36, count 2 2006.225.08:13:08.69#ibcon#about to write, iclass 36, count 2 2006.225.08:13:08.69#ibcon#wrote, iclass 36, count 2 2006.225.08:13:08.69#ibcon#about to read 3, iclass 36, count 2 2006.225.08:13:08.72#ibcon#read 3, iclass 36, count 2 2006.225.08:13:08.72#ibcon#about to read 4, iclass 36, count 2 2006.225.08:13:08.72#ibcon#read 4, iclass 36, count 2 2006.225.08:13:08.72#ibcon#about to read 5, iclass 36, count 2 2006.225.08:13:08.72#ibcon#read 5, iclass 36, count 2 2006.225.08:13:08.72#ibcon#about to read 6, iclass 36, count 2 2006.225.08:13:08.72#ibcon#read 6, iclass 36, count 2 2006.225.08:13:08.72#ibcon#end of sib2, iclass 36, count 2 2006.225.08:13:08.72#ibcon#*after write, iclass 36, count 2 2006.225.08:13:08.72#ibcon#*before return 0, iclass 36, count 2 2006.225.08:13:08.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:13:08.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:13:08.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.08:13:08.72#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:08.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:13:08.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:13:08.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:13:08.84#ibcon#enter wrdev, iclass 36, count 0 2006.225.08:13:08.84#ibcon#first serial, iclass 36, count 0 2006.225.08:13:08.84#ibcon#enter sib2, iclass 36, count 0 2006.225.08:13:08.84#ibcon#flushed, iclass 36, count 0 2006.225.08:13:08.84#ibcon#about to write, iclass 36, count 0 2006.225.08:13:08.84#ibcon#wrote, iclass 36, count 0 2006.225.08:13:08.84#ibcon#about to read 3, iclass 36, count 0 2006.225.08:13:08.86#ibcon#read 3, iclass 36, count 0 2006.225.08:13:08.86#ibcon#about to read 4, iclass 36, count 0 2006.225.08:13:08.86#ibcon#read 4, iclass 36, count 0 2006.225.08:13:08.86#ibcon#about to read 5, iclass 36, count 0 2006.225.08:13:08.86#ibcon#read 5, iclass 36, count 0 2006.225.08:13:08.86#ibcon#about to read 6, iclass 36, count 0 2006.225.08:13:08.86#ibcon#read 6, iclass 36, count 0 2006.225.08:13:08.86#ibcon#end of sib2, iclass 36, count 0 2006.225.08:13:08.86#ibcon#*mode == 0, iclass 36, count 0 2006.225.08:13:08.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.08:13:08.86#ibcon#[25=USB\r\n] 2006.225.08:13:08.86#ibcon#*before write, iclass 36, count 0 2006.225.08:13:08.86#ibcon#enter sib2, iclass 36, count 0 2006.225.08:13:08.86#ibcon#flushed, iclass 36, count 0 2006.225.08:13:08.86#ibcon#about to write, iclass 36, count 0 2006.225.08:13:08.86#ibcon#wrote, iclass 36, count 0 2006.225.08:13:08.86#ibcon#about to read 3, iclass 36, count 0 2006.225.08:13:08.89#ibcon#read 3, iclass 36, count 0 2006.225.08:13:08.89#ibcon#about to read 4, iclass 36, count 0 2006.225.08:13:08.89#ibcon#read 4, iclass 36, count 0 2006.225.08:13:08.89#ibcon#about to read 5, iclass 36, count 0 2006.225.08:13:08.89#ibcon#read 5, iclass 36, count 0 2006.225.08:13:08.89#ibcon#about to read 6, iclass 36, count 0 2006.225.08:13:08.89#ibcon#read 6, iclass 36, count 0 2006.225.08:13:08.89#ibcon#end of sib2, iclass 36, count 0 2006.225.08:13:08.89#ibcon#*after write, iclass 36, count 0 2006.225.08:13:08.89#ibcon#*before return 0, iclass 36, count 0 2006.225.08:13:08.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:13:08.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:13:08.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.08:13:08.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.08:13:08.89$vc4f8/valo=4,832.99 2006.225.08:13:08.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.08:13:08.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.08:13:08.89#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:08.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:13:08.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:13:08.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:13:08.89#ibcon#enter wrdev, iclass 38, count 0 2006.225.08:13:08.89#ibcon#first serial, iclass 38, count 0 2006.225.08:13:08.89#ibcon#enter sib2, iclass 38, count 0 2006.225.08:13:08.89#ibcon#flushed, iclass 38, count 0 2006.225.08:13:08.89#ibcon#about to write, iclass 38, count 0 2006.225.08:13:08.89#ibcon#wrote, iclass 38, count 0 2006.225.08:13:08.89#ibcon#about to read 3, iclass 38, count 0 2006.225.08:13:08.91#ibcon#read 3, iclass 38, count 0 2006.225.08:13:08.91#ibcon#about to read 4, iclass 38, count 0 2006.225.08:13:08.91#ibcon#read 4, iclass 38, count 0 2006.225.08:13:08.91#ibcon#about to read 5, iclass 38, count 0 2006.225.08:13:08.91#ibcon#read 5, iclass 38, count 0 2006.225.08:13:08.91#ibcon#about to read 6, iclass 38, count 0 2006.225.08:13:08.91#ibcon#read 6, iclass 38, count 0 2006.225.08:13:08.91#ibcon#end of sib2, iclass 38, count 0 2006.225.08:13:08.91#ibcon#*mode == 0, iclass 38, count 0 2006.225.08:13:08.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.08:13:08.91#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:13:08.91#ibcon#*before write, iclass 38, count 0 2006.225.08:13:08.91#ibcon#enter sib2, iclass 38, count 0 2006.225.08:13:08.91#ibcon#flushed, iclass 38, count 0 2006.225.08:13:08.91#ibcon#about to write, iclass 38, count 0 2006.225.08:13:08.91#ibcon#wrote, iclass 38, count 0 2006.225.08:13:08.91#ibcon#about to read 3, iclass 38, count 0 2006.225.08:13:08.95#ibcon#read 3, iclass 38, count 0 2006.225.08:13:08.95#ibcon#about to read 4, iclass 38, count 0 2006.225.08:13:08.95#ibcon#read 4, iclass 38, count 0 2006.225.08:13:08.95#ibcon#about to read 5, iclass 38, count 0 2006.225.08:13:08.95#ibcon#read 5, iclass 38, count 0 2006.225.08:13:08.95#ibcon#about to read 6, iclass 38, count 0 2006.225.08:13:08.95#ibcon#read 6, iclass 38, count 0 2006.225.08:13:08.95#ibcon#end of sib2, iclass 38, count 0 2006.225.08:13:08.95#ibcon#*after write, iclass 38, count 0 2006.225.08:13:08.95#ibcon#*before return 0, iclass 38, count 0 2006.225.08:13:08.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:13:08.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:13:08.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.08:13:08.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.08:13:08.95$vc4f8/va=4,7 2006.225.08:13:08.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.225.08:13:08.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.225.08:13:08.95#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:08.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:13:09.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:13:09.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:13:09.01#ibcon#enter wrdev, iclass 40, count 2 2006.225.08:13:09.01#ibcon#first serial, iclass 40, count 2 2006.225.08:13:09.01#ibcon#enter sib2, iclass 40, count 2 2006.225.08:13:09.01#ibcon#flushed, iclass 40, count 2 2006.225.08:13:09.01#ibcon#about to write, iclass 40, count 2 2006.225.08:13:09.01#ibcon#wrote, iclass 40, count 2 2006.225.08:13:09.01#ibcon#about to read 3, iclass 40, count 2 2006.225.08:13:09.03#ibcon#read 3, iclass 40, count 2 2006.225.08:13:09.03#ibcon#about to read 4, iclass 40, count 2 2006.225.08:13:09.03#ibcon#read 4, iclass 40, count 2 2006.225.08:13:09.03#ibcon#about to read 5, iclass 40, count 2 2006.225.08:13:09.03#ibcon#read 5, iclass 40, count 2 2006.225.08:13:09.03#ibcon#about to read 6, iclass 40, count 2 2006.225.08:13:09.03#ibcon#read 6, iclass 40, count 2 2006.225.08:13:09.03#ibcon#end of sib2, iclass 40, count 2 2006.225.08:13:09.03#ibcon#*mode == 0, iclass 40, count 2 2006.225.08:13:09.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.225.08:13:09.03#ibcon#[25=AT04-07\r\n] 2006.225.08:13:09.03#ibcon#*before write, iclass 40, count 2 2006.225.08:13:09.03#ibcon#enter sib2, iclass 40, count 2 2006.225.08:13:09.03#ibcon#flushed, iclass 40, count 2 2006.225.08:13:09.03#ibcon#about to write, iclass 40, count 2 2006.225.08:13:09.03#ibcon#wrote, iclass 40, count 2 2006.225.08:13:09.03#ibcon#about to read 3, iclass 40, count 2 2006.225.08:13:09.06#ibcon#read 3, iclass 40, count 2 2006.225.08:13:09.06#ibcon#about to read 4, iclass 40, count 2 2006.225.08:13:09.06#ibcon#read 4, iclass 40, count 2 2006.225.08:13:09.06#ibcon#about to read 5, iclass 40, count 2 2006.225.08:13:09.06#ibcon#read 5, iclass 40, count 2 2006.225.08:13:09.06#ibcon#about to read 6, iclass 40, count 2 2006.225.08:13:09.06#ibcon#read 6, iclass 40, count 2 2006.225.08:13:09.06#ibcon#end of sib2, iclass 40, count 2 2006.225.08:13:09.06#ibcon#*after write, iclass 40, count 2 2006.225.08:13:09.06#ibcon#*before return 0, iclass 40, count 2 2006.225.08:13:09.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:13:09.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:13:09.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.225.08:13:09.06#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:09.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:13:09.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:13:09.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:13:09.18#ibcon#enter wrdev, iclass 40, count 0 2006.225.08:13:09.18#ibcon#first serial, iclass 40, count 0 2006.225.08:13:09.18#ibcon#enter sib2, iclass 40, count 0 2006.225.08:13:09.18#ibcon#flushed, iclass 40, count 0 2006.225.08:13:09.18#ibcon#about to write, iclass 40, count 0 2006.225.08:13:09.18#ibcon#wrote, iclass 40, count 0 2006.225.08:13:09.18#ibcon#about to read 3, iclass 40, count 0 2006.225.08:13:09.20#ibcon#read 3, iclass 40, count 0 2006.225.08:13:09.20#ibcon#about to read 4, iclass 40, count 0 2006.225.08:13:09.20#ibcon#read 4, iclass 40, count 0 2006.225.08:13:09.20#ibcon#about to read 5, iclass 40, count 0 2006.225.08:13:09.20#ibcon#read 5, iclass 40, count 0 2006.225.08:13:09.20#ibcon#about to read 6, iclass 40, count 0 2006.225.08:13:09.20#ibcon#read 6, iclass 40, count 0 2006.225.08:13:09.20#ibcon#end of sib2, iclass 40, count 0 2006.225.08:13:09.20#ibcon#*mode == 0, iclass 40, count 0 2006.225.08:13:09.20#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.08:13:09.20#ibcon#[25=USB\r\n] 2006.225.08:13:09.20#ibcon#*before write, iclass 40, count 0 2006.225.08:13:09.20#ibcon#enter sib2, iclass 40, count 0 2006.225.08:13:09.20#ibcon#flushed, iclass 40, count 0 2006.225.08:13:09.20#ibcon#about to write, iclass 40, count 0 2006.225.08:13:09.20#ibcon#wrote, iclass 40, count 0 2006.225.08:13:09.20#ibcon#about to read 3, iclass 40, count 0 2006.225.08:13:09.23#ibcon#read 3, iclass 40, count 0 2006.225.08:13:09.23#ibcon#about to read 4, iclass 40, count 0 2006.225.08:13:09.23#ibcon#read 4, iclass 40, count 0 2006.225.08:13:09.23#ibcon#about to read 5, iclass 40, count 0 2006.225.08:13:09.23#ibcon#read 5, iclass 40, count 0 2006.225.08:13:09.23#ibcon#about to read 6, iclass 40, count 0 2006.225.08:13:09.23#ibcon#read 6, iclass 40, count 0 2006.225.08:13:09.23#ibcon#end of sib2, iclass 40, count 0 2006.225.08:13:09.23#ibcon#*after write, iclass 40, count 0 2006.225.08:13:09.23#ibcon#*before return 0, iclass 40, count 0 2006.225.08:13:09.23#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:13:09.23#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:13:09.23#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.08:13:09.23#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.08:13:09.23$vc4f8/valo=5,652.99 2006.225.08:13:09.23#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.08:13:09.23#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.08:13:09.23#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:09.23#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:13:09.23#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:13:09.23#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:13:09.23#ibcon#enter wrdev, iclass 4, count 0 2006.225.08:13:09.23#ibcon#first serial, iclass 4, count 0 2006.225.08:13:09.23#ibcon#enter sib2, iclass 4, count 0 2006.225.08:13:09.23#ibcon#flushed, iclass 4, count 0 2006.225.08:13:09.23#ibcon#about to write, iclass 4, count 0 2006.225.08:13:09.23#ibcon#wrote, iclass 4, count 0 2006.225.08:13:09.23#ibcon#about to read 3, iclass 4, count 0 2006.225.08:13:09.25#ibcon#read 3, iclass 4, count 0 2006.225.08:13:09.25#ibcon#about to read 4, iclass 4, count 0 2006.225.08:13:09.25#ibcon#read 4, iclass 4, count 0 2006.225.08:13:09.25#ibcon#about to read 5, iclass 4, count 0 2006.225.08:13:09.25#ibcon#read 5, iclass 4, count 0 2006.225.08:13:09.25#ibcon#about to read 6, iclass 4, count 0 2006.225.08:13:09.25#ibcon#read 6, iclass 4, count 0 2006.225.08:13:09.25#ibcon#end of sib2, iclass 4, count 0 2006.225.08:13:09.25#ibcon#*mode == 0, iclass 4, count 0 2006.225.08:13:09.25#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.08:13:09.25#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:13:09.25#ibcon#*before write, iclass 4, count 0 2006.225.08:13:09.25#ibcon#enter sib2, iclass 4, count 0 2006.225.08:13:09.25#ibcon#flushed, iclass 4, count 0 2006.225.08:13:09.25#ibcon#about to write, iclass 4, count 0 2006.225.08:13:09.25#ibcon#wrote, iclass 4, count 0 2006.225.08:13:09.25#ibcon#about to read 3, iclass 4, count 0 2006.225.08:13:09.29#ibcon#read 3, iclass 4, count 0 2006.225.08:13:09.29#ibcon#about to read 4, iclass 4, count 0 2006.225.08:13:09.29#ibcon#read 4, iclass 4, count 0 2006.225.08:13:09.29#ibcon#about to read 5, iclass 4, count 0 2006.225.08:13:09.29#ibcon#read 5, iclass 4, count 0 2006.225.08:13:09.29#ibcon#about to read 6, iclass 4, count 0 2006.225.08:13:09.29#ibcon#read 6, iclass 4, count 0 2006.225.08:13:09.29#ibcon#end of sib2, iclass 4, count 0 2006.225.08:13:09.29#ibcon#*after write, iclass 4, count 0 2006.225.08:13:09.29#ibcon#*before return 0, iclass 4, count 0 2006.225.08:13:09.29#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:13:09.29#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:13:09.29#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.08:13:09.29#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.08:13:09.29$vc4f8/va=5,7 2006.225.08:13:09.29#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.225.08:13:09.29#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.225.08:13:09.29#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:09.29#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:13:09.35#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:13:09.35#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:13:09.35#ibcon#enter wrdev, iclass 6, count 2 2006.225.08:13:09.35#ibcon#first serial, iclass 6, count 2 2006.225.08:13:09.35#ibcon#enter sib2, iclass 6, count 2 2006.225.08:13:09.35#ibcon#flushed, iclass 6, count 2 2006.225.08:13:09.35#ibcon#about to write, iclass 6, count 2 2006.225.08:13:09.35#ibcon#wrote, iclass 6, count 2 2006.225.08:13:09.35#ibcon#about to read 3, iclass 6, count 2 2006.225.08:13:09.37#ibcon#read 3, iclass 6, count 2 2006.225.08:13:09.37#ibcon#about to read 4, iclass 6, count 2 2006.225.08:13:09.37#ibcon#read 4, iclass 6, count 2 2006.225.08:13:09.37#ibcon#about to read 5, iclass 6, count 2 2006.225.08:13:09.37#ibcon#read 5, iclass 6, count 2 2006.225.08:13:09.37#ibcon#about to read 6, iclass 6, count 2 2006.225.08:13:09.37#ibcon#read 6, iclass 6, count 2 2006.225.08:13:09.37#ibcon#end of sib2, iclass 6, count 2 2006.225.08:13:09.37#ibcon#*mode == 0, iclass 6, count 2 2006.225.08:13:09.37#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.225.08:13:09.37#ibcon#[25=AT05-07\r\n] 2006.225.08:13:09.37#ibcon#*before write, iclass 6, count 2 2006.225.08:13:09.37#ibcon#enter sib2, iclass 6, count 2 2006.225.08:13:09.37#ibcon#flushed, iclass 6, count 2 2006.225.08:13:09.37#ibcon#about to write, iclass 6, count 2 2006.225.08:13:09.37#ibcon#wrote, iclass 6, count 2 2006.225.08:13:09.37#ibcon#about to read 3, iclass 6, count 2 2006.225.08:13:09.40#ibcon#read 3, iclass 6, count 2 2006.225.08:13:09.40#ibcon#about to read 4, iclass 6, count 2 2006.225.08:13:09.40#ibcon#read 4, iclass 6, count 2 2006.225.08:13:09.40#ibcon#about to read 5, iclass 6, count 2 2006.225.08:13:09.40#ibcon#read 5, iclass 6, count 2 2006.225.08:13:09.40#ibcon#about to read 6, iclass 6, count 2 2006.225.08:13:09.40#ibcon#read 6, iclass 6, count 2 2006.225.08:13:09.40#ibcon#end of sib2, iclass 6, count 2 2006.225.08:13:09.40#ibcon#*after write, iclass 6, count 2 2006.225.08:13:09.40#ibcon#*before return 0, iclass 6, count 2 2006.225.08:13:09.40#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:13:09.40#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:13:09.40#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.225.08:13:09.40#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:09.40#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:13:09.52#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:13:09.52#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:13:09.52#ibcon#enter wrdev, iclass 6, count 0 2006.225.08:13:09.52#ibcon#first serial, iclass 6, count 0 2006.225.08:13:09.52#ibcon#enter sib2, iclass 6, count 0 2006.225.08:13:09.52#ibcon#flushed, iclass 6, count 0 2006.225.08:13:09.52#ibcon#about to write, iclass 6, count 0 2006.225.08:13:09.52#ibcon#wrote, iclass 6, count 0 2006.225.08:13:09.52#ibcon#about to read 3, iclass 6, count 0 2006.225.08:13:09.54#ibcon#read 3, iclass 6, count 0 2006.225.08:13:09.54#ibcon#about to read 4, iclass 6, count 0 2006.225.08:13:09.54#ibcon#read 4, iclass 6, count 0 2006.225.08:13:09.54#ibcon#about to read 5, iclass 6, count 0 2006.225.08:13:09.54#ibcon#read 5, iclass 6, count 0 2006.225.08:13:09.54#ibcon#about to read 6, iclass 6, count 0 2006.225.08:13:09.54#ibcon#read 6, iclass 6, count 0 2006.225.08:13:09.54#ibcon#end of sib2, iclass 6, count 0 2006.225.08:13:09.54#ibcon#*mode == 0, iclass 6, count 0 2006.225.08:13:09.54#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.08:13:09.54#ibcon#[25=USB\r\n] 2006.225.08:13:09.54#ibcon#*before write, iclass 6, count 0 2006.225.08:13:09.54#ibcon#enter sib2, iclass 6, count 0 2006.225.08:13:09.54#ibcon#flushed, iclass 6, count 0 2006.225.08:13:09.54#ibcon#about to write, iclass 6, count 0 2006.225.08:13:09.54#ibcon#wrote, iclass 6, count 0 2006.225.08:13:09.54#ibcon#about to read 3, iclass 6, count 0 2006.225.08:13:09.57#ibcon#read 3, iclass 6, count 0 2006.225.08:13:09.57#ibcon#about to read 4, iclass 6, count 0 2006.225.08:13:09.57#ibcon#read 4, iclass 6, count 0 2006.225.08:13:09.57#ibcon#about to read 5, iclass 6, count 0 2006.225.08:13:09.57#ibcon#read 5, iclass 6, count 0 2006.225.08:13:09.57#ibcon#about to read 6, iclass 6, count 0 2006.225.08:13:09.57#ibcon#read 6, iclass 6, count 0 2006.225.08:13:09.57#ibcon#end of sib2, iclass 6, count 0 2006.225.08:13:09.57#ibcon#*after write, iclass 6, count 0 2006.225.08:13:09.57#ibcon#*before return 0, iclass 6, count 0 2006.225.08:13:09.57#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:13:09.57#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:13:09.57#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.08:13:09.57#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.08:13:09.57$vc4f8/valo=6,772.99 2006.225.08:13:09.57#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.08:13:09.57#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.08:13:09.57#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:09.57#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:13:09.57#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:13:09.57#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:13:09.57#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:13:09.57#ibcon#first serial, iclass 10, count 0 2006.225.08:13:09.57#ibcon#enter sib2, iclass 10, count 0 2006.225.08:13:09.57#ibcon#flushed, iclass 10, count 0 2006.225.08:13:09.57#ibcon#about to write, iclass 10, count 0 2006.225.08:13:09.57#ibcon#wrote, iclass 10, count 0 2006.225.08:13:09.57#ibcon#about to read 3, iclass 10, count 0 2006.225.08:13:09.59#ibcon#read 3, iclass 10, count 0 2006.225.08:13:09.59#ibcon#about to read 4, iclass 10, count 0 2006.225.08:13:09.59#ibcon#read 4, iclass 10, count 0 2006.225.08:13:09.59#ibcon#about to read 5, iclass 10, count 0 2006.225.08:13:09.59#ibcon#read 5, iclass 10, count 0 2006.225.08:13:09.59#ibcon#about to read 6, iclass 10, count 0 2006.225.08:13:09.59#ibcon#read 6, iclass 10, count 0 2006.225.08:13:09.59#ibcon#end of sib2, iclass 10, count 0 2006.225.08:13:09.59#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:13:09.59#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:13:09.59#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:13:09.59#ibcon#*before write, iclass 10, count 0 2006.225.08:13:09.59#ibcon#enter sib2, iclass 10, count 0 2006.225.08:13:09.59#ibcon#flushed, iclass 10, count 0 2006.225.08:13:09.59#ibcon#about to write, iclass 10, count 0 2006.225.08:13:09.59#ibcon#wrote, iclass 10, count 0 2006.225.08:13:09.59#ibcon#about to read 3, iclass 10, count 0 2006.225.08:13:09.63#ibcon#read 3, iclass 10, count 0 2006.225.08:13:09.63#ibcon#about to read 4, iclass 10, count 0 2006.225.08:13:09.63#ibcon#read 4, iclass 10, count 0 2006.225.08:13:09.63#ibcon#about to read 5, iclass 10, count 0 2006.225.08:13:09.63#ibcon#read 5, iclass 10, count 0 2006.225.08:13:09.63#ibcon#about to read 6, iclass 10, count 0 2006.225.08:13:09.63#ibcon#read 6, iclass 10, count 0 2006.225.08:13:09.63#ibcon#end of sib2, iclass 10, count 0 2006.225.08:13:09.63#ibcon#*after write, iclass 10, count 0 2006.225.08:13:09.63#ibcon#*before return 0, iclass 10, count 0 2006.225.08:13:09.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:13:09.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:13:09.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:13:09.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:13:09.63$vc4f8/va=6,6 2006.225.08:13:09.63#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.08:13:09.63#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.08:13:09.63#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:09.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:13:09.69#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:13:09.69#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:13:09.69#ibcon#enter wrdev, iclass 12, count 2 2006.225.08:13:09.69#ibcon#first serial, iclass 12, count 2 2006.225.08:13:09.69#ibcon#enter sib2, iclass 12, count 2 2006.225.08:13:09.69#ibcon#flushed, iclass 12, count 2 2006.225.08:13:09.69#ibcon#about to write, iclass 12, count 2 2006.225.08:13:09.69#ibcon#wrote, iclass 12, count 2 2006.225.08:13:09.69#ibcon#about to read 3, iclass 12, count 2 2006.225.08:13:09.71#ibcon#read 3, iclass 12, count 2 2006.225.08:13:09.71#ibcon#about to read 4, iclass 12, count 2 2006.225.08:13:09.71#ibcon#read 4, iclass 12, count 2 2006.225.08:13:09.71#ibcon#about to read 5, iclass 12, count 2 2006.225.08:13:09.71#ibcon#read 5, iclass 12, count 2 2006.225.08:13:09.71#ibcon#about to read 6, iclass 12, count 2 2006.225.08:13:09.71#ibcon#read 6, iclass 12, count 2 2006.225.08:13:09.71#ibcon#end of sib2, iclass 12, count 2 2006.225.08:13:09.71#ibcon#*mode == 0, iclass 12, count 2 2006.225.08:13:09.71#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.08:13:09.71#ibcon#[25=AT06-06\r\n] 2006.225.08:13:09.71#ibcon#*before write, iclass 12, count 2 2006.225.08:13:09.71#ibcon#enter sib2, iclass 12, count 2 2006.225.08:13:09.71#ibcon#flushed, iclass 12, count 2 2006.225.08:13:09.71#ibcon#about to write, iclass 12, count 2 2006.225.08:13:09.71#ibcon#wrote, iclass 12, count 2 2006.225.08:13:09.71#ibcon#about to read 3, iclass 12, count 2 2006.225.08:13:09.74#ibcon#read 3, iclass 12, count 2 2006.225.08:13:09.74#ibcon#about to read 4, iclass 12, count 2 2006.225.08:13:09.74#ibcon#read 4, iclass 12, count 2 2006.225.08:13:09.74#ibcon#about to read 5, iclass 12, count 2 2006.225.08:13:09.74#ibcon#read 5, iclass 12, count 2 2006.225.08:13:09.74#ibcon#about to read 6, iclass 12, count 2 2006.225.08:13:09.74#ibcon#read 6, iclass 12, count 2 2006.225.08:13:09.74#ibcon#end of sib2, iclass 12, count 2 2006.225.08:13:09.74#ibcon#*after write, iclass 12, count 2 2006.225.08:13:09.74#ibcon#*before return 0, iclass 12, count 2 2006.225.08:13:09.74#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:13:09.74#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:13:09.74#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.08:13:09.74#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:09.74#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:13:09.86#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:13:09.86#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:13:09.86#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:13:09.86#ibcon#first serial, iclass 12, count 0 2006.225.08:13:09.86#ibcon#enter sib2, iclass 12, count 0 2006.225.08:13:09.86#ibcon#flushed, iclass 12, count 0 2006.225.08:13:09.86#ibcon#about to write, iclass 12, count 0 2006.225.08:13:09.86#ibcon#wrote, iclass 12, count 0 2006.225.08:13:09.86#ibcon#about to read 3, iclass 12, count 0 2006.225.08:13:09.88#ibcon#read 3, iclass 12, count 0 2006.225.08:13:09.88#ibcon#about to read 4, iclass 12, count 0 2006.225.08:13:09.88#ibcon#read 4, iclass 12, count 0 2006.225.08:13:09.88#ibcon#about to read 5, iclass 12, count 0 2006.225.08:13:09.88#ibcon#read 5, iclass 12, count 0 2006.225.08:13:09.88#ibcon#about to read 6, iclass 12, count 0 2006.225.08:13:09.88#ibcon#read 6, iclass 12, count 0 2006.225.08:13:09.88#ibcon#end of sib2, iclass 12, count 0 2006.225.08:13:09.88#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:13:09.88#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:13:09.88#ibcon#[25=USB\r\n] 2006.225.08:13:09.88#ibcon#*before write, iclass 12, count 0 2006.225.08:13:09.88#ibcon#enter sib2, iclass 12, count 0 2006.225.08:13:09.88#ibcon#flushed, iclass 12, count 0 2006.225.08:13:09.88#ibcon#about to write, iclass 12, count 0 2006.225.08:13:09.88#ibcon#wrote, iclass 12, count 0 2006.225.08:13:09.88#ibcon#about to read 3, iclass 12, count 0 2006.225.08:13:09.91#ibcon#read 3, iclass 12, count 0 2006.225.08:13:09.91#ibcon#about to read 4, iclass 12, count 0 2006.225.08:13:09.91#ibcon#read 4, iclass 12, count 0 2006.225.08:13:09.91#ibcon#about to read 5, iclass 12, count 0 2006.225.08:13:09.91#ibcon#read 5, iclass 12, count 0 2006.225.08:13:09.91#ibcon#about to read 6, iclass 12, count 0 2006.225.08:13:09.91#ibcon#read 6, iclass 12, count 0 2006.225.08:13:09.91#ibcon#end of sib2, iclass 12, count 0 2006.225.08:13:09.91#ibcon#*after write, iclass 12, count 0 2006.225.08:13:09.91#ibcon#*before return 0, iclass 12, count 0 2006.225.08:13:09.91#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:13:09.91#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:13:09.91#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:13:09.91#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:13:09.91$vc4f8/valo=7,832.99 2006.225.08:13:09.91#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.08:13:09.91#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.08:13:09.91#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:09.91#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:13:09.91#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:13:09.91#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:13:09.91#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:13:09.91#ibcon#first serial, iclass 14, count 0 2006.225.08:13:09.91#ibcon#enter sib2, iclass 14, count 0 2006.225.08:13:09.91#ibcon#flushed, iclass 14, count 0 2006.225.08:13:09.91#ibcon#about to write, iclass 14, count 0 2006.225.08:13:09.91#ibcon#wrote, iclass 14, count 0 2006.225.08:13:09.91#ibcon#about to read 3, iclass 14, count 0 2006.225.08:13:09.93#ibcon#read 3, iclass 14, count 0 2006.225.08:13:09.93#ibcon#about to read 4, iclass 14, count 0 2006.225.08:13:09.93#ibcon#read 4, iclass 14, count 0 2006.225.08:13:09.93#ibcon#about to read 5, iclass 14, count 0 2006.225.08:13:09.93#ibcon#read 5, iclass 14, count 0 2006.225.08:13:09.93#ibcon#about to read 6, iclass 14, count 0 2006.225.08:13:09.93#ibcon#read 6, iclass 14, count 0 2006.225.08:13:09.93#ibcon#end of sib2, iclass 14, count 0 2006.225.08:13:09.93#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:13:09.93#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:13:09.93#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:13:09.93#ibcon#*before write, iclass 14, count 0 2006.225.08:13:09.93#ibcon#enter sib2, iclass 14, count 0 2006.225.08:13:09.93#ibcon#flushed, iclass 14, count 0 2006.225.08:13:09.93#ibcon#about to write, iclass 14, count 0 2006.225.08:13:09.93#ibcon#wrote, iclass 14, count 0 2006.225.08:13:09.93#ibcon#about to read 3, iclass 14, count 0 2006.225.08:13:09.97#ibcon#read 3, iclass 14, count 0 2006.225.08:13:09.97#ibcon#about to read 4, iclass 14, count 0 2006.225.08:13:09.97#ibcon#read 4, iclass 14, count 0 2006.225.08:13:09.97#ibcon#about to read 5, iclass 14, count 0 2006.225.08:13:09.97#ibcon#read 5, iclass 14, count 0 2006.225.08:13:09.97#ibcon#about to read 6, iclass 14, count 0 2006.225.08:13:09.97#ibcon#read 6, iclass 14, count 0 2006.225.08:13:09.97#ibcon#end of sib2, iclass 14, count 0 2006.225.08:13:09.97#ibcon#*after write, iclass 14, count 0 2006.225.08:13:09.97#ibcon#*before return 0, iclass 14, count 0 2006.225.08:13:09.97#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:13:09.97#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:13:09.97#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:13:09.97#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:13:09.97$vc4f8/va=7,6 2006.225.08:13:09.97#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.08:13:09.97#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.08:13:09.97#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:09.97#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:13:10.03#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:13:10.03#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:13:10.03#ibcon#enter wrdev, iclass 16, count 2 2006.225.08:13:10.03#ibcon#first serial, iclass 16, count 2 2006.225.08:13:10.03#ibcon#enter sib2, iclass 16, count 2 2006.225.08:13:10.03#ibcon#flushed, iclass 16, count 2 2006.225.08:13:10.03#ibcon#about to write, iclass 16, count 2 2006.225.08:13:10.03#ibcon#wrote, iclass 16, count 2 2006.225.08:13:10.03#ibcon#about to read 3, iclass 16, count 2 2006.225.08:13:10.05#ibcon#read 3, iclass 16, count 2 2006.225.08:13:10.05#ibcon#about to read 4, iclass 16, count 2 2006.225.08:13:10.05#ibcon#read 4, iclass 16, count 2 2006.225.08:13:10.05#ibcon#about to read 5, iclass 16, count 2 2006.225.08:13:10.05#ibcon#read 5, iclass 16, count 2 2006.225.08:13:10.05#ibcon#about to read 6, iclass 16, count 2 2006.225.08:13:10.05#ibcon#read 6, iclass 16, count 2 2006.225.08:13:10.05#ibcon#end of sib2, iclass 16, count 2 2006.225.08:13:10.05#ibcon#*mode == 0, iclass 16, count 2 2006.225.08:13:10.05#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.08:13:10.05#ibcon#[25=AT07-06\r\n] 2006.225.08:13:10.05#ibcon#*before write, iclass 16, count 2 2006.225.08:13:10.05#ibcon#enter sib2, iclass 16, count 2 2006.225.08:13:10.05#ibcon#flushed, iclass 16, count 2 2006.225.08:13:10.05#ibcon#about to write, iclass 16, count 2 2006.225.08:13:10.05#ibcon#wrote, iclass 16, count 2 2006.225.08:13:10.05#ibcon#about to read 3, iclass 16, count 2 2006.225.08:13:10.08#ibcon#read 3, iclass 16, count 2 2006.225.08:13:10.08#ibcon#about to read 4, iclass 16, count 2 2006.225.08:13:10.08#ibcon#read 4, iclass 16, count 2 2006.225.08:13:10.08#ibcon#about to read 5, iclass 16, count 2 2006.225.08:13:10.08#ibcon#read 5, iclass 16, count 2 2006.225.08:13:10.08#ibcon#about to read 6, iclass 16, count 2 2006.225.08:13:10.08#ibcon#read 6, iclass 16, count 2 2006.225.08:13:10.08#ibcon#end of sib2, iclass 16, count 2 2006.225.08:13:10.08#ibcon#*after write, iclass 16, count 2 2006.225.08:13:10.08#ibcon#*before return 0, iclass 16, count 2 2006.225.08:13:10.08#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:13:10.08#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:13:10.08#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.08:13:10.08#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:10.08#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:13:10.20#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:13:10.20#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:13:10.20#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:13:10.20#ibcon#first serial, iclass 16, count 0 2006.225.08:13:10.20#ibcon#enter sib2, iclass 16, count 0 2006.225.08:13:10.20#ibcon#flushed, iclass 16, count 0 2006.225.08:13:10.20#ibcon#about to write, iclass 16, count 0 2006.225.08:13:10.20#ibcon#wrote, iclass 16, count 0 2006.225.08:13:10.20#ibcon#about to read 3, iclass 16, count 0 2006.225.08:13:10.22#ibcon#read 3, iclass 16, count 0 2006.225.08:13:10.22#ibcon#about to read 4, iclass 16, count 0 2006.225.08:13:10.22#ibcon#read 4, iclass 16, count 0 2006.225.08:13:10.22#ibcon#about to read 5, iclass 16, count 0 2006.225.08:13:10.22#ibcon#read 5, iclass 16, count 0 2006.225.08:13:10.22#ibcon#about to read 6, iclass 16, count 0 2006.225.08:13:10.22#ibcon#read 6, iclass 16, count 0 2006.225.08:13:10.22#ibcon#end of sib2, iclass 16, count 0 2006.225.08:13:10.22#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:13:10.22#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:13:10.22#ibcon#[25=USB\r\n] 2006.225.08:13:10.22#ibcon#*before write, iclass 16, count 0 2006.225.08:13:10.22#ibcon#enter sib2, iclass 16, count 0 2006.225.08:13:10.22#ibcon#flushed, iclass 16, count 0 2006.225.08:13:10.22#ibcon#about to write, iclass 16, count 0 2006.225.08:13:10.22#ibcon#wrote, iclass 16, count 0 2006.225.08:13:10.22#ibcon#about to read 3, iclass 16, count 0 2006.225.08:13:10.25#ibcon#read 3, iclass 16, count 0 2006.225.08:13:10.25#ibcon#about to read 4, iclass 16, count 0 2006.225.08:13:10.25#ibcon#read 4, iclass 16, count 0 2006.225.08:13:10.25#ibcon#about to read 5, iclass 16, count 0 2006.225.08:13:10.25#ibcon#read 5, iclass 16, count 0 2006.225.08:13:10.25#ibcon#about to read 6, iclass 16, count 0 2006.225.08:13:10.25#ibcon#read 6, iclass 16, count 0 2006.225.08:13:10.25#ibcon#end of sib2, iclass 16, count 0 2006.225.08:13:10.25#ibcon#*after write, iclass 16, count 0 2006.225.08:13:10.25#ibcon#*before return 0, iclass 16, count 0 2006.225.08:13:10.25#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:13:10.25#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:13:10.25#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:13:10.25#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:13:10.25$vc4f8/valo=8,852.99 2006.225.08:13:10.25#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.08:13:10.25#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.08:13:10.25#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:10.25#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:13:10.25#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:13:10.25#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:13:10.25#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:13:10.25#ibcon#first serial, iclass 18, count 0 2006.225.08:13:10.25#ibcon#enter sib2, iclass 18, count 0 2006.225.08:13:10.25#ibcon#flushed, iclass 18, count 0 2006.225.08:13:10.25#ibcon#about to write, iclass 18, count 0 2006.225.08:13:10.25#ibcon#wrote, iclass 18, count 0 2006.225.08:13:10.25#ibcon#about to read 3, iclass 18, count 0 2006.225.08:13:10.27#ibcon#read 3, iclass 18, count 0 2006.225.08:13:10.27#ibcon#about to read 4, iclass 18, count 0 2006.225.08:13:10.27#ibcon#read 4, iclass 18, count 0 2006.225.08:13:10.27#ibcon#about to read 5, iclass 18, count 0 2006.225.08:13:10.27#ibcon#read 5, iclass 18, count 0 2006.225.08:13:10.27#ibcon#about to read 6, iclass 18, count 0 2006.225.08:13:10.27#ibcon#read 6, iclass 18, count 0 2006.225.08:13:10.27#ibcon#end of sib2, iclass 18, count 0 2006.225.08:13:10.27#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:13:10.27#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:13:10.27#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:13:10.27#ibcon#*before write, iclass 18, count 0 2006.225.08:13:10.27#ibcon#enter sib2, iclass 18, count 0 2006.225.08:13:10.27#ibcon#flushed, iclass 18, count 0 2006.225.08:13:10.27#ibcon#about to write, iclass 18, count 0 2006.225.08:13:10.27#ibcon#wrote, iclass 18, count 0 2006.225.08:13:10.27#ibcon#about to read 3, iclass 18, count 0 2006.225.08:13:10.31#ibcon#read 3, iclass 18, count 0 2006.225.08:13:10.31#ibcon#about to read 4, iclass 18, count 0 2006.225.08:13:10.31#ibcon#read 4, iclass 18, count 0 2006.225.08:13:10.31#ibcon#about to read 5, iclass 18, count 0 2006.225.08:13:10.31#ibcon#read 5, iclass 18, count 0 2006.225.08:13:10.31#ibcon#about to read 6, iclass 18, count 0 2006.225.08:13:10.31#ibcon#read 6, iclass 18, count 0 2006.225.08:13:10.31#ibcon#end of sib2, iclass 18, count 0 2006.225.08:13:10.31#ibcon#*after write, iclass 18, count 0 2006.225.08:13:10.31#ibcon#*before return 0, iclass 18, count 0 2006.225.08:13:10.31#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:13:10.31#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:13:10.31#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:13:10.31#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:13:10.31$vc4f8/va=8,7 2006.225.08:13:10.31#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.08:13:10.31#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.08:13:10.31#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:10.31#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:13:10.37#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:13:10.37#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:13:10.37#ibcon#enter wrdev, iclass 20, count 2 2006.225.08:13:10.37#ibcon#first serial, iclass 20, count 2 2006.225.08:13:10.37#ibcon#enter sib2, iclass 20, count 2 2006.225.08:13:10.37#ibcon#flushed, iclass 20, count 2 2006.225.08:13:10.37#ibcon#about to write, iclass 20, count 2 2006.225.08:13:10.37#ibcon#wrote, iclass 20, count 2 2006.225.08:13:10.37#ibcon#about to read 3, iclass 20, count 2 2006.225.08:13:10.39#ibcon#read 3, iclass 20, count 2 2006.225.08:13:10.39#ibcon#about to read 4, iclass 20, count 2 2006.225.08:13:10.39#ibcon#read 4, iclass 20, count 2 2006.225.08:13:10.39#ibcon#about to read 5, iclass 20, count 2 2006.225.08:13:10.39#ibcon#read 5, iclass 20, count 2 2006.225.08:13:10.39#ibcon#about to read 6, iclass 20, count 2 2006.225.08:13:10.39#ibcon#read 6, iclass 20, count 2 2006.225.08:13:10.39#ibcon#end of sib2, iclass 20, count 2 2006.225.08:13:10.39#ibcon#*mode == 0, iclass 20, count 2 2006.225.08:13:10.39#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.08:13:10.39#ibcon#[25=AT08-07\r\n] 2006.225.08:13:10.39#ibcon#*before write, iclass 20, count 2 2006.225.08:13:10.39#ibcon#enter sib2, iclass 20, count 2 2006.225.08:13:10.39#ibcon#flushed, iclass 20, count 2 2006.225.08:13:10.39#ibcon#about to write, iclass 20, count 2 2006.225.08:13:10.39#ibcon#wrote, iclass 20, count 2 2006.225.08:13:10.39#ibcon#about to read 3, iclass 20, count 2 2006.225.08:13:10.42#ibcon#read 3, iclass 20, count 2 2006.225.08:13:10.42#ibcon#about to read 4, iclass 20, count 2 2006.225.08:13:10.42#ibcon#read 4, iclass 20, count 2 2006.225.08:13:10.42#ibcon#about to read 5, iclass 20, count 2 2006.225.08:13:10.42#ibcon#read 5, iclass 20, count 2 2006.225.08:13:10.42#ibcon#about to read 6, iclass 20, count 2 2006.225.08:13:10.42#ibcon#read 6, iclass 20, count 2 2006.225.08:13:10.42#ibcon#end of sib2, iclass 20, count 2 2006.225.08:13:10.42#ibcon#*after write, iclass 20, count 2 2006.225.08:13:10.42#ibcon#*before return 0, iclass 20, count 2 2006.225.08:13:10.42#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:13:10.42#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:13:10.42#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.08:13:10.42#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:10.42#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:13:10.54#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:13:10.54#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:13:10.54#ibcon#enter wrdev, iclass 20, count 0 2006.225.08:13:10.54#ibcon#first serial, iclass 20, count 0 2006.225.08:13:10.54#ibcon#enter sib2, iclass 20, count 0 2006.225.08:13:10.54#ibcon#flushed, iclass 20, count 0 2006.225.08:13:10.54#ibcon#about to write, iclass 20, count 0 2006.225.08:13:10.54#ibcon#wrote, iclass 20, count 0 2006.225.08:13:10.54#ibcon#about to read 3, iclass 20, count 0 2006.225.08:13:10.56#ibcon#read 3, iclass 20, count 0 2006.225.08:13:10.56#ibcon#about to read 4, iclass 20, count 0 2006.225.08:13:10.56#ibcon#read 4, iclass 20, count 0 2006.225.08:13:10.56#ibcon#about to read 5, iclass 20, count 0 2006.225.08:13:10.56#ibcon#read 5, iclass 20, count 0 2006.225.08:13:10.56#ibcon#about to read 6, iclass 20, count 0 2006.225.08:13:10.56#ibcon#read 6, iclass 20, count 0 2006.225.08:13:10.56#ibcon#end of sib2, iclass 20, count 0 2006.225.08:13:10.56#ibcon#*mode == 0, iclass 20, count 0 2006.225.08:13:10.56#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.08:13:10.56#ibcon#[25=USB\r\n] 2006.225.08:13:10.56#ibcon#*before write, iclass 20, count 0 2006.225.08:13:10.56#ibcon#enter sib2, iclass 20, count 0 2006.225.08:13:10.56#ibcon#flushed, iclass 20, count 0 2006.225.08:13:10.56#ibcon#about to write, iclass 20, count 0 2006.225.08:13:10.56#ibcon#wrote, iclass 20, count 0 2006.225.08:13:10.56#ibcon#about to read 3, iclass 20, count 0 2006.225.08:13:10.59#ibcon#read 3, iclass 20, count 0 2006.225.08:13:10.59#ibcon#about to read 4, iclass 20, count 0 2006.225.08:13:10.59#ibcon#read 4, iclass 20, count 0 2006.225.08:13:10.59#ibcon#about to read 5, iclass 20, count 0 2006.225.08:13:10.59#ibcon#read 5, iclass 20, count 0 2006.225.08:13:10.59#ibcon#about to read 6, iclass 20, count 0 2006.225.08:13:10.59#ibcon#read 6, iclass 20, count 0 2006.225.08:13:10.59#ibcon#end of sib2, iclass 20, count 0 2006.225.08:13:10.59#ibcon#*after write, iclass 20, count 0 2006.225.08:13:10.59#ibcon#*before return 0, iclass 20, count 0 2006.225.08:13:10.59#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:13:10.59#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:13:10.59#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.08:13:10.59#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.08:13:10.59$vc4f8/vblo=1,632.99 2006.225.08:13:10.59#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.08:13:10.59#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.08:13:10.59#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:10.59#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:13:10.59#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:13:10.59#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:13:10.59#ibcon#enter wrdev, iclass 22, count 0 2006.225.08:13:10.59#ibcon#first serial, iclass 22, count 0 2006.225.08:13:10.59#ibcon#enter sib2, iclass 22, count 0 2006.225.08:13:10.59#ibcon#flushed, iclass 22, count 0 2006.225.08:13:10.59#ibcon#about to write, iclass 22, count 0 2006.225.08:13:10.59#ibcon#wrote, iclass 22, count 0 2006.225.08:13:10.59#ibcon#about to read 3, iclass 22, count 0 2006.225.08:13:10.61#ibcon#read 3, iclass 22, count 0 2006.225.08:13:10.61#ibcon#about to read 4, iclass 22, count 0 2006.225.08:13:10.61#ibcon#read 4, iclass 22, count 0 2006.225.08:13:10.61#ibcon#about to read 5, iclass 22, count 0 2006.225.08:13:10.61#ibcon#read 5, iclass 22, count 0 2006.225.08:13:10.61#ibcon#about to read 6, iclass 22, count 0 2006.225.08:13:10.61#ibcon#read 6, iclass 22, count 0 2006.225.08:13:10.61#ibcon#end of sib2, iclass 22, count 0 2006.225.08:13:10.61#ibcon#*mode == 0, iclass 22, count 0 2006.225.08:13:10.61#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.08:13:10.61#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:13:10.61#ibcon#*before write, iclass 22, count 0 2006.225.08:13:10.61#ibcon#enter sib2, iclass 22, count 0 2006.225.08:13:10.61#ibcon#flushed, iclass 22, count 0 2006.225.08:13:10.61#ibcon#about to write, iclass 22, count 0 2006.225.08:13:10.61#ibcon#wrote, iclass 22, count 0 2006.225.08:13:10.61#ibcon#about to read 3, iclass 22, count 0 2006.225.08:13:10.65#ibcon#read 3, iclass 22, count 0 2006.225.08:13:10.65#ibcon#about to read 4, iclass 22, count 0 2006.225.08:13:10.65#ibcon#read 4, iclass 22, count 0 2006.225.08:13:10.65#ibcon#about to read 5, iclass 22, count 0 2006.225.08:13:10.65#ibcon#read 5, iclass 22, count 0 2006.225.08:13:10.65#ibcon#about to read 6, iclass 22, count 0 2006.225.08:13:10.65#ibcon#read 6, iclass 22, count 0 2006.225.08:13:10.65#ibcon#end of sib2, iclass 22, count 0 2006.225.08:13:10.65#ibcon#*after write, iclass 22, count 0 2006.225.08:13:10.65#ibcon#*before return 0, iclass 22, count 0 2006.225.08:13:10.65#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:13:10.65#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:13:10.65#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.08:13:10.65#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.08:13:10.65$vc4f8/vb=1,4 2006.225.08:13:10.65#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.08:13:10.65#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.08:13:10.65#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:10.65#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:13:10.65#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:13:10.65#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:13:10.65#ibcon#enter wrdev, iclass 24, count 2 2006.225.08:13:10.65#ibcon#first serial, iclass 24, count 2 2006.225.08:13:10.65#ibcon#enter sib2, iclass 24, count 2 2006.225.08:13:10.65#ibcon#flushed, iclass 24, count 2 2006.225.08:13:10.65#ibcon#about to write, iclass 24, count 2 2006.225.08:13:10.65#ibcon#wrote, iclass 24, count 2 2006.225.08:13:10.65#ibcon#about to read 3, iclass 24, count 2 2006.225.08:13:10.67#ibcon#read 3, iclass 24, count 2 2006.225.08:13:10.67#ibcon#about to read 4, iclass 24, count 2 2006.225.08:13:10.67#ibcon#read 4, iclass 24, count 2 2006.225.08:13:10.67#ibcon#about to read 5, iclass 24, count 2 2006.225.08:13:10.67#ibcon#read 5, iclass 24, count 2 2006.225.08:13:10.67#ibcon#about to read 6, iclass 24, count 2 2006.225.08:13:10.67#ibcon#read 6, iclass 24, count 2 2006.225.08:13:10.67#ibcon#end of sib2, iclass 24, count 2 2006.225.08:13:10.67#ibcon#*mode == 0, iclass 24, count 2 2006.225.08:13:10.67#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.08:13:10.67#ibcon#[27=AT01-04\r\n] 2006.225.08:13:10.67#ibcon#*before write, iclass 24, count 2 2006.225.08:13:10.67#ibcon#enter sib2, iclass 24, count 2 2006.225.08:13:10.67#ibcon#flushed, iclass 24, count 2 2006.225.08:13:10.67#ibcon#about to write, iclass 24, count 2 2006.225.08:13:10.67#ibcon#wrote, iclass 24, count 2 2006.225.08:13:10.67#ibcon#about to read 3, iclass 24, count 2 2006.225.08:13:10.70#ibcon#read 3, iclass 24, count 2 2006.225.08:13:10.70#ibcon#about to read 4, iclass 24, count 2 2006.225.08:13:10.70#ibcon#read 4, iclass 24, count 2 2006.225.08:13:10.70#ibcon#about to read 5, iclass 24, count 2 2006.225.08:13:10.70#ibcon#read 5, iclass 24, count 2 2006.225.08:13:10.70#ibcon#about to read 6, iclass 24, count 2 2006.225.08:13:10.70#ibcon#read 6, iclass 24, count 2 2006.225.08:13:10.70#ibcon#end of sib2, iclass 24, count 2 2006.225.08:13:10.70#ibcon#*after write, iclass 24, count 2 2006.225.08:13:10.70#ibcon#*before return 0, iclass 24, count 2 2006.225.08:13:10.70#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:13:10.70#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:13:10.70#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.08:13:10.70#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:10.70#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:13:10.82#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:13:10.82#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:13:10.82#ibcon#enter wrdev, iclass 24, count 0 2006.225.08:13:10.82#ibcon#first serial, iclass 24, count 0 2006.225.08:13:10.82#ibcon#enter sib2, iclass 24, count 0 2006.225.08:13:10.82#ibcon#flushed, iclass 24, count 0 2006.225.08:13:10.82#ibcon#about to write, iclass 24, count 0 2006.225.08:13:10.82#ibcon#wrote, iclass 24, count 0 2006.225.08:13:10.82#ibcon#about to read 3, iclass 24, count 0 2006.225.08:13:10.84#ibcon#read 3, iclass 24, count 0 2006.225.08:13:10.84#ibcon#about to read 4, iclass 24, count 0 2006.225.08:13:10.84#ibcon#read 4, iclass 24, count 0 2006.225.08:13:10.84#ibcon#about to read 5, iclass 24, count 0 2006.225.08:13:10.84#ibcon#read 5, iclass 24, count 0 2006.225.08:13:10.84#ibcon#about to read 6, iclass 24, count 0 2006.225.08:13:10.84#ibcon#read 6, iclass 24, count 0 2006.225.08:13:10.84#ibcon#end of sib2, iclass 24, count 0 2006.225.08:13:10.84#ibcon#*mode == 0, iclass 24, count 0 2006.225.08:13:10.84#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.08:13:10.84#ibcon#[27=USB\r\n] 2006.225.08:13:10.84#ibcon#*before write, iclass 24, count 0 2006.225.08:13:10.84#ibcon#enter sib2, iclass 24, count 0 2006.225.08:13:10.84#ibcon#flushed, iclass 24, count 0 2006.225.08:13:10.84#ibcon#about to write, iclass 24, count 0 2006.225.08:13:10.84#ibcon#wrote, iclass 24, count 0 2006.225.08:13:10.84#ibcon#about to read 3, iclass 24, count 0 2006.225.08:13:10.87#ibcon#read 3, iclass 24, count 0 2006.225.08:13:10.87#ibcon#about to read 4, iclass 24, count 0 2006.225.08:13:10.87#ibcon#read 4, iclass 24, count 0 2006.225.08:13:10.87#ibcon#about to read 5, iclass 24, count 0 2006.225.08:13:10.87#ibcon#read 5, iclass 24, count 0 2006.225.08:13:10.87#ibcon#about to read 6, iclass 24, count 0 2006.225.08:13:10.87#ibcon#read 6, iclass 24, count 0 2006.225.08:13:10.87#ibcon#end of sib2, iclass 24, count 0 2006.225.08:13:10.87#ibcon#*after write, iclass 24, count 0 2006.225.08:13:10.87#ibcon#*before return 0, iclass 24, count 0 2006.225.08:13:10.87#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:13:10.87#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:13:10.87#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.08:13:10.87#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.08:13:10.87$vc4f8/vblo=2,640.99 2006.225.08:13:10.87#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.08:13:10.87#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.08:13:10.87#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:10.87#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:13:10.87#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:13:10.87#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:13:10.87#ibcon#enter wrdev, iclass 26, count 0 2006.225.08:13:10.87#ibcon#first serial, iclass 26, count 0 2006.225.08:13:10.87#ibcon#enter sib2, iclass 26, count 0 2006.225.08:13:10.87#ibcon#flushed, iclass 26, count 0 2006.225.08:13:10.87#ibcon#about to write, iclass 26, count 0 2006.225.08:13:10.87#ibcon#wrote, iclass 26, count 0 2006.225.08:13:10.87#ibcon#about to read 3, iclass 26, count 0 2006.225.08:13:10.89#ibcon#read 3, iclass 26, count 0 2006.225.08:13:10.89#ibcon#about to read 4, iclass 26, count 0 2006.225.08:13:10.89#ibcon#read 4, iclass 26, count 0 2006.225.08:13:10.89#ibcon#about to read 5, iclass 26, count 0 2006.225.08:13:10.89#ibcon#read 5, iclass 26, count 0 2006.225.08:13:10.89#ibcon#about to read 6, iclass 26, count 0 2006.225.08:13:10.89#ibcon#read 6, iclass 26, count 0 2006.225.08:13:10.89#ibcon#end of sib2, iclass 26, count 0 2006.225.08:13:10.89#ibcon#*mode == 0, iclass 26, count 0 2006.225.08:13:10.89#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.08:13:10.89#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:13:10.89#ibcon#*before write, iclass 26, count 0 2006.225.08:13:10.89#ibcon#enter sib2, iclass 26, count 0 2006.225.08:13:10.89#ibcon#flushed, iclass 26, count 0 2006.225.08:13:10.89#ibcon#about to write, iclass 26, count 0 2006.225.08:13:10.89#ibcon#wrote, iclass 26, count 0 2006.225.08:13:10.89#ibcon#about to read 3, iclass 26, count 0 2006.225.08:13:10.93#ibcon#read 3, iclass 26, count 0 2006.225.08:13:10.93#ibcon#about to read 4, iclass 26, count 0 2006.225.08:13:10.93#ibcon#read 4, iclass 26, count 0 2006.225.08:13:10.93#ibcon#about to read 5, iclass 26, count 0 2006.225.08:13:10.93#ibcon#read 5, iclass 26, count 0 2006.225.08:13:10.93#ibcon#about to read 6, iclass 26, count 0 2006.225.08:13:10.93#ibcon#read 6, iclass 26, count 0 2006.225.08:13:10.93#ibcon#end of sib2, iclass 26, count 0 2006.225.08:13:10.93#ibcon#*after write, iclass 26, count 0 2006.225.08:13:10.93#ibcon#*before return 0, iclass 26, count 0 2006.225.08:13:10.93#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:13:10.93#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:13:10.93#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.08:13:10.93#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.08:13:10.93$vc4f8/vb=2,4 2006.225.08:13:10.93#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.08:13:10.93#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.08:13:10.93#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:10.93#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:13:10.99#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:13:10.99#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:13:10.99#ibcon#enter wrdev, iclass 28, count 2 2006.225.08:13:10.99#ibcon#first serial, iclass 28, count 2 2006.225.08:13:10.99#ibcon#enter sib2, iclass 28, count 2 2006.225.08:13:10.99#ibcon#flushed, iclass 28, count 2 2006.225.08:13:10.99#ibcon#about to write, iclass 28, count 2 2006.225.08:13:10.99#ibcon#wrote, iclass 28, count 2 2006.225.08:13:10.99#ibcon#about to read 3, iclass 28, count 2 2006.225.08:13:11.01#ibcon#read 3, iclass 28, count 2 2006.225.08:13:11.01#ibcon#about to read 4, iclass 28, count 2 2006.225.08:13:11.01#ibcon#read 4, iclass 28, count 2 2006.225.08:13:11.01#ibcon#about to read 5, iclass 28, count 2 2006.225.08:13:11.01#ibcon#read 5, iclass 28, count 2 2006.225.08:13:11.01#ibcon#about to read 6, iclass 28, count 2 2006.225.08:13:11.01#ibcon#read 6, iclass 28, count 2 2006.225.08:13:11.01#ibcon#end of sib2, iclass 28, count 2 2006.225.08:13:11.01#ibcon#*mode == 0, iclass 28, count 2 2006.225.08:13:11.01#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.08:13:11.01#ibcon#[27=AT02-04\r\n] 2006.225.08:13:11.01#ibcon#*before write, iclass 28, count 2 2006.225.08:13:11.01#ibcon#enter sib2, iclass 28, count 2 2006.225.08:13:11.01#ibcon#flushed, iclass 28, count 2 2006.225.08:13:11.01#ibcon#about to write, iclass 28, count 2 2006.225.08:13:11.01#ibcon#wrote, iclass 28, count 2 2006.225.08:13:11.01#ibcon#about to read 3, iclass 28, count 2 2006.225.08:13:11.04#ibcon#read 3, iclass 28, count 2 2006.225.08:13:11.04#ibcon#about to read 4, iclass 28, count 2 2006.225.08:13:11.04#ibcon#read 4, iclass 28, count 2 2006.225.08:13:11.04#ibcon#about to read 5, iclass 28, count 2 2006.225.08:13:11.04#ibcon#read 5, iclass 28, count 2 2006.225.08:13:11.04#ibcon#about to read 6, iclass 28, count 2 2006.225.08:13:11.04#ibcon#read 6, iclass 28, count 2 2006.225.08:13:11.04#ibcon#end of sib2, iclass 28, count 2 2006.225.08:13:11.04#ibcon#*after write, iclass 28, count 2 2006.225.08:13:11.04#ibcon#*before return 0, iclass 28, count 2 2006.225.08:13:11.04#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:13:11.04#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:13:11.04#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.08:13:11.04#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:11.04#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:13:11.16#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:13:11.16#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:13:11.16#ibcon#enter wrdev, iclass 28, count 0 2006.225.08:13:11.16#ibcon#first serial, iclass 28, count 0 2006.225.08:13:11.16#ibcon#enter sib2, iclass 28, count 0 2006.225.08:13:11.16#ibcon#flushed, iclass 28, count 0 2006.225.08:13:11.16#ibcon#about to write, iclass 28, count 0 2006.225.08:13:11.16#ibcon#wrote, iclass 28, count 0 2006.225.08:13:11.16#ibcon#about to read 3, iclass 28, count 0 2006.225.08:13:11.18#ibcon#read 3, iclass 28, count 0 2006.225.08:13:11.18#ibcon#about to read 4, iclass 28, count 0 2006.225.08:13:11.18#ibcon#read 4, iclass 28, count 0 2006.225.08:13:11.18#ibcon#about to read 5, iclass 28, count 0 2006.225.08:13:11.18#ibcon#read 5, iclass 28, count 0 2006.225.08:13:11.18#ibcon#about to read 6, iclass 28, count 0 2006.225.08:13:11.18#ibcon#read 6, iclass 28, count 0 2006.225.08:13:11.18#ibcon#end of sib2, iclass 28, count 0 2006.225.08:13:11.18#ibcon#*mode == 0, iclass 28, count 0 2006.225.08:13:11.18#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.08:13:11.18#ibcon#[27=USB\r\n] 2006.225.08:13:11.18#ibcon#*before write, iclass 28, count 0 2006.225.08:13:11.18#ibcon#enter sib2, iclass 28, count 0 2006.225.08:13:11.18#ibcon#flushed, iclass 28, count 0 2006.225.08:13:11.18#ibcon#about to write, iclass 28, count 0 2006.225.08:13:11.18#ibcon#wrote, iclass 28, count 0 2006.225.08:13:11.18#ibcon#about to read 3, iclass 28, count 0 2006.225.08:13:11.21#ibcon#read 3, iclass 28, count 0 2006.225.08:13:11.21#ibcon#about to read 4, iclass 28, count 0 2006.225.08:13:11.21#ibcon#read 4, iclass 28, count 0 2006.225.08:13:11.21#ibcon#about to read 5, iclass 28, count 0 2006.225.08:13:11.21#ibcon#read 5, iclass 28, count 0 2006.225.08:13:11.21#ibcon#about to read 6, iclass 28, count 0 2006.225.08:13:11.21#ibcon#read 6, iclass 28, count 0 2006.225.08:13:11.21#ibcon#end of sib2, iclass 28, count 0 2006.225.08:13:11.21#ibcon#*after write, iclass 28, count 0 2006.225.08:13:11.21#ibcon#*before return 0, iclass 28, count 0 2006.225.08:13:11.21#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:13:11.21#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:13:11.21#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.08:13:11.21#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.08:13:11.21$vc4f8/vblo=3,656.99 2006.225.08:13:11.21#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.08:13:11.21#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.08:13:11.21#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:11.21#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:13:11.21#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:13:11.21#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:13:11.21#ibcon#enter wrdev, iclass 30, count 0 2006.225.08:13:11.21#ibcon#first serial, iclass 30, count 0 2006.225.08:13:11.21#ibcon#enter sib2, iclass 30, count 0 2006.225.08:13:11.21#ibcon#flushed, iclass 30, count 0 2006.225.08:13:11.21#ibcon#about to write, iclass 30, count 0 2006.225.08:13:11.21#ibcon#wrote, iclass 30, count 0 2006.225.08:13:11.21#ibcon#about to read 3, iclass 30, count 0 2006.225.08:13:11.23#ibcon#read 3, iclass 30, count 0 2006.225.08:13:11.23#ibcon#about to read 4, iclass 30, count 0 2006.225.08:13:11.23#ibcon#read 4, iclass 30, count 0 2006.225.08:13:11.23#ibcon#about to read 5, iclass 30, count 0 2006.225.08:13:11.23#ibcon#read 5, iclass 30, count 0 2006.225.08:13:11.23#ibcon#about to read 6, iclass 30, count 0 2006.225.08:13:11.23#ibcon#read 6, iclass 30, count 0 2006.225.08:13:11.23#ibcon#end of sib2, iclass 30, count 0 2006.225.08:13:11.23#ibcon#*mode == 0, iclass 30, count 0 2006.225.08:13:11.23#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.08:13:11.23#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:13:11.23#ibcon#*before write, iclass 30, count 0 2006.225.08:13:11.23#ibcon#enter sib2, iclass 30, count 0 2006.225.08:13:11.23#ibcon#flushed, iclass 30, count 0 2006.225.08:13:11.23#ibcon#about to write, iclass 30, count 0 2006.225.08:13:11.23#ibcon#wrote, iclass 30, count 0 2006.225.08:13:11.23#ibcon#about to read 3, iclass 30, count 0 2006.225.08:13:11.27#ibcon#read 3, iclass 30, count 0 2006.225.08:13:11.27#ibcon#about to read 4, iclass 30, count 0 2006.225.08:13:11.27#ibcon#read 4, iclass 30, count 0 2006.225.08:13:11.27#ibcon#about to read 5, iclass 30, count 0 2006.225.08:13:11.27#ibcon#read 5, iclass 30, count 0 2006.225.08:13:11.27#ibcon#about to read 6, iclass 30, count 0 2006.225.08:13:11.27#ibcon#read 6, iclass 30, count 0 2006.225.08:13:11.27#ibcon#end of sib2, iclass 30, count 0 2006.225.08:13:11.27#ibcon#*after write, iclass 30, count 0 2006.225.08:13:11.27#ibcon#*before return 0, iclass 30, count 0 2006.225.08:13:11.27#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:13:11.27#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:13:11.27#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.08:13:11.27#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.08:13:11.27$vc4f8/vb=3,4 2006.225.08:13:11.27#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.225.08:13:11.27#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.225.08:13:11.27#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:11.27#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:13:11.33#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:13:11.33#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:13:11.33#ibcon#enter wrdev, iclass 32, count 2 2006.225.08:13:11.33#ibcon#first serial, iclass 32, count 2 2006.225.08:13:11.33#ibcon#enter sib2, iclass 32, count 2 2006.225.08:13:11.33#ibcon#flushed, iclass 32, count 2 2006.225.08:13:11.33#ibcon#about to write, iclass 32, count 2 2006.225.08:13:11.33#ibcon#wrote, iclass 32, count 2 2006.225.08:13:11.33#ibcon#about to read 3, iclass 32, count 2 2006.225.08:13:11.35#ibcon#read 3, iclass 32, count 2 2006.225.08:13:11.35#ibcon#about to read 4, iclass 32, count 2 2006.225.08:13:11.35#ibcon#read 4, iclass 32, count 2 2006.225.08:13:11.35#ibcon#about to read 5, iclass 32, count 2 2006.225.08:13:11.35#ibcon#read 5, iclass 32, count 2 2006.225.08:13:11.35#ibcon#about to read 6, iclass 32, count 2 2006.225.08:13:11.35#ibcon#read 6, iclass 32, count 2 2006.225.08:13:11.35#ibcon#end of sib2, iclass 32, count 2 2006.225.08:13:11.35#ibcon#*mode == 0, iclass 32, count 2 2006.225.08:13:11.35#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.225.08:13:11.35#ibcon#[27=AT03-04\r\n] 2006.225.08:13:11.35#ibcon#*before write, iclass 32, count 2 2006.225.08:13:11.35#ibcon#enter sib2, iclass 32, count 2 2006.225.08:13:11.35#ibcon#flushed, iclass 32, count 2 2006.225.08:13:11.35#ibcon#about to write, iclass 32, count 2 2006.225.08:13:11.35#ibcon#wrote, iclass 32, count 2 2006.225.08:13:11.35#ibcon#about to read 3, iclass 32, count 2 2006.225.08:13:11.38#ibcon#read 3, iclass 32, count 2 2006.225.08:13:11.38#ibcon#about to read 4, iclass 32, count 2 2006.225.08:13:11.38#ibcon#read 4, iclass 32, count 2 2006.225.08:13:11.38#ibcon#about to read 5, iclass 32, count 2 2006.225.08:13:11.38#ibcon#read 5, iclass 32, count 2 2006.225.08:13:11.38#ibcon#about to read 6, iclass 32, count 2 2006.225.08:13:11.38#ibcon#read 6, iclass 32, count 2 2006.225.08:13:11.38#ibcon#end of sib2, iclass 32, count 2 2006.225.08:13:11.38#ibcon#*after write, iclass 32, count 2 2006.225.08:13:11.38#ibcon#*before return 0, iclass 32, count 2 2006.225.08:13:11.38#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:13:11.38#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:13:11.38#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.225.08:13:11.38#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:11.38#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:13:11.50#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:13:11.50#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:13:11.50#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:13:11.50#ibcon#first serial, iclass 32, count 0 2006.225.08:13:11.50#ibcon#enter sib2, iclass 32, count 0 2006.225.08:13:11.50#ibcon#flushed, iclass 32, count 0 2006.225.08:13:11.50#ibcon#about to write, iclass 32, count 0 2006.225.08:13:11.50#ibcon#wrote, iclass 32, count 0 2006.225.08:13:11.50#ibcon#about to read 3, iclass 32, count 0 2006.225.08:13:11.52#ibcon#read 3, iclass 32, count 0 2006.225.08:13:11.52#ibcon#about to read 4, iclass 32, count 0 2006.225.08:13:11.52#ibcon#read 4, iclass 32, count 0 2006.225.08:13:11.52#ibcon#about to read 5, iclass 32, count 0 2006.225.08:13:11.52#ibcon#read 5, iclass 32, count 0 2006.225.08:13:11.52#ibcon#about to read 6, iclass 32, count 0 2006.225.08:13:11.52#ibcon#read 6, iclass 32, count 0 2006.225.08:13:11.52#ibcon#end of sib2, iclass 32, count 0 2006.225.08:13:11.52#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:13:11.52#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:13:11.52#ibcon#[27=USB\r\n] 2006.225.08:13:11.52#ibcon#*before write, iclass 32, count 0 2006.225.08:13:11.52#ibcon#enter sib2, iclass 32, count 0 2006.225.08:13:11.52#ibcon#flushed, iclass 32, count 0 2006.225.08:13:11.52#ibcon#about to write, iclass 32, count 0 2006.225.08:13:11.52#ibcon#wrote, iclass 32, count 0 2006.225.08:13:11.52#ibcon#about to read 3, iclass 32, count 0 2006.225.08:13:11.55#ibcon#read 3, iclass 32, count 0 2006.225.08:13:11.55#ibcon#about to read 4, iclass 32, count 0 2006.225.08:13:11.55#ibcon#read 4, iclass 32, count 0 2006.225.08:13:11.55#ibcon#about to read 5, iclass 32, count 0 2006.225.08:13:11.55#ibcon#read 5, iclass 32, count 0 2006.225.08:13:11.55#ibcon#about to read 6, iclass 32, count 0 2006.225.08:13:11.55#ibcon#read 6, iclass 32, count 0 2006.225.08:13:11.55#ibcon#end of sib2, iclass 32, count 0 2006.225.08:13:11.55#ibcon#*after write, iclass 32, count 0 2006.225.08:13:11.55#ibcon#*before return 0, iclass 32, count 0 2006.225.08:13:11.55#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:13:11.55#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:13:11.55#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:13:11.55#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:13:11.55$vc4f8/vblo=4,712.99 2006.225.08:13:11.55#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.08:13:11.55#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.08:13:11.55#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:11.55#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:13:11.55#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:13:11.55#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:13:11.55#ibcon#enter wrdev, iclass 34, count 0 2006.225.08:13:11.55#ibcon#first serial, iclass 34, count 0 2006.225.08:13:11.55#ibcon#enter sib2, iclass 34, count 0 2006.225.08:13:11.55#ibcon#flushed, iclass 34, count 0 2006.225.08:13:11.55#ibcon#about to write, iclass 34, count 0 2006.225.08:13:11.55#ibcon#wrote, iclass 34, count 0 2006.225.08:13:11.55#ibcon#about to read 3, iclass 34, count 0 2006.225.08:13:11.57#ibcon#read 3, iclass 34, count 0 2006.225.08:13:11.57#ibcon#about to read 4, iclass 34, count 0 2006.225.08:13:11.57#ibcon#read 4, iclass 34, count 0 2006.225.08:13:11.57#ibcon#about to read 5, iclass 34, count 0 2006.225.08:13:11.57#ibcon#read 5, iclass 34, count 0 2006.225.08:13:11.57#ibcon#about to read 6, iclass 34, count 0 2006.225.08:13:11.57#ibcon#read 6, iclass 34, count 0 2006.225.08:13:11.57#ibcon#end of sib2, iclass 34, count 0 2006.225.08:13:11.57#ibcon#*mode == 0, iclass 34, count 0 2006.225.08:13:11.57#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.08:13:11.57#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:13:11.57#ibcon#*before write, iclass 34, count 0 2006.225.08:13:11.57#ibcon#enter sib2, iclass 34, count 0 2006.225.08:13:11.57#ibcon#flushed, iclass 34, count 0 2006.225.08:13:11.57#ibcon#about to write, iclass 34, count 0 2006.225.08:13:11.57#ibcon#wrote, iclass 34, count 0 2006.225.08:13:11.57#ibcon#about to read 3, iclass 34, count 0 2006.225.08:13:11.61#ibcon#read 3, iclass 34, count 0 2006.225.08:13:11.61#ibcon#about to read 4, iclass 34, count 0 2006.225.08:13:11.61#ibcon#read 4, iclass 34, count 0 2006.225.08:13:11.61#ibcon#about to read 5, iclass 34, count 0 2006.225.08:13:11.61#ibcon#read 5, iclass 34, count 0 2006.225.08:13:11.61#ibcon#about to read 6, iclass 34, count 0 2006.225.08:13:11.61#ibcon#read 6, iclass 34, count 0 2006.225.08:13:11.61#ibcon#end of sib2, iclass 34, count 0 2006.225.08:13:11.61#ibcon#*after write, iclass 34, count 0 2006.225.08:13:11.61#ibcon#*before return 0, iclass 34, count 0 2006.225.08:13:11.61#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:13:11.61#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:13:11.61#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.08:13:11.61#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.08:13:11.61$vc4f8/vb=4,4 2006.225.08:13:11.61#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.08:13:11.61#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.08:13:11.61#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:11.61#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:13:11.67#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:13:11.67#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:13:11.67#ibcon#enter wrdev, iclass 36, count 2 2006.225.08:13:11.67#ibcon#first serial, iclass 36, count 2 2006.225.08:13:11.67#ibcon#enter sib2, iclass 36, count 2 2006.225.08:13:11.67#ibcon#flushed, iclass 36, count 2 2006.225.08:13:11.67#ibcon#about to write, iclass 36, count 2 2006.225.08:13:11.67#ibcon#wrote, iclass 36, count 2 2006.225.08:13:11.67#ibcon#about to read 3, iclass 36, count 2 2006.225.08:13:11.69#ibcon#read 3, iclass 36, count 2 2006.225.08:13:11.69#ibcon#about to read 4, iclass 36, count 2 2006.225.08:13:11.69#ibcon#read 4, iclass 36, count 2 2006.225.08:13:11.69#ibcon#about to read 5, iclass 36, count 2 2006.225.08:13:11.69#ibcon#read 5, iclass 36, count 2 2006.225.08:13:11.69#ibcon#about to read 6, iclass 36, count 2 2006.225.08:13:11.69#ibcon#read 6, iclass 36, count 2 2006.225.08:13:11.69#ibcon#end of sib2, iclass 36, count 2 2006.225.08:13:11.69#ibcon#*mode == 0, iclass 36, count 2 2006.225.08:13:11.69#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.08:13:11.69#ibcon#[27=AT04-04\r\n] 2006.225.08:13:11.69#ibcon#*before write, iclass 36, count 2 2006.225.08:13:11.69#ibcon#enter sib2, iclass 36, count 2 2006.225.08:13:11.69#ibcon#flushed, iclass 36, count 2 2006.225.08:13:11.69#ibcon#about to write, iclass 36, count 2 2006.225.08:13:11.69#ibcon#wrote, iclass 36, count 2 2006.225.08:13:11.69#ibcon#about to read 3, iclass 36, count 2 2006.225.08:13:11.72#ibcon#read 3, iclass 36, count 2 2006.225.08:13:11.72#ibcon#about to read 4, iclass 36, count 2 2006.225.08:13:11.72#ibcon#read 4, iclass 36, count 2 2006.225.08:13:11.72#ibcon#about to read 5, iclass 36, count 2 2006.225.08:13:11.72#ibcon#read 5, iclass 36, count 2 2006.225.08:13:11.72#ibcon#about to read 6, iclass 36, count 2 2006.225.08:13:11.72#ibcon#read 6, iclass 36, count 2 2006.225.08:13:11.72#ibcon#end of sib2, iclass 36, count 2 2006.225.08:13:11.72#ibcon#*after write, iclass 36, count 2 2006.225.08:13:11.72#ibcon#*before return 0, iclass 36, count 2 2006.225.08:13:11.72#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:13:11.72#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:13:11.72#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.08:13:11.72#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:11.72#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:13:11.84#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:13:11.84#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:13:11.84#ibcon#enter wrdev, iclass 36, count 0 2006.225.08:13:11.84#ibcon#first serial, iclass 36, count 0 2006.225.08:13:11.84#ibcon#enter sib2, iclass 36, count 0 2006.225.08:13:11.84#ibcon#flushed, iclass 36, count 0 2006.225.08:13:11.84#ibcon#about to write, iclass 36, count 0 2006.225.08:13:11.84#ibcon#wrote, iclass 36, count 0 2006.225.08:13:11.84#ibcon#about to read 3, iclass 36, count 0 2006.225.08:13:11.86#ibcon#read 3, iclass 36, count 0 2006.225.08:13:11.86#ibcon#about to read 4, iclass 36, count 0 2006.225.08:13:11.86#ibcon#read 4, iclass 36, count 0 2006.225.08:13:11.86#ibcon#about to read 5, iclass 36, count 0 2006.225.08:13:11.86#ibcon#read 5, iclass 36, count 0 2006.225.08:13:11.86#ibcon#about to read 6, iclass 36, count 0 2006.225.08:13:11.86#ibcon#read 6, iclass 36, count 0 2006.225.08:13:11.86#ibcon#end of sib2, iclass 36, count 0 2006.225.08:13:11.86#ibcon#*mode == 0, iclass 36, count 0 2006.225.08:13:11.86#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.08:13:11.86#ibcon#[27=USB\r\n] 2006.225.08:13:11.86#ibcon#*before write, iclass 36, count 0 2006.225.08:13:11.86#ibcon#enter sib2, iclass 36, count 0 2006.225.08:13:11.86#ibcon#flushed, iclass 36, count 0 2006.225.08:13:11.86#ibcon#about to write, iclass 36, count 0 2006.225.08:13:11.86#ibcon#wrote, iclass 36, count 0 2006.225.08:13:11.86#ibcon#about to read 3, iclass 36, count 0 2006.225.08:13:11.89#ibcon#read 3, iclass 36, count 0 2006.225.08:13:11.89#ibcon#about to read 4, iclass 36, count 0 2006.225.08:13:11.89#ibcon#read 4, iclass 36, count 0 2006.225.08:13:11.89#ibcon#about to read 5, iclass 36, count 0 2006.225.08:13:11.89#ibcon#read 5, iclass 36, count 0 2006.225.08:13:11.89#ibcon#about to read 6, iclass 36, count 0 2006.225.08:13:11.89#ibcon#read 6, iclass 36, count 0 2006.225.08:13:11.89#ibcon#end of sib2, iclass 36, count 0 2006.225.08:13:11.89#ibcon#*after write, iclass 36, count 0 2006.225.08:13:11.89#ibcon#*before return 0, iclass 36, count 0 2006.225.08:13:11.89#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:13:11.89#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:13:11.89#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.08:13:11.89#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.08:13:11.89$vc4f8/vblo=5,744.99 2006.225.08:13:11.89#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.08:13:11.89#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.08:13:11.89#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:11.89#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:13:11.89#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:13:11.89#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:13:11.89#ibcon#enter wrdev, iclass 38, count 0 2006.225.08:13:11.89#ibcon#first serial, iclass 38, count 0 2006.225.08:13:11.89#ibcon#enter sib2, iclass 38, count 0 2006.225.08:13:11.89#ibcon#flushed, iclass 38, count 0 2006.225.08:13:11.89#ibcon#about to write, iclass 38, count 0 2006.225.08:13:11.89#ibcon#wrote, iclass 38, count 0 2006.225.08:13:11.89#ibcon#about to read 3, iclass 38, count 0 2006.225.08:13:11.91#ibcon#read 3, iclass 38, count 0 2006.225.08:13:11.91#ibcon#about to read 4, iclass 38, count 0 2006.225.08:13:11.91#ibcon#read 4, iclass 38, count 0 2006.225.08:13:11.91#ibcon#about to read 5, iclass 38, count 0 2006.225.08:13:11.91#ibcon#read 5, iclass 38, count 0 2006.225.08:13:11.91#ibcon#about to read 6, iclass 38, count 0 2006.225.08:13:11.91#ibcon#read 6, iclass 38, count 0 2006.225.08:13:11.91#ibcon#end of sib2, iclass 38, count 0 2006.225.08:13:11.91#ibcon#*mode == 0, iclass 38, count 0 2006.225.08:13:11.91#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.08:13:11.91#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:13:11.91#ibcon#*before write, iclass 38, count 0 2006.225.08:13:11.91#ibcon#enter sib2, iclass 38, count 0 2006.225.08:13:11.91#ibcon#flushed, iclass 38, count 0 2006.225.08:13:11.91#ibcon#about to write, iclass 38, count 0 2006.225.08:13:11.91#ibcon#wrote, iclass 38, count 0 2006.225.08:13:11.91#ibcon#about to read 3, iclass 38, count 0 2006.225.08:13:11.95#ibcon#read 3, iclass 38, count 0 2006.225.08:13:11.95#ibcon#about to read 4, iclass 38, count 0 2006.225.08:13:11.95#ibcon#read 4, iclass 38, count 0 2006.225.08:13:11.95#ibcon#about to read 5, iclass 38, count 0 2006.225.08:13:11.95#ibcon#read 5, iclass 38, count 0 2006.225.08:13:11.95#ibcon#about to read 6, iclass 38, count 0 2006.225.08:13:11.95#ibcon#read 6, iclass 38, count 0 2006.225.08:13:11.95#ibcon#end of sib2, iclass 38, count 0 2006.225.08:13:11.95#ibcon#*after write, iclass 38, count 0 2006.225.08:13:11.95#ibcon#*before return 0, iclass 38, count 0 2006.225.08:13:11.95#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:13:11.95#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:13:11.95#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.08:13:11.95#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.08:13:11.95$vc4f8/vb=5,4 2006.225.08:13:11.95#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.225.08:13:11.95#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.225.08:13:11.95#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:11.95#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:13:12.01#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:13:12.01#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:13:12.01#ibcon#enter wrdev, iclass 40, count 2 2006.225.08:13:12.01#ibcon#first serial, iclass 40, count 2 2006.225.08:13:12.01#ibcon#enter sib2, iclass 40, count 2 2006.225.08:13:12.01#ibcon#flushed, iclass 40, count 2 2006.225.08:13:12.01#ibcon#about to write, iclass 40, count 2 2006.225.08:13:12.01#ibcon#wrote, iclass 40, count 2 2006.225.08:13:12.01#ibcon#about to read 3, iclass 40, count 2 2006.225.08:13:12.03#ibcon#read 3, iclass 40, count 2 2006.225.08:13:12.03#ibcon#about to read 4, iclass 40, count 2 2006.225.08:13:12.03#ibcon#read 4, iclass 40, count 2 2006.225.08:13:12.03#ibcon#about to read 5, iclass 40, count 2 2006.225.08:13:12.03#ibcon#read 5, iclass 40, count 2 2006.225.08:13:12.03#ibcon#about to read 6, iclass 40, count 2 2006.225.08:13:12.03#ibcon#read 6, iclass 40, count 2 2006.225.08:13:12.03#ibcon#end of sib2, iclass 40, count 2 2006.225.08:13:12.03#ibcon#*mode == 0, iclass 40, count 2 2006.225.08:13:12.03#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.225.08:13:12.03#ibcon#[27=AT05-04\r\n] 2006.225.08:13:12.03#ibcon#*before write, iclass 40, count 2 2006.225.08:13:12.03#ibcon#enter sib2, iclass 40, count 2 2006.225.08:13:12.03#ibcon#flushed, iclass 40, count 2 2006.225.08:13:12.03#ibcon#about to write, iclass 40, count 2 2006.225.08:13:12.03#ibcon#wrote, iclass 40, count 2 2006.225.08:13:12.03#ibcon#about to read 3, iclass 40, count 2 2006.225.08:13:12.06#ibcon#read 3, iclass 40, count 2 2006.225.08:13:12.06#ibcon#about to read 4, iclass 40, count 2 2006.225.08:13:12.06#ibcon#read 4, iclass 40, count 2 2006.225.08:13:12.06#ibcon#about to read 5, iclass 40, count 2 2006.225.08:13:12.06#ibcon#read 5, iclass 40, count 2 2006.225.08:13:12.06#ibcon#about to read 6, iclass 40, count 2 2006.225.08:13:12.06#ibcon#read 6, iclass 40, count 2 2006.225.08:13:12.06#ibcon#end of sib2, iclass 40, count 2 2006.225.08:13:12.06#ibcon#*after write, iclass 40, count 2 2006.225.08:13:12.06#ibcon#*before return 0, iclass 40, count 2 2006.225.08:13:12.06#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:13:12.06#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:13:12.06#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.225.08:13:12.06#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:12.06#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:13:12.18#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:13:12.18#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:13:12.18#ibcon#enter wrdev, iclass 40, count 0 2006.225.08:13:12.18#ibcon#first serial, iclass 40, count 0 2006.225.08:13:12.18#ibcon#enter sib2, iclass 40, count 0 2006.225.08:13:12.18#ibcon#flushed, iclass 40, count 0 2006.225.08:13:12.18#ibcon#about to write, iclass 40, count 0 2006.225.08:13:12.18#ibcon#wrote, iclass 40, count 0 2006.225.08:13:12.18#ibcon#about to read 3, iclass 40, count 0 2006.225.08:13:12.22#ibcon#read 3, iclass 40, count 0 2006.225.08:13:12.22#ibcon#about to read 4, iclass 40, count 0 2006.225.08:13:12.22#ibcon#read 4, iclass 40, count 0 2006.225.08:13:12.22#ibcon#about to read 5, iclass 40, count 0 2006.225.08:13:12.22#ibcon#read 5, iclass 40, count 0 2006.225.08:13:12.22#ibcon#about to read 6, iclass 40, count 0 2006.225.08:13:12.22#ibcon#read 6, iclass 40, count 0 2006.225.08:13:12.22#ibcon#end of sib2, iclass 40, count 0 2006.225.08:13:12.22#ibcon#*mode == 0, iclass 40, count 0 2006.225.08:13:12.22#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.08:13:12.22#ibcon#[27=USB\r\n] 2006.225.08:13:12.22#ibcon#*before write, iclass 40, count 0 2006.225.08:13:12.22#ibcon#enter sib2, iclass 40, count 0 2006.225.08:13:12.22#ibcon#flushed, iclass 40, count 0 2006.225.08:13:12.22#ibcon#about to write, iclass 40, count 0 2006.225.08:13:12.22#ibcon#wrote, iclass 40, count 0 2006.225.08:13:12.22#ibcon#about to read 3, iclass 40, count 0 2006.225.08:13:12.24#ibcon#read 3, iclass 40, count 0 2006.225.08:13:12.24#ibcon#about to read 4, iclass 40, count 0 2006.225.08:13:12.24#ibcon#read 4, iclass 40, count 0 2006.225.08:13:12.24#ibcon#about to read 5, iclass 40, count 0 2006.225.08:13:12.24#ibcon#read 5, iclass 40, count 0 2006.225.08:13:12.24#ibcon#about to read 6, iclass 40, count 0 2006.225.08:13:12.24#ibcon#read 6, iclass 40, count 0 2006.225.08:13:12.24#ibcon#end of sib2, iclass 40, count 0 2006.225.08:13:12.24#ibcon#*after write, iclass 40, count 0 2006.225.08:13:12.24#ibcon#*before return 0, iclass 40, count 0 2006.225.08:13:12.24#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:13:12.24#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:13:12.24#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.08:13:12.24#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.08:13:12.24$vc4f8/vblo=6,752.99 2006.225.08:13:12.24#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.08:13:12.24#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.08:13:12.24#ibcon#ireg 17 cls_cnt 0 2006.225.08:13:12.24#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:13:12.24#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:13:12.24#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:13:12.24#ibcon#enter wrdev, iclass 4, count 0 2006.225.08:13:12.24#ibcon#first serial, iclass 4, count 0 2006.225.08:13:12.24#ibcon#enter sib2, iclass 4, count 0 2006.225.08:13:12.24#ibcon#flushed, iclass 4, count 0 2006.225.08:13:12.24#ibcon#about to write, iclass 4, count 0 2006.225.08:13:12.24#ibcon#wrote, iclass 4, count 0 2006.225.08:13:12.24#ibcon#about to read 3, iclass 4, count 0 2006.225.08:13:12.26#ibcon#read 3, iclass 4, count 0 2006.225.08:13:12.26#ibcon#about to read 4, iclass 4, count 0 2006.225.08:13:12.26#ibcon#read 4, iclass 4, count 0 2006.225.08:13:12.26#ibcon#about to read 5, iclass 4, count 0 2006.225.08:13:12.26#ibcon#read 5, iclass 4, count 0 2006.225.08:13:12.26#ibcon#about to read 6, iclass 4, count 0 2006.225.08:13:12.26#ibcon#read 6, iclass 4, count 0 2006.225.08:13:12.26#ibcon#end of sib2, iclass 4, count 0 2006.225.08:13:12.26#ibcon#*mode == 0, iclass 4, count 0 2006.225.08:13:12.26#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.08:13:12.26#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:13:12.26#ibcon#*before write, iclass 4, count 0 2006.225.08:13:12.26#ibcon#enter sib2, iclass 4, count 0 2006.225.08:13:12.26#ibcon#flushed, iclass 4, count 0 2006.225.08:13:12.26#ibcon#about to write, iclass 4, count 0 2006.225.08:13:12.26#ibcon#wrote, iclass 4, count 0 2006.225.08:13:12.26#ibcon#about to read 3, iclass 4, count 0 2006.225.08:13:12.30#ibcon#read 3, iclass 4, count 0 2006.225.08:13:12.30#ibcon#about to read 4, iclass 4, count 0 2006.225.08:13:12.30#ibcon#read 4, iclass 4, count 0 2006.225.08:13:12.30#ibcon#about to read 5, iclass 4, count 0 2006.225.08:13:12.30#ibcon#read 5, iclass 4, count 0 2006.225.08:13:12.30#ibcon#about to read 6, iclass 4, count 0 2006.225.08:13:12.30#ibcon#read 6, iclass 4, count 0 2006.225.08:13:12.30#ibcon#end of sib2, iclass 4, count 0 2006.225.08:13:12.30#ibcon#*after write, iclass 4, count 0 2006.225.08:13:12.30#ibcon#*before return 0, iclass 4, count 0 2006.225.08:13:12.30#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:13:12.30#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:13:12.30#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.08:13:12.30#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.08:13:12.30$vc4f8/vb=6,4 2006.225.08:13:12.30#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.225.08:13:12.30#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.225.08:13:12.30#ibcon#ireg 11 cls_cnt 2 2006.225.08:13:12.30#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:13:12.36#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:13:12.36#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:13:12.36#ibcon#enter wrdev, iclass 6, count 2 2006.225.08:13:12.36#ibcon#first serial, iclass 6, count 2 2006.225.08:13:12.36#ibcon#enter sib2, iclass 6, count 2 2006.225.08:13:12.36#ibcon#flushed, iclass 6, count 2 2006.225.08:13:12.36#ibcon#about to write, iclass 6, count 2 2006.225.08:13:12.36#ibcon#wrote, iclass 6, count 2 2006.225.08:13:12.36#ibcon#about to read 3, iclass 6, count 2 2006.225.08:13:12.38#ibcon#read 3, iclass 6, count 2 2006.225.08:13:12.38#ibcon#about to read 4, iclass 6, count 2 2006.225.08:13:12.38#ibcon#read 4, iclass 6, count 2 2006.225.08:13:12.38#ibcon#about to read 5, iclass 6, count 2 2006.225.08:13:12.38#ibcon#read 5, iclass 6, count 2 2006.225.08:13:12.38#ibcon#about to read 6, iclass 6, count 2 2006.225.08:13:12.38#ibcon#read 6, iclass 6, count 2 2006.225.08:13:12.38#ibcon#end of sib2, iclass 6, count 2 2006.225.08:13:12.38#ibcon#*mode == 0, iclass 6, count 2 2006.225.08:13:12.38#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.225.08:13:12.38#ibcon#[27=AT06-04\r\n] 2006.225.08:13:12.38#ibcon#*before write, iclass 6, count 2 2006.225.08:13:12.38#ibcon#enter sib2, iclass 6, count 2 2006.225.08:13:12.38#ibcon#flushed, iclass 6, count 2 2006.225.08:13:12.38#ibcon#about to write, iclass 6, count 2 2006.225.08:13:12.38#ibcon#wrote, iclass 6, count 2 2006.225.08:13:12.38#ibcon#about to read 3, iclass 6, count 2 2006.225.08:13:12.41#ibcon#read 3, iclass 6, count 2 2006.225.08:13:12.41#ibcon#about to read 4, iclass 6, count 2 2006.225.08:13:12.41#ibcon#read 4, iclass 6, count 2 2006.225.08:13:12.41#ibcon#about to read 5, iclass 6, count 2 2006.225.08:13:12.41#ibcon#read 5, iclass 6, count 2 2006.225.08:13:12.41#ibcon#about to read 6, iclass 6, count 2 2006.225.08:13:12.41#ibcon#read 6, iclass 6, count 2 2006.225.08:13:12.41#ibcon#end of sib2, iclass 6, count 2 2006.225.08:13:12.41#ibcon#*after write, iclass 6, count 2 2006.225.08:13:12.41#ibcon#*before return 0, iclass 6, count 2 2006.225.08:13:12.41#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:13:12.41#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:13:12.41#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.225.08:13:12.41#ibcon#ireg 7 cls_cnt 0 2006.225.08:13:12.41#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:13:12.53#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:13:12.53#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:13:12.53#ibcon#enter wrdev, iclass 6, count 0 2006.225.08:13:12.53#ibcon#first serial, iclass 6, count 0 2006.225.08:13:12.53#ibcon#enter sib2, iclass 6, count 0 2006.225.08:13:12.53#ibcon#flushed, iclass 6, count 0 2006.225.08:13:12.53#ibcon#about to write, iclass 6, count 0 2006.225.08:13:12.53#ibcon#wrote, iclass 6, count 0 2006.225.08:13:12.53#ibcon#about to read 3, iclass 6, count 0 2006.225.08:13:12.55#ibcon#read 3, iclass 6, count 0 2006.225.08:13:12.55#ibcon#about to read 4, iclass 6, count 0 2006.225.08:13:12.55#ibcon#read 4, iclass 6, count 0 2006.225.08:13:12.55#ibcon#about to read 5, iclass 6, count 0 2006.225.08:13:12.55#ibcon#read 5, iclass 6, count 0 2006.225.08:13:12.55#ibcon#about to read 6, iclass 6, count 0 2006.225.08:13:12.55#ibcon#read 6, iclass 6, count 0 2006.225.08:13:12.55#ibcon#end of sib2, iclass 6, count 0 2006.225.08:13:12.55#ibcon#*mode == 0, iclass 6, count 0 2006.225.08:13:12.55#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.08:13:12.55#ibcon#[27=USB\r\n] 2006.225.08:13:12.55#ibcon#*before write, iclass 6, count 0 2006.225.08:13:12.55#ibcon#enter sib2, iclass 6, count 0 2006.225.08:13:12.55#ibcon#flushed, iclass 6, count 0 2006.225.08:13:12.55#ibcon#about to write, iclass 6, count 0 2006.225.08:13:12.55#ibcon#wrote, iclass 6, count 0 2006.225.08:13:12.55#ibcon#about to read 3, iclass 6, count 0 2006.225.08:13:12.58#ibcon#read 3, iclass 6, count 0 2006.225.08:13:12.58#ibcon#about to read 4, iclass 6, count 0 2006.225.08:13:12.58#ibcon#read 4, iclass 6, count 0 2006.225.08:13:12.58#ibcon#about to read 5, iclass 6, count 0 2006.225.08:13:12.58#ibcon#read 5, iclass 6, count 0 2006.225.08:13:12.58#ibcon#about to read 6, iclass 6, count 0 2006.225.08:13:12.58#ibcon#read 6, iclass 6, count 0 2006.225.08:13:12.58#ibcon#end of sib2, iclass 6, count 0 2006.225.08:13:12.58#ibcon#*after write, iclass 6, count 0 2006.225.08:13:12.58#ibcon#*before return 0, iclass 6, count 0 2006.225.08:13:12.58#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:13:12.58#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:13:12.58#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.08:13:12.58#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.08:13:12.58$vc4f8/vabw=wide 2006.225.08:13:12.58#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.08:13:12.58#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.08:13:12.58#ibcon#ireg 8 cls_cnt 0 2006.225.08:13:12.58#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:13:12.58#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:13:12.58#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:13:12.58#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:13:12.58#ibcon#first serial, iclass 10, count 0 2006.225.08:13:12.58#ibcon#enter sib2, iclass 10, count 0 2006.225.08:13:12.58#ibcon#flushed, iclass 10, count 0 2006.225.08:13:12.58#ibcon#about to write, iclass 10, count 0 2006.225.08:13:12.58#ibcon#wrote, iclass 10, count 0 2006.225.08:13:12.58#ibcon#about to read 3, iclass 10, count 0 2006.225.08:13:12.60#ibcon#read 3, iclass 10, count 0 2006.225.08:13:12.60#ibcon#about to read 4, iclass 10, count 0 2006.225.08:13:12.60#ibcon#read 4, iclass 10, count 0 2006.225.08:13:12.60#ibcon#about to read 5, iclass 10, count 0 2006.225.08:13:12.60#ibcon#read 5, iclass 10, count 0 2006.225.08:13:12.60#ibcon#about to read 6, iclass 10, count 0 2006.225.08:13:12.60#ibcon#read 6, iclass 10, count 0 2006.225.08:13:12.60#ibcon#end of sib2, iclass 10, count 0 2006.225.08:13:12.60#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:13:12.60#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:13:12.60#ibcon#[25=BW32\r\n] 2006.225.08:13:12.60#ibcon#*before write, iclass 10, count 0 2006.225.08:13:12.60#ibcon#enter sib2, iclass 10, count 0 2006.225.08:13:12.60#ibcon#flushed, iclass 10, count 0 2006.225.08:13:12.60#ibcon#about to write, iclass 10, count 0 2006.225.08:13:12.60#ibcon#wrote, iclass 10, count 0 2006.225.08:13:12.60#ibcon#about to read 3, iclass 10, count 0 2006.225.08:13:12.63#ibcon#read 3, iclass 10, count 0 2006.225.08:13:12.63#ibcon#about to read 4, iclass 10, count 0 2006.225.08:13:12.63#ibcon#read 4, iclass 10, count 0 2006.225.08:13:12.63#ibcon#about to read 5, iclass 10, count 0 2006.225.08:13:12.63#ibcon#read 5, iclass 10, count 0 2006.225.08:13:12.63#ibcon#about to read 6, iclass 10, count 0 2006.225.08:13:12.63#ibcon#read 6, iclass 10, count 0 2006.225.08:13:12.63#ibcon#end of sib2, iclass 10, count 0 2006.225.08:13:12.63#ibcon#*after write, iclass 10, count 0 2006.225.08:13:12.63#ibcon#*before return 0, iclass 10, count 0 2006.225.08:13:12.63#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:13:12.63#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:13:12.63#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:13:12.63#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:13:12.63$vc4f8/vbbw=wide 2006.225.08:13:12.63#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.08:13:12.63#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.08:13:12.63#ibcon#ireg 8 cls_cnt 0 2006.225.08:13:12.63#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:13:12.70#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:13:12.70#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:13:12.70#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:13:12.70#ibcon#first serial, iclass 12, count 0 2006.225.08:13:12.70#ibcon#enter sib2, iclass 12, count 0 2006.225.08:13:12.70#ibcon#flushed, iclass 12, count 0 2006.225.08:13:12.70#ibcon#about to write, iclass 12, count 0 2006.225.08:13:12.70#ibcon#wrote, iclass 12, count 0 2006.225.08:13:12.70#ibcon#about to read 3, iclass 12, count 0 2006.225.08:13:12.72#ibcon#read 3, iclass 12, count 0 2006.225.08:13:12.72#ibcon#about to read 4, iclass 12, count 0 2006.225.08:13:12.72#ibcon#read 4, iclass 12, count 0 2006.225.08:13:12.72#ibcon#about to read 5, iclass 12, count 0 2006.225.08:13:12.72#ibcon#read 5, iclass 12, count 0 2006.225.08:13:12.72#ibcon#about to read 6, iclass 12, count 0 2006.225.08:13:12.72#ibcon#read 6, iclass 12, count 0 2006.225.08:13:12.72#ibcon#end of sib2, iclass 12, count 0 2006.225.08:13:12.72#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:13:12.72#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:13:12.72#ibcon#[27=BW32\r\n] 2006.225.08:13:12.72#ibcon#*before write, iclass 12, count 0 2006.225.08:13:12.72#ibcon#enter sib2, iclass 12, count 0 2006.225.08:13:12.72#ibcon#flushed, iclass 12, count 0 2006.225.08:13:12.72#ibcon#about to write, iclass 12, count 0 2006.225.08:13:12.72#ibcon#wrote, iclass 12, count 0 2006.225.08:13:12.72#ibcon#about to read 3, iclass 12, count 0 2006.225.08:13:12.75#ibcon#read 3, iclass 12, count 0 2006.225.08:13:12.75#ibcon#about to read 4, iclass 12, count 0 2006.225.08:13:12.75#ibcon#read 4, iclass 12, count 0 2006.225.08:13:12.75#ibcon#about to read 5, iclass 12, count 0 2006.225.08:13:12.75#ibcon#read 5, iclass 12, count 0 2006.225.08:13:12.75#ibcon#about to read 6, iclass 12, count 0 2006.225.08:13:12.75#ibcon#read 6, iclass 12, count 0 2006.225.08:13:12.75#ibcon#end of sib2, iclass 12, count 0 2006.225.08:13:12.75#ibcon#*after write, iclass 12, count 0 2006.225.08:13:12.75#ibcon#*before return 0, iclass 12, count 0 2006.225.08:13:12.75#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:13:12.75#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:13:12.75#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:13:12.75#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:13:12.75$4f8m12a/ifd4f 2006.225.08:13:12.75$ifd4f/lo= 2006.225.08:13:12.75$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:13:12.75$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:13:12.75$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:13:12.75$ifd4f/patch= 2006.225.08:13:12.75$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:13:12.75$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:13:12.75$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:13:12.75$4f8m12a/"form=m,16.000,1:2 2006.225.08:13:12.75$4f8m12a/"tpicd 2006.225.08:13:12.75$4f8m12a/echo=off 2006.225.08:13:12.75$4f8m12a/xlog=off 2006.225.08:13:12.75:!2006.225.08:14:00 2006.225.08:13:37.14#trakl#Source acquired 2006.225.08:13:39.14#flagr#flagr/antenna,acquired 2006.225.08:14:00.00:preob 2006.225.08:14:01.14/onsource/TRACKING 2006.225.08:14:01.14:!2006.225.08:14:10 2006.225.08:14:10.00:data_valid=on 2006.225.08:14:10.00:midob 2006.225.08:14:10.14/onsource/TRACKING 2006.225.08:14:10.14/wx/28.08,1003.3,72 2006.225.08:14:10.26/cable/+6.4056E-03 2006.225.08:14:11.35/va/01,08,usb,yes,29,30 2006.225.08:14:11.35/va/02,07,usb,yes,29,30 2006.225.08:14:11.35/va/03,06,usb,yes,31,31 2006.225.08:14:11.35/va/04,07,usb,yes,30,33 2006.225.08:14:11.35/va/05,07,usb,yes,32,34 2006.225.08:14:11.35/va/06,06,usb,yes,31,31 2006.225.08:14:11.35/va/07,06,usb,yes,32,31 2006.225.08:14:11.35/va/08,07,usb,yes,30,29 2006.225.08:14:11.58/valo/01,532.99,yes,locked 2006.225.08:14:11.58/valo/02,572.99,yes,locked 2006.225.08:14:11.58/valo/03,672.99,yes,locked 2006.225.08:14:11.58/valo/04,832.99,yes,locked 2006.225.08:14:11.58/valo/05,652.99,yes,locked 2006.225.08:14:11.58/valo/06,772.99,yes,locked 2006.225.08:14:11.58/valo/07,832.99,yes,locked 2006.225.08:14:11.58/valo/08,852.99,yes,locked 2006.225.08:14:12.67/vb/01,04,usb,yes,31,29 2006.225.08:14:12.67/vb/02,04,usb,yes,32,34 2006.225.08:14:12.67/vb/03,04,usb,yes,29,33 2006.225.08:14:12.67/vb/04,04,usb,yes,30,30 2006.225.08:14:12.67/vb/05,04,usb,yes,28,32 2006.225.08:14:12.67/vb/06,04,usb,yes,29,32 2006.225.08:14:12.67/vb/07,04,usb,yes,31,31 2006.225.08:14:12.67/vb/08,04,usb,yes,29,32 2006.225.08:14:12.91/vblo/01,632.99,yes,locked 2006.225.08:14:12.91/vblo/02,640.99,yes,locked 2006.225.08:14:12.91/vblo/03,656.99,yes,locked 2006.225.08:14:12.91/vblo/04,712.99,yes,locked 2006.225.08:14:12.91/vblo/05,744.99,yes,locked 2006.225.08:14:12.91/vblo/06,752.99,yes,locked 2006.225.08:14:12.91/vblo/07,734.99,yes,locked 2006.225.08:14:12.91/vblo/08,744.99,yes,locked 2006.225.08:14:13.06/vabw/8 2006.225.08:14:13.21/vbbw/8 2006.225.08:14:13.30/xfe/off,on,15.0 2006.225.08:14:13.67/ifatt/23,28,28,28 2006.225.08:14:14.07/fmout-gps/S +4.59E-07 2006.225.08:14:14.11:!2006.225.08:15:20 2006.225.08:15:20.01:data_valid=off 2006.225.08:15:20.02:postob 2006.225.08:15:20.13/cable/+6.4049E-03 2006.225.08:15:20.14/wx/28.08,1003.3,73 2006.225.08:15:21.07/fmout-gps/S +4.57E-07 2006.225.08:15:21.08:scan_name=225-0816,k06225,60 2006.225.08:15:21.08:source=1128+385,113053.28,381518.5,2000.0,ccw 2006.225.08:15:22.14#flagr#flagr/antenna,new-source 2006.225.08:15:22.15:checkk5 2006.225.08:15:22.52/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:15:22.90/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:15:23.27/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:15:23.65/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:15:24.01/chk_obsdata//k5ts1/T2250814??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.225.08:15:24.38/chk_obsdata//k5ts2/T2250814??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.225.08:15:24.74/chk_obsdata//k5ts3/T2250814??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.225.08:15:25.11/chk_obsdata//k5ts4/T2250814??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.225.08:15:25.81/k5log//k5ts1_log_newline 2006.225.08:15:26.51/k5log//k5ts2_log_newline 2006.225.08:15:27.20/k5log//k5ts3_log_newline 2006.225.08:15:27.90/k5log//k5ts4_log_newline 2006.225.08:15:27.92/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:15:27.92:4f8m12a=2 2006.225.08:15:27.92$4f8m12a/echo=on 2006.225.08:15:27.92$4f8m12a/pcalon 2006.225.08:15:27.92$pcalon/"no phase cal control is implemented here 2006.225.08:15:27.92$4f8m12a/"tpicd=stop 2006.225.08:15:27.92$4f8m12a/vc4f8 2006.225.08:15:27.92$vc4f8/valo=1,532.99 2006.225.08:15:27.92#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.225.08:15:27.92#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.225.08:15:27.92#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:27.92#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:15:27.92#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:15:27.92#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:15:27.92#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:15:27.92#ibcon#first serial, iclass 35, count 0 2006.225.08:15:27.92#ibcon#enter sib2, iclass 35, count 0 2006.225.08:15:27.92#ibcon#flushed, iclass 35, count 0 2006.225.08:15:27.92#ibcon#about to write, iclass 35, count 0 2006.225.08:15:27.92#ibcon#wrote, iclass 35, count 0 2006.225.08:15:27.92#ibcon#about to read 3, iclass 35, count 0 2006.225.08:15:27.97#ibcon#read 3, iclass 35, count 0 2006.225.08:15:27.97#ibcon#about to read 4, iclass 35, count 0 2006.225.08:15:27.97#ibcon#read 4, iclass 35, count 0 2006.225.08:15:27.97#ibcon#about to read 5, iclass 35, count 0 2006.225.08:15:27.97#ibcon#read 5, iclass 35, count 0 2006.225.08:15:27.97#ibcon#about to read 6, iclass 35, count 0 2006.225.08:15:27.97#ibcon#read 6, iclass 35, count 0 2006.225.08:15:27.97#ibcon#end of sib2, iclass 35, count 0 2006.225.08:15:27.97#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:15:27.97#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:15:27.97#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:15:27.97#ibcon#*before write, iclass 35, count 0 2006.225.08:15:27.97#ibcon#enter sib2, iclass 35, count 0 2006.225.08:15:27.97#ibcon#flushed, iclass 35, count 0 2006.225.08:15:27.97#ibcon#about to write, iclass 35, count 0 2006.225.08:15:27.97#ibcon#wrote, iclass 35, count 0 2006.225.08:15:27.97#ibcon#about to read 3, iclass 35, count 0 2006.225.08:15:28.01#ibcon#read 3, iclass 35, count 0 2006.225.08:15:28.01#ibcon#about to read 4, iclass 35, count 0 2006.225.08:15:28.01#ibcon#read 4, iclass 35, count 0 2006.225.08:15:28.01#ibcon#about to read 5, iclass 35, count 0 2006.225.08:15:28.01#ibcon#read 5, iclass 35, count 0 2006.225.08:15:28.01#ibcon#about to read 6, iclass 35, count 0 2006.225.08:15:28.01#ibcon#read 6, iclass 35, count 0 2006.225.08:15:28.01#ibcon#end of sib2, iclass 35, count 0 2006.225.08:15:28.01#ibcon#*after write, iclass 35, count 0 2006.225.08:15:28.01#ibcon#*before return 0, iclass 35, count 0 2006.225.08:15:28.01#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:15:28.01#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:15:28.01#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:15:28.01#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:15:28.01$vc4f8/va=1,8 2006.225.08:15:28.01#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.225.08:15:28.01#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.225.08:15:28.01#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:28.01#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:15:28.01#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:15:28.01#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:15:28.01#ibcon#enter wrdev, iclass 37, count 2 2006.225.08:15:28.01#ibcon#first serial, iclass 37, count 2 2006.225.08:15:28.01#ibcon#enter sib2, iclass 37, count 2 2006.225.08:15:28.01#ibcon#flushed, iclass 37, count 2 2006.225.08:15:28.01#ibcon#about to write, iclass 37, count 2 2006.225.08:15:28.01#ibcon#wrote, iclass 37, count 2 2006.225.08:15:28.01#ibcon#about to read 3, iclass 37, count 2 2006.225.08:15:28.03#ibcon#read 3, iclass 37, count 2 2006.225.08:15:28.03#ibcon#about to read 4, iclass 37, count 2 2006.225.08:15:28.03#ibcon#read 4, iclass 37, count 2 2006.225.08:15:28.03#ibcon#about to read 5, iclass 37, count 2 2006.225.08:15:28.03#ibcon#read 5, iclass 37, count 2 2006.225.08:15:28.03#ibcon#about to read 6, iclass 37, count 2 2006.225.08:15:28.03#ibcon#read 6, iclass 37, count 2 2006.225.08:15:28.03#ibcon#end of sib2, iclass 37, count 2 2006.225.08:15:28.03#ibcon#*mode == 0, iclass 37, count 2 2006.225.08:15:28.03#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.225.08:15:28.03#ibcon#[25=AT01-08\r\n] 2006.225.08:15:28.03#ibcon#*before write, iclass 37, count 2 2006.225.08:15:28.03#ibcon#enter sib2, iclass 37, count 2 2006.225.08:15:28.03#ibcon#flushed, iclass 37, count 2 2006.225.08:15:28.03#ibcon#about to write, iclass 37, count 2 2006.225.08:15:28.03#ibcon#wrote, iclass 37, count 2 2006.225.08:15:28.03#ibcon#about to read 3, iclass 37, count 2 2006.225.08:15:28.06#ibcon#read 3, iclass 37, count 2 2006.225.08:15:28.06#ibcon#about to read 4, iclass 37, count 2 2006.225.08:15:28.06#ibcon#read 4, iclass 37, count 2 2006.225.08:15:28.06#ibcon#about to read 5, iclass 37, count 2 2006.225.08:15:28.06#ibcon#read 5, iclass 37, count 2 2006.225.08:15:28.06#ibcon#about to read 6, iclass 37, count 2 2006.225.08:15:28.06#ibcon#read 6, iclass 37, count 2 2006.225.08:15:28.06#ibcon#end of sib2, iclass 37, count 2 2006.225.08:15:28.06#ibcon#*after write, iclass 37, count 2 2006.225.08:15:28.06#ibcon#*before return 0, iclass 37, count 2 2006.225.08:15:28.06#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:15:28.06#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:15:28.06#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.225.08:15:28.06#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:28.06#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:15:28.18#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:15:28.18#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:15:28.18#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:15:28.18#ibcon#first serial, iclass 37, count 0 2006.225.08:15:28.18#ibcon#enter sib2, iclass 37, count 0 2006.225.08:15:28.18#ibcon#flushed, iclass 37, count 0 2006.225.08:15:28.18#ibcon#about to write, iclass 37, count 0 2006.225.08:15:28.18#ibcon#wrote, iclass 37, count 0 2006.225.08:15:28.18#ibcon#about to read 3, iclass 37, count 0 2006.225.08:15:28.20#ibcon#read 3, iclass 37, count 0 2006.225.08:15:28.20#ibcon#about to read 4, iclass 37, count 0 2006.225.08:15:28.20#ibcon#read 4, iclass 37, count 0 2006.225.08:15:28.20#ibcon#about to read 5, iclass 37, count 0 2006.225.08:15:28.20#ibcon#read 5, iclass 37, count 0 2006.225.08:15:28.20#ibcon#about to read 6, iclass 37, count 0 2006.225.08:15:28.20#ibcon#read 6, iclass 37, count 0 2006.225.08:15:28.20#ibcon#end of sib2, iclass 37, count 0 2006.225.08:15:28.20#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:15:28.20#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:15:28.20#ibcon#[25=USB\r\n] 2006.225.08:15:28.20#ibcon#*before write, iclass 37, count 0 2006.225.08:15:28.20#ibcon#enter sib2, iclass 37, count 0 2006.225.08:15:28.20#ibcon#flushed, iclass 37, count 0 2006.225.08:15:28.20#ibcon#about to write, iclass 37, count 0 2006.225.08:15:28.20#ibcon#wrote, iclass 37, count 0 2006.225.08:15:28.20#ibcon#about to read 3, iclass 37, count 0 2006.225.08:15:28.23#ibcon#read 3, iclass 37, count 0 2006.225.08:15:28.23#ibcon#about to read 4, iclass 37, count 0 2006.225.08:15:28.23#ibcon#read 4, iclass 37, count 0 2006.225.08:15:28.23#ibcon#about to read 5, iclass 37, count 0 2006.225.08:15:28.23#ibcon#read 5, iclass 37, count 0 2006.225.08:15:28.23#ibcon#about to read 6, iclass 37, count 0 2006.225.08:15:28.23#ibcon#read 6, iclass 37, count 0 2006.225.08:15:28.23#ibcon#end of sib2, iclass 37, count 0 2006.225.08:15:28.23#ibcon#*after write, iclass 37, count 0 2006.225.08:15:28.23#ibcon#*before return 0, iclass 37, count 0 2006.225.08:15:28.23#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:15:28.23#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:15:28.23#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:15:28.23#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:15:28.24$vc4f8/valo=2,572.99 2006.225.08:15:28.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.08:15:28.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.08:15:28.24#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:28.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:15:28.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:15:28.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:15:28.24#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:15:28.24#ibcon#first serial, iclass 39, count 0 2006.225.08:15:28.24#ibcon#enter sib2, iclass 39, count 0 2006.225.08:15:28.24#ibcon#flushed, iclass 39, count 0 2006.225.08:15:28.24#ibcon#about to write, iclass 39, count 0 2006.225.08:15:28.24#ibcon#wrote, iclass 39, count 0 2006.225.08:15:28.24#ibcon#about to read 3, iclass 39, count 0 2006.225.08:15:28.25#ibcon#read 3, iclass 39, count 0 2006.225.08:15:28.25#ibcon#about to read 4, iclass 39, count 0 2006.225.08:15:28.25#ibcon#read 4, iclass 39, count 0 2006.225.08:15:28.25#ibcon#about to read 5, iclass 39, count 0 2006.225.08:15:28.25#ibcon#read 5, iclass 39, count 0 2006.225.08:15:28.25#ibcon#about to read 6, iclass 39, count 0 2006.225.08:15:28.25#ibcon#read 6, iclass 39, count 0 2006.225.08:15:28.25#ibcon#end of sib2, iclass 39, count 0 2006.225.08:15:28.25#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:15:28.25#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:15:28.25#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:15:28.25#ibcon#*before write, iclass 39, count 0 2006.225.08:15:28.25#ibcon#enter sib2, iclass 39, count 0 2006.225.08:15:28.25#ibcon#flushed, iclass 39, count 0 2006.225.08:15:28.25#ibcon#about to write, iclass 39, count 0 2006.225.08:15:28.25#ibcon#wrote, iclass 39, count 0 2006.225.08:15:28.25#ibcon#about to read 3, iclass 39, count 0 2006.225.08:15:28.29#ibcon#read 3, iclass 39, count 0 2006.225.08:15:28.29#ibcon#about to read 4, iclass 39, count 0 2006.225.08:15:28.29#ibcon#read 4, iclass 39, count 0 2006.225.08:15:28.29#ibcon#about to read 5, iclass 39, count 0 2006.225.08:15:28.29#ibcon#read 5, iclass 39, count 0 2006.225.08:15:28.29#ibcon#about to read 6, iclass 39, count 0 2006.225.08:15:28.29#ibcon#read 6, iclass 39, count 0 2006.225.08:15:28.29#ibcon#end of sib2, iclass 39, count 0 2006.225.08:15:28.29#ibcon#*after write, iclass 39, count 0 2006.225.08:15:28.29#ibcon#*before return 0, iclass 39, count 0 2006.225.08:15:28.29#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:15:28.29#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:15:28.29#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:15:28.29#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:15:28.29$vc4f8/va=2,7 2006.225.08:15:28.29#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.08:15:28.29#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.08:15:28.29#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:28.29#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:15:28.35#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:15:28.35#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:15:28.35#ibcon#enter wrdev, iclass 3, count 2 2006.225.08:15:28.35#ibcon#first serial, iclass 3, count 2 2006.225.08:15:28.35#ibcon#enter sib2, iclass 3, count 2 2006.225.08:15:28.35#ibcon#flushed, iclass 3, count 2 2006.225.08:15:28.35#ibcon#about to write, iclass 3, count 2 2006.225.08:15:28.35#ibcon#wrote, iclass 3, count 2 2006.225.08:15:28.35#ibcon#about to read 3, iclass 3, count 2 2006.225.08:15:28.37#ibcon#read 3, iclass 3, count 2 2006.225.08:15:28.37#ibcon#about to read 4, iclass 3, count 2 2006.225.08:15:28.37#ibcon#read 4, iclass 3, count 2 2006.225.08:15:28.37#ibcon#about to read 5, iclass 3, count 2 2006.225.08:15:28.37#ibcon#read 5, iclass 3, count 2 2006.225.08:15:28.37#ibcon#about to read 6, iclass 3, count 2 2006.225.08:15:28.37#ibcon#read 6, iclass 3, count 2 2006.225.08:15:28.37#ibcon#end of sib2, iclass 3, count 2 2006.225.08:15:28.37#ibcon#*mode == 0, iclass 3, count 2 2006.225.08:15:28.37#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.08:15:28.37#ibcon#[25=AT02-07\r\n] 2006.225.08:15:28.37#ibcon#*before write, iclass 3, count 2 2006.225.08:15:28.37#ibcon#enter sib2, iclass 3, count 2 2006.225.08:15:28.37#ibcon#flushed, iclass 3, count 2 2006.225.08:15:28.37#ibcon#about to write, iclass 3, count 2 2006.225.08:15:28.37#ibcon#wrote, iclass 3, count 2 2006.225.08:15:28.37#ibcon#about to read 3, iclass 3, count 2 2006.225.08:15:28.40#ibcon#read 3, iclass 3, count 2 2006.225.08:15:28.40#ibcon#about to read 4, iclass 3, count 2 2006.225.08:15:28.40#ibcon#read 4, iclass 3, count 2 2006.225.08:15:28.40#ibcon#about to read 5, iclass 3, count 2 2006.225.08:15:28.40#ibcon#read 5, iclass 3, count 2 2006.225.08:15:28.40#ibcon#about to read 6, iclass 3, count 2 2006.225.08:15:28.40#ibcon#read 6, iclass 3, count 2 2006.225.08:15:28.40#ibcon#end of sib2, iclass 3, count 2 2006.225.08:15:28.40#ibcon#*after write, iclass 3, count 2 2006.225.08:15:28.40#ibcon#*before return 0, iclass 3, count 2 2006.225.08:15:28.40#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:15:28.40#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:15:28.40#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.08:15:28.40#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:28.40#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:15:28.52#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:15:28.52#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:15:28.52#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:15:28.52#ibcon#first serial, iclass 3, count 0 2006.225.08:15:28.52#ibcon#enter sib2, iclass 3, count 0 2006.225.08:15:28.52#ibcon#flushed, iclass 3, count 0 2006.225.08:15:28.52#ibcon#about to write, iclass 3, count 0 2006.225.08:15:28.52#ibcon#wrote, iclass 3, count 0 2006.225.08:15:28.52#ibcon#about to read 3, iclass 3, count 0 2006.225.08:15:28.54#ibcon#read 3, iclass 3, count 0 2006.225.08:15:28.54#ibcon#about to read 4, iclass 3, count 0 2006.225.08:15:28.54#ibcon#read 4, iclass 3, count 0 2006.225.08:15:28.54#ibcon#about to read 5, iclass 3, count 0 2006.225.08:15:28.54#ibcon#read 5, iclass 3, count 0 2006.225.08:15:28.54#ibcon#about to read 6, iclass 3, count 0 2006.225.08:15:28.54#ibcon#read 6, iclass 3, count 0 2006.225.08:15:28.54#ibcon#end of sib2, iclass 3, count 0 2006.225.08:15:28.54#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:15:28.54#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:15:28.54#ibcon#[25=USB\r\n] 2006.225.08:15:28.54#ibcon#*before write, iclass 3, count 0 2006.225.08:15:28.54#ibcon#enter sib2, iclass 3, count 0 2006.225.08:15:28.54#ibcon#flushed, iclass 3, count 0 2006.225.08:15:28.54#ibcon#about to write, iclass 3, count 0 2006.225.08:15:28.54#ibcon#wrote, iclass 3, count 0 2006.225.08:15:28.54#ibcon#about to read 3, iclass 3, count 0 2006.225.08:15:28.57#ibcon#read 3, iclass 3, count 0 2006.225.08:15:28.57#ibcon#about to read 4, iclass 3, count 0 2006.225.08:15:28.57#ibcon#read 4, iclass 3, count 0 2006.225.08:15:28.57#ibcon#about to read 5, iclass 3, count 0 2006.225.08:15:28.57#ibcon#read 5, iclass 3, count 0 2006.225.08:15:28.57#ibcon#about to read 6, iclass 3, count 0 2006.225.08:15:28.57#ibcon#read 6, iclass 3, count 0 2006.225.08:15:28.57#ibcon#end of sib2, iclass 3, count 0 2006.225.08:15:28.57#ibcon#*after write, iclass 3, count 0 2006.225.08:15:28.57#ibcon#*before return 0, iclass 3, count 0 2006.225.08:15:28.57#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:15:28.57#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:15:28.57#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:15:28.57#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:15:28.57$vc4f8/valo=3,672.99 2006.225.08:15:28.57#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.08:15:28.57#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.08:15:28.57#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:28.57#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:15:28.57#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:15:28.57#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:15:28.57#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:15:28.57#ibcon#first serial, iclass 5, count 0 2006.225.08:15:28.57#ibcon#enter sib2, iclass 5, count 0 2006.225.08:15:28.57#ibcon#flushed, iclass 5, count 0 2006.225.08:15:28.57#ibcon#about to write, iclass 5, count 0 2006.225.08:15:28.57#ibcon#wrote, iclass 5, count 0 2006.225.08:15:28.57#ibcon#about to read 3, iclass 5, count 0 2006.225.08:15:28.59#ibcon#read 3, iclass 5, count 0 2006.225.08:15:28.59#ibcon#about to read 4, iclass 5, count 0 2006.225.08:15:28.59#ibcon#read 4, iclass 5, count 0 2006.225.08:15:28.59#ibcon#about to read 5, iclass 5, count 0 2006.225.08:15:28.59#ibcon#read 5, iclass 5, count 0 2006.225.08:15:28.59#ibcon#about to read 6, iclass 5, count 0 2006.225.08:15:28.59#ibcon#read 6, iclass 5, count 0 2006.225.08:15:28.59#ibcon#end of sib2, iclass 5, count 0 2006.225.08:15:28.59#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:15:28.59#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:15:28.59#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:15:28.59#ibcon#*before write, iclass 5, count 0 2006.225.08:15:28.59#ibcon#enter sib2, iclass 5, count 0 2006.225.08:15:28.59#ibcon#flushed, iclass 5, count 0 2006.225.08:15:28.59#ibcon#about to write, iclass 5, count 0 2006.225.08:15:28.59#ibcon#wrote, iclass 5, count 0 2006.225.08:15:28.59#ibcon#about to read 3, iclass 5, count 0 2006.225.08:15:28.63#ibcon#read 3, iclass 5, count 0 2006.225.08:15:28.63#ibcon#about to read 4, iclass 5, count 0 2006.225.08:15:28.63#ibcon#read 4, iclass 5, count 0 2006.225.08:15:28.63#ibcon#about to read 5, iclass 5, count 0 2006.225.08:15:28.63#ibcon#read 5, iclass 5, count 0 2006.225.08:15:28.63#ibcon#about to read 6, iclass 5, count 0 2006.225.08:15:28.63#ibcon#read 6, iclass 5, count 0 2006.225.08:15:28.63#ibcon#end of sib2, iclass 5, count 0 2006.225.08:15:28.63#ibcon#*after write, iclass 5, count 0 2006.225.08:15:28.63#ibcon#*before return 0, iclass 5, count 0 2006.225.08:15:28.63#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:15:28.63#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:15:28.63#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:15:28.63#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:15:28.63$vc4f8/va=3,6 2006.225.08:15:28.63#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.08:15:28.63#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.08:15:28.63#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:28.63#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:15:28.69#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:15:28.69#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:15:28.69#ibcon#enter wrdev, iclass 7, count 2 2006.225.08:15:28.69#ibcon#first serial, iclass 7, count 2 2006.225.08:15:28.69#ibcon#enter sib2, iclass 7, count 2 2006.225.08:15:28.69#ibcon#flushed, iclass 7, count 2 2006.225.08:15:28.69#ibcon#about to write, iclass 7, count 2 2006.225.08:15:28.69#ibcon#wrote, iclass 7, count 2 2006.225.08:15:28.69#ibcon#about to read 3, iclass 7, count 2 2006.225.08:15:28.72#ibcon#read 3, iclass 7, count 2 2006.225.08:15:28.72#ibcon#about to read 4, iclass 7, count 2 2006.225.08:15:28.72#ibcon#read 4, iclass 7, count 2 2006.225.08:15:28.72#ibcon#about to read 5, iclass 7, count 2 2006.225.08:15:28.72#ibcon#read 5, iclass 7, count 2 2006.225.08:15:28.72#ibcon#about to read 6, iclass 7, count 2 2006.225.08:15:28.72#ibcon#read 6, iclass 7, count 2 2006.225.08:15:28.72#ibcon#end of sib2, iclass 7, count 2 2006.225.08:15:28.72#ibcon#*mode == 0, iclass 7, count 2 2006.225.08:15:28.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.08:15:28.72#ibcon#[25=AT03-06\r\n] 2006.225.08:15:28.72#ibcon#*before write, iclass 7, count 2 2006.225.08:15:28.72#ibcon#enter sib2, iclass 7, count 2 2006.225.08:15:28.72#ibcon#flushed, iclass 7, count 2 2006.225.08:15:28.72#ibcon#about to write, iclass 7, count 2 2006.225.08:15:28.72#ibcon#wrote, iclass 7, count 2 2006.225.08:15:28.72#ibcon#about to read 3, iclass 7, count 2 2006.225.08:15:28.75#ibcon#read 3, iclass 7, count 2 2006.225.08:15:28.75#ibcon#about to read 4, iclass 7, count 2 2006.225.08:15:28.75#ibcon#read 4, iclass 7, count 2 2006.225.08:15:28.75#ibcon#about to read 5, iclass 7, count 2 2006.225.08:15:28.75#ibcon#read 5, iclass 7, count 2 2006.225.08:15:28.75#ibcon#about to read 6, iclass 7, count 2 2006.225.08:15:28.75#ibcon#read 6, iclass 7, count 2 2006.225.08:15:28.75#ibcon#end of sib2, iclass 7, count 2 2006.225.08:15:28.75#ibcon#*after write, iclass 7, count 2 2006.225.08:15:28.75#ibcon#*before return 0, iclass 7, count 2 2006.225.08:15:28.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:15:28.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:15:28.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.08:15:28.75#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:28.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:15:28.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:15:28.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:15:28.87#ibcon#enter wrdev, iclass 7, count 0 2006.225.08:15:28.87#ibcon#first serial, iclass 7, count 0 2006.225.08:15:28.87#ibcon#enter sib2, iclass 7, count 0 2006.225.08:15:28.87#ibcon#flushed, iclass 7, count 0 2006.225.08:15:28.87#ibcon#about to write, iclass 7, count 0 2006.225.08:15:28.87#ibcon#wrote, iclass 7, count 0 2006.225.08:15:28.87#ibcon#about to read 3, iclass 7, count 0 2006.225.08:15:28.89#ibcon#read 3, iclass 7, count 0 2006.225.08:15:28.89#ibcon#about to read 4, iclass 7, count 0 2006.225.08:15:28.89#ibcon#read 4, iclass 7, count 0 2006.225.08:15:28.89#ibcon#about to read 5, iclass 7, count 0 2006.225.08:15:28.89#ibcon#read 5, iclass 7, count 0 2006.225.08:15:28.89#ibcon#about to read 6, iclass 7, count 0 2006.225.08:15:28.89#ibcon#read 6, iclass 7, count 0 2006.225.08:15:28.89#ibcon#end of sib2, iclass 7, count 0 2006.225.08:15:28.89#ibcon#*mode == 0, iclass 7, count 0 2006.225.08:15:28.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.08:15:28.89#ibcon#[25=USB\r\n] 2006.225.08:15:28.89#ibcon#*before write, iclass 7, count 0 2006.225.08:15:28.89#ibcon#enter sib2, iclass 7, count 0 2006.225.08:15:28.89#ibcon#flushed, iclass 7, count 0 2006.225.08:15:28.89#ibcon#about to write, iclass 7, count 0 2006.225.08:15:28.89#ibcon#wrote, iclass 7, count 0 2006.225.08:15:28.89#ibcon#about to read 3, iclass 7, count 0 2006.225.08:15:28.92#ibcon#read 3, iclass 7, count 0 2006.225.08:15:28.92#ibcon#about to read 4, iclass 7, count 0 2006.225.08:15:28.92#ibcon#read 4, iclass 7, count 0 2006.225.08:15:28.92#ibcon#about to read 5, iclass 7, count 0 2006.225.08:15:28.92#ibcon#read 5, iclass 7, count 0 2006.225.08:15:28.92#ibcon#about to read 6, iclass 7, count 0 2006.225.08:15:28.92#ibcon#read 6, iclass 7, count 0 2006.225.08:15:28.92#ibcon#end of sib2, iclass 7, count 0 2006.225.08:15:28.92#ibcon#*after write, iclass 7, count 0 2006.225.08:15:28.92#ibcon#*before return 0, iclass 7, count 0 2006.225.08:15:28.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:15:28.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:15:28.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.08:15:28.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.08:15:28.92$vc4f8/valo=4,832.99 2006.225.08:15:28.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.08:15:28.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.08:15:28.92#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:28.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:15:28.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:15:28.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:15:28.92#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:15:28.92#ibcon#first serial, iclass 11, count 0 2006.225.08:15:28.92#ibcon#enter sib2, iclass 11, count 0 2006.225.08:15:28.92#ibcon#flushed, iclass 11, count 0 2006.225.08:15:28.92#ibcon#about to write, iclass 11, count 0 2006.225.08:15:28.92#ibcon#wrote, iclass 11, count 0 2006.225.08:15:28.92#ibcon#about to read 3, iclass 11, count 0 2006.225.08:15:28.94#ibcon#read 3, iclass 11, count 0 2006.225.08:15:28.94#ibcon#about to read 4, iclass 11, count 0 2006.225.08:15:28.94#ibcon#read 4, iclass 11, count 0 2006.225.08:15:28.94#ibcon#about to read 5, iclass 11, count 0 2006.225.08:15:28.94#ibcon#read 5, iclass 11, count 0 2006.225.08:15:28.94#ibcon#about to read 6, iclass 11, count 0 2006.225.08:15:28.94#ibcon#read 6, iclass 11, count 0 2006.225.08:15:28.94#ibcon#end of sib2, iclass 11, count 0 2006.225.08:15:28.94#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:15:28.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:15:28.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:15:28.94#ibcon#*before write, iclass 11, count 0 2006.225.08:15:28.94#ibcon#enter sib2, iclass 11, count 0 2006.225.08:15:28.94#ibcon#flushed, iclass 11, count 0 2006.225.08:15:28.94#ibcon#about to write, iclass 11, count 0 2006.225.08:15:28.94#ibcon#wrote, iclass 11, count 0 2006.225.08:15:28.94#ibcon#about to read 3, iclass 11, count 0 2006.225.08:15:28.98#ibcon#read 3, iclass 11, count 0 2006.225.08:15:28.98#ibcon#about to read 4, iclass 11, count 0 2006.225.08:15:28.98#ibcon#read 4, iclass 11, count 0 2006.225.08:15:28.98#ibcon#about to read 5, iclass 11, count 0 2006.225.08:15:28.98#ibcon#read 5, iclass 11, count 0 2006.225.08:15:28.98#ibcon#about to read 6, iclass 11, count 0 2006.225.08:15:28.98#ibcon#read 6, iclass 11, count 0 2006.225.08:15:28.98#ibcon#end of sib2, iclass 11, count 0 2006.225.08:15:28.98#ibcon#*after write, iclass 11, count 0 2006.225.08:15:28.98#ibcon#*before return 0, iclass 11, count 0 2006.225.08:15:28.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:15:28.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:15:28.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:15:28.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:15:28.98$vc4f8/va=4,7 2006.225.08:15:28.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.08:15:28.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.08:15:28.98#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:28.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:15:29.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:15:29.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:15:29.04#ibcon#enter wrdev, iclass 13, count 2 2006.225.08:15:29.04#ibcon#first serial, iclass 13, count 2 2006.225.08:15:29.04#ibcon#enter sib2, iclass 13, count 2 2006.225.08:15:29.04#ibcon#flushed, iclass 13, count 2 2006.225.08:15:29.04#ibcon#about to write, iclass 13, count 2 2006.225.08:15:29.04#ibcon#wrote, iclass 13, count 2 2006.225.08:15:29.04#ibcon#about to read 3, iclass 13, count 2 2006.225.08:15:29.06#ibcon#read 3, iclass 13, count 2 2006.225.08:15:29.06#ibcon#about to read 4, iclass 13, count 2 2006.225.08:15:29.06#ibcon#read 4, iclass 13, count 2 2006.225.08:15:29.06#ibcon#about to read 5, iclass 13, count 2 2006.225.08:15:29.06#ibcon#read 5, iclass 13, count 2 2006.225.08:15:29.06#ibcon#about to read 6, iclass 13, count 2 2006.225.08:15:29.06#ibcon#read 6, iclass 13, count 2 2006.225.08:15:29.06#ibcon#end of sib2, iclass 13, count 2 2006.225.08:15:29.06#ibcon#*mode == 0, iclass 13, count 2 2006.225.08:15:29.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.08:15:29.06#ibcon#[25=AT04-07\r\n] 2006.225.08:15:29.06#ibcon#*before write, iclass 13, count 2 2006.225.08:15:29.06#ibcon#enter sib2, iclass 13, count 2 2006.225.08:15:29.06#ibcon#flushed, iclass 13, count 2 2006.225.08:15:29.06#ibcon#about to write, iclass 13, count 2 2006.225.08:15:29.06#ibcon#wrote, iclass 13, count 2 2006.225.08:15:29.06#ibcon#about to read 3, iclass 13, count 2 2006.225.08:15:29.09#ibcon#read 3, iclass 13, count 2 2006.225.08:15:29.09#ibcon#about to read 4, iclass 13, count 2 2006.225.08:15:29.09#ibcon#read 4, iclass 13, count 2 2006.225.08:15:29.09#ibcon#about to read 5, iclass 13, count 2 2006.225.08:15:29.09#ibcon#read 5, iclass 13, count 2 2006.225.08:15:29.09#ibcon#about to read 6, iclass 13, count 2 2006.225.08:15:29.09#ibcon#read 6, iclass 13, count 2 2006.225.08:15:29.09#ibcon#end of sib2, iclass 13, count 2 2006.225.08:15:29.09#ibcon#*after write, iclass 13, count 2 2006.225.08:15:29.09#ibcon#*before return 0, iclass 13, count 2 2006.225.08:15:29.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:15:29.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:15:29.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.08:15:29.09#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:29.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:15:29.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:15:29.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:15:29.21#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:15:29.21#ibcon#first serial, iclass 13, count 0 2006.225.08:15:29.21#ibcon#enter sib2, iclass 13, count 0 2006.225.08:15:29.21#ibcon#flushed, iclass 13, count 0 2006.225.08:15:29.21#ibcon#about to write, iclass 13, count 0 2006.225.08:15:29.21#ibcon#wrote, iclass 13, count 0 2006.225.08:15:29.21#ibcon#about to read 3, iclass 13, count 0 2006.225.08:15:29.23#ibcon#read 3, iclass 13, count 0 2006.225.08:15:29.23#ibcon#about to read 4, iclass 13, count 0 2006.225.08:15:29.23#ibcon#read 4, iclass 13, count 0 2006.225.08:15:29.23#ibcon#about to read 5, iclass 13, count 0 2006.225.08:15:29.23#ibcon#read 5, iclass 13, count 0 2006.225.08:15:29.23#ibcon#about to read 6, iclass 13, count 0 2006.225.08:15:29.23#ibcon#read 6, iclass 13, count 0 2006.225.08:15:29.23#ibcon#end of sib2, iclass 13, count 0 2006.225.08:15:29.23#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:15:29.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:15:29.23#ibcon#[25=USB\r\n] 2006.225.08:15:29.23#ibcon#*before write, iclass 13, count 0 2006.225.08:15:29.23#ibcon#enter sib2, iclass 13, count 0 2006.225.08:15:29.23#ibcon#flushed, iclass 13, count 0 2006.225.08:15:29.23#ibcon#about to write, iclass 13, count 0 2006.225.08:15:29.23#ibcon#wrote, iclass 13, count 0 2006.225.08:15:29.23#ibcon#about to read 3, iclass 13, count 0 2006.225.08:15:29.26#ibcon#read 3, iclass 13, count 0 2006.225.08:15:29.26#ibcon#about to read 4, iclass 13, count 0 2006.225.08:15:29.26#ibcon#read 4, iclass 13, count 0 2006.225.08:15:29.26#ibcon#about to read 5, iclass 13, count 0 2006.225.08:15:29.26#ibcon#read 5, iclass 13, count 0 2006.225.08:15:29.26#ibcon#about to read 6, iclass 13, count 0 2006.225.08:15:29.26#ibcon#read 6, iclass 13, count 0 2006.225.08:15:29.26#ibcon#end of sib2, iclass 13, count 0 2006.225.08:15:29.26#ibcon#*after write, iclass 13, count 0 2006.225.08:15:29.26#ibcon#*before return 0, iclass 13, count 0 2006.225.08:15:29.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:15:29.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:15:29.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:15:29.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:15:29.26$vc4f8/valo=5,652.99 2006.225.08:15:29.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.08:15:29.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.08:15:29.26#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:29.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:15:29.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:15:29.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:15:29.26#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:15:29.26#ibcon#first serial, iclass 15, count 0 2006.225.08:15:29.26#ibcon#enter sib2, iclass 15, count 0 2006.225.08:15:29.26#ibcon#flushed, iclass 15, count 0 2006.225.08:15:29.26#ibcon#about to write, iclass 15, count 0 2006.225.08:15:29.26#ibcon#wrote, iclass 15, count 0 2006.225.08:15:29.26#ibcon#about to read 3, iclass 15, count 0 2006.225.08:15:29.28#ibcon#read 3, iclass 15, count 0 2006.225.08:15:29.28#ibcon#about to read 4, iclass 15, count 0 2006.225.08:15:29.28#ibcon#read 4, iclass 15, count 0 2006.225.08:15:29.28#ibcon#about to read 5, iclass 15, count 0 2006.225.08:15:29.28#ibcon#read 5, iclass 15, count 0 2006.225.08:15:29.28#ibcon#about to read 6, iclass 15, count 0 2006.225.08:15:29.28#ibcon#read 6, iclass 15, count 0 2006.225.08:15:29.28#ibcon#end of sib2, iclass 15, count 0 2006.225.08:15:29.28#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:15:29.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:15:29.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:15:29.28#ibcon#*before write, iclass 15, count 0 2006.225.08:15:29.28#ibcon#enter sib2, iclass 15, count 0 2006.225.08:15:29.28#ibcon#flushed, iclass 15, count 0 2006.225.08:15:29.28#ibcon#about to write, iclass 15, count 0 2006.225.08:15:29.28#ibcon#wrote, iclass 15, count 0 2006.225.08:15:29.28#ibcon#about to read 3, iclass 15, count 0 2006.225.08:15:29.32#ibcon#read 3, iclass 15, count 0 2006.225.08:15:29.32#ibcon#about to read 4, iclass 15, count 0 2006.225.08:15:29.32#ibcon#read 4, iclass 15, count 0 2006.225.08:15:29.32#ibcon#about to read 5, iclass 15, count 0 2006.225.08:15:29.32#ibcon#read 5, iclass 15, count 0 2006.225.08:15:29.32#ibcon#about to read 6, iclass 15, count 0 2006.225.08:15:29.32#ibcon#read 6, iclass 15, count 0 2006.225.08:15:29.32#ibcon#end of sib2, iclass 15, count 0 2006.225.08:15:29.32#ibcon#*after write, iclass 15, count 0 2006.225.08:15:29.32#ibcon#*before return 0, iclass 15, count 0 2006.225.08:15:29.32#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:15:29.32#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:15:29.32#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:15:29.32#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:15:29.32$vc4f8/va=5,7 2006.225.08:15:29.32#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.08:15:29.32#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.08:15:29.32#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:29.32#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:15:29.38#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:15:29.38#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:15:29.38#ibcon#enter wrdev, iclass 17, count 2 2006.225.08:15:29.38#ibcon#first serial, iclass 17, count 2 2006.225.08:15:29.38#ibcon#enter sib2, iclass 17, count 2 2006.225.08:15:29.38#ibcon#flushed, iclass 17, count 2 2006.225.08:15:29.38#ibcon#about to write, iclass 17, count 2 2006.225.08:15:29.38#ibcon#wrote, iclass 17, count 2 2006.225.08:15:29.38#ibcon#about to read 3, iclass 17, count 2 2006.225.08:15:29.40#ibcon#read 3, iclass 17, count 2 2006.225.08:15:29.40#ibcon#about to read 4, iclass 17, count 2 2006.225.08:15:29.40#ibcon#read 4, iclass 17, count 2 2006.225.08:15:29.40#ibcon#about to read 5, iclass 17, count 2 2006.225.08:15:29.40#ibcon#read 5, iclass 17, count 2 2006.225.08:15:29.40#ibcon#about to read 6, iclass 17, count 2 2006.225.08:15:29.40#ibcon#read 6, iclass 17, count 2 2006.225.08:15:29.40#ibcon#end of sib2, iclass 17, count 2 2006.225.08:15:29.40#ibcon#*mode == 0, iclass 17, count 2 2006.225.08:15:29.40#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.08:15:29.40#ibcon#[25=AT05-07\r\n] 2006.225.08:15:29.40#ibcon#*before write, iclass 17, count 2 2006.225.08:15:29.40#ibcon#enter sib2, iclass 17, count 2 2006.225.08:15:29.40#ibcon#flushed, iclass 17, count 2 2006.225.08:15:29.40#ibcon#about to write, iclass 17, count 2 2006.225.08:15:29.40#ibcon#wrote, iclass 17, count 2 2006.225.08:15:29.40#ibcon#about to read 3, iclass 17, count 2 2006.225.08:15:29.43#ibcon#read 3, iclass 17, count 2 2006.225.08:15:29.43#ibcon#about to read 4, iclass 17, count 2 2006.225.08:15:29.43#ibcon#read 4, iclass 17, count 2 2006.225.08:15:29.43#ibcon#about to read 5, iclass 17, count 2 2006.225.08:15:29.43#ibcon#read 5, iclass 17, count 2 2006.225.08:15:29.43#ibcon#about to read 6, iclass 17, count 2 2006.225.08:15:29.43#ibcon#read 6, iclass 17, count 2 2006.225.08:15:29.43#ibcon#end of sib2, iclass 17, count 2 2006.225.08:15:29.43#ibcon#*after write, iclass 17, count 2 2006.225.08:15:29.43#ibcon#*before return 0, iclass 17, count 2 2006.225.08:15:29.43#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:15:29.43#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:15:29.43#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.08:15:29.43#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:29.43#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:15:29.55#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:15:29.55#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:15:29.55#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:15:29.55#ibcon#first serial, iclass 17, count 0 2006.225.08:15:29.55#ibcon#enter sib2, iclass 17, count 0 2006.225.08:15:29.55#ibcon#flushed, iclass 17, count 0 2006.225.08:15:29.55#ibcon#about to write, iclass 17, count 0 2006.225.08:15:29.55#ibcon#wrote, iclass 17, count 0 2006.225.08:15:29.55#ibcon#about to read 3, iclass 17, count 0 2006.225.08:15:29.57#ibcon#read 3, iclass 17, count 0 2006.225.08:15:29.57#ibcon#about to read 4, iclass 17, count 0 2006.225.08:15:29.57#ibcon#read 4, iclass 17, count 0 2006.225.08:15:29.57#ibcon#about to read 5, iclass 17, count 0 2006.225.08:15:29.57#ibcon#read 5, iclass 17, count 0 2006.225.08:15:29.57#ibcon#about to read 6, iclass 17, count 0 2006.225.08:15:29.57#ibcon#read 6, iclass 17, count 0 2006.225.08:15:29.57#ibcon#end of sib2, iclass 17, count 0 2006.225.08:15:29.57#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:15:29.57#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:15:29.57#ibcon#[25=USB\r\n] 2006.225.08:15:29.57#ibcon#*before write, iclass 17, count 0 2006.225.08:15:29.57#ibcon#enter sib2, iclass 17, count 0 2006.225.08:15:29.57#ibcon#flushed, iclass 17, count 0 2006.225.08:15:29.57#ibcon#about to write, iclass 17, count 0 2006.225.08:15:29.57#ibcon#wrote, iclass 17, count 0 2006.225.08:15:29.57#ibcon#about to read 3, iclass 17, count 0 2006.225.08:15:29.60#ibcon#read 3, iclass 17, count 0 2006.225.08:15:29.60#ibcon#about to read 4, iclass 17, count 0 2006.225.08:15:29.60#ibcon#read 4, iclass 17, count 0 2006.225.08:15:29.60#ibcon#about to read 5, iclass 17, count 0 2006.225.08:15:29.60#ibcon#read 5, iclass 17, count 0 2006.225.08:15:29.60#ibcon#about to read 6, iclass 17, count 0 2006.225.08:15:29.60#ibcon#read 6, iclass 17, count 0 2006.225.08:15:29.60#ibcon#end of sib2, iclass 17, count 0 2006.225.08:15:29.60#ibcon#*after write, iclass 17, count 0 2006.225.08:15:29.60#ibcon#*before return 0, iclass 17, count 0 2006.225.08:15:29.60#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:15:29.60#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:15:29.60#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:15:29.60#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:15:29.60$vc4f8/valo=6,772.99 2006.225.08:15:29.60#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.08:15:29.60#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.08:15:29.60#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:29.60#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:15:29.60#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:15:29.60#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:15:29.60#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:15:29.60#ibcon#first serial, iclass 19, count 0 2006.225.08:15:29.60#ibcon#enter sib2, iclass 19, count 0 2006.225.08:15:29.60#ibcon#flushed, iclass 19, count 0 2006.225.08:15:29.60#ibcon#about to write, iclass 19, count 0 2006.225.08:15:29.60#ibcon#wrote, iclass 19, count 0 2006.225.08:15:29.60#ibcon#about to read 3, iclass 19, count 0 2006.225.08:15:29.62#ibcon#read 3, iclass 19, count 0 2006.225.08:15:29.62#ibcon#about to read 4, iclass 19, count 0 2006.225.08:15:29.62#ibcon#read 4, iclass 19, count 0 2006.225.08:15:29.62#ibcon#about to read 5, iclass 19, count 0 2006.225.08:15:29.62#ibcon#read 5, iclass 19, count 0 2006.225.08:15:29.62#ibcon#about to read 6, iclass 19, count 0 2006.225.08:15:29.62#ibcon#read 6, iclass 19, count 0 2006.225.08:15:29.62#ibcon#end of sib2, iclass 19, count 0 2006.225.08:15:29.62#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:15:29.62#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:15:29.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:15:29.62#ibcon#*before write, iclass 19, count 0 2006.225.08:15:29.62#ibcon#enter sib2, iclass 19, count 0 2006.225.08:15:29.62#ibcon#flushed, iclass 19, count 0 2006.225.08:15:29.62#ibcon#about to write, iclass 19, count 0 2006.225.08:15:29.62#ibcon#wrote, iclass 19, count 0 2006.225.08:15:29.62#ibcon#about to read 3, iclass 19, count 0 2006.225.08:15:29.66#ibcon#read 3, iclass 19, count 0 2006.225.08:15:29.66#ibcon#about to read 4, iclass 19, count 0 2006.225.08:15:29.66#ibcon#read 4, iclass 19, count 0 2006.225.08:15:29.66#ibcon#about to read 5, iclass 19, count 0 2006.225.08:15:29.66#ibcon#read 5, iclass 19, count 0 2006.225.08:15:29.66#ibcon#about to read 6, iclass 19, count 0 2006.225.08:15:29.66#ibcon#read 6, iclass 19, count 0 2006.225.08:15:29.66#ibcon#end of sib2, iclass 19, count 0 2006.225.08:15:29.66#ibcon#*after write, iclass 19, count 0 2006.225.08:15:29.66#ibcon#*before return 0, iclass 19, count 0 2006.225.08:15:29.66#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:15:29.66#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:15:29.66#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:15:29.66#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:15:29.66$vc4f8/va=6,6 2006.225.08:15:29.66#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.225.08:15:29.66#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.225.08:15:29.66#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:29.66#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:15:29.73#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:15:29.73#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:15:29.73#ibcon#enter wrdev, iclass 21, count 2 2006.225.08:15:29.73#ibcon#first serial, iclass 21, count 2 2006.225.08:15:29.73#ibcon#enter sib2, iclass 21, count 2 2006.225.08:15:29.73#ibcon#flushed, iclass 21, count 2 2006.225.08:15:29.73#ibcon#about to write, iclass 21, count 2 2006.225.08:15:29.73#ibcon#wrote, iclass 21, count 2 2006.225.08:15:29.73#ibcon#about to read 3, iclass 21, count 2 2006.225.08:15:29.74#ibcon#read 3, iclass 21, count 2 2006.225.08:15:29.74#ibcon#about to read 4, iclass 21, count 2 2006.225.08:15:29.74#ibcon#read 4, iclass 21, count 2 2006.225.08:15:29.74#ibcon#about to read 5, iclass 21, count 2 2006.225.08:15:29.74#ibcon#read 5, iclass 21, count 2 2006.225.08:15:29.74#ibcon#about to read 6, iclass 21, count 2 2006.225.08:15:29.74#ibcon#read 6, iclass 21, count 2 2006.225.08:15:29.74#ibcon#end of sib2, iclass 21, count 2 2006.225.08:15:29.74#ibcon#*mode == 0, iclass 21, count 2 2006.225.08:15:29.74#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.225.08:15:29.74#ibcon#[25=AT06-06\r\n] 2006.225.08:15:29.74#ibcon#*before write, iclass 21, count 2 2006.225.08:15:29.74#ibcon#enter sib2, iclass 21, count 2 2006.225.08:15:29.74#ibcon#flushed, iclass 21, count 2 2006.225.08:15:29.74#ibcon#about to write, iclass 21, count 2 2006.225.08:15:29.74#ibcon#wrote, iclass 21, count 2 2006.225.08:15:29.74#ibcon#about to read 3, iclass 21, count 2 2006.225.08:15:29.77#ibcon#read 3, iclass 21, count 2 2006.225.08:15:29.77#ibcon#about to read 4, iclass 21, count 2 2006.225.08:15:29.77#ibcon#read 4, iclass 21, count 2 2006.225.08:15:29.77#ibcon#about to read 5, iclass 21, count 2 2006.225.08:15:29.77#ibcon#read 5, iclass 21, count 2 2006.225.08:15:29.77#ibcon#about to read 6, iclass 21, count 2 2006.225.08:15:29.77#ibcon#read 6, iclass 21, count 2 2006.225.08:15:29.77#ibcon#end of sib2, iclass 21, count 2 2006.225.08:15:29.77#ibcon#*after write, iclass 21, count 2 2006.225.08:15:29.77#ibcon#*before return 0, iclass 21, count 2 2006.225.08:15:29.77#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:15:29.77#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:15:29.77#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.225.08:15:29.77#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:29.77#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:15:29.89#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:15:29.89#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:15:29.89#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:15:29.89#ibcon#first serial, iclass 21, count 0 2006.225.08:15:29.89#ibcon#enter sib2, iclass 21, count 0 2006.225.08:15:29.89#ibcon#flushed, iclass 21, count 0 2006.225.08:15:29.89#ibcon#about to write, iclass 21, count 0 2006.225.08:15:29.89#ibcon#wrote, iclass 21, count 0 2006.225.08:15:29.89#ibcon#about to read 3, iclass 21, count 0 2006.225.08:15:29.91#ibcon#read 3, iclass 21, count 0 2006.225.08:15:29.91#ibcon#about to read 4, iclass 21, count 0 2006.225.08:15:29.91#ibcon#read 4, iclass 21, count 0 2006.225.08:15:29.91#ibcon#about to read 5, iclass 21, count 0 2006.225.08:15:29.91#ibcon#read 5, iclass 21, count 0 2006.225.08:15:29.91#ibcon#about to read 6, iclass 21, count 0 2006.225.08:15:29.91#ibcon#read 6, iclass 21, count 0 2006.225.08:15:29.91#ibcon#end of sib2, iclass 21, count 0 2006.225.08:15:29.91#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:15:29.91#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:15:29.91#ibcon#[25=USB\r\n] 2006.225.08:15:29.91#ibcon#*before write, iclass 21, count 0 2006.225.08:15:29.91#ibcon#enter sib2, iclass 21, count 0 2006.225.08:15:29.91#ibcon#flushed, iclass 21, count 0 2006.225.08:15:29.91#ibcon#about to write, iclass 21, count 0 2006.225.08:15:29.91#ibcon#wrote, iclass 21, count 0 2006.225.08:15:29.91#ibcon#about to read 3, iclass 21, count 0 2006.225.08:15:29.94#ibcon#read 3, iclass 21, count 0 2006.225.08:15:29.94#ibcon#about to read 4, iclass 21, count 0 2006.225.08:15:29.94#ibcon#read 4, iclass 21, count 0 2006.225.08:15:29.94#ibcon#about to read 5, iclass 21, count 0 2006.225.08:15:29.94#ibcon#read 5, iclass 21, count 0 2006.225.08:15:29.94#ibcon#about to read 6, iclass 21, count 0 2006.225.08:15:29.94#ibcon#read 6, iclass 21, count 0 2006.225.08:15:29.94#ibcon#end of sib2, iclass 21, count 0 2006.225.08:15:29.94#ibcon#*after write, iclass 21, count 0 2006.225.08:15:29.94#ibcon#*before return 0, iclass 21, count 0 2006.225.08:15:29.94#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:15:29.94#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:15:29.94#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:15:29.94#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:15:29.94$vc4f8/valo=7,832.99 2006.225.08:15:29.94#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.225.08:15:29.94#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.225.08:15:29.94#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:29.94#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:15:29.94#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:15:29.94#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:15:29.94#ibcon#enter wrdev, iclass 23, count 0 2006.225.08:15:29.94#ibcon#first serial, iclass 23, count 0 2006.225.08:15:29.94#ibcon#enter sib2, iclass 23, count 0 2006.225.08:15:29.94#ibcon#flushed, iclass 23, count 0 2006.225.08:15:29.94#ibcon#about to write, iclass 23, count 0 2006.225.08:15:29.94#ibcon#wrote, iclass 23, count 0 2006.225.08:15:29.94#ibcon#about to read 3, iclass 23, count 0 2006.225.08:15:29.96#ibcon#read 3, iclass 23, count 0 2006.225.08:15:29.96#ibcon#about to read 4, iclass 23, count 0 2006.225.08:15:29.96#ibcon#read 4, iclass 23, count 0 2006.225.08:15:29.96#ibcon#about to read 5, iclass 23, count 0 2006.225.08:15:29.96#ibcon#read 5, iclass 23, count 0 2006.225.08:15:29.96#ibcon#about to read 6, iclass 23, count 0 2006.225.08:15:29.96#ibcon#read 6, iclass 23, count 0 2006.225.08:15:29.96#ibcon#end of sib2, iclass 23, count 0 2006.225.08:15:29.96#ibcon#*mode == 0, iclass 23, count 0 2006.225.08:15:29.96#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.08:15:29.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:15:29.96#ibcon#*before write, iclass 23, count 0 2006.225.08:15:29.96#ibcon#enter sib2, iclass 23, count 0 2006.225.08:15:29.96#ibcon#flushed, iclass 23, count 0 2006.225.08:15:29.96#ibcon#about to write, iclass 23, count 0 2006.225.08:15:29.96#ibcon#wrote, iclass 23, count 0 2006.225.08:15:29.96#ibcon#about to read 3, iclass 23, count 0 2006.225.08:15:30.00#ibcon#read 3, iclass 23, count 0 2006.225.08:15:30.00#ibcon#about to read 4, iclass 23, count 0 2006.225.08:15:30.00#ibcon#read 4, iclass 23, count 0 2006.225.08:15:30.00#ibcon#about to read 5, iclass 23, count 0 2006.225.08:15:30.00#ibcon#read 5, iclass 23, count 0 2006.225.08:15:30.00#ibcon#about to read 6, iclass 23, count 0 2006.225.08:15:30.00#ibcon#read 6, iclass 23, count 0 2006.225.08:15:30.00#ibcon#end of sib2, iclass 23, count 0 2006.225.08:15:30.00#ibcon#*after write, iclass 23, count 0 2006.225.08:15:30.00#ibcon#*before return 0, iclass 23, count 0 2006.225.08:15:30.00#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:15:30.00#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:15:30.00#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.08:15:30.00#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.08:15:30.00$vc4f8/va=7,6 2006.225.08:15:30.00#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.225.08:15:30.00#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.225.08:15:30.00#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:30.00#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:15:30.06#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:15:30.06#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:15:30.06#ibcon#enter wrdev, iclass 25, count 2 2006.225.08:15:30.06#ibcon#first serial, iclass 25, count 2 2006.225.08:15:30.06#ibcon#enter sib2, iclass 25, count 2 2006.225.08:15:30.06#ibcon#flushed, iclass 25, count 2 2006.225.08:15:30.06#ibcon#about to write, iclass 25, count 2 2006.225.08:15:30.06#ibcon#wrote, iclass 25, count 2 2006.225.08:15:30.06#ibcon#about to read 3, iclass 25, count 2 2006.225.08:15:30.08#ibcon#read 3, iclass 25, count 2 2006.225.08:15:30.08#ibcon#about to read 4, iclass 25, count 2 2006.225.08:15:30.08#ibcon#read 4, iclass 25, count 2 2006.225.08:15:30.08#ibcon#about to read 5, iclass 25, count 2 2006.225.08:15:30.08#ibcon#read 5, iclass 25, count 2 2006.225.08:15:30.08#ibcon#about to read 6, iclass 25, count 2 2006.225.08:15:30.08#ibcon#read 6, iclass 25, count 2 2006.225.08:15:30.08#ibcon#end of sib2, iclass 25, count 2 2006.225.08:15:30.08#ibcon#*mode == 0, iclass 25, count 2 2006.225.08:15:30.08#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.225.08:15:30.08#ibcon#[25=AT07-06\r\n] 2006.225.08:15:30.08#ibcon#*before write, iclass 25, count 2 2006.225.08:15:30.08#ibcon#enter sib2, iclass 25, count 2 2006.225.08:15:30.08#ibcon#flushed, iclass 25, count 2 2006.225.08:15:30.08#ibcon#about to write, iclass 25, count 2 2006.225.08:15:30.08#ibcon#wrote, iclass 25, count 2 2006.225.08:15:30.08#ibcon#about to read 3, iclass 25, count 2 2006.225.08:15:30.11#ibcon#read 3, iclass 25, count 2 2006.225.08:15:30.11#ibcon#about to read 4, iclass 25, count 2 2006.225.08:15:30.11#ibcon#read 4, iclass 25, count 2 2006.225.08:15:30.11#ibcon#about to read 5, iclass 25, count 2 2006.225.08:15:30.11#ibcon#read 5, iclass 25, count 2 2006.225.08:15:30.11#ibcon#about to read 6, iclass 25, count 2 2006.225.08:15:30.11#ibcon#read 6, iclass 25, count 2 2006.225.08:15:30.11#ibcon#end of sib2, iclass 25, count 2 2006.225.08:15:30.11#ibcon#*after write, iclass 25, count 2 2006.225.08:15:30.11#ibcon#*before return 0, iclass 25, count 2 2006.225.08:15:30.11#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:15:30.11#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:15:30.11#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.225.08:15:30.11#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:30.11#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:15:30.23#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:15:30.23#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:15:30.23#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:15:30.23#ibcon#first serial, iclass 25, count 0 2006.225.08:15:30.23#ibcon#enter sib2, iclass 25, count 0 2006.225.08:15:30.23#ibcon#flushed, iclass 25, count 0 2006.225.08:15:30.23#ibcon#about to write, iclass 25, count 0 2006.225.08:15:30.23#ibcon#wrote, iclass 25, count 0 2006.225.08:15:30.23#ibcon#about to read 3, iclass 25, count 0 2006.225.08:15:30.25#ibcon#read 3, iclass 25, count 0 2006.225.08:15:30.25#ibcon#about to read 4, iclass 25, count 0 2006.225.08:15:30.25#ibcon#read 4, iclass 25, count 0 2006.225.08:15:30.25#ibcon#about to read 5, iclass 25, count 0 2006.225.08:15:30.25#ibcon#read 5, iclass 25, count 0 2006.225.08:15:30.25#ibcon#about to read 6, iclass 25, count 0 2006.225.08:15:30.25#ibcon#read 6, iclass 25, count 0 2006.225.08:15:30.25#ibcon#end of sib2, iclass 25, count 0 2006.225.08:15:30.25#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:15:30.25#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:15:30.25#ibcon#[25=USB\r\n] 2006.225.08:15:30.25#ibcon#*before write, iclass 25, count 0 2006.225.08:15:30.25#ibcon#enter sib2, iclass 25, count 0 2006.225.08:15:30.25#ibcon#flushed, iclass 25, count 0 2006.225.08:15:30.25#ibcon#about to write, iclass 25, count 0 2006.225.08:15:30.25#ibcon#wrote, iclass 25, count 0 2006.225.08:15:30.25#ibcon#about to read 3, iclass 25, count 0 2006.225.08:15:30.28#ibcon#read 3, iclass 25, count 0 2006.225.08:15:30.28#ibcon#about to read 4, iclass 25, count 0 2006.225.08:15:30.28#ibcon#read 4, iclass 25, count 0 2006.225.08:15:30.28#ibcon#about to read 5, iclass 25, count 0 2006.225.08:15:30.28#ibcon#read 5, iclass 25, count 0 2006.225.08:15:30.28#ibcon#about to read 6, iclass 25, count 0 2006.225.08:15:30.28#ibcon#read 6, iclass 25, count 0 2006.225.08:15:30.28#ibcon#end of sib2, iclass 25, count 0 2006.225.08:15:30.28#ibcon#*after write, iclass 25, count 0 2006.225.08:15:30.28#ibcon#*before return 0, iclass 25, count 0 2006.225.08:15:30.28#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:15:30.28#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:15:30.28#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:15:30.28#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:15:30.28$vc4f8/valo=8,852.99 2006.225.08:15:30.28#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.08:15:30.28#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.08:15:30.28#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:30.28#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:15:30.28#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:15:30.28#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:15:30.28#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:15:30.28#ibcon#first serial, iclass 27, count 0 2006.225.08:15:30.28#ibcon#enter sib2, iclass 27, count 0 2006.225.08:15:30.28#ibcon#flushed, iclass 27, count 0 2006.225.08:15:30.28#ibcon#about to write, iclass 27, count 0 2006.225.08:15:30.28#ibcon#wrote, iclass 27, count 0 2006.225.08:15:30.28#ibcon#about to read 3, iclass 27, count 0 2006.225.08:15:30.30#ibcon#read 3, iclass 27, count 0 2006.225.08:15:30.30#ibcon#about to read 4, iclass 27, count 0 2006.225.08:15:30.30#ibcon#read 4, iclass 27, count 0 2006.225.08:15:30.30#ibcon#about to read 5, iclass 27, count 0 2006.225.08:15:30.30#ibcon#read 5, iclass 27, count 0 2006.225.08:15:30.30#ibcon#about to read 6, iclass 27, count 0 2006.225.08:15:30.30#ibcon#read 6, iclass 27, count 0 2006.225.08:15:30.30#ibcon#end of sib2, iclass 27, count 0 2006.225.08:15:30.30#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:15:30.30#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:15:30.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:15:30.30#ibcon#*before write, iclass 27, count 0 2006.225.08:15:30.30#ibcon#enter sib2, iclass 27, count 0 2006.225.08:15:30.30#ibcon#flushed, iclass 27, count 0 2006.225.08:15:30.30#ibcon#about to write, iclass 27, count 0 2006.225.08:15:30.30#ibcon#wrote, iclass 27, count 0 2006.225.08:15:30.30#ibcon#about to read 3, iclass 27, count 0 2006.225.08:15:30.34#ibcon#read 3, iclass 27, count 0 2006.225.08:15:30.34#ibcon#about to read 4, iclass 27, count 0 2006.225.08:15:30.34#ibcon#read 4, iclass 27, count 0 2006.225.08:15:30.34#ibcon#about to read 5, iclass 27, count 0 2006.225.08:15:30.34#ibcon#read 5, iclass 27, count 0 2006.225.08:15:30.34#ibcon#about to read 6, iclass 27, count 0 2006.225.08:15:30.34#ibcon#read 6, iclass 27, count 0 2006.225.08:15:30.34#ibcon#end of sib2, iclass 27, count 0 2006.225.08:15:30.34#ibcon#*after write, iclass 27, count 0 2006.225.08:15:30.34#ibcon#*before return 0, iclass 27, count 0 2006.225.08:15:30.34#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:15:30.34#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:15:30.34#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:15:30.34#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:15:30.34$vc4f8/va=8,7 2006.225.08:15:30.34#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.225.08:15:30.34#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.225.08:15:30.34#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:30.34#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:15:30.40#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:15:30.40#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:15:30.40#ibcon#enter wrdev, iclass 29, count 2 2006.225.08:15:30.40#ibcon#first serial, iclass 29, count 2 2006.225.08:15:30.40#ibcon#enter sib2, iclass 29, count 2 2006.225.08:15:30.40#ibcon#flushed, iclass 29, count 2 2006.225.08:15:30.40#ibcon#about to write, iclass 29, count 2 2006.225.08:15:30.40#ibcon#wrote, iclass 29, count 2 2006.225.08:15:30.40#ibcon#about to read 3, iclass 29, count 2 2006.225.08:15:30.42#ibcon#read 3, iclass 29, count 2 2006.225.08:15:30.42#ibcon#about to read 4, iclass 29, count 2 2006.225.08:15:30.42#ibcon#read 4, iclass 29, count 2 2006.225.08:15:30.42#ibcon#about to read 5, iclass 29, count 2 2006.225.08:15:30.42#ibcon#read 5, iclass 29, count 2 2006.225.08:15:30.42#ibcon#about to read 6, iclass 29, count 2 2006.225.08:15:30.42#ibcon#read 6, iclass 29, count 2 2006.225.08:15:30.42#ibcon#end of sib2, iclass 29, count 2 2006.225.08:15:30.42#ibcon#*mode == 0, iclass 29, count 2 2006.225.08:15:30.42#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.225.08:15:30.42#ibcon#[25=AT08-07\r\n] 2006.225.08:15:30.42#ibcon#*before write, iclass 29, count 2 2006.225.08:15:30.42#ibcon#enter sib2, iclass 29, count 2 2006.225.08:15:30.42#ibcon#flushed, iclass 29, count 2 2006.225.08:15:30.42#ibcon#about to write, iclass 29, count 2 2006.225.08:15:30.42#ibcon#wrote, iclass 29, count 2 2006.225.08:15:30.42#ibcon#about to read 3, iclass 29, count 2 2006.225.08:15:30.45#ibcon#read 3, iclass 29, count 2 2006.225.08:15:30.45#ibcon#about to read 4, iclass 29, count 2 2006.225.08:15:30.45#ibcon#read 4, iclass 29, count 2 2006.225.08:15:30.45#ibcon#about to read 5, iclass 29, count 2 2006.225.08:15:30.45#ibcon#read 5, iclass 29, count 2 2006.225.08:15:30.45#ibcon#about to read 6, iclass 29, count 2 2006.225.08:15:30.45#ibcon#read 6, iclass 29, count 2 2006.225.08:15:30.45#ibcon#end of sib2, iclass 29, count 2 2006.225.08:15:30.45#ibcon#*after write, iclass 29, count 2 2006.225.08:15:30.45#ibcon#*before return 0, iclass 29, count 2 2006.225.08:15:30.45#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:15:30.45#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:15:30.45#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.225.08:15:30.45#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:30.45#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:15:30.57#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:15:30.57#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:15:30.57#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:15:30.57#ibcon#first serial, iclass 29, count 0 2006.225.08:15:30.57#ibcon#enter sib2, iclass 29, count 0 2006.225.08:15:30.57#ibcon#flushed, iclass 29, count 0 2006.225.08:15:30.57#ibcon#about to write, iclass 29, count 0 2006.225.08:15:30.57#ibcon#wrote, iclass 29, count 0 2006.225.08:15:30.57#ibcon#about to read 3, iclass 29, count 0 2006.225.08:15:30.59#ibcon#read 3, iclass 29, count 0 2006.225.08:15:30.59#ibcon#about to read 4, iclass 29, count 0 2006.225.08:15:30.59#ibcon#read 4, iclass 29, count 0 2006.225.08:15:30.59#ibcon#about to read 5, iclass 29, count 0 2006.225.08:15:30.59#ibcon#read 5, iclass 29, count 0 2006.225.08:15:30.59#ibcon#about to read 6, iclass 29, count 0 2006.225.08:15:30.59#ibcon#read 6, iclass 29, count 0 2006.225.08:15:30.59#ibcon#end of sib2, iclass 29, count 0 2006.225.08:15:30.59#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:15:30.59#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:15:30.59#ibcon#[25=USB\r\n] 2006.225.08:15:30.59#ibcon#*before write, iclass 29, count 0 2006.225.08:15:30.59#ibcon#enter sib2, iclass 29, count 0 2006.225.08:15:30.59#ibcon#flushed, iclass 29, count 0 2006.225.08:15:30.59#ibcon#about to write, iclass 29, count 0 2006.225.08:15:30.59#ibcon#wrote, iclass 29, count 0 2006.225.08:15:30.59#ibcon#about to read 3, iclass 29, count 0 2006.225.08:15:30.62#ibcon#read 3, iclass 29, count 0 2006.225.08:15:30.62#ibcon#about to read 4, iclass 29, count 0 2006.225.08:15:30.62#ibcon#read 4, iclass 29, count 0 2006.225.08:15:30.62#ibcon#about to read 5, iclass 29, count 0 2006.225.08:15:30.62#ibcon#read 5, iclass 29, count 0 2006.225.08:15:30.62#ibcon#about to read 6, iclass 29, count 0 2006.225.08:15:30.62#ibcon#read 6, iclass 29, count 0 2006.225.08:15:30.62#ibcon#end of sib2, iclass 29, count 0 2006.225.08:15:30.62#ibcon#*after write, iclass 29, count 0 2006.225.08:15:30.62#ibcon#*before return 0, iclass 29, count 0 2006.225.08:15:30.62#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:15:30.62#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:15:30.62#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:15:30.62#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:15:30.62$vc4f8/vblo=1,632.99 2006.225.08:15:30.62#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.08:15:30.62#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.08:15:30.62#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:30.62#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:15:30.62#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:15:30.62#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:15:30.62#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:15:30.62#ibcon#first serial, iclass 31, count 0 2006.225.08:15:30.62#ibcon#enter sib2, iclass 31, count 0 2006.225.08:15:30.62#ibcon#flushed, iclass 31, count 0 2006.225.08:15:30.62#ibcon#about to write, iclass 31, count 0 2006.225.08:15:30.62#ibcon#wrote, iclass 31, count 0 2006.225.08:15:30.62#ibcon#about to read 3, iclass 31, count 0 2006.225.08:15:30.64#ibcon#read 3, iclass 31, count 0 2006.225.08:15:30.64#ibcon#about to read 4, iclass 31, count 0 2006.225.08:15:30.64#ibcon#read 4, iclass 31, count 0 2006.225.08:15:30.64#ibcon#about to read 5, iclass 31, count 0 2006.225.08:15:30.64#ibcon#read 5, iclass 31, count 0 2006.225.08:15:30.64#ibcon#about to read 6, iclass 31, count 0 2006.225.08:15:30.64#ibcon#read 6, iclass 31, count 0 2006.225.08:15:30.64#ibcon#end of sib2, iclass 31, count 0 2006.225.08:15:30.64#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:15:30.64#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:15:30.64#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:15:30.64#ibcon#*before write, iclass 31, count 0 2006.225.08:15:30.64#ibcon#enter sib2, iclass 31, count 0 2006.225.08:15:30.64#ibcon#flushed, iclass 31, count 0 2006.225.08:15:30.64#ibcon#about to write, iclass 31, count 0 2006.225.08:15:30.64#ibcon#wrote, iclass 31, count 0 2006.225.08:15:30.64#ibcon#about to read 3, iclass 31, count 0 2006.225.08:15:30.68#ibcon#read 3, iclass 31, count 0 2006.225.08:15:30.68#ibcon#about to read 4, iclass 31, count 0 2006.225.08:15:30.68#ibcon#read 4, iclass 31, count 0 2006.225.08:15:30.68#ibcon#about to read 5, iclass 31, count 0 2006.225.08:15:30.68#ibcon#read 5, iclass 31, count 0 2006.225.08:15:30.68#ibcon#about to read 6, iclass 31, count 0 2006.225.08:15:30.68#ibcon#read 6, iclass 31, count 0 2006.225.08:15:30.68#ibcon#end of sib2, iclass 31, count 0 2006.225.08:15:30.68#ibcon#*after write, iclass 31, count 0 2006.225.08:15:30.68#ibcon#*before return 0, iclass 31, count 0 2006.225.08:15:30.68#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:15:30.68#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:15:30.68#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:15:30.68#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:15:30.68$vc4f8/vb=1,4 2006.225.08:15:30.68#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.225.08:15:30.68#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.225.08:15:30.68#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:30.68#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:15:30.68#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:15:30.68#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:15:30.68#ibcon#enter wrdev, iclass 33, count 2 2006.225.08:15:30.68#ibcon#first serial, iclass 33, count 2 2006.225.08:15:30.68#ibcon#enter sib2, iclass 33, count 2 2006.225.08:15:30.68#ibcon#flushed, iclass 33, count 2 2006.225.08:15:30.68#ibcon#about to write, iclass 33, count 2 2006.225.08:15:30.68#ibcon#wrote, iclass 33, count 2 2006.225.08:15:30.68#ibcon#about to read 3, iclass 33, count 2 2006.225.08:15:30.70#ibcon#read 3, iclass 33, count 2 2006.225.08:15:30.70#ibcon#about to read 4, iclass 33, count 2 2006.225.08:15:30.70#ibcon#read 4, iclass 33, count 2 2006.225.08:15:30.70#ibcon#about to read 5, iclass 33, count 2 2006.225.08:15:30.70#ibcon#read 5, iclass 33, count 2 2006.225.08:15:30.70#ibcon#about to read 6, iclass 33, count 2 2006.225.08:15:30.70#ibcon#read 6, iclass 33, count 2 2006.225.08:15:30.70#ibcon#end of sib2, iclass 33, count 2 2006.225.08:15:30.70#ibcon#*mode == 0, iclass 33, count 2 2006.225.08:15:30.70#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.225.08:15:30.70#ibcon#[27=AT01-04\r\n] 2006.225.08:15:30.70#ibcon#*before write, iclass 33, count 2 2006.225.08:15:30.70#ibcon#enter sib2, iclass 33, count 2 2006.225.08:15:30.70#ibcon#flushed, iclass 33, count 2 2006.225.08:15:30.70#ibcon#about to write, iclass 33, count 2 2006.225.08:15:30.70#ibcon#wrote, iclass 33, count 2 2006.225.08:15:30.70#ibcon#about to read 3, iclass 33, count 2 2006.225.08:15:30.73#ibcon#read 3, iclass 33, count 2 2006.225.08:15:30.73#ibcon#about to read 4, iclass 33, count 2 2006.225.08:15:30.73#ibcon#read 4, iclass 33, count 2 2006.225.08:15:30.73#ibcon#about to read 5, iclass 33, count 2 2006.225.08:15:30.73#ibcon#read 5, iclass 33, count 2 2006.225.08:15:30.73#ibcon#about to read 6, iclass 33, count 2 2006.225.08:15:30.73#ibcon#read 6, iclass 33, count 2 2006.225.08:15:30.73#ibcon#end of sib2, iclass 33, count 2 2006.225.08:15:30.73#ibcon#*after write, iclass 33, count 2 2006.225.08:15:30.73#ibcon#*before return 0, iclass 33, count 2 2006.225.08:15:30.73#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:15:30.73#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:15:30.73#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.225.08:15:30.73#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:30.73#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:15:30.85#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:15:30.85#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:15:30.85#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:15:30.85#ibcon#first serial, iclass 33, count 0 2006.225.08:15:30.85#ibcon#enter sib2, iclass 33, count 0 2006.225.08:15:30.85#ibcon#flushed, iclass 33, count 0 2006.225.08:15:30.85#ibcon#about to write, iclass 33, count 0 2006.225.08:15:30.85#ibcon#wrote, iclass 33, count 0 2006.225.08:15:30.85#ibcon#about to read 3, iclass 33, count 0 2006.225.08:15:30.87#ibcon#read 3, iclass 33, count 0 2006.225.08:15:30.87#ibcon#about to read 4, iclass 33, count 0 2006.225.08:15:30.87#ibcon#read 4, iclass 33, count 0 2006.225.08:15:30.87#ibcon#about to read 5, iclass 33, count 0 2006.225.08:15:30.87#ibcon#read 5, iclass 33, count 0 2006.225.08:15:30.87#ibcon#about to read 6, iclass 33, count 0 2006.225.08:15:30.87#ibcon#read 6, iclass 33, count 0 2006.225.08:15:30.87#ibcon#end of sib2, iclass 33, count 0 2006.225.08:15:30.87#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:15:30.87#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:15:30.87#ibcon#[27=USB\r\n] 2006.225.08:15:30.87#ibcon#*before write, iclass 33, count 0 2006.225.08:15:30.87#ibcon#enter sib2, iclass 33, count 0 2006.225.08:15:30.87#ibcon#flushed, iclass 33, count 0 2006.225.08:15:30.87#ibcon#about to write, iclass 33, count 0 2006.225.08:15:30.87#ibcon#wrote, iclass 33, count 0 2006.225.08:15:30.87#ibcon#about to read 3, iclass 33, count 0 2006.225.08:15:30.90#ibcon#read 3, iclass 33, count 0 2006.225.08:15:30.90#ibcon#about to read 4, iclass 33, count 0 2006.225.08:15:30.90#ibcon#read 4, iclass 33, count 0 2006.225.08:15:30.90#ibcon#about to read 5, iclass 33, count 0 2006.225.08:15:30.90#ibcon#read 5, iclass 33, count 0 2006.225.08:15:30.90#ibcon#about to read 6, iclass 33, count 0 2006.225.08:15:30.90#ibcon#read 6, iclass 33, count 0 2006.225.08:15:30.90#ibcon#end of sib2, iclass 33, count 0 2006.225.08:15:30.90#ibcon#*after write, iclass 33, count 0 2006.225.08:15:30.90#ibcon#*before return 0, iclass 33, count 0 2006.225.08:15:30.90#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:15:30.90#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:15:30.90#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:15:30.90#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:15:30.90$vc4f8/vblo=2,640.99 2006.225.08:15:30.90#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.225.08:15:30.90#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.225.08:15:30.90#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:30.90#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:15:30.90#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:15:30.90#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:15:30.90#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:15:30.90#ibcon#first serial, iclass 35, count 0 2006.225.08:15:30.90#ibcon#enter sib2, iclass 35, count 0 2006.225.08:15:30.90#ibcon#flushed, iclass 35, count 0 2006.225.08:15:30.90#ibcon#about to write, iclass 35, count 0 2006.225.08:15:30.90#ibcon#wrote, iclass 35, count 0 2006.225.08:15:30.90#ibcon#about to read 3, iclass 35, count 0 2006.225.08:15:30.92#ibcon#read 3, iclass 35, count 0 2006.225.08:15:30.92#ibcon#about to read 4, iclass 35, count 0 2006.225.08:15:30.92#ibcon#read 4, iclass 35, count 0 2006.225.08:15:30.92#ibcon#about to read 5, iclass 35, count 0 2006.225.08:15:30.92#ibcon#read 5, iclass 35, count 0 2006.225.08:15:30.92#ibcon#about to read 6, iclass 35, count 0 2006.225.08:15:30.92#ibcon#read 6, iclass 35, count 0 2006.225.08:15:30.92#ibcon#end of sib2, iclass 35, count 0 2006.225.08:15:30.92#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:15:30.92#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:15:30.92#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:15:30.92#ibcon#*before write, iclass 35, count 0 2006.225.08:15:30.92#ibcon#enter sib2, iclass 35, count 0 2006.225.08:15:30.92#ibcon#flushed, iclass 35, count 0 2006.225.08:15:30.92#ibcon#about to write, iclass 35, count 0 2006.225.08:15:30.92#ibcon#wrote, iclass 35, count 0 2006.225.08:15:30.92#ibcon#about to read 3, iclass 35, count 0 2006.225.08:15:30.96#ibcon#read 3, iclass 35, count 0 2006.225.08:15:30.96#ibcon#about to read 4, iclass 35, count 0 2006.225.08:15:30.96#ibcon#read 4, iclass 35, count 0 2006.225.08:15:30.96#ibcon#about to read 5, iclass 35, count 0 2006.225.08:15:30.96#ibcon#read 5, iclass 35, count 0 2006.225.08:15:30.96#ibcon#about to read 6, iclass 35, count 0 2006.225.08:15:30.96#ibcon#read 6, iclass 35, count 0 2006.225.08:15:30.96#ibcon#end of sib2, iclass 35, count 0 2006.225.08:15:30.96#ibcon#*after write, iclass 35, count 0 2006.225.08:15:30.96#ibcon#*before return 0, iclass 35, count 0 2006.225.08:15:30.96#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:15:30.96#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:15:30.96#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:15:30.96#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:15:30.96$vc4f8/vb=2,4 2006.225.08:15:30.96#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.225.08:15:30.96#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.225.08:15:30.96#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:30.96#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:15:31.02#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:15:31.02#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:15:31.02#ibcon#enter wrdev, iclass 37, count 2 2006.225.08:15:31.02#ibcon#first serial, iclass 37, count 2 2006.225.08:15:31.02#ibcon#enter sib2, iclass 37, count 2 2006.225.08:15:31.02#ibcon#flushed, iclass 37, count 2 2006.225.08:15:31.02#ibcon#about to write, iclass 37, count 2 2006.225.08:15:31.02#ibcon#wrote, iclass 37, count 2 2006.225.08:15:31.02#ibcon#about to read 3, iclass 37, count 2 2006.225.08:15:31.04#ibcon#read 3, iclass 37, count 2 2006.225.08:15:31.04#ibcon#about to read 4, iclass 37, count 2 2006.225.08:15:31.04#ibcon#read 4, iclass 37, count 2 2006.225.08:15:31.04#ibcon#about to read 5, iclass 37, count 2 2006.225.08:15:31.04#ibcon#read 5, iclass 37, count 2 2006.225.08:15:31.04#ibcon#about to read 6, iclass 37, count 2 2006.225.08:15:31.04#ibcon#read 6, iclass 37, count 2 2006.225.08:15:31.04#ibcon#end of sib2, iclass 37, count 2 2006.225.08:15:31.04#ibcon#*mode == 0, iclass 37, count 2 2006.225.08:15:31.04#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.225.08:15:31.04#ibcon#[27=AT02-04\r\n] 2006.225.08:15:31.04#ibcon#*before write, iclass 37, count 2 2006.225.08:15:31.04#ibcon#enter sib2, iclass 37, count 2 2006.225.08:15:31.04#ibcon#flushed, iclass 37, count 2 2006.225.08:15:31.04#ibcon#about to write, iclass 37, count 2 2006.225.08:15:31.04#ibcon#wrote, iclass 37, count 2 2006.225.08:15:31.04#ibcon#about to read 3, iclass 37, count 2 2006.225.08:15:31.07#ibcon#read 3, iclass 37, count 2 2006.225.08:15:31.07#ibcon#about to read 4, iclass 37, count 2 2006.225.08:15:31.07#ibcon#read 4, iclass 37, count 2 2006.225.08:15:31.07#ibcon#about to read 5, iclass 37, count 2 2006.225.08:15:31.07#ibcon#read 5, iclass 37, count 2 2006.225.08:15:31.07#ibcon#about to read 6, iclass 37, count 2 2006.225.08:15:31.07#ibcon#read 6, iclass 37, count 2 2006.225.08:15:31.07#ibcon#end of sib2, iclass 37, count 2 2006.225.08:15:31.07#ibcon#*after write, iclass 37, count 2 2006.225.08:15:31.07#ibcon#*before return 0, iclass 37, count 2 2006.225.08:15:31.07#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:15:31.07#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:15:31.07#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.225.08:15:31.07#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:31.07#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:15:31.19#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:15:31.19#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:15:31.19#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:15:31.19#ibcon#first serial, iclass 37, count 0 2006.225.08:15:31.19#ibcon#enter sib2, iclass 37, count 0 2006.225.08:15:31.19#ibcon#flushed, iclass 37, count 0 2006.225.08:15:31.19#ibcon#about to write, iclass 37, count 0 2006.225.08:15:31.19#ibcon#wrote, iclass 37, count 0 2006.225.08:15:31.19#ibcon#about to read 3, iclass 37, count 0 2006.225.08:15:31.21#ibcon#read 3, iclass 37, count 0 2006.225.08:15:31.21#ibcon#about to read 4, iclass 37, count 0 2006.225.08:15:31.21#ibcon#read 4, iclass 37, count 0 2006.225.08:15:31.21#ibcon#about to read 5, iclass 37, count 0 2006.225.08:15:31.21#ibcon#read 5, iclass 37, count 0 2006.225.08:15:31.21#ibcon#about to read 6, iclass 37, count 0 2006.225.08:15:31.21#ibcon#read 6, iclass 37, count 0 2006.225.08:15:31.21#ibcon#end of sib2, iclass 37, count 0 2006.225.08:15:31.21#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:15:31.21#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:15:31.21#ibcon#[27=USB\r\n] 2006.225.08:15:31.21#ibcon#*before write, iclass 37, count 0 2006.225.08:15:31.21#ibcon#enter sib2, iclass 37, count 0 2006.225.08:15:31.21#ibcon#flushed, iclass 37, count 0 2006.225.08:15:31.21#ibcon#about to write, iclass 37, count 0 2006.225.08:15:31.21#ibcon#wrote, iclass 37, count 0 2006.225.08:15:31.21#ibcon#about to read 3, iclass 37, count 0 2006.225.08:15:31.24#ibcon#read 3, iclass 37, count 0 2006.225.08:15:31.24#ibcon#about to read 4, iclass 37, count 0 2006.225.08:15:31.24#ibcon#read 4, iclass 37, count 0 2006.225.08:15:31.24#ibcon#about to read 5, iclass 37, count 0 2006.225.08:15:31.24#ibcon#read 5, iclass 37, count 0 2006.225.08:15:31.24#ibcon#about to read 6, iclass 37, count 0 2006.225.08:15:31.24#ibcon#read 6, iclass 37, count 0 2006.225.08:15:31.24#ibcon#end of sib2, iclass 37, count 0 2006.225.08:15:31.24#ibcon#*after write, iclass 37, count 0 2006.225.08:15:31.24#ibcon#*before return 0, iclass 37, count 0 2006.225.08:15:31.24#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:15:31.24#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:15:31.24#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:15:31.24#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:15:31.24$vc4f8/vblo=3,656.99 2006.225.08:15:31.24#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.08:15:31.24#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.08:15:31.24#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:31.24#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:15:31.24#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:15:31.24#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:15:31.24#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:15:31.24#ibcon#first serial, iclass 39, count 0 2006.225.08:15:31.24#ibcon#enter sib2, iclass 39, count 0 2006.225.08:15:31.24#ibcon#flushed, iclass 39, count 0 2006.225.08:15:31.24#ibcon#about to write, iclass 39, count 0 2006.225.08:15:31.24#ibcon#wrote, iclass 39, count 0 2006.225.08:15:31.24#ibcon#about to read 3, iclass 39, count 0 2006.225.08:15:31.26#ibcon#read 3, iclass 39, count 0 2006.225.08:15:31.26#ibcon#about to read 4, iclass 39, count 0 2006.225.08:15:31.26#ibcon#read 4, iclass 39, count 0 2006.225.08:15:31.26#ibcon#about to read 5, iclass 39, count 0 2006.225.08:15:31.26#ibcon#read 5, iclass 39, count 0 2006.225.08:15:31.26#ibcon#about to read 6, iclass 39, count 0 2006.225.08:15:31.26#ibcon#read 6, iclass 39, count 0 2006.225.08:15:31.26#ibcon#end of sib2, iclass 39, count 0 2006.225.08:15:31.26#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:15:31.26#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:15:31.26#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:15:31.26#ibcon#*before write, iclass 39, count 0 2006.225.08:15:31.26#ibcon#enter sib2, iclass 39, count 0 2006.225.08:15:31.26#ibcon#flushed, iclass 39, count 0 2006.225.08:15:31.26#ibcon#about to write, iclass 39, count 0 2006.225.08:15:31.26#ibcon#wrote, iclass 39, count 0 2006.225.08:15:31.26#ibcon#about to read 3, iclass 39, count 0 2006.225.08:15:31.30#ibcon#read 3, iclass 39, count 0 2006.225.08:15:31.30#ibcon#about to read 4, iclass 39, count 0 2006.225.08:15:31.30#ibcon#read 4, iclass 39, count 0 2006.225.08:15:31.30#ibcon#about to read 5, iclass 39, count 0 2006.225.08:15:31.30#ibcon#read 5, iclass 39, count 0 2006.225.08:15:31.30#ibcon#about to read 6, iclass 39, count 0 2006.225.08:15:31.30#ibcon#read 6, iclass 39, count 0 2006.225.08:15:31.30#ibcon#end of sib2, iclass 39, count 0 2006.225.08:15:31.30#ibcon#*after write, iclass 39, count 0 2006.225.08:15:31.30#ibcon#*before return 0, iclass 39, count 0 2006.225.08:15:31.30#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:15:31.30#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:15:31.30#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:15:31.30#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:15:31.30$vc4f8/vb=3,4 2006.225.08:15:31.30#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.08:15:31.30#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.08:15:31.30#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:31.30#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:15:31.36#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:15:31.36#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:15:31.36#ibcon#enter wrdev, iclass 3, count 2 2006.225.08:15:31.36#ibcon#first serial, iclass 3, count 2 2006.225.08:15:31.36#ibcon#enter sib2, iclass 3, count 2 2006.225.08:15:31.36#ibcon#flushed, iclass 3, count 2 2006.225.08:15:31.36#ibcon#about to write, iclass 3, count 2 2006.225.08:15:31.36#ibcon#wrote, iclass 3, count 2 2006.225.08:15:31.36#ibcon#about to read 3, iclass 3, count 2 2006.225.08:15:31.38#ibcon#read 3, iclass 3, count 2 2006.225.08:15:31.38#ibcon#about to read 4, iclass 3, count 2 2006.225.08:15:31.38#ibcon#read 4, iclass 3, count 2 2006.225.08:15:31.38#ibcon#about to read 5, iclass 3, count 2 2006.225.08:15:31.38#ibcon#read 5, iclass 3, count 2 2006.225.08:15:31.38#ibcon#about to read 6, iclass 3, count 2 2006.225.08:15:31.38#ibcon#read 6, iclass 3, count 2 2006.225.08:15:31.38#ibcon#end of sib2, iclass 3, count 2 2006.225.08:15:31.38#ibcon#*mode == 0, iclass 3, count 2 2006.225.08:15:31.38#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.08:15:31.38#ibcon#[27=AT03-04\r\n] 2006.225.08:15:31.38#ibcon#*before write, iclass 3, count 2 2006.225.08:15:31.38#ibcon#enter sib2, iclass 3, count 2 2006.225.08:15:31.38#ibcon#flushed, iclass 3, count 2 2006.225.08:15:31.38#ibcon#about to write, iclass 3, count 2 2006.225.08:15:31.38#ibcon#wrote, iclass 3, count 2 2006.225.08:15:31.38#ibcon#about to read 3, iclass 3, count 2 2006.225.08:15:31.41#ibcon#read 3, iclass 3, count 2 2006.225.08:15:31.41#ibcon#about to read 4, iclass 3, count 2 2006.225.08:15:31.41#ibcon#read 4, iclass 3, count 2 2006.225.08:15:31.41#ibcon#about to read 5, iclass 3, count 2 2006.225.08:15:31.41#ibcon#read 5, iclass 3, count 2 2006.225.08:15:31.41#ibcon#about to read 6, iclass 3, count 2 2006.225.08:15:31.41#ibcon#read 6, iclass 3, count 2 2006.225.08:15:31.41#ibcon#end of sib2, iclass 3, count 2 2006.225.08:15:31.41#ibcon#*after write, iclass 3, count 2 2006.225.08:15:31.41#ibcon#*before return 0, iclass 3, count 2 2006.225.08:15:31.41#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:15:31.41#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:15:31.41#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.08:15:31.41#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:31.41#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:15:31.53#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:15:31.53#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:15:31.53#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:15:31.53#ibcon#first serial, iclass 3, count 0 2006.225.08:15:31.53#ibcon#enter sib2, iclass 3, count 0 2006.225.08:15:31.53#ibcon#flushed, iclass 3, count 0 2006.225.08:15:31.53#ibcon#about to write, iclass 3, count 0 2006.225.08:15:31.53#ibcon#wrote, iclass 3, count 0 2006.225.08:15:31.53#ibcon#about to read 3, iclass 3, count 0 2006.225.08:15:31.55#ibcon#read 3, iclass 3, count 0 2006.225.08:15:31.55#ibcon#about to read 4, iclass 3, count 0 2006.225.08:15:31.55#ibcon#read 4, iclass 3, count 0 2006.225.08:15:31.55#ibcon#about to read 5, iclass 3, count 0 2006.225.08:15:31.55#ibcon#read 5, iclass 3, count 0 2006.225.08:15:31.55#ibcon#about to read 6, iclass 3, count 0 2006.225.08:15:31.55#ibcon#read 6, iclass 3, count 0 2006.225.08:15:31.55#ibcon#end of sib2, iclass 3, count 0 2006.225.08:15:31.55#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:15:31.55#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:15:31.55#ibcon#[27=USB\r\n] 2006.225.08:15:31.55#ibcon#*before write, iclass 3, count 0 2006.225.08:15:31.55#ibcon#enter sib2, iclass 3, count 0 2006.225.08:15:31.55#ibcon#flushed, iclass 3, count 0 2006.225.08:15:31.55#ibcon#about to write, iclass 3, count 0 2006.225.08:15:31.55#ibcon#wrote, iclass 3, count 0 2006.225.08:15:31.55#ibcon#about to read 3, iclass 3, count 0 2006.225.08:15:31.58#ibcon#read 3, iclass 3, count 0 2006.225.08:15:31.58#ibcon#about to read 4, iclass 3, count 0 2006.225.08:15:31.58#ibcon#read 4, iclass 3, count 0 2006.225.08:15:31.58#ibcon#about to read 5, iclass 3, count 0 2006.225.08:15:31.58#ibcon#read 5, iclass 3, count 0 2006.225.08:15:31.58#ibcon#about to read 6, iclass 3, count 0 2006.225.08:15:31.58#ibcon#read 6, iclass 3, count 0 2006.225.08:15:31.58#ibcon#end of sib2, iclass 3, count 0 2006.225.08:15:31.58#ibcon#*after write, iclass 3, count 0 2006.225.08:15:31.58#ibcon#*before return 0, iclass 3, count 0 2006.225.08:15:31.58#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:15:31.58#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:15:31.58#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:15:31.58#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:15:31.58$vc4f8/vblo=4,712.99 2006.225.08:15:31.58#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.08:15:31.58#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.08:15:31.58#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:31.58#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:15:31.58#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:15:31.58#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:15:31.58#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:15:31.58#ibcon#first serial, iclass 5, count 0 2006.225.08:15:31.58#ibcon#enter sib2, iclass 5, count 0 2006.225.08:15:31.58#ibcon#flushed, iclass 5, count 0 2006.225.08:15:31.58#ibcon#about to write, iclass 5, count 0 2006.225.08:15:31.58#ibcon#wrote, iclass 5, count 0 2006.225.08:15:31.58#ibcon#about to read 3, iclass 5, count 0 2006.225.08:15:31.60#ibcon#read 3, iclass 5, count 0 2006.225.08:15:31.60#ibcon#about to read 4, iclass 5, count 0 2006.225.08:15:31.60#ibcon#read 4, iclass 5, count 0 2006.225.08:15:31.60#ibcon#about to read 5, iclass 5, count 0 2006.225.08:15:31.60#ibcon#read 5, iclass 5, count 0 2006.225.08:15:31.60#ibcon#about to read 6, iclass 5, count 0 2006.225.08:15:31.60#ibcon#read 6, iclass 5, count 0 2006.225.08:15:31.60#ibcon#end of sib2, iclass 5, count 0 2006.225.08:15:31.60#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:15:31.60#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:15:31.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:15:31.60#ibcon#*before write, iclass 5, count 0 2006.225.08:15:31.60#ibcon#enter sib2, iclass 5, count 0 2006.225.08:15:31.60#ibcon#flushed, iclass 5, count 0 2006.225.08:15:31.60#ibcon#about to write, iclass 5, count 0 2006.225.08:15:31.60#ibcon#wrote, iclass 5, count 0 2006.225.08:15:31.60#ibcon#about to read 3, iclass 5, count 0 2006.225.08:15:31.64#ibcon#read 3, iclass 5, count 0 2006.225.08:15:31.64#ibcon#about to read 4, iclass 5, count 0 2006.225.08:15:31.64#ibcon#read 4, iclass 5, count 0 2006.225.08:15:31.64#ibcon#about to read 5, iclass 5, count 0 2006.225.08:15:31.64#ibcon#read 5, iclass 5, count 0 2006.225.08:15:31.64#ibcon#about to read 6, iclass 5, count 0 2006.225.08:15:31.64#ibcon#read 6, iclass 5, count 0 2006.225.08:15:31.64#ibcon#end of sib2, iclass 5, count 0 2006.225.08:15:31.64#ibcon#*after write, iclass 5, count 0 2006.225.08:15:31.64#ibcon#*before return 0, iclass 5, count 0 2006.225.08:15:31.64#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:15:31.64#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:15:31.64#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:15:31.64#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:15:31.64$vc4f8/vb=4,4 2006.225.08:15:31.64#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.08:15:31.64#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.08:15:31.64#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:31.64#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:15:31.70#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:15:31.70#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:15:31.70#ibcon#enter wrdev, iclass 7, count 2 2006.225.08:15:31.70#ibcon#first serial, iclass 7, count 2 2006.225.08:15:31.70#ibcon#enter sib2, iclass 7, count 2 2006.225.08:15:31.70#ibcon#flushed, iclass 7, count 2 2006.225.08:15:31.70#ibcon#about to write, iclass 7, count 2 2006.225.08:15:31.70#ibcon#wrote, iclass 7, count 2 2006.225.08:15:31.70#ibcon#about to read 3, iclass 7, count 2 2006.225.08:15:31.72#ibcon#read 3, iclass 7, count 2 2006.225.08:15:31.72#ibcon#about to read 4, iclass 7, count 2 2006.225.08:15:31.72#ibcon#read 4, iclass 7, count 2 2006.225.08:15:31.72#ibcon#about to read 5, iclass 7, count 2 2006.225.08:15:31.72#ibcon#read 5, iclass 7, count 2 2006.225.08:15:31.72#ibcon#about to read 6, iclass 7, count 2 2006.225.08:15:31.72#ibcon#read 6, iclass 7, count 2 2006.225.08:15:31.72#ibcon#end of sib2, iclass 7, count 2 2006.225.08:15:31.72#ibcon#*mode == 0, iclass 7, count 2 2006.225.08:15:31.72#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.08:15:31.72#ibcon#[27=AT04-04\r\n] 2006.225.08:15:31.72#ibcon#*before write, iclass 7, count 2 2006.225.08:15:31.72#ibcon#enter sib2, iclass 7, count 2 2006.225.08:15:31.72#ibcon#flushed, iclass 7, count 2 2006.225.08:15:31.72#ibcon#about to write, iclass 7, count 2 2006.225.08:15:31.72#ibcon#wrote, iclass 7, count 2 2006.225.08:15:31.72#ibcon#about to read 3, iclass 7, count 2 2006.225.08:15:31.75#ibcon#read 3, iclass 7, count 2 2006.225.08:15:31.75#ibcon#about to read 4, iclass 7, count 2 2006.225.08:15:31.75#ibcon#read 4, iclass 7, count 2 2006.225.08:15:31.75#ibcon#about to read 5, iclass 7, count 2 2006.225.08:15:31.75#ibcon#read 5, iclass 7, count 2 2006.225.08:15:31.75#ibcon#about to read 6, iclass 7, count 2 2006.225.08:15:31.75#ibcon#read 6, iclass 7, count 2 2006.225.08:15:31.75#ibcon#end of sib2, iclass 7, count 2 2006.225.08:15:31.75#ibcon#*after write, iclass 7, count 2 2006.225.08:15:31.75#ibcon#*before return 0, iclass 7, count 2 2006.225.08:15:31.75#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:15:31.75#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:15:31.75#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.08:15:31.75#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:31.75#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:15:31.87#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:15:31.87#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:15:31.87#ibcon#enter wrdev, iclass 7, count 0 2006.225.08:15:31.87#ibcon#first serial, iclass 7, count 0 2006.225.08:15:31.87#ibcon#enter sib2, iclass 7, count 0 2006.225.08:15:31.87#ibcon#flushed, iclass 7, count 0 2006.225.08:15:31.87#ibcon#about to write, iclass 7, count 0 2006.225.08:15:31.87#ibcon#wrote, iclass 7, count 0 2006.225.08:15:31.87#ibcon#about to read 3, iclass 7, count 0 2006.225.08:15:31.89#ibcon#read 3, iclass 7, count 0 2006.225.08:15:31.89#ibcon#about to read 4, iclass 7, count 0 2006.225.08:15:31.89#ibcon#read 4, iclass 7, count 0 2006.225.08:15:31.89#ibcon#about to read 5, iclass 7, count 0 2006.225.08:15:31.89#ibcon#read 5, iclass 7, count 0 2006.225.08:15:31.89#ibcon#about to read 6, iclass 7, count 0 2006.225.08:15:31.89#ibcon#read 6, iclass 7, count 0 2006.225.08:15:31.89#ibcon#end of sib2, iclass 7, count 0 2006.225.08:15:31.89#ibcon#*mode == 0, iclass 7, count 0 2006.225.08:15:31.89#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.08:15:31.89#ibcon#[27=USB\r\n] 2006.225.08:15:31.89#ibcon#*before write, iclass 7, count 0 2006.225.08:15:31.89#ibcon#enter sib2, iclass 7, count 0 2006.225.08:15:31.89#ibcon#flushed, iclass 7, count 0 2006.225.08:15:31.89#ibcon#about to write, iclass 7, count 0 2006.225.08:15:31.89#ibcon#wrote, iclass 7, count 0 2006.225.08:15:31.89#ibcon#about to read 3, iclass 7, count 0 2006.225.08:15:31.92#ibcon#read 3, iclass 7, count 0 2006.225.08:15:31.92#ibcon#about to read 4, iclass 7, count 0 2006.225.08:15:31.92#ibcon#read 4, iclass 7, count 0 2006.225.08:15:31.92#ibcon#about to read 5, iclass 7, count 0 2006.225.08:15:31.92#ibcon#read 5, iclass 7, count 0 2006.225.08:15:31.92#ibcon#about to read 6, iclass 7, count 0 2006.225.08:15:31.92#ibcon#read 6, iclass 7, count 0 2006.225.08:15:31.92#ibcon#end of sib2, iclass 7, count 0 2006.225.08:15:31.92#ibcon#*after write, iclass 7, count 0 2006.225.08:15:31.92#ibcon#*before return 0, iclass 7, count 0 2006.225.08:15:31.92#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:15:31.92#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:15:31.92#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.08:15:31.92#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.08:15:31.92$vc4f8/vblo=5,744.99 2006.225.08:15:31.92#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.08:15:31.92#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.08:15:31.92#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:31.92#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:15:31.92#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:15:31.92#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:15:31.92#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:15:31.92#ibcon#first serial, iclass 11, count 0 2006.225.08:15:31.92#ibcon#enter sib2, iclass 11, count 0 2006.225.08:15:31.92#ibcon#flushed, iclass 11, count 0 2006.225.08:15:31.92#ibcon#about to write, iclass 11, count 0 2006.225.08:15:31.92#ibcon#wrote, iclass 11, count 0 2006.225.08:15:31.92#ibcon#about to read 3, iclass 11, count 0 2006.225.08:15:31.94#ibcon#read 3, iclass 11, count 0 2006.225.08:15:31.94#ibcon#about to read 4, iclass 11, count 0 2006.225.08:15:31.94#ibcon#read 4, iclass 11, count 0 2006.225.08:15:31.94#ibcon#about to read 5, iclass 11, count 0 2006.225.08:15:31.94#ibcon#read 5, iclass 11, count 0 2006.225.08:15:31.94#ibcon#about to read 6, iclass 11, count 0 2006.225.08:15:31.94#ibcon#read 6, iclass 11, count 0 2006.225.08:15:31.94#ibcon#end of sib2, iclass 11, count 0 2006.225.08:15:31.94#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:15:31.94#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:15:31.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:15:31.94#ibcon#*before write, iclass 11, count 0 2006.225.08:15:31.94#ibcon#enter sib2, iclass 11, count 0 2006.225.08:15:31.94#ibcon#flushed, iclass 11, count 0 2006.225.08:15:31.94#ibcon#about to write, iclass 11, count 0 2006.225.08:15:31.94#ibcon#wrote, iclass 11, count 0 2006.225.08:15:31.94#ibcon#about to read 3, iclass 11, count 0 2006.225.08:15:31.98#ibcon#read 3, iclass 11, count 0 2006.225.08:15:31.98#ibcon#about to read 4, iclass 11, count 0 2006.225.08:15:31.98#ibcon#read 4, iclass 11, count 0 2006.225.08:15:31.98#ibcon#about to read 5, iclass 11, count 0 2006.225.08:15:31.98#ibcon#read 5, iclass 11, count 0 2006.225.08:15:31.98#ibcon#about to read 6, iclass 11, count 0 2006.225.08:15:31.98#ibcon#read 6, iclass 11, count 0 2006.225.08:15:31.98#ibcon#end of sib2, iclass 11, count 0 2006.225.08:15:31.98#ibcon#*after write, iclass 11, count 0 2006.225.08:15:31.98#ibcon#*before return 0, iclass 11, count 0 2006.225.08:15:31.98#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:15:31.98#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:15:31.98#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:15:31.98#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:15:31.98$vc4f8/vb=5,4 2006.225.08:15:31.98#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.08:15:31.98#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.08:15:31.98#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:31.98#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:15:32.04#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:15:32.04#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:15:32.04#ibcon#enter wrdev, iclass 13, count 2 2006.225.08:15:32.04#ibcon#first serial, iclass 13, count 2 2006.225.08:15:32.04#ibcon#enter sib2, iclass 13, count 2 2006.225.08:15:32.04#ibcon#flushed, iclass 13, count 2 2006.225.08:15:32.04#ibcon#about to write, iclass 13, count 2 2006.225.08:15:32.04#ibcon#wrote, iclass 13, count 2 2006.225.08:15:32.04#ibcon#about to read 3, iclass 13, count 2 2006.225.08:15:32.06#ibcon#read 3, iclass 13, count 2 2006.225.08:15:32.06#ibcon#about to read 4, iclass 13, count 2 2006.225.08:15:32.06#ibcon#read 4, iclass 13, count 2 2006.225.08:15:32.06#ibcon#about to read 5, iclass 13, count 2 2006.225.08:15:32.06#ibcon#read 5, iclass 13, count 2 2006.225.08:15:32.06#ibcon#about to read 6, iclass 13, count 2 2006.225.08:15:32.06#ibcon#read 6, iclass 13, count 2 2006.225.08:15:32.06#ibcon#end of sib2, iclass 13, count 2 2006.225.08:15:32.06#ibcon#*mode == 0, iclass 13, count 2 2006.225.08:15:32.06#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.08:15:32.06#ibcon#[27=AT05-04\r\n] 2006.225.08:15:32.06#ibcon#*before write, iclass 13, count 2 2006.225.08:15:32.06#ibcon#enter sib2, iclass 13, count 2 2006.225.08:15:32.06#ibcon#flushed, iclass 13, count 2 2006.225.08:15:32.06#ibcon#about to write, iclass 13, count 2 2006.225.08:15:32.06#ibcon#wrote, iclass 13, count 2 2006.225.08:15:32.06#ibcon#about to read 3, iclass 13, count 2 2006.225.08:15:32.09#ibcon#read 3, iclass 13, count 2 2006.225.08:15:32.09#ibcon#about to read 4, iclass 13, count 2 2006.225.08:15:32.09#ibcon#read 4, iclass 13, count 2 2006.225.08:15:32.09#ibcon#about to read 5, iclass 13, count 2 2006.225.08:15:32.09#ibcon#read 5, iclass 13, count 2 2006.225.08:15:32.09#ibcon#about to read 6, iclass 13, count 2 2006.225.08:15:32.09#ibcon#read 6, iclass 13, count 2 2006.225.08:15:32.09#ibcon#end of sib2, iclass 13, count 2 2006.225.08:15:32.09#ibcon#*after write, iclass 13, count 2 2006.225.08:15:32.09#ibcon#*before return 0, iclass 13, count 2 2006.225.08:15:32.09#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:15:32.09#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:15:32.09#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.08:15:32.09#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:32.09#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:15:32.21#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:15:32.21#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:15:32.21#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:15:32.21#ibcon#first serial, iclass 13, count 0 2006.225.08:15:32.21#ibcon#enter sib2, iclass 13, count 0 2006.225.08:15:32.21#ibcon#flushed, iclass 13, count 0 2006.225.08:15:32.21#ibcon#about to write, iclass 13, count 0 2006.225.08:15:32.21#ibcon#wrote, iclass 13, count 0 2006.225.08:15:32.21#ibcon#about to read 3, iclass 13, count 0 2006.225.08:15:32.23#ibcon#read 3, iclass 13, count 0 2006.225.08:15:32.23#ibcon#about to read 4, iclass 13, count 0 2006.225.08:15:32.23#ibcon#read 4, iclass 13, count 0 2006.225.08:15:32.23#ibcon#about to read 5, iclass 13, count 0 2006.225.08:15:32.23#ibcon#read 5, iclass 13, count 0 2006.225.08:15:32.23#ibcon#about to read 6, iclass 13, count 0 2006.225.08:15:32.23#ibcon#read 6, iclass 13, count 0 2006.225.08:15:32.23#ibcon#end of sib2, iclass 13, count 0 2006.225.08:15:32.23#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:15:32.23#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:15:32.23#ibcon#[27=USB\r\n] 2006.225.08:15:32.23#ibcon#*before write, iclass 13, count 0 2006.225.08:15:32.23#ibcon#enter sib2, iclass 13, count 0 2006.225.08:15:32.23#ibcon#flushed, iclass 13, count 0 2006.225.08:15:32.23#ibcon#about to write, iclass 13, count 0 2006.225.08:15:32.23#ibcon#wrote, iclass 13, count 0 2006.225.08:15:32.23#ibcon#about to read 3, iclass 13, count 0 2006.225.08:15:32.26#ibcon#read 3, iclass 13, count 0 2006.225.08:15:32.26#ibcon#about to read 4, iclass 13, count 0 2006.225.08:15:32.26#ibcon#read 4, iclass 13, count 0 2006.225.08:15:32.26#ibcon#about to read 5, iclass 13, count 0 2006.225.08:15:32.26#ibcon#read 5, iclass 13, count 0 2006.225.08:15:32.26#ibcon#about to read 6, iclass 13, count 0 2006.225.08:15:32.26#ibcon#read 6, iclass 13, count 0 2006.225.08:15:32.26#ibcon#end of sib2, iclass 13, count 0 2006.225.08:15:32.26#ibcon#*after write, iclass 13, count 0 2006.225.08:15:32.26#ibcon#*before return 0, iclass 13, count 0 2006.225.08:15:32.26#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:15:32.26#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:15:32.26#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:15:32.26#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:15:32.26$vc4f8/vblo=6,752.99 2006.225.08:15:32.26#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.08:15:32.26#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.08:15:32.26#ibcon#ireg 17 cls_cnt 0 2006.225.08:15:32.26#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:15:32.26#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:15:32.26#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:15:32.26#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:15:32.26#ibcon#first serial, iclass 15, count 0 2006.225.08:15:32.26#ibcon#enter sib2, iclass 15, count 0 2006.225.08:15:32.26#ibcon#flushed, iclass 15, count 0 2006.225.08:15:32.26#ibcon#about to write, iclass 15, count 0 2006.225.08:15:32.26#ibcon#wrote, iclass 15, count 0 2006.225.08:15:32.26#ibcon#about to read 3, iclass 15, count 0 2006.225.08:15:32.28#ibcon#read 3, iclass 15, count 0 2006.225.08:15:32.28#ibcon#about to read 4, iclass 15, count 0 2006.225.08:15:32.28#ibcon#read 4, iclass 15, count 0 2006.225.08:15:32.28#ibcon#about to read 5, iclass 15, count 0 2006.225.08:15:32.28#ibcon#read 5, iclass 15, count 0 2006.225.08:15:32.28#ibcon#about to read 6, iclass 15, count 0 2006.225.08:15:32.28#ibcon#read 6, iclass 15, count 0 2006.225.08:15:32.28#ibcon#end of sib2, iclass 15, count 0 2006.225.08:15:32.28#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:15:32.28#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:15:32.28#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:15:32.28#ibcon#*before write, iclass 15, count 0 2006.225.08:15:32.28#ibcon#enter sib2, iclass 15, count 0 2006.225.08:15:32.28#ibcon#flushed, iclass 15, count 0 2006.225.08:15:32.28#ibcon#about to write, iclass 15, count 0 2006.225.08:15:32.28#ibcon#wrote, iclass 15, count 0 2006.225.08:15:32.28#ibcon#about to read 3, iclass 15, count 0 2006.225.08:15:32.33#ibcon#read 3, iclass 15, count 0 2006.225.08:15:32.33#ibcon#about to read 4, iclass 15, count 0 2006.225.08:15:32.33#ibcon#read 4, iclass 15, count 0 2006.225.08:15:32.33#ibcon#about to read 5, iclass 15, count 0 2006.225.08:15:32.33#ibcon#read 5, iclass 15, count 0 2006.225.08:15:32.33#ibcon#about to read 6, iclass 15, count 0 2006.225.08:15:32.33#ibcon#read 6, iclass 15, count 0 2006.225.08:15:32.33#ibcon#end of sib2, iclass 15, count 0 2006.225.08:15:32.33#ibcon#*after write, iclass 15, count 0 2006.225.08:15:32.33#ibcon#*before return 0, iclass 15, count 0 2006.225.08:15:32.33#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:15:32.33#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:15:32.33#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:15:32.33#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:15:32.33$vc4f8/vb=6,4 2006.225.08:15:32.33#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.08:15:32.33#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.08:15:32.33#ibcon#ireg 11 cls_cnt 2 2006.225.08:15:32.33#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:15:32.37#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:15:32.37#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:15:32.37#ibcon#enter wrdev, iclass 17, count 2 2006.225.08:15:32.37#ibcon#first serial, iclass 17, count 2 2006.225.08:15:32.37#ibcon#enter sib2, iclass 17, count 2 2006.225.08:15:32.37#ibcon#flushed, iclass 17, count 2 2006.225.08:15:32.37#ibcon#about to write, iclass 17, count 2 2006.225.08:15:32.37#ibcon#wrote, iclass 17, count 2 2006.225.08:15:32.37#ibcon#about to read 3, iclass 17, count 2 2006.225.08:15:32.39#ibcon#read 3, iclass 17, count 2 2006.225.08:15:32.39#ibcon#about to read 4, iclass 17, count 2 2006.225.08:15:32.39#ibcon#read 4, iclass 17, count 2 2006.225.08:15:32.39#ibcon#about to read 5, iclass 17, count 2 2006.225.08:15:32.39#ibcon#read 5, iclass 17, count 2 2006.225.08:15:32.39#ibcon#about to read 6, iclass 17, count 2 2006.225.08:15:32.39#ibcon#read 6, iclass 17, count 2 2006.225.08:15:32.39#ibcon#end of sib2, iclass 17, count 2 2006.225.08:15:32.39#ibcon#*mode == 0, iclass 17, count 2 2006.225.08:15:32.39#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.08:15:32.39#ibcon#[27=AT06-04\r\n] 2006.225.08:15:32.39#ibcon#*before write, iclass 17, count 2 2006.225.08:15:32.39#ibcon#enter sib2, iclass 17, count 2 2006.225.08:15:32.39#ibcon#flushed, iclass 17, count 2 2006.225.08:15:32.39#ibcon#about to write, iclass 17, count 2 2006.225.08:15:32.39#ibcon#wrote, iclass 17, count 2 2006.225.08:15:32.39#ibcon#about to read 3, iclass 17, count 2 2006.225.08:15:32.42#ibcon#read 3, iclass 17, count 2 2006.225.08:15:32.42#ibcon#about to read 4, iclass 17, count 2 2006.225.08:15:32.42#ibcon#read 4, iclass 17, count 2 2006.225.08:15:32.42#ibcon#about to read 5, iclass 17, count 2 2006.225.08:15:32.42#ibcon#read 5, iclass 17, count 2 2006.225.08:15:32.42#ibcon#about to read 6, iclass 17, count 2 2006.225.08:15:32.42#ibcon#read 6, iclass 17, count 2 2006.225.08:15:32.42#ibcon#end of sib2, iclass 17, count 2 2006.225.08:15:32.42#ibcon#*after write, iclass 17, count 2 2006.225.08:15:32.42#ibcon#*before return 0, iclass 17, count 2 2006.225.08:15:32.42#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:15:32.42#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:15:32.42#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.08:15:32.42#ibcon#ireg 7 cls_cnt 0 2006.225.08:15:32.42#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:15:32.54#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:15:32.54#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:15:32.54#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:15:32.54#ibcon#first serial, iclass 17, count 0 2006.225.08:15:32.54#ibcon#enter sib2, iclass 17, count 0 2006.225.08:15:32.54#ibcon#flushed, iclass 17, count 0 2006.225.08:15:32.54#ibcon#about to write, iclass 17, count 0 2006.225.08:15:32.54#ibcon#wrote, iclass 17, count 0 2006.225.08:15:32.54#ibcon#about to read 3, iclass 17, count 0 2006.225.08:15:32.56#ibcon#read 3, iclass 17, count 0 2006.225.08:15:32.56#ibcon#about to read 4, iclass 17, count 0 2006.225.08:15:32.56#ibcon#read 4, iclass 17, count 0 2006.225.08:15:32.56#ibcon#about to read 5, iclass 17, count 0 2006.225.08:15:32.56#ibcon#read 5, iclass 17, count 0 2006.225.08:15:32.56#ibcon#about to read 6, iclass 17, count 0 2006.225.08:15:32.56#ibcon#read 6, iclass 17, count 0 2006.225.08:15:32.56#ibcon#end of sib2, iclass 17, count 0 2006.225.08:15:32.56#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:15:32.56#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:15:32.56#ibcon#[27=USB\r\n] 2006.225.08:15:32.56#ibcon#*before write, iclass 17, count 0 2006.225.08:15:32.56#ibcon#enter sib2, iclass 17, count 0 2006.225.08:15:32.56#ibcon#flushed, iclass 17, count 0 2006.225.08:15:32.56#ibcon#about to write, iclass 17, count 0 2006.225.08:15:32.56#ibcon#wrote, iclass 17, count 0 2006.225.08:15:32.56#ibcon#about to read 3, iclass 17, count 0 2006.225.08:15:32.59#ibcon#read 3, iclass 17, count 0 2006.225.08:15:32.59#ibcon#about to read 4, iclass 17, count 0 2006.225.08:15:32.59#ibcon#read 4, iclass 17, count 0 2006.225.08:15:32.59#ibcon#about to read 5, iclass 17, count 0 2006.225.08:15:32.59#ibcon#read 5, iclass 17, count 0 2006.225.08:15:32.59#ibcon#about to read 6, iclass 17, count 0 2006.225.08:15:32.59#ibcon#read 6, iclass 17, count 0 2006.225.08:15:32.59#ibcon#end of sib2, iclass 17, count 0 2006.225.08:15:32.59#ibcon#*after write, iclass 17, count 0 2006.225.08:15:32.59#ibcon#*before return 0, iclass 17, count 0 2006.225.08:15:32.59#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:15:32.59#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:15:32.59#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:15:32.59#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:15:32.59$vc4f8/vabw=wide 2006.225.08:15:32.59#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.08:15:32.59#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.08:15:32.59#ibcon#ireg 8 cls_cnt 0 2006.225.08:15:32.59#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:15:32.59#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:15:32.59#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:15:32.59#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:15:32.59#ibcon#first serial, iclass 19, count 0 2006.225.08:15:32.59#ibcon#enter sib2, iclass 19, count 0 2006.225.08:15:32.59#ibcon#flushed, iclass 19, count 0 2006.225.08:15:32.59#ibcon#about to write, iclass 19, count 0 2006.225.08:15:32.59#ibcon#wrote, iclass 19, count 0 2006.225.08:15:32.59#ibcon#about to read 3, iclass 19, count 0 2006.225.08:15:32.61#ibcon#read 3, iclass 19, count 0 2006.225.08:15:32.61#ibcon#about to read 4, iclass 19, count 0 2006.225.08:15:32.61#ibcon#read 4, iclass 19, count 0 2006.225.08:15:32.61#ibcon#about to read 5, iclass 19, count 0 2006.225.08:15:32.61#ibcon#read 5, iclass 19, count 0 2006.225.08:15:32.61#ibcon#about to read 6, iclass 19, count 0 2006.225.08:15:32.61#ibcon#read 6, iclass 19, count 0 2006.225.08:15:32.61#ibcon#end of sib2, iclass 19, count 0 2006.225.08:15:32.61#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:15:32.61#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:15:32.61#ibcon#[25=BW32\r\n] 2006.225.08:15:32.61#ibcon#*before write, iclass 19, count 0 2006.225.08:15:32.61#ibcon#enter sib2, iclass 19, count 0 2006.225.08:15:32.61#ibcon#flushed, iclass 19, count 0 2006.225.08:15:32.61#ibcon#about to write, iclass 19, count 0 2006.225.08:15:32.61#ibcon#wrote, iclass 19, count 0 2006.225.08:15:32.61#ibcon#about to read 3, iclass 19, count 0 2006.225.08:15:32.64#ibcon#read 3, iclass 19, count 0 2006.225.08:15:32.64#ibcon#about to read 4, iclass 19, count 0 2006.225.08:15:32.64#ibcon#read 4, iclass 19, count 0 2006.225.08:15:32.64#ibcon#about to read 5, iclass 19, count 0 2006.225.08:15:32.64#ibcon#read 5, iclass 19, count 0 2006.225.08:15:32.64#ibcon#about to read 6, iclass 19, count 0 2006.225.08:15:32.64#ibcon#read 6, iclass 19, count 0 2006.225.08:15:32.64#ibcon#end of sib2, iclass 19, count 0 2006.225.08:15:32.64#ibcon#*after write, iclass 19, count 0 2006.225.08:15:32.64#ibcon#*before return 0, iclass 19, count 0 2006.225.08:15:32.64#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:15:32.64#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:15:32.64#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:15:32.64#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:15:32.64$vc4f8/vbbw=wide 2006.225.08:15:32.64#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.225.08:15:32.64#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.225.08:15:32.64#ibcon#ireg 8 cls_cnt 0 2006.225.08:15:32.64#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:15:32.71#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:15:32.71#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:15:32.71#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:15:32.71#ibcon#first serial, iclass 21, count 0 2006.225.08:15:32.71#ibcon#enter sib2, iclass 21, count 0 2006.225.08:15:32.71#ibcon#flushed, iclass 21, count 0 2006.225.08:15:32.71#ibcon#about to write, iclass 21, count 0 2006.225.08:15:32.71#ibcon#wrote, iclass 21, count 0 2006.225.08:15:32.71#ibcon#about to read 3, iclass 21, count 0 2006.225.08:15:32.73#ibcon#read 3, iclass 21, count 0 2006.225.08:15:32.73#ibcon#about to read 4, iclass 21, count 0 2006.225.08:15:32.73#ibcon#read 4, iclass 21, count 0 2006.225.08:15:32.73#ibcon#about to read 5, iclass 21, count 0 2006.225.08:15:32.73#ibcon#read 5, iclass 21, count 0 2006.225.08:15:32.73#ibcon#about to read 6, iclass 21, count 0 2006.225.08:15:32.73#ibcon#read 6, iclass 21, count 0 2006.225.08:15:32.73#ibcon#end of sib2, iclass 21, count 0 2006.225.08:15:32.73#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:15:32.73#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:15:32.73#ibcon#[27=BW32\r\n] 2006.225.08:15:32.73#ibcon#*before write, iclass 21, count 0 2006.225.08:15:32.73#ibcon#enter sib2, iclass 21, count 0 2006.225.08:15:32.73#ibcon#flushed, iclass 21, count 0 2006.225.08:15:32.73#ibcon#about to write, iclass 21, count 0 2006.225.08:15:32.73#ibcon#wrote, iclass 21, count 0 2006.225.08:15:32.73#ibcon#about to read 3, iclass 21, count 0 2006.225.08:15:32.76#ibcon#read 3, iclass 21, count 0 2006.225.08:15:32.76#ibcon#about to read 4, iclass 21, count 0 2006.225.08:15:32.76#ibcon#read 4, iclass 21, count 0 2006.225.08:15:32.76#ibcon#about to read 5, iclass 21, count 0 2006.225.08:15:32.76#ibcon#read 5, iclass 21, count 0 2006.225.08:15:32.76#ibcon#about to read 6, iclass 21, count 0 2006.225.08:15:32.76#ibcon#read 6, iclass 21, count 0 2006.225.08:15:32.76#ibcon#end of sib2, iclass 21, count 0 2006.225.08:15:32.76#ibcon#*after write, iclass 21, count 0 2006.225.08:15:32.76#ibcon#*before return 0, iclass 21, count 0 2006.225.08:15:32.76#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:15:32.76#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:15:32.76#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:15:32.76#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:15:32.76$4f8m12a/ifd4f 2006.225.08:15:32.76$ifd4f/lo= 2006.225.08:15:32.76$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:15:32.76$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:15:32.76$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:15:32.76$ifd4f/patch= 2006.225.08:15:32.76$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:15:32.76$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:15:32.76$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:15:32.76$4f8m12a/"form=m,16.000,1:2 2006.225.08:15:32.76$4f8m12a/"tpicd 2006.225.08:15:32.76$4f8m12a/echo=off 2006.225.08:15:32.76$4f8m12a/xlog=off 2006.225.08:15:32.76:!2006.225.08:16:00 2006.225.08:15:41.14#trakl#Source acquired 2006.225.08:15:41.14#flagr#flagr/antenna,acquired 2006.225.08:16:00.00:preob 2006.225.08:16:00.14/onsource/TRACKING 2006.225.08:16:00.14:!2006.225.08:16:10 2006.225.08:16:10.00:data_valid=on 2006.225.08:16:10.00:midob 2006.225.08:16:11.13/onsource/TRACKING 2006.225.08:16:11.13/wx/28.08,1003.4,73 2006.225.08:16:11.30/cable/+6.4053E-03 2006.225.08:16:12.39/va/01,08,usb,yes,28,30 2006.225.08:16:12.39/va/02,07,usb,yes,28,30 2006.225.08:16:12.39/va/03,06,usb,yes,30,30 2006.225.08:16:12.39/va/04,07,usb,yes,30,32 2006.225.08:16:12.39/va/05,07,usb,yes,32,33 2006.225.08:16:12.39/va/06,06,usb,yes,31,31 2006.225.08:16:12.39/va/07,06,usb,yes,31,31 2006.225.08:16:12.39/va/08,07,usb,yes,30,29 2006.225.08:16:12.62/valo/01,532.99,yes,locked 2006.225.08:16:12.62/valo/02,572.99,yes,locked 2006.225.08:16:12.62/valo/03,672.99,yes,locked 2006.225.08:16:12.62/valo/04,832.99,yes,locked 2006.225.08:16:12.62/valo/05,652.99,yes,locked 2006.225.08:16:12.62/valo/06,772.99,yes,locked 2006.225.08:16:12.62/valo/07,832.99,yes,locked 2006.225.08:16:12.62/valo/08,852.99,yes,locked 2006.225.08:16:13.71/vb/01,04,usb,yes,30,29 2006.225.08:16:13.71/vb/02,04,usb,yes,32,34 2006.225.08:16:13.71/vb/03,04,usb,yes,28,32 2006.225.08:16:13.71/vb/04,04,usb,yes,29,29 2006.225.08:16:13.71/vb/05,04,usb,yes,28,32 2006.225.08:16:13.71/vb/06,04,usb,yes,29,31 2006.225.08:16:13.71/vb/07,04,usb,yes,31,31 2006.225.08:16:13.71/vb/08,04,usb,yes,28,32 2006.225.08:16:13.94/vblo/01,632.99,yes,locked 2006.225.08:16:13.94/vblo/02,640.99,yes,locked 2006.225.08:16:13.94/vblo/03,656.99,yes,locked 2006.225.08:16:13.94/vblo/04,712.99,yes,locked 2006.225.08:16:13.94/vblo/05,744.99,yes,locked 2006.225.08:16:13.94/vblo/06,752.99,yes,locked 2006.225.08:16:13.94/vblo/07,734.99,yes,locked 2006.225.08:16:13.94/vblo/08,744.99,yes,locked 2006.225.08:16:14.09/vabw/8 2006.225.08:16:14.24/vbbw/8 2006.225.08:16:14.33/xfe/off,on,15.0 2006.225.08:16:14.71/ifatt/23,28,28,28 2006.225.08:16:15.07/fmout-gps/S +4.57E-07 2006.225.08:16:15.11:!2006.225.08:17:10 2006.225.08:17:10.00:data_valid=off 2006.225.08:17:10.00:postob 2006.225.08:17:10.17/cable/+6.4049E-03 2006.225.08:17:10.17/wx/28.08,1003.3,74 2006.225.08:17:11.07/fmout-gps/S +4.56E-07 2006.225.08:17:11.07:scan_name=225-0818,k06225,60 2006.225.08:17:11.07:source=1417+385,141946.61,382148.5,2000.0,ccw 2006.225.08:17:11.13#flagr#flagr/antenna,new-source 2006.225.08:17:12.13:checkk5 2006.225.08:17:12.50/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:17:12.88/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:17:13.25/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:17:13.63/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:17:13.99/chk_obsdata//k5ts1/T2250816??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:17:14.36/chk_obsdata//k5ts2/T2250816??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:17:14.72/chk_obsdata//k5ts3/T2250816??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:17:15.09/chk_obsdata//k5ts4/T2250816??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:17:15.79/k5log//k5ts1_log_newline 2006.225.08:17:16.50/k5log//k5ts2_log_newline 2006.225.08:17:17.19/k5log//k5ts3_log_newline 2006.225.08:17:17.88/k5log//k5ts4_log_newline 2006.225.08:17:17.91/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:17:17.91:4f8m12a=2 2006.225.08:17:17.91$4f8m12a/echo=on 2006.225.08:17:17.91$4f8m12a/pcalon 2006.225.08:17:17.91$pcalon/"no phase cal control is implemented here 2006.225.08:17:17.91$4f8m12a/"tpicd=stop 2006.225.08:17:17.91$4f8m12a/vc4f8 2006.225.08:17:17.91$vc4f8/valo=1,532.99 2006.225.08:17:17.91#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.08:17:17.91#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.08:17:17.91#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:17.91#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:17:17.91#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:17:17.91#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:17:17.91#ibcon#enter wrdev, iclass 28, count 0 2006.225.08:17:17.91#ibcon#first serial, iclass 28, count 0 2006.225.08:17:17.91#ibcon#enter sib2, iclass 28, count 0 2006.225.08:17:17.91#ibcon#flushed, iclass 28, count 0 2006.225.08:17:17.91#ibcon#about to write, iclass 28, count 0 2006.225.08:17:17.91#ibcon#wrote, iclass 28, count 0 2006.225.08:17:17.91#ibcon#about to read 3, iclass 28, count 0 2006.225.08:17:17.95#ibcon#read 3, iclass 28, count 0 2006.225.08:17:17.95#ibcon#about to read 4, iclass 28, count 0 2006.225.08:17:17.95#ibcon#read 4, iclass 28, count 0 2006.225.08:17:17.95#ibcon#about to read 5, iclass 28, count 0 2006.225.08:17:17.95#ibcon#read 5, iclass 28, count 0 2006.225.08:17:17.95#ibcon#about to read 6, iclass 28, count 0 2006.225.08:17:17.95#ibcon#read 6, iclass 28, count 0 2006.225.08:17:17.95#ibcon#end of sib2, iclass 28, count 0 2006.225.08:17:17.95#ibcon#*mode == 0, iclass 28, count 0 2006.225.08:17:17.95#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.08:17:17.95#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:17:17.95#ibcon#*before write, iclass 28, count 0 2006.225.08:17:17.95#ibcon#enter sib2, iclass 28, count 0 2006.225.08:17:17.95#ibcon#flushed, iclass 28, count 0 2006.225.08:17:17.95#ibcon#about to write, iclass 28, count 0 2006.225.08:17:17.95#ibcon#wrote, iclass 28, count 0 2006.225.08:17:17.95#ibcon#about to read 3, iclass 28, count 0 2006.225.08:17:18.00#ibcon#read 3, iclass 28, count 0 2006.225.08:17:18.00#ibcon#about to read 4, iclass 28, count 0 2006.225.08:17:18.00#ibcon#read 4, iclass 28, count 0 2006.225.08:17:18.00#ibcon#about to read 5, iclass 28, count 0 2006.225.08:17:18.00#ibcon#read 5, iclass 28, count 0 2006.225.08:17:18.00#ibcon#about to read 6, iclass 28, count 0 2006.225.08:17:18.00#ibcon#read 6, iclass 28, count 0 2006.225.08:17:18.00#ibcon#end of sib2, iclass 28, count 0 2006.225.08:17:18.00#ibcon#*after write, iclass 28, count 0 2006.225.08:17:18.00#ibcon#*before return 0, iclass 28, count 0 2006.225.08:17:18.00#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:17:18.00#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:17:18.00#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.08:17:18.00#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.08:17:18.00$vc4f8/va=1,8 2006.225.08:17:18.00#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.08:17:18.00#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.08:17:18.00#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:18.00#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:17:18.00#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:17:18.00#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:17:18.00#ibcon#enter wrdev, iclass 30, count 2 2006.225.08:17:18.00#ibcon#first serial, iclass 30, count 2 2006.225.08:17:18.00#ibcon#enter sib2, iclass 30, count 2 2006.225.08:17:18.00#ibcon#flushed, iclass 30, count 2 2006.225.08:17:18.00#ibcon#about to write, iclass 30, count 2 2006.225.08:17:18.00#ibcon#wrote, iclass 30, count 2 2006.225.08:17:18.00#ibcon#about to read 3, iclass 30, count 2 2006.225.08:17:18.03#ibcon#read 3, iclass 30, count 2 2006.225.08:17:18.03#ibcon#about to read 4, iclass 30, count 2 2006.225.08:17:18.03#ibcon#read 4, iclass 30, count 2 2006.225.08:17:18.03#ibcon#about to read 5, iclass 30, count 2 2006.225.08:17:18.03#ibcon#read 5, iclass 30, count 2 2006.225.08:17:18.03#ibcon#about to read 6, iclass 30, count 2 2006.225.08:17:18.03#ibcon#read 6, iclass 30, count 2 2006.225.08:17:18.03#ibcon#end of sib2, iclass 30, count 2 2006.225.08:17:18.03#ibcon#*mode == 0, iclass 30, count 2 2006.225.08:17:18.03#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.08:17:18.03#ibcon#[25=AT01-08\r\n] 2006.225.08:17:18.03#ibcon#*before write, iclass 30, count 2 2006.225.08:17:18.03#ibcon#enter sib2, iclass 30, count 2 2006.225.08:17:18.03#ibcon#flushed, iclass 30, count 2 2006.225.08:17:18.03#ibcon#about to write, iclass 30, count 2 2006.225.08:17:18.03#ibcon#wrote, iclass 30, count 2 2006.225.08:17:18.03#ibcon#about to read 3, iclass 30, count 2 2006.225.08:17:18.06#ibcon#read 3, iclass 30, count 2 2006.225.08:17:18.06#ibcon#about to read 4, iclass 30, count 2 2006.225.08:17:18.06#ibcon#read 4, iclass 30, count 2 2006.225.08:17:18.06#ibcon#about to read 5, iclass 30, count 2 2006.225.08:17:18.06#ibcon#read 5, iclass 30, count 2 2006.225.08:17:18.06#ibcon#about to read 6, iclass 30, count 2 2006.225.08:17:18.06#ibcon#read 6, iclass 30, count 2 2006.225.08:17:18.06#ibcon#end of sib2, iclass 30, count 2 2006.225.08:17:18.06#ibcon#*after write, iclass 30, count 2 2006.225.08:17:18.06#ibcon#*before return 0, iclass 30, count 2 2006.225.08:17:18.06#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:17:18.06#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:17:18.06#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.08:17:18.06#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:18.06#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:17:18.18#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:17:18.18#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:17:18.18#ibcon#enter wrdev, iclass 30, count 0 2006.225.08:17:18.18#ibcon#first serial, iclass 30, count 0 2006.225.08:17:18.18#ibcon#enter sib2, iclass 30, count 0 2006.225.08:17:18.18#ibcon#flushed, iclass 30, count 0 2006.225.08:17:18.18#ibcon#about to write, iclass 30, count 0 2006.225.08:17:18.18#ibcon#wrote, iclass 30, count 0 2006.225.08:17:18.18#ibcon#about to read 3, iclass 30, count 0 2006.225.08:17:18.21#ibcon#read 3, iclass 30, count 0 2006.225.08:17:18.21#ibcon#about to read 4, iclass 30, count 0 2006.225.08:17:18.21#ibcon#read 4, iclass 30, count 0 2006.225.08:17:18.21#ibcon#about to read 5, iclass 30, count 0 2006.225.08:17:18.21#ibcon#read 5, iclass 30, count 0 2006.225.08:17:18.21#ibcon#about to read 6, iclass 30, count 0 2006.225.08:17:18.21#ibcon#read 6, iclass 30, count 0 2006.225.08:17:18.21#ibcon#end of sib2, iclass 30, count 0 2006.225.08:17:18.21#ibcon#*mode == 0, iclass 30, count 0 2006.225.08:17:18.21#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.08:17:18.21#ibcon#[25=USB\r\n] 2006.225.08:17:18.21#ibcon#*before write, iclass 30, count 0 2006.225.08:17:18.21#ibcon#enter sib2, iclass 30, count 0 2006.225.08:17:18.21#ibcon#flushed, iclass 30, count 0 2006.225.08:17:18.21#ibcon#about to write, iclass 30, count 0 2006.225.08:17:18.21#ibcon#wrote, iclass 30, count 0 2006.225.08:17:18.21#ibcon#about to read 3, iclass 30, count 0 2006.225.08:17:18.24#ibcon#read 3, iclass 30, count 0 2006.225.08:17:18.24#ibcon#about to read 4, iclass 30, count 0 2006.225.08:17:18.24#ibcon#read 4, iclass 30, count 0 2006.225.08:17:18.24#ibcon#about to read 5, iclass 30, count 0 2006.225.08:17:18.24#ibcon#read 5, iclass 30, count 0 2006.225.08:17:18.24#ibcon#about to read 6, iclass 30, count 0 2006.225.08:17:18.24#ibcon#read 6, iclass 30, count 0 2006.225.08:17:18.24#ibcon#end of sib2, iclass 30, count 0 2006.225.08:17:18.24#ibcon#*after write, iclass 30, count 0 2006.225.08:17:18.24#ibcon#*before return 0, iclass 30, count 0 2006.225.08:17:18.24#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:17:18.24#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:17:18.24#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.08:17:18.24#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.08:17:18.24$vc4f8/valo=2,572.99 2006.225.08:17:18.24#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.08:17:18.24#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.08:17:18.24#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:18.24#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:17:18.24#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:17:18.24#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:17:18.24#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:17:18.24#ibcon#first serial, iclass 32, count 0 2006.225.08:17:18.24#ibcon#enter sib2, iclass 32, count 0 2006.225.08:17:18.24#ibcon#flushed, iclass 32, count 0 2006.225.08:17:18.24#ibcon#about to write, iclass 32, count 0 2006.225.08:17:18.24#ibcon#wrote, iclass 32, count 0 2006.225.08:17:18.24#ibcon#about to read 3, iclass 32, count 0 2006.225.08:17:18.26#ibcon#read 3, iclass 32, count 0 2006.225.08:17:18.26#ibcon#about to read 4, iclass 32, count 0 2006.225.08:17:18.26#ibcon#read 4, iclass 32, count 0 2006.225.08:17:18.26#ibcon#about to read 5, iclass 32, count 0 2006.225.08:17:18.26#ibcon#read 5, iclass 32, count 0 2006.225.08:17:18.26#ibcon#about to read 6, iclass 32, count 0 2006.225.08:17:18.26#ibcon#read 6, iclass 32, count 0 2006.225.08:17:18.26#ibcon#end of sib2, iclass 32, count 0 2006.225.08:17:18.26#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:17:18.26#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:17:18.26#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:17:18.26#ibcon#*before write, iclass 32, count 0 2006.225.08:17:18.26#ibcon#enter sib2, iclass 32, count 0 2006.225.08:17:18.26#ibcon#flushed, iclass 32, count 0 2006.225.08:17:18.26#ibcon#about to write, iclass 32, count 0 2006.225.08:17:18.26#ibcon#wrote, iclass 32, count 0 2006.225.08:17:18.26#ibcon#about to read 3, iclass 32, count 0 2006.225.08:17:18.30#ibcon#read 3, iclass 32, count 0 2006.225.08:17:18.30#ibcon#about to read 4, iclass 32, count 0 2006.225.08:17:18.30#ibcon#read 4, iclass 32, count 0 2006.225.08:17:18.30#ibcon#about to read 5, iclass 32, count 0 2006.225.08:17:18.30#ibcon#read 5, iclass 32, count 0 2006.225.08:17:18.30#ibcon#about to read 6, iclass 32, count 0 2006.225.08:17:18.30#ibcon#read 6, iclass 32, count 0 2006.225.08:17:18.30#ibcon#end of sib2, iclass 32, count 0 2006.225.08:17:18.30#ibcon#*after write, iclass 32, count 0 2006.225.08:17:18.30#ibcon#*before return 0, iclass 32, count 0 2006.225.08:17:18.30#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:17:18.30#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:17:18.30#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:17:18.30#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:17:18.30$vc4f8/va=2,7 2006.225.08:17:18.30#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.08:17:18.30#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.08:17:18.30#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:18.30#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:17:18.36#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:17:18.36#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:17:18.36#ibcon#enter wrdev, iclass 34, count 2 2006.225.08:17:18.36#ibcon#first serial, iclass 34, count 2 2006.225.08:17:18.36#ibcon#enter sib2, iclass 34, count 2 2006.225.08:17:18.36#ibcon#flushed, iclass 34, count 2 2006.225.08:17:18.36#ibcon#about to write, iclass 34, count 2 2006.225.08:17:18.36#ibcon#wrote, iclass 34, count 2 2006.225.08:17:18.36#ibcon#about to read 3, iclass 34, count 2 2006.225.08:17:18.38#ibcon#read 3, iclass 34, count 2 2006.225.08:17:18.38#ibcon#about to read 4, iclass 34, count 2 2006.225.08:17:18.38#ibcon#read 4, iclass 34, count 2 2006.225.08:17:18.38#ibcon#about to read 5, iclass 34, count 2 2006.225.08:17:18.38#ibcon#read 5, iclass 34, count 2 2006.225.08:17:18.38#ibcon#about to read 6, iclass 34, count 2 2006.225.08:17:18.38#ibcon#read 6, iclass 34, count 2 2006.225.08:17:18.38#ibcon#end of sib2, iclass 34, count 2 2006.225.08:17:18.38#ibcon#*mode == 0, iclass 34, count 2 2006.225.08:17:18.38#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.08:17:18.38#ibcon#[25=AT02-07\r\n] 2006.225.08:17:18.38#ibcon#*before write, iclass 34, count 2 2006.225.08:17:18.38#ibcon#enter sib2, iclass 34, count 2 2006.225.08:17:18.38#ibcon#flushed, iclass 34, count 2 2006.225.08:17:18.38#ibcon#about to write, iclass 34, count 2 2006.225.08:17:18.38#ibcon#wrote, iclass 34, count 2 2006.225.08:17:18.38#ibcon#about to read 3, iclass 34, count 2 2006.225.08:17:18.41#ibcon#read 3, iclass 34, count 2 2006.225.08:17:18.41#ibcon#about to read 4, iclass 34, count 2 2006.225.08:17:18.41#ibcon#read 4, iclass 34, count 2 2006.225.08:17:18.41#ibcon#about to read 5, iclass 34, count 2 2006.225.08:17:18.41#ibcon#read 5, iclass 34, count 2 2006.225.08:17:18.41#ibcon#about to read 6, iclass 34, count 2 2006.225.08:17:18.41#ibcon#read 6, iclass 34, count 2 2006.225.08:17:18.41#ibcon#end of sib2, iclass 34, count 2 2006.225.08:17:18.41#ibcon#*after write, iclass 34, count 2 2006.225.08:17:18.41#ibcon#*before return 0, iclass 34, count 2 2006.225.08:17:18.41#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:17:18.41#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:17:18.41#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.08:17:18.41#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:18.41#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:17:18.53#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:17:18.53#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:17:18.53#ibcon#enter wrdev, iclass 34, count 0 2006.225.08:17:18.53#ibcon#first serial, iclass 34, count 0 2006.225.08:17:18.53#ibcon#enter sib2, iclass 34, count 0 2006.225.08:17:18.53#ibcon#flushed, iclass 34, count 0 2006.225.08:17:18.53#ibcon#about to write, iclass 34, count 0 2006.225.08:17:18.53#ibcon#wrote, iclass 34, count 0 2006.225.08:17:18.53#ibcon#about to read 3, iclass 34, count 0 2006.225.08:17:18.55#ibcon#read 3, iclass 34, count 0 2006.225.08:17:18.55#ibcon#about to read 4, iclass 34, count 0 2006.225.08:17:18.55#ibcon#read 4, iclass 34, count 0 2006.225.08:17:18.55#ibcon#about to read 5, iclass 34, count 0 2006.225.08:17:18.55#ibcon#read 5, iclass 34, count 0 2006.225.08:17:18.55#ibcon#about to read 6, iclass 34, count 0 2006.225.08:17:18.55#ibcon#read 6, iclass 34, count 0 2006.225.08:17:18.55#ibcon#end of sib2, iclass 34, count 0 2006.225.08:17:18.55#ibcon#*mode == 0, iclass 34, count 0 2006.225.08:17:18.55#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.08:17:18.55#ibcon#[25=USB\r\n] 2006.225.08:17:18.55#ibcon#*before write, iclass 34, count 0 2006.225.08:17:18.55#ibcon#enter sib2, iclass 34, count 0 2006.225.08:17:18.55#ibcon#flushed, iclass 34, count 0 2006.225.08:17:18.55#ibcon#about to write, iclass 34, count 0 2006.225.08:17:18.55#ibcon#wrote, iclass 34, count 0 2006.225.08:17:18.55#ibcon#about to read 3, iclass 34, count 0 2006.225.08:17:18.58#ibcon#read 3, iclass 34, count 0 2006.225.08:17:18.58#ibcon#about to read 4, iclass 34, count 0 2006.225.08:17:18.58#ibcon#read 4, iclass 34, count 0 2006.225.08:17:18.58#ibcon#about to read 5, iclass 34, count 0 2006.225.08:17:18.58#ibcon#read 5, iclass 34, count 0 2006.225.08:17:18.58#ibcon#about to read 6, iclass 34, count 0 2006.225.08:17:18.58#ibcon#read 6, iclass 34, count 0 2006.225.08:17:18.58#ibcon#end of sib2, iclass 34, count 0 2006.225.08:17:18.58#ibcon#*after write, iclass 34, count 0 2006.225.08:17:18.58#ibcon#*before return 0, iclass 34, count 0 2006.225.08:17:18.58#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:17:18.58#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:17:18.58#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.08:17:18.58#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.08:17:18.58$vc4f8/valo=3,672.99 2006.225.08:17:18.58#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.08:17:18.58#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.08:17:18.58#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:18.58#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:17:18.58#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:17:18.58#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:17:18.58#ibcon#enter wrdev, iclass 36, count 0 2006.225.08:17:18.58#ibcon#first serial, iclass 36, count 0 2006.225.08:17:18.58#ibcon#enter sib2, iclass 36, count 0 2006.225.08:17:18.58#ibcon#flushed, iclass 36, count 0 2006.225.08:17:18.58#ibcon#about to write, iclass 36, count 0 2006.225.08:17:18.58#ibcon#wrote, iclass 36, count 0 2006.225.08:17:18.58#ibcon#about to read 3, iclass 36, count 0 2006.225.08:17:18.61#ibcon#read 3, iclass 36, count 0 2006.225.08:17:18.61#ibcon#about to read 4, iclass 36, count 0 2006.225.08:17:18.61#ibcon#read 4, iclass 36, count 0 2006.225.08:17:18.61#ibcon#about to read 5, iclass 36, count 0 2006.225.08:17:18.61#ibcon#read 5, iclass 36, count 0 2006.225.08:17:18.61#ibcon#about to read 6, iclass 36, count 0 2006.225.08:17:18.61#ibcon#read 6, iclass 36, count 0 2006.225.08:17:18.61#ibcon#end of sib2, iclass 36, count 0 2006.225.08:17:18.61#ibcon#*mode == 0, iclass 36, count 0 2006.225.08:17:18.61#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.08:17:18.61#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:17:18.61#ibcon#*before write, iclass 36, count 0 2006.225.08:17:18.61#ibcon#enter sib2, iclass 36, count 0 2006.225.08:17:18.61#ibcon#flushed, iclass 36, count 0 2006.225.08:17:18.61#ibcon#about to write, iclass 36, count 0 2006.225.08:17:18.61#ibcon#wrote, iclass 36, count 0 2006.225.08:17:18.61#ibcon#about to read 3, iclass 36, count 0 2006.225.08:17:18.65#ibcon#read 3, iclass 36, count 0 2006.225.08:17:18.65#ibcon#about to read 4, iclass 36, count 0 2006.225.08:17:18.65#ibcon#read 4, iclass 36, count 0 2006.225.08:17:18.65#ibcon#about to read 5, iclass 36, count 0 2006.225.08:17:18.65#ibcon#read 5, iclass 36, count 0 2006.225.08:17:18.65#ibcon#about to read 6, iclass 36, count 0 2006.225.08:17:18.65#ibcon#read 6, iclass 36, count 0 2006.225.08:17:18.65#ibcon#end of sib2, iclass 36, count 0 2006.225.08:17:18.65#ibcon#*after write, iclass 36, count 0 2006.225.08:17:18.65#ibcon#*before return 0, iclass 36, count 0 2006.225.08:17:18.65#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:17:18.65#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:17:18.65#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.08:17:18.65#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.08:17:18.65$vc4f8/va=3,6 2006.225.08:17:18.65#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.08:17:18.65#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.08:17:18.65#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:18.65#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:17:18.70#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:17:18.70#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:17:18.70#ibcon#enter wrdev, iclass 38, count 2 2006.225.08:17:18.70#ibcon#first serial, iclass 38, count 2 2006.225.08:17:18.70#ibcon#enter sib2, iclass 38, count 2 2006.225.08:17:18.70#ibcon#flushed, iclass 38, count 2 2006.225.08:17:18.70#ibcon#about to write, iclass 38, count 2 2006.225.08:17:18.70#ibcon#wrote, iclass 38, count 2 2006.225.08:17:18.70#ibcon#about to read 3, iclass 38, count 2 2006.225.08:17:18.72#ibcon#read 3, iclass 38, count 2 2006.225.08:17:18.72#ibcon#about to read 4, iclass 38, count 2 2006.225.08:17:18.72#ibcon#read 4, iclass 38, count 2 2006.225.08:17:18.72#ibcon#about to read 5, iclass 38, count 2 2006.225.08:17:18.72#ibcon#read 5, iclass 38, count 2 2006.225.08:17:18.72#ibcon#about to read 6, iclass 38, count 2 2006.225.08:17:18.72#ibcon#read 6, iclass 38, count 2 2006.225.08:17:18.72#ibcon#end of sib2, iclass 38, count 2 2006.225.08:17:18.72#ibcon#*mode == 0, iclass 38, count 2 2006.225.08:17:18.72#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.08:17:18.72#ibcon#[25=AT03-06\r\n] 2006.225.08:17:18.72#ibcon#*before write, iclass 38, count 2 2006.225.08:17:18.72#ibcon#enter sib2, iclass 38, count 2 2006.225.08:17:18.72#ibcon#flushed, iclass 38, count 2 2006.225.08:17:18.72#ibcon#about to write, iclass 38, count 2 2006.225.08:17:18.72#ibcon#wrote, iclass 38, count 2 2006.225.08:17:18.72#ibcon#about to read 3, iclass 38, count 2 2006.225.08:17:18.75#ibcon#read 3, iclass 38, count 2 2006.225.08:17:18.75#ibcon#about to read 4, iclass 38, count 2 2006.225.08:17:18.75#ibcon#read 4, iclass 38, count 2 2006.225.08:17:18.75#ibcon#about to read 5, iclass 38, count 2 2006.225.08:17:18.75#ibcon#read 5, iclass 38, count 2 2006.225.08:17:18.75#ibcon#about to read 6, iclass 38, count 2 2006.225.08:17:18.75#ibcon#read 6, iclass 38, count 2 2006.225.08:17:18.75#ibcon#end of sib2, iclass 38, count 2 2006.225.08:17:18.75#ibcon#*after write, iclass 38, count 2 2006.225.08:17:18.75#ibcon#*before return 0, iclass 38, count 2 2006.225.08:17:18.75#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:17:18.75#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:17:18.75#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.08:17:18.75#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:18.75#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:17:18.87#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:17:18.87#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:17:18.87#ibcon#enter wrdev, iclass 38, count 0 2006.225.08:17:18.87#ibcon#first serial, iclass 38, count 0 2006.225.08:17:18.87#ibcon#enter sib2, iclass 38, count 0 2006.225.08:17:18.87#ibcon#flushed, iclass 38, count 0 2006.225.08:17:18.87#ibcon#about to write, iclass 38, count 0 2006.225.08:17:18.87#ibcon#wrote, iclass 38, count 0 2006.225.08:17:18.87#ibcon#about to read 3, iclass 38, count 0 2006.225.08:17:18.89#ibcon#read 3, iclass 38, count 0 2006.225.08:17:18.89#ibcon#about to read 4, iclass 38, count 0 2006.225.08:17:18.89#ibcon#read 4, iclass 38, count 0 2006.225.08:17:18.89#ibcon#about to read 5, iclass 38, count 0 2006.225.08:17:18.89#ibcon#read 5, iclass 38, count 0 2006.225.08:17:18.89#ibcon#about to read 6, iclass 38, count 0 2006.225.08:17:18.89#ibcon#read 6, iclass 38, count 0 2006.225.08:17:18.89#ibcon#end of sib2, iclass 38, count 0 2006.225.08:17:18.89#ibcon#*mode == 0, iclass 38, count 0 2006.225.08:17:18.89#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.08:17:18.89#ibcon#[25=USB\r\n] 2006.225.08:17:18.89#ibcon#*before write, iclass 38, count 0 2006.225.08:17:18.89#ibcon#enter sib2, iclass 38, count 0 2006.225.08:17:18.89#ibcon#flushed, iclass 38, count 0 2006.225.08:17:18.89#ibcon#about to write, iclass 38, count 0 2006.225.08:17:18.89#ibcon#wrote, iclass 38, count 0 2006.225.08:17:18.89#ibcon#about to read 3, iclass 38, count 0 2006.225.08:17:18.92#ibcon#read 3, iclass 38, count 0 2006.225.08:17:18.92#ibcon#about to read 4, iclass 38, count 0 2006.225.08:17:18.92#ibcon#read 4, iclass 38, count 0 2006.225.08:17:18.92#ibcon#about to read 5, iclass 38, count 0 2006.225.08:17:18.92#ibcon#read 5, iclass 38, count 0 2006.225.08:17:18.92#ibcon#about to read 6, iclass 38, count 0 2006.225.08:17:18.92#ibcon#read 6, iclass 38, count 0 2006.225.08:17:18.92#ibcon#end of sib2, iclass 38, count 0 2006.225.08:17:18.92#ibcon#*after write, iclass 38, count 0 2006.225.08:17:18.92#ibcon#*before return 0, iclass 38, count 0 2006.225.08:17:18.92#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:17:18.92#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:17:18.92#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.08:17:18.92#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.08:17:18.92$vc4f8/valo=4,832.99 2006.225.08:17:18.92#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.08:17:18.92#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.08:17:18.92#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:18.92#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:17:18.92#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:17:18.92#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:17:18.92#ibcon#enter wrdev, iclass 40, count 0 2006.225.08:17:18.92#ibcon#first serial, iclass 40, count 0 2006.225.08:17:18.92#ibcon#enter sib2, iclass 40, count 0 2006.225.08:17:18.92#ibcon#flushed, iclass 40, count 0 2006.225.08:17:18.92#ibcon#about to write, iclass 40, count 0 2006.225.08:17:18.92#ibcon#wrote, iclass 40, count 0 2006.225.08:17:18.92#ibcon#about to read 3, iclass 40, count 0 2006.225.08:17:18.94#ibcon#read 3, iclass 40, count 0 2006.225.08:17:18.94#ibcon#about to read 4, iclass 40, count 0 2006.225.08:17:18.94#ibcon#read 4, iclass 40, count 0 2006.225.08:17:18.94#ibcon#about to read 5, iclass 40, count 0 2006.225.08:17:18.94#ibcon#read 5, iclass 40, count 0 2006.225.08:17:18.94#ibcon#about to read 6, iclass 40, count 0 2006.225.08:17:18.94#ibcon#read 6, iclass 40, count 0 2006.225.08:17:18.94#ibcon#end of sib2, iclass 40, count 0 2006.225.08:17:18.94#ibcon#*mode == 0, iclass 40, count 0 2006.225.08:17:18.94#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.08:17:18.94#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:17:18.94#ibcon#*before write, iclass 40, count 0 2006.225.08:17:18.94#ibcon#enter sib2, iclass 40, count 0 2006.225.08:17:18.94#ibcon#flushed, iclass 40, count 0 2006.225.08:17:18.94#ibcon#about to write, iclass 40, count 0 2006.225.08:17:18.94#ibcon#wrote, iclass 40, count 0 2006.225.08:17:18.94#ibcon#about to read 3, iclass 40, count 0 2006.225.08:17:18.98#ibcon#read 3, iclass 40, count 0 2006.225.08:17:18.98#ibcon#about to read 4, iclass 40, count 0 2006.225.08:17:18.98#ibcon#read 4, iclass 40, count 0 2006.225.08:17:18.98#ibcon#about to read 5, iclass 40, count 0 2006.225.08:17:18.98#ibcon#read 5, iclass 40, count 0 2006.225.08:17:18.98#ibcon#about to read 6, iclass 40, count 0 2006.225.08:17:18.98#ibcon#read 6, iclass 40, count 0 2006.225.08:17:18.98#ibcon#end of sib2, iclass 40, count 0 2006.225.08:17:18.98#ibcon#*after write, iclass 40, count 0 2006.225.08:17:18.98#ibcon#*before return 0, iclass 40, count 0 2006.225.08:17:18.98#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:17:18.98#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:17:18.98#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.08:17:18.98#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.08:17:18.98$vc4f8/va=4,7 2006.225.08:17:18.98#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.08:17:18.98#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.08:17:18.98#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:18.98#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:17:19.04#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:17:19.04#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:17:19.04#ibcon#enter wrdev, iclass 4, count 2 2006.225.08:17:19.04#ibcon#first serial, iclass 4, count 2 2006.225.08:17:19.04#ibcon#enter sib2, iclass 4, count 2 2006.225.08:17:19.04#ibcon#flushed, iclass 4, count 2 2006.225.08:17:19.04#ibcon#about to write, iclass 4, count 2 2006.225.08:17:19.04#ibcon#wrote, iclass 4, count 2 2006.225.08:17:19.04#ibcon#about to read 3, iclass 4, count 2 2006.225.08:17:19.06#ibcon#read 3, iclass 4, count 2 2006.225.08:17:19.06#ibcon#about to read 4, iclass 4, count 2 2006.225.08:17:19.06#ibcon#read 4, iclass 4, count 2 2006.225.08:17:19.06#ibcon#about to read 5, iclass 4, count 2 2006.225.08:17:19.06#ibcon#read 5, iclass 4, count 2 2006.225.08:17:19.06#ibcon#about to read 6, iclass 4, count 2 2006.225.08:17:19.06#ibcon#read 6, iclass 4, count 2 2006.225.08:17:19.06#ibcon#end of sib2, iclass 4, count 2 2006.225.08:17:19.06#ibcon#*mode == 0, iclass 4, count 2 2006.225.08:17:19.06#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.08:17:19.06#ibcon#[25=AT04-07\r\n] 2006.225.08:17:19.06#ibcon#*before write, iclass 4, count 2 2006.225.08:17:19.06#ibcon#enter sib2, iclass 4, count 2 2006.225.08:17:19.06#ibcon#flushed, iclass 4, count 2 2006.225.08:17:19.06#ibcon#about to write, iclass 4, count 2 2006.225.08:17:19.06#ibcon#wrote, iclass 4, count 2 2006.225.08:17:19.06#ibcon#about to read 3, iclass 4, count 2 2006.225.08:17:19.09#abcon#<5=/04 2.3 4.6 28.09 731003.3\r\n> 2006.225.08:17:19.09#ibcon#read 3, iclass 4, count 2 2006.225.08:17:19.09#ibcon#about to read 4, iclass 4, count 2 2006.225.08:17:19.09#ibcon#read 4, iclass 4, count 2 2006.225.08:17:19.09#ibcon#about to read 5, iclass 4, count 2 2006.225.08:17:19.09#ibcon#read 5, iclass 4, count 2 2006.225.08:17:19.09#ibcon#about to read 6, iclass 4, count 2 2006.225.08:17:19.09#ibcon#read 6, iclass 4, count 2 2006.225.08:17:19.09#ibcon#end of sib2, iclass 4, count 2 2006.225.08:17:19.09#ibcon#*after write, iclass 4, count 2 2006.225.08:17:19.09#ibcon#*before return 0, iclass 4, count 2 2006.225.08:17:19.09#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:17:19.09#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:17:19.09#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.08:17:19.09#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:19.09#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:17:19.11#abcon#{5=INTERFACE CLEAR} 2006.225.08:17:19.17#abcon#[5=S1D000X0/0*\r\n] 2006.225.08:17:19.21#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:17:19.21#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:17:19.21#ibcon#enter wrdev, iclass 4, count 0 2006.225.08:17:19.21#ibcon#first serial, iclass 4, count 0 2006.225.08:17:19.21#ibcon#enter sib2, iclass 4, count 0 2006.225.08:17:19.21#ibcon#flushed, iclass 4, count 0 2006.225.08:17:19.21#ibcon#about to write, iclass 4, count 0 2006.225.08:17:19.21#ibcon#wrote, iclass 4, count 0 2006.225.08:17:19.21#ibcon#about to read 3, iclass 4, count 0 2006.225.08:17:19.23#ibcon#read 3, iclass 4, count 0 2006.225.08:17:19.23#ibcon#about to read 4, iclass 4, count 0 2006.225.08:17:19.23#ibcon#read 4, iclass 4, count 0 2006.225.08:17:19.23#ibcon#about to read 5, iclass 4, count 0 2006.225.08:17:19.23#ibcon#read 5, iclass 4, count 0 2006.225.08:17:19.23#ibcon#about to read 6, iclass 4, count 0 2006.225.08:17:19.23#ibcon#read 6, iclass 4, count 0 2006.225.08:17:19.23#ibcon#end of sib2, iclass 4, count 0 2006.225.08:17:19.23#ibcon#*mode == 0, iclass 4, count 0 2006.225.08:17:19.23#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.08:17:19.23#ibcon#[25=USB\r\n] 2006.225.08:17:19.23#ibcon#*before write, iclass 4, count 0 2006.225.08:17:19.23#ibcon#enter sib2, iclass 4, count 0 2006.225.08:17:19.23#ibcon#flushed, iclass 4, count 0 2006.225.08:17:19.23#ibcon#about to write, iclass 4, count 0 2006.225.08:17:19.23#ibcon#wrote, iclass 4, count 0 2006.225.08:17:19.23#ibcon#about to read 3, iclass 4, count 0 2006.225.08:17:19.26#ibcon#read 3, iclass 4, count 0 2006.225.08:17:19.26#ibcon#about to read 4, iclass 4, count 0 2006.225.08:17:19.26#ibcon#read 4, iclass 4, count 0 2006.225.08:17:19.26#ibcon#about to read 5, iclass 4, count 0 2006.225.08:17:19.26#ibcon#read 5, iclass 4, count 0 2006.225.08:17:19.26#ibcon#about to read 6, iclass 4, count 0 2006.225.08:17:19.26#ibcon#read 6, iclass 4, count 0 2006.225.08:17:19.26#ibcon#end of sib2, iclass 4, count 0 2006.225.08:17:19.26#ibcon#*after write, iclass 4, count 0 2006.225.08:17:19.26#ibcon#*before return 0, iclass 4, count 0 2006.225.08:17:19.26#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:17:19.26#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:17:19.26#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.08:17:19.26#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.08:17:19.26$vc4f8/valo=5,652.99 2006.225.08:17:19.26#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.08:17:19.26#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.08:17:19.26#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:19.26#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:17:19.26#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:17:19.26#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:17:19.26#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:17:19.26#ibcon#first serial, iclass 12, count 0 2006.225.08:17:19.26#ibcon#enter sib2, iclass 12, count 0 2006.225.08:17:19.26#ibcon#flushed, iclass 12, count 0 2006.225.08:17:19.26#ibcon#about to write, iclass 12, count 0 2006.225.08:17:19.26#ibcon#wrote, iclass 12, count 0 2006.225.08:17:19.26#ibcon#about to read 3, iclass 12, count 0 2006.225.08:17:19.28#ibcon#read 3, iclass 12, count 0 2006.225.08:17:19.28#ibcon#about to read 4, iclass 12, count 0 2006.225.08:17:19.28#ibcon#read 4, iclass 12, count 0 2006.225.08:17:19.28#ibcon#about to read 5, iclass 12, count 0 2006.225.08:17:19.28#ibcon#read 5, iclass 12, count 0 2006.225.08:17:19.28#ibcon#about to read 6, iclass 12, count 0 2006.225.08:17:19.28#ibcon#read 6, iclass 12, count 0 2006.225.08:17:19.28#ibcon#end of sib2, iclass 12, count 0 2006.225.08:17:19.28#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:17:19.28#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:17:19.28#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:17:19.28#ibcon#*before write, iclass 12, count 0 2006.225.08:17:19.28#ibcon#enter sib2, iclass 12, count 0 2006.225.08:17:19.28#ibcon#flushed, iclass 12, count 0 2006.225.08:17:19.28#ibcon#about to write, iclass 12, count 0 2006.225.08:17:19.28#ibcon#wrote, iclass 12, count 0 2006.225.08:17:19.28#ibcon#about to read 3, iclass 12, count 0 2006.225.08:17:19.32#ibcon#read 3, iclass 12, count 0 2006.225.08:17:19.32#ibcon#about to read 4, iclass 12, count 0 2006.225.08:17:19.32#ibcon#read 4, iclass 12, count 0 2006.225.08:17:19.32#ibcon#about to read 5, iclass 12, count 0 2006.225.08:17:19.32#ibcon#read 5, iclass 12, count 0 2006.225.08:17:19.32#ibcon#about to read 6, iclass 12, count 0 2006.225.08:17:19.32#ibcon#read 6, iclass 12, count 0 2006.225.08:17:19.32#ibcon#end of sib2, iclass 12, count 0 2006.225.08:17:19.32#ibcon#*after write, iclass 12, count 0 2006.225.08:17:19.32#ibcon#*before return 0, iclass 12, count 0 2006.225.08:17:19.32#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:17:19.32#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:17:19.32#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:17:19.32#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:17:19.32$vc4f8/va=5,7 2006.225.08:17:19.32#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.225.08:17:19.32#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.225.08:17:19.32#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:19.32#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:17:19.38#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:17:19.38#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:17:19.38#ibcon#enter wrdev, iclass 14, count 2 2006.225.08:17:19.38#ibcon#first serial, iclass 14, count 2 2006.225.08:17:19.38#ibcon#enter sib2, iclass 14, count 2 2006.225.08:17:19.38#ibcon#flushed, iclass 14, count 2 2006.225.08:17:19.38#ibcon#about to write, iclass 14, count 2 2006.225.08:17:19.38#ibcon#wrote, iclass 14, count 2 2006.225.08:17:19.38#ibcon#about to read 3, iclass 14, count 2 2006.225.08:17:19.40#ibcon#read 3, iclass 14, count 2 2006.225.08:17:19.40#ibcon#about to read 4, iclass 14, count 2 2006.225.08:17:19.40#ibcon#read 4, iclass 14, count 2 2006.225.08:17:19.40#ibcon#about to read 5, iclass 14, count 2 2006.225.08:17:19.40#ibcon#read 5, iclass 14, count 2 2006.225.08:17:19.40#ibcon#about to read 6, iclass 14, count 2 2006.225.08:17:19.40#ibcon#read 6, iclass 14, count 2 2006.225.08:17:19.40#ibcon#end of sib2, iclass 14, count 2 2006.225.08:17:19.40#ibcon#*mode == 0, iclass 14, count 2 2006.225.08:17:19.40#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.225.08:17:19.40#ibcon#[25=AT05-07\r\n] 2006.225.08:17:19.40#ibcon#*before write, iclass 14, count 2 2006.225.08:17:19.40#ibcon#enter sib2, iclass 14, count 2 2006.225.08:17:19.40#ibcon#flushed, iclass 14, count 2 2006.225.08:17:19.40#ibcon#about to write, iclass 14, count 2 2006.225.08:17:19.40#ibcon#wrote, iclass 14, count 2 2006.225.08:17:19.40#ibcon#about to read 3, iclass 14, count 2 2006.225.08:17:19.43#ibcon#read 3, iclass 14, count 2 2006.225.08:17:19.43#ibcon#about to read 4, iclass 14, count 2 2006.225.08:17:19.43#ibcon#read 4, iclass 14, count 2 2006.225.08:17:19.43#ibcon#about to read 5, iclass 14, count 2 2006.225.08:17:19.43#ibcon#read 5, iclass 14, count 2 2006.225.08:17:19.43#ibcon#about to read 6, iclass 14, count 2 2006.225.08:17:19.43#ibcon#read 6, iclass 14, count 2 2006.225.08:17:19.43#ibcon#end of sib2, iclass 14, count 2 2006.225.08:17:19.43#ibcon#*after write, iclass 14, count 2 2006.225.08:17:19.43#ibcon#*before return 0, iclass 14, count 2 2006.225.08:17:19.43#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:17:19.43#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:17:19.43#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.225.08:17:19.43#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:19.43#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:17:19.55#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:17:19.55#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:17:19.55#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:17:19.55#ibcon#first serial, iclass 14, count 0 2006.225.08:17:19.55#ibcon#enter sib2, iclass 14, count 0 2006.225.08:17:19.55#ibcon#flushed, iclass 14, count 0 2006.225.08:17:19.55#ibcon#about to write, iclass 14, count 0 2006.225.08:17:19.55#ibcon#wrote, iclass 14, count 0 2006.225.08:17:19.55#ibcon#about to read 3, iclass 14, count 0 2006.225.08:17:19.57#ibcon#read 3, iclass 14, count 0 2006.225.08:17:19.57#ibcon#about to read 4, iclass 14, count 0 2006.225.08:17:19.57#ibcon#read 4, iclass 14, count 0 2006.225.08:17:19.57#ibcon#about to read 5, iclass 14, count 0 2006.225.08:17:19.57#ibcon#read 5, iclass 14, count 0 2006.225.08:17:19.57#ibcon#about to read 6, iclass 14, count 0 2006.225.08:17:19.57#ibcon#read 6, iclass 14, count 0 2006.225.08:17:19.57#ibcon#end of sib2, iclass 14, count 0 2006.225.08:17:19.57#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:17:19.57#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:17:19.57#ibcon#[25=USB\r\n] 2006.225.08:17:19.57#ibcon#*before write, iclass 14, count 0 2006.225.08:17:19.57#ibcon#enter sib2, iclass 14, count 0 2006.225.08:17:19.57#ibcon#flushed, iclass 14, count 0 2006.225.08:17:19.57#ibcon#about to write, iclass 14, count 0 2006.225.08:17:19.57#ibcon#wrote, iclass 14, count 0 2006.225.08:17:19.57#ibcon#about to read 3, iclass 14, count 0 2006.225.08:17:19.60#ibcon#read 3, iclass 14, count 0 2006.225.08:17:19.60#ibcon#about to read 4, iclass 14, count 0 2006.225.08:17:19.60#ibcon#read 4, iclass 14, count 0 2006.225.08:17:19.60#ibcon#about to read 5, iclass 14, count 0 2006.225.08:17:19.60#ibcon#read 5, iclass 14, count 0 2006.225.08:17:19.60#ibcon#about to read 6, iclass 14, count 0 2006.225.08:17:19.60#ibcon#read 6, iclass 14, count 0 2006.225.08:17:19.60#ibcon#end of sib2, iclass 14, count 0 2006.225.08:17:19.60#ibcon#*after write, iclass 14, count 0 2006.225.08:17:19.60#ibcon#*before return 0, iclass 14, count 0 2006.225.08:17:19.60#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:17:19.60#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:17:19.60#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:17:19.60#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:17:19.60$vc4f8/valo=6,772.99 2006.225.08:17:19.60#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.08:17:19.60#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.08:17:19.60#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:19.60#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:17:19.60#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:17:19.60#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:17:19.60#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:17:19.60#ibcon#first serial, iclass 16, count 0 2006.225.08:17:19.60#ibcon#enter sib2, iclass 16, count 0 2006.225.08:17:19.60#ibcon#flushed, iclass 16, count 0 2006.225.08:17:19.60#ibcon#about to write, iclass 16, count 0 2006.225.08:17:19.60#ibcon#wrote, iclass 16, count 0 2006.225.08:17:19.60#ibcon#about to read 3, iclass 16, count 0 2006.225.08:17:19.62#ibcon#read 3, iclass 16, count 0 2006.225.08:17:19.62#ibcon#about to read 4, iclass 16, count 0 2006.225.08:17:19.62#ibcon#read 4, iclass 16, count 0 2006.225.08:17:19.62#ibcon#about to read 5, iclass 16, count 0 2006.225.08:17:19.62#ibcon#read 5, iclass 16, count 0 2006.225.08:17:19.62#ibcon#about to read 6, iclass 16, count 0 2006.225.08:17:19.62#ibcon#read 6, iclass 16, count 0 2006.225.08:17:19.62#ibcon#end of sib2, iclass 16, count 0 2006.225.08:17:19.62#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:17:19.62#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:17:19.62#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:17:19.62#ibcon#*before write, iclass 16, count 0 2006.225.08:17:19.62#ibcon#enter sib2, iclass 16, count 0 2006.225.08:17:19.62#ibcon#flushed, iclass 16, count 0 2006.225.08:17:19.62#ibcon#about to write, iclass 16, count 0 2006.225.08:17:19.62#ibcon#wrote, iclass 16, count 0 2006.225.08:17:19.62#ibcon#about to read 3, iclass 16, count 0 2006.225.08:17:19.66#ibcon#read 3, iclass 16, count 0 2006.225.08:17:19.66#ibcon#about to read 4, iclass 16, count 0 2006.225.08:17:19.66#ibcon#read 4, iclass 16, count 0 2006.225.08:17:19.66#ibcon#about to read 5, iclass 16, count 0 2006.225.08:17:19.66#ibcon#read 5, iclass 16, count 0 2006.225.08:17:19.66#ibcon#about to read 6, iclass 16, count 0 2006.225.08:17:19.66#ibcon#read 6, iclass 16, count 0 2006.225.08:17:19.66#ibcon#end of sib2, iclass 16, count 0 2006.225.08:17:19.66#ibcon#*after write, iclass 16, count 0 2006.225.08:17:19.66#ibcon#*before return 0, iclass 16, count 0 2006.225.08:17:19.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:17:19.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:17:19.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:17:19.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:17:19.66$vc4f8/va=6,6 2006.225.08:17:19.66#ibcon#iclass 18 nclrec 2 cls_cnt 3 2006.225.08:17:19.66#ibcon#iclass 18 iclrec 1 cls_cnt 3 2006.225.08:17:19.66#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:19.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:17:19.72#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:17:19.72#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:17:19.72#ibcon#enter wrdev, iclass 18, count 2 2006.225.08:17:19.72#ibcon#first serial, iclass 18, count 2 2006.225.08:17:19.72#ibcon#enter sib2, iclass 18, count 2 2006.225.08:17:19.72#ibcon#flushed, iclass 18, count 2 2006.225.08:17:19.72#ibcon#about to write, iclass 18, count 2 2006.225.08:17:19.72#ibcon#wrote, iclass 18, count 2 2006.225.08:17:19.72#ibcon#about to read 3, iclass 18, count 2 2006.225.08:17:19.74#ibcon#read 3, iclass 18, count 2 2006.225.08:17:19.74#ibcon#about to read 4, iclass 18, count 2 2006.225.08:17:19.74#ibcon#read 4, iclass 18, count 2 2006.225.08:17:19.74#ibcon#about to read 5, iclass 18, count 2 2006.225.08:17:19.74#ibcon#read 5, iclass 18, count 2 2006.225.08:17:19.74#ibcon#about to read 6, iclass 18, count 2 2006.225.08:17:19.74#ibcon#read 6, iclass 18, count 2 2006.225.08:17:19.74#ibcon#end of sib2, iclass 18, count 2 2006.225.08:17:19.74#ibcon#*mode == 0, iclass 18, count 2 2006.225.08:17:19.74#ibcon#*mode == 0 && serial, iclass 18, count 2 2006.225.08:17:19.74#ibcon#[25=AT06-06\r\n] 2006.225.08:17:19.74#ibcon#*before write, iclass 18, count 2 2006.225.08:17:19.74#ibcon#enter sib2, iclass 18, count 2 2006.225.08:17:19.74#ibcon#flushed, iclass 18, count 2 2006.225.08:17:19.74#ibcon#about to write, iclass 18, count 2 2006.225.08:17:19.74#ibcon#wrote, iclass 18, count 2 2006.225.08:17:19.74#ibcon#about to read 3, iclass 18, count 2 2006.225.08:17:19.77#ibcon#read 3, iclass 18, count 2 2006.225.08:17:19.77#ibcon#about to read 4, iclass 18, count 2 2006.225.08:17:19.77#ibcon#read 4, iclass 18, count 2 2006.225.08:17:19.77#ibcon#about to read 5, iclass 18, count 2 2006.225.08:17:19.77#ibcon#read 5, iclass 18, count 2 2006.225.08:17:19.77#ibcon#about to read 6, iclass 18, count 2 2006.225.08:17:19.77#ibcon#read 6, iclass 18, count 2 2006.225.08:17:19.77#ibcon#end of sib2, iclass 18, count 2 2006.225.08:17:19.77#ibcon#*after write, iclass 18, count 2 2006.225.08:17:19.77#ibcon#*before return 0, iclass 18, count 2 2006.225.08:17:19.77#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:17:19.77#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 2 2006.225.08:17:19.77#ibcon#iclass 18 iclrec 2 cls_cnt 2 2006.225.08:17:19.77#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:19.77#ibcon#before find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:17:19.89#ibcon#after find_delay mode 2, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:17:19.89#ibcon#before mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:17:19.89#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:17:19.89#ibcon#first serial, iclass 18, count 0 2006.225.08:17:19.89#ibcon#enter sib2, iclass 18, count 0 2006.225.08:17:19.89#ibcon#flushed, iclass 18, count 0 2006.225.08:17:19.89#ibcon#about to write, iclass 18, count 0 2006.225.08:17:19.89#ibcon#wrote, iclass 18, count 0 2006.225.08:17:19.89#ibcon#about to read 3, iclass 18, count 0 2006.225.08:17:19.91#ibcon#read 3, iclass 18, count 0 2006.225.08:17:19.91#ibcon#about to read 4, iclass 18, count 0 2006.225.08:17:19.91#ibcon#read 4, iclass 18, count 0 2006.225.08:17:19.91#ibcon#about to read 5, iclass 18, count 0 2006.225.08:17:19.91#ibcon#read 5, iclass 18, count 0 2006.225.08:17:19.91#ibcon#about to read 6, iclass 18, count 0 2006.225.08:17:19.91#ibcon#read 6, iclass 18, count 0 2006.225.08:17:19.91#ibcon#end of sib2, iclass 18, count 0 2006.225.08:17:19.91#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:17:19.91#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:17:19.91#ibcon#[25=USB\r\n] 2006.225.08:17:19.91#ibcon#*before write, iclass 18, count 0 2006.225.08:17:19.91#ibcon#enter sib2, iclass 18, count 0 2006.225.08:17:19.91#ibcon#flushed, iclass 18, count 0 2006.225.08:17:19.91#ibcon#about to write, iclass 18, count 0 2006.225.08:17:19.91#ibcon#wrote, iclass 18, count 0 2006.225.08:17:19.91#ibcon#about to read 3, iclass 18, count 0 2006.225.08:17:19.94#ibcon#read 3, iclass 18, count 0 2006.225.08:17:19.94#ibcon#about to read 4, iclass 18, count 0 2006.225.08:17:19.94#ibcon#read 4, iclass 18, count 0 2006.225.08:17:19.94#ibcon#about to read 5, iclass 18, count 0 2006.225.08:17:19.94#ibcon#read 5, iclass 18, count 0 2006.225.08:17:19.94#ibcon#about to read 6, iclass 18, count 0 2006.225.08:17:19.94#ibcon#read 6, iclass 18, count 0 2006.225.08:17:19.94#ibcon#end of sib2, iclass 18, count 0 2006.225.08:17:19.94#ibcon#*after write, iclass 18, count 0 2006.225.08:17:19.94#ibcon#*before return 0, iclass 18, count 0 2006.225.08:17:19.94#ibcon#after mode 2 write, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:17:19.94#ibcon#end of loop, iclass 18 iclrec 2 cls_cnt 0 2006.225.08:17:19.94#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:17:19.94#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:17:19.94$vc4f8/valo=7,832.99 2006.225.08:17:19.94#ibcon#iclass 20 nclrec 1 cls_cnt 2 2006.225.08:17:19.94#ibcon#iclass 20 iclrec 1 cls_cnt 2 2006.225.08:17:19.94#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:19.94#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:17:19.94#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:17:19.94#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:17:19.94#ibcon#enter wrdev, iclass 20, count 0 2006.225.08:17:19.94#ibcon#first serial, iclass 20, count 0 2006.225.08:17:19.94#ibcon#enter sib2, iclass 20, count 0 2006.225.08:17:19.94#ibcon#flushed, iclass 20, count 0 2006.225.08:17:19.94#ibcon#about to write, iclass 20, count 0 2006.225.08:17:19.94#ibcon#wrote, iclass 20, count 0 2006.225.08:17:19.94#ibcon#about to read 3, iclass 20, count 0 2006.225.08:17:19.96#ibcon#read 3, iclass 20, count 0 2006.225.08:17:19.96#ibcon#about to read 4, iclass 20, count 0 2006.225.08:17:19.96#ibcon#read 4, iclass 20, count 0 2006.225.08:17:19.96#ibcon#about to read 5, iclass 20, count 0 2006.225.08:17:19.96#ibcon#read 5, iclass 20, count 0 2006.225.08:17:19.96#ibcon#about to read 6, iclass 20, count 0 2006.225.08:17:19.96#ibcon#read 6, iclass 20, count 0 2006.225.08:17:19.96#ibcon#end of sib2, iclass 20, count 0 2006.225.08:17:19.96#ibcon#*mode == 0, iclass 20, count 0 2006.225.08:17:19.96#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.08:17:19.96#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:17:19.96#ibcon#*before write, iclass 20, count 0 2006.225.08:17:19.96#ibcon#enter sib2, iclass 20, count 0 2006.225.08:17:19.96#ibcon#flushed, iclass 20, count 0 2006.225.08:17:19.96#ibcon#about to write, iclass 20, count 0 2006.225.08:17:19.96#ibcon#wrote, iclass 20, count 0 2006.225.08:17:19.96#ibcon#about to read 3, iclass 20, count 0 2006.225.08:17:20.00#ibcon#read 3, iclass 20, count 0 2006.225.08:17:20.00#ibcon#about to read 4, iclass 20, count 0 2006.225.08:17:20.00#ibcon#read 4, iclass 20, count 0 2006.225.08:17:20.00#ibcon#about to read 5, iclass 20, count 0 2006.225.08:17:20.00#ibcon#read 5, iclass 20, count 0 2006.225.08:17:20.00#ibcon#about to read 6, iclass 20, count 0 2006.225.08:17:20.00#ibcon#read 6, iclass 20, count 0 2006.225.08:17:20.00#ibcon#end of sib2, iclass 20, count 0 2006.225.08:17:20.00#ibcon#*after write, iclass 20, count 0 2006.225.08:17:20.00#ibcon#*before return 0, iclass 20, count 0 2006.225.08:17:20.00#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:17:20.00#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 0 2006.225.08:17:20.00#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.08:17:20.00#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.08:17:20.00$vc4f8/va=7,6 2006.225.08:17:20.00#ibcon#iclass 22 nclrec 2 cls_cnt 3 2006.225.08:17:20.00#ibcon#iclass 22 iclrec 1 cls_cnt 3 2006.225.08:17:20.00#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:20.00#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:17:20.06#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:17:20.06#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:17:20.06#ibcon#enter wrdev, iclass 22, count 2 2006.225.08:17:20.06#ibcon#first serial, iclass 22, count 2 2006.225.08:17:20.06#ibcon#enter sib2, iclass 22, count 2 2006.225.08:17:20.06#ibcon#flushed, iclass 22, count 2 2006.225.08:17:20.06#ibcon#about to write, iclass 22, count 2 2006.225.08:17:20.06#ibcon#wrote, iclass 22, count 2 2006.225.08:17:20.06#ibcon#about to read 3, iclass 22, count 2 2006.225.08:17:20.08#ibcon#read 3, iclass 22, count 2 2006.225.08:17:20.08#ibcon#about to read 4, iclass 22, count 2 2006.225.08:17:20.08#ibcon#read 4, iclass 22, count 2 2006.225.08:17:20.08#ibcon#about to read 5, iclass 22, count 2 2006.225.08:17:20.08#ibcon#read 5, iclass 22, count 2 2006.225.08:17:20.08#ibcon#about to read 6, iclass 22, count 2 2006.225.08:17:20.08#ibcon#read 6, iclass 22, count 2 2006.225.08:17:20.08#ibcon#end of sib2, iclass 22, count 2 2006.225.08:17:20.08#ibcon#*mode == 0, iclass 22, count 2 2006.225.08:17:20.08#ibcon#*mode == 0 && serial, iclass 22, count 2 2006.225.08:17:20.08#ibcon#[25=AT07-06\r\n] 2006.225.08:17:20.08#ibcon#*before write, iclass 22, count 2 2006.225.08:17:20.08#ibcon#enter sib2, iclass 22, count 2 2006.225.08:17:20.08#ibcon#flushed, iclass 22, count 2 2006.225.08:17:20.08#ibcon#about to write, iclass 22, count 2 2006.225.08:17:20.08#ibcon#wrote, iclass 22, count 2 2006.225.08:17:20.08#ibcon#about to read 3, iclass 22, count 2 2006.225.08:17:20.11#ibcon#read 3, iclass 22, count 2 2006.225.08:17:20.11#ibcon#about to read 4, iclass 22, count 2 2006.225.08:17:20.11#ibcon#read 4, iclass 22, count 2 2006.225.08:17:20.11#ibcon#about to read 5, iclass 22, count 2 2006.225.08:17:20.11#ibcon#read 5, iclass 22, count 2 2006.225.08:17:20.11#ibcon#about to read 6, iclass 22, count 2 2006.225.08:17:20.11#ibcon#read 6, iclass 22, count 2 2006.225.08:17:20.11#ibcon#end of sib2, iclass 22, count 2 2006.225.08:17:20.11#ibcon#*after write, iclass 22, count 2 2006.225.08:17:20.11#ibcon#*before return 0, iclass 22, count 2 2006.225.08:17:20.11#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:17:20.11#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 2 2006.225.08:17:20.11#ibcon#iclass 22 iclrec 2 cls_cnt 2 2006.225.08:17:20.11#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:20.11#ibcon#before find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:17:20.23#ibcon#after find_delay mode 2, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:17:20.23#ibcon#before mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:17:20.23#ibcon#enter wrdev, iclass 22, count 0 2006.225.08:17:20.23#ibcon#first serial, iclass 22, count 0 2006.225.08:17:20.23#ibcon#enter sib2, iclass 22, count 0 2006.225.08:17:20.23#ibcon#flushed, iclass 22, count 0 2006.225.08:17:20.23#ibcon#about to write, iclass 22, count 0 2006.225.08:17:20.23#ibcon#wrote, iclass 22, count 0 2006.225.08:17:20.23#ibcon#about to read 3, iclass 22, count 0 2006.225.08:17:20.25#ibcon#read 3, iclass 22, count 0 2006.225.08:17:20.25#ibcon#about to read 4, iclass 22, count 0 2006.225.08:17:20.25#ibcon#read 4, iclass 22, count 0 2006.225.08:17:20.25#ibcon#about to read 5, iclass 22, count 0 2006.225.08:17:20.25#ibcon#read 5, iclass 22, count 0 2006.225.08:17:20.25#ibcon#about to read 6, iclass 22, count 0 2006.225.08:17:20.25#ibcon#read 6, iclass 22, count 0 2006.225.08:17:20.25#ibcon#end of sib2, iclass 22, count 0 2006.225.08:17:20.25#ibcon#*mode == 0, iclass 22, count 0 2006.225.08:17:20.25#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.08:17:20.25#ibcon#[25=USB\r\n] 2006.225.08:17:20.25#ibcon#*before write, iclass 22, count 0 2006.225.08:17:20.25#ibcon#enter sib2, iclass 22, count 0 2006.225.08:17:20.25#ibcon#flushed, iclass 22, count 0 2006.225.08:17:20.25#ibcon#about to write, iclass 22, count 0 2006.225.08:17:20.25#ibcon#wrote, iclass 22, count 0 2006.225.08:17:20.25#ibcon#about to read 3, iclass 22, count 0 2006.225.08:17:20.28#ibcon#read 3, iclass 22, count 0 2006.225.08:17:20.28#ibcon#about to read 4, iclass 22, count 0 2006.225.08:17:20.28#ibcon#read 4, iclass 22, count 0 2006.225.08:17:20.28#ibcon#about to read 5, iclass 22, count 0 2006.225.08:17:20.28#ibcon#read 5, iclass 22, count 0 2006.225.08:17:20.28#ibcon#about to read 6, iclass 22, count 0 2006.225.08:17:20.28#ibcon#read 6, iclass 22, count 0 2006.225.08:17:20.28#ibcon#end of sib2, iclass 22, count 0 2006.225.08:17:20.28#ibcon#*after write, iclass 22, count 0 2006.225.08:17:20.28#ibcon#*before return 0, iclass 22, count 0 2006.225.08:17:20.28#ibcon#after mode 2 write, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:17:20.28#ibcon#end of loop, iclass 22 iclrec 2 cls_cnt 0 2006.225.08:17:20.28#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.08:17:20.28#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.08:17:20.28$vc4f8/valo=8,852.99 2006.225.08:17:20.28#ibcon#iclass 24 nclrec 1 cls_cnt 2 2006.225.08:17:20.28#ibcon#iclass 24 iclrec 1 cls_cnt 2 2006.225.08:17:20.28#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:20.28#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:17:20.28#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:17:20.28#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:17:20.28#ibcon#enter wrdev, iclass 24, count 0 2006.225.08:17:20.28#ibcon#first serial, iclass 24, count 0 2006.225.08:17:20.28#ibcon#enter sib2, iclass 24, count 0 2006.225.08:17:20.28#ibcon#flushed, iclass 24, count 0 2006.225.08:17:20.28#ibcon#about to write, iclass 24, count 0 2006.225.08:17:20.28#ibcon#wrote, iclass 24, count 0 2006.225.08:17:20.28#ibcon#about to read 3, iclass 24, count 0 2006.225.08:17:20.30#ibcon#read 3, iclass 24, count 0 2006.225.08:17:20.30#ibcon#about to read 4, iclass 24, count 0 2006.225.08:17:20.30#ibcon#read 4, iclass 24, count 0 2006.225.08:17:20.30#ibcon#about to read 5, iclass 24, count 0 2006.225.08:17:20.30#ibcon#read 5, iclass 24, count 0 2006.225.08:17:20.30#ibcon#about to read 6, iclass 24, count 0 2006.225.08:17:20.30#ibcon#read 6, iclass 24, count 0 2006.225.08:17:20.30#ibcon#end of sib2, iclass 24, count 0 2006.225.08:17:20.30#ibcon#*mode == 0, iclass 24, count 0 2006.225.08:17:20.30#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.08:17:20.30#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:17:20.30#ibcon#*before write, iclass 24, count 0 2006.225.08:17:20.30#ibcon#enter sib2, iclass 24, count 0 2006.225.08:17:20.30#ibcon#flushed, iclass 24, count 0 2006.225.08:17:20.30#ibcon#about to write, iclass 24, count 0 2006.225.08:17:20.30#ibcon#wrote, iclass 24, count 0 2006.225.08:17:20.30#ibcon#about to read 3, iclass 24, count 0 2006.225.08:17:20.34#ibcon#read 3, iclass 24, count 0 2006.225.08:17:20.34#ibcon#about to read 4, iclass 24, count 0 2006.225.08:17:20.34#ibcon#read 4, iclass 24, count 0 2006.225.08:17:20.34#ibcon#about to read 5, iclass 24, count 0 2006.225.08:17:20.34#ibcon#read 5, iclass 24, count 0 2006.225.08:17:20.34#ibcon#about to read 6, iclass 24, count 0 2006.225.08:17:20.34#ibcon#read 6, iclass 24, count 0 2006.225.08:17:20.34#ibcon#end of sib2, iclass 24, count 0 2006.225.08:17:20.34#ibcon#*after write, iclass 24, count 0 2006.225.08:17:20.34#ibcon#*before return 0, iclass 24, count 0 2006.225.08:17:20.34#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:17:20.34#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 0 2006.225.08:17:20.34#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.08:17:20.34#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.08:17:20.34$vc4f8/va=8,7 2006.225.08:17:20.34#ibcon#iclass 26 nclrec 2 cls_cnt 3 2006.225.08:17:20.34#ibcon#iclass 26 iclrec 1 cls_cnt 3 2006.225.08:17:20.34#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:20.34#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.08:17:20.40#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 2 2006.225.08:17:20.40#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.08:17:20.40#ibcon#enter wrdev, iclass 26, count 2 2006.225.08:17:20.40#ibcon#first serial, iclass 26, count 2 2006.225.08:17:20.40#ibcon#enter sib2, iclass 26, count 2 2006.225.08:17:20.40#ibcon#flushed, iclass 26, count 2 2006.225.08:17:20.40#ibcon#about to write, iclass 26, count 2 2006.225.08:17:20.40#ibcon#wrote, iclass 26, count 2 2006.225.08:17:20.40#ibcon#about to read 3, iclass 26, count 2 2006.225.08:17:20.42#ibcon#read 3, iclass 26, count 2 2006.225.08:17:20.42#ibcon#about to read 4, iclass 26, count 2 2006.225.08:17:20.42#ibcon#read 4, iclass 26, count 2 2006.225.08:17:20.42#ibcon#about to read 5, iclass 26, count 2 2006.225.08:17:20.42#ibcon#read 5, iclass 26, count 2 2006.225.08:17:20.42#ibcon#about to read 6, iclass 26, count 2 2006.225.08:17:20.42#ibcon#read 6, iclass 26, count 2 2006.225.08:17:20.42#ibcon#end of sib2, iclass 26, count 2 2006.225.08:17:20.42#ibcon#*mode == 0, iclass 26, count 2 2006.225.08:17:20.42#ibcon#*mode == 0 && serial, iclass 26, count 2 2006.225.08:17:20.42#ibcon#[25=AT08-07\r\n] 2006.225.08:17:20.42#ibcon#*before write, iclass 26, count 2 2006.225.08:17:20.42#ibcon#enter sib2, iclass 26, count 2 2006.225.08:17:20.42#ibcon#flushed, iclass 26, count 2 2006.225.08:17:20.42#ibcon#about to write, iclass 26, count 2 2006.225.08:17:20.42#ibcon#wrote, iclass 26, count 2 2006.225.08:17:20.42#ibcon#about to read 3, iclass 26, count 2 2006.225.08:17:20.45#ibcon#read 3, iclass 26, count 2 2006.225.08:17:20.45#ibcon#about to read 4, iclass 26, count 2 2006.225.08:17:20.45#ibcon#read 4, iclass 26, count 2 2006.225.08:17:20.45#ibcon#about to read 5, iclass 26, count 2 2006.225.08:17:20.45#ibcon#read 5, iclass 26, count 2 2006.225.08:17:20.45#ibcon#about to read 6, iclass 26, count 2 2006.225.08:17:20.45#ibcon#read 6, iclass 26, count 2 2006.225.08:17:20.45#ibcon#end of sib2, iclass 26, count 2 2006.225.08:17:20.45#ibcon#*after write, iclass 26, count 2 2006.225.08:17:20.45#ibcon#*before return 0, iclass 26, count 2 2006.225.08:17:20.45#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 2 2006.225.08:17:20.45#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 2 2006.225.08:17:20.45#ibcon#iclass 26 iclrec 2 cls_cnt 2 2006.225.08:17:20.45#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:20.45#ibcon#before find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.08:17:20.57#ibcon#after find_delay mode 2, iclass 26 iclrec 2 cls_cnt 0 2006.225.08:17:20.57#ibcon#before mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.08:17:20.57#ibcon#enter wrdev, iclass 26, count 0 2006.225.08:17:20.57#ibcon#first serial, iclass 26, count 0 2006.225.08:17:20.57#ibcon#enter sib2, iclass 26, count 0 2006.225.08:17:20.57#ibcon#flushed, iclass 26, count 0 2006.225.08:17:20.57#ibcon#about to write, iclass 26, count 0 2006.225.08:17:20.57#ibcon#wrote, iclass 26, count 0 2006.225.08:17:20.57#ibcon#about to read 3, iclass 26, count 0 2006.225.08:17:20.59#ibcon#read 3, iclass 26, count 0 2006.225.08:17:20.59#ibcon#about to read 4, iclass 26, count 0 2006.225.08:17:20.59#ibcon#read 4, iclass 26, count 0 2006.225.08:17:20.59#ibcon#about to read 5, iclass 26, count 0 2006.225.08:17:20.59#ibcon#read 5, iclass 26, count 0 2006.225.08:17:20.59#ibcon#about to read 6, iclass 26, count 0 2006.225.08:17:20.59#ibcon#read 6, iclass 26, count 0 2006.225.08:17:20.59#ibcon#end of sib2, iclass 26, count 0 2006.225.08:17:20.59#ibcon#*mode == 0, iclass 26, count 0 2006.225.08:17:20.59#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.08:17:20.59#ibcon#[25=USB\r\n] 2006.225.08:17:20.59#ibcon#*before write, iclass 26, count 0 2006.225.08:17:20.59#ibcon#enter sib2, iclass 26, count 0 2006.225.08:17:20.59#ibcon#flushed, iclass 26, count 0 2006.225.08:17:20.59#ibcon#about to write, iclass 26, count 0 2006.225.08:17:20.59#ibcon#wrote, iclass 26, count 0 2006.225.08:17:20.59#ibcon#about to read 3, iclass 26, count 0 2006.225.08:17:20.62#ibcon#read 3, iclass 26, count 0 2006.225.08:17:20.62#ibcon#about to read 4, iclass 26, count 0 2006.225.08:17:20.62#ibcon#read 4, iclass 26, count 0 2006.225.08:17:20.62#ibcon#about to read 5, iclass 26, count 0 2006.225.08:17:20.62#ibcon#read 5, iclass 26, count 0 2006.225.08:17:20.62#ibcon#about to read 6, iclass 26, count 0 2006.225.08:17:20.62#ibcon#read 6, iclass 26, count 0 2006.225.08:17:20.62#ibcon#end of sib2, iclass 26, count 0 2006.225.08:17:20.62#ibcon#*after write, iclass 26, count 0 2006.225.08:17:20.62#ibcon#*before return 0, iclass 26, count 0 2006.225.08:17:20.62#ibcon#after mode 2 write, iclass 26 iclrec 2 cls_cnt 0 2006.225.08:17:20.62#ibcon#end of loop, iclass 26 iclrec 2 cls_cnt 0 2006.225.08:17:20.62#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.08:17:20.62#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.08:17:20.62$vc4f8/vblo=1,632.99 2006.225.08:17:20.62#ibcon#iclass 28 nclrec 1 cls_cnt 2 2006.225.08:17:20.62#ibcon#iclass 28 iclrec 1 cls_cnt 2 2006.225.08:17:20.62#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:20.62#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:17:20.62#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:17:20.62#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:17:20.62#ibcon#enter wrdev, iclass 28, count 0 2006.225.08:17:20.62#ibcon#first serial, iclass 28, count 0 2006.225.08:17:20.62#ibcon#enter sib2, iclass 28, count 0 2006.225.08:17:20.62#ibcon#flushed, iclass 28, count 0 2006.225.08:17:20.62#ibcon#about to write, iclass 28, count 0 2006.225.08:17:20.62#ibcon#wrote, iclass 28, count 0 2006.225.08:17:20.62#ibcon#about to read 3, iclass 28, count 0 2006.225.08:17:20.65#ibcon#read 3, iclass 28, count 0 2006.225.08:17:20.65#ibcon#about to read 4, iclass 28, count 0 2006.225.08:17:20.65#ibcon#read 4, iclass 28, count 0 2006.225.08:17:20.65#ibcon#about to read 5, iclass 28, count 0 2006.225.08:17:20.65#ibcon#read 5, iclass 28, count 0 2006.225.08:17:20.65#ibcon#about to read 6, iclass 28, count 0 2006.225.08:17:20.65#ibcon#read 6, iclass 28, count 0 2006.225.08:17:20.65#ibcon#end of sib2, iclass 28, count 0 2006.225.08:17:20.65#ibcon#*mode == 0, iclass 28, count 0 2006.225.08:17:20.65#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.08:17:20.65#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:17:20.65#ibcon#*before write, iclass 28, count 0 2006.225.08:17:20.65#ibcon#enter sib2, iclass 28, count 0 2006.225.08:17:20.65#ibcon#flushed, iclass 28, count 0 2006.225.08:17:20.65#ibcon#about to write, iclass 28, count 0 2006.225.08:17:20.65#ibcon#wrote, iclass 28, count 0 2006.225.08:17:20.65#ibcon#about to read 3, iclass 28, count 0 2006.225.08:17:20.69#ibcon#read 3, iclass 28, count 0 2006.225.08:17:20.69#ibcon#about to read 4, iclass 28, count 0 2006.225.08:17:20.69#ibcon#read 4, iclass 28, count 0 2006.225.08:17:20.69#ibcon#about to read 5, iclass 28, count 0 2006.225.08:17:20.69#ibcon#read 5, iclass 28, count 0 2006.225.08:17:20.69#ibcon#about to read 6, iclass 28, count 0 2006.225.08:17:20.69#ibcon#read 6, iclass 28, count 0 2006.225.08:17:20.69#ibcon#end of sib2, iclass 28, count 0 2006.225.08:17:20.69#ibcon#*after write, iclass 28, count 0 2006.225.08:17:20.69#ibcon#*before return 0, iclass 28, count 0 2006.225.08:17:20.69#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:17:20.69#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 0 2006.225.08:17:20.69#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.08:17:20.69#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.08:17:20.69$vc4f8/vb=1,4 2006.225.08:17:20.69#ibcon#iclass 30 nclrec 2 cls_cnt 3 2006.225.08:17:20.69#ibcon#iclass 30 iclrec 1 cls_cnt 3 2006.225.08:17:20.69#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:20.69#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:17:20.69#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:17:20.69#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:17:20.69#ibcon#enter wrdev, iclass 30, count 2 2006.225.08:17:20.69#ibcon#first serial, iclass 30, count 2 2006.225.08:17:20.69#ibcon#enter sib2, iclass 30, count 2 2006.225.08:17:20.69#ibcon#flushed, iclass 30, count 2 2006.225.08:17:20.69#ibcon#about to write, iclass 30, count 2 2006.225.08:17:20.69#ibcon#wrote, iclass 30, count 2 2006.225.08:17:20.69#ibcon#about to read 3, iclass 30, count 2 2006.225.08:17:20.71#ibcon#read 3, iclass 30, count 2 2006.225.08:17:20.71#ibcon#about to read 4, iclass 30, count 2 2006.225.08:17:20.71#ibcon#read 4, iclass 30, count 2 2006.225.08:17:20.71#ibcon#about to read 5, iclass 30, count 2 2006.225.08:17:20.71#ibcon#read 5, iclass 30, count 2 2006.225.08:17:20.71#ibcon#about to read 6, iclass 30, count 2 2006.225.08:17:20.71#ibcon#read 6, iclass 30, count 2 2006.225.08:17:20.71#ibcon#end of sib2, iclass 30, count 2 2006.225.08:17:20.71#ibcon#*mode == 0, iclass 30, count 2 2006.225.08:17:20.71#ibcon#*mode == 0 && serial, iclass 30, count 2 2006.225.08:17:20.71#ibcon#[27=AT01-04\r\n] 2006.225.08:17:20.71#ibcon#*before write, iclass 30, count 2 2006.225.08:17:20.71#ibcon#enter sib2, iclass 30, count 2 2006.225.08:17:20.71#ibcon#flushed, iclass 30, count 2 2006.225.08:17:20.71#ibcon#about to write, iclass 30, count 2 2006.225.08:17:20.71#ibcon#wrote, iclass 30, count 2 2006.225.08:17:20.71#ibcon#about to read 3, iclass 30, count 2 2006.225.08:17:20.74#ibcon#read 3, iclass 30, count 2 2006.225.08:17:20.74#ibcon#about to read 4, iclass 30, count 2 2006.225.08:17:20.74#ibcon#read 4, iclass 30, count 2 2006.225.08:17:20.74#ibcon#about to read 5, iclass 30, count 2 2006.225.08:17:20.74#ibcon#read 5, iclass 30, count 2 2006.225.08:17:20.74#ibcon#about to read 6, iclass 30, count 2 2006.225.08:17:20.74#ibcon#read 6, iclass 30, count 2 2006.225.08:17:20.74#ibcon#end of sib2, iclass 30, count 2 2006.225.08:17:20.74#ibcon#*after write, iclass 30, count 2 2006.225.08:17:20.74#ibcon#*before return 0, iclass 30, count 2 2006.225.08:17:20.74#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:17:20.74#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 2 2006.225.08:17:20.74#ibcon#iclass 30 iclrec 2 cls_cnt 2 2006.225.08:17:20.74#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:20.74#ibcon#before find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:17:20.86#ibcon#after find_delay mode 2, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:17:20.86#ibcon#before mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:17:20.86#ibcon#enter wrdev, iclass 30, count 0 2006.225.08:17:20.86#ibcon#first serial, iclass 30, count 0 2006.225.08:17:20.86#ibcon#enter sib2, iclass 30, count 0 2006.225.08:17:20.86#ibcon#flushed, iclass 30, count 0 2006.225.08:17:20.86#ibcon#about to write, iclass 30, count 0 2006.225.08:17:20.86#ibcon#wrote, iclass 30, count 0 2006.225.08:17:20.86#ibcon#about to read 3, iclass 30, count 0 2006.225.08:17:20.88#ibcon#read 3, iclass 30, count 0 2006.225.08:17:20.88#ibcon#about to read 4, iclass 30, count 0 2006.225.08:17:20.88#ibcon#read 4, iclass 30, count 0 2006.225.08:17:20.88#ibcon#about to read 5, iclass 30, count 0 2006.225.08:17:20.88#ibcon#read 5, iclass 30, count 0 2006.225.08:17:20.88#ibcon#about to read 6, iclass 30, count 0 2006.225.08:17:20.88#ibcon#read 6, iclass 30, count 0 2006.225.08:17:20.88#ibcon#end of sib2, iclass 30, count 0 2006.225.08:17:20.88#ibcon#*mode == 0, iclass 30, count 0 2006.225.08:17:20.88#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.08:17:20.88#ibcon#[27=USB\r\n] 2006.225.08:17:20.88#ibcon#*before write, iclass 30, count 0 2006.225.08:17:20.88#ibcon#enter sib2, iclass 30, count 0 2006.225.08:17:20.88#ibcon#flushed, iclass 30, count 0 2006.225.08:17:20.88#ibcon#about to write, iclass 30, count 0 2006.225.08:17:20.88#ibcon#wrote, iclass 30, count 0 2006.225.08:17:20.88#ibcon#about to read 3, iclass 30, count 0 2006.225.08:17:20.91#ibcon#read 3, iclass 30, count 0 2006.225.08:17:20.91#ibcon#about to read 4, iclass 30, count 0 2006.225.08:17:20.91#ibcon#read 4, iclass 30, count 0 2006.225.08:17:20.91#ibcon#about to read 5, iclass 30, count 0 2006.225.08:17:20.91#ibcon#read 5, iclass 30, count 0 2006.225.08:17:20.91#ibcon#about to read 6, iclass 30, count 0 2006.225.08:17:20.91#ibcon#read 6, iclass 30, count 0 2006.225.08:17:20.91#ibcon#end of sib2, iclass 30, count 0 2006.225.08:17:20.91#ibcon#*after write, iclass 30, count 0 2006.225.08:17:20.91#ibcon#*before return 0, iclass 30, count 0 2006.225.08:17:20.91#ibcon#after mode 2 write, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:17:20.91#ibcon#end of loop, iclass 30 iclrec 2 cls_cnt 0 2006.225.08:17:20.91#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.08:17:20.91#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.08:17:20.91$vc4f8/vblo=2,640.99 2006.225.08:17:20.91#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.08:17:20.91#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.08:17:20.91#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:20.91#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:17:20.91#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:17:20.91#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:17:20.91#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:17:20.91#ibcon#first serial, iclass 32, count 0 2006.225.08:17:20.91#ibcon#enter sib2, iclass 32, count 0 2006.225.08:17:20.91#ibcon#flushed, iclass 32, count 0 2006.225.08:17:20.91#ibcon#about to write, iclass 32, count 0 2006.225.08:17:20.91#ibcon#wrote, iclass 32, count 0 2006.225.08:17:20.91#ibcon#about to read 3, iclass 32, count 0 2006.225.08:17:20.93#ibcon#read 3, iclass 32, count 0 2006.225.08:17:20.93#ibcon#about to read 4, iclass 32, count 0 2006.225.08:17:20.93#ibcon#read 4, iclass 32, count 0 2006.225.08:17:20.93#ibcon#about to read 5, iclass 32, count 0 2006.225.08:17:20.93#ibcon#read 5, iclass 32, count 0 2006.225.08:17:20.93#ibcon#about to read 6, iclass 32, count 0 2006.225.08:17:20.93#ibcon#read 6, iclass 32, count 0 2006.225.08:17:20.93#ibcon#end of sib2, iclass 32, count 0 2006.225.08:17:20.93#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:17:20.93#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:17:20.93#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:17:20.93#ibcon#*before write, iclass 32, count 0 2006.225.08:17:20.93#ibcon#enter sib2, iclass 32, count 0 2006.225.08:17:20.93#ibcon#flushed, iclass 32, count 0 2006.225.08:17:20.93#ibcon#about to write, iclass 32, count 0 2006.225.08:17:20.93#ibcon#wrote, iclass 32, count 0 2006.225.08:17:20.93#ibcon#about to read 3, iclass 32, count 0 2006.225.08:17:20.97#ibcon#read 3, iclass 32, count 0 2006.225.08:17:20.97#ibcon#about to read 4, iclass 32, count 0 2006.225.08:17:20.97#ibcon#read 4, iclass 32, count 0 2006.225.08:17:20.97#ibcon#about to read 5, iclass 32, count 0 2006.225.08:17:20.97#ibcon#read 5, iclass 32, count 0 2006.225.08:17:20.97#ibcon#about to read 6, iclass 32, count 0 2006.225.08:17:20.97#ibcon#read 6, iclass 32, count 0 2006.225.08:17:20.97#ibcon#end of sib2, iclass 32, count 0 2006.225.08:17:20.97#ibcon#*after write, iclass 32, count 0 2006.225.08:17:20.97#ibcon#*before return 0, iclass 32, count 0 2006.225.08:17:20.97#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:17:20.97#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:17:20.97#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:17:20.97#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:17:20.97$vc4f8/vb=2,4 2006.225.08:17:20.97#ibcon#iclass 34 nclrec 2 cls_cnt 3 2006.225.08:17:20.97#ibcon#iclass 34 iclrec 1 cls_cnt 3 2006.225.08:17:20.97#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:20.97#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:17:21.03#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:17:21.03#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:17:21.03#ibcon#enter wrdev, iclass 34, count 2 2006.225.08:17:21.03#ibcon#first serial, iclass 34, count 2 2006.225.08:17:21.03#ibcon#enter sib2, iclass 34, count 2 2006.225.08:17:21.03#ibcon#flushed, iclass 34, count 2 2006.225.08:17:21.03#ibcon#about to write, iclass 34, count 2 2006.225.08:17:21.03#ibcon#wrote, iclass 34, count 2 2006.225.08:17:21.03#ibcon#about to read 3, iclass 34, count 2 2006.225.08:17:21.05#ibcon#read 3, iclass 34, count 2 2006.225.08:17:21.05#ibcon#about to read 4, iclass 34, count 2 2006.225.08:17:21.05#ibcon#read 4, iclass 34, count 2 2006.225.08:17:21.05#ibcon#about to read 5, iclass 34, count 2 2006.225.08:17:21.05#ibcon#read 5, iclass 34, count 2 2006.225.08:17:21.05#ibcon#about to read 6, iclass 34, count 2 2006.225.08:17:21.05#ibcon#read 6, iclass 34, count 2 2006.225.08:17:21.05#ibcon#end of sib2, iclass 34, count 2 2006.225.08:17:21.05#ibcon#*mode == 0, iclass 34, count 2 2006.225.08:17:21.05#ibcon#*mode == 0 && serial, iclass 34, count 2 2006.225.08:17:21.05#ibcon#[27=AT02-04\r\n] 2006.225.08:17:21.05#ibcon#*before write, iclass 34, count 2 2006.225.08:17:21.05#ibcon#enter sib2, iclass 34, count 2 2006.225.08:17:21.05#ibcon#flushed, iclass 34, count 2 2006.225.08:17:21.05#ibcon#about to write, iclass 34, count 2 2006.225.08:17:21.05#ibcon#wrote, iclass 34, count 2 2006.225.08:17:21.05#ibcon#about to read 3, iclass 34, count 2 2006.225.08:17:21.08#ibcon#read 3, iclass 34, count 2 2006.225.08:17:21.08#ibcon#about to read 4, iclass 34, count 2 2006.225.08:17:21.08#ibcon#read 4, iclass 34, count 2 2006.225.08:17:21.08#ibcon#about to read 5, iclass 34, count 2 2006.225.08:17:21.08#ibcon#read 5, iclass 34, count 2 2006.225.08:17:21.08#ibcon#about to read 6, iclass 34, count 2 2006.225.08:17:21.08#ibcon#read 6, iclass 34, count 2 2006.225.08:17:21.08#ibcon#end of sib2, iclass 34, count 2 2006.225.08:17:21.08#ibcon#*after write, iclass 34, count 2 2006.225.08:17:21.08#ibcon#*before return 0, iclass 34, count 2 2006.225.08:17:21.08#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:17:21.08#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 2 2006.225.08:17:21.08#ibcon#iclass 34 iclrec 2 cls_cnt 2 2006.225.08:17:21.08#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:21.08#ibcon#before find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:17:21.20#ibcon#after find_delay mode 2, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:17:21.20#ibcon#before mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:17:21.20#ibcon#enter wrdev, iclass 34, count 0 2006.225.08:17:21.20#ibcon#first serial, iclass 34, count 0 2006.225.08:17:21.20#ibcon#enter sib2, iclass 34, count 0 2006.225.08:17:21.20#ibcon#flushed, iclass 34, count 0 2006.225.08:17:21.20#ibcon#about to write, iclass 34, count 0 2006.225.08:17:21.20#ibcon#wrote, iclass 34, count 0 2006.225.08:17:21.20#ibcon#about to read 3, iclass 34, count 0 2006.225.08:17:21.22#ibcon#read 3, iclass 34, count 0 2006.225.08:17:21.22#ibcon#about to read 4, iclass 34, count 0 2006.225.08:17:21.22#ibcon#read 4, iclass 34, count 0 2006.225.08:17:21.22#ibcon#about to read 5, iclass 34, count 0 2006.225.08:17:21.22#ibcon#read 5, iclass 34, count 0 2006.225.08:17:21.22#ibcon#about to read 6, iclass 34, count 0 2006.225.08:17:21.22#ibcon#read 6, iclass 34, count 0 2006.225.08:17:21.22#ibcon#end of sib2, iclass 34, count 0 2006.225.08:17:21.22#ibcon#*mode == 0, iclass 34, count 0 2006.225.08:17:21.22#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.08:17:21.22#ibcon#[27=USB\r\n] 2006.225.08:17:21.22#ibcon#*before write, iclass 34, count 0 2006.225.08:17:21.22#ibcon#enter sib2, iclass 34, count 0 2006.225.08:17:21.22#ibcon#flushed, iclass 34, count 0 2006.225.08:17:21.22#ibcon#about to write, iclass 34, count 0 2006.225.08:17:21.22#ibcon#wrote, iclass 34, count 0 2006.225.08:17:21.22#ibcon#about to read 3, iclass 34, count 0 2006.225.08:17:21.25#ibcon#read 3, iclass 34, count 0 2006.225.08:17:21.25#ibcon#about to read 4, iclass 34, count 0 2006.225.08:17:21.25#ibcon#read 4, iclass 34, count 0 2006.225.08:17:21.25#ibcon#about to read 5, iclass 34, count 0 2006.225.08:17:21.25#ibcon#read 5, iclass 34, count 0 2006.225.08:17:21.25#ibcon#about to read 6, iclass 34, count 0 2006.225.08:17:21.25#ibcon#read 6, iclass 34, count 0 2006.225.08:17:21.25#ibcon#end of sib2, iclass 34, count 0 2006.225.08:17:21.25#ibcon#*after write, iclass 34, count 0 2006.225.08:17:21.25#ibcon#*before return 0, iclass 34, count 0 2006.225.08:17:21.25#ibcon#after mode 2 write, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:17:21.25#ibcon#end of loop, iclass 34 iclrec 2 cls_cnt 0 2006.225.08:17:21.25#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.08:17:21.25#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.08:17:21.25$vc4f8/vblo=3,656.99 2006.225.08:17:21.25#ibcon#iclass 36 nclrec 1 cls_cnt 2 2006.225.08:17:21.25#ibcon#iclass 36 iclrec 1 cls_cnt 2 2006.225.08:17:21.25#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:21.25#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:17:21.25#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:17:21.25#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:17:21.25#ibcon#enter wrdev, iclass 36, count 0 2006.225.08:17:21.25#ibcon#first serial, iclass 36, count 0 2006.225.08:17:21.25#ibcon#enter sib2, iclass 36, count 0 2006.225.08:17:21.25#ibcon#flushed, iclass 36, count 0 2006.225.08:17:21.25#ibcon#about to write, iclass 36, count 0 2006.225.08:17:21.25#ibcon#wrote, iclass 36, count 0 2006.225.08:17:21.25#ibcon#about to read 3, iclass 36, count 0 2006.225.08:17:21.27#ibcon#read 3, iclass 36, count 0 2006.225.08:17:21.27#ibcon#about to read 4, iclass 36, count 0 2006.225.08:17:21.27#ibcon#read 4, iclass 36, count 0 2006.225.08:17:21.27#ibcon#about to read 5, iclass 36, count 0 2006.225.08:17:21.27#ibcon#read 5, iclass 36, count 0 2006.225.08:17:21.27#ibcon#about to read 6, iclass 36, count 0 2006.225.08:17:21.27#ibcon#read 6, iclass 36, count 0 2006.225.08:17:21.27#ibcon#end of sib2, iclass 36, count 0 2006.225.08:17:21.27#ibcon#*mode == 0, iclass 36, count 0 2006.225.08:17:21.27#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.08:17:21.27#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:17:21.27#ibcon#*before write, iclass 36, count 0 2006.225.08:17:21.27#ibcon#enter sib2, iclass 36, count 0 2006.225.08:17:21.27#ibcon#flushed, iclass 36, count 0 2006.225.08:17:21.27#ibcon#about to write, iclass 36, count 0 2006.225.08:17:21.27#ibcon#wrote, iclass 36, count 0 2006.225.08:17:21.27#ibcon#about to read 3, iclass 36, count 0 2006.225.08:17:21.32#ibcon#read 3, iclass 36, count 0 2006.225.08:17:21.32#ibcon#about to read 4, iclass 36, count 0 2006.225.08:17:21.32#ibcon#read 4, iclass 36, count 0 2006.225.08:17:21.32#ibcon#about to read 5, iclass 36, count 0 2006.225.08:17:21.32#ibcon#read 5, iclass 36, count 0 2006.225.08:17:21.32#ibcon#about to read 6, iclass 36, count 0 2006.225.08:17:21.32#ibcon#read 6, iclass 36, count 0 2006.225.08:17:21.32#ibcon#end of sib2, iclass 36, count 0 2006.225.08:17:21.32#ibcon#*after write, iclass 36, count 0 2006.225.08:17:21.32#ibcon#*before return 0, iclass 36, count 0 2006.225.08:17:21.32#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:17:21.32#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 0 2006.225.08:17:21.32#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.08:17:21.32#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.08:17:21.32$vc4f8/vb=3,4 2006.225.08:17:21.32#ibcon#iclass 38 nclrec 2 cls_cnt 3 2006.225.08:17:21.32#ibcon#iclass 38 iclrec 1 cls_cnt 3 2006.225.08:17:21.32#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:21.32#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:17:21.36#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:17:21.36#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:17:21.36#ibcon#enter wrdev, iclass 38, count 2 2006.225.08:17:21.36#ibcon#first serial, iclass 38, count 2 2006.225.08:17:21.36#ibcon#enter sib2, iclass 38, count 2 2006.225.08:17:21.36#ibcon#flushed, iclass 38, count 2 2006.225.08:17:21.36#ibcon#about to write, iclass 38, count 2 2006.225.08:17:21.36#ibcon#wrote, iclass 38, count 2 2006.225.08:17:21.36#ibcon#about to read 3, iclass 38, count 2 2006.225.08:17:21.38#ibcon#read 3, iclass 38, count 2 2006.225.08:17:21.38#ibcon#about to read 4, iclass 38, count 2 2006.225.08:17:21.38#ibcon#read 4, iclass 38, count 2 2006.225.08:17:21.38#ibcon#about to read 5, iclass 38, count 2 2006.225.08:17:21.38#ibcon#read 5, iclass 38, count 2 2006.225.08:17:21.38#ibcon#about to read 6, iclass 38, count 2 2006.225.08:17:21.38#ibcon#read 6, iclass 38, count 2 2006.225.08:17:21.38#ibcon#end of sib2, iclass 38, count 2 2006.225.08:17:21.38#ibcon#*mode == 0, iclass 38, count 2 2006.225.08:17:21.38#ibcon#*mode == 0 && serial, iclass 38, count 2 2006.225.08:17:21.38#ibcon#[27=AT03-04\r\n] 2006.225.08:17:21.38#ibcon#*before write, iclass 38, count 2 2006.225.08:17:21.38#ibcon#enter sib2, iclass 38, count 2 2006.225.08:17:21.38#ibcon#flushed, iclass 38, count 2 2006.225.08:17:21.38#ibcon#about to write, iclass 38, count 2 2006.225.08:17:21.38#ibcon#wrote, iclass 38, count 2 2006.225.08:17:21.38#ibcon#about to read 3, iclass 38, count 2 2006.225.08:17:21.41#ibcon#read 3, iclass 38, count 2 2006.225.08:17:21.41#ibcon#about to read 4, iclass 38, count 2 2006.225.08:17:21.41#ibcon#read 4, iclass 38, count 2 2006.225.08:17:21.41#ibcon#about to read 5, iclass 38, count 2 2006.225.08:17:21.41#ibcon#read 5, iclass 38, count 2 2006.225.08:17:21.41#ibcon#about to read 6, iclass 38, count 2 2006.225.08:17:21.41#ibcon#read 6, iclass 38, count 2 2006.225.08:17:21.41#ibcon#end of sib2, iclass 38, count 2 2006.225.08:17:21.41#ibcon#*after write, iclass 38, count 2 2006.225.08:17:21.41#ibcon#*before return 0, iclass 38, count 2 2006.225.08:17:21.41#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:17:21.41#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 2 2006.225.08:17:21.41#ibcon#iclass 38 iclrec 2 cls_cnt 2 2006.225.08:17:21.41#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:21.41#ibcon#before find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:17:21.53#ibcon#after find_delay mode 2, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:17:21.53#ibcon#before mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:17:21.53#ibcon#enter wrdev, iclass 38, count 0 2006.225.08:17:21.53#ibcon#first serial, iclass 38, count 0 2006.225.08:17:21.53#ibcon#enter sib2, iclass 38, count 0 2006.225.08:17:21.53#ibcon#flushed, iclass 38, count 0 2006.225.08:17:21.53#ibcon#about to write, iclass 38, count 0 2006.225.08:17:21.53#ibcon#wrote, iclass 38, count 0 2006.225.08:17:21.53#ibcon#about to read 3, iclass 38, count 0 2006.225.08:17:21.55#ibcon#read 3, iclass 38, count 0 2006.225.08:17:21.55#ibcon#about to read 4, iclass 38, count 0 2006.225.08:17:21.55#ibcon#read 4, iclass 38, count 0 2006.225.08:17:21.55#ibcon#about to read 5, iclass 38, count 0 2006.225.08:17:21.55#ibcon#read 5, iclass 38, count 0 2006.225.08:17:21.55#ibcon#about to read 6, iclass 38, count 0 2006.225.08:17:21.55#ibcon#read 6, iclass 38, count 0 2006.225.08:17:21.55#ibcon#end of sib2, iclass 38, count 0 2006.225.08:17:21.55#ibcon#*mode == 0, iclass 38, count 0 2006.225.08:17:21.55#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.08:17:21.55#ibcon#[27=USB\r\n] 2006.225.08:17:21.55#ibcon#*before write, iclass 38, count 0 2006.225.08:17:21.55#ibcon#enter sib2, iclass 38, count 0 2006.225.08:17:21.55#ibcon#flushed, iclass 38, count 0 2006.225.08:17:21.55#ibcon#about to write, iclass 38, count 0 2006.225.08:17:21.55#ibcon#wrote, iclass 38, count 0 2006.225.08:17:21.55#ibcon#about to read 3, iclass 38, count 0 2006.225.08:17:21.58#ibcon#read 3, iclass 38, count 0 2006.225.08:17:21.58#ibcon#about to read 4, iclass 38, count 0 2006.225.08:17:21.58#ibcon#read 4, iclass 38, count 0 2006.225.08:17:21.58#ibcon#about to read 5, iclass 38, count 0 2006.225.08:17:21.58#ibcon#read 5, iclass 38, count 0 2006.225.08:17:21.58#ibcon#about to read 6, iclass 38, count 0 2006.225.08:17:21.58#ibcon#read 6, iclass 38, count 0 2006.225.08:17:21.58#ibcon#end of sib2, iclass 38, count 0 2006.225.08:17:21.58#ibcon#*after write, iclass 38, count 0 2006.225.08:17:21.58#ibcon#*before return 0, iclass 38, count 0 2006.225.08:17:21.58#ibcon#after mode 2 write, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:17:21.58#ibcon#end of loop, iclass 38 iclrec 2 cls_cnt 0 2006.225.08:17:21.58#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.08:17:21.58#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.08:17:21.58$vc4f8/vblo=4,712.99 2006.225.08:17:21.58#ibcon#iclass 40 nclrec 1 cls_cnt 2 2006.225.08:17:21.58#ibcon#iclass 40 iclrec 1 cls_cnt 2 2006.225.08:17:21.58#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:21.58#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:17:21.58#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:17:21.58#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:17:21.58#ibcon#enter wrdev, iclass 40, count 0 2006.225.08:17:21.58#ibcon#first serial, iclass 40, count 0 2006.225.08:17:21.58#ibcon#enter sib2, iclass 40, count 0 2006.225.08:17:21.58#ibcon#flushed, iclass 40, count 0 2006.225.08:17:21.58#ibcon#about to write, iclass 40, count 0 2006.225.08:17:21.58#ibcon#wrote, iclass 40, count 0 2006.225.08:17:21.58#ibcon#about to read 3, iclass 40, count 0 2006.225.08:17:21.60#ibcon#read 3, iclass 40, count 0 2006.225.08:17:21.60#ibcon#about to read 4, iclass 40, count 0 2006.225.08:17:21.60#ibcon#read 4, iclass 40, count 0 2006.225.08:17:21.60#ibcon#about to read 5, iclass 40, count 0 2006.225.08:17:21.60#ibcon#read 5, iclass 40, count 0 2006.225.08:17:21.60#ibcon#about to read 6, iclass 40, count 0 2006.225.08:17:21.60#ibcon#read 6, iclass 40, count 0 2006.225.08:17:21.60#ibcon#end of sib2, iclass 40, count 0 2006.225.08:17:21.60#ibcon#*mode == 0, iclass 40, count 0 2006.225.08:17:21.60#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.08:17:21.60#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:17:21.60#ibcon#*before write, iclass 40, count 0 2006.225.08:17:21.60#ibcon#enter sib2, iclass 40, count 0 2006.225.08:17:21.60#ibcon#flushed, iclass 40, count 0 2006.225.08:17:21.60#ibcon#about to write, iclass 40, count 0 2006.225.08:17:21.60#ibcon#wrote, iclass 40, count 0 2006.225.08:17:21.60#ibcon#about to read 3, iclass 40, count 0 2006.225.08:17:21.64#ibcon#read 3, iclass 40, count 0 2006.225.08:17:21.64#ibcon#about to read 4, iclass 40, count 0 2006.225.08:17:21.64#ibcon#read 4, iclass 40, count 0 2006.225.08:17:21.64#ibcon#about to read 5, iclass 40, count 0 2006.225.08:17:21.64#ibcon#read 5, iclass 40, count 0 2006.225.08:17:21.64#ibcon#about to read 6, iclass 40, count 0 2006.225.08:17:21.64#ibcon#read 6, iclass 40, count 0 2006.225.08:17:21.64#ibcon#end of sib2, iclass 40, count 0 2006.225.08:17:21.64#ibcon#*after write, iclass 40, count 0 2006.225.08:17:21.64#ibcon#*before return 0, iclass 40, count 0 2006.225.08:17:21.64#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:17:21.64#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 0 2006.225.08:17:21.64#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.08:17:21.64#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.08:17:21.64$vc4f8/vb=4,4 2006.225.08:17:21.64#ibcon#iclass 4 nclrec 2 cls_cnt 3 2006.225.08:17:21.64#ibcon#iclass 4 iclrec 1 cls_cnt 3 2006.225.08:17:21.64#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:21.64#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:17:21.70#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:17:21.70#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:17:21.70#ibcon#enter wrdev, iclass 4, count 2 2006.225.08:17:21.70#ibcon#first serial, iclass 4, count 2 2006.225.08:17:21.70#ibcon#enter sib2, iclass 4, count 2 2006.225.08:17:21.70#ibcon#flushed, iclass 4, count 2 2006.225.08:17:21.70#ibcon#about to write, iclass 4, count 2 2006.225.08:17:21.70#ibcon#wrote, iclass 4, count 2 2006.225.08:17:21.70#ibcon#about to read 3, iclass 4, count 2 2006.225.08:17:21.72#ibcon#read 3, iclass 4, count 2 2006.225.08:17:21.72#ibcon#about to read 4, iclass 4, count 2 2006.225.08:17:21.72#ibcon#read 4, iclass 4, count 2 2006.225.08:17:21.72#ibcon#about to read 5, iclass 4, count 2 2006.225.08:17:21.72#ibcon#read 5, iclass 4, count 2 2006.225.08:17:21.72#ibcon#about to read 6, iclass 4, count 2 2006.225.08:17:21.72#ibcon#read 6, iclass 4, count 2 2006.225.08:17:21.72#ibcon#end of sib2, iclass 4, count 2 2006.225.08:17:21.72#ibcon#*mode == 0, iclass 4, count 2 2006.225.08:17:21.72#ibcon#*mode == 0 && serial, iclass 4, count 2 2006.225.08:17:21.72#ibcon#[27=AT04-04\r\n] 2006.225.08:17:21.72#ibcon#*before write, iclass 4, count 2 2006.225.08:17:21.72#ibcon#enter sib2, iclass 4, count 2 2006.225.08:17:21.72#ibcon#flushed, iclass 4, count 2 2006.225.08:17:21.72#ibcon#about to write, iclass 4, count 2 2006.225.08:17:21.72#ibcon#wrote, iclass 4, count 2 2006.225.08:17:21.72#ibcon#about to read 3, iclass 4, count 2 2006.225.08:17:21.75#ibcon#read 3, iclass 4, count 2 2006.225.08:17:21.75#ibcon#about to read 4, iclass 4, count 2 2006.225.08:17:21.75#ibcon#read 4, iclass 4, count 2 2006.225.08:17:21.75#ibcon#about to read 5, iclass 4, count 2 2006.225.08:17:21.75#ibcon#read 5, iclass 4, count 2 2006.225.08:17:21.75#ibcon#about to read 6, iclass 4, count 2 2006.225.08:17:21.75#ibcon#read 6, iclass 4, count 2 2006.225.08:17:21.75#ibcon#end of sib2, iclass 4, count 2 2006.225.08:17:21.75#ibcon#*after write, iclass 4, count 2 2006.225.08:17:21.75#ibcon#*before return 0, iclass 4, count 2 2006.225.08:17:21.75#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:17:21.75#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 2 2006.225.08:17:21.75#ibcon#iclass 4 iclrec 2 cls_cnt 2 2006.225.08:17:21.75#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:21.75#ibcon#before find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:17:21.87#ibcon#after find_delay mode 2, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:17:21.87#ibcon#before mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:17:21.87#ibcon#enter wrdev, iclass 4, count 0 2006.225.08:17:21.87#ibcon#first serial, iclass 4, count 0 2006.225.08:17:21.87#ibcon#enter sib2, iclass 4, count 0 2006.225.08:17:21.87#ibcon#flushed, iclass 4, count 0 2006.225.08:17:21.87#ibcon#about to write, iclass 4, count 0 2006.225.08:17:21.87#ibcon#wrote, iclass 4, count 0 2006.225.08:17:21.87#ibcon#about to read 3, iclass 4, count 0 2006.225.08:17:21.89#ibcon#read 3, iclass 4, count 0 2006.225.08:17:21.89#ibcon#about to read 4, iclass 4, count 0 2006.225.08:17:21.89#ibcon#read 4, iclass 4, count 0 2006.225.08:17:21.89#ibcon#about to read 5, iclass 4, count 0 2006.225.08:17:21.89#ibcon#read 5, iclass 4, count 0 2006.225.08:17:21.89#ibcon#about to read 6, iclass 4, count 0 2006.225.08:17:21.89#ibcon#read 6, iclass 4, count 0 2006.225.08:17:21.89#ibcon#end of sib2, iclass 4, count 0 2006.225.08:17:21.89#ibcon#*mode == 0, iclass 4, count 0 2006.225.08:17:21.89#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.08:17:21.89#ibcon#[27=USB\r\n] 2006.225.08:17:21.89#ibcon#*before write, iclass 4, count 0 2006.225.08:17:21.89#ibcon#enter sib2, iclass 4, count 0 2006.225.08:17:21.89#ibcon#flushed, iclass 4, count 0 2006.225.08:17:21.89#ibcon#about to write, iclass 4, count 0 2006.225.08:17:21.89#ibcon#wrote, iclass 4, count 0 2006.225.08:17:21.89#ibcon#about to read 3, iclass 4, count 0 2006.225.08:17:21.92#ibcon#read 3, iclass 4, count 0 2006.225.08:17:21.92#ibcon#about to read 4, iclass 4, count 0 2006.225.08:17:21.92#ibcon#read 4, iclass 4, count 0 2006.225.08:17:21.92#ibcon#about to read 5, iclass 4, count 0 2006.225.08:17:21.92#ibcon#read 5, iclass 4, count 0 2006.225.08:17:21.92#ibcon#about to read 6, iclass 4, count 0 2006.225.08:17:21.92#ibcon#read 6, iclass 4, count 0 2006.225.08:17:21.92#ibcon#end of sib2, iclass 4, count 0 2006.225.08:17:21.92#ibcon#*after write, iclass 4, count 0 2006.225.08:17:21.92#ibcon#*before return 0, iclass 4, count 0 2006.225.08:17:21.92#ibcon#after mode 2 write, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:17:21.92#ibcon#end of loop, iclass 4 iclrec 2 cls_cnt 0 2006.225.08:17:21.92#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.08:17:21.92#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.08:17:21.92$vc4f8/vblo=5,744.99 2006.225.08:17:21.92#ibcon#iclass 6 nclrec 1 cls_cnt 2 2006.225.08:17:21.92#ibcon#iclass 6 iclrec 1 cls_cnt 2 2006.225.08:17:21.92#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:21.92#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:17:21.92#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:17:21.92#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:17:21.92#ibcon#enter wrdev, iclass 6, count 0 2006.225.08:17:21.92#ibcon#first serial, iclass 6, count 0 2006.225.08:17:21.92#ibcon#enter sib2, iclass 6, count 0 2006.225.08:17:21.92#ibcon#flushed, iclass 6, count 0 2006.225.08:17:21.92#ibcon#about to write, iclass 6, count 0 2006.225.08:17:21.92#ibcon#wrote, iclass 6, count 0 2006.225.08:17:21.92#ibcon#about to read 3, iclass 6, count 0 2006.225.08:17:21.94#ibcon#read 3, iclass 6, count 0 2006.225.08:17:21.94#ibcon#about to read 4, iclass 6, count 0 2006.225.08:17:21.94#ibcon#read 4, iclass 6, count 0 2006.225.08:17:21.94#ibcon#about to read 5, iclass 6, count 0 2006.225.08:17:21.94#ibcon#read 5, iclass 6, count 0 2006.225.08:17:21.94#ibcon#about to read 6, iclass 6, count 0 2006.225.08:17:21.94#ibcon#read 6, iclass 6, count 0 2006.225.08:17:21.94#ibcon#end of sib2, iclass 6, count 0 2006.225.08:17:21.94#ibcon#*mode == 0, iclass 6, count 0 2006.225.08:17:21.94#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.08:17:21.94#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:17:21.94#ibcon#*before write, iclass 6, count 0 2006.225.08:17:21.94#ibcon#enter sib2, iclass 6, count 0 2006.225.08:17:21.94#ibcon#flushed, iclass 6, count 0 2006.225.08:17:21.94#ibcon#about to write, iclass 6, count 0 2006.225.08:17:21.94#ibcon#wrote, iclass 6, count 0 2006.225.08:17:21.94#ibcon#about to read 3, iclass 6, count 0 2006.225.08:17:21.98#ibcon#read 3, iclass 6, count 0 2006.225.08:17:21.98#ibcon#about to read 4, iclass 6, count 0 2006.225.08:17:21.98#ibcon#read 4, iclass 6, count 0 2006.225.08:17:21.98#ibcon#about to read 5, iclass 6, count 0 2006.225.08:17:21.98#ibcon#read 5, iclass 6, count 0 2006.225.08:17:21.98#ibcon#about to read 6, iclass 6, count 0 2006.225.08:17:21.98#ibcon#read 6, iclass 6, count 0 2006.225.08:17:21.98#ibcon#end of sib2, iclass 6, count 0 2006.225.08:17:21.98#ibcon#*after write, iclass 6, count 0 2006.225.08:17:21.98#ibcon#*before return 0, iclass 6, count 0 2006.225.08:17:21.98#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:17:21.98#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 0 2006.225.08:17:21.98#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.08:17:21.98#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.08:17:21.98$vc4f8/vb=5,4 2006.225.08:17:21.98#ibcon#iclass 10 nclrec 2 cls_cnt 3 2006.225.08:17:21.98#ibcon#iclass 10 iclrec 1 cls_cnt 3 2006.225.08:17:21.98#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:21.98#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:17:22.04#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:17:22.04#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:17:22.04#ibcon#enter wrdev, iclass 10, count 2 2006.225.08:17:22.04#ibcon#first serial, iclass 10, count 2 2006.225.08:17:22.04#ibcon#enter sib2, iclass 10, count 2 2006.225.08:17:22.04#ibcon#flushed, iclass 10, count 2 2006.225.08:17:22.04#ibcon#about to write, iclass 10, count 2 2006.225.08:17:22.04#ibcon#wrote, iclass 10, count 2 2006.225.08:17:22.04#ibcon#about to read 3, iclass 10, count 2 2006.225.08:17:22.06#ibcon#read 3, iclass 10, count 2 2006.225.08:17:22.06#ibcon#about to read 4, iclass 10, count 2 2006.225.08:17:22.06#ibcon#read 4, iclass 10, count 2 2006.225.08:17:22.06#ibcon#about to read 5, iclass 10, count 2 2006.225.08:17:22.06#ibcon#read 5, iclass 10, count 2 2006.225.08:17:22.06#ibcon#about to read 6, iclass 10, count 2 2006.225.08:17:22.06#ibcon#read 6, iclass 10, count 2 2006.225.08:17:22.06#ibcon#end of sib2, iclass 10, count 2 2006.225.08:17:22.06#ibcon#*mode == 0, iclass 10, count 2 2006.225.08:17:22.06#ibcon#*mode == 0 && serial, iclass 10, count 2 2006.225.08:17:22.06#ibcon#[27=AT05-04\r\n] 2006.225.08:17:22.06#ibcon#*before write, iclass 10, count 2 2006.225.08:17:22.06#ibcon#enter sib2, iclass 10, count 2 2006.225.08:17:22.06#ibcon#flushed, iclass 10, count 2 2006.225.08:17:22.06#ibcon#about to write, iclass 10, count 2 2006.225.08:17:22.06#ibcon#wrote, iclass 10, count 2 2006.225.08:17:22.06#ibcon#about to read 3, iclass 10, count 2 2006.225.08:17:22.09#ibcon#read 3, iclass 10, count 2 2006.225.08:17:22.09#ibcon#about to read 4, iclass 10, count 2 2006.225.08:17:22.09#ibcon#read 4, iclass 10, count 2 2006.225.08:17:22.09#ibcon#about to read 5, iclass 10, count 2 2006.225.08:17:22.09#ibcon#read 5, iclass 10, count 2 2006.225.08:17:22.09#ibcon#about to read 6, iclass 10, count 2 2006.225.08:17:22.09#ibcon#read 6, iclass 10, count 2 2006.225.08:17:22.09#ibcon#end of sib2, iclass 10, count 2 2006.225.08:17:22.09#ibcon#*after write, iclass 10, count 2 2006.225.08:17:22.09#ibcon#*before return 0, iclass 10, count 2 2006.225.08:17:22.09#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:17:22.09#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 2 2006.225.08:17:22.09#ibcon#iclass 10 iclrec 2 cls_cnt 2 2006.225.08:17:22.09#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:22.09#ibcon#before find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:17:22.21#ibcon#after find_delay mode 2, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:17:22.21#ibcon#before mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:17:22.21#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:17:22.21#ibcon#first serial, iclass 10, count 0 2006.225.08:17:22.21#ibcon#enter sib2, iclass 10, count 0 2006.225.08:17:22.21#ibcon#flushed, iclass 10, count 0 2006.225.08:17:22.21#ibcon#about to write, iclass 10, count 0 2006.225.08:17:22.21#ibcon#wrote, iclass 10, count 0 2006.225.08:17:22.21#ibcon#about to read 3, iclass 10, count 0 2006.225.08:17:22.24#ibcon#read 3, iclass 10, count 0 2006.225.08:17:22.24#ibcon#about to read 4, iclass 10, count 0 2006.225.08:17:22.24#ibcon#read 4, iclass 10, count 0 2006.225.08:17:22.24#ibcon#about to read 5, iclass 10, count 0 2006.225.08:17:22.24#ibcon#read 5, iclass 10, count 0 2006.225.08:17:22.24#ibcon#about to read 6, iclass 10, count 0 2006.225.08:17:22.24#ibcon#read 6, iclass 10, count 0 2006.225.08:17:22.24#ibcon#end of sib2, iclass 10, count 0 2006.225.08:17:22.24#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:17:22.25#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:17:22.25#ibcon#[27=USB\r\n] 2006.225.08:17:22.25#ibcon#*before write, iclass 10, count 0 2006.225.08:17:22.25#ibcon#enter sib2, iclass 10, count 0 2006.225.08:17:22.25#ibcon#flushed, iclass 10, count 0 2006.225.08:17:22.25#ibcon#about to write, iclass 10, count 0 2006.225.08:17:22.25#ibcon#wrote, iclass 10, count 0 2006.225.08:17:22.25#ibcon#about to read 3, iclass 10, count 0 2006.225.08:17:22.27#ibcon#read 3, iclass 10, count 0 2006.225.08:17:22.27#ibcon#about to read 4, iclass 10, count 0 2006.225.08:17:22.27#ibcon#read 4, iclass 10, count 0 2006.225.08:17:22.27#ibcon#about to read 5, iclass 10, count 0 2006.225.08:17:22.27#ibcon#read 5, iclass 10, count 0 2006.225.08:17:22.27#ibcon#about to read 6, iclass 10, count 0 2006.225.08:17:22.27#ibcon#read 6, iclass 10, count 0 2006.225.08:17:22.27#ibcon#end of sib2, iclass 10, count 0 2006.225.08:17:22.27#ibcon#*after write, iclass 10, count 0 2006.225.08:17:22.27#ibcon#*before return 0, iclass 10, count 0 2006.225.08:17:22.27#ibcon#after mode 2 write, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:17:22.27#ibcon#end of loop, iclass 10 iclrec 2 cls_cnt 0 2006.225.08:17:22.27#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:17:22.27#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:17:22.27$vc4f8/vblo=6,752.99 2006.225.08:17:22.27#ibcon#iclass 12 nclrec 1 cls_cnt 2 2006.225.08:17:22.27#ibcon#iclass 12 iclrec 1 cls_cnt 2 2006.225.08:17:22.27#ibcon#ireg 17 cls_cnt 0 2006.225.08:17:22.27#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:17:22.27#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:17:22.27#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:17:22.27#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:17:22.27#ibcon#first serial, iclass 12, count 0 2006.225.08:17:22.27#ibcon#enter sib2, iclass 12, count 0 2006.225.08:17:22.27#ibcon#flushed, iclass 12, count 0 2006.225.08:17:22.27#ibcon#about to write, iclass 12, count 0 2006.225.08:17:22.27#ibcon#wrote, iclass 12, count 0 2006.225.08:17:22.27#ibcon#about to read 3, iclass 12, count 0 2006.225.08:17:22.29#ibcon#read 3, iclass 12, count 0 2006.225.08:17:22.29#ibcon#about to read 4, iclass 12, count 0 2006.225.08:17:22.29#ibcon#read 4, iclass 12, count 0 2006.225.08:17:22.29#ibcon#about to read 5, iclass 12, count 0 2006.225.08:17:22.29#ibcon#read 5, iclass 12, count 0 2006.225.08:17:22.29#ibcon#about to read 6, iclass 12, count 0 2006.225.08:17:22.29#ibcon#read 6, iclass 12, count 0 2006.225.08:17:22.29#ibcon#end of sib2, iclass 12, count 0 2006.225.08:17:22.29#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:17:22.29#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:17:22.29#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:17:22.29#ibcon#*before write, iclass 12, count 0 2006.225.08:17:22.29#ibcon#enter sib2, iclass 12, count 0 2006.225.08:17:22.29#ibcon#flushed, iclass 12, count 0 2006.225.08:17:22.29#ibcon#about to write, iclass 12, count 0 2006.225.08:17:22.29#ibcon#wrote, iclass 12, count 0 2006.225.08:17:22.29#ibcon#about to read 3, iclass 12, count 0 2006.225.08:17:22.33#ibcon#read 3, iclass 12, count 0 2006.225.08:17:22.33#ibcon#about to read 4, iclass 12, count 0 2006.225.08:17:22.33#ibcon#read 4, iclass 12, count 0 2006.225.08:17:22.33#ibcon#about to read 5, iclass 12, count 0 2006.225.08:17:22.33#ibcon#read 5, iclass 12, count 0 2006.225.08:17:22.33#ibcon#about to read 6, iclass 12, count 0 2006.225.08:17:22.33#ibcon#read 6, iclass 12, count 0 2006.225.08:17:22.33#ibcon#end of sib2, iclass 12, count 0 2006.225.08:17:22.33#ibcon#*after write, iclass 12, count 0 2006.225.08:17:22.33#ibcon#*before return 0, iclass 12, count 0 2006.225.08:17:22.33#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:17:22.33#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 0 2006.225.08:17:22.33#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:17:22.33#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:17:22.33$vc4f8/vb=6,4 2006.225.08:17:22.33#ibcon#iclass 14 nclrec 2 cls_cnt 3 2006.225.08:17:22.33#ibcon#iclass 14 iclrec 1 cls_cnt 3 2006.225.08:17:22.33#ibcon#ireg 11 cls_cnt 2 2006.225.08:17:22.33#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:17:22.39#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:17:22.39#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:17:22.39#ibcon#enter wrdev, iclass 14, count 2 2006.225.08:17:22.39#ibcon#first serial, iclass 14, count 2 2006.225.08:17:22.39#ibcon#enter sib2, iclass 14, count 2 2006.225.08:17:22.39#ibcon#flushed, iclass 14, count 2 2006.225.08:17:22.39#ibcon#about to write, iclass 14, count 2 2006.225.08:17:22.39#ibcon#wrote, iclass 14, count 2 2006.225.08:17:22.39#ibcon#about to read 3, iclass 14, count 2 2006.225.08:17:22.41#ibcon#read 3, iclass 14, count 2 2006.225.08:17:22.41#ibcon#about to read 4, iclass 14, count 2 2006.225.08:17:22.41#ibcon#read 4, iclass 14, count 2 2006.225.08:17:22.41#ibcon#about to read 5, iclass 14, count 2 2006.225.08:17:22.41#ibcon#read 5, iclass 14, count 2 2006.225.08:17:22.41#ibcon#about to read 6, iclass 14, count 2 2006.225.08:17:22.41#ibcon#read 6, iclass 14, count 2 2006.225.08:17:22.41#ibcon#end of sib2, iclass 14, count 2 2006.225.08:17:22.41#ibcon#*mode == 0, iclass 14, count 2 2006.225.08:17:22.41#ibcon#*mode == 0 && serial, iclass 14, count 2 2006.225.08:17:22.41#ibcon#[27=AT06-04\r\n] 2006.225.08:17:22.41#ibcon#*before write, iclass 14, count 2 2006.225.08:17:22.41#ibcon#enter sib2, iclass 14, count 2 2006.225.08:17:22.41#ibcon#flushed, iclass 14, count 2 2006.225.08:17:22.41#ibcon#about to write, iclass 14, count 2 2006.225.08:17:22.41#ibcon#wrote, iclass 14, count 2 2006.225.08:17:22.41#ibcon#about to read 3, iclass 14, count 2 2006.225.08:17:22.44#ibcon#read 3, iclass 14, count 2 2006.225.08:17:22.44#ibcon#about to read 4, iclass 14, count 2 2006.225.08:17:22.44#ibcon#read 4, iclass 14, count 2 2006.225.08:17:22.44#ibcon#about to read 5, iclass 14, count 2 2006.225.08:17:22.44#ibcon#read 5, iclass 14, count 2 2006.225.08:17:22.44#ibcon#about to read 6, iclass 14, count 2 2006.225.08:17:22.44#ibcon#read 6, iclass 14, count 2 2006.225.08:17:22.44#ibcon#end of sib2, iclass 14, count 2 2006.225.08:17:22.44#ibcon#*after write, iclass 14, count 2 2006.225.08:17:22.44#ibcon#*before return 0, iclass 14, count 2 2006.225.08:17:22.44#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:17:22.44#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 2 2006.225.08:17:22.44#ibcon#iclass 14 iclrec 2 cls_cnt 2 2006.225.08:17:22.44#ibcon#ireg 7 cls_cnt 0 2006.225.08:17:22.44#ibcon#before find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:17:22.56#ibcon#after find_delay mode 2, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:17:22.56#ibcon#before mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:17:22.56#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:17:22.56#ibcon#first serial, iclass 14, count 0 2006.225.08:17:22.56#ibcon#enter sib2, iclass 14, count 0 2006.225.08:17:22.56#ibcon#flushed, iclass 14, count 0 2006.225.08:17:22.56#ibcon#about to write, iclass 14, count 0 2006.225.08:17:22.56#ibcon#wrote, iclass 14, count 0 2006.225.08:17:22.56#ibcon#about to read 3, iclass 14, count 0 2006.225.08:17:22.58#ibcon#read 3, iclass 14, count 0 2006.225.08:17:22.58#ibcon#about to read 4, iclass 14, count 0 2006.225.08:17:22.58#ibcon#read 4, iclass 14, count 0 2006.225.08:17:22.58#ibcon#about to read 5, iclass 14, count 0 2006.225.08:17:22.58#ibcon#read 5, iclass 14, count 0 2006.225.08:17:22.58#ibcon#about to read 6, iclass 14, count 0 2006.225.08:17:22.58#ibcon#read 6, iclass 14, count 0 2006.225.08:17:22.58#ibcon#end of sib2, iclass 14, count 0 2006.225.08:17:22.58#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:17:22.58#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:17:22.58#ibcon#[27=USB\r\n] 2006.225.08:17:22.58#ibcon#*before write, iclass 14, count 0 2006.225.08:17:22.58#ibcon#enter sib2, iclass 14, count 0 2006.225.08:17:22.58#ibcon#flushed, iclass 14, count 0 2006.225.08:17:22.58#ibcon#about to write, iclass 14, count 0 2006.225.08:17:22.58#ibcon#wrote, iclass 14, count 0 2006.225.08:17:22.58#ibcon#about to read 3, iclass 14, count 0 2006.225.08:17:22.61#ibcon#read 3, iclass 14, count 0 2006.225.08:17:22.61#ibcon#about to read 4, iclass 14, count 0 2006.225.08:17:22.61#ibcon#read 4, iclass 14, count 0 2006.225.08:17:22.61#ibcon#about to read 5, iclass 14, count 0 2006.225.08:17:22.61#ibcon#read 5, iclass 14, count 0 2006.225.08:17:22.61#ibcon#about to read 6, iclass 14, count 0 2006.225.08:17:22.61#ibcon#read 6, iclass 14, count 0 2006.225.08:17:22.61#ibcon#end of sib2, iclass 14, count 0 2006.225.08:17:22.61#ibcon#*after write, iclass 14, count 0 2006.225.08:17:22.61#ibcon#*before return 0, iclass 14, count 0 2006.225.08:17:22.61#ibcon#after mode 2 write, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:17:22.61#ibcon#end of loop, iclass 14 iclrec 2 cls_cnt 0 2006.225.08:17:22.61#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:17:22.61#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:17:22.61$vc4f8/vabw=wide 2006.225.08:17:22.61#ibcon#iclass 16 nclrec 1 cls_cnt 2 2006.225.08:17:22.61#ibcon#iclass 16 iclrec 1 cls_cnt 2 2006.225.08:17:22.61#ibcon#ireg 8 cls_cnt 0 2006.225.08:17:22.61#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:17:22.61#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:17:22.61#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:17:22.61#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:17:22.61#ibcon#first serial, iclass 16, count 0 2006.225.08:17:22.61#ibcon#enter sib2, iclass 16, count 0 2006.225.08:17:22.61#ibcon#flushed, iclass 16, count 0 2006.225.08:17:22.61#ibcon#about to write, iclass 16, count 0 2006.225.08:17:22.61#ibcon#wrote, iclass 16, count 0 2006.225.08:17:22.61#ibcon#about to read 3, iclass 16, count 0 2006.225.08:17:22.63#ibcon#read 3, iclass 16, count 0 2006.225.08:17:22.63#ibcon#about to read 4, iclass 16, count 0 2006.225.08:17:22.63#ibcon#read 4, iclass 16, count 0 2006.225.08:17:22.63#ibcon#about to read 5, iclass 16, count 0 2006.225.08:17:22.63#ibcon#read 5, iclass 16, count 0 2006.225.08:17:22.63#ibcon#about to read 6, iclass 16, count 0 2006.225.08:17:22.63#ibcon#read 6, iclass 16, count 0 2006.225.08:17:22.63#ibcon#end of sib2, iclass 16, count 0 2006.225.08:17:22.63#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:17:22.63#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:17:22.63#ibcon#[25=BW32\r\n] 2006.225.08:17:22.63#ibcon#*before write, iclass 16, count 0 2006.225.08:17:22.63#ibcon#enter sib2, iclass 16, count 0 2006.225.08:17:22.63#ibcon#flushed, iclass 16, count 0 2006.225.08:17:22.63#ibcon#about to write, iclass 16, count 0 2006.225.08:17:22.63#ibcon#wrote, iclass 16, count 0 2006.225.08:17:22.63#ibcon#about to read 3, iclass 16, count 0 2006.225.08:17:22.66#ibcon#read 3, iclass 16, count 0 2006.225.08:17:22.66#ibcon#about to read 4, iclass 16, count 0 2006.225.08:17:22.66#ibcon#read 4, iclass 16, count 0 2006.225.08:17:22.66#ibcon#about to read 5, iclass 16, count 0 2006.225.08:17:22.66#ibcon#read 5, iclass 16, count 0 2006.225.08:17:22.66#ibcon#about to read 6, iclass 16, count 0 2006.225.08:17:22.66#ibcon#read 6, iclass 16, count 0 2006.225.08:17:22.66#ibcon#end of sib2, iclass 16, count 0 2006.225.08:17:22.66#ibcon#*after write, iclass 16, count 0 2006.225.08:17:22.66#ibcon#*before return 0, iclass 16, count 0 2006.225.08:17:22.66#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:17:22.66#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 0 2006.225.08:17:22.66#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:17:22.66#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:17:22.66$vc4f8/vbbw=wide 2006.225.08:17:22.66#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.08:17:22.66#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.08:17:22.66#ibcon#ireg 8 cls_cnt 0 2006.225.08:17:22.66#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:17:22.73#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:17:22.73#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:17:22.73#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:17:22.73#ibcon#first serial, iclass 18, count 0 2006.225.08:17:22.73#ibcon#enter sib2, iclass 18, count 0 2006.225.08:17:22.73#ibcon#flushed, iclass 18, count 0 2006.225.08:17:22.73#ibcon#about to write, iclass 18, count 0 2006.225.08:17:22.73#ibcon#wrote, iclass 18, count 0 2006.225.08:17:22.73#ibcon#about to read 3, iclass 18, count 0 2006.225.08:17:22.75#ibcon#read 3, iclass 18, count 0 2006.225.08:17:22.75#ibcon#about to read 4, iclass 18, count 0 2006.225.08:17:22.75#ibcon#read 4, iclass 18, count 0 2006.225.08:17:22.75#ibcon#about to read 5, iclass 18, count 0 2006.225.08:17:22.75#ibcon#read 5, iclass 18, count 0 2006.225.08:17:22.75#ibcon#about to read 6, iclass 18, count 0 2006.225.08:17:22.75#ibcon#read 6, iclass 18, count 0 2006.225.08:17:22.75#ibcon#end of sib2, iclass 18, count 0 2006.225.08:17:22.75#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:17:22.75#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:17:22.75#ibcon#[27=BW32\r\n] 2006.225.08:17:22.75#ibcon#*before write, iclass 18, count 0 2006.225.08:17:22.75#ibcon#enter sib2, iclass 18, count 0 2006.225.08:17:22.75#ibcon#flushed, iclass 18, count 0 2006.225.08:17:22.75#ibcon#about to write, iclass 18, count 0 2006.225.08:17:22.75#ibcon#wrote, iclass 18, count 0 2006.225.08:17:22.75#ibcon#about to read 3, iclass 18, count 0 2006.225.08:17:22.78#ibcon#read 3, iclass 18, count 0 2006.225.08:17:22.78#ibcon#about to read 4, iclass 18, count 0 2006.225.08:17:22.78#ibcon#read 4, iclass 18, count 0 2006.225.08:17:22.78#ibcon#about to read 5, iclass 18, count 0 2006.225.08:17:22.78#ibcon#read 5, iclass 18, count 0 2006.225.08:17:22.78#ibcon#about to read 6, iclass 18, count 0 2006.225.08:17:22.78#ibcon#read 6, iclass 18, count 0 2006.225.08:17:22.78#ibcon#end of sib2, iclass 18, count 0 2006.225.08:17:22.78#ibcon#*after write, iclass 18, count 0 2006.225.08:17:22.78#ibcon#*before return 0, iclass 18, count 0 2006.225.08:17:22.78#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:17:22.78#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:17:22.78#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:17:22.78#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:17:22.78$4f8m12a/ifd4f 2006.225.08:17:22.78$ifd4f/lo= 2006.225.08:17:22.78$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:17:22.78$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:17:22.78$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:17:22.78$ifd4f/patch= 2006.225.08:17:22.78$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:17:22.78$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:17:22.78$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:17:22.78$4f8m12a/"form=m,16.000,1:2 2006.225.08:17:22.78$4f8m12a/"tpicd 2006.225.08:17:22.78$4f8m12a/echo=off 2006.225.08:17:22.78$4f8m12a/xlog=off 2006.225.08:17:22.78:!2006.225.08:17:50 2006.225.08:17:33.13#trakl#Source acquired 2006.225.08:17:35.13#flagr#flagr/antenna,acquired 2006.225.08:17:50.00:preob 2006.225.08:17:51.13/onsource/TRACKING 2006.225.08:17:51.13:!2006.225.08:18:00 2006.225.08:18:00.00:data_valid=on 2006.225.08:18:00.00:midob 2006.225.08:18:00.13/onsource/TRACKING 2006.225.08:18:00.13/wx/28.09,1003.3,74 2006.225.08:18:00.29/cable/+6.4046E-03 2006.225.08:18:01.38/va/01,08,usb,yes,28,29 2006.225.08:18:01.38/va/02,07,usb,yes,28,29 2006.225.08:18:01.38/va/03,06,usb,yes,30,30 2006.225.08:18:01.38/va/04,07,usb,yes,29,32 2006.225.08:18:01.38/va/05,07,usb,yes,31,33 2006.225.08:18:01.38/va/06,06,usb,yes,30,30 2006.225.08:18:01.38/va/07,06,usb,yes,31,31 2006.225.08:18:01.38/va/08,07,usb,yes,29,29 2006.225.08:18:01.61/valo/01,532.99,yes,locked 2006.225.08:18:01.61/valo/02,572.99,yes,locked 2006.225.08:18:01.61/valo/03,672.99,yes,locked 2006.225.08:18:01.61/valo/04,832.99,yes,locked 2006.225.08:18:01.61/valo/05,652.99,yes,locked 2006.225.08:18:01.61/valo/06,772.99,yes,locked 2006.225.08:18:01.61/valo/07,832.99,yes,locked 2006.225.08:18:01.61/valo/08,852.99,yes,locked 2006.225.08:18:02.70/vb/01,04,usb,yes,30,29 2006.225.08:18:02.70/vb/02,04,usb,yes,32,33 2006.225.08:18:02.70/vb/03,04,usb,yes,28,32 2006.225.08:18:02.70/vb/04,04,usb,yes,29,29 2006.225.08:18:02.70/vb/05,04,usb,yes,28,32 2006.225.08:18:02.70/vb/06,04,usb,yes,29,31 2006.225.08:18:02.70/vb/07,04,usb,yes,31,31 2006.225.08:18:02.70/vb/08,04,usb,yes,28,32 2006.225.08:18:02.94/vblo/01,632.99,yes,locked 2006.225.08:18:02.94/vblo/02,640.99,yes,locked 2006.225.08:18:02.94/vblo/03,656.99,yes,locked 2006.225.08:18:02.94/vblo/04,712.99,yes,locked 2006.225.08:18:02.94/vblo/05,744.99,yes,locked 2006.225.08:18:02.94/vblo/06,752.99,yes,locked 2006.225.08:18:02.94/vblo/07,734.99,yes,locked 2006.225.08:18:02.94/vblo/08,744.99,yes,locked 2006.225.08:18:03.09/vabw/8 2006.225.08:18:03.24/vbbw/8 2006.225.08:18:03.33/xfe/off,on,15.0 2006.225.08:18:03.72/ifatt/23,28,28,28 2006.225.08:18:04.07/fmout-gps/S +4.57E-07 2006.225.08:18:04.11:!2006.225.08:19:00 2006.225.08:19:00.01:data_valid=off 2006.225.08:19:00.02:postob 2006.225.08:19:00.17/cable/+6.4041E-03 2006.225.08:19:00.17/wx/28.09,1003.3,74 2006.225.08:19:01.07/fmout-gps/S +4.56E-07 2006.225.08:19:01.07:scan_name=225-0820,k06225,60 2006.225.08:19:01.08:source=1803+784,180045.68,782804.0,2000.0,cw 2006.225.08:19:01.14#flagr#flagr/antenna,new-source 2006.225.08:19:02.14:checkk5 2006.225.08:19:02.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:19:02.89/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:19:03.26/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:19:03.63/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:19:04.00/chk_obsdata//k5ts1/T2250818??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:19:04.37/chk_obsdata//k5ts2/T2250818??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:19:04.74/chk_obsdata//k5ts3/T2250818??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:19:05.10/chk_obsdata//k5ts4/T2250818??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:19:05.78/k5log//k5ts1_log_newline 2006.225.08:19:06.47/k5log//k5ts2_log_newline 2006.225.08:19:07.16/k5log//k5ts3_log_newline 2006.225.08:19:07.84/k5log//k5ts4_log_newline 2006.225.08:19:07.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:19:07.86:4f8m12a=3 2006.225.08:19:07.86$4f8m12a/echo=on 2006.225.08:19:07.86$4f8m12a/pcalon 2006.225.08:19:07.86$pcalon/"no phase cal control is implemented here 2006.225.08:19:07.86$4f8m12a/"tpicd=stop 2006.225.08:19:07.86$4f8m12a/vc4f8 2006.225.08:19:07.86$vc4f8/valo=1,532.99 2006.225.08:19:07.86#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.225.08:19:07.86#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.225.08:19:07.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:07.86#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:19:07.86#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:19:07.86#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:19:07.86#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:19:07.86#ibcon#first serial, iclass 25, count 0 2006.225.08:19:07.86#ibcon#enter sib2, iclass 25, count 0 2006.225.08:19:07.86#ibcon#flushed, iclass 25, count 0 2006.225.08:19:07.86#ibcon#about to write, iclass 25, count 0 2006.225.08:19:07.86#ibcon#wrote, iclass 25, count 0 2006.225.08:19:07.86#ibcon#about to read 3, iclass 25, count 0 2006.225.08:19:07.90#ibcon#read 3, iclass 25, count 0 2006.225.08:19:07.90#ibcon#about to read 4, iclass 25, count 0 2006.225.08:19:07.90#ibcon#read 4, iclass 25, count 0 2006.225.08:19:07.90#ibcon#about to read 5, iclass 25, count 0 2006.225.08:19:07.90#ibcon#read 5, iclass 25, count 0 2006.225.08:19:07.90#ibcon#about to read 6, iclass 25, count 0 2006.225.08:19:07.90#ibcon#read 6, iclass 25, count 0 2006.225.08:19:07.90#ibcon#end of sib2, iclass 25, count 0 2006.225.08:19:07.90#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:19:07.90#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:19:07.90#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:19:07.90#ibcon#*before write, iclass 25, count 0 2006.225.08:19:07.90#ibcon#enter sib2, iclass 25, count 0 2006.225.08:19:07.90#ibcon#flushed, iclass 25, count 0 2006.225.08:19:07.90#ibcon#about to write, iclass 25, count 0 2006.225.08:19:07.90#ibcon#wrote, iclass 25, count 0 2006.225.08:19:07.90#ibcon#about to read 3, iclass 25, count 0 2006.225.08:19:07.95#ibcon#read 3, iclass 25, count 0 2006.225.08:19:07.95#ibcon#about to read 4, iclass 25, count 0 2006.225.08:19:07.95#ibcon#read 4, iclass 25, count 0 2006.225.08:19:07.95#ibcon#about to read 5, iclass 25, count 0 2006.225.08:19:07.95#ibcon#read 5, iclass 25, count 0 2006.225.08:19:07.95#ibcon#about to read 6, iclass 25, count 0 2006.225.08:19:07.95#ibcon#read 6, iclass 25, count 0 2006.225.08:19:07.95#ibcon#end of sib2, iclass 25, count 0 2006.225.08:19:07.95#ibcon#*after write, iclass 25, count 0 2006.225.08:19:07.95#ibcon#*before return 0, iclass 25, count 0 2006.225.08:19:07.95#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:19:07.95#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:19:07.95#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:19:07.95#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:19:07.95$vc4f8/va=1,8 2006.225.08:19:07.95#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.225.08:19:07.95#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.225.08:19:07.95#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:07.95#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:19:07.95#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:19:07.95#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:19:07.95#ibcon#enter wrdev, iclass 27, count 2 2006.225.08:19:07.95#ibcon#first serial, iclass 27, count 2 2006.225.08:19:07.95#ibcon#enter sib2, iclass 27, count 2 2006.225.08:19:07.95#ibcon#flushed, iclass 27, count 2 2006.225.08:19:07.95#ibcon#about to write, iclass 27, count 2 2006.225.08:19:07.95#ibcon#wrote, iclass 27, count 2 2006.225.08:19:07.95#ibcon#about to read 3, iclass 27, count 2 2006.225.08:19:07.98#ibcon#read 3, iclass 27, count 2 2006.225.08:19:07.98#ibcon#about to read 4, iclass 27, count 2 2006.225.08:19:07.98#ibcon#read 4, iclass 27, count 2 2006.225.08:19:07.98#ibcon#about to read 5, iclass 27, count 2 2006.225.08:19:07.98#ibcon#read 5, iclass 27, count 2 2006.225.08:19:07.98#ibcon#about to read 6, iclass 27, count 2 2006.225.08:19:07.98#ibcon#read 6, iclass 27, count 2 2006.225.08:19:07.98#ibcon#end of sib2, iclass 27, count 2 2006.225.08:19:07.98#ibcon#*mode == 0, iclass 27, count 2 2006.225.08:19:07.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.225.08:19:07.98#ibcon#[25=AT01-08\r\n] 2006.225.08:19:07.98#ibcon#*before write, iclass 27, count 2 2006.225.08:19:07.98#ibcon#enter sib2, iclass 27, count 2 2006.225.08:19:07.98#ibcon#flushed, iclass 27, count 2 2006.225.08:19:07.98#ibcon#about to write, iclass 27, count 2 2006.225.08:19:07.98#ibcon#wrote, iclass 27, count 2 2006.225.08:19:07.98#ibcon#about to read 3, iclass 27, count 2 2006.225.08:19:08.01#ibcon#read 3, iclass 27, count 2 2006.225.08:19:08.01#ibcon#about to read 4, iclass 27, count 2 2006.225.08:19:08.01#ibcon#read 4, iclass 27, count 2 2006.225.08:19:08.01#ibcon#about to read 5, iclass 27, count 2 2006.225.08:19:08.01#ibcon#read 5, iclass 27, count 2 2006.225.08:19:08.01#ibcon#about to read 6, iclass 27, count 2 2006.225.08:19:08.01#ibcon#read 6, iclass 27, count 2 2006.225.08:19:08.01#ibcon#end of sib2, iclass 27, count 2 2006.225.08:19:08.01#ibcon#*after write, iclass 27, count 2 2006.225.08:19:08.01#ibcon#*before return 0, iclass 27, count 2 2006.225.08:19:08.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:19:08.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:19:08.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.225.08:19:08.01#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:08.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:19:08.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:19:08.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:19:08.13#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:19:08.13#ibcon#first serial, iclass 27, count 0 2006.225.08:19:08.13#ibcon#enter sib2, iclass 27, count 0 2006.225.08:19:08.13#ibcon#flushed, iclass 27, count 0 2006.225.08:19:08.13#ibcon#about to write, iclass 27, count 0 2006.225.08:19:08.13#ibcon#wrote, iclass 27, count 0 2006.225.08:19:08.13#ibcon#about to read 3, iclass 27, count 0 2006.225.08:19:08.15#ibcon#read 3, iclass 27, count 0 2006.225.08:19:08.15#ibcon#about to read 4, iclass 27, count 0 2006.225.08:19:08.15#ibcon#read 4, iclass 27, count 0 2006.225.08:19:08.15#ibcon#about to read 5, iclass 27, count 0 2006.225.08:19:08.15#ibcon#read 5, iclass 27, count 0 2006.225.08:19:08.15#ibcon#about to read 6, iclass 27, count 0 2006.225.08:19:08.15#ibcon#read 6, iclass 27, count 0 2006.225.08:19:08.15#ibcon#end of sib2, iclass 27, count 0 2006.225.08:19:08.15#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:19:08.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:19:08.15#ibcon#[25=USB\r\n] 2006.225.08:19:08.15#ibcon#*before write, iclass 27, count 0 2006.225.08:19:08.15#ibcon#enter sib2, iclass 27, count 0 2006.225.08:19:08.15#ibcon#flushed, iclass 27, count 0 2006.225.08:19:08.15#ibcon#about to write, iclass 27, count 0 2006.225.08:19:08.15#ibcon#wrote, iclass 27, count 0 2006.225.08:19:08.15#ibcon#about to read 3, iclass 27, count 0 2006.225.08:19:08.18#ibcon#read 3, iclass 27, count 0 2006.225.08:19:08.18#ibcon#about to read 4, iclass 27, count 0 2006.225.08:19:08.18#ibcon#read 4, iclass 27, count 0 2006.225.08:19:08.18#ibcon#about to read 5, iclass 27, count 0 2006.225.08:19:08.18#ibcon#read 5, iclass 27, count 0 2006.225.08:19:08.18#ibcon#about to read 6, iclass 27, count 0 2006.225.08:19:08.18#ibcon#read 6, iclass 27, count 0 2006.225.08:19:08.18#ibcon#end of sib2, iclass 27, count 0 2006.225.08:19:08.18#ibcon#*after write, iclass 27, count 0 2006.225.08:19:08.18#ibcon#*before return 0, iclass 27, count 0 2006.225.08:19:08.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:19:08.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:19:08.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:19:08.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:19:08.18$vc4f8/valo=2,572.99 2006.225.08:19:08.18#ibcon#iclass 29 nclrec 1 cls_cnt 2 2006.225.08:19:08.18#ibcon#iclass 29 iclrec 1 cls_cnt 2 2006.225.08:19:08.18#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:08.18#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:19:08.18#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:19:08.18#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:19:08.18#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:19:08.18#ibcon#first serial, iclass 29, count 0 2006.225.08:19:08.18#ibcon#enter sib2, iclass 29, count 0 2006.225.08:19:08.18#ibcon#flushed, iclass 29, count 0 2006.225.08:19:08.18#ibcon#about to write, iclass 29, count 0 2006.225.08:19:08.18#ibcon#wrote, iclass 29, count 0 2006.225.08:19:08.18#ibcon#about to read 3, iclass 29, count 0 2006.225.08:19:08.21#ibcon#read 3, iclass 29, count 0 2006.225.08:19:08.21#ibcon#about to read 4, iclass 29, count 0 2006.225.08:19:08.21#ibcon#read 4, iclass 29, count 0 2006.225.08:19:08.21#ibcon#about to read 5, iclass 29, count 0 2006.225.08:19:08.21#ibcon#read 5, iclass 29, count 0 2006.225.08:19:08.21#ibcon#about to read 6, iclass 29, count 0 2006.225.08:19:08.21#ibcon#read 6, iclass 29, count 0 2006.225.08:19:08.21#ibcon#end of sib2, iclass 29, count 0 2006.225.08:19:08.21#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:19:08.21#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:19:08.21#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:19:08.21#ibcon#*before write, iclass 29, count 0 2006.225.08:19:08.21#ibcon#enter sib2, iclass 29, count 0 2006.225.08:19:08.21#ibcon#flushed, iclass 29, count 0 2006.225.08:19:08.21#ibcon#about to write, iclass 29, count 0 2006.225.08:19:08.21#ibcon#wrote, iclass 29, count 0 2006.225.08:19:08.21#ibcon#about to read 3, iclass 29, count 0 2006.225.08:19:08.25#ibcon#read 3, iclass 29, count 0 2006.225.08:19:08.25#ibcon#about to read 4, iclass 29, count 0 2006.225.08:19:08.25#ibcon#read 4, iclass 29, count 0 2006.225.08:19:08.25#ibcon#about to read 5, iclass 29, count 0 2006.225.08:19:08.25#ibcon#read 5, iclass 29, count 0 2006.225.08:19:08.25#ibcon#about to read 6, iclass 29, count 0 2006.225.08:19:08.25#ibcon#read 6, iclass 29, count 0 2006.225.08:19:08.25#ibcon#end of sib2, iclass 29, count 0 2006.225.08:19:08.25#ibcon#*after write, iclass 29, count 0 2006.225.08:19:08.25#ibcon#*before return 0, iclass 29, count 0 2006.225.08:19:08.25#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:19:08.25#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 0 2006.225.08:19:08.25#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:19:08.25#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:19:08.25$vc4f8/va=2,7 2006.225.08:19:08.25#ibcon#iclass 31 nclrec 2 cls_cnt 3 2006.225.08:19:08.25#ibcon#iclass 31 iclrec 1 cls_cnt 3 2006.225.08:19:08.25#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:08.25#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:19:08.30#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:19:08.30#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:19:08.30#ibcon#enter wrdev, iclass 31, count 2 2006.225.08:19:08.30#ibcon#first serial, iclass 31, count 2 2006.225.08:19:08.30#ibcon#enter sib2, iclass 31, count 2 2006.225.08:19:08.30#ibcon#flushed, iclass 31, count 2 2006.225.08:19:08.30#ibcon#about to write, iclass 31, count 2 2006.225.08:19:08.30#ibcon#wrote, iclass 31, count 2 2006.225.08:19:08.30#ibcon#about to read 3, iclass 31, count 2 2006.225.08:19:08.32#ibcon#read 3, iclass 31, count 2 2006.225.08:19:08.32#ibcon#about to read 4, iclass 31, count 2 2006.225.08:19:08.32#ibcon#read 4, iclass 31, count 2 2006.225.08:19:08.32#ibcon#about to read 5, iclass 31, count 2 2006.225.08:19:08.32#ibcon#read 5, iclass 31, count 2 2006.225.08:19:08.32#ibcon#about to read 6, iclass 31, count 2 2006.225.08:19:08.32#ibcon#read 6, iclass 31, count 2 2006.225.08:19:08.32#ibcon#end of sib2, iclass 31, count 2 2006.225.08:19:08.32#ibcon#*mode == 0, iclass 31, count 2 2006.225.08:19:08.32#ibcon#*mode == 0 && serial, iclass 31, count 2 2006.225.08:19:08.32#ibcon#[25=AT02-07\r\n] 2006.225.08:19:08.32#ibcon#*before write, iclass 31, count 2 2006.225.08:19:08.32#ibcon#enter sib2, iclass 31, count 2 2006.225.08:19:08.32#ibcon#flushed, iclass 31, count 2 2006.225.08:19:08.32#ibcon#about to write, iclass 31, count 2 2006.225.08:19:08.32#ibcon#wrote, iclass 31, count 2 2006.225.08:19:08.32#ibcon#about to read 3, iclass 31, count 2 2006.225.08:19:08.35#ibcon#read 3, iclass 31, count 2 2006.225.08:19:08.35#ibcon#about to read 4, iclass 31, count 2 2006.225.08:19:08.35#ibcon#read 4, iclass 31, count 2 2006.225.08:19:08.35#ibcon#about to read 5, iclass 31, count 2 2006.225.08:19:08.35#ibcon#read 5, iclass 31, count 2 2006.225.08:19:08.35#ibcon#about to read 6, iclass 31, count 2 2006.225.08:19:08.35#ibcon#read 6, iclass 31, count 2 2006.225.08:19:08.35#ibcon#end of sib2, iclass 31, count 2 2006.225.08:19:08.35#ibcon#*after write, iclass 31, count 2 2006.225.08:19:08.35#ibcon#*before return 0, iclass 31, count 2 2006.225.08:19:08.35#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:19:08.35#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 2 2006.225.08:19:08.35#ibcon#iclass 31 iclrec 2 cls_cnt 2 2006.225.08:19:08.35#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:08.35#ibcon#before find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:19:08.47#ibcon#after find_delay mode 2, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:19:08.47#ibcon#before mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:19:08.47#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:19:08.47#ibcon#first serial, iclass 31, count 0 2006.225.08:19:08.47#ibcon#enter sib2, iclass 31, count 0 2006.225.08:19:08.47#ibcon#flushed, iclass 31, count 0 2006.225.08:19:08.47#ibcon#about to write, iclass 31, count 0 2006.225.08:19:08.47#ibcon#wrote, iclass 31, count 0 2006.225.08:19:08.47#ibcon#about to read 3, iclass 31, count 0 2006.225.08:19:08.49#ibcon#read 3, iclass 31, count 0 2006.225.08:19:08.49#ibcon#about to read 4, iclass 31, count 0 2006.225.08:19:08.49#ibcon#read 4, iclass 31, count 0 2006.225.08:19:08.49#ibcon#about to read 5, iclass 31, count 0 2006.225.08:19:08.49#ibcon#read 5, iclass 31, count 0 2006.225.08:19:08.49#ibcon#about to read 6, iclass 31, count 0 2006.225.08:19:08.49#ibcon#read 6, iclass 31, count 0 2006.225.08:19:08.49#ibcon#end of sib2, iclass 31, count 0 2006.225.08:19:08.49#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:19:08.49#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:19:08.49#ibcon#[25=USB\r\n] 2006.225.08:19:08.49#ibcon#*before write, iclass 31, count 0 2006.225.08:19:08.49#ibcon#enter sib2, iclass 31, count 0 2006.225.08:19:08.49#ibcon#flushed, iclass 31, count 0 2006.225.08:19:08.49#ibcon#about to write, iclass 31, count 0 2006.225.08:19:08.49#ibcon#wrote, iclass 31, count 0 2006.225.08:19:08.49#ibcon#about to read 3, iclass 31, count 0 2006.225.08:19:08.52#ibcon#read 3, iclass 31, count 0 2006.225.08:19:08.52#ibcon#about to read 4, iclass 31, count 0 2006.225.08:19:08.52#ibcon#read 4, iclass 31, count 0 2006.225.08:19:08.52#ibcon#about to read 5, iclass 31, count 0 2006.225.08:19:08.52#ibcon#read 5, iclass 31, count 0 2006.225.08:19:08.52#ibcon#about to read 6, iclass 31, count 0 2006.225.08:19:08.52#ibcon#read 6, iclass 31, count 0 2006.225.08:19:08.52#ibcon#end of sib2, iclass 31, count 0 2006.225.08:19:08.52#ibcon#*after write, iclass 31, count 0 2006.225.08:19:08.52#ibcon#*before return 0, iclass 31, count 0 2006.225.08:19:08.52#ibcon#after mode 2 write, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:19:08.52#ibcon#end of loop, iclass 31 iclrec 2 cls_cnt 0 2006.225.08:19:08.52#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:19:08.52#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:19:08.52$vc4f8/valo=3,672.99 2006.225.08:19:08.52#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.08:19:08.52#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.08:19:08.52#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:08.52#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:19:08.52#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:19:08.52#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:19:08.52#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:19:08.52#ibcon#first serial, iclass 33, count 0 2006.225.08:19:08.52#ibcon#enter sib2, iclass 33, count 0 2006.225.08:19:08.52#ibcon#flushed, iclass 33, count 0 2006.225.08:19:08.52#ibcon#about to write, iclass 33, count 0 2006.225.08:19:08.52#ibcon#wrote, iclass 33, count 0 2006.225.08:19:08.52#ibcon#about to read 3, iclass 33, count 0 2006.225.08:19:08.55#ibcon#read 3, iclass 33, count 0 2006.225.08:19:08.55#ibcon#about to read 4, iclass 33, count 0 2006.225.08:19:08.55#ibcon#read 4, iclass 33, count 0 2006.225.08:19:08.55#ibcon#about to read 5, iclass 33, count 0 2006.225.08:19:08.55#ibcon#read 5, iclass 33, count 0 2006.225.08:19:08.55#ibcon#about to read 6, iclass 33, count 0 2006.225.08:19:08.55#ibcon#read 6, iclass 33, count 0 2006.225.08:19:08.55#ibcon#end of sib2, iclass 33, count 0 2006.225.08:19:08.55#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:19:08.55#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:19:08.55#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:19:08.55#ibcon#*before write, iclass 33, count 0 2006.225.08:19:08.55#ibcon#enter sib2, iclass 33, count 0 2006.225.08:19:08.55#ibcon#flushed, iclass 33, count 0 2006.225.08:19:08.55#ibcon#about to write, iclass 33, count 0 2006.225.08:19:08.55#ibcon#wrote, iclass 33, count 0 2006.225.08:19:08.55#ibcon#about to read 3, iclass 33, count 0 2006.225.08:19:08.59#ibcon#read 3, iclass 33, count 0 2006.225.08:19:08.59#ibcon#about to read 4, iclass 33, count 0 2006.225.08:19:08.59#ibcon#read 4, iclass 33, count 0 2006.225.08:19:08.59#ibcon#about to read 5, iclass 33, count 0 2006.225.08:19:08.59#ibcon#read 5, iclass 33, count 0 2006.225.08:19:08.59#ibcon#about to read 6, iclass 33, count 0 2006.225.08:19:08.59#ibcon#read 6, iclass 33, count 0 2006.225.08:19:08.59#ibcon#end of sib2, iclass 33, count 0 2006.225.08:19:08.59#ibcon#*after write, iclass 33, count 0 2006.225.08:19:08.59#ibcon#*before return 0, iclass 33, count 0 2006.225.08:19:08.59#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:19:08.59#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:19:08.59#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:19:08.59#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:19:08.59$vc4f8/va=3,6 2006.225.08:19:08.59#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.08:19:08.59#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.08:19:08.59#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:08.59#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:19:08.64#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:19:08.64#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:19:08.64#ibcon#enter wrdev, iclass 35, count 2 2006.225.08:19:08.64#ibcon#first serial, iclass 35, count 2 2006.225.08:19:08.64#ibcon#enter sib2, iclass 35, count 2 2006.225.08:19:08.64#ibcon#flushed, iclass 35, count 2 2006.225.08:19:08.64#ibcon#about to write, iclass 35, count 2 2006.225.08:19:08.64#ibcon#wrote, iclass 35, count 2 2006.225.08:19:08.64#ibcon#about to read 3, iclass 35, count 2 2006.225.08:19:08.66#ibcon#read 3, iclass 35, count 2 2006.225.08:19:08.66#ibcon#about to read 4, iclass 35, count 2 2006.225.08:19:08.66#ibcon#read 4, iclass 35, count 2 2006.225.08:19:08.66#ibcon#about to read 5, iclass 35, count 2 2006.225.08:19:08.66#ibcon#read 5, iclass 35, count 2 2006.225.08:19:08.66#ibcon#about to read 6, iclass 35, count 2 2006.225.08:19:08.66#ibcon#read 6, iclass 35, count 2 2006.225.08:19:08.66#ibcon#end of sib2, iclass 35, count 2 2006.225.08:19:08.66#ibcon#*mode == 0, iclass 35, count 2 2006.225.08:19:08.66#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.08:19:08.66#ibcon#[25=AT03-06\r\n] 2006.225.08:19:08.66#ibcon#*before write, iclass 35, count 2 2006.225.08:19:08.66#ibcon#enter sib2, iclass 35, count 2 2006.225.08:19:08.66#ibcon#flushed, iclass 35, count 2 2006.225.08:19:08.66#ibcon#about to write, iclass 35, count 2 2006.225.08:19:08.66#ibcon#wrote, iclass 35, count 2 2006.225.08:19:08.66#ibcon#about to read 3, iclass 35, count 2 2006.225.08:19:08.69#ibcon#read 3, iclass 35, count 2 2006.225.08:19:08.69#ibcon#about to read 4, iclass 35, count 2 2006.225.08:19:08.69#ibcon#read 4, iclass 35, count 2 2006.225.08:19:08.69#ibcon#about to read 5, iclass 35, count 2 2006.225.08:19:08.69#ibcon#read 5, iclass 35, count 2 2006.225.08:19:08.69#ibcon#about to read 6, iclass 35, count 2 2006.225.08:19:08.69#ibcon#read 6, iclass 35, count 2 2006.225.08:19:08.69#ibcon#end of sib2, iclass 35, count 2 2006.225.08:19:08.69#ibcon#*after write, iclass 35, count 2 2006.225.08:19:08.69#ibcon#*before return 0, iclass 35, count 2 2006.225.08:19:08.69#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:19:08.69#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:19:08.69#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.08:19:08.69#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:08.69#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:19:08.81#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:19:08.81#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:19:08.81#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:19:08.81#ibcon#first serial, iclass 35, count 0 2006.225.08:19:08.81#ibcon#enter sib2, iclass 35, count 0 2006.225.08:19:08.81#ibcon#flushed, iclass 35, count 0 2006.225.08:19:08.81#ibcon#about to write, iclass 35, count 0 2006.225.08:19:08.81#ibcon#wrote, iclass 35, count 0 2006.225.08:19:08.81#ibcon#about to read 3, iclass 35, count 0 2006.225.08:19:08.83#ibcon#read 3, iclass 35, count 0 2006.225.08:19:08.83#ibcon#about to read 4, iclass 35, count 0 2006.225.08:19:08.83#ibcon#read 4, iclass 35, count 0 2006.225.08:19:08.83#ibcon#about to read 5, iclass 35, count 0 2006.225.08:19:08.83#ibcon#read 5, iclass 35, count 0 2006.225.08:19:08.83#ibcon#about to read 6, iclass 35, count 0 2006.225.08:19:08.83#ibcon#read 6, iclass 35, count 0 2006.225.08:19:08.83#ibcon#end of sib2, iclass 35, count 0 2006.225.08:19:08.83#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:19:08.83#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:19:08.83#ibcon#[25=USB\r\n] 2006.225.08:19:08.83#ibcon#*before write, iclass 35, count 0 2006.225.08:19:08.83#ibcon#enter sib2, iclass 35, count 0 2006.225.08:19:08.83#ibcon#flushed, iclass 35, count 0 2006.225.08:19:08.83#ibcon#about to write, iclass 35, count 0 2006.225.08:19:08.83#ibcon#wrote, iclass 35, count 0 2006.225.08:19:08.83#ibcon#about to read 3, iclass 35, count 0 2006.225.08:19:08.86#ibcon#read 3, iclass 35, count 0 2006.225.08:19:08.86#ibcon#about to read 4, iclass 35, count 0 2006.225.08:19:08.86#ibcon#read 4, iclass 35, count 0 2006.225.08:19:08.86#ibcon#about to read 5, iclass 35, count 0 2006.225.08:19:08.86#ibcon#read 5, iclass 35, count 0 2006.225.08:19:08.86#ibcon#about to read 6, iclass 35, count 0 2006.225.08:19:08.86#ibcon#read 6, iclass 35, count 0 2006.225.08:19:08.86#ibcon#end of sib2, iclass 35, count 0 2006.225.08:19:08.86#ibcon#*after write, iclass 35, count 0 2006.225.08:19:08.86#ibcon#*before return 0, iclass 35, count 0 2006.225.08:19:08.86#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:19:08.86#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:19:08.86#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:19:08.86#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:19:08.86$vc4f8/valo=4,832.99 2006.225.08:19:08.86#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.08:19:08.86#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.08:19:08.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:08.86#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:19:08.86#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:19:08.86#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:19:08.86#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:19:08.86#ibcon#first serial, iclass 37, count 0 2006.225.08:19:08.86#ibcon#enter sib2, iclass 37, count 0 2006.225.08:19:08.86#ibcon#flushed, iclass 37, count 0 2006.225.08:19:08.86#ibcon#about to write, iclass 37, count 0 2006.225.08:19:08.86#ibcon#wrote, iclass 37, count 0 2006.225.08:19:08.86#ibcon#about to read 3, iclass 37, count 0 2006.225.08:19:08.88#ibcon#read 3, iclass 37, count 0 2006.225.08:19:08.88#ibcon#about to read 4, iclass 37, count 0 2006.225.08:19:08.88#ibcon#read 4, iclass 37, count 0 2006.225.08:19:08.88#ibcon#about to read 5, iclass 37, count 0 2006.225.08:19:08.88#ibcon#read 5, iclass 37, count 0 2006.225.08:19:08.88#ibcon#about to read 6, iclass 37, count 0 2006.225.08:19:08.88#ibcon#read 6, iclass 37, count 0 2006.225.08:19:08.88#ibcon#end of sib2, iclass 37, count 0 2006.225.08:19:08.88#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:19:08.88#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:19:08.88#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:19:08.88#ibcon#*before write, iclass 37, count 0 2006.225.08:19:08.88#ibcon#enter sib2, iclass 37, count 0 2006.225.08:19:08.88#ibcon#flushed, iclass 37, count 0 2006.225.08:19:08.88#ibcon#about to write, iclass 37, count 0 2006.225.08:19:08.88#ibcon#wrote, iclass 37, count 0 2006.225.08:19:08.88#ibcon#about to read 3, iclass 37, count 0 2006.225.08:19:08.92#ibcon#read 3, iclass 37, count 0 2006.225.08:19:08.92#ibcon#about to read 4, iclass 37, count 0 2006.225.08:19:08.92#ibcon#read 4, iclass 37, count 0 2006.225.08:19:08.92#ibcon#about to read 5, iclass 37, count 0 2006.225.08:19:08.92#ibcon#read 5, iclass 37, count 0 2006.225.08:19:08.92#ibcon#about to read 6, iclass 37, count 0 2006.225.08:19:08.92#ibcon#read 6, iclass 37, count 0 2006.225.08:19:08.92#ibcon#end of sib2, iclass 37, count 0 2006.225.08:19:08.92#ibcon#*after write, iclass 37, count 0 2006.225.08:19:08.92#ibcon#*before return 0, iclass 37, count 0 2006.225.08:19:08.92#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:19:08.92#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:19:08.92#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:19:08.92#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:19:08.92$vc4f8/va=4,7 2006.225.08:19:08.92#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.08:19:08.92#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.08:19:08.92#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:08.92#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:19:08.98#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:19:08.98#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:19:08.98#ibcon#enter wrdev, iclass 39, count 2 2006.225.08:19:08.98#ibcon#first serial, iclass 39, count 2 2006.225.08:19:08.98#ibcon#enter sib2, iclass 39, count 2 2006.225.08:19:08.98#ibcon#flushed, iclass 39, count 2 2006.225.08:19:08.98#ibcon#about to write, iclass 39, count 2 2006.225.08:19:08.98#ibcon#wrote, iclass 39, count 2 2006.225.08:19:08.98#ibcon#about to read 3, iclass 39, count 2 2006.225.08:19:09.00#ibcon#read 3, iclass 39, count 2 2006.225.08:19:09.00#ibcon#about to read 4, iclass 39, count 2 2006.225.08:19:09.00#ibcon#read 4, iclass 39, count 2 2006.225.08:19:09.00#ibcon#about to read 5, iclass 39, count 2 2006.225.08:19:09.00#ibcon#read 5, iclass 39, count 2 2006.225.08:19:09.00#ibcon#about to read 6, iclass 39, count 2 2006.225.08:19:09.00#ibcon#read 6, iclass 39, count 2 2006.225.08:19:09.00#ibcon#end of sib2, iclass 39, count 2 2006.225.08:19:09.00#ibcon#*mode == 0, iclass 39, count 2 2006.225.08:19:09.00#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.08:19:09.00#ibcon#[25=AT04-07\r\n] 2006.225.08:19:09.00#ibcon#*before write, iclass 39, count 2 2006.225.08:19:09.00#ibcon#enter sib2, iclass 39, count 2 2006.225.08:19:09.00#ibcon#flushed, iclass 39, count 2 2006.225.08:19:09.00#ibcon#about to write, iclass 39, count 2 2006.225.08:19:09.00#ibcon#wrote, iclass 39, count 2 2006.225.08:19:09.00#ibcon#about to read 3, iclass 39, count 2 2006.225.08:19:09.03#ibcon#read 3, iclass 39, count 2 2006.225.08:19:09.03#ibcon#about to read 4, iclass 39, count 2 2006.225.08:19:09.03#ibcon#read 4, iclass 39, count 2 2006.225.08:19:09.03#ibcon#about to read 5, iclass 39, count 2 2006.225.08:19:09.03#ibcon#read 5, iclass 39, count 2 2006.225.08:19:09.03#ibcon#about to read 6, iclass 39, count 2 2006.225.08:19:09.03#ibcon#read 6, iclass 39, count 2 2006.225.08:19:09.03#ibcon#end of sib2, iclass 39, count 2 2006.225.08:19:09.03#ibcon#*after write, iclass 39, count 2 2006.225.08:19:09.03#ibcon#*before return 0, iclass 39, count 2 2006.225.08:19:09.03#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:19:09.03#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:19:09.03#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.08:19:09.03#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:09.03#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:19:09.15#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:19:09.15#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:19:09.15#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:19:09.15#ibcon#first serial, iclass 39, count 0 2006.225.08:19:09.15#ibcon#enter sib2, iclass 39, count 0 2006.225.08:19:09.15#ibcon#flushed, iclass 39, count 0 2006.225.08:19:09.15#ibcon#about to write, iclass 39, count 0 2006.225.08:19:09.15#ibcon#wrote, iclass 39, count 0 2006.225.08:19:09.15#ibcon#about to read 3, iclass 39, count 0 2006.225.08:19:09.17#ibcon#read 3, iclass 39, count 0 2006.225.08:19:09.17#ibcon#about to read 4, iclass 39, count 0 2006.225.08:19:09.17#ibcon#read 4, iclass 39, count 0 2006.225.08:19:09.17#ibcon#about to read 5, iclass 39, count 0 2006.225.08:19:09.17#ibcon#read 5, iclass 39, count 0 2006.225.08:19:09.17#ibcon#about to read 6, iclass 39, count 0 2006.225.08:19:09.17#ibcon#read 6, iclass 39, count 0 2006.225.08:19:09.17#ibcon#end of sib2, iclass 39, count 0 2006.225.08:19:09.17#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:19:09.17#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:19:09.17#ibcon#[25=USB\r\n] 2006.225.08:19:09.17#ibcon#*before write, iclass 39, count 0 2006.225.08:19:09.17#ibcon#enter sib2, iclass 39, count 0 2006.225.08:19:09.17#ibcon#flushed, iclass 39, count 0 2006.225.08:19:09.17#ibcon#about to write, iclass 39, count 0 2006.225.08:19:09.17#ibcon#wrote, iclass 39, count 0 2006.225.08:19:09.17#ibcon#about to read 3, iclass 39, count 0 2006.225.08:19:09.20#ibcon#read 3, iclass 39, count 0 2006.225.08:19:09.20#ibcon#about to read 4, iclass 39, count 0 2006.225.08:19:09.20#ibcon#read 4, iclass 39, count 0 2006.225.08:19:09.20#ibcon#about to read 5, iclass 39, count 0 2006.225.08:19:09.20#ibcon#read 5, iclass 39, count 0 2006.225.08:19:09.20#ibcon#about to read 6, iclass 39, count 0 2006.225.08:19:09.20#ibcon#read 6, iclass 39, count 0 2006.225.08:19:09.20#ibcon#end of sib2, iclass 39, count 0 2006.225.08:19:09.20#ibcon#*after write, iclass 39, count 0 2006.225.08:19:09.20#ibcon#*before return 0, iclass 39, count 0 2006.225.08:19:09.20#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:19:09.20#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:19:09.20#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:19:09.20#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:19:09.20$vc4f8/valo=5,652.99 2006.225.08:19:09.20#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.08:19:09.20#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.08:19:09.20#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:09.20#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:19:09.20#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:19:09.20#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:19:09.20#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:19:09.20#ibcon#first serial, iclass 3, count 0 2006.225.08:19:09.20#ibcon#enter sib2, iclass 3, count 0 2006.225.08:19:09.20#ibcon#flushed, iclass 3, count 0 2006.225.08:19:09.20#ibcon#about to write, iclass 3, count 0 2006.225.08:19:09.20#ibcon#wrote, iclass 3, count 0 2006.225.08:19:09.20#ibcon#about to read 3, iclass 3, count 0 2006.225.08:19:09.22#ibcon#read 3, iclass 3, count 0 2006.225.08:19:09.22#ibcon#about to read 4, iclass 3, count 0 2006.225.08:19:09.22#ibcon#read 4, iclass 3, count 0 2006.225.08:19:09.22#ibcon#about to read 5, iclass 3, count 0 2006.225.08:19:09.22#ibcon#read 5, iclass 3, count 0 2006.225.08:19:09.22#ibcon#about to read 6, iclass 3, count 0 2006.225.08:19:09.22#ibcon#read 6, iclass 3, count 0 2006.225.08:19:09.22#ibcon#end of sib2, iclass 3, count 0 2006.225.08:19:09.22#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:19:09.22#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:19:09.22#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:19:09.22#ibcon#*before write, iclass 3, count 0 2006.225.08:19:09.22#ibcon#enter sib2, iclass 3, count 0 2006.225.08:19:09.22#ibcon#flushed, iclass 3, count 0 2006.225.08:19:09.22#ibcon#about to write, iclass 3, count 0 2006.225.08:19:09.22#ibcon#wrote, iclass 3, count 0 2006.225.08:19:09.22#ibcon#about to read 3, iclass 3, count 0 2006.225.08:19:09.26#ibcon#read 3, iclass 3, count 0 2006.225.08:19:09.26#ibcon#about to read 4, iclass 3, count 0 2006.225.08:19:09.26#ibcon#read 4, iclass 3, count 0 2006.225.08:19:09.26#ibcon#about to read 5, iclass 3, count 0 2006.225.08:19:09.26#ibcon#read 5, iclass 3, count 0 2006.225.08:19:09.26#ibcon#about to read 6, iclass 3, count 0 2006.225.08:19:09.26#ibcon#read 6, iclass 3, count 0 2006.225.08:19:09.26#ibcon#end of sib2, iclass 3, count 0 2006.225.08:19:09.26#ibcon#*after write, iclass 3, count 0 2006.225.08:19:09.26#ibcon#*before return 0, iclass 3, count 0 2006.225.08:19:09.26#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:19:09.26#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:19:09.26#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:19:09.26#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:19:09.26$vc4f8/va=5,7 2006.225.08:19:09.26#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.08:19:09.26#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.08:19:09.26#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:09.26#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:19:09.32#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:19:09.32#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:19:09.32#ibcon#enter wrdev, iclass 5, count 2 2006.225.08:19:09.32#ibcon#first serial, iclass 5, count 2 2006.225.08:19:09.32#ibcon#enter sib2, iclass 5, count 2 2006.225.08:19:09.32#ibcon#flushed, iclass 5, count 2 2006.225.08:19:09.32#ibcon#about to write, iclass 5, count 2 2006.225.08:19:09.32#ibcon#wrote, iclass 5, count 2 2006.225.08:19:09.32#ibcon#about to read 3, iclass 5, count 2 2006.225.08:19:09.34#ibcon#read 3, iclass 5, count 2 2006.225.08:19:09.34#ibcon#about to read 4, iclass 5, count 2 2006.225.08:19:09.34#ibcon#read 4, iclass 5, count 2 2006.225.08:19:09.34#ibcon#about to read 5, iclass 5, count 2 2006.225.08:19:09.34#ibcon#read 5, iclass 5, count 2 2006.225.08:19:09.34#ibcon#about to read 6, iclass 5, count 2 2006.225.08:19:09.34#ibcon#read 6, iclass 5, count 2 2006.225.08:19:09.34#ibcon#end of sib2, iclass 5, count 2 2006.225.08:19:09.34#ibcon#*mode == 0, iclass 5, count 2 2006.225.08:19:09.34#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.08:19:09.34#ibcon#[25=AT05-07\r\n] 2006.225.08:19:09.34#ibcon#*before write, iclass 5, count 2 2006.225.08:19:09.34#ibcon#enter sib2, iclass 5, count 2 2006.225.08:19:09.34#ibcon#flushed, iclass 5, count 2 2006.225.08:19:09.34#ibcon#about to write, iclass 5, count 2 2006.225.08:19:09.34#ibcon#wrote, iclass 5, count 2 2006.225.08:19:09.34#ibcon#about to read 3, iclass 5, count 2 2006.225.08:19:09.37#ibcon#read 3, iclass 5, count 2 2006.225.08:19:09.37#ibcon#about to read 4, iclass 5, count 2 2006.225.08:19:09.37#ibcon#read 4, iclass 5, count 2 2006.225.08:19:09.37#ibcon#about to read 5, iclass 5, count 2 2006.225.08:19:09.37#ibcon#read 5, iclass 5, count 2 2006.225.08:19:09.37#ibcon#about to read 6, iclass 5, count 2 2006.225.08:19:09.37#ibcon#read 6, iclass 5, count 2 2006.225.08:19:09.37#ibcon#end of sib2, iclass 5, count 2 2006.225.08:19:09.37#ibcon#*after write, iclass 5, count 2 2006.225.08:19:09.37#ibcon#*before return 0, iclass 5, count 2 2006.225.08:19:09.37#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:19:09.37#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:19:09.37#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.08:19:09.37#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:09.37#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:19:09.49#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:19:09.49#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:19:09.49#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:19:09.49#ibcon#first serial, iclass 5, count 0 2006.225.08:19:09.49#ibcon#enter sib2, iclass 5, count 0 2006.225.08:19:09.49#ibcon#flushed, iclass 5, count 0 2006.225.08:19:09.49#ibcon#about to write, iclass 5, count 0 2006.225.08:19:09.49#ibcon#wrote, iclass 5, count 0 2006.225.08:19:09.49#ibcon#about to read 3, iclass 5, count 0 2006.225.08:19:09.51#ibcon#read 3, iclass 5, count 0 2006.225.08:19:09.51#ibcon#about to read 4, iclass 5, count 0 2006.225.08:19:09.51#ibcon#read 4, iclass 5, count 0 2006.225.08:19:09.51#ibcon#about to read 5, iclass 5, count 0 2006.225.08:19:09.51#ibcon#read 5, iclass 5, count 0 2006.225.08:19:09.51#ibcon#about to read 6, iclass 5, count 0 2006.225.08:19:09.51#ibcon#read 6, iclass 5, count 0 2006.225.08:19:09.51#ibcon#end of sib2, iclass 5, count 0 2006.225.08:19:09.51#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:19:09.51#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:19:09.51#ibcon#[25=USB\r\n] 2006.225.08:19:09.51#ibcon#*before write, iclass 5, count 0 2006.225.08:19:09.51#ibcon#enter sib2, iclass 5, count 0 2006.225.08:19:09.51#ibcon#flushed, iclass 5, count 0 2006.225.08:19:09.51#ibcon#about to write, iclass 5, count 0 2006.225.08:19:09.51#ibcon#wrote, iclass 5, count 0 2006.225.08:19:09.51#ibcon#about to read 3, iclass 5, count 0 2006.225.08:19:09.54#ibcon#read 3, iclass 5, count 0 2006.225.08:19:09.54#ibcon#about to read 4, iclass 5, count 0 2006.225.08:19:09.54#ibcon#read 4, iclass 5, count 0 2006.225.08:19:09.54#ibcon#about to read 5, iclass 5, count 0 2006.225.08:19:09.54#ibcon#read 5, iclass 5, count 0 2006.225.08:19:09.54#ibcon#about to read 6, iclass 5, count 0 2006.225.08:19:09.54#ibcon#read 6, iclass 5, count 0 2006.225.08:19:09.54#ibcon#end of sib2, iclass 5, count 0 2006.225.08:19:09.54#ibcon#*after write, iclass 5, count 0 2006.225.08:19:09.54#ibcon#*before return 0, iclass 5, count 0 2006.225.08:19:09.54#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:19:09.54#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:19:09.54#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:19:09.54#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:19:09.54$vc4f8/valo=6,772.99 2006.225.08:19:09.54#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.225.08:19:09.54#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.225.08:19:09.54#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:09.54#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:19:09.54#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:19:09.54#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:19:09.54#ibcon#enter wrdev, iclass 7, count 0 2006.225.08:19:09.54#ibcon#first serial, iclass 7, count 0 2006.225.08:19:09.54#ibcon#enter sib2, iclass 7, count 0 2006.225.08:19:09.54#ibcon#flushed, iclass 7, count 0 2006.225.08:19:09.54#ibcon#about to write, iclass 7, count 0 2006.225.08:19:09.54#ibcon#wrote, iclass 7, count 0 2006.225.08:19:09.54#ibcon#about to read 3, iclass 7, count 0 2006.225.08:19:09.56#ibcon#read 3, iclass 7, count 0 2006.225.08:19:09.56#ibcon#about to read 4, iclass 7, count 0 2006.225.08:19:09.56#ibcon#read 4, iclass 7, count 0 2006.225.08:19:09.56#ibcon#about to read 5, iclass 7, count 0 2006.225.08:19:09.56#ibcon#read 5, iclass 7, count 0 2006.225.08:19:09.56#ibcon#about to read 6, iclass 7, count 0 2006.225.08:19:09.56#ibcon#read 6, iclass 7, count 0 2006.225.08:19:09.56#ibcon#end of sib2, iclass 7, count 0 2006.225.08:19:09.56#ibcon#*mode == 0, iclass 7, count 0 2006.225.08:19:09.56#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.08:19:09.56#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:19:09.56#ibcon#*before write, iclass 7, count 0 2006.225.08:19:09.56#ibcon#enter sib2, iclass 7, count 0 2006.225.08:19:09.56#ibcon#flushed, iclass 7, count 0 2006.225.08:19:09.56#ibcon#about to write, iclass 7, count 0 2006.225.08:19:09.56#ibcon#wrote, iclass 7, count 0 2006.225.08:19:09.56#ibcon#about to read 3, iclass 7, count 0 2006.225.08:19:09.60#ibcon#read 3, iclass 7, count 0 2006.225.08:19:09.60#ibcon#about to read 4, iclass 7, count 0 2006.225.08:19:09.60#ibcon#read 4, iclass 7, count 0 2006.225.08:19:09.60#ibcon#about to read 5, iclass 7, count 0 2006.225.08:19:09.60#ibcon#read 5, iclass 7, count 0 2006.225.08:19:09.60#ibcon#about to read 6, iclass 7, count 0 2006.225.08:19:09.60#ibcon#read 6, iclass 7, count 0 2006.225.08:19:09.60#ibcon#end of sib2, iclass 7, count 0 2006.225.08:19:09.60#ibcon#*after write, iclass 7, count 0 2006.225.08:19:09.60#ibcon#*before return 0, iclass 7, count 0 2006.225.08:19:09.60#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:19:09.60#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:19:09.60#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.08:19:09.60#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.08:19:09.60$vc4f8/va=6,6 2006.225.08:19:09.60#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.225.08:19:09.60#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.225.08:19:09.60#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:09.60#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:19:09.66#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:19:09.66#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:19:09.66#ibcon#enter wrdev, iclass 11, count 2 2006.225.08:19:09.66#ibcon#first serial, iclass 11, count 2 2006.225.08:19:09.66#ibcon#enter sib2, iclass 11, count 2 2006.225.08:19:09.66#ibcon#flushed, iclass 11, count 2 2006.225.08:19:09.66#ibcon#about to write, iclass 11, count 2 2006.225.08:19:09.66#ibcon#wrote, iclass 11, count 2 2006.225.08:19:09.66#ibcon#about to read 3, iclass 11, count 2 2006.225.08:19:09.68#ibcon#read 3, iclass 11, count 2 2006.225.08:19:09.68#ibcon#about to read 4, iclass 11, count 2 2006.225.08:19:09.68#ibcon#read 4, iclass 11, count 2 2006.225.08:19:09.68#ibcon#about to read 5, iclass 11, count 2 2006.225.08:19:09.68#ibcon#read 5, iclass 11, count 2 2006.225.08:19:09.68#ibcon#about to read 6, iclass 11, count 2 2006.225.08:19:09.68#ibcon#read 6, iclass 11, count 2 2006.225.08:19:09.68#ibcon#end of sib2, iclass 11, count 2 2006.225.08:19:09.68#ibcon#*mode == 0, iclass 11, count 2 2006.225.08:19:09.68#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.225.08:19:09.68#ibcon#[25=AT06-06\r\n] 2006.225.08:19:09.68#ibcon#*before write, iclass 11, count 2 2006.225.08:19:09.68#ibcon#enter sib2, iclass 11, count 2 2006.225.08:19:09.68#ibcon#flushed, iclass 11, count 2 2006.225.08:19:09.68#ibcon#about to write, iclass 11, count 2 2006.225.08:19:09.68#ibcon#wrote, iclass 11, count 2 2006.225.08:19:09.68#ibcon#about to read 3, iclass 11, count 2 2006.225.08:19:09.71#ibcon#read 3, iclass 11, count 2 2006.225.08:19:09.71#ibcon#about to read 4, iclass 11, count 2 2006.225.08:19:09.71#ibcon#read 4, iclass 11, count 2 2006.225.08:19:09.71#ibcon#about to read 5, iclass 11, count 2 2006.225.08:19:09.71#ibcon#read 5, iclass 11, count 2 2006.225.08:19:09.71#ibcon#about to read 6, iclass 11, count 2 2006.225.08:19:09.71#ibcon#read 6, iclass 11, count 2 2006.225.08:19:09.71#ibcon#end of sib2, iclass 11, count 2 2006.225.08:19:09.71#ibcon#*after write, iclass 11, count 2 2006.225.08:19:09.71#ibcon#*before return 0, iclass 11, count 2 2006.225.08:19:09.71#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:19:09.71#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:19:09.71#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.225.08:19:09.71#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:09.71#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:19:09.83#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:19:09.83#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:19:09.83#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:19:09.83#ibcon#first serial, iclass 11, count 0 2006.225.08:19:09.83#ibcon#enter sib2, iclass 11, count 0 2006.225.08:19:09.83#ibcon#flushed, iclass 11, count 0 2006.225.08:19:09.83#ibcon#about to write, iclass 11, count 0 2006.225.08:19:09.83#ibcon#wrote, iclass 11, count 0 2006.225.08:19:09.83#ibcon#about to read 3, iclass 11, count 0 2006.225.08:19:09.85#ibcon#read 3, iclass 11, count 0 2006.225.08:19:09.85#ibcon#about to read 4, iclass 11, count 0 2006.225.08:19:09.85#ibcon#read 4, iclass 11, count 0 2006.225.08:19:09.85#ibcon#about to read 5, iclass 11, count 0 2006.225.08:19:09.85#ibcon#read 5, iclass 11, count 0 2006.225.08:19:09.85#ibcon#about to read 6, iclass 11, count 0 2006.225.08:19:09.85#ibcon#read 6, iclass 11, count 0 2006.225.08:19:09.85#ibcon#end of sib2, iclass 11, count 0 2006.225.08:19:09.85#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:19:09.85#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:19:09.85#ibcon#[25=USB\r\n] 2006.225.08:19:09.85#ibcon#*before write, iclass 11, count 0 2006.225.08:19:09.85#ibcon#enter sib2, iclass 11, count 0 2006.225.08:19:09.85#ibcon#flushed, iclass 11, count 0 2006.225.08:19:09.85#ibcon#about to write, iclass 11, count 0 2006.225.08:19:09.85#ibcon#wrote, iclass 11, count 0 2006.225.08:19:09.85#ibcon#about to read 3, iclass 11, count 0 2006.225.08:19:09.88#ibcon#read 3, iclass 11, count 0 2006.225.08:19:09.88#ibcon#about to read 4, iclass 11, count 0 2006.225.08:19:09.88#ibcon#read 4, iclass 11, count 0 2006.225.08:19:09.88#ibcon#about to read 5, iclass 11, count 0 2006.225.08:19:09.88#ibcon#read 5, iclass 11, count 0 2006.225.08:19:09.88#ibcon#about to read 6, iclass 11, count 0 2006.225.08:19:09.88#ibcon#read 6, iclass 11, count 0 2006.225.08:19:09.88#ibcon#end of sib2, iclass 11, count 0 2006.225.08:19:09.88#ibcon#*after write, iclass 11, count 0 2006.225.08:19:09.88#ibcon#*before return 0, iclass 11, count 0 2006.225.08:19:09.88#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:19:09.88#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:19:09.88#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:19:09.88#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:19:09.88$vc4f8/valo=7,832.99 2006.225.08:19:09.88#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.08:19:09.88#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.08:19:09.88#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:09.88#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:19:09.88#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:19:09.88#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:19:09.88#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:19:09.88#ibcon#first serial, iclass 13, count 0 2006.225.08:19:09.88#ibcon#enter sib2, iclass 13, count 0 2006.225.08:19:09.88#ibcon#flushed, iclass 13, count 0 2006.225.08:19:09.88#ibcon#about to write, iclass 13, count 0 2006.225.08:19:09.88#ibcon#wrote, iclass 13, count 0 2006.225.08:19:09.88#ibcon#about to read 3, iclass 13, count 0 2006.225.08:19:09.90#ibcon#read 3, iclass 13, count 0 2006.225.08:19:09.90#ibcon#about to read 4, iclass 13, count 0 2006.225.08:19:09.90#ibcon#read 4, iclass 13, count 0 2006.225.08:19:09.90#ibcon#about to read 5, iclass 13, count 0 2006.225.08:19:09.90#ibcon#read 5, iclass 13, count 0 2006.225.08:19:09.90#ibcon#about to read 6, iclass 13, count 0 2006.225.08:19:09.90#ibcon#read 6, iclass 13, count 0 2006.225.08:19:09.90#ibcon#end of sib2, iclass 13, count 0 2006.225.08:19:09.90#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:19:09.90#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:19:09.90#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:19:09.90#ibcon#*before write, iclass 13, count 0 2006.225.08:19:09.90#ibcon#enter sib2, iclass 13, count 0 2006.225.08:19:09.90#ibcon#flushed, iclass 13, count 0 2006.225.08:19:09.90#ibcon#about to write, iclass 13, count 0 2006.225.08:19:09.90#ibcon#wrote, iclass 13, count 0 2006.225.08:19:09.90#ibcon#about to read 3, iclass 13, count 0 2006.225.08:19:09.94#ibcon#read 3, iclass 13, count 0 2006.225.08:19:09.94#ibcon#about to read 4, iclass 13, count 0 2006.225.08:19:09.94#ibcon#read 4, iclass 13, count 0 2006.225.08:19:09.94#ibcon#about to read 5, iclass 13, count 0 2006.225.08:19:09.94#ibcon#read 5, iclass 13, count 0 2006.225.08:19:09.94#ibcon#about to read 6, iclass 13, count 0 2006.225.08:19:09.94#ibcon#read 6, iclass 13, count 0 2006.225.08:19:09.94#ibcon#end of sib2, iclass 13, count 0 2006.225.08:19:09.94#ibcon#*after write, iclass 13, count 0 2006.225.08:19:09.94#ibcon#*before return 0, iclass 13, count 0 2006.225.08:19:09.94#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:19:09.94#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:19:09.94#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:19:09.94#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:19:09.94$vc4f8/va=7,6 2006.225.08:19:09.94#ibcon#iclass 15 nclrec 2 cls_cnt 3 2006.225.08:19:09.94#ibcon#iclass 15 iclrec 1 cls_cnt 3 2006.225.08:19:09.94#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:09.94#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:19:10.00#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:19:10.00#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:19:10.00#ibcon#enter wrdev, iclass 15, count 2 2006.225.08:19:10.00#ibcon#first serial, iclass 15, count 2 2006.225.08:19:10.00#ibcon#enter sib2, iclass 15, count 2 2006.225.08:19:10.00#ibcon#flushed, iclass 15, count 2 2006.225.08:19:10.00#ibcon#about to write, iclass 15, count 2 2006.225.08:19:10.00#ibcon#wrote, iclass 15, count 2 2006.225.08:19:10.00#ibcon#about to read 3, iclass 15, count 2 2006.225.08:19:10.02#ibcon#read 3, iclass 15, count 2 2006.225.08:19:10.02#ibcon#about to read 4, iclass 15, count 2 2006.225.08:19:10.02#ibcon#read 4, iclass 15, count 2 2006.225.08:19:10.02#ibcon#about to read 5, iclass 15, count 2 2006.225.08:19:10.02#ibcon#read 5, iclass 15, count 2 2006.225.08:19:10.02#ibcon#about to read 6, iclass 15, count 2 2006.225.08:19:10.02#ibcon#read 6, iclass 15, count 2 2006.225.08:19:10.02#ibcon#end of sib2, iclass 15, count 2 2006.225.08:19:10.02#ibcon#*mode == 0, iclass 15, count 2 2006.225.08:19:10.02#ibcon#*mode == 0 && serial, iclass 15, count 2 2006.225.08:19:10.02#ibcon#[25=AT07-06\r\n] 2006.225.08:19:10.02#ibcon#*before write, iclass 15, count 2 2006.225.08:19:10.02#ibcon#enter sib2, iclass 15, count 2 2006.225.08:19:10.02#ibcon#flushed, iclass 15, count 2 2006.225.08:19:10.02#ibcon#about to write, iclass 15, count 2 2006.225.08:19:10.02#ibcon#wrote, iclass 15, count 2 2006.225.08:19:10.02#ibcon#about to read 3, iclass 15, count 2 2006.225.08:19:10.05#ibcon#read 3, iclass 15, count 2 2006.225.08:19:10.05#ibcon#about to read 4, iclass 15, count 2 2006.225.08:19:10.05#ibcon#read 4, iclass 15, count 2 2006.225.08:19:10.05#ibcon#about to read 5, iclass 15, count 2 2006.225.08:19:10.05#ibcon#read 5, iclass 15, count 2 2006.225.08:19:10.05#ibcon#about to read 6, iclass 15, count 2 2006.225.08:19:10.05#ibcon#read 6, iclass 15, count 2 2006.225.08:19:10.05#ibcon#end of sib2, iclass 15, count 2 2006.225.08:19:10.05#ibcon#*after write, iclass 15, count 2 2006.225.08:19:10.05#ibcon#*before return 0, iclass 15, count 2 2006.225.08:19:10.05#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:19:10.05#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 2 2006.225.08:19:10.05#ibcon#iclass 15 iclrec 2 cls_cnt 2 2006.225.08:19:10.05#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:10.05#ibcon#before find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:19:10.17#ibcon#after find_delay mode 2, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:19:10.17#ibcon#before mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:19:10.17#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:19:10.17#ibcon#first serial, iclass 15, count 0 2006.225.08:19:10.17#ibcon#enter sib2, iclass 15, count 0 2006.225.08:19:10.17#ibcon#flushed, iclass 15, count 0 2006.225.08:19:10.17#ibcon#about to write, iclass 15, count 0 2006.225.08:19:10.17#ibcon#wrote, iclass 15, count 0 2006.225.08:19:10.17#ibcon#about to read 3, iclass 15, count 0 2006.225.08:19:10.19#ibcon#read 3, iclass 15, count 0 2006.225.08:19:10.19#ibcon#about to read 4, iclass 15, count 0 2006.225.08:19:10.19#ibcon#read 4, iclass 15, count 0 2006.225.08:19:10.19#ibcon#about to read 5, iclass 15, count 0 2006.225.08:19:10.19#ibcon#read 5, iclass 15, count 0 2006.225.08:19:10.19#ibcon#about to read 6, iclass 15, count 0 2006.225.08:19:10.19#ibcon#read 6, iclass 15, count 0 2006.225.08:19:10.19#ibcon#end of sib2, iclass 15, count 0 2006.225.08:19:10.19#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:19:10.19#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:19:10.19#ibcon#[25=USB\r\n] 2006.225.08:19:10.19#ibcon#*before write, iclass 15, count 0 2006.225.08:19:10.19#ibcon#enter sib2, iclass 15, count 0 2006.225.08:19:10.19#ibcon#flushed, iclass 15, count 0 2006.225.08:19:10.19#ibcon#about to write, iclass 15, count 0 2006.225.08:19:10.19#ibcon#wrote, iclass 15, count 0 2006.225.08:19:10.19#ibcon#about to read 3, iclass 15, count 0 2006.225.08:19:10.22#ibcon#read 3, iclass 15, count 0 2006.225.08:19:10.22#ibcon#about to read 4, iclass 15, count 0 2006.225.08:19:10.22#ibcon#read 4, iclass 15, count 0 2006.225.08:19:10.22#ibcon#about to read 5, iclass 15, count 0 2006.225.08:19:10.22#ibcon#read 5, iclass 15, count 0 2006.225.08:19:10.22#ibcon#about to read 6, iclass 15, count 0 2006.225.08:19:10.22#ibcon#read 6, iclass 15, count 0 2006.225.08:19:10.22#ibcon#end of sib2, iclass 15, count 0 2006.225.08:19:10.22#ibcon#*after write, iclass 15, count 0 2006.225.08:19:10.22#ibcon#*before return 0, iclass 15, count 0 2006.225.08:19:10.22#ibcon#after mode 2 write, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:19:10.22#ibcon#end of loop, iclass 15 iclrec 2 cls_cnt 0 2006.225.08:19:10.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:19:10.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:19:10.22$vc4f8/valo=8,852.99 2006.225.08:19:10.22#ibcon#iclass 17 nclrec 1 cls_cnt 2 2006.225.08:19:10.22#ibcon#iclass 17 iclrec 1 cls_cnt 2 2006.225.08:19:10.22#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:10.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:19:10.22#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:19:10.22#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:19:10.22#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:19:10.22#ibcon#first serial, iclass 17, count 0 2006.225.08:19:10.22#ibcon#enter sib2, iclass 17, count 0 2006.225.08:19:10.22#ibcon#flushed, iclass 17, count 0 2006.225.08:19:10.22#ibcon#about to write, iclass 17, count 0 2006.225.08:19:10.22#ibcon#wrote, iclass 17, count 0 2006.225.08:19:10.22#ibcon#about to read 3, iclass 17, count 0 2006.225.08:19:10.24#ibcon#read 3, iclass 17, count 0 2006.225.08:19:10.24#ibcon#about to read 4, iclass 17, count 0 2006.225.08:19:10.24#ibcon#read 4, iclass 17, count 0 2006.225.08:19:10.24#ibcon#about to read 5, iclass 17, count 0 2006.225.08:19:10.24#ibcon#read 5, iclass 17, count 0 2006.225.08:19:10.24#ibcon#about to read 6, iclass 17, count 0 2006.225.08:19:10.24#ibcon#read 6, iclass 17, count 0 2006.225.08:19:10.24#ibcon#end of sib2, iclass 17, count 0 2006.225.08:19:10.24#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:19:10.24#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:19:10.24#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:19:10.24#ibcon#*before write, iclass 17, count 0 2006.225.08:19:10.24#ibcon#enter sib2, iclass 17, count 0 2006.225.08:19:10.24#ibcon#flushed, iclass 17, count 0 2006.225.08:19:10.24#ibcon#about to write, iclass 17, count 0 2006.225.08:19:10.24#ibcon#wrote, iclass 17, count 0 2006.225.08:19:10.24#ibcon#about to read 3, iclass 17, count 0 2006.225.08:19:10.28#ibcon#read 3, iclass 17, count 0 2006.225.08:19:10.28#ibcon#about to read 4, iclass 17, count 0 2006.225.08:19:10.28#ibcon#read 4, iclass 17, count 0 2006.225.08:19:10.28#ibcon#about to read 5, iclass 17, count 0 2006.225.08:19:10.28#ibcon#read 5, iclass 17, count 0 2006.225.08:19:10.28#ibcon#about to read 6, iclass 17, count 0 2006.225.08:19:10.28#ibcon#read 6, iclass 17, count 0 2006.225.08:19:10.28#ibcon#end of sib2, iclass 17, count 0 2006.225.08:19:10.28#ibcon#*after write, iclass 17, count 0 2006.225.08:19:10.28#ibcon#*before return 0, iclass 17, count 0 2006.225.08:19:10.28#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:19:10.28#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 0 2006.225.08:19:10.28#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:19:10.28#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:19:10.28$vc4f8/va=8,7 2006.225.08:19:10.28#ibcon#iclass 19 nclrec 2 cls_cnt 3 2006.225.08:19:10.28#ibcon#iclass 19 iclrec 1 cls_cnt 3 2006.225.08:19:10.28#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:10.28#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:19:10.34#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:19:10.34#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:19:10.34#ibcon#enter wrdev, iclass 19, count 2 2006.225.08:19:10.34#ibcon#first serial, iclass 19, count 2 2006.225.08:19:10.34#ibcon#enter sib2, iclass 19, count 2 2006.225.08:19:10.34#ibcon#flushed, iclass 19, count 2 2006.225.08:19:10.34#ibcon#about to write, iclass 19, count 2 2006.225.08:19:10.34#ibcon#wrote, iclass 19, count 2 2006.225.08:19:10.34#ibcon#about to read 3, iclass 19, count 2 2006.225.08:19:10.36#ibcon#read 3, iclass 19, count 2 2006.225.08:19:10.36#ibcon#about to read 4, iclass 19, count 2 2006.225.08:19:10.36#ibcon#read 4, iclass 19, count 2 2006.225.08:19:10.36#ibcon#about to read 5, iclass 19, count 2 2006.225.08:19:10.36#ibcon#read 5, iclass 19, count 2 2006.225.08:19:10.36#ibcon#about to read 6, iclass 19, count 2 2006.225.08:19:10.36#ibcon#read 6, iclass 19, count 2 2006.225.08:19:10.36#ibcon#end of sib2, iclass 19, count 2 2006.225.08:19:10.36#ibcon#*mode == 0, iclass 19, count 2 2006.225.08:19:10.36#ibcon#*mode == 0 && serial, iclass 19, count 2 2006.225.08:19:10.36#ibcon#[25=AT08-07\r\n] 2006.225.08:19:10.36#ibcon#*before write, iclass 19, count 2 2006.225.08:19:10.36#ibcon#enter sib2, iclass 19, count 2 2006.225.08:19:10.36#ibcon#flushed, iclass 19, count 2 2006.225.08:19:10.36#ibcon#about to write, iclass 19, count 2 2006.225.08:19:10.36#ibcon#wrote, iclass 19, count 2 2006.225.08:19:10.36#ibcon#about to read 3, iclass 19, count 2 2006.225.08:19:10.39#ibcon#read 3, iclass 19, count 2 2006.225.08:19:10.39#ibcon#about to read 4, iclass 19, count 2 2006.225.08:19:10.39#ibcon#read 4, iclass 19, count 2 2006.225.08:19:10.39#ibcon#about to read 5, iclass 19, count 2 2006.225.08:19:10.39#ibcon#read 5, iclass 19, count 2 2006.225.08:19:10.39#ibcon#about to read 6, iclass 19, count 2 2006.225.08:19:10.39#ibcon#read 6, iclass 19, count 2 2006.225.08:19:10.39#ibcon#end of sib2, iclass 19, count 2 2006.225.08:19:10.39#ibcon#*after write, iclass 19, count 2 2006.225.08:19:10.39#ibcon#*before return 0, iclass 19, count 2 2006.225.08:19:10.39#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:19:10.39#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 2 2006.225.08:19:10.39#ibcon#iclass 19 iclrec 2 cls_cnt 2 2006.225.08:19:10.39#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:10.39#ibcon#before find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:19:10.51#ibcon#after find_delay mode 2, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:19:10.51#ibcon#before mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:19:10.51#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:19:10.51#ibcon#first serial, iclass 19, count 0 2006.225.08:19:10.51#ibcon#enter sib2, iclass 19, count 0 2006.225.08:19:10.51#ibcon#flushed, iclass 19, count 0 2006.225.08:19:10.51#ibcon#about to write, iclass 19, count 0 2006.225.08:19:10.51#ibcon#wrote, iclass 19, count 0 2006.225.08:19:10.51#ibcon#about to read 3, iclass 19, count 0 2006.225.08:19:10.53#ibcon#read 3, iclass 19, count 0 2006.225.08:19:10.53#ibcon#about to read 4, iclass 19, count 0 2006.225.08:19:10.53#ibcon#read 4, iclass 19, count 0 2006.225.08:19:10.53#ibcon#about to read 5, iclass 19, count 0 2006.225.08:19:10.53#ibcon#read 5, iclass 19, count 0 2006.225.08:19:10.53#ibcon#about to read 6, iclass 19, count 0 2006.225.08:19:10.53#ibcon#read 6, iclass 19, count 0 2006.225.08:19:10.53#ibcon#end of sib2, iclass 19, count 0 2006.225.08:19:10.53#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:19:10.53#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:19:10.53#ibcon#[25=USB\r\n] 2006.225.08:19:10.53#ibcon#*before write, iclass 19, count 0 2006.225.08:19:10.53#ibcon#enter sib2, iclass 19, count 0 2006.225.08:19:10.53#ibcon#flushed, iclass 19, count 0 2006.225.08:19:10.53#ibcon#about to write, iclass 19, count 0 2006.225.08:19:10.53#ibcon#wrote, iclass 19, count 0 2006.225.08:19:10.53#ibcon#about to read 3, iclass 19, count 0 2006.225.08:19:10.56#ibcon#read 3, iclass 19, count 0 2006.225.08:19:10.56#ibcon#about to read 4, iclass 19, count 0 2006.225.08:19:10.56#ibcon#read 4, iclass 19, count 0 2006.225.08:19:10.56#ibcon#about to read 5, iclass 19, count 0 2006.225.08:19:10.56#ibcon#read 5, iclass 19, count 0 2006.225.08:19:10.56#ibcon#about to read 6, iclass 19, count 0 2006.225.08:19:10.56#ibcon#read 6, iclass 19, count 0 2006.225.08:19:10.56#ibcon#end of sib2, iclass 19, count 0 2006.225.08:19:10.56#ibcon#*after write, iclass 19, count 0 2006.225.08:19:10.56#ibcon#*before return 0, iclass 19, count 0 2006.225.08:19:10.56#ibcon#after mode 2 write, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:19:10.56#ibcon#end of loop, iclass 19 iclrec 2 cls_cnt 0 2006.225.08:19:10.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:19:10.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:19:10.56$vc4f8/vblo=1,632.99 2006.225.08:19:10.56#ibcon#iclass 21 nclrec 1 cls_cnt 2 2006.225.08:19:10.56#ibcon#iclass 21 iclrec 1 cls_cnt 2 2006.225.08:19:10.56#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:10.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:19:10.56#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:19:10.56#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:19:10.56#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:19:10.56#ibcon#first serial, iclass 21, count 0 2006.225.08:19:10.56#ibcon#enter sib2, iclass 21, count 0 2006.225.08:19:10.56#ibcon#flushed, iclass 21, count 0 2006.225.08:19:10.56#ibcon#about to write, iclass 21, count 0 2006.225.08:19:10.56#ibcon#wrote, iclass 21, count 0 2006.225.08:19:10.56#ibcon#about to read 3, iclass 21, count 0 2006.225.08:19:10.58#ibcon#read 3, iclass 21, count 0 2006.225.08:19:10.58#ibcon#about to read 4, iclass 21, count 0 2006.225.08:19:10.58#ibcon#read 4, iclass 21, count 0 2006.225.08:19:10.58#ibcon#about to read 5, iclass 21, count 0 2006.225.08:19:10.58#ibcon#read 5, iclass 21, count 0 2006.225.08:19:10.58#ibcon#about to read 6, iclass 21, count 0 2006.225.08:19:10.58#ibcon#read 6, iclass 21, count 0 2006.225.08:19:10.58#ibcon#end of sib2, iclass 21, count 0 2006.225.08:19:10.58#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:19:10.58#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:19:10.58#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:19:10.58#ibcon#*before write, iclass 21, count 0 2006.225.08:19:10.58#ibcon#enter sib2, iclass 21, count 0 2006.225.08:19:10.58#ibcon#flushed, iclass 21, count 0 2006.225.08:19:10.58#ibcon#about to write, iclass 21, count 0 2006.225.08:19:10.58#ibcon#wrote, iclass 21, count 0 2006.225.08:19:10.58#ibcon#about to read 3, iclass 21, count 0 2006.225.08:19:10.62#ibcon#read 3, iclass 21, count 0 2006.225.08:19:10.62#ibcon#about to read 4, iclass 21, count 0 2006.225.08:19:10.62#ibcon#read 4, iclass 21, count 0 2006.225.08:19:10.62#ibcon#about to read 5, iclass 21, count 0 2006.225.08:19:10.62#ibcon#read 5, iclass 21, count 0 2006.225.08:19:10.62#ibcon#about to read 6, iclass 21, count 0 2006.225.08:19:10.62#ibcon#read 6, iclass 21, count 0 2006.225.08:19:10.62#ibcon#end of sib2, iclass 21, count 0 2006.225.08:19:10.62#ibcon#*after write, iclass 21, count 0 2006.225.08:19:10.62#ibcon#*before return 0, iclass 21, count 0 2006.225.08:19:10.62#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:19:10.62#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 0 2006.225.08:19:10.62#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:19:10.62#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:19:10.62$vc4f8/vb=1,4 2006.225.08:19:10.62#ibcon#iclass 23 nclrec 2 cls_cnt 3 2006.225.08:19:10.62#ibcon#iclass 23 iclrec 1 cls_cnt 3 2006.225.08:19:10.62#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:10.62#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:19:10.62#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:19:10.62#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:19:10.62#ibcon#enter wrdev, iclass 23, count 2 2006.225.08:19:10.62#ibcon#first serial, iclass 23, count 2 2006.225.08:19:10.62#ibcon#enter sib2, iclass 23, count 2 2006.225.08:19:10.62#ibcon#flushed, iclass 23, count 2 2006.225.08:19:10.62#ibcon#about to write, iclass 23, count 2 2006.225.08:19:10.62#ibcon#wrote, iclass 23, count 2 2006.225.08:19:10.62#ibcon#about to read 3, iclass 23, count 2 2006.225.08:19:10.64#ibcon#read 3, iclass 23, count 2 2006.225.08:19:10.64#ibcon#about to read 4, iclass 23, count 2 2006.225.08:19:10.64#ibcon#read 4, iclass 23, count 2 2006.225.08:19:10.64#ibcon#about to read 5, iclass 23, count 2 2006.225.08:19:10.64#ibcon#read 5, iclass 23, count 2 2006.225.08:19:10.64#ibcon#about to read 6, iclass 23, count 2 2006.225.08:19:10.64#ibcon#read 6, iclass 23, count 2 2006.225.08:19:10.64#ibcon#end of sib2, iclass 23, count 2 2006.225.08:19:10.64#ibcon#*mode == 0, iclass 23, count 2 2006.225.08:19:10.64#ibcon#*mode == 0 && serial, iclass 23, count 2 2006.225.08:19:10.64#ibcon#[27=AT01-04\r\n] 2006.225.08:19:10.64#ibcon#*before write, iclass 23, count 2 2006.225.08:19:10.64#ibcon#enter sib2, iclass 23, count 2 2006.225.08:19:10.64#ibcon#flushed, iclass 23, count 2 2006.225.08:19:10.64#ibcon#about to write, iclass 23, count 2 2006.225.08:19:10.64#ibcon#wrote, iclass 23, count 2 2006.225.08:19:10.64#ibcon#about to read 3, iclass 23, count 2 2006.225.08:19:10.67#ibcon#read 3, iclass 23, count 2 2006.225.08:19:10.67#ibcon#about to read 4, iclass 23, count 2 2006.225.08:19:10.67#ibcon#read 4, iclass 23, count 2 2006.225.08:19:10.67#ibcon#about to read 5, iclass 23, count 2 2006.225.08:19:10.67#ibcon#read 5, iclass 23, count 2 2006.225.08:19:10.67#ibcon#about to read 6, iclass 23, count 2 2006.225.08:19:10.67#ibcon#read 6, iclass 23, count 2 2006.225.08:19:10.67#ibcon#end of sib2, iclass 23, count 2 2006.225.08:19:10.67#ibcon#*after write, iclass 23, count 2 2006.225.08:19:10.67#ibcon#*before return 0, iclass 23, count 2 2006.225.08:19:10.67#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:19:10.67#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 2 2006.225.08:19:10.67#ibcon#iclass 23 iclrec 2 cls_cnt 2 2006.225.08:19:10.67#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:10.67#ibcon#before find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:19:10.79#ibcon#after find_delay mode 2, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:19:10.79#ibcon#before mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:19:10.79#ibcon#enter wrdev, iclass 23, count 0 2006.225.08:19:10.79#ibcon#first serial, iclass 23, count 0 2006.225.08:19:10.79#ibcon#enter sib2, iclass 23, count 0 2006.225.08:19:10.79#ibcon#flushed, iclass 23, count 0 2006.225.08:19:10.79#ibcon#about to write, iclass 23, count 0 2006.225.08:19:10.79#ibcon#wrote, iclass 23, count 0 2006.225.08:19:10.79#ibcon#about to read 3, iclass 23, count 0 2006.225.08:19:10.81#ibcon#read 3, iclass 23, count 0 2006.225.08:19:10.81#ibcon#about to read 4, iclass 23, count 0 2006.225.08:19:10.81#ibcon#read 4, iclass 23, count 0 2006.225.08:19:10.81#ibcon#about to read 5, iclass 23, count 0 2006.225.08:19:10.81#ibcon#read 5, iclass 23, count 0 2006.225.08:19:10.81#ibcon#about to read 6, iclass 23, count 0 2006.225.08:19:10.81#ibcon#read 6, iclass 23, count 0 2006.225.08:19:10.81#ibcon#end of sib2, iclass 23, count 0 2006.225.08:19:10.81#ibcon#*mode == 0, iclass 23, count 0 2006.225.08:19:10.81#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.08:19:10.81#ibcon#[27=USB\r\n] 2006.225.08:19:10.81#ibcon#*before write, iclass 23, count 0 2006.225.08:19:10.81#ibcon#enter sib2, iclass 23, count 0 2006.225.08:19:10.81#ibcon#flushed, iclass 23, count 0 2006.225.08:19:10.81#ibcon#about to write, iclass 23, count 0 2006.225.08:19:10.81#ibcon#wrote, iclass 23, count 0 2006.225.08:19:10.81#ibcon#about to read 3, iclass 23, count 0 2006.225.08:19:10.84#ibcon#read 3, iclass 23, count 0 2006.225.08:19:10.84#ibcon#about to read 4, iclass 23, count 0 2006.225.08:19:10.84#ibcon#read 4, iclass 23, count 0 2006.225.08:19:10.84#ibcon#about to read 5, iclass 23, count 0 2006.225.08:19:10.84#ibcon#read 5, iclass 23, count 0 2006.225.08:19:10.84#ibcon#about to read 6, iclass 23, count 0 2006.225.08:19:10.84#ibcon#read 6, iclass 23, count 0 2006.225.08:19:10.84#ibcon#end of sib2, iclass 23, count 0 2006.225.08:19:10.84#ibcon#*after write, iclass 23, count 0 2006.225.08:19:10.84#ibcon#*before return 0, iclass 23, count 0 2006.225.08:19:10.84#ibcon#after mode 2 write, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:19:10.84#ibcon#end of loop, iclass 23 iclrec 2 cls_cnt 0 2006.225.08:19:10.84#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.08:19:10.84#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.08:19:10.84$vc4f8/vblo=2,640.99 2006.225.08:19:10.84#ibcon#iclass 25 nclrec 1 cls_cnt 2 2006.225.08:19:10.84#ibcon#iclass 25 iclrec 1 cls_cnt 2 2006.225.08:19:10.84#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:10.84#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:19:10.84#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:19:10.84#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:19:10.84#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:19:10.84#ibcon#first serial, iclass 25, count 0 2006.225.08:19:10.84#ibcon#enter sib2, iclass 25, count 0 2006.225.08:19:10.84#ibcon#flushed, iclass 25, count 0 2006.225.08:19:10.84#ibcon#about to write, iclass 25, count 0 2006.225.08:19:10.84#ibcon#wrote, iclass 25, count 0 2006.225.08:19:10.84#ibcon#about to read 3, iclass 25, count 0 2006.225.08:19:10.86#ibcon#read 3, iclass 25, count 0 2006.225.08:19:10.86#ibcon#about to read 4, iclass 25, count 0 2006.225.08:19:10.86#ibcon#read 4, iclass 25, count 0 2006.225.08:19:10.86#ibcon#about to read 5, iclass 25, count 0 2006.225.08:19:10.86#ibcon#read 5, iclass 25, count 0 2006.225.08:19:10.86#ibcon#about to read 6, iclass 25, count 0 2006.225.08:19:10.86#ibcon#read 6, iclass 25, count 0 2006.225.08:19:10.86#ibcon#end of sib2, iclass 25, count 0 2006.225.08:19:10.86#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:19:10.86#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:19:10.86#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:19:10.86#ibcon#*before write, iclass 25, count 0 2006.225.08:19:10.86#ibcon#enter sib2, iclass 25, count 0 2006.225.08:19:10.86#ibcon#flushed, iclass 25, count 0 2006.225.08:19:10.86#ibcon#about to write, iclass 25, count 0 2006.225.08:19:10.86#ibcon#wrote, iclass 25, count 0 2006.225.08:19:10.86#ibcon#about to read 3, iclass 25, count 0 2006.225.08:19:10.90#ibcon#read 3, iclass 25, count 0 2006.225.08:19:10.90#ibcon#about to read 4, iclass 25, count 0 2006.225.08:19:10.90#ibcon#read 4, iclass 25, count 0 2006.225.08:19:10.90#ibcon#about to read 5, iclass 25, count 0 2006.225.08:19:10.90#ibcon#read 5, iclass 25, count 0 2006.225.08:19:10.90#ibcon#about to read 6, iclass 25, count 0 2006.225.08:19:10.90#ibcon#read 6, iclass 25, count 0 2006.225.08:19:10.90#ibcon#end of sib2, iclass 25, count 0 2006.225.08:19:10.90#ibcon#*after write, iclass 25, count 0 2006.225.08:19:10.90#ibcon#*before return 0, iclass 25, count 0 2006.225.08:19:10.90#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:19:10.90#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 0 2006.225.08:19:10.90#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:19:10.90#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:19:10.90$vc4f8/vb=2,4 2006.225.08:19:10.90#ibcon#iclass 27 nclrec 2 cls_cnt 3 2006.225.08:19:10.90#ibcon#iclass 27 iclrec 1 cls_cnt 3 2006.225.08:19:10.90#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:10.90#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:19:10.96#abcon#<5=/04 2.2 4.6 28.09 741003.3\r\n> 2006.225.08:19:10.96#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:19:10.96#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:19:10.96#ibcon#enter wrdev, iclass 27, count 2 2006.225.08:19:10.96#ibcon#first serial, iclass 27, count 2 2006.225.08:19:10.96#ibcon#enter sib2, iclass 27, count 2 2006.225.08:19:10.96#ibcon#flushed, iclass 27, count 2 2006.225.08:19:10.96#ibcon#about to write, iclass 27, count 2 2006.225.08:19:10.96#ibcon#wrote, iclass 27, count 2 2006.225.08:19:10.96#ibcon#about to read 3, iclass 27, count 2 2006.225.08:19:10.98#ibcon#read 3, iclass 27, count 2 2006.225.08:19:10.98#ibcon#about to read 4, iclass 27, count 2 2006.225.08:19:10.98#ibcon#read 4, iclass 27, count 2 2006.225.08:19:10.98#ibcon#about to read 5, iclass 27, count 2 2006.225.08:19:10.98#ibcon#read 5, iclass 27, count 2 2006.225.08:19:10.98#ibcon#about to read 6, iclass 27, count 2 2006.225.08:19:10.98#ibcon#read 6, iclass 27, count 2 2006.225.08:19:10.98#ibcon#end of sib2, iclass 27, count 2 2006.225.08:19:10.98#ibcon#*mode == 0, iclass 27, count 2 2006.225.08:19:10.98#ibcon#*mode == 0 && serial, iclass 27, count 2 2006.225.08:19:10.98#ibcon#[27=AT02-04\r\n] 2006.225.08:19:10.98#ibcon#*before write, iclass 27, count 2 2006.225.08:19:10.98#ibcon#enter sib2, iclass 27, count 2 2006.225.08:19:10.98#ibcon#flushed, iclass 27, count 2 2006.225.08:19:10.98#ibcon#about to write, iclass 27, count 2 2006.225.08:19:10.98#ibcon#wrote, iclass 27, count 2 2006.225.08:19:10.98#ibcon#about to read 3, iclass 27, count 2 2006.225.08:19:10.98#abcon#{5=INTERFACE CLEAR} 2006.225.08:19:11.01#ibcon#read 3, iclass 27, count 2 2006.225.08:19:11.01#ibcon#about to read 4, iclass 27, count 2 2006.225.08:19:11.01#ibcon#read 4, iclass 27, count 2 2006.225.08:19:11.01#ibcon#about to read 5, iclass 27, count 2 2006.225.08:19:11.01#ibcon#read 5, iclass 27, count 2 2006.225.08:19:11.01#ibcon#about to read 6, iclass 27, count 2 2006.225.08:19:11.01#ibcon#read 6, iclass 27, count 2 2006.225.08:19:11.01#ibcon#end of sib2, iclass 27, count 2 2006.225.08:19:11.01#ibcon#*after write, iclass 27, count 2 2006.225.08:19:11.01#ibcon#*before return 0, iclass 27, count 2 2006.225.08:19:11.01#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:19:11.01#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 2 2006.225.08:19:11.01#ibcon#iclass 27 iclrec 2 cls_cnt 2 2006.225.08:19:11.01#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:11.01#ibcon#before find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:19:11.04#abcon#[5=S1D000X0/0*\r\n] 2006.225.08:19:11.13#ibcon#after find_delay mode 2, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:19:11.13#ibcon#before mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:19:11.13#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:19:11.13#ibcon#first serial, iclass 27, count 0 2006.225.08:19:11.13#ibcon#enter sib2, iclass 27, count 0 2006.225.08:19:11.13#ibcon#flushed, iclass 27, count 0 2006.225.08:19:11.13#ibcon#about to write, iclass 27, count 0 2006.225.08:19:11.13#ibcon#wrote, iclass 27, count 0 2006.225.08:19:11.13#ibcon#about to read 3, iclass 27, count 0 2006.225.08:19:11.15#ibcon#read 3, iclass 27, count 0 2006.225.08:19:11.15#ibcon#about to read 4, iclass 27, count 0 2006.225.08:19:11.15#ibcon#read 4, iclass 27, count 0 2006.225.08:19:11.15#ibcon#about to read 5, iclass 27, count 0 2006.225.08:19:11.15#ibcon#read 5, iclass 27, count 0 2006.225.08:19:11.15#ibcon#about to read 6, iclass 27, count 0 2006.225.08:19:11.15#ibcon#read 6, iclass 27, count 0 2006.225.08:19:11.15#ibcon#end of sib2, iclass 27, count 0 2006.225.08:19:11.15#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:19:11.15#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:19:11.15#ibcon#[27=USB\r\n] 2006.225.08:19:11.15#ibcon#*before write, iclass 27, count 0 2006.225.08:19:11.15#ibcon#enter sib2, iclass 27, count 0 2006.225.08:19:11.15#ibcon#flushed, iclass 27, count 0 2006.225.08:19:11.15#ibcon#about to write, iclass 27, count 0 2006.225.08:19:11.15#ibcon#wrote, iclass 27, count 0 2006.225.08:19:11.15#ibcon#about to read 3, iclass 27, count 0 2006.225.08:19:11.18#ibcon#read 3, iclass 27, count 0 2006.225.08:19:11.18#ibcon#about to read 4, iclass 27, count 0 2006.225.08:19:11.18#ibcon#read 4, iclass 27, count 0 2006.225.08:19:11.18#ibcon#about to read 5, iclass 27, count 0 2006.225.08:19:11.18#ibcon#read 5, iclass 27, count 0 2006.225.08:19:11.18#ibcon#about to read 6, iclass 27, count 0 2006.225.08:19:11.18#ibcon#read 6, iclass 27, count 0 2006.225.08:19:11.18#ibcon#end of sib2, iclass 27, count 0 2006.225.08:19:11.18#ibcon#*after write, iclass 27, count 0 2006.225.08:19:11.18#ibcon#*before return 0, iclass 27, count 0 2006.225.08:19:11.18#ibcon#after mode 2 write, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:19:11.18#ibcon#end of loop, iclass 27 iclrec 2 cls_cnt 0 2006.225.08:19:11.18#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:19:11.18#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:19:11.18$vc4f8/vblo=3,656.99 2006.225.08:19:11.18#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.08:19:11.18#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.08:19:11.18#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:11.18#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:19:11.18#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:19:11.18#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:19:11.18#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:19:11.18#ibcon#first serial, iclass 33, count 0 2006.225.08:19:11.18#ibcon#enter sib2, iclass 33, count 0 2006.225.08:19:11.18#ibcon#flushed, iclass 33, count 0 2006.225.08:19:11.18#ibcon#about to write, iclass 33, count 0 2006.225.08:19:11.18#ibcon#wrote, iclass 33, count 0 2006.225.08:19:11.18#ibcon#about to read 3, iclass 33, count 0 2006.225.08:19:11.20#ibcon#read 3, iclass 33, count 0 2006.225.08:19:11.20#ibcon#about to read 4, iclass 33, count 0 2006.225.08:19:11.20#ibcon#read 4, iclass 33, count 0 2006.225.08:19:11.20#ibcon#about to read 5, iclass 33, count 0 2006.225.08:19:11.20#ibcon#read 5, iclass 33, count 0 2006.225.08:19:11.20#ibcon#about to read 6, iclass 33, count 0 2006.225.08:19:11.20#ibcon#read 6, iclass 33, count 0 2006.225.08:19:11.20#ibcon#end of sib2, iclass 33, count 0 2006.225.08:19:11.20#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:19:11.20#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:19:11.20#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:19:11.20#ibcon#*before write, iclass 33, count 0 2006.225.08:19:11.20#ibcon#enter sib2, iclass 33, count 0 2006.225.08:19:11.20#ibcon#flushed, iclass 33, count 0 2006.225.08:19:11.20#ibcon#about to write, iclass 33, count 0 2006.225.08:19:11.20#ibcon#wrote, iclass 33, count 0 2006.225.08:19:11.20#ibcon#about to read 3, iclass 33, count 0 2006.225.08:19:11.24#ibcon#read 3, iclass 33, count 0 2006.225.08:19:11.24#ibcon#about to read 4, iclass 33, count 0 2006.225.08:19:11.24#ibcon#read 4, iclass 33, count 0 2006.225.08:19:11.24#ibcon#about to read 5, iclass 33, count 0 2006.225.08:19:11.24#ibcon#read 5, iclass 33, count 0 2006.225.08:19:11.24#ibcon#about to read 6, iclass 33, count 0 2006.225.08:19:11.24#ibcon#read 6, iclass 33, count 0 2006.225.08:19:11.24#ibcon#end of sib2, iclass 33, count 0 2006.225.08:19:11.24#ibcon#*after write, iclass 33, count 0 2006.225.08:19:11.24#ibcon#*before return 0, iclass 33, count 0 2006.225.08:19:11.24#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:19:11.24#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:19:11.24#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:19:11.24#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:19:11.24$vc4f8/vb=3,4 2006.225.08:19:11.24#ibcon#iclass 35 nclrec 2 cls_cnt 3 2006.225.08:19:11.24#ibcon#iclass 35 iclrec 1 cls_cnt 3 2006.225.08:19:11.24#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:11.24#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:19:11.30#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:19:11.30#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:19:11.30#ibcon#enter wrdev, iclass 35, count 2 2006.225.08:19:11.30#ibcon#first serial, iclass 35, count 2 2006.225.08:19:11.30#ibcon#enter sib2, iclass 35, count 2 2006.225.08:19:11.30#ibcon#flushed, iclass 35, count 2 2006.225.08:19:11.30#ibcon#about to write, iclass 35, count 2 2006.225.08:19:11.30#ibcon#wrote, iclass 35, count 2 2006.225.08:19:11.30#ibcon#about to read 3, iclass 35, count 2 2006.225.08:19:11.32#ibcon#read 3, iclass 35, count 2 2006.225.08:19:11.32#ibcon#about to read 4, iclass 35, count 2 2006.225.08:19:11.32#ibcon#read 4, iclass 35, count 2 2006.225.08:19:11.32#ibcon#about to read 5, iclass 35, count 2 2006.225.08:19:11.32#ibcon#read 5, iclass 35, count 2 2006.225.08:19:11.32#ibcon#about to read 6, iclass 35, count 2 2006.225.08:19:11.32#ibcon#read 6, iclass 35, count 2 2006.225.08:19:11.32#ibcon#end of sib2, iclass 35, count 2 2006.225.08:19:11.32#ibcon#*mode == 0, iclass 35, count 2 2006.225.08:19:11.32#ibcon#*mode == 0 && serial, iclass 35, count 2 2006.225.08:19:11.32#ibcon#[27=AT03-04\r\n] 2006.225.08:19:11.32#ibcon#*before write, iclass 35, count 2 2006.225.08:19:11.32#ibcon#enter sib2, iclass 35, count 2 2006.225.08:19:11.32#ibcon#flushed, iclass 35, count 2 2006.225.08:19:11.32#ibcon#about to write, iclass 35, count 2 2006.225.08:19:11.32#ibcon#wrote, iclass 35, count 2 2006.225.08:19:11.32#ibcon#about to read 3, iclass 35, count 2 2006.225.08:19:11.35#ibcon#read 3, iclass 35, count 2 2006.225.08:19:11.35#ibcon#about to read 4, iclass 35, count 2 2006.225.08:19:11.35#ibcon#read 4, iclass 35, count 2 2006.225.08:19:11.35#ibcon#about to read 5, iclass 35, count 2 2006.225.08:19:11.35#ibcon#read 5, iclass 35, count 2 2006.225.08:19:11.35#ibcon#about to read 6, iclass 35, count 2 2006.225.08:19:11.35#ibcon#read 6, iclass 35, count 2 2006.225.08:19:11.35#ibcon#end of sib2, iclass 35, count 2 2006.225.08:19:11.35#ibcon#*after write, iclass 35, count 2 2006.225.08:19:11.35#ibcon#*before return 0, iclass 35, count 2 2006.225.08:19:11.35#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:19:11.35#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 2 2006.225.08:19:11.35#ibcon#iclass 35 iclrec 2 cls_cnt 2 2006.225.08:19:11.35#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:11.35#ibcon#before find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:19:11.47#ibcon#after find_delay mode 2, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:19:11.47#ibcon#before mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:19:11.47#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:19:11.47#ibcon#first serial, iclass 35, count 0 2006.225.08:19:11.47#ibcon#enter sib2, iclass 35, count 0 2006.225.08:19:11.47#ibcon#flushed, iclass 35, count 0 2006.225.08:19:11.47#ibcon#about to write, iclass 35, count 0 2006.225.08:19:11.47#ibcon#wrote, iclass 35, count 0 2006.225.08:19:11.47#ibcon#about to read 3, iclass 35, count 0 2006.225.08:19:11.49#ibcon#read 3, iclass 35, count 0 2006.225.08:19:11.49#ibcon#about to read 4, iclass 35, count 0 2006.225.08:19:11.49#ibcon#read 4, iclass 35, count 0 2006.225.08:19:11.49#ibcon#about to read 5, iclass 35, count 0 2006.225.08:19:11.49#ibcon#read 5, iclass 35, count 0 2006.225.08:19:11.49#ibcon#about to read 6, iclass 35, count 0 2006.225.08:19:11.49#ibcon#read 6, iclass 35, count 0 2006.225.08:19:11.49#ibcon#end of sib2, iclass 35, count 0 2006.225.08:19:11.49#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:19:11.49#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:19:11.49#ibcon#[27=USB\r\n] 2006.225.08:19:11.49#ibcon#*before write, iclass 35, count 0 2006.225.08:19:11.49#ibcon#enter sib2, iclass 35, count 0 2006.225.08:19:11.49#ibcon#flushed, iclass 35, count 0 2006.225.08:19:11.49#ibcon#about to write, iclass 35, count 0 2006.225.08:19:11.49#ibcon#wrote, iclass 35, count 0 2006.225.08:19:11.49#ibcon#about to read 3, iclass 35, count 0 2006.225.08:19:11.52#ibcon#read 3, iclass 35, count 0 2006.225.08:19:11.52#ibcon#about to read 4, iclass 35, count 0 2006.225.08:19:11.52#ibcon#read 4, iclass 35, count 0 2006.225.08:19:11.52#ibcon#about to read 5, iclass 35, count 0 2006.225.08:19:11.52#ibcon#read 5, iclass 35, count 0 2006.225.08:19:11.52#ibcon#about to read 6, iclass 35, count 0 2006.225.08:19:11.52#ibcon#read 6, iclass 35, count 0 2006.225.08:19:11.52#ibcon#end of sib2, iclass 35, count 0 2006.225.08:19:11.52#ibcon#*after write, iclass 35, count 0 2006.225.08:19:11.52#ibcon#*before return 0, iclass 35, count 0 2006.225.08:19:11.52#ibcon#after mode 2 write, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:19:11.52#ibcon#end of loop, iclass 35 iclrec 2 cls_cnt 0 2006.225.08:19:11.52#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:19:11.52#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:19:11.52$vc4f8/vblo=4,712.99 2006.225.08:19:11.52#ibcon#iclass 37 nclrec 1 cls_cnt 2 2006.225.08:19:11.52#ibcon#iclass 37 iclrec 1 cls_cnt 2 2006.225.08:19:11.52#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:11.52#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:19:11.52#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:19:11.52#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:19:11.52#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:19:11.52#ibcon#first serial, iclass 37, count 0 2006.225.08:19:11.52#ibcon#enter sib2, iclass 37, count 0 2006.225.08:19:11.52#ibcon#flushed, iclass 37, count 0 2006.225.08:19:11.52#ibcon#about to write, iclass 37, count 0 2006.225.08:19:11.52#ibcon#wrote, iclass 37, count 0 2006.225.08:19:11.52#ibcon#about to read 3, iclass 37, count 0 2006.225.08:19:11.54#ibcon#read 3, iclass 37, count 0 2006.225.08:19:11.54#ibcon#about to read 4, iclass 37, count 0 2006.225.08:19:11.54#ibcon#read 4, iclass 37, count 0 2006.225.08:19:11.54#ibcon#about to read 5, iclass 37, count 0 2006.225.08:19:11.54#ibcon#read 5, iclass 37, count 0 2006.225.08:19:11.54#ibcon#about to read 6, iclass 37, count 0 2006.225.08:19:11.54#ibcon#read 6, iclass 37, count 0 2006.225.08:19:11.54#ibcon#end of sib2, iclass 37, count 0 2006.225.08:19:11.54#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:19:11.54#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:19:11.54#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:19:11.54#ibcon#*before write, iclass 37, count 0 2006.225.08:19:11.54#ibcon#enter sib2, iclass 37, count 0 2006.225.08:19:11.54#ibcon#flushed, iclass 37, count 0 2006.225.08:19:11.54#ibcon#about to write, iclass 37, count 0 2006.225.08:19:11.54#ibcon#wrote, iclass 37, count 0 2006.225.08:19:11.54#ibcon#about to read 3, iclass 37, count 0 2006.225.08:19:11.58#ibcon#read 3, iclass 37, count 0 2006.225.08:19:11.58#ibcon#about to read 4, iclass 37, count 0 2006.225.08:19:11.58#ibcon#read 4, iclass 37, count 0 2006.225.08:19:11.58#ibcon#about to read 5, iclass 37, count 0 2006.225.08:19:11.58#ibcon#read 5, iclass 37, count 0 2006.225.08:19:11.58#ibcon#about to read 6, iclass 37, count 0 2006.225.08:19:11.58#ibcon#read 6, iclass 37, count 0 2006.225.08:19:11.58#ibcon#end of sib2, iclass 37, count 0 2006.225.08:19:11.58#ibcon#*after write, iclass 37, count 0 2006.225.08:19:11.58#ibcon#*before return 0, iclass 37, count 0 2006.225.08:19:11.58#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:19:11.58#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 0 2006.225.08:19:11.58#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:19:11.58#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:19:11.58$vc4f8/vb=4,4 2006.225.08:19:11.58#ibcon#iclass 39 nclrec 2 cls_cnt 3 2006.225.08:19:11.58#ibcon#iclass 39 iclrec 1 cls_cnt 3 2006.225.08:19:11.58#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:11.58#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:19:11.64#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:19:11.64#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:19:11.64#ibcon#enter wrdev, iclass 39, count 2 2006.225.08:19:11.64#ibcon#first serial, iclass 39, count 2 2006.225.08:19:11.64#ibcon#enter sib2, iclass 39, count 2 2006.225.08:19:11.64#ibcon#flushed, iclass 39, count 2 2006.225.08:19:11.64#ibcon#about to write, iclass 39, count 2 2006.225.08:19:11.64#ibcon#wrote, iclass 39, count 2 2006.225.08:19:11.64#ibcon#about to read 3, iclass 39, count 2 2006.225.08:19:11.66#ibcon#read 3, iclass 39, count 2 2006.225.08:19:11.66#ibcon#about to read 4, iclass 39, count 2 2006.225.08:19:11.66#ibcon#read 4, iclass 39, count 2 2006.225.08:19:11.66#ibcon#about to read 5, iclass 39, count 2 2006.225.08:19:11.66#ibcon#read 5, iclass 39, count 2 2006.225.08:19:11.66#ibcon#about to read 6, iclass 39, count 2 2006.225.08:19:11.66#ibcon#read 6, iclass 39, count 2 2006.225.08:19:11.66#ibcon#end of sib2, iclass 39, count 2 2006.225.08:19:11.66#ibcon#*mode == 0, iclass 39, count 2 2006.225.08:19:11.66#ibcon#*mode == 0 && serial, iclass 39, count 2 2006.225.08:19:11.66#ibcon#[27=AT04-04\r\n] 2006.225.08:19:11.66#ibcon#*before write, iclass 39, count 2 2006.225.08:19:11.66#ibcon#enter sib2, iclass 39, count 2 2006.225.08:19:11.66#ibcon#flushed, iclass 39, count 2 2006.225.08:19:11.66#ibcon#about to write, iclass 39, count 2 2006.225.08:19:11.66#ibcon#wrote, iclass 39, count 2 2006.225.08:19:11.66#ibcon#about to read 3, iclass 39, count 2 2006.225.08:19:11.69#ibcon#read 3, iclass 39, count 2 2006.225.08:19:11.69#ibcon#about to read 4, iclass 39, count 2 2006.225.08:19:11.69#ibcon#read 4, iclass 39, count 2 2006.225.08:19:11.69#ibcon#about to read 5, iclass 39, count 2 2006.225.08:19:11.69#ibcon#read 5, iclass 39, count 2 2006.225.08:19:11.69#ibcon#about to read 6, iclass 39, count 2 2006.225.08:19:11.69#ibcon#read 6, iclass 39, count 2 2006.225.08:19:11.69#ibcon#end of sib2, iclass 39, count 2 2006.225.08:19:11.69#ibcon#*after write, iclass 39, count 2 2006.225.08:19:11.69#ibcon#*before return 0, iclass 39, count 2 2006.225.08:19:11.69#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:19:11.69#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 2 2006.225.08:19:11.69#ibcon#iclass 39 iclrec 2 cls_cnt 2 2006.225.08:19:11.69#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:11.69#ibcon#before find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:19:11.81#ibcon#after find_delay mode 2, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:19:11.81#ibcon#before mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:19:11.81#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:19:11.81#ibcon#first serial, iclass 39, count 0 2006.225.08:19:11.81#ibcon#enter sib2, iclass 39, count 0 2006.225.08:19:11.81#ibcon#flushed, iclass 39, count 0 2006.225.08:19:11.81#ibcon#about to write, iclass 39, count 0 2006.225.08:19:11.81#ibcon#wrote, iclass 39, count 0 2006.225.08:19:11.81#ibcon#about to read 3, iclass 39, count 0 2006.225.08:19:11.83#ibcon#read 3, iclass 39, count 0 2006.225.08:19:11.83#ibcon#about to read 4, iclass 39, count 0 2006.225.08:19:11.83#ibcon#read 4, iclass 39, count 0 2006.225.08:19:11.83#ibcon#about to read 5, iclass 39, count 0 2006.225.08:19:11.83#ibcon#read 5, iclass 39, count 0 2006.225.08:19:11.83#ibcon#about to read 6, iclass 39, count 0 2006.225.08:19:11.83#ibcon#read 6, iclass 39, count 0 2006.225.08:19:11.83#ibcon#end of sib2, iclass 39, count 0 2006.225.08:19:11.83#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:19:11.83#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:19:11.83#ibcon#[27=USB\r\n] 2006.225.08:19:11.83#ibcon#*before write, iclass 39, count 0 2006.225.08:19:11.83#ibcon#enter sib2, iclass 39, count 0 2006.225.08:19:11.83#ibcon#flushed, iclass 39, count 0 2006.225.08:19:11.83#ibcon#about to write, iclass 39, count 0 2006.225.08:19:11.83#ibcon#wrote, iclass 39, count 0 2006.225.08:19:11.83#ibcon#about to read 3, iclass 39, count 0 2006.225.08:19:11.86#ibcon#read 3, iclass 39, count 0 2006.225.08:19:11.86#ibcon#about to read 4, iclass 39, count 0 2006.225.08:19:11.86#ibcon#read 4, iclass 39, count 0 2006.225.08:19:11.86#ibcon#about to read 5, iclass 39, count 0 2006.225.08:19:11.86#ibcon#read 5, iclass 39, count 0 2006.225.08:19:11.86#ibcon#about to read 6, iclass 39, count 0 2006.225.08:19:11.86#ibcon#read 6, iclass 39, count 0 2006.225.08:19:11.86#ibcon#end of sib2, iclass 39, count 0 2006.225.08:19:11.86#ibcon#*after write, iclass 39, count 0 2006.225.08:19:11.86#ibcon#*before return 0, iclass 39, count 0 2006.225.08:19:11.86#ibcon#after mode 2 write, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:19:11.86#ibcon#end of loop, iclass 39 iclrec 2 cls_cnt 0 2006.225.08:19:11.86#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:19:11.86#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:19:11.86$vc4f8/vblo=5,744.99 2006.225.08:19:11.86#ibcon#iclass 3 nclrec 1 cls_cnt 2 2006.225.08:19:11.86#ibcon#iclass 3 iclrec 1 cls_cnt 2 2006.225.08:19:11.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:11.86#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:19:11.86#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:19:11.86#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:19:11.86#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:19:11.86#ibcon#first serial, iclass 3, count 0 2006.225.08:19:11.86#ibcon#enter sib2, iclass 3, count 0 2006.225.08:19:11.86#ibcon#flushed, iclass 3, count 0 2006.225.08:19:11.86#ibcon#about to write, iclass 3, count 0 2006.225.08:19:11.86#ibcon#wrote, iclass 3, count 0 2006.225.08:19:11.86#ibcon#about to read 3, iclass 3, count 0 2006.225.08:19:11.88#ibcon#read 3, iclass 3, count 0 2006.225.08:19:11.88#ibcon#about to read 4, iclass 3, count 0 2006.225.08:19:11.88#ibcon#read 4, iclass 3, count 0 2006.225.08:19:11.88#ibcon#about to read 5, iclass 3, count 0 2006.225.08:19:11.88#ibcon#read 5, iclass 3, count 0 2006.225.08:19:11.88#ibcon#about to read 6, iclass 3, count 0 2006.225.08:19:11.88#ibcon#read 6, iclass 3, count 0 2006.225.08:19:11.88#ibcon#end of sib2, iclass 3, count 0 2006.225.08:19:11.88#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:19:11.88#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:19:11.88#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:19:11.88#ibcon#*before write, iclass 3, count 0 2006.225.08:19:11.88#ibcon#enter sib2, iclass 3, count 0 2006.225.08:19:11.88#ibcon#flushed, iclass 3, count 0 2006.225.08:19:11.88#ibcon#about to write, iclass 3, count 0 2006.225.08:19:11.88#ibcon#wrote, iclass 3, count 0 2006.225.08:19:11.88#ibcon#about to read 3, iclass 3, count 0 2006.225.08:19:11.92#ibcon#read 3, iclass 3, count 0 2006.225.08:19:11.92#ibcon#about to read 4, iclass 3, count 0 2006.225.08:19:11.92#ibcon#read 4, iclass 3, count 0 2006.225.08:19:11.92#ibcon#about to read 5, iclass 3, count 0 2006.225.08:19:11.92#ibcon#read 5, iclass 3, count 0 2006.225.08:19:11.92#ibcon#about to read 6, iclass 3, count 0 2006.225.08:19:11.92#ibcon#read 6, iclass 3, count 0 2006.225.08:19:11.92#ibcon#end of sib2, iclass 3, count 0 2006.225.08:19:11.92#ibcon#*after write, iclass 3, count 0 2006.225.08:19:11.92#ibcon#*before return 0, iclass 3, count 0 2006.225.08:19:11.92#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:19:11.92#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 0 2006.225.08:19:11.92#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:19:11.92#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:19:11.92$vc4f8/vb=5,4 2006.225.08:19:11.92#ibcon#iclass 5 nclrec 2 cls_cnt 3 2006.225.08:19:11.92#ibcon#iclass 5 iclrec 1 cls_cnt 3 2006.225.08:19:11.92#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:11.92#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:19:11.98#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:19:11.98#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:19:11.98#ibcon#enter wrdev, iclass 5, count 2 2006.225.08:19:11.98#ibcon#first serial, iclass 5, count 2 2006.225.08:19:11.98#ibcon#enter sib2, iclass 5, count 2 2006.225.08:19:11.98#ibcon#flushed, iclass 5, count 2 2006.225.08:19:11.98#ibcon#about to write, iclass 5, count 2 2006.225.08:19:11.98#ibcon#wrote, iclass 5, count 2 2006.225.08:19:11.98#ibcon#about to read 3, iclass 5, count 2 2006.225.08:19:12.00#ibcon#read 3, iclass 5, count 2 2006.225.08:19:12.00#ibcon#about to read 4, iclass 5, count 2 2006.225.08:19:12.00#ibcon#read 4, iclass 5, count 2 2006.225.08:19:12.00#ibcon#about to read 5, iclass 5, count 2 2006.225.08:19:12.00#ibcon#read 5, iclass 5, count 2 2006.225.08:19:12.00#ibcon#about to read 6, iclass 5, count 2 2006.225.08:19:12.00#ibcon#read 6, iclass 5, count 2 2006.225.08:19:12.00#ibcon#end of sib2, iclass 5, count 2 2006.225.08:19:12.00#ibcon#*mode == 0, iclass 5, count 2 2006.225.08:19:12.00#ibcon#*mode == 0 && serial, iclass 5, count 2 2006.225.08:19:12.00#ibcon#[27=AT05-04\r\n] 2006.225.08:19:12.00#ibcon#*before write, iclass 5, count 2 2006.225.08:19:12.00#ibcon#enter sib2, iclass 5, count 2 2006.225.08:19:12.00#ibcon#flushed, iclass 5, count 2 2006.225.08:19:12.00#ibcon#about to write, iclass 5, count 2 2006.225.08:19:12.00#ibcon#wrote, iclass 5, count 2 2006.225.08:19:12.00#ibcon#about to read 3, iclass 5, count 2 2006.225.08:19:12.03#ibcon#read 3, iclass 5, count 2 2006.225.08:19:12.03#ibcon#about to read 4, iclass 5, count 2 2006.225.08:19:12.03#ibcon#read 4, iclass 5, count 2 2006.225.08:19:12.03#ibcon#about to read 5, iclass 5, count 2 2006.225.08:19:12.03#ibcon#read 5, iclass 5, count 2 2006.225.08:19:12.03#ibcon#about to read 6, iclass 5, count 2 2006.225.08:19:12.03#ibcon#read 6, iclass 5, count 2 2006.225.08:19:12.03#ibcon#end of sib2, iclass 5, count 2 2006.225.08:19:12.03#ibcon#*after write, iclass 5, count 2 2006.225.08:19:12.03#ibcon#*before return 0, iclass 5, count 2 2006.225.08:19:12.03#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:19:12.03#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 2 2006.225.08:19:12.03#ibcon#iclass 5 iclrec 2 cls_cnt 2 2006.225.08:19:12.03#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:12.03#ibcon#before find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:19:12.15#ibcon#after find_delay mode 2, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:19:12.15#ibcon#before mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:19:12.15#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:19:12.15#ibcon#first serial, iclass 5, count 0 2006.225.08:19:12.15#ibcon#enter sib2, iclass 5, count 0 2006.225.08:19:12.15#ibcon#flushed, iclass 5, count 0 2006.225.08:19:12.15#ibcon#about to write, iclass 5, count 0 2006.225.08:19:12.15#ibcon#wrote, iclass 5, count 0 2006.225.08:19:12.15#ibcon#about to read 3, iclass 5, count 0 2006.225.08:19:12.17#ibcon#read 3, iclass 5, count 0 2006.225.08:19:12.17#ibcon#about to read 4, iclass 5, count 0 2006.225.08:19:12.17#ibcon#read 4, iclass 5, count 0 2006.225.08:19:12.17#ibcon#about to read 5, iclass 5, count 0 2006.225.08:19:12.17#ibcon#read 5, iclass 5, count 0 2006.225.08:19:12.17#ibcon#about to read 6, iclass 5, count 0 2006.225.08:19:12.17#ibcon#read 6, iclass 5, count 0 2006.225.08:19:12.17#ibcon#end of sib2, iclass 5, count 0 2006.225.08:19:12.17#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:19:12.17#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:19:12.17#ibcon#[27=USB\r\n] 2006.225.08:19:12.17#ibcon#*before write, iclass 5, count 0 2006.225.08:19:12.17#ibcon#enter sib2, iclass 5, count 0 2006.225.08:19:12.17#ibcon#flushed, iclass 5, count 0 2006.225.08:19:12.17#ibcon#about to write, iclass 5, count 0 2006.225.08:19:12.17#ibcon#wrote, iclass 5, count 0 2006.225.08:19:12.17#ibcon#about to read 3, iclass 5, count 0 2006.225.08:19:12.20#ibcon#read 3, iclass 5, count 0 2006.225.08:19:12.20#ibcon#about to read 4, iclass 5, count 0 2006.225.08:19:12.20#ibcon#read 4, iclass 5, count 0 2006.225.08:19:12.20#ibcon#about to read 5, iclass 5, count 0 2006.225.08:19:12.20#ibcon#read 5, iclass 5, count 0 2006.225.08:19:12.20#ibcon#about to read 6, iclass 5, count 0 2006.225.08:19:12.20#ibcon#read 6, iclass 5, count 0 2006.225.08:19:12.20#ibcon#end of sib2, iclass 5, count 0 2006.225.08:19:12.20#ibcon#*after write, iclass 5, count 0 2006.225.08:19:12.20#ibcon#*before return 0, iclass 5, count 0 2006.225.08:19:12.20#ibcon#after mode 2 write, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:19:12.20#ibcon#end of loop, iclass 5 iclrec 2 cls_cnt 0 2006.225.08:19:12.20#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:19:12.20#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:19:12.20$vc4f8/vblo=6,752.99 2006.225.08:19:12.20#ibcon#iclass 7 nclrec 1 cls_cnt 2 2006.225.08:19:12.20#ibcon#iclass 7 iclrec 1 cls_cnt 2 2006.225.08:19:12.20#ibcon#ireg 17 cls_cnt 0 2006.225.08:19:12.20#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:19:12.20#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:19:12.20#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:19:12.20#ibcon#enter wrdev, iclass 7, count 0 2006.225.08:19:12.20#ibcon#first serial, iclass 7, count 0 2006.225.08:19:12.20#ibcon#enter sib2, iclass 7, count 0 2006.225.08:19:12.20#ibcon#flushed, iclass 7, count 0 2006.225.08:19:12.20#ibcon#about to write, iclass 7, count 0 2006.225.08:19:12.20#ibcon#wrote, iclass 7, count 0 2006.225.08:19:12.20#ibcon#about to read 3, iclass 7, count 0 2006.225.08:19:12.22#ibcon#read 3, iclass 7, count 0 2006.225.08:19:12.22#ibcon#about to read 4, iclass 7, count 0 2006.225.08:19:12.22#ibcon#read 4, iclass 7, count 0 2006.225.08:19:12.22#ibcon#about to read 5, iclass 7, count 0 2006.225.08:19:12.22#ibcon#read 5, iclass 7, count 0 2006.225.08:19:12.22#ibcon#about to read 6, iclass 7, count 0 2006.225.08:19:12.22#ibcon#read 6, iclass 7, count 0 2006.225.08:19:12.22#ibcon#end of sib2, iclass 7, count 0 2006.225.08:19:12.22#ibcon#*mode == 0, iclass 7, count 0 2006.225.08:19:12.22#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.08:19:12.22#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:19:12.22#ibcon#*before write, iclass 7, count 0 2006.225.08:19:12.22#ibcon#enter sib2, iclass 7, count 0 2006.225.08:19:12.22#ibcon#flushed, iclass 7, count 0 2006.225.08:19:12.22#ibcon#about to write, iclass 7, count 0 2006.225.08:19:12.22#ibcon#wrote, iclass 7, count 0 2006.225.08:19:12.22#ibcon#about to read 3, iclass 7, count 0 2006.225.08:19:12.26#ibcon#read 3, iclass 7, count 0 2006.225.08:19:12.26#ibcon#about to read 4, iclass 7, count 0 2006.225.08:19:12.26#ibcon#read 4, iclass 7, count 0 2006.225.08:19:12.26#ibcon#about to read 5, iclass 7, count 0 2006.225.08:19:12.26#ibcon#read 5, iclass 7, count 0 2006.225.08:19:12.26#ibcon#about to read 6, iclass 7, count 0 2006.225.08:19:12.26#ibcon#read 6, iclass 7, count 0 2006.225.08:19:12.26#ibcon#end of sib2, iclass 7, count 0 2006.225.08:19:12.26#ibcon#*after write, iclass 7, count 0 2006.225.08:19:12.26#ibcon#*before return 0, iclass 7, count 0 2006.225.08:19:12.26#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:19:12.26#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 0 2006.225.08:19:12.26#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.08:19:12.26#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.08:19:12.26$vc4f8/vb=6,4 2006.225.08:19:12.26#ibcon#iclass 11 nclrec 2 cls_cnt 3 2006.225.08:19:12.26#ibcon#iclass 11 iclrec 1 cls_cnt 3 2006.225.08:19:12.26#ibcon#ireg 11 cls_cnt 2 2006.225.08:19:12.26#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:19:12.32#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:19:12.32#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:19:12.32#ibcon#enter wrdev, iclass 11, count 2 2006.225.08:19:12.32#ibcon#first serial, iclass 11, count 2 2006.225.08:19:12.32#ibcon#enter sib2, iclass 11, count 2 2006.225.08:19:12.32#ibcon#flushed, iclass 11, count 2 2006.225.08:19:12.32#ibcon#about to write, iclass 11, count 2 2006.225.08:19:12.32#ibcon#wrote, iclass 11, count 2 2006.225.08:19:12.32#ibcon#about to read 3, iclass 11, count 2 2006.225.08:19:12.34#ibcon#read 3, iclass 11, count 2 2006.225.08:19:12.34#ibcon#about to read 4, iclass 11, count 2 2006.225.08:19:12.34#ibcon#read 4, iclass 11, count 2 2006.225.08:19:12.34#ibcon#about to read 5, iclass 11, count 2 2006.225.08:19:12.34#ibcon#read 5, iclass 11, count 2 2006.225.08:19:12.34#ibcon#about to read 6, iclass 11, count 2 2006.225.08:19:12.34#ibcon#read 6, iclass 11, count 2 2006.225.08:19:12.34#ibcon#end of sib2, iclass 11, count 2 2006.225.08:19:12.34#ibcon#*mode == 0, iclass 11, count 2 2006.225.08:19:12.34#ibcon#*mode == 0 && serial, iclass 11, count 2 2006.225.08:19:12.34#ibcon#[27=AT06-04\r\n] 2006.225.08:19:12.34#ibcon#*before write, iclass 11, count 2 2006.225.08:19:12.34#ibcon#enter sib2, iclass 11, count 2 2006.225.08:19:12.34#ibcon#flushed, iclass 11, count 2 2006.225.08:19:12.34#ibcon#about to write, iclass 11, count 2 2006.225.08:19:12.34#ibcon#wrote, iclass 11, count 2 2006.225.08:19:12.34#ibcon#about to read 3, iclass 11, count 2 2006.225.08:19:12.37#ibcon#read 3, iclass 11, count 2 2006.225.08:19:12.37#ibcon#about to read 4, iclass 11, count 2 2006.225.08:19:12.37#ibcon#read 4, iclass 11, count 2 2006.225.08:19:12.37#ibcon#about to read 5, iclass 11, count 2 2006.225.08:19:12.37#ibcon#read 5, iclass 11, count 2 2006.225.08:19:12.37#ibcon#about to read 6, iclass 11, count 2 2006.225.08:19:12.37#ibcon#read 6, iclass 11, count 2 2006.225.08:19:12.37#ibcon#end of sib2, iclass 11, count 2 2006.225.08:19:12.37#ibcon#*after write, iclass 11, count 2 2006.225.08:19:12.37#ibcon#*before return 0, iclass 11, count 2 2006.225.08:19:12.37#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:19:12.37#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 2 2006.225.08:19:12.37#ibcon#iclass 11 iclrec 2 cls_cnt 2 2006.225.08:19:12.37#ibcon#ireg 7 cls_cnt 0 2006.225.08:19:12.37#ibcon#before find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:19:12.49#ibcon#after find_delay mode 2, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:19:12.49#ibcon#before mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:19:12.49#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:19:12.49#ibcon#first serial, iclass 11, count 0 2006.225.08:19:12.49#ibcon#enter sib2, iclass 11, count 0 2006.225.08:19:12.49#ibcon#flushed, iclass 11, count 0 2006.225.08:19:12.49#ibcon#about to write, iclass 11, count 0 2006.225.08:19:12.49#ibcon#wrote, iclass 11, count 0 2006.225.08:19:12.49#ibcon#about to read 3, iclass 11, count 0 2006.225.08:19:12.51#ibcon#read 3, iclass 11, count 0 2006.225.08:19:12.51#ibcon#about to read 4, iclass 11, count 0 2006.225.08:19:12.51#ibcon#read 4, iclass 11, count 0 2006.225.08:19:12.51#ibcon#about to read 5, iclass 11, count 0 2006.225.08:19:12.51#ibcon#read 5, iclass 11, count 0 2006.225.08:19:12.51#ibcon#about to read 6, iclass 11, count 0 2006.225.08:19:12.51#ibcon#read 6, iclass 11, count 0 2006.225.08:19:12.51#ibcon#end of sib2, iclass 11, count 0 2006.225.08:19:12.51#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:19:12.51#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:19:12.51#ibcon#[27=USB\r\n] 2006.225.08:19:12.51#ibcon#*before write, iclass 11, count 0 2006.225.08:19:12.51#ibcon#enter sib2, iclass 11, count 0 2006.225.08:19:12.51#ibcon#flushed, iclass 11, count 0 2006.225.08:19:12.51#ibcon#about to write, iclass 11, count 0 2006.225.08:19:12.51#ibcon#wrote, iclass 11, count 0 2006.225.08:19:12.51#ibcon#about to read 3, iclass 11, count 0 2006.225.08:19:12.54#ibcon#read 3, iclass 11, count 0 2006.225.08:19:12.54#ibcon#about to read 4, iclass 11, count 0 2006.225.08:19:12.54#ibcon#read 4, iclass 11, count 0 2006.225.08:19:12.54#ibcon#about to read 5, iclass 11, count 0 2006.225.08:19:12.54#ibcon#read 5, iclass 11, count 0 2006.225.08:19:12.54#ibcon#about to read 6, iclass 11, count 0 2006.225.08:19:12.54#ibcon#read 6, iclass 11, count 0 2006.225.08:19:12.54#ibcon#end of sib2, iclass 11, count 0 2006.225.08:19:12.54#ibcon#*after write, iclass 11, count 0 2006.225.08:19:12.54#ibcon#*before return 0, iclass 11, count 0 2006.225.08:19:12.54#ibcon#after mode 2 write, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:19:12.54#ibcon#end of loop, iclass 11 iclrec 2 cls_cnt 0 2006.225.08:19:12.54#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:19:12.54#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:19:12.54$vc4f8/vabw=wide 2006.225.08:19:12.54#ibcon#iclass 13 nclrec 1 cls_cnt 2 2006.225.08:19:12.54#ibcon#iclass 13 iclrec 1 cls_cnt 2 2006.225.08:19:12.54#ibcon#ireg 8 cls_cnt 0 2006.225.08:19:12.54#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:19:12.54#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:19:12.54#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:19:12.54#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:19:12.54#ibcon#first serial, iclass 13, count 0 2006.225.08:19:12.54#ibcon#enter sib2, iclass 13, count 0 2006.225.08:19:12.54#ibcon#flushed, iclass 13, count 0 2006.225.08:19:12.54#ibcon#about to write, iclass 13, count 0 2006.225.08:19:12.54#ibcon#wrote, iclass 13, count 0 2006.225.08:19:12.54#ibcon#about to read 3, iclass 13, count 0 2006.225.08:19:12.56#ibcon#read 3, iclass 13, count 0 2006.225.08:19:12.56#ibcon#about to read 4, iclass 13, count 0 2006.225.08:19:12.56#ibcon#read 4, iclass 13, count 0 2006.225.08:19:12.56#ibcon#about to read 5, iclass 13, count 0 2006.225.08:19:12.56#ibcon#read 5, iclass 13, count 0 2006.225.08:19:12.56#ibcon#about to read 6, iclass 13, count 0 2006.225.08:19:12.56#ibcon#read 6, iclass 13, count 0 2006.225.08:19:12.56#ibcon#end of sib2, iclass 13, count 0 2006.225.08:19:12.56#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:19:12.56#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:19:12.56#ibcon#[25=BW32\r\n] 2006.225.08:19:12.56#ibcon#*before write, iclass 13, count 0 2006.225.08:19:12.56#ibcon#enter sib2, iclass 13, count 0 2006.225.08:19:12.56#ibcon#flushed, iclass 13, count 0 2006.225.08:19:12.56#ibcon#about to write, iclass 13, count 0 2006.225.08:19:12.56#ibcon#wrote, iclass 13, count 0 2006.225.08:19:12.56#ibcon#about to read 3, iclass 13, count 0 2006.225.08:19:12.59#ibcon#read 3, iclass 13, count 0 2006.225.08:19:12.59#ibcon#about to read 4, iclass 13, count 0 2006.225.08:19:12.59#ibcon#read 4, iclass 13, count 0 2006.225.08:19:12.59#ibcon#about to read 5, iclass 13, count 0 2006.225.08:19:12.59#ibcon#read 5, iclass 13, count 0 2006.225.08:19:12.59#ibcon#about to read 6, iclass 13, count 0 2006.225.08:19:12.59#ibcon#read 6, iclass 13, count 0 2006.225.08:19:12.59#ibcon#end of sib2, iclass 13, count 0 2006.225.08:19:12.59#ibcon#*after write, iclass 13, count 0 2006.225.08:19:12.59#ibcon#*before return 0, iclass 13, count 0 2006.225.08:19:12.59#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:19:12.59#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 0 2006.225.08:19:12.59#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:19:12.59#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:19:12.59$vc4f8/vbbw=wide 2006.225.08:19:12.59#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.08:19:12.59#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.08:19:12.59#ibcon#ireg 8 cls_cnt 0 2006.225.08:19:12.59#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:19:12.66#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:19:12.66#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:19:12.66#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:19:12.66#ibcon#first serial, iclass 15, count 0 2006.225.08:19:12.66#ibcon#enter sib2, iclass 15, count 0 2006.225.08:19:12.66#ibcon#flushed, iclass 15, count 0 2006.225.08:19:12.66#ibcon#about to write, iclass 15, count 0 2006.225.08:19:12.66#ibcon#wrote, iclass 15, count 0 2006.225.08:19:12.66#ibcon#about to read 3, iclass 15, count 0 2006.225.08:19:12.68#ibcon#read 3, iclass 15, count 0 2006.225.08:19:12.68#ibcon#about to read 4, iclass 15, count 0 2006.225.08:19:12.68#ibcon#read 4, iclass 15, count 0 2006.225.08:19:12.68#ibcon#about to read 5, iclass 15, count 0 2006.225.08:19:12.68#ibcon#read 5, iclass 15, count 0 2006.225.08:19:12.68#ibcon#about to read 6, iclass 15, count 0 2006.225.08:19:12.68#ibcon#read 6, iclass 15, count 0 2006.225.08:19:12.68#ibcon#end of sib2, iclass 15, count 0 2006.225.08:19:12.68#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:19:12.68#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:19:12.68#ibcon#[27=BW32\r\n] 2006.225.08:19:12.68#ibcon#*before write, iclass 15, count 0 2006.225.08:19:12.68#ibcon#enter sib2, iclass 15, count 0 2006.225.08:19:12.68#ibcon#flushed, iclass 15, count 0 2006.225.08:19:12.68#ibcon#about to write, iclass 15, count 0 2006.225.08:19:12.68#ibcon#wrote, iclass 15, count 0 2006.225.08:19:12.68#ibcon#about to read 3, iclass 15, count 0 2006.225.08:19:12.71#ibcon#read 3, iclass 15, count 0 2006.225.08:19:12.71#ibcon#about to read 4, iclass 15, count 0 2006.225.08:19:12.71#ibcon#read 4, iclass 15, count 0 2006.225.08:19:12.71#ibcon#about to read 5, iclass 15, count 0 2006.225.08:19:12.71#ibcon#read 5, iclass 15, count 0 2006.225.08:19:12.71#ibcon#about to read 6, iclass 15, count 0 2006.225.08:19:12.71#ibcon#read 6, iclass 15, count 0 2006.225.08:19:12.71#ibcon#end of sib2, iclass 15, count 0 2006.225.08:19:12.71#ibcon#*after write, iclass 15, count 0 2006.225.08:19:12.71#ibcon#*before return 0, iclass 15, count 0 2006.225.08:19:12.71#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:19:12.71#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:19:12.71#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:19:12.71#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:19:12.71$4f8m12a/ifd4f 2006.225.08:19:12.71$ifd4f/lo= 2006.225.08:19:12.71$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:19:12.71$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:19:12.71$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:19:12.71$ifd4f/patch= 2006.225.08:19:12.71$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:19:12.71$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:19:12.71$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:19:12.71$4f8m12a/"form=m,16.000,1:2 2006.225.08:19:12.71$4f8m12a/"tpicd 2006.225.08:19:12.71$4f8m12a/echo=off 2006.225.08:19:12.71$4f8m12a/xlog=off 2006.225.08:19:12.71:!2006.225.08:20:40 2006.225.08:19:38.14#trakl#Source acquired 2006.225.08:19:40.14#flagr#flagr/antenna,acquired 2006.225.08:20:40.00:preob 2006.225.08:20:41.14/onsource/TRACKING 2006.225.08:20:41.14:!2006.225.08:20:50 2006.225.08:20:50.00:data_valid=on 2006.225.08:20:50.00:midob 2006.225.08:20:50.14/onsource/TRACKING 2006.225.08:20:50.14/wx/28.08,1003.3,74 2006.225.08:20:50.35/cable/+6.4043E-03 2006.225.08:20:51.44/va/01,08,usb,yes,29,30 2006.225.08:20:51.44/va/02,07,usb,yes,28,30 2006.225.08:20:51.44/va/03,06,usb,yes,30,31 2006.225.08:20:51.44/va/04,07,usb,yes,30,32 2006.225.08:20:51.44/va/05,07,usb,yes,32,33 2006.225.08:20:51.44/va/06,06,usb,yes,31,31 2006.225.08:20:51.44/va/07,06,usb,yes,31,31 2006.225.08:20:51.44/va/08,07,usb,yes,30,29 2006.225.08:20:51.67/valo/01,532.99,yes,locked 2006.225.08:20:51.67/valo/02,572.99,yes,locked 2006.225.08:20:51.67/valo/03,672.99,yes,locked 2006.225.08:20:51.67/valo/04,832.99,yes,locked 2006.225.08:20:51.67/valo/05,652.99,yes,locked 2006.225.08:20:51.67/valo/06,772.99,yes,locked 2006.225.08:20:51.67/valo/07,832.99,yes,locked 2006.225.08:20:51.67/valo/08,852.99,yes,locked 2006.225.08:20:52.76/vb/01,04,usb,yes,30,29 2006.225.08:20:52.76/vb/02,04,usb,yes,32,33 2006.225.08:20:52.76/vb/03,04,usb,yes,28,32 2006.225.08:20:52.76/vb/04,04,usb,yes,29,29 2006.225.08:20:52.76/vb/05,04,usb,yes,28,32 2006.225.08:20:52.76/vb/06,04,usb,yes,29,32 2006.225.08:20:52.76/vb/07,04,usb,yes,31,31 2006.225.08:20:52.76/vb/08,04,usb,yes,28,32 2006.225.08:20:53.00/vblo/01,632.99,yes,locked 2006.225.08:20:53.00/vblo/02,640.99,yes,locked 2006.225.08:20:53.00/vblo/03,656.99,yes,locked 2006.225.08:20:53.00/vblo/04,712.99,yes,locked 2006.225.08:20:53.00/vblo/05,744.99,yes,locked 2006.225.08:20:53.00/vblo/06,752.99,yes,locked 2006.225.08:20:53.00/vblo/07,734.99,yes,locked 2006.225.08:20:53.00/vblo/08,744.99,yes,locked 2006.225.08:20:53.15/vabw/8 2006.225.08:20:53.30/vbbw/8 2006.225.08:20:53.39/xfe/off,on,15.0 2006.225.08:20:53.76/ifatt/23,28,28,28 2006.225.08:20:54.07/fmout-gps/S +4.56E-07 2006.225.08:20:54.11:!2006.225.08:21:50 2006.225.08:21:50.01:data_valid=off 2006.225.08:21:50.01:postob 2006.225.08:21:50.14/cable/+6.4048E-03 2006.225.08:21:50.14/wx/28.08,1003.3,75 2006.225.08:21:51.07/fmout-gps/S +4.55E-07 2006.225.08:21:51.07:scan_name=225-0824,k06225,60 2006.225.08:21:51.08:source=oq208,140700.39,282714.7,2000.0,ccw 2006.225.08:21:51.14#flagr#flagr/antenna,new-source 2006.225.08:21:52.14:checkk5 2006.225.08:21:52.51/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:21:52.89/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:21:53.25/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:21:53.63/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:21:54.00/chk_obsdata//k5ts1/T2250820??a.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:21:54.37/chk_obsdata//k5ts2/T2250820??b.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:21:54.74/chk_obsdata//k5ts3/T2250820??c.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:21:55.11/chk_obsdata//k5ts4/T2250820??d.dat file size is correct (nominal:480MB, actual:472MB). 2006.225.08:21:55.79/k5log//k5ts1_log_newline 2006.225.08:21:56.49/k5log//k5ts2_log_newline 2006.225.08:21:57.17/k5log//k5ts3_log_newline 2006.225.08:21:57.85/k5log//k5ts4_log_newline 2006.225.08:21:57.87/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:21:57.87:4f8m12a=3 2006.225.08:21:57.87$4f8m12a/echo=on 2006.225.08:21:57.87$4f8m12a/pcalon 2006.225.08:21:57.87$pcalon/"no phase cal control is implemented here 2006.225.08:21:57.87$4f8m12a/"tpicd=stop 2006.225.08:21:57.87$4f8m12a/vc4f8 2006.225.08:21:57.87$vc4f8/valo=1,532.99 2006.225.08:21:57.87#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.08:21:57.87#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.08:21:57.87#ibcon#ireg 17 cls_cnt 0 2006.225.08:21:57.87#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:21:57.87#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:21:57.87#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:21:57.87#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:21:57.87#ibcon#first serial, iclass 10, count 0 2006.225.08:21:57.87#ibcon#enter sib2, iclass 10, count 0 2006.225.08:21:57.87#ibcon#flushed, iclass 10, count 0 2006.225.08:21:57.87#ibcon#about to write, iclass 10, count 0 2006.225.08:21:57.87#ibcon#wrote, iclass 10, count 0 2006.225.08:21:57.87#ibcon#about to read 3, iclass 10, count 0 2006.225.08:21:57.89#ibcon#read 3, iclass 10, count 0 2006.225.08:21:57.89#ibcon#about to read 4, iclass 10, count 0 2006.225.08:21:57.89#ibcon#read 4, iclass 10, count 0 2006.225.08:21:57.89#ibcon#about to read 5, iclass 10, count 0 2006.225.08:21:57.89#ibcon#read 5, iclass 10, count 0 2006.225.08:21:57.89#ibcon#about to read 6, iclass 10, count 0 2006.225.08:21:57.89#ibcon#read 6, iclass 10, count 0 2006.225.08:21:57.89#ibcon#end of sib2, iclass 10, count 0 2006.225.08:21:57.89#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:21:57.89#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:21:57.89#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:21:57.89#ibcon#*before write, iclass 10, count 0 2006.225.08:21:57.89#ibcon#enter sib2, iclass 10, count 0 2006.225.08:21:57.89#ibcon#flushed, iclass 10, count 0 2006.225.08:21:57.89#ibcon#about to write, iclass 10, count 0 2006.225.08:21:57.89#ibcon#wrote, iclass 10, count 0 2006.225.08:21:57.89#ibcon#about to read 3, iclass 10, count 0 2006.225.08:21:57.94#ibcon#read 3, iclass 10, count 0 2006.225.08:21:57.94#ibcon#about to read 4, iclass 10, count 0 2006.225.08:21:57.94#ibcon#read 4, iclass 10, count 0 2006.225.08:21:57.94#ibcon#about to read 5, iclass 10, count 0 2006.225.08:21:57.94#ibcon#read 5, iclass 10, count 0 2006.225.08:21:57.94#ibcon#about to read 6, iclass 10, count 0 2006.225.08:21:57.94#ibcon#read 6, iclass 10, count 0 2006.225.08:21:57.94#ibcon#end of sib2, iclass 10, count 0 2006.225.08:21:57.94#ibcon#*after write, iclass 10, count 0 2006.225.08:21:57.94#ibcon#*before return 0, iclass 10, count 0 2006.225.08:21:57.94#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:21:57.94#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:21:57.94#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:21:57.94#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:21:57.94$vc4f8/va=1,8 2006.225.08:21:57.94#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.08:21:57.94#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.08:21:57.94#ibcon#ireg 11 cls_cnt 2 2006.225.08:21:57.94#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:21:57.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:21:57.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:21:57.94#ibcon#enter wrdev, iclass 12, count 2 2006.225.08:21:57.94#ibcon#first serial, iclass 12, count 2 2006.225.08:21:57.94#ibcon#enter sib2, iclass 12, count 2 2006.225.08:21:57.94#ibcon#flushed, iclass 12, count 2 2006.225.08:21:57.94#ibcon#about to write, iclass 12, count 2 2006.225.08:21:57.94#ibcon#wrote, iclass 12, count 2 2006.225.08:21:57.94#ibcon#about to read 3, iclass 12, count 2 2006.225.08:21:57.96#ibcon#read 3, iclass 12, count 2 2006.225.08:21:57.96#ibcon#about to read 4, iclass 12, count 2 2006.225.08:21:57.96#ibcon#read 4, iclass 12, count 2 2006.225.08:21:57.96#ibcon#about to read 5, iclass 12, count 2 2006.225.08:21:57.96#ibcon#read 5, iclass 12, count 2 2006.225.08:21:57.96#ibcon#about to read 6, iclass 12, count 2 2006.225.08:21:57.96#ibcon#read 6, iclass 12, count 2 2006.225.08:21:57.96#ibcon#end of sib2, iclass 12, count 2 2006.225.08:21:57.96#ibcon#*mode == 0, iclass 12, count 2 2006.225.08:21:57.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.08:21:57.96#ibcon#[25=AT01-08\r\n] 2006.225.08:21:57.96#ibcon#*before write, iclass 12, count 2 2006.225.08:21:57.96#ibcon#enter sib2, iclass 12, count 2 2006.225.08:21:57.96#ibcon#flushed, iclass 12, count 2 2006.225.08:21:57.96#ibcon#about to write, iclass 12, count 2 2006.225.08:21:57.96#ibcon#wrote, iclass 12, count 2 2006.225.08:21:57.96#ibcon#about to read 3, iclass 12, count 2 2006.225.08:21:57.99#ibcon#read 3, iclass 12, count 2 2006.225.08:21:57.99#ibcon#about to read 4, iclass 12, count 2 2006.225.08:21:57.99#ibcon#read 4, iclass 12, count 2 2006.225.08:21:57.99#ibcon#about to read 5, iclass 12, count 2 2006.225.08:21:57.99#ibcon#read 5, iclass 12, count 2 2006.225.08:21:57.99#ibcon#about to read 6, iclass 12, count 2 2006.225.08:21:57.99#ibcon#read 6, iclass 12, count 2 2006.225.08:21:57.99#ibcon#end of sib2, iclass 12, count 2 2006.225.08:21:57.99#ibcon#*after write, iclass 12, count 2 2006.225.08:21:57.99#ibcon#*before return 0, iclass 12, count 2 2006.225.08:21:57.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:21:57.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:21:57.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.08:21:57.99#ibcon#ireg 7 cls_cnt 0 2006.225.08:21:57.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:21:58.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:21:58.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:21:58.11#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:21:58.11#ibcon#first serial, iclass 12, count 0 2006.225.08:21:58.11#ibcon#enter sib2, iclass 12, count 0 2006.225.08:21:58.11#ibcon#flushed, iclass 12, count 0 2006.225.08:21:58.11#ibcon#about to write, iclass 12, count 0 2006.225.08:21:58.11#ibcon#wrote, iclass 12, count 0 2006.225.08:21:58.11#ibcon#about to read 3, iclass 12, count 0 2006.225.08:21:58.13#ibcon#read 3, iclass 12, count 0 2006.225.08:21:58.13#ibcon#about to read 4, iclass 12, count 0 2006.225.08:21:58.13#ibcon#read 4, iclass 12, count 0 2006.225.08:21:58.13#ibcon#about to read 5, iclass 12, count 0 2006.225.08:21:58.13#ibcon#read 5, iclass 12, count 0 2006.225.08:21:58.13#ibcon#about to read 6, iclass 12, count 0 2006.225.08:21:58.13#ibcon#read 6, iclass 12, count 0 2006.225.08:21:58.13#ibcon#end of sib2, iclass 12, count 0 2006.225.08:21:58.13#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:21:58.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:21:58.13#ibcon#[25=USB\r\n] 2006.225.08:21:58.13#ibcon#*before write, iclass 12, count 0 2006.225.08:21:58.13#ibcon#enter sib2, iclass 12, count 0 2006.225.08:21:58.13#ibcon#flushed, iclass 12, count 0 2006.225.08:21:58.13#ibcon#about to write, iclass 12, count 0 2006.225.08:21:58.13#ibcon#wrote, iclass 12, count 0 2006.225.08:21:58.13#ibcon#about to read 3, iclass 12, count 0 2006.225.08:21:58.16#ibcon#read 3, iclass 12, count 0 2006.225.08:21:58.16#ibcon#about to read 4, iclass 12, count 0 2006.225.08:21:58.16#ibcon#read 4, iclass 12, count 0 2006.225.08:21:58.16#ibcon#about to read 5, iclass 12, count 0 2006.225.08:21:58.16#ibcon#read 5, iclass 12, count 0 2006.225.08:21:58.16#ibcon#about to read 6, iclass 12, count 0 2006.225.08:21:58.16#ibcon#read 6, iclass 12, count 0 2006.225.08:21:58.16#ibcon#end of sib2, iclass 12, count 0 2006.225.08:21:58.16#ibcon#*after write, iclass 12, count 0 2006.225.08:21:58.16#ibcon#*before return 0, iclass 12, count 0 2006.225.08:21:58.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:21:58.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:21:58.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:21:58.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:21:58.16$vc4f8/valo=2,572.99 2006.225.08:21:58.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.08:21:58.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.08:21:58.16#ibcon#ireg 17 cls_cnt 0 2006.225.08:21:58.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:21:58.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:21:58.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:21:58.16#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:21:58.16#ibcon#first serial, iclass 14, count 0 2006.225.08:21:58.16#ibcon#enter sib2, iclass 14, count 0 2006.225.08:21:58.16#ibcon#flushed, iclass 14, count 0 2006.225.08:21:58.16#ibcon#about to write, iclass 14, count 0 2006.225.08:21:58.16#ibcon#wrote, iclass 14, count 0 2006.225.08:21:58.16#ibcon#about to read 3, iclass 14, count 0 2006.225.08:21:58.19#ibcon#read 3, iclass 14, count 0 2006.225.08:21:58.19#ibcon#about to read 4, iclass 14, count 0 2006.225.08:21:58.19#ibcon#read 4, iclass 14, count 0 2006.225.08:21:58.19#ibcon#about to read 5, iclass 14, count 0 2006.225.08:21:58.19#ibcon#read 5, iclass 14, count 0 2006.225.08:21:58.19#ibcon#about to read 6, iclass 14, count 0 2006.225.08:21:58.19#ibcon#read 6, iclass 14, count 0 2006.225.08:21:58.19#ibcon#end of sib2, iclass 14, count 0 2006.225.08:21:58.19#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:21:58.19#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:21:58.19#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:21:58.19#ibcon#*before write, iclass 14, count 0 2006.225.08:21:58.19#ibcon#enter sib2, iclass 14, count 0 2006.225.08:21:58.19#ibcon#flushed, iclass 14, count 0 2006.225.08:21:58.19#ibcon#about to write, iclass 14, count 0 2006.225.08:21:58.19#ibcon#wrote, iclass 14, count 0 2006.225.08:21:58.19#ibcon#about to read 3, iclass 14, count 0 2006.225.08:21:58.23#ibcon#read 3, iclass 14, count 0 2006.225.08:21:58.23#ibcon#about to read 4, iclass 14, count 0 2006.225.08:21:58.23#ibcon#read 4, iclass 14, count 0 2006.225.08:21:58.23#ibcon#about to read 5, iclass 14, count 0 2006.225.08:21:58.23#ibcon#read 5, iclass 14, count 0 2006.225.08:21:58.23#ibcon#about to read 6, iclass 14, count 0 2006.225.08:21:58.23#ibcon#read 6, iclass 14, count 0 2006.225.08:21:58.23#ibcon#end of sib2, iclass 14, count 0 2006.225.08:21:58.23#ibcon#*after write, iclass 14, count 0 2006.225.08:21:58.23#ibcon#*before return 0, iclass 14, count 0 2006.225.08:21:58.23#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:21:58.23#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:21:58.23#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:21:58.23#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:21:58.23$vc4f8/va=2,7 2006.225.08:21:58.23#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.08:21:58.23#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.08:21:58.23#ibcon#ireg 11 cls_cnt 2 2006.225.08:21:58.23#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:21:58.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:21:58.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:21:58.28#ibcon#enter wrdev, iclass 16, count 2 2006.225.08:21:58.28#ibcon#first serial, iclass 16, count 2 2006.225.08:21:58.28#ibcon#enter sib2, iclass 16, count 2 2006.225.08:21:58.28#ibcon#flushed, iclass 16, count 2 2006.225.08:21:58.28#ibcon#about to write, iclass 16, count 2 2006.225.08:21:58.28#ibcon#wrote, iclass 16, count 2 2006.225.08:21:58.28#ibcon#about to read 3, iclass 16, count 2 2006.225.08:21:58.30#ibcon#read 3, iclass 16, count 2 2006.225.08:21:58.30#ibcon#about to read 4, iclass 16, count 2 2006.225.08:21:58.30#ibcon#read 4, iclass 16, count 2 2006.225.08:21:58.30#ibcon#about to read 5, iclass 16, count 2 2006.225.08:21:58.30#ibcon#read 5, iclass 16, count 2 2006.225.08:21:58.30#ibcon#about to read 6, iclass 16, count 2 2006.225.08:21:58.30#ibcon#read 6, iclass 16, count 2 2006.225.08:21:58.30#ibcon#end of sib2, iclass 16, count 2 2006.225.08:21:58.30#ibcon#*mode == 0, iclass 16, count 2 2006.225.08:21:58.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.08:21:58.30#ibcon#[25=AT02-07\r\n] 2006.225.08:21:58.30#ibcon#*before write, iclass 16, count 2 2006.225.08:21:58.30#ibcon#enter sib2, iclass 16, count 2 2006.225.08:21:58.30#ibcon#flushed, iclass 16, count 2 2006.225.08:21:58.30#ibcon#about to write, iclass 16, count 2 2006.225.08:21:58.30#ibcon#wrote, iclass 16, count 2 2006.225.08:21:58.30#ibcon#about to read 3, iclass 16, count 2 2006.225.08:21:58.33#ibcon#read 3, iclass 16, count 2 2006.225.08:21:58.33#ibcon#about to read 4, iclass 16, count 2 2006.225.08:21:58.33#ibcon#read 4, iclass 16, count 2 2006.225.08:21:58.33#ibcon#about to read 5, iclass 16, count 2 2006.225.08:21:58.33#ibcon#read 5, iclass 16, count 2 2006.225.08:21:58.33#ibcon#about to read 6, iclass 16, count 2 2006.225.08:21:58.33#ibcon#read 6, iclass 16, count 2 2006.225.08:21:58.33#ibcon#end of sib2, iclass 16, count 2 2006.225.08:21:58.33#ibcon#*after write, iclass 16, count 2 2006.225.08:21:58.33#ibcon#*before return 0, iclass 16, count 2 2006.225.08:21:58.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:21:58.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:21:58.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.08:21:58.33#ibcon#ireg 7 cls_cnt 0 2006.225.08:21:58.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:21:58.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:21:58.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:21:58.45#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:21:58.45#ibcon#first serial, iclass 16, count 0 2006.225.08:21:58.45#ibcon#enter sib2, iclass 16, count 0 2006.225.08:21:58.45#ibcon#flushed, iclass 16, count 0 2006.225.08:21:58.45#ibcon#about to write, iclass 16, count 0 2006.225.08:21:58.45#ibcon#wrote, iclass 16, count 0 2006.225.08:21:58.45#ibcon#about to read 3, iclass 16, count 0 2006.225.08:21:58.47#ibcon#read 3, iclass 16, count 0 2006.225.08:21:58.47#ibcon#about to read 4, iclass 16, count 0 2006.225.08:21:58.47#ibcon#read 4, iclass 16, count 0 2006.225.08:21:58.47#ibcon#about to read 5, iclass 16, count 0 2006.225.08:21:58.47#ibcon#read 5, iclass 16, count 0 2006.225.08:21:58.47#ibcon#about to read 6, iclass 16, count 0 2006.225.08:21:58.47#ibcon#read 6, iclass 16, count 0 2006.225.08:21:58.47#ibcon#end of sib2, iclass 16, count 0 2006.225.08:21:58.47#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:21:58.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:21:58.47#ibcon#[25=USB\r\n] 2006.225.08:21:58.47#ibcon#*before write, iclass 16, count 0 2006.225.08:21:58.47#ibcon#enter sib2, iclass 16, count 0 2006.225.08:21:58.47#ibcon#flushed, iclass 16, count 0 2006.225.08:21:58.47#ibcon#about to write, iclass 16, count 0 2006.225.08:21:58.47#ibcon#wrote, iclass 16, count 0 2006.225.08:21:58.47#ibcon#about to read 3, iclass 16, count 0 2006.225.08:21:58.50#ibcon#read 3, iclass 16, count 0 2006.225.08:21:58.50#ibcon#about to read 4, iclass 16, count 0 2006.225.08:21:58.50#ibcon#read 4, iclass 16, count 0 2006.225.08:21:58.50#ibcon#about to read 5, iclass 16, count 0 2006.225.08:21:58.50#ibcon#read 5, iclass 16, count 0 2006.225.08:21:58.50#ibcon#about to read 6, iclass 16, count 0 2006.225.08:21:58.50#ibcon#read 6, iclass 16, count 0 2006.225.08:21:58.50#ibcon#end of sib2, iclass 16, count 0 2006.225.08:21:58.50#ibcon#*after write, iclass 16, count 0 2006.225.08:21:58.50#ibcon#*before return 0, iclass 16, count 0 2006.225.08:21:58.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:21:58.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:21:58.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:21:58.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:21:58.50$vc4f8/valo=3,672.99 2006.225.08:21:58.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.08:21:58.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.08:21:58.50#ibcon#ireg 17 cls_cnt 0 2006.225.08:21:58.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:21:58.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:21:58.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:21:58.50#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:21:58.50#ibcon#first serial, iclass 18, count 0 2006.225.08:21:58.50#ibcon#enter sib2, iclass 18, count 0 2006.225.08:21:58.50#ibcon#flushed, iclass 18, count 0 2006.225.08:21:58.50#ibcon#about to write, iclass 18, count 0 2006.225.08:21:58.50#ibcon#wrote, iclass 18, count 0 2006.225.08:21:58.50#ibcon#about to read 3, iclass 18, count 0 2006.225.08:21:58.53#ibcon#read 3, iclass 18, count 0 2006.225.08:21:58.53#ibcon#about to read 4, iclass 18, count 0 2006.225.08:21:58.53#ibcon#read 4, iclass 18, count 0 2006.225.08:21:58.53#ibcon#about to read 5, iclass 18, count 0 2006.225.08:21:58.53#ibcon#read 5, iclass 18, count 0 2006.225.08:21:58.53#ibcon#about to read 6, iclass 18, count 0 2006.225.08:21:58.53#ibcon#read 6, iclass 18, count 0 2006.225.08:21:58.53#ibcon#end of sib2, iclass 18, count 0 2006.225.08:21:58.53#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:21:58.53#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:21:58.53#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:21:58.53#ibcon#*before write, iclass 18, count 0 2006.225.08:21:58.53#ibcon#enter sib2, iclass 18, count 0 2006.225.08:21:58.53#ibcon#flushed, iclass 18, count 0 2006.225.08:21:58.53#ibcon#about to write, iclass 18, count 0 2006.225.08:21:58.53#ibcon#wrote, iclass 18, count 0 2006.225.08:21:58.53#ibcon#about to read 3, iclass 18, count 0 2006.225.08:21:58.57#ibcon#read 3, iclass 18, count 0 2006.225.08:21:58.57#ibcon#about to read 4, iclass 18, count 0 2006.225.08:21:58.57#ibcon#read 4, iclass 18, count 0 2006.225.08:21:58.57#ibcon#about to read 5, iclass 18, count 0 2006.225.08:21:58.57#ibcon#read 5, iclass 18, count 0 2006.225.08:21:58.57#ibcon#about to read 6, iclass 18, count 0 2006.225.08:21:58.57#ibcon#read 6, iclass 18, count 0 2006.225.08:21:58.57#ibcon#end of sib2, iclass 18, count 0 2006.225.08:21:58.57#ibcon#*after write, iclass 18, count 0 2006.225.08:21:58.57#ibcon#*before return 0, iclass 18, count 0 2006.225.08:21:58.57#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:21:58.57#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:21:58.57#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:21:58.57#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:21:58.57$vc4f8/va=3,6 2006.225.08:21:58.57#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.08:21:58.57#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.08:21:58.57#ibcon#ireg 11 cls_cnt 2 2006.225.08:21:58.57#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:21:58.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:21:58.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:21:58.62#ibcon#enter wrdev, iclass 20, count 2 2006.225.08:21:58.62#ibcon#first serial, iclass 20, count 2 2006.225.08:21:58.62#ibcon#enter sib2, iclass 20, count 2 2006.225.08:21:58.62#ibcon#flushed, iclass 20, count 2 2006.225.08:21:58.62#ibcon#about to write, iclass 20, count 2 2006.225.08:21:58.62#ibcon#wrote, iclass 20, count 2 2006.225.08:21:58.62#ibcon#about to read 3, iclass 20, count 2 2006.225.08:21:58.64#ibcon#read 3, iclass 20, count 2 2006.225.08:21:58.64#ibcon#about to read 4, iclass 20, count 2 2006.225.08:21:58.64#ibcon#read 4, iclass 20, count 2 2006.225.08:21:58.64#ibcon#about to read 5, iclass 20, count 2 2006.225.08:21:58.64#ibcon#read 5, iclass 20, count 2 2006.225.08:21:58.64#ibcon#about to read 6, iclass 20, count 2 2006.225.08:21:58.64#ibcon#read 6, iclass 20, count 2 2006.225.08:21:58.64#ibcon#end of sib2, iclass 20, count 2 2006.225.08:21:58.64#ibcon#*mode == 0, iclass 20, count 2 2006.225.08:21:58.64#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.08:21:58.64#ibcon#[25=AT03-06\r\n] 2006.225.08:21:58.64#ibcon#*before write, iclass 20, count 2 2006.225.08:21:58.64#ibcon#enter sib2, iclass 20, count 2 2006.225.08:21:58.64#ibcon#flushed, iclass 20, count 2 2006.225.08:21:58.64#ibcon#about to write, iclass 20, count 2 2006.225.08:21:58.64#ibcon#wrote, iclass 20, count 2 2006.225.08:21:58.64#ibcon#about to read 3, iclass 20, count 2 2006.225.08:21:58.67#ibcon#read 3, iclass 20, count 2 2006.225.08:21:58.67#ibcon#about to read 4, iclass 20, count 2 2006.225.08:21:58.67#ibcon#read 4, iclass 20, count 2 2006.225.08:21:58.67#ibcon#about to read 5, iclass 20, count 2 2006.225.08:21:58.67#ibcon#read 5, iclass 20, count 2 2006.225.08:21:58.67#ibcon#about to read 6, iclass 20, count 2 2006.225.08:21:58.67#ibcon#read 6, iclass 20, count 2 2006.225.08:21:58.67#ibcon#end of sib2, iclass 20, count 2 2006.225.08:21:58.67#ibcon#*after write, iclass 20, count 2 2006.225.08:21:58.67#ibcon#*before return 0, iclass 20, count 2 2006.225.08:21:58.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:21:58.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:21:58.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.08:21:58.67#ibcon#ireg 7 cls_cnt 0 2006.225.08:21:58.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:21:58.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:21:58.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:21:58.79#ibcon#enter wrdev, iclass 20, count 0 2006.225.08:21:58.79#ibcon#first serial, iclass 20, count 0 2006.225.08:21:58.79#ibcon#enter sib2, iclass 20, count 0 2006.225.08:21:58.79#ibcon#flushed, iclass 20, count 0 2006.225.08:21:58.79#ibcon#about to write, iclass 20, count 0 2006.225.08:21:58.79#ibcon#wrote, iclass 20, count 0 2006.225.08:21:58.79#ibcon#about to read 3, iclass 20, count 0 2006.225.08:21:58.81#ibcon#read 3, iclass 20, count 0 2006.225.08:21:58.81#ibcon#about to read 4, iclass 20, count 0 2006.225.08:21:58.81#ibcon#read 4, iclass 20, count 0 2006.225.08:21:58.81#ibcon#about to read 5, iclass 20, count 0 2006.225.08:21:58.81#ibcon#read 5, iclass 20, count 0 2006.225.08:21:58.81#ibcon#about to read 6, iclass 20, count 0 2006.225.08:21:58.81#ibcon#read 6, iclass 20, count 0 2006.225.08:21:58.81#ibcon#end of sib2, iclass 20, count 0 2006.225.08:21:58.81#ibcon#*mode == 0, iclass 20, count 0 2006.225.08:21:58.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.08:21:58.81#ibcon#[25=USB\r\n] 2006.225.08:21:58.81#ibcon#*before write, iclass 20, count 0 2006.225.08:21:58.81#ibcon#enter sib2, iclass 20, count 0 2006.225.08:21:58.81#ibcon#flushed, iclass 20, count 0 2006.225.08:21:58.81#ibcon#about to write, iclass 20, count 0 2006.225.08:21:58.81#ibcon#wrote, iclass 20, count 0 2006.225.08:21:58.81#ibcon#about to read 3, iclass 20, count 0 2006.225.08:21:58.84#ibcon#read 3, iclass 20, count 0 2006.225.08:21:58.84#ibcon#about to read 4, iclass 20, count 0 2006.225.08:21:58.84#ibcon#read 4, iclass 20, count 0 2006.225.08:21:58.84#ibcon#about to read 5, iclass 20, count 0 2006.225.08:21:58.84#ibcon#read 5, iclass 20, count 0 2006.225.08:21:58.84#ibcon#about to read 6, iclass 20, count 0 2006.225.08:21:58.84#ibcon#read 6, iclass 20, count 0 2006.225.08:21:58.84#ibcon#end of sib2, iclass 20, count 0 2006.225.08:21:58.84#ibcon#*after write, iclass 20, count 0 2006.225.08:21:58.84#ibcon#*before return 0, iclass 20, count 0 2006.225.08:21:58.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:21:58.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:21:58.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.08:21:58.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.08:21:58.84$vc4f8/valo=4,832.99 2006.225.08:21:58.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.08:21:58.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.08:21:58.84#ibcon#ireg 17 cls_cnt 0 2006.225.08:21:58.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:21:58.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:21:58.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:21:58.84#ibcon#enter wrdev, iclass 22, count 0 2006.225.08:21:58.84#ibcon#first serial, iclass 22, count 0 2006.225.08:21:58.84#ibcon#enter sib2, iclass 22, count 0 2006.225.08:21:58.84#ibcon#flushed, iclass 22, count 0 2006.225.08:21:58.84#ibcon#about to write, iclass 22, count 0 2006.225.08:21:58.84#ibcon#wrote, iclass 22, count 0 2006.225.08:21:58.84#ibcon#about to read 3, iclass 22, count 0 2006.225.08:21:58.87#ibcon#read 3, iclass 22, count 0 2006.225.08:21:58.87#ibcon#about to read 4, iclass 22, count 0 2006.225.08:21:58.87#ibcon#read 4, iclass 22, count 0 2006.225.08:21:58.87#ibcon#about to read 5, iclass 22, count 0 2006.225.08:21:58.87#ibcon#read 5, iclass 22, count 0 2006.225.08:21:58.87#ibcon#about to read 6, iclass 22, count 0 2006.225.08:21:58.87#ibcon#read 6, iclass 22, count 0 2006.225.08:21:58.87#ibcon#end of sib2, iclass 22, count 0 2006.225.08:21:58.87#ibcon#*mode == 0, iclass 22, count 0 2006.225.08:21:58.87#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.08:21:58.87#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:21:58.87#ibcon#*before write, iclass 22, count 0 2006.225.08:21:58.87#ibcon#enter sib2, iclass 22, count 0 2006.225.08:21:58.87#ibcon#flushed, iclass 22, count 0 2006.225.08:21:58.87#ibcon#about to write, iclass 22, count 0 2006.225.08:21:58.87#ibcon#wrote, iclass 22, count 0 2006.225.08:21:58.87#ibcon#about to read 3, iclass 22, count 0 2006.225.08:21:58.91#ibcon#read 3, iclass 22, count 0 2006.225.08:21:58.91#ibcon#about to read 4, iclass 22, count 0 2006.225.08:21:58.91#ibcon#read 4, iclass 22, count 0 2006.225.08:21:58.91#ibcon#about to read 5, iclass 22, count 0 2006.225.08:21:58.91#ibcon#read 5, iclass 22, count 0 2006.225.08:21:58.91#ibcon#about to read 6, iclass 22, count 0 2006.225.08:21:58.91#ibcon#read 6, iclass 22, count 0 2006.225.08:21:58.91#ibcon#end of sib2, iclass 22, count 0 2006.225.08:21:58.91#ibcon#*after write, iclass 22, count 0 2006.225.08:21:58.91#ibcon#*before return 0, iclass 22, count 0 2006.225.08:21:58.91#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:21:58.91#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:21:58.91#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.08:21:58.91#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.08:21:58.91$vc4f8/va=4,7 2006.225.08:21:58.91#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.08:21:58.91#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.08:21:58.91#ibcon#ireg 11 cls_cnt 2 2006.225.08:21:58.91#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:21:58.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:21:58.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:21:58.96#ibcon#enter wrdev, iclass 24, count 2 2006.225.08:21:58.96#ibcon#first serial, iclass 24, count 2 2006.225.08:21:58.96#ibcon#enter sib2, iclass 24, count 2 2006.225.08:21:58.96#ibcon#flushed, iclass 24, count 2 2006.225.08:21:58.96#ibcon#about to write, iclass 24, count 2 2006.225.08:21:58.96#ibcon#wrote, iclass 24, count 2 2006.225.08:21:58.96#ibcon#about to read 3, iclass 24, count 2 2006.225.08:21:58.98#ibcon#read 3, iclass 24, count 2 2006.225.08:21:58.98#ibcon#about to read 4, iclass 24, count 2 2006.225.08:21:58.98#ibcon#read 4, iclass 24, count 2 2006.225.08:21:58.98#ibcon#about to read 5, iclass 24, count 2 2006.225.08:21:58.98#ibcon#read 5, iclass 24, count 2 2006.225.08:21:58.98#ibcon#about to read 6, iclass 24, count 2 2006.225.08:21:58.98#ibcon#read 6, iclass 24, count 2 2006.225.08:21:58.98#ibcon#end of sib2, iclass 24, count 2 2006.225.08:21:58.98#ibcon#*mode == 0, iclass 24, count 2 2006.225.08:21:58.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.08:21:58.98#ibcon#[25=AT04-07\r\n] 2006.225.08:21:58.98#ibcon#*before write, iclass 24, count 2 2006.225.08:21:58.98#ibcon#enter sib2, iclass 24, count 2 2006.225.08:21:58.98#ibcon#flushed, iclass 24, count 2 2006.225.08:21:58.98#ibcon#about to write, iclass 24, count 2 2006.225.08:21:58.98#ibcon#wrote, iclass 24, count 2 2006.225.08:21:58.98#ibcon#about to read 3, iclass 24, count 2 2006.225.08:21:59.01#ibcon#read 3, iclass 24, count 2 2006.225.08:21:59.01#ibcon#about to read 4, iclass 24, count 2 2006.225.08:21:59.01#ibcon#read 4, iclass 24, count 2 2006.225.08:21:59.01#ibcon#about to read 5, iclass 24, count 2 2006.225.08:21:59.01#ibcon#read 5, iclass 24, count 2 2006.225.08:21:59.01#ibcon#about to read 6, iclass 24, count 2 2006.225.08:21:59.01#ibcon#read 6, iclass 24, count 2 2006.225.08:21:59.01#ibcon#end of sib2, iclass 24, count 2 2006.225.08:21:59.01#ibcon#*after write, iclass 24, count 2 2006.225.08:21:59.01#ibcon#*before return 0, iclass 24, count 2 2006.225.08:21:59.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:21:59.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:21:59.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.08:21:59.01#ibcon#ireg 7 cls_cnt 0 2006.225.08:21:59.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:21:59.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:21:59.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:21:59.13#ibcon#enter wrdev, iclass 24, count 0 2006.225.08:21:59.13#ibcon#first serial, iclass 24, count 0 2006.225.08:21:59.13#ibcon#enter sib2, iclass 24, count 0 2006.225.08:21:59.13#ibcon#flushed, iclass 24, count 0 2006.225.08:21:59.13#ibcon#about to write, iclass 24, count 0 2006.225.08:21:59.13#ibcon#wrote, iclass 24, count 0 2006.225.08:21:59.13#ibcon#about to read 3, iclass 24, count 0 2006.225.08:21:59.15#ibcon#read 3, iclass 24, count 0 2006.225.08:21:59.15#ibcon#about to read 4, iclass 24, count 0 2006.225.08:21:59.15#ibcon#read 4, iclass 24, count 0 2006.225.08:21:59.15#ibcon#about to read 5, iclass 24, count 0 2006.225.08:21:59.15#ibcon#read 5, iclass 24, count 0 2006.225.08:21:59.15#ibcon#about to read 6, iclass 24, count 0 2006.225.08:21:59.15#ibcon#read 6, iclass 24, count 0 2006.225.08:21:59.15#ibcon#end of sib2, iclass 24, count 0 2006.225.08:21:59.15#ibcon#*mode == 0, iclass 24, count 0 2006.225.08:21:59.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.08:21:59.15#ibcon#[25=USB\r\n] 2006.225.08:21:59.15#ibcon#*before write, iclass 24, count 0 2006.225.08:21:59.15#ibcon#enter sib2, iclass 24, count 0 2006.225.08:21:59.15#ibcon#flushed, iclass 24, count 0 2006.225.08:21:59.15#ibcon#about to write, iclass 24, count 0 2006.225.08:21:59.15#ibcon#wrote, iclass 24, count 0 2006.225.08:21:59.15#ibcon#about to read 3, iclass 24, count 0 2006.225.08:21:59.18#ibcon#read 3, iclass 24, count 0 2006.225.08:21:59.18#ibcon#about to read 4, iclass 24, count 0 2006.225.08:21:59.18#ibcon#read 4, iclass 24, count 0 2006.225.08:21:59.18#ibcon#about to read 5, iclass 24, count 0 2006.225.08:21:59.18#ibcon#read 5, iclass 24, count 0 2006.225.08:21:59.18#ibcon#about to read 6, iclass 24, count 0 2006.225.08:21:59.18#ibcon#read 6, iclass 24, count 0 2006.225.08:21:59.18#ibcon#end of sib2, iclass 24, count 0 2006.225.08:21:59.18#ibcon#*after write, iclass 24, count 0 2006.225.08:21:59.18#ibcon#*before return 0, iclass 24, count 0 2006.225.08:21:59.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:21:59.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:21:59.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.08:21:59.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.08:21:59.18$vc4f8/valo=5,652.99 2006.225.08:21:59.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.08:21:59.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.08:21:59.18#ibcon#ireg 17 cls_cnt 0 2006.225.08:21:59.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:21:59.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:21:59.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:21:59.18#ibcon#enter wrdev, iclass 26, count 0 2006.225.08:21:59.18#ibcon#first serial, iclass 26, count 0 2006.225.08:21:59.18#ibcon#enter sib2, iclass 26, count 0 2006.225.08:21:59.18#ibcon#flushed, iclass 26, count 0 2006.225.08:21:59.18#ibcon#about to write, iclass 26, count 0 2006.225.08:21:59.18#ibcon#wrote, iclass 26, count 0 2006.225.08:21:59.18#ibcon#about to read 3, iclass 26, count 0 2006.225.08:21:59.20#ibcon#read 3, iclass 26, count 0 2006.225.08:21:59.20#ibcon#about to read 4, iclass 26, count 0 2006.225.08:21:59.20#ibcon#read 4, iclass 26, count 0 2006.225.08:21:59.20#ibcon#about to read 5, iclass 26, count 0 2006.225.08:21:59.20#ibcon#read 5, iclass 26, count 0 2006.225.08:21:59.20#ibcon#about to read 6, iclass 26, count 0 2006.225.08:21:59.20#ibcon#read 6, iclass 26, count 0 2006.225.08:21:59.20#ibcon#end of sib2, iclass 26, count 0 2006.225.08:21:59.20#ibcon#*mode == 0, iclass 26, count 0 2006.225.08:21:59.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.08:21:59.20#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:21:59.20#ibcon#*before write, iclass 26, count 0 2006.225.08:21:59.20#ibcon#enter sib2, iclass 26, count 0 2006.225.08:21:59.20#ibcon#flushed, iclass 26, count 0 2006.225.08:21:59.20#ibcon#about to write, iclass 26, count 0 2006.225.08:21:59.20#ibcon#wrote, iclass 26, count 0 2006.225.08:21:59.20#ibcon#about to read 3, iclass 26, count 0 2006.225.08:21:59.24#ibcon#read 3, iclass 26, count 0 2006.225.08:21:59.24#ibcon#about to read 4, iclass 26, count 0 2006.225.08:21:59.24#ibcon#read 4, iclass 26, count 0 2006.225.08:21:59.24#ibcon#about to read 5, iclass 26, count 0 2006.225.08:21:59.24#ibcon#read 5, iclass 26, count 0 2006.225.08:21:59.24#ibcon#about to read 6, iclass 26, count 0 2006.225.08:21:59.24#ibcon#read 6, iclass 26, count 0 2006.225.08:21:59.24#ibcon#end of sib2, iclass 26, count 0 2006.225.08:21:59.24#ibcon#*after write, iclass 26, count 0 2006.225.08:21:59.24#ibcon#*before return 0, iclass 26, count 0 2006.225.08:21:59.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:21:59.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:21:59.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.08:21:59.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.08:21:59.24$vc4f8/va=5,7 2006.225.08:21:59.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.08:21:59.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.08:21:59.24#ibcon#ireg 11 cls_cnt 2 2006.225.08:21:59.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:21:59.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:21:59.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:21:59.30#ibcon#enter wrdev, iclass 28, count 2 2006.225.08:21:59.30#ibcon#first serial, iclass 28, count 2 2006.225.08:21:59.30#ibcon#enter sib2, iclass 28, count 2 2006.225.08:21:59.30#ibcon#flushed, iclass 28, count 2 2006.225.08:21:59.30#ibcon#about to write, iclass 28, count 2 2006.225.08:21:59.30#ibcon#wrote, iclass 28, count 2 2006.225.08:21:59.30#ibcon#about to read 3, iclass 28, count 2 2006.225.08:21:59.32#ibcon#read 3, iclass 28, count 2 2006.225.08:21:59.32#ibcon#about to read 4, iclass 28, count 2 2006.225.08:21:59.32#ibcon#read 4, iclass 28, count 2 2006.225.08:21:59.32#ibcon#about to read 5, iclass 28, count 2 2006.225.08:21:59.32#ibcon#read 5, iclass 28, count 2 2006.225.08:21:59.32#ibcon#about to read 6, iclass 28, count 2 2006.225.08:21:59.32#ibcon#read 6, iclass 28, count 2 2006.225.08:21:59.32#ibcon#end of sib2, iclass 28, count 2 2006.225.08:21:59.32#ibcon#*mode == 0, iclass 28, count 2 2006.225.08:21:59.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.08:21:59.32#ibcon#[25=AT05-07\r\n] 2006.225.08:21:59.32#ibcon#*before write, iclass 28, count 2 2006.225.08:21:59.32#ibcon#enter sib2, iclass 28, count 2 2006.225.08:21:59.32#ibcon#flushed, iclass 28, count 2 2006.225.08:21:59.32#ibcon#about to write, iclass 28, count 2 2006.225.08:21:59.32#ibcon#wrote, iclass 28, count 2 2006.225.08:21:59.32#ibcon#about to read 3, iclass 28, count 2 2006.225.08:21:59.35#ibcon#read 3, iclass 28, count 2 2006.225.08:21:59.35#ibcon#about to read 4, iclass 28, count 2 2006.225.08:21:59.35#ibcon#read 4, iclass 28, count 2 2006.225.08:21:59.35#ibcon#about to read 5, iclass 28, count 2 2006.225.08:21:59.35#ibcon#read 5, iclass 28, count 2 2006.225.08:21:59.35#ibcon#about to read 6, iclass 28, count 2 2006.225.08:21:59.35#ibcon#read 6, iclass 28, count 2 2006.225.08:21:59.35#ibcon#end of sib2, iclass 28, count 2 2006.225.08:21:59.35#ibcon#*after write, iclass 28, count 2 2006.225.08:21:59.35#ibcon#*before return 0, iclass 28, count 2 2006.225.08:21:59.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:21:59.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:21:59.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.08:21:59.35#ibcon#ireg 7 cls_cnt 0 2006.225.08:21:59.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:21:59.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:21:59.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:21:59.47#ibcon#enter wrdev, iclass 28, count 0 2006.225.08:21:59.47#ibcon#first serial, iclass 28, count 0 2006.225.08:21:59.47#ibcon#enter sib2, iclass 28, count 0 2006.225.08:21:59.47#ibcon#flushed, iclass 28, count 0 2006.225.08:21:59.47#ibcon#about to write, iclass 28, count 0 2006.225.08:21:59.47#ibcon#wrote, iclass 28, count 0 2006.225.08:21:59.47#ibcon#about to read 3, iclass 28, count 0 2006.225.08:21:59.49#ibcon#read 3, iclass 28, count 0 2006.225.08:21:59.49#ibcon#about to read 4, iclass 28, count 0 2006.225.08:21:59.49#ibcon#read 4, iclass 28, count 0 2006.225.08:21:59.49#ibcon#about to read 5, iclass 28, count 0 2006.225.08:21:59.49#ibcon#read 5, iclass 28, count 0 2006.225.08:21:59.49#ibcon#about to read 6, iclass 28, count 0 2006.225.08:21:59.49#ibcon#read 6, iclass 28, count 0 2006.225.08:21:59.49#ibcon#end of sib2, iclass 28, count 0 2006.225.08:21:59.49#ibcon#*mode == 0, iclass 28, count 0 2006.225.08:21:59.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.08:21:59.49#ibcon#[25=USB\r\n] 2006.225.08:21:59.49#ibcon#*before write, iclass 28, count 0 2006.225.08:21:59.49#ibcon#enter sib2, iclass 28, count 0 2006.225.08:21:59.49#ibcon#flushed, iclass 28, count 0 2006.225.08:21:59.49#ibcon#about to write, iclass 28, count 0 2006.225.08:21:59.49#ibcon#wrote, iclass 28, count 0 2006.225.08:21:59.49#ibcon#about to read 3, iclass 28, count 0 2006.225.08:21:59.52#ibcon#read 3, iclass 28, count 0 2006.225.08:21:59.52#ibcon#about to read 4, iclass 28, count 0 2006.225.08:21:59.52#ibcon#read 4, iclass 28, count 0 2006.225.08:21:59.52#ibcon#about to read 5, iclass 28, count 0 2006.225.08:21:59.52#ibcon#read 5, iclass 28, count 0 2006.225.08:21:59.52#ibcon#about to read 6, iclass 28, count 0 2006.225.08:21:59.52#ibcon#read 6, iclass 28, count 0 2006.225.08:21:59.52#ibcon#end of sib2, iclass 28, count 0 2006.225.08:21:59.52#ibcon#*after write, iclass 28, count 0 2006.225.08:21:59.52#ibcon#*before return 0, iclass 28, count 0 2006.225.08:21:59.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:21:59.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:21:59.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.08:21:59.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.08:21:59.52$vc4f8/valo=6,772.99 2006.225.08:21:59.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.08:21:59.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.08:21:59.52#ibcon#ireg 17 cls_cnt 0 2006.225.08:21:59.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:21:59.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:21:59.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:21:59.52#ibcon#enter wrdev, iclass 30, count 0 2006.225.08:21:59.52#ibcon#first serial, iclass 30, count 0 2006.225.08:21:59.52#ibcon#enter sib2, iclass 30, count 0 2006.225.08:21:59.52#ibcon#flushed, iclass 30, count 0 2006.225.08:21:59.52#ibcon#about to write, iclass 30, count 0 2006.225.08:21:59.52#ibcon#wrote, iclass 30, count 0 2006.225.08:21:59.52#ibcon#about to read 3, iclass 30, count 0 2006.225.08:21:59.55#ibcon#read 3, iclass 30, count 0 2006.225.08:21:59.55#ibcon#about to read 4, iclass 30, count 0 2006.225.08:21:59.55#ibcon#read 4, iclass 30, count 0 2006.225.08:21:59.55#ibcon#about to read 5, iclass 30, count 0 2006.225.08:21:59.55#ibcon#read 5, iclass 30, count 0 2006.225.08:21:59.55#ibcon#about to read 6, iclass 30, count 0 2006.225.08:21:59.55#ibcon#read 6, iclass 30, count 0 2006.225.08:21:59.55#ibcon#end of sib2, iclass 30, count 0 2006.225.08:21:59.55#ibcon#*mode == 0, iclass 30, count 0 2006.225.08:21:59.55#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.08:21:59.55#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:21:59.55#ibcon#*before write, iclass 30, count 0 2006.225.08:21:59.55#ibcon#enter sib2, iclass 30, count 0 2006.225.08:21:59.55#ibcon#flushed, iclass 30, count 0 2006.225.08:21:59.55#ibcon#about to write, iclass 30, count 0 2006.225.08:21:59.55#ibcon#wrote, iclass 30, count 0 2006.225.08:21:59.55#ibcon#about to read 3, iclass 30, count 0 2006.225.08:21:59.59#ibcon#read 3, iclass 30, count 0 2006.225.08:21:59.59#ibcon#about to read 4, iclass 30, count 0 2006.225.08:21:59.59#ibcon#read 4, iclass 30, count 0 2006.225.08:21:59.59#ibcon#about to read 5, iclass 30, count 0 2006.225.08:21:59.59#ibcon#read 5, iclass 30, count 0 2006.225.08:21:59.59#ibcon#about to read 6, iclass 30, count 0 2006.225.08:21:59.59#ibcon#read 6, iclass 30, count 0 2006.225.08:21:59.59#ibcon#end of sib2, iclass 30, count 0 2006.225.08:21:59.59#ibcon#*after write, iclass 30, count 0 2006.225.08:21:59.59#ibcon#*before return 0, iclass 30, count 0 2006.225.08:21:59.59#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:21:59.59#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:21:59.59#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.08:21:59.59#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.08:21:59.59$vc4f8/va=6,6 2006.225.08:21:59.59#ibcon#iclass 32 nclrec 2 cls_cnt 3 2006.225.08:21:59.59#ibcon#iclass 32 iclrec 1 cls_cnt 3 2006.225.08:21:59.59#ibcon#ireg 11 cls_cnt 2 2006.225.08:21:59.59#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:21:59.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:21:59.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:21:59.64#ibcon#enter wrdev, iclass 32, count 2 2006.225.08:21:59.64#ibcon#first serial, iclass 32, count 2 2006.225.08:21:59.64#ibcon#enter sib2, iclass 32, count 2 2006.225.08:21:59.64#ibcon#flushed, iclass 32, count 2 2006.225.08:21:59.64#ibcon#about to write, iclass 32, count 2 2006.225.08:21:59.64#ibcon#wrote, iclass 32, count 2 2006.225.08:21:59.64#ibcon#about to read 3, iclass 32, count 2 2006.225.08:21:59.66#ibcon#read 3, iclass 32, count 2 2006.225.08:21:59.66#ibcon#about to read 4, iclass 32, count 2 2006.225.08:21:59.66#ibcon#read 4, iclass 32, count 2 2006.225.08:21:59.66#ibcon#about to read 5, iclass 32, count 2 2006.225.08:21:59.66#ibcon#read 5, iclass 32, count 2 2006.225.08:21:59.66#ibcon#about to read 6, iclass 32, count 2 2006.225.08:21:59.66#ibcon#read 6, iclass 32, count 2 2006.225.08:21:59.66#ibcon#end of sib2, iclass 32, count 2 2006.225.08:21:59.66#ibcon#*mode == 0, iclass 32, count 2 2006.225.08:21:59.66#ibcon#*mode == 0 && serial, iclass 32, count 2 2006.225.08:21:59.66#ibcon#[25=AT06-06\r\n] 2006.225.08:21:59.66#ibcon#*before write, iclass 32, count 2 2006.225.08:21:59.66#ibcon#enter sib2, iclass 32, count 2 2006.225.08:21:59.66#ibcon#flushed, iclass 32, count 2 2006.225.08:21:59.66#ibcon#about to write, iclass 32, count 2 2006.225.08:21:59.66#ibcon#wrote, iclass 32, count 2 2006.225.08:21:59.66#ibcon#about to read 3, iclass 32, count 2 2006.225.08:21:59.69#ibcon#read 3, iclass 32, count 2 2006.225.08:21:59.69#ibcon#about to read 4, iclass 32, count 2 2006.225.08:21:59.69#ibcon#read 4, iclass 32, count 2 2006.225.08:21:59.69#ibcon#about to read 5, iclass 32, count 2 2006.225.08:21:59.69#ibcon#read 5, iclass 32, count 2 2006.225.08:21:59.69#ibcon#about to read 6, iclass 32, count 2 2006.225.08:21:59.69#ibcon#read 6, iclass 32, count 2 2006.225.08:21:59.69#ibcon#end of sib2, iclass 32, count 2 2006.225.08:21:59.69#ibcon#*after write, iclass 32, count 2 2006.225.08:21:59.69#ibcon#*before return 0, iclass 32, count 2 2006.225.08:21:59.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:21:59.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 2 2006.225.08:21:59.69#ibcon#iclass 32 iclrec 2 cls_cnt 2 2006.225.08:21:59.69#ibcon#ireg 7 cls_cnt 0 2006.225.08:21:59.69#ibcon#before find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:21:59.81#ibcon#after find_delay mode 2, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:21:59.81#ibcon#before mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:21:59.81#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:21:59.81#ibcon#first serial, iclass 32, count 0 2006.225.08:21:59.81#ibcon#enter sib2, iclass 32, count 0 2006.225.08:21:59.81#ibcon#flushed, iclass 32, count 0 2006.225.08:21:59.81#ibcon#about to write, iclass 32, count 0 2006.225.08:21:59.81#ibcon#wrote, iclass 32, count 0 2006.225.08:21:59.81#ibcon#about to read 3, iclass 32, count 0 2006.225.08:21:59.83#ibcon#read 3, iclass 32, count 0 2006.225.08:21:59.83#ibcon#about to read 4, iclass 32, count 0 2006.225.08:21:59.83#ibcon#read 4, iclass 32, count 0 2006.225.08:21:59.83#ibcon#about to read 5, iclass 32, count 0 2006.225.08:21:59.83#ibcon#read 5, iclass 32, count 0 2006.225.08:21:59.83#ibcon#about to read 6, iclass 32, count 0 2006.225.08:21:59.83#ibcon#read 6, iclass 32, count 0 2006.225.08:21:59.83#ibcon#end of sib2, iclass 32, count 0 2006.225.08:21:59.83#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:21:59.83#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:21:59.83#ibcon#[25=USB\r\n] 2006.225.08:21:59.83#ibcon#*before write, iclass 32, count 0 2006.225.08:21:59.83#ibcon#enter sib2, iclass 32, count 0 2006.225.08:21:59.83#ibcon#flushed, iclass 32, count 0 2006.225.08:21:59.83#ibcon#about to write, iclass 32, count 0 2006.225.08:21:59.83#ibcon#wrote, iclass 32, count 0 2006.225.08:21:59.83#ibcon#about to read 3, iclass 32, count 0 2006.225.08:21:59.86#ibcon#read 3, iclass 32, count 0 2006.225.08:21:59.86#ibcon#about to read 4, iclass 32, count 0 2006.225.08:21:59.86#ibcon#read 4, iclass 32, count 0 2006.225.08:21:59.86#ibcon#about to read 5, iclass 32, count 0 2006.225.08:21:59.86#ibcon#read 5, iclass 32, count 0 2006.225.08:21:59.86#ibcon#about to read 6, iclass 32, count 0 2006.225.08:21:59.86#ibcon#read 6, iclass 32, count 0 2006.225.08:21:59.86#ibcon#end of sib2, iclass 32, count 0 2006.225.08:21:59.86#ibcon#*after write, iclass 32, count 0 2006.225.08:21:59.86#ibcon#*before return 0, iclass 32, count 0 2006.225.08:21:59.86#ibcon#after mode 2 write, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:21:59.86#ibcon#end of loop, iclass 32 iclrec 2 cls_cnt 0 2006.225.08:21:59.86#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:21:59.86#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:21:59.86$vc4f8/valo=7,832.99 2006.225.08:21:59.86#ibcon#iclass 34 nclrec 1 cls_cnt 2 2006.225.08:21:59.86#ibcon#iclass 34 iclrec 1 cls_cnt 2 2006.225.08:21:59.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:21:59.86#ibcon#before find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:21:59.86#ibcon#after find_delay mode 2, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:21:59.86#ibcon#before mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:21:59.86#ibcon#enter wrdev, iclass 34, count 0 2006.225.08:21:59.86#ibcon#first serial, iclass 34, count 0 2006.225.08:21:59.86#ibcon#enter sib2, iclass 34, count 0 2006.225.08:21:59.86#ibcon#flushed, iclass 34, count 0 2006.225.08:21:59.86#ibcon#about to write, iclass 34, count 0 2006.225.08:21:59.86#ibcon#wrote, iclass 34, count 0 2006.225.08:21:59.86#ibcon#about to read 3, iclass 34, count 0 2006.225.08:21:59.88#ibcon#read 3, iclass 34, count 0 2006.225.08:21:59.88#ibcon#about to read 4, iclass 34, count 0 2006.225.08:21:59.88#ibcon#read 4, iclass 34, count 0 2006.225.08:21:59.88#ibcon#about to read 5, iclass 34, count 0 2006.225.08:21:59.88#ibcon#read 5, iclass 34, count 0 2006.225.08:21:59.88#ibcon#about to read 6, iclass 34, count 0 2006.225.08:21:59.88#ibcon#read 6, iclass 34, count 0 2006.225.08:21:59.88#ibcon#end of sib2, iclass 34, count 0 2006.225.08:21:59.88#ibcon#*mode == 0, iclass 34, count 0 2006.225.08:21:59.88#ibcon#*mode == 0 && serial, iclass 34, count 0 2006.225.08:21:59.88#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:21:59.88#ibcon#*before write, iclass 34, count 0 2006.225.08:21:59.88#ibcon#enter sib2, iclass 34, count 0 2006.225.08:21:59.88#ibcon#flushed, iclass 34, count 0 2006.225.08:21:59.88#ibcon#about to write, iclass 34, count 0 2006.225.08:21:59.88#ibcon#wrote, iclass 34, count 0 2006.225.08:21:59.88#ibcon#about to read 3, iclass 34, count 0 2006.225.08:21:59.92#ibcon#read 3, iclass 34, count 0 2006.225.08:21:59.92#ibcon#about to read 4, iclass 34, count 0 2006.225.08:21:59.92#ibcon#read 4, iclass 34, count 0 2006.225.08:21:59.92#ibcon#about to read 5, iclass 34, count 0 2006.225.08:21:59.92#ibcon#read 5, iclass 34, count 0 2006.225.08:21:59.92#ibcon#about to read 6, iclass 34, count 0 2006.225.08:21:59.92#ibcon#read 6, iclass 34, count 0 2006.225.08:21:59.92#ibcon#end of sib2, iclass 34, count 0 2006.225.08:21:59.92#ibcon#*after write, iclass 34, count 0 2006.225.08:21:59.92#ibcon#*before return 0, iclass 34, count 0 2006.225.08:21:59.92#ibcon#after mode 2 write, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:21:59.92#ibcon#end of loop, iclass 34 iclrec 1 cls_cnt 0 2006.225.08:21:59.92#ibcon#about to clear, iclass 34 cls_cnt 0 2006.225.08:21:59.92#ibcon#cleared, iclass 34 cls_cnt 0 2006.225.08:21:59.92$vc4f8/va=7,6 2006.225.08:21:59.92#ibcon#iclass 36 nclrec 2 cls_cnt 3 2006.225.08:21:59.92#ibcon#iclass 36 iclrec 1 cls_cnt 3 2006.225.08:21:59.92#ibcon#ireg 11 cls_cnt 2 2006.225.08:21:59.92#ibcon#before find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:21:59.98#ibcon#after find_delay mode 2, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:21:59.98#ibcon#before mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:21:59.98#ibcon#enter wrdev, iclass 36, count 2 2006.225.08:21:59.98#ibcon#first serial, iclass 36, count 2 2006.225.08:21:59.98#ibcon#enter sib2, iclass 36, count 2 2006.225.08:21:59.98#ibcon#flushed, iclass 36, count 2 2006.225.08:21:59.98#ibcon#about to write, iclass 36, count 2 2006.225.08:21:59.98#ibcon#wrote, iclass 36, count 2 2006.225.08:21:59.98#ibcon#about to read 3, iclass 36, count 2 2006.225.08:22:00.00#ibcon#read 3, iclass 36, count 2 2006.225.08:22:00.00#ibcon#about to read 4, iclass 36, count 2 2006.225.08:22:00.00#ibcon#read 4, iclass 36, count 2 2006.225.08:22:00.00#ibcon#about to read 5, iclass 36, count 2 2006.225.08:22:00.00#ibcon#read 5, iclass 36, count 2 2006.225.08:22:00.00#ibcon#about to read 6, iclass 36, count 2 2006.225.08:22:00.00#ibcon#read 6, iclass 36, count 2 2006.225.08:22:00.00#ibcon#end of sib2, iclass 36, count 2 2006.225.08:22:00.00#ibcon#*mode == 0, iclass 36, count 2 2006.225.08:22:00.00#ibcon#*mode == 0 && serial, iclass 36, count 2 2006.225.08:22:00.00#ibcon#[25=AT07-06\r\n] 2006.225.08:22:00.00#ibcon#*before write, iclass 36, count 2 2006.225.08:22:00.00#ibcon#enter sib2, iclass 36, count 2 2006.225.08:22:00.00#ibcon#flushed, iclass 36, count 2 2006.225.08:22:00.00#ibcon#about to write, iclass 36, count 2 2006.225.08:22:00.00#ibcon#wrote, iclass 36, count 2 2006.225.08:22:00.00#ibcon#about to read 3, iclass 36, count 2 2006.225.08:22:00.03#ibcon#read 3, iclass 36, count 2 2006.225.08:22:00.03#ibcon#about to read 4, iclass 36, count 2 2006.225.08:22:00.03#ibcon#read 4, iclass 36, count 2 2006.225.08:22:00.03#ibcon#about to read 5, iclass 36, count 2 2006.225.08:22:00.03#ibcon#read 5, iclass 36, count 2 2006.225.08:22:00.03#ibcon#about to read 6, iclass 36, count 2 2006.225.08:22:00.03#ibcon#read 6, iclass 36, count 2 2006.225.08:22:00.03#ibcon#end of sib2, iclass 36, count 2 2006.225.08:22:00.03#ibcon#*after write, iclass 36, count 2 2006.225.08:22:00.03#ibcon#*before return 0, iclass 36, count 2 2006.225.08:22:00.03#ibcon#after mode 2 write, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:22:00.03#ibcon#end of loop, iclass 36 iclrec 1 cls_cnt 2 2006.225.08:22:00.03#ibcon#iclass 36 iclrec 2 cls_cnt 2 2006.225.08:22:00.03#ibcon#ireg 7 cls_cnt 0 2006.225.08:22:00.03#ibcon#before find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:22:00.15#ibcon#after find_delay mode 2, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:22:00.15#ibcon#before mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:22:00.15#ibcon#enter wrdev, iclass 36, count 0 2006.225.08:22:00.15#ibcon#first serial, iclass 36, count 0 2006.225.08:22:00.15#ibcon#enter sib2, iclass 36, count 0 2006.225.08:22:00.15#ibcon#flushed, iclass 36, count 0 2006.225.08:22:00.15#ibcon#about to write, iclass 36, count 0 2006.225.08:22:00.15#ibcon#wrote, iclass 36, count 0 2006.225.08:22:00.15#ibcon#about to read 3, iclass 36, count 0 2006.225.08:22:00.17#ibcon#read 3, iclass 36, count 0 2006.225.08:22:00.17#ibcon#about to read 4, iclass 36, count 0 2006.225.08:22:00.17#ibcon#read 4, iclass 36, count 0 2006.225.08:22:00.17#ibcon#about to read 5, iclass 36, count 0 2006.225.08:22:00.17#ibcon#read 5, iclass 36, count 0 2006.225.08:22:00.17#ibcon#about to read 6, iclass 36, count 0 2006.225.08:22:00.17#ibcon#read 6, iclass 36, count 0 2006.225.08:22:00.17#ibcon#end of sib2, iclass 36, count 0 2006.225.08:22:00.17#ibcon#*mode == 0, iclass 36, count 0 2006.225.08:22:00.17#ibcon#*mode == 0 && serial, iclass 36, count 0 2006.225.08:22:00.17#ibcon#[25=USB\r\n] 2006.225.08:22:00.17#ibcon#*before write, iclass 36, count 0 2006.225.08:22:00.17#ibcon#enter sib2, iclass 36, count 0 2006.225.08:22:00.17#ibcon#flushed, iclass 36, count 0 2006.225.08:22:00.17#ibcon#about to write, iclass 36, count 0 2006.225.08:22:00.17#ibcon#wrote, iclass 36, count 0 2006.225.08:22:00.17#ibcon#about to read 3, iclass 36, count 0 2006.225.08:22:00.20#ibcon#read 3, iclass 36, count 0 2006.225.08:22:00.20#ibcon#about to read 4, iclass 36, count 0 2006.225.08:22:00.20#ibcon#read 4, iclass 36, count 0 2006.225.08:22:00.20#ibcon#about to read 5, iclass 36, count 0 2006.225.08:22:00.20#ibcon#read 5, iclass 36, count 0 2006.225.08:22:00.20#ibcon#about to read 6, iclass 36, count 0 2006.225.08:22:00.20#ibcon#read 6, iclass 36, count 0 2006.225.08:22:00.20#ibcon#end of sib2, iclass 36, count 0 2006.225.08:22:00.20#ibcon#*after write, iclass 36, count 0 2006.225.08:22:00.20#ibcon#*before return 0, iclass 36, count 0 2006.225.08:22:00.20#ibcon#after mode 2 write, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:22:00.20#ibcon#end of loop, iclass 36 iclrec 2 cls_cnt 0 2006.225.08:22:00.20#ibcon#about to clear, iclass 36 cls_cnt 0 2006.225.08:22:00.20#ibcon#cleared, iclass 36 cls_cnt 0 2006.225.08:22:00.20$vc4f8/valo=8,852.99 2006.225.08:22:00.20#ibcon#iclass 38 nclrec 1 cls_cnt 2 2006.225.08:22:00.20#ibcon#iclass 38 iclrec 1 cls_cnt 2 2006.225.08:22:00.20#ibcon#ireg 17 cls_cnt 0 2006.225.08:22:00.20#ibcon#before find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:22:00.20#ibcon#after find_delay mode 2, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:22:00.20#ibcon#before mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:22:00.20#ibcon#enter wrdev, iclass 38, count 0 2006.225.08:22:00.20#ibcon#first serial, iclass 38, count 0 2006.225.08:22:00.20#ibcon#enter sib2, iclass 38, count 0 2006.225.08:22:00.20#ibcon#flushed, iclass 38, count 0 2006.225.08:22:00.20#ibcon#about to write, iclass 38, count 0 2006.225.08:22:00.20#ibcon#wrote, iclass 38, count 0 2006.225.08:22:00.20#ibcon#about to read 3, iclass 38, count 0 2006.225.08:22:00.22#ibcon#read 3, iclass 38, count 0 2006.225.08:22:00.22#ibcon#about to read 4, iclass 38, count 0 2006.225.08:22:00.22#ibcon#read 4, iclass 38, count 0 2006.225.08:22:00.22#ibcon#about to read 5, iclass 38, count 0 2006.225.08:22:00.22#ibcon#read 5, iclass 38, count 0 2006.225.08:22:00.22#ibcon#about to read 6, iclass 38, count 0 2006.225.08:22:00.22#ibcon#read 6, iclass 38, count 0 2006.225.08:22:00.22#ibcon#end of sib2, iclass 38, count 0 2006.225.08:22:00.22#ibcon#*mode == 0, iclass 38, count 0 2006.225.08:22:00.22#ibcon#*mode == 0 && serial, iclass 38, count 0 2006.225.08:22:00.22#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:22:00.22#ibcon#*before write, iclass 38, count 0 2006.225.08:22:00.22#ibcon#enter sib2, iclass 38, count 0 2006.225.08:22:00.22#ibcon#flushed, iclass 38, count 0 2006.225.08:22:00.22#ibcon#about to write, iclass 38, count 0 2006.225.08:22:00.22#ibcon#wrote, iclass 38, count 0 2006.225.08:22:00.22#ibcon#about to read 3, iclass 38, count 0 2006.225.08:22:00.26#ibcon#read 3, iclass 38, count 0 2006.225.08:22:00.26#ibcon#about to read 4, iclass 38, count 0 2006.225.08:22:00.26#ibcon#read 4, iclass 38, count 0 2006.225.08:22:00.26#ibcon#about to read 5, iclass 38, count 0 2006.225.08:22:00.26#ibcon#read 5, iclass 38, count 0 2006.225.08:22:00.26#ibcon#about to read 6, iclass 38, count 0 2006.225.08:22:00.26#ibcon#read 6, iclass 38, count 0 2006.225.08:22:00.26#ibcon#end of sib2, iclass 38, count 0 2006.225.08:22:00.26#ibcon#*after write, iclass 38, count 0 2006.225.08:22:00.26#ibcon#*before return 0, iclass 38, count 0 2006.225.08:22:00.26#ibcon#after mode 2 write, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:22:00.26#ibcon#end of loop, iclass 38 iclrec 1 cls_cnt 0 2006.225.08:22:00.26#ibcon#about to clear, iclass 38 cls_cnt 0 2006.225.08:22:00.26#ibcon#cleared, iclass 38 cls_cnt 0 2006.225.08:22:00.26$vc4f8/va=8,7 2006.225.08:22:00.26#ibcon#iclass 40 nclrec 2 cls_cnt 3 2006.225.08:22:00.26#ibcon#iclass 40 iclrec 1 cls_cnt 3 2006.225.08:22:00.26#ibcon#ireg 11 cls_cnt 2 2006.225.08:22:00.26#ibcon#before find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:22:00.32#ibcon#after find_delay mode 2, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:22:00.32#ibcon#before mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:22:00.32#ibcon#enter wrdev, iclass 40, count 2 2006.225.08:22:00.32#ibcon#first serial, iclass 40, count 2 2006.225.08:22:00.32#ibcon#enter sib2, iclass 40, count 2 2006.225.08:22:00.32#ibcon#flushed, iclass 40, count 2 2006.225.08:22:00.32#ibcon#about to write, iclass 40, count 2 2006.225.08:22:00.32#ibcon#wrote, iclass 40, count 2 2006.225.08:22:00.32#ibcon#about to read 3, iclass 40, count 2 2006.225.08:22:00.34#ibcon#read 3, iclass 40, count 2 2006.225.08:22:00.34#ibcon#about to read 4, iclass 40, count 2 2006.225.08:22:00.34#ibcon#read 4, iclass 40, count 2 2006.225.08:22:00.34#ibcon#about to read 5, iclass 40, count 2 2006.225.08:22:00.34#ibcon#read 5, iclass 40, count 2 2006.225.08:22:00.34#ibcon#about to read 6, iclass 40, count 2 2006.225.08:22:00.34#ibcon#read 6, iclass 40, count 2 2006.225.08:22:00.34#ibcon#end of sib2, iclass 40, count 2 2006.225.08:22:00.34#ibcon#*mode == 0, iclass 40, count 2 2006.225.08:22:00.34#ibcon#*mode == 0 && serial, iclass 40, count 2 2006.225.08:22:00.34#ibcon#[25=AT08-07\r\n] 2006.225.08:22:00.34#ibcon#*before write, iclass 40, count 2 2006.225.08:22:00.34#ibcon#enter sib2, iclass 40, count 2 2006.225.08:22:00.34#ibcon#flushed, iclass 40, count 2 2006.225.08:22:00.34#ibcon#about to write, iclass 40, count 2 2006.225.08:22:00.34#ibcon#wrote, iclass 40, count 2 2006.225.08:22:00.34#ibcon#about to read 3, iclass 40, count 2 2006.225.08:22:00.37#ibcon#read 3, iclass 40, count 2 2006.225.08:22:00.37#ibcon#about to read 4, iclass 40, count 2 2006.225.08:22:00.37#ibcon#read 4, iclass 40, count 2 2006.225.08:22:00.37#ibcon#about to read 5, iclass 40, count 2 2006.225.08:22:00.37#ibcon#read 5, iclass 40, count 2 2006.225.08:22:00.37#ibcon#about to read 6, iclass 40, count 2 2006.225.08:22:00.37#ibcon#read 6, iclass 40, count 2 2006.225.08:22:00.37#ibcon#end of sib2, iclass 40, count 2 2006.225.08:22:00.37#ibcon#*after write, iclass 40, count 2 2006.225.08:22:00.37#ibcon#*before return 0, iclass 40, count 2 2006.225.08:22:00.37#ibcon#after mode 2 write, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:22:00.37#ibcon#end of loop, iclass 40 iclrec 1 cls_cnt 2 2006.225.08:22:00.37#ibcon#iclass 40 iclrec 2 cls_cnt 2 2006.225.08:22:00.37#ibcon#ireg 7 cls_cnt 0 2006.225.08:22:00.37#ibcon#before find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:22:00.49#ibcon#after find_delay mode 2, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:22:00.49#ibcon#before mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:22:00.49#ibcon#enter wrdev, iclass 40, count 0 2006.225.08:22:00.49#ibcon#first serial, iclass 40, count 0 2006.225.08:22:00.49#ibcon#enter sib2, iclass 40, count 0 2006.225.08:22:00.49#ibcon#flushed, iclass 40, count 0 2006.225.08:22:00.49#ibcon#about to write, iclass 40, count 0 2006.225.08:22:00.49#ibcon#wrote, iclass 40, count 0 2006.225.08:22:00.49#ibcon#about to read 3, iclass 40, count 0 2006.225.08:22:00.51#ibcon#read 3, iclass 40, count 0 2006.225.08:22:00.51#ibcon#about to read 4, iclass 40, count 0 2006.225.08:22:00.51#ibcon#read 4, iclass 40, count 0 2006.225.08:22:00.51#ibcon#about to read 5, iclass 40, count 0 2006.225.08:22:00.51#ibcon#read 5, iclass 40, count 0 2006.225.08:22:00.51#ibcon#about to read 6, iclass 40, count 0 2006.225.08:22:00.51#ibcon#read 6, iclass 40, count 0 2006.225.08:22:00.51#ibcon#end of sib2, iclass 40, count 0 2006.225.08:22:00.51#ibcon#*mode == 0, iclass 40, count 0 2006.225.08:22:00.51#ibcon#*mode == 0 && serial, iclass 40, count 0 2006.225.08:22:00.51#ibcon#[25=USB\r\n] 2006.225.08:22:00.51#ibcon#*before write, iclass 40, count 0 2006.225.08:22:00.51#ibcon#enter sib2, iclass 40, count 0 2006.225.08:22:00.51#ibcon#flushed, iclass 40, count 0 2006.225.08:22:00.51#ibcon#about to write, iclass 40, count 0 2006.225.08:22:00.51#ibcon#wrote, iclass 40, count 0 2006.225.08:22:00.51#ibcon#about to read 3, iclass 40, count 0 2006.225.08:22:00.54#ibcon#read 3, iclass 40, count 0 2006.225.08:22:00.54#ibcon#about to read 4, iclass 40, count 0 2006.225.08:22:00.54#ibcon#read 4, iclass 40, count 0 2006.225.08:22:00.54#ibcon#about to read 5, iclass 40, count 0 2006.225.08:22:00.54#ibcon#read 5, iclass 40, count 0 2006.225.08:22:00.54#ibcon#about to read 6, iclass 40, count 0 2006.225.08:22:00.54#ibcon#read 6, iclass 40, count 0 2006.225.08:22:00.54#ibcon#end of sib2, iclass 40, count 0 2006.225.08:22:00.54#ibcon#*after write, iclass 40, count 0 2006.225.08:22:00.54#ibcon#*before return 0, iclass 40, count 0 2006.225.08:22:00.54#ibcon#after mode 2 write, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:22:00.54#ibcon#end of loop, iclass 40 iclrec 2 cls_cnt 0 2006.225.08:22:00.54#ibcon#about to clear, iclass 40 cls_cnt 0 2006.225.08:22:00.54#ibcon#cleared, iclass 40 cls_cnt 0 2006.225.08:22:00.54$vc4f8/vblo=1,632.99 2006.225.08:22:00.54#ibcon#iclass 4 nclrec 1 cls_cnt 2 2006.225.08:22:00.54#ibcon#iclass 4 iclrec 1 cls_cnt 2 2006.225.08:22:00.54#ibcon#ireg 17 cls_cnt 0 2006.225.08:22:00.54#ibcon#before find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:22:00.54#ibcon#after find_delay mode 2, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:22:00.54#ibcon#before mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:22:00.54#ibcon#enter wrdev, iclass 4, count 0 2006.225.08:22:00.54#ibcon#first serial, iclass 4, count 0 2006.225.08:22:00.54#ibcon#enter sib2, iclass 4, count 0 2006.225.08:22:00.54#ibcon#flushed, iclass 4, count 0 2006.225.08:22:00.54#ibcon#about to write, iclass 4, count 0 2006.225.08:22:00.54#ibcon#wrote, iclass 4, count 0 2006.225.08:22:00.54#ibcon#about to read 3, iclass 4, count 0 2006.225.08:22:00.56#ibcon#read 3, iclass 4, count 0 2006.225.08:22:00.56#ibcon#about to read 4, iclass 4, count 0 2006.225.08:22:00.56#ibcon#read 4, iclass 4, count 0 2006.225.08:22:00.56#ibcon#about to read 5, iclass 4, count 0 2006.225.08:22:00.56#ibcon#read 5, iclass 4, count 0 2006.225.08:22:00.56#ibcon#about to read 6, iclass 4, count 0 2006.225.08:22:00.56#ibcon#read 6, iclass 4, count 0 2006.225.08:22:00.56#ibcon#end of sib2, iclass 4, count 0 2006.225.08:22:00.56#ibcon#*mode == 0, iclass 4, count 0 2006.225.08:22:00.56#ibcon#*mode == 0 && serial, iclass 4, count 0 2006.225.08:22:00.56#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:22:00.56#ibcon#*before write, iclass 4, count 0 2006.225.08:22:00.56#ibcon#enter sib2, iclass 4, count 0 2006.225.08:22:00.56#ibcon#flushed, iclass 4, count 0 2006.225.08:22:00.56#ibcon#about to write, iclass 4, count 0 2006.225.08:22:00.56#ibcon#wrote, iclass 4, count 0 2006.225.08:22:00.56#ibcon#about to read 3, iclass 4, count 0 2006.225.08:22:00.60#ibcon#read 3, iclass 4, count 0 2006.225.08:22:00.60#ibcon#about to read 4, iclass 4, count 0 2006.225.08:22:00.60#ibcon#read 4, iclass 4, count 0 2006.225.08:22:00.60#ibcon#about to read 5, iclass 4, count 0 2006.225.08:22:00.60#ibcon#read 5, iclass 4, count 0 2006.225.08:22:00.60#ibcon#about to read 6, iclass 4, count 0 2006.225.08:22:00.60#ibcon#read 6, iclass 4, count 0 2006.225.08:22:00.60#ibcon#end of sib2, iclass 4, count 0 2006.225.08:22:00.60#ibcon#*after write, iclass 4, count 0 2006.225.08:22:00.60#ibcon#*before return 0, iclass 4, count 0 2006.225.08:22:00.60#ibcon#after mode 2 write, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:22:00.60#ibcon#end of loop, iclass 4 iclrec 1 cls_cnt 0 2006.225.08:22:00.60#ibcon#about to clear, iclass 4 cls_cnt 0 2006.225.08:22:00.60#ibcon#cleared, iclass 4 cls_cnt 0 2006.225.08:22:00.60$vc4f8/vb=1,4 2006.225.08:22:00.60#ibcon#iclass 6 nclrec 2 cls_cnt 3 2006.225.08:22:00.60#ibcon#iclass 6 iclrec 1 cls_cnt 3 2006.225.08:22:00.60#ibcon#ireg 11 cls_cnt 2 2006.225.08:22:00.60#ibcon#before find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:22:00.60#ibcon#after find_delay mode 2, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:22:00.60#ibcon#before mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:22:00.60#ibcon#enter wrdev, iclass 6, count 2 2006.225.08:22:00.60#ibcon#first serial, iclass 6, count 2 2006.225.08:22:00.60#ibcon#enter sib2, iclass 6, count 2 2006.225.08:22:00.60#ibcon#flushed, iclass 6, count 2 2006.225.08:22:00.60#ibcon#about to write, iclass 6, count 2 2006.225.08:22:00.60#ibcon#wrote, iclass 6, count 2 2006.225.08:22:00.60#ibcon#about to read 3, iclass 6, count 2 2006.225.08:22:00.62#ibcon#read 3, iclass 6, count 2 2006.225.08:22:00.62#ibcon#about to read 4, iclass 6, count 2 2006.225.08:22:00.62#ibcon#read 4, iclass 6, count 2 2006.225.08:22:00.62#ibcon#about to read 5, iclass 6, count 2 2006.225.08:22:00.62#ibcon#read 5, iclass 6, count 2 2006.225.08:22:00.62#ibcon#about to read 6, iclass 6, count 2 2006.225.08:22:00.62#ibcon#read 6, iclass 6, count 2 2006.225.08:22:00.62#ibcon#end of sib2, iclass 6, count 2 2006.225.08:22:00.62#ibcon#*mode == 0, iclass 6, count 2 2006.225.08:22:00.62#ibcon#*mode == 0 && serial, iclass 6, count 2 2006.225.08:22:00.62#ibcon#[27=AT01-04\r\n] 2006.225.08:22:00.62#ibcon#*before write, iclass 6, count 2 2006.225.08:22:00.62#ibcon#enter sib2, iclass 6, count 2 2006.225.08:22:00.62#ibcon#flushed, iclass 6, count 2 2006.225.08:22:00.62#ibcon#about to write, iclass 6, count 2 2006.225.08:22:00.62#ibcon#wrote, iclass 6, count 2 2006.225.08:22:00.62#ibcon#about to read 3, iclass 6, count 2 2006.225.08:22:00.65#ibcon#read 3, iclass 6, count 2 2006.225.08:22:00.65#ibcon#about to read 4, iclass 6, count 2 2006.225.08:22:00.65#ibcon#read 4, iclass 6, count 2 2006.225.08:22:00.65#ibcon#about to read 5, iclass 6, count 2 2006.225.08:22:00.65#ibcon#read 5, iclass 6, count 2 2006.225.08:22:00.65#ibcon#about to read 6, iclass 6, count 2 2006.225.08:22:00.65#ibcon#read 6, iclass 6, count 2 2006.225.08:22:00.65#ibcon#end of sib2, iclass 6, count 2 2006.225.08:22:00.65#ibcon#*after write, iclass 6, count 2 2006.225.08:22:00.65#ibcon#*before return 0, iclass 6, count 2 2006.225.08:22:00.65#ibcon#after mode 2 write, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:22:00.65#ibcon#end of loop, iclass 6 iclrec 1 cls_cnt 2 2006.225.08:22:00.65#ibcon#iclass 6 iclrec 2 cls_cnt 2 2006.225.08:22:00.65#ibcon#ireg 7 cls_cnt 0 2006.225.08:22:00.65#ibcon#before find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:22:00.77#ibcon#after find_delay mode 2, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:22:00.77#ibcon#before mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:22:00.77#ibcon#enter wrdev, iclass 6, count 0 2006.225.08:22:00.77#ibcon#first serial, iclass 6, count 0 2006.225.08:22:00.77#ibcon#enter sib2, iclass 6, count 0 2006.225.08:22:00.77#ibcon#flushed, iclass 6, count 0 2006.225.08:22:00.77#ibcon#about to write, iclass 6, count 0 2006.225.08:22:00.77#ibcon#wrote, iclass 6, count 0 2006.225.08:22:00.77#ibcon#about to read 3, iclass 6, count 0 2006.225.08:22:00.79#ibcon#read 3, iclass 6, count 0 2006.225.08:22:00.79#ibcon#about to read 4, iclass 6, count 0 2006.225.08:22:00.79#ibcon#read 4, iclass 6, count 0 2006.225.08:22:00.79#ibcon#about to read 5, iclass 6, count 0 2006.225.08:22:00.79#ibcon#read 5, iclass 6, count 0 2006.225.08:22:00.79#ibcon#about to read 6, iclass 6, count 0 2006.225.08:22:00.79#ibcon#read 6, iclass 6, count 0 2006.225.08:22:00.79#ibcon#end of sib2, iclass 6, count 0 2006.225.08:22:00.79#ibcon#*mode == 0, iclass 6, count 0 2006.225.08:22:00.79#ibcon#*mode == 0 && serial, iclass 6, count 0 2006.225.08:22:00.79#ibcon#[27=USB\r\n] 2006.225.08:22:00.79#ibcon#*before write, iclass 6, count 0 2006.225.08:22:00.79#ibcon#enter sib2, iclass 6, count 0 2006.225.08:22:00.79#ibcon#flushed, iclass 6, count 0 2006.225.08:22:00.79#ibcon#about to write, iclass 6, count 0 2006.225.08:22:00.79#ibcon#wrote, iclass 6, count 0 2006.225.08:22:00.79#ibcon#about to read 3, iclass 6, count 0 2006.225.08:22:00.82#ibcon#read 3, iclass 6, count 0 2006.225.08:22:00.82#ibcon#about to read 4, iclass 6, count 0 2006.225.08:22:00.82#ibcon#read 4, iclass 6, count 0 2006.225.08:22:00.82#ibcon#about to read 5, iclass 6, count 0 2006.225.08:22:00.82#ibcon#read 5, iclass 6, count 0 2006.225.08:22:00.82#ibcon#about to read 6, iclass 6, count 0 2006.225.08:22:00.82#ibcon#read 6, iclass 6, count 0 2006.225.08:22:00.82#ibcon#end of sib2, iclass 6, count 0 2006.225.08:22:00.82#ibcon#*after write, iclass 6, count 0 2006.225.08:22:00.82#ibcon#*before return 0, iclass 6, count 0 2006.225.08:22:00.82#ibcon#after mode 2 write, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:22:00.82#ibcon#end of loop, iclass 6 iclrec 2 cls_cnt 0 2006.225.08:22:00.82#ibcon#about to clear, iclass 6 cls_cnt 0 2006.225.08:22:00.82#ibcon#cleared, iclass 6 cls_cnt 0 2006.225.08:22:00.82$vc4f8/vblo=2,640.99 2006.225.08:22:00.82#ibcon#iclass 10 nclrec 1 cls_cnt 2 2006.225.08:22:00.82#ibcon#iclass 10 iclrec 1 cls_cnt 2 2006.225.08:22:00.82#ibcon#ireg 17 cls_cnt 0 2006.225.08:22:00.82#ibcon#before find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:22:00.82#ibcon#after find_delay mode 2, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:22:00.82#ibcon#before mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:22:00.82#ibcon#enter wrdev, iclass 10, count 0 2006.225.08:22:00.82#ibcon#first serial, iclass 10, count 0 2006.225.08:22:00.82#ibcon#enter sib2, iclass 10, count 0 2006.225.08:22:00.82#ibcon#flushed, iclass 10, count 0 2006.225.08:22:00.82#ibcon#about to write, iclass 10, count 0 2006.225.08:22:00.82#ibcon#wrote, iclass 10, count 0 2006.225.08:22:00.82#ibcon#about to read 3, iclass 10, count 0 2006.225.08:22:00.84#ibcon#read 3, iclass 10, count 0 2006.225.08:22:00.84#ibcon#about to read 4, iclass 10, count 0 2006.225.08:22:00.84#ibcon#read 4, iclass 10, count 0 2006.225.08:22:00.84#ibcon#about to read 5, iclass 10, count 0 2006.225.08:22:00.84#ibcon#read 5, iclass 10, count 0 2006.225.08:22:00.84#ibcon#about to read 6, iclass 10, count 0 2006.225.08:22:00.84#ibcon#read 6, iclass 10, count 0 2006.225.08:22:00.84#ibcon#end of sib2, iclass 10, count 0 2006.225.08:22:00.84#ibcon#*mode == 0, iclass 10, count 0 2006.225.08:22:00.84#ibcon#*mode == 0 && serial, iclass 10, count 0 2006.225.08:22:00.84#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:22:00.84#ibcon#*before write, iclass 10, count 0 2006.225.08:22:00.84#ibcon#enter sib2, iclass 10, count 0 2006.225.08:22:00.84#ibcon#flushed, iclass 10, count 0 2006.225.08:22:00.84#ibcon#about to write, iclass 10, count 0 2006.225.08:22:00.84#ibcon#wrote, iclass 10, count 0 2006.225.08:22:00.84#ibcon#about to read 3, iclass 10, count 0 2006.225.08:22:00.88#ibcon#read 3, iclass 10, count 0 2006.225.08:22:00.88#ibcon#about to read 4, iclass 10, count 0 2006.225.08:22:00.88#ibcon#read 4, iclass 10, count 0 2006.225.08:22:00.88#ibcon#about to read 5, iclass 10, count 0 2006.225.08:22:00.88#ibcon#read 5, iclass 10, count 0 2006.225.08:22:00.88#ibcon#about to read 6, iclass 10, count 0 2006.225.08:22:00.88#ibcon#read 6, iclass 10, count 0 2006.225.08:22:00.88#ibcon#end of sib2, iclass 10, count 0 2006.225.08:22:00.88#ibcon#*after write, iclass 10, count 0 2006.225.08:22:00.88#ibcon#*before return 0, iclass 10, count 0 2006.225.08:22:00.88#ibcon#after mode 2 write, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:22:00.88#ibcon#end of loop, iclass 10 iclrec 1 cls_cnt 0 2006.225.08:22:00.88#ibcon#about to clear, iclass 10 cls_cnt 0 2006.225.08:22:00.88#ibcon#cleared, iclass 10 cls_cnt 0 2006.225.08:22:00.88$vc4f8/vb=2,4 2006.225.08:22:00.88#ibcon#iclass 12 nclrec 2 cls_cnt 3 2006.225.08:22:00.88#ibcon#iclass 12 iclrec 1 cls_cnt 3 2006.225.08:22:00.88#ibcon#ireg 11 cls_cnt 2 2006.225.08:22:00.88#ibcon#before find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:22:00.94#ibcon#after find_delay mode 2, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:22:00.94#ibcon#before mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:22:00.94#ibcon#enter wrdev, iclass 12, count 2 2006.225.08:22:00.94#ibcon#first serial, iclass 12, count 2 2006.225.08:22:00.94#ibcon#enter sib2, iclass 12, count 2 2006.225.08:22:00.94#ibcon#flushed, iclass 12, count 2 2006.225.08:22:00.94#ibcon#about to write, iclass 12, count 2 2006.225.08:22:00.94#ibcon#wrote, iclass 12, count 2 2006.225.08:22:00.94#ibcon#about to read 3, iclass 12, count 2 2006.225.08:22:00.96#ibcon#read 3, iclass 12, count 2 2006.225.08:22:00.96#ibcon#about to read 4, iclass 12, count 2 2006.225.08:22:00.96#ibcon#read 4, iclass 12, count 2 2006.225.08:22:00.96#ibcon#about to read 5, iclass 12, count 2 2006.225.08:22:00.96#ibcon#read 5, iclass 12, count 2 2006.225.08:22:00.96#ibcon#about to read 6, iclass 12, count 2 2006.225.08:22:00.96#ibcon#read 6, iclass 12, count 2 2006.225.08:22:00.96#ibcon#end of sib2, iclass 12, count 2 2006.225.08:22:00.96#ibcon#*mode == 0, iclass 12, count 2 2006.225.08:22:00.96#ibcon#*mode == 0 && serial, iclass 12, count 2 2006.225.08:22:00.96#ibcon#[27=AT02-04\r\n] 2006.225.08:22:00.96#ibcon#*before write, iclass 12, count 2 2006.225.08:22:00.96#ibcon#enter sib2, iclass 12, count 2 2006.225.08:22:00.96#ibcon#flushed, iclass 12, count 2 2006.225.08:22:00.96#ibcon#about to write, iclass 12, count 2 2006.225.08:22:00.96#ibcon#wrote, iclass 12, count 2 2006.225.08:22:00.96#ibcon#about to read 3, iclass 12, count 2 2006.225.08:22:00.99#ibcon#read 3, iclass 12, count 2 2006.225.08:22:00.99#ibcon#about to read 4, iclass 12, count 2 2006.225.08:22:00.99#ibcon#read 4, iclass 12, count 2 2006.225.08:22:00.99#ibcon#about to read 5, iclass 12, count 2 2006.225.08:22:00.99#ibcon#read 5, iclass 12, count 2 2006.225.08:22:00.99#ibcon#about to read 6, iclass 12, count 2 2006.225.08:22:00.99#ibcon#read 6, iclass 12, count 2 2006.225.08:22:00.99#ibcon#end of sib2, iclass 12, count 2 2006.225.08:22:00.99#ibcon#*after write, iclass 12, count 2 2006.225.08:22:00.99#ibcon#*before return 0, iclass 12, count 2 2006.225.08:22:00.99#ibcon#after mode 2 write, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:22:00.99#ibcon#end of loop, iclass 12 iclrec 1 cls_cnt 2 2006.225.08:22:00.99#ibcon#iclass 12 iclrec 2 cls_cnt 2 2006.225.08:22:00.99#ibcon#ireg 7 cls_cnt 0 2006.225.08:22:00.99#ibcon#before find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:22:01.11#ibcon#after find_delay mode 2, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:22:01.11#ibcon#before mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:22:01.11#ibcon#enter wrdev, iclass 12, count 0 2006.225.08:22:01.11#ibcon#first serial, iclass 12, count 0 2006.225.08:22:01.11#ibcon#enter sib2, iclass 12, count 0 2006.225.08:22:01.11#ibcon#flushed, iclass 12, count 0 2006.225.08:22:01.11#ibcon#about to write, iclass 12, count 0 2006.225.08:22:01.11#ibcon#wrote, iclass 12, count 0 2006.225.08:22:01.11#ibcon#about to read 3, iclass 12, count 0 2006.225.08:22:01.13#ibcon#read 3, iclass 12, count 0 2006.225.08:22:01.13#ibcon#about to read 4, iclass 12, count 0 2006.225.08:22:01.13#ibcon#read 4, iclass 12, count 0 2006.225.08:22:01.13#ibcon#about to read 5, iclass 12, count 0 2006.225.08:22:01.13#ibcon#read 5, iclass 12, count 0 2006.225.08:22:01.13#ibcon#about to read 6, iclass 12, count 0 2006.225.08:22:01.13#ibcon#read 6, iclass 12, count 0 2006.225.08:22:01.13#ibcon#end of sib2, iclass 12, count 0 2006.225.08:22:01.13#ibcon#*mode == 0, iclass 12, count 0 2006.225.08:22:01.13#ibcon#*mode == 0 && serial, iclass 12, count 0 2006.225.08:22:01.13#ibcon#[27=USB\r\n] 2006.225.08:22:01.13#ibcon#*before write, iclass 12, count 0 2006.225.08:22:01.13#ibcon#enter sib2, iclass 12, count 0 2006.225.08:22:01.13#ibcon#flushed, iclass 12, count 0 2006.225.08:22:01.13#ibcon#about to write, iclass 12, count 0 2006.225.08:22:01.13#ibcon#wrote, iclass 12, count 0 2006.225.08:22:01.13#ibcon#about to read 3, iclass 12, count 0 2006.225.08:22:01.16#ibcon#read 3, iclass 12, count 0 2006.225.08:22:01.16#ibcon#about to read 4, iclass 12, count 0 2006.225.08:22:01.16#ibcon#read 4, iclass 12, count 0 2006.225.08:22:01.16#ibcon#about to read 5, iclass 12, count 0 2006.225.08:22:01.16#ibcon#read 5, iclass 12, count 0 2006.225.08:22:01.16#ibcon#about to read 6, iclass 12, count 0 2006.225.08:22:01.16#ibcon#read 6, iclass 12, count 0 2006.225.08:22:01.16#ibcon#end of sib2, iclass 12, count 0 2006.225.08:22:01.16#ibcon#*after write, iclass 12, count 0 2006.225.08:22:01.16#ibcon#*before return 0, iclass 12, count 0 2006.225.08:22:01.16#ibcon#after mode 2 write, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:22:01.16#ibcon#end of loop, iclass 12 iclrec 2 cls_cnt 0 2006.225.08:22:01.16#ibcon#about to clear, iclass 12 cls_cnt 0 2006.225.08:22:01.16#ibcon#cleared, iclass 12 cls_cnt 0 2006.225.08:22:01.16$vc4f8/vblo=3,656.99 2006.225.08:22:01.16#ibcon#iclass 14 nclrec 1 cls_cnt 2 2006.225.08:22:01.16#ibcon#iclass 14 iclrec 1 cls_cnt 2 2006.225.08:22:01.16#ibcon#ireg 17 cls_cnt 0 2006.225.08:22:01.16#ibcon#before find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:22:01.16#ibcon#after find_delay mode 2, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:22:01.16#ibcon#before mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:22:01.16#ibcon#enter wrdev, iclass 14, count 0 2006.225.08:22:01.16#ibcon#first serial, iclass 14, count 0 2006.225.08:22:01.16#ibcon#enter sib2, iclass 14, count 0 2006.225.08:22:01.16#ibcon#flushed, iclass 14, count 0 2006.225.08:22:01.16#ibcon#about to write, iclass 14, count 0 2006.225.08:22:01.16#ibcon#wrote, iclass 14, count 0 2006.225.08:22:01.16#ibcon#about to read 3, iclass 14, count 0 2006.225.08:22:01.18#ibcon#read 3, iclass 14, count 0 2006.225.08:22:01.18#ibcon#about to read 4, iclass 14, count 0 2006.225.08:22:01.18#ibcon#read 4, iclass 14, count 0 2006.225.08:22:01.18#ibcon#about to read 5, iclass 14, count 0 2006.225.08:22:01.18#ibcon#read 5, iclass 14, count 0 2006.225.08:22:01.18#ibcon#about to read 6, iclass 14, count 0 2006.225.08:22:01.18#ibcon#read 6, iclass 14, count 0 2006.225.08:22:01.18#ibcon#end of sib2, iclass 14, count 0 2006.225.08:22:01.18#ibcon#*mode == 0, iclass 14, count 0 2006.225.08:22:01.18#ibcon#*mode == 0 && serial, iclass 14, count 0 2006.225.08:22:01.18#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:22:01.18#ibcon#*before write, iclass 14, count 0 2006.225.08:22:01.18#ibcon#enter sib2, iclass 14, count 0 2006.225.08:22:01.18#ibcon#flushed, iclass 14, count 0 2006.225.08:22:01.18#ibcon#about to write, iclass 14, count 0 2006.225.08:22:01.18#ibcon#wrote, iclass 14, count 0 2006.225.08:22:01.18#ibcon#about to read 3, iclass 14, count 0 2006.225.08:22:01.22#ibcon#read 3, iclass 14, count 0 2006.225.08:22:01.22#ibcon#about to read 4, iclass 14, count 0 2006.225.08:22:01.22#ibcon#read 4, iclass 14, count 0 2006.225.08:22:01.22#ibcon#about to read 5, iclass 14, count 0 2006.225.08:22:01.22#ibcon#read 5, iclass 14, count 0 2006.225.08:22:01.22#ibcon#about to read 6, iclass 14, count 0 2006.225.08:22:01.22#ibcon#read 6, iclass 14, count 0 2006.225.08:22:01.22#ibcon#end of sib2, iclass 14, count 0 2006.225.08:22:01.22#ibcon#*after write, iclass 14, count 0 2006.225.08:22:01.22#ibcon#*before return 0, iclass 14, count 0 2006.225.08:22:01.22#ibcon#after mode 2 write, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:22:01.22#ibcon#end of loop, iclass 14 iclrec 1 cls_cnt 0 2006.225.08:22:01.22#ibcon#about to clear, iclass 14 cls_cnt 0 2006.225.08:22:01.22#ibcon#cleared, iclass 14 cls_cnt 0 2006.225.08:22:01.22$vc4f8/vb=3,4 2006.225.08:22:01.22#ibcon#iclass 16 nclrec 2 cls_cnt 3 2006.225.08:22:01.22#ibcon#iclass 16 iclrec 1 cls_cnt 3 2006.225.08:22:01.22#ibcon#ireg 11 cls_cnt 2 2006.225.08:22:01.22#ibcon#before find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:22:01.28#ibcon#after find_delay mode 2, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:22:01.28#ibcon#before mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:22:01.28#ibcon#enter wrdev, iclass 16, count 2 2006.225.08:22:01.28#ibcon#first serial, iclass 16, count 2 2006.225.08:22:01.28#ibcon#enter sib2, iclass 16, count 2 2006.225.08:22:01.28#ibcon#flushed, iclass 16, count 2 2006.225.08:22:01.28#ibcon#about to write, iclass 16, count 2 2006.225.08:22:01.28#ibcon#wrote, iclass 16, count 2 2006.225.08:22:01.28#ibcon#about to read 3, iclass 16, count 2 2006.225.08:22:01.30#ibcon#read 3, iclass 16, count 2 2006.225.08:22:01.30#ibcon#about to read 4, iclass 16, count 2 2006.225.08:22:01.30#ibcon#read 4, iclass 16, count 2 2006.225.08:22:01.30#ibcon#about to read 5, iclass 16, count 2 2006.225.08:22:01.30#ibcon#read 5, iclass 16, count 2 2006.225.08:22:01.30#ibcon#about to read 6, iclass 16, count 2 2006.225.08:22:01.30#ibcon#read 6, iclass 16, count 2 2006.225.08:22:01.30#ibcon#end of sib2, iclass 16, count 2 2006.225.08:22:01.30#ibcon#*mode == 0, iclass 16, count 2 2006.225.08:22:01.30#ibcon#*mode == 0 && serial, iclass 16, count 2 2006.225.08:22:01.30#ibcon#[27=AT03-04\r\n] 2006.225.08:22:01.30#ibcon#*before write, iclass 16, count 2 2006.225.08:22:01.30#ibcon#enter sib2, iclass 16, count 2 2006.225.08:22:01.30#ibcon#flushed, iclass 16, count 2 2006.225.08:22:01.30#ibcon#about to write, iclass 16, count 2 2006.225.08:22:01.30#ibcon#wrote, iclass 16, count 2 2006.225.08:22:01.30#ibcon#about to read 3, iclass 16, count 2 2006.225.08:22:01.33#ibcon#read 3, iclass 16, count 2 2006.225.08:22:01.33#ibcon#about to read 4, iclass 16, count 2 2006.225.08:22:01.33#ibcon#read 4, iclass 16, count 2 2006.225.08:22:01.33#ibcon#about to read 5, iclass 16, count 2 2006.225.08:22:01.33#ibcon#read 5, iclass 16, count 2 2006.225.08:22:01.33#ibcon#about to read 6, iclass 16, count 2 2006.225.08:22:01.33#ibcon#read 6, iclass 16, count 2 2006.225.08:22:01.33#ibcon#end of sib2, iclass 16, count 2 2006.225.08:22:01.33#ibcon#*after write, iclass 16, count 2 2006.225.08:22:01.33#ibcon#*before return 0, iclass 16, count 2 2006.225.08:22:01.33#ibcon#after mode 2 write, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:22:01.33#ibcon#end of loop, iclass 16 iclrec 1 cls_cnt 2 2006.225.08:22:01.33#ibcon#iclass 16 iclrec 2 cls_cnt 2 2006.225.08:22:01.33#ibcon#ireg 7 cls_cnt 0 2006.225.08:22:01.33#ibcon#before find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:22:01.45#ibcon#after find_delay mode 2, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:22:01.45#ibcon#before mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:22:01.45#ibcon#enter wrdev, iclass 16, count 0 2006.225.08:22:01.45#ibcon#first serial, iclass 16, count 0 2006.225.08:22:01.45#ibcon#enter sib2, iclass 16, count 0 2006.225.08:22:01.45#ibcon#flushed, iclass 16, count 0 2006.225.08:22:01.45#ibcon#about to write, iclass 16, count 0 2006.225.08:22:01.45#ibcon#wrote, iclass 16, count 0 2006.225.08:22:01.45#ibcon#about to read 3, iclass 16, count 0 2006.225.08:22:01.47#ibcon#read 3, iclass 16, count 0 2006.225.08:22:01.47#ibcon#about to read 4, iclass 16, count 0 2006.225.08:22:01.47#ibcon#read 4, iclass 16, count 0 2006.225.08:22:01.47#ibcon#about to read 5, iclass 16, count 0 2006.225.08:22:01.47#ibcon#read 5, iclass 16, count 0 2006.225.08:22:01.47#ibcon#about to read 6, iclass 16, count 0 2006.225.08:22:01.47#ibcon#read 6, iclass 16, count 0 2006.225.08:22:01.47#ibcon#end of sib2, iclass 16, count 0 2006.225.08:22:01.47#ibcon#*mode == 0, iclass 16, count 0 2006.225.08:22:01.47#ibcon#*mode == 0 && serial, iclass 16, count 0 2006.225.08:22:01.47#ibcon#[27=USB\r\n] 2006.225.08:22:01.47#ibcon#*before write, iclass 16, count 0 2006.225.08:22:01.47#ibcon#enter sib2, iclass 16, count 0 2006.225.08:22:01.47#ibcon#flushed, iclass 16, count 0 2006.225.08:22:01.47#ibcon#about to write, iclass 16, count 0 2006.225.08:22:01.47#ibcon#wrote, iclass 16, count 0 2006.225.08:22:01.47#ibcon#about to read 3, iclass 16, count 0 2006.225.08:22:01.50#ibcon#read 3, iclass 16, count 0 2006.225.08:22:01.50#ibcon#about to read 4, iclass 16, count 0 2006.225.08:22:01.50#ibcon#read 4, iclass 16, count 0 2006.225.08:22:01.50#ibcon#about to read 5, iclass 16, count 0 2006.225.08:22:01.50#ibcon#read 5, iclass 16, count 0 2006.225.08:22:01.50#ibcon#about to read 6, iclass 16, count 0 2006.225.08:22:01.50#ibcon#read 6, iclass 16, count 0 2006.225.08:22:01.50#ibcon#end of sib2, iclass 16, count 0 2006.225.08:22:01.50#ibcon#*after write, iclass 16, count 0 2006.225.08:22:01.50#ibcon#*before return 0, iclass 16, count 0 2006.225.08:22:01.50#ibcon#after mode 2 write, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:22:01.50#ibcon#end of loop, iclass 16 iclrec 2 cls_cnt 0 2006.225.08:22:01.50#ibcon#about to clear, iclass 16 cls_cnt 0 2006.225.08:22:01.50#ibcon#cleared, iclass 16 cls_cnt 0 2006.225.08:22:01.50$vc4f8/vblo=4,712.99 2006.225.08:22:01.50#ibcon#iclass 18 nclrec 1 cls_cnt 2 2006.225.08:22:01.50#ibcon#iclass 18 iclrec 1 cls_cnt 2 2006.225.08:22:01.50#ibcon#ireg 17 cls_cnt 0 2006.225.08:22:01.50#ibcon#before find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:22:01.50#ibcon#after find_delay mode 2, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:22:01.50#ibcon#before mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:22:01.50#ibcon#enter wrdev, iclass 18, count 0 2006.225.08:22:01.50#ibcon#first serial, iclass 18, count 0 2006.225.08:22:01.50#ibcon#enter sib2, iclass 18, count 0 2006.225.08:22:01.50#ibcon#flushed, iclass 18, count 0 2006.225.08:22:01.50#ibcon#about to write, iclass 18, count 0 2006.225.08:22:01.50#ibcon#wrote, iclass 18, count 0 2006.225.08:22:01.50#ibcon#about to read 3, iclass 18, count 0 2006.225.08:22:01.52#ibcon#read 3, iclass 18, count 0 2006.225.08:22:01.52#ibcon#about to read 4, iclass 18, count 0 2006.225.08:22:01.52#ibcon#read 4, iclass 18, count 0 2006.225.08:22:01.52#ibcon#about to read 5, iclass 18, count 0 2006.225.08:22:01.52#ibcon#read 5, iclass 18, count 0 2006.225.08:22:01.52#ibcon#about to read 6, iclass 18, count 0 2006.225.08:22:01.52#ibcon#read 6, iclass 18, count 0 2006.225.08:22:01.52#ibcon#end of sib2, iclass 18, count 0 2006.225.08:22:01.52#ibcon#*mode == 0, iclass 18, count 0 2006.225.08:22:01.52#ibcon#*mode == 0 && serial, iclass 18, count 0 2006.225.08:22:01.52#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:22:01.52#ibcon#*before write, iclass 18, count 0 2006.225.08:22:01.52#ibcon#enter sib2, iclass 18, count 0 2006.225.08:22:01.52#ibcon#flushed, iclass 18, count 0 2006.225.08:22:01.52#ibcon#about to write, iclass 18, count 0 2006.225.08:22:01.52#ibcon#wrote, iclass 18, count 0 2006.225.08:22:01.52#ibcon#about to read 3, iclass 18, count 0 2006.225.08:22:01.56#ibcon#read 3, iclass 18, count 0 2006.225.08:22:01.56#ibcon#about to read 4, iclass 18, count 0 2006.225.08:22:01.56#ibcon#read 4, iclass 18, count 0 2006.225.08:22:01.56#ibcon#about to read 5, iclass 18, count 0 2006.225.08:22:01.56#ibcon#read 5, iclass 18, count 0 2006.225.08:22:01.56#ibcon#about to read 6, iclass 18, count 0 2006.225.08:22:01.56#ibcon#read 6, iclass 18, count 0 2006.225.08:22:01.56#ibcon#end of sib2, iclass 18, count 0 2006.225.08:22:01.56#ibcon#*after write, iclass 18, count 0 2006.225.08:22:01.56#ibcon#*before return 0, iclass 18, count 0 2006.225.08:22:01.56#ibcon#after mode 2 write, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:22:01.56#ibcon#end of loop, iclass 18 iclrec 1 cls_cnt 0 2006.225.08:22:01.56#ibcon#about to clear, iclass 18 cls_cnt 0 2006.225.08:22:01.56#ibcon#cleared, iclass 18 cls_cnt 0 2006.225.08:22:01.56$vc4f8/vb=4,4 2006.225.08:22:01.56#ibcon#iclass 20 nclrec 2 cls_cnt 3 2006.225.08:22:01.56#ibcon#iclass 20 iclrec 1 cls_cnt 3 2006.225.08:22:01.56#ibcon#ireg 11 cls_cnt 2 2006.225.08:22:01.56#ibcon#before find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:22:01.62#ibcon#after find_delay mode 2, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:22:01.62#ibcon#before mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:22:01.62#ibcon#enter wrdev, iclass 20, count 2 2006.225.08:22:01.62#ibcon#first serial, iclass 20, count 2 2006.225.08:22:01.62#ibcon#enter sib2, iclass 20, count 2 2006.225.08:22:01.62#ibcon#flushed, iclass 20, count 2 2006.225.08:22:01.62#ibcon#about to write, iclass 20, count 2 2006.225.08:22:01.62#ibcon#wrote, iclass 20, count 2 2006.225.08:22:01.62#ibcon#about to read 3, iclass 20, count 2 2006.225.08:22:01.64#ibcon#read 3, iclass 20, count 2 2006.225.08:22:01.64#ibcon#about to read 4, iclass 20, count 2 2006.225.08:22:01.64#ibcon#read 4, iclass 20, count 2 2006.225.08:22:01.64#ibcon#about to read 5, iclass 20, count 2 2006.225.08:22:01.64#ibcon#read 5, iclass 20, count 2 2006.225.08:22:01.64#ibcon#about to read 6, iclass 20, count 2 2006.225.08:22:01.64#ibcon#read 6, iclass 20, count 2 2006.225.08:22:01.64#ibcon#end of sib2, iclass 20, count 2 2006.225.08:22:01.64#ibcon#*mode == 0, iclass 20, count 2 2006.225.08:22:01.64#ibcon#*mode == 0 && serial, iclass 20, count 2 2006.225.08:22:01.64#ibcon#[27=AT04-04\r\n] 2006.225.08:22:01.64#ibcon#*before write, iclass 20, count 2 2006.225.08:22:01.64#ibcon#enter sib2, iclass 20, count 2 2006.225.08:22:01.64#ibcon#flushed, iclass 20, count 2 2006.225.08:22:01.64#ibcon#about to write, iclass 20, count 2 2006.225.08:22:01.64#ibcon#wrote, iclass 20, count 2 2006.225.08:22:01.64#ibcon#about to read 3, iclass 20, count 2 2006.225.08:22:01.67#ibcon#read 3, iclass 20, count 2 2006.225.08:22:01.67#ibcon#about to read 4, iclass 20, count 2 2006.225.08:22:01.67#ibcon#read 4, iclass 20, count 2 2006.225.08:22:01.67#ibcon#about to read 5, iclass 20, count 2 2006.225.08:22:01.67#ibcon#read 5, iclass 20, count 2 2006.225.08:22:01.67#ibcon#about to read 6, iclass 20, count 2 2006.225.08:22:01.67#ibcon#read 6, iclass 20, count 2 2006.225.08:22:01.67#ibcon#end of sib2, iclass 20, count 2 2006.225.08:22:01.67#ibcon#*after write, iclass 20, count 2 2006.225.08:22:01.67#ibcon#*before return 0, iclass 20, count 2 2006.225.08:22:01.67#ibcon#after mode 2 write, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:22:01.67#ibcon#end of loop, iclass 20 iclrec 1 cls_cnt 2 2006.225.08:22:01.67#ibcon#iclass 20 iclrec 2 cls_cnt 2 2006.225.08:22:01.67#ibcon#ireg 7 cls_cnt 0 2006.225.08:22:01.67#ibcon#before find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:22:01.79#ibcon#after find_delay mode 2, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:22:01.79#ibcon#before mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:22:01.79#ibcon#enter wrdev, iclass 20, count 0 2006.225.08:22:01.79#ibcon#first serial, iclass 20, count 0 2006.225.08:22:01.79#ibcon#enter sib2, iclass 20, count 0 2006.225.08:22:01.79#ibcon#flushed, iclass 20, count 0 2006.225.08:22:01.79#ibcon#about to write, iclass 20, count 0 2006.225.08:22:01.79#ibcon#wrote, iclass 20, count 0 2006.225.08:22:01.79#ibcon#about to read 3, iclass 20, count 0 2006.225.08:22:01.81#ibcon#read 3, iclass 20, count 0 2006.225.08:22:01.81#ibcon#about to read 4, iclass 20, count 0 2006.225.08:22:01.81#ibcon#read 4, iclass 20, count 0 2006.225.08:22:01.81#ibcon#about to read 5, iclass 20, count 0 2006.225.08:22:01.81#ibcon#read 5, iclass 20, count 0 2006.225.08:22:01.81#ibcon#about to read 6, iclass 20, count 0 2006.225.08:22:01.81#ibcon#read 6, iclass 20, count 0 2006.225.08:22:01.81#ibcon#end of sib2, iclass 20, count 0 2006.225.08:22:01.81#ibcon#*mode == 0, iclass 20, count 0 2006.225.08:22:01.81#ibcon#*mode == 0 && serial, iclass 20, count 0 2006.225.08:22:01.81#ibcon#[27=USB\r\n] 2006.225.08:22:01.81#ibcon#*before write, iclass 20, count 0 2006.225.08:22:01.81#ibcon#enter sib2, iclass 20, count 0 2006.225.08:22:01.81#ibcon#flushed, iclass 20, count 0 2006.225.08:22:01.81#ibcon#about to write, iclass 20, count 0 2006.225.08:22:01.81#ibcon#wrote, iclass 20, count 0 2006.225.08:22:01.81#ibcon#about to read 3, iclass 20, count 0 2006.225.08:22:01.84#ibcon#read 3, iclass 20, count 0 2006.225.08:22:01.84#ibcon#about to read 4, iclass 20, count 0 2006.225.08:22:01.84#ibcon#read 4, iclass 20, count 0 2006.225.08:22:01.84#ibcon#about to read 5, iclass 20, count 0 2006.225.08:22:01.84#ibcon#read 5, iclass 20, count 0 2006.225.08:22:01.84#ibcon#about to read 6, iclass 20, count 0 2006.225.08:22:01.84#ibcon#read 6, iclass 20, count 0 2006.225.08:22:01.84#ibcon#end of sib2, iclass 20, count 0 2006.225.08:22:01.84#ibcon#*after write, iclass 20, count 0 2006.225.08:22:01.84#ibcon#*before return 0, iclass 20, count 0 2006.225.08:22:01.84#ibcon#after mode 2 write, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:22:01.84#ibcon#end of loop, iclass 20 iclrec 2 cls_cnt 0 2006.225.08:22:01.84#ibcon#about to clear, iclass 20 cls_cnt 0 2006.225.08:22:01.84#ibcon#cleared, iclass 20 cls_cnt 0 2006.225.08:22:01.84$vc4f8/vblo=5,744.99 2006.225.08:22:01.84#ibcon#iclass 22 nclrec 1 cls_cnt 2 2006.225.08:22:01.84#ibcon#iclass 22 iclrec 1 cls_cnt 2 2006.225.08:22:01.84#ibcon#ireg 17 cls_cnt 0 2006.225.08:22:01.84#ibcon#before find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:22:01.84#ibcon#after find_delay mode 2, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:22:01.84#ibcon#before mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:22:01.84#ibcon#enter wrdev, iclass 22, count 0 2006.225.08:22:01.84#ibcon#first serial, iclass 22, count 0 2006.225.08:22:01.84#ibcon#enter sib2, iclass 22, count 0 2006.225.08:22:01.84#ibcon#flushed, iclass 22, count 0 2006.225.08:22:01.84#ibcon#about to write, iclass 22, count 0 2006.225.08:22:01.84#ibcon#wrote, iclass 22, count 0 2006.225.08:22:01.84#ibcon#about to read 3, iclass 22, count 0 2006.225.08:22:01.86#ibcon#read 3, iclass 22, count 0 2006.225.08:22:01.86#ibcon#about to read 4, iclass 22, count 0 2006.225.08:22:01.86#ibcon#read 4, iclass 22, count 0 2006.225.08:22:01.86#ibcon#about to read 5, iclass 22, count 0 2006.225.08:22:01.86#ibcon#read 5, iclass 22, count 0 2006.225.08:22:01.86#ibcon#about to read 6, iclass 22, count 0 2006.225.08:22:01.86#ibcon#read 6, iclass 22, count 0 2006.225.08:22:01.86#ibcon#end of sib2, iclass 22, count 0 2006.225.08:22:01.86#ibcon#*mode == 0, iclass 22, count 0 2006.225.08:22:01.86#ibcon#*mode == 0 && serial, iclass 22, count 0 2006.225.08:22:01.86#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:22:01.86#ibcon#*before write, iclass 22, count 0 2006.225.08:22:01.86#ibcon#enter sib2, iclass 22, count 0 2006.225.08:22:01.86#ibcon#flushed, iclass 22, count 0 2006.225.08:22:01.86#ibcon#about to write, iclass 22, count 0 2006.225.08:22:01.86#ibcon#wrote, iclass 22, count 0 2006.225.08:22:01.86#ibcon#about to read 3, iclass 22, count 0 2006.225.08:22:01.90#ibcon#read 3, iclass 22, count 0 2006.225.08:22:01.90#ibcon#about to read 4, iclass 22, count 0 2006.225.08:22:01.90#ibcon#read 4, iclass 22, count 0 2006.225.08:22:01.90#ibcon#about to read 5, iclass 22, count 0 2006.225.08:22:01.90#ibcon#read 5, iclass 22, count 0 2006.225.08:22:01.90#ibcon#about to read 6, iclass 22, count 0 2006.225.08:22:01.90#ibcon#read 6, iclass 22, count 0 2006.225.08:22:01.90#ibcon#end of sib2, iclass 22, count 0 2006.225.08:22:01.90#ibcon#*after write, iclass 22, count 0 2006.225.08:22:01.90#ibcon#*before return 0, iclass 22, count 0 2006.225.08:22:01.90#ibcon#after mode 2 write, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:22:01.90#ibcon#end of loop, iclass 22 iclrec 1 cls_cnt 0 2006.225.08:22:01.90#ibcon#about to clear, iclass 22 cls_cnt 0 2006.225.08:22:01.90#ibcon#cleared, iclass 22 cls_cnt 0 2006.225.08:22:01.90$vc4f8/vb=5,4 2006.225.08:22:01.90#ibcon#iclass 24 nclrec 2 cls_cnt 3 2006.225.08:22:01.90#ibcon#iclass 24 iclrec 1 cls_cnt 3 2006.225.08:22:01.90#ibcon#ireg 11 cls_cnt 2 2006.225.08:22:01.90#ibcon#before find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:22:01.96#ibcon#after find_delay mode 2, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:22:01.96#ibcon#before mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:22:01.96#ibcon#enter wrdev, iclass 24, count 2 2006.225.08:22:01.96#ibcon#first serial, iclass 24, count 2 2006.225.08:22:01.96#ibcon#enter sib2, iclass 24, count 2 2006.225.08:22:01.96#ibcon#flushed, iclass 24, count 2 2006.225.08:22:01.96#ibcon#about to write, iclass 24, count 2 2006.225.08:22:01.96#ibcon#wrote, iclass 24, count 2 2006.225.08:22:01.96#ibcon#about to read 3, iclass 24, count 2 2006.225.08:22:01.98#ibcon#read 3, iclass 24, count 2 2006.225.08:22:01.98#ibcon#about to read 4, iclass 24, count 2 2006.225.08:22:01.98#ibcon#read 4, iclass 24, count 2 2006.225.08:22:01.98#ibcon#about to read 5, iclass 24, count 2 2006.225.08:22:01.98#ibcon#read 5, iclass 24, count 2 2006.225.08:22:01.98#ibcon#about to read 6, iclass 24, count 2 2006.225.08:22:01.98#ibcon#read 6, iclass 24, count 2 2006.225.08:22:01.98#ibcon#end of sib2, iclass 24, count 2 2006.225.08:22:01.98#ibcon#*mode == 0, iclass 24, count 2 2006.225.08:22:01.98#ibcon#*mode == 0 && serial, iclass 24, count 2 2006.225.08:22:01.98#ibcon#[27=AT05-04\r\n] 2006.225.08:22:01.98#ibcon#*before write, iclass 24, count 2 2006.225.08:22:01.98#ibcon#enter sib2, iclass 24, count 2 2006.225.08:22:01.98#ibcon#flushed, iclass 24, count 2 2006.225.08:22:01.98#ibcon#about to write, iclass 24, count 2 2006.225.08:22:01.98#ibcon#wrote, iclass 24, count 2 2006.225.08:22:01.98#ibcon#about to read 3, iclass 24, count 2 2006.225.08:22:02.01#ibcon#read 3, iclass 24, count 2 2006.225.08:22:02.01#ibcon#about to read 4, iclass 24, count 2 2006.225.08:22:02.01#ibcon#read 4, iclass 24, count 2 2006.225.08:22:02.01#ibcon#about to read 5, iclass 24, count 2 2006.225.08:22:02.01#ibcon#read 5, iclass 24, count 2 2006.225.08:22:02.01#ibcon#about to read 6, iclass 24, count 2 2006.225.08:22:02.01#ibcon#read 6, iclass 24, count 2 2006.225.08:22:02.01#ibcon#end of sib2, iclass 24, count 2 2006.225.08:22:02.01#ibcon#*after write, iclass 24, count 2 2006.225.08:22:02.01#ibcon#*before return 0, iclass 24, count 2 2006.225.08:22:02.01#ibcon#after mode 2 write, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:22:02.01#ibcon#end of loop, iclass 24 iclrec 1 cls_cnt 2 2006.225.08:22:02.01#ibcon#iclass 24 iclrec 2 cls_cnt 2 2006.225.08:22:02.01#ibcon#ireg 7 cls_cnt 0 2006.225.08:22:02.01#ibcon#before find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:22:02.13#ibcon#after find_delay mode 2, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:22:02.13#ibcon#before mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:22:02.13#ibcon#enter wrdev, iclass 24, count 0 2006.225.08:22:02.13#ibcon#first serial, iclass 24, count 0 2006.225.08:22:02.13#ibcon#enter sib2, iclass 24, count 0 2006.225.08:22:02.13#ibcon#flushed, iclass 24, count 0 2006.225.08:22:02.13#ibcon#about to write, iclass 24, count 0 2006.225.08:22:02.13#ibcon#wrote, iclass 24, count 0 2006.225.08:22:02.13#ibcon#about to read 3, iclass 24, count 0 2006.225.08:22:02.15#ibcon#read 3, iclass 24, count 0 2006.225.08:22:02.15#ibcon#about to read 4, iclass 24, count 0 2006.225.08:22:02.15#ibcon#read 4, iclass 24, count 0 2006.225.08:22:02.15#ibcon#about to read 5, iclass 24, count 0 2006.225.08:22:02.15#ibcon#read 5, iclass 24, count 0 2006.225.08:22:02.15#ibcon#about to read 6, iclass 24, count 0 2006.225.08:22:02.15#ibcon#read 6, iclass 24, count 0 2006.225.08:22:02.15#ibcon#end of sib2, iclass 24, count 0 2006.225.08:22:02.15#ibcon#*mode == 0, iclass 24, count 0 2006.225.08:22:02.15#ibcon#*mode == 0 && serial, iclass 24, count 0 2006.225.08:22:02.15#ibcon#[27=USB\r\n] 2006.225.08:22:02.15#ibcon#*before write, iclass 24, count 0 2006.225.08:22:02.15#ibcon#enter sib2, iclass 24, count 0 2006.225.08:22:02.15#ibcon#flushed, iclass 24, count 0 2006.225.08:22:02.15#ibcon#about to write, iclass 24, count 0 2006.225.08:22:02.15#ibcon#wrote, iclass 24, count 0 2006.225.08:22:02.15#ibcon#about to read 3, iclass 24, count 0 2006.225.08:22:02.18#ibcon#read 3, iclass 24, count 0 2006.225.08:22:02.18#ibcon#about to read 4, iclass 24, count 0 2006.225.08:22:02.18#ibcon#read 4, iclass 24, count 0 2006.225.08:22:02.18#ibcon#about to read 5, iclass 24, count 0 2006.225.08:22:02.18#ibcon#read 5, iclass 24, count 0 2006.225.08:22:02.18#ibcon#about to read 6, iclass 24, count 0 2006.225.08:22:02.18#ibcon#read 6, iclass 24, count 0 2006.225.08:22:02.18#ibcon#end of sib2, iclass 24, count 0 2006.225.08:22:02.18#ibcon#*after write, iclass 24, count 0 2006.225.08:22:02.18#ibcon#*before return 0, iclass 24, count 0 2006.225.08:22:02.18#ibcon#after mode 2 write, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:22:02.18#ibcon#end of loop, iclass 24 iclrec 2 cls_cnt 0 2006.225.08:22:02.18#ibcon#about to clear, iclass 24 cls_cnt 0 2006.225.08:22:02.18#ibcon#cleared, iclass 24 cls_cnt 0 2006.225.08:22:02.18$vc4f8/vblo=6,752.99 2006.225.08:22:02.18#ibcon#iclass 26 nclrec 1 cls_cnt 2 2006.225.08:22:02.18#ibcon#iclass 26 iclrec 1 cls_cnt 2 2006.225.08:22:02.18#ibcon#ireg 17 cls_cnt 0 2006.225.08:22:02.18#ibcon#before find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:22:02.18#ibcon#after find_delay mode 2, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:22:02.18#ibcon#before mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:22:02.18#ibcon#enter wrdev, iclass 26, count 0 2006.225.08:22:02.18#ibcon#first serial, iclass 26, count 0 2006.225.08:22:02.18#ibcon#enter sib2, iclass 26, count 0 2006.225.08:22:02.18#ibcon#flushed, iclass 26, count 0 2006.225.08:22:02.18#ibcon#about to write, iclass 26, count 0 2006.225.08:22:02.18#ibcon#wrote, iclass 26, count 0 2006.225.08:22:02.18#ibcon#about to read 3, iclass 26, count 0 2006.225.08:22:02.20#ibcon#read 3, iclass 26, count 0 2006.225.08:22:02.20#ibcon#about to read 4, iclass 26, count 0 2006.225.08:22:02.20#ibcon#read 4, iclass 26, count 0 2006.225.08:22:02.20#ibcon#about to read 5, iclass 26, count 0 2006.225.08:22:02.20#ibcon#read 5, iclass 26, count 0 2006.225.08:22:02.20#ibcon#about to read 6, iclass 26, count 0 2006.225.08:22:02.20#ibcon#read 6, iclass 26, count 0 2006.225.08:22:02.20#ibcon#end of sib2, iclass 26, count 0 2006.225.08:22:02.20#ibcon#*mode == 0, iclass 26, count 0 2006.225.08:22:02.20#ibcon#*mode == 0 && serial, iclass 26, count 0 2006.225.08:22:02.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:22:02.20#ibcon#*before write, iclass 26, count 0 2006.225.08:22:02.20#ibcon#enter sib2, iclass 26, count 0 2006.225.08:22:02.20#ibcon#flushed, iclass 26, count 0 2006.225.08:22:02.20#ibcon#about to write, iclass 26, count 0 2006.225.08:22:02.20#ibcon#wrote, iclass 26, count 0 2006.225.08:22:02.20#ibcon#about to read 3, iclass 26, count 0 2006.225.08:22:02.24#ibcon#read 3, iclass 26, count 0 2006.225.08:22:02.24#ibcon#about to read 4, iclass 26, count 0 2006.225.08:22:02.24#ibcon#read 4, iclass 26, count 0 2006.225.08:22:02.24#ibcon#about to read 5, iclass 26, count 0 2006.225.08:22:02.24#ibcon#read 5, iclass 26, count 0 2006.225.08:22:02.24#ibcon#about to read 6, iclass 26, count 0 2006.225.08:22:02.24#ibcon#read 6, iclass 26, count 0 2006.225.08:22:02.24#ibcon#end of sib2, iclass 26, count 0 2006.225.08:22:02.24#ibcon#*after write, iclass 26, count 0 2006.225.08:22:02.24#ibcon#*before return 0, iclass 26, count 0 2006.225.08:22:02.24#ibcon#after mode 2 write, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:22:02.24#ibcon#end of loop, iclass 26 iclrec 1 cls_cnt 0 2006.225.08:22:02.24#ibcon#about to clear, iclass 26 cls_cnt 0 2006.225.08:22:02.24#ibcon#cleared, iclass 26 cls_cnt 0 2006.225.08:22:02.24$vc4f8/vb=6,4 2006.225.08:22:02.24#ibcon#iclass 28 nclrec 2 cls_cnt 3 2006.225.08:22:02.24#ibcon#iclass 28 iclrec 1 cls_cnt 3 2006.225.08:22:02.24#ibcon#ireg 11 cls_cnt 2 2006.225.08:22:02.24#ibcon#before find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:22:02.30#ibcon#after find_delay mode 2, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:22:02.30#ibcon#before mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:22:02.30#ibcon#enter wrdev, iclass 28, count 2 2006.225.08:22:02.30#ibcon#first serial, iclass 28, count 2 2006.225.08:22:02.30#ibcon#enter sib2, iclass 28, count 2 2006.225.08:22:02.30#ibcon#flushed, iclass 28, count 2 2006.225.08:22:02.30#ibcon#about to write, iclass 28, count 2 2006.225.08:22:02.30#ibcon#wrote, iclass 28, count 2 2006.225.08:22:02.30#ibcon#about to read 3, iclass 28, count 2 2006.225.08:22:02.32#ibcon#read 3, iclass 28, count 2 2006.225.08:22:02.32#ibcon#about to read 4, iclass 28, count 2 2006.225.08:22:02.32#ibcon#read 4, iclass 28, count 2 2006.225.08:22:02.32#ibcon#about to read 5, iclass 28, count 2 2006.225.08:22:02.32#ibcon#read 5, iclass 28, count 2 2006.225.08:22:02.32#ibcon#about to read 6, iclass 28, count 2 2006.225.08:22:02.32#ibcon#read 6, iclass 28, count 2 2006.225.08:22:02.32#ibcon#end of sib2, iclass 28, count 2 2006.225.08:22:02.32#ibcon#*mode == 0, iclass 28, count 2 2006.225.08:22:02.32#ibcon#*mode == 0 && serial, iclass 28, count 2 2006.225.08:22:02.32#ibcon#[27=AT06-04\r\n] 2006.225.08:22:02.32#ibcon#*before write, iclass 28, count 2 2006.225.08:22:02.32#ibcon#enter sib2, iclass 28, count 2 2006.225.08:22:02.32#ibcon#flushed, iclass 28, count 2 2006.225.08:22:02.32#ibcon#about to write, iclass 28, count 2 2006.225.08:22:02.32#ibcon#wrote, iclass 28, count 2 2006.225.08:22:02.32#ibcon#about to read 3, iclass 28, count 2 2006.225.08:22:02.35#ibcon#read 3, iclass 28, count 2 2006.225.08:22:02.35#ibcon#about to read 4, iclass 28, count 2 2006.225.08:22:02.35#ibcon#read 4, iclass 28, count 2 2006.225.08:22:02.35#ibcon#about to read 5, iclass 28, count 2 2006.225.08:22:02.35#ibcon#read 5, iclass 28, count 2 2006.225.08:22:02.35#ibcon#about to read 6, iclass 28, count 2 2006.225.08:22:02.35#ibcon#read 6, iclass 28, count 2 2006.225.08:22:02.35#ibcon#end of sib2, iclass 28, count 2 2006.225.08:22:02.35#ibcon#*after write, iclass 28, count 2 2006.225.08:22:02.35#ibcon#*before return 0, iclass 28, count 2 2006.225.08:22:02.35#ibcon#after mode 2 write, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:22:02.35#ibcon#end of loop, iclass 28 iclrec 1 cls_cnt 2 2006.225.08:22:02.35#ibcon#iclass 28 iclrec 2 cls_cnt 2 2006.225.08:22:02.35#ibcon#ireg 7 cls_cnt 0 2006.225.08:22:02.35#ibcon#before find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:22:02.47#ibcon#after find_delay mode 2, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:22:02.47#ibcon#before mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:22:02.47#ibcon#enter wrdev, iclass 28, count 0 2006.225.08:22:02.47#ibcon#first serial, iclass 28, count 0 2006.225.08:22:02.47#ibcon#enter sib2, iclass 28, count 0 2006.225.08:22:02.47#ibcon#flushed, iclass 28, count 0 2006.225.08:22:02.47#ibcon#about to write, iclass 28, count 0 2006.225.08:22:02.47#ibcon#wrote, iclass 28, count 0 2006.225.08:22:02.47#ibcon#about to read 3, iclass 28, count 0 2006.225.08:22:02.49#ibcon#read 3, iclass 28, count 0 2006.225.08:22:02.49#ibcon#about to read 4, iclass 28, count 0 2006.225.08:22:02.49#ibcon#read 4, iclass 28, count 0 2006.225.08:22:02.49#ibcon#about to read 5, iclass 28, count 0 2006.225.08:22:02.49#ibcon#read 5, iclass 28, count 0 2006.225.08:22:02.49#ibcon#about to read 6, iclass 28, count 0 2006.225.08:22:02.49#ibcon#read 6, iclass 28, count 0 2006.225.08:22:02.49#ibcon#end of sib2, iclass 28, count 0 2006.225.08:22:02.49#ibcon#*mode == 0, iclass 28, count 0 2006.225.08:22:02.49#ibcon#*mode == 0 && serial, iclass 28, count 0 2006.225.08:22:02.49#ibcon#[27=USB\r\n] 2006.225.08:22:02.49#ibcon#*before write, iclass 28, count 0 2006.225.08:22:02.49#ibcon#enter sib2, iclass 28, count 0 2006.225.08:22:02.49#ibcon#flushed, iclass 28, count 0 2006.225.08:22:02.49#ibcon#about to write, iclass 28, count 0 2006.225.08:22:02.49#ibcon#wrote, iclass 28, count 0 2006.225.08:22:02.49#ibcon#about to read 3, iclass 28, count 0 2006.225.08:22:02.52#ibcon#read 3, iclass 28, count 0 2006.225.08:22:02.52#ibcon#about to read 4, iclass 28, count 0 2006.225.08:22:02.52#ibcon#read 4, iclass 28, count 0 2006.225.08:22:02.52#ibcon#about to read 5, iclass 28, count 0 2006.225.08:22:02.52#ibcon#read 5, iclass 28, count 0 2006.225.08:22:02.52#ibcon#about to read 6, iclass 28, count 0 2006.225.08:22:02.52#ibcon#read 6, iclass 28, count 0 2006.225.08:22:02.52#ibcon#end of sib2, iclass 28, count 0 2006.225.08:22:02.52#ibcon#*after write, iclass 28, count 0 2006.225.08:22:02.52#ibcon#*before return 0, iclass 28, count 0 2006.225.08:22:02.52#ibcon#after mode 2 write, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:22:02.52#ibcon#end of loop, iclass 28 iclrec 2 cls_cnt 0 2006.225.08:22:02.52#ibcon#about to clear, iclass 28 cls_cnt 0 2006.225.08:22:02.52#ibcon#cleared, iclass 28 cls_cnt 0 2006.225.08:22:02.52$vc4f8/vabw=wide 2006.225.08:22:02.52#ibcon#iclass 30 nclrec 1 cls_cnt 2 2006.225.08:22:02.52#ibcon#iclass 30 iclrec 1 cls_cnt 2 2006.225.08:22:02.52#ibcon#ireg 8 cls_cnt 0 2006.225.08:22:02.52#ibcon#before find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:22:02.52#ibcon#after find_delay mode 2, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:22:02.52#ibcon#before mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:22:02.52#ibcon#enter wrdev, iclass 30, count 0 2006.225.08:22:02.52#ibcon#first serial, iclass 30, count 0 2006.225.08:22:02.52#ibcon#enter sib2, iclass 30, count 0 2006.225.08:22:02.52#ibcon#flushed, iclass 30, count 0 2006.225.08:22:02.52#ibcon#about to write, iclass 30, count 0 2006.225.08:22:02.52#ibcon#wrote, iclass 30, count 0 2006.225.08:22:02.52#ibcon#about to read 3, iclass 30, count 0 2006.225.08:22:02.54#ibcon#read 3, iclass 30, count 0 2006.225.08:22:02.54#ibcon#about to read 4, iclass 30, count 0 2006.225.08:22:02.54#ibcon#read 4, iclass 30, count 0 2006.225.08:22:02.54#ibcon#about to read 5, iclass 30, count 0 2006.225.08:22:02.54#ibcon#read 5, iclass 30, count 0 2006.225.08:22:02.54#ibcon#about to read 6, iclass 30, count 0 2006.225.08:22:02.54#ibcon#read 6, iclass 30, count 0 2006.225.08:22:02.54#ibcon#end of sib2, iclass 30, count 0 2006.225.08:22:02.54#ibcon#*mode == 0, iclass 30, count 0 2006.225.08:22:02.54#ibcon#*mode == 0 && serial, iclass 30, count 0 2006.225.08:22:02.54#ibcon#[25=BW32\r\n] 2006.225.08:22:02.54#ibcon#*before write, iclass 30, count 0 2006.225.08:22:02.54#ibcon#enter sib2, iclass 30, count 0 2006.225.08:22:02.54#ibcon#flushed, iclass 30, count 0 2006.225.08:22:02.54#ibcon#about to write, iclass 30, count 0 2006.225.08:22:02.54#ibcon#wrote, iclass 30, count 0 2006.225.08:22:02.54#ibcon#about to read 3, iclass 30, count 0 2006.225.08:22:02.57#ibcon#read 3, iclass 30, count 0 2006.225.08:22:02.57#ibcon#about to read 4, iclass 30, count 0 2006.225.08:22:02.57#ibcon#read 4, iclass 30, count 0 2006.225.08:22:02.57#ibcon#about to read 5, iclass 30, count 0 2006.225.08:22:02.57#ibcon#read 5, iclass 30, count 0 2006.225.08:22:02.57#ibcon#about to read 6, iclass 30, count 0 2006.225.08:22:02.57#ibcon#read 6, iclass 30, count 0 2006.225.08:22:02.57#ibcon#end of sib2, iclass 30, count 0 2006.225.08:22:02.57#ibcon#*after write, iclass 30, count 0 2006.225.08:22:02.57#ibcon#*before return 0, iclass 30, count 0 2006.225.08:22:02.57#ibcon#after mode 2 write, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:22:02.57#ibcon#end of loop, iclass 30 iclrec 1 cls_cnt 0 2006.225.08:22:02.57#ibcon#about to clear, iclass 30 cls_cnt 0 2006.225.08:22:02.57#ibcon#cleared, iclass 30 cls_cnt 0 2006.225.08:22:02.57$vc4f8/vbbw=wide 2006.225.08:22:02.57#ibcon#iclass 32 nclrec 1 cls_cnt 2 2006.225.08:22:02.57#ibcon#iclass 32 iclrec 1 cls_cnt 2 2006.225.08:22:02.57#ibcon#ireg 8 cls_cnt 0 2006.225.08:22:02.57#ibcon#before find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:22:02.64#ibcon#after find_delay mode 2, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:22:02.64#ibcon#before mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:22:02.64#ibcon#enter wrdev, iclass 32, count 0 2006.225.08:22:02.64#ibcon#first serial, iclass 32, count 0 2006.225.08:22:02.64#ibcon#enter sib2, iclass 32, count 0 2006.225.08:22:02.64#ibcon#flushed, iclass 32, count 0 2006.225.08:22:02.64#ibcon#about to write, iclass 32, count 0 2006.225.08:22:02.64#ibcon#wrote, iclass 32, count 0 2006.225.08:22:02.64#ibcon#about to read 3, iclass 32, count 0 2006.225.08:22:02.66#ibcon#read 3, iclass 32, count 0 2006.225.08:22:02.66#ibcon#about to read 4, iclass 32, count 0 2006.225.08:22:02.66#ibcon#read 4, iclass 32, count 0 2006.225.08:22:02.66#ibcon#about to read 5, iclass 32, count 0 2006.225.08:22:02.66#ibcon#read 5, iclass 32, count 0 2006.225.08:22:02.66#ibcon#about to read 6, iclass 32, count 0 2006.225.08:22:02.66#ibcon#read 6, iclass 32, count 0 2006.225.08:22:02.66#ibcon#end of sib2, iclass 32, count 0 2006.225.08:22:02.66#ibcon#*mode == 0, iclass 32, count 0 2006.225.08:22:02.66#ibcon#*mode == 0 && serial, iclass 32, count 0 2006.225.08:22:02.66#ibcon#[27=BW32\r\n] 2006.225.08:22:02.66#ibcon#*before write, iclass 32, count 0 2006.225.08:22:02.66#ibcon#enter sib2, iclass 32, count 0 2006.225.08:22:02.66#ibcon#flushed, iclass 32, count 0 2006.225.08:22:02.66#ibcon#about to write, iclass 32, count 0 2006.225.08:22:02.66#ibcon#wrote, iclass 32, count 0 2006.225.08:22:02.66#ibcon#about to read 3, iclass 32, count 0 2006.225.08:22:02.69#ibcon#read 3, iclass 32, count 0 2006.225.08:22:02.69#ibcon#about to read 4, iclass 32, count 0 2006.225.08:22:02.69#ibcon#read 4, iclass 32, count 0 2006.225.08:22:02.69#ibcon#about to read 5, iclass 32, count 0 2006.225.08:22:02.69#ibcon#read 5, iclass 32, count 0 2006.225.08:22:02.69#ibcon#about to read 6, iclass 32, count 0 2006.225.08:22:02.69#ibcon#read 6, iclass 32, count 0 2006.225.08:22:02.69#ibcon#end of sib2, iclass 32, count 0 2006.225.08:22:02.69#ibcon#*after write, iclass 32, count 0 2006.225.08:22:02.69#ibcon#*before return 0, iclass 32, count 0 2006.225.08:22:02.69#ibcon#after mode 2 write, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:22:02.69#ibcon#end of loop, iclass 32 iclrec 1 cls_cnt 0 2006.225.08:22:02.69#ibcon#about to clear, iclass 32 cls_cnt 0 2006.225.08:22:02.69#ibcon#cleared, iclass 32 cls_cnt 0 2006.225.08:22:02.69$4f8m12a/ifd4f 2006.225.08:22:02.69$ifd4f/lo= 2006.225.08:22:02.69$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:22:02.69$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:22:02.69$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:22:02.69$ifd4f/patch= 2006.225.08:22:02.69$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:22:02.69$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:22:02.69$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:22:02.69$4f8m12a/"form=m,16.000,1:2 2006.225.08:22:02.69$4f8m12a/"tpicd 2006.225.08:22:02.69$4f8m12a/echo=off 2006.225.08:22:02.69$4f8m12a/xlog=off 2006.225.08:22:02.69:!2006.225.08:24:10 2006.225.08:22:40.14#trakl#Source acquired 2006.225.08:22:42.14#flagr#flagr/antenna,acquired 2006.225.08:24:10.00:preob 2006.225.08:24:10.14/onsource/TRACKING 2006.225.08:24:10.14:!2006.225.08:24:20 2006.225.08:24:20.00:data_valid=on 2006.225.08:24:20.00:midob 2006.225.08:24:21.14/onsource/TRACKING 2006.225.08:24:21.14/wx/28.08,1003.3,76 2006.225.08:24:21.26/cable/+6.4061E-03 2006.225.08:24:22.35/va/01,08,usb,yes,28,30 2006.225.08:24:22.35/va/02,07,usb,yes,28,30 2006.225.08:24:22.35/va/03,06,usb,yes,30,30 2006.225.08:24:22.35/va/04,07,usb,yes,29,32 2006.225.08:24:22.35/va/05,07,usb,yes,31,33 2006.225.08:24:22.35/va/06,06,usb,yes,30,30 2006.225.08:24:22.35/va/07,06,usb,yes,31,31 2006.225.08:24:22.35/va/08,07,usb,yes,29,29 2006.225.08:24:22.58/valo/01,532.99,yes,locked 2006.225.08:24:22.58/valo/02,572.99,yes,locked 2006.225.08:24:22.58/valo/03,672.99,yes,locked 2006.225.08:24:22.58/valo/04,832.99,yes,locked 2006.225.08:24:22.58/valo/05,652.99,yes,locked 2006.225.08:24:22.58/valo/06,772.99,yes,locked 2006.225.08:24:22.58/valo/07,832.99,yes,locked 2006.225.08:24:22.58/valo/08,852.99,yes,locked 2006.225.08:24:23.67/vb/01,04,usb,yes,30,29 2006.225.08:24:23.67/vb/02,04,usb,yes,32,33 2006.225.08:24:23.67/vb/03,04,usb,yes,28,32 2006.225.08:24:23.67/vb/04,04,usb,yes,29,29 2006.225.08:24:23.67/vb/05,04,usb,yes,28,32 2006.225.08:24:23.67/vb/06,04,usb,yes,28,31 2006.225.08:24:23.67/vb/07,04,usb,yes,31,31 2006.225.08:24:23.67/vb/08,04,usb,yes,28,32 2006.225.08:24:23.91/vblo/01,632.99,yes,locked 2006.225.08:24:23.91/vblo/02,640.99,yes,locked 2006.225.08:24:23.91/vblo/03,656.99,yes,locked 2006.225.08:24:23.91/vblo/04,712.99,yes,locked 2006.225.08:24:23.91/vblo/05,744.99,yes,locked 2006.225.08:24:23.91/vblo/06,752.99,yes,locked 2006.225.08:24:23.91/vblo/07,734.99,yes,locked 2006.225.08:24:23.91/vblo/08,744.99,yes,locked 2006.225.08:24:24.06/vabw/8 2006.225.08:24:24.21/vbbw/8 2006.225.08:24:24.30/xfe/off,on,15.2 2006.225.08:24:24.68/ifatt/23,28,28,28 2006.225.08:24:25.08/fmout-gps/S +4.54E-07 2006.225.08:24:25.12:!2006.225.08:25:20 2006.225.08:25:20.00:data_valid=off 2006.225.08:25:20.00:postob 2006.225.08:25:20.22/cable/+6.4073E-03 2006.225.08:25:20.22/wx/28.08,1003.4,76 2006.225.08:25:21.08/fmout-gps/S +4.54E-07 2006.225.08:25:21.08:scan_name=225-0826,k06225,70 2006.225.08:25:21.08:source=1116+128,111857.30,123441.7,2000.0,ccw 2006.225.08:25:21.13#flagr#flagr/antenna,new-source 2006.225.08:25:22.13:checkk5 2006.225.08:25:22.50/chk_autoobs//k5ts1/ autoobs is running! 2006.225.08:25:22.87/chk_autoobs//k5ts2/ autoobs is running! 2006.225.08:25:23.24/chk_autoobs//k5ts3/ autoobs is running! 2006.225.08:25:23.61/chk_autoobs//k5ts4/ autoobs is running! 2006.225.08:25:23.97/chk_obsdata//k5ts1/T2250824??a.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:25:24.34/chk_obsdata//k5ts2/T2250824??b.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:25:24.71/chk_obsdata//k5ts3/T2250824??c.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:25:25.08/chk_obsdata//k5ts4/T2250824??d.dat file size is correct (nominal:480MB, actual:480MB). 2006.225.08:25:25.77/k5log//k5ts1_log_newline 2006.225.08:25:26.46/k5log//k5ts2_log_newline 2006.225.08:25:27.16/k5log//k5ts3_log_newline 2006.225.08:25:27.84/k5log//k5ts4_log_newline 2006.225.08:25:27.86/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:25:27.86:4f8m12a=3 2006.225.08:25:27.86$4f8m12a/echo=on 2006.225.08:25:27.86$4f8m12a/pcalon 2006.225.08:25:27.86$pcalon/"no phase cal control is implemented here 2006.225.08:25:27.86$4f8m12a/"tpicd=stop 2006.225.08:25:27.86$4f8m12a/vc4f8 2006.225.08:25:27.86$vc4f8/valo=1,532.99 2006.225.08:25:27.86#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.08:25:27.86#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.08:25:27.86#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:27.86#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:25:27.86#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:25:27.86#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:25:27.86#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:25:27.86#ibcon#first serial, iclass 11, count 0 2006.225.08:25:27.86#ibcon#enter sib2, iclass 11, count 0 2006.225.08:25:27.86#ibcon#flushed, iclass 11, count 0 2006.225.08:25:27.86#ibcon#about to write, iclass 11, count 0 2006.225.08:25:27.86#ibcon#wrote, iclass 11, count 0 2006.225.08:25:27.86#ibcon#about to read 3, iclass 11, count 0 2006.225.08:25:27.88#ibcon#read 3, iclass 11, count 0 2006.225.08:25:27.88#ibcon#about to read 4, iclass 11, count 0 2006.225.08:25:27.88#ibcon#read 4, iclass 11, count 0 2006.225.08:25:27.88#ibcon#about to read 5, iclass 11, count 0 2006.225.08:25:27.88#ibcon#read 5, iclass 11, count 0 2006.225.08:25:27.88#ibcon#about to read 6, iclass 11, count 0 2006.225.08:25:27.88#ibcon#read 6, iclass 11, count 0 2006.225.08:25:27.88#ibcon#end of sib2, iclass 11, count 0 2006.225.08:25:27.88#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:25:27.88#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:25:27.88#ibcon#[26=FRQ=01,532.99\r\n] 2006.225.08:25:27.88#ibcon#*before write, iclass 11, count 0 2006.225.08:25:27.88#ibcon#enter sib2, iclass 11, count 0 2006.225.08:25:27.88#ibcon#flushed, iclass 11, count 0 2006.225.08:25:27.88#ibcon#about to write, iclass 11, count 0 2006.225.08:25:27.88#ibcon#wrote, iclass 11, count 0 2006.225.08:25:27.88#ibcon#about to read 3, iclass 11, count 0 2006.225.08:25:27.93#ibcon#read 3, iclass 11, count 0 2006.225.08:25:27.93#ibcon#about to read 4, iclass 11, count 0 2006.225.08:25:27.93#ibcon#read 4, iclass 11, count 0 2006.225.08:25:27.93#ibcon#about to read 5, iclass 11, count 0 2006.225.08:25:27.93#ibcon#read 5, iclass 11, count 0 2006.225.08:25:27.93#ibcon#about to read 6, iclass 11, count 0 2006.225.08:25:27.93#ibcon#read 6, iclass 11, count 0 2006.225.08:25:27.93#ibcon#end of sib2, iclass 11, count 0 2006.225.08:25:27.93#ibcon#*after write, iclass 11, count 0 2006.225.08:25:27.93#ibcon#*before return 0, iclass 11, count 0 2006.225.08:25:27.93#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:25:27.93#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:25:27.93#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:25:27.93#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:25:27.93$vc4f8/va=1,8 2006.225.08:25:27.93#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.08:25:27.93#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.08:25:27.93#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:27.93#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:25:27.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:25:27.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:25:27.93#ibcon#enter wrdev, iclass 13, count 2 2006.225.08:25:27.93#ibcon#first serial, iclass 13, count 2 2006.225.08:25:27.93#ibcon#enter sib2, iclass 13, count 2 2006.225.08:25:27.93#ibcon#flushed, iclass 13, count 2 2006.225.08:25:27.93#ibcon#about to write, iclass 13, count 2 2006.225.08:25:27.93#ibcon#wrote, iclass 13, count 2 2006.225.08:25:27.93#ibcon#about to read 3, iclass 13, count 2 2006.225.08:25:27.95#ibcon#read 3, iclass 13, count 2 2006.225.08:25:27.95#ibcon#about to read 4, iclass 13, count 2 2006.225.08:25:27.95#ibcon#read 4, iclass 13, count 2 2006.225.08:25:27.95#ibcon#about to read 5, iclass 13, count 2 2006.225.08:25:27.95#ibcon#read 5, iclass 13, count 2 2006.225.08:25:27.95#ibcon#about to read 6, iclass 13, count 2 2006.225.08:25:27.95#ibcon#read 6, iclass 13, count 2 2006.225.08:25:27.95#ibcon#end of sib2, iclass 13, count 2 2006.225.08:25:27.95#ibcon#*mode == 0, iclass 13, count 2 2006.225.08:25:27.95#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.08:25:27.95#ibcon#[25=AT01-08\r\n] 2006.225.08:25:27.95#ibcon#*before write, iclass 13, count 2 2006.225.08:25:27.95#ibcon#enter sib2, iclass 13, count 2 2006.225.08:25:27.95#ibcon#flushed, iclass 13, count 2 2006.225.08:25:27.95#ibcon#about to write, iclass 13, count 2 2006.225.08:25:27.95#ibcon#wrote, iclass 13, count 2 2006.225.08:25:27.95#ibcon#about to read 3, iclass 13, count 2 2006.225.08:25:27.98#ibcon#read 3, iclass 13, count 2 2006.225.08:25:27.98#ibcon#about to read 4, iclass 13, count 2 2006.225.08:25:27.98#ibcon#read 4, iclass 13, count 2 2006.225.08:25:27.98#ibcon#about to read 5, iclass 13, count 2 2006.225.08:25:27.98#ibcon#read 5, iclass 13, count 2 2006.225.08:25:27.98#ibcon#about to read 6, iclass 13, count 2 2006.225.08:25:27.98#ibcon#read 6, iclass 13, count 2 2006.225.08:25:27.98#ibcon#end of sib2, iclass 13, count 2 2006.225.08:25:27.98#ibcon#*after write, iclass 13, count 2 2006.225.08:25:27.98#ibcon#*before return 0, iclass 13, count 2 2006.225.08:25:27.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:25:27.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:25:27.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.08:25:27.98#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:27.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:25:28.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:25:28.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:25:28.10#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:25:28.10#ibcon#first serial, iclass 13, count 0 2006.225.08:25:28.10#ibcon#enter sib2, iclass 13, count 0 2006.225.08:25:28.10#ibcon#flushed, iclass 13, count 0 2006.225.08:25:28.10#ibcon#about to write, iclass 13, count 0 2006.225.08:25:28.10#ibcon#wrote, iclass 13, count 0 2006.225.08:25:28.10#ibcon#about to read 3, iclass 13, count 0 2006.225.08:25:28.12#ibcon#read 3, iclass 13, count 0 2006.225.08:25:28.12#ibcon#about to read 4, iclass 13, count 0 2006.225.08:25:28.12#ibcon#read 4, iclass 13, count 0 2006.225.08:25:28.12#ibcon#about to read 5, iclass 13, count 0 2006.225.08:25:28.12#ibcon#read 5, iclass 13, count 0 2006.225.08:25:28.12#ibcon#about to read 6, iclass 13, count 0 2006.225.08:25:28.12#ibcon#read 6, iclass 13, count 0 2006.225.08:25:28.12#ibcon#end of sib2, iclass 13, count 0 2006.225.08:25:28.12#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:25:28.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:25:28.12#ibcon#[25=USB\r\n] 2006.225.08:25:28.12#ibcon#*before write, iclass 13, count 0 2006.225.08:25:28.12#ibcon#enter sib2, iclass 13, count 0 2006.225.08:25:28.12#ibcon#flushed, iclass 13, count 0 2006.225.08:25:28.12#ibcon#about to write, iclass 13, count 0 2006.225.08:25:28.12#ibcon#wrote, iclass 13, count 0 2006.225.08:25:28.12#ibcon#about to read 3, iclass 13, count 0 2006.225.08:25:28.15#ibcon#read 3, iclass 13, count 0 2006.225.08:25:28.15#ibcon#about to read 4, iclass 13, count 0 2006.225.08:25:28.15#ibcon#read 4, iclass 13, count 0 2006.225.08:25:28.15#ibcon#about to read 5, iclass 13, count 0 2006.225.08:25:28.15#ibcon#read 5, iclass 13, count 0 2006.225.08:25:28.15#ibcon#about to read 6, iclass 13, count 0 2006.225.08:25:28.15#ibcon#read 6, iclass 13, count 0 2006.225.08:25:28.15#ibcon#end of sib2, iclass 13, count 0 2006.225.08:25:28.15#ibcon#*after write, iclass 13, count 0 2006.225.08:25:28.15#ibcon#*before return 0, iclass 13, count 0 2006.225.08:25:28.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:25:28.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:25:28.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:25:28.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:25:28.15$vc4f8/valo=2,572.99 2006.225.08:25:28.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.08:25:28.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.08:25:28.15#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:28.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:25:28.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:25:28.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:25:28.15#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:25:28.15#ibcon#first serial, iclass 15, count 0 2006.225.08:25:28.15#ibcon#enter sib2, iclass 15, count 0 2006.225.08:25:28.15#ibcon#flushed, iclass 15, count 0 2006.225.08:25:28.15#ibcon#about to write, iclass 15, count 0 2006.225.08:25:28.15#ibcon#wrote, iclass 15, count 0 2006.225.08:25:28.15#ibcon#about to read 3, iclass 15, count 0 2006.225.08:25:28.18#ibcon#read 3, iclass 15, count 0 2006.225.08:25:28.18#ibcon#about to read 4, iclass 15, count 0 2006.225.08:25:28.18#ibcon#read 4, iclass 15, count 0 2006.225.08:25:28.18#ibcon#about to read 5, iclass 15, count 0 2006.225.08:25:28.18#ibcon#read 5, iclass 15, count 0 2006.225.08:25:28.18#ibcon#about to read 6, iclass 15, count 0 2006.225.08:25:28.18#ibcon#read 6, iclass 15, count 0 2006.225.08:25:28.18#ibcon#end of sib2, iclass 15, count 0 2006.225.08:25:28.18#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:25:28.18#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:25:28.18#ibcon#[26=FRQ=02,572.99\r\n] 2006.225.08:25:28.18#ibcon#*before write, iclass 15, count 0 2006.225.08:25:28.18#ibcon#enter sib2, iclass 15, count 0 2006.225.08:25:28.18#ibcon#flushed, iclass 15, count 0 2006.225.08:25:28.18#ibcon#about to write, iclass 15, count 0 2006.225.08:25:28.18#ibcon#wrote, iclass 15, count 0 2006.225.08:25:28.18#ibcon#about to read 3, iclass 15, count 0 2006.225.08:25:28.22#ibcon#read 3, iclass 15, count 0 2006.225.08:25:28.22#ibcon#about to read 4, iclass 15, count 0 2006.225.08:25:28.22#ibcon#read 4, iclass 15, count 0 2006.225.08:25:28.22#ibcon#about to read 5, iclass 15, count 0 2006.225.08:25:28.22#ibcon#read 5, iclass 15, count 0 2006.225.08:25:28.22#ibcon#about to read 6, iclass 15, count 0 2006.225.08:25:28.22#ibcon#read 6, iclass 15, count 0 2006.225.08:25:28.22#ibcon#end of sib2, iclass 15, count 0 2006.225.08:25:28.22#ibcon#*after write, iclass 15, count 0 2006.225.08:25:28.22#ibcon#*before return 0, iclass 15, count 0 2006.225.08:25:28.22#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:25:28.22#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:25:28.22#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:25:28.22#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:25:28.22$vc4f8/va=2,7 2006.225.08:25:28.22#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.08:25:28.22#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.08:25:28.22#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:28.22#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:25:28.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:25:28.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:25:28.27#ibcon#enter wrdev, iclass 17, count 2 2006.225.08:25:28.27#ibcon#first serial, iclass 17, count 2 2006.225.08:25:28.27#ibcon#enter sib2, iclass 17, count 2 2006.225.08:25:28.27#ibcon#flushed, iclass 17, count 2 2006.225.08:25:28.27#ibcon#about to write, iclass 17, count 2 2006.225.08:25:28.27#ibcon#wrote, iclass 17, count 2 2006.225.08:25:28.27#ibcon#about to read 3, iclass 17, count 2 2006.225.08:25:28.29#ibcon#read 3, iclass 17, count 2 2006.225.08:25:28.29#ibcon#about to read 4, iclass 17, count 2 2006.225.08:25:28.29#ibcon#read 4, iclass 17, count 2 2006.225.08:25:28.29#ibcon#about to read 5, iclass 17, count 2 2006.225.08:25:28.29#ibcon#read 5, iclass 17, count 2 2006.225.08:25:28.29#ibcon#about to read 6, iclass 17, count 2 2006.225.08:25:28.29#ibcon#read 6, iclass 17, count 2 2006.225.08:25:28.29#ibcon#end of sib2, iclass 17, count 2 2006.225.08:25:28.29#ibcon#*mode == 0, iclass 17, count 2 2006.225.08:25:28.29#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.08:25:28.29#ibcon#[25=AT02-07\r\n] 2006.225.08:25:28.29#ibcon#*before write, iclass 17, count 2 2006.225.08:25:28.29#ibcon#enter sib2, iclass 17, count 2 2006.225.08:25:28.29#ibcon#flushed, iclass 17, count 2 2006.225.08:25:28.29#ibcon#about to write, iclass 17, count 2 2006.225.08:25:28.29#ibcon#wrote, iclass 17, count 2 2006.225.08:25:28.29#ibcon#about to read 3, iclass 17, count 2 2006.225.08:25:28.32#ibcon#read 3, iclass 17, count 2 2006.225.08:25:28.32#ibcon#about to read 4, iclass 17, count 2 2006.225.08:25:28.32#ibcon#read 4, iclass 17, count 2 2006.225.08:25:28.32#ibcon#about to read 5, iclass 17, count 2 2006.225.08:25:28.32#ibcon#read 5, iclass 17, count 2 2006.225.08:25:28.32#ibcon#about to read 6, iclass 17, count 2 2006.225.08:25:28.32#ibcon#read 6, iclass 17, count 2 2006.225.08:25:28.32#ibcon#end of sib2, iclass 17, count 2 2006.225.08:25:28.32#ibcon#*after write, iclass 17, count 2 2006.225.08:25:28.32#ibcon#*before return 0, iclass 17, count 2 2006.225.08:25:28.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:25:28.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:25:28.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.08:25:28.32#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:28.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:25:28.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:25:28.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:25:28.44#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:25:28.44#ibcon#first serial, iclass 17, count 0 2006.225.08:25:28.44#ibcon#enter sib2, iclass 17, count 0 2006.225.08:25:28.44#ibcon#flushed, iclass 17, count 0 2006.225.08:25:28.44#ibcon#about to write, iclass 17, count 0 2006.225.08:25:28.44#ibcon#wrote, iclass 17, count 0 2006.225.08:25:28.44#ibcon#about to read 3, iclass 17, count 0 2006.225.08:25:28.46#ibcon#read 3, iclass 17, count 0 2006.225.08:25:28.46#ibcon#about to read 4, iclass 17, count 0 2006.225.08:25:28.46#ibcon#read 4, iclass 17, count 0 2006.225.08:25:28.46#ibcon#about to read 5, iclass 17, count 0 2006.225.08:25:28.46#ibcon#read 5, iclass 17, count 0 2006.225.08:25:28.46#ibcon#about to read 6, iclass 17, count 0 2006.225.08:25:28.46#ibcon#read 6, iclass 17, count 0 2006.225.08:25:28.46#ibcon#end of sib2, iclass 17, count 0 2006.225.08:25:28.46#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:25:28.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:25:28.46#ibcon#[25=USB\r\n] 2006.225.08:25:28.46#ibcon#*before write, iclass 17, count 0 2006.225.08:25:28.46#ibcon#enter sib2, iclass 17, count 0 2006.225.08:25:28.46#ibcon#flushed, iclass 17, count 0 2006.225.08:25:28.46#ibcon#about to write, iclass 17, count 0 2006.225.08:25:28.46#ibcon#wrote, iclass 17, count 0 2006.225.08:25:28.46#ibcon#about to read 3, iclass 17, count 0 2006.225.08:25:28.49#ibcon#read 3, iclass 17, count 0 2006.225.08:25:28.49#ibcon#about to read 4, iclass 17, count 0 2006.225.08:25:28.49#ibcon#read 4, iclass 17, count 0 2006.225.08:25:28.49#ibcon#about to read 5, iclass 17, count 0 2006.225.08:25:28.49#ibcon#read 5, iclass 17, count 0 2006.225.08:25:28.49#ibcon#about to read 6, iclass 17, count 0 2006.225.08:25:28.49#ibcon#read 6, iclass 17, count 0 2006.225.08:25:28.49#ibcon#end of sib2, iclass 17, count 0 2006.225.08:25:28.49#ibcon#*after write, iclass 17, count 0 2006.225.08:25:28.49#ibcon#*before return 0, iclass 17, count 0 2006.225.08:25:28.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:25:28.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:25:28.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:25:28.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:25:28.49$vc4f8/valo=3,672.99 2006.225.08:25:28.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.08:25:28.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.08:25:28.49#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:28.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:25:28.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:25:28.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:25:28.49#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:25:28.49#ibcon#first serial, iclass 19, count 0 2006.225.08:25:28.49#ibcon#enter sib2, iclass 19, count 0 2006.225.08:25:28.49#ibcon#flushed, iclass 19, count 0 2006.225.08:25:28.49#ibcon#about to write, iclass 19, count 0 2006.225.08:25:28.49#ibcon#wrote, iclass 19, count 0 2006.225.08:25:28.49#ibcon#about to read 3, iclass 19, count 0 2006.225.08:25:28.52#ibcon#read 3, iclass 19, count 0 2006.225.08:25:28.52#ibcon#about to read 4, iclass 19, count 0 2006.225.08:25:28.52#ibcon#read 4, iclass 19, count 0 2006.225.08:25:28.52#ibcon#about to read 5, iclass 19, count 0 2006.225.08:25:28.52#ibcon#read 5, iclass 19, count 0 2006.225.08:25:28.52#ibcon#about to read 6, iclass 19, count 0 2006.225.08:25:28.52#ibcon#read 6, iclass 19, count 0 2006.225.08:25:28.52#ibcon#end of sib2, iclass 19, count 0 2006.225.08:25:28.52#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:25:28.52#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:25:28.52#ibcon#[26=FRQ=03,672.99\r\n] 2006.225.08:25:28.52#ibcon#*before write, iclass 19, count 0 2006.225.08:25:28.52#ibcon#enter sib2, iclass 19, count 0 2006.225.08:25:28.52#ibcon#flushed, iclass 19, count 0 2006.225.08:25:28.52#ibcon#about to write, iclass 19, count 0 2006.225.08:25:28.52#ibcon#wrote, iclass 19, count 0 2006.225.08:25:28.52#ibcon#about to read 3, iclass 19, count 0 2006.225.08:25:28.56#ibcon#read 3, iclass 19, count 0 2006.225.08:25:28.56#ibcon#about to read 4, iclass 19, count 0 2006.225.08:25:28.56#ibcon#read 4, iclass 19, count 0 2006.225.08:25:28.56#ibcon#about to read 5, iclass 19, count 0 2006.225.08:25:28.56#ibcon#read 5, iclass 19, count 0 2006.225.08:25:28.56#ibcon#about to read 6, iclass 19, count 0 2006.225.08:25:28.56#ibcon#read 6, iclass 19, count 0 2006.225.08:25:28.56#ibcon#end of sib2, iclass 19, count 0 2006.225.08:25:28.56#ibcon#*after write, iclass 19, count 0 2006.225.08:25:28.56#ibcon#*before return 0, iclass 19, count 0 2006.225.08:25:28.56#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:25:28.56#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:25:28.56#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:25:28.56#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:25:28.56$vc4f8/va=3,6 2006.225.08:25:28.56#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.225.08:25:28.56#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.225.08:25:28.56#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:28.56#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:25:28.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:25:28.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:25:28.61#ibcon#enter wrdev, iclass 21, count 2 2006.225.08:25:28.61#ibcon#first serial, iclass 21, count 2 2006.225.08:25:28.61#ibcon#enter sib2, iclass 21, count 2 2006.225.08:25:28.61#ibcon#flushed, iclass 21, count 2 2006.225.08:25:28.61#ibcon#about to write, iclass 21, count 2 2006.225.08:25:28.61#ibcon#wrote, iclass 21, count 2 2006.225.08:25:28.61#ibcon#about to read 3, iclass 21, count 2 2006.225.08:25:28.63#ibcon#read 3, iclass 21, count 2 2006.225.08:25:28.63#ibcon#about to read 4, iclass 21, count 2 2006.225.08:25:28.63#ibcon#read 4, iclass 21, count 2 2006.225.08:25:28.63#ibcon#about to read 5, iclass 21, count 2 2006.225.08:25:28.63#ibcon#read 5, iclass 21, count 2 2006.225.08:25:28.63#ibcon#about to read 6, iclass 21, count 2 2006.225.08:25:28.63#ibcon#read 6, iclass 21, count 2 2006.225.08:25:28.63#ibcon#end of sib2, iclass 21, count 2 2006.225.08:25:28.63#ibcon#*mode == 0, iclass 21, count 2 2006.225.08:25:28.63#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.225.08:25:28.63#ibcon#[25=AT03-06\r\n] 2006.225.08:25:28.63#ibcon#*before write, iclass 21, count 2 2006.225.08:25:28.63#ibcon#enter sib2, iclass 21, count 2 2006.225.08:25:28.63#ibcon#flushed, iclass 21, count 2 2006.225.08:25:28.63#ibcon#about to write, iclass 21, count 2 2006.225.08:25:28.63#ibcon#wrote, iclass 21, count 2 2006.225.08:25:28.63#ibcon#about to read 3, iclass 21, count 2 2006.225.08:25:28.66#ibcon#read 3, iclass 21, count 2 2006.225.08:25:28.66#ibcon#about to read 4, iclass 21, count 2 2006.225.08:25:28.66#ibcon#read 4, iclass 21, count 2 2006.225.08:25:28.66#ibcon#about to read 5, iclass 21, count 2 2006.225.08:25:28.66#ibcon#read 5, iclass 21, count 2 2006.225.08:25:28.66#ibcon#about to read 6, iclass 21, count 2 2006.225.08:25:28.66#ibcon#read 6, iclass 21, count 2 2006.225.08:25:28.66#ibcon#end of sib2, iclass 21, count 2 2006.225.08:25:28.66#ibcon#*after write, iclass 21, count 2 2006.225.08:25:28.66#ibcon#*before return 0, iclass 21, count 2 2006.225.08:25:28.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:25:28.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:25:28.66#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.225.08:25:28.66#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:28.66#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:25:28.78#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:25:28.78#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:25:28.78#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:25:28.78#ibcon#first serial, iclass 21, count 0 2006.225.08:25:28.78#ibcon#enter sib2, iclass 21, count 0 2006.225.08:25:28.78#ibcon#flushed, iclass 21, count 0 2006.225.08:25:28.78#ibcon#about to write, iclass 21, count 0 2006.225.08:25:28.78#ibcon#wrote, iclass 21, count 0 2006.225.08:25:28.78#ibcon#about to read 3, iclass 21, count 0 2006.225.08:25:28.80#ibcon#read 3, iclass 21, count 0 2006.225.08:25:28.80#ibcon#about to read 4, iclass 21, count 0 2006.225.08:25:28.80#ibcon#read 4, iclass 21, count 0 2006.225.08:25:28.80#ibcon#about to read 5, iclass 21, count 0 2006.225.08:25:28.80#ibcon#read 5, iclass 21, count 0 2006.225.08:25:28.80#ibcon#about to read 6, iclass 21, count 0 2006.225.08:25:28.80#ibcon#read 6, iclass 21, count 0 2006.225.08:25:28.80#ibcon#end of sib2, iclass 21, count 0 2006.225.08:25:28.80#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:25:28.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:25:28.80#ibcon#[25=USB\r\n] 2006.225.08:25:28.80#ibcon#*before write, iclass 21, count 0 2006.225.08:25:28.80#ibcon#enter sib2, iclass 21, count 0 2006.225.08:25:28.80#ibcon#flushed, iclass 21, count 0 2006.225.08:25:28.80#ibcon#about to write, iclass 21, count 0 2006.225.08:25:28.80#ibcon#wrote, iclass 21, count 0 2006.225.08:25:28.80#ibcon#about to read 3, iclass 21, count 0 2006.225.08:25:28.83#ibcon#read 3, iclass 21, count 0 2006.225.08:25:28.83#ibcon#about to read 4, iclass 21, count 0 2006.225.08:25:28.83#ibcon#read 4, iclass 21, count 0 2006.225.08:25:28.83#ibcon#about to read 5, iclass 21, count 0 2006.225.08:25:28.83#ibcon#read 5, iclass 21, count 0 2006.225.08:25:28.83#ibcon#about to read 6, iclass 21, count 0 2006.225.08:25:28.83#ibcon#read 6, iclass 21, count 0 2006.225.08:25:28.83#ibcon#end of sib2, iclass 21, count 0 2006.225.08:25:28.83#ibcon#*after write, iclass 21, count 0 2006.225.08:25:28.83#ibcon#*before return 0, iclass 21, count 0 2006.225.08:25:28.83#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:25:28.83#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:25:28.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:25:28.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:25:28.83$vc4f8/valo=4,832.99 2006.225.08:25:28.83#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.225.08:25:28.83#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.225.08:25:28.83#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:28.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:25:28.83#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:25:28.83#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:25:28.83#ibcon#enter wrdev, iclass 23, count 0 2006.225.08:25:28.83#ibcon#first serial, iclass 23, count 0 2006.225.08:25:28.83#ibcon#enter sib2, iclass 23, count 0 2006.225.08:25:28.83#ibcon#flushed, iclass 23, count 0 2006.225.08:25:28.83#ibcon#about to write, iclass 23, count 0 2006.225.08:25:28.83#ibcon#wrote, iclass 23, count 0 2006.225.08:25:28.83#ibcon#about to read 3, iclass 23, count 0 2006.225.08:25:28.86#ibcon#read 3, iclass 23, count 0 2006.225.08:25:28.86#ibcon#about to read 4, iclass 23, count 0 2006.225.08:25:28.86#ibcon#read 4, iclass 23, count 0 2006.225.08:25:28.86#ibcon#about to read 5, iclass 23, count 0 2006.225.08:25:28.86#ibcon#read 5, iclass 23, count 0 2006.225.08:25:28.86#ibcon#about to read 6, iclass 23, count 0 2006.225.08:25:28.86#ibcon#read 6, iclass 23, count 0 2006.225.08:25:28.86#ibcon#end of sib2, iclass 23, count 0 2006.225.08:25:28.86#ibcon#*mode == 0, iclass 23, count 0 2006.225.08:25:28.86#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.08:25:28.86#ibcon#[26=FRQ=04,832.99\r\n] 2006.225.08:25:28.86#ibcon#*before write, iclass 23, count 0 2006.225.08:25:28.86#ibcon#enter sib2, iclass 23, count 0 2006.225.08:25:28.86#ibcon#flushed, iclass 23, count 0 2006.225.08:25:28.86#ibcon#about to write, iclass 23, count 0 2006.225.08:25:28.86#ibcon#wrote, iclass 23, count 0 2006.225.08:25:28.86#ibcon#about to read 3, iclass 23, count 0 2006.225.08:25:28.90#ibcon#read 3, iclass 23, count 0 2006.225.08:25:28.90#ibcon#about to read 4, iclass 23, count 0 2006.225.08:25:28.90#ibcon#read 4, iclass 23, count 0 2006.225.08:25:28.90#ibcon#about to read 5, iclass 23, count 0 2006.225.08:25:28.90#ibcon#read 5, iclass 23, count 0 2006.225.08:25:28.90#ibcon#about to read 6, iclass 23, count 0 2006.225.08:25:28.90#ibcon#read 6, iclass 23, count 0 2006.225.08:25:28.90#ibcon#end of sib2, iclass 23, count 0 2006.225.08:25:28.90#ibcon#*after write, iclass 23, count 0 2006.225.08:25:28.90#ibcon#*before return 0, iclass 23, count 0 2006.225.08:25:28.90#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:25:28.90#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:25:28.90#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.08:25:28.90#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.08:25:28.90$vc4f8/va=4,7 2006.225.08:25:28.90#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.225.08:25:28.90#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.225.08:25:28.90#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:28.90#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:25:28.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:25:28.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:25:28.95#ibcon#enter wrdev, iclass 25, count 2 2006.225.08:25:28.95#ibcon#first serial, iclass 25, count 2 2006.225.08:25:28.95#ibcon#enter sib2, iclass 25, count 2 2006.225.08:25:28.95#ibcon#flushed, iclass 25, count 2 2006.225.08:25:28.95#ibcon#about to write, iclass 25, count 2 2006.225.08:25:28.95#ibcon#wrote, iclass 25, count 2 2006.225.08:25:28.95#ibcon#about to read 3, iclass 25, count 2 2006.225.08:25:28.97#ibcon#read 3, iclass 25, count 2 2006.225.08:25:28.97#ibcon#about to read 4, iclass 25, count 2 2006.225.08:25:28.97#ibcon#read 4, iclass 25, count 2 2006.225.08:25:28.97#ibcon#about to read 5, iclass 25, count 2 2006.225.08:25:28.97#ibcon#read 5, iclass 25, count 2 2006.225.08:25:28.97#ibcon#about to read 6, iclass 25, count 2 2006.225.08:25:28.97#ibcon#read 6, iclass 25, count 2 2006.225.08:25:28.97#ibcon#end of sib2, iclass 25, count 2 2006.225.08:25:28.97#ibcon#*mode == 0, iclass 25, count 2 2006.225.08:25:28.97#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.225.08:25:28.97#ibcon#[25=AT04-07\r\n] 2006.225.08:25:28.97#ibcon#*before write, iclass 25, count 2 2006.225.08:25:28.97#ibcon#enter sib2, iclass 25, count 2 2006.225.08:25:28.97#ibcon#flushed, iclass 25, count 2 2006.225.08:25:28.97#ibcon#about to write, iclass 25, count 2 2006.225.08:25:28.97#ibcon#wrote, iclass 25, count 2 2006.225.08:25:28.97#ibcon#about to read 3, iclass 25, count 2 2006.225.08:25:29.00#ibcon#read 3, iclass 25, count 2 2006.225.08:25:29.00#ibcon#about to read 4, iclass 25, count 2 2006.225.08:25:29.00#ibcon#read 4, iclass 25, count 2 2006.225.08:25:29.00#ibcon#about to read 5, iclass 25, count 2 2006.225.08:25:29.00#ibcon#read 5, iclass 25, count 2 2006.225.08:25:29.00#ibcon#about to read 6, iclass 25, count 2 2006.225.08:25:29.00#ibcon#read 6, iclass 25, count 2 2006.225.08:25:29.00#ibcon#end of sib2, iclass 25, count 2 2006.225.08:25:29.00#ibcon#*after write, iclass 25, count 2 2006.225.08:25:29.00#ibcon#*before return 0, iclass 25, count 2 2006.225.08:25:29.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:25:29.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:25:29.00#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.225.08:25:29.00#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:29.00#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:25:29.12#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:25:29.12#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:25:29.12#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:25:29.12#ibcon#first serial, iclass 25, count 0 2006.225.08:25:29.12#ibcon#enter sib2, iclass 25, count 0 2006.225.08:25:29.12#ibcon#flushed, iclass 25, count 0 2006.225.08:25:29.12#ibcon#about to write, iclass 25, count 0 2006.225.08:25:29.12#ibcon#wrote, iclass 25, count 0 2006.225.08:25:29.12#ibcon#about to read 3, iclass 25, count 0 2006.225.08:25:29.14#ibcon#read 3, iclass 25, count 0 2006.225.08:25:29.14#ibcon#about to read 4, iclass 25, count 0 2006.225.08:25:29.14#ibcon#read 4, iclass 25, count 0 2006.225.08:25:29.14#ibcon#about to read 5, iclass 25, count 0 2006.225.08:25:29.14#ibcon#read 5, iclass 25, count 0 2006.225.08:25:29.14#ibcon#about to read 6, iclass 25, count 0 2006.225.08:25:29.14#ibcon#read 6, iclass 25, count 0 2006.225.08:25:29.14#ibcon#end of sib2, iclass 25, count 0 2006.225.08:25:29.14#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:25:29.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:25:29.14#ibcon#[25=USB\r\n] 2006.225.08:25:29.14#ibcon#*before write, iclass 25, count 0 2006.225.08:25:29.14#ibcon#enter sib2, iclass 25, count 0 2006.225.08:25:29.14#ibcon#flushed, iclass 25, count 0 2006.225.08:25:29.14#ibcon#about to write, iclass 25, count 0 2006.225.08:25:29.14#ibcon#wrote, iclass 25, count 0 2006.225.08:25:29.14#ibcon#about to read 3, iclass 25, count 0 2006.225.08:25:29.17#ibcon#read 3, iclass 25, count 0 2006.225.08:25:29.17#ibcon#about to read 4, iclass 25, count 0 2006.225.08:25:29.17#ibcon#read 4, iclass 25, count 0 2006.225.08:25:29.17#ibcon#about to read 5, iclass 25, count 0 2006.225.08:25:29.17#ibcon#read 5, iclass 25, count 0 2006.225.08:25:29.17#ibcon#about to read 6, iclass 25, count 0 2006.225.08:25:29.17#ibcon#read 6, iclass 25, count 0 2006.225.08:25:29.17#ibcon#end of sib2, iclass 25, count 0 2006.225.08:25:29.17#ibcon#*after write, iclass 25, count 0 2006.225.08:25:29.17#ibcon#*before return 0, iclass 25, count 0 2006.225.08:25:29.17#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:25:29.17#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:25:29.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:25:29.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:25:29.17$vc4f8/valo=5,652.99 2006.225.08:25:29.17#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.08:25:29.17#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.08:25:29.17#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:29.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:25:29.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:25:29.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:25:29.17#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:25:29.17#ibcon#first serial, iclass 27, count 0 2006.225.08:25:29.17#ibcon#enter sib2, iclass 27, count 0 2006.225.08:25:29.17#ibcon#flushed, iclass 27, count 0 2006.225.08:25:29.17#ibcon#about to write, iclass 27, count 0 2006.225.08:25:29.17#ibcon#wrote, iclass 27, count 0 2006.225.08:25:29.17#ibcon#about to read 3, iclass 27, count 0 2006.225.08:25:29.19#ibcon#read 3, iclass 27, count 0 2006.225.08:25:29.19#ibcon#about to read 4, iclass 27, count 0 2006.225.08:25:29.19#ibcon#read 4, iclass 27, count 0 2006.225.08:25:29.19#ibcon#about to read 5, iclass 27, count 0 2006.225.08:25:29.19#ibcon#read 5, iclass 27, count 0 2006.225.08:25:29.19#ibcon#about to read 6, iclass 27, count 0 2006.225.08:25:29.19#ibcon#read 6, iclass 27, count 0 2006.225.08:25:29.19#ibcon#end of sib2, iclass 27, count 0 2006.225.08:25:29.19#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:25:29.19#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:25:29.19#ibcon#[26=FRQ=05,652.99\r\n] 2006.225.08:25:29.19#ibcon#*before write, iclass 27, count 0 2006.225.08:25:29.19#ibcon#enter sib2, iclass 27, count 0 2006.225.08:25:29.19#ibcon#flushed, iclass 27, count 0 2006.225.08:25:29.19#ibcon#about to write, iclass 27, count 0 2006.225.08:25:29.19#ibcon#wrote, iclass 27, count 0 2006.225.08:25:29.19#ibcon#about to read 3, iclass 27, count 0 2006.225.08:25:29.23#ibcon#read 3, iclass 27, count 0 2006.225.08:25:29.23#ibcon#about to read 4, iclass 27, count 0 2006.225.08:25:29.23#ibcon#read 4, iclass 27, count 0 2006.225.08:25:29.23#ibcon#about to read 5, iclass 27, count 0 2006.225.08:25:29.23#ibcon#read 5, iclass 27, count 0 2006.225.08:25:29.23#ibcon#about to read 6, iclass 27, count 0 2006.225.08:25:29.23#ibcon#read 6, iclass 27, count 0 2006.225.08:25:29.23#ibcon#end of sib2, iclass 27, count 0 2006.225.08:25:29.23#ibcon#*after write, iclass 27, count 0 2006.225.08:25:29.23#ibcon#*before return 0, iclass 27, count 0 2006.225.08:25:29.23#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:25:29.23#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:25:29.23#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:25:29.23#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:25:29.23$vc4f8/va=5,7 2006.225.08:25:29.23#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.225.08:25:29.23#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.225.08:25:29.23#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:29.23#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:25:29.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:25:29.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:25:29.29#ibcon#enter wrdev, iclass 29, count 2 2006.225.08:25:29.29#ibcon#first serial, iclass 29, count 2 2006.225.08:25:29.29#ibcon#enter sib2, iclass 29, count 2 2006.225.08:25:29.29#ibcon#flushed, iclass 29, count 2 2006.225.08:25:29.29#ibcon#about to write, iclass 29, count 2 2006.225.08:25:29.29#ibcon#wrote, iclass 29, count 2 2006.225.08:25:29.29#ibcon#about to read 3, iclass 29, count 2 2006.225.08:25:29.31#ibcon#read 3, iclass 29, count 2 2006.225.08:25:29.31#ibcon#about to read 4, iclass 29, count 2 2006.225.08:25:29.31#ibcon#read 4, iclass 29, count 2 2006.225.08:25:29.31#ibcon#about to read 5, iclass 29, count 2 2006.225.08:25:29.31#ibcon#read 5, iclass 29, count 2 2006.225.08:25:29.31#ibcon#about to read 6, iclass 29, count 2 2006.225.08:25:29.31#ibcon#read 6, iclass 29, count 2 2006.225.08:25:29.31#ibcon#end of sib2, iclass 29, count 2 2006.225.08:25:29.31#ibcon#*mode == 0, iclass 29, count 2 2006.225.08:25:29.31#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.225.08:25:29.31#ibcon#[25=AT05-07\r\n] 2006.225.08:25:29.31#ibcon#*before write, iclass 29, count 2 2006.225.08:25:29.31#ibcon#enter sib2, iclass 29, count 2 2006.225.08:25:29.31#ibcon#flushed, iclass 29, count 2 2006.225.08:25:29.31#ibcon#about to write, iclass 29, count 2 2006.225.08:25:29.31#ibcon#wrote, iclass 29, count 2 2006.225.08:25:29.31#ibcon#about to read 3, iclass 29, count 2 2006.225.08:25:29.34#ibcon#read 3, iclass 29, count 2 2006.225.08:25:29.34#ibcon#about to read 4, iclass 29, count 2 2006.225.08:25:29.34#ibcon#read 4, iclass 29, count 2 2006.225.08:25:29.34#ibcon#about to read 5, iclass 29, count 2 2006.225.08:25:29.34#ibcon#read 5, iclass 29, count 2 2006.225.08:25:29.34#ibcon#about to read 6, iclass 29, count 2 2006.225.08:25:29.34#ibcon#read 6, iclass 29, count 2 2006.225.08:25:29.34#ibcon#end of sib2, iclass 29, count 2 2006.225.08:25:29.34#ibcon#*after write, iclass 29, count 2 2006.225.08:25:29.34#ibcon#*before return 0, iclass 29, count 2 2006.225.08:25:29.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:25:29.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:25:29.34#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.225.08:25:29.34#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:29.34#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:25:29.46#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:25:29.46#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:25:29.46#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:25:29.46#ibcon#first serial, iclass 29, count 0 2006.225.08:25:29.46#ibcon#enter sib2, iclass 29, count 0 2006.225.08:25:29.46#ibcon#flushed, iclass 29, count 0 2006.225.08:25:29.46#ibcon#about to write, iclass 29, count 0 2006.225.08:25:29.46#ibcon#wrote, iclass 29, count 0 2006.225.08:25:29.46#ibcon#about to read 3, iclass 29, count 0 2006.225.08:25:29.48#ibcon#read 3, iclass 29, count 0 2006.225.08:25:29.48#ibcon#about to read 4, iclass 29, count 0 2006.225.08:25:29.48#ibcon#read 4, iclass 29, count 0 2006.225.08:25:29.48#ibcon#about to read 5, iclass 29, count 0 2006.225.08:25:29.48#ibcon#read 5, iclass 29, count 0 2006.225.08:25:29.48#ibcon#about to read 6, iclass 29, count 0 2006.225.08:25:29.48#ibcon#read 6, iclass 29, count 0 2006.225.08:25:29.48#ibcon#end of sib2, iclass 29, count 0 2006.225.08:25:29.48#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:25:29.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:25:29.48#ibcon#[25=USB\r\n] 2006.225.08:25:29.48#ibcon#*before write, iclass 29, count 0 2006.225.08:25:29.48#ibcon#enter sib2, iclass 29, count 0 2006.225.08:25:29.48#ibcon#flushed, iclass 29, count 0 2006.225.08:25:29.48#ibcon#about to write, iclass 29, count 0 2006.225.08:25:29.48#ibcon#wrote, iclass 29, count 0 2006.225.08:25:29.48#ibcon#about to read 3, iclass 29, count 0 2006.225.08:25:29.51#ibcon#read 3, iclass 29, count 0 2006.225.08:25:29.51#ibcon#about to read 4, iclass 29, count 0 2006.225.08:25:29.51#ibcon#read 4, iclass 29, count 0 2006.225.08:25:29.51#ibcon#about to read 5, iclass 29, count 0 2006.225.08:25:29.51#ibcon#read 5, iclass 29, count 0 2006.225.08:25:29.51#ibcon#about to read 6, iclass 29, count 0 2006.225.08:25:29.51#ibcon#read 6, iclass 29, count 0 2006.225.08:25:29.51#ibcon#end of sib2, iclass 29, count 0 2006.225.08:25:29.51#ibcon#*after write, iclass 29, count 0 2006.225.08:25:29.51#ibcon#*before return 0, iclass 29, count 0 2006.225.08:25:29.51#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:25:29.51#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:25:29.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:25:29.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:25:29.51$vc4f8/valo=6,772.99 2006.225.08:25:29.51#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.08:25:29.51#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.08:25:29.51#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:29.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:25:29.51#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:25:29.51#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:25:29.51#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:25:29.51#ibcon#first serial, iclass 31, count 0 2006.225.08:25:29.51#ibcon#enter sib2, iclass 31, count 0 2006.225.08:25:29.51#ibcon#flushed, iclass 31, count 0 2006.225.08:25:29.51#ibcon#about to write, iclass 31, count 0 2006.225.08:25:29.51#ibcon#wrote, iclass 31, count 0 2006.225.08:25:29.51#ibcon#about to read 3, iclass 31, count 0 2006.225.08:25:29.54#ibcon#read 3, iclass 31, count 0 2006.225.08:25:29.54#ibcon#about to read 4, iclass 31, count 0 2006.225.08:25:29.54#ibcon#read 4, iclass 31, count 0 2006.225.08:25:29.54#ibcon#about to read 5, iclass 31, count 0 2006.225.08:25:29.54#ibcon#read 5, iclass 31, count 0 2006.225.08:25:29.54#ibcon#about to read 6, iclass 31, count 0 2006.225.08:25:29.54#ibcon#read 6, iclass 31, count 0 2006.225.08:25:29.54#ibcon#end of sib2, iclass 31, count 0 2006.225.08:25:29.54#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:25:29.54#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:25:29.54#ibcon#[26=FRQ=06,772.99\r\n] 2006.225.08:25:29.54#ibcon#*before write, iclass 31, count 0 2006.225.08:25:29.54#ibcon#enter sib2, iclass 31, count 0 2006.225.08:25:29.54#ibcon#flushed, iclass 31, count 0 2006.225.08:25:29.54#ibcon#about to write, iclass 31, count 0 2006.225.08:25:29.54#ibcon#wrote, iclass 31, count 0 2006.225.08:25:29.54#ibcon#about to read 3, iclass 31, count 0 2006.225.08:25:29.58#ibcon#read 3, iclass 31, count 0 2006.225.08:25:29.58#ibcon#about to read 4, iclass 31, count 0 2006.225.08:25:29.58#ibcon#read 4, iclass 31, count 0 2006.225.08:25:29.58#ibcon#about to read 5, iclass 31, count 0 2006.225.08:25:29.58#ibcon#read 5, iclass 31, count 0 2006.225.08:25:29.58#ibcon#about to read 6, iclass 31, count 0 2006.225.08:25:29.58#ibcon#read 6, iclass 31, count 0 2006.225.08:25:29.58#ibcon#end of sib2, iclass 31, count 0 2006.225.08:25:29.58#ibcon#*after write, iclass 31, count 0 2006.225.08:25:29.58#ibcon#*before return 0, iclass 31, count 0 2006.225.08:25:29.58#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:25:29.58#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:25:29.58#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:25:29.58#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:25:29.58$vc4f8/va=6,6 2006.225.08:25:29.58#ibcon#iclass 33 nclrec 2 cls_cnt 3 2006.225.08:25:29.58#ibcon#iclass 33 iclrec 1 cls_cnt 3 2006.225.08:25:29.58#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:29.58#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:25:29.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:25:29.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:25:29.63#ibcon#enter wrdev, iclass 33, count 2 2006.225.08:25:29.63#ibcon#first serial, iclass 33, count 2 2006.225.08:25:29.63#ibcon#enter sib2, iclass 33, count 2 2006.225.08:25:29.63#ibcon#flushed, iclass 33, count 2 2006.225.08:25:29.63#ibcon#about to write, iclass 33, count 2 2006.225.08:25:29.63#ibcon#wrote, iclass 33, count 2 2006.225.08:25:29.63#ibcon#about to read 3, iclass 33, count 2 2006.225.08:25:29.65#ibcon#read 3, iclass 33, count 2 2006.225.08:25:29.65#ibcon#about to read 4, iclass 33, count 2 2006.225.08:25:29.65#ibcon#read 4, iclass 33, count 2 2006.225.08:25:29.65#ibcon#about to read 5, iclass 33, count 2 2006.225.08:25:29.65#ibcon#read 5, iclass 33, count 2 2006.225.08:25:29.65#ibcon#about to read 6, iclass 33, count 2 2006.225.08:25:29.65#ibcon#read 6, iclass 33, count 2 2006.225.08:25:29.65#ibcon#end of sib2, iclass 33, count 2 2006.225.08:25:29.65#ibcon#*mode == 0, iclass 33, count 2 2006.225.08:25:29.65#ibcon#*mode == 0 && serial, iclass 33, count 2 2006.225.08:25:29.65#ibcon#[25=AT06-06\r\n] 2006.225.08:25:29.65#ibcon#*before write, iclass 33, count 2 2006.225.08:25:29.65#ibcon#enter sib2, iclass 33, count 2 2006.225.08:25:29.65#ibcon#flushed, iclass 33, count 2 2006.225.08:25:29.65#ibcon#about to write, iclass 33, count 2 2006.225.08:25:29.65#ibcon#wrote, iclass 33, count 2 2006.225.08:25:29.65#ibcon#about to read 3, iclass 33, count 2 2006.225.08:25:29.68#ibcon#read 3, iclass 33, count 2 2006.225.08:25:29.68#ibcon#about to read 4, iclass 33, count 2 2006.225.08:25:29.68#ibcon#read 4, iclass 33, count 2 2006.225.08:25:29.68#ibcon#about to read 5, iclass 33, count 2 2006.225.08:25:29.68#ibcon#read 5, iclass 33, count 2 2006.225.08:25:29.68#ibcon#about to read 6, iclass 33, count 2 2006.225.08:25:29.68#ibcon#read 6, iclass 33, count 2 2006.225.08:25:29.68#ibcon#end of sib2, iclass 33, count 2 2006.225.08:25:29.68#ibcon#*after write, iclass 33, count 2 2006.225.08:25:29.68#ibcon#*before return 0, iclass 33, count 2 2006.225.08:25:29.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:25:29.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 2 2006.225.08:25:29.68#ibcon#iclass 33 iclrec 2 cls_cnt 2 2006.225.08:25:29.68#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:29.68#ibcon#before find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:25:29.80#ibcon#after find_delay mode 2, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:25:29.80#ibcon#before mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:25:29.80#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:25:29.80#ibcon#first serial, iclass 33, count 0 2006.225.08:25:29.80#ibcon#enter sib2, iclass 33, count 0 2006.225.08:25:29.80#ibcon#flushed, iclass 33, count 0 2006.225.08:25:29.80#ibcon#about to write, iclass 33, count 0 2006.225.08:25:29.80#ibcon#wrote, iclass 33, count 0 2006.225.08:25:29.80#ibcon#about to read 3, iclass 33, count 0 2006.225.08:25:29.82#ibcon#read 3, iclass 33, count 0 2006.225.08:25:29.82#ibcon#about to read 4, iclass 33, count 0 2006.225.08:25:29.82#ibcon#read 4, iclass 33, count 0 2006.225.08:25:29.82#ibcon#about to read 5, iclass 33, count 0 2006.225.08:25:29.82#ibcon#read 5, iclass 33, count 0 2006.225.08:25:29.82#ibcon#about to read 6, iclass 33, count 0 2006.225.08:25:29.82#ibcon#read 6, iclass 33, count 0 2006.225.08:25:29.82#ibcon#end of sib2, iclass 33, count 0 2006.225.08:25:29.82#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:25:29.82#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:25:29.82#ibcon#[25=USB\r\n] 2006.225.08:25:29.82#ibcon#*before write, iclass 33, count 0 2006.225.08:25:29.82#ibcon#enter sib2, iclass 33, count 0 2006.225.08:25:29.82#ibcon#flushed, iclass 33, count 0 2006.225.08:25:29.82#ibcon#about to write, iclass 33, count 0 2006.225.08:25:29.82#ibcon#wrote, iclass 33, count 0 2006.225.08:25:29.82#ibcon#about to read 3, iclass 33, count 0 2006.225.08:25:29.85#ibcon#read 3, iclass 33, count 0 2006.225.08:25:29.85#ibcon#about to read 4, iclass 33, count 0 2006.225.08:25:29.85#ibcon#read 4, iclass 33, count 0 2006.225.08:25:29.85#ibcon#about to read 5, iclass 33, count 0 2006.225.08:25:29.85#ibcon#read 5, iclass 33, count 0 2006.225.08:25:29.85#ibcon#about to read 6, iclass 33, count 0 2006.225.08:25:29.85#ibcon#read 6, iclass 33, count 0 2006.225.08:25:29.85#ibcon#end of sib2, iclass 33, count 0 2006.225.08:25:29.85#ibcon#*after write, iclass 33, count 0 2006.225.08:25:29.85#ibcon#*before return 0, iclass 33, count 0 2006.225.08:25:29.85#ibcon#after mode 2 write, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:25:29.85#ibcon#end of loop, iclass 33 iclrec 2 cls_cnt 0 2006.225.08:25:29.85#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:25:29.85#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:25:29.85$vc4f8/valo=7,832.99 2006.225.08:25:29.85#ibcon#iclass 35 nclrec 1 cls_cnt 2 2006.225.08:25:29.85#ibcon#iclass 35 iclrec 1 cls_cnt 2 2006.225.08:25:29.85#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:29.85#ibcon#before find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:25:29.85#ibcon#after find_delay mode 2, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:25:29.85#ibcon#before mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:25:29.85#ibcon#enter wrdev, iclass 35, count 0 2006.225.08:25:29.85#ibcon#first serial, iclass 35, count 0 2006.225.08:25:29.85#ibcon#enter sib2, iclass 35, count 0 2006.225.08:25:29.85#ibcon#flushed, iclass 35, count 0 2006.225.08:25:29.85#ibcon#about to write, iclass 35, count 0 2006.225.08:25:29.85#ibcon#wrote, iclass 35, count 0 2006.225.08:25:29.85#ibcon#about to read 3, iclass 35, count 0 2006.225.08:25:29.87#ibcon#read 3, iclass 35, count 0 2006.225.08:25:29.87#ibcon#about to read 4, iclass 35, count 0 2006.225.08:25:29.87#ibcon#read 4, iclass 35, count 0 2006.225.08:25:29.87#ibcon#about to read 5, iclass 35, count 0 2006.225.08:25:29.87#ibcon#read 5, iclass 35, count 0 2006.225.08:25:29.87#ibcon#about to read 6, iclass 35, count 0 2006.225.08:25:29.87#ibcon#read 6, iclass 35, count 0 2006.225.08:25:29.87#ibcon#end of sib2, iclass 35, count 0 2006.225.08:25:29.87#ibcon#*mode == 0, iclass 35, count 0 2006.225.08:25:29.87#ibcon#*mode == 0 && serial, iclass 35, count 0 2006.225.08:25:29.87#ibcon#[26=FRQ=07,832.99\r\n] 2006.225.08:25:29.87#ibcon#*before write, iclass 35, count 0 2006.225.08:25:29.87#ibcon#enter sib2, iclass 35, count 0 2006.225.08:25:29.87#ibcon#flushed, iclass 35, count 0 2006.225.08:25:29.87#ibcon#about to write, iclass 35, count 0 2006.225.08:25:29.87#ibcon#wrote, iclass 35, count 0 2006.225.08:25:29.87#ibcon#about to read 3, iclass 35, count 0 2006.225.08:25:29.91#ibcon#read 3, iclass 35, count 0 2006.225.08:25:29.91#ibcon#about to read 4, iclass 35, count 0 2006.225.08:25:29.91#ibcon#read 4, iclass 35, count 0 2006.225.08:25:29.91#ibcon#about to read 5, iclass 35, count 0 2006.225.08:25:29.91#ibcon#read 5, iclass 35, count 0 2006.225.08:25:29.91#ibcon#about to read 6, iclass 35, count 0 2006.225.08:25:29.91#ibcon#read 6, iclass 35, count 0 2006.225.08:25:29.91#ibcon#end of sib2, iclass 35, count 0 2006.225.08:25:29.91#ibcon#*after write, iclass 35, count 0 2006.225.08:25:29.91#ibcon#*before return 0, iclass 35, count 0 2006.225.08:25:29.91#ibcon#after mode 2 write, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:25:29.91#ibcon#end of loop, iclass 35 iclrec 1 cls_cnt 0 2006.225.08:25:29.91#ibcon#about to clear, iclass 35 cls_cnt 0 2006.225.08:25:29.91#ibcon#cleared, iclass 35 cls_cnt 0 2006.225.08:25:29.91$vc4f8/va=7,6 2006.225.08:25:29.91#ibcon#iclass 37 nclrec 2 cls_cnt 3 2006.225.08:25:29.91#ibcon#iclass 37 iclrec 1 cls_cnt 3 2006.225.08:25:29.91#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:29.91#ibcon#before find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:25:29.97#ibcon#after find_delay mode 2, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:25:29.97#ibcon#before mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:25:29.97#ibcon#enter wrdev, iclass 37, count 2 2006.225.08:25:29.97#ibcon#first serial, iclass 37, count 2 2006.225.08:25:29.97#ibcon#enter sib2, iclass 37, count 2 2006.225.08:25:29.97#ibcon#flushed, iclass 37, count 2 2006.225.08:25:29.97#ibcon#about to write, iclass 37, count 2 2006.225.08:25:29.97#ibcon#wrote, iclass 37, count 2 2006.225.08:25:29.97#ibcon#about to read 3, iclass 37, count 2 2006.225.08:25:29.99#ibcon#read 3, iclass 37, count 2 2006.225.08:25:29.99#ibcon#about to read 4, iclass 37, count 2 2006.225.08:25:29.99#ibcon#read 4, iclass 37, count 2 2006.225.08:25:29.99#ibcon#about to read 5, iclass 37, count 2 2006.225.08:25:29.99#ibcon#read 5, iclass 37, count 2 2006.225.08:25:29.99#ibcon#about to read 6, iclass 37, count 2 2006.225.08:25:29.99#ibcon#read 6, iclass 37, count 2 2006.225.08:25:29.99#ibcon#end of sib2, iclass 37, count 2 2006.225.08:25:29.99#ibcon#*mode == 0, iclass 37, count 2 2006.225.08:25:29.99#ibcon#*mode == 0 && serial, iclass 37, count 2 2006.225.08:25:29.99#ibcon#[25=AT07-06\r\n] 2006.225.08:25:29.99#ibcon#*before write, iclass 37, count 2 2006.225.08:25:29.99#ibcon#enter sib2, iclass 37, count 2 2006.225.08:25:29.99#ibcon#flushed, iclass 37, count 2 2006.225.08:25:29.99#ibcon#about to write, iclass 37, count 2 2006.225.08:25:29.99#ibcon#wrote, iclass 37, count 2 2006.225.08:25:29.99#ibcon#about to read 3, iclass 37, count 2 2006.225.08:25:30.02#ibcon#read 3, iclass 37, count 2 2006.225.08:25:30.02#ibcon#about to read 4, iclass 37, count 2 2006.225.08:25:30.02#ibcon#read 4, iclass 37, count 2 2006.225.08:25:30.02#ibcon#about to read 5, iclass 37, count 2 2006.225.08:25:30.02#ibcon#read 5, iclass 37, count 2 2006.225.08:25:30.02#ibcon#about to read 6, iclass 37, count 2 2006.225.08:25:30.02#ibcon#read 6, iclass 37, count 2 2006.225.08:25:30.02#ibcon#end of sib2, iclass 37, count 2 2006.225.08:25:30.02#ibcon#*after write, iclass 37, count 2 2006.225.08:25:30.02#ibcon#*before return 0, iclass 37, count 2 2006.225.08:25:30.02#ibcon#after mode 2 write, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:25:30.02#ibcon#end of loop, iclass 37 iclrec 1 cls_cnt 2 2006.225.08:25:30.02#ibcon#iclass 37 iclrec 2 cls_cnt 2 2006.225.08:25:30.02#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:30.02#ibcon#before find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:25:30.14#ibcon#after find_delay mode 2, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:25:30.14#ibcon#before mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:25:30.14#ibcon#enter wrdev, iclass 37, count 0 2006.225.08:25:30.14#ibcon#first serial, iclass 37, count 0 2006.225.08:25:30.14#ibcon#enter sib2, iclass 37, count 0 2006.225.08:25:30.14#ibcon#flushed, iclass 37, count 0 2006.225.08:25:30.14#ibcon#about to write, iclass 37, count 0 2006.225.08:25:30.14#ibcon#wrote, iclass 37, count 0 2006.225.08:25:30.14#ibcon#about to read 3, iclass 37, count 0 2006.225.08:25:30.16#ibcon#read 3, iclass 37, count 0 2006.225.08:25:30.16#ibcon#about to read 4, iclass 37, count 0 2006.225.08:25:30.16#ibcon#read 4, iclass 37, count 0 2006.225.08:25:30.16#ibcon#about to read 5, iclass 37, count 0 2006.225.08:25:30.16#ibcon#read 5, iclass 37, count 0 2006.225.08:25:30.16#ibcon#about to read 6, iclass 37, count 0 2006.225.08:25:30.16#ibcon#read 6, iclass 37, count 0 2006.225.08:25:30.16#ibcon#end of sib2, iclass 37, count 0 2006.225.08:25:30.16#ibcon#*mode == 0, iclass 37, count 0 2006.225.08:25:30.16#ibcon#*mode == 0 && serial, iclass 37, count 0 2006.225.08:25:30.16#ibcon#[25=USB\r\n] 2006.225.08:25:30.16#ibcon#*before write, iclass 37, count 0 2006.225.08:25:30.16#ibcon#enter sib2, iclass 37, count 0 2006.225.08:25:30.16#ibcon#flushed, iclass 37, count 0 2006.225.08:25:30.16#ibcon#about to write, iclass 37, count 0 2006.225.08:25:30.16#ibcon#wrote, iclass 37, count 0 2006.225.08:25:30.16#ibcon#about to read 3, iclass 37, count 0 2006.225.08:25:30.19#ibcon#read 3, iclass 37, count 0 2006.225.08:25:30.19#ibcon#about to read 4, iclass 37, count 0 2006.225.08:25:30.19#ibcon#read 4, iclass 37, count 0 2006.225.08:25:30.19#ibcon#about to read 5, iclass 37, count 0 2006.225.08:25:30.19#ibcon#read 5, iclass 37, count 0 2006.225.08:25:30.19#ibcon#about to read 6, iclass 37, count 0 2006.225.08:25:30.19#ibcon#read 6, iclass 37, count 0 2006.225.08:25:30.19#ibcon#end of sib2, iclass 37, count 0 2006.225.08:25:30.19#ibcon#*after write, iclass 37, count 0 2006.225.08:25:30.19#ibcon#*before return 0, iclass 37, count 0 2006.225.08:25:30.19#ibcon#after mode 2 write, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:25:30.19#ibcon#end of loop, iclass 37 iclrec 2 cls_cnt 0 2006.225.08:25:30.19#ibcon#about to clear, iclass 37 cls_cnt 0 2006.225.08:25:30.19#ibcon#cleared, iclass 37 cls_cnt 0 2006.225.08:25:30.19$vc4f8/valo=8,852.99 2006.225.08:25:30.19#ibcon#iclass 39 nclrec 1 cls_cnt 2 2006.225.08:25:30.19#ibcon#iclass 39 iclrec 1 cls_cnt 2 2006.225.08:25:30.19#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:30.19#ibcon#before find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:25:30.19#ibcon#after find_delay mode 2, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:25:30.19#ibcon#before mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:25:30.19#ibcon#enter wrdev, iclass 39, count 0 2006.225.08:25:30.19#ibcon#first serial, iclass 39, count 0 2006.225.08:25:30.19#ibcon#enter sib2, iclass 39, count 0 2006.225.08:25:30.19#ibcon#flushed, iclass 39, count 0 2006.225.08:25:30.19#ibcon#about to write, iclass 39, count 0 2006.225.08:25:30.19#ibcon#wrote, iclass 39, count 0 2006.225.08:25:30.19#ibcon#about to read 3, iclass 39, count 0 2006.225.08:25:30.21#ibcon#read 3, iclass 39, count 0 2006.225.08:25:30.21#ibcon#about to read 4, iclass 39, count 0 2006.225.08:25:30.21#ibcon#read 4, iclass 39, count 0 2006.225.08:25:30.21#ibcon#about to read 5, iclass 39, count 0 2006.225.08:25:30.21#ibcon#read 5, iclass 39, count 0 2006.225.08:25:30.21#ibcon#about to read 6, iclass 39, count 0 2006.225.08:25:30.21#ibcon#read 6, iclass 39, count 0 2006.225.08:25:30.21#ibcon#end of sib2, iclass 39, count 0 2006.225.08:25:30.21#ibcon#*mode == 0, iclass 39, count 0 2006.225.08:25:30.21#ibcon#*mode == 0 && serial, iclass 39, count 0 2006.225.08:25:30.21#ibcon#[26=FRQ=08,852.99\r\n] 2006.225.08:25:30.21#ibcon#*before write, iclass 39, count 0 2006.225.08:25:30.21#ibcon#enter sib2, iclass 39, count 0 2006.225.08:25:30.21#ibcon#flushed, iclass 39, count 0 2006.225.08:25:30.21#ibcon#about to write, iclass 39, count 0 2006.225.08:25:30.21#ibcon#wrote, iclass 39, count 0 2006.225.08:25:30.21#ibcon#about to read 3, iclass 39, count 0 2006.225.08:25:30.25#ibcon#read 3, iclass 39, count 0 2006.225.08:25:30.25#ibcon#about to read 4, iclass 39, count 0 2006.225.08:25:30.25#ibcon#read 4, iclass 39, count 0 2006.225.08:25:30.25#ibcon#about to read 5, iclass 39, count 0 2006.225.08:25:30.25#ibcon#read 5, iclass 39, count 0 2006.225.08:25:30.25#ibcon#about to read 6, iclass 39, count 0 2006.225.08:25:30.25#ibcon#read 6, iclass 39, count 0 2006.225.08:25:30.25#ibcon#end of sib2, iclass 39, count 0 2006.225.08:25:30.25#ibcon#*after write, iclass 39, count 0 2006.225.08:25:30.25#ibcon#*before return 0, iclass 39, count 0 2006.225.08:25:30.25#ibcon#after mode 2 write, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:25:30.25#ibcon#end of loop, iclass 39 iclrec 1 cls_cnt 0 2006.225.08:25:30.25#ibcon#about to clear, iclass 39 cls_cnt 0 2006.225.08:25:30.25#ibcon#cleared, iclass 39 cls_cnt 0 2006.225.08:25:30.25$vc4f8/va=8,7 2006.225.08:25:30.25#ibcon#iclass 3 nclrec 2 cls_cnt 3 2006.225.08:25:30.25#ibcon#iclass 3 iclrec 1 cls_cnt 3 2006.225.08:25:30.25#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:30.25#ibcon#before find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:25:30.31#ibcon#after find_delay mode 2, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:25:30.31#ibcon#before mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:25:30.31#ibcon#enter wrdev, iclass 3, count 2 2006.225.08:25:30.31#ibcon#first serial, iclass 3, count 2 2006.225.08:25:30.31#ibcon#enter sib2, iclass 3, count 2 2006.225.08:25:30.31#ibcon#flushed, iclass 3, count 2 2006.225.08:25:30.31#ibcon#about to write, iclass 3, count 2 2006.225.08:25:30.31#ibcon#wrote, iclass 3, count 2 2006.225.08:25:30.31#ibcon#about to read 3, iclass 3, count 2 2006.225.08:25:30.33#ibcon#read 3, iclass 3, count 2 2006.225.08:25:30.33#ibcon#about to read 4, iclass 3, count 2 2006.225.08:25:30.33#ibcon#read 4, iclass 3, count 2 2006.225.08:25:30.33#ibcon#about to read 5, iclass 3, count 2 2006.225.08:25:30.33#ibcon#read 5, iclass 3, count 2 2006.225.08:25:30.33#ibcon#about to read 6, iclass 3, count 2 2006.225.08:25:30.33#ibcon#read 6, iclass 3, count 2 2006.225.08:25:30.33#ibcon#end of sib2, iclass 3, count 2 2006.225.08:25:30.33#ibcon#*mode == 0, iclass 3, count 2 2006.225.08:25:30.33#ibcon#*mode == 0 && serial, iclass 3, count 2 2006.225.08:25:30.33#ibcon#[25=AT08-07\r\n] 2006.225.08:25:30.33#ibcon#*before write, iclass 3, count 2 2006.225.08:25:30.33#ibcon#enter sib2, iclass 3, count 2 2006.225.08:25:30.33#ibcon#flushed, iclass 3, count 2 2006.225.08:25:30.33#ibcon#about to write, iclass 3, count 2 2006.225.08:25:30.33#ibcon#wrote, iclass 3, count 2 2006.225.08:25:30.33#ibcon#about to read 3, iclass 3, count 2 2006.225.08:25:30.36#ibcon#read 3, iclass 3, count 2 2006.225.08:25:30.36#ibcon#about to read 4, iclass 3, count 2 2006.225.08:25:30.36#ibcon#read 4, iclass 3, count 2 2006.225.08:25:30.36#ibcon#about to read 5, iclass 3, count 2 2006.225.08:25:30.36#ibcon#read 5, iclass 3, count 2 2006.225.08:25:30.36#ibcon#about to read 6, iclass 3, count 2 2006.225.08:25:30.36#ibcon#read 6, iclass 3, count 2 2006.225.08:25:30.36#ibcon#end of sib2, iclass 3, count 2 2006.225.08:25:30.36#ibcon#*after write, iclass 3, count 2 2006.225.08:25:30.36#ibcon#*before return 0, iclass 3, count 2 2006.225.08:25:30.36#ibcon#after mode 2 write, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:25:30.36#ibcon#end of loop, iclass 3 iclrec 1 cls_cnt 2 2006.225.08:25:30.36#ibcon#iclass 3 iclrec 2 cls_cnt 2 2006.225.08:25:30.36#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:30.36#ibcon#before find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:25:30.48#ibcon#after find_delay mode 2, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:25:30.48#ibcon#before mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:25:30.48#ibcon#enter wrdev, iclass 3, count 0 2006.225.08:25:30.48#ibcon#first serial, iclass 3, count 0 2006.225.08:25:30.48#ibcon#enter sib2, iclass 3, count 0 2006.225.08:25:30.48#ibcon#flushed, iclass 3, count 0 2006.225.08:25:30.48#ibcon#about to write, iclass 3, count 0 2006.225.08:25:30.48#ibcon#wrote, iclass 3, count 0 2006.225.08:25:30.48#ibcon#about to read 3, iclass 3, count 0 2006.225.08:25:30.50#ibcon#read 3, iclass 3, count 0 2006.225.08:25:30.50#ibcon#about to read 4, iclass 3, count 0 2006.225.08:25:30.50#ibcon#read 4, iclass 3, count 0 2006.225.08:25:30.50#ibcon#about to read 5, iclass 3, count 0 2006.225.08:25:30.50#ibcon#read 5, iclass 3, count 0 2006.225.08:25:30.50#ibcon#about to read 6, iclass 3, count 0 2006.225.08:25:30.50#ibcon#read 6, iclass 3, count 0 2006.225.08:25:30.50#ibcon#end of sib2, iclass 3, count 0 2006.225.08:25:30.50#ibcon#*mode == 0, iclass 3, count 0 2006.225.08:25:30.50#ibcon#*mode == 0 && serial, iclass 3, count 0 2006.225.08:25:30.50#ibcon#[25=USB\r\n] 2006.225.08:25:30.50#ibcon#*before write, iclass 3, count 0 2006.225.08:25:30.50#ibcon#enter sib2, iclass 3, count 0 2006.225.08:25:30.50#ibcon#flushed, iclass 3, count 0 2006.225.08:25:30.50#ibcon#about to write, iclass 3, count 0 2006.225.08:25:30.50#ibcon#wrote, iclass 3, count 0 2006.225.08:25:30.50#ibcon#about to read 3, iclass 3, count 0 2006.225.08:25:30.53#ibcon#read 3, iclass 3, count 0 2006.225.08:25:30.53#ibcon#about to read 4, iclass 3, count 0 2006.225.08:25:30.53#ibcon#read 4, iclass 3, count 0 2006.225.08:25:30.53#ibcon#about to read 5, iclass 3, count 0 2006.225.08:25:30.53#ibcon#read 5, iclass 3, count 0 2006.225.08:25:30.53#ibcon#about to read 6, iclass 3, count 0 2006.225.08:25:30.53#ibcon#read 6, iclass 3, count 0 2006.225.08:25:30.53#ibcon#end of sib2, iclass 3, count 0 2006.225.08:25:30.53#ibcon#*after write, iclass 3, count 0 2006.225.08:25:30.53#ibcon#*before return 0, iclass 3, count 0 2006.225.08:25:30.53#ibcon#after mode 2 write, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:25:30.53#ibcon#end of loop, iclass 3 iclrec 2 cls_cnt 0 2006.225.08:25:30.53#ibcon#about to clear, iclass 3 cls_cnt 0 2006.225.08:25:30.53#ibcon#cleared, iclass 3 cls_cnt 0 2006.225.08:25:30.53$vc4f8/vblo=1,632.99 2006.225.08:25:30.53#ibcon#iclass 5 nclrec 1 cls_cnt 2 2006.225.08:25:30.53#ibcon#iclass 5 iclrec 1 cls_cnt 2 2006.225.08:25:30.53#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:30.53#ibcon#before find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:25:30.53#ibcon#after find_delay mode 2, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:25:30.53#ibcon#before mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:25:30.53#ibcon#enter wrdev, iclass 5, count 0 2006.225.08:25:30.53#ibcon#first serial, iclass 5, count 0 2006.225.08:25:30.53#ibcon#enter sib2, iclass 5, count 0 2006.225.08:25:30.53#ibcon#flushed, iclass 5, count 0 2006.225.08:25:30.53#ibcon#about to write, iclass 5, count 0 2006.225.08:25:30.53#ibcon#wrote, iclass 5, count 0 2006.225.08:25:30.53#ibcon#about to read 3, iclass 5, count 0 2006.225.08:25:30.55#ibcon#read 3, iclass 5, count 0 2006.225.08:25:30.55#ibcon#about to read 4, iclass 5, count 0 2006.225.08:25:30.55#ibcon#read 4, iclass 5, count 0 2006.225.08:25:30.55#ibcon#about to read 5, iclass 5, count 0 2006.225.08:25:30.55#ibcon#read 5, iclass 5, count 0 2006.225.08:25:30.55#ibcon#about to read 6, iclass 5, count 0 2006.225.08:25:30.55#ibcon#read 6, iclass 5, count 0 2006.225.08:25:30.55#ibcon#end of sib2, iclass 5, count 0 2006.225.08:25:30.55#ibcon#*mode == 0, iclass 5, count 0 2006.225.08:25:30.55#ibcon#*mode == 0 && serial, iclass 5, count 0 2006.225.08:25:30.55#ibcon#[28=FRQ=01,632.99\r\n] 2006.225.08:25:30.55#ibcon#*before write, iclass 5, count 0 2006.225.08:25:30.55#ibcon#enter sib2, iclass 5, count 0 2006.225.08:25:30.55#ibcon#flushed, iclass 5, count 0 2006.225.08:25:30.55#ibcon#about to write, iclass 5, count 0 2006.225.08:25:30.55#ibcon#wrote, iclass 5, count 0 2006.225.08:25:30.55#ibcon#about to read 3, iclass 5, count 0 2006.225.08:25:30.59#ibcon#read 3, iclass 5, count 0 2006.225.08:25:30.59#ibcon#about to read 4, iclass 5, count 0 2006.225.08:25:30.59#ibcon#read 4, iclass 5, count 0 2006.225.08:25:30.59#ibcon#about to read 5, iclass 5, count 0 2006.225.08:25:30.59#ibcon#read 5, iclass 5, count 0 2006.225.08:25:30.59#ibcon#about to read 6, iclass 5, count 0 2006.225.08:25:30.59#ibcon#read 6, iclass 5, count 0 2006.225.08:25:30.59#ibcon#end of sib2, iclass 5, count 0 2006.225.08:25:30.59#ibcon#*after write, iclass 5, count 0 2006.225.08:25:30.59#ibcon#*before return 0, iclass 5, count 0 2006.225.08:25:30.59#ibcon#after mode 2 write, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:25:30.59#ibcon#end of loop, iclass 5 iclrec 1 cls_cnt 0 2006.225.08:25:30.59#ibcon#about to clear, iclass 5 cls_cnt 0 2006.225.08:25:30.59#ibcon#cleared, iclass 5 cls_cnt 0 2006.225.08:25:30.59$vc4f8/vb=1,4 2006.225.08:25:30.59#ibcon#iclass 7 nclrec 2 cls_cnt 3 2006.225.08:25:30.59#ibcon#iclass 7 iclrec 1 cls_cnt 3 2006.225.08:25:30.59#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:30.59#ibcon#before find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:25:30.59#ibcon#after find_delay mode 2, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:25:30.59#ibcon#before mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:25:30.59#ibcon#enter wrdev, iclass 7, count 2 2006.225.08:25:30.59#ibcon#first serial, iclass 7, count 2 2006.225.08:25:30.59#ibcon#enter sib2, iclass 7, count 2 2006.225.08:25:30.59#ibcon#flushed, iclass 7, count 2 2006.225.08:25:30.59#ibcon#about to write, iclass 7, count 2 2006.225.08:25:30.59#ibcon#wrote, iclass 7, count 2 2006.225.08:25:30.59#ibcon#about to read 3, iclass 7, count 2 2006.225.08:25:30.61#ibcon#read 3, iclass 7, count 2 2006.225.08:25:30.61#ibcon#about to read 4, iclass 7, count 2 2006.225.08:25:30.61#ibcon#read 4, iclass 7, count 2 2006.225.08:25:30.61#ibcon#about to read 5, iclass 7, count 2 2006.225.08:25:30.61#ibcon#read 5, iclass 7, count 2 2006.225.08:25:30.61#ibcon#about to read 6, iclass 7, count 2 2006.225.08:25:30.61#ibcon#read 6, iclass 7, count 2 2006.225.08:25:30.61#ibcon#end of sib2, iclass 7, count 2 2006.225.08:25:30.61#ibcon#*mode == 0, iclass 7, count 2 2006.225.08:25:30.61#ibcon#*mode == 0 && serial, iclass 7, count 2 2006.225.08:25:30.61#ibcon#[27=AT01-04\r\n] 2006.225.08:25:30.61#ibcon#*before write, iclass 7, count 2 2006.225.08:25:30.61#ibcon#enter sib2, iclass 7, count 2 2006.225.08:25:30.61#ibcon#flushed, iclass 7, count 2 2006.225.08:25:30.61#ibcon#about to write, iclass 7, count 2 2006.225.08:25:30.61#ibcon#wrote, iclass 7, count 2 2006.225.08:25:30.61#ibcon#about to read 3, iclass 7, count 2 2006.225.08:25:30.64#ibcon#read 3, iclass 7, count 2 2006.225.08:25:30.64#ibcon#about to read 4, iclass 7, count 2 2006.225.08:25:30.64#ibcon#read 4, iclass 7, count 2 2006.225.08:25:30.64#ibcon#about to read 5, iclass 7, count 2 2006.225.08:25:30.64#ibcon#read 5, iclass 7, count 2 2006.225.08:25:30.64#ibcon#about to read 6, iclass 7, count 2 2006.225.08:25:30.64#ibcon#read 6, iclass 7, count 2 2006.225.08:25:30.64#ibcon#end of sib2, iclass 7, count 2 2006.225.08:25:30.64#ibcon#*after write, iclass 7, count 2 2006.225.08:25:30.64#ibcon#*before return 0, iclass 7, count 2 2006.225.08:25:30.64#ibcon#after mode 2 write, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:25:30.64#ibcon#end of loop, iclass 7 iclrec 1 cls_cnt 2 2006.225.08:25:30.64#ibcon#iclass 7 iclrec 2 cls_cnt 2 2006.225.08:25:30.64#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:30.64#ibcon#before find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:25:30.76#ibcon#after find_delay mode 2, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:25:30.76#ibcon#before mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:25:30.76#ibcon#enter wrdev, iclass 7, count 0 2006.225.08:25:30.76#ibcon#first serial, iclass 7, count 0 2006.225.08:25:30.76#ibcon#enter sib2, iclass 7, count 0 2006.225.08:25:30.76#ibcon#flushed, iclass 7, count 0 2006.225.08:25:30.76#ibcon#about to write, iclass 7, count 0 2006.225.08:25:30.76#ibcon#wrote, iclass 7, count 0 2006.225.08:25:30.76#ibcon#about to read 3, iclass 7, count 0 2006.225.08:25:30.78#ibcon#read 3, iclass 7, count 0 2006.225.08:25:30.78#ibcon#about to read 4, iclass 7, count 0 2006.225.08:25:30.78#ibcon#read 4, iclass 7, count 0 2006.225.08:25:30.78#ibcon#about to read 5, iclass 7, count 0 2006.225.08:25:30.78#ibcon#read 5, iclass 7, count 0 2006.225.08:25:30.78#ibcon#about to read 6, iclass 7, count 0 2006.225.08:25:30.78#ibcon#read 6, iclass 7, count 0 2006.225.08:25:30.78#ibcon#end of sib2, iclass 7, count 0 2006.225.08:25:30.78#ibcon#*mode == 0, iclass 7, count 0 2006.225.08:25:30.78#ibcon#*mode == 0 && serial, iclass 7, count 0 2006.225.08:25:30.78#ibcon#[27=USB\r\n] 2006.225.08:25:30.78#ibcon#*before write, iclass 7, count 0 2006.225.08:25:30.78#ibcon#enter sib2, iclass 7, count 0 2006.225.08:25:30.78#ibcon#flushed, iclass 7, count 0 2006.225.08:25:30.78#ibcon#about to write, iclass 7, count 0 2006.225.08:25:30.78#ibcon#wrote, iclass 7, count 0 2006.225.08:25:30.78#ibcon#about to read 3, iclass 7, count 0 2006.225.08:25:30.81#ibcon#read 3, iclass 7, count 0 2006.225.08:25:30.81#ibcon#about to read 4, iclass 7, count 0 2006.225.08:25:30.81#ibcon#read 4, iclass 7, count 0 2006.225.08:25:30.81#ibcon#about to read 5, iclass 7, count 0 2006.225.08:25:30.81#ibcon#read 5, iclass 7, count 0 2006.225.08:25:30.81#ibcon#about to read 6, iclass 7, count 0 2006.225.08:25:30.81#ibcon#read 6, iclass 7, count 0 2006.225.08:25:30.81#ibcon#end of sib2, iclass 7, count 0 2006.225.08:25:30.81#ibcon#*after write, iclass 7, count 0 2006.225.08:25:30.81#ibcon#*before return 0, iclass 7, count 0 2006.225.08:25:30.81#ibcon#after mode 2 write, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:25:30.81#ibcon#end of loop, iclass 7 iclrec 2 cls_cnt 0 2006.225.08:25:30.81#ibcon#about to clear, iclass 7 cls_cnt 0 2006.225.08:25:30.81#ibcon#cleared, iclass 7 cls_cnt 0 2006.225.08:25:30.81$vc4f8/vblo=2,640.99 2006.225.08:25:30.81#ibcon#iclass 11 nclrec 1 cls_cnt 2 2006.225.08:25:30.81#ibcon#iclass 11 iclrec 1 cls_cnt 2 2006.225.08:25:30.81#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:30.81#ibcon#before find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:25:30.81#ibcon#after find_delay mode 2, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:25:30.81#ibcon#before mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:25:30.81#ibcon#enter wrdev, iclass 11, count 0 2006.225.08:25:30.81#ibcon#first serial, iclass 11, count 0 2006.225.08:25:30.81#ibcon#enter sib2, iclass 11, count 0 2006.225.08:25:30.81#ibcon#flushed, iclass 11, count 0 2006.225.08:25:30.81#ibcon#about to write, iclass 11, count 0 2006.225.08:25:30.81#ibcon#wrote, iclass 11, count 0 2006.225.08:25:30.81#ibcon#about to read 3, iclass 11, count 0 2006.225.08:25:30.83#ibcon#read 3, iclass 11, count 0 2006.225.08:25:30.83#ibcon#about to read 4, iclass 11, count 0 2006.225.08:25:30.83#ibcon#read 4, iclass 11, count 0 2006.225.08:25:30.83#ibcon#about to read 5, iclass 11, count 0 2006.225.08:25:30.83#ibcon#read 5, iclass 11, count 0 2006.225.08:25:30.83#ibcon#about to read 6, iclass 11, count 0 2006.225.08:25:30.83#ibcon#read 6, iclass 11, count 0 2006.225.08:25:30.83#ibcon#end of sib2, iclass 11, count 0 2006.225.08:25:30.83#ibcon#*mode == 0, iclass 11, count 0 2006.225.08:25:30.83#ibcon#*mode == 0 && serial, iclass 11, count 0 2006.225.08:25:30.83#ibcon#[28=FRQ=02,640.99\r\n] 2006.225.08:25:30.83#ibcon#*before write, iclass 11, count 0 2006.225.08:25:30.83#ibcon#enter sib2, iclass 11, count 0 2006.225.08:25:30.83#ibcon#flushed, iclass 11, count 0 2006.225.08:25:30.83#ibcon#about to write, iclass 11, count 0 2006.225.08:25:30.83#ibcon#wrote, iclass 11, count 0 2006.225.08:25:30.83#ibcon#about to read 3, iclass 11, count 0 2006.225.08:25:30.87#ibcon#read 3, iclass 11, count 0 2006.225.08:25:30.87#ibcon#about to read 4, iclass 11, count 0 2006.225.08:25:30.87#ibcon#read 4, iclass 11, count 0 2006.225.08:25:30.87#ibcon#about to read 5, iclass 11, count 0 2006.225.08:25:30.87#ibcon#read 5, iclass 11, count 0 2006.225.08:25:30.87#ibcon#about to read 6, iclass 11, count 0 2006.225.08:25:30.87#ibcon#read 6, iclass 11, count 0 2006.225.08:25:30.87#ibcon#end of sib2, iclass 11, count 0 2006.225.08:25:30.87#ibcon#*after write, iclass 11, count 0 2006.225.08:25:30.87#ibcon#*before return 0, iclass 11, count 0 2006.225.08:25:30.87#ibcon#after mode 2 write, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:25:30.87#ibcon#end of loop, iclass 11 iclrec 1 cls_cnt 0 2006.225.08:25:30.87#ibcon#about to clear, iclass 11 cls_cnt 0 2006.225.08:25:30.87#ibcon#cleared, iclass 11 cls_cnt 0 2006.225.08:25:30.87$vc4f8/vb=2,4 2006.225.08:25:30.87#ibcon#iclass 13 nclrec 2 cls_cnt 3 2006.225.08:25:30.87#ibcon#iclass 13 iclrec 1 cls_cnt 3 2006.225.08:25:30.87#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:30.87#ibcon#before find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:25:30.93#ibcon#after find_delay mode 2, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:25:30.93#ibcon#before mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:25:30.93#ibcon#enter wrdev, iclass 13, count 2 2006.225.08:25:30.93#ibcon#first serial, iclass 13, count 2 2006.225.08:25:30.93#ibcon#enter sib2, iclass 13, count 2 2006.225.08:25:30.93#ibcon#flushed, iclass 13, count 2 2006.225.08:25:30.93#ibcon#about to write, iclass 13, count 2 2006.225.08:25:30.93#ibcon#wrote, iclass 13, count 2 2006.225.08:25:30.93#ibcon#about to read 3, iclass 13, count 2 2006.225.08:25:30.95#ibcon#read 3, iclass 13, count 2 2006.225.08:25:30.95#ibcon#about to read 4, iclass 13, count 2 2006.225.08:25:30.95#ibcon#read 4, iclass 13, count 2 2006.225.08:25:30.95#ibcon#about to read 5, iclass 13, count 2 2006.225.08:25:30.95#ibcon#read 5, iclass 13, count 2 2006.225.08:25:30.95#ibcon#about to read 6, iclass 13, count 2 2006.225.08:25:30.95#ibcon#read 6, iclass 13, count 2 2006.225.08:25:30.95#ibcon#end of sib2, iclass 13, count 2 2006.225.08:25:30.95#ibcon#*mode == 0, iclass 13, count 2 2006.225.08:25:30.95#ibcon#*mode == 0 && serial, iclass 13, count 2 2006.225.08:25:30.95#ibcon#[27=AT02-04\r\n] 2006.225.08:25:30.95#ibcon#*before write, iclass 13, count 2 2006.225.08:25:30.95#ibcon#enter sib2, iclass 13, count 2 2006.225.08:25:30.95#ibcon#flushed, iclass 13, count 2 2006.225.08:25:30.95#ibcon#about to write, iclass 13, count 2 2006.225.08:25:30.95#ibcon#wrote, iclass 13, count 2 2006.225.08:25:30.95#ibcon#about to read 3, iclass 13, count 2 2006.225.08:25:30.98#ibcon#read 3, iclass 13, count 2 2006.225.08:25:30.98#ibcon#about to read 4, iclass 13, count 2 2006.225.08:25:30.98#ibcon#read 4, iclass 13, count 2 2006.225.08:25:30.98#ibcon#about to read 5, iclass 13, count 2 2006.225.08:25:30.98#ibcon#read 5, iclass 13, count 2 2006.225.08:25:30.98#ibcon#about to read 6, iclass 13, count 2 2006.225.08:25:30.98#ibcon#read 6, iclass 13, count 2 2006.225.08:25:30.98#ibcon#end of sib2, iclass 13, count 2 2006.225.08:25:30.98#ibcon#*after write, iclass 13, count 2 2006.225.08:25:30.98#ibcon#*before return 0, iclass 13, count 2 2006.225.08:25:30.98#ibcon#after mode 2 write, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:25:30.98#ibcon#end of loop, iclass 13 iclrec 1 cls_cnt 2 2006.225.08:25:30.98#ibcon#iclass 13 iclrec 2 cls_cnt 2 2006.225.08:25:30.98#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:30.98#ibcon#before find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:25:31.10#ibcon#after find_delay mode 2, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:25:31.10#ibcon#before mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:25:31.10#ibcon#enter wrdev, iclass 13, count 0 2006.225.08:25:31.10#ibcon#first serial, iclass 13, count 0 2006.225.08:25:31.10#ibcon#enter sib2, iclass 13, count 0 2006.225.08:25:31.10#ibcon#flushed, iclass 13, count 0 2006.225.08:25:31.10#ibcon#about to write, iclass 13, count 0 2006.225.08:25:31.10#ibcon#wrote, iclass 13, count 0 2006.225.08:25:31.10#ibcon#about to read 3, iclass 13, count 0 2006.225.08:25:31.12#ibcon#read 3, iclass 13, count 0 2006.225.08:25:31.12#ibcon#about to read 4, iclass 13, count 0 2006.225.08:25:31.12#ibcon#read 4, iclass 13, count 0 2006.225.08:25:31.12#ibcon#about to read 5, iclass 13, count 0 2006.225.08:25:31.12#ibcon#read 5, iclass 13, count 0 2006.225.08:25:31.12#ibcon#about to read 6, iclass 13, count 0 2006.225.08:25:31.12#ibcon#read 6, iclass 13, count 0 2006.225.08:25:31.12#ibcon#end of sib2, iclass 13, count 0 2006.225.08:25:31.12#ibcon#*mode == 0, iclass 13, count 0 2006.225.08:25:31.12#ibcon#*mode == 0 && serial, iclass 13, count 0 2006.225.08:25:31.12#ibcon#[27=USB\r\n] 2006.225.08:25:31.12#ibcon#*before write, iclass 13, count 0 2006.225.08:25:31.12#ibcon#enter sib2, iclass 13, count 0 2006.225.08:25:31.12#ibcon#flushed, iclass 13, count 0 2006.225.08:25:31.12#ibcon#about to write, iclass 13, count 0 2006.225.08:25:31.12#ibcon#wrote, iclass 13, count 0 2006.225.08:25:31.12#ibcon#about to read 3, iclass 13, count 0 2006.225.08:25:31.15#ibcon#read 3, iclass 13, count 0 2006.225.08:25:31.15#ibcon#about to read 4, iclass 13, count 0 2006.225.08:25:31.15#ibcon#read 4, iclass 13, count 0 2006.225.08:25:31.15#ibcon#about to read 5, iclass 13, count 0 2006.225.08:25:31.15#ibcon#read 5, iclass 13, count 0 2006.225.08:25:31.15#ibcon#about to read 6, iclass 13, count 0 2006.225.08:25:31.15#ibcon#read 6, iclass 13, count 0 2006.225.08:25:31.15#ibcon#end of sib2, iclass 13, count 0 2006.225.08:25:31.15#ibcon#*after write, iclass 13, count 0 2006.225.08:25:31.15#ibcon#*before return 0, iclass 13, count 0 2006.225.08:25:31.15#ibcon#after mode 2 write, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:25:31.15#ibcon#end of loop, iclass 13 iclrec 2 cls_cnt 0 2006.225.08:25:31.15#ibcon#about to clear, iclass 13 cls_cnt 0 2006.225.08:25:31.15#ibcon#cleared, iclass 13 cls_cnt 0 2006.225.08:25:31.15$vc4f8/vblo=3,656.99 2006.225.08:25:31.15#ibcon#iclass 15 nclrec 1 cls_cnt 2 2006.225.08:25:31.15#ibcon#iclass 15 iclrec 1 cls_cnt 2 2006.225.08:25:31.15#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:31.15#ibcon#before find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:25:31.15#ibcon#after find_delay mode 2, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:25:31.15#ibcon#before mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:25:31.15#ibcon#enter wrdev, iclass 15, count 0 2006.225.08:25:31.15#ibcon#first serial, iclass 15, count 0 2006.225.08:25:31.15#ibcon#enter sib2, iclass 15, count 0 2006.225.08:25:31.15#ibcon#flushed, iclass 15, count 0 2006.225.08:25:31.15#ibcon#about to write, iclass 15, count 0 2006.225.08:25:31.15#ibcon#wrote, iclass 15, count 0 2006.225.08:25:31.15#ibcon#about to read 3, iclass 15, count 0 2006.225.08:25:31.17#ibcon#read 3, iclass 15, count 0 2006.225.08:25:31.17#ibcon#about to read 4, iclass 15, count 0 2006.225.08:25:31.17#ibcon#read 4, iclass 15, count 0 2006.225.08:25:31.17#ibcon#about to read 5, iclass 15, count 0 2006.225.08:25:31.17#ibcon#read 5, iclass 15, count 0 2006.225.08:25:31.17#ibcon#about to read 6, iclass 15, count 0 2006.225.08:25:31.17#ibcon#read 6, iclass 15, count 0 2006.225.08:25:31.17#ibcon#end of sib2, iclass 15, count 0 2006.225.08:25:31.17#ibcon#*mode == 0, iclass 15, count 0 2006.225.08:25:31.17#ibcon#*mode == 0 && serial, iclass 15, count 0 2006.225.08:25:31.17#ibcon#[28=FRQ=03,656.99\r\n] 2006.225.08:25:31.17#ibcon#*before write, iclass 15, count 0 2006.225.08:25:31.17#ibcon#enter sib2, iclass 15, count 0 2006.225.08:25:31.17#ibcon#flushed, iclass 15, count 0 2006.225.08:25:31.17#ibcon#about to write, iclass 15, count 0 2006.225.08:25:31.17#ibcon#wrote, iclass 15, count 0 2006.225.08:25:31.17#ibcon#about to read 3, iclass 15, count 0 2006.225.08:25:31.21#ibcon#read 3, iclass 15, count 0 2006.225.08:25:31.21#ibcon#about to read 4, iclass 15, count 0 2006.225.08:25:31.21#ibcon#read 4, iclass 15, count 0 2006.225.08:25:31.21#ibcon#about to read 5, iclass 15, count 0 2006.225.08:25:31.21#ibcon#read 5, iclass 15, count 0 2006.225.08:25:31.21#ibcon#about to read 6, iclass 15, count 0 2006.225.08:25:31.21#ibcon#read 6, iclass 15, count 0 2006.225.08:25:31.21#ibcon#end of sib2, iclass 15, count 0 2006.225.08:25:31.21#ibcon#*after write, iclass 15, count 0 2006.225.08:25:31.21#ibcon#*before return 0, iclass 15, count 0 2006.225.08:25:31.21#ibcon#after mode 2 write, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:25:31.21#ibcon#end of loop, iclass 15 iclrec 1 cls_cnt 0 2006.225.08:25:31.21#ibcon#about to clear, iclass 15 cls_cnt 0 2006.225.08:25:31.21#ibcon#cleared, iclass 15 cls_cnt 0 2006.225.08:25:31.21$vc4f8/vb=3,4 2006.225.08:25:31.21#ibcon#iclass 17 nclrec 2 cls_cnt 3 2006.225.08:25:31.21#ibcon#iclass 17 iclrec 1 cls_cnt 3 2006.225.08:25:31.21#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:31.21#ibcon#before find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:25:31.27#ibcon#after find_delay mode 2, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:25:31.27#ibcon#before mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:25:31.27#ibcon#enter wrdev, iclass 17, count 2 2006.225.08:25:31.27#ibcon#first serial, iclass 17, count 2 2006.225.08:25:31.27#ibcon#enter sib2, iclass 17, count 2 2006.225.08:25:31.27#ibcon#flushed, iclass 17, count 2 2006.225.08:25:31.27#ibcon#about to write, iclass 17, count 2 2006.225.08:25:31.27#ibcon#wrote, iclass 17, count 2 2006.225.08:25:31.27#ibcon#about to read 3, iclass 17, count 2 2006.225.08:25:31.29#ibcon#read 3, iclass 17, count 2 2006.225.08:25:31.29#ibcon#about to read 4, iclass 17, count 2 2006.225.08:25:31.29#ibcon#read 4, iclass 17, count 2 2006.225.08:25:31.29#ibcon#about to read 5, iclass 17, count 2 2006.225.08:25:31.29#ibcon#read 5, iclass 17, count 2 2006.225.08:25:31.29#ibcon#about to read 6, iclass 17, count 2 2006.225.08:25:31.29#ibcon#read 6, iclass 17, count 2 2006.225.08:25:31.29#ibcon#end of sib2, iclass 17, count 2 2006.225.08:25:31.29#ibcon#*mode == 0, iclass 17, count 2 2006.225.08:25:31.29#ibcon#*mode == 0 && serial, iclass 17, count 2 2006.225.08:25:31.29#ibcon#[27=AT03-04\r\n] 2006.225.08:25:31.29#ibcon#*before write, iclass 17, count 2 2006.225.08:25:31.29#ibcon#enter sib2, iclass 17, count 2 2006.225.08:25:31.29#ibcon#flushed, iclass 17, count 2 2006.225.08:25:31.29#ibcon#about to write, iclass 17, count 2 2006.225.08:25:31.29#ibcon#wrote, iclass 17, count 2 2006.225.08:25:31.29#ibcon#about to read 3, iclass 17, count 2 2006.225.08:25:31.32#ibcon#read 3, iclass 17, count 2 2006.225.08:25:31.32#ibcon#about to read 4, iclass 17, count 2 2006.225.08:25:31.32#ibcon#read 4, iclass 17, count 2 2006.225.08:25:31.32#ibcon#about to read 5, iclass 17, count 2 2006.225.08:25:31.32#ibcon#read 5, iclass 17, count 2 2006.225.08:25:31.32#ibcon#about to read 6, iclass 17, count 2 2006.225.08:25:31.32#ibcon#read 6, iclass 17, count 2 2006.225.08:25:31.32#ibcon#end of sib2, iclass 17, count 2 2006.225.08:25:31.32#ibcon#*after write, iclass 17, count 2 2006.225.08:25:31.32#ibcon#*before return 0, iclass 17, count 2 2006.225.08:25:31.32#ibcon#after mode 2 write, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:25:31.32#ibcon#end of loop, iclass 17 iclrec 1 cls_cnt 2 2006.225.08:25:31.32#ibcon#iclass 17 iclrec 2 cls_cnt 2 2006.225.08:25:31.32#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:31.32#ibcon#before find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:25:31.44#ibcon#after find_delay mode 2, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:25:31.44#ibcon#before mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:25:31.44#ibcon#enter wrdev, iclass 17, count 0 2006.225.08:25:31.44#ibcon#first serial, iclass 17, count 0 2006.225.08:25:31.44#ibcon#enter sib2, iclass 17, count 0 2006.225.08:25:31.44#ibcon#flushed, iclass 17, count 0 2006.225.08:25:31.44#ibcon#about to write, iclass 17, count 0 2006.225.08:25:31.44#ibcon#wrote, iclass 17, count 0 2006.225.08:25:31.44#ibcon#about to read 3, iclass 17, count 0 2006.225.08:25:31.46#ibcon#read 3, iclass 17, count 0 2006.225.08:25:31.46#ibcon#about to read 4, iclass 17, count 0 2006.225.08:25:31.46#ibcon#read 4, iclass 17, count 0 2006.225.08:25:31.46#ibcon#about to read 5, iclass 17, count 0 2006.225.08:25:31.46#ibcon#read 5, iclass 17, count 0 2006.225.08:25:31.46#ibcon#about to read 6, iclass 17, count 0 2006.225.08:25:31.46#ibcon#read 6, iclass 17, count 0 2006.225.08:25:31.46#ibcon#end of sib2, iclass 17, count 0 2006.225.08:25:31.46#ibcon#*mode == 0, iclass 17, count 0 2006.225.08:25:31.46#ibcon#*mode == 0 && serial, iclass 17, count 0 2006.225.08:25:31.46#ibcon#[27=USB\r\n] 2006.225.08:25:31.46#ibcon#*before write, iclass 17, count 0 2006.225.08:25:31.46#ibcon#enter sib2, iclass 17, count 0 2006.225.08:25:31.46#ibcon#flushed, iclass 17, count 0 2006.225.08:25:31.46#ibcon#about to write, iclass 17, count 0 2006.225.08:25:31.46#ibcon#wrote, iclass 17, count 0 2006.225.08:25:31.46#ibcon#about to read 3, iclass 17, count 0 2006.225.08:25:31.49#ibcon#read 3, iclass 17, count 0 2006.225.08:25:31.49#ibcon#about to read 4, iclass 17, count 0 2006.225.08:25:31.49#ibcon#read 4, iclass 17, count 0 2006.225.08:25:31.49#ibcon#about to read 5, iclass 17, count 0 2006.225.08:25:31.49#ibcon#read 5, iclass 17, count 0 2006.225.08:25:31.49#ibcon#about to read 6, iclass 17, count 0 2006.225.08:25:31.49#ibcon#read 6, iclass 17, count 0 2006.225.08:25:31.49#ibcon#end of sib2, iclass 17, count 0 2006.225.08:25:31.49#ibcon#*after write, iclass 17, count 0 2006.225.08:25:31.49#ibcon#*before return 0, iclass 17, count 0 2006.225.08:25:31.49#ibcon#after mode 2 write, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:25:31.49#ibcon#end of loop, iclass 17 iclrec 2 cls_cnt 0 2006.225.08:25:31.49#ibcon#about to clear, iclass 17 cls_cnt 0 2006.225.08:25:31.49#ibcon#cleared, iclass 17 cls_cnt 0 2006.225.08:25:31.49$vc4f8/vblo=4,712.99 2006.225.08:25:31.49#ibcon#iclass 19 nclrec 1 cls_cnt 2 2006.225.08:25:31.49#ibcon#iclass 19 iclrec 1 cls_cnt 2 2006.225.08:25:31.49#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:31.49#ibcon#before find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:25:31.49#ibcon#after find_delay mode 2, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:25:31.49#ibcon#before mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:25:31.49#ibcon#enter wrdev, iclass 19, count 0 2006.225.08:25:31.49#ibcon#first serial, iclass 19, count 0 2006.225.08:25:31.49#ibcon#enter sib2, iclass 19, count 0 2006.225.08:25:31.49#ibcon#flushed, iclass 19, count 0 2006.225.08:25:31.49#ibcon#about to write, iclass 19, count 0 2006.225.08:25:31.49#ibcon#wrote, iclass 19, count 0 2006.225.08:25:31.49#ibcon#about to read 3, iclass 19, count 0 2006.225.08:25:31.51#ibcon#read 3, iclass 19, count 0 2006.225.08:25:31.51#ibcon#about to read 4, iclass 19, count 0 2006.225.08:25:31.51#ibcon#read 4, iclass 19, count 0 2006.225.08:25:31.51#ibcon#about to read 5, iclass 19, count 0 2006.225.08:25:31.51#ibcon#read 5, iclass 19, count 0 2006.225.08:25:31.51#ibcon#about to read 6, iclass 19, count 0 2006.225.08:25:31.51#ibcon#read 6, iclass 19, count 0 2006.225.08:25:31.51#ibcon#end of sib2, iclass 19, count 0 2006.225.08:25:31.51#ibcon#*mode == 0, iclass 19, count 0 2006.225.08:25:31.51#ibcon#*mode == 0 && serial, iclass 19, count 0 2006.225.08:25:31.51#ibcon#[28=FRQ=04,712.99\r\n] 2006.225.08:25:31.51#ibcon#*before write, iclass 19, count 0 2006.225.08:25:31.51#ibcon#enter sib2, iclass 19, count 0 2006.225.08:25:31.51#ibcon#flushed, iclass 19, count 0 2006.225.08:25:31.51#ibcon#about to write, iclass 19, count 0 2006.225.08:25:31.51#ibcon#wrote, iclass 19, count 0 2006.225.08:25:31.51#ibcon#about to read 3, iclass 19, count 0 2006.225.08:25:31.55#ibcon#read 3, iclass 19, count 0 2006.225.08:25:31.55#ibcon#about to read 4, iclass 19, count 0 2006.225.08:25:31.55#ibcon#read 4, iclass 19, count 0 2006.225.08:25:31.55#ibcon#about to read 5, iclass 19, count 0 2006.225.08:25:31.55#ibcon#read 5, iclass 19, count 0 2006.225.08:25:31.55#ibcon#about to read 6, iclass 19, count 0 2006.225.08:25:31.55#ibcon#read 6, iclass 19, count 0 2006.225.08:25:31.55#ibcon#end of sib2, iclass 19, count 0 2006.225.08:25:31.55#ibcon#*after write, iclass 19, count 0 2006.225.08:25:31.55#ibcon#*before return 0, iclass 19, count 0 2006.225.08:25:31.55#ibcon#after mode 2 write, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:25:31.55#ibcon#end of loop, iclass 19 iclrec 1 cls_cnt 0 2006.225.08:25:31.55#ibcon#about to clear, iclass 19 cls_cnt 0 2006.225.08:25:31.55#ibcon#cleared, iclass 19 cls_cnt 0 2006.225.08:25:31.55$vc4f8/vb=4,4 2006.225.08:25:31.55#ibcon#iclass 21 nclrec 2 cls_cnt 3 2006.225.08:25:31.55#ibcon#iclass 21 iclrec 1 cls_cnt 3 2006.225.08:25:31.55#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:31.55#ibcon#before find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:25:31.61#ibcon#after find_delay mode 2, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:25:31.61#ibcon#before mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:25:31.61#ibcon#enter wrdev, iclass 21, count 2 2006.225.08:25:31.61#ibcon#first serial, iclass 21, count 2 2006.225.08:25:31.61#ibcon#enter sib2, iclass 21, count 2 2006.225.08:25:31.61#ibcon#flushed, iclass 21, count 2 2006.225.08:25:31.61#ibcon#about to write, iclass 21, count 2 2006.225.08:25:31.61#ibcon#wrote, iclass 21, count 2 2006.225.08:25:31.61#ibcon#about to read 3, iclass 21, count 2 2006.225.08:25:31.63#ibcon#read 3, iclass 21, count 2 2006.225.08:25:31.63#ibcon#about to read 4, iclass 21, count 2 2006.225.08:25:31.63#ibcon#read 4, iclass 21, count 2 2006.225.08:25:31.63#ibcon#about to read 5, iclass 21, count 2 2006.225.08:25:31.63#ibcon#read 5, iclass 21, count 2 2006.225.08:25:31.63#ibcon#about to read 6, iclass 21, count 2 2006.225.08:25:31.63#ibcon#read 6, iclass 21, count 2 2006.225.08:25:31.63#ibcon#end of sib2, iclass 21, count 2 2006.225.08:25:31.63#ibcon#*mode == 0, iclass 21, count 2 2006.225.08:25:31.63#ibcon#*mode == 0 && serial, iclass 21, count 2 2006.225.08:25:31.63#ibcon#[27=AT04-04\r\n] 2006.225.08:25:31.63#ibcon#*before write, iclass 21, count 2 2006.225.08:25:31.63#ibcon#enter sib2, iclass 21, count 2 2006.225.08:25:31.63#ibcon#flushed, iclass 21, count 2 2006.225.08:25:31.63#ibcon#about to write, iclass 21, count 2 2006.225.08:25:31.63#ibcon#wrote, iclass 21, count 2 2006.225.08:25:31.63#ibcon#about to read 3, iclass 21, count 2 2006.225.08:25:31.66#ibcon#read 3, iclass 21, count 2 2006.225.08:25:31.66#ibcon#about to read 4, iclass 21, count 2 2006.225.08:25:31.66#ibcon#read 4, iclass 21, count 2 2006.225.08:25:31.66#ibcon#about to read 5, iclass 21, count 2 2006.225.08:25:31.66#ibcon#read 5, iclass 21, count 2 2006.225.08:25:31.66#ibcon#about to read 6, iclass 21, count 2 2006.225.08:25:31.66#ibcon#read 6, iclass 21, count 2 2006.225.08:25:31.66#ibcon#end of sib2, iclass 21, count 2 2006.225.08:25:31.66#ibcon#*after write, iclass 21, count 2 2006.225.08:25:31.66#ibcon#*before return 0, iclass 21, count 2 2006.225.08:25:31.66#ibcon#after mode 2 write, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:25:31.66#ibcon#end of loop, iclass 21 iclrec 1 cls_cnt 2 2006.225.08:25:31.66#ibcon#iclass 21 iclrec 2 cls_cnt 2 2006.225.08:25:31.66#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:31.66#ibcon#before find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:25:31.78#ibcon#after find_delay mode 2, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:25:31.78#ibcon#before mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:25:31.78#ibcon#enter wrdev, iclass 21, count 0 2006.225.08:25:31.78#ibcon#first serial, iclass 21, count 0 2006.225.08:25:31.78#ibcon#enter sib2, iclass 21, count 0 2006.225.08:25:31.78#ibcon#flushed, iclass 21, count 0 2006.225.08:25:31.78#ibcon#about to write, iclass 21, count 0 2006.225.08:25:31.78#ibcon#wrote, iclass 21, count 0 2006.225.08:25:31.78#ibcon#about to read 3, iclass 21, count 0 2006.225.08:25:31.80#ibcon#read 3, iclass 21, count 0 2006.225.08:25:31.80#ibcon#about to read 4, iclass 21, count 0 2006.225.08:25:31.80#ibcon#read 4, iclass 21, count 0 2006.225.08:25:31.80#ibcon#about to read 5, iclass 21, count 0 2006.225.08:25:31.80#ibcon#read 5, iclass 21, count 0 2006.225.08:25:31.80#ibcon#about to read 6, iclass 21, count 0 2006.225.08:25:31.80#ibcon#read 6, iclass 21, count 0 2006.225.08:25:31.80#ibcon#end of sib2, iclass 21, count 0 2006.225.08:25:31.80#ibcon#*mode == 0, iclass 21, count 0 2006.225.08:25:31.80#ibcon#*mode == 0 && serial, iclass 21, count 0 2006.225.08:25:31.80#ibcon#[27=USB\r\n] 2006.225.08:25:31.80#ibcon#*before write, iclass 21, count 0 2006.225.08:25:31.80#ibcon#enter sib2, iclass 21, count 0 2006.225.08:25:31.80#ibcon#flushed, iclass 21, count 0 2006.225.08:25:31.80#ibcon#about to write, iclass 21, count 0 2006.225.08:25:31.80#ibcon#wrote, iclass 21, count 0 2006.225.08:25:31.80#ibcon#about to read 3, iclass 21, count 0 2006.225.08:25:31.83#ibcon#read 3, iclass 21, count 0 2006.225.08:25:31.83#ibcon#about to read 4, iclass 21, count 0 2006.225.08:25:31.83#ibcon#read 4, iclass 21, count 0 2006.225.08:25:31.83#ibcon#about to read 5, iclass 21, count 0 2006.225.08:25:31.83#ibcon#read 5, iclass 21, count 0 2006.225.08:25:31.83#ibcon#about to read 6, iclass 21, count 0 2006.225.08:25:31.83#ibcon#read 6, iclass 21, count 0 2006.225.08:25:31.83#ibcon#end of sib2, iclass 21, count 0 2006.225.08:25:31.83#ibcon#*after write, iclass 21, count 0 2006.225.08:25:31.83#ibcon#*before return 0, iclass 21, count 0 2006.225.08:25:31.83#ibcon#after mode 2 write, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:25:31.83#ibcon#end of loop, iclass 21 iclrec 2 cls_cnt 0 2006.225.08:25:31.83#ibcon#about to clear, iclass 21 cls_cnt 0 2006.225.08:25:31.83#ibcon#cleared, iclass 21 cls_cnt 0 2006.225.08:25:31.83$vc4f8/vblo=5,744.99 2006.225.08:25:31.83#ibcon#iclass 23 nclrec 1 cls_cnt 2 2006.225.08:25:31.83#ibcon#iclass 23 iclrec 1 cls_cnt 2 2006.225.08:25:31.83#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:31.83#ibcon#before find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:25:31.83#ibcon#after find_delay mode 2, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:25:31.83#ibcon#before mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:25:31.83#ibcon#enter wrdev, iclass 23, count 0 2006.225.08:25:31.83#ibcon#first serial, iclass 23, count 0 2006.225.08:25:31.83#ibcon#enter sib2, iclass 23, count 0 2006.225.08:25:31.83#ibcon#flushed, iclass 23, count 0 2006.225.08:25:31.83#ibcon#about to write, iclass 23, count 0 2006.225.08:25:31.83#ibcon#wrote, iclass 23, count 0 2006.225.08:25:31.83#ibcon#about to read 3, iclass 23, count 0 2006.225.08:25:31.85#ibcon#read 3, iclass 23, count 0 2006.225.08:25:31.85#ibcon#about to read 4, iclass 23, count 0 2006.225.08:25:31.85#ibcon#read 4, iclass 23, count 0 2006.225.08:25:31.85#ibcon#about to read 5, iclass 23, count 0 2006.225.08:25:31.85#ibcon#read 5, iclass 23, count 0 2006.225.08:25:31.85#ibcon#about to read 6, iclass 23, count 0 2006.225.08:25:31.85#ibcon#read 6, iclass 23, count 0 2006.225.08:25:31.85#ibcon#end of sib2, iclass 23, count 0 2006.225.08:25:31.85#ibcon#*mode == 0, iclass 23, count 0 2006.225.08:25:31.85#ibcon#*mode == 0 && serial, iclass 23, count 0 2006.225.08:25:31.85#ibcon#[28=FRQ=05,744.99\r\n] 2006.225.08:25:31.85#ibcon#*before write, iclass 23, count 0 2006.225.08:25:31.85#ibcon#enter sib2, iclass 23, count 0 2006.225.08:25:31.85#ibcon#flushed, iclass 23, count 0 2006.225.08:25:31.85#ibcon#about to write, iclass 23, count 0 2006.225.08:25:31.85#ibcon#wrote, iclass 23, count 0 2006.225.08:25:31.85#ibcon#about to read 3, iclass 23, count 0 2006.225.08:25:31.89#ibcon#read 3, iclass 23, count 0 2006.225.08:25:31.89#ibcon#about to read 4, iclass 23, count 0 2006.225.08:25:31.89#ibcon#read 4, iclass 23, count 0 2006.225.08:25:31.89#ibcon#about to read 5, iclass 23, count 0 2006.225.08:25:31.89#ibcon#read 5, iclass 23, count 0 2006.225.08:25:31.89#ibcon#about to read 6, iclass 23, count 0 2006.225.08:25:31.89#ibcon#read 6, iclass 23, count 0 2006.225.08:25:31.89#ibcon#end of sib2, iclass 23, count 0 2006.225.08:25:31.89#ibcon#*after write, iclass 23, count 0 2006.225.08:25:31.89#ibcon#*before return 0, iclass 23, count 0 2006.225.08:25:31.89#ibcon#after mode 2 write, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:25:31.89#ibcon#end of loop, iclass 23 iclrec 1 cls_cnt 0 2006.225.08:25:31.89#ibcon#about to clear, iclass 23 cls_cnt 0 2006.225.08:25:31.89#ibcon#cleared, iclass 23 cls_cnt 0 2006.225.08:25:31.89$vc4f8/vb=5,4 2006.225.08:25:31.89#ibcon#iclass 25 nclrec 2 cls_cnt 3 2006.225.08:25:31.89#ibcon#iclass 25 iclrec 1 cls_cnt 3 2006.225.08:25:31.89#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:31.89#ibcon#before find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:25:31.95#ibcon#after find_delay mode 2, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:25:31.95#ibcon#before mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:25:31.95#ibcon#enter wrdev, iclass 25, count 2 2006.225.08:25:31.95#ibcon#first serial, iclass 25, count 2 2006.225.08:25:31.95#ibcon#enter sib2, iclass 25, count 2 2006.225.08:25:31.95#ibcon#flushed, iclass 25, count 2 2006.225.08:25:31.95#ibcon#about to write, iclass 25, count 2 2006.225.08:25:31.95#ibcon#wrote, iclass 25, count 2 2006.225.08:25:31.95#ibcon#about to read 3, iclass 25, count 2 2006.225.08:25:31.97#ibcon#read 3, iclass 25, count 2 2006.225.08:25:31.97#ibcon#about to read 4, iclass 25, count 2 2006.225.08:25:31.97#ibcon#read 4, iclass 25, count 2 2006.225.08:25:31.97#ibcon#about to read 5, iclass 25, count 2 2006.225.08:25:31.97#ibcon#read 5, iclass 25, count 2 2006.225.08:25:31.97#ibcon#about to read 6, iclass 25, count 2 2006.225.08:25:31.97#ibcon#read 6, iclass 25, count 2 2006.225.08:25:31.97#ibcon#end of sib2, iclass 25, count 2 2006.225.08:25:31.97#ibcon#*mode == 0, iclass 25, count 2 2006.225.08:25:31.97#ibcon#*mode == 0 && serial, iclass 25, count 2 2006.225.08:25:31.97#ibcon#[27=AT05-04\r\n] 2006.225.08:25:31.97#ibcon#*before write, iclass 25, count 2 2006.225.08:25:31.97#ibcon#enter sib2, iclass 25, count 2 2006.225.08:25:31.97#ibcon#flushed, iclass 25, count 2 2006.225.08:25:31.97#ibcon#about to write, iclass 25, count 2 2006.225.08:25:31.97#ibcon#wrote, iclass 25, count 2 2006.225.08:25:31.97#ibcon#about to read 3, iclass 25, count 2 2006.225.08:25:32.00#ibcon#read 3, iclass 25, count 2 2006.225.08:25:32.00#ibcon#about to read 4, iclass 25, count 2 2006.225.08:25:32.00#ibcon#read 4, iclass 25, count 2 2006.225.08:25:32.00#ibcon#about to read 5, iclass 25, count 2 2006.225.08:25:32.00#ibcon#read 5, iclass 25, count 2 2006.225.08:25:32.00#ibcon#about to read 6, iclass 25, count 2 2006.225.08:25:32.00#ibcon#read 6, iclass 25, count 2 2006.225.08:25:32.00#ibcon#end of sib2, iclass 25, count 2 2006.225.08:25:32.00#ibcon#*after write, iclass 25, count 2 2006.225.08:25:32.00#ibcon#*before return 0, iclass 25, count 2 2006.225.08:25:32.00#ibcon#after mode 2 write, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:25:32.00#ibcon#end of loop, iclass 25 iclrec 1 cls_cnt 2 2006.225.08:25:32.00#ibcon#iclass 25 iclrec 2 cls_cnt 2 2006.225.08:25:32.00#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:32.00#ibcon#before find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:25:32.12#ibcon#after find_delay mode 2, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:25:32.12#ibcon#before mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:25:32.12#ibcon#enter wrdev, iclass 25, count 0 2006.225.08:25:32.12#ibcon#first serial, iclass 25, count 0 2006.225.08:25:32.12#ibcon#enter sib2, iclass 25, count 0 2006.225.08:25:32.12#ibcon#flushed, iclass 25, count 0 2006.225.08:25:32.12#ibcon#about to write, iclass 25, count 0 2006.225.08:25:32.12#ibcon#wrote, iclass 25, count 0 2006.225.08:25:32.12#ibcon#about to read 3, iclass 25, count 0 2006.225.08:25:32.14#ibcon#read 3, iclass 25, count 0 2006.225.08:25:32.14#ibcon#about to read 4, iclass 25, count 0 2006.225.08:25:32.14#ibcon#read 4, iclass 25, count 0 2006.225.08:25:32.14#ibcon#about to read 5, iclass 25, count 0 2006.225.08:25:32.14#ibcon#read 5, iclass 25, count 0 2006.225.08:25:32.14#ibcon#about to read 6, iclass 25, count 0 2006.225.08:25:32.14#ibcon#read 6, iclass 25, count 0 2006.225.08:25:32.14#ibcon#end of sib2, iclass 25, count 0 2006.225.08:25:32.14#ibcon#*mode == 0, iclass 25, count 0 2006.225.08:25:32.14#ibcon#*mode == 0 && serial, iclass 25, count 0 2006.225.08:25:32.14#ibcon#[27=USB\r\n] 2006.225.08:25:32.14#ibcon#*before write, iclass 25, count 0 2006.225.08:25:32.14#ibcon#enter sib2, iclass 25, count 0 2006.225.08:25:32.14#ibcon#flushed, iclass 25, count 0 2006.225.08:25:32.14#ibcon#about to write, iclass 25, count 0 2006.225.08:25:32.14#ibcon#wrote, iclass 25, count 0 2006.225.08:25:32.14#ibcon#about to read 3, iclass 25, count 0 2006.225.08:25:32.17#ibcon#read 3, iclass 25, count 0 2006.225.08:25:32.17#ibcon#about to read 4, iclass 25, count 0 2006.225.08:25:32.17#ibcon#read 4, iclass 25, count 0 2006.225.08:25:32.17#ibcon#about to read 5, iclass 25, count 0 2006.225.08:25:32.17#ibcon#read 5, iclass 25, count 0 2006.225.08:25:32.17#ibcon#about to read 6, iclass 25, count 0 2006.225.08:25:32.17#ibcon#read 6, iclass 25, count 0 2006.225.08:25:32.17#ibcon#end of sib2, iclass 25, count 0 2006.225.08:25:32.17#ibcon#*after write, iclass 25, count 0 2006.225.08:25:32.17#ibcon#*before return 0, iclass 25, count 0 2006.225.08:25:32.17#ibcon#after mode 2 write, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:25:32.17#ibcon#end of loop, iclass 25 iclrec 2 cls_cnt 0 2006.225.08:25:32.17#ibcon#about to clear, iclass 25 cls_cnt 0 2006.225.08:25:32.17#ibcon#cleared, iclass 25 cls_cnt 0 2006.225.08:25:32.17$vc4f8/vblo=6,752.99 2006.225.08:25:32.17#ibcon#iclass 27 nclrec 1 cls_cnt 2 2006.225.08:25:32.17#ibcon#iclass 27 iclrec 1 cls_cnt 2 2006.225.08:25:32.17#ibcon#ireg 17 cls_cnt 0 2006.225.08:25:32.17#ibcon#before find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:25:32.17#ibcon#after find_delay mode 2, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:25:32.17#ibcon#before mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:25:32.17#ibcon#enter wrdev, iclass 27, count 0 2006.225.08:25:32.17#ibcon#first serial, iclass 27, count 0 2006.225.08:25:32.17#ibcon#enter sib2, iclass 27, count 0 2006.225.08:25:32.17#ibcon#flushed, iclass 27, count 0 2006.225.08:25:32.17#ibcon#about to write, iclass 27, count 0 2006.225.08:25:32.17#ibcon#wrote, iclass 27, count 0 2006.225.08:25:32.17#ibcon#about to read 3, iclass 27, count 0 2006.225.08:25:32.20#ibcon#read 3, iclass 27, count 0 2006.225.08:25:32.20#ibcon#about to read 4, iclass 27, count 0 2006.225.08:25:32.20#ibcon#read 4, iclass 27, count 0 2006.225.08:25:32.20#ibcon#about to read 5, iclass 27, count 0 2006.225.08:25:32.20#ibcon#read 5, iclass 27, count 0 2006.225.08:25:32.20#ibcon#about to read 6, iclass 27, count 0 2006.225.08:25:32.20#ibcon#read 6, iclass 27, count 0 2006.225.08:25:32.20#ibcon#end of sib2, iclass 27, count 0 2006.225.08:25:32.20#ibcon#*mode == 0, iclass 27, count 0 2006.225.08:25:32.20#ibcon#*mode == 0 && serial, iclass 27, count 0 2006.225.08:25:32.20#ibcon#[28=FRQ=06,752.99\r\n] 2006.225.08:25:32.20#ibcon#*before write, iclass 27, count 0 2006.225.08:25:32.20#ibcon#enter sib2, iclass 27, count 0 2006.225.08:25:32.20#ibcon#flushed, iclass 27, count 0 2006.225.08:25:32.20#ibcon#about to write, iclass 27, count 0 2006.225.08:25:32.20#ibcon#wrote, iclass 27, count 0 2006.225.08:25:32.20#ibcon#about to read 3, iclass 27, count 0 2006.225.08:25:32.24#ibcon#read 3, iclass 27, count 0 2006.225.08:25:32.24#ibcon#about to read 4, iclass 27, count 0 2006.225.08:25:32.24#ibcon#read 4, iclass 27, count 0 2006.225.08:25:32.24#ibcon#about to read 5, iclass 27, count 0 2006.225.08:25:32.24#ibcon#read 5, iclass 27, count 0 2006.225.08:25:32.24#ibcon#about to read 6, iclass 27, count 0 2006.225.08:25:32.24#ibcon#read 6, iclass 27, count 0 2006.225.08:25:32.24#ibcon#end of sib2, iclass 27, count 0 2006.225.08:25:32.24#ibcon#*after write, iclass 27, count 0 2006.225.08:25:32.24#ibcon#*before return 0, iclass 27, count 0 2006.225.08:25:32.24#ibcon#after mode 2 write, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:25:32.24#ibcon#end of loop, iclass 27 iclrec 1 cls_cnt 0 2006.225.08:25:32.24#ibcon#about to clear, iclass 27 cls_cnt 0 2006.225.08:25:32.24#ibcon#cleared, iclass 27 cls_cnt 0 2006.225.08:25:32.24$vc4f8/vb=6,4 2006.225.08:25:32.24#ibcon#iclass 29 nclrec 2 cls_cnt 3 2006.225.08:25:32.24#ibcon#iclass 29 iclrec 1 cls_cnt 3 2006.225.08:25:32.24#ibcon#ireg 11 cls_cnt 2 2006.225.08:25:32.24#ibcon#before find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:25:32.29#ibcon#after find_delay mode 2, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:25:32.29#ibcon#before mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:25:32.29#ibcon#enter wrdev, iclass 29, count 2 2006.225.08:25:32.29#ibcon#first serial, iclass 29, count 2 2006.225.08:25:32.29#ibcon#enter sib2, iclass 29, count 2 2006.225.08:25:32.29#ibcon#flushed, iclass 29, count 2 2006.225.08:25:32.29#ibcon#about to write, iclass 29, count 2 2006.225.08:25:32.29#ibcon#wrote, iclass 29, count 2 2006.225.08:25:32.29#ibcon#about to read 3, iclass 29, count 2 2006.225.08:25:32.31#ibcon#read 3, iclass 29, count 2 2006.225.08:25:32.31#ibcon#about to read 4, iclass 29, count 2 2006.225.08:25:32.31#ibcon#read 4, iclass 29, count 2 2006.225.08:25:32.31#ibcon#about to read 5, iclass 29, count 2 2006.225.08:25:32.31#ibcon#read 5, iclass 29, count 2 2006.225.08:25:32.31#ibcon#about to read 6, iclass 29, count 2 2006.225.08:25:32.31#ibcon#read 6, iclass 29, count 2 2006.225.08:25:32.31#ibcon#end of sib2, iclass 29, count 2 2006.225.08:25:32.31#ibcon#*mode == 0, iclass 29, count 2 2006.225.08:25:32.31#ibcon#*mode == 0 && serial, iclass 29, count 2 2006.225.08:25:32.31#ibcon#[27=AT06-04\r\n] 2006.225.08:25:32.31#ibcon#*before write, iclass 29, count 2 2006.225.08:25:32.31#ibcon#enter sib2, iclass 29, count 2 2006.225.08:25:32.31#ibcon#flushed, iclass 29, count 2 2006.225.08:25:32.31#ibcon#about to write, iclass 29, count 2 2006.225.08:25:32.31#ibcon#wrote, iclass 29, count 2 2006.225.08:25:32.31#ibcon#about to read 3, iclass 29, count 2 2006.225.08:25:32.34#ibcon#read 3, iclass 29, count 2 2006.225.08:25:32.34#ibcon#about to read 4, iclass 29, count 2 2006.225.08:25:32.34#ibcon#read 4, iclass 29, count 2 2006.225.08:25:32.34#ibcon#about to read 5, iclass 29, count 2 2006.225.08:25:32.34#ibcon#read 5, iclass 29, count 2 2006.225.08:25:32.34#ibcon#about to read 6, iclass 29, count 2 2006.225.08:25:32.34#ibcon#read 6, iclass 29, count 2 2006.225.08:25:32.34#ibcon#end of sib2, iclass 29, count 2 2006.225.08:25:32.34#ibcon#*after write, iclass 29, count 2 2006.225.08:25:32.34#ibcon#*before return 0, iclass 29, count 2 2006.225.08:25:32.34#ibcon#after mode 2 write, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:25:32.34#ibcon#end of loop, iclass 29 iclrec 1 cls_cnt 2 2006.225.08:25:32.34#ibcon#iclass 29 iclrec 2 cls_cnt 2 2006.225.08:25:32.34#ibcon#ireg 7 cls_cnt 0 2006.225.08:25:32.34#ibcon#before find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:25:32.46#ibcon#after find_delay mode 2, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:25:32.46#ibcon#before mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:25:32.46#ibcon#enter wrdev, iclass 29, count 0 2006.225.08:25:32.46#ibcon#first serial, iclass 29, count 0 2006.225.08:25:32.46#ibcon#enter sib2, iclass 29, count 0 2006.225.08:25:32.46#ibcon#flushed, iclass 29, count 0 2006.225.08:25:32.46#ibcon#about to write, iclass 29, count 0 2006.225.08:25:32.46#ibcon#wrote, iclass 29, count 0 2006.225.08:25:32.46#ibcon#about to read 3, iclass 29, count 0 2006.225.08:25:32.48#ibcon#read 3, iclass 29, count 0 2006.225.08:25:32.48#ibcon#about to read 4, iclass 29, count 0 2006.225.08:25:32.48#ibcon#read 4, iclass 29, count 0 2006.225.08:25:32.48#ibcon#about to read 5, iclass 29, count 0 2006.225.08:25:32.48#ibcon#read 5, iclass 29, count 0 2006.225.08:25:32.48#ibcon#about to read 6, iclass 29, count 0 2006.225.08:25:32.48#ibcon#read 6, iclass 29, count 0 2006.225.08:25:32.48#ibcon#end of sib2, iclass 29, count 0 2006.225.08:25:32.48#ibcon#*mode == 0, iclass 29, count 0 2006.225.08:25:32.48#ibcon#*mode == 0 && serial, iclass 29, count 0 2006.225.08:25:32.48#ibcon#[27=USB\r\n] 2006.225.08:25:32.48#ibcon#*before write, iclass 29, count 0 2006.225.08:25:32.48#ibcon#enter sib2, iclass 29, count 0 2006.225.08:25:32.48#ibcon#flushed, iclass 29, count 0 2006.225.08:25:32.48#ibcon#about to write, iclass 29, count 0 2006.225.08:25:32.48#ibcon#wrote, iclass 29, count 0 2006.225.08:25:32.48#ibcon#about to read 3, iclass 29, count 0 2006.225.08:25:32.51#ibcon#read 3, iclass 29, count 0 2006.225.08:25:32.51#ibcon#about to read 4, iclass 29, count 0 2006.225.08:25:32.51#ibcon#read 4, iclass 29, count 0 2006.225.08:25:32.51#ibcon#about to read 5, iclass 29, count 0 2006.225.08:25:32.51#ibcon#read 5, iclass 29, count 0 2006.225.08:25:32.51#ibcon#about to read 6, iclass 29, count 0 2006.225.08:25:32.51#ibcon#read 6, iclass 29, count 0 2006.225.08:25:32.51#ibcon#end of sib2, iclass 29, count 0 2006.225.08:25:32.51#ibcon#*after write, iclass 29, count 0 2006.225.08:25:32.51#ibcon#*before return 0, iclass 29, count 0 2006.225.08:25:32.51#ibcon#after mode 2 write, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:25:32.51#ibcon#end of loop, iclass 29 iclrec 2 cls_cnt 0 2006.225.08:25:32.51#ibcon#about to clear, iclass 29 cls_cnt 0 2006.225.08:25:32.51#ibcon#cleared, iclass 29 cls_cnt 0 2006.225.08:25:32.51$vc4f8/vabw=wide 2006.225.08:25:32.51#ibcon#iclass 31 nclrec 1 cls_cnt 2 2006.225.08:25:32.51#ibcon#iclass 31 iclrec 1 cls_cnt 2 2006.225.08:25:32.51#ibcon#ireg 8 cls_cnt 0 2006.225.08:25:32.51#ibcon#before find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:25:32.51#ibcon#after find_delay mode 2, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:25:32.51#ibcon#before mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:25:32.51#ibcon#enter wrdev, iclass 31, count 0 2006.225.08:25:32.51#ibcon#first serial, iclass 31, count 0 2006.225.08:25:32.51#ibcon#enter sib2, iclass 31, count 0 2006.225.08:25:32.51#ibcon#flushed, iclass 31, count 0 2006.225.08:25:32.51#ibcon#about to write, iclass 31, count 0 2006.225.08:25:32.51#ibcon#wrote, iclass 31, count 0 2006.225.08:25:32.51#ibcon#about to read 3, iclass 31, count 0 2006.225.08:25:32.53#ibcon#read 3, iclass 31, count 0 2006.225.08:25:32.53#ibcon#about to read 4, iclass 31, count 0 2006.225.08:25:32.53#ibcon#read 4, iclass 31, count 0 2006.225.08:25:32.53#ibcon#about to read 5, iclass 31, count 0 2006.225.08:25:32.53#ibcon#read 5, iclass 31, count 0 2006.225.08:25:32.53#ibcon#about to read 6, iclass 31, count 0 2006.225.08:25:32.53#ibcon#read 6, iclass 31, count 0 2006.225.08:25:32.53#ibcon#end of sib2, iclass 31, count 0 2006.225.08:25:32.53#ibcon#*mode == 0, iclass 31, count 0 2006.225.08:25:32.53#ibcon#*mode == 0 && serial, iclass 31, count 0 2006.225.08:25:32.53#ibcon#[25=BW32\r\n] 2006.225.08:25:32.53#ibcon#*before write, iclass 31, count 0 2006.225.08:25:32.53#ibcon#enter sib2, iclass 31, count 0 2006.225.08:25:32.53#ibcon#flushed, iclass 31, count 0 2006.225.08:25:32.53#ibcon#about to write, iclass 31, count 0 2006.225.08:25:32.53#ibcon#wrote, iclass 31, count 0 2006.225.08:25:32.53#ibcon#about to read 3, iclass 31, count 0 2006.225.08:25:32.56#ibcon#read 3, iclass 31, count 0 2006.225.08:25:32.56#ibcon#about to read 4, iclass 31, count 0 2006.225.08:25:32.56#ibcon#read 4, iclass 31, count 0 2006.225.08:25:32.56#ibcon#about to read 5, iclass 31, count 0 2006.225.08:25:32.56#ibcon#read 5, iclass 31, count 0 2006.225.08:25:32.56#ibcon#about to read 6, iclass 31, count 0 2006.225.08:25:32.56#ibcon#read 6, iclass 31, count 0 2006.225.08:25:32.56#ibcon#end of sib2, iclass 31, count 0 2006.225.08:25:32.56#ibcon#*after write, iclass 31, count 0 2006.225.08:25:32.56#ibcon#*before return 0, iclass 31, count 0 2006.225.08:25:32.56#ibcon#after mode 2 write, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:25:32.56#ibcon#end of loop, iclass 31 iclrec 1 cls_cnt 0 2006.225.08:25:32.56#ibcon#about to clear, iclass 31 cls_cnt 0 2006.225.08:25:32.56#ibcon#cleared, iclass 31 cls_cnt 0 2006.225.08:25:32.56$vc4f8/vbbw=wide 2006.225.08:25:32.56#ibcon#iclass 33 nclrec 1 cls_cnt 2 2006.225.08:25:32.56#ibcon#iclass 33 iclrec 1 cls_cnt 2 2006.225.08:25:32.56#ibcon#ireg 8 cls_cnt 0 2006.225.08:25:32.56#ibcon#before find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:25:32.63#ibcon#after find_delay mode 2, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:25:32.63#ibcon#before mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:25:32.63#ibcon#enter wrdev, iclass 33, count 0 2006.225.08:25:32.63#ibcon#first serial, iclass 33, count 0 2006.225.08:25:32.63#ibcon#enter sib2, iclass 33, count 0 2006.225.08:25:32.63#ibcon#flushed, iclass 33, count 0 2006.225.08:25:32.63#ibcon#about to write, iclass 33, count 0 2006.225.08:25:32.63#ibcon#wrote, iclass 33, count 0 2006.225.08:25:32.63#ibcon#about to read 3, iclass 33, count 0 2006.225.08:25:32.65#ibcon#read 3, iclass 33, count 0 2006.225.08:25:32.65#ibcon#about to read 4, iclass 33, count 0 2006.225.08:25:32.65#ibcon#read 4, iclass 33, count 0 2006.225.08:25:32.65#ibcon#about to read 5, iclass 33, count 0 2006.225.08:25:32.65#ibcon#read 5, iclass 33, count 0 2006.225.08:25:32.65#ibcon#about to read 6, iclass 33, count 0 2006.225.08:25:32.65#ibcon#read 6, iclass 33, count 0 2006.225.08:25:32.65#ibcon#end of sib2, iclass 33, count 0 2006.225.08:25:32.65#ibcon#*mode == 0, iclass 33, count 0 2006.225.08:25:32.65#ibcon#*mode == 0 && serial, iclass 33, count 0 2006.225.08:25:32.65#ibcon#[27=BW32\r\n] 2006.225.08:25:32.65#ibcon#*before write, iclass 33, count 0 2006.225.08:25:32.65#ibcon#enter sib2, iclass 33, count 0 2006.225.08:25:32.65#ibcon#flushed, iclass 33, count 0 2006.225.08:25:32.65#ibcon#about to write, iclass 33, count 0 2006.225.08:25:32.65#ibcon#wrote, iclass 33, count 0 2006.225.08:25:32.65#ibcon#about to read 3, iclass 33, count 0 2006.225.08:25:32.68#ibcon#read 3, iclass 33, count 0 2006.225.08:25:32.68#ibcon#about to read 4, iclass 33, count 0 2006.225.08:25:32.68#ibcon#read 4, iclass 33, count 0 2006.225.08:25:32.68#ibcon#about to read 5, iclass 33, count 0 2006.225.08:25:32.68#ibcon#read 5, iclass 33, count 0 2006.225.08:25:32.68#ibcon#about to read 6, iclass 33, count 0 2006.225.08:25:32.68#ibcon#read 6, iclass 33, count 0 2006.225.08:25:32.68#ibcon#end of sib2, iclass 33, count 0 2006.225.08:25:32.68#ibcon#*after write, iclass 33, count 0 2006.225.08:25:32.68#ibcon#*before return 0, iclass 33, count 0 2006.225.08:25:32.68#ibcon#after mode 2 write, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:25:32.68#ibcon#end of loop, iclass 33 iclrec 1 cls_cnt 0 2006.225.08:25:32.68#ibcon#about to clear, iclass 33 cls_cnt 0 2006.225.08:25:32.68#ibcon#cleared, iclass 33 cls_cnt 0 2006.225.08:25:32.68$4f8m12a/ifd4f 2006.225.08:25:32.68$ifd4f/lo= 2006.225.08:25:32.68$ifd4f/lo=lo1,7680.00,usb,rcp,1 2006.225.08:25:32.68$ifd4f/lo=lo2,1600.00,usb,rcp,1 2006.225.08:25:32.68$ifd4f/lo=lo3,8080.00,usb,rcp,1 2006.225.08:25:32.68$ifd4f/patch= 2006.225.08:25:32.68$ifd4f/patch=lo1,a1,a2,a3,a4 2006.225.08:25:32.68$ifd4f/patch=lo2,b1,b2,b3,b4,b5,b6 2006.225.08:25:32.68$ifd4f/patch=lo3,a5,a6,a7,a8 2006.225.08:25:32.68$4f8m12a/"form=m,16.000,1:2 2006.225.08:25:32.68$4f8m12a/"tpicd 2006.225.08:25:32.68$4f8m12a/echo=off 2006.225.08:25:32.68$4f8m12a/xlog=off 2006.225.08:25:32.68:!2006.225.08:26:00 2006.225.08:25:47.13#trakl#Source acquired 2006.225.08:25:48.13#flagr#flagr/antenna,acquired 2006.225.08:26:00.00:preob 2006.225.08:26:01.13/onsource/TRACKING 2006.225.08:26:01.13:!2006.225.08:26:10 2006.225.08:26:10.00:data_valid=on 2006.225.08:26:10.00:midob 2006.225.08:26:10.13/onsource/TRACKING 2006.225.08:26:10.13/wx/28.07,1003.4,76 2006.225.08:26:10.27/cable/+6.4064E-03 2006.225.08:26:11.36/va/01,08,usb,yes,29,31 2006.225.08:26:11.36/va/02,07,usb,yes,29,31 2006.225.08:26:11.36/va/03,06,usb,yes,31,31 2006.225.08:26:11.36/va/04,07,usb,yes,30,33 2006.225.08:26:11.36/va/05,07,usb,yes,32,34 2006.225.08:26:11.36/va/06,06,usb,yes,31,31 2006.225.08:26:11.36/va/07,06,usb,yes,32,32 2006.225.08:26:11.36/va/08,07,usb,yes,30,30 2006.225.08:26:11.59/valo/01,532.99,yes,locked 2006.225.08:26:11.59/valo/02,572.99,yes,locked 2006.225.08:26:11.59/valo/03,672.99,yes,locked 2006.225.08:26:11.59/valo/04,832.99,yes,locked 2006.225.08:26:11.59/valo/05,652.99,yes,locked 2006.225.08:26:11.59/valo/06,772.99,yes,locked 2006.225.08:26:11.59/valo/07,832.99,yes,locked 2006.225.08:26:11.59/valo/08,852.99,yes,locked 2006.225.08:26:12.68/vb/01,04,usb,yes,31,29 2006.225.08:26:12.68/vb/02,04,usb,yes,33,34 2006.225.08:26:12.68/vb/03,04,usb,yes,29,33 2006.225.08:26:12.68/vb/04,04,usb,yes,30,30 2006.225.08:26:12.68/vb/05,04,usb,yes,28,32 2006.225.08:26:12.68/vb/06,04,usb,yes,29,32 2006.225.08:26:12.68/vb/07,04,usb,yes,31,31 2006.225.08:26:12.68/vb/08,04,usb,yes,29,32 2006.225.08:26:12.91/vblo/01,632.99,yes,locked 2006.225.08:26:12.91/vblo/02,640.99,yes,locked 2006.225.08:26:12.91/vblo/03,656.99,yes,locked 2006.225.08:26:12.91/vblo/04,712.99,yes,locked 2006.225.08:26:12.91/vblo/05,744.99,yes,locked 2006.225.08:26:12.91/vblo/06,752.99,yes,locked 2006.225.08:26:12.91/vblo/07,734.99,yes,locked 2006.225.08:26:12.91/vblo/08,744.99,yes,locked 2006.225.08:26:13.06/vabw/8 2006.225.08:26:13.21/vbbw/8 2006.225.08:26:13.30/xfe/off,on,15.2 2006.225.08:26:13.68/ifatt/23,28,28,28 2006.225.08:26:14.08/fmout-gps/S +4.55E-07 2006.225.08:26:14.12:!2006.225.08:27:20 2006.225.08:27:20.00:data_valid=off 2006.225.08:27:20.00:postob 2006.225.08:27:20.11/cable/+6.4036E-03 2006.225.08:27:20.11/wx/28.07,1003.4,77 2006.225.08:27:21.07/fmout-gps/S +4.59E-07 2006.225.08:27:21.07:checkk5last 2006.225.08:27:21.07&checkk5last/chk_obsdata=1 2006.225.08:27:21.07&checkk5last/chk_obsdata=2 2006.225.08:27:21.07&checkk5last/chk_obsdata=3 2006.225.08:27:21.07&checkk5last/chk_obsdata=4 2006.225.08:27:21.07&checkk5last/k5log=1 2006.225.08:27:21.07&checkk5last/k5log=2 2006.225.08:27:21.07&checkk5last/k5log=3 2006.225.08:27:21.07&checkk5last/k5log=4 2006.225.08:27:21.07&checkk5last/obsinfo 2006.225.08:27:21.45/chk_obsdata//k5ts1/T2250826??a.dat file size is correct (nominal:560MB, actual:552MB). 2006.225.08:27:21.82/chk_obsdata//k5ts2/T2250826??b.dat file size is correct (nominal:560MB, actual:552MB). 2006.225.08:27:22.21/chk_obsdata//k5ts3/T2250826??c.dat file size is correct (nominal:560MB, actual:552MB). 2006.225.08:27:22.57/chk_obsdata//k5ts4/T2250826??d.dat file size is correct (nominal:560MB, actual:552MB). 2006.225.08:27:23.26/k5log//k5ts1_log_newline 2006.225.08:27:23.95/k5log//k5ts2_log_newline 2006.225.08:27:24.63/k5log//k5ts3_log_newline 2006.225.08:27:25.31/k5log//k5ts4_log_newline 2006.225.08:27:25.34/obsinfo/Obs information was written on file(obsinfo.tmp). 2006.225.08:27:25.34:sched_end 2006.225.08:27:25.34&sched_end/stopcheck 2006.225.08:27:25.34&stopcheck/sy=killall check_fsrun.pl 2006.225.08:27:25.34&stopcheck/" sy=killall chmem.sh 2006.225.08:27:25.42:source=idle 2006.225.08:27:26.14#flagr#flagr/antenna,new-source 2006.225.08:27:26.14:stow 2006.225.08:27:26.15&stow/source=idle 2006.225.08:27:26.15&stow/"this is stow command. 2006.225.08:27:26.15&stow/antenna=m3 2006.225.08:27:30.01:!+10m 2006.225.08:37:30.02:standby 2006.225.08:37:30.02&standby/"this is standby command. 2006.225.08:37:30.02&standby/antenna=m0 2006.225.08:37:31.01:checkk5hdd 2006.225.08:37:31.01&checkk5hdd/chk_hdd=1 2006.225.08:37:31.01&checkk5hdd/chk_hdd=2 2006.225.08:37:31.02&checkk5hdd/chk_hdd=3 2006.225.08:37:31.02&checkk5hdd/chk_hdd=4 2006.225.08:37:33.82/chk_hdd//k5ts1/GSI00275:T225073000a.dat~T225082610a.dat[13033340928Byte] 2006.225.08:37:36.60/chk_hdd//k5ts2/GSI00163:T225073000b.dat~T225082610b.dat[13033340928Byte] 2006.225.08:37:39.38/chk_hdd//k5ts3/GSI00278:T225073000c.dat~T225082610c.dat[13033340928Byte] 2006.225.08:37:42.17/chk_hdd//k5ts4/GSI00141:T225073000d.dat~T225082610d.dat[13033340928Byte] 2006.225.08:37:42.17:sy=cp /usr2/log/k06225ts.log /usr2/log_backup/ 2006.225.08:37:42.26:*end of schedule